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Document:	MS11-A,B,C Memory Systems Maintenance Manual
Order Number:	EK-MS11A-MM
Revision:	006
Pages:	119
Original Filename:	EK-MS11A-MM-006_MS11-A_B_C_Memory_Systems_Maintenance_Manual_Aug76.pdf

OCR Text

dlilgliltlall

EK-MS11A-MM-006

memory systems

maintenance manual

digital equipment corporation - maynard, massachusetts

1st Edition, February 1976

2nd Printing (Rev), August 1976

The material in this manual is for informational
purposes and is subject to change without notice.
Digital

Equipment

Corporation

assumes

responsibility for any errors which may appear in
;
this manual.
Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

MASSBUS

DECUS

6/78-14

CONTENTS
Page

CHAPTER 1
1.1

1.2
1.3

14
1.5

1.5.1

1.5.2

1.53

1.54
1.5.5

1.5.6
1.6

SYSTEM DESCRIPTION

INTRODUCTION . . . i i o e e e e e e e et e et e e e ot e s o e e e e
M8111 BIPOLAR MEMORY MATRIXMODULE . ... ... ... ...
M8121 BIPOLAR MEMORY MATRIXMODULE .. ... ..... .. ...
G401 MOS MEMORY MATRIXMODULE . . . . .. . ¢ o v v v v i ove v oo v
..
M8110 AND M8121 SEMICONDUCTOR MEMORY CONTROL MODULES . .. ...
e
e
e
oo
.
.«
.
.
.
.
Memory Address Multiplexing
e
Write and Read Data Registers . . . . . . . o v oot v v v i v i i i
e
t
Timingand Control . . . . . . . oo

RefreSh LOGIC

1-1
1-2
1-2
1-2
1-3
1-3
14
14

- ¢ -« v v v v o e e e e e et 1-4

e 14
Parity CONtrol . . . ¢ v v i e i e e e
e
Diagnostic LOgic . . .« c v v o i 1-5
SYSTEM SPECIFICATIONS . . & ¢t o e e e vt e e e e e e e e e e e e e et e s 1-5

1.7

SEMICONDUCTOR MEMORY SYSTEM CONFIGURATIONS . . .. ... ... ..... 1-6

CHAPTER 2

MEMORY SYSTEM INTERFACE OPERATIONS

2.1

2.2
2.2.1
2.2.2
223

224

2.3
2.3.1
232

INTRODUCTION . . o o i et e e e e ettt e e e et e i e e e e e e e e e e e
BASIC MEMORY ACCESS OPERATIONS . . . . . . . v v vt vom oo oo oee v
Data In(DATDI CYCle .+« v v v v v e e oo e e oo e e oo e
Data In, Pause (DATIP) Cycle . . . . o v v v v i v oo
Data Out (DATO) Operation . . . . v« o v v v v v oo v o i e oo oo ie e e e

2-1
2-2
2-2
2-2
2-2

Data Out, Byte (DATOB) Cycle . . . . . . .o v vt im oo oniee e e 2-4

FASTBUSINTERFACE . . . o i it i e e et et et e e e et ea st e e e s 24
e e s 24
Fastbus DATOCYCle . . . . v v v v v it oottt e e e
Fastbus DATICycle . . . . o v o v v ottt et e 2-7
UNIBUSINTERFACE . . . o i i i it e e it e e et e e et e e e e e e oo e e 2-7

2.6.5

Unibus DATOCycle . . . o v o it ittt e e e 2-8
Unibus DATICycle . . .« v v vt it ettt e e e 2-8
e e e e e 2-8
MEMORY BUS . . o o e i e i e et e e e e e e et e e e e
v vv oo oo e 2-8
oo
..
.
SEMICONDUCTOR MEMORY ADDRESSING . . . ..
Address Decoding at the M8110/M8120 Control . . . . . . . . o v v v v e vl b 2-10
Address Mapping at the M8110/M8120 Control . . . . .« . .« v v v v v v v e e 2-11
4K Bipolar Memory Matrix Module Address Decoding . . . . . . o .o oo v v 2-12
1K Bipolar Memory Matrix Module Address Decoding . . . . . .. ...« oo v e 2-13
4K MOS Memory Matrix Module Address Decoding . . . . . . . .. oo 0o oo oo 2-14

CHAPTER 3

LOGIC DESCRIPTION

24.1
242
2.5

2.6

26.1
2.6.2
263
2.64

3.1
3.2

3.2.1
3.2.2

323

3.2.3.1
3.23.2

INTRODUCTION . . ot o o v i e e e e e e e oo e e e e s o s oo st aa e s e e e e
M8110/M8120 SEMICONDUCTOR MEMORY CONTROL MODULE . . .. ... ....
e
Memory Selection Logic . . . . . v . oo h e
t
i
vt
ot
vt
v
o
o
.«
.
.
.
Unibus Interface SMCH)
e
Address Multiplexing (SMCC) . . . . . . o vt i vt i

3-1
3-1
3-1
3-6
3-8

Unibus Address Multiplexing . . . . . .« ¢ o v oo oo oo 39
Fastbus Address Multiplexing . . . . . . . . ¢ o v v oot v e 39

CONTENTS (Cont)

3233

324

Refresh Address Multiplexing

Data Multiplexing (SMCD)

. . . . . ... ... ... ............

. . . . . . . . . ...

3.25

Data Output (SMCE)

3.2.6

M8110/M8120 Control Logic

3.2.7

Parity Logic

. . . . . . . . . . .

. . . . . . . . v v v v e e e e e e e

. . . . . . . . e
e
e

3.2.7.1

Parity Register Address Decoding

3272

Parity Register Address Set-up

. . . . .. ... ... ... .........

. . . . . ... ... . . ... .. . ... ...,

3.2.7.3

Parity Register

32.74

Parity Generator

. . . . . . . . . . ...

Parity Checking

. . . . . . . . . . . . . e

3.2.75
3.2.8

Refresh Logic

. . . . . . . . .. ... . .

. . . .. .. . .

3.2.8.1

Normal RefreshCycle

3282

Refresh Cycle Intervention During Single-StepMode

3.28.3

3.3.1

. . ... .. ... ... . ... . ... . ... 0....

Refresh Cycle During Power-Down Periods

3.3.1.1

AddressBuffer

Data Buffering and Write Pulse Fanout Logic

33.13

Address Examination Logic

3.3.2

34.1

Bipolar MatriX

. . ... ... ... . ... . . ..

. . . . . v o

e e e e

e e

M8111 BIPOLAR MEMORY MATRIXMODULELOGIC
Memory Matrix Control

. . . . . . . . . . ..

34.12

Data Inversion and Write Pulse Fanout Logic

3.5

. . ... ... ... . . ...

Address Examination Logic
Bipolar Matrix

. .. ... ... .........

. . . ... ... ... ...

... . .. .. ...

. . . . . . . . . .

G401 MOS MEMORY MATRIXMODULELOGIC

... ......
... ... .....

3.5.1

MOS Memory Writing

. . . . . . . . . ..

3.5.2

MOS Memory Reading

. . . . . . . .. ... ...

CHAPTER 4

... ... ............

. e

AddressBuffer

34.13

. . ................

. . . ... ... ... ....... ... .....

34.1.1

34.2

... ... ............

. . . . . . . . . . . . . . e

33.1.2

. . . . ... ... .. ..

. . . ... ... ..........

M8121 BIPOLAR MEMORY MATRIXMODULELOGIC
Memory Matrix Control

i it

CALIBRATION AND MAINTENANCE

4.1
4.2

4.2.1

Memory Cycling Program

. . . . . . . . . . 0 i i i

422

Test Equipment Required

. . . ... .. ... .. ... .. ... ... .. .....

423
4.3

4.3.1
4.3.1.1
43.2

43.2.1

43.3

Calibration Setup

. . . . . . . . .

MEMORY SYSTEM CALIBRATION

e e

. . . .. .. . .

MOS Memory System Calibration

e e

e e e e

ie e it

. . . ... ... ... ... ... ... ....

Address Set Up, Precharge, CENABLE, and Access Ready Timing Adjustments
Bipolar Memory System Calibration

. .. ... ... ... ... .. .. .......

Address Set Up, Precharge, and Access Ready Timing Adjustments
Cycle Time Adjustment

. . . . . ..

. . . . . . . . . .. . .ttt ittt e

4.4

SEMICONDUCTOR MEMORY SYSTEM DIAGNOSTICS

4.5

MEMORY MATRIXMODULESTRUCTURE

4.5.1

. . . . ... ... ........

. ... ....................

CONTENTS (Cont)
Page

APPENDIX A

SEMICONDUCTOR MEMORIES

A4.

INTRODUCTION . . . . ottt e e e e e e e e e e e e e e e e e A-1
oo e e e e e e e A-1
it et
. . . . . . . i
BIPOLARMEMORIES
e e e e e A-8
e e e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
ittt
. . .
MOS DEVICES
MOS MEMORIES . . . . . it i e e e e e e e e e e e e e e e e e A-10
et s e e e e e e A-14
Refresh ACtION . . . . vt v v i i e e e e e e e e e e

APPENDIX B

INTEGRATED CIRCUIT DESCRIPTIONS

A.l

ILLUSTRATIONS
Figure No.
1-1
1-2
2-1

2-2

2-3
24
2-5

2-6
2-7

2-8
29

2-10
3-1
3-2
3-3
34

3-5

3-6
3-7

3-8
39
3-10

3-11
3-12

3-13
3-14

3-15

3-16
3-17

3-18

Title

Page

MS11 Semiconductor Memory System, Block Diagram . . . ... ... .......... 1-1
MS11 Semiconductor Memory Control Module, Block Diagram . . . .. ... ... .... 1-3
Semiconductor Memory Configuration within PDP-11/45 Systems . . . . . ... ... .. 2-1
. .. .. ... ... ... 000 2-3
Semiconductor Memory System Interfaces
e e e e e e e e e e e e e e e e e e 2-6
e
e
i
i
i
i
o
o
.
.
.
.
.
.
.
Fastbus Interface
e e e e e e e e e e e e e e e e e 29
e
e
e
e
e
e
e
Unibus Interface . . . . v v v v e e e
Semiconductor Memory Bus, Simplified Block Diagram . . . . .. ... ... ....... 2-10
000 2-11
Semiconductor Memory Address Examination . .. .. ... ... ... ...
2-11
oL
e
...
.
..
.
.
.
.
.
Mapping
Address
Memory
Semiconductor
2-12
....
..........
...
...
.
.
.
(M8121)
Addressing
4K Bipolar Memory Matrix
2-13
.....
...
...
...
..
..
.
.
.
.
1)
1K Bipolar Memory Matrix Addressing(M811
2-14
..........
4K MOS Memory Matrix Address Examination (G401) . . . ... ...
M8110/M8120 Semiconductor Memory Control Block Diagram . . . ... ... ...... 3-2
. . . . . . ... ... ... ... ... 3-5
Simplified Memory Address Decode (SMCF)
Jumpers . . . . ... ... ... ... 3-6
E67
Required
(14:11)
Fastbus Address Multiplexing
oo il a e 3-7
Address Decoding (DrawingSMCF) . . . . .. ... ...
Unibus Address Multiplexing (14:11) Required E78 Jumpers . . . . . ... ... ... .. 3-7
e 3-12
Unibus DATO Logic Flow . . . . . . .o o i it
3-15
e
t
iiiii
tt
.o
..
.
.
.
.
.
.
.
Flow
Fastbus DATOLogic

e e 3-18
Unibus DATI Logic Flow . . . . . . . . oo it i it i i
e 3-19
Fastbus DATI Logic Flow . . . . . . . . i ittt ittt
oo 3-20
Fastbus DATI-DATO Logic Flow . . . . . . . . . oot v it i
3-24
i
oottt
v
oo
.
.
.
.
.
.
.
.
(Bipolar)
Unibus DATO Timing
3-25
.
..
..
.
Fastbus DATO Timing (Bipolar) . . . . . ..
326
e i
Unibus DATI Timing (Bipolar) . . . . . . .« o ot it it
oo v ittt 327
Fastbus DATI Timing (Bipolar) . . . . . . . .. .
Fastbus DATIP-DATO Timing (Bipolar) . . . .. . .. . ... o 3-28
e 3-29
et et
Fastbus DATO Timing (MOS) . . . . . . . o o ot i
Parity Logic, Block Diagram . . . . . .. ... ... oo i 3-31
oo 3-36
Normal MOS Refresh Cycle Timing . . . . . . . . . ... .o v v

ILLUSTRATIONS (Cont)

Figure No.

Title

3-19

M8121 4K Bipolar Memory Matrix, Block Diagram

. . . . ... ... ... ........

3-20

M8111 1K Bipolar Memory Matrix, Block Diagram

. . . . ... .. .. ..........

321

G401 4K MOS Memory Matrix, Block Diagram

4-1

M8110 Timing and Termination Delay Adjustment for MOS Memory

(Logic Drawing SMCA)
4-2

. . . . . . . . .

. . . . . ... ... ... .........

M8120 Timing and Termination Delay Adjustment for Bipolar Memory

(Logic Drawing SMCA)

. . . . . . . . . .

4.3

G401-Y
A MOS Memory Matrix Module — Relationship of ICs toBits

. . . ... ... ...

M8111 Bipolar Memory Matrix Module — Relationship of ICsto Bits

. . . . .. ... ...

4.5

M8121-YA Bipolar Memory Matrix Module — Relationship of ICs to Bits

Bipolar Memory Cells

16-Word by 4-Bit Memory

A-3

1 Outof 16 Address Decoder

16-Bit Memory Element (16-Wordsby 4-Bits)

Structure of MOS Devices

MOS Memory Circuits

Dynamic MOS RAM Circuits

. . . . ... ...

. . . . . . . . . .

. . . . . . . . ...
. . . . . . . .. .. ... .. ...
. . . . .. ... ... .. ... .......

. . . . . o . v v it

. . . . . . . .

e e

. . . . . . . . v v i v it e e e e e e e e e e e

TABLES
Table No.

Title

I-1

M8121 (4K) Bipolar Memory System Configuration

. . . ... ... ... .........

1-2

M8111 (1K) Bipolar Memory System Configuration

. . ... ... ... ... .......

1-3

G401 (4K) MOS Memory System Configuration

2-1

Fastbus-M8110/M8120 Interface and Control Signals

2-2

Fastbus and Unibus Control Bit States

. . . .. . ... ... ... ........
. . . . ... .. ...........

. . . . . . . .. ... ... ... ... ... ....

2-3

Unibus/M8110 Interface Information and Control Signals

3-1

Fastbus/Unibus Memory Address (Assign and Decode)

. . . . ... ...........

3-2

MOS/Bipolar Module Addressing

3-3

MOS/Bipolar Memory Addressing

Multiplexed Address Inputsto MAD(SMCC)

3-5

MOS and Bipolar Memory Timing (M8110/M8120)

3-6

Parity Register, Assigned Addresses

3-7

Parity Register Flip-Flops, Bit Identity and Function

3-8

Expanded M8121 Memory Address Allocation

. . . ... ... ... ... ........
. . . . .. ... ... ... ... ......

. . .. ... ... .. .. .....

. . . . . . . . v it
. . . . . . . . it i

e e e e e

. . . . . . . . . . .. . .

...

. . . .. . ... ... . .. ... ...

. . . . . . ... ... ... ... ...
.. ... .. ... ..........

Address Bit to MAD Bit Translation (M8121)

3-10

M8121 Bipolar Matrix Selected Address Configuration (1 of 16K)

3-11

Expanded M8111 Memory Address Allocation

. . .. .. .................

. . . . ... ... ... .. .........

3-12

Address Bit to MAD Bit Translation (M8111)

3-13

M8111 Bipolar Matrix Selected Address Configuration (1of 16K)

3-14

Address Decoding for Memory Circuit Enabling

. .. ... ... . ...

. ... ... ... ...

. . . ... ... ... ...........

3-15

MOS Matrix Selected Address Configuration (4 of 16K)

3-16

MOS Matrix Control Level Generation and Selected Memory Address Block (1 of 4K)

4-1

Semiconductor Memory Adjustments

. . . . ... . ... ... .....

. . . . ... ... ... ...

INTRODUCTION

This manual describes the MS11 options that constitute the PDP-11/45, 11/50 and 11 /55 Semiconductor Memory
System. Its primary purpose is to provide information for DIGITAL Field Service representatives and customer
personnel, with similar PDP-11/45 training, to perform on-site maintenance of the MS11 options. The information is
presented in four chapters.

Chapter 1 describes the MS11 Semiconductor Memory System structure and provides module specifications and
system configuration information.

Chapter 2 describes semiconductor memory system access operations, interfacing and addressing.
Chapter 3 provides a detailed analysis of semiconductor memory logic operation.

Chapter 4 presents the procedures required for semiconductor memory calibration and maintenance.

All descriptions assume that the reader is familiar with basic digital computer theory and the operating
characteristics of bipolar and metal-oxide semiconductor (MOS) digital integrated circuits. Because of the many

recent advances in MOS technology concerning memory system applications, Appendix A contains a description of

MOS and bipolar memory circuit theory.

Data, address, and control signals relevant to semiconductor memory operation are transmitted on the Unibus or the
Central Processor Unit (CPU) Fastbus. This manual references the data, address, and control lines that interface the
semiconductor memory system with other PDP-11/45 units according to the conventions established for Unibus and
PDP-11/45 signals mnemonics. For example, SAPJ PA (17:06)H refers to the 12 physical-address (PA) inputs, named
PA17 through PA0Q6, which are generated as shown on drawing SAPJ. The prefix SAPJ indicates sheet J of the SAP
module schematic. Complete details on data, address, and control signal origin and derivation are provided in the
following related manuals:

PDP-11/45 and PDP-11/50 System Maintenance Manual, EK-11045-MM-005
KB11-A Central Processor Unit Maintenance Manual, EK-KB11A-TM-001

KB11-D Central Processor Unit Maintenance Manual, EK-KB11D-TM-001
KT11-C Memory Management Option Manual, EK-KY11C-MM-003

KT11-CD Memory Management Option Manual, EK-KY11CD-MM-003

CHAPTER 1

SYSTEM DESCRIPTION

1.1 INTRODUCTION

Digjtal Equipment Corporation’s MS11 Semiconductor Memory Systems for the PDP-11/45, 11/50 or 11/55 Systeme
metal-oxid
are high-speed random access memories available in two basic solid-state types: bipolar (TTL) and specific
MSI
the
in
made
is
systems
semiconductor (MOS). The distinction between bipolar and MOS memory
control
M8110
the
uses
MS11
the
of
components used to form the memory storage matrices. The MOS version
4096-word
module and the bipolar version of the MS11 uses an M8120 control module. The M8110 can controld four
Bipolar
M8111
1024-wor
four
either
G401 MOS Memory Matrix modules (Figure 1-1). The M8120 can control
bipolar
and
MOS
the
Both
modules.
Memory Matrix modules or four 4096-word M8121 Bipolar Memory Matrix
without
or
with
available
are
modules
systems provide storage for up to 16,384 16-bit words; both types of memory
byte parity.

DIRECT ACCESS

DEVICES

CPU

UNIBUS B

FAST BUS

d L
SEMICONDUCTOR

SEMICONBUCTOR

MEMORY CONTROL

MEMORY CONTROL
M8110/M8120

M8110/M8120

MEMORY

MATR X

MEMORY

MODULE

MEMORY

MATA X

MODULE

|X
MATR

MATRIX
MODULE

MATR X
MODULE

MATRIX

MEMORY

X
MATR
MODULE

MATRIX
MODULE

11-1318

Figure 1-1 MS11 Semiconductor Memory System, Block Diagram
1-1

The bipolar and MOS semiconductor memories can be jointly or separately operated from either the KB11 Fastbus
or the PDP-11 Unibus, or from both, depending on the specific system configuration. When operated from the
Unibus, each semiconductor memory system functions as a PDP-11 compatible peripheral and can serve as the basic
memory in a large-scale system. Operation under joint control of the Fastbus and Unibus provides direct high-speed
memory access through the Fastbus for the KB11 Processor, while maintaining the processor/peripheral relationships

characteristic of the

Unibus. Whether

operating jointly -or separately with the Unibus and/or Fastbus, a

semiconductor memory always assumes the role of a “slave’ device to the processor. Under Unibus control, the

memory also is “‘slave” to any peripheral (direct access) device currently designated ‘“master”.
Because readout from semiconductor memories is non-destructive, the write-after-read-cycle time associated with
ferrite-core memories is eliminated. In addition, the switching speed for semiconductor memories is characteristically
much faster than that for the ferrite-core memory. The extremely high switching speeds characteristic of bipolar
memory cells permit typical memory cycle times of 300 ns for an operating bipolar memory system. MOS
semiconductor memory systems have slower typical cycle times of 495 ns.

1.2 M8111 BIPOLAR MEMORY MATRIX MODULE
The M8111 Bipolar Memory Matrix module is an 8-1/2 in. X 15 in. (21.59 cm X 38.1 cm) multilayer glass hex
board, configured to store or not store byte parity. The M8111-YA parity-equipped modules contain seventy-two
256 X 1-bit TTL MSI memory circuits, interconnected to form a 1024 X 18-bit memory matrix. Each 18-bit word in
this matrix is formed by two 8-bit bytes and two parity bits, one per byte. This module also contains appropriate

address decoding and driving logic, 18 write-data inversion stages, and control-signal decoding logic. All decoding
inversion and driving logic is formed by TTL integrated circuits. Address lines 14:13,11:10 at each M8111 matrix
module are jumper-connected so that in a given bipolar memory system each matrix module can be configured to

decode a unique address. The M8111 Bipolar Memory Matrix module is identical to the M8111-YA in all respects,
except that the M8111 contains sixty-four 256 X 1-bit MSI memory circuits interconnected to form a 1024 X 16-bit

memory matrix without byte parity.
1.3 M8121 BIPOLAR MEMORY MATRIX MODULE

The M8121-YA Bipolar Memory Matrix module is similar to the M8111 module just described. It is an 8-1/2 in. X
15in. (21.59 cm X 38.1 cm) multilayer glass hex board, configured to store or not store byte parity. The M8121-YA
parity-equipped modules contain seventy-two 1024 X 1-bit TTL MSI memory circuits interconnected to form a
4096 X 18-bit memory matrix. Each 18-bit word in this matrix is formed by two 8-bit bytes and two parity bits, one
per byte. This module also contains appropriate address decoding and driving logic, 18 write-data buffering stages,

and control-signal decoding logic. All decoding inversion and driving logic is formed by TTL integrated circuits.
Address lines 14:13, 11:10 are decoded at this module to select the specific module and the group of 1024 words
addressed within the selected module. Address bits MAD (14:13) are switch connected so that each 4096-word
matrix can be selected for a unique address assignment.

Only the M8121-YA version is available; a version without byte parity is not manufactured.

1.4 G401 MOS MEMORY MATRIX MODULE

The G401 MOS Memory Matrix module is an 8-1/2 in. X 15 in. (21.59 cm X 38.1 ¢cm) double-sided, multilayer glass
hex circuit board, also configured to store or not store byte parity. The G401-YA parity equipped module contains

seventy-two 1024 X 1-bit MOS MSI circuits interconnected to form a 4096 X 18-bit memory. The 18-bit word
configuration is exactly the same as the bipolar matrix, i.e., two 8-bit bytes and two parity bits, one per byte. This

module also contains appropriate logic to level-shift addresses, data, and control signals from TTL to MOS and MOS
to TTL voltage levels; and 16 or 18 integrated-circuit sense amplifiers, depending on whether parity is specified, one

for each of the read-sense lines. The states of memory address (MAD) register bits (02:01) and (14:31) are decoded at
this module to select the specific module and the group of 1024 words addressed within the selected module.
Address bits MAD (14:13) are jumper-connected so that each 4096-word matrix can be selected and wired for a
unique address assignment. The G401 MOS Memory Matrix module is identical in all respects to the G401-YA,

1-2

except that the G401 contains sixty-four 1024 X 1-bit MSI memory circuits interconnected to form a 4096 X 16-bit
memory matrix without byte parity.

Operation of the MOS memory matrix is substantially different from the bipolar matrix in two respects. First,
because of the nature of the dynamic MOS storage cell (Appendix A), each memory access must include a time
interval for precharging the addressed cells prior to the actual access. Second, all memory locations in a MOS system
must be periodically refreshed, usually every 1 ms, to assure data validity during any extended standby intervals.
1.5 M8110 AND M8120 SEMICONDUCTOR MEMORY CONTROL MODULES

The M8110 and M812@ Semiconductor Memory Control modules are fully integrated two-part memory controllers.
The M8110 control is capable of controlling four G401 MOS Memory Matrix modules; the M8120 can control either
four M8111 or four M8121 Bipolar Memory Matrix modules. (The controls are similar in most respects and will be
described together in the following paragraphs. They will be referred to as the M81 10/M8120 memory controls.)
The M8110/M8120 controls multiplex memory access addresses and associated data between the Fastbus and a
Unibus, and direct the logic and timing sequences necessary for the storage or retrieval of each data word or byte
associated with a given access cycle. A simplified block diagram of the M8110/M8120 is shown in Figure 1-2.

=
o
I;B”O/MBIZO MEMORY CONTROL
(MOSREFRESH
MEMORYLOGIC
ONLY)

TIMING
AND
CONTROL

DIAGNOSTIC LOGIC

DATA

PARITY CONTROL

REGISTERS

MEMORY (#4)
M(}Efi‘;fggflg

—|

|
|
|

A \)
MOS OR BIPOLAR
MEMORY

MATRIX

BOARDS

n-1317

Figure 1-2 MS11 Semiconductor Memory Control Module, Block Diagram
1.5.1 Memory Address Multiplexing

The memory address multiplexing function involves two sequential actions under direct control of the
M8110/M8120 timing and control logic. First, based on priority, arbitration of memory access requests performed
by the timing and control logic, Fastbus, Unibus, or refresh addresses (for M8110 MOS memory systems only) are
multiplexed into the memory address (MAD) register. Second, through a parallel bit-to-bit connection scheme,
Fastbus or Unibus addresses are mapped into the MAD register. Once mapped into the MAD register, an address is
strobed into the associated bipolar or MOS memory matrix module selected by that address through action of the

M8110/M8120 timing and control function.

1-3

1.5.2 Write and Read Data Registers
The M8110/M8120 contains two data registers: the write-data (Data In) Register, and the read-data (Data Out)
Register. The Data In Register multiplexes a 16-bit data word (or two 8-bit data bytes), from either the Fastbus or
Unibus, and stores that data until strobed into the associated bipolar or MOS memory matrix module by the

M8110/M8120. The 18-bit Data In Register stores parity for the lower and upper data bytes in the most significant
Data In Register stages. These parity bits are generated as part of word or byte storage in the Data In Register. Data
from the Unibus is received at the M8110/M8120 Unibus interface for storage in the Data In Register. Fastbus data
to be written is received directly at the Data In Register because of the proximity of the M81106/M8120 to the KB11

Processor. At the appropriate time, the data accompanying a Data In cycle is strobed into the memory location
designated by the associated address.

The M8110/M8120 Data Out Register receives and stores data from the location addressed in the memory matrix as
a direct result of a Unibus or Fastbus DATI cycle. At the end of a DATI cycle, data is strobed jointly onto the
M8110/M8120 Unibus interface, and to the Fastbus for retrieval by the requesting bus. Fastbus data lines are
unidirectional; Unibus data lines are bidirectional.

1.5.3 Timing and Control
The M8110/M8120 timing and control interprets control signals from the Fastbus or Unibus and derives the internal

multiplexing priorities, timing, and the nature of the operation to be subsequently performed (DATO or DATI). In
addition, specific portions of the address contained in the MAD register are decoded by the selection logic to
identify the physical memory selected, the memory section to be addressed (one out of four 1024-word sections or

one out of four 4096-word sections), the required byte configuration, and to determine if data words are to be
interleaved. If the operation to be performed is a DATO, the timing and control logic develops the strobe levels
necessary to load multiplex addresses and data, according to the priority of the request, into pertinent registers. The
timing and control logic also enables the designated memory section for writing and performs the DATO operation.
Because readout from semiconductor memories is non-destructive, the timing and control logic strobes the addressed
data onto the output lines which connect to both buses. In this case, the bus that initiated the read operation
receives the data at the bus input as the data requested.

1.5.4 Refresh Logic

The nature of the dynamic MOS MSI circuits forming the G401 MOS Memory Matrix module requires that each
storage cell, which is the circuit equivalent of a capacitive node, be periodically charged above the threshold of the
data stored. Refreshing the data contained in each integrated-circuit memory requires that all states of the row
address for that circuit be cycled each 1 ms. The M8110 refresh logic performs this function automatically by
generating 32 sequential row addresses during each 1 ms period. These sequential addresses are then input to the

address multiplexer. Coincident control levels from the refresh logic serve to enable the address priority portion of
the timing and control logic to permit input of refresh addresses at the assigned priority level.

Each DATO or DATI operation (with the exception of the write portion of a write-after-read operation) also
includes the precharging or refreshing of each address written into or read. When the M8110 is used with bipolar
memory matrix modules, this refresh logic is inhibited and the precharge interval is ignored. The M8120 also
contains refresh logic. It is always inhibited because the M8120 is used only to control bipolar modules.
1.5.5 Parity Control
Data to be written is transferred to the M8110/M8120 over 16 data lines. If the operation is a DATO cycle, parity is
generated and stored in bit 16 for the low-order byte and in bit 17 for the high order byte. If the operation is a

DATOB, parity is generated only for the byte written and stored in the corresponding parity.
During Fastbus DATI operations, parity is checked after each

16 bits of data read are transferred to the

M8110/M8120 Data Out Register. If a parity error is detected, the Fastbus is notified. (Parity error checking is
inhibited on Unibus DATI cycles.)
1-4

1.5.6 Diagnostic Logic

M8110/M8120 memory control diagnostic logic allows you to write data from the Unibus with parity selected as
odd or even at any memory address, and to check the parity of data read from memory. Normal parity is even; odd
parity generates a read parity error as a reliability check of the diagnostic logic. Each M8110/M8120 module
contains a three flip-flop parity register that controls the parity function within that memory control module. A

unique address, determined by the first memory address under the control of the M8110/M8120, is assigned as the
parity register address and is decoded within the diagnostic logic; each M8110/M8120 has an addressable parity
register that can be read or written to. These operations are conducted when a Unibus DATI or DATO is addressed
to the parity register. Parity error indication, when enabled, is transmitted directly to the processor via the Fastbus.
1.6 SYSTEM SPECIFICATIONS
M8110/M8120
Semiconductor

M8111
Bipolar Memory

M8121-YA
Bipolar Memory

G401
MOS Memory

1K Matrix Module

4K Matrix Module

N/A

1024 18-bit words

4096 18-bit words

N/A
N/A

N/A
200 ns (max)

A
N/A
200 ns (max)

N/A
410 ns (max)

N/A

330 ns (max)

300 ns (typical)

495 ns (typical)

+5V,-15V

+5V

5V
+23.7V
+0.7V
+19.7V

+5%

Active
Inactive

19.65W
19.65 W

S55W
55W

60 W
60 W

39.35 W
16.01'W

Maximum ac power

MS11-CC:

110 W, 376 Btu/hr

MS11-AP:

MS11-BM, BT

50° to 104°F
(10°t 0 40°C)

50° to 104°F
(10° to 40°C)

10% to 90%

Characteristics

Storage capacity
Access time:

DATO cycle
DATI cycle

Cycle time:
Operating voltages:

VCC
VBB
VvDD
VSS

Over-voltage regulation

Memory Control Module

190 ns (typical)

300 ns (typical)

190 ns (typical)

395 ns (typical)

510 ns (max)

Maximum dc power

consumption:’

Environmental conditions:
Temperature
Humidity
Mechanical parameters:

15 in. (38.1 cm)

1/2 in. (1.27 cm)

8.5in (21.59 cm)
1/2 in. (1.27 cm)

Fiberglass/

multilayer

CPU (internal) fan

Dedicated plug-in

slot in CPU

15 in. (38.1 cm)
8.5in. (21.59 cm)

Depth

Height

Construction

Cooling
Mounting

15 in. (38.1 cm)

15 in. (38.1 cm)
8.5 in. (21.59 cm)
1/2in. (1.27 c¢cm)

Width

!Maximum power per module of each type.

2Includes regulator efficiency and total power consumed with this option.
1-5

8.5in. (2159 cm)
1/2in. (1.27 ¢cm)

1.7 SEMICONDUCTOR MEMORY SYSTEM CONFIGURATIONS
Tables 1-1, 1-2, and 1-3 list the number of options that are required as a result of a selected memory type (MOS or

Bipolar) and size. The module complement that comprises the corresponding option is also shown. If, for example, a
24K capacity bipolar memory is desired, the required configuration will consist of two MS11-CC options (each

consisting of one M8120 module and two H744 modules) and six MS11-AP options (M8121-YA modules). The
second M8120 control (MS11-CC option) is necessary for the 8K of memory in excess of 16K controlled by the first
M8120.

Table 1-1
M8121 (4K) Bipolar Memory System Configuration
Option Type Number

Installed

Memory
Capacity

(with Parity)

MSII-CC

MSIL-AP

- Module Complement

(1) M8120

(2) H744

(1) M8121-YA

12K

16K

20K

24K

28K

32K

Table 1-2
M8111 (1K) Bipolar Memory System Configuration
Installed

Option Type Number

Memory
Capacity
With

Parity

MS11-CC
Without

(1)M8120*

Parity

(2)H744A

msiem
|
Module Complement

MS11-CP

(H)M8111

()M8111-YA

3
3

2
5K

4
-

5
5

*Early revisions use the M8110. 4K bipolar modules (Table 1-1) must use the M8120.

1-6

Table 1-3

G401(4K) MOS Memory System Configuration

Installed

MS11-BC

Memory
Capacity
,

With
4K

12K
16K
20K

24K
28K
32K

Option Type Number

MS11.BD

MSII-BR,BM* | MS11-BT, BP*

Module Complement
,

Without

(1)M8110

(1)H746A

(1)M8110

(1)G401

1
4K

12K

16K

20K

24K

28K

32K

(1)G401-YA

*High performance versions of the BR and BT options (available on special order).

3
4
5

6
7
8

CHAPTER 2
MEMORY SYSTEM
INTERFACE OPERATIONS
2.1 INTRODUCTION

A PDP-11/45 System can be equipped with one or two M8110 or M8120 Semiconductor Memory Control modules.
Each M8110/M8120 module, in turn, can exercise control of up to four M8111 or M8121 Bipolar Memory Matrix
modules, or up to four G401 MOS Memory Matrix modules. Since the memory capacity of these three matrix

module types is different (the M8111 provides 1K and the G401 and M8121 provide 4K of memory) the total
memory capacity available to the user is determined by the selected configuration. A typical two-M8110 module
arrangement can consist of up to 8K of bipolar memory in 1K increments (32K in 4K increments) or up to 32K of
MOS memory in 4K increments. The two-controller configuration might also have one of the controllers directing
bipolar matrices while the other is connected to MOS matrices. However, memory matrices of different types cannot

be connected to the same M8110 control. As indicated in Tables 1-1/1-2, and 1-3 the memory capacity determines

the number of M8110/M8120 modules required (the maximum configuration is 16K of MOS or Bipolar memory per
module). Figure 2-1 illustrates the memory system, bus, and processor relationship. Within a PDP-11/45 computer
system, the CPU communicates with associated semiconductor memory controls through an extremely high-speed
information path which is internal to the CPU and under control of the CPU Fastbus. One Unibus in the system,

normally Unibus A, also communicates with the two M8110/M8120 controls.

e
|

PDP-11/45

CONNECTED)

I
|

|
|

Tmmmmmmmmm

|
| |
| |
| I
l
|
| |

4K OR 16K
BI-POLAR
OR
16K
MOS

4K OR16K
Bi-POLAR
OR
16K
MOS

NORMALLY |

|
|
|

(UNIBUS A
AND UNIBUS

CPU

11-0833

Figure 2-1 Semiconductor Memory Configuration within PDP-11/45 Systems
2-1

Each M8110/8120 control, in turn, communicates with up to four bipolar or four MOS memory matrix modules.
Therefore, an operating M8110/M8120 Semiconductor Memory Control has three active interfaces: the Fastbus
interface, the Unibus interface, and the memory bus. The relationship of a typical PDP-11/45 Semiconductor
Memory System to these interfaces is shown in Figure 2-2. Because the M8110/M8120 control and associated

memory matrix modules are physically located in the PDP-11/45 processor, connection to the Fastbus is by

direct-wiring the control and matrix module connectors to the PDP-11/45 CPU backplane. However, the potentially
remote location of a second Unibus, with respect to the M8110/M8120 control, requires a defined Unibus interface
on the control to drive and receive information and control signals to and from that Unibus. Like the Fastbus

connection, memory bus connection between an M8110/M8120 control and associated M8111 or M8121 bipolar or
G401 MOS memory modules involves physically adjacent connectors, so that control-matrix module information

and signals are direct-wire connected.
Discussion of semiconductor memory system interfaces will involve a description of memory access operation, a

definition of each interface in terms of information and signals exchanged, and an explanation of the conventions
used to address semiconductor memories.

2.2 BASIC MEMORY ACCESS OPERATIONS
MS11 Semiconductor Memory Systems operate in four accessing modes: read, write, optional byte handling, and
pause for a write following a read. These operations are designated as follows:

Read data (DATI)

Read data and pause (DATIP)

Write data (DATO)

Write data bytes (DATOB)

Each of these modes is briefly discussed in the following paragraphs.

2.2.1 Data In (DATI) Cycle
During a DATI cycle,

data in the locations addressed at the memory matrix module is loaded into the

M8110/M8120 output data latch for retrieval by the initiating bus (Unibus or Fastbus). Readout of semiconductor
memories is non-destructive; thus, the restore portion of the conventional core memory read cycle is not required.

2.2.2 Data In, Pause (DATIP) Cycle
The purpose of this reading mode is to hold memory secure after data is read from a set of memory addresses until

that data can be revised and then written again. PDP-11 convention requires that execution of a DATIP be followed

always by the execution of a DATO or DATOB operation, except when parity error is sensed in DATIP. A DATIP is
a duplicate of a DATI operation except for a pause for initiation of the impending DATO or DATOB.

2.2.3 Data Out (DATO) Operation
A DATO, or write operation, causes data outgoing from the Unibus or Fastbus to be written one word at a time (16

bits) at the address order designated. The nature of semiconductor memories is such that locations to be written in
do not require prior clearing. As a consequence,.the writing of data begins immediately after cycle initiation, with no
prior clearing required.

2-2

MB8111 OR M8121
Bi-POLAR
OR
G401
MOS MEMORY
MATRIX
MODULE

M8111 OR MB812t

M8111 OR MB121

M8111 OR M8121

BI-POLAR
OR
G401
MOS MEMORY

B81-POLAR
OR
G401
MOS MEMORY
MATRIX
MODULE

Bi-POLAR

MATR
IX
MODULE

OR
G401
MOS MEMORY
MATRIX
MODULE

{}
M8110/M8120 MEMORY BUS

Y
M8110/M8120TM

FAST BUS INTERFAC§>

SEMICONDUCTOR

K UNIBUS INTERFACE

MEMORY

D <

CONTROL

UNIBUS

| PERIPHERA-L_I|
(DIRECT

ACCESS)
DEVICES

M8110/M8120"
FAST BUS INTERFACE >

SEMICONDUCTOR

I UNIBUS INTERFACE

MEMORY

CONTROL

{}
M8110/M8120 MEMORY BUS

mM8111
B1-POLAR
OR
G401
MOS MEMORY

L ARR
B1—-POLAR
OR
G401
MOS MEMORY

mMa111
B81-POLAR
OR

MATRIX
MODULE

MATRIX

MOS

G401
MEMORY

MATRIX
MODULE

MODULE

M8 111
BI-POLAR
OR
G401
MOS MEMORY
MATRIX
MOOULE

3% A SINGLE M8110/M8120 CAN DIRECT EITHER FOUR G401 MODULES, FOUR M8121 MODULES OR
FOUR M8111 MODULES BUT NOT A MIXTURE OF THE THREE
MODULE TYPES.

11-0826

Figure 2-2 Semiconductor Memory System Interfaces
2-3

2.2.4 Data Out, Byte (DATOB) Cycle
A DATOB cycle is a duplicate of a DATO cycle, except that data is written as 8-bit bytes rather than as a 16-bit

word. Decoding of each address designates whether the corresponding byte transferred from the Unibus or Fastbus is

to be written as a low- or high-order byte in the 16 bits available at each memory location. Therefore, data to be
written in memory as bytes must be received on the data lines corresponding to the byte position designated by the
address.
2.3 FASTBUS INTERFACE
The Fastbus interface provides a high-speed, full-duplexed, dedicated data path between the processor and the

M8110/M8120 Semiconductor Memory Control. The Fastbus address, data, and control lines are defined in Table
2-1.

Table 2-1
Fastbus-M8110/M8120 Interface and Control Signals

Name
Address

Mnemonic
DAPB BAMX (05:00) H
SAPJ PA(17:06) H

Ds:aurwf:g Dgramw?:gon

Function

DAPB
SAPJ

SMCC,
SMCF

Selects memory location

Data In

SMCE MEM D<(15:00) H

SMCE

PDRA

DATI lines from Fastbus

Data Out

PDRB BR({15:00)B L

PDRB

SMCD

DATO lines to Fastbus

Bus Start

TMCE BUST OUT L

TMCE

SMCA

Starts Fastbus-initiated memory

Memory

SMCF MEM L

SMCF

TMCF

Informs Fastbus that address is in semiconductor memory

access cycle

Selected

Control OK

UBCA CONTROL OK H

UBCA

SMCA

Informs control that current access

Memory Sync

| SMCA MEM SYNC (B) L

SMCA

TIGA

Informs Fastbus that current memory

UBCCMEMBUSCOL

UBCC

SMCA

Specifies type of memory access cycle

cycle can be completed

access cycle is being completed

Control

(Table 2-2)

Control

UBCCMEM BUSCI L

UBCC

SMCA

Specifies type of memory access cycle
(Table 2-2)

Bus End

TMCE BEND CLR L

TMCE

SMCA

Clear

Terminates current memory access
cycle at M8110 control if Fastbus
anticipated address is incorrect

Parity Error

SMCB PERF L

SCMB

UBCB

Sets processor parity error flag

UBCD PERF ACKN H

UBCD

SMCB

Acknowledgment by processor of

Flag

Parity Error

Acknowledge

receipt of parity error indication

2.3.1 Fastbus DATO Cycle
Initiation of a semiconductor memory access cycle via the Fastbus occurs when the processor places the desired
memory address on the address lines (Figure 2-3, numbers indicate order of occurrence). Data to be stored at this
address is present on the DATO lines at the same time. The address bits are decoded in the memory selection logic

and the resultant MEM signal to the processor denotes receipt of a valid address. Although the address is transmitted
to both M8110/M8120 controls, only that controller having this address within its assigned range of addresses will
acknowledge with the MEM signal. The response (internal to the processor) to MEM is TMCF FAST L, which

2-4

Table 2-2

Fastbus and Unibus Control Bit States

Input from

Fastbus

Unibus

UBCC MEM

BUSCIL

UBCC MEM

BUSCOL

BUSB C1 L

SMCA

SMCH

MEM CIL

MEM COL

UBC1,H,L

UBCO,H, L

DATI

0
1
1

1
0
1

0
1
1

1
0
1

DATIP
DATO
DATOB

SMCA

Usable
Signal

Usable
Signal
gha

BUSB CO L
SMCH

Access

Cycle
to be

Performed

results in the CPU inhibiting MSYN and clearing BUSY; Unibus memory addressing is inhibited. TMCE BUST OUT
L, also from the processor, asserts PREQ (1) H. This latter signal, together with MEM H, initiates memory timing.
The memory address is now latched into the MAD register and a usable address is presented to the memory module.
Required timing signals are also furnished to the memory logic. MEM BUS CO and C1, received prior to CONTROL
OK, are now decoded to indicate a DATO operation. Table 2-2 lists the four access cycle types that are decoded
from these two control bits. With the subsequent CONTROL OK signal, the processor verifies the current memory
access cycle. Since this is a request from the processor (PREQ), SMCA D, or in early versions ACCESS READY

LATCH H, (a product of the timing operation), together with CONTROL OK, generates MEM SYNC. This latter
signal performs several functions; it is returned to Fastbus to inform the processor that data is to be stored, and with
MEM C1, develops DATA LATCH. The final steps are accomplished with DATA LATCH; the data to be written
(Data Out) is latched into the Data In Register, placed on the bus to the memory module and then stored at the
specified location with the concurrent WRITE PULSE.

NOTE

The KB11 Processor, during execution of a current instruction, attempts to predict the address of the word needed next

for purposes of increased operating efficiency. After each
instruction fetch, the processor initiates another bus cycle to
fetch the word following the current instruction cycle. If the
instruction currently being executed requires data, not from
the next word but from a different address, then the processor
terminates that bus cycle aimed at retrieving the next word.
This terminating process results in the processor issuing TMCE
BEND CLR L to the semiconductor memory control. At the
control that previously acknowledged the address associated
with the discontinued bus cycle by responding with SMCF
MEM L, TMCE BEND CLR L terminates the memory access
cycle initiated by TMCE BUST OUT L.

2-5

DATO
-

paTA ouT — @
6)
@
=

CONTROL Ct

MEM SYNC <

DATA IN

LATCH
DATA(10)

|
(9)

CONTROL OK

MEM SYNC

(5)
PREQ

(B)

>MEMORY
MODULE

CPU<

(4)

BUST OUT

sMca p* (8)

MEM <2

;rsc:LS)

TIMING

ADDRESS

write |

MEMORY | ACCESS READY LATCH

PULSE

MEMORY

SELECTION

LATCH MAD REG

[ TM

_
MAD

DATI
DATA IN -

(11)

(6)
CONTROL C1 —:]

DATA LATCH

DATA QUT
REGISTER

(10)
SA LATCH

MEM SYNC
=

{9)

CPU< CONTROL OK—

NS'B'SE!
(5)

PREQ (B)

susT ouT

TMcE
FAST L

(3]

4
4!

MEM
=

SMCA D*

(2)

(8)

|ACCESS READY LATCH
_ _ |
MEMORY

TIMING

ADDRESS

(1)

MEMORY

SELECTION

LATCH MAD REG
Map

EARLY VERSIONS USED ACCESS

READY LATCH

i
-

TO ASSERT MEM SYNC.

- Figure 2-3 Fastbus Interface

2-6

2.3.2 Fastbus DATI Cycle

If the Fastbus-initiated access cycle is a DATI or DATIP (Figure 2-3), the sequence is essentially the same as when
DATO was executed. When the memory address from the Fastbus is decoded, MEM is returned to the processor. The
BUST OUT signal from the processor that follows asserts PREQ (1) H. This latter signal, together with MEM H,
initiates memory timing, the memory address is placed on the lines to the memory module. After CONTROL OK is

received, the timing sequence continues without further processor interruption. SMCA D, or in early versions
ACCESS READY LATCH, a product of the timing process, generates the MEM SYNC signal. Unlike the DATO
operation, MEM BUS C1 (Table 2-2) is a 0 for DATI and DATA LATCH is inhibited. However, due to the signal
levels used, SA LATCH is set at the termination of the MEM SYNC pulse. The data from the desired address in the
memory matrix is then transmitted as DATA IN, from the Data Out Register via Fastbus to the processor.

Although the M8110/M8120 parity diagnostic register is addressed and loaded through the Unibus interface, the
parity error indicator signal PERF is relayed to the processor through the Fastbus. The processor looks for PERF at
the time it drops CONTROL OK; if set, it responds with PERF ACK.
2.4 UNIBUS INTERFACE

Data transfers through the Unibus between the semiconductor memory system and the processor (or other devices)
are conducted on a master/slave basis with the memory in all circumstances having slave status (refer to the PDP-11
Peripherals Handbook). Unlike the Fastbus interface, data lines between the Unibus and the M8110/M8120 control
are bidirectional. The information and control signals passed between the Unibus and the M8I 10/M8120
Semiconductor Memory Control module are defined in Table 2-3.
Table 2-3

Unibus/M8110 Interface Information and Control Signals

Name

Mnemonic

Source

Function

Destination

Address
Data

BUSB A{17:00) L
BUSBD(15:000 L

BUSB
BUSB

SMCH
SMCH

Master SYNC

BUSB MSYNC L

BUSB

SMCH

Selects memory location
Provides for bidirectional data
transfer between Unibus and
semiconductor memory

Initiates memory access cycle

specified by state of UBCC CO
and C1

Slave SYNC

BUSB SSYNC L

SMCF

BUSB

Acknowledges connection

Specifies type of memory access

Control

BUSB CO L

BUSB

SMCH

Control

BUSBC1 L

BUSB

SMCH

Specifies type of memory access

DC power low | BUSADCLO L

BUSA power

SMCH

Indicates dc voltage out of tolerance

DC power low | BUSBDCLO L

BUSB power

SMCH

Indicates dc voltage out of tolerance

(Bus A)
(Bus B)

control modules
control modules

cycle (Table 2-2)

on bus A
on bus B

At the M8110/M8120, all information and control-signal interchange with the Unibus is routed through the SMCH

logic on the M8110/M8120 control. This logic consists of a drive/receiver interface designed for high-speed
information and control-signal transmission and receipt from remote locations over the Unibus cable module.

2.4.1 Unibus DATO Cycle
A memory access cycle is initiated (Figure 2-4) from the Unibus when the processor or direct access device places
the memory address on the input lines to both M8110/M8120 controls. Only that control where the address falls
within the established address range will have its memory selection logic activated. Control bits CO and C1 are also
present at the control input at this time; they are decoded (Table 2-2) to determine the type of memory access cycle
to be executed. The data to be stored is concurrently available on the DATA lines. Enabling of the address decoding
circuitry occurs with the arrival of MSYNC from the Unibus. The subsequent BREQ initiates the memory timing

sequence. One of the first signals generated, BREQ IN PROG, provides a required condition for DATA LATCH.
Latching of the memory address into the MAD Register occurs next; the memory matrix module is thereby
presented with a usable storage address prior to the data being strobed over the memory bus. Following a delay,
ACCESS READY LATCH simultaneously produces DATA LATCH and MEM SSYNC. The latter signal is returned,
via the Unibus, as BUSB SSYNC, informing the processor that the selected control has accepted and stored the data.

DATA LATCH results in the DATA being gated into the Data In Register and then placed on the bus to the memory
matrix. Concurrent with this, DATA LATCH produces the WRITE PULSE, the function of which is to store the
data at the prescribed memory location. The advent of SSYNC disables MSYNC and the access cycle is complete

with respect to the Unibus and M8110/M8120 interfacing.
2.4.2 Unibus DATI Cycle

A DATI memory access operation (Figure 2-4) is similar to the Unibus DATO procedure just described. The access
cycle is initiated in the M8110/M8120 logic on receipt of the memory address. Control bits CO and C1 are input at
the same time; C1 is a 0. However, unlike DATO, DATA is not sent from the processor in a DATI operation; the
bidirectional data lines will be used to carry the data retrieved from memory back to the processor. MSYNC results in

BREQ, which triggers the timing sequence that follows. BREQ IN PROG fulfills the second requirement for MEM
SSYNC and the memory address is latched into the MAD register. The selected memory address is then delivered to
the memory matrix along with required timing signals. MEM SSYNC is brought up, after a delay, by ACCESS
READY LATCH. MEM SSYN notifies the processor that the timing sequence is completed and that the data
requested is available for acceptance. Although SA LATCH is not set, the read data bypasses the Data Out Register

en route to the Unibus.
2.5 MEMORY BUS
Figure 2-5 is a simplified block diagram of the semiconductor memory bus. This bus is part of the M§110/M8120

Semiconductor Memory Control module and implements the multiplexing of DATO and DATI operations between
the Fastbus, Unibus, and semiconductor memory system storage.

The multiplexing of memory access operations over the memory bus is governed by priority aribitration logic on the

M8110/M8120 control. This logic arbitrates memory access requests only when simultaneous requests are received
from the Unibus and Fastbus. In such arbitration, Unibus memory access cycles have higher priority. In all other

cases, memory is multiplexed between the Fastbus and the Unibus on a “first come, first served” basis. In addition,
any memory access cycle, once started, locks out all other bus requests until completed. The DATI side of the

M8110/M8120 memory bus is coupled to both the Fastbus data-in lines and the Unibus interface so that disposition
of data on this portion of the memory bus is handled by the requesting bus.
2.6 SEMICONDUCTOR MEMORY ADDRESSING

The M8110/M8120 Semiconductor Memory Control module, whether directing bipolar or MOS memories, always
processes an incoming Fastbus or Unibus address in the same manner. This process involves two simultaneous actions

by each M8110/M8120 control: address examination and address mapping. In order to clarify the effects of these
actions, the specific description of each action is preceded by a brief description of the PDP-11 addressing scheme.

2-8

DATO

oatA —V

MEM SSYNC

Buss (7)

ssync TM

DATA IN | (8)

CONTROL (1)
ci

DATA

CPU/DIRECT

MEMORY

(7)

(4)

BREQ

IN PROG

(3)

(2)

MSYNC ——» MEMORY | BREQ
Lo

ApDRESS

SELECTION

ACCESS

%n?:g

READY LATCH

) .

()

LATCH

MAD REG.

WRITE

—

PULSE

(8)

(5)
MAD

L
DATI
f

DaTA <8

)

T
)

DATA OUT
REGISTER

MEM SSYNC (7)

BUSB L

SSYNC

MEMORY

CPU/DIRECT

ACCESS <

DEVICE

conTrOL
ct

)

BREQ IN PROG (4)

msyne L2
ADDRESS

MODULE

,
l

_‘"!

(3)

MEMORY | BREQ .| MEMORY

SELECTION

ACCESS READY LATCH (6)

TIMING

>
LATCH MAD REG (5)
MAD

11-1320

Figure 2-4 Unibus Interface

FASTBUS

DATA
OUT

UNIBUS

DATA
IN

ADDRESS

DATA

ADDRESS

FASTBUS
INTERFACE

MULT!PLEXER

UNIBUS

INTERFACE

MBLTQL&QER

ADDRESS

MAD <14:01>

SMCD

MEM DATA <17:00>

SEMI- CONDUCTOR |
MEMORY MATRIX

(MOS OR BIPOLAR)

SMCC

IN/OUT

MEM SA <17:00>

MEM D <15:00>

DATA
o

SMCE
L

] 4
11-1321

Figure 2-5 Semiconductor Memory Bus, Simplified Block Diagram

In the PDP-11 System, a 16-bit word is addressed by an even binary number. The high-order byte in that word is

addressed by the next higher number in the binary address count, which is an odd number. In this manner, the state
of the least-significant bit in an address (bit 0) determines whether a full word (or low-order byte) or the high-order

byte is being addressed. Consequently, the address for a 16-word (or the low order byte in any word) is always even,
and the address for a high-order byte in any word is always odd.
For example:

Typical address for a full 16-bit word or low-order byte

1733464

Address for the high-order byte in the same word

1733474

2.6.1 Address Decoding at the M8110/M8120 Control
Figure 2-6 shows how each M8110/M8120 control examines Unibus and Fastbus address. At each control, the states
of address bit {17:13) are compared with equivalent jumper-wired states to decode the address. Address bits (17:16)
designate up to 32K of semiconductor memory locations out of a total memory capacity of 128K. Decoding of

address bit 15 designates the specific M8110/M8120 control being addressed. Therefore, that control whose

2-10

18 BIT
FASTBUS OR UNIBUS
ADDRESS

17 |

14 | 13

CEEES GEENES TEEEE AN GEDEND G

el CAERED CGEENED GO S r" B ]

MOS AND/OR BIPOLAR MEMORY
CEEE

I D

G TR GRS

'SYSTEM

16 15 14 13

SEMICONDUCTOR

CONTROL

15 14 13

M8110/M8120

MEMORY

M8110 / M8120

11-0831

Figure 2-6 Semiconductor Memory Address Examination

jumper-wired states of bits (17:15) match the states of address bits (17:15) has the location being addressed within
its total range of memory locations. Decoding address bits (14:13), as compared with jumpered states at each
module, designate that the memory location specified by the address being examined is within one of the 4K-word

pages comprising the semiconductor memory. When all conditions of ‘address decoding, as specified by jumper
connections at either control, are satisfied, then mapping of that address is enabled at the selected controls.
2.6.2 Address Mapping at the M8110/M8120 Control

The manner in which addresses are examined by the M8110/M8120 requires that each incoming Fastbus or Unibus

address must be mapped into MAD register. This mapping action, as illustrated in Figure 2-7, amounts to the shifting
of address bits (12:02) one position to the right, and the routing of address bits 01 and 12 according to specific
jumper configurations. The installation of required address jumpers is described in detail in Paragraph 3.2.1.
BYTE

MAD REGISTER
17

iLOW

0
b

)

, fi

UNIBUS OR FASTBUS ADDRESS
11-0681

Figure 2-7

Semiconductor Memory Address Mapping
2-11

2.6.3 4K Bipolar Memory Matrix Module Address Decoding

In addition to being part of the addressing scheme on the M8110/M8120 control, MAD bits (14:13) are decoded on
each M8121 4K Memory Matrix module attached to the selected M8110/M8120 (Figure 2-8). The states of MAD

(14:13) are compared with a unique switch configuration on each M8121 module. The module with the matching
states is the one to be accessed. This equality at the addressed M8121 module, in turn, enables examination of MAD
(11:10). The states of these two bits are decoded, by a logic network on the M8121, to identify which one of four

1K word rows contains the 16-bit word location to be addressed. Finally, MAD bits (12,09:01)are decoded on the

M8121 to select the particular word within the chosen 1K section.
FASTBUS/UNIBUS ADDRESS

MEMORY

—7

ADDRESS REGISTER

ADDRESS

1 OF 2

|1 OF 4 IK

CONTROL

12
4

'
4K M8121 MEMORY

MATRIX MODULE

4K M8121

MEMORY

MATRIX MODULE

I
N
O

M8120

WORD LOCATIONS

1 OF 1K

|WORD ROWS

BOARDS

CONTROLS

(MAD)

ADDRESS 1 OF

4-4K MATRIX

|
|

l
|

4K M8121 MEMORY

MATRIX

MODULE

4K M8121 MEMORY
MATRIX MODULE

16K BIPOLAR
—_—

Figure 2-8 4K Bipolar Memory Matrix Addressing (M812 1)
2-12

1-3634

2.6.4 1K Bipolar Memory Matrix Module Address Decoding

Address decoding in the 1K M8111 Memory Matrix module is similar to that performed in the 4K M8121 module
just described. The difference is in the function of the individual MAD bits (Figure 2-9). In the M8111, MAD bits

(14:13, 11:10) are compared with a unique jumper configuration. The M8111 with the jumpers that match the MAD
bit configuration is the one to be accessed. This bit comparison on an M8111 then allows MAD bits (09:08) to
identify which one of four 256-word rows contains the word location to be addressed. The particular word in this
256-word row is selected by MAD bits {12,07:01).

FASTBUS/UNIBUS ADDRESS

]

MEMORY ADDRESS REGISTER (MAD)

ADDRESS
1 OF 256
WORD LOCATIONS

ADDRESS
1 OF 4-256
WORD ROWS

e ——— ——

ADDRESS 1 OF
4-1K MATRIX
BOARDS %

ADDRESS
1 OF 2
CONTROLS

1K M8t11 MEMORY

MATRIX MODULE

1K M8111 MEMORY
MODULE

M8120

% SELECT ONE OUT
OF 16 POSSIBLE

1K ADDRESS BLOCKS

—_——— e

———

CONTROL

MATRIX

1K M8111 MEMORY
MATRIX MODULE

1K M8111 MEMORY

MATRIX MODULE

BIPOLAR
e

—— ——

—— —

—

Figure 2-9 1K Bipolar Memory Matrix Addressing (M8111)
2-13

1-1323

2.6.5 4K MOS Memory Matrix Module Address Decoding

The MAD (14:13) and (02:01) bits are decoded at each G401 MOS Memory Matrix module when the directing

M8110/M8210 control is addressed (Figure 2-10). Because the states of MAD (14:13) are compared to jumpered
states unique to each module, the module with matching states is the module to be accessed. This equality at the

addressed G401 module, in turn, enables examination of MAD (02:01). The states of these bits are decoded at a logic
structure on the G401 module to determine which of the four 1024 X 16-bit word block contains the location being

addressed. Output from this structure enables addressing of the pertinent 1024-word blocks and implements access

to the address location.
FASTBUS/UNIBUS
15

MEMORY

14
—

ADDRESS

0F 2

GE—

MATRIX

——

—

——

S——

—

CONTROL

MODULE

G401

MEMORY

MATRIX MODULE

|
I

—

4K G401 MEMORY

MATRIX

]

——

)

:
4K

ADDRESS

4K G401 MEMORY

1 0F a-1K
MEMORY BLOCKS

| |
M8110

ADDRESS

1 OF 1024
WORD LOCATIONS

1 OF 4
4K MATRIX MODULES

CONTROLS

ADDRESS REG!STER (MAD)

ADDRESS

MODULE

4K G401 MEMORY

MATRIX MODULE

—— e

———

—

——

Figure 2-10 4K MOS Memory Matrix Address Examination (G401)

2-14

11-1322

CHAPTER 3
LOGIC DESCRIPTION

3.1 INTRODUCTION
As described in Paragraph 1.1, an MS11 Semiconductor Memory System can take two forms: bipolar and MOS.
Systems with bipolar memory use the M8120 control; MOS systems use the M8110 control. Both types of control

are described in the following paragraphs. The descriptions of semiconductor modules follow this system structure.
The narrative begins with the M8110/M8120 control selection, memory bias, and interface logic. This is followed by

a description of the M8110/M8120 parity function and the refresh logic, which pertains only to the MOS
semiconductor memory system. Finally, there is a description of the three memory matrix modules: M8121, M8110

and G401.

3.2 M8110/M8120 SEMICONDUCTOR MEMORY CONTROL MODULE
Figure

3-1

is detailed block diagram of the M8110/M8120 control. Note that transfer of data through the

M8110/M8120 to and from the Unibus or Fastbus and the associated memory matrix module is directed by the
timing and control logic shown on drawing SMCA. This logic within the M8110/M8120 interprets control signals

from the Fastbus or Unibus, controls communication with these buses, and implements DATO and DATI cycles
when requested. The MOS memory refresh logic on the M8110 control is enabled through a jumper connection so
that this logic is operational only when MOS memory matrix modules are controlled by the M8110 control.
Detailed descriptions of M8110/M8120 logic operation are divided into the following sections:
1.

The selection, interface, bus, and multiplexing subfunctions, manipulated by the M8110/M8120 control

logic to perform memory access cycles (Paragraphs 3.2.1 — 3.2.5)

The M8110/M8120 control logic (Paragraph 3.2.6)

The M8110/M8120 parity logic (Paragraph 3.2.7)

The M8110 refresh logic (Paragraph 3.2.8)

3.2.1 Memory Selection Logic
Memory addresses from the Fastbus or Unibus are received in the M8110/M8120 control address selection logic

(drawing SMCF) where they are decoded at a jumper-wired decoding matrix. Decoding of the states of address bits
11 through 17 determines if an address is within the previously established address range, i.e., the address is valid at

this controller and memory will be accessed. In a PDP-11/45 System, address bits 17 and 16 address one of four

32K-word sections of memory. Because bit 15 addresses one of two 16K-word groups within a 32K-word section,
the state of this bit designates the specific control being addressed. Address bits 14 and 13 specify, for a control with

16K words of MOS or bipolar memory, that the location being addressed is within one of the four G401 MOS or
MB8121 bipolar matrix modules. For a control with 4K of bipolar memory, the jumpered states of address bits 11
through 14 allow selection of 1K of contiguous addresses out of a 16K address block, i.e., they select one of 4-1K

M8111 matrix modules.
3-1

FASTBUS DATA FROM
K811 PROCESSOR

PDRB BR< I15:00>8B L

SMCD MEM DATA<17:00 > H
DATA IN

IMULTIPLEXER

select fl,‘f’éu;

SMCA PREQ (B) H

AND

SMCB WWP (1) H -

PARITY.

A | GENERATOR

SMCH UB DATAK 15:00>H

SMCD

YarefB oy

SMCB DATA LATCH H ——T
FASTBUS DATA TO

KB11

PROCESSOR

DATA

asc::':veas

(

omvgns

BUSB A <‘I7=OO>I>
R
4

BUSB DC LO L
CONTROL - BUSA DC LO L
LINES BUSB MSYNC L
-

]

SMCE MEM SA <15:00
> H

UNIBUS ADDRESS ,

SMCH UBAD <14:00> H

FASTBUS

ADDRESS
ADDRESS
MULTIPLEXER

DAPB BAMX <05:00>H AND SAPJ PA <14:06> H

AND

FMAD REGISTER

<1'.RT;>
-—
>H
SAPY PAITN

FAST BUS ADDRESS LINES

SMCF PAR REG STB

pus
N past
AND

CPU)

SMCH UBC1 H

SMCH UBCH L
SMCH MSYNC (B) L
SMCH POWER CLR H
.

- SMCH UBCO L——l

smcF |CONTROL
SNEG L

)

Figure 3-1

UBCA CONTROL OK H

§ alal=

UBCB PERF ACKN L

Slzlz1z

SMCB PERF L =

SMCB|___

AIEE

-HEERE

SMCA ACCESS READY LATCH H

SMCA MEM CO H

l’

SMCA MEM C1 H

REF
REQ. L
|

slelsle
ol W g &
x fo

S|S|S|S

ZZZ|=

UBCC MEM BUS C1

TMCE BEND CLR

TMCE BUST OUT

M8110/M8120 Semiconductor Memory

Control Block Diagram

3-2

SYNCHRONIZATION

CONTROL TO MEMORY
MATRIX MODULES

yvyYVvYy

SARIDy

UBCA CONTROL OK H
UBCC MEM BUS CO

SMCA MEM SYNC (B) L
CPU
CONTROL

'SMCC MAD <14:01 >(1)l>

REFRESH

—

ADDRESS | \sr—
DECODERS

uniBus [PARITY REGISTER DATA

ADDRESS

SMCB RFAD<04:00>H

SMCH UB DATA <15,12,00>

PARITY REGISTER DATA OUT

REFRESH

—

MEMORY
MATRIX
MODULES

SMCE

BUSB SSYNC Le—

SMCF MEM

—>

UNIBUS | ,

BUSB CO L
BUSB C1 L

UNIBUS

AND.

'SMCE MEM SA <17:00>H

SMCE HIGH BYTE PARITY L | PARITY [+ SMCA SA LATCH (1) H
SMCE LOW BYTE PARITY L | CHECKER [¢—— SMCA PREQ (1) L

I N

UNIBUS ADDRESS LINES

DATA OUT (
.

BUSB D<I5S:00>

LINES

SMCE MEM D<15:00>H

B1-DIRECTIONAL
UNIBUS

06 ~volm

CHEck PAR: vy

AND TIMING

SMCA CENABLE L

SMCA PRECHARGE L
SMCA

WRITE PULSE LOW L

SMCA WRITE PULSE HIGH

SMCA
11-0727

Table 3-1 correlates the states of address bits 13 through 17 to the associated memory areas. The required jumper
configurations are also shown.

A valid or acceptable memory address from the Fastbus is indicated by SMCF MEM L being returned to the
processor via the Fastbus. This signal is the output of a wired AND configuration whose inputs are five
exclusive-NOR gates, E89 and E76, and four NAND gates, E77. The address configuration and the absence or
presence of jumpers C, D, E, F, H, J, K, L, and M determines SMCF MEM L generation. The jumpers are located at
the input to the exclusive-NOR gates and the output of the NAND gates.

As indicated in Table 3-1, retaining or removing the jumpers establishes the memory range controlled by Fastbus and
Unibus address bits 13 through 17. Removal of jumper C,D, E, F, or H will cause the associated Fastbus address bit,
when equal to a 1 (high), to disable the exclusive-NOR gate and provide one of the required (high) “AND” inputs
for SMCF MEM L. Likewise, retaining a jumper results in a 0 address bit disabling the particular exclusive-NOR gate
to provide another high input to the wired AND. A simplified version of the address decoder is depicted in Figure
to the wired AND. Highs from the exclusive-NOR
3.2. The assertion of SMCF MEM L results from all high inputs
gates result when both inputs are low or both inputs are high, thereby disabling the gates. It can be concluded from
this that jumper presence (a low) allows a 0 bit (a low) to disable the gate; the gate is wired to accept a 0 address bit.
Likewise, jumper absence allows 1 bits to be accepted. A high from a NAND gate results from one of two
conditions: 1. The output from the NAND gate enabled by an address within the desired range, is blocked by a cut
jumper, or 2. The NAND gate, with a jumper intact, is disabled by an address that is outside the desired range.
NOTE

Jumpers F and H are applicable to 1K bipolar memory only;
they are left intact for 4K bipolar and MOS memory
addressing.

Table 3-2 lists those address bits (11 and 12 for 1K bipolar and 13 and 14 for 4K bipolar and MOS) and jumpers that
pertain to the memory address range assignment of individual MOS and bipolar matrix modules. The removal of any

one jumper assigns the corresponding address range to a MOS or bipolar module. However, most memory

configurations consist of more than one memory module. Table 3-3 lists those jumpers that must be removed to
assign memory addresses to the given capacity memory. These addresses are relative to the address block assigned by
jumpers C, D, E, F and H. For example, an 8K bipolar memory of two modules would be assigned addresses 0—8191
by removing jumpers J and K in this group of jumpers and leaving the other jumpers (C, D, E, F, and H) intact.
However, if this same 8K memory were to be assigned Fastbus addresses 16384 to 24575 (16-24k) then jumper E
would also have to be cut. Note that these jumpers (J, K, L, and M for Fastbus addresses; N, P, R, and S for Unibus
addresses) are used to assign addresses to individual matrix modules under the direction of a particular
M8110/M8120 control, whereas jumpers C, D, E, F, and H are used to assign a 4K or a 16K memory block to a
M8110/M8120 control from the total (128K) address area.

The aforementioned jumpers are physically located on the M8110/M8120 module at locations E87 and E75. For
example, as indicated on drawing SMCF, jumper J can be found at E75, between terminals 01 and 16.

The inputs to the four NAND gates, E77, in the Fastbus address decoding circuit are SMCF FB MUX 14/12 H and
SMCF FB 13/11 H. They are derived from a jumper-wired multiplexer, E67, located on the M8110/M8120 module.
Whether address bits 11 and 12 or 13 and 14 are used is determined by the memory type; bits 11 and 12 select a 1K
section out of a 4K memory area for 1K bipolar, while bits 13 and 14 select a 4K section out of a 16K area for a 4K
bipolar or MOS module. Figure 3-3 illustrates the required jumper connections for both memory types. Memory
address bits 13 and 14 (SMCF FB MUX DEC 13, 14 H) are also input to decoder NOR gates E76 and E89 from this
same multiplexer, E67. Again, the memory type determines the address bit origin.
NOTE

When installing a 4K matrix board, cut E67 jumpers at pins 1,
3, 5, and 7. For a 1K matrix board, cut E67 jumpers at pins 2,
4,6,and 8.

3-3

Table 3-1

Fastbus/Unibus Memory Address (Assign and Decode)

Fastbus/Unibus
Address Decoder Bits

Memory Address

M8110 Jumpers (E87)

Assignment

(NOTE 1, NOTE 2)

4K MOS or

0
0

1K Bipolar | 4K Bipolar | C

0—4K

48K

0
0

1
1

0
1

8—-12K
12—16K

16—20K

0
0

1
|

0
1

1
0

20-24K
24-28K

X
X

0
0

0
1

1
0

|
0

28—-32K
32—-36K

36—40K

40—-44K

0
0

1
1

0
1

|
0

1
0]

44--48K
48—-52K

X
X

0-16K

X
X
16—-32K

32—-48K

48—-64K

X
X

52-56K

0
0

|
|

1
1

0
|

56—60K
60—64K

X
X

64—68K

68--72K

72—76K

76—80K

|
1

0
0

1
1

0
0

0
|

80—-84K
84—-88K

88—92K

92-96K

96—100K

100—-104K

104—108K

108-112K

112—-116K | 112—-128K | X

64—80K

80—-96K

96-—-112K

X
X

X
X
X

X
X

X
X
X
X

116—120K

120—-124K

124—-128K

NOTES:

1. “X” denotes jumper to be cut.

2. Jumpers F and H are left intact for all 4K memory assignments, i.e., when assigning addresses
to G401 and M8121 modules.

FBMUX <14:13> R
FBMUX 14712, 13/11

FBMUX <14:13> H
SAPJ PA17:4§>H

SAPJ PAIT:15> H

SMCF DOECODE <17:13>

(TO UNIBUS
DECODE CKT)

\}/
1
SMCF MEM H
1-1326

Figure 3-2

Simplified Memory Address Decode (SMCF)

Table 3-2

MOS/Bipolar Module Addressing

Fastbus/Unibus

Memory Address

Memory Address Bits

Assignment (within 128K area)

FBMUX
14/12

FB MUX
13/1

0
0

Remove Jumpers
Fastbus

Unibus

K Mf)S or
4K Bipolar

1K Bipolar

Address
Select

0—-4095

0—-1023

4096—8191

1024-2047

819212287

2048-3071

12288—16383

3072—-4095

Table 3-3

MOS/Bipolar Memory Addressing
No.

of M

0. ol

Remove Jumpers

Viemory

Npdules
Memorv

Memory

Khiosor

Capacit

4K Bipolar

]

1K anohr

Addres

Adires

ess

Select

ress

Select

12K

JKL

NPR

16K

JKIM

NPRS

*Connected to one M8110/M8120 Control.

3-5

4K BIPOLAR
4K MOS

SAPJ PA14 H

SMCF

2 L| 15|

4| —— ,3l

DECODE 14 H .|
TM

SAPY PAH1 H

SAPJ PA{3 H
SMCF

DECODE 13 H

MU 14712 H

SAPJ PA12 H

sMmcF FB

SAPJ PA14 H

MUX DEC
14 H
oS 13711 H

SMCF FB

sl ——°

SAPJ

SMCF

E67

13|

MUX DEC 14
H

PA11 H

SAPJ PA{3 H

MUX DEC 13 H

WL 14712 1

|3L

SMCF

SMCF FB

2 Y 15|
‘

DECODE 14 H

12
-

/\———I

@ Ifl lm

SAPJ PA42 H

1K BIPOLAR
16

DECODE 13 H

“l

"¢
9

SMCF FB

SMCF FB
MUX 13/11 H

SMCF
MUX DEC 13 H

E67

Note that in the 4K module configuration, with jumpers F and H retained, the jumper inputs to NOR gates E76 and

E89 (bits 13 and 14) are always at ground. The address bit inputs to these same gates are jumpered, at E67, to the F
and H jumper inputs (SMCF DECODE 13, 14 H), thereby disabling the gates (all inputs are at ground). Since the
output from these two NOR gates is always high, effectively removing them from the decoder, the influence of bits
13 and 14 in 4K memory addressing depends on the absence or presence of jumpers J, K, L, and M.
Figure 3-4 shows the signals used by the Fastbus and Unibus Address decoders.

An effective Unibus memory address, together with

SMCH MSYNC (B) L, generates the SMCF BREQ L signal that

initiates a Unibus DATO or DATI operation. The Unibus address decoder (SMCF) is a wired-AND circuit, similar to

the Fastbus address decoder just described, that consists of five NAND gates (E74 and E85) and five exclusive-NOR

gates (E76 and E88). Inputs to the exclusive-NOR gates are: Unibus address bits 15, 16, and 17; Unibus MUX DEC

address bits 13 and 14 from E78; a jumper-wired multiplexer on the M8110/M8120 module; and the outputs (SMCF
DECODE (17:13) H) from five of the jumpers in the Fastbus address decoder.E78 is wired (Figure 3-5)according to
the memory type installed; it performs the same function for Unibus addressing as E67 does for Fastbus addressing.
Inputs to four of the NAND gates (E74) are SMCF UB MUX 13/11 H and SMCF UB MUX 14/12 H, also from E78.

Unibus decoder bits 13 through 17 use the same jumper (C, D, E, F, and H) configuration established for Fastbus
addressing. In addition, jumpers N, P, R, and S at the outputs of NAND gates E74 must be selectively removed

(Tables 3-2 and 3-3) to establish the desired memory addresses for the matrix modules. Jumpers N, P, R, and S are
located at the same physical location (E75) as jumpers J, K, L, and M of the Fastbus address decoder.
NOTE
When installing a 4K matrix board, cut E78 jumpers at pins 1,

3, 5, and 7. For a 1K matrix, cut E78 jumpers at pins 2, 4, 6,
and 8.
3.2.2 Unibus Interface (SMCH)

Figure 3-1 shows the Unibus data and address paths. In contrast to the Fastbus, which, along with a semiconductor

memory, is a physical component of the PDP-11/45 processor, the Unibus can be located remotely. As a

consequence, the M8110/M8120 can connect to the full-duplexed Unibus through long lines which must be driven
and received. The Unibus receiver and driver logic (shown on drawing SMCH) includes: the address receiving logic
involved in both DATO and DATI cycles, the data receiving logic which operates only on a DATO, the data driving
logic which responds to a DATI operation, and specific logic signals controlling Unibus DATO and DATI operations.
The 18-bit Unibus address received at SMCH on the lines BUSB A (17:00) L is input to an 18-stage buffer formed by
type 380 line receivers. The second input to each receiver is conditioned by a common line to ground. Therefore,

each Unibus address received is terminated at the characteristic line impedance and inverted to assert SMCH UBAD

(17:00) H. These outputs are applied to the MAD register shown on SMCC.

3-6

11-1327

Figure 3-3 Fastbus Address Multiplexing {14:11) Required E67 Jumpers

SAPJ

PA (17:15) H
FASTBUS

FASTBUS
ADDRESS

SMCF FB MUX 14/12,13/11

SAPJ PA (14:11) H> Ak

SMCF FB MUX DEC (14:13) H

FASTBUS

(E67)

ADDRESS

SMCF MEM H/L

DECODER

_
>

{NOTE 1)

SMCF DECODE (14:13) H

SMCF

DECODE

(17:15)H

SMCF_UB_MUX 14/12,13/11
UNIBUS

MUX

SMCH UBAD (14:11) H

SMCF_UB MUX DEC (14:13)
H

(E78)

UNIBUS

SMCH MSYN (8) L | peoooen

UNIBUS
ADDRESS

SMCF BREQ H/L _

(NOTE 2)

SMCH UBAD (17 :15) H

NOTES

{ - Jumpers C,D,E,F and H (E87)
Jumpers J,K,L and M (E75)
2 - Jumpers

N,P,R

and S (E75)
n- 2185

Figure 3-4 Address Decoding (Drawing SMCF)

4K BIPOLAR

1K BIPOLAR

4K MOS

DECODE 14 H
SMCH UBAD 11

SMCH UBAD 13 H
SMCF
DECODE 13 H

SMCH UBAD 14 H

SMCF UB

2] —— 13|

MUX DEC 14 H

SMCF

U
E—MUX 13741

SMCH UBAD 12 H ——lj

SMCF
DECODE 14 H
SMCH
SMCH

| 9|

SMCF

UBAD i H
UBAD 13 H

UuB

MUX DEC 13 H

SMCF
DECODE 13 H

/"\16

/_\ 14

smcr

I 3

16
SMCF uB
j—is MUX 14712 H

Olfl'm AIO‘|N

SMCH UBAD 14 H

1
.

(DINJIO)

SMCH UBAD 12 H

/—\12
11

9 I

SMCF UB
MUX 14/12 H
SMCF UB
MUX DEC

14 H

SMCF UB
MUX 13/{1

SMCF

MUX DEC13 H

E78
11-1329

Figure 3-5 Unibus Address Multiplexing (14:11) Required E78 Jumpers

3-7

The 16-bit Unibus data input is received at SMCH on the lines BUSB D (15:00) L as input to a 16-stage buffer which

consists of type 380 line receivers. The second input to each receiver is conditioned by a common line to ground. As
a result, each data word received from the Unibus is terminated at the characteristic line impedance and inverted to
assert SMCH UB DATA (15:00) H. These outputs are applied to the data in the multiplexer shown on SMCD.
The data word read during a given DATI cycle is asserted at the Unibus interface as SMCE MEM SA (15:00) H. This

data is input to a 16-stage drive network formed by type 8881 open collector NAND gates, AND gates E45, E46,
E47, and E48. This gating network is enabled by the ANDing of SMCB MEM SSYNC L and SMCH UBC1 H. SMCH
UBC1 H is low during DATI operations and SMCB MEM SSYNC L is asserted during each DATI cycle at the point
where the data word addressed during that cycle is stable. The output of this gating network, when enabled, asserts
the line BUSB D (15:00) L on the Unibus.

All Unibus control signals to the M8110/M8120 are received and buffered at SMCH. BUSB MSYNC L is received at

the Unibus interface and inverted to assert SMCH MSYN (B) H (E96). This level is, in turn, inverted to assert the
complementary signal SMCH MSYNC (B) L at E100.
BUSB CO L and C1 L define the nature of each Unibus access cycle. They are received and inverted to generate
SMCH UBCO H, L at E37 and E39 and SMCH UBC1 H, L at E49 and E39. The latter signal is inhibited until SMCH

MSYNC (B) L (E100) is received 150 ns after the processor raises BUS BUSY. The states of SMCH UBCO and SMCH
UBC1, along with the memory operation initiated by each state, are listed in Table 2-2. Note that the levels of UBCO
L and UBC1 L correspond directly with the COL and C1L levels from the Unibus, while the UBCO H and UBC1 H
levels are complementary to the Unibus inputs.

PWRS MEM DC LO L is received at the interface and inverted to assert one of the OR conditions for SMCH POWER
CLR L. BUSB INIT L is received at the Unibus and gated with the AND of SMCB REF REQ L and SMCA RREQ
(B) L. The result, when true, is the other OR condition that asserts SMCH POWER CLR L. The purpose of this level
is to clear all condition-sensitive logic following a power-up cycle and to initialize this logic at start-up time. Note

that if a refresh cycle is in process, SMCH POWER CLR L is inhibited, except when a power failure causes PWRS
MEM DC LO L to be asserted.
NOTE
Fastbus address and data interfacing are shown, respectively,

on drawings SMCC and SMCD. These drawings are described
in Paragraphs 3.2.3 and 3.2.4.

3.2.3 Address Multiplexing (SMCC)

The semiconductor memory bus is part of the M8110/M8120 control and includes the multiplexing of memory
address and data from the Fastbus and Unibus to the memory matrix modules (Figure 2-5). Data addressed on a
DATI cycle is bused directly from the matrix modules to both the Fastbus and Unibus interfaces to be received by

the requesting bus (Fastbus or Unibus). Refer to the data and address path block diagram shown in Figure 3-1. The

M8110/M8120 address multiplexing logic, shown on drawing SMCC, is shared by three classes of addresses: the
Unibus address, the Fastbus address, and the refresh address.
NOTE

Refresh addresses are generated only when an M8110 is
controlling G401 MOS Memory Matrix modules. When an

M8110is controlling M8111 or M8121 Bipolar Memory Matrix
modules, the logic that generates refresh addresses is disabled.

Out of each 18 address bits received at the control from either the Unibus or Fastbus, 15 bits are multiplexed and
mapped as shown in Figure 2-7 and Table 3-4. The refresh address SMCB RFAD (04:00) H is a row address only and
*internally generated (Paragraph 3.2.8).

3-8

Address multiplexing occurs asynchronously, based either on demand, as with isolated access requests, or on priority
arbitration, as in the case of several simultaneous access requests. However, when the multiplexing strobe levels are
asserted at the address multiplexing logic, all priority claims have been arbitrated; subsequent requests are locked
out. The previous address is output until the leading edge of SMCA REQ LATCH PULSE L, when it is unlatched
from the buffer.
Table 3-4

Multiplexed Address Inputs to MAD (SMCC)

Unibus

Fastbus

Refresh

Memory

Address

Address
SMCH

SAP]

DAPB

SMCB

SMCC

UBAD XX H

PA XX H

BAMX XX H

RFAD XX H

MAD XX (1)H, L

03
04

>
-

06
07

07
08

13
14

15
(Note)

(Note)

NOTE: Fastbus/Unibus address bits 15, 16, and 17 are used in the bus address decoders (SMCF). They are not
included in the MAD configuration output to the memory matrix modules.

3.2.3.1 Unibus Address Multiplexing — SMCA BREQ (B) H and SMCA REQ LATCH PULSE H (drawings SMCA
and SMCC) assert SMCA BREQ ADDR EN L to gate SMCH UBAD (14:00) H into the latching buffer. This address
from the Unibus is latched into the buffer on the trailing edge of SMCA REQ LATCH PULSE L. This serves to map
the address so that SMCH UBAD (12:02) corresponds to MAD (11:01) (1) H, SMCH UBAD 01 H corresponds to
SMCC MAD 12 (1) H, SMCH UBAD (14:13) H corresponds to SMCC MAD (14:13) (1) H, and SMCH UBAD 00 H
corresponds to SMCC MAD 00 (1) H.

3.2.3.2 Fastbus Address Multiplexing — Fastbus addresses are multiplexed onto the address latching bus by SMCA
PREQ ADDR EN L, which is asserted by SMCA BREQ (B) L, SMCA RREQ (B) L, and SMCA REQ LATCH PULSE
H. This action gates the Fastbus address inputs onto the address latching bus. This address data is latched into the
buffer on the trailing edge of REQ LATCH PULSE L. Fastbus addresses are mapped in the same manner as Unibus
addresses.

3.2.3.3 Refresh Address Multiplexing — The 5-bit internally generated refresh address SMCB RFAD (04:00) H is
multiplexed into the address latching buffer by the assertion of SMCA RREQ (B) L and latched on the trailing edge
of SMCA REQ LATCH PULSE L. Each refresh address loaded into the buffer is mapped so that SMCB RFAD
(04:00) H corresponds to MAD (07:03) (1) H.
3.2.4 Data Multiplexing (SMCD)

In executing a DATO operation from the Fastbus or Unibus, a data word or byte accompanies the memory address.
Multiplexing of the data takes place in a 16-stage memory data buffer, with each stage driving the corresponding
stage of a 16-stage latching data register. Logic is shown on drawing SMCD. Four 745158 multiplexers comprise the
data buffer; the latching data register is composed of three elements of a 3404 latch (E1, E3, and E13).

During a Fastbus DATO operation, data (PDRB BR (15:00) B L) is gated into the data buffer with SMCA PREQ (B)

H. However, during a Unibus DATO, the absence of this signal (SMCA PREQ (B) H) enables the data (SMCH UB
DATA (15:00) H) entry. The output of each multiplexer stage is delivered to the data (D) input of the corresponding
data latching register stage. SMCB DATA LATCH H is the common latching pulse to all the L inputs of this register
for both Fastbus and Unibus write operations.

The (1) outputs from the 3404 latches follow the D inputs as long as the L inputs are low (SMCB DATA LATCH H).
These latches are latched when SMCB DATA LATCH H is asserted. The (1) outputs are thus locked, i.., the
information present at the D inputs, at the time of the positive-going transition at the L input, is retained at the (1)
outputs.

SMCD MEM DATA (15:00) H is output to memory for storage. The output of the data buffer, SMCD MBD (15:00)
is also input to two parity generators, E2 and E4, whose outputs are the parity bits SMCD MEM DATA (17:16)H to
memory (Paragraph 3.2.7.4). The resultant output of E2 and E4 is latched into two latching register stages, E13,
with SMCB DATA LATCH H. During DATO, both outputs of the parity generator are stored; bit 17 with the
high-order byte and bit 16 with the low-order byte. Only one of the two bits will be generated and stored when a
DATOB is executed.

3.2.5 Data Output (SMCE)

Read data, destined for the Fastbus during DATI operation, is retained in the Data Out Register shown on drawing

SMCE. This 18-stage logic circuit, composed of a latching register and an output buffer, functions as the interface
when memory is read out to the Fastbus. Read data to the Unibus, bypassing this logic, is routed directly from
memory to the Unibus drivers (drawing SMCH).

The 16 low-order stages of the Data Out Register are formed by three 3404 latch elements (E102, E111, and E122)
and four 74S03 open-collector NAND GATE CHIPS (E101, E112, E113, and E123). Stages 16 and 17, which latch
the lower and upper byte parity bits for input to the parity checking circuits (E103 and E124), are formed by two
'

of the latches in E122.

The data (SMCE MEM SA (17:00) H) from the addressed memory location is inverted in the latching register and
output to the parity checking logic as SMCE DATA OUT (17:00) L. Latching of the input data into the latching
register occurs once during each DATI cycle when SMCA SA LATCH (1) H is raised. SMCE DATA OUT (15:00) L
is, in turn, inverted in the output buffer and gated by SMCA PREQ (1) L onto the Fastbus as SMCA MEM D (15:00)
H. The parity checker, E103 and E124, provides a parity check for each 8-bit byte (Paragraph 3.2.7.5).
3.2.6 M8110/M8120 Control Logic

The M8110/M8120 control logic (drawing SMCA) directs all aspects of a given memory access cycle, including
priority arbitration, in response to a specific Fastbus or Unibus request. Description of SMCA control logic
operation is based on the logic event sequence characteristic of DATO and DATI bus transactions. These event
sequences apply to M8110/M8120 controls with either MOS or bipolar memory, with or without optional parity. In
a system without byte parity, M8110/M8120 parity and diagnostic logic is ignored.

3-10

Because the semiconductor memory system can be accessed from either the Unibus or Fastbus, a DATO operation
necessarily has two sources of data access initiation: one in response to Unibus DATO requests, and the other in
response to Fastbus DATO requests. Both modes of DATO execution generally share a common control logic

structure, with entrances to the logic being a function of the specific request. This same structure also serves to
implement the internally initiated refresh cycle, which is applicable only to a MOS memory system.

In a DATI cycle, the location is addressed and the data in that location is read and transferred to the Unibus or
Fastbus. However, a DATIP implements a pause after the data is read and transferred, which locks out all other
access cycle requests until the next access cycle is initiated. This next access cycle must be a DATO or DATOB
R

unless a parity error is detected during a Fastbus DATIP. In other cases, the DATO following a DATIP will occur
within one processor machine cycle. Like the DATO cycle, a DATI operation has two modes of initiation: one in
response to a Unibus DATI request, and one in response to a Fastbus DATI request. Both modes of DATI execution

generally share a common control logic structure with entrances to this logic being a function of the specific request.

Figures 3-6, 3-7, 3-8, and 3-9 are flowcharts illustrating the sequential steps during DATO and DATI cycles from the
Unibus and Fastbus to a bipolar or MOS memory location. Figure 3-10 provides a similar description of a Fastbus
DATIP operation followed by the necessary DATO. The individual steps in the flowcharts itemize events or
conditions that are necessary for the completion of the entire DATO/DATI/DATIP cycle. Required operations are

shown by rectangular blocks, while necessary decisions are depicted by diamond-shaped blocks. A decision is
resolved on the basis of the particular condition prevailing at the time the decision block is entered. AND and OR

functions are shown, where necessary, to emphasize the requisites for certain operations; off-page connectors
provide intra-figure continuity. The remarks section contains comments relative to the particular steps, signal
requirements, and the logic drawing where the circuits can be found. Timing (as it pertains to bipolar memory) for

the five types of cycles covered by the flowcharts is shown in Figures 3-11, 3-12, 3-13, 3-14 and 3-15. Figure 3-16
depicts the timing for a Unibus DATO operation when the M8110/M8120 is connected to a MOS memory (timing

for other operations to MOS memory is similar). Table 3-5 lists the timing requirements relative to the two memory
types.

3.2.7 Parity Logic
The parity generating and detection circuits in the MS11 provide the means for the operating system and the
diagnostic software to control and test for correct memory data parity. The parity detection circuit determines when

a (Fastbus) read parity error occurs and then notifies the operating system of the fact. The operating system can

then remove the faulty memory module from use. There is a provision to disable the parity detection function when

parity checking is not desired. This would be the case if it is necessary to execute a diagnostic out of a memory with
known errors. The parity error checking function is normally enabled only when looking for errors. Another portion

of the parity logic is used to assign correct parity to write data. The appropriate parity bit or bits are asserted and

sent to the addressed memory module. A write-wrong parity bit is also available for diagnostic checking of the parity

trap logic. This bit causes odd parity to be stored in memory so that when it is read back a parity error is generated.

The parity logic is contained on the M8110/M8120 module (drawings SMCB, SMCD, SMCE, and SMCF). The
principal circuits are the parity register address decoder, the parity register, the parity generator, and the
parity

checker. Figure 3-17 shows the relationship of these circuits to the read and write data routed through respectively,

the Data Out Register and the Data In Multiplexer.

3.2.7.1 Parity Register Address Decoding — The parity register (Paragraph 3.2.7.2) is assigned one of 16 addresses in

the range 772100-7721365. The function of the parity register address decoder (drawing SMCF) is to check all
addresses on the Unibus and compare them to the address assigned to the parity register in this M8110/M8120
module. The logic is hard-wired to decode only one of the 16 possible addresses. (The address selection jumper
configuration in the address selection logic and a jumper in the parity register address decoder decode the two

low-order octal digits in the parity register address. The high order digits, 7721xx, are decoded separately.) If the

address on the Unibus is the same as the one assigned to the parity register, and master sync is asserted, one of two

signals is asserted: 1) if a read (DATI or DATIP) is indicated, the signal SMCF PAR REG OUT H is asserted and the

8.6

Unibus

* C START )

SMCH UBAD (17:13 H((4K modulés),SMCF. SMCH UBAD (17:11) - (1K modules).

Address

Decode

SMCF

Denotes useable address, SMCF.

BREQH.L

8.1
BUS
BUSY L

;MCA
REQ

Indicates Unibus in use. All other devices locked out.

Generated after < 12 nsec inherent delay. (Signal not latched at this time), SMCA E51.

B) H

Memory

Address
SMCH
UBAD
{(17:00H

8.2

SMCA

Input to Unibus address receivers as BUSB A(17:00) L, SMCH.

BREQ
IN PROG H

Receiver output, SMCH.

8.8
§MCA

‘REQ

""SMCA RREQ (B) L, SMCA. (SMCA BREQ IN PROG L
is not applicable to DATO, used in DATIP operations.)

" SMCA DONE L, SMCA.

LATCHH

8.3

Control
Bits

SMCH
UBCOH,L

SMCH
UBC1H,L

8.9

BUSB CO L, BUSB C1 L specify DATO. SMCH.

Latch

SMCA E51

Inhibit

Refresh inhibited during DATO * SMCB REF REQ L latched in.

BREQ (B) H

Recsiver output, SMCH.

REF REQ

Receiver output inhibited until SMCH MSYNC (B) L generated, SMCH E48.

PREQ (B) H

s a e

BREQ (B) L inhibits PBEQ (B) H,L

84
Write

Input to Unibus data receivers as BUSB D(15:00) L. "* SMCA PREQ (B) H data is input

Data

to data buffer. SMCH, SMCD.

8.10

SMCA REQ

Asserted independently of SMCA REQ LATCH PULSE L.

LATCHPULSE 2 L
8.5

SMCA

BUS B

MSYNC L
SMCH
MSYNC
(B) H,L

Initiate latching pulse, SMCA E53.

REQ LATCH

Initiates DATO operation 150 nsec (deskew delay) after BUS BUSY L, SMCH.

PULSE L

Receiver output, SMCH.

8.11

Wired AND, SMCF.
-

Unlatch
MAD Reg.

Drop p prprevious memory ry add address ( SMCC MAD (14:00")

8.12

BREQ

ADDRENL

SMCA

11-1297

)
Figure 3-6 Unibus DATO Logic Flow (Sheet 1 of 3)

3-12

11-1298

MOS only

8.18

SMCA

RC timeout = 70 nsec, SMCA E14 pin 4 disabled. (SMCB BIPOLAR L for MOS operations)

CENABLE

SMCA E25 pin 6.

Gate

CENABLE gates MOSA A, B, C, D (G401 module) to access
memory (Paragraph 3.5). Refer to NOTE 1 on Figure 3-6, Sheet 3.

MOS Adr

8.13

Address

——

8.19
Memory

New memory ad-ress input to MAD Reg. SMCC.

8.14
Delay

SMCA

RC timeout = 60 (Bipolar) or 90 (MOS) nsec, E14 pin 9 enabled.

" SMCABL

PRECHARGE L

SMCA REQ LATCH PULSE L after approx. 65 (80 if MOS) nsec as determined by R42.

Time Out
Latch

MAD Reg.

SMCA REQ

LATCH PULSE 2L
BREQ
ADDR EN

Set
BUSY
BUSY

(1) H

Latch new memory address into the MAD Reg. (Table 3-4), SMCC.
8.20
Coincident with

SMCA

)
!

SMCA REQ LATCH PULSE L

RC timeout = 90 (Bipolar) or 230 (MOS) nsec, SMCA E15 pin 4 disabled.

MAD Reg. holds address " REQ LATCH PULSE L, SMCC.

ACCESS
READY
LATCH

Adjust R42 for 80 (95 if MOS) nsec delay between SMCA REQ LATCH initiation and SMCA PRECHAfRGE.

SMCA E25 pin 11.

BUSY set < 80 (95 if MOS) nsec after REQ LATCH - BUSY is a prerequisite for PRECHARGE, SMCA{
Acess bipolar memory at this time - SMCA CENABLE L asserted (SMCA A H always high). Refer to

Note 1 on Figure 3-6, sheet 3.

8.15

Start

Timing

8.16
PRECHARGE
L

]

Initiate RC network delays for SMCA A H (MOS only) SMCAB L,

SMCA CH, and SMCA D L. SMCA D L not used in Unibus operations.
8.21

“SMCA B L. Precharge MOS memory cells. (Ignored by bipolar)

8.17

Set

DATA
LATCH

GATED

REQ

SMCB E52.

DATA

PULSE L

LATCH H,L

Clear

DATA

SMCB E31 pin 12.

Point in access cycle where Unibus data considered de-skewed, SMCB E31.

SMCB E32.

LATCH
822
Latch

Write

11-1299

Latch write data into Data In Reg, SMCD.

Data

11-1300

Figure 3-6 Unibus DATO Logic Flow (Sheet 2 of 3)

3-13

8.33

8.26

ACCESS

Set

MEM

READY

Concurrent with set DATA LATCH, SMCB E31 pin 12.

SSYNC

SMCA

LATCH

8.23
Byte

Latch both latches E28. " BREQ (B) H - UBCO L at SMCA E50 pins 2 and 3, the D inputs

Select

to both latches are high.

SMCA
OUT HIGH,
LOW

8.27

DATO — OUT HIGH and OUT LOW.

BUS B

DATOB — OUT HIGH or OUT LOW depending on state of MAD 00. (Provides the means

SSYNC L

.
N
o
" SMCF BREQ H. Unibus notified DATO is being executed, SMCF E40.

8.34

Clear

to specify which byte is to be stored.)

MEM

SSYNC

8.28

MSYNC L

PULSE HIGH,
LOW

Store
Data

SMCH

(B) H,L
BREQH,L

DATO — Both signals output concurrently
DATOB — One signal output (as determined by MAD 00).

Write 8-bit byte (DATOB) or 16-bit word (DATO) into memory,

SMCF

BUSB

BREQ
H, SMCF E40 pin 11. Aithough BREQ
H generates SMC8 MEM SSYNC L,

SSYNC L

MEM SSYNC H is not cleared at this time "~ SMCB E20 pin 12 remains enabled.

Clear

Direct reset 30 nsec (fixed delay) after

DONE

flip-flop is set, SMCA E42 pin 13.

8.36
BREQ

MOSC (G401) or BIPB (M8111/M8121)

BIH

{

DONE
L

Terminate write pulses, SMCA E27.

Clear

SMCA E30 pin 4

BUSY

SMCA EA41 pin 9.

Unibus available after 76 nsec de-skew period following MSYNC L (Step 8.28.)

8.38
ADDRESS

8.31 1
I AH, BL,CH,
DH

SMCA E16.

SMCA

8.39

‘

STOP

’

NOTE 1: If memory is bipolar, jumper A is not cut; BIPOLAR L
is asserted (SMCB). .. SMCA E14 pin 4 is never enabled (low).

8.32

CENABLE L

.. SMCA CENABLE L follows the SMCA BUSY (1) H output.

SMCA

CENABLE generates BIPB C3A, B, C, D on M8111 module and
BIPB C30, 1,2, 3 on M8121 module.

I-1303

e o

I1-13 01

Input to Unibus receivers dropped. SMCH

DATA

DONE

BUS Busy
8.30

Set

8.37

SMCA E17 pin 6 goes low.

. DONE L. SMCA E18, E17.

SMCA E39, pin 2

Timeout

REQ

LATCH A

IN PROG

"'BREQ L at 8.28, SMCA E51 pin 1 (NOTE: Inherent delay <12 nsec.)

Delay

R13 adjusted to generate a 60 nsec write pulse, SMCA.

11-1302

Figure 3-6 Unibus DATO Logic Flow (Sheet 3 of 3)

3-14
S

Delay

BREQ REQ

8.29

{

ISR

8.25

(See note, step 8.28).

Unibus response to BUSB SSYNC L, SMCH

MSYNC

8.24

WRITE

NC.

H "~ SMCB E20 pin 12 diszhi~d and SMCB MEM SSYNC L,
MEM SSYNC
H

9.12
9.7

MEMH, L

Acknowledge usesble address to CPU

(NOTE: Invalid addresses generate MEM H; hold PREQ reset,
terminate DATO cycle.) SMCF.

Unlatch

Drop previous address, SMCC MAD (14:00).

MAD Register

9.13
9.8

9.0

‘

(~i

START

PREQ

TMCE BUST OUT

’
Set PREQ

SMCA E42

PREQ (1) H

SMCA

9.1
Write

Data

]

PDRB BR (15:00) B L input to data buffer from Fastbus, SMCD.
02

PREQ

(B)H,L

9.14

SMCA ES, E54

BEND

PULSE L is initiated. BEND CLR terminates an already started

CLR

Fastbus memory cycle that the processor does not wish to

Bits

Specify
DATO

latched at this time), SMCC.

CPU sends BEND CLR (and BCY is set) before REQ LATCH

" REFREQL : BREQ L

_ 9.3

[

New memory address input to MAD register (not

9.9
‘9.15

UBCC MEM BUS CO L, UBCC MEM BUS C1 L specify DATO. SMCA.
..

SMCA MEM CO H, SMCA MEM C1 H (not latched at this time)

YES

BEND

continue.

Control

U
Memory Address

SMCA E31 pin 6.

ADDRENL

SMCA

CLR

CPU sends BEND CLR after REQ LATCH PULSE L is
initiated. Fastbus memory cycle terminated.

9.9.1

Set BCY

SMCA BCY (1) H

SMCA

9.15.1

SMCA

Set BCY

SMCA

SMCA REQ
9.4

Memory
Address

Asserted " PREQ (1) L. SMCA ES52.

LATCH PULSE L

9.5

Multiplexer

L Delay Time Out

9.1

Coincident with REQ LATCH PULSE L, SMCA E19.

LATCHPULSE 2L
Latch PREQ (B) H

SAPJ PA <17:13> H (4K memory modules), SMCF.

Decode

(SAPJ PA <17:11> H ~ 1K memory modules)

SMCA REQ LATCH PULSE L after approx. 80 nsec for
MOS, 65 nsec for bipolar.

Latch

Latch new address into MAD reg. (Table 3-4). SMCC

MAD Register

inhibit

Address

Delay Time Out

" BREQ - REF REQ L are latched, SMCA.

(unless BCY SET)

9.6

Normal delay time out after approx. 80 nsec for

MOS, 65 nsec for bipolar.

9.16

SMCA REQ

Wired AND, SMCF.

—]

Initiate address latching puise " PREQ or BCY set, SMCA E17.

LATCHH
B

Fastbus

tremely short, SMCC.

9.15.2
DAPB BAMX (05: 00) H, SAPJ PA(14:06) H, SMCC.

SMCA REQ

address if REQ LATCH PULSE L assertion time is ex-

MAD Register

l
Address

Indeterminate latched address. Could be the old or new

Latch

SMCA REQ

DAPB BAMX (05:00) H, SAPJ PA (17:06) H (Refer to Figure 3-12 for timing).

Signal terminated early, SMCA E8 pin 8.

LATCH PULSE L

9.10

PREQ

" REQ LATCH H locks out requests, SMCA E51.

BREQ, RREQ

MAD reg. holds address *.

REQ LATCH PULSE L, SMCC.

ADDRENL

9.16.1

9.9.2

IH-1304

Inhibit REQ

]

MAD Register

]

LATCH PULSE L
Remains Latched

SMCA REQ

" Delay time out, SMCA E 19 pin 4.

LATCHPULSE 2L

SMCA E8
Address of previous operation retained in MAD (new address

SetBUSY

Access bipolar memory at this time - SMCA CENABLE

asserted (SMCA A H always high if memory is bipolar).
See remarks at 8.14 (Figure 3-6).

locked out), SMCC.
9.15.3

9.9.3

PREQ (B) H

" SMCA BCY (0) H. Inhibit write data to Data In Mux, SMCD.

.
PREQ

Signal terminated early; MAD reg. holds

ADDRENL

address " REQ LATCH PULSE L, SMCC.

PREQ(B) H

" SMCA BCY (0) H. Inhibit write data to
Data In MUX, SMCD.

11-1306

11-1305

Figure 3-7 Fastbus DATO Logic Flow (Sheet 1 of 3)

3-15

9.23
9.17

Start

Initiate RC network delays for SMCA AH,BL,CHand D L.

CENABLE

SMCA E25 pin 6

Gate

CENABLE gates MOSA A, B, C, D (G401 module) to access MOS memory.

MOS Adr.

(Paragraph 3.5 and Figure 3-6, NOTE 1).

U e

Timing

9.18

PRECHARGE

- SMCA B L -BUSY (1) H. Precharge MOS memory cells.
Used with bipolar for timing only.

9.24

9.19

Clear
DATA
LATCH

PRECHARGE L

SMCB E52

RC timeout = 60 (Bipolar) or 90 (MOS) nsec, SMCA E14 pin 9 enabled.

i
oo
o

GATED
REQUEST
PULSE L

SMCA

~“SMCABL

SMCB E32

SMCA
CPU sends BEND CLR after REQ LATCH PULSE L

RC timeout = 90 (Bipolar) or 230 (MOS) nsec, SMCA E 14 pin 4 disabled.

times out (but before CONTROL OK would normally

READY
[ ACCESSLATCH

be asserted). Fastbus memory cycle terminated.

]

SMCA E25
9.26

SMCA E9

[

SMCADL

e At

SMCA E54 Inhibit write data to Data in MUX, SMCD.*

M_EM

RC timeout = 30/60 (Bipolar) or 240/210 (MOS) nsec, SMCA E 15 pin 9 enabled.
SMCA Eb55,

et e

SYNCH,L

9.21

CONTROL
OKH, L
Latch

Control

Signals

|
]

Signal from CPU allows cycle to continue. SMCB, SMCA.

9.27

»
MEM

g
.
Returned to CPU to indicate data is to be stored, SMCA E55.

SYNC (B) L

SMCAMEMCOH, L and
SMCA MEM C1 H, L latched.

9.28

MOS only

Set

SMCB E44 pin 6

DATA

9.22

LATCH

RC timeout = 70 nsec, SMCA E14 pin 4 disabled (SMCB BIPOLAR L
for MOS operations).

DATA

11-1307

Point in access cycle where Fastbus data considered de-skewed, SMCB E32.

LATCHH,L

SMCA

I1-1308

Figure 3-7 Fastbus DATO Logic Flow (Sheet 2 of 3)

3-16

[Al

[K]

|
]

]

9.34

MEM SYNC (B) L ]

"~ PREQ (B) H, SMCA

9.35
9.29
Latch

Write

)

WP Delay

Latch write data into Data in Reg., SMCD.

Data

R13 adjusted to generate a 60 nsec write pulse, SMCA.

|
|

Delay Timeout

SMCA E17 pin 6 goes low.

Sst DONE

9.30

Terminate write pulse, SMCA.
" WP H during normal DATO or PREQ (B) H if DATO terminated

by BEND CLR, SMCA E41 pins 9 and 2.

Byte

Select
SMCA
OUT HIGH,
LOW

Latch both latches E28.

|
|

DONE L

}

" PREQ (B) H - MEM CO, both D inputs are high, SMCA !

SMCA E16.

DATO — OUT HIGH and OUT LOW.

(DATOB — OUT HIGH or OUT LOW as determined by s*ate of MAD 00;
the means by which only one byte is selectively stored.

9.36

Clear BCY

]

Clear BCY if set, SMCA.

\J}/

037

9.31
WRITE

PULSE
HIGH, LOW
Store Data

DATO — Both signals output concurrently

(DATOB — One signal output as determined by MAD 00)

Clear REQ LATCH ]

SMCA E18.

Write 16-bit word. (DATOB = write 8-bit byte.) MOSC (G401) or
B1PB (M8111/M8121).
9.38

Clear BUSY

Direct reset, SMCA.

9.32

AH, BL, CH, DL,

CONTROL
OK
ADDRESS.
DATA

CPU drops signals after MEM SYNC. SMCB, SMCA.

SMCA.

CENABLE

ACCESS

SMCA

READY LATCH

" ADDRESS. SMCF, SMCA.

9.38A

MEM SYNC L

wmemsvnc@IL

SMCA

9.33
Clear
PREQ

9.39

" CONTROL OK + MEM H (BEND CLR -BCY), SMCA

Clear DONE

STOP

)

Direct reset 30 nsec after flip-flop is set, SMCA E42.

9.40
1-1309

11-1310

Figure 3-7 Fastbus DATO Logic Flow (Sheet 3 of 3)
3-17

10.0

START

>
10.8

10.1

10.17

GATED

Unibus DATO

REQ

Refer to Unibus DATO Logic Flow (Figure 3-6).

steps

SMCB Eb52

Unibus response to BUSB SSYNC (SMCH)

BUSB MSYNC L

PULSE L

8.1 and 8.2

SMCH

MSYNC
(B)H, L
BREQ

10.9

10.2
Control

BUSB CO L, BUSB
C1 L specify DATI. SMCH.

Bits

SMCH

UBCOH.L
UBC1H.,L

Refer to step 8.3 (Figure 3-6).

10.3

Initiates DATI operation 150 nsec (de-skew delay) after

BUS BUSY L, SMCH.

SMCB E32

10.18

]

SA LATCH

SMCA E30 pin 13

SA LATCH

BUSB

H, L

10.10

Clear
MSYNC L

SMCF

—

Clear
DATA
LATCH.

Not applicable to Unibus DATI *- MEM SYNC not asserted; data bypasses Data Out Reg
(Step 10.15), SMCA.

Not Set

10.11

MSYNC

(B)H, L

Receiver output, SMCH.

Unibus DATO

steps

See remark at 8.28, Figure 3-6.

See remark at 10.1

8.18 through 8.20

10.20

10.12

10.4

Set
MEM SSYNC

Unibus DATO

steps

See remark at 10.1

.e pg——

SMCB E20 pin 12 enabled.
!0.21

8.6 through 8.14

10.13
Access
Memory
105

CENABLE gates MOSA A, B, C, D (G401 module) to access MOS memory.

Unibus DATO

With bipolar memory CENABLE is asserted when BUSY is set. BIPB CS3
A,B,C,D on M8111 module and BIPB CS0 1, 2, 3 on M8121 module
access bipolar memory at that time (step 10.4). Refer to NOTE 1 on

8.30 through 8.35

steps

See remark at 10.1

Figure 3-6, sheet 3.

Set

If SMCH UBCO H the access cycle is a DATIP. BUSY (1) H sets PAUSE.DONE

SMCB PAUSE

?0.22

10.14

inhibited at 10.20 to prevent termination until the next (DATO) cycle.

Read

Data

Unibus DATO

SMCE MEM SA (15:00) H (SMCH).

steps

SMCB PAUSE

See remark at 10.1

8.29 and 8.36

1u.6

Clear

- BREQ H at SMCA E41 pin- 1

DONE

Wired AND, SMCF

]0.23

During the succeeding DATO, DATA LATCH L clears PAUSE.

Unibus DATO

(Step 8.21, Figure 3-6).

steps

8.37 and 8.38
10.7

See remark at 10.1

10.15

Unibus DATO

steps

8.15 and 8.16

g:;dus

See remark at 10.1

Data

10.24

Read data on Unibus data lines,

BUSB D (15:00) L (SMCH).

STOP

)
11-1313

10.16

BUSB

" BREQ H. Unibus notified DATI is being executed (data is available

SSYN L

on the D lines), SMCF E40.

=131l
C

11-1312

Figure 3-8 Unibus DATI Logic Flow

3-18

11.0

(

START

CENABLE gates MOSA A, B, C, D to access MOS memory (G401).
119

With bipolar memory CENABLE is asserted when BUSY is set.

Access

Memo

1.1
PREQ

' REF REQ L - BREQ L SMCA, E8, E54

(B)H, L

Refer to NOTE 1 on Figure 3-6, sheet 3.

.
SMCE MEM SA (17:00) H input to Data Out Reg. (not latched at this time). SMCE

Read
Data

Control

UBCC MEM BUSCOL,

Bits

UBCCMEMBUSC1L.

SMCA

11.11

SMCA MEM COH, SMCAMEMC1H

- Specify

Fastbus

(not latched at this time)

DATI

Read

SMCE MEM (15:00) H

Data
11.3

11.12

Fastbus DATO

BIPBCS3 A,B,C,D on M8111 module and BIPB CS0, 1,2, 3

on M8121 module access bipolar memory at that time (step 11.14),

11.10

11.2

Refer to Fastbus DATO Logic Flow (Figure 3-7).

steps
9.4 through 9.13

;:“bus DATO
Ps
9.24 through 9.26

11.4

See remark at 11.3
.
:
(NOTE: DATA LATCH not set during Fastbus DATI)

11.13

Fastbus DATO

MEM

See remark 11.3

steps

SYNC (B) L

9.14 through 9.19

1 1.5
Clear

Unlatch Data Out Reg. in preparation for new data from memory,

SA LATCH

SMCA E30 pin 13.

Return to CPU to indicate read data is available. SMCA EB5.

11.14

Fastbus DATO

See remark at 11.3

steps
9.32 t0 9.34

1 1.6

Fastbus DATO
See remark at 11.3

steps

11.15

9.20 and 9.20.1

Set
SA LATCH

11.7

CONTROL
OKH, L
Latch
Control

Signals

Signal from CPU allows DATI cycle to continue. SMCB, SMCA

- SMCA MEM SYNC L clocks flip-flop, SMCA
'

11.16

Latch

Data Out

SMCA MEM CO H, L, SMCA MEM C1H, L latched.

Latched data on D lines, SMCE

Reg.
11.17

j 1.8

Set

DONE

Fastbus DATO

See remark at 11.3

steps

9.22 and 9.23

- PREQ (1) H.at SMCA EA41 pin 3.

Generate DONE L, SMCA E16

11.18

Fastbus DATO

steps

See remark at 11.3

9.38 to 9.40

i1-1314

11.19

(

stor )
11-1315

Figure 3-9 Fastbus DATI Logic Flow

3-19

o i ot
e

16.0

E’]

C START )
16.1

PRE (B) H, L

ér:sF ::% L - BREQL
A

E8,

E54

MEM L, H

Acknowledge useable address to CPU.

Unlatch MAD Reg.

] Drop previous memory address, SMCC MAD < 14:00> .

16.8

Control Bits

] UBCC MEM BUS CO L, UBCC MEM BUS C1L specify DATIP. SMCA.

TMCE BUST OUT

SMCA

163 I

Specify DATIP

I SMCA MEM CO H, SMCA MEM C1 H (not latched at this time).

Set PREQ

SMCA E42

PREQ (1) H

SMCA

16.4

Memory Address

16.14

—

,
|
(Processor can terminate operation before, during, or after (16.20) REQ

16.9

REQLATCHH

]

Memory Address

‘

Wired AND, SMCF EA J
.

16.

" BREQL * REF REQ L are latched.

l.
Inhibit REF REQ, BREQ ]
SAPJ PA (17:13) H (4K memory modules), SMCF.

16.12

.
(SAPJ PA (17:11)
H-— 1K memory modules).

SMCA REQ LATCH PULSE L after approx. 80 nsec

Latch WD R

Latch new address into MAD Reg.

atch VRO Tes.
'

" REQ LATCH H locks out request, SMCA. Eb51.

PREQ ADDR EN L
|

PULSE L

SMCA REQ LATCH

SMCA Eb53.

]

\
BUSY #1)
H

for MOS, 65 nsec for bipolar.

(Table 3-4). SMCC

MAD Reg. holds address "~ REQ LATCH PULSE L
" SMCA REQ PULSE 2L

rk at 8.14 (Figure 3-6).

See remark a

(Figur

SMCA CENABLE asserted (SMCA AH always

Access bipolar memory at this time
high if memory is bipolar).

SMCA E30

1M1-2175%

et e T

11-2176

11-2141

Delay Time out

Set BUSY

Decode

(Not latched at this time), SMCC.

‘

L Latch PREQ(B)H, L l

16.6

Fastbus Address

New memory address input to MAD Reg.

16.16
16.10

16.15

Initiate address latching pulse * PREQ (1)L, SMCA E52

DAPB BAMX (05:00) H, SAPJ PA
(14:06) H, SMCC.

I SMCA E31 pin6

)

through 9.20).

16.5

Address Multiplexer

LATCH PULSE timeout by sending BEND CLR. See Figure 3-7,9.9

DAPB BAMX (05:00) H, SAPJ P(17:06) H

16.13

terminate DATIP cycle) SMCF.

16.2

(NOTE: Invalid addresses generate MEM H; hold PREQ reset,

Figure 3-10 Fastbus DATI-DATO Logic Flow (Sheet 1 of 4)
3-20

e
=
e
b
.
e
o
s

16.17

16.18

PRECHARGE L

Start Timing

Initiate RC network delays for SMCAAH,BL,CHand D L.

SMCA B L -BUSY (1)H. Precharge MOS memory cells.
Used with bipolar for timing only.

|
1
|

16.23

16.19

GATED REQUEST

SMCB E52

PULSE L

CENABLE L

Clear DATA LATCH

Gate MOS Adr

1
I

16.28

SMCA E25

CENABLE gates MOSA A, B, C, D (G401 module) to access MOS

memory (Paragraph 3.5 and Figure 3-8, Note 1).

PRECHARGE L

SMCA E14 pin 9 ensbled.

“SMCABL

SMCB E32

Unlatch Data Out Reg. in preparation for new data from memory,

Clear SA LATCH

SMCA E30.

16.24

CPU sends BEND CLR after REQ LATCH PULSE L times out and

_instead of CONTROL OK. Fastbus memory cycle terminated.

dcommamory

‘lj

RC timeout = 230 nsec (MOS) or 90 nsec (bipolar)

SMCA E 14 pin 4 enabled.

‘

16.25

16.29

MOS or bipolar

SMCE MEM SA (§7:00) H input to Data Out Reg.

16.30

(Not latched at this time).

ACCESS READY

LATCH

DL
raem SYNCH, L

SMCA E9

LOW BYTE PAR H and/or HI BYTE PAR H assert SMCB BAD PAR H

1
rEM SYNC (B) L

if odd byte perity detected. BAD PAR H asserts PERF L at 16.21.1

SMCA EB4. Inhibit write data to Data in MUX, SMCD.

and SET PEL at 16.37 and 16.42 (see remerk at 16.21.1).

; Set PAUSE
1

16.21

16.27
CONTROL OKH, L

Signal from CPU allows cycle to continue. SMCB, SMCA.

Fastbus Read Data 1

SMCE MEM (15:00) H

CONTROL OK,

SMCA MEM C1 H, latched. SMCA E51

DATA
~

STB PAR H

Not applicable in DATIP, SMCA

RC timeout = 240/210 nsec (MOS) or 30/60 nsec (bipolar)

SMCA E 15 pin 9 enabled.
SMCA E55

Return to CPU to indicate read data is available, SMCA.
/

" MEM SYNC, SMCB (Set by BUSY (1) H if Unibus cycle)

16.31

SMCAMEMCOH, L and

Latch Control Signals

SMCB

ADDRESS, MEM H, L
11-2245

CPU drops signal in next time state 1, PERF is valid only

if aseerted at this time. SMCA, SMCB.
Write data placed on the Fastbus data lines.
Not latched at this time, SMCD.

CPU does not drop the address.
" MEM H remains asserted, SMCF.

11-2182

16.21.1

RC timeout = 90 nsec, (MOS) or 60 nsec (bipolar)

SMCAB L

SMCB PERF L

Asserted provided EIE F/F is set. There is an initial, false assertion

of PERF due to data path delays and skew. PERF is a valid error
indication only if it is asserted at the time the CPU drops CONTROL

OK (16.31), SMCB.

MOS only

16.22

[

SMCA A H

RC timeout = 70 nsec, SMCA E 14 pin 4 disabled.

11-2192

Figure 3-10 Fastbus DATI-DATO Logic Flow (Sheet 2 of 4)

3-21

16.40

‘

;

YES

Refresh

(MOS only)

i memory is MOS and SMCB REF REQ (1) H.

is asserted during the pause. the subssquent

DATO
is

treated
as

16.41

{

1 6.32

- CONTROL OK + MEM H +
(BENDCLR L |. BCY), SMCA i

Clear PREQ

MEM SYNC L

- PREG
PREQ (BI
(B) HH + CONTROL OK, SMCA

Sot SA LATCH

Clocked by MEM SYNC L with DATA LATCHR
+ PAUSE L

Latch Data Out Register. .

separate
operation
SMCB.

RREQ (B) H,L

SMCA

REQ LATCH H

—_—
* RREQ (B) H - DONE L, SMCA

Latch RREQ (B) H

‘

Read data latched. SMCA, SMCE.

SMCA

Set DONE

"' PAUSE H - RREQ (B) L, SMCA

16.42

Set PE F/F

Direct set by SMCB SET PE L

if BAD PAR H remains

asserted at this time, SMCB.

PERF ACKN

YES

16.43
)

CPU response to a valid PERF (Step 16.31).

)

" Cloar Timing

16.36

Clear BUSY and . AH,BL,CH, D L and ACCESS READY LATCH

Cloar PAUSE

- PERF ACKN - BREQ IN PROG L (BREQ

IN PROG inhibits PERF ACKN from halting

16.44

a Unibus DATIP being executed in

{

the other M8110/M8120 module).

16.36

" RREQ(B) L + PAUSE H. (Flip-flop is direct

Set DONE

cleared after 30 nsec delay), SMCA.

that remained asserted from the DATIP, SMCA.

I
‘

Clear DONE

Flip-flop is cleared after 30 nsec delay, SMCA.

I REQLATCH PULSE L I ** RREQ (B) H - DONEL, SMCA.

[...J

16.45

Refresh Cycle

I Perform normal refresh cycle (Figure 3-17).

16.37

l
|

Set PE F/F
'

Direct
set by SMCB SET PE L

if BAD PAR H remains asserted

at this time, SMCB

16.38

Clear BUSY
Clear Timing

SMCA
Clear

AH,BL,CH,DL, REQ LATCH, and ACCESS READY

LATCH that remained asserted from the DATIP, SMCA. -

|
|

BUST ouT

CPU sends BUST OUT for DATO cycle, SMCA. [Write data and

control bits for DATO (UBCC MEM BUS CO L and
UBCC MEM BUS C1 L) already on Fastbus lines. SMCA, SMCD].

16.39

(tJ

No DATO Cycle 1 Since a PE was detected the CPU does not initiate the DATO. |

VES
Was refresh performed during the pause?

11-2183

16.48

ATO cycle

]

Perform normal DATO cycle (Figure 3-7).

' DONE cleared BUSY and timing signals (16.43).
°*

DATIP address still on Fastbus lines.

n-2189

Figure 3-10 Fastbus DATI-DATO Logic Flow (Sheet 3 of 4)

3-22

16.58

15
Latch both latdhes E28.

Byte Select

16.49

DATIP signals retained I
16.50

BUSY (1) H,AH,BL,CH,DH, CENABLE, ACCESS READY

DATO — OUT HIGH and OUT LOW. (DATOB — OUT HIGH or
I SMCA OUT HIGH, LOW I OUT
LOW as +termined by the state of MAD 00.)

LATCH and REQ LATCH remain asserted from the DATIP DONE was never asserted.

PREQ (1) L (below) " DONE never asserted during DATIP
16.59

(C138 never discharged). Previous address remains latched in the
MAD Register.

WRITE PULSE HIGH,

-16.51

LOW

REQ LATCHPULSE 2L I

Remains high from DATIP (Step 16.16) and is not asserted by

I REQ LATCH PULSE L I

' PREQ (B) H,|both D inputs are high, SMCA.

{

DATO - Both 'Bignals output concurrently. (DATOB — One signal

output as determined by MAD 00)
|

Remains high from DATIP (See remark at step 16.50), SMCA.

!
!

16.60
16.52

)

PREQ (B) H, L

]

Remains latched from DATIP - REQ LATCH never disabled, SMCA.

16.53

L DATA LATCHH

]

'Remains disabled (Step 16.19) from the DATIP. Data latches
open to write data. SMCB, SMCD.

Store Data

Write 16-bit word (DATOB = write 8-bit byte) MOSA through
MOSJ.

ADDRESS,
DATA

CPU drops signals in

MEMH, L

- ADDRESS, SMCA, SMCF

next time state 5

{

CONTROL OK

CPU drops signal in next time state 1, SMCB, SMCA.

Clear PREQ

Set PREQ

1 " BUST OUT L, SMCA.

MEM SYNC

" CONTROL QK, SMCA.

" CONTROL aK, SMCA.

16.55

CONTROL OK 1 Signal from CPU allows DATO cycle to continue, SMCA.
MEM SYNCH, L

16.62

I " CONTROL OK H, SMCA.

WP Delay

R13 adjusted to generate a 60 nsec write puise, SMCA.

WP H

Delay times out to terminate the write pulse, SMCA.
1

‘- WPH; terminate REQ LATCH, SMCA.

Set DONE

16.56

L MEM SYNC (B) L j Remains asserted from DATIP, SMCA.

(Prevents the CPU from stopping, i.e. doing a T2 Pause).

16.57

DATA LATCHH, L

SMCA

SMCB E44 pin 6.

Latch Write Data

Latch write data into Data In Register, SMCD.

Clear PAUSE

= DATA LATCH H asserts PAUSE L, SMCB.

16.63

MEM
MEM SYNC
SYNC (B)
(B) L

Clear BUSY

Clear Timing Signals

SMCA
BUSY (1) H

inatess

AH,BL,CH,D L, CENABLE L, and

ACCESS READY LATCH, SMCA.

16.64

I Direct reset ah+ 30 nsec delay, SMCA.

Clear DONE

11-2190

‘

STOP

,
11-2191

Figure 3-10 Fastbus DATI-DATO Logic Flow (Sheet 4 of 4)

3-23

75nsec

DESKEW —

BUS BUSY L

BUSB SSYNC L

150nsec —sf~_

DESKEW

BUS ADDRESS, C@,C1 LINES L

1)
(NOTE
BUSB DATA L

MSYNC L

[
=

SMCF BREQ L

SMCA BREQ (B)H

BUSB

['——

$ 12nsec DELAY -—-HZ‘—

SMCA REQ LATCH H

SMCA REQ LATCH PULSE 2 L

£65nsec

DONE L

I
|

SMCA BUSY (1) H

SMCA CENABLE L

SMCA B L

:
|

SMCA CH

SMCA PRECHARGE L

ec..wj'

' 80nsec
90nsec

SMCA ACCESS READY LATCHH

({

;!BREQ

BUSB SSYNCL

SMCB GATED

SMCB DATA LATCHH

REQ PULSE L

SMCA WRITE PULSE HIGH/LOW L

L
60nsec —:l____k——

30nsec AJZ_L—

SMCA DONE L

NOTE:

11-2630

C1 input inhibited until MSYN asserted.

s
i i

g
e
e e,
A

it
e

Figure 3-11 Unibus DATO Timing (Bipolar)

3-24

F'—BUST uSTATE '——':"PAUSE pSTATE-—'l‘_—'lUST # STATE

[ i_!__rg0ns
i

CPU TIME swrssfi

—

1
(L8

SEGMEN- | L——

MgN" —
h-sTEf
TION

DELAY |

TATION

| DELAY |

90ms |

W -————

ADDRESS LINES (H)

-2

(NEXT CYCLE)

TMCE BUST OUT L

—— et

- L

DATA LINES L
UBCA CONTROL OK H

NOTE 2

SMCF MEM L

SMCA PREQ (1) L

SMCA CENABLE L

SMCA CH

SMCA PRECHARGE L

80nsec |

i
-

[

o
2

nsec

i——

90nsec

SMCA ACCESS READY LATCHH
SMCA

) wigA BL

—

H
SMCA BUSY (1}

;65nsecd_é’

SMCA REQ LATCH PULSE 2L

/L_j

\In——aoo -330nsec

SMCA REQ LATCH L

|
|

|
L

30/60 nsec o

SMCA MEM SYNC (B) L

(NOTE 3)

CONTROL OK

AND SMCADH

SMCA MEM SYNC H

SMCB GATED

SMCB DATA LATCH H

REQ PULSE L

60nsec fl

SMCA WRITE PULSE HIGH/LOW L

30nsec

SMCA DONE L
NOTES:

1. CPU timing may stop in time state 5 for 30 nsec if MEM SYNC
is not stable on TIG board.’

2. CPU may send BEND CLEAR in place of CONTROL OK.
See Figure 3-7 (9.9, 9.15 and 9.20).

3. REV
F

REV
[

4. Adjust R42 for 300 to 330 nsec between cycles
(represented by dotted lines). Refer to Paragraph 4.3.2.2.

5. Cleared either by CONTROL OK or MEM L

60 nsec if M8109 jumper W5 out, W6 in.
30 nsec if M8109 jumper W5 in. W6 out.

60 nsec if flip-flop at E8 (M8109) not used.
30 nsec if flip-flop at E8 (M8109) has

11-3629

jumpers at pins 11 and 12.

Figure 3-12 Fastbus DATO Timing (Bipolar)

3-25

T75nsec

—~—

—-L

BUS ADDRESS, C@,C1 LINES L

BUSB SSYNC L

150nsec DESKEW \\

{

—

(NOTE 1)

—

BUSB MSYNC L

BUS BUSY L

t DESKEW

) l-\ SMCB MEM SSYNC L

SMCB MEM

BUSB DATA L

SSYNC L

SMCF BREQ L

)
\

___)

*12nsec DELAY

SMCA BREQ (B)H

SMCA REQ LATCH H
(NOTE 2)

SMCA REQ LATCH PULSE 2L

( DONE L

SMCA BUSY (1} H

SMCA BL

SMCA PRECHARGE L

-fi

SMCACH

! 90nsec( I—-‘Q

SMCA ACCESS READY LATCHH

BUSB SSYNC L

SMCA SA LATCH (1) H

SMCB GATED REQ PULSE

L—]

3
! NOTE
i

SMCA DONE L

BUSY (1)H—-—|:_

SMCB PAUSE H

NOTE:

. Ct input inhibited until MSYN asserted

2. Adjust R42 for 300 to 330nsec between cycles
using a prescribed program loop (Para 4.3.2.2.)
3. Not set on unibus DATI data transter.
See figure 3-8,10.18

11-3628

Figure 3-13 Unibus DATI Timing (Bipolar)

3-26

r—————BUST
|

pSTATE———le—PAUSE uSTATE—ele——

!
2

TIME STATES

90ns

sEoMEN-|

TATION |

90ns

—— 0

uSTATE

(NEXT CYCLE)
TM
[

Lt g

IL'
CPU

BUST

3
L——

s
SEGMEN-

TATION

L4
|

ADDRESS LINES H

——[

VALID

[

ADDRESS i

SMCE BUST OUT L

e e
d

UBCA CONTROL OK H

NOTE 2 |

SMCE MEM L

SMCA PREQ (1) L

@——300 330nsec

SMCA REQ LATCHL

SMCA REQ LATCH PULSE 2L

—»{ NOTE4

& 65 nsec

DONE L

SMCA BUSY (1)
H

r—q

)

[

r—d
|

C X W —-——-[ t

e
b o

SMCA PRECHARGE L

SMCACH

SMCA MEM SYNC L -+

SMCA SA LATCH (1) H

r..;-.

SMCB GATED REQ PULSE L

e cne
l

SMCA B L

90 nsec

SMCA ACCESS READY LATCHH

SMCADH

SMCA MEM SYNC (B) L

30760 nsec

(NOTE 3)

CONTROL OK /L

I\ \

AND SMCA DH

--"@
&——:L_L— 30nsec

SMCA DONE L
NOTES:

CPU timing may stop for 30 nsec in time state 5 if
MEM SYNC is not stable on TIG board.

CPU may send BEND CLEAR in place of CONTROL OK.

See Figure 3-7 (9.9, 9.15 and 9.20).

30 nsec if M8109 jumper WS in, W6 out.

REV | 60 nsec if flip flop at E8 (M8109) not used.

30 nsec if flip flop at E8 (M8109) has
jumpers at pins 11 and 12.

. Adjust R42 for 300 to 330 nsec between cycles
(represented by dotted lines). Refer to Paragraph 4.3.2.2.

n-3627

Cleared either by CONTROL OK or MEM L

Figure 3-14 Fastbus DATI Timing (Bipolar)

3-27

gt e

. REV [ 60 nsec if M8109 jumper WS out, W6 in.

e
D

SMCA PREQ (1)L —

FASTBUS DATA LINES

(SMCE MEM D<15:00>H)

SMCA BUSY (1) H—]

SMCA BUSY (1)H/43

SMCA CENABLE L

r--

SMCA MEM SYNC L

FASTBUS

ODATIP

<«— DATI |

+90nsec IF

DATO —»

SEGMENTATION
3

5 (NOTE1)

CENABLE‘% SMCE MEM D(15:00)H

_l (NOTE2) PDRB

]

——

e
s

!~—80nsec —fi \ _}— 60nsec

SMCA B L

SMCA C H

ewn
-

.
/

«—— 90nsec L

({

SMCA D H

UBCA CONTROL pK H

SMCB PA UESE H

30/60 nsec

(NOTE 3) |

}——— CONTROL OK

30 nsec if flip flop at E8 (M8109) has
jumpers at pins 11 and 12.

. CPU may send BEND CLEAR in place of CONTROL OK.
See Figure 3-7 (9.9, 9.15 and 9.20).
. SMCB PAUSE H is asserted by SMCA BUSY (1) H if Unibus DATIP.

|JnoTE
4)

NOTE 5,

M8109 jumper W5 out, W6 in.

30 nsec if M8108 jumper W5 in, W6 out.

REV | 60 nsec if flip flop at E8 (M8109) not used.
C

REV [ 60 nsec if
F

MEM SYNC

Data clocked into the BR.

TSR

BUSY (1)H —s|

SMCA SA LATCH (1) H

SMCB DATA LATCH H

cafie

SMCB GATED REQ PULSE L

SMCA MEM SYNC L

board

]

= 65nsec—o[

s ol w—

sMca BUSY (1) H

SMCA ACCESS READY LATCH

SMCA REQ LATCH PULSE2 L

SMCA CENABLE L

(E27) before time pulse T5).

ot
di o

SMCA PREQ(1) H

of the DATI

et
bty
Bl dind Rl

SMCA PRECHARGE L

Memory waits for CPU’s next T1, T3 (BUSTOUT) following completion

(a pause may not occur with Bipolar due to receipt of MEM SYNC (B) L at TIG

BR(15:00)B

o apenapueiy PRty

C1,CO0=10 (DATO)

{

SMCA REQ LATCH PULiSE L

NOTES:

C1,C0 =01 (DATIP)

SMCE MEM H

SMCA REQ LAT‘!CH H

——

9 ]

SMCE BUST OUT L

DATA LINES (H)

—

CO,C1 LINES (H)

ADDRESS LINES (H)

CPU TIMING PULSES (TP)

\:[

SMCA WRITE PULSE mGH/Lciw L

-60nse
3 YA

SMCA DONE L

30 nsec
11-3625

Figure 3-15 Fastbus DATIP-DATO Timing (Bipolar)

3-28

1je————BUST umSTATE

|
1
—

PAUSE uSTATE

**~

BUST uSTATE

1
i

'
|

1
L

1
»
A

CPU TIME STATESfi

| SEGMEN-

DELAY

180

nsec

TIMING PAUSE
(NOTE

L=
3

Em—

——-[

le-TATION- [ L_%
|
:

ADDRESS LINES (H)

_90ns

(NEXT CYCLE)

ADDRESS _

VALID

—

TMCE BUST OUT L

DATA LINES (L)

UBCA CONTROL OK H
Sl

SMOE MEM L

\I_

SMCA PREQ (1) L

SMCA REQ LATCH L
SMCA REQ LATCH PULSE 2L

K\l'

%;
DONE L

=~ 80nsec

SMCA BUSY (W H

SMCABL

SMCA CENABLE L

SMCA PRECHARGE L
SMCACH

}4——— 230nsec

SMCA ACCESS READY LATCH H

SMCA D H

!
je—— 210/240 nsec

SMCA MEM SYNC (B) L

(NOTE 3)

SMCA MEM SYNCH

SMCB GATED

SMCB DATA LATCH H

REQ PULSE L

60nsec

SMCA WRITE PULSE HIGH/LOW L

30nsec

SMCA DONE L
NOTES:

CPU timing may remain stopped for an additional 30 nsec if

MEM SYNC is not stable on the TIG board at the end of the
180 nsec delay.

See Figure 3-7 (9.9, 9.15 and 9.20).

3. REV

{240 nsec if M8109 jumper W5 out, W6 in.

F {210 nsec if M8109 jumper W5 in, W6 out.
REV [ 240 nsec if flip flop at E8 (M8109) not used.
jumpers at pins 11 and 12.

Figure 3-16 Fastbus DATO Timing (MOS)

3-29

1-3626

Table 3-5
MOS and Bipolar Memory Timing (M8110/M8120)

Assertion Time

.
.
Function or Signal

Measured

(nanoseconds)
Bipolar

MOS

From

SMCA REQ LATCH ?

SMCA PRECHARGE L {

Address Set-Up

SMCA PRECHARGE L

SMCA PRECHARGE L}

SMCA PRECHARGE L t

Access Time

230

SMCA PRECHARGE L {

SMCA ACCESS

READY LATCHH 1
MEM Sync

SMCA WRITE

30 or 60

210 or 240

(Note 1)

(Note 2)

SMCA PRECHARGE L |

(BYL{

PULSE HIGH L
NOTES:

SMCA MEM SYNC

SMCA WRITE PULSE

HIGH L

HIGH Lt

1. Refer to Note 3 on Figure 3-12.
2. Refer to Note 3 on Figure 3-16.

(1) H outputs from the parity register flip-flops are gated to the Unibus; 2) if a write (DATO) is decoded, the signal
SMCF PAR REG STB H is asserted. This signal clocks the parity register and new data is written into the parity

register flip-flops. Note that both these signals are inhibited, and consequently all parity functions are disabled, if
jumper B (E87) is in place. Access to the parity register can only be gained by cutting this jumper. As a result of
decoding the assigned parity register address, the parity register can either be read or written into. (The parity
register is not byte addressable.) The access cycle that accomplishes this reading or writing is the same as any other
Unibus access cycle except for the unique address.
The parity register address is assigned according to the starting address, i.c., the lowest address to which this M8110

responds. Table 3-6 shows the starting addresses, from 000000 through 7400003 in 8K increments because the
memory must be located on 8K boundaries in order to meet parity register addressing specifications. (This
restriction can be disregarded if MS11 parity functions are not enabled.) Thus, in a system configuration with no

local memory, 0000005 is the lowest Unibus address that the M8110/M8120 responds to and therefore the parity

address determination; it could consist of for example, 1K (minimum bipolar) or 16K (maximum MOS or bipolar)
memory locations and the parity register address would remain the same. Every parity memory unit on the Unibus is

assigned a unique parity register address. For example, address 7721003 would be assigned to a 12K (0-0577764)
local memory. If, in addition, a 16K MS11 were connected to the same Unibus, its assigned address range would be

from 16 to 32K (100000 — 177776g) in order to comply with the 8K boundary restriction. Accordingly, with a
starting address of 100000g, the assigned parity register address for the MS11 is 7721043. The same parity register

address would be used regardless of the MS11 memory size provided the starting Unibus address remains the same. If

a second M8110 module with additional memory (starting address = 2000003) were included in the MS11, its parity
register address would be 772110;.

The 13 most significant bits (17:05) of the parity register address are always decoded as 7721XXg. Two NAND

gates in the parity address decoding logic (drawing SMCF) decode bits (17:06); address bit 05 is input to a third
NAND gate in the same circuit. Four 8242 exclusive-NOR gates in the decoder determine address bits (04:01).
Inputs to these gates consist of four Unibus address bits, SMCH UBAD (04:01) H, three signals from the address

selection jumper network, SMCF DECODE (17:15) H, and a high or low input from jumper T(E87) in the parity
register address decoder. SMCH UBAD (04:02) H are exclusively ORed with SMCF DECODE (17:15) H to define

parity register address bits {04:02). Likewise SMCH UBAD 01 H is exclusively ORed with the jumper T output to

decode address bit O1. If this jumper is in place, bit 01 is a O; if it is cut, bit 01 is a 1. The 8242 gates in the parity

3-30

SMCH
DBAD

BUS
B
SSYNC L

SMCF PAR

(17:00)H
(NOTE)

SSYNC H

SMCH
UBDATA

UNIBUS

BUSB
|OOL

(NOTE)
(N

|SMCH
BUS
| SMCH
|UBDATA
[B
UB DATA
(NO
(NOTE)

BUSB
02 L

1L | SeoTe)
(NOT

MYSN ——|

(B)H

ADDRESS

DECODER

SMCF

SMCF|

‘

\es78

C1 20—

"\ OUT H

(READ)

l
| -~
.

SMCF

(17:15)H

DECODE

ADDRESS

SMCF

STBH

SELECTION

—40

(WRITE)

NOTE:

ia
;;:e::;:’%filfi
s

EIE

F/F

11—

—4D

—

F/F

SMCB

SMCB L (
SET PE

SMCB

(1) H

LATCH H

SMCE LOW BYTE PARL | PARITY |
||
CHECKER V' sMcE DATA OUT(I7:00L]
SMCE M BYTE PAR
-

SMCE LOW

BYTE PAR H
PAR H

'(wlg'[())O)L
'

1\)

SMC B STB

SMCD

SMCE HI BYTE PAR L

UBCD
PERF ACKN L

SMCD MEM DATA (15:00)H

MU
X

WWP

(NOTE)

PARITY

WRITE

PARITY

BITS

GENERATOR | smcD MEM DATA (17:16) H
SMCD

BCY
-——SA LATCH-DONE- __

sMcs

(RESET PAUSE F/F
IF SET)

DAA

wwe | |

SARITY

SMCBEIE(V)H

MEM SA
(15:00) H

g’g‘g‘-

SMCA|PREQ (B) H

|
*

(\SMCE

(NOTE)

\/
PARITY

3‘;‘3[;‘”
A
(15:00) H

SMCB
PERF L

FASTBUS

DATA

ouT
REGISTER

SMc

SMCE

BR (15:00)
BL

SMCE MEM SA (17:00) H
E

SMCE
MEM D

(15:00)H

,\/

11-2188

Figure 3-17 Parity Logic, Block Diagram

3-31

Table 3-6
Parity Register, Assigned Addresses

SMCF DECODE XX L

Jumper
E87 “T”

(Note 1)

Decimal

Assigned Parity
Register

Starting Unibus Address

Octal

Address

000000

772100

040000

16K

100000

772102
772104

24K

140000

772106

32K

200000

772110

40K

240000

48K

772112

300000

772114

56K

340000

772116

64K

400000

772120

72K

440000

772122

80K

500000

772124

88K

540000

772126

96K

600000

772130

104K

640000

772132

112K

700000

771134

120K

740000

772136

(Note 2)
NOTES:

1. Jumper IN = 0, Jumper OUT = 1.
.
2. Unibus address space 124—-128K is reserved for peripheral registers.

register address decoder operate in the same manner
as they do in the address decoder (Paragraph 3.2.1).
If both
inputs to a single gate are either high or low, the output
is high and one leg of the decoder is enabled. Therefor
e if a
jumper is in place (a low), the corresponding address
bit must be a 0 (also a low) to disable the 8242 gate
and
generate the necessary high output. Likewise, if
a jumper is cut, the resultant high input to the
8242 gate must be
accompanied with an address bit = 1 (high) in order to
disable the gate. A jumper in place decodes a 0 bit in the

address; an excluded jumper decodes a 1 bit. (Note that the polarity

Unibus line polarity; 1 bits are high and 0 bits are low.)

required before the register can be accessed. The master

and the output from jumper B (E87) must also be high

of the address bits at this point is opposite the

Two other inputs to the parity register address decoder

sync signal derivative, SMCH MSYNC (B) H, must be

(the jumper must be cut to enable parity functions).

are

high

Two outputs from the parity register address decoder,
SMCF PAR REG STB H and SMCH PAR REG OUT H,
are
described above. A third output, SMCF PAR SSYN H, is
asserted regardless of the bus cycle in effect. This signal
asserts BUSB SSYN L on the Unibus, thus acknowledging
acceptance of the request for access to the parity register.

3.2.7.2 Parity Register Address Set-up — It is easy to determin
e the parity register address since it is dependent on
the starting Unibus address for the memory. Bits (04:02)
of the parity register address are equal to bits (17:15)
of the
Unibus address. Jumper T is then cut or left in place
to decode parity register address bit 01 (jumper cut decodes
a
1; jumper left in place decodes a 0). The other
parity register address bits, (17:06), are fixed; they
are always
decoded as 7721XX. For example, if a 4K bipolar
memory uses the 72-76K memory space, the starting
Unibus
address is 4400005 . Therefore, the parity
register address is 772122 g

Starting Unibus Address

W 000,

Assigned Parity Register Address

Jll1 111 010 001 Q10 0]0

Fixed

3-32

Cut Jumper T

Ignored

3.2.7.3 Parity Register — This register consists of three 74H74 D-Type flip-flops shown on drawing SMCB: parity

error (PE), write wrong parity (WWP), and error indication enable (EIE). Table 3-7 lists their bit assignments and
functions.

Table 3-7

Parity Register Flip-Flops, Bit Identity and Function

Flip-Flop Name

Input Data

Output Data

EIE
(error indication
enable)

SMCH UB
DATA OO H

BUSBOO L

WWwP
(write wrong

SMCH UB
DATAO2 H

BUSB 02 L

SMCH UB
DATA 15 H

BUSB15L

Performed

Enables parity-initiated aborts
when set (SMCB PERF L);
disables when reset.

0dd (bad) parity is stored when
set; even (normal) parity when
reset.

parity)

PE
(parity error)

Parity/Diagnostic Function

Error flag, direct set upon
detection of a parity error by
SMCB SET PE L.

The EIE flip-flop is used to control the parity error checking function by allowing or inhibiting the parity error flag
(SMCB PERF L) to the Fastbus when an error is detected. When a word is read during a Fastbus DATI cycle, both
bytes are checked for even parity; either (or both) SMCE HI BYTE PAR H or SMCE LO BYTE PAR H is asserted if
odd parity is detected. If the EIE flip-flop is set, SMCB EIE (1) H gates the asserted parity error signal(s) to the
Fastbus as SMCB PERF L. This latter signal sets the processor parity error flag (Paragraph 3.2.7.5).

The signal SMCH UB DATA 00 H from the Unibus data receivers controls the state of the EIE flip-flop which is
clocked set or reset when a DATO is addressed to the parity register. The flip-flop output, SMCB EIE (1) H, is gated
to the Unibus as BUSB 00 L when a DATI or DATIP is directed to the parity register.

A check of the parity logic itself can be made by forcing a parity error when the memory is read. The write wrong

parity bit is used for this purpose. By generating incorrect (odd) parity when a byte or word is stored, it forces the
generation of a parity error when the same location is subsequently read. Failure of the parity logic would be
indicated if the error is not detected. The WWP flip-flop is set when clocked by SMCF PAR REG STB H and the D

input, SMCB UB DATA 02 H, is high. The (1) H output is then routed to the parity generator (drawing SMCD)
where it controls the parity mode. If SMCB WWP (1) H is high, the asserted parity is odd; if low, the parity is even
(Paragraph 3.2.7.4).

The PE flip-flop is used to record the fact that a Fastbus read parity error occurred; it serves no other function in the
MS11. When an error is detected (SMCE HI BYTE PAR L and/or SMCE LO BYTE PAR L are asserted), the flip-flop
is direct set by SMCB SET PE L. SMCB PERF L is also asserted to the Fastbus if the EIE flip-flop is in the set state
when the read error is detected. However, the two operations (set PE and assert PERF) are performed
independently. The PE flip-flop is set on detection of an error, regardless of the state of the EIE flip-flop, but EIE
must be set for a Fastbus error to assert SMCB PERF L. In addition to the direct set input, the PE flip-flop can be

set or cleared by Unibus data bit 15 when a DATO addresses the parity register. Normally, the flip-flop is direct set
on error detection and then reset (bit 15 is a 0) by the processor.

3.2.7.4 Parity Generator — The parity generator (drawing SMCD) provides one (DATOB) or two (DATO) parity bits
which are stored with the write data. These two bits, SMCD MEM DATA 16 H for the low byte and SMCD MEM
DATA 17 H for the high byte, are asserted to maintain either odd or even byte parity when data is written into

3-33

memory. Two 82862,9 input parity generator/parity checker chips and two 3404 latches make up the circuit. Each

82562 produces one of the two parity bits as necessary to maintain the desired parity; the state of SMCB WWP (1) H
determines whether the generated parity is odd or even. The (1) outputs from the 3404 latches follow the D inputs
during the time the L inputs are low (SMCB DATA LATCH H). They are then locked (i.e., not influenced by any
subsequent changes at the D inputs) when the latches are latched on the assertion of SMCB DATA LATCH H.

Normally, SMCB WWP (1) H is low and even parity data is stored. However, when SMCB WWP (1) H is high, the
generated parity is odd. The data is then read and the resultant bad parity indications (PE flip-flop set and SMCB
PERF L asserted) verify the reliability of the parity checking logic.

3.2.7.5 Parity Checking — The parity checker consists of two other 82862 chips (drawing SMCE) on the
M8110/M8120 module. Inputs to this circuit are the two 8-bit data bytes, SMCE DATA OUT (07:00) L and SMCE
DATA OUT (15:08) L, and their respective parity bits, SMCE DATA OUT 16 L and SMCE DATA OUT 17 L, from
the Data Out Register latches. Read data, as a result of both Fastbus DATI and DATIP cycles, is latched into the
Data Out Register. Unibus DATI/DATIP read data is not latched into these latches because SA LATCH is not set
during Unibus cycles (MEM SYNC is never asserted).

Each of the two 82562 chips checks a data byte and its parity bit for even parity. If an odd number of 1 bits is
found in either 9-bit data group, the respective bad parity indication signal, SMCE LOW BYTE PAR H (and L) or
SMCE HI BYTE PAR H (and L), is asserted. (Both signals are asserted if both bit groups are found to have bad
parity. However, the second error indication signal is redundant; the consequences of bad parity in one or both bytes
are the same.)

SMCE LOW BYTE PAR L or SMCE HI BYTE PAR L asserts SMCB BAD PAR H. This latter signal, in turn, asserts
SMCB SET PE L if bad parity exists at the conclusion of the memory cycle when the DONE flip-flop is set. SMCB
SET PE L direct sets the PE flip-flop in the parity register (Paragraph 3.2.7.3).
H and HI BYTE PAR H, serve
The parity error indication signals of the opposite polarity, SMCE LOW BYTE PAR
an additional function. The diagnostic program has two options available with respect to specifying processor action
when a Fastbus error is detected. If the EIE flip-flop is reset (Unibus data bit 00 = 0), all parity errors are ignored.
However, if EIE is set, the parity error flag (SMCB PERF L) is asserted to the processor, via the Fastbus, and a
processor abort is enabled; SMCB PERF L causes a trap to location 114. Parity errors on the Unibus are ignored.
SMCB PERF L is inhibited during a Unibus DATI cycle since SMCB STB PAR H, another requisite for the signal,
requires the assertion of both PREQ (1) H and UBCA CONTROL OK; neither of these signals are asserted during a

Unibus cycle. It should be noted that there are false assertions of PERF during the time CONTROL OK (and
therefore SMCB STB PAR H) is asserted. Initially, this is due to the absence of data in the parity checker, and later

to the presence of skewed data on the data lines from the memory module, i.e., at the input to the parity checker.
Erroneous assertions of SMCE LOW BYTE PAR H and/or SMCE HI BYTE PAR H result from these conditions.
Therefore, PERF will fluctuate during the period when CONTROL OK is asserted. The CPU checks for the presence
of PERF when it drops CONTROL OK. Consequently, PERF is a valid error indicator only when it is asserted at the
time CONTROL OK goes low.
3.2.8 Refresh Logic

The M8110 control contains refresh logic that charges each G401 MOS memory cell above the threshold of the data
stored there once every millisecond. (The M8120 also contains the same refresh logic. However, it is inoperative
since the M8120 is used only with M8111 and M8121 bipolar modules. Bipolar memory does not need to be
refreshed.)

3-34

A refresh cycle can occur under three different séts of operational conditions:
1.

Refresh cycle during normal access operation

Refresh/Cycle intervention during processor single-step instruction mode

Refresh cycle during power-down periods

Each of these conditions is described separately in the following paragraphs.
3.2.8.1 Normal Refresh Cycle — A normal refresh cycle (Figure 3-18) consists of simultaneously addressing one of
32 rows at each G401 MOS Memory Matrix module (drawing SMCB). Each row addressing cycle is timed by a 30 us
free running clock. This clock is formed by the RC network C140 and R62, which is base-collector coupled to the
NPN switching transistor Q1. The emitter of Q1 is coupled through three inverter stages and fed back to the base of
Q1. The 30 us square-wave output of the clock, SMCB REF CLOCK H, is taken off the output from the first
inverter stage as a30 us square wave. SMCB REF CLOCK H is a continuous clocking input to the REF REQ flip-flop.

The D input to this flip-flop is +3 V; therefore, when clocked, the output of this flip-flop is REF REQ (1) H a signal
with a 30 us repetition rate. REF REQ (1) H is gated with BIPOLAR L to assert REF REQ L.
NOTE

Jumper A (SMCB) must be cut for MOS memories. Therefore,

BIPOLAR L is always high for MOS memories and always low
for bipolar memories. The purpose of this level is to disable the
refresh cycle when an M8120 control is directing an M8111 or

M8121 Bipolar Memory Matrix module.

SMCB REF REQ L is input to a latch (E51) which asserts SMCA RREQ (B) H (drawing SMCA). SMCA RREQ (B) H
initiates an access cycle in the same manner as the Unibus or Fastbus, resulting in the assertion of SMCA REQ
LATCH PULSE L. SMCA REQ LATCH PULSE H is ANDed (SMCA) with SMCA RREQ (B) H to generate SMCA
RREQ ADDR EN L. This pulse multiplexes the current refresh address SMCB RFAD (04:00) H onto SMCC MAD

{07:03) to the memory plane (Table 3-4). Note that if an access cycle from the Unibus or Fastbus is underway,

coincident with one of the synchronous assertions of RREQ L, all subsequent assertions of PREQ L will be locked

out until the current access cycle is complete. This lock-out action is affected by SMCA REQ LATCH H, which is
asserted during all access cycles. SMCA REQ LATCH inhibits the output of the latching element responsible (ES1,
pin 4) for assertion of SMCA RREQ (B) L, SMCA RREQ (B) H, and SMCA RREQ IN PROG L.

When SMCA RREQ (B) L is generated, a 60 ns delay is initiated at the termination of which a logic low is produced
at SMCA E17, pin 6. This signal will inhibit any write pulse from NAND gates E27 (SMCA) when ACCESS READY

LATCH H is asserted at the end of the timing cycle. The REF REQ flip-flop is cleared (SMCB E127, pin 13) as the
result of its own outputs. SMCB REF REQ L (derived from REF REQ (1) H) raises SMCA RREQ (B) H which, in
turn, generates SMCA REQ LATCH PULSE H via SMCA E17, pin 9. This latter signal is ANDed (SMCB E128, pin 3)

with RREQ (B) H to clear the REF REQ flip-flop; SMCB REF REQ L is inhibited until the next REF CLOCK
signal.

The refresh address is output from a 5-stage binary counter, formed by a 4-bit synchronous binary counter (E129)
and a D flip-flop (E130), which forms the fifth and most significant stage. This 5-stage counter, shown on drawing
SMCB, is clocked by REF CLOCK H.

SMCA RREQ IN PROG L forces the memory gating control levels (MOSA A, B, C, and D) simultaneously high at
each 3207 TTL/MOS level shifting gate, so that as G401 module CENABLE AND PRECHARGE are asserted, these

levels are gated to every 1103 MSI memory circuit comprising each G401. In addition, the current 5-bit row address

SMCC MAD (07:03) (1) H is gated into the two address inputs to all G401 MOS memory modules at the same time.

3-35

SMCB REF CLOCK H

SMCB REF REQ (4) H

(

SMCB REF REQ

SMCA RREQ

(

)

{
)
{

’

| “

)

(B) H
}

SMCA EI7 PIN 6

SMCA REQ

:Q—SOnS—Ol

(INHIBIT WRITE PULSE HIGH/LOW)

LATCH H

SMCA BUSY (1) H

j/\)\

SMCA A H

SMCA B

SMCAC

|
[

SMCA PRECHARGE L

[

{

-—

9%ns

SMCA ACCESS READY
LATCH H

{

[
SMCA DONE L

{

)

|
§

SMCA CENABLE

30ns
11-1293

Figure 3-18 Normal MOS Refresh Cycle Timing

Therefore, with the coincidence of a given row address, SMCA CENABLE L, and SMCA PRECHARGE L, 32
corresponding data words are refreshed simultaneously in each 1024-word section of the four G401 MOS memory
modules for a total of 128 words per refresh cycle. When SMCA ACCESS READY LATCH H is asserted in the

refresh cycle, SMCA DONE L is asserted and the cycle is complete. The next refresh cycle will not start until the
next positive-going transition of SMCB REF CLOCK H.

3.2.8.2 Refresh Cycle Intervention During Single-Step Mode — During the single-step execution of processor
instructions resulting in a DATO or DATI from either the Unibus or Fastbus, it is possible that a given access cycle
could encompass two or more processor microstate (or machine) cycles. In such cases, the access cycle can be
initiated from the Unibus or Fastbus during one cycle, with address and data being propagated to the addressed
M8110 control on the next cycle. Because execution time of this next cycle in the single-step mode is dependent
upon human response, a long time could elapse between two such cycles. In order to maintain validity during these
periods, the refresh logic is structured to permit intervention in single-step-initiated access cycles to refresh data.
This intervention has no affect on the current access cycle.
In the normal refresh cycle, the REF REQ flip-flop is clocked on the positive-going edge of SMCB REF CLOCK H to
assert SMCB REF REQ (1) H and, thereby, start a refresh cycle. However, if after memory is selected there is a
single-step (mode) initiation of a Unibus or Fastbus access cycle, SMCA ACCESS READY LATCH will remain high
for longer than normal if the access cycle is split between two processor cycles. Consequently, DONE L is not
asserted for an inordinately long period and SMCA REQ LATCH H remains high. This latter signal locks up the 3404
latching element at E51, preventing SMCB REF REQ L from initiating a normal refresh cycle (Paragraph 3.2.8.1).
This characteristic of a memory access cycle in the single-step mode is detected at a logic circuit shown on drawing

3-36

SMCB. This structure is an integrating one-shot multivibrator formed by one element of a 75107 line receiver
(E125), combined with an external RC network made up of discrete resistors R20, R21, and capacitor C139. The
period of this one-shot is 15 us. When SMCB REF REQ L is asserted, this one-shot is triggered so that 15 us later, if

conditioned by SMCA ACCESS READY LATCH H, SMCB REF TIME OUT L becomes true. The effect of asserting
this level is as follows: when a refresh cycle is requested but not successfully completed within 15 us after SMCB
REF REQ L becomes true, the logic sequence for initiating a refresh cycle, regardless of memory state, is enabled.
When asserted, SMCB REF TIME OUT L activates the termination logic and SMCA DONE L is asserted. SMCA

DONE L then unlatches the 74S64 logic (E18) enabled by the current single-step mode access cycle and forces
SMCA REQ LATCH false. With SMCA REQ LATCH false, SMCB REF REQ L can change the state of the 3404
latching element at SMCA ES1 to assert SMCA RREQ (B) H, thereby enabling SMCA E17 and restarting a refresh
cycle.

Because activity in the single-step mode is based on a human, rather than machine, time reference, the state of an
access cycle is, for all practical effect, frozen. As a consequence, the approximately 450 ns refresh cycle is performed

on a cycle-steal basis with respect to the current access cycle. All control levels pertinent to the current single-step
mode access cycle remain asserted, so that upon completion of the subject refresh cycle, the addressed M8110
reverts to the state specified by that access cycle. In addition, completing the subject refresh cycle, results in
resetting the REF REQ flip-flop and disabling SMCB REF REQ L. At this point, the 15 us delay is terminated.

3.2.8.3 Refresh Cycle During Power-Down Periods — The free-running clock (SMCB E104) will continue to cycle
during power down situations and (30 us) REF CLOCK H signal production is maintained. Unless PWRS MEM DC
LO L is received (SMCH E37), +5 V will be present at the collector of Q1 and the clock generator will function as in
normal power-up periods. Response of the memory refresh logic to REF CLOCK H is the same as during the normal
refresh cycle (Paragraph 3.2.8.1 and Figure 3-18).

3.3 M8121 BIPOLAR MEMORY MATRIX MODULE LOGIC

The maximum storage capability of an M8121-YA Bipolar Memory Matrix module is formed by 72 fully decoded,
random-access, 1024-bit bipolar TTL memory integrated circuits, all interconnected to form a 4096-word X 18-bit
memory (Figure 3-19). Each memory chip is organized as 1024 1-bit words. Therefore, eighteen ICs comprise a 1024
X 18-bit memory, and four rows of 1024 X 18 bits provide the 4K capacity.
A16-bit (no parity) version of the M8121-YA is not manufactured.

The M8121-YA module logic functionally divides into two sections, as shown in the drawings for the matrix control
BIPA and BIPB, and the memory matrix proper, BIPC, BIPD, BIPE, BIPF, BIPH, BIPJ, BIPK, and BIPL. The
description of the detailed logic which follows is based on this functional division.
3.3.1 Memory Matrix Control

The BIPA and BIPB matrix control logic performs four basic functions with respect to the memory matrix portion
of an M8121 module. First, address lines from the M8120 control are buffered to provide the fanout necessary to
address the bipolar memory circuits. Second, DATA lines from the M8120 control are buffered before being input
to the memory matrix, with accompanying write pulses being buffered for necessary fanout. Third, address bits

MAD (14:13) (equivalent to Fastbus or Unibus address bits (14:13)) are decoded to enable the specific 4096-word
module out of the four 4096-word bipolar modules directed by the M8120 control (Figure 2-8). Fourth, CENABLE
from the M8120 and MAD (11:10), equivalent to Fastbus or Unibus address bits (12:11), are decoded to enable the
1024-word section at the selected module containing the addressed location.

3.3.1.1 Address Buffer — The M8121 address buffer (drawing BIPA) is a 10-stage parallel buffer which expands each
of the ten address lines MAD (09:01) and MAD 12 into four separate lines per bit, thereby providing necessary

fanout to the matrix. For each address line input to the buffer from the M8120 control, four lines are output to the
memory matrix, one line for each 1024-word row of a 4096-word bipolar memory module. Each stage consists of an
input inversion stage (one element of a 74504 hex inverter) and two 74540 dual 4-input buffer NAND gates (shown

3-37

M8120

M8120 CONTROL

CONTROL

WRITE DATA (SMCD MEM DATA <17:00> H)

SMCC MAD <14:01>

MAD <12, 09:01>

DATA BUFFERING

MEM DATA <17:00> H

S0P —»

B8IPB

Ll
D
TTTTTTIT
17 15 14 13 12 11 10 09 08 16 O7 06 05 04 03 02 01 00
by by e bbb
bbb
1

WR HIB —

1st 1024 LOCATIONS (ROW @)

+— WR LOB

e—Cs!

;

cSt—s

e— WR LOB

2nd 1024 LOCATIONS (ROW 1)

WR HIB —»

ADDRESS
EXPANDER

Be— ADS SEL

ca—l]i-10

BIPA

e— CS2

]

cs2 —»

pe]

g81pPE [+—ADS SEL 1-108B

BIPF |

ADS SEL 1-10B —

e—C5¢

gIpc [« ADS SEL 1-10A

81PD E

ADS SEL 1-10A —w

o
os?

ADS ser?-zalg::

3 '0.24;?:‘??0% (Row2)

BIPH ::ADS SEL 1-18C

MAD <14,13,11,10>]

WR HIB —;
ADS SEL 1-10D —&

(ROW 3)
LOCATIONS
41h 1024 BipL
|

e— WR LOB 1-10D

LOW/HIGH

WR LOB

cS3—»

e— CS3

WRITE PULSE

B1pK [+ ADS SEL

I_CF_NABLE

TTI
T T
[TT10TTT
09 08 16 O7 06 05 04 03 02 01 00
bd bbb e bbb v bbb bbb

17 15 14 13 12 11

READ DATA (SMCE MEM SA <17:00>H)

BROENBLI

cSg +—

ROW 8

MODULE.

CS1e—{CHIP

cs2 «—]SELECT

CS3 a——

B'PB

WR LOB

M8120

WR HiB <

CONTROL

11-3633

Figure 3-19 M8121 4K Bipolar Memory Matrix, Block Diagram

as negative input OR gates). All four buffer gates in each buffer stage are inhibited at three inputs by a common line
to approximately +3.5 V in a voltage divider (drawing BIPA). The enabling input to the buffer is the inverted address
so that the polarity of the expanded output address matches that of the input address. The expanded addresses
connect to a corresponding 1024-word section of M8121 bipolar memory as shown in Table 3-8.
Table 3-8
Expanded M8121 Memory Address Allocation

Expanded Addresses

Memory Area Addressed

BIPA ADRS SEL(10A:1A)

0 to 1023,

BIPA ADRS SEL(10B:1B)

BIPA ADRS SEL(10C:1C)

2048 to 30714

BIPA ADRS SEL<10D:1D)

3072 to 4095 5,

3.3.1.2 Data Buffering and Write Pulse Fanout Logic — Input to the data buffering logic consists of the DATO lines
from the M8120 control SMCD MEM DATA (17:00) H (drawing BIPB). This 18-stage circuit, formed by five triple
element 74811 AND gates, buffers the non-inverted data lines to the bipolar memory matrix. Note, however, that
the DATI (sense) lines from the M8121 bipolar module to the M8120 control are propagated directly from each
memory circuit sense line, SMCE MEM SA (17:00) H, as shown on drawings BIPC through BIPL. Each of the 18
sense lines in a 1024-word section is wire-ORed (to the M8120 control) with the same lines from the other three
1024-word sections.

3-38

The two write-enabling pulses that can be asserted at the M8121 module (BIPB) during a DATO are SMCA WRITE

PULSE LO L and WRITE PULSE HI L, which enable writing of low-order and/or high-order bytes, respectively, at
the addressed location. If a full 18-bit word is being written, both levels will be asserted simultaneously. Each write
pulse is buffered in parallel by two identical buffer networks to provide the necessary fanout capability. For
example, SMCA WRITE PULSE LO L, when asserted, is first inverted by one stage of a 74504 hex inverter. The
inverter output then enables one gate in two 74540 NAND buffers (E6 and E7). With SMCA WRITE PULSE LO L
asserted, the buffer gate outputs are BIPB WR LOB A L and BIPB WR LOB B L. When SMCA WRITE PULSE HI L
is asserted, BIPB WR HIB A L and BIPB WR HIB B L are asserted. BIPB WR LOB A L and BIPB WR LOB B L
enable writing a low-order byte and BIPB WR HIB A L and BIPB WR HIB B L enable writing a high-order byte.
When all four pulses are asserted simultaneously, a full 18-bit word is stored at the addressed location.

3.3.1.3 Address Examination Logic — The M8121 Bipolar Memory Matrix module decodes Unibus or Fastbus
address bits (14:11) (drawing BIPB). The relationship of address bits to MAD register bits is shown in Table 3-9.
Table 3-9

Address Bit to MAD Bit Translation (M8121)

Fastbus or Unibus Address Bit

MAD Register Bit

ADR 14

MAD 14

ADR 13
ADR 12
ADR I

MAD 13
MAD 11
MAD 10

MAD register bits 14 and 13, in both states at switch S1, MAD (11:10) (1) H, and chip select signal SMCA
CENABLE are input to four 74540 NAND gates, E3 and E4 (BIPB). Unibus or Fastbus address bits (14:11) place a
given address within a unique 1K section of a 16K group of addresses. (Unibus or Fastbus address bits (17:15) select
the 16K address group out of the total 128K address space. Refer to Table 3-1 and Figure 2-8).The selection of this
1K section of addresses is determined by the position of the four switches in S1 (MAD bits {14:13)) and the high or

low state of MAD bits (11:10). Table 3-10 lists the switches that must be closed along with the Unibus/Fastbus
address configuration that are necessary to access a 1K address section on the 4K M8121 module. For example, if S1
switches B and C are closed (A and D must then be open), then the 4K address area XX4096 through XX8191 is

assigned to this M8121 module. If a Unibus or Fastbus address is within this range, e.g., MAD 14=0,MAD 13 =1,
MAD 11 =1, and MAD 10 = 1, then the 1K section of memory XX7168 through XX8191 will be accessed.

The outputs of the four 74540 NAND gates (E3 and E4) are BIPB CS(3:0)L. Each output drives one (1K) row of
memory chips.

The discrete location in the selected 1K row is determined by BIPA ADRS SEL (10:00) that is derived from SMCA

MAD (12,09:01) H (Figure 2-8).
3.3.2 Bipolar Matrix

The 4096-word bipolar storage matrix contained on the M8121 memory module is organized as four rows with 1024
words in each row. Each of these four rows is made up of 1024 18-bit words. A bipolar matrix including parity, is
formed by 72 memory circuits. Each of the circuits in a given 1024-word row is enabled by a unique enabling level
as shown in Table 3-10. In addition to the 1024 X 1-word storage capacity, each memory circuit contains integral

write and sense amplifiers so that data is written directly into, or read directly from, each circuit in the matrix as
addressed. If the current memory access cycle is a DATO, the M8120 control would, following assertion of SMCA
CENABLE L, assert one or both of the pulses SMCA WRITE PULSE LO L and SMCA WRITE PULSE HI L,
depending upon whether a byte or a full word is being written. At this point in a DATO, the specific memory

location is addressed, and the data to be written is present so that assertion of WR LOB AL and WR LOB B L
and/or WR HIB A L and WR HIB B L will enable the write amplifiers on the memory circuits addressed.

3-39

Table 3-10
M8121 Bipolar Matrix Selected Address Configuration (1 of 16K)

Unibus/Fastbus
14 l

13 [ 12 I

Memory

| S1 Switches Closed

(Denoted by X)

MAD
14(

|11

|10

| A|

B | C

Address

Chip Select

Assignment

Signal Asserted

(Within Any 16K

(Enabling Level)

D | Block of Memory)

X | O0to 1023

BIPB CSOL

OO0

X |

1024 to 2047

BIPB CSIL

X | 2048 to 3071

BIPB CS2L

X | 3072 to 4095

BIPB CS3L

4096 to 5119

BIPB CSOL

X | X

5120 to 6143

BIPB CSIL

X | X

6144 to 7167

BIPB CS2L

7168 to 8191

BIPB CS3L

| X

X | X

X | 8192t09215

BIPB CSOL

X | 9216to0 10,239

BIPB CSIL

X | 10,240t0 11,263

BIPB CS2L

X |

| X

11,264 to 12,287

BIPB CS3L

12,288 to 13,311

BIPB CSOL

13,312 to 14,335

BIPB CSIL

14,336 to 15,359

BIPB CS2L

15,360 to 16,383

BIPB CS3L

If the current memory access operation is a DATI, the action of addressing a given location enables the memory

circuits comprising that location and places the data stored in the addressed location on lines MEM SA (17:00) to the

M8120 control.
3.4 M8111 BIPOLAR MEMORY MATRIX MODULE LOGIC
The maximum storage capability of an M8111-YA Bipolar Memory Matrix module is formed by 72 fully decoded,

random-access, 256-bit bipolar TTL memory integrated circuits, interconnected to form a 1024-word X 18-bit

memory (Figure 3-20). Each memory chip is organized as 256 1-bit words. Therefore, eighteen ICs comprise a 256 X
18-bit memory, and four rows of 256 X 18 bits provide the 1K capacity.

The M8111 Bipolar Memory Matrix module is identical to the M8111-YA in every respect, except that the memory
word is 16 bits without byte parity. Therefore, the maximum memory capacity of an M8111 is formed by 64
memory circuits.

The module logic functionally divides into two sections, as shown in the drawings for the matrix control BIPA and
BIPB, and the memory matrix proper, BIPC, BIPD, BIPE, BIPF, BIPH, BIPJ, BIPK, and BIPL. The description of the

detailed logic which follows is based on this functional division; it is applicable to both the M8111 and M8111-YA
modules.
3.4.1 Memory Matrix Control
The BIPA and BIPB matrix control logic performs five basic functions with respect to the memory matrix portion of

an M8111 module. First, address lines from the M8120 control are buffered to provide the fanout necessary to
address the bipolar memory circuits. Second, DATA lines from the M8120 control are inverted providing the proper

3-40

M8120 CONTROL

WRITE DATA (SMCD MEM DATA <17:00> H)

SMCC MAD <14:01>

~
DATA

MAD <12,10:01>

INVERSION

MEM DATA <17:00> L

81PB

10 09

NN
08 O7 06 05 04 03

02 O1

IFADDRESS
Cap

l«— CS1 RO

151 256 LOCATIONS

il §§§ :0

Rz R2

2nd 256 L:OCATIONS

BIPD |

BIPC fe— ADS SEL 1-8a

BIPF |

e— CS1 R

— g:g g‘
BIPE fe— ADS SEL 1-88

;

2
3

le— CS1

o R2

EXPANDER

|row sececTioN
s

B A‘Dsl iLia —
ABCD

Dl g:i 22
BI1PH le— ADS SEL 1-8C

e— CS1 R3

WRITE PULSE

4th 256 LOCATIONS
|
BIPL |

+—
CSZR3
e— CS3 D
BIPK fe— ADS SEL 1-8D

LOW/HIGH
I‘CENABLE

l‘ RN
16

3rd 256 LOCATIONS
BIPY I

10 09

08 O7 06 05 04 03 02 Of

READ DATA (SMCE MEM SA <17:00>H)

Mo <19.13. 112

cromne wooute
||
sire|

{

M8120
CONTROL

WR EN
LO/HI
11-132%

Figure 3-20

MS8111 1K Bipolar Memory Matrix, Block Diagram

logic level polarity to the memory matrix, with accompanying write pulses being buffered for necessary fanout.

Third, address bits MAD (14:13) and (11:10) (equivalent to Fastbus or Unibus address bits {14:11)) are decoded to
enable the specific 1024-word matrix out of the four 1024-word bipolar modules directed by the M8120 control
(Figure 2-9). Fourth, CENABLE from the M8120 is buffered to provide required fanout. Fifth, MAD (09:08) are
decoded to enable the 256-word section at the selected module containing the addressed location.

3.4.1.1 Address Buffer — The M8111 address buffer (drawing BIPA) is an 8-stage parallel buffer which expands each
of the eight address lines MAD (07:01)> and MAD 12 into four separate lines per bit, thereby providing necessary
fanout to the matrix. For each address line input to the buffer from the M8120 control, four lines are output to the

memory matrix, one line for each 256-word section of a 1024-word bipolar memory module. Each stage consists of
an input inversion stage (one element of a 74S04 hex inverter) and two 74S40 dual 4-input buffer NAND gates
(shown as negative input AND gates). All four buffer gates in each buffer stage are conditioned at three inputs by a
common line to +3V (drawing BIPA). The enabling input to the buffer is the inverted address so that the polarity

of the expanded output address matches that of the input address. The expanded addresses connect to a
corresponding 256-word section of M8111 bipolar memory as shown in Table 3-11.

341

Table 3-11
Expanded M8111 Memory Address Allocation
Expanded Addresses

Memory Area Addressed

BIPA ADRS SEL (8A:1A)

0 to 25510

BIPA ADRS SEL(8B:1B)

256 to 5114,

BIPA ADRS SEL(8C:1C)

512 to 767

BIPA ADRS SEL (8D:1D)

768 to 1023,

3.4.1.2 Data Inversion and Write Pulse Fanout Logic — Input to the data inversion logic are the DATA lines from
the M8120 control SMCD MEM DATA (17:00) H (drawing BIPB). This 18-stage inversion logic, formed by four

74804 hex inverters, drives inverted data lines to the bipolar memory matrix. Note that DATI (sense) lines from the
M8111 bipolar module to the M8120 controls are propagated directly from each memory circuit as MEM SA (17:00)
H. Each sense line in a 256-word section is wire-ORed (to the M81110 control) with the same lines from the other
three 256-word sections.
The two write-enabling pulses that can be asserted at the M8111 module (BIPB) during a DATO are SMCA WRITE

PULSE LOW L and WRITE PULSE HIGH L, which enable writing of low-order and/or high-order bytes,
respectively, in the addressed location. If a full

16-bit word is being written, both levels will be asserted

simultaneously. Each write pulse is buffered in parallel by two identical buffer networks to provide the necessary
fanout capability. For example, SMCA WRITE PULSE LOW L, when asserted, is first inverted by one stage of a
74504 hex inverter. Inverter output then enables both gates of a 74540 NAND buffer (E13). With SMCA WRITE
PULSE LOW L asserted, buffer gate outputs are BIPB WR EN LO A L and BIPB WR EN LO B L. When WRITE

PULSE HIGH L is asserted, BIPB WR EN HI A L and BIPB WR EN HI B L are asserted. BIPB WR EN LO A and
BIPB WR EN LO B enable writing a low-order byte and BIPB WR EN HI A and BIPB WR EN HI B enable writing a
high-order byte. When all four pulses are asserted simultaneously, writing a full word at the addressed location is

enabled.

3.4.1.3 Address Examination Logic — The M8111

Bipolar Memory Matrix module decodes Unibus or Fastbus

address bits (14:11) (drawing BIPB). The relationship of address bits to MAD register bits is shown in Table 3-12.
Table 3-12

Address Bit to MAD Bit Translation (M8111)
Fastbus or Unibus Address Bit

MAD Register Bit

ADR 14

MAD 14

ADR 13

MAD 13

ADR 12

MAD 11

ADR 11

MAD 10

ADR 10

MAD 09

ADR 09

MAD 08

MAD register bits 14 and 13 in both states, along with MAD 11 (1) H, are jumpered at BIPB for input to a triple
3-input NAND gate, E8. Unibus or Fastbus address bits (14:11) serve to place a given address within a 16K set of

addresses. Therefore, the selective jumpering of these address bit inputs at an M8111 memory module can designate
that memory module as having a unique 1K set of consecutive addresses within the total set of 16K addresses. Table

3-42

3-13 lists jumper connections and corresponding address set selected by each connection configuration, along with
the (MAD) address bit configuration necessary to access the module. For example, if jumpers D, E, J, and A are
installed, the memory module is assigned addresses XX7168 through XX8191. Then a Fastbus or Unibus address
within this range (MAD 14 = 0, MAD 13 = 1, MAD 11 = 1, and MAD 10 = 1) will cause this memory module to
'respond.

Table 3-13

M8111 Bipolar Matrix Selected Address Configuration (1 of 16K)

UNIBUS

Memory

Address

Required Jumpers

||n|n

Assignment

MAD

41131

(Within Any 16K

11]10 | (MAD14) | (MAD13) | (MAD11) | (MAD10) | Block of Memory)

o{oj|O0
0
0
0
1
0
0
|
0
0
0
1
0
0
|
0
1
1
0
|
1
0
0
0
1
0
0
1
1
0
|
1
0
1
0
1
1
0
1
1
1
|
1
1
1
1

0O
1
0
1
0
1
0
|
0
1
0
1
0
1
0
1

D
D
D
D
D
D
D
D
C
C
C
C
C
C
C
C

H
H
J
J
H
H
J
J
H
H
J
J
H
H
J
J

F
F
F
F
E

E
E
E
F
F
F
F
E
E
E
E

B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A

0 to 1023
1024 to 2047
2048 to 3071
3072 to 4095
4096 to 5119
5120 to 6143
6144 to 7167
7168 to 8191
8192 to 9215
9216 to 10,239
10,240 to 11,263
11,264 to 12,287
12,288 to 13,311
13,312 to 14,335
14,336 to 15,359
15,360 to 16,383

Fastbus or Unibus address bits (10:09) are translated by the M8120 control, as shown in Table 3-12, as MAD

(09:08). The states of these address bits designate which 256-word section of the 1024-word matrix contains the

location being addressed. These bits are received at each M8111 module and inverter-buffered by two parallel,
dual-stage inverter networks to assert the corresponding levels BIPA A 09 L, BIPA A 09 H, BIPA A 10 L, and BIPA
A 10 H. These levels are then input to an 8-stage logic network formed by four dual power gate units: E6, E7,El4,
and E15. This network is conditioned by the four state combinations of BIPA (A 10:A09) and +3 V. The network is
enabled when the level BIPB BRD ENBL and the appropriate state of MAD 10 are assertcd as a consequence of
address decoding. Enabled output from this network consists of one of four pairs of enabling levels being true, as
listed in Table 3-14, to enable the 256-word section of bipolar memory being addressed. These enabling levels are
low when asserted and constitute two of the three required chip-select inputs. The third chip-select input is
generated by SMCA CENABLE L from the M8120 control. This signal is received by E9 on BIPB that drives four

gates (E4 and E5) in parallel to provide the required fanout. The outputs are BIPB CS3 (A, B, C, D) L. Each set of
chip-select signals, e.g., BIPA CS1 RO L, BIPA CS2 RO L, and BIPB CS3 A L, drives one row of memory chips.

343

Table 3-14
Address Decoding for Memory Circuit Enabling

BIPA A10

BIPA A09

(MAD 09)

(MAD 08)

Enabling Levels

Memory Locations Selected

BIPACSIROL

0-255 (Row 0)

BIPACS2 RO L
0

BIPACSIRI L

256511 (Row 1)

‘BIPACS2R1L
1

BIPACSIR2L

512—767 (Row 2)

BIPACS2 R2 L

BIPACSI R3 L

768—1023 (Row 3)

BIPACS2 R3 L

Using the example given above, further definition of the memory location within the 1K memory block (addresses

XX7168 through XX8191) is effected using the states of MAD 08 and MAD 09. If MAD 08 = 1 and MAD 09 =0,
then the respective BIPA A09 and BIPA A10 signals generate BIPA CS1 R1L and BIPA CS2 R1L. These signals,
together with CENABLE generated BIPB CS3 .BL, will address the second 256 group of locations within the 1K
block, i.e., locations XX7424 through XX7679. MAD 12 (7:1) (BIPA ADRS SEL (8:1)) select the discrete location
from this 256 location group.

3.4.2 Bipolar Matrix

The 1024-word bipolar storage matrix contained on the M8111 memory module is organized as four rows with 256
words in each row. If the module is equipped for parity, each of these four rows is made up of 256 18-bit words. If

the module is not equipped for parity, each row is made up of 16-bit words. A bipolar matrix with parity is formed
by 72 memory circuits; a non-parity matrix is formed by 64 memory circuits. Each of the circuits in a given

256-word row is enabled by a unique set of enabling levels as shown in Table 3-14, in coincidence with BIPB BRD
ENBL H. In addition to the 256 X 1-word storage capacity, each memory circuit contains integral write and sense

amplifiers so that data is written directly into, or read directly from, each circuit in the matrix as addressed. If the

current memory access cycle is a DATO, the M8120 control would, following assertion of SMCA CENABLE L,
assert one or both of the pulses SMCA WRITE PULSE LOW L and SMCA WRITE PULSE HIGH L, depending upon
whether a byte or a full word is being written. At this point in DATO, the specific memory location is addressed,

and the data to be written is present so that assertion of WR EN LO A L/WR EN LO B L, and/or WR EN HI A
L/WR EN HI B L will enable the write amplifiers on the memory circuits addressed.
If the current memory access operation is a DATI, the action of addressing a given location enables the memory

circuits comprising that location and places the data stored in the addressed location on lines MEM SA (17:00) to the
M8120 control.

3.5 G401 MOS MEMORY MATRIX MODULE LOGIC
The memory capacity of the G401 is formed by seventy-two 1103-type fully decoded, random-access, 1024 X 1-bit
dynamic memory circuits. These 4096-word memories are directly addressed on the basis of 1024 18-bit words
(Figure 3-21). The specific set of 1024 words addressed is determined by the states of MAD register bits 01 and 02.
The states of these bits, asserted as MAD 01 (1) H and MAD 01 (1) H on drawing MOSA, are decoded to enable the
control levels CENABLE and PRECHARGE to the specific set of 1024 words to be addressed for a DATO or DATI.

The result of MAD 01 (1) H and MAD 02 (1) H decoding is a set of gating control levels designated MOSA A H,
MOSA B H, MOSA C H, and MOSA D H.

I1stK —»
— —

B ——

8 —»

B ——l

B ——
MOSH

cC —»

2nd K

8 —t»
MOSE

MOSC

S:L D:L

S{L DIL

S:L DIL

3rd K —»

3rd K

MOSA A —»

MAD <14, 13,02,01>

MOSA 4—-

B ——f

*— 2nd K

C —f

MOSA

SIL Di_

MOSA

*«— 3rd K

c —»

MOSA A —

D ——

41h K

cC —»
MOSJ

1[r 15 14 1'3 1'2

D —

F———
-K

MOSA A —

D ——

4th K

c —f
MOSF

D —#

1'1 1|o ole c!e

Y1l

FP—— —"

D ——

SEL 13 =

MOSA M«S —

0 —

SEL 14 *+—

<— 4th K

¢ —»
MOSD

16 O7 06 05
P4

b4y

8 -—

C «—

READ DATA (SMCE MEM SENSE AMPS <17:00>)

D —»

MOS8
o

4th K —»

————— K

PROG

o B

—(

RREQ

N\
ACCESS
CONTROL
LEVELS

)

- —_——

D —¥

1 B I R

B] —ll

C —»

MAD <12:03>

- {8t K

_____ <

MOSA A —

2nd K

‘

~—
Q —

1st K

—Q —

1st K

—
Q —

C —»

1so7osols

o — .4<

MOSA A —

2nd K —»

1111loolsoe

O —
-—
G—

51141312

__J*

bMCC MAD <14:01> J

— Q—

MOSA A —»

WRITE DATA (SMCD MEM DATA <17:00>)

o—
@ —

M8110 CONTROL

e—
O —.
H

M8110 CONTROL

M8110 CONTROL
11-1324

Figure 3-21 G401 4K MOS Memory Matrix, Block Diagram

3-45

o
g
e
e
i,
s
et
e
e

Decoding of MAD 01 (1) H and MAD 02 (1) H is performed by the logic shown on drawing MOSA. This logic is
enabled by the states of address bits MAD 13 and MAD 14, that specify which of the four G401 MOS memory
modules directed by a given control (Figure 2-10) is being addressed. The states of MAD 13 and MAD 14 are
uniquely jumper-connected at each G401 module to condition the gating of control levels MOSA A H, B H, C H, and
D H only at the memory module addressed. The states of MAD (14:13), as jumpered, also assert levels MOSA SEL
13 H and MOSA SEL 14 H to enable the G401 read amplifiers at the addressed memory module in case the current
access cycle is a DATI.

Table 3-15 lists the required jumper configuration for the assignment of the associated 4K block of MOS memory

addresses, while Table 3-16 indicates the control levels generated, and the 1K memory block selected, from MAD 01

and MAD 02. Control levels MOSA A, MOSA B, MOSA C, and MOSA D gate SMCA PRECHARGE, SMCA
CENABLE, and WRITE PULSE HIGH/LOW to access one of four sets of 1024 words. For example, if a G401 MOS
matrix has jumpers C and B installed, then that matrix contains memory locations XX4096 through XX8191.(Since
there are 131,072(10) possible addresses, XX equals 00 to 13. As described in Paragraph 3.2.1, Fastbus/Unibus
address decoder bits (17:15) determine these higher range address assignments.) Any address, directed to this
memory module, where MAD 14 is a 0 and MAD 13 is a 1 will cause the matrix to recognize and respond to the
address. Further definition of the same address is made by the MAD 01 and MAD 02 configuration. f MAD 02 isa 1
and MAD 01 is a 0, then control levels MOSA D and MOSA A are generated. As indicated by Table 3-16, these two
control levels will select the third 1K memory segment, in this case locations XX6144 through XX7167.
Table 3-15

MOS Matrix Selected Address Configuration (4 of 16K)
MOS Matrix Memory

Required Jumpers

MAD

(MAD 14)

(MAD 13)

Address Assignment

0
0
1
|

0
|
0
|

C
C
D
D

A
B
A
B

0—4095
4096—8191
8192—-12,287
12,288—16,383

Table 3-16

MOS Matrix Control Level Generation and Selected Memory

Address Block (1 of 4K)

MAD

Control Levels Generated

Memory Address

(MAD 02)

(MAD 01)

Block Selected

0
0
|

0
1
0

MOSA B
MOSA B
MOSA D

MOSA A
MOSA C
MOSA A

0-1023
1024—-2047
2048-3071

MOSAD

MOSA C

- 3072-4095

The discrete location in the 1K block of addresses is determined by A(12:03), for the low byte, and B(12:03) for the
high byte. These G401 add ress bits are derived from the M8110 address bits SMCC MAD (12:03) (1) H (Figure

2-10).

3.5.1 MOS Memory Writing

Address lines MAD (12:03) (drawings MOSA through MOSJ) are input to the MOS memory module and enable a
level-shifting NAND gate structure formed by 3-input 3207 type level shifters. Outputs are the MOS levels +1 V and

+19 V, so that a +3 V TTL input is level-shifted to +1 V, and TTL ground input is level-shifted to +19 V. Each gate
output is propagated through a series-damping resistor to the corresponding 1103 type MOS memory circuit address
input terminal. The access control levels PRECHARGE, CENABLE, WRITE PULSE HIGH, and/or WRITE PULSE
LOW are also input to this level-shifting NAND gate structure and are propagated to the corresponding 1103 input
terminals in the same manner. The use of damping resistors at the gate output effectively eliminates any potential
ringing problems.

As shown on drawings MOSA through MOSJ, the level-shifting NAND gate structure is configured to form two
duplicate level-shifting gate structures: one to access the low-order byte and one to access the high-order byte. The
only logical difference in these duplicate structures is that WRITE PULSE LOW H conditions the structure accessing
the low-order byte, and WRITE PULSE HIGH H conditions the structure accessing the high-order byte. The outputs
from each gate structure connect in parallel to the address and control terminals for the 36 circuits storing the four
groups of 1024 bytes. With these gating structures conditioned by the appropriate access control levels, the state of
gating control levels MOSA A H, MOSA B H,MOSA CH, and MOSADH (Table 3-16) enable accessing the specific
1024 bytes or words designated by the current address.

The access levels CENABLE L, PRECHARGE L, WRITE PULSE LOW L, and WRITE PULSE HIGH L are inverted
and buffered by two buffer gates (MOSC E10 and E11) to provide the drive necessary to access the MOS memory.

Write data from the M8110 control consists of the data bits SMCD MEM DATA (16,07:00) H for the low byte and
SMCD MEM DATA (17,15:08) H for the high byte. Input to the memory matrix is through type 3207 level shifters
just described.

3.5.2 MOS Memory Reading

At the selected G401 MOS memory module, the states of MAD bits 13 and 14 will assert MOSA SEL 13 H and
MOSA SEL 14 H from gates E7. These levels enable a parallel sense-amplifier network made up of 18 sense
amplifiers, one for each memory bit. Each sense amplifier consists of one element of a 75108 dual-line receiver with
open collector output. The input to each sense amplifier is wire-ORed to the output of four memory circuits. As a
result, the input to each sense amplifier is the wire-OR of 1024 memory bit locations. Therefore, when a given word
is addressed, the content of the addressed location is input to the sense amplifiers. Note that the second input to
each sense amplifier is an unterminated line paralleling the first input. The purpose of this line is to cancel
common-mode noise generation on the adjacent sense line. The DATA output from each 1103 memory circuit
functions as an active current source so that output is 900 uA for logic 1 and O pA for logic 0. In addition, the
sensed output from each sense amplifier is a TTL output; therefore, output logic levelsare 3V=1and 0V = 0.

In summary, during a given DATI cycle, as the location to be retrieved is addressed, the data stored in that location
is placed on the internal lines MEM SA (17:00) to the output data multiplexing logic shown on drawing SMCE.

347

CHAPTER 4
CALIBRATION AND
MAINTENANCE

4.1 INTRODUCTION

This chapter concerns the calibration procedures and maintenance requirements necessary to maintain an MS11
Semiconductor Memory System. Paragraph 4.3 presents the detailed procedures necessary to perform all memory
system adjustment and calibration. The section on maintenance includes lists and descriptions of the diagnostic

program set required to perform memory system troubleshooting. Also included are references to specific

maintenance requirements contained in associated PDP-11/45 System documentation.
4.2 SEMICONDUCTOR MEMORY SYSTEM PRECALIBRATION PROCEDURES

Certain steps must be taken prior to actual memory calibration to assure valid results. These include loading a simple
memory cycling program, assembling the correct tools and equipment, and verifying that all portions of the memory
system and the overall PDP-11/45 System are operational. These steps are presented in the following paragraphs.
4.2.1 Memory Cycling Program

Proper performance of the adjustments listed in Table 4-1 requires that the semiconductor memory be continuously
cycling during actual calibration. While the memory refresh function automatically (during a power-up or
power-down condition) provides this requirement for MOS memory configuration, bipolar installations require the
input of a simple two-step program to implement continuous memory cycling. This program forces a DATI to the
memory system being calibrated every four KB11 bus cycles. Load this program into the processor through the
console switches as outlined in the following steps:

Set the octal address NNN 200 in the console switch register.
NOTE

The three leading digits of this address defines a core or semiconductor memory area other than the semiconductor memory

being calibrated.

Press the console LOAD ADRS switch.

Set 137005 in the console switch register and press DEP.

Place any address from within the semiconductor memory area being calibrated in the console switch
register and press DEP.

Set 0007754 in the console switch register and press DEP.

Repeat Steps 1 and 2, then press START.

4-1

Table 4-1
Semiconductor Memory Adjustments

Adjustment

Pin Nos.

Purpose

R42

E18 pin 8 to

Delays start of memory access cycle until address lines

REQ L LATCH PULSE L

E25 pin 8

are stable.

E25 pin 8 to

Times the assertion of AH, which, in turn, asserts

AH/CENABLE

)

E2S5 pin 6

CENABLE to enable the memory chips addressed.

E25 pin 8

Times the assertion of BL, which defines the trailing

BL/PRECHARGE

edge of PRECHARGE to complete recharging of
MOS memory prior to accessing.

R11

E2S5 pin 8 to

Times the assertion of CH, which asserts ACCESS

CH/ACCESS

E27 pin 13

READY LATCH to implement the current access

READY LATCH

cycle.

E2S pin 8 to

Times the assertion of SMCA D L, which, in turn,

SMCADL

E55 pin 6

asserts SMCA MEM SYNC L. (Effectively controls
the start of the write pulse. Figure 3-12.)

R13

E27 pin 8

Adjusts WRITE PULSE HIGH L assertion period.

At this point, a continuous DATI cycle will be performed at the M8110 control to be calibrated. Note that this
program originates from a memory area remote from the memory being calibrated so that the test program will be
unaffected by the calibration procedure. Upon completion of a calibration procedure, the test program can be
terminated by pressing the console HALT switch.

4.2.2 Test Equipment Required
Calibration of M8110 control timing is best performed with a Tektronix 453 oscilloscope or an equivalent equipped

with P6000-type probes. Also required for this calibration procedure are three, dual height, DEC W900 multilayer
extender boards and two IC chip clips.
4.2.3 Calibration Setup
Before adjusting the semiconductor memory system, perform the following steps:
1.

Verify that all semiconductor system modules are properly installed in the correct CPU backplane slots

as shown in Drawing E-MU-KB11-A-01 in the PDP-11/45 System Engineering Drawings.
2.

Visually check modules for such obviousdefects as broken wires and connectors.

Turn on primary power and verify that the overall computer system is operational.

4.3 MEMORY SYSTEM CALIBRATION

The characteristically different operating speeds of MOS and bipolar memory systems, and the resulting difference in
timing, requires separate calibration procedures for the system adjustments listed in Table 4-1.
4.3.1 MOS Memory System Calibration
The following procedures delineate all necessary adjustments to an M8110 memory control directing G401 MOS
Memory Matrix modules.

4-2

4.3.1.1 Address Set Up, Precharge, CENABLE, and Access Ready Timing Adjustments — To perform address set up,
precharge CENABLE, and access ready timing, proceed as follows:
1.

Remove the M8110 control from the processor and install the W900 extender boards in its place.

Plug the M8110 control into the W900 extenders.

Load the program described in Paragraph 4.2.1.

Set the oscilloscope as follows:place SLOPE switch in the minus (—) position; set the SOURCE switch to
INT SOURCE; press the INT TRIGGER button on CHANNEL 1 only; set the TIME BASE switch to 20
ns/cm; and set the VOLTS/DIV switch to 0.5 V/cm. All time measurements are made from the —1.5V
point on the displayed waveforms.

Locate IC 18 and IC 25 on the M8110 module and place an IC chip on each device.

Place the oscilloscope A probe on pin 8 of IC E18 (input); place the B probe on pin 8 of IC E25
(output).

Refer to Figure 4-1, which shows the relationship of the oscilloscope A Trace to the B Trace.

Locate R42 on the M8110 module and adjust the delay until the leading edge of B Trace occurs

approximately 95 ns after the leading edge of A Trace.
NOTE

The size of the slotted-head adjusting screw on R42 requires a
small screwdriver with a thin blade. Such a tool can be made

by grinding or filing the blade of a 3-inch pocket-type
screwdriver until it fits the delay-adjusting screw.

Remove the oscilloscope probes; attach the A probe to pin 8 of IC E25 and the B probe to pin 6 of IC
E25.

10.

Refer to Figure 4-1, then locate and adjust R9 until the A Trace shows a 90 ns negative-going waveform,
*1 ns.

11.

Refer to Figure 4-1, then locate and adjust R7 until the negative-going leading edge of B Trace occurs 70

ns after the negative-going leading edge of the A Trace.

12.

Remove the IC chip clip from IC E18 and place it on IC E27.

13.

Attach the B probe to pin 13 of IC E27. This is ACCESS READY LATCH H; it is used to define the
access time.

14.

Refer to Figure 4-1, then locate and adjust R11 until the positive-going leading edge of B Trace occurs

230 ns *1 ns, after the leading edge of A Trace.

15.

Remove the IC chip clip from IC E27.

16.

Locate IC 55 and place an IC chip clip on it.

17.

Attach the B probe to pin 6 of IC 55. Adjust R1 so that the leading edge of the B Trace occurs 240 ns
after the leading edge of the A Trace.
4-3

NOTE

Adjustment of R1 for single/double synchronizing.

M8109 Rev F Etch: Observe jumpers W6 and W5 on the
M8109. If W6 is IN and WS is OUT, adjust R1 of the M8110
to 240 ns. If W6 is OUT and W5 is IN adjust R1 to 210 ns.

M8109 Rev C Etch: If jumpers have been installed on the
previously unused half (pins 11, 12, etc.) of the flip-flop at E8
of the M8109, R1 of the M8110 should be adjusted to 210 ns.

If the flip-flop is unused, adjust R1 to 240 ns.
18.

Remove both IC chip clips from IC 25 and IC 55.

19.

Place an IC chip clip on IC 27.

20.

Attach probe A to pin 8 of IC 27. Adjust R13 so that the A Trace (SMCA WRITE PULSE HIGH L)
shows a pulse width of 60 ns.

21.

Remove the probe and the chip clip.

22.

Reinstall the M8110 Semiconductor Memory Control in its original connector slot.

l|=

REQ LATCH L

A TRACE

|
(R42

)

—~

(E18-8)

480 or 510 ns

PRECHARGE L

le——
95 ns

(E25-8)

l———— 90 ns

A TRACE(R1,R7,R9,R11}

i —_f" S
4|

B TRACE (R42)

CENABLE L

(£25-6)

ACCESS READY LATCHH

(E27-13)
MEM SYNC
L

’

(SMCAD L)

(E55-6)

(See NOTE,

B TRACE (R7)

(E27~8)

B TRACE (RM1)

240ns

para. 4.3.1.1, Step17)

WRITE PULSE HIGH L

¢Jr

230 ns

B TRACE (R1)

'!-——-s

A TRACE (R13)

tGOnsj

Y
11-2186

Figure 4-1 M8110 Timing and Termination Delay Adjustment

for MOS Memory (Logic Drawing SMCA)

4.3.2 Bipolar Memory System Calibration

The high speed of bipolar memory systems requires that several M8120 control delay adjustments be calibrated
differently than for a MOS memory system (M8110). The procedures for these adjustments are exactly the same as
the equivalent MOS memory system adjustment, except for the actual duration of the delay.

4.3.2.1 Address Set Up, Precharge, and Access Ready Timing Adjustments — To perform address set up, precharge,
and access ready timing adjustments, proceed as follows:
1.

Remove the M8120 control from the processor and install the W900 extender boards in its place.

Plug the M8120 control into the W900 extenders.

Load the program described in Paragraph 4.2.1.

Set the oscilloscope as follows: Place SLOPE switch in the minus (—) position; set the SOURCE switch
to INT SOURCE; press the INT TRIGGER button on CHANNEL 1 only; set the TIME BASE switch to
20 ns/cm; and set the VOLTS/DIV switch to 0.5 V/cm. All time measurements are made from the —1.5
V point on the displayed waveforms.

Locate IC 18 and IC 25 on the M8120 module and place an IC chip clip on each device.

Place the oscilloscope A probe on pin 8 of IC 18 (input); place the B probe on pin 8 of IC E25 (output).
Refer to Figure 4-2, which shows the relationship of the oscilloscope A Trace to the B Trace.
Locate R42 on the M8120 module and adjust the delay until the leading edge of B Trace occurs
approximately 80 ns after the leading edge of A Trace.
NOTE

The size of the slotted-head adjusting screw on R42 requires a
small screwdriver with a thin blade. Such a tool can be made

by grinding or filing the blade of a 3-inch pocket-type
screwdriver until it fits the delay-adjusting screw.
Remove the oscilloscope probes; attach the A probe to pin 8 of IC E25.
10.

Refer to Figure 4-2, then locate and adjust R9 until the A Trace shows a 60 ns negative-going waveform,
*1 ns.

11.

Remove the IC chip clip from IC E18 and place it on IC E27.

12.

Attach the B probe to pin 13 of IC E27. This is ACCESS READY LATCH H; it is used to define the
access time.

13.

Refer to Figure 4-2, then locate and adjust R11 until the positive-going leading edge of B Trace occurs
90 ns, *1 ns, after the leading edge of A Trace.

14.

Remove the IC chip clip from IC 27.

15.

Locate IC 55 and place an IC chip clip on it.

16.

Attach the B probe to pin 6 of IC 55. Adjust R1 so that the leading edge of the B Trace occurs 60 ns
after the leading edge of the A Trace.

4.5

NOTE

Adjustment of R1 for single/double synchronizing.
M8109 Rev F Etch: Observe jumpers W6 and W5 on the
M8109. If W6 is IN and W5 is OUT, adjust R1 of the M8120
to 60 ns. If W6 is OUT and W5 is IN adjust R1 to 30 ns.

M8109 Rev C Etch: If jumpers have been installed on the
previously unused half (pins 11, 12, etc.) of the flip-flop at E8
of the M8109, R1 of the M8120 should be adjusted to 30 ns.
If the flip-flop is unused, adjust R1 to 60 ns.

17.

Remove both IC chip clips from IC 25 and IC 55.

18.

Place an IC chip clip on IC 27.

19.

Attach probe A to pin 8 of IC 27. Adjust R13 so that the A Trace (SMCA WRITE PULSE HIGH L)
shows a pulse width of 60 ns.

20.

Remove the probe and the chip clip.

21.

Reinstall the M8120 Semiconductor Memory Control in its original connector slot.
i—

(€18 -8)

300 or330+ns-

REQ LATCH L

=‘l

ATRACE(R42)‘)‘r

)

T oS

te— 80ns M
'

A TRACE (R9,R11)

B TRACE (R42)

(£27-13)

:-—90ns—:[

ACCESS READY LATCHH

B TRACE (R11) "

MEM SYNC L

(SMCAD L)
(E55-6)

e-30/60ns
(See NOTE,

B TRACE (R1)

para 4.3.2.1,
Step 16) !

WRITE PULS(EE;';G_HBL)

(

60ns—»|

B TRACE (R13)
11- 2187

Figure 4-2 M8120 Timing and Termination Delay Adjustment
for Bipolar Memory (Logic Drawing SMCA)
4.3.3 Cycle Time Adjustment

To perform the cycle time adjustment, proceed as follows:
1.

Remove the M8120 (M8110 for MOS) control from the processor and install the W900 extender boards
in its place.

Plug the M8110/M8120 control into the W900 extenders.

With power on, zero the first 2005 locations (trap vectors) using the following procedure: Set the SR to
0, press the LOAD ADRS switch and DEP switch. Repeatedly press DEP until the address indicators
equal 2003 . The following steps will load 1000g locations with MOV RO, RO instructions.

4-6

Set SR=0
Press LOAD ADRS switch

Set SR = 10000. (MOV RO, R0)
Press REG DEP
Set SR = 00001¢
Press LOAD ADRS

Set SR = XXXXXg. The lowest address on the control whose timing is to be checked. If the control uses
the lowest memory addresses, then XXXXXg should be 23005.
Press REG DEP

(GPR 0 now contains the instruction MOV RO, RO; GPR 1 now contains an address 3005 .)
Set SR = 2004

Press LOAD ADRS

Set SR =100215 (MOV RO, R1+)
Press DEP

Set SR = 007765 (BR.—2)
Press DEP

Set SR = 200g
Press LOAD ADRES

Place the ENABL/HALT switch in the ENABL position
Press START. CPU will run an instant HALTing at location 000023 . (All of memory, starting at address

XXXXXs, is now loaded with MOV RO, RO instructions.)
Place the ENABL/HALT switch in the HALT position.

Set SR = XXXXX3 + 10003. (Address in GPR 1 at Step 4 + 10005)
Press LOAD ADRS

Set SR = 001375. (JMP instruction)
Press DEP

Set SR = XXXXX5. (Address in GPR 1 at Step 4)
Press DEP

Press LOAD ADRS

Place the ENABL/HALT switch in the ENABL position.
Press START

(MOV RO, RO instructions are now executed continuously.)
Set the oscilloscope as follows: Place SLOPE switch in the minus (—) position; set the source switch to
INT SOURCE; press the INT TRIGGER button on Channel 1 only; set the TIME BASE to 50 ns/cm

(100 ns/cm for MOS); set the VOLTS/DIV switch to 0.5 V/cm. All time measurements are made from
the +1.5 V point on the displayed waveform.

Locate IC E18 on the M8110/M8120 module and place an IC chip clip on it.

Place the oscilloscope A probe on pin 8 of IC 18. The period between cycles should be constant at either

300 or 330 ns (480 or 510 ns for MOS). (See Figures 4-1 and 4-2.) If the cycle time fluctuates between
300 and 330 ns (480 and 510 ns for MOS) adjust R42 on the M8110/M8120 until the displayed signal is
stable. (Some MOS modules may operate error-free only when adjusted to 510 ns.)
10.

Remove the probe and the chip clip.

11.

Reinstall the M8110/M8120 Semiconductor Memory Control in its original connector slot.

4.4 SEMICONDUCTOR MEMORY SYSTEM DIAGNOSTICS
The PDP-11/45 System Maintenance Manual presents a brief abstract for each diagnostic, describing program
function and application.

4.5 MEMORY MATRIX MODULE STRUCTURE

The relationship of G401 MOS Memory Matrix Module ICs to function is shown in Figure 4-3. Figures 4-4 and 4-5
provide similar information for M8111 and M8121 Bipolar Memory Matrix Modules.
4.5.1 Isolation of Malfunctions to Module Component

Various means are available to maintenance personnel to identify the source of memory errors: Signal tracing using
the oscilloscope and other test devices, diagnostic software that exercises selected areas of logic, and replacement of

suspected modules with identical spares that are known to be operational. The method (or methods) used is

determined by such factors as the nature of the problem, availability of on-line time and test equipment, applicable
maintenance directives, and instructions from supervisory (maintenance) personnel.

Isolation of memory problems to the module level involves identifying the failing address(es) and determining which
module has been assigned this address. As previously described (Paragraph 3.2.1) the jumper configurations on the
M8110/M8120 Semiconductor Memory Control(s) and the G401/G401-YA, M8111/M8111-YA and M8121 Memory
Matrix Modules determine this memory address assignment (refer to Tables 3-1, 3-2, 3-3, 3-9, 3-12, 3-14, and 3-15).
The processor, through software, is able to identify the failing address(es); this is accomplished by such means as the

ability to generate and check the parity (odd or even) of data stored in memory and to write 8-bit bytes in addition

to 16-bit words. (It should be noted that parity testing operations require the presence of a memory with the parity
option.) These selective methods of storage, in conjunction with the processors “error halt” facility, provide a very
positive means for processor identification of failing memory address.

Identification of the faulty IC in the memory matrix module is the logical conclusion of this procedure where
known data is stored at and read from known locations, with the processor halting when errors are discerned. As
indicated in Figures 4-3, 4-4, and 4-5, 256 or 1K word memory areas (high byte and low byte), storage bits, and
control circuits are identifiable to the component (IC) level. (The “E” numbers for these ICs can be found on
drawings D-CS-G401-1 (MOS), D-CS-M8111-0-1 and D-CS-M8121-YA-1 (bipolar).)

LOW BYTE
STORAGE BITS
DATA

5.6,

DRIVERS-BITS

716

t1e

12|l

13}

ADDRESS

~ JUMPERS

A,8,C,D

l2)1la

144

ADDRESS

|17

CONTROL

UNIBUS
03

UNIBUS
02

(MAD 02)| {(MAD O1)

(

0-1023 —

)

1024-2047 ——» §

2048-3071— I8

\3072-4095 —»

0-1023 ——

1024 -2047 ——» |

2048-307{—=»

3072-4095 ——»

LOW BYTE<

(

HIGH BYTE<

15
17

SENSE

AMPLIFIERS BITS

8 9 10 11 12 1314 15 17'
STORAGE

BITS

Figure 4-3 G401-YA MOS Memory Matrix Module —
Relationship of ICs to Bits

4-9

CHIP SELECT 3 DRIVERS
WRITE

WIRE WRAP

ADDRESS
JUMPERS A 88

ENABLE

DRIVERS

CS 182

ENABLE

INPUT DATA
DRIVERS
WIRE

WRAP

ADDRESS

JUMPERS
C,D,E,F,H,J

CHIP SELECT
18 2 DRIVERS

ADDRESS

SELECT
AND DRIVERS

ROW SELECTION

MAD

O09

UNIBUS

ROW | LOCATIONS

HIGH BYTE
1

768-1023

LOW BYTE

HIGH BYTE

512-767
LOWBYTE

MEMORY
+ STORAGE
MATRIX

HIGH BYTE

256 -511
LOW BYTE

HIGH BYTE

0-255
e

LOW BYTE

i3}

STORAGE

BIT:

Figure 4-4 M8111 Bipolar Memory Matrix Module —
Relationship of ICs to Bits

4-10

}

M81i1

ONLY

INPUT DATA BUFFERING

WRITE PULSE

E1,E8 THRU E12

BUFFERING

ES5, E6, E7

ADDRESS
DECODING AND
CHIP SELECTION

ADDRESS
DECODING
SWITCH S1

E2, E3, E4

ROW SELECTION

ADDRESS BUFFERING

MAD

UNIBUS/FASTBUS

ROW

LOCATIONS

0-1023

(MAD 1 -9, 12)

E13 THRU E34
LOW BYTE

HIGH BYTE

LOW BYTE

1024-2047
HIGH BYTE

MEMORY

STORAGE
MATRIX

LOW BYTE
1

2048-3071
HIGH BYTE

LOWBYTE

3072-4095
HIGH BYTE

— 16 LOW BYTE PARITY

STORAGE BIT:

of1]
8

2|
9

3|
10

4]s
12

——17 HIGHBYTE P

7
13

GHE

ARIT Y
7745-1

Figure 4-5 M8121-YA Bipolar Memory Matrix Module —

Relationship of ICs to Bits

4-11

APPENDIX A

SEMICONDUCTOR MEMORIES

A.1

INTRODUCTION

The purpose of the following description is to provide the reader with a general overview of the construction,
operation, and use of semiconductor memories. It is a general discussion of these devices and does not necessarily

reflect the operation of the MOS and bipolar memory modules used in the MS11 Semiconductor Memory system.
Bipolar memories are described first, followed by metal-oxide-semiconductor (MOS) storage devices. A basic
understanding of transistor terms and operation is assumed.

Various types of semiconductor memories, based on both MOS and bipolar technologies, are presently being used.

These memories differ in cost, organization, and performance. In general, MOS technology offers higher density

(and is therefore more economical) but lower performance memories than bipolar. The use of dynamic MOS

circuits permits retention of data at very low power. Thus, when volatility of memory data is a problem, dynamic
MOS devices, with batteries as a back-up power source, are more: suitable than bipolar devices.

A.2

BIPOLAR MEMORIES

Most bipolar memories use a relatively standard flip-flop as the storage element. Variations in process techniques

include the use of an epitaxial layer for resistors and the use of Schottky-barrier diodes to improve response speed
and for memory selection. Two basic bipolar memory cells are shown in Figure A-1. Detail A is a cell that uses

multiple emitter transistors. In detail B, Schottky diode selection is used.

In the MS11-CC, a monolithic semiconductor bipolar 256-bit memory chip is used as the basic element in fabricating 1024-word random-access-memory (RAM) arrays. (The MS11-AP uses a similar chip containing 1024 bits.)
This high speed 256-bit random-access-memory element is organized into a 1024-word by 18-bit array. On-chip

address decoding, along with chip enable, write enable, and uncommitted collector outputs, provide for connection of these memory elements into the larger array. The entire chip, including address decoding, write and sense
circuitry, typically dissipates 450 mW. A word is accessible in less than 60 ns, the write recovery time is less than
35 ns, while the write pulse width required is 60 ns.

Each one-bit memory element is a latch flip-flop. This simple form of flip-flop, used for bit storage, comprises
two 2-emitter transistors and three resistors. One emitter on each transistor is used for word selection, one

emitter remains at a reference voltage, while the remaining emitter is:used for writing information into the cell
and reading information from the cell (Figure A-1, detail C).

The monolithic memory cell also contains.the “write enable” which controls data to be written into the flip-flop,
allowing only selected-data into the cell when its input is low. No data can be written into the flip-flop when the
input to the write enable is high. Conversely, no data can be read out of the flip-flop when the write enable input

A-1

SELECT |

SELECT

DATA

8. SCHOT TKY DIODE SELECTION

A. MULTIPLE EMITTER SELECTION

oVece
_oVp

WRITE

WORD SELECTION LINE
C.MEMORY CELL STRUCTURE

Figure A-1

2170

Bipolar Memory Cells

is low. The write amplifier will write selected data into the flip-flop only when the write enable input and
the

chip enable are low. The sense amplifier will only read selected data out of the flip-flop when the chip enable
is low and the write enable input is high.

To analyze the memory operation in more detail, a simplified 16-word by 4-bit matrix is used as an example
(Figure A-2). Beginning with the read operation, assume that a logic 1 is stored in the flip-flop. This means that

transistor Q, is on and conducting current. As long as the word selection line is low, the current path will be
through this line. However, if the word selection line is high and the write enable line is high, the current will

switch to the second emitter and flow down into the appropriate data sense amplifier, activating a logic 1 at the
data output of this amplifier.

Now, let us examine the write operation in more detail by writing a logic 0 into the flip-flop. First, chip enable

and write enable must be low and the cell is selected through the appropriate binary code at the address inputs.
Then, the output to the selected write amplifier is reduced to a low, turning off the output of the amplifier. This
will, in turn, raise the voltage on the write read line to a high, causing transistor Q, to turn off and Q, to turn on.
Now the flip-flop is said to have a logic O stored. In order to write a logic 1 into the flip-flop, the chip enable and
write enable remain the same, but in this case, the input to the selected write amplifier is increased to a high.

This will, in turn, lower the voltage on the write/read line to a low, causing transistor Q, to turn on and Q, to
turn off.
A reduction in the number of inputs required for this memory element example can be accomplished by the addition of an address decoder (Figure A-3). The addition of a decoder reduces the inputs of this 16-word by 4-bit
memory element from 16 address lines to 4. This decoder has five inputs; four inputs, Ay, A;, A,, A;,

act as

addresses to produce an output at a corresponding output terminal, while the fifth input, chip enable (C/E), is
used primarily in larger memory arrays to select a 64-bit memory element chip. The A, input terminal of the

decoder is considered the least significant so that an input configuration such as 1000 on inputs Ay, A, A,, A;,
respectively, will produce a logic 1 on output 1.

To analyze the address decoding operation in more detail, place a logic O at the chip enable input and A, , A,, A,
inputs while placing a logic 1 at the A,y input (1000). This will cause gate B to turn off and gate C to turn on,

resulting in logic 1 at point B, and logic O at point B, presenting logic 1s at all the inputs of gate 1. Gate 1 will
now be turned off, resulting in logic 1 at output 1, while gates 0 and 2 through 15 have at least one logic 0 at
their input, leaving their outputs at logic 0 as indicated by the truth table.
Looking further, the truth table shows the A, input terminal of this decoder to be the most significant bit. An
input configuration such as 1000 on inputs A, A, , Aj, respectively, would produce a logic 1 on output 1. An
input configuration such as 0001 would produce a logic 1 at output 8.

Now that the various sections of the 64-bit memory array have been discussed, the entire element can be connected together (Figure A-4). To read the sixteenth word out of this 16-word by 4-bit memory element.example,

the chip enable and write enable input must be placed at logic 0 and all inputs Ay, A;, A,, A; must be at logic 1.
This code will cause the correct word selection line (15) to go high, resulting in data from all four bit locations

of the sixteenth word to be read out simultaneously at Dy, D, , D,, and D; outputs.
To write data into the ninth 4-bit word of this memory element, the write enable input must be placed at logic 0,
the chip enable and write amplifier inputs must be at logic 0, and the inputs Ay, A, A,, A; must be placed in
logic 1, 0, 0, 1, respectively. This configuration will cause the correct word selection line (8) to go high, allowing

data at the write inputs (Wy, W;, W,, W3) to be written into the four bit locations of this word.

A-3

b 4

CELL

W/R

LINE

REF

—

WORD
SELECTION
LINE

\]/,P

\%P

CELL

VTP

CELL

—

CELL

[

CELL

—

Tvp

CELL

Tvp

CELL

\Vp

CELL

|—4

*—

1
|
|

3
|

o—

W/E

o—

Nn-2174

Figure A-2

16-Word by 4-Bit Memory

WWW‘JW’M’JWHJ

(1-OUT-OF-16)

- R R

CHIP
ENABLE
C/E

0X
=
By

L
_2
1

—03

—o0 7

]

——0 8

— o1

—0 0

’

——o0 10

—o12

——o0 13

8o
31.—,_\

014

}

—015

193

11-2172

Figure A-3

1 Out of 16 Address Decoder (Sheet 1 of 2)

Truth Table
Input

Output
Ay

Figure A-3

1 Out of 16 Address Decoder (Sheet 2 of 2)

A-6

CHIP
ENABLE

— cELL

o—

o—
Az

— ceLL

|
VP

—] CELL

]

—{ ceLL |

CELL

| ceLL

o=
Az

TGND

[

—| CELL

|
1

REF

ELEM

CELL }—

ADDRESS

DECODER

;

F— 2

— 3

]

OUT-OF

—

—— 6

— 7

—— g

]

:
'

‘

]

F—— 12

¢—JCELL|—¢

¢4 CELL|—<¢

¢—{CELL <

¢— CELL }—¢

—— 11

WRITE
ENABLE
o

)
W/E

—°

-0

©°

wo
o~

c>3

n-2173

Figure A-4

16-Bit Memory Element

(16-Words by 4-Bits)

A.3

MOS DEVICES

One of the most important features of the MOS (metal-oxide-semic

onductor) device is its simplicity. An electric
field, applied through an oxide-insulated gate electrode, is used to control
the conductance of a channel layer of

semiconductor material under the gate. The channel is a lightly
doped region between two highly doped

called the source and the drain.

areas

There are four basic types of MOS structure. The channel can be
a p- or n-type, depending on whether the
majority carriers are holes or electrons, and the mode of operation

can be enhancement or depletion, depending
on the state of the channel region at zero gate bias. If a conducting channel
exists at zero bias, the device is

called depletion mode, because current flows unless the channel

is depleted by an applied gate field. If a channel

must be formed by the gate field before current can flow, the device

is termed enhancement mode.

The enhancement mode is attractive in digital circuits, because it provides inherent
age must exceed a threshold voltage before the device turns on.

schemes, and is used in linear ICs.

noise immunity — input volt-

This mode is also suitable for self-biasing circuitry

Depletion mode devices, on the other hand, which conduct at zero gate voltage,

are especially attractive for tuner

input stages. The high-impedance gate is simply connected to an antenna coil,
and the input

signal modulates the
conductance between source and drain. Since the depletion mode device is
formed of material that has a higher
doping level than in the enhancement mode device, and channel mobility is also higher,

it can operate at higher

frequencies.

The most common device, the p-type enhancement mode, is built on a substrate of n-type

silicon, into which are
diffused two p-regions: the source and the drain (Figure A-5, detail A). These are normally
formed by diffusing
two wells of n-type impurity (phosphorous) into the substrate, and in operation are connected

by an induced

p-region, which is the channel.

The gate or control element covers the region between the source and the drain and is insulated

from the semiconductor material by a layer of silicon oxide. The input resistance of the gate is extremely high
— on the order

of 108 ohms — and the input impedance at high frequencies is almost purely capacitive. The gate is
a layer of
metal, usually aluminum, as are the contacts to the source and the drain. Normally the oxide
layer under the
gate is made much thinner than the protective oxide on the rest of the chip, to enhance the effect of

the gate

field on the conductance of the channel region.
If the gate, source and substrate are grounded and a negative voltage is applied to the drain, no current will

flow
between the source and drain because they are isolated from each other by the reverse-biased drain-to-body pn

junction.
If a negative voltage is applied to the gate, the surface of the n-type silicon inverts, becoming essentially p-type.
The negative gate voltage attracts holes from the n-type substrate to the surface. The channel area, very near the
surface, initially has an excess of electrons, because the material is n-type, but the holes drawn into the area by
the gate field neutralize these electrons. At some gate voltage, the attracted holes just compensate for the
excess
electrons, and the channel behaves like the instrinsic semiconductor. At higher gate voltages, the holes
predominate. The channel area, a few microns deep, is referred to as “inverted” — it now behaves like a p-type
semicon-

ductor, providing a current path from source to drain.

The surface region under the gate does not invert, and no conduction can occur until the gate voltage is more
negative than the threshold voltage Ve, which is about —5 V for most p-channel enhancement mode

devices.

This effect results, in part, from the presence of impurity charge in the silicon, which must be neutralized
the channel region can invert. In general, the thinner the gate oxide, the lower the threshold voltage.

A-8

before

Q—Vos
£

-20

GATE

-14

-12

-10

-8

-6

-4

CONTACT

-7

-2

Ves " -6
DRAIN

THICK OXIDE

-16

Ves
* -5

SOURCE CONTACT
THIN OXIDE

-18

g/
T

—

-2

V%=—8

(

Ves = -9

SATURATE

A . THE MOS TRANSISTOR: A SIMPLE CONFIGURATION OF

SOURCE, DRAIN AND GATE ELECTRODES.

n-2177

-9
=10

B. THE DC CHARACTERISTIC: CHANNEL CONDUCTANCE IS
DETERMINED BY THE GATE - TO - SOURCE VOLTAGE.

W—

n-2178

C. THE SATURATION PHEOMENON: DRAIN TO SOURCE
VOLTAGE EFFECTS ARE LIMITED BY CHANNEL PINCH-OFF.
n-2279

Figure A-5

Structure of MOS Devices

A-9

As the gate voltage becomes more negative than the threshold V1, the conducting

channel is formed, and its
depth increases with increasingly negative gate voltage. For low-drain current,
the channel is an ohmic resistance,

and the current, Ip, is directly proportional to the drain-to-source voltage Vps-

however, the channel saturates, and the current levels off (F igure A-5, Detail B).

As Vpg becomes more negative,

The saturation phenomenon is easily understood. Assume that the device is operated
with the source grounded
and the gate at =12 V. If the drain voltage is zero volts, no current flows, even though
a channel exists. As the
drain voltage is made negative, current flows from the source to the drain through the resistive
channel (Figure
A-5, Detail C). The voltage difference between the gate and the body of the device is
=12 V at the left
creases along the length of the channel, due to the resistive voltage drop, to a minimum of

and de-

(=12 - (=Vpg)) at the

drain. This voltage difference determines the extent to which a channel is formed in the substrate
material.
If the negative voltage -Vpg increases enough, the gate-to-body voltage at the drain (=12 — (—VDS))

approaches

the threshold voltage V1, and the voltage near the drain is just sufficient to form a channel at that point.

If Vpg

is made still more negative, the inversion channel terminates short of the drain; the drain current is limited

and

becomes independent of further changes in Vps-

A.4

MOS MEMORIES

Many different MOS memories are available or in development. Both static and dynamic storage cells may
be
realized in MOS, and either type of MOS storage may be organized as random-access memory (RAM) or as serial

(shift register) memory. Dynamic MOS shift register memories usually offer the lowest cost per bit. Very little
chip area is wasted, since the shift register permits small memory cells, requires no decoder, and uses very few
leads. Static MOS memories usually show poorer performance and higher costs, but may be easier to drive, for
in general, dynamic memories require clock signals in addition to power supplies.

Dynamic MOS circuits, such as those used in the MS11, make use of the very low leakage current associated with
the gate circuits and junctions of well-designed MOS devices. These leakage currents are small enough to permit

the circuit parasitic capacitances to exhibit time constants from milliseconds to seconds.
To illustrate the basic differences between dynamic and static MOS circuits, a dynamic inverter is compared with
a static inverter in Figure A-6, detail A and B.

In the static inverter, a MOS transistor is used for the resistor-like device, Q,. When the input signal is a 1

(negative voltage), the output must be a 0. Thus the resistance of Q, must be very high when compared with
that of the lower transistor, Q,, or the output voltage will be too great to be considered a 0. As this resistor

device is turned on harder than the lower device, certain geometric relationships between the two devices must
be maintained. The resistor must have a long narrow channel, and the lower device must have a short wide channel. As the minimum channel dimension tends to be determined by the minimum tolerance possible, both devices are larger than a minimum-sized device (approximately square channel). In addition, far less current is

available for charging an output load capacitance than discharging. Part of the load capacitance is due to the
parasitics of the inverter devices. Because these devices are larger than the minimum device, the load capacitance

is greater, reducing the speed of the circuit.
In the dynamic circuit, when an input ® goes negative (for p-channel devices) the output is charged, via Q,,toa

negative potential. The only loads permitted are capacitive (except for junction leakage), so when ® returns to
ground potential, the output will remain negative unless Q, conducts. Device Q, will conduct only if the input
isa 1. Therefore, after applying a pulse on line ®, the output, after a short delay, will represent the logical inverse of the input. Because circuit operation does not depend upon the ratio of device resistances, both devices

MOS

INVERTERS
v

' Q1

01
ouT

ouT

—|Q;

——

-do.
27T\

MOS

STORAGE

DYNAMIC

STATIC

CELLS

SEL

DATA

R-SEL

STATIC

RAM

|
1
-l
-

»,

/"l\

—

W-SEL

2
W- DATA

R- DATA
DYNAMIC

RAM

DYNAMIC

SHIFT

11-2180

Figure A-6

MOS Memory Circuits

A-11

can be of minimum geometry. Thus, some of the tradeoffs between static and dynamic become obvious: the

dynamic circuit is less expensive and faster but requires more elaborate drive signals.

The basic MOS storage cells are shown in Figure A-7, details C, D, and E. A static storage cell using transmission
gate selection is shown in detail C; a dynamic memory cell for use in random access memories is depicted in
detail D; and detail E shows a dynamic shift register stage.

In the static RAM stage of detail C, two static inverters are wired together to make a flip-flop. Devices Q5 and
Qg are used as (2-way) transmission gates. When reading, the conducting side of the flip-flop pulls the data line
toward ground through these gates. Writing is accomplished by forcing the data lines to the value desired in the

cell, thereby overriding the contents of the cell. Because of the small current capability of devices Q; and Q,, it
is important that neither of the data lines be near ground when the transmission gates are turned on, or the charge
associated with the capacitance of the data lines may flip the cell.

The organization of a 1024-bit dynamic random-access memory chip employing the memory cell of Figure A-6,
detail D, is shown in Figure A-7, detail A.

The dynamic RAM is organized as a 1024-bit memory plane. The input address is fully decoded on the chip.
For input/output, a single dual purpose lead is used. Operation of the memory shown consists of transferring
the data from one row of cells (as selected by the X address) to the refresh amplifiers, then reading the output

of one amplifier (as selected by the Y address). To write, the contents of the refresh amplifiers are rewritten

into the rows of cells, and then the contents of the selected cell are changed by the input data.

It can be seen from Figure A-6, detail D that storage within the cell is achieved by charge storage on the parasitic
capacitance of the gate circuit of storage device Q,. The data may be non-destructively read by precharging the
R-DATA lead, then turning on Q, with the R-SEL line. If the gate of Q, has been charged, the R-DATA lead
will be discharged. The refresh amplifier inverts the signal on the R-DATA lead and applies the result to the
corresponding W-DATA lead. This data may then be written into the cell by activating the W-SEL lead.

In the organization shown in Figure A-7, detail A, reading and writing occur for all cells of one row simultaneously.

Because only one bit at a time is available for writing, an internal read operation must be performed prior to
writing, so that the refresh amplifiers contain data corresponding to the contents of the row into which writing
will take place.

There are three clock-like signals associated with the dynamic RAM. These are shown in Figure A-7, details B
and C. Prior to the start of the cycle, the precharge signal is present (negative), and X and Y enables are absent
(at their most positive value). Upon receipt of the address, the cycle starts by removing the precharge signal and
then turning on the X enable. After waiting a specified period of time, Y enable may be turned on. Aftera
specified delay, an output current from the device indicates whether the selected bit contained a 1 ora 0. To
read this current, the output terminal must be held negative.

If writing is to take place, the Y enable is removed while the X enable remains on. The data to be written is
then placed on the data input/output lead. To complete the memory cycle, both X enable and Y enable must

be turned off, and then the precharge signal must be turned on for a minimum period before starting the next
cycle.

X enable and Y enable both act as a chip select for both reading and writing. Several chips may have the input/
output lead OR-tied to build larger than 1024-bit planes.

Using silicon-gate MOS technology, the clock signals and addresses are nominally 20 V peak-to-peak. Memory
cycle times depend upon chip organization and drive signal rise and fall time.

A-12

(wrire)

(Reao)

W OR7A

ROATA

o—
v

ADDRESS 00—

DECODE

o——

WeT==L1

X- ENABLE 0————

Y-ENABLE o-

Rse/

X32 ARRAY

Vo se/

ONE MEMORY

CELL OF 32

woRe

f'-__—_-'!
A

|
—

|
PRECHARGE 0—

oneoFs2

AwmPLIFIERS

REFRESH

Vo——

Go——

Y DECODE

—-———

INPUT/

OUTPUT

Y ADDRESS

(170)

! &UUL':‘UETNT)

/i “\

DATA

:':'SUL;AGE)

B. READ CYCLE

~N_

- -~ —_—

C.WRITE CYCLE
n-a2181

Figure A-7

Dynamic MOS RAM Circuits

A.4.1

Refresh Action

The memory array must be driven by a control circuit which includes provision for refresh action. Because the
storage in the memory cells is dynamic, the data must be periodically read from the cells and rewritten. With
the chip organization shown in Figure A-7, detail A, executing a read/refresh cycle restores the data in one row

of cells. To refresh the entire chip, 32 refresh cycles must be executed, i.e., one for each of the 32 possible X

address states.

To accomplish refresh action, a refresh controller may be constructed and attached to the memory as a highpriority cycle-stealing device. Since the longest time a cell may retain data without refreshing is approximately
1 ms, the cycle-stealing refresh control should steal one cycle every 1/32 ms, or approximately one cycle every
30 us. The stolen refresh cycles operate the X address states in sequence so that in any 1 ms period, all cells are
refreshed. To refresh the entire memory, the decoding associated with the X enables (and precharge, etc.) is
overridden. Data on the data lines is ignored during these refresh cycles.

Refresh cycle control need not be provided if the memory is operated sequentially with a high enough cycle rate.

Other refresh control techniques may also be used. For example, separate circuits, either analog or digital, may
be provided to determine which X address rows have not been refreshed by normal operation. In general, this
technique is more expensive. Even if all refresh cycles can be saved, the total represents only 1 percent of the
available memory time.

A-14

APPENDIX B

INTEGRATED CIRCUIT DESCRIPTIONS

This appendix contains descriptions of integrated circuits used only in the M8110, M811 1, or G401 modules.

De-

scriptions of other integrated circuits used throughout the PDP-11/45 System, as well as in the MS11 Semiconductor Memory System, are provided in Appendix A of the PDP-11/45 System Maintenance Manual.

1103 RANDOM ACCESS 1024-BIT MEMORY

The 1103 random access 1024-bit dynamic metal-oxide semiconductor (MOS) memory is an MSI circuit characterized by high speed and extremely low power dissipation. The circuit is organized as a 1024 X 1-bit memory

with integral address decoding, OR-tie capability at the outputs, and integral refresh logic. Data, once written, is

read non-destructively. Refreshing of all 1024 bits in a circuit is accomplished in 32 read cycles, which are re-

quired every 2 ms. Data written into an 1103 memory is inverted when read so that a high, when written, is read

as a O current, and a low, when written, is read as 0.9 mA (typical).

With reference to the block diagram and timing diagrams, access begins T , - before the negative transition of
CENABLE. During this period, PRECHARGE is active, and the address becomes stable in row and column decoders. After the CENABLE transition, the contents of the 32 cells along the selected row are written into the
32 on-chip refresh amplifiers, one of which is required for each column in the array. At the positive transition of
PRECHARGE, the contents of the refresh amplifiers are written back into their respective columns, and the out-

put appears T p, later. Tpy, after the positive edge of PRECHARGE, new data on the data input lead may be
written into the selected cell, using a READ/WRITE pulse of minimum duration T .

MADO4 (Ay) 3

[

MADO3 (Ap) 4

[

LJ 0L

15(A4) MADO?7

L J

16 CENABLE (CHIP ENABLE)

[

14 DATA OUT

PRECHARGE

[

MADOS (A3) 2

<
»

18 WRITE PULSE

MADO6 (A3) 1

[

MAD11

MADOS8 (As) 8

(12) DATA IN

MAD10 (A7) 9

MADO9 (Ag) 7

13 (Ag)

(11) Voo

(10) Vgg
11-0680

B-2

WRITE CYCLE

READ/WRITE CYCLE

<
VIH

ADDRESS

ViL

'wc OR 'rwe
i

@(3

ViH

>
7

ADDRESS STABLE

%cf#%fi?«%efZ
—»

[——
1ty —Pre-1t

*tovH -» ”

—_

PRECHARGE
v

tpc —TM

ViH

)

CENABLE

ViL

— tovL

——

READ/WRITE

le—— t.,

a1y

‘P

——

“*tcw

-— 'wp—’/

ViL

77X,

tow (NOTE 3)

[/ DATA CANZ WW
VL //A/é,
CHANGE A/ 4

DATA IN

DATA OUT

CLOAD = 50pF

READ CYCLE
ViH

ADDRESS

ViL

VREF=80mV

Acct

tacce

DAT

DATA
OUT

VALID

@(@

|e—

ADDRESS STABLE

[—

—t

OVH

MND%T‘%%EZ
—_

ViL

READ/WRITE

tovL

ViH

—

D
e P ———
cP

tpc —TM

ViL

pov

VOH

1pg ——!

———————- -

CLoap =50pf )\

RLoAD = 1008

VoL

VREF=80mV

YY TN

DATA OUT

'acct
t

@ oD

A AT
A QUT
'~
..
NOT VALID

tre

PRECHARGE

NOTES:

BTt

DATA OUT

tpy (NOTE 4)

STABLE
DATA
TIME

RLoap® 1008
—
N—
t

—

_..1

-—— 'PO —.POH

VoL

CENABLE

VIH 7

————

VALID

Accz

}t, Is defined os the transitions between these two points,

Vpp= 2V

@ vss=2v

3. tow s referenced to point @ of the rising edge of chip enable or read/write, which ever occurs first,
4. tpy !s referenced to point @ of the rising edge of chip enable or read/write, which ever occurs first.
11-0859

READY
WRITE
AMPLIFIERS

MEMORY MATRIX:

64
h S

1 OF 32
ROW
SELECTOR

32
ROWS
32 COLUMS

(1024 BITS)
164

REFRESH AMPLIFIERS
READ/WRITE COLUMN
GATING

DATA

VSS¢>—————D

Vgg o—
PRECHARGE

o—

ENABLE

o—»

READ/WRITE

o———»

32
1 OF 32
COLUMN SELECTOR

DATA OUT

Ag
11-0682

3207 QUAD 3-INPUT NAND TTL/MOS LEVEL SHIFTER

The 3207 TTL/MOS level-shifting integrated-circuit NAND gate provides an operational interface between TTL
control circuits and MOS data storage circuits. Each gate in a unit is enabled by the coincidence of three +3V in-

put levels. Enabled output is +19V. Inputs are connected so that each group of two gates has two common in-

puts with one unique input for each gate. This connection scheme permits cascaded level-shifting logic structures

which are conditioned in common by the coincidence of several control levels, with the output of each gate being
enabled by a single input.

VSS

1 —

— 16

— 15

Vcc

— 13

]
—
GND

8 —

—
9

Vpp

ouT

GND

1H-0860

B-4

3404 HIGH SPEED HEX LATCH
The individual latching elements in the 3404 6-bit high-speed latching

circuit are organized as separate 4-bit and
2-bit latches with each section having a common write line. This device
is directly compatible with both DTL

and TTL logic and provides an output sink capability of 10 mA minimum.

as high-speed inverters when the write input is held low.

The latches in this device can also act

D, €3

= 0
4

9 0,

MEASUREMENT FOR DATA DELAY
-y

ymmmem

DATA
INPUT

'seT uP

TM| YHouwD

WRITE

ENABLE

ouT

D G

D GD

SR G

D WS GU

NOTE 1
LT

NOTE 1:

e )

Output Data is valid after .t

—+

MEASUREMENT FOR WRITE ENABLE DELAY
DATA

INPUT
D

WRITE

S S

oy of

—\

ENABLE

dadad

ouT

NOTE 2
cToaswawessd

NOTE 2:

Output Data is valid after t__ S,

B-5

82562 9-BIT PARITY GENERATOR AND CHECKER

The 82862 9-Input Parity Generator/Parity Checker is a versatile MSI device commonly used to detect errors in

data transmission or in data retrieval two outputs, EVEN and ODD, provide versatility. The INHIBIT input disables both outputs of the 82562 (a logic 1 at the INHIBIT input forces both outputs to a logic 0).
When used as a parity generator, the 82S62 supplies a parity bit which is transmitted together with the data word.

Read data is input to the 82S62 when it is used as a parity checker. The outputs then indicate that data has been
received correctly or that an error has been detected.

LOGIC DIAGRAM
'

(1)

HD>—

(2)

INHIBIT

(3)

00D

{4)

{10)

EVEN

(11)

OUTPUT

(9)
(12)

: :

(13)
o—

(5)
1-2184

B-6

74200 BIPOLAR 256-BIT RANDOM ACCESS MEMORY
The 74200 integrated-circuit memory is a high-speed, fully decoded, static

bipolar 256-bit RAM, organized as a
256 X 1-word memory. The circuit contains integral write and sense amplifiers
with sense amplifier output being

uncommitted collector output. Each circuit is addressed through the ADS
SEL 1 to ADS SEL 8 inputs which select
one of the 256 words. A circuit is enabled by placing all three CS inputs
to logic 0. If the WR EN HI/LO (write
enable) is at logic O, the data at pin 13 is written into the addressed word
in the complementary form. When
WR EN HI/LO returns to logic 1, the data that was written can be read
out. However, a bit as read is the complement of the same bit as written. The figure below shows the functional
logic for one bit (a single IC on the

M8111 module). Pin numbers are shown in parenthess.

RATINGS
Tri-State Drive;
Output OFF @ Voff

VOH minimum @ IOH

Voff (forced)
VOL maximum @ IOL

-10 mA (min)

Input load factor

140 pA (max)

PT (typical)

16 mA (min)

Access Time (typical)

24V

Enable Time (typical)

Sense Recovery Time (typical)

04V

Write Pulse Width (typical)

(7)

(9)
BIPA ADS SEL 6 O—

(11)

510 mW
40 ns

04to24V

(BIPA ADS SEL 5 0——

(10)
BIPA ADS SEL 7 0o—

0.67

256 BIT

(32 BY 8)
MEMORY

CELL

[

BIPA ADS SEL 8 0—

_DL Y ? 99

Ioy—High Level ON @ VoH

SELECT
INPUTS

30 ns
20 ns

(14)

BIPA ADS SEL 4 0——

20 ns

SMCE MEM sa | READ

<17:00>

[ OUTPUT

(1)

BIPA ADS SEL 2 ('TZ)

1 OF 8 DECODER

(15)

| BIPA ADS SEL 3 0———

(13)

BIPB MEM DATA <17:00>
0—

(12 )

Ft)'—
BIPA CSt
BIPA CS2 %} é

BIPB WR EN HI/LO
O-

(3)

MEMORY
ENABLES

BIPA cs3

PIN (16)= V.. , PIN (8)
x GND
11~ 1316

75107/75108 DUAL-LINE RECEIVERS
The 75107 and 75108 dual-line receivers are linear integrated circuits

consisting of two independent channels per
circuit. Each receiver channel is formed by a differential input stage, a
level shifting stage, and a TTL NAND

gate output stage.

The 75107 NAND gate stage provides the familiar totem pole

open collector output at the NAND gate stage for wire-ORing.

output; the 75108 provides an

GATE 16
INPUT 1A

QUTPUT 1Y

INPUT 1B

STROBE
INPUT 2A

INPUT 28

OUTPUT 2
GATE 26

o
e

TYPICAL
CHARACTERISTICS

g
g
<o
X

88
o<
SF

¢«
w
Wz

s'0

23k

wo
w a

DUAL

"E n

: = w

Sow

g :t- L

odu

(_20.

<O°'

=02

aoo

134

LINE RECEIVER WITH

DUAL LINE RECEIVER WITH

(OPEN-COLLECTOR)
GATE

(TTL) GATE OQUTPUT
75108

z
)
z
2
91;2

26
g
Eh
W

75107

cLs

OQUTPUT

11-1074

B-8

8242 EXCLUSIVE-NOR 4-BIT DIGITAL COMPARATOR
The 8242 digital comparator circuit consists of four independent exclusive-NOR gates with each gate

structure

having an open collector output to permit multiple bit comparisons. A 4-bit comparator network is formed
by
connecting the independent outputs; such a network is easily expanded by cascading the outputs.

0
1

—_

B-9

O|»

—_ 0

TRUTH TABLE

82510/93415 1024-BIT RANDOM ACCESS MEMORY
The 82510/93415 random access 1024-bit bipolar memory is organized as a 1024 X 1 word memory. It is fully
compatible with standard DTL and TTL families. Bit selection is achieved by means of a 10-bit address input

BIPA ADRS SEL(10:01A, B, C, D, H, pins 2—6, 9—13. A chip select (CS) input (BIPB CS (3:0) L, pin 1) provides for memory array expansion; the fast chip select time permits the decoding of CS from the address without

affecting system performance.

The read and write operations are controlled by the state of the active low write enable (WE) input (BIPB WR

LOB/HIB A, B L; pin 14). With WE held low and the chip selected, the data (BIPB MEM DATA (17:00) H, pin
15) is written into the addressed location. To read data at a memory location, WE is held high and the chip is
selected. Noninverted data (SMCE MEM SA (17:00) H) is then read out to pin 7.

BIPB CS(3:0)L |1_

BIPA ADRSSEL1(D!A)H E

BIPA ADRS SEL 2(D:A) H E
BIPA ADRS SEL 3(D:A) H E
BIPA ADRS SEL 4(D:A) H E

BIPA ADRS SEL 5(D:A) H E

B E]ETE]
B

TOP VIEW

Vee
BIPB MEM DATA (17:00) H

BIPB WR

LOB/HIB
L

BIPA ADRS SEL 10(D:A)H

BIPA ADRS SEL 9(D:A)H

BIPA ADRS SEL 8(D:A)H

o] B

SMCE MEM SA (17:00) H I 7

GND l_B-

BIPA

ADRS SEL 7(D:A)H

BIPA

ADRS SEL 6(D:A)H

ADRS SEL(5:1)

2 3[4] 5| 6]
ADDRESS

D ECODER

WORD

DRIVERS

—\

18,

SMCE MEM SA (17:00) H
(DATA

OUT)

32 X32
ARRAY

WRITE
5

SENSE AMPS

WRITE

DRIVERS |

BIPB CS (3:0)L

p—

WRITE |y
1

o_—

ADDRESS

(CHIP SELECT)

BIPB WR LOB/HIB L
(WRITE ENABLE)

18, BIPB MEM DATA (17:00) H

DECODER

( DATA IN)

9 |01 1213
ADRS SEL (10:6)
1-3623

B-10

READ
PROPAGATION

ADDRESS
INPUTS

MODE

DELAY FROM CHIP SELECT AND ADDRESS

INPUTS

X
L_45/70ns _.I

DATA

ouT

30/40ns
HOns _.l )

CHIP
SELECT

’._

_.'

L_ 30/40ns

/
WRITE MODE
SWITCHING

WAVEFORMS
(Setup, hold and write pulse requiments, see note)

—
ADDRESS
INPUTS (AO-A9)

r— 5/15 ns min.

—’1

]

—
DATA IN

%‘— S5ns min

—":

X
|

(DIN)

—
CHIP SELECT

(CS)

—-:

4
|

WRITE PULSE

|WRITE DISABLE
|

DATA OUT

30/40ns

(DOUT)

l— 5ns min.

}\L__ 35750 ns min. ——7/

(WE)

le— Sns min.

j— 5ns min.

WRITE ENABLE

le— Sns min.

f*—

WRITE

RECOVERY

30745ns mox
0/4

ax.

NOTE:

If two times are indicated the shorter one
is for the —O1variation and the longer one
is for the —QOQ variation.
TRUTH

INPUTS
—

TABLE

OUTPUT

MODE

OPEN

WE | Dy | COLLECTOR

WRITE O

WRITE

DOUT

READ

H= HIGH VOLTAGE

LEVEL

L=LOW

LEVEL

VOLTAGE

NOT SELECTED

X = IRREVELANT
11-3624

MS11-A, B, C

Reader’s Comments

MEMORY SYSTEMS

MAINTENANCE MANUAL

EK-MS11A-MM-006

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