Digital PDFs

EK-KDJ1E-UG-001

January 1991

383 pages

Original

14MB

Document:	-001 KDJ11-E CPU Module Users Guide Jan91
Order Number:	EK-KDJ1E-UG
Revision:	001
Pages:	383
Original Filename:	EK-KDJ1E-UG-001_KDJ11-E_CPU_Module_Users_Guide_Jan91.pdf

OCR Text

KDJII-E CPU Module

User Guide

Order Number: EK-KDJ1 E-UG-001

KDJ11-E CPU Module User Guide
Order Number EK-KDJ1 E-UG-001

Revision/Update Information:

Digital Equipment Corporation

This is a new manual.

January 1991
The information in this document is subject to change without notice and should not be construed as a
commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for
any errors that may appear in this document.
The software described in this document is furnished under a license and may be used or copied only in
accordance with the terms of such license.
No responsibility is assumed for the use or reliability of software on equipment that is not supplied by
Digital Equipment Corporation or its affiliated companies.
Restricted Rights: Use, duplication, or disclosure by the U. S. (rl)vernment is subject to restrictions as set
forth in subparagraph (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS
252.227-7013.
Copyright © Digital Equipment Corporation 1991
All Rights Reserved.
Printed in U.S.A.
The follOWing are trademarks of Digital Equipment Corporation: DEC system, PDp, PDP-lI, PDP-1lJ03,
PDP-1lJ05, PDP-1lJ10, PDP-lI/15, PDP-UI20, PDP-1l/23, PDP-1lJ23+, PDP-ll/24, PDP-1lJ35, PDP-11140,
PDP-1lJ44, PDP-lI/45, PDP-11150, PDP-11153, PDP-1l/60, PDP-11170, PDP-1lJ73, PDP-1lJ83, PPP-1lJ84,
PDP-1lJ93, PDP-11194, Q-bus, Q22-bus, RSX-ll, RSX-llM, RT-ll, UNIBUS, VT100, VT220, VT330, and
the DIGITAL logo.
This document was prepared and published by Educational Services Development and Publishing, Digital
Equipment Corporation.

Contents
About This Manual
1

XIX

Architecture
1..1

KDJ11-E CPU Module Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

1.2 DCJ11-A Microprocessor Features ............................
1.2.1
Stack-Limit Protection ................................ ~ . .
1.2.2
Kernel Protection ........................................
1.2.3
General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.4
Stack Pointer ......................................... .
1.2.5
Program Counter ...................................... .
1.2.6
Processor Status Word (17777776) ......................... .
CPU Error Register (17777766) ........................... .
1.2.7
1.2.8
Program Interrupt Request Register (17777772) ............... .

1-2
1-4
1-4
1-4
1-4
1-5
1-5
1-7
1-7

1.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1
Sunset Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.3.2
Red Stack Aborts .......................................
1.3.3
Addressing Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.3.4
Bus Timeout Errors .....................................
1.3.5
Interrupt Vector Timeouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.3.6
No SACK Timeouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1-8
1-10
1-11
1-11
1-11
1-11
1-11

1.4 Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.4.1
Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.4.1.1
16-Bit Mapping. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . ..
1.4.1.2
18-Bit Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.4.1.3
22-Bit Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.4.2
Compatibility. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . ..
1.4.2.1
Virtual Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.4.3
Interrupts Under Memory Management. . . . . . . . . . . . . . . . . . . . ..
1.4.3.1
Construction of a Physical Address. . . . . . . . . . . . . . . . . . . . . . ..
1.4.4
Memory Management Registers.. . . . . . . . . . . . . . . . . . . . . . . . . ..
1.4.4.1
Page Address Register (PAR) ............................
1.4.4.2
Page Descripfur Register (PDR) ..........................
1.4.5
Fault Recovery Registers .................................
1.4.5.1
Memory Management Register 0 (17777572) ................

1-11
1-12
1-12
1-13
1-13
1-14
1-14
1-15
1-15
1-17
1-20
1-21
1-22
1-22
iii

Contents

Memory Management Register 1 (17777574) ..................
1.4.6
Memory Management Register 2 (17777576) ................
1.4.6.1
Memory Management Register 3 (17772516) ................
1.4.6.2
Instruction Back-Up and Restart Recovery. . . . . . . . . . . . . . . . ..
1.4.6.3
Clearing Status Registers Following Abort . . . . . . . .. . . . . . . . ..
1.4.6.4
Multiple Faults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.4.6.5
Common Usage Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.4.7
Typical Memory Page. . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . ..
1.4.7.1
Nonconsecutive Memory Pages. . . . . . . .. . . . . . . . . . . . . . . . . ..
1.4.7.2
Stack Memory Pages. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . ..
1.4.7.3
Transparency ..........................................
1.4.8

1-23
1-24
1-24
1-24
1-25
1-25
1-25
1-25
1-27
1-28
1-29

KDJII-E Memory System Implementation. . . . . . . . . . . . . . . . . . . . ..
1.5
Memory System Error Register (17777744) .......... ~ . . . . . . . ..
1.5.1
1.5.2'
Cache Control Register (17777746) . . . . . . . . . . . . . . . . . . . . . . . . ..
HitJMiss Register (17777752) ..... . . . . . . . . . . . . . . . . . . . . . . . ..
1.5.3
Parity CSR Register (17772100) . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.5.4

1-29
1-29
1-30
1-31
1-31

1.6 Private Memory Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PMI Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.6.1
1.6.1.1
Bus Device NPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bus Device Interrupt ........................ ~ . . . . . . . ..
1.6.1.2
1.6.2
PMI Data Transfers .....................................
1.6.2.1
Data In/Data In Pause .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.6.2.2
Block Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1..6.2.3
Data OutJData Out Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1-32
1-32
1-32
1-32
1-32
1-33
1-33
1-33

KDJ11-E Serial Line Units .................................
1.7
Silo Buffer Length .................................. ,,' . . ..
1.7.1
1.7.2
Serial Line Unit Registers ................................
Receiver Status Register (1777xxxO) . . . . . . . . . . . . . . . . . . . . . ..
1.7.2.1
1. 7.2.2
Receiver Data Buffer Register (1777xxx2) . . . . . . . . . .. . . . . . . ..
Transmitter Status Register (1777xxx4) . . . . . . . . . . . . . . . . . . ..
1. 7.2.3
Transmitter Data Buffer Register (1777xxx6) . . . . . . . . . . . . . . ..
1.7.2.4
Break Response ........................................ .
1.7.3

1-33
1-34
1-36
1-36
1-37
1-38
1-39
1-41

Boot and Diagnostic Register Set ............................ .
1.8
Control/Status Register (17777520) ......................... .
1.8.1
Page Control Register (17777522) .......................... .
1.8.2
Configuration and Display Register (17777524) ............... .
1.8.3
Additional Status Register (17777526) ...................... .
1.8.4

1-41
1-42
1-44
1-45
1-46

1.9
Line Frequency Clock and Status Register (17777546) . . . . . . . . . . . .. 1-47
1.9.1
Maintenance Register (17777750) ........................... 1-48
1.10 Time of Year Clock (TOY Clock) ......... '. . . .. . . . . . . . . . . . . . . ..
1.10.1 Programming Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.10.1.1
Clear the Comparison Register Pointer. . . . . . . . . . . . . . . . . . . ..
1.10.1.2
Establish the Pattern Recognition. . . . . . . . . . . . . . . . . . . . . . . ..
1.10.1.3
Updating Information in the TOY Clock . . . . . . . . . . . . . . . . . . ..

1-49
1-50
1-50
1-50
1-50

Contents v

Configuration
2.1

Introduction ............................................ .

2-1

Module Configuration ....................... ".............. .
2.2.1
Jumpers For +5 V Power Source Selection ................... .
Switchpack ...................... -..................... .
2.2.2
2.2.2.1
Baud Rate Selection .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2.2
"Force Dialog Mode ....................................
2.2.2.3
ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2.4
Console/SLU Enable - Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-2
2-3
2-3
2-6
2-6
2-6
2-7

EEPROM Configuration Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . .

2-7

2.4
System Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LSI-II Based Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1
2.4.2
Restricted LSI-II Systems ............................... .
2.4.3
UNIBUS Based Systems ................................. .

2-7
2-8
2-8

2.5

Module Contact Finger Identification ......................... .

2-9

2.6

Module Installation Procedure ............................... 2-16

2.7

Specifications ................ : . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-17

2.2

2.3

2-9

Console On-Line Debugging Technique (ODT)
3.1
Introduction ........................................... ..
Terminal Interface ..................................... .
3.1.1

3-1
3-1

Console ODT Entry Conditions .............................. .

3-1

Console ODT Command Set ................................ .
3.3
Slash (/) Command (ASCII 057) .................... ~" ...... .
3.3.1
Carriage Return «CR» Command (ASCII 15) ............... .
3.3.2
Line Feed «LF» Command (ASCII 12) ..................... .
3.3.3
Internal Register Designator ($) (ASCII 044) or (R) (ASCII 122) .. .
3.3.4
Processor Status Word Designator (S) (ASCII 123) ............. .
3.3.5
Go (G) Command (ASCII 107) ............................. .
3.3.6
Proceed (P) Command (ASCII 120) ......................... .
3.3.7
Binary Dump «CTRL> <SHIFT> S) Command (ASCII 23) ...... .
3.3.8

3-2
3-3
3-3
3-4
3-4
3-4

ODT Address Specification ................................. .
3.4
Processor 110 Addresses ................................. .
3.4.1
3.4.2 -. Stack Pointer Selection .................................. .

3-6
3-6
3-7
3-7
3-7
3-7

3.2

3.4.3
3.4.4
3.4.5

Entering Octal Digits ................................... .
ODT Timeout ......................................... .
General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-5
3-5
3-6

vi Contents

Boot ROMs and Diagnostics
4.1

Operation Overview . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .

4-1

4.2
Hard Copy Terminal Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2.1
Boot Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4--3
4.2.1.1
Transferring Control to Non-Digital Boot Modules (UNIBUS
4-4
System Implementation) ...............................
4.2.1.2
Transferring Control to Non-Digital Boot Modules (Q-bus System
Implementation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4
4.2.1.3
Error Detection During the Boot Command . . . . . . . . . . . . . . . . . 4-5
4.2.2
Diagnostic Command .................................... 4-5
4.2.3
Help Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4--8
4.2.4
List Command ......................................... 4-9
4.2.5
Map Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-10
4.2.6
Setup Command ....................................... 4--11
4.2.6.1
Setup Mode Command 1 - Exit ........................... 4-12
4.2.6.2
Setup Mode Command 2 - Select Configuration Parameters. . . .. 4--12
4.2.6.3
Setup Mode Command 3 - Select Diagnostic Configuration. . . . .. 4--21
4.2.6.4
Setup Mode Command 4 - Select Serial Line Parameters. . . . . .. 4-23
4.2.6.5
Setup Mode Command 5 - Select Boot Parameters ............ 4-25
4.2.6.6
Setup Mode Command 6 - List Available Boot Programs (for
UNIBUS System) . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-27
4".2.6.7
Setup Mode Command 6 - List Available Boot Programs (Q-bus
System) ............................................ 4-29
4.2.6.8
Setup Mode Command 7 - Factory Setting .................. 4-29
4.2.6.9
Setup Mode Command 8 - Save the Setup Table in the EEPROM 4--30
4.2.6.10
Setup Mode Command 9 - Load EEPROM Data into the Setup
Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. .. 4-30
4.2.6.11
Setup Mode Command 10 - Load EEPROM Boot Program into
Memory ........................................... . 4--31
4.2.6.12
Setup Mode Command 11 - Edit or Create EEPROM Boot
Program ........................................... . 4-31
4.2.6.13
Setup Mode Command 12 - Save" a Boot Program in the EEPROM 4--33
4.2.6.14
Setup Mode Command 13 - Delete a Saved EEPROM Boot
Program ........................................... . 4-34
4.2.6.15
Setup Mode Command 14 - Enter ROM ODT ............... . 4-34
4.2.7
TOY Command ........................................ . 4-35

Video Terminal Support ................................... .
4.3
4.3.1
Moving Through Menus ................................. .
4.3.2
Types of Function Fields - Video Terminal ................... .
Setup Menu .......................................... .
"4.3.3
4.3.4
Self-Test Menu ........................................ .
4.3.4.1
Selecting or Deselecting Tests Executed Upon Power-Up" . . . . . ..
Selecting and Executing an Individual Test . . . . . . . . . . . . . . . ..
4.3.4.2
Selecting and Executing a Group of Tests (Test 30) ...........
4.3.4.3
User
Boot Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.3.5
Map Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.3.6
4.4

4-35
4--36
4-36
4--36
4-42
4-42
4-43
4-43
4-43
4-45

Diagnostic Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-45

Contents vii

4.4.1
4.4.1.1
4.4.1.2
4.4.2

KDJ11-E Self-Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Video Terminal Mode ..................................
Hard Copy Terminal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
KDJ11-E CPU Module Fault Isolation. . . . . . . . . . . . . . . . . . . . . ..

4-46
4-47
4-48
4-63

Extended LSI-11 Bus
5.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

5-1

5.2

Bus Signal Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .

5-2

5.3 Data Transfer Bus Cycles ........................... ; . . . . . . . 5-3
5.3.1
Bus Cycle Protocol ...................................... 5-4
5.3.1.1
Device Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.1.2
DATI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.3.1.3
DATO(B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-7
5.3.1.4
DATIO(B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-10
5.4

Direct Memory Access ................................... ~ .. 5-13

5.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.5.1
Device Priority ......................................... 5-17
5.5.2
Interrupt Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-17
5.5.3
4-Level Interrupt Configurations ........................... 5-20
5.6 Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.6.1
Halt ..................................................
5.6.2
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.6.3
Power Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.6.3.1
BDCOK H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.6.3.2
BPOKH ............................................
Power-Up ...........................................
5.6.3.3
5.6.3.4
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.6.4
BEVNT L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

5-22
5-22
5-22
5-22
5-22
5-22
5-23
5-23
5-23

5.7 Bus Electrical Characteristics . ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Signal Level Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.7.1
5.7.2
AC Bus Load Definition ...................................
5.7.3
DC Bus Load Definition ..................................
5.7.4
120 (J LSI-11 Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.7.5
Bus Drivers. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bus Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.7.6
Bus Termination . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . ..
5.7.7
Bus Interconnection Wiring .............................
5.7.7.1
Backplane Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.7.7.2
Intrabackplane Bus Wiring. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.7.7.3
Power and Ground ................................. . ..
5.7.7.4
5.7.7.5
Maintenance and Spare Pins ............................

5-23
5-24
5-24
5-24
5-24
5-25
5-25
5-25
5-26
5-26
5-27
5-27
5-27

5.8 System Configurations .................................. . .. 5-28
Rules for Configuring Single-Backplane Systems. . . . . . . . . . . . . .. 5-29
5.8.1
5.8.2
Rules for Configuring Multiple-Backplane Systems ............. 5-29

viii

Contents

5.8.3

Power Supply Loading. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. 5-31

Private Memory Interconnect Bus
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... ~ . . . . . . . . .

6--1

6.2
PMI Interface ........................................... .
6.2.1
PMI Bus Master Signals ................................. .
PMI Slave Signals ...................................... .
6.2.2
PMI UNIBUS Adapter Signals ............................ .
6.2.3
6.2.4
LSI Bus Signals ....................................... .

6--1
6--1
6--1
6-1
6-2

6.3

PMI Operation in an LSI-11 System .......................... .

6-5

PMI Operation in a UNIBUS System ......................... .
6.4
6.4.1
Bus Device NPR or DMA ................................ .
PMI Bus Device Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.2

6-5
6--6
6-7

6.1

6.5
PMI Data 'rransfers ....................................... 6-8
6.5.1
PMI Data In/Data In Pause ............................... 6-8
6.5.2
PMI Block Data In .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.5.3
PMI Data Out/Data Out Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-11

6.6

PMI Interrupt Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-13

6.7

PMI Power-Up/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6--13

Addressing Modes
7.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-1

7.2 Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .
7.2.1
Single-Operand Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.2
Double-Operand Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.3
Direct Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.3.1
Register Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.3.2
Autoincrement Mode [OPR (Rn)+J. . . . . . . . . . . . .. . . . . . . . . . . .
7.2.3.3
Autodecrement Mode [OPR -(Rn)] . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.3.4
Index Mode [OPR X(Rn)]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Deferred (Indirect) Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
7.2.4
Use of the PC as a General Purpose Register. . . . . . . . . . . . . . . . ..
7.2.5
Immediate Mode [OPR#n,DD] . . . . . . . . . . . . . . . . . . . . . . . . . . ..
7.2.5.1
7.2.5.2
Absolute Mode [OPR @#A] ..............................
Relative Addressing Mode [OPR A or OPR X(PC)] . . . . . . . . . . ..
7.2.5.3
Relative-Deferred Addressing Mode [OPR @A or OPR @X(PC)] ..
7.2.5.4
7.2.6
Use of the General Purpose Registers as a Stack Pointer. . . . . . . ..

7-1
7-2
7-3
7-4
7-5
7-7
7-9
7-11
7-13
7-17
7-17
7-18
7-19
7-20
7-21

Contents ix

Base Instruction Set
8.1

Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

8-1

8.2

Instruction Formats ....................................... .

8-4

8.3

Byte Instructions ......................................... .

8-8

8.4 List of Instructions ....................................... .
8.4.1
Single-Operand ........................................ .
8.4.2
Double-Operand ....................................... .
8.4.3
Program Control ........................................ .
8.4.4
Miscellaneous ......................................... .
8.4.5
Condition Code Operators ................................ .

8-8

8.5 Single-Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8.5.1
General .............................................. .
8.5.2
Shifts and Rotates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5.3
Multiple-Precision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PSW Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8.5.4

8-9
8-10
8-10
8-12
8-12
8~13

8-13
8-19
8-24
8-28

8.6 Double-Operand Instructions ................................ 8-30
8.6.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-30
8.6.2
Logical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-37
8.7 Program Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Branches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8.7.1
Signed Conditional Branches ..............................
8.7.2
Unsigned Conditional Branches ............................
8.7.3
8.7.4
Jump and Subroutine Instructions . . . . . . . . . . . . . . . . . . . . . . . . ..
Traps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8.7.5
Miscellaneous Program Controls. . . . . . . . . . . . . . . . . . . . . . . . ..
8.7.5.1
Reserved
Instruction Traps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8.7.6
8.7.7
Trace Trap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

8-41
8-41
8-47
8-50
8-52
8-56
8-61
8-63
8-64

8.8

Miscellaneous Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-65

8.9

Condition Code Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-69

Floating-Point Arithmetic
9.1

Introduction ............................................ .

9-1

9.2 Floating-Point Data Formats ............................... .
Nonvanishing Floating-Point Numbers ...................... .
9.2.1
Floating-Point Zero ..................................... .
9.2.2
Undefined Variables .................................... .
9.2.3
Floating-Point Data .................................... .
9.2.4

9-1
9-1
9-2
9-2
9-2

9.3

Floating-Point Status Register (FPS) ......................... .

9-2

9.4

Floating Exception Code and Address Registers ................. .

9-6

9.5

Floating-Point Instruction Addressing ........................ .

9-7

9.6

Accuracy . . . . . . . . . . ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-8

x Contents

9.7
Floating-Point Instructions. . . . . . . . . . . . • . . . . . . . . . . . . . . . . . .. . . 9~9
9.7.1
Terms Used in Instruction Definitions ....................... 9-10

Programming Techniques
10.1 Introduction............................................. 10-1
10.2 Position-Independent Code (PIC) ............................. 10-1
10.2.1 Use of Addressing Modes in the Construction of
Position-Independent Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-1
10.2.2 Comparison of Position-Dependent and Position-Independent Code. 10-3
10.3 Stacks.................................................. 10-5
10.3.1 Pushing onto a Stack .................................... 10-5
10.3.2 Popping from a Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-6
10.3.3 Deleting Items from a Stack ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-7
10.3.4 Stack Uses ............................................ 10-8
10.3.5 Stack Use Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-9
10.3.6 Subroutine Linkage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.3.6.1
Return from a Subroutine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.3.6.2
Subroutine Advantages ................................. 10-12
10.3.7 Interrupts ............................................. 10-12
10.3.7.1
Interrupt Service Routines ...... ~ . . . . . . . . .. . . . . . . . . . . . . . 10-12
Nesting ............................................. 10-13
10.3.7.2
10.3.8 Reentrancy ............................................ 10-13
10.3.8.1
Reentrant Code ....................................... 10-14
10.3.8.2
Writing Reentrant Code ................................ 10-15
10.3.9 Coroutines ............................................. 10-13
10.3.9.1
Coroutine Calls ....................................... 10-16
10.3.9.2
Coroutines Versus Subroutines ........................... 10-16
10.3.9.3
Using Coroutines ...................................•. 10-17
10.3.10 Recursion ............................................. 10-19
10.3.11 Processor Traps ......................................... 10-21
10.3.11.1 Trap Instructions ................................... ,'. 10-22
10.3.11.2 Use of Macro Calls ................. . . . . . . . . . . . . . . . . . . . 10-23
10.3.12 Conversion Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 10-24
lOA

Programming the Processor Status Word . . . . . . . . . . . . . . . . . . . . . . . 10-28

10.5 Programming Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28
10.6 PDP-11 Programming Examples ............................. 10-29
. 10.7 Looping Techniques ........................................ 10-37

Contents xi

Setup Parameters Worksheet
A1

Original Setup Menu Worksheet - Video Terminal Support

A-2

New Setup Menu Worksheet - Video Terminal Support ........... .

A-3

Original Worksheet - Hard Copy Printer Support ................ .

A-4

A.4

New Worksheet - Hard Copy Printer Support ................... .

A-5

Index
Examples
4-1
4-2
4-3
4-4

Main Menu ...................................
Boot Command .......................
Diagnostic Command ..
Help Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5 List Command (Q-bus System) .........
4-6 Map Command ..........
4-7 Setup Command
4-8 Setup Mode Command 1 ..............
4-9 Setup Mode Command 2 ......
4-10 Setup Mode Command 3 - Select Diagnostic Configuration
4-11 Setup Mode Command 4 ...
4-12 Setup Mode Command 5 - Boot Parameters Menu ...
4-13 Setup Mode Command 6 (UNIBUS System) ..
4-14 Setup Mode Command 6 (Q-bus System)
4-15 Setup Mode Command 7
4-16 Setup Mode Command 8 ............
4-17 Setup Mode Command 9
4-18 Setup Mode Command 10 ..
4-19 Setup Mode Command 11 ..
4-20 Setup Mode Command 12 - Save a Boot Program in the EEPROM ...
4-21 Setup Mode Command 13 ..
4-22 Setup Mode Command 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-23 TOY Command ..............
4-24 Setup Menu .............
4-25 Resident-Supported Boot Devices ................
4-26 Self-Test Menu ..............
4-27 User Boot Menu ........
4-28 Map Menu ...................
4-29 Self-Test Menu ................
4-30 Self-Test Menu ................
4-31 Setup Menu .............
4-32 Selecting Individual Tests . . .
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4-2
4-5

4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-22
4-24
4-25
4-28
4-29
4-30
4-30
4-31
4-31
4-32
4-34
4-34
4-35
4-35
4-37
4-38
4-42
4-44
4-45
4-48
4-49
4-50
4-51

xii

Contents

Figures
1-1 Programming Model ...... , ........ '.' ............... '...... ~ 1-3
1-2 Processor Status Word Register .............. ~ ... ~ ........... . 1-5
1-3 CPU Error Register ....................................... . 1-7
1-4 Program Interrupt Request Register (17777772) ........ ~ ........ . 1-8
1-5 16-Bit Mapping .......................... '.' ............... . 1-13
1-6 18-Bit Mapping .......................................... . 1-13
1-7 22-Bit Mapping .......................................... . 1-14
1-8 Virtual Address Mapping into Physical Address ................. . 1-15
1-9 Interpretation of a Virtual Address ........................... . 1-16
1-10 Displacement Field of a Virtual Address ....................... . l-16
1-11 Construction of a Physical Address ....................... ~ .... . 1-17
1-12 Active Page Register ...................................... . 1-18
1-13 Page Address Register .................................... . 1-20
1-14 Page Descriptor Register ............................ '.' .... '.' 1-21
1-15 Memory Management Register 0 (Ml'4RO) ......•................ 1-22
1-16 Memory Management Register 1 (MMRl) ... " .. '.' ............... . 1-23
1-17 Memory Management Register 3 Format (17772516) ............. . 1-24
1-18 Typical Memory Page (17772516),' ........................... . 1-26
1-19 Nonconsecutive Memory Pages ............ '.' ................ . 1-28
1-20 Typical Stack ~emory Page ... '. '.' ........ '.' ................ . 1-29
1-21 Memory System Error Register Format (17777744) .............. . 1-30
1-22 Cache Control Register For~at (17777746) ... ',' .........•.. '.' .. . 1-30
1-23 Parity CSR Register (17772100) •............................. 1-31
1-24 KDJII-E Jumper and PIP Switch Locations ..................... . 1-35
1-25 Receiver Status Register Format (1777xxxO) ................... . 1-37
1-26 Receiver Data Buffer Register Format (177.7xxx2) ............... . 1-37
1-27 Transmitter Status Register Format (1777xxx4) ................. . 1-38
1-28 Transmitter Data Buffer Register Format (1777xxx6) ......•....... 1-39
1-29 Control/Status Register Format (17777520) .................... . 1-42
1-30 Page' Control Register Format (17777522) ..........•... ~ ...... . 1-45
1-31 Boot and Diagnostic Configuration Register Format (17777524 Read-Only) .......................... '.' '.' ............... . 1-45
1-32 Boot and Diagnostic Display Register Format (17777524 ~ Write-Only) 1-46
1-33 Additional Status Register (17777526) ........................ . 1-46
1-34 Clock Status Register Format (17777546) ...................... . 1-47
1-35 Maintenance Register Format (17777750) ...................... . 1-48
2-1 KDJII-E Jumper and DIP Switch Locations .................... . 2-2
2-2 KDJI1-E Switch Configuration .............................. . 2-4
2-3 Switch Connections for Connector J2 ......................... . 2-5
2-4 KDJI1-E Module Contacts ................................. . 2-10
4-1 KDJII-E CPU Module Layout .............................. . 4-63
5-1 DATI Bus Cycle .............................. '.' . ~ ......... . 5-5
5-2 DATI Bus Cycle Timing ................................... . 5-6
5-3 DATO or DATO(B) Bus Cycle ............................... . 5-8
5-4 DATO or DATO(B) Bus Cycle Timing ......................... . 5-9

Contents - xiii

DATIO or DATIO(B) Bus Cycle .............................. .
DATIO or DATIO(B) Bus Cycle Timing ........................ .
5-7 DMA RequestJGrant Sequence ............... '.' ............. .
5-8 DMA RequestJGrant Bus Cycle Timing ........................ .
5-9 Interrupt RequestiAcknowledge Sequence ...................... .
5-10 Interrupt Protocol Timing .................................. .
5-11 Position-Independent Configuration .......................... .
5-12 Position-Dependent Configuration ............................ .
5-13 Bus Line Termination ..................................... .
5-14 Single-Backplane Configuration ............................. .
5-15 Multiple-Backplane Configuration ........................... .
7-1 Single-Operand Addressing ................................. .
7-2 Double-Operand Addressing ................................ .
7-3 Mode 0, Register ......................................... .
7-4 Mode 2, Autoincrement .................................... .
7-5 Mode 4, Autodecrement .................................... .
7-6 Mode 6, Index ........................................... .
7-7 INC R3 ................................................ .
7-8 ADD R2,R4 ............................................ .
7-9 COMBR4 ............................................. .
7-10 CLR (R5)+ ........................... ; .................. .
7-11 CLRB (R5)+ ............................................ .
7-12 ADD(R2)+,R4 ........................................... .
7-13 INC -(RO) .............................................. .
7-14 INCB -(RO) ............................................. .
7-15 ADD -(R3),RO ............................................ .
7-16 CLR 200(R4) ............................................ .
7-17 COMB 200(R1) .......................................... .
7-18 ADD 30(R2),20(R5) ............. ' .......................... .
7-19 Mode 1, Register-Deferred ..................... '.' ........... .
7-20 Mode 3, Autoincrement-Deferred ............................ .
7-21 Mode 5, Autodecrement-Deferred ............................ .
7-22 Mode 7, Index-Deferred .................................... .
7-23 CLR@R5 .............................................. .
7-24 INC @(R2)+ ............................................ .
7-25 COM @-(RO) ............................................ .
7-26 ADD @1000(R2),R1 ...................................... .
7-27 ADD #10,RO ............................................ .
7-28 CLR @#1100 ............................................ .
7-29 ADD @#2000 ............................................
7-30 INC A .................................................
7-31 CLR @A ................................................
8-1 Single-Operand Group .....................................
8-2 Double-Operand Group 1 ...................................
8-3 Double-Operand Group 2 ...................................
8-4 Program Control Group Branch ..............................

5-5

5-6

5-11
5-12
5-14
5-15
5-18
5-19
5-21
5-21
5-26
5-29
5-30
7-3
7-3
7-4

7-5
7-5
7-5

7-6
7-7

7-7
7-8
7-8
7-9
7-9
7-10
7-10
7-11
7-12
7-12
7-13
7-13
7-14
7-14
7-15
7-15
7-16
7-16
7-18
7-18
7-19
7-20
7-21
8-4
8-4
8-5
8-5

xiv Contents

8-5 Program Control Group JMP .... "... c•• ; • • • • • • • • • • • • • • • • • c' • • • •
8-6 Program Control Group JSR ............... ~
8-7 Program Control Group RTS ...
8-8 Program Control Group Traps ..
8-9 Program Control Group Subtract ..
8-10 Mark ...............
~"o
8-11 Call to Supervisor Mode
o.
8-12 Set Priority Level ...
8-13 Operate Group.
8-14 Condition Group ..
~
8-15 Move To and From Previous Instruction/Data Space Group .
8-16 Byte Instructions
8-17 Clear Destination
o.
8-18 Complement Destination
8-19 Increment Destination .
~
o.
8-20 Decrement Destination
o.
8-21 Negate Destination ...
8-22 Test Destination .....
8-23 ReadILock Destination, WritelUnlock RO into Destination o.
o.
8-24 Test Destination and Set Low Bit ..
8-25 Arithmetic Shift Right .
8-26 Example: Arithmetic Shift Right
8-27 Arithmetic Shift Left.
o.
8-28 Example: Arithmetic Shift Left ..
8-29 Rotate Right ........
8-30 Example: Rotate Right
~
8-31 Rotate Left .......
8-32 Example: Rotate Left .
8-33 Swap Bytes ..
8-34 Multiple-Precision ...
8-35 Add Carry ...
8-36 Subtract Carry ....
8-37 Sign Extend ........................
8-38 Move Byte from Processor Status Word .....
8-39 Move Byte to Processor Status Word ........
8-40 Move Source to Destination
8-41 Compare SRC to Destination ......
8-42 Add SRC to Destination ....
8-43 Subtract SRC from DST ..
8-44 Arithmetic Shift .....................
8-45 Arithmetic Shift Combined .............
8-46 Multiply ...........................
8-47 Divide ..............
8-48 Bit Test ................
8-49 Bit Clear ..................
8-50 Bit Set ..................
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8-6
8-6
8-6
8-6
8-7
8-7
&-7
8-7
8-8
8-13
8-14
8-15
8-15
8-16
8-17
8-18
8-18
8-19
8-19
8-20
8-20
8-21
8-21
8-22
8-22
8-23
8-24
&-25
8-26
8-27
8-28
8-29
8-30
8-31
8-32
8-33
8-34
8-35
8-36
8-36
8-37
8-38
8-39

Contents xv

8--51 Exclusive .OR ...........................
8-52 Branch (Unconditional) .
o.
8--53 Branch if Not Equal (to Zero) .......
8-54 Branch if Equal (to Zero) ........................
8-55 Branch if Plus .....
8-56 Branch if Minus ........
8-57 Branch if Overflow is Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8--58 Branch if Overflow is Set ..............
8-59 Branch if Carry is Clear ................
8-60 Branch if Carry is Set ......................
8-61 Branch if Greater Than or Equal (to Zero) . . . . . . . . . . . . . . . . . . . . ..
8-62 Branch if Less Than (Zero)
8-63 Branch if Greater Than Zero.
8-64 Branch if Less Than or Equal (to Zero)
8-65 Branch if Higher ............
8-66 Branch if Lower or Same .....
8-67 Branch if Higher or Same ...
o.
8-68 Branch if Lower ............
8-69 Jump ...............................
8-70 Jump to Subroutine .....................
8-71 Example: Jump to Subroutine ...............
8-72 Return from Subroutine .......
8-73 Example: RTS R5 ..............
8-74 Subtract One and Branch ......
8-75 Emulator Trap ...........
8-76 Example: Emulator Trap.
8-77 Trap .......................
8-78 Breakpoint Trap ...................
8-79 Input/Output Trap ....................
8-80 Return from Interrupt ...................
8-81 Return from Trap ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8-82 Mark .................................
8-83 Example: Mark ..............
8-84 Set Priority Level .................
8-85 Call to Supervisor Mode ..............
8-86 Halt .........................................
8-87 Wait for Interrupt ............
8-88 Reset External Bus .........................
8-89 Move from Processor Type Word ..........
8-90 Move to Previous Data Space (Bit 15 =1)
Move to Previous Instruction Space (Bit 15 =0) ......................
8-91 Move from Previous Data Space (Bit 15 = 1)
Move from Previous Instruction Space (Bit 15 =0) .........
8-92 Condition Code Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9-1 Single-Precision Format .........................
9-2 Double-Precision Format ..................
9-3 2's Complement Format .......
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8-42
8-43
8-44
8-44
8-45
8-45
8-46
8-46
8-46
8-48
8-48
8-49
8-49
8-50
8--50
8-51
8--51
8--52
8--53
8-54
8-55
8--55
8--56
8--57
8--57
8-58
8--58
8--59
8-59
8-60
8-61
8-61
8-62
8-63
8-65
8-66
8-66
8-67
8-67
8-68
8-69
9-3
9-3
9-4

xvi

Contents

9-4 Floating-Point Status Register. . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . 9-4
9-5 Floating-Point Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9-6 Make Absolute FloatingIDouble ............................... 9-11
9-7 Add FloatinglDouble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-12
9-8 Copy Floating Condition Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-13
9-9 Clear Floating/Double. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ... . . . . .. 9-13
9-10 Compare Floating/Double. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-14
9-11 Divide FloatinglDouble . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 9-15
9-12 Load and Convert From Double-To-Floating
and from Floating-to-Double ..................................... 9-16
9-13 Load and Convert Integer or Long Inte,ger
to Floating or Double-Precision ........ . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-17
9-14 Load Exponent, ................... '.' . . . . . . . . . . . . . . . . . . . . .. 9-18
9-15 Load FloatingIDouble .................... '. . . . . . . . . . . . . . . . .. 9-19
9-16 Load Floating-Point Program Status .......................... 9-19
9-17 Multiply and Separate Integer and Fraction FloatingIDouble ....... 9-20
9-18 Multiply FloatinglDouble ................................... 9-22
9-19 Negate Floating/Double .................................... 9-23
9-20 Set Floating Double mode .................................. 9-23
9-21 Set Floating Mode. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. 9-24
9-22 Set Integer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-24
9-23 Set Long Integer Mode. . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . ... .. 9-24
9-24 Store and Convert from Floating-To-Double and from
Double-To-Floating ..................' . . . . . . . . . . . . . . . . . . . . .. 9-25
9-25 Store and Convert from Floating-to-Double To Integer Or Long Integer 9-26
9-26 Store Exponent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-27
9-27 Store Floating/Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-27
9-28 Store Floating-Point Program Status. . . . . . . . . . . . . . . . . . . . . . . . .. 9-28
9-29 Store FPP's Status ........................................ 9-28
9-30 Subtract Floating/Double ................................... 9-29
9-31 Test Floating/Double . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. 9-30
10-1 Word and Byte Stacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-6
10-2 Push and Pop Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-7
10-3 Byte Stack Used as a Character Buffer. . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10-4 JSR Stack Condition Example ............................... 10-11
10-5 Nested Interrupt Service Routines and Subroutines . . . . . . . . . . . . . . . 10-13
1.0-6 Reentrant Routines ........................................ 10-14
10-7 Sharing Control of a Routine ................................. 10-15
10-8 Coroutine Example ........................................ 10-16
10-9 Coroutines Versus Subroutines ............................... 10-17
10-10 Coroutine Path ........................................... 10-18
10-11 Coroutine Interaction ...................................... 10-19
10-12 Recursive Routine Flow .................................... 10-20

Contents -xvii

Tables
1-1 General Purpose Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2 Stack Pointer (PSW <15:14 or <13:12» .........................
1-3 Processor Status Word Bit Description. . . . . . . . . . . . . . . . . . . . . . . . .
1-4 CPU Error Register Bit Descriptions ..........................
1-5 Program Interrupt Register Bit Descriptions ....................
1-6 KDJ11-E Interrupts .......................................
1-7 KDJ11-E Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1-8 Memory Management Register Address. . . . . . . . . . . . . . . . . . . . . . ..
1-9 Page Descriptor Register Bit Description .................... ". ..
1-10 MMRO Bit Description ..............
1-11 Memory Management Register 3 Bit Descriptions ................
1-12 Memory System Error Register Bit Descriptions .................
1-13 Cache Control Register Bit Descriptions.
1-14 Parity CSR Register (17772100) .......
1-15 ConsolelSLU Panel - SLU 8 ......
1-16 Receiver Status Register Bit Descriptions
1-17 Receiver Data Buffer Register Bit Descriptions ...............
1-18 Transmitter Status Register Bit Descriptions ..
1-19 Transmitter Data Buffer Register Bit Descriptions. . . . . . . . . . . . . . ..
1-20 ConsolelSLU Register Settings - Base Address 176500 ....
1-21 ConsolelSLU Register Settings - Base Address 176600 .........
1-22 Control/Status Register Bit Descriptions.
1-23 Page Control Register Bit Descriptions .. o. . . . . . • . . • . . . . . . • . . . ••
1-24 Display Register Bit Descriptions ..... ' 0 • • • • • • • • • • • • • • • • • • • • o.
1-25 Additional Status Register
1-26 Clock Status Register Bit Descriptions ..
1-27 Maintenance Register Bit Descriptions ..............
o.
1-28 Recognition Pattern ....
2-1 Baud Rate Selections ...............
2-2 ROM Mode Switch Settings ...................
2-3 KDJ11-E Module and LSI-11 Bus Signals ......
2-4 Module PMI Signal Assignments ..........
2-5 J1, Connector Pin Assignments
2-6 J2, Connector Pin Assignments ..............
2-7 J3, Connector Pin Assignment~ .....
3-1 Console ODT Commands ....
4-1 ROM Code Interpretation of User Input .........
4-2 Boot Command Errors ..
4-3 Memory Intern Parameter Variations ...........
4-4 ROM on 173000 Parameter Variations .....
4-5 ROM on 165000 Parameter Variations ..
4-6 ROM Mode Switch Settings .........
4-7 Power-On Self-Tests Parameter Variations .....
4-8 Alternate Boot Block Parameter Variations ..
4-9 LTC Register Parameter Variations ...........................
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1-3
1-5
1-5
1-7
1-8
1-9
1-14
1-18
1-21
1-23
1-24
1-30
1-31
1-31
1-33
1-37
1-37
1-38
1-39
1-39
1-40
1-42
1-45
1-46
1-46
1-48
1-49
1-50
2-6
2-6
2-10
2-12
2-13
2-14
2-16
3-2
4-4
4-5

4-14
4-14
4-14
4-16
4-16
4-17
4-17

xviii

Contents

4-10 Force Clock Interrupt Parameter Variations
4-11 Clock Frequency Parameter Variations
4-12 Halt-on-Break Parameter Variations
4-13 Trap-oil-Halt Parameter Variations
4-14 Ignore Battery Parameter Variations
4-15 Lines On Parameter Variations
4-16 Disable UBA ROM Parameter Variations
4-17 Enable UBA 18-Bit Mode Parameter Variations
4-18 Default Boot Programs ...
4-19 ROM Mode
4-20 ROM ODT Commands .
4-21 Moving Through Menus ........
4-22 Types of Function Fields .
4-23 Setup Menu Configuration Parameters
4-24 Diagnostic Programs
4-25 LED Display Messages and Descriptions
4-26 Error Messages .
4-27 CPU Troubleshooting ...............
5-1 Summary Of Signal Line Functions .
5-2 Data Transfer Bus Cycles .
5-3 Data Transfer Bus Signals
5-4 Position-Independent, Multilevel Device Requirements
6-1 PMI Bus Master Signals .....
6-2 PMI Slave Signals.
6-3 PMI UNIBUS Adapter Signals
6-4 LSI Bus Signals .
7-1 Sample KDJ11-E Instructions
8-1 Instruction Set .
9-1 FPS Register Bit Descriptions
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4-33
4-36
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4-52
4-60
4-64
5-1
5-3

5-4
5-20
6-2
6-2
6-3

6-4
7-3
8-1
9-5

About This Manual
This user guide contains descriptions of the KDJ11-E CPU module architecture,
configuration, system requirements, and programming.

Audience
This manual is intended for Digital Customer Services, self-maintenance, and Original
Equipment Manufacturing (OEM) personnel.

Organization
This manual contains ten chapters, an appendix, and an index.
•

Chapter 1, Architecture, describes the KDJ11-E CPU module architecture.

•

Chapter 2, Configuration, describes the configuration requirements when configuring
and installing the KDJII-E CPU module into an LSI-1I based system.

•

Chapter 3, Console On-Line Debugging Technique (ODT), describes ODT.

Chapter 4, Boot ROMs and Diagnostics, describes diagnostics that test the CPU, UBA
and memory; the chapter also includes hard copy ROM commands.

•

Chapter 5, Extended LSI-1I Bus, describes the LSI-1I bus.

•

Chapter 6, Private Memory Interconnect Bus, describes PMI protocol, and PMI bus
signals.

•

Chapter 7, Addressing Modes, describes the addressing modes.

•

Chapter 8, Base Instruction Set, describes the KDJ1I-E instruction set.

•

Chapter 9, Floating-Point Arithmetic, describes floating-point instructions.

•

Chapter 10, Programming Techniques, describes utilizing the combination of the
instruction set, addressing mode and programming techniques to develop new
software or to utilize old programs effectively.

•

Appendix A, Setup Parameters Worksheet, contains two worksheets for each mode
(video terminal or hardcopy) to record the original setup parameter selections and the
new setup parameters selections contained in the EEPROM of the KDJI1-E module.

COnventions
The following conventions are used in this manual:
Convention

Meaning

Caution

Contains information to prevent damage to equipment

xix

xx About This Manual

Convention

Meaning

Note

Contains general information

<x:y>

Represents a bit field, a set of lines, or a set of signals, ranging from
x through y. For example, RO <7:4> indicates bits 7 through 4 in a
general-purpose register RO.

RIW
R

ReadlWrite

Read-only

Read

1
Architecture

1.1 KDJ11·E CPU Module Description
The KDJII-E is a quad-height processor module for LSI-II bus systems. It is designed
for use in high-speed, real-time applications, and multiuser, multitasking environments.
The module can also operate as a CPU in PDP-II UNIBUS systems, when used in
conjunction with the KTJII-B UNIBUS adapter module.
The module interfaces to the standard 22-bit LSI bus and has the additional control
signals necessary for communication using the Private Memory Interconnect (PMI). The
PMI protocol uses the CID interconnect bus and allows high-speed data transfers across
the bus, including double-word reads. The LSI bus can address up to 4 Mbytes of main
memory.. Block mode direct memory access (DMA) transfers (allowed. on the extended
bus) aresu,pported by the KDJII-E module.
The KDJII-E module executes the complete PDP-I1J70 base instruction set, including
the. extended instruction set (EIS) and the MTPS, MFPS,. MFPT, CSM, TSTSET, and
WRTLCK instructions. ·It also supports the FPII floating-point instruction set that is
compatible with FPII-A, -C, -E, and -F floating-point processors. Full 22-bit memory
management is provided for both instruction references and data references in three
protection modes: kernel, supervisor, and user.
The three protection modes provide the ability to implement layered software protection.
Memory management separately manages the three modes, allowing each one to ,access
different sections of main memory. Each section can also have different access protection
rights. Each mode uses a separate system stack. pointer that offers an additional degree
of isolation. The protection modes are organized so that a higher protection mode
can always enter a lower protection mode, while a lower protection mode can never
accidentally enter a higher protection mode. Kernel mode has full privileges and can
execute all instructions~ . Supervisor mode and user mode, the two lower-privileged
modes, cannot execute certain instructioJ;ls.

Features
The KDJI1;.Esystem module is a high performance CPU module with the following
features:
•

DCJll microprocessor

•

Floating-point accelerator (FPJll)

•

22-bit memory management

•

Programmable line frequency clock

•

Console serial line unit
1-1

1-2 Architecture

•

Seven serial line units (SLUs)

•

Boot and diagnostic ROMs

•

Time of Year (TOY) clock

•

Two or four Mbytes onboard parity memory

•

Console programmable setup features

•

Comprehensive self-test capability

•

LED status indicator

The boot and diagnostic ROM features include:
•

Booting of the user's software on various devices

•

Memory size display

•

Time and date of TOY clock

•

Boot device selection

•

Ability to define parameters for SLUs

•

Self-test selection

•

User boot area on EEPROM

•

Support for hard copy terminals and video display terminals

Self-diagnostic display LEDs are provided on the KDJ11.;E module. They indicate the
status of the module and system when the module is powered up. The LEDs aid in
troubleshooting module failures.
Figure 1-1· shows the user-addressable registers, classified as general purpose, system
control, memory system, floating-point and Memory Management Registers (MMRs).
The KDJ11-E module supports console emulation (micro-ODT). This allows users to
interrogate and write main memory and CPU registers as if a console switch panel and
display lights were available.

1.2 DCJ11-A Microprocessor Features
The DCJ11-A microprocessor operates in three modes: kernel, supervisor, and user.
A program operating in the kernel mode has complete control of the system and
incorporates protection mechanisms against any external interferences. Programs
operating in the supervisor and user modes can be inhibited from executing certain
instructions and can be denied direct access to the system peripherals. This feature
provides complete executive protection in a multiprogram environment.
There are 16 general purpose registers (Table 1-1), but only 8 are addressable to the
user at any given time. The general-purpose registers provide a stack pointer (SP)
for each of the three operating modes and a program counter. (PC). The remaining 12
registers are divided into two groups of general purpose registers, RO-R5 and RO'-R5'.
All of these registers can be used as accumulators, deferred addresses, index references,
autoincrement registers, autodecrement registers, and stack pointers.

Architecture 1-3

General Purpose

System Control

RO'

KSP

R1'

SSP

R2'

USP

R3'

R4'

R5'

GJ I

Memory System

SLU

PSW

II Une Clock

PIRQ

Maint
_......11 Cache Ctrl II RBUF 1-8
II......_

I Memory CSR I I RCSR 1-8

Mem Sys Err

CPU Error

Hit/Miss
Floating Point

XCSR 1-8

II XBUF 1-8

Memory Management

~~~

MMRO

MMR1

MMR211 MMR31
Boot and Diagnostics

Accumulators (64-Bit)
Page Registers (32-Bit)
Kemal (00)
PAR

PDR

Supervisor (01 )

User (11)

PAR

PDR

ControVStatus

Page control

Cont and Disp

Additional
Status Reg
LJ-00154-TIO

Figure 1-1

Programming Model

Table 1-1

General Purpose Registers

Designation

RO'

Rl'

R2'

Ra'

R4'
R5'

KSP. SSP
PC

USP

The system control registers are the processor status word (PSW), program interrupt
request (PIRQ), and CPU error register.

1-4 Architecture

1.2.1 Stack-Limit Protection
The DCJ11 monitors the kernel stack references against the fixed lim~t of 400. A yellow
stack trap occurs. at the end of the current instruction when the aqdress of the stack
reference is less than 400. A yellow stack trap can only occur in the kernel mode during
a stack reference. This is defined as a mode 4 or 5 reference through R6, a JSR trap, or
an interrupt stack push.
The microprocessor also checks for kernel stack aborts during interrupts, traps, and abort
sequences .. When a kernel stack push causes an abort during one of these conditions, a
red stack trap occurs. This type of stack trap sets bit 2 in the CPU error register and
loads virtual address 4 into the kernel stack pointer (R6). A trap through location 4 in
the kernel space now occurs and the old PC and PSW are saved in locations 0 and 2,
respectively, of the kernel space.

1.2.2 Kernel Protection
The following mechanisms are used to protect· the kernel operating system against
external interference:
•

In kernel mode, the HALT,RESET, and SPL instructions are executed as specified.
In supervisor or user mode, the HALT instruction causes a trap through location 4,
but the RESET and SPL instructions are treated as NOPs.

•

In kernel mode, the RTI and RTr instructions can freely change bits <15:11> and
<7:5> of the PSW register. In supervisor or user mode, these instructions can change
only bits <15:11> of the PSW register.

•

In kernel mode, the MTPS instruction can change bits <7:5> of the PSW register. In
supervisor or user mode, the MTPS instruction cannot change bits <7:5> of the PSW
register.

•

All the trap and interrupt vector addresses are classified as kernel space addresses,
no matter what memory management mode the system is using or what the contents
of the PSW are at the time the interrupt or trap occurs.

•

Kernel stack references are checked for stack overflow, but supervisor and user stack
references are not checked.

1.2.3 General Registers
There are two groups of six registers, designated RO-R5 and RO'-R5'. The group
currently in use is selected by bit 11 in the PSW. When bit 11 is set (1), the RO'-R5'
group is selected. When bit 11 is cleared (0), the RO-R5 group is selected.

1.2.4 Stack Pointer
Register six (R6) is designated as the system stack pointer. There are three stack
pointers available, one for each corresponding protection mode. However, only one is
visible to the user at a given time. Processor status bits 14 and 15 select the active stack
pointer used for all instructions except MFPI, MFPD, MTPI, and MTPD. When these
instructions select R6 as the destination register, bits 12 and 13 of the PSW select the
active stack pointer. In both cases, the 2-bit selection codes described in Table 1-2 are
used to select the active register.

Architecture -1-5

Table 1-2 Stack Pointer (PSW <15:14 or <13:12»
Code

Selected R6

Kernel stack pointer (KSP)

Supervisor stack pointer (SSP)

10
11

illegal-User stack pointer selected
User stack pointer (USP)

1.2.5 Program Counter
The program counter (PC) contains the 16-bit address of the next instruction to be
accessed. It is designated as R7 and controls the sequencing of instructions. The PC is
directly addressable by 'single- and double-operand instructions and is a general purpose
register, although normally it is not used as an accumulator.

1.2.6 Processor Status Word (17777776)
The processor status word (PSW) provides the current and previous operational modes,
the general purpose register group being used, the current priority level, the condition
code status, and the trace trap bit used for program debugging. The PSW is initialized
at power-up and is cleared with a console start. Figure 1-2 shows the PSW register.
Table 1-3 describes the PSW bits.
15

LJ-00148-TIO

Figure 1-2

Processor Status Word Register

Table 1-3 Processor Status Word Bft Description
Bits

Name

Status

Function

<15:14>

Current mode

RJW

Indicates the current operating mode and is
coded as follows:

Bit
15

Mode

Kernel

Supervisor

illegal

User

1-6 Architecture

, Table 1-3 (Cont.) Processor Status Word Bit Description
Bits

Name

Status

Function

<i3:12>

Previous
mode

RIW

Indicates the previous operating mode and
is coded the same as bits <15:14>.

RIW

Selects the group of general purpose
registers being used. When the bit is
set, the RO'-R5' group is selected and when
cleared, the RO-R5 group is selected.

<10:9>

Unused

Read as Os.

Suspended
information

R
RIW

<7:5>

Priority

RIW

Indicates the current priority level of the
processor and is coded as follows:

Reserved.

Bit

Priority
Level

5
4

RIW

The trap bit is inactive when it is cleared.
When set, the processor traps to location 14
at the end of the current instruction. It is
useful for debugging programs and setting
breakpoints.

Negative

RIW

Condition code N is set when the previous
operation result was negative.

Zero

RIW

Condition code Z is set when the previous
operation result was O.

Overfiow

RIW

Condition code V is set when the previous
operation resulted in an arithmetic
overflow.

Carry

RIW

Condition code C is set when the previous
operation caused a carry out.

lThe T-bit cannot be set by explicitly writing to the PSW; it can only be changed by the RTIIRTT instructions.

Architecture

1-7

1.2.7 CPU Error. Register (17777766)
The error register, at address 17777766, identifies the source of any abort or trap that
caused a trap through location 4. The CPU error register is cleared when it is written. It
is also cleared at power-up or by console start. The CPU error register is unaffected by a
RESET instruction. Figure 1--3 shows the register format. Table 1-4 provides the CPU
error register bit descriptions.
15

Address Error
Nonexisitent Memory
110 Bus Timeout-----""
Yellow Stack Violation - - - -......

Red Stack Violation

---------.1
LJ-00149-TIO

Figure 1-3

CPU Error Register

Table 1-4 CPU Error Register Bit Descriptions
Bits

Name

Status

Function

Dlegal HALT

Set when execution of a HALT instruction
is attempted in user or supervisor mode.

Address Error

Set when word access to an odd byte
address or an instruction fetch from an
internal register is attempted.

Nonexistent
Memory

Set when a reference to main memory times
out.

I/O Bus
Timeout

Set when a reference to the I/O page times
out.

Yellow Stack
Violation

Set on a yellow zone stack overflow trap.

Red Stack
Violation

Set on a red zone stack overflow trap.

1.2.8 Program Interrupt Request Register (177/1172)
The program interrupt request register (PIRQ), at location 17777772, implements a
software interrupt facility. When a program interrupt request is granted, the processor
traps through location 240. It is the responsibility of the interrupt service routines
to clear the appropriate bit in PffiQ before exiting. PIRQ is cleared at power-up by a
console start and by the RESET instruction. Figure 1-4 shows the register. Table 1-5
provides the program interrupt register bit descriptions.

1-8 Architecture
15

Priority Encoded
Value of Bits <15.9>

PIR7
PIR6

Priority Encpded
Value of Bits <15.9>

PIR5
PIR4 - - - - - - '
PIR3 - - - - - - '
PIR2 - - - - - - - - '
PIR1 - - - - - - - - - '
LJ.OOUIOoTIO

Figure 1-4

Program Interrupt Request Register (1n77772)

Table 1-5 Program Interrupt Register Bit Descriptions
Bits

Name

Function

<15:09>

PIR 7-1

Each bit, when set, provides one of seven levels of
software interrupt, corresponding to interrupt priority
levels 7 through 1.

Unused

Read as O.

<07:05>

Priority encoded
value of bits <15:09>

These three bits are set by the CPU to the encoded value
of the highest pending interrupt request (bits <15:09».

Unused

Read as O.

<03:01>

Priority encoded
value of bits <15:09>

The function of these bits is identical to bits <07:05>.

1.3 Interrupts
The KDJII-E module uses a variety of trap, hardware, and software interrupts.
Table 1-6 lists the KDJII-E interrupts in order of their priority. Four interrupt request
lines allow external hardware to interrupt the processor on four interrupt levels using
an externally supplied vector. Seven levels of software interrupt requests are supported
through use of the PIRQ register. A variety of internally vectored traps are provided to
flag error conditions, and certain instructions result in a trap condition.
Interrupts and traps are requests that cause the KDJII-E to temporarily suspend the
execution of the current program, and service the· device or condition that caused the
interrupt or trap. The KDJII-E has eight levels of interrupt priority and the current
priority level is defined by bits <07:05> of the processor status register. Therefore, only
interrupts with a higher priority than the current priority can interrupt the current
program. The only exception to this is the nonmaskable interrupt or trap that occurs
independently of the processor priority. These nonmaskable interrupts have their own
priority structure (Table 1-6).

Architecture -1-9

Table 1-6 KDJ 11·E Interrupts
Internal
!External

Vector
Address

Red stack trap
(CPU error register, bit 2)

Internal

NMI

Address error
(CPU error register, bit 6)

Internal

Memory management violation
(MMRO, bits <13:15»

Internal

250

Timeout/nonexistent memory
(CPU error register, bits <4:5»

Internal

Parity error (PARITY, ABORT)

Internal

114

Trace (T-bit) trap (PSW, bit 4)

Internal

Yellow stack trap
(CPU error register, bit 3)

Internal

Power fail (PWRF)

External

FP exception (FPE)

External

244

PIR 7 (PIRQ, bit 15)

Internal

240

IRQ 7

External

Userdefined

PIR 6 (PIRQ, bit 14)

Internal

240

BEVNT(LTC)

External

100

IRQ 6

External

Userdefined

PIR 5 (PIRQ, bit 13)

Internal

240

IRQ 5

External

Userdefined

PIR 4 (PIRQ, bit 12)

Internal

240

IRQ 4

External

Userdefined

SLU 1, receive

Internal

300/400

SLU 2, receive

Internal

310/410

SLU 3, receive

Internal

320/420

SLU 4, receive

Internal

330/430

SLU 5, receive

Internal

340/440

SLU 6, receive

Internal

350/450

SLU 7, receive

Internal

360/460

SLU 8, receive(Console)

Internal

SLU 1, transmit

Internal

3041404

SLU 2, transmit

Internal

3141414

SLU 3, transmit

Internal

3241424

Interrupt

INM = Nonmaskable

Priority Level

1-10 Architecture

. Table 1-6 (Cont.) KDJ11-E Interrupts
Interrupt

Internal
!External

Vector
Address

Priority Level

SLU 4, transmit

Internal

3341434

SLU 5, transmit

Internal

3441444

SLU 6, transmit

Internal

3541454

SLU 7, transmit

Internal

3641464

SLU 8, transmit(Console)

Internal

PIR 3 (PIRQ, bit 11)

Internal

240

PIR 2 (PIRQ, bit 10)

Internal

240

PIR 1 (PIRQ, bit 9)

Internal

240

Halt line (HALT~

External

None

FP instruction exception

244

TRAP (trap instruction)

EMT (emulator trap instruction)

lOT (110 trap instruction)

BPT (breakpoint trap instruction)

CSM (call to supervisor mode
instruction)

HALT instruction

WAIT (wait-for-interrupt
instruction)

Does not trap, but frees the bus when waiting for external
interrupt.

2The halt line usually has the lowest priority. However, it has the highest priority during vector reads. This
allows the user to break out of potential infinite loops called sunset loops. A sunset loop could occur if a vector
has not been properly mapped during memory management operations.

1.3.1 Sunset Loops
A sunset loop is an infinite loop caused by illegally mapped vectors. The following sunset
loops can be exited by asserting the BHALT input:
Interrupts

Cause

Parity
error

Bad parity in the parity vector

Trace trap

Trace vector has T-bit set

All PIRQs

PIRQ vector priority level does not block that level

Aborts

Any abort that occurs during a service routine such as reading the vector or pushing
onto the stack. These include nonexistent memory, 110 timeouts, MMU aborts,
parity aborts, and odd address aborts.

Sunset loops that cannot be exited are caused by external inputs that are not being reset
or cleared. These can be MPWRF L, MFPE L, MIRQ <3:0> H, and MEVNT L.

Architecture

1-11

1.3.2 Red Stac~ Aborts
A red stack abort happens when an abort sequence occurs while pushing the PC and
PSW onto the kernel stack while in the process of servicing an interrupt, an abort, or
a trap routine. This type of abort sets bit 2 of the CPU error register, loads the kernel
stack pointer (R6) with virtual address 4, and then traps through location 4 in the kernel
space. The old PC and PSW are saved in locations 0 and 2 of the kernel space.
The service routine to clear bit 2 of the CPU error register reads the vector at virtual
address 4 in the kernel space. An emergency stack is then set up in the new mode at
virtual address 4 and executes a trap through virtual address 4. This ensures that the
old PC and PSW are saved in kernel space locations 0 and 2.

1.3.3 Addressing Errors
An addressing error occurs when an odd address is used with a word reference (odd
address error), or an instruction stream fetch attempts to access an internal processor
register. The internal processor registers are the PDRs, PARs, CPU error, PSW, PIRQ,
MMRO-MMR3, HitJMiss, and CCR. When an addressing error happens, it sets bit 6 of
the CPU error register and traps through virtual address 4 of the kernel data space.

1.3.4 Bus Timeout Errors
A bus timeout error occurs if the BRPLY L bus signal is not asserted within 12.8l'seconds
after the KDJ11-E asserts the BDIN Lor BnOUT L signals. The 110 page timeout
error sets bit 4 of the CPU error register if the address references the 110 page. The
nonexistent memory timeout error sets bit 5 of the CPU error register for all other
address errors. As a result of the error condition, the KDJ11-E traps through virtual
address 4 of the kernel space. In a UNIBUS system, the KDJ11-E does not time out, but
relies on the UNIBUS adapter module to assert the PMI timeout signal.

1.3.5 Interrupt Vector Timeouts
An interrupt vector timeout occurs if the BRPLY L bus signal is not asserted within

12.8 I'seconds after the KDJI1-E acknowledges an interrupt by asserting the BIAK L
bus signal. The timeout is ignored by the KDJ11-E and it continues as if the interrupt
request did not occur. In a UNIBUS system, the KDJ11-E does not time out, but relies
on the UNIBUS adapter module to assert the PMI timeout signal.

1.3.6 No SACK Timeouts
The no SACK (selection acknowledge) timeout occurs when the BSACK L bus signal is
not asserted within 12.8 ,",seconds after the KDJ11-E grants a DMA request by asserting
BDMG L. The timeou.t is ignored by the KDJI1-E and it continues as if the DMA request
did not occur.

1.4 Memory Management
KDJII-E memory inanagement provides the hardware for complete memory management
and protection. It is designed to be a memory management facility for accessing all of the
physical memory and for multiuser, multiprogramming systems where memory protection
and relocation facilities are necessary.

1-12 Architecture

In multiprogramming environments, several user programs are resident in memory at
any given time. The supervisory program includes the following tasks:
•

Control the execution of the various user programs

•

Manage the allocation of memory and peripheral device resources

•

Safeguard the integrity of the system as a whole by controlling each user program

In a multiprogramming system, memory management provides the means for assigning
memory pages to a user program and for preventing that user from making any
unauthorized access to pages outside his assigned area. Thus, a user can effectively
be prevented from accidental or willful destruction of any other user program or of the
system executive program.
The following are the basic characteristics of KDJII-E memory management:

•
•
•
•
•
•
•
•
•
•

16 user mode memory pages
16 supervisor mode memory pages
16 kernel mode memory pages
8 pages in each mode for instructions
8 pages in each mode for data
Page lengths from 64 to 8192 bytes
Each page has full protection and relocation
Transparent operation
3 modes of memory access control
Memory access to 4 Mbytes

1.4.1 Memory Mapping
The processor can perform 16-, 18-, or 22-bit address mapping. The· 110 page, which is
the uppermost 4K words of memory, always uses the physical address locations 17760000
to 17777777.
1.4.1.1 16·81t Mapping
There is a direct mapping relocation from virtual to physical addresses. The lowest 28K
virtual addresses are the same corresponding physical addresses. The 110 page physical
addresses are in the upper 4K block (Figure 1-5).

Architecture 1-13

17777777
4K

1n60000'
17n77
160000

001577n

Virtual
(16 Bits)

28K

.....
_ _ _ _ _~ _ _ _ _ _ _ _ . . .10.....
_ _ _ _ __..1
OO~O
O~OOOO

Incoming Address

Physical Address
Space (22 Bits)
U-00161-TIO

Figure 1-5

16-81t Mapping

1.4.1.2 18-81t Mapping

Each of the three modes: kernel, supervisor, and user, are allocated 32K addresses
that are mapped into 128K words of physical address space. The lowest 124K words of
physical memory, or the 110 page, can be seen in Figure 1-6.
1.4.1.3 22-81t Mapping

This mode uses the full 22-bit address to access all of the physical memory. The upper
4K block is still the 110 page (Figure 1-7).
17777777
4K

17760000

00757777

1n777
Virtual
(16 Bits)

000000
.....
_ _ _ _ _--a. - - - - - - - Incoming Address

124K

Mem
Mgmt

00000000
_ _ _ _ _.......

Physical Address
Space (22 Bits)
LJ-00162-TIO

Figure 1-6

18-811 Mapping

1-14 Architecture

17n7777
4K
17760000

1n5nn
177777
2044K

Virtual
(16 Bits)

1--......

Mem
Mgmt

'------.... - - - - - - - - ......_---_
Incoming Address
Physical Address
00000000

000000

Space (22 Bits)
LJ-00153-TIO

Figure 1-7

2~-Blt Mapping

1.4.2 Compatibility
The operation of 16-, 18-, and 22-bit mapping can be used to provide compatibility among
other PDP-II computers. This means that software written and developed for any
PDP-11 computer can be run on the KDJ11-E (Table 1-7).
Table 1-7 KDJ11-E Compatibility
Mapping

Memory
Mauagement

System

16-Bit

Off

PDP-11105, -11110, -11115, -11120, -11103

IS-Bit

PDP-11135, -11140, -11145, -11150, -11160, -11123

22-Bit

PDP-11194, -11184, -11no, -11144, -11124,
PDP-11193, -1118S, -lInS, -1115S, -1112S+

1.4.2.1 Vlnual Addressing
When memory management is operating, the normal 16-bit address is no longer
interpreted as a direct physical address, but as a virtual address containing information
to be used in constructing a new 22-bit physical address. The information contained in
the virtual address is combined with relocation inforIllation contained in the page address
register to yield a 22-bit physical address (Figure 1-8). Using memory management,
memory can be dynamically allocated in pages, each composed of 1 to 128 integral blocks
of 64 bytes.
The starting physical address for each page is an integral multiple of 64 bytes, and each
page has a maximum size of 8192 bytes. Pages may be located anywhere within the
physical address space. The determination of which set of 16 page registers is used to
form a physical address is made by the current mode of operation (kemel, supervisor, or
user mode) and by whether the reference is for instructions or data.

Architecture 1-15

Physical Address
Registers

Page 5

Virtual Instruction/Data
Address Space
32K

Page 6

PAR 7

PAR 6

-...

PAR 5
PAR 4
PAR 3
PAR 2

Page 7

Page 4

PAR 1

PAR 0
Virtual Address
(16 Bits)

Page Address Registers

Physical Address
(22 Bits)

PAR:: Page Address Register
LJ.00155·TIO

Figure 1-8

Vlnual Address Mapping Into Physical Address

1.4.3 Interrupts Under Memory Management
Memory management relocates all addresses. When it is enabled, all traps, aborts, and
interrupt vectors are mapped using the data-space mapping registers in kernel mode.
Therefore, when a vectored transfer occurs, the new PC and PSW are obtained from
two consecutive words physically located at the trap vector, and are mapped using the
data-space registers in kernel mode.
The stack used for the push of the current PC and PSW is specified by bits <15:14> of
the new PSw. The PSW mode bits also determine the new mapping register set. This
allows the kernel mode program to have complete control over servicing all traps, aborts,
or interrupts. The kernel program may assign the service of some of these conditions to a
supervisor or user mode program by simply setting the- mode bits of the new PSW in the
vector to return control to the appropriate mode.
1.4.3.1 Construction of a Physical Address

All addresses with memory relocation enabled either reference information in instruction
(I) space or data (D) space. 1 space is used for all instruction fetches, index words,
absolute addresses, and immediate operands; D space is used for all other references.
1 space and D space each have eight page address registers (PARs) in each mode of
CPU operation (kernel, supervisor, and user). MMR3 can disable D space and map all
references (instructions and data) through 1 space, or can enable D space and map all
references through both I and D space.
The basic information needed for the construction of a physical address comes from the
virtual address (Figure 1-9), and the a~propriate PAR set.

1-16 Architecture

The virtual address (VA) consists of the following fields:
•

The active page field (APF). This 3-bit field determines which of the eight page
address registers from the set PARO-PAR7 is used to form the physical address.

•

The displacement field. This 13-bit field contains an address relative to the beginning
of a page. The longest page length is 8 Kbytes as determined by the 13 bits. The
displacement field is further subdivided into two fields (Figure 1-10).
15

I :APF : I __________________
: : : : : :OF:------------------J
: : : : : I
~

~\~

Active Page
Field

Displacement Field
W·OC)156·TIO

Figure 1-9

Interpretation of a Virtual Address

I : : :BN: : : I : : +: : I
12

"-_ _ _ _ _ _y_-----...,J"-----_y_----J
Block Number

Displacement in Block
W.oo157·TlO

Figure 1-10

Displacement Field of a Virtual Address

The displacement field consists of the following:
•

'rhe block number. This 7-bit field is interpreted as the block number within the
current page.

•

The displacement in block. This 6-bit field contains the displacement within the block
referred to by the block number.

The remainder of the information needed to construct the physical address comes from
the contents of the PAR referenced by the page address field (PAF). This 16-bit register
specifies the starting address of the memory page. The PAF is actually a block number in
the physical memory. For instance, if PAF is 3 it indicates a starting address of 96 (3 x
32 words in physical memory).
Figure 1-11 illustrates the construction of the physical address (PA). The logical sequence
involved in constructing a PA is as follows:
1. The APF of the VA selects one of eight page address registers (PARO-PAR7) from
the appropriate set. The set used depends on the space being referenced and the
protection mode being used.

2. The PAF of the selected PAR contains the starting address of the currently active
page as a block number in physical memory.
3. The block number from the VA is added to the PAF to yield the number of the block
in physical memory. These are bits <21:6> of the PA being constructed.

Architecture 1-17

4. The displacement in block from the displacement field of the VA is joined to the
physical block number to yield a true 22-bit PA
15

v~ual _ _ 1 :

15
Select PAR

Page (VA)

PbysblAdd __

I::I
I::::::::::::I
I : : ~S: : : : : : I
15

+PAF

Offset Into

1 : : :5 ~ : : : : : : : : : : : I
W-00158·TIO

Figure 1-11

Construction of a Physical Address

1.4.4 Memory Management Registers
Memory management implements three sets of thirty-two 16-bit registers (Figure 1-12).
One set of registers is used in kernel mode, another in supervisor mode, 8l)d the other in
user mode. The protection mode in use determines which set is to be used. Each set is
subdivided into two groups of 16 registers. One group is used for references to instruction
(I) space, and one to data (D) space.
The I space group is used for all instruction fetches, index words, absolute addresses,
and immediate operands. The D space group is used for all other references, providing
it has not been disabled by MMR3. Each group is further subdivided into two parts of
eight registers. One part is the PAR whose function is described in the following section.
The other part is the page descriptor register (PDR). PARs and PDRs are always selected
in pairs by the top three bits of the virtual address. A PARJPDR pair contains all the
information needed to describe and locate a currently active memory page.
The MMRs are in the uppermost 8 Kbytes of physical address space, which is designated
as the 110 page. Table 1--8 lists the addresses allocated to the MMRs.

1-18 Architecture

15 114

Kernel (00)

PAR

PDR

Supervisor (01)

PAR

User (11)

PDR

PAR

PDR

I Space

PAR

PDR

PAR

PDR

PAR

PDR

o Space

'If

,
LJ·OO159-110

Figure 1-12

Active Page Register

Table 1-8 Memory Management Register Address
Register

Address

Memory management register 0 (MMRO)

17777572

Memory management register 1 (MMR1)

17777574

Memory management register 2 (MMR2)

17777576

Memory management register 3 (MMR3)

17772516

User I space descriptor register (UISDRO)

17777600

Architecture 1-19

Table 1-8 (Cont.) Memory Management Register Address

Address

User I space descriptor register (UISDR7)

17777616

User D space descriptor register (UDSDRO)

17777620

User D space descriptor register (UDSDR7)

17777636

User I space address register (UISARO)

17777640

User I space address register (UISAR7)

17777656

User D space address register (UDSARO)

17777660

User D space address register (UDSAR7)

17777676

Supervisor I space descriptor register (SISDRO)

17772200

Supervisor I space descriptor register (SISDR7)

17772216

Supervisor D space descriptor register (SDSDRO)

17772220

Supervisor D space descriptor register (SDSDR7)

17772236

Supervisor I space address register (SISARO)

17772240

Supervisor I space address register (SISAR7)

17772256

Supervisor D space address register (SDSARO)

17772260

1-20 Architecture

Table 1-8 (Cont.) Memory Management Register Address
Register

Address

Supervisor D space address register (SDSAR7)

17772276

Kernel I space descriptor register (KISDRO)

17772300

Kernel I space descriptor register (KISDR7)

17772816

Kernel D space descriptor register (KDSDRO)

17772320

Kernel D space descriptor register (KDSDR7)

17772336

Kernel I space address register (KISARO)

17772340

Kernel I space address register (KISAR7)

17772356

Kernel D space address register (KDSARO)

17772360

Kernel D space address register (KDSAR7)

17772376

1.4.4.1 Page Address Register (PAR)

The PAR contains the PAF, a 16-bit field that specifies the starting address of the page as
a block number in physical memory.
The PAR (Figure 1-13) contains the PAF that, may be alternatively thought of as a
relocation register containing a relocation constant, or as a base register containing a
base address. These registers are not changed by either console starts or by the RESET
instruction. They are undefined at power-up ..
15

+: : : : : : : I
00

I:::::::

LJ·0018Q. TIO

Figure 1-13

Page Address Register

Architecture

1-21

1.4.4.2 Page Descriptor Register (PDR)

The PDR contains information relative to page expansion, page length, and access
control. Figure 1-14 shows the page descriptor register. Table 1-9 describes the bits.
15

Bypass
Cache

Page Length Field

Page Written

Expansion
Direction
LJ-001S1-TIO

Figure 1-14

Page Descriptor Register

Table 1-9 Page Descriptor Register Bit Description
Bit

Name

Status

Function

Bypass cache

RJW

This bit implements a conditional cache bypass
mechanism. If the PDR accessed during
a relocation operation has this bit set, the
reference goes directly to main memory. Read
or write hits result in invalidation of the
accessed cache location.

<14:8>

Page length field

RJW

This field specifies the block number that
defines the page boundary. The block number
of the virtual address is compared against the
page length field to detect length errors. An
error occurs when expanding upwards, if the
block number is greater than the page length
field, and when expanding downwards, if the
block number is less than the-page field.

Unused

Read as o.

Page written

The written into bit (W-bit) indicates whether
the page has been written into since it was
loaded in memory. When this bit is set,
it indicates a modified page. The W-bit is
automatically cleared when the PAR of that
page is written.

<5:4>

Unused

Read as O.

Expansion
direction

RJW

This bit specifies the direction in which the
page expands. If it equals 0, the page expands
upward from block number 0 to include blocks
with higher addresses; if it equals 1, the page
expands downward from block number 127 to
include blocks with lower addresses.

1-22 Architecture

, Table 1-9 (COnt.) Page Descriptor Register Bit Description
Bit

Name

Status

Function

Access control
field

R/W

This field contains the access code for this
particular page. The access code specifies
the manner in which a page may be accessed
and whether or not a given access should
result in an abort of the current operation.
Implemented codes are as follows:
00
01
10
11

Unused

Nonresident - abort all accesses
Read only
- abort on write
Not used
- abort all accesses
Read/write access

Read as O.

1.4.5 Fault Recovery Registers
Aborts generated by the memory management hardware are vectored through kernel
virtual location 250. MMRs 0, 1, 2, and 3 are used to determine why the abort occurred
and to allow for program restarting.
NOTE

An abort to a location which is itself an invalid address causes another abort.
Thus, the kernel program must ensure that kernel virtual address 250 is
mapped into a valid address. Otherwise, a loop requiring console intervention
occurs.
1.4.5.1 Memory Management Register 0 (17777572)

MMRO provides control and records memory management unit status. The register
contains abort and status flags (Figure 1-15). Table 1-10 describes the bits.
15

14
I

Abort Read-Only
Access Violation

'----y---J

Page Mode

Page Number

"--_ _ Abort Page
Length Error
Abort
" - - - - - - Non-Resident

Page Address
Space 110

Enable Relocation

LJ-00162-TIO

Flgurt 1-15

Memory Management Register 0 (MMRO)

Architecture

1-23

Table 1-10 MMRO Bit Descriptio.,
Bit

Name

Status

Function

Nonresident
abort

RJW

Bit 15 is set by attempting to access a page with
an access control field key equal to 0 or 2. It is also
set by attempting to use memory relocation with a
processor mode (PSW <15:14» of 2.

Page
length
abort

RJW

Bit 14 is set by attempting to access a location in
a page with a block number (virtual address bits
<12:6» that is outside the area authorized by the
page length field of the PDR for that page.

Read only
abort

RJW

Bit 13 is set by attempting to write in a read-only
page. Read-only pages have access keys of 1.

<12:7>

Not used

Read as Os.

<6:5>

Processor
mode

Bits <6:5> indicate the processor (kernel, supervisor,
user, illegal) associated with the page causing the
abort (kernel = 00, supervisor = 01, user = 11, illegal
= 10). If the illegal mode is specified, an abort is
generated and bit 15 is set.

Page space

Bit 4 indicates the address space (lor D) associated
with the page causing the abort (0 = I space, 1 = D
space).

<3:1>

Page
number

Bits <3:1> contain the page number of the page
causing the abort.

Enable
relocation

RJW

Bit 0 enables relocation. When it is set to 1, all
addresses are relocated. When it is set to 0, memory
management is inoperative and addresses are not
relocated.

IBits <15:13> can be set by an explicit write. However, such an action does not cause an abort. Whether set
explicitly or by an abort, setting any bit in bits <15:13> causes memory management to freeze the contents of
MMRO <6:1>, MMR1, and MMR2. The status registers remain frozen until MMRO <15:13> is cleared by an
explicit write.

1.4.6 Memory Management Register 1 (17777574)
MMR1 records any autoincrement or autodecrement of a general purpose register,
including explicit references through the PC. The increment or decrement amount by
which the register was modified is stored in 2's complement notation. The lower byte is
used for all source operand instructions and the destination operand may be stored in
either byte, depending on the mode and instruction type. The register is cleared at the
beginning of each instruction fetch. The register is defined in Figure 1-16.
15

LJ-00163-TIO

Figure 1-16

Memory Management Register 1 (MMR1)

1-24 Architecture

1.4.6.1 Memory Management Register 2 (17777576)
MMR2 is loaded with the program counter of the current instruction and is frozen when
any abort condition is posted in MMRO.
1.4.6.2 Memory Management Register 3 (17772516)
Memory management register 3 (MMR3) at address 17772516 enables or disables D
space, 22-bit mapping, the Call Supervisor Mode (CSM) instruction, and the IJO map
(when applicable). MMR3 is cleared at power-up by a console start and by a RESET
instruction. Figure 1-17 shows the register format. Table 1-11 provides memory
management register 3 bit descriptions.
15

000

Enable CSM Instruction - - - - - - - - - '
Enable Kernal Data Space _ _ _ _ _ _ _ _....J
Enable Supervisor Data Space _ _ _ _ _ _ _ _- - 1
Enable User Data Space - - - - - - - - - - - -......
LJ·00164·TIO

Figure 1-17

Memory Management Register 3 Format (17772516)

Table 1-11 Memory Management Register 3 Bit Descriptions
Bits

Name

<15:06>

Unused

Enable UNIBUS
Map

RJW

This bit enables the 110 map for the UNmUS
adapter (UNmUS systems only).
-

Enable 22-bit
mapping

RJW

This bit, when set, selects 22-bit memory
addressing. When this bit is clear, 18-bit
addressing is selected. (Only when MMRO
bit <0> is set is 18- or 22-bit addressing actually
enabled.)

Enable CSM
instruction

RJW

This bit enables recognition of the Call
Supervisor Mode (CSM) instruction.

<2:0>

Enable data space

RJW

These three bits enable data space mapping for
kernel, supervisor, and user mode, respectively.

Status

Function
Read as Os.

1.4.6.3 Instruction Back-Up and Restart Recovery
The process of backing up and restarting a partially completed instruction involves the
following steps:

1. Performing the appropriate memory management tasks to alleviate the cause of the
abort (for example, loading a missing page).
2. Restoring the general purpose registers indicated in MMRI to their contents at the
start of the instruction, by subtracting the modify value specified in MMRI.

Architecture 1-25

3. Restoring the PC to the abort-time PC by loading R7 with the contents of MMR2,
which contains the value of the virtual PC at the time the "abort-generating"
instruction was fetched.
Note that this back-up and restart procedure assumes that the general-purpose register
used in the program segment will not be used by the abort recovery routine. This is
automatically the case if the recovery program uses a different general-purpose register
set.
1.4.6.4 Clearing Status Reg Isters Following Abort

At the end of a fault service routine, bits <15:13> of MMRO must be cleared (set to 0) to
resume error checking. On the next memory reference following the clearing of these bits,
the various registers resume monitoring the status of the addressing operations. MMR2
is then loaded with the next instruction address, MMRI stores the register change
information, and MMR~ logs the memory management status information.
1.4.6.5 Multiple FauHs

After an abort occurs, any subsequent errors occurring while the memory management
registers are still frozen do not change MMRO, MMRl, or MMR2. The information saved
in MMRO to MMR2 always refers to the first abort that it detected.

1.4.7 Common Usage Examples
The memory management provides a general-purpose memory management tool. It can
be used in a manner as simple or as complex as desired. It can be anything from a simple
memory expansion device to a complete memory management facility.
The versatility offered by the memory management means that both single-user
and multiprogramming systems have complete freedom to make whatever memory
management decisions best suit their individual needs. Though there are more common
methods of using the memory management, there is no limit to the ways to use these
facilities can be used.
In typical applications, the control over the actual memory page assignments and their
protection resides in a supervisory program that operates in kernel mode.- This program
sets access keys in such a way as to protect itself from willful or accidental destruction by
other supervisor or user mode programs. The facilities are also provided in such a way
that the kernel mode program can dynamically assign memory pages of varying sizes in
response to system needs.
1.4.7.1 Typical Memory Page

When the memory management is enabled, kernel, supervisor, and user mode programs
each have eight active pages described by the appropriate PARs and PDRs for data and
eight pages for instructions. Each segment is made up of 1 to 128 blocks and is pointed
to by the PAF of the corresponding PAR (Figure 1-18).

1-26 Architecture

The memory segment in Figure 1-18 has the following attributes:
•

Page length: 40 blocks

•

Virtual address range: 140000-144777

•

Physical address range: 312000-316777

•

Nothing has been modified (that is, written) in the page

•

Read-only protection

•

Upward expansion

These attributes were determined according to the following scheme:
1. The page address register (PAR6) and page descriptor register (PDR6) were selected
by the APF of the VA (Bits <15:13> of the VA =6.)
VA 157777

PA331777

VA 144777
Block 47 (39 )
8
10

Block 1
PA 312000

Block 0

PAR6

3120
PAF

VA 140000

PoR6

~ 478 ~o f?}A10\1
PLF

ED ACF
LJ·OO185· TlO

Figure 1-18

Typical Memory Page (1m2516)

Architecture

1-27

2. The initial address of the page was determined from the PAF of PAR6 (312000 =
31208 blocks 40 (3210) words per block 2 bytes per word).
NOTE

The PAR that contains the PAF constitutes what is often referred to as a
base register containing a base address or a relocation register containing a
relocation constant.

a. The page length (47 + 1 =4010 blocks) was determined from the page length field
(PLF) contained in PDR6. Any attempt to reference beyond the 4010 blocks in this
page causes a page length error, which results in an abort, vectored through kernel
virtual address 250.
4. The PAs were constructed according to the scheme shown in Figure 1-11.

5. The W-bit indicates that no locations in this page have been modified (that is,
written). If an attempt is made to modify any location in this particular page, an
access control violation abort occurs. If the page is involved in a disk swapping or
memory overlay scheme, the W-bit is used to determine whether the page has been
modified and therefore requires saving before overlay.
6. The page is read-only protected (that is, no locations in the page may be modified).
The mode of protection was specified by the access control field of PDR6.
7. The expansion direction is upward (ED bit set to 0). If more blocks are required in
this segment, they must be added by assigning blocks with higher relative addresses.
The attributes that describe the page shown in Figure 1-48 are determined under
software control. The parameters describing the page are loaded into the appropriate
PAR and PDR under program control. In a normal application, the page, which itself
contains these registers, is assigned to the control of a kernel mode program.

1.4.7.2 Nonconsecutive Memory Pages
Higher virtual addresses do not necessarily map to higher physical addresses. It is
possible to set up the PAFs of the PARs so that higher virtual address blocks may be
located in lower physical address blocks as in Figure 1-19.
Although a single memory page must consist of a block of contiguous locations,
consecutive virtual memory pages do not have to be located in consecutive physical
address locations. The assignment of memory pages is not limited to consecutive
nonoverlapping physical address locations.

1-28 Architecture

VA 037777

PA467777

·I
I
I

·
PAR 7

VA 020000

PA 460000

VA 017777

PA 560777

PAF

I
I
I
PAR 1

PAF

PAR 0

PAF

VA 000000

PA 541000

LJ·00188·TIO

Flgure1-19

Nonconsecutive Memory Page.

1.4.7.3 Stack Memory Pages

When constructing programs, it is often desirable to isolate all program variables from
pure code (that is, program instructions) by placing them on a register indexed stack.
These variables can then be pushed or popped from the stack area as needed. Since
stacks expand by adding locations with lower addresses, when a memory page containing
"stacked" variables needs more room, it must expand down by adding blocks with lower
relative addresses to the current page. This mode of expansion is specified by s.etting the
expansion direction bit of the appropriate PDR to a 1. Figure 1-20 shows a typical stack
memory page and has the following parameters:
PAR6: PAF =3120
PDR6: PLF =1758 or 12510 (12810-3)

ED 1
W = 0 or 1
ACF = nnn (to be determined by the programmer as necessary)

In this case the stack begins 128 blocks above the relative origin of the memory page and
extends downward for a length of three blocks: A page length error abort is generated by
the hardware whenever an attempt is made to reference any location below the assigned
area (i.e., when the block number from the VA is less than the PLF of the appropriate
PDR).
NOTE

The W-bit is set by hardware.

Architecture

VA 157777

Block 177 (127 )
8
10

1-29

PA 331777

Block 175 (125 )
8
10
....,.........."....,......"....,......"....,.....,....,....,....,....,....,....,....,....,....,...,....,...........
PA 331500

VA 140000

PAR6
PAR 6

PA 312000

Block 0

PAF
SLF

l81W~E~
ACF
LJ-00167-TIO

Figure 1-20

Typical Stack Memory Page

1.4.8 Transparency
In a multiprogramming application, it is possible for memory pages to be allocated so that
a program appears to have a complete 64 Kbyte memory configuration. Using relocation,
a kernel mode supervisory-type program can perform all memory management tasks
which are entirely transparent to a supervisor or user mode program. In effect, a system
can use its resources to provide maximum throughput and response to a number of users.

1.5 KDJ11-E Memory System Implementation
Technological advances implemented on the KDJII-E allow the onboard memory to
perform at cache-like speeds, eliminating the need for cache. The KDJ11-E cache register
set has been implemented for compatibility purposes only and all bits should remain
cleared at all times.

1.5.1 Memory System Error Register (17777744)
The memory system error register (MSER), at address 17777744, reflects the status
of cache and main memory parity errors. Figure 1-21 shows the register format.
Table 1-12 provides memory system error register bit descriptions.

1-30 Architecture

I;~~I I
0

II II II IIII I I I I
MA·0330·90.DG

Figure 1-21

Memory System Error Register Format (177m44)

Table 1-12 Memory System Error Register Bit Descriptions
Bits

Name

Status

Function

CPU abort

This bit is set if a main memory parity error
results in an instruction abort (only during the
demand read cycle). Main memory parity errors
always cause an abort.

<14:00>

Unused

Read as Os.

Main memory parity errors always cause the CPU to abort the current instruction, set
MSER <15>, and trap through vector location 114.

1.5.2 Cache Control Register (17777746)
The cache control register (CCR) is at address 17777746. This register is used
for compatibility with former designs only. All bits should be cleared at all times.
Figure 1-22 shows the register format. Table 1-13 describes the cache control register
bits.
15

1 0 1 0 1 0 1 0 1 0 IMVIMVI

IMVIMVIMVIMVI I IAAVIMVI
FO~CE
I
MISS
FORCE

MISS
MA·0329·90.DG

Figure 1-22

Cache Control Register Format (17777746)

NOTE

During normal operations all bits should be cleared at all times.

Architecture

1-31

Table 1-13 Cache Control Register Bit Descriptions
Bits

Name

Function

<3:2>

Force Miss

When either bit is set, all CPU memory references go
directly to main memory. The cache tag and data stores
are not changed. The parity is not checked. When set (1),
these bits remove the cache memory from the system.

<14:00>

Unused

Read as Os.

1.5.3 Hit/Miss Register (17777752)
This register, at address 17777752, is for compatibility purposes only.

1.5.4 Parity CSR Register (17772100)
The parity control status register (CSR) is used to control parity checking. Parity
checking should only be enabled after the entire memory has been written to and the
right parity has been generated. Wrong parity can also be written for test purposes
(WWPAR). Figure 1-23 shows the register format. Table 1-14 describes the parity CSR
register (17772100).
15

I:~:I 0 I 0 I 0 10 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 1;::1 0 Ip:NRI
MA-0339-90.0G

Figure 1-23

Parity CSR Register (17772100)

Table 1-14 Parity CSR Register (17772100)
Bits

Name

Status

Function

PARER

RJW

Parity error. Bit 15 is set when a parity
error is detected in the main memory. Bit
15 is reset by a power-up, !NIT command.
This bit can also be written.

<14:03>

Unused

WWPAR

Unused

PAREN

Read as O.
RJW

Write wrong parity. When set, "wrong"
parity bits are written in to the main
memory with each write access made. This
provokes a parity error with each read
access that follows.
Read as O.

RJW

Parity checking enable. When set, parity
checking is enabled. When enabled, parity
errors detected will cause a parity trap.
This bit is reset by a power-up or INIT
command.

1-32 Architecture

1.6 Private Memory Interconnect
The private memory interconnect (PMI) is a unique Q22-bus protocol that provides a high
performance data path between the KDJII-E module and KTJII-B·(UNIBUS adapter
module) in UNIBUS systems. The PMI protocol functions in a UNIBUS system by using
the KTJII-B UNIBUS adapter module designed to interface with a PMI system. The
PMI interface consists of 14 control signals used on the C/D interface, 6 Q22-bus control
signals, the bank 7 select signal (BBS7) and the 22 data/address lines (BDAL <22:0». A
complete description of the PMI operation is provided in Chapter 6.

1.6.1 PMI Protocol
In a Q22-bus system, the KDJ11-E CPU is the default Q22-bus master and PMI master.
Any device on the Q22-bus that has the capability to be a bus master can take control
of the bus and execute normal data transfers over the Q22-bus. However, it does not
become the PMI master.
In a UNIBUS system, the KDJ11-E CPU is the default PMI master and the KTJ11B UNIBUS adapter is the default UNIBUS master. When the CPU, as PMI master,
references an I/O page address on the UNIBUS, the UNIBUS adapter responds as the
slave on the PMI and controls the UNIBUS side of the transaction as the UNIBUS
master.
The UNIBUS adapter can become the PMI master when the CPU issues a DMA grant
or performs an interrupt transaction. The DMA or interrupt grant is accepted by the
UNIBUS adapter and it becomes the PMI master and the UNIBUS slave. It also passes
the DMA or interrupt grant onto a UNIBUS device, which then becomes the UNIBUS
master. In UNIBUS systems, the bus master and PMI master can be requested by a
Nonprocessor Request (NPR) or interrupt request from a UNIBUS device, or by a DMA
or interrupt request.
1.6.1.1 Bus Device NPR

Any UNIBUS device that is capable of being a bus master can issue an NPR request
and become the bus master to control data transfers. During these data transfers, the
UNIBUS adapter is the PMI master and responds as a slave if the device accesses the
memory, the PMI 110 page, or the UNIBUS adapter 110 page.
1.6.1.2 Bus Device Interrupt

Any UNIBUS device that is capable of being a bus master can issue a BR7 through
BR4 request and become the bus master to control data or interrupt vector transfers.
In both cases, the UNIBUS adapter is the PMI master and responds as a slave if the
device performs an interrupt vector transaction or accesses memory, the PMI 110 page or
UNIBUS adapter 110 page.

1.6.2 PMI Data Transfers
There are three general categories for the PMI data transfer cycles:
•

Data In/Data In Pause (DATIIDATIP)

•

Block Data In (DATBI)

•

Data OutlData Out Byte (DATO/DATOB)

These three cycles are described in the following paragraphs.

Architecture

1-33

On the Q22-bus, the bus master can perform a read-modify-write cycle that transmits
an address, reads a data word or byte and then writes the data word or byte. The PMI
read-modify-write is performed by a DATIP cycle that is followed by a DATOIDATOB
cycle. The PMI bus master has the responsibility to control the-bus for the duration of
both cycles.
1.6.2.1 Data In/Data In Pause

The DATI and DATIP cycles are used to read one or two words when the PMI bus master
accesses the memory. When the PMI bus master accesses the I/O page it can only read
one word.
The PMI DATIP is identical to the DATI cycle except that TPBYT is asserted with
TADDR to indicate that the cycle immediately following the current cycle is going to be a
DATO cycle to the same address.
1.6.2.2 Block Data In

The DATBI cycle is used to read up to 16 words of data when the PMI bus master
accesses the memory. The PMI bus master cannot use the DATBI cycle when accessing
the I/O page.
The PMI bus master can only start DATBI transfers on even word boundaries. This
means that address bits <1:0> must be equal to Os. The PMI bus master cannot use the
DATBI cycle to transfer across 16-word address boundaries. This means that the PMI
bus master must terminate DATBI data transfers when it reaches a memory location
where the address bits <4:1> are all equal to Is.
1.6.2.3 Data Out/Data Out Byte

The DATO and DATOB cycles are used by the PMI bus master to transfer a single word
or byte to a PMI slave.

1.7 KDJ11-E Serial Line Units
The KDJ11-E has eight serial line units (SLUs). As a factory setting, SLU 8 is configured
as the console port, with a base addresslvector of 177560/60. Optionally, SLU 8 can follow
in ascending order after SLU s 1 - 7 as the eighth SLU or it can be set independently from
the other seven SLUs as the console/SLU.
NOTE

Modem control is not available.
Table 1-15 describes SLU 8.
Table 1-15 Console/SLU Panel - SLU 8
Switch 1
Setting

Function

Address

Vector

Off

Console
enabled

177560

Console
disabled

176570 (176670)

370 (470)

NOTE

Console SLU 8 has fixed parameters of eight data bits, no parity, and one stop
bit. The baud rate is determined by switches 6, 7, and 8.

1-34 Architecture

SLU lines 1-7 can be set independently from each other. See Chapter 4 for information
, on using the setup menu.

1-.7.1 Silo Buffer Length
The serial interfaces located on the KDJ11-E are "DL" type interfaces. Each line on
the KDJ11-E has a five-character silo. The silos were implemented on the KDJ11-E to
prevent overrun problems from occurring on heavily loaded systems. Serial characters
that are not picked by the operating systems under peak loading, are stored in these silo
buffers. If the operating system does not get around to these characters the silo buffer
will slowly be filled as other characters are being rec·eived.
The serial line interfaces are controlled by a dedicated processor and each line has a
five-character silo. This is a compromise between overrun protection'and operating
transparency. It is possible, however, to change the silo size on each line individually to
any value between two and 65 characters by modifying the firmware on the K.DJ11-E.
NOTE

It is explicitly emphasized that Digital Equipment Corporation does not support
any modules in which the original code in the EPROMs is modified. Therefore,
this modification should be performed by appropriately trained personnel only.
To modify the firmware on the KDJ11-E, the following is needed:

•

An EPROM programming device with the capability of editing individual bytes.

•

An empty EPROM that is the same type (27128) as the one on the module.

For each individual channel, there are three locations within the SLU EPROM that
contain the data that determines the buffer size. All three locations for each channel
must contain the same data. (For the location of the SLU EPROM see Figure 1-24).

Architecture

1-35

TOV BATTERV

EEPROM

BOOT
EPROM

KDJ11-E

~____~-r==,-~SLU

EPROM

)'11111111
Ioco~
I(GRN) I

0 0 0 1 000

OFF

POWER
(VEL)

~~~liUil~~~
1

3 4

•

SWITCHPACK

MA·0325·90.DG

DIAGNOSTIC
(RED)

Figure 1-24

KDJ11·E Jumper and DIP Switch Locations

Example for Channel 1:
Reference Field

Pointer

Actual Parameter

Address I Data

Address

Address I Data

070H:

CD 02

02CDH

02CDH:

072H:

E602

02E6H

02E6H:

4906

0649H:

08.

074H:

0649H

The addresses 70H, 72H, 74H point to where in the EEPROM the parameters are located,
and this location is where the new values are to be entered. A similar procedure is used
for the other seven channels. The fixed reference fields have the following addresses:

1-36 Architecture

Reference Field

Channel

070H, 072H, 074H

078H, 07AH, 07CH

080H, 082H, 084H

088H, 08AH, 08CH

090H, 092H, 094H

098H, 09AH, 09CH

OAOH, OA2H, OA4H

08AH, OAAH, EACH

All addresses are specified in a hexadecimal format. To determine from the parameter
data what the silo buffer size equals, use the following formula:
(Parameter data/2) + 1 =Silo Buffer Length
For example, if the Parameter data equals 8 (factory setting) then the silo buffer size
equals five.
8 divided by 2 equals 4, plus 1 equals 5.
To determine what the parameter should be, insert the desired silo buffer size into the
following formula:
(Silo Buffer Length - 1) x 2 =Parameter data

For example, if the desired buffer size equals 65, then the parameter data equals 128
decimal (80H).
65 minus 1 equals 64, times 2 equals 128
The valid range of parameters lies between 2 and 80H (128 decimal)·which corresponds
to effective buffer lengths of 2 to 65 characters. All three parameters per channel spread
throughout the EEPROM must be of the same value.

1.7.2 Serial Line Unit Registers
Each serial line unit has four registers:
•

Receiver status register

•

Receiver data buffer register

•

Transmitter status register

•

Transmitter data buffer register

These registers are described in the following sections.
1.7.2.1 Receiver Status Register (1777xxxO)

Figure 1-25 shows the Receiver Status Register (RCSR) format at address 1777xxxO.
Table 1-16 provides the receiver status register bit descriptions.

Architecture

1-37

MA-0334-90.0G

Figure 1-25

Receiver Status Register Format (1777xxxO)

Table 1-16 Receiver Status Register Bit Descriptions
Bits

Name

Status

Function

<15:08>

Unused,

RXDONE

Receiver Done. This bit is set when an
entire character has been received and is
ready to be read from the RBUF register.
This bit is automatically cleared when
RBUF is read. It is also cleared by powerup.

RX IE

RJW

Receiver Interrupt Enable. Thls bit is
cleared by power-up and bus initialization.
If both RCVR DONE and RCVR INT ENB
are set, a program interrupt is requested.

<05:00>

Unused

Read as Os.

1.7.2.2 Receiver Data Buffer Register (1777xxx2)

Figure 1-26 shows the receiver data buffer register (RBUF) format at address 1777xxx2.
Table 1-17 provides the receiver data buffer register bit descriptions.
15

IERRI~*=~I~~~I

11
0

I I I II I I I I I 1- I
\.

y
Received Data Bits

MA·0335·90.DG

Figure 1-26

Receiver Data Buffer Register Format (1777xxx2)

Table 1-17 Receiver Data Buffer Register Bit Descriptions
Bits

Name

Status

Function

ERR

Error. This bit is set if RBUF 14 or 13 is
set. ERR is cleared if these two bits are
cleared. This bit cannot generate a program
interrupt.

1-38 Architecture

. Table 1-17 (Cont.) Receiver Data Buffer Register Bit Descriptions
Bits

Name

Status

Function

OVRERR

Overrun Error. This bit is set if a
previously received character is not read
before being overwritten by the present
character.

FRMERR

Framing Error. This bit is set if the present
character has no valid stop bit. This bit is
used to detect a break.

NOTE
Error conditions remain present until the next character is received. At that point, the
error bits are updated. The error bits are not necessarily cleared by power-up.

Receiver
Parity Error

This bit is set when the parity received does
not match the parity expected.

<11:08>

Unused

Read as Os.

<07:00>

Received
Data Bits

These read-only bits contain the received
character.

1.7.2.3 Transmitter Status Register (1777xxx4)

Figure 1-27 shows the transmitter status register (XCSR) format at address 1777xxx4.
Table 1-18 provides the transmitter status register hit descriptions.
15

I I I I I I I I IR~YI7: I I I I I I~~
MA·0338·90.DG

Figure 1-27

Transmitter Status Register Format (1777xxx4)

Table 1-18 TransmHter Status Register BH Descriptions
Bits

Name

<15:08>

Unused

TXRDY

Transmitter Ready. This bit is cleared when
XBUF is loaded. The bit sets when XBUF
can receive another character. XMT RDY is
set by power-up and by bus initialization.

TXIE

RJW

Transmitter Interrupt Enable. This
bit is cleared by power-up and by bus
initialization. If both TX RDY and TX IE
are set, a program interrupt is requested.

<05:01>

Unused

XMITBRK

Status

Function
Read as Os.

Read as Os.

RJW

Transmit Break. When this bit is set,
the serial output is forced to the space
condition. XMIT BRK is cleared by powerup and by bus initialization.

Architecture

1-39

1.7.2.4 Transml~er Data B,ufferReglster (1777xxx6)

Figure 1-28 shows "the transmitter data buffer register (XBUF) format at address
1777xxx6. Table 1-19 contains the bit descriptions.
15

I 0 1 0 1

1009

10 1 0 1

10 10

IIIIIIIII
\-----------y-----------)
XBUF
W·OO168-TIO

Figure 1-28

Transmitter Data Buffer Register Format (1777xxx6)

Table 1-19 Transmitter Data Buffer Register Bit Descriptions
Bits

Name

<15:08>
<07:00>

Unused

XBUF

Status

Function
Read as Os.

These eight bits are used to load the transmitted
"character.
"

Table 1-20 describes the consolelSLU register settings for a data base address set at
176500.
Table 1-20 Console/SLU RegiSter Settings· Base Address 176500
SLU

Address

Vector

176500

RCSRI
RBUFI
XCSRI
XBUFI
RCSR2
RBUF2
XCSR2
XBUF2
RCSR3
RBUF3
XCSRS
XBUF3
RCSR4
RBUF4
XCSR4
XBUF4
RCSR5

300

17650~

176504
176506
176510
176512
176514
176516
176520
176522
176524
176526
176530
176532
176534
176536
176540

304
310
314
320
324
330
334
340

1-40 Architecture

Table 1-20 (Cont.) Console/SLU Register Settings • Base Address 176500

SLU

Address

176542
176544
176546
176550
176552
176554
176556
176560
176562
176564
176566
177560
177562
177564
177566

RBUF5
XCSRS
XBUF5
RCSR6
RBUF6
XCSR6
XBUF6
RCSR7

Vector

RBUF7
XCSR7
XBUF7
RCSR8
RBUF8
XCSRS
XBUF8

344
350
354
360
364
60
64

Table 1-21 describes the consolelSLU register settings for a data base address set at
176600.
Table 1-21

Console/SLU Register Settings· Base Address 176600

SLU

Address

Vector

176600
176602
176604
176606
176610
176612
176614
176616
176620
176622
176624
176626
176630
176632
176634

RCSR1
RBUF1
XCSR1
XBUF1
RCSR2
RBUF2
XCSR2

400

404
410
414

~UF2

RCSR3
RBUF3
XCSR3
XBUF3
RCSR4
RBUF4
XCSR4

420
424
430
434

Architecture

1-41

Table 1-21 (Cont.) Console/SLU Register Settings· Base Address 176600

SLU

Address

Vector

176636
176640
176642
176644
176646
176650

XBUF4
RCSR5
RBUF5

440

176652
176654
176656
176660
176662
176664
176666
177560
177562
177564
177566

RBUF6
XCSR6
XBUF6
RCSR7
RBUF7
XCSR7
XBUF7
RCSR8
RBUF8
XCSRS
XBUF8

XCSR5
XBUF5
RCSR6

444
450
454
460
464
60
64

1.7.3 Break Response
The KDJI1-E console serial line unit may be configured either to perform a halt operation
or to have no response when a break condition is received. A halt operation will cause
the processor to halt and enter the octal debugging technique (ODT) microcode. The
halt-on-break option is selected using the halt-on-break parameter in the setup menu.

1.8 Boot and Diagnostic Register Set
The following registers are used by the KDJI1-E ROM code:
•

Control/status register

•

Page control register

•

Configuration and display register

•

Additional status register

•

Maintenance register

These registers are described in the following paragraphs.

1-42 Architecture

1.8.1

Control/Statu~ Register (17777520)

The control/status register (CSR), at address 17777520, is both word and byte
addressable. Figure 1-29 shows the register fonnat. The CSR allows the boot and
diagnostic ROM programs to test battery backup status, to set parameters for the line
clock, to enable the console halt-on-break feature, and to enter or exit from standalone
mode .

The CSR also allows these programs to selectively disable the response of the boot and
diagnostic ROMs at addresses 17765000 through 17765776 or at addresses 17773000
through 17773776, or both, and to control read/write access to the EEPROM memory.
Programs that access the 110 page can use the CSR to alter the line clock parameters,
to enable or disable the halt-on-break feature, and to control access to the EPROM and
EEPROM memories.
15

DIS
73

DIS
65

RS365

Q-Bus
Only

LJ-00218-TIO

Figure 1-29

Control/Status Register Format (17777520)

Table 1-22 provides the control/status register bit descriptions.
Table 1-22 Control/Status Register Bit Descriptions
Bits

Name

Status

Function

BBRBE

Battery Backup Reboot Enable. When set,
this bit indicates that battery backup failed
to maintain voltages to the memory system
during the previous power failure. When
this bit is clear, it indicates that the system
does not feature battery backup, or that
battery backup maintained voltages during
the previous power failure. This signal
is received from backplane pin BHl and
latched when DC OK is asserted.

RBTPLS
Q-bus only

Reboot Pulse. This read-only bit is set (1)
when the DCOK input is pulsed by the
control panel switch or by a special Q22bus device. This bit is cleared (0) by the
negation of the POK input. A similar bit for
UNIBUS systems is used in the KTJII-B
CSR.

Architecture

1-43

Table 1-22 (Cont.) ControliStatus Register Bit Descriptions
Bits

Name

FRCLCIE

Force Line Clock Interrupt Enable. If
this bit is set, assertion of the signal
selected by CSR <11:10> and <1:0> will
unconditionally request interrupts. If FRC
LCIE is clear, assertion of the selected
signal will request interrupts only if the
line clock status register bit 6 (LCIE) is
set under program control. FRC LCIE is
cleared by the negation of DCOK.

DISLKS

Line Clock Status Register Disable. If this
bit is set, the line clock status register
(LKS) is disabled. If this bit is clear, LKS
is enabled and responds to bus address
17777546. LKS DIS is cleared by the
negation of DCOK.

11
10

CLKSELI
CLKSELO

Clock Select Bits 1 and o. These two bits
select the source of the line clock interrupt
request:

Status

Function

CLK SELl
of Interrupt

CLK SELO

Source

Power

On-

1
board 60 Hz

On-

supply
board 50 Hz

board 800 Hz
Both bits are cleared by the negation of
DCOK.

ENBHOB

Unused

DIS 73

BJW

Enable Halt-on-Break. When this bit is
set, the console serial line unit halt-onbreak feature is enabled. When this bit is·
clear, the feature is disabled. ENB HOB is
cleared by the negation of DCOK.
Read as o.

BJW

Disable 17773000. When this bit is set,
response of the 16-bit ROM memory to
addresses 17773000 through 17773776
is disabled, allowing the operation of an
external ROM that uses those addresses.
When DIS 73 is clear, the 16-bit ROMs
respond to those addresses, using the high
byte of the page control register as the most
significant address bits. DIS 73 is cleared
by the negation of DCOK.

1-44 Architecture

Table 1-22 (Cont.) Control/Status Register Bit Descriptions
Bits

Name

Status

Function

DIS 65

RJW

Disable 17765000. When this bit is set,
response of the boot and diagnostic 16bit and 8-bit ROM memory to addresses
17765000 to 17765776 is disabled; this
allows the operation of external ROM which
uses those addresses. When DIS 65 is clear,
the ROM memory selected by CSR bit 5
responds to those addresses, using the low
byte of the page control register as the most
significant address bits. DIS 65 is cleared
by the negation of DCOK..

RS365

When this read/write bit is set (1), the
EEPROM responds to addresses between
17765000 and 17765776, provided that bit
6 of the CSR is reset. When this bit 5 is
reset (0), then the ROM at these addresses
is selected instead. In both cases, the high
byte of the ROM address is made up of
the low byte of the PCR. The bit is reset
through the negation of the DCOK inputs.

RS3WE

When this read/write bit is set and the
CSR bit 5 is set with the CSR bit 6 reset,
then the program is able to write into
the EEPROM. This bit is reset through
power-up and initialization routines.

<03:00>

Unused

Read as Os.

1.8.2 Page Control Register (17n7522)
The page control register (PCR) is a read/write register that can be addressed by words
and bytes. Only the bits <15:9> and <7:1> can be used. The remaining bits will always
be read as Os. This register is reset through the negation of the nCOK input.
The PCR bits <15:9> become the ROM address bits <15:9> for the address area from
17773000 to 17773776 and together with the current address bits <8:0>, they make up a
16-bit address for the boot EPROM . The PCR bits <7: 1> becomes the EEPROM address
bits <15:9> for the addresses from 17765000 TO 17765766 and together with the current
address bits <8:0> they make up a 16-bit address for the EEPROM.
The control/status register (CSR) bits <7:4> control the access to the boot EPROM and
EEPROM.
Figure 1-30 shows the register format. Table 1-23 describes the page control register
bits.

Architecture

1-45

I I I I I I I I I I I II I I I I
y
~~------------------------)

~~----------y-----------)
Upper address

Upper address

173XXX

165 XXX
MA-Q333-90.0G

Figure 1-30

Page Control Register Format (17777522)

Table 1-23 Page Control Register Bit Descriptions
Bits

Name

Function

<15:09>

Upper address
173xxx

Used for address area 17773000 to 17773776.

Unused

Read as O.

<07:00>

Upper address
165xxx

Used for address area 17765000 to 17766766.

1.8.3 Configuration and Display Register (17777524)
The configuration and display register (CDR) consists of two independent registers which
are pointed to by the same address:
NOTE

Switch in the offposition is read as 1.
•

Read-only boot and diagnostic configuration register.
The read-only boot and diagnostic configuration register specifies the -status of the
configuration switches (8 to 1) that are located on the module. When· switches 8 to
1 on the KDJII-E are set to the off position, the state of the register bits can be
controlled using external switches. Figure 1-31 shows the register format.
15

X=Unused

8-Bit
Switch Pack
LJ-00169-TIO

Figure 1-31
Only)

Boot and Diagnostic Configuration Register Format (177n524 • Read·

1-46 Architecture

•

Write-only boot and diagnostic display register.
The write-only boot and diagnostic display register (BDR), at address 17777524,
allows the boot diagnostic programs to light the LEDs on the KDJ11-E module.
These display bits are also available on external connector J02. Bits <05:00> are
cleared on power-up (all LEDs on) by the negation of DCOK Figure 1-32 shows the
.
register format.
15

Ixlxl xl xlxl xlxlxlxlxl I I I I I I
\.

Y
LED

X=Unused

LJ-OO 170-TIO

Figure 1-32

Boot and Diagnostic Display Register Format (17777524· Write-Only)

Table 1-24 describes the display register bits.
Table 1-24 Display Register Bit Descriptions
Bits

Name

Function

<15:06>

Unused

Read as Os.

<05:00>

LED 5-0

These bits enable the boot and diagnostic programs to
light the LEDs located at the top of the CPU module.
Clearing any of these bits lights the corresponding LED.

1.8.4 Additional Status Register (17777526)
The additional status register controls board-intemal functional units such as memory
and interfaces. It is used by the boot and test firmware for testing and configuration
purposes. Basic processor functions are performed here. Figure 1-33 shows the register
format.
15

MA·0338·90.DG

Figure 1-33

Additional Status Register (17777526)

Table 1-25 describes the additional status register.
Table 1-25 Additional Status Register
Bits

Status

Function

<15:14>

Unused

Read as Os.

Architecture

1-47

Table 1-25 (Cont.) ·Addltlonal Status Register
Bits

Status

Function

<13:12>

RJW

Selects interfaces internally as follows:
Serial lines address/vector

SERSEL

SEREN

SLUs on 176500/300

SLUs on 176600/400

No serial lines selected.

<11:09>

Unused

Read as Os.

RJW

This bit is used for serial communication to the TOY.

<07:06>

Unused

Read as Os.

<05:04>

RJW

Selects internal memory as follows:
MEMSEL

MEMSEN

Function

o
o

Disabled

0-2 Mbyte memory

0-4 Mbyte memory

<03:02>

Unused

Read as Os.

RJW

Flag for PMI-Cycle (set by system).

Unused

Read as o.

1.9 Line Frequency Clock and Status Register (17777546)
The line clock provides the system with timing information at fixed intervals determined
by the LTC line (BEVENT) OJ," by one of the on-board KDJI1-E frequency signals. The
signals are programmed by boot and diagnostic controller status register bits <11:10>.
Typically, LTC cycles at the AC line frequency, producing intervals of 16.7 ms (60 Hz line)
or 20.0 ms (50 Hz line). The three on-board frequencies are 50 Hz, 60 Hz and 800 Hz.
The LKS, at address 17777546, allows line clock interrupts to be enabled and disabled
under program control. Alternatively, line clock interrupts can be unconditionally enabled
by setting CSR <13> (FRC LCIE). Program recognition of the clock status register can be
disabled by setting CSR <12> (LKS DIS).
The normal KDJ11-E configuration is FRC LCIE and LKS DIS both clear. These bits are
set up by the boot and diagnostic ROM programs from the KDJ11-E configuration data.
Figure 1-34 shows the clock status register format. Table 1-26 describes the clock status
register bits.
15

I
LCM

01 0

LCIE

Figure 1-34

Clock Status Register Format (17777546)

LJ-00249-TIO

1-48 Architecture

Table 1-26 Clock Status Register Bit Descriptions
Status

Function

Bits

Name

<15:08>

Unused

LCM

RJW

Line Clock Monitor. This bit is set by
the leading edge of the external BEVENT
line (or of one of the three on-board clock
frequencies), and by bus initialization.
LCM is cleared automatically on processor
interrupts acknowledge. It is also cleared
by writes to the LKS with bit 7 = o.

LCIE

RJW

Line Clock Interrupt Enable. This bit,
when set, causes the set condition of LCM
(LKS bit 7) to initiate a program interrupt
request at a priority level of 6. When LCIE
is clear, line clock interrupts are disabled.
LCIE is cleared by power-up and by bus
initialization. LCIE is held set INIT. LCIE
is held set when CSR bit 13 (FRC LCIE) is
set.

<05:00>

Unused

Read as Os.

1.9.1 Maintenance Register (17777750)
The DCJ11 microcode addresses the maintenance register at address 17777750 and
reads BPOK H, the power-up option code, and the halt/trap option hit. Other bits in the
maintenance register, not used by DCJ11 microcode, contain infonnation on the module
type and system parameters which is useful to operating system and diagnostic software.
Figure 1-35 shows the register format.
15

00000

Reserved

FPA
Available

Module Type
(Fixed)

UNIBUS
System

Power-Up
Option (Fixed)
HaltlTrap
Option

BPOK

H
MA..()331·90.DG

Figure 1-35

Maintenance Register Format (17777750)

The power-up option code is hard-wired for standard bootstrap operation (code 2). The
PSW is set to 340, and the processor begins program execution at address 173000. The
boot and diagnostic code, which starts at address 173000, configures the KDJ11-E. The
code runs standalone diagnostics before acting on the user-specified power-up option
stored as part of the EEPROM configuration data. Table 1-27 describes the maintenance
register bits.

Architecture

1-49

Table 1-27 Maintenance Register Bit Descriptions
Bits

Name

Status

Function

<15:11>

Unused

Reserved for future use. Read as Os.

Unused

Reserved for future use. Read as o.

UNffiUS
System

This bit reflects the status of the externally
applied UNIBUS adapter line. A 1
indicates that the system includes a
UNIBUS adapter.

FPA Available

Read as 1.

<07:04>

Module Type

Haltl'1.rap

<02:01>

Power-up
code

This 2-bit code is hard-wired as a 2. At
power-up, the processor sets the PC
to 173000 and sets the PSW to 340. It
then starts program execution at location
173000, which is the starting location for
the KDJll-E boot and diagnostic ROM
program. These programs test the KDJII-E
module and then implement the userselected power-up option specified in the
configuration data.

BPOKH

This bit is set (1) if the PMI bus signal
BPOK H is asserted, indicating that AC
power is acceptable.

This 4-bit code is hard-wired as a 5,
indicating a KDJII-E module.

R/W

This read/write bit determines the response
of a processor to a kernel mode halt
instruction. Setting the bit selects the
trap option, causing the CPU to trap to
location 4. Clearing the bit selects the halt
option, causing the CPU to halt and enter
ODT. This bit is cleared by the negation of
DCOK and is set by the boot and diagnostic
ROM code if the trap option is selected by
a bit in the configuration RAM. The trap
option is not intended for normal use and is
reserved for controller applications.

1.10 Time of Year Clock (TOY Clock)
The TOY clock is used to establish the time and date after a power down. It is not used
during normal operation. (Normal timekeeping for the KDJII-E is performed with the
Line Time clock.) The TOY clock uses 24-hour mode.
In the absence of power, battery backup is derived from an on -board lithium battery.
The TOY clock provides:
•

Hundredths of seconds

•

Seconds

•

Minutes

•

Hours

•

Day of week

1-50 Architecture

•

Month

• Year
Aruustments for months with less than 31 days and leap year are automatic. The time
and date can be read and set from dialog mode or by programming the time chip.

1.10.1 Programming Information
Communication between the KDJII-E module and the TOY clock is through bit 8 of the
additional status register (17777526).
Communication between the KDJII-E module and TOY clock is established by pattern
recognition of a unique serial bit stream of 64 bits (Bits 0 - 63).
Table 1-28 shows the recognition pattern.

Table 1-28 Recognition Pattern
Character
Recognition
Word

11 14 18

12 11 10

987

654

S2 1 0

1 0

101

100

010 1

085805

1 Bits 0-15

1 0

1 1

o 0/ 1

010

001 1

056248

2 Bits 16-81

1 0

101

100

o1 0 1

085805

8 Bits 32-47

1 0

1 1

001

010

001 1

056248

4 Bits 48-68

1.10.1.1 Clear the Comparison Register Pointer
Prior to sending the recognition pattern to the TOY clock, the comparison register pointer
must be cleared. To clear the pointer read the additional status register (17777526).
1.10.1.2 Establish the Pattern Recognition

The communication with the Time Chip is established by pattern recognition of a serial
bit stream of 64 bits (Table 1-28), which must be matched by executing 64 consecutive
write cycles containing the proper data.
All information must shift one bit at a time through bit 8 of the additional status register
(177526).
Writing starts with bit 0 of the first word and ends with bit 15 of the last word.
1.10.1.3 Updating Information In the TOY Clock

Information for the TOY clock can be read or updated after the recognition pattern
sequence has been established. When the first write cycle is executed, it is compared to
bit 1 of the 64-bit comparison register. If a match is found, the pointer increments to
the next location of the comparison register. If a match is not found, the pointer does
not advance and all subsequent write cycles are ignored. If a read cycle occurs at any
time during pattern recognition, the present sequence is aborted and the comparison
register pointer is reset. On the KDJII-E module the port to the Time Chip is bit 8 of
the additional status register (177526). Writing starts with bit 0 of the first word and
ends with bit 15 of the last word (Table 1-28). After recognition is established, the next
64 read or write cycles either extract or update data in the Time Chip.

Architecture

1-51

The Time Chip information is contained in eight registers of eight bits each, which are
sequentially accessed one bit at a time after the 64-bit pattern recognition sequence
has been completed. When updating the Time Chip registers, each must be handled in
groups of eight bits. Writing and reading individual bits within a register could produce
erroneous results. The read/write registers are defined in the following tables. Reading
and writing the registers is always accomplished by stepping through all eight registers,
starting with bit 0 of register 0 and ending with bit 7 of register 7.
Here is the format of the eight 8-bit registers.

654

321

0.1 Sec

0.01 Sec

Digit

Range 0-9

10 Sec

Sec

Digit

Range 0-5

Range 0-9

1-52 Architecture

765

Min

10 Min
Digit

Digit

Range 0-5

Range 0-9

10 Drs

Hours

Digit

Range 0-2

Range 0-9

000

Day

Digit

Range 0-0

Range 1-7

Note:
The KDJ11-E ROM Code assigns day 1 as Monday.

Architecture

1-53

10 DATE

DATE

Digit

Range 0-3

Range 0-9

NOTE

The last date of the month is automatically adjusted for months with less than
31 days, including leap years.
RegisterS
Byte Number 6
Range: 01-12
Function: Month

765

Month

000
Digit

Digit

Range 1-1

Range 0-9

321

10 Year

Year

Digit

Range 0-9

2
Configuration

2.1 Introduction
This chapter discusses the configuration requirements and other factors to consider when
configuring the KDJ11-E module and installing it into an LSI-11 system. The module
must be installed in a backplane that has the extended LSI-11 bus in the AlB rows and
the interconnecting bus in the em rows. A 22-bit LSI bus utilizes the full capability of
the module and the interconnecting bus is required because of the PMI feature of the
module.
The H9278-A backplane is designed to accommodate the module in LSI-11 based systems.
The H9277-AlB backplane is designed to accommodate the module and adapt it to a
UNIBUS based system. The UNIBUS Adapter module (UBA) provides the interface
requirements necessary to interface UNIBUS modules with the LSI-11 bus.
The user must consider the following items to determine the configuration requirements
for the module. If the module is installed in a prepackaged system, the user should be
aware of the system components and their intended use.
1.

Select the features controlled by the jumpers and switches located on the module.

2. Define the type of system and the mass storage devices being supported.
3. Select the desired configuration parameters available in the EEPROM.
4. Determine the bootstrap programs necessary to support the system.
5. Understand the system differences if an existing system is being upgraded.

2-1

2-2 Configuration

2.2 Module Configuration
The KDJII-E module has two jumpers and eight switches mounted in a switchpack on
the module as shown in Figure 2-1.
W1

TOY BATTERY

EEPROM

BOOT
EPROM

KOJ11-E

~----~-r=='-1-SLU
EPROM

)'11111111
0°°1°00
POWER
(YEL)

IoCO~
I(GRN) I

ON
OFF

~~~~~~~~
1

•

SWITCHPACK

DIAGNOSTIC
(RED)

Figure 2-1

•

KDJ11·E Jumper and DIP Switch Locations

MA·0325·tO.OG

Configuration

2-3

2.2.1 Jumpers For +5 V Power Source Selection
The KDJ11-E CPU module has two jumpers (W1 and W2), which will select the +5 V
power source. The +5 V power source for the KDJ11-E can be obtained from one of the
following two sources:
•

Module pins AA2, BA2, CA2, DA2 (W1 & W2 installed)

•

Connector J3 (W1 & W2 removed)

NOTE

Only one source may be selected.
The two jumpers, W1 and W2, connect the +5 V power source from backplane pins AA2,
BA2, CA2 and DA2 to the +5 V logic on the KDJI1-E CPU module.
The KDJ11-E CPU mo~ule uses either connector J3 or backplane pins AA2, BA2, CA2,
and DA2 as its source for +5 V power.
CAUTION

H connector J3 is used as the source for +5 V, jumpers WI and W2 must be
removed. Otherwise the two +5 V sources will be shorted together which can
result in damage to the power supply.

2.2.2 Switch pack
The switchpack contains eight individual switches that provide the following functions
(Figure 2-2):
•

Console baud rate - selected by switches 6, 7 and 8.

•

ROM mode - selected by switches 2, 3, and 4.

•

Force dialog mode - selected by switch 5.

•

Console SLU enable/disable - condition determined by switch 1.

The switches are wired to connector J2. The functions provided by these switches can
be controlled remotely by an external switchpack connected to J2. When using an
external switchpack, switches 1 through 8 on the KDJ11-E should be placed in the off
position. A switch placed in the ON position on the CPU will override the selection of
the corresponding switch located on the rear SLU I/O panel. Then the user can remotely
turn a switch on by grounding the corresponding pin on the connector cabling. The
switch connections for connector J2 are shown in Figure 2-3. The functions controlled by
the switches are described in the paragraphs that follow.

2-4 Configuration

EEPROM

oc::Jo

BOOT
EPROM

1001

SWitch 1: ON • Disable Console SLU
SWitch 1: OFF - Enable Console SLU

SWITCHES
8o0t
AUTO
1
2
3
4
5
8
AUTO

<2>
ON
ON
ON
ON
OFF
OFF
OFF
OFF

<3>
ON
ON
OFF
OFf
ON
ON
OFF
OFF

<4>
ON
OFF
ON
OFF
ON
OFF
ON
OFF

SWitch
Baudrate of
ConsoleSLU

ON
ON
ON
ON
OFF
OFF
OFF
OFF

ON
ON
OFF
OFF
ON
ON
OFF
OFF

ON
OFF
ON
OFF
ON
OFF
ON
OFF

38400 Baud
19200 Baud
9800 Baud
4800 Baud
2400 Baud
1200 Baud
800 Baud
300 Baud

W·OOt73-11O

Figure 2-2

KDJ11-E Switch Configuration

Configuration

2-5

J02
F03
+5V~--n

2
SW6
SW7

Bit 6
3

SW8
SW1

Bit 7
Bit 0

Bit 4
Bit 1

SW5
SW.2

Bit 5

Bit 2

SW3

LEOOa

+5V~---,----------~~"~4---------------~-<Y

LED 05

LED 04

LED 03

15
16

LED 02

LED 01

SW4

Blt3

Pins 21 Through 38
Not Shown

~
o

U-00174-TlO

Figure 2-3

Switch Connections for Connector J2

2-6 Configuration

2.2.2.1 Baud Rate Selection

The baud rate for the console SLU is selected by switches 6, 7 and 8. The baud rate
selections and the switch conditions are listed in Table 2-1.
Table 2-1

Baud Rate Selections

Switches
7
8

Baud Rate

38,400

Off

19,290

Off

9600

Off

4800

Off

2400

Off

1200

Off

600

Off

300

2.2.2.2 Force Dialog Mode

Force dialog mode allows the user to establish a dialog with the system via the console
terminal by using the dialog commands that are described in Chapter 4.
If the force dialog switch (85 on the switch pack) is on, the ROM code enters dialog mode
at power-up or restart regardless of the selections in the EEPROM.
With switch 5 in the off position, (force dialog disabled) the action at power-up or restart
is predetermined by the set-up in the ROM code.
2.2.2.3 ROM Mode

ROM Mode is a special automatic boot mode that is entered as a power-up/restart option
to boot specific devices when one or more of switches 2 through 4 on the KDJ11-E CPU
module are set to the ON position.
When switches 2 through 4 are set to one of the six combinations shown in Table 2-2
and force dialog mode is not selected, ROM mode is entered. The mode attempts to boot
only the one device selected by this command. If the boot is unsuccessful, the ROM code
prints out the normal error message and enters dialog mode.
Table 2-2
Switches

ROM Mode Switch Settings
Settings

Description

off off off

Normal Automatic Boot Mode.

off

Device 1 in list/change boot parameters.

off on

Device 2 in list/change boot parameters.

off off

Device 3 in list/change boot parameters.

off on

Device 4 in list/change boot parameters.

off on

off

Device 5 in list/change boot parameters.

off off on

Device 6 in list/change boot parameters.

Normal Auto Boot Mode

Configuration - 2-7

2.2.2.4 Console/SLU Enable - Disable

The console/SLU is enabled by setting switch 1 to the off position. If the switch is in the
ON position, the system consolelSLU is disabled.

2.3 EEPROM Configuration Parameters
The general configuration parameters are stored in the EEPROM and can be modified or
changed by the user to meet the necessary requirements.
The CPU contains EEPROMs which store the programs (ROM code) that
comprehensively test the CPU, UBA and memory at power-up. The ROM code:
•

Boots the user's software on various devices

•

Provides memory size display

•

Provides time and date of TOY clock

•

Provides boot device selection

Provides the ability to define parameters for SLUs

•

Provides self-test selection

•

Provides user boot area on EEPROM

•

Provides support for:
Hard copy terminals
Video display terminals

The CPU automatically starts the ROM code each time you power up the system or
restart it with the Restart/Run/Halt switch on the front panel. The action the ROM
code takes is determined by the parameters stored in the EEPROM.
The parameters in the EEPROM determine the tests to be run, the general mode entered
after testing is complete, and the final configuration of certain registers on the CPU and
UBA module (UNIBUS systems only) before the system software is started. Parameters
in the EEPROM can easily be changed through a program in the ROM code called
Setup Mode without removing the CPU module. The EEPROM can also store customer
bootstrap programs.
The ROM code runs tests selected by parameters in the EEPROM. After testing is
complete, parameters in the EEPROM determine what action is to be taken next by the
ROM code. Typically, the ROM code will automatically load and start a program from the
user's disk or tape. This is commonly referred to as booting a program or automatic boot
mode.
For a detailed description of EEPROM c<?nfiguration parameters, refer to Chapter 4.

2.4 System Installation
The KDJII-E module can be used in any system that incorporates a backplane with the
extended LSI-II bus in rows A and B, and the interconnecting bus in rows C and D.

2-8 Configuration

. 2.4.1 LSI-11 Based Systems
An LSI-II based system can be custom designed using the KDJ11-E module and

compatible LSI-II components.
NOTE

It is recommended that the ac and dc loading for the final configuration
be checked for conformance to the LSI·11 bus loading rules. It is also
recommended that you check for overloading on the +5 V and +12 V power
supplies.
When building a custom LSI-II system in a BA2S enclosure, the following rules apply:
1. Slot 1 is reserved for the KDJ11-E.
2. Slots 2 and S can accept one dual or one quad Q-bus option.
S. Slots 4 through 8 can accept one quad or two dual Q-bus options.

4. All open A and B rows in slots 2 through 8 and all open C and D rows in slots 4
through 8 must be filled with a grant card if any modules follow in the backplane.
5. The terminating resistors on the backplane should be removed when using an
extended backplane system.

2.4.2 Restricted LSI-11 Systems
There are many LSI-II options that are not compatible because they were designed
primarily for 16- and 18-bit systems or for a particular application. The LSI-II options
which are not compatible are backplanes, memories, or I/O devices that are not capable
of 22-bit addressing. They may generate or decode erroneous addresses if used in
systems that implement 22-bit addressing. Memory and memory addressing devices
that implement only 16- or 18-bit addressing may be used in a 22-bit backplane, but the
size of the system memory must be restricted to the address range of these devices (64
Kbytes for systems with a 16-bit device, 256 Kbytes for systems with an 18-bit device).
Consider the following rules when adding restricted LSI-II options to the system:
1. The option must not use pins BC1, BD1, BEl, or BF1 except as the required BDAL

18-21 connections. Some early LSI-II options were allowed to use these pins as test
points or for user provided interconnections.
2. If the option is a DMA device, it must support the full 22-bit addressing requirement.
S. If the option responds to non-I/O page addresses, it must also decode the BDAL 18-21

address lines as part of the address.
4. The power requirements for each option must be considered to avoid overloading the
power supply.
5. The switching and electrical parameters of the option must conform to the LSI-II
specification of DEC STD 160.
NOTE

DMA devices having 18 bits can potentially work in a 22·bit system by buffering
110 in the 18·bit address space.

Configuration

2-9

2.4.3 UNIBUS Based Systems
A UNIBUS based system can be custom designed by using the KDJ11-E CPU module,
the KTJ11-B UBA and compatible UNIBUS components. This type of system must be
installed in the H9277-A or H9277-B backplane.
The following requirements must be considered when adding a UNIBUS option to the
system:
1. The timing and electrical parameters of the option must conform to the UNIBUS
specification of DEC STD 158.
2. The ac and dc loading of the UNIBUS must be within the allowable specifications.
3. The power requirements must not exceed the ratings of the power supply and
hardware. The speed differences between UNIBUS processors, diagnostics, and
operating systems may cause problems.

2.5 Module Contact Finger Identification
The LSI-11 type modules, including the KDJ11-E, all use the same contact (pin)
identification system. The contacts used on a quad-height module are identified in
Figure 2--4. The LSI-11 bus signals are assigned to rows A and B, each with 18 contacts
on the component side and the solder side. The KDJ11-E bus signals are identified along
with the LSI-11 bus signals in Table 2-3 and the pins are identified as follows:
AV2

A =
V =
2 =

Row identifier side (Row A)
Pin identifier (Pin V)
1 = component side/2 = solder side

The positioning notch between the two rows of pins mates with a protrusion on the
connector block for correct module positioning. A complete description of the backplane
and bus operation is provided in Chapter 5.

2-10 Configuration

Row A

RowB

RowC

Row 0
Side'
Component Side

Solder Side
U·GD111i·lIII

Figure 2-4
Table 2-3

KDJ11·E Module Contacts
KDJ11·E Module and LSI·11 Bus Signals

Component side

Solder Side

LSI·II Bus

KDJII·E

LSI·II Bus

KDJII·E

AA1

BffiQ5L

AA2

+5V

AB1

BffiQ6L

AB2

12V

Not used

AC1

BDAL 16 L

AC2

GND

AD1

BDAL 17 L

AD2

+12 V

Not used

AE1

SSPARE 1

Not used

AE2

BDOUTL

AF1

SSPARE 2

SRUNLI

AF2

BRPLYL

AH1

SSPARE 3

Not used

AH2

BDINL

AJ1

GND

AJ2

BSYNCL

BSYNC L

AK1

MSPAREA

Not used

AK2

BWTBTL

ALI

MSPAREA

Not used

AL2

BffiQ4L

BIRQ4L

AM!

GND

AM2

BIAKI L

Not used

ANI

BDMRL

AN2

BIALO L

BIAKL

API

BHALTL

BHALT L

AP2

BBS7L

IThe SRUN L signal is primarily used to drive a run light indicator. It is used for BAll-N and later systems.
It indicates that the processor is executing instructions.

Configuration

Table 2-3 (Cont.)

KDJ11-E Module and LSI-11 Bus Signals

Component side

Solder Side

-2-11

LSI·II Bus

IIDJII·E

LSI·II Bus

KDJII·E

AR1

BREFL

Not used

AR2

BDMGI L·

Not used

AS1

+12V

Not used

AS2

BDMGO L

AT1

GND

AT2

BOOT L

BINIT L

AU1

PSPARE 1

Not used

AU2

BDALO L

AV1

+5V

AV2

BDAL 1 L

BA1

BDCOKH

BA2

+5 V

+5V

BB1

BPOKH

BB2

12V

Not used

BC1

SSPARE4

BDAL 18 L

BC2

GND

BD1

SSPARE 5

BDAL 19 L

BD2

+12V

Not used

BEl

SSPARE6

BDAL20 L

BE2

BDAL2 L

BF1

SSPARE 7

BDAL21 L

BF2

BDAL3 L

BH1

SSPARE 8

Not used

BH2

BDAL4 L

BJ1

GND

BJ2

BDAL5 L

BK1

MSPARE B

Not used

BK2

BDAL6 L

BL1

MSPAREB

Not used

BL2

BDAL7 L

BM1

GND

BM2

BDAL8 L

BN1

BSACK L

BSACKL

BN2

BDAL9 L

BP1

BIRQ7L

BP2

BDAL 10 L

BR1

BEVNTL

BR2

BDAL 11 L

BS1

PSPARE4

Not used

BS2

BDAL 12 L

BTl

GND

BT2

BDAL 13 L

BU1

PSPARE 2

Not used

BU2

BDAL 14 L

BV1

+5V

BV2

BDAL 15 L

The KDJII-E module also uses rows C and D in the backplane for the PMI feature. The
C and D rows provide an interconnection between modules placed in adjacent slots. The
signals assigned to the C and D rows are identical for the KDJII-E CPU module and the
KTJII-B UBA The module signals are identified in Table 2-4.
Also refer to Table 2-5 through Table 2-7 for reference information concerning the
KDJII-E connector pin assignments Jl through J3.

2-12 Configuration

. Table 2-4 Module PMI Signal Assignments
Component Side

Solder Side

KDJll·E

CAl

Not used

CA2

+5V

CBI

PSSELL

CB2

Not used

CCI

SRUNL

CC2

GND

CDI

PUBMEML

CD2

Not used

CEI

PBCYCL

CE2

Not used

CFI

PUBSYSL

CF2

Not used

CHI

PHBPARL

CH2

Not used

CJI

PSBFULL

CJ2

Not used

CKI

PLBPARL

CK2

Not used

eLl

Not used

CL2

Not used

CMl

PRDSTB

CM2

Not used

CNI

Not used

CN2

Not used

CPl

PBLKML

CP2

Not used

CRI

PBSYL

CR2

Not used

CSI

Not used

CS2

Not used

CTI

GND

CT2

Not used

CUI

Not used

CU2

Not used

CVl

PUBTMOL

CV2

Not used

DAI

Not used

DA2

+5V

DBI

PWTSTBL

DB2

Not used

DCl

PBYTL

DC2

GND

DDI

PMAPEL

DD2

Not used

DEI

Not used

DE2

Not used

DFI

Not used

DF2

Not used

DHI

Not used

DH2

Not used

DJl

Not used

002

Not used

DKI

Not used

DK2

Not used

DLI

Not used

DL2

Not used

DMI

Not used

DM2

Not used

DNI

CNSLLOCKL

DN2

Not used

DPI

Not used

DP2

Not used

DRI

Not used

DR2

Not used

DSI

Not used

DS2

Not used

DTI

GND

DT2

Not used

Configuration

Table 2-4 (Cont.) Module PMI Signal Assignments
Component Side

Solder Side

KDJll·E

DUI

Not used

DU2

Not used

DVI

Not used

DV2

Not used

Table 2-5 J1, Connector Pin Assignments
Pin

Signal

Used For

JOI pin

N/C

Serial Line Unit 5

JOI pin

GND

Serial Line Unit 5

JOI pin

Serial Line Unit 5

JOI pin

GND

Serial Line Unit 5

JOI pin

GND

Serial Line Unit 5

JOI pin

N/C

Serial Line Unit 5

JOI pin

RX-

Serial Line Unit 5

JOI pin

RX+

Serial Line Unit 5

JOI pin 9

GND

Serial Line Unit 5

JOI pin

+12VF2

Serial Line Unit 5

JOI pin

N/C

Serial Line Unit 6

JOI pin

GND

Serial Line Unit 6

JOI pin

Serial Line Unit 6

JOI pin

GND

Serial Line Unit 6

JOI pin

GND

Serial Line Unit 6

JOI pin

N/C

Serial Line Unit 6

JOI pin

RX-

Serial Line Unit 6

JOI pin

RX+

Serial Line Unit 6

JOI pin

GND

Serial Line Unit 6

JOI pin

+12VF2

Serial Line Unit 6

JOl pin

N/C

Serial Line Unit 7

JOI pin

GND

Serial Line Unit 7

JOI pin

Serial Line Unit 7

JOI pin

GND

Serial Line Unit 7

JOt pin

GND

Serial Line Unit 7

JOI pin

N/C

Serial Line Unit 7

JOI pin

RX-

Serial Line Unit 7

JOI pin

RX+

Serial Line Unit 7

JOI pin

GND

Serial Line Unit 7

2-13

2-14 Configuration

Table 2-5 (Cont.) J1, Connector Pin Assignments
Pin

Signal

Used For

J01 pin

+12VF2

Serial Line Unit 7

J01 pin

N/C

Serial Line Unit 8/Console

J01 pin

GND

Serial Line Unit 8/Console

J01 pin

33 (-'"

Serial Line Unit 8/Console

J01 pin

GND

Serial Line Unit 81Console

J01 pin

GND

Serial Line Unit 8/Console

J01 pin

N/C

Serial Line Unit 8/Console

J01 pin

37 ""-

RX-

Serial Line Unit 8/Console

J01 pin

38 -

RX+

Serial Line Unit 81Console

J01 pin

GND

Serial Line Unit 8/Console

J01 pin

+12VF2

Serial Line Unit 8/Console

Table 2-6 J2, Connector Pin Assignments
pin

Signal

Used For

J02 pin

+5V

+5 Volts for Console/SLU Panel

J02 pin

Switch 6

Remote Console/SLU Connection

J02 pin

Switch 7

Remote ConsolelSLU Connection

J02 pin

Switch 8

Remote Console/SLU Connection

J02 pin

Switch 1

Remote ConsolelSLU Connection

J02 pin

Switch 5

Remote Console/SLU Connection

J02 pin

Switch 2

Remote Console/SLU Connection

J02 pin

Switch 3

Remote Console/SLU Connection

J02 pin

GND

Remote Console/SLU Connection

J02 pin

GND

Remote Console/SLU Connection

J02 pin

Led 06

Remote ConsolelSLU Connection

J02 pin

Led 05

Remote Console/SLU Connection

J02 pin

Led 04

Remote Console/SLU Connection

J02 pin

GND

Remote Console/SLU Connection

J02 pin

Led 03

Remote Console/SLU Connection

J02 pin

Led 02

Remote Console/SLU Connection

J02 pin

Led 01

Remote Console/SLU Connection

J02 pin

GND

Remote Console/SLU Connection

J02 pin

Switch 4

Remote Console/SLU Connection

J02 pin

GND

Remote Console/SLU Connection

J02 pin

N/C

Serial Line Unit 1

Configuration

Table 2-6 (Cont.) J2, Connector Pin Assignments
pin

Signal

Used For

J02 pin

GND

Serial Line Unit 1

J02 pin

Serial Line Unit 1

J02 pin

Serial Line Unit 1

J02 pin

GND
GND

J02 pin

N/C

Serial Line Unit 1

J02 pin

RX-

Serial Line Unit 1

J02 pin

RX+

Serial Line Unit 1

J02 pin

GND

Serial Line Unit 1

J02 pin

+12VFl

Serial Line Unit 1

J02 pin

N/C

Serial Line Unit 2

J02 pin

GND

Serial Line Unit 2

J02 pin

Serial Line Unit 2

J02 pin

Serial Line Unit 2

J02 pin

GND
GND

J02 pin

N/C

Serial Line Unit 2

J02 pin

RX-

Serial Line Unit 2

J02 pin

RX+

Serial Line Unit 2

J02 pin

GND

Serial Line Unit 2

J02 pin

+12VFl

Serial Line Unit 2

J02 pin

N/C

Serial Line Unit 3

J02 pin

GND

Serial Line Unit 3

J02 pin

Serial Line Unit 3

J02 pin

Serial Line Unit 3

J02 pin

GND
GND

J02 pin

N/C

Serial Line Unit 3

J02 pin

RX-

Serial Line Unit 3

J02 pin

RX+

Serial Line Unit 3

J02 pin

GND

Serial Line Unit 3

J02 pin

+12VFl

Serial Line Unit 3

J02 pin

N/C

Serial Line Unit 4

J02 pin

GND

Serial Line Unit 3

J02 pin

Serial Line Unit 3

J02 pin

Serial Line Unit 3

J02 pin

GND
GND

J02 pin

N/C

Serial Line Unit 3

J02 pin

RX-

Serial Line Unit 3

Serial Line Unit 1

Serial Line Unit 2

Serial Line Unit 3

2-15

2-16 Configuration

Table 2-6 (Cont.) J2, Connector Pin Assignments
Signal

Used For

RX+

Serial Line Unit 3

J02 pin 59

GND

Serial Line Unit 3

J02 pin

+l2VFl

Serial Line Unit 3

J02 pin

Table 2-7 J3, Connector Pin Assignments
Signal

Used For

+5V

Power

J02 pin 2

+5V

Power

J03 pin 2

+5V

Power

J04 pin 2

+5V

Power

JOl pin

2.6 Module Installation Procedure
To install or replace the KDJ11-E module or any LSI-11 option used in the system, follow
these procedures.
1. Ensure that no power is applied to the backplane when removing or inserting the
module.
2. Verify that the configuration of the module jumpers is correct.
3. Insert the KDJ11-E module into the backplane with the component side facing up.
4. Ensure that either the module or the selected system components provide the powerup protocol.
5. Use a single switch to apply all power to the system.

Configuration

2-17

2.7 Specifications
Identification

M8981

Size

Quad

Dimensions

26.5 em x 22.8 em (10.5 in x 8.9 in)

Power Consumption

+5 V ±5% at 4.5 A (maximum)
+12 V ±5% at 0.6 A (maximum)

AC Bus Loads

1 unit load

DC Bus Loads

1 unit load

Environmental:
Storage

-40°C to +65°C (-40°F to 150°F), 10% to 90% relative humidity,
noncondensing

Operating

For ambient temperatures above +55°C, sufficient air flow must be
provided to limit the module temperature to less than +65°C. For inlet
temperatures below +55°C, air flow must be provided to limit temperature
rise across the module to +10°C.
Derate maximum temperature by 1°C (1.8°F) for each 305 m (1000 ft)
above 2440 m (8000 ft).

3
Console On-Line Debugging Technique (ODT)

3.1

Introduction

The console on-line debugging technique (console ODT), allows the KDJ11-E to respond
to commands and information entered via a console terminal connected to the module.
The console interface uses addresses 17777560 through 17777566 to communicate with
the DCJ11 microprocessor. The addresses of the console terminal are generated in the
microcode and cannot be changed. Communication between the microprocessor and the
user is a stream of ASCII characters interpreted as console commands. These commands
are a subset of the commands used in the ODT-11 software for microcomputers.
This feature (ODT) is called the microcode on-line debugging technique, or micro-ODT.
The KDJ11-E micro-ODT accepts 22-bit addresses, allowing it to access 4088 Kbytesof
memory, plus the 8 Kbyte 110 page. Micro-ODT provides a more sophisticated range of
debugging techniques, including access to memory locations by virtual address.

3.1.1 Terminal Interface
The KDJI1-E provides a console serial line interface unit (SLU) on the module. This
allows the console to communicate with the KDJ11-E. The console SLU uses four
registers designated as the RCSR, RBUF, XCSR and XBUF. These registers are described
in Chapter 1.
Console ODT uses bit 7 of the RCSR and the XCSR registers and the low bytes of th~
RBUF and XBUF registers. The other bits used by these registers are ignored with the
following exceptions:
•

The XMIT break bit 0 must be cleared in order for the console ODT to function.

•

The interrupt enable bits 6 of the XCSR and RCSR registers have no effect during
console 0 DT.

3.2 Console ODT Entry Conditions
The console ODT mode can be entered in the following ways:
•

During execution of a HALT instruction in kernel mode, provided the trap option is
not selected in the maintenance register (address 17777750, bit 3). The trap option is
reset by the negation of DCOK

•

During assertion of the BHALT signal on the bus. Note that the signal must be
asserted long enough to be seen at the end of a macroinstruction by the service state
in the processor. BHALT is asserted if the halt-on-break feature is enabled by setting
BCSR bit 9 to a 1, then the SLU console receives a break character.

3-1

3-2 Console On-Line Debugging Technique (ODT)

•

At power-up when the power-up option is selected or at power-up and restart if the
halt switch is depressed.

ODT causes the following conditions upon entry:
1.

Performs a DATI from RBUF (input data buffer at 17777562) and then ignores the
character present in the buffer. This operation prevents the ODT from interpreting
erroneous characters or user program characters as a command.

2. Prints a carriage return <CR> and a line feed <LF> the console terminal.
3. Prints the contents of the PC (program counter R7) in six digits.
4. Prints a <CR> and <LF>.
5. Prints the prompt character @.
6. Enters a wait loop for the console terminal input. The DONE flag (bit 7) in the RCSR
at 17777560 is constantly being tested for a 1 by a DATI by the processor. If bit 7 is
a 0, the processor keeps testing.

3.3 Console ODT Command Set
The console ODT commands are a subset of the commands used in the ODT-11 software
and the same command characters are used. ODT has 10 internal states; each state
recognizes certain characters as valid input and responds with a question mark (?) to all
others.
The parity bit (bit 7) on all input characters is ignored (that is, not stripped) by the
console ODT, and if the input character is echoed, the state of the parity bit is copied to
the output buffer (XBUF). Output characters internally generated by ODT (for example,
<CR» have the parity bit equal to o. All commands are echoed except for <LF>.
The following descriptions of the console ODT commands include examples of what is
displayed on the console terminal in response to the commands entered by the user.
NOTE

For the novice user, these paragraphs should be scanned first for familiarization
and then reread for detail. The word "location," used in the following
paragraphs, refers to a bus address, processor register, or PSW.
Table 3-1 lists the console ODT commands.
Table 3-1

Console OOT Commands

Command

Symbol

Function

Slash

Prints the contents of a specified location

Carriage return

<CR>

Closes an open location

Line feed

<LF>

Closes an open location and then opens the next
contiguous location

Internal register
designator

$ orR

Opens a specific processor register

PSW

Opens the PSW; must follow an S or R command

Starts execution of a program

Proceed

Resumes execution of a program

Binary dump

<CTRL><SHIFT>S

Manufacturing use only

Console On-Line Debugging Technique (COT) 3-3

NOTE
<CTRL> J serves 8S line feed <LF> on some terminals.

3.3.1 Slash (I) Command (ASCII 057)
The slash (/) command is used to open a bus address, processor register, or PSW and
is normally preceded by other characters that specify a location. In response to a slash
(/), ODT prints the contents of the location (six characters) and then a space (ASCII 40).
After the printing is complete, ODT waits for either new data for that location or a valid
close co~mand. The space character is issued so that the contents of the location and
possible new contents entered by the ,user are legible on the terminal.
Example:

@00001000/012525

Where:

@ = ODT prompt
character

00001000

octal location in the Q22-bus address
space desired by the user (leading Os are not
required)

= command to open and print contents of
location

012525

contents of octal location 1000

The slash (I) command can be used without a location specifier to verify the data just
entered into a previously opened location. The slash produces this result only if it is
entered immediately after a prompt character that follows a location previously closed
by a carriage return «CR». A slash issued immediately after the processor enters ODT
mode causes? <CR> <LF> to be printed because a location has not yet been opened.
Example:

@1000/012525 1234 <CR>
@/001234<SPACE>

Where:

first line

second line

= a I entered without a location specifier
opens the previous location to reveal the new
contents.

new data of 1234 entered into location
1000 and location closed with <CR>.

3.3.2 Carriage Return «CR» Command (ASCII 15)
The carriage return «CR» command is used to close an open location. If the contents of
a location are to be changed, the user must precede the carriage return «CR» with the
new data. If no change is desired, a carriage return «CR» closes the location without
altering its contents.

3-4 Console On-Line Debugging Technique (ODT)

Example:

@Rl/004321 <CR> <LF>
@

Processor register RI was opened and no change was desired, so the user issued a
carriage return «CR».
Example:

@Rl/004321 1234 <CR> <LF>
@

In this case, the user desired to change Rl. The new data, 1234, was entered before the
carriage return «CR». ODT deposited the new data into the open location.

3.3.3 Line Feed «LF» Command (ASCII 12)
The line feed «LF» command is used to close an open location and then open the next
contiguous location. Bus addresses and processor registers are incremented by two and
one, respectively. If the PSW is open when an line feed «LF» is issued, it is then closed,
<CR> <LF>@ is printed, and no new location is opened. If the open location contents is
to be changed, the new data must precede the line feed «LF». If no data is entered, the
location is closed without being altered.
NOTE

<CTRL> J serves as line feed «LF» on some terminals.
Example:

@R2I123456 <LF>
@RS/OM321

In this case, the user entered a line feed «LF» with no data preceding it. In response,
ODT closed R2, then opened R3. When a user has the last register, R7, open, and issues
a line feed «LF», ODT rolls over to the first register, RO. ODT opens location 0 if the
last location in the 110 page (17777776) is open and the user issues a line feed «LF».

3.3.4 Internal Register Designator ($) (ASCII 044) or (R) (ASCII 122)
The internal register designator ($ or R), when followed by a register number (0 to 7)
or PSW designator (S), opens the processor register specified. The dollar sign ($) is
recognized to be compatible with ODT-Il. The R character was introduced as a one-keyexit stroke representation of its function. Lower case r (ASCII 162) is treated the same
as an uppercase R.
Examples:

@$O/OOOI23
@R7/000123 <LF>
@RO/054321

If more than one character (digit or S) follows the R or dollar sign ($), ODT uses the last
character as the register designator. However, an exception is that if the last three digits
are either 077 or 477, ODT opens the PSW rather than R7.

3.3.5 Processor Status Word Designator (S) (ASCII 123)
This designator is for opening the PSW and must be used after the user has entered an
R or dollar sign ($) register designator. A lower case s (ASCII 163) is treated the same as
an uppercase S.

Console On-Line Debugging Technique (ODT) - 3-5

Example:

@RSll00377 0
@/OOOOIO

Note that the trace bit (bit 4) of the PSW cannot be modified by the user. This is to
prevent the PDP-II program debugging utilities (for example, ODT-ll) that use the T-bit
for single-stepping from being accidentally harmed by the user. If the user issues a line
feed «LF» while the PSW is open, the word is closed and ODT prints an at sign (@). No
new location is opened.

3.3.6 Go (G) Command (ASCII 107)
The go (G) command is used to start program execution at a location entered immediately
before the G. This function is equivalent to the Load Address and Start switch sequence
on other PDP-II consoles.
Example:

@200 G

The ODT sequence for a G, after echoing the command character, is as follows:
1. Print two nulls (ASCII 0) so the bus initialize that follows does not flush the G

character.
2. Load R7 (PC) with the entered data. If no data is entered, 0 is used. (In the
preceding example, R7 equals 200 and that is where program execution begins.)
3. The floating-point status register (FPS) and the PSW are cleared to o.
4. The LSI-II bus is initialized by the processor asserting BINIT L for 12.6 microseconds, negating BINIT L, and then waiting for 110 micro-seconds.
5. The service state is entered by the processor. Anything to be serviced is processed.
If the BHALT L bus signal is asserted, the processor reenters the console ODT state.
This feature is used to initialize a system without starting a program (R7 is altered).
If the user wants to single-step a program, the user issues a G and then successive P
commands, all with the BHALT L bus signal asserted.

3.3.7 Proceed (P) Command (ASCII 120)
The proceed (P) command is used to resume execution of a program and it corresponds
to the Continue switch on other PDP-II consoles. No machine state visible to the
programmer is altered using this command.
Example:

Program execution resumes at the place pointed to by R7. After the P is echoed, the ODT
state is left and the processor immediately enters the state to fetch the next instruction.
If a halt request is asserted, it is recognized at the end of the instruction (during the
service state) and the processor then reenters ODT. Upon entry, the contents of the PC
(R7) are printed. In this fashion, a user can single-step through a program and get a PC
trace displayed on the terminal.

3-6

Console On-Line Debugging Technique (ODT)

. 3.3.8 Binary Dump «CTRL> <SHIFT> S) Command (ASCII 23)
The binary dump «CTRL> <SHIFl'> S) command is used for test purposes by
manufacturing and is not a normal user command. The command is normally received
from another computer and not the system console. It is recommended that this
command not be issued from the terminal because the console ODT echoes back the
ASCII 23 code, and this may cause the keyboard to lock up, and prevent data from being
displayed on the screen. There is no reason to issue this command from a terminal
because it then dumps the binary data. The terminal is intended to receive ASCII
data. The binary dump command is intended to more efficiently display a portion of
the memory, as compared to the slash (I) and line feed «LF» commands.
The binary dump command can accidentally be entered on many terminals by typing
<CTRL> S, <CTRL> s, <CTRL> 3, or in many cases by pressing <NO SCROLL>, since
all these conditions normally generate the ASCII 23 code. If the user accidentally enters
this command, the user should reset the terminal and type an "a" at least three times to
ensure that console ODT· is ready to accept commands again. The command protocol is as
follows:
1. Mter a prompt character, ODT receives a binary dump «CTRL> <SHIFl'> S)
command and echoes it.

2. The host system at the other end of the serial line must then send two 8-bit bytes,
which ODT interprets as a starting address. These two bytes are not echoed. The
first byte specifies starting address <15:08>, and the second byte specifies starting
address <07:00>. Bus address bits <21:16> are always forced to 0; the dump
command is restricted to the first 32K words of address space. The starting address
may be even or odd.
3. After the second address byte is received, ODT outputs 10 bytes to the serial line,
starting at the address previously specified. When the output is finished, ODT prints
an at sign (@).

3.4 ODT Address Specification
The KDJ11-E micro-ODT accepts 22-bit addresses, allowing it to access 4088 Kbytes of
memory, plus the 8 Kbyte I/O page. All I/O page addresses must be entered by users
with the full 22 bits specified. For example, to open the RCSR of the SLU , the user must
enter 17777560, not 177560 or 777560.

3.4.1 Processor I/O Addresses
Certain processor and memory management registers have 110 addresses assigned to
them for programming purposes. If referenced in ODT, the PSW responds to its bus
address, 17777776. Processor registers RO through R7 do not respond (that is, timeout
occurs) to bus addresses 17777700 through 17777707 if referenced in ODT.
The MMRs and PARlPDR pairs can be accessed from ODT by entering their bus address.
Example:

@177775721000001

In this case, MMRO is opened to show the memory management enable bit set.
The FP11 accumulators cannot be accessed from ODT. Only FP11 instructions can access
these registers.

Console On-Une Debugging Technique (ODT) 3-7

3.4.2 Stack Pointer Selection
Accessing kernel, superVisor, and user stack pointer registers is accomplished in the
following way. Whenever R6 is referenced in ODT, it accesses the SP specified by the
PSW current mode bits (PSW <15:14». If a program operating in kemel mode (PSW
<15:14> equals 00) is halted and R6 is open, the KSP is accessed.
Similarly, if a program is operating in user mode (PSW <15:14> equals 11), the R6
command accesses the USP. If a different SP is desired, PSW <15:14> must be set by the
user to the appropriate value, and then the R6 command can be used. If an operating
program has been halted, the original value of PSW <15:14> must be restored in order to
continue 'execution.
Example:

PS = 140000
@R6/1234G6

USP has been opened.
@RSl140000 O<CR> <CR> <LF>

@R6/123456 <CR>
@RSlOOOOOO 140000 <CR> <LF>

In this case, the KSP was desired. The PSW was opened and PSW <15:14> was set to 00
(kernel mode). Then R6 was examined and closed. The original value of PSW <15:14>
was restored, and then the program was continued using the P command.

3.4.3 Entering Octal Digits
When the user is specifying an address, the console ODT uses the last eight digits if more
than eight digits have been entered. When the user is specifying data, the console ODT
uses the last six octal digits if more than six were entered. The user does not need to
enter leading Os for either address or data; the console ODT forces Os as the default. If
an odd address is entered, the console ODT responds to the error by printing a question
mark (?) followed by an at sign (@).

3.4.4 ODT Timeout
If the user specifies a nonexistent address or causes a parity error, ODT responds to the
bus timeout by printing a question mark (?) followed by an at sign (@).

3.4.5 General Registers
Whenever RO through R5 are referenced in the console ODT, they access the general
register set currently specified by PSW bit 11. If a program is operating in general
register set 0 (PSW bit 11 set to 0), the program is halted. A general register is opened
and register set 0 is accessed. Similarly, if a program is operating in register set 1,
references to RO through R5 access register set 1.

3-8 Console On-Line Debugging Technique (ODT)

If a specific register set is desired, PSW bit 11 must be set by the user to the appropriate
value, and then the RO through R5 commands can be used. If an operating program
has been halted, the original value of PSW hit 11 must be restored in order to continue
execution.
.
Example:

PSW = 000000
@R4I062526 <CR>

R4 in register set 0 has been opened.
@RS/OOOOOO 4000 <CR>
@R4I177777 <CR>

@RS/004000 0 <CR>

In this case, R4 in register set 1 was desired. The PSW was opened and PSW bit 11 was
set to 1 (selecting register set 1). Then R4 was examined and closed. The original value
of PSW bit 11 was restored and the program was continued by using the P command.

4
Boot ROMs and Diagnostics

4.1 Operation Overview
NOTE

All reference to KTJII-B or UBA through out this chapter shall refer only to
UNIBUS systems.
NOTE

All reference to UNIBUS systems shown in example printouts through out this
chapter are displayed for UNIBUS systems and are omitted for Q-bus systems.
The CPU contains EEPROMs which store the programs (ROM code) that
comprehensively test the CPU, UBA and memory at power-up. The ROM code also:
•

Boots the user's software on various devices

•

Provides memory size display

•

Provides time and date from TOY clock

•

Provides boot device selection

•

Provides the ability to define parameters for SLUs

•

Provides self-test selection

•

Provides user boot area on EEPROM

•

Provides support for:
-

Hard copy terminals

Video display terminals

The CPU automatically starts the ROM code each time the system is powered up or
restarted with the Restart switch on the 'front panel. The action the ROM code takes is
determined by the parameters stored in the EEPROM.
The parameters in the EEPROM determine the tests to be run, the general mode entered
after testing is complete, and the final configuration of certain registers on the CPU
and UBA module before the system software is started. Parameters in the EEPROM
can easily be changed through a program in the ROM code called Setup Mode without
removing the CPU or UBA modules. The EEPROM can also store customer bootstrap
programs.

4-1

4-2

Boot ROMs and Diagnostics

The ROM code runs tests selected by parameters in the EEPROM. After testing is
. complete, parameters in the EEPROM determine what action is to be taken next by
the ROM code. Typically, the ROM code will automatically load and start a program from
t~e user's disk or tape. This is commonly referred to as booting a program or automatic
boot mode.
After the software is started, the ROM code is not entered again until the system is
powered up or restarted. In some cases, after testing is complete, the ROM code enters
Dialog Mode which allows you to select the actions entered through keyboard commands
using the console terminal.
Dialog mode allows you to:
•

Boot a device

•

List the boot programs available

•

Run ROM resident tests

•

List a map of the 110 page locations

•

Enter setup mode to list or change all parameters in the EEPROM

•

Modify time and date in TOY clock

Section 4.2 describes hard copy terminal support.
Section 4.3 describes video terminal support.

4.2 Hard Copy Terminal Support
This section describes the hard copy ROM commands.
When dialog mode is entered, the ROM code displays the main menu at the console
terminal and waits for you to select a command.
Example 4-1 shows an example of the main menu.

•

KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Unibus Syste.
Memory
2048 Kwtt
EEprom
4 Kwtt
Time
15:44:37 30-May-90 Wed"

•

Commands are: [Boot, Diagnostic, Help, List, Map, Setup, Toy]
Type a command then press the RETURN key:

Example 4-1

'Main Menu

The ROM code heading contains:
•

Version number of the ROM code and date created

•

Indicates UNIBUS system

•

Memory size in Kilowords

•

EEPROM area for USERBOOT programs

•

Time and date from TOY Clock

Boot ROMs and Diagnostics 4-3

•

Command line for selecting one of the seven hard copy ROM commands:
Boot

Map

Diagnostic

Setup

Help

TOY

List

These commands are described in the following sections.

4.2.1 Boot Command
The boot command allows a device to be booted. The primary boot program normally
reads 256 words from the device into memory starting at location o. If the secondary
bootstrap "block 0" is loaded without errors, then the ROM code transfers control to
location 0 with the MMU off, RO equal to the unit number of the device booted and R1
equal to the base address of the device CSR. For some devices, R1 is the base address
plus an offset.
The format for the boot command is:
B XXN

Where:

B
XX

Is the boot command.

Is the unit number to be booted.

Is the two letter mnemonic representing the device to be booted. The device
name must be alpha ch~ters.

When the ROM code has a device name, it searches for the first boot program with the
same device name. The ROM code looks for matches from these sources in the following
sequence:
1. CPU EEPROM (user boot)

2. CPU EPROM
3. UBA module (UNIBUS system only)
4. M9312 module (UNIBUS system only)

There are two optional switches that can be used with the boot command:
Switch

Description

'Thlls the ROM code to search for the boot program in the UBA ROMs
first, then the M9312 (if present). This overrides the standard sequence
of searching first in the EEPROM, then the CPU EPROM.

Overrides the default address and allows you to enter a new address.

Table 4-1 provides examples of how the ROM code interprets user input.

4-4 Boot ROMs and Diagnostics

Table 4-1

ROM Code Interpretation of User Input

User Input

ROM Code Action

BDL1

Boots DLI.

BDU7

Boots DU unit 7.

Transfers control to an external boot module.

BfA 160100 DKO

Boots RK05 with a eSR address of 160100.

BDUO

Invalid format. No space allowed in the device name DU.

BDUO

Invalid format. There must be a space between the boot command and
the device name.

NOTE

For a complete list of all the boot programs, execute the list command from the
main menu.
4.2.1.1 Transferring Control to Non-Digital Boot Modules (UNIBUS System
Implementation)
The single-letter device name B implements a method of supporting non-Digital boot
devices on the UNIBUS.

B causes the ROM code to transfer control to the address contained in location 17773024
of a ROM on the UNIBUS (if any) as long as the value in location 17773024 is not odd.

When the CPU ROM passes control:
•

The CPU ROMs and the UBA ROMs are disabled.

•

RO contains a unit number.

•

R1 contains O.

The ROM code types out an invalid device message if:
•

The address in location 17773024 on the UNIBUS is odd.

•

The boot module does not respond to all addresses from 17773000 to 17773776.

Typically the single-letter device name B is used when you have a module which has a
switch pack that responds at address 17773024 similar to a M9312 module. Usually the
start address of the program desired is set in the switch pack on the module.
4.2.1.2 Transferring Control to Non-DlgHal Boot Modules (Q.bus System
Implementation)
The single-letter device name B implements a method of supporting non-Digital boot
devices on the Q-bus.

On Q-bus systems, the letter B causes ROM to disable the CPU ROM and check location
17773000 for the existence of a ROM on the Q-bus. If a ROM is present and location
17773000 of the ROM is not 0 (HALT instruction), ROM will pass control to address
17773000 with MMU oft' and MMR3 set to O.

Boot ROMs and Diagnostics - 4-5

4.2.1.3 Error Detection During the Boot Command

The ROM code boot programs attempt to detect errors during the boot process and take
the appropriate action. Table 4-2 lists the possible errors that the ROM code tries to
detect. Not all errors are applicable for all boot programs.
Table 4-2

Boot Command Errors

LED Code

Description

Drive error

Controller error

17
16
15

Boot device selection was invalid

Non-existent controller

No tape

No disk

Invalid boot block

Drive not ready

No bootable device found (while in Auto Boot Mode)

Invalid unit number selected
Non-existent drive

NOTE

After successful completion of the loading of a secondary bootstrap, the display
is set to 00. Before transferring control to the secondary boot, the ROM code
prints out Starting System. At this time, parameters saved in the ROMs are
loaded into the CPU registers.
The following is an example of a boot command:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Unibus System
Memory
2048 KW
EEprom
4 KW
Time
15:41:52 16-May-90 Wed
Commands are: [Boot, Diagnostic, Help, List, Map, Setup, Toy]
Type a command then press the RETURN key: B DLO
Trying
Starting System

Example 4-2

Boot Command

4.2.2 Diagnostic Command
The diagnostic command allows you to test the CPU, the on-board memory SLUs, and
the KTJII-B (UNIBUS system only). Tests can be run individually or as a group (Test
30, All Selected Tests).
To execute the Diagnostic Command:
1. At the command line on the Main Menu, type D.

2. Press Return.

4-6 Boot ROMs and Diagnostics

You are then prompted for the following information:
Prompt

Action

Test Number

Select a test from the list displayed on the terminal
'Thst 30) All Selected 'lests) runs all tests selected in Setup Mode
Command 3. See Section 4.2.6.3 for more information.
'Thst 32) Serial line Unit Loopback 'Thst requires that loopback connectors
be installed on all SLUs on the KDJll-E.

Repeat Counter

Type the number of desired iterations in decimal) or type 0 to run the
test(s) continuously.

Testing starts after you select the test number and number of iterations. The ROM code
displays the test number, description of the test, error count, and iteration number.
If continuous testing is selected, no information is printed except errors. This allows the
Diagnostic Command to run for extended periods of time without requiring additional
printer paper.
To· terminate testing, type CtrllC or CtrllP.

Boot ROMs and Diagnostics 4-7
In the following example, test 67 is selected to be run once.
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Unibus System
Memory
2048 KW
EEprom
4 KW
Time
15:44:37 30-May-90 Wed
Commands are: [Boot, Diagnostic, Help, List, Map, Setup, Toy]
Type a command then press the RETURN key: D
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Single diagnostic test repeat
67 CPU Test
66 MMU Test
65 Pre-Console Test
64 MSER Test
63 CCR r/w Test
62 HIT/MISS-Reg Test
61 LTC Speed Test
60 Add-Stat-Reg Test
57 CPU-Err-Reg Test
55 UBA reg. resp. Testtt
54 Address 0 Test
53 Pre-Memory (0-4KW) Test
52 FPA Register Test
51 FPA Function Test
50 Int Mem Address Test
47 Int Mem Data Test
46 PIRQ-Reg Test
45 LTC Int Test
44 Lines Config. Test
43 Serial Lines Test
40 Memory parity Test
37 UBA map reg Test"
36 UBA NPR Cycle Test"
32 Loopback SLU Test
31 Extended Memory Test
30 All Selected Tests
Type CTRL Z to exit
Test number

New - 67

Type 0 for endless loop; break loop with CTRL C
Repeat counter = 000001
67 CPU Test

No Errors found

Example 4-3

Diagnostic Command

•

New - 1

Selected tests intended for UNIBUS systems only

NOTE

If the repeat counter is set to 0, to run continuously, only errors will be printed.

4-8

Boot· ROMs and Diagnostics

4.2.3 Help Command
The help command prints out a brief description of all the commands. At the end of this
command, you are returned to the main menu.

To execute the help command:
1. At the command line on the main menu, type H.

2. Press Return.
The following is an example of the help command:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Unibus system
Memory
2048 KW
EEprom
4. KW
Time
15:44:37 30-May-90 Wed
Commands are: [Boot, Diagnostic, Help, List, Map, Setup, Toy]
Type a command then press the RETURN key: H
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Command

Description

Help
Boot
Diagnostic
List
Map
Setup
Toy

Type this message
Load and start a program from a device
Execute a self-test single or repetitive
List boot programs
Map memory and I/O page
Enter Setup mode
Set time and date

Commands are: [Boot, Diagnostic, Help, List, Map, Setup, Toy]
Type a command then press the RETURN key:

Example 4-4

Help Command

Boot ROMs and Diagnostics - 4-9

4.2.4 List Command
The list command prints out a list of all available boot programs found in the CPU
EPROM, the CPU EEPROM (user boot), ROM sockets on the .UNIBUS adapter (if
present), or an M9312 (if present).
To execute the list command:
1.

At the command line on the main menu, type L.

2. Press Return.
The following is an example of the List Command (for Q-bus system):
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Memory
EEPROM
Time

2048 KW
4 KW
15:44:37 30-May-90 Wed

Commands are: [Boot, Diagnostic, Help, List, Map, Setup, Toy]
Type a command then press the RETURN key: L
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990

oDevice • Unit

•

Name

Numbers Source Device Type

0
0
0- 1
0- 7
0- 1
0- 15
0- 15
0- 15
0-255
0- 3
0- 1
0- 3
0-255

TT
DD
DK
MS
NE

NF
NU
DU
DL
DX
DY
MU

USR
USR
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM

TU58
RK05
TK25, TS04/05/11, TU80
DECNET DLV11-E
DECNET DLV11-F
DECNET DUV11
MSCP (RAxx, RDxx, RX50 , RC25 , ...)
RL01/RL02
RX01
RX02
TMSCP (TK50, TU81,
)

...

Press RETURN key when ready to continue

Example 4-5

•

List Command (Q-bus System)

Device Name is a two-letter mnemonic. The device name must be alpha characters.
At input, ROM converts all lowercase letters to uppercase letters.

.. Unit Numbers range is the allowable range of unit numbers valid for a particular
boot program.
.. Source lists where the actual boot program is located:
Physical Location of Boot
Program

Source

CPU EPROM

ROM

ROM Sockets on the UNIBUS
adapter module

UBA (UNmUS system only)

4-10 Boot ROMs and Diagnostics

. Physical Location of Boot
Program

Source

M9312

M93 (UNIBUS system only)

User Boot Area

USR

e Device Type is a description of the device to be booted.
At the completion of the list command, you are returned to the main menu.

4.2.5 Map Command
The map command prints out all addresses in the 110. page that respond. The 110 page
starts at address 17760000.
In addition, all addresses that are on the CPU or on the UBA that respond, are briefly
described. There is no description for optional device addresses that respond. At
completion of the map command, you are returned to the main menu.
To execute the map command:
1. At the command line on the main menu, type M.
2. Press Return.
The following is an example of the Map Command:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Unibus System
Memory
2048 KW
EEprom
4 KW
Time
15:44:37 30-May-90 Wed
Commands are: [Boot, Diagnostic, Help, List, Map, Setup, Toy]
Type a command then press the RETURN key: M
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
I/O page Map
Starting
Ending
Address
address
17765000
17772100
17772200
17772300
17772516
17773000
17776500
17777200
17777520
17777546
17777560
17777572
17777600

17765776
17772276
17772376
17773776
17776566
17777376
17777526
17777566
17777576
17777676

CPU ROM or EEPROM
Memory CSR
Supervisor I and D PDR/PAR's
Kernel I and D PDR/PAR's
MMR3
CPU ROM
SLU's
UBA map REG',s
CSR, PCR, BCR/BDR ASR
Clock CSR
Console SLU
MMRO,1,2
User I and D PDR/PAR's

Press RETURN key when ready to continue

Example 4-6

Map Command

Boot ROMs and Diagnostics 4-11

4.2.6 Setup Command
The setup command has fourteen commands (Example 4-7). These commands allow you
to list, change, or list and change all parameters stored in the EEPROM. Setup also
allows you to create or edit USERBOOT programs stored in the EEPROM.
The EEPROM contains information needed by the ROM code to configure the KDJllE (CPU) and the KTJII-B (UBA) and to determine the boot device, diagnostic test
selections, and restart modes.
NOTE

Changes made under setup mode are ignored unless they are saved in EEPROM
using setup mode command 8.
To execute the setup command:
1. At the command line on the main menu, type S.

2. Press Return.
The following is an example of the setup command:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Unibus System
Memory
2048 KW
EEprom
4 KW
Time
15:44:37 30-May-90 Wed
Commands are: [Boot, Diagnostic~ Help, List, Map, Setup, Toy]
Type a command then press the RETURN key: S
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Setup Mode Commands
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Exit
Select configuration parameters
Select diagnostic configuration
Select serial line parameters
Select boot parameters
List available boot programs
Factory setting
Save the setup table in the EEPROM
Load EEPROM data into the setup table
Load EEPROM boot program into memory
Edit or create EEPROM boot program
Save a boot program in the EEPROM
Delete a saved EEPROM boot program
Enter ROM ODT

Commands are: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14]
Type a command then press the RETURN key:

Example 4-7

Setup Command

4-12

Boot ROMs and Diagnostics

4.2.6.1 Setup Mode Command 1 • exit

Setup mode command 1 exits setup mode and returns to the main menu. You can also
retum to the main menu by pressing CtrllC.

To execute the setup mode command 1:
1. At the command line on the setup menu, type 1.
2. Press Return.
The following is an example of setup mode command 1:
KDJ11-E Monitor Version 1.0630-Jul-1990
(C) Digital Equipment Corporation 1990
Unibus System
Memory
2048 KW
EEprom
4 KW
Time
15:44:37 16-May-90 Wed
Commands are: [Boot, Diagnostic, Help, List, Map, Setup, Toy]
Type a command then press the RETURN key:

Example 4-8

Setup Mode Command 1

4.2.6.2 Setup Mode Command 2 • Select Configuration Parameters

The setup mode command 2 prints out the current status of various parameters and
allows you to change them.
When setup mode command 2 is executed, the ROM code prints out the current status of
all parameters, repeats the first parameter,then waits for your input.
There are two methods you can use to position the program at the parameter you want to
change:
•

Press Return until you are positioned at the parameter to be changed.

•

To go directly to the parameter to be changed, enter the letter to the left of the
parameter.

To change a parameter, enter the new value and press Return. The ROM code proceeds
to the next parameter.
NOTE

Changes made under setup mode are ignored unless they are saved in the
EEPROM using setup mode command 8 (Section 4.2.8.9).
To execute setup mode command 2:
1. At the command line on the setup menu, type 2.
2. Press Return.
The following is an example of setup mode command 2:

Boot ROMs and Diagnostics 4-13

KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
A

Memory Intern

(0) =

2MB

(1)

4MB

= 1

Rom on 173000

(0) =

(1 ) ==

Yes

Rom on 165000

(0) =

(1 )

Yes

Power-up Mode

(0)
Dialog
(1) =
Odt
Trap24
(2)
(3) = Auto

Restart Mode

(0)
(1)
(2)
(3)

= Dialog
Odt
Trap24
Auto

Power-on Self-tests

(0) ==

(1)

Yes

Alternate Boot Block

(0)

(1)

Yes

LTC Register

(0)

(1)

Yes

Force Clock Interrupt

(0)

(1)

Yes

Clock Frequency

(0)
(1)
(2)
(3)

50Hz
60Hz
800Hz

Pis
2

Halt on Break

(O)

(1)

Yes

Trap on Halt

(O)

(1)

Yes

Ignore Battery

(0)

(1)

Yes

Lines on

(O)

(1)
(2)

DIS
176500
176600

= 1

Disable UBA ROMtt

(0)

(1)

Yes

Enable UBA 18-Bit Mode8

(0)

(1)

Yes

Type CTRL Z to exit or press Return key to proceed

Example 4-9

Setup Mode Command 2

o UNIBUS system only
A description of each parameter that can be changed using setup code command 2 follows:
A - Memory Intern

The KDJII-E CPU module contains the following on-board memory:
KDJII-EA

Contains 2 Mbyte of on-board memory.

KDJII-EB

Contains 4 Mbyte of on-board memory.

If the amount of memory selected does not match the memory on-board, the message
Mem mismatch prints. This parameter has no effect on the KDJII-EA
The KDJII-EB contains 4 Mbyte of on-board memory. For some applications it may be
desirable to disable the top 2 Mbyte of memory.

4-14 Boot ROMs and Diagnostics

Table 4-3 describes the variations of the memory intern parameter.
Table 4-3 Memory Intern Parameter Variations

settin,

Description

2Mbyte

4Mbyte

B • ROM on 173000
This parameter sets/resets bit 7 of the eSR at address 17777520.
The KDJ11-E ROM code responds to the addresses from 17773000 through 17773777.
This address range is automatically enabled at power up or after the restart switch is
enabled regardless of the setting of this parameter.
Table 4-4 describes the variations of the ROM on 173000 parameter.
Table 4-4 ROM on 173000 Parameter Variations

Value

Description

KDJ11-E ROM code disabled.

KDJ11-E responds to addresses 17773000 - 17773777. Factory settin,.

C - ROM on 165000
This parameter allows you to disable the ROM. It sets/resets bit 6 of the eSR at address
17777520.
Table 4-5 describes the variations of this parameter.
Table 4-5 ROM on 165000 Parameter Variations

Value

Description

The KDJ11-E does not respond to addresses 17765000 - 17765777. Factory
settin,.

Enables internal EEPROM or the boot EPROM to respond to addresses
17765000 - 17765777.

o . Power-up Mode and E • Restart Mode
There' are four mode choices for either the power-up mode or the restart mode:
•

Dialog mode

•

ODTmode

•

Trap 24 mode

•

Automatic boot mode

Boot ROMs and Diagnostics 4-15

When the ROM code is started, it checks a status bit to determine if the unit is powering
up or if the restart switch was activated. The ROM code then uses the appropriate mode
selected. You can define the action taken by the ROM code at power-up or restart to be
the same or different.
•

Dialog mode
In dialog mode, all selected tests are executed at power-up unless power-up self-tests
are disabled. Dialog mode allows you to:

•

Boot a device

List boot programs available

Run ROM resident tests

Print a map of all 110 page locations

Enter setup mode to list and change all parameters in the EEPROM.

Enter time and date for TOY clock.

ODT mode
At completion of a very limited set of tests, the ROM code executes a halt instruction
and passes control to Jll micro-ODT. This mode is used in debug environments.
The ROM code does not change any locations in memory before entering ODT mode
(Chapter 3).

•

Trap 24 Mode
At the completion of a limited set of tests, the ROM code loads the PSW with the
content~ of location 26 and then transfers control to the address in location 24. This
mode is used when power fail recovery is desired.

•

Automatic boot mode
In automatic boot mode, all selected tests are executed at power-up unless power-up
self-tests are disabled.
NOTE

If the force dialog switch (85 on the KDJll·E CPU 'module> is on, the ROM

code enters dialog Mode at power-up or restart regardless of the selections
in the EEPROM.
The ROM code enters an automatic boot routine that tries to boot a previously
selected device or devices. The list of devices can be from one to six devices long.
Each device is tried sequentially until a successful boot occurs or the end of the boot
table is reached.
ROM mode is a special automatic boot mode that is entered as a power-up/restart
option to boot specific devices when one or more of switches 2 through 4 on the
KDJII-E CPU module are set.
When switches 2 through 4 of the KDJII-E CPU module are set to one of the six
combinations shown in Table 4-6 and force dialog mode is not selected, ROM mode
is entered. The mode attempts to boot only the one device selected by this command.
If the boot is unsuccessful, the ROM code prints out the normal error message and
enters dialog mode.

4-16

Boot ROMs and Diagnostics

Table 4-6 ROM Mode Switch Settings

Switches

Settings

Description

off off off

Normal Automatic Boot Mode. (Does not enter ROM mode.)

on on off

Device 1 in list/change boot parameters.

on off on

Device 2 in list/change boot parameters.

on off off

Device 3 in list/change boot parameters.

off on on

Device 4 in list/change boot parameters.

off on off

Device 5 in list/change boot parameters.

off off on

Device 6 in list/change boot parameters.

NOTE

See Section 4.2.6.5 to add or delete devices from the boot device block.
F - Power-on Self-tests

Mer a power-up sequence, the diagnostic tests contained in the ROM code are executed.
Control is passed to the ROM code and a comprehensive set of diagnostic tests check the
KDJII-E and UNIBUS adapter. Upon completion of the on-board diagnostics, control is
passed to the previously selected power-up mode option.
NOTE

The force dialog switch (86) on the KDJII-E CPU module must be off.
Table 4-7 describes. the variations of the power-on self-tests parameter.
Table 4-7 Power-On Self-Tests Parameter Variations

Value

Description

No self-tests performed after a power-up.

Self-tests performed after a power-up. Factory setting.

NOTE

Power-on self-tests are not executed if:
•

If power-up mode is set to Trap 24.

•

If power-up mode is set to ODT.

•

If ROM code is entered by depressing the RESTART switch on the front
panel.
.

G - Alternate Boot Block

When you attempt to boot a device, the ROM code does not transfer control to the booted
device unless the device looks boatable.
Some poking around is done by the ROM code to ensure control is never passed to
unbootable media. For example, a blank pack may have been mounted in a disk drive by
mistake.

Boot ROMs and Diagnostics

4-17

The boot block on all bootable PDP-11 software distributed by Digital Equipment
Corporation has the following format:
•

Location 0 can range from 240 to 277. Normally this locatio~ contains a no operation
command (240).

•

Location 2 can range from 400 to 777. This is an unconditional branch instruction.

Table 4-8 describes the variations of the alternate boot block parameter.
Table 4-8

Alternate Boot Block Parameter Variations

Value

Description

Standard format bootblock. Factory setting. If this parameter is set to 0,
the ROM code looks for memory location 0 to be a value of 240 to 277 and for
memory, location 2 to be 400 to 777. If the data found is within those ranges,
the ROM code assumes that bootable media is present. At this point, the ROM
code passes control to the secondary boot program starting at memory address
o. If the data in memory location 0 or 2 is not within the range specified above,
the ROM code will type out an error message indicating that the media is not
bootable. (Boot block error)

Nonstandard format for the boot block. No poking around is done by the ROM
code to determine if the media is bootable. All the ROM code does is verify that
memory location 0 does not contain a halt instruction (000000).
When this parameter is set to 1 the ROM code looks for location 0 of the boot
block to be any nonzero number. If a nonzero number is found, control is passed
unconditionally to the secondary boot starting at memory location O.
This allows you to boot media that is in nonstandard format.

NOTE

The ROM code checks location 0 or 2 after the boot block (normally block 0) is
loaded into memory.
NOTE

USERBOOT programs are not checked to see if they are bootable.
H· LTC Register

Table 4-9 describes the variatio'ns of the LTC register parameter.
Table 4-9

LTC Register Parameter Variations

Value

Description

Disables the KDJII-E line time clock register to allow you to place a customer
time clock at this address.

Enables the KDJII-E line time clock register. Factory setting.

4-18

Boot ROMs and Diagnostics

I - Force Clock Interrupt

Table 4-10 describes the variations of the force clock interrupt parameter.
Table 4-10 Force Clock Interrupt Parameter Variations
Value

Description

Factory setting. The clock can request interrupts only if:

•

The clock CSR is enabled, parameter H LTC Register

•

The interrupt enable bit, CSR bit 6, is set at address 17777546.

•

The processor priority is 5 or less.

The clock unconditionally requests interrupts when the processor priority is 5 or
less.

NOTE
If the force clock interrupt is selected, always disable the clock eSB, because
the eSB has no control over the clock.

J - Clock Frequency
The clock frequency parameter determines the source of the clock to be used.
Table 4-11 describes the variations of this parameter.
Table 4-11

Clock Frequency Parameter Variations

Value

Source

Clock sourced from power supply, at backplane pin BRI. The power supply
drives this signal at 50 or 60 Hz. Factory settin••

Clock sourced internally at 50 Hz from KDJII-E.

Clock sourced internally at 60 Hz from KDJII-E.

Clock sourced internally at 800 Hz from KDJII-E.

K - Halt-on-Break

Table 4-12 describes the variations of the halt-on-break parameter.
Table 4-12 Halt-on-Break Parameter Variations
Value

Description

Console breaks are ignored from the Break key on terminal. Factory settin••

Enables the processor to halt if the console SLU detects a break condition from
the Break key on terminal.

Boot ROMs and Diagnostics 4-19

L - Trap on Halt

Table 4-13 describes the variations of the trap-on-halt parameter.
Table 4-13 Trap-on-Halt Parameter Variations
Value

Description

Factory setting. The processor enters Jll micro-ODT if a haIt instruction is
executed in kernel mode.

The processor traps to location 4 if a halt instruction is executed in kernel mode.

M- Ignore Battery

The ignore battery parameter is used only when the current power up or restart mode is
set to 24 (3).
Table 4-14 describes the variations of this parameter.
Table 4-14 Ignore Battery Parameter Variations
Value

Description

Factory setting. The battery OK signal (BOK) must be present to execute Trap
24. Battery OK indicates that the memory contents were not corrupted as a
result of a power failure. If BOK is not set, Trap 24 mode is not executed and
dialog mode is entered.

Trap 24 mode is executed regardless of the status of the battery OK bit. This
mode is used if you have custom battery back-up hardware. In this case, the
battery OK bit may not reflect the actual state of the memory on the KDJII-E.

N - Lines On

The lines on parameter allows you to select the starting address/vector of serial lines 1
through 7. The priority level is set to 4 and cannot be changed.
To select other parameters for SLUs 1 through 7 (such as baud rate, number of data bits,
stop bits or pality), use setup mode command 4 (Section 4.2.6.4).
Table 4-15 describes the variations of the lines on parameter.
NOTE

Mter selecting and saving the desired starting address/vector for this
parameter, the system must be powered down and then rebooted for the change
to occur.

4-20

Boot ROMs and Diagnostics

Table 4-15 Lines On Parameter Variations

Value

Description

Disables SLUs 1 through 7. SLUs do not respond to any address and cannot be accessed.

SLUs respond to the following addresses/vectors:

UNIBUS

Address

Vector

SLUNumber

176500
176510
176520
176530
176540
176550
176560
176670

300
310
320
330
340
350
360
370

1
2

3
4
5
6

8
Line 8 is included in the list only if the KDJII-E is
disabled. The KDJI1-E is disabled if switch 1, disable
console serial line unit, located on the KDJI1-E is set to
the on position.· In this case a console SLU, a DLll for
example, must be provided by the user.

SLUs respond to the following addresses/vectors:

UNIBUS

Address

Vector

SLUNumber

176600
176610
176620
176630
176640
176650
176660
176670

400
410
420
430
440
450
460
470

1
2

3
4

5
6
7

8
Line 8 is included in the list only if the console/SLU is
disabled. The consoleiSLU is disabled if switch 1, disable
console serial line unit, located on the KDJII-E, is set to
the on position. In this case a console SLU, a DLll for
example, must be provided by the user.

Boot ROMs and Diagnostics -4-21

o . Disable UBA ROM (UNIBUS Systems Only)
Table 4-16 describes the variations of the disable UBA ROM parameter.
Table 4-16

Disable UBA ROM Parameter Variations

Value

Description

Enables the UBA ROMs. Factory setting.

Disables the UBA ROMs. This allows other ROM boards on the UNmUS to
show up in the UBA ROM address range of 17773000 to 17773776.

NOTE
If the ROM code is booting directly from an M9312 type boot ROM located on

the M9312 module, the ROM code automatically disables the CPU ROM in the
17773nnn address range and the ROMs on the UBA module and uses the ROMs
on the M9312 module. This action is taken regardless of the status of the disable
UBA ROM parameter and the disable ROM parameter.

P • Enable UBA 18-BIt Mode (UNIBUS system Only)

Table 4-17 describes the variations of the enable UBA IS-bit mode parameter.
Table 4-17 Enable UBA 18·BII Mode Parameter Variations

Value

Description

Selects 22-bit addressing. Factory setting.

Selects 1S-bit addressing.

4.2.6.3 Setup Mode Command 3 • Select Diagnostic Configuration

This command allows you to select or deselect individual tests (Example 4-10). The
tests selected here are run when power-on self-tests (Section 4.2.6.2) and the diagnostic
command (Section 4.2.2) are enabled.
NOTE

To run the diagnostic command, changes to the self-test menu do not need to be

saved.
To execute setup mode command 3:
1. At the command line on the Setup Menu, type 3.

2. Press Return.
The following is an example of Setup Mode Command 3:

4-22

Boot ROMs and Diagnostics

KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
A Nr. 67 CPU Test

(0) =

(1) ..

Yes

- 1

Nr. 66 MMU Test

(0) -

(1) -

Yes

C Nr. 65 Pre-Console Test

(0) -

(1) -

Yes

- 1
- 1

D Nr. 64 MSER Test

(0) -

(1) -

Yes

- 1

Nr. 63 CCR r/w Test

(0) -

(1) -

Yes

Nr. 62 HIT/MISS-Reg Test

(0) -

(1) -

Yes

Nr. 61 LTC Speed Test

(0) -

(1) -

Yes

H Nr. 60 Add-Stat-Reg Test

(0) -

(1) -

Yes

Nr. 57 CPU-Err-Reg Test

(0) -

(1) -

Yes

Nr. 55 USA reg. resp. Teste

(0) -

(1) -

Yes

(0) -

(1) -

Yes

(0) -

(1) -

Yes

M Nr. 52 FPA Register Test

(0) -

(1) -

Yes

N Nr. 51 FPA Function Test

(0) -

(1) -

Yes

K Nr. 54 Address 0 Test
L

Nr. 53 Pre-Memory (0-4KW) Test

Nr. 50 Int Mem Address Test

(0) -

(1) -

Yes

Nr. 47 Int Mem Data Test

(0) -

(1) -

Yes

Q Nr. 46 PIRQ-Reg Test

(0) -

(1) -

Yes

R Nr. 45 LTC Int Test

(0) -

(1) -

Yes

Nr. 44 Lines Config. Test

(0) -

(1) -

Yes

Nr. 43 Serial Lines Test

(0) -

(1) -

Yes

U Nr. 40 Memory parity Test

(0) -

(1) -

Yes

V Nr. 37 USA map reg Test.

(0) -

(1) -

Yes

W Nr. 36 USA NPR Cycle Test

(0) -

(1) -

Yes

Nr. 32 Loopback SLU Test

(0) -

(1) -

Yes

- 0

Y Nr. 31 Extended Memory Test

(0) -

(1) -

Yes

Nr. 30 All Selected Tests

(0) -

(1) -

Yes

- 0

Type CTRL Z to exit or press Return key to proceed

Example 4-10

•

Setup Mode Command 3 • Select Diagnostic Configuration

UNIBUS system only

Boot ROMs and Diagnostics 4-23

4.2.6.4 Setup Mode Command 4 • SeleCt Serial Line Parameters

This command prints out the current status of selectable parameters for SLUs 1 through
7 and then allows you to change them if desired.
The following parameters can be modified for SLUs 1 through 7:
Parameter

Values

Baud rate

300,600, 1200,2400,4800,9600, 19,200, 38,400

Number of data bits

7 or 8

Number of stop bits

lor 2

Parity

Even, odd, or disabled

NOTE

The following parameters are fixed for the console/SLU:
Baud rate

Set by using switches 6, 7, 8 on the KDcJ11-E.

Number of data bits

Number of stop bits

Parity

None

To execute the setup mode command 4:
1. At the command line on the setup menu, type 4.
2. Press Return.

4-24 Boot ROMs and Diagnostics

The following is an example of Setup Mode Command 4:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
A

Line 1

Baudrate

300
600
1200
2400
4800
9600
(5) (6) - 19200
(7) - 38400
(0)
(1)
(2)
(3)
(4)

Line 1

Data bits

(0) -

(1) -

- 0

Line 1

Stop bits

(0) -

(1) -

- 1

Line 1

Parity

(0) - Even
(1) - Odd
(2)
Dis

- 2

300
600
1200
2400
4800
9600
(5) (6) - 19200
(7) - 38400

Line 7

Baudrate

(0)
(1)
(2)
(3)
(4)

Line 7

Data bits

(0) -

(1) -

Line 7

Stop bits

(0) -

(1) -

Line 7

Parity

(0) - Even
(1)
Odd
(2)
Dis

Type <CTRL> Z to exit or press Return key to proceed

Example 4-11

setup Mode Command 4

- 0
- 1

- 2

Boot ROMs and Diagnostics 4-25

3. If you do not want to change any parameters, enter CtrllZ to return to the setup
menu.
4. If you want to change parameters, there are two methods you can use to position the
program at the parameter you want to change:
a. Press Return until positioned at the parameter to be changed.
b. Type one of the following letters:
A

'1b change parameters for line 1

'1b change parameters for line 2

'1b change parameters for line '3

'1b change parameters for line 4

'1b change parameters for line 5

'1b change parameters for line 6

'1b change parameters for line 7

5. Press Return. The ROM code proceeds to the next parameter.
4.2.6.5 Setup Mode Command 5· Select Boot Parameters

This command allows you to list current boot parameters for the power-up/restart mode
of Autoboot and to modify the Autoboot table.
To execute the setup mode command 5:
1. At the command line on the setup menu, type 5.

2. Press Return.
The following is an example of setup mode command 5:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
List/change boot parameter
Boot 1 :
Boot 2:
Boot 3:
Boot 4 :
Boot 5:
Boot 6:

Switches 2,3,4 on on off
Switches 2,3,4 on off on
Switches 2,3,4 on off off
Switches 2,3,4 off on on
Switches 2,3,4 off on off
Switches 2,3,4 off off on

Device Unit Address
0 Default
0 Default
0 000000
0 Default

= OM ROM
= DL ROM
= TT USR
= DL UBA
= blank
= blank

Type CTRL Z to exit or press Return key to proceed

Example 4-12

Setup Mode Command 5 • Boot Parameters Menu

3. If you want to return to the setup menu, enter CtrllZ.
4. To proceed, press Return.
The following is an example:
Boot 1: Switches 2,3,4 on on off = OM ROM
0 Default
80evice name
ttBoot location
(0) = USR (1) = ROM (2) = UBA(UNIBUS system only)
(3) = M93(UNIBUS system only) = 1
tlunit number
= 0
.Address
Boot 2: Switches 2,3,4 on
Device name

off on

DL ROM

Default

4-26 Boot ROMs and Diagnostics

•

Device Name
The ROM code prompts you for a device name. The previous mnemonic is displayed.
You can change the device by typing a new two-letter mnemonic associated with the
device to be selected. Pressing Return leaves the parameter unchanged.
Table 4-18 lists the default boot programs in the CPU ROM. Your system may
contain boot programs that are not on this list.

Table 4-18 Default Boot Programs

Device
Name

Unit

Numbers

Source

Device Type

0-255

ROM

MSCP (RAn, RDxx, RX50, RC25, ... )

0-3

ROM

RL011RL02

0-1

ROM

RX01

0-3

ROM

RX02

0-1

ROM

TK.25, TS04l05/11, TU80 (Q-bus only)

0-1

ROM

TU10, TE10, TS03 (UNmUS only)

0-255

ROM

TMSCP (TK50, TU81, ..•)

0-15

ROM

DECNET DLV11-E (Q-bus only)

0-15

ROM

DECNET DLV11-F (Q-bus only)

0-15

ROM

DECNET DUV11 (Q-bus only)

XlI

ROM

ETHERNET (Q-bus only)

NOTE
To print a complete list of all avaUable bootstraps and associated

mnemonics, use the list commAnd.

•

Boot Location
The ROM code requires you to enter the location of the boot code. The default is the
the standard on-board ROM.
Where:
USR

User previously created a User Boot. Boot code is located in the User Boot
area.
Standard default area.
M9312-type ROMs located in the ROM sockets of the UNIBUS Adapter
Module.
M9312-type ROMs located in the ROM sockets of the optional M9312 module
on the UNIBUS.

1lJNIBUS system only

•

Unit Number
The ROM code prompts for the unit number. Type in the unit number of the device
.
to be booted.

Boot ROMs and Diagnostics 4-27

•

Address

To select the default address press Return.
Enter an address if the device CSR is set at a nonstandard or floating address.
The ROM code continues to prompt for all six boot entries shown in Example 4-12.
If you do not want to change any items in Example 4-12, press CtrllZ to return to the
setup command menu. You can also skip any entry by pressing Return for each entry you
want to skip.
The ROM code continues to prompt for all six entries in Example 4-12.
Autoboot Mode

Autoboot mode allows you to select the devices to be tried in the automatic boot sequence.
You can create a list that defines the devices and the order in which they are tried. One
entry is needed to define a device and its unit number. If the same device is used more
than once with different unit numbers, then one entry is needed for each unit number.
The ROM code attempts to boot the devices you have defined in Example 4-12, starting
with boot 1. If the autoboot is unsuccessful, an error message is printed and the ROM
code enters dialog mode.
ROM Mode

ROM Mode is entered when Autoboot is selected as a power-up/restart option and one or
more of switches 2 through 4 of the KDJ11-E CPU module are set.
When switches 2 through 4 of the KDJ11-E are set to one of the six combinations shown
in Table 4-19 and force dialog mode is not selected, the ROM code enters a special
autoboot mode called ROM mode. ROM mode attempts to boot only the one device
selected by this command. If the boot is unsuccessful, the ROM code prints out the
normal error message and enters dialog mode.
Table 4-19 ROM Mode
Switches

Settings

Description

off off off

Normal Automatic Boot Mode.

on off

Device 1 in list/change boot parameters.

2 3 4

off on

Device 2 in list/change boot parameters.

3 4

off off

Device 3 in list/change boot parameters.

3 4

off on on

Device 4 in list/change boot parameters.

off on

off

Device 5 in list/chapge boot parameters.
Device 6 in list/change boot-parameters.

3 4

2 3

2 3 4
2

3 4

off off on

3 4

on on

Normal Automatic Boot Mode

4.2.6.6 Setup Mode Command 6 • List Available Boot Programs (for UNIBUS System)

To execute the setup mode command 6:
1. At the command line on the setup menu, type 6.
2.

Press Return.

4-28

Boot ROMs and Diagnostics

The following is an example of setup mode command 6: (UNIBUS System)
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990

• •

USR
USR
ROM
ROM
ROM
ROM
ROM
ROM
USA

MSCP (RAxx, RDxx, RX50, RC25, ..• )
RL01/RL02
RXOl
RX02
TU10, TE10, TS03
TMSCP (TK50, TU81, ••• )
RL01/RL02

Device
Name

Unit
Numbers Source Device Type

o
o

TT
DU
DL

0-255
0- 3
0- 1
0- 3
0- 1
0-255
0- 3

DX
DY
MT

MU
DL

Press RETURN key when ready to continue

Example 4-13

•
•

Setup Mode Command 6 (UNIBUS System)

Device name is a two-letter mnemonic. The device name must be alpha characters.
At input, the ROM code converts all lowercase letters to uppercase letters.
Unit numbers is the allowable range of unit numbers that is valid for a particular
boot program. The range varies from 0 to 255, depending on the device. If the unit
numbers range information is blank, the ROM code assumes the range limit is 0 to
255.

•

Source lists where the actual boot program is located:

Physical Location of Boot ROM

Source

User boot area

CPU EPROM
ROM sockets on the UNmUS adapter

USR
ROM
UBA

M93121

M93

module1

1UNIBUS system only

•

Device Type is a description of the device to be booted. It is the name on the outside of
the device to be booted. For example, the description for a device name DL is RL02,
which is the name on the outside of the physical device.

The mnemonic for each ROM found on either the UBA or the M9312 is checked against
the list of mnemonics in the ROM code. If the mnemonic matches an item in this list, the
ROM code prints out a description of that device. If no match is found, the description is
left blank for that mnemonic.

Boot ROMs and Diagnostics 4-29

4.2.6.7 Setup Mode Command 6 - List Available Boot Programs (Q-bus System)

To execute the setup mode command 6:
1. At the command line on the setup menu, type 6.
2. Press Return.
The following is an example of setup mode command 6:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990

• • • •
Device
Name

Unit
Numbers Source Device Type

0
0
0- 1
0- 7
0- 1
0- 15
0- 15
0- 15
0-255
0- 3
0- 1
0- 3
0-255

TT
DO
OK
MS
NE
NF

NU
DU
DL
OX
DY
MU

USR
USR
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM

TU58
RK05
TK25, TS04/05/11, TU80
DECNET DLV11-E
DECNET DLV11-F
DECNET DUV11
MSCP (RAxx, RDxx, RX50, RC25,
RL01/RL02
RX01
RX02
)
TMSCP (TK50, TU81,

... )

...

Press RETURN key when ready to continue

Example 4-14

Setup Mode Command 6 (Q-bus System)

•

Device Name is a two-letter mnemonic. The device name must be alpha characters.
At input, ROM converts all lowercase letters to uppercase letters.

•

Unit Numbers is the allowable range of unit numbers that is valid for a particular
boot program. The range varies from 0 to 255, depending on the device. If the unit
numbers range information is blank, ROM assumes the range limit is 0 to 255.

•

Source lists where the actual boot program is located:

Physical Location of Boot ROM

Source

CPU EPROM

ROM

USERBOOT area

USR

•

Device 'IYpe is a description of the dev.ice to be booted. It is the name on the outside of
the device to be booted. For example, the description for a device name DL is RL02,
which is the name on the outside of the physical device.

4.2.6.8 Setup Mode Command 7· Factory Setting
This command initializes the current contents of the values in the setup menu table to
the default factory settings.

To execute the setup mode command 7:
1. At the command line on the setup menu, type 7.

2. Press Return.

4-30

Boot ROMs and Diagnostics

The following is an example of setup mode command 7:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Factory setting

Example 4-15

Setup Mode Command 7

3. Execute setup mode command 8, if you want to save the values in the setup table
into the EEPROM.
4.2.6.9 Setup' Mode Command 8 • Save the Setup Table In the EEPROM
NOTE

All changes made in setup mode will be lost if setup mode command 8 is
executed.
This command permanently saves the current parameters of the setup table in the
EEPROM.
To execute the setup mode command 8:
1. At the command line on the setup menu, type 8.
2. Press Retum.
The following is an example of setup mode command 8:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Saving setup table in the EEPROM, please wait

Example 4-16

Setup Mode Command 8

4.2.6.10 Setup Mode Command 9· Load EEPROM Data Into the Setup Table

This command restores the setup table in memory with the values stored in the EEPROM
during the last save. You can also restore the setup table after making temporary
changes.
To execute the setup mode command 9:

1. At the command line on the setup menu, type 9.

2. Press Retum.
The following is an example of setup mode command 9:

Boot ROMs and Diagnostics 4-31

KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Load EEPROM data into the setup table

Example 4-17

Setup Mode Command 9

4.2.6.11 Setup Mode Command 10· Load EEPROM Boot Program Into Memory

When this command is executed, the ROM code loads a previously created user boot
program. The ROM code asks for the device name of an EEPROM boot to be loaded in
memory.

To execute setup mode command 10:
1. At the command line on the setup menu, type 10.
2. Press Return.
3. Enter the two-letter mnemonic of the boot program to load:
Device name

New - TT

The following is an example of setup mode command 10:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Loading EEprom boot program
Type CTRL Z to exit or press Return key to proceed

Example 4-18

Setup Mode Command 10

NOTE

Setup mode command 10 only loads the program. To examine or edit the
userboot program, use setup mode command 11.
4.2.6.12 Setup Mode Command 11 • Edit or Create EEPROM Boot Program

This command is used to either create a new EEPROM boot program or to edit a program
previously loaded using setup mode command 10.
You can change or enter the:
•

Device name

•

Beginning address of the user boot program

•

Ending address of the user boot program

•

Start address

Highest unit number

•

Device description

When these changes are complete, the ROM code enters ROM ODT which is a RO~ code
version of Jll micro-ODT. When this command is first entered, it lists the available space
in the EEPROM for boots.
CAUTION

To ensure the new or edited user boot program is not lost, you must save it

using setup mode command 12.

4-32 Boot ROMs and Diagnostics

To execute setup mode command 11:
1. At the command line on the setup menu, type 11.

2. Press Return.
The following is an example of setup mode command 11:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
User boot editor
Type CTRL Z to exit or press Return key to proceed
11630 Bytes free in the EEPROM
Ooevice name

- TT

New -

tlBeginning address

- 01000

New -

ttLast byte address

- 01010

New -

estart address

- 01000

New -

tlHighest unit number

- 000

New -

tIoevice description

New - test

.nter ROM ODT
xxxxxx/ RETURN • or LF -

open word location xxxxxx if address even; byte if odd
close location
close location and open next
close location and open previous

ROM OOT >

Example 4-19

•
•

Setup Mode Command 11

Device name is a two-letter mnemonic for the boot program to be created.
Beginning address is the first location of the program in memory. The address range
is 1000 to 17544.
The ROM code prints out the old starting address and prompts you for a new starting
address. Type in a new address or press Retum to accept the old starting address.

•

Last byte address is the address of the last byte of code used in memory. If in doubt,
use the last address of data + 2 for this value. Do not use a much larger number to
avoid wasting EEPROM space.
The ROM code prints out the old ending address and prompts you for a new ending
address. Type in a new address or press ~tum to accept the old ending address.

•

Start address is the address that the ROM code passes control to. The start address
does not have to be the same as the beginning address but it must be even and a
value in the range defined by the beginning and ending addresses.

•

Highest unit number defines the allowable range of valid unit numbers for this device.
If the value is set to 3, the allowable range is 0 to 3. If a unit number is typed in at
boot time and it is not in range, an invalid unit number error occurs.

•

Device description is an optional but recommended description of the device name.
The name should be the name that is physically marked on the outside of the device
(for example, RA.82).

Boot ROMs and Diagnostics ·4-33

NOTE

After entering the device description, ROM ODT is automatically entered•
•

Enter ROM ODT - At this time, a new program can be entered or an existing
program can be edited/examined using ROM ODT. ROM OnT uses the commands
in Table 4-20.

CAUTION

After creating or editing a user boot program, use setup mode command 12 to
save it. If you do not save the program, it is lost.
To exit ROM ODT mode, press Ctr1lZ.
Table 4-20 ROM ODT Commands
Command

Symbol

Description

Slash

Prints contents of specified location or if no address is defined,
then the contents of the last location that was opened prints.
If the location opened is an odd number, then only the
contents of the byte prints. If location is even, the mode is
word. If location is odd, the mode is byte. Leading zero's are
assumed. Only bits 15 through zero of the address are used.

Return

<CR>

Closes an open location.

Line Feed

<LF>

Closes an open location and opens the next location. If the
mode is word, the address is incremented by 2. If the mode is
bytes, the address is incremented by 1.

Period

Alternate character for line feed. This command is useful
when the terminal is a VT2xx senes terminal. It is also
convenient to use with the keypad.

Minus

Alternate character for the up arrow on the cursor control
keypad. This command is useful when the terminal is a
VT2xx series terminal. It is also convenient to use with the
keypad.

Delete
CTRLZ

DELETE
AZ

Deletes the previously typed character.
Exits ROM ODT and returns to Setup mode.

4.2.6.13 Setup Mode Command 12· Save a Boot Program In the EEPROM

This command allows you to save the user boot program created or edited in setup mode
command 11 into the EEPROM. This is the only command that actually writes a boot
into the EEPROM.
When saving a boot program into memory, the device name of the program must not
match the name of an existing program in the EEPROM. If the program name already
exists, you must delete that program first or change the name of the program to be saved.
NOTE

The save procedure can take up to two minutes at the full length of 8 Kbytes.
To execute the setup mode command 12:
1. At the command line on the setup menu, type 12.
2. Press Return.

4-34 Boot ROMs and Diagnostics

Example 4-20 shows the setup mode command 12:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Saving boot program
Are you sure

YIN? Y

Saving Boot,wait-

Example 4-20

Setup Mode Command 12 • Save a Boot Program In the EEPROM

4.2.6.14 Setup Mode Command 13· Delete a Saved EEPROM Boot Program

This command allows you to delete an EEPROM boot. If this command is executed the
ROM code asks for the device name of the EEPROM boot to be deleted. After the device
name is input, the ROM code looks for the first boot program in the EEPROM. If it finds
the boot program, the ROM code deletes it.

To execute setup mode command 13:
1. At the command line on the setup menu, type 13.
2. Press Return.
The following is an example of setup mode command 13:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Del saved boot
Type CTRL Z to exit or press Return key to proceed
Device name

Example 4-21

== TT

New - JP

Setup Mode Command 13

3. Press Return. The following is displayed:
Are you sure?

Y!N?

4.2.6.15 Setup Mode Command 14· Enter ROM ODT

This command enters ROM ODT. The ROM code opens up the address defined by the
beginning address of the program. ROM ODT is not the same as J11 micro-ODT. The
only purpose of ROM ODT is to allow the user to create or edit a small bootstrap program
to be stored in the EEPROM.
In ROM ODT, the only allowable addresses that can be examined are the addresses of
memory from 0-28 KW (0-00157776). Any other addresses and any attempt to access the
110 page or any registers are not allowed.
Rom ODT uses the commands listed in Table 4-20.

To execute setup mode command 14:
1. At the command line on the setup menu, type 14.
2. Press Return.

Boot ROMs and Diagnostics 4-35
The following is an example of setup mode command 14:
KDJII-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 19~0
Enter ROM ODT
xxxxxx/ = open word location xxxxxx if address even; byte if odd
RETURN - close location
. or LF = close location and open next
= close location and open previous
ROM COT >

Example 4-22

Setup Mode Command 14

3. To exit ROM ODT mode and retum to the setup menu, press CtrllZ.

4.2.7 TOY Command
The TOY command allows you to change the time and date of the TOY clock. The time is
in 24-hour format.

To execute the TOY command:
1. Enter T.

2. Press Retum.
The following is an example of the TOY command:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
UNIBUS System
Memory
2048 KW
EEprom
4 KW
Time
15:44:37 30-May-90 Wed
Commands are: [Boot, Diagnostic, Help, List, Map, Setup, Toy]
Type a command then press the RETURN key: T
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Set time and date
Use following format:
For time: HH:MM:SS

For date: DD-MMM-YY

Time: 15:45:20
Input:
Date: 16-May-90
Input:
Commands are: [Boot, Diagnostic, Help, List, Map, Setup, Toy)
Type a command then press the RETURN key:

Example 4-23

TOY Command

4.3 Video Terminal suppon
This section describes how to operate the KDJI1-E ROM code using video terminal
support.

4-36 Boot ROMs and Diagnostics

4.3.1 Moving Through Menus
Table 4-21 describes how to move through or execute instructions in the menus.
Table 4-21

Moving Through Menus

Key

Function

Return

Executes a Do or an Edit.

Space bar

Selects the next value for a parameter.

Backspace

Selects the previous value for a parameter.

Tab

In setup menu, moves the cursor to the Save parameter. 1b save changes,
press Return.
In the self-test Menu, moves the cursor to the Monitor parameter. 1b
return to setup menu, press Return.
In the user boot menu, moves the cursor to the Exit parameter. 1b return
to the setup menu, press Return.
In the Map Menu, returns you to the setup menu.

Moves the cursor up to the next parameter.

Moves the cursor down to the next parameter.
Moves the cursor to t1:ae next parameter on the right.
Moves the cursor to the next parameter on the left.

Displays a list of all boot programs while in the boot device block.

CtrllC or CtrllP

Ends self-test and returns you to the setup menu.

4.3.2 Types of Function Fields • Video Terminal
Each menu contains function fields which allow you to perform a specific operation.
There are three types of function fields which are described in Table 4-22.
Table 4-22 Types of Function Fields
Field

Function

Edit

This is an executable function. When entered, Edit brings you to
a submenu such as Self-test, User Boot, or Map. You can make
modifications through the submenu. Not all fields can be edited.

This is an executable function. When selected, Do executes a specific
operation after pressing Return.

Addresses

Allows you to enter addresses directly in an octal format.

4.3.3 Setup Menu
The setup menu lists all the parameters in the EEPROM including boot parameters. Use
the setup menu to modify these parameters. Example 4-24 shows a setup menu.

Boot ROMs and Diagnostics 4-37

•

KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
UNIBUS System
Memory
2044 KW
EEprom
4 KW
16:17:45 18-May-90 Fri
&Time
8Nr Device Unit Address
1 DU ROM
0 Default Do
2 DL ROM
0 Default Do
3 TT USR
0 000000 Do
Do
4
Do
5
Do
6
Address/Vec
176500/300
176510/310
176520/320
176530/330
176540/340
176550/350
176560/360

ltLines
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7

Example 4-24

•

Baud
9600
9600
9600
9600
9600
9600
9600

Data
8
8
8
8
8
8
8

Stop
1
1
1
1
1
1
1

Par
Dis
Dis
Dis
Dis
Dis
Dis
Dis

Disable UBA ROM1
Enable UB~ 18-Bit Model
Memory Intern
Rom on 173000
Rom on 165000
Power-up Mode
Restart Mode
Power-on Self-tests
Select Self-tests
User Boot
Alternate Boot Block
LTC Register
Force Clock Interrupt
Clock Frequency
Halt on Break
Trap on Halt
Ignore Battery
Lines on

No
No
4MB
Yes
No
Dialog
Dialog
Yes
Edit
Edit
No
Yes
No
PIS
No
No
No
176500

Map
Factory Setting
Save

Do
Do
Do

Setup Menu

The time and date from the TOY clock is displayed here. To change the time and
date:
1. Move the cursor to the Time field and press Return.
2. Enter the new time and date in the following format:
NOTE

Use the right arrow key to move from the time field to the date field.
HH:MM:SS DD-MMM-YY
3. Press Return. The day is automatically entered.
•

The boot device block contains six lines which are divided into five sections:
Nr

Represents the sequence number.

Dev

A two letter mnemonic which represents a boot program and its location.

Unit

represents the unit number to be booted from. The space bar moves you to
the next unit number.

Address

Default is the standard address. If the device is set at a nonstandard
address, enter a new address.

Executes the boot for that line.

Each line of this boot device block provides you with 12 different boot devices with
corresponding units and the source where the actual boot program is located. As a
default setting, three boot devices have been set at the factory. To change the boot
device, move the cursor to the device and press the space bar to display a different
device.

UNffiUS system only

4-38

Boot ROMs and Diagnostics

A list of resident-supported boot devices can be displayed by positioning the cursor
anywhere within the boot device block and pressing the H key. An example follows:
KDJ11-E .Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Device
Name

Unit
Numbers Source Device Type

0
0-255
0- 3
0- 1
0- . 3
0- 1
0- 1
0-255
0
0- 3

DU
DL
OX
DY
MS
MT

MU
XH
DL

USR
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
USA

MSCP (RAxx, RDxx, RX50, RC25,
RL01/RL02
RX01
RX02
TK25, TS04/05/11, TU80
TU10, TE10, TS03
)
TMSCP (TK50, TU81,
ETHERNET
RL01/RL02

... )

...

Press RETURN key when ready to continue

Example 4-25

•

Resldent-Supponec:t Boot Devices

The SLU setup block individually sets the baud rate and character format for each
channel as follows:
Baud rate
range

300-38400

Data bits

Eight bitst
Seven Bits

Stop bits

Two stop bits
One stop bitt

Parity

Even
Odd
No parityt

t Default setting

NOTE

•

The status of the setup is only read during power-up or during an
initialization (INIT). Changes in the SLU settings are not implemented until
completion of a successful boot.
Configuration parameters allow you to enable or disable various functions or change
the values of others. Table 4-23 describes each parameter.

Table 4-23 Setup Menu Configuration Parameters
Parameter

Description

Values

Disable UBA
ROM I

Controls the ROMs
located on the UBA.

Yes disables the four ROM sockets.
No (factory setting) enables the UBA ROMs. It is
ignored when you try to boot the UBA or the M9312
boot ROMs.

I UNIBUS systems only

Boot ROMs and Diagnostics 4-39

Table 4-23 (Cont.) .Setup Menu Configuration Parameters

Parameter

Description

Values

Enable UBA
18-bit model

Selects 18- or 22-bit
addressing modes.
Its status is copied
into bit 5 of the UBA
KTJ11 Memory
Configuration
Register (KMCR).

Yes enables the memory to use 18-bit mode.
No (factory setting) enables the memory to use 22-bit
mode.

Memory
intern

Allows you to disable
the top 2 Mbyte
of memory on a
4 Mbyte board.
If the amount of
memory selected
does not match the
memory onboard,
the message Mem
mismatch displays.
This parameter has
no effect on a 2
Mbyte board.

2Mbyte
4Mbyte

ROM on
173000

Enables or disables
the CPU ROM code
at address 1730000.

Yes (factory setting) enables the internal boot
EPROM on the KDJ11-E. When enabled, the boot
EPROM occupies the address area from 173000
to 173777. This area consists of 512 words which
represents one page out of the EPROM. This parameter
sets/resets bit 7 of the CSR at address 17777520 just
before transferring control to another boot program.
The page number can be selected through the bits 15-9
of the PCR register.
No disables the internal boot EPROM on the KDJ11-E.

Rom on
165000

Enables or disables
the CPU ROM code
at address 165000.

Yes enables the internal EEPROM or boot EPROM
depending on bit 6 of the CSR register (17777520). The
ROM code uses an address area from 165000 to 165776
for EEPROM or for the boot EPROM, depending on bit
6 of the CSR register.
No (factory setting) disables the internal EEPROM.

Power-up
Mode

When the ROM
code is started, it.
checks a status bit
to determine if the
unit is powering
up or if the front
panel RESTART
switch was activated.
The ROM code then
uses the appropriate
mode selected. There
are four power-up
modes which you can
select.

Dialog Mode (factory setting) - Force dialog must
be disabled (85 oft). The setup menu is entered when
dialog mode is selected.

I UNIBUS systems only

4-40

Boot ROMs and Diagnostics

Table 4-23 (Coni.) Setup Menu Configuration Parameters
Parameter

Description

Values
Auto Mode - At the completion of the diagnostics the
ROM code enters an automatic boot routine that tries
to boot a previously selected device' or devices. The list
of devices can be from 1 to 6 devices long. Each device
is tried sequentially until a successful boot occurs or
the end of the boot table is reached.
ROM Mode is a special automatic boot mode that is
entered as a power-upl restart option to boot specific
devices when one or more of switches 2 through 4 on
the KDJII-E are set.
When switches 2 through 4 of the KDJII-E are set
to one of the six combinations shown in Table 4-6 and
force dialog mode is not selected, ROM mode is entered.
The mode attempts to boot only the one device selected
by this command. If the boot is unsuccessful, the ROM
code prints out the normal error message and enters
dialog mode. See Table 4-6 for switch settings.

ODT Mode - At completion of a very limited set of
tests, the ROM code executes a halt instruction and
passes control to Jll micro-ODT. This mode is used in
debug environments. The ROM code does not change
any locations in memory before entering ODT mode.

Trap 24 Mode - The ROM code loads the PSW with
the contents of locate 26 and then transfers control
to the address located in location 24. This mode is
used when power-fail recovery is desired. The ROM
code does not change any locations in memory before
executing mode 24.
Restart mode

See power-up mode.

Power-on
self-tests

Enables or disables
power-on self-tests.

Yes (factory setting) executes all self-tests during a
power-on. The force dialog switch (85) must be set to
off. During a restart the self-tests are not performed.
No disables all self-tests.

Select selftests

Allows you to enter
the self-tests menu.

Edit

User boot

Allows you to enter
the user boot menu.

Edit

Alternate

After the boot block
of a device is loaded
into memory, the
ROM code looks at
word locations 0 and
2 to see if the device
looks bootable. If the
data is not correct,
the ROM code types
out an error message
indicating that
the media is not
bootable.

Yes sets the ROM code to expect location 0 to be any
nonzero number.
No (factory setting) 1J8ts the ROM code to look for
location 0 to be a value of 240 to 277 and for location 2
to be 400 to 777.

boot block

Boot ROMs and Diagnostics 4-41

Table 4-23 (Cont.) Setup Menu Configuration Parameters
Parameter

Description

Values

LTC register

Enables/disables the
LTC register.

Yes (factory setting) enables the clock CSR at
address 17777546.
No disables the clock CSR at address 17777546.

Force clock
interrupt

Allows you to
unconditionally
force LTC interrupts.

Yes enables the clock to unconditionally request
interrupts when the processor priority is 5 or less.
No (factory setting) enables the clock to request
interrupts only if the clock CSR is enabled, clock CSR
bit 6 is 1, and the processor priority is 5 or less.

Clock
frequency

Determines the
source of the clock to
be used.

PS determines the source of the clock to be from
backplane pin BRI. The power supply normally drives
this signal at 50 or 60 Hz.
50 Hz (factory setting) determines the source of the
clock to be from the KDJII-E at 50 Hz.
60 Hz determines the source of the clock to be from the
KDJII-E at 60 Hz.
800 Hz determines the source of the clock to be from
the KDJII-E at 800 Hz.

Halt-on-break

Enables the
processor to halt
when the break key
is pressed.

Yes halts the processor when the break key is pressed.
No (factory setting) tells the processor to ignore any
break request.

Trap-on-halt

Enables or disables a
trap-on-halt.

Yes - If a halt instruction is executed in kernel mode,
the processor traps to location 4 if a halt.
No (factory setting) - If a halt instruction is executed
in kernel mode, the processor enters Jll micro-ODT.

Ignore
battery

This is used only
when the current
power-up or restart
mode is set to 24.

Yes executes mode 24 regardless of the status of the
battery.
No (factory setting) - The battery OK signal must be
present to execute mode 24. Battery OK indicates that
the memory contents were not corrupted as a result
of a power failure. If BOK is set, Trap 24 mode is not
executed and dialog mode is entered.

Lines on

Changes the
addresses of the
serial interfaces 1-7
from 176500-176560
to 176600-176660.

176500 (factory setting) selects address 176500,
vector 300.
176600 selects address 176600, vector 400.
DIS disables all SLUs.
NOTE
After selecting and saving the desired starting
address, the system must be powered down and
then rebooted for the change to occur.

Map

Maps all locations in
the 110 page.

Tn execute the map parameter, move the cursor to Do
and press Return. Upon execution, the map menu is
displayed (Example 4--28). After the valid 110 page
addresses are displayed, the setup menu is displayed.

Factory
setting

Resets all
parameters to their
factory settings.

Move the cursor to Do and press Return to execute the
factory setting parameter.

Save

Saves all
modifications made
to the setup menu.

Press the Thb key to move the cursor to Do. Press
Return to execute Save. You are prompted "Are you
sure? YIN'. Enter Y to save the modifications. Enter
N if you do not want to save the modifications.

4-42 Boot ROMs and Diagnostics

NOTE
If you want to save all function modifications, you must execute Save before leaving the

setup menu.

4.3.4 Self-Test Menu
When you execute Select Self-tests on the setup menu, the self-test menu is displayed
(Example 4-26). This menu is used to determine which tests are executed on power-up
and also allows individual tests to be selected and executed. The factory settings are
shown in the following example:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
67 CPU Test
66 MMU Test
65 Pre-Console Test
64 MSER Test
63 CCR r/w Test
62 HIT/MISS-Reg Test
61 LTC Speed Test
60 Add-Stat-Reg Test
57 CPU-Err-Reg Test
55 UBA Reg. Resp. Test"
54 Address 0 Test
53 Pre-Memory (0-4KW) Test
52 FPA Register Test
51 FPA Function Test
50 Int Mem Address Test
47 Int Mem Data Test
46 PIRQ-Reg Test
45 LTC Int Test
Monitor

•

44 Lines Config. Test
43 Serial Lines Test
40 Memory parity Test
37 UBA Map Reg Teste
36 UBA NPR Cycles Test"

Yes
Yes
Yes
Yes
Yes

32 Loopback SLU Test
31 Extended Memory Test

No
No

30 All Selected Tests

Test 00

Example 4-26

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

Repeat 00000

Self-Test Menu

UNIBUS system only

NOTE

Test 30, All Selected Tests, runs all tests selected (parameter. Yes) as a group.
Test 32, Loopback SLU Test, requires loopback connectors installed on all SLUs
on the KDJll·E.
4.3.4.1 Selecting or Deselecting Teats Executed Upon Power-Up

To select or deselect tests that are executed upon power-up:
1. Move the cursor to the test to be changed.
2. Press Retum to select Yes or No.
3. Press Tab to select the Monitor field.
4. Press Retum to retum to the setup menu.
5. Press Tab to select the Save field.
6. Press Retum to save the self-test parameters.

Boot ROMs and Diagnostics 4-43

4.3.4.2 Selecting and Executing an Individual Test

To select and execute an individual test:
1. Move the cursor to the Test field.
2. Type in the test number of the test to be run.
3. Move the cursor to the Repeat field.
4. Type in the number of iterations to run the test or enter 0 to run the tests
continuously.
5. Move the cursor to Do.
6. Press Retum to execute testing.
NOTE
CtrVC terminates testing.
4.3.4.3 Selecting and Executing a Group of Tests (Test 30)

To select and execute a group of tests using Test 30:
1. Move the cursor to each test to be changed.
2. Press Retum to select Yes or No.
3. Move the cursor to the Test field.
4. Enter 30 to select Test 30, All Selected Tests.
5. Move the cursor to the Repeat field.
6. Type in the number of iterations to run the tests or enter 0 to run the tests
continuously.
7. Move the cursor to Do.
B. Press Retum to execute testing.

NOTE
CtrVC terminates testing.

4.3.5 User Boot Menu
Example 4-27 shows a sample user boot menu. The addressing scheme shown is for
clarity only. Normally the boot routine resides here.

4-44 Boot ROMs and Diagnostics

KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
tIoevice name
tIoev Description
tlHighest Unit
Addrs.
001000
001020
001040
001060
001100
001120
001140
001160
001200
001220
001240
001260
001300
001320
001340
001360

000000
012737
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000

Example 4-27

DK
RK05
7

000002
000005
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000

tleeginning addr
ttLast byte addr
4istart addr
000004
177404
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000

000006
105737
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000

1000
1016
1000

000010
177404
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000

ttExit
Do
ttsave boot
Do
ttLoad saved boot Do
ttnel saved boot Do
000012
100375
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000

000014
000774
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000

000016.
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000

User Boot Menu

•

Device name is a two-letter mnemonic name for the boot program.

•

Beginning addr refers to the the first address of the boot routine. The address range
is 1000-17544. The ROM code prints out the old beginning address and prompts you
for the new beginning address. Type in a new address or press Return to accept the
old beginning address.

•

Exit returns you to the Setup Menu.

•

Save boot saves the boot program in the EEPROM. This function can take up to two
minutes for the full length of 8 Kbytes.

•

Dev Description is an optional but recommended description of the device name. The
name is usually the name that is physically marked on the outside of the device (for
example, RA82).

•

Last byte addr is the address of the last byte of code used in memory.

•

Load saved boot reloads previously saved boot program. This allows additional
changes to be made to the boot routine.

•

Highest Unit defines the allowable range· of valid unit numbers for this device. If the
value is set to 3, the allowable range is 0 to 3. If a unit number is typed in at boot
time and it is not in range, an invalid unit number error occurs.

•

Start addr is the address that the ROM code passes control to.

•

Del saved boot deletes the boot program from the EEPROM.
NOTE

The beginning address and last byte address refer to physical addresses in
memory for the program. Permitted values are between 1000 and 1'7544.
Pressing Return closes a location. To select a different address, use the cursor control
arrows.

Boot ROMs and Diagnostics 4-45

4.3.6 Map Menu
The map menu displays all addresses in the I/O page that respond. The 110 page is from
addresses 17760000 through 17777776. In addition, all addresses on the CPU or the
UBA that respond, are described. There is no description for optional device addresses
that respond.
The setup menu is displayed at the completion of the Map function. The ROM code waits
for you to press Return rather than scrolling data forward on video screen terminals. The
ROM code always assumes the terminal can display at least 24 lines of 80-column data.
A sample map menu is shown in Example 4-28.
KDJ11-E Monitor Version 1.06 30~Jul-1990
(C) Digital Equipment Corporation 1990
I/O page Map
Starting
Ending
Address
address
17765000
17772100
17772200
17772300
17772516
17773000
17776500
17777200
17777520
17777546
17777560
17777572
17777600

17765776
17772276
17772376
17773776
17776566
17777376
17777526
17777566
17777576
17777676

CPU ROM or EEPROM
Memory CSR
Supervisor I and D PDR/PAR's
Kernel I and D PDR/PAR's
MMR3
CPU ROM
SLU's
UBA map REG's
CSR, PCR, BCR/BDR ASR
Clock CSR
Console SLU
MMRO,1,2
User I and D PDR/PAR's

Press RETURN key when ready to continue
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
I/O page Map
Starting
Ending
Address
address
17777730
17777744
17777766
17777772
17777776

17777736
17777752

DCSR, DDR, KMCR
MSER, CCR, MREG, Hit/Miss
CPU Error
PIRQ
PSW

Press RETURN key when ready to continue

Example 4-28

Map Menu

4.4 Diagnostic Programs
The KDJ11-E supports two types of diagnostic programs. Table 4-24 describes these
programs.

4-46

Boot ROMs and Diagnostics

. Table 4-24 DlagnostlcPrograms
Diagnostic Program

Function

OECXll

DECXll is a system level exerciser. DECXll tests all parts of the
KDJII-E CPU module. The following DECXll modules should be
configured for a basic system:

Read-only memory (ROM)
resident diagnostics

MONE

Monitor E supports the memory management
unit and mapping in UNmUS systems.

MONQ

Monitor Q supports the memory management
unit in Q-bus systems.

KWA

Line time clock.

CPA

KDJII-E instruction set.

CPB

KDJII-E extended instruction set.

FPB

Floating point unit.

DLA

Serial line units.

CPU ROM resident startup diagnostics test various functions
specific to the CPU and UBA modules.

A comprehensive set of diagnostics can be executed during a system power-up by selecting
the Power-On Self-Test on the setup menu. A failure during diagnostic execution halts
the testing and displays one of the following:
•

If tests 30-67 fail, an error code and an error message on the console terminal (if
connected).

•

A test number in the KDJ11-E CPU module diagnostic LEDs.

4.4.1 KDJ11-E Self-Test
The KDJ11-E self-test allows you to comprehensively test:
•
•

CPU
Memory management

•

On-board memory

•

Serial line units

•

Console/SLU bulkhead (if equipped)

•

UNIBUS signals

•

KTJII-B

The self-test menu allows you to select and execute tests individually or as a group using
either video terminal mode or hard copy terminal mode.
•

To select and execute self-tests using the video terminal mode, proceed to
Section 4.4.1.1.

•

To select and execute self-tests using the hard copy terminal mode, proceed to
Section 4.4.1.2.

Boot ROMs and Diagnostics 4-47

4.4.1.1 Video Terminal Mode
NOTE

Test 30, All Selected Tests, runs all tests selected (parameter. Yes) as a group.
Test 32, Loopback SLU Test, requires loopback connectors installed on all SLUs
on the console/SLU panel (if equipped).
Selecting or Deselecting Tests Executed Upon Power-Up
To. select or deselect tests that are executed upon power-up:

1. Move the cursor to the test to be changed.
2. Press Return to select Yes or No.

a. Press Tab to select the Monitor field.
4. Press Return to return to the setup menu.
5. Press Tab to select the Save field.
6. Press Return to save the self-test parameters.
Selecting and Executing Individual Tests
To select and execute an individual test:

1. Move the cursor to the Test field.
2. Type in the test number of the test to be run.

a. Move the cursor to the Repeat field.
4. Type in the number of iterations to run the test or enter 0 to run the tests
continuously.
5. Move the cursor to Do.
6. Press Return to execute testing.
NOTE

Ctr1JC terminates testing. To return to the setup menu, move the cursor to the
Monitor field and press Return.
Selecting and Executing a Group of Tests

To select and execute a group of tests using test ao:
1. Move the cursor to each test to be changed.

2. Press Return to select Yes or No.

a. Move the cursor to the Test field.
4. Enter ao to select test ao, All Selected Tests.
5. Move the cursor to the Repeat field.
6. Type in the number of iterations to run the tests or enter 0 to run the tests
continuously.
7. Move the cursor to Do.
8. Press Return to execute testing.
NOTE

CtrllC terminates testing. To return to the setup menu, move the cursor to the
Monitor field and press Return.

4-48

Boot ROMs and Diagnostics

An example of the self-test menu follows:
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
67 CPU Test
66 MMU Test
65 Pre-Console Test
64 MSER Test
63 CCR r/w Test
62 HIT/MISS-Reg Test
61 LTC Speed Test
60 Add-Stat-Reg Test
57 CPU-Err-Reg Test
55 UBA reg. resp. Test"
54 Address 0 Test
53 Pre-Memory (0-4KW) Test
52 FPA Register Test
51 FPA Function Test
50 Int Mem Address Test
47 Int Mem Data Test
46 PIRQ-Reg Test
45 LTC Int Test
Monitor

Example 4-29

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Test 00

44 Lines CQnfig. Test
43 Serial Lines Test
40 Memory parity Test
37 USA map reg Teste
36 USA NPR cycles Test"

Yes
Yes
Yes
Yes
Yes

32 Loopback SLU Test
31 Extended Memory Test

No
No

30 All Selected Tests

Repeat 00000

Self-Test Menu

o UNIBUS systems only
4.4.1.2 Hard Copy Terminal Mode
Selecting and Executing Individual Tests

To select and execute an individual test:
1.

Enter D on the main menu,.

2. Press Return to execute the diagnostic command. The self-test menu is displayed
(Example 4-30).

Boot ROMs and Diagnostics 4-49

KDJ11-E Monitor Version 1.06 30-Jul-1990
Licensed to Digital Equipment Corporation

•

67 CPU Test
66 MMU Test
65 Pre-console Test
64 MSER Test
63 CCR r/w Test
62 HIT/MISS-Reg Test
61 LTC Speed Test
60 Add-Stat-Reg Test
57 CPU-Err-Reg Test
55 UBA Reg. Resp. Test 1
,
54 Address 0 Test
53 Pre-Memory (0-4KW) Test
52 FPA Register Test
51 FPA Function Test
50 Int Mem Address Test
47 Int Mem Data Test
46 PIRQ-Reg Test
45 LTC Int Test
44 Lines Config. Test
43 Serial Lines Test
40 Memory parity Test
37 UBA Map Reg Test 1
36 UBA NPR Cycle Test 1
32 Loopback SLU Test
30 All Selected Tests

=tt
Repeat counter = 000000 tt
New =at

Test number = 67~

Example 4-30

•
•

New

Self-Test Menu

List of tests that can be selected.
32 Loopback SLU Test requires that turnarounds are installed on the SLU's
(1-7).

Test number lists the currently selected test.

e New allows you to change the currently selected test by entering a new test
number.

•

Repeat counter lists the currently selected number of times to repeat a test.

e New allows you to change the currently selected number of times to repeat a test
by entering a new number.
3. Enter the number of the new test to be run.
4.

Enter the number of the times the new test is to be repeated. Enter 0 if you want the
test to run continuously.

5. Press Return to start the testing.

UNIBUS systems only

4-50 Boot ROMs and Diagnostics

During the testing, the test number, description of the test, error count and repeat
number are displayed and printed. If continuous testing is selected, no information
will be printed except for errors to allow the Diagnostic Command to run for an
extended period of time.
6. Press CtrllC or CtrllP to stop the testing.
Selecting and Executing a Group of Tests

To select and execute a group of tests:
1. Type S on the command line on the main menu.

2. Press Return to execute the Setup command. The setup menu is displayed
(Example 4-31).
KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
Setup Mode Commands
1 Exit
2 Select configuration parameters
3 Select diagnostic configuration
4 Select serial line parameters
5 Select boot parameters
6 List available boot programs
7 Factory setting
8 Save the setup table in the EEPROM
9 Load EEPROM data into the setup table
10 Load EEPROM boot program into memory
11 Edit or create EEPROM boot program
12 Save a boot program in the EEPROM
13 Delete a saved EEPROM boot program
14
Enter ROM ODT
Commands are: [1, 2, 3, 4, 5, 6, 7,8 ,9 10, 11, 12, 13, 14]
type a command then press the RETURN key:

Example 4-31

Setup Menu

3. Type 3 on the command line of the setup menu.
4. Press Return to execute the setup mode command 3. The following list is displayed:

Boot ROMs and Diagnostics 4-51

KDJ11-E Monitor Version 1.06 30-Jul-1990
(C) Digital Equipment Corporation 1990
A Nr. 67 CPU Test

(0) .. No

(1)

Yes

- 1

B Nr. 66 MMU Test

(0) -

(1)

Yes

- 1

C Nr. 65 Pre-Console Test

(0)

== No

(1)

::I

Yes

- 1

D Nr. 64 MSER Test

(0)

::z

(1)

== Yes

- 1

E Nr. 63 CCR r/w Test

(0) - No

(1) - Yes

... 1

F Nr. 62 HIT/MISS-Reg Test

(0) ""

(1)

Yes

- 1

G Nr. 61 LTC Speed Test

(0) -

(1) - Yes

- 1

H Nr. 60 Add-Stat_Reg Test

(0) - No

(1)

Yes

- 1

I Nr. 57 CPU-Err-Reg Test

(0) - No

(1) - Yes

- 1

J Nr. 55 UBA Reg. Resp. Testt»

(0) "" No

(1) - Yes

,.. 1

K Nr. 54 Address 0 Test

(0)

(1) - Yes

... 1

L Nr. 53 Pre-Memory (O-4KW) Test

(0)

== No

(1)

== Yes

== 1

M Nr. 52 FPA Register Test

(0)

== No

(1)

Yes

N Nr. 51 FPA Function Test

(0) ""

(1)

Yes

- 1

o Nr. 50 Int Mem Address Test

(0) -

(1)

Yes

P Nr. 47 Int Mem Data Test

(0) -No

(1)

== Yes

- 1

Q Nr. 46 PIRQ-Reg Test

(0) - No

(1) -

Yes

== 1

R Nr. 45 LTC Int Test

(0)

(1)

== Yes

S Nr. 44 Lines Config. Test

(0)

== No

(1)

== Yes

- 1

T Nr. 43 Serial Lines Test

(0) == No

(1) == Yes

- 1

U Nr. 40 Memory parity Test

(0) - No

(1) - Yes

== 1

V Nr. 37 UBA Map Reg Testt»

(0) - No

(1) == Yes

== 1

W Nr. 36 UBA NPR Cycle Testt»

(0) == No

(1) - Yes

- 1

X Nr. 32 Loopback SLU Test

(0)

== Yes

== 1

(1) == Yes

== 1

== Yes

Y Nr. 31 Extended Memory Test

(0) == No

Z Nr. 30 All Selected Tests

(0) =

(1)

Type CTRL\Z to exit or press Return key to proceed

Example 4-32

Selecting Individual Tests

t» UNIBUS systems only

5. To deselect a test, enter 0 at the appropriate test number.
6. To select a test, enter 1 at the appropriate test number.
7. Press Return to return to the main menu.
8. Enter D on the main menu to select and execute the diagnostic command. The
self-test menu is displayed (Example 4-30).
9. Enter 30 as the number of the new test to be run. Test 30 runs the group of tests
previously selected in setup command 3.

4-52

Boot ROMs and Diagnostics

10. Enter the number of the times test 30 is to be repeated. Enter 0 if you want test 30

to run continuously.
11. Press Return to start the testing.

During the testing, the test number, description of the test, error count, and repeat
number are displayed and printed. If continuous testing is selected, no information
will be printed except for errors to allow the diagnostic command to run for an
extended period of time.
12. Ctr1lC or Ctr1lP stops the testing.
Table 4-25 describes the test numbers, status display numbers, and boot error numbers.
Table 4-26 provides recommendations to correct any errors that can occur during
testing.
Table 4-25 LED Display Messages and Descriptions
Number Function

Description

Test

CPU or halt switch. When the CPU is powered up or restarted the
DCOK signal causes the display to be set to 77. If the CPU hangs with
the display set to 77 then either the halt switch is on or the CPU does
not have enough logic functioning to execute an instruction out of the
ROM.

Test

CPU and MMU. Set the LED display to 76 to indicate the first
instruction has been executed without hanging up the processor. Enter
standalone mode, set PSW to priority 7 and tum off MMU. Clear PCU
and set up SP. Jump to the high page of the ROM if not already there
(173xxx).
Execute a few simple CPU tests. General register writes and reads,
branch instructions, and a simple JSR instruction.

Test

CPU ROM Checksum and Page Control Register (17777522). Use the
user PAR for stack operations and enable upper and lower page of
EPROM so that page 0 can be accessed on 173xxx and 165xxx. Test the
function of the PCR register. The following steps are performed:
•

Disable 173xxx and jump to 165xxx

•

Enable 173xxx, disable 165xxx, and jump back to higher page

•

Enable 165xxx and jump to lower page

•

Increment PCR high and compare the page number on 173774

•

Jump back to higher page and use lower page for comparison

Tum on MMU, run CPU and MMU. Test all MMU registers:
•

Test all PARs using a floating 0 and 1 pattern

•

Check with this pattern all R/W bits of PDR <14:8, 3:1>

•

Write PAR address into PAR registers to verify address uniqueness

•

Compare content of MMR2 with the PC of current instruction

•

Check RIW bits of MMR3 <5:0>

Enable the memory management unit.

Boot ROMs and Diagnostics -4-53

Table 4-25 (Cont.)

LED Display Messages and Descriptions

Number Function

Description

Determine if system is restarting or powering up. Determine if the
ROM code has started by the CPU being powered up or restarted, by
use of the Restart switch on the front panel.

Test

**UNmus Systems**
Test the state of bit 7, Reboot Pulse, of the Memory Configuration
Register. (17777734)
Bit 7 = 1 System is being started by use of the Restart switch on the
front panel.
Bit 7 = 0 System is being powered up.
**Q-bus Systems**
Test the state of bit 14, Reboot Pulse, of the Control/Status Register
, (17777520).
Bit 14 = 1 System is being started by use of the Restart switch on the
front panel.
Bit 14 = 0 System is being powered up.
72

Test

EEPROM Checksum. This test will verify EEPROM checksum. If a
checksum error is found dialog mode is entered. The user should do a
factory setting to write a good EEPROM checksum.
The ROM code will branch in the following way:
A

Check the state of the Force Dialog switch. If switch 5 is in the ON
position go to Dialog Mode no matter what the Restart or Power up
option was set to.

B. Compare EEPROM Checksum, on error jump to Dialog Mode.
C. If '!rap 24 was selected as a Power-up or Restart Option go to Test
70.
D. If ODT was selected as a Power-up or Restart Option go to Test 71.
E. Determine what diagnostic selections previously selected.
71

Status
Display

This is not a test. It is the display that indicates that the selected
Power-uplRestart mode is ODT. A limited set of diagnostics is run and
the ROM code executes a HALT instruction and passes control to the
micro-ODT code. The EEPROM parameter are installed and the MMU
is disabled.
If the operator proceeds from ODT without changing any registers the
ROM code will continue to run selected tests and enter dialog mode
when complete.

4-54 Boot ROMs and Diagnostics

, Table 4-25 (Cont.) LED Display Messages and Descriptions

Number Function

Description

System Start Mode Trap 24. This is not a test. If the selected startup
Irestart mode is 24126 then check the status of the ignore battery status
parameter in the EEPROM.

Status
Display

*** Ignore Battery parameter = No.
If the Battery Backup Reboot Enable Bit in the Control Status Register
(177777520 bit 15) is cleared indicating that the battery backup
maintained voltages during the previous power fail. The ROM code
loads the contents of location 26 into the PSW and then transfers
control to the address specified by the contents of location 24. The
EEPROM parameters are installed and the MMU mapping is disabled.
If BBRE is set, Battery Backup failed to maintain memory voltages, go
to Dialog Mode.

*** Ignore Battery parameter = Yes.
Unconditionally the ROM code loads the contents of location 26 into the
PSW and then transfers control to the address specified by the contents
of location 24. The EEPROM parameters are installed and the MMU
mapping is disabled.

Boot ROMs and Diagnostics 4-55

Table 4-25 (Cont.) .LED Display Messages and Descriptions
Number Function

Description

Miscellaneous CPU. There are 10 CPU diagnostics implemented to test
the CPU instruction set:

Test

Test A Branch instruction test
BEQ, BNE, BMI, BPL, BVS, BVC, BCS, BCC, BLT, BGT, BLE,
BGE, BLOS, BHI, BR
Test B Single operand instruction destination mode 0
CLR, COM, NEG, ROR, ROL, ADC, SBC, ASR, ASL, INC, DEC,
TST

Test C Byte single operand instruction destination mode 0
CLRB,COMB,NEGB,SVVAB,RORB,ROLB,ADCB,SBCB,
ASRB,ASLB,INCB,DECB,TSTB
Test D Double operand word instruction all source modes
destination mode o.
MOV, CMP, ADD, SUB, BIC, BIS, BIT, XOR
Source mode 0
Source mode 1
Source mode 2
Source mode 3
Source mode 4
Source mode 5
Source mode 6
Source.mode 7
Test E Jump instruction destination modes 1, 3, 6
JMP

Mode 1
Mode 3
Mode 6
Test F TSTB and TST destination mode 1, 2, 4, PC reI addr
TST, TSTB
Mode 1
Mode 2
Mode 4
PC relative addr

4-56

Boot ROMs and Diagnostics

Table 4-25 (Cont.) LED Display Messages and Descriptions
Number Function

Description
Test G Byte double operand instruction destination mode 0
BICB, BITB, BISB, MOVB, CMPB
Source mode 1
Source mode 2
Source mode 4
PC relative addr
Test H Single and Double Operand Instructions Mode 1-7
ADC, ADD, ASL, ASR, BIC, BIS, BIT, CLR, CMP, COM, DEC,
INC, MOV, NEG, ROL, ROR, SUB, TST
Test Ii Byte instruction destination modes 1-7
CLRB,COMB,SBCB,INCB,NEGB,DECB,SWAB,ASLB,
RORB, ASRB, ROLB, ADCB, CMPB, BISB, BICB, BITB
Test J JSR instruction destination mode 7

Test

MMU Modes and Aborts. 'Thst the memory management unit in kernel,
supervisor and user mode. All three modes are read and write with
byte/word access. 'Thst memory management violation and error bits.
'Thst that the protection bits in the PDRs will cause aborts when the
conditions are violated. Verify that abort occurs through virtual address
250. Verify that MMR1 properly records changes in the general purpose
registers affected by the abort.

Pre-console

Test the console transmitter ready bit. Send a nonprinting character to
console and wait in a time-out loop for the ready bit.
Identify the terminal type... Hardcopy of Video 'Thrminal.
The ROM code supports a VT100, VT220, VT330. All other terminal
types will be set up as hard copy.
From now on, a message including test number and a short description
will be displayed for the next tests on the terminal.

Test

MSER Test read/write access of the Memory. System Errror Register
(17777744).

Test

CCR RJWfl'imeout. Rotate pattern through the Cache Control Register
(17777746) to check RIW bits.

Test

HitlMiss Register. 'Thst force miss condition. Produce a stream of MISS
cycles to check the function of the HitlMiss Register (17777752).

Test

LTC Speed. Test the Line Time Clock. Test the On-board 50HZ, 60HZ
and 800HZ clock source. A internal software loop is used to verify clock
speeds. The interrupt logic is not tested here.

Test

Additional Status Register 'Thst (17777526). Tests the functionality of
ASR bits 12 and 13, serial line address/vector selection logic. Test the
functionality of ASR bits 4 and 5, internal memory address encoding.

Boot ROMs and Diagnostics 4-57

Table 4-25 (Cont.) LED Display Messages and Descriptions

Number Function

Description

CPU Error Conditions (CPU Error Register). 'Thst the CPU Error
Register (17777766). Verify the error detection logic is functioning.
Error conditions will be created to test error detection logic.

'Thst

The following errors will be tested:
•

Bit 6: word access to an odd byte address

•

Bit 5: access to a nonexistent memory address

•

Bit 4: access to a nonexistent 110 address

NOTE: Address 1776600 is used for a timeout address. If 1776600 exists
,on the system this test will fail.
Verify bits 3 •. 0 are read only.
56

'Thst

Reserved

'Thst

UBA register response test ***UNIBUS Systems Only***
Test that the DCSR, KMCR and DDR respond properly on the UBA.
Test the KMCR with a data pattern.
Enable UBA diagnostic mode and read the following UNIBUS lines.
UNmUS Address Lines
UNmUS Data Lines 15:00
UNmUS Control Lines: CO, Cl, PB, SSYN, MSYN

'Thst

Verify that memory exists at location O. Rotate pattern through memory
location O. 'Thst read/modify/write with bus lock.

'Thst

Test memory from 0 to 4 KW. This test fully checks out the first 4 KW of
memory before the main memory tests are loaded and run.
The following steps are performed:
•

Write pattern (101010 .. ) in ascending order into memory to verify
data

•

Complement, read, and compare data in descending order

•

Write physical address as data into memory in ascending order to
verify address uniqueness

•

Compare memory address data in descending order

'Thst

FPA Register. Check the bits of the floating-point register. Rotate a bit
through the register ACO-AC5 and execute instructions in doubleprecision mode. The results are stored in memory and compared
with the pattern. An error will occur if no floating-point accelerator
is available.

'Thst

FPA Function. Clear ACO-AC5 and memory space, set double precision
mode. 'Thst the following instructions.
LDFPS, STFPS, SETD, CLRD, STD, LDD, LDCID, ADDD, DIVD, MOD,
SUBD, STCDI, CFCC

4-58

Boot ROMs and Diagnostics

. Table 4-25 (Cont.) LED Display Messages and Descriptions
Number Function

Description

Test

Internal Memory Address Test. This test verifies the address
uniqueness of the whole internal memory. The segment address is
written as data on each segment address of internal memory, starting
from physical 0 to the end of internal memory. The data is compared in
descending order. During the whole test parity abort is enabled.

Test

Internal Memory Data Test. This test will verify all of memory with
data patterns.
Write pattern in ascending order into memory.
Compare all data in descending order.
Complement all data in ascending order.
Compare complemented data in descending order.
Parity is enabled for this test.
If a memory error occurs the following information will be printed:
The memory address
Expected pattern
Pattern read

Test

PIRQ Interrupt Level Test. This test checks the software interrupt
facility of the CPU. A trap table is installed in RAM to detect
unexpected interrupts.

PSW

pmQ
Level

Interrupt
Level

Expect Interrupt
Vector

240
240
240
240
240
240
240

Next test sets PIRQ and PSW intelTUpt to the same level. Interrupt
should only occur after decrementing PSW level by one step. Repeat
with all interrupt levels.
Last tests starts with the lowest PSW interupt level, enable all PIRQ
interrupt, count and compare interrupt events. Repeat the loop with all
PSW interrupt levels.
45

Test

LTC Interrupt Test. Test the line time clock interrupt facility for the
50, 60, 800 Hz clock source. Test the ability of the clock to interrupt to
location 100 and that it can interrupt at the correct BR Level. On an
interrupt, once the. clock is in sync, check that bit 7 (LCM) is cleared on
an interrupt.

Test

SLU Configuration. Check transmitter ready bit and look for correct
configuration of all Serial Lines Units.

Boot ROMs and Diagnostics 4-59

Table 4-25 (Cont.) .LED Display Messages and Descriptions

Number Function

Description

Test

SLU Function. 'Thst the receiver and transmitter interrupt ability of all
the Serial Line Units. Show received characters with corresponding port
number if turnaround connectors installed.

Test

Reserved

Test

Reserved

Test

Memory Parity. Memory Parity Error bit is tested by creating parity
errors. Memory is tested in 4 KW segments.

Test

UBA Mapping Registers Test ***UNmUS Systems Only***
Test all 32 UNmUS Map Register pairs with a rotating 1s and Os
pattern and an address uniqueness pattern. All 32 register pairs are
tested.

Test

UBA NPR ReadlWrite Cycles ***UNmUS Systems Only***
With mapping disabled execute a floating 1s and Os test through a
floating address pattern using diagnostic Data In and Out cycles for
124K words of memory if present.
With mapping enabled, execute a floating 1s and Os test through a
floating address pattern using diagnostic Data In and Out cycles for up
to 2044K words of memory if present. This test floats a 1 and 0 across
both inputs to the UBA address adder.
This tests that the UNmUS can write and read alIOs and 1s.

Test

Not Used

Test

Not Used

Test

Serial Line Unit 'Thst **Install 1Urnaround Connectors**
This test assumes all lines have turnaround connectors installed. This
test uses the EEPROM Configuration Parameter (Baudrate, Data Bits,
Stop Bits, Parity) to check the data rate of the serial lines. It calculates
first a counter value dependent on the EEPROM parameter. Then it
checks the port to see whether all loop back connectors are installed.
The routine installs the RX vectors for the receiver interrupt routine and
starts to transmit a fixed number of characters. The transmitter time is
compared with the calculated data rate. An LTC counter is running in
the background, to stop the test if no RX interrupt happens in a defined
time. All data received is compared with the data transmitted and the
error bits are monitored.

Not Used

Reserved for the MDM in "A" series enclosures only.
Not used by ROM code. This code is driven by the MDM module on
UNIBUS systems. Blower under/over speed. This is for "A" Series
UNIBUS systems only.

Not Used

Boot Error

Drive error

Boot Error

Controller error

4-60

Boot ROMs and Diagnostics

Table 4-25 (Cont.)

LED Display Messages and Descriptions

Number Function

~scription

Boot Error

Boot device selection was invalid

Boot Error

Invalid unit number selected

Boot Error

Nonexistent drive

Boot Error

Nonexistent controller

Boot Error

No tape

Boot Error

No disk

11
10

Boot Error

Invalid boot block

Boot Error

Drive not ready

Boot Error

No bootable device found while in Auto Boot Mode

06
05

Not used
Not used

Status
Display

Dialog mode

Status
Display

UBA ROM boot in progress

Status
Display

EEPROM boot in progress

Status
Display

CPU ROM boot in progress

Status
Display

Boot successful

Table 4-26

Control transferred from ROM code to booted device. The message
"Starting System" is displayed. The display blanks when it receives a
code of 00.

Error Messages

LED Display

Probable Cause

Recommended Action

1. Halt switch/button in
halt position.
2. CPU module failure.
3. UNIBUS failure.

1. Check runlhalt switch.
2. Replace the CPU module.
3. Replace UBA; verify devices on UNIBUS.

CPU module failure.

Replace the CPU module.

CPU module failure.

'Replace the CPU module.

CPU module failure.

Replace the CPU module.

1. UBA module failure.
2. CPU module failure.

1. Replace the UBA.
2. Replace the CPU module.

CPU module failure.

Replace the CPU module.

1. UBA failure.
2. CPU module failure.

1. Replace the UBA.
2. Replace the CPU module.

CPU module failure.

Replace the CPU module.

Boot ROMs and Diagnostics 4-61

Table 4-26 (Cont.) Error Messages
LED Display

Probable Cause

Recommended Action

CPU module failure.

Replace the CPU module.

CPU module failure.

Replace the CPU module.

CPU module failure.

Replace the CPU module.

CPU module failure.

Replace the CPU module.

CPU module failure.

Replace the CPU module.

Line Time Clock failure.

Replace the CPU module.

CPU module failure.

Replace the CPU module.

1. UBA failure.
2. CPU'module failure.

1. Replace the UBA.
2. Replace the CPU module.

CPU module failure.

Replace the CPU module.

CPU module failure.

Replace the CPU module.

52
51

CPU module failure.

Replace the CPU module.

CPU module failure.

Replace the CPU module.

CPU module failure.

Replace the CPU module.

CPU module failure.

Replace the CPU module.

CPU module failure.

Replace the CPU module.

CPU module failure.

Replace the CPU module.

CPU module failure.

Replace the CPU module.

1. CPU module failure.
2. SLU panel failure. 1
3. Cables from SLU to
CPU. l

1. Replace the CPU module.
2. Replace the SLU panel.
3. Check the cables from SLU to CPU.

CPU module failure.

Replace the CPU module.

UBA failure.

Replace the UBA.

UBA failure.

Replace the UBA.

1. CPU module failure.
2. 'lUrnarounds.
3. Cables from SLU to CPU.

1. Replace CPU module.
2. Check turnarounds.
3. Check cables from SLU to CPU.

CPU module failure.

Replace CPU module.

1. KDJll-E: Blower
assembly.
2. KDJ11-E: Fan assembly.

1. KDJl1-E: replace blower assembly.
2. KDJl1-E: replace fan assembly.

Boot error indicating that
the media you are trying to
to boot from is not bootable.

Reboot from another media.

Boot error.

Make sure that the NPG jumper (UNIBUS
system only) was removed if the device is
a direct memory access (DMA) controller.
Consult the device's technical manual for more
information.

1If equipped

2UNIBUS systems only

4-62

Boot ROMs and Diagnostics

Table 4-26 (Cont.) Error Messages
LED Display

Probable Cause

Recommended Action

Boot error indicating that
the mnemonic typed in
for the boot device is
either incorrect or the
boot ROM for that device is
not installed.

Enter dialog mode and list the valid devices.

Boot error indicating
an invalid unit number
selection.

The unit number after the mnemonic is not
within the acceptable range for that device. See
that device's technical manual for help.

Boot error indicating a
nonexistent drive.

The drive number you are trying to boot from is
not on the system. Enter a drive number that is
on the system.

Boot error indicating a
nonexistent controller.

The controller for the device you are trying to
boot from is not on the UNIBUS or is addressed
incorrectly.

Boot error indicating that
no tape is installed in the
drive.

Install a tape.

Boot error indicating that
no media is in the drive or
the drive LOAD button is
not in.

Boot from a drive in which media is installed.
Push the drive LOAD button in.

Boot error indicating that
the bootstrap data from the
device does not conform to
the boot block specifications.

Make sure that media is bootable. Change
setup mode to accept nonstandard boot blocks.

Boot error indicating no
media is present in the
drive or the disk drive has
not completed its spinup
function.

Boot from a drive in which media is installed.
Wait until the disk drive has completed its
spinup function.

Boot error indicating no
bootable device is found in
automatic boot mode.

Check devices in auto boot list.

CAUTION

Do not bypass errors unless all user software has been removed or write protected.

Boot ROMs and Diagnostics 4-63

4.4.2 KOJ11-E CPU Module Fault Isolation
The KDJll-E module contains:
One green power OK LED

Indicates DCOK status

One yellow LED

Indicates that dc power to the CPU module is present

Six red LEDs

Corresponds to the status display shown in Figure 4-1

If the CPU module is the suspected problem, before replacing the module:

•

Ensure that jumpers Wl and W2 are configured correctly (Figure 4-1) .
W2

TOY BATTERY

EEPROM

BOOT
EPROM

KOJ11-E

L-----~-r==,-1_SlU

EPROM

)11111111
loco':!
I(GRN) I
vvvrvvv

POWER
(YEl)

ON
OFF

~~~~liHHiI~
1

•

SWITCHPACK

MA-0325-90.0G

DIAGNOSTIC
(RED)

Figure 4-1

KDJ11-E CPU Module Layout

•

Ensure that the dual in-line package (DIP) switches are configured correctly
(Figure 4-1).

•

The three 1A fuses (F01, F02 and F03). F01 and F02 protect +12 V on the connectors
J01 (pins 30, 40, 50, and 60) and J02 (pins 10,20, 30, and 40). F03 protects +5 V on
J02 (pin 1).

4-64 Boot ROMs and Diagnostics

Table 4-27 describes some CPU failure symptoms, the probable causes, and corrective
actions.
Table 4-27 CPU Troubleshooting
Symptom

Possible Cause

Corrective Action .

TOY fails.

Defective battery.

Replace battery.

SLU ports 1-4 fail.

Defective fuse.

Replace F2.

SLU ports 5-8 fail.

Defective fuse.

Replace Fl.

No +5V on J02 pin 1.

Defective fuse.

Replace Fa.

Power LED is not lit.

No +5 V present on
the CPU module.

VerifY the presence of +5 V and ensure
that WI & W2 are configured correctly.

5
Extended LSI-11 Bus

5.1

Introduction

The processor, memory and 110 devices communicate through signal lines that constitute
the extended LSI-II bus. The extended LSI-II bus contains 4 extra address lines (BDAL
<21:18» in addition to the 38 original LSI-II bus lines. The four additional address
lines extend the 256-Kbyte physical address space of the LSI-II bus to 4 Mbytes.
Addresses, 8-bit bytes or 16-bit data words, bus synchronization, and control signals
are sent along these 42 lines. Addresses may be 16-, 18-, or 22-bits wide, depending on
the addressing capability of the processor installed in the system. The 16-bit data and
the first 16 address bits are time-multiplexed over the same 16 data/address lines. Two
additional address bits «17:16» and the memory parity bits are also time-multiplexed
over two signal lines. The signal lines are functionally divided as listed in Table 5-1 .
See Chapter 2 for a list of the extended LSI-II bus signals.
The LSI-II bus lines are treated as transmission lines that are terminated in their
characteristic impedance (ZO) at both the near and far ends of the bus. The near end of
the bus is defined as the first bus interface slot in the backplane; the far end is the last
bus interface slot.
Table 5-1

Summary Of Signal Line Functions

Quality

Function

Bus Signal Mnemonic

Data/address lines

BDAL <15:00>

Memory parity
laddress lines

BDAL <17:16>

Address lines

BDAL <21:18>

Address and data
transfer control lines

BSYNC, BDIN, BDOUT, BWTBT, BBS7, BRPLY

DMA control lines

BDMR, BDMG, BSACK

Interrupt control
lines

BIRQ4, BIRQ5, BIRQ6, BIRQ7, BIAK

System control lines

BPOK, BDCOK, BINIT, BHALT, BREF, BEVNT

Most LSI-II bus signals are bidirectional and use a terminating resistor network
connected between +5 V and ground to provide a negated (high) signal level. Devices
may be connected to any point along the bus to receive signals from the near or far end
of the bus through high-impedance bus receivers, or to transmit signals to the near or far
end through gated open -collector bus drivers. A bus driver asserts a signal by causing
the line to go from a high level (approximately 3.4 V) to a low level (approximately

5-1

5-2

Extended LSI-11 Bus

0.5 V). The electrically bidirectional lines sometimes carry signals that are functionally
unidirectional. These functionally unidirectional lines carry signals that are required to
travel in only one direction. For example, when a device asserts a bus request signal
(~IRQ), the signal always travels from the requesting device to the processor and never
in the reverse direction.
The interrupt acknowledge (BIAK) and DMA grant (BDMG) signals are physically
unidirectional signals that are wired to each LSI-11 bus slot in a daisy-chain scheme.
These signals are generated by the processor in response to interrupt and DMA requests
and are transmitted to the bus by output signal pins. Each of the output signals (BIAKO
or BDMGO) is received on a device input pin (BIAKI or BDMGI) and is conditionally
retransmitted by a device output pin (BIAKO or BDMGO). These signals are received
from higher-priority devices and are retransmitted to lower-priority devices on the bus.
Bus master/slave relationship communication between devices on the bus is
asynchronous. A master/slave relationship exists throughout each bus transaction. At
any time, there is one device that has control of the bus. This controlling device is termed
the bus master. The master device controls the bus when communicating with another
device on the bus, termed the slave. The bus master (typically the KDJI1-E processor or
a DMA device) initiates a bus transaction. The slave device responds by acknowledging
the transaction in progress and by receiving data from, or transmitting data to, the
bus master. The extended LSI-11 bus control signals transmitted or received by the
bus master or bus slave device must complete the sequence according to the protocol
established for transferring address and data information. The processor controls bus
arbitration (that is, it decides which device is to be bus master at any given time).
A typical example of a master/slave relationship is the processor, as master, fetching an
instruction from memory, which is always a slave. Another example is a disk drive, as
master, transferring data to memory, again as the slave. Any device except the processor
can be master or slave depending on the circumstances. Communication on the extended
LSI-11 bus is interlocked; for each control signal issued by the master device, there must
be a response from the slave in order to complete the transfer. It is the master/slave
signal protocol that makes the extended LSI-11 bus asynchronous. The asynchronous
operation allows both fast and slow devices to use the bus and eliminates the need for
synchronizing clock pulses between the bus master and slave device.
Since bus cycle completion by the bus master requires response from the slave device,
each bus master must include a timeout error circuit that aborts the bus cycle if the slave
device does not respond to the bus transaction within 12.8 p,s. The KDJ11-E has a bus
timer that restarts the clock when no device responds to BDIN L or BDOUT L within
12.8 p,s. An immediate trap to location 4 occurs. The slowest peripheral or memory
device must respond in less than 12.8 p,s to prevent a bus timeout error.

5.2 Bus Signal Nomenclature
Throughout the following protocol specifications, bus signals are referred to in several
different ways.
1. In general discussions where timing, polarity, and physical location are unimportant,

the base signal name without any prefixes or suffixes is used. For example:

Extended LSI-11 Bus 5-3

SYNC, WTBT, BS7, DAL <21:00> or the DAL lines
2. Most signals on the backplane etch are asserted low and are referred to with a prefix
character B, and a suffix (space) L. For example:
BSYNC L, BWTBT L, BBS7 L, BDAL <21:00> L
BPOK Hand BDCOK H are asserted high.
3. Receivers and drivers are considered to be part of the bus. Signal inputs to drivers
are referred to with a prefix character T, for transmit. For example:
T8YNC, TWTBT, TBS7, TDAL <21:00>
4. Signal outputs of receivers are referred to with the prefix character R, for receive.
For example:
RSYNC, RWTBT, RBS7, RDAL <21:00>
Whenever timing is important, the designations in items 3 and 4, listed previously, are
used to reference timing to a receiver output or driver input. For example, after receipt of
the negation of RDIN, the slave negates its TRPLY (0 ns minimum, 8000 ns maximum).
It must maintain data valid on its TDAL lines until 0 ns (minimum) after the negation
of RDIN, and must negate its TDAL lines 100 ns (maximum) after the negation of its
TRPLY.

5.3 Data Transfer Bus Cycles
Data is transferred between a bus master and slave device to accomplish various
functions. Table 5-2 describes the data transfer bus cycles and their functions.
These bus cycles, executed by bus master devices, transfer 16-bit words or 8-bit bytes to
or from slave devices. The data to be written in the destination byte during byte output
operations is valid on the appropriate BDAL lines. For example, BDAL < 15:8> contains
the high byte, and BDAL <7:0> contains the low byte. Table 5-3 describes the bus signals
used in a data transfer operation.
Data transfer bus cycles can be reduced to three basic types: DATI, DATO(B) and
DATIO(B). These transactions occur between the bus master and one slave device
selected during the addressing portion of the bus cycle.
Table 5-2 Data Transfer Bus Cycles
Bus Cycle
Mnemonic

Description

Function (with Respect to the Bus Master)

DATI

Data word input

Read

DATO

Data word output

Write

DATOB

Data byte output

Write byte

DATIO

Data word input
/output

Read-modify-write

DATIOB

Data word inputlbyte
output

Read-modify-write byte

5-4

Extended LSI-11 Bus

Table 5-3 Data Transfer Bus Signals
Mnemonic

Description

Function

BDAL <21:00> L

22 data/address lines

BDAL <21:18> L are used for 22-bit extended
addressing; BDAL <17:16> L are used for 18-bit
extended addressing, memory parity error, and
memory parity error enable functions; BDAL <15:0>
L are used for 16-bit addressing, word and byte
transfers.

BSYNCL

Synchronize

Strobe signals

BDINL

Data input strobe

BDOUTL

Data output strobe

BRPLYL

BWTBTL

Write/byte control

BBS7L

Bank 7 select

Control signals

5.3.1 Bus Cycle Protocol
Before initiating a bus cycle, the previous bus transaction must be complete (BSYNC
L negated) and the device must become bus master. The bus cycle is divided into
two parts-an addressing portion, and a data transfer portion. During the addressing
portion, the bus master outputs the address for the desired slave device (memory location
or device register). The selected slave device responds by latching the address bits and
holding this condition for the duration of the bus cycle (until BSYNC L becomes negated).
During the data transfer portion of the bus cycle, the operations which are performed
vary slightly, depending on the type of data transfer desired.
5.3.1.1 Device Addressing

The device addressing portion of a data transfer bus cycle comprises an address setup
Ideskew time and an address hold/deskew time. During the address setup/deskew time,
the bus master does the following:
1. It asserts TDAL <21:00> with the desired slave device address bits.
2. It asserts TBS7 if a device in the I/O page is being addressed.
3. It asserts TWTBT if the cycle is a DATO(B) bus cycle.
4.

It asserts TSYNC 150 ns (minimum) after gating TDAL, TBS7, and TWTBT onto the

bus.

During this time the address, RBS7, and RWTBT signals are asserted at the slave bus
receiver for at least 75 ns before RSYNC becomes active. Devices in the I/O page ignore
the 9 high-order address bits RDAL <21:13> and, instead, decode RBS7 along with the
13 low-order address bits. An active RWTBT signal indicates that a DATO(B) operation
follows, while an inactive RWTBT indicates a DATI or DATIO(B) operation.
The address hold/deskew time begins after RSYNC is asserted. The slave device uses
the active RSYNC to clock RDAL address bits, RBS7 and RWTBT, into its internal logic.
RDAL <21:00>, RBS7, and RWTBT remain active for 25 ns (minimum) after RSYNC
becomes active. RSYNC remains active for the duration of the bus cycle.

Extended LSI-11 Bus - 5-5

Memory and peripheral devices are addressed similarly, except for the way they respond
to RBS7. Addressed peripheral devices must not decode address bits on RDAL <17:13>.
Addressed peripheral devices may respond to a bus cycle only when RBS7 is asserted
during the addressing portion of the cycle. When asserted, RBS7 indicates that the
device address resides in the 110 page (the upper 8-Kbyte address space). Memory
devices generally do not respond to addresses in the 110 page. However, some system
applications may permit memory to reside in the I/O page for use as DMA buffers, ROM
bootstraps, diagnostics, etc.
5.3.1.2 DATI

The DATI bus cycle is a read operation that inputs data from the slave device to the bus
master. Figure 5-1 shows the operations performed by the bus master and slave device
during a DATI bus cycle. Figure 5-2 shows the DATI bus cycle timing. Data consists
of 16-bit word transfers over the bus. During the data transfer portion of the DATI bus
cycle, the bus master asserts TDIN 100 ns (minimum) after it asserts TSYNC. The slave
device responds to RDIN active by asserting:
1. TRPLY after receiving RDIN, and 125 ns (maximum) before TDAL bus driver data
bits are valid
2. TDAL <17:0> L with the addressed data and error information
Bus Master
(Processor or Device)

Slave
Memory Device

Address Device or Memory
• Asserts BDAL <21 :00> with
address and
• Asserts BBS7 if the address
is in the 110 page
• Asserts BSYNC L

- -- ---

- - - - - . Decode Address
• Store "Device Selected"

Request Data

~-------

- --

operation

• Remove the address from
BDAL <21 :00> Land
Negate BBS7 L
• Assert BDIN L

- -- --------.

Input Data
• Place data on BDAL <15:00> L
• Assert BRPLY L

Terminate Input Transfer

.Jc -

• Accept data and respond
by negating BDIN L

Terminate Bus Cycle
• Negate BSYNC L

~ _

-..... Operation Completed
_ _ _ _ _ _ _ _ _ • Negate BRPLY L
LJ-00176-TIO

Figure 5-1

DATI Bus Cycle

5-6 Extended LSI-11 Bus

TR DAL

TACDR

~100NS

RCata

(4)

Minimum

TSYNC
100 NS Minimum
8 ..S Maximum

T DIN

t;=

R RPLY
150 NS
!;:nlmum

TBS7

T~BT

1;::100 NS Minimum

~__~~~-_-_-_-_-~~}(~______________________(~_____________________________

:J\________

J)(~

__________________(_4)_________________________
TIMING AT MASTER DEVICE

RfT DAL

TData
125 NS Maximum

RSYNC

R DIN

TRPLY

R BS7

(4)

R~BT ~______-J)(~

__________________ _____________________________
~_)

TIMING AT SLAVE DEVICE
NOTES:
1. Timing shown at requesting device bus driver
inputs and bus receiver outputs.

3. Bus driver output and bus receiver input
signal names include a "B" prefix.

2. Signal name prefixes are defined below
T =Bus Driver Input
R=Bus Receiver Output

4. Don't care condition.

LJ-00177-TIO

Figure 5-2

DATI Bus Cycle Timing

Extended LSI-11 Bus 5-7

When the bus master receives RRPLY, it does the following:
1. It waits at least 200 ns deskew time and then accepts input data at RDAL <15:00>
bus receivers. RDAL <17: 16> are monitored for a possible parity error indication.

2. It negates TDIN 150 ns (minimum) after RRPLY becomes active.
The slave device responds to RDIN negation by negating TRPLY and removing read data
from TDAL bus drivers. TRPLY must be negated 100 ns (maximum) prior to removal of
read data. The bus master responds to the negated RRPLY by negating TSYNC.
Conditions for the next TSYNC assertion are as follows:
1. TSYNC must remain negated for 200 ns (minimum).

2. TSYNC must not become asserted within 300 ns of the previous RRPLY negation.
5.3.1.3DATO(B)

DATO(B) is a write operation. Data is transferred in 16-bit words (DATO) or 8-bit bytes
(DATOB) from the bus master to the slave device. The data transfer output can occur
after the addressing portion of a bus cycle when TWTBT has been asserted by the
bus master, or immediately following an input transfer part of a DATIO(B) bus cycle.
Figure 5-3 shows the operations performed by the bus master and slave device during a
DATO(B) bus cycle. Figure 5-4 shows the DATO(B) bus cycle timing.
The data transfer portion of a DATO(B) bus cycle comprises a data setup/deskew time
and a data hold/deskew time. During the data setup/deskew time, the bus master outputs
the data on TDAL <15:00> 100 ns (minimum) after TSYNC is asserted. If it is a word
transfer, the bus master negates TWTBT while gating data onto the bus. If the transfer
is a byte transfer, the bus master asserts TWTBT while gating data onto the bus. During
a byte transfer, the condition of BDAL 00 L during the address cycle selects the high or
low byte. If asserted, the high byte (BDAL <15:08> L) is selected. Otherwise, the low
byte (BDAL <07:00> L) is selected. An asserted BDAL 16 L at data transfer time forces
a parity error to be written into memory (if the memory is parity memory). BDAL 17 L
is not used for write operations. The bus master asserts TDOUT L 100 ns (minimum)
after the TDAL and TWTBT bus driver inputs are stable. The slave device responds to
RDOUT by accepting the input data and asserting TRPLY (8 p,s maximum to avoid bus
timeout). This completes the data setup/deskew time.
During the data hold/deskew time the bus master negates TDOUT 150 ns (minimum)
after the assertion of RRPLY. TDAL <21:00> bus drivers remain stable for at least 100
ns after TDOUT negation. The bus master then negates TDAL inputs. The slave device
senses RDOUT negation and negates TRPLY. The bus master responds by negating
TSYNC. The processor, however, does not negate TSYNC for at least 175 ns after
negating TDOUT. This completes the DATO(B) bus cycle. Before the next cycle, TSYNC
must remain unasserted for at least 200 ns. Also, TSYNC may not be asserted until 300
ns (minimum) after RRPLY is negated.

5-8

Extended LSI-11 Bus
Bus Master
(Processor or Device)
Address devicelmemory
• Assert BDAL <21 :00> L with
address and
• Assert BBS7 L if address is
in the 1/0 Page
• Assert BWTBT L (write cycle)
.• Assert BSYNC L

Slave
(Memory or Device)

--- ---

- - - - ...... Decode Address
• Store -Device Selectedoperation

... ------

Output Data
• Remove the address from
BDAL <21 :00> L and negat~ BB7 L
• Negate BWTBT L unless DATOB
• Place data on BDAL <15:00> L
• Assert BDOUT L
-

-- --- - - - - ...... Take Data

4l1li:--

Terminate Output Transfer
• Negate BDOUT L (and BWTBT L
if a DATOB bus cycle)
• Remove data from BDAL <15:00> L _

Terminate Bus Cycle

- ---

--- ---

• Receive data from BDAL lines
__ " • Assert BRPLY L

-- --

- - - ~ Operation Completed
. . _ _ _ _ _ _ _ _ _ _ • Negate BRPLY L

• Negate BSYNC L
LJ·00178·TIO

Figure 5-3

DATO or DATO(B) Bus Cycle

Extended LSI-11 Bus - 5-9

ONS Minimum

TDAL

(4)

TSYNC
81'S
Maximum

TDOUT

R RPLY
100 NS Minimum

(4)

TBS7

TWTBT

(4)

150NS
Minimum

_I
--.,

100 NS
Minimum

1'-I---

TIMING AT MASTER DEVICE

RIT DAL

RSYNC

R DIN

TRPLY

R BS7

RWTBT

TIMING AT SLAVE DEVICE

NOTES:

Figure 5-4

1. Timing shown at requesting device bus driver
inputs and bus receiver outputs.

3. Bus driver output and bus receiver input
signal names include a "B" prefix.

2. Signal name prefixes are defined below
T =Bus Driver Input
R=Bus Receiver Output

4. Don't care condition.

DATO or DATO(B) Bus Cycle Timing

LJ-00179-110

5-10

Extended LSI-11 Bus

5.3.1.4 DAlIO(B)
The protocol for a DATIO(B) bus cycle is identical to the addressing and data transfer
portions of the DATI and DATO(B) bus cycles. After addressing the device, a DATI cycle
i~ performed as explained in Section 5.3.1.2, except TSYNC is not negated. TSYNC
remains active for an output word or byte transfer DATO(B). The bus master maintains
at least 200 ns between RRPLY negation during the DATI cycle and TDOUT assertion.
The cycle is terminated when the bus master negates TSYNC, which follows the same
protocol as described for DATO(B). ~gure 5-5 shows the operations performed by the bus
master and slave device during a DATIO or DATIO(B) bus cycle. Figure fH) shows the
DATIO and DATIO(B) bus cycle timing.

Extended LSI-11 Bus 5-11

Slave
(Memory or Device)

Bus Master
(Processor or Device)
Address device memory
• Assert BDAL <21 :00> L with
address
• Assert BBS7 L if the
address is in the I/O page

--- ---

• Assert BSYNC L

Request Data
• Remove the address from
BDAL <21 :00> L
• Assert BDIN L

- - - -.... Decode Address
• Store -Device Selected"
operation

...------ --- - -- --

Terminate Input Transfer
• Accept data and respond by
terminating BDIN L

-------~

--- ----

Input Data
• Place data on BDAL <15:00> L
• Assert BRPLY L

--- -------~
Complete Input Transfer

...----- --- ----

• Remove data
• Negate BRPLY L

Output Data
• Place output data on BDAL <15:00> L
• Assert BWTBT L if an output
byte transfer
• Assert BDOUT L

Terminate Output Transfer

---- ---

- - -~

...----------

Take Data

• Receive data from BDAL lines
_ _ • Assert BRPLY L

• Remove data from BDAL lines
• Negate BDOUT L

- -- ------- ..... Operation Completed

Terminate Bus Cycle

...------ --- - --

• Negate BRPLY L

• Negate BSYNC L
(and BWTBT L if N
A DATIOB bus cycle)
W·00180·TIO

Figure 5-5

DATIO or DATIO(B) Bus Cycle

5-12

Extended LSI-11 Bus

RIT DAL

TSYNC
TDOUT

TDIN

R RPLY

TBS7

TWTBT

TIMING AT MASTER DEVICE

TIMING AT SLAVE DEVICE
NOTES:

1. Timing shown at requesting device bus driver'
inputs and bus receiver outputs.

3. Bus driver output and bus receiver input
Signal names Include a -B- prefix.

2. Signal name prefixes are defined below
T -Bus Driver Input
R-Bus Receiver Output

4. Don't care condition.

LJ·00181·TIO

Figure~

DATIO or DATIO(B) Bus Cycle nmlng

Extended LSI-11 Bus 5-13

5.4 Direct Memory Access
Direct Memory Access (DMA) capability allows direct data transfers between 110 devices
and memory. This is useful when using mass storage devices (for example, disk drives)
that move large blocks of data to and from memory. A DMA device only needs to know
the starting address in memory, the starting address in mass storage, the length of the
transfer, and whether the operation is read or write. When this information is available,
the DMA device can transfer data directly to or from memory. Since most DMA devices
must perform data transfers in rapid succession or lose data, DMA requests are assigned
the highest priority level.
DMA is accomplished after the processor (normally bus master) has passed bus
mastership to the highest-priority DMA device that is requesting the bus. The processor
arbitrates all requests and grants the bus to the DMA device located closest (electrically)
to the processor. A DMA device remains bus master until it relinquishes its mastership.
The following control signals are used during bus arbitration.
Signal

Name

BDMGIL

DMA grant input

BDMGOL

DMA grant output

BDMRL

DMA request line

BSACKL

Bus grant acknowledge

A DMA transaction is divided into three phases: the bus mastership acquisition phase,
the data transfer phase, and the bus mastership relinquish phase. Figure 5-7 shows the
operations performed by the processor and bus master during the DMA request/grant
sequence. Figure 5-8 shows the DMA request/grant bus cycle timing.

5-14 Extended LSI-11 Bus

KOJ11-E Processor
(Memory is Slave)

Bus Master
(Controller)

~-----Grant Bus Control
• Near the end of the
current bus cycle
(BRPLY L is negated) .
.Assert BOMGO Land
inhibit new processor
generated BSYNC L for
the duration of the
OMA operation.

- -- ---- ...

Terminate Grant
Sequence
• Negate BOMGO Land
wait for OMA operation
to be completed.
• Monitor the transaction to
invalidate cache if
cache hit.

Resume Processor
Operation
.Enable processorgenerated BSYNC L
(processor is bus
master) or issl,Je
another grant if BOMR
L is asserted.

--_ ..

--- ........

- ----...... --

- ........ -........ ....

-- ....

-----...... --

Request Bus
• Assert BOMR L

Acknowledge Bus
Mastership
• Receive BOMG
• Wait for negation of
BSYNC Land BRPLY L
• Assert BSACK L
• Negate BOM R L

Execute a DMA Data
Transfer
• Address memory and
transfer up to 4 words
of data as described
for DATI or DATO base
cycles.
• Release the bus by
terminating BSACK L
(no sooner than
negation of last BRPLY L)
and BSYNC L

I
Wait 4 JLS or until
another FIFO transfer
is pending before
requesting bus again.
LJ-00182·TIO

Figure 5-7

DMA Request/Grant Sequence

During the bus mastership acquisition phase, a DMA device requests the bus by asserting
TDMR. The processor arbitrates the request and initiates the transfer of bus mastership
by asserting TDMG. The maximum time between BDMR L assertion by the DMA device
and BDMGO L assertion by the processor is DMA latency. This time is processordependent. The KDJI1-E asserts TDMG 1.4 p.s (maximum) after the assertion of RDMR.

Extended LSI-11 Bus 5-15

BDMGO UBDMGI L is one of two signals that are daisy-chained through each module
in the backplane. The signal is driven out of the processor on the BDMGO L pin, enters
each module on the BDMGI L pin and exits on the BDMGO L pin. This signal passes
through the modules in descending order of priority until it is stopped by the requesting
device. The requesting device blocks the output of BDMGO L and asserts TSACK. If no
device responds to the DMA grant, the processor clears the grant and rearbitrates the
bus.
NOTE

The KDJl1·E uses a no SACK timer that clears BDMGO L if BSACK L is not
received from the DMA device within 12.8 ",seconds.
During the data transfer phase, the DMA device continues asserting BSACK L. If
multiple data transfers are performed during this phase, consideration must be given
to the use of the bus for other system functions, such as memory refresh (if required).
The actual data transfer is performed in the same manner as the data transfer portion of
DATI, DATO(B) and DATIO(B) bus cycles.

TDMR

RDMG

TSACK

RIT SYNC

RIT RPLY

r---- 0 NS
NS Minimum
Minimum ,..._ _ _ _ _ _ _
~O

TDAL
(ALSOBS7

ADDR

Data

WTBT,REF)

NOTES:
1. Timing shown at requesting device bus driver
inputs and bus receiver outputs.

3. Bus driver output and bus receiver input
signal names include a "B" prefix.

2. Signal name prefixes are defined below
T=Bus Driver Input
R=Bus Receiver Output

4. Don't care condition.

W·00183·TIO

Figure 5-8

DMA Request/Grant Bus Cycle Timing

The DMA device can assert TSYNC L for a data transfer 0 ns (minimum) after it receives
RDMGI L, 250 ns (minimum) after RSYNC is negated, and 300 ns (minimum) after
RRPLY is negated.

5-16

Extended LSI-11 Bus

During the bus mastership relinquish phase, the DMA device relinquishes the bus by
negating TSACK. This occurs after the last data transfer cycle (RRPLY negated) is
completed (or aborted). TSACK may be negated up to 300 ns (maximum) before negating
TSYNC.

5.5 Interrupts
The interrupt capability of the LSI-1! bus allows any 110 device to temporarily suspend
(interrupt) current program execution and divert processor operation for service of the
requesting device. The processor inputs a vector from the device to start the service
routine (handler). As with a device register address, the hardware fixes the device vector
at locations within a designated range of addresses between 000 and 777. The vector
indicates the first of a pair of addresses. The content of the first address is read by the
processor; it is the starting address of the interrupt handler. The content of the second
address is a new PSW. PSW bits <07:05> can be programmed to a priority level from 0
to 7. Only interrupts on a level higher than the number in the PSW priority level field
are serviced by the processor. If the interrupt priority level of the new PSW is higher
than that of the original PSW, the new PSW raises the interrupt priority level and thus
prevents lower-level interrupts from breaking into the current interrupt service routine.
Control is returned to the interrupted program when the interrupt service routine is
complete.
The original (interrupted) program address (PC) and its associated PSW are stored on
a stack. The original PC and PSW are restored by a return from interrupt instruction
(RTI or RTT) at the end of the service routine. The use of the stack and the LSI-11 bus
interrupt scheme can allow interrupts to occur within interrupts (nested interrupts) if
the requesting interrupt has a higher priority level than the interrupt currently being
serviced.
Interrupts can be caused by LSI-11 bus options and can also originate in the processor.
Interrupts originating in the processor are called traps and are caused by programming
errors, hardware errors, special instructions, and maintenance features. The LSI-11 bus
signals used in interrupt transactions are listed here.
Signal

Name

BIRQ4 L

Interrupt request priority level 4

BIRQ5 L

Interrupt request priority level 5

BIRQ6 L

Interrupt request priority level 6

BIRQ7 L

Interrupt request priority level 7

BIAKI L

Interrupt acknowledge input

BIAKOL

Interrupt acknowledge output

BDAL <15:00> L

Data/address lines

BDINL

Data input strobe

BRPLYL

Extended LSI·11 Bus 5-17

5.5.1 Device Priority
The LSI·11 bus supports the following two methods of determining device priority:
•

Distributed arbitration - Priority levels are implemented on the hardware. When
devices of equal priority level request an interrupt, priority is given to the device
electrically closest to the processor.

•

Position·defined arbitration - Priority is determined solely by electrical position on
the bus. The device closest to the processor has the highest priority, while the device
at the far end of the bus has the lowest priority.

The KDJ11·E uses both methods-distributed arbitration, with four levels of priority,
and position·defined arbitration within each level. Interrupts on these priority levels
are enabled/disabled by bits in the processor status word (PSW <07:05». Single-level
interrupt (position-defined) devices that interrupt on BIRQ4 can also be used in KDJ11·E
systems, but must be placed in a bus slot following the last bus slot in which a positionindependent device is installed.

5.5.2 Interrupt Protocol
Interrupt protocol has three phases: the interrupt request phase, the interrupt
acknowledge and priority arbitration phase, and the interrupt vector transfer phase.
Figure 5-9 shows the operations performed by the processor and interrupting device.
Figure 5-10 shows the interrupt protocol timing.

5-18

Extended LSI-11 Bus

Processor"

Strobe Interrupts
• Assert BOIN L

I
I
I

Device
~------

Request
---- Iniate
• Assert BIRQ L

--- --- - - - -.... Receive BOIN L
• Store -Interrupt Sendingin device.

Grant Request
• Pause and assert BIAKO L

-- --JIIIII:-

Receive Vector and
Terminate Request
• Input vector address
• Negate BOIN L and BIAKO L

- ~ Receive BIAKI L
• Receive BIAKI L and inhibit
BIAKOL
• Place vector on BOAL <15:00> L
• Assert BRPLY L
• Negate BIRQ L

--- -----

--- --- ---- ....

Process the Interrupt
• Save interrupted program
PC and PS on stack
• Load new PC and PS from
vector address location
• Execute interrupt service
routine for the device

---- -----

--- ---

Complete· Vector Transfer
• Remove vector from BOAL bus
• Negate BRPLY L

W"()()184·T10

Figure 5-9

Interrupt Request/Acknowledge Sequence

Extended LSI-11 Bus 5-19

=~e~~~me
TIRQ

RDIN

R 1AKI

T RPlY

(4)

TDAl

(UnalSened)

RSYNC

(Unassened)

RBS7

NOTES:
1. Timing shown at requesting device bus driver
inputs and bus receiver outputs.

3. Bus driver output and bus receiver Input
signal names Include a -B- prefix.

2. Signal name prefixes are defined below
T =Bus Driver Input
R=Bus Receiver Output

4. Don't care condition.

Figure 5-10

W·OO185·TIO

Interrupt Protocol Timing

The interrupt request phase begins when a device meets its specific conditions for
interrupt requests (for example, when the device is ready, done, or when an error has
occurred). The interrupt enable hit in a device status register must be set. The device
then initiates the interrupt by asserting the interrupt request line(s). BIRQ4 L is the
lowest hardware priority level and is asserted for all interrupt requests for compatibility
with previous LSI-11 processors. The level at which a device is configured must also be
asserted. (A special case exists for level 7 devices that must also assert level 6.) The
interrupt request line remains asserted until the request is acknowledged.
Interrupt
Level

Lines Asserted By Device

BffiQ4L

BIRQ4 L, BffiQ5 L

BIRQ4 L, BffiQ6 L

BffiQ4 L, BffiQ6 L, BffiQ7 L

5-20

Extended LSI-11 Bus

During the interrupt acknowledge and priority arbitration phase, the KDJ11-E
acknowledges interrupts under the following conditions:
1. The device interrupt priority is higher than the current priority level stored in PSW

<07:05>.
2. The processor has completed instruction execution and no additional bus cycles are
pending.
The processor acknowledges the interrupt request by asserting TDIN and, 225 ns
(minimum) later, by asserting TIAKO. The device electrically closest to the processor
receives the acknowledgment on its RIAKI bus receiver.
On the leading edge of RDIN, each bus option capable of requesting interrupts decides
whether to accept or to pass on the RIAKI signal. A device that does not support positionindependent, multilevel interrupts accepts RIAKI if it is requesting an interrupt when
RDIN asserts. A device that does support position-independent, multilevel interrupts
accepts RIAKI if it is requesting an interrupt and if there is no higher-priority request
pending when RDIN asserts. This decision must be clocked into a flip-flop, which settles
within 150 ns ofTDIN.
Devices that support position-independent, multilevel interrupts assert from one to
three interrupt request lines when requesting an interrupt. Table 5-4 presents the
Interrupt Request (IRQ) lines that a device at each level must assert in order to request
an interrupt. Table 5-4 also lists the lines it must monitor to determine whether a
higher-priority device is requesting an interrupt.
During the interrupt vector transfer phase, the responding interrupt device receives
RIAKI and then asserts TRPLY. The vector address must be stable at TDAL <8:2> 125 ns
(maximum) after TRPLY is asserted. The processor receives the assertion of RRPLY and,
200 ns (minimum) later, it inputs the vector address and negates both TDIN and TIAKI.
The interrupting device negates TRPLY after the negation of RIAKI, and removes the
vector address from TDAL <8:2> 100 ns (maximum) after TRPLY negates. Since vector
addresses are constrained between 000 and 774, none of the remaining TDAL lines are
used.

Table 5-4 Position-Independent, Multilevel Device Requirements
Interrupt
Level

IRQ Lines
Asserted

IRQ Lines Monitored

4
5

TIRQ4

RIRQ5, RIRQ6

TIRQ4, TIRQ5

TIRQ4, TIRQ6

RIRQ6
RIRQ7

TIRQ4, TIRQ6,
TIRQ7

5.5.3 4-Level Interrupt Configurations
Users having high-speed peripherals and desiring better software performance can
use the 4-level interrupt scheme. Both position-independent and position-dependent
configurations can be used with the 4-level interrupt scheme.

Extended LSI-11 Bus 5-21

Figure 5-11 shows the position-independent configuration. This configuration allows
peripheral devices that use the 4-level interrupt scheme to be placed in the backplane
in any order. These devices must send out interrupt requests and monitor higher-level
request lines, as described in Section 5.5.2. The level 4 request is always asserted by a
requesting device, regardless of priority, to allow compatibility if an LSI-II or LSI-1112
processor is in the same system. If two or more devices of equally high priority request
an interrupt, the device physically closest to the processor wins arbitration. Devices that
use the single-level interrupt scheme must be modified or be placed at the end of the bus
for arbitration to function properly.
Figure 5-12 shows the position-dependent configuration. This configuration is simpler to
implement, but has the following constraint: peripheral devices must be ordered so that
the highest-priority device is located closest to the processor, with the remaining devices
placed in the backplane in decreasing order of priority.
With the position-dependent configuration, each device must assert only its own level and
level 4 (for compatibility with an LSI-II or LSI-1112). Monitoring higher-level request
lines is unnecessary. Arbitration is achieved through the physical positioning of each
device on the bus. Single-level interrupt devices on level 4 must be positioned last on the
bus.
BIAK (Interrupt Acknowledge)

...

KDJ11

'!,U

BIRO 4 (Level 4 Interrupt Request)

Level 4
Device

BIAK

r----

Level 6
Device

+' "

BIRO 5 (Level 5 Interrupt Request)
BIRO 6 (Level 6 Interrupt Request)

BIAK
~

Level 5
Device

BIAI<

r-----

Level 7
Device

~ if

BIRO 7 (Level 7 Interrupt Request)
LJ-00186-TIO

Figure 5-11

Position-Independent Configuration

BIAK (Interrupt Acknowledge)

KDJ11

,, ,
~

Level 7
Device

BIRO 4 (Level 4 Interrupt Request)

BIAK

----...

Level 6
Device

BIRO 5 (Level 5 Interrupt Request)
BIRO 6 (Level 6 Interrupt Request)

BIAK

r----.

Level 5
Device

BIAI<

-----

Level 4
Device

BIRO 7 (Level 7 Interrupt Request) ~
LJ-00187-TIO

Figure 5-12

Position-Dependent Configuration

5-22

Extended LSI-11 Bus

5.6 Control Functions
The following LSI-11 bus signals provide system control functions:
Signal

Name

BREFL

Memory refresh

BHALTL

Processor halt

BINIT L

Initialize

BPOKH

Power OK

BDCOKH

DC power OK

BEVNTL

External event interrupt request

5.6.1 Halt
The assertion of BHALT L stops program execution and forces the processor
unconditionally into console ODT mode. The processor does not assert the BHALT L
bus line when it comes to a programmed halt.

5.6.2 Initialization
Devices along the bus are initialized when BINIT L is asserted. The processor asserts
the BINIT L signal under the following conditions:
1. During a power-down sequence
2. During a power-up sequence
3. During the execution of a RESET instruction
4. After detection of a G character in ODT mode (if the processor features an ODT mode
and a G command within it), and before execution ~f the code starting at the address
that preceded the G command

5.6.3 Power Status
Power status protocol is controlled by two signals, BDCOK H and BPOK H. These signals
are driven by an external device (usually the power supply) and are defined in the
following sections:
5.6.3.1 BDeOK H

The assertion of this line indicates that dc power has been stable for at least 3 ms. Once
asserted this line remains asserted until the power fails.
5.6.3.2 BPOK H

The assertion of this line indicates that there is at least an 8 ms reserve of dc power and
that BDCOK H has been asserted for at least 70 ms. Once BPOK H has been asserted, it
must remain asserted for at least 3 ms.
The negation of this line indicates that power is failing and that only 4 ms of dc power
reserve remains. The negation of this line during processor operation initiates a powerfail trap sequence.

Extended LSI-11 Bus 5-23

5.6.3.3 Power-Up

The following events occur during a power-up sequence:
1. Logic associated with the power supply negates BDCOK H during power-up and
asserts BDCOK H 3 ms (minimum) after dc power is restored to voltages within
specification.
2. The processor asserts BINIT L after receiving nominal power and negates BINIT L 0
ns (minimum) after the assertion of BDCOK H.
3. Logic associated with the power supply negates BPOK H during power-up and asserts
BPOK H 70 ms (minimum) after the assertion of BDCOK H. If power does not remain
stable for 70 ms, BDCOK H is negated. Therefore, devices must suspend critical
actions until BPOK H is asserted.
4. BPOK H must remain asserted for a minimum of 3 ms. BDCOK H must remain
asserted 4 ms (minimum) after the negation of BPOK H.
5.6.3.4 Power-Down

The following events occur during a power-down sequence:
1. If the ac voltage to a power supply drops below 75% of the nominal voltage for one
full line cycle (15 to 24 ms), BPOK H is negated by the power supply. Once BPOK H
is negated, the entire power-down sequence must be completed.
A device that requested bus mastership before the power failure that has not become
bus master must maintain the request until BINIT L is asserted or the request is
acknowledged (in which case regular bus protocol is followed).
2. Processor software must execute a RESET instruction 3 ms (minimum) after the
negation of BPOK H. This asserts BINIT L for 8 to 20 JJS. Processor software executes
a HALT instruction immediately following the RESET instruction.
3. BDCOK H must be negated a minimum of 4 ms after the negation of BPOK H. This
4 ms allows mass storage and similar devices to protect themselves against erasures
and erroneous writes during a power failure.
4. The processor asserts BINIT L 1 JJS (minimum) after the negation of BDCOK H.
5. The dc power must remain stable for a minimum of 5 JJS after the negation of BDCOK

H.
6. BDCOK H must remain negated for a minimum of 3 ms.

5.6.4 BEVNT l
The BEVNT L signal is an external line clock interrupt request to the processor. When
BEVNT L is asserted, the processor internally assigns location 100 as the vector address
for the BEVNT service routine. Because the vector is internally assigned, the processor
does not execute the protocol for reading in the interrupt vector address (as is the case
for other external interrupt requests).

5.7 Bus Electrical Characteristics
This paragraph contains information about the electrical characteristics of the LSI-1!
bus.

5-24 Extended LSI-11 Bus

5.7.1 Signal Level Specification
Input Logic Levels
TTL logical low:

0.8 Vdc (maximum)

TTL logical high:

2.0 Vdc (minimum)

Output Logic
Levels
TIL logical low:

0.4 Vde (maximum)

TTL logical high:

2.4 Vdc (minimum)

5.7.2 AC Bus Load Definition
The amount of capacitance a module presents to a bus signal line is the ac bus load. This
capacitance is measured between each module signal line and ground, and is expressed
in ac unit loads, where each unit load is defined as 9.35 pF.

5.7.3 DC Bus Load Definition
The amount of leakage current a module presents to a bus signal line is the dc bus load.
A dc unit load is defined as 105 pA flowing into a module device when the signal line is
in the unasserted (high) state.

5.7.4 120 n LSI·11 Bus
The electrical conductors interconnecting the bus device slots are treated as transmission
lines. A uniform transmission line, terminated in its characteristic impedance,
propagates an electrical signal without reflections. Because bus drivers, receivers,
and wiring connected to the bus have finite resistance and nonzero reactance, the
transmission line impedance becomes nonuniform, and therefore introduces distortions
into pulses propagated along it. Passive components of the LSI-11 bus (such as wiring,
cabling, and etched signal conductors) are designed to have a nominal characteristic
impedance of 120 n .
The maximum length of the interconnecting cable in multiple-backplane systems
(excluding wiring within the backplane) is limited to 4.88 m (16 ft).
NOTE

The KDJ11-E processor (as well as all standard Digital-supplied LSI-11
interfaces) connects to the bus via special drivers and receivers des·~ribed in
Section 5.7.5 and Section 5.7.6.
The KDJ11-E processor provides resistive (250 n) pull-up on all bussed lines to
3.4 Vdc for this wired-OR interconnecting scheme.

Extended LSI-11 Bus -5-25

5.7.5 Bus Drivers
Devices driving the 120 n LSI -11 bus must have open collector outputs and meet the
specifications that follow.

DC Specifications l
•

Vcc may vary from 4.75 V to 5.25 V.

•

Output low voltage when sinking 70 rnA of current: 0.7 V (maximum).

•

Output high leakage current when connected to 3.8 Vdc: 25 p.A (even if no power is
applied to them, except for BDeOK H and BPOK H).

AC Specifications
•

Bus driver output pin capacitance load: not to exceed 10 pF.

•

Propagation delay: not to exceed 35 ns.

•

Driver skew (difference in propagation time between slowest and fastest bus driver):
not to exceed 25 ns.

•

Rise/fall times: transition time from 10% to 90% for positive transition, and from 90%
to 10% for negative transition, must be no faster then 5 ns.

5.7.6 Bus Receivers
Devices that receive signals from the 120 n LSI-11 bus must meet the following
requirements.

DC Specifications2
•

Vcc may vary from 4.75 V to 5.25 V.

•

Input low voltage: 1.3 V (maximum).

•

Input high voltage: 1.7 V (minimum).

•

Maximum input leakage current when connected to 3.8 Vdc: 80 p.A with Vcc between
0.0 V and 5.25 V.

AC Specifications
•

Bus receiver input pin capacitance load: not to exceed 10 pF.

•

Propagation delay: not to exceed 35 ns.

•

Receiver skew (difference in propagation time between slowest and fastest receiver):
not to exceed 25 ns.

5.7.7 Bus Termination
The 120 n LSI-11 bus should be terminated at each end by an appropriate resistive
termination. A pair of resistors in series from +5.0 V to ground is used to establish a
voltage for each bidirectional1ine when that line is not being driven (negated). The
parallel impedance of this pair of resistors is 250 n. Figure 5-13 shows the terminating
resistors. The KDJ11-E contains terminating resistor networks which provide the 120 n
(terminations for the data/address, synchronization, and control lines) at the processor
end of the bus.
1

These conditions must be met at worst-case supply voltage, temperature, and input signal levels
These conditions must be met at worst-case supply voltage, temperature, and output signal levels

5-26

Extended LSI-11 Bus

Some system configurations do not require terminating resistors at the far end of the bus.
If the system configuration does require such termination, it is typically provided by an
M9404-YA cable connector module.
5.7.7.1 Bus Interconnection Wiring

The bus interface for the module connectors is provided by one, two, or three backplanes,
depending on the system configuration.
5.7.7.2 Backplane Wiring

The wiring that interconnects all device interface slots on the LSI-11 bus must meet the
following specifications:
1. The conductors must be arranged so that each line exhibits a characteristic
impedance of 120 n (measured with respect to the bus common return).
2. Crosstalk from a pulse-driven line to an undriven line to which a constant 5 V is
applied must be less than 5% of the 5 V. Note that worst-case crosstalk is manifested
by simultaneously driving all but one signal line and measuring the effect on the
undriven line.
3. The dc resistance of a bus segment signal path, as measured between the near-end
terminator and far-end terminator modules (including all intervening connectors,
cables, backplane wiring, connector-module etch, and so on), must not exceed 2 n .
4. The dc resistance of a bus segment common return path, as measured between
the near-end terminator and far-end terminator modules (including all intervening
connectors, cables, backplane wiring, connector-module etch, etc.), must not exceed
an equivalent of 2 n per signal path. Thus, the composite signal return path dc
resistance must not exceed 2 n divided by 40 bus lines, or 50 Mil. Note that
although this common return path is nominally at ground potential, the conductance
must be part of the bus wiring; the specified low-impedance return path must be
provided by the bus wiring as distinguished from common system or power ground
path.
+5 V

+5V

330n

178 n
120n

250n

Bus Line
Termination

383n
1%

680n

LJ·00188-TIO

Figure 5-13

Bus Line Termination

Extended LSI-11 Bus 5-27

5.7.7.3 Intrabackplane Bus Wiring

The wiring that interconnects the bus connector slots within one contiguous backplane is
part of the overall bus transmission line. Due to implementation constraints, the nominal
characteristic impedance of 120 n may not be achievable. Distributed wiring capacitance
in excess of the amount required to achieve the nominal 120 n impedance may not exceed
60 pF per signal line per backplane.
5.7.7.4 Power and Ground

Each bus interface slot has connector pins assigned for the following dc voltages.
Voltage

Number of pins

+5Vdc

Three pins, 4.5 A (maximum) per bus device slot

+12 Vdc

'l\vo pins, 3.0 A (maximum) per bus device slot

Ground

Eight pins, shared by power return and signal return

The maximum allowable current per pin is 1.5 A The +5 Vdc must be regulated to +5%
and the maximum ripple should not exceed 100 mV peak-to-peak. The +12 Vdc must be
regulated to +3% and the maximum ripple should not exceed 200 mV peak-to-peak.
NOTE

Power is not bussed between backplanes on any interconnecting LSI-tt bus
cables.
5.7.7.5 Maintenance and Spare Pins

There are four M SPARE pins per bus device slot assigned to maintenance (AK1, ALl,
BK1, BL1). The maintenance pins on the basic LSI-11 system are not bussed from
module to module. Instead, at each bus device slot, the maintenance pins are shorted
together as pairs. These pins must be shorted together for some modules to operate.
This allows a module to use these pins during initial testing as two separate points. This
feature is used by Digital for manufacturing tests only. Spare pins are allocated on the
backplane as follows:
S SPARES - Four pins: AE1, AH1, BH1, AF1 (with the exception of AF1 in slot
1), are reserved for the particular use of a module or set of modules. They may be
used as test points or for intermodule connection. Appropriate wires must be added
for intermodule communication since these pins are not connected in any way. The
processor uses AF1 in slot 1 as an output pin for the SRUN signal. S SPARE lines
cannot be used as bus connections.
P SPARES - Two pins: AU1 and BU1, are similar to the S SPARE pins except that

they are located in a manner that causes dc voltages to appear on them if a module is
inserted backwards. Use of these pins is not recommended.

5-28

Extended LSI-11 Bus

5.8 System Configurations
LSI-II bus systems can be divided into two types. The first type comprises those systems
that use only one backplane; the second type comprises those systems that use multiple
backplanes. Two sets of configuration rules are necessary to accommodate the different
electrical characteristics of the two types of systems.
Three characteristics of each component in an LSI-II bus system must be known before
configuring any system.
•

Power consumption - The total amount of current drawn from the +5 Vdc and +12
Vdc power supplies by all modules in the system.

•

AC bus loading - The amount of capacitance a module presents to a bus signal line.
AC loading is expressed in ac unit loads, where one ac unit load equals 9.35 pF of
capacitance.

•

DC bus loading - The amount of dc leakage current a module presents to a bus
signal when the line is high (undriven). DC loading is expressed in terms of dc unit
loads, where one dc unit load equals 105 pA (nomina}).

Power consumption, ac loading, and dc loading specifications for each module are included
in the Microcomputer Interfaces Handbook.
NOTE

The ac and dc loads and the power consumption of the processor module,
terminator module, and backplane must be included in determining the total
bus loading of a backplane.

Extended LSI-11 Bus -5-29

5.8.1 Rules for Configuring Single-Backplane Systems
The following rules apply only to single-backplane systems. Any extension of the bus
off the backplane is considered a multiple-backplane system and must be configured
accordingly. Figure 5-14 shows a configuration diagram for a single-backplane.
1. The bus can accommodate modules that have up to 35 ac loads (total) before the

termination is required. The processor has on-board termination for one end of
the bus. If more than 20 ac loads are included, the other end of the bus must be
terminated.
2. A 120 n terminated bus can accommodate modules comprising up to 45 ac loads

(total).
3. The bus' can accommodate modules up to 20 dc loads (total).
4. The bus signalline~ on the backplane can be up to 35.6 cm (14 in) long.
5. It is recommended that the far end of the bus be terminated with 240 n .

One
Unit
Load

Optional

One
Unit
Load

3.4V
)

y
35 AC Loads

KDJ11-B
Processor

Backplane Wire
35.6 CM (14 IN) Maximum

20 DC Loads

WKhTenn
Term
W·00189-TIO

Figure 5-14

Single-Backplane Configuration

5.8.2 Rules for Configuring Multiple-Backplane Systems
Multiple-backplane systems can contain a maximum of three backplanes. Figure 5-15
shows a configuration diagram for a multiple-backplane system.
1. The signal lines on each backplane can be up to 25.4 cm (10 in) long.
2.

Each backplane can accommodate modules that have up to 20 ac loads (total).
Unused ac loads from one backplane may not be added to another backplane if the
second backplane loading will then exceed 20 ac loads. Loading backplanes equally is
recommended.

5-30

Extended LSI-11 Bus

3. The dc loading of all modules in all backplanes cannot exceed 30 loads (total).
Backplane Wire
35.6 eM (14 IN) Maximum
I

Cable

One
Unit
Load

3.4 V

One
Unit
Load

Y
20 AC Loads Max

KOJ11-B
Processor
Backplane Wire
25.4 CM (10 IN) Maximum

One
Unit
Load

2400
3AV

One
Unit
Load

y
20 AC Loads Max

2400
3,4A

)

LJ-002SD-TIO

Figure 5-15

Multiple-Backplane Configuration

4. The first backplane must have an impedance of 120 n (obtained via the processor
module). The second backplane is terminated by 240 n resistor networks contained
on the backplane.
5. The cables connecting the backplanes must observe the following conditions.
a. The cables connecting the two backplanes must be 61 cm (2 ft) or greater in
length.
b. The length of the cables must not exceed 4.88 m (16 ft).
c. The cables used must have a characteristic impedance of 120 n .

Extended LSI-11 Bus 5-31

5.8.3 Power Supply Loading
Total power requirements for each backplane can be determined by obtaining the
total power requirements for each module in the backplane. Obtain separate totals
for +5 V and +12 V power. Power requirements for each module are specified in the
Microcomputer Interfaces Handbook.
no not attempt to distribute power via the LSI-II bus cables in multiple-backplane
systems. Provide separate, appropriate power wiring from each power supply to each
backplane. Each power supply should be capable of asserting BPOK H and BneOK
H signals according to bus protocol. This is required if automatic power-fail/restart
programs are implemented or if specific peripherals require an orderly power-down
halt sequence. The proper use of the BPOK H and BneOK H signals is strongly
recommended.

6
Private Memory Interconnect Bus

6.1 Description'
The PMI bus provides a high performance communications path between the KDJII-E
CPU module and the KTJ11-B UBA The PMI bus consists of 14 signals that support
the PMI protocol and the additional LSI bus signals that are shared with the LSI bus
protocol. The address and data information is multiplexed using the same LSI bus data
laddress lines. The PMI protocol is designed for LSI systems and unique LSI-controlled
UNIBUS systems that use the UBA

6.2 PMllnterface
The PMI interface signals are defined as the PMI bus master signals, the PMI slave
signals, and the PMI UNIBUS adapter signals. These interface signals are assigned
to the C and D rows of the backplane and are defined as the interconnect bus. The
PMI interface signals on the C/D bus are normally assigned two pins to provide an
interconnection between the slots. The LSI bus signals that are used with the PMI
protocol use the A and B rows of the backplane defined as the LSI bus.

6.2.1 PMI Bus Master Signals
The PMI bus master controls the PMI bus cycles by using the nonmultiplexed control
signals described in Table 6-1. These signals are asserted low and negated high.

6.2.2 PMI Slave Signals
The PMI slave responds to the bus master by the nonmultiplexed signals listed in
Table 6-2. These signals are asserted low and negated high by any device that is capable
of being a slave.

6.2.3 PMI UNIBUS Adapter Signals
The UBA is used exclusively for UNIBUS systems. The PMI incorporates a special group
of signals to establish communications between the KDJ11-E and the UBA These signals
are nonmultiplexed as described in Table 6-3 and are not used in any LSI based system.

6-1

6-2 Private Memory Interconnect Bus

. 6.2.4 LSI Bus Sign~ls
The PMI protocol uses some of the standard LSI bus signals in conjunction with the PMI
high speed control signals. These LSI bus signals may not be used exactly as they are
used in an LSI bus operation. The LSI bus signals used with the PMI are listed with
their PMI functions in Table 6-4.
Table 6-1

PMI Bus Master Signals

Mnemonic

DC1

PBYTL

Function
PMI Byte PBYT L
is asserted or negated in conjunction with the BWTBT L LSI bus
signal to select the type of bus cycle as follows:

BWTBT L

PBYT L

Bus Cycle

DATI or DATBI

DATIP

DATO

L
PMI Bus Cycle

DATOB

CEl

PBCYCL

The PMI bus master starts a PMI cycle by asserting PBCYC L and
ends a PMI cycle by negating PBCYC L.
CP1

PBLKML

PMI Block Mode
1b read more than two words, the PMI bus master uses PBLKM
L and PBCYC L to control the timing of the DATBI cycle. Both
PBLKM L and PBCYC L are asserted at the start of the DATBI
cycle, and after reading two words PBLKM L is negated. If there
are more than two words that remain to be read, PBLKM L is
asserted and negated every time two words are read (except for the
last two words, where it remains negated). After reading the last
two words, PBCYC is also negated.

DB1

PWTSTBL

PMI Write Strobe
After the bus master gates the data onto the bus, PWTSTB is
asserted to latch the data into the write buffer of the PMI slave.

Table 6-2 PMI Slave Signals
Pin

Mnemonic

CB1

PSSELL

Function
PMI Slave Selected
Whenever a slave is addressed by the BDAL bus lines, it responds
by asserting PSSEL L. The UBA does not assert this signal.

CH1

PHBPARL

PMI High Byte Data Parity
This signal is generated by the selected PMI memory module during
DATI and DATBI cycles. It provides an odd parity bit for the high
data byte transmitted on BDAL <15:8>.

CK1

PLBPARL

PMI Low Byte Data Parity
This signal is generated by the selected PMI memory module during
DATI and DATBI cycles. It provides an even parity bit for the low
data byte transmitted on BDAL <7:0>.

Private Memory Interconnect Bus 6-3

Table 6-2 (Cont.) PMI Slave Signals

Mnemonic

Function

CMl

PRDSTBL

PMI Read Strobe
This signal is asserted and negated by the selected PMI memory
module to control data transfers during DATI and DATBI cycles.
The bus master uses the negating edge of PRDSTB L to latch the
first data word. The second data word is latched at a specified time
after PRDSTB L is negated.

CJl

PSBFULL

PMI Slave Buffer Full
The selected PMI slave asserts PSBFUL L during DATO and
DATBO cycles to indicate that its write buffer is full and,
consequently, it cannot respond to another cycle request. The bus
master may output another address while PSBFUL L is asserted,
but it must not assert PBCYC L until PSBFUL L is negated.

Table 6-3 PMI UNIBUS Adapter Signals

Mnemonic

Function

DDI

PMAPEL

PMI UNIBUS Map Enable
The KDJll-E asserts this signal when bit 5 of MMR3 is set. The
signal is negated when bit 5 is cleared or reset. The UBA enables
the UNmUS map when PMAPE L is asserted and disables the
UNmUS map when PMAPE L is negated. The memory modules do
not use this signal.

CFl

PUBSYSL

PMI UNIBUS System
In a UNIBUS system, PUBSYS L is asserted by the UBA to direct
the KDJll-E to follow PMI protocol for all data transfers, whether
PSSEL L is asserted or not. LSI-II bus protocol is disabledJor all
PMI devices when PUBSYS L is asserted.

In an LSI-II system, PUBSYS L is always negated. IfPSSEL L is
negated, the KDJII-E follows LSI-II protocol and the PMI memory
then responds to the LSI-II protocol by the LSI DMA devices.
CDI

PUBMEML

PMI UNIBUS Memory
The UBA asserts PUBMEM L to indicate that UNIBUS memory
space is being addressed. The signal is latched when PBCYC L is
asserted. When a PMI slave is addressed, it asserts PSSEL L, but
it must not respond to the PMI control signals if PUBMEM L is
asserted. The KDJII-E ignores the PSSEL L signal ifPUBMEM L
is asserted.

CVI

PUBTMOL

PM! UNIBUS Timeout
The UBA asserts PUBTMO L in response to any of the following
conditions:

•

When an NXM timeout occurs and the KDJII-E addresses the
UNmUS

•

When a SACK timeout occurs during an interrupt cycle

•

When a UNmUS interrupting device was granted bus
mastership, but fails to execute an interrupt transaction

6-4 Private Memory Interconnect Bus

Table 6-3 (Cont.) PMI UNIBUS Adapter Signals

Mnemonic

Function

CRI

PBSYL

PMIBusy
This signal is asserted by the PMI bus master (KDJII-E or UBA)
when it gains control of the PMI bus. The PMI bus master negates
this signal when it relinquishes PMI mastership.
The KDJII-E is the bus master at power-up and when the bus is
idle.

Table 6-4 LSI Bus Signals

Mnemonic

Function

AK2

BWTBTL

Write Byte (PMI Write Indication)
In a PMI system, BWTBT L is used in conjunction with PBYT L to
define the data transfer cycle. BWTBT L and PBYT L are asserted
for this purpose when the bus master gates the address onto the
BDAL lines.
BWTBT L
PBY'!' L
Bus Cycle

AF2

BRPLYL

DATI or DATBI

DATIP

DATO

DATOB

Reply
During PMI cycles, BRPLY L is asserted by the KDJII-E and the
PMI slave to prevent the next bus master from gaining control of
the bus too soon. In a UNIBUS system, BRPLY L is asserted by
the UBA as a slave response during the PMI DATOB cycle and
interrupt vector DATI cycle.

NOTE
The PM! memory slave modules in a UNIBUS system must have BRPLY L disabled at aU
times.
AH2

BDINL

Data Input
The BDIN L signal is only used in PMI UNffiUS systems during
interrupt grant cycles. The KDJII-E asserts BDIN L after it gates
the interrupt priority, BDAL bits <3:0>, onto the bus. The UBA
then latches the interrupt priority data using the leading edge of
BDIN L.

AM2
AN2

BIAKIL
BIAKOL

Interrupt Acknowledge In
Interrupt Acknowledge Out
These signals are only used in PMI UNffiUS systems during the
interrupt grant cycles. The KDJII-E asserts the BIAKI L signal
and the UBA acknowledges it by asserting one of the UNffiUS bus
grant signals.

Private Memory Interconnect Bus - 6-5

Table 6-4 (Cont.) LSI Bus Signals

Mnemonic

Function

BBl

BPOKH

Power OK
This signal is only used in PMI UNffiUS systems for the UNffiUS
power-uplpower-down protocol. This signal is asserted and negated
by the UBA in response to the UNffiUS AC LO signal. The
assertion of AC LO may be prolonged by the UNIBUS devices
or the PMI memory during power-up.

6.3 PMI Operation in an LSI-11 System
The KDJ11-E is the default bus master in an LSI-11 system. Any bus device that has
the appropriate circuits can become the bus master and can control data transfers over
the LSI-11 bus. The KDJ11-E relinquishes control of the bus by acknowledging a DMA
request from a DMA device which then becomes bus master. During the time that a
DMA device is bus master, there is no PMI master. The standard LSI-11 bus operations
are described in Chapter 5.
If the KDJ11-E receives a DMA request while performing a PMI cycle or while gating an
address onto the bus, it must also perform the following relationships:
1. If the KDJ11-E has gated an address onto the bus for a PMI cycle or an LSI bus cycle

and wants to abort the cycle, it removes the address and control signals from the bus
and asserts the BDMG L signal.
2. In a PMI data transfer cycle, the KDJ11-E asserts the BDMG L signal after it asserts
the BRPLY L signal.
3. In a PMI DATIP cycle, the KDJ11-E negates the BRPLY L signal before the PMI
slave removes the data from the bus.
4. In a PMI DATOB cycle, the KDJ11-E negates the BRPLY L signal before it removes
the data from the bus.
5. In a PMI DATOB cycle, the PMI slave negates the BRPLY L signal before it is ready
to receive the BSYNC L signal from a DMA device.
The KDJ11-E can regain bus mastership only after BSYNC Land BSACK L have been
negated by the DMA device.

6.4 PMI Operation in a UNIBUS System
In a UNIBUS system the KDJII-E CPU is the default PMI master and the KTJ11B UBA is the default UNIBUS master. When the CPU as the PMI master addresses
the 110 page, the UBA responds as a PMI slave while simultaneously controlling the
UNIBUS side of the transaction as the bus master.
The UBA can become .the PMI master when the CPU issues a DMA grant or performs
an interrupt transaction. The DMA or interrupt grant is accepted by the UBA and
passes the DMA or interrupt grant onto a UNIBUS device, which would then become the
UNIBUS master.
In UNIBUS systems, the bus master and PMI master can be requested by an NPR or
interrupt request from a bus device, or a DMA or interrupt request from the UBA

6-6 Private Memory Interconnect Bus

6.4.1 Bus Device NPR or DMA
Any UNIBUS device that is capable of being a UNIBUS master can issue an NPR or
DMA request to become bus master and control data transfers. When a UNIBUS device
becomes the bus master through an NPR or DMA request, it can perform UNIBUS
DATI, DATIP, DATO, and DATOB cycles. The UBA responds as a UNIBUS slave when
accessing PMI memory, the PMI 110 page, or a UBA 110 page location on behalf of a
UNIBUS master. During the same cycle, the UBA also acts as the PMI bus master to
control the PMI portion of the data transfer for accesses to PMI memory or the PMI 110
page.
The KDJII-E and the UBA use the following protocol to arbitrate an NPR:
1. The UBA asserts the DMA request (DMR) after receipt of a UNIBUS NPR or when it
is ready to transfer data to or from memory.
2. The KDJII-E bus arbitrator asserts the DMA grant (DMGO) after receiving the DMR
input and after the negation of BSACK by the UBA
3. The UBA enters the DMA cycle if it is the highest requesting priority or it asserts
the nonprocessor grant (NPG) to the UNIBUS after receiving the DMG from the
KDJII-E.
4. Since the UBA does not have the required priority it cannot be the next bus master.
Instead, it negates bus busy (BBSY) after the assertion of DMR and clears the
UNIBUS.
5. The device with the highest priority asserts selection acknowledge (SACK) to the
UBA and negates the NPR after the UBA asserts NPG.
6. This device is now master of the UNIBUS and asserts BBSY and SACK when the
previous bus master relinquishes the bus by negating BBSY. The new bus master
may then initiate data transfer cycles.
7. The UBA asserts BSACK to the KDJI1-E after receiving UNIBUS SACK or because
of a timeout occurring 10 JlS after it asserts NPG. If UNIBUS SACK is not received
within 10 JlS after the assertion of NPG, the UBA automatically asserts BSACK.
8. The UBA asserts transmitted PMI busy (PBSY) after it is negated by the PMI bus
master. The UBA is now the PMI bus master and can initiate PMI data transfer
cycles.
9. The KDJ11-E bus arbitrator negates DMGO after BSACK is asserted. Since the
UBA provides the timeout function, the KDJ11-E maintains DMGO until it receives
BSACK.
10. The UBA negates NPG after the KDJ11-E negates DMGO.
11. The device that is the current bus master negates SACK after it asserts BBSY and
receives the negation of NPG.
12. The UBA negates BSACK after the UNIBUS SACK is negated and after BBSY is
asserted. The KDJII-E bus arbitrator continues arbitration for 75 ns after BSACK is
negated.
13. The bus master negates BBSY after it has cleared the bus.
14. If the KDJ11-E is the next PMI bus master, the UBA or the current bus master clears
the bus. The PMI control data negates PBSY to relinquish control of the PMI bus.

Private Memory Interconnect Bus 6-7

6.4.2 PMI Bus Device Interrupt
Any UNIBUS device that is capable of being a bus master can issue a BR7 through BR4
request and become the bus master to control data or interrupt vector transfers. In both
cases, the UBA is the PMI master and responds as a slave if the device performs an
interrupt vector transaction or accesses the PMI memory, the PMI I/O page, or the UBA
I/O page. When a UNIBUS device becomes the bus master through an interrupt request,
it can perform the same UNIBUS data transfers described for the NPR.
The KDJ11-E and the UBA use the following protocol to arbitrate an interrupt request:
1. In response to a UNIBUS device, the UBA asserts an interrupt request on BIRQ
<7:4>~

2. The KDJ11-E bus arbitrator responds as follows:
a. Asserts interrupt level on BDAL <3:0>.
b. Asserts BDIN 150 ns after gating BDAL <3:0>.
c.

Asserts the interrupt acknowledge grant (BIAKO) 250 ns after asserting BDIN.

3. The UBA latches BDAL <3:0> when BDIN is asserted and asserts the UNIBUS
interrupt level BG <7 :4> after BIAKO is asserted.
4. Since the UBA does not have the highest priority, it negates BBSY after it asserts BG
<7:4> and clears the UNIBUS.
5. The UNIBUS device with the highest priority asserts select acknowledge (SACK)
after it receives BG <7:4> and negates its interrupt request.
6. The UBA asserts BSACK to the KDJ11-E after the device asserts SACK.
NOTE

The UBA asserts PUBTMO to indicate a timeout if SACK is not received within
10 JlS after the assertion ofBG <7:4>. The KDJII-E cancels the interrupt cycle
and becomes the PMI bus master by receiving PUBTMO.
7. The UBA asserts PBSY after it asserts BSACK and after the pr~vious PMI bus
master negates PBSY. The UBA now has control of the PMI and)may initiate PMI
data transfer or interrupt cycles after PBSY is asserted.
8. The UBA negates BG <7:4> after BSACK is asserted and negates BDGMO if BSACK
is not asserted within the 10 JIS timeout period.
9. The new UNIBUS master asserts BBSY after it asserts SACK and the previous bus
master negates BBSY.
10. The bus master negates SACK after the negation of BG <7:4> and after the assertion
ofBBSY.
11. The UBA negates BSACK to the KDJ11-E after the negation of SACK and the
assertion of PBSY.
12. The KDJ11-E resumes NPR arbitration for 75 ns after the negation of BSACK,
but does not resume BIRQ arbitration until the interrupt request is aborted by the
assertion of PUBTMO or the completion of the interrupt operation.
13. If a UNIBUS device responds to BG <7:4> with one or more DMA transfers, the UBA
responds as it would to a device that received bus mastership by an NPR request.
The assertion of BDIN and BIAKO by the KDJ11-E has no effect on the PMI protocol.

6-8

Private Memory Interconnect Bus

14. If the UNIBUS master relinquishes control without sending the interrupt vector, the
UBA asserts PUBTMO, indicating a timeout to the KDJ11-E, and the interrupt cycle
is aborted.
15. The UNIBUS master negates BBSY after it clears the UNIBUS.

6.5 PMI Data Transfers
There are three general categories of PMI data transfer cycles. They are the
DATIIDATIP, DATBI, and DATOIDATOB cycles. They are briefly described below.
On the Q22-bus, the bus master can perform a read-modify-write (DATIO or DATIOB)
cycle that transmits an address, reads a data word or byte, and then writes the data
word or byte to the same address. The PMI read-modify-write is performed by a DATIP
cycle followed by a DATO or DATOB cycle. The PMI bus master has the responsibility of
controlling the bus for the duration of both cycles.

6.5.1 PMI Data InlData In Pause
The DATI and the DATIP cycles are used to read one or two words when the PMI bus
master accesses the memory. The PMI bus master detects an I/O page reference by the
assertion of TBS7.
The PMI DATIP cycle is identical to the DATI cycle except that TPBYT is asserted with
TADDR to indicate that the cycle immediately following the current cycle will be a DATO
cycle to the same address. The protocol used by the DATI and DATIP cycles is as follows:
1. When the PMI master assumes control of the bus, the BDAL <21:0> lines are
addressed, BBS7 is asserted, and PBYT is asserted for DATIP cycles.
2. Each PMI slave asserts PSSEL within 45 ns after it receives the asserted BDAL
<21:0> and BBS7 signals, if necessary.
3. The UBA asserts PUBMEM within 100 ns after it receives the asserted BDAL <21:0>
and BBS7 signals, if necessary.
4. The PMI master receives PSSEL within 130 ns after gating the asserted BDAL
<21:0> and BBS7 signals.
5. The PMI master receives PUBMEM within 120 ns after gating the asserted BDAL
<21:0>. and BBS7 signals.
6. If PSSEL is asserted and PUBMEM is negated, the PMI master proceeds as follows.
a. The PMI master asserts PBCYC within 130 ns after gating the BDAL <21:0>,
BBS7, and PBYT signals and only after PSBFUL is negated.
b. The PMI master continues to assert the BDAL <21:0>, BBS7, and PBYT signals
for a minimum of 40 ns and a maximum of 100 ns after asserting PBCYC.
c. The UBA latches PUBMEM when PBCYC is asserted.
d. The PMI slave receives stable BDAL <21:0>, BBS7, and PBYT signals for 65 ns
(minimum) before PBCYC is asserted and for 30 ns after PBCYC is asserted.
e. The PMI slave receives a valid PUBMEM from 10 ns (minimum) before the
assertion of PBCYC and until 10 ns before PBCYC is negated.
7. If PSSEL is negated and the KDJ11-E is the PMI master, then PMI cycles are
performed with the UBA responding as a slave, and follow the routine listed in
steps 1 through 6.

Private Memory Interconnect Bus - 6-9

8. If PSSEL is negated and PUBMEM is asserted, the UBA is the PMI master and it
aborts the PMI cycle and does not respond as a UNIBUS slave.
9. The assertion of BRPLY by the PMI slave is optional in
as follows:

LB. systems. Its protocol is

a. The PMI slave asserts BRPLY after PBCYC is asserted.
b. The PMI slave negates BRPLY within 100 ns after the negation of PRDSTB.
10. The PMI slave gates the data onto the bus within 125 ns after the assertion of
PBCYC.
11. The PMI slave gates PHBPAR and PLBPAR parity bits after the assertion of PBCYC.
These parity bits are generated only for the memory locations being cached on the
KDJ11-E from the main memory.
12. The PMI slave asserts PRDSTB after the assertion of PBCYC.
13. The PMI slave negates PRDSTB within 150 ns after the assertion of PBCYC. It is
negated within 75 ns after the first data word is gated on the bus and 55 DS after the
PHBPAR and PLBPAR bits are gated for the first word.
14. The PMI slave maintains the data word, PHBPAR and PLBPAR for 30 DS after
negating PRDSTB.
15. The PMI master receives the first data word from 10 ns before PRDSTB is negated
and until 20 ns after PRDSTB is negated.
16. The PMI master receives PHBPAR and PLBPAR from 35 ns before PRDSTB is
negated and until 10 ns after PRDSTB is negated.
17. If the PMI master is executing a single word read, it negates PBCYC after PRDSTB
is negated and latches the data before PRDSTB is negated. The following process is
used only with double-word reads:
a. The PMI slave gates the second word data onto the bus after PRDSTB is negated.
b. The PMI slave gates the second word PHBPAR and PLBPAR bits onto the bus
within 100 ns after PRDSTB is negated.
c. The PMI master receives the second data word within 145 ns after PRDSTB is
negated.
d. The PMI master receives the second word PHBPAR and PLBPAR bits within 120
ns after PRDSTB is negated.
e. If the PMI master is reading two words, it negates PBCYC after latching the
second word.
f.

The PMI slave removes the second word data from the bus within 50 ns after
PBCYC is negated.

6.5.2 PM. Block Data In
The DATBI cycle is used to read up to 16 words of data when the PMI bus master
accesses the PMI memory. The PMI bus master cannot use the DATBI cycle when
accessing the 110 page. The PMI bus master detects an 110 page reference by the
assertion of TBS7.

6-10

Private Memory Interconnect Bus

The PMI bus master can only start DATBI transfers on even word boundaries. This
means that address bitS <1:0> must be equal to Os. The PMI bus master cannot use the
DATBI cycle to transfer across 16 word address boundaries. This means that the PMI
bus master must terminate DATBI data transfers when it reaches a memory location
where the address bits <4: 1> are all equal to 1s. The protocol used by the DATBI cycle is
as follows:
1. When the PMI master assumes control of the bus, the BDAL <21:0> lines are
addressed and BBS7 is asserted.

2. Each PMI slave asserts PSSEL within 45 ns after it receives the asserted BDAL
<21:0> and BBS7 signals, if necessary.
3. The UBA asserts PUBMEM within 100 ns after it receives the asserted BDAL <21:0>
and BBS7 signals, if necessary.
4. The PMI master receives PSSEL within 130 ns after gating the asserted BDAL
<21:0> and BBS7 signals.
5. The PMI master receives PUBMEM within 120 ns after gating the asserted BDAL
<21:0> and BBS7 signals.
6. If PSSEL is asserted and PUBMEM is negated, the PMI master proceeds as follows:
a. The PMI master asserts PBCYC within 130 ns after gating the BDAL <21:0>,
BBS7, BWTBT, and PBYT signals, and after PSBFUL is negated.
b. The PMI master continues to assert the BDAL <21:0>, BBS7, BWTBT and PBYT
signals for a minimum of 40 ns and a maximum of 100 ns after it asserts PBCYC.
c. The UBA latches PUBMEM when PBCYC is asserted.
d. The PMI slave receives stable BDAL <21:0>, BBS7, BWTBT and PBYT signals
for 65 ns (minimum) before PBCYC is asserted and for 30 ns after PBCYC is
asserted.
e. The PMI slave receives a valid PUBMEM from 10 ns (minimum) before the
assertion of PBCYC and until 10 ns before PBCYC is negated.
7. If PSSEL is negated and the KDJ11-E is the PMI master, the PMI cycles are
performed with the UBA responding as a slave, and follow the routine listed in
steps 1 through 6.
8. If PSSEL is negated and PUBMEM is asserted, the UBA is the PMI master and it
aborts the PMI cycle and does not respond as a UNIBUS slave.
9. The PMI master asserts PBLKM: within 50 ns after PBCYC is asserted.
10. The assertion of BRPLY by the PMI slave is optional in LSI systems. Its protocol is
as follows:
a. The PMI slave asserts BRPLY after PBCYC is asserted.
b. The PMI slave negates BRPLY within 100 ns after the negation of PRDSTB.
11. The PMI slave gates the data onto the bus within 125 ns after the assertion of
PBCYC.
12. The PMI slave gates PHBPAR and PLBPAR parity bits after the assertion of PBCYC.
These parity bits are generated only for the memory locations being cached on the
KDJ11-E from the main memory.
13. The PMI slave asserts PRDSTB after the assertion of PBCYC.

Private Memory Interconned Bus 6-11

14. The PMI slave negates PRDSTB within 150 ns after the assertion of PBCYC. It is
negated within 75 ns after the first data word is gated on the bus and 55 ns after the
PHBPAR and PLBPAR bits are gated for the first word.
15. The PMI slave maintains the data word, PHBPAR and PLBPAR for 30 ns after
negating PRDSTB.
16. The PMI master receives the first data word from 10 ns before PRDSTB is negated
and until 20 ns after PRDSTB is negated.
17. The PMI master receives PHBPAR and PLBPAR from 35 ns before PRDSTB is
negated and until 10 ns after PRDSTB is negated.
18. The PMI slave gates the second word data onto the bus within 80 ns after PRDSTB
is negated.
19. The PMI slave gates the second word PHBPAR and PLBPAR bits onto the bus within
100 ns after PRDSTB is negated.
20. The PMI master receives the second data word within 145 ns after PRDSTB is
negated.
21. The PMI master receives the second word PHBPAR and PLBPAR bits within 120 ns
after PRDSTB is negated.
22. If four or more data words are to be transmitted, the sequence proceeds as follows:
a. The bus master negates PBLKM within 240 ns after the negation of PRDSTB and
after latching the second word data.
b. The PMI slave removes the second word data when PBLKM is negated.
c. The PMI slave asserts PRDSTB after the negation of PBLKM.
d. The PMI master asserts PBLKM 40 to 70 ns after negating it.
e. Return to step 13.
If two more data words are to be transmitted, the sequence proceeds as follows:
a. The bus master negates PBLKM within 240 ns after the negation of PRDSTB and
after latching the second word data.
b. The PMI slave removes the second word data when PBLKM is negated.
c. The PMI slave asserts PRDSTB after the negation of PBLKM.
d. Return to step 13.
If the last data word is to be transmitted, the sequence proceeds as follows:
a. The bus master negates PBCYC after latching the last word data.
b. The PMI slave ren10ves the last word data from bus within 50 DS after PBCYC is
negated.

6.5.3 PM. Data Out/Data Out Byte
The DATO and DATOB cycles are used by the PMI bus master to transfer a single word
or byte to a PMI slave. The protocol used by the DATO and DATOB cycles is as follows:
1. When the PMI master assumes control of the bus, the BDAL <21:0> lines are
addressed, and BBS7 and BWTBT are asserted for DATO cycles. In addition, PBYT
is asserted for DATOB cycles.

6-12

Private Memory Interconnect Bus

2. Each PMI slave assertS PSSEL within 45 ns after it receives the asserted BDAL
<21:0> and BBS7 signals, if necessary.
3. The UBA asserts PUBMEM within 100 ns after it receives the asserted BDAL <21:0>
and BBS7 signals, if necessary.
.
4. The PMI master receives PSSEL within 130 ns after gating the asserted BDAL
<21:0> and BBS7 signals.
5. The PM! master receives PUBMEM within 120 ns after gating the asserted BDAL
<21:0> and BBS7 signals.
6. If PSSEL is asserted and PUBMEM is negated, the PMI master proceeds as follows:
a. The PMI master asserts PBCYC within 130 ns after gating the BDAL <21:0>,
BBS7, BWTBT, and PBYT signals, and after PSBFUL is negated.
b. The PMI master continues to assert the BDAL <21:0>, BBS7, BWTBT, and PBYT
signals for a minimum of 40 ns and a maximum of 100 ns after it asserts PBCYC.
c. The UBA latches PUBMEM when PBCYC is asserted.
d. The PMI slave receives stable BDAL <21:0>, BBS7, BWTBT, and PBYT signals
for 65 ns (minimum) before PBCYC is asserted and for 30 ns after PBCYC is
asserted.
e. The PMI slave receives a valid PUBMEM from 10 ns (minimum) before the
assertion of PBCYC and until 10 ns before PBCYC is negated.
7. If PSSEL is negated and the KDJ11-E is the PMI master, the PMI cycles are
performed with the UBA responding as a slave, and follow the routine listed in
steps 1 through 6.
B. If PSSEL is negated and PUBMEM is asserted, the UBA is the PMI master and it

aborts the PMI cycle and does not respond as a UNIBUS slave.
9. The PMI slave asserts BRPLY within 50 ns after the assertion of PBCYC (LSI bus
systems only).
10. The PMI master gates the data onto the bus within BO ns after the assertion of
PBCYC.
11. The PMI master asserts PWTSTB within 75 ns after the data is placed on the bus.
12. The PMI maintains the data on the bus for 30 ns after it asserts PWTSTB.
13. The PMI slave receives the data from within 10 ns before the assertion of PWTSTB
and until 20 ns after the assertion of PWTSTB.
14. The PMI slave asserts PSBFUL within 50 ns after the assertion of PWTSTB.
15. The PMI master negates PWTSTB 40 ns' after asserting it.
16. The PMI master negates PBCYC after negating PWTSTB.
17. The PMI slave negates BRPLY within 300 ns (LSI systems) and cannot perform
another PMI or LSI bus cycle during this period.

Private Memory Interconnect Bus -6-13

6.6 PMllnterrupt Protocol
The PMI interrupt protocol consists of the interrupt request, granting the interrupt
and fetching the interrupt vector to service the interrupt. The LSI requirements for an
interrupt are defined in Chapter 5. The UNIBUS requirements for the request and grant
are described in Section 6.4.2. The transfer of the interrupt vector from the requesting
UNIBUS device to the KDJ11-E requires a combination of the UNIBUS and LSI bus
protocols as follows:
1. Once the requesting device is the bus master, it places the interrupt vector on the
UNIBUS after it asserts BBSY.
2. The requesting device asserts INTR after the vector data is on the UNIBUS.
3. The UBA is the PMI bus master and asserts BRPLY after it receives INTR on the
UNIBUS.
4. The UBA receives the interrupt vector and places it on the BDAL data lines within
75 ns after BRPLY is asserted.
5. The UBA latches the interrupt vector within 75 os after INTR is asserted and then
asserts SSYN on the UNIBUS.
6. The requesting device is the bus master and it removes the vector after it receives
SSYN. It also negates INTR at this time.
7. The requesting device negates BBSY after negating INTR to relinquish bus
mastership.
8. The KDJ11-E latches the vector data within 200 os after the UBA-asserted BRPLY.
9. The KDJ11-E negates BDIN and BIAKO after it latches the vector data.
10. The UBA negates BRPLY after BIAKO is negated.

6.7 PMI Power-Up/Power-Down
The power-up/power-down protocol for the PMI bus in an LSI system is described in
Chapter 5. The protocol used in a UNIBUS system is similar to that of the LSI system.
The primary difference is that in an LSI system, the BPOK signal is negated by the
power supply 3 ms after it is asserted, and in the UNIBUS system, the KDJ11-E must
ignore the assertion of AC LO for a minimum of 2 ms after it is asserted. These delays
allow the system software enough time to prepare for a power-down before the KDJ11-E
can execute the power-down sequence.
In the UNIBUS system, the KDJ11-E receives DC LO as the DCOK signal, and the
BPOK signal is isolated from AC LO by the UBA When a UNIBUS device asserts AC
LO to the UBA, it asserts BPOK for a minimum of 2 ms before it allows AC LO to negate
BPOK.

7
Addressing Modes

7.1

Introduction

The KDJ11-E uses the six addressing modes described here with the base instruction set
to control or program the operations executed by the microprocessor. Included in this
chapter are specific examples of how these addressing modes are used.
•

Single-Operand Addressing - One part of the instruction word specifies the registers;
the other part provides information for locating the operand.

•

Double-Operand Addressing - One part of the instruction word specifies the registers;
the remaining parts provide information for locating two operands.

•

Direct Addressing - The operand is the content of the selected register.

•

Deferred (Indirect) Addressing - The contents of the selected register is the address of
the operand.

•

Use of the Program Counter (PC) as a general purpose register - The PC is different
from other general purpose registers in one important respect. Whenever the
processor retrieves an instruction, it automatically advances the PC by two. By
combining this automatic advancement of the PC with four of the basic addressing
modes, the four special PC modes:immediate, absolute, relative, and relative-deferred,
are created.

•

Use of the general purpose registers as a stack pointer (SP) - General purpose
registers can be used for stack operations.

7.2 Addressing Modes
Data stored in memory must be accessed and manipulated. Data handling is specified by
a KDJ11-E instruction (MOV, ADD, and so on), and usually includes the following:
•

The function to be performed (operation code)

•

The general purpose register to be used when locating the source operand, or
destination operand (where required), or both.

•

The addressing mode, which specifies how the selected registers are to be used

A large portion of the data handled by a computer is structured (character strings, arrays,
lists, etc.) The KDJ11-E addressing modes provide for efficient and flexible handling of
structured data.
A general purpose register may be used with an instruction in any of the following ways:
1. As an accumulator - The data to be manipulated resides in the register.

7-1

7-2 Addressing Modes

2. As a pointer - The contents of the register is the address of an operand, rather than
the operand itself.
3. As a pointer that automatically steps through memory location~ - Automatically
stepping forward through consecutive locations is known as autoincrement
addressing; automatically stepping backward is known as autodecrement addressing.
These modes are particularly useful for processing tabular or array data.
4. As an index register - In this instance, the contents of the register and the word

following the instruction are summed to produce the address of the operand. This
allows easy access to variable entries in a list.
An important KDJII-E feature that should be considered with the addressing modes is
the following register arrangement:
•

Two sets of six general purpose registers (RO - R5 and RO'- R5')

•

A hardware SP register' (R6) for each processor mode (kernel, supervisor, user)

•

A PC register (R7)

Registers RO - R5 and RO'- R5' are not dedicated to any specific function. Their uses are
determined by decoded instructions and include the following:
•

They can be used for operand storage. For example, the contents of two registers can
be added and stored in another register.

•

They can contain the address of an operand or serve as pointers to the address of an
operand.

•

They can be used for the autoincrement or autodecrement features.

•

They can be used as index registers for convenient data and program access.

KDJII-E also has instruction addressing mode combinations that facilitate temporary
data storage structures. These can be used for convenient handling of data that must be
accessed frequently. This is known as stack manipulation. The register that keeps track
of stack manipulation is called the stack pointer (SP). Any register can be used as an SP
under program control. However, certain instructions associated with subroutine linkage
and interrupt service automatically use R6 as a hardware stack pointer. For this reason,
R6 is frequently referred to as the SP. The SP functions include the following:
•

The SP keeps track of the latest entry on the stack.

•

The SP moves down as items are added to the stack and moves up as items are
removed. Therefore, the SP always points to the top of the stack.

•

The hardware stack is used during trap or interrupt handling to store information,
allowing an orderly retum to the interrupted program.

R7 is used by the processor as its PC. It is recommended that R7 not be used as an SP or
accumulator. Whenever an instruction is fetched from memory, the PC is automatically
incremented by two to point to the next instruction word.

7.2.1 Single-Operand Addressing
The instruction format for all single-operand instructions (such as CLR, INC, TST) is
shown in Figure 7-1. Bits <15:6> specify the operation code that defines the type of
instruction to be executed. Bits <5:0> form a 6-bit field called the destination address
field. The destination address field consists of two subfields, as follows:

Addressing Modes - 7-3

•

Bits <5:3> specify the destination mode. Bit 3 is set to indicate (indirect) deferred
addressing.

•

Bits <2:0> specify which of the eight general purpose regis~rs is to be referenced by
this instruction word.
15

I : : : : : : : : : I :Mode: I :R'; I
\

OP Code

Destination Address
MA-1152-90.DG

Figure 7-1

Single-Operand Addressing

7.2.2 Double-Operand Addressing
Operations that employ two operands (such as ADD, SUB, MOV, and CMP) are handled
by instructions that specify two addresses. The first operand is called the source
operand; the second is called the destination operand. Bit assignments in the source and
destination address fields may specify different modes and different registers. Figure 7-2
shows the instruction format for the double-operand instruction .
The source address field is used to select the source operand (the first operand). The
destination is used similarly, and locates the second operand and the result. For example;
the instruction ADD A, B adds the contents (source operand) of location A to the contents
(destination operand) of location B. After execution, B contains the result of the addition
and the contents of A is unchanged.
Examples throughout this chapter use the sample KDJ11-E instructions given in
Table 7-1. (A complete list of KDJ11-E instructions appears in Chapter 8 Table 8-1.
15

I :OP ~Od< I :Mode: I :Rn : I :Mode: I >.: I
\

Y
Source Address

)

Y
Destination Address

MA-1153-90.DG

Figure 7-2

Double-Operand Addressing

Table 7-1

Sample KDJ11·E Instructions

Mnemonic

Description

Octal Code!

CLR

Clear - Zero the specified destination.

0050DD

CLRB

Clear byte - Zero the byte in the specified
destination.

l050DD

1 DD = Destination field (six bits)
SS = Source field (six bits)

7-4 Addressing Modes

Table 7-1 (Cont.) Sample KDJ11·E Instructions
Mnemonic

Description

Octal Codel

INC

Increment - Add one to the contents of the
destination.

0052DD

INCB

Increment byte - Add one to the contents
of the destination byte.

l052DD

COM

Complement - Replace the contents of
the destination by its logical complement;
each 0 bit is set and each 1 bit is cleared.

0051DD

COMB

Complement byte - Replace the contents
of the destination byte by its logical
complement; each 0 bit is set and each 1
bit is cleared.

l051DD

ADD

Add - Add the source operand to the
destination operand and store the result
at the destination address.

06SSDD

Inn = Destination field (six bits)
SS = Source field (six bits)
7.2.3 Direct Addressing
There are four basic modes used with· direct addressing:
•

•

Autoincrement mode (mode 2)

•

Autodecrement mode (mode 4)

•

Index mode (mode 6)

These direct modes are illustrated in Figure 7-3 through Figure 7-6, and are
summarized in the following paragraphs.
Assembler
Mode

Name

Syntas

Fu.notion

~_In_s_tr_ua_io_n__~--~~~~I

___o_~__~_nd__~
MA·1164·8Q

Figure 7-3

Mode 0, Register

Mode

Name

Syntax

Function

Autoincrement

(Rn+)

Assembler

Addressing Modes 7-5

Instruction

••

Address

"'1

1
I

Operand

"'1

+2 for Word
+1 for Byte

I---

MA·1155·90

Figure 7-4

Mode 2, Autolncrement

Mode

Name

Assembler
Syntax

Autodecrement

-(Rn)

Function
Register is decremented and then used as a
pointer

+2 for Word
+1 for Byte

Instruction

Operand

MA-1156·go

Figure 7-5

Mode 4, Autodecrement

Mode

Name

Assembler
Syntax

Function

Index

X(Rn)

Value X is added to (Rn) to produce address of
operand. Neither X nor (Rn) is modified

Instruction

Address

Operand

x
MA·1157·90

Figure 7-6

Mode 6, Index

7.2.3.1 Register Mode
With register mode (mode 0) any of the general registers may be used as simple
accumulators with the operand contained in the selected register. Since they are
hardware registers (within the processor), the general registers operate at high speeds
and provide speed advantages when used for operating on frequently accessed variables.
The assembler interprets and assembles instructions of the form OPR Rn as register
mode operations. Rn represents a general register name or number and OPR is used to

7-6 Addressing Modes

represent a general instruction mnemonic. Assembler syntax requires a general register
be defined as follows:

RO %0 (% sign indicates register definition)
RI=%1
R2 = %2, and so on.
Registers are typically referred to by names as RO, RI, R2, Ra, R4, R5, R6 and R7.
However, R6 and R7 are also referred to as SP and PC, respectively. Three register mode
operations are illustrated in Figure 7-7 through Figure 7-9.

Symbolic

Code

Instruction Name

INCR3

005203

Increment

Operation: Add one to the contents of R3.
15

Select

1«°:<,:0;<°>;01':°1°1< ;'~"ag~
~~

____________~____________A~______~_______J

OP code (INC(0052»

I
I
I
I

Destination Field

RO
R1
R2
R3

R4
RS
RS (SP)
R7(PC)
MA-11I1-tO.DO

Figure 7-7

INC R3

SymboUc

Octal
Code

m8traction Name

ADDR2,R4

060204

Add

Operation: Add the contents of R2 to the contents of R4.

Addressing Modes - 7-7

Before

After

R21

000002

R41

000004

000006
MA-1159-90.DG

Figure 7-8

ADD R2,R4

Symbolic

Octal
Code

Instruction Name

COMBR4

105104

Complement byte

Operation: 1's complement <7:0>(byte) in R4. When general registers are used, byte
instructions (with the exception of MOVB) operate only on bits <7:0>, that is, byte 0
of the register. MOVB to a register, unique for byte instructions, extends the most
significant bit of the low-order byte (sign-extension) into the high byte of the selected
register. Otherwise, MOVB operates on bytes the same way MOV operates on words.
Before

R41

022222

After

R41

022155
MA-1160-90.DG

Figure 7-9

COMB R4

7.2.3.2 Autolncrement Mode [OPR (Rn)+]
The autoincrement mode (mode 2) provides for automatic stepping of a pointer through
sequential elements of a table of operands. It assumes that the contents of the selected
general purpose register is the address of the operand. Contents of registers are stepped
(by one for byte instructions, by two for word instructions, always two for R6 and R7)
to address the next sequential location. The autoincrement mode is especially useful for
array processing and stack processing. It accesses an element of a table and then steps
the pointer to address the next operand in the table. Although autoincrement mode is
most useful for table handling, it is completely general and may be used for a variety of
purposes. Three autoincrement mode operations are illustrated in Figure 7-10 through
Figure 7-12.

Autoincrement Mode Examples:

Symbolic

Octal
Code

Instruction Name

CLR (R5)+

005025

Clear

Operation: Use the contents R5 as the address of the operand. Clear the selected
operand and then increment the contents of R5 by two.

7-8 Addressing Modes

. Before

After

Address Space

20000

005025

Address Space

20000

005025

030002

Operation: Use the contents R5 as the address of the operand. Clear the selected byte
operand and then increment the contents of R5 by one.
After

Before
Address Space

Address Space

20000

105025

20000

105025

30000 1111

030001

! 000 I
MA-1182-90.DG

Figure 7-11

CLRB (R5)+

Symbolic

Octal
Code

Instruction Name

ADD (R2)+,R4

062204

Add

Operation: The contents of R2 is used as the address of the operand, which is added to
the contents of R4. R2 is then incremented by two.

Addressing Modes 7-9

After

Before
Address Space

Address Space

10000

062204

R41

1000021

10000

062204

010000

1000021

R21

100004

R41

020000

010000
MA·1163·90.DG

Figure 7-12

ADD(R2)+,R4

7.2.3.3 Autodecrement Mode [OPR -(Rn)]

The autodecrement mode (mode 4) is useful for processing data in a list in reverse
direction. The contents of the selected general purpose register is decremented (by one
for byte instructions, by two for word instructions) and then used as the address of the
operand. The postincrement and predecrement features on the KDJ11-E are intended
to facilitate hardware/software operations. Three autodecrement mode operations are
-illustrated in Figure 7-13 through Figure 7-15.

Autodecrement Mode Examples:

Symbolic

Octal
Code

Instruction Name

INC -(RO)

005240

Increment

Operation: The contents of RO is decremented by two and used as the address of the
operand. The operand is incremented by one.
After

Before
Address Space

1000 I

005240

1n74 1

000000

Address Space

ROI

100002

1000

005240

17774

000001

MA·1164·90.DG

Figure 7-13

INC -(RG)

7-10 Addressing Modes

Symbolic

Octal
Code

Instruction Name

!NCB -(RO)

105240

Increment byte

Operation: The contents of RO is decremented by one and then used as the address of
the operand. The ope~d byte is increased by one.
After

Before
Address Space

1000

105240

017776

1000

17774~

17774

17776

CL:J

Address Space

105240

001

I 000
MA·1185·90.DG

Figura 7-14

INCB -(RO)

Symbolic

Octal
Code

Instruction Name

ADD --(R3),RO

064300

Add

Operation: The contents of R3 is decremented by two and then used as a pointer to an
operand (source), which is added to the contents of RO (destination operand).
After

Before
Address Space
10020

064300

Address Space

ROI

000020

R31

Onn6

10020

064300

0000070

77774~

7n74~.
050

7n76

n776

c===l

c===l
MA·1186·90.0G

Figure 7-15

ADD -(R3),RO

Addressing Modes -7-11

7.2.3.4 Index Mode [OPR X(Rn)]

In the index mode (mode 6), the contents of the selected general purpose register and
an index word following the instruction word are summed to form the address of the
operand. The contents of the selected register maybe used as a base for calculating a
series of addresses, thus allowing random access to elements of data structures. The
selected register can then be modified by a program to access data in the table. Index
addressing instructions are of the form OPR X(Rn), where X is the indexed word located
in the memory location following the instruction word, and Rn is the selected general
purpose register. Three index mode operations are illustrated in Figure 7-16 through
Figure 7-18.

Index Mode Examples:

Symbolic

Octal
Code

Instruction Name

CLR 200(R4)

005064
000200

Clear

Operation: The address of the operand is determined by adding 200 to the contents of
R4. The operand location is then cleared.
After

Before
Address Space
1020

005064

1022

Address Space

R41 001000

000200

1020

005064

1022

000200

001000

t-------f

1024

1000

1024

+200
1200
1200

177777

'B"

1202

MA-1167-90.DG

Figure 7-16

ClR 200(R4)

Symbolic

Octal
Code

COMB 200(R1)

105161
000200

Instruction Name
Complement byte

Operation: The contents of a location, determined by adding 200 to R1, is replaced by
its logical 1's complement. Each 0 bit is set and each 1 bit is cleared.

7-12 Addressing Modes

After

Before
Address Space

1020

105161

017777

1022

000200

R11

Address Space

017777
+200
020177
20176

000

20200

1020

105161

1022

000200

017777

20176ffi

20200

MA·1188-90.DG

Figure 7-17

COMB 200(R1)
Octal

SymboHc

Code

IDstruction Name

ADD 80(R2),20(R5)

066265
000080
000020

Add

Operation: The contents of a location determined by adding 30 to the contents of R2 is
added to the contents of a location determined by adding 20 to the contents of R5. The
result is stored at the destination address, that is 20(R5).
After

Before
Address Space
1020

066265

1022

000030

1024

000020

1130

·2020

I
I

Address Space

1020

066265

1022

000030

1024

000020

000001

1130

000001

2020

000002

1100
+30
1130

001100

002000

2000
+20
2020
MA·1169·90.DG

Figure 7-18

ADD 3O(R2),20(R5)

Addressing Modes 7-13

7.2.4 Deferred (Indirect) Addressing
The four basic modes may also be used with deferred addressing. While in register mode
the operand is the contents of the selected register; in register-deferred mode the contents
of the selected register is the address of the operand.
In the other three deferred modes, the contents of the register selects the address of the
operand rather than the operand itself. These modes are therefore used when a table
consists of addresses rather than operands. The assembler syntax for indicating deferred
addressing is an at sign (@), or parentheses ().
The following section summarizes the deferred versions of the basic modes. These
deferred modes are illustrated in Figure 7-19 through Figure 7-22.

Mode

Name

Registerdeferred

Assembler
Syntax
@Rn or (Rn)

Instruction

1-1--i~~1

Function
Register contains the address of the
operand

I-----I~...

Operand
MA-1170-90.DG

Figure 7-19

Mode 1, Register-Deferred

mode

Name

Autoincrementdeferred

Assembler
Syntax
@(Rn)+

Function
Register is used as a pointer to a word
containing the address of the operand, and
then is incremented (always by two, even
for byte instructions)

MA-1171-90.DG

Figure 7-20

Mode 3, Autolncrement·Deferrec:l

7-14 Addressing Modes

Mode

Name

AutodecrementdefetTed

Assembler
Syntax
@-(Rn)

Function
Register is decremented (always by two,
even for byte instructions) and then used
as a pointer to a word containing the
address of the operand.

MA·1172·90.DG

Figure 7-21

Mode 5. Autodecrement-Deferred

Mode

Name

Assembler
Syntax

Index-deferred

@X(Rn)

Instruction

Function
Value X (stored in a word following the
instruction) and (Rn) are added. The sum
is used as a pointer to a word containing
the address of the operand. Neither X nor
(Rn) is modified.

Address

Operand

x
MA-1173-90

Figure 7-22

Mode 7. Index-Deferred

The following examples shows in Figure 7-23 through Figure 7-26, further illustrate use
of the deferred modes.

Symbolic

Octal
Code

Instruction

CLR@R5

005015

Clear

Operation: The contents of a location specified in R5 is cleared.

Addressing Modes -7-15

After

Before
Address Space

1676[=:=J

1700~

Address Space

001700

1676 [ = : = J

Rsl

001700

1700~
MA-1174-90.0G

Figure 7-23

CLR @R5

Autoincrement-Deferred Mode Example:

Symbolic

Octal
Code

Instruction Name

INC @(R2)+

005232

Increment

Operation: The contents of R2 is used as the address of the operand. The operand is
increased by one; the contents of R2 is incremented by two.
After

Before
Address Space

Address Space

R21

1010g

1012

010302

MA-1175-90.0G

Figure 7-24

INC @(R2)+

Autodecrement-Deferred Mode Example:

Symbolic

Octal
Code

Instruction Name

COM @-(RO)

005150

Complement

Operation: The contents of RO is decremented by two and then used as the address
of the address of the operand. The operand is 1's complemented, that is, logically
complemented.

7-16 Addressing Modes

After

Before
Address Space
10100
10102

~.345

c==J

Address Space

010776

10100~
10102

c==J

10774~

10776

c==J

c==J
MA·1178·90.DG

Figure 7-25

COM @-(RO)

Index-Deferred Mode Example:
Octal
Code

SymboUc
ADD @10000(R2),R1

Instruction Name

067201
001000

Add

Operation: Location 1000 and the contents of R2 are summed to produce the address of
the address of the source operand, the contents of which are added to the contents of Rl.
The result is stored in Rl.
After

Before
Address Space
1020

067201

1022

001000

1024

Address Space

1020

067201

001236

1022

001000

R21

001234

000100

1024

000100

1~~
"
1100

ll00t=j

001050
1000
+100
1100

MA·1177·90.DG

Figure 7-26

ADD @1000(R2),R1

Addressing Modes 7-17

7.2.5 Use of the. PC as a General Purpose Register
Although R7 is a general purpose register, it doubles in function as the PC for the
KDJ11-E. Whenever the processor uses the PC to acquire a word from memory, the
PC is automatically incremented by two to point to the address of the next word of the
instruction being executed or the' address of the next instruction· to be executed. (When
the program uses the PC to locate byte data, the PC is incremented by two.)
The PC responds to all the standard KDJ11-E addressing modes. However, with four
of these modes the PC can provide advantages for handling Position-Independent Code
(PIC) and unstructured data. When utilizing the PC, these modes are termed immediate,
absolute (or immediate-deferred), relative, and relative-deferred. They are summarized
in the following chart.

Mode

Name

Assembler
Syntax

Function

Immediate

Operand follows instruction

Absolute

@#A

Absolute address of the operand follows instruction

Relative

Relative address (index value) follows the
instruction

Relativedeferred

Index value (stored in the word after the instruction)
is the relative address for the address of the operand

When a standard program is available for different users, it is often helpful to be able
to load it into different areas of memory and run it in those areas. The KDJ11-E can
accomplish the relocation of a program very efficiently through the the use of the PIC,
which is written by using the PC addressing modes. If an instruction and its operands
are moved in such a way that the relative distance between them is not altered, the
same offset relative to the PC can be used in all positions in memory. Thus, PIC usually
references locations relative to the current location.
The PC also greatly facilitates the handling of unstructured data. This is particularly
true of the immediate and relative modes.
.
7.2.5.1 Immediate Mode [OPR#n,DD]

With the PC, immediate mode (mode 2) is equivalent in use to the autoincrement
mode. It provides speed improvements for accessing constant operands by including the
constant in the memory location immediately following the instruction word. Figure 7-27
illustrates an immediate mode operation.

Immediate Mode Example:

Symbolic

ADD#10,RO

Octal
Code

062700
000010

Instruction Name

ADD

Operation: The value 10 is located in the second word of the instruction and is added
to the contents of RO. Just before this instruction is fetched and executed, the PC points
to the first word of the instruction. The processor fetches the first word and increments
the PC by two. The source operand mode is 27 (autoincrement the PC). Thus, the PC is
used as a pointer to fetch the operand (the second word of the instruction) before it is
incremented by two to the next instruction.

7-18 Addressing Modes

After

Before
Address Space

1020

062700

1022

000010

Address Space

000020

1024

1020

062700

1022

000010

000030

1024
PC
MA-1178-90.DG

Figure 7-27

ADD #10,RO

7.2.5.2 Absolute Mode [OPR @tAl
Using the PC, the absolute mode (mode 3) is the equivalent of the immediate-deferred or
autoincrement-deferred modes. The contents of the location following the instruction are
taken as the address of the operand. Immediate data is interpreted as an absolute
address, that is an address that remains constant no matter where in memory the
assembled instruction occurs. Figure 7-28 and Figure 7-29 illustrate two absolute mode
operations.

Absolute Mode Eumples:
Octal

SymlboHc

Code

Instruction Name

CLR @'1100

005037
001100

Clear

Operation: Clear the contents of location 1100.
Before

After

Address Space

005037

001100

005037

001100

1100~

1102 c = J

.1102c=J

MA-1179-90.DG

Figure 7-28

CLR @t1100

Addressing Modes -7-19

Octal
Code

Symbolic

Add @#2000,Ra

Instruction Name

063703
002000

Add

Operation: Add the contents of location 2000 to Ra.
After

Before
Address Space
063703

Address Space

000500

063703

002000

1
22

002000

000030

001000

2000Ej
MA-1180-90.DG

Figure 7-29

ADD @#2000

7.2.5.3 Relative Addressing Mode [OPR A or OPR X(PC)]

Using R7, the relative addressing mode (mode 6) is assembled as index mode. The
base of the address calculation, which is stored in the second or third word of the
instruction, is not the address of the operand, but the number which, when added to
the PC, becomes the address of the operand. This mode is useful for writing PIC since
the location referenced is always fixed relative to the PC. When instruction OPR X(PC) is
interpreted, ''X is the location of A relative to the PC". Figure 7-30 illustrates a relative
mode operation.

Relative Addressing Mode Example:

Symbolic

Octal
Code

Instruction

INCA

005267
000054

Increment

Operation: To increment location A, the contents of the memory location immediately
following the instruction word is added to the PC to produce address A The contents of A
is increased by one.

7-20

Addressing Modes

Before

After

Address Space

1020

005267

1022

000054

1020

~ PC 1022

1024

1026

1100

000000

005267

1024

t - - - - - - 1 1~
00

1100

000054

~ PC

000001

L..._

MA·1181·90

Figure 7-30

INC A

7.2.5.4 Relative-Deferred Addressing Mode [OPR @A or OPR @X(PC)]

The relative-deferred addressing mode (mode 7) is similar to relative mode, except that
the second word of the instruction, when added to the PC, contains the address of the
address of the operand, rather than the address of the operand. The instruction OPR
@X(PC) is interpreted as I'X is the location containing the address of A, relative to the
PC." Figure 7-31 illustrates a relative-deferred mode operation.

Relative-Deferred Addressing Mode Example:
Octal

SymboHc

Code

Instruction Name

CLR@A

005077
000020

Clear

Operation: Add second word of instruction to the updated PC to produce the address of
the address of the operand. Clear the operand.

Addressing Modes 7-21

Before

After

Address Space

(PC=1020) 1020

005077

1022

000020

1024

1024
+20
1044

1020

005077

1022

000020

1024
PC

010100

1044

10100

100001

10100

000000
MA·1182·90.DG

Figure 7-31

CLR @A

7.2.6 Use of the General Purpose Registers as a Stack Pointer
The processor SP (R6) is, in most cases, the general purpose register used for the stack
operations related to program nesting. Autodecrement using R6 "pushes" data onto the
stack, and autoincrementing using R6 "pops" data off the stack. Since the SP is used
by the processor for interrupt handling, it has a special attribute: Autoincrements and
autodecrements are always done in steps of two. Byte operations using the SP in this
way leave odd addresses (upper bytes) unmodified.

8
Base Instruction Set

8.1 Instruction 'Set
This chapter describes the KDJ11-E base instruction set. The chapter includes an
explanation of each instruction mnemonic, octal code, binary code, a diagram showing
the format of the instruction, a symbolic notation describing its execution and effect on
the condition codes, a description, special comments, and examples. Each explanation
is headed by its mnemonic. When the word instruction has a byte equivalent, the byte
mnemonic also appears.
The instruction set is listed by functional groups in Section 8.4, and an alphabetical list
is provided in Table B-1.
Table 8-1

Instruction Set

Mnemonic

Instruction

Op Code

ADC(B)

Add carry

ADD

Add source to destination

ASH

Arithmetic shift

~55DD
06SSDD
072RSS

ASHC

Arithmetic shift combined

073RSS

ASL(B)

Arithmetic shift left

~63DD

ASR(B)

Arithmetic shift right

~62DD

BCC

Branch if carry is clear

103000

BCS

Branch if carry is set

103400

BEQ

Branch if equal (to zero)

001400

BGE

Branch if greater than or equal (to zero)

002000

BGT

Branch if greater than (zero)

003000

BHI

Branch if higher

101000

BHIS

Branch if higher or same

103000

BIC(B)

Bit clear

~SSDD

BIS(B)

Bit set

~SSDD

BIT(B)

Bit test

BLE

Branch if less than or equal (to zero)

~SSDD
003400

8-1

8-2

Base Instruction Set

Table 8-1 (Cont.) Instruction Set
Mnemonic

Instruction

Op Code

BLO

Branch if lower

103400

BLOB

Branch if lower or same

103400

BLT

Branch if less than (zero)

101400

BMI

Branch if minus

100400

BNE

Branch if not equal (to zero)

001000

BPL

Branch if plus

100000

BPT

Breakpoint trap

000003

Branch (unconditional)

000400

BVC

Branch if overflow is clear

102000

BV8

Branch if overflow is set

102400

CCC

Clear all CC bits

000257

CLC

Clear C

000241

CLN

Clear N

000250

CLR(B)

Clear destination

~50DD

CLV

Clear V

000242

CLZ

Clear Z

000244

CMP(B)

Compare source to destination

~SSDD

COM(B)

Complement destination

~51DD

C8M

Call to supervisor mode

0070DD

DEC(B)

Decrement destination

DIV

Divide

~53DD
071RSS

EMT

Emulator trap

104000-104377

HALT

Halt

000000

lOT

InputJoutput trap

000004

INC(B)

Increment destination

~52DD

JMP

Jump

0001DD

J8R

Jump to subroutine

004RDD

MARK

Mark

0064NN

MFPD

Move from previous data space

006588

MFPI

Move from previous instruction space

106588

MFPS

Move byte from PS

1067DD

MFPT

Move processor type

000007

MOV(B)

Move source to destination

~SSDD

Base Instruction Set 8-3

Table 8-1 (Cont.) Instruction Set
Mnemonic

Instruction

Op Code

MTPD

Move to previous data space

106688

MTPI

Move to previous instruction space

006688

MTP8

Move byte to P8

106488

MUL

Multiply

070RSS

NEG(B)

Negate destination

~54DD

NOP

No operation

000240

RESET

Reset external bus

000005

ROL(B)

Rotate left

~61DD

ROR(B)

Rotate right

~60DD

RTI

Return from interrupt

000002

RTS

Return from subroutine

00020R

RTT

Return from interrupt

000006

SBC(B)

Subtract carry

~56DD

SCC

Set all CC bits

000277

SEC

Set C

000261

SEN

SetN

000270

SEV

Set V

000262

SEZ

SetZ

000264

SOB

Subtract one and branch (if::F 0)

077R00

SPL

Set priority level

00023N

SUB

Subtract source from destination

16SSDD

SWAB

Swap bytes

0003DD

SXT

Sigh extend

0067DD

TRAP

Trap

104400-104777

TST(B)

'Thst destination

~57DD

TSTSET

'Thst destination, set low bit

00720D

WAIT

Wait for interrupt

000001

WRTLCK

Write interlocked

0073DD

XOR

Exclusive OR

o74RDD

The diagram that accompanies each instruction shows the octal op code, and bit
assignments.
NOTE
In byte instructions, the most significant bit (bit 15) is always a 1.

8-4 Base Instruction Set

Symbols:

( ) =contents of

v =Boolean OR

SS or src = source address

V =exclusive OR

DD or DST =destination address

== Boolean not

REG or R =register

loe =location
+--

=becomes

B == byte

t ="is popped from stack"

~ =0 for word, 1 for byte

l == "is pushed onto stack"

, .. concatenated

" • Boolean AND

8.2 Instruction Formats
The following formats include all instructions used in the KDJ11-E. Refer to individual
instructions for more detailed information.

CLR, CLRB, COM, COMB, INC, INCB,
DEC, DECB, NEG, NEGB, ADC, ADCB,
SBC, SBCB, TST, TSTB, ROR, RORB
ROL, ROLB, ASR, ASRB, ASL, ASLB,
JMp, SWAB, MFPS, MTPS, SXT,
TSTSET, WRTLCK

1. Single-Operand Group:

I : : : :OPf-: : : : I :

MA-1183-80.DG

Figure 8-1

Single-Operand Group

2. Double-Operand Groups:

a. Group 1:

BIT, BITB, BIC, BICB, BIS, BISB
ADD, SUB, MOV, MOVB, CMp, CMPB
12

I :opr-: I : : + :" : I : : +: : I
MA·1184·80.DG

Figure 8-2

Double-Operand Group 1

Base Instruction Set- 8-5

ASH, ASHC, DIV, MUL, XOR

h. Group 2:
15

MA-1185-90.0G

Figure 8-3

Double-Operand Group 2

3. Program Control Groups:
a. Branch (all branch instructions)
15

1 :

:
MA-1186-90.0G

Figure 8-4

Program Control Group Branch

b. Jump (JMP)
15

1< :< : >: »11 : :
Figure 8-5

MA-1187-90.0G

Program Control Group JMP

c. Jump to Subroutine (JSR)
15

1<
Figure 8-6

>: : >: I
09

Program Control Group JSR

:R:

I : : 0:0 : : 1
MA-1188-90.0G

8-6 Base Instruction Set

d. Subroutine Return (RTS)
15

1< :< : >: : >: : :a: : >: I
MA-1189-90.DG

Figure 8-7

Program Control Group RTS

e. Traps (breakpoint, lOT, EMT, TRAP, BPT)
15

I::::::

::::::I
MA-1190-90.DG

Figure 8-8

Program Control Group Traps

Subtract 1 and Branch (if =0) (SOB)

1< :< : :< I :< I : :
Figure 8-9

MA-1191-90.DG

Program Control Group Subtract

g. Mark
15

1< :< : >: : :< I : : +: : I
MA-1192-90.DG

Figure 8-10

Mark

h. Call to Supervisor Mode (CSM)
.

1< >: : >: : :< I : : ~D

Figure 8-11

Can to Supervisor Mode

MA-1193-90.DG

Base Instruction Set 8-7

Set PrioritY.Level (SPL)
15

1< >: :
Figure 8-12

>: : :< : :< I >: 1
03

MA·1194-90.DG

Set Priority Level

HALT, WAIT, RTI, RESET, RTT,

4. Operate Group:

NOP,MFPl'
15

10; :0; : >: : I : :
Figure 8-13

::I
MA·1196-90.DG

Operate Group

5. Condition Code Operators:

(all condition code instructions)

MA·1198-90.DG

Figure 8-14

Condition Group

6. Move To and From Previous InstructionlData Space Group:
MTPD, MTPl
MFPD, MFPI

MA·1197·90.DG

Figure 8-15

Move To and From Previous Instruction/Data Space Group

8-8 Base Instruction Set

8.3 Byte Instructions
The KDJ11-E includes a full complement of instructions that manipulate byte operands.
Since all KDJ11-E addressing is byte-oriented, byte manipulation -addressing is
straightforward. Byte instructions with autoincrement or autodecrement direct
addressing cause the specified register to be modified by one to point to the next byte of
data. Byte operations in register mode access the low-order byte of the specified register.
These provisions enable the KDJ11-E to perform as either a word or byte processor.
Figure·8-16 shows the numbering scheme for word and byte addresses in memory.
The most significant bit (bit 15) of the instruction word is set to indicate a byte
instruction.

Example:
Symbolic

Octal Code

Instruction Name

CLR
CLRB

0050DD

Clear word

l050DD

Clear byte
High Byte
Address

Word or Byte
Address

002001

Byte 1

Byte 0

002000

002003

Byte 3

Byte 2

002002

MA-1198-90.OG

Figure 8-16

Byte Instructions

8.4 List of Instructions
The following section provides a functionalli~t of the KDJ11-E instruction set.

Base Instruction Set . 8-9

8.4.1 Single-Operand
General
Mnemonic

Instruction

Op Code

CLR(B)

Clear destination

~50DD

COM(B)

Complement destination

~51DD

INC(B)

Increment destination

~52DD

DEC(B)

Decrement destination

~53DD

NEG(B)

Negate destination

~54DD

TST(B)

Test Destination

WRTLCK

Readllock destination, write
lunlock RO into destination

~57DD
00 73DD

TSTSET

Test destination, set low bit

0072DD

Shift and Rotate
Mnemonic

Instruction

Op Code

ASR(B)

Arithmetic shift right

~62DD

ASL(B)

Arithmetic shift left

~63DD

ROR(B)

Rotate right

~60DD

ROL(B)

Rotate left

~61DD

SWAB

Swap bytes

0003DD

Multiple-Precision
Mnemonic

Instruction

Op Code

ADC(B)

Add carry

~55DD

SBC(B)

Subtract carry

~56DD

SXT

Sign extend

0067DD

PSW Operators
Mnemonic

Instruction

Op Code

MFPS

Move byte from PSW

1067DD

MTPS

Move byte to PSW

1064S8

8-10 Base Instruction Set

8.4.2 Double-Operand
General
Mnemonic

Instruction

Op Code

MOVE(B)

Move source to destination

CMP(B)

Compare source to
destination

~SSDD
~SSDD

ADD

Add source to destination

06SSDD

SUB

Subtract source from
destination

16SSDD

ASH

Arithmetic shift

072RSS

ASHC

Arithmetic shift combined

073RSS

MUL

Multiply

070RSS

DIV

Divide

071RSS

Mnemonic

Instruction

Op Code

BIT(B)

Bit test

I§iSSDD

BIC(B)

Bit clear

I§iSSDD

BIS(B)

Bit set

~SSDD

XOR

Exclusive OR

074RDD

Logical

8.4.3 Program Control
Mnemonic

Instruction

Op Code or Base Code

Branch (unconditional)

000400

BNE

Branch if not equal (to zero)

001000

BEQ

Branch if equal (to zero)

001400

BPL

Branch if plus

100000

BMI

Branch if minus

100400

BVC

Branch if overflow is clear

102000

BVS

Branch if overflow is set

102400

BCC

Branch if carry is clear

103000

BCS

Branch if carry is set

103400

Branch

Base Instruction Set 8-11

Signed Conditional Branch
Mnemonic

Instruction

Op Code or Base Code

BGE

Branch if greater than or
equal (to zero)

002000

BLT

Branch if less than (zero)

002400

BGT

Branch if greater than
(zero)

003000

Branch if less than or equal

003400

BLE

(to zero)

Unsigned Conditional Branch
Mnemonic

Instruction

Op Code or Base Code

BHI

Branch if higher

101000

BLOS

Branch if lower OT same

101400

BHIS

Branch if higher or same

103000

BLO

Branch if lower

103400

Jump and Subroutine
Mnemonic

Instruction

Op Code or Base Code

JMP

Jump

0001DD

JSR

Jump to subroutine

0045DD

RTS

Return from. subroutine

00020R

SOB

Subtract one and branch (if

077RDD

#=)0

Trap and Interrupt
Mnemonic

Instruction

Op Code or Base Code

EMT

Emulator trap

104000-104377

TRAP

Trap

104400-104777

BPT

Breakpoint trap

000003

lOT

Input/output trap

000004

RTI

Return from interrupt

000002

RTT

Return from interrupt

000006

8-12

Base Instruction Set

Miscellaneous Program Control
Mnemonic

Instruction

Op Code or Base Code

CSM

Call to supervisor mode

0070DD

MARK

Mark

0064NN

SPL

Set priority level

00023N

8.4.4 Miscellaneous
Mnemonic

Instruction

Op Code or Base Code

HALT

Halt

000000

WAIT

Wait for interrupt

000001

RESET

Reset external bus

000005

MFPT

Move processor type

000007

MTPD

Move to previous data space

1066DD

MTPI

Move to previous instruction
space

0066DD

MFPD

Move from previous data
space

1065SS

MFPI

Move from previous
instruction space

0065SS

8.4.5 Condition Code Operators
Mnemonic

Instruction

Op Code or Base Code

CLC

Clear C

000241

CLV

Clear V

000242

CLZ

Clear Z

000244

CLN

Clear N

000250

CCC

Clear all CC bits

000257

SEC

Set C

000261

SEV

Set V

000262

SEZ

Set Z

000264

SEN

SetN

000270

sec

Set all ec bits

000277

NOP

No operation

000240

Base instruction Set 8-13

8.5 Single-Operand Instructions
The KDJII-E instructions that involve only one operand are described in the paragraphs
that follow.

8.5.1 General
CLR
CLRB
Clear Destination

[B) 05000
00

MA-1199-90.DG

Figure 8-17

Clear Destination

Operation:

(DST) +-- 0

Condition Codes:

N: cleared
Z: set
V: cleared
C: cleared

Description:

Word: The contents of the specified destination are replaced with Os.
Byte: Same

Example:

CLRR1
Before

After

(R1) = 177777

(R1) = 000000

NZVC

1111

0100

8-14

Base Instruction Set

COM
COMB
Complement DST

[B) 05100

MA·1200·90.DG

Figure 8-18
Operation:

Complement Destination
(DST) + - "-J (DST)

Condition Codes:

N: set if most significant bit of result
is set; cleared otherwise
Z: set if result is 0; cleared otherwise
V: cleared
C: set

Description:

Word: Replace the contents of the destination address by its logical
complement. Each bit equal to 0 is set and each bit equal to 1 is
cleared.
Byte: Same

Example:

COMR
Before

After

(R) =013333

(R) =164444

NZVC

0110

1001

Base Instruction Set 8-15

INC
INCB
Increment DST

[8] 05200

MA·1201·90.DG

Figure 8-19

Increment Destination

Operation:

(DST) +- (DST) + 1

Condition Codes:

N: set if result is -< 0: cleared otherwise
Z: set if result is 0; cleared otherwise
V: set if (DST) held 077777; cleared otherwise
C: not affected

Description:

Word: Add 1 to the contents of the destination.
Byte: Same

Example:

INCR2
Before

After

(R2) = 000333

(R2) = 000334

NZVC

0000

Decrement DST

(8)05300

MA·1202·90.DG

Figure 8-20

Decrement Destination

Operation:

(DST) +- (DST) -

Condition Codes:

N: set if result is -< 0; cleared otherwise
Z: set if result is 0; cleared otherwise
V: set if (DST) was 100000; cleared otherwise
C: not affected

Description:

Word: Subtract 1 from the contents of the destination.

Byte: Same
Example:

DECR5
Before

After

(R5) = 000001

(R5) = 000000

NZVC

1000

0100

8-16 Base Instruction Set

NEG
NEGB
Negate OST

[8]05400
~

~D: : I
MA-1203-90.0G

Figure 8-21

Negate Destination

Operation:

(DST) +- -

(DST)

Condition Codes:

N: set if result is -< 0; cleared otherwise
Z: set if result is 0; cleared otherwise
V: set if (DST) was 100000; cleared otherwise
C: cleared if result is 0; set otherwise

Description:

Word: Replaces the contents of the destination address by its
2's complement. Note that 100000 is replaced by itself. In 2's
complement notation the most negative number has no positive
counterpart.
Byte: Same

Example:

NEGR
Before

After

(R) = 000010

(R) = 177770

NZVC

0000

1001

Base Instruction Set "8-17

TST
TSTB
[8]05700

Test OST

::I

MA-1204-90.0G

Figure 8-22
Operation:

Test Destination
(DST) +- (DST)

Condition Codes:

N: set if result is -< 0; cleared otherwise
Z: set if result is 0; cleared otherwise
V: cleared
C: cleared

Description:

Word: Sets the condition codes N and Z according to the contents of
the destination address; the contents of DST remain unmodified.
Byte: Same.

Example:

TST

Before

After

(Rl) = 012340

(Rl) =012340

NZVC

0011

0000

8-18 Base Instruction Set

WRTLCK
ReadILock Destination
Write/Unlock R 0 into Destination

007300
00

MA-12OS-SlO.DG

Figure 8-23
Operation:

Read/Lock Destination, Write/Unlock RO Into Destination
(DST) . - (R)

Condition Codes:

N: set ifR -< 0
Z: set ifR = 0
V: cleared
C: unchanged

Description:

Writes contents of R into destination using bus lock. If mode is 0,
traps to 10.

TSTSET
007200

Test Destination and Set Low Bit

1«« : : >: >1 : :
Figure 8-24
Operation:

MA-1206-90.DG

Test Destination and Set Low an
(R) . - (DST),(DST) . - (DST) V 000001 (octal)

Condition Codes:

N: set ifR -< 0
Z: set ifR = 0
V: cleared
C: gets contents of old destination bit o.

Description:

Readsllocks destination word and stores it in R. Writes/unlocks (R) V
1 into destination. If mode is 0, traps to 10.

Base Instruction Set 8-19

8.5.2 Shifts and Rotates
Scaling data by factors of two is accomplished by the shift instructions:
ASR-Arithmetic shift right
ASL-Arithmetic shift left
The sign bit (bit 15) of the operand is reproduced in shifts to the right. The low-order
bit is filled with Os in shifts to the left. Bits shifted out of the C-bit, as shown in the
following instructions, are lost.
The rotate instructions operate on the destination word and the C-bit as though they
formed a 17-bit "circular buffer." These instructions facilitate sequential bit testing and
detailed bit manipulation.
ASK
ASRB
Arithmetic Shift Right

.06200
00

MA-1207-90.0G

Figure 8-25
Operation:

Arithmetic Shift Right
(DST) ~ (DST) shifted one place to the right
N: set if high-order bit of result is set (result < 0); cleared otherwise

Condition Codes:

Z: set if result =·0; cleared otherwise

V: loaded from exclusive OR of N-bit and C-bit (as set by the
completion of the shift operation)
C: loaded from low-order bit of destination
Description:

Word: Shifts all bits of the destination right one place. Bit 15 is
reproduced. The C-bit is loaded from bit 0 of the destination. ASR
performs signed division of the destination by 2.
Byte: Same.

Word:

HG-

~-~~:~:~:~::~:~:~:~:~:~:-:~:~:
Byte:

D
~:
5

Odd_....

: : : : : : Hj~: : : : : : : t-G
08

r::7

EvenAddres.

MA-1208-90.DG

Figure 8-26

Example: Arithmetic Shift Right

8-20

Base Instruction Set

ASL
ASLB
Arithmetic Shift Left
15

[B) 06300
07

+: : I
MA·1209·90.DG

Figure 8-27

ArnhmetlcShlft Left

Operation:

(DST) + - (DST) shifted one place to the left

Condition Codes:

N: set if high-order bit of result is set (result < 0); cleared otherwise
Z: set if result = 0; cleared otherwise
V: loaded with exclusive OR of N-bit and C-bit (as set by the
completion of the shift operation)
C: loaded with high-order bit of destination

Description:

Word: Shifts all bits of the destination left one place. Bit 0 is loaded
with a o. The C-bit of the PSW is loaded from the most significant
bit of the destination. ASL performs a signed multiplication of the
destination by 2 with overflow indication.
Byte: Same.

Word:

&1::::::::::::::: I
~ 15

e..n Addr...

C ::::::: r-0c:H : : : : : : : r-o
Odd A d d . . . . . .

rrT

MA-1210·to.DG

Figure 8-28

Example: Arithmetic Shift Left

Base Instruction Set -8-21

ROR
RORB
Rotate Right

06000
00

MA·1213·90.0G

Figure 8-29

Rotate Right

Operation:

(DST) 4 - (DST) rotate one place to the right

Condition Codes:

N: set if high-order bit of result is set (result < 0); cleared otherwise
Z: set if all bits of result = 0; cleared otherwise
V: loaded with exclusive OR of N-bit and C-bit (as set by the
completion of the rotate operation)
C: loaded with low-order bit of destination

Description:

Word: Rotates all bits of the destination right one place. Bit 0 is
loaded into the C-bit and the previous contents of the C-bit are
loaded into bit 15 of the destination.
Byte: Same, except the C-bit is loaded into MSB 7 or 15.

Word:

Byte:

I: : :
Figure 8-30

: : :

Example: Rotate Right

I I : : : E7- : : : I
MA·1214·90.0G

8-22 Base InstrudionSet

ROL
ROLB
(8)06100

Rotate Left

MA·1215-90.DG

Rotate Left

Figure. 8-31
Operation:

(DST) +- (DST) rotate one place to the left

Condition Codes:

N: set if high-order bit of result word is set (result < 0); cleared
otherwise
Z: set if all bits of result word = 0; cleared otherwise
V: loaded with exclusive OR of the N-bit and C-bit (as set by the
completion of the rotate operation)
C: loaded with high-order bit of destination

Description:

Word: Rotates all bits of the destination left one place. Bit 15 is
loaded into the C-bit of the PSW and the previous contents of the
C-bit are loaded into bit 0 of the destination.
Byte: Same, except the C-bit is loaded into LSB 8 or O.

Word:

Byte:

TII----,

I : : : +: : :
15

TII---------"',

"""""'1:~:--r-:--"-~n--r-:..,..-:.,...---.:1
MA-121S·90.DG

Figure 8-32

Example: Rotate Left

Base Instruction Set 8-23

SWAB
·000300

Swap Bytes

MA-1217-90.DG

Figure ~33

Swap Bytes

Operation:

byte 1lbyte O+-byte Olbyte 1

Condition Codes:

N: set if high-order bit of low-order byte (bit 7) of the result is set;
cleared otherwise
Z: set if low-order byte of result =0; cleared otherwise
V: cleared
C: cleared

Description:

Exchanges high-order byte and low-order byte of the destination
word. The destination must be a word address.

Example:

SWABR1

Before

After

(R1)= 077777

(R1)

NZVC

1111

0000

=177577

8-24 Base Instruction Set

8.5.3 Multiple-Precision
It is sometimes necessary to do arithmetic operations on operands considered as multiple
words or bytes. The KDJ11-E makes special provision for such operations with the
instructions ADC (add carry) and SBC (subtract carry) and their byte equivalents.
For example, two 16-bit words may be combined into a 32-bit double-precision word and
added or subtracted as shown below.
32-BitWord

r__------------------.oo------~A~-----------------------------------~,
31

Operand

-------A-1------~11~------A-O------~

,~---------------------------A--------------------------~,
31

Operand

~-----B1------~11~---------oo------------~

I I

Result

MA-1218-eO.DG

Figure 8-34

Multiple-Precision

Base .Instruction Set -8-25

Example:
The addition of -1 and -1 could be performed as follows.
-1 =37777777777
(R1) = 177777 (R2) = 177777 (Ra) = 177777 (R4) = 177777
ADDR1,R2
ADCR3
ADD R4,Ra
1. After (R1) and (R2) are added, 1 is loaded into the C-bit.

2. The ADC instruction adds the C-bit to (Ra); (Ra) =O.
3. (R3) and (R4) are added.
4. The result is 37777777776, or-2

ADC
ADCB
Add Carry

[8105500
~

MA-1219-90.00

Figure 8-35

Add carry

Operation:

(DST)+-(DST) + (C-bit)

Condition Codes:

N: set if result< 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if (DST) was 077777 and (C) was 1; cleared otherwise
C: set if (DST) was 177777 and (C) was 1; cleared otherwise

Description:

Word: Adds the contents of the C-bit to the destination. This permits
the carry from the addition of the low-order words to be carried to the
high-order result.
Byte: Same

Example:

Double-precision addition may be done with the following instruction
sequence:
;add low-order parts
AO,BO
ADD

ADC

;add carry into high-order

ADD

Al,Bl

;add high-order parts

8-26 Base Instruction Set

SBC
SBCB
Subtract Carry

[8]05600

MA·1220·90.DG

Figure 8-36' Subtract carry
Operation:
Condition Codes:

(DST)+-(DSTHC)
N: set if result< 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if (DST) was 100000; cleared otherwise

C: set if (DST) was 0 and C was 1; cleared otherwise
Description:

Word: Subtracts the contents of the C-bit from the destination. This
permits the carry from the subtraction of two low-order wordS to be
subtracted from the high-order part of the result.
Byte: Same

Example:

Double-precision subtraction may be done with the following
instruction sequence:

SUB

AO,BO

SBC

Bl
Al,Bl

SUB

Base Instruction Set 8-27

SXT
Sign Extend

.006700

MA-1221-90.0G

Figure ~7
Operation:

Sign Extend
(DST)~O if N-bit is clear
(DST) ~ 1 ifN-bit is set

Condition Codes:

N: not affected
Z: set if N-bit is clear
V: cleared
C: not affected

Description:

If the condition code bit N is set, a -1 is placed in the destination
operand; if the N-bit is clear, a 0 is placed in the destination operand.
This instruction is particularly useful in multiple-precision arithmetic
because it permits the sign to be extended through multiple words.

Example:

SXTA
Before

After

(A)= 012345

(A)= 177777

NZVC

1000

8-28 Base Instruction Set

8.5.4 PSW Operators .
The MFPS and MTPS are op codes used directly with the processor status word.
MFPS
106700

Move Byte from Processor Status Word

I »»: :< : : I : :
15

Figure 8-38

MA-1222-90.0G

Move Byte from Processor Status Word

Operation:

(DST)+- PSW DST lower 8 bits

Condition Codes:

N: set if PSW bit 7 = 1; cleared otherwise
Z: set ifPSW<7:0>= 0; cleared otherwise
V: cleared
C: not affected

Description:

The 8·bit contents of the PSW are moved to the effective destination.
If the destination is mode 0, PSW bit 7 is sign-extended through the
upper byte of the register. The destination operand address is treated
as a byte address.

Example:

MFPSR
Before

After

(R)= 0

(R)= 000014

(PSW)= 000014

(PSW)= 000000

Base Instruction Set -8-29

MTPS
Move Byte to Processor Status Word

1064SS
06

::I
MA-1223-90.0G

Figure 8-39

Move Byte to Processor Status Word

Operation:

PSW +- (src)

Condition Codes:

Set according to effective SRC operand bits <3:0>

Description:

The eight bits of the effective operand replace the current contents of
the lower byte of the PSW. The source operand address is treated as
a byte address. Note: The T-bit (PSW bit 4) cannot be set with this
instruction. The SRC operand remains unchanged. This instruction
can be used to change the priority bits (PSW <7:5» in the PSWonly
in kernel mode. If not in kernel mode, PSW <7:5> cannot be changed.

Example:

MTPS R1
Before

After

(R1)= 000777

(PSW)= XXXOOO

(PSW)= XXX357

NZVC

0000

1111

8-30 Base Instruction Set

8.6 Double-Operand Instructions
Double-operand instructions· save instructions (and time), since they eliminate the need
for load and save sequences such as those used in accumulator-oriented machines.

8.6.1 General
MOV
MOVB
Move Source to Destination
15

[BJ1SSDD

MA·1224·90.DG

Figure 8-40

Move Source to Destination

Operation:

(DST) +- (arc)

Condition Codes:

N: set if (arc) < 0; cleared otherwise
Z: set if (src) = 0; cleared otherwise
V: cleared
C: not affected

Description:

Word: Moves the source operand to the destination location. The
previous contents of the destination are lost. Contents of the source
address are not affected.
Byte: Same as MOV. The MOVB to a register (unique among byte
instructions) extends the most significant bit of the low-order byte
(sign extension). Otherwise, MOVB operates on bytes exactly as
MOV operates on words.

Example:

MOVxxx,R1

MOV '20,R

;loads register 1 with the contents of
memory location; xxx represents a
programmer defined mnemonic used to
represent a memory location
;loads the number 20 into register 0;
# indicates that the value 20 is the

operand
MOV @20,-{R6)

;pushes the operand contained in
location 20 onto the stack

MOV (R6)+,@177566

;pops the operand off a stack and
moves it into memory location 177566
(terminal print buffer)

MOV R1,Ha

;performs an inter-register transfer

MOVB @177562,@177566

;moves a character from the terminal
keyboard buffer to the terminal printer
buffer

Base Instruction Set 8-31

CMP
CMPB
Compare SRC to DST
15
12

[B]2SSDD
11

MA-1225-90.DG

Figure 8-41
Operation:

Compare SRC to Destination
(srcHDST)

Condition Codes:

N: set if result <0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if there was arithmetic overflow; that is, operands were of
opposite signs and the sign of the destination was the same as the
sign of the result; cleared otherwise
C: cleared if there was a carry from the most significant bit of the
result; set otherwise

Description:

Compares the source and destination operands and sets the condition
codes, which may then be used for arithmetic and logical conditional
branches. Both operands are not affected. The only action is to
set the condition codes. The compare is customarily followed by
a conditional branch instruction. Notice that unlike the subtract
instruction, the order of operation is (arc) - (DST), not (DST) (src)

8-32 Base Instruction Set

ADD
Add SAC to OST
15

06SS00
12

10; : ;0 I : :
MA-1227-90.DG

Figure 8-42
Operation:

Add SRC to Destination
(DST) ~ (src) + (DST)

Condition Codes:

N: set if result <0; cleared otherwise
Z: set if result = 0; cleared otherwise
V; set if there was arithmetic overflow as a result of the operation,
that is, both operands were of the same sign and the result was of
the opposite sign; cleared otherwise
C: set if there was a carry from the most significant bit of the result;
cleared otherwise

Description:

Adds the source operand to the destination operand and stores
the result at the destination address. The original contents of the
destination are lost. The contents of the source are not affected. 2's
complement addition is performed. Notice that there is no equivalent
byte mode.

Example:

Add to register:

ADD #20,R

Add to memory:

ADDR1,xxx

Add register to register:

ADDR1,R2

Add memory to memory:

ADD @ 17750)00{

(XXX is a programmer-defined mnemonic for a memory location.)

Base Instruction Set 8-33

SUB
16SSDD

Subtract SRC from DST

I : : >I : : +
15

Figure 8-43
Operation:

MA-1226-90.0G

Subtract SRC from DST
(DST) +- (DST) -

(src)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if there was arithmetic overflow as a result of the operation,
that is, if operands were of opposite signs and the sign of the source
was the same as the sign of the result; cleared otherwise
C: cleared if there was a carry from the most significant bit of the
result; set otherwise

Description:

Subtracts the source operand from the destination operand and
leaves the result at the destination address. The original contents of
the destination are lost. The contents of the source are not affected.
In double-precision arithmetic the C-bit, when set, indicates a
"borrow." Notice that there is no equivalent byte mode.

Example:

SUB R1,R2
Before

After

(R1) = 011111

(R2) = 012345

(R2) = 001234

NZVC

1111

0000

8-34 Base Instruction Set

ASH
Arithmetic Shift

072RSS

:< >1 :< 1 : : + : :
09

MA-1228-90.0G

Figure~

Operation:

Arfthmetlc Shift
R +- R shifted arithmetically NN places to the right or left where
NN = (src)

Condition Codes:

N: set if result < 0
Z: set if result =0
V: set if sign of register changed during shift
C: loaded from last bit shifted out of register

Description:

The contents of the register are shifted right or left the number of
times specified by the source operand. The shift count is taken as the
low-order six bits of the source operand. This number ranges from
-32 to +31. Negative is a right shift and positive (less than +31) is a
left shift.

NOTE

A shift count of +31 shifts the contents of the register to the right 31 times.

Base Instruction Set 8-35

ASHe
Arithmetic Shift Combined

< : I :< I : :
09

10; : : :
Figure 8-45

[B]073RSS

MA-1229-90.DG

Arithmetic Shift Combined

Operation:

R, R V 1~ R, Rv 1
The double word is shifted NN places to the right or left where NN =
(src)

Condition Codes:

N: set if result < 0
Z: set if result = 0
V: set if sign bit changes during shift
C: loaded with high-order bit when left shift; loaded with low-order
bit when right shift (loaded with the last bit shifted out of the 32-bit
operand)

Description:

The contents of the register and the register ORed with 1 are treated
as one 32-bit word. Rv 1 (bits <15:0» and R (bits <31:16» are
shifted right or left the number of times specified by the shift count.
The shift count is taken as the low-order 6 bits of the source operand;
the upper 11 bits of the source operand must be O. This number
ranges from -32 to +31. Negative is a right shift and positive is a left
shift.
When the register chosen is an odd number, the register and the
register ORed with 1 are the same. In this case, the right shift
becomes a rotate. The 16-bit word is rotated right the number of
times specified by the shift count.

NOTE

Bits <5:0> shift count. Bits <15:6> must be o.

8-36 Base Instruction Set

MUL
Multiply

070RSS

1< : : »>1 :< 1 : : +: : I
MA·1230·90.DG

Figure 8-46

Multiply

Operation:

R, R V I+-R x (src)

Condition Codes:

~: set if product < 0
Z: set if product = 0
V: cleared
C: set if the result is less than -2 ** 15 or greater than or equal to 2
**15 -1.

Description:

The contents of the destination register and source taken as 2's
complement integers are multiplied and stored in the destination
register and the succeeding register, if R is even. If R is odd, only the
low-order product is stored. Assembler syntax is: MUL S,R. Notice
that the actual destination is R,R V 1, which reduces to just R when
Ris odd.

DIY
Divide

171 RSS

10; : : :a:a: 1
Figure 8-47

>: 1 : : +: : 1
MA·1231·91.DG

Divide

Operation:

R, R V I+- R, R V lI(src)

Condition Codes:

N: set if quotient < 0
Z: set if quotient =0
V: set if source = 0 or if the absolute value of the register is larger
than the absolute value of the instruction in the source. (In this case
the instruction is a~rted because the quotient would exceed 15 bits.)
C: set if divide by zero is attempted.

Description:

The 32-bit 2's complement integer in R and R V 1 is divided by the
source operand. The quotient is left in R; the remainder is of the
same sign as the dividend. R must be even.

Base Instruction Set -8-37

8.6.2 Logical
These instructions have the same format as those in the double-operand
arithmetic group. They permit operations on data at the bit le-vel.
BIT

BITB
Bit Test

(B]3SSDD

MA-1232-90.0G

Figure 8-48

Bit Test

Operation:

(src) " (DST)

Condition Codes:

N: set if high-order bit of result set; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared
C: not affected

Description:

Performs logical AND comparison of the source and destination
operands and modifies condition codes accordingly. Neither the
source nor the destination is affected. The BIT instruction may
be used to test whether any of the corresponding bits set in the
destination are also set in the source, or whether all corresponding
bits set in the destination are clear in the source.

Example:

BIT #30,R3

;test bits three and four of R3 to see if
both are off.

R3 = 0000000000011
000
Before

After

NZVC

1111

0001

8-38 Base Instruction Set
BIC
BICB
[B)4SSDD

Bit Clear

MA-1233-90.0G

Figure 8-49

Bit Clear

Operation:

(DST)+-IV (src)A (DST)

Condition Codes:

N: set if high-order bit of result set; cleared
otherwise
Z: set if result =0; cleared otherwise
V: cleared
C: not affected

Description:

Clears each bit in the destination that corresponds to a set bit in
the source. The original contents of the destination are lost. The
contents of the source are not affected.

Example:

BIC RS,R4
Before

After

(RS) = 001234

(R4) =001111

(R4) =000101

NZVC

1111

0001

Before:

(RS) = 0 000 001 010 011 100
(R4) = 0 000 001 001 001 001

After:

(R4) = 0 000 000 001 000 001

Base Instruction Set 8-39

DIS
DISD
[B]5SSDD

Bit Set

MA-1234-90.DG

Figure 8-50

Bit Set

Operation:

(DBT)~ (src) V (DST)

Condition Codes:

N: set if high-order bit of result set; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared
C: not affected

Description:

Performs an inclusive OR operation between the source and
destination operands and leaves the result at the destination address,
that is, corresponding bits set in the source are set in the destination.
The contents of the destination are lost

Example:

BIB R,Rl
Before

After

(R) = 001234

(R1) = 001111

(Rl) =001335

NZVC

0000

Before:

(R) = 0 000 001 010 011 100
(Rl) =0 000 001 001 001 001

After:

(Rl) = 0 000 001 011 011 101

8-40

Base Instruction Set

XOR
[B]074RDD

Exclusive OR

1< : : : »1 >: I : : : : I
15

0;0

MA-1235-90.0G

Figure 8-51

Exclusive OR

Operation:

(DST) +-(reg) V (DST)

Condition Codes:

N: set if result V 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared
C: not affected

Description:

The exclusive OR of the register and destination operand is stored in
the destination address. The contents of the register are not affected.
The assembler format is XOR R,D.

Example:

XORR,R2
Before

After

(R) = 001234

(R2) = 001111

(R2) = 000325

NZVC

1111

0001

Before:

(R) = 0 000 001 010 011 100
(R2) =0 000 001 001 001 001

After:

(R2) = 0 000 000 011 010 101

Base Instruction Set -&-41

8.7 Program Control Instructions
The following paragraphs describe the KDJ11-E instructions that affect program control.

8.7.1 Branches
Program control instructions cause a branch to a location defined by the sum of the offset
(multiplied by 2) and the current contents of the program counter if:
1. The branch instruction is unconditional.

2. The branch instruction is conditional and the conditions are met after testing the
condition codes (N Z V C).
The offset is the number of words from the current contents of the PC, forward or
backward. Note that the current contents of the PC point to the word following the
branch instruction.
Although the offset expresses a byte address, the PC is expressed in words. The offset
is automatically multiplied by 2 and sign-extended to express words before it is added to
the PC. Bit 7 is the sign of the offset. If it is set, the offset is negative and the branch
is done in the backward direction. If it is not set, the offset is positive and the branch is
done in the forward direction.
The a-bit offset allows branching in the backward direction by 200 octal words (400 octal
bytes) from the current PC, and in the forward direction by 177 octal words (376 octal
bytes) from the current PC.
The KDJ11-E assembler typically handles address arithmetic for the user and computes
and assembles the proper offset field for branch instructions in the following format:
Bxx loc
Bxx is the branch instruction and loc is the address where the branch is to be made. The
assembler gives an error indication in the instruction if the permissible branch range
is exceeded. Branch instructions have no effect on condition codes. Conditional branch
instructions where the branch condition is not met are treated as NOPs.

8-42

Base Instruction Set

BR
Branch (Unconditional)

000400 Plus Offset

1«««< I: : :~M: : : 1
MA-1238-90.DG

Figure 8-52 . Branch (Unconditional)
Operation:

PC+- PC + (2 x offset)

Condition Codes:

Not affected

Description:

Provides a way of transferring program control within a range of -128 to +127
words with a one word instruction.
New PC address =updated PC + (2 x offset)
Updated PC =address of branch instruction +2

Example:

With the branch instruction at location 500, the following offsets apply:

New PC Address

Offset Code

Offset (decimal)

474

--S

500

875
876
377

502

000

504

001

506

002

476

-2
-1

Base Instruction Set 8--43

BNE
Branch if Not Equal (to Zero)

0001000 Plus Offset

1«««< I : : :
08

Figure 8-:-53

MA-1237-90.0G

Branch If Not Equal (to Zero)

Operation:

PC+- PC + (2x offset) if Z = 0

Condition Codes:

Not affected

Description:

'Thsts the state of the Z-bit and causes a branch if the Z-bit is clear. BNE
is the complementary operation of BEQ. It is used to test: (1) inequality
following a CMP, (2) that some bits set in the destination were also in the
source following a BIT operation,and (3) generally, that the result of the
previous operation was not o.

Example:

Branch to C if A ;:f: B
;compare A and B
CMPA,B
BNEC

;branch if they are not equal

Branch to C if
A+B;:f:O
ADDA,B

;addAtoB

BNEC

;branch if the result is not equal to 0

8-44 Base Instruction Set

BEQ
Branch if Equal (to Zero)

001400 Plus Offset

1««« : I : : :+<: : I
15

MA-1238-90.DG

Figure 8-54

Branch If Equal (to Zero)

Operation:

PC+- PC + (2x offset) if Z = 1

Condition Codes:

Not affected
'Thsts the state of the Z-bit and causes a branch if Z is set. It is used to test:

Description:

(1) equality following a CMPoperation, (2) that no bits set in the destination
were also set in the source following a BIT operation, and (3) generally, that

the result of the previous operation was o.

Example:

Branch to C if A = B
CMPA,B

;compare A and B

BEQC

;branch if they are equal

Branch to C if

A+B=O
ADDA,B

;add A to B

BEQC

;branch if the result = 0

BPL
100000 Plus Offset

Branch if Plus

MA-1239-90.DG

Figure 8-55

Branch If Plus

Operation:

PC+- PC + (2 x offset) if N =0

Condition Codes:

Not affected

Description:

'Thsts the state of the N-bit and causes a branch if N is clear (positive result).
BPL is the complementary operation of BMI.

Base Instruction Set -8-45

BMI
Branch if Minus

100400 Plus Offset

1>:««<
15

Figure 8-56

>+1: : : I
00

MA-124o-90.DG

Branch If Minus

Operation:

PC ~ PC + (2 x offset) if N = 1

Condition Codes:

Not affected

Description:

'Thsts the state of the N-bit and causes a branch if N is set. It is used to
test the sign (most significant bit) of the result of the previous operation,
branching if negative. BMI is the complementary function of BPL.

Bve
102000 Plus Offset

Branch if Overflow is Clear
15

1»»»>1: : :+< : : I
MA-1241-91.DG

Figure 8-57

Branch If Overflow Is Clear

Operation:

PC ~ PC· + (2 x offset) if V = 0

Condition Codes:

Not affected

Description:

'Thsts the state of the V-bit and causes a branch if the V-bit is clear. BVC is
the complementary operation of BVS.

8-46 Base Instruction Set

BVS
102400 Plus Offset

Branch if Overflow is Set

MA-1242-91.0G

Figure 8-58

Branch If Overflow Is Set

Operation:

PC +- PC + (2 x offset) if V = 1

Condition Codes:

Not affected

Description:

'Thsts the state of the V-bit (overflow) and causes a branch if V is set. BVS is
used to detect arithmetic overflow in the previous operation.

Bee
103000 Plus Offset

Branch if Carry is Clear
15

I»»: : >1 : : :0+< : : I
MA-1243-91.0G

Figure 8-59
Operation:

Branch If Carry Is Clear
PC +- PC + (2 x offset) ifC = 0

Condition Codes:

Not affected

Description:

'Thsts the state of the C-bit and causes a branch if C is clear. BCC is the
complementary operation of BeS.

Des
Branch if Carry Is Set
15

103400 Plus Offset
08

»;0:< : :

Figure 8-60

:c+< : :

MA-1244-91.0G

Branch If Carry Is Set

Operation:

PC +- PC + (2 X offset) if C = 1

Condition Codes:

Not affected

Description:

'Thsts the state of the C-bit and causes a branch if C is set. It is used to test
for a carry in the result of a previous operation.

Base Instrudion Set 8-47

8.7.2 Signed Conditional Branches
Particular combinations of the condition code hits are tested with the signed conditional
branches. These instructions are used to test the results of instructions in which the
operands were considered as signed (2's complement) values.
Note that the sense of signed comparisons differs from that of unsigned comparisons in
that in signed, 16-hit, 2's complement arithmetic, the sequence of values is as follows:
largest

077777

positive

077776

000001
000000
177777
177776

smallest
negative

100001
100000

Whereas, in unsigned, 16-bit arithmetic, the sequence is considered to be:
lrighest
177777

000002
000001
lowest

000000

8-48

Base Instruction Set

BGE
Branch if Greater Than or Equal (to Zero)

002000 Plus Offset

MA-1245-91.DG

Figure 8-61

Branch If Greater Than or Equal (to Zero)

Operation:

PC +- PC + (2 x offset) if N V V = 0

Condition Codes:

Not affected

Description:

Causes a branch if N and V are either both clear or both set. BGE is the
complementary operation of BLT. Thus, BGE will always cause a branch
when it follows an operation that caused addition of two positive numbers.
BGE will also cause a branch on a 0 result.

BLT
Branch is Less Than (Zero)

002400 Plus Offset

1««0; :< I: : :+< : : I
15

MA-1246-91.DG

Figure 8-62

Branch If Less Than (Zero)

Operation:

PC +- PC + (2 x offset) if N V V = 1

Condition Codes:

Not affected

Description:

Causes a branch if the exclusive OR of the N- and V-bits is 1. Thus, BLT
will always branch following an operation that added two negative numbers,
even if overflow occurred. In particular, BLT will always cause a branch if
it follows a CMP instruction operating on a negative source and a positive
destination (even if overflow occurred). Further, BLT will never cause a
branch when it follows a CMP instruction operating on a positive source and
negative destination. BLT will not cause a branch if the result of the previous
operation was 0 (without overflow).

Base Instrudion Set 8-49

BGT
Branch is Greater Than (Zero)

003000 Plus Offset

MA-1247-91.DG

Figure 8-63

Branch If Greater Than Zero

Operation:

PC 4 - - PC + (2 x offset) if Z (N V v) =0

Condition Codes:

Not ~ected

Description:

Operation of BGT is similar to BGE, except that BGT will not cause a branch
on a 0 result.

BLE
Branch if Less Than or Equal (to Zero)
15

003400 Plus Offset
08

0; 0; 0; 0; 0; : : I : : :

+: :

MA-1248-91.DG

Figure 8-64

Branch If Less Than or Equal (to Zero)

Operation:

PC 4 - - PC + (2 x offset) if Z v (N V V) =1

Condition Codes:

Not affected

Description:

Operation is similar to BLT, but in addition will cause a branch if the result
of the previous operation was o.

8-50 Base Instruction Set

8.7.3 Unsigned Conditional Branches
The unsigned conditional branches provide a means for testing the result of comparison
operations in which the operands are considered to be unsigned values.

BBI
101000 Plus Offset

Branch if Higher
15

+: : : I
00

MA·1249-91.DG

Figure 8-65

Branch HHigher

Operation:

PC +- PC + (2 x offset) if C = 0 and Z =0

Condition Codes:

Not affected

Description:

Causes a branch if the previous operation caused neither a carry nor a 0
result. This wi]] happen in comparison (CMP) operations as long as the
source has a higher unsigned value than the destination.

BLOS
Branch if Lower or Same

101400 Plus Offset

I :««< : I : : :+< : : I
15

MA·1250-91.OG

Figure 8-66

Branch If Lower or Same

Operation:

PC +- PC + (2 x offset) if C V Z =1

Condition Codes:

Not affected

Description:

Causes a branch if the previous operation caused either a carry or a 0 result.
BLOB is the complementary operation of BHI. The branch will occur in
comparison operations as long as the source is equal to or has a lower
unsigned value than the destination.

Base instruction Set 8-51

BBIS
Branch if Higher or Same

103000 Plus Offset

I»»: : >1 : : :+: : : I
08

MA-1251-91.DG

Figure ~7

Branch If Higher or Same

Operation:

PC +- PC + (2 x offset) if C =0

Condition Codes:

Not affected

Description:

BHIS is the same instruction as BCC. This mnemonic is included for
convenience only.

BLO
Branch if Lower

103400 Plus Offset

I»»: : :

Figure 8-68

:+: : :

MA-1252-91.DG

Branch If Lower

Operation:

PC +- PC + (2 x offset) if C =1

Condition Codes:

Not affected

Description:

BLO is the same instruction as BCS. This mnemonic is included for
convenience only.

8-52 Base Instruction Set

8.7.4 Jump and Subroutine Instructions
The subroutine call in the KDJII-E provides for automatic nesting of subroutines,
reentrancy, and multiple entry points. Subroutines may call other $ubroutines (or indeed
themselves) to any level of nesting without making special provision for storage of return
addresses at each level of subroutine call. The subroutine calling mechanism does not
modify any fixed location in memory, and thus provides for reentrancy. This allows one
copy of a subroutine to be shared among several interrupting processes.

JMP
000100

Jump

MA-1253-90.DG

Figure 8-69
Operation:

Jump
PC +- (DST)

Condition Codes:

Not affected

Description:

JMP provides more flexible program branching than the branch instructions
do. Control may be transferred to any location in memory (no range
limitation) and can be accomplished with the full flexibility of the addressing
modes, with the exception of register mode o. Execution of a jump with
mode 0 will cause an illegal instruction condition, and will cause the CPU
to trap to vector address 4. (Program control cannot be transferred to a
register.) Register-deferred mode is legal and will cause program control to be
transferred to the address held in the specified register. Note that instructions
are word data and must therefore be fetched from an even-numbered address.
Deferred-index mode JMP instructions permit transfer of control to the
address contained in a selectable element of a table of dispatch vectors.

Example:

First:
JMP FIRST

;transfers to FIRST

JMP@LIST

;transfers to location pointed to at LIST

List:
FIRST

;pointer to FIRST

JMP@(SP)+

;transfer to location pointed to by the top of the stack,
and remove the pointer from the stack

Base Instruction Set -8-53

JSR
004RDD

Jump To Subroutine
15

. MA·1254·90.DG

Figure &-70
Operation:

Jump to Subroutine
(tmp) +- (DST) (tmp is an internal processor register)

! (SP) reg (pushes register contents onto processor stack)
reg +- PC (PC holds location following JSR-this address now put in
register)
PC +- (DST) (PC now points to subroutine destination)
Description:

In execution of the JSR, the old contents of the specified register (the linkage
pointer) are automatically pushed onto the processor stack and new linkage
information is placed in the register. Thus, subroutines nested within
subroutines to any depth may all be called with the same linkage register.
There is no need either to plan the maximum depth at which any particular
subroutine will be called or to include instructions in each routine to save
and restore the linkage pointer. Further, since all linkages are saved in a
reentrant manner on the processor stack, execution of a subroutine may be
interrupted. The same subroutine may be reentered and executed by an
interrupt serVice routine. Execution of the initial subroutine can then be
resumed when other requests are satisfied. This process (called nesting) can
proceed to any level.
.
A subroutine called with a JSR reg,DST instruction can access the arguments
following the call with either autoincrement addressing, (reg) +, if arguments
are accessed sequentially; or by indexed addressing, X(reg), if accessed in
random order. These addressing modes may also be deferred, @(reg)+ and
@X(reg), if the parameters are operand addresses rather than the operands
themselves.
JSR PC, DST is a special case of the KDJII-E subroutine call suitable for
subroutine calls that transmit parameters through the general registers. The
SP and the PC are the only registers that may be modified by this call.
Another special case of the JSR instruction is JSR PC,@(SP) +, which
exchanges the top element of the processor stack with the contents of the
program counter. This instruction allows two routines to swap program
control and resume operation from where they left off when they are recalled.
Such routines are called coroutines.
Return from a subroutine is done by the (RTS) instruction. (RTS) reg loads
the contents of reg into the PC and pops the top element of the processor
stack into the specified register.

NOTE

JSR with register mode destination 0 is illegal and traps to 10.

8-54 Base Instruction Set

Example:
SBCALL:

JSRRS,SBR

SBCALL+4:

ARGI

SBCALL

ARG2

SBCALL+2+2M:

ARG M

CONT:

Next Instruction

CONT

SBR:

MOV (R5)+,DST 1

SBCALL+4

n-2

SBR

n-2

EXIT

MOV (R5)+,DST 2

EXIT:

MOV (R5)+,DST M

SBCALL+2+2M

Other Instructions

CONT

RTSRS

CONT
JSR RS,SBR

Before:

After:

(PC) R71

(SP) R6

SBR

n-2

I
I

Rsl

PC+2

Stack

I
I

....

DATA 0

...

MA-1255-90

Figure 8-71

Example: Jump to Subroutine

Base Instrudion Set 8-55

RT8
Return from Subroutine
15

. 00020R

»»>:< »»1 :< I
03

0
:

MA-1258-80.DG

Figure 8:-72
Operation:
Description:

Return from Subroutine
PC +- (reg)
(reg) +- (SP) t
Loads the contents of the register into the PC and pops the top element of the
processor stack into the specified register.
Return from a nonreentrant subroutine is typically made through the same
register that was used in its call. Thus, a subroutine called with a JSR PC,
DST exits with an RTS PC, and a subroutine called with a JSR R5, DST may
pick up parameters with addressing modes (R5) +, X(R5), or @X(R5), and
finally exits with an RTS R5.

Example:

RTS R5
RTSR5

Before:

Stack

SBR

I
I

ASI

(PC) R7

DATA 0
(SP) R6

After:

...... PC .....

R71

n+2

I
I

-""

DATA 0

MA-1257-90

Figure 8-73

Example: RTS RS

8-56

Base Instruction Set

SOB
Subtract One and Branch (IF::/:O)

077RNN

1< : : : : : I :< I : : +< : I
15

MA-1258-90.DG

Figure ~74

Subtract One and Branch

Operation:

(R) ~ (R}-l; if this result '1= 0, then PC ~ PC-(2 x offset); if (R) = 0 then
PC~PC

Condition Codes:

Not affected

Description:

The register is decremented. If the contents does not equal 0, twice the offset
is subtracted from the PC (now pointing to the following word). The offset
is interpreted as a 6-bit positive number. This instruction provides a fast,
efficient method of loop control. The assembler syntax is SOB R,A where A is
the address to which transfer is to be made if the decremented R is not equal
to 0. Notice that the SOB instruction cannot be used to transfer control in the
forward direction.

8.7.5 Traps
Trap instructions provide for calls to emulators, 110 monitors, debugging packages, and
user-defined interpreters. A trap is effectively an interrupt generated by software. When
a trap occurs, the contents of the current PC and PSW are pushed onto the processor
stack and are replaced by the contents of a 2-word trap vector containing a new PC and
new PSW.The return sequence from a trap involves executing an RTI or RTT instruction,
which restores the old PC and old PSW by popping them from the stack. Trap instruction
vectors are located at permanently assigned fixed addresses.

Base Instruction Set 8-57

EMT
Emulator Trap

104000-104377

I »:0: >;0>1 : : : : : : : I
MA·12S9-91.DG

Figure 8-75
Operation:

Emulator Trap
! (SP)+- PSW
! (SP)+- PC
PC+- (30)
PSW+- (32)

Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

All operation codes from 104000 to 104377 are EMT instructions and may
be used to transmit information to the emulating routine (for example, the
function to be performed). The trap vector for EMT is at address 30. The new
PC is taken from the word at address 30; the new PSW is taken from the
word at address 32.

NOTE

EMT is used frequently by Digital system software and is therefore not
recommended for general use.
Before:

Stack

PS 1

PC 1

I
I

-...

DATA 1

n
I __
....

SP ...

After:

(32)

(30)

n-4

DATA 1
PS 1

...

PC 1

MA-126Q.90

Figure 8-76

Example: Emulator Trap

8-58 Base Instruction Set

TRAP
104400-104n7

Trap

:0;0; I : : :

+: : : I
00

MA-1261-91.DG

Figure 8-77
Operation:

Trap
! (SP)+- PSW
! (SP)+- PC
PC+- (34)
PSW+- (36)

Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

Operation codes from 104400 to 104777 are TRAP instructions. TRAPs and
EMTs are identical in operation, except that the trap vector for TRAP is at
address 34.

NOTE

Since Digital software makes frequent use of EMT, the TRAP instruction is
recommended for general use.
BPr
Breakpoint Trap

000003

0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0:

: 1 I

MA-1262-90.DG

Figure 8-78
Operation:

Breakpoint Trap
! (SP)+- PSW
! (SP)+- PC
PC+- (14)
PSW+- (16)

Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

Performs a trap sequence with a trap vector address of 14. Used to call
debugging aids. The user is cautioned against employing code 000003 in
programs run under these debugging aids. (No information is transmitted in
the low byte.)

Base Instrudion Set 8-59

lOT
Input/Output Trap

000004

I 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0:

: 0 : 0

MA-1263-90.OG

Figure ~79

Input/Output Trap
! (SP)~ PSW
!(SP)~ PC
PC~ (20)

Operation:

PSW~(22)

Condition Codes:

N: loaded from trap vector

Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

Performs a trap sequence with a trap vector address of 20. (No information is
transmitted in the low byte.)

RTI
Return from Interrupt

000002

I 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0 : 0:

: 0

MA-1264-90.OG

Figure 8-80
Operation:

Return from Interrupt
PC~ (SP)t
PSW~ (SP)

Condition Codes:

N: loaded from processor stack
Z: loaded from processor stack
V: loaded from processor stack
C: loaded from processor stack

Description:

Used to exit from an intelTUpt or TRAP service routine. The PC and PSW are
restored (popped) from the processor stack. If the RTI sets the T-bit in the
PSW, a trace trap will occur prior to execution of the next instruction.
When executing in kernel mode, any legal mode can be stored in PSW <15:14,
13:12>. When executing in supervisor mode, only supervisor or user mode can
be stored, and in user mode, only the user mode can be stored.

•

When executing in kernel mode, either a 1 or a 0 can be stored in PSW bit 11.
When executing in supervisor mode, a stored 0 can be changed to a 1, but a
stored 1 cannot be changed to a O.

8-60 Base Instruction Set

RTT
Return from Trap

000006

1°;0»»»:««< : >1
MA·1285-90.DG

Figure 8-81

Return from Trap

Operation:

PC+- (SP)t
PSW+- (SP)t

Condition Codes:

N: loaded' from processor stack
Z: loaded from processor stack
V: loaded from processor stack
C: loaded from processor stack

Description:

Operation is the same as RTI except that it inhibits a trace trap, whereas RTI
permits a trace trap. If the new PSW has the T-bit set, a trap will occur after
execution of the instruction following RTT.
When executing in kernel mode, any legal mode can be stored in PSW
<15:14,13:12>. When executing in supervisor mode, only supervisor or user
mode can be stored, and in user mode, only the user mode can be stored.
When executing in kernel mode, either a 1 or a 0 can be stored in PSW bit 1t.
When executing in supervisor mode, a stored 0 can be changed to a 1, but a
stored 1 cannot be changed to a O.

Base Instrudion Set -8-61

8.7.5.1 Miscellaneous Program Controls

MARK
0064NN

Mark
~

+: : I
MA-1287-90.0G

Figure 8-82

Mark
SP +- PC + 2 X NN
PC +-RS
RS +- (SP)+

Operation:

(NN = number of parameters)

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

Description:

Used as part of the standard subroutine return convention. MARK
facilitates the stack clean-up procedures involved in subroutine exit.
Assembler fonnat is: MARK N.

Example:

MOV RS,-{SP)

;place old RS on stack

MOV Pl,-{SP)

;place N parameters on

MOV P2,-{SP)

;the stack to be used
;there by the subroutine

MOV PN,-{SP)
MOV MARKN,-{SP)

;place the instruction
;MARK N on the stack

MOVSp,RS

;set up address at MARK N
;instruction

JSRPC,SUB

;jump to subroutine

At this point the stack is as follows:
OlOR5
P1
PN
MARKN

Olope
MA-1266-90.0G

Figure 8-83

Example: Mark

8-62 Base Instruction Set

. The program is at the address SUB, which is the beginning of the subroutine.
SUB:

;execution of the
;subroutine itself

RTSRS

;the return begins:
;this causes the contents
;of R5 to be placed in the
;pC which then results in
;the execution of the
;instruction MARK N. The
;contents of the old PC
;are placed in RS.

NOTE

If memory management is in use, the stack must be mapped through both I and
D space to execute the MARK instruction.

SPL
0OO23N

Set Priority Level

MA·1268·90.DG

Figure 8-84

Set Priority Level

Operation:

PSW bits <7:5> + - priority
(priority = N)

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

Description:

In kernel mode, the least significant three bits of the instruction are
loaded into PSW bits <7:5>, thus causing a changed priority. The
old priority is lost. In user or supervisor modes, SPL executes as an
NOP.
Assembler syntax is: SPL N

Base Instruction Set 8-63

CSM
007000

Call to Supervisor Mode

MA-1269-90.0G

Figure 8-85

call to Supervisor Mode

Operation:

If MMR3 bit 3 = I, and current mode =kernel, then supervisor SP+-- current
mode SP temp <15:4>+-- PSW <15:4> temp <3:0>+- 0
PSW <13:12>+-- PSW <15:14>
PSW <15:14>+-- 1
PSW 4+-- 0
-(SP)+-- temp
-(SP)+-- PC
-(SP)+-- (DST)
-PC+-- (10);
otherwise, traps to 10 in kernel mode.

Condition Codes:

N: unaffected
Z:unafTected
V: unaffected
C: unaffected

Description:

CSM may be executed in user or supervisor mode, but is an illegal instruction
in kernel mode. CSM copies the current SP to the supervisor mode, switches

to supervisor mode, stacks three words on the supervisor stack (the PSW with
the condition codes cleared, the PC, and the argument word addressed by the
operand), and sets the PC to the contents of location 10 (in supervisor space).
The called program in supervisor space may return to the calling program by
popping the argument word from the stack. and executing RTI. On return, the
condition codes are determined by the PSW on the stack. Hence, the called
program in supervisor space may control the condition code values following
return.

8.7.6 Reserved Instruction Traps
Reserved instruction traps are caused by attempts to execute instruction codes reserved
for future processor expansion (reserved instructions) or instructions with illegal
addressing modes (illegal instructions). Order codes not corresponding to any of the
instructions described are considered to be reserved instructions. JMP and JSR with
register mode destinations are illegal instructions; they trap to virtual address 10 in
kernel data space. Reserved instructions trap to vector address 10 in kernel data space.

8-64 Base Instruction Set

8.7.7 Trace Trap
Trace trap is enabled by bit 4 of the PSW and causes processor traps at the end of
instruction execution. The instruction that is executed after the instruction that sets the
T-bit proceeds to completion and then traps through the trap vector at address 14. The
trace trap is a system debugging aid and is transparent to the general programmer.
NOTE

Bit 4 of the PSW can only be set indirectly by executing an RTI or RTT
instruction with the desired PSW on the stack.
NOTE

The traced instruction is the instruction after the one that sets the T·bit.
The following are special cases of the T-bit:
1. An instruction that clears the T-bit-Upon fetching the traced instruction, an internal
flag-the trace flag-is set. The trap still occurs at the end of this instruction. The
PSW on the stack, however, has a clear T-bit.
2. An instruction that sets the T-bit-Since the T-bit is already set, setting it again has
no effect. The trap still occurs.
3. An instruction that causes an instruction trap-The instruction trap is performed
and the entire routine for the service trap is executed. If the service routine exits
with an RTI, or in any other way restores the stacked PSW, the T-bit is set again, the
instruction following the traced instruction is executed, and, unless it is one of the
special cases noted previously, a trace trap occurs.
4. An instruction that causes a stack overflow -The instruction completes execution as
usual. The stack overflow does not cause a trap. The trace trap vector is loaded into
the PC and PSW and the old PC and PSW are pushed onto the stack. Stack overflow
occurs again, and this time the trap is made.
5. An interrupt between setting the T-bit and fetching the traced instruction - The
entire interrupt service routine is executed and then the T-bit is set again by
the exiting RTI. The traced instruction is executed (if there have been no other
interrupts), and, unless it is a special case noted in steps 1 through 4, a trace trap
occurs.
6. Interrupt trap priorities-See Table 1-6.

Base Instruction Set -8-65

8.8 Miscellaneous Instructions
HALT
Halt

000000

1 0: 0;0:0:0:0;0;0;0:0;0;0:«0:01
MA·1270·90.0G

Figure 8-86
Operation:

Halt

! (SP)+- PSW
l (SP)+- PC
PC~ restart address
PSW+- 340

Condition Codes:

Not affected

Description:

The effect of HALT depends upon the CPU operating mode and the state of
the trap-on-halt option (bit 3) in the maintenance register. Execution of the
HALT instruction in kernel mode with the trap-on-halt option cleared causes
the CPU to end the execution of instructions after the current instruction
and enter the DCJll micro-ODT mode. Execution of the HALT instruction in
kernel mode with the halt-on-trap option set, or at any time in supervisor or
user modes, causes a trap through virtual address 4 and also sets bit 7 of the
CPU error register.

NOTE

DMA activity may continue whne the CPU is halted, even if the Halt switch is
on.

NOTE

The state of the halt-on-trap option has no effect on the operation of the Halt
switch located on the operator console panel.

8-66 Base Instruction Set

WAIT
Wait For Interrupt

000001

1°»»»;0:°;0»»:< I
MA·1271·90.DG

Figure 8-87 . Walt for Interrupt
Condition Codes:

Not affected

Description:

The WAIT instruction allows the processor to relinquish the bus while it
waits for an interrupt. During this time the processor does not compete for
instructions or operands from memory. This may permit higher transfer rates
between devices and memory, since there are no processor induced latencies
by requests from the devices.
In WAIT, as in all instructions, the PC points to the next instruction following
the WAIT instruction. Thus, when an interrupt causes the PC and PSW to be
pushed onto the processor stack, the address of the next instruction following
the WAIT is saved. The exit from the interrupt routine causes resumption
of the interrupted process at the instruction following the WAIT. The WAIT
instruction executes as an NOP in supervisor and user modes.

RESET
Reset External Bus

000005

I°:°:°:°:°:°:°:°:°:°:°:°:0: : 0:

MA·1272·90.DG

Figure 8-88

Reset External Bus

Condition Codes:

Not affected

Description:

The following sequence of events occurs: (1) a general purpose write cycle is
performed and a general purpose code of 014 is generated; (2) operation is
delayed for 69 microcycles; (3) a general purpose write is performed and a
general purpose code of 214 is generated; and (4) operation is delayed for 600
microcycies. If not in kernel mode, RESET operates as an NOP.

Base Instrudion Set 8-67

MFPT
·000007

Move from Processor Type Word
15

MA-1273-90.DG

Figure 8-89

Move from Processor 'TYpe Word

Operation:

R+-5

Condition Codes:

Not affected

Description:

The number 5 is placed in R, indicating to the operating system software that
the processor type is a KDJ11-E.

MTPDIMTPI
Move to Previous Data Space (Bit 15=1)
Move to Previous Instruction Space (Bit 15=0)
15

[B)066DD
07

MA-1274-90.DG

Figure &-90 Move to Previous Data Space (Bit 15
Move to Previous Instruction Space (Bit 15 = 0)
Operation:

=1)

(temp)+- (SP)+
(DST)+- (temp)

Condition Codes:

N: set if the source < 0
Z: set if the source = 0
V: cleared
Z: unaffected

Description:

The instruction pops a word off the current stack determined by PSW <15:14>
and stores that word in an address in the previous space (PSW <13:12». The
destination address is computed using the current registers and memory map.

8-68 Base Instruction Set

MFPDIMFPI
Move From Previous Data Space (Bit 15=1)
Move From Previous Instruction Space (Bit 15=0)

[B]065SS

MA·1275-90.DG

Figure 8-91 Move from Previous Data Space (Bit 15 = 1)
Move from Previous Instruction Space (Bit 15 0)

Operation:

(temp)+- (src)
-(SP)+- (temp)

Condition Codes:

N: set if the source < 0
Z: set if the source = 0
V: cleared
Z: unaffected

Description:

Pushes a word onto the current stack from an address in the previous
space determined by PSW <13:12>. The source address is computed using
the current registers and memory map. When MFPI is executed and both
previous mode and current mode are user, the instruction functions as though
it were MFPD.

Base Instruction Set -8-69

8.9 Condition Code Operators
The op codes that can be used to set/clear condition codes, either independently or ORed
together, are as follows:
Condition Code Operators

002XX

MA·1278·90.DG

Figure 8-92
Description:

Condition Code Operators
Set and clear condition code bits. Selectable combinations of these bits may
be cleared or set together. Condition code bits corresponding to bits in the
condition code operator (bits <3:0» are modified according to the sense of bit
4, the set/clear bit of the operator. That is, set the bit specified by bit 0, 1, 2,
or 3, if bit 4 = 1. Clear corresponding bits if bit 4 = o.

Mnemonic

Operation

Op Code

CLC

Clear C

000241

CLV

Clear V

000242

CLZ

Clear Z

000244

CLN

Clear N

000250

SEC

SetC

000261

SEV

Set V

000262

SEZ

SetZ

000264

SEN

SetN

000270

SCC

Set all CCs

000277

CCC

Clear all CCs

000257

Clear V and C

000243

No operation

000240

NOP

Combinations of the above set and clear operations may be ORed together to form
combined instructions.

9
Floating-Point Arithmetic

9.1 Introduction
The KDJ11-E executes 46 floating-point instructions. The floating-point instruction set
is compatible with the FP11 instruction set for PDP-11 computers. Both single- and
double-precision floating-point capabilities are available with other features, including
f1oating-to-integer and integer-to-f1oating conversion.

9.2 Floating-Point Data Formats
Mathematically, a floating-point number may be defined as having the form (2 ** K) * f,
where K is an integer and f is a fraction. For a nonvanishing number, K and fare
uniquely determined by imposing the condition 112 < f < 1. The fractional part (f) of the
number is then said to be normalized. For the number 0, f is assigned the value 0, and
the value of K is indeterminate.
The floating-point data formats are derived from this mathematical representation for
floating-point numbers. Two types of floating-point data are provided. In single-precision,
or floating mode, the data is 32 bits long. In double-precision, or double mode, the data is
64 bits long. Sign magnitude notation is used.

9.2.1 Nonvanishing Floating-Point Numbers
The fractional part (f) is assumed to be normalized, so that its most significant bit
must be 1. This 1 is the hidden bit. It is not stored explicitly in the data word, but
the microcode restores it before carrying out arithmetic operations. The floating and
double modes reserve 23 and 55 bits, respectively, for f. These bits, with the hidden bit,
imply effective word lengths of 24 bits and 56 bits.
Eight bits are reserved for storage of the exponent K in excess 200 notation (that is,
as K + 200 octal), giving a biased exponent. Thus, exponents from -128 to +127 may
be represented by 0 to 377 (base 8), or 0 to 255 (base 10). For reasons described in the
following section, a biased exponent of 0 (the true exponent of -200 octal) is reserved for
floating-point O. Therefore, exponents are restricted to the range -127 to +127 inclusive
(-177 to +177 octal) or, in excess 200 notation, 1 to 377.
The remaining bit of the floating-point word is the sign bit. The number is negative if the
sign bit is a 1.

9-1

9-2

Floating-Point Arithmetic

9.2.2 Floating-Point Zero
Because of the hidden bit, the fractional part is not available to distinguish between 0
and nonvanishing numbers whose fractional part is exactly 112. Th.erefore, the KDJ11-E
reserves a biased exponent of 0 for this purpose, and any floating-point number with
a biased exponent of 0 either traps or is treated as if it were an exact 0 in arithmetic
operations. An exact or clean 0 is represented by a word whose bits are all Os. A dirty 0
is a floating-point number with a biased exponent of 0 and a nonzero fractional part.
An arithmetic operation for which the resulting true exponent exceeds 177 octal is
regarded as producing a floating overflow; if the true exponent is less than -177 octal, the
operation is regarded as producing a floating underflow. A biased exponent of 0 can thus
arise from arithmetic operations as a special case of overflow (true exponent = 200 octal).
(Recall that only eight bits are reserved for the biased exponent.) The fractional part of
results obtained from such overflow and underflow is correct.

9.2.3 Undefined Variables
An undefined variable is any bit pattern with a sign bit of 1 and a biased exponent of

O. The term undefined variable is used, for historical reasons, to indicate that these bit
patterns are not assigned a corresponding floating-point arithmetic value. Note that the
undefined variable is frequently referred to as -0 elsewhere in this chapter.
A design objective was to ensure that the undefined variable would not be stored as the
result of any floating-point operation in a program run with the overflow and underflow
interrupts disabled. This is achieved by storing an exact 0 on overflow and underflow if
the corresponding interrupt is disabled. This feature, together with an ability to detect
reference to the undefined variable (implemented by the FIUV bit discussed later), is
intended to provide the user with a debugging aid: if -0 occurs, it did not result from a
previous floating-point arithmetic instruction.

9.2.4 Floating-Point Data
Floating-point data is stored in words of memory as illustrated in Figure 9-1 and
Figure 9-2.
The KDJ11-E provides for conversion of floating-point to integer format and vice versa.
The processor recognizes single-precision integer (I) and double-precision integer long (L)
numbers, which are stored in standard 2's complement form (Figure 9--3).

9.3 Floating-Point Status Register (FPS)
The floating-point status register (FPS) provides mode and interrupt control for the
currently executing floating-point instruction and also reflects conditions resulting from
the execution of the previous instruction (Figure 9-4). In this discussion a set bit = 1 and
a reset bit =O. Three bits of the FPS register control the modes of operation as follows:
Single/Double -Floating-point numbers can be either single- or double-precision.
Long/Short-Integer numbers can be 16 bits or 32 bits.
Chop/Round -The result of a floating-point operation can be either chopped or rounded.
The term chop is used instead of truncate to avoid confusion with truncation of series
used in approximations for function subroutines.
The FPS register contains an error flag and four condition codes (5 bits): carry, overflow,
zero, and negative, which are analogous to the CPU condition codes.

Floating-Point Arithmetic - 9-3

F Format, Floating-Point Single Precision
15

::::::I
15

: : : I :

MA-1277-90.0G

Figure 9-1

Single-Precision Format

o Format, Floating-Point Double Precision
15

I : : : : : : ~~+15:~ : : : : : : I
15

I : : : : : : Fr~:<31+ : : : : : : I
15

::::::I
15

S.Sign of fraction
Exp=Exponent in excess 200 notation, restricted to 1 to 377 octal
for nonvanishing numbers.
Fraction=23 bits in F format, 55 bits in 0 format plus one hidden
bit(normalization). The binary radix point is to the left.
MA-1278-90.00

Figure 9-2

Double-Precision Fonnat

9-4 Floating-Point Arithmetic

I Format, Short-Integer Double Precision
15

I I : : : : : +b+1S+ : : : :: : I
L Format, Long-Integer Double Precision
15

::::::I
15

S=Sign of number
Number=15bits in I format, 31 bits in L format
MA-1279-90.DG

Figure 9-3
15

2's Complement Format
14

FIV

FIC

Reserved
MA-1280-90.DG

Figure 9-4

Floating-Point Status Register

The KDJ11-E recognizes the following six floating-point exceptions:
•

Detection of the presence of the undefined variable in memory

•

Floating overflow

•

Floating underflow

•

Failure of floating-to-integer conversion

•

Attempt to divide by 0

•

Illegal floating op code

For the first four of these exceptions, bits in the FPS register are available to individually
enable and disable interrupts. An interrupt on the occurrence of either of the last two
exceptions can be disabled only by setting a bit that disables interrupts on all six of the
exceptions as a group.

Of the 13 FPS bits, 5 are set as part of the output of a floating-point instruction: the
error flag and condition codes. Any of the mode and interrupt control bits may be set by
the user; the LDFPS instruction is available for this purpose. These 13 bits are stored in
the FPS register (Figure 9-4). Table 9-1 describes the FPS register bits.

Floating-Point Arithmetic 9-5

Table 9-1

FPS Register Bit Descriptions

Bit

Name

Function

FER

The floating error (FER) bit is set by the DCJ11 if:
1.

Division by zero occurs

An illegal op code occurs

Anyone of the remaining floating-point exceptions occurs and
the corresponding interrupt is enabled

Note that the above action is independent of whether the FID bit is
set or clear.
Note also that the DCJ11 never resets the FER bit. Once the
FER bit is set by the DCJ11, it can be cleared only by an LDFPS
instruction. (The RESET instruction does not clear the FER bit.)
This means that the FER bit is up to date only if the most recent
floating-point instruction produced a floating-point exception.

FID

If the FID bit is set, all floating-point interrupts are disabled

NOTE
The FlO bit is primarily a maintenance feature. It is normally clear and must be clear if
you want to ensure that storage of -0 by the DCJll is accompanied by an interrupt.

Throughout the rest of this chapter, assume that the FID bit is clear in all discussions
involving overftow, underflow, occurrence of -0, and integer conversion errors.

13
12

Reserved

Reserved for future use.

Reserved

Reserved for future use.

FIUV

An interrupt occurs if FIUV is set and a --0 is obtained from memory

as an operand of ADD, SUB, MUL, DIv,. CMP, MOD, NEG, ABS,
TST, or any LOAD instructions. When FIUV is reset, --0 can be
loaded and used in any floating-point operation.
Note that the interrupt is not activated by the presence of --0 in an
accumulator operand of an arithmetic instruction. In particular,
trap on -0 never occurs in mode O. A result of --0 is not stored
without the simultaneous occurrence of an interrupt.

FlU

When the FlU bit is set, floating underflow causes an interrupt. The
fractional part of the result of the operation causing the interrupt
is correct. The biased exponent is too large by 400, except for the
special case of 0, which is correct. A special case is discussed later
in the description of the LDEXP instruction.

FIV

When the FIV bit is set, floating overflow causes an interrupt. The
fractional part of the result of the operation causing the overflow is
correct. The biased exponent is too small by 400.
If the FIV bit is reset and overflow occurs, there is no interrupt.
The DCJ11 returns exact O.
Special cases of overflow are discussed later in the detailed
descriptions of the MOD and LDEXP instructions.

9-6 Floating-Point Arithmetic

Table 9-1 (Cont.) FPS Register Bit Descriptions
Bit

Name

Function

FIe

When the FIe bit is set and a conversion to integer instruction fails,
an interrupt occurs. When the interrupt occurs, destination is set to
o and all other registers are left untouched.
If the FIe bit is reset, the result of the operation is the same as that
detailed previously, but no interrupt occurs.
The conversion instruction fails ifit generates an integer with more
bits than can fit in the short or long integer word specified by the
FL bit.

The FD bit determines the precision that is used for floating-point
calculations. When set, double-precision is assumed. When reset,
single-precision is used.

The FL bit is active in conversion between integer and floating-point
formats. When set, the integer format assumed is doubled-precision
2's complement (32 bits). When reset, the integer format assumed
is single-precision 2's complement (16 bits).

When the FT bit is set, the result of any arithmetic operation is
chopped (truncated). When reset, the result is rounded.

Reserved

Reserved for future use.

FN is set if the previous floating-point operation result was
negative; otherwise it is reset.

FZ is set if the previous floating-point operation was 0; otherwise it
is reset.

FV is set if the previous floating-point operation in an exponent
overflow; otherwise it is reset.

Fe is set if the previous floating-point operation resulted in a carry
of the most significant bit.

9.4 Floating Exception Code and Address Registers
One interrupt vector is assigned to take care of all floating-point exceptions (location 244).
The six possible errors are coded in the 4-bit Floating Exception Code (FEe) register as
follows:

Code

Exception

Floating op code error

Floating divide by zero error

Floating-to-integer or double-to-integer conversion error

Floating overflow error

Floating underflow error

Floating undefined variable error

Floating-Point Arithmetic - 9-7

The address of the instruction producing the exception is stored in the Floating Exception
Address (FEA) register.
The FEC and FEA registers are updated only when one of the following occurs.
•

Division by zero

•

Illegal op code

•

Any of the other four exceptions with the corresponding interrupt enabled

This implies that the FEe and FEA registers are updated only when the FER bit is set.

NOTE

1. If one of the last four exceptions occurs with the corresponding interrupt
disabled, the FEe and FEA are not updated.
2. If an exception occurs, inhibition of interrupts by the FID bit does not inhibit
updating of the FEe and FEA.
3. The FEe and FEA are not updated if no exception occurs. This means that
the store status (STST) instruction returns current information only if the most
recent floating-point instruction produced an exception.
4. Unlike the FPS, no instructions are provided for storage into the FEe and
FEA registers.

9.5 Floating-Point Instruction Addressing
Floating-point instructions use the same type of addressing as the central processor
instructions. A source or destination operand is specified by designating one of eight
addressing modes and one of eight central processor general registers to be used in the
specified mode. The modes of addressing are the same as those of the central processor,
except in mode O. In mode 0, the operand is located in the designated floating-point
processor accumulator rather than in a central processor general register. The modes of
addressing are as follows:

o =Floating-point accumulator
1 = Deferred
2 =Autoincrement
3 =Autoincrement-deferred
4 =Autodecrement
5 =Autodecrement-deferred
6 =Index
7 = Index-deferred
Autoincrement and autodecrement operate on increments and decrements of 4 for F
format, and 10 (octal) for D format.
In mode 0, all six floating-point accumulators (ACO-AC5) may be used as source or
destination. Specifying floating-point accumulators AC6 or AC7 results in an illegal
op code trap. In all other modes, which involve transfer of data to or from memory or
the general registers, users are restricted to the first four floating-point accumulators
(ACO-AC3). When reading or writing a floating-point number to or from memory, the low
memory word contains the most significant word of the floating-point number, and the
high memory word contains the least significant word.

9-8 Floating-Point· Arithmetic

9.6 Accuracy
General comments on the accuracy of the KDJI1-E floating-point instructions are
presented here. The descriptions of the individual instructions include the accuracy
at which they operate. An instruction or operation is regarded as exact if the result is
identical to an infinite precision calculation involving the same operands. The accuracy of
the operands is thus ignored. All arithmetic instructions treat an operand whose biased
exponent is 0 as an exact 0 (unless FIUV is enabled and the operand is -0, in which
case an interrupt occurs). For all arithmetic operations except DIY, a 0 operand implies
that the instruction is exact. The same statement holds for DIV if the 0 operand is the
dividend. But if it is the divisor, division is undefined and an interrupt occurs.
For nonvanishing floating-point operands, the fractional part is binary normalized. It
contains 24 bits or 56 bits for floating mode and double mode, respectively. For ADD,
SUB, MUL, and DIV, two guard bits are necessary and sufficient for the general case.
This guarantees return of a chopped or rounded result, identical to the corresponding
infinite precision operation (chopped or rounded), to the specified word length. Thus,
with two guard bits, a chopped result has an error bound of one Least Significant Bit
(LSB); a rounded result has an error bound of 1/2 LSB. These error bounds are realized
by the KDJII-E for all instructions.
In the rest of this chapter, an arithmetic result is called exact if no nonvanishing bits
would be lost by chopping. The first bit lost in chopping is referred to as the rounding
bit. The value of a rounded result is related to the chopped result as follows:
1. If the rounding bit is 1, the rounded result is the chopped result incremented by a
LSB.
2. If the rounding bit is 0, the rounded and chopped results are identical.

It follows that if the result is exact:

Rounded value =chopped value =exact value.
If the result is not exact, its magnitude is
•

always decreased by chopping

•

decreased by rounding if the rounding bit is 0

•

increased by rounding if the rounding bit is 1

Occurrence of floating-point overflow and underflow is an error condition; the result
of the calculation cannot be correctly stored because the exponent is too large to fit
into the eight bits reserved for it. However, the internal hardware has produced the
correct answer. In the case of underflow, replacement of the correct answer with 0 is a
reasonable resolution of the problem for many applications. This is done by the KDJ11-E
if the underflow interrupt is disabled. The error incurred by this action is an absolute
rather than a relative error; it is bounded (in absolute value) by 2 ** -128. There is no
such -simple resolution for the case of overflow. The action taken, if the overflow interrupt
is disabled, is described under FIV (bit 09) in Table 9-1.

Floating-Point Arithmetic 9-9

The FIV and FlU bits (of the floating-point status word) provide users with an
opportunity to implement their own correction of an overflow or underflow condition. If
such a condition occurs and the corresponding interrupt is enabled, the microcode stores
the fractional part and the low eight bits of the biased exponent. When the interrupt
takes place, users can identify the cause by examination of the floating overflow (FV) bit
or the FEC. The reader can readily verify that (for the standard arithmetic operations
ADD, SUB, MUL, and DIV) the biased exponent returned by the instruction bears the
following relation to the correct exponent:
•

On overflow, it is too small by 400 (octal).

•

On underflow, if the biased exponent is 0, it is correct. If the biased exponent is not
0, it is too large by 400 (octal).

Thus, with the interrupt enable, enough information is available to determine the correct
answer. Users may, for example, rescale their variables (by using STEXP and LDEXP) to
continue a calculation. Note that the accuracy of the fractional part is unaffected by the
occurrence of underflow or overflow.

9.7 Floating-Point Instructions
Each instruction that references a floating-point number can operate on either single- or
double-precision numbers, depending on the state of the FD mode bit. Similarly, there is
an FL mode bit that determines whether a 32-bit integer (FL = 1) or a 16-bit integer (FL
=0) is used in conve~sion between integer and floating-point representations. FSRC and
FDST operands use floating-point addressing modes (Figure 9-5); SRC and DST operands
use CPU addressing modes.

Double-Operand Addressing

Single-Operand Addressing

I : +: I : : +: : I +C'fDST;SRC,:DS<
15

OC",Opcode= 17
FOC=Floating opcode
AC=Floating point accumulator (ACO, AC3)
FSAC and DST use CPU addressing modes
SAC and DST use CPU addressing modes
MA-1281-90.DG

Figure 9-5

Floating-Point Addressing Modes

9-10

Floating-Point Arithmetic

9.7.1 Terms Used in Instruction Definitions
The following paragraphs provide a list of the tenns used in instruction definitions, as
well as explanations of and figures for each instruction.
Thrms
Used in
Instruction
Definitions
OC = op code = 17
FOC = floating op code
AC = contents of accumulator, as specified by AC field of instruction
FSRC = address of floating-point source operand
FDST = address of floating-point destination operand
f = fraction '
XL = largest fraction that can be represented:
1 -

2 ** ( -24), FD =0; single-precision

1 - 2 ** ( -56), FD = 1; double-precision
XLL = smallest number that is not identical to zero =
2 ** (-128)

XUL =largest number that can be represented =
2 ** (127) * XL
JL = largest integer that can be represented:

2 ** (15) -

1; FL = 0; short integer

2 ** (31) -

1; FL = 1; long integer

ABS (address) = absolute value of (address)
EXP (address) = biased exponent of (address)
.LT. = less than
.LE. = less than or equal to
.GT. = greater than
.GE.

=greater than or equal to

LSB = least significant bit

Boolean
Symbols

,,= AND
V = inclusive OR

'V = exclusive OR
'" = NOT

Floating-Point Arithmetic -9-11

ABSF/ABSD
1706 FOST

Make Absolute Floating/Double
15

I : : : 1«< : >1 : :
MA·1282·90.DG

Figure 9-6

Make Absolute Floating/Double

Format:

ABSF FDST

Operation:

If (FDST) < O,(FDST) +-

(FDST).

If EXP(FDST) =0, (FDST) +- exact O.

For all other cases, (FDST) +- (FDST).
Condition Codes:

FC+-O
FV+-O
FZ +- 1 if (FDST) = 0, else FZ +- 0
FN+-O

Description:

Set the contents of FDST to its absolute value.

Interrupts:

If FIUV is enabled, trap on -0 occurs before execution. Overflow and
underflow cannot occur.

Accuracy:

These instructions are exact.

9-12. Floating-Point Arithmetic

ADDF/ADDD
172(AC)FSRC

Add Floating/Double
12

I : : : I : : : I + I : : F~RC : : I
0

MA·1283·90.DG

Figure 9-7

Add Floating/Double

Format:

ADDF FSRC,A.C

Operation:

Let SUM = (AC) + (FSRC).
If underflow occurs and FlU is not enabled, AC +-- exact o.
If overflow occurs and FIV is not enabled, AC +-- exact o.
For all others cases, AC +-- SUM.

Condition Codes:

FC +-- 0
FV +-- 1 if overflow occurs, else FV +-- 0
FZ +-- 1 if (AC) = 0, else FZ +-- 0
FN +-- 1 if (AC) < 0, else FN +-- 0

Description:

Add the contents of FSRC to the contents of AC. The addition is
carried out in single- or double-precision and is rounded or chopped
in accordance with the values of the FD and FT bits in the FPS
register. The result is stored in AC except for:
Overflow with interrupt disabled
Underflow with interrupt disabled
For these exceptional cases, an exact 0 is stored in AC.

Interrupts:

If FIUV is enabled, trap on --0 in FSRC occurs before execution. If
overflow or underflow occurs, and if the corresponding interrupt is
enabled, the trap occurs with the faulty result in AC. The fractional
parts are correctly stored. The exponent part is too small by 400 for
overflow. It is too large by 400 for underflow, except for the special
case of 0, which is correct.

Accuracy:

Errors due to overflow and underflow are described above. If neither
occurs, then for oppositely signed operands with exponent difference
of 0 or 1, the answer returned is exact if a loss of significance of one
or more bits can occur. Note that these are the only cases for which
loss of significance of more than one bit can occur. For all other cases
the result is inexact with error bounds of:
LSB in chopping mode with either single- or double-precision
1/2 LSB in rounding mode with either single- or double-precision

Special Comment:

The undefined variable 0 can occur only in conjunction with overflow
or underflow. It is stored in AC only if the corresponding interrupt is
enabled.

Floating-Point Arithmetic 9-13

CFCC
Copy Floating Condition Codes
15

170000

I : : : 1°;0;0»:««<0;°1
MA-1284-90.DG

Figure 9-8

Copy Floating Condition Codes

Format:

CFCC

Operation:

C +- FC
V+-FV
Z+-FZ
N+-FN

Description:

Copy the floating-point condition codes into the CPU condition codes.

CLRF/CLRD
Clear Floating/Double
15

.12

1704 FDST
11

MA-1285-90.DG

Figure 9-9

Clear Floating/Double

Format:

CLRF FDST

Operation:

(FDST) +- exact 0

Condition Codes:

FC+-O
FV+-O
FZ +--1

FN+-O

Description:

Set FDST to O. Set FZ condition code and clear other condition code
bits.

Interrupts:

No interrupts occur. Overflow and underflow cannot occur.

Accuracy:

These instructions are exact.

9-14 Floating-Point Arithmetic

CMPF/CMPD
173(AC+4)FSRC

Compare Floating/Double
15

: : I : : : I
0

+ I : : F~ : : I
MA-1288-90.DG

Figure 9-10

Compare Floating/Double

Fonnat:

CMPF FSRC,AC

Operation:

(FSRC) - (AC)

Condition Codes:

FC+-O
FV+-O
FZ +- 1 if (FSRC) = 0, else FZ +- 0
FN +- 1 if (FSRC) < 0, else FN +- 0

Description:

Compare the contents of FSRC with the accumulator. Set
the appropriate floating-point condition codes. FSRC and the
accumulator are left unchanged except as noted later.

Interrupts:

If FIUV is enabled, trap on -0 occurs before execution.

Accuracy:

These instructions are exact.

Special Comment:

An operand that has a biased exponent of 0 is treated as if it were an
exact O. In this case, where both operands are 0, the KDJI1-E stores
an exact 0 in AC.

Floating-Point Arithmetic ·9-15

DIVFIDIVD
174(AC+4)FSRC

Divide Floating/Double
15

I : : : I ;0: 0; I + I : :

MA-1287-90.0G

Figure 9-11

Divide Floating/Double

Format:

DIVF FSRC,AC

Operation:

If EXP(FSRC) = 0, (AC) +- (AC) and the instruction is aborted.

If EXP(AC) =0, (AC) +- exact O.
For all other cases, let QUOT = (AC)I(FSRC).
If underflow occurs and FlU is not enabled, AC +- exact O.
If overflow occurs and FIV is not enabled, AC +- exact O.

For all others cases, AC +- QUOT.
Condition Codes:

FC+-O
FV +- 1 if overflow occurs, else FV +- 0
FZ +- 1 if (AC) = 0, else FZ +- 0
FN +- 1 if (AC) < 0, else FN +- 0

Description:

If either operand has a biased exponent of 0, it is treated as an
exact O. For FSRC this would imply division by 0; in this case, the
instruction is aborted, the FEC register is set to 4, and an interrupt
occurs. Otherwise, the quotient is developed to single- or doubleprecision with two guard bits for correct rounding. The quotient is
rounded or chopped in accordance with the values of the FD and FT
bits in the FPS register. The result is stored in the AC except for

Overflow with interrupt disabled
Underflow with interrupt disabled
For these exceptional cases, an exact 0 is stored in AC.
Interrupts:

If FIUV is enabled, trap on 0 in FSRC occurs before execution. If
(FSRC) = 0, interrupt traps occur on an attempt to divide by O. If
overflow or underflow occurs, and if the corresponding interrupt is
enabled, the trap occurs with the faulty result in AC. The fractional
parts are correctly stored. The exponent part is too small by 400 for
overflow. It is too large by 400 for underflow, except for the special
case of 0, which is correct.

Accuracy:

Errors due to overflow and underflow are described previously. If
no underflow or overflow errors occur, the error in the quotient is
bounded by 1 LSB in chopping mode and by 112 LSB in rounding
mode.

Special Comment:

The undefined variable -0 can occur only in conjunction with overflow
or underflow. It is stored in AC only if the corresponding interrupt is
enabled.

9-16 Floating-Point Arithmetic

LDCDFILDCFD
Load and Convert from Double-to-Floatlng
and from Floatlng-to-Double

(5 : '

12111

177(AC+4)FSRC

>>: 1 +1
08

05 :

+< : I
00

MA·128a·80.DG

Figure 9-12 Load and Convert From Double-To-Floating
and from Floatlng-to-Double
Format:

LDCDF FSRC,AC

Operation:

If EXP(FSRC) = 0, AC +- exact o.
If FD = 1, FT = 0, FIV = 0 and rounding causes overflow, AC +exact O.

In all other cases, AC +- Cx:y(FSRC), where Cxy specifies conversion
from floating mode x to floating mode y.
x = D, y = F if FD = 0 (single) LDCDF
y = F, y = D if FD = 1 (double) LDCFD
Condition Codes:

FC+-O
FV +- 1 if conversion produces overflow, else
FV+-O
FZ +- 1 if (AC) = 0, else FZ +- 0
FN +- 1 if (Ae) < 0, else FN +- 0

Description:

If the current mode is floating mode (FD =0), the source is assumed
to be a double-precision number and is converted to single-precision.
If the floating chop bit (FT) is set, the number is chopped; otherwise,
the number is rounded.
If the current mode is double mode (FD = 1), the source is assumed
to be a single-precision number and is loaded left-justified in AC. The
lower half of AC is cleared.

Interrupts:

If FIUV is enabled, trap on -0 occurs before execution. Overflow
cannot occur for LDCFD.
A trap occurs if FIV is enabled and if rounding with LDCDF causes
overflow. AC +- overflowed result. This result must be +0 or -0.
Underflow cannot occur.

Accuracy:

LDCFD is an exact instruction. Except for overflow (see above),
LDCDF incurs an error bounded by 1 LSB in chopping mode and by
1/2 LSB in rounding mode.

Floating-Point Arithmetic 9-17

LDCIFILDCIDILDCLFILDCLD
load and Convert Integer or Long Integer
to Floating or Double-Precision
15

177(AC)SRC
08

sF: : I
MA·12811·90.DG

Figure 9-13 Load and Convert Integer or Long Integer
to Floating or Double-Precision
Fonnat:

LDCIF SRC,AC

Operation:

AC +-- Cjx(SRC), where Cjx specifies conversion from integer mode j
to floating mode x.
j = I if FL = 0, j = L if FL = 1
x = F if FD = 0, x = D if FD = 1

Condition Codes:

FC +-- 0
FV +-- 0

FZ +-- 1 if (AC) = 0, else FZ +-- 0
FN +-- 1 if (AC) < 0, else FN +-- 0
Description:

Conversion is perfonned on the contents of SRC from a 2's
complement integer with precision j to a floating-point number of
precision x. Note that j and x are determined by the state of the
mode bits FL and FD.
If a 82-bit integer is specified (L mode) and (SRC) has an addressing
mode of 0 or immediate addressing mode is specified, the 16 bits of
the source register are left-justified and the remaining 16 bits are
loaded with Os before conversion.

In the case of LDCLF, the fractional part of the floating-point
representation is chopped or rounded to 24 bits for FT = 1 or 0,
respectively.
Interrupts:

None. SRC is not floating-point, so trap on -0 cannot occur.

Accuracy:

LDCIF, LDCID, and LDCLD are exact instructions. The error
incurred by LDCLF is bounded by 1 LSB in chopping mode and
by 1/2 LSB in rounding mode.

9-18

Floating-Point Arithmetic

LDEXP
176(AC+4)SRC

Load Exponent

: : I : : : I
0

Figure 9-14

I :

: s~c : : I
MA-129D-90.DG

Load Exponent

Format:

LDEXP SRC,AR

Operation:

(Note that 177 and 200, appearing throughout this instruction
definition, are octal numbers.)
If -200 < SRC < 200, EXP +- (AC) SRC + 200 and the rest of AC is
unchanged.
If (SRC) > 177 and FIV is enabled, EXP(AC) +- [(SRC) + 200]<7:0>.
If (SRC) > 177 and FIV is disabled, AC +- exact O.
If (SRC) < 177 and FlU is enabled, EXP(AC) +- [(SRC) + 200]<7:0>.
If (SRC) < 177 and FlU is disabled, AC +- exact o.

Condition Codes:

FC +-0
FV +- 1 if (SRC) > 177, else FV +- 0
FZ +- 1 if (AC) =0, else FZ +- 0
FN +- 1 if (AC) < 0, else FN +- 0

Description:

Change AC so that its unbiased exponent = (SRC). That is, convert
(SRC) from 2's complement to excess 200 notation and insert it into
the EXP field of AC. This is a meaningful operation only if ABS(SRC)
LE 177.
If SRC > 177, the result is treated as overflow. If SRC < -177, the
result is treated as underflow.

Interrupts:

No trap on -0 in AC occurs, even if FIUV is enabled. If SRC > 177
and FIV is enabled, trap on overflow occurs. If SRC <-177 and FlU
is enabled, trap on underflow occurs.

Accuracy:

Errors due to overflow and underflow are described previously. If
EXP(AC) = 0 and (SRC) = -200, AC changes from a floating-point
number treated as 0 by all floating arithmetic operations to a nonzero
number. This happens because the insertion of the hidden bit in the
microcode implementation of arithmetic instructions is triggered by a
nonvanishing value of EXP.
For all other cases, DDEXP implements exactly the transformation
of a floating-point number (2 ** K) * f into (2 ** (SRC» * f where 112
.LE. ABS(f) .LT. 1.

Floating-Point Arithmetic -9-19

LDFILDD
172(AC+4)FSRC

Load Floating/Double

I : : : 1< >: 1 +
Figure 9-15

+< :

MA·1291·91.DG

Load Floating/Double

Fonnat:

LDF FSRC,AC

Operation:

AC +- (FSRC)

Condition Codes:

FC +-0
FV+-O
FZ +- 1 if (AC) = 0, else FZ +- 0
FN +- 1 if (AC) < 0, else FN +- 0

Description:

Load single- or double-precision number into AC.

Interrupts:

If FIUV is enabled, trap on -0 occurs before AC is loaded. Overflow
and underflow cannot occur.

Accuracy:

These instructions are exact.

Special Comment:

These instructions permit use of 0 in a subsequent floating-point
instruction if FIUV is not enabled and (FSRC) = -0.

LDFPS
1701 SRC

Load Floating-Point Program Status

I : : : 1««< I : :
Figure 9-16

MA·1292·90.DG

Load Floating-Point Program Status

Fonnat:

LDFPS SRC

Operation:

FPS +- (SRC)

Description:

Load fioating-PQint status register from SRC.

Special Comment:

Users are cautioned not to use bits 13, 12, and 4 for their own
purposes, since these bits are not recoverable by the STFPS
instruction.

9-20

Floating-Point Arithmetic

MODFIMODD
Multiply and Separate Integer
and Fraction Floating/Double

I:::

11
0

171 (AC+4) FSRC

>: : + I : : +c; : I
00

MA·1203·03.DG

Figure 9-17

Multiply and Separate Integer and Fraction Floating/Double

Format:

MODF FSRC,AC

Description and
Operation:

This instruction generates the product of its two floating-point
operands, separates the product into integer and fractional parts,
and then stores one or both parts as floating-point numbers.
Let PROD = (AC) * (FSRC) so that in
Floating-point: ABS(PROD) = (2 ** K) * f, where
112 .LE. f .LT. 1, and EXP(PROD) = (200 + K).

Fixed-point binary: PROD = N + g, where
N = INT(PROD) = integer part of PROD, and
g = PROD INT(PROD) = fractional.p&rt of
PROD with 0 .LE. g .LT. 1.
Both N and g have the same sign as PROD. They are returned as
follows.
If AC is an even-numbered accumulator (0 or 2), N is stored in AC +
1 (lor 3), and g is stored in AC.
If AC is an odd-numbered accumulator, N is not stored and g is
stored in AC.
These two statements can be combined as:

N is returned to AC V 1 and g is returned to AC.
Five special cases occur, as indicated in the following formal
description with L = 24 for floating mode and L = 56 for double
mode.
1. If PROD overflows and FIV is enabled, AC v+- 1 N, chopped to
L bits, AC +- exact O.

Note that EXP(N) is too small by 400 and that -0 can be stored in
AC V 1.
If FIV is not enabled, AC vI+- exact 0, AC +- exact 0, and -0
will never be stored.
2. If 2 ** L .LE. ABS(PROD) and no overflow, AC VI+- N, chopped
to L bits, AC +- exact O.
The sign and EXPof N are correct, but low-order bit information is
lost.

Floating-Point Arithmetic

9-21

3. If 1 .LE. ABS(PROD) .LT. 2 ** L, AC VI+- N, AC g.
The integer part N is exact. The fractional part g is nonnalized and
chopped or rounded in accordance with FT. Rounding may cause a
return of + unity for the fractional part. For L = 24, the error in g
is bounded by 1 LSB in chopping mode and by 112 LSB in rounding
mode. For L = 56, the error in g increases from the limits above
as ABS(N) increases above 8, because only 59 bits of PROD are
generated.
If 2 ** P .LE. ABS(N) .LT. 2 ** (p + 1), with p > 2, the low order p -2
bits of g may be in error.
4. If ABS(PROD) .LT. 1 and no underflow, AC VI+- exact 0 and
AC +-g.
There is no error in the integer part. The error in the fractional part
is bounded by 1 LSB in chopping mode and 1/2 LSB in rounding
mode. Rounding may cause a return of + unity for the fractional
part.
5. If PROD underflows and FlU is enabled, AC Vi+- exact 0 and
AC +-g.
Errors are as in case 4, except that EXP(AC) is too large by 4008 (if
EXP = 0, it is correct). Interrupt occurs and -0 can be stored in AC.
If FlU is not enabled, AC VI+- exact 0 and AC exact +- O.
For this case the error in the fractional part is less than 2 ** ( -128).
Condition Codes:

FC +-0
FV +- 1 if PROD overflows, else FV +- 0
FZ +- 1 if (AC) = 0, else FZ +- 0
FN +- 1 if (AC) < 0, else FN +- 0

Interrupts:

If FIUV is enabled, trap on 0 in FSRC occurs before execution.
Overflow and underflow are described previously.

Accuracy:

Described previously.

Applicatioi1s~

1. Binary-to-decimal conversion of a proper fraction. The following
algorithm, using MOD, generates decimal digits D(1), D(2). . . from
left to right.

Initialize:

1+-0;

X +- number to be converted;
ABSex) < 1;
While:

X#O

Begin:

PROD +- X * 10;
I +- 1+ 1;
D(I) +- INT(PROD);
X +- PROD INT(PROD);

End.

This algorithrIl is exact. It is case 3 in the description because the number of
nonvanishing bits in the fractional part of PROD never exceeds L, and hence neither
chopping nor rounding can introduce error.
2. 1b reduce the argument of a trigonometric function.
ARG * 2IPI = N + g. The two low bits of N identify the quadrant, and
g is the argument reduced to the first quadrant. The accuracy of N +
g is limited to L bits because of the factor 2IPI. The accuracy of the
reduced argument thus depends on the size of N.

9-22

Floating-Point ~rithmetic

3. '1b evaluate the exponential function e ** x, obtain x * (log e base
2) = N + g, then e ** x = (2 ** N) * (e ** (g * In 2»
The reduced argument is g * ln2 < 1 and the' factor 2 ** N is an exact
power of 2, which may be scaled in at the end via STEXP, ADD N to
EXP and LDEXP. The accuracy of N + g is limited to L bits because
of the factor (log e base 2). The accuracy of the reduced argument
thus depends on the size of N.

MULF/MULD
171 (AC )FSRC

Multiply Floating/Double
15

I : : : I : : : I + I : : FiRe : : I
0

MA-1294-94.DG

Figure 9-18

Multiply Floating/Double

Format:

MULF FSRC,AC

Operation:

Let PROD = (AC) * (FSRC).
If underflow occurs and FlU is not enabled, AC +- exact o.
If overflow occurs and FIV is not enabled, AC +- exact o.
For all others cases, AC +- PROD.

Condition Codes~

FC+-O
FV +- 1 if overflow occurs, else FV +- 0
FZ +- 1 if (AC) = 0, else FZ +- 0
FN +- 1 if (AC) < 0, else FN +- 0

Description:

If the biased exponent of either operand is 0, (AC) +- exact o. For
all other cases PROD is generated to 48 bits for floating mode and 59
bits for double mode. The product is rounded or chopped for FT = 0
or 1, respectively, and is stored in AC except for:
Overflow with interrupt disabled
Underflow with interrupt disabled
For these exceptional cases, an exact 0 is stored in AC.

Interrupts:

If FIUV is enabled, trap on 0 in FSRC occurs before execution. If
overflow or underflow occurs, and if the corresponding interrupt is
enabled, the trap occurs with the faulty result in AC. The fractional
parts are correctly stored. The exponent part is too small by 400 for
overflow. It is too large by 400 for underflow, except for the special
case of 0, which is correct.

Accuracy:

Errors due to overflow and underflow are described above. If neither
occurs, the error incurred is bounded by 1 LSB in chopping mode and
1/2 LSB in rounding mode.

Special Comment:

The undefined variable --0 can occur only in conjunction with overflow
or underflow. It is stored in AC only if the corresponding interrupt is
enabled.

Floating-Point Arithmetic 9-23

NEGFINEGD
Negate Floating/Double
15

1707 FDST

I : : : I a: 0; a: : : I : :

MA-1295-90.DG

Figure 9-19

Negate Floating/Double

Format:

NEGF FDST

Operation:

(FDST) +- - (FDST) if (FDST) = 0 , else (FDST) + - exact O.

Condition Codes:

FC+-O
FV+-O
FZ +- 1 if (FDST) = 0, else FZ +- 0
FN +- 1 if (FDST) < 0, else FN +- 0

Description:

Negate the single- or double-precision number and store result in
same location (FDST).

Interrupts:

If FIUV is enabled, trap on -0 occurs before execution. Overflow and

underflow cannot occur.
Accuracy:

These instructions are exact.

SETD
Set Floating Double Mode

170011

MA-1296-90.DG

Figure 9-20

Set Floating Double mode

Format:

SETD

Operation:

FD +- 1

Description:

Set the KDJII-E in double-precision mode.

9-24

Floating-Point Arithmetic

SETF
Set Floating Mode
15

170001
12

1°»»:«<°:«

MA-1297-90.DG

Figure 9-21
Fonnat:

Set Floating Mode
SETF

Operation:

FD +-- 0

Description:

Set the KDJII-E in single-precision mode.

SETI
Set Integer Mode
15

170002
12

1< : : 1«««««<°1
MA-1298-90.DG

Figure 9-22
Fonnat:
Operation:
Description:

Set Integer Mode
SETI
FL +-- 0
Set the KDJII-E for short-integer data.

SETL
170012

Set Long-Integer Mode
15

MA-1299-90.DG

Figure 9-23

Set long Integer Mode

Fonnat:

SETL

Operation:

FL + - 1

Description:

Set the KDJI1-E for long-integer data.

Floating-Point Arithmetic 9-25

STCFD/STCDF
Store and Convert from Floatlng-to-Double
and from Double-to-Floatlng
12

176(AC)FDST
08

I : : : I : ;0>1 + I : >+< : 1
MA-1300-90.0G

Figure 9-24

Store and Convert from Floating-To-Double and from Double-To-Floating

Format:

STCFD AC, FDST

Operation:

If (AC) = 0, (FDST) exact +- o.
If FD = 1,
exact o.

Fr = 0, FIV = 0 and rounding causes overflow, (FDST) +-

In all other cases, (FDST) +- Cxy(AC), where Cxy specifies
conversion from floating mode x to floating mode y.
x = F, y = D if FD = 0 (single) STCFD
x = D, y = F if FD = 1 (double) STCDF
Condition Codes:

FC+-O
FV +- 1 if conversion produces overflow, else
FV+-O
FZ + - 1 if (AC) = 0, else FZ + - 0
FN +- 1 if (AC) < 0, else FN + - 0

Description:

If the current mode is single-precision, the accumulator is stored
left-justified in FDST and the lower half is cleared.
If the current mode is double-precision, the contents of the
accumulator are converted to single-precision, chopped or rounded
depending on the state of FT, and stored in FDST.

Interrupts:

Trap on -0 does not occur even if FIUV is enabled because FSRC is
an accumulator. Underflow cannot occur. Overflow cannot occur for
STCFD.
A trap occurs if FIV is enabled and if rounding with STCDF causes
overflow. (FDST) +- overflowed result. This result must be +0 or -0.

Accuracy:

STCFD is an exact instruction. Except for overflow (see above),
STCDF incurs an error bounded by 1 LSB in chopping mode and by
1/2 LSB in rounding mode.

9-26

FIQ~ting-Point Arithmetic

STCFVSTCFLSTCDUSTCDL
Store and Convert from Floating or Double
to Integer or Long Integer
15

175(AC+4 )DST
08

I : : : I ;0: : I

I : : +r:: I
LJ·00431· TIO

Figure 9-25

Store and Convert from Floatlng-to-Double To Integer Or Long Integer

Fonnat:

STCFI AC,DST

Operation:

(DST) +- CJd(AC) if-JL - 1 < Cxj(AC) < JL + 1, else (DST) +- 0,
where Cjx specifies conversion from floating mode j to integer mode x.
j =I if FL = 0, j = L if FL = 1

x =F if FD = 0, x =D if FD = 1

JL is the largest integer.
2 ** 15 -1 for FL = 0
2 ** 32 -1 for FL = 1
Condition Codes:

C, FC +- 0 if -JL -1 < CJd(AC) < JL + 1, else
C, FC +--1
V,FV+-O
Z, FZ +- 1 if (DST) = 0, else Z, FZ +-- 0
N, FN +- 1 if (DST) < 0, else N, +- FN +-- 0

Description:

Conversion is perfonned from a floating-point representation of the
data in the accumulator to an integer representation.
If the conversion is to a 32-bit word (L mode), and an addressing
mode of 0 or immediate addressing mode is specified, only the most
significant 16 bits are stored in the destination register.
If the operation is out of the integer range selected by FL, FC is set
to 1 and the contents of the nST are set to O.
N umbers to be converted are always chopped (rather than rounded)
before they are converted. This is true even when chop mode bit FT
is cleared in the FPS register.

Interrupts:

These instructions do not interrupt if FIUV is enabled, because the
-0 (if present) is in AC, not in memory. If FIC is enabled, trap on
conversion failure occurs.

Accuracy:

These instructions store the integer part of the floating-point
operand, which may not be the integer most closely approximating
the operand. They are exact if the integer part is within the range
implied by FL.

Floating-Point Arithmetic 9-27

STEXP
Store Exponent

175(AC)DST

I : : : 1 ;0: >1

+1 : : + : : I
MA-1302-90.0G

Figure 9-26

Store Exponent

Format:

STEXP AC,DST

Operation:

(DST) +- EXP(AC) -200.

Condition Codes:

C,+-FCO
V,FV+-O
Z, FZ +- 1 if (DST) = 0, else Z, FZ +- 0
N, FN +- 1 if (DST) < 0, else N, FN +- 0

Description:

Convert the AC exponent from excess 200 notation to 2's complement
and store the result in DST.

Interrupts:

This instruction does not trap on O. Overflow and underflow cannot
occur.

Accuracy:

This instruction is exact.

STF/STD
Store Floating/Double

I:::
Figure 9-27

174(AC)FDST

>:a >I

I : :

+< : I
00

MA-1303-90.0G

Store Floating/Double

Format:

STF AC,FDST

Operation:

(FDST) +- AC

Condition Codes:

FC +-FC
FV+-FV
FZ +- FZ
FN +- FN

Description:

Store single- or double-precision number from AC.

Interrupts:

These instructions do not interrupt if FIUV is enabled, because the
-0 (if present) is in AC, not in memory. Overflow and underflow
cannot occur.

Accuracy:

These instructions are exact.

Special Comment:

These instructions permit storage of a -0 in memory from AC.
There are two conditions in which -0 can be stored in an AC of the
KDJII-E. One occurs when underflow or overflow is present and the
corresponding interrupt is enabled. A second occurs when an LDF or
LDD instruction is executed and the FIUV bit is disabled.

9-28

Floating-Point Arithmetic

STFPS
Store Floating-Point Program Status

1702DST
06

::I
MA-1304-90,OG

Figure 9-28

Store Floating-Point Program Status

Format:

STFPS DST

Operation:

(DST) .-. FPS

Description:

Store the floating-point status register in DST.

Special Comment:

Bits 13, 12, and 4 are loaded with o. All other bits are the
corresponding bits in the FPS.

STST
1703DST

Store FPP's Status

I : : : 10;«< : 1 : : +: : I
15

MA-1305-90,OG

Figure 9-29

Store FPP's Status

Format:

STST DST

Operation:

(DST) .-. FEC (DST + 2) .-. FEA.

Description:

Store the FEe and FEA in DST and DST + 2. Note the following.
If the destination mode specifies a general register or immediate
addressing, only the FEC is saved.
The information in these registers is current only if the most recently
executed floating-point instruction caused a floating-point exception.

Floating-Point Arithmetic 9-29

SUBF/SUBD
173(AC)FSRC

Subtract Floating/Double

I : : : 1< : >1
MA-1306-90.0G

Figure g.,...ao

Subtract Floating/Double

Format:

SUBF FSRC,AC

Operation:

Let DIFF = (AC) - (FSRC).
If underflow occurs and FlU is not enabled, AC exact +-- o.
If overflow occurs and FIV is not enabled, AC exact +-- o.
For all others cases, AC DIFF.

Condition Codes:

FC +-- 0 FV +-- 1 if overflow occurs, else FV +-- 0
FZ +--·1 if (AC) = 0, else FZ +-- 0
FN +-- 1 if (AC) < 0, else
FN +-- 0

Description:

Subtract the contents of FSRC from the contents of AC. The
subtraction is carried out in single- or double-precision and is
rounded or chopped in accordance with the values of the FD and
FT bits in the FPS register. The result is stored in AC except for:
Overflow with interrupt disabled
Underflow with intenupt disabled
For these exceptional cases, an exact 0 is stored in AC.

Intenupts:

If FIUV is enabled, trap on -0 in FSRC occurs before execution. If
overflow or underflow occurs, and if the corresponding intenupt is
enabled, the trap occurs with the faulty result in AC. The fractional
parts are correctly stored. The exponent part is too small by 400 for
overflow. It is too large by 400 for underflow, except for the special
case of 0, which is correct.

Accuracy:

Errors due to overflow and underflow are described above. If neither
occurs, then for like-signed operands with exponent difference of 0 or
1, the answer returned is exact if a loss of significance of one or more
bits can occur. Note that these are the only cases for which loss of
significance of more than one bit can occur. For all other cases the
result is inexact with error bounds of:
LSB in chopping mode with either single- or double-precision
112 LSB in rounding mode with either single- or double-precision

-Special Comment:

The undefined variable -0 can occur only in conjunction with overflow
or underflow. It is stored in AC only if the corresponding interrupt is
enabled.

9-30

Floating-Point Arithmetic

TSTFtrSTD
1702FDST

Test Floating/Double
15

I: : : 1«< >: I : :F+r: : I
MA·1307·90.DG

Figure 9-31
Format:

Test Floating/Double
TSTF FDST

Operation:

(FDST)

Condition Codes:

FC+- 0
FV+-O

FZ +- 1 if (FDST) = 0, else FZ +- 0
FN +- 1 if (FDST) < 0, else FN +- 0
Description:

Set the floating-point condition codes according to the contents of
FDST.

Interrupts:

If FIUV is set, trap on 0 occurs before execution. Overflow and
underflow cannot occur.

Accuracy:

These instructions are exact.

10
Programming Techniques

10.1 Introduction
The KDJII-E offers a great deal of programming flexibility and power. Using the
combination of the instruction set, the addressing modes, and the programming
techniques, it is possible to develop new software or to use old programs effectively.
The programming techniques in this chapter show the capabilities of the KDJII-E. The
techniques discussed involve PIC, stacks, subroutines, interrupts, reentrancy, coroutines,
recursion, processor traps, programming peripherals, and conversion.

10.2 Position-Independent Code (PIC)
The output of a MACRO-II assembly is a relocatable object module. The task builder
or linker binds one or more modules together to create an executable task image. Once
built, a task can only be loaded and executed at the virtual address specified at link
time. This is because the linker has had to modify some instructions to reflect the
memory locations in which the program is to run. Such a body of code is considered
position-dependent (that is, dependent on the virtual address to which it is bound).
The KDJII-E processor offers addressing modes that make it possible to write
instructions that do not depend on the virtual addresses to which they are bound. This
type of code is termed position-independent and can be loaded and executed at any
virtual address. PIC can improve system efficiency, both in use of virtual address space
and in conservation of physical memory.
In multiprogramming systems like RSX-IIM , it is important that many tasks be able
to share a single physical copy of common code (for example, a library routine). To make
optimum use of the virtual address space of a task, shared code should be positionindependent. Code that is not position-independent can also be shared, but it must
appear in the same virtual locations in every task using it. This restricts the placement
of such code by the task builder and can result in the loss of virtual addressing space.

10.2.1 Use of Addressing Modes in the Construct jon of
Position-Independent Code
The construction of PIC is closely linked to the proper use of addressing modes . The
remainder of this explanation assumes the reader is familiar with the addressing modes
described in Chapter 7.

10-1

10-2 Programming Techniques

The following addressing modes, which involve only register references, are positionindependent:
R

(R)

(R)+

Autoincrement mode

@(R)+

Autoincrement-deferred mode

-(R)

Autodecrement mode

@-(R)

Autodecrement-deferred mode

When employing these addressing modes, the user is guaranteed position independence,
providing the contents of the registers are supplied independently of a particular virtual
memory location.
The following two relative addressing modes are position-independent when a relocatable
address is referenced from a relocatable instruction:
A

Relative mode

Relative-deferred mode

Relative modes are not position-independent when an absolute address (that is, a
nonrelocatable address) is referenced from a relocatable instruction. In such a case,
absolute addressing (@#A) may be employed to make the reference position-independent.
Index modes can be either position-independent or position-dependent, according to their
use in the program.
X(R)
. @X(R)

Index mode
Index-deferred mode

If the base,X, is an absolute value (for example, a control block offset), the reference is
position-independent. The following is an example:
MOV

2(SP),RO

;POSITION-INDEPENDENT

MOV

N(SP),RO

;POSITION-INDEPENDENT

N=4

If, however, X is a relocatable address, the reference is position-dependent, as the
following example shows:

CLR

ADDR(Rl)

;POSITION-DEPENDENT

Immediate mode can be either position-independent or not, according to its use.
Immediate mode references are formatted as follows:

Immediate mode

When an absolute expression defines the value of N, the code is position-independent.
When a relocatable expression defines N, the code is position-dependent. That is,
immediate mode references are position-independent only when N is an absolute value.

Programming Techniques

1Q-3

Absolute mode addressing is position-independent only in those cases where an absolute
virtual location is being referenced. Absolute mode addressing references are formatted
as follows:
@#A

Absolute mode

An example of a position-independent absolute reference is a reference to the PSW from
a relocatable instruction, as in this example:
MOV

@#PSW,RO

;RETRIEVE STATUS AND PLACE IN REGISTER

1 O.2~2 Comparison of Position-Dependent and Position-Independent
Code
The RSX-ll library routine, PWRUP, is a FORTRAN-callable subroutine for establishing
or removing a user power failure, Asynchronous System Trap (AST) entry point address.
Embedded within the routine is the actual AST entry point that saves all registers,
effects a call to the user-specified entry point, restores all registers on return, and
executes an AST exit directive; The following examples are excerpts from this routine.
The first example is modified to illustrate position-dependent references. The second
example is the position-independent version.

Position-Dependent Code

PWRUP::
CLR

-{SP)

;ASSUME SUCCESS

CALL

~X.PAA

;PUSH (SAVE)
;ARGUMENT ADDRESSES
;ONTOSTACK

WORD

1.,$PSW

;CLEAR PSw, ANP
;SET R1=R2 SP

MOV

$OTSV,R4

;GET OTS IMPURE
;AREA POINTER

MOV

(SP)+,R2

;GET AST ENTRY
;POINT ADDRESS

BNE

10$

;IF NONE SPECIFIED,
;SPECIFY NO POWER

CLR

-{SP)

;RECOVERY AST SERVICE

20$

MOV

R2,F.PF(R4)

;SET AST ENTRY POINT

MOV

#BA, -{SP)

;PUSH AST SERVICE
;ADDRESS

CALL

.X.EXT

;ISSUE DIRECTIVE, EXIT.

10$:

20$:

10-4 Programming T~chniques

BA:

.BYTE

109.,2.

MOV

RO, -(SP)

;PUSH (SAVE) RO

MOV
MOV

R1, -(SP)
R2, -(SP)

;PUSH (SAVE) R1
;PUSH (SAVE) R2

Position-Independent Code

PWRUP::
CLR
CALL

-(SP)

.WORD

1.,$PSW

MOV

@ $OTSY,R4

MOV

(SP)+,R2

BNE

10$

CLR

-(SP)

20$

MOV
MOV
ADD

R2,F.PF(R4)
PC, -(SP)
BA- .,(SP)

;SET AST ENTRY POINT
;PUSH CURRENT LOCATION
;COMPUTE ACTUAL LOCATION
;OF AST

CALL
.BYTE

.x.EXT
109.,2.

;ISSUE DIRECTIVE, EXIT.

.x.PAA

;ASSUME SUCCESS
;PUSH ARGUMENT
;ADDRESSES ONTO
;STACK
;CLEAR PSw, AND
;SET Rl=R2 SP.
;GET OTS IMPURE
;AREA POINTER
;GET AST ENTRY
;POINT ADDRESS
;IF NONE SPECIFIED,
;SPECIFY NO POWER
;RECOVERY AST SERVICE

10$:

20$:

;ACTUAL AST SERVICE ROUTINE:
;

1) SAVE REGISTERS

; 2) EFFECT A CALL TO SPECIFIED
SUBROUTINE
3) RESTORE REGISTERS
;

4) ISSUE AST EXIT DIRECTIVE

Programming Techniques "10-5

BA:

MOV

RO, -(SP)

;PUSH (SAVE) RO

MOV

Rl, -(SP)

;PUSH (SAVE) Rl

MOV

R2, -(SP)

;PUSH (SAVE) R2

The position-dependent version of the subroutine contains a relative reference to an
absolute symbol ($OTSV) and a literal reference to a relocatable symbol (BA). Both
references are bound by the task builder to fixed memory locations. Therefore, the
routine does not execute properly as part of a resident library, if its location in virtual
memory is not the same as the location specified at link time.
In the position-independent version, the reference to $OTSV has been changed to an
absolute reference. In addition, the necessary code has been added to compute the virtual
location of BA based upon the value of the PC. In this case, the value is obtained by
adding the value of the PC to the fixed displacement between the current location and
the specified symbol. Thus, execution of the modified routine is not affected by its location
in the virtual address space of the image.

10.3 Stacks
The stack is part of the basic design architecture of the KDJ11-E. It is an area of memory
set aside by the programmer or the operating system for temporary storage and linkage.
It is handled on a Last In, First Out (LIFO) basis, where items are retrieved in reverse of
the order in which they were stored. A stack starts at the highest location reserved for it
and expands linearly downward to lower addresses as items are added.
It is not necessary to keep track of the actual locations into which data is being stacked.
This is done automatically through an SP. To keep track of the last item added to the
stack, a general register is used to store the memory address of the last item in the stack.
Any register except R7 (the PC) may be used as an SP under program control; however,
instructions associated with subroutine linkage and interrupt service automatically use
R6 as a hardware stack pointer. For this reason, R6 is frequently referred to as the
system SPa Stacks may be maintained in either full-word or byte units. This is true for a
stack pointed to by any register except R6, which must be organized in full-word units.
Byte stacks (Figure 10-1) "require instructions capable of operating on bytes rather than
full words.

10.3.1 Pushing onto a Stack
Items are added to a stack using the autodecrement addressing mode. Adding items to
the stack is called pushing, and is accomplished by the following instructions:

MOV

Source, -(SP)

;MOV CONTENTS OF SOURCE WORD
;ONTO THE STACK
OR

MOVB

Source, -(SP)

;MOVB SOURCE BYTE ONTO
;THESTACK

10-6 Programming Techniques

Word Stack

007100

Item #1

007076

Item #2

007074

Item #3

007072

Item #4

.......- SP I

007072

007070
007066
007064

Byte Stack

007100

Item #1

007077

Item #2

007076

Item #3

007075

Item #4

~ SP

I 007075

Note:

Bytes are arranged In
words as follows:
Byte 3

Byte 2

Byte 1

Byte 0

)

Word
MA-1308-90.DG

Figure 10-1

Word and Byte Stacks

10.3.2 Popping from a Stack
Removing data ttom the stack is called popping. This operation is accomplished u$ing
the autoincrement mode.

MOV

(SP)+,Destination

MOVB

(SP)+,Destination

;MOV DESTINATION WORD
jOFF THE STACK
OR
;MOVB DESTINATION BYTE
;OFF THE STACK

Programming Techniques

10-7

After an item has been popped, its stack location is considered free and available for
other use. The SP points to the last-used location, implying that the next lower location
is free. Thus, a stack may represent a pool of shareable temporary storage locations.
Figure 10-2 illustrates the push and pop operations.
High Memory

+- SP

}

Stack
Area

Low Memory
1 An empty stack area

-ti'4- SP

t - -_ __ _

3 Pushing another

2 Pushing a datum
onto the stack

datum onto the
stacks

2
;IE

4 - - SP

r+- SP

4 Another push

~ SP

5 Pop

~ SP

6 Push

EO
E1

7 Pop
MA-1309-90.DG

Figure 10-2

Push and Pop Operations

10.3.3 Deleting Items from a Stack
The following techniques may be used to delete items from a stack:

To delete one item from a byte stack:
INC SP or TSTB(SP)+
To delete two items from a word stack:
ADD#2,SP or TST(SP)+
To delete 50 items from a word stack:
ADD#100.,SP

10-8 Programming Techniques

10.3.4 Stack Uses
A stack is used in the following ways:
1. Often, one of the general-purpose registers must be used in a subroutine or interrupt
service routine and then be returned to its original value. The stack can be used to

store the contents of the registers in~olved.
2. The stack is used in storing linkage information between a subroutine and its calling
program. The JSR instruction, used in calling a subroutine, requires the specification
of a linkage register along with the entry address of the subroutine. The content
of this linkage register is stored on the stack, so as not to be lost, and the return
address is moved from the PC to the linkage register. This provides a pointer back
to the calling program so that successive arguments may be transmitted easily to the
subroutine.
S.

If no arguments need to be passed by stacking them after the JSR instruction, the PC
may be used as the linkage register. In this case, the result of the JSR is to move the
return address in the calling program from the PC onto the stack and replace it with
the entry address of the. called subroutine.

4. In many cases, the operations performed by the subroutine can be applied directly to
the data located on or pointed to by a stack without the need to move the data into
the subroutine area.

Example:
;CALLING PROGRAM
MOVSP,Rl

;Rl IS USED AS THE STACK

JSRPC,SUBR

;POINTER HERE.
;SUBROUTINE

ADD (Rl)+,(Rl)

;ADD ITEM '1 TO '2, PLACE
;RESULT IN ITEM #2,
;Rl POINTS TO
;ITEM'2NOW

Since arguments. may be obtained from the stack by using some form of registerindexed addressing, it is sometimes useful to save a temporary copy of R6 in some
other register that has been saved at the beginning of a subroutine. If R6 is saved
in R5 at the beginning of the subroutine, R5 may be used to index the arguments.
During this time, R6 is free to be incremented and decremented while being used
as the SP. If R6 is used directly as the base for indexing and is not copied, it may
be difficult to keep track of its position in the argument list, since the base of the
stack changes with every autoincremeptJdecrement.
However, if the contents of R6 (SP) are saved in R5 before any arguments are
pushed onto the stack, the position relative to R5 remains constant.
Return from a subroutine also involves the stack, as the return instruction, RTS,
must retrieve information stored there by the JSR.

Programming Techniques -10-9

When a subroutine returns, it is necessary to clean up the stack by eliminating
or skipping over the subroutine arguments. One way this can be done is to insist
that the subroutine keep the number of arguments as its first stack item. Returns
from subroutines then involve calculating the amount by which to reset the SP,
resetting the SP, and then storing the original contents of the register that was
used as the SP copy.
5. Stack storage is used in trap and interrupt linkage. The PC and the PSW of the
executing program are pushed on the stack.
6. When the system stack is being used, nesting of subroutines, interrupts, and traps to
any level can occur until the stack overflows its legal limits.
7. The stack method is also available for temporary storage of any kind of data. It may
be used as a LIFO list for storing inputs, intermediate results, and so on.

10.3.5 Stack Use Examples
As an example of stack use, consider this situation. A subroutine (SUBR) wants to use
registers 1 and 2, but these registers must be returned to the calling program with their
contents unchanged. The subroutine could be written as follows:
Not Using the Stack
Assembler
Address

Octal Code

Syntax

Comments

076322

010167
SUBR:

MOV R1,TEMP1

;SAVE R1

076324

000074
010267

MOV R2,TEMP2

000072

076410

016701

MOV TEMP1,R1

076412
076414

000006
016702

076416
076420

000004
000207

RTSPC

076422

000000

TEMP1:0

076424

000000

TEMP2:0

076326
076330

1 Index constants

MOV TEMP2,R2
*1

;SAVE R2

;RESTORE R1
;RESTORER2

10-10 Programming Techniques

Using the Stack
Note that in this case, R3 is being used as an SP ~d has been previously set to point to
the end of an unused block of memory.
Assembler
Address

010020

OetalCode

Syntax

Comments

010143

MOV Rl, (RS)

;PUSHRI

SUBR:

010022

010243

MOVR2, (RS)

;PUSHR2

010130
010132
010134

012302
012301
000207

MOV (RS)+,R2

;POPR2

MOV (RS)+,Rl

;POPRI

RTSPC

The second routine uses four fewer words of instruction code and two words of temporary
stack storage. Another routine may use the same stack space at some later point. Thus,
the ability to share temporary storage in the form of a stack is a way to save on memory
usage.
As another example of stack use, consider the task of managing an input buffer from
a terminal. As characters come in, the user may wish to delete characters from the
line. This is accomplished very easily by maintaining a byte stack containing the input
characters. Whenever a backspace is received, a character is popped off the stack and
eliminated from consideration. In this example, popping characters to be eliminated can
be done by using either the MOVB (move byte) or INC (increment) instructions.
Note that in this case the INC instruction is preferable to MOVB, since it accomplishes
the task of eliminating the unwanted character from the stack by readjusting the SP
without the need for a destination location. Note also, that the SP used in this example
cannot be the system SP (R6) because R6 may point only to word (even) locations. See
Figure 10-3.

Programming Techniques

001011

001010

001007

001006

001005

001004

001003

001002

001001

INCR3

10-11

R31~_00_100_1___

1__0_01_00_2_.....

!4- R3 ..

LJ-00253-TIO

Figure 10-3

Byte Stack Used as a Character Buffer

10.3.6 Subroutine Linkage
The contents of the linkage register are saved on the system stack when a JSR is
executed. The effect is the same as executing a MOV reg, -(R6). Following the JSR
instruction, the same register is loaded with the memory address (the contents of the
current PC) and a jump is made to the entry location specified. Figure 10-4 shows the
conditions before and after the subroutine instruction JSR R5, 1064 is executed.
Because hardware already uses general purpose register 6 to point to a stack for saving
and restoring PC and PSW information, it is convenient to use that stack to save and
restore intermediate results and to transmit arguments to and from subroutines. Using
R6 this way permits nesting subroutines and interrupt service routines.
BEFORE

AFTER

(RS) =000132
(R6) =001776
(PC) =(R7) =001000

(RS) "" 001004
(R4) ... 001774
(PC) - (R7) - 001064

nnnnn

002000

nnnnn

001776

mmmmmm

001774

000132

001772

002000
001776

mmmmmm

4 - - SP

001776

1-------1

Figure 1Q-4

----

001774

JSR Stack Condition Example

10.3.6.1 Return from a Subroutine
An RTS instruction provides for a retum from the subroutine to the calling program.

The RTS instruction must specify the same register the JSR instruction used in the
subroutine call. When the RTS is executed, the register specified is moved to the PC, and
the top of the stack is placed in the register specified. Thus, an RTS PC has the effect of
retuming to the address specified on the top of the stack.

10-12 Programming Techniques

10.3.6.2 Subroutine Advantages

The JSR instruction provides several advantages to the subroutine ~alling procedure.
1. Arguments can be passed quickly between the calling program and the subroutine.

2. If there are no arguments, or the arguments are in a general register or on the stack,
the JSR PC,DST mode can be used so that none of the general purpose registers need
to be used for linkage.
3. Many JSRs can be executed without the need to provide any saving procedure for
the linkage information, since all linkage information is automatically pushed onto
the stack in sequential order. Returns can be made by automatically popping this
information from the stack in the order opposite to the JSRs.
This linkage address bookkeeping is called automatic nesting of subroutine calls. This
feature enables construction' of fast, efficient linkages in a simple, flexible manner. It also
permits a routine to call itself.

10.3.7 Interrupts
An interrupt is similar to a subroutine call, except that it is initiated by the hardware
rather than by the software. An interrupt can occur after the execution of an instruction.
Interrupt-driven techniques are used to reduce CPU waiting time. In direct program data
transfer, the CPU loops to check the state of the done/ready flag (bit 7) in the peripheral
interface. Using interrupts, the CPU can handle other functions until the peripheral
initiates service by setting the done bit in its CSR. The CPU completes the instruction
being executed, then acknowledges the interrupt, and vectors to an interrupt service
routine. The service routine transfers the data and may perform calculations with it.
After the interrupt service routine is complete, the computer resumes the program that
was interrupted by the high-priority request.
10.3.7.1 Interrupt Service Routines

With interrupt service routines, linkage information is passed so that a return to the
main program can be made. More information is necessary for an interrupt sequence
than for a subroutine call because of the random nature of interrupts. The complete
machine state of the program immediately prior to the occurrence of the interrupt must
be preserved in order to return to the program without any noticeable effects. This
information is stored in the PSW. Upon interrupt, the contents of the PC (address of next
instruction) and the PSW are automatically pushed onto the R6 system stack. The effect
is the same as executing:
MOV PS,-(SP)

;PUSHPSW

MOV PC,-(SP)

;PUSHPC

The new contents of the PC and PSW are loaded from two preassigned consecutive
memory locations called vector addresses. The first word contains the interrupt service
routine entry address (the address of the service routine program sequence). The
second word contains the new PSW that will determine the machine status, including
the operational mode and. register set to be used by the interrupt service routine. The
contents of the vector address is set under program control.

Programming Techniques

10-13

After the interrupt service routine is complete, an RTI is performed. The top two words
of the stack are automatically popped and placed in the PC and PSW, respectively, thus
resuming the interrupted program. Interrupt service programming is intimately involved
with the concept of CPU and device priority levels.
10.3.7.2 Nesting

Interrupts can be nested in much the same manner that subroutines are nested
(Figure 10--5). It is possible to nest any arbitrary mixture of subroutines and interrupts
with out any confusion. When the respective RTI and RTS instructions are used, the
proper returns are automatic.
1. Process 0 Is running; SP Is
pointing to location PO.

7. Subroutine A releases the temporary
storage holding TAl and TA2.

PO
PSO
PCO
TEO
11:1
1"51

2. Interrupt stops process 0 with
PC.PCO,and status.PSO, starts
process 1.

PCl
PC2

-.
0

3. Process 1 uses stack for temporary
storage (TEO,TE1).
SP

...

PSO
PCO
TEO
TEl

8. Subroutine A returns control to
process 2 with an RTS R7; PC Is
reset to PC2.

PO
P50
PCO
TEO
TEl
PSl
PCl

SP ....

o
4. Process 1 Interrupted with PC.PCl
and status-PS1; process 21s started.

SP ....

PSO
PCO
TEO
TEl
PSl
PCl

9. Process 2 completes with an RTI
Instruction (dismiss Interrupt);
PC Is reset to PCl and status
PC Is reset to PCl and status
Is reset to PSl and status.

PO~
PSO
PCO

SP-:

o
10. Process 1 releases the

5. Process 2 Is running and does a JSR
R7, A to subroutine A with PC.PC2.

PO
PSO
PCO
TEO

temporary storage holding TEO
and TEl.

11:1

SP ....

PSl
PCl
PC2

o
6. Subroutine A is running and uses

PSO
PO~

SP ....

11. Process 1 completes Its operation SP .... POo
with an RTI, PC Is reset to
-----'I
pca, and F status Is reset to PSO.
. . . . . _ - _.......
1-_

PO
PSO
PCO
TEO
TEl
PSl
PCl
PC2
TAl

stack for temporary storage.

SP ....

TA2

o
MA·1310·90.DG

Figure 10-5

Nested Interrupt Service Routines and Subroutines

10.3.8 Reentrancy
Other advantages of the KDJII-E stack organization occur in programming systems
that handle several tasks. Multitask program environments range from simple singleuser applications that manage a mixture of I/O interrupt service and background data
processing (as in RT-ll), to complex multiprogramming systems that manage an intricate
mixture of executive and multiuser programming situations (as in RSX-ll).

10-14 Programming Techniques

In all these situations, using the stack as a programming. technique provides flexibility
and time/memory economy by allowing many tasks to use a single copy of the same
routine with a simple straightforward way of keeping track of complex program linkages.
The ability to share a single copy of a program among users or among tasks is called
reentrancy. Reentrant program routines differ from ordinary subroutines in that it is not
necessary for reentrant routines to finish processing a given task before they can be used
by another task. At any time, tasks can exist in various stages of completion in the same
routine. Thus, the situation shown in Figure 10-6 may occur.
Memory
Program 1
Program 2
Subroutine A
Program 31--_ _ _ _--1

Memory
Program 1

Subroutine A

Program 2

Subroutine A

Program 3

Subroutine A

KDJ 11-E Approach

Conventional Approach

Programs 1,2, and 3 can
share subroutine A.

A separate copy of subroutine A must
be provided for each program.
MA·1311·QO.DG

Figure 10-6

Reentrant Routines

10.3.8.1 Reentrant Code
Reentrant routines must be written in pure code (that is, any code that consists
exclusively of instructions and constants). The value of using pure code whenever
possible is that the resulting code has the following characteristics:

•

It is generally considered easier to debug than standard code.

•

It can be kept in read-only memory (is read-only protected).

Using reentrant code, control of a routine can be shared as follows (Figure 10-7).
1. Task A requests processing by reentrant routine Q.
2. Task A temporarily gives up control of reentrant routine Q before it completes
processing.
3. Task B starts processing the same copy of reentrant routine Q.
4. Task B completes processing by reentrant routine Q.
5. Task A regains use of reentrant routine Q and resumes where it stopped.

Programming Techniques

10-15

Reentrant
Routine G

MA-1312-90.DG

Figure 10-7

Sharing Control of a Routine

10.3.8.2 Writing Reentrant· Code

In an operating system environment, when one task is executing and is interrupted· to
allow another task to run, a context switch occurs in which the PSW and current contents
of the general purpose registers are saved and replaced by the appropriate values for the
task being entered. Therefore, reentrant code must use the general purpose registers and
the stack for any counters, pointers, or data to be modified or manipulated in the routine.
The context switch occurs whenever a new task is allowed to execute. It causes all of the
general purpose registers, the PSw, and often, other task-related information to be saved
in an impure area. It then reloads these registers and locations with the appropriate
data for the task being entered. Notice that one consequence of this is that a new SP
value is loaded into R6, thereby causing a new area to be used as the stack when the
second task is entered.
The following guidelines should be followed when writing reentrant code:
1. All data should be in or pointed to by one of the general purpose registers.

2. A stack can be used for temporary storage of data or pointers to impure areas within
the task space. The pointer to such a stack would be stored in a general purpose
register.
3. Parameter addresses should be used by indexing and indirect reference rather than
by putting them into instructions within the code.
4. When temporary storage is accessed within the program, it should be by indexed
addresses, which can be set by the calling task in order to handle any possible
recursion.

10.3.9 Coroutines
In some programming situations, several program segments or routines are highly
interactive. Control is passed back and forth between the routines, each going through
a period of suspension before being resumed. Since the routines maintain a symmetric
relationship with each other, they are called coroutines.
Coroutines are two program sections, either one subordinate to the call of the other. The
nature of the call is, "I have processed all I can for now, so you can execute until you
are ready to stop, then I will continue." The coroutine call and return are identical, each
being a jump to subroutine instruction with the destination address on top of the stack
and the PC serving as the linkage register, as follows:

10-16 Programming Techniques

JSR PC,@(R6)+

10.3.9.1 Coroutine calls
The coding of coroutine calls is made simple by the stack feature. Initially, the entry
address of the coroutine is placed on the stack, and from that point the JSR PC,@(R6)+
instruction is used for both the call and the return statements. This JSR instruction
results in an exchange of the contents of the PC and the top element of the stack,
permitting the two routines to swap control and resume operation where each was
terminated by the previous swap. An example is shown in Figure 10-8. Notice that the
coroutine linkage cleans up the stack with each control transfer.

ROUTINE A

STACK

MeV 'lOC-(SP)

lOC

-SP

JSR Pc.@(SP)+
(PCO)

PCO

-SP

PC1

RounNEB

COMMENTS
lOC Is pushed onto the stack
to prepare for the coroutIne call.

lOC:

When the callIs executed the PC
from routIne A Is pushed on the
stack and executIon contInues
atlOC.

JSR PC.@(SP)+
(PC1)

RoutIne B can return control to
routIne A by another coroutIne call.
PCO Is popped from the atack and
executIon resumes In routIne A
Just after the call to routIne B.
(that Is. at PCO). PC11s saved on the
stack for a later return to
routIne B.
MA·1348·to.DG

Figure 10-8

Coroutine Example

10.3.9.2 Coroutlnes Versus Subroutines
Coroutines can be compared to subroutines in the following ways:

•

A subroutine is considered subordinate to the main or calling routine, but a coroutine
is considered to be on the same level, as each coroutine calls the other when it has
completed current processing.

•

When called, a subroutine executes to the end of its code. When called again, the
same code will execute before returning. A coroutine executes from the point after
the last call of the other coroutine. Therefore, the same code will not be executed
each time the coroutine is called. An example is shown in Figure 10-9.

•

The call and return instructions for coroutines are the same.
JSR PC,@(SP)+

•

This one instruction also cleans up the stack with each call. The last coroutine call
leaves an address on the stack that must be popped if no further calls are to be made.
See Section 10.3.6.1 for information on the return from subroutine instruction.

Programming Techniques

•

1-0-17

Each coroutine call returns to the coroutine code at the point after the last exit with
no need for a specific entry point label, as would be required with subroutines.
COROUTINES

MAIN PROGRAMS

SUBROUTINES

/ISIWC

JSR Rn, LOC

JSR PC,@ (SP)+

RTS

/JSRPC.@ (SP)+

JSR PC,@ (SP)+

" " JSR PC.@ (SP)+
MA-1313-90.0G

Figure 10-9

Coroutlnes Versus Subroutines

10.3.9.3 Using Coroutlnes
Coroutines should be used in the following situations:

•

Whenever two tasks must be coordinated in their execution without obscuring the
basic structure of the program. For example, in decoding a line of assembly language
code, the results at anyone position might indicate the next process to be entered. A
detected label must be processed. If no label is present, the operator must be located,
and so on.

•

To add clarity to the process being performed, to ease in the debugging phase, and so
on.

An assembler must perform a lexicographic scan of each assembly language statement
during pass 1 of the assembly process. The various steps in such a scan should
be separated from the main program flow to add to program clarity and to aid in
debugging by isolating details. Subroutines are not satisfactory in this case, as too much
information has to be passed to the subroutine each time it is called. Coroutines could
be effectively used, with one routine performing as the assembly pass 1 routine and the
other extracting one item at a time from the current input line. Figure 10-10 illustrates
this example.
Coroutines can be utilized in 110 processing. Figure 10-10 shows coroutines used in
double-buffered 110 using lOX. The flow of events may be described as follows:

10-18 Programming Techniques

Write 01
concurrently,

Read 11
Process 12
then
Write 02

concurrently,

Read 12
Process 11

Figure 10-11 illustrates a coroutine swapping interaction.
ROUTINE A

ROUTINE B

Start and Skip
Blanks
Nonblank

Read Name

Process Name

Skip Blanks

Process Mnemonics

Read Mnemonics

,
Read Address
Line Terminator
Semicolon

,
Skip Comment

End

MA·1314·90.DG

Figure 10-10

Coroutine Path

Programming Techniques

10-19

Routine #1 is operating, it then
executes:
MOV #PC2,-(R6)
JSR PC,@(R6)+

SP ----.

PC2

with the following results:

1. PC2 is popped from the stack
and the SP is autoincremented.
2. SP is autodecremented and
the old PC (PC 1) is pushed.

3. Control is transferred to the
location PC2 (routine #2).
Routine #2 is operating, it then
executes:

JSR PC,@(R6)+
with the result that PC2 is
exchanged for PC 1 on the
stack and control is

SP ----.

PC1

transferred back to routine #1.

MA-1315-90.DG

Figure 10-11

Coroutine Interaction

When routine 1 is operating, it executes
MOV #PC2, (R6)
JSR PC,@(R6)+

with the following results:
1. PC2 is popped from the stack and the SP is autoincremented.
2. SP is autodecremented and the old PC (PC1) is·pushed.
3. Control is transferred to the location PC2 (routine 2).
When routine 2 is operating, it executes
JSR PC,@(R6)+

with the result that PC2 is exchanged for PC1 on the stack and control is transferred
back to routine 1.

10.3.10 Recursion
An interesting aspect of a stack facility, other than its providing for automatic handling of

nested subroutines and interrupts, is that a program may call on itself as a subroutinejust as it can call on any other routine. Each new call causes the return linkage to
be placed on the stack, which (as it is a LIFO queue) sets up a natural unraveling to
each routine just after the point of departure. Figure 10-12 shows a typical flow for a
recursive routine.

10-20 Programming Techniques

Main Program

Sub 1

Sub 2

MA·1316·90.DG

Figure 10-12

Recursive Routine Flow

The main program calls function 1, SUB 1, which calls function 2, SUB 2, which recurses
once before returning.

Example:
DNCF:

BEQl$
JSR
R5,DNCF

;TO EXIT RECURSIVE LOOP
;RECURSE

RTSR5

;RETURN TO 1$ FOR
jEACH CALL, THEN TO
;MAIN PROGRAM

The routine DNCF calls itself until the variable tested becomes equal to O. Then it exits
to 1$, where the RTS instruction is executed, returning to the 1$ once for each recursive
call and a final time to return to the main program.
In general, recursion techniques lead to slower programs than the corresponding
interactive techniques, but recursion does produce shorter programs, and thus saves
memory space. Both the brevity and clarity produced by recursion are important in
assembly language programs.
Uses of Recursion-Recursion can be used in any routine in which the same process is
required several times. For example, a function to be integrated may contain another
function to be integrated, as in solving for XM, where

Programming Techniques

10-21

SM = 1 + F(X)

and
F(X) = G(X).

Another use for a recursive function could be in calculating a factorial function, because
FACT(N) = FACT(N 1) * N.

Recursion should terminate when N = 1.
The macroprocessor within MACRO-II is itself recursive, since it can process nested
macrodefinitions and calls. For example, within a macrodefinition, other macros can be
called. When a macro call is encountered within definition, the processor must work
recursively (that is, it n:tust process one macro before it is finished with another and then
continue with the previous one). The stack is used for a separate storage area for the
variables associated with each call to the procedure.
&; long as nested definitions of macros are available, it is possible for a macro to call

itself. However, unless conditionals are used to terminate this expansion, an infinite loop
may be generated.

10.3.11 Processor Traps
Certain errors and programming conditions cause the KDJII-E processor to enter the
service state and trap to a fixed location. A trap is an interrupt generated by hardware.
Pending conditions are arbitrated according to a priority. The following list describes the
priority from highest to lowest.

Condition

Description

Memory management
violation1(MMUERR)

A memory management
violation causes an abort
and traps to location 2508.

Timeout error1 (BUSERR)

No response from a bus device during
a bus transaction causes an abort
and traps to location 48.

Parity error1 (PARERR)

A parity error signal received by the
processor during a bus transaction
causes an abort and traps to location
1148. ,

Trace (T) bit1

If PSW bit 4 is set at the end of instruction
execution, the processor traps to location 148.

Stack overflow1 (STKOVF)

If the KSP was pushed below 4008
during instruction execution, the
processor traps to location 48 at
the end of the instruction.

1 Nonmaskable software cannot inhibit the condition.

when the processor is executing a program.

MMUERR, BUSERR PARERR are mutually exclusive

10-22 Programming Techniques

Condition
l

Description

Power fail (PFAIL)

If the power OK bus signal (BPOK H) was
negated during instruction execution) the
processor traps to location 248 at the
end of the instruction.

IntelTUpt level 7 (BIRQ7)
IntelTUpt level 6 (BIRQ6)
Interrupt level 5 (BIRQ5)
Interrupt level 4 (BIRQ4)

If device interrupt requests are
asserted and PSW <7:5> are properly
set, the processor at the end of the
present instruction execution
initiates an interrupt vector
sequence on the bus. These inputs
are maskable by PSW <7:5>.

Halt line

PSW <'711>

Levels Inhibited

All

6,5,4

5)4

0-3

None

If the BHALT L bus signal is asserted during the
service state, the processor enters ODT mode.

INonmaskable software cannot inhibit the condition. MMUERR, BUSERR PARERR are mutually exclusive
when the processor is executing a program.

10.3.11.1 Trap Instructions
Trap instructions provide for calls to emulators, 110 monitors, debugging packages, and
user-defined interpreters. When a trap occurs, the contents of the current PC and PSW
are pushed onto the processor stack and are replaced by the contents of a 2-word trap
vector containing a new PC and new PSw. The return sequence from a trap involves
executing an RTI or RT!' instruction, which restores the old PC and old PSW by popping
them from the stack. Trap vectors are located at permanently assigned fixed addresses.

The EMT (trap emulator) and TRAP instructions do not use the low-order byte of the
word in their machine language representation. This allows user information to be
transferred in the low-order byte. The new value of the PC, loaded from the vector
address of the TRAP or EMT instructions, is typically the starting address of a routine to
access and interpret this information. This routine is called a trap handler.
A trap handler must accomplish several tasks. It must save and restore all necessary
general purpose registers, interpret the low byte of the trap instruction and call the
indicated routine, serve as an interface between the calling program and this routine by
handling any data that needs to be passed between them, and finally, cause the return to
the main routine.

Programming Techniques

10-23

A trap handler can be useful as a patching technique. Jumping out to a patch area is
often difficult because a 2-word jump must be performed. However, the 1-word TRAP
instruction may be used to dispatch to patch· areas. A sufficient number of slots for
patching should first be reserved in the dispatch table of the trap handler. The jump
can then be accomplished by placing the address of the patch area into the table and
inserting the proper TRAP instruction where the patch is to be made.
10.3.11.2 Use of Macro calls

The trap handler can be used in a program to dispatch execution to anyone of several
routines. Macros may be defined to cause the proper expansion of a call to one of these
routines, as in the following example:
.MACRO SUB2 ARG
MOV ARG,RO
TRAP +1

.ENDM

When expanded, this macro sets up the one argument required by the routine in RO, and
then causes the trap instruction with the number 1 in the lower byte. The trap handler
should be written so that it recognizes a 1 as a call to SUB2. Notice that ARG here is
being transmitted to SUB2 from the calling program. It may be data required by the
routine or it may be a pointer to a longer list of arguments.
In an operating system environment like RT-ll, the EMT instruction is used to call the
system or monitor routines from a user program. The monitor of an operating system
necessarily contains coding for many functions, such as 110, file manipulation, and so
on. This coding is made accessible to the program through a series of macro calls that
expand into EMT instructions with low bytes, indicating the routine or group of routines
to which the desired routine belongs. Often a general purpose register is designated to be
used to pass an identification code to further indicate to the trap handler which routine
is desired. For example, the macro expansion for a resume execution command in RT-11
is as follows:
.MACRO .RSUM
CM3,2 .
.ENDM

CM3 is defined:
.MACRO CM3 CHAN, CODE
MOV CODE

*400,RO

.IIF NB

CHAN,BISB CHAN,RO

EMT374
.ENDM

Note that the EMT low byte is 374. This is interpreted by the EMT handler to indicate a
group of routines. Then the contents of RO (high byte) is tested by the handler to identify
exactly which routine within the group is being requested .,.....in this case routine number
2. (The CM3 call of the .RSUM is set up to pass the identification code.)

10-24 Programming Techniques

10.3.12 Conversion Routines
Almost all assembly language programs require the translation of data or results from
one form to another. Code that performs such a transformation is called a conversion
routine. Several commonly used conversion routines follow.
Almost all assembly language programs involve some type of conversion routine. Octalto-ASCII, octal-to-decimal, and decimal-to-ASCII are a few of the most widely used.
Arithmetic multiply and divide routines are fundamental to many conversion routines.
Division is typically approached in one of two ways.
1.

The division can be accomplished through a combination of rotates and subtractions.
Example:
The following example uses a 3-bit word:
DIV:
1$

MOV .a, (SP)
CLR (SP)
ASL (SP)
ASLR1
ROLRO
CMPRO,RS
BLT2$
SUBRS,RO
INC (SP)
DEC 2 (SP)
BNE$l

;SET UP DIGIT COUNTER
;CLEAR RESULT

;RO CONTAINS REMAINDER
;INCREMENT RESULT
;DECREMENT COUNTER

Therefore, to divide 7 by 2:
RO = 000
R1 = 111
R3 = 010
C bit =0

Stack
011
000

remainder
7 (multiplicand)
2 (multiplier)

counter
quotient

Following through the coding, the quotient, remainder, and dividend all shift left,
manipulating the most significant digit first, and so on.
At the conclusion of the routine:

Programming Techniques

RO = 001

10-25

remainder

Rl = 000
R3 = 010

Stack

000

counter

011

quotient

The second method of division works by repeated subtraction of the powers of the divisor,
keeping a count of the number of subtractions at each level.
Example:
'1b divide 22110 by 10, first try to subtract powers of 10 until a nonnegative value is
obtained, counting the number of subtractions of each power.

221
-1000
Negative, so go to the next lower power, and count for 103 = o.

221
-100
121 count for 1()2 =1
-100
21 count
-100

Negative, so reduce power, and count for 1()2 = 2.
21
-10
-11 count for 101 = 1

11
-10
1 count
-10

Negative, so count for 101 = 2.

10-26 Programming Techniques

No lower power, so remainder is 1.
Answer = 022, remainder 1.

Multiplication is also approached in one of two ways.
1.

Multiplication can be done with a combination of rotates and additions.
Example:
The following example uses a 3-bit word:
CLRRO

;HIGH HALF OF ANSWER

MOV#3,CNT

;SET UP COUNTER

MOV
R1,MULT;

;MULTIPLICAND

RORR2
BCCNOW
ADD MULT,RO

;IF INDICATED,
ADD
;MULTIPLICAND
NOW;

RORRO
R04R1
DECCNT
BNEMORE

MULT:
CNT:

The following conditions exist for 6 X 3.
RO = 000

high-order half of result

R1 = 110

multiplicand'

R3 = 011

multiplier

After the routine is executed:
RO = 010

high-order half of result

R1 = 010

low-order half of result

R2 = 100
CNT=O

Programming Techniques

10-27

·MULT= 110

The
second
method
of
multiplication

repetitive
ad-

dition.

Example:
Multiplication of RO by 508(101000).
MUL50:

MOV RO, -(SP)
ASLRO
ASLRO
ADD (SP)+,RO
ASLRO
ASLRO
ASLRO
RETURN

If RO contains 7:
RO = 111
After execution:

RO =
100011000
(78 * 50s = 430s)

ASCII Conversions- The conversion of ASCII characters to the internal representation
of a number, as well as the conversion of an internal number to ASCII in 110 operations,
presents a challenge. The following routine takes the 16-bit word in Rl and stores the
corresponding 6 ASCII characters in the buffer addressed by R2.
OUT:

MOV

#5,RO

;LOOP COUNT

LOOP:

MOV

Rl,-(SP)

;COpy WORD INTO STACK

BIC

#177770,@SP

;ONE OCTAL VALUE

ADD

#'O,@SP

;CONVERT TO ASCII

MOVB

(SP)+, -(R2)

;STORE IN BUFFER

ASR

;SHIFT

ASR

;RIGHT

10-28 Programming Techniques

ASR
DEC
BNE

R1
RO
LOOP

;THREE
;TEST IF DONE
;NO, DO IT AGAIN

BIC
ADD
MOVB
RTS

'177776,R1
1f0,R1
R5, -{R2)

;GET LAST BIT
;CONVERT TO ASCII

;STORE IN BUFFER
;DONE,RETURN

10.4 Programming the Processor Status Word
The current processor status can be read and written using several programming
techniques on the PSw. The PSW has an 110 address of 17777776. The KDJ11-E
and other PDP-II processots implement this address, whereas LSI-II and LSI-1li2
processors do not. One technique is to use the 110 address as a source or destination
address with any instruction.
CLR @'17777776
MOV @'17777776, RO

The first instruction clears the PSW and the second instruction moves the contents of the
PSW to general register o.
The PSW explicit address (17 777 776) can be accessed on a word or byte basis. The
KDJ11-E recognizes the PSW odd address (17 777 777) and the access result is identical
to an odd memory address reference.
Another technique is to use the two dedicated PSW instructions, MTPS and MFPS. These
instructions only reference the even byte. If memory management is enabled, certain
PSW bits are protected.

10.5 Programming Peripherals
Programming LSI-II bus compatible modules (devices) is simple. A special class of
instructions that deals with 110 operations is unnecessary. The bus structure permits
a unified addressing structure in which control, status, and data registers for devices
are directly addressed as memory locations. Therefore, all operations on these registers
(such as information transfer and data manipulation) are performed by normal memory
reference instructions.
The use of all memory reference instructions on device registers greatly increases the
flexibility of 110 programming. For example, information in a device register can be
compared directly with a value and a branch made on the result.
CMP RBUF,
BEQSERVICE

.101

In this case, the program looks for 101 in the DLV11 receiver data buffer register
(RBUF) and branches if it finds it. There is no need to transfer the information into
an intermediate register for comparison.

Programming Techniques

10-29

When the character is of interest, a memory reference instruction can transfer
the character into a user buffer in memory or to another peripheral device. The
instruction MOV DRINBUF LOC transfers a character from the DRV11 data input
buffer (DRINBUF) into a user-defined location.
All arithmetic operations can be performed on a peripheral device register. For example,
the instruction ADD #10, DROUT BUF adds 10 to the DRV11 output buffer. All read
/write device registers can be treated as accumulators. There is no need to funnel all
data transfers, arithmetic operations, and comparisons through one or a small number of
accumulator registers.

10.6 PDP-11 Programming Examples
The programming examples that follow show how the instruction set, addressing modes,
and programming techniques can be used to solve some simple problems. The format
used is MACR0-11.

Program Program
Address Counter Label

Op
Code

Operand Comments

;PROGRAMMING EXAMPLE
;SUBTRACT CONTENTS OF LOCS 700710
;FROM CONTENTS OF LOCS 1000-1010
000000

RO=%O
Rl=%l
R2=%2
R3=%3
R4=%4
R5=%5
SP=%6
PC=%7

000001
000002
000003
000004
000005
000006
000007

000500
000504
000510
000514

000500
012706
000500
012701
000700
012702
000712
012703
001000

START:

.=500
MOV

.#.,SP

MOV

#700,Rl

MOV

#712,R2

MOV

#1000,R3

;INIT STACK POINTER

10-30 Programming Techniques

. Program Program
Address Counter Label

Op
Code

Operand Comments

OQ0520

012704
001012

MOV

#1012,R4

000524
000526
000430

005000
005005
062105

RO
R5
(R1)+,R5

000532
000534
000536
000540
000542

020102
001375
062300
020304
001375

SUM2:

CLR
CLR
ADD
CMP
BNE
ADD
CMP
BNE

000544

160500

DIFF:

SUB

R5,RO

;SUBTRACT RESULTS

000546

HALT
.=700
WORD 1,2,3,4,5

;THAT'S ALL FOLKS

000700
000702
000704
000706
000710

000000
000700
000001
000002
000003
000004
000005

001000
001002
001004
001006
001010

001000
000004
000005
000006
000007
000010

.=1000
WORD 4,5,6,7,8

000500

END

SUM1:

;START ADDING
R1,R2
;FINISHED ADDING?
SUM 1
;IF NOT BRANCH BACK
(R3)+,RO ;START ADDING
RS,R4
;FINISHED ADDING?
SUM2
;IF NOT BRANCH BACK

Programming Techniques

Program. Program
Address Counter Label

Op
Code

10-31

Operand Comments

;PROGRAM TO COUNT NEGATIVE
NUMBERS
;IN A TABLE
;20. SIGNED WORDS
;BEGINNING AT LOC VALUES
;COUNT HOW MANY ARE NEGATIVE
INRO
RO=%O
Rl=%l
R2=%2
SP=%6
PC=%7

.=500
START:

MOV'.,SP
MOV .VALUE,Rl
MOV
'VALUES+40.,R2

;SET UP STACK
;SET UP POINTER
;SET UP COUNTER

CLRRO
CHECK:
BPL
NEXT

TST(Rl)+

;NO, INCREMENT
;COUNTER

INC
RO
NEXm
BNE
CHECK
HALT
VALUES:O
.END

;TEST NUMBER
;POSITIVE?

CMP Rl,R2

;YES, FINISHED?
;NO, GO BACK
;YES, STOP

10-32 Programming Techniques

Program. Program
Address Counter Label

Op
Code

Operand Comments

;PROGRAM TO COUNT ABOVE
AVERAGE QUIZ SCORES
;LIST OF 16. QUIZ SCORES
;BEGINNING AT LOC SCORES
;KNOWN AVERAGE IN LOC AVERAGE
;COUNT IN RO SCORES ABOVE
AVERAGE
RO=9bO
Rl=,*,l
R2=9b2
RS.9bS
SP.tH
PC-9b7
.-500
START:

CHECK:

MOV'.,SP

;SET UP STACK

MOV'16.,R1
MOV
'SCORES,R2
MOV
'AVERAGE,RS
CLRRO

;SET UP COUNTER
;SET UP POINTER

CMP (R2)+,(RS)

;COMPARE SCORE AND AVERAGE
;LESS THAN OR EQUAL
;TO AVERAGE?
;NO, COUNT

BLENO
INCRO
NO:

DECR1
BNECHECK
HALT

;YES, DECREMENT COUNTER
;FINISHED? NO, CHECK
;YES, STOP

AVERAGE:65.
SCORES· 25.,70.,100.,60.,80.,80.,40.
55.,75.,100.,65.,90.,70.,65.,70.

.END

Programming Techniques

Program Program
Address Counter Label

Op
Code

1Q-33

Operand Comments

;PROGRAMMING EXAMPLE
;ACCEPT (IMMEDIATE ECHO) AND
;STORE 20. CHARS
;FROM THE KEYBOARD, OUTPUT CR
&LF
;ECHO ENTIRE STRING FROM
STORAGE
RO=%O
Rl=%1
SP=%6
CR=15
LF=12
TKS=177560
TKB=TKS+2
TPS=TKB+2
TPB=TPS+2

.TITLE
ECHO
.=1000
#.,SP

;INITIALIZE STACK POINTER

START:

MOV

#SAVE+2,RO

;SA OF BUFFER
;BEYOND CR & LF

MOV

#20.,Rl

;CHARACTER COUNT

IN:

TSTB
BPL

@#TKS
IN

@#TPS

;CHAR IN BUFFER?
;IF NOT BRANCH BACK
;ANDWAIT

;CHECK TELEPRINTER
;READY STATUS

ECHO:

TSTB

BPL
MOVB

ECHO
@#TKB,@#TPB

;ECHO CHARACTER

MOVB

@#TKB,(RO)+

;STORE CHARACTER AWAY

DEC

BNE

;FINISHED INPUTTING?

MOV

#SAVE,RO

;SA OF BUFFER INCLUDING
;CR&LF

10-34 Programming Techniques

. Program Program
Address Counter Label

OUT:

Op
Code

Operand Comments

MOV

122.,Rl

;COUNTER OF BUFFER
;INCLUDING CR & LF

TSTB

@#TPS

;CHECK TELEPRINTER
;READY STATUS

BPL
MOVB

OUT
(RO)+,@lTPB

DEC

BNE

OUT

;OUTPUT CHARACTER
;FINISHED OUTPUTTING?

HALT
SAVE:

.BYTE

CR,LF
.=.+20,
.END

Program Program
Address Counter Label

Op
Code

Operand Comment.
;PROGRAMMING EXAMPLE
;SUBROUTINE TO INPUT TEN VALUES

MOV
IBUFFER,RO

;SETUPSAOF
;STORAGE BUFFER
;SET UP COUNTER

IN:

MOV I -lO.,Rl
TSTB@#TKS

OUT:

BPLIN
TSTB@#TPS

INPUT:

;TEST KYBD READY STATUS
;TEST TOO READY STATUS

BPLOUT
MOVB
@#TKB,@ITPB

;ECHO CHARACTER

MOVB
@#TKB,(RO)+

;STORE CHARACTER

INCRl

;INC COUNTER

BNEIN
RTSPC

;EXIT

Programming Techniques

Program Program.

Address Counter Label

Code

Ope~d

10-35

Comments
;PROGRAMMING EXAMPLE
;SUBROUTINE TO SORT TEN VALUES

SORT:

MOV , -10.,R4

MOV COUNT,R3
MOV 'BUFFER+9.,RO
ADDR3,RO
MOVB (RO)+,R1

LOOP:

CMPB (RO)+,R1
BGEGT

LT:

MOVB -{RO),R2
MOVB R1,(RO)+
MOVR2,R1

GT:

INC R3
BNELOOP

INSERT:

MOVB R1,BUFFER+10.(R4)
INCR4
INC COUNT
BNENEXT
MOV'9.,COUNT

;RESTORE LOCATION COUNT

RTSPC

;EXIT

COUNT:

.WORD -9.

LINE1:

.ANCIIIINPUT ANY TEN SINGLE-DIGIT VALUES (0-9);PW
.ASCIYSORT AND OUTPUT THEM INI

LINE2:

.ASCIYSMALLEST TO LARGEST ORDER)

BUFFER: .=.+10.
.ENDINITSP

Program Program
Address Counter Label

Op
Code

;FINISHED!!!

Operand Comments
;PROGRAMMING EXAMPLE
;SUBROUTINE EXAMPLE
;INPUT TEN VALUES, SORT, AND
;OUTPUT THEM IN SMALLEST TO
LARGEST ORDER

10-36 Programming Techniques

Program Propam
Address Counter Label

Code

Operand Comments

RO=~O
R1~1
R2=~2
RS.~3

R4=9b4
RS=~5

SP=%6

PC=~7

TKS=177560
(address oftenninal control status register)
TKB=TKS+2 - (terminal data buffer register)
TPS=TKB+2 - (terminal output control and status registers)
TPB=TPS+2 - (terminal output data buffer)
.=3000
INITSP:

Program Propam
Address Counter Label

CRLF:

MOVt.,SP
JSRPC,CRLF
JSR RS, OUTPUT
LINE1
69.
JSRPC,CRLF
JSR R5,OUTPUT
LINE2
26.
JSRPC,CRLF
JSR PC,INPUT
JSRPC,SORT
JSRPC,CRLF
JSR R5,OUTPUT
BUFFER
10.
JSRPC,CRLF
HALT

;INITIALIZE STACK POINTER
;00 TO CRLF SUBROUTINE
;00 TO OUTPUT SUBROUTINE
;SA OF LINE 1 BUFFER
;NUMBER OF OUTPUTS
;00 TO CRLF SUBROUTINE
;00 TO OUTPUT SUBROUTINE
;SA OF LINE 2 BUFFER
;NUMBER OF OUTPUTS
;00 TO CRLF SUBROUTINE
;00 TO INPUT SUBROUTINE
;00 TO SORT SUBROUTINE
;00 TO CRLF SUBROUTINE
;00 TO OUTPUT SUBROUTINE
;INPUT BUFFER AREA
;NUMBER OF OUTPUTS
;THE END!!!

Code

Operand Comment!!

TSTB @#TPS
BPLCRLF

;PROGRAMMING EXAMPLE
;SUBROUTINE TO OUTPUT A CR " LF
;TEST TOO READY STATUS

Programming Techniques

Program Program
Address Counter Label

LNFD:

Op
Code

10-37

Operand Comments

MOVB
#15,@#TPB

;OUTPUT CARRIAGE RETURN

TSTB @#TPS

;TEST TTO READY STATUS

BPLLNFD
MOVB
#12,@#TPB

;OUTPUT LINE FEED

RTSPC

;EXIT

;SUBROUTINE TO OUTPUT A
;VARIABLE LENGTH MESSAGE
OUTPUT: MOV (R5)+,RO

AGAIN:

;PICK UP SA OF DATA BLOCK

MOV (R5)+,R1

;PICK UP NUMBER OF OUTPUTS

NEGR1

;NEGATE IT

TSTB @#TPS

;TEST TTO READY STATUS

BPLAGAIN
MOVB (RO)+,@#TPB
;OUTPUT CHARACTER
INCR1

;BUMP COUNTER

BNEAGAIN
RTSR5

10.7 Looping Techniques
Looping techniques are illustrated in the program segments that follow. The segments
are used to clear a 50-word table.
1.

Autoincrement (pointer address in general purpose register)

RO=%O
MOVE #TBL,RO
CLR(RO)+
CMP RO,#TBL+100.
BNELOOP

LOOP:

Autodecrement (pointer and limit values in general purpose register)

10-38 Programming Techniques

RO=%O
Rl=%l
MOV#TBL,RO
MOV #TBL+lOO.,Rl
CLR-(Rl)
CMPRl,RO
BNELOOP

LOOP:

Counter (decrementing a general purpose register containing count)

RO=%O
Rl=%l
MOV#TBL,RO
MOV#50.,Rl
CLR(RO)+
DEeRl
BNELOOP

LOOP:

Index Register Modification (indexed mode, modifying index value)

RO=%O
CLRRO
CLRTBL(RO)
ADD#2,RO
CMP RO,#100.
BNELOOP

LOOP:

Faster Index Register Modification (storing values in general purpose register)

RO=%O
Rl=%l
R2=%2
MOV#2,Rl
MOV #100.,R2
CLRRO
CLRTBL (RO)
ADD Rl,RO
CMPRO,R2
BNE LOOP

LOOP:

Address Modification (indexed mode, modifying base address)

RO=%O
MOV#TBL,RO
LOOP:

CLR'O(RO)
ADD #2,LOOP+2
eMP LOOP+2,#100.
BNELOOP

A
Setup Parameters Worksheet
Two worksheets for each mode (video terminal or hardcopy) are provided for you to
record the original setup parameter selections and the new setup parameters selections
contained in the EEPROM of the KDJII-E CPU module:
•

Fill out the original worksheet when you install a KDJII-E CPU module.

•

Fill out the new worksheet when you change the parameter selections.

The information on these worksheets is used for programming any future replacement
KDJII-E CPU module.
Leave the worksheets with the system for future use.
Refer to Chapter 4 for more information on setup.

A-1

A-2 Setup Parameters Worksheet

A.1 Original Setup Menu Worksheet - Video Terminal suppon
Disable UBA ROM

.Yes/No

Unibus System

Enable USA lS-Bit Mode

Yes/No

Memory

Memory Intern

Do not change

EEprom

Rom on 173000

Yes/No

Time

Rom on 165000

Yes/No

Power up Mode

Rom/Auto/ODT/Trap 24

Restart Mode

Rom/Auto/ODT/Trap 24

Power-on Self-tests

Yes/No

Select Self-tests

Edit

User Boot

Edit

Alternate Boot Block

Yes/No

LTC Register

Yes/No

Force Clock Interrupt

Yes/No

Clock Frequency

PS/50Hz/60Hz/SOOHz

Halt on Break

Yes/No

Trap on Halt

Yes/No

Ignore Battery

Yes/No

Lines on

176500/176600/DIS

KDJ11-E Monitor

Version 1.06

Licensed to Digital Equipment
Corporation

Boot

Dev.

Unit

Address

1
2

4
5

Lines

Address / Vec

Line 1

Line 2

Line 3

Line 4

Line 5

Line 6

Line 7

Baud

Data Stop Par

Setup Parameters Worksheet A-3

A.2 New Setup Menu Worksheet - Video Terminal Support
Disable UBA ROM

Yes/No

Unibus System

Enable UBA 18-Bit Mode

Yes/No

Memory

Memory Intern

Do not change

EEprom

Rom on 173000

Yes/No

Time

Rom on 165000

Yes/No

Power up Mode

Rom/Auto/ODT/Trap 24

Restart Mode

Rom/Auto/ODT/Trap 24

Power-on Self-tests

Yes/No

Select Self-tests

Edit

User Boot

Edit

Alternate Boot Block

Yes/No

LTC Register

Yes/No

Force Clock Interrupt

Yes/No

Clock Frequency

PS/50Hz/60Hz/800Hz

Halt on Break

Yes/No

Trap on Halt

Yes/No

Ignore Battery

Yes/No

Lines on

176500/176600/DIS

KDJ11-E Monitor

Version 1.06

Licensed to Digital Equipment
Corporation

Boot

Dev.

Unit

Address

1
2
3
4
5
6

Lines

Address / Vee

Line 1

Line 2

Line 3

Line 4

Line 5

Line 6

Line 7

Baud

Data Stop Par

A-4 Setup Parameters Worksheet

A.3 Original Worksheet - Hard Copy Printer suppon
KDJ11-E Monitor Version 1.06 30-July-1990
(C) Digital Equipment Corporation 1990
A Memory Intern

(0) -

2MB

(1) -

4MB

B Rom on 173000

(0) -

(1) -

Yes

C Rom on 165000

(0) -

(1) -

Yes

D Power-up Mode

(0) - Dialog
Odt
(1) (2) - Trap24
(3)
Auto

Restart Mode

(0)
(1)
(2)
(3)

Power-on Self-tests

(0) -

(1) -

Yes

Alternate Boot Block

(0) -

(1) -

Yes

(1) -

Yes

(1) -

Yes

(1) -

Yes

(1) -

Yes

(1) -

Yes

H LTC Register

- Dialog
Odt
- Trap24
- Auto

(0) -

Force Clock Interrupt

(0) -

Clock Frequency

(0)
(1)
(2)
(3)

Trap on Halt

PIS
- 50Hz
- 60Hz
- 800Hz
No
(0) No
(0) -

Ignore Battery

(0) -

K Halt on Break

N Lines on

DIS
(0) (1) - 176500
(2) - 176600

Disable USA ,ROM

(0) -

(1)

Yes

Enable USA la-Bit Mode

(0) -

(1)

Yes

Setup Parameters Worksheet A-5

A.4 New Worksheet - Hard Copy Printer Support
KDJ11-E Monitor Version 1.06 30-July-1990
(C) Digital Equipment Corporation 1990
A Memory Intern

(0) -

2MB

(1) -

4MB

B Rom on 173000

(0) -

(1) -

Yes

C Rom on 165000

(0) -

(1) -

Yes

D Power-up Mode

(0) - Dialoq
Odt
(1) (2) - Trap24
(3)
Auto

Restart Mode

(0)
(1)
(2)
(3)

Power-on Self-tests

(0) -

(1) -

Yes

G Alternate Boot Block

- Dialoq
Odt
- Trap24
- Auto

(0) -

(1) -

Yes

H LTC Register

(0) -

(1) -

Yes

Force Clock Interrupt

(0) -

(1) -

Yes

Clock Frequency

(0)
(1)
(2)
(3)

PIS
- 50Hz
- 60Hz
- 800Hz

K Halt on Break

(0) -

(1) -

Yes

Trap on Halt

(0) -

(1) -

Yes

M Ignore Battery

(0) -

(1) -

Yes

N Lines on

DIS
(0) (1) - 176500
(2) - 176600

Disable USA ROM

(0) -

(1) -

Yes

Enable USA 18-Bit Mode

(0) -

(1) -

Yes

Index

A
ABSF instruction, 9-11
Absolute addressing mode, 7-18
AC bus loads definition, 5-24
ADC instruction, 8-25
ADDF instruction, 9-12
ADD instruction, 8-32
Addressing errors, 1-11
Addressing modes, 7-1
Address specification
entering octal digits, 3-7
KDJ11-E, 3--6
ODT timeout, 3-7
processor 110 addresses, 3-6
stack pointer selection, 3-7
ASHe instruction, 8--35
ASH instruction, 8-34
ASL instruction, 8-19
ASR instruction, 8-19
Autodecrement-deferred, 7-13
Autodecrement mode, 7-9
Autoincrement-deferred, 7-13
Autoincrement mode, 7-7

B
Baud rate selection, 2-6
BCC instruction, 8--46
BCS instruction, 8--46
BEQ instruction, .8-44
BGE instruction, 8-48
BGT instruction, 8-49
BHI instruction, 8-50
BHIS instruction, 8-51
BIC instruction, 8-38
BIS instruction, 8--39
BIT instruction, 8--37
BLE instruction, 8--49
BLO instruction, 8-51
BLOS instruction, 8--50
BLT instruction, 8--48
BMI instruction, 8--45
BNE instruction, 8--43
Boolean symbols, 9-10
Boot and diagnostic register set, 1-41
Boot command, 4-3

BPL instruction, 8-44
BPT instruction, 8-58
Branches, 8-41
BR instruction, 8-42
Bus cycle
DATI, 5-5
DATIO(B), 5-9
DATO(B), 5-7
PMI block data in, 6-9
PMI data in/data in pause, 6-8
PMI data out/data out byte, 6-11
protocol, 5-4
Bus cycles
data transfer, 5-3
Bus device interrupt, 1-32
Bus device NPR, 1-32
Bus master, 5-2
Bus termination - KDJll-E, 5-25
Bus timeout errors, 1-11
BVC instruction, 8-45
Byte instructions, 8--8

C
CFCC instruction, 9-13
Clearing status registers following abort,
1-25
CLRF instruction, 9-13
CLR instruction, 8-13
CMPF instruction, 9-14
CMP instruction, 8-31
code

Position independent, 10-1
Use of addressing modes in
the construction of position
independent code, 10-1
Code
Comparison of position dependent and
position independent code, 10-3
COM instruction, 8-14
Command
diagnostic, 4-5
help, 4-8
list, 4-9
map, 4-10
setup, 4-11
Commands
TOY (hard copy), 4-35

Index 1

2 Index

Conditional branches (signed), 8-47
Conditional branches (unsigned), 8-50
Condi tion code operators, 8-69
Configuring multiple-backplane systems,
. 5-29
Configuring single-backplane systems,
5-29
Console ODT, 3-1
/ (ANSI 057)-slash, 3-3
$ (ASCII 044) or R (ASCII 122), 3-4
command set, 3-2
<CR> (ASCII 15)--carriage return, 3-3
<CTRL><SHIFT>S(ASCII 23)-binary
dump, 3-6
G (ASCII 107)-go, 3-5
<LF> (ASCII 12)-line feed, 3-4
P (ASCII 120)- proceed, 3-5
S (ASCII 123)-processor status word
designator, 3-4
ConsoleiSLU enable - disable, 2-7
Construction of a physical address 1-15
Control; functions
'
external event interrupt request 5-23
Control functions
'
DC power OK, 5-22
Initialization, 5-22
power-ok, 5-22
power status, 5-22
processor halt, 5-22
Conversion routines, 10-24
Coroutine
coroutine calls, 10--16
coroutines versus subroutines. 10--16
using coroutines, 10--17
Coroutines, 10--15
CPU error register, 1-7
CPU module
troubleshooting, 4-63
CSM instruction, 8-63

D
DATI bus cycle, 5-5
DC bus load definition, 5-24
DCJII-A microprocessor features 1-2
Decrement instruction, 8-15
'
DECXll, 4-46
Deferred (indirect)addressing 7-13
Destination operand, 7-2 '
Device priority, 5-17
Diagnostic programs, 4--45
Direct addressing, 7-4
DIVF instruction, 9-15
DIV instruction, 8-36

DMA
Direct Memory Access
Direct Memory Access 'lransaction,
5-12
double-operand addressing, 7-3
Double-operand instruction
format
ADD, 8-32

Double-operand instruction
format (Cont.)
ASH, 8-34
ASHC, 8-35
BIC,BICB, 8-38
BIS,BISB, 8-39
BIT,BITB, 8-37
CMP,CMPB, 8-31
DIV, 8-36
MOV,MOVB,8-30
MUL,8-36
SUB, 8-33
XOR, 8-40
Double-operand instruction set
list
condition code operators, 8-12
general, 8-10
jump and subroutine, 8-11
logical, 8-10
miscellaneous instruction set 8-12
miscellaneous program contr~l,
8-12
program control, 8-10
signed conditional branch, 8-11
trap and interrupt, 8-11
unsigned conditional branch, 8-11

E
EEPROM configuration parameters 2-7
EMT instruction, 8-57
•
Error detection
during boot command, 4-5
Error messages. 4-60
console terminal, 4-46

F
Floating exception code and addressing
registers, 9-6
Floating-point data, 9-2
Floating-point data formats, 9-1
formats
Floating-point data, 9-2
Floating-point data formats, 9-1
Floating point zero, 9-1
Nonvanishing floating-point
numbers, 9-1
Undefined variables, 9-2
Floating-point instruction
Format
ABSF/ABSD, 9-11
ADDF/ADDD, 9-12
CFCC, 9-13
CLRF/CLRD, 9-13
CMPF/CMPD, 9-14
DIVFIDIVD, 9-15
LDCDFILDCFD, 9-16
LDCIFILDCIDILDCLFILDCLD,
9-17
LDEXP, 9--18
LDFILDD, 9-19

Index 3

Floating-point instruction
Fonnat (Cont.)
LDFPS, 9-19
MODFIMODD, 9-20
MULFIMULD, 9-22
NEGFINEGD, 9-23
SETD, 9-23
SETF, 9-24
SETI, 9-24
SETL, 9-24
STCFD/STCDF, 9-25
STCFIISTCFUSTCDIISTCDL,
. 9-26
STEXP, 9-27
STFPS, 9-28
STF/STD, 9-27
STST, 9-28
SUBF/SUBD, 9-29
TSTFITSTD, 9-30
Float~ng-po~nt instruction addressing, 9-7
FloatIng-pOInt status register (FPS) 9-2
Floating-point zero, 9-1
'
Force dialog mode, 2-6
Formats
types of
Floating-point data formats, 9-1
to 9-2
FPJ11, 1-1

G
General registers, 1-4

H
HALT instruction, 8-65
Hard copy commands
TOY, 4-35
Hard copy tenninal support, 4-2

Interrupt (Cont.)
service routines, 10-12
Interrupt protocol, 5-17
Interrupts, 1-8, 5-16, 10-12
Interrupts under memory management,
1-15
Interrupt vector timeouts 1-11
lOT instruction, 8-59 '

J
JMP instruction, 8-52
JSR instruction, 8-53
Jump and subroutine instructions, 8-52
Jumpers for +5 V power source selection
2-3
'

K
KDJ11-E
troubleshooting, 4-63
KDJ11-E CPU Module
troubleshooting, 4-63
KDJ11-E module features, 1-1
KDJ11-E serial line units, 1-33
Kernel protection, 1-4

L
LDCDF instruction, 9-16
LDCIF instruction, 9-17
LDEXP instruction, 9-18
LDF instruction, 9-19
LDFPS instruction, 9-19
Looping techniques, 10-37
LSI-II based systems, 2-8
LSI-II bus, 5-1
LSI bus signals, 6-2

M
Immediate mode, 7-17
INC instruction, 8-15
Index-deferred, 7-14
Index-mode, 7-11
Instruction fonnats, 8-4
Instructions
types of
double-operand, 8-30 to 8-40
Floating point, 9-9 to 9-30
miscellaneous, 8-65 to 8-68
Program control, 8-41 to 8-63
single-operand, 8-13 to 8-29
Instruction set
functional list of
double-operand, 8-10 to 8-12
single-operand, 8-9
Instruction set list, 8-1
Interrupt
nesting, 10-13

Mapping, 16-bit, 1-12
Mapping, 18-Bit, 1-13
Mapping, 22-hit, 1-13
MARK instruction, 8-61
Memory management, 1-11
types of
registers, 1-17 to 1-24
Memory management register
Memory management register 0, 1-22
Memory management register 1, 1-23
Memory management register 2, 1-24
Memory management register 3, 1-24
Memory management registers, 1-17
Page address register, 1-20
Page descriptor register, 1-21
Memory mapping, 1-12
Memory pages - nonconsecutive, 1-27
Memory pages - stack, 1-28
Memory page - typical, 1-25
Menu

4 Index
Menu (Cont.)
map) 4-45
self-test) 4-42
setup) 4-36
user boot) 4-43
MFPD instruction) 8-68
MFPS instruction, 8-28
MFPl' instruction, 8-67
MODF instruction, 9-20
Module finger identificatioDt 2-9
Module installation procedure, 2-16
MOV instruction, 8-30
MTPD instruction, 8-67
MTPS instruction) 8-29
MULF instruction, 9-22
MUL instruction, 8-36
Multiple faults, 1-25
Multiple-precision, 8-24

N
NEGF instruction) 9-23
NEG instruction, 8-16
Nonvanishing floating-point numbers, 9-1
No SACK timeouts, 1-11

ODT

console command set, 3-2
entry conditions, 3-1
timeout, 3-7
Operation overview, 4-1

P
PMI
bus master signals) 6-1
interface, 6-1
interrupt protocol, 6-13
power-uplpower-down, 6-13
slave signals, 6-1
UNffiUS adapter signals) 6-1
PMI data transfers, 1-32, 6-8
PMI operation
in an LSI-II system, 6-5
in a UNffiUS system, 6-5
PMI protocol, 1-32
Position-independent, 7-17
Power supply loading, 5-31
Private memory interconnect, 1-32
Processor status word, 1-5
Processor traps, 10-21
trap instructions) 10-22
use of macro calls, 10-23
Program control instruction
format
BCC,8-46
BCS, 8-46
BEQ, 8-44
BGE, 8-48

Program control instruction
format (Cont.)
BOT, 8-49
BBI, 8-50·
BBIS, 8-51
BLE, 8-49
BLO, 8-51
BLOS,8-50
BLT, 8-48
BMI) 8-45
BNE,8-43
BPL) 8-44
BPl',8-58
B~ 8-42
BVC, 8-45
CSM, 8-63
EMT, 8-57
HALT) 8-65
lOT) 8-59
JMP,8-52
JS~ 8-53
MARK, 8-61
MFPD,MFPI, 8-68
MFPl') 8-67
MTPD,MTPI, 8-67
RESET, 8-66
RTI, 8-59
RTS, 8-55
RTT) 8-60
SOB, 8-56
SPL, 8-62
Trap, 8-58
WAIT, 8-66
Program controls (miscellaneous), 8-61
Program counter) 1-5
Program interrupt request register, 1-7
Programming
PDP-II examples, 10-29
peripherals, 10-28
the processor status word, 10-28
PSWoperators, 8-28

R
Recursion) 10-19
Red stack aborts, 1-11
Reentrancy, 10-13
Reentrant
reentrant code, 10-14
writing reentrant code, 10-15
Register - additional status (17777526),
1-46
Register - cache control (17777746), 1-30
Register - configuration and display
(17777524), 1-45
.
Register - control/status (17777520), 1-42
Register-deferred, 7-13
Register - hit/miss (17777752), 1-31
Register - line frequency clock and status
•
(17777546), 1-47
Register - Maintenance (17777750), 1-48

Index 5

Register - memory system error
(17777744), 1-29
Register-mode, 7-5
Register - page address, 1-20
Register - page control (17777522), 1-44
Register - parity CSR (17772100), 1-31
Register - receiver data buffer (1777xxx2),
1--37
Register - receiver status register
(1777xxxO), 1--36
Register - transmitter data buffer
(177xxx6), 1--39
Register - transmitter status (1777xxx4),
1--38
Relative-addressing mode, 7-19
Relative-deferred addressing mode, 7-20
RESET instruction, 8-66'
Restricted LSI-II systems, 2-8
ROL instruction, 8-22
ROM, 4-1
ROM mode, 2-6
ROR instruction, 8-21
RTI instruction, 8-59
RTS instruction, 8-55
RTT instruction, 8-60

S
SBC instruction, 8-26
Self-test
KDJl1-E, 4-46
SETD instruction, 9-23
SETF instruction, 9-24
SETI instruction, 9-24
SETL instruction, 9-24
Setup
worksheet, A-I
Setup mode
command 10 - load EEPROM boot
program into memory, 4-31
command 11 - edit or create EEPROM
boot program, 4-31
command 12 - save a boot program in
the EEPROM, 4-33
command 13 - delete a saved EEPROM
boot program, 4-34
command 14 - enter ROM ODT, 4-34
command 1 - exit, 4-12
command 2 - select configuration
parameters, 4-12
command 3 - select diagnostic
configuration, 4-21
command 4 - select serial line
parameters, 4-23
command 5 - select boot parameters,
4-25
command 6 - list available boot
programs, 4-27
command 7 - factory setting, 4-29
command 8 - save the setup table in
the EEPROM, 4-30

Setup mode (Cont.)
command 9 - load EEPROM data into
the setup table, 4-30
Shifts and rotates, 8-19
Single-operand addressing, 7-2
Single-operand instruction
format
ADC,ADCB, 8-25
ASL,ASLB, 8-19
ASR,ASRB, 8-19
CLR,CLRB, 8-13
COM, COMB, 8-14
DEC,DECB, 8-15
INC,INCB, 8-15
MFPS, 8-28
MTPS, 8-29
NEG,NEGB, 8-16
ROL,ROLB, 8-22
ROR,RORB, 8-21
SBC,SBCB, 8-26
SWAB, 8-23
SXT, 8-27
TST,TSTB, 8-17
TSTSET, 8-18
WRTLCK, 8-18
Single-operand instruction set
list
general, 8-9
multiple-precision, 8-9
PSW operators, 8-9
shift and rotate, ~
SOB instruction, 8-56
Source-operand, 7-3
Specification
signal level, 5-24
SPL instruction, 8-62
Stack
deleting items from a stack, 10-7
popping from a stack, 10-6
pushing onto a stack, 10-5
return from a subroutine, 10-11
stack use (examples), 10-9
stack uses, 10-8
subroutine linkage, 10-11
Stack limit protection, 1-4
Stack pointer, 1-4
Stacks, 10-5
STCFD instruction, 9-25
STCFI instruction, 9-26
STEXP instruction, 9-27
STF instruction, 9-27
STFPS instruction, 9-28
STST instruction, 9-28
SUBF instruction, 9-29
SUB instruction, 8-33
Sunset loops, 1-10
SWAB instruction, 8-23
Switchpack, 2-3
SXT instruction, 8-27

6 Index

T
~rminal interface, 3-1
'Thrms used in instruction definitions,
9-10
TOY Clock
programming information, 1-50
Time of Year, 1-49
TOY command
hard copy, 4-35
Transfer - bloclt data in, 1-33
Transfer - Data inlData in pause, 1-33
Transfer - data out/data out byte, 1-33
Transfening control to non-digital boot
modules (Q-bus), 4-4
Transfening control to non-digital boot
modules (UNIBUS), 4-4
Trap instruction, 8-58
Traps, 8-56
Reserved Instruction traps
trace traps, 8-63
Troubleshooting
CPU module, 4-63

TSTF instruction, 9-30
TST instruction, 8-17
TSTSET instruction, 8-18

U
Undefined variables, 9-2
UNIBUS based systems, 2-9

V
Virtual addressing, 1-14

W
WAIT instruction, 8-66
WRTLCK instruction, 8-18

X
XOR instruction, 8-40