Digital PDFs

EK-KT11C-MM-005

April 1976

100 pages

Original

8.3MB

view download

OCR Version

4.6MB

view download

Document:	KT11-C,CD Memory Management Unit Maintenance Manual
Order Number:	EK-KT11C-MM
Revision:	005
Pages:	100
Original Filename:	EK-KT11C-MM-005-KT11-C_CD_Memory_Management_Maintenance_Manual_1976.pdf

OCR Text

EK-KT11C-MM-005

KT11-C,CD memory
management unit
maintenance manual

digital equipment corporation - maynard, massachusetts

1st Edition, April 1972
2nd Printing (Rev) July 1972
3rd Printing, November 1972
4th Printing, February 1973
5th Printing, July 1973
6th Printing (Rev) October 1973
7th Printing, January 1974
8th Printing, November 1974
9th Printing (Rev) June 1976

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no respon-

sibility for any errors which may appear in this

manual.

‘
Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

DECtape

PDP

DECCOMM
DECsystem-10

DECUS
DIGITAL
MASSBUS

TYPESET-8
TYPESET-11

DECSYSTEM-20

RSTS

UNIBUS

CONTENTS
Page

CHAPTER 1

GENERAL DESCRIPTION

1.1

Purpose of Option

1-1

1.2

Prerequisite

1-1

1.3

Features

1-1

Memory Protection

1-1

1.3.2

Relocation/Virtual Memory

1-3

1.3.3

Memory Expansion

1-3

1.3.4

Variable Size Pages

1-3

1.3.5

Page State Information

1-3

1.3.6

Instruction/Data Spaces

1-4

1.3.7

Kernel/Supervisor/User Spaces

1-4

1.3.8

Program vs Stack Pages

1-4

1.3.9

Fault Recovery

1-4

Statistical Traps

1-4

1.3.1

1.3.10
1.4

KT11-C, CD Memory Management Unit Specifications

CHAPTER 2

OPERATION AND PROGRAMMING

2.1

Basic KT11-C, CD Mechanisms

1-4

2.1.1

Address Relocation Mechanism

2-1

2.1.2

Memory Protection Mechanisms

2.1.2.1

Non-Resident/Read-Only Protection

2-4

2.1.2.2

Execute-Only Protection

2-4

2.1.2.3

Multiple Address Space Protection

2-5

2.1.3

Memory Management Statistics Mechanism

2-5

2.14
2.2

Trap/Abort Mechanism
PAR/PDR Registers

2-6
2-6

2.2.1

Page Address Registers (PAR)

2-7

2.2.2

Page Descriptor Registers (PDR)

2-8

2.2.2.1

Access Control Field (ACF)

2-9

2.2.2.2

Expansion Direction (ED)

2-9

2.2.2.3

Written Into (W)

2-10

2.2.2.4

Attention (A)

2-12

Page Length Field (PLF)

2-12

2.2.2.5

2.3

Memory Management Status Registers

2-13

Status Register O (SRO)

2-14

2.3.1.1

Abort-Nonresident

2-14

2.3.1.2

Abort-Page Length

2-14

2.3.1.3

Abort-Read Only

2-14

2.3.1.4

Trap-Memory Management

2-14

2.3.1.5

Bit 11

2-14

2.3.1.6

Enable Memory Management

2-15

2.3.1.7

Maintenance/Destination Mode

2-15

2.3.1.8

Instruction Completed

2-15

2.3.1

CONTENTS (Cont)
Page

2.3.1.9

Abort Recovery Information

2-15

2.3.1.10

Enable KT11-C, CD

2-15

2.3.2

Status Register 1 (SR1)

2-15

2.3.3

Status Register 2 (SR2)

2-16

Status Register 3 (SR3)

2-17

2.3.4
2.4

2-17

KT11-C, CD Operation
Console Operations

2-17

24.1.1

Single Step Mode

2-17

2.4.1.2

Address Display

2-17

2.4.1.3

Stepping Over 32K-Word Boundaries

2-17

2.4.2

Physical Address Determination

2-17

2.4.3

Protection Without Relocation

2-18

2.4.4

Communication Between User/Supervisor/Kernel Address

2-19

2.4.1

Space

2.4.4.1

Overlapping Physical Addresses

2-19

2.4.4.2

MFPI and MTPD Instructions Use

2-19

2.4.4.3

Control Information

2-20

2.4.5

Statistical Aids Use

2-20

2.4.6

I and D Space Use

2-21

2.4.7

I/O Operations

2-22

2.4.7.1

Kernel Mode Protection

2-22

2.4.7.2

Avoiding I/O Lockout

2-22

2.4.8

Processor Status Word

2-22

2.4.8.1

Explicit References to PS

2-22

2.4.8.2

Implicit Modification of the PS

2-23

2.4.9

Non-Recoverable Aborts

2-23

2.4.10

Page Fault Recovery

2-23

2.4.10.1

Definitions

2-23

2.4.10.2

Program Example

2-25

2.4.11

Fatal System Errors

2-28

CHAPTER 3

LOGIC DESCRIPTION

3.1

PDP-11/45,11/50, and 11/55 System Interface

3.2

KT11-C, CD Organization

3-2

3.2.1

System Address Path (SAP)

3.2.2

Status and Control Logic

3.3
3.3.1

3-2

PAR/PDR Registers
Page Address Registers (PAR)

3-5

3.3.1.1

Selection

3.3.1.2

Addressing

3-5

3.3.1.3

Writing Into a PAR

3-6

3.3.1.4

Reading From a PAR

3.3.2

Page Descriptor Registers (PDR)

3-6

3.3.2.1

Selection

3-6

CONTENTS (Cont)
Page

3.3.2.2

Addressing

3.3.2.3

Writing Into a PDR

3-7

3.3.24

Setting A or W Bits

3-7

3.3.25

Clearing A or W Bits

3.3.2.6

Reading From a PDR
Relocation Logic

3-7
3-7

34.1

Address Inverters/Buffers

3-7

34.2

12-Bit Adder

3-7

343
35

Relocation Multiplexer

Console Address Display and Control

3-8

3.5.1

ADDRESS Display

3-8

3.5.2

Console Mode Control

3-8

3.6

Abort and Trap Decode

3-8

3.6.1

Abort Control Logic

3-10

3.6.1.1

Non-Resident (NR) Page Fault

3-10

3.6.1.2

Resident Read-Only (RRO) Fault

3-10

3.6.1.3

Page Length Fault

3-10

3.6.2

Internal Register Inhibit

3-10

3.6.3

Memory Management Trap Decode

3-11

3.7

PAR/PDR Read Multiplexers

3-11

3.8

Unibus Address Drivers

3-11

3.9

Status Register 3 (SR3)

3-11

3.10

KT11-C, CD ROM and Decode

3-11

3.10.1

ROM Organization

3-12

3.10.2

ROM Outputs (3:1) and Decoders

3-14

3.10.2.1

RESTORE PS

3-14

3.10.2.2

SSRA JSR.30 (ROM (3:1) = 5)

3-14

3.10.2.3

BRK.30 (ROM (3:1) = 4)

3-15

3.10.24

AUTO DEC (ROM (3:1) = 3)

3-15

3.10.2.5

ONE CHANGED (ROM (3:1) =2 or 3)

3-15

3.10.3

ROM Outputs {16:04)

3-15

3.10.4

Kernel Space Control

3-16

3.10.5

Supervisor Space Control

3-17

3.10.6

User Space Control

3-17

3.10.7

I Space Control

3-17

3.11

Status Register 0 (SRO)

3-18

3.11.1

Abort Flags SRO(15:13)

3-18

3.11.2

Memory Management Trap (SRO Bit 12)

3-20

3.11.2.1

Enable Management Traps

3-20

3.11.2.2

Pre-Management Trap

3-20

3.11.2.3

Memory Management Hold

3-20

3.11.24

Writing Into SRO Bit 12

3-20

3.11.3

Trap Flag (SRO Bit 11)

3-20

3.11.4

DST MODE (SRO Bit 08)

3-22

CONTENTS (Cont)

Page

3.11.5

INSTR COMP (SRO Bit 07)

3.11.6

SRO Mode Field (SRO Bits (06:05))

3-22

3.11.7

Address Space — I/D (SRO Bit 04)

3-23

3.11.8

Page Number (SRO Bits (03:01))

3-23

3.11.9

KT11-C, CD Relocating (SWO Bit 00)

3-23

3.12

Status Register 1 (SR1)

3-22

3-23

3.12.1

General Register Address

3-23

3.12.2

Autoincrement/Autodecrement

3-23

3.12.3

Examples of SR1 Loading

3-24

3.13

Status Register 2 (SR2)

3-24

3.14

Internal Data Bus Multiplexers

3-25

3.15

KT11-C, CD Memory Management Timing

3-26

3.15.1

Event Times Related to Memory Cycles

3.15.2

Address Relocation Timing

3-26

3.15.3

Internal Register Access Timing

3-26

3.16

Internal Register Control

3-26

3.16.1

PAR/PDR Decode and Control

3-31

3.16.2

SSR Decode and Control

3-31

3.16.2.1

SSR REG

3-31

3.16.2.2

INT SR3

3-31

3.16.3

Internal Register Fast Decode

3-31

CHAPTER 4

INSTALLATION AND MAINTENANCE

4.1

Installation

4.2

Diagnostics

4-1

4.3

Troubleshooting Test Procedures

4-2

APPENDIX A GLOSSARY

A-1

APPENDIX B REFERENCE LITERATURE

B-1

APPENDIX C IC DESCRIPTIONS

C-1

ILLUSTRATIONS

Figure No.

Title

1-1

System Block Diagram

2-1

Basic KT11-C, CD Relocation Mechanism

2-2

Page
1-2

Relocation of a 32K-Word Program into 124K-Word Physical

2-3

Memory

2-3

Construction of an 18-Bit Physical Address

2-3

ILLUSTRATIONS (Cont)

Figure No.
2-4

Title
Comparison of Non-Reentrant and Reentrant Program Space

Requirements

Page
24

2-5

KT11-C, CD Memory Management Unit PAR/PDR Registers

2-6

Page Address Register (PAR) Format

2-7

Page Descriptor Register (PDR) Format

2-9

2-8

Example of an Upward Expandable Page

2-10

2-9

Example of a Downward Expandable Page

2-11

2-10

Format of Status Register 0 (SR0)

2-13

2-11

Format of Status Register 1 (SR1)

2-16

2-12

Format of Status Register 2 (SR2)

2-16

2-13

Format of Status Register 3 (SR3)

2-17

2-14

Flow Chart for a Page Fault Recovery Routine

2-24

3-1

KT11-C, CD System Hardware Interface

3-1

3-2

KT11-C, CD Memory Management Unit, Block Diagram

3-3

PAR/PDR Addressing and Format

3-4

Sources of ADDRESS Display, Simplified Diagram

3-9

3-5

KT11-C, CD/KB11-A, D Abort Control Sequence

3-19

KT11-C, CD/KB11-A, D Trap Control Sequence

3-21

3-6

Examples of SR1 Loading

3-25

KT11-C, CD Timing Diagram

3-27

3-9

Address Relocation Sequence, Simplified Diagram

3-29

3-10

Internal Register Access Sequence, Simplified Diagram

3-30

3-8

TABLES

Table No.

Title

Page

1-1

Abridged Specifications Summary

1-5

2-1

PAR/PDR Address Assignments

2-8

2-2

Access Control Field Keys

2-3

Address Display Select Switch

2-18

Relating Virtual Address to PAR/PDR Set

2-18

2-5

Mnemonic Definitions

2-25

3-1

Address Bit Source

3-5

3-2

Address Display Sources

3-3

ROM Output Decoding

3-4

Truth Table for Constant Multiplexer Outputs

3-24

3-5

How KT11-C Events Relate to KB11-A Memory Cycles

3-28

3-12

vii

INTRODUCTION

The KT11-C, CD Memory Management Unit is a hardware option designed for use with the PDP-11/45, 11/50,
and 11/55 Programmed Data Processors. This manual:

®
®

Provides an understanding of the KT11-C, CD in a PDP-11/45, 11/50, and 11/55 system.
Explains the KT11-C, CD hardware and how it can be used to develop the memory management module
of a software operating system.

Describes the KT11-C, CD logic in sufficient detail to enable maintenance personnel to perform onsite troubleshooting and repair.

The KT11-C, CD interacts with the KB11-A and KB11-D Central Processor Units and operating system software
to achieve PDP-11/45, 11/50, and 11/55 system memory management objectives. For this reason, a description

of memory management system objectives and programming information is included in this manual.
Chapter 1 introduces the purpose and features of the memory management unit.

Chapter 2 describes the implementation of the features from a programming level. It also describes the
internal registers and their application, hints, and exceptions of interest to programmers.
Chapter 3 provides a detailed description of the logic.

Chapter 4 provides installation and diagnostic information and references the maintenance procedures provided in the PDP-11/45, 11/50 and 11/55 System Maintenance Manual (EK-11045-MM-007).
Appendix A is a glossary of terms.

Appendix B is a bibliography of references on operating systems memory management.
Appendix C contains IC descriptions.

The Index is an alphabetical list of subjects with the page number where the subject appears.

Detailed descriptions of the processor, console, Unibus, Fastbus, and memory logic that interface with the memory management unit are provided in the following related documents.

PDP-11/45, 11/50, and 11/55 System Maintenance Manual

EK-11045-MM-007

KB11-A/D Central Processor Unit Maintenance Manual

EK-KB11A-MM-004

MS11-A, B, C Memory Systems Maintenance Manual

EK-MS11A-MM-005

PDP-11/04, 05, 10, 35, 40, 45 Processor Handbook

EK-05138-75-070/20

CHAPTER 1
GENERAL DESCRIPTION

This chapter describes the features of the KT11-C, CD in “systems’ terms and also includes a specification
summary.

1.1

PURPOSE OF OPTION

The KT11-C, CD Memory Management Unit intercepts addresses generated by the processor (before they reach
memory
), processes the addresses received, and then transmits the processed addresses to memory. Address pro-

cessing is the main function of the memory management option. This processing or modification of addresses is

called relocation. Processing is termed relocation because it consists of adding a fixed constant to every processor
address. The location of the KT11-C, CD option in the PDP-11/45, 11/50, or 11/55 system is shown in Figure 1-1.
The KT11-C is used as memory management for the KB11-A Central Processor and the KT11-CD is used as memory management for the KB11-D Central Processor.
The terms and definitions contained in Appendix A and referred to in this manual are consistent with industry-

accepted definitions.

1.2

PREREQUISITE

The KT11-C, CD Memory Management Unit is required on all systems with more than 28K of main memory (bi-

polar, MOS, and core). The option should also be considered for systems with real-time and timesharing applications as well as any system that runs user programs under a control or monitor program. For a narrative

description of the PDP-11/45, 11/50, and 11/55 systems’ ability to support timesharing and real-time operating
systems, refer to Paragraph 4.3 in the KB11-A/D Central Processor Maintenance Manual.

1.3

FEATURES

The KT11-C, CD features outlined below are described in detail in this manual. The KT11-C, CD option:

expands the basic 28K-word memory capability to 124K words.

provides dynamic read-only and execute-only memory protection.

provides up to 16 relocatable, variable length pages per processor mode.

ensures protection of operating system and user programs by implementing separate address spaces for
the Kernel, Supervisor, and User modes.

®
1.3.1

provides additional advanced memory management capabilities.
Memory Protection

The memory management unit enables the user to protect one section of memory from access or destruction by
programs located in another section. The KT11-C, CD divides the memory into sections called pages. Each

1-1

=0 0iog
SvNBIN

LNdNT

——— a

(ASlHoONW9I0N8) 7oNILVO>NTd Nb]

1 il

ANOWIW W3LSAS

S30IA3Q

‘310N

3S9VHVOLWSS301A34

N AN

AVHLINIGD

1-2

(d 4)

individual page has a protection or access key associated with it that restricts access to the page. With the memory
management unit, a page can be keyed non-resident (memory neither readable nor writable), read-only (no write

or store operations to memory) or execute-only (only instructions, immediate operands, absolute addresses, and
index words can be accessed from memory). These three types of protection in association with other features

of the KT11-C, CO erable the user to develop an ultrareliable computer operating system. With the non-resident
key, memory not specifically assigned to a program can be made unavailable to it. As a result, program errors are

unable to execute unwanted material left over from some other process, and they cannot modify any other programs. The read-only key protects data bases and pure code sections from malicious or accidental destruction
while allowing them to be accessed. With User mode programs, the execute-only feature allows proprietary codes
to be executed but not copied.

1.3.2

Relocation/Virtual Memory

Often it is desirable to load a program into one set of locations in memory and then execute it as if it were located in another set of locations, €.g., when several user programs are simultaneously stored in memory. When
any one program is running, it must be accessed by the processor as if it were located in the set of addresses beginning at 0. This process is called relocation. When the processor accesses program location 0, an address base
(base address) is added to the address; thus, the relocated O location of the program is accessed. This same base

address is added to all references while the program is running. A different base address is used for each of the
other programs in memory.

Processor-generated addresses differ from those that address memory; thus the processor addresses are sometimes

termed virtual addresses, and the memory addresses termed physical addresses. The memory management option
specifies relocation on a page basis, which allows a large program to be loaded into discontiguous pages in memory. This ability eliminates the need to shuffle programs to accomodate a new one. It also minimizes unusable
memory fragments, allowing more users to be loaded in a specific memory size.

In timesharing systems with swapping, relocation eliminates the need to “relink” a program when it is swapped
into a different memory location.
1.3.3

Memory Expansion

The relocated address is an 18-bit address that can access 128K words of address space, enabling the memory
management option to expand the accessable address space of a program from 32K to 128K. Expanding the address space permits larger programs to be handled and allows several programs to occupy the memory at once.

In addition, the KT11-C, CD option provides for expansion into multiprocessor systems where typically the
total memory exceeds 28K words.

1.3.4

Variable Size Pages

A program and its data may occupy as many as 16 pages in the memory. The size of each page varies and each
page can be any multiple of 32 words up to 4096 words in length. These features enable small areas in memory
to be protected, i.e., stacks, buffers, etc., and also enable the last page of a program exceeding 4K words to be of

adequate length to protect and relocate the remainder of the program. As a result, the page fragmentation problem inherent with fixed length pages is eliminated. With the relocation mechanism, the base address of each
page can be any multiple of 32 words in the 128K physical address space, thus ensuring compacted code. Finally, the variable page size enables pages to be dynamically changed at run time.

1.3.5

Page State Information

The memory management unit provides two bits of active page state information: an “accessed” bit and a
“written into” bit. These bits are read by the operating system and indicate whether the page has been accessed

1-3

and, if so, whether it was written into. The accessed bit is used with operating system programs to determine
which page should be overlaid with the new program page in systems that swap programs back and forth from a

disk. The written into bit is used to determine whether the page to be overlaid must be swapped back to the
disk or whether it is identical to a copy already there.

1.3.6

Instruction/Data Spaces

The memory management unit can relocate data and instruction references with separate base address values;
thus, it is possible to have a user program of 64K words consisting of 32K of pure procedure and 32K of data.
Moreover, a convenient means of building reentrant shared programs is provided (these programs keep a separate
data area for each user). The ability of the KT11-C, CD option to relocate information with separate base address
values enables shared compilers, assemblers, editors, and supervisors to be developed, in addition to providing an
“execute-only” form of protection. With this form of protection, alterable data is automatically separated from
reentrant code, and it is impossible to read any information relocated by an instruction base address as data.

1.3.7

Kernel/Supervisor/User Spaces

The KT11-C, CD provides three separate sets of pages (spaces) for use in the processor’s Kernel, Supervisor, and
User modes. These sets of pages increase system protection by physically isolating User programs from service
Supervisor programs and the basic Kernel program. The service programs (compilers, editors, file system,
assemblers, etc.) are also separated from the Kernel program (exception handling, I/O, memory management, etc.).
Separate relocation register sets greatly reduced the time necessary to switch context between modes. The 3-space
(page) construction also aids the user in designing an operating system that has clearly defined communications,
is modular, and is easily debugged and maintained. During development cycles, these features result in time and
cost savings;-in the final system design, they result in an efficient and reliable system.

1.3.8

Program vs Stack Pages

PDP-11

stacks expand by pushing words into lower addresses and thus grow downward; procedure sections in-

crease by growing upward into higher addresses. All memory pages can be expanded by adding lower addresses

(stack) or higher addresses (procedure, data). As a result, both stack and program pages are easily dynamically
expanded.

1.3.9

Fault Recovery

Four status registers record all information necessary to recover from a page fault. This information comprises
the page number that faulted, the type of violation that caused the fault (exceeded length, read-only violation,
etc.), and all information needed to easily restart the faulting instruction once the offending address has been

made resident in memory.

1.3.10

Statistical Traps

Three protection keys will cause a trap, i.e., an automatic transfer of program control to location 250 at end of
current instruction. The trap feature is useful for gathering frequency-of-page-use statistics. One protection key
traps on a read access to a read-only page; a second key traps on either a read or a write access from a read/write

page; and the third key traps only on a write to a read/write page.

1.4

KT11-C, CD MEMORY MANAGEMENT UNIT SPECIFICATIONS

Table 1-1 is a summary of specifications and technical characteristics of the KT11-C, CD.

1-4

Table 1-1

Abridged Specifications Summary

Characteristic
Memory Expansion

Specification or Descfiption
Expands KB11-A, D CPU memory address capability up to 124K
words.

Interface

Address line outputs compatible with PDP-11 Unibus and KB11-A, D

Fastbus.
Timing

Timing derived from basic KB11-A, D processor TIG module.

Delay

Adds 90 ns to every memory reference when enabled.

Modes of Operation

Implements the KB11-A, D processor Kernel, Supervisor, and User
modes.

Available Pages

Provides sixteen 4K-word pages for each module. (Eight for I space
and eight for D space.)

Page Length

A page can vary in length from one 32-word block up to 128

32-word blocks. Maximum page length is therefore 4096 words.

Program Capacity

Eight 4096-word pages will accommodate 32K-word programs. Use
of I'and D space can provide 64K-word capacity (32K words of program and 32K words of data).

Page Fault Recovery
Physical Description

Contains status registers that allow full recovery from page faults.
Option consists of two standard hex modules (15 X 8.5 in.) that
mount in KB11-A, D backplane assembly.

SAP Module M8107
SSR Module M8108 (-YA)

Located in slot 14. Replaces SJB Module M8116, when installed.

Located in slot 13. M8108 for the KT11-C. M8108-YA for the
KT11-CD.

Power Requirements

DC Power (Max.)

40 watts (8 A @5 Vdc)

AC Power (Max.)

80 watts (273 Btu/hr)

AC Current

11/45, 50, 55 -CA

0.8 Arms AC®@ 115 Vac

11/45, 50, 55 -CB

0.4 Arms AC @230 Vac J

Environmental

Provided by CPU power system.

Refer to overall PDP-11/45, 50, and 55 specifications listed in

PDP-11/45, 11/50, and 11/55 System Maintenance Manual,
EK-11045-MM-007.

1-5

CHAPTER 2

OPERATION AND PROGRAMMING

This chapter describes the relocation, protection, and abort mechanisms of the KT11-C, CD, all registers available
to the programmer, and operating hints and procedures.
2.1

BASIC KT11-C, CD MECHANISMS

2.1.1

Address Relocation Mechanism

The current processor mode (Kernel, Supervisor, or User) bits (bits 14 and 15 in the processor status word) select
one of three sets of 16 registers to serve as the page base on the current access. The logic, in combination with

the processor address selects either the subset of eight instruction base registers or the subset of eight data base

registers within the set. All instructions, index words, absolute addresses, and immediate operands use the instruction base registers. All other references uses the data base registers. Bits 13, 14, and 15 of the processor address
are then employed as a 3-bit encoded index into the eight register subsets previously selected. This encoded index
selects a specific base (relocation) register, and thus for each memory reference, one of 48 base registers is
selected to perform the address relocation.

The content of the selected base register is an initial or base value in the physical address space. The base value
is always a multiple of 32 words; as a result, the lowest 6 bits of the base address (bit O specifies byte address on
the PDP-11) are always 0. In actuality, only the upper 12 bits of the base address are stored in the base registers
because the lower 6 bits are by implication 0.

To form the final physical address, a displacement from the base specified by the lowest 13 bits of the processor
address (the upper 3 bits have been stripped off as an index into the base registers) is added to the base value con-

tained in the base register. Note that this mapping technique allows pages of variable length (32 to 4096 words)
to be packed efficiently in physical memory. Also note that the use of pages with less than 4096 words will re-

sult in discontiguous virtual address spaces because in the virtual address space a page begins on a 4096-word
boundary.

As a specific example consider program A, starting address 0, is relocated by the constant 6400, which provides
an address of 6400 (Figure 2-1). If the next processor virtual address is 2, the relocation constant will then cause

physical address 64028 , which is the second item of program A to be accessed. When program B is running, the
relocation constant is changed to 1000,. Then program B virtual addresses starting at O are relocated to access
physical addresses starting at 100000,. Using the active page address registers to provide relocation eliminates

the need to “relink” a program each time it is loaded into a different physical memory location. To the processor, the program always appears to start at the same address. Note that the base address is stored in a Page Address Register (PAR).

PROCESSOR VIRTUAL ADDRESS
A

1514|13 12l11|10|9|8l7|6 5[4]3'2[1@
PAGE

NUMBER

INSTRUCTION

DATA ACCESS

1 OF 48
BASE REGISTERS

SELECTED

NUMBER

BLOCKS

ABOVE PAGE

LOCATION

WITHIN

BLOCK

L
A A
.

R MODE {

KERNEE/SUPER/

PAGE BASEF
72 8178
STARTING BLOCK OF NUMBER PAGE

INPUT

F——

HTHTHHTHTITITTIT

I FULL ADDER
LT
OUTPUT

Llwlwlmlwlwlnlwl nRnBRBAnns
J

PHYSICAL ADDRESS

Figure 2-1

11-1214

Basic KT11-C, CD Relocation Mechanism

The relocation example shown in Figure 2-2 illustrates several points about memory relocation. These points
a.

are:

Although the program appears to be in contiguous address space to the processor, the 32K-word vir-

tual address space is actually relocated to several separate areas of physical memory. As long as the
total available physical memory space is adequate, a program can be loaded. The physical memory
space need not be contiguous.

Pages may be relocated to higher or lower physical addresses, with respect to their virtual address

ranges. In Figure 2-2, page 1 is relocated to a higher range of physical addresses, page 4 is relocated to

a lower range, and page 3 is not relocated at all (even though its relocation constant is non-zero).

All of the pages in the example start on 32-word boundaries.

Each page is relocated independently. There is no reason two or more pages could not be relocated to
the same physical memory space. Using more than one page address register in the set to access the
same space is one way of providing different memory access rights to the same data, depending on

which part of a program was referencing that data. Further information on memory protection is provided in Paragraph 2.1.2. In Figure 2-2, note that the same relocation constant is assigned to Pages 4
and 6. As aresult, virtual addresses within both address ranges access the same physical addresses in

memory, using separate page address registers.

When the KT11-C, CD Memory Management Unit option is added to the PDP-11/45, 11/50, or 11 /55 system, the

16-bit KB11-A or KB11-D address output is no longer interpreted as the direct physical address of a device or a
memory location. Instead, it is considered a 16-bit virtual address that contains information to be used by the

KT11-C, CD to construct an 18-bit physical address. Figure 2-3 shows how the 18-bit physical address is constructed. Virtual address bits (15:13) are interpreted as an active page field to select one of eight page registers in
a set. Virtual address bits <12:06) provide the block number (0 to 177 ) within the page; VA (05:00)

indicate the

displacement within each 32-word block. The Page Address Register (PAR) contains a Page Address Field (PAF)
that is written into the PAR under program control when the program page is defined. Consider the PAF as the

2-2

base address of the page. The block number, VA (12:06), is added to the base address PAF (11:00) to provide

12 most significant bits of the physical address. This address and virtual address bits VA (05:00) (unchanged

the

relocation) form the 18-bit physical address.

WAX
PROCESSOR

KT11-C,CD

VIRTUAL ADDRESS

RANGES

PHYSICAL

NO. | PAGE BASE

ADDRESSES
S

o | a0ooxx

020000- 037776

040000~ 057776
060000- 077776

¥K

MEMORY

PAGE

000000- 017776
01777
| 4K

poge

D prees

| 3200xx

.
—

400000

2 | 2500xx \W
3 | oeooxx
4 | 0200xx \ ]
"
B

100000~ 117776

120000
- 137776

140000- 157776

6 | 0200xx

160000~ 177776

7 | 1s00xx

oTM

287776 | pAGE
2 | «+ig
250000

| 1000xx

e A

]

150000 | PAGE
7{ 4/c
e

17776
100000}
PAGE 5] %<

or7776

060000 } PAGE 3| 4K

e
I

037776 |
020000/
e

PAGES
486

—

|4k

000000
H-3953

Figure 2-2

Relocation of a 32K-Word Program

into 124K-Word Physical Memory

PUNE——

06 05

BLOCK

NUMBER

APF SELECTS PAGE ADDRESS

WORD_

NUMBE
Y

PAR &

FROM: PROCESSOR

EXAMPLE: 157746 g

APF

129 DlecKs

PAGE ADDRESS FIELD
EXAMPLE:5460g

loo
1%y Bytes per Block
1o

PAF<17:06
> =
BASE ADDRESS OF PAGE

1109
1

8
i

716

001

5460XX

CHANGED

]

A
t

VA< 05:00>
IS NOT

FULL ADDER X

EXAMPLE :565746g

565746

18-8BIT PHYSICAL ADDRESS

0O0O0

17746

10
9

PA <17:06 >

JL
1

6,5
4

0:1t
1 O
3

VA <05:00>

TO UNIBUS A ADDRESS DRIVERS AND TO FASTBUS ADDRESS LINES
H-1027

Figure 2-3

per

— -

)

ADDRESS

> F--—+

16-BIT VIRTUAL

Construction of an 18-Bit Physical Address

PAR 7 =

7609

For

TS0

feye

Jor Js

BlocK

2.1.2 Memory Protection Mechanisms

Three address protection mechanisms in the KT11-C, CD provide non-resident and read-only protection, executeonly protection, and internal protection for the three processor mode address spaces.

2.1.2.1 Non-Resident/Read-Only Protection — A Page Descriptor Register (PDR) is selected in the same manner
as a Page Address Register (PAR). After the selection occurs, three bits from the PDR are decoded as an access
key. If the access rights designated by the key are inconsistent with the current memory reference, the memory
reference is not completed and an abort to Kernel D space 250 occurs.

When the access key is set to 0, the page is defined as non-resident, and an immediate abort prevents any attempt
by a program to access a non-resident page. Using this feature to provide memory protection, only those pages

associated with the current program are set to legal access keys. The access control keys of all other program

pages are set to 0, which prevents illegal memory references.

The access control key for a page can be set to 2, allowing read (fetch) memory references to the page but imme-

diately aborting any attempt to write into the page. This read-only type of memory protection can be afforded
to pages that contain common data, subroutines, or shared algorithms. This type of memory protection makes

certain that access rights to a given information module are user-dependent, i.e., the access right to a given information module may be varied for different users by altering the access control key.

A Page Address Register in each of the sets (Kernel, User, and Supervisor modes) may be set up to reference the
same physical page in memory and each may be keyed for different access rights. For example, the User access
control key might be 2 (read-only access), the Supervisor access control key might be 0 (non-resident), and the
Kernel access control key might be 6 (allowing complete read/write access).

2.1.2.2 Execute-Only Protection — The execute-only type of memory protection is part of an overall ability to
use reentrant software, which prevents excessive use of memory space when a program is provided for several
users. Such programs can be written in two parts. One part contains pure code that is not modified during execution and can be used to simultaneously service any number of users. For example, the pure code portion of
FORTRAN can service multiple FORTRAN users. A separate second part of the program belongs strictly to
each user and consists of the code and data that is developed during the compiling process. This portion is

stored in a separate page of memory. Figure 2-4 shows a comparison of memory space for non-reentrant and reentrant systems.

The KT11-C, CD hardware can differentiate between pure code
H
3
3
immediate oper
are instructions,
memory references (which

FORTRAN 1
COMPILER

FORTRAN
CODE
PURE

ands, index words, and absolute addresses) and all other mem]
)
ory references. When this feature is enabled under program

COMPILER 2

FORTRAN

USER 1

control, the KT11-C, CD will take the “pure code” portion of such

FORTRAN

USER 2

USER 3

a program from an I (instruction) space page. All other data

COMPILER 3

SPACE SAVED _

will be put into an associated D (data) space page. Any illegal

NON-REENTRANT

REENTRANT
11-1034

attempt by an unauthorized user to read from the executeonly I space will be relocated to a separate D space page. Because the I and D space pages have separate PDRs, access con-

trol can be keyed differently for each page. For example, the

Figure 2-4

Comparison of Non-Reentrant

and Reentrant Program Space Requirements

D space access control key could be set to O to cause a non-

resident abort, or, as an alternative, the base address of the D space page could be set up to map over some other
part of a user’s program. In any case, the D space PDR must not be set so that a user can write into the pure
code I space. The difference between the read-only protection described in Paragraph 2.1.2.1 and execute-only

protection is that the contents of execute-only pages cannot be read as data. This feature is particularly useful

in protecting proprietary programs from some users. Paragraph 2.4.6 describes I and D space more fully.
In the special case when in User mode and the previous mode specified by the processor status is also User mode,
the action of the MFPI instruction is modified so that the read is via the D relocation registers. In this manner,
the integrity of the execute-only mode is reserved.

2.1.2.3

Multiple Address Space Protection — The three completely separate PAR/PDR sets provided by the KT11-

C, CD for each mode of processor operation (Kernel, Supervisor, and User) give the timesharing system another

type of memory protection. The mode of operation is specified by the Processor Status Word current mode field.
The active page register sets are enabled as follows:

PS<(15:14)

PAR/PDR Set Enabled

Kernel mode

Supervisor mode

Illegal (all references aborted)

User mode

Thus, a User mode program is relocated by its own PAR/PDR set, as are Kernel and Supervisor programs. It is
therefore impossible for a program running in one mode to accidentally reference space allocated to another

mode when the active page registers are set correctly by a monitor program. For example, a user cannot transfer
to Supervisor or Kernel space. The Supervisor mode address space may be reserved by the system to accommo-

date resident compilers, utility programs, and other shared resource programs. The Kernel mode address space

may be reserved for resident system monitor functions, such as the basic Input/Output Control (IOC) routines,
memory management trap handlers, abort handlers, and timesharing scheduling module. By dividing the types
of timesharing system programs functionally between the Kernel, Supervisor, and User modes, a minimum

amount of space control housekeeping is required as the timeshared operating system sequences from one user
program to the next. For example, only the User PAR/PDR set needs to be updated as each new user program is

serviced. The three PAR/PDR sets implemented in the KT11-C, CD Memory Management Unit option are shown
in Figure 2-5.

2.1.3

Memory Management Statistics Mechanism

A timeshared system swaps programs or parts of programs in and out of memory using secondary storage facilities such as disk or drum systems. In a swapping environment, the operating system must provide the software
routines that decide what programs should be swapped and when and how these programs can be swapped between memory and secondary storage. The operating system routines can be simple or complex depending on
system requirements, e.g., the amount of overhead time that can be tolerated. The operating system may also
have to decide which active page is least likely to be required in the immediate future and may therefore be

swapped out to make memory space available for a new program. To make such a memory management deci-

sion, the operating system requires statistics on the use of active pages. Some indication of whether a program

has been modified during its residence in memory is also desirable. If it has been modified, the modified program must be swapped (re-written) into secondary storage. If no modification has been made and the program
can always be re-called from secondary storage, the space it occupies in memory can be overlayed without swapping delay. The KT11-C, CD logic provides the kind of information required by an operating system to gather memory management statistics on the use of active pages. The availability of this information in the hardware re-

duces the overhead time of any routine, simple or complex, in the efficient management of memory. In the

KT11-C, CD the Page Descriptor Register associated with

KERNEL

PAR/PDR

REGISTERS

each active page includes a W (written into) and an A

(attention) bit. When any active page is written into, the

;

W bit is set by the logic; therefore, by testing the W bit the

memory management software routine can decide whether

a page can be overlayed or if it needs to be swapped out.

- SPACE

The A bit has several uses. To use this feature the system

PDR

SUPERVISOR

programmer first enables the memory management trap

logic.

PAR

PAR/PDR

1 SPACE

:?5

struction fetch)

PAR

PDR

USER

PAR/PDR

Memory management trap on write

¢c.

Memory management trap on read or write.

;

431

accessed as specified and a resultant memory management

trap occurs. The vector at trap location 250 Kernel address

’

1 _SPACE

PAR

D _SPACE

2
v

’

space causes the operating system routine to service the
memory management trap.

PDR

REGISTERS

Then, the A bit for the active page is set when the page is

D _SPACE

pages of interest for special trap conditions. Access control

Memory management trap on read (including in-

PDR

REGISTERS

keys are provided to cause:

2 SPAct

3
PAR

He can then set the access control keys of the active

~om
11-1029

The routine can test the A bit

to acmilmulat? .statl'stws Ofl the use of that l?age. When a
swapping decision is required of the operating system, these

Figure 2-5

KT11-C, CD Memory Management
Unit PAR/PDR Registers

statistics can be examined to determine the more active
pages (which might therefore be retained in memory).

2.1.4

Trap/Abort Mechanism

Memory references that violate the protection keys set in the KT11-C, CD cause an interrupt in the processor.
The interrupt process is described in Paragraph 5.3 of the PDP-11/04, 05, 10, 35, 40, 45 Processor Handbook. In

KT11-C, CD aborts and traps, the new PC for the abort/trap service routine is taken from 250 in Kernel virtual D
space, while the new PS is taken from 252. No other interrupts use 250 as a trap vector. Note that both abort and
statistical traps are taken to 250.

Non-resident, read-only, and page length violations cause an interrupt to the processor before the reference is
made. Memory management traps occur only at the end of complete instructions. Paragraphs 3.11.1 and 3.11.2

describe the trap/abort logic and inciude two system diagrams that indicate how the interrupt is implemented in
the logic. The order of interrupt service is listed in Appendix C of the PDP-11/04, 05, 10, 35, 40, 45 Processor

Handbook.

2.2

PAR/PDR REGISTERS

The contents of the Page Address Register (PAR) and the Page Descriptor Register (PDR) describe a merriory
page.

The KT11-C, CD provides three sets of 16 PAR/PDR pairs. As indicated in Figure 2-5, one PAR/PDR set is used
to reference memory while the processor is in Kernel mode, another in Supervisor mode, and the third in User
mode. Each set is subdivided into two groups: one for reference to instruction (I) space and one for reference
to data (D) space. Figure 2-5 shows the organization of the three sets. Each pair consists of a Page Address

Register (PAR) and a Page Descriptor Register (PDR). These registers are always used as a pair and contain all
the information required to locate and describe the current active pages for each mode of operation.
The current mode bits (bits 14 and 15) of the Processor Status Word determine which set will be referenced for

each memory access. A program operatihg in one mode cannot use the PAR/PDR sets of the other two modes
to access memory. Thus, the three sets are a key feature in providing a fully protected environment for a time-

shared multiprogramming system. The virtual address value determines which page within a set is to be used.
This correspondence is listed below:

Page No.

Virtual Addresses

000000 — 017777

020000 — 037777

040000 — 057777

060000 — 077777

100000 — 117777

120000 — 137777

140000 — 157777

160000 — 177777

Finally the use of the reference (part of an instruction or data access) determines whether the I space PAR/PDR

set or the D space PAR/PDR set is used. Each PAR and PDR of every set is assigned to a specific processor 1/O
address. Table 2-1 is a complete list of address assignments.
NOTE

Unibus devices cannot access PARs or PDRs.
In a fully-protected multiprogramming environment, only a program operating in Kernel mode would be allowed
to access the PAR and PDR locations for the purpose of mapping a user’s programs. However, there are no restraints
imposed by the KT11-C, CD logic that will prevent Supervisor or User mode programs from accessing these
registers. PAR and PDR are not cleared by INIT. The option of implementing such a feature in the operating sys-

tem and thus explicitly protecting these locations from user’s programs is available to the system software designer.

2.2.1

Page Address Registers (PAR)

The Page Address Register (PAR) shown in Figure 2-6 contains the base address of the page in the form of a 12bit Page Address Field (PAF). Bits 15—12 of the PAR are not implemented in the hardware.
The PAR can also be thought of as a relocation register containing a relocation constant or as a base register containing a base address. Either interpretation indicates the basic function of the PAR in the relocation scheme.
Note that the PAF is interpreted in address calculations as a multiplier of 32, i.e., when used as a base register,

the lowest 6 bits are assumed to be 0. The bit stored in bit 0 of the PAF becomes bit 6 of the page base address,
bit 1 of the PAF, bit 7 of the page base address, etc. Thus, bit 11 of the PAF becomes bit 17 of the page base

address.

PAGE ADDRESS FIELD

(PAF)

11-1036

Figure 2-6

Page Address Register (PAR) Format

Table 2-1

PAR/PDR Address Assignments
Kernel

5/& « @

I Space

Jn 5%#04 2‘/ v ns
-

D Space

No.

PAR

PDR

No.

PAR

PDR

A ddrasses

772320

772342

772302

772360

772340 | 772300

772362

772322

772344

772304

772364

772324

772346

772306

772366

772326

772350

772310

772370

772330

772352

772312

6
7

772354
772356

772314
772316

5
6

772372
772374

772332
772334

772376

772336

L//cfl"a’l

T dox

Supervisor

I Space

D Space |

No.

PAR

PDR

No.

PAR

PDR

0
1
2
3
4
5
6

772240
772242
772244
772246
772250
772252
772254

772200
772202
772204
772206
772210
772212
772214

0
1
2
3
4
5
6

772260
772262
772264
772266
772270
772272
772274

772220
772222
772224
772226
772230
772232
772234

772256

772216

772276

772236

User

I Space
No.

PAR

PDR

No.

PAR

PDR

777640

777600

777660

777620

1
2
3
4
5
6
7

2.2.2

"D Spfi‘cg

777642
777644
777646
777650
777652
777654
777656

777602
777604
777606
777610
777612
777614
777616

1
2
3
4
5
6
7

777662
777664
777666
777670
777672
777674
777676

777622
777624
777626
777630
777632
777634
777636

Page Descriptor Registers (PDR)

The Page Descriptor Register (PDR) contains page expansion, direction, page length, and access control (Figure
2-7).

(PLF)

FIELD

7Y
w //////

PA GE LENGTH H

ACF
11-1037

Figure 2-7

2.2.2.1

Page Descriptor Register (PDR) Format

Access Control Field (ACF) — The ACF is a 3-bit field (occupying bits 2—0 of the PDR) that describes

the access rights to this particular page. The access codes or “keys” specify the manner in which a page may be
accessed and whether or not a given access should result in a trap or an abort of the current operation. A mem-

ory reference that causes an abort is not completed and is terminated immediately. Hence an aborted “read”
reference does not obtain any data from the location, and an aborted “write” reference does not change the data
in the location. A memory reference that causes a trap is completed. When a memory reference causes a trap,
the trap does not occur until the entire instruction has been completed. Aborts are caused by attempts to access
non-resident pages, page length errors, or access violations, such as attempting to write into a read-only page.
Traps are used as an aid in gathering memory management information.

In the context of access control, the term write is used to indicate the action of any instruction that modifies
the contents of any addressable word. A write is synonymous with what is usually termed a store or modify in

many computer systems. Table 2-2 lists the ACF keys and their functions. The ACF is written into the PDR

under program control.

Table 2-2

Access Control Field Keys

Function

AFC

Key

Description

000

-0

Non-resident (NR)

Abort any attempt to access this non-resident page.

001

Read only and trap (RROT)

Trap to location 250 in Kernel D space after read.

010

Resident read only (RRO)

Abort any attempt to write into this page.

011

Illegal

Unused. Reserved for future use. Abort any access

Abort any attempt to write into this page.

attempt.

100

Resident read/write and trap
(RRWT)

Memory management trap to location 250 in Kernel D space upon completion of a read or write to
this page.

101

Resident read/write and trap

Allows read/write of page and traps to location 250

when write (RRWTW)

in Kernel D space upon completion of a write.

110

Resident read/write (RRW)

Read or write allowed. No trap or abort occurs.-

111

Illegal

Unused. Reserved for future use. Abort any access
attempts.

2.2.2.2 Expansion Direction (ED) — The ED bit located in PDR bit position 03 indicates the authorized direction in which the page expands. A logic 0 in this bit (ED = 0) indicates that the page expands upward from relative zero (page base address). A logic 1 in this bit (ED = 1) indicates that the page expands downward toward
relative zero (page base address). The ED bit is written into the PDR under program control. When expansion
is upward (ED = 0), the page length is increased by adding blocks with higher relative addresses. Upward

expansion is usually specified for program or data pages to add more program or table space. An example of page

expansion upward is shown in Figure 2-8.

PAR

000

001

PDR

111

000

0101001

PAF=O170:I
PLF = 51g = 41,,=BLOCK

0000 O 110

NO.

ED=0= UPWARD EXPANSION

ACF=6=READ/WRITE

NOTE:

TO SPECIFY A BLOCK LENGTH OF 42 FOR AN UPWARD EXPANDABLE
PAGE, WRITE

HIGHEST AUTHORIZED

BLOCK NO. DIRECTLY

INTO HIGH

BYTE OF PDR. BIT 15 IS NOT USED BECAUSE THE HIGHEST ALLOWABLE BLOCK
NUMBER

IS 177

VIRTUAL

ADDRESS

BLOCK NO
> PDR

BLOCK NO.+PAGE

70000000

BLOCK ‘779/

)

ADDRESS

771

RANGE

OF POTENTIAL PAGE
EXPANSION BY

CHANGING THE PLF

BLOCK 1764

| ANY BLOCK NUMBER

GREATER THAN 41,4 (51g)

5> 51y)
(va<12:06

ERROR (PLE)

)

LENGTH

WILL CAUSE A PAGE
LENGTH ABORT

BLOCK 524

i)|
024176

BLOCK S1g

0170XX START

024100 | ~

024

BLOCKS

1XX

END

017276

AUTHORIZED

PAGE

BLOCK 2

LENGTH = 4210 BLOCKS

017200

OR O THRU 51g=

017176
017100
017076

BLOCK O
017000

p=»—BASE ADDRESS OF PAGE
11-1030

Figure 2-8

Example of an Upward Expandable Page (From the Base)

When expansion is downward (ED = 1), the page length is increased by adding blocks with lower relative addresses.
Downward expansion is specified for stack pages so that more stack space can be added. An example of page ex-

pansion is shown in Figure 2-9. Paragraphs 2.5.3 and 2.5.4 provide a description of the interaction of the ED bit
with the Page Length Field (PLF).

2.2.2.3

Written Into (W) — The W bit located in PDR bit position 06 indicates whether the page has been writ-

ten into since it was loaded into memory. W = 1 is affirmative. Note that the W bit is set independent of the

ACF key and the memory management enable bit (bit 9) in SRO. The W bit is automatically cleared when either
the PAR or PDR of a page is written into. It can only be set by KT11-C, CD control logic.

2-10

I’—ACTIVE PAGE REGISTER CONTENTS—-|
PAR

PDR

Ii)OO Q01 11 0001

LO101011O 0000 1 ch

———

|—

PAF=O170—_—,

PLF=126g = 869

ED=1= DOWNWARD EXPANSION

TO SPECIFY

WRITE

PAGE

LENGTH

COMPLEMENT

FOR

A DOWNWARD

BLOCKS

REQUIRED

IN THIS EXAMPLE,
A 42-BLOCK
PLF IS DERIVED AS FOLLOWS
:

PAGE

EXPANDABLE

INTO

HIGH BYTE

PAGE,
OF PDR.,

IS REQUIRED.

420 =52g ; TWO'S COMPLEMENT = 126

VIRTUAL

ADDRESS

BLOCK

NO.<PDR

BLOCK

NO.-= PAGE

LENGTH

ERROR (PLE)

938776 | | FirsT BLOCK OF DOWNWARD

BLOCK égé‘?oo

EXPANDABLE PAGE

0/7000

036676

200009

036600

037000

BLOCK 176
AUTHORIZED PAGE

036576

LENGTH=42 10 BLOCKS | BLOCK 175g

)
75005 Blo

036776

036500

0170XX

7126
126

—~—~—~—~—~~]

0316XX

Dty

0367XX

o3t676 |

BLOCK 126g
|

ffljd 6’05@

PAGE

BASE

‘5

BLOCKS —.

Top Aldress

520
S - Fof Bfes
R

START

BLOCKS

3/ 576:

END

37600

Lost Adlsess

031600
-

BLOCK

125g

A BLOCK NUMBER
REFERENCE LESS
g
THAN 126

ADDRESS RANGE
OF POTENTIAL PAGE

(VA <12:06> LESS THAN 126g)

EXPANS!ON BY
CHANGING THE PLF

WILL CAUSE A PAGE
LENGTH ABORT.

017100
7, C17076

BLOCK 077
7017000

/<—BASE ADDRESS OF PAGE
11-1031

Figure 2-9

Example of a Downward Expandable Page

(From Top of Page Toward Base)

In disk swapping and memory overlay applications, the W bit can be used to determine the pages in memory that

have been modified by a user. Those that have been written into must be saved in their current form; those that

have not been written into (W = 0), need not be saved and can be overlayed with new pages if necessary.
NOTE

The W bit cannot be set by a memory access of a KT11-C, CD
internal register or a memory access that causes an abort.

2-11

2.2.2.4 Attention (A) — The A bit located in PDR bit position 07 indicates whether any memory page accesses
caused memory management trap conditionsto be true. A =1 is affirmative. Trap conditions are specified by
the ACF. The following conditions will set the A bit.
1.

ACF =001 and read reference.

ACF=100.

ACF = 101 and write reference.

Note that the A bit is set independent of the memory management enable bit (bit 9) in SRO. The A bit is used
in the process of gathering memory management statistics for the purpose of optimizing memory use. The A bit
is automatically cleared when the PAR or PDR of the page is written into. It can only be set by the KT11-C, CD
control logic.

NOTE

The A bit cannot be set by a memory access of a KT11-C,
CD internal register or a memory access that causes an abort.

2.2.2.5 Page Length Field (PLF) — The 7-bit PLF is located in PDR bits <14:08). It specifies the authorized
length of the page in 32-word blocks. The PLF holds block numbers from 0 to 177, thus allowing any page
length from 1 to 128,, blocks. The PLF is written in the PDR under program control.

cocd : PLF (# 65 Glacks Daswed)~|

= [ost [ege! Blck #

PLF for an Upward Expandable Page

When the page expands upward, the PLF must be set to one less than the intended number of blocks authorized
for that page. For example, if 42, blocks are authorized, the PLF is set to 51, (41,,) (Figure 2-8). The
KT11-C, CD hardware compares the virtual address block number, VA (12:06), with the PLF to determine if the
virtual address is within the authorized page length. When the virtual address block number is less than or equal
to the PLF, the virtual address is within the authorized page length. If the virtual address block number is greater
than the PLF, a page length fault (address too high) is detected by the hardware and an abort occurs. In cases
where the authorized page length is less than 4096 words, the virtual address space legal to the program is noncontighous. This is because the three most significant bits of the virtual address are used to select the PAR/PDR
set, and the unauthorized virtual addresses within the page space are “lost”. The operating system abort recovery

routines might include some form of dynamic memory allocation. Such routines would have to perform the fol-

lowing:

Determine the cause of the abort (page length fault).

Check the expansion direction bit (upward).

Allocate an additional block or more of memory space by incrementing the PLF in the case of an upward expandable page.

Correct the general registers modified by the partially completed operation.

Return control to the user program and thus allow the now legal virtual address memory reference to
be completed.

Note that Paragraph 2.4.10 contains such a recovery routine.

PLF for a Downward Expandable Page

I/ / : PLF: 2’5 Cop ef pe 03; fl/w/’; 093‘/"4/

The downward expansion capability for a page is intended specifically for those pages that are to be used as
stacks. In the PDP-11, a stack starts at the highest location reserved for it and expands downward toward the
lowest address as items are added to the stack. (S_ee Chapter S of the PDP-11/04, 05, 10, 35, 40, 45 Processor

2-12

Handbook for complete details.) When the page is to be downward expandable, the PLF must be set to authorize
a page length, in blocks, that starts at the highest address of the page, i.e., always block 1774. Figure 2-9 shows

an example of a downward expandable page. A page length of 42, , blocks is arbitrarily chosen so that the
example can be compared with the upward expandable example shown in Figure 2-8.
NOTE

The same PAF is used in both examples to emphasize that the
PAF, as the base address, always determines the lowest address
of the page, whether it is upward or downward expandable.

PAGE THAT SET
ABORT ERROR FLAGS

'
|

t ot

: NON-RESIDENT —] '
ABORT

ADDRESS:
777572

tt’— ENABLE KT11-C,CD

ABORT :PAGE LENGTH ERR

PAGE NUMBER

ADDRESS SPACE 1/D

ABORT: READ ONLY VIOLATION

MODE OF OPERATION

TRAP :MEMORY MANAGEMENT

INSTRUCTION COMPLETE

UNUSED

MAINTENANCE

ENABLE MEMORY
MANAGEMENT TRAPS

MODE

11-39
61

Figure 2-10

Format of Status Register 0 (SRO)

To calculate the value to be placed in the PLF for a downward expandable page proceed as follows.

Take the number of 32-word blocks to be authorized and create the negative of it in 2’s complement notation.
The 2’s complement is formed by negating each binary bit, then adding 1 to the result.

| Example:
524

= 0101010

bit negation = 1010101
add

1264

= 1010110

The same dynamic memory allocation routine can be used to recover from a page length abort. After determining that the page was downward expandable, the PLF would be decremented to allow downward expansion.
2.3

MEMORY MANAGEMENT STATUS REGISTERS

Aborts and traps generated by the KT11-C, CD logic are vectored through Kernel D space address location 250.
Status Registers SRO, SR1, and SR2 can be referenced by fault recovery routines to differentiate between an
abort and a trap, determine why the abort or trap occurred, perform the service routines required to recover

from the abort or handle the trap, and allow for program restart. The following paragraphs describe the formats
of each status register.

2-13

2.3.1

Status Register 0 (SRO)

SRO contains abort error flags, memory management enable and trap flag bits, plus other essential information
required by an operating system to recover from an abort or to service a memory management trap. The physi-

cal address of SRO is 777572. The SRO format is shown in Figure 2-10.
Bits 15—11 are the abort and trap flags, and can be considered to be in a “priority queue” in that “flags to the

right” are less significant and should be ignored. For example, a “non-resident’ abort service routine would ignore page length, access control, and memory management flags. A “‘page length” abort service routine would

ignore access control and memory management faults.

NOTE

Bits 15, 14, or 13, when set (abort conditions) cause the
KT11-C, CD logic to freeze the contents of SRO bits 1—7 and
and status registers SR1 and SR2 to facilitate recovery from

the abort.
The error flag bits 15—12 are enabled when an address is being relocated by the KT1 1-C, CD. This implies that
either SRO, bit 0 is equal to 1 (KT11-C, CD operating) or that SRO, bit 8 is equal to 1 and the memory reference
is the final one of a destination calculation (maintenance/destination mode).

Note that SRO bits 0, 8, and 9 can be set under program control to provide meaningful memory management
control information. However, information written into all other bits is not meaningful. Only that information
automatically written into these remaining bits as a result of hardware actions is useful as a monitor of the status

of the memory management unit. Setting bits 15—11 under program control will not cause aborts or traps to
occur. Bits 15—11 must be reset to 0 after an abort or trap has occurred in order to resume monitoring memory

management. Setting bits 15, 14, or 13 will, however, freeze the contents of SRO bits (1:7), Status Register 1

(SR1) and Status Register 2 (SR2).

2.3.1.1

Abort-Nonresident — Bit 15 is the “Abort-Nonresident” bit. It is set by attempting to access a page

with an access control field (ACF) key equal to 0, 3, or 7.
2.3.1.2

Abort-Page Length — Bit 14 is the “Abort Page Length” bit. It is set by attempting to access a location

in a page with a virtual address block number (Virtual Address bits{12:06)) that is outside the area authorized by

the Page Length Field (PLF) of the PDR for that page. Bits 14 and 15 of SRO may be set simultaneously by the
same access attempt.

2.3.1.3

Abort-Read Only — Bit 13 is the “Abort-Read Only” bit. It is set by attempting to write in a page with

an access key of 1 or 2.

2.3.1.4

Trap-Memory Management — Bit 12 is the “Trap-Memory Management” bit. It is set by a read opera-

tion that references a page with an ACF key of 1 or 4 and by a write operation with an ACF key of 4 or 5. The

functions of these ACF keys are listed in Table 2-2. Note that the “Enable Memory Management’’ bit (SRO, bit

9) must be a 1 for the “Trap-Memory Management”’ bit to be set.
2.3.1.5

Bit 11 — Bit 11

is a spare flag reserved for future use.

2-14

2.3.1.6

Enable Memory Management — Bit 9 is the “Enable Memory Management” bit. It can be set or cleared

by doing a direct write into SRO. If bit 9 is cleared, no memory management traps can occur. The A and W bits
will, however, continue to log potential memory management traps. When bit 9 is set to 1, the next memory
management trap condition will cause a trap, vectored through Kernel D virtual address 250.

NOTE If the instruction that clears bit 9 (to disable memory management) causes a potential memory management trap in the

course of any of its memory references prior to the one actually changing SRO, the trap will occur at the end of the instruc-

tion.

2.3.1.7

Maintenance/Destination Mode — Bit 8 specifies maintenance use of the memory management unit. It

is used for KT11-C, CD diagnostic purposes. For the instructions used in the initial diagnostic program, bit 8 is
set so that only the final destination reference is relocated. This bit must not be used for other purposes.

2.3.1.8

Instruction Completed — When an abort has occured, bit 7 indicates that the current instruction has

been completed and that the current memory references are caused by an interrupt or “T”’ bit, Parity, Odd
Address or Timeout traps.

2.3.1.9

Abort Recovery Information — When an abort occurs, bits {1:6) of SRO contain the information neces-

sary to determine which of the 48 pages caused the abort. Specifically, bits {1:6) contain the processor mode,
whether I or D space, and which 4K page within mode-space.

Mode of Operation

Bits 5 and 6 indicate the CPU mode (User/Supervisor/Kernel) associated with the page causing the abort or trap
(Kernel = 00, Supervisor = 01, User = 11). These bits are controlled by the KT11-C, CD logic that decodes current
previous mode bits of the PSW.

Address Space I/D
Bit 4 indicates the type of space (I or D) being accessed (0 =1 Space, 1 = D Space). It is controlled by the

KT11-C, CD logic that selects I/D space.

Page

Number

Bits 3—1 contain the page number of a reference. Pages, like blocks, are numbered from 0 upwards. The page
number and address space bits are used by the error recovery routine to identify the page being accessed if an

abort occurs.

2.3.1.10

Enable KT11-C, CD — Bit 0 is the “Enable KT11-C, CD” bit. When it is set to 1, all addresses are re-

located and protected by the memory management unit. When bit O is set to 0, the memory management unit is
disabled and addresses are neither relocated nor protected. Note that with this bit 0, all programs that run on the

PDP-11/20 will run on the PDP-11/45, 50, or 55.
2.3.2

Status Register 1 (SR1)

SR1 records any autoincrement/autodecrement of the general purpose registers, excluding implicit changes to
the PC. The physical address of SR1 is 777574. SR1 is cleared at the beginning of each instruction fetch and interrupt. When a general register is autoincremented or autodecremented, the register number and the amount

2-15

(in 2’s complement notation) by which the register was modified is written into SR1 (Figure 2-11). The infor-

mation contained in SR1 is necessary to accomplish an effective recovery from an abort. The low order byte is
written first, and it describes the first general register that was changed. If a second general register is changed by
the instruction, that change information is written into the high order byte of SR1. It is not possible for a
PDP-11

instruction to autoincrement/autodecrement more than two general registers per instruction before an

“abort-causing’’ reference. Because only three bits are provided for the general register number, it is up to the

software to determine which set of registers (User/Supervisor/Kernel-General Set 0/General Set 1) was modified
by determining the CPU and Register modes as contained in the Processor Status Word (PSW) at the time of the
abort. SR1 is read-only;a write attempt will not modify its contents.

2.3.3

Status Register 2 (SR2)

SR?2 is loaded with the 16-bit Virtual Address (VA) at the beginning of each instruction fetch, or with the address Trap Vector at the beginning of an interrupt; “T Bit” trap, Parity, Odd Address, and Timeout traps are also
loaded with the trap vector. The physical address of SR2 is 777576. SR2 is read-only; a write attempt will not
modify its contents. SR?2 is the Virtual Address Program Counter (Figure 2-12).

111

——

100

010

OI1

—

Hr"

SR1 EXAMPLE 172423

was incremented by 2.

was decremented by 2.

110

0
ADDRESS:
777574

AMOUNT CHANGED

(2's COMPLEMENT)

NUMBER

AMOUNT CHANGED

(2'S

COMPLEMENT)

NUMBER

11-1039

Figure 2-11

Format of Status Register 1 (SR1)

0
16-BIT VIRTUAL ADDRESS

AGDRESS:

777576

11-1040

Figure 2-12

Format of Status Register 2 (SR2)

Status Register 3 (SR3)

2.3.4

SR3 is a 4-bit register that stores I/D space control information. The physical address of SR3 is 772516. Data
can be written into or read from SR3 under program control. The SR3 format is shown in Figure 2-13. When
the ENABLE D SPACE bit for a specific mode (Kernel, Supervisor, or User) is cleared, only the I space PAR/
PDR set will be used when operating in that mode. If an ENABLE D SPACE bit is set, then the D space PAR/
PDR set for that mode is enabled. Then, if a memory reference is not an instruction fetch, immediate operand,
index word, or an absolute address, the D space PAR/PDR set will be used to relocate that memory reference.
3

0
ADDRESS:
772516¢g

SF’ARE—f

’

KERNEL MODE

"1" ENABLES
D SPACE

SUPER MODE
USER MODE
11-1041

Figure 2-13

2.4

Format of Status Register 3 (SR3)

KT11-C, CD OPERATION

This section contains operational information, including techniques, hints, and cautions.
2.4.1

Console Operations

When the KT11-C, CD option is implemented and enabled in the PDP-11/45, 50, or 55 system, console operations
are effected as described in the following paragraphs.

2.4.1.1 Single Step Mode — To single step through a program, do not use the console START switch. To do so

will disable the KT11-C, CD by clearing SRO. As an alternative, load the PC (R7) with the starting address and
press the CONT switch.

2.4.1.2 Address Display — When the KT11-C, CD is enabled, the console address display is determined by the
Address Display Select switch position, as indicated in Table 2-3.

2.4.1.3 Stepping Over 32K-Word Boundaries — On Examine Next and Deposit Next operations a carry is not
propagated from bit 15 to bit 16.
2.4.2

Physical Address Determination

A 16-bit virtual address can specify up to 32K words in the range from 0 to 1777764 (word boundaries are even
octal numbers). The three most significant virtual address bits designate the PAR/PDR set to be referenced dur-

ing page address relocation. Table 2-4 lists the virtual address ranges that specify each of the PAR/PDR sets.

To calculate the physical address, disregard the three most significant VA bits and add the remaindter to the PAR
contents, left-shifted six places.

2-17

Example:

VA = 167456

xxx0

111

100

=011

100

101

110

PA = 355256 = 011

101

010

+(PAR) = 3456

101

110

101

110

Where x indicates these bits are not used in the calculation.

Table 2-3
Address Display Select Switch
Switch Position

PROG PHY

Interpretation and Use

Program Physical Address:

Physical (relocated) addresses accessed by the

program. This position is used for single stepping through the program be-

ing relocated. It will always display the actual memory address of the loca-

tion being accessed.
CONS PHY

Console Physical Operations:

Used for examines or deposits to a physical

address whether the KT11-C, CD is enabled or not. It will display the ad-

dress loaded from the console switch register.

USER, SUPER, or
KERNEL,IorD

Virtual Address: Used for examines or deposits to the virtual address when
the current physical location may be unknown. These positions always display the address generated by the KB11-A or KB11-D processor.

NOTE

A detailed description of the source of individual address bits

is provided in Paragraph 3.5.1.

Table 24
Relating Virtual Address to PAR/PDR Set

Virtual Address Range

W=
O

000000 — 17776

020000 — 37776

040000 — 57776
060000 — 77776

100000 — 117776

~NON N

120000 — 137776

140000 — 157776
160000 — 177776

2.4.3

PAR/PDR Set

Protection Without Relocation

To obtain a one-to-one mapping of virtual address space to physical address space (no relocation), a value must

be placed in each PAR to be accessed, because the three most significant bits of the virtual address are “stripped”

to select the PAR/PDR set. Therefore, these three bits must be “mirrored” by the contents of each PAR, as indicatedin the chart on the following page.

2-18

PAR

Contents

000000

000200

000400

000600

001000

001200

001400

001600

NOTE
If PAR 7 is to address the I/O page, its contents must be

007600.
2.4.4

Communication Between User/Supervisor/Kernel Address Space

A program in one address space can communicate with a program

in another address space using three basic

methods. The simplest method is to make a part of each program
common
A second method is to use the MTPD, MTPI, MFPD, and MFPI

Chapters 9 and 11 of the PDP-11/04, 05, 10, 35, 40, 45 Processor
“return from interrupt” (RTI) instruction. These methods

2.4.4.1

by overlapping physical address space.

instructions. These instructions are defined in
Handbook. A third method is to use the

are described in the following paragraphs.

Overlapping Physical Addresses — Consider the problem of providing a buffer area to move data to and

from I/O devices through the monitor/file system. Without overlapping, the data would be brought into a buffer
area located in Kernel data space. It would then be moved into a separate buffer area in User
space. However,
using KT11-C, CD memory mapping capabilities, a single buffer area can be located in physical
memory with
provisions for access by User, Supervisor, and Kernel mode programs. This method
space required for separate buffer areas and also the time required to move data

2.4.4.2

saves the additional memory

from one buffer area to another.

MFPI and MTPD Instructions Use — In the following example, a word is popped off the Kernel stack

and pushed onto the User stack. This method of stack-to-stack communication is typical of well-defined operating system communication. Assume that the processor is running in the Kernel mode and the previous mode
was the User mode. The MFP and MTP instructions are double operand instructions and the missing operand is

always the stack of the mode you are in.
Internal Register

Transfers
0065 SS

MFPI

;GET CURRENT VALUE OF USER STACK POINTER.

~(R6) < (R17)

;PUSH IT ONTO KERNEL STACK. NOTE

KER SP

USER SP

;THAT SINCE ALL GENERAL REGISTERS ARE

;IN BOTH I AND D SPACE, THIS INSTRUCTION

;COULD HAVE BEEN “MFPD”,
MOV

(R6) +, R1

;POP USER R6 VALUE OFF KERNEL STACK.

R1 « + (R6)

;PUT IT IN GENERAL REGISTER 1.
1066 DD

MTPD

—(R1)

;POP ARGUMENT OFF KERNEL STACK. PUT

;IT ON TOP OF USER STACK.
.

KER SP
(R17) < —(R1)

USER SP
(R1) < HR6)

;ADDITIONAL WORDS MOVED HERE

MOV

0066 DD

MTPI

R1, —(R6)

KER

;PUT CORRECTED USER STACK POINTER ON

-(R6) < R1

;KERNEL STACK.

KER SP

;POP CORRECTED USER R6 VALUE OFF KERNEL

(R17) < +(R6)

;STACK AND PUT IN USER Ré6. (INSTRUCTION

USER SP

;COULD HAVE BEEN “MTPD”.)

2-19

KER SP

The use of MTPI and MFPI is restricted in the User mode. If the previous mode bits (13:12) of the PS word also
specify User mode (11), then the following restriction is implemented to preserve the integrity of execute-only
protection. The execution of a MFPI will be relocated by the equivalent D space PAR/PDR register set if “D”
space for the User mode is enabled (SR3, bit 0 = 1). This prevents a user from using MFPI to read from an
execute-only page in his address space.

2.4.4.3 Control Information — Control is passed inward from User and Supervisor modes to the Kernel mode
by all traps and interrupts. All trap and interrupt vectors are located in Kernel virtual address space. Thus, all
traps and interrupts pass through Kernel space to obtain their new PC and PS, and determine the new mode of
processing. Control is passed outward from the Kernel mode to the User and Supervisor modes by the RTT and
RTI instructions, which restore the old PC and PS by popping them from the stack.
2.4.5

Statistical Aids Use

Three ACF keys (1, 4, and 5) can cause traps at the end of the current instruction when the Enable Memory Management Traps bit is set in the SRO. These keys also cause the A bit in the associated PDR to be set, regardless of
whether the Enable Memory Management Trap bit is set. A PDP-11 double operand instruction can access up to
six different pages of memory during execution. If each of the six PDRs had ACF keys that specified memory
management traps, then the A bit in each of the PDRs will have been set by the time the instruction is com-

pleted and the memory management trap service routine is entered. A statistic gathering service routine that col-

lects “frequency of use” data can scan all PDRs and thus gather A bit information from all six PDRs that might
have been set. The status registers are set only once. Therefore, if the statistical facility is to collect valid frequency of use on pages, a more elaborate approach is required of the software service routine.

One approach is to leave the Enable Memory Management Trap bit reset to 0, so that no traps occur, but set the
ACF keys to specify the appropriate traps. This will cause the A bit to be set. Then, use a real-time clock to in-

terrogate the A bits. When one is found set, a count location corresponding to that page can be incremented,
and then that A bit must be cleared in the PDR. .

One way to clear the A bit is to write into the PDR. For example, the instruction:

MOV

@#PDR,

@#PDR

will clear the A and W bits, but leave all other PDR bits unchanged. A less complex way is to set all read-only
page ACF keys equal to 1 and all read/write page ACF keys equal to 4. At the end of the user time period, interrogate the A and W bits. Most state transitions with the ACF can be accomplished by incrementing the PDR.
The ACF keys change as follows:

S
T S

Effect of ACF Key Change

New

ACF Key
AN ON N

Original

ACF Key

No memory management trap on read.
No memory management trap on read.
No memory management trap on write.
No memory management trap on a read or write.

Thus, by incrementing the ACF key, characteristics of the original key that are no longer required are deleted by
the new key. Other essentials are retained by the new key. For example, when the ACF key increments from
1 to 2, the KT11-C, CD still aborts any attempt to write into that page.

2-20

Iand D Space Use

2.4.6

NOTE

To use separate I and D space, a programmer must be able to
write pure procedure code. The use of I and D space is an ad-

vanced technique that should not be attempted by novice programmers,

Eight I space PAR/PDR pairs accommodate up to 32K instruction words and eight D space PAR/PDR pairs accommodate up to 32K data words. By using the separate I and D space PAR/PDR pairs, a maximum 64K-word
program capacity is possible. The following rules apply to any separate I and D space programs.

Ispace can contain only instructions, immediate operands (Mode 2, Register 7), absolute addresses
(Mode 3, Register 7), and index words (Modes 6 and 7).

The stack page must be mapped into both I and D space if the Mark instruction is used (standard PDP11/45, 50, and 55 subroutine calling sequence), because it is executed off the stack.

Ispace only pages cannot contain subroutine parameters, which are data. Therefore, any page that
contains standard PDP-11/20 calling sequences for example cannot be mapped into an I space page.

The trap catcher technique of putting .+2 in the TV followed by a halt must be mapped into both I
space and D space.

The following chart shows the separation of I and D references for all address modes and all registers. Note that
all registers (RO—R7) are in both spaces.

Name

Mode

000

[ INSTRUCTION

I space

001

[ INSTRUCTION

I space

{ DATA

D space

[INSTRUCTION

__ ]

[Ispace

{ DATA

]

D space

010

011

0—6

Autoincrement

Immediate

0-6

Autoincrement Deferred

Absolute

INSTRUCTION

I space

IMMEDIATE DATA

I space

[ INDIRECT

D space

[ DATA

D space

[ INSTRUCTION

INSTRUCTION

I space

ABSOLUTE ADDRESS

I space

D space

[ INSTRUCTION

Ispace

L DATA

D space

{ DATA

100

0-6
7

Autodecrement

DO NOT USE THIS CONSTRUCTION
(continued on next page)

2-21

Mode

Name

101

0-6

Autodecrement Deferred

{ INSTRUCTION

{ INDIRECT

[ DATA
7
110

I space

D space

DO NOT USE THIS CONSTRUCTION

111

Index

INSTRUCTION

Index Deferred

I space

INDEX

I space

DATA

D space

INSTRUCTION

I space

INDEX

I space

| INDIRECT

| DATA

]

D space

]

D space

Note that when D space is not enabled for a mode by setting the proper bit in SR3, all memory references are re-

located and protected by the I space set of PAR/PDR registers.

2.4.7

1/O Operations

2.4.7.1

Kernel Mode Protection — All I/O operations should be performed by programs running in Kernel

space, forcing User and Supervisor programs to call upon a Kernel mode routine to perform their I/O operations.
This precaution increases system reliability by preventing possible errors by User and Supervisor programs. This
precaution is necessary because the physical addresses issued by NPR devices on the Unibus are not relocated by

the KT11-C, CD. Therefore, proper I/O transfers between NPR devices and relocated memory depends upon
careful checking of I/O requests by the Kernel mode routines; proper 1/O transfers provide relocated memory
addresses and ensure that the referenced pages of memory are resident and authorized.

2.4.7.2

Avoiding I/O Lockout — If the Kernel mode is used to handle all I/O operations, the programmer must

ensure that the Kernel space to which the I/O routines are assigned never becomes non-resident. If this occurs,
it becomes impossible to access the PAR/PDR sets to re-establish residency and to turn the KT11-C, CD off by
accessing bit 0 of SRO.

One method of recovering from such a situation is to execute a RESET instruction, which will disable the
KTI11-C, CD relocation logic and allow direct I/O access again.

2.4.8

Processor Status Word

In addition to the material below consult Paragraph 4.5 in the KB11-A, D Central Processor Maintenance Manual.

2.4.8.1
a.

Explicit References to PS
If the following three instructions cause a page fault on the “write” into the destination address, the
PS condition codes may be modified.
MOV PS, (dst modes 3,4, 5,6, 7)

MFPI PS

MFPD PS
This may cause a different PS to be stored when the instruction is restarted.
(continued on next page)

2-22

The sequence

SPL
WAIT
should be used with care. Note that the processing of a KT11-C, CD abort (page fault) may occur on
the fetch of the WAIT instruction. Hence, priority levels must be carefully controlled or the interrupt

that was expected to transfer control from the WAIT instruction may occur before the execution of
the WAIT instruction.
2.4.8.2

Implicit Modification of the PS — When a KT11-C, CD abort occurs, the PS condition code may have

already been modified by the partially completed instruction. However, in all cases except those described in
Paragraph 2.4.8.1, restarting the aborted instruction still causes the condition codes to be set to the expected value.

2.4.9

Non-Recoverable Aborts

Instructions that have autoincremented (popped) the Kernel stack pointer cannot be properly restarted, if they
cause an abort. When an instruction that pops something off the Kernel stack causes an abort, it cannot be re-

started because the abort mechanism pushes two items (old PS and PC) onto the Kernel stack. The first of these
pushes wipes out the item that the abort-causing instruction previously tried to pop off the stack.

NOTE
The MTPI and MTPD instructions in particular are nonrecoverable if done in Kernel mode to an illegal user area.

2.4.10

Page Fault Recovery

This paragraph presents an approach to recovering from either non-resident page faults or demands for a larger
page. The description comprises a flow chart and sample program code with notation and includes only material

that directly relates to using the KT11-C, CD status registers properly. Emphasis is placed on proper procedure
for restarting once the new page is defined and authorized.
The recovery routine takes one of two paths. The flow chart (Figure 2-14) shows that the correct path is determined by the Instruction Complete (IC) bit in status register SRO. If the IC bit is 1, then the “emulate aborted
interrupt” path is taken. If the IC bit is O, then the “general register backup/instruction restart” path is taken.

Remember that the IC bit indicates if the aborted memory access was part of an instruction (IC = 0) or part of
an interrupt or trap (IC = 1), as described in Paragraph 2.3.1.8.

2.4.10.1

Definitions — Table 2-5 lists the definitions of mnemonics used in Figure 2-14.

2-23

® SdI NO

32IAY3S

afisod1®
|

S3A

M3N 39vd

M3N) (Sd

NOAJvlSA3NY3IN

3137dW0D

I3NE3N g3HSNd

2-24

ul ou |oux

S¥-0Y d0d 8 Jdd 3AOW
2WO4uSd

sy by

Table 2-5

Mnemonic Definitions

Mnemonic

Definition

APC

Abort Program Counter. The value of the contents of location 250. This value normally is the starting address of the KT11-C, CD Abort/Trap Service Routine. Location
250 is the address of the KT11-C, CD Trap Vector.

APS

Abort Processor Status. The value of the contents of location 252. This value is normally the processor status during the KT11-C, CD Abort/Trap Service Routine.

IPC

Interrupt Program Counter. The value contained in the interrupt trap vector location;
the starting address of the interrupt service routine.

IPS

Interrupt Processor Status. The value contained in the interrupt trap vector location
plus two; the processor status to be set upon servicing the interrupt.

IR6

Interrupt Register 6. Value of the stack pointer for the interrupt service routine;either
the Kernel, Supervisor, or User R6 and is specified by bits (15:14) of the IPS.

KR6

Kernel Register 6. The value of the stack pointer when the processor is in Kernel mode.

PPC

Program Program Counter. The value placed on the Kernel stack when the KT11-C, CD
causes an abort. If the abort was caused by an interrupt, then the PPC is the location
of the next instruction to be executed when control is returned to the program that
was interrupted. If the abort was caused by an instruction reference, then the PPC is

equal to two more than the value of the last I space reference. In the latter case, the
PPC will not be used for any computation.

PPS

Program Processor Status. Value equal to the contents of the PS at the time of
KT11-C, CD abort that is placed on the Kernel stack.

PR6

2.4.10.2

Program Register 6. Value of the stack pointer for the “program”. Note that PR6 may
be KR6 if the program was in Kernel mode. If the program was in Supervisor mode,
PR6 is the Supervisor R6; if the program was in User mode, PR6 is the User R6.

Program Example

;NOTE THAT REGISTER SET 1 IS ASSUMED TO BE IN USE FOR BOTH THE USER AND KERNEL
:MODES.

START:

MFPD

Ré6

;PUSH PR6 ONTO KERNEL STACK

MOV

RS, -(R6)

;PUSH R5—R0 ONTO KERNEL STACK

MOV

R4, -(R6)

MOV

R3,-(R6)

MOV

R2,-(R6)

MOV

R1,-(R6)

MOV

RO, - (R6)

BIT

#140000, @ #177572

;TEST FOR NON-RESIDENT OR PAGE
;LENGTH ABORT

BEQ

JMP

ERROR

;WAS SOMETHING OTHER THAN NON-RESIDENT
;OR PAGE LENGTH ABORT.
(continued on next page)

2-25

;“ERROR” ROUTINE IS NOT DESCRIBED IN THIS EXAMPLE. INSERT CODE HERE TO FIND A FREE
;MEMORY BLOCK AND PULL THE PAGE INTO MEMORY FROM DISK OR DRUM SYSTEM. ASSUME

;THE SUBROUTINE LEAVES THE PAR IN R1, THE PAR ADDRESS IN R2, THE PDR IN R3, AND THE
;PDR ADDRESS IN R4.

MOV

R1, @R2

;SET UP PAR OF NEW PAGE

MOV

R3, @R4

SET UP PDR OF NEW PAGE

;THIS CODE TESTS FOR WHETHER THE ABORT WAS CAUSED BY AN INSTRUCTION ACCESS OR BY

;AN INTERRUPT ACCESS.
TSTB

@#177572

;TEST INSTR. COMP. BIT OF SRO.

BPL

NORM

;IF NOT SET, GO TO NORMAL RECOVERY
;ROUTINE.

;THE FOLLOWING CODE OBTAINS LOCATION OF INTERRUPT TRAP VECTOR

MOV

@#177576, R3

;MOVE KT11-C, CD SR2 (THE TRAP VECTOR ADDRESS)
;TO R3

MOV

2(R3), R4

BIT

#140000, R4

;TEST BITS 15:14 OF IPS FOR 0 (=KERNEL MODE)

BEQ

KERNEL

;JF KERNEL MODE, GO TO KERNEL ROUTINE.

sMOVE CONTENTS OF TV + 2 (THE TV PS) TO R4

;THE FOLLOWING ROUTINE OBTAINS THE STACK POINTER (IR6) OF THE SPACE THAT THE IPS IN
;THE TV CALLED FOR. IF KT11-C,CD SR1 HAS LOGGED CHANGES TO THIS R6, THEN IT WILL BE

;CORRECTED. THE ROUTINE THEN PUTS THE PROGRAM PC AND PS (PPC AND PPS) CURRENTLY ON
;THE KERNEL STACK ONTO THE STACK THAT IS CALLED FOR BY THE IPS; THUS PERFORMING THE
;FIRST PART OF “EMULATING” THE INTERRUPT.
MOV

@#177776, RO

;PSW TO RO

MOV

RO, R2

;COPY PSW TO R2

BIC

#030000, R2

;CLEAR OUT PREVIOUS MODE BITS IN COPY OF

ASH

-2,R4

;SHIFT THE NEW TV PS 2 PLACES RIGHT, PUTTING

;THE PSW.
;THE TV PS CURRENT MODE BITS IN THE
;PREVIOUS MODE POSITIONS.

BIC

#147777, R4

:MASK OUT ALL BUT PREVIOUS MODE BITS IN

BIS

R4, R2

;A NEW PS CREATED WITH CORRECT PREVIOUS

MOV

R2,@#177776

MFPD

Ré6

:GET PROPER Ré6

MOV

(R6)+, R2

:POP R6 OFF KERNEL STACK, PUT IT IN R2

;SHIFTED COPY OF IPS.

:MODE IS NOW IN R2.

:CHANGE PS SO WE CAN GET TO R6

:SPECIFIED BY IPS.

;THE FOLLOWING CODE CORRECTS THE PROPER R6, IF NECESSARY, TO ACCOUNT FOR THE
;PUSHES OF THE PPC AND PPS ON THE STACK SPECIFIED BY THE IPS CURRENT MODE.

TST

@#177574

;CHECK SR1 FOR AUTODECREMENT OF R6 IF IR6

BNE

ISOK

sWAS ALREADY CHANGED. (ONLY POSSIBILITY

;IS BY 4 BYTES.) IF SO, IT DOES NOT HAVE TO BE
;CORRECTED.

SUB

#4,R2

;DO THE AUTODECREMENT TO COPY OF IR6 in R2

MOV

RO, R1

;COPY APS INTO R1 SO THAT WE CAN DETERMINE

BIC

#147777, R1

;LEAVE PMODE BITS OF APS (SPECIFYING MODE

XOR

R1,R4

;sWHETHER PR6 IS IDENTICAL TO R6.

;OF PREVIOUS PROGRAM) IN R1.
;TV MODE BITS IN R4

2-26

(continued on next page)

SAME:

BEQ

SAME

;GO TO “SAME” IF PR6 = IR6.

MOV

R2,-(R6)

;PUSH COPY ONTO KERNEL STACK

MTPD

;PUT CORRECTED IR6 BACK IN REGISTER.

ISOK

;DONE WITH THIS PHASE

SUB

#4, 14 (R6)

;THE PR6 ON THE KERNEL STACK IS THE ONE TO

;BE CORRECTED.
;THIS CODE PUSHES THE PPC AND PPS, NOW ON THE KERNEL STACK, ONTO THE STACK SPECIFIED
;BY THE IPS (IR6)

ISOK:

MOV

16 (R6),-(R6)

;PUSH PPC ONTO TOP OF KERNEL STACK

MOV

22 (R6),-(R6)

;PUSH PPS ONTO TOP OF KERNEL STACK

MTPD

(R2)

;PPS OFF KERNEL STACK
;AND PUSHED ON I STACK.

MTPD

-(R2)

;PDC OFF KERNEL STACK
;AND PUSHED ON I STACK.

MOV

RO, #177776

;RESTORE APS. GET CORRECT PMODE BITS BACK

;THE FOLLOWING CODE PUTS THE IPC AND IPS INTO THE KERNEL STACK IN THE LOCATIONS
;PREVIOUSLY OCCUPIED BY PPC AND PPS. NOTE THE PMODE BITS IN THE TV PS MUST BE PROPERLY

SET FROM THE CMODE BITS OF THE PPS STILL ON THE KERNEL STACK.

MOV

20 (R6), RO

ASH

-2, R0

;PUT COPY OF PPS INTO RO
;RIGHT SHIFT PPS COPY PLACING CMODE BITS
;INTO PMODE POSITION.

BIC

#147777, RO

MOV

2 (R3), 20 (R6)

;LEAVE ONLY PMODE BITS IN RO

;PUT COPY OF IPS INTO KERNEL STACK WHERE
;PPS USED TO BE.

BIC

#30000, 20 (R6)

BIS

RO, 20 (R6)

;CLEAR OUT PMODE BITS OF IPS.
;SET IPS PMODE WITH VALUE FROM CMODE OF
;PPS.

MOV

(R3), 20 (R6)

;PC IN TRAP VECTOR REPLACES PC ON KERNEL
STACK.

;THE FOLLOWING CODE RESTORES THE GENERAL REGISTERS

RESTUR:

MOV

(R6)+, RO

;RESTORE RO—-R5 FROM THE KERNEL

MOV

(R6) +, R1

STACK

MOV

(R6) +, R2

MOV

(R6) +,R3

MOV

(R6) +, R4

MOV

(R6) +, R5

MTPI

;RESTORE R6 TO USER R6

;RESET STATUS REGISTER SRO, RETURN
RETURN:

MOV

#000001, @#177572

RTI

;CLEAR SRO, SET KT11-C, CD ON.

;RETURN

;JF IT WAS KERNEL, ONLY NON-FATAL ERROR COULD BE TV NON-RESIDENT. THEREFORE, R6
;COULD NOT HAVE BEEN CHANGED BY THE INTERRUPT. THE FOLLOWING CODE POPS RO—R6 OFF
;KERNEL STACK AND PUTS IPC AND IPS ON STACK.

KERNEL:

MOV

(R6) +, RO

MOV

(R6) +, R1

MOV

(R6) +, R2

MOV

(R6) +, R3

MOV

(R6) +, R4

MOV

(R6) +, R5

;POP RO-R6

(continued on next page)

2-27

MOV

@#177576, (R6)

;ITV WRITTEN OVER OLD KR6.

MOV

@(R6), - (R6)

;PUSH COPY OF CONTENTS OF ITV ON STACK

ADD

#2,2 (R6)

;ITV + 2

MOV

@2 (R6), 2 (R6)

;REPLACE ITV + 2 WITH IPS

;(PC).

;THE FOLLOWING CODE TESTS FOR AN AUTODECREMENT OR AUTOINCREMENT OF KERNEL R6.
;IF ONE IS DETECTED, CONTROL PASSES TO WAS6 WHICH CANNOT RESTART THE INSTRUCTION.
NORM:

MOV

@#177776, R3

GET PS TO R3

BIT

#030000, R3

TEST FOR PREVIOUS KERNEL MODE

BNE

CORECT

WAS NOT KERNEL

MOV

@#177574, R4

:PUT SR1 IN R4

BIC

#174370, R4

.LEAVE REG #S IN R4

CMPB

#6, R4

TST FOR KR6, LOW BYTE

BEQ

WAS6

SWAB

CMPB

#6, R4

BEQ

WAS6

:TST FOR KR6, HIGH BYTE

;THE FOLLOWING CODE CORRECTS REGISTERS AUTOINCREMENTED OR AUTODECREMENTED
;DURING INSTRUCTION THAT CAUSED ABORT. THIS CODE IS NOT USED WHEN AN INTERRUPT

;CAUSED THE ABORT.

CORECT:

LOOP1:

MOV

#177574, R2

MOV

#2,R3

;ADDRESS OF SR1

MOVB

(R2)+, RO

;PUT CONTENTS OF SR1 IN RO, STEP ADDRESS

BEQ

DONE

;NO REGISTER CHANGED

MOV

RO, R1

;COPY SR1 INTO R1

BIC

#177770, R1

;MASK ALL BUT REGISTER #

ASL

sMULTIPLY REGISTER # TO GET CORRECT INDEX

;INTO STACK WHERE REGISTER IS TEMPORARILY
;STORED.

ASH

-3,R0O

;RIGHT JUSTIFY CORRECTION CONSTANT

ADD

R6, R1

;CREATE POINTER TO REG ON STACK

ADD

RO, (R1)

SOB

R3, LOOP1

;BRANCH FOR SECOND CORRECTION

;CODE TO RESTORE PROGRAM COUNTER

DONE:

2.4.11

MOV

@#177576, 16 (R6)

RESTUR

Fatal System Errors

The PDP-11/45, 50, and 55 hardware designs employ many safeguards that facilitate their use in reliable real-time
and timeshared operating systems. These safeguards either prevent careless programmers from causing fatal system

errors or allow the operating system to recover from the program fault. However, certain restrictions apply to
system error, or ‘“‘exception’ handling. All facilities for handling interrupts with priority greater than processor
priority 7 must be resident, meaning that for each of the fault types below the trap vectors, the appropriate stack

and the service routine must all be resident. Otherwise, a fatal system error loop may occur that can only be
intercepted from the console.

2-28

Service Routine

Trap Vector

Old Address

Fatal Stack Violation (Red)
KT11-C, CD Abort

4
250

Non-existent Memory Timeout

Parity Error

Warning Stack Violation (Yellow)
Power Fail

4
24

FP11 Exception Trap

224

This restriction is necessary because: if, during the initial processing of a KT11-C, CD abort any of these inter-

rupts causes a second KT11-C, CD abort, recovery will not be possible because the KT11-C, CD can log status
information in SRO, SR1, and SR2 for a single abort only. Until the information in SR0O, SR1, and SR2 has been
captured to handle the first abort, a second KT11-C, CD abort must not occur.

2-29

CHAPTER 3
LOGIC DESCRIPTION

This chapter describes the KT11-C, CD logic in sufficient detail that maintenance personnel can quickly determine

the function and purpose of the logic circuits shown on the block schematics in the engineering drawings. Because the block schematics are drawn to show one or two functional sections of logic per sheet, the major para-

graphs in this chapter follow the sequence of block schematic organization.

3.1

PDP-11/45,11/50, AND 11/55 SYSTEM INTERFACE

In the PDP-11/45,11/50, or 11/55 system, the KT11-C, CD Memory Management Unit is located between the
KB11-A, D Central Processor Unit and the Fastbus, and Unibus A address lines (Figure 3-1).

TO ALL
UNIBUS A DEVICES

UNIBUS A

16-BIT

>
See Note

VIRTUAL ADDRESS

BAMX<15:00>H

FP11-B,C

POINT

FLOATING

PROCE SSOR

K811-AD

PROCESSOR

BR <15:00>8 L

READ DATA

CENTRAL

UNIT

UNIBUS

WRITE DATA

BUS INTD<15:00>L

CORE

MAGNETIC

MEMORIES

ADDRES
S

843 fost

KT1-CCD

MANAGEMENT

124K

} ADDRESS

mQPMSUM

18- BIT PHYSICAL

unIT

FASTBUS
ADDRESS
AT
O H

CONTROL AND TIMING

BAMX
< 05:00>H

See

Note

FASTBUS

MS11

SEMICONDUCTOR
MEMORY SYSTEM
(MOS AND/OR
B-POLAR)

NOTE:
The KT11-C,CD provides only address outputs to unibus A and the fastbus. Data and bus
control signals do not pass through the KT11-C,CD.
11-3955

Figure 3-1

KTI11-C, CD System Hardware Interface

The processor provides a 16-bit virtual memory address to the memory management unit on the BAMX (15:00) H

lines. These lines permit addressing a maximum of 32K word locations, The memory management unit adds the
13 least significant virtual address bits with 12 high order address bits obtained from internal page address registers to provide an 18-bit physical address that allows addressing up to 124K word locations in memory plus 4K

locations in the I/O page. The method of physical address construction is described in Paragraph 2.1.1.

3-1

The 18-bit physical address is provided in two versions. The Unibus A address lines are BUS A (17:00) L. These
outputs are used to address memories and devices connected to Unibus A. In addition, the 18-bit memory ad-

dress formed by linking physical address bits PA (17:06) H and virtual address bits BAMX ¢05:00) H is output to
the Fastbus; the high-speed MS11 Semiconductor Memory System is connected to the Fastbus.

Specific addresses are assigned to the internal Page Address and Page Descriptor Registers (PAR and PDR) so that

page description and address data can be written into these registers under program control. The data inputs
from the processor are BR (15:00) B L. These also provide the data inputs to some of the internal status registers.

The contents of the PAR/PDR registers and the internal status registers can be read onto the processor internal
data bus lines BUS INTD (15:00) L under program control.
3.2

KTI11-C, CD ORGANIZATION

Figure 3-2 is an overall block diagram of the KT11-C, CD Memory Management Unit. The drawing reference

within each block indicates the block schematic sheet that shows the associated logic. Only the major signal
inputs and outputs are indicated on the overall block diagram. Complete circuit details are shown on the referenced block schematics.

3.2.1

System Address Path (SAP)

The upper half of the block diagram shows the flow of physical address generation, beginning with the BAMX

(15:00) H inputs from the processor. This input is equivalent to the virtual memory address. The relocation logic
links the virtual address with the contents of the page address field in the PAR to provide the physical address.
Two versions of the physical address are available at the output. A Fastbus memory address that consists of PA

(17:06> H and BAMX<05:00) H is provided for high-speed MOS and bipolar memories. The Unibus A memory
address BUSA A (17:00) L, provided for memory and devices, is derived from PA (17:00) H and BAMX (05:00) H.
As indicated on the block diagram, most of the address path logic elements are located on the SAP module M8107.

3.2.2

Status and Control Logic

The lower half of the block diagram shows the status registers, timing logic, and control logic. Where possible,
control and timing signals and data paths between the memory management unit and other major components

of the PDP-11/45, 50, and 55 systems are indicated on the block diagram. Most of the status register and control
logic elements are located on the System Status Registers (SSR) module (M8108 in the KT11-C and M8108-YAin the KT11-CD).
3.3

PAR/PDR REGISTERS

The PDP-11/45, 50, and 55 Memory Management Units use three PAR/PDR sets. A set is provided for each
mode: Kernel, Supervisor, and User. Each set consists of 32 16-bit registers, subdivided into two groups of 16.
One group of 16 is used for references to Instruction (I) space and another group of 16 is used for references to
Data (D) space. Each group is further divided into a set of eight Page Address Registers (PAR) and eight Page
Descriptor Registers (PDR). Thus, there are 48 PAR/PDR register pairs or a total of 96 registers.
In hardware, each PAR is 12 bits wide and each PDR is 16 bits wide. A PAR and PDR are always used as a pair
to provide a complete register pair that contains all the information required to describe and locate a current

active memory page. The PAR/PDR organization is shown in Figure 3-3.

3-2

[rus o

ENYSEIN ) 148H<0:GI>SLIE INI934W
¥3LSI93Y 39vd HiON3T 3nvd'j ¥dV18

Le-21

4 | SHIAING

ABHYO <90:L) F10SN0D A.FdVS90:L1>VdH<

208ld3Wi+WH a/1 o )

9Yad0:1>48 ——— .$S380aV

40WL139340H)245H<0:GI>S.l8 ses-n

"2@9'82N'8IdHVa3H1<408H:61>XNVE A”L/s3uay
HX<0W:V50E>Y

M1S[|sA302Hi9487aHN<0:2v>735 mwZ8Tu30m82¥S|Yu3L¥N1wASOL3sUIH5VOW¥LSfv1VI9OoN/LWVI3lON8CSIYDO4Nvs ]S|usH§INd

vHGoLIvoIyL

(W¥31vs)dn

3-3

w4‘_ad-—v——a—— (O72y‘Au-e1oIydTr-wnO1guDaIeidgW€p1lgIiuL(neWgYJy

RvsLnvea
P

Selected by
SSRB KERNEL SPACE,
SSRB SUPER SPACE and
SSRB USER SPACE logic

SAPE

KERNEL

000

PAR

SUPERVISOR
PDR

PAR

USER
PDR

PAR

KERNEL PAR L

SAPE

KERNEL CS L

SAPE

SUPER PARL

SAPE

SUPER CS

SAPE

USER PAR L

SAPE

USER CS L

PDR

001

010
I SPACE

100
104
110
111

000

]

PAR

POR

PAR

PDR

PAR

SAPK ADDR 3K

SAPK

ADDR 3S

SAPK

ADDR

PDR
| or D SPACE selected

001

by MMR3(2:0) and

010

by SSRB | SPACE A

D SPACE @—

o111

and SSRB | SPACE B.

When SAPK ADDR 3 K,

100

3 Sand 3 U are high,

101

when they are low, D

| space is selected;
space is selected.

110

]

Addressing

of PAR/PDR

SAPK ADDRg L
SAPK

ADDR1Y

SAPK

ADDR2 L

One of eight registers
selected by VA (15:13),

PAGE ADDRESS FIELD

7 ///////// /

(PAF)

Page Address Register (PAR) Format

PAGE LENGTH FIELD

(PLF)

Page Descriptor

Figure 3-3

Alw

)

ACF

PAR/PDR Addressing and Format

11-3954

3.3.1

Page Address Registers (PAR)

Refer to drawings SAPA, SAPB, and SAPC. A PAR contains a 12-bit Page Address Field (PAF)

that specifies

the starting address of the page as a block number in physical memory. A set of 16 registers is provided for each
mode:

Kernel, Supervisor, and User. The 12-bit output of each set is ORed to the PAF (17:06) H lines. How-

ever, only one PAR set is enabled at any given time, depending upon which Chip Select input is asserted. Dis-

abled PAR sets have their outputs “high”. Each PAR set is made up of three 3101A 16 X 4 bit memory chips,

configured to provide 16 12-bit addressable registers. The Kernel PAR (KPAR) is shown on drawing SAPA, the
Supervisor PAR (SPAR) is shown on drawing SAPB, and the User PAR (UPAR) is shown on drawing SAPC.

3.3.1.1

Selection — Only one PAR set is selected at a time. Selection is accomplished by asserting the Chip

Select (CS) inputs. A PAR set is selected in either of two ways: by addressing one of the registers within the set
or by operating in the mode associated with the set. Internal register decode logic shown on drawing SSRL pro-

vides the appropriate output if a register is addressed. The PAR addresses for Kernel, Supervisor, and User modes
are charted on drawing SSRL. The Kernel/Supervisor/User address space control logic shown on drawing SSRB
provides the appropriate Chip Select output in each operating mode. The SSRB KERNEL SPACE (1) L, SSRB

SUPER SPACE (1) L, or SSRB USER SPACE (1) L output will be asserted depending upon the current or previous processor status, the current KB11 microstate, and other processor operating conditions described in Para-

graphs 3.10.4 through 3.10.6.
3.3.1.2

Addressing — There are two ways to address one of the 16 registers within a selected PAR set.

Virtual Memory Addressing: The three most significant bits of the virtual address BAMX (15:13), plus a
bit that tells whether the reference is I space or D space, are used to generate the address of a specific
register.

Internal Register Addressing: When data is to be written into, or read from, a specific register of the
selected PAR set, the five low order bits of the internal register address are used to generate address

bits ADDR (3:0) and a “byte”” select bit.
The most significant address bit, SAPA APR ADDR3K H, is used to specify the group of eight D space registers
or the group of eight I space registers of the selected set. The source of address bits is summarized in Table 3-1.

Table 3-1
Address Bit Source
PAR Address Source
Access

ADDR3

ADDR?2

ADDRI1

ADDRO

BAMX04

BAMXO03

BAMXO02

BAMXO01

I SPACE

BAMX15

BAMX14

BAMX13

D SPACE

BAXMI15

BAMX14

BAMX13

Internal register
Not internal register

The ADDR3 sources for each PAR set, Kernel, Supervisor, and User, are selected by a 74S158 shown on drawing

SAPA. The I SPACE bit is generated by the address space control logic shown on drawing SSRB and described

in Paragraph 3.1/0.7. The ENBL D inputs for Kernel, Supervisor, and User APR addresses are derived from Status
Register 3 outputs. SR3 is shown on drawing SAPN and described in Paragraph 3.9. The specific address is decoded from the BAMX inputs by a 74S158 Line Selector shown on drawing SAPA. When the address is not that
of an internal register, SSRL INT REG FAST L remains high and DAPD BAMX (15:13) H are selected. If an internal register address is decoded, SSRL INT REG FAST L is asserted and DAPB BAMX ¢03:01) H are selected.

3-5

3.3.1.3

Writing Into a PAR — With the Chip Select and address inputs asserted as described, data from the pro-

cessor bus register, PDRB BR (11:00) B L, will be written into the addressed PAR when the Write (W) input goes
low (Paragraph 3.15.3). The following conditions are required:
a.

TMCE C1 H — Asserted for all DATO or DATOB bus transactions.

TMCE BEND H — Must be low. If asserted by bus, parity, or stack errors, or certain processor ROM
states, the bus cycle will end.

UBCCHIBYTE H and UBCC LO BYTE H — Asserted for all DATO bus transactions and for DATOB
transactions coincident with byte address bit BAMX 00.

SSRL KERNEL PAR (1) H — Asserted by any Kernel PAR address. If the address is that of a Supervisor or User PAR, the appropriate SSRL SUPER PAR (1) H or SSRL USER PAR (1) H level will be
asserted (drawings SAPB and SAPC).

When the above conditions are valid, data on PDRB BR (11:00) B L is written into the selected PAR when timing pulse SAPC PULSE BC9 H goes high. This occurs at time T4 of the Pause or Long Pause Cycle.

3.3.1.4

Reading From a PAR — The contents of a specific PAR are available on the SAPA + B + C PAF 17:06) H

output lines when that address is asserted and the appropriate Chip Select inputs go low. The KPAR, SPAR, and
UPAR outputs are ORed to the same lines but only one set is enabled to provide the PAF (17:06) H page address.
PAF (17:06) H can be selected as APR BIT (11:00) H inputs to the internal bus data lines (Paragraphs 3.7 and
3.14).

3.3.2

Page Descriptor Registers (PDR)

Refer to drawings SAPD, SAPE, and SAPF. A PDR is the second word of the 32-bit PAR/PDR set that describes
each active page. A set of 16 registers is provided as the PDR for each mode: Kernel, Supervisor, and User.
Each PDR contains the 7-bit Page Length Field (PLF), two bits of access information (A and W), an Expansion
Direction bit (ED), and a 3-bit Access Control Field (ACF). The significance of each PDR field and bit is described in Paragraph 2.2.2. The 16-bit output of each PDR set is collector-ORed to the same set of output lines;

however, only one PDR set is enabled at any given time, depending upon the asserted Chip Select input.
Each PDR set comprises four

3101A 16 X 4 bit memory chips, configured to provide 16 16-bit addressable reg-

isters. The Kernel PDR (KPDR) is shown on drawing SAPD, the Supervisor PDR (SPDR) is shown on drawing

SAPE, and the User PDR (UPDR) is shown on drawing SAPF.

3.3.2.1

Selection — There are three ways to select a PDR set:

When the address of any PDR within that set is decoded.

When the address of an associated PAR within that set is decoded.

When the address space control logic shown on drawing SSRB asserts the appropriate space control
signal. The SSRB KERNEL SPACE (1) L, SSRB SUPER SPACE (1) L, or SSRB USER SPACE (1) L
' output will be asserted depending upon the current microstate and other processor operating conditions described in Paragraphs 3.10.4 through 3.10.6.

3.3.2.2

Addressing — The APR addressing logic that asserts SAPA ADDR (3:0) H to select one of 16 registers

within a selected PDR set is described in Paragraph 3.3.1.2

3.3.2.3 Writing Into a PDR — The PLF, ED, and ACF fields are written into each register of a PDR under program control in the same way a base address is written into each PAR. The timing and control conditions used
to assert the W inputs to three of the 3101A chips are the same as those described in Paragraph 3.3.1.2. When

these SAPA WR OK conditions are satisfied and the appropriate PDR is selected, data from the bus register will
be written into the PLF, ED, and ACF fields on PDRB BR (15:08) B L and PDRB BR<(03:00) B L.

3.3.2.4 Setting A or W Bits — Refer to drawing SAPD. Separate logic provides the W input to the 3101A that
stores the A and W bits of each PDR set. SAPD WR A + W L is asserted during physical address generation if no
internal register address is decoded, or if the decoded internal register is any PAR/PDR address and SAPA WR
OK H conditions are satisfied.

The A bit is set if a memory management trap occurs during the access of the associated memory segment. The
A bit is stored in the ATTN flip-flop. The W bit is set if a write cycle occurs during the access of the associated
memory page. The W bit is stored in the WRTN INTO flip-flop. Once the A or W bit has been set, all subsequent
access of that page causes the bits to be read out of the 3101A and clocked into the ATTN and WRTN INTO

flip-flops at TS of the Bust cycle. Then, at T4 of the Pause cycle, the contents of the ATTN and WRTN INTO
flip-flops are written back into the

3101A. Note that any new information caused by the current memory access

is ORed into the A and W bits at this time. The bits cannot be set if an abort occurs during the access or if an internal register is accessed.

3.3.2.5 Clearing A or W Bits — Whenever the physical address of the current memory reference is an internal
register, SAPD ATTN DATA and SAPD WRTN DATA are not asserted. Thus, the A and W bits of a PDR are
cleared by writing into either that PDR or the corresponding PAR of that pair.

3.3.2.6 Reading From a PDR — The KPDR, SPDR, and UPDR outputs are collector-ORed, but only the chipselected PDR output will be available. The PAR/PDR read multiplexer that selects either PAR or PDR outputs
is shown on drawing SAPM. Selection is controlled by virtual address bit VAOS. When a PAR is addressed,

SAPC VA0S B H will always be high and the PAF inputs will be selected as the PAR/PDR multiplexer output. If
a PDR is addressed, SAPC VAOS B H will always be low and the PDR fields will be selected as the PAR/PDR
multiplexer output.

3.4

RELOCATION LOGIC

3.4.1

Address Inverters/Buffers

The virtual address inverters/drivers are shown on drawing SAPH. They convert the 16 BAMX (15:00) H address

inputs from DAPB, DAPC, and DAPD to virtual address outputs SAPH VA (15:00) B H. The 74504 inverters
are used to obtain inverted outputs SAPH VA (08:00) B L, required in the memory management.
3.4.2

12-Bit Adder

Refer to drawing SAPJ. Tfie 12-bit adder consists of three 74S181 4-bit ALUs and a 745182 Look-Ahead Carry

Generator. The function select inputs (S3:S0) on the 74S181 are connected H L L H to perform the add function F = A plus B. The mode control (M) inputs are connected low to select the arithmetic mode of operation.

The low order 745181 ALU adds SAPA + B + C SAF (09:06) H to SAPH VA (09:06) B H to produce SAPJ ADRS
(09:06) H. Fast simultaneous carry generation is performed by two cascade outputs, SAPJ ARIT AP H and SAPJ
ARIT AG H. These are applied to the 745182 Look-Ahead Carry Generator that generates the SAPJ COUT A L
signal applied to the next 4-bit ALU.

SAPA + B + C SAF (13:10) H and SAPH VA (12:10) H are full-added, with carry input

by the next 74S181 ALU.

Because of the possibility of a carry output, the 74S182 Look-Ahead Carry Generator

processes SAPJ ARIT BP H

and SAPJ ARIT BG H. Output SAPJ COUT B L is added to SAPA + B + C SAF (17:
14) H by a third 74S181

ALU to produce SAPJ ADRS (17:14) H.

Thus, the 7-bit block number of the virtual address VA (12:06) B H is added to the 12-bit base address
provided
by page address field bits PAF (17:06) H to provide SAPJ ADRS (17:06) H. These are the 12
most significant
bits of the relocated physical address. Typical add time is 36 ns.

3.4.3

Relocation Multiplexer

Refer to drawing SAPJ. The relocation multiplexer consists of the three 74S157 Multiplexer
chips, whose enable inputs are always enabled. The signal SSRE RELOC L is applied to the select inputs; therefore,
when the
KT11-C, CD is in operation (Paragraph 3.10.9), the A inputs SAPJ ADRS (17:06) H are selected

by the multi-

plexers to provide physical address bits SAPJ PA (17:06) H.
If the KT11-C, CD is not enabled, SSRE RELOC L will be high and the multiplexers will select the B inputs
as the
physical address. Under non-operational conditions, BAMX ¢15:06) H provide physical address bits PA (15:06)
H
directly from the central processor. The two most significant bits of the address PA (17:16)
are provided by
DAPD EX MEM FLAG H. This forces PA (17:16) to be asserted when BAMX (15:13) are asserted
(an I/O ad-

dress). Otherwise, PA (17:16) will not be asserted.
3.5

CONSOLE ADDRESS DISPLAY AND CONTROL

3.5.1

ADDRESS Display

The sources of the ADDRESS display bits SAPK DISP ADR (17:00) H are shown on drawings SAPH, SAPJ,

and

SAPK. Figure 3-4 is a simplified diagram of the ADDRESS source.
ADDRESS display bits SAPK DISP ADR (05:00) H are not affected by KT11-C, CD logic or

console Address

Display Select switch positions. The source of these bits is DAPB BAMX (05:00) H.
ADDRESS display bits SAPK DISP ADR (15:06) H depend upon the status of the KT11-C,
ting of the console Address Display Select switch. The source of SAPK DISP ADR {15:06)

CD unit and the set-

H for each condition

of these variables is summarized in Table 3-2.
The source of ADDRESS display bits SAPK DISP ADR (17:16) H is determined by the KT11-C,

CD status, the

console Address Display Select switch position, the console switches, and the DAPD EX MEM FLAG H

signal.

The source of SAPK DISP ADR (17:16) H for each condition is summarized in Table 3-2.

3.5.2

Console Mode Control

The Console Address Display Select switch performs mode and space select functions, in addition to ADDRESS

display selection (Paragraph 3.5.1). UBCJ DIS ADRS SEL (2:0) H inputs from the console are decoded by
a
7442 Decoder (drawing SSRK). The outputs are used with ROM OUT12

to set the appropriate space control

flip-flops under console control conditions (Paragraphs 3.10.4 through 3.10.6).

3.6

ABORT AND TRAP DECODE

Drawing SAPL shows the abort and trap decode logic. The abort control logic is also shown on SSRC;
the memory management trap control logic is located on the SSR module and shown on drawing SSRD.

Paragraph

3.11.2 is a detailed description of the trap control logic. A KT11-C, CD abort causes a processor interrupt that is

3-8

vectored through Kernel virtual address location 250 in D space. The abort is caused by one of four types of

illegal memory references. If one of these is detected by the abort decode logic, the memory reference is not
completed and the processor traps immediately to location 250 in Kernel D space.

DAPB BAMX < 05:00>H ‘D‘SAPH VA <05:00>BL —O > SAPK DISP ADR<05:00>H
>—— SAPH VA<15:06>8BH

B
Irr

DAPD,C BAMX <15:06>H

SAPJ PA <15:06>H

B
A
g

SAPJ

ADRS <15:06> H—Agg
|

ADDED TO VA)

74157

AggL

PROG PHYS DSPLY L——I

[74sS157

( PAF

SAPK DISP ADR<15:06> H

SSRE RELOC L

_—E
DAPD EX

SAPJ PAS17:16>H

745153

MEM FLAG H

74153

SAPJ ADRS<I17:16>H

SAPK DISP ADR<17:16>H

153

SSRE RELOC

SAPK SR<17:16 >B(1) H

74574

SSRK

(2)
UBCF

CNSLO7 (1)
H

CNSL

PHYS

DSPLY

SSRK PROG PHYS DSPLY L

Figure 3-4

11-1033

Sources of ADDRESS Display, Simplified Diagram

Table 3-2

Address Display Sources
Address Display

KT11-C, CD

Select Switch

Enabled

Source of ADDRESS Display Bits

17:16)

(15:06) | (05:00)

PROG PHY

EX MEM FLAG*

BAMX

PROG PHY

Yes

BAMX

CONS PHY

SWR

BAMX

CONS PHY

Yes

SWR

BAMX

KERNEL, IorD

BAMX

Yes

BAMX

SUPER, I or D

USER,IorD

745153

$1|s0 | INPUT

SSRA KY PH MEM AC (1) H———1

PDRH SWR

* EX MEM FLAG = BAMX ({15*14*13)H

The four categories of illegal memory references that will cause an abort are:

Non-Resident Page — Any attempt to access pages with ACF keys = 0, 3, or 7 causes an abort.

Read-Only Page — Any attempt to write into pages with ACF keys = 1 or 2 causes an abort.

Page Length Error: Address Too Low — If the page expansion direction is down and the block number

Page Length Error: Address Too High — If the page expansion direction is up and the block number is

is lower than the PLF, the address is too low and an abort occurs.
higher than the PLF, the address is too high and an abort occurs.

Abort Control Logic

3.6.1

The following paragraphs describe the abort decode logic used to detect these types of illegal memory references.
The abort flags that identify each type of abort condition are part of SRO (drawing SSRC).

3.6.1.1 Non-Resident (NR) Page Fault — The non-resident page keys are 0, 3, and 7. The ACF bits are decoded
to produce SAPL KEY =0 L or SAPL KEY =3 + 7 L. Either output asserts SAPL NON RES FAULT L, which
is one of the inputs that asserts SAPL ABORT COND H. Note (drawing SSRC) that SAPL NON RES FAULT H
will be written into SRO bit 15 as an indication of the cause of the abort.

3.6.1.2 Resident Read-Only (RRO) Fault — The RROT (resident read-only and trap) key is 1. The RRO (resident read-only) key is 2. If either key is decoded from the ACF and SAPL WRITE CYCLE H is high, a resident
read-only fault is detected and SAPL READ ONLY FAULT H asserts SAPL ABORT COND H. Note, on draw-

ing SSRC, that SAPL READ ONLY FAULT H will be written into SRO bit 13, as an indication of what caused
the abort. Also, SAPL WRITE CYCLE H will be asserted for either a DATO or DATIP bus cycle.

3.6.1.3

Page Length Fault — Two 7485 Comparators, shown on drawing SAPL, perform a high-speed compari-

son of the 7-bit block number, VA (12:06) B H and the 7-bit page length field PLF (06:00) H, which is the
authorized page length. The following subparagraphs expand on the page length examples presented in Paragraph 2.2.2.5 to explain the logic.

Address Too High — Refer to Figure 2-9. Assume the expansion direction is up (ED = 0) and the

authorized page length is 42, blocks. The number in the PLF will be set to 51 (41 10)> Which is the
highest block number that can be accessed. If the block number, VA (12:06) B H, is greater than the
PLF, comparator output A > B will go high, asserting SAPL PLF < VA. This signal is NANDed with
SAPD PGE EXPN DOWN L to produce SAPL ADRS TOO HIGH L.

Address Too Low — Refer to Figure 2-10. Assume the expansion direction is down (ED = 1) and the
authorized page length is 42, blocks. The number in the PLF will be set to 1264. If the block number, VA (12:06) B H, is less than the PLF, comparator output A < B will go high, asserting SAPL
VA < PLF. This signal is NANDed with SAPD + E + F PGE EXPN DOWN H to produce SAPL ADRS
TOO LOW L.

3.6.2

Internal Register Inhibit

The abort conditions decoded as described in Paragraph 3.6.1 are ORed to produce the SAPL ERROR H signal.

Signal SAPL ERROR H goes to the D input of the INHIBIT flip-flop on drawing SSRK. This flip-flop is clocked

at T4 of the Bust part of every memory cycle that is relocated. The flip-flop is cleared by either INIT or by doing an examine or deposit with the console Address Select switch in either “Program Physical” or “Console Physical” position. Thus, any abort condition asserts SSRK INHIBIT (1) L, which prevents any internal register
selection flip-flop from being clocked. Refer to the internal register control logic shown on drawing SSRL.

3-10

The SSRK INHIBIT flip-flop is required for proper operation of the internal register logic on SSRL when the RC
processor clock is set very slow (more than 1 us/time state) for maintenance purposes.
3.6.3 Memory Management Trap Decode

The decode logic for memory management trap conditions is also shown on drawing SAPL. The memory man-

agement trap conditions are specified by the ACF keys as listed in Table 2-2. These conditions are summarized
as follows:

Trap any attempt to read if the ACF key is 1.
Trap any attempt to write if the ACF key is 5.
Trap any access attempt if the ACF key is 4.

a.
b.
c.

When any of these conditions is decoded, SAPL MEM MGMT H is asserted. The resulting output is sent to the
memory management trap control logic located on the SSR module (Paragraph 3.11.2).
3.7

PAR/PDR READ MULTIPLEXERS

Refer to drawing SAPM. The purpose of the PAR/PDR read multiplexers is to select either the Page Address
Register or the Page Descriptor Register as the output that is applied to the internal bus data multiplexers shown
on drawing SSRJ. The PAR/PDR read multiplexers consist of four 74S157s that are always enabled.
One of 16 PARs or PDRs will be read, depending on the internal register address. The only difference in addresses of a specific PAR/PDR pair is bit VAO5. When VAOS is high, a PAR is addressed and the B inputs to the
multiplexers are selected as the SAPM PAR/PDR BIT (15:00) H output. When a PDR is addressed, VAOS is low
and the A inputs are selected.

3.8

UNIBUS ADDRESS DRIVERS

The Unibus A address drivers are shown on drawing SAPN. These drivers are enabled by the UBCA CPBSY BH
signal from the processor Unibus control logic. The 18-bit Unibus A address output, BUSA A (17:00) L, is made

up of physical address bits SAPJ PA (17:06) H and virtual address bits DAPB BAMX (05:00) H. The relocation
logic provides SAPJ PA (17:06) H. The relocation logic provides SAPJ PA (17:06) H (Paragraph 3.4).
3.9

STATUS REGISTER 3 (SR3)

Refer to drawing SAPN. SR3 is a 4-bit register consisting of a 745174 D-type flip-flop IC, located on the SAP
module. The purpose and format of SR3 are described in Paragraph 3.16.2.2. The SR3 contents are applied to the
APR address control logic shown on drawing SAPA. That logic is described in Paragraph 3.3.1.2.

SSRL INT SR3 (1) H is required to write data into SR3 and assert SSRL READ SR3 H, which gates the SR3 contents onto the processor internal data bus. The INT SR3 flip-flop is set when the SR3 address, 772516, is
decoded.

3.10

KT11-C,CD ROM AND DECODE

The KT11-C, CD ROM is a 16-bit extension of the CPU microcode ROMs which provides microcontrol signals
for memory management. The ROM receives its microaddress from the CPU as a dedicated copy of the RAR
A module
(RACD RAR {07:00)). This ROM is included on the M8108 module of the KT11-C and the M8108-Y

of the KT11-CD. Both modules provide a unique ROM pattern. The M8108 ROM contains the memory management microcode extension for the KB11-A microprogram. The M8108-YA ROM contains the memory management microcode extension for the KB11-D microprogram.

NOTE
The only difference between the KT11-C and the KT11-CD is

the replacement of the M8108 module with the M8108-Y
A
module.

The KT11-C, CD ROM includes four 256 X 4 Read-Only Memories. The ROM and associated decode logic

for

the KT11-C, CD is shown on drawing SSRA. A chart that shows which processor microstates are affected

by the
ROM is contained on drawing SSRM for the KT11-C and SSRN for the KT11-CD. The KT1 1-C, CD logic decodes

the ROM output to control the operation of the memory management unit in coincidence with processor control
operations. Several ROM bits control loading SR1 with autoincrement/decrement information. Seven ROM bits

provide separation of I and D space addresses; other ROM bits provide miscellaneous control.

3.10.1

ROM Organization

Each 74187 ROM provides 256 4-bit locations that are addressed by ROM address bits RACD RAR (07:00) H.

Drawing SSRM (for the KT11-C) and SSRN (for the KT11-CD) are charts that lists the processor microstate
associated with each location and indicates the ROM outputs that are asserted when each location is

name

addressed.

Thus, the charts represent truth tables for 256 X 16-bit ROM, made up of the four ICs shown on drawing
SSRA.
For example, using SSRM when the KB11-A processor enters microstate D40.20, ROM location 121 is addressed
by the RACD RAR (07:00) H inputs and ROM outputs 4, 5, and 7 are asserted. If D10.30 (122), D40.30
or D10.40 (311) were addressed, these same ROM outputs are asserted. The bus transactions involved

(131),

in these

microstates appear identical to the KT11-C unit.

ROM Output 4:

Destination Mode

ROM Output 5:

BSOPI

ROM Output 7:

Bust Cycle

Thus, the KT11-C, CD ROM augments the processor ROM outputs for any microstate that involves memory
management. Table 3-3 lists the ROM function that is decoded from each ROM otuput, or combination of ROM

outputs. Paragraph 3.10.2 summarizes ROM output functions by ROM output number.

Table 3-3
ROM Output Decoding
SSRA ROM

ROM Output

Outputs

Asserted

Function

Signal Derived

413121

Purpose

ROM IC #1 (E7)

X010 |0

None

N/A

X[{010 |1

SSRA ROM OUT1 H

SSRA RESTORES PA (1) H

No operation
Forces processor to restore PS if abort
occurs during trap sequence.

X101

SSRA ROM OUT2 H

SSRA AUTO DEC (0) H

Clears AUTO DEC flip-flop on SSRA

SSRA ONE CHANGED (1) H | to indicate increment. Sets ONE
CHANGED flip-flop on SSRA.
X{0]1]1

SSRA ROM OUT! H

SSRA AUTO DEC (1) H

SSRA ROM OUT2 H

SSRA ONE CHANGED (1) H | decrement. Sets ONE CHANGED

Sets AUTO DEC flip-flop to indicate

flip-flop.
X|1{0|0

SSRA ROM OUT3 H

SSRA BRK.30 (1) H

Indicates processor is in BRK.30 microstate. Sets INSTR COMP flip-flop and

clears SR2.

3-12

Table 3-3 (Cont)

ROM Output Decoding

SSRA ROM

ROM Output

Outputs

Asserted

tput

Function

Signal Derived

413121
X[1{01

Purpose

ROM IC #1 (E7) (Cont)
SSRA ROM OUT1 H

SSRA JSR.30

Prevents destruction of processor reg-

SSRA ROM OUT3 H

ister contents if an abort occurs during
a JSR.

Xj11110

SSRA ROM OUT2 H

SSRACLR16+17H

SSRA ROM OUT3 H
X1

SSRA ROM OUT!1 H

Clears SR16, SR17 flip-flops on SAPK

following a START or CONTINUE.
SSRACLR PSR (1)H

SSRA ROM OUT2 H

Clears PS Restore flip-flop in FET.00

and BRK.00 microstates.

SSRA ROM OUT3 H
XXX

SSRA ROM OUT4 H

SSRADST(1)H

used with MMRO (08).

8{7(615
X[ XIX]1

Provides maintenance facility when

ROM IC #2 (E8)
SSRA ROM OUT5 H

SSRB MF/TP SPACE L

Permits loading Kernel, Supervisor or

User flip-flops during BSOP1 Bus condition if MFP or MTP instructions are
utilized.
X[X|1

SSRA ROM OUT6 H

KERNEL DATI

Bus transaction is Kernel mode DATI.

X|1|XiX

SSRA ROM OUT7 H

BUST

Indicates BUST cycle.

1{X]|X[X

SSRA ROM OUT8 H

I IF MTP SPACE

Forces I space if current instruction is
MTPI or MFPI and both the current
and previous modes are not both user.

1211{10/9
X X] X]1

ROM IC #3 (E9)
SSRA ROM OUT9 H

SSRB I SPACE ALWAYS

Sets I SPACE flip-flop on SAPA if current microstate enters I space.

SSRA ROM OUT11 H|

IIFPREV =1

Asserts SSRB I SPACE A L if previous
memory cycle was I.

X] XX

SSRAROMOUTI2H|

TIIFCNSL=1

Asserts SSRB I SPACE A L if DEPosit
or EXAMine console operation.

16[15/14{13
Xl X1 X]1

ROM IC #4 (E10)
SSRA ROM OUTI3 H|

IIF SRCF7

Asserts SSRB I SPACE B L if source
register field is 7.

X X1

SSRA ROM OUT14H|

IIF DSTF7 * -(MTP + MFP) | Asserts SSRB I SPACE B L if destina-

tion register field is 7 or instruction is
not in MTP or MFP space.
X1

X|X

SSRA ROM OUTI15 H{

IIF DSTF7

Asserts SSRB I SPACE B L if destina-

tion register field is 7.
1|

X] X|X

SSRA ROM OUT16 H|

I@IF DST F7 and DST M2

Asserts SSRB I SPACE B L if destination register field is 7 and destination
mode 2.

3.10.2

ROM Outputs (3:1) and Decoders

ROM OUT (3:1) provide control of both CPU and memory management during abort sequences. They also provide specialized control of the internal status of memory management during instruction execution. The control
functions are encoded. (Refer to Paragraphs 3.10.2.1 through 3.10.2.5 for details.)

ROM outputs ROM OUT (3:1) H are decoded by two 748157 Selectors used as high-speed decoders. When ROM
F16 bit M2 is logic 0, the lower decoder is enabled and the upper decoder is disabled. ROM bit M1 is the select
input. When it is logic 0, A inputs are selected; when MO is logic 1, the SVC.70 function is decoded. When M1 is

logic 1, B inputs are selected. Under these conditions, the autoincrement function is decoded when MO is logic O,
and the autodecrement function is decoded when MO is logic 1.
NOTE

Either autoincrement or autodecrement provides SSRA ONE
CHANGED (1) H.

When ROM bit M2 is logic 1, the upper decoder is enabled and the lower decoder is disabled. M1 is the select input. When M1 is logic 0, A inputs are selected. Under these conditions, the BRK.30 (instruction complete)

function is decoded when MO is logic O; when MO is logic 1, the

JSR.30 function is decoded. When M1 is logic 1,

the decoder outputs are irrelevant.

The truth table for the ROM outputs is shown on drawing SSRA. The outputs are clocked into the 74175 flipflops by SSRK PULSE 23 H, which occurs near the beginning of every processor micrqcycle (Paragraph 3.14).

The following paragraphs describe the functions of microstates decoded from the ROM OUT (3:1) outputs.
3.10.2.1

RESTORE PS — SSRA RESTORE PS (1) H is asserted only during processor microstate SVC.60. This

is the Bust part of the push of the old PS onto the stack specified by the new PS during any trap or interrupt se-

quence. SSRA RESTORE PS (1) H is inverted and renamed SSRA SET PSR L. This output sets the PSR flipflop at SVC.60. The PSR flip-flop remains set until SSRA CLR PSR (1) H is asserted, which occurs during the
FET.00 or BRK.00 microstates. Thus, the PSR flip-flop is only set during the push of the old PS and PC onto

the stack during a trap or interrupt. If a KT11-C, CD abort occurs during either of these push attempts, the old
PS and PC must be restored. The old PS is temporarily stored in the processor BR; the old PC is temporarily
stored in the processor DR.

The purpose of SSRA PS RESTORE (1) H is to force the processor through microstates ZAP.10 through ZAP.30
and to enable clocking of the PS register in the processor. Refer to Flow Diagram 12 in the KB11-A or KB11-D

drawing set. The old PS is restored to the PS register, and the old PC is restored to the PC register. PS RESTORE
allows proper recovery from aborts on interrupt and trap sequences.

3.10.2.2

SSRA JSR.30 (ROM (3:1) = 5) — If an abort occurs during a JSR instruction, SSRA JSR.30 (1) H as-

serts SSRA INH PWE H (Inhibit Pad Write Enable), which prevents the processor from writing into the general
registers. This function may be invoked if an abort occurs on the push of the destination register onto the stack
during a JSR (microstate JSR.30) or if an abort occurs on the fetch of the new top of the stack (MRK.20).
At JSR.30 the old PC is normally written into the destination register thus destroying the destination register

contents. SSRA INH PWE prevents this destruction. At MRK.20 the stack pointer, register 6, is normally modified by N (the MARK argument) + 2. SSRA INH PWE prevents this modification if an abort occurs at the new
top of the stack. Signal SSRA JSR.30 allows proper recovery from aborts at

3-14

JSR.30 and MRK.20 microstates.

3.10.2.3

BRK.30 (ROM (3:1) = 4) — The BRK.30 microstate is decoded from the ROM as an indication that

the current instruction is complete and that some interrupt or trap memory reference is about to begin. BRK.30
(1) His ANDed with SSRC NO ERROR H to set the INSTR COMP flip-flop (drawing SSRE).

3.10.2.4

AUTO DEC (ROM (3:1) = 3) — The AUTO DEC signal is decoded from the KT11-C, CD ROM for any

microstate in which autodecrementing a general register is required. The AUTO DEC signal controls the MSB of
each SR1 byte and configures the 2’s complement generator (Paragraph 3.12).

3.10.2.5

ONE CHANGED (ROM (3:1) =2 or 3) — The ONE CHANGED flip-flop is set when any microstates in

which autoincrement or autodecrement occurs is decoded from the KT11-C, CD ROM. This flip-flop sets the
ONE AUTOED flip-flop (Paragraph 3.12) for the purpose of clocking byte 0 and byte 1 of SR1. It is initially
cleared so that the first general register that is “autoed” is described in byte 0 of SR1. ONE AUTOED is then set.

If a second general register is autoed during the instruction, that general register description is loaded into byte 1
of SR1.

3.10.3

ROM OQutputs (16:04)

SSRA ROM OUT (16:04) inform the memory management logic of the occurrence of certain conditions in the
processor. The significance of these outputs is described below.

ROM OUTO04 (DST) is asserted to indicate destination mode. It is used during maintenance mode only in conjunction with bit 08 of MMRO to enable relocation during the execution cycle of the instruction. When the current memory reference is the final reference of a destination calculation, ROM OUT 4 H is asserted. The micro-

states that provide ROM OUT 4 are listed on SSRB. The ROM OUT 4 H output controls the state of the DST
flip-flop, which is clocked by TIGC TI L. This provides the “maintenance” facility that is used by certain memory
diagnostic programs.

ROM OUTO05 [CLOCK PREV MODE (MT/FP)] is asserted during ROM cycles that assert BSOP1. This is shown
on the Flows as BC-BSOP1. BSOP1 is normally called for in an execute cycle that is common to several instructions which have different bus operation requirements. Thus, BSOP1 is a DATI for MFP instructions and a DATO
for MTP instructions. ROM OUTOS5 is used to clock the previous mode (PS(13:12)) into the K, S, U flip-flops
during MFP and MTP instructions.

ROM OUTO06 (KERN DATI) is asserted when the BSC ROM bits=2 and forces Kernel mode during the Service
Flows (Paragraph 3.10.4). During these cycles, the new PC and PS are loaded from Kernel space. This condition

appears on the Flows as BC-KERN DATI and occurs only in ROM cycles SVC.00 — SVC.30, BRK.30 and
TRP.10. These cycles all force Kernel mode but do not change PS{(15:14). BRK.30 and TRP.10 are followed by

SVC.00, 10, 20 and 30. In this last cycle, the current mode bits, PS{15:14) are stored in the previous mode bits,
PS(13:12), and the new current mode bits are loaded into PS(15:14) from BR(15:14) (IBS=2).

ROM OUTO7 (BUST) is asserted during all BUST cycles. ANDed with T1, this bit is used as a clock in several
places in Memory Management.

ROM OUTOS8 (I SPACE IF MT/FPI) is asserted during destination cycles that are used by MFP and MTP instructions, along with other instructions. I space is forced when this bit is asserted if the instruction is an MFPI or an
MTPI [(IR15=0)*(IRCC MFP+MTP)]. See ROM OUT14.

ROM OUTO09 (I SPACE ON IND WORD FETCH) is asserted during all fetch cycles and during cycles that read
index words. Since these are all in I space, I space is unconditionally forced when this bit is asserted.
ROM OUT10 is not used.

ROM OUT11 (I11F INST START IN 1) is asserted during the EXC.00, EXC.10, NEG.20 and SHR.10 micropro-

gram cycles (Flows 11). These cycles execute the DATO/B portion of a DATIP/DATO transaction and thus must
be executed in the same space as the previous DATIP data transfer cycle.

ROM OUT12 (DEPOSIT+EXAMINE) is asserted only during Console EXAM or DEP cycles (DEP.10, DEP.20,
EXM.10, EXM.20, Flows 14). These cycles are executed in the space designated by the Console ADDRESS
SELECT switch.
ROM OUT13 (SRCM = 1+2+3+4+5)

is asserted during cycles that fetch the source operand for binary instructions

with source modes 1 — 5. If the source register field is 7, this operand is the second word of the instruction and
as such is in I space. These cycles are S13.00, S13.01, S13.10 and S45.10 on Flows 1.
ROM OUT14 (DSTM = 1+2) is asserted during Destination Mode 1 or 2 cycles that are common to MTP and MFP
and to other DAC or O/class instructions. If the destination register field is 7, the operand is in I space. ROM

OUTO08 is also asserted when ROM OUT 14 is asserted (D12.00, D12.01, D12.10, D12.60, D12.80 and D12.90,

Flows 5), so that I space is addressed when ROM OUT14 is asserted.
1.

If the instruction is either MFPI or MTPI (I space is accessed, by definition), or

The Destination Mode of the instruction (not MFPI or MTPI) is 7 (the word accessed is in I space). See
ROM OUTOS.

ROM OUT15 (DSTM = 3) is asserted during Destination Mode 3 cycles (D30.10, D30.80 and D30.90). If the
destination register field is 7 during these cycles, the addressing mode is Absolute and the address word should
come from I space.
ROM OUT16 (FLOATING POINT INST) is asserted for FPP Immediate Mode bus operations (FSV.00 and

FSV.10, Flows 12). It is used to ensure that the immediate operand comes from I space if DM?2 and DF7.

3.10.4

Kernel Space Control

Refer to drawing SSRB. Four conditions select the KERNEL SPACE flip-flop:
a.

By doing an EXAM or DEP operation under console control with the ADDress SELect switch set to

Kernel I or Kernel D. (SSRK CNSL KERNEL H generated.)
b.

By SSRA ROM OUT6 H, indicating the Kernel DATI bus condition service flows (trap, interrupt, or
abort).

By BSOPI bus condition (SSRA ROM OUTS5 H) if the instruction is a move to MTP or from MFP previous data space, and the previous processor mode was Kernel.

By processor status word if current processor mode is Kernel, the console is not active, and the instruc-

tion is not a BSOP1 transaction and not a move to or from previous data space.

Any of the above conditions qualifies the D input of the KERNEL SPACE flip-flop. It is clocked and reset to
assert SSRB KERNEL SPACE (1) L at T1 of the Bust cycle.

3-16

3.10.5

Supervisor Space Control

Refer to drawing SSRB. The three conditions that select the SUPER SPACE
select KERNEL SPACE (Paragraph 3.104,a, c,and d). The SUPER SPACE
a.

flip-flop are similar to those that
flip-flop is qualified if:

Selected by doing an EXAM or DEP operation under console control with the

set to Super I or Super D (SSRK CNSL SUPER H generated).

ADDress SELect switch

Selected by BSOP1 bus condition if instruction is a move to or from previous data space,

vious processor mode was Supervisor.

and the pre-

Selected by processor status word if current processor mode is Supervisor, the
console is not active,
and the current instruction is not a BSOP] transaction and not a move to or
from previous data space,
and not a Kernel DATI.
When any of these conditions are true, the SUPER SPACE flip-flop asserts

3.10.6

SSRB SUPER SPACE (1) L.

User Space Control

The only differences between User space control conditions and Supervisor space control

are the processor status

word bits and console control switch selections. Thus, the USER SPACE flip-flop is qualified
a.

if:

Selected by doing an EXAM or DEP operation under console control with the ADDress SELect

switch

set to User I or User D (SSRK CNSL User H generated).

Selected by BSOP1 buscondition if instruction is a move to or from previous data space, and
the pre-

vious processor mode was User.

Selected by processor status word if current processor mode is User, the console is not active,

and the

current instruction is not a BSOP1 and not a move to or from previous data space,
and not a Kernel

mode DATI.

3.10.7

1 Space Control

Refer to drawing SSRB. The I space decoders assert I SPACE A L or I SPACE B L under the following
conditions:
a.

SSRA ROM OUTS H. I space is selected if the current instruction is a move to or from

IRCA IR 15 (1) L ensures D space (MTPD + MFPD).

previous I space.

SSRA ROM OUT9 H. This ROM output is an unqualified request for I space.
No other conditions

are required to assert I SPACE A L.

Used for instruction fetches.

SSRA ROM OUT11 H. This output asserts I space if previous memory reference
was I space. It is
ANDed with the output of the PREV = 1 flip-flop, which stores the I space condition
from the previous memory cycle. Used for continuation of DATIP bus cycles.

SSRA ROM OUT12 H. This output asserts I space if I space is selected at the console
control (SAPP

CNSL I SPACE H asserted).

SSRA ROM OUT13 H. This output asserts I space if the current instruction is
source register 7 (DPCH

SRC F7 L asserted).

‘

SSRA ROM OUTI14 H. This output asserts I space if the current instruction is
destination register 7
(SSRB DST F7 H), and if the instruction is not an MTP or MFP instruction.
SSRA ROM OUT15 H. This output asserts SSRB I SPACE A L whenever
the destination register

SSRA ROM OUT16 H. This output asserts SSRB I SPACE A
L whenever the destinati

is 7.

on mode is 2 and

the destination register is 7.

3-17

The I space control logic (drawing SSRB) is required to provide high-speed memory management throughput because there is a lack of direct association of I space for each specific microstate. SSRB I SPACEA L and SSRB
I SPACEB L are used to set the I SPACEA and I SPACEB flip-flops (drawing SAPA) during T1 of the Bust cycle.

This logic minimizes the delay required to generate the most significant PAR/PDR address bit, which determines
whether an I space or D space PAR/PDR set is addressed.
STATUS REGISTER 0 (SR0)

3.11

The contents and format of SRO are described in Paragraph 2.3.1. The SRO bits and control logic are shown on
drawings SSRC, SSRD, and SSRE. The SRO format is shown in Figure 2-10.
3.11.1

Abort Flags SRO (15:13)

Refer to drawings SAPL and SSRC. SRO bits 15, 14, and 13 are the memory management abort flags that indicate the cause of an abort. The fault detection logic is described in Paragraph 3.5 and shown on drawing SAPL.
The fault signal outputs are SAPL NON RES FAULT H, SAPL PGE LENGTH FAULT H, and SAPL READ
ONLY FAULT H. These inputs are applied to a 74157 Multiplexer at the B inputs. If not writing into the SRO,
these inputs are selected as the data inputs to the 74175 flip-flops that store SRO bits (15:13).
SSRE STROBE OK L asserts SSRC STROBE ENABLE H when the following conditions are met:
a.
b.
c.

Not a BEND (processor will not complete memory cycle).
No errors have been detected on previous memory references.
The current memory reference is not accessing an internal register.

KT11-C, CD is enabled.

SSRE STROBE ENABLE H allows the fault information to be strobed into SRO by the SSRK PULSE BC89 H

clock pulse that occurs during the processor Pause cycle. The contents of SRO (15:13) are ORed to the data input of the NO ERROR flip-flop, which is clocked by the SSRK PULSE BC910 L clock pulse. If no error flags
are set, the NO ERROR flip-flop will remain set.

Data can be written into SRO bits (15:13) under program control. Buffer register bits PDRB BR (15:13) B L are
applied to the A inputs of the 74157. When SSRL WRITE SRO REG H is asserted (Paragraph 3.5.1) and SAPH
VA (02:01) B L indicate the SRO address, the A inputs are selected as the data inputs to the SRO flip-flops. The
data will be written into the SRQ when SSRK PULSE BC89 H occurs. In this case, SSRC STROBE ENABLE H
is asserted by SSRE WRITE SRO H and UBCC HI BYTE H.
NOTE

Setting the SRO error flags under program control does
not cause an abort.

The ABT FLG flip-flop (drawing SSRC) will only be set when the SAPL ABORT COND H signal is asserted and
no internal register accesses are in progress. The state of SRO bits 15, 14, 13 has no effect on the ABORT FLAG.
Figure 3-5 is a simplified diagram that depicts the KT11-C, CD logic and how it interacts with the KB11-A, D
logic to force a trap to Kernel D space location 250 when an abort condition is detected. The signal mnemonic

prefixes indicate where each signal is generated in the two units. Refer to the KB11-A or KB11-D drawings for
more complete details.

3-18

N2TV1OI9OL0I7QY é1879O3A5L

)

SW$SO3IYAY (Ts¥0Ma2v)

NYOV 8oV0S8NL0H 4lLONLSV3‘03LHISVAMOW3W

\JG)

9y3IININIJIIHTM38

LYH8OWOVY

O—

viS h L
891 bl H

HANOJLH08Y1dVS 7MO01S¥QVTaVvs

‘LNL3QISNIYV-NYON4

3—1o0v5d3N00K x3JNOW3¥:VO3IS3H
0'OSAL4UNdY2VLZS

oNI LV ONZLLI

413s980nO¥4vd0

OL3H9VO84dV

souanbeg [01u0) HOQY @ ‘V-114M/AD O-TILA §-¢ 8L

79741408V|935JMS LHVdIVILINTONINGMOT33LVLS7
80vy

NOILINYLSNI

3-19

£HY891820

3.11.2

Memory Management Trap (SRO Bit 12)

The memory management trap control logic is shown on drawing

SSRD. The decode logic that detects trap con-

ditions is shown on drawing SAPL and described in Paragraph 3.6.4.

the KT11-C, CD trap control logic and the interaction with the

3.11.2.1

Figure 3-6 is a simplified diagram that shows

KB1 1-A, D trap control logic.

Enable Management Traps — The ENABLE MGMT flip-flop (SRO

trol. This is accomplished by writing into the SRO with data bit
BR0O9
put is clocked into the ENABLE MGMT flip-flop by SSRE

during the Pause cycle.

bit 09) must be set by program con-

on alogic 1. The SSRD DATA 09 H in-

SRO HIB CLK L, which is produced when T3 occurs

Several other conditions must be satisfied before a memory manageme

nt trap can occur. These are:

SSRE RELOC H must be asserted, indicating the KT11-C, CD
is enabled.
The bus transaction has not been terminated by Bus End (BEND).

No internal register is being accessed.

No abort occured during the memory access.

3.11.2.2 Pre-Management Trap — If the conditions specified
in Paragraph 3.11.2.1 are satisfied and one of the
three memory management trap conditions is decoded (Paragraph
3.6.4), SSRD PRE MGMT TRAP H is asserted.
Because the MEM MGMT TRAP DETECTED flip-flop is initially
cleared, the MGT TP DET DLY L signal is high
at this time. As a result, SSRD CUR FLT L causes SSRD MEM
MGMT TRAP L to be asserted. This is the trap
signal that is sent to the processor. The same conditions that caused
SSRD MEM MGMT TRAP L to be asserted
allow the MEM MGMT TRAP DETECTED flip-flop to be direct-set when
clock pulse SSRK PULSE BC89 H
occurs. SSRD PRE MGMT TRAP H guarantees that a trap will be executed

instruction, before the next instruction is started.

3.11.2.3

on the last memory reference of an

Memory Management Hold — When SSRK PULSE BC89 H occurs, SSRD

MEM MGMT B H is asserted.
SSRD MGT TP DET DLY L will remain high for 50 ns. Thus, a 50-ns SSRD
SET MGMT HOLD L pulse is pro-

duced to direct-set the MEM MGMT HOLD flip-flop. The purpose is
to maintain the SSRD MEM MGMT TRAP L
signal to the processor until it is acknowledged. Because traps are not
handled by the processor until the end of

an instruction, several memory references may occur before the processor
sends TMCA SEG ACKN L, which
clears MEM MGMT HOLD. Once the MEM MGMT TRAP DETECTED
flip-flop (SRO bit 12) is set, it will not

cause another trap until it is cleared, even though additional

trap conditions may be detected. It is normally

cleared under program control by writing a 0 into bit 12 of SRO.

3.11.2.4

Writing Into SRO Bit 12 — The MEM MGMT TRAP DETECTED

program control by writing into the SRO with data bit SR12ona

1 or 0.

flip-flop can be set or cleared under

SSRD DATA 12 H is clocked into the

flip-flop by SSRD SRO HIB CLK L. Because SSRD PRE MGMT TRAP
H and SSRD MEM MGMT B L are

asserted, no memory management trap will occur.

3.11.3

not

Trap Flag (SRO Bit 11)

The TRAP flip-flop (SRO bit 11) is shown on drawing SSRD.
The MEM MGMT HOLD flip-flop is set by the positive-going

The flip-flop is direct-set by the TRAP L input.
edge of the TRAP L signal. As a result, the SSRD

MEM MGMT TRAP L signal is sent to the processor. The memory
management trap service routine must inter-

rogate the SRO to determine whether the trap was caused

or by the trap flag.

by an access code violation detected by the KT11C,

The flag can be set or cleared under program control

by writing into the SRO with data bit BR11 set to 1
or 0.
Setting the TRAP flip-flop under program control does
not cause a memory management trap.

3-20

TdVS 18Me=A3N T

¥QMS4D

3-21

QdMyVS YMT "

OTNIIM1'L¥1331S3YY] 1LO8N24

biStvl

OdVS NL V H(}

€SL 1

a91L

ANIHSS
793y

¥0dOSNNIOLIv1LI3118OSN3OHD1Y04

biSHL

@dV3Yy3LX9OYv1e4HV1IvLdN O0l43NSIV3L03¥8d
VOWL 741938
MRk

SINIL ONIYNAQ
3SNVdJ-NON

VOWLd4+NOD+93S7

11938

VOWL T93S
NXOVY

BY el

3Nyt H

sbL L0SbLl= (OcHD S30H04 OYIIW

T I N Y I N AVNLYIA

3
S
N
v
d
$
M
0
1
0
4
¥
O
1
D
3
A
0
1
d4b0V=VN4Al0d:VYt¥=dL4OV:0iS3Vl=ILNNI4OOE1SdMv3QVLvILW3N4YIMIW7934 OHvSSbbLQOLuHSSH‘L100OW3SN38I'1WLS253tN30AI-10WD13¥9OO70dSV3W1N4aN¥1N333088a3(y7)19,1b3L0S,HQS3LT1M0OOHNIIQYSIV1QYu1¥S330‘SNO59SPWdl0O33AvIH3S3738WybM087lL4L9V01NV4N3YOd3N5W3 dYSM0vJOSHTLO13N0I0V4N4‘Od—I5SN9GIOHlgo(e)NVQ19I3MQ31HLy9YMs+3I4S'WN3VISYdWN»vCdLHIONOW S9o1l YOSHVLOWL OvSHVLIWLHpOONSOtHL OsHbL
3Insig9-€1W08O¥1SN1SN31S"8OAW8=2HO}NI¥LVdIB-M14)/dD dei]joryuLo33)990NMo1DSuagHsnbagXIO9WLHoygpasagS9qNNuIInYSy¥NSNXAIG3V}30AAUNSSdIINXVOSdQHN3240I01PUlawi}23uanbas

Sa34v31)OL30I1NA30AYIdY¥d,Q10H,OYSLI8SINL'2! ; viSbLSuodsk vLSHL 89153IAEN3

oaovwbootlsovvzs|osVdVSSpH=MAe3GN=AAINTAADISb~Lio)/-.rs_csmuN:OMS.H\__ONJODdNaatIOd3ISs1)dL4vI43yGv\3lS—Na4C(OLdvD/W>LOWMO4W9NdIY13H811H35OLJOIATYISaWY3‘H7d9v0d¥8lu1dNOD0iISbJd5SdL1vyA8°Ny0Sl3l2LS'1i0#4as1ANnH3g¥Y83,IowommsmnWd_vI.vmaW:lqN(aL1\W)JOW/-OGHYoue{0)3NWTOMDOSObNHLX9|N=O1Y3T3S8b9NL03193sH()HS$3bSI0yNHH0IOAN0SQ4DY3dS0v8Yo2lL
¥08S3008d
S3TH5YINNSVDIdS*IA3Y870€vAiS0d1l40

0L %48 10"

OWYLg
WYE90Hd

116£80-

O‘SH3ILVLNS YL3HvLO CSH31OVI1NS

*310N

3.11.4

DST MODE (SRO Bit 08)

Refer to the mode/status control logic shown on drawing SSRE. The DST MODE flip-flop (SRO bit 08) is set or
cleared under program control by writing into the SR0 with data bit BRO8 set to 1 or 0. The data is clocked into

the DST MODE flip-flop by SSRE SRO HIB CLK L. This bit is set by program control during maintenance operations, which are performed with the RELOCATING flip-flop (SRO bit 00) cleared. When the DST MODE flipflop is set, the true output is ANDed with SSRA DST (1) H to assert the SSRE RELOC H signal. SSRA DST (1) H
is decoded from the ROM when the final destination address is calculated. The purpose of this logic is to assert
SSRE RELOC H only when the final address is calculated; thus, in the maintenance mode, only the final address
is relocated and protected by the KT11-C, CD unit.
NOTE

SRO bit 08 is used by the KT11-C, CD diagnostic programs and
is not to be used for any other purpose.

3.11.5

INSTR COMP (SRO Bit 07)

Refer to drawing SSRE, which shows the INSTR COMP flip-flop, SRO bit 07. This bit indicates the status of
each instruction. It is cleared at the beginning of each new instruction if the preceding instruction was executed

without a page error. When the BRK.30 microstate is decoded at the ROM output, the INSTR COMP flip-flop is
again set. Reaching the BRK.30 microstate implies that an interrupt is in progress and that the next memory reference will not be caused by an instruction. Setting the INSTR COMP bit in the SRO provides the error handling
routines with a means of determining whether the current instruction needs to be repeated in the course of recov-

ering from an abort or whether some interrupt sequence will have to be emulated.

3.11.6

SRO Mode Field (SRO Bits (06:05?)

The SRO mode field (bits 06 and 05) is shown on drawing SSRE. These bits are determined by the SSRB SRO
MODE (1:0) H D inputs to the 74175. The truth table for these inputs is:

SSRB SRO Mode

Space Mode Asserted

SSRB KERNEL SPACE (1) L
SSRB SUPER SPACE (1) L
SSRB USER SPACE (1) L
None (Illegal)

SRO Mode Field
1

H
L

L
L

01
11

SRO mode field 10 is illegal. Any attempt to access memory in that mode is aborted. Because no space is

selected, the outputs of all PAR/PDRs are high. The ACF is therefore 111 (key = 7), an abort condition.
The SRO mode field bits are clocked into the SRO at the end of the Pause cycle by SSRK PULSE BC89 H if
SSRE STROBE OK H is asserted. This only happens when:
a.

KT11-C, CD is enabled.

No BEND is issued by the processor.

No internal register is involved.

No paging error was detected on a previous bus cycle. If an error was detected, the mode field associated with the previous memory reference must be retained in SRO (06:05) to aid in error recovery.

3-22

Address Space — I/D (SRO Bit 04)

3.11.7

Refer to drawing SSRE. SRO bit 04 indicates whether I or D space is being addressed. The bit is stored by one
D-type flip-flop of a 74175. If I space is not addressed, SAPA IND DATA H is high at the input, and SRO bit 04
will be set when clocked, indicating D space is addressed. The bit is clocked under the same conditions as described in Paragraph 3.11.6.

3.11.8 Page Number (SRO Bits (03:01))

Refer to drawing SSRE. SRO bits {03:01) are stored by three D-type flip-flops. The inputs are SAPH VA
{15:13) H, which represent the page number being addressed. These bits are clocked as described in Paragraph
3.11.6.

KT11-C, CD RELOCATING (SWO0 Bit 00)

3.11.9

Refer to drawing SSRE. The KT11-C, CD RELOCATING flip-flop (SRO bit 00) is only set under program control
by writing into the SRO with data bit BROO set to 1. Normally, setting SRO bit 00 will assert SSRE RELOCH. T
The only exception is when performing a physical memory access from the console. Then, SSRA KY PH MEM
AC (0) H goes low and inhibits SSRE RELOC H. This allows the address set on the console switches to address
the physical unrelocated address.
NOTE

This bit essentially turns the KT11-C, CD on and off.
3.12

STATUS REGISTER 1 (SR1)

Refer to drawing SSRF. Status Register 1 is a 16-bit register comprising four 745174 D-type flip-flops. (Two

flip-flops on each 748174 are not used.) SR1 keeps track of any autoincrementing or autodecrementing of the
general registers that may occur during the execution of instructions. The layout of SR1 is shown in Figure 2-11.
When a general register is either incremented or decremented, the general register address GRAC GRA (2:0) BH
and the number of bits by which the register was modified are stored in SR1. SR1 is divided into bytes Oand 1.
The low order byte (byte 0) is written first. SR1 is a read-only register; it cannot be written into under program
control.

3.12.1

General Register Address

The general register address is available on inputs GRAC GRA (2:0) and is applied to the three low order bits of
each byte in SR1. When the general register destination is in Register Set 1, GRAC GRA3 L is asserted and

SSRF GRA3 B H goes high. The purpose of this logic is to inhibit SSRF GRADO B H if general register 17 (User

mode Stack Pointer) is addressed. Thus, a reference to GRA17 is stored in Status Register 1, Register Number
field as R6.

3.12.2 Autoincrement/Autodecrement

The constant that indicates the number of bits by which the general register was modified is available on inputs
DAPD KOMX {03:00) B L. The KOMX constant multiplexer provides only constants 1, 2, 4, or 8; thus, only one
of these inverted inputs will be logic 0 for any of these four constants. When the general register is decremented
by a constant, the processor “subtracts” a positive constant. Therefore, the 2’s complement of the constant is

generated by the KT11-C, CD logic. The 74S157 Multiplexer is used as a 2’s complement generator for this purpose; the 748157 is always enabled. During a decrement operation, SSRA AUTO DEC (0) H is low and the A inputs are selected to provide the 2’s complement of the constant. During an increment, SSRA AUTO DEC (0) His

3-23

high and the B inputs are selected to provide the constant as a positive binary number. Table 3-4 shows the con-

stant multiplexer truth table for both decrement and increment outputs. The constant is input to bits SR1
(06:03) of byte 0 or SR1(14:11) of byte 1. The SSRE AUTO DEC (1) H signal is input to SR1 as the MSB of
each byte. This bit functions as a sign bit for each byte, indicating a decrement or an increment operation.

Table 34

Truth Table for Constant Multiplexer Outputs

1
2
4
8

3.12.3

SSRA AUTO DEC (0) H

SSRA AUTODEC (1)H

DAPD KOMX B L
Constant

01 +00

1
1
1
0

1
1
0
1

1
0
1
1

0
1
1
1

1
1
1
1

1
1
1
0

1
1
0
0

1
0
0
0

0
0
0
1

0
0
1
0

0
1
0
0

1
0
0
0

Examples of SR1 Loading

As an example of SR1 loading, assume general register R5 is autoincremented by 2 in the source calculation of

an instruction. SR is initially cleared by SSRH LOAD IR L. The ONE AUTOED flip-flop is also cleared. The
general register RS address is available at the GRAC GRA (2:0) inputs. The constant 2 is provided by DAPD
KOMX 01 B L, and because the calculation is an increment, the 2’s complement of the constant is selected.
Therefore, the information that is clocked into byte 0 of SR1 at time TS is shown in Figure 3-7a. Further as-

sume that general register R4 is autoincremented by 4 in the destination calculation of the instruction. The
ONE AUTOED flip-flop is set when clock pulse SSRK PULSE 51 H occurs to provide SSRF CLK BYTE 1 H.
Byte 1 of SR1 will be loaded as shown in Figure 3-7b at that time.

gf an error occurs between the time one instruction is loaded (RACA UIRK H) and the time the next instruction
is loaded or an interrupt is processed (BRK.30), SR1 has the general register modification information required
to recover from the error. This information is available to the software recovery service routine.

Once the instruction is complete, no error has been detected, and an interrupt is being serviced, SSRA BRK.30 L
and SSRC NO ERROR (1) H clear SR1 and the ONE AUTOED flip-flop. Any stack modification that occurs
from that point until the next instruction fetch is recorded. There will be no need to restart the instruction,

even if segmentation faults are detected before the next instruction fetch. Instead, the trap sequence has to be
emulated to completion to recover and restart.
3.13

STATUS REGISTER 2 (SR2)

SR?2 consists of three 74174 D-type flip-flops (drawing SSRH). It is loaded with the 16-bit virtual address SAPH

VA (15:00) B H at the start of each instruction fetch. Under these conditions, it stores the virtual address of
each current instruction. It can also be loaded with the trap vector at the beginning of an interrupt or “T”’ bit,
Parity, Odd Address, and Timeout traps. The clock input, SSRH NEW SEQUENCE CLK H, is produced by

RACA UIRK H or the BRK.30 (0) L signal decoded at the KT11-C, CD ROM output.

NOTE

SR2 is read only; it cannot be written into.

3-24

e BYTEQO ———

8 | 7

SR1

3|2

-2

0. AUTO-DECREMENT R5 BY 2, SOURCE CALCULATION

——————BYTE 1 ————

1| 10

sktlo

o1t

of1t

3|2
1t

o]t

-2

b. AUTO- INCREMENT R4 BY 4, DESTINATION CALCULATION
11-1035

Figure 3-7

3.14

Examples of SR1 Loading

INTERNAL DATA BUS MULTIPLEXERS

The internal data bus multiplexers are made up of eight 74153 Multiplexers, shown on drawing SSRJ. The multiplexers are capable of selecting the contents of one of four registers as the 16-bit output to the processor internal

data bus. The inputs are the APR, SRO, SR1, or SR2. The APR can be either the PAR or the PDR, depending
upon the input selected by the PAR/PDR read multiplexer (Paragraph 3.7).
The specific register selected is determined by decoding virtual address bits BAMX (02:01), the SSR REG flip-

flop, and SSRL APR REG L. The input selection logic decodes this information as indicated in the following
chart:

SSRH BAMX

Input

SSRL SSR REG (1)H | SSRL APR REG

. 1::“"{‘;’)“ ze]';’c“’(‘)l ‘:‘S t

A: SRO(15:00)H
B:

SRI (15:00)H

SR2 (15:00)H

D: APR (15:00)H

1 indicates assertion, 0 indicates non-assertion, * indicates irrelevant.

The multiplexers are enabled when TMCE C1 H is asserted by the processor, provided that an internal register is

addressed and the TMCF GET OFF H input is not asserted. At this time, data in the addressed register is available on the processor internal data bus lines, INT BUS DATA (15:00) H. The TMCF GET OFF input is only asserted for floating-point processor or switch register operations that use the same processor internal data bus lines.

3-25

3.15

KT11-C,CD MEMORY MANAGEMENT TIMING

Timing for the KT11-C, CD option is derived from KB11-A and KB11-D Central Processor time states TIGD TS
(5:2) H (drawing SSRK). The processor time state inputs are not fixed but vary in length depending on the type
of cycle through which the processor is progressing. Sample timing for the Bust and Pause memory cycles is shown
in Figure 3-8. Note the memory management delay indicated on the diagram. The TIG module is normally

jumpered to provide three time periods of delay. This is adequate for the KT11-C, CD logic to complete its func-

tions and allow the processor to continue through the Bust cycle.
3.15.1

Event Times Related to Memory Cycles

Table 3-5 is a chart that shows how the KT11-C events relate to the KB11-A memory cycles and time states. The
KT11-CD events relate to the KB11-D similarly. The heavy lines indicate that an event occurs over an extended
period of time. For example, the INT REG flip-flop remains cleared over the first half of T1. An asterisk indi-

cates the possibility of an event if conditions other than timing are met. For example, if the BRK.30 microstate
is decoded or the UIRK field of the current processor microstate is set to 1, SR1 will be cleared through the
remainder of the memory cycle. The chart includes drawing references, indicating where the associated timing
logic is on the block schematics.

3.15.2

Address Relocation Timing

Figure 3-9 is a simplified diagram that shows the timing of the events that occur during page address relocation.
The sequence of events is indicated by the numbered text boxes. Maximum time lapse for an event to occur is
related to the leading edge of processor time state T1. Statements within rectangles apply to address relocation

when the KT11-C, CD is enabled, and a 16-bit virtual address is converted to an 18-bit physical address. Statements within ovals apply when the KT11-C, CD is disabled (SRO bit 00 = 0), and the 16-bit virtual address is
passed through the KT11-C, CD without change.

3.15.3

Internal Register Access Timing

Figure 3-10 is a simplified diagram that shows the sequence of operations involved in a typical internal register

access. The specific conditions assumed for this example are stated in the notes. Note that as soon as the KPAR
contents are added to the virtual address and the resultant UPAR physical address is decoded, the D input of the
User PAR flip-flop goes high. It is clocked at T5 of the Bust cycle, and SSRL INT REG FAST L is asserted.

That signal de-selects the KPAR as shown. It is also sent to the processor in acknowledgement of a Fastbus address. All the KT11-C, CD internal registers are Fastbus device addresses. Therefore, the KB11-A, D proceeds
through a Fastbus memory cycle, not a Unibus cycle.

For a read (DATI) operation, the contents of the selected UPAR will be gated to the processor internal data bus
(statements 8R and 9R on Figure 3-10). For a write (DATO) operation, the data from the processor BR will be
written into the selected UPAR at T4 of the Pause cycle (statements 8W and 9W on Figure 3-10).
3.16

INTERNAL REGISTER CONTROL

The internal register address decode and control logic is shown on drawing SSRL.

3-26

r‘l..rl__rlrwrlrfljlfll—lmmr“
MEM. MGMT. DELAY-q
3 TIME PERIODS

TIGD TS2L
TIGD TS3 L

TIGD TS5 L

SSRK PULSE 23 H

SSRK PULSE 34

UNIBUY

(«— PAUS

|
|

TIGD TS4 L

/-FASTBUS PAUSE

5 1

m
))
R

|
B

"
1

{(

(

BRL

IS"

.,
)}

SSRK PULSE 45 H
51

SSRK

PULSE

SSRK

PULSE BC34 H

SSRK

PULSE BC45 H

SSRK

PULSE

S5RK

PULSE BC910 H

H
BC89

SSRL INT CLR L

SSRL INT CLK L

SSRL SEG FAST CLK H
SAPA I SPACE CLK L

SAPA WRITE LOBYTE KPAR L

(OR WRITE INTO ANY SELECTED APR)

SSRC CLK SRO HI B L

SRO CLOCK

SSRE SRO LO B CLK L

SRO CLOCK

SSRH NEW SEQUENCE CLK H

SR2 CLOCK

s&%gesvsA LA"ng CONTROL

r
|

//7///////

e—
NOTES:

4 time periods. However, 3is
3. and
% TIG jumpers can provide for delays of 2,
recommended.

33 Pause only if Slave Sync is not yet received during a Unibus Cycle.

BUST CYCLE

|
|

~( (

”IF

((

)

| (0'

ole

”X\\\\\\\

PAUSE CYCLE

*** Pause only if Memory Sync is not yet received during a Fastbus Cycle. With bipolar
memory, this pause may not occur. With MOS memory, this pause will be at least 180
11-3960

ns.

Figure 3-8

KT11-C, CD Timing Diagram
3-27

w sIaS4N0ov1dPU],aq6i1s|od>{pyouapryayjupsupouaMdapuodnsuoyipuodJayoouoy*Bujw&iyA0D oINI938ANV9351SV4$,d44

9) Pk|[2V10SBS4SMVsdp9yoSq,8o0judiDo)NYSHe)Ly 3D|¥p|0y-L Dpy|S| josuo)21607Buiwy]

NdD awi)

s
n
y
o
y
g
s
o
y
s
1
6
a
y
10 A¥AlLl s.4(adv.s) L¥01.S30H[30D (LYHS3S) AP0« .P(oPo4T024D3PDS0>),ILLIIN=NDIAOOV3Dd4WWdSO3O,*YY(5*9,'1(¥4T€S€YS)*SS5+i),(d4Qd4Y[S**R(()VoVUI]SSD))
J(Ix3aN)| 1GLl s,-¥vvddv4s0)*$,4Ad &#20[D A(HYS) oEL 20DONYOU¥I*(D¥S)

0NuEg"1Psne

€l

LSNI 0¥S|

£l D30,|201D
(WHS )

1(¥4S¥S) £(4NSdVS)

d1qeL §-€

MOH01¥LSYD[SHUSAT9IES[OY03[-1AIOWIWSOP£A4SD IS,D4Vdd*S(gS¥,S.4S4)*(oVdDVS)150@DPupwAIXDVHdS.

(4¥59)%

(34S )

—

Lfl/\

8s6E-L

SulS+i1

sug+il

1Vv0N

|
° viSYL

aNVv
-]

XWVE)(<10:0 > N3HM

£V
—qdH YOXWYE 8Yda

—©

€

a3s

s+u1bil

3-29

‘310N

YOStL

)

N~ uvdn035v1d
on AdoRaN

40 SNINN1938

¥343y

MOS3ID0MdS1M§9XWYE<€h:SI>Q3193132dVS69351nd :V.,EM3 I1 vivasna
B

Q431930.135

1o Auonaw

g_o 0 30230 ]4 Q3193135 SININOD

H1SN830WL

vis LNOWOY L H

H3snN 1ys

/_0oav

c —

Q INI sna

3+8+vdVS Hd<9v0:Ldb>

1LS6€-

3-30

LH7913O04N13AVL0I58Sd 9W14vsoSvL135V3y

9L43NS4I <X1W0:V€08> $S3¥Y0QV

B73YINSU3N

3.16.1

PAR/PDR Decode and Control

On drawing SSRL, each address is decoded to determine whether one of the six PAR/PDR sets is being addressed.
The address ranges of User, Supervisor, and Kernel PAR/PDR sets are tabulated on the drawing. Physical
address

bits PA 17:06) H and virtual address bits VA (05:00) H are decoded to detect any address within these ranges.
A control flip-flop is associated with each group (PAR or PDR of User, Supervisor, or Kernel mode). These flip-

flops are cleared at T1 of each Bust cycle, when a new address is put on the lines. Time is allowed for decoding.
Then, at TS of the Bust cycle, the flip-flops are clocked. If an internal PAR or PDR is addressed, the output of
the associated flip-flop is used to condition the CS (Chip Select) inputs to that specific APR set (drawings SAPA

through SAPF).

3.16.2
3.16.2.1

SSR Decode and Control
SSR REG — The D input to the SSR REG flip-flop is qualified only by addresses 777572 (SRO),

777574 (SR1), or 777576 (SR2). When one of these registers is addressed during a Bust cycle, SSR REG
is set
at TS. If the bus transaction is a DATO or DATOB, TMCE C1 H is asserted. Asa result, SSRL WRITE SRO
REG H is asserted to allow data to be written into SRO under program control. SSR REG is cleared at T1
of the
next Bust cycle, after the data has been written.

3.16.2.2

INT SR3 — The SR3 address (772516) is decoded on SSRL. When SR3 is addressed, INT SR3 is set

(drawing SAPN). SSRL INT SR3 (1) H allows data to be clocked into SR3. SSRL READ SR3 H is
asserted if

the transaction is DATI or DATIP to gate the contents of SR3 onto the processor internal data bus.
3.16.3

Internal Register Fast Decode

All of the internal register addresses decoded on drawing SSRL are ORed to provide SSRL INT REG FAST L.

If any internal register is addressed, that signal is available at T5 of the Bust cycle. It is used to provide the
correct APR address (Paragraph 3.3.1.2).
At the same time, the inputs to the internal register control flip-flops are ORed to provide SSRL INT

REG ADRS.

Thus, if any internal register address is decoded, KT11-C FAST is set at TS of the Bust cycle. SSRL KT11-C
FAST (1) L is sent to the CPU to indicate that a Fastbus device has acknowledged the address.

3-31

CHAPTER 4

INSTALLATION AND MAINTENANCE

4.1

INSTALLATION

When the ‘KTl 1-C, CD is included as part of the initial PDP-11/45, 11/50, or 11/55 system, the SSR module
(M8108 for the KT11-C or M8108-YA for the KT11-CD) and the SAP module (M8107) are installed prior to
shipment. If the KT11-C, CD option is added to an existing system, the installation procedure is as follows:
1.

Turn switched power off at the console by shutting off both circuit breakers on the power supplies.

Install SSR Module (M8108 for KT11-C or M8108-YA for KT11-CD) in slot 13 of the CPU backplane
assembly.

Install SAP Module (M8107) 1n slot 14 of the CPU backplane assembly.
NOTE

SAP Module (M8107) replaces the SJB Module (M8116), which is
located in slot 14 when the KT11-C, CD is not installed.

4.
5.

Tumn circuijc breakers on.
Measure the voltage at pin A13A2, which receives +5 Vdc from the H744 +5 V Regulator located in

slot C of the H7420 Power Supply. If voltage is not between +5.0 V and +5.1 V, adjust voltage a

required.
6.

‘

Runthe KT11-C, CD Memory Management Unit diagnostic programs listed below to verify that the
KT11-C, CD is operating properly.

4.2

DIAGNOSTICS

Table 4-1 lists the diagnostic programs for the KT11-C, CD Memory Management Unit option. If a fault is
suspected in the KT11-C, CD prior to running the diagnostics, the internal registers (status, page address, and
page description) should be checked at the console for proper operation. The addresses of the status registers
are:

SRO — 777572
SR1 — 777574
SR2 — 777576
SR3 — 772516
The addresses of the page address and page description registers are given in Table 2-1. Bits 12 through 15 of the
Page Address Registers are not used, and bits 4, 5, and 15 of the Page Description Registers are not used. Press the
DEP and EXAM switches for each of the registers.

Table 4-1

KT11-C, CD Memory Management Unit Diagnostic Programs

Number

Tests

MAINDEC-11-DCKTA-X

Basic Logic Test, Part 1

MAINDEC-11-DCKTB-X

Basic Logic Test, Part 2

MAINDEC-11-DCKTC-X

Access Keys Test

MAINDEC-11-DCKTD-X

Move to Previous I/D Space Test

MAINDEC-11-DCKTE-X

Move from Previous I/D Space Test

MAINDEC-11-DCKTF-X

Abort Tests

MAINDEC-11-DCKTG-X

Memory Management Exerciser

X denotes current software revision level.

DCKTA and DCKTB Basic Logic Tests One and Two — Tests the basic logic, including write into PAR and PDR,

and all status registers.
DCKTC Access Keys Test — Performs a test of all Access Control Field (ACF) keys to verify that each key provides the required results for valid and invalid access attempts.

DCKTD MTPD/I with Memory Management — Tests the MTPD and MTPI instructions with the KT11-C, CD
enabled. The instructions are executed in all combinations of current and previous mode conditions.

DCKTE MFPD/I with Memory Management — Tests the MFPD and MFPI instructions with the KT11-C, CD
enabled. The instructions are executed in all combinations of current and previous mode conditions.
DCKTF Memory Management Abort Tests — Tests the memory management abort errors. This diagnostic causes
an abort of each BUST of the KB11-A, D. Following the abort, the diagnostic checks for correct information in

the status registers and on the stack. The sequence of tests begins with Page 1 of the microflows and proceeds
from left to right.

DCKTG KT11-C, CD Exerciser — Exercises basic KT11-C, CD Memory Management Unit functions. In addition,
this diagnostic uses all available memory and will run many I/O devices simultaneously with KT11-C, CD tests.

4.3

TROUBLESHOOTING TEST PROCEDURES

The use of the W131 maintenance card and the W900 extender modules are described in the PDP-11/45, 11/50,

and 11/55 System Maintenance Manual, EK-11045-MM-007).

APPENDIX A

GLOSSARY

Term

Abort

Definition
A processor interrupt that can occur at any memory reference, not just
between instructions. The KT11-C, CD will cause an abort if an address attempts to access a non-resident address, to write into a read-only page, or

violates the length of a page. When the abort occurs, the KT11-C, CD logs
the page number causing the abort, the virtual address of the instruction
causing the abort, and any other information necessary to process the
abort.

A KT11-C, CD abort takes a new PC from Kernel D virtual address

250 and a new PS from 252. The old PS and PC are pushed on the stack
specified by the new PS bits (14:15).

Address Space

The set of addresses used during processing in a specific processor mode

(Kernel, Supervisor, User). The Virtual Address Space is that set of addresses authorized by the KT11-C, CD for a particular mode. The Physical
Address Space for the mode is the virtual address space as mapped into
physical addresses. In general, the Kernel, Supervisor, and User modes will

operate out of the same virtual address space but out of different physical
address spaces.
BEND

Acronym for Bus END — meaning that the bus cycle (read “memory”

cycle) in process is terminated. A BEND condition occurs when an anticipatory fetch turns out to be wrong or when some error condition is detected on the reference. When the BEND condition is detected in the
KT11-C, CD logic, no abort or memory management trap can occur on the

reference.
BUST

Acronym for BUs STart (read “memory cycle” start). The name of the
processor state that constitutes the first half of a memory cycle. The sec-

ond half of the memory cycle is designated PAUSE.

Internal Register

All Page Address Registers, Page Descriptor Registers, Status Registers O,
1, 2, and 3 are considered to be “internal registers”’.

Mode

The PDP-11/45, 50, and 55 have three modes of operation: Kernel, Supervisor, and User. The KT11-C, CD provides a separate set of PAR/PDR registers for use in each of these modes. The mode is specified by bits (15:14)

in the processor status (PS) word: 00 = Kernel, 01 = Supervisor, 11 = User.

Operating System

A collection of programs that provides facilities and service to a user by
allocating resources (CPU, memory, I/O) among several users. An operating
system is identical to a ““control” program, a “monitor’’ program, or

“supervisor’ program. The PDP-11/45, 50, and 55 are designed to run the
operating system in the Kernel and Supervisor modes.

A-1

Term

Definition

An abbreviation for “Physical Address”.

Page

A collection of continuous memory addresses. The KT11-C, CD divides
the 32K word processor address space into eight 4K sections called pages.
The lowest address in each page is a whole multiple of 4096. The length of
the page is some whole multiple of 32 through 128. Thus, a page may vary
in size from 32 to 4096 words, in 32 word increments, and begins on a

4096 word boundary.
PAR — Page Address Register

A register containing the “‘base address” or “relocation constant” associ-

ated with a page. The KT11-C, CD has 48 PARs, 16 associated with each

of the three processor modes (User, Supervisor, and Kernel).
Pause

The term used to describe the second half of a memory cycle. During the
Pause cycle, KT11-C, CD status registers are updated and the processor, if
necessary, pauses to wait for completion of the current memory cycle.

PDR — Page Descriptor Register

A register containing information associated with a page. This includes the

length of the page, the expansion direction, and the access key. The

KT11-C, CD has 48 PDRs, 16 associated with each of the three processor
modes (User, Supervisor, and Kernel).

Physical Address

The address generated by the KT11-C, CD that is used to select a specific
memory location. When the KT11-C, CD is operating, the “physical
address” is identical to the “relocated address”.

ROM — Read Only Memory

A hardware device that is able to store bit patterns that can be read by
providing a specific address. In the KT11-C, CD, four ROMs are used to

control modifications to status registers, detect exceptions, and separate
I space references from D space references.

An abbreviation for “Virtual Address”.

Virtual Address

The address generated by the PDP-11/45, 50, or 55 processor. The term
“virtual” is applied because the address will be relocated by the contents

of the PAR. The memory location reached will be the relocated address.
Hence, the processor “thinks” it is addressing one location but actually
gets another. The first address is then really a dummy or “‘virtual” address.

APPENDIX B

REFERENCE LITERATURE

The following list of references covers some of the more general aspects of memory management tasks of interest
to systems programmers. It is part of the recommended bibliography of the National Academy of Engineering
for its course outline on ‘‘Operating System Principles”.
The following abbreviations are used in the bibliography.

ACM

Association for Computing Machinery

IEEE

Institute for Electrical and Electronics Engineers

IEEETC

IEEE Transactions on Computers

CACM

Communications of the ACM

JACM

Journal of the ACM

Computing Surveys (ACM)
Fall Joint Computer Conference

FICC
SICC

Spring Joint Computer Conference

2SOSP

Second Symposium on Operating Systems Principles (proceedings available from ACM,
1133 Avenue of Americas, New York, N.Y. 10036)

Abate, J., and Dubner, H. Optimizing the Performance of a Drum-Like Storage. IEEE Trans. C-18,
11 (Nov. 1969), 992—-997).

Belady, L.A. A Study of Replacement Algorithms for Virtual Storage Computers. IBM Sys. J. 5, 2 (1966),
78—101.

Bensoussan, A., Clingen, C.T., and Daley, R.C. The Multics Virtual Memory. Proc. 2SOSP (Oct. 1969).
Denning, P.J. The Working Set Model for Program Behavior. Comm. ACM 11, 5 (May 1968), 323-333.
Denning, P.J. Thrashing: Its Causes and Prevention. AFIPS Conf. Proc. 33 (1968 FJCC), 915-922.
Denning, P.J. Virtual Memory. CS 2, 3 (Sept. 1970), 153—189.

Dennis, J.B. Segmentation and the Design of Multiprogrammed Computer Systems. JACM 12, 4 (Oct. 1965),
589-602.

Kilburn, T. et al. One-Level Storage System. IRE Trans. EC-11, 2 (Apr. 1962), 223-235.
Knuth, D.E. The Art of Computer Programming (Vol. 1). Addison-Wesley (1968), Ch. 2.
Mattson, R.L., Gecsei, J., Slutz, D.R., and Traiger, [.L. Evaluation Techniques for Storage Hierarchies.
IBM Sys. J. 9,2 (1970), 78—117.

Randell, B., and Keuhner, C.J. Dynamic Storage Allocation Systems. Comm. ACM 11, 5 (May 1968), 197-305.

Sayre, D. Is Automatic Folding of Programs Efficient Enough to Displace Manual? CACM 12, 12 (Dec. 1969),
656—660.

Wilkes, M.V. Slave Memories and Dynamic Storage Allocation. IEEE Trans. EC-14 (Apr. 1965), 270-271.
Wilkes, M.V. Time-Sharing Computer Systems. Am. Elsevier (1968).

B-1

APPENDIX C

IC DESCRIPTIONS

The following ICs are described in this appendix. The S or H version of an IC listed below, merely indicates high

speed.

7442

BCD to Decimal Decoder

7474

Dual D-Flip-Flops

74153 Dual 4-Line to 1-Line Multiplexer

74157 Quad 2-Line to 1-Line Multiplexer
74174 Hex D Flip-Flop Register
74175 Quad D Flip-Flops
74187

1024-Bit Read Only Memory

7442 BCD to Decimal Decoder

fg jo)
g

o0
9

f7 p—
12

fe P—

fso—

7442

DECIMAL

) OUTPUT

BCD
INPUT

14
—

fz P—
D1

f2
f1q

a
1

Vee = PIN 16
GND = PIN O8
1C-7442

7442
TRUTH TABLE

Decimal

BCD

Output

Input

C-2

7474 Dual D-Flip-Flops

STANDARD CONFIGURATION

REDIFINED CONFIGURATION

PRESET

604 05
02

601

——

1 006

1 c05

7474

7474
—c

06
——

o—

—C

Yo1

lf0;5)

Yoa

CLEAR

PRESET
&10

PRESET
4)13
09

o—

1[os
108

290

7474

1fos9..

7474
09

110

113

CLEAR

IC-7474

Vee= PIN 14

GND=PIN O7

TRUTH TABLE FOR

7474 STANDARD CONFIGURATION
(EACH FLIP-FLOP)

tnh

th+1

Preset

Clear

D laput

1 Side

0 Side

Pin 4(10)

Pin 1(13)

Pin 2(12)

Pin5

Pin 6

High

Low

High

Low

High

Low

High

Low

High

Low

High

th = bit time before clock pulse.
th+1 = bit time after clock pulse.
X = irrelevant

74153 Dual 4-Line to 1-Line Multiplexer

ADDRESS

INPUTS

DATA INPUTS

STROBE

OUTPUT

STB

Address inputs SO and S1 are common to both sections.

H = high level, L = low level, X = irrelevant.

_13_. DI

co
fo

74153

|07

f1L.09_
11

74153

|02

l14

STBO

TO1

VCC= PIN16
GND= PINOS8

|02

|14

STBi1

T15
IC-74153

74157 Quad 2-Line to 1-Line Multiplexer

TRUTH TABLE
INPUT

OUTPUTS

tn + 1

R(1)R(O)

H
L

L
H

th =Bit time before

clock pulse.

tnt1=Bit time after

clock pulse.

[REPA

N
AL
14

R3(0) |~

2212
1

DATA J

R2(0) P

INPUTS

74175

'S—Dl
4

R1(1)"7—
R1(0) &

(1)

OUTPUTS

Rro(n}E
Dio

Rou»-é—J
CLR

(5)
(1)
R1
CLK (0)

CLK

CLEAR

p2 o2

(1)
R2

CLK (0)
CLEAR

D3 o3
(9)

CLOCK o—r

)

r_—\__/

)

CLEAR ofl—-C{>O—L l

(1)
R3

O CLK (0)}—>
CLEAR

]

Pin (16)=Vcc, Pin (8)=GND
IC-74175

74174 Hex D Flip-Flop Register

(3)

TRUTH TABLE
INPUT

(2)

Do°

[OUTPUT

th+1

R(1)

—
oRO(1)
—
olcLock
CLEAR

__J

tn = Bit time before

clock pulse.

D1 cg)

—(2)0R1 (1)

th+1=Bit time after

clock pulse.

——D5

R5(1)

13 Ipa

Ra (1) 2

—D3

R3(1)

74174

CLEAR

i Py

R (1) ——

CLR

D2 o8

R2(1) }—
5

4»————?

—1D2
.

—— Do

—QeLock

L (T r2(1)
—QICLOCK
CLEAR

RO(1) }—

CLK

p3 &

]

100,
o3 1)
Q| CLOCK
CLEAR

L
D4 c(ls)

flg—)O R4 (1)
acLock
CLEAR

LT
14

(15)

D5 cr( )
(9)

CLOCK 0—

)

[——

CLEAR i1

—0o R5(1)
deLocx
CLEAR

| T

Pin (16)= Ve, Pin (8)= GND
1C-74174

C-6

74175 Quad D Flip-Flops

INPUTS

STB | SO

OUTPUT

f
L

H = high level, L = low level, X = irrelevant.

312

|4,

05 fa

74157

STB

0
STB

T15

|01

VCC:=P
GND=P

f0
O -

2|22

IC-74157

C-7

74187 1024-Bit Read-Only Memory
The 74187 is a custom-programmed, 1024-b it read-onl

TTL memory array is addressed in straight 8 -bit binary

y memory organized as 256 words of 4 bits each. This
with full decoding. Two overriding memory enable

inputs are provided which, when taken high, will inhibit

the function causing all four outputs to remain high.

1024

(a7

81T MEMORY CELL

115)

A6 ——p

"
1

AS (2)

1 OF 32
DECODER

32 BY 32
MEMORY MATRIX

A43——>
(3)

BINARY%
SELECT

A3Tfl

A2(7)

10F8:10F8:10F8

2; (6)
\

MEMORY
ENABLE

DECODER

1 OF 8

DECODER

(5)

ENB1M)
) ENB3

(13)

(9)

(10)

(11

OUTPUTS

74187

M3(1) p—22
10
M2(1) p—2—

.,
M1(1)

o—

Mo(1) po—2——

ENB1

ENBO

T‘M

T13

VCC=PIN 16
GND
= PIN 08
IC-74187

INDEX

A (Attention) Bit
for gathering statistics, 2.4.5
logic, 3.3.2.4
purpose, 2.1.3

Base Address, 2.1.1
Block Number, 2.2.2.5
Bus Pause Timing, F3-8

Abort
control sequence, F3-4

decode logic, 3.6.1

flags, format, 2.3.1
flags, logic, 3.11.1
mechanism, 2.1.4
processing, 2.4.8.1
recovery, F2-15

Communication Between Programs, 2.4.4
Console
operation with KT11-C, CD, 2.4.1.1

mode control, 3.5.2

Access Control Field

ACF, 2.1.2.1

detailed functions, 2.2.2.1
keys, T2-2

Destination Mode
control logic, 3.11.4

ACF Keys

definitions, T2-2
statistics gathering aids, 2.1.3, 2.4.5

Address
assignments, 2.2

display, 3.5.1, F3-4

drivers, 3.8

PAR/PDR assignments, T2-1

purpose of bit, 2.3.1.7

Dynamic Memory Allocation, 2.2.2.5

D Space
control logic, 3.10.7

PDR, 2.1.2.2
use of, 2.4.6

enable D space, 2.3.4

path, 3.2.1

physical, F2-3

relocation, 2.1.1
relocation sequence, F3-9
selection switch, 2.4

virtual, 1.3.2

Execute-Only Protection, 1.3.1, 2.1.2.2

Expansion Direction, 2.2.2.2

downward, F2-9
Active Page Registers, F2-5

upward, F2-8

Attention

memory, 1.3.3

A bit, 2.2.2.4
ATTN flip-flop, 3.3.2.4

Autodecrement/Autoincrement, 3.10.2.4,3.12.2

Fast Decode, Internal Registers, 3.16.3
Fastbus, 3.1

INDEX (Cont)

Fault Detection Logic, 3.5
Fault Recovery, F2-15

Memory Expansion, 1.3.3

Memory Protection, 2.1.2, 2.4.3

Memory Management
General Registers

enable, 2.3.1.6

address logic, 3.12.1

ROM, 3.10

status, 2.3.2

statistics, 2.1.3
status registers, 2.3

trap logic, 3.11.2

I/D space

bit of SRO, 2.3.1.9
control by SR3, 2.3.4

control logic, 3.10.7

KT11-C, CD capability, 1.3.5 °
limitations, 2.4.6

Non-Reentrant Programs, 2.1.2.2
Non-Resident

page fault, 3.6.1
protection, 2.1.2.1

Instruction Complete, 2.3.18
bit use, 2.4.10
Interface, hardware, F3-1
Internal Registers
access timing, F3-10

control logic, 3.16

fast decode, 3.16.3
inhibit, 3.6.2

SRO, SR1, SR2, and SR3, 2.3
Internal Data Bus, 3.14

PAR/PDR, 2-5
addresses, T2-1

description, 3.3

multiplexers, 3.7

selection, 3.3.3.1
Page Address Field (PAF), 2.1.1

format, F2-6
logic, 3.3.1

Page Address Register (PAR), 2.1.1
address assignments, T2-1
Kernel Space

address assignments, T2-1

control logic, 3.10.4
general, 1.3.7

SRO mode field, 3.11.6

contents, 2.2

format, F2-6
logic, 3.3.1

Page Descriptor Register (PDR)

address assignments, T2-1
contents, 2.2
format, F2-7
logic, 3.3.2

INDEX (Cont)

Page

- ROM

expansion, 2.2.2.2

organization, 3.10.1

fault recovery, F2-15

output decode, T3-3

length, 1.3.1, T1-1

variable length, 1.3.4
Page Number, 3.11.8
Physical Address

construction, F2-3
determination, 2.4.2
display, T2-3
overlapping, 2.4.4.1

no. virtual address, 1.3.2
Power Requirements, T1-1
Processor Status Word, 2.1.2.3

modification, 2.4.8
Protection

kernel mode, 2.4.7.1
memory, 1.3.1
PS Restore, 3.10.2.1

PSW Bits, Current Mode, 2.1.2.4

SAP Module M8107

functions, F3-2

installation, 4.1
location, T1-1

SSR Module (M8108inthe KT11-C,M8108-YAin the KT11-CD)
functions, F3-2

installation, 4.1
location, T1-1

Stack

communication, 2.4.4.2
downward expandable page, 2.2.2.5
no program, 1.3.8

Statistics

gathering routine, 2.4.5
memory management, 2.1.3
Status Registers

format
SRO, 2.3.1
SR1, 2.3.2

Read-Only

SR2,2.3.3

fault logic, 3.6.1.2
protection, 2.1.2.1

Read-Only Memory (ROM), 3.10.1
Recovery

from abort, 2.4.10

from 1/O lockout, 2.4.7.2
routine, flow chart, F2-15

Reentrant Programs, 2.1.2.2
Relocation

address relocation, 2.1.1

block diagrams, F2-1, F2-2
definition, 1.3.2
logic, 3.4

timing, F3-9

SR3,2.3.4
logic
SRO, 3.11

SR1, 3.12
SR2, 3.13
SR3, 3.9
Supervisor Space

address assignments, T2-1
control logic, 3.10.5

general, 1.3.7

SRO mode field, 3.11.6
Swapping, 2.1.3

INDEX (Cont)

User Space

address assignments, T2-1
T-Bit, 2.3.3

control logic, 3.10.6

SR2 logic, 3.13

general, 1.3.7

SRO mode field, 3.11.7

Timing

diagram, F3-8
event times; KT11-C, T3-5
Trap
coatrol logic, 3.11.2

Virtual Address
display, T2-3

control sequence, F3-5

inverters, 3.4.1

decode logic, 3.6.3

page numbers, 2.2

flag format, 2.3.1.4

program counter, 2.3.3

memory management, 2.3.1.4

vs physical addresses, 1.3.2

vector addresses, 2.4.11

Trap/Abort
mechanism, 2.14
recovery, F2-15

W (Written Into) Bit

logic, 3.3.2.4

purpose, 2.1.3

written into, 2.2.2.2

Unibus

address drivers, F3-9

interface, F3-1

NOTE: T = Tables and F = Figures.

Reader’s Comments

KT11-C, CD MEMORY MANAGEMENT UNIT
MAINTENANCE MANUAL

EK-KT11C-MM-005

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of

our publications.

What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well
written, etc.? Is it easy to use?

CUT OUT ON DOTTED LINE

What features are most useful?

What faults do you find with the manual?

Does this manual satisfy the need you think it was intended to satisfy?

Does it satisfy your needs?

Why?

Would you please indicate any factual errors you have found.

Please describe your position.

Name —
Street

City

—

Organization

Department

’ :

State

Zip or Country

FIRST CLASS

PERMIT NO. 33
MAYNARD, MASS.

BUSINESS REPLY MAIL

NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES
Postage will be paid by:

Digital Equipment Corporation
Technical Documentation Department
146 Main Street

Maynard, Massachusetts 01754

BEe

cliigliltlall
i

Printed in U.S.A.