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EK-KE44A-TM-001

May 1981

150 pages

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Document:	KE44-A CISP Technical Manual
Order Number:	EK-KE44A-TM
Revision:	001
Pages:	150
Original Filename:	EK-KE44A-TM-001_KE44-A_CISP_Technical_Manual_1981.pdf

OCR Text

EK -KE44A-1M-OO 1

KE44-A CISP
Technical Manual·

Prepared by Educational Services
of
Digital Equipment Corporation

The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIG ITA L'5 DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation.
Maynard. Massachusetts:
DIGITAL
DEC
PDP
DECUS
UNIBUS

o ECsystem-l 0
DECSYSTEM-20
DIBOl
EDUSYSTEM
VAX
VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
lAS

CONTENTS
CHAPTER 1

INTRODUCTION

1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.3

PURPOSE AND SCOPE ......................................................................................
GENERAL DESCRIPTION ................................................................................
Commercial I nstruction Set............................... .............................................
Suspension (Interrupt)....................................................................................
The Microcode................................................................................................
Hardware Description..... ......... .......... ... .................. ....... .......... ...... .............. ...
RELATED HARDWARE MANUALS ...............................................................

CHAPTER 2

INTERFACING

2.1
2.2
2.3

GENERAL.............................................................................................................
INITIAL OPERATION ........................................................................................
MICROCODE GENERATION ...........................................................................

CHAPTER 3

EXTENDED INSTRUCTION DATA TYPES

3.1
3.1.1
3.1.2
3.1.3
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.3

CHARACTER DATA TyPES.............................................................................. 3-1
Character........................................................................................................ 3-1
Character String....... .............. ........... ................. ........... ....... .................. ........ 3-1
Character Set.................................................................................................. 3-2
DECIMAL STRING DATA TYPES ................................................................... 3-3
Common Properties .......... ....... .... ......................... ................ ....... ........ .... ....... 3-3
Decimal String Descriptors ............................................................................ 3-5
Packed Strings ............................................................... :................................ 3-6
Zoned Strings.................................................................................................. 3-8
Overpunch Strings.. ............. ..................... ...... ...... ................ .......... .......... ...... 3-9
Separate Strings.. ..... ........ ...... ................. ...... ......... .............. .............. ..... ........ 3-11
LONG INTEGER .................................................................................................. 3-14

CHAPTER 4

THEORY OF OPERATION

4.1
4.1.1
4.1.2
4.1.2.1
4.1.2.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5

290lA MICROPROCESSOR SLiCER................................................................ 4-1
2901ARAM ................................................................................................... 4-1
Arithmetic Logic Unit (ALU) ........................................................................ ·4-4
Logical and Arithmetic Functions............................... ................... ........ 4-5
Logical Functions for G, P, CN+4, and OVR........................................ 4-6
Q-Register....................................................................................................... 4-6
Bit Shifting. ................... ...... ............ .... ........................................................... 4-8
Status Bits....................................................................................................... 4-8
Carry Lookahead Logic................ .................................................................. 4-8
2901 A Pin Definitions .................................................................................... 4-8
INSTRUCTION SUSPENSION (INTERRUPT)............................................... 4-9
Steps Leading to Suspension .................... ......................... ........... .................. 4-9
Returning from Suspension ............................................................................ 4-9
DETAILED LOGIC DESCRIPTION .................................................................. 4-9
I R Decode....................................................................................................... 4-9
CPC Branching ............................................................................................... 4-11
MPC Addressing..................................................... ....................................... 4-12
Maintenance Switch ............................... ............. ............ .... ........... ................ 4-12
BCD Operation PROM .................................................................................. 4-12

Page

iii

1-1
1-1
1-1
1-1
1-1
1-2
1-2

2-1
2-3
2-3

4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.6.7
4.6.8
4.6.9
4.6.10
4.6.11

DETAILED BINARY DATA PATH ................................................................... 4-13
Direct Data (ALU-In) Multiplexer ................................................................ 4-13
Constants Generation for 2901A .................................................................... 4-13
Saving Constants Before Suspension (Interrupt) ............................................ 4-13
Restoring Constants After Suspension (Interrupt) ......................................... 4-13
2901 A Write Operations ................................................................................. 4-14
2901A Shift Operations .................................................................................. 4-14
Input Multiplexers .......................................................................................... 4-14
DETAILED BCD ALU DESCRIPTION ............................................................. 4-15
BCD "A" Register/BCD "B" Register .......................................................... 4-16
BCD Carry ...................................................................................................... 4-16
BCD Multiply ................................................................................................. 4-16
BCD ASCII Encoding .................................................................................... 4-16
BCD Sign Translation ..................................................................................... 4-16
DETAILED LOGIC DESCRIPTION OF STATUS BITS ................................. 4-17
Status Bits ....................................................................................................... 4-17
Nonzero Conditions ........................................................................................ 4-17
Carry / Borrow................................................................................................. 4-18
Sign Bits .......................................................................................................... 4-18
Address Odd Conditions................................................................................. 4-19
Status Bit Operation with BR Interrupt Pending ........................................... 4-19
Return from Interrupt .................................................................................... 4-19
Categorizing Instructions to Form N.Z,V,C Bits ..............................-..... ~ ...... 4-20
Arithmetic Condition Codes ........................................................................... 4-21
Condition Code Output................................................................................... 4-21
Character String Condition Codes .............. :.................................................. 4-21

CHAPTERS

MICROCODE

5.1
5.1.1
5.1.2
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.2.10
5.2: 11
5.2.12
5.2.13
5.2.14
5.2.15
5.2.16

INTRODUCTION.................................................................................................
Design Guideline ............................................................................................
Microcode Listing...........................................................................................
THE MICROWORD .............................................................................................
CPC Field (87:76) .........................................................................................
APORT Field (75:72) ....................................................................................
CISSPW Field (71:70) ..................................................................................
ALUCB Bit (69) ............................................................................................
BPORT Field (68:65) ....................................................................................
SHITIN Bit (64) ...........................................................................................
SHITC Field (63:62) ....................................................................................
ALUDST Field (61:59) .................................................................................
ALUFTN Field (58:56) .................................................................................
ALUSRC Field (55:53) .................................................................................
SALUI Bit (52) .................................................................................. "-..........
INEN Bit (51) ...............................................................................................
SWAP Field (50:49) ......................................................................................
ENIB Bit (48) ................................................................................................
ENOB Bit (47) ..............................................................................................
LBYTE Bit (46).............................................................................................

5-1
5-1
5-1
5-1
5-3
5-3
5-3
5-3
5-3
5-3
5-3
5-3
5-3
5-3
5-3
5-4
5·4
5-4
5-4
5-4

5.2.17
5.2.18
5.2.19
5.2.20
5.2.21
5.2.22
5.2.23
5.2.24
5.2.25
5.2.26
5.2.27
5.2.28
5.2.29
5.2.30
5.2.31
5.2.32
5.3
5.3.1
5.3.2
5.3.3
5.4

CONI Field (45:41) ...................................................................................... 5-4
CONST Field (40:38) ................................................................ 4................... 5-4
ENSNIN Bit (37}.......................................................................................... 5-4
ENSNOU Bit (36) ........................................................................................ 5-4
BMUX Field (35:34) ..................................................................................... 5-4
BCDOP Field (33:32) .................................................................................... 5-4
BCDMX3 Field (31 :30) ................................................................................. 5-5
BCDMXl Field (29:28) ................................................................................ 5-5
CON2 Field (27:25) ...................................................................................... 5-5
CON3 Field (24:21) ...................................................................................... 5-5
CON4 Field (20:16) ...................................................................................... 5-5
MPC Field (15:10)......................................................................................... 5-5
CONBR2 Field (9:6) ..................................................................................... 5-5
CONBRI Field (5:2) ..................................................................................... 5-5
ENCIS Bit (1) ............................................................................................... 5-5
ENCB Bit (O) ................................................................................................. 5-5
READING THE MICROCODE .......................................................................... 5-5
The Field Definitions ................................ .................. .................................... 5-6
The Microinstruction. ...... ........ .............. ....... .................................. ................ 5-7
Reading the Macrodefinitions ... .............. ....... ................. ......... ...................... 5-7
THE CIS MICROCODE INSTRUCTIONS ....................................................... 5-10

CHAPTER 6

INSTALLATION AND CHECKOUT

6.1

6.2

INSTALLATION ........................................................................... .......................
CHECKOUT ..........................................................................................................

CHAPTER 7

MAINTENANCE

7.1
7.2
7.2.1
7.2.2
7.2.2.1
7.2.2.2
7.2.2.3
7:2.3
7.2.4
7.2.5
7.3

GENERAL.............................................................................................................
KE44-A DIAGNOSTICS ......................................................................................
CZKEEA Program Abstract... ........ ...... ................................. ........................
Program Starting Procedure.................... ................................... ....................
Starting Address 200..............................................................................
Starting Address 204..............................................................................
Starting Address 210..............................................................................
Error Information ...........................................................................................
Program Options.............. ...............................................................................
Program Execution Times ..............................................................................
ASCII PROGRAMMER CONSOLE...................................................................

APPENDIX A

EXTENDED-INSTRUcrION DEFINITIONS

APPENDIXB

CIS MPC FUNCTIONS

APPENDIX C

CIS ABBREVIATIONS

APPENDIX D

CISP MNEMONICS

6-1
6-2

7-1
7-1
7-1
7-1
7-1
7-3
7-3
7-4
7-4
7-4
7-5

FIGURES
Figure No.
2-1
4-1
4-2
4-3
4-4
4-5
4-6

5-1
5-2
5-3
5-4

6-1
6-2

Title

Page

KE44-A/CPU Interface Lines................................................................................ 2-1
KE44-A Block Diagram.......................................................................................... 4-2
2901 A Detailed Block Diagram ......... ...... ................................................ ..... .......... 4-3
AM290lA Pin Connections .................................................................................... 4-8
MPC Timing ....... ..... .... ............................. ....................... ...... ...... ......... .......... ........ 4-10
2901 A Shift Operations .......... ............... ... ..... ........................ ............... ..... .......... ... 4-15
CIS Status Word..................................................................................................... 4-17
CIS Microword Field Map. ............................ ........................................ ................ 5-2
Sample Page of Microcode Field Definitions ................................. ... ...... .... ........... 5-6
Sample Page of Microinstructions .......................................................................... 5-8
Sample Page of Macrodefinitions ........................................................................... 5-9
Module Placement in Processor Backplane. ....... .......... ....... ....... .... .... .... ........... ..... 6-1
KE44-A Data Path/Logic Module, M7092............................................................ 6-2

TABLES
Table No.
2-1
4-1
4-2
4-3
4-4

4-5
4-6
4-7
4-8
4-9

Title

Pale

KE44-A/CPU Interface Line Definitions .............................................................. 2-2
Microcode Matrix for Source Operands and ALU Functions ................................ 4-4
ALU Logic Mode Functions ................................................................................... 4-5
ALU Arithmetic Mode Functions .......................................................................... 4-6
P, 0, CN+4, and OVR Functions ........................................................................... 4-7
CPC Bits Affected by Branching Conditions .......................................................... 4-11
BCD ALU Operations ............................................................................................ 4-12
Sign Coding............ ...... ............ ............ ................................... ................ .... ............ 4-19
Instruction Categories ............................................................................................. 4-20
Condition Code Settings .................................................................................. ....... 4-22

CHAPTER 1
INTRODUCTION

1.1 PURPOSE AND SCOPE
This manual provides the data necessary for the installation and operation of the KE44-A Commercial
Instruction Set Processor (CISP) option to the KDII-Z Central Processing Unit (CPU). The KE44-A
option significantly extends the capability of the PDP-l 1/44 computer in the area of commercial data
processing. The KE44-A option is installed in the PDP-ll/44 cabinet.
CIS-specific abbreviations used in this manual are listed in Appendix C. Appendix D lists the CIS
microword mnemonics.
1.2 GENERAL DESCRIPTION
1.2.1 Commercial Instruction Set
The CIS is a series of instructions for manipulating byte strings in order to provide improved COBOL
performance, text editing and word processing capability. The instruction set includes instructions for
character handling and decimal string operations. Each of these instructions has two forms: register and
in-line.
In the register form descriptors are loaded into the general registers before the instruction is performed.
With the in-line form, descriptors are accessed by descriptor address pointers. The CIS also includes
"load two" and "load three" descriptor instructions that augment the register form. The op code for all
CIS instruction is 076 nnn.
1.2.2 Suspension (Interrupt)
Since CIS instruction times may be long (due to large operands), a method is provided for giving system devices interrupt access to the processor. Thus, during CIS instructions, a test is made at specific
points in the microcode for Bus Request (BR) interrupts. If an interrupt is detected, the CIS instruction
is automatically interrupted, "suspended", on a BR priority basis. During suspension, the CIS instruction is stopped and control is returned to the KD ll-Z. The interrupt routine will then run, executing one
or more new CIS instructions during the period of suspension. At the end of this interrupt routine, control is returned to the KE44-A for completion of the suspended instructions. The entry point (microword address) for the suspended instruction is the same as the initial entry point. The control store
contains a service interrupt save-state routine and a restore-from-service- interrupt routine.
1.2.3 The Microcode
The CIS instructions are implemented in microcode. The KE44-A microstore comprises 1,000 88-bit
words. When a valid op code is received, the starting microstore address is entered and the instruction is
performed. All of the microwords necessary to perform the op code specified operation are sequenced
through. Each 88-bit microword is subdivided into 32 fields. The CIS program counter (CPC) field
<87:76) of each microword is coded with the address of the next microword.

1-1

1.2.4 Hardware Description
The main hardware elements of the KE44-A are a control store module and a data path module. The
control store is a quad-height (M709I) board that contains the microcode in ROM form. The operational logic is on a hex-height (M7092) board that contains four basic sections.
1.

Instruction Register (lR) Decode, CIS Program Counter (PC) and Microprocessor Code
(MPC) Addressing logic

Binary data path logic

Decimal data path logic

Status Information and Condition Code Generation logic

These sections are described in detail in Chapter 4.
1.3 RELATED HARDWARE MANUALS
The following hardware manuals are related to the KE44-A and may be purchased from Digital Equipment Corporation.

Title

Document
Number

Availability

PDP-I 1/44 CP Subsystem
Technical Manual

EK-KDIIZ-TM

Hardcopy and
Microfiche

PDP-l 1/44 System User's
Guide

EK-II044-UG

Hardcopy

FPII-F Floating-Point
Technical Manual

EK-FPII F-TM

Hardcopy and
Microfiche

All purchase orders for hardware manuals should be forwarded to:
Digital Equipment Corporation
Accessory and Supplies Group (P086)
Cotton Road
Nashua, NH 03060
Purchase orders must show shipping and billing addresses and state whether a partial shipment will be
accepted.
All correspondence and invoicing inquiries should be directed to the above address.
For information concerning microfiche libraries, contact:
Digital Equipment Corporation
Micropublishing Group BU /D2
12 Crosby Drive
Bedford, MA 01730

1-2

CHAPTER 2
INTERFACING

2.1 GENERAL
The KD Il-Z CPU loads commercial instructions and operands into the CISP KE44-A. After the CISP
executes the requested operation, the CPU reads the results and stores them in memory. Figure 2-1
shows the KE44-A/CPU interface lines; Table 2-1 describes the interface signals.
NOTE
The KE44-A does not directly interface witb the
UNIBUS, but is connected to the KDII-Z via a bus
that is separate from the UNIBUS and uses the
KDII-Z microcode for data transfers to and from
memory.

PROC INIT L
EXTCLKA L

(

MPCO - 8 L
PAGE FAULT H

)
---

LOAD IR L
CPU

I"0-15
~TRI-STATE
AMUX

KE44-A

)

AMUX L

FORCE CPC L
FORCE CIS OATA L

FREE BUS H
PFAIL BR PEND H

ENAB CIS L
CIS ABORT H

--TK-7232

Figure 2-1

KE44-A/CPU Interface Lines

2-1

Table 2-1

KE44-A/CPU Interface Line Definitions

Mnemonic

Signal Flow

Function

MPC (00:08) L

Bidirectional

Microprogram address lines. Used to sequence
the CPU through the microprogram. Derived
from KE44-A microcode. Cannot be altered by
CPU.

AMUX (00:15) L

Bidirectional

Data lines used to transfer instructions and operands between CPU and KE44-A.

ENAB CIS L

KE44-A to CPU

Forces CPU to a service state after the completion of a CIS instruction; i.e., when a low-tohigh signal transition occurs.

CIS ABORT H

CPU to KE44-A

Clears CIS CPC line when an abort condition exists in CPU.

PROC INIT L

CPU to KE44-A

CPU initialize. Used to initialize status registers
in KE44-A.

LOAD IR L

CPU TO KE44-A

Cause KE44..A to load its instruction register
(lR) from AMUX lines.

TRI-ST ATE AMUX L

KE44-A to CPU

Causes CPU to remove data from AMUX lines.
Turns off the KDII-Z drivers, thus enabling
KE44-A access to the AMUX lines.

PFAIL BR PEND H

CPU to KE44-A

When high, indicates that an interrupt needs servicing. Used by the KE44-A to suspend instructions in the middle of execution.

PAGE FAULT H

CPU TO KE44-A

If high, indicates that a page of memory cannot
be written into. This signal is generated by probing, rather than writing to the page.

FORCE CIS DATA L

CPU to KE44-A

Console-generated signal for monitoring MBUS
data via the AMUX lines.

FREE BUS H

CPU to KE44-A

Console-generated signal that tri-states all maintenance that drive the AMUX lines.

EXT CLK A L

CPU to KE44-A

CPU signal that clocks the control word through
the control logic.

FORCE CPC L

CPU to KE44-A

Console-generated signal for monitoring the CPC
lines via the AMUX lines.

2-2

l.l INITIAL OPERATION
Initially, the CPU fetches an instruction from memory and decodes it in the CPU and CIS. During this
fetch, LOAD IR L is asserted to load the CIS IR. Any instruction with an op code of 0760xx or 0761 xx
is a commercial instruction and requires the use of the KE44-A to process. The CIS next asserts 740 on
the MPC 0-8 microprocessor code bus (MPC bus). Since CIS instructions are only recognized by the
KE44-A option, the assertion of MPC 740 is required to prevent the CPU from trapping on an illegal
instruction. MPC 740 is decoded by the KDII-Z to set up the CIS processor for an operation in the
next CPU cycle. Concurrently with this decoding, a CPC (CIS program counter) address is asserted to
the 88-bit control store of the KE44-A. This control word is clocked by EXT CLK A L from the CPU.
2.3 MICROCODE GENERATION
A series of microcodes is generated in the KE44-A to control microprocessor operation during each
instruction. During CIS operation, the KE44-A informs the CPU (via a microcode asserted on the
MPC 0-8 lines) whenever data can be read from the AMUX 0-15 lines. The KE44-A also sends the
CPU a TRI STATE AMUX L signal that enables it to read data from the AMUX lines. The CPU then
stores this data and continues operation.

2-3

NOTE
Chapter 3 has been duplicated directly from
DECSTDI68-PDP-ll Extended Instructions.

CHAPTER 3
EXTENDED-INSTRUCfION DATA TYPES

3.1

CHARACTER DATA TYPES

There are three different character data types. The 'character' is a
single byte, and is an abbreviated string of length one.
The
'character string' is a contiguous group of bytes in memory.
The
third is a 'character set'.
3.1.1

Character

The character is an 8 bit byte:
7

char

The character is used "as an operand by CISII instructions. When it
appears in a general register, the character is in the low order half;
the high order half of the register must be zero. When it ap~ears in
the instruction-stream, the character is in the low order naIf of a
word; the higb order half of the word must be zero. If the high order
half of a word which contains a character is non-zero, the effect of
the instruction which uses it will be unpredictable.
3.1.2

Character String

A character string is a contiguous sequence of bytes in memory that
and ends on a byte boundary.
It is addressed by its most
significant character (lowest address).
The higbest address is the
least significant character. It is specified by a two word descriptor
wi th the attributes of length and lowest address. The length is an
unsigned binary integer which represents the number of characters in
the string and may range from 0 to 55,535. A cheracter string with
zero length is said to be vacant; its address is ignored. A character
string with non-zero length is said to be occupied.

b~ins

The character string descriptor is used as an operand by CISll
instructions. It appears in two consecutive general registers, or in
two consecutive words in memory pointed to by a word in the
instruction stream. The following figure shows the descriptor for a
character string of length 'n' starting at address 'A' in memory:

Rx
Rx+l

ptr
or

ptr+2

-----------------------------------

3-1

The following figure shows the character string in memory:

Almost sig chari

A+1

A+n-l Ileast sig chrl

3.1.3

Character Set

A 'character set' is a subset of the 256 possible characters that can
be encoded in a byte. It is specified by a descriptor which consists
of the address of a 256 byte table and an 8 bit mask. The address is
of the zeroeth byte in the table. Each byte in the table specifies up
to eight orthogonal character subsets of which the corresponding
character is a member. The mask selects which combinations of these
orthogonal subsets comprise the entire character set. In effect, each
bit in the mask corresponds to one of eight orthogonal subsets that
may be encoded by the table.
The mask specifies the union of the
selected subsets into the character set.
Typical sets ~uld be:
upper case, lower case, non-zero digits, end of line, etc.
Operationally, a character (char) is considered to be in the character
set if the evaluation of (M[table.adr+char] AND mask) is not equal to
zero. The character is not in the character set if the evaluation is
zero.
Each byte in the table indicates which combination of up to
eight orthogonal character subsets (i.e. one for each of the eight
bit vectors 00000001 (2), 00000010 (2), 00000100 (2), 000~1000 (2),
00010000 (2), 00100000 (2),
01000000 (2)
and 10000000 (2»
the
corresponding character is a member. The mask specifies which union
of the eight orthogonal character subsets comprise the total character
set.
For example, if the eight bit vector 00000001(2) appearing in
the table corresponds to the character subset of all upper case
alphabetic characters, 00000010(2) appearing in the table corresponds
to the character subset of all lower case alphabetic characters, and
00000100(2) appearing in the table corresponds to the decimal digits,
then using the mask 00000011(2) with this table specifies the
character set of all alphabetic characters, and using the mask
00000111(2) specifies the character set of all alphanumeric
characters.

3-2

The character set descriptor is used as an operand by CISII
instructions. It appears in two consecutive general registers, or in
two consecutive words in memory pointed to by a word in the
instruction stream.
If the high order half of the first descriptor
word is non-zero, the effect of an instruction which uses a character
set will be unpredictable.
8 7

mask
or
----------------------------------Rx+l
ptr+2
table address
Rx

3.2

ptr

DECIMAL STRING DATA TY~ES

Two classes of decimal string data types -- numeric strings and packed
strings -- are defined. Both have similar arithmetic and operational
properties; they primarily differ in the representation of signs and
the placement of digits in memory.
.
The numeric string data types are signed zoned, unsigned zoned,
trailing overpunch, leading overpunch, trailing separate and leading
separate. The packed string data types are signed packed and unsigned
packed.
Instructions which operate on nllDeric strings permi teach
numeric string operand to be separately specified; similarly, packed
string instructions permit each packed string operand to be separately
specified. Thus, within each of the two classes of decimal strings,
the operands of an instructions may be of any data type wi thin the
appropriate class.

3.2.1

Common Properties

Decimal strings exist in memory as contiguous bytes which begin and
end on a b¥te boundary.
They represent nllDbers consisting of 0 to
31(10) digits in eitner sign-magnitude or absolute-value form.
Sign-magnitude strings (SIGNED) may be positive or negative;
absolute-value strings (UNSIGNED) represent the absolute value of the
magnitude.
Decimal nl.lnbers are whole integer values with an implied
decimal radix point immediately beyond the least significant digit;
they may be conceptually extended with zero digits beyond the most
significant digit.
A 4-bit binary coded decimal representation is used for most digits in
decimal strings. A four bit half byte is called a 'nibble' and may be
used to contain a binary bit pattern which represents the value of a
decimal digit. The following table shows the binary nibble contents
associated with each decimal digit:

3-3

digit

nibble
------

0
1
2
3
4

5
6
7
8
9

0000
0001
"010
0011
0100
0101
0110
0111
1000
1001

Each decimal string data type may have several representations. These
representations permit certain latitude when accepting source
operands. Decimal String data types have a PREFERRED representation
which is a valid source representation and which is used to construct
the destination string.
Addi tional ALTERNATE representations are
provided for some decimal data types when accepting source operands.
Decimal strings used as source operands will not be checked for
validity.
Instructions will produce upredictable results
if a decimal string used as a source operand contains an
invalid digit encoding, invalid sign designator, or in the case of
overpunched numbers, an invalid sign/digit encoding.
When used as a source, decimal strings with zero magnitude are unique,
regardless of sign.
Thus, both positive and negative zero have
identical interpretations.
Conceptually, decimal string instructions first determine the correct
result, and then store the decimal string representation of the
correct result in the destination string. A result of zero magnitude
is considered to be positively signed. If the destination string can
contain more digits than are significant in the result, the excess
most significant destination string digits have zero digits stored in
them.
If the destination string can not contain all significant
digits of the result, the excess most significant result digits are
not stored; the instruction will indicate decimal overflow. Note that
negative zero is stored in the destination string as a side effect of
decimal overflow where the sign of the result is negative and the
destination is not large enough to contain any non-zero digits of the
result.
If the destination string has zero length, no result digits will be
stored. The sign of the result will be stored in separate and packed
strings, but not in zoned and overpunched strings. Decimal overflow
will indicate a non-zero result.

3-4

3.2.2

Decimal String Descriptors

Decimal strings are represented by a two word descriptor.
The
descriptor contains the length, data type, and address of the string.
It appears in two consecutive general registers (register form of
instructions), or in two consecutive words in memory pointed to by a
word in the instruction stream (in-line form of instructions).
The
The
unused bi ts are reserved by the archi tecture and must be 0.
effect of an instruction uSlng a descriptor will be unpredictable if
any non-zero reserved fields in the descriptor contain non-zero values
or a reserved data type encod ing is used.
The design of the nlDeric and packed string descriptors are
identical:
First Word:
length <4:0) - Number of digits specified as an unsigned binary
integer.
data type (14: 12) - Specifies which decimal data type representation
is used.
Second Word:
address <15:0) - Specifies the address of the byte which contains
the most significant digit of the decimal string.
The following figure shows the descriptor for a decimal string of data
type 'T' whose length is 'L' digits and whose most significant digit
is at address 'A':
15 .14

Rx
Rx+1

ptr
or

ptr+2

12 11

5 4

L
T
I ~I
----------------------------------A

The encodings (in binary) for the NUMERIC string data type field are:
000
~01
~10
~11
1~0

101
ll~

111

signed zoned
unsigned zoned
trailing overpunch
leading overpunch
trailing separate
leading separate
reserved by the architecture
-- reserved by the architecture

3-5

The encodings (in binary) for the PACKED string data type field are:
000
001
010
011
100
101
110
111

3.2.3

reserved by the architecture
reser'Jed by the architecture
reserved by the architecture
reserved by the architecture
reserved by the architecture
reserved by the architecture
signed packed
unsigned packed

Packed Strings

Packed strings can store two decimal digits in each byte. The least
significant (highest addressed) byte contains the the sign of the
number in bits <3:0> and the least significant digit in bits <7:4>.
Signed packed Strings The preferred positive sign designator is 1100(2); alternate
positive sign designators are 1010 (2), 1110 (2) and 1111 (2). 'l11e
preferred negative sign designator is 1101 (2) ; the al ternat_e
negative sign designator is 1011 (2) .
Source strings will
properly accept both :.he preferred and alternate designators;
destination strings will be stored with the preferred designator.
Unsigned Packed Strings PACKED SIGN NIBBLE:
Sign
Nibble

-----posi tive
negative
unsigned

Preferred
Designator

Alternate
Designators

1100(2)
1101(2)
1111 (2)

1010(2)
HHl (2)

---------- -----------

111~(2)

1111(2)

For other than the least significant byte, bytes contain two
consecutive digits -- the one of lower significance in bits <3:0> and
the one of higher significance in bits <7:4>.
For numbers whose
lenqth is odd, the most significant digit is in bits <7:4> of the
lowest addressed byte. Numbers with an even length have their most
significant digit in bits <3:0> of the lowest addressed byte; bits
<7:4> of this byte must be zero for source strings, and are cleared to
0000(2) for destination strings. Numbers with a length of one occupy
a single byte and contain their digit in bits <7:4>.
The number of
bytes which represent a packed string is (length/21 +1 (integer
division where the fractional portion of the quotient is discarded) •

3-6

The following is a packed string with an odd number of digits:
4 3

msd

A+l

I lsd

A+[length/2]

I sign I

The following is a packed string with an even number of digits:
7

4 3

msd I

I lsd

I sign I

A+l

A+[length/2]

A zero length packed string occupies a single byte of storage; bi ts
<7:4> of this byte must be zero for source strings, and are cleared to
0000(2) for destination strings. Bits <3:9) must be a valid sign for
source strings, and are used to store the sign of the resul t for
destination str ings.
When used as a source, zero length str i ngs
represent operands with zero magnitude. When used as a destination,
they can only reflect a resul t of zero magni tude wi thout ind icat ing
overflow. The following is a zero length packed string:
7

4 3

" I sign I

A valid packed string is characterized by:
1.

A length from" to 31(10) digits.

3-7

Every digit nibble is in the range 0000(2) to 1001(2).

Po r even leng th sources, bi ts (7: 4>
byte are 0000(2).

Signed Packed Strings - sign nibble is either 1010(2),
1011(2),1101(2),1101(2),1110(2) or 1111(2).

UnSigned packed Strings - sign nibble is 1111(2).

3.2.4

0 f

the lowest add ressed

Zoned Strings

Zoned strings represent one decimal digit in each byte.
Each
byte is divided into two portions -- the high order nibble (bits
(7:4» and the lov order nibble (bits (3:0». The lov order nibble
contains the value of the corresponding decimal digit.
Signed Zoned Strings When used as a source string, the high order nibble of the least
significant byte contains tne sign of the number; the high order
nibbles of a~l other bytes are ignored. Destination strings ara
stored wi th the sign in the high order nibble of the least
significant byte, and 0011 (2) in the hi9h order nibble of all
other bytes. 0011(2) in the high order nibble corresponds to the
ASCII encoding for numeric digits. The positive sign designator
is 0011(2); the negative sign designator is' 0111(2).
Unsigned Zoned Strings When used as a source string, the high order nibbles of all bytes
are ignored. Destination strings are stored with 0011(2) in the
high order nibble of all bytes.
The number of bytes needed to contain a zoned string is identical to
the length of toe decimal number.
7
A

4 3

I msd

A+1

A+n-1

'sign I lsd

3-8

'sign' is present only
signed zoned strings

A zero length zoned string does not occupy memory; the address portion
of its descriptor is ignored.
When used as a source, zero length
strings provide operands with zero magnitude; when used as a
destination, they can only accurately reflect a result of zero
magnitude (the sign of the operation is lost). An attempt to store a
non-zero result will be indicated by setting overflow.
A valid zoned string is characterized by:
1.

A length from 9 to 31(19) digits.

The low order nibble of each byte is in the range 0000(2) to
1091(2).

Signed Zoned Strings - The high order nibble of the least
significant byte is either 9911(2) or 9111(2).

3.2.5

OVerpunch Strings

OVerpunch strings represent one decimal digit in each byte. Trailing
overpunch strings combine the encoding of the sign and the least
significant digit; leading overpunch strings combine the encoding of
the sign and the most significant digit. Bytes other than the byte in
which the sign is encoded are divided into two portions -- the high
order nibble (bits <7:4» and the low order nibble (bits <3:9~). The
low order nibble contains the value of the corresponding decimal
digit.
When used as a source string, the high order nibble of all
bytes which do not contain the sign are ignored. Destination strings
are stored with 0011(2) in the high order nibble of all bytes which do
not contain the sign. 9011(2) in the high order nibble corresponds to
the ASCII encoding for numeric digits.
The following table shows the sign of the decimal string and the value
of the digit which is encoded in the sign byte. Source strings will
properly accept both the preferred and alternate designators;
destination strings will store the preferred designator.
The
preferred designators correspond to the ASCII graphics 'A' to 'R', '{'
and '}'. The alternate designators correspond to the ASCII graphics
, 0' to '9', '[', '?', '1', '!' and ':'.

3-9

OVERPUNCH SIGN/DIGIT BYTE:
Overpunch
Sign/Digit

---------+0
+1
+2
+3
+4
+5
+6
+7
+8
+9
-0
-1
-2
-3

-4
-5
-6
-7

-8
-9

Preferred
Designator

Alternate
Designators

01111~11(2)
01~00001(2)
01000~10(2)
010~0011(2)

~~11000~(2) , 01~11011(2), 00111111(2)
00110001(2)
00110010(2)
00110011(2)
00110100(2)
00110101(2)
00110110(2)
00110111(2)
00111000(2)
00111001(2)
01011101 (2) , 00100001 (2), 00111010 (2)

----------

01000100(2)
0100~101(2)

01000110(2)
01(~00111 (2)

01001000(2)
01~01001(2)
~1111101(2)

-----------

01001010(2)
01001011(2)
01001100(2)
01001101(2)
01~01110(2)

01001111(2)
01010000(2)
01010001(2)
01010010(2)

The number of bytes needed to contain an overpunch string is identical
to the length of the decimal number.
The following is a trailing overpunch string:
7
A

4 3

I msd

A+1

A+n-1

I sign and 1sdl

3-10

The following is a leading overpunch string:
7

4 3

I sign and msdl

A+l

A+n-l

lsd I

zero length overpunch string does not occupy memory; the address
portion of its descriptor is ignored.
When used as a source, zero
length strings provide operands with zero magnitude; when used as a
destination, they can only accurately reflect a result of zero
magnitude (the sign of the operation is lost). An attempt to store a
non-zero result will be indicated by setting overflow.
A

A valid overpunch string is characterized by:
1.

A length from e to 31(10) digits.

The low order nibble of each digit byte

is in the range

0000 (2) to HHH (2) •

3.2.6

The encoded sign/digit t;>yte contains values from the above
table of preferred and alternate overpunch sign/digit values.

Separate Strings

Separate strings represent one decimal digit in each byte. Trailing
separate strings encode the sign in a byte immediately beyond the
least significant digit; leading separate strings encode the sign in a
byte immediately beyond the most significant digit. Bytes other than
the byte in which the sign is encoded are divided into two portions -the high order nibble (bits <7:4» and the low order nibble (bits
<3:0». The low order nibble contains the value of the corresponding
decimal digit.

3-11

When used as a source string the high order nibbles of all digit bytes
are ignored. Destination strings are stored with 0011(2) in the high
order nibble of all digit bytes.
0011 (2) in the high order nibble
corresponds to the ASCII encoding for numeric digits. The preferred
positive sign designator is 00101011(2) and the alternate positive
sign designator is 00100000 (2) •
'ftle negative sign designator is
00101101(2). These designators correspond to the ASCII encoding for
'+', 'space' and '-'.

SEPARATE SIGN BYTE:
Sign
Byte
positive
negative

Preferred
Designator

Alternate
Designators

---------- ----------00101011(2) 00100000(2)
00101101(2)

The number of bytes needed to contain a leading or trailing separate
string is identical to 1ength+l.
The following is a trailing separate string:
7
A

4 3

msd I

A+1

lsd I

A+n-l

A+n

sign

3-12

The following is a leading separate string:
7

4 3

A-I

sign

msd I

A+l

A+n-l

lsd I

A zero length separate string occupies a single byte of memory which
contains the sign. When used as a source, zero length strings provide
operands with zero magnitude; when used as a destination, they can
only reflect a result of zero magnitude without indicating overflow;
the sign of the result is stored.
The following is a zero length trailing separate string:
7

A .1

sign

The following is a zero length leading separate string:
7

A-I

sign

A valid separate string is characterized by:
1.

A length from 0 to 31(19) digits.

The low order nibble of each digit byte is in the range
0000(2) to 1901(2).

The sign byte
99191101(2) •

eitner

3-13

00199000 (2),

99101011 (2)

3.3

LONG INTEGER

Long integers are 32 bit binary two's complement numbers organized as
two words in consecutive registers or in memory -- no descriptor i!:
used.
One word contains the high order 15 bits.
The' sign is in
bit<15>; .bit<14> is the most significant. The other word contains the
low order 16 bi ts wi th bi t<0> the least signi ficant.
The range of
numbers that can be represented is -2,147,483,648 to +2,147,483,047.
The register form of decimal convert instructions use a restricted
form of long inteqer with the number in the general register pair
R2-R3:

15 14
R2

Is I

high
low

The in-line form of decimal convert instructions reference the
long
integer by a word address pointer which is part of the instruction
stream:

15 14
ptr
ptr+2

low

Is I

high

Note that these two representations of long integers differ. There is
no single representation 0 f long integer among EAE, ErS, FPP and
software. The "register form" was selected to be compatible with EIS;
the "in-line form" was selected to be compatible with current standard
software usage.

3-14

CHAPTER 4
THEORY OF OPERATION

4.1 2901A MICROPROCESSOR SLICER
A functional block diagram of the KE44-A (Figure 4-1) shows the use of 290 I A in the binary data path.
The 2901 A has four 4-bit microprocessor slices that are configured for carry lookahead and external
shift control in the 16-bit data path (Figure 4-2). The principal elements in each of the identical 290 I As
are: 1) a 16-1ocation RAM, 2) a high-speed ALU, and 3) a separate, shiftable hol4ing register called the
Q-register. The RAM locations are used as KE44 working registers. The ALU, in conjunction with the
working registers and the Q-register, performs the arithmetic and logical functions necessary to implement the macroinstruction set. Data enters the 290lAs from the 290lA D bus; 2901A output data is
transmitted on the 290lA Y bus. The output data is from either the 290lA ALU or the contents of a
2901A RAM (working register) location.

4.1.1 290IA RAM
In the KE44-A, the RAM of the 290 I As is the scratch pad area where the results of the arithmetic and
logical operations can be temporarily stored. RAM contents are read into the ALU in response to microcode control signals received from the control store logic. Since each of the four 2901A microprocessors comprising this RAM has a 16 X 4-bit slice, the combination yields a total RAM capacity of
sixteen 16-bit words.
The data in any of these words can be read from the A port via the 4-bit RAM APORT 0-3 H address
line inputs. If the same address is applied to both A and B address lines, identical data appears at both
RAM output ports. The RAM A and B outputs are applied to latches. When the RAM is write-enabled,
new data is written into the RAM word selected by the RAM B input PORT 0-3 H. The RAM input
data is received from a 3-input multiplexer (Figure 4-2). Multiplexer 00-03 inputs from the ALU output permit the ALU result to be loaded into the RAM directly, or to be left- or right-shifted by one
place.

4-1

STATUS INFORMATION AND CON·
DITtON CODE GENERATION

IR DECODE,
CPC, AND MPC
ADDRESSING LOGIC

BINARY DATA
PATH

.------------,-----.-------,-----------------,
BCD DATA PATH

"60"
BCDMUX

<53:50>
<31:28>

I
I

L-- T - - - - - - - - - - " ' "
I

~--~~-r~~LOADIRI11 I

MPC

I
I
I
I

- - - - _ _<08:00>
________J
Figure 4-1

KE44-A Block Diagram

DATA OUTPUTS UI LINES TO SWAP BVTE CKTS;
fROM RAM PORT "A" OR ALU. DEPENDING UPON
2:1 MUX)
DEST • ALU .l26IINATION SELECT
FUNC" ALU ~ION
SRC- ALU SPUBCf. OPeRANDS

~O ~' ~2

OUT
EN

ALU
CARRY OUT

TO CPU

<61-59>

GEN
PROP
OVERFLOW

fSIGN

ALU OST {

pf J
,,,,
.~

Ul:'

Co'"
R2

ALU

G P (VR
S1

,
,
,
'~,l,l..l..1
~~r'f~i~~ ~~1F~~~~~7~~~

ALU F (3:0 HlJTPUT

ALU FTN{
<58-56>

.Jrl

i...-

ALUSRC{ 11

<55:53>

.,"' 'm' '"

10
OREGISTER{ OL
SHIFT LEFT

APORT
"A"WORD
ADDRESS

"B"WORD
ADDRESS
BPORT

<88:85>

NJ
A1

A2
A3
80
81
82
83

fttf

,113 B2 81 80,

PORT "A" OUT

~ 03

01
a REGISTER
02
01

PORT "8"

A2
)'READ ONLV, RAM OUT
A1
(RIW)
NJ
83
82
81

BO
D3

ADDRESS
INPUTS

H~~~~

ffff·

~~M(U A2 A11UJ,
~

~LK CP

"I
E 8 LATCH"

E A LATCH

CLOCKCP

<75:72>

f---

r')tyr

11.4 2 PORT

QR
INPUT DATA
Dt
02

a REG SHIFT RIGHT

6~.A .A
~ ~ Yff -z-r~f~~ ~~
I

&\1
FL

RAM
SHIFT LEFT7 (X)

r--

FR RAM
SHIFT RIGHn (+)

Figure 4-2 2901A Detailed Block Diagram

4.1.2 Arithmetic Logic Unit (ALU)
The ALU is the data path component that performs the arithmetic/logical operation under command
of the microcode control word (Table 4-1) contained in the control store logic PROMs. ALU R inputs
are from four 2-input multiplexers whose inputs are the direct data inputs 03-00 and the A port outputs A3-AO of the RAM. The S inputs, received via four 3-input multiplexers, include the A and B
ports of the RAM and the Q-register outputs.
Decode of the ALU function (FUNC) lines 13-15 determines the arithmetic or logical function to be
performed. Decode of the ALU destination (DEST) lines 18-16 determines which of the indicated registers the data is routed to or whether it will be a data output of the device itself. ALU output data
F3-FO can be routed to the Q-register or RAM, or placed on lines as Y3-YO.

Table 4-1

Microcode Matrix for Source Operands
and ALU Functions

A.Q

A.B

O.Q

O.B

O.A

D.A

D.Q

D.O

A+Q

A+8

O+A

O+Q

Cn=H

A+Q+I

A+8+1

0+1

8+1

A+I

D+A+l

D+O+l

0+1

Cn=L

Q-A-I

8-A-I

Q-I

8 I

A-D-l

Q-D-I

-D-l

Cn=H

Q-A

8-A

A-D

Q-D

-0

Cn=L

A-Q-l

A-8-1

-Q-I

-8-1

-A-I

D-A-l

D-Q-I

0-1

Cn=H

A-Q

A-B

-Q

-A

D-A

D-Q

RORS

AVQ

AVB

D-A

DVQ

RANDS

AI\Q

AI\8

DI\A

DI\Q

RANDS

AI\Q

AI\B

D~A

D~Q

R EX"()R S

A\fQ

A~B

D\+A

DVQ

-D

REX-NOR S

-AVQ

AVB

OVA

OVQ

12 I 0 Octal
ALU
Source
154 J Octal

AlU
Function

Cn=L
0

..,

R Plus S

S Minus R

R Minus S

+ = Plus: - = Minus: V = OR, 1\ = AND: V = EX OR

4-4

The ALU source operand decode performs the actual register selection. All three of these functions are
controlled by ALU instructions 18-10 from the control store logic.
The ALU can perform three binary arithmetic and five logical operations on the two input words received via the Rand S inputs. Each R input is driven by a separate 2 input multiplexer and each S
input from a separate 3 input multiplexer. In the KE44-A CIS, the R input multiplexer can be used to
select either the RAM A port data or a direct data input consisting of constants or MBUS data. The S
input multiplexer selects the Q-register output or the RAM output of port A or B. Both multiplexers
have an inhibit output capaDility that produces a source operand of zero.
4.1.2.1 Logical and Arithmetic Functions - The ALU performs five logical and three arithmetic functions on eight source operand pairs. ALU logic functions and appropriate control bit values (source
select 12-10, and function select 15-13) are described in Table 4-2. The carry input (C n) has no effect
on operations in logic mode but does affect operations in arithmetic mode (Table 4-3), which defines
carry-in high (C n = 1) and carry-in low (C n = 1) for this mode.

Table 4-2

ALU Logic Mode Functions

Octal
1543,12JO

40
4)
45
46
30
31
35
36
60
6I
65
66
70
7I
75
76
72
73

Octal
Group

Function

1543,1210

74
77

AI\Q
AI\B
AND

62
63
64

AVO
AVB
DVA
DVQ
A\¢Q

EXOR

EX NOR

Function

Invert

A
D

DI\A
DI\O

Group

A\fB
D\fA

32
33
34
37

AVQ
AVB
DVA
DVQ

44
47

50
5I
55
56

4-5

42
43

Pass

D\fQ

-Q

Pass

B
A

D
0
0
UZeroH

0
0
A/\Q
A 1\8

Mask

DM
DI\Q

Table 4-3 ALU Arithmetic Mode Functions
C n =0 (Low)

Octal

Is 4 J' 12 I 0
00
o1
05
06
02
03
04
07
12
13
14
27

Group

ADD

PASS

Decrement

.., ..,

23
24
17

10
11
15
16
20
21
25
26

l's Compo

Subtract
( 1's Comp.)

C n = I (High)

Function

Group

Function

A+Q
A+B
D+A
D+Q

ADD plus
one

A+Q+l
A+B+l
D+A+l
D+Q+l

Q
8
A
D

Increment

Q-I
8-1
A-I
D-l
-Q-l
-8-1
-A-l
-D-l
Q-A-l
8-A-l
A-D-I
Q-D-l
A-Q-I
A-8-1
O-A-I
D-Q-I

Pass

2's Compo
(Negate)

Subtract
(2's Comp.)

Q+l
8+1
A+l
D+l
Q
8
A
D
-Q
-8
-A
-0
Q-A
8-A
A-D
Q-D
A-Q
A-8
D-A
D-Q

4.1.2.2 Logical Functions for G, P, CN+4, and OVR - When the microprocessor is in the add or subtract mode, signals G and P indicate carry lookahead, C n +4 indicates carry, and OVR indicates overflow conditions. However, OVR is not used in the CIS implementation. Table 4-4 gives the logic equations for the G, P and C n +4 signals for each of the eight ALU functions. The Rand S inputs are the
two inputs selected in accordance with Table 4-4.
4.1.3 Q-Register
The Q-register, a file loaded from the ALU, functions as a temporary storage register. Q-register output can be loaded back into itself, or shifted right or left (e.g., during convert, multiply, divide or arithmetic shift operations).

4-6

Table 4-4

P, G, CN+~ and OVR Functions

1543

Function

C.+ 4

OVR

R+S

p)P2P,Po

G) + p)G 2 + p)P 2G, + p)P 2P,G O

C) VC.

S - R

Same as R + S equations, but substitute R, for R, in definitions

R-S

Same as R + S equations: but substitute S, for S, in definitions

RVS

Low

p)P 2P,PO

p)P 2P,PO + C n

Rf\S

Low

G} + G 2 + G, + Go

G} + G 2 + G, + Go + C n

G} + G Z + G, + Go + C n

li"s

Low

RVS

+ =OR
V =OR

" = AND
¥ = EX OR

Same as R " S equations, but substitute R, for R, in definitions
Same as R ¥ S, but substitute R, for R, in definitions

G J + G 2 + G, + Go

Po = Ro + So

G} + p)G 2 + p}P2G, + p)P 2P,Po

G J + P JG 2 + p)P 2G, +
P J P 2P,PO (Go + Cn)

[P2 + G2P, + G2G,PO + GlG,GoC nl ¥
[PJ + G)Pl + G JG 2P, + G)G 2G,PO + GJG2G,GoC nl

c. == G) + p)G l + p)PlG, + PJ P2P,GO + p)P2P,POC
C J == G 2 + PlG, + P2 P,Go + P2P,POC n

4.1.4 Bit Shifting
After data has been parallel-loaded into the microprocessor, both the Q-register and any RAM data,
addressed by either A or B port, may be shifted left or right. To accomplish these shifts, the most significant bit (MSB) of each 4-bit microprocessor is connected to the least significant bit (LSD) of the adjacent, more significant, 4-bit microprocessor via a bidirectional transfer line. During a shift operation,
the bit transferred out of the last 2901A (E47) is used as the final shifted-out bit.
4.1.5 Status Bits
Each 4-bit microprocessor generates two status bits, F =0 and F sign.
The F=O status bit provides zero detection by indicating when the data equals zero. It is an opencollector output which uwire ORs" the two 2901As associated with each byte. Each byte, therefore, has
a signal that indicates zero. These signals are CIS ALU 0-7=0 H and CIS ALU 8-15=0 H.
The F sign output is used to monitor the MSD of each 4-bit microprocessor. Only the highest nibble in
each byte is monitored. The signal names are CIS ALU 07 H and CIS ALU 15 H. The F3 outputs of
the low nibbles for the two remaining 4-bit microprocessors are not used.
Both status bits (CIS ALU 15 H and CIS ALU 07 H) can be monitored without enabling the output
driver in the 4-bit microprocessor. Either bit can be used as a sign bit during CIS operations.

4.1.6 Carry Lookahead Logic
The 2901 As use full lookahead carry logic that speeds instruction execution. Each of the four 4-bit
microprocessors generates both a carry generate (G) and a carry propagate (P) output. The four pairs
of G and P signals are combined in a single 745182 lookahead carry generator.
4.1.7 2901A Pin Definitions
Pin assignments for the AM2901A, 40 pin dual in-line package are shown in Figure 4-3.

Am2901 A

NOTE: PIN 1 IS MARKED FOR ORIENTATION.
TK·7231

Figure 4-3

AM2901A Pin Connections

4-8

4.2 INSTRUCTION SUSPENSION (INTERRUPT)
The execution time for some CIS instructions will use more CPU time if longer than normal string
lengths are involved. Therefore, to keep BR latencies below 35 microseconds, the CIS permits interrupt
of all CIS instructions except two (L2Dr and L3Dr). The interrupt routine, called "CIS instruction
suspension," allows an interrupted instruction to be restarted from the point of breakoff. This feature is
important because to run an entire instruction again from its beginning would mean very long execution
times. Suspension allows high priority devices to interrupt the processing sequence so that the CPU can
service the interrupting device.
Any number of interrupts can be made during a CIS instruction. Also any CIS instruction can be interrupted by another CIS instruction since all the necessary information is stored on the stack and not in
the CIS.
4.2.1 Steps Leading To Suspension
The CIS' microcode checks for BRs at specific points in the microinstructions. Macroinstructions, a
collection of microinstructions that read like English, are used to test for service. The macroinstruction
used is either a "service?" or a previously defined macro which adds "service?" to it. This macro sets
the CONBR2 field to a value of 07, to address a conditional branch PROM (programmable read-only
memory) whose output enables E78 (74S03).
Upon receipt of a BR, the CPU asserts PFAIL BR PEND. This signal is "ANDed" with the CONBR2
field (referred to above) to assert CPCOO. The CIS microcode then branches to a location corresponding to the existing CPC "ORed" with a 1. This routine is the start of a CIS "save state" operation that
pushes all necessary information onto the processor stack.
In a series of instructions, the microcode also pushes the CIS status, the contents of some of the 2901 A
registers, and the returning CPC address onto the stack. The CIS then moves the PC address back to
the beginning of the CIS instruction; PSW bit 8 is set (indicating a suspended CIS instruction), and the
device interrupt service routine is entered.
4.2.2 Returning from Suspension
After the interrupt is serviced, the stack is popped, thereby returning the processor to the previous PC
and processor status word (PSW). The PC used is the backed-up PC. The PSW has bit 8 set, indicating
a suspended instruction.
The CIS instruction begins execution as if a suspension had not occurred. The CIS microcode tests for
PSW bit 8 which, if set, causes branching to the "restore" subroutine. This subroutine restores the CIS
status bits, the contents of the 290lA registers, and the returning CPC address from the stack. After
the CIS has been restored, it returns to the CPC address from which exit was made and continues
processing the interrupted microcode.
4.3

DET AILED LOGIC DESCRIPTION
(Reference: CS-M7092, page 6 of 10)

4.3.1 IR Decode
The clock signal for CIS (CIS ClK l) is derived from the processor signal EXT ClK A l. EXT ClK
A l is inverted to become CIS ClK H, and this signal is inverted to become CIS ClK L. Cycle time is
180 nsec short cycle and 240 nsec long cycle with 30 nsec off time.

4-9

The fetch cycle for the CIS is like the cycle of any other instruction. MPC lOis latched into the processor instruction register by the deassertion of PROC CLK L, which also asserts LOAD IR L (Figure 44). The instruction is fetched at MPC 10 and then decoded in the KD ll-Z and the M7092 module of
the CISP. The instruction is present on the AMUX lines and since CIS DIS IBUF H (bit 48) is unasserted, the CIS instruction register also has the instruction. The instruction is latched by E69-11
(LOAD IR L) being asserted and E69-12 (CIS CLK L) becoming asserted. CIS INST H (E80-9) is
also asserted at this time.
This sequence occurs for all instructions. If a CIS instruction is present, E80-8 (CIS INST L) is asserted, partially enabling E89, the starting address PROM. E89 is completely enabled when CIS CLK
L becomes unasserted. At this time, the next CPC address is asserted from the starting address PROM.
This CPC address is applied to the control store (M7091) which outputs the starting microinstruction
(See Chapter 5 for bit descriptions). This microinstruction contains the 88 bits of information used to
direct CIS logic operations. Bits (87:76) contain the next, CPC address to execute.
PROC ClK l
EXT ClKA L
(CIS ClK l)

MPC10 lATCHED INTO
PROCESSOR IR AND
EXECUTED
SIGNAL LOAD IR L
ASSERTED

u u u
STARTING CPC BEGINS
- - EXECUTION
CIS ENAB ASSERTED

CIS IR LATCHED BY
ASSERTION OF LOAD
IRLANDCISCLKL

CIS INST H ASSERTED

ES2-S ASSERTED HIGH
MPC 740 GENERATED
BY E94-11 ASSERTING
LOW

STARTING CPC ROM
(ES9) ENABLED. STARTING CPC ADDRESS
ASSERTED.
TK-7233

Figure 4-4

MPC Timing

4-10

4.3.2 CPC Branching
The next CPC can be modified to branch to a different location if certain conditions exist. For example,
a 290} A subtract operation could be executing and a test for carry may be needed. The C-bit would
then determine whether the initial CPC, or the CPC "ORed" with bit 01, should be executed next.
Table 4-5 shows which signals can cause branches and the affected CPC bit(s). Branching is caused by
"ORing" bits 0, } or 2 of the CPC lines.
Table 4-5 CPC Bits Affected by Branching Conditions

CPC Bits Affected

Signal Name
CIS PAGE FAULT H
CIS CCZ H
CIS SHIT OUT H
PFAIL BR PEND H
CIS NONZERO A H
CIS NONZERO C H
CIS IRO} H
CIS IR06 H
CIS NONZERO A and not
CIS NONZERO B

0
0
0
0
0
0
0
0
0

CIS CCC H
CIS SUB OP H
CIS SIGN 2 H
CIS DST ADR ODD H
CIS SIGN} H
CIS IR05 H
CIS IR 04 H
CIS NONZERO B
CIS IR 00 H
CIS DST ADR ODD and not
CIS SRC} ADR ODD
CIS NONZERO B and not
CIS NONZERO A

}
I
1
1
1
1
1
1
1
1

CIS CCN H
CIS C/B H
CIS SRC } ADR ODD H
CIS SRC 1 ADR ODD and not
DST ADRODO

2
2
2
2

CIS NONZERO A and CIS NONZERO B

0, }

CIS DST ADR ODD and CIS SRCI ADR ODD

I, 2

4-11

4.3.3 MPC Addressing
At the same time the starting CPC address is asserted, an MPC of 7408 is also asserted. This is a result
of both E94-13 (CIS INST H) and E94-12 (output of ES2-S) being high. The cOll}ponents used to
generate the MPC are EIIO, EIII, and E122. Asserting the MPC 740 prevents the base machine from
trapping to ten. The base machine itself does not recognize CIS instructions.
4.3.4 Maintenance Switch
Switch S I selects either the upper or lower part of the starting address PROM (ES9). This switch
should be off for field use (e.g., when viewing the board from side 1 with the switch at the upper right
side of the board, the switch lever should be to the left). The other switch position is used during the
manufacturing test.
4.3.5 BCD Operation PROM
IR06 - IROO connects to the input of the BCD OP PROM (E91) which, during binary coded decimal
(BCD) operation, sets up the initial operation of the BCD ALU PROMs (E41, E43). The BCD ALU
control signals, called DEC 01 H and DEC 00 H, are obtained from the OP MUX (E73). E73 selects
either the initial operation from the BCD OP PROM or a different operation by using OPOIH and
OPOOH (bits 33 and 32 of microword). DEC 01 H and DEC 00 H direct the BCD ALU to one of the
operations shown in Table 4-6.
The need for changing operations after the instruction has already been defined, is used, for example, in
the divide packed (DIVP) instructions. A DIVP uses successive shift rights and subtracts. The end of
the digit string may not be known until one too many subtracts have been completed. In this case an
add is needed to restore the string by one digit and will be done bY'setting DEC 01 and 00 to a value of
00.

Table 4-6

BCD ALU Operations

BCDALU
Control Lines
DEC
01

DEC
00

ALU
Function

A+B

0
I
I

A-B
B-A
AXB

0
I

4-12

4.4

DETAILED BINARY DATA PATH
(Reference: CS-M7092, pages 1, 2, 3, 4 of 10)
The binary data path, as mentioned earlier, centers around the four 2901A bit slices, E44, E45, E46,
and E47. (Refer to the 2901A description in Paragraph 4.1 for operational details.)
4.4.1 Direct Data (ALU-In) Multiplexer
The four 2901As, when combined, form seventeen 16-bit registers that are addressed by either the A
port (read-only) or the B port (read/write). Data is supplied to the register by the "direct-data-in" lines,
or internally from a resulting operation. If the direct data input is used, data can be selected by the
ALU-in (direct data) multiplexer from either the internal CIS bus (MBUS) or from the constants circuitry. The ALU-in multiplexer is made up of E24, E14, E39, E40. The signal SELECT ALU IN H
(bit 52) to the multiplexer makes the selection.
4.4.2 Constants Generation for 2901A
During CIS instruction, a constant may be needed to count up (or down) the number of bits in a character string, to add two to the PC, or other such operations. The constants PROM (E4) generates these
constants by addressing the PROM with CONST SEL S2H - SOH of the control store bits 40-38. The
outputs of E4 are applied to E3/E2 (a 74LS298 2:1 multiplexer/latch) which selects either the constants PROM or the MBUS. The output of E3/E2 drives the ALU-in multiplexer or, if ENAB CONST
L (bits 27-25) is asserted, also drives the MBUS.
4.4.3 Saving Constants Before Suspension (Interrupt)
A BR request will suspend the CIS instruction. Before the actual suspension occurs, the CIS must clean
up and save information on the stack. Constants previously generated must also be saved on the stack.
Storing the constants is a two step process.
1.

The constant must be enabled to the MBUS by asserting CIS ENAB CONST L. This signal
is derived from the CON2 field of the control store, bits (27:25). E13, an octal buffer, then
enables the constants to the MBUS.

By this time, the CPU will have addressed a stack location. The data on the MBUS must
then be pushed onto the stack of the CPU after transmission via the output multiplexer and
the AMUX lines. (Paragraph 4.2 gives a more detailed description of suspension protocol.)

4.4.4 Restoring Constants After Suspension (Interrupt)
After completion of a CIS instruction suspension, instruction execution is resumed (from the point of
exit) by popping the stack and retrieving the information stored there before suspension. One of these
stored pieces of data is the constant.
At this point in the restoration of constants after suspension, the MPC directs the CPU to obtain the
information from the stack for transmission to the MBUS via the AMUX lines. The CIS control store
then deasserts SEL CONST H and asserts LOAD CONST H. SEL CONST H, being unasserted, selects the 0 input of E3/E2 (the 2:1 multiplexer latch previously referred to), which accepts the MBUS
data. LOAD CONST H enables E59 (a 74S00) to latch the MBUS data at the end of the cycle.

4-13

4.4.5 290tA Write Operations
The 2901A registers are written to on the trailing edge of the clock only. The upper and lower bytes can
be written independently of one another by asserting either CIS SP HIGH WRITE H (Bit 70) and/or
CIS SP WRITE H (bit 71) with the trailing edge of the clock. (Figure 5-1 shows the bit fields of the
CIS microword and Appendix D gives the meanings of the mnemonics involved.)
The result of the 2901A operation, if selected, can be taken from the 2901A at the Y output (pins
39-36) or can be circulated to another internal register. The output of the 2901A can be enabled by pin
40 (OUT EN) going low if qualified by one of three inputs: FORCE CIS DATA, FREE BUS or DISAB IBUF H (bit 48).
FORCE CIS DATA and FREE BUS, which are generated by the KDII-Z MFM (multifunction)
M7096 module, are used to look at the MBUS data. If the 290 I A is enabled to the MBUS, the data
viewed by the MFM is the 2901 A data.
DISAB IBUF H (bit 48) determines whether the 290lA data or the AMUX data is selected as the
input to the input multiplexer (EI6, E5, E8, E17, E6, E7, E9, and EI8).
4.4.6 290 I A Shift Operations
The 2901A internal Q-Register and RAM can be connected together to form a 32-bit word that can be
shifted left or right. Shift-function electrical connectiofls are shown on page 6 of lOin the M7092 Print
Set; Figure 4-5 shows the results of these connections. SHFT SI and SHFf SO are bits 63 and 62,
respectively.
4.4.7 Input Multiplexers
The input multiplexer receives:
•
•
•
•

The direct output of the 2901A or the direct input AMUX data
The swapped bytes of the 2901A output or swapped bytes of the AMUX data input
BCD data in the low byte
BCD data in the high byte

Swapping is performed in the INPUT MUX (E5, E 16, E 17, E8, E6, E7, E9 and E 18) by asserting the
signal SWAP SEL H. That is, while the CIS is fetching data over the AMUX lines, the received highbyte data is swapped; i.e., it appears in the low-byte of the word used by CIS. SWAP SEL H is generated by E71, which selects one of four inputs to determine whether or not to swap. The input signals to
E71 are:
Signal

Function

o
1

No swap
Swap

CIS SRCI ADD ODD H
CIS SRC2 ADD ODD H

Swap if SRC 1 ADR was ODD
Swap if SRC 2 ADR was ODD

These signals are selected by SWAP S 1Hand SWAP OOH of the control store (bits 50-49).
The output from the INPUT MUX is enabled to the MBUS by asserting INPUT ENAB H (bit 51).
The outputting of data from the MBUS to the AMUX is done by enabling ENAB OBUF H (bit 47)
which enables TRI STATE AMUX L and the output multiplexer (E34, E26, E25, E27).
The CPC lines can be enabled onto the AMUX line for viewing on the console terminal by the E/M 1
command. This is accomplished by asserting FORCE CPC L and FREE BUS H from the M7096 multifunction module (MFM) in the CPU.
4-14

A) SHFT S1 - 0
RAM

SHFTSO-O

OREG

L( SERIAL SHIFT H

SHIFT OUT H . J

B) SHFT S1 - 0
RAM

SHFT SO-1

OREG

L( SERIAL
SHIFT H

SHIFT OUT H.J
15

C) SHFT S1 - 1
RAM

SHFT SO- 0

SERIAL SHIFT H

OREG

L. SHIFT OUT H

15 .

D) SHFT S1 - 1
SHFT SO- 1

SERIAL SHIFT H

RAM

OREG

>---'

L.SHIFT
OUTH
TK.72:M

Figure 4-5

2901A Shift Operations

DETAILED BCD ALU DESCRIPTION
(Reference: CS-M7092, pages 5 and 9 of 10)
The BCD ALU performs its arithmetic by table lookup. A 2-operand add (A+ B) applies the two least
significant nibbles to a ROM E43 as an address; the output data is an arithmetic result and a carry. If a
carry is generated by the addition, it will ripple through to the next arithmetic unit (E4l). The arithmetic performed by E41 is identical to that of E43. However, E41 operates on the two most significant
nibbles and, if present, a carry from E43. E41 generates the final carry for addition and subtraction.
4.S

The ALU can do four operations which are controlled by the DEC 00 and DEC 01 bits (Table 4-6,
BCD ALU Operations).
4-15

4.5.1 BCD" A" Register/BCD "B" Register
The input operands are obtained by loading the A register (E29, E20) and the B register (E 10, E21)
with one or two nibbles. The registers are loaded by asserting either LOAD AREG H or LOAD BREG
H. The outputs of the registers are latched up at the end of the cycle during the low to high transition of
the clock. The output data remains the same until the registers are loaded again or PROC INIT is
asserted.
"A" register output is applied directly to the BCD ALU. "B" register output, however, can be shifted
left or right, or sent straight through to the BCD ALU. These functions are accomplished in the BCD
shift multiplexer (Ell, E22, E54, E31, E32) and are selected by BMUX SO and BMUX SI (bits 34
and 35). The BCD shift multiplexer can also generate a zero for the BCD ALU.
The shift nibble (E64) stores the "shifted-out" nibble from Ell when BMUX SO (bit 34) is high. This
shifted-out nibble is usually used to hold the sign nibble for the BCD multiplexer before going to the
2901 A or MBUS.
4.5.2 BCD Carry
A carry (C/B 3 H) generated from E43 during an add or subtract operation mayor may not propogate,
depending on the selection made by the 2:1 multiplexer E83. E83 selects either the C/B generated by
E43 or, if latched by EI02 (a 74S74) in a preceding operation, selects C/BH.

4.5.3 BCD Multiply
The largest addition of two BCD nibbles is 9 + 9. Therefore, an add or subtract operation can only
generate a carry of one bit. The answer is 18, where 8 is the low-nibble answer with a carry of one.
A multiply operation can generate a larger carry. That is, the largest multiply can be 9 X 9. The answer is 81, where 1 is the answer with a carry of 8. To obtain the answer, the two operands are still
applied to E43 to obtain the low-nibble answer, but the carry is generated by table lookup in a 1K X 4
ROM (E42).
4.5.4 BCD ASCII Encoding
The BCD multiplexer (E51, E49, E76, E53) selects one of the following for input.
•
•
•
•

The output of the BCD ALU
The output of the multiply PROM
The BLEG output
A value of 60

These inputs are selected by the signals BCD MUX S3, S2, SI and SO (bits 31-28).
The BLEG output, if selected, bypasses the BCD ALU. The value 60 can be tacked onto a nibble used
for output in order to produce an ASCII number in the numeric format. The output of the BCD multiplexer is enabled to the input multiplexer (EI6, E5, E8, E17, E6, E9, E18) by asserting ENABSIGN
TRAN H (bit 37).

4.5.5 BCD Sign Translation
To effect a necessary translation of the sign nibble in a source or a destination string, the sign nibble is
extracted from a source string or is added to a destination string.
Input sign translation is accomplished by the input sign translator (E50). Inputs 14 and 13 to E50 are
used to distinguish between packed and zoned formats. BLEG 07 H - BLEG 00 H (which contain the
BCD digit and sign) are the other inputs to the translation ROM. The output of the PROM is a BCD
number with bit 7 OFF for a positive number or ON for a negative number.

4-16

The output sign translator PROM (E74) outputs a BCD number with a sign. This output depends on
CIS SIGN H and the numeric or packed format of the instruction. CIS INPUT 12, CIS INPUT 13,
and CIS INPUT 14 are used to determine the format of instruction. The BLEG inputs are used if data
is to be encoded with the sign.
The output of each sign translator is applied to the sign select multiplexer (E6S, ESS). One of these
signals is selected and then enabled to the BCD lines by the signal CIS ENAB SIGN TRAN H.
DETAILED LOGIC DESCRIPTION OF STATUS BITS
(Reference: CS-M7092, pages 8, 9, 10 of 10)
The format of the 16-bit CIS status word is shown in Figure 4-6. Bits (3:0) are the condition codes (N,
Z, V and C) used by the PDP-II for branch testing. The status bits (12:04) are used by the CIS for
internal branching.
4.6

The CIS uses this status word internally and stores it on the stack during suspension. CIS status information other than the condition codes is not available to the user through a register.

BIT
15

BIT
00

~UNUSED--4•.-tI~.-------STATUS B'TS------~.a.tl••-COND'T'ON CODES---i
TK.7235

'Figure 4-6

CIS Status Word

4.6.1 Status Bits
The status bits (12:04) are set by the result of CIS operations or by conditions of the data string. A CIS
operation could set the following bits.
•
•
•
•

Address odd conditions (bits 12: 10)
Sign (status bits 9, 8)
Zero condition (status bits 7:S)
Carry /borrow (status bit 4)

4.6.2

Nonzero Conditions
(Reference: CS-M7092, page 5 of 10)
The zero conditions are set or cleared after a BCD ALU operation. Two signals, CIS BCD 3:0=0 H
and CIS BCD 7:4=0 H, are used to generate the three zero condition bits. These signals monitor the
low- and high-nibble respectively, of the BCD arithmetic ROMs. The negated state of the zero condition bits is used for the status indication. The signal names are therefore referred to as NONZERO and
have three versions:
1.
2.
3.

NONZERO A (bit 7)
NONZERO B (bit 6)
NONZERO C (bit S)

All three status bits may be used, if the status of the source 1, the source 2, and the destination need to
be known. This can occur in three address arithmetic when using an ADD, SUB, MULP or DIVP.

4-17

Each of the NONZERO flip-flops is independently enabled. These signals originate from the M7091
control store and enable the signal CIS CLK H, which latches the NONZERO flip-flops 30 nsec before
the end of the CIS cycle. The enabling signal names are:
1.

2.
3.

ENAB NONZERO A H
ENAB NONZERO B H
ENAB NONZERO C H

These signals are derived from the CON4 field of the control store, bits (20:16).
The nonzero signals, which are latched by 74S74 flip-flops, stay set until a CLEAR NONZERO H
signal is received from the control store or a zero condition is latched. A CLR NONZERO or PROC
INIT signal clears all NONZERO flip-flops.
4.6.3 Carry / Borrow
The carry/borrow (C/B) status bit (bit 4) is set or cleared by a carry-out during a BCD operation. The
carry bit is latched up by EI02 (a 74S74) if the enable signal ENAB C/B H is present. ENAB C/B H
is the ENCB field (bit 0) of the control store. A C/B may also be forced by the control store if CIS
FORCE C/B H is asserted. This signal is derived from the CON4 field of the control store (bits 20:16).
The carryI borrow status bit can be selected from either the high or low nibble. That is C/B OUT H or
C/B 3 H from the BCD ALU will be inputted to the C/B latch. CIS LNIB SEL H (low-nibble select)
selects either C/B H or C/B 3 H and is derived from the CON4 field (bits 20:16). The selection is done
by 4: I mUltiplexer E96.

4.6.4 Sign Bits
Two sign bits are available to store the sign for two source operands. These bits are latched for use in
setting the condition codes during character string instructions, or for CPC address branching.
The two sign bits, CIS SIGN 1 H (status bit 8) and CIS SIGN 2 H (status bit 9), are derived from the
signal CIS OAT SIGN H at E70 pin 9. CIS OAT SIGN H is produced from one of the following
signals, depending upon the data type of the instruction.
CIS OAT SIGN H is set during character instructions, if data bit 15 or 7 on the MBUS is set. This is
the sign bit of either the high byte or the low byte.
CIS OAT SIGN H is set during long integer instructions, if bit 15 (the sign bit) of the MBUS is set.
CIS DAT SIGN H is set during zoned string instructions if bit 6 of the MBUS data is set. The state of
bit 6 represents the difference between a positive or negative number in the zoned format. A byte with
a positive signed number is represented as 0011 xxxx and a byte with a negative signed number is represented as 0111 xxxx, where xxxx is a valid BCD number.
CIS DAT SIGN H is set during packed data instructions if bit 0 of the MBUS data is set. The state of
bit 0 represents the difference between a positive or negative signed number in the packed format. A
positive number with sign is represented as xxxx 1100 while a negative number with sign is xxxx 1101,
where xxxx is a valid BCD number. Notice that the state of bit 0 in the nibble differentiates the positive
from the negative numbers.
DAT TYPE 01 H and OAT TYPE 00 H are the signals that select the correct bit for CIS OAT SIGN
H. Table 4-7 shows their functions.
The SIGN 1 and SIGN 2 flip-flops (enabled by ENAB SIGN I Hand ENAB SIGN 2 H respectively)
are derived from the CON4 field of the control store (bits 20: 16). The SIGN 1 and SIGN 2 latches are
cleared by PROC INIT or by loading a positive sign bit.
4-18

Table 4-7

Sign Coding

Data Type

Sign Bit

DATTypeOl

DatTypeOO

Character String

MBUS 15 or
MBUS07

Long Integer

MBUS 15

Arithmetic Zoned

MBUS06

Arithmetic Packed

MBUSOO

4.6.S Address Odd Conditions
Since CIS data strings can start or stop on odd address boundaries, the determination of whether writing is to a word or byte, is made by the CIS. Three signals are available for determining whether the
sources and/or the destination addresses are odd:
CIS SRC 1 ADR ODD H
CIS SRC 2 ADR ODD H
CIS DST ADR ODD H
Each of these signals monitors the MBUS 00 signal. An odd address condition is set if the address
loaded to the MBUS has bit 0 set. The microcode will test these three signals and branch if at least one
of the indicated conditions is set.

4.6.6 Status Bit Operation With BR Interrupt Pending
A test is made at specific points in the microcode for the presence of a BR interrupt request. A successful test (Le., a BR interrupt is detected) will branch the microcode to a "save state subroutine" that
stores essential information on the stack. One such piece of information is the CIS status word.
The status word is first enabled to the MBUS, then to the AMUX, and finally to the stack. The MBUS
receives the status bits via buffers E 12 (status bits 7:0), and E92 (status bits 15:8). The signal CIS
ENAB CISS L, which enables the status information to the MBUS, is derived from the CON2 field
(bits 27:25) of the control store.

4.6.7 Return From Interrupt
After an interrupt has been serviced and control is returned to the CIS, the CIS must continue from
where it left off. The stack is popped twice after returning from the interrupt, first to load the PC and
then to load the PSW. The instruction then continues as though suspension had not occurred. The PSW
is examined by the CIS mirocode and, if PSW bit 8 is set (indicating that a CIS instruction was suspended), a restore subroutine is called to pop previous information off the stack.
One of the items popped from the stack is the status word, which is placed on the AMUX lines and
enabled to the MBUS via the input multiplexer (EI6, E5, E8, E17, E6, E7, E9, E12). The MBUS
connects to the multiplexers which drive the status latches. The multiplexers used to restore status information are E62, E30 (74S153), E93 (74S157), and E96 (74S153). The MBUS signals (status bits)
are enabled to the latches by CIS SEL CISS L which is derived from the CON2 field of the control
store (bits 27:25). The status word and all pertinent information is restored from the stack thus allowing
continuation of the interrupted instruction.
4-19

4.6.8 Categorizing Instructions To Form N, Z, V, C Bits
(Reference drawing: CS-M7092, page 8 of 10)
The condition codes are formed by first categorizing similar instruction (Table 4-8). Two general categorizing groups exist: character string instructions and arithmetic instructions. Within each group are
subgroups. Specifically, character string instructions are divided into two groups and arithmetic instructions into eight groups. Each subgroup comprises all instructions that output similar condition
codes. Functionally, this grouping takes place in EI00 which is a 256 X 8 PROM. This PROM also
outputs two signals indicating the format of the data type. These signals (DAT TYPE 00 and OAT
TYPE 01) are only used to form the output sign for character instructions.
The categorizing logic is divided into two sections: character string condition codes and arithmetic condition codes. Condition codes for arithmetic instructions are formed by using the four categorizing signals from Eloo and some status bits. The character string condition codes are derived from the 2901A
status bits.

Table 4-8

Instruction Categories
CCCod~

Categorizing
Instruction

High
CCSELL

028

01H

OOH

MOVC,MOVRC,MOVTC,CMPC
MATC,LOCC,SKPC,SCANC,SPAN C,L3 DX,L2Dx

o
o

0
0

ADDy
SUBy
DIVP
MULP
CMPy
ASHy
CVTLy
CVTyL

1
1
I
1
I
1
1
1

0
0
0
1
1

0
1
1
0
0

I
1
0

CVTLy
CVTNP
CVTPN
CVTyL

Data type is long integer.
Data type is ZONED.
Data type is PACKED.
Data type is ZONED or PACKED.
where x = any number in the range 0-7
y = PorN

4-20

1
0

1
0
1
0
1
0
1
0

4.6.9 Arithmetic Condition Codes
The status bits and the categorized group of the instructions, set the arithmetic condition codes (N, Z,
V, C bits). The status bits are formed by the results of the BCD ALU and are as follows:
CIS C/B H
CIS NONZERO A H
CIS NONZERO B H
CIS NONZERO C H
CIS SIGN 2
CIS SIGN 1
These signals, together with the categorizing ROM (EI00) output, address the decimal condition code
ROM (E79), which then outputs the N, Z, V, C bits and a sign bit. The sign bit will be set under the
following sign 1 and sign 2 settings:
Instruction

Condition

ADDx,SUBx
DIVP, MULP
CPMx
ASHx,CVTxx

Sign 2
Sign I XOR Sign 2
Sign not set
Sign I

The condition code settings for each instruction are given in Table 4-9.
4.6.10 Condition Code Output
The condition codes are selected by two dual 4: 1 multiplexers (E62, E30). The inputs to these multiplexers are either the decimal CC decode ROM, character condition codes, or the MBUS.
After the correct input is selected, the output of the multiplexer is stored in the condition code latch
(E 19). The data can then be fed to the PSW via the MBUS and AMUX lines of the CIS.
4.6.11 Character String Condition Codes
The character string condition codes are set by monitoring the status information on the 2901A ALUs.
The 2901 As F = 0 output of either high byte or low byte can set the Z bit. The signal names are CIS
ALU 15:8=0 H, and CIS ALU 7:0=0 H. CIS ALU 15:8=0 H indicates that the high byte is zero;
CIS ALU 7:0=0 H indicates that the low byte is zero.
The carry bit (C) indicates a carry-out of the 2901A, and either the high byte (CIS ALU COUT H) or
low byte (CIS ALU COUT 7) can be selected to obtain the signal. CIS ALU COUT 7 H is generated
by the carry-lookahead chip, E48. CIS ALU COUT 7 H is generated as a separate output by the most
significant nibble of the 2901A, E47.
The negative bit (N) is set if the sign bit of either the low or high byte is set. Two signals (ALU 15 H
and ALU 07 H) from the 2901 A can set the N-bit.
The overflow bit (V) is used only during a MOVC, MOVRC, MOVTC or CMPC instruction. During
other character string instructions the V-bit is zero. The V-bit is set by the simple Boolean expression
found in the Condition Code Setting Table 4-9, V column.

4-21

Table 4-9 Coadition Code Setti.
N

Instruction
MOVC. MOVRC
MOVTC.CMPC

AlU7 or AlU 15

LOCC. SKPC, SCANC,
SPANC, MATCHC

AlUIS

ADDN.ADDP

SIGN2 • NONZEROA

SUBN,SUBP

SIGN2· NONZEROA

DIVP

(SIGN) ¥ SIGN2)' NONZEROA

MUlP

(SIGN I ¥ SIGN2)· NONZEROA

CMPN. CMPP

SIGN) • SIG N2 [C/B' (NONZEROB· C/B)' NONZEROA] +
(CIS, SIGN) + (SIGN I • SIGN2· NONZEROA· C/B)

ASHN, ASHP

SIGN I • NONZEROA

CVTLN.CVTLP
CVTPN.CVTNP

SIGN I • NONZEROA

CVTN L. CVTPL

SIGNI·NONZEROA

¥ - XOR

4-22

ALU <7:0> ==0 or ALU < 15:0> -0

(SIGNt ¥ SIGN2)·
[SIGN2 ¥ (ALUt5+ALU07)]

ALU COUT

ALU<IS:O>-O

NONZEROA

C/B + NONZEROB

NONZEROA

C/B + NONZEROB

o
o

NONZEROA

C/B + NONZEROB + NONZEROC

NONZEROC

NONZEROA

C/B + NONZEROB

<[(SIGN t ¥ SIGN2)· NONZEROA· NONZEROB· C/B1 + 0
[(SIGNt ¥ SIGN2)·(NONZEROA + C/B)]>

NONZEROA

C/B + NONZEROB

NONZEROA

C/B + NONZEROB

o
o

NONZEROA

C/B + NONZEROB

SIGN2 • NONZEROC

¥ -XOR

4-23

CHAPTER 5
MICROCODE

5.1 INTRODUCfION
The KE44-A microcode (control store) consists of 1,000 88-bit words. Each word of the microcode controls an operation or a set of operations within the KE44-A, as well as the selection of the next microword. Initial microword selection, however, is controlled by the op code of the CIS instruction to be
performed. (Refer to Appendix A for a description of these instructions.) When a valid CIS op code
(076 nnn) is received, a microword (specified by the decode of the op code) is addressed, and control of
KD II-Z operation transfers to the KE44-A. The series of operations specified by the microwords contained in the addressed op code routine is then performed. This sequence also includes subroutines
called for by the addressed routine. Upon completion of the tasks called for by the instructions, the
KE44-A is returned to the idle state address (0000) and control of system operation is returned to the
KD II-Z. In this idle state, the KE44-A monitors KD ll-Z operation in order to detect any valid CIS op
code transmitted on the AMUX (15:00) lines.
5.1.1 Design Guideline
DEC STO 168, PDP-II Extended Instructions is the design guideline for the CIS microcode.
5.1.2 Microcode Listing
The contents of the control store are described in a computer listing of definitions used in the instructions. These definitions include a detailed description of each microword broken down by operational
areas (fields), and a definition of the macros (Appendix A) used in the microword instructions.
The microword instructions are listed by routine or subroutine and, in general, appear in their sequence
of occurrence within that category. The listing begins with general (nonroutine-related) microwords, for
example, "CIS idle state".
Each microword address is accompanied in the microcode listing by a description of the operations to
be performed when the microword is implemented. Each description is followed by a listing of the values for each field (given under the number representing the location of the least significant digit (LSD)
for that field). Each entry ends with a to/from listing showing the words that can be entered from a
given word as well as the words from which the given word stemmed.

5.2 THE MICROWORD
The microword contains 88 bits (87:00). These bits are divided into groups called fields and subfields,
which control operations internal to the KE44-A and addresses to the KD l1-Z microstore. Figure 5-1
shows the microword field map.

5-1

87 86 85 84 8382 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
DEFAULT

X X

X X X X
A PORT CISS PW
A3 A2 A1 AO
B3 B2 B1 BO
CIS SP ALU C8

CPC

WRITE

SHFTC ALU DST

I 118 17 16
SHFT
S1
SHFTIN
SHFT SO
SERIAL
SHIFT H

ALU
CIN H

SP HIGH WRITE

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
10 0 0101010
ICONST

CONST SEL S2 H
CONST SEL S1 H
CONST SE L SO H
ENAB SIGN TRAN

DSTTRAN H

010

BMUX J.

I I 1CQN2
010

010

I I

BCDMX3

BCDOP

3 TO B

0
CON

0 010

o 0 0

CON41

32X8

010

o 0
MPC

BCDMX 1

010

ooll}oJ

CONBR2

2 1

OON[Ug

ENAB C/B H
ENA8 CIS H
COND BR 00 H

ENSNIN

COND 8R 01 H

ENSNOU

COND 8R 02 H

BMUXSl H
Ul

COND 8R 03 H

BMUXSO H

COND 8R 04

OPOl H

COND BR 05

OPOO H

COND BR06

BCD MUXSJ H

COND 8R07

BCD MUXS2 H

BTOOH

BCD MUXS1.H

8T01H
BT02 H

BCD MUXSO H
INPUTSEL L

BT03 H

ENAB CPC L

BT04 H

SEL CPC L

NOT USED
ENAB SIGN1 H

ENABL CISS L
SEL CISS L

ENABSIGN2 H

ENAB CONST L

ENAB NON ZERO A H

SEL CONST L

ENAB NON ZE RO B H

ENAB SRC1 ADR H"

ENAB NON ZERO C H

ENAB SRC2 ADR H

FORCE C/8 H

ENAB DST ADR H

L NIB SEL H

CLR NONZERO H

Figure 5-1

CIS Microword Field Map

S.2.1 CPC Field (87:76)
The CISP program counter (CPC) field is the next microword address pointer (00008 through 17778).
The CPC field output can be modified during KE44-A operation by the results of tests called for by the
CONBR! and CONBR2 fields and/or condition codes.
5.2.2 APORT Field (75:72)
The APORT field determines which of the 16 working registers in the 290lA data processor of the
binary data path are to be read by the APORT. The default for this field (APORT = 17) is "register
17".
5.2.3 CISSPW Field (71:70)
The CISP scratch pad write field (CISSPW) enables the writing of a data byte or word to the 2901A
ALU registers via the BPORT. The default for this field (CISSPW == 0) is "disable writing to the
registers" .
5.2.4 ALUCB Bit (69)
The ALU carry/borrow bit (ALUeB) controls the carry/borrow operation for the binary path ALU.
The default for this bit (ALUCB = 1) is "no carry/borrow input".
5.2.5 BPORT Field (68:65)
The BPORT field determines which of the 16 registers in the 2901A binary data path are to be written
to and/or read from. The default for this field (BPORT = 17) is "register 17".
5.2.6 SHFfIN Bit (64)
The shifted-in bit (SHFTIN) controls the value (lor 0) of data shifted in. The default for this field
(SHFTIN = 0) is "shift in zero".
5.2.7 SHFfC Field (63:62)
The shift control field (SHFTC) controls the direction of shift for data being loaded into the binary
path RAM and/or Q-register. The default for this field (SHFTC = 0) is "left shift one bit in RAM
regist~r if _enabled by ALUDST (61:59)".
5.2.8 ALUDST Field (61:59)
The ALU destination field (ALUDST) controls the form of the 290lA ALU output in the binary data
path (Le., whether the output is RAM data or calculated output) and the data input to the BPORT and
the Q-register. The default for this field (ALUDST = 3) is "read the calculated output to the Youtput
and back to the BPORT".
5.2.9 ALUITN Field (58:56)
The ALU function field (ALUFTN) controls the arithmetic/logical operation to be performed by the
ALU of the 2901A data processor in the binary data: path. The default for this field (ALUFTN = 3) is
~~selects a logical OR operation of the ALU input". ALU inputs are selected by the ALU SRC field.
S.2.10 ALUSRC Field (55:53)
The ALU source field (ALUSRC) controls the selection of data sources as inputs to the binary path
ALU. The default for this field (ALUSRC = 7) is "selects the direct data for the R input and zero for
the S input to the ALU".
5.2.11 SALUI Bit (52)
The select ALU input bit (SALUI) controls the input multiplexer selection for the binary path ALU
(2901A) direct path (D) input. The default for this bit (SALUI = 0) is "transfer the contents of the
MBUS to the D input".

5-3

5.2.12 INEN Bit (51)
The input enable bit (INEN) is the enable/inhibit control for the tri-state output of the eight input
multiplexers. The default for this bit (lNEN = 0) is "inhibit output". When the input multiplexer is
enabled, data is put onto the MBUS.
5.2.13 SWAP Field (50:49)
The SWAP field controls the swapping of bytes in a word or in a data string. The swapping operation is
performed in the reading of data from the input multiplexer. The default for this field (SWAP = 0) is
"inhibit the swap of byte data".
5.2.14 ENIB Bit (48)
The enable input buffer bit (ENIB) is the enable/inhibit control for the tri-state buffers, the AMUX
input line and the ALU Y output lines. The default for this field (ENIB = 1) is "enable ALU Y outputs" (AMUX inputs inhibited).
5.2.15 ENOB Bit (47)
The enable output buffer bit (ENOB) is the enable/inhibit control for the tri-state output of the output
multiplexer. When set, this bit enables data from the MBUS to the AMUX lines. The default for this
bit (ENOB = 0) is "inhibit output multiplexer output".
5.2.16 LBYTE BIT (46)
_
The low byte enable bit (LBYTE) controls the location (high or low byte) of the condition codes. The
default for this bit (LBYTE = 0) is "load the condition codes into the high byte".
5.2.17 CONI Field (45:41)
The control I field (CONI) controls the selection of internal CIS data for loading onto the MBUS. The
default for this field (CONI = 0) is "inhibit loading data to MBUS".
5.2.18 CONST Field (40:38)
The constant field (CONST) selects which of the eight constants from the constants ROM is enabled as
the input to the constant multiplexer. The default for this field (CONST = 0) is "enable the constant
7".
5.2.19 ENSNIN Bit (37)
The enable sign input bit (ENSNIN) enables/inhibits the translation of the input sign data. The
default for this bit (ENSNIN = 0) is "inhibit sign translation".
5.2.20 ENSNOU Bit (36)
The enable sign output bit (ENSNOU) enables/inhibits the translation of the output sign data. The
default for this bit (ENSNOU = 0) is "inhibit sign translation".
5.2.21 BMUX Field (35:34)
The B multiplexer field (BMUX) controls the selection of data to be read from the BCD shift multiplexer and from the shift nibble register. The default for this field (BMUX = 0) is "read the contents
of the B register to the BCD shift multiplexer unshifted".
5.2.22 BCOOP Field (33:32)
The BCD operation field (BCOOP) controls the operations to be performed by the BCD ALU. The
default for this field (BCOOP) is "use the decode of the BCD operation PROM to control the BCD
ALU".

5-4

5.2.23 BCDMX3 Field (31:30)
The BCD multiplexer 3 field (BCDMX3) controls the selection of the output of the high-nibble multiplexer data to the input multiplexer. The default for this field (BCDMX3 = 0) is "read the output of
the BCD ALU unchanged".
5.2.24 BCDMXl Field (29:28)
The BCD multiplexer 1 field (BCDMXI) controls the selection of the low-nibble multiplexer data to
the input multiplexer. The default for this field (BCDMX = 0) is "read the BCD ALU output unchanged".
5.2.25 CON2 Field (27:25)
The control 2 field (CON2) comprises the enabling signals for control of the data input to the MBUS.
This field works in conjunction with CON 1. The default for this field (CON2 = 0) is "inhibit all enabling signals (no data to the MBUS)". The three bits of this field are converted to eight signal lines on
the M7091 control store module.
5.2.26 CON3 Field (24:21)
The control 3 field (CON3) comprises the enabling signals for the latching of odd address conditions in
the source and destination. The default for this field (CON3 = 0) is "disable all enabling".
5.2.27 CON4 Field (20:16)
The control 4 field (CON4) is a series of enabling signals for CIS operations. The five bits of this field
are decoded by the M7091 control store module into seven control signals. The default for this field
(CON4 = 0) is "disable all enabling".
5.2.18 MPC Field (15: to)
The microprogram counter field (MPC) comprises control signals that go to the KD l1-Z. These signals
are read from MPC decode to the· MPC line (8:0). The resulting decode of the MPC field is in the
range from 7408 to 7768. The default for this field (MPC = 1) is 741.
5.2.29 CONBR2 Field (9:6)
The conditional branch 2 field (CONBR2) is used in conjunction with the condition codes, to generate
branch conditions in the CPC\2:0+ field. The default for this field (CONBR2 = 0) is "inhibit all
conditioned branches".
5.2.30 CONBRI Field (S:2)
The conditional branch 1 field (CONBRl) is used by the FPLA to generate branch signals for CPC
(7:0). The default for this field (CONBRI = 0) is "inhibit all branch conditions".
5.2.31

ENeIS Bit <1}

The enable CIS bit (ENCIS) controls the CIS operational mode. When ENCIS = 0, the KD ll-Z is in
control. When ENCIS = 1, the KE44-A controls the operation; i.e., a CIS instruction has been decoded.

5.2.32 ENCB Bit (O)
This bit controls the loading of the carry/borrow bit to the MBUS and is used in BCD operations.

5.3 READING THE MICROCODE
Reading the microcode listing involves a series of steps. These steps vary according to the contents of
the microword and the familiarity of the user with the appropriate tools. The tools available include the
field definitions, the sets of macro-definitions, the KDII-Z operations, and the microword listing with
its descriptions.

5-5

5.3.1 The Field Definitions
Figure 5-2 is a sample page of microcode field definitions. Note that each field is defined by: 1) a
symbol, 2) its position and range in the microword, and 3) its default value~
SYMBOL/ = (n:nw), default = m
Mlcroflow al(0') 12141108 26-Mar-1981 Cll"4.FL~ 4.-CII
Clll.MCR
1
3
3

,R10L
.TOC

,TME D!rINITlo~ or THE WORD IS -IGH! TO LEFT

-'4 CII MICRownRD DEFINITIONM"

5
6

'7
8
9
HJ
11

12
1J

15
16
11
18
19
2'
31
22
2J
24
35

36
3'7
28
29
3.
31
32
3J
34

CPC/ a C87176>,.NEXTaDDR!SI
8K2a ..
81(481
APORT/aC1SI'72>,.DE'AULT817
IC"a0(11
ICla01
Je2a'2
le3a8]
.c.a.,4
leSa"S
K6a"6
le'7ae1
lelea1e
Kltal1
K12a13
Je13al3
Je14at4
K1S815
1(16816
1(1'7.11
CIISPW/.C'71110>,.DErAULTa,
SPNw8e
H8YT!a1
L8YTEa2
IPW8J
aLUC8/aC69>,.DEFAULTal
NOCA,a1
YESCARae
APORT/ac6816S>,.DEFAULTa17

IU,a""

36
3'7
3'
39

52
5]
54
55

IENaBL!S 2901 WRIT! O~TtON
.DISABLE WAITE INTO RlM
IWRITE HIGH IYTE AND LOW BYTI
IW~lTE O~LY LOW BYTE
IwRITE INTO RAM
IcaR't 8lt Ir eONTROL I?ORI
INO CARRY/BORROW I.CARRy IN or 1
,CONTROLS REG rOR IPO.! ,IAD/WRITE

K18~1

1(2.'2
K38,,3
K4.04
IC5.,,5
K6a'6
IC1a.,1

41
42
4]
44
45
46
4'7
48
49
5.

.CONTaINS ADDR or NEXT MtCROWORD
.FIRIT 2K
ROMS
.SECOND 2K or ROMS
.wHICH REG TO BE READ IV APORT

KlI'.U,

Kl1al1
K12a12
IC13a13
1C14at4
1C158t5
1(16a16

1(1'7a\7
SHrTIN/aC64>,.DE'AULT.'
ZE'O."
ONEat
~H'TC/.(63'62>,.D£'AULT.p

L'T16a ..

Figure 5-2

.81T TO ~E SKIrTED IN BY SHIrT COMMANDS
.SHI'T Itt a 1£1'0
,sMI'T IN A I
,CONTROLS SHt". I' a SHIF! OCCURS
.LEFT SHIr' b, ONE 8Xr "SlMG 16 81T 1'EG

Sample Page of Microcode Field Definitions
5-6

The symbol is a signal name or mnemonic followed by a slash (/) followed by an equal sign (=).
The bracketed numbers(s) «n:nw» show the location and range of the field in the 88-bit microword. N
is the MSD and NW is the LSD of the field with the microword. The default is the value (m) to which
the field is set if no value is given for that field in a given microword. This entry is followed by a descriptive statement of the field.
The field definition entry is followed by a series of entries defining the resulting action or value for the
bit combinations within the field.

5.3.2 The Microinstruction
Figure 5-3 is a sample page of microinstructions. Each microinstruction in the listing is an entry in the
control store. The microwords are grouped by routine or subroutine, and each group is identified by a
table of content (TOC) entry. The comment is repeated at the top of each page containing a given
routine or subroutine.
Each microword entry begins with an identifying label. The label, an identifying symbol for the microword, is used by. the other microwords to call (go to) that address. If more than one label is given, any of
these can be used as a call. Each label is followed by a colon, e.g., 0000: and SERV: (Figure 5-3).
A label may be followed by a descriptive statement appearing on the same line. The statement identifies a specific detail (i.e., why it was called or what it will do) related to that word. The descriptive
statement is separated from the label by two semicolons.
The line following the label contains macrostatements identifying the operations performed as a result
of asserting the microword. Each macrostatement line may also contain a short descriptive statement
about macrooperation. The descriptive statement is separated from the macro by a semicolon. Macro
entries are followed by the address of the microword, a six digit octal number in brackets, e.g.,
[000000] (Figure 5-3).
The microword address is followed by two sets of 3 lines; each set gives, for example, the field name
(epC), the LSD of the field (76), and the bit value for that field (0000).
For the idle state (address 0000) the next address is 0000. The KE44-A repeats this operation until a
valid CIS op code (076 nnn) is received.
The contents of the microword entry is followed by a list of to/from entries (e.g., from: +- U [00035]).
The value 892, which follows this number, is the cross-reference (CREF) number for microword
000351. The "from" entries show the origin of this microword. The "jump" form (not shown in Figure
5-3), is for the next address only. When a branch condition exists, all possible addresses and the condition for selection are given. In the idle state the next word address is determined by the decode of the
nnn part of the 076 nnn op code.

5.3.3 Reading the Macrodefinitions
Figure 5-4 is a sample page of macrodefinitions. The macrodefinitions are grouped by functions and
each group is identified by a table of contents (TOC) entry which defines the function of the macros.
Under each TOC entry are two columns. The first column is the macrocode listing; the second column
is a definition of the macro. In some cases, a macro may have already been defined at a previous point
in the listing, e.g., TEMP-2901 (Figure 5-4).
5-7

Nieroflow 'Ace.) 121411MI 26.M_r.l'l, ~11,p4.'L~ 44.els
Cla'.MCR
IRANCH M1C~O
6.6
6.7
6.8
6.9
6"

"U.~.C1LL1

'LOAD-CPC'
NO.WRltE?
·CnN~R"~OWRITr.·
tR'I'
·CON~Pl/tR"·
tR'b'
·C9N~Rl/tR'6·
NIG.lND.OR.SIRVICE'
·CONIR2/p,eCN,e~N"~DCPC·
aUI.oP'
·CON8R2/TENCO~·

611
612

6tl
6it
615

.tOC

""'1
atRVI" aERVICE LOOP, MlttlNe '0 EXECUTE CII INaTR

61b
617
611

619

62e

re·.·.·l
c.c

ENCla/,14,
AWfJX.fO.Mlua,
cua,w/l'.,
M.C/IEI",
C'C/IERV

44 '0 CONTROL THTNGS

.w..

•

c-c.c--

n
n
n
12

n
n
u

n
u
n
u

U
J2

'"18 !N08 LIYTE CONl COl.' ENININ II'NOU
1,0RT C111." ALUCI B.ORt aMrtlN ~HrtC ALUDST 'LurTN ALuapc SlLUI INEH
51
.,
••
.7
46
It
'7
36
52
72
10
69
65
62
!9
!6
53
1
~
,
e
e Ie
e
e
•
••••
I'
I
1
t7
~
~
3
J
7
INUX 8CDO. ICD~Xl ICO~X' CON2 CON! CON4 MPC CON~R2 cnNPRl ENeIS ENCe
e
J2
le
28
25
2t
16 1.
6
2
14
e
e
~
ft
e
e'
A~
e~
~~
~~
"
RETURN 0lOR LARG!M THA~ 77, INVALID, IXIT
'ROMI c •• U
[e •• l'1'
~92 ~STe)~. CCN-"
'ROM,
U
[~el""
lJ07 ENTR2e2
FROMI
U
,e'let6)
1'.5 tNTR)9
'ROMI
U
l8et24"
1451 EXtTtl. RF,TURN TO CALLER rORM tXIT aueR O~ A!I'O~E rRO~ .I,VICE TAAP
rROMI c •• U
(e.ll.6,
2211 L000J2, crM-tA"-l,CCI.', EXIT 'RO~ CO~M.ND
IERVICE/IRDECODI
U
l.eel'61
2174 MVCAll. MOVC, ~OVTC, MOVRC COM~ANDS
atRVICE/IRDECODI
U
(eee1571
2221 ICNe.0, Tqr SCAN/IP1N/lllPI LOCATE CH1R1CTER CoMMAID
aERVl~E/l'D!CODI
u
(.ee16e]
2416 cpee01, TU! COMPARE aND ~lTCH CHAPACTEP COMMINO
IIRVICE/IRD!COPI
U
[.e'161)
2024 LDOWA1, LftlD 2 DESCRIPTOR OR LOAD J DESCRIPTOR COM~ANo
I!RVICE/IIlDICODI
U
l.e'162)
len '.000'2, LnlD 2 DISCRIPTOR OR LOAD ) DEIR COMM1ND 81110 ON PI
ItRVICE/I~DECODI
._) U
,Ae'16l1
2'4' LoDe.). tnlD 2· DEsCR OR LOAD 3 oEICR CO~MA"D IAIED ON P2
I!RVICE/IIlDICODi
U
"'1164'
~14' LoDe •• , Lnln 2 D!ICR OR LOID J DIICR COMMAND 81lED ON Pl
U
(011165)
2056 LDDee5, LnAD 2 OESCP OP LO~o 3 DEICR COMMAND tlSEo ON R.
S!RVICE/IRDtCODI
(.eI166,
2e64 LoDe'" tOlD 2 oEICR OP LOAD 1 oESCR COMMAND BASID ON R5
IIRVICE/IPDICooi •• > U
8!AVICE/IIlD!CODI •• ) U
(188167)
2078 LoDee7, Lnao 2 DEICR OR LOAD 1 DEICR COMM1ND BIIED ON R6
IIRVICE/I~D!C~DJ •• ) U
[Ae'l")
2t81 LDDe12. LnaD 2 oEICA Oil LOAD 1 DraCR COMMlND BlllD ON PC
SERVICE/IRDECODI
U
,e.e1711
1221 llCeel. f~E lOOP, lOON, SUBP, IUSN, CM.N, IND CM" COMMANDS
IEPVICE/I'D!CODI
U
['1'1131
4698 PNLtftl, C~NVERT P1ClED, NUMERIC TO LONG COMMAND
I!AVICI/I~DIC9D;
U
""1'1)
5279 V,Nxxe, T~E CO~V'RT PaCJID fO NU~£RIC CO~MA~D
,.elt1.1
5495 VNPXXI. THE CO~VERt NUM~RtC TO PAelED COMMAND
IERVICI/IRD!CODI •• ) U
S!PVICE/tRDtCODI •• > U
[A,81'"
4191 ASHee1, 1M[ )RltH~EtIC sHIrT COMMAND, P1CKED AND NUMERIC
I!RVICE/l~DICODi
U
'le'11b)
5731 LNPI'l, C~NvrRT LONG TO NUMERIC, P1C~ED COMMaNDa
IERVICE/IPDICODI --) U
,ee•• 71J
b~2' Dv.eel. fPI MULTIPLy PACKED, lND DIVIDE 'lCK!D COMMAIoS
76

V'I
I
00

Il~L~w

.->
-->
-->
-->

-->

-->
-->

.->
-->
.->
.->

Figure 5-3 Sample Page of Microinstructions

116
317
lt8

119
128
121
123
121
124
125
326
127
128

329

III

'.TOc:

IMACROI rop TEMPORIRY RESULTS IN 2tll-Rn WRITE TO aCR1TCH'P1D(8POR!) NOR TO !HI Mlua'
'I'£fC'':'290t

T_O'(J~R$_A'18rl

T.9'tl,RLAtlQ
T.O'(I~Rs.eQ

.0' [) .

-ALUDIT/LOAD82,rrlip./IPNW,INIB/ENIINI
'ttM,.29fJt,ALusaC/18,ALUFT.,.t,A.ORf/,2,IPOIT/.1I
'TtMP_29fJl,lLUS~C/~Q,ALUrTN/'I,lPORT/'2'
-T!M'.29~1,ALUSRC/,00,ALurTN/.tl
.

'TIMP.2901,ALUI_C/,.I,ALur'N/.t,IPOR".a '
T
RS.fJ8 r 1
T.OP[J,RS.fJ,rJ
~TIMP_29'1,lLua_C/.el,ILurTN/.t,APORT/'21
"!M'_2gel,ALUI~C/OA,lLU'TN/'I,IALUI/'2,APOR"'JI
T.O'fJ,Rs.O"1rl
T.O,tJ.RS.D[lQ
'T'MP.2,el,ALpS~~/DQ,ALU'T·"1,aALUI/'2·
T.A[1
·T.0,[R.OR.SJ.R&rIA t.1J'
T.All.MINUS.!
".O'[I.MINUI,R'~R ••elt'IJI
T.All .MINua.ltt]
"_OPtR.NINU •• '1.RI~['118C'21,lLUeI/Yllel.·
T.AtJ.M1Nua.Btl.MIIUI.1 'T.o'rR.MJHu •• s,.~'-lt'lJ8C'2J'
',.O.,I.MINUI.R1.RI_lc.aJat.1J,lLUel/yEIClRI
T.ln .MI"us.in

Figure 5-4 Sample Page of Macrodefinitions

5.4 THE CIS MICROCODE INSTRUcnONS
Each CIS instruction uses a group of words in the microstore. The number of words may be as few as in
the L2Dn instruction or as many as in the DIVP instruction. This group of words (routine) may be
completely self-contained or, when necessary, may call other routines or subroutines.
All instructions other than those for the L2Dn and L3Dn have a register and an in-line form. A large
percentage of the microwords in the register form of the instruction are used by the in-line form.
Since all instructions except L2Dn and L3Dn (Appendix A) are suspendable, they have mUltiple start
and resume or restart microword entry points. After suspension a "restore from interrupt" subroutine is
executed to restore the instruction data so that the instruction can be completed.
Each microword in the KE44-A instruction set addresses a word in the KDII-Z microstore. To fully
interpret the action of the KE44-A microword requires reading the word addressed in the KD ll-Z.
At the end of each CIS instruction the KE44-A is returned to the idle loop.

5-10

CHAPTER 6
INSTALLATION AND CHECKOUT

6.1 INSTALLATION
The two KE44-A modules plug into a dedicated 14-slot processor backplane. The M7091 control store
module plugs into sections C-F of slot 1; the M7092 data path module plugs into slot 2 (Figure 6-1).
The M7091 module has no jumpers or switches for use in the field. The M7092 module, however, has
one toggle switch (SI) whose lever is set toward the left (toward the center of the module) for normal
operation (Figure 6-2).

NOTE
The lever of switch S 1 is set to the right during manufacturing test only.

ROWS

SLOTS

A
M7090 {KDll·Z/CIMI

M7091

(KE44-A)

M7092

(KE44-AI

M7093

(FP1'-F)

M7094

(KD11-Z/DATA PATH)

M7095

(KD11-Z/CONTROL)

M7096

(KD11-Z/MFMI

M7097

(CACHE)

M7098

(KD 11-Z/UB I)

M8722

(MS11-M)

M8722

(MSll-M)

M8722

(MS11-M)

M8722

13
14

FRONT

(MS11-MI
SPC

M9302. M9202. BCll-A

SPC

NOTES:
1. A G 727. G7270 CARD IS REQUIRED IN ROW 0 OF ANY UNUSED SPC SLOT TO
PROVIDE BUS GRANT CONTINUITY.
2. A G7273 CARD IS REQUIRED IN ROW C AND 0 OF ANY UNUSED SPC SLOT TO
PROVIDE BUS GRANT CONTINUITY.
3. MODULES ARE INSERTED WITH COMPONENT SIDE TOWARD RIGHT SIDE OF
BACKPLANE.
TK~O

Figure 6-1

Module Placement in Processor Backplane

6-1

o
SWITCH HANDLE
MUST BE TO THE
LEFT FOR NORMAL
OPERATION

M7092

A
TK-4254

Figure 6-2

KE44-A Data Path/Logic Module, M7092

6.2 CHECKOUT
After installation, the KE44-A is checked out by running diagnostic CZKEEA (PDP-Ii CIS Instruction Exerciser). It tests all CIS instructions in both register and in-line modes. Each instruction is tested
under the following conditions.
•
•
•
•
•
•

Using all combinations of operand data types
In each of three processor modes (user, supervisor and kernel)
With memory management enabled/disabled
With D-space enabled/disabled
In an interrupt environment
For many cases of string length, string address, and string data

6-2

CHAPTER 7
MAINTENANCE

7.1 GENERAL
This chapter describes the use of the CZKEEA diagnostic program and the ASCII programmer's console in the maintenance of the KE44-A commercial instruction set option.
7.2 KE44-A DIAGNOSTICS
The CZKEEA is the only field diagnostic program available for the validation and diagnosis of the
KE44-A. However, since the KDII-Z data path is used extensively in executing CIS instructions, CPU
tests should be run prior to running CIS diagnostics if there is any doubt about the operational status of
the CPU. However, successful running of the CPU tests does not rule out the possibility that a KDI1-Z
failure may cause only the CIS instructions to fail.
7.2.1 CZKEEA Program Abstract
The CIS instruction exerciser tests all CIS instructions in both register and in-line modes. Each instruction is tested:
•
•
•
•
•
•

Using all combinations of operand data types
In each of the three possible processor modes (user, supervisor, and kernel)
With memory management enabled/disabled
With D-space enabled/disabled
In an interrupt environment
For many cases of string length, string address and string data.

7.2.2 Program Starting Procedure
The normal program starting address is 200. An optional starting address (204) provides for user selection of test instructions and control over the test environment. Another optional starting address (210)
provides a quick-verify mode tailored to the type of processor under test. This mode has a run time of
less than five minutes per pass and provides a fair level of microcode coverage (>80%).
7.2.2.1 Starting Address 200 - When the diagnostic CZKEEA is started at its normal starting address
of 200, the execution (approximately 30 minutes on the PDP-l1/44) of all tabled test cases for all instructions is followed by an "end-of-pass" indication. Testing then proceeds in a random mode until the
operator terminates program execution.
CIS instruction interruptability will automatically be exercised if the system under test has either a
line-time clock (KW11-L type) or a programmable real-time clock (KWII-P). The program uses the
KWI1-P at a frequency of 100 kHz if both clocks exist.
Processor mode (kernel, supervisor, user) is selected randomly prior to the execution of each test case in
the CIS instructions. Memory management is enabled with the D-space enable/disable state selected
randomly prior to each test case. Mode is switched to the test mode and memory management is turned
on just prior to execution of the CIS instruction under test. During interrupt service, and immediately
following the completion of the CIS instruction execution, the mode is switched back to kernel and
memory management is shut off.
7-1

Tabled test cases are exhausted for any given instruction before proceeding to test the next CIS instruction. At the start of each new instruction in nonrandom mode, a message identifying the CIS instruction
under test is displayed as a progress indicator. The following list gives the order in which instructions
are tested in nonrandom mode, and the approximate number of tests executed for each instruction.
Instruction

Number of Tests

L2D
L3D
MOVC
LOCC
CMPC
MOVRC
MOVTC
SKPC
MATC
SCANC
SPANC
CVTPN
CVTNP
CVTLP
CVTLN
CVTPL
CVTNL
ADDP
ADDN
SUBP
SUBN
CMPP
CMPN
ASHP
ASHN
MULP
DIVP

8
8
354
36
362
354
354
30
904
126
126
226
568
170
323
53
99
1970
3872
1970
3746
502
1089
1972
3872
1993
1973

After being started at location 200, the program should respond as follows:
CZKEEAO PDP-II CIS instruction exerciser
Inst under test will be displayed ...... .
Pass time: II/XX approx. XX min
L2DO Inst Ct: XX XXXXX

DIVP Inst Ct: XX XXXXX
End of pass (execution of tabled test cases complete)
Entering random test mode
No further end of pass messages will be issued
Random # generator seed constants will be printed
Every 2000 CIS instruction tests
Random # generator seed XXXXXX XXXXXX XXXXXX

(Until program execution is terminated by user)
7-2

A Control (1\ T) command entered at any time will cause the program to display the instruction under
test and the current instruction count.
The instruction count displayed at the start of testing for each instruction is cumulative from the first
L2DO CIS instruction tested. The lower five digit count gets incremented once per executed CIS instruction test and counts from 0 to 65,535 (decimal). The upper two digit count gets incremented once
per 65,535 tests. The instruction count is zeroed at the start of random mode testing. Control T must be
used to display the instruction count in random mode.
7.2.2.2 Starting Address 204 - If the CZEEKA program is at address 204, the operator is required to
respond to questions relating to the selection of instructions for test, test mode, and test environment.
After being started at location 204, the program should respond as follows:
CZKEEAO PDP-II CIS instruction exerciser
Test interruptability of CIS instructions (Y or N)?
Random exercise mode (Y or N)?
Enter instruction to test (All)
If the user answers yes (Y) to the interruptability question, the program will prompt for the selection of
an interrupt source (e.g., the line-time clock (LTC); KWII-P at 100 kHz; KWII-P at 10 kHz; or
KWII-P with external I-MHz oscillator). If the LTC is selected, the program controls interrupt timing
to assure that most CIS instructions are interrupted once. If the KWII-P with a I-MHz external oscillator is selected, each CIS instruction will be interrupted and forced to suspend execution at all possible service exit points.

If either the KWII-P at 100 kHz or the KWII-P with external I-MHz oscillator is selected, the program will ask whether or not to allow an interrupt during the CIS instruction DIVP (state disturbing
instruction) normally executed within the KW II-P interrupt service routine.
If the user answers yes (Y) to the random exercise mode question, then the memory management test
state, the processor test mode, test operands and string data for each CIS instruction test will be derived using a- random number generator. A no (N) answer will cause execution of CIS instruction tests
with all test operands and string data provided from program input and parameter tables. Following a
(N) response, the program will prompt for processor test mode (kernel, supervisor, user) and memory
management test state (off when D space is enabled, or on when D space is disabled).
The last question enables the user to select one or all CIS instructions for test. To select a single instruction for test, the mnemonic for the desired instruction is entered from the instruction list. The same
question is repeated if the instruction is incorrectly entered. To select all CIS instructions for test (the
default case) the operator simply responds with a carriage return.
If the random mode question is answered yes (Y) and the instruction(s) for test is/are answered by a
(CR) indicating ~ll, the actual instruction under test at any given point on the procedure is selected at
random.
7.2.2.3 Starting Address 210 - If the diagnostic run is started at address 210, a quick verify (QV) pass
provides a fair (more than 80 percent) level of microcode coverage in less than five minutes per pass.
This QV mode results in execution of a subset of the tabled test cases. The subset has been verified to
provide at least the desired 80 percent level of coverage. Note that some CIS instructions may not be
executed at all in QV mode, because it has been determined that, due to common routines within the
microcode implementation, it is possible to get the desired 80 percent coverage without exercising all
instructions.
7-3

The instruction counts listed above under the normal run mode (starting address 200) do not apply in
QV mode.
CIS instruction interruptability is exercised provided that the system under test has either a line-time
clock or a KWII-P programmable real-time clock.
Processor test mode (kernel, supervisor, user) and memory management test state are selected randomly as in the Hstarting address = 200" section above.
After being started at location 210, the program should respond as follows:
CZKEEAO PDP-II CIS instruction exerciser
Quick verify pass time: less than 5 minutes
L2DO Inst CT: XX XXXXX

DIVP Inst CT: XX XXXXX
End of quick verify pass
Random mode exercising is not invoked during a quick verify pass.

7.2.3 Error Information
If the computer halts without an error display, the following locations should be examined to determine
information about the failing test.
TINST - CIS instruction under test
TRO - TR6 - CIS instruction operands (lengths, addresses, etc.)
The information displayed upon detection of an error describes the complete environment of the failure.
All instruction errors are displayed in one format. The format has slight variations to account for differences between character and decimal string instruction. Continuing the program from a trap will provide the user with a complete error printout.

7.2.4 Program Options
The following control characters are recognized by the exerciser during test execution:
CNTL T - Display instruction under test and test number.
CNTL C - Restart exerciser (recognized only if program was started at 204.)
CNTL D - Display all test case operands and results prior to each CIS instruction test.
CNTL E - Display all test case operands and results prior to each CIS instruction test. Query for
continue.
CNTL N -Cancel prior CNTL D or CNTL E request.
CNTL 0 - Control over progress indication printout (i.e. INST and instruction CNT; random
number generator seed; ON - OFF toggle).

7.2.5 Program Execution Times
For the PDP-I 1/44, first pass run time (tabled test cases only) is approximately 30 minutes.
After the first pass, the program enters random test mode and executes randomly generated test cases
indefinitely.
In quick verify (QV) mode, pass time is less than five minutes.

7-4

7.3 ASCII PROGRAMMER CONSOLE
The normal maintenance features provided by the programmer console for use in debugging and diagnosing the KDII-Z processor are directly extendable to the KE44-A CIS option. These features include:
•
•
•
•

The console functions of examining and depositing data into the memory and general registers
Single-instruction stepping
Console maintenance features of single microinstruction stepping
The displaying of MPC lines, UNIBUS data, CIS data and the contents of the machine dependent register.

The console displays MPC 0-10 L if the proper command is selected at the programmer console. Thus,
single microstepping of the machine through the CIS microcode is possible.
A change in the KDII-Z processor (from its KDII-E predecessor) enables the AMUX lines onto the
UNIBUS data lines.

NOTE
Refer to the PDP-Il/44 Serial Console Specification for other details of console use.

7-5

NOTE
Appendix A bas been duplicated directly from
DECSTDI68-PDP-ll
Extended
Instructions.
Paragrapbs S.13 through S.IS have been removed as
they do not pertain to the KE44.

APPENDIX A
EXTENDED-INSTRUcnON DEFINITIONS
5.1

ADON / ADOP / ADONI / ADOPI - Add Decimal

Format:
15

320

9 8

ADON

076

AOOP

076

ADONI

076

15
src1.dscr.ptr
.src2 .dscr • ptr
dst.dscr.ptr

ADOPI

076

srcl.dscr.ptr
src2.dscr.ptr
dst.dscr.ptr
Operation:
dst <- src2 + srcl
Condition Codes:
N:
Z:
V:
C:

set if dst<0; cleared otherwise
set if dst=0; cleared otherwise
set if dst can not contain all significant digits of the
result; cleared otherwise
cleared

Suspendability:
This instruction is potentially suspendable.
A-I

Description:
Srcl is added to src2, and the result is stored in the destination
string.
The condition codes reflect the value stored in the
destination string, and whether all significant digits were
stored.
Register Form - ADON and ADDP
When the instruction starts, the operands must have been placed in
the general registers. The first source descriptor is placed in
Re-Rl, the second source descr iptor is placed in R2-R3, and the
destination descriptor is placed in R4-R5:
15
Re
srcl.dscr
Rl
R2
src2.dscr
R3

dst.dscr

---------------------------------~-

When the instruction is completed, the source descriptor registers
are cleared:
15
R0

Rl
R2
R3

o
o

R4
RS

dst.dscr

A-2

In-line Form - ADONI and ADDPI
Each word address pointer which follows the opcode word in the
instruction stream refers to a two word decimal string descriptor.
R0-R6 are unchanged when the instruction is completed.
Formal Description:
TBS;
Examples:

Three Address Add - Register Form
MOV
SRC 1. DSCR, RS
MOV
SRCl.DSCR+2,Rl
MOV
SRC2.DSCR,R2
MOV
SRC2.DSCR+2,R3
MOV
DST. DSCR, R4
MOV
DST.DSCR+2,R5
ADDN / ADOP
OVERFLOW
BVS
BLT
NEGATIVE
EQUAL
BEQ
BGT
GREATER

2nd source descriptor
destination descriptor
add
check for error
negative destination
zero destination
positive destination

Three Address Add - In-line Form
ADONI /
.WORD
.WORD
.WORD
BVS
BLT
BEQ
BGT

1st source descriptor

ADOPI
SRCl.DSCR.PTR
SRC2.DSCR.PTR
OST.OSCR.PTR
OVERFLOW
NEGATIVE
EQUAL
GREATER

add
ptr to srcl descriptor
ptr to src2 descriptor
ptr to dst descriptor
check for error
negative destination
zero destination
positive destination

Two Address Add - Register Form
MOV
SRC.OSCR,RS
MOV
SRC. DSCR+2, Rl
MOV
OST.DSCR,R2
MOV
DST. DSCR+2, R3
MOV
R2,R4
MOV
R3,RS
ADDN / AOOP
BVS
OVERFLOW
NEGATIVE
BLT
BEQ
EQUAL
BGT
GREATER

source descriptor
destination descriptor
duplicate destination
add
check for error
negative destination
zero destination
positive destination

A-3

Two Address Add - In-Line Form
ADDNI /
•WORD
•WORD
•WORD
BVS
BLT
BEQ
BGT

ADOPI
SRC.DSCR.PTR
DST.DSCR.PTR
DST.DSCR.PTR
OVERFLOW
NEGATIVE
EQUAL
GREATER

add
ptr to src descriptor
ptr to dst descriptor
ptr to dst descriptor
check for error
negative destination
zero destination
positive destination

Notes:
1.

The operation of these instructions is unaffected by any
overlap of the source strings provided that each source string
is a valid representation of the specified data type.

Source strings may overlap the destination string only if all
corresponding digits of the strings are in coincident bytes in
memory.

A-4

5.2

ASHN / ASHP / ASHN! / ASHP! - Arithmetic Shift Decimal

Format:
15

321

9 8

ASSN

076

ASHP

076

ASHN!

076

src.dscr.ptr
dst.dscr.ptr
shift.dscr

ASHP!

076

src.dscr.ptr
dst.dscr.ptr
shift.dscr
Operation:
dst <- src * (10 ** shift count)
Condition Codes:
N:
Z:
V:
C:

set if dst<O; cleared otherwise
set if dst=O: cleared otherwise
set if dst can not contain all significant digits of the
result; cleared otherwise
cleared

Suspendability:
This instruction is potentially suspendable.

A-5

Description:
The dec imal number spec if ied by the source descr iptor is
ar i thmeticly shifted, and stored in the area specified by the
destination descriptor.
The shifted result is aligned with the
least significant digit position in the destination string. The
shift count is a two I s complement byte whose value ranges from
-128(10) to +127(10). If the shift count is positive, a shift in
the direction of least to most significant digits is performed. A
negative shift count performs a shift from most to least
significant digit. Thus, the shift count is the power of ten by
which the source is multiplied; negative powers of ten effectively
divide. Zero digits are supplied for vacated digit positions. A
zero shift count will move the source to the destination.
The
condition codes reflect the value stored in the destination
string, and whether all significant digits were stored.
A negative shift count invokes a rounding operation. The result
is constructed by shifting the source the specified number of
digit positions.
The rounding digit is then added to the most
significant digit which was shifted out. If this sum is less than
10 (10), the shifted result is stored in the destination string.
If the sum is 10 (10) or greater, the magnitude of th'e shifted
result is increased by 1 and then stored in the destinatlon
string. If no rounding is desired, the rounding digit should be
zero.

The shift count and rounding digit are r.epresented in a single
word referred to as the shift descr iptor.
Bits <15: 12> of this
word must be zero:
15

12 11

8 7

Irnd.dgtl

shift.cnt

Register Form - ASHN and ASHP
When the instruction starts, the operands must have been placed in
the general registers. The source descriptor is placed in R0-Rl,
the destination descriptor is placed in R2-R3, and the shift
descriptor is placed in R4:

A-6

src.dscr

Rl
R2

dst.dscr
R3
shift.dscr

When the instruction is completed, the source descriptor registers
and shift descriptor register are cleared:
15

R"
Rl
R2

-----------------------------------II
"

dst.dscr
R3
R4

In-line Form - ASHN! and ASHP!
The words which follow the opcode word in the instruction stream
are a word address pointer to a two word decimal string source
descriptor, a word address pointer to a two word decimal string
destination descr iptor, and a shift descr iptor word. RI-R6 are
unchanged when the instruction is completed.
Formal Description:
TBS~

Examples:
1.

Multipling by 1"" - Register Form
source descriptor

MOV
SRC.OSCR,R"
MOV
SRC.OSCR+2,Rl
MOV
DST.DSCR,R2
MeV
DST.OSCR+2,R3
MOV
t2,R4
ASHN / ASHP

destination descriptor
shift descriptor word
shift

A-7

BVS

BLT
BEQ
BGT

NEGATIVE
EQUAL
GREATER

Multipling by 100 - In-line Form
ASHNI I
.WORD
.WORD
.WORD

ASHPI
SRC.DSCR.PTR
DST.DSCR.PTR
2

BVS

OVERFLOW

BLT
BEQ
BGT

check for error
negative destination
zero destination
positive destination

OVERFLOW

shift
ptr to src descriptor
ptr to dst descriptor
shift descriptor word
check for error
negative destination
zero destination
positive destination

NEGATIVE
EQUAL
GREATER

Move decimal number - Register Form
MOV
MOV
MOV
MOV

SRC.DSCR,R0
SRC.DSCR+2,Rl
DST.DSCR,R2
DST.DSCR+2,R3

CLR

BVS

OVERFLOW

NEGATIVE
EQUAL
GREATER

destination descriptor
shift descriptor word
shift
check for error
negative destination
zero destination
positive destination

ASHN I ASHP
BLT
BEQ
BGT

source descriptor

Move decimal number - In-line Form
shift
ptr to src descriptor
ptr to dst descriptor
shift descriptor word
check for error
negative destination
zero destination
positive destination

ASHNI / ASHPI
•WORD
SRC. DSCR. PTR
.WORD
DST.DSCR.PTR
.WORD
BVS

0
OVERFLOW

BLT
BEQ

NEGATIVE
EQUAL
GREATER

8GT

Notes:
1.

If bits <15:12> of the shift descriptor word are not zero, the
effect of the instruction is unpredictable.

If bits <11:8> of the shift descriptor are not a valid decimal
digit, the results of the instruction are unpredictable.

Any overlap of the source and destination strings will produce
unpredictable results.

A-8

5.3

CMPC / CMPCI - Compare Character

Format:
15

987

3 2

CMPC

076

CMPCI

076

srcl.dscr.ptr
src2.dscr.ptr

fill

Operation:
Srcl is compared with src2 (srcl-src2).
Condition Codes:
The condition codes are based on the arithmetic comparison of the
most significant pair of unequal srcl and src2 characters
(srcl.byte-src2.byte).
N:
Z:
V:
C:

set if result<0: cleared otherwise
set if result-0: cleared otherwise
set if there was arithmetic overflow, that is, srcl.byte<7)
and src2.byte<7> were different, and src2.byte<7> was the same
as bit <7> of (srcl.byte-src2.byte): cleared otherwise
cleared if there was a carry from the most significant bit of
the result: set otherwise

Suspendability:
This instruction is potentially suspendable.
Description:
Each character of srcl is compared with the corresponding
character of src2 by examining the character strings from most
significant to least significant characters.
If the character
strings are of unequal len<)th, the shorter character string is
conceptually extended to the length of the longer character string
with fill characters beyond its least significant character. The
instruction terminates when the first corresponding unequal
characters are found or when both character strings are exhausted.

A-9

The condition codes reflect the last comparison, permitting the
unsigned branch instructions to test the result.
Register Form - CMPC
When the instruction starts, the operands must have been placed in
the general registers.
The first source character string
descriptor is placed in R0-Rl, the second source character string
descriptor is placed in R2-R3, the fill character is placed in
R4<7:0>, and R4<l5:8> must be zero:
•

8 7

R0
srcl.dscr
Rl
R2
src2.dscr
R3
fill

The instruction terminates with sub-string descriptors in R0-Rl
and R2-R3 which represent the portion of each source character
string beginning with
the
most
significant corresponding
unequal characters.
R0-Rl contain a descriptor for the unequal
portion of the original srcl strin~; R2-R3 contain a descriptor
for the unequal portion of the or 19 inal src2 str ing.
A vacant
character string descriptor indicates that the entire source
character string was equal to the corresponding portion of the
other source character string, including extension by the fill
character;
its address is one greater than that of the least
significant character of the character string.

8 7

R0
sub.srcl.dscr
Rl
R2
sub.src2.dscr
R3
R4

fill

A-lO

In-line Form - CMPCI
The words which follow the opcode word in the instruction stream
are a word address pointer to a two word character string srcl
descriptor, a word address pointer to a two word character string
sre2 descriptor, and a·word whose low order half contains the fill
character and whose high order half must be zero.
R0-R6 are
unchanged when the instruction is completed.
Formal Description:
srcl.len • R0:
srel.adr • Rl:
sre2.1en • R2:
src2.adr • R3:
fill • R4<7:0>: ,

CMPC only

temp • M[R7]:
CMPCIonly
srel.len • M[temp]; 1
srel.adr = M[temp+2];!
R7 • R7+2;
1
temp • M[R7];
src2.1en • M[temp]; 1
src2.adr • M[temp+2];1
R7 • R7+2;
1
fill • M[R7]<7:B>;
R7 • R7+2;
found • 1;
while (srel.len nequ 0) and (src2.1en nequ 0)
and (found nequ 0) do
if (M[srcl.adr] eqlu M[sre2.adr]) then
begin
srcl.len -= srcl.len-l;
srcl.adr -= srcl.adr+l;
src2.1en • src2.len-l:
src2.adr • src2.adr+l
end
else found -= 0;
while (srel.len nequ 0) and (found nequ 0) do
if M[srel.adr] eqlu fill then
begin
srcl.len • srel.len-l;
srcl.adr • srcl.adr+l
end
else found = 0:
while (sre2.1en nequ 0) and (found nequ 0) do
if M[src2.adr] eqlu fill then
begin
src2.len = src2.len-l;

A-II

src2.adr = src2.adr+l
end
else found = 0:
if (srcl.len eq1u 0) then btmpl = fill
else btmpl = M[src1.adr]:
if (src2.1en eq1u 0) then btmp2 = fill
else btmp2 = M[src2.adr]:
carry@btmp = btmp1-btmp2:
N = btmp<lS>;
if btmp eql e then Z = 1 else Z = 0:
if (btmpl<7> neq btmp2<7» and (btmp2<7> eq1 btmp<7»
V = 1 else V = 0:
C = carry;
R0 = src1.1en:
Rl = src1.adr:
R2 = src2.1en:
R3 = src2.adr:
R4 = 0<lS:8>@fi11:

then

CMPC only

Examples:
1.

Compare Strings - Register Form
MOV
MOV
MOV
MOV
MOV
CMPC
BLO
BEQ
BHI

SRC1. DSCR, R0
SRC1. DSCR+2, Rl
SRC2. DSCR, R2
SRC2. DSCR+2, R3
i' ,R4
LESS
EQUAL
GREATER

2nd source descriptor
extend with spaces
compare
srcl<src2
src1=src2
src1>src2

Compare Strings - In-line Form
CMPCI

1st source descriptor

• WORD
• WORD
• WORD

SRC1. DSCR. PTR
SRC 2. DSCR. PTR

BLO
BEQ
BHI

LESS
EQUAL
GREATER

compare
ptr to srcl descriptor
ptr to src2 descriptor
extend with spaces
srcl<src2
src1=src2
srcl>src2

Compare as far as the length of shorter of two str ings Register Form
MOV
MOV
MOV
MOV

SRC1. DSCR, R0
SRC1. DSCR+2, R1
SRC2. DSCR, R2
SRC2. DSCR+2,R3

A-12

1st source descriptor
2nd source descriptor

CMP
BHI
MOV
1$: MOV
CMPC
BEQ
BNE

Re,R2

length of shorter

RI,R2
R2,Re
no fill is used
compare strings
use unsigned branches

EQUAL
NOTEQL

Notes:
1.

The operation of this instruction is unaffected by any overlap
of tne source character strings.

If the srcl character string is vacant, the fill character
will be compared with src2. 11 the src2 character string is
vacant, the fill character will be compared with srcl.
If
both character strings are vacant, the condition codes will
indicate equality.

CMPC -- If an initial source character string descriptor is
vacant, the resulting sub-string descriptor is the same as the
original character string descriptor.

A test for success is BEQ1

When the instruction terminates, the condition codes will be
set as if a CMPB instruction operated on the most significant
unequal characters. If both strings are initially vacant or
are identical, the condition codes will be set as if the last
character's to be compared were identical.
This results in
equality with N cleared, Z set, V cleared, and C cleared.

Both CMPC and CMPCI update the cond it ion codes.
sub-string descriptors.

a test for failure is BNE.

A-I3

CMPC returns

5.4

CMPN / CMPP / CMPNI / CMPPI - Compare Decimal

Format:
15

9 8

3 2

CMPN

076

CMPP

076

CMPNI

076

srcl.dscr.ptr
src2.dscr.ptr

CMPPI

076

srcl.dscr.ptr
src2.dscr.ptr
Operation:
Srcl is compared with src2 (srcl-src2).
Condition Codes:
N:
Z:
V:
C:

set if srcl<src2:
set if srcl=src2:
cleared
cleared

cleared otherwise
cleared otherwise

Suspendability:
This instruction is potentially suspendable.
Description:
Srcl is arithmetically compared with src2.
The condition codes
reflect the comparison. The signed branch instruction can be used
to test the result.

A-14

Register Form - CMPN and CMPP
When the instruction starts, the operands must have been placed in
the general registers. The first source descriptor is placed in
R0-Rl, and the second source descriptor is placed in R2-R3:
15

R0
srcl.dscr
Rl
R2
src2.dscr

When the instruction is completed, the source descriptor registers
are cleared:
15

"
"
"
"

Rl
R2
R3

In-line Form - CMPNI and CMPPI
Each word address pointer which follows the opcode word in the
instruction stream"refers to a two word decimal string descriptor.
R"-R6 are unchanged when the instruction is completed.
Formal Description:
TBS;

Examples:
1.

Compare Decimal Strings - Register Form
MOV
MOV
MOV
MOV

SRCl.DSCR,R0
SRC1. DSCR+2, Rl
SRC2. DSCR, R2
SRC2. DSCR+2 ,R3

A-IS

1st source descriptor
2nd source descriptor

compare
use signed branches

CMPN / CMPP
BLT
LESS
SEQ
EQUAL
SGT
GREATER

Compare Decimal Strings - In-line Form
compare
ptr to srcl descriptor
ptr to src2 descriptor
negative destination
zero destination
positive destination

CMPNI / CMPPI
.WORD
SRCl.DSCR.PTR
.WORD
SRC2.DSCR.PTR
SLT
NEGATIVE
SEQ
EQUAL
SGT
GREATER

Notes:
1.

The operation of these instructions is unaffected by any
overlap of the source strings provided that each source string
is a valid representation of the specified data type.

A-16

5.5

CVTLN / CVTLP / CVTLNI / CVTLPI - Convert Long to Decimal

Format:
15

9 8

320

CVTLN

876

CVTLP

876

CVTLNI

876

dst.dscr.ptr
src.long.ptr

CVTLPI

876

dst.dscr.ptr
src.long.ptr
Operation:
decimal string <- long integer
Condition Codes:
N:
Z:
V:

set if dst<8, cleared otherwise
set if dst-8J cleared otherwise
set if dst can not contain all significant digits of the
resultJ cleared otherwise
C: - cleared

Suspendability:
This instruction is potentially suspendable.

A-17

Description:
The source long integer is converted to a decimal string.
The
condition codes reflect the result stored in the destination
decimal string, and whether all significant digits were stored.
Register Form - CVTLN and CVTLP
When the instruction starts, the operands must have been placed in
the general registers.
The destination descr iptor is placed in
R0-Rl, and the source long integer is placed in R2-R3:
15

RS
dst.dscr
Rl
R2
src.10ng
R3
When the instruction is completed, the source long integer
registers are cleared:
15

R0
dst.dscr
R1
R2

In-line Form - CVTLNI and CVTLPI
The words which follow the opcode word in the instruction stream
are a word address pointer to a two word decimal str ing
destination descriptor, and a word address pointer to a two word
long integer source. RS-R6 are unchanged when the instruction is
completed.

A-I8

Formal Description:
TBS:

Examples:
1.

Convert Long to Decimal - Register Form
MOV
MOV
MOV
MOV

OST.OSCR,R0
DST.DSCR+2,Rl
SRC.LONG+2,R2
SRC.LONG,R3

destination descriptor
source long integer
convert
check for error
negative destination
zero destination
positive destination

CV'I'LN / CVTLP

BVS
BLT
BEQ
BGT

OVERFLOW
NEGATIVE
EQUAL
GREATER

Convert Long to Decimal - In-line Form
CVTLNI / CVTLPI
OST. DSCR. PTR
• WORD
SRC.LONG.PTR
•WORD
SVS
OVERFLOW
BLT
NEGATIVE
SEQ
EQUAL
BGT
GREATER

convert
ptr. to dst descriptor
ptr to long integer
check for error
negative destination
zero destination
positive destination

Notes:
1.

In-line forms use a long integer oriented with the low order
portion in src.long, and the sign and high order portion in
src.long+2.

A-19

5.6

CVTNL / CVTPL / CVTNLI / CVTPLI - Decimal to Long

Format:
15

9 8

320

CVTNL

076

CVTPL

076

CVTNLI

076

src.dscr.ptr
dst.long.ptr

CVTPLI

076

src.dscr.ptr
dst.long.ptr
Operation:
long int~er <- decimal string
Condition Codes:
The condition codes are based on the long integer destination and
on the sign of the source decimal string.
N:
Z:
V:
C:

set if 10ng.inteqer<0; cleared otherwise
set if 10ng.inteqer=0: cleared otherwise
set if long. integer dst can not correctly represent the two's
complement form of the result; cleared otherwise
set if src<0 and long.integerI0: cleared otherwise

Suspendability:
This instruction is potentially suspendab1e.

A-20

Description:
The source decimal string is converted to a long integer. The
condition codes reflect the result of the operation, or whether
significant digits were not converted.
Register Form - CVTNL and CVTPL
When the instruction starts, the operands must have been placed in
the general registers. The source decimal string descriptor is
placed in R0-Rl:
15

src.dscr

Rl
When the instruction is completed, the source decim~l string
descriptor registers are cleared, and the destination long integer
is returned in R2-R3:
15
R9

Rl
R2

dst.long

In-line Form - CVTNLI and CVTPLI
The words which follow the opcode word in the instruction stream
are a word address pointer to a two word dec imal str in9 source
descriptor, and a word address pointer to a two word long integer
destination.
R0-R6 are unchanged when the instruct ion is
completed.
Formal Description:
TB5:

A-21

Examples:
1.

Convert Decimal to Long - Register Form
SRC • DSCR, R0
SRC.DSCR+2,Rl
CVTNL I CV'l'PL
SVS
OVERFLOW
BLT
NEGATIVE
SEQ
EQUAL
GREATER
SGT

source descriptor

MOV
MOV

Convert Decimal to Long

convert
check for error
negative destination
zero destination
positive destination
In-line Form
convert
ptr to src descriptor
ptr to dst long int
check for error
negative destination
zero destination
positive destination

CV'l'NLI / CVTPLI
•WORD
SRC. DSCR. PTR
.WORD
DST.LONG.PTR
BVS
OVERFLOW
BLT
NEGATIVE
SEQ
EQUAL
SGT
GREATER
Notes:
1.

In-line forms use a long integer oriented with the low order
portion in dst .long, and the sign and high order portion in
dst .10ng+2.

If the V bit is set, the contents of the long integer
destination are the least significant 32 bits of the result.

A source whose value is +2**31 can be represented as a 32 bit
binary integer.
However, since the destination is a two's
complement long integer, the resul ting condition codes will
be N set, Z cleared, V set, and C cleared.

A-22

5.7

CVTNP / CVTPN / CVTNPI / CVTPNI - Convert Decimal

Format:

321

9 8

CVTNP

176

CVTPN

876

CVTNPI

876

src.dscr.ptr
dst.dscr.ptr

CVTPNI

876

src.dscr.ptr
dst.dscr.ptr
Operation:
CVTNP /

CVTNPI

CVTPN / CV'l'PNI

packed string <- numeric string
numeric string <- packed string

Condition Codes:
N:
Z:
V:
C:

set if dst<8; cleared otherwise
set if dst=8; cleared otherwise
set if dst can not contain all significant digits of the
result; cleared otherwise
cleared

Suspendability:
This instruction is potentially suspendable.

A-23

Description:
These instructions convert between numeric and packed decimal
strings. The source decimal string is converted and moved to the
destination string. The condition codes reflect the result of the
operation, or whether all significant digits were stored.
Register Form - CVTNP and CVTPN
When the instruction starts, the operands must have been placed in
the general registers. The source descriptor is placed in RI-Rl,
and the destination descriptor is placed in R2-R3:
15

src.dscr

Rl
R2

dst.dscr

R3
When the instruction is completed, the source descriptor registers
are cleared:
15

R0
Rl
R2
R3

dst.dscr

In-line Form - CVTNPI and CVTPNI
Each word address pointer which follows the opcode word in the
instruction stream refers to a two word decimal string descriptor.
R0-R6 are unchanged when the instruction is completed.
Formal Description:
TBS;

A-24

Examples:
1.

Convert Between Numeric String and Packed String - Register
Form
SRC.DSCR,R8
SRC.DSCR+2,Rl
NOV
DST.DSCR,R2
NOV
DST.DSCR+2,R3
CVTNP / CVTPN
BVS
OVERFLCM
BLT
NEGATIVE
BBQ
EQUAL
NOV

1 source descriptor

NOV

BG'l'

destination descriptor
convert
check for error
negative destination
zero destination
positive destination

GREATER

Convert Between Numeric String and Packed String - In-line
Form
convert
ptr to src descriptor
ptr to dst descriptor
check for error
negative destination
zero destination
positive destination

CV'l'NPI / CVTPNI
•WORD
SRC. DSCR. PTR

BVS
BLT
BEQ

CST. DSCR. PTR
OVERFLCM
NEGATIVE
BQUAL

BG'l'

GREATER

• WORD

Notes:
1.

The results of the instruction are unpredictable if the source
and destinatiqn strings overlap.

'!'hese instructions use both a numeric and a packed decimal
string descriptor.

A-25

5.8

DIVP / DIVPI - Divide Decimal

Format:
15

9 8

'3 2

DIVP

076

DIVPI

076

srcl.dscr.ptr
src2.dscr.ptr
dst.dscr.ptr
Operation:
dst <- src2 / srcl
Condition Codes:
N:
Z:
V:

set if dst<0; cleared otherwise
set if dst=0; cleared otherwise
set if dst can not contain all significant digits of the
result or if srcl=0; cleared otherwise
set if srcl=0; cleared otherwise

Suspendability:
This instruction is potentially suspendable.
Description:
Src2 is divided by srcl, and the quotient (fraction truncated) is
stored in the destination string. The condition codes reflect the
value stored in the destination string, and whether all
significant digits were stored.
Register Form - DIVP
When the instruction starts, the operands must have been placed in
the general registers. The first source descriptor is placed in
R0-Rl, the second source descr iptor is placed in R2-R3, and the
destination descriptor is placed in R4-R5:

A-26

15
R0

srcl.dscr

Rl
R2

src2.dscr
R3
R4

dst.dscr
RS
When the instruction is completed, the source descriptor registers
are cleared:

Rl
R2

dst.dscr

RS
In-line Form - DIVPI

Each word address pointer which follows the opcode word in the
instruction stream refers to a two word decimal string descriptor.
R9-R6 are unchanged when the instruction is completed.
Formal Description:
TB5:

Examples:
1.

Divide - Register Form
MOV
MOV
MOV
MOV

SRCI. OSCR, R0
SRCl.DSCR+2,Rl
SRC2. OSCR, R2
SRC2 •DSCR+2 , R3

A-27

divisor descriptor
dividend descriptor

MOV
MOV
DIvp·
BVS
BLT
BEQ
BGT
2.

DST.D5CR,R4
DST. DSCR+2, RS

quotient descriptor

OVERFLOW
NEGATIVE
EQUAL
GREATER

divide
check for error
negative destination
zero destination
positive destination

Divide - In-line Form
DIVPI
•WORD
• WORD
•WORD

SVS
SLT
SEQ
BGT

divide
ptr to divisor dscr
ptr to dividend dscr
ptr to quotient dscr
check for error
negative destination
zero destination
positive destination

SRCl.DSCR.PTR
SRC 2. DSCR. PTR
DST.DSCR.PTR
OVERFLOW
NEGATIVE
EQUAL
GREATER

Notes:
1.

The operation of these instructions is unaffected by any
overlap of the source strings provided that each source string
is a valid representation of the specified data type.

The results of the instruction are unpredictable if the source
and destination strings overlap.

Division by zero will set the V and C bits. The destination
string, and the Nand Z condition code bits will be
unpredictable.

No numeric string divide instruction is provided.

A-28

5.9

LOCC / LOCCI - Locate Character

Format:
15

3 2

987

LOCC

076

LOCCI

076

o
I

src.dscr.ptr

~----------------------------------

char

Operation:
Search source character string for a character.
Condition Codes:
The condition codes are based on the final contents of R0.
N:
Z:
V:
C:

set if R0<lS> set; cleared otherwise
set if R0=0: cleared otherwise
cleared
cleared

Suspendability:
This instruction is potentially suspendable.
Description:
The source character string is searched from most significant to
least significant character until the first occurrence of the
search character. A character str ing descr iptor is returned in
R0-Rl which represents the portion of the source character string
beginning with the located character.
If the source character
string contains only characters not equal to the search character,
the instructions return a vacant character string descriptor with
an address one greater than that of the least s1gnificant
character of the source character string. The condition codes
reflect the resulting value in R0.

A-29

Register Form - LOCC
When the instruction starts, the operands must have been placed in
the general registers. The source character string descriptor is
placed in R0-Rl, the search character is placed in R4<7: 0>, and
R4<15:8> must be zero:
15

8 7

R0
src.dscr

char

When the instruction is completed, R0-Rl contain a character set
descriptor which represents the sub-string of the source character
string beginning with the located character:
15
R0

8 7
sub.src.dscr

char

In-line Form - LOCe!
The words which follow the opcode word in the instruction stream
are a word address pointer to a two word character string source
descr iptor, and a word whose low order half contains the search
character and whose high order half must be zero.
When the
instruction is completed, R0-Rl contain a character str ing
descriptor which represents the sub-string of the source character
string beginning with the located character. R2-R6 are unchanged:

A-30

8 7

R0
sub.src.dscr
Rl
Formal Description:
src.len - R07
src.adr • R17
char • R4<7:0>7

LOCC only

temp • M[R7] ;
src.len • M[temp] 7
src.adr • M[temp+2];
R7 • R7+2;
char == M[R7]<7:8>;
R7 • R7+2;

LOCCI only

found == 0;
while (src.len nequ 0) and (found eqlu 0) do
if M[src.adr] nequ char then
begin
src.len == src.len-17
src.adr == src.adr+l
end
else found • 1;
R0 == src.len;
Rl at src.adr;
R4 == 0<lS:8>@char7

LOCC only

N == R0<lS>7
Z • R0 eqlu 0;
V == 0;
C == 0J

Examples:
1.

Find the Beginning of a Comment - Register Form
MOV
MOV
MOV
LOCC
BNE

STR.DSCR,R0
STR. DSCR+2, Rl
I' 7,R4
FOUND

A-3J

string to search
search for semi-colon
locate
R0 and Rl are the
sub-string descriptor

Find the Beginning of a Comment - In-Line Form
LOCCI

locate
ptr to src descriptor
search for semi-colon
R0 and Rl are the
sub-string descriptor

• WORD
• WORD

SRC.DSCR.PTR
,

BNE

FOUND

Notes:
1.

If the initial source character string descriptor is vacant,
the instruction terminates with the condition codes indicating
no match was found.
The original source character string
descriptor is returned in RS-Rl.

A test for success is BNE; )a test for failure is BEQ.

The condition codes will be set as if this instruction were
followed by TST R0.

A-32

5.10

L2Dr - Load 2 Descriptors

Format:
15
L2Dr

9 8
876

3 2
82

Operation:
Load word pairs into R8-Rl and R2-R3.
Condition Codes:
The condition codes are not affected.
N:
Z:
V:

not affected
not affected
not affected
not affected

Suspendability:
This instruction is non-suspendable.
Description:
This instruction augments the character and decimal str ing
instructions by efficiently loading string descriptors into the
general registers .•
A descr iptor 'alpha' is loaded into R8-Rl; a second descr iptor
'beta' is loaded into R2-R3. The address of the descriptors are
determined by the addressing mode @(Rr)+ where r is the low order
three bits of the opcode word.
The address of the descr iptor
• alpha' is der ived by applying this addressing mode once; the
address of the descriptor 'beta' is derived by applying this
addressing mode a second time.
The addressing mode
auto-increments the indicated register by 2. The addressing mode
computation is not affected by the descr iptors which are loaded
into the general registers. The words which contain the addresses
of the descriptors are in consecutive words in memory:
the
descriptors themselves may be anywhere in memory. The condition
codes are not affected.

A-33

When the instruction is completed, the 'alpha' descr iptor is in
R0-Rl and the 'beta' descriptor is in R2-R3:
15

R0
alpha.dscr

Rl
R2

beta.dscr
R3
Formal Description:
temp = R[r]i
adr.alpha = M[temp]i temp = temp+2;
adr.beta = M[temp]i temp = temp+2;
if (r gequ 4) then R[r] = tempi
R0 = M[adr.alpha);
Rl = M[adr.alpha+2]i
R2 = M[adr.beta];
R3 = M[adr.beta+2];
Examples:

Decimal String Compare
load descriptors

L2D7
.WORD
.WORD

SRCI
SRC2
compare

CMPN

SRCl: •WORD

SRCl. LEN
SRCl.ADR

1st src descriptor

.WORD

SRC2: •WORD
.WORD

SRC2. LEN
SRC2.ADR

2nd src descriptor

Notes:

A-34

5.11

L3Dr - Load 3 Descriptors

Format:
15
L3Dr

9 8
076

3 2
06

Operation:
Load word pairs into R0-Rl, R2-R3 and R4-Rs.
Condition Codes:
The condition codes are not affected.
N:
Z:
V:

not affected
not affected
not affected
not affected

Suspendability:
This instruction is non-suspendable.
Description:
This instruction augments the character and decimal string
instructions by efficiently loading str ing descr iptors into the
general registers.
A descr iptor 'alpha' is loaded into R0-Rl:
a second descr iptor
'beta' is loaded into R2-R3; a third descriptor 'gamma' is loaded
into R4-Rs. The address of the descriptors are determined by the
addressing mode @(Rr)+ where r is the low order three bits of the
_ opcode word. The address of the descriptor 'alpha' is derived by
applying this addressing mode once; the address of the descriptor
'beta' is derived by applying this addressing mode a second time;
the address of the descriptor 'gamma' is derived by applying this
addressing mode a third time.
The address mode auto-increments
the indicated register by 2. The addressing mode computation is
not affected by the descriptors which are loaded into the general
registers.
The words which contain the addresses of the
descriptors are in consecutive words in memory: the descriptors
themselves may be anywhere in memory. The condition codes are not
affected.

A-35

When the instruction is completed, the 'alpha' descr iptor is in
R0-Rl, the 'beta' descr iptC?r is in R2-R3 and the 'gamma'
descriptor is in R4-R5:
15

R0
Rl

alpha.dscr

R2
R3

beta.dscr

R4
gamma.dscr
R5
Formal Description:
temp = R[r]i
adr.alpha = M[temp]i temp = temp+2i
adr.beta = M[temp]i temp = temp+2i
adr.gamma = M[temp]i temp = temp+2i
if (r gequ 6) then R[r] = tempi
R0 = M[adr.alpha]i
Rl = M[adr.alpha+2];
R2 = M[adr.betali
R3 = M[adr.beta+2];
R4 = M[adr.gamma]i
R5 = M[adr.gamma+2]i

A-36

Examples:
1.

Three Address Add
L3D7
•WORD
• WORD
• WORD
ADDN

load descriptors
SRCl
SRC2
DST

add

SRC1. LEN
SRC1. ADR

1st src descriptor

•WORD

SRC2: .WORD
.WORD

SRC2.LEN
SRC2.AOR

2nd src descriptor

DST.LEN
DST • ADR

dst descriptor

SRC1: • WORD

DST:.WORD
•WORD

Notes:

A-37

5.12

MATC / MATC! - Match Character

Format:
15

3 2

MATC

076

MATC!

076

src.dscr.ptr
obj.dscr.ptr
Operation:
Search source character string for object character string.
Condition Codes:
The condition codes are based on the final contents of R0.
N:
Z:
V:
C:

set if R0<15> set; cleared otherwise
set if R0=0; cleared otherwise
cleared
cleared

Suspendability:
This instruction is potentially suspendable.
Description:
The source character string is searched from most significant to
least significant character for the first occurrence of the entire
object character str ing.
A character str ing descr iptor is
returned in R0-Rl which represents the portion of the or iginal
source character string beginning with the most significant
character to completely match the object- character string. If the
object character str ing did not completely match any portion of
the source character string, the character descriptor returned in
R0-Rl is vacant with an address one greater than the least
significant character in the source string. The condition codes
reflect the resulting value in R0. If the Z bit is cleared, the
entire object was successfully matched with the source character
string; if the Z bit is set, the match failed.

A-38

Register Form - MATe
When the instruction starts, the operands must have been placed in
the general registers. The source character string descriptor is
placed in R0-Rl, and the object character str ing descr iptor is
placed in R2-R3:
15
R0
src.dscr
Rl
R2
obj.dscr
R3
The instruction terminates with a character sub-string descriptor
returned in R0-Rl which represents the portion of the original
source character string beginning with the most significant
character to completely match the object character string.
15
R0
sub.src.dscr
Rl
R2
obj.dscr
R3

In-line Form - MATCI
The words which follow the opcode word in the instruction stream
are a word address pointer to a two word character string source
descr iptor, and a word address pointer to a two word character
str ing object descr iptor.
The instruction terminates with a
character sub-string descriptor returned in R0-Rl which represents
the portion of the original source character string beginnlng with
the most significant character to completely match the object
character str ing.
R2-R6 are unchanged when the instruction is
completed.

A-39

15
R0
sub.src.dscr

Rl
Formal Description:
src.len = R0i
src.adr = Rli
obj.len = R2i
obj.adr = R3i

MATC only

temp = M[R7] ;
src.len = M[temp];
src.adr = M[temp+2];
R7 = R7+2;
temp = M[R7] ;
obj.len = M[temp]i
obj.adr = M[temp+2];
R7 = R7+2i

MATC! only

tmp.len = obj.len;
found = 0;
while (src.len gequ obj.len) and (obj.len nequ 0)
and (found eqlu 0) do
begin
same = 1;
while (obj.len nequ 0) and (same eqlu 1) do
if (M[obj.adr] eqlu M[src.adr])
then
begin
obj.len = obj.len-l;
obJ.adr = ob).adr+l;
src.len = src.len-l;
src.adr = src.adr+l
end
else
same = 0;
found = same;
obj.adr = obj.adr+obj.len-tmp.1eni
src.len = src.len+tmp.len-obj.len-l;
src.adr = src.adr+obj.len-tmp.len+l;
obj.len = tmp.len
endi

if found eql 1
then
begin
R0 = src.len+li
Rl = src.adr-l
end

A-40

else
begin
R0 -= 0;
Rl -= src.adr+src.len
end;
MATC only

R2 • obj.len;
R3 = obj.adr;
N • R0<lS>;
Z • R0 eqlu 0;
V = 0;
C = 0i
Examples:
1.

Find a Keyword - Register Form
MOV
MOV
Mev
MOV
MATC
BNE

SRC.DSCR,R0
SRC.DSCR+2,Rl
OBJ.DSCR,R2
OBJ. DSCR+2, R3

1st source descriptor
2nd source descriptor
search for keyword
object was in string

FOUND

Find a Keyword - In-line Form
MATCI
•WORD
•WORD
BNE

search for keyword
ptr to src descriptor
ptr to obj descriptor
object was in string

SRC.DSCR.PTR
OBJ.DSCR.PTR
FOUND

Notes:
1.

The operation of this instruction is unaffected by any overlap
of the source and object character strings.

A vacant object character string
matches
any non-vacant
source character string.
A vacant source character string
will not match any object character str ing.
If the initial
source character string descriptor is vacant, the instruction
terminates with the condition codes indicating no match was
found.
The original source character string descriptor is
returned in R0-Rl.

A-41

If the length of the object character string is greater than
that of the source character string then no mat~h is found;
R0-Rl and the condition codes will be updated.

A test for success is BNE: a test for failure is BEQ.

The condition codes will be set as if this instruction were
followed by TST R0.

A42

5.16

Move/ MoveI - Move Character

Format:
15

987

3 2

Move

076

MOVCI

"76

src.dscr.ptr
dst.dscr.ptr

fill

Operation:
dst <- src
Condition Codes:
The condition codes are based on the arithmetic comparison of the
initial character string lengths (result=src.len-dst.len).
N:
Z:
V:
C:

set if result<0: cleared otherwise
set if result:0: cleared otherwise
set if there was arithmetic overflow, that is, src.len<lS> and
dst.len<lS> were different, and dst.len<lS> was the same as
bit <15> of (src.len-dst.len): cleared otherwise
cleared if there was a carry from the most significant bit of
the result; set otherwise

Suspendability:
This instruction is potentially suspendable.
Description:
The character string specified by the source descriptor is moved
into the area specified by the destination descr iptor.
It is
aligned by the most significant character.
The condition codes
reflect an arithmetic comparison of the original source and
destination lengths.
If the source str ing is shorter than the
destination string, the fill character is used to complete the
least significant part of the destination string.
This is
indicated by the C bit set.

A-43

If the source string is longer than the destination string, the
least si9nificant characters of the source string are not moved.
This i~ lndicated by the Z and e bits cleared. If the source and
destination strings are of equal length, all characters are moved
with neither truncation nor filling. This is indicated by the Z
bit set. The unsigned branch instructions may test the result of
the instruction.
Register Form - MOVe
When the instruction starts, the operands must have been placed in
the general registers. The source character string descriptor is
placed in R0-RI, the destination character str ing descr iptor is
placed in R2-R3, the fill character is placed in R4<7: 0), and
R4<15:8) must be zero:
15 ,

8 7

src.dscr

Rl
R2

dst.dscr

R3
R4

fill

When the instruction is completed, R0 contains the number of
unmoved source string characters, and Rl through R3 are cleared:
15
R0

8 7

max(8,src.len-dst.len)

Rl
R2
R3
R4

fill

A-44

In-line Form - Movel
The words which follow the opcode word in the instruction stream
are a word address pointer to a two word character string source
descriptor, a word address pointer to a two word character string
destination descriptor, and a word whose low order half contains
the fill character and whose high order half must be zero. R0-R6
are unchanged when the instruction is completed.
Formal Description:
src.len • R0:
src.adr = Rl:
dst.len • R2:
dst.adr = R3:
fill = R4<7:0>~

Move only

temp = M[R7]:
src.len = M{temp]:
src.adr = M[temp+2];
R7 = R7+2i
temp = M[R7] i
dst.len = H[temp]:
dst.adr = M[temp+2];
R7 = R7+2:
fill = M[R7]<7:0>:
R7 = R7+2:

Movel only

carry@temp = src.len-dst.len:
N = temp<lS>:
Z = temp eqlu 0;
V = (src.len<lS> neq dst.len<lS»
temp<lS»
C = carry;

and (src.len<lS> eql

if src.adr gequ dst.adr then
begin
! most to least significant
characters
while (src.len nequ 0) and (dst.len nequ 0) do
begin
M[dst.adr] = M[src.adr];
src.len = src.len-l;
src.adr = src.adr+l:
dst.len = dst.len-l:
dst.adr = dst.adr+l
end:
while dst.len nequ 0 do
begin
M[dst.adr] = fill:
dst.len = dst.len-l;
dst.adr = dst.adr+l

A-45

end
end

else

begin
! least to most significant
characters
src.adr = src.len-l-max{0,src.len-dst.len)+src.adr:
dst.adr = dst.len+dst.adr-li
while src.len lssu dst.len do
begin
M(dst.adr] = fill:
dst.len = dst.len-l:
dst.adr = dst.adr-l
end:
while dst.len nequ 0 do
begin
M[dst.adr] = M[src.adr];
src.len = src.len-l;
src.adr = src.adr-li
dst.len = dst.len-l;
dst.adr = dst.adr-l
end
end;
R0 = src.len:
Rl = 0;
R2 = 0;
R3 == 0;
R4 == 0<15:8>@filli

MOVC only

Examples:
1.

Moving Data - Register Form
MOV
MOV
MOV
MOV
MOV
MOVC
BHI
BLO
BEQ

source descriptor

SRC.DSCR,R0
SRC • DSCR+ 2, Rl
DST.DSCR,R2
DST.DSCR+2,R3
t' ,R4

destination descriptor
fill with spaces
move
test for truncation
test for fill
test for equal length

TRONC
FILL
EQUAL

Moving Data - In-line Form

Move I
•WORD
• WORD
• WORD

SRC. DSCR. PTR
DST.DSCR.PTR

BHI

TRUNC
FILL
EQUAL

SLO

SEQ

move
ptr to src descriptor
ptr to dst descriptor
fill is space
test for truncation
test for fill
test for equal length

A-46

Clearing Storage - Register Form
CLR
MOV
MOV
CLR
MOVC

R0
DST. DSCR, R2
DST. DSCR+2, R3
R4

zero length source
destination descriptor
store null characters
propagate fill

Clearing Storage - In-line Form
MOVCI
• WORD
• WORD

•WORD

propagate fill
ptr to null str dscr
ptr to dst descriptor
fill with nulls

SRC. DSCR. PTR
DST.DSCR.PTR

Notes:
1.

The operation of this instruction is unaffected by any overlap
of the source and dest ination str ings.
The resul t is
equivalent to having read the ent ire source str ing before
storing characters in the destination.

If the source string is vacant, the fill character will be
propagated through the destination string. If the destination
string is vacant, no characters will be moved. The condition
codes will be updated.
MOVC will update the general
registers.

Move -- When the instruction terminates, R0 is zero only if Z

The condition codes will be set as if this instruction were
preceded by eMP src.len,dst.len.

or C are set.

A-47

5.17

MOVRC / HOVRCI - Move Reverse Justified Character

Format:
15

3 2

987

HOVRC

076

HOVReI

076

src.dscr.ptr
dst.dscr.ptr

fill

Operation:
dst <- reverse justified src
Condition Codes:
The condition codes are based on the arithmetic comparison of the
initial character string lengths (result=src.len-dst.len).
N:
Z:
V:

set if result<0: cleared otherwise
set if result=0: cleared otherwise
set if there was arithmetic overflow, that is, src.len<15> and
dst.len<15> were different, and dst.len<15> was the same as
bit <15> of (src.len-dst.len): cleared otherwise
cleared if there was a carry from the most significant bit of
the result: set otherwise

Suspendability:
This instruction is potentially suspendable.
Description:
3he character string specified by the source descriptor is moved
into the area specified by the destination descriptor.
It is
aligned by the least significant character. The condition codes
reflect an arithmetic comparison of the original source and
destination lengths.
If the source str ing is shorter than the
destination str ing, the fill character is used to complete the
most significant part of the destination string.
This is
indicated by the C bit set.

A-48

If the source str ing is longer than the destination str ing, the
most significant characters of the source string are not moved.
This is indicated by the Z and C bits cleared. If the source and
destination strings are of equal length, all characters are moved
with neither truncation nor filling. This is indicated by the Z
bit set. The unsigned branch instructions may test the result of
the instruction.
Register Form - MOVRC
When the instruction starts, the operands must have been placed in
the general.reqisters. The source character string descriptor is
placed in R"-R~, the destination character string descriptor is
placed in R2-R3, the fill character is placed in R4<7:fJ>, and
R4<15:8> must be zero:
15

8 7

src.dscr

Rl
R2

dst.dscr

fill

When the instruction is completed, R0 contains the number of
unmoved source string characters, and Rl through R3 are cleared:
15

8 7

max (0,src.len-dst.len)

R2
R3

----------------------------------0
fill
I

A-49

In-line Form - MOVRCr
The words which follow the opcode word in the instruction stream
are a word address pointer to a two word character string source
descriptor, a word address pointer to a two word character string
destination descriptor, and a word whose low order half contains
the fill character and whose high order half must be zero. R0-R6
are unchanged when the instruction is completed.
Formal Description:
src.len = RBi
src.adr = Rl;
dst.len = R2;
dst.adr = R3i
fill = R4<7:0>;

MOVRC only

temp = M[R7] ;
src.len = M[temp];
src.adr = M[temp+21i
R7 = R7+2i
temp = M[R7] i
dst.len = M[temp]i
dst.adr = M[temp+2];
R7 = R7+2;
fill = M[R7)<7:S>:
R7 = R7+2;

MOVRcr only

carry@temp = src.len-dst.leni
N = temp<IS>;
Z == temp eqlu 0;
V = (src.len<lS> neq dst.len<IS»
. . C = carry:

and (src.Ien<IS> eqi temp<IS»

if (src.len+src.adr-I) gequ (dst.Ien+dst.adr-l) then
begin
! most to least significant
characters
src.adr = max(0,src.Ien-dst.Ien)+src.adri
while src.len Issu dst.len do
begin
M[dst.adr] = fill;
dst.Ien = dst.len-li
dst.adr = dst.adr+l
end;
while dst.len nequ 0 do
begin
M{dst.adr] = M[src.adr];
src.len = src.len-I;
src.adr = src.adr+l;
dst.len = dst.len-l;
dst.adr = dst.adr+l

A-50

Notes:
1.

The operation of this instruction is unaffected by any overlap
of the source and destination strings.
The result is
equivalent to having read the entire source string before
storing characters in the destination.

If the source string is vacant, the fill character will be
propagated through the destination string. If the destination
string is vacant, no characters will be moved.
Condition
codes will be updated.
MOVRC will update the general
registers.

HOVRC -- When the instruction terminates, R0 is zero only if Z
or C are set.

The condition codes will be set as if this instruction were
preceded by CMP src.len,dst.len.

A-51

end;
end

else

begin
! least to most significant
characters
src.adr = src.len+src.adr-l:
dst.adr = dst.len+dst.adr-li
while (src.len nequ 0) and (dst.len nequ 0) do
becjin
M(dst.adr] = M(src.adr];
src.len = src.len-li
src.adr = src.adr-l;
dst.len = dst.len-l;
dst.adr = dst.adr-l
end:
while dst.len nequ 0 do
becjin
M(dst.adr1 = fill;
dst.len = dst.len-l;
dst.adr = dst.adr-l
end
end;
R0 = src.len;
Rl = 0;
0;
R2
R3 = 0;
R4 = 0<15:8>@fill;

MOVRC only

::II

Examples:
1.

Moving Data - Register Form
MOV
MOV
MOV
MOV
MOV
MOVRC
SHI
SLO

SEQ
2.

source descriptor

SRC.DSCR,R0
SRC • OSCR+ 2, Rl
DST.OSCR,R2
DST.DSCR+2,R3
i' ,R4

destination descriptor
fill with spaces
move
test for truncation
test for fill
test for equal length

TRUNC
FILL
EQUAL

Moving Data - In-line Form
move
ptr to src descriptor
ptr to dst descriptor
fill is space
test for truncation
test for fill
test for equal length

MOVRCI
• WORD
• WORD
• WORD

SRC.DSCR. PTR
DST. OSCR. PTR

SHI
BLO
SEQ

TRUNC
FILL
EQUAL

A-52

5.18

MOVTC / HOVTCI - Move Translated Character

Format:
15

3 2

987

HOvrC

"76

MOCTCI

976

src.dscr.ptr
dst.dscr.ptr

" table.adr fill
Operation:
dst <- translated src
Condition Codes:
The condition codes are based on the arithmetic comparison of the
initial character string lengths (result=src.len-dst.len).
N:
Z:
V:
C:

set if result<3i cleared otherwise
set if result="; cleared otherwise
set if there was arithmetic overflow, that is, src.len<lS> and
dst.len<15> were different, and dst.len<lS> was the same as
bit <15> of (src.len-dst.len); cleared otherwise
cleared if there was a carry from the most significant bit of
the result; set otherwise

Suspendability:
This instruction is potentially suspendable.

A-53

Description:
The character string specified by the source descriptor is
translated and moved into the area specified by the destination
descr iptor.
It is aligned by the most significant character.
Translation is accomplished by using each source character as an 8
bit positive integer index into a 256 byte table, the address of
which is an operand of the instruction. The byte at the indexed
location in the table is stored in the destination str ing. The
condition codes reflect an arithmetic comparison of the original
contents source and destination lengths.
If the source string is shorter than the destination string, the
untranslated fill character is used to complete the least
significant part of the destination string. This is indicated by
the C bit set.
If the source string is longer than the
destination string, the least significant characters of the source
string are not moved.
This is indicated by the Z and C bits
cleared.
If the source and destination strings are of equal
length, all characters are translated and moved with neither
truncation nor filling. This is indicated by the Z bit set. The
unsigned branch instructions may test the result of the
instruction.
Register Form - MOVTC
When the instruction starts, the operands must have been placed in
the general registers. The source charact'er string descriptor is
placed in R0-Rl, the destination character string descriptor is
placed in R2-R3, the fill character is placed in R4<7:B>, R4<l5:8>
must be zero, and the translation table address is placed in R5:
15

8 7

R0
Rl

src.dscr

R2
dst.dscr
R3
fill

R4
R5

table.adr

When the instruction is completed, RB contains the number of
unmoved source string characters, and Rl through R3 are cleared:

A-54

v • (src.len<IS> neq dst.len<IS»
C = carry:

and (src.len<IS> eql temp<lS»

if src.adr gequ dst.adr then
begin
! most to least significant
characters
while (src.len nequ 0) and (dst.len nequ 0) do
begin
M[dst.adr] = M[table.adr+M[src.adr]]:
src.len = src.len-l;
src.adr = src.adr+l:
dst.len = dst.len-l;
dst.adr = dst.adr+l
end;
while dst.len nequ 0 do
begin
M[dst.adr] = fill:
dst.len = dst.len-li
dst.adr = dst.adr+l
end;
end
else
begin
! least to most significant
characters
src.adr = src.len-I-max(B,src.len-dst.len)+sre.adr;
dst.adr = dst.len+dst.adr-l;
while sre.len lssu dst.len do
begin
M[dst.adr] = fill;
dst.len = dst.len-l;
dst.adr = dst.adr-l
end;
while dst.len nequ 0 do
begin
M[dst.adr] = H[table.adr+M[src.adr]];
src.len = sre.len-l;
src.adr = sre.adr-l;
dst.len = dst.len-l;
dst.adr = dst.adr-l
end
end;
RS = sre.len;
Rl = 0:
R2 = 0;
R3 = 0:
R4 = 0<lS:8>@fill;
RS = table.adr;

HOvre only

A-55

8 7

max (0,src.len-dst.len)

R2
R3

-----------------------------------

R4
RS

" table.adr fill

In-line Form - MOVTCI
Tbe words which follow the opcode word in the instruction stream
are a word address pointer to a two word character string source
descriptor, a word address pointer to a two word character string
destination descriptor, a word whose low order half contains the
fill character and whose high order half must be zero, and a word
containing the address of the translation table.
R"-R6 are
unchanged when the instruction is completed.
Formal Description:
src.len = R0;
src.adr = Rl:
dst.len = R2:
dst.adr = R3:
~fill = R4<7:0>:
table.adr = RS;

MOvre only

temp = M[R7] ;
src.len = M[temp):
src.adr = M[temp+2]:
R7 = R7+2:
temp = M[R7) ;
dst.len = M[temp]:
dst.adr = M[temp+2):
R7 = R7+2:
rill = M[R7]<7:0>:
R7 = R7+2:
table.adr = M[R7]:
R7 = R7+2:

MOVTCI only

carry@temp = src~len-dst.len:
N = temp<lS>:
Z = temp eqlu 0:

A-56

Examples:
1.

Character Code Conversion - Register Form
MOV
MOV
MOV
MOV
MOV
MOV
MOVTC
B81
BOO
BEQ

SRC.DSCR,Ra
SRC.DSCR+2,Rl
DST.DSCR,R2
DST.DSCR+2,R3
I' ,R4
ITABLE,R5

EBCDIC source
ASCII destination
fill with ASCII spaces
translation table
translate and move
source was truncated
test for fill
test for equal length

TRUNC
FILL
EQUAL

Character Code Conversion - In-line Form
MOVTCI

translate and move

• WORD
•WORD
•WORD

SRC.DSCR.PTR
DST.DSCR.PTR

B81
BOO
BEQ

TRUNC
FILL
EQUAL

ptr to src descriptor
ptr to dst descriptor
fill is space
test for truncation
test for fill
test for equal length

Notes:
1.

The operation of this instruction is unaffected by any overlap
of the source and destination str ings.
The resul t is
equivalent to having read the entire source str ing before
storing characters in the destination.

If the destination string overlaps the trarislation table in
any way, the results of the instruction will be unpredictable.

If the source str ing is vacant, the untranslated fill
character will be propagated through the destination string.
If the destination str ing is vacant, no characters will be
Condition codes will be updated. MOVTC will update
moved.
the general registers.

MOVTC -- When the instruction terminates, Ra is zero only if Z
or C are set.

The condition codes will be set as if this instruction were
preceded by CMP src.len,dst.len.

The effect of the instruction is unpredictable if the entire
256 byte translation table is not in readable memory.

A-57

5.19

MULP / MULPI - Multiply Decimal

Format:
15

9 8

3 2

MULP

076

MULPI

076

srcl.dscr.ptr
src2.dscr.ptr
dst.dscr.ptr
Operation:
dst <- src2 * srcl
Condition Codes:
N:
Z:
V:

set if dst<0; cleared otherwise
set if dst=0: cleared otherwise
set if dst can not contain all significant digits of the
result; cleared otherwise
cleared

Suspendability:
This instruction is potentially suspendable.
Description:
Srcl and src2 are mul tipl ied, and the result is stored in the
destination string. The condition codes reflect the value stored
in the destination string, and whether all significant digits were
stored.
- Reqister Form - MULP
When the instruction starts, the operands must have been placed in
the general registers. The first source descriptor is placed in
R0-Rl, the second source des.cr iptor is placed in R2-R3, and the
destination descriptor is placed in R4-Rs:

A-58

srcl.dscr

Rl
R2

src2.dscr
I

-----------------------------------I

dst.dscr

When the instruction is completed, the source descriptor registers
are cleared: •

o
o

dst.dscr

Rs
In-line Form - MULPI

Each word address pointer which follows the opcode word in the
instruction stream refers to a two word decimal string descriptor.
R0-R6 are unchanged when the instruction is completed.
Formal Description:
TBS;

Examples:
1.

Multiply - Register Form
MOV

MOV
MOV

MOV

SRC1. OSCR, R0
SRCl.DSCR+2,Rl
SRC2.DSCR,R2
SRC2. DSCR+ 2, R3

A-59

1st source descriptor
2nd source descriptor

MOV
MOV
MULP
BVS
BLT
BEQ
BGT

DST.DSCR,R4
DST. DSCR+ 2, RS

destination descriptor
multiply

OVERFLOW
NEGATIVE
EQUAL
GREATER

,. check for error
negative destination
zero destination
positive destination

Multiply - In-line Form
folULPI
•WORD
•WORD
•WORD
BVS
BLT
BEQ
BGT

multiply
ptr to srcl descriptor
ptr to src2 descriptor
ptr to dst descriptor
check for error
negative destination
zero destination
positive destination

SRC 1. DSCR. PTR
SRC2. DSCR. PTR
DST. DSCR. PTR
OVERFLOW
NEGATIVE
EQUAL
GREATER

Notes:
1.

The operation of these instructions is unaffected by any
overlap of the source strings provided that each source string
is a valid representation of the specified data type.

The results of the instruction are unpredictable if the source
and destination strings overlap.

No numeric string multiply instruction is provided.

A-60

5.20

SCANC / SCANCI - Scan Character

Format:
15
SCANC

SCANCI

987

3 2

076

"76

----~--~-------~-----~--~----------

src.dscr.ptr

set.dscr.ptr
Operation:
Search source character string for a member of the character set.
Condition Codes:
The condition codes are based on the final contents of R0.
N:
Z:
V:

set if R0<lS> set; cleared otherwise
set if R0=0; cleared otherwise
cleared
cleared

Suspendability:
This instruction is potentially suspendable.
~scription:

The source character string is searched from most significant to
least significant character until the first occurrence of a
character which is a member of the character set.
A character
string descriptor is returned in R0-Rl which represents the
portion of the source character string beginning with the located
member of the character set.
If the source character str ing
contains only characters which are not in the character set, the
instructions return a vacant character string descriptor with an
address one greater than that of the least significant character
of the source character string. The condition codes reflect the
resulting value in R0.

A-61

Register Form - SCANC
When the instruction starts, the operands must have been placed in
the general registers. The source character string descriptor is
placed in R0-Rl, and the character set descr iptor is placed in
R4-R5:

src.dscr

R4
set.dscr

When the instruction is completed, R0-Rl contain a character
str ing descr iptor which represents the sub-str ing of the source
character string beginning with the character which is a member of
the character set:

sub.src.dscr

R4
R5

set.dscr

In-line Form - SCANCI
The words which follow the opcode word in the instruction stream
are a word address pointer to a two word character string source
descriptor, and a word address pointer to a two word character set
descr iptor • When the instruction is completed, R0-Rl contain a
character string descriptor which represents the sub-string of the
source character string beginning with the character which is a
member of the character set. R2-R6 are unchanged:

A-62

R0
sub.sre.dser

Rl
Formal Description:
sre.len = R0:
sre.adr = Rl:
mask = R4<7:0>:
table.adr = RS:

SCANC only

temp = M(R7];
SCANClonly
sre.len = M[temp):
sre.adr = M[temp+2):
R7 = R7+2:
char = M[R7)<7:0>:
R7 = R7+2:
temp = M[R7]:
mask = M[temp]<7:0>: 1
table.adr = M[temp+2];!
R7 = R7+2:
!
found = 0:
while (sre.len nequ 0) and (found eqlu 0) do
if (M[table.adr+M[sre.adr]] and mask) eqlu 0 then
begin
sre.len = src.len-l:
src.adr = src.adr+l
end .
else found = 1:
R0 = src.len:
Rl = src.adr;
R4 = 0<ls:8>@mask:
RS = table.adr:

SCANC only

N = R0<ls>;
Z = R0 eqlu 0;
V = 0;
C = 0:

Examples:

Find Next Digit - Register Form
MOV
MOV
MOV
MOV

STR.DSCR,R0
STR.DSCR+2,Rl
tl,R4
tTAB,R5

A-63

string to scan
mask for char set
character set table

SCANC
BNE
BEQ

DIGIT
NODIGIT

scan string for digits
digit found
string had no digits

TAB: • BYTE
• BYTE
•BYTE

0
0
0

ASCII 090
ASCII 001
ASCII 992

• BYTE
.BYTE
• BYTE
• BYTE
•BYTE
• BYTE
.BYTE
•BYTE
• BYTE
• BYTE
•BYTE
• BYTE

1
1
1
1
1
1
1
1
1
1
0

ASCII 060 - fe'
ASCII 061 = '1 '
ASCII 962 = '2'
ASCII 063 • '3 '
ASCII 064 = '4'
ASCII e65 = '5'
ASCII 066 = '6'
ASCII 067 = '7 •
ASCII e79 = '8 •
ASCII 071 = • 9'
ASCII 972
ASCII 073

•BYTE

ASCII 377

Find Next Digit - In-line Form
SCANCI
•WORD
•WORD
BNE
BEQ

scan
ptr to src descriptor
ptr to char set dscr
digit found
string had no digits

SRC. DSCR. PTR
SET.DSCR.PTR
DIGIT
NODIGIT

Notes:
1.

If the initial source character string descriptor is vacant,
the instruction terminates with the condition codes indicating
that no characters in the set were found. The original source
character string descriptor is returned in R0-Rl.

The source character
overlap in any way.

A test for success is BNE;

string

and

character

set

tab1~

a test for failure is BEQ.

A-64

may

The condition codes will be set as if this instruction were
followed by TST RS.

The effect of the instruction is unpredictable if the entire
256 byte character set table is not in readable memory.

A~5

5.21

SKPC / SKPCI - Skip Character

Format:
15

3 2

987

SKPC

076

SKPCI

076

src.dscr.ptr

char

Operation:
Search source character string until a character other than the
search character is found.
Condition Codes:
The condition codes are based on the final contents of R0.
N:
Z:
V:
C:

set if RB<lS) set; cleared otherwise
set if R0=0; cleared otherwise
cleared
cleared

Suspendability:
This instruction is potentially suspendable.
Description:
The source character string is searched from most significant to
least significant character until the first occurrence of a
character which is not the search character. A character string
descr iptor is returned in R0-Rl which represents the portion of
the source character string beginning which the most significant
character which was not equal to the search character.
If the
source character str ing contains only characters equal to the
search character, the instructions return a vacant character
str ing descr iptor with an address one greater than that of the
least significant character of the source character string. The
condition codes reflect the resulting value in R0.

A-66

Register Form - SKPC
When the instruction starts, the operands must have been placed in
the general registers. The source character string descriptor is
placed in R0-Rl, the search character is placed in R4<7:0>, and
R4<l5:8> must be zero:
15

8 7

src.dscr

char

When the instruction is completed, R0-Rl contain a character
str ing descr iptor which represents the sub-ser ing of the source
character string beginning with the most significant character
which was not equal to the search character:

8 7

R0
sub.src.dscr
Rl

char

In-line Form - SKPCI
The words which follow the opcode word in the instruction stream
are a word address pointer to a two word character string source
descr iptor, and a word whose low order half contains the search
character and whose high order half must be zero. When the
instruction is completed, R0-Rl contain a character str ing
descriptor which represents the sub-string of the source character
string beginning with the most significant character which was not
equal to the search character. R2-R6 are unchanged:

A-67

R0
sub.src.dscr

Rl
Formal Description:
src.len - Re;
src.adr - Rl;
char - R4<7:e>;

SKPC only

temp - M [R7] ;
src.len - M[temp];
src.adr - M[temp+2];
R7 - R7+2;
char - M[R7]<7:1>;
R7 • R7+2;

SKPCI only

found • 1;
while (src.len nequ 0) and (found eqlu 1) do
if M[src.adr1 eqlu char then
begin
src.len = src.len-l;
src.adr = src.adr+l
end
else found = 0;
RS • src.len;
Rl - src. adr;
R4 • 0<15:8>@char;

SKPC only

R8<lS>;
Z - R0 eqlu 0:
V • ih

N •

C • 0;

Examples:
1.

Skip Leading Spaces - Register Form
MOV
MOV
MOV
SKPC
BEQ

STR. DSCR, R0
STR.DSCR+2,Rl
•• ,R4
BLANK

A-68

string to search
space character
skip
line was blank

Skip Leading Spaces - In-line Form
SKPCI
.WORD
•WORD

SRC.DSCR.PTR

8EQ

BLANK

skip
ptr to src descriptor
space character
line was blank

Notes:
1.

If the initial source character string descriptor is vacant,
the instruction terminates with the condition codes indicating
the character string only contained search characters.
The
original source character string descriptor is returned in
RS-Rl.

The condition codes will be set as
followed by TST RS.

A-69

this instruction were

5.22

SPANC / SPANCI - Span Character

Format:
15

987

3 2

SPANC

076

.04

SPANCI

076

src.dscr.ptr
set.dscr.ptr
Operation:
Search source character string for a character which is not a a
member of the character set.
Condition Codes:
The condition codes are based on the final contents of R0.
N:
Z:
V:
C:

set if R0<15> set; cleared otherwise
set if R0=0: cleared otherwise
cleared
cleared

Suspendabi1ity:
t

This instruction is potentially suspendable.
Description:
The source character string is searched from most significant to
least significant character until the first occurrence of
character which is not a member of the character set. A character
string descriptor is returned in RS-Rl which represents the
portion of the source character string beginning with the
character which is not a member of the character set.
If the
source character string contains only characters which are in the
character set, the instructions return a vacant character string
descriptor with an address one greater than that of the least
significant character of the source character string.
The
condition codes reflect the resulting value in R0.

A-70

Register Form - SPANC
When the instruction starts, the operands must have been placed in
the general registers. The source character string descriptor is
placed in R0-Rl, and the character set descr iptor is placed in
R4-RS:

15
R0
src.dscr
Rl

R4
set.dscr
RS
When the instruction is completed, R0-Rl contain a character
str ing descr iptor which represents the sub-str ing of the source
character string beginning with the character which is not a
member of the character set:
15
R0
Rl

sub.src.dscr

R4
set.dscr
RS

In-line Form - SPANCI
The words which follow the opcode word in the instruction stream
are a word address pointer to a two word character string source
descriptor, and a word address pointer to a two word character set
descriptor.
When the instruction is completed, R0-Rl contain a
character string descriptor which represents the sub-string of the
source character string be<]inning with the character which is a
member of the character set. R2-R6 are unchanged:

A-71

15
R0
sub.sre.dser

Rl
Formal Description:
sre.len = R0;
sre.adr = Rl:
mask
R4<7:0>;
table.adr
R5:

SPANC only

:II

temp = M[R7);
SPANClonly
sre.len = M[temp):
'sre.adr = M[temp+2):
R7 = R7+2:
ehar = M[R7]<7:0>;
R7 = R7+2i
temp = M[R7] ;
mask = M[temp]<7:0>:
table.adr = M[temp+2];!
R7
R7+2:
!
:II

found = 1;
while (sre.len nequ 0) and (found eqlu 1) do
if (M[table+M[sre.adr]1 and mask) nequ 0 then
begin
sre.len = sre.len-l;
sre.adr = sre.adr+l
end
else found = 0;
R0 = sre.len;
Rl = sre.adr;
R4 = 0<15:8>@mask;
R5 = table.adr;

SPANC only

N = R0<15>;

Z = R0
V = 0;
C = 0;

eqlu 0;

A-72

Examples:
1.

Pass Tabs and Blanks - Register Form
MOV
MOV
MOV
MOV
SPANC
BNE
BEQ

string to scan

STR.DSCR,R0
STR.DSCR+2,Rl
t2,R4
'TAB,RS

character set mask
character set table
span
printing char found
string contained only
tabs and spaces

FOUND
EMPTY

The following table can be combined with the one
in the SCANC example.

TAB: • BYTE
• BYTE
• BYTE

0
0

.BYTE

• BYTE
• BYTE

0
0

ASCII 000
ASCII 001
ASCII 002

ASCII 011 = TAB
ASCII 012
ASCII 013

• BYTE

•BYTE

ASCII 040 = SPACE
ASCII 041
ASCII 042

•BYTE

ASCII 377

Pass Tabs and Blanks - In-line Form
SPANCI
• WORD
• WORD

BNE
SEQ

scan
ptr to src descriptor
ptr to char set dscr
printing char found
string contained only
tabs and spaces

SRC. DSCR. PTR
SET. DSCR.PTR
FOUND
EMPTY

A-73

Notes:
1.

If the initial source character string descriptor is vacant,
the instruction terminates with the condition codes indicating
that only characters in the set were found.
The original
source character string descriptor is returned in R0-Rl.

The source character
overlap in any way.

The condition codes will be set as if this instruction were
followed by TST R0.

The effect of the instruction is unpredictable if the entire
256 byte character set table is not in readable memory.

string

A-74

and

character

set

table may

5.23

SUBN / SUBP / SUBNI / SUBPI - Subtract Decimal

Format:
15

320

9 8

SUBN

076

SUBP

076

SUBNI

076

srcl.dscr.ptr
-~-------------~-~------~~----~-~--

src2.dscr.ptr

dst.dscr.ptr

SUBPI

076

srcl.dscr.ptr
src2.dscr .ptr
dst.dscr.ptr
Operation:
dst <- src2 - srcl
Condition Codes:
N:
Z:
V:
C:

set if dst<0; cleared otherwise
set if dst-O; cleared otherwise
set if dst can not contain all significant digits of the
result; cleared otherwise
cleared

Suspendability:
This instruction is potentially suspendable.

A-75

Description:
Srcl is subtracted from src2, and the result is stored in the
destination string. The condition codes reflect the value stoted
in the destination string, and whether all significant digits were
stored.
Register Form - SUBN and SUBP
When the instruction starts, the operands must have been placed in
the general registers. The first source descriptor is placed in
R0-Rl, the second source descr iptor is placed in R2-R3, and the
destination descriptor is placed in R4-R5:
15
R0
srcl.dscr
Rl
R2
src2.dscr
R3
R4
dst.dscr
R5

. I

When the instruction is completed, the source descriptor registers
are cleared:

15
R0

Rl
R2
R3
R4
dst.dscr

A-76

In-line Form - SUBNI and SUBPI
Each word address pointer which follows the opcode word in the
instruction stream refers to a two word decimal string descriptor.
R0-R6 are unchanged when the instruction is completed.
Formal Description:
TBSJ

Examples:
1.

Three address subtract - Register Form
SRC1. DSCR, R0
MOV
SRC1.DSCR+2,R1
MOV
SRC2.DSCR,R2
MOV
SRC2.DSCR+2,R3
MOV
MOV
DST.DSCR,R4
DST.DSCR+2,RS
MOV
SUBN / SUBP
OVERFLa4
BVS
NEGATIVE
BLT
EQUAL
BEQ
BGT
GREATER

minuend descriptor
difference descriptor
subtract
check for error
negative destination
zero destination
positive destination

Three address subtract - In-line Form
SUBNI /
•WORD
•WORD
•WORD
BVS
BLT
BEQ
BGT

subtrahend descriptor

subtract
ptr to sub descriptor
ptr to min descriptor
ptr to dif descriptor
check for error
negative destination
zero destination
positive destination

SUBPI
SRC 1. DSCR. PTR
SRC2. DSCR. PTR
DST.DSCR.PTR
OVERFLOW
NEGATIVE
EQUAL
GREATER

Two address subtract - Register Form
subtrahend descriptor

SRC.DSCR,R0
MOV
MOV
SRC.DSCR+2,R1
DST.DSCR,R2
MOV
DST. DSCR+2, R3
MOV
MOV
R2,R4
MOV
R3,RS
SUBN / SUBP
OVERFLOW
BVS
NEGATIVE
BLT
BEQ
EQUAL
BGT
GREATER

minuend descriptor
difference descriptor
subtract
check for error
negative destination
zero destination
positive destination

A-77

Two address subtract - In-Line Form
subtract
ptr to sub descriptor
ptr to min descriptor
ptr to dif descriptor
check for error
negative destination
zero destination
positive destination

SUBNI / SUBPI
SRC.DSCR.PTR
•WORD
• WORD
DST.DSCR.PTR
DST.DSCR.PTR
• WORD
BVS
OVERFLOW
BLT
NEGATIVE
SEQ
EQUAL
SGT
GREATER

Notes:
1.

The operation of these instructions is unaffected by any
overlap of the source strings provided that each source string
is a valid representation of the specified dat type.

Source strings may overlap the destination string only if all
corresponding digits of the strings are in coincident bytes in
memory.

A-78

APPENDIX B
CIS MPC FUNCTIONS

740
741
742
743
744
745
746
747
750
751
752
753
754
755
756
757
760
_ 761
762
763
764
765
766
767
770
771
772
773
774
775
776

RILRI2
ROL_ROL
RIL_RIL
R2L_R2L
R3L_R3L
R4L_R4L
R5L-R5L
R6L_R6L, ENAB STOV
R7L_R7L
BA,R6_R6-2, ENAB STOV
BA, R6_R6+2, ENAB STOV
R14_R14
RIO_RIO
R6_R6, ENAB STOV
R7_R7
RI2L-RI2L
R13L-R13L
R14L_RI4L
RIOL-RIOL
PSW-PSW
BA-R6, DATI (0), B_UOATA
BA-R13, DATI (0), EXTERNAL.UOATA
BA-RI4, DATI (D), EXTERNAL.UDATA
BA-RIO, DATI (D), EXTERNAL.UDATA
BA-RIO, DATI (D), B_UOATA
BA-RIO, DATI (I), B_UDATA
BA-R6
BA-RIO
DATO(D), UDA TA-B
DATOB(D), UDATA-EXTERNAL
BA-RIOL

B-1

APPENDIX C
CIS ABBREVIATIONS

Abbre,iadon

Definition

ADR
ALU
AREG
B
BR
BREG

Address
Arithmetic logic unit
"A" register (of BCD path)
Borrow
Bus request
"B" register (of BCD path)
Carry (condition code)
Carry lborrow bit
Condition code
Commercial instruction set
CIS processor
CIS scratch pad write
CIS status
Control
CIS program counter
Descriptor
Destination
Data type
Function
Field programmable logic array
Carry generate
General purpose register
Input buffer
Instruction
Instruction register
Load 2 descriptor
Load 3 descriptor
Local store
Default value
Microprogram counter
Negative (condition code)
Overflow
Carry propagate
Processor status word
Source
Overflow (condition code)
Zero (condition code)

C
C/B
CC
CIS
CISP
CISPW
CISS
CNTL
CPC
DESCR
DST

DT
FNCT
FPLA
G
GPR
IBUF
INST
IR
L2dr
L3dr
LS

m
MPC
N
OVR
P
PSW
SRC
V

C-l

APPENDIX D
CISP MNEMONICS

Microword

Definition

ALUDST
ALUfTN
ALUSRC
APORT

ALU destination field (61 :59)
ALU function field (58:56)
ALU source field (55:53)
"A" address field of 290 I A RAM

BCDMX]
8CDMX3
8COOP
BMUX
8PORT

BCD multiplexer 1 field (29:28)
BCD multiplexer 3 field (3] :30)
BCD operation field (33:32)
B multiplexer field (35:34)
"8" address field of 2901 A RAM

CISSPW
CON2
CON3
CON4
CONBRI
CONBR2
CONST

CIS scratch pad write field (71 :70)
Control 2 field (27:25)
Control 3 field (24:21)
Control 4 field (20: 16 )
Conditional branch 1 field (5:2)
Conditional branch 2 field (9:6)
Constant field (40:38)

ENCB
ENCIS
ENIB
ENOB
ENSNIN
ENSNOU

Enable carry/borrow bit (0)
Enable CIS bit (1 )
Disable input buffer bit (48)
Enable output buffer bit (47)
Enable sign input bit (37)
Enable sign output bit (36)

INEN

Input enable bit (5])

L8YTE

Low byte enable bit (46)

MPC

Microprogram counter field (15: 1O)

SALUI
SHFfC
SHfTlN
SWAP

Select ALU input bit (52)
Shift control field (63:62)
Shifted in bit (64)
Swap bytes in a word or in a data string (50:49)

D-l

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KE44-A CISP
TECHNICAL MANUAL
EK-KE44A-TM-OO 1

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