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EK-KD11Z-TM-001

December 1980

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Document:	1144 SystemTechMan
Order Number:	EK-KD11Z-TM
Revision:	001
Pages:	261
Original Filename:	1144_SystemTechMan.pdf

OCR Text

PDP-11/44 System
Technical Manudal

dlilgliltlall

EK-KD11Z-TM-001

PDP-11/44

System Technical Manual

digital equipment corporation - maynard, massachusetts

First Edition, December 1930

The material in this manual is for informational purposes and is
subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:

DIGITAL
DEC
PDP

DECsystem-10
DECSYSTEM-20
DIBOL

DECUS
UNIBUS

EDUSYSTEM
VAX

0S/8
RSTS
RSX

VMS

IAS

9/82-14

MASSBUS
OMNIBUS

CONTENTS
Page

GENERAL. ...t
ettt ettt
tt
et et e s e e e s e eanans
EQUIPMENT DESCRIPTION..........ett
ettt e ba et e b e e e enttraeeeebbeeeeaareeeenrreeas

B LW

=
N
W

it et ok e
= et

W
R —

W RN
B
A

DN DN

BRW

ek
et
i
ok pd
et
et bk
e
ek
ek
et
et
ek
ki

ninin
s e
N =
L

ket

PRhREAEAAERARADERAPADL

)

p—

—

INTRODUCTION

LW WL
-

CHAPTER 1
f—

PREFACE

CHAPTER 2

PDP-11/44 CA, -CB Processor SYStEM .......ccveceeeeeeeeeeereeeeresessereeenseessennn.
PDP-11X44 Processor SYSTEM.......c.ccviivriivieviiinnieceieeeeseeeseeeesereeersseseesenns

1-1
1-3

1-3
1-4

Standard Hardware COmPONEnts ...........c.ooovvievieeeeeeeeereeeeeeeeeereeereeereeeseens
1-5
Hardware OPtions.........oocceiiiiiiini
ettt
eeiecrececce
e e e e et e s
1-5
EQUIPMENT SPECIFICATIONS......oootiiieeeeeeeeee e
1-5
PDP-11/44 System Specifications ...........ccccuvveiiiiirinieneseeeeeeeeeeeeeeeeseenns
1-6
PDP-11X44 System SpecifiCations ..........cccceouveivevervieiieeeseeeeeeeeereseressenesenns
1-7
H7140 AA, -AB Power Supply Electrical
SPECHICALIONS. ...eveiiiitirieiiiiere
ettt
eeeeeeee s e enes
1-9
SYSTEM DESCRIPTION .....cootiiiiiiiiieticcecteeeece
et
seteete
e, 1-10
KD11-Z Central ProCESSOT ...ccvviiiieeiiieiieereteieececeie
ettt eeee e eeeesve e
e 1-12
Data Path Module (M7094) ........cooiiiiiiiiiee ettt 1-12
Control Module (M7095) ....uuoiuiiiieiieeiiieceeceeeteeeee
e
eea e, 1-12
Multifunction Module (M7096)........ccccevmrieiieeeeeeeeeeceeeeeeeeereeeeeeere
e, 1-12
UNIBUS Interface Module (M7098) ....ccoovviiioieeeieeeeeeeeeeeeeeeereeeseinnenn 1-13
Console Interface Module (M7090)........coovevieiiieeeeeeeeeeeereesieeeeieseinns 1-13
MOS MEMOTY...uviiiiiii
ettt ettt et eeaeeeeeeteeeee
eniiinti
s e eesessseesreas 1-13
KK11-B Cache MEemOIY ......ccouiiiettt
ieiiiiiictiii
eeee e e e e tic
e eaeaens 1-13
UNIBUS Terminator (M9302) .....uuiiiii
e e eeeeeeeeeeeesseseeeeeeeasessaneees
iiiiiiieeie 1-13
Optional Modules and DeviCes .........oouieviirriiiiiiiiiiieieeeeeee
e eeeeeeee e 1-13
FP11-F Floating-Point Processor..........c.ocvvivviiiiiiiienereeeeeeeeee
e,
ee 1-13
KE44-A Commercial Instruction Set
PrOCESSOT ... iiiiiiiciiectiice ettt
s e 1-13
TUSE DECape I ....c.ooiiiiiiiieciee
ettt 1-13
Standard PDP-11 Peripheral Devices ........cccovvvvviveeeeerieeeeeeeeeeeeenenns 1-14
RELATED DOCUMENTS ......ooiitiiiieeeee
ettt sttt
ee
eee
ane e 1-14
DIGITAL Personnel Ordering ......c..oeeevveeeviiiveciiniieeeeeeeeeeeeeeeee
e eeeees e, 1-15
Customer Ordering Information............ccccuovvieiiiiiniiiiiireeeeeee
e eeee
1-15

OPERATION

FRONT CONTROL PANEL........ooommvimiririrnerensreonnees
eeesessiesee
eeeeseneeneee

2-1

CONSOLE COMMANDS ......coo
ettt
iitieceee
ettt e s eaeeerasaes
ct
2-3
SPecial FUNCHONS. .....ccuiiiiiiciecier
ettt s e e eae s e s eneeseees
2-3
Console Command Qualifiers............cccoviveiviineiniiniiieecreeeeeeeeeeeeeene
e 2-4
Special Address Field Characters .........ooovvvviiviiiecieseeeeeeeeeeeeeveeeen, 2-4
(670
115 (0] W31 1:1 - 101 1 £ OO
S RUTUURURTUPRUURRP
2-4
ADDER Command ........cooccoeiiiiiiiiini
et
icice
ea e e e s
2-7
BOOT Command.........ccceeuiiieiiiiei
st esteseeseeeeeeeseaeseseeeesesna
eiiiciiicctecees
2-8
CONTINUE Command..........ivceceeveeieienriiiseciicieceesteseeseereseereseesneeeeeneenes 2-10
DEPOSIT Command .........cccocueeeuiiviiiniiinrioniecieeei
et eeveesaeeseeseeseeesaeas
esteese 2-11

2.2.6
2.2.7

2.2.8
2.2.9

2.2.10
2.2.11

2.2.12
2.2.13

2.2.14

2.2.15

EXAMINE COMMANG . .covveiiiiiieeeeeireeeseetnereeeeeenseeessesnessssessesssssesnseseesanes 2-11
FILL Command..........c.cooiiiiiiiieiiiieiiiiiine
e eeiieee et serreessenaeeesesnneeesennne 2-13
HALT Command..........ooovviiimiiiiiiiieienieteeeeersciiirereereeereeeessssessssssssnsnsssesnecenns 2-14
INITIALIZE Command .......cccccceveiirmiiiiineenniirieeecniieeeeee
e siiiieeeeessnneeeees 2-14
MICROSTEP Command .........ccccvvieriiriiiiiireiensiiireeeessnirreeeeeesssmeeeeeeessemnees 2-14
SINGLE-INSTRUCTION-STEP Command .........cccccceeevvivvvereeinnninennnennnnns 2-15
START Command........cccccciieriiiiiiieiniiiresiirreeesiieeessueeeeessmneessssseneesssseessssnnee 2-16
SELF-TEST Command........ccccoceeiiiiiiiiiiie
e escrercee s seinrreeeessenneneeeas 2-16
BINARY LOAD/UNLOAD Command......c.ccccouevirviiiiiniiiiiniciiinenien, 2-16
REPEAT Command......ccccoiiuiiriiiiieiiiiiiinniiciiiineeereeeeeeeeessesssessnsmmesnrnesseeeessessns 2-17

2.3.1 2

Summary of Errors............ et tereeereeeeen i ——reeessa i attrteeeea it rraesesaearrttaeeessanrnnes 2-17
Summary of Commands ........cccevvuiiiiiiiiiiiiiieeerrere
e 2-18
PDP-11/44 REGISTERS........ccoirc 2-18
CPU REGISIEIS c.ciciiiiiiiiiiiiiiiiiiiireee
s
rerrree et e s e s e e s e s s ssabrsreraaeeeeeesasesas 2-18
Processor Status Word .......coovccvviieeiinniinrerniniiirreeennriirnee
s ssineeeessesans 2-20
Program Interrupt Request RegiSter......cccevvvvvvveiiiirrriieereeeeeenneninnennnnns 2-22

2.3.1 3

EITOT REZISTET .. uuuuiiiiiiiiiiiiiiieeiiiei
e icirterteee e e e s e enenrreeenr e eeeneessssnnen 2-22

2.3.1 4

General REGISTEIS ..ovuuvuuiiiiiiiiiiiiiiiirerecrrresrreesreee
e s s re e s eeeeeeeeeseeeerearnnereneeens 2-25
Multifunction Module REgISter.........ccovviiiiiiiiiiiiiiieccerrireee
e ereiirieee e 2-25
Console Terminal Receiver Control/Status
REISTET ittt
e e et e e s e s s s sbab e e reeaaeeeeeesssansanas 2-25
Console Terminal Receiver Data Buffer
REGISTET oottt
e e s rrr e e e e st ra e e e s e nares 2-26
Console Terminal Transmitter Control/Status
REGISTOT i
e 2-27
Console Terminal Transmitter Buffer
2T
4 T 1) PP
UPPPPPPPPRR 2-28
TUS58 Receiver Control/Status Register ... 2-29
TUS8 Receiver Buffer Register .......oovvvveviiiiiiiiiiiiiiiiinec
e, 2-30
TUS58 Transmitter Control/Status Register........cccecvevviiniiiniinniennncn. 2-30
TUS8 Transmitter Data Buffer Register.......ccocccvvviivivniiiiieieiinvinnenenn. 2-32
SIENAl REEISTET ..ovvviiiiiiiiiiieiiec et
eesrr e e e e s saibreeees 2-32
Line Time Clock Control/Status Register........cccovvvvrrverieeriiernieerneennne 2-33
Cache Memory [/O Page RegiSters ........occovuvieiieninieninienenienieneeie
e, 2-34
Cache Memory Data Register.......ccccoviiiiiiiiiiiiiiiiiiiiiiiiiiiicieee, 2-34
Cache Hit RegiSter.......ccooiiiiiiiieee
e 2-35
Cache Maintenance Register..........coooviiiiiiiiiiiiiiccccnrrrreeeeee
e, 2-35
Cache Control/Status RegiSter.........cccceviiriinernieeniniinenreeeeeeereene 2-37
Cache Error Register....ccccooviiiiiiiiiiiiiiiiiiccec
ettt ee s s e s 2-39
Memory Management REZISLErs ........cocccviiiiiiiiiiiiieeri
e 2-40
Status Register 0 (SRO) ....oovviiiiiiiiiiii
e vv—. 2-40
Status Register SR .....c.oooiviiiiiiiiiiecc
et
es e 2-42
Status Register SR2 .....cocoiiiiiiiii
e 2-42
Status Register SR
3 ..o
e 2-42
Page Address RegISters . ....ccovvviiiiiiiiiiiiiiiiiccciieees
et eecrere e 2-44
Page Descriptor RegiSter.....cccuviiiiiiieeiiiiieecccciireee ettt 2-44

2.2.16

2.2.17
2.3
2.3.1
2.3.1.1

2.3.2

2.3.2.1
2.3.2.2
2323
2324

2.3.2.5
2.3.2.6
2.3.2.7

2.3.2.8
2.3.2.9

2.3.2.10
2.3.3
2.3.3.1

2.3.3.2

2.3.3.3
2334

2.3.3.5
2.34
2.3.4.1

2.34.2
2.343
2.3.44
2.3.4.5

PROCESSOR BACKPLANE ASSIGNMENTS.......cooiiiirtreeee
e
Backplane Assembly Pin Designations..........ccoceeeerecviieeeesieccineeneeeesennnnnneeeae
Module Contact Designations..........ccccccecviieiiiiiiiiiieieececicireeeeeeereerreeeeeeesssnnnens

CPU CONFIGURATION

CHAPTER 3
W

2.3.4.6

3-1
3-3
3-6

S G I

W N

nh W~

Sy apap Ay

b —

WLWWWWWWWWWWLWWWWWWNINN
=

[\S

e
W

b ek pemd et e
it
DN NI DD rem

R DO
—

st
et

CHAPTER 4

4.2.2.1

SPC MOAUIE INStALIATI0N 1 .tvverreierreereieeineereeeitterranertiestneersiresieesaassressnsaeennees 3-6
MODULE CURRENT REQUIREMENTS ..o, 3-7
DC Power REQUIFEMENTS ..ecvvvereiiniiiiiiiiiiiiiiiit et 3-7
s 3-9
s esiiaesa e
H7140-AA, -AB DC Power QUEPULS ....oveveeeiieiiiiiiiriree
MODULE SWITCHES, JUMPERS AND INDICATORS ..o 3-10
Console Interface Module (M7090) ......ooeviiiiieeeiimiiiiieieeeniiree 3-11
e, 3-11
Console Terminal Configurations..........eeeeevvreeeeiiiininiiiinniiniineeen
TU58 DECtape II Configuration........ccocvvmiiiiiiiiiiiiinciinniiiiceieee 3-11
Remote Diagnosis Configuration ..........ccoeeevviiiiiniiiinininiiiinieneees 3-14
Voltage MONILOTING ...ccccvverriiiiiiiiiiiiiiiiinitie e 3-14
LED INAICATOT ...cvvvvieeiriirieeeeirreeeeirreeseieeeeessinntesssnsnnseessasnesssesrasaasnsnns 3-14
s 3-14
iire
siee
st
Multifunction Module (M7096) .......ccovvieeirreeeiiiiiiiiiriiiee
Console Terminal Jumper Leads Selections.........cccooieviieniininiinniennne 3-14
MFM Console Terminal Baud Rate Selection.........cccccveiiviiininnnniin, 3-15
MFEM TU58 DECtape IT Jumper Leads......ccoccovviiiiiiniiiniiniiiine, 3-16
MFM TUS58 Baud Rate Selection.......ccovvieiiiiiiiiniiiniiiniienneees 3-16
MFM TUS58 Device Address Selection..........eooeeeeeviniiiiiiiiiiniiiniinnen. 3-16
TUS58 Vector Address Selection..........oovviiiiiiiiiineeiieiniieniineieeeeee 3-16
Line Time Clock Enable/Disable ........cccooviviiniiniiniiniiiiiienee, 3-18
s 3-18
UNIBUS Interface Module (M7098) ....ccoooiiiiiiiiiiiiiiiiiiitinicc
Page
Memory
and
UBI Jumper Leads
besaraaseeees 3-18
staaeeaaaaae
Selection.....cccceeeveeeeeeinnnnn,e eeerereeetbbba—b———————ttaataaaa
Diagnostic and Bootstrap Loader ROMS ..o 3-21
Cache Memory Module (M7097)......ccooviiniiiiiiiiiiiiiiniinieesen 3-23
LED Indicator FUNCHions ......ccccceeeriiveeieniienieniinieniiiiree e 3-24
Multiport Memory Selection.........cccviviiiiiniiiiniinine, 3-24
Control Module (M7095) .t 3-24
INSTALLATION

st s s eeibess s srnaa s e 4-1
tt
it cssinrr
SITE CONSIDERATIONS ... ot
e 4-1
Temperature and Humidity ......c.ccoovevviiniiniiniininii
e 4-1
Acoustical DampPening..........ccooveeiiiiniiiiiiiiiiie
t 4-1
tt
re ett
LAZREIIIE 1.vveveereeieeeie et
Static BleCtriCity . coiiiiiierireeniieciiiiieni i 4-2
ShOCK aNd ViDIAtiOn ...ovviveiiviriieeeiiiireesiireeesesereeessinteesesiireeeessssrseessssssssassssaes 4-2
Electrical Interference. ...ooouvvviiiieiiiiiiiiiiiee et 4-2
s s ae s s sabe s s sas e s ssssanasasss 4-2
seitee e e s e s sbeessbr s sastt
UNPACKING....t
niini 4-2
iiiimniinci
.......ccco
Removal
Unit
-CB
PDP-11/44-CA,
4-4
iiinniinienenn.
ccveviiviiiniiiiiii
Removal..........cc
Cabinet
-CB
,
PDP-11X44-CA
Shipping Restraint Removal ...........coviiiiiinni 4-5
EQUIPMENT DIMENSIONS ....cccoiiiiiiiiiiineieieniesn s 4-8
iiee 4-8
e
AC INPUT POWER REQUIREMENTS ......ccooiviiiiiiiiii
Power Connections (AC) ....c.vveevveeeiiien i 4-10
System GTOUNAING ....c.ccceviiiiiriiiiiniitiiire e 4-10
PDP-11/44 MOUNTING BOX INSTALLATION ....cccocoiviiiiiiiiiiiiie, 4-12
e 4-13
sebre e sanee o
eeniiieniii
et
Index Plate MOUNTING ....cceeiuvieiiiiienie
Slide Assembly MOUNTING....ccccoriiiiiiiiiiriiniiiireenrtie e 4-14
Mounting Box to Slide Installation.........coieiiiiiin, 4-17
PDP-11X44 SYSTEM CABINET INSTALLATION ....cccccoiiniiiiiiiieiecee 4-19
Base Stabilizer Installation.......ccccevuimmeiierrriiciniiieiiniinirseeee 4-19
ieitiiie 4-20
e e sttt sb e sttt
ettt iiieiris
SEIVICING ATEA ..ecveiveruieeee

4.7
4.7.1
4.7.2
4.8
4.8.1
4.8.1.1
4.8.2
4.8.2.1
4.9
4.9.1
49.1.1
4.9.2

RTOTRTUOR 4-21
CABLE ROUTING. ............c.....U
Mounting Box Cable ROULING......ccccccvvviiiniiriiiiiiiiiire 4-21
PDP-11X44 Cabinet Cable ROULING.........vvvvimimiiiiiiiiiiiniiineinnecenne, 4-21
POWER CHECKS.....ooiiiiiiieieee
ettt eseirrre e s s essirree e e s snebneeessecnnnneessssssnanns 4-21
AC POWET DiStIIDULION ..vvvvvviiireieiieeeeeieiiciiiiieirrreeerreeeeseeessssssssrassrereeeeessseeenes 4-22
Initial AC Power CheCKS....ooioiiiiiiiiiiiiiiiirrcerieeeinncenininnninre
e 4-23
eee 4-23
sssennnneeses
iiiieeiiinirr
e eeciirreeesessrrreeeesssnreeeeeese
DC Power DiStriDULION ...ecciveiiii
DC POWETr CRECKS......ioiiiiiiiiiiiiiiieriirritreetee
e e e seseeerseeeeeecesseessssssssssnnnnns 4-23
PERFORMANCE EVALUATION ...ttt 4-25
MAINDEC Diagnostic Programs ........cccccccccevvviiviiniiiiininininienneeenne. 4-25
Diagnostic Designations .........ccccevvvveeriiiniiieiiiiieiiniiniieee
e cenineee s 4-25
Internal Diagnostic Programs..........cccovcviviiiiiiniiniiiiiniiiiieie
e 4-26

CHAPTER 5

REMOVAL/REPLACEMENT PROCEDURES

5.1
5.1.1
5.1.2
5.1.3
5.2
5.3
5.3.1

BA11-AA, -AB MOUNTING BOX IN SYSTEM CABINET.........ccccoconinennne. 5-1
Mounting Box Removal........cccooociiniiiiiiiiiiniiiiiicne
e, 5-2
Interface Bracket Removal/Installation .......ccccvvvvvnieiniiniiniiniinniiinnn., 5-8
Mounting Box Replacement .........cccovveviviiiiniiiiiniiiiiiii
e 5-8
BA11-AA, -AB SLIDE MOUNTED REMOVAL /REPLACEMENT................ 5-10
FAN ASSEMBLY .ottt
s st eessieesesssre e s sabnnessssnasssssnaanesssanbenes 5-10
Fan Assembly Removal/Replacement.........ccoovviiiniiiniiniiinininiiinninnn, 5-10

5.4.1
542
5.5
5.5.1
5.5.2
5.5.3
554

Power Supply Removal........ccoooiviiiiiiiiniiiiiiie
e 5-12
Power Supply Replacement..........cccooveveiiniiiiniiiiniiiniiieiinceeenines 5-15
OPTIONAL BACKPLANE ASSEMBLIES........coociiiiiiiiiieccine, 5-16
Optional Backplane Configurations...........ccoccvveviviiiniiiniiiiniieniiininnnennnenne. 5-18
Backplane Assembly Installation.........ccoccovveiniiiiniiniiniiiiiiine, 5-18
Backplane Connector ASSIZNMEnts........cccovevvieiiniiniiiniiiiiiieeenre
e 5-21
NPG and BG Jumper Lead Routing .......c.cccovvvvirivieeiinviieninniciiiinenn 5-22

5.4

5.5.5

5.5.6
5.5.7

H7140-AA, -AB POWER SUPPLY
REMOVAL/REPLACEMENT ......ccocoiiiiiiiiiniiinie 5-12

Standard and Modified Backplane Locations ........cc.cccceeveerivniiiiiiniiinnninnne, 5-23

SPC Backplane LOCAtiONS. .....ccoccvirueeeerierieriinieneennieeeseinesiesneseineenesnsenee
s 5-23

Backplane Power Connections...........ccccevcvrverimimiiiiiinieenieee
e
eennnnes 5-23

CHAPTER 6

DETAILED FUNCTIONAL DESCRIPTION

6.1
6.2
6.2.1
6.3
6.3.1
6.3.2
6.3.3

INTRODUCTION. ..ottt
svtre et essiereessenraeessnnneesssbbaeessssasaeessnnnnns 6-1
CONTROL STORE ..ottt
inss e csanae s snne s snaas s s 6-1
J\Y $163 (0] S OX € 131153
221 4 o) + LSRR USSR 6-1
DATA PATH......oeeeeeeeeeccee ettt e e sras s ssaaa e s s abaae s sabaeeeens 6-5
Arithmetic Logic Unit (ALU) ....ccooviiiiiiiiieiiiiinceeerineneeccnn
e, 6-5
ALU B-Leg LOZIC....ciiiiiiriiiiiieeeeiriieieeeeinttte
e ssnineee s 6-5
ALU Multiplexer (AMUX).....coovvriiiiiiiiniiiiniciniiiiiinennee
s 6-10
Swap Sign Extend Multiplexer (SSMUX)......cccccevviiniiinniinniiiniiniiiininenn 6-12
Scratchpad MEMOTY ...c.ccuveriieeeiireeiiiiecie
e 6-12
Scratchpad Operation .......... F
PP
URUROPRRRORRY . o £
Processor Status Word (PSW). ..o iiieerrerrrrrereeerreesn
s e e s s e e e e 6-15
INSTRUCTION DECODE........cociieiiieeinierrcireniressnie
e
sanssssneesons 6-16
INStruCtiON ClaSSES....ccceiiiiriireririieeereee
e e e eeererereretereee e s e s e s ssssasnnsrarres e 6-17
Double Operand and Branch Instructions.........cceecvvvviiiniiiiniiiiinnnnn, 6-17
Single Operand INStruCtIONS......cccoiivviiiiiieiiniiiiieecn
i, 6-18

6.3.4
6.3.5
6.3.5.1
6.3.6
6.4
6.4.1
6.4.1.1
6.4.1.2

6.4.1.3
6.4.2
6.4.3
6.5
6.5.1

6.5.1.1
6.5.1.2
6.5.1.3
6.5.1.4
6.5.1.5
6.5.2
6.5.2.1

6.5.2.2
6.5.2.3
6.5.2.4
6.5.3
6.5.4
6.6
6.7
6.8
6.8.1
6.8.1.1
6.8.1.2
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
6.9
6.9.1
6.9.2
6.9.3
6.10
6.10.1
6.10.2
6.10.3
6.10.4
6.11
6.11.1
6.11.1.1

MiSCEllaneous INSTIUCTIONS .....cvvveueeeeeieetieeeeriieeeeeeteeeeesrseeeeeserssereesssnnreess 6-18
Miscellaneous Decoding for Reset Instruction
ANA T Bit .o
et 6-19
ALU Auxilliary Control .............. ett
ettt et e
et e e ee et bt raeee e e bbraeeeeaenrarres 6-19
DATA TRANSFER LOGIC ...ttt 6-21
UNIBUS Transfer LOZIC......uuuiiiiiviiiiiiiiiieiniieieceieeee
e ssreeeeesvteeeeesieeens 6-21
Processor Clock Inhibit .......cccoccvviiiiiiiiniiieniic
e 6-21
UNIBUS Synchronization ........cccccecueeivieeeiciieenineec
e
cenneeenn 6-21
BUS CONIOL..ccciiiiiiiiiiiciiiicciie ittt 6-22
Generation of MSYN and MSYN/SSYN Timeout..........cccevrveeveeneenn. 6-23
Restarting Processor ClOCK ......ccuiiiiuiiivrireeiniee it 6-25
BUS ATDILIALION ....veveiiecieeieeiecr ettt
ettt e en et e see s 6-25
T

e 6-25
Request Synchronization.........cc.ueeccviiiiieeinieeiniee e 6-27
SACK TIMEOUL...cccuiiiiiiirieeiiieiieeeieeere
ettt eeee et eereeereesrbeesaeeens 6-27
Programmed Interrupt Request (PIRQ)......ooovvviivviiiiiiiiiiiiiiireeceennee, 6-29
EITOT LOZIC coineiieeeiiii ittt
et
eate e 6-29
Cache INterface ......ccviiviiiiiiiiiiiiic
e 6-30
SYSTEM CLOCK ...ooiiitiiiiiiiciieeeittcnitee
e srtreeeerree e sves e et sree s sbaesenbbesssneseeas 6-30
POWER FAIL/AUTO RESTART ......coooiiiiiieeeceeceeceectee et 6-33
MEMORY MANAGEMENT ..ottt 6-36
RElOCALION ...ccuuiiiiiiiieiite ettt
b e e eabe e eree s ebeeeereeeens 6-37

BUS REQUESES ..coiiiiiiiiiiiiiiiicccee

Address Mapping .......coccvevvveiniiiniiieniciiecire ettt e
Address Translation........c...ccceevvereriiiniieiiniinnese
e
PrOtECHION. ..cii ittt et
e earae s
Page Address Registers (PAR).....covvviveiiiiiiiieeieeceee
e
Page Descriptor Registers (PDR).......cccoovviiiiiiiiiii
e,
Memory Management Fault LOZIiC.........cccvevviiiiiniiiiiiiee
e,
I and D Space. ....... e

6-37
6-39
6-46
6-46
6-46
6-50

eetrtteeeeae

bbb eaeeeee et tataeeeee e abbaaeeeeeaebaaaaeeeenarrreeeeeennntens 6-51
e rre e e e ——aeeeabraaeeerraeesentbaeeeaataeeeans 6-52
MaAD CONLIOL.....eiiiiiieciic sttt
eteees 6-52
Map Addressing and Relocation............coovvveiiieeriirieenieeenieee
e 6-55
Addressing LIMitS......ccuieeiiiiiiiiiiiiiniiec
e ceieee e csreeeeree e caeeessaeeseaeeee e 6-55
CONSOLE PROCESSOR .....ooiiiiiiiiiiciececteeers
ettt ettt 6-57
BO8BS AAAIESSING ..vvveieiiiiieeiiiiiiee ettt esare e cesbaeesssaateessaaeeeessnanes 6-60
Console Data FIOW........cooiiiiiiiiiiiciieeccirie et
sre e
n 6-61
Console-to-PAX INterface ........ccceviieiiiiiiiiiiiierie et 6-61
Operation During Command EXeCUtion ........c.cccoccvvvvneeiinieiinieenieee
e, 6-62
SERIAL LINE UNITS ...ttt
estraesvae s seare e s eanne s enns 6-63
Console Terminal SLU ........ccoviiiiiiiiiiiiiiiicciicccreeree
et
eveee
6-63
Transmitter Operation (Terminal UART) ....cccccocvvvevvveecnivieenneeecreeee, 6-65
UNIBUS MAP........ovrreeerieeeeerreen, ett

6.11.1.2

Receiver Operation (Terminal UART) ....coooivvivireniiieiiresresreseeiesaen, 6-65

6.11.1.3
6.11.2
6.11.2.1
6.11.2.2
6.11.2.3
6.11.3
6.11.4
6.11.4.1
6.11.4.2
6.11.4.3
6.11.4.4

Console Terminal Baud Rate LogiC .......c.ccovvveevveeinireiiniiieeiiee
e 6-66
TUSEB SLU ...ttt
re e s ebe e s sab e et e s eabaees 6-66
Transmitter Operation (TUS8 UART) ....ccoovvviveiiviivieiiieeecccireeccennen, 6-66
Receiver Operation (TUS8 UART) ...ccoovvvveviecieieiciiieec e 6-68
Baud Rate LOZIC......cvviiiiiiieiiiciiiee ettt 6-68
AdAress SElECtION .....c.vveveiiiiiiiiiiciiiecciree
et rre et ens 6-69
Console Terminal and TUS8 Register Descriptions 6-73
Terminal Receiver Status RegiSter ......ccovvvuvireiiiiviiinriereiiireeeeeeeeeeennne, 6-73
Terminal Receiver Buffer Register..........ccvvevevvieeviieeeeciiniec
e,.. 6-74
Terminal Transmitter Status Register ......ccoevvvvevivivveeieciieieeccieee
e, 6-75
Terminal Transmitter Buffer Register........coocvvieeviiviecciieeiecieee
e, 6-76

vii

0O ~Jd O\ L
k.

Lk rbnn

)

Yl
S
[

Y
e e N e
el

pa—y

—

e R

—
N B W

ok
o

- o

—

o - - N

[—

12.4.2

6.12.5.1
6.12.5.2
6.12.6
6.12.7
6.12.8
6.12.9
6.12.10
6.12.11
6.12.12

Line Clock Status RegiSter......cccevviiriireniieiriiriniinnenec
e 6-77
TUS58 Receiver Status Register.........vvvvvviiivivineecninciiiiieeiieeecceennn 6-77
TUS58 Receiver Buffer Register ....oivvvvivviiiincciiiieeerecicinnns 6-78
TU58 Transmitter Status RegISter.....coovvvveemeveriiiiiiiininiiiinnnne, 6-79
TUS58 Transmitter Buffer RegiSter ......covvviviiiiinieniiiiii 6-80
Interrupt Request LOZIC ...coovvviiiiiiniiiiiiiiiiiiiiiiines
e 6-80
Arbitration Between Terminal and TUS8

|1155
¢ 10 o £SO
TP 6-81
KK11-B CACHE ..ottt sttt snne s saaa s 6-81
Memory Organization.........cceeeeeerireeiiininiiiiniiiiiie
e
enres s 6-84
Interface LOZIC .oooivviieiiiiiiiiiiicee e
6-85
AdAress LOZIC ...uvviiiiiiiiiiiiiie ettt
e 6-88
Data CONIIOL....cccvvreeiiiiiiieiieeiiiirerereeesessirrreeessseibreeseesssssnnnnesssssnnrreneessssssenns 6-89
Write Data LatChing ........covvvveerviiienmiiiieeeeceeeeccncciininieeceeeeenn 6-90
Read Data ENable ....vvvvviiiiiiiiiee
s 6-90
CACRE ATTAY ..veiiiiiiiiiieeree ettt
rbaa e e a 6-91
Data SECLION ....ooiiiiiiirittrreeer e e e eescrcrrrr et e et e ssesssssannnesnnranareeeeesssss 6-91
TAZ SECHION....cciiieeeiireciieeeer et
an s e 6-91
Cache FIush COntrol.......vecieeiiiiiieiiiiiiiireeseniinrnree
s eseerreesseenreeeee s e sssnaneeees e 6-91
Valid Control LOZIC ....uvvviiiiiiiiiiiiieeeecceerc et 6-92
Write Control LOZiC.....ccvviv it 6-92
Hit Detect LOZIC . uiiiiiiiiieeiiiieeiiiiiee
e 6-95
Cache Register Control .......ccceeevveirniiiiiiieneceniciirre
e 6-96
Address MatCh LOZIC .oooiiiiiiiiiiiiiceeecee
et 6-96
CaChe REZISTETS ..uvviiiiiiiiiiiiee ettt 6-97

FIGURES

Title

Page

PDP-11/44 System Configurations .........c.cccvceniiininiininiiinns 1-2
PDP-11/44-CA, -CB in Mounting BoX ........c.ccccoevirviiniiinininiiiiiic 1-4
Typical PDP-11/44 System and Selected Options ..........cccoivviiiiiniiiiiiiinicnnnne, 1-11
Front Control Panel...........cviiiiiiiiiiii
e
e eSR 2-1
PSW Register FOrmat........coooviiiiiiiiiiiieieieneesinecsncirnereereeeee
s ssisnnesssessssreesesse e 2-20
PIR Register FOrmMAt ......occcuviiiriiiiiiiiiine
e
eircee et ec s errraee s ssnreee e 2-22
CPU Error Register FOrmat .........cccooiiviiiiiiieiininniieneneerccceeene
e 2-23
Console Terminal RCSR Format.........coooovviieviiiiiiinnrenniiiiiceeenienee
e 2-25
Console Terminal RBUF Format.........cccccoiiiriiieeeriiinnniiiiieeee 2-26
Console Terminal XCSR FOrmat.........cccociiiriiiiieeeeneeninriinrrrrrcceeeen
s 2-27
Console Terminal XBUF Format..........ccoocvvriiiiiieeeriiinnncriiiiiiiiecn
s, 2-28
TUSE RCSR FOIMAL.......cvviiiiiiieeieiiieieeineeeinirneeesrreesseseeesessseeesssssnessossaeesssneesssns 2-29
TUS8 RBUF FOIMAt.....occoiiiiiiiiiiieeeiiiciiiitee
s cecnereessssssesneessssesnsnnesssssssnssnesasesssnnnnes 2-30
TUS8 XCSR FOIMAL ...uvviiieiiiieiiiieeeiiricinieees
s sscrereesssssirereeessssnsrtesessesssnresseesssssnns 2-31
TUSE XBUF FOIMAat.......cvviiiiiiiiiiiiireeeisiiiiiireereessiirresssnreeseesssssnvetesssssessnsssseseess 2-32
Signal Register FOrmat..........ccooovviiiiiiiiiii
s rcccririerreeceeeee s sesee s
mseeeneeees 2-32
Line Time Clock (TCSR) FOrmat.......cccccvvveeiivieiiiiciiiiirreeeeeeeee
e seesecinsnnsesssseseeeeees 2-33
Cache CDR FOrmat ...t
cessrcirrrnreee s e e e e s e s s e s s s
neeesnneees 2-34
Cache CHR FOrmat......ccccciiiiiiiiiiieciiiiiiriieeeeeeen
e s eesesesnisseeeenreceeessesssssassssssssnnnnns 2-35

viii

CaChe CMER FOTIMIAL .ooevvveieeeeeeeiiiieeeeeerrerraniiaesserrrreensesssetttrmmmiiiessersssrsmmnissssesssssenes 2-36
esesiansesssnaness 2-37
enrrresssnraessssnteeeiinree
Cache CCSR FOIMAL......oiiiriiiiiiiireeeeseiieeeesii
ssnnasses 2-39
esssnnessssausees
nresesnrsessssnse
ireeeeesiieteesii
CaAChe CIME FOTMAL....ccciiiiiiieiiirireeeeeei
2-40
iinii
ccoeven
.......
Format.
Memory Management SRO
2-42
ii
einiiii
ccooovi
.......
Format.
SR1
Memory Management
2-43
iiii
ooniin
...ooo
......
Format
SR2
t
Memory Managemen
Memory Management SR3 Format.........ccooovinii, 2-43
Memory Management PAR Format ... 2-44
Memory Management PDR Format........ocoveiiiiniii 2-45
e 3-1
Backplane Module LOCAtiONS..........ouvviieiniminieineiniiiiis
Backplane Assembly, Pin Designations ... 3-3
Module Contact Designations.........ccoveviuiiiiiniiiieniiineees 3-6
SPC Slots, NPG Jumper Lead Locations.........ccoovmirineeneenininiii, 3-7
CIM Jumper Lead Locations, Connectors and

LED INAICALO0T e eeititeeeeieeeetieeeeiiieietieeeeeiinneenreeerttettttrteeaaseesasssssssssasnsnsserebaststiessessaeens 3-12
MFM Jumper Lead Locations, Switches and

LED INAICALOT . uveeeeereeeeteeeeteeeeereeeerreessiseeesmareessarssinarsssraaassssesssiaeesasssessnsessssissens 3-15
e 3-17
TUS58 Device Address SEleCtiON .....ccvvvveercieriiinimiiieiiiiiee
e 3-17
ere
TUS58 Vector AdAress SElECtion ....cccvveveeerieioimiiiiiiiiiiiiirn
niinninn, 3-18
vveniiiniininni
..........ccece
UBI Module, Switch and Jumper Lead Locations
Cache Memory Module, Switches, LED Indicators and Jumper

L ead L OCATIONS cceeeuereeeeeeeeeiiiirrrerreeeeeserrrraeeesssaerasateeeeeessitnnrasreasesabbraeeaesssasnbnssisees 3-24
Control Module, Bootstrap Control Switch .......ccooviininiiini 3-25
PDP-11/44 Unit Unpacking .......ccccouvirinninininenniniiiissse, 4-3
PDP-11X44 Cabinet Unpacking.......ccoccovveiiviiiniiiniiniiniiieniieieiiiiniesns 4-4
PDP-11X44 Cabinet Type Identification .........coceiimniinieiiinniini 4-5
Left and Right Side Panel Removal ... 4-6
Shipping Bracket LoCation .........cooeviinieiiniininenniiiiii 4-7
PDP-11/44 Unit DIMENSIoNs .......ccoovvivirueieiereniniiisiiiisiiis s 4-8
ii 4-9
PDP-11X44 System Cabinet DImensions .........ecevvereniniiniiiie
Mounting Box Rear Panel COmPONENts......c.coevervivenciiiiiiiniiiiiniecnes 4-11
PDP-11/44-CA, -CB AC Power Connector Specifications ........cocvvvveevireeiinniennnnenn 4-11

O \O
—

RO R, RV R, R
.1
11
ILIJ]-F-PJI;

UNB LN
=

872-D, -E Power Controller, Input Power

SPECIICALIONS ...evvoveeeeeeiniiiiniiter it 4-12
Mounting Box in HI61 Cabinet...........coovvieiminieienininiiiiinss 4-13
BA11-AA, -AB Mounting Box Index Plate Installation ........cccooeeciininnininnnnnn 4-14
Single- and Double-Channel Slide ASSemDbIIES .......ccoovvviiiiiiiniiii 4-15
H961 Cabinet, Slide Mounting Locations ..........ccccoeuvrmiiiiiiencenninnieniinin. 4-16
iie 4-17
esbee e
e eeeereii
Cabinet Slide TNstallation ....c.veeeeviivreeeiriir
4-18
o
.
.
Mounting Box to Slide Installation
4-19
s
bas
ii
et
ieeiii
esree
ieerrr
et
cveeie
.....c
Cabinet Stabilizer MOUNTING
4-20
iniiiecns
inniniiiiini
ccoveervenni
Area......c.
Service
Cabinet
PDP-11X44 System
e 4-21
BA11-A Cable Routing LoCAtions .........cccveriviiiiniiemniiniienciiiiiisn
4-22
s
inieniinic
iiiiiiiiii
eeiriiviii
......coev
ROULING
Cable
Cabinet
PDP-11X44
Backplane Assembly, Pin Designations ..o 4-24
PDP-11X44 Cabinet Type Identification ..........cccoccemieeieniniiniini, 5-1
PDP-11X44 Systems Cabinet Mounting Box Release Lever.........cooviiininnnenn 5-3
PDP-11X44 Top Cover Mounting (Type A)....ccceieiiiieneniiiiniiiens 5-4
PDP-11X44 Cabinet Top Cover Mounting (Type B)....ccoceevvevieiiniiiiininiinn. 5-4
PDP-11X44, Slide Latch Locations.........covviiiermiiiniiinieneciiiniee 5-5
PDP-11X44 Cabinet Safety Lever.....ccooiviiiiiiiiiiniieneniiiiiiciceeee 5-6
PDP-11X44 Cabinet Mounting Box Hardware ........cccoeviiienicnninnin. 5-7
Interface Bracket MOUNTING ...ccveeevveerrneeiriiiiiiiiriirersiessnee et 5-8

ixX

UnNBhWN—O

et 5-10

Fan Assembly Removal ..........cocvviviiiiiiiiiiiccece
e s 5-11

Power Supply Assembly, Rear Mounting SCrews..........ccovevvevvivieiienverieeeveenenn, 5-13
Power Supply Assembly Removal ........cccoeevieiiiiiciiiiiccceeeee
e 5-13
Power Lead Connections.........ccccuiiiiieiiiiniiiiniee
et
eseve e e
5-14
Power Distribution Panel and Connectors ...........covcovviiiiiiiiiiieeinieieeeeeseeeeeeeenn. 5-15
Optional Backplane ASSemDbIIEs.........ccceciveviiiiiiniiiiiicii
e 5-17

WOV

Optional Backplane Configurations.........c..cocueeeiiiiiiinieiiiiiiecereccreesteeeeessee
e 5-19
Backplane Assembly MOUNEING .........coceviiiiiiiiiiiieciece et 5-20

OO
LN
WN—=O

O\O\O\O\O‘\O\?\O\O\O\O\O\O\O\ O\O\O\O\O\MMMML{\MU’IMMMU’IML}IMM

Mounting Box Release Lever.........cccvvviviiiiiciiiiiiiecci

Backplane Assembly ALIGNmMENt ..........cccoovviiiiiiiiiiiiiiicciie et 5-21
Optional Backplane S1ot ASSIZNMENTS ..........ccecviiiiiriieiiiiesieerecteseeereeeeseeeenaeas 5-22
NPG Jumper Leads ROULING ....ccccvevuiiiiiiiiiiiicic
et e 5-23
Standard and Modified Backplane Pin AsSignments...........ccccovvevereeeeneeeecneeeenennn 5-24
SPC Backplane Pin ASSIZNMENtS.......cccviveeiuieiiiiniiiniiiiecreesieectceseeeseeseeeeeseeeeee
e 5-25
Backplane Power Connector Pin Designations .............ccceevveveiviiiiiinreeeneeneeeneenes 5-26
KD11-Z Microinstruction FOrmat .........ccccceeeiiiinrieiniieiiiiicne e
6-2
MIiCTOPC GeNEIation........eiiuiiiciiiriiesitiesie
ettt ste st eeeaeeereeeeneeeeaeeseeeeas
6-4
Data Path BIock Diagram.......cccceiiiiviiiiiiiiiiiiecie
ettt e ee e s
6-6
Arithmetic Logic UNIt ...viiiiiiiieiiiiiicii ettt ee s v an
6-7
ALU B-Leg LOZIC ....oiiiiiiiiiiiiiicicceit ettt sttt
s eseeneas
6-8
ROtate INSIIUCLIONS. ... .eivtiiiiiiiiie ettt
b e e reeseeeesraee s 6-11
SCratChpad LOZIC ......cccceiiiiniiiniiiieiiini ettt ettt e e sare s e e 6-13
Scratchpad TIMING ......oocvevieiiiiiiiiiiciccce ettt e e e s e enaeens 6-14
PSW LOZIC ..ctiiiiiiiieiicctint
ettt
ettt eeae s een e e teeaaeennes 6-16
UNIBUS SyNCRIONIZET......ccciiiciiiiiiccic
ettt st se e eeeeeseveeaans 6-22
Generation of MSYN and MSYN/SSYN Timeout ........cccceevevviviiieeerereerenenn. 6-24
DESKEW LOZIC ...cuieieitiiiiiiiie ettt
ettt ev e e bt e et eeeseeeeneesane 6-26
Request Synchronization ........c..coueciiiiiiiiiiceeeec
et 6-27
SACK TIMEOUL ....couiiiiiiiiiiticiitesiesee
ettt ettt sae e st e sree e eeeeeeeneeseeens 6-28
Transfer Error LOZIC.......coviiiiiiiiiiciieiecr ettt se e e et e eae e s 6-29
Generation of ABORT RESTART L and ABORT H ......oocovviiviiviieeieeeeeene, 6-30
PDP-11/44 System Clock Short Cycle Timing Diagram ........coccceeveeeveveeeveeeennnnn. 6-32
PDP-11/44 System Clock Long Cycle Timing Diagram..........cccccoeevvevveeveeveeenennn.. 6-32
PDP-11/44 System Clock Timing Diagram with Memory
CYCLE ettt
b et b e et e e at e st teetee et eareeraraans 6-34
BUS AC LO and DC LO Timing Diagram ..........ccccovvvevievienivieieeneerreeeeeeseneeeeesnns 6-35
Interpretation of VBA . .....ooiiiiiiiiiic
ettt sttt
e e esena e 6-37
Displacement FIeld .........ccocviriiiiiiiiiiiii it
e s e e 6-38
Construction of PA ......ccooiiiiiiiiicie ettt ettt
ens 6-38
Memory Management Block Diagram ...........cccoovvvvviiieiiiiiiiinieneeeeeeeeeeeeeee
s, 6-40
16-Bit MAPPING ...eoiiiiiiiieiieieesi
sttt ettt e s et et eette
tiiitcsiee
st e srbesseeeeeesseeneeeans 6-41
16-Bit Mapping: Generation of PA ...........ccoooviiiiiiiiiciicce
ettt
eeeveeeeees 6-41
18-Bit MaPPING .....eiiiii
ittt
iieiiiiiiii
et ebeseteestvesseteseeeeeeaeseseass
iiecirie
sessseeas 6-42
18-Bit Mapping: Memory AdAIess .......cocuiivviiiiiiiiiiiieceeesteeeeteseeeeeeessrveseseesseens 6-43
18-Bit Mapping: UNIBUS Address.........cccevieviiiiieniiiiiiceticceeeeeeeeseeeeee
esnes 6-44
22-Bit MAPPING ....ooii
ettt
iiieiiii
ettt iinitee
v et sne st e e eeesaeenaneees 6-45
22-Bit Address Mapping ......cccvcveviieeuenieerionieeiicii
et e eteseeeveeeeese s cecesrt
eeseeseesaeas 6-45
Memory Management Relocation REZISTETS .......cocuviveeieeieeieneeeeeeeeeveeereeeeseeeereeenns 6-47
Page DesCriptor REGISIET ......cuvvi
ettt
iiiiiicciii
e e e e e eeeeeeaeeeeeeseesrae
iciii
e 6-47
UPWAard EXPansion.........occeceviinin
e iniinicieiecrce
eseetesre s s e et et eeeseeseeenesnnas
eeer 6-48
Downward EXPansion.........c.ccciiiiiii
sttt
iiniiiciccceeec
s e e et aeeenas
te 6-49
UNIBUS Address SPACE ......ocvevi
ettt
iiiecierieii
ettt st steevteseeseesnesssessasseens
ente 6-52
UNIBUS Map BIock DI@Bram .......c.cccceeuiiiiniiiiiiiiiiieseeeeeeeeeeeeeeeeeeeeeeveeeeeeeaneas 6-54

6-38

6-39
6-40
6-41
6-42
6-43
6-44
6-45
6-46
6-47
6-48
6-49
6-50
6-51
6-52
6-53
6-54
6-55
6-56
6-57
6-58
6-59
6-60

Construction 0f the PA ..ottt 6-56
UNIBUS Map Addressing Limits.......ccocovviiiiiiiiiiiiiiiiiiccnns 6-57
iiiiiie 6-58
e
Console Processor Block Diagram ........occcveeevviieeiiniiiiiii
Console Processor to PAX, Interface Control LOgIC ......uviveveeerieeeriiiiiiiinniiiiinnninnne. 6-63
Console Terminal SLU .....uviiiiiiiiiiieicireeceeriereccirre i 6-64
TUSE SLU ..vvteieecieieeeeeiirre e tesirreesesseraeessassbsaeesasreasessisraesessabbesesaasbasssessssssaanssrnaesanss 6-67
Address Selection LOZIC.......ciivvieraieeiniiiiiiiiiiiiieirrer s 6-70
ieiine 6-71
it iinnree s sesiineeeesesnns
SLU Address FOrmat.....oocovvviieiiiiiiiiiiieineeeeeii
e 6-73
Terminal Receiver Status REGISTEr ....uuvvieevirniciiiiiiiiiiiiiiiiiinre
Terminal Receiver Buffer Register....ccccovviveeiiviiiiiininiiiiiiiiiiieene 6-74
s 6-75
Terminal Transmitter Status REIStEr.......uvvvieiiiiiiiiiiiiiiiiiiiicee
6-76
iniiiiiines
Terminal Transmitter Buffer Register.....ccccovviviiiiii
6-77
it
Line Clock Status REGISTEr ...uuiiiviiiieiriiiiiiiiiiiiiiee
6-77
et
iiniiiciiien
TUS8 Receiver Status REGISTET ..ouvviivireernvieinii
6-78
i
iiiies
veeiiiiiiiiiiiiii
TUS58 Receiver Buffer Register.....covv
6-79
i
iiiiiiii
..oooovvveeerrviiiii
ReISter
TUS58 Transmitter Status
6-80
eieen
iiiiiiiiiiiii
...ccovvvviii
RegiSter.....
Buffer
TUS58 Transmitter
Terminal and TUS8 Interrupt Arbitration LOZIC.......cooivvviiiniinniiiniiiii 6-82
KK11-B Cache Memory Block Diagram.........cccoviiiiiiiniinninnninniinne 6-83
Cache Memory Addressing........coooveviiiiiiiiriieeiiaiisie i 6-84
Cache Memory Organization..........coovuiiniiniiniieiinniiniree e 6-85
Cache Address Multiplexer Control LOZIC.......cccvviiiiiiiiiiiiiiiniiiin 6-89
e 6-92
Cache Flush Timing Diagram......cccccccovvvriiiiiiiiiiiiiiniiiie

TABLES

HWNO—=O

O\ D»n
p— ikttt
D) OO ~]

NNNN[})NNP—H—H—‘

SRR I, NV

]

Table No.

Page

Title

e 1-3
Processor System Designations.........cocvniiiiiiiniinimninii
nnn. 1-5
ieiniinininininniini
........ccccovcoinie
Components
PDP-11/44 Standard Hardware
1-6
t
e
e
erreriiniiniiiiiiii
Hardware OPLiOnS.......cceve
1-6
iiiiiniiiiini,
.......ccooevvni
Specifications..
Equipment
-CB
PDP-11/44-CA,
PDP-11X44-CA, -CB Equipment Specifications..........ccvevvemniiiniiniiennienninnn, 1-8
H7140-AA, -AB Power Supply Specifications .........cccevnieeiniiiinieniniienienine 1-9
esiinntte 1-14
e e sssiabrare e e s s s snnraraeeessssanne
Related PUDLICAtIONS .vvvvvvviiieeiiiiiiirreieeeeeeriiirreeeeee
s 2-2
Front Panel Switches and Indicators .......coovevvmiiiieiiiiiiiiii
e 2-4
eesses
reiitiiiiirree
e sesessiirirrrressesee
Console Mode Commands.........coovvrerrreiiiummmerimrer
e 2-4
Console Command Terms and Characters.....ccc.ooovviriiiiiiiiniiin
s 2-5
Console Command QUAlIfiers .......cceevverrvciiiiiiiiiiiii
Special Address Field Characters..........ccocoviiinininnininiiii, 2-6
CONEIOL CRATACLETS .. ivvvrirriieieeeriirirreeereesssiieteteeessssiiarttrseeesirrarsessssssrnnnasesssssnnsnss 2-6
Device Bootstrap Identifiers .......cccceeviivniiiiiiiiiiiiiiiiee 2-9
Bootstrap ROM Identifiers.......cccoovviiiiiiiininiiniininiieiciis 2-10
DEPOSIT Command Qualifiers........cccceevvveiiiiiiniiiiiiiiiiieesiieeereecnecsniiens 2-12
e cnanenns 2-12
EXAMINE Command QUAalifiers ......cccceevveeriieiiniininiiiniieenneeniennces
2-18
s
iiiii
c..covvvivieiiiiiiii
SUMmMAry Of EITOIS
2-19
st
s
ieeeirreesireessee
rerreeeriniiieiiii
SUMMATY......cciie
Console Command
PDP-11/44 CPU and I/O Device Register Address............cooevvinnmiiniininnnicnnes 2-20
Processor Status Word Register Bit DescCriptions.........ccovveereiieiniiennneennniiiniinns 2-21

LW WWwWwW

O~
P W
—

— OO0
UL
WN—=D

S I

lwwwwww

SIS
S

Processor Interrupt Request Register Bit
DESCIIPLIONS ..oouviisttt
iiiiiiei
ettt iciiitec
ettt st et e et e e e e s eeseeeseeeeeeeens
ie 2-23
Error Register Bit DeSCriptions .........ccoviveeviciiiiiciiciciseceee
e, 2-23
General Register AdAresses.....coiiiuiiieriieiiiieiieeeeeeeeee
e e e e e e e ees oo eereeeee
e, 2-25
Console Terminal RCSR Bit DesCriptions..........ccceveeveeveeeereeeeeeereeseereesereeesenennn, 2-26
Console Terminal RBUF Bit DeSCriptions........ccvovveeveveeeeeeeeeeeeeeeeeeeeeeeeeeessenoos 2-26
Console Terminal XCSR Bit DeSCIiptions..........coveveeveeeeeeeeeeeseeereereereereereessesenn. 2-28
Console Terminal XBUF Bit DeSCIIPLONS. ......c..ovevvieeiveeeieeeeeeeeeeeereeseeeeresesnesns 2-29
TUS8 RCSR Bit DESCIIPLONS. ....ccviieriiiiiitccrice
ettt eer oo iceeceee
ee e ees e e 2-29
TUS8 RBUF Bit DeSCIIPLONS......cvviuiiriiiiiciiiei
et ceccttceeeee
e e e e es eenenas 2-30
TUS8 XCSR Bit DESCIIPLIONS ....ouveuviieiiiitietici
et e e seeeeeesreesesseesessesss
icecceectese
ens 2-31
TUS8 XBUF Bit DESCIIPLONS......ccocviiiiiiiiiiciiceic
et eeeeete
eeiictecttee
e oo
e 2-32
Signal Register Bit DesCriptions ........c..c.ooveuiiuiiiiiii
e e eer
neeeeeeeeeee
e eesees oo, 2-33
Line Time Clock (LKS) Bit DeSCriPtions ....c.coveeviveereeeeeeeeeeeeeereeeeeseeeeesoeesos 2-34
Cache CDR Bit DeSCIIPLIONS ......ceeviiviirinieeiitii
et
e e eesees
ieeieeeee
s e esees e 2-34
Cache CHR Bit DesCriptions...........ooviviiiiieiieee
e oo
eeeeeeeeeeee
e oo, 2-35
Cache CMR Bit DESCIIPUONS ..c..ecveiviieiiiieeiiii
et eee e e ciceeec
s ees e 2-36
Cache CCSR Bit DeSCIiPtiONS .....ccvevvieiiivieiiieiceic
et eeee ooeceeeeeee
e
2-38
Cache CME Bit DESCIiPtioNs ........ccveviuiiiie
ettt iiiieiicic
eeeee e e
eseons
is 2-40
SRO Bit DESCIIPIONS. ....cuiiiiiiiieieiiiieiect ettt et
es e 2-41
SR Bit DESCIIPHIONS. ....coviviriirieiiieiet ettt
e et et s e ee e s e 2-42
SR2 Bit DESCIIPtION ...cc.evuiiiiieirieiitiet ettt
oo, 2-43
SR3 Bit DESCIIPLIONS. ....eitiiuieiiei
ettt ettt
ieiieiii
eer s s e s e ee oo
cct 2-43
PAR Bit DESCIIPLION ..cveiuiieiiiiiitiictieiesie
ettt e e e e e 2-44
PAR/PDR UNIBUS Addresses.......ccocovururmuiiiiiirirereretceeseeseeeseeeeeeese
e esenenas 2-45
PDR Bit DESCTIPLIONS. ...cccuiiiiiiiiiii
etttiiitiicte
et e e s e et eecee
e 2-46
Standard CPU Backplane Modules ...........c.oouoeviieeioeereeeeeseeeeeeeeeeeeeeeeer
oo 3-2
Optional CPU Backplane Modules..........coovoviviiiiiniieeeeeeeeeeeeeeeeeeeer
e, 3-2
CPU Backplane Connector P1, Signals and Voltages..........ccocvevvveeveeveevreereensnnn. 3-4
CPU Backplane Voltage DistribUtion.........ccoccoecvievviieeeeeeeeeeseeeeeeeeeeeesereeenns 3-4
CPU Backplane Ground Distribution ............c.ocuvuiveeeieveeeereeeseeeseeeeeeeeereer
e, 3-5
SPC Location, Signal Identification...........cccoeveeviirmeeeeeeeeeeeeeeeese oo, 3-8
CPU Module Current ReqUIreMents.............ccooveueeeeuieerereeeeeeereeeeeeeeeenesenea, 3-10
H7140-AA, -AB Power Supply Maximum
OULPUL CUTTENT 1.tt
e e st e e e t
e es et e etee e 3-10
—~15V, +15 Vdc Option Power ReqUirements ..........ccooveeveeeeeeevveeveeereeseereereennnon, 3-11
Console Terminal Configuration, 20 mA INterface ......coevevveereeeeereeeoeeeeeesooeoenn 3-13
Console Terminal Configuration, EIA Interface .........ocooveveevveveeeeeveeeeeoesoeeon. 3-13
TUS58 DECtape II, EIA Configuration............cccvviveeeeeeeeeeeeeeeeeees oo, 3-13
MEFM Console Terminal Jumper Lead Configuration............ocoeeeveevovoevoeeoenienn 3-14
MFM Console Terminal Baud Rate Selection..........coeeeveeeeeeeeeveeersreereerereieeenn. 3-15
MFM TU58 Jumper Lead Configurations .........c.coe.cveveeeerreeeeereeereereereserosseenennn. 3-16
MFM TUS58 Baud Rate Selection (Switch PACK E7) v.evveveeveeeeeeeeeeeoeeeeeeeoeoee, 3-17
Line Time Clock OPEration .........cccececceeiirieeie
niiiciicistes
eeereeseesees e s,
tee 3-18
UBI Module Jumper Lead Functions .............ccccooueeivviveeieieeeeeeeeeeeereereeeon, 3-19
UNIBUS Map Jumper Leads, Lower Limit.........ccc.ccoveeeereeeeinereeeseeeeeeversn, 3-19
UNIBUS Map Jumper Leads, Upper Limit.........ccccoeverveeireeeeeeeeeeesreereereesseessonns 3-20
CPU Diagnostic and Bootstrap Loader
ROM AQAIESSES......oveeiieeiieiiieisietcetee ettt et e s es e e, 3-22
Bootstrap ROM LOCAtIONS ......cocuviiiiiieie
et
riiticieti
eeeeee e et ees e cictece
s seee s 3-23
Device ROM Part NUMDETIS ....cccocviiiiivii
etiiceicicc
ee e e e eeeees e
ceee 3-23
Cache Module, LED Indicator FUNCHONS .........cccveveieeeeeeeereeeeeeeeeeeeseseesereses 3-24
System AC Input Power ReqQUIr€MEnts ..........ccoceveeveeeeeeeeeeeeeseeeeeeeseoes
oo, 4-10

xii

B W~
R WN

O\O\O\O\O\O\O’\UIUIUIU:l

CPU Backplane Connector P1, Signals and Voltages...........ccccocrnieiniiiinniinnnn. 4-24
PDP-11/44 MAINDEC Diagnostic Programs..........cccccceiiiiiiinininiiniininn 4-26
UBI Diagnostic ROM Error Indicators........coccevvviiiiiiiiiniiniiiiiiiiniiee
s 4-27
Optional Backplane Assemblies.........ccoevviiiiiiiiiiiiiiiiiii
i 5-16
Backplane Assembly Types.........ccceeuveennnn.e
rer e e et e i ieba—reaeeeaaa———aaeeeaaa
e raaareaeaarrres 5-18
Power Connector Signal Assignments for DD11-CK ........ccoocoiiiiiiiiiiiiiinnnnn. 5-26
Power Connector Signal Assignments for DD11-DK .......cccccciiiiiinn. 5-27
Error Logic QUEPULS.....cccuiiiieiiiiieniieiee ittt 6-31
Address Mapping MoAes .......oocuveeeiiiiiiiniiiiiiieni i 6-39
Memory Management Fault PROM Inputs......c.cccciviiiiiiiiniiinii, 6-50
Memory Management Fault PROM Outputs ........cccovviiiniiiniiiniiiiiniii, 6-51
Access to UNIBUS Map REZISLErS ......covevviiviieiiiiiiiieeeei
e 6-53
TUS58 Baud Rate SeleCtion ... u..oiicuiriiiiiiieiiiiee ettt 6-69

Cache Read/Write ReSPONSE .......cccvvvvivieiiiniinniiiiieinnen, ettt 6-93

xiii

PREFACE

The PDP-11/44 is a midrange computer system which is available in a standard configuration and is
expandable by the user to conform to specific user requirements.
This manual defines the standard system and provides the information required to unpack and install
the system in a cabinet, and to wire the system for operation. This manual also gives a detailed func-

tional description of the KD11-Z Central Processor used in the PDP-11/44.
Chapter 1, Introduction — Includes a general description of the PDP-11/44 system and the modules
supplied with the unit. The chapter also describes the features and capability of the system, the available options, and the equipment specifications, including the power supply.
Chapter 2, Operation — Describes the front panel controls and indicators, the console commands available, and register bit assignments.
Chapter 3, Configuration — Provides the module current requirements and information on placement in
the processor backplane, and the switch and jumper lead information required to configure the modules
for specific requirements.
Chapter 4, Installation — Provides the information necessary to prepare the installation area, to connect
the unit to ac power and to mount the unit into a PDP-11/44 system cabinet or standard 48.26 cm (19
in) cabinet.
Chapter 5, Removal/Replacement Procedures — Describes the procedures required to remove and replace the main units and assemblies and to install additional backplanes for expansion of the system
functions.
Chapter 6, Detailed Functional Description — Describes each of the major logic elements of the KD11Z Central Processor.

CHAPTER 1

INTRODUCTION

The PDP-11/44 processor consists of CPU modules, memory modules, and interface modules enclosed
in the BA11-AA or BA11-AB mounting box. The box includes a front control panel and power supply.
The mounting box can be installed in a standard 48.26 ¢cm (19 in) rack or cabinet or in a DIGITAL
system cabinet.

The PDP-11X44 system consists of the PDP-11/44 processor mounted into the 100 cm (40 in) lowprofile, top-loading H9642 cabinet. This cabinet conforms in style to other DIGITAL PDP-11 peripheral unit cabinets.
Figure 1-1 shows several typical PDP-11X44 system configurations that include disk drive units and
magnetic tape units. The PDP-11X44 cabinet attaches to the RL0O2 and RK07 Disk Drive Units and to

the TS11 Magnetic Tape Unit.
1.1
GENERAL
The PDP-11/44 and the PDP-11X44 are medium range, general purpose computer systems which operate with 16-bit data words and provide 22 bits for memory addressing. A total of one megabyte of main
memory can be included with the system in increments of 256K bytes. The system includes the complete instruction set of the PDP-11/70 processor except for the FD MAINT INST instruction. Two

additional instructions, Move From Processor Type (MFPT) and Call to Supervisor Mode (CSM), are
included.
The systems also include an 8K byte cache memory and the extended instruction set (EIS). A microprocessor interprets the ASCII codes from the console terminal and allows the functions previously
performed at the console switches to be initiated at the console terminal.
A floating-point processor and a commercial instruction set processor are available as options with the
system.

The PDP-11X44 system includes a dual TUS8 DECtape II cartridge tape unit used to load diagnostic
programs and to update software. The following operating software systems are compatible with the
PDP-11/44 and PDP-11X44 systems.
Software

Version

Software

Version

RT-11

V4.0

CTS-500

Vs5.0

RSX-11M

V3.2

DSM-11

V2.0

RSX-11S

V3.2

TRAX

V2.0

RSX-11M +
RSTS/E

V1.0

COBOL-11

V4B

V7.0

MACRO-11

V4.0

1-1

S——————

PDP—11X44
LT
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PDP—11/44

100CM(40 IN)
SYSTEM CABINET

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DUAL RLO2 PDP—11X44
e

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[

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SEPARATE

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PDP—11X44
(LTI

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——————
ATTACHED CABINETS

—~—
~/
ATTACHED CABINETS

TS 1

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PDP—11X44

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ATTACHED CABINETS

Figure 1-1

TK-4367

PDP-11/44 System Configurations

1-2

1.2 EQUIPMENT DESCRIPTION
The PDP-11/44 and PDP-11X44 processor systems are available to operate with either 120 Vac or 240
Vac input power. Table 1-1 lists and describes the components included with each system.

Table 1-1

Designation

PDP-11/44-CA

Processor System Designations

Description

Contains a CPU, 256K bytes of ECC MOS memory, two EIA serial line units,
one for the console terminal and one for the TU58 tape transport (not included),
BA11-AA mounting box with cabinet, mounting slides and a filter distribution
panel. Operates with 120 Vac input power.

PDP-11/44-CB

Same as PDP-11/44-CA except the mounting box is a BA11-AB wired for 240
Vac input power.

PDP-11X44-CA

Same as PDP-11/44-CA except the BA11-AA mounting box is installed in an
H9642 system cabinet which includes a dual TUS8 tape unit and power control
unit for 120 Vac input power.

PDP-11X44-CB

Same as PDP-11X44-CA except it is wired for 240 Vac input power.

1.2.1
PDP-11/44-CA, -CB Processor System
The PDP-11/44-CA, -CB processors are supplied in the BA11-AA, -AB mounting box shown in Figure
1-2. The mounting box contains a 14-slot (column) backplane assembly with the system modules installed, a fan assembly, and an H7140-AA, -AB power supply assembly. The fan assembly contains
three fans and provides cooling for the modules and power supply. The fans are mounted on a slide, for

case of removal, and are powered by the power supply. A bezel is attached to the front of the mounting
box and contains a control panel and ventilating slots for air circulation. An open-cell foam filter is
located directly behind the front bezel and may be easily removed for cleaning.
A control panel, located on the lower section of the front bezel, contains a keyswitch, panel switch, and
indicators to select and indicate operating conditions. A removable top and bottom cover is also sup-

plied with the mounting box.
Attached to each side of the mounting box is a slide index plate which allows the unit to be rotated to a
vertical position, when the unit is mounted in a cabinet, onto the slides that are provided with the unit.
The slide index plates are released by the side pawl retractors also located on each side of the unit,

toward the front.
The BA11-AA, -AB box provides a 14-slot CPU backplane and 29 card guides at the front and rear of

the unit to allow additional modules to be installed. One DD11-DK 9-slot, double-system unit and one
DD11-K single-system unit or three DD11-CK single-system units may be installed and connected
directly to the power supply by the cables and connectors attached to the system units. These system
units provide additional mounting space for I1/O device options.

1-3

TOP COVER

H7140—AA—-AB

POWER SUPPLY

AIR FILTER

ASSEMBLY
SLIDE INDEX
PLATE
SIDE PAWL
RETRACTOR

BOTTOM COVER

TK-4368

Figure 1-2

PDP-11/44-CA, -CB in Mounting Box

1.2.2 PDP-11X44 Processor System
The PDP-11X44-CA, -CB consists of the components described for the PDP-11/44-CA, -CB which are
mounted in a system cabinet as shown on the frontispiece. Mounted below the front bezel is a dual
TUSS8 tape unit which enables the loading of diagnostic programs from cassettes and provides data storage for up to 256K bytes of information.
The BA11-AA, -AB mounting box is attached to the top of the cabinet and can be released and tilted
vertically for servicing. When tilted, the mounting box is supported by two gas springs. A hinged panel
is provided at the front and the rear of the cabinet to allow access to the power controller unit provided
with the cabinet, to the battery backup unit which is supplied as an option, and to the I/O connector
panel.

1-4

1.2.3

Standard Hardware Components

Table 1-2 lists the standard hardware supplied with each PDP-11/44 system.

Table 1-2

PDP-11/44 Standard Hardware Components

Quantity

Description

KD11-Z Central Processor consisting of:
(M7090) Console Interface Module
(M7094) Data Path Module
(M7095) Control Module
(M7096) Multifunction Module
(M7098) UNIBUS Interface Module

MS11-MB ECC MOS Memory (256K bytes)

8K byte cache memory on hex-height module (M7097).

BA11-AA (120 Vac) or BA11-AB (240 Vac) mountmg box with power supply

and DD11-DK backplane (70-16502)

M9302 UNIBUS Terminator Module

M9642 Cabinet (PDP-11/X44-CA, -CB only)

TUS58 Dual Tape Drive (PDP-11/X44-CA, -CB only)

872-D Power Controller Unit (PDP-11/X44-CA, -CB only)

I/O Connector Panel

1.2.4

Hardware Options

The standard PDP-11/44 system capabilities can be expanded with the installation of several available
hardware options which are listed in Table 1-3.

1.3

EQUIPMENT SPECIFICATIONS

The following paragraphs contain the mechanical /environmental specifications for the PDP-11/44 and
PDP-11X44 equipment. Detailed specifications for the peripheral devices supplied with these units are
contained in the user’s guide associated with the device.

1-5

Table 1-3

Hardware Options

Designation

Description

MS11-MB

256K bytes ECC memory on hex-height module

MSI11-MC

Same as MS11-MB except 512K bytes on two hex-height modules

MSI11-MD

Same as MS11-MB except 758K bytes

FP11-F

Floating-point processor on hex-height module (M7093)

KE44-A

Commercial instruction set processor on a quad-height module (M7091) and
hex-height module (M7092)

H7750-BA

Battery backup unit 120 Vac/60 Hz, 240 Vac/50 Hz

H7750-BD

Same as H7750-BA except for 240 Vac/50 Hz

TUS8-CA

Dual cassette tape transport

BAI1I-AE, -AF

Expander box for PDP-11/44 system expansion; includes power supply

1.3.1 PDP-11/44 System Specifications
Table 1-4 lists the equipment specifications for the basic PDP-11/44 unit. When the system is operated
with a TUS8 DECtape II option, the specifications will be similar to those listed in Table 1-5 for the
PDP-11X44 system.

Table 1-4

PDP-11/44-CA, -CB Equipment Specifications

Characteristic

Description

Mechanical

Overall dimensions (with front bezel)

70.15 cm long X 48.26 cm wide X 26.34 cm high
(27.62 in long X 19 in wide X 10.37 in high)

Weight

Unpacked

32.66 kg (72 1b)

Packed

36.2 kg (80 1b)

1-6

Table 1-4

PDP-11/44-CA, -CB Equipment Specifications (Cont)

Characteristics

Description

Environmental*
Temperature

Operating

5°Cto50°C(41°Fto122°F)

Nonoperating

—40° C t0 66° C (-40° F to 151° F)

Humidity

Operating

10% to 95% relative (RH) with a maximum wet bulb of
32° C (90° F) and a minimum dew point of 2° C (36° F)

Nonoperating

50% relative (RH) or less to 95% (RH) or less with a
maximum wet bulb of 46° C (115° F)

Vibration

Operating

Nonoperating (PDP-11/44 packed for
shipment)

5t0 22 Hz: 0.01 in DA; 22 to 500 Hz: 0.25 Gpk. Sweep

rate of 1.0 octave/min. All three axes.

Vertical Axis Random Vibration: 1.4 Grms overall from
10 to 300 Hz; duration: 1 h.
Longitudinal & Lateral Axis Random Vibration: 0.68
Grms overall from 10 to 200 Hz; duration: 1 h. each

Altitude
Operating

0 to 2.4 km (8000 ft)

Nonoperating

9.1 km (30000 ft)

Shock
Operating

10 Gpk for 10 ms (+ 3 ms), 1/2 sine wave, vertical axis
only

Nonoperating

Flat drop for a 6 in height, 3 drops total (vertical
direction only)

*The operating temperature and humidity for PDP-11/44 systems, which include magnetic tape units, disk units, or card
readers, is the same as defined in Table 1-5 for the PDP-11X44 system.

1.3.2

PDP-11X44 System Specifications

Table 1-5 lists the equipment specifications for the PDP-11X44 system including the TU58.

1-7

Table 1-5
Characteristic

PDP-11X44-CA, -CB Equipment Specifications
Description

Mechanical
Cabinet dimensions

76.2 cm long X 54.29 cm wide X 100.33 cm high (30 in
long X 21.38 in wide X 39.5 in high) (not including
leveling feet)

Weight

Unpacked

140.6 kg (310 Ib)

Packed

181 kg (400 1b)

Environmental
Temperature

Operating

10° C to 40° C (50° F to 104° F)

Nonoperating

—40° C t0 66° C (—40° Cto 151° F)

Humidity
Operating

10% to 90% relative (RH) with a maximum wet bulb of
28° C (82° F) and a minimum dew point of 2° C (36° F)

Nonoperating

50% relative (RH) or less to 95% (RH) or less with a
maximum wet bulb of 46° C (115° F)

Vibration

Operating

5t0 22 Hz: 0.01 in DA; 22 to 500 Hz: 0.25 Gpk. Sweep
rate of 1.0 octave/min. All three axes.

Nonoperating
(PDP-11X44
packed for
shipment)

Vertical Axis Random Vibration: 1.4 Grms overall from
10 to 300 Hz; duration: 1 h.
Longitudinal & Lateral Axis Random Vibration: 0.68
Grms overall from 10 to 200 Hz; duration: 1 h each

Altitude

Operating

0 to 2.4 km (8000 ft)

Nonoperating

9.1 km (30000 ft)

Shock
Operating

10 Gpk for 10 ms (+3 ms), 1/2 sine wave, vertical axis
only

Nonoperating

Flat drop from a 6 in height, 3 drops total (vertical
direction only)
1-8

1.3.3 H7140-AA, -AB Power Supply Electrical Specifications
Table 1-6 lists the electrical specifications of the H7140-AA, -AB power supplies.

Table 1-6

Characteristics

H7140-AA, -AB Power Supply Specifications

Description

H7140-AA
Line voltage

90 Vrms — 128 Vrms, single-phase, two-wire and ground (120

Frequency

47-63 Hz

Current (ac)

15 A (rms) maximum at 120 Vac
55 A (peak) maximum at 120 Vac

Power factor

Greater than 0.60 at full output load and low input voltage

Inrush current

65 A peak at 128 Vrms for 1/2 cycle, followed by repetitive
peaks of decreasing amplitude for an additional 8 cycles of

Vrms nominal)

(90 V)

the input voltage

Power

1350 W with maximum load applied at nominal voltage output

Overvoltage condition

Can withstand input overvoltage of 150 Vrms for one second

Noise transient

Low-energy transients

High-energy transients

Conducted noise

Radiated noise

300 V peak voltage spike* containing not more than 0.2 Ws of

energy per spike

1 KV peak voltage spike* containing not more than 2.5 Ws of

energy per spike

CW-10 KHz to 30 MHz, 3 Vrms

RF field strength: 10 KHz to 30 MHz, 1 V/M 30 MHz to 1

GHz, 10 V/m

H7140-AB

Line voltage

180 Vrms — 256 Vrms, single-phase, two-wire and ground

(240 Vrms nominal)

Frequency

47-63 Hz

Current (ac)

9 A (rms) maximum at 240 Vac
33 A (peak) maximum at 240 Vac
1-9

Table 1-6

Characteristics

H7140-AA, -AB Power Supply Specifications (Cont)

Description

Power factor

Greater than 0.60 at full output load and low input voltage

(180 V)
Inrush current

130 A peak at 256 Vrms for 1/2 cycle, followed by repetitive

peaks of decreasing amplitude for an additional 8 cycles of
the input voltage
Power

1350 W with maximum load applied at nominal voltage output

Overvoltage condition

Input overvoltage of 300 Vrms for one second

Noise transient
Low-energy transients

300 V peak voltage spike* containing not more than 0.2 Ws of

energy per spike

High-energy transients

1 KV peak voltage spike* containing not more than 2.5 Ws of

energy per spike
Conducted noise

CW - 10 KHz to 300 MHz, 3 Vrms

Radiated noise

RF field strength — 10 KHz to 30 MHz, 1 V/M 30 MHz to 1
:

GHz, 10 V/m

*A spike is a voltage transient of either polarity and of either common or differential mode, with a rise time (10% to 90%) of
0.1 us or less, and a fall time (to 10%) of 10 us or more. The average power of spikes should not exceed 0.5 W.

1.4 SYSTEM DESCRIPTION
Figure 1-3 is a block diagram of a typical PDP-11/44 system which consists of a console terminal,
modem, TU58 tape unit and selected options. The PDP-11/44 processor incorporates the complete in-

struction set used in the PDP-11/70 processor series and two additional instructions, MFPT and CSM.

The main memory (MS11-L) of the PDP-11/44 is addressed by a 22-bit physical address extension
(PAX) bus which provides access to over 4 million bytes. In addition, the PDP-11/44 enables memory
to be placed on the UNIBUS. This memory resides in the top 124K words of physical address space.
The processor can perform transfers to and from the UNIBUS memory independently of main memory
transfers. DMA devices making a reference to an address allocated to UNIBUS memory will never
access main memory and, therefore, such transfers are not cached.

The PDP-11/44 includes a high-speed cache memory that buffers words between the processor and
main memory. The cache stores those memory locations that will most likely be accessed by the execu-

ting program. The program can be executed quickly by accessing the high-speed cache and must slow
down only occasionally for main memory operations.

1-10

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The memory management system of the PDP-11/44 provides the address relocation and memory protection facilities required in a multiprogramming system. This system enables several user programs to
be located simultaneously in memory. Memory management includes three mapping schemes: 16-bit,

18-bit, or 22-bit. Mapping converts the 16-bit, processor-generated virtual address to a physical address.
A separate mapping scheme, the UNIBUS map, converts 18-bit UNIBUS addresses to 22-bit memory

addresses. This allows devices on the UNIBUS to communicate with main memory via nonprocessor
requests (NPRs).
The memory management system permits instructions or pure code to be mapped into physical memory

separately from data. When this feature is enabled, instructions, index values and immediate operands
are mapped through instruction (I) space. Data, or words that can be modified, are mapped through
data (D) space. The 1/D space facility is enabled under software control. When it is disabled, all memory references are mapped through instruction space.

The internal communication of the PDP-11/44 processor (KD11-Z) is through a 16-bit data bus and a

22-bit PAX bus. Communication between the processor and main memory is through the extended
UNIBUS (EUB) and the data lines of the UNIBUS. The UNIBUS provides the path for transfers

between the processor and its associated main memory, the peripherals, or the memory on the
UNIBUS. The UNIBUS interface module (UBI) controls the information transfers to and from the

PAX bus, the EUB, and the UNIBUS.
The multifunction module (MFM) consists of an 8085 microprocessor and the logic necessary to enable
the execution of the console command set in the CPU. The 8085 software contains diagnostic programs

to test logic and data paths.
In addition to the standard features of the PDP-11/44, the commercial instruction set processor (CISP)
and floating-point processor (FPP) can be installed in dedicated slots of the backplane.
The following paragraphs provide a brief description of each of the standard and optional components

of the PDP-11/44 system.
1.4.1

KD11-Z Central Processor

The KD11-Z central processor is comprised of four hex-height modules (M7094, M7095, M7096, and
M7098) and one double-height module (M7090). The following provides a brief description of each.
1.4.1.1

Data Path Module (M7094) - The data path module contains the data path logic and the

memory management logic. The data path performs arithmetic and logic processing, shifting of 8-, 16-,

and 32-bit data formats, byte swapping and sign extension of data, storage of general register data, and
storage of status information. Data comes from or goes to the CIS and floating-point options via the Amultiplexer (AMUX) bus of the data path. The memory management section of this module performs
address relocation and contains several of the memory management registers.
1.4.1.2

Control Module (M7095) — The control module contains the control store programmable read-

only memories (PROMs) and associated logic required to decode and execute PDP-11 instructions. It
also contains the system clock, power-fail /autorestart logic, boot control logic and trap handling logic.

1.4.1.3

Multifunction Module (M7096) ~ The multifunction module (MFM) contains an 8085 micro-

processor, two serial line ports, a line clock and related logic. The microprocessor allows the system

terminal to be used as a programmer’s console. The 8085 software routines enable the execution of the
console commands discussed in Chapter 2. The serial line port used for the system terminal also serves
as a remote diagnostic serial port. The second serial line port of the MFM supports a TUS8 tape unit or
can be used with other serial line devices.

1.4.1.4
UNIBUS Interface Module (M7098) — The UNIBUS interface module (UBI) provides the
logic which enables the processor to access the UNIBUS. It also includes bus arbitration logic for interrupts and NPRs, the boot circuits which allow booting of up to four devices, and buffers for the PAX
data lines to and from the processor. The UNIBUS map contained on the module allows direct memory
access (DMA) transfers between main memory and peripherals on the UNIBUS. The UBI also controls
the operations of the EUB.

1.4.1.5 Console Interface Module (M7090) — The console interface module (CIM) links the central
processor to the console terminal, TUS58 tape drives and the remote diagnostic unit. Signals between the
processor and these units are buffered by the CIM to provide noise and static immunity and are converted to the proper voltage levels. The CIM also has voltage monitoring circuitry which can detect
over or under voltage conditions of the power supply at the processor backplane.
1.4.2
MOS Memory
The MOS memory (MS11-M) provides 256K bytes on each module. A maximum of four modules can
be installed in the PDP-11/44 system. Each memory module consists of a single hex-height module

(M8722) that contains the UNIBUS /extended UNIBUS interface, timing and control logic, error correcting code (ECC) logic and a MOS storage array. The module also contains circuitry for ECC initialization and memory refresh, and a control and status register (CSR). The MS11-M also provides
address interleaving for improved speed of operation.
1.4.3

KK11-B Cache Memory

The KK11-B cache increases system performance by decreasing processor-to-memory read-access time.
The cache is an 8K byte, high-speed RAM which is used to store the most commonly accessed memory
locations. It is contained on a single hex-height module (M7097) and is organized as a directly mapped
cache with a write-through facility.
1.4.4
UNIBUS Terminator (M9302)
The M9302 terminator is a double-height module that must be installed in all PDP-11/44 systems at
the end of the UNIBUS furthest from the processor. This module contains terminating resistors and
logic.
1.4.5 Optional Modules and Devices
The following options can be used with the PDP-11/44 to expand the system’s capabilities.
1.4.5.1

FP11-F Floating-Point Processor — The FP11-F is contained on a single hex-height module

(M7093) and allows floating-point operations to be executed with greater speed than equivalent software routines. The floating-point instructions provide for both single-precision (32-bit) and double-precision (64-bit) operands.

1.4.5.2
KE44-A Commercial Instruction Set (CIS) Processor — The KE44-A is contained on one quadheight module (M7091) and one hex-height module (M7092). It enables the KD11-Z to execute the
PDP-11 commercial instruction set which provides for manipulation of byte strings, character handling
and decimal arithmetic operations.

1.4.5.3

TUS8 DECtape II - The TUS58 is a random-access, fixed-length block, mass-storage tape sys-

tem. It uses DIGITAL preformatted tape cartridges which have a storage capacity of 256K bytes of
data in 512-byte blocks. There are 256 blocks on each of the two tracks. The tape cartridges are miniature reel-to-reel packages containing 42.7 m (140 ft) of 3.81 mm, (0.150 in) wide tape. The TUS58
interfaces to the processor through the CIM module and through the serial line unit (SLU) on the multifunction module.

1.4.5.4 Standard PDP-11 Peripheral Devices — The /O capabilities of the PDP-11/44 can be expanded through the use of PDP-11 peripheral devices such as card readers, alphanumeric display terminals, lineprinters, teletypewriters or high-speed paper tape readers. Available storage devices include
magnetic tapes and disk memories.
1.5
RELATED DOCUMENTS
Table 1-7 lists the manuals and publications that contain information related to the installation and
operation of the PDP-11/44 processor system. This information is available from the locations listed in
the following paragraphs.

Table 1-7

Related Publications

Title

Document Number

BA11-AA,-AB Mounting Box and Power System
Technical Manual

EK-BAI1A-TM

FP11-F Floating-Point Technical Manual

EK-FP11F-TM

KE44-A CISP Technical Manual

EK-KE44A-TM

MS11-M MOS Memory User’s Guide

EK-MS11M-UG

PDP-11 Peripherals Handbook

EB-07667-20/78

PDP-11/04/34A/44/60/70 Processor Handbook

EB-17716-18/79

Terminals and Communications Handbook

EB-07666-20/78

TUS8 DECtape I1 Technical Manual

EK-OTUS8-UG

BA11-A Box Assembly Field Maintenance Print Set

MP00832

11/44 System Field Maintenance Print Set

MP00809

PDP-11/44 Unit Assembly (IPB)

EK-01144-1P

BA11-A Unit Assembly (IPB)

EK-BA11A-IP

H7140 Power Supply (IPB)

EK-H7140-IP

1.5.1
DIGITAL Personnel Ordering
Additional copies of this document and printed copies of the documents listed may be obtained from:

Digital Equipment Corporation
444 Whitney Street
Northboro, Massachusetts 01532

ATTN: Printing and Circulation Services (NR2/M15)

Customer Services Section
1.5.2

Customer Ordering Information

Purchase orders for supplies and accessories should be forwarded to:
Digital Equipment Corporation
Accessories and Supplies Group

Cotton Road
Nashua, New Hampshire 03060
Contact your local sales office or call DIGITAL Direct Catalog Sales toll-free 800-258-1710 from 8:30
a.m. to 5:00 p.m. eastern standard time (U.S. customers only). New Hampshire, Alaska and Hawaii

customers should dial (603)-884-6660. Terms and conditions include net 30 days and F.O.B. DIGITAL
plant. Freight charges will be prepaid by DIGITAL and added to the invoice. Minimum order is

$35.00. Minimum does not apply when full payment is submitted with an order. Checks and money
orders should be made out to Digital Equipment Corporation.

CHAPTER 2

OPERATION

This chapter describes the hardware characteristics of the PDP-11/44 system and includes the addresses assigned to the internal registers and detailed descriptions of the register bit functions. Additional
information is contained in the PDP-11 Processor Handbook 1979/80 or the latest edition.
User programs for the PDP-11/44 can be developed using the information in this chapter and the information contained in the software operating system documents.
2.1

FRONT CONTROL PANEL

The operator’s control panel (Figure 2-1) is located on the lower section of the front bezel.
Table 2-1 lists and describes the functions of the front panel controls and indicators.

LOCAL

oFF

OC DSBL

STD

RUN

DC ON BATT REMOTE HALT CONT BOOT,

pP11aa O O O O

Figure 2-1

[

]

Front Control Panel

2-1

Table 2-1

Description

Front Panel Switches and Indicators

Status

Function

Power (4-position
rotary keyswitch)

The dc power is removed from the system and cooling
fans are off. The DC OFF position does not remove ac
power from the system. The ac power is removed only

DC OFF

by disconnecting the line cord.

is applied to logic
Normal ON position. The dc power
and fans are on. The system terminal can be used in
console mode or program 1/O mode. The HALT posi-

LOCAL

tion of the toggle switch is disabled.

Local disable. Normal power is applied to the system.
Console mode is disabled but the console terminal can

LOC DSBL

operate in program I/O mode.

Standby. Main dc power (+5V, 415V, —15V) is off.
Memory voltages are present and fans remain on.

STD BY

HALT/CONT/BOOT
(3-position
toggle switch)

HALT

The CPU program is stopped.

CONT

Continue. The CPU program is continued.

BOOT

A momentary position which enables the bootstrap program. When the toggle switch is released, it returns to
the CONT position.

Indicators

RUN

DC ON

Processor is executing instructions.

Off

Processor has halted.

Indicates dc power is present and all voltages are within

Blinking (5 Hz)

specified levels.

Indicates one or more of the voltages is not within specified levels.

Off

The dc power is off.

2-2

Table 2-1

Front Panel Switches and Indicators (Cont)

Description

Status

Function

BATT

Battery is present and charged to 90% or greater capacity. Used only when the battery backup unit (H7750) is
installed.

Slow Blinking

Battery is at less than 90% capacity and is charging.

Fast Blinking

The ac power has failed, discharging, memory contents
are valid.

Off

Battery is fully discharged or not present and memory
contents will be destroyed when the ac power fails.

CPU is under control of the remote diagnostic unit.

REMOTE

Off

CPU is not being accessed by the remote diagnostic

unit.

2.2 CONSOLE COMMANDS
The following paragraphs provide a description of the PDP-11/44 console commands and brief examples of their use. The system terminal can be used to input console commands only when the system is
in console mode. Console mode can be entered in either of two ways:
1.

The processor halting, or

The user typing the console break character, control P ( NP,

When the system is not in the console mode, it is in the program I/O mode, and data to or from the
terminal is controlled by the software currently being executed.
The commands that can be performed in the console mode are listed in Table 2-2.
NOTE
All addresses specified in a console command are assumed to be 22-bit physical addresses and all data
transfers are 16-bit word transfers.
2.2.1

Special Functions

In the descriptions of each console command, several expressions, special characters, and qualifiers are
used. Angle brackets, (N), are used to denote category names. For example, the category name (ADDRESS) is used in an expression to represent any valid address. In an actual command, an address
(e.g., 17775604) would be typed in place of the category name. Table 2-3 lists and describes the terms
and characters used in the syntax expressions.
Square brackets, [N], surrounding an expression in a command description indicate that the expression
is optional and is not required to issue a valid command.

2-3

Table 2-2

Console Mode Commands

Command

Designation

Command

Designation

ADDER

BOOT
CONTINUE
DEPOSIT
EXAMINE
FILL

B
C
D
E
F

INITIALIZE
MICROSTEP
SINGLE-INSTRUCTION STEP
REPEAT
START
SELF-TEST

I
M
N
R
S
T

HALT

BINARY LOAD/UNLOAD

Table 2-3

Console Command Terms and Characters

Name

Description

(SP)
(COUNT)

One space
A numeric count in octal

(ADDRESS)

An address argument in octal

(DATA)

A data argument in octal

(QUALIFIER)
(INPUT-PROMPT)

A command modifier
The console’s prompt string () ) ))
Carriage return
Line feed

(CR)
(LF)

2.2.1.1
Console Command Qualifiers — Several of the console commands can be modified by typing
qualifiers. Qualifiers expand the capability of commands by providing a number of options. All qualifiers are optional and are not required to issue a valid command. A qualifier always begins with a slash
(/). Table 2-4 lists the qualifiers and describes their functions.

2.2.1.2

Special Address Field Characters — The special characters used in the (ADDRESS) field of a

command to modify the address argument are listed and defined in Table 2-5.

2.2.1.3

Control Characters — A number of control characters are available to the user. Table 2-6 lists

control characters and functions..

2-4

Table 2-4

Console Command Qualifiers

Qualifier

Function

A general register qualifier that provides a method of specifying a general regis-

ter as the address argument. In the examine or deposit command, an E or D can
be typed followed by the /G qualifier and the register number (0 to 17g), rather
than the full 22-bit address (eight octal digits).
/N

This qualifier permits examine or deposit commands to be performed on sequential addresses without issuing a new command for each address. The /N
qualifier has an associated qualifier value (COUNT), which specifies the number of sequential operations to be performed. The syntax for the /N qualifier is:
/N [:{COUNT)]
The actual number of operations to be performed can be expressed as: the initial operation (1) plus (COUNT - 1) additional operations. The default condition for (COUNT) is one.

This qualifier allows a machine-dependent register to be specified as the address argument similar to the /G qualifier that specifies a general register. The
address of each machine-dependent register is defined as follows:

/TB

OO
—

PbhWN—~=O

Address

Register
Floating-Point Data
CIS Micro PC (CPC)
CIS Data
CPU Data CPU Micro PC (MPC)
Cache Data
CPU Error Register
MFM Data
UNIBUS Data

Signal Register

The take bus qualifier is a maintenance feature which allows the console to per-

form bus transfers even though the bus may be hung.

/CB

The cache bypass qualifier allows main memory transfers to be performed even

though cache is turned on and the transfer would normally result in a cache hit.
This only inhibits a hit for the current command.
/E

This qualifier specifies test-extensive and is used only with the self-test (T) command.

This qualifier specifies test-extensive-APT and is used only with the self-test (T)
command for manufacturing use.

2-5

Table 2-5

Special Address Field Characters

Character

Function

The plus sign in the (ADDRESS) field of a command will cause the last address used to be incremented by two and used as the address argument of the
command. If the /G or /M qualifier is also specified in the command, the last
address is incremented by 1.
The minus sign in the (ADDRESS) field of a command will cause the last address to be decremented (by two) and used as the address argument of the command. If the /G or /M qualifier is also specified in the command, the last address is incremented by 1.
The “at” sign in the (ADDRESS) field of a command will cause the command
to use the last data as the address argument. The “at” sign may be used following an indirect addressing chain of instructions.
The asterisk in the (ADDRESS) field of a command will cause the command
to use the last address as the address argument.

The letters SW in the (ADDRESS) field of a command will cause the command to use the address of the switch register as the address argument. This
may be used with examine or deposit commands.
NOTE

When accessing the switch register by its UNIBUS address, 17 777 570, only a
read operation can be performed.

Table 2-6

Control Characters

Control
Character

Echo

Function

(CTRL-C)

Causes all the repetitive console operations to be aborted.

(CTRL-O)

Alternately suppresses and continues the display of data at the
terminal. While the display is suppressed, the operation continues
but no results are printed. An error or the end of the command
will cancel the effect of the control character.

(CTRL-P)

Initiates the console mode if the keyswitch is in the LOCAL position.

2-6

Table 2-6

Control
Character

Control Characters (Cont)

.
Echo

Function

(CTRL-Q)

Restarts the terminal output that was suspended by CTRL-S.

(CTRL-S)

Suspends the terminal output until CTRL-Q is typed. No output

is lost.

(CTRL-U)

Cancels the current input line and discards it.

(RUBOUT) OR
(DELETE)

Deletes the last character typed on the terminal. The terminal re-

sponds to the first RUBOUT by echoing a backslash (\) and the
character being deleted. Successive RUBOUT will only echo the
character being deleted. If the user attempts to rubout beyond
the start of the command, the RUBOUT will continue to echo the
first character of the input string. The first character typed by
the user that is not a RUBOUT will result in the terminal echoing
a backslash (\) and the new character being entered. As an example, if the user types:
YWYE(SP)17713(RUBOUT) (RUBOUT)65000(CR)

the displayed echo will be:
Y)YE17713\31\65000
which is equivalent to the user deleting the entire line by control
character CTRL-U, then typing the following:

Y)YE(SP)17765000(CR)

2.2.2
ADDER Command
This command prints the 16-bit result of the current address pointer and the last data examined plus 2.
This command can be used to calculate the effective address for an instruction using mode 6, register 7

or mode 7, register 7.
The syntax for the ADDER command is as follows:
A(CR)

2-7

The following are examples of the ADDER command.
001000

016767

MOV

001002
001004
001006

000774
001772
000000

HALT

2000,3000

E 1000(CR)
00001000 016767

E(CR)
00001002 000774
A(CR)
002000

E(CR)
000001004 001772
A(CR)

003000
E(CR)
00001006 000000

2.2.3

BOOT COMMAND

The syntax for the BOOT command is as follows:
B [(SP) (DEVICE-IDENTIFIER)] (CR)

The BOOT command can be performed only if the processor is halted. When typing B(CR) without
the optional device code, a default boot is performed depending on the setup of the boot switches located on the UNIBUS interface (UBI) module (M7098). The optional device identifier is a two-character code which identifies the peripheral bootstrap to be performed. Device codes for some typical peripherals are listed in Table 2-7.

The device identifier may also include the unit number of the peripheral (e.g., DK1 boots RKO05 unit
number 1). If a unit number is not typed, the default number is 0.
When the BOOT command is issued, the device code typed is compared to the device identifiers of the
boot ROMs. If the device is not supported by the boot ROMs (i.e., no device match), the console will
respond with the console prompt ()))). If the device is supported or if no device code was typed
(default boot), an initialize is issued. The priority bits of the processor status word are set to 7 and the
carry bit is set or cleared, depending on the setting of the boot switches. If the carry bit is cleared, the
ROM diagnostic programs will be performed prior to the initiation of the bootstrap program for the
specified device. General register O is loaded with the unit number, or with zero if none is typed. The
PC is then loaded with the starting address of the boot program. If a device code was not typed, the PC
is loaded with the starting address indicated by the boot switches. Once the PC is loaded, the processor
is started and the system enters program I/O mode.

2-8

Table 2-7

Device Bootstrap Identifiers

Device

Identifier

Device

Identifier

TAIll

RP04/05/06 RM02/03

DD
DK

TUSS8
RKO03/05/05J (Units 2)

DL
DM
DP
DS
DT

RLO1
RK06/07
RP02/03
RS03/04
TUS5/56

PR
TT
XM
XW
XU

RXO01

’

Device

RX02

TU16/E16(TM02/03)

MS
MT

TS04
TU10/TE10/TS03
PCO05 (High-Speed Reader)
ASR33 (Low-Speed Reader)
DMC-11
DUP-11
DU11
DL11

The following are examples of BOOT command.
y)Y)YB (CR)

Perform the default boot.

y))YB (SP) DK1 (CR)

Boot the RKOS5, Unit 1.

Up to four devices can be selected for program loading. To determine the value of the starting address
selected by the switch pack E28 on the UBI module and the devices which are controlled by a bootstrap
ROM, perform the following procedure:
1.

Examine address 773024 and evaluate the response as follows:
165 XYZ = Boot to Console Mode
173 XYZ = Boot to selected device

The remaining three octal digits (XYZ) can be separated into the binary values associated
with the ES58 switch positions as follows:

Switch
Value

S3 | S4

——

X
I

0-7g

‘

|S6|

S7]|

S9|

SI0

0-7g
Binary 1 = On
Binary 0 = Off

2-9

0,2,4 or 63

To identify the device bootstrap ROMs that are installed, initiate the diagnostic program
MAINDEC CZMB9B or examine the following five addresses and compare the response with
the device ROM identification numbers listed in Table 2-8.
17776774
17773000
17773200
17773400
17773600

(CPU diagnostic ROM)
(Device ROM 1)
(Device ROM 2)
(Device ROM 3)
(Device ROM 4)

A 177776 response will indicate the continuation of a ROM diagnostic program to an additional ROM.

An XXX777 response will indicate a ROM failure or no ROM present at the addressed location.
2.2.4

CONTINUE Command

The syntax for the CONTINUE command is as follows:
C (CR)

If the processor was halted when the CONTINUE command was initiated, the processor will begin
operating and the system will enter the program I/O mode. If the processor was running when the
CONTINUE command was initiated, the system will only enter the program I/O mode.

Table 2-8

Octal ID

Bootstrap ROM Identifiers

Device ROM

Octal ID

Device ROM

041460

PDP-11/44 Diagnostic

050122

ASR33 (Low-Speed Reader)

041524

TAll

042104

TUS8

054114

042113

RKO03/05/05J

177776

042113
042114

TUS5/56
RLO1

177776

042115
042120

RKO06/07
RP02/03

054115
177776

042120
042120
042123

RP04/05/06
RMO02/03
RS03/04

177776
054125

042130

RXO01

177776

042131

RX02

177776

046515
046523
046524
050122

TU16/45/77/TE16
TS04
TU10, TE10, TSO03
PCO05 (High-Speed Reader)

054127
177776
177776

2-10

DLI11

DMC-11

DU11

DUP-11

2.2.5 DEPOSIT Command
'
The syntax for the DEPOSIT command is as follows:
D [(QUALIFIER)](SP) (ADDRESS) (SP) (DATA) (CR)

The DEPOSIT command will deposit (DATA) into the (ADDRESS) specified. The address space
will depend upon the qualifiers specified with the command.
Initiating deposits while the processor is running is illegal unless the deposit is to the console switch
register (D(SP)SW (SP) (DATA) (CR)). Since the switch register is internal to the console, the qual-

ifiers /TB and /CB would be useless.
Table 2-9 lists the qualifiers that can be used with the DEPOSIT command.
The (ADDRESS) in the DEPOSIT command can be a one-to eight-digit octal number, SW or any of
the special address characters (+, —, *, @). The (DATA) in the command can be a one-to six-digit
octal number.
Upon completion of the deposit, the console will respond with the console prompt ()))).

The following are examples of the DEPOSIT command.
Y)Y)YD(SP)1000(SP)5

Deposits 5 into location 1000.

Y)Y)YD(SP)+ (SP)776

Deposits 776 into last address +2. If preceded by above example, then data would be deposited into location 1002.

Y)Y YD(SP)*(SP)400

Deposits 400 into last address. If preceded by above example,
then data would be deposited into location 1002.

»Y)YD/M(SP)4(SP)240

Deposits 240 into the processor micro PC.

»))YD/G/N:5(SP)0(SP)35

Deposits 35 into the next 5 general registers starting with RO.

2.2.6 EXAMINE Command
The syntax for the EXAMINE command is as follows:
E [[(QUALIFIER)](SP) (ADDRESS)](CR)]

Examines are legal while the processor is running. The console will respond to the examine command
by printing the eight-digit physical address examined followed by the six-digit octal data contained in
that location. This will occur unless the printout is inhibited by a control character. Upon completion of
the examine, the console will respond with the console prompt ()))).
The qualifiers that can be used with the EXAMINE command are listed in Table 2-10.
The (ADDRESS) in the EXAMINE command can be a one- to eight-digit octal number, SW or any of
the special address characters (4+, —, *, @). The (ADDRESS) in the EXAMINE command is optional. If none is typed, the last address is incremented by 2 or 1 if the /G or /M qualifier is used.

2-11

Table 2-9

Qualifiers

Deposit Command Qualifiers

Function

Enables deposits into the general registers without typing the full eight-digit oc/N, /TB or /CB can be used in conjunction with the

tal address. The qualifiers
/G qualifier.

The only machine-dependent register that can be deposited into is the CPU micro PC register (address 00000004). The data deposited into this register will be
used as the next processor micro PC.

Allows deposits into sequential locations.

/TB

The take bus qualifier is used for maintenance purposes only.

/CB

Using the cache bypass qualifier may cause a cache invalidate if the address
specified is in cache.

Table 2-10

Qualifier

Examine Command Qualifiers

Function

Enables the general registers to be examined without typing the full eight-digit
octal address. The qualfiiers /N, /TB, /CB can be used in conjunction with the

/G qualifier.
/M

Allows the machine-dependent registers to be examined. The qualifiers /N,
/TB or /CB can be used in conjunction with the /M qualifier.

Allows examines of sequential locations.

/TB

The take bus qualifier is used for maintenance purposes only.

/CB

Using the cache bypass qualifier may cause a cache invalidate if the address
specified is in cache.

2-12

The following are examples of the EXAMINE command.

Y)Y YE(SP)1000(CR)
00001000 002625

))YE(CR)

00001002 005646

»)YE/G(SP)7(CR)

17777707 001514

))YE(SP)@(CR)

00001514 012737

Examine location 1000.

Examine the next location. An equivalent command would
be: E(SP) + (CR).

Examine the PC.

Now examine the location pointed to by the PC (i.e., use the
last data for the new address).

YYE/M/N:5(SP)0O(CR)
00000000 130260

Examine the next 5 machine-dependent registers starting with
the machine-dependent register O.

00000001 177777

00000002 177777
00000003 177777

00000004 000010

2.2,7
FILL Command
The syntax for the FILL command is as follows:

F[(SP)(COUNT)](CR)
The console will send (COUNT) null characters after each (CR) before any further transmissions.
When a power failure occurs, the (COUNT) will be cleared.

The FILL command sets the fill count to the value typed in the (COUNT) field, where (COUNT) is a
one- to six-digit octal number. However, the maximum fill count is 17 (octal). If the (COUNT) entered

is greater than 17, then the fill count is set to 17. If no (COUNT) is entered, the fill count is set to zero.
Also, on powerup, the fill count is set to zero. Upon completion of the FILL command, the console
responds with the console prompt ()))). The FILL command causes the (COUNT) number of null
characters to be echoed following a (CR).
The following are examples of the FILL command.

Y)YF(SP)4(CR)

Set fill count to 4. Subsequent carriage returns will be followed by 4 null characters generated by the MFM module as
shown below.

»)YE{(SP)1000(CR) (NULL) (NULL)(NULL)(NULL)({LF)
00001000 002625 (CR) (NULL)(NULL)(NULL)(NULL)(LF)

Y)Y YF(CR)

Resets the fill count to 0.

2-13

2.2.8

HALT Command

The syntax for the HALT command is as follows:
H(CR)

The HALT command initiates a halt by asserting the CPU halt request. If the request is honored and
the clock is stopped, the console examines register R7 (the PC), then prints 17777707 and the updated
PC value. If the processor does not halt within 600 ms, an error message is printed.

If the processor is halted when the HALT command is issued, the halt request is not asserted and the
console responds with the console prompt ()))). No error message is issued.
The following are examples of the HALT command.

))YH(CR)
17777707 001000 (CR)

Halt the CPU and print the contents of R7.

)Y YH(CR)
YY)

Since the processor is already halted, this command is ig-

2.2.9

nored.

INITIALIZE Command

The syntax for the INITIALIZE command is as follows:
[{CR)

The INITIALIZE command is valid only if the processor is halted. Upon receiving a valid INITIALIZE command, the console issues a UNIBUS initialize. The console then issues the console
prompt ()))).
2.2.10

MICROSTEP Command

The syntax for the MICROSTEP command is as follows:
M[(SP) (COUNT)](CR)

of microinstructions specified by the (COUNT) value. If
The CPU is allowed to execute the number
no count is specified, one microinstruction is performed.

The MICROSTEP command is valid only if the processor is halted. The (COUNT), if specified, is a
one- to six-digit octal number. The command will cause the console to perform an initial microinstruction plus (COUNT)-1 additional microinstructions. For each microstep, the console enables the
processor clock for one cycle, examines the micro PC register, and prints the register address
(00000004) and contents of the PC register.

The count is decremented after each microinstruction is performed. When the count equals 0, the console will print out the last micro PC and the console prompt () ) }). The console is then in the spacebar
step mode and an additional microinstruction is performed each time the spacebar is pressed. When no
count is specified, the console enters spacebar step mode after the first microinstruction is performed.

2-14

The following is an example of the MICROSTEP command:

Y)Y YM(SP)3(CR)

Perform 3 microinstructions

00000004 000010
00000004 000015
00000004 000210
YY)

The console is now in the spacebar step mode and another mi-

croinstruction can be executed by pressing the spacebar.
Execution of the MICROSTEP command causes the address of the CPU micro PC (00000004) and the
contents of that location to be printed. This is the default printout for the MICROSTEP command.
Other machine-dependent registers may be monitored during microstepping. The following example illustrates this capability.

))YM(CR)

00000004 000015

) YE/M(SP)10(CR)
00000010 000777
) »00000010 000000

This command executes one microstep; sets the console into

the spacebar step mode. The second command 10 examines
the machine register 10 (UNIBUS data) and changes the
default printout. Pressing the spacebar will then cause another microstep to be performed and the new contents of machine register 10 to be printed.
2.2.11
SINGLE-INSTRUCTION-STEP Command
The syntax for the SINGLE-INSTRUCTION-STEP command is as follows:
N[(SP) (COUNT)](CR)

The SINGLE-INSTRUCTION-STEP command is valid only if the processor is halted. The
(COUNT), if specified, is a one- to six-digit octal number. This command will cause the console to
perform an initial instruction plus (COUNT)-1 additional instructions. For each instruction step, the
console enables the processor clock for one instruction, examines the PC, and prints its address
(17777707) and contents.
The count is decremented after each instruction step is performed. When the count equals 0, the console will print out the last PC and the console prompt ()))). The console is then in spacebar step mode

and an additional instruction step can be performed by pressing the spacebar. When no count is specified, the console enters spacebar step mode after the first instruction step is performed.
The following is an example of the SINGLE-INSTRUCTION-STEP command:

Y)IYN(SP)3(CR)

Perform 3 single-instruction steps.

17777707 001000
17777707 001002
17777707 001004
)

The console is now in spacebar step mode and another instruc-

tion can be performed by pressing the spacebar.

2.2.12

START Command

The syntax for the START command is as follows:
S[(SP)(DATA)](CR)

The START command is valid only if the processor is halted. The (DATA), if specified, is a one- to
six-digit octal number that is deposited into the PC when the command is performed. The console responds to a valid START command by issuing an initialize and depositing data into the PC. If no data
is specified, the PC is unchanged. Following the initialize and deposit, the processor continues and the
system enters the program I/O mode.

The following are examples of the START command.

Y)YS(SP)1000(CR)

Deposits 1000 into the PC and starts the processor from that
location.

The following combination of commands is equivalent to the above command:
»YyD/G(SP)7(SP)1000(CR)

Y)Y YS(CR)I

2.2.13

Deposits 1000 into the PC.

Initialize — Continue the processor at current PC (1000).

SELF-TEST Command

The syntax for the SELF-TEST command is as follows:
T[(QUALIFIER)](CR)

The SELF-TEST command is valid while the processor is running only if no qualifiers are specified. If
qualifiers are specified, the processor must be halted. The qualifiers that may be used are /E (testextensive) or /A (test-extensive-APT).

The self-test is executed in response to this command and also upon entry into console mode via AP or
processor halt.

If the self-test is completed without error, the message CONSOLE is printed followed by the console
prompt. If the self-test was entered as a result of a processor halt, then the test is run, the PC is examined, the contents are printed, and the console prompt ()))) is printed.
If the T/E or T/A command is entered, additional tests are performed along with the self-test. The
console responds to the T/E command by printing CONSOLE-TESTB followed by the console prompt.
NOTE

Caution should be exercised in performing these
commands because the T/E and T/A commands
modify main memory. The T/A command restarts
the processor after execution of the command.

If any of the tests being performed detect an error, the appropriate error message is printed and the test
program will loop on the error.

2.2.14 BINARY LOAD/UNLOAD Command
The syntax for the BINARY LOAD command is as follows:

X{(SP) (ADDRESS) (SP) (COUNT) (CR) (COMMAND CHECKSUM)
(DATA)(LOAD CHECKSUM)
2-16

The syntax for the BINARY UNLOAD command is:
X(SP) (ADDRESS) (SP) (COUNT) (CR) (COMMAND CHECKSUM)

NOTE
Bit 15 of the (COUNT) field indicates direction
control (1=UNLOAD,
0=LOAD).
The BINARY LOAD/UNLOAD command enables strings of bytes of binary data to be read from or

written into memory. The number of binary bytes is represented by the (COUNT) field. The console
does not perform byte transfers. The load or unload command is executed by assembling the bytes into
words before performing the transfer. Since only word transfers are supported, the (COUNT) field
must represent an even number.

During the BINARY LOAD command, the processor cannot process control characters typed by the
user since the binary data contains similar characters. To prevent the BINARY LOAD command from

being initiated erroneously, the command is terminated by a special (CHECKSUM)

character.

During either the BINARY LOAD/UNLOAD command, the checksum is calculated in a similar manner. The command checksum is a binary byte of data that represents the 2’s complement of the sum of

the ASCII characters that comprise the command string, including (CR). As the command string is
read by the console, each character is added to a memory location, which is initially set to 0. If no

errors occur, the result of the addition will be zero. If the checksum is correct, the console echoes the

prompt string but remains in binary mode. If the command is a binary load, the echo of the input data
is suppressed. If the checksum is incorrect, an error is reported. The command checksum is not loaded
into memory and does not cause the (COUNT) to be decremented.
'

In the BINARY LOAD command, a binary string of data of length (COUNT) + 1 will be sent to the
console once the requester receives the input prompt which indicates the console’s acceptance of the

command. The console will sequentially deposit all but the last byte into memory, starting at (ADDRESS). As the console receives the binary data, it calculates the load checksum. Similar to the command checksum, the load checksum is a binary byte of data which when added to the total checksum,
should yield a zero result. Once the (COUNT) is exhausted, the load checksum is sent by the console.
If an error is encountered during the load or checksum, the error is reported. If no errors occur, the
console will respond with the console prompt.
In the BINARY UNLOAD command, the console processes the command and checks the checksum.
If the checksum is correct, the console responds with the input prompt followed by a string of bytes,
which is the binary data requested. As each binary byte is sent from the console, the 2’s complement is

added to a byte, initially set to zero. This byte will be sent upon completion of the command and it is
followed by the input prompt. The receiver of the unloaded data can now check to ensure that all bytes

were correctly received.

2.2.15
REPEAT Command
The syntax for the REPEAT command is as follows:
R(SP)(COMMAND)(CR)

This command will repeatedly execute the EXAMINE or DEPOSIT command and is terminated by
the control character CTRL-C ( A C).

2.2.16 Summary of Errors
When an error is detected during the performance of a console command, the errors listed in Table 2-11

may be reported by the console.

2-17

Table 2-11

Summary of Errors

Character

Definition

201

Syntax error, illegal command.

Illegal internal processor register designated using /M qualifier.

215

Command is illegal while processor is running.

220

Transfer error. The console tried to examine or deposit but failed due to memo-

721

Halt error. The console tried to halt the processor but failed.

722

CPU hung. As opposed to 720, the console directed the processor to initiate a

ry time-out or parity error.

transfer, but the transfer was never started.

Checksum error. In executing a BINARY LOAD/UNLOAD command, a

730

checksum error occurred.

781

Checksum error. In executing the self-test, the console control store was found

782

Checksum error. In executing the self-test, the console control store was found

785

Error in read/write test for console RAM.

TA7

Halt/continue test of test/extensive failed.

7A8

PAX data bus test of test/extensive failed.

?7A9

PAX address test of test/extensive failed.

7AA

Switch register test of test/extensive failed.

to have a checksum error in PROM 1.

to have a checksum error in PROM 2.

2.2.17

Summary of Commands

Table 2-12 is a list of the console commmands, special characters, modifiers and qualifiers.
2.3

PDP-11/44 REGISTERS

The upper 4K of the physical address space is assigned to the CPU registers and I1/O device registers.
Table 2-13 lists some of the registers and their associated addresses.
2.3.1

CPU Registers

The CPU contains several registers which can be used to store processor status information, error information and interrupt requests. Eight general purpose registers are also included to be used as accumulators, counters, index registers, or for other programming functions.

2-18

Table 2-12

Console Command Summary

Syntax

Command

BOOT

[(SP) (DEVICE IDENTIFIER)] (CR)

C (CR)
D [(QUALIFIERS)]({SP) (ADDRESS) (SP) (DATA) (CR)
E [(QUALIFIERS) (SP) (ADDRESS)] (CR)
F [(SP) (COUNT)] (CR)
H (CR)
I (CR)
M [(SP) (COUNT)] (CR)
N [(SP) (DATA)] (CR)

EXAMINE
FILL
HALT
INITIALIZE
MICROSTEP
SINGLE-

S
T
A
R

INSTRUCTION STEP
START
SELF-TEST
ADDER
REPEAT

[(SP) (DATA)] (CR)
[(QUALIFIER)] (CR)
(CR)
(COMMAND) (CR)

CONTINUE
DEPOSIT

Special

Characters

Function

Control C

Causes the aborting of all repetitive console operations.

Control O

Enables/disables terminal output.

Control P

Forces entry into console mode if keyswitch is in LOCAL position. Programs in
operation will continue, however, no 1/O operations to a terminal can occur by
program until the program I/O mode is reentered.

Control U

Deletes entire line currently being typed.

Control S

Stops terminal output.

Control Q

Starts terminal output.

Address Modifiers

Autoincrement

—

Autodecrement

Use last address

Use last data as address

Switch register

Qualifiers

/G
/N:(COUNT)
/M
/TB
/CB
/E
/A

General register
Multiple operations
Machine-dependent registers
Take bus
Cache bypass
Test-extensive
Test-extensive-APT

2-19

PDP-11/44 CPU and 1/0 Device Register Address

Table 2-13
Address

17 777 776
17777772

Processor Status Word (PSW)
Program Interrupt Request (PIRQ)

17 777 707 - 17 777 700

CPU General Registers

CPU Error
Cache Registers

17 777 766
17 777 744,46,50,52,54

17777 676 — 17 777 660
17 777 656 — 17 777 640
17 777 636 - 17 777 620
17777 616 — 17 777 600

User Data PAR, Reg. 0-7
User Instruction PAR, Reg. 0-7
User Data PDR, Reg. 07
User Instruction PDR, Reg. 0-7

17777 576
17 777 574
17 777 572
17 777 566 — 17 777 560

MM Status Register 2 (SR2)
MM Status Register 1 (SR1)
MM Status Register 0 (SRO)
Console Terminal SLU

17 77x xx0 — 17 76x xx0

TUS58 DECtape SLUs
Switch Register

17 777 570
17 777 516

17772376 — 17 772 360

MM Status Register 3 (SR3)
Kernel Data PAR, Reg. 0-7

17 772 356 — 17 772 340
17772 336 - 17 772 320
17772316 -17 772 300
17772276 — 17 772 260

Kernel Instruction PAR, Reg. 07
Kernel Data PDR, Reg. 0-7
Kernel Instruction PDR, Reg. 0-7
Supervisor Data PAR, Reg. 0-7

17 772 256 — 17 772 240
17772 236 - 17 772 220
17 772 216 — 17 772 200
17 770 372 - 17 770 200

Supervisor Instruction PAR, Reg. 0-7
Supervisor Data PDR, Reg. 0-7
Supervisor Instruction PDR, Reg. 0-7
Map Registers

2.3.1.1 Processor Status Word (PSW) — The format of the processor status word (PSW) register is

shown on Figure 2-2. Table 2-14 lists the functions of the PSW bits.

00
READ/WRITE

17777776

CRNT

MODE

NOT USED

PRIORITY

INST

SUSP
TK-3642

Figure 2-2

PSW Register Format

2-20

Table 2-14

Processor Status Word Register Bit Descriptions

Bit

Description

15:14

Current Mode — These bits specify the current processor mode as follows:
00 — The processor is in kernel mode and all operations are legal.

01 — The processor is in supervisor mode. A HALT instruction will trap to location 4 and the instructions RESET and SET PRIORITY LEVEL (SPL) are
treated as a NO OPERATION (NOP).
10 — An illegal mode. If memory management is enabled, a memory management abort occurs.

11 — The processor is in user mode. A HALT instruction will trap to location 4
and the instructions RESET and SPL are treated as a NOP.
13:12

Previous Mode — Specify the previous processor mode, prior to the last trap,
interrupt or loading of the PSW. The modes are the same as defined for the
current mode (bits 15:14).

11:09

Not used.

CIS Instruction Suspension — This bit is set to 1 when a CIS instruction is entered and cleared when the instruction is completed. If this bit is set when an
interrupt occurs, it indicates that the instruction was not completed and must be
continued upon return from the interrupt. If this bit is set, the T-bit cannot be
set. This prevents looping in trace trap mode.

07:05

Priority — These bits specify the current level of the processor priority. The central processor operates at any of eight levels of priority, 0~7. When the CPU is

operating at level 7, an external device cannot interrupt it with a request for

service. The central processor must be operating at a lower priority than the
priority of the external device’s request in order for the interruption to take effect. The eight processor levels provide an interrupt mask, which can be altered
through use of the set priority level (SPL) instruction. This instruction can be
used only by the kernel mode and allows a kernel mode program to alter the
central processor’s priority without affecting the rest of the processor status
word.
04:00

Condition Codes — The condition codes contain information which occurred as a
result of the previous CPU operation. The bits are defined as follows:
T (04)

Trap — Set to 1 or cleared under program control. When set, a pro-

cessor trap will occur through location 14 on completion of instruction execution and a new processor status word will be loaded. This
bit is useful for debugging programs by providing a method of tracing the execution of programs.

2-21

Table 2-14

Processor Status Word Register
Bit Descriptions (Cont)

Bit

Description

N (03)

Negative — Set to 1 if the result of the last data manipulation was
negative.

Z (02)

Zero — Set to | if the result of the last data manipulation was zero.

V (01)

Overflow — Set if the result of the last data manipulation caused an

overflow.
C (00)

Carry — Set if the last data manipulation produced a carry bit.

2.3.1.2
Program Interrupt Request Register — System software may request an interrupt by setting one
of bits (PIR) 15:09 for PIR7-PIR1 in the program interrupt request (PIRQ) register. The hardware
sets bits 07:05 and 03:01 to the encoded value of the highest PIR bit set. Bits 07:05 allow the program
interrupt active (PIA) field to be moved into the processor status word register and set the processor

priority to the level of the request honored. This disables all requests on the same level or below. Bits
03:01 can be used as an index constant in branching to an interrupt service routine for the appropriate
priority level request.
When a priority interrupt request is granted, the processor traps to location 240. A new PC is taken
from location 240 and a new PSW from location 242. The interrupt service routine must queue requests

within a priority level and clear the PIR bit before the interrupt is dropped.

Figure 2-3 shows the bit assignments of the PIRQ and Table 2-15 lists the functions of the bits.

2.3.1.3 Error Register — This register identifies the source of the abort or trap that used the vector at
location 4. Bits 07:04, bit 02 and bit 00 are cleared when the CPU error register is written; the remaining bits are software transparent and are accessible only when the console has control. Figure 2-4 descriptions are listed in Table 2-16.

15
17777772

PIR7 «—

PIR1
PIRQ LEVEL

PIA

NOT

USED

——

PIA

NOT

USED

NOT

USED
TK:3647

Figure 2-3

PIRQ Register Format

2-22

Table 2-15

Processor Interrupt Request Register

Bit Descriptions

Bit

Description

15:09

PIR7-PIR1 — Seven program interrupt request bits which may be set to request
an interrupt at a given priority level.

Not used.

07:05, 03:01

PIA — Program interrupt active bit, which is the encoded value of the highest
PIR bit set.

Not used.

15
17777766 |

14
|

| *

|«

.DATA | CACHE | BE
TRAN

RSRT

KTE

08
|

DCLO

MEM

HALT | tmouT !

PROC

INTR

INIT

oDD

UNIBUS

ADD

TMOUT

STOV

ERR

* SOFTWARE TRANSPARENT

Bit

ACLO [ ILL.
PE

Figure 2-4

CPU Error Register Format

Table 2-16

Error Register Bit Descriptions

00
READ/WRITE

CIM
PWR
FAIL

Description

Data Transfer — This bit monitors the DATA TRAN line of the processor.
When clear, this bit indicates the processor is initiating a data transfer on the
UNIBUS.

C1 — This bit is set to 1 when the UNIBUS control signal BUS C1 is asserted,

indicating a DATO or DATOB transfer is being performed.
13

Cache Restart — This bit, when set to 1, indicates that the cache has generated

the signal necessary to restart the processor clock.
12

KTE - This bit, when set to 1, indicates that one of the memory management

errors (nonresident, page length or read-only abort) has occurred.

2-23

Table 2-16

Bit

Error Register Bit Descriptions (Cont)

Description

Bus Error — This bit, when set to 1, indicates that the processor has attempted
to access nonexistent memory, odd address during word reference or there was
no response on the UNIBUS within approximately 20 us.
Parity Error — This bit, when set to 1, indicates that the processor has received

a memory parity error.
09

AC LO - This bit, when set to 1, indicates that UNIBUS AC LO is asserted.
This signal is not latched and, therefore, bit 09 is not affected by a processor
INIT.

DC LO - This bit, when set to 1, indicates that UNIBUS DC LO is asserted.
This signal is not latched and, therefore, bit 08 is not affected by a processor
INIT.

Illegal Halt — This bit is set to 1 when a halt instruction is attempted when the
processor is in user or supervisor mode.

Odd Address Error — This bit is set to 1 when the program attempts a word
reference on an odd address.

Memory Time-Out — This bit is set to 1 when the program attempts to read a
word from a nonexistent memory location. This does not include UNIBUS ad-

dresses.

UNIBUS Time-Out — This bit is set to 1 when there is no response on the
UNIBUS within approximately 20 us.

Processor Initialize — This bit monitors the processor initialize signal.

Stack Overflow — This bit is set to 1 when the kernel hardware stack is less than
octal 400.

Interrupt — This bit is set when the PAX interrupt line is asserted.

CIM Power Failure — This bit, when set to 1, indicates that dc power to the
machine has exceeded voltage tolerance limits for a period of 1.5 us or greater.

2-24

2.3.1.4 General Registers — The CPU contains several 16-bit general registers that can be used as accumulators, index registers, autoincrement registers, autodecrement registers or as stack pointers for
temporary storage of data. A few of these registers are used for special purposes. Register 7 (R7) is
used as the program counter (PC) and contains the address of the next instruction to be executed. R6 is
generally used as the processor stack pointer (SP) if the processor is in kernel mode. If the processor is
in supervisor or user mode, R16 or R17 is used as the processor stack pointer, respectively. Table 2-17
lists the general registers and their addresses and functions.
Table 2-17

2.3.2

General Register Addresses

Address

Function

17 177 705 - 17 177 700

R5-R0O, General Purpose Registers

17 777 706
17 777 707
17 777 710
17 777 711

R6, Kernel Mode Stack Pointer
R7, Program Counter
R10, Temporary Storage
R11, Unused

17777 715 =17 777 712

R15-R12, Temporary Storage

17777 716
17 777 717

R16, Supervisor Mode Stack Pointer
R17, User Mode Stack Pointer

Multifunction Module Register

The multifunction module (MFM) contains two serial line units (SLUs) which provide the interface
ports between the serial line devices and the PDP-11/44 processor. The SLU can be connected to a
console terminal, to the TUSS8 tape unit, or to a remote diagnostic facility. The console terminal operates as a standard 1/0 device or as a programmer’s console to access and load registers within the CPU.

2.3.2.1 Console Terminal Receiver Control /Status Register (RCSR) - Figure 2-5 shows the format of
the console terminal receiver control/status register (RCSR) and Table 2-18 lists and describes the
functions of the bits.

17777560

07
R

NOT USED—I

06 05
|R/W

TERM RCVR DONE

TERM RCVR INT ENAB

NOT USED
TK-4370

Figure 2-5

Console Terminal RCSR Format

2-25

Table 2-18

Console Terminal RCSR Bit Descriptions

Bit

Description

15:08

Not used.

Terminal Receiver Done — A read-only bit that is set to 1 during the program

I/O mode when a complete character is contained in the console terminal
RBUF. Cleared when the RBUF is addressed and when an initialize operation
occurs.

Terminal Receiver Interrupt Enable — A read/write bit, set to 1 to allow the
interrupt sequence to be initiated when the RCVR DONE bit is set.

05:00

Not used.

2.3.2.2 Console Terminal, Receiver Data Buffer (RBUF) — Figure 2-6 shows the format of the console
terminal receiver data buffer register and Table 2-19 lists and describes the function of the bits.

15
17777562)

14
|

| R | R

TERM ERROR—J

00
R

)

TERM OR ERROR
TERM FR ERROR
TERM PAR ERROR
NOT USED

TERM RCVR DATA
TK-4371

Figure 2-6

Table 2-19

Console Terminal RBUF Format

Console Terminal RBUF Bit Descriptions

Bit

Description

Terminal Error — A read-only bit that is set to 1 when the TERM OR ERROR

(bit 14), the TERM FR ERROR (bit 13), or the TERM PAR ERROR (bit 12)
is set to 1. Cleared by an initialize operation or by the reception of new and
correct data.

2-26

Table 2-19

Console Terminal RBUF Descriptions (Cont)

Bit

Description

Terminal Overrun Error — A read-only bit that is set to 1 if the character in the

RBUF has not been read before another character is received. Cleared by an
initialize operation or when the RBUF is emptied.
13

Terminal Framing Error — A read-only bit that is set to 1 when the character

read does not include a valid stop bit(s). Cleared when a valid character is received. This bit may indicate an error in transmission or the reception of a
“break” character.
12

Terminal Parity Error — A read-only bit that is set to 1 when the parity of the
data in the RBUF is incorrect relative to the parity mode selected. This indicates an error in transmission. Cleared when the parity of the next character
is validated.

11:08

Not used.

07:00

Terminal Receiver Data — Read-only bits that is the data character that was

read from the terminal.

2.3.2.3 Console Terminal Transmitter Control/Status Register (XCSR) - Figure 2-7 shows the format
of the console terminal transmitter control and status register (XCSR) and Table 2-20 lists the function
of the bits.

17777564

NOT USED

R[RW]

|RW

00
R/W

TERM XMIT RDY
TERM XMIT INT ENAB
CIM REMOT

ENAB CONSOLE

RD BIT ENAB
TERM MAINT

NOT USED

TERM BREAK
TK-4372

Figure 2-7

Console Terminal XCSR Format

2-27

Table 2-20

Console Terminal XCSR Bit Descriptions

Bit

Description

15:08

Not used.

Terminal Transmitter Ready — A read-only bit that is set to 1 when the console
terminal XBUF Tegister is ready to accept a character or when an initialize operation occurs. It initiates the interrupt sequence if the TERM XMIT INT
ENB (bit 06) is set to 1. Cleared when the XBUF receives a character.

Terminal Transmitter Interrupt Enable — A read/write bit that is set to 1, by
the program to enable the interrupt sequence to be initiated if the TERM
XMIT RDY (bit 07) is set to 1. Cleared by program or by the initialize sequence.

Console Interface Remote — A read-only bit that is set to 1 when the CPU is
operating in the remote diagnostic mode.

Enable Console — A read-only bit that is set to 1 by the program to indicate that
the CPU is operating in the console mode.

Remote Diagnostic Bits Enable — A read-only bit set by switch S2 (E79) on the

MFM module. When the switch is on, the status of bits 04 and 05 is entered
into this register and when the switch is off, the bits will be zeros.
02

Terminal Maintenance — A read/write bit which, when set to 1 by the program,

will cause a closed loop test of the console terminal UART. The serial output of
the XBUF will be returned to serial input of the RBUF. The data transfer rate
will be at the baud rate of the transmitter. Cleared by an initialize operation or
by the program.

Terminal Break — A read/write bit that is set to 1 by the program and causes

the transmission of a continuous space character. This will cause a framing error (bit 13) of the RBUF to be set. Cleared by the program or by an initialize
sequence. Can be disabled permanently by removing the jumper lead W5 on the
MFM module.

2.3.2.4

Console Terminal Transmitter Buffer Register (XBUF) — Figure 2-8 shows the format of the

console terminal transmitter buffer register (XBUF) and Table 2-21 lists the function of the bits.

08 07

17777566

00
w

NOT USED

TERM XMIT DATA
TK-4373

Figure 2-8

Console Terminal XBUF Format

2-28

Table 2-21

Console Terminal (XBUF) Bit Descriptions

Bit

Description

15:08

Not used.

07:00

Terminal Transmitter Data — These are write-only bits which form the data

character to be transferred to the console terminal.

2.3.2.5

TUS8 Receiver Control/Status Register (RCSR) - Figure 2-9 shows the format of the TUS58
receiver control/status register (RCSR) and Table 2-22 lists the function of the bits. The typical addresses assigned to the TUS8 registers are from 17776500 to 17776506.

177 XXXX0
.

NOT USEDJ

|R/W

TU5B8 RCVR DONE

TUG8 RCVR INT ENAB
NOT USED
TK-4374

Figure 2-9

Table 2-22

TUS58 RCSR Format

TUS8 RCSR Bit Descriptions

Bit

Description

15:08

Not used.

TUS58 Receiver Done — A read-only bit that is set to 1 during the program /0

mode only when a complete character is contained in the TU58 RBUF. Cleared
when the TUS58 RBUF is addressed or when an initialize operation occurs. In-

itiates the interrupt sequence when the TU58 RCVR INT ENAB bit (06) is set
to 1.

TU58 RCVR Interrupt Enable — A read/write bit which is set to 1 by the pro-

gram to allow the interrupt sequence to be initiated by the TU58 RCVR

DONE bit (07).
05:00

Not used.

2-29

2.3.2.6 TUS58 Receiver Buffer Register (RBUF) — Figure 2-10 shows the format of the TUS58 receiver
buffer register (RBUF) and Table 2-23 lists the function of the bits.

o2l

08 07

R | R

| R

TUS8 ERROR

—

NOT

TU58 OR ERROR

USED

)

TU58 RCVR DATA

TUB8 FR ERROR
TUS8 P ERROR
TK-4375

Figure 2-10

Table 2-23

TUS8 RBUF Format

TUS8 RBUF Bit Descriptions

Bit

Description

TUS8 Error — A read-only bit that is set to 1 when the TU58 OR ERROR (bit
14), TU58 FR ERROR (bit 13), or the TU58 PAR ERROR (bit 12) is set to 1.
Cleared by an initialize operation or by the reception of new and correct data.

TUS8 Overrun Error — A read-only bit that is set to 1 if the character in the
RBUF has not been read before another character is received. Cleared by an
initialize operation or when the RBUF is emptied.

TUS8 Framing Error — A read-only bit that is set to 1 when the character read
in the RBUF does not have a valid stop bit(s). Cleared when a valid character is
received. This bit may indicate an error in transmission or the reception of a
“break” character.

TUS8 Parity Error — A read-only bit that is set to 1 when the parity of the character read in the RBUF is incorrect relative to the parity mode selected.
Cleared when the parity of the next character is validated.

11:08

Not used.

07:00

TUS58 Received Data — These are read-only bits that form the data character
received from the TUSS.

2.3.2.7 TUS5S8 Transmitter Control/Status Register (XCSR) - Figure 2-11 shows the format of the
TUS8 transmitter control/status register (XCSR) and Table 2-24 lists the functions of the bits.

2-30

177XXXX4

NOT USED—]/

|R/W

R/W

TUB8 XMIT RDY
TUB8 XMIT INT ENAB
NOT USED
TUS8 MAINT
NOT USED

TU58 BREAK
TK-4376

Figure 2-11

Table 2-24

TUS58 XCSR Format

TU58 XCSR Bit Descriptions

Bit

Description

15:08

Not used.

TUS8 Transmitter Ready — A read-only bit that is set to 1 when the TU58
XBUF is ready to accept a character or when an initialize operation occurs. Setting the bit initiates an interrupt sequence if the TU58 XMIT ENAB (bit 06) is
set to 1. Cleared when a character is written into the XBUF.

TUS58 Transmitter Interrupt Enable — A read/write bit that is set to 1 by the
program. Enables the interrupt sequence to be initiated if the TUS8 XMIT
RDY (bit 07) is set to 1. Cleared by the program or by the initialize sequence.

05:03

TUS58 Maintenance — A read/write bit that when set to 1 by the program will
cause a closed loop test of the TUS8 UART. The serial output of the transmitter will be returned to the serial input of the receiver. The data transfer rate
will be the baud rate of the transmitter. Cleared by the program or by an initialize operation.

Not used.

TUS8 Break — A read/write bit that is set to 1 by the program and that causes a
space character to be continuously transmitted to the TUS8. Cleared by the
program or by an initialize sequence. The break function can be permanently
disabled by removing jumper lead W10 on the MFM module.

2-31

2.3.2.8 TUSS Transmitter Data Buffer (XBUF) Register — Figure 2-12 shows the format of the TUS8
transmitter buffer register (XBUF) and Table 2-25 lists the functions of the bits.
2.3.2.9 Signal Register — The signal register provides information about the operational status of the
MFM module and CPU. Figure 2-13 shows the format of the signal register and Table 2-26 lists the
function of the bits.

08 07

177XXXX6

Figure 2-12

Table 2-25

)

TU58 XMIT DATA

NOT USED

TUS58 XBUF Format

TUS8 XBUF Bit Descriptions

Bit

Description

15:08

Not used.

07:00

TUS58 Transmitter Data — These are write-only bits that form the data character to be transferred to the TUS8.

ACCESSED

1514

0706

0403

BY CONSOLE

READ ONLY

COMMAND

E/M<SP>11<CR>

CIM

MFM CLK|XFER DONE L

HALT
H

[INH
H

RUNH

SACKH

CIM
REMOTE H
TK-3659

Figure 2-13

Signal Register Format

2-32

Table 2-26

Signal Register Bit Descriptions

Bit

Description

15:06

Not used.

Run — Set to 1 to indicate that the processor is executing instructions.

Console Interface Module Halt — Set to 1 to indicate that the toggle switch on

the control panel of the PDP-11/44 is in the HALT position.
03

Selection Acknowledge — Set to 1 to indicate that a device has acknowledged

the bus grant.
02

Multifunction Module Clock Inhibit — Set to 1 when the MFM is inhibiting the

operation of the CPU clock..
01

Console Interface Module Remote — Set to 1 when the CPU is operating in the
remote mode.

Transfer Done — Not used.

2.3.2.10 Line Time Clock Control/Status Register (LKS) — Figure 2-14 shows the format of the Line
Time Clock Control Status Register (LKS) and Table 2-27 lists the functions of the bits.

17777546

NOT USED——I

|R/W

LTC INT MON
LTC ENAB

NOT USED
TK-4378

Figure 2-14

Line Time Clock (TCSR) Format

2-33

Table 2-27

Bit

Description

15:08

Not used.

Line Time Clock LKS, Bit Descriptions

Line Time Clock Monitor — A read-only bit set to 1 for each cycle of the ac

voltage and cleared by the program. Provides an interrupt request at an interval
of 16.66 ms for the 60 Hz version and 20 ms for the 50 Hz version. Also sct
during the initialize sequence.

Line Time Clock Interrupt Enable — A read-write bit set to 1 by the program to

allow the interrupt sequence to be initiated when the LTC MON (bit 07) is set.
Not used.

05:00

2.3.3

Cache Memory 1/0, Page Registers

The cache memory module (KK 11-B) contains several registers that are used to store data information,
error indications, and control and status information.

2.3.3.1 Cache Memory Data Register (CDR) - The cache memory data register (CDR) is loaded from
the 16-bit data array section of the cache RAM when a read-access occurs to main memory. Figure 215 shows the CDR format and Table 2-28 lists the functions of the bits.

00
READ ONLY

17777754

—

CACHE DATA BITS 15:00
TK-3649

Figure 2-15

Table 2-28

Cache CDR Format

Cache CDR Bit Descriptions

Bit

Description

15:00

These bits are read-only and are loaded from the 16-bit data array section of the
cache RAM on every read-access to main memory, except the top 256K bytes.
This register can be used with the hit-on-destination-only bit to aid the cache
diagnostics in identifying failures in the data section of the cache array.

2-34

2.3.3.2 Cache Hit Register (CHR) — The cache hit register (CHR) is a dual-purpose register
used as
an address match register when written and as a tag address /hit register when read. Figure 2-16
shows
the CHR format and Table 2-29 lists the functions of the bits.

17777752

WRITE ONLY

ADDRESS MATCH

BITS 15:00

17777752

READ ONLY

—

TAG ADDRESS

—~—~

HIT REGISTER

TK-3646

Figure 2-16
Table 2-29

Cache CHR Format

Cache CHR Bit Descriptions

Bit

Description

15:00

Address Match Bits 15:00 — These write-only bits correspond to bits 15:00 of
the address match register. Bits 21:16 of the address match register are contain-

ed in the cache maintenance register. When bits 21:00 of the address match
register are the same as memory address lines 21:00, bit 3 of the CMR s set, a
sync pulse is provided to a user-accessible test point and the address match
LED is lite. When bit 4 of the CMR is set, the processor clock is stopped. When

bit 2 of the CMR is set, the processor is halted.
15:07

Tag Address — These read-only bits contain the nine tag store memory bits of

the last main memory access. When used in conjunction with bits 01 and 00 of
the cache maintenance register, the tag address bits will allow cache diagnostics

to read the tag field of any location in the array.
06

Not used.

05:00

Hit Register — These read-only bits indicate the number of read and write cache
hits on the last processor accesses to non-1/O page memory. These bits flow

from the LSB to MSB of the field with a 1 indicating a hit and a 0 indicating a

miss.

2.3.3.3

Cache Maintenance Register (CMR) - The cache maintenance register (CMR) is a dual-purpose register. The high byte is used as an address match register when written and contains maintenance bits when read. The lower byte contains read /write maintenance bits. Figure 2-17 shows the format of the CMR and Table 2-30 lists the function of the bits.

2-35

17777750

WRITE—ONLY

ADDRESS MATCH

BITS 21:16

17777750

READ—ONLY

CM1

CM3

CcM2

HBP

VLD

L.BP

HIT

17777750

READ/WRITE

ESA

EHA

TDAR

HODO

TK-3648

Figure 2-17

Table 2-30

Cache CMR Format

Cache CMR Bit Descriptions

Bit

Description

15:10

Address Match Bits 21:16 — These write-only bits correspond to bits 21:16 of
the address match register. Bits 15:00 of the address match register are contained in the cache hit register. When bits 21:00 of the address match register are
the same as memory address lines 21:00, a sync pulse is provided to a user-accessible test point.

15:13

Compare 3:1 — These read-only bits represent the value of the compare lines of

the cache hit detect logic. when these bits are set, it indicates that the 9-bit tag
field currently being read matches the upper 9 bits of the PAX address (bits
21:13).
Valid — This read-only bit, when set, indicates that the word currently being
read from cache is a valid copy of a backing store location.

2-36

Table 2-30

Cache CMR Bit Descriptions (Cont)

Bit

Description

11:09

High Parity, Low Parity, Tag Parity — These read-only bits indicate the parity
of the high byte of the data field, low byte of the data field, and the tag field,

respectively.

Hit — This read-only bit, when set, indicates that all the conditions necessary for
a processor-read hit have been met.

Enable Stop Action — This read/write bit, when set, will cause the processor
clock to stop when a cache parity error or address match condition is detected.

Address Matched — This read/write bit is set when the 22-bit address match
register is equal to the 22-bit PAX address.

Enable Halt Action — This read/write bit, when set, will cause a processor halt

upon detection of a cache parity error or address match condition.
01

Hit on Destination Only — This read/write bit, when set, causes the cache to be
enabled only during the destination memory access portion of an instruction.
Read hits and updates will occur only during the final destination access.

Tag Data from Address Match Register — This read /write bit, when set, en-

ables the tag field of the cache to be written with data from bits 08:00 of the
address match register. When this bit is set, all cache writes will cause the valid
bit to be cleared in that location.

2.3.3.4
Cache Control/Status Register (CCSR) - Figure 2-18 shows the format of the cache (CCSR)
and Table 2-31 lists the functions of the bits.

17777746

13
R

NOT

USED

12
|

VSIU

RW|RW|

[Rw|R/wW

WWPT

VCIP

UCB

WWP

PEA

04
|

NOT

R/W|R/W

00
R/W

FM LO

USED ey

NOT USED

DC P!
NOT USED
TK-3651

Figure 2-18

Cache CCSR Format

2-37

Table 2-31

Cache CCSR Bit Descriptions

Bit

Description

15:14

Not used.

Valid Store in Use — This read-only bit controls which set of valid store bits is
currently being used to determine the validity of the contents of the tag store
memory. When this bit is set to 1, valid bit B is in use; when clear, bit A is in
use. This bit is complemented each time the cache is flushed.

Valid Clear in Progress — This read-only bit, when set, indicates that the cache
is currently in the process of clearing a valid store set. A cache clear cycle is
initiated on powerup and when the flush cache bit is set.

Not used.

Write Wrong Parity Tag — This read/write bit, when set, causes tag parity bits
to be written with wrong parity on processor read misses and write hits. This
will cause a parity error to occur on the next access to that location. This feature is used by the cache diagnostic programs.

Unconditional Cache Bypass — This read/write bit, when set, will force all
memory references by the processor to go to main memory. Read or write hits
will result in invalidation of those locations in cache, and misses will not change
the contents.

Flush Cache — This writc-only bit, when set, will cause the entire contents of the
cache to be declared invalid.

Parity Error Abort — This rcad/write bit controls the response of cache to a
parity error. When this bit is set, a cache parity error will cause a force miss
and an abort to occur. When cleared, this bit inhibits the abort and enables an
interrupt to parity error vector 114. All cache parity errors result in force
misses.

Write Wrong Parity Data — This read /write bit, when set, causes high and low
parity bytes to be written with wrong parity on all updates (processor read
misses and write hits). This will cause a cache parity error to occur on the next
access to that location. This feature is used in the cache diagnostic programs.

05-04

Not used.

Force Miss High - This read/write bit, when set, causes a forced miss on CPU
reads where bit 12 of the location’s address is a 1. This bit can also be set by a
toggle switch (S1) on the cache board. When switch S1 is returned to the cacheon position, bit 03 remains set until cleared by the program or by an initialization.

2-38

Table 2-31

Cache CCSR Bit Descriptions (Cont)

Bit

Description

Force Miss Low — This read /write bit, when set, causes a forced miss on CPU
read operations when bit 12 of the location’s address is a 0. This bit can also be
set by a toggle switch (S2) on the cache board. When switch S2 is returned to

the cache-on position, bit 02 remains set until cleared by the program or by an
initialization. Setting both bits 03 and 02 will cause all CPU read operations to
be misses thereby effectively disabling the cache.

Not used.

Disable Cache Parity Interrupt — This read/write bit, when set, overrides the
cleared condition of the parity error abort bit (bit 07), thereby disabling the
interrupt to location 114. The following shows the relationship between bits 00

and 07 and the effect on cache parity errors.

Bit

Result

Interrupt to location 114 and force miss

Force miss only

0/1

Abort and force miss

2.3.3.5
Cache Error Register (CME) - Figure 2-19 shows the format of the cache CME register and
Table 2-32 lists the functions of the bits.

17777744

READ/WRITE CLEAR

CM PE

NOT USED

PE HI

TPE

NOT USED

PE LO

TK-3650

Figure 2-19

Cache CME Format

2-39

Table 2-32

Cache CME Bit Descriptions

)

Bit

Description

Cache Memory Parity Error — This bit is set if a cache parity error is detected
while the cache parity abort bit (control register bit 07) is set or if a memory
parity error occurs. If this bit is set, the cache will force a miss. This bit is
cleared by any write to the cache memory error register or by a console INIT.

14:08

Not used.

Parity Error High Byte — Set to | when a parity error occurs in the high byte of
data and the PEA (bit 07) of the CSSR is set to 1. If the cycle is not aborted
(PEA = 0), bit 06:05 of the CME will also be set by this error. All parity bits
are cleared by a write operation to the CME or by a console INIT.

Parity Error Low Byte — Set to 1 when a parity error occurs in the low byte of
the cache data, and the PEA (bit 07) of the CCSR is set to 1. If the cycle is not
aborted (PEA = 0), bits 07 and 05 will also be set to 1 by this error.

Tag Parity Error — Set to 1 when a parity error occurs in the tag address field of
the CHR, and the PEA (bit 07) of the CCSR is set to 1. If the cycle is not

aborted (PEA = 0), bits 06 and 07 of the CME will also be set to 1. All parity
bits are cleared by a write operation to the CME or by a console INIT.
Not used.

04:00

2.3.4

Memory Management Registers

The 16-bit virtual address is translated to a 22-bit physical address by the memory management func-

tion. Four status registers, 48-page address registers (PAR), and 48-page descriptor registers (PDR) are
associated with the memory management.
2.3.4.1

Status Register 0 (SR0) - Mcmory management status register 0 (SRO) contains error flags,

the page number whose reference caused the abort and various status flags. The format of SRO is
shown in Figure 2-20 and bit descriptions are listed in Table 2-33.

15
17777572 | pyw

NON-—
RSDT

ABORT

R/W|R/W

NOT
READ—
ONLY ~ USED

page

ABORT

LGTH
ABORT

08
R/W

MAINT
MODE

06
R

PAGE

MODE

R/W

ID
SPACE

o gg

ENBL
RELOC

NO :

NOT USED

TK-3644

Figure 2-20

Memory Management SRO Format

2-40

Table 2-33

SRO Bit Descriptions

Bit

Description

15:13

Error Flags — These error bits are prioritized; i.e., flags to the right are less significant and are ignored if a flag to the left is present. For example, a nonresident fault service routine would ignore page length and access control
faults.

Nonresident Abort — This bit is set to 1 when an attempt to access a page with
an access control field (ACF) key equal to 0. It is also set if there is an attempt
to use memory relocation with a processor mode of 2.

Page Length Abort — This bit is set to 1 if there is an attempt to access a location in a page with a block number (virtual address bits 12:06) that is outside
the area authorized by the page length field (PLF) of the page descriptor register (PDR) for that page. It is also set if there is an attempt to use memory relocation with a processor mode of 2. Bits 15 and 14 can be set simultaneously by
the same access attempt.

Read-Only Abort — This bit is set if there is an attempt to write in a read-only
page. Read-only pages have an access key of 1.

12:09

Not used.

Maintenance/Destination Mode — This bit, when set, specifies that only desti-

nation mode references will be relocated using memory management. This bit is

used for diagnostic purposes only.
07

Not used.

06:05

Page Mode — These bits indicate the processor mode (kernel/supervisor/user)
associated with the page causing the abort; kernel = 00, supervisor = 01, user
= 11, illegal mode = 10. If an illegal mode is specified, bits 15 and 14 will be

set.

I/D SPACE - This bit indicates the type of address space (I or D) the memory
management was using when the fault occurred; 0 = I space, 1 = D space.

03:01

Page Number — These bits contain the page number of the reference causing a
memory management fault.

Enable Relocation — When this bit is set, all addresses are relocated. When this
bit is clear, the memory management facility is inoperative and addresses are
not relocated or protected.

2-41

2.3.4.2 Status Register SR1 — The format of memory management status register 1 (SR1) is shown in
Figure 2-21. SR1 records any autoincrement/decrement of the general purpose register, including explicit references through the PC. SR1 is cleared at the beginning of the fetch cycles for each instruction. Whenever a general purpose register is either autoincremented or autodecremented, the register
number and the amount in 2’s complement notation by which the register was modified are written into
SR1. A single operand instruction will only set the lower byte with the source register change and the
upper byte with the destination register change. Table 2-34 describes each of the bits in the SR1.
2.3.4.3

Status Register SR2 — The status register SR2 is loaded with the value of the program counter

at the beginning of the fetch cycle of each instruction.

At the beginning of an interrupt, SR2 contains the address trap vector, the T bit, parity traps, odd
address, parity and time-out aborts. Figure 2-22 shows the format of SR2 and Table 2-35 lists the function of the bits.

2.3.4.4

Status Register SR3 - Figure 2-23 shows the format of SR3 and Table 2-36 describes the bits.

READ—ONLY

17777574
INC/DECEG

INC/DEC

FIRST R

TK-3645

Figure 2-21

Memory Management SR1 Format

Table 2-34

Bit

15:11

SR1 Bit Descriptions

Description

Increment/Decrement Second Register — The 2’s complement value of the in-

crementing or decrementing of the second general register.

10:08

Second Register Number — The octal value of the second general register num-

07:03

Increment/Decrement First Register — The 2’s complement value that is a result of the incrementing or decrementing of the first general register.

02:00

First Register Number — The octal value of the first general register.

ber (octal O for register 0).

2-42

READ ONLY

17777576
L

—~—

16 BIT VIRTUAL ADDRESS
TK-3652

Figure 2-22

Memory Management SR2 Format

Table 2-35

SR2 Bit Description

Description

Bit

Virtual Address — Read-only bits that are the virtual address at the beginning of

15:00

the fetch cycle of each instruction.

R/WIR/W|R/W|R/W|R/W|R/W

17772516

_J [

ENB UNIBUS|ENB CALL|

NOT USED

MAP

SUPER

ENB 22-BIT

KERNEL

USER

MAPPING
TK-3653

Figure 2-23

Memory Management SR3 Format

Table 2-36

SR3 Bit Descriptions

Bit

Description

15:06

Not used.

Enable UNIBUS Map — Set to 1 by program control to enable the UNIBUS
map which converts 18-bit UNIBUS addresses to 22-bit memory addresses.

Enable 22-Bit Mapping — Set to | by program control to enable 22-bit mapping
when the ENBL RELOC (bit 01) of SRO is seto 1. When cleared to 0, 18-bit
mapping is enabled.

2-43

Table 2-36

Bit

SR3 Bit Descriptions (Cont)

Description

Enable Call Supervisor — Set to

by program to enable the CALL TO

SUPERVISOR MODE instruction to be performed.
02

Kernel — Set to 1 by program control to enable kernel mode D space.

Supervisor — Set to 1 by program control to enable supervisor mode D space.

User — Set to 1 by program control to enable data space in the user mode. When

data space is disabled, all references use the instruction (I) space registers.
When D space is enabled, either the I space or the D space registers are used.

2.3.4.5
Page Address Registers (PAR) — The page address registers (PAR) contain the 16-bit page
address field that specifies the base address of the page as a block number in physical memory. Figure
2-24 shows the format of a PAR and Table 2-37 describes the bits.
2.3.4.6

Page Descriptor Register (PDR) ~ The page descriptor registers (PDRs) contain information

relative to page expansion, page length and access control. There are six sets of eight PDRs which are

allocated in the same manner as the PARs. The addresses of these registers are listed in Table 2-38.
The format of the PDR is shown in Figure 2-25 and bit descriptions are listed in Table 2-39.

ADDRESS

(TABLE 2-36)

PAGE ADDRESS FIELD

Figure 2-24

Memory Management PAR Format

Table 2-37

Bit

15:00

PAR Bit Description

Description

Page Address Field — Read/write bits that are the page address field. There are

six sets of eight PARs, one set each for kernel data space, kernel instruction

space, supervisor data space, supervisor instruction space, user data space and
user instruction space. The addresses of these registers are listed in Table 2-38.

2-44

Table 2-38

PAR/PDR UNIBUS Addresses

D Space

I Space

PDR

PAR

No.

PAR

PDR

0
1
2
3
4
5
6
7

17 772 360
17 772 362
17 772 364
17772 366
17772 370
17772 372
17772 374
17772 376

17 772 320
17772 322
17772 324
17 772 326
17 772 330
17 772 332
17772 334
17 772 336

0
1
2
3
4
5
6
7

17 772 260
17772 262
17 772 264
17 772 266
17772 270
17772 272
17772 274
17772 276

17 772 220
17 772 222
17772 224
17772 226
17 772 230
17 772 232
17 772 234
17 772 236

0
1
2
3
4
5
6
7

17 772 660
17 772 662
17 772 664
17 772 666
17772 670
17772 672
17772 674
17772 676

17 772 620
17 772 622
17 772 624
17 772 626
17 772 630
17 772 632
17 772 634
17 772 636

Kernel

0
1
2
3
4
5
6
7

17 772 340
17 772 342
17 772 344
17 772 346
17 772 350
17772 352
17 772 354
17772 356

17 772 300
17 772 302
17 772 304
17 772 306
17772 310
17772312
17772 314
17772 316
Supervisor

0
1
2
3
4
5
6
7

17 772 240
17 772 242
17 772 244
17 772 246
17772 250
17 772 252
17 772 254
17 772 256

17 772 200
17772 202
17 772 204
17 772 206
17772 210
17772212
17772214
17772216
User

0
1
2
3
4
5
6
7

17 772 640
17 772 642
17 772 644
17 772 646
17 772 650
17772 652
17772 654
17 772 656

17 772 600
17 772 602
17 772 604
17 772 606
17772610
17772612
17772 614
17772616

ADCRESS

(TABLE 2—36) |R/W

——

R/W|

R/W
\

CACHE

wRITTENYSED

BYPASS

INTO

R/W

——
ACC

NOT

PAGE LNGTH

gxp
pir

CONT - NOT

ELD usep
TK-3654

Figure 2-25

Memory Management PDR Format

2-45

Table 2-39

Bit

PDR Bit Descriptions

Description

Cache Bypass — When set to 1 by the program, this bit will cause all references
to this page to bypass the cache memory and directly access the main memory.

14:08

Page Length Field — Specifies the octal number of 32-word blocks in the current page. The block number of the virtual address is compared to the page

length field to detect length errors. An error occurs when expanding upwards if
the block number is greater than the page length field, and when expanding
downwards if the block number is less than the page length field.
07

Not used.

Page Written Into — This bit is set to 1 to indicate to the program that the page
being accessed was modified since the PAR or PDR was loaded. This bit is used
in applications that involve disk swapping and memory overlays. It determines

which pages have been modified and must be saved in their new form, and

which pages have not been modified and can be overlaid and not saved.
05:04

Not used.

Expansion Direction — Specifies the direction in which a page is authorized to
expand. When cleared to 0, the page expands upward from relative 0 by adding

blocks with higher memory addresses. When set to 1, the page expands downward from block number 177g or 127¢ by adding blocks with lower addresses.
Upward expansion is usually used for program space while downward expansion
is used for stack space.
02:01

Access Control Field — A two-bit field which defines the access rights for the

Bit

Function

—_—_—0

—_0
— O

addressed page as follows:

Nonresident — abort all accesses

Read-only — abort all attempts to write
Unused — abort all accesses
Read/write — read or write allowed, no trap
or abort occurs

Not used.

2-46

CHAPTER 3

CPU CONFIGURATION

The BA11-AA, -AB mounting box contains a 6-row, 14-column CPU backplane which is dedicated to
the PDP-11/44 system modules. Space is provided within the mounting box to allow the installation of
additional backplanes.

Some of the installed system modules contain switches and jumper leads which must be set or con-

figured for particular system applications.

3.1

PROCESSOR BACKPLANE ASSIGNMENTS

Figure 3-1 shows the location of the modules within the system backplane. Row A is positioned toward
the rear of the mounting box where the power supply is mounted. The asterisked (*) modules are optional and are not supplied with the basic system. Table 3-1 lists and describes the standard modules
supplied with the system, and Table 3-2 lists the modules that are available as options.
ROWS

SLOTS

w7000 (kD11-Z/CIM)

(KE44—A)

*M7091

*M7092

(KE44—A)

*M7093

(FP11—F)

M7094

(KD11—Z/DATA PATH)

M7095

(KD11-Z/CONTROL)

M7096

(KD11-Z/MFM)

M7097

(CACHE)

M7098

(KD11-Z/UBI)

FRONT

(MS11-M)

M8722

*M8722

(MS11-M)

*M8722

(MS11-M)

*M8722

(MS11—-M) -

*SPC

14 [ M9302, *M9202, *BC11-A
*MODULE OPTIONS AVAILABLE (TABLE 3-2)
NOTES:

1.AG727,G7270 CARD IS REQUIRED IN ROW D OF ANY UNUSED SPC SLOT TO
PROVIDE BUS GRANT CONTINUITY.

2. A G7273 CARD IS REQUIRED IN ROW C AND D OR ANY UNUSED SPC SLOT TO
PROVIDE BUS GRANT CONTINUITY.

3. MODULES ARE INSERTED WITH COMPONENT SIDE TOWARD RIGHT SIDE OF
BACKPLANE.

TK-4380

Figure 3-1

Backplane Module Locations
3-1

Table 3-1

Standard CPU Backplane Modules

Function

Description

CPU Modules
KD11-Z

M7090 — Console Interface Module (CIM)
M7094 — Data Path Module
M7095 - Control Module
M7096 — Multifunction Module (MFM)
M7097 — Cache Memory Module
M7098 — UNIBUS Interface Module (UBI)

Memory
MS11-MB option

M8722 - 256 KB ECC MOS Memory

UNIBUS

M9302 — Bus Terminator Module

Table 3-2

Optional CPU Backplane Modules

Function

Description

Commercial Instruction

M7091 — Control Module
M7092 — Data Path Module

Set Processor

KE44-A

Floating-Point Processor
FP11-F

M7093 — Floating-Point Processor
Module

Memory Expansion

MS11-MC

Two M8722 Modules — a total of

MS11-MD

of ECC MOS memory
Three M8722 Modules — a total of 768 KB

512 KB

ECC MOS memory
UNIBUS Cable Assembly

BC11-A - connects the UNIBUS of the CPU backplane
to a remote backplane

Bus Grant Continuity

G727, G7270, G7273 modules — inserted into unused slots
to continue bus grant continuity

3-2

3.1.1
Backplane Assembly Pin Designations
The system backplane assembly consists of connector blocks mounted to a metal frame. The top of the
backplane contains slots into which the module contacts are inserted. The bottom of the backplane provides the wirewrap pins. Figure 3-2 shows the wiring side of the system backplane that contains 14 slots
(columns) and 6 rows (A—F). With the mounting box tilted to its servicing position, row F will be located at the top of the assembly and slot 1 (column) will be located at the right side when facing the
wirewrap pins. Each slot has 36 pins associated with the slot connectors and a pin is identified by the
row, slot, pin designation, and side of the pin row where it is located as shown.

Table 3-3 lists the voltages and signals supplied by connector P1. Table 3-4 lists the voltages distributed
to the connector pins of the backplane and Table 3-5 lists the ground lead distribution.

PIN SIDE

SYSTEM BACKPLANE

PIN SIDE
SLOT

14 -

I
|

PR A

| {

|0
4w
|0
[I—}———M

¢l { |

[| }

.dlooooooooool
‘1

1|‘

L[]

[]

|||

I
g

0t—-E

loe—+--0

d-—c

} D——{-——B
LI

PIN LOCATION

—_l'_J

BL —

{

1l|

bf—-s

———

I |

T ——

D !

1i —

2 4 6

ROW

T—

| D——l——V

| 0

el
|

ROW <A—F)J
(51"9:4)

CONNECTOR P1

+5V

FLEXPRINT CABLE

fi:zERCC))CV (10R2)
PIN DESIGNATION
A-V

{G,1,0,Q,W.X,Y,Z,OMITTED}

GND
FLEXPRINT CABLE

POWER

FLEXPRINT
CABLE
TK 4381

Figure 3-2

Backplane Assembly, Pin Designations

3-3

Table 3-3

CPU Backplane Connector P1, Signals and Voltages

Function

1-10
11-16
17,18
19
20
21
22
23
24
25,27
26, 28

+5VB
+12 VB
—12 VB
LTC
BUS ACLOL
BOOT ENAB L
BUS DCLO L
GND SENSE
+5 SENSE
—15V
+15V

Table 3-4

CPU Backplane Voltage Distribution

Voltage

Connector Pin

Voltage

Connector Pin

+12

AO1R1

BO1B1, BO9B1 ~ BO12B1

AO9R1 - A12R1

B09D1 — B012D1

+12 VB

J1-11 to J1-15

+5 VB

J1-1-J1-10

+15

BO1C2
Co6U1, C12U1 - C14U1
J1-26-J1-28

—12

AO01S1, A09S1 - A12S1

—12 VB

J1-17,J1-18

AO01A2 - AO14A2

—15V

BOITI

+5-1

AO01V1 - AO8VI

C12B2
- C14B2

BO1A2 — B14A2

D12B2
- D14B2

CO01A2 - C14A2

E12B2
- E14B2

C01V1 - CO8V1

F12B2
— F14B2

J2-1, J1-24

J1-25, J1-27

- D14A2
DO1A2
DO1VI1, D02Vl

EO1A2
- E14A2
FO1A2
- F14A2
FO1V1 - FO8V1

Table 3-5

CPU Backplane Ground Distribution

Ground

Connector Pin

Ground

Connector Pin

GND 01

A01C2, AOIT1

GND 08

A08C2, AO8T1

B0O1C1, BO1T2
C01C2, CO1T1
D01C2, DO1T1
EO1C2, EOIT1
FO01C2, FO1T1
J00123

B08C2, BO8T1
C08C2, CO8T1
D08C2, DO8T1
E08C2, EO8T1
FO8C2, FO8T1
GND 09

A09C2, A09T1

GND 02

A02C2, A02T1
B02C2, B02T1
C02C2, C02T1
E02C2, E02T1
F02C2, FO2T1

B09C2, B09T1
C09C2, CO9T1
D09C2, D0O9T1
E09C2, EO9T1
F09C2, FO9T1

GND 03

A03C2, A03T1
B03C2, BO3T1
C03C2, C03T1
D03C2, DO3T1
E03C2, EO3T1
FO3C2, FO3T1

GND 10

A10C2, A10T1
B10C2, B10T1
C10C2, C10T1
D10C2, D10T1
E10C2, E10T1
F10C2, F10T1

GND 04

A04C2, A04T1
B04C2, B04T1
C04C2, C04T1
D04C2, D04T1
E04C2, E04T1
F04C2, F04T1

GND 11

Al1C2, A11T1
B11C2,B11T1
C11C2,C11T1
D11C2,DI11T1
E11C2, E11TI1
F11C2,F11T1

GND 05

A05C2, AOST1
B05C2, BO5T1
C05C2, CO5T1
D05C2, DO5T1
E05C2, EO5T1
FO5C2, FOST1

GND 12

A12C2, A12T1
B12C2, B12T1
C12C2, B12T1
D12C2, D12T1
E12C2, E12T1
F12C2, F12T1

GND 06

A06C2, AO6T1
B06C2, BO6T1
C06C2, C06T1
D06C2, D06T1
E06C2, E06T1
F06C2, FO6T1

GND 13

Al13C2, A13T1
B13C2,B13T1
C13C2, C13T1
D13C2, D13T1
E13A2, E13C2, E13T1
F13C2, F13T1, F13J2

GND 07

A07C2, A07T1

GND 14

Al14B2, A14C2, A14N1, A14P1,
Al14R1, A14S1, A14T1, A14V1
B14B2, B14C2, B14D1, B14E]1,

B07C2, BO7TI
C07C2, CO7T1
D07C2, DO7TI
E07C2, EO7T1
F07C2, FO7T1

B14T1, B14V2

F14C2, F14T1, F14J2

3-5

3.1.2

Module Contact Designations
Figure 3-3 shows the contact designations for a hex-height module. The contact designations for single-,
double-, and quad-height modules will be similar starting with row A and proceeding to the maximum
number of rows. When components are mounted on the module, they will be located on side 1.
3.1.3 SPC Module Installation
Slot 13, rows A through F, and slot 14, rows C through F of the system backplane, are allocated to the
installation of small peripheral control (SPC) modules. The SPC modules provide control for the transfer of data between the CPU and peripheral devices. Slot 13 can contain a hex-height SPC module and
slot 14 can contain a quad-height module. If no module is installed in an SPC slot, a G727 module must
be inserted in row D to maintain the bus grant continuity of the backplane.

Some SPC modules allow block data transfers to or from a device without processor intervention. These
modules use a nonprocessor grant (NPGQG) line of the UNIBUS to initiate the data transfers. The NPG
line continuity is maintained by jumper wires wrapped to pins on the backplane.
When a module with NPG capability is installed in an SPC location, the jumper lead between pins Al
and B1 of row C must be removed. Figure 3-4 shows the location of the jumper wires on the backplane.

NOTE

When the NPG modaule is removed or when a module
without the NPG capability is installed, the jumper
lead must be connected to maintain the signal conti-

nuity.

Table 3-6 identifies the signals on the connector pins of row C through row D of the SPC locations. The
XX designation in the “Pin” column of the table is slot 13 or 14 unless otherwise indicated.

18 CONTACTS

ON EACH SIDE

’[
:L,

v
u
T

S
R

NOTES:

1. SIDE 1 IS COMPONENT SIDE

HEX MODULE

SIDE 1

CONTAINS

COMPONENTS

N
M

2. EACH SIDE CONTAINS

18 CONTACTS THAT ARE DESIGNATED

L
K

A COMPLETE MODULE CONTACT

H
F

DESIGNATION CONTAINS A

CONNECTOR LETTER PREFIX,

CONTACT LETTER, AND SIDE

SUFFIX NUMBER. FOR EXAMPLE: AD2

C
B
A

TK-4382

Figure 3-3

Module Contact Designations

BACKPLANE SLOT

SLOT

—

_*& | _

ul—1a

MMM

> oo

:IN
ROW

REMOVABLE

|
+—LEAD
Al

_—

TK-4383

Figure 3-4

3.2

SPC Slots, NPG Jumper Lead Locations

MODULE CURRENT REQUIREMENTS

Table 3-7 lists the typical current requirements of the modules which can be inserted into the CPU
backplane.

3.2.1
DC Power Requirements
The H7140-AA, -AB provides the dc power to the modules installed in the CPU backplane and any
additional SPC backplane assemblies. The total amount of current available at the dc outputs of the
power supply must be considered when installing additional modules to ensure that adequate power is

available.

3-7

Table 3-6

SPC Location, Signal Identification

Signal Mnemonic

BUS D14 L

F1
F2
H1
H2
J1
J2
K1
K2
L1
L2

SEL 0
BUS BR5 L
IN
BUS BR4
L
SEL 2
BR OUT
OUTH
UBA BG7OUTH
BUS INIT L
BUS BG7A H

F1
F2
Hl1

BUSDI3 L
BUS DII L
BUSDI2L

M2
NI
N2

MFM BG6 OUT
INT
A
BUS BG6A H

INT B

Pin
C(XX)A1
Al
A2
Bl
B2
Cl1
C2
D1
D2
El
E2

Signal Mnemonic

BUS NPG H (IN)
+5V
—15V
BUS PAL
GND
LTC
BUSDISL

BUS D09 L

BUS DO8 L

BUS DO7 L

N1
N2
P1

BUS D04 L

P2
R1

R2
S1

T2
Ul
U2
Vi
V2
D(XX)Al1
Al
A2
B1
Cl
C2
D1
D2
El
E2

BUS DIOL

UBA BG5 OUT H

BUS BG5A H

MFM BG4 OUT H

BUS BG4A H

U2
V1
V2

BG IN
SSYN IN H
BG OUT

A2
B2
Cl

SSYN IN H

D1
D2
El
E2
F1
F2
H1
H2
J1
J2
K1
K2
L1

BUS A17L
BUS AIS L
BUS MSYN L
BUS A16 L
BUS AO2 L
BUSCIL
BUS AOL L
BUS A00 L
BUS SSYN L
BUS COL
BUS A14 L
BUS AI3 L
BUS A1l L

INTENBL

BUS DCLO L

BUS DO5S L
BUS DO1 L

BUSPB L
BUS DOO L

BUSDO3 L

E(XX)Al
Al

BUS D02 L
BUS D06 L

SEL 6
OUT LOW
BUS BR7 L
SEL 4

BUS BRG L

L2
Ml

3-8

BUS A12 L

Table 3-6

SPC Location Signal Identification (Cont)

Signal Mnemonic

M2
N1
N2
P1
P2
R1
R2
S1
S2

OUTH

F2
Hl
H?2
J1
J2
K1
K2
L1
L2

OUT LOW
BUS AO8 L
BUS AIOL
BUS A07 L
BUS A0S L
SEL 4
SEL 6
SEL 0

Signal Mnemonic

INT ENB B
BUS NPR
L

INTB

SEL 2

Ul
U2
Vi
V2

BUS A06
L
BUS A04 L
BUS AOS L
BUS A06 L

N1
N2
Pl
P2

F13N1 (F14N1)

F(XX)A1
A2
B1
B2
Cl
C2
D1
D2
El
E2
F1

BR OUT

R1
R2
S1
S2
T1
T2
Ul
U2
Vi
V2

F13L2 (F14L2)
F13N1 (F14N1)
F13M2 (F14M2)
F13P2 (F14P2)

BG IN

BUS BBSY
F13N1 (F14N1)
F13V2 (F14V2)

F13L2 (F14L2)
BUS INTR L
F13M2 (F14M2)

BR OUT
F13P2 (F14P2)

BUS SACK L
INT A
BR OUT
INT ENB B

F13V2 (F14V2)

3.2.2
H7140-AA, -AB DC Power Output
Table 3-8 lists the total current supplied from the H7140-AA, -AB power supply. The current output of
the +5.1 V output is derated by the amount of current required by the +15 V and —15 V outputs
according to the following formula:

Iisgv=120—5[(Tr15v—1)+ A—15v — 1)]
The maximum current supplied at the +5.1 Vdc output is 120 A with 1 A or less drawn from each of

the +15 Vdc and — 15 Vdc outputs. The minimum current available at the 4+5.1 Vdc output is 100 A
where maximum current of 3 A is supplied at both the +15 Vdc and —15 Vdc outputs.
Table 3-9 lists some of the UNIBUS options that are available for use in the PDP-11/44 systems and
the typical —15 V and + 15 Vdc power requirements of the modules. Refer to the PDP-11 Peripherals

Handbook and the Terminals and Communications Handbook for more detailed information on these
options.

3-9

Table 3-7

CPU Module Current Requirements

DC Current

Option (Modules)

+5.1V

KDI11-Z

+12V

—12V

+5.1 BB

1. A

50 mA

1.5A

M7090
M7094
M7095
M7096
M7098

0.5A
75 A
75 A
50A
7.0 A

KK11-B (M7097)
FP11-F (M7093)

6.5A
7.0 A

KE44-A

M7091
M7092

3.1 A
6.0 A

MS11-MB (M8722-BA)
M9302

Table 3-8
DC Outputs

+5.1V*

+15V
—15V

+5.1 BB

+12V
—12V

4.8 A
1.5A

H7140-AA, -AB Power Supply>Maximum Output Current
Current in Amperes

120

3
3

10 (battery backup)

5
1

*Derated by the current drawn at the +15 and —15 Vdc outputs

3.3

MODULE SWITCHES, JUMPERS AND INDICATORS

Several of the modules provided with the PDP-11/44 system contain switches and jumper leads which
must be set and configured for specific system requirements. The description of the switch and jumper
lead configurations for the memory, modules (M8722) is contained in the MSII-M MOS Memory
User’s Guide. Configuration information for the optional modules is contained in the respective documents listed in Table 1-2.

3-10

Table 3-9

—15V, 415 Vdc Option Power Requirements
Current Requirements (Amperes)

Option
Designation

+15 Vdc

DHI11-AD
DHI11-AE
DLI11-E
DL11-WA
DL11-WB
DMCI11-DA
DMCI11-FA
DMCI11-MA
DMCI11-MD
DUPI11-DA
DVI1I1-AA
DZ11-A
DZ11-B
DZ11-C
DZ11-D
DZ11-E
DZ11-F
RIMO02, RJP0O6, TJE16, TIU77
RK711-PA
RL11-AK, RL211-AK

0.40
0.10
0.05
0.05
0.05
0.03
0.03
0.18
0.18
0.08
0.60
0.10
0.10
0.12
0.12
0.20
0.24
0.00
0.18
0.50

—15 Vdc

0.65
0.34
0.15
0.15
0.15
0.31
0.31
0.46
0.46
0.08
1.00
0.13
0.13
0.40
0.40
0.26
0.80
0.40
0.40
0.50

Console Interface Module (M7090)

3.3.1

The console interface module (CIM) (Figure 3-5) contains 21 jumper lead locations and a light-emitting diode (LED) indicator. The jumpers are used to select transmission methods for compatibility between the CPU and the console terminal, the CPU and the TUS58 tape unit, and the CPU and the remote diagnostic unit. The jumper leads as shown in Figure 3-5 select RS-232-C transmission mode for
SLU1 (console terminal) and SLU2 (TUS8 tape unit).

3.3.1.1 Console Terminal Configurations — The console terminal cable attaches to connector J2. The
following methods of data transmission are selectable.
1.

20 mA current loop: active or passive mode

Electronic Industries Association (EIA) Standard: RS-232C, RS-423 and RS-422

Table 3-10 lists the jumper lead configuration for the 20 mA interface and Table 3-11 for the EIA
interface.

3.3.1.2 TUS58 DECtape II Configuration — The TU58 DECtape 11 device cable attaches to connector
J4. Table 3-12 lists the jumper lead configuration for selecting the EIA transmission mode.

LED

CONSOLE
TERM

TUS8

W20 O=mO

wi9o

O=mOW16

Owis
FRONT

O—oOw14

W130

PANEL

ow9

ows

OWw7?

Owe

W12 O==O
o

ow21

ows

W11 OmemO

W10 O=—0

W18 O===O

W30

wi7o

w20

wio

CIM

M7090
TK-3639

Figure 3-5

CIM Jumper Lead Locations, Connectors and
LED Indicator

3-12

Table 3-10

Mode

Transmitter
Active
Passive
EIA device
Receiver
Active
Passive
EIA device

Console Terminal Configuration, 20 mA Interface

Out
In
Out

In
Out
Out

Jumper Leads*

Wé

W13

In
Out
Out

Out
In
Out

In
Out
Out

W17

W18

In
Out
Out

Out
In
Out

In
Out
Out

Out
In
Out

In
Out
Out

In
In
Out

Out
Out
In

*Jumper lead W11 should always be installed except for module testing. When 20 mA operation is selected, jumper leads
W12, W15, W16, W19 and W20 may remain installed.

Table 3-11

Console Terminal Configuration, EIA Interface

Jumper Leads

Mode

W12

W15

W16

W17

W18

W19

W20

W1-W9, W13

RS-232C
RS-423
RS-422

In
Out
Out

Out
Out
In

In
In
Out

Out
Out
Out

In
In
In

Out
Out
In

In
In
Out

Out
Out
Out

Table 3-12

TUS8 DECtape II, EIA Configuration

Jumper Lead

Mode

W14

RS-232C
RS-423

In
Out

3-13

3.3.1.3 Remote Diagnosis Configuration — The remote diagnostic cable attaches to connector J3.
When jumper lead W21 is not installed, the remote diagnostic unit has control of the CPU when the
front panel switch is set to either the LOCAL or LOC DSBL position. When jumper lead W21 is installed, the remote diagnostic unit cannot take control of the CPU if the front panel switch is in the
LOC DSBL position.
3.3.1.4

Voltage Monitoring — The voltage monitoring circuits detect over or under voltage conditions.

Jumper lead W10, when IN, enables the 12 V supply voltages to be monitored. When jumper W10 is
OUT, the 12 V supply voltages are not monitored.
3.3.1.5
LED Indicator — The LED indicator lights when EIA data transmission to the console terminal
has occurred in both directions.
3.3.2

Multifunction Module (M7096)

The multifunction module (Figure 3-6) contains a LED indicator, 14 jumper lead locations and 4 switch

packs. The LED on the module is a self-test command indicator which lights at the beginning of a selftest command and is extinguished after the completion of the test.
3.3.2.1

Console Terminal Jumper Leads Selections — Table 3-13 lists the configuration and functions

of the console terminal jumper leads on the multifunction module.

Table 3-13

MFM Console Terminal Jumper Lead Configuration

Jumper Lead

Function

When in, address decode for the console terminal is enabled.

When in, the receiver error bits (15:12) of the console terminal receiver buffer

When in, the break bit (bit 0) of the console terminal transmitter status register

(RBUF) is enabled and can be set or cleared. When out, the break bit is dis-

abled and will remain clear.
W6

When in, console terminal receiver parity detection is enabled and parity will be

generated. If W4 is in, the parity error bit (bit 12) of the terminal receiver buffer register (XBUF) will be set on a parity error. When W6 is out, parity detection and generation is disabled and the parity error bit will remain cleared.
W7 and W8

These jumpers specify the character length for the console terminal UART, as

follows:
Jumper

Leads

5 Bits

6 Bits

7 Bits

8 Bits

Out

When in, odd parity will be generated and checked, if jumper W6 is also in.

When W9 is out, even parity will be generated and checked, if jumper W6 is in.

3-14

3.3.2.2 MFM Console Terminal Baud Rate Selection — Table 3-14 lists the positions of switch pack E6
on the MFM
to select the baud rate of the console terminal. The location of E6 is shown in Figure 3-6.
Switch S1 of E6 selects the stop bit: ON is one stop bit; OFF is two stop bits. The OFF position will also
select 1.5 stop bits if a 5-bit character is selected by jumper leads W7 and W8 (Table 3-13).

W5—

ooooI

LED

0000

wsi

w21 W1I

WI0-W14

Ioooo

0000

o
o

$1—w S10

S1—ws7

S1—+S8

S1—e89

[e ]

MEM
M7096

r. ri

TK-3634

Figure 3-6

MFM Jumper Lead Locations Switches and
LED Indicator

Table 3-14

MFM Console Terminal Baud Rate Selection

Switch Pack E6

Receiver Switch Locations

Transmitter Switch Locations

50
75
110

On
On
On

On
On
Off

On
Off
On

150
200
300

On
On
On

Off
Off
Off

On
On
Off

Baud Rate*

134.5

600
1200
1800
2000
2400
3600

4800
9600
19200

On
Off
Off
Off
Off
Off

Off
Off
Off

Off
On
On
On
On
Off
Off
Off

Off

Off
On
On
Off
Off
On

Off
On
Off
On
Off
On

On
Off
Off

On
Off
On

Off
On
Off

*When the processor is placed in the remote mode of operation, the console baud rate defaults to 19200 baud.
3-15

3.3.2.3

MFM TUS8 DECtape II Jumper Leads — Table 3-15 lists the jumper leads that select the

operating parameters of the TUS8 tape unit.
3.3.2.4

MFM TUS8 Baud Rate Selection — Switches S1 through S6 of switch pack E7 are used to
select the baud rates of the TUS58 transmitter and receiver. The location of E7 is shown in Figure 3-6.
Switch S7 of E7 selects the stop bit: ON is.one stop bit; OFF is two stop bits. The OFF position will also
select 1.5 stop bits if a 5-bit character is sélected by jumper leads W12 and W13 (Table 3-15). Switch
position S2 through S6 should only be set to the combinations shown in Table 3-16. The baud rate for
the transmitter and receiver can be different.
3.3.2.5

MFM TUSS8 Device Address Selection — The switch pack at location E70 contains switches S1

through S10 and is used to select the base address of the TUS58 tape unit from 17760000 to 17777777.
Figure 3-7 shows the address bits affected by the switch settings.
3.3.2.6

TUS8 Vector Address Selection — The switch pack at location E79 contains switches S1
through S8. Switch S1, when ON, enables the TU58 address to be decoded. Switch S2 is related to
console terminal operation. Switches S3 through S8 are used to set the TUS58 vector address from O to
770 (octal). The recommended vector address for use with DIGITAL software is 300. The transmitter
vector equals the receiver vector plus 4. Figure 3-8 shows the correspondence between the switch positions and the TUS58 vector address.

Table 3-15

Jumper Lead

MFM TUS8 Jumper Lead Configurations

Function

When in, the receiver error bits (15:12) of the TUS8 receiver buffer register are

enabled. When out, the error bits are read as zero.
W10

When in, the break bit (bit 0) of the TUS8 transmitter status register is enabled

and can be set or cleared. When out, the break bit is disabled and will remain
clear.
Wil

When in, TUS8 receiver parity detection is enabled and parity will be gener-

ated. If W3 is in, the parity error bit (bit 12) of the TUS58 receiver buffer register will be set on a parity error. When W11 is out, parity detection and generation is disabled and the parity error bit will remain cleared.
W12 and W13

These jumpers specify the character length for the TU58 UART, as follows:
Jumper

W14

Leads

5 Bits

6 Bits

7 Bits

Wi2
W13

8 Bits

Out

When in, odd parity will be generated and checked, if jumper W11

is also in.

When W14 is out, even parity will be generated and checked, if jumper W11l
,
in.

3-16

An example of the switch positions required to select a vector address of 300 is as follows:
S8 to S6 = OFF
S5,S4 = ON
S3 = OFF

SWITCH PACK E70

ADDRESS BIT

137

SWITCH ON= LOGICAL 1,

olojo
)1

NOT SWITCH
SELECTABLE

~02__

DATA f1[1[1{1{1]1]|1]|11

7 89 10— —
23456

‘ ‘-?4 S~—~— —~—7 NOT
-7
0-7 SWITCH
0-7
SELECTABLE
0/1

OFF=LOGICAL 0
TK-3637

Figure 3-7

TUS58 Device Address Selection

SWITCH PACK E79
BUS DATABIT

15141312111009

080706 050403020100

DATA |0;010|0|0]0|0O

/34567

ofo|0

8\— —

NOT SWITCH

NOT

SELECTABLE

SWITCH
SELECTABLE

SWITCH ON = LOGICAL 1, OFF = LOGICAL O

NOTE: DATABIT# 21S0 FOR RECEIVER VECTOR AND 1 for TRANSMITTER VECTOR
TK-3638

Figure 3-8

Table 3-16

TUS58 Vector Address Selection

TUS58 Baud Rate Selection (Switch Pack E7 *)

Receiver Switch
Transmitter Switch

1
4

2
5

3
6

Baud Rate 38,400
9600

ON
OFF

OFF
ON

OFF
OFF

OFF

Same baud rate as
selected for the

console terminal

*Switch S7 is not used

3.3.2.7

Line Time Clock Enable/Disable -

Jumper lead location W2 on the MFM module controls the

operation of the line time clock as listed in Table 3-17.

3.3.3

UNIBUS Interface Module (M7098)

The UNIBUS interface (UBI) module shown in Figure 3-9 contains 14 jumper lead locations and one
switch pack at location E28.

3.3.3.1
UBI Jumper Leads and Memory Page Selection — Table 3-18 lists the function of thejumper
leads on the UBI module.
Jumper leads W12-W8 and W7-W3 specify the lower and upper limit, respectively, of a set of
UNIBUS addresses not mapped to main memory (asserted on the UNIBUS only). Except for the [/0
page, every UNIBUS address not in this set is mapped to main memory (asserted on the memory bus)
by the UNIBUS map. Devices on the UNIBUS should be addressed only in unmapped or 1/O page

address space.
When the upper and lower limits are set to the same octal bank (page) number, every non-1/0 page
addressis mapped to main memory.
Table 3-19 lists the jumper lead selections for the lower limit of the set of unmapped addresses.
UNIBUS addresses from zero to just below this limit are mapped to main memory. The octal bank
number in this table is the first bank of the unmapped set, except when the lower and upper limits are

set to the same bank number, in which case only the
Table 3-17

/O page is unmapped.

Line Time Clock Operation

Line Time Clock Address

Enable decode

Out

Disable decode

~—=

fl__gfi

Wiiimiiii i
N

e
TK-3636

Figure 3-9

UBI Module, Switch and Jumper Lead Locations

3-18

Table 3-18

Jumper Lead

UBI Module Jumper Lead Functions

Function

When in, enables parity error abort

When in, enables diagnostic ROM

W3-W7

UNIBUS map page number, upper limit

WE-W12

UNIBUS map page number, lower limit

W17, W18

Always in

Table 3-19

UNIBUS Map Jumper Leads, Lower Limit

Lowest Address

Decimal

Octal

In Unmapped Set

K Words

Bank

Wi2

Jumper Leads*
Wil

W10

None

124

740 000
720 000
700 000

120
116
112

36
35
34

[
O
I

Q)
I
I

0]
O
Q)

O
0]
O

660 000

108

640 000
620 000
600 000
560 000
540 000
520 000

104
100
96
92
88
84

32
31
30
27
26
25

I
O
I
O
I
O

0)
I
|
O
Q)
I

I
I
I
0]
O
O

Q)
@)
0]
[
I
|

Q)
O
O
0]
O
Q)
O

500 000

460 000

440 000

420 000

400 000

360 000
340 000
320 000
300 000
260 000

60
56
52
48
44

17
16
15
14
13

Q)
I
O
I
Q)

@)
Q)
I
I
0]

O
O
0]
0]
I

O
O
O
0]
0]

I
I
|
I
I

240 000
220 000

40
36

12
11

O
I

I
|

200 000

160 000

140 000

120 000

100 000

[

60 000

40 000

20 000

[

*[ = IN
O = 0UuUT

3-19

Table 3-20 lists the jumper selections for the upper limit of the set of unmapped addresses. UNIBUS
addresses above this limit and below 760 000 are mapped to main memory. The octal bank number in
this table is the first mapped bank after the unmapped set, except when it is bank 37, the I/O page
(always unmapped).

Table 3-20

UNIBUS Map Jumper Lead, Upper Limit

Highest Address

Decimal

Octal

In Unmapped Set

K Words

Bank

Jumper Leads*
W6

757 777
737777

124
120

37
36

0]
I

O
0]

Q)
0)

O
Q)

O
O
0]

717777

116

677777

112

657 777
637777
617777

108
104
100

33
32
31

O
I
Q)

Q)
O
|

I
I
I

O
Q)
Q)

O
0]
O

577777

557777
537777

92
88

27
26

0]
I

O
O

O
0)

|
I

Q)
O

517777

477 777

457 777
437 777
417777

76
72
68

23
23
21

0]
0]
0]

O
0]
I

|
I
I

I
I
I

377 777

357777

)

337777

317 777

277777

257 777
2371777
217777

44
40
36

13
12
11

0]
I
O

O
@)
I

I
I
I

O
O
O

|
|
I
I

O
O

177 777

157 777

137 777

117 777

77777

57777

37777

17 777

None

*I = IN
O =0uUT

3-20

The following example describes the jumper selections for 3 pages (12 decimal K words) of UNIBUS
device addresses immediately following the 1/O page.

Page (bank) 37 is the 1/O page; therefore, the three pages to be unmapped are 34, 35, and
36.

Read jumper settings for W12 through W8 from the lower limit (Table 3-19) at bank 34, the
first unmapped bank: W12 = in, W11 = in, W10 = out, W9 = out, and W8 = out.

Read jumper settings for W7 through W3 from the upper limit (Table 3-20) at bank 37, the
next bank after the unmapped set desired (34, 35, and 36): W7 = out, W6 = out, W5 = out,
W4 = out, and W3 = out.

Notice that the upper limit “Decimal K Words” amount minus the lower limit “Decimal K Words”
amount is equal to 12K words. This is the size of the area desired.
3.3.3.2 Diagnostic and Bootstrap Loader ROMs - The UBI module provides five 16-pin, dual in-line
package (DIP) sockets for the installation of a CPU diagnostic ROM and four device bootstrap loader
ROMs. If selected, the CPU diagnostic ROM checks the CPU, main memory, and cache when power
is initially applied to the system or when a device bootstrap is initiated.

The device bootstrap loader ROMs contain device-independent bootstrap programs that enable the
loading of information from a selected peripheral device into main memory. One or two bootstrap programs may be contained in a particular ROM; however, some devices may require two or more ROMs
to contain their particular bootstrap programs. Table 3-23 lists the part numbers for the available device bootstrap ROMs.
A bootstrap operation using the UBI module boot logic can be initiated by any one of the following
actions.
1.

Pressing the front panel toggle switch to the boot position.

Typing the bootstrap command at the console terminal when in console mode.

Powering up the system.

The actual bootstrap operation performed can be a boot to the console mode (with or without diagnostics) or a boot to a selected device bootstrap ROM (with or without diagnostics). Switches S1 through
S10 at location E28 of the UBI module control the boot operation as follows.
Switch S1 determines the upper three digits of the bootstrap starting address.

S1 = On

(Boot to the console mode)

S1 = Off

(Boot selected device ROM)

Switch S2 controls the operation of the internal bootstrap logic.
S2 = On

(Internal UBI boot logic is enabled.)

S2 = Off

(Internal UBI boot logic is disabled.
This allows an external auxillary boot device to be used.)

3-21

Switches S3 through S10 are bits (08:01) of the bootstrap starting address. Table 3-21 lists the location
of the CPU diagnostic ROM and bootstrap loader ROMs and the starting address associated with each
one. The selection of the first device starting address determines whether the CPU diagnostic will be
performed before the bootstrap program is performed. The second devices listed in the table are for
selecting a second device bootstrap program contained in the same ROM as the first device bootstrap
program.

Table 3-21 CPU Diagnostic and Bdotstrap Loader, ROM Addresses
S3-10

Second

Multiple

CPU
Diagnostic

Diagnostic
(ES8)

No
Yes

0144
0020

Device 1
(E48)

No
Yes

0004
0006

0050
0052

0034
0036

004
006

030
032

Device 2
(E49)

No
Yes

0204
0206

0250
0252

0234
0236

204
206

230
232

Device 3
(E50)

No
Yes

0404
0406

0450
0452

0434
0436

Device 4
(ES9)

No
Yes

0604
0606

0650
0652

0634
0636

ROM
Location

" Device
Address
23-755A9

Second

First
Device
Address

Device
23-756A9
23-760A9

ROM Device*

Unit0 Unitl

CPU

*The DMC-11, DU-11, and DUP-11 use multiple ROMs. Table 3-23 lists the ROM part numbers.

The position of the bootstrap ROMs on the module must be sequential, starting with BT1 and progressing to BT4 as listed in Table 3-22. The IC location is indicated on the module etch.
To select an RLOI installed in the second ROM location (E49) and run the CPU diagnostic program,
set the switches as described in the following example.
RLO1 ROM in location E49
Run diagnostics and then boot RLOI

CPU

E28

= OFF

= ON

3-22

S10

Table 3-23 lists the part numbers for the available bootstrap ROMs. Some of the ROMs contain more
than one device program. The bootstrap loaders for the communication devices DL11, DMC-11, DU11
and DUP-11 are supplied in three ROMs for each device.

Table 3-22 Bootstrap ROM Locations
IC Location

Bootstrap ROM

E48

Device 1

E49

Device 2

E50

Device 3

E59

Table 3-23

Device 4

Device ROM Part Numbers

Device

ROM Part Number

Device

ROM Part Number

ASR33

23-760A9

RLOI

23-751A9

DL11

23-926A9
23-927A9
23-928A9

RP02/03

23-755A9

RP04/05/06

23-755A9

23-862A9

RS03/04

23-759A9

23-864A9

RXO01

23-753A9

23-868A9

RX02

23-811A9

23-870A9

TS04

23-764A9

23-865A9

TUI10, TE10, TSO3
TUI16, 45,77, TEI6

23-758A9
23-757A9

23-867A9

TUS5/56

23-756A9

PCO05

23-760A9

TUSS8

23-765A9

RKO03/05

23-756A9

TU60

23-761A9

RKO06/07

23-752A9

DMC-11

23-863A9

DU-11

23-869A9

DUP-11

23-866A9

3.3.4
Cache Memory Module (M7097)
The cache memory module, shownin Figure 3-10, contains three LED indicators, two toggle switches
and two jumper lead locations.

3-23

n
N
Y—=n—n
D2 D1 D3 /
oo

|s2

ONesOFF

=P
W10—o0
W20

HI LOW

KK11-B

M7097

rmn

T
mn
J71r&
TK-3635

Figure 3-10

3.3.4.1

Cache Memory Module, Switches, LED Indicators and
Jumper Lead Locations

LED Indicator Functions — Table 3-24 lists the functions of the LED indicators.

3.3.4.2 Multiport Memory Selection — Jumpers W1 and W2 are provided to accommodate multiported memory. In the PDP-11/44 (without multiported memory), jumper W1 should be in and jumper
W2 should be out. In systems using multiport memory, jumper W1 is out and jumper W2 is in.
When on, switches S1 and S2 will force misses to the high and low cache address space, respectively.
The switch is on when the lever is positioned to the left, toward the LED indicators.
3.3.5

Control Module (M7095)

The control module contains a toggle switch, S1, (Figure 3-11) that is used to enable or disable the
bootstrap operation on power-up.

Table 3-24

Cache Module, LED Indicator Functions

LED

Function

D‘X’-’

Parity error

Hit
Address MATCHED

Dl
D$2

— MEM 3'/5A‘5

3-24

R
|.
ONe—f{

—OFF

BOOT

ENABLE=ON

CONTROL
M7095

B I

|
TK-5020

Figure 3-11

Control Module, Bootstrap Control Switch

3-25

CHAPTER 4
INSTALLATION

The PDP-11/44 and PDP-11X44 systems and peripheral devices can be operated in most contaminantfree environments such as offices, laboratories or light manufacturing areas. However, to ensure reliable operation, certain environmental conditions are recommended.
4.1
SITE CONSIDERATIONS
The computer equipment should be operated in an environment that is controlled by an air-conditioning
system which provides temperature controlled, filtered air at the specified levels of humidity. The airconditioning system should also increase the air pressure in the computer area to prevent the infiltration
of dust and other contaminants from adjacent areas.
The air-conditioning equipment should conform to the requirements of the Standard for the Installation
of Air-Conditioning and Ventilating Systems (Non-Residential), N.F.P.A. No. 90A, as well as the requirements of the Standard for Electronic Computer Systems, N.F.P.A. No. 75.
4.1.1

Temperature and Humidity

Temperature cycling and thermal gradients can induce changes in materials which will affect the per-

formance of the system. High temperatures also increase the rate of deterioration of materials. An environment of high absolute humidity can cause dimensional changes in paper tapes, lineprinter papers
and cards. Low humidity can produce static electricity, resulting in dust accumulation on magnetic

tape and disk devices, which will adversely affect the system operation.
The PDP-11/44 systems are designed to operate in a temperature range of 5° to 50° C (41° to 122° F)
at a relative humidity of 10 to 95 percent without condensation. System configurations that use 1/O
devices, such as magnetic tape units, card readers, disks, etc., require an operating temperature range
from 10° to 40° C (50° to 104° F) at a relative humidity of 40 to 66 percent without condensation. The
nominal operating conditions for a system configuration are a temperature of 20° C (70° F) and a rela-

tive humidity of 45 percent.

4.1.2 Acoustical Dampening
Some peripheral devices such as character printers, lineprinters and magnetic tape transports generate
noisc when operating. When many of these units are located in an area, sound absorbent materials may
be used to reduce the noise level. Sound absorbent ceiling materials are available and antistatic carpets
may be installed. In addition, the wall areas may be covered with drapes or other suitable material
which will reduce the reflected noise.
4.1.3

Lighting

When video displays (CRTs) are used with the system, a reduced lighting level at the site will prevent

excessive reflection from the face of the CRT and enable the display to be viewed more easily by the
operator. The light levels may be controlled by dimmers or by the installation of translucent materials
between the light source and the surrounding areas.

4.1.4 Static Electricity
The PDP-11/44 and related cabinets should be adequately grounded to prevent the effects of static
electricity from interfering with the equipment operation. Static charges can be reduced by maintaining the relative humidity of the room at the specified 45 percent nominal value. Antistatic carpeting is
also available to minimize the static charges generated. When raised floors are used at the computer
installation, the framing of the floor panels should be adequately grounded.
4.1.5

Shock and Vibration
When the PDP-11/44 units are to be installed at locations subjected to excessive shock and vibration,
special cabinet mounting hardware may be required. Contact your local DIGITAL sales representative
for information related to special environmental conditions.

4.1.6 FElectrical Interference
Several types of electrical interference may be indigenous to the site location and may require special
filtering to prevent equipment malfunctions.
The interference transmitted through the air is electromagnetic interference (EMI) and may be caused

by TV and radio waves, radar transmissions, lightning discharges, ignition systems and power line transmissions. Interference may also be transmitted through the ac power lines. If the interference is suspected to be causing problems with the operation of the equipment, shielding may be required, or filtering of the ac power to the site. Contact your local DIGITAL sales office or field service representative
for information related to interference problems.
4.2

UNPACKING

The system equipment, associated devices, and cabinets are packed and shipped in reinforced cartons

and are protected internally by foam inserts and polyethylene bags. Accessories and supplies such as
documentation, magnetic tape or disks, and connecting cables and hardware are packed in separate
containers. Before unpacking any carton, remove the packing list from the container and check that the
items ordered are listed. When the items are unpacked, use the list to check that all the items are in the
package. The unpacking information for consoles, printers, disk drives and magnetic tape is contained
in the user’s guide supplied with each device.
NOTE
Retain the packing materials and shipping containers in the event reshipping is required.

4.2.1
PDP-11/44-CA, -CB Unit Removal
The PDP-11/44-CA and CB units are packed in reinforced cartons and protected by foam inserts and a
polyethylene bag as shown in Figure 4-1. To remove the unit from the container, perform the following

procedure.
CAUTION
The PDP-11/44-CA, -CB units weigh approximately 34 kg (75 lbs). Use care when lifting the unit

Nk w—~

from the carton.

Open the leaves of the outer carton by cutting the tape at the seams.
Remove the inner carton from the foam protector.
Open the leaves of the inner carton by cutting the tape at the seams.
Remove the side and rear protectors.
Remove the unit from the polyethylene bag.
Remove the bezel protector.
Inspect the unit for visible damage and ensure that the contents are complete.

4-2

SIDE PROTECTOR

REAR PROTECTOR

4
BA11—A UNIT

\POLY BAG

BEZEL PROTECTOR

/—INNER BOX

OUTER BOX

FOAM PROTECTOR

TK-3529

Figufe 4-1

PDP-11/44 Unit Unpacking

4-3

AR
ol

4.2.2 PDP-11X44-CA, -CB Cabinet Removal
The PDP-11X44-CA, -CB units are attached to a wooden base, covered with a polyethylene bag and
enclosed by a carton as shown in Figure 4-2. To remove the unit, perform the following procedure.
Cut the polyester straps that secure the carton and unit to the base.

Slide the carton up and away from the unit.
Remove the polyethylene bag from the unit.
Remove the bolts that hold the bottom of the unit to the wooden base.
Remove the unit from the wooden base and set the unit in its operating location.
Attach the stabilizer feet to the bottom of the unit.

CARTON SEALING TAPE

HALF SLOTTED CARTON WITH
BOTTOM FLANGE

CORNER SUPPORTS

POLYESTER STRAP
FOAM PAD

[ POLYETHYLENE BAG

PDP—11X44

SYSTEM CABINET

TK-4385

Figure 4-2

PDP-11X44 Cabinet Unpacking

4-4

4.2.2.1 Shipping Restraint Removal — Two types of shipping restraint are used in the PDP-11X44 cabinet. The type of restraint used can be determined by the configuration of the top cover as shown in
Figure 4-3. In the type A configuration, the box is secured in the cabinet by two shipping brackets and
screws. In the type B configuration, the shipping restraint and release mechanism are one unit which
does not have to be removed. To disengage the type B release mechanism, refer to Paragraph 5.1.1,
|
steps 6 and 11.

To remove the shipping restraint in the type A configuration, perform the following procedure.
1.

Open the front and rear doors of the cabinet. Use a 4mm (5/32 in) hex wrench to release the

Slide the retractable hinge pin down until the top of the rear door is released.

Tilt the top of the door away from the cabinet and lift the door until the lower hinge pin is

Remove the rear door.

Remove and retain the two 1/4-20 screws and washers that attach the right bracket to the

door fasteners (Figure 4-4).

removed from the hole in the lower right bracket.

cabinet frame.

Retain the right bracket.

Remove and retain the two 1/4-20 screws and washers that attach the left bracket to the

Retain the bracket.

cabinet frame.

TYPE A

TYPE B

FILLER STRIPS

ONE PIECE CABINET

TOP COVER

CABINET

TOP COVER

——
CABINET
REAR

CABINET
REAR

TK-5641

Figure 4-3

PDP-11X44 Cabinet Type Identification

4-5

RETRACTABLE
HINGE PIN

REAR DOOR

DOOR

FASTENER

RIGHT
BRACKET

L
[]

LEFT
BRACKET

HINGE PIN

SCREWS—

BRACKET

TK-4921

Figure 4-4

Left and Right Side Panel Removal

4-6

Grasp the left side panel by the ends at the front and rear of the cabinet and lift up approximately 2.5 cm (1 in) to disengage the panel and pull the panel away from the cabinet to
remove it.

NOTE

A ground lead is attached to the panel and will restrict the movement of the panel away from the cabinet. Do not remove the lead.

10.

Perform step 9 to remove the right side panel from the cabinet.

11.

Remove the 10-32 screw and washer that is inserted through the shipping bracket and into

12.

Replace the left and right side panels that were removed in steps 9 and 10.

13.

Replace the brackets that were removed in steps 5 and 7.

14.

Tilt the rear door and insert the lower hinge pin into the hole of the bracket closest to the

the mounting box at the left and right side of the cabinet (Figure 4-5).

right side panel.

FRONT

BEZEL

Q\\s

GAS SPRING Q
LEFT

SHIPPING

BRACKET

Y
[0}

%\\-\\\

TK-4922

Figure 4-5

Shipping Bracket Location
47

15.

Move the top of the rear door toward its mounting position while holding the retractable
hinge pin downward.

16.

Release the retractable hinge pin when the pin is aligned with the hole in the top of the cabinet frame.

17.

Close the front and rear doors of the cabinet.

4.3

EQUIPMENT DIMENSIONS
Figure 4-6 shows the overall dimensions of the PDP-11/44 unit. The unit will occupy a 26.7 cm (10-1/2

inch) vertical space within a rack or cabinet.

Figure 4-7 shows the overall dimensions of the PDP-11X44 unit. This system is enclosed within a standard system cabinet. When additional units are included in the system configuration, refer to the respec-

tive user’s guide for the space requirements of each cabinet.

4.4 AC INPUT POWER REQUIREMENTS
The ac input power to the PDP-11/44 system equipment should be supplied by a separate power circuit
which is dedicated only to the system.

Table 4-1 lists the power requirements for the four basic system configurations. Any additional equip-

ment installed into the cabinet of the PDP-11X44-CA, -CB system or modules installed into the mounting box may increase the power consumption. Refer to the respective user’s guide for the power require-

ments of the peripheral devices that are supplied with the system.

"\42.21 cM

———u
|

—

(16.62)

26.34 CM

(10.37)

26.34 CM|

(10.37)

48.26 CM

(19.0)
NOTE:

DIMENSIONS IN PARENTHESIS
ARE IN INCHES

TK-4384

Figure 4-6

PDP-11/44 Unit Dimensions

4-8

54.29 cm

(21.38)

——————»
=~

Mlm,

T T

100.33 CM

(39.5)

NOTE:

DIMENSIONS IN PARENTHESES
ARE IN INCHES
TK-4386

igure
4Figure
4-7

PDP-11X44 System Cabinet Dimensions

4-9

Table 4-1

System AC Input Power Requirements
System Designation

PDP-11/44-CA
PDP-11X44-CA

PDP-11/44-CB

90-128 V

180-256 V

Tolerance

47-63 Hz

Phase(s)

Steady State
Current (RMS)

16 A rms max load

9.5 A rms max load

Surge Current

65 A peak

130 A peak

Surge Duration

1/2 cycle

AC Voltage
Tolerance

PDP-11X44-CB

Frequency

4.4.1

Power Connections (AC)

The PDP-11/44-CA, -CB units are supplied with a 2.74 m (9 ft) line cord attached to the rear of the
unit. Figure 4-8 shows the ac line cord circuit breaker and connectors. The line cord plug may be connected to an 872-D, -E power controller unit (or equivalent) or directly to the ac power receptacle at the
site location. Figure 4-9 shows the type of connector plugs and receptacles used and the DIGITAL part
numbers for the connectors. The color of the cable wires connected to the plug is also indicated. The
NEMA 5-20 P plug is attached to the PDP-11/44-CA (120 Vac) cable and the NEMA 6-15 P is attached to the PDP-11/44-CB cable. The NEMA 5-20 R and 6-15 R are dual receptacle outlets which
can be installed within a wall outlet box or a power distribution unit.
Mounted at the lower rear of the PDP-11X44-CA, -CB cabinet is a power controller unit which controls
and distributes the ac power to the units within the cabinet. The PDP-11X44-CA contains an 872-D
(120 Vac) power controller, and the PDP-11X44-CB contains an 872-E (240 Vac) power controller.
Each controller is supplied with a 4.57 m (15 ft) cord and plug which connects to a receptacle at the site
location. Figure 4-10 shows the connector configurations and DIGITAL part numbers for the plugs and
receptacles.
4.4.2 System Grounding
The PDP-11/44 and PDP-11X44 systems are commonly grounded to the main power lines through the
ac power cord. All units which are part of the system should be connected to a separate and common ac
power distribution source to ensure the integrity of the grounding network. If a grounding problem is
evident, the potential of the cabinet or mounting box grounds may be checked by connecting a voltmeter between two cabinet frames or between the cabinet frames and the BA11-A mounting box. To
ensure positive grounding between the cabinets of the system, it is recommended that a grounding strap
or cable be attached in common to each of the cabinet frames. Contact your local DIGITAL field service office for information related to grounding problems.

4-10

o
|

]

#__J [
e

A A
D

O m

T AT

0 0o

)

::_n_:_l n_:_n_:_J L

0 _H_
I

I |A
oo

I
e

| R

[€X6)

ksl

on o

AC POWER

©)

D o

® \

120/240 VAC

gl°

e Bt e
c8|

CIRCUIT

SWITCH

TERMINAL COVER

5 J1

BREAKER
AC

LINE CORD

——
TK-4389

Figure 4-8

Mounting Box Rear Panel Components

PIN SIDE

GROUND

(GRN/YEL)

GRN/YEL

NEUTRAL

(BLUE)

pHase (BLUE)
125V 20A

MALE PLUG

POP—11/44—CA

PDP—11/44—CB

DESIGNATION

POWER

RATING

DIGITAL PART NO.

520 P

125V 204

12—15183—00

5-20 R

6—15 P

6—15 R
P =

PLUG

R =

RECEPTACLE

*
%

Figure 4-9

(BRN)

240V, 15A

MALE PLUG

NEMA *

PHASE

(BRN)

12—12265-00 * *
90—08853—00

240V, T5A

DUAL RECEPTACLE OUTLET

12—-11204—01 * *

TK-4390

PDP-11/44-CA, -CB AC Connector Specifications

RECEPTACLE (FEMALE)
PHASE OR
NEUTRAL

(NEUTRAL

X
GREEN
EARTH

PLUG (MALE)

PREFERRED)

<§
©

GROUND

{

PHASE OR

NEUTRAL
NEMA L6-30R

NEMA L6 -30FP

230 V USED WITH THE 872—-E

RECEPTACLE (FEMALE)

GREEN G

EARTH

PLUG (MALE)

NEUTRAL
PHASE

GROUND

)

NEMA L5-30R

NEMA L5-30P

115 V USED WITH THE 872-D

CONNECTOR SPECIFICATIONS

MODEL

PLUG

RECEPTACLE (SUPPLIED BY CUSTOMER)

NUMBER

POWER

RATING

NEMA CODE

DEC PART NO.

872-D

115 V

30 A

L5-30P

L5-30R

12-11194

872—E

230 V

20 A

L6-30R

12-11191

TK-4391

Figure 4-10

872-D, -E Power Controller Input Power
Specifications

4.5 BA11-AA, -AB MOUNTING BOX INSTALLATION
The BA11-AA, -AB mounting box is designed to be installed within a standard 48.26 cm (19 in) rack or
cabinet on slide mounting assemblies as shown in Figure 4-11.
A slide kit is available (part number 70-18133) and includes one each of the following items: left and
right index plates and mounting hardware; left and right slide assembly and mounting hardware.

3
ooooooeooooooeoéj.oo,oooeoooooooooooooooo

XXXX3N]
XX
X

CIECE

- /
<2

NOTE:

SLIDE AND SLIDE INDEX PLATE
ARE USED WITH RACK MOUNTED VERSION.
TK-4183

Figure 4-11

Mounting Box in H961 Cabinet

4.5.1
Index Plate Mounting
The index plates supplied with the kit are mounted onto the sides of the BA11-AA, -AB mounting box
and permit the box to be tilted on the slides for servicing. To install the index plates refer to Figure 4-12
and perform the following procedures.
1.

Position the right index plate onto the pawl as shown. The index plate mounting tab protrudes

away from the side of the box.
2.

Insert the pivot screw and tighten with a screwdriver.

Ensure that the index plate rotates freely when the locking pawl is released.

Perform steps 1 and 3 using the left index plate.

4-13

RIGHT INDEX
PLATE

/— PIVOT SCREW

|
o

PAWL
RETRACTOR

BA11—AA, —AB MOUNTING BOX
o]

RIGHT SIDE VIEW

LEFT INDEX

PLATE —

PIVOT SCREW

/I PAWL

%
0o

mn S S
CHE)
O

TAB

O
PAWL

BAT1-AA, —AB MOUNTING BOX

RETRACTOR

LEFT SIDE VIEW
TK-4392

Figure 4-12

BAI11-AA, -AB Mounting Box Index Plate Installation

4.5.2

Slide Assembly Mounting
One of two types of slide assemblies is provided with the slide kit option: a single-channel slide set or a
double-channel slide set. Figure 4-13 shows each type mounted to the BA11-AA, -AB unit and fully
extended from the cabinet. The mounting location of the slides will vary depending on the type of slide.
Figure 4-14 shows a typical H961 standard cabinet with the PDP-11/44-CA, -CB unit. The mounting
location holes of the single-channel slides for each 26.67 ¢cm (10.5 in) unit are indicated in Figure 4-14.
When installing double-channel slides, the hole location numbers will be decreased by two for the same
mounting position of the unit.

4-14

CABINET RAIL

/—— BA1T1-AA, —AB UNIT

PAWL RETRACTOR

SINGLE—/
CHANNEL

SLIDE

/ BA11-AA,—AB UNIT

CABINET RAIL

4
PAWL RETRACTOR

7
«
4

[

SLIDE H_OLD-/
LEVER

[

DOUBLE CHANNEL —/

]

SLIDE

TK-4393

Figure 4-13

Single- and Double-Channel Slide Assemblies

SLIDE

62 E
59

* RAIL HOLE
NUMBERS

[0 0]

H961 CABINET

MOUNT

|IO

F EACH LOCATION

10.5 IN (26.67 CM)

R
PDP—-11/44

MOUNTING

E
44
11O
41
26

|IO

BOX

g
*

NOTE
DECREASE RAIL HOLE NUMBERS

BY TWO (2) WHEN INSTALLING
A DOUBLE CHANNEL SLIDE SET.
TK-4394

Figure 4-14

H961 Cabinet Slide Mounting Locations

Figure 4-15 shows the hardware and installation of a single-channel slide assembly. The double-channel
slide assembly is mounted in a similar manner. To install the slide, perform the following procedure.
1.
2.

Position the left slide against the left front and left rear cabinet rail as shown.
Insert one 10-32 screw and washer through the top hole in the slide bracket, through the hole
in the front rail and into the top threaded hole in the nut plate. Do not tighten.

Perform steps 1 and 2 at the left rear rail of the cabinet.

Insert one 10-32 screw and washer through the second hole from the bottom in the slide
bracket, through the hole in the front rail and into the nut plate. Do not tighten in the front
rail.

Perform step 4 at the left rear rail of the cabinet.

Insert one 10-32 screw and washer through the third hole from the bottom in the slide
bracket. Tighten the three screws in the front rail.

Perform step 6 at the left rear rail of the cabinet.

Perform steps 1 through 7 to install the remaining slide onto the right side of the cabinet.
LEFT REAR

CABINET RAIL

LEFT FRONT
CABINET RAIL

/@@@6@]@@@@@@

LOCK

—

screws
(10-32)

6 PLACES
FRONT AND
REAR

WASHER

SINGLE CHANNEL
SLIDE ASSEMBLY

\_ SLIDE
BRACKET
TK-4395

Figure 4-15

Cabinet Slide Installation

4.5.3
Mounting Box to Slide Installation
Figure 4-16 shows the method and hardware used to install the mounting box onto the slide mounting
bracket. Perform the following procedure.
1.

Extend the left and right slide‘channels to their maximum position at the front of the cabinet.
When fully extended, the channels will be held in place by the slide hold lever shown on

Figure 4-13.

4-17

8-32 SCREWS
(3 PLACES)

INDEX
PLATE
SLIDE

ALIGNMENT

MOUNTING

TAB

BRACKET

TK-3486

Figure 4-16

Mounting Box to Slide Installation

Carefully lift the mounting box over and above the extended slides and set the index plate
over the slide mounting bracket on each side of the box. The index plate alignment tabs will
engage the sides of the slide mounting bracket.
NOTE
When the slides are fully extended, it may be necessary to force the ends of the slides inward toward the
sides of the mounting box.
Insert the three 8-32 screws through the left index plate tab and into the threaded holes of

the slide mounting bracket.
Perform step 3 for the right index plate.

4-18

4.6 PDP-11X44 SYSTEM CABINET INSTALLATION
The PDP-11X44-CA, -CB system cabinet is supplied with four rollers on the bottom frame and four
leveler feet. The cabinet can be positioned alone or attached to another H9640 series cabinet. When
operating alone, a stabilizer bar (option no. H9544-MJ) must be attached to the rear of the unit to
prevent the cabinet from tilting when the BA11-AA, -AB boxis raised to the servicing position.
4.6.1
Base Stabilizer Installation
Figure 4-17 shows the mounting position and hardware used to install the base stabilizer onto the PDP11X44 system cabinet. To mount the stabilizer, perform the following procedure.

Position the left and right coupler over the collars on the base stabilizer as shown.

Slide the stabilizer under the rear of the cabinet and align the mounting holes.

Insert the mounting bolt and washer, through the plate, through the slot in the frame, and
into the threaded hole of the coupler. Do not tighten.

MOUNTING
BOLT

WASHER ———»é
PLATE —»@
|

CABINET
FRAME
SCREW

DRIVER
-

TURN

RAISE

COUPLER
—

BASE

STABILIZER

COLLA\R

TURN
TO

TK-4388

Figure 4-17

Cabinet Stabilizer Mounting

4-19

Tolevel the cabinet turn the coupler by inserting the shank of a screwdriver through the hole,
in the direction desired.

Insert the shim into the location as shown.

Tighten the mounting screw with a 13/16 in box-end wrench while holding the coupler in
position with the screwdriver.

4.6.2 Servicing Area
The rear door of the PDP-11X44 system cabinet can be opened to gain access to the 872-D, -E power
controller, the connectors attached to the I/O panel, and the rear panel of the BA11-AA, -AE mounting
box. Figure 4-18 shows the service area clearance at the rear of the cabinet to permit the opening of the
door and access to the internal units. The clearance also prevents the obstruction of air flow through the
cabinet.

/////

_
46.35 CM

(18.25)

PDP—11/X44

SYSTEM
CABINET

NOTE:

DIMENSIONS IN PARENTHESES
ARE IN INCHES
TK-4387

Figure 4-18

PDP-11X44 System Cabinct Service Area

4-20

4.7

CABLE ROUTING

The power and signal cables routed between assemblies within a cabinet and externally between cabi-

nets should be properly secured away from sharp objects. Cables connected between cabinets should be
protected from damage by routing through a channel or by covering with protective padding. The ac
power cables and signal cables should be routed separately from each other to prevent the possibility of
signal interference.
4.7.1
Mounting Box Cable Routing
The cable assemblies that are attached to connectors on the modules are routed between the rear card
guides through the cable trough directly behind the card guides and through the trough on the left side
of the power supply. Figure 4-19 shows the position of the rear card guides and cable troughs.

4.7.2

PDP-11X44 Cabinet Cable Routing

Figure 4-20 shows the routing of the cables at the rear of the system cabinet. The UNIBUS cable is

folded and clamped at the rear of the power supply as shown. All other cables such as the console
terminal cable from the 1/O panel should be clamped to the cabinet channels. The length of all cables
should be adequate to allow the mounting box to be raised for servicing without causing cable strain.
Nylon tiewraps can be used to secure the cables to cabinet channels.

4.8
POWER CHECKS
The system contains several indicators that can be used to check the ac and dc power to the system. The
872-D, -E Power Controller unit contains an ac indicator that lights when ac power is applied. The
control panel of the BA11-A box also contains a DC ON indicator that displays the status of the dc
voltage from the power supply.

gf\gg

CABLE

ROUGHS

H7140—AA,—AB

POWER SUPPLY

GUIDES

TK-3478

Figure 4-19

BAI11-A Cable Routing Locations
4-21

0000000000 000000O0 (e

flovecseee

OOOOOO\,OOOOOOOUbeOOOOOOOC?QOOO.O....OOOOOOOOOO[(D

CABLE

CONSOLE

" TERMINAL
CABLE

| _L-1/0 PANEL

20 MA
ADAPTER
CABLE

UNIBUS

—1

OEEED

sla

/
l

0EEIN

o
\
p

@’

_-POWER

—

am O

—| CONTROLER
@y

CIRCUIT
BREAKER

TK-3640

Figure 4-20

PDP-11X44 Cabinet Cable Routing

AC Power Distribution
The ac power in the PDP-11/44 system cabinet is distributed from the 872-D, -E Power Controller or a

similar power controller unit. The 872-D, -E unit contains three dual-switched ac receptacles and one

dual receptacle that is not switched. The ac power to the switched receptacles is controlled by the LOCAL/OFF/REMOTE switch on the 872-D, -E control panel, or by the keyswitch on the front panel of
the mounting box if the LOCAL/OFF/REMOTE switch is in the REMOTE position.

4-22

4.8.1.1
Initial AC Power Checks
To check the ac power, perform the following steps.
l.

Ensure that the keyswitch on the control panel of the mounting box is in the LOCAL, LOC
DSBL or STD BY position.

Check that the ac indicator, on the control panel of the 872-D, -E unit, is lighted.
If the indicator is not lighted, check the main ac power outlet to ensure that ac voltage is
present.

If the indicator is lighted, check that the MAIN POWER circuit breaker on the 872-D, -E
unit is in the ON position (1).

Check that the LOCAL-ON/OFF/REMOTE-ON switch on the POWER CONTROLLER
is in the LOCAL-ON or REMOTE-ON position.

If in the REMOTE-ON position, set the switch to the LOCAL-ON position.

If the ac power is not applied, remove connector P1 or P2 from the dc power control bus on
the power control unit.

If pin 1 of P1 is open to ground, check the continuity of the power control cable between
connector P1 and P2.

Remove connector P1 from J3 on the rear of the PDP-11/44 mounting box.
10.
11.

If pin 1 of J3 is open to ground, the mounting box wiring is defective.

If pin 2 of P1 in step 7 is grounded, an overtemperature condition exists in a unit within the
system cabinet or peripheral cabinet.

4.8.2

DC Power Distribution

The dc voltages from the power supply are distributed to the CPU backplane and to any optional backplanes in the mounting box. The DC ON indicator on the control panel of the PDP-11/44 mounting box
monitors the dc voltages and provides a visual indication of power failures.
4.8.2.1

DC Power Checks — To check the dc power, perform the following steps.

Perform steps 1 through 5 of paragraph 4.8.1.1

Measure the +5 V CPU backplane voltage at the connector end of the flexprint cable shown
in Figure 4-21.
CAUTION
When measuring the +5 V bus voltage, do not short
the +5 V bus and ground bus together.

Measure the remaining backplane voltages at connector Pl of the power flexprint cable

shown in Figure 4-21. Table 4-2 indicates the voltage and signal connections on P1.

If a dc voltage failure is evident, remove and replace the H7140-AA, -AB power supply as
described in paragraph 5.4 of this manual.

4-23

PIN SIDE

SYSTEM BACKPLANE

44—

PIN SIDE
SLOT

TT7

§
D

1l o o o 06 0 @ o 0 0 o l
TTT..........T

fll

fl"r——U

! I

e
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| 0 l]—l —-—M
o fee

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[~$-——H
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ot+--¢

od-——c

T
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—1
I

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| :

: |

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L
lo

|| !

|} |

’H

[l |

111

135

11-1
o

———

[

PIN LOCATION
01

PIN DESIGNATION

POWER
FLEXPRINT

CABLE

Backplane Assembly, Pin Designations

CPU Backplane Connector P1, Signals and Voltages

Function

1-10

+5B

11-16
17,18

—12 VB

+12 VB

LTC

BUS ACLOL

21
22
23
24

BOOT ENAB L
BUS DCLO L
GND SENSE
+5 SENSE
—15
+15

4-24

SIDE OF

GND
FLEXPRINT CABLE

26,28

‘

PIN ROW (1 OR 2)

FLEXPRINT CABLE

25,27

ROW (A—F)

+5V

Table 4-2

|—+--0

| 1]

Figure 4-21

t——s

0-—f-—r

[®

CONNECTOR P1

; I

o]
1

-i

| 0—gq——V

e ———————H

24 6

o o

ROW

—

o
Pl |
I

(G,1,0,Q,W,X,Y,Z,OMITTED)

4.9

SYSTEM EVALUATION

The PDP-11/44 system can be evaluated by a series of diagnostic exerciser programs. These programs
detect and isolate system failures where they occur.
Two basic types of diagnostics are associated with the system, external and internal. The external diagnostics are loaded and executed under XXDO04. The internal diagnostic programs are contained in
ROMs located on the UBI and MFM modules.
4.9.1
MAINDEC Diagnostic Programs
The MAINDEC diagnostics are external programs which are listed in Table 4-3. These programs are
loaded and executed with the MAINDEC diagnostic package XXDP+. This package includes monitor
programs, device driver programs and utility programs for the CPU and peripheral devices.

Diagnostics 1 through 11 should be executed in the sequence as listed to obtain the proper results. Each
diagnostic test assumes the successful completion of the preceding test.

4.9.1.1

Diagnostic Designations — The designations assigned to the PDP-11 family of diagnostic pro-

grams are described as follows.

CKFPA

“C” indicates a PDP-11 diagnostic.*

Indicates a series of diagnostics: A =

part 1, B = part 2, C = part 3, etc.

“K” indicates a specific diagnostic for
the PDP-11/44 system.

Indicates the specific device tested by
the diagnostic:
“FP” = Floating Point diagnostic
“RK” = RKOS5 (disk diagnostic)

“Z” indicates a general PDP-11
diagnostic.
* Not used on diagnostic disk pack or on magnetic tape.

The “xy” designation that appears after the MAINDEC diagnostic listing on the table contains the
following information.

(xy)
Revision

Patch Number (0-9)

Character

(alpha)

4-25

Table 4-3

PDP-11/44 MAINDEC Diagnostic Programs

MAINDEC

Operating

Diagnostic

Sequence

Title

CKK FA (xy)
CKK AA (xy)
CKK AB (xy)
CKK TA (xy)
CKK TB (xy)
CZM 9B (xy)
CKK UA (xy)
CKK KA (xy)
CZM SD (xy)
CZD LD (xy)
CKK AC (xy)
CKF PA (xy)
CKF PB (xy)
CKF PC (xy)
CZK EE (xy)
CZK UA (xy)
CZK UB (xy)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

11/44 Diagnostic ROM*
11/44 CPU/EIS
11/44 Traps
11/44 Mem. Mgt. Prt
A
11/44 Mem. Mgt. Prt
B
M9312/11/44 UBI Boot
11/44 UBI Map
11/44 KK11-B Cache
MSL-M/L Memory
DL11-W/MFM SLU
11/44 Power Fail
FP11-F Part A
FP11-F Part B
FP11-F Part
C
PDP-11 CIS Instr. Exerciser
UNIBUS Systems Exerciser Diag.
UNIBUS Exerciser Module

*Included with the M7098 UBI module.

4.9.2

Internal Diagnostic Programs

The internal diagnostics consist of the PDP-11/44 diagnostics contained in the CPU diagnostic ROM
located on the UBI module and the console diagnostics contained in a ROM on the MFM module. The
CPU diagnostic, if selected (refer to Paragraph 3.3.3.2), is initiated by one of the following actions:

Pressing the front panel toggle switch to the BOOT position.

Typing the bootstrap command at the console when in the console mode.

Powering up the system with switch S1 on control module in the ON position (powerup boot

enabled.)

4-26

Table 4-4 lists the LOOP/HALT addresses and the test that failed the CPU diagnostic. When a failing
test is in a loop, enter console mode and halt the CPU with a halt command from the console. The
console will then print the LOOP address.
The console diagnostic is initiated by one of the following actions:
1.

When the CPU is halted except by a HALT command from the console.

When entering console mode using a AP command.

When using the T or T/E command when in console mode.

Table 4-4

CPU Diagnostic ROM Error Indicators

Loop/Halt

Test

Address

No.*

Sequence or Instruction Failure

165070
165106
165122
165134
165172
165202
165220
165240
165246
165260
165302
165312
165334
165346
165356
165366
165400
165406

1
2
3
4
5
6
7
10
11
11
12
13
13
14
14
14
14
14

Unconditional branch
CIR, mode 0, BMI, BVS, BHI, BLT, BLOS
DEC, mode 0, BPL, BEQ, BGE, BLE
ROR, mode 0, BUC, BHIS, BNE
Register data path
ROL, BCC, BLK
ADD, INC, COM, BCS, BLE
BOR, DEC, BIS, ADD, BLO
COM, BLOS
BIC, BGT, BLE
SWAB, CMP, BIT, BNE BGT
MOVB, BPL
SOB, CIR, TST, BNE
JSR
Push onto stack failed
RTS
RTI
JMP

165634
165652
165664
165702

16
16
150r 16
Any test

No hit in cache**
No hit in cache**
Parity error
Hardware trap to 4 (check stack)

165526
165550

15
15

Main memory data error WO /cache
Main memory data error WO/cache

*Tests 1-14 loop on error. Tests 15-16 halt on error.
** Cache memory may be manually disabled by switches S1 and S2 on the cache memory module.

4-27

CHAPTER 35

REMOVAL/REPLACEMENT
PROCEDURES

The PDP-11/44 system is designed to permit units and assemblies to be easily removed and replaced.
This section includes the removal and replacement procedures for the BA11-AA, -AB mounting box,
the H7140-AA, -AB power supply, and the fan assembly. For detailed removal and replacement procedures related to other units supplied with the system, refer to the appropriate manuals supplied.
5.1

BA11-AA, -AB MOUNTING BOX IN SYSTEM CABINET

In the PDP-11X44 system, the BA11-AA, -AB mounting box is located at the top of the system cabinet.
Two types of release mechanisms are in use to allow the BA11-A mounting box to be raised to the
servicing position in the PDP-11X44 cabinet. The type of mechanism that the cabinet contains can be
identified by the top cover configuration as shown in Figure 5-1. The cabinet with the type A release
has filler strips located at the rear of the unit. The cabinet with the type B release has a one piece top
cover.

A
IYPE
FILLER STRIPS

TYPEB

ONE PIECE CABINET

CABINET
TOP COVER

TOP COVER

\
CABINET
REAR

CABINET
REAR

TK-5641

Figure 5-1

PDP-11X44 Cabinet Type Identification

5-1

5.1.1

Mounting Box Removal

To remove the BA11-AA, -AB mounting box from the PDP-11X44 system cabinet, perform the follow-

ing procedure,
l.

Open the rear door of the cabinet. Use a 4mm (5/32 in) hex wrench to release the door fastener.

Remove the ac power from the power controller by setting the circuit breaker in the down (0)
position (Figure 4-20).
Remove the BA11-AA, -AB power cord plug from the nonswitched receptacle at the rear of

the power controller.
Cut or release any fasteners used to secure the power cord to the cabinet frame.
If the release mechanism is type A (Paragraph 5.1), insert the blade of a small screwdriver
into the hole behind the slot which is located at the top, right side of the front bezel.
a.

Release the latch which holds the mounting box by sliding the screwdriver in the direction shown in Figure 5-2.

Raise the front of the mounting box until the unit is approximately at a 45° angle with
the top of the cabinet.

Loosen the four (10-32) screws which hold the cover brackets to the left and right sides
of the mounting box (Figure 5-3). Do not remove the screws.

d.
e.

Remove the top cover.
Lower the front of the mounting box until it is in the normal position and the latch engages.

If the release mechanism is type B, remove the screw (10-32) that secures the top cover
ground lead to the back of the cabinet frame (Figure 5-4).
a.

Use a slot head screwdriver to release the two captive screws that secure the back of the
top cover to the cabinet.
Raise the back of the top cover so the pins are released from the spring latch at the front
of the cover.

Remove the top cover.

Disconnect all bus and 1/O cable connectors attached to the modules within the unit.

At the rear of the BA11-AA, -AB box, remove and retain the two 1/4 inch nuts used to secure the cable clamp bar to the power supply (Figure 4-20).

5-2

Remove the cables from the cable trough in the BA11-AA, -AB mounting box and feed the
cables toward the back of the cabinet and away from the mounting box.
10.

If the release mechanism is type A, release the latch (Figure 5-2) and raise the front of the
mounting box.

If the release mechanism is type B, locate the left and right slide latches on the angle
brackets attached to each side of the BA11-AA, -AB mounting box (Figure 5-5).
a.

Raise the front of the mounting box to the maintenance position shown in Figure 5-6 and
raise the safety lever to hold the mounting box.

}
]|

RELEASE

DIRECTION

.|
1
C
| | m—
—JI
3
C I JCJC
-~

| —

(
11— JC—JC__JC
1
o
Jr—JC _Ji.J

12.

Slide the latches, in the direction shown, to release the latch from the holding pin.

| m—

11.

TK-3458

Figure 5-2

PDP-11X44 Type A Cabinct Mounting Box Release Lever

5-3

LEFT COVER
BRACKET

SCREWS
(10-32)
2 PLACES

(EACH SIDE)

TK-4396

Figure 5-3

PDP-11X44 Top Cover Mounting (Type A)

CABINET
TOP

CABINET
TOP COVER

GROUND
LEAD

REAR
DOOR

COVER

CAPTIVE
SCREWS

——— SCREW

(10-32)

[
TK-5639

Figure 5-4

PDP-11X44 Cabinet Top Cover Mounting (Type B)
5-4

WARNING

When the gas springs are removed, the safety lever
cannot support the weight of the BA11-A mounting
box. The box should be supported by a field service
person while servicing is continued.
13.

Remove the retaining clip from the upper ball connectors of the gas spring on the left and

right interface bracket (Figure 5-7). Use needle-nose pliers to help the clip removal.
14.

Remove the retaining clip from the lower ball connectors of the gas spring on the left and
right side of the cabinet.
Support the mounting box.

LEFT

SLIDE LATCH

HOLDING
PIN

{

15.

g
=

]

1o RELE

RIGHT
SLIDE LATCH

FRONT

TK-5638

Figure 5-5

PDP-11X44 Cabinet, Slide Latch Locations
5-5

16.

17.

Remove the ball connectors from the studs on the right side of the cabinet by inserting a
screwdriver blade between the ball connector and the ball stud mounting surface.
Remove the ball connectors from the studs on the left side of the cabinet using the procedure

described in step 16,
18.

At the rear of the cabinet remove the four 10-32 screws and washers (two on each side near

the top of the mounting box facing toward the center of the cabinet) which secure the pivot
bracket to the cabinet frame on the left and right side of the cabinet (Figure 5-7). These
screws can not be reached once the box is lowered.
19.

At the front of the cabinet, while supporting the weight of the box, lower the safety lever, and
lower the mounting box to its normal position (Figure 5-6).

NOTE
When the gas springs have been removed, the mounting box is not properly supported. If not properly
supported, it can fall causing ‘possible personal in-

jury.

20.

At the rear of the cabinet, remove and retain the two 10-32 screws and washers on the left
and right side of the cabinet which secure the pivot bracket to the mounting box (Figure 5-7).

21.

Grasp the bottom of the mounting box at the front and rear and gently slide the box toward
the front of the cabinet. Lift the back of the mounting box and slide the box forward and
away from the cabinet frame.

BA11-AA, —AB
MOUNTING BOX

RIGHT GAS
SPRING

///

NN
N

Figure 5-6

SAFETY
LEVER

PDP-11X44 Cabinct Safety Lever

5-6

CAUTION

Removal of the mounting box requires two people
due to its weight, with one person lifting from the
left side and one person lifting from the right side of
the cabinet.

BA11-AA, —AB

SCREWS

MOUNTING BOX

(10-32)
2 PLACES

(EACH SIDE)
MOUNTING

SCREWS

BRACKET

- INTERFACE
BRACKET

| GAs

(10-32)
PLACES
2(EACH
SIDE) /

EFT

LEFT

SPRING

f—

MOUNTING SCREWS

RIGHT

(ONE ON EACH SIDE)

PIVOT

BRACKET
PISTON

BALL

CONNECTOR

PISTON

ROD

\
RETAINER

CLIP

BODY BALL

CONNECTOR

(NOT SHOWN

}
TK-3469

Figure 5-7

PDP-11X44 Cabinet Mounting Box Hardware
5-7

S5.1.2

Interface Bracket Removal /Installation
If the mounting box to be installed does not have the interface and pivot bracket mounted on each side,
remove the brackets from the box to be replaced and install using the following procedure.

Using a 1/2 in open- or box-end wrench, remove the two 5/16-24 bolts and the 5/16-24 ball
stud located on the left and right side of the mounting box (Figure 5-8).

‘

Remove the two bracket assemblies and, using the hardware previously removed, install onto

the left and right side of the replacement mounting box. Do not tighten bolts.
3.

Align the top of the interface bracket parallel with the top of the mounting box and at the

dimension shown in Figure 5-8.
4.

Tighten the two 5/16-24 bolts and the ball stud.

PIVOT

11.18 CM

INTERFACE

BRAC§ET

(.44 IN) ‘l

BRACKET

o] T/

BOLTS

(5116241

/2 PLACES
/

BALL (5/16
— 24)
STUD

BA11-AA, —AB
MOUNTING BOX

(LEFT SIDE)
TK-4398

Figure 5-8

Interface Bracket Mounting

5.1.3
Mounting Box Replacement
Perform the following procedure to install the BA11-AA, -AB mounting box in the PDP-11X44 system
cabinet.
CAUTION
Installation of the mounting box requires two people
due to its weight, with one person lifting from the

left side and one person lifting from the right side of
the cabinet.
1.

Grasp the bottom of the mounting box at the front and rear and position the box on the support rails (see Figure 4-4) with the front of the unit extending away from the front of the

system cabinet.

5-8

Slide the mounting box toward the rear of the unit while lifting the rear of the box to clear

the ball stud (Figure 5-8).

At the rear of the cabinet, install the two 10-32 screws and washers, removed in step 20 of
Paragraph 5.1.1, in the angle part of the left and right interface bracket (Figure 5-7). Do not

tighten the screws.

WARNING

When the gas springs are removed, the safety lever
cannot support the weight of the BA11-A mounting
box. The box should be supported by a field service
person while servicing is continued.

Raise the front of the mounting box to the position shown in Figure 5-7, raise the stop lever
and hold the mounting box in position.

Replace the two 10-32 interface bracket screws and washers, removed in step 18 of Paragraph 5.1.1, into the left and right cabinet frame (Figure 5-7).
NOTE

It may be necessary to shift the position of the
mounting box in a direction that will cause the holes
of the interface bracket to be properly aligned with
cabinet frame holes.

Tighten the screws installed in step 5.

Replace both gas springs, removed in Paragraph 5.1.1, snapping the lower ball connectors on
first and then the upper ball connectors.

Install the four retaining clips removed in Paragraph 5.1.1.

Lower the stop lever and lower the mounting box to its normal operating position.
10.

Route the cables removed in step 9 of Paragraph 5.1.1 through the cable trough.

11.

Insert the cable connectors removed in step 7 of Paragraph 5.1.1.

13.

Install the cable clamp removed in step 8' of Paragraph 5.1.1.
Release the moufiting box latch as described in steps 5 and 6 of Paragraph 5.1.1.

14.

Raise the front of the mounting box as described in steps 5 and 6 of Paragraph 5.1.1.

15.

Install the top cover onto the mounting box and tighten the screws which were released in

12.

16.

5.2

step 5 or 6 of Paragraph 5.1.1.

Lower the front of the unit to its normal operating position and engage the latch.

BA11-AA, -AB SLIDE MOUNTED REMOVAL/REPLACEMENT

Refer to Chapter 4 for the installation of the BAI1-AA, -AB mounting box on slide assemblies.

5-9

5.3 FAN ASSEMBLY
The fan assembly is installed on the right side of the BA11-AA, -AB mounting box and
can easily be
removed for servicing. The assembly contains three fans, each of which can be removed
and replaced.
5.3.1

Fan Assembly Removal/Replacement
Perform the following procedure to remove the fan assembly and fans.
1.

Remove the ac power from the BA11-AA, -AB mounting box by removing the ac power
cord
plug from its receptacle.

2a.

In the PDP-11X44 system cabinet, perform steps 5, 6 and 11 of paragraph 5.1.1.

2b.

If the mounting box is installed on slides in a cabinet, insert a screwdriver blade into
the hole
behind the slot which is located at the top, right side of the front bezel (Figure 5-9).
Release the latch which holds the mounting box by sliding the screwdriver in the

shown.
4a.

4b.

In the PDP-11X44 system, raise the front of the mounting box to its maintenanc
e position
and raise the safety lever (Figure 5-6).

If the mounting box is installed on slides, pull the front of the box until the slide hold

are engaged (Figure 4-13).

levers

RELEASE

]

)[

DIRECTION

W'
e
J L
J LI
I
E—
[
] |
JL

JL__JL __JC_JC—ac

Release the pawl retractors on each side of the mounting box and tilt the box 90°
to the
maintenance position.

4c.

direction

TK-3458

Figure 59

Mounting Box Release Lever

5-10

Remove the two 6-32 screws which secure the fan assembly to the side of the box (Figure 510).

Slide the fan assembly away from the side of the box approximately 5 cm (2 in) and dis-

connect connector P1 from J1.

Continue to slide the assembly away from the box.
NOTE

Any of the three fans can be replaced by disconnecting the power plug on the fan and removing
the four 6-32 mounting screws which secure the fans
to the slide. Use only the specified replacement fan
and mount the new fan to assembly using the hardware removed.

FRONT

‘

CABINET

RAIL

eoe/%%000fc0oppo
0 —

BA11 MOUNTING BOX *

SCREWS
(6-32)
2 PLACES
POWER

CONNECTOR
P1/J1

* SLIDE MOUNTED UNIT SHOWN.
FAN ASSEMBLY MOUNTED IN A

SIMILAR MANNER IN THE

PDP-11/X44 SYSTEM CABINET.

Figure 5-10

TK-4399

Fan Assembly Removal
5-11

To replace the fan assembly, perform the instructions described in steps 5, 6, and 7 in the
reverse order and reset the mounting box in its normal operating position.

NOTE
The slide holding levers (Figure 4-13) must be released by pressing inward before the slides will retract.

5.4
HT7140-AA, -AB POWER SUPPLY REMOVAL/REPLACEMENT
Before removing the power supply assembly from the mounting box, remove the power cord plug
of the
power supply from the ac power distribution connector. To remove and replace the power
supply, perform the following procedure.

5.4.1

Power Supply Removal

From the rear of the cabinet, remove and retain the two 8-32 screws located in each of the
two chassis angles at the rear of the mounting box (Figure 5-11).
Perform steps 1 through 4 of Paragraph 5.3.1

Remove and retain the four 6-32 screws that secure the bottom cover to the mounting box
(Figure 5-12). Remove the cover.
Remove and retain the four 6-32 screws that secure the cover plate to the bottom of the power supply assembly. Remove the cover.
Remove and retain the 10-32 screw that secures the ground lead to the ground bus (Figure 5-

13).

Loosen the two 3/8 in nuts on the clamp that holds the ground flex print cable to the ground
bus bar.

Loosen the two 3/8 in nuts on the clamp that holds the +5 V flex print cable to the +5 V
bus bar.

Slide the ground and +5 V flex print cables away from the clamps and bend up toward the
backplane.
Remove the power flex print connector P1 from power supply connector J11 and bend up
toward the backplane.
10.

Remove connector P3 of the CIM cable assembly from connector J1 of the power supply.
Move the tabs on each side of J1 to releasc P3 (Figure 5-14).

11.

Remove the 3/8 in nut that secures the ground lead of connector P3, removed in step 10, to
the chassis ground stud.

12.

If one or more additional backplanes arc mounted in the box, remove the connectors attached
to J2, J3 and J4 of the power distribution board. Remove the backplane connectors from P2,

P3 and P4 of the power distribution harness.

5-12

N EXN
ChelcX

(

SCREW /

(8:32)

00®4eee® 0000000000 (@

e
)

(SR

2 PLACES

le——m

2 PLACES

|~ (8:32)

000000000000 000000000000000x ®Ie AN

TK-4400

Figure 5-11

Power Supply Assembly, Rear Mounting Screws

BA11-A

MOUNTING BOX *

/ FRONT

CABINET

[6600] 0000 ca

RAIL

BOTTOM COVER

SCREWS (6-32)

[-N-N-)

4 PLACES

&
‘

(632

POWER SUPPLY

]

SCREWS

H7140 AA—AB

s\\

COVER PLATE

SCREW (6-32)
4 PLACES

(EACH SIDE)
g

%MOVE
T

NOTE:

SLIDE MOUNTED VERSION OF THE
BA11-A BOX IS SHOWN. THE
PDP-11X44 SYSTEM CABINET
VERSION IS SIMILAR.
TK-4401

Figure 5-12

Power Supply Assembly Removal

5-13

13.

In a slide mounted installation, remove and retain the 8-32 screws located on each side of the
mounting box, toward the rear (Figure 5-12).

14.

In a PDP-11X44 installation, remove and retain the 8-32 screws located on each side of the
mounting box, toward the rear (Figure 5-7).
CAUTION
The H7140 power supply assembly will tend to slide
forward when the screws in step 14 are removed.

BEZEL PC BOARD
FRONT

PANEL

| 3

TU58

’

eI,

® e

C1M

fi (M9070)

/E.

CONSOLE

ciM —=1CABLE

ASSY

TERM

’

KD11-2

-+~ BACKPLANE

/—POWER FLEXPRINT CABLE

FAV‘\\‘IEA;SY

/-GROUND FLEXPRINT CABLE

CABLE

(J2 AND J3
NOT SHOWN)

/—+5V FLEXPRINT CABLE

———GROUND
LEAD

T~ SCREW

/
J4

(10-32)

GND

CABLE

9.5 MM (3/8
IN)

2 PLACES

CONNECTOR
P1/J11

Figure 5-13

TK-3641

Power Lead Connections

5-14

Slide the power supply assembly forward approximately 5 cm (2 in) and disconnect the fan
assembly power cable shown in Figure 5-13 from connectors J2 and J3 (not shown) on the

15.

power supply PC board.

Slide the power supply assembly from the mounting box (Figure 5-12) and away from the

16.

cabinet.

Power Supply Replacement

5.4.2

With the mounting box in the maintenance position, slide the power supply into the mounting
box chassis.

NOTE

When the power supply assembly is being inserted,
check that the 1/0 and bus cables are properly positioned and do not interfere with the power supply installation. Before the supply is fully inserted, connect the fan assembly power leads that were removed
in step 15 of Paragraph 5.4.1.

Replace the 8-32 screws removed in step 13 or 14 of Paragraph 5.4.1.

Replace the backplane connectors removed in step 12 of Paragraph 5.4.1.
H7140-AA, -AB POWER SUPPLY UNIT

NUT

9.56 MM

(3/8 IN)

\S—

/4]

TK-4405

J2
P4

Figure 5-14

Power Distribution Panel and Connectors

5-15

Replace the ground lead removed in step 11 of Paragraph 5.4.1.
Replace connector P3 removed in step 10 of Paragraph 5.4.1.
Replace the power flex print cable connector removed in step 9 of Paragraph 5.4.1.

Replace the +5 V and ground flex print cables removed in steps 8, 7 and 6 of Paragraph
5.4.1.
Replace the ground lead removed in step 5 of Paragraph 5.4.1.

Replace the cover-plate removed in step 4 of Paragraph 5.4.1.
10.

11a.

Replace the bottom cover removed in step 3 of Paragaraph 5.4.1.
In the PDP-11X44 system, release the safety lever and lower the mounting box and engage

the latch.
11b.

If the mounting box is installed on slides, release the slide hold levers on each side slide rail

and slide the mounting box into the cabinet until the front latch engages.
12.

From the rear of the cabinet, replace the four 8-32 screws removed in step 1 of Paragraph
5.4.1.

5.5 OPTIONAL BACKPLANE ASSEMBLIES
Two types of backplane assemblies are available for installation in the BA11-A mounting box. The
DD11-CK backplane is a single system unit and the DD11-DK is a double system unit. The backplane

assemblies are shown in Figure 5-15 and consist of module connector blocks that are mounted in a met-

al frame. The connector block pins are prewired for the PDP-11 bus signals and for the dc power and
ground. Table 5-1 lists the slot columns and rows available in each backplane.
The backplane assemblies are installed within the mounting box in the area adjacent to the CPU backplanc. The dc power is supplied to the backplane through a wire harness and connectors that mate with

the power supply connectors. Table 5-2 lists the maximum number of each type of backplane which can
be installed.

Table 5-1

Opti‘onal Backplane Assemblies

Designation

Type

Slot Columns

Rows

DDI11-CK

Single

Modules

2 quad-hcight and

2 quad/hex-height
DDI1-DK

Double

2 quad-height and
7 quad/hex-hcight

5-16

€d— ® — --

ln_lm®|=]=|s)—||=10—71Ss1
- ®

5-17

Table 5-2

5.5.1

Backplane Assembly Types

Option Number

Total Slot Columns

One DD11-DK

One DD11-CK and
One DD11-DK

Three DD11-CK

Optional Backplane Configurations

Figure 5-16 shows three configurations of the DD11-CK (4 slot) and DD11-DK (9 slot) backplanes
installed in the mounting box.
5.5.2

Backplane Assembly Installation

To install the DD11-CK or DD11-DK backplane assembly, perform the following procedures.
1.

In the PDP-11X44 system cabinet, perform steps 1 through 3 and steps 5 through 9 of Paragraph 5.1.1.

2a.

If the mounting box is installed on slides, insert a screwdriver blade into the hole behind the
slot which is located at the right side of the bezel (Figure 5-9).

2b.

Pull the front of the box until the slide hold levers are engaged (Figure 4-13).

2C.

Release the pawl retractors on each side of the mounting box and tilt the box 90° to the
maintenance position.
Remove and retain the four 6-32 screws that secure the bottom cover to the mounting box
(Figure 5-12). Remove cover.
Remove and retain the four 6-32 screws that secure the cover plate to the bottom of the power supply assembly. Remove the cover.
Position the backplane assembly on the mounting rails so that the tapped holes in the rails are
aligned with the backplane mounting holes (Figure 5-17).
NOTE
The backplane harness includes a ground lead with a

lug attached which must be installed
mounting screw.

under the

Install the four 8-32 screws that are supplied with the backplane assembly. Do not tighten the
SCrews,

Lower the mounting box to its normal horizontal position and insert a hex-height module into
the module guides that are aligned with the slot columns on each side of the backplane assembly (Figure 5-18).

NOTE

The backplane assembly can be shifted in position to
enable the module connectors to be properly aligned
with the module slots.
5-18

Raise the mounting box to the maintenance position and tighten the four 8-32 screws that

were installed in step 6.

Install the backplane wiring harness connectors P2, P3 and P4 into the power distribution
connectors J5, J4 and J6, respectively. For the DD11-CK backplane assembly, install connector P2 and P3 into connectors J5 and J4, respectively (Figure 5-14).

—

4-SLOT

9-SLOT

CPU BACKPLANE

iT
::::::::::

"
(

=
T+

T 4.sLoT

‘\‘N

& 9-SLOT

CPU BACKPLANE

4-sSLOT é
CPU BACKPLANE

TK-3467

Figure 5-16

Optional Backplane Configurations

5-19

10.

Replace the bottom cover and cover plate removed in steps 3 and 4.

11.

Lower the mounting box to its normal operating position.

12.

Remove the hex modules used for alignment in step 7.

13.

Install the UNIBUS jumper module, SPC modules and UNIBUS terminator modules.

14.

In the PDP-11X44 system cabinet, perform steps 15 and 16 of Paragraph 5.1.3.

15.

In the PDP-11/44 slide mounted system, replace the top cover of the mounting box using the
four 6-32 screws.

DD11-DK 9 SLOT—-COLUMN
BACKPLANE
14 SLOT—COLUMN

CPU BACKPLANE

SCREWS
(8-32)
4 PLACES

GROUND
LUG
e
—

P4/J4-

P3/43

P2/J2

TK-4403

Figure 5-17

Backplane Assembly Mounting
5-20

Cmm

~>—IN WWW%&
HEX MODULE

COMPONENT SIDE
FRONT

GUIDE

(RED)

REAR GUIDE

(BLACK)

SYSTEM UNIT

TK-4404

Figure 5-18

5.5.3

Backplane Assembly Alignment

Backplane Connector Assignments

The connectors in the backplane are classified into three categories: standard UNIBUS, modified

UNIBUS, and small peripheral control (SPC) connectors. Particular areas of the backplane are re-

served for the different types of connectors as shown in Figure 5-19.

The standard UNIBUS connectors contain all the UNIBUS connections. Sections A and B of slot 1 are
the beginning of the UNIBUS in the DD1-CK and DD11-DK and should be occupied by the BC11-A
UNIBUS cable since they are expander backplanes. Sections A and B of slot 9 in the DD11-DK or of
slot 4 in the DD11-CK are the end of the UNIBUS on the backplane. These sections should be occupied by the BC11-A UNIBUS cable or a terminator module.
5-21

DD11-CK BACKPLANE
ROW
A

‘

1 \

z ?
5 3
Q

/ /|

QUAD

—HEIGHT

MODULE

DD11-DK BACKPLANE

QUAD

TR
sl

Y S

QUAD HEIGHT

L HEIGHT

MODULE

S—

ORHEIGHT
HEX
MODULE

QUAD OR HEX-HEIGHT

MODULES

8
4

L QUAD HEIGHT MODULE
MODULE SIDE

NNy
STANDARD UNIBUS

SLOTS

Sdn

MODIFIED UNIBUS

SMALL PERIPHERAL

SLOTS FOR MODIFIED

CONTROLLER (SPC) SLOTS

UNIBUS DEVICES (MUD)

Figure 5-19

Optional Backplane Slot Assignments

3.5.4
NPG and BG Jumper Lead Routing
The NPG line is the UNIBUS grant line for devices that perform data transfers without processor in-

tervention. Continuity of the NPG line is provided by wirewrap jumpers on the backplane. When an
NPR device is placed in a slot, the corresponding jumper wire from pin CA1 to pin CB1 of that slot
must be removed. The routing of the NPG signal through the backplane is shown in Figure 5-20. Grant

priority decreases from slot 1 to slot 9 in the DD11-DK (slot 1 has the highest priority and slot 9 has the
lowest).
NOTE
If an NPR device is removed from a slot, the jumper
wire from CA1 to CB1 must be reconnected.

The bus grant lines (BG4:BG7) for devices requiring processor intervention during data transfers are

routed through each small peripheral control section in slot D. Each of the four grant signals is routed
on a separate line. Grant priority for each level decreases from slot 1 to slot 9.
NOTE
A bus grant jumper card (G727 G7270, or G7273)
must be placed in connector D of any unoccupied

SPC section. If an SPC section is left open, bus
grant continuity will be lost.

5-22

ROW

A
AU1 @~

AU1 L

CA1 /831

SLOT NO.

REMOVABLE WIRE WRAP

TK-4407

Figure 5-20

5.5.5

NPG Jumper Leads Routing

Standard and Modified Backplane Locations

Figure 5-21 shows the pin designations of the standard and modified UNIBUS connectors. The modificd UNIBUS differs from the standard UNIBUS in that certain pins have been redesignated. Some
ground connections, BUS GRANT signals, and the NPG signal have been removed from the modified
UNIBUS and have been redesignated with core memory voltage pins, battery backup voltage pins for
MOS memory, parity signal pins, several reserved pins, and test point pins.

Dual-height modules that ére standard UNIBUS compatible must not be placed in the modified

UNIBUS sections.
5.5.6

SPC Backplane Locations

The small peripheral control sections (C, D, E and F) collectively contain all the UNIBUS lines as well
as power voltages (+5 V, +15 V, —15 V). These sections can be used by hex-height or quad-height
modules containing the control logic for peripheral devices. Figure 5-22 shows the pin designations for
the SPC connectors.

5.5.7

Backplane Power Connections

Power is supplied to the backplane via a wire harness that connects to the power distribution board with
the power supply. The wires run from the backplane to a set of Mate-N-Lok connectors that run

directly into the distribution board.

The power harness from the DD11-DK contains two large connectors (15-pin Mate-N-Lok) and one
small connector (6-pin Mate-N-Lok). The DD11-CK backplane has only one 15-pin connector and one
6-pin connector. The connector pin locations are shown in Figure 5-23 and the signal assignments for
each pin are listed in Table 5-3 (DD11-CK) and Table 5-4 (DD11-DK).

5-23

STANDARD UNIBUS

MODIFIED UNIBUS

PIN DESIGNATIONS

SIDE

|+5v

|BG6

INTR|GND

|BG5

INnIT

PIN\]

+5V

INIT|

+5V

|RESV|

+5V

GND

INTR]

[RESV|

¢
[»)

D02

|pot1

BR4

Do4

|[D03

D06

|DO5

L
Do8

|GND

|toL

[Do7

[A01

A00

|[A03

A02

D12

|D11

|A0S

A04

D14

|D13

|AO7

A06

|D15

|A09

A08

|PB

|A11

A10

|BBSY|

A13

A12

|sAck|

A15

| A14

GND
P

d
GND

y |

GND

|[NPR | A17

S
GND

|BR7

|GND

L
|BR6

|sSYN

)

BG?

|GND

D04 | D03 | INT

|[PAR

L | L

[SSYNgDET

[ACc

|DC

{LoL|Lo L

pog | bo7 | A01
L

| A0O

D12 | D11]
K

R
S

| co
)

| D15|

PAR|

L
L

| A11 | A10

+15

|SAck]|

A09 | AO8

|BBSY|

A07 | AOD6

PAR

oleatd

A05 | A04

D14 | D13]|

D10 { D09 | AO3 | AO2

A13 | A12
L

A15 | A14

| NPR | A17 | At6

BAT‘

GND | BR7

|GND |

L
J(+2°'

BR6

{CORE}

L
|[SSYN|

[MSYN | GND

NOTE: D INDICATES A REDESIGNATED PIN.
Figure 5-21

| BR4

|{BAT

NPG

A16

Do2 | po1 | +5

Do6 | Dos

|AC

|D09

GND

BG4

c D00 | GND | BRS | GND

|GND

D10

GNDfl

D00 |GND |BRS

Standard and Modified Backplane Pin Assignments

5-24

TK-4402

ROW

SIDE
PIN

NPG

+5V

ABG

-15V

ouT

ASSYN | -15V

IN H
A SEL

| GND

D15

A OUT | BR7

D14

A SEL

| BR6

D13

A12

ABG

A SEL | BR5

-16V

IN
GND

SSYN

GND

A17

A15

BBSY

FO1

D02

MSYN

| A16

FO1

A02

D05

D06

D11

D12

A IN

B8R4

A01

A00

D07

A INT

ENB B

A INT

D10

SSYN

NPR

GND

A SEL |

D09

AINT

D08

ENBB

ABR

ouT

A OUT | BG7

A14

A13

D08

AINT

INIT

B8G7

All

D03

FO1

ouT

D07

AINT

BG6

AIN

ENBA

D04

A INT

BG6

AOUT | A0S

ouT

LOW

BG5S

A10

BG5S

HALT

D05

REQ

HALT

D01

GRT

D00

GND

DO3

GND

L
AC

D06 | ASSYN

IN H

L
AOUT | INTR

L2
FO1

FO1

D04

AO07

ABR

FO1

ouT

A09

ASEL

FO1

ouT

BG4

ASEL

FO1

BG4

GND

ASEL

GND

SACK

ABG

A06

A04

A INT

ABR

ouT

ABG

AQ05

A03

A INT

FO1

ouT

HIGH

ouT

+15/+8 | D02

GND

+5V

LOwW

-15Vv

GND

LTC

(OUT)
PA

(IN)
NPG

ENB A | FO1
TK-4410

Figure 5-22

SPC Backplane Pin Assignments

5-25

PIN SIDE

6 |

O O’P 4 6

9 \NLO
o ©o) O/r/
OMVT
\

WLO O Of |13

ey "

m © O*C‘#

L\O (]}
o Oj \\KEY
-

6 PIN CONNECTOR

155,

KEY/V

|10

OfF

KEY

15 PIN CONNECTOR

Figure 5-23

Table 5-3

Backplane Power Connector Pin Designations

Power Connector Signal Assignments for DD11-CK

Signal

Wire Gauge

Color

15-Pin Mate-N-Lok Connector

1
2

45V
+15V

14
18

Red
Gray

4
5

+20V

Orange

+5V
Spare (not connected)

14
—

Red
—

+15B

Green

7
8
9
10
11
12
13
14
15

Ground
Ground
Spare (not connected)
Spare (not connected)
Spare (not connected)
+5B
—15V
-5V
—15B

14
14
14
18
18
18

Black
Black
—
—
—
Red
Blue
Brown
White

6-Pin Mate-N-Lok Connector

]
2

14
18

LO GND
LTC (line clock)
DCLO

Violet

4
5

ACLO
Spare (not connected)

18
-

Yellow
-

Spare (not connected)

—

5-26

Black
Brown

Table 5-4

Power Connector Signal Assignments for DD11-DK

Wire Gauge

Signal

Color

15-Pin Mate-N-Lok Connector 1

1
2
3
4

14
18
14
14

+5V
+15V
+20V
+5V

Red
Gray
Orange
Red

5
6
7

Spare (not connected)
Spare (not connected)
Spare (not connected)

—
-

—
—
~

10
11

Spare (not connected)
Spare (not connected)

—
—

Spare (not connected)

—

Spare (not connected)

—

8
9

12
13

14
15

14
14

Ground
Ground

+5B

-5V

Black
Black

Red
Brown

15-Pin Mate-N-Lok Connector 2

+5V

Red

Spare (not connected)

—

10
11
12

Spare (not connected)
Spare (not connected)
Spare (not connected)

—
—

—
—
—

Spare (not connected)

—

3
4
6
8
9

+20V
+5V
+15B

Ground
Ground

—15V

—15B

14
14
18
14
14

Orange
Red
White
Black
Black

Blue

Green

6-Pin Mate-N-Lok Connector

1
2
3
4
5
6

:
LO GND
LTC (line clock)
DC LO
ACLO

Spare (not connected)
Spare (not connected)

18
18
18

—
—

5-27

Black

Brown
Violet
Yellow
-

CHAPTER 6
DETAILED FUNCTIONAL DESCRIPTION

6.1

INTRODUCTION

This chapter describes the major logic elements of the KD11-Z central processor used in the PDP-

11/44. References to pages in the print set are made in the figures and text where applicable.
6.2 CONTROL STORE
Execution of each PDP-11 instruction requires the performance of a sequence of operations. The sequence is controlled by the microprogram contained in the PROM control store (K2-6,7,8,13). The
KD11-Z control store provides storage for 1K of 56-bit microinstructions. Every microinstruction comprises 23 fields which control particular functions in the processor. Figure 6-1 illustrates the format of
the KD11-Z microinstruction and the significance of each field value.
6.2.1

MicroPC Generation

The address of the current microinstruction (microPC) can be generated from a number of sources.
Refer to Figure 6-2. The two major sources of the microPC lines (K2-6 MPC 10:00 H) are the central
processor and the console processor. The signals from the central processor and console processor are
wire ORed but only one group of signals is enabled at any particular time.

The console processor can generate a particular microPC by writing the address onto the PAX data bus
and generating K3-2 MFM LOAD MPC L. This signal clocks the PAX data bits into a flip-flop and
enables that data onto the MPC lines (K2-6 MPC 10:00H). In addition, the console processor can read
the current microPC via the PAX data bus by generating K3-4 FORCE CPU MPC L.
Under normal conditions, the central processor generates the address of the microinstruction. The signal K3-2 MFM LOAD MPC L is false and the CPU MPC line drivers are enabled by the signal K2-9
ENAB CPU MPC L. The next address field (CS 00:10) of the current microinstruction will specify the
microPC. Control store bits 00:10 generate MPC bits 10:00, respectively. However, several signals are
wire ‘'ORed with the MPC lines to enable branching at specific points within the microprogram.
Branches are enabled in the following situations.
Branch on Micro Test — The BUT ENABLE field of the microinstruction (CS 36:39) selects certain
signals or groups of signals to be ORed with MPC bits 07:00. The microPC will be altered to reflect the
status of those signal lines being tested.

Instruction Decode — The instruction decode logic generates signals which are wire ORed with MPC
bits 07:00. When enabled, the instruction decode logic can cause branching within the microprogram.
The microbranch address will depend on the instruction, mode, and operands specified.
Power Restart — Power restart will force the MPC lines to be cleared by an initialize signal (K2-11
PROC INIT H). The power up circuit (K2-2) will then enable MPC bit 00, forcing the processor to

perform the power up routine beginning at microprogram address 001.

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Trap Decode — The processor enters the service microstate when CS bit 42 is enabled (K2-8 BUT SERVICE 1 (H) is generated). The service logic (K2-2) can then monitor various trap conditions and enable
MPC bit 00. This causes a branch to a microroutine which initiates an error macroroutine. The error
routine pushes and pops the PC and PSW on or off the processor stack.
6.3

DATA PATH

The data path (Figure 6-3) provides the logic required for arithmetic and logic processing (ALU), shifting of 8, 16, and 32-bit data formats (ALU B-leg logic), byte swapping and sign extention of data
(SSMUX), storage of general register data (scratch pad memory), and storage of status information
(processor status word). The following paragraphs describe each major element of the data path.
6.3.1
Arithmetic Logic Unit (ALU)
The ALU (Figure 6-4) is the main processing element of the data path. It performs arithmetic (with full
carry look-ahead) or logic operations on 16-bit operands. The ALU is physically divided into four 4-bit
slices (K1-1 through K1-4). Operations performed by the ALU are specified by the ALU/BLEG
CTRL field (CS 18:22) of the current microinstruction or by the auxiliary control logic.

When bit 23 of the microinstruction equals 1, the signal K2-7 AUX CONTROL (1) H is generated and
the auxiliary ALU control PROMs (K2-4) are enabled. The ALU operation will then be a direct function of the current PDP-11 instruction being executed. Refer to the auxiliary control description. If the
auxiliary control bit (CS 23) is not set, the ALU function is defined explicitly by CS 18:22, as shown in
Figure 6-1.
’
The data sources for the A input of the ALU are the scratch pad memory and KT multiplexer (KT
MUX). These sources are wire ORed to generate the signals SP 15:00 (1) H. The internal address de-

code logic (K1-10) generates K1-10 ENAB KT MUX L which enables the KT MUX and disables the
scratchpad memory. The KT MUX and scratchpad are thereby prevented from driving the SP lines at
the same time. The data source for the B input of the ALU is the B-leg multiplexer (BMUX). The
BMUX can select the BX register, B register, + 1, or zero. Refer to paragraph 6.3.2.

The data outputs of the ALUl (ALU 15:00 H) are input to one leg of the ALU multiplexer (AMUX)

and the condition code logic (K1-10). The generate and propagate outputs of each ALU slice are input
to the look ahead carry generator. This circuit enables the carry to be anticipated across the four ALU
slices.
6.3.2

ALU B-Leg Logic

The B leg of the ALU (Figure 6-5) consists of three components: the B-leg multiplexer (BMUX), the B
register (B REG) and the BX register (BX REG). Each of these components is divided into four 4-bit
slices (K1-1 through K1-4).

The BMUX selects the data source for the B input of the ALU. The BMUX can select the B REG, BX
REG, or the constants 1 and 0, depending on the value of the BMUX control lines, as follows.
K2-7 BLEG 01 H

K2-7 BLEG 00 H

BMUX OUTPUT (DP BLEG 15:00 H)

BREG 15:00 (1) H

BXREG 15:00 (1) H

EP BLEG 15:01 = 0, DP BLEG 00 =K2-3 PLUS ONE

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SCRATCH

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B
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AUX
ALU
PROMS
-4
(K2-4)

cs 23
FF

ENB
K2-7 AUX CONTROL H

ALU

CS 18:22

CNTR

PROM
(K2-7)
TK-3180

Figure 6-4

Arithmetic Logic Unit

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The constants 1 and O are generated during autoincrement and autodecrement operations. During either operation, if a word instruction is being performed, the specified register is incremented or decremented by two; if a byte operation is being performed, the register is incremented or decremented by
one.

The ALU uses the signal K2-8 ALU CIN L to increment or decrement the A-leg input by one. The Bleg input must provide the constant 1 or O to obtain the correct autoincrement or autodecrement result.
The constant 0 is generated by disabling the BMUX output. The constant 1 is generated by disabling
the BMX output and ORing BMUX bit 0 with the signal K2-3 PLUS ONE H. This signal is true when
the contents of the specified register are to be incremented or decremented by two.
The B REG and BX REG are 16-bit general purpose registers that can be shifted right or left by a
single bit. Both registers can also be parallel loaded with data from the swap sign extend multiplexer
(SSMUX). The BREG and BXREG have separate pairs of mode control lines (Figure 6-5) but they
perform the same functions, as follows.
Mode

Mode

Hold

Contents of register do not change.

Shift Right

Contents are shifted right one bit.

Shift Left

Contents are shifted left one bit.

Parallel Load

Function

Data from SSMUX is loaded into the register and appears at its output.

Each register can be shifted as a 16-bit word or the registers can be combined and shifted as a 32-bit
B REG and BX REG are used in conjunction, the B REG represents the upper 16 bits.

word. When the

The B REG can also be shifted as an 8-bit byte. The signal K1-10 SHIFT IN B H is fed into both serial
shift inputs (SHF RT and SHF LFT) of the B REG. This signal is generated by the B SHIFT multi-

plexer. The B SHIFT MUX can select B REG bit 15, BX REG bit 15, 0, or K2-4 SERIAL SHIFT H
as the serial input for either a right of left shift. To allow the byte shift function of the B REG, bit 07 of
the B REG is loaded with the signal K1-10 SHIFT IN 07 H (generated by the BYTE SHIFT multiplexer). During a byte operation, the BYTE SHIFT MUX selects K2-4 SERIAL SHIFT H to be
directly input into bit 07 of the B REG. During a word instruction, the signal K1-3 B REG 08 (1) H is
input to bit 07.

As previously mentioned, the BX register can also be shifted to the right or left. During a shift right,
the BX register contents are moved one place toward the least significant position and BX REG bit 15
is loaded with B REG bit 00. Thus, for all right shifts, the BX REG represents the low-order 16 bits of
a 32-bit word. During a shift left, the register contents are shifted toward the most significant bit position and BX REG bit 00 is loaded with the signal K1-10 SHIFT IN BX H, generated by the BX
SHIFT MUX. The BX SHIFT MUX can select K1-4 ALU COUT H, the output of the EIS overflow
detection logic (K1-10 OUX (1) H), 1 or O as the serial input for a left shift.

6-9

The shift capabilities of the B register and BX register are used during the performance of a number of
instructions. The following briefly describes the shifting requlrements for the ASL, ASR, ROL, ROR,
ASH, and ASHC instructions.
1.

Arithmetic Shift Left (ASL) — Shifts all bits of the destination left one place. The low-order
bit is loaded with a 0. The C bit of the status word is loaded from the high-order bit of the
destination. ASL performs a signed multiplication of the destination by two, with overflow
indication.
Arithmetic Shift Right (ASR) — Shifts all bits of the destination right one place. The highorder bit is duplicated. The C bit is loaded from the low-order bit of the destination. ASR
performs signed division of the destination by two.

Rotate Left (ROL or ROLB, depending on whether a word or byte operation) — Rotates all
bits of the destination left one place. The high-order bit is loaded into the C bit of the status
word, and the previous contents of the C bit are loaded into the low-order bit of the destination.
Rotate Right (ROR or RORB) — Rotates all bits of the destination right one place. The loworder bit is loaded into the C bit, and the previous contents of the C bit are loaded into the
high-order bit of the destination.
Arithmetic Shift (ASH) — Shifts the contents ofjthe register right or left the number of times
specified by the source operand. The shift count is taken as the low-order six bits of the
source operand. This number ranges from — 32 to +31. Negative is a right shift and positive
is a left shift.

Arithmetic Shift Combined (ASHC) — Treats the contents of the register and register ORed
with one (R+1) as one 32-bit word. R+
1 (bits 15:00) and R (bits 31:16) are shifted right or
left the number of times specified by the shift count. The shift count is taken as the low-order
six bits of the source operand. This number ranges from —32 to +31. Negative is a right
shift and positive is a left shift. When the register chosen is an odd number, the register and
the register ORed with one are the same. In this case, the right shift becomes a rotate. The
16-bit word is rotated right the number of bits specified by the shift count.
NOTE
When R is an even-numbered register, R+ 1 will be
the next highest register. If R is an odd-numbered
register, R+
1 will be the same register. For example, if

R = R4, then R+1 = RS; if

R = RS,

then R+1 = RS.

Figure 6-6 illustrates the operations performed by the shift and rotate instruction.
6.3.3
ALU Multiplexer (AMUX)
The AMUX enables the selection of one of four sources as the input data for the SSMUX. The AMUX

can select data which is external to the processor (K1-5 PAX D 15:00 H) or internal data from the
ALU, PSW, or constants. The AMUX output can also be placed in a high impedance state. This allows

data from the floating point processor or commercial instruction set processor to be input to the data
path via the AMUX lines. The output enable lines of the AMUX are controlled by the console processor on the multifunction module. When the console processor generates K3-4 FORCE CPU DATA L,
the AMUX output is enabled and one of the four AMUX sources can be input to the SSMUX. When
the console processor generates K3-4 FREE BUS H, the signal TRI STATE AMUX L is asserted low
and the AMUX outputs are placed in the high impedance state.
6-10

When the AMUX outputs are enabled, one of the following four inputs will be selected:
PAX data (K1-5 PAX D15:00)
Constant inputs (K2-2 C7:C1 H) used to generate vectors
ALU inputs (ALU 15:00 H)
Processor status word (PSW) inputs

ROR
RORB
WORD:

I§I~*+15 R

¥o

BYTE:

L,‘J oo

] I R

ROL
ROLB
WORD:

IHI'_415 L 1

| I

L 40

BYTE:

[ R
15[

00D

o{c]

418

EVEN

ASR

ASRB

WORD:

- L

R R

144J—41II|_’
)

BYTE:

DLnululE.l.l
15

ODD ADDRESS

EVEN ADDRESS

ASL

ASLB

WORD:

BT
15

BYTE:

el e
e
15

ODD ADDRESS

EVEN ADDRESS

11-3952

Figure 6-6

Rotate Instructions

6-11

6.3.4 Swap Sign Extend Multiplexer (SSMUX)
The SSMUX provides the capability of changing the format of the data before it is output from the
data path or routed to another portion of the data path. The value of the two multiplexer select lines
determine which of the following functions will be performed by the SSMUX.
K2-7 SWAP H

K2-7 SEX H

SSMUX Function

Data is passed through the SSMUX unchanged.

The sign bit of the low byte (K1-2 AMUX 07 H) is ex-

tended into the entire word.
1

The low and high bytes of the word are swapped.

The low and high bytes are swapped and then the sign

bit of the new low byte (previously the high byte) is extended into the entire word.
The SSMUX input comes from the AMUX lines (AMUX 15:00). These signal lines can be generated

by the AMUX or by the floating point or commercial instruction set (CIS) options. The output of the
SSMUX goes to other sections of the data path (PSW, B leg, and scratchpad memory) and to the memory management system. The SSMUX output can also be routed to the rest of the computer system via

the PAX data bus.
6.3.5

Scratchpad Memory

The scratchpad (Figure 6-7) consists of a 16-word by 16-bit random access memory. The scratchpad is

divided into four 4-bit slices, shown on prints K1-1 through K1-4. The 16 scratchpad registers can be
used for temporary storage or as general purpose registers specified during instruction execution. The

following lists the scratchpad registers and their normal use.
Register

Number

Description

RO
R1
R2
R3

General Purpose Registers

R4
RS

Kernel Mode Stack Pointer

Program Counter

Temporary Storage

R11

Unused

R12

Temporary Storage

R13

Temporary Storage

R14

Temporary Storage

R15

Temporary Storage

Rl16
R17

Supervisor Mode Stack Pointer
~

User Mode Stack Pointer

6-12

avd 0:51XNS o H0:€0Vd9L)
< e 1-1)

13s |
v

*L 135 OUS VdS £L-2

6-13

O1Hd2VEN1

68LE-AHL
(9-1 )

The scratchpad address (K2-3 SPA 03:00) is generated by the scratchpad address multiplexer
(SPAM). The SPAM can select one of the following four address sources depending on the value of the
multiplexer select lines;
Physical Address Bus (K1-6 PA 03:00 H)
Instruction Register Source Field (K2-4 IR 08:06)

Instruction Register Destination Field (K2-4 IR 02:00)
Control Store ROM SPA Field (K2-13 ROM SPA 03:00)
Note that scratchpad address R6 is forced to R16 when the memory management system 1s in user
mode and the address is specified by the instruction register or the control store.

The select lines for the SPAM are also generated by a multiplexer. During the first half of the machine
cycle, the signal K2-1 TAP 30 H is not asserted and the multiplexer selects K2-8 SPA SRC SEL 1:0(1)

H as the source for the SPAM select lines. During the second half of the machine cycle K2-8 SPA DST
SEL 1:0 H is selected as the source. These two sources are generated by two fields of the microinstruction: SPA SRC SEL (CS 52:53) and SPA DST SEL (CS 34:35).

6.3.5.1
Scratchpad Operation — The scratchpad registers can be read or written under program control, or the scratchpad memory can be disabled with its output placed in a high impedance state. Since

the scratchpad output is wire ORed with the output of the KT MUX, the scratchpad must be disabled
when the KT MUX is enabled. The output of the scratchpad (SP 15:00 (1) H) is fed into the
A input of
the ALU and the UBA latch. The following descriptions of the read and write operations
assume the
scratchpad memory is enabled (K1-10 ENAB GR L asserted low). Figure 6-8 shows the timing
relationships of the read and write operations.
Read Operation - In a read operation, the scratchpad register is addressed during the first
half of the
machine cycle and the contents of the register are latched on the scratchpad output lines during the

second half of the cycle. When the signal K2-1 EXT TAP 30 H goes low, the output store signal (K1-1
OUTPUT STORE L) goes high. This sets up the scratch pad for a read operation from
the addressed
register. When TAP 30 goes high and output store signal is enabled low, the contents of the
addressed
register are latched on the output of the scratchpad memory (SP 15:00 (1) H). The data can then be
read for the remainder of the machine cycle. The outputs will not be affected by any modification
s to
the SPM address lines until TAP 30 goes low at the beginning of the next cycle.

READ DATA LATCHED
AT SP OUTPUT

r
[

-—

ENAB GR L _—L

SP WRITE L

‘

—_—

[

|
|

REG CLK H (PROC CLK L)

TAP 30 H

SSMUX DATA WRITTEN
INTO SP REG

{

|
READ OPERATION

WRITE OPERATION

SP DEST REG

SP SRC REG

ADDRESSED

|&———— MACHINE CYCLE ——]
TK-3192

Figure 6-8

Scratchpad Timing
6-14

Write Operation — A write operation can occur during the second half of the machine cycle (TAP 30 H
asserted high) if the write enable signal (K1-10 SP WRITE L) is asserted low. On the high to low
transition of the clock signal (K1-1 REG CLK H), data from the SSMUX is loaded into the addressed
scratchpad register. If the instruction is performing a byte operation, bits 15:08 of the scratchpad are
not written.

6.3.6

Processor Status Word (PSW)

The processor status word is a 16-bit register (3 bits are unused) which contains the current and previous memory management modes, an indication of CIS instruction suspension, the current processor
priority, a processor trap bit and the condition code results of the previous operation. The following lists
the name and use of each PSW bit.

Use

PSW Bit

Name

15:14

Memory Management

13:12

Memory Management

11:09

Unused

CIS Instruction

Contain the current memory

management mode.

Current Mode

Contain the previous memory

management mode.

Previous Mode

This bit, when set, indicates

that a CIS instruction has

Suspension

been suspended by an interrupt and must be continued
upon return from the interrupt.
Setting this bit also inhibits a
trace trap.

07:05

Priority

Set the processor priority.

Trace

When this bit is set, the processor traps to the trace vec-

tor. Used for program debugging.

02
01

Set when the result of the last

data manipulation is negative.

Set when the result of the last

data manipulation is zero.

data manipulation produces an
overflow.

Set when the result of the last

data manipulation produces a
carry from the most-significant bit.

6-15

The PSW is composed of flip-flops (Figure 6-9) which are all clocked by K2-1 EXT CLK B L, provided
the proper control signal is enabled. The enabling signals are generated by the control store or the internal address decode PROM. All of the PSW bits can be loaded from the SSMUX. However, the previous memory management mode bits (13:12) and the condition code bits (03:00) can be loaded from
alternative sources via the PSW multiplexer.
When the control store generates K2-8 FORCE KERNEL (1) H the PSWMUX selects
PSW bits
15:14 as the source of the previous mode bits. When the force kernel line is not enabled, the
PSWMUX

selects SSMUX bits 13:12.

When the internal address decode logic generates K1-10 LOAD PSWL, the PSWMUX selects
the
SSMUX as the source for bits 03:00 of the PSW. The condition code bits (K1-10 CC N,Z,V,C)
are
loaded into the PSW only if the address decode does not generate the LOAD PSW line and the
control

store generates the auxiliary control signal (K2-7 AUX CONTROL L).

6.4
INSTRUCTION DECODE
The instruction decode circuitry consists of a set of PAX data buffers which pass the instruction

to the
instruction register where it is loaded on the rising edge of PROC CLK L (K2-4). From the instruction
register, the information is passed to three programmable logic arrays (PLA) and several AUX

control
PROMS where it is decoded and used to generate the next microinstruction (MPC). The three
PLAs
handle the bulk of the instruction decoding while the AUX control is used when the
instruction takes
the form of Y — X OP B or where the microcode does not contain enough information to
properly
execute the instruction.

8SMUX 16:14

[

PSW 15:14

PSW

SSMUX 13:12

13:12

MUX

—

SEL

(K1-4)
K2-8 FORCE KERNEL (1) H

" SSMUX 08

PSW 15:08, 07:00
(K1-3)

SSMUX

07:
07:04
07:04

—

(K1-2)
CCNZV.CH

|psw
MUX

SSMUX 03:00 | SEL
K2-7 AUX CONTROL L

‘-—-\

03:00

(K1-1)

K1-10 LOAD PSW L

TK-3187

Figure 6-9

PSW Logic

6-16

The outputs of the instruction decode PLAs are wire ORed with the microprogram lines (MPC 07:00).
These lines help create the address to the control store. After the control store has been addressed, the
outputs of the control store are latched and routed to the other CPU modules where they control the
operation of the ALU, BUS routing, scratch pad addressing and other base machine functions including
the creation of the next MPC address.

The three PLAs used to decode the PDP-11 instruction set respond to several enabling conditions. Two
of these enabling conditions are signals generated by the control store (K2-6). One signal is K2-4 IR
DECODE (1) H. This signal indicates that the instruction register was loaded in the last microstate and
the instruction is ready to be decoded. The other signal is K2-6 BUT DEST L, which is a microcode
signal that indicates a branch on microtest. When this line is asserted and the instruction remains constant, it allows different microvectors to be asserted using the same instruction. This ability to keep the
same instruction and change the microvector is very useful because it allows one set of micro routines to
service several similar instructions without duplicating microcode. For example, a double operand instruction can be routed through a common fetch routine and, after the operands are fetched, each instruction can be executed by its own handler. Thus, MOV and ADD instructions may have some common microcode.
6.4.1
Instruction Classes
The instructions are loosely divided into three groups with each group being decoded by one PLA.
1.
2.
3.

Double operand and branch instructions
Single operand instructions
Miscellaneous instructions (WAIT, HALT, etc.)

6.4.1.1
Double Operand and Branch Instructions — All branch instructions and most double operand
instructions are decoded by one PLA (K2-5, E116).
Branch Instructions — A branch instruction, along with the status of the condition code bits K1-1 C, V,
Z and N BIT (1) H, will enable the different branches used in the PDP-11 instruction set.
If the branch is true then a vector to microaddress 210 is executed. This vector will create a new PC for
the branch. If the branch fails, the microprogram returns to instruction fetch. When a branch is decoded, signal K2-5 BRNSRV H is generated which creates a pscudo BUT NO SERVE condition. If a
branch is false, this signal helps to decrease the time needed to execute the instruction by allowing the
processor to skip the service state during an instruction fetch if no interrupt or trap is waiting to be
serviced.

Floating-Point Instructions — If the FP11-F floating-point option is installed and input FP11-F ATTACHED L is asserted, all floating-point instructions will be forced to microaddress 50. If the floatingpoint option is not installed, a reserved instruction trap will occur (K2-5 IRCODE 00 L).

Double Operand Instructions — Inputs K2-4 08:15 (1) H, K2-6 BUT DEST L, IR DECODE (1) H, and
destination mode (pin 20, E116) are used to decode double operand instructions. The outputs of the
PLA are wire ORed to MPC 07:03 lines. K2-5 MOV L is asserted if a move instruction is decoded.
Whenever it is desired to place the destination mode of the current instruction on the MPC lines, pin 10

of E116 (K2-5) is asserted, which through its associated logic places the destination mode on MPC line
02:00. PDP-11 instruction source and destination modes are usually brought out in this manner to cause
a microbranch for every mode. The outputs for various double operand instructions are as follows.

6-17

6.4.1.2

=
—_—— (OO

SOB
XOR

ik bt

ASH or ASHC

MPC 7

= e

OooOo—O

MPC 6

MOV (SMO:DMO)
DOP NON-MOD (SMO:DMO)
SUB (SMO:DMO)
MUL or DIV

MPC 5

SO
OO
OO

MPC 4

= O

MPC 3

Instruction Type

Single Operand Instructions — Most of the single operand and some double operand instruc-

tions are decoded on one PLA (K2-5, E115). The inputs and outputs of this PLA are similar to that of
the double operand and branch decode PLA with one exception. K1-4 P.C. USER H is used to detect if

the previous processor mode and the current processor mode in the PSW are both USER. When this
condition is detected, K1-4 P.C. USER H is asserted and provides execute-only protection as acknowledged by the MFPI instruction. An MFPI instruction, which occurs when K1-4 P.C. USER H is asserted, will automatically relocate through D space, thus preventing unauthorized access to program
code.

MPC 4

MPC 5
— 00000
— ——— O

SOP Modify
SOP Non-modify
NEG
Rotate/Shift
JSR
JMP

MARK
SWAB
MFPI (D)
MTPI (D)
*DOP MOD (SMO:DMO)
(ADD, BIC, BIS)

MPC 6
—_—_—,
O OO — =
—

MPC 3

COO—
= — O — O — —

Instruction Type

OC—O0O—O0O0O——~—O0OO

The output for various single operand instructions are as follows.

*Double operand instruction.

CSM
(Call-to-supervisor mode)
HALT

K2-5 CPU HLT RQST L

6-18

0
I

I
1

MPC 3
—O

MPC 2

RESET
RTI/RTT
SET CC
CLR CC
RTS
WAIT

MPC 1

MPC 0

—_—

Instruction

—_o
OO — O -

6.4.1.3
Miscellaneous Instructions — Miscellancous instructions such as HALT, WAIT, SET and
CLEAR condition codes, along with trap and interrupt instructions, are decoded by this PLA (K2-5,
E100). This PLA also generates most of the IR codes and K2-5 CPU HALT REQUEST H. The outputs generated by the various instructions are as follows.

Instruction

IRC 00

IRC 01

IRC 02

HLT
IMP/JSR
EMT
TRAP
10T
BPT

0
0
1
0
0
1

0
1
0
1
0
|

0
0
|
1
]
0

Reserved

Input K2-2 USER + SUPER H detects the absence of kernel mode for certain instructions. K2-10 EN
CALL SUPER H allows the call to supervisor mode (CSM) instruction to be executed.
6.4.2 Miscellaneous Decoding for Reset Instruction and T Bit
PROM E88 K2-5 and associated gating are used to decode reset, return to interrupt (RTI) and return
to interrupt no trace trap (RTT) instructions. When these instructions are decoded three possible signals are generated.
1.

K2-5 DISABLE LOAD PRW H - This signal prevents the loading of the processor priority
bits when the CPU is not in the kernel mode. It is generated during the RTI (T) instruction
when the CPU is in the user or supervisor modes.

K2-5 ENAB T BIT H - This signal simply enables the T bit trap for RTI instructions when
asserted and disables it for RTT instructions when not asserted.

K2-5 START RESET H - This signal will cause a UNIBUS INIT to be generated for 150
ms when a RESET instruction with the CPU in kernel mode is detected. A RESET in the

user or supervisor mode is no-oped. When the CPU is not in a power clear mode, the
UNIBUS INIT is performed by a one-shot (K2-11, E9).

6.4.3

ALU Auxilliary Control

The AUX control logic (K2-4) consists of a three PROMs (E68, E46, E43) which are used to determine
the ALU operation to be performed when an instruction takes the form of X — Y OP B. The Y designates a scratchpad register and the X designates either the B REG or a scratch pad register.
The AUX DOP PROM (E68) decodes double operand instructions, and is enabled when K2-7 AUX
CONTROL (1) H is asserted and K2-4 IR 12-14 = 0 L is not asserted. The following table gives the
output of the PROM as a function of the instruction being performed. (B represents the B register, A
represents any scratchpad register, and F represents the ALU output.)

ALU

Outputs

Function

D00

D01

D02

D03

D04

D05

D06

DO7

MOYV (B)
COMP (B)
ADD
SUB
,
BIT (B)
BIC (B)
BIS (B)
XOR

F=A
F=A minus
B
F=A plus B
F=A minus B
F=A.B
F=A.B
F=A + B
F=A + B

0
0
0
0
0
0

]
0
0
0
0
0
0
0

0
0
1
0
0
0

1
0
C
0
]
]
]
1

0
]
0
1
0
1

0
0
1
0
0
0

0
0
1
0
1
1

0
1
0
1
0
1

?’\

0
0

Instruction

0
0

1
1

0
0

0
1

The AUX SOP PROM (E46) decodes single operand instructions, and is enabled when K2-7 AUX
CONTROL (1) H is asserted and K2-4 IR 12-14 = 0 H is asserted. The following table gives the
outputs of the PROM as a function of the instruction being decoded.
ALU

Outputs

Instruction

Function

D07

D06

D05

D04

D03

D02

D01

D00

SWAB

F=A

CLR (B)

F=ZERO

COM (B)

F=A

INC (B)

F=A plus 1

DEC (B)

F=A minus |

NEG B

F=A minus
B

ADC (B)

*F=A plus

F=A plus
C BIT (1)

*F=A minus

F=A minus
C BIT (1)

TST (B)

F=A

ROR (B)

F=B

ROL (B)

F=B

ASR (B)

F=B

ASL (B)

F=B

MARK

N/A

MFRI (D)

F=A

MTPI (D)

F=A

MFPS

F=A

MTBS

F=A

SXT

F=NBIT (0)

F=NBIT (1)

C BIT (0)

SBC (B)

C BIT (0)

6-20

Auxiliary control signals are also necessary for performing rotate and shift instructions. The RO-

TATE/SHIFT PROM (E43) decodes these instructions and generates the control signals necessary to

shift the contents of the B REG. Inputs K1-1 B REG 00 (1) H, K1-10 CC N H, and K1-1 CBIT (1) H
also determine the K2-4 SERIAL SHIFT H and K2-4 ROT C BIT H signals. The SERIAL SHIFT H
signal is sent to the B SHIFT MUX where it is used in determining K1-10 SHIFT IN B H. SERIAL
SHIFT is also sent to the BYTE SHIFT MUX where it is used in determining K1-10 SHIFT IN 07 H
when just a byte of data is shifted. K2-4 ROT C BIT (1) H is used in the calculation of the new carry
condition (condition code PROM K1-10, E42). Note that for all rotate and shift operations, the AUX
control is performed on the B «— B step before each X — Y OP B step previously mentioned. This is
done to allow the condition codes to be set up without slowing the processor.

6.5

DATA TRANSFER LOGIC

6.5.1

UNIBUS Transfer Logic

All data transfers on the UNIBUS are controlled by the bus transfer logic on print K4-1. This logic
monitors the status of the UNIBUS (Bus Busy), controls the bus control lines BBSY, MSYN, CO and
C1, and also detects parity errors, bus errors, memory management errors and odd address errors.

6.5.1.1 Processor Clock Inhibit — All processor data transfers on the UNIBUS are started by K2-7
BUF DATA TRAN (1) H. When a data transfer is started, it is necessary to stop the system clock. The
clock is stopped by K2-1 EXT TAP 30 H, K4-1 ABORT RESTART L (not asserted), and E102 pin 12
(K4-1) being ANDed to create K4-1 TRAN INH L. K4-1 TRAN INH L then asserts K4-2 INH L
which stops the clock.

6.5.1.2 UNIBUS Synchronization — The synchronization logic shown in Figure 6-10 determines
whether the processor or some other device will control the UNIBUS. Flip-flop E116 (K4-1) and its
associated logic determines whether or not the bus is in use. When BUS IN USE H is asserted at the
set input of E116, the bus is in use. Each of the inputs on E122 and E100 that combine to create BUS
IN USE H, monitors a specific set of bus conditions.

A UNIBUS peripheral has asserted a nonprocessor request (NPR)

NPR

and wishes to gain control of the bus immediately.

(K4-2 NPR H)

Another UNIBUS device already has control of the bus and is as-

BBSY

(K4-1 BBSY H)

serting a bus busy (BBSY).

NPG
(K4-2 NPG (1) H)

An NPR device has gained control of the UNIBUS and the processor has issued a nonprocessor request grant (NPG). The condition

may exist where the NPR device has already recognized the NPG
and has dropped its NPR signal, while not yet having asserted a
SACK or BBSY.

NO SACK L
(K4-2 NO SACK L)

A device has requested control of the UNIBUS. The processor has
issued a grant, and the device has returned SACK L, causing NO
SACK L to go high. The condition may exist where only SACK L
remains on the UNIBUS for a period of time before the peripheral
asserts BBSY.

6-21

TAKE BUS H
(K2-9 TAKE BUS H)

Gives unconditional control of the UNIBUS to the MFM (console
module).

DATIP (0) L
(K4-1 DATIP (0) L)

When this input is true, all of the above signals are overridden. It
indicates
that
the
processor
is
performing
a
DATIP

(read/modify/write) operation, and has control of the UNIBUS
(BBSY asserted). NPR devices may, however, be granted control,
but must wait until the processor releases BBSY before asserting
theirs. (DATIP operations dictate worst-case bus latencies for NPR
devices.) The DATIP flip-flop (E95) is clocked with the assertion of
CPU MSYN (1) H during a DATIP cycle. It is cleared out by the

following cycle which must be a DATO (B).

If none of the above bus-in-use conditions exist, the E116 flip-flop on K4-1 can be set when K4-1 GET
BUS H is asserted. K4-1 GET BUS H is asserted by K2-7 BUF DATA TRAN (1) H and remains

asserted until K4-1 GET BUS H goes low followed by the assertion of K2-1 EXT TAP 30 H. Setting
E116 starts the data transfer.

K4-1 DATIP (1} L.

K4-1 DATIP (0) L

K2-9 TAKE BUS H — ’
E100

K4-1 BBSY H

K4-2 NPR H

K4-2 NPG (1) A

}

BUS IN USE H

K4-2 NO SACK L

E116

K4-1 GET BUS H

;

1900 ¢

30 NS

DELAY ==

100 PF

K4-1 ENAB

ADRS H

(STARTS DATA
TRANSFER)

TK-6353

Figure 6-10

UNIBUS Synchronizer

6.5.1.3

Bus Control - When flip-flop E116 is set, the bus transfer circuitry begins a UNIBUS data
transfer by asserting K4-1 ENAB ADRS H which begins the following actions.
1.

Enables the bus address drivers

Enables bus busy driver (K4-1)

6-22

Enables the bus control signals BUS C0 and BUS CI, which determine the kind of transfer

being performed

Cco

Operation

0
0
1
1

0
1
0
1

DATI
DATIP
DATO
DATOB

The actual condition of these control lines is determined by K2-8 BUF CO (1) H and K2-8
BUF C1 (1) H.

Enables the bus data drivers if the operation being performed is a DATO.

' K4-1 ENAB ADRS H is asserted 30 ns after E116 is set by K4-1 GET BUS H being asserted and BUS
IN USE H being negated. The delay is created by R5 and C1. The PAX address is then passed to the
UNIBUS or memory bus (EUB) as determined by flip-flop E81 (K4-3) and K1-11 UPPER 128K L. At
this time, BUS BBSY L is also asserted.

6.5.1.4 Generation of MSYN and MSYN/SSYN Timeout — The logic in Figure 6-11 is used to generate MSYN and MSYN/SSYN timeout. The generation of MSYN begins with the assertion of K4-1
ENAB ADRS H. When this signal is asserted, it is sent down serial delay line E127 which generates
K4-1 DLY ENAB H. There are two possible time delays inserted, depending on the type of instruction
being exccuted. If the instruction is a standard PDP-11 instruction, the delay will be 40 ns. This delay
allows the address lines to settle and gives the cache memory enough time to recognize the address on
the PAX lines. The other delay, 160 ns, is used if the commercial instruction set (CIS) option is installed and a CIS instruction is being executed. This time delay is inserted to allow the address to be
transfered through the additional logic associated with the CIS option.

When K4-1 DLY ENAB H is asserted, it is ANDed with K3-2 START TRN H, which is asserted 90 ns
into the current cycle, and with the output of E102 pin 4, which is always high at the beginning of short
cycles, to create K4-1 START TRAN L. K4-1 START TRAN L is then fed into serial delay E86
which is used to develop the timing necessary to complete the generation of CPU MSYN.

When K4-1 START TRAN L is asserted, the direct clear on CPU MSYN flip-flop (E95) is removed.
K4-1 CACHE GATE H is asserted 45 ns after K4-1 START TRAN L is asserted. This signal, along
with K1-11 UPPER 128K L, is used to determine if the address is a UNIBUS or memory bus (EUB)
address. Approximately 90 ns after K4-1 START TRAN L is asserted, K4-1 STROBE CACHE H is
asserted for approximately 15 ns. This signal strobes cache and if a cache hit is registered, CACHE
RESTART L is asserted. CACHE RESTART L restarts the system clock and clears the CPUMSYN
flip-flop (E95). This series of events cancels the remainder of the DATA TRAN cycle because a bus
transfer is no longer needed. If a cache miss occurs, CACHE RESTART L is not asserted and CPU
MSYN one-shot (E97) is armed. After the MSYN one-shot is armed, K4-1 CPU MSYN (1) H is asserted and fires the MSYN one-shot. The low going pulse of the MYSN one-shot readies the
MSYN/SSYN timeout flip-flop (E115). If K4-3 SSYN H is not asserted by the time the MSYN oneshot times out, the MSYN/SSYN timeout flip-flop is set and K4-1 TO (1) H and K4-1 TO (1) L are
asserted and signal a timeout. Normally, however, K4-3 SSYN H will be asserted and complete the
transfer before the MSYN one-shot times out. During the next microcycle, START TRAN H will be
negated and direct clear the MSYN one-shot.

6-23

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When a DATI or DATIP operation is performed, it is necessary to delay the MSYN cycle (MSYN
long cycle) to allow for the creation of the relocated physical address. This is done by selecting ALLOW MSYN H (E102) as one of the signals used to generate K4-1 START TRAN L. ALLOW
MSYN H is delayed 90 ns before it is asserted, allowing enough time to create the relocated physical
address.

6.5.1.5

Restarting Processor Clock — The processor clock can be restarted by the following conditions.

1. | A cache HIT-CACHE RESTART
L is asserted and restarts the clock.
2.

An error condition exists. If an odd address, parity, timeout, or KT error has occured,
ABORT RESTART L is asserted and negates K4-1 TRN INH L which negates K4-2 INH
L and restarts the clock.

Completion of data transfer. The clock is restarted at the end of a data transfer cycle by
clearing pin 12 of multiplexer E102, which negates K4-1 TRAN INH L, which negates K4-2
INH L, and restarts the clock.

On DATI and DATIP operations, when K4-3 SSYN H is asserted at E84 (K4-1 CPU MSYN (1) H is
already asserted), the outgoing signal is deskewed (Figure 6-12) a nominal 75 ns to allow for worst-case
bus transit and receiver times. The signal is deskewed 140 ns when a CIS instruction is in use. This is to
allow for additional delay created by the CIS processor. Note that a parity error which asserts K4-1 PB
H will not allow the clock to restart.
On DATO and DATOB cycles, it is not necessary to deskew the output of E84, therefore, it is passed
directly to E102 to negate K4-1 TRAN INH L and start the clock.
6.5.2
Bus Arbitration
The PDP-11/44, like other PDP-11

processors, responds to bus requests (BRs) and nonprocessor
requests (NPRs) issued by the different UNIBUS devices (CPU, peripheral devices). These requests
have an established priority that determines which request is serviced next. The requests in descending
order of priority are NPR, BR7, BR6, BRS, and BR4.

The bus arbitration logic of the PDP-11/44 recognizes a software controlled request, programmed interrupt request (PIRQ), which is initiated by the software to schedule certain tasks, such as, housekeeping functions. This request, along with the priority level of the processor, and the current highest
BR level are arbitrated by the bus arbitration logic and use of the bus granted to one.
6.5.2.1
Bus Requests — Bus requests are handled by the logic on K4-2. The BRs are received and
clocked into holding register E101 by the positive transition of EXT CLK C L. The output of the holding register is then passed to the arbitration PLA (E82) where it is compared with the processor priority
level (PSW 07:05) and the PIRQ priority level (PIA 3:1). After the requests have been arbitrated by
the PLA, one of three actions will take place.

No Action — This indicates the processor has the highest priority level.

Issue a PIRQ Grant — The PIRQ request has the highest priority level.

Issue a Bus Grant — The BR has the highest priority level and a BG at the same level is
issued by asserting the proper input to E92 and BG + HLT H.

Because a BR can cause a program interrupt, it may be serviced only after the completion of the current instruction cycle.

6-25

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6-26

If no halt requests or traps are pending, then K2-2 ENAB GRANTS H is asserted and ANDed with
BG + HLT H to halt the clock by causing K4-2 INH L to be asserted. This combined signal is also
used to set the enable BG flip-flop (E113). The issuing of grants is controlled by the request synchronization logic.

6.5.2.2 Request Synchronization — The request synchronization logic of Figure 6-13 is used to determine whether a BG or a nonprocessor grant (NPG) is to be enabled.
Flip-flop E116 acts as the synchronizer between BRs and NPRs. During the service state of the microprogram, K2-8 BUT SERVICE (1) H is asserted. If there are no NPGs on the bus, K4-2 NPG (0) H 1s
asserted, the console has not stopped the clock, and MFM CLK INH L is not asserted, then the output
of E47 goes high. This allows E116 to be cleared if there are no NPRs present. [f SACK is not asserted,
then E124-8 goes high, clocks E113 and enables the proper BG. During the acceptance sequence, the
clock is stopped.

The request synchronization logic allows an NPR to be granted use of the bus anytime the bus is not in
an arbitration sequence; that is, BUS SACK L is not asserted, thus allowing any DMA traffic to be
processed at this time. When BUS NPR L is asserted, E116 will be set if a competing BG has not
already cleared the flip-flop. If SACK is not asserted, E124-11 goes high and clocks E113 which causes
BUS NPG H to be asserted. While NPG is asserted, no further bus grants are honored.
6.5.2.3 SACK Timeout — The SACK timeout logic of Figure 6-14 is used to determine if SACK has
been generated by the device receiving either the BG or NPG.
The gencration of BUS SACK L from the device requesting use of the bus direct clears both halves of
E113 (K4-2). E113 pin 6 goes high, and clocks SACK return flip-flop E114 which stops the system
clock and clears request latch E101. When BUS SACK L is negated, K4-2 NO SACK L is asserted
and clears the SACK return flip-flop E114 which restarts the system clock and allows a new arbitration
for the bus.

‘

The SACK timeout circuitry consists of one-shot E97 and its associated logic. One-shot E97 monitors
the BG and NPG lines. If BUS SACK L is not asserted in 20 us to acknowledge the grant, one-shot E97
times out and clears the grant itself. This is done either to avoid hanging the processor on nonexistent
devices or when the BR is removed by the interrupting device before the grant could be accepted.

K2-8 BUT

SERVICE (1) H—]

MFM CLK INH L ——]

H —

‘

E126

RCD INIT L .a} O
BUS NPR L —O|

E109

£124

8 TOBG
FLIP-FLOP

c124

YLTONPG

BG ENABLE

NPG ENABLE

FLIP-FLOP

|||—>

K4-2 NPG (0)

E47

|
L

K42

NPR
H

FROM SACK
TK-5381

Figure 6-13

Request Synchronization

6-27

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6-28

Program Interrupt Request (PIRQ) - The program interrupt request register is described in

6.5.2.4

paragraph 2.3.1.2.

The PIRQ logic is located on K2-10. The PIRQ consists of E69, E15 and PROM E6. The PIRQ is
loaded via BUF PAX D 15:9 with the assertion of K1-10 LOAD PRIH L and on the rising edge of
PROC CLK L. PROM E¢6 is a priority encoder which takes the highest priority level (0-7) and changes
it to a three digit octal value, PIA 3:1.

The bus arbitration logic (K4-2) issues a PIRQ grant by asserting K4-2 PIRQ GRANT L. This causes
MPC 00 L and INT VECTOR L (K2-2) to be asserted when the next service state is entered. The trap
service PLA (E99) asserts the PIRQ vector 240 which is strobed into the processor during the trap
handling microsequence. The PIRQ vector 240 is put onto the SSMUX lines by the assertion of INT
VECTOR L (K1-10) so the vector can be read by the processor.

6.5.3

Error Logic

The data transfer error logic in Figure 6-15 is used to log the four different types of errors that may
el

occur during a CPU data transfer. The following are the four types of errors.
Bus error
Odd address error

Parity errors — memory read and cache
KT errors

K2-3 DISABLE MSYN L

K4-1TO(1) L

K4-1 SET BE L

E111 )&

—— K4-1 BE (1) H

K4-1 ABORT H

K4-1 PARITY ERROR H

E 119

O— K4-1BE (1) L

—1{C

CACHE PE INTR L

K4-1 PE (1) H
D

E 119
o

—C

K4-1 ABORT H

K1-8 KT FAULTL ob
K4-2 BUS SERV L —O|

EXT CLKCL—O

E76

D
[

E 115

0
o

K2-11 PROC INIT L‘-T_-_

END TRAN TO MFM L:g

BUS STATUS ENAB L

Figure 6-15

Transfer Error Logic

6-29

K4-1 KTE (1) H

TK-5344

When any of these errors are detected, with the exception of a cache parity error, and the appropriate
signal is asserted, ABORT H and ABORT RESTART L are asserted. Figure 6-16 shows the logic used
to generate ABORT H and ABORT RESTART L. ABORT H is a pulse approximately 15 ns in duration that clocks the errors into flip-flops E115 and E119 where they are logged. ABORT H also clears

the next MPC address latches (K2-6, K2-8) which forces the CPU into a trap service state and sets the
appropriate bits in the CPU error register (K2-11). Approximately 100 ns after ABORT H is asserted,

ABORT RESTART L is asserted and restarts the system clock. Restarting the system clock causes the
CPU to service the trap condition created by the specific error or errors. The trap vector is generated
by the trap service PLA (K2-2).

The error signals and the error conditions that cause them are shown in Table 6-1.

The error logic may be cleared by:
1.

a processor INIT

a console read of the error register

servicing the error.

K1-8 KT FAULT L

K2-3 DISABLE
MSYN L

—Q

K4-1 E118-P4 H —
START TRAN H —
K4-1 PARITY ERROR H

K4-1TO (1) H

K4-1 ABORT
RESTART L

E120

{15 NS DELAY)

/_L_\CS

K4-1 ABORT H

l—

R12

E126

K4-1 DISABLE

W BITL

TK-56345

Figure 6-16

6.5.4

Generation of ABORT RESTART L and ABORT H

Cache Interface

An 8K byte direct-mapped cache memory reduces the average memory cycle time in the PDP-11 /44 to

a minimum. For an explanation of how the cache memory operates, refer to paragraph 6.12, KK11-B
Cache.

6.6

SYSTEM CLOCK

The system clock (K2-1) on the PDP-11/44 generates all the timing signals to which the processor is
synchronized. This allows an orderly execution of the various functions performed by the processor. The

clock consists of a delay line (E3) and associated logic (E2, E13, E21, E22) that is used to create the

positive feedback necessary for the clock to sustain oscillation. The various timing signals are taken
from the different taps on the delay line.

6-30

Table 6-1' Error Logic Outputs

Error Signal

K4-1 BE (1) H

Error Condition

SSYN was not returned in time and the SSYN timeout one-shot (E97)

times out, clocks flip-flop E115 and asserts K4-1 TO (1) H.

An odd address error is detected and K2-3 DISABLE MSYN L is as:
.
serted.

K4-1 PE (1) H

A memory read parity error is detected and K4-1 PARITY ERROR H is

asserted.

A cache memory parity error is detected and CACHE PE INTR L is asserted. This signal does not generate ABORT H or ABORT RESTART
L. This error is serviced at the end of the current instruction cycle.

K4-1 KTE (1) H

A nonresident, read only, or page length violation is detected and K1-8
KT FAULT L is asserted.

When power is applied to the clock, and if none of the clock disable signals are asserted (K42 INH L,
K2-11 INT PROC INIT L, MAN CLK ENAB L), the clock will start running. The length of the operating cycle will be either 180 ns or 240 ns. The normal cycle, or short cycle, for the processor is 180 ns.
The 240 ns cycle, or the long cycle, is used when a DATO or DATOB is being performed, or in situations where the condition code must be determined before an operation can be performed. The long
cycle is selected by K2-6 LONG CYCLE L being asserted.

The basic timing signals generated by the clock are shown in Figures 6-17 and 6-18 in relationship to
the delay line input (E3). The rising edge of PROC CLK L is designated as TO because it is at this time
that the execution of the next microinstruction begins. The other signals created from these basic signals are the following.

EXTCLKAL,EXTCLKBL, EXT CLK C L - These timing signals are logically identical

to PROC CLK L. These separate signals are sent to the various modules. These signals are
used so that loading will be equalized and edge skews minimized.

PROC CLK H - is the inverse of PROC CLK L.

EXT TAP 30 H - is identical to TAP 30 H.

EXT TAP 90 L — is the inverse of TAP 90 H.

ALLOW MSYN H - is generated by the ANDing of TAP 30 H, TAP 90 H, TAP 120 H or
by RELOCATE H not being asserted. This signal delays the memory cycle until the PAX

ADRS is loaded during a DATI or DATIP operation.

6-31

T30

T60

T90

T120

(150 NS)

T150

T180

PROC CLK L

(90 NS)

TAP 30 H

(45 NS)

TAPO9OH

(135 NS)

(75 NS)

TAP 120 H

(165 NS)

B
(45 NS)

[]
(135 NS)

LOAD VBA H

(75 NS)

(165 NS)

LOAD BAR H
INPUT TO DELAY

LINE

I
TK-5343

Figure 6-17

PDP-11/44 System Clock Short Cycle Timing Diagram

T30

T60

T90

T120

T150

T180

T210
'

(210 NS)

PROCCLK L

]

TAP 30 H

—

l‘

TAP 90 H

(45 N%

TAP 120 H

l(195 NS)
(165 NS)

L
(75 NS)

DELAY

INPUT TO

LINE

[(165 NS)

(45 NS)

LOAD BAR H

120 NS)

(75 "fii

LOAD VBA H

(195 NS)

T240
l

|
TK-5338

Figure 6-18

PDP-11/44 System Clock Long Cycle Timing Diagram

6-32

The clock may be stopped by asserting one of three signals.
1.

MAN CLK ENAB L — This signal disables the clock and allows it to be manually stepped by
the assertion of MAN CLK L. Any TTL-compatible waveform may be used to single-step
the clock.

INT PROC INIT L — This signal will stop the clock when asserted.

INH L - This signal stops the clock when asserted. This signal indicates a bus cycle is in
progress and can be overridden by CACHE RESTART L which restarts the clock.
Figure 6-19 shows a memory cycle in which the system clock is stopped.

oYX
AW =

The system clock is turned off by the appropriate signal under the following conditions.

6.7

During a BUS INIT that is not caused by a RESET
During the INIT portion of the power-up routine
During the INIT portion of the power-down routine
During a RESET

During a BUT service arbitration delay
During a priority interrupt

While BUS SACK is asserted by an interrupting device (not for NPRs)
During bus data transfers
After a HALT instruction is executed

When the console processor generates a clock inhibit signal

When the manual clock is enabled

POWER FAIL/AUTO RESTART

The PDP-11/44 power fail/auto restart circuitry (K2-2) serves the following purposes.
1.

Initializes the microprogram, the UNIBUS control, and the UNIBUS to a known state im-

mediately after power is applied to the computer.

Notifies the microprogram of an impending power failure.

Prevents the processor from responding to an impending power failure for 2 ms after initial
startup.

The actual power fail/auto restart sequences are microprogram routines. The operation of the power
fail /auto restart circiutry depends on the proper sequencing of two bus signals: AC LO and DC LO.
Because of the electrical properties of the UNIBUS drivers and receivers, the entire computer system
must be powered up for the machine to operate. Therefore, the processor is notified of a power failure
in peripherals, as well as in its own ac source.

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The notification of power status of any PDP-11 system component is transmitted from each device by
the signals BUS AC LO L and BUS DC LO L (K2-2). The power-up sequence (Figure 6-20) shows that
BUS DC LO L is unasserted before BUS AC LO L is unasserted. When BUS DC LO L is not asserted,
it is assumed that the power in every component of the system is sufficient to operate. When BUS AC
LO L is not asserted, there is sufficient stored energy in the regulator capacitors of the power supply to
operate the computer for 5 ms, should power be shut down immediately.
As ac power is removed, BUS AC LO L is asserted by the power supply, warning the processor of an
impending power failure. When BUS DC LO is asserted, it must be assumed that the computer system
can no longer operate predictably. Memories manufactured by DIGITAL use BUS DC LO L as a
switched signal, turning them off even if power is still available. Time A t2 (Figure 6-20) is the time

delay between the assertion of BUS AC LO L and the assertion of BUS DC LO L; this time delay must
be greater than 5 ms. This allows for power to be rapidly cycled on and off. According to PDP-11 specifications, on system start up, a minimum of 2 ms run time is guaranteed before a power fail trap occurs,
even if the line power is removed simultaneous with the beginning of the power-up sequence. After the
power fail trap occurs, a minimum of 2 ms run time is guaranteed before the system shuts down. Given
the tolerance permitted in the timing circuitry used in most equipment, At2 must be greater than 5 ms.
When a pending power fail is sensed, a program trap occurs, causing the present contents of the PC
(R7) and the PSW to be pushed onto the memory stack, as determined by the contents of R6 (stack
pointer register). The PSW is then loaded with the contents of location 26g and R7 with the contents of

243. Processing is continued with the new R7 and PSW. The user’s program must prepare for the impending power failure by storing away volatile registers and reloading location 24g and 26g with a power-up vector. This vector points to the beginning of a restart routine.
When power is restored, the processor loads the PC (R7) with the contents of location 24g and the PSW
with the contents of location 26g. After loading these registers, the user’s program presumably will pre-

pare locations 24g and 26g for another power failure. If the HLT RQST L input is asserted by an external switch closure, the processor powers up through locations 24g and 26g and halts.

Schematics for the power fail, auto restart, and bus reset logic are on K2-2. One-shot E9 generates a
150-ms processor INIT pulse as soon as BUS DC LO L is negated after power is applied to the processor. This pulse is used to initialize the processor by asserting K2-2 PWR CLR L which asserts the various initialize signals on K2-11. At the end of 150 ms, the PUP one-shot (E10) is fired if BUS DC LO L
is not asserted and the processor begins the PC and PSW load routine. The PUP one-shot generates a 2ms pulse, during which the assertion of BUS AC LO L is ignored.

+5V

g
=)

BUS AC LO L gy

—

BUS DC LO L OV——[

—blAtld—

INIT

|A11>Oms

)

—

|<—At2>5ms

((’_

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POWER UP

l_g -

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PDWN

)

l<*6.6ms->‘
1-3950

Figure 6-20

BUS AC LO and BUS DC LO Timing Diagram
6-35

The triggering of the 150-ms INIT one-shot (E9) also resets the POWER INIT flip-flop (E51). Setting

this flip-flop forces the control store to run the power-up routine beginning at microPC address 001. It
is this routine that reads location 24g and 26g for the new PC and PSW.
After PUP has timed out, the assertion of BUS AC LO L would fire the PDWN one-shot (E10). Upon
entering the next service microcode state, K2-2 PFAIL H is latched into E112 (K4-2), causing a power

fail trap to be recognized by the microprogram on entering the next service state. Various traps are
arbitrated by the BUT service PLA (E99).

If a momentary power failure causes the assertion of BUS AC LO L but does not cause the assertion of
BUS DC LO L, the processor will restart when the PDWN one-shot times out, retriggering the INIT
one-shot.
CIM BOOT H is used to initiate a power fail sequence from the front panel boot switch. During the
power failure initiated by the front panel boot switch, BUT BOOT H (K2-8) is asserted which forces
the microcode to execute a boot routine which fetches the new PC from location 773024g. A power
failure initiated by a remote bootstrap module, such as an M9312, will also assert BUT BOOT H, causing a boot power-up sequence to occur.
6.8

MEMORY MANAGEMENT
Memory management is used to relocate a 16-bit virtual address, if necessary, and transmit the 22-bit
physical address to the UNIBUS (refer to paragraph 6.9, Unibus Map), cache memory, or main memo-

ry. Address modification is the main function of memory management. The modification of addresses is
called relocation because it consists of adding a fixed constant to a virtual address to create a physical
address.
Memory management also allows the user to protect one section of memory from access by programs
located in another section. Memory management divides memory into individual sections called pages.
Each page has a protection or access key associated with it that defines the type of access allowed on
that particular page. With the memory management unit, a page can be keyed nonresident (memory
neither readable nor writable) or read-only (no write operations to memory). These two types of protection, in association with other features, enable the user to develop a secure operating system.

It is often desirable to load a program into one area of physical memory and execute it as if it were
located in another area of memory, for example, when several user programs are simultaneously stored
in memory. When any one program is running, it must be accessed by the processor as if it were located
in the set of addresses beginning at 0. This process is called relocation. When the processor accesses
virtual bus address 0, a base address is added to it and the relocated O location of the program is accessed. Typically this base address is added to all references while the program is running. A different

base address is used for each of the other programs in memory.
Memory management specifies relocation on a page basis, which allows a large program to be loaded
into nonadjacent pages in memory. This capability eliminates the need to shuffle programs to accommodate a new one. It also minimizes unusable memory fragments, thus allowing more users to be
loaded into a specific memory size.
A program and its data can occupy as many as 16 pages in the memory. The size of each page may vary
and can be any multiple of 32 words up to 4096 words in length. This feature allows small areas of
memory to be protected (stacks, buffers, etc.), and also allows the last page of program, exceeding 4K
words, to be of adequate length to protect and relocate the remainder of the program. As a result, the
memory fragmentation problem inherent with fixed-length pages is eliminated. The base address of
each page can be any multiple of 32 words in the physical address space, thus ensuring efficient use of
main memory. The variable page length also allows the pages to be dynamically changed at run time.

6-36

Memory management provides three separate sets of pages for use in the processor’s kernel, Supervisor,

and user modes. These sets of pages increase system protection by physically isolating user programs
from service supervisor programs and the kernel program. The service programs are also separated
from the kernel program. Separate relocation register sets greatly reduce the time necessary to switch
context between mapping. The three sets of registers also aid the user in designing an operating system
that has clearly defined communications, is modular, and is more easily debugged and maintained.

The virtual bus address space is further divided, within each of the kernel, supervisor, and user pages,
into instruction space and data space (I and D space). I space contains code, that is, any word that is
part of the program such as instructions, index words and immediate operands. D space contains information that can be modified, such as data buffers.

By using this feature, memory management can relocate data and instruction references with separate
base address values. Therefore it is possible to have a user program of 64K words consisting of 32K of
instructions and 32K of data.
6.8.1

Relocation

When memory management is enabled, the normal 16-bit direct-byte address is no longer interpreted as
a direct physical address (PA) but as a virtual bus address (VBA) containing information to be used in

constructing a new 22-bit PA. The information contained in the VBA is combined with relocation information contained in the page address register (PAR) to make a 22-bit PA. Using memory management,

memory can be dynamically allocated in pages composed of from 1 to 128 blocks of 32 words each.

The starting PA for each page is a multiple of 32 words, and each page has a maximum size of 4096
words. Pages may be located anywhere within the PA space. The sct of 16 PARs to be used to create
the PA is determined by the current mode of operation of the CPU (kernel, supervisor, or user).
6.8.1.1 Address Mapping — All addresses with memory relocation enabled reference information in
either instruction (I) space or data (D) space. I space and D space each have eight PARs in each mode
of CPU operation. Using register SR3, the operating system may select to disable D space and map all
references through I space, or to use both I and D space.

The basic information needed for the construction of a PA comes from the VBA, which is illustrated in
Figure 6-21, and the appropriate PAR set.

15
1

APF

12
1

ACTIVE PAGE

DISPLACEMENT FIELD

FIELD
TK-5348

Figure 6-21

Interpretation of VBA

The VBA consists of:

1. - The Active Page Field (APF) — This 3-bit field determines which of the eight PARs will form
the PA.

The Displacement Field (DF) — This 13-bit field contains an address relative to the beginning
of a page. This permits page lengths of up to 4K words. The DF is further subdivided into
two fields as shown in Figure 6-22.

6-37

]

05
DiB

]

BLOCK NUMBER

DISPLACEMENT IN BLOCK
TK-5349

Figure 6-22

Displacement Field

The displacement field consists of:
1.

The Block Number (BN) — This 7-bit field is interpreted as the block number within the
current page.

The Displacement in Block (DIB) — This 6-bit field contains the displacement within the

block referred to by the block number (BN).
The remainder of the information needed to construct the PA comes from the 16-bit page address field
(PAF) which is contained in the PAR and specifies the starting address of the memory page. The PAF
is actually a block number in the physical memory, for example, PAF =3 indicates a starting address of
96(3 X 32) words in physical memory.

The formation of the PA is illustrated in Figure 6-23.

VIRTUAL

ADDRESS

SELECTS

06 05

PLUS——J

l
e

PAR
\

[

EQUALS

J
21

PHYSICAL
ADDRESS

TK-4494

Figure 6-23

Construction of PA

6-38

The logical sequence involved in constructing a PA is as follows.

Select a set of PARs, depending on the space being referenced (I or D).

The APF of the VBA is used to select a PAR (PARO-PAR7).

The PAF of the selected PAR contains the starting address of the currently active page as a

The block number (BN) from the VBA is added to the PAF to yield the number of the physical block in memory which will contain the PA being constructed.

The displacement in block (DIB) from the displacement field (DF) of the VBA is joined to

block number in physical memory.

the physical block number to yield a 22-bit PA.

6.8.1.2 Address Translation — Address translation is done from the VBA (Figure 6-24) which is created by latching the scratchpad outputs into the memory management (KT) buffer (K1-6, E77, E91,
E106) on the falling edge of LOAD VBA H. K1-8 RELOCATE H, K2-10 E22 BITS H and K2-8 D
SPACE H are also latched into the KT buffer at this time. These signals are used to enable the memory
management logic, and to determine the address mode.

Table 6-2 shows which of these signals will be asserted for a particular address mapping mode.
16-Bit Mapping — Refer to Figure 6-25. In 16-bit mapping, the PA space consists of 28K memory locations (PA = 00000 000 — 00 157 777) and the 4K peripheral page (PA = 17 760 000 ~ 17 777 777).
Physical addresses 00 160 000 — 17 577 777 cannot be generated when using 16-bit mapping.

Refer to Figure 6-26. A 16-bit VBA is the PA if bits 15:13 are not equal to 111. In this case bits 21:16
of the PA are made zeros and bits 15:00 of the PA are the same as bits 15:00 of the VBA. If bits 15:13
of the VBA are equal to 111, then a reference to the peripheral page is intended by the program and
bits 21:16 of the PA are set to 1 and bits 15:00 are the same as the VBA.

Table 6-2

Address Mapping Modes

Address Mode

D Space H

Relocate H

E22 Bits H

16-bit I space
18-bit | space

X*
0

0
1

X
0

18-bit D space
22-bit I space
22-bit D space

1
1
1

1
0
1

*Does not matter.

6-39

0
1
1

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[

6-40

2Indig ¥7-9

H3IAIHA

<90:Z1>
Liagl

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XVd

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XNINS <0 :S1>

0HOLvHOS a—133y0vHd—s —Z—ZWH0O1—L3Y4HTH@30VdS

Xvd SN

XN —

LE S

NO1lv LER Y

FLOW

17777777

77760000

| 17600000

PERIPHERAL PAGE

axK

16777777

1920K

177777

160000

VRTUAL

(16 BITS)

ooo00O

INCOMING
ADDRESS

00157777

28K

00000000

ADDRESS
LOCATIONS

PHYSICAL
ADDRESS SPACE

(22 BITS)

1-4049

=RELOCATION

——

ADDRESS
— ——=—— =NO
RELOCATION
16-Bit Mapping

Figure 6-25

VIRTUAL ADDRESS=157 746

16-BIT MAPPING

PHYSICAL ADDR.}

=00 157 746

{

UNIBUS

NOT

“ 21

ADDRESS

VIRTUAL ADDRESS=167

7461

—
16-BIT MAPPING

PHYSICAL ADDR.| 1
=17 767 746

11
|

tlr

16 15

[

UNIBUS ADDRESS

Figure 6-26

{

[ °

11-4028

16-Bit Mapping: Generation of PA

6-41

16-bit mapping is enabled by K1-6 M16 (1) H being asserted. VBA 15:00 are latched into E71, E94
(K1-6) and E93 (K1-11) on the falling edge of LOAD BAR H and are then driven onto the PAX ad-

dress lines. This action causes a one-to-one transfer of VBA 15:00 to PAX 15:00, and PAX 21:16 are set
to 0 if VBA 15:13 are not all ones. If VBA 15:13 are all ones, then K1-6 V I/O PAGE is asserted and
PAX 21:16 are forced to ones. This action causes a reference to the I/O page which is contained in the
upper 4K of memory.
18-Bit Mapping — Refer to Figure 6-27. In 18-bit mapping the VBA is added to the selected PAF to
generate the PA. This address mode has a range of 128K. The PA space consists of 124K (00 000 000 —
00 757 777) and the 4K peripheral page (17760000 — 17777777).
18-bit mapping is enabled by the assertion of K1-6 RELO (1) H and K1-6 M18 (1) H. As in 16-bit
mapping, VBA 05:00 are directly driven onto the PAX address lines via E71 (K1-6). VBA 15:13 are
used to select a PAR (PAR 0-7) which is then added to VBA 12:06 by high speed adders E98, E99,
E113 (K1-11). Bits 15:12 of the PAR are not used in 18-bit mapping. The sum of PAR 11:00 and VBA
12:06 create PA 21:06 which is then driven onto the PAX address lines by E95 and E104. If bits 17:13
are all ones, a reference to the peripheral page is intended by the program: E116 detects this condition
and forces PA 21:18 to ones. If bits 17:13 are not all ones then E116 will force PA 21:18 to 0.

FLOW

77777727

T T T T T 7 17777777

PERIPHERAL PAGE

770000

177777

VIRTUAL

(16BITS)

MEM
— T MGMT

000000

16777777

00757777

1020k

124K

100000000

INCOMING
ADDRESS

17600000

o 00000000

PHYSICAL
ADDRESS SPACE

ADDRESS
LOCATIONS

{22 BITS)

———— =RELOCATION
— ————%

=NO ADDRESS

1-4048

RELOCATION

Figure 6-27

18-Bit Mapping

6-42

Figure 6-28 illustrates an 18-bit PA that is not a UNIBUS reference, that is, bits 17:13 are not all ones.
In this case bits 21:18 of the PA are set to zeros, which causes a memory reference.

Figure 6-29 illustrates an 18-bit relocated address that is a UNIBUS reference, that is, bits 17:13 are
all ones. In this case bits 21:18 of the PA are changed to ones, which causes a UNIBUS reference.

VIRTUAL ADDRESS=157 746}

1312

06 05

APF

1]/1

BLOCK NUMBER

o
JI

DISPLACEMENT

IN BLOCK

SELECTS PAR 6

PAR 6 =13 546 000

06/

o©

‘

ACTIVE PAGE FIELD

|
|

21
ol

1
-

{

[

]

|
,

ADDER

21
INPUT

MULTIPLEXERS =|
13 565 746

21
18-BIT MODE

PHYSICAL ADDR]J

=00 565 746

o[t

1t
I

00,

]

0©

NOT

UNIBUS ADDRESS
1-4032

Figure 6-28

18-Bit Mapping: Memory Address

6-43

15
VIRTUAL

ADDRESS=157

13 12

746t

06 05

—~

APF

BLOCK NUMBER

111

DISPLACEMENT

[

IN BLOCK

SELECTS PAR 6

PAR
6 =13 746 000

12
0

121

'
f

o°

ADDER

06/

—

1
c

INPUT

21
ol

—~—

FIELD

|
ACTIVE PAGE

L__W_..__JL

00,

MULTIPLEXERS

=|1

13 765 746

18-BIT MODE

PHYSICAL

ADDR]

=17 765 746

|
UNIBUS

ADDRESS
11-4031

Figure 6-29

18-Bit Mapping: UNIBUS Address

22-Bit Mapping — Refer to Figures 6-30 and 6-31. In 22-bit mapping the VBA is relocated in the same
manner as 18-bit mapping, but the relocated address becomes the PA without modification. Thus, all
PAs from 00 000 000 — 17 777 777 can be generated.

Addresses 17 760 000 — 17 777 777 are UNIBUS 1/0 page references. Addresses 00 000 000 — 16 777

777 are memory addresses. The top 124K of addresses 17 000 000 — 17 757 777 may be used to access
memory via the UNIBUS map (paragraph 6.9).

22-bit relocation is enabled by the assertion of K1-6 RELO (1) H and M22 (1) H. As with 18-bit relocation, VBA 05:00 are used to make PA 05:00 and driven onto PAX address 05:00. VBA 15:13 are used
to select a PAR which contains a base constant. The 16 bits of the PAR are added to VBA 12:06 by
adders E98, E99, E113, E122, and carry generator E110. The output of the adders create PA 21:06
which are driven onto the PAX address lines by E95 and E115. If a reference to a UNIBUS address is
made, PA 21:18 all ones, K1-11 UPPER 128K L will be asserted and passed to the UNIBUS map logic
(paragraph 6.9).

6-44

FLOW

\7777777

77727777

PERIPHERAL PAGE

17600000

760000
12757777
124K

17000000

6777777

UNIBUS

6777777

MAP

1920K

ADDRESS
MEM

177777

/MGMT
__
|

_loooooooo
PHYSICAL
ADDRESS SPACE

000000
INCOMING
ADDRESS

00000000
ADDRESS

LOCATIONS

(22 BITS)

= =RELOCATION
~— ———— =NO ADDRESS
RELOCATION

1-4047

Figure 6-30

22-Bit Mapping

VIRTUAL ADDRESS=157 746|t

L___V__-J&

11+
A

BLOCK NUMBER

APF

‘

ol 1
.
|

121

13 765 746

—

1+ 1

1t 1
1

}
|

1
00.

‘l
|

ADDER

ADDRESS =

22 BIT PHYSICAL

06!

112

¥+

DISPLACEMENT

4}1

PAR 6 =13 746 000

SELECTS PAR 6

IN BLOCK

ACTIVE PAGE FIELD

06 05

1312

1t 0o 0o

0
11- 4037

Figure 6-31

22-Bit Address Mapping

6-45

6.8.2

Protection

A timesharing system performs multiprogramming; it allows several programs to reside in memory si-

multaneously, and to operate sequentially. Access to these programs and the memory space they occupy must be strictly defined and controlled. Several types of protection must be afforded a timesharing

system.

User programs must not be allowed to expand beyond allocated space, unless authorized by
the system.

Users must be prevented from modifying common subroutines and algorithms that are resident for all users.

Users must be prevented from gaining control of or modifying the operating system software.

The memory management logic provides the hardware facilities to implement all of the above types of
memory protection.

6.8.3
Page Address Registers (PAR)
The page address registers (K1-7) contain the constant or base address which memory management
adds to the VBA to create a 22-bit physical address. The forty-eight 16-bit PARs are made up of four
256 X 4 random-access memories, E69, E59, E58, E66. These registers can be either read or written.

Address selection is done via a multiplexer made up of E97 and E105. K1-10 PAR+PDR L is used to
select

the inputs used to address the PARs. During memory management relocation, KI-10
PAR+PDR L is not asserted. K1-9 PSEL 05:00 are created from VBA 15:13, MODE 01:00 (processor
mode), and LATCH D SPACE. VBA 15:13 determine which PAR, 0-7, is to be used. MODE 01:00

selects which set of PARs, user, supervisor, or kernel will be used. LATCH D SPACE selects [ space or

D space. Figure 6-32 shows the allocation of the PARs. When a PAR is going to be written, examined
by the console, or read by the program, K1-10 PAR+PDR L is asserted and PAX/A08, 06, 04:01 are

used to create K1-9 PSEL 05:00. K1-10 PAR+PDR L is generated by PLA E114. Data on the
SSMUX will then be written into the selected PAR on the falling edge of EXT CLK B L. Whether the

high byte or the low byte or both high and low bytes will be written is determined by K1-10 LOAD
PARH L and K1-10 LOAD PARL L which are used to enable the write inputs to the PARs.

6.8.4

Page Descriptor Registers (PDR)
In addition to its relocation function, memory management has supervisory or memory protection

tions which are determined by the contents of the PDR.

func-

The PDR is read at the same time as its corresponding PAR during relocation and contains
all the
information required for the supervisory or memory protection functions. Figure 6-33 shows the PDR.

Access Control Field (ACF)
This 2-bit field, occupying bits 2:1 of the PDR, contains the access rights to a particular page.

The keys
specify the manner in which a page may be accessed and whether or not a particular access
should
result in an abort of the current operation. In the context of access control, the term “write”
is used to
indicate the action of any instruction which modifies the contents of any addressable word.

6-46

USER

SUPERVISOR

KERNEL

PDR

PAR

PDR

PAR

PDR

| SPACE

v
07

PDR

PAR

PDR

PAR

PDR

D SPACE

TK-5352

Figure 6-32

Memory Management Relocation Registers

1 ] LPLFI 1 l

07
2

/ W //A ED ACF /
7

CACHE BYPASS
PAGE LENGTH FIELD

PAGE WRITTEN INTO

EXPANSION DIRECTION
(0 =UP, 1= DOWN)
ACCESS CONTROL FIELD
TK-5360

Figure 6-33 Page Descriptor Register

6-47

The access control keys are the following.

ACF

Description

Function

nonresident

abort all accesses

read only

illegal mode

abort all write attempts
abort all accesses

read /write

read or write allowed

It should be noted that the use of I space in conjunction with read-only access provides the user with
another form of protection, Execute Only.
Expansion Direction (ED)

|
Bit 3 of the PDR specifies the direction the page is to expand. If ED = 0, the page expands upward
from block number 0 to include blocks with higher addresses (Figure 6-34). If ED = 1, the page expands downward from block number 1773 to include blocks with lower addresses (Figure 6-35).

ACTIVE

PAGE

(APR)

PAR

PDR

000

0O0OOOOT 1

15 14

08 07 06

00101001Q0

PAF

PLF

CACHE

BYPASS

PAF = 000 1704

{

03 02

o1
1
ED

ACF

PLF=52g-1=51g=

LARGEST BLOCK

NO.

ED= 0=

UPWARD EXPANSION

/BLOCK 1774
/
ADDRESS

RANGE

OF EXPANSION
FOTENTIAL PAGE
BY
CHANGING THE

ANY BLOCK NUMBER

/BLOCK 176,

GREATER

THAN 51g

) ) (VA<12:06> GREATER THAN 5tg)

PLF

WILL CAUSE A PAGE
7
7,

LENGTH

ABOQORT.

BLOCK 524

00024176

BLOCK 51g

00024100

0170XX START OF PAGE
+51

BLOCKS

024 1XX

LAST BLOCK

00017276
AUTHORIZED

LENGTH =52g

(0-51g)

PAGE

BLOCKS

BLOCK 2

00017200

00017176
BLOCK

1
00017100

00017076
BLOCK

00017000

[«—BASE ADDRESS OF PAGE
TK-6381

Figure 6-34

Upward Expansion

6-48

Upward expansion is typically used for program space, and downward expansion for stack space.
Written Into (W)

The W bit, bit 6, indicates whether or not the specified page has been modified (written into) since
either the PAR or PDR was loaded (W = 1 is affirmative). The W bit is useful in applications which
involve disk swapping and memory overlays. It is used to determine which pages have been modified
and must be saved in their new form, and which pages have not been modified and can be simply overlayed.

The W bit is reset to 0 whenever the PAR or PDR associated with it is written into.

PAR

PAGE REGISTER (APR)

ACTIVE

PDR

15 14

000 0O OO OOOT11 1t 1 1 00 O
l
|
|

olt o1 ot
‘
|

PAF=2's COMPLEMENT¥
OF 525=1264 =

)

DOWNWARD EXPANSION

LOWEST BLOCK NO.

% 2'S COMPLEMENT =1'S COMPLEMENT + 1:
52g=0101010

1'S COMP= 1010101

1010110 =1264

00036776
BLOCK 1778

]

FIRST BLOCK OF DOWNWARD

EXPANDABLE PAGE

00036700

00036676
BLOCK 176g

AUTHORIZED PAGE
LENGTH=52g BLOCKS
(177g=1264)

367 FIRST BLOCK ADDRESS
_—52 BLOCKS

00036576
BLOCK 1758
00036500

126 PLF

126

316 LAST LEGAL BLOCK

OR
h—

/ PAGE
+170 MAX. BLOCKS

00031600

315 FIRST ILLEGAL ADDRESS

BLOCK

170 PAGE BASE ADDRESS

+177 MAX. BLOCKS / PAGE

00036600

[T
:

+52 NO. OF BLOCKS

—_—

37000=STACK POINTER

BLOCK 125g

ADDRESS RANGE

A BLOCK NUMBER

/Bg?/c-x f248

OF POTENTIAL PAGE

EXPANSION BY

CHANGING THE PLF

7, 00017176

BLOCK 1 ZZ]

00017100

SRS LESS
8

(VA <12 :06> LESS THAN 126g)
WILL CAUSE A PAGE

LENGTH ABORT.

| (00 017 000-00 03I 576)

00017176

BLOCK 077
7/08017000
<

Ja— BASE ADDRESS OF PAGE
TK-5360

Figure 6-35

Downward Expansion

6-49

ED=1=

BYPASS

PAF =000170¢

Ot 00

PLF

CACHE

03 02

0/111
7
7
ACF
ED

[

PAF

1 0

07 06

Page Length Field (PLF)
The 7-bit field occupying bits 14:08 of the PDR specifies the block number (BN) which makes up the
boundary of that page. The BN of the VBA is compared against the PLF to detect page length errors.

An error occurs when expanding upward if the BN is greater than the PLF, and when expanding downward if the BN is less than the PLF.
’
The PDRs are made up of 256 X 4 RAMs E68, E70, E67, and 256 X 1 RAM E87 on K1-7. The PDRs
are addressed in the same way as the PARs. They are written in the same manner as the PARs except
that K1-10 LOAD PDRH L and K1-10 LOAD PDRL L are used to enable the write inputs to E68,
E70 and E67. E87 and latch E89 are used for the W bit. The write enable signal is generated whenever
a page of a PAR or PDR is written into. K1-9 WRITE WBIT H, K1-1 REG CLK H, and K1-6 PAX
CI H are ANDed together by E109 to create this signal.
6.8.5 Memory Management Fault Logic
The memory management fault logic (K1-8) is used to notify the operating system of a memory management error, such as an attempt to access a nonresident page. The error logic consists of comparators
E81 and E92 and PROM E84. PROM E84 generates four errors which are determined by the existing
input conditions. A list of the inputs and their description is contained in Table 6-3. Table 6-4 lists the
outputs of the PROM and their description.

Table 6-3

Memory Management Fault PROM Inputs

Input Signal

Description

BUF DATA TRAN (1) H

When asserted, a bus data transfer is in progress.

UBUS C1, CO

Used to determine the type of data transfer being done (DATI,
DATIP, DATO, DATOB).

KT DISABLE MSYN L

Disables the memory management logic when the data transfer is
an odd address (byte address). The memory management logic uses
only word references.

MODE 01, 00

These two signals give the operating mode of the processor (kernel,
supervisor, or user).

ACF2, ACF1

These are the access control bits from the PDR and are used to notify the fault logic of the type of access the program has to the specific page.

Comparator E92 Output

Used with ED to determine if a page length error has occurred.

Expansion direction bit of the PDR used to determine if page ex-

pansion is up or down,

Chip Enable

Allows the memory management fault PROM to be enabled only
during a relocated bus transfer.

6-50

Table 6-4

Memory Management Fault PROM Outputs

Output

Description

Indicates a write access was attempted to a read-only page.

Indicates an attempt to address a memory location outside the spec-

ified page boundaries or the PSW contains an illegal processor
mode.

Indicates an attempt to access a nonresident page.

MAINT

Used for memory management maintenance purposes. Allows the

user to prevent relocation on the destination portion of a memory
cycle.

KT FAULT L

Used to signal that a memory management fault has occurred. Se-

lects the multiplexer input to SRO 15:13, 08. Starts the abort function.

Comparators E81 and E92, along with the expansion direction bit from the PDR, are used to determine
if a page length error has occurred. The comparators compare VBA 12:06 with the page length field in
the PDR (bits 14:08) to determine if the VBA page address is greater than, equal to, or less than the
PDR page length field. If the expansion direction of the page is up, then VBA 12:06 must be less than
or equal to the PLF or a page length error occurs. If the expansion direction is down, then VBA 12:06
must be greater than or equal to the PLF or a page length error occurs.

When a memory management error is detected K1-8 KT FAULT L is asserted, which selects PROM
E84 outputs as the inputs to SR0O 15:13, 08, along with aborting the data transfer that was in progress.
The output of E100 is clocked into SRO 15:14, 08 (E111) by K1-1 REG CLK H ANDed with K2-7
BUF DATA TRAN (1) H and either K1-8 KT FAULT L or LOAD SROH L. LOAD SROH L allows
the upper byte of SRO to be loaded from the SSMUX and K1-8 KT FAULT L loads SRO with a hardware-generated error condition. When any one of SRO bits 15:13, 08 is set, K1-8 ERROR H is asserted
which locks out any other attempts to change the contents of SRO. The register cannot be reloaded until
it has been cleared manually and K1-8 ERROR H is negated.
6.8.6

1 and D Space

The concept of 1 and D space is used in mapping information into separate physical memory scgments

depending on whether the information is considered instructions (I) or data (D). In PDP-11 architecture all instruction fetches, immediate mode operands, absolute addresses, and index words are located in | space; any other memory reference that does not fit into these categories is located in D
space. In the PDP-11/44 separate PARs and PDRs are used for I and D space relocations (Figure 632). Bits 02:00 of SR3 enable D space for each of the three processor operating modes: bit 00 user, bit
01 supervisor, bit 02 kernel. The hardware then selects the correct register set. If D space is not enabled
for a particular operating mode, all references are then relocated through I space.

The use of I and D space allows programs to exist in two virtual segments and effectively doubles the
addresses available to the user from 32K words to 64K words.

6-51

6.9 UNIBUS MAP
The UNIBUS map is the interface between the UNIBUS and main memory. It responds as a slave
device to UNIBUS signals and converts 18-bit UNIBUS addresses to 22-bit memory addresses.

The top 4K word addresses of the 128K UNIBUS addresses are reserved for the CPU and 1/O registers and are called the peripherals page (Figure 6-36). The lower 124K addresses are used by the
UNIBUS map to reference physical memory.

17 777

777

PERIPHERAL
PAGE

(4K _WORDS)

17 760 000
17 757

777

17 000

000

124K

(TO UNIBUS MAP)

1-4051

Figure 6-36

UNIBUS Address Space

The UNIBUS map is made up of a 21-bit adder (K4-8) and 32 mapping registers (K4-6) which may be
written or read. These registers are 21 bits wide and require two UNIBUS transactions for each read or

write. Therefore, 64 addresses are allotted to them on the 1/O page (Table 6-5). It should be noted that

the last mapping register (addresses 17 770 374 and 17 770 376) can be read and written, but cannot be
used to map UNIBUS addresses because it would be used by addresses in the range of the peripherals
page (17 760 000 — 17 777 777).
The UNIBUS map does relocation by adding one of 31 UNIBUS map registers, which contain a relocation constant, to the 18-bit UNIBUS address to create a 22-bit physical address (PA) which is used to
reference physical memory. When the UNIBUS map is disabled its operation is transparent to the user
and the incoming UNIBUS address is used to reference the first 124K of physical memory.
Figure 6-37 shows a block diagram of the UNIBUS map and its associated control logic.

6.9.1
Map Control
The map control logic (K4-4) is used to control the reading and the writing of the 32 map registers and
consists of UNIBUS map and boot address decode PLA (E45), a delay line (E69), and associated
read/write and buffer control logic. PLA E45 decodes the UNIBUS address to determine if a read or
write of the map registers is intended and asserts the appropriate signal, MAP WRITE L or MAP
READ L. MAP WRITE L and MAP READ L are used to generate MAP R/W L. MAP R/W L is
used to accomplish the following during a read or write of the map registers.
1.

Assert DISALLOW MEM MSYN. This keeps MSYN, intended for the map registers, from
being sent to main memory.

Asserts the input of delay line E69 which is used to generate UBI SSYN L (approximately

120 ns after MAP R/W L is asserted), and MAP SSYN H which is used to negate WRITE
MAP L.
3.

Assert MAP CE L which is the chip-enabling signal for the map registers.

6-52

Table 6-5

Access to Unibus Map Registers

UNIBUS Address for
Memory Reference

UNIBUS Address
Read or Write

0
1
2

17 770 200,
17 770 204,
17 770 210,

02
06
12

— 17 017 777
17 000 000
17 020 000 — 17 037 777
17 040 000
— 17 057 777

4
5
6
7

17 770 220,
17 770 224,
17 770 230,
17 770 234,

22
26
32
36

17100000 —-17 117 777
17 120 000
— 17 137 777
17 140 000— 17 157 777
17 160 000
— 17 177 777

10
11
12
13

17 770 240,
17 770 244,
17 770 250,
17 770 254,

42
46
52
56

17 200000
— 17 217 777
17 220 000 — 17 237 777
17 240 000 — 17 257 777
17 260 000 — 17 277 777

14
15
16
17

17 770 260,
17 770 264,
17 770 270,
17770 274,

62
66
72
76

17 300000
- 17 317 777
17 320000 — 17 337 777
17 340 000 — 17 357 777
17 360000 — 17 377 777

20
21
22
23

17 770 300,
17 770 304,
17 770 310,
17 770 314,

02
06
12
16

17 400 000 — 17 417 777
17 420 000 — 17 437 777
17 440 000 — 17 457 777
17 460 000 — 17 477 777

24
25
26
27

17 770 320,
17 770 324,
17 770 330,
17 770 334,

22
26
32
36

17 500 000 — 17 517 777
17 520000 — 17 537 777
17 540 000 — 17 557 777
17 560 000 — 17 577 777

30
31
32
33

17 770 340,
17 770 344,
17 770 350,
17 770 354,

42
46
52
56

17 600000 - 17 617 777
17 620 000 — 17 637 777
17 640 000 — 17 657 777
17 660000 - 17 677 777

34
35
36
*37

17 770 360,
17 770 364,
17 770 370,
17 770 374,

62
66
72
76

17 700 000 — 17 717 777
17 720 000 — 17 737 777
17 740 000 — 17 757 777
17 760 000 — 17 777 777

17 770 214,

17 060 000
— 17 077 777

*Can be read or written into, but not used for mapping.

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The remainder of the map control logic is used to steer the map output to the proper bus during a read
operation. Normally PD TO UBI H and PD TO UBI L are asserted and PAX data is passed directly to
the UNIBUS drivers. For a map read operation, these signals are negated and MAP TO UBI L is
asserted and causes the output of the map registers to be passed to the UNIBUS drivers.
6.9.2

Map Addressing and Relocation

Relocation expands the 18-bit UNIBUS address to the 22-bit main memory address. This allows the
UNIBUS to access any location in main memory. This relocation or mapping of addresses is done by
adding the contents of one of the mapping registers to bits (12:01) of the incoming UNIBUS address.
All mapping registers in the UNIBUS map are 21 bits wide. A 22nd bit, which is not writeable and is
always read as zero, acts as the lowest-order bit for each register. Each register specifies the 21-bit PA
of a 4K page residing on any word boundary in memory. The reason for using word boundaries is that
the mapping logic does not know if a byte operation is being executed, and if so, what byte is required.
Figure 6-38 illustrates the construction of a PA by the UNIBUS map. Bits (17:13) of the 18-bit
UNIBUS address select a map register. The remaining bits (12:00) of the UNIBUS address are used as
an offset into the page to which the mapping register is pointing.
When an address is taken off the UNIBUS, the mapping register is automatically selected and the
contents read out. That 21-bit address is added to the 12-bit offset in the UNIBUS address to form the
PA. This mapping function is very similar to that performed by memory management.
The program controls this process both by selecting the contents of the mapping registers and by its
ability to enable and disable the UNIBUS map relocation function.
The UNIBUS map is enabled by the assertion of E MAP H (bit 5 of SR3). The UNIBUS address lines
BA (17:00) are received by the map logic. BA 17:13 are selected by the map address multiplexer (E35,
55) to generate the address, RAM A 4:0, to the map registers. The output of the selected register, MAP
21:01 H, is sent to the adder, which is made up of ALUs E35, E46, E33, E44, E37 and carry generators
E26, where it is added to BA 12:01 to create MA 21:01. The output of the ALUs, MA 21:01, along with
BA 00 and ADRS OUT 21 H, are used to create the PA. These signals are then passed to the memory
bus (EUB) via buffers E30, E31, and E43.
When the UNIBUS map is disabled, bits 21:18 of the PA are set to 0 and BA 17:00 are used for bits
17:00 of the PA. This allows the UNIBUS to access the first 24K of main memory.

When a peripherals page address (17 760 000 — 17 777 777) is decoded by the map, U 1/O PAGE L is
asserted. U I/O PAGE L being asserted forces bits 21:13 of the PA to be set to ones and BA 12:00 are
used for bits 12:00 of the PA. This action forces a reference to the upper 4K of physical memory.
6.9.3

Addressing Limits

There are 31 mapping registers which can be accessed by the UNIBUS for relocation. The actual number is determined by two sets of five jumpers (K4-4) which are used to set the upper limit (W3-W7) and
the lower limit (W18-W12).
The lower limit jumpers are used to select the first address that will not be mapped to main memory
starting at UNIBUS address 0 up to the lower limit. The lower limit allows the UNIBUS space that
will be mapped to main memory to be expanded upward from UNIBUS address O up to 760 000 in 4K
word segments.

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The upper limit jumpers are used to select the first address that will not be mapped to main memory
starting at UNIBUS address 757 776 down to the upper limit. The upper limit allows the UNIBUS
space that will be mapped to main memory to be expanded downward from UNIBUS address 760 000
in 4K word segments.

Figure 6-39 shows how the addressing limits affect UNIBUS space. When the upper and lower limits

are set to address 0 (0K) or 760 000 (124K) or if the limits overlap (that is, lower limit = 400 000
(64K), upper limit = 417 776 (68K)) all of the UNIBUS space, with the exception of the I/O page,
will be passed to main memory.

NOTE

For CPU diagnostics to run properly it is necessary
to set both the upper and lower limits to UNIBUS
address 0 or 760 000.

17 777 777

1/0 PAGE

(128K)

17 760 000

(124K)

MAPPED TO MAIN MEMORY

UPPER LIMIT

e8k)

17 417 776

T 7 1 (EXPANDS DOWNWARD)
| -~

17100000

| _ _ — —

(16K)

17 000 000
(0K)

MAPPED TO MAIN MEMORY

LOWER LIMIT

(EXPANDS UPWARD)

TK-5346

Figure 6-39

6.10

UNIBUS Map Addressing Limits

CONSOLE PROCESSOR

The console processor consists of an 8085 microprocessor and associated logic. The console processor,

in conjunction with the console terminal, is used to interpret ASCII characters so they can perform the

equivalent functions of the “lights and switches” console of earlier processors.

The console terminal (the LA120 or equivalent used for the system console/programmer console) can
be operated in one of two modes.

Console Mode — the console is used to perform such functions as: start, halt, deposit, exam-

ine, continue, etc. The operation of the console is controlled by the 8085 microprocessor.

Program I1/O Mode — the console functions as the system console and is controlled by the

operating system of the CPU.

For an explanation of the console commands refer to Chapter 2.

Figure 6-40 is a block diagram that shows the addressing and data flow of the console processor.

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6.10.1

8085 Addressing

The 8085 microprocessor, as it is used in this application, when addressing a location will do one of two
cycles, a read or a write. The 8085 uses a 16-bit address when referencing its program store, random

access memory, or 1 /O locations.
The upper eight bits of the address are direct buffered onto the console address bus. The lower eight

bits, because they are multiplexed with data going to or from the 8085, are latched by E123 (K3-2) and
then buffered onto the console address bus. the 8085 controls E123 with the address latch enable
(ALE) signal.

The following paragraph is an example of an 8085 address as used in the PDP-11/44 console processor.
The upper eight address bits are asserted and buffered onto the console address bus by E127. At the
same time the upper eight address bits are asserted, the lower eight bits along with ALE are asserted.
After a certain period of time, ALE is negated and AD 07:00 of the 8085 change from address to data
lines. A 15:08 and the output of the latch (E123) remain asserted until the beginning of the next address cycle.

When the 8085 asserts an address, the upper eight address bits and the 1/0 signal from the 8085 are
decoded by the address decode select ROM (E126). The address decode select ROM determines
whether a program store, RAM, or I/O address has been asserted. The I/0O addresses are further decoded by the I/O address decode logic (E100, E102, E103, and E131). The outputs of the 1/O address
decode logic are used for two different functions:

Control functions.

The control functions are implemented by writing to the /O address that corresponds to the particular
function. There is no transfer of data to or from the 8085. Thus, by the 8085 writing to the correct 1/0

address, the selected control function is implemented. There are five control signals selected by the 1/0

addresses.
1.

SET MODE CONSOLE L - This signal is used to set the console mode flip-flop (K3-6, E62)
which enables the console mode operation of the console terminal.
Continue — This signal is used to clear the console processor inhibit of the PDP-11/44 CPU

clock by initiating a 130-ns continue pulse via one-shot E37 (K3-2). Note that the 8085 has to
read from this address, unlike the other four control signals which are written to.

SET PROG I/O L - This signal is used to clear the console mode flip-flop (K3-6, E62) and
return the console terminal to the program I/O mode.

LD VBUS DATA L - This signal enables the selected VBUS source by asserting K3-2
ENAB VBUS SOURCE and then puts the data on the PAX bus. The data on the PAX bus is

then trailing-edge clocked into the console’s PAX data in register by LD VBUS DATA L.
5.

MFM LOAD MPC L - This signal is used to load the next MPC via the console logic. This
signal enables the PAX data out multiplexer which puts the data onto the PAX bus. After

the data is on the PAX bus it is clocked into the next MPC registers, thereby loading the next
MPC.

All other 1/O locations addressed by the 8085 involve either the writing or reading of data to or from
the console data bus by the 8085.
6-60

Console Data Flow

6.10.2

The 8085 microprocessor, as it is used in this application, has only two types of I/O cycles: a read for
incoming data and a write for outgoing data. The data going to and coming from the 8085 microprocessor is transferred on the console data bus. Because the number of loads on the console data bus
are more than the 8085 can drive, it is necessary to buffer the data entering and leaving the microprocessor via its address/data lines (AD 07:00). Figure 6-40 shows the buffers and the different loads
on the console data bus.

When the 8085 is doing a read, it asserts K3-2 READ L (K3-2) which enables the incoming data buffer, E124 (K3-2), and the addressed data source (program store, RAM, I/O locations). The data is read
by the 8085 and then K3-2 READ L is negated to complete the read cycle. When the 8085 is going to
write data it asserts K3-2 WRITE L which enables the outgoing data buffer and also synchronizes the
write operation at the data’s destination. When the write cycle is completed (approximately 400 ns),
K3-2 WRITE L is negated. The output buffer (E125) is not disabled until 40 ns after K3-2 WRITE L
has been negated. This delay is needed to allow for any hold time requirements of the receiving logic.
The delay is created by the propagation of K3-2 WRITE L through the gates of E140 (Etch Rev. B E138) (K3-2) before the output buffer is disabled.
6.10.3

Console-to-PAX Interface

The console-to-PAX interface is the path by which the console processor communicates with the PDP11/44 processor. The PAX bus is the internal data and address bus of the CPU and is the route by
which all information going to or from the PDP-11/44 CPU must pass. The console-to-PAX interface is
made up of buffers, registers, and control logic necessary for the console processor to interface with the
PAX bus.

The logic for the console-to-PAX interface is located on K3-3 and K3-4 of the print set. The interface
consists of an outgoing 24-bit (22-bit address and 2 control bits) PAX address register (E67, E78, Eg9),
an outgoing 16-bit PAX data register (E33, E24), and an incoming 16-bit PAX data register [ES6, E42
(Etch Rev. B-E45)]. The control logic consists of flip-flop E110 and gates E12, E13, E15, E130 on K3-3
along with the VBUS and CPU system clock control logic on K3-4. The PDP-11/44 data transfer logic
(paragraph 6.5) is used to handle bus arbitration, timing, and detection of data transfer errors. This
eliminates the need to duplicate this logic in the console processor.

Nouvbk
WD —

To understand how the console-to-PAX interface works, an understanding of the various types of deposits and examines, used by the console processor, is needed. (For an explanation of the console commands, refer to paragraph 2.2.) An examine (E) command from the console is executed as follows.
Load data out registers with next MPC for MFM data in.
Load next MPC register in CPU.

Load the outgoing PAX address registers with the address to be examined.

Start the CPU clock to do the data transfer.
Read PAX DATI register.

Check for a transfer error by checking the CPU error register.
Convert binary data to ASCII and send to console terminal.

A deposit (D) command is similar to an examine command except that a different MPC is loaded into
the CPU and the data to be deposited is loaded into the data out registers. A deposit (D) command
ARl

from the console is executed as follows.

Load data out registers with next MPC for MFM data out.

Load next MPC register in CPU.

Load outgoing PAX address registers with location of where data is to be deposited.
Load data out registers with data.
Start CPU clock to do data transfer.
Check CPU error register for data transfer error.
6-61

A more detailed explanation of how an examine and deposit command functions is contained in the next
section, paragraph 6.10.4, Operation During Command Execution.
6.10.4 Operation During Command Execution
The operation of the console processor during command execution is a function of the software contained in the console processor’s program store. When doing any type of function that requires the transfer
of data to or from the console, some of the control for the data transfer is handled by the CPU data
transfer logic. During command execution, the console processor controls the manipulation of data
within itself, direct communication with the console terminal, control of the CPU clock and the loading
of the next MPC, if required.

A detailed explanation of a deposit command (D) best explains how the console processor functions
during command execution.
Deposit 5 into location 1000. This is entered at the console terminal as follows:
D(SP) 1000(SP)5 (CR)

The carriage return (CR) at the end of the command tells the console processor that the command is
complete and execution can start. The console processor first determines that a deposit is to be done
and then converts the address and data from ASCII to binary format and stores this information in
RAM. After this conversion is done, the command execution begins. First the console processor selects
an internal constant which will be used as the next MPC value in the CPU. When doing a deposit this
constant designates that an MFM data out is going to be done by the CPU. The console processor then
loads this constant into the PAX DATO registers in two write cycles by the 8085 microprocessor. MFM
LOAD MPC L (K3-2) is then asserted by the 8085 to put the MPC value on the PAX bus and clock it
into the next MPC registers in the CPU. After the MPC is loaded into the CPU, the console processor
sets up for the deposit by loading the PAX ADR registers (three write cycles by 8085) with the address
where the data is to be deposited and the PAX DATO registers (two write cycles by 8085) with the
data. The console processor also asserts FREE BUS H. This signal puts the PAX bus into a high impedance state and prevents any conflicting data from being on the bus when the transfer begins.
When the setup is complete the console processor is ready to let the CPU take control of the data transfer. This is accomplished by the console processor setting the XFER DONE bit and the WAIT bit in
the CON IR (K3-4 E90). By setting the WAIT bit, one-shot E35 is triggered and asserts K3-4 WAIT H
which triggers one-shot E37 (K3-2) to start the CPU clock by asserting K3-2 CONTINUE L. The CPU
now takes control of the transfer; this is done by the control logic on K3-3 (Figure 6-41). When the CPU
clock starts running, TRAN TO MFM L is asserted and direct sets flip-flop E110 as soon as CPU
ENAB ADRS H is asserted by the data transfer Logic (K4-1), approximately 60 ns after the clock
starts. The PAX address buffers are enabled by E110, when it is set, and put the address on the PAX
bus. A short time after CPU ENAB ADRS H is asserted, CPU DATO L is asserted, CPU DATO L is
ANDed with TRAN TO MFM L to assert ENAB DATA L. When ENAB DATA L is asserted, the
contents of the PAX DATO registers are put on the PAX bus and deposited in the addressed location.
When the transfer is complete, TRAN TO MFM L is negated and END TRAN L is asserted. END
TRAN L is ANDed with the output of E110 to clear thc CON IR and then clocks E110 to clear the
flip-flop. Clearing the CON IR clears the wait one-shot and restarts the 8085. Also, at the end of the
transfer, the CPU halts and returns control of the CPU clock to the console processor.
When the transfer is completed the console processor checks the CPU crror register to see if there was

a transfer error. If a transfer error has occurred and the transfer is not completed, the console processor
does not know until it checks the CPU error register. This is becausc the WAIT one-shot will timeout
and restart the 8085 in 220 ms if the CPU has not asserted END TRAN L before the one-shot times
out.

6-62

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K2-1 EXT PROC CLK L

K2-9 TRAN TO MFM L

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E12

‘

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‘E—_— E110
K2-9 END TRAN
TO MEM L

ENABLE PAX ADR REG

i K4-1 CPU ENAB
ADRS H

-O

E13

K3-3 CLR CON IR L
TK-5340

Figure 6-41

Console Processor to PAX, Interface Control Logic

An examine command is similar to a deposit except that there is no data that needs to be loaded into
the PAX DATO registers after the MPC constant for an examine has been loaded. Gates E12, E15,
and EXT PROC CLK L (Figure 6-41) are used to clock the incoming data into the PAX DATI registers. The console processor, after checking for a transfer error, converts the data and address from binary to ASCII and puts the information out on the console terminal. Note that when examining one of the
machine registers it is not necessary to load the PAX address registers because the VBUS register (K34, E122, E121) is used to select the source register in the CPU.

For a complete listing of the console commands and their functions refer to paragraph 2.2.
6.11

SERIAL LINE UNITS

The multifunction module (MFM) contains two serial line units (SLUs): a console terminal SLU and a

TUS58 SLU. The following paragraphs describe each unit separately, except where areas of logic are
shared (for example, address and interrupt logic).
6.11.1

Console Terminal SLU

The console terminal SLU (Figure 6-42) provides the 1/O port for an LA36 or LA120 serial terminal or
cquivalent. The console terminal operates in two modes: as the standard system terminal (program I/0O
mode) or as a programmer’s console (console mode). In console mode, the terminal is used in conjunction with the 8085 microprocessor to functionally replace the switch register and light display of
the traditional control panel. In this mode, all characters input on the terminal are interpreted as commands to the processor control section or as commands to verify and control the console logic.
In cither console or program mode, the console terminal SLU enables the transfer of data between the
console processor or CPU (parallel data) and the external terminal (serial data). The major functional
area of this unit is a universal asynchronous receiver/transmitter (UART).

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6.11.1.1 Transmitter Operation (Terminal UART) - Parallel data to be transmitted from the processor
to the terminal is input to the UART transmit data lines (XD 7:0). The source for the transmit data is a
multiplexer which selects either the console data bus (K3-2 CON DATA 7:0) or the PAX data bus (K31 PX D 07:00). This multiplexer is clocked under two circumstances:
1.

when the central processor performs a DATO operation to the terminal transmitter buffer via
the PAX data bus (K3-5 TERM XMIT DATA CLK L is generated), or

when the console processor writes data to the terminal via the console data bus (K3-2 LD
SER XMIT DATA L is generated).

In both circumstances, the signal that clocks the multiplexer also triggers a 300-ns one-shot which generates the data strobe (K3-6 LD XD L) signal on the UART. The 300-ns one-shot keeps the load signal
low for the time period required by the UART transmitter. The parallel-loaded character is converted
by the UART to serial data and is output through the SER OUT line of the UART. When the transmitter buffer is emptied, the UART generates the transmit ready line (K3-6 XMIT READY H) indicating a new character can be loaded. The format of the serial character is determined by control
inputs to the UART. These inputs can be enabled or disabled by the following jumpers and switch:
Jumper /Switch

Function

Jumpers W7 and W8

These jumpers specify the character length as follows:

W7
W38

5 Bits

6 Bits

7 Bits

8 Bits

In
In

In
Out

Out
In

Out
Out

Jumper W6

Parity is generated and detected when this jumper is in.

Jumper WO

Odd/even parity select. When this jumper and W6 are in, odd parity will be generated and checked.

Switch E6 — Position 1

~Stop bit select. This switch position is on for 1 stop bit and off for 2
stop bits. This position is also off for 1.5 stop bits if a 5-bit character
length has been selected.

The serial character (K3-6 MFM SER OUT H) is transferred from the MFM to the console interface
module (CIM) where it can be output to the terminal. The rate at which the character bits are transmitted (baud rate) is switch selectable. Refer to paragraph 6.11.1.3.

6.11.1.2 Receiver Operation (Terminal UART) - The receiver section of the UART accepts a serial
character from terminal for conversion to parallel data. The receiver samples the serial input line (SER
IN) at selected edges of the receiver clock (RCLK). The source of data for the serial input line is a
multiplexer. During normal operation, the multiplexer selects serial data from the console interface
module (CIM-1 MFM SER IN H). In maintenance mode, the multiplexer selects the SER OUT line
of the UART. This enables the closed-loop test of the receiver and transmitter.

The receiver enters the data entry state when it detects a mark-to-space (high to low) transition of the
serial input line. If the receiver control logic has been set up to detect parity (jumper W6 IN), the
receiver checks the parity of the data bits plus the parity bit following the data bits. The receiver compares the parity of these lines with the parity select line (pin 39 of the UART). If the parity of the
received character differs from the parity of the UART control logic, the parity error line (K3-6
TERM P ERR H) is asserted and bit 12 of the terminal receiver buffer register is set.
6-65

The receiver samples the first stop bit which occurs after the parity bit or after the data bits if no parity
is selected. If the stop bit or bits are valid, it indicates that the entire character has been received and
shifted into the receiver shift register. The receiver then parallel transfers the contents of the shift register into the receiver data holding register, and sets the data available line (K3-6 RCVR DONE H).
If the receiver samples the first stop bit and it is low, this indicates an invalid stop code. The UART will
then generate a framing error signal (K3-6 TERM FR ERR H) which sets bit 13 of the terminal receiver buffer register.
In addition to the parity error and framing error conditions, a third error condition (overrun) is associated with receiver operation. The overrun condition indicates that a new character is being loaded into
the UART before the previous character has been read. Under these circumstances, the UART generates K3-6 TERM OR ERR H which sets bit 14 of the terminal receiver buffer register.
The serial character received is converted by the UART to parallel data (K3-6 TERM R DATA
07:00). The central processor can read this data by reading the terminal receiver buffer register. The
console processor can read the parallel data via the console data bus (K3-2 CON DATA 07:00 H).
Also, the character is decoded to determine if it is the console break character (ASCII AP). If the
character is decoded as AP (020g or 220g), the console terminal enters console mode.
6.11.1.3 Conscle Terminal Baud Rate Logic — The baud rates for the console terminal receiver and
transmitter are derived from a 5.52960 MHz master oscillator and frequency divider circuits. The oscillator drives the internal clock generator of the 8085 microprocessor (K3-2). The clock output of the
8085 1s used to generate two timing signals (K3-2 MFM CLK H and K3-2 MFM CLK L) which are
used as the clock inputs of the frequency dividers.
The frequency divide circuits have switch-selectable inputs which determine the receiver and terminal
clock frequencies and the corresponding baud rate of each. Table 3-14 lists the switch settings and resulting baud rates.
NOTE
The frequencies required by the UART are 16 times
the desired baud rate.
The clock outputs of the two frequency dividers (K3-6 TERM RCLK H and K3-6 TERM XCLK H)
are input to a multiplexer. In the normal mode of operation, K3-6 TERM RCLK H is fed into the

receiver clock input of the UART and K3-6 TERM XCLK H is fed into the transmitter clock input. In
maintenance mode, the multiplexer is selected so that K3-6 TERM XCLK H is fed into both the receiver and transmitter inputs of the UART, thereby ensuring the same baud rate for both.
6.11.2 TUS8 SLU
The TUS58 SLU (Figure 6-43) provides the 1/0 port for the TUS8 tape unit. Operation of this serial line
unit is very similar to that of the console terminal SLU. Serial data transferred to and from the TUS5S is
converted to parallel data for the central processor. As in the console terminal SLU, the major functional unit is the UART.
6.11.2.1

Transmitter Operation (TUS8 UART) - Parallel data from the processor (K3-1 PX D07:00)
is loaded into the UART transmitter when the processor performs a DATO to the TUS58 transmitter
buffer. The address logic generates K3-5 TU58 XBUF WRITE L which triggers a 300-ns one-shot. The

output of the one-shot clocks the PAX data latch and keeps the data strobe (K3-7 LD XD TUS58 L) low

for the time period required by the UART transmitter.

6-66

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The parallel data loaded from the PAX data bus is converted by the UART to serial data and transmitted through the SER OUT line of the UART. The serial data (K3-7 TU58 SER OUT H) is transferred from the MFM to the console interface module where it is output to the TUS58. The format of the
serial data is determined by control inputs to the TU58 UART, which are jumper and switch selectable.
The following describes the function of the associated jumpers and switch.

Jumper/Switch

Function

Jumpers W12 and W13

These jumpers specify the character length as follows:

W12

W13

S5 Bits

6 Bits

7 Bits

8 Bits

In
In

In
Out

Out

Jumper W1l

Parity is generated and detected when this jumper is in.

Jumper W14

Odd/even parity select. When this jumper and W11 are in, odd parity will be generated and checked.

Switch E7 — Position 7

Stop bit select. This switch position is on for 1 stop bit and off for 2
stop bits. This position is also off for 1.5 stop bits if a 5-bit character
length has been selected.

6.11.2.2 Receiver Operation (TUS8 UART) - The receiver accepts serial data TUS8 (CIM—-1 TUS8
SER IN H) from the console interface module. During normal operations the serial TUS58 data is selected by a multiplexer as the SER IN source of the UART. In maintenance mode, the multiplexer
selects the SER OUT line of the UART as the SER IN source.
The receiver samples the serial input line and enters the data entry state when it detects a mark to
space (high to low) transition. If parity detection has been enabled (jumper W11 in), the receiver
checks the parity of the data bits plus the parity bit following the data bits. If the checked parity differs
from the expected parity, the UART generates K3-7 TU58 P ERR H which sets bit 12 of the TU58
receiver buffer register.
If the receiver samples the stop code and it is valid, the entire character is shifted into the receiver shift
register. The receiver then parallel transfers the contents of the shift register into the receiver data
holding register, and sets the data available line (K3-7 TU58 R DONE H).
A framing error signal (K3-7 TU58 FR ERR H) is generated if the receiver detects an invalid stop
code. This sets bit 13 of the TUS8 receiver buffer register. An overrun error signal (K3-7 TU58 OR
ERR H) is generated if a new character is being loaded into the UART before the previous character is
read.

The serial data received from the TUS8 is converted by the UART to parallel data (K3-7 TUS8 R
DATA 07:00). The central processor can read this data by reading the TUS58 receiver buffer register.
6.11.2.3 TUS8 Baud Rate Logic — The baud rate for the TUS8 receiver and transmitter is derived
from a 5.52960 MHz master oscillator and a synchronous counter. The oscillator output is fed into the
clock input of the counter. The counter generates K3-2 614.4 KHz H (38.4K baud) which can be selected as the source for the receiver clock and transmitter clock.

6-68

K3-2 614.4 KHz H also supplies the input to a divide-by-four counter which genefates K3-7 153.6 KHz

H (9.6K baud) which can be selected as the source for the receiver clock and the transmitter clock.
Note that the frequency used by the UART is 16 times the selected baud rate.

The source for the TUS58 baud rate is switch selectable for both the receiver and transmitter. In addition to the standard 38.4K baud and 9.6K baud rates and the console terminal receiver rate can be
selected as the source. Table 6-6 lists the switch settings for the possible TUS58 baud rates.

Table 6-6

TUS8 Baud Rate Selection

Switch E7 (K3-7)
1
2
3
4
5
6

Receiver Switch Locations
Transmitter Switch Locations

Baud Rate
38,400
9,600
Console Terminal Receiver Baud Rate

Off

NOTE: Switch positions E7-1 through E7-6 should not be set up in any combination other than those shown in Table 6-6. The
baud rate sources for the transmitter and receiver do not have to be the same.

6.11.3 Address Selection
The address selection logic (Figure 6-44) is shared by the console terminal SLU and the TU58 SLU.
The PAX address and control lines (PX A21:00, PX C1:C0) are decoded to determine which of nine
SLU registers is to be read or written from the central processor. Bit descriptions of each register are
provided in paragraph 6.11.4. The address of the console terminal registers and line clock register are
fixed as follows.
Address

Console Terminal Register

17777560

Terminal Receiver Status Register

17777562

Terminal Receiver Buffer Register

17777564

Terminal Transmitter Status Register

17777566

Terminal Transmitter Buffer Register

17777546

Line Clock Status Register

NOTE

The console terminal registers can be disabled by removing jumper W1 (K3-5). The line clock register
can be disabled by removing jumper W2 (K3-5).

6-69

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The base address of the TU58 registers is switch selectable and falls within the range of 17760000 to
17777770. The base address corresponds to the TUS58 receiver status register. The following shows the
TUS8 register addresses with respect to the selectable base address.

NOTE
Bits 3 through 12 are switch selectable.
Address

TUSS8 Register

177XXXX0
177XXXX2
177XXXX4
177XXXX6

TUS58 Receiver Status Register
TUS8 Receiver Buffer Register
TUS8 Transmitter Status Register
TUS58 Transmitter Buffer Register

The format of the address lines is shown in Figure 6-45. Address lines PX A21:13 must be all ones. This
specifies an address within the top 4K address space which is dedicated to device registers. If the first
five octal digits of the address are decoded as 1777756X, a terminal register has been selected for the

operation. The final octal digit (address line PX A02, PX AOl, PX A00) determines which register has
been selected and whether a word or byte operation is to be performed. The line clock register is selected if address 17777546 is decoded.
Address lines PX A12:A03 are switch selectable for the TUS8 base address. The switches are configured with exclusive OR gates so that when the switch is closed, it will match a one (high) on the
associated address line. A match of all the address lines will generate the control line K3-5 TUSS L.
This control line can be enabled or disabled by a switch (E79-1). When this switch is closed, the TU58
address decode is enabled. Address lines PX A02:A01 select one of the four TUS8 registers.

21201918
17 16 15 14 1312 1110 9
TMT1T

1yt

1111

111

1)1

ILO

J
REGISTER
SELECT

LTC OR

BYTE

TERM

CONTROL

SELECT
A. TERMINAL OR LINE CLOCK FORMAT

PX
A

21201918

171615

141312

1110
9

0
I

vt ]1t

1111

7
SWITCH

|
|

POS!TION—: 1

N
SELECTED BY SWITCH E70

9101

BYTE

CONTROL

Figure 6-45

SLU Address Format

6-71

Three additional lines are input to the address decode logic: K3-1 MSYN H, K3-1 PX C1 H, and K3-1
PX CO H. The master synchronization line (MSYN) indicates that the processor is bus master and
enables the address control lines. The C1 and CO lines determine the type of operation to be performed:
C1

Type of data transfer

DATI

DATIP

DATO

DATOB

The address selection logic generates a number of control signals which affect the SLU registers. The

following provides a brief description of each signal.

Control Signal

Destination

Function

K3-5 ENAB READ L

K3-3

Selects the serial data input to the PAX data
multiplexer. This allows one of the terminal or
TUSS8 registers to be read onto the PAX data
bus.

K3-5 XBUF READ H

K3-8

Disables the multiplexers so that all zeros will
be read when a DATI or DATIP is performed
on the terminal transmitter buffer register.

K3-5 LTC WRITE L

K3-8

Clocks PAX data bit 06 into the LTC interrupt
enable flip-flop, and clocks data bit 7 (only
when zero) into the line clock monitor flip-flop.

K3-5 TERM XMIT DATA CLK L

K3-6

This signal is a 100-ns low pulse which is used
to clock the terminal transmitter data multiplexer and the terminal UART transmitter buffer.

K3-5 TAKE PAX DATA L

K3-6

Selects the PAX data input to the terminal
transmitter data multiplexer.

K3-5 SEND SSYN H

K3-1

Returns PAX SSYN to the processor on a valid
address selection.

K3-5 TERM XCSR WRITE H

K3-6

Clocks PAX data bits 06, 02, and 00 into terminal transmitter status register bits 06, 02, and
00, respectively.

K3-5 TERM CLR R DONE L

K3-6, K3-8

Generated when the terminal receiver buffer
register is read, indicating that a new character
may be loaded into the receiver. This signal
CLR R DONE on the terminal

generates

UART and also enables the terminal error bits
to be read as bits 15:12 of the terminal receiver
buffer register.

6-72

Control Signal

Destination

K3-5 TERM RCSR WRITE H

K3-6

K3-5 TU58 XBUF WRITE L

K3-7

K3-5 TUS8 XCSR WRITE H

K3-7

K3-5 TU5S8 CLR R DONE L

K3-7, K3-8

Function

Clocks PAX data bit 06 into terminal receiver

status register bit 06.

Clocks PAX data bits 07:00 into the TUSS8

transmitter buffer register.

Clocks PAX data bits 06, 02, and 00 into the

TUS8 transmitter status register bits 06, 02,
and 00, respectively.

Generated when the TUS8 receiver buffer register is addressed, indicating that a new character may be loaded into the receiver. This signal
generates CLR R DONE on the TU58 UART
and also enables the TUSS8 error bits to be read
as bits 15:12 of the TUS8 receiver buffer register.

K3-5 TU58 RCSR WRITE H

K3-7

Clocks PAX data bit 06 into TUS58 receiver status register bit 06.

Each of the address control signals are used to read or write bits in the TUS8 and terminal registers.
The format and bit descriptions of the registers are described in paragraph 6.11.4.
6.11.4 Console Terminal and TUS8 Register Descriptions
This section provides the format and bit descriptions of each device register associated with the console
terminal and TUS58 serial line units and the line clock. Each of these bits are fed into the serial multiplexer (K3-8). The address decode logic controls which SLU register will be selected by the serial multiplexer. The output of the serial line data multiplexer (K3-8 SER D 15:00 H) is fed into the PAX data
multiplexer (K3-9). When the address decode logic detects a valid line clock or SLU register address,
the serial line data input to the PAX data multiplexer is selected and the PAX data lines (K3-1 PAX
D15:00 H) are enabled.

6.11.4.1

Terminal Receiver Status Register — The terminal receiver status register (Figure 6-46) pro-

vides two bits which monitor the receiver logic and enable an interrupt sequence.

Each of these bits is described in the following paragraphs.

17777560

07
R

NOT USED—-—],

06 05

|R/w

TERM RCVR DONE
TERM RCVR INT ENAB

NOT USED
TK-4370

Figure 6-46

Terminal Receiver Status Register

6-73

Terminal Receiver Done (Bit 07) — This is a read-only bit which indicates that a full character has been
received from the terminal and has been stored in the UART parallel output register. This bit can only
be set if the terminal is in program [/O mode. It is inhibited if the character received was an ASCII
020 or 220 ( A P). This character holds the done bit clear and thus prevents further program output.
The done bit is ANDed with the interrupt enable signal (K3-6 TERM REC INT ENA H) to clock the
receiver interrupt request flip-flop. Setting of the flip-flop generates K3-6 REQ TERM REC INT H
which initiates an interrupt sequence.
This bit is cleared by the signal K3-6 CLR R DONE BUF L which is generated by INIT or by one of

the following conditions.
1.

The PAX address logic generates K3-5 TERM CLR R DONE L.

The console processor address logic generated K3-2 READ SER REC DATA L.

Both conditions indicate that the terminal receiver buffer register was addressed and that a new character may be loaded into the receiver. Either signal will also generate CLR R DONE on the UART.
Terminal Receiver Interrupt Enable (Bit 06) — This is a read/write bit. It enables an interrupt sequence

to be initiated when the TERM R DONE bit is set, indicating that a character has been received and is
ready for transfer to the PAX data bus. Bit 06 is written when a write operation to the terminal receiver
status register is decoded by the address logic. The signal K3-5 TERM RCSR WRITE H clocks PAX
data bit 06 (K3-1 PX D06 H) into the interrupt enable flip-flop. This bit is cleared by INIT.
6.11.4.2

Terminal Receiver Buffer Register — The terminal receiver buffer register (Figure 6-47) con-

sists of four error bits and eight data bits associated with the UART receiver.

17777562

| R

| R |

TERM ERROR-]

TERM OR ERROR
TERM FR ERROR
TERM PAR ERROR
NOT USED
TERM RCVR DATA
TK-4371

Figure 6-47

Terminal Receiver Buffer Register

Terminal Receiver Error Bits (Bits 15 to 12) — The four error bits of the buffer register are set to in-

dicate improper receiver operation. These bits are read only and can be disabled by removing jumper
W4 (shown on print K3-8). Three of the error bits are generated by the UART and the fourth bit
(TERM ERROR) is the inclusive-OR of the other three. The error bits are described as follows.

Overrun Error (TERM OR ERROR) - Generated by the UART when R DONE was not
resct prior to receiving a new character. This indicates that the UART received a new char-

acter before the processor read the previous character.
2.

Framing Error (TERM FR ERR) — Generated by the UART to indicate that the character

read has no stop bit.

6-74

Parity Error (TERM P ERR) — Generated by the UART to indicate that the parity received
does not agree with the parity expected.
‘

Terminal Error (TERM ERROR) — Indicates that any one or more of the other three error
bits is set.

Each of the error bits is updated when a new character is received. All four bits are cleared on a powerup when DCLO becomes unasserted.
- Terminal Receiver Data Bits (Bits 07 to 00) — The receiver buffer is read only and is loaded by the
UART. The UART receives the serial data from the terminal, converts it to parallel data and places it
on the terminal receciver data lines (K3-6 TERM R DATA 07:00). This data can then be read by the
central processor or the console processor.
6.11.4.3 Terminal Transmitter Status Register — The terminal transmitter status register (Figure 6-48)
contains both transmitter status information and maintenance information.

17777564

NOT USED

R|RW|

|RW

00
R/W

TERM XMIT RDY
TERM XMIT INT ENAB
CIM REMOT

ENAB CONSOLE
RD BIT ENAB
TERM MAINT

NOT USED
TERM BREAK
TK-4372

Figure 6-48

Terminal Transmitter Status Register

Terminal Ready (Bit 07) — This is a read-only bit that indicates the terminal transmitter buffer if ready
to accept another character from the PAX data bus.
This bit also initiates an interrupt sequence if bit 06 is set. The ready bit is ANDed with the interrupt
enable signal (K3-6 TERM XMIT INT ENA H) to clock the transmitter interrupt request flip-flop.
Setting of this flip-flop generates K3-6 REQ TERM XMIT INT H which initiates an interrupt sequence.

Bit 07 is set by the initialize signal (K3-1 INIT L) and is the transmitter ready output of the UART,
indicating that the transmitter buffer is empty. Terminal ready is cleared by K3-6 LD XD L, which is
generated when the transmitter buffer is being loaded with data.
Note that bit 07 can only be set when the terminal is in program 1/O mode. If the terminal is in console
mode, this bit and the associated interrupt sequence to the processor are inhibited. This enables the
console processor to load a character into the transmitter buffer via the console data bus (K3-2 CON
DATA 7:0). The signal K3-6 XMIT READY H notifies the console processor that the transmitter buffer is ready.
6-75

Terminal Transmitter Interrupt Enable (Bit 06) — This is a read/write bit. Bit 06 enables an interrupt
sequence to be initiated when bit 07 (terminal ready) is set, indicating that the terminal transmitter
buffer can accept another character. This bit is written when a write operation to the terminal transmitter status register is decoded by the address logic. The signal K3-5 TERM XCSR WRITE H clocks
PAX data bit 06 (K3-1 PX D06 H) into the interrupt enable flip-flop. This bit is cleared by INIT.
Console Interface Module Remote (Bit 05) — This bit is read-only and indicates that the system is being
operated in the remote diagnosis mode.
Enable Console (Bit 04) — This bit is read-only and indicates that the system terminal is operating in
console mode.
Enable Remote Diagnosis Status Bits (Bit 03) — This is a switch-selectable read-only bit. When switch
E79-2 is ON (causing bit 03 to be set), bits 05 and 04 are enabled and can be read in the terminal
transmitter status register; otherwise these three bits are always zero.

Terminal Maintenance (Bit 02) — This is a read /write bit. When set, a closed loop test of the terminal
UART can be performed. The serial output of the transmitter is fed back to the serial input of the
receiver. The receiver is forced to run at transmitter speed. This bit is written by clocking PAX data bit
02 (K3-1 PX D02 H) into the TERM MAINT flip-flop. This bit is cleared by INIT and disabled if the
terminal is in console mode.
Terminal Break (Bit 00) — This is a read/write bit. When set, a continuous space (low or zero logic

level) is transmitted to the terminal. It can be disabled by removing jumper WS5. This bit is written by
clocking PAX data bit 00 (K3-1 PX D00 H) into the TERM BREAK flip-flop. Bit 00 is cleared by
INIT and disabled if the terminal is in console mode.

6.11.4.4 Terminal Transmitter Buffer Register — The terminal transmitter buffer (Figure 6-49) is a
write-only register that receives parallel data from the PAX data bus (K3-1 PX D07:00 H) or the console data bus (K3-2 CON DATA 7:0 H).

The parallel data is loaded into the UART for serial conversion and transmission to the terminal. The
two data sources for the transmitter buffer are multiplexed. If the signal K3-5 TAKE PAX DATA L is
asserted, the PAX data bus is selected as the source.
Two signals can be generated which clock the data from the multiplexer onto the transmit data lines.
The signal K3-5 TERM XMIT DATA CLK L is generated by the address decode logic to clock the
PAX data lines. The signal K3-2 LD SER XMIT DATA L is generated by the console processor address logic to clock the console data lines. When either of these signals is generated, the resulting clock
signal triggers a 300-ns one-shot. The one-shot keeps the data load signal (K3-6 LD XD L) low for the

time required by the UART transmitter.

08 07

17777566

00
W

TERM XMIT DATA

NOT USED

TK-4373

Figure 6-49

Terminal Transmitter Buffer Register

6-76

6.11.4.5 Line Clock Status Register — The line clock status register (Figure 6-50) contains two bits
associated with line clock operation: an interrupt monitor bit and an interrupt enable bit.

15
17777546

06 05

{R/W

NOT USED—I

)

LTC INT MON

LTC ENAB
NOT USED
TK-4378

Figure 6-50

Line Clock Status Register

Line Clock Monitor (Bit 07) — This is a read-only bit which provides noninterrupt mode timing information and allows software to measure time intervals.

The LTC interrupt monitor flip-flop is clocked by K3-8 BUS LTC L. This signal is a square wave with
the same frequency as the ac power and is generated in the power supply. The line clock monitor bit is
set once for each cycle of ac power. The program must clear the bit each time it becomes set, if interrupts are disabled. The program clears the bit by writing the line clock status register with PAX data
bit 07 low. This will also disables the line clock interrupt request (K3-8 BR6 REQ L) at the same time
if the interrupt has not occurred.

Line Clock Interrupt Enable (Bit 06) — This is a read/write bit which allows the generation of timed
interrupt sequences. Interrupt sequences occur at time intervals of 16-2/3 ms (60 Hz) or 20 ms (50
Hz), depending on the frequency of the ac power. This bit is set when the line clock status register is
written (K3-5 LTC WRITE L) with PAX data bit 06 high. When bit 06 is set, the direct-clear signal is
removed from the interrupt request flip-flop. This enables the interrupt request flip-flop to be set on the
next falling edge of K3-8 BUS LTC L. This generates the BR6 interrupt request line and initiates an
interrupt sequence.

6.11.4.6

TUS5S8 Receiver Status Register

The TUS8 receiver status register (Figure 6-51) provides a receiver done monitor bit and interrupt enable bit for the TUS58 receiver logic.
15

177 XXXX0

NOT USED—‘\r

[R/W

TUus8 RCVR DONE

TUB8 RCVR INT ENAB
NOT USED
TK-4374

Figure 6-51

TUS58 Receiver Status Register

6-77

TUS8 Receiver Done (Bit 07) — This is a read-only bit which indicates that the UART has received a
full character from the TUS8. The done bit is ANDed with the interrupt enable signal (K3-7 TUS8
REC INT ENA H) to clock the receiver interrupt request flip-flop. This generates K3-7 REQ TUS58
REC INT H which initiates an interrupt sequence.
The done bit is cleared by the signal K3-7 TU58 CLR DONE L which generates the CLR R DONE
signal on the UART. The clear signal is generated by INIT or by the processor reading the TUS8 receiver buffer register (K3-5 TUS8 CLR R DONE L is generated). Once the receiver buffer has been
read, a new character may be loaded into the receiver.
TUS8 Receiver Interrupt Enable (Bit 06) - This is a read/write bit. It enables an interrupt sequence
when the TU58 R DONE bit is set, indicating that a character has been received and is ready for
transfer to the PAX data bus. This bit is written when the address logic decodes a write operation to the
TUS8 receiver status register. The signal K3-5 TU58 RCSR WRITE H clocks PAX data bit 06 (K3-1

PX D06 H) into the interrupt enable flip-flop. This bit is cleared by INIT.
6.11.4.7

TUSS8 Receiver Buffer Register — The TUS58 receiver buffer register (Figure 6-52) consists of
four error bits and eight data bits associated with the TU58 UART receiver.

177xxxx2l

08 07

| R|{ R | R

TUS8 ERROR

NOT

TUS8 OR ERROR

TUS8 RCVR DATA

USED

TUS58 FR ERROR
TU58 P ERROR
TK-4375

Figure 6-52

TUS58 Receiver Buffer Register

TUS8 Receiver Error Bits (Bits 15 to 12) — The four error bits of the buffer register are set to indicate
improper receiver operation. These bits are read only and can be disabled by removing jumper W3
(shown on print K3-8). Three of the error bits are generated by the UART and the fourth bit (TU58
ERROR) is the inclusive-OR of the other three. The error bits are described as follows.

Overrun Error (TU58 OR ERROR) - Generated by the UART when R DONE was not
cleared prior to receiving a new character. This indicates that the UART received a new

character before the processor read the previous character.
2.

Framing Error (TU58 FR ERR) — Generated by the UART to indicate that the character
read has no stop bit.
Parity Error (TU58 P ERR) — Generated by the UART to indicate that the parity received

does not agree with the parity expected.
4.

TUSS8 Error — Indicates that one or more of the other three error bits is set.

Each of the error bits is updated when a new character is received. All four error bits are cleared by

INIT.

6-78

TUS58 Receiver Data Bits (Bits 07 to 00) — The receiver buffer is read only and is loaded by the UART.
The UART receives the serial data from the TU58, converts it to parallel data and places it on the
TUS8 receiver data lines (K3-7 TU58 R DATA 07:00). This data can then be read by the central proCESSOr.

6.11.4.8

TUS5S8 Transmitter Status Register — The TU58 transmitter status register (Figure 6-53) con-

tains transmitter status information and maintenance information.

177 XXXX4

07
R

06 05

|R/W

02
R/W

00
R/W

NOT USED—:I/

TUS8 XMIT RDY
TUB8 XMIT INT ENAB

NOT USED
TU58 MAINT
NOT USED

TU58 BREAK
TK-4376

Figure 6-53

TUS58 Transmitter Status Register

TUS58 Ready (Bit 07) — This is a read-only bit that indicates the TU58 transmitter buffer is ready to
accept a character from the PAX data bus. The ready bit initiates an interrupt sequence if bit 06 is set.
"It is ANDed with the interrupt enable signal (K3-7 TUS8 XMIT INT ENAB H) to clock the transmitter interrupt request flip-flop.

Setting of the request flip-flop generates K3-7 REQ TU58 XMIT INT H which intitiates the interrupt
sequence.

TUS58 Transmitter Interrupt Enable (Bit 06) — This is a read /write bit. It enables an interrupt sequence
to be initiated when bit 07 (TU58 READY) is set. Bit 06 is written when the address logic decodes a
write operation to the TUS58 transmitter status register. The signal K3-5 TU58 XCSR WRITE H
clocks PAX data bit 06 (K3-1 PX D06 H) into the interrupt enable flip-flop. This bit is cleared by
INIT.

TUS58 Maintenance (Bit 02) — This is a read /write bit. When set, a closed loop test of the TU58 UART
can be performed. The serial output of transmitter is fed back to the serial input of the'receiver and the
receiver is forced to run at transmitter speed. This bit is written by clocking PAX data bit 02 (K3-1 PX
D02 H) into the TU58 MAINT flip-flop. This bit is cleared by INIT.

TUS58 Break (Bit 00) — This is a read/writc bit. When set, a continuous space is transmitted to the
TUS58. It can be disabled by removing jumper W10. This bit is written by clocking PAX data bit 00
(K3-1 PX D00 H) into the TU58 BREAK flip-flop. Bit 00 is cleared by INIT.

6-79

6.11.4.9 TUSS8 Transmitter Buffer Register — The TUS58 transmitter buffer (Figure 6-54) is a writeonly register that receives parallel data from the PAX data bus (K3-1 PX D07:00 H).

08 07

177XXXX6

NOT USED

TUB8 XMIT DATA

J
TK-4377

Figure 6-54

TUS58 Transmitter Buffer Register

The parallel data is loaded when the processor writes the transmitter buffer. The address decode logic
generates K3-5 TU58 XBUF WRITE L that clocks the PAX data latch and triggers a 300 ns one-shot.
The one-shot keeps the data load signal (K3-7 LD XD TUS58 L) low for the time required by UART

transmitter. The parallel data is then converted for serial transmission to the TUS5S.
6.11.5

Interrupt Request Logic

The interrupt request logic enables the console terminal SLU, TU58 SLU, and line clock to interrupt

the processor and initiate a service routine. Each of these devices will direct the processor to the correct

routine by sending an appropriate vector. The following are the vectors corresponding to each device
interrupt.

Device

Vector

Line Clock
Terminal Receiver
Terminal Transmitter

060

TUS8 Receiver

000-777

TUS8 Transmitter

Receiver vector plus 4

100
064

The line clock and terminal vectors are fixed. The TUS58 receiver and transmitter vectors are switch
selectable.
The terminal and TUSS8 interrupts are generated on bus request level 4 (BR4). The line time clock
generates an interrupt on bus request level 6 (BR6). Each of the two bus request lines (K3-7 BR4 REQ

L and K3-8 BR6 REQ L) are fed into UNIBUS control chips (DCO13).
The UNIBUS control chip asserts the bus request if the interrupt logic is not already the master. The
bus requests are sent to the processor arbitration logic (K4-2). The processor arbitrates the request and

returns a bus grant (K3-1 BUS BG6 IN H or K3-1 BUS BG4 IN H) if no device of higher priority is
making a request.
The UNBIUS control chip receives the grant and decides whether to accept it or pass it on. If a request

is made before the grant is received, the control chip accepts the grant and asserts K3-8 BG SACK L.
However, if a nonprocessor request (NPR) is also being made, the control chip does not execute an
interrupt sequence upon receiving the grant.

6-80

The processor responds to SACK by dropping the bus grant. Removal of the bus grant causes the
UNIBUS control chip to drop SACK and generate a MASTER signal. The MASTER signal is ANDed with K2-8 BUT SERVICE (1) H to place the vector on the PAX data bus. The processor clocks in
the vector, returns PAX SSYN L, and begins running the microcode routine corresponding to that vector. The MASTER signal is also routed back to the MASTER CLR input of the control chip. This
enables the control chip to drop MASTER when it receives PAX SSYN from the processor.

Note that the vector is transferred to the PAX data bus via the PAX data multiplexer (K3-9). The
vector bits (K3-8 VECTOR D8:D2 H) are generated by the vector multiplexer (K3-8) and used as one
source of the PAX data multiplexer. The MASTER signal of the control chip is ANDed with the BUT
SERVICE signal of the processor to produce K3-8 ENAB VECTOR L. This signal causes the PAX
data multiplexer to select the vector bits and enables the PAX data lines (K3-1 PAX D15:00 H).

6.11.5.1

Arbitration Between Terminal and TU58 Interrupts — As previously mentioned, the TUS58 and

terminal SLUs both interrupt on bus request level 4. Therefore, the interrupt request logic (Figure 655) must arbitrate between simultaneous interrupts. The order of priority for these interrupts is the
following.
Highest

TUS8 Receiver
TUS8 Transmitter
TERM Receiver

Lowest

TERM Transmitter

As an example of interrupt arbitration, consider simultaneous requests by the TU58 receiver (K3-7
REQ TUS58 REC INT H) and the terminal transmitter (K3-6 REQ TERM XMIT INT H). The two
requests are clocked into the interrupt request latch by the arbitration control logic. Since the TUS8
request has higher priority, the priority encode PROM will generate the following signals.
K3-7ANY RECINTL
K3-7TUS8 RECINT L
ANY INT L

The signal K3-7 ANY REC INT L is an input to bit 02 of the vector multiplexer and generates a zero
in that bit position. ANY INT L clocks the bus request flip-flop which generates K3-7 BR4 REQ L.
The signal K3-7 TU58 REC INT L clears the TU58 interrupt request (K3-7 REQ TU58 REC INT H)
and is also fed into the clear bus request and rearbitrate logic. Rearbitration occurs if the TUS8 receiver interrupt enable bit is cleared or a character is transmitted before the bus request is granted. The
bus request flip-flop is cleared and the interrupt request latch is clocked again. The signals generated
by the priority encode PROM depend on the current interrupt requests. Under normal conditions, the
rearbitration occurs when the MASTER signal is unasserted in response to PAX SSYN becoming asserted.

6.12

KK11-B CACHE

The KK 11-B Cache Memory is an integral part of the PDP-11/44 processor and is designed to increase
the CPU performance by decreasing the CPU-to-memory read-access time. It is an 8K-byte high-speed
RAM, memory organized as a direct-mapped cache with write-through. Figure 6-56 shows a block diagram of the KK11-B cache.

6-81

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The KK11-B cache operates as an associative memory in parallel with main memory and is connected

to the CPU via the PAX lines. When the CPU is performing a DATI from main memory, the cache
memory is first checked to see if it contains the requested data. If the data is in cache memory (a read
hit), the data transfer from main memory is discontinued and the data in cache is sent to the CPU via
the PAX data lines. If the data is not in cache memory (a read miss), the data transfer is completed,
with cache memory performing a write-through to update itself. When the CPU performs a DATO to
main memory, the cache updates itself if the addressed location is presently in cache. DMA (direct
memory access) and data transfers from the UNIBUS are monitored by the cache and result in the
invalidation of cached locations. Only CPU transfers to main memory are cached. Memory located on
the UNIBUS will not be cached.
6.12.1

Memory Organization

The KK11-B cache is an 8K-byte direct-mapping cache with write-through. A direct-mapping cache
allows each main memory address only one possible location in cache.
Each address is divided into two fields: the index field and the tag field (Figure 6-57). The index field
specifies the cache locations in which the tag and data are stored. The stored tag field is then compared

to the tag of the requested word to determine if there is a cache hit.

PAX ADDRESS
21

13 12

PAR
GEN

7777

NOTES:
1.BITS 12:1 OF THE CACHE ADDRESS

CHOOSE 1 of 4096 LOCATIONS.
2. BITS 21:13 ARE STORED IN THE

TAG FIELD PORTION OF CACHE
ON READ MISSES
3. ON ANY CACHE ACCESS, BITS 21:13
OF THE CACHE ADDRESS ARE
0

COMPARED WITH THE TAG FIELD OF
N

TAG FIELD

THE LOCATION ACCESSED BY BITS 12:1

PARITY

TO DETERMINE

IF THERE IS A MATCH

TK-4565

Figure 6-57

Cache Memory Addressing

6-84

The KK11-B Cache Memory consists of thirty 4096 X 1 static MOS RAM chips. The organization of

these chips is shown in Figure 6-58. The cache memory is divided into three basic segments.
TAG

Consists of nine tag field bits plus one parity bit.

VALID

Consists of two bits; one bit is active while the other bit is cleared. The two bits
allow a fast flush of cache by switching to the set of valid bits previously

DATA

Consists of two 8-bit bytes plus a parity bit for each byte.

30 BITS

B TS

l¢————9 BITS———»

4096
WORDS

le———9 BITS———ta———9 BITS ——»

|e— 9

1BIT—»

HI BYTE

—io

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TK-5347

Figure 6-58

6.12.2

Cache Memory Organization

Interface Logic

The KK11-B cache interface logic consists of the PAX address and EUB address buffers located on
K7-3 and the PAX data buffers and latches on K7-2, along with several control and t1m1ng signals. A
detailed explanation of the PAX address, EUB address and PAX data logicis containedin paragraphs
6.12.3, Address Logic, and 6.12.4, Data Control.

The following describes the cache interface signals.
PAX A21:00 H

These 22 lines are the physical address bits taken directly from the
physical address register (BA) in the CPU. The cache looks at these
address lines whenever the CPU starts a memory transfer.

EUB A21:00 L

These 22 lines are the memory address bus. The cache looks at

these lines by default if the processor is not currently transferring
data. The cache looks at these lines to watch for any DMA traffic
that might result in invalidations of a cached location.

PAX D15:00 H

EUB CO, Cl L

These 16 lines are the main CPU data bus. This bus connects the
CPU data path and control section, the multifunction module, the
UNIBUS interface and the cache. If the cacheis providing data to
the CPU, it comes over this bus. If the cacheis updating itself via a
READ MISS or WRITE HIT, the data is also on this bus.

These two lines are the memory bus control lines. They work in the
same manner as the UNIBUS control lines. The cache monitors
these lines to determine the type and direction of transfer taking
place.

6-85

EUB MSYN L
EUB SSYN L

These two lines are the memory master SYNC and memory slave

SYNC lines. They work in the same manner as the UNIBUS
MSYN and SSYN lines. These lines are isolated from the

UNIBUS lines to reduce loading.
The cache monitors these lines to determine when memory has been
accessed.

PAX SSYN L

This line is used by the various 1/O page registers within the CPU
(including cache) that communicate over the PAX data bus. This
line works like BUS SSYN and is used to inform the processor that
the data should only appear on the PAX data bus and not the
UNIBUS data lines.

BUS PB L

This is the only UNIBUS line that the cache is connected to. The
cache looks at this line to see if a memory read resulted in a parity
error. This line is driven by the cache to cause the CPU to abort and
trap on a cache parity error if the appropriate control bits have been

set in the cache control registers.
PROC INIT L

This line is used by the cache to initialize its internal registers and
also flush both valid bits. This signal is asserted on power-up or by
the initialize command from the console.

ENAB ADRS H

This line is issued by the CPU as soon as it has successfully arbitrated for the bus. This signal is the first indication to the cache that
the CPU is about to transfer data. On receiving this signal, the
cache immediately switches from its standby mode of watching for
I/O traffic on the memory address bus (EUB A21:00 L) to its fastaccess mode where it looks at the processor physical address bus
(PAX A21:00). This address bus will stablize the earliest in the
cycle and hence give the cache the earliest possible address setup
time.

UPPER 128 K L

This signal is generated by the CPU when the address on the PAX

address lines (PAX A21:00) is within the range of the upper 128K
of address space. Since this space is allocated to the UNIBUS ad-

dress and I/O page group, it is of special interest to the cache. It
tells the cache not to store any of the data that appears in this address range.
BUF CI (1) H

This signal, which is generated by the data transfer logic of the
CPU, gives the cache the earliest possible indication of the direction of the transfer about to take place, that is, DATO or DATI.

START TRAN L

This signal actually initiates the cache cycle. When the cache sees

this signal it knows that the PAX address lines (PAX A21:00) are
now stable. The leading edge of this signal is the point from which
the cache access time is measured.

6-86

CACHE GATE H

This signal is derived by the CPU from START TRAN delayed by
45 ns. CACHE GATE is used by the cache in conjunction with
START TRAN to control address switching and data enabling circuits.

STROBE CACHE H

This is a 15-ns wide pulse issued by the CPU 90 ns after the assertion of START TRAN. The cache uses this pulse to strobe its read
hit logic to determine if the cycle is a cache read hit.

CACHE RESTART L

This signal is issued by the cache if the STROBE CACHE signal
resulted in a read hit. The cache drives this line to restart the processor clock and inhibit the data transfer from main memory.

EXT CLK CL

This signal is a buffered version of PROC CLK, the main CPU
clock. The cache uses this signal in various places to clock data
from the CPU.

FAULT H

This signal is generated by the CPU when an odd address fault or
memory management fault is detected. The cache uses this line to
abort a cache read hit sequence on the occurrence of either of these
errors.

CACHE PE INTR H

This signal is issued by the cache to direct-set the parity error flipflop in the CPU if a cache parity error is detected. The CPU traps
the parity error after the instruction is executed.

CACHE BYPASS H

This signal is issued by the CPU if one of three conditions exists.
1.

If the memory management page address register currently in
use has the cache bypass bit 15 true.

If the operator specifies an examine operation with cache bypass.

On detection of the destination access of an ASRB instruction,
this feature is used in certain multiported memory applications.

These three actions result in the cache forcing a miss condition if
that location is currently cached and disallows the read update that
would normally follow a miss.

FREE BUS H

This signal is issued by the console logic to disable all devices from
driving data onto the PAX data bus. This action is used by certain
maintenance commands issued by the operator.

FORCE CACHE DATA L

This signal is used by the console in conjunction with FREE BUS to
allow the console to see the internal data bus in the cache during
special console maintenance operations.

6-87

ENAB MAINT (1) H

This signal is issued by the CPU during the final destination memo-

ry reference of an instruction to allow the cache and memory management diagnostics to test these devices without affecting the
fetching of the instructions in the diagnostic itself.
CPU HALT REQUEST L

The address match register in the cache can be set to allow the
cache to halt the CPU on recognition of a unique 22-bit address.
The cache asserts CPU HALT REQUEST L as soon as the selected address appears in the cache, if the appropriate maintenance
bits are set.

This line can also be driven by the parity detect logic on the cache
to halt the processor after an instruction that caused a cache parity
error.

MAN CLK ENAB L

This line is used in a manner similar to CPU HALT REQUEST.
The cache can be set up to stop the processor clock on recognition

of a 22 bit address. MAN CLK ENAB is a wire-ORed line that can

be driven by the cache or the console to stop the CPU clock. This
line can also be driven by the parity detect logic on the CACHE to
stop the clock on a cache parity error.

6.12.3 Address Logic
The KK11-B cache address control logic (K7-3) selects the bus, PAX address or EUB address, that

drives the internal cache address lines CA 21:00. Three basic conditions determine which set of address
lines are selected to drive the cache address lines.
1.

When the CPU is performing a data transfer, the PAX address lines are the point at which
the 22-bit physical address will stabilize earliest. Therefore, when a data transfer is in progress, the cache will want to monitor the PAX address lines to see if it contains the requested

data.
2.

When a DMA transfer is in progress, the UNIBUS address generated by the DMA device is

mapped to main memory via the UNIBUS map. Because of this, the PAX address lines will
not show any DMA activity. For the cache to monitor DMA traffic, it must look at the EUB
address lines.

When the CPU performs a data transfer to UNIBUS address space (upper 128K of main
memory address space), the address on the PAX address lines may not be the same as the
address on the EUB address lines. This condition is called “wraparound” and will be explained later.

Because the cache does not know when a UNIBUS device is accessing main memory (DMA), the cache
address multiplexer (K7-3), by default, looks at the EUB address lines. When the CPU is performing a
data transfer, the cache address multiplexer looks at the PAX address lines.
The control logic for the cache address multiplexer consists of E1, E2, E13, E23, and E59 located on
K7-3 (Figure 6-59). This logic is used to generate the signals PA TO CA L and PA TO CA H. When
PA TO CA L and PA TO CA H are not asserted (the default state), the EUB address lines are driven
onto cache address lines CA 21:00. When the CPU starts a data transfer, ENAB ADRS H is asserted
which asserts PA TO CA L and PA TO CA H. These two signals being asserted selects the PAX address lines and drives them onto the cache address lines CA 21:00.

6-88

+3 VA

UPPER 128K L —Q D

O—— WRAP AROUND (1) L
E1

CACHE GATE H

ENAB ADRS H

E13

PATO CA L

PATOCAH

START TRANH

CACHE GATE H
TK-5354

Figure 6-59

Cache Address Multiplexer Control Logic

One exception to the function of the cache address multiplexer is the special wraparound condition that
can exist when the CPU is performing a data transfer to UNIBUS address space (upper 128K) with the
UNIBUS map enabled. (For an explanation of how the UNIBUS map functions, refer to paragraph
6.9.) Due to the nature of the UNIBUS map, any address that appears on the UNIBUS is mapped into
main memory via the map relocation registers when relocation is enabled. This also includes references
to the UNIBUS address space made by the CPU when 22-bit relocation is enabled by memory management. Because of mapping of the PAX address by the UNIBUS map, the address on the EUB may not
be the same as the original PAX address. This action is called “wraparound” because the original PAX
address is wrapped around to main memory via the UNIBUS.
The circuitry that controls the wraparound action (K7-3) is shown in Figure 6-59. This circuit detects
references to UNIBUS address space (upper 128K) by the CPU. When the CPU starts a data transfer,
START TRAN H and ENAB ADRS H will switch the cache address multiplexer to the PAX address
lines and START TRAN H removes the direct-clear from flip-flop E1. A minimum of 45 ns after
ENAB ADRS H is asserted, CACHE GATE
H will be asserted. CACHE GATE H clocks flip-flop E1
to determine if the address is in the upper 128K of physical address space. (If the address is not in the
upper 128K of address space, signal PA TOP 128K L will not be asserted. Therefore, flip-flop E1 will
be held clear and the address multiplexer will continue to look at the PAX address lines.) When the
address is in the upper 128K of the physical address space, PA TOP 128K L will be asserted thus
signifying a reference to UNIBUS address space. When CACHE GATE H clocks flip-flop E1 and
UPPER 128K L is asserted, the flip-flop will be set and change the multiplexer so it is looking at the
EUB address lines.
The output of E1 is labeled WRAPAROUND and is used elsewhere in the cache to force a cache miss
condition to occur because the wraparound condition violates cache read hit timing. WRAPAROUND
is also used to enable/disable the data array (K7-5 and K7-6).
6.12.4
Data Control
The cache data control logic (K7-2) can be divided into two parts:
1.
2.

Write data latching
Read data enable

6-89

6.12.4.1
Write Data Latching — The write data circuit is used when writing data from the PAX data
bus into the cache array. When writing into the cache array, the data that is on the PAX data bus must
be latched up for approximately 70 ns after the leading edge of PROC CLK L. This action provides the
hold time required by the cache array when writing into it.
The write data circuit can be divided into two parts:
1.
2.

Transparent data latches E68 and E95
Latch control circuit E6, E31, and E33

The outputs of the transparent data latches, when the hold input is not asserted, will follow the data at
their inputs. When writing into the cache array, BUF CACHE GATE L will be asserted and remove
the preset from E6, which does not allow LATCH DATA L to be asserted. Approximately 45 ns after
BUF CACHE GATE L is asserted, EXT CLK C L will be asserted, clocking flip-flop E6 and asserting
LATCH DATA L which latches the data on the PAX data bus into latches E68 and E95. The latch will
stay set until cleared by the negation of BUF CACHE GATE L which happens no less than 75 ns after
the leading edge of EXT CLK C L. This circuit gives the necessary data hold times when the cache is
being written into. The clearing of the latch is also controlled by 1/O REG L. This signal is generated
on K7-11 and is the result of a reference to a cache register. This input to the data latch flip-flop guarantees that data on the input to the cache registers will be true up to 100 ns after the clock enable
inputs are negated.
6.12.4.2 Read Data Enable — The read data circuit consists of the data drivers and control logic used
when reading data from the cache. There is also a maintenance control allowing access to cache via the
console for maintenance purposes.
The drivers (E85, E87) are used to drive the requested cache data onto the PAX data bus for use by the
CPU. Because of the relatively slow enable time of the data drivers as compared to their data-in to
data-out time, the data enable circuit has been designed to enable the drivers as soon as possible during
a cache read cycle. Three different conditions result in the cache data drivers being enabled so that the
cache data is driven onto the PAX data bus.
1.

A read of one of the five cache registers — When the address decode logic on K7-11 recognizes one of the addresses of one of the five cache registers, it asserts /O REG READ H. If
FREE BUS H is not asserted, the data drivers will be enabled via E18, E5 and E16 and will
put the internal data onto the PAX data bus.

Cache READ HITs — To allow the data as much time as possible to propagate into the CPU
and its options, the read data enable circuit has been designed to assume that all read accesses to cache will result in read hits. The control logic works as follows.
START TRAN L is asserted by the CPU a minimum of 30 ns after the PAX address lines
have stabilized. The assertion of START TRAN L clocks flip-flop E3 to determine if the
data transfer is a DATO or a DATI. The data input to the flip-flop, BUF C1 H, provides the
direction of the data transfer. If BUF C1 H is not asscrted, a DATI cycle (when flip-flop E3
is clocked), ENAB DATA H, will be asserted, and, if FREE BUS H is not asserted, the data
drivers E85 and E87 will be enabled. At this point it has not been determined if the read
access is a hit or not. Approximately 85 ns after the assertion of START TRAN L, the inputs
to the hit-detect logic have stabilized. The STROBE CACHE pulse is generated 90 ns after
START TRAN L is asserted. If it is a read hit then CACHE RESTART is asserted and the
CPU clock is restarted which results in START TRAN L being negated. (For a detailed
cxplanation of a data transfer refer to paragraph 6.5.) START TRAN L is negated after the
cache data has been clocked into the CPU. START TRAN L is then ANDed with BUF
CACHE GATE H which clears flip-flop E3 and disables the data drivers.

6-90

If the read access to cache had resulted in a cache miss, the sequence will remain the same
up to the STROBE CACHE pulse. As soon as the cache determines the read access was a
miss, CLR ENAB DATA L is asserted and flip-flop E3 is cleared, disabling the data drivers.
3.

6.12.5
6.12.5.1

Cache maintenance from the console - FREE BUS H and MFM FORCE CACHE DATA L
are used by the console to override all drivers on the PAX data bus and to examine certain
data in the cache, thus allowing the console visibility into the cache.

Cache Array
Data Section — The cache data section of the cache memory array, K7-5 and K7-6, consists of

sixteen 4096 X 1 RAMs. The RAMs are addressed by CA 12:01 and the data inputs are the write data
lines, WRT D 15:00, found in the data control logic, K7-2. Each byte of the data array can be written
independently as determined by the write control logic (K7-1). The two write pulses, WRITE LO
BYTE L and WRITE HI BYTE L, are generated by this logic. The output of the RAMs are enabled
by the assertion of POWER ENABLE L, generated by AND gate E16 on K7-5. POWER ENABLE L

is used to take advantage of the stand-by power-down feature of the RAM chips, thereby reducing the
amount of power drawn by the data section of the cache array.
6.12.5.2

Tag Section — The tag section of the cache array, K7-4, consists of nine 4096 X 1 static

MOS RAMs. Unlike the data section, the output of the tag RAMs is permanently enabled because the
output of the tag field must be available during DMA transfers to determine if a DMA DATO cycle
will result in the invalidation of a cache location.
The data input to the tag field is controlled by a multiplexer (E97, E100, E103) which selects one of

two data inputs. This aids in diagnosing a problem in the tag field. During normal operation TDAR L is
not asscrted, thus gating CA 21:13 onto TAG WRT D 21:13. TDAR (tag data from address register) is
a bit in the cache maintenance that, when set, asserts TDAR L and causes the multiplexer to gate
AMR 08:00 onto TAG WRT D 21:13. Since the address match register (AMR) can be directly loaded

by the diagnostic and the tag field can be read through the cache bit register, the diagnostic can isolate
a failurc in the tag section of cache.
The KK11-B cache has independent parity generation and checking for the cache data (high byte, low

byte) and tag sections. The parity logic (K7-7) consists of three parity generators (E76, 81, 102) which
gencrate the even parity used by cache. Each of the three parity generators has an extra input, from the

cache control register, that allows the writing of wrong parity for diagnostic purposes. The outputs of
the parity RAMs (E111, E110, E109) are read back in parallel with the rest of the cache array and are
checked by three parity checkers (E79, E101, E58). The outputs of the parity checkers are ORed to-

gether to generate RAM PE H if a parity error exists. This signal and its components are clocked into

the cache error register, E47, every time there is a read access to a valid cache location. (For a description of the bits in the cache error register refer to paragraph 2.3.3.5.) When a parity error is detected
and RAM PE H is asserted, the clock input to the cache error register, E47, is inhibited by the assertion of CACHE PE L, thus saving the contents of the register for use by error recovery and logging
routines. The cache error register can be cleared by a write operation to the register, a processor initialization which occurs on power-up, or by a console INIT command.

6.12.6 Cache Flush Control
The cache flush control selects which valid control sct, A or B, will be used by cache while alternately
clearing the other set, or it may do a cache flush which clears both sets of valid bits simultaneously. The
cache flush logic (K7-8) can be activated by software by setting bit 8 in the cache control register, or by
the assertion of PROC INIT on power-up, or a console initialize command.
6-91

Three flip-flops, E39 A, E39 B and E38 A, control the operation of the cache flush logic. On power-up,
BUF PROC INIT L is asserted for 150 ns after AC LO is negated. This signal direct-sets both sections
of E39, clears the flush counter E26, E43, and E54, clears the flush done flip-flop E38 B, and inhibits
the delay line oscillator ES2 and E53. With the direct setting of E39 B, both the direct-set and clear
inputs of E38 A are asserted causing VALID A SEL L and VALID B SEL L to be unasserted and
allowing both the valid A and valid B bits to be cleared by the flush counter.
When BUF PROC INIT L is negated, the oscillator starts to run, thereby beginning the cache flush.
For 45 ns the oscillator generates FLUSH CLK H, which is the write enable to the valid RAMs, causing location O to be written. The flush counter is incremented 15 ns after FLUSH CLK H is negated
and, 120 ns later, FLUSH CLK H is asserted, writes the next location, and the cycle repeats. (Figure 660 shows the cache flush timing.) E38 B is clocked 4095 cycles later by the carry output of E26 which
sets the flip-flop, stopping the oscillator and clearing E39 A and B. With E39 B cleared, the direct-set
and clear inputs of E38 A are unasserted. Since the clear input to E38 A is connected through an RC
delay, the input is unasserted last, thereby clearing the flip-flop and selecting valid set A.

A cache flush sequence can also be invoked by setting bit 8 in the cache control register. This results in
clearing the counters and flush done flip-flop. When the DATO to the cache control register is completed, E39 A is clocked set. This is the valid clear in progress (VCIP) flip-flop which releases the hold
on the flush oscillator to start the flush sequence. Every time the cache flush bit is set, E38 A is complemented which causes the current valid set to be deselected and cleared while the previously cleared
valid set is nonselected for immediate use. If a second flush command is issued before the last has
finished (less than 800 us), then valid clear in progress will still be set and will cause a one to be clocked
into E39 B. This results in the direct-clear and set inputs being negated. The net result is if two flush
commands are issued less than 800 us apart, both valid sets are desclected and cleared, leaving the
cache inoperative until completion of the double flush.
6.12.7 Valid Control Logic
The valid control logic (K7-9) consists of two 4096 X 1 RAMs and their associated input multiplexers.
The input multiplexers are used to gate either CA 12:01 or CNT 12:01 to the address inputs of the valid
A or B RAMs, and also to select the source for the write pulse and data inputs.

If the valid A set is selected, VALID A SEL L asserted, then its multiplexer is switched to look at the
cache address lines CA 12:01, the write valid input from the write control logic, and the data input
from K7-9 VALID DATA H. Valid set B, at this time, is either in the process of being flushed or it is
clear and idle waiting for the next flush command to switch it into the in-use state. The data input to a
VALID RAM is 0 if it is being flushed, or it is VALID DATA H.

ONS

INPUT TO DELAY LINE
FLUSH CLOCK H

[

150

IWRITE VALID

180

225

I WRITE VALID

240

270

300 NS

INC COUNTER H

INCREMENT COUNTER

INCREMENT COUNTER
TK-5342

Figure 6-60

Cache Flush Timing Diagram

6-92

VALID DATA H is asserted when there is a CPU transfer to all but the upper 128K of address space,
WRAPAROUND L not asserted. VALID DATA H will not be asserted if a cache bypass is in effect,
BYPASS L asserted, or if the tag field is being tested by a diagnostic, TDAR L asserted. The output of
the valid A RAM is routed through both multiplexers such that if a double flush is in progress (both
sets of valid bits being cleared at once), VALID H will be held unasserted to keep the cache inoperative
until the double flush is completed.
'
6.12.8 Write Control Logic
The algorithm used in the write control logic (K7-1) of the KK11-B cache is standard for a directmapped single-block single-set cache. Table 6-7 shows the response of the cache to different types of
cycles and accesses (DMA or CPU).

As can be seen from Table 6-7 the cache will be written on four different occasions.

CPU DATI misses to main memory with cache bypass disabled (update).
CPU DATI hits to main memory with cache bypass enabled (invalidate).
CPU DATO hits to main memory (invalidate or update).
DMA DATO hits to main memory (invalidate).

The write control logic (K7-1) determines if a cache write is to be done and, if so, to which parts of the
cache array (valid bit, tag field, cache memory high byte, or cache memory low byte).

The write control logic uses two multiplexers, E8 and E10, to select between the different conditions
resulting in a cache write. E8 determines if it is a read (DATI) or a write (DATO, DATOB) cycle. E10
determines if it is a CPU or a DMA access. The remainder of the write control logic gives the result of
the cache access (hit/miss), selects which section of the cache array is to be written, and generates the
write enable pulse required by the cache array RAMs.

The inputs to multiplexer E8 are selected by C1 H to determine if the cycle is a read (DATI) or a write |
(DATO). If a read cycle is being done, then C1 H is not asserted and the DO inputs are selected. If a
write cycle is being done, C1 H is asserted and the D1 inputs are selected. The outputs of E8 are ENABLE WRITE H and byte selected for a DATOB cycle.

Table 6-7

Type of
Cycle

Hit

Read

DMA

Cache Read/Write Response

CPU

Miss

Hit

Nothing

Cached

Update

Read Bypass

Nothing

Nothing or

Nothing

Write Bypass

Invalidate

Nothing

Invalidate

Nothing

Write

Invalidate

Nothing

Update

Nothing

Invalidate*

Miss

*This action takes place when using multiported memory, Jumper W2 and W1 out, thereby eliminating the possibility of stale
data in cache.

6-93

Read Cycle - When a read miss of cache occurs, a cache update is done. A miss condition is detected by
AND gate, E7. The inputs to E7 and their functions are as follows.
BYPASS L — If this signal is not asserted then E7 is enabled to determine if the cycle is a read
miss.
UPPER 128K L — This signal not asserted means that the address is in main memory space.

UBUS PB L — This signal not asserted means that the backing store reference that could occur, as
a result of a cache miss, does not have a parity error.
BUF CACHE GATE H - This signal asserted means that the access to cache is from the CPU.
Cache Hit Flip-Flop — This flip-flop (E6) signals if there was a cache hit or miss on a read or write.
The input to E7 from E6 being high tells the cache that the memory access now occurring was a
result of a cache miss.
All of the above conditions result in ENABLE WRITE H being asserted. ENABLE WRITE H is sent
to the write cycle mutliplexer (E10) which will be described later. If BYPASS L had been asserted,
with jumper W1 installed, then ENABLE WRITE H would not be asserted resulting in no action by
the cache. With jumper W2 installed and BYPASS L asserted, E7 will be disabled and AND gate E9

enabled to look for CPU HIT (1) H, thus generating ENABLE WRITE H to cause a write cycle for the
bypass invalidate sequence.
'
Write Cycle - The write cycle logic consists of a multiplexer (E10), its input logic, and a pulse generator. The pulse generator is made up of a flip-flop (E42) and a delay line (E32); it is used to generate an
accurate write pulse for the RAMs in the cache array. The inputs to the pulse generator are the data

input to the flip-flop, which decides if a write cycle is to happen, and the clock input, which decides
when the write cycle is to happen. The write cycle multiplexer is switched by BUF CACHE GATE H

to determine if the write cycle is from the CPU or DMA traffic. The multiplexer selects the inputs to
the pulse generator.
When BUF CACHE GATE H is not asserted the multiplexer selects the output of AND gate E40 as
the data input to the pulse generator. The output of E40 will be asserted if C1 L and INTERNAL HIT
L are asserted. These conditions indicate a write hit from a DMA device and the currently cached data
is to be invalidated. EUB MSYN H and EUB SSYN H are ANDed together to provide the edge
needed to clock the write pulse circuit and invalidate the specified location in cache.

If the cycle is a CPU write, then BUF CACHE GATE H will be asserted and switch the multiplexer so
that ENABLE WRITE H is the data input to the pulse generator. EUB SSYN H ANDed with PROC
CLK H is the clock input to flip-flop E42. PROC CLK H is used so that the cache will be written at the
same time the CPU is writing its registers, thereby reducing the possibility of skew problems.
The pulse generator can be disabled by the hit on destination only bit being set in the cache mainte-

nance register. This bit set asserts DISAB CACHE WRITE H which disables the outputs of the write
cycle multiplexer, E10. When asserted, this signal remains asserted for all but the final destination access of any instruction. This feature allows diagnostics to test the cache without concern for how the
instruction stream affects the write algorithm. This feature should be used with care because it is pos-

sible to create stale data in some cases.
The output of the pulse generator is sent directly to the valid logic (K7-9) because it can be written
without affecting the rest of the cache array. The rest of the cache array is written only when BUF
CACHE GATE H is asserted, indicating a CPU access. The logic that controls which section of the
cache array is written consists of gates E13, E16, E22, E30, E46 and section A of multiplexer ES8.

6-94

When BUF CACHE GATE H is asserted, the gates that generate WRITE TAG L (E46), WRITE HI
BYTE L (E30), and WRITE LO BYTE L (E16) are enabled. If the cycle is a read update, all of the
cache array will be written. If the cycle is a write update, the output of multiplexer E8 section A will
determine if it is a DATO or DATOB. A DATO will write the high byte and low byte while a DATOB
will look at CA 00 H to see if the high or low byte is to be written.

6.12.9
Hit Detect Logic
The hit detect logic (K7-10) determines if all the conditions necessary for a CPU READ HIT have
been met. The hit detect logic consists of a 13-input NAND gate and its input logic. The signals and
their purpose are as follows.

COMPARE | H
COMPARE 2 H
COMPARE 3 H

VALID H

These three input signals are generated by comparators E61 and E57 along with
XOR gate E64. This logic compares the tag field selected by CA 12:01 with the
upper nine bits of the cache address, CA 21:13, to see if there is a match. When
there is a match, all the signals will be asserted.
This bit being asserted indicates that the word currently being read out of cache
is valid.

TAG PE L
HI BYTE PE L
LO BYTE PE L

These three signals are normally not asserted, indicating that the parity of the
word being accessed is correct. Any of these signals being asserted along with
VALID H indicates a cache parity error and will force a miss condition.

MAINT DISAB
CACHE L

This signal, when asserted, indicates that either a wraparound condition exists
or the cache maintenance bit, hit on destination only, is set and the current access is not a destination access. This signal being asserted will cause a cache
miss.

MISS HI L
MISS LO L

Cl H
BYPASS H

FAULT H

These two signals are generated from FMHI (1) H and FMLO (1) H (force
miss high and force miss low) which can be set from either the cache control
register or the two toggle switches mounted on the cache module. When asserted, these signals cause misses to high and low address space, respectively.
High cache address space is when cache address bit 12 (CA 12 H) is set and
low cache address space is when CA 12 H is not set.

These two signals are ORed (E19) together and must not be asserted to allow a
cache hit. Hits are only permitted for read operations (C1 H unasserted) without bypass (BYPASS H unasserted).
This signal must not be asserted to allows hits from cache. This signal is gener-

ated by the CPU to indicate an error in the virtual address (odd address error)
or an error in the physical address (memory management violation). In either
case the CPU has decided to abort the transfer, and this signal is used to cause

the cache to do the same.
6-95

When all the inputs to E28 are high, CACHE HIT L will be asserted to signify a cache read hit.
CACHE HIT L is clocked into the cache hit flip-flop (E42) by STROBE CACHE H and sets the flipflop. When the cache hit flip-flop is set, CACHE RESTART L is asserted and the CPU clock is restarted so the CPU can clock in the cache data. CACHE RESTART L also holds the CPU master sync
flip-flop clear, thus aborting the main memory reference that would occur if the cycle was a cache miss.
CACHE HIT L and STROBE CACHE H are ANDed (E9) to generate CLR ENAB DATA L. This
signal is used to disable the cache data drivers when a cache read miss occurs (CACHE HIT L unasserted).

The cache hit register (E73) is used to save the hit/miss sequence for the last six memory references.
~ This register is wired as a shifter and is clocked by STROBE CACHE H ANDed with MAINT DISAB CACHE L. As long as the address is within main memory and the hit on destination only bit of the
cache maintenance register is not set, every STROBE CACHE H pulse will shift in the current value of
INTERNAL HIT L. This signal reflects both read and write hits. The output of the first stage of the
hit register is used to drive a LED, mounted on the cache module, to provide a visual indication of
cache hits.

6.12.10

Cache Register Control

The cache register control logic (K7-11) consists of a decoder (E60) and AND gates E62 and E74
which are used to decode the upper part of the cache register addresses 17777740 to 17777756. The
outputs of E62, E74 and AND gate E2, which is asserted when EUB MSYN A and START TRAN H
are both asserted, are used to enable the decoder (E60). Cache address bits 1:3 (CA 03:01 H) are used
to select the particular register addressed. The outputs of the decoder are ORed together (E50, E13,
E19) and delayed by an RC network to generate PAX SSYN L. This signal is used by any processor
options that communicate over the PAX bus and is the same as BUS SSYN on the UNIBUS. Two
other signals are also generated by the outpt of E9: I/O REG READ H which is used to turn the cache
data drivers on and put the data on the PAX bus, and 1/O REG L which is used to control the write
data latch. (Refer to paragraph 6.12.4.) These signals determine whether it is a read or a write to the
selected cache register. Some of the outputs of the decoder are ANDed with LOAD HI BYTE L and
LOAD LO BYTE L to generate the required load signals for the writable registers.

For a description of each cache register and its bit functions refer to paragraph 2.3.3.
6.12.11

Address Match Logic

The KK11-B cache implements an address match and oscilloscope sync register which can be used by
diagnostics to check the address buses within the cache or it can be used by maintenance personnel to
provide a convenient oscilloscope sync point for troubleshooting both cache and CPU failures.

The 22-bit address match register (K7-12) consists of three octal registers that can be loaded by a
DATO cycle to cache registers 17777750 and 17777752. Once the registers are loaded, comparators
E104, E69, E67, E75, and E106, along with XOR gate E64, monitor the cache address lines CA 21:00
for a match with the address match register AMR 21:00. If a match is detected, all eight inputs of
AND gate E66 will be asserted, thus generating CA EQUALS AMR L which will direct-set the address match (AM) flip-flop E71. The output of the AM flip-flop is used to drive a LED mounted on the
cache module. The direct-set input to the AM flip-flop is also available on the backplane and on terminal points, T.P. 1 and T.P. 2, accessible on the top of the cache module. The AM flip-flop is read/write
through the cache maintenance register. Two bits in the cache maintenance register allow the cache to
either stop the CPU clock or halt the CPU on an address match condition or a cache parity error. This
feature is useful when troubleshooting intermittent cache or system problems. Two AND gates (E21)
are used to drive CPU HLT REQ L or MAN CLK ENAB L if the enable halt action or enable stop
action bits of the cache maintenance register have been set before an address match or a cache parity

error.

6-96

6.12.12

Cache Registers

The registers and drivers shown on K7-13 are all driven onto the cache internal data bus, INT D 15:00
H, by their various select signals that are generated by the address decode logic on K7-11. The drivers,
when enabled, drive the contents of the selected cache register onto the cache internal data bus which,
in turn, is driven onto the PAX data bus during read accesses to the cache registers.

Four octal registers, E86, E99, E98, E89, and a flip-flop E63, are used to save the contents of the addressed section of the cache array and associated internal status on every CPU READ to main memory.
These registers are clocked by CLK DATA L which is generated anytime there is a CPU read access to
main memory.

6-97

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