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EK-KK11A-UG-001

October 1978

28 pages

Original

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Document:	KK11-A Cache Memory Users Guide
Order Number:	EK-KK11A-UG
Revision:	001
Pages:	28
Original Filename:	EK-KK11A-UG-001_KK11-A_Cache_Memory_Users_Guide_Oct78.pdf

OCR Text

EK-KK11A-UG-001

KK11-A
cache memory
user's guide

digital equipment corporation. maynard, massachusetts

1st Edition, October 1978

The drawings and specifications herein are the property of Digital Equipment
Corporation and shall not be reproduced or copied or used in whole or in part
as the basis for the manufacture or sale of equipment described herein without
written permission.

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in
this manual.

Printed in U.S.A.

This document was set on DIGITAL's DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:
DIGITAL
DEC
PDP
DEC US
UNIBUS

DECsystem-1O
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX
VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
lAS

CONTENTS

Page
PREFACE
CHAPTER 1

INTRODUCTION

1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5

OVERVIEW ........................................................................................................ 1-1
PHYSICAL DESCRIPTION .............................................................................. 1-1
SYSTEM ARCHITECTURE .............................................................................. 1- 1
CACHE MEMORY ORGANIZATION ............................................................. 1-1
Addressing Cache ......................................................................................... 1-3
Multiprocessing ............................................................................................ 1-4
NPR Memory References ............................................................................. 1-5
Unibus Registers .......................................................................................... 1-5
Performance ................................................................................................. 1-5

CHAPTER 2

INSTALLATION

2.1
2.2
2.2.1
2.2.2
2.3
2.4
2.5
2.6
2.7

SCOPE ................................................................................................................ 2-1
UNPACKING AND INSPECTION ................................................................... 2-1
Unpacking ................................................................................................... 2-1
Inspection .................................................................................................... 2-2
PRE-INSTALLATION CHECK ......................................................................... 2-2
BAII-KA MOUNTING BOX INSTALLATION PROCEDURE ...................... 2-2
BAII-L MOUNTING BOX INSTALLATION PROCEDURE .......................... 2-6
OPERATION ...................................................................................................... 2-7
CHECKOUT PROCEDURES ............................................................................ 2-7

CHAPTER 3

SERVICE

3.1
3.2
3.3

MAINTENANCE PHILOSOPHy ...................................................................... 3-1
SYSTEM MAINTENANCE AND TESTING .................................................... 3-1
TROUBLESHOOTING GUIDELINES ............................................................. 3-1

FIGURES
Figure No.
1-1
1-2

Tide

Page

General System Architecture ................................................................................ 1-2
Cache Memory Format ........................................................................................ 1-2
iii

FIG URES (Cont)

Figure No.

1-3
2-1
2-2
3-1
3-2

Tide

Page

Direct Mapping Cache Memory System ... ............................................................ 1-3
Cache Installation Diagram .................................................................................. 2-3
Power/Configuration Schematic .......................................................................... 2-5
Troubleshooting Flowchart ....... ........................................................................... 3-3
Backplane Jumpers .............................................................................................. 3-8

TABLES
Table No.

1-1
2-1
3-1

Title

Page

Cache Responses to Hit/Miss Operations ............................................................ .1-4
+ 5 V Power Consumption For Some Common Options .. .....................................2-4
Maintenance Equipment Required ....................................................................... 3-1

PREFACE

This manual describes the KKII-A Cache Memory option to the KDII-EA central processing unit of
the PDP-II /34A system. The user must be familiar with the KD II-EA to completely understand the
contents of this manual.
The following documents are useful references:
KDll-EA Central Processor Maintenance Manual (EK-KDIEA-MM-OOI)
KDII-EA Print Set (MP00043)
KKII-A Print Set (MPOO574)
BA II-K Print Set
KYII-LB Programmer's Console/Interface Module Operation and Maintenance Manual
(EK-KYILB-MM-OOI)

CHAPTER 1
INTRODUCfION

1.1 OVERVIEW
The KKll-A is a cache memory option to the PDP-ll/34A's KDll-EA processor. The cache is a
small, high-speed memory that maintains a copy of previously selected portions of main memory; it is
designed to decrease central processing unit (CPU) to memory read access time.
1.2 PHYSICAl, DESCRIPTION
The KKII-A is implemented on a hex multilayer module (M8268) that contains a 1024-word, highspeed random access memory (RAM) organized as a direct mapped cache with write-through compatible with the current version of the PDP-ll /34A. The M8268 module interfaces to the KD ll-EA
processor (M8265 module) via a 40-pin over-the-top connector (H8821 or H8822). The only power
required is 5 Vdc at 4 A maximum (Figure 2-2).
1.3 SYSTEM ARCHITECTURE
Cache operates as an associative memory in parallel with the Unibus main memory but with its own
high-speed data path (AMUX lines that are also used by the FPII-A - a floating-point option). Cache
reads by the CPU result in data being transmitted over the AMUX lines. Read misses (desired data is
not present in cache) and write hits (bus address and cache location match) which result in cache
updates are accomplished by the cache capturing the data from the Unibus as the CPU /main memory
transaction occurs. Direct memory access (DMA) transfers to memory are also monitored by the
cache (Figure I-I).
1.4 CACHE MEMORY ORGANIZATION
Cache memory consists of twenty-eight 1024 X I RAM chips arranged as shown in Figure 1-2. Specific
implementation of the cache memory organization for the PDP-II /34A is as follows.
ClIChe Characteristics

PDP-ll/34A Implementation

Address mechanism

Direct mapping - allows each word from main memory only
one possible location in cache. Requires only one address comparison (Figure 1-3).

Block size

Block size of one - every time a fetch to the backing store
(main memory) occurs, only one word is allocated to cache in
the event of a miss.

Set size

Set size of one - there is one unique location in cache for any
given word from backing store. If a miss occurs, only one
cache location is available for data to be written into.

Write-through

Data from a write operation is written into cache and simultaneously copied into main memory. Maintains main memory
(backing store) with a valid copy of all data.

I-I

r---'
I

I
I
I

ID~~

CPU
CACHE
READS

UNIBUS
R MISSES/w HITS

ICACHE
UP-

I
I
I
I
I

CPU

DMA

~--;MONITOREDBY
CACHE

- -

L....--.
AMUX

MEM

CACHE

NPR
DEV ICES

I
I

1/0

V- r - - - - - _JI
FPll-A
(OPT.)

L...- _ _

L _ _ -.J

NOTE:
ALL MEMORY SHOULD BE LOCATED
BElWEEN THE CACHE AND ALL NPR DEVICES

MA-1896

Figure I-I

General System Architecture

(28. 1024Xl RAM CHIPS)

PARITY~

VALID BITS--

PARITY~

!--ADDRESS_

i - - - H I BYTE-.J

PARITY~

I----LO BYTE---!

18BITS
·_0

17161514131211 P BIA 15141312 11109 8 P 7 6 5 4 3 2 1 0 P

I
I
I

1024 WORDS

CACHE'INDEX
POSITIONS

: ... TAG FIELD_

I
I I+- - - -

-DATA FIELD- -

,..

J_,m,[

I
I

.1
1
... - - - - - - - - - - - - - - - 2 B BITS-~----~----I~_t

BLOCK SIZE OF 1
SET SIZE OF 1
VALID BITS = lWO SETS:
SET OF 1024 A BITS
SET OF 1024 B BITS
MA-1900

Figure 1-2

Cache Memory Format

1-2

MAIN
MEMORY

ADDRESS

/ l - - - - - - - i 2874§0

BLOCK

...i:=====::1 2574~

CACHE

A - - - - - I 2016~

6
5
4

3
l - - - - - - i 4510

"'-t:===~ 1322
7!6

Figure 1-3 Direct Mapping Cache Memory System

The 1024 cache index positions contain 28 bits each. The tag field contains seven address bits. Each
position contains a tag parity bit and two valid bits. One valid bit is currently active, allowing the other
bit to be cleared concurrently. The use of two sets of valid bits allows the cache to be flushed (cleared)
by switching to the second previously cleared bit set and then clearing the first set of valid bits. This
method allows the use of one set of valid bits while the other set is being cleared, useful in multiprocessing applications. The data field of the index position consists of two 8-bit bytes of data, each
with byte parity.

1.4.1 Addressing Cache
When addressing cache, the PDP-ll/34A uses an I8-bit address formatted as shown below.

!~.L.,...-

11l.10

i.17

L.~_ _ _ _ _-L..!_ _ _ _ _ _ _ _

BIT POSITION
CACHE FIELD NAME

""'"--C-HE-C-KE-'O'-A-G-AI-N-ST--"--A-D-D'-RE-SS-O-F"v"28--BI-TW-O-R-D-J

BYTE FIELD - SELECTS

TAG FIELD OF
INDEX WORD

IN CACHE

HI OR LO BYTE

The lower part of the address (10: 1) is applied against the I K cache matrix and the high-order bits
( 17: II) are checked against the tag field of the index word obtained (data field in cache). If the tag field
in the address matches the tag field stored with the data in cache, a hit is designated. If the fields do not
match, it is designated as a miss.

1-3

The processor always looks for data in the fast cache memory first.
• If a CPU hit occurs during a read non-bypass mode (Table 1-1) data is read from cache; in
bypass mode, cache is invalidated.
• If a CPU hit occurs during a write non-bypass mode, data is written into cache; in bypass
mode, cache is invalidated.
• If a CPU miss occurs during a read non-bypass mode, data and tag are written into cache; in
bypass mode, cache is not affected.
• If a CPU miss occurs during a CPU write non-bypass or bypass mode, cache is not affected.

Tallie I-I

Cache Responses to Hit/Miss Operations

Mode

DMA Miss·

DMA Hit·

CPU Hit

CPU Miss

Read
Bypass

Not
Affected

Cache
Read

Write Data
Write Tag
Write Valid

Read
Bypass

Not
Affected

Invalidate

Not
Affected

Write
Bypass

Not
Affected

Invalidate

Not
Affected

Write
Bypass

Not
Affected

Invalidate
(UCB)t
Invalidate
(UCB)t
Invalidate

Write Data
Write Valid

Not
Affected

*DMA hit/miss operations are discussed in Paragraph 1.4.3.
tUCD = Unconditional bypass

1.4.2 Multiprocessing
Additional functionality is required to perform multiprocessing.

• Unconditional Cache Bypass
In bypass mode, all memory references are forced to be misses and to invalidate (clear valid bit)
on cache hits.
• Conditional Cache Bypass·
A virtual page can be defined such that all memory references to that page by the CPU result in
being bypassed.
• LOCK (ASRB) Instruction·
Guaranteed ownership of the cache for the duration of the destination operand cycle; must
operate in bypass mode.

*Not implemented in the KDII-EA Processor.

1-4

1.4.3 NPR Memory References
• If a DMA hit occurs during a read non-bypass mode, the cache is not affected; in bypass mode,
cache is invalidated (unconditional cache bypass) Table 1-1.
• If a DMA hit occurs during a write non-bypass mode or bypass mode, cache is invalidated.
• If a DMA miss occurs during a read or write bypass and non-bypass modes, cache is not
affected.

1.4.4 Unibus Registers
The following hardware registers are implemented in the cache.
• Cache Memory Error Register (CME)
Address 777 744
Parity error detection of cache memory, high byte, low byte, and tag.
• Cache Control Register (CCR)
Address 777 746
The state of specific CCR bits control (1) valid, UCB, and flush cache, (2) the response of the
cache to parity errors, and (3) the occurrence of CPU forced misses.
• Cache Maintenance Register (CMR)
Address 777 750
Contains one read/write bit used for memory system maintenance.
• Cache Hit Register (CHR)
Address 777 752
Contains the seven bits of the tag store memory of the last valid access and indicates the
number of cache hits on the last six CPU accesses to non-I/O page memory.
1.4.5 Performance
The cache system is intended to simulate a system having a large amount of moderately fast memory.
Therefore, the system contains a small amount of very fast memory (cache) and a large amount of slow
memory (backing store). The cache system works because it can successfully predict which words a
program will require most of the time. Program behavior is such that cache hits should occur 85 to 90
percent of the time, substantially decreasing average access time.
Unibus Transactions - For a normal memory read (MMII-DP), BUS BUSY is asserted for 1.2 liS. A
cache hit read results in the CPU asserting BUS BUSY for approximately 450 ns. Thus, for every cache
hit, about 750 ns are saved.

1-5

CHAPTER 2
INSTALLATION

2.1 SCOPE
Information for installing the KKII-A Cache Memory option and checkout procedures to ensure
proper operation of the cache and the system are provided in this chapter.
The following tools are required:
• No.2 Phillips screwdriver
• M ultimeter with ohm capability
• Diagonal cutting pliers
• Soldering iron, 40 watt
• Solder sucker
• Spares kit (Control Distribution)
• Wire-wrap tools
2.2 UNPACKING AND INSPECfION
NOTE
Customer should not unpack the cache memory
option unless a DIGITAL representative is present;
to do so voids the warranty.
2.2.1 Unpacking
If the customer's receiving area procedures require it and/or to facilitate inventory, the shipment may
be moved to the computer area. Otherwise, unpacking and inventory must be done in the receiving
area.
Follow steps 1 through 4 to unpack the shipment.
I.

Ensure that the shipping container is sealed. If container is open, notify the customer and
record it on the installation report or LARS form.

Check the shipment against the packing list to ensure that the correct number of containers
has been received and that they are the correct ones. If the shipment is incorrect, notify the
customer and the branch service manager or supervisor. The customer should check with the
carrier to try and locate the missing item(s).

Check all containers for external damage. If any damage is found, notify the customer and
record it on the installation report or LARS form.

2-1

Open containers one at a time, starting with the one marked "OPEN ME FIRST." Inventory the contents of each package with its packing slip and record any missing items on the
installation report.
NOTE
Packing materials such as foam fillers and plastic
inserts should be retained if reshipment is contemplated.

2.2.2 Inspection
Inspect each component for damage, e.g., scratches, chips, or breaks. Report any damage to the
customer and record it on the instaUation report. Report any damaged components that require replacement immediately to the branch service manager.

2.3 PRE-INSTALLATION CHECK
The KKI1-A cannot be installed unless the CPU is a PDP-l1/34A. Inspect the serial number tag for
proper CPU verification. Ensure that the CPU is operating properly by running the following diagnostics.
DFKAA
DKKTH
CZQMC

PDP-II /34 basic instruction test
K T exerciser (PDP-II /34)
0-124K memory exerciser (16K)

The KK11-A cache memory option for the PDP-ll/34A consists of the following:
M8268
H8821
H8822

Cache module
2O-pin over-the-top (OTT) connector
2O-pin over-the-top (OTT) connector

2.4 BAlI-KA MOUNTING BOX INSTALLATION PROCEDURE
The BA11-KA mounting box is capable of delivering 64 A of +5 Vdc, which is supplied by two H7441
regulators. The +5 V is distributed to the backplane in the BAII-KA via five Mate-N-Lok connectors.
One H7441 +5 Vdc regulator supplies two Mate-N-Lok connectors; the other H7441 +5 Vdc regulator supplies the remaining three Mate-N-Loks. The PDP-ll/34A CPU backplane, DDll-PK,
attaches to the BA11-KA power distribution board via connectors J9 and J11, thus allowing the CPU
backplane the full capabilities of one H7441 regulator (i.e., 32 A of +5 Vdc). To prevent overloading
of the +5 Vdc, the current drain of the modules contained in the DDII-PK should not exceed 32 A
(Table 2-1).
If the total current drain used by the devices in the BA II-KA exceeds 61 A without cache, an expander
box will be needed (Figure 2-1).
NOTE
To prevent overloading of the +5 Vdc, the current
drain should be calculated. The current drain should
not exceed 32 A in the DDlI-PK backplane.

2-2

SEE NOTE 1

M8266

SEE NOTE 6

I
I

SEE NOTE '2

I
I
I

M8266

#3#2#1
SLOT CONFIGURATION "C"
SEE NOTES 3 & 4

#3 #2 #1
SLOT CONFIGURATION "D"
SEE NOTE 5
MA-2277

#5 #4 #3 #2 #1
SLOT
CONFIGURATION "A"
SEE NOTE 3

NOTES:
1. THE W9042 EXTENDER BOARD ASSY. IS
STORED IN THE BACKPLANE AND IS
USED FOR SOME MAINTENANCE OPERATIONS.

PARTS LIST

I
I
I

1
M8267

I
I

CACHE MEMORY (KKll-A)

D-UA-M8268-0-0 3

1 BOARD. INTERCONN 40 PIN

D-UA-H8821-0-0

1 TRICONN BOARD

D-UA-H8822-0-0

#5 #4 #3 #2 #1
SLOT
CONFIGURATION "B"
SEE NOTE 5

MODULES M8265 AND M8266 ARE PART
OF KDll-EA AND ARE SHOWN FOR REF.
ONLY.

CONFIGURATION C SHOWS SLOT 3 UTILIZATION FOR EITHER KKll-A OR FPll-A
WHEN ONLY ONE IS PRESENT.

ALL CONFIGURATIONS SHOWN ARE
USED IN THE BAl1-K (10.5in. BOX)
OR BA11-L (5-114 BOX)

CONFIGURATIONS B & D SHOW TYPICAL
MAINTENANCE SET UP.

M8267. 5412416 AND W9042 ARE PART
OF FPll-A AND ARE SHOWN FOR REF.
ONLY.

Figure 2-1

Cache Installation Diagram

2-3

Table 2-1 +5 V Power Consumption
For Some Common Options
Option Number

Description

+5 VA

Mounting Code

ARI1
DLlI-WA/B
DRI1-K
DUP-ll
KYII-LB

IO-bit A/D converter
Line interface and clock
Digital I/O
Synchronous line interface
Programmer's console/interface

4.0A
2.0A
2.SA
3.6A
3.0A

LAI80
MSII-FP
MSII-JP
MMII-CP
MMII-DP
M7850
M9301
M9302
RXII
TMBII
LPIIW,V
MMII-YP
FPII-A

DECprinter I
8K MOS memory
16K MOS memory
8K core memory
16K core memory
Parity control
Bootstrap
Unibus terminator
Floppy disk
TaPe control
Printer
32K core memory
PDP-I 1/34 floating-point
processor (FPP)
Asynchronous line interface
Synchronous line interface
CRC generator
RKOS controller
PDP-I1/34 A CPU
Bootstrap
RK06 controller

1.5 A
2.0A
2.0A
3.0A
3.0A
I.OA
2.0A
1.3 A
I.S A
6.0A
1.5 A
S.OA
7.0A

Hex
Quad
Quad
Hex
Quad (in PDP-II /34
CPU backplane)
Quad
Hex
Hex
Hex Quad
2 Hex
DH* module
DH*module
DH* module
Quad
SUt
Quad
2 Hex
Hex

1.8 A
2.0A
1.2 A
7.SA
II.SA
2.0A
IS.OA

Quad
Quad
Quad
Sut
2 Hex
DHmodule
2SUst

DLlIA-E
DUll
KGII
RKII-D
KDI1-EA
M9312
RK611
*DH = double height.
tSU = single unit.

Perform the following steps when installing KKII-A with the FPII-A present.
1. Turn system power OFF.

2. Extend the BAII-KA mounting box from the system.
3. Remove the top cover by loosening the screw at the side, then slide the cover off.
4. If the KYII-LB is present, remove the two maintenance connectors from the M8266.
5. Remove the 54-12416 orr connector from the M8266 and M8267 modules.
6. Remove the M8266 module from slot 1.
7. Visually verify that M8266 ECO No.4 is installed by checking that resistor R2 is 1 kn.
NOTE
Where R2 is less than I kn, install a I kn resistor
per instructions on M8266 ECO No.4.

8. Replace M8266 into slot 1 and replace the 54-12416 over-the-top connector.
9. Remove the H8821 connector from the M8265 and M8267 modules.

2-4

10. Remove any module in slot five and carefully reconfigure the modules in the DDll-PK
backplane (Figure 2-2).
11. Insert the M8268 module into DDll-PK slot 5.

NOTE
To prevent overloading of tbe +5 Vdc, make sure
tbat the current drain does not exceed 32 A. Calculate power consumptions using 4 A for KKll-A
(cacbe),7 A for FPll-A, and 11.5 A for KDll-EA.

~
1

CPU"

CPU~(ll.5a)

2
3

FPll-A (FPP). (7.08)
BOOT

4~)

KYll-LB

(3.0a)

KKll-A (CACHE). (4.0a)
5
HEX OR QUAD.

HEX OR QUAD.

7
8

HEX OR QUAD.

-.t UNIBUS
..,.- UNIBUS

IF THE FPll-A IS USED. AN ADDITIONAL
DOll-OK IS REQUIRED FOR ALL MEMORY DUE TO THE POWER RESTRICTiONS
IN THE FIRST 9-SLOT BACKPLANE.

BEFORE PLUGGING IN ANY ADDITIONAL
INTERFACES INTO THE EMPTY SLOTS IN
THE CPU BACKPLANE. PLEASE DO A
POWER CONSUMPTION CHECK IN ORDER
TO ENSURE THAT THE 32 AMP POWER
REGULATOR LIMIT FOR THAT CPU BACKPLANE HAS NOT BEEN EXCEEDED.

QUAD.

DL11-W (2.0a)

(1.0a)
PARITY

(1) 84K BYTE (5.0a) (2) 32K BYTE (4.0a)

QUAD·

MMll-YP OR MSll-JP

(1) 84K BYTE (5.0a) (2) 32K BYTE (4.0a)

MMll-YP OR MSll-JP
HEX OR QUAD.

7
B

NOTES:
1. IF THE FPll-A IS NOT USED. THE 7.08
MAY BE USED FOR 84KW of MSll-JP
PARITY MEMORY OR 32KW OF MMll-YP
PARITY CORE MEMORY IN SLOTS 8. 7.
AND B.

HEX OR QUAD.
M9302

-t (l.3a)

QUAD.
(1) SYSTEM UNIT.
MA-227st

Figure 2-2

Power/Configuration Schematic

12. Install the H8822 connector on the M8265, M8267, and M8268 modules (slots 2,3, and 5,
respectively). Make sure the arrow on this connector points toward slot 1.*
13. Check that both FORCE MISS switches SI and S2 are on. Have both switch handles point-

ing toward the console.
14. Loosen both screws on the bottom of the BAII-KA mounting box and remove the cover.

·When using other than the M9301-YF bootstrap terminator, the handle of the bootstrap terminator may interfere with the H8822 connector. Therefore, carefully remove that part of the handle which interferes.

2-5

15. Check for continuity between backplane connection COl EI and B02Al. This is the cache hit
line; if not present, a jumper (30 gauge wire, DIGITAL PIN 91-05740) should be installed.
Then recheck for continuity.
16. Replace the bottom and top covers, and slide the BAII-K into the system chassis.
17. Power-up the system.
18. Verify the CPU, cache, and FPll-A by running the diagnostics listed in Paragraph 2.7.
To install cache when the FPll-A is not present, perform the following steps.
I.

Repeat steps 1 through 8.

Remove any module in slot 3 and carefully reconfigure the modules in the DDI1-PK backplane (Figure 2-2).

Insert the M8268 cache module into slot 3 of the DDll-PK.

Install the H8821 connector on the M8265 and M8268 modules (slots 2 and 3, respectively).
Make sure that the arrow on this connector points toward slot 1.*

Check that both FORCE MISS switches S 1 and S2 are on. Have both BATT switches
pointing toward the console.

Complete steps 14-18 in the previous procedure.

2.S BAll-L MOUNTING BOX INSTALLATION PROCEDURE
The 13.3 cm (5 in) BAII-L mounting box can contain a power supply with either a 32 A or 25 A +5 V
regulator. Use the following chart in determining whether you have the proper 32 A supply.
C.,ent
25A

Regulator
H777-AA
-AB
-BA

-BB
32A

H777-CB
-CA

-DA
-DB

NOTE
To prevent overloading of the +S Vdc, make sure
that the +S Vdc current consumption does not exceed the capacity of the regulator.

·When using other than the M9301-YF bootstrap terminator, the handle ofthe bootstrap terminator may interfere with the H8822 connector. Therefore, carefully remove that part of the handle which interferes.

2-6

Perform the following steps when installing the KKII-A in a DAII-L mounting box.
I.

Slide the wire frame out of the wrap-around.

Turn CDI to off first, then turn the DC ON/DC OFF switch to DC OFF.

If the KYII-LD is present, remove the two maintenance connectors from the M8266 module.
Make sure that the DDII-PK is Rev C or later.

4.
5.

Remove the M8266 module from slot I and visually verify that ECO M8266 No.4 (R2 = I
kn) is installed.
NOTE
When R2 is less than 1 kn, change this resistor per
instructions on M8266 ECO No.4.

Replace M8266 into slot I.

Remove any module in slot 3 and carefully reconfigure the system.

Insert the M8268 cache module into DDII-PK slot 3 or 5.

Install the H8821 or H8822 connector on the M8265 and M8268 modules (slots 2 and 3 or
slots 2 and 5, respectively). Make sure arrow points toward slot I.

10.

Check that both FORCE MISS switches SI and S2 are on. Have both switch handles pointing toward the console.

II.

Reconnect the KYII-LD maintenance cable to the M8266 module.

12.

Turn CDI on and slide the wire frame inside the wrap-around carefully.

13.

Turn DC OFF to DC ON.

14.

Verify CPU, memory, and cache by running the diagnostics listed in Paragraph 2.7.

2.6 OPERATION
The cache module is program transparent. The only observable effect while in operation will be
reduced program run time.
2.7 CHECKOUT PROCEDURES
Run CPU and PDP-II/34A cache diagnostics for verification of the functionality of the options.
• PDP-II /34 Diagnostics
DFKAA
DFKAB
DFKAC
DKKTH
CZQMC

PDP-l 1/34
PDP-ll/34
PDP-l 1/34

Basic instruction test
Traps test
EIS instruction test
KTexerciser (PDP-l 1/34)
0-124K memory exerciser (16K)

2-7

• PD P-ll /34A FPP Diagnostics
DFFPB
DFFPB
DFFPC

PDP-Il/34
PDP-Il/34
PDP-Il/34

FPP Diagnostic Part I
FPP Diagnostic Part 2
FPP Diagnostic Part 3

• PD P-ll /34 Cache Diagnostics
CFKKAA

PD P-II /34

Cache diagnostics

The startup procedure is non-stanard form. A "RUN" command is required in addition to the
normal load and go at address 200.
Procedures are included with the diagnostic media.
• DEC/Xll monitor - the QABM monitor must be patched when the command "CON" for
cache on is given.
The patch for this problem is:

MOD

13136
13140

240
240

2-8

CHAPTER 3
SERVICE

3.1 MAINTENANCE PIDLOSOPHY
The field maintenance and repair philosophy reflects a module replacement approach. Once the cache
has been identified as the failing option in the PDP-ll/34A system, the module should be replaced.
The faulty cache is returned to the Maynard facility in Massachusetts or to European Depots for
repair (whichever location is feasible). Because of the complexity of the cache module and its etch
width, on-site component level repair is not encouraged. The standalone diagnostics should be run to
detect the cache module failure.
3.2 SYSTEM MAINTENANCE AND TESTING
For a PDP-ll/34A system that is unable to load diagnostics, use procedures in Chapter 6 ofthe PDPll/34A System User Manual to diagnose the problem. Table 3-1 lists the maintenance equipment
required to troubleshoot the cache.

Table 3-1 Maintenance Fquipment Required
Equipment

Manufacturer

Model/Type/Part No.

Oscilloscope

Tektronix

453·

Volt/Ohmmeter (VOM) Triplett

DEC Part No.

29-13510

Unwrapping Tool

Gardner-Denver
DEC Catalog (j11812A

505 244475

29-18387

Hand-Wrap Tool

Gardner-Denver
DEC Catalog (j11811A

A-20557-29

29-18301

Wire Strippers

Miller

lOIS

29-13467

Module Extender
Boards (2)

DEC

W9042

·Tektronix type 453 oscilloscope is adequate for most test procedures; Type 454 or equivalent may be required
for some measurements.

3.3 TROUBLESHOOTING GUIDELINES
The following guidelines are provided for debugging failures in the cache memory module installed in
a PDP-ll/34A system. Standard PDP-ll/34A diagnostics should be run first before attempting to
follow the procedures outlined in this section.

3-1

To verify the system integrity, run the following diagnostics in the sequence given below.
DFKAB
DFKAA
DFKAC
CZQMC

Traps Test (at lease Rev C)
PDP-I 1/34 CPU Test
EISTest
0-124K Memory Exerciser

If the FPII-A option is included with the system, run the following diagnostics.
DFFPB
DFFPB
DFFPC

PDP-I 1/34 FPP Diagnostic - Part I
PDP-I 1/34 FPP Diagnostic - Part 2
PD P-II /34 FPP Diagnostic - Part 3

The flowchart in Figure 3-1 is a helpful tool in troubleshooting the system.

3-2

6
REFER TO
CHAPTER 6
OF THE PDP-11/34A
USER'S MAN.

CACHE MEM
SHOULD NOT
BE INSTALLED
ON ANY SYS.
OTHER THAN
AN 11/34A

VERIFY VIA
SYSTEM
SERIAL NAME
TAG

CALCULATE THE
+5 VDC CURRENT
DRAIN IN THE
11/34ACPU
BACKPLANE

MUST
USE AN
EXPANDER
BOX
11

MUST USE
AN EXPANDER
BOX

MA-2284

Figure 3-1

Troubleshooting Flowchart
(Sheet I of 5)

SHEET 1

ON BA 11-KA BOX.
ADJUST +5 VDC
REGULATOR
IH7441) TO
+5.20 VOLTS

CACHE SLOT
F03A2
OR
F05A2

IF THE JUMPER IS IN THE CPU
BACKPLANE:
ADD .5 AMPS OF +5 VDC FOR
EACH MOS MEMORY BOARD
NOT IN THE CPU BACKPLANE
ICPU BOX ONLY) TO CURRENT
DRAIN TOTAL FOR CPU
BACKPLANE

THEN SYSTEM
SHOULD
HAVE CORE

THIS CONCLUDES
THAT BATIERY
BACKUP IS NOT
INSTALLED

BATIERY BACKUP
IS INSTALLED
& NO JUMPERS

THE CPU

JuW;; ~N~U-;A;;;;N-

}- -

~~1J~P~ +5 V JUMPER IN

ONLY SHOULD
HAVE JUMPERS
INSTALLED

+15 VB .... +15 V JUMPER IN
-15 VB .... -15 V JUMPER IN

SEE I
FIG I

•
......___..-__-1_ - - _ _ _ _ _ _ _ _ _
3·2 I
....J

r--A-LL-O-T..JIH~E-R--"'" BACKPLANES
IN THE CPU
BOX SHOULD BE

......---..----1-

JuMP;;

C;N~U-;A~N- -

DD11-DK.CK
+5 VB .... +5 V JUMPER OUT
+ 15 VB .... + 15 V JUMPER IN
-15 VB .... -15 V JUMPER IN

-- - - - - - - - - -

-,
I

I
I
I
......J

MA·2212

Figure 3·1

Troubleshooting Flowchart
(Sheet 2 of 5)

SHEET 2

CACHE MUST
BE IN SLOTS
3 OR 5 ONLY
IN 1134A SYS

OTT • OVER THE
TOP CONNECTOR
PROP - PROPERLY

~
\:.!I

INSTALL CONN.
AND ENSURE
THAT IT IS
SEATED PROPERLY.
ARROW
SLOT

SLOT

I
BACKPLANE
CONNECTIONS
COIEI TO
B02AI

INSTALL
ECO WIRE
IN
BACKPLANE

SI ANDS2
ON. BOTH
SWITCH HANDLES
FACE CONSOLE

CACHE HIT L
BCKPL. M82BB
802AI -+ BAI
ECOI/4
R2 = I KO

INSTALL
I KOIR2)

VISUALLY INSPECT
MODULE AND
BACKPLANE FOR
BROKEN WIRES.
CONNECTORS OR
OTHER DEFECTS

MAo-2ft"

Figure 3-1

Troubleshooting Flowchart
(Sheet 3 of 5)

SHEET 3

LOAD ADDRESS
LOCATION 200
AND DEPOSIT A
BRANCH SELF (777)

ALL MEMORY MUST BE BETWEEN THE
CACHE MODULE AND ALL NPR DEVICES.
REMOVE RESPECTIVE NPR DEVICE AND
REINSTALL IT ON THE OTHER SIDE OF
THE MEMORY (SEE FIGURE 1-1 OF
CHAPTER 1). IN CACHE. MSYN IS INHIBITED. THUS ABORTING THE MAIN
MEMORY TRANSFER. CACHE HITS BY
THE CPU RESULT IN THE DATA BEING
TRANSMITIED OVER THE AMUX LINES.
READ MISSES AND WRITE HITS WHICH
RESULT IN CACHE UPDATES ARE
ACCOMPLISHED BY THE CACHE
CAPTURING THE DATA FROM THE
UNIBUS AS THE CPU/MAIN MEMORY
TRANSACTIONS OCCUR DMA TRANSFERS
TO MEMORY ARE MONITORED BY
THE CACHE IN ORDER TO INVALIDATE
CACHED LOCATIONS. THIS REQUIRES
THAT MEMORY BE LOCATED ELECTRICALLY CLOSE TO THE CACHE.

PRESS CONTROL
START CAUSING
EXECUTION OF THE
INSTRUCTION

HALT THE CPU AND
EXAMINE THE CACHE
HIT REGISTER
ADDR; 777752

CACHE APPEARS TO
BE WORKINGRUN CACHE
DIAGNOSTICS
MA-2281

Figure 3-1

Troubleshooting flowchart
(Sheet 4 of 5)

3-6

SHEET 4

LOAD ADDRESS OF
THE CACHE CONTROL
REGISTER
ADDR=777746
EXAMINE CCR BITS

__ e__ ,~_J

LOAD ADDRESS OF
THE CACHE. MEMORY
ERROR REG
ADDR=777744

E~~~~

RESET
(lNIT)

-L---- ~19

----UV

CHECK FOR A
PARITY ERROR
IN BACKING
STORE (MAIN
MEMORY

MA-2260

Figure 3-1

Troubleshooting Flowchart
(Sheet 5 of 5)

3-7

+15V JUMPER

-==

+5V JUMPEfI

[]

o 0 GND
o 0

~-15

0
~+15
S+15
o 0 -158
<2:9)+58
<2:9) -5

NOTES

DC LO
AC LO

@::ID
@::ID

1. JUMPERS SHOWN ARE

~LTC

-15TO-158

<2:9)+20

+15 TO +158

~+5
o 0

+5 TO +58
2_ USE #20 INSULATED
8US WIRE FOR JUMPERS

VIEWA
11-5343

Figure 3-2

Backplane Jumpers

3-8

KKll-A CACHE MEMORY USER'S GUIDE
EK-KKllA-UG-OOl

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