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EK-SBC02-UG-001

March 1984

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Document:	SBC-11/21 Plus Single-Board Computer User's Guide
Order Number:	EK-SBC02-UG
Revision:	001
Pages:	470
Original Filename:	EK-SBC02-UG-001_SBC-11_21_Plus_Single-Board_Computer_Users_Guide_Mar1984.pdf

OCR Text

EK-SBC02-UG-OOi

SBC-11j21 PLUS
Single-Board Computer
. User's Guide

Prepared by Educational Services
of
.
Digital Equipment Corporation

First Edition. Mari:h t 984

The material in this manual is for informational purposes and is subject to
change without notice.
The drawings and specifications herein are the property of Digital Equipment
Corporation and shall not be reproduced or copied or used in whole or in part
as the basis for the manufacture or sale of equipment described herein without
written permission.
Digital Equipment Corporation assumes no responsibility for any errors wmch
may appear in this manual.
The manuscript for this book was created using a DIGITAL Word Processing
System and. via a translation program. was automatically typeset on DIGITAL's DECset Integrated Publishing System. Book production was done by
Educational Services Development and Publishing in Marlboro. MA.

The following are trademarks of Digital Equipment Corporation:

IIIIII F
DEC
OECmate
DECnet
DECUS
DECsystem-IO
OECSVSTEM-20
DECwrher

MASSBUS
MicioPowerIPascal
MINC-II
OMNIBUS

OS/8
PDP
PDT

P/OS

DlBOL

Professional

EduSystem
lAS

Q-Bus
Rainbow

RSTS
RSX
RT-tl
TOPS-tO
TOPS-20
UNIBUS
VAX
VMS
VT
Work Processor

CONTENTS
Page
PREFACE
CHAPTER 1

INTRODUCfION

1.1

INTRODUCTION ..................................................................................................... 1-1
SPECIFICATIONS .................................................................................................... 1-3

1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.3
1.4

Physical. .............................................................................................................. 1-3
Power Requirements .......................................................................................... 1-3
Bus Loading ........................................................................................................ 1-3
Environmental ...................................... ,............................................................ , 1-4
BACKPLANE PIN IDENTIFiCATION ................................................................. 1-4
RELATED f)()(:UMENTS ....................................................................................... 1~ 7

CHAPTER 2

INSTALLATION

2.1
,2.2
2.2.1
2.2.2
2;2.4
2.2.5
2.2.6

INTRODUCTION, ....................................................................,................................. 2-1
SELECTING OPERATIONAL FEATURES ......................................................... 2·1
Battery Backup.......................... "........................................................................ 2-1
Wake-Up Circuit .......... "..................................................................................... 2-8
Starting Address ................................................................................................. 2~8
Interrupts ............................................................
2-8
Parallel I/O ...................................................................................................... 2-11
Serial I/O ......................................................................................................... 2~ 12

2.2.7
2.2.7.1

Memories .............. ,..........................................................................-................. 2-16
Memory Maps .......................................................................................... 2-16

2.2.7.2
2.2.7.3

PROMs/EPROMs/EEPROMs ............................................................... 2-16
RAMs....................................................................................................... 2-16
SELECTING BACKPLANES AND OPTIONS ................................................... 2-22
POWER SUPPLY ............................... ".............,.......................... ~ ........................... 2-22
EXTERNAL CABLES............................................................................................ 2-22
Parallel I/O Interface (J3) ............................................................................... 2-23
Serial Line Interfaces (Jl and J2) ................................................................... 2-25
VERIFYING OPERATION ...................................................... " ........................... 2-28
Macro-OD1' Option .......................................................................................... 2-28

2.2.3

2.3

2.4
2.5
2.5.1

2.5.2
2.6
2.6.1
2.6.2
2.6.3

ro . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . .

Loopback Connectors ....................................................................................... 2-28
Verification Procedure ..................................................................................... 2-28

CHAPTER 3

OPTIONS

3.1

INTRODUCTION ..................................................................................................... 3-1
SUPPORTED OPTIONS .......................................................................................... 3-1

3.2
3.2.1
3.2.2
3.2.2.1

3.2.2.2

Hardware Options .............................................................................................. 3-1
Software Options ....................................................................... " ....................... 3-5
RT-I J Operating System ........................................................................... 3·5
MicroPower/Pascal Operating System .................................................... 3-6
iii

CONTENTS (Coot)
Page
CHAPTER 4

MACROwODT

4.1

4.4.5
4.4.6
4.4.7
4.4.8
4.4.9
4.5
4.6
4.6. )
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.6.7
4.6.8
4.6.9

INTRODUCTION ..................................................................................................... 4~1
INSTALLATION AND CONFIGURATION ........................................................ 4-1
ENTRY CONDITIONS ........................................................................................ ~ ....4-1
Macro-ODT Input Sequence .............................................................................. 4-1
Macro-ODT Output Sequ~nce ........................................................................... 4-2
MACRO-ODT COMMANDS ................................................................................... 4·2
/(ASCII 057) Slash ............................................................................................ 4-2
<CR> (ASCII i 5) Carriage Return .................................................................. 4·5
<LF> (ASCII 12) Line Feed ............................................................................. 4-5
R (ASCII 122) Internal Register Designator .................................................... 4-5
S (ASCII 123) Processor Status Word (PSW) ................................................ 4-6
G (ASCII 107) Go ............................................................................................. 4-6
P (ASCII 120) Proceed ................................... ,.................~ ................................ 4·6
DO, DX, DY Bootstraps ..................................................................................... 4·6
X (ASCII 130) Diagnostics ................................................................................ 4-8
INITIALIZATION .................................................................................................... 4-8
WARNINGS AND PROGRAMMING HINTS ..................................................... 4·8
Error Decoding ................................................................................................... 4~8
ODT Stack Warning .......................................................................................... 4-8
Addresses to Avoid ............................................................................................ 4-8
CPU Priority ...................................................................................................... 4·9
Terminal Related Problems ............................................................................. ;. 4-9
Spurious Halts .................................................................................................... 4-9
Serial I/O Protocol. ............................................................................................ 4-9
Interrupt Vector Initialization ............................................................................ 4-9
Boot ROM Address Scheme .............................................................................. 4-9

CHAPTER 5

SYSTEM ARCHITECTURE

5.1

5.2.2
S.2.3
5.3
5.4
5.5

INTRODUCTION ..................................................................................................... 5-1
MICROPROCESSOR ARCHITECTURE ............................................................... 5·1
Registers ...................................................................... ,...................................... 5-1
General Registers ................................................................................ ,...... 5-1
Status Register ............................................................................................ 5-1
Hardware Stack .................................................................................................. 5-2
Interrupts ............................................................................................................ 5-2
DMA (DIRECT MEMORY ACCESS) .................................................................... 5-4
MEMORY ORGANIZATION ................................................................................. 5·4
POWER-UP/POWER-OOWN FACILITy ............................................................. 5-4

CHAPTER 6

PROGRAMMING INFORMATION

6.1

INTRODUCTION ..................................................................................................... 6-1
ASYNCHRONOUS SERIAL LINE UNITS .......................................................... 6-1
Data Baud Rates ................................................................................................ 6-1
Interrupts ............................................................................................................. 6-7

4.2
4.3
4.3.1
4.3.2
4.4
4.4.1
4.4.2
4.4.3

4.4.4

!
i

5.2

5.2.1.1

!
I

l
i

I
~

i
t
,I

5~2.1

5.2.1.2

6.2
6.2.1

6.2.2

!
i'

CONTENTS (Coat)
Pap

6.3
6.3.1
6.3.1.1
6:3.1.2

6.3.4

PROGRAMMING THE PARALLEL I/O INTERFACE ..................................... 6-7
Modes of Operation............................................ ~ ............................................... 6-7
Port C Resister ............................
6-10
Mode 0 Basic Input/Output .................................................................... 6-10
Port A and B Registers ...............................~........................................... 6-11
Port C Register in Mode 0 ...................................................................... 6-11
Mode I (Strobed Input/Output) ............................................................. 6-11
Mode 2 (Strobed Bidirectional I/O) ........................................................ 6-18
Control Word Register ..................................................................................... 6-22
Mode Selection......................................................................................... 6-22
Se,tting Bits in Port C ................•.....................•...........•.•.................. ,...... 6-22
Parallel I/O Initialimtion .................................................................................. 6-25
Parallel I/O Handshaking ................................................................................ 6-25

CHAPTER 7

ADDR~ING MODES AND INSTRUcnON SET

7. I
7.2
7.2.1

INTRODUCTION ..................................................................................................... 7-1 .
ADDRESSING MODES ......................................................... ;................................. 7·1
Single Operand Addressing ................................................................................ 7-3
Double Operand Addressing .............................................................................. 7·3
Direct Addressing ..........................................................! .................................... 7-4
Register MClde (Mooe 0) .......................•......••..•.......•................................ 7-6
Autoincrement Mode (Mode 2)................................................................. 1-8
Autodecrement Mode (Mode 4) .............................................................. 7-10
Index Mode (Mocle 6) .................................•............................................ 7-12
I>eferred (Indirect) Addressing ........................................................................ 7-14
Use of the PC as a General-Purpose Register................................................. 7·17
Immediate Mooe .................................................... "................................. 7-18
Absolute Addressing ................................................................................ 7-19
Relative Addressing ........................................ ;........................................ 7·20
Relative I>eferred Addressing ...................................•.............................. 7-21
Use of the Stack Pointer as a General-Purpose Register ................................ 7-22
INSTRUCTION SET .............................................................................................. 7·22
Instruction Formats .......................................................................................... 7·23
List of Instructions ........ ".............. "......... "...... ".•................................................ 7..26
Single Operand Instructions ............................................................................. 7·28
General ..................................................................................... :............... 7-29
Shifts and Rotates .........•................................•..........•...........•.................. 7-32
Multiple Precision .................................................................................... 7-37
PS Word Operators .: ..........................•.......•..•........ ~ ...........•...........•••...... 7-.40
Double Operand Instructions ..................................................•........................ 7-41,
General ................................................................................:.................... 7-41
I..ogical ...............................................................•...................................•.. 7-44
Program Control Instructions........................................................................... 7-46
Branches ................................................................................................... 7-46
Sianed Conditional Branches ...............................•..........•..........•............. 7-5 I
Unsianed Conditional Branches ............................................................... 7-53
Jump and Subroutine Instructions ........................................................... 7·55

6.3.1.3
6.3.1.4

6.3.1.5
6.3.1.6

6.3.2
6.3.2.1

6.3.2.2
6.3.3

7.2.2
7.2.3
7.2.3.1

7.2.3.2
7.2.3.3
7.2.3.4

7.2.4
7.2.5
7.2.5.1
7.2.5.2

7.2.5.3
7.2.5.4
7.2.6
7.3

7.3.1
7.3.2
7.3.3
7.3.3.1
1.3.3.2
1.3.3.3
1.3.3.4
7.3.4
7.3.4.1
7.3.4.2

7.3.5
7.3.5.1

7.3.5.2
7.3.5.3
7.3.5.4

a ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••

•
v

CONTENTS (CoiIt)
Page
7.~.S.S

7.3.5.6
7.3.5.7
7.3.5.8
7.3.5.9

7.3.5.10
7.3.5.• 11
7.3.6
7.3.7

Traps ......:.................................................................................................. 7-60
Reserved Instruction Traps ...................................................................... 7-64
HALT Interrupt ....................................................... :............................... 7-64
Trace Trap ............................................................................................... 7-64·
Power Failure Interrupt ........................................................................... 7-64
Interrupts .................................................................................................. 7-64
Special Cases (T-bit) ................................................................................ 7-65
Miscellaneous Instructions~............................................................................... 7-65
Condition Code Operators ................................................................................ 7-67

CHAPTER 8

THEORY OF OPERATION

8.1

INTRODUCTION ..................................................................................................... 8-1
MICROPROCESS<>R ................................................................................................ 8-1
Microprocessor Initialization .............................................................................. 8-1
RESET Instruction .................................................................................... 8-4
Power-up Input (PUP) ......................................... :...................................... 8-4'
Clock Input (-TCLK) ........................................................................................ 8-5
Ready Input (READy) ...................................................................................... 8-5
Microprocessor Control Signals.......................................................................... 8-5
Row A4dress Strobe (RAS) ....................................................................... 8-5
Column Address Strobe (CAS) ................... ;............................................. 8-5
Priority In (PI) ........................................................................................... 8-5
Read/Write (R/-WHB and R/-WLB) ................................................... 8-5
Select Output Flags (SELO and SEll) ..................................................... 8-5
Bus Clear (BCLR) ..................................................................................... 8-6
Clock Out (COUT) .................................·................................................... 8-6
Microprocessor Transactions ............ :................................................................. 8-6
Fetch/Read ................................................................................................ 8-6
Write .......................................................................................................... 8-8
IAK ............................................................................................................ 8-8
DMA ........................................................................................................... 8-8
ASPI ........................................................................................................... 8-8
NOP ............................................................................................................ 8-8
. MODE REGISTER CONTROL ............................................................................ 8-13
INTERRUPT CONTROL ...................................................................................... 8-14
Interrupt Control Logic .................................................................................... 8-16
Ready Logic ..................................................................................................... 8.. 17
IAK Data In (IAKDIN) .................................................................................. 8-18
HALT Interrupt ............................................................................................... 8- J9
Power Fail (-PFAIL) ....................................................................................... 8-19
1.oca1 .................................................................................................................. 8-20
External ... ;......... ~ ....................................................... ~ ....................... :.............. 8-20
DMA Interrupt ................................................................ ;................................ 8-20
OCOO4 PROTOCOL ................................................................................................ 8·20
ADDRESS LATCH ................................................................................................. 8-21
MEMORY ADDRESS DECODE .................... ~ ..................................................... 8-21
RAM MEMORy ..................................................................................................... 8-21
ROM/RAM MEMORY SOCKETS..................................................... :................. 8-21

. 8.2
8.2.1
8.2.1.1
8.2.1.2
8.2.2
8.2.3
8.2.4
8.2.4.1
8.2.4.2
8.2.4.3
8.2.4.4

8.2.4.5
8.2.4.6
8.2.4.7

8.2.5
8.2.5.1
8.2.S.2
8.2.5.3
8.2.5.4

8.2.5.5
8.2.5.6
8.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4

8.4.5
8.4.6
8.4.7
8.4.8

8.S

8.6 .
8~1

8.8
8.9

CONTENTS (Cont) .
Page

8.19

SERIAL LINE INTERFACE UNITS .................................................................... 8~23
PARALLEL 1/0 INTERFACE .................. " ......................................................... 8-25
POWER-UP ............................................................................................................. 8-27
CLOCK .............................................................................................. ;...................... 8-28
CLOCK CONTROL ................................................................................................ 8-29
DMA ......................................................................................................................... 8-29
TSYNC ..................................................................................................................... 8-31
READ/WRITE ........................................................................................................ 8-31
REPLY TIME-OUT ................................................................................................ 8-33
BUS CONTROL ...................................................................................... " .............. 8-33

CHAPTER 9

LSI-II BUS

9.1
9.2
9.3
9.4
9.4.1
9.4.2
9.5
9.5.1·
9.5.2
9.6
9.6.1

9.6.3
9.6.4
9.7
9.8

INTRODUCTION ..................................................................................................... 9-1
SBC·tl/21 PLUS SINGLE·BOARD COMPUTER ................................................ 9·2
MASTER/SLA VE RELA TIONSHIP ...................................................................... 9-2
DATA TRANSFER BUS CYCLES ........................................................................ 9-3
Bus Cycle Protocol .............................................................................................. 9-4
Direct Memory Access ....................................................................................... 9~8
INTERRUPTS ......................................................................................................... 9-12
Device Priority ................................................................................................. 9-12
Interrupt Protocol ............................................................................................. 9-12
CONTROL FUNCTIONS ...................................................................................... 9~14
Hait ................................................................................................................... 9-14
Initiali7..ation ...................................................................................................... 9-14
Power Status ..................................................................................................... 9-14
Power-Up/Power-Down Protocol ..................................................................... 9-15
LSI-It BUS ELECTRICAL CHARACTERISTICS ............................................. 9-16
MODULE CONTACT FINGER IDENTIFICATION ......................................... 9-16

APPENDIX A

INSTRUCTION TIMING

APPENDIX B

PROGRAMMING DIFFERENCE LIST

APPENDIX C

sonw ARE DEVELOPMENT

APPENDIX D

MACRO-ODT ROM LISTING FOR KXTII-A2 OPTION

APPENDIX E

MACRO-ODT ROM LISTING FOR KXTI1-AS OPTION

APPENDIX F

SBC-II/21 PLUS SCHEMATICS

APPENDIX G

GLOSSARY

8.10

8.1}
8.12
8.13
8.14
8.15
8.16
8.17

8. I 8

9.6.2

INDEX

vii

FIGURES
Figure No.
1·1

2-1
2-2
2:.3
2-4

2-5

2-6
2-7
2-8
2-9
2-10
2-11
5-1
5-2
6-1

6-2
6-3
6-4
6-5

6-6
6-7
6-8
6-9

6-\0
6-11

6-12
6-13
6-14
7-1
7-2

7-3
7-4
7-5
7-6
7-7
7-8

7·9
7-10
7-11
7-12
7-13
7-14

7- t 5
7-16
7·t7
7-18
7-19
7-20

Tide

Page

KXTll-AB (M7676) SBC-l1/21 PLUS Module ..................................................... 1-1
SOC-IIIll PLUS Module Layout ................................................ ;........................... 2-2
Interrupt Configurations ...................................................................................... ;.... 2-10
Time-out During LSI· I I Bus Interrupt Acknowledge ............................................. 2-11
Parallel i/O Configuration ....................................................................................... 2-12
Socket Sets A and B Interconnection .... :................................................................. 2-17
Memory Configuration ............... :............................................................................. 2-18
Memory Maps .......................................................................................................... 2-19
30-Pin Parallel I/O Connector ................................................................................. 2-24
IO-Pin Serial Line Unit Connector .......................................................................... 2-26
BC20N-05 Null Modem Cable ................................................................................ 2-27
OC2l B-05 Modem Cable ......................................................................................... 2-27
Registers and Processor Status Word ........................................................................ 5-2
Memory Maps ............................................................................................................ 5·6
Serial Line Unit (SLU) I.nterface ............................................................................... 6-2
Serial Line Unit Register Bit Maps ........................................................................... 6-4
Parallel 1/0 Interface ................................................................................................. 6-8
Parallel I/O Flowchart ............................................................................................... 6-9
Mode 0 Port A or B Bit Assignments ..................................................................... 6-11
Mode 0 Port C Bit Assignments .............................................................................. 6-12
Mode I Port C Bit Assignments .............................................................................. 6-15
Mode 2 Port C Bit Assignments .............................................................................. 6- 20
Mode I Input Data Handshaking Sequence ............................................................ 6·26
Mode I Strobed Input Timing ................................................................................. 6-26
Mode I Output Data Handshaking Sequence .......................................................... 6-27
Mode I Port A Strobed Output Timing ....................... : .......................................... 6-28
Mode 1 Port B Strobed Output Timing .................................................................. 6·28
Mode 2 Port A Bidirectional Timing ....................................................................... 6-29
Single Operand Addressing ........................................................................................ 7-3
Double Operand Addressing ....................................................................................... 7-3
Mode 0 Register ......................................................................................................... 7-5
Mode 2 Autoincrement .............................................................................................. 7-5
Mode 4 Autodecrement. ............................................................................................. 7-5
Mode 6 Index .............................................................................................................. 7-5
INC R3 ....................................................................................................................... 7-6
ADD R2,R4 ................................................................................................................ 7-7
COMB R4 .................................................................................................................. 7-7
CLR (R5)+ ................................................................................................................. 7-8
CLRB (R5)+ ............................................................................................................... 7-9
ADD (R2)+,R4 .......................................................................................................... 7-9
INC -(RO) ................................................................................................................ 7·10
INCB -(RO) .............................................................................................................. 7-tl
ADD -(R3),RO ........................................................................................................ 7-1t
CLR 200(R4) ........................................................................................................... 7-12
COMB 200(Rl) ........................................................................................................ 7-13
ADD 30(R2),20(R5) ................................................................................................. 7-13
Mode I Register Dcferred ........................................................................................ 7-14
Mode 3 Autoincrement Dcferred ............................................................................. 7-14

viii

FIGURES (Cont)
Figure No.
7-2 t
7-22
7-23
7-24
7-25
7-26
7-27
7-28
7-29'
7-30
7-31
7-32
7-33
8·1
8-2
8-3
8~4

8-5
8-6'
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-\8
8-19
8-20
8-21
8-22
8-23
8-24
8-25
8-26
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9

Title

Page

Mode 5 Autodecrement Deferred ............................................................................ 7-15
Mode 7 Index Deferred ............................................................................................ 7-15
CLR @R5 ................................................................................................................. 7-15
INC @(R2)+ ............................................................................................................. 7-16
COM @ -(RO) ......................................................................................................... 7-16
ADD @IOOO(R2),Rl ................................................................................................ 7-17
ADD #IO,RO ....................................................................................................... ,.... 7·19
CLR @#lIOO ............................................................................................................ 7-19
ADD @#2000,R3 ........................................ .'............................................................ 7-20
INC A ....................................................................................................................... 7-21
CLR@A ................................................................................................................... 7-22
Byte Instructions ....................................................................................................... 7-25
Multiple Precision ...................................................................................................... 7-37
SBC-Il/21 PLUS Functional Block Diagram ........................................................... 8·2
SBC-II/21 PLUS Microprocessor.. ........................................................................... 8-4
Fetch/Read Transaction ............................................................................................. 8-7
Write Transaction ....................................................................................................... 8-9
IAK Transaction ....................................................................................................... 8-10
DMA Transaction ..................................................................................................... 8-11
ASPI Transaction ..................................................................................................... 8~ 12
BUS 'NOP Transaction ............................................................................................. 8-12
Mode Register Control ............................................................................................. 8-13
SBC-lI/2l PLUS Interrupt Control ....................................................................... 8-14
Interrupt Control Logic ............................................................................................ 8-16
Ready ........................................................................................................................ 8-18
IAKDIN .................................................................................................................... 8-l8
HALT Interrupt .........................................................: .............................................. 8-l9
Memory Maps .......................................................................................................... 8-22
RAM Memory .......................................................................................................... 8-23
Serial Line Interface Units ....................................................................................... 8-24
Parallel I/O Interface ............................................................................................... 8-26
Power-up ................................................................................................................... 8-27
Clock ......................................................................................................................... 8-28
Clock Control ........................................................................................................... 8-29
DMA ......................................................................................................................... 8-30
TSYNC ................................................ :.................................................................... 8-31
Read/Write .................,.............................................................................................. 8-32
Reply Time-out ......................................................................................................... 8-33
Bus Control .................................... ,.......................................................................... 8-34
DATI Bus Cycle ......................
9·6
. DATI Bus Cycle Timing ............................................................................................ 9-7
DATa or DATOB Bus Cycle ...... ,............................................................................. 9-9
DA TO or DA TaB Bus Cycle Timing ........... " ........................................................ 9-10
DMA Protocol .......................................................................................................... 9-1 1
DMA Request/Grant Timing .................................................................................. 9-12
Interrupt Request!Acknowledge Sequence .............................................................. 9-13
Power-Up/Power-[)own Timing ............................................................................... 9-15
Double-Height Module Contact finger Identification .............................................. 9·16
h

.................................................................................

FIGURES (Cont)
Figure No.
C-l
C·2
C~3

C-4
C-S
C-6

C-1
C-S
C-9
C-IO

C-Il

C-i2
H-I

Title

Page

Overview of Software Development .......................................................................... C-4
Application Overview ................................................................................................ C-5
Monitor Program ........................................................ '" ............................................ C-8
Load Map ................................................................................................................ C-I J
Power-up Task ......................................................................................................... C·II
Po"{er Fail Recovery ............................................................................................... C-I2
SLU Diagnostic Task ................................................... ,.......................................... C-12
RAM Diagnostic Task .............. ,.............................................................................. C-13
ROM Diagnostic Task ................. ~ ........................................................................... C-13
Parallel I/O Diagnostic Task .................................................................................. C-14
Control Task ............................................................................................................ C-14
Power Fail Task ....................................................................................................... C-tS
SBC-ll/2) PLUS Memory Maps ............................................................................ H~3

TABLES
Table No.
lot
\-2

2· J
2-2
2-3
2-4
2-5

2-6
2-7
2-8
2-9
2-10
2-11

2-12
2-13
2-14
2-15
4-1
4·2
5-1
5-2
5-3
6-1

6-2
6-3

6·4
6-5

6-6

Title

Page

SOC-li/21 PLUS Module Backplane Pin
Identification ............................................................... ,. .............................................. 1~5
Related Documentation .............................................................................................. 1-7
Configuration Pin Definitions .......................................................................... ,.......... 2-3
Configuration Pin Functions ........................................................................................ 2-5
Standard Factory Configuration ................................................................................. 2-7
Mode Register Configuration ..................................................................................... 2-9
Mode 0 Buffer Configuration (No Handshake) ....................................................... 2-13
Mode 1 Buffer Configuration (Strobed 1/0) ........................................................... 2-14
Mode 2 Buffer Configuration and Handshake ......................................................... 2-15
SLU 1 BREAK Detection ......................................................................................... 2-15
Memory Map Configurations ................................................................................... 2-20
Socket Set A Configuration for EPROM/PROM/EEPROM ............................... 2-20
Socket Set B Configuration for EPROM/PROM/EEPROM ................................ 2-21
Socket Set A Configuration for RAM .................................................................... 2<!2
Socket Set B Configuration for RAM ..................................................................... 2-22
EIA Slew Rate Resistor Values ............................................................................... 2-26
Diagnostic Fault Indicators ....................................................................................... 2-29
Macro-ODT Commands ........................................................................................ '" ... 4-3
Macro-ODT States and Valid Input Characters ........................................................ 4-4
Processor Status Word Bit Descriptions..................................................................... 5-3
PSW Interrupt Levels ................................................................................................. 5-3
SBC-tl/21 PLUS Interrupts ..................................................................................... 5~5
Serial Line Unit Register Addresses .......................................................................... 6-3
Receiver Control and Status Bit Descriptions ............................................................ 6-4
Receiver Data Buffer Bit Descriptions ....................................................................... 6-4
Transmitter Control and Status Bit Descriptions.. ..................................................... 6-4
Transmitter Data Buffer Bit Descriptions .................................................................. 6-7
Parallel I/O Register Addresses ................................................................................. 6-8

TABLES (Cont)
Table No.
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-2}
6-22
6-23
7-1
7-2
7-3
7-4
7-5
8-1
8-2

8·3
8-4
9-1
9-2
9-3
9-4
A-I
8-1
8~2

H-I

H-2
H-3

Title

Page

Mode 0 Configuration .............................................................................................. 6-10
Mode 0 Port A or B Bit Descriptions ...................................................................... 6-11
Mode 0 Port C Bit Descriptions ............................................................................... 6-12
Port C Control Signals in Mode 1 ........................................................................... 6-13
Combinations of Mode 1.......................................................................................... 6-14
Mode J Port C Bit Descriptions ............................................................................... 6-15
Mode 1 Configuration .............................................................................................. 6-18
Port C Control Signals in Mode 2 ........................................................................... 6-19
Mode 2 Port C Bit Descriptions ............................................................................... 6-20
Mode 2 Configuration .............................................................................................. 6-21
Control Register Mode Selection Bit Functions ....................................................... 6-22
Control Words for Mode Selection .......................................................................... 6-23
Control Register Bit Set/Reset Functions ............................................................... 6-24
Interrupt Set/Reset Control Words ......................................................................... 6-24
Mode I Input Handshaking Signals ......................................................................... 6-25
Mode 1 Output Handshaking Signals ...................................................................... 6-27
Mode 2 Bidirectional Handshaking Signals .............................................................. 6-29
Sample SBC-lI/2} PLUS Instructions ..................................................................... 7-4
Direct Addressing Modes ........................................................................................... 7·4
Indirect Addressing Modes ...............
7-14
Register Addressing Modes ...................................................................................... 7-18
SBC-ll/21 PLUS Instruction Set. ........................................................................... 7-26
Start Address Configurations ................................................................................... 8-14
Designated Interrupts ................................................................................................ 8-t7
Serial Line Unit Registers ........................................................................................ 8-25
PPI Addressable Registers ....................................................................................... 8-26
Signal Assignments ..................................................................................................... 9-3
Data Transfer Operations ........................................................................................... 9·4
Bus Signals Used in Data Transfer Operations .......................................................... 9-4
Bus Pin Identifiers .................................................................................................... 9- I 7
Instruction Timing ......................................................... :........................................... A-I
SBC-t1/21 PLUS, LSI-tI/2, and LSI/l 1123 Comparisons .................................... B-l
Illegal Address Traps ............................. '" .................................................................. 8-6
FPLA Code for the SBC-11/21 PLUS .................................................................... H-2
Option 23-77C6-00 FPLA Code ............................................................................... H-4
Functional Equivalent Pins ........................................................................................ H-8
n

......................................................................

PREFACE

This User's Guide provides the user with configuration. system architecture, and programming information for the SBC-11/21 PLUS single-board computer. Appendix H presents a list of the differences
between the SBC-II/l1 and the SBC-lI/21 PLUS so that a user who is familiar with the SBC-11/21
may easily configure the SBC·II 121 PLUS.

NOTE

This User's Guide is for use with the SBC-H/ll
PLUS module, M7676 and subsequent revisions
only. This revision is identified by the circuit board
5016277 loeated on the module as described in
Fiaure 1-1.

xiii

CHAPTER 1
INTRODUCTION

1.1 INTRODUCTION
The KXTll·AB (M7676) module, called the SBC-l1/21 PLUS single-board computer, is shown in Figure
1-1. It is a complete computer system on an 8.5 X 5.2 inch printed circuit board that executes the well
known PDP-It instruction set (see Appendix B). The SBC- I 1/21 PLUS module contains 16Kb (kilobytes)
of RAM, sockets for up to 32Kb of PROM or additional RAM, two serial I/O lines, twenty-four lines of
parallel I/O, and a 50 Hz, 60 Hz, or 800 Hz real-time clock. In addition, the SBC-ll/21 PLUS supports
the complete LSI-II bus interface that enables it to communicate with most of Digital's large family of
modules (see Chapter 3), For a description refer to the Microcomputer Interfaces and Microcomputers
and Memories handbooks.

C19

C21

cn C26

REVISION

STATUS

C15 RtO

C24

C33
ell

C35
R9

C27
C2

C23

Figure t-l

KXTll·AB (M7676) SBC-lI/2l PLUS Module

C25

----11!11111

_ _"c,._.~~ __c~~~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

The SOC> II /21 PLUS computer features the following:
•

A powerful processor running the PDP-Ii instruction set.

•

Direct addressing of 32K, 16-bit words or 64K. 8-bit bytes (K = 1024).

•

Efficient processing of 8 bit characters without the need to rotate, swap, or mask.

•

On-board 16Kb of static read/write memory.

•

Sockets for up to 32Kb of PROM for a wide range of memory types from many vendors.
, Additional RAM can also be installed in these sockets.

•

Hardware memory stack for handling data, subroutines, and interrupts.

•

Direct memory access for high data rate devices.

•

Eight general-purpose registers for data storage, pointers, and accumulators; two are dedicated:
stack pointer (SP) and program counter (PC).

•

Fast on-board bus for high throughput when external memory access is not needed.

•

LSI-I! bus structure that provides position dependent priority for peripheral device interfaces
connected to the bus.

•

Fast vectored interrupt response without device polling.

•

A powerful set of instructions.

•

Two serial I/O interfaces, compatible with EIA RS-232C and EIA RS-423 , with software
programmable baud rates over the range of 300 to 38,400 baud.

•

One parallel I/O interface with two bidirectional 8-bit input/output ports and one 8-bit control
port.

•

Real-time clock that can be set by the user to 50 Hz, 60 Hz, or 800 Hz.

•

Jumper-selected operating modes, including four memory maps, exception handling, start and
restart addresses, parallel I/O configurations, and real-time clock frequency.

•

Optional PROM resident Macro-ODT containing module diagnostics, bootstrap programs for
mass storage devices (TUS8, RXOl, RX02, RLOI, RL02, RX50, and RD51 devices), console
communications, and on-line debugging facility.

•

Supports RT-ll VS.l or subsequent versions and MicroPower/Pascal V1.5 or subsequent
versions.

•

For detailed differences between the SBC-Il /21 and SBC-lt /21 PLUS see Appendix H.

1-2

1.2 SPEC1FlCAnONS
The Sse-Ji/21 PLUS module specifications follow:

1.2.1

Playslcal
Height

13.2 cm (5.2 in)

Length
(includes module handle)

22.8 em (8.9 in)

Width

1.27 em (0.5 in)

Weight

255 g (8.5 oz) typical

1.2.2 Power Requirements
Power Supply:
+5.0 V ± 5%

2.5 A (typical), 2.8 A (maximum)

+12.0 V ± 5%

60 mA (typical) used by on-board circuitry, 1.1 A (maximum)
includes current provided to outside interface through pin 10 of
the serial I/O connector

Battery Backup:
+5.0 V ± 5%

170 mA (typical), 260 mA (maximum)

NOTE
The +12.0 V typical current is measured with no
coanections at pin 10 of the serial I/O connectors
(fused liDe).
1.2.3 Bus Loading
AC Loads
DC Loads

2.7
0.5

1-3

1.2.4

Environmental
Temperature:
-400 C to 66° C (-400 F to 1500 F)
5° C to 600 C (41° F to 140" F)

Storage
Operating

NOTE
The module must be brought into the operating temperature environment and allowed to stabilize before
operating.
Relative Humidity:
10% to 95% (no condensation)
10% to 95% (no condensation)

Storage
Operating
Altitude:

Up to 15 km (50,000 ft)
Up to 15 km (50,000 ft)
(90 mm mercury minimum)

Storage
Operating

NOTE
Lower the maximum operating temperature by 10 C
(1.80 F) for each 300 m (1,000 ft) of altitude above
2.4 km (8,000 ft).
Environment:

Air must be noncaustic.

Airflow (operating):

There must be enough airflow to limit the input to output temperature rise across the module to 5" C (9" F) when the input
temperature is 60° C (1400 F). For operation below 55° C (131 0
F), there must be enough airflow to limit the input to output
temperature rise across the module to 100 C (18° f) maximum.

NOTE
These are design limits. Lower temperature limits
will help increase the life of the product.
1.3 BACKPLANE PIN IDENTIFICATION
Table 1-1 lists backplane pin connections for the SBC-II /21 PLUS module, pin identification and signal
names unique to the SOC-II /21 PLUS module. and standard LSI~ II bus backplane names assigned to
each pin. Although the signal names may differ, the module is completely LSI-II bus compatible with the
exception of bus refresh transaction (BREF) which is not performed by the SOC-II /21 PLUS. Signals
STOP L, SRUN L. and START L are not used on the LSI-Il bus. These are TTL level signals unique to
the SBC-Il/21 PLUS.

1-4

Tallie I~t SIIC-Il/ll PLUS MCNIuIe Backplaae Pia '_tuteation .
Baclplaae
Pill

SBC-1l/11 PLUS
SipaI Fuactioa

lSI-II Bas
Signal Name

Side 1 (Cempoaellt Side)

AAI
ABI
ACI
ADI
AEI
AFI
AHI
AJI
AKI
All
AMI
ANI
API
ARI
ASI
ATI
AUl
AVI
BAI
BBI

DCI
BDI
BEl
BFt
BHl
BJI
BKI
BLI
BM)
BNl
BPI
BRI
BSI
BTl
BUI
BV}

Bus terminator

Bus terminator
Bus terminator
Bus terminator
srOPL
SRUNL
Not connected
GND
Not connected
GND
GND
BDMRL
BHALT L
Bus terminator
Not connected
GND
Not connected
+5 VB (battery)
BOCOK H
BPOKH
Bus terminator
Bus terminator
Bus terminator
Bus terminator
STARTL
GND
Not connected
Not connected
GND
BSACK L
Bus terminator
BEVNT L
Not connected
GND
Not connected,.
+5 V

1-5

BIRQ5 L
BIRQ6 L
BDALl6 L
BDALl? L
SSPAREI
SSPARE2
SSPARE3
GND
MSPAREA
MSPAREA
GND
BDMRL
BHALT L
BREFL
+12B
GND
PSPAREI
+5B
BOCOK H
BPOKH
SSPARE4
SSPARE5
SSPARE6
SSPARE7
SSPARE8
MSPAREB
MSPAREB
BSACK L
BIRQ? L
BEV~T L
+12B
GND
PSPARE2
+5 V

Table I-I

SOC-I1/21 PLUS Module Backplane Pin Identification (Cont)
SBC-H/21 PLUS
Signal Function

LSI-ll Bus
Signal Name

AA2
AB2
AC2
AD2
AE2
AF2
AH2
AJ2
AK2
AL2
AM2
AN2
AP2
AR2
AS2
AT2
AU2
AV2

+5 V
Not connected
GND
+12 V
BOOUT L
BRPLY L
BDIN L
BSYNC L
BWTBT L
BIRQ4 L
Not connected
BIAKO L
BBS7 L
Not connected
BDMGO L
BINIT L
BDALO L
BDALI L

+S V
-12 V
GND
+12 V
BOOUT L
BRPLY L
BDINL
BSYNC L
BWTBT L
BIRQ4 L
BIAKI L
BIAKO L
BBS1 L
BDMGI L
BDMGOL
BINIT L
BDALO L
BDALI L

BA2
BB2
BC2
BD2
BE2
BF2
BH2

+5 V
Not connected
GNO
Not connected
BDAL2 L
BDAL3 L
BDAL4 L
BDALS L
BOAL6 L
BOAL7 L
BOAL8 L
BOAL9 L
BOALlO L
BOALlI L
BOALl2 L
BOALl3 L
BOALl4 L
BDAL15 L

+5 V

BackpJane
Pin
Side 2 (Solder Side)

BJ2

BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2

1-6

-12 V

GND
+12 V
BDAL2 L
BDAL3 L
BDAL4 L
BOALS L
BDAL6 L
BDAL1 L
BDALS L
BOAL9 L
BOALlO L
BOALI I L
BOALl2 L
BOALl3 L
BDAL14 L
BOAL1S L

I." RELATED DOCUMENTS
This User's Guide is the primary reference document for the SBC-ll/21 PLUS. Important information
about other lSI-II bus compatible products may be found in the publications listed in Table 1-2.

Table 1-2

Related DocUlllelltatlon

ntle

Document Number

Microcomputers and Memories Handbook. 1982 Edition

EB-20912-20

Microcomputer Inter/aces Handbook. 1980 Edition

EB-20l75-20

PDP-lJ Bus Handbook. 1979 Edition

EB-17525-20

Guide to RT-ll Documentation

AA-5285G-TC

MicroPower/Pascal RT-Il

QJ029GZ

These documents can be ordered from:
Digital Equipment Corporation
Printing and Circulation Services
444 Whitney Street
Northboro. MA 01532
Attention:

Communications Services (NR2/M15)
Customer Services Section

1-7

CHAPTER 2
INSTALLATION

2.1

INTROOUCl10N

The installation of tbe SBC-Il/21 PLUS single-board computer module is discussed in this chapter. The
following five items. which are an integral part of the installation procedur~, are covered in detail.

NOTE

It Is best to leate the fadory configuration as Is
until module performance has been verified.

J•

Installing jumpers to select operational features.

Selecting and mounting an LSI-II bus structured backplane and adding any required LSI-II
. bus options.

Selecting an,d connecting an appropriate power supply.

Providing appropriate cables to connect external devices to the serial line and parallel I/O
interfaces.
.

Verifying operation of the module.

2.2 SELECTING OPERATIONAL FEATURES
The module has sixty-one .wirewrap pins with which the user configures the module for the operating
modes necessary to meet any requirements. This is done by either installing or removing jumper wires
between the wirewrap pins. The locations and identification numbers of the wirewrap pins are illustrated in
Figure 2-1. Table 2-1 defines the wirewrap pins, and Table 2~2 lists the pin functions by the features they
support. The selectable features are battery backup, power~up, starting address, interrupts, parallel I/O
buffers. and memory maps. Detailed requirements for each of these configurations are described in the
following paragraphs. The standard factory configuration is described in Table. 2-3.

2.2.1

Battery Baekup

The user can select battery backup mode to maintain a +5 Vdc battery supply to: (1) the 16Kb of onboard static RAM, (2) 24-pin devices in socket set A and (3) 28-pin or 24-pin devices in socket set B. The
+5 Vdc battery supply is provided through the LSI-II bus pin AVI. A maximum of 2mA is required. This
supply is connected to wirewrap pin M 16.
To enable battery backup, the jumper wire between MI and MI5 is removed and a jumper wire is
installed between M16 and MIS. This provides battery backed up power for the 16Kb of on-board static
RAM. To enable battery backup of 24-pin deviceS in socket set A, a jumper wire is installed between M7
and M41. To enable battery backup of 28-pin devices in socket set B, a jumper wire between M59 and
M41 is installed. To enable battery backup of 24-pin devices in socket set B, a jumper wire between M66
and M34 is installed.

2-1

DODD
1'1152 1'1153 1'1158 M65

0000

~
...
C"i
W

MM 1'1150 1'1151

ODD

gggD~~
~=----Il
cco

1'1149 M25

00
0000

1'112

DO
1'113 1'1121

0000 w

1'1155

1'1118 1'1126 1'1129

DODD
DODO
ODD
DOD

ooaa C"i

000 N
CCO W

1'1131

M74

1'115

Mf!

Ml? 1'1120 1'<117 1'1124

1'1128

MIl

MI9

1'119

M23 Nl27

..=:=:.. . . -;...;.;"..,0
o
o
o

0000
0000
00

o
8114

~==::: !===~ a a 0 0

0000

MID

~(j

M34

DODO
I'll""
M66 M64

L....._--t

~~~

1'1163 81136

DODO

1'1137 1'1135 81146 M56

0000
Ml9 1'1148 1'1157 M44

00'

M10M1S'
M16
Mal

1'1133

Figure 2-1

1'1159

[J.f]
0 0
8116 M7 1'1113 1'1114

SBC-Il/21 PLUS Module Layout .

2-2

Table 1-1

Configuration Pin Definitions

Schematic
Sheet
Number

Description

MI
M2
M3
M4
M5

5
2
2
3
3

System +5 V power (+5 VNCR)
System GND
High logic level (+3 Vdc)
Wake up circuit diode, anode side
Receive side of BHALT line transceiver

M6
M7
M8
M9
MIO

3
5
3

Wake up circuit diode, cathode side (+5 VNCR)
Socket set A, high and low byte, pin 26
BREAK request clock line
High logic level (+3 Vdc)
Address line 14

6
5
5
5
5

System GND
High logic level (+5 VNCR)
Socket set B, high and low byte, pin 1
Socket set A, high and low byte, pin I
+5 Vdc power distribution to support static RAM

MI7

5
6

Battery backup +5 Vdc power source
Serial line unit (SLU) I BREAK detect, interrupt request output

Ml8
M19
M20

2
6
3

High logic level (+3 Vdc)
60 Hz real-time clock output
Transmit side of BHALT line transceiver

M21
M22
M23

2
I
6

M24
M25

5
2

Memory map select (MSB)
Start address control (TDAL 15)
Transmit side of BEVNT line transceiver
System GND
Memory map select (LSB)

M26
M27
M28
M29
M30

1
6
6
I
1

Start address control (TOAL 14)
50 Hz reaHime clock output
800 Hz reaHime clock output
System GNO
Start address control (TOAL 13)

M31
M32
M33
M34
M35

3
I
5
5

System GND
System GND
Socket set B, high byte, pin 27
High logic level (+5 VCR)
Socket set B, low byte, pin 23

Mil
MI2
MI3

M14
MI5
Ml6

Table 2-1

Schematic
Sheet
Number

M36
M37
M39
M40
M4!

M42
M44
M46
M48
M49

M50
M51
M52
M53
M54
M55
M56
M57
M58
M59
M61
M63
M64
M65
M66
M74

5
5
5
5

5
5

Configuration Pin Definitions (Cont)

Description
High logic level (+5 VNCR)
Socket set A, low byte, pin 27
Socket set A, high byte, pin 27
Socket set A, low byte, pin 23
High logic level (+5 VCR)
Address line 15
Address line 12
High logic level for PROMs (+5 VNCR)
Socket set S, low byte, pin 27
Port B buffer direction control

High logic level (+3 Vdc)

7
7
7
7

System GND

5
5

System GND
High byte write strobe (-WHB)
Low byte write strobe (-WLB)
Port C PC4 output (E26 pin 13)
Socket set B, high and low byte, pin 28

5
7
5
5

5
5
7
5
I

Port A buffer direction control
Port C buffered output, to J3 pin 7
Port C PC6 output (E26 pin t I)

Socket set A, high byte, pin 23
Socket set S, high byte, pin 23
RAM, high and low byte, pin 26
Port C buffered output, to J3 pin 5
Socket set Bt high and low byte, pin 26
-CTMER interrupt enable

2-4

Table 1..1 Configuration Pin Functions

Function

Description

Battery backup
MI6
MI5
Ml
M36
M41
M34
M14
M13
M7
M66
M59
M64
M4

Battery backup +5 Vdc power source
+SVdc power distribution to support static RAM
System +5V power (+5 VNCR)
High logic level (+5 VNCR)
Higb logic level (+5 VCR)
High logic level (+5 VCR)
Socket set A, high and low byte, pin 1
Socket set B, high and low byte, pin I
Socket set A, high and low byte, pin 26
Socket set B, high and low byte, pin 26
Socket set B, high and low byte, pin 28
RAM, high and low byte, pin 26
Wake-up circuit diode, anode side
Power·up (wake·up circuitry)

System +5 V power, wake-up circuit diode, cathode
side (+5 VNCR)
Wake-up circuit diode, anode side

M4
Serial line unit (SLU) I
M31
M20
M17

System GND
Transmit side of BHALT line transceiver
Serial line unit (SLU) 1 BREAK detect
Serial line unit (SLU) 2
Transmit side of BEVNT line transceiver
50 Hz real-time clock output
60 Hz real-time clock output
800 Hz real-time clock output
System GND
High logic level (+3 Vde)

M23
M27
M19
M28
Mil
M9
Memory map decoder

High logic level (+3 Vde)
Memory map select (LSB)
Memory map select (MSB)
System GND

M3
M25
M21
M2
Start address
(mode register)

2-5

Table 1-1 Configuration Pin Functions (Cont)
Pin

Function

M30
M26
M22

Description
Start address control (TDAL 13)
Start address control (TDAL 14)
Start address control (TDAL 15)
High logic level (+3 Vde)
System GND

MI8
M29

Nonmaskable interrupt and trap to the restart address
M74
M32

HALT request line
System GND
BHALT interrupt
(level 7, maskable)

M20
M31
M24
Ml7

Transmit side of BHALT line transceiver
System GND
System GND
Serial line unit (SLU) 1 BREAK detect, interrupt
request output
Receive side of BHALT line transceiver
BREAK request clock line

M5
M8
Memory
Ml4
MI3
M7

M66
M59
M64

M6t
M40
M63
M35

M39
M37
M33
M48
M44

M56
M57
Ml
M6

M36
MI2
M46
M34

MI5
M41

Socket set A, high and low byte, pin 1
Socket set B, high and low byte, pin 1
Socket set A, high and low byte, pin 26
Socket set B. high and low byte, pin 26
Socket set B, high and low byte, pin 28
RAM, high and low byte, pin 26
Socket set A, high byte, pin 23
Socket set A, low byte. pin 23
Socket set B, high byte, pin 23
Socket set B, low byte, pin 23
Socket set A, high byte, pin 27
Socket set A, low byte, pin 27
Socket set B, high byte, pin 27
Socket set B, low byte. pin 27
Address line 12
High byte write strobe (-WHB)
Low byte write strobe (-WLB)
High logic level (+5 VNCR)
High logic level (+5 VNCR)
High logic level (+5 VNCR)
High logic level (+5 VNCR)
High logic level (+5 VNCR)
High logic level (+5 VCR)
High logic level (+5 VCR)
High logic level (+5 VCR)

2-6

Table 2-2 Configuration Pin Functions (Cont)
Pin

Function

Description

Parallel input/output
M49
MSl
M55
M65
M53
M58
M54
M50
M52

Port B buffer direction control
System GND
System GND
Port C buffered output, to 13 pin 5
Port C buffered output, to 13 pin 7
Port C PC4 output (8255A-5 pin 13)
Port C PC6 output (8255A-5 pin II)
High logic level (+3 Vde)
Port A buffer direction control

Table 2-3 Standard Factory Configuration
Jumpers
Installed

Function

Between

No Battery backup
Wake-up circuit enabled

Ml to MI5

Start Address'" 10000
Restart address 10004

M22 to MIS
M26 to M29
M30 to M26

Memories:
Map 0

M64 and M7
M25 to M21
M21 to M2

Skt A contains 2K X 8 EPROM

skt A

M7 to M6
M61 to MI2
MI2 to M40

Skt B contains 8K X 8 SRAM

skt B

M59 to M36
M33 to M56
M48 to M57
M66 to M4
M63 to M44
M35 to M44

•

Before use with Macro-ODT. the start address must be changed to 172000 as described in Table 2·4.

2·7

Table 2-3 Standard Factory Configuration (Cont)
Jumpers

Installed
Between

Function
Interrupts:
SLUJ BREAK asserts HALT
and is received as level 7
interrupt (Vector 140)

M17 to M20
M5 to M8

60 Hz Real time clock asserts BEVNT

M19 to M23

Parallel flO Port A receive
Port B transmit

M52 to M50
M49 to M51
M65 to M58

M74 to M32

If the battery backup option is enabled, the wake-up circuitry must also be enabled (see Paragraph 2.2.2)
for all RAMs on the board. The wake-up circuitry is enabled by ensuring that no jumper is installed
between M4 and M6 (this is the standard factory configuration).
2.2.2 Wake-Up Circuit
The module has an on-board power wake-up circuit designed for use in systems without the LSI-Il bus
power sequencing protocol or in systems with battery backup. This circuit holds the BOCOK line negated
until one second after +5 V power is applied. When the module is used in an LSI-II backplane that has a
power sequencing routine, the module wake-up circuit must be disabled. To do this, a jumper wire is
installed between M6 and M4. The jumper wire is removed when using power supplies without power
sequencing or when the battery backup option is installed. The module requires the +5 Vdc and +12 Vdc
power supplies to have a rise time of less than 50 ms.
2.2.3 Starting Address
The user selects the starting address for the microprocessor via wirewrap pins. When the module is
powered up, the microprocessor loads this value into R 7 (program counter) as. the first fetch address. The
wirewrap pins are M22, M26, M29. M30. and M18, and are defined in Table 2·1. The user can select
from eight available starting addresses. Table 2~4 lists these available addresses and the jumper connections required for each address. The restart address is always the start address incremented by four. The
wirewrap pin locations ate shown in Figure 2-1.
2.2.4 Interrupts
The SBC-lI/2l PLUS implements a multilevel interrupt system that has eleven separate interrupts. See
Table 5-3 for a complete list of system interrupts. Three interrupts, eTMER, BKRQ. and REVNT. are
user configurable by means of jumper wires as shown in Figure 2-2 and are discussed here.

2-8

Table 2-4

Start

Mode Register Configuration

Address

Restart
Address

Connect
M22 to

000000
010000*
020000
040000
100000
140000
172000
173000

000004
010004
020004
040004
100004
140004
172004
173004

MI8
Ml8
M29
M29
M29
M29
MI8
MIS

- Connect
M26 to
M29
M29
MI8
MI8
M29
M29
MI8
MI8

Connect
M30 to
MI8
M29
MIS
M29
MI8
M29
MI8
M29

Factory setting. The start address should be selected in conjunction with the memory map configuration. Figure 2-6 shows
how the available start addresses fit into the memory maps.

The CTMER interrupt is at the highest level (nonmaskable). It is caused by a time-out, that is, a failure to
detect RRPL Y during a fetch/read, write, or IAK transaction. Such a condition could occur only jf the
peripheral that caused the interrupt failed to return BRPLY during the vector reading operation. See
Chapter 8 for a discussion of external interrupts. Figure 2-3 describes the sequence of events that takes
place during the IAK time-out.
The other two interrupts the user can select are BKRQ and BEVNT. Their vectors and priorities are
described in Table 5-3. All jumper combinations, which are "electrically correct" as shown in Figure 2·2,
are legal.
A description of some typical configurations follows to familiarize the user with the different combinations
available.
Install jumpers between

M7 and M74
M20 and M31
M28 and M23
M8 and M24

This arrangement allows the SLU 1 BREAK input to set the -CTMER nonmaskable interrupt and trap to
the restart address. The BHALT L bus signal is ignored. The SLU2 800 Hz line time clock and the
BEVNT L bus signal enable the REVNT interrupt.
Install jumpers between

M5 and M74
M17 and M8
M20 and M31
M23 and M71

This arrangement allows the BHALT L bus signal to set the -CTMER nonmaskable interrupt and trap to
the restart address. The SLU 1 BREAK input sets the BKRQ level 7 maskable interrupt, and only the
BEVNT L bus signal enables the REVNT interrupt.

2-9

GND ~ _______ ~ 0

-HTRP
TIMEOUT

El
CAS

-CTMER

-B2CLR

+3 VDC
I

BKRO

0
M5 ________ ~ C

SLUI
M17
M20
BREAK ---0- __ -I'"J THAL T

NONMASKABLE
INTERRUPT

CBKRO

E19

E2
CAS

LEVEl.. 7
MASKABLE
INTERRUPT

M31
GND--o

•
o

SHALT L

RESET

BeVNT L

REVENT

M27

50HZ - - 0

SLU2{
LTC

-B2CLR

+3 VDC

f19

M19
M23
60HZ ---0-- --0 TEVNT

!NTERRUPT
LEVEL 6

M28

800HZ - - C

+3 VDC

RESET

----0
M11

GND - - 0
MA-12l't4

Figure 2·2

Interrupt Configurations

LSI-l1 BUS INTERRUPT
(BIRQ41

PROCESSOR RETURNS IAK

TIME-OUT DURING IAK

NOCTMER

PC AND PSW PUSHED ON THE STACK
PC AND PSW LOADED FROM VECTOR AND VECTOA +2
(VECTOR IS 0 BECAUSE NOTHING IS DRIVING TDAL)

JUMP TO NEW PC
MA-'t2T1S

Figure 2-3

Install jumpers between

Time-out During LSI-II Bus Interrupt Acknowledge

M74 and M32
Ml7 and M20
M5 and M8
M23 and M9

This arrangement allows the time-out (TMER) to set the -CTMER nonmaskable interrupt for aU timeouts. The SLUI BREAK or the BHALT bus signal set the BKRQ level 7 maskable interrupt, and the
BEVNT L bus line is clamped low and therefore, no interrupts can be generated by BEVNT L.

2.2.5 Parallel I/O
The parallel I/O is implemented with the 8255A-5 programmable peripheral interface (PPI) and connects
to the user's interface through the J3 connector. Figure 2-4 illustrates the wirewrap pins used for the
configuration of the parallel I/O. (These pins are defined in Table 2-1.) The dash lines in Figure 2-4
represent the factory configuration jumpers installed. (The wirewrap pin locations are shown in Figure 21.) The directions of port A and port B transceivers are dependent on the logic level connected to M49 and
M52. Wirewrap pin 52 connects to port A through a 200 ns minimum rise time edge delay circuit. When
M50 (+3 Vdc) is jumpered to pins M49 and M52, port A and port B buffers are inputs to the PPI from
the 13 connector. When M51 (GND) is jumpered to pins M49 and M52, port A and port B buffers are
outputs from the PPI to the J3 connector.
The direction of port A and port B can also be controlled by a user's program. To make this possible, M58
and M54 must be jumpered to M49 and M52. The data outputs via port C will control the voltage levels at
the direction control inputs to ports A and B. The software required to do this control is discussed in
Chapter 6.

pea
PC3 } INTERRUPTS

pca

n4tsi4~:1
BUFFERS

PCI

PC2

PC3

PORT C

6
7
PC]

LED

M55
GNO--o
M51
M49
GND-Q--PORT A BUS
TRANSCEIVERS

1
Figure 2-4

C22

Parallel I/O Configuration

Wirewrap pins M65 and M53 can be jumpered to M49 and M52 to allow the user to control the direction
of the transceivers via 13 connector pins 5 and 7. When not using wirewrap pins M58 and M65 or M54
and M53 to control the direction of ports A and B, jumpers connected between M58 and M65 and
between M54 and M53 allow PC4 and PC6 to be used as inputs to the PPI from the 13 connector.

NOTE
If pins M65, M53, M58, or MS4 are used for program control of port A or B, the user must ensure
tbat tbe PPI and tbe buffer do not contend as driver
output to driver output. If tbis condition is allowed
to occur, damage to botb drivers may result.
The programmable peripheral interface can function in three modes selected by software. The jumper
configurations and the handshake signals for each of these modes are shown in Table 2-5, Table 2-6, and
Table 2-7. See Chapter 6 for programming information.

2.2.6 Serial I/O
The jumper options relating to the serial I/O determine the interrupt response of the system and were
explained in Paragraph 2.2.4. AU responses to the BREAK detection by SLUl are listed in Table 2-8.

2-12

Table :Z·S

Mode 0 Buffer Configuration (No Handshake)

PPI
Element

To Act
as Input

To Act
as Output

Program Control
via Port C

Port A

M52 to M50

M52 to M51

M52 to M54 or M58

Port B

M49 to M50

M49 to M51

M49 to M54 or M58

PC7

Never an input

Always an output

PC6

M54 to M53

Never an external
output

PC5

Never an input

Always an output

PC4

M58 to M65

Never an external
output

PC3

Never an input

Interrupt A
(vector 134)
Always an output

PC2

Always an input

Never an output

PCl

Never an input

Always an output

PCO

Never an input

Interrupt B
(vector 130)
Always an output

Table 2-6
PPI

Mode I Buffer Configuration (Strobed I/O)

Element

To Act
as Input

To Act
as Output

Program Control
via Port C

Port A

M52 to M50

M52 to M51

N/A

Port B

M49 to M50

M49 to M51

M49 to M54 or M58

PC7

Never an input

Indicates
buffer A full

PC6

MS4 to M53
(Acknowledge A)*

Never an
external output

peS

Never an input

Indicates
buffer A fun

PC4

MS8 to M65
(Strobe A)

Never an
external output

PC3

Never an input

Interrupt A

PC2

Strobe B
in input mode
Acknowledge B in
output mode

Never an output

PCI

Never an input

Buffer B full
on input or output

peo

Never an input

Interrupt B
(vector 130)

·User's hardware acknowledges receipt of data output by port A.

2-14

Table 2-7

Mode 2 Buffer Configuration and Handshake

PPI Element

Input Signal

Output Signal

Port A

Bidirectional bus

If M52 to M54 to MS3

Port B

Not used in mode 2

PC7

Never an input

Output buffer A fuJI

PC6

Acknowledge A

Never an output

PCS

Never an input

Input buffer A full

PC4

Strobe A (if M65 to M58)

Never an output

PC3

Never an input

Interrupt A

PC2

Always an input

Never an output

PCI

Never an input

Always an output

PCO

Never an input

Always an output

Table 2-8 SLUl BREAK Detedion
Jumper Connection*

BREAK Response

M17 to M20

BHALT L signal to the LSI-II bus
and BKRQ interrupt (vector 140)

M5 to M8
M20 to M31
MS to M8

No response

M8 to M17
M20 to M31

BKRQ interrupt (vector 140)
(no BHALT L to bus)

M17 to M74

CTMER interrupt
(HALT trap) through restart

M20 to M31
M8 to M24
*Refer to Figure 2·2,

2-15

2.2.7 Memories
The memory system for the module is the LSI-II bus, 4Kb of local RAM, and four 28-pin sockets that
accept either 24-pin or 28-pin industry standard +5 V memory chips. These chips are provided by the user
and can be either EEPROMs, EPROMs, PROMs, ROMs, or static RAMs. The sockets will accept 2K X
8, 4K X 8, 8K X 8, and 16K X 8 PROMsjEPROMs/EEPROMs. or 2K X 8, and 8K X 8 static RAMs.
There are two socket sets: set A which is controlled by -CSKTA and set B which is controlled by
-CSKTB. Each set has a high byte socket and a low byte socket that are interconnected as shown in
Figure 2-5. The wirewrap pins used to configure the memory are shown in Figure 2-6 and described in
Table 2-1. The standard factory configuration of the installed jumper wires is represented by the dash lines
in Figure 2-6. In addition to configuring the sockets, the user must configure the decode memory address
chip to select one of the four memory maps available.
NOTE
The SBe-H/21 PLUS contains semiconductor
devices that may be susceptible to damage by electrostatic charges. When handling the board and configuring the wirewrap pins, the board should be kept
on a grounded conductive plane. Also, wrist straps in
contact with the skin should be used to keep the
operator at the same ground potential.
2.2.7.1 Memory Maps - Figure 2-7 shows the four memory maps available. The module can be
configured to select the one that meets the user's requirements. Wirewrap pins Ml8, M21, M29, and M25
are used to select the memory map. The jumper requirements are listed in Table 2~9.
2.2.7.2 PROMs/EPROMs/EEPROMs - The 28-pin sockets accept 24-pin and 28-pin PROMs,
EPROMs or EEPROMs. If 24-pin chips are selected, caution must be observed to ensure that pin 1 of the
chip is placed into socket hole 3. The configuration requirements of some industry compatible
PROMs/EPROMs are described in Table 2-10 and Table 2·11. The user may select chips from other
vendors, however, the pin configuration must be compatible with the sockets provided. A 250 ns maximum output enable time is also required, and the maximum access time for compatible
PROMs/EPROMs is 450 ns. The maximum output enable time is defined as the time from the assertion
of TDIN or TOOUT by a bus master to the time the module asserts valid data onto the bus.
The user installs a jumper wire from the pin referenced by the chip type to the socket pin described in the
tables. Figure 2-6 provides a reference for all signals and th~ socket pins associated with the wirewrap pins.
These interconnections are listed separately under socket set A and socket set B. and some jumper wires
are common to both socket sets. Some devices may not require a connection or installation of a jumper
wire and are designated by an NC in the tables. The wirewrap pin locations are shown in Figure 2-1.
2.2.7.3 RAMs - The 28-pin sockets can also accept 24-pin static RAM chips, and caution must be
observed to ensure that pin 1 of the chip is installed into socket hole 3. The configuration requirements of
some industry compatible RAMs are described in Table 2·12 and Table 2-13. The user may select chips
from other vendors, however, the pin configuration must be compatible with the sockets provided. The
selected RAMs are required to meet the maximum output enable time and the maximum access time
specified for the PROMs.
The user installs a jumper wire from the pin referenced by the chip type to the socket pin described in the
tables. Figure 2-6 provides a reference for all signals and the socket pins associated with the wirewrap pins.
These interconnections are listed separately under socket set A and socket set B, and some jumper wires
are common to both socket sets. Some devices may not require a connection or installation of a jumper
wire and are designated by an NC in the tables. The wirewrap pin locations are shown in Figure 2-1.

2·16

28
M14
AD13
M41
+5 VCR --0
M34
+5 VCR -0

ADS

AD12 --0

AD3
XE31

-WHB --0

M57
-WlB --0

TOALlO

M6t

AD5

-READ

A04

ADll

AD3

-CSKTA

28PIN
SOCKETSETB
HIGHSYTE
XE32

TGA~j!j
13

TOAll0
15

TDAL11

GND

-CSKTS

tlt TGAU,

AD1

M63
-READ
AD!1

TOAl8

TOAlS

GND

AD2

MEi6
ADS
A010

ADS

AD4

A01
TDAlS

A07
28 PIN
SOCKET SET A
HIGH BYTE

M33

ADa

ADS

OM59

AD7

AD:!
M56

M13

M39

ADS
M44

+5 VNCR

16 TOAL12

Ot;

TDALl1

M46

to.)

-...J

+SVNCR --0
M12
+5VNCR --0

M36

+5VNCR --0
M6
+6VNCR --0

I -J
ACt3
ADS

.2
3

AD7
A06
AD5

28 PIN
SOCKETSH A
lOW BYTE

AD4
A03

TOAlO
TOAll
TDAl2
GND

AD13
ADS

AD9

AD10
M40

A07
ADS
ADS
AD4
AD3

XE38

A02
AOI

+5VNCR
M37

10
11
12
13
14

A02

28 PIN
SOCKET SET 8
lOW BYTE

XE39

23
22

M46

A09
AD10

M3S
-READ
AD11
-CSKTS

ADI

TOAL7

TDAlO

TOAlS

TDAll

TDAlS

TOAl2

TDAL4

GNO

TDAll
MR"12117

Figure 2-5 Socket Sets A and B Interconnection

1
I

+5 VNCR
M6

~ PIN1HIGHBYTESETB

""i_

~ PIN 1 LOW BYTE SET B

... ~ PIN 26 HIGH BYTE SET A

..........

r ~ PIN 26 LOW BYTE SET A
: ~ PIN 26 HIGH BYTE SET 8

.J.
I""'.....

.....

'\ I

M46"

+5 VCR

.....

: "

M34

M15

l ~ PIN 26 HIGH BYTE RAM
-~-~ PIN 26 LOW BYTE RAM

/,
'\

')-

WAKE UP

~ PIN 23 HIGH BYTE SET A

CIRCUIT

PIN 26 LOW BYTE SET B

~ PIN 28 LOW BYTE SETB

/11

M41

f. ~ PIN 28 HIGH BYTe SET B

',/

PIN 1 HIGH BYTE SET A

~ PIN 1 LOW BYTE SET A

'- ~ PiN 23 LOW BYTE SET A

t::'-~ PIN 23 HIGH BYTE SET B

-j

AD!2 ~_--

L~ PIN 23 LOW BYTE SET B

-WHB ~

~ PIN 27 HIGH BYTE SET A
.....

oME. PIN 27 LOW BYTE SET A
.....

.......

~ PIN 27 HIGH BYTe SET B

.....

+3VDC

GNO

~ PIN 27 LOW BYTE SET B

M25r----.,

!£..o..--

M21

DECODe
MEMORY
ADDRESS

NOTE: DOTTED LINES ILLUSTRATE FACTORY CONFIGURATION.

Figure 2~6

Memory Configuration

2-18

MAP 0
(1777761 64KB

128 BYTES
(NOTE 21
(NOTE 1)

(1740001 62KB

4KB
SOCKET A

(1640001 58K8
(1600001 56K8

L51·11 BUS

MAP 1

MAP2

64K 8

64K B
(NOTE 1)

62K 8
5BK B
56K 8

62K 8
14KB
SOCKET B

58K a
56K

1,~B~!TES
(NOTE 2)
(NOTE 1)

4KB
SOCKET A

MAP3

64KB
LSI·11 sus
(NOTE 1)

62K8
58K8

14K8
SOCKET B

56KB

aKB
LOCAL RAM
{140000}

48K B

48KB

(120000) 40K8

16KB
SOCKET B

40K 8

48K B

48KB

16KS
LOCAL RAM.

32K B

(100000) 32KB

LSI·1 f BUS

40K8

40K B

32K B

128 BYTES

32KB
SOCKET A

32KB

(NOTE 31

24K

i400001

16K8

(20000)

aKB

LSI·11 BUS

16K B

24K B

32KB
SOCKET A

LOCAL RAM

l6KB

16K B

aKB\-

8K B

OKa

OKS

24K8

16K8
SOCKETS

8KB

TSKS
LOCAL RAM

(~)

(NOTE4)
OKB

OKS

NOTES:

1. THIS SECTION CONTAINS HIE LOCAL I/O ADDRESSES FOR THE SLUS AND
PPL ALL UNASSIGNED ADDRESSES ARE ASSUMED TO RESIDE ON THE LSI·l1 BUS.
2. ADDRESSES 177177·177600 IN MAPS 0 AND:2 ARE RAM SCRATCHf'AD
LOCATIONS USED BY MACRO-ODT.

3. ADDRESSES 77777· 77600 IN MAP 2 ARE ALLOCATED TO THE LSI·11 BUS.
4. UNDERLINED ADDRESSES ARE JUMPER SELECTABLE START ADDRESSES.

(SEE TABLE 2·4)

Figure 2-7

Memory Maps.

2-19

Table 1-9 Memory Map ConfiguratioRs
Map Selection
Map 0
Map 1
Map 2
Map 3

Jumper MlS to

Jumper Mll to

M21

M29
M29
MIS
MIS

M1S
M29
M21

Table 2·10 Socket Set A Configuration for EEPROMs/EPROMs/PROMs

Parts

Pias Size

Connect Referenced
Pinto Socket A Pin
M40 M37 M7 M61 Mill M39

2815

2Kx8

MI2 NC

2716

2K X 8
2K X 8
2Kx 8

MI2 NC

2716-2

24
24
24

2732
2132A

24
24

4K X 8

M44

M44 NC

4K X 8

INTEL

2764

8K X 8

M44 M46 NC

INTEL

27128

16K X 8

M44 M39 MlO M44 M39 M36

TMS2516
TMS25 16-35

24
24

2K X 8

MI2 NC

Ml2 NC

2Kx 8

Mostek

MK2716

2K X 8

MI2 NC

Mostek

MK2764

8K X 8

M44 NC

M44 M36 NC

INTEL

3632

4K X 8

MI2 NC

M12 NC

INTEL

3632-1

4K X 8

MI2 NC

Veador
EEPROMs
INTEL
EPROMs
INTEL

2716~1

INTEL

M44 M36 M46

PROMs

NC - requires no connection.

2-20

T..lel.. n

Seelet Set B Configuration for EEPROMs/EPROMs/PROMs

Parts

PiBs Size

Connect Referenced Pia
to Seeket B Pia
M35 M48 M13 M63 M59 M66 M33

2815

2K X 8

MI2 NC

INTEL

2716
2716-1
2716-2

24
24
·24

2Kx 8
2K X 8
2K X 8

MI2 NC

INTEL

2732
2732A

24
24

4K X 8
4K X 8

M44 NC

INTEL

2764

8K X 8

M44 M46 M36 M44 M36 NC

M46

INTEL

27128

16 X 8

M44 M33 M33 M44 M36 MIO M59

TMS2516
TMS25 16-35

24
24

2K X 8
2K X 8

MI2 NC

Mostek

MK2716

2K X 8

MI2 NC

Mostek

MK2764

8K X 8

M44 NC

M36 M44 M36 NC

INTEL

3632

4K X 8

MI2 NC -NC- MI2 NC

INTEL

3632·1

4Kx 8

MI2 NC

_ VeBdor
EEPROMs
INTEL
EPROMs

PROMs

NC - requires no connection.

MI2 NC

Table 2~1l Socket Set A Configuration for RAM

Connect Referenced Pin
to Socket A Pin
Vemlor

Parts

Pins Size

M40 M37 M7

Mostek

MK4802

2K X 8

M57 NC

M34 M56

Toshiba

TMM2016P
24
TMM2016P-i
24
28
TC5565P/P-l
TC5565PL/PL-l

2K X 8

M57 NC

M34 M56

8K X 8

M44 M57 M34 M44 NC

M56

2K X 8
8K X 8

M57 NC M34 M56 NC
M44 M57 M34 M44 NC

Hitachi

HM6116P
HM6264P

24
28

M61 M14 M39

2K X 8

M56

NC - requires no connection.

Table 1-13 Socket Set B Configuration for RAM
Connect Referenced Pin
to Socket B Pia
M35 M48 M13 M63 M59 M66 M33

Vendor

Pam

Pins Size

Mostek

MK4802

2K X 8

M57 NC

Toshiba

24
TMM2016P
TMM2016P-l
24
28
TC5565P/P-l
TC5565PL/PL-l

2K x 8
2KX8
8K X 8

M57 NC

NC M56 NC M34 NC

M44 M57 NC

M44 M41 M41 M56

HM6116P

2K X 8

M57 NC

M56 NC

Hitachi

M56 NC

M34 NC

NC - requires no connection.

2.3 SELECTING BACKPLANES AND OPTIONS
A number of different LSI-ll bus compatible backplanes and boxes are available from Digital. The choice
is defined by system requirements such as the number and type of options (described in Chapter 3),
environment conditions, and packaging considerations. A list of aU available backplanes and boxes is
provided in the Microcomputer Interfaces Handbook.

2.4 POWER SUPPLY
The choice of power supply is controlled by the size of the system and packaging requirements. An
important consideration is the performance of the supply during power·up and power-down. All Digital
power supplies listed in the Microcomputer Interfaces Handbook are compatible with the LSI-It bus
protocol which aUows dependable operation with no loss of data when using battery backed-up memories.
Any user designed power supply must agree with the LSI-i 1 bus protocol.
2.SEXTERNAL CABLES
The module has a 30-pin connector (13) for an external interface with the programmable I/O interface
and two to-pin connectors (Jl and J2) for the external interface of the serial line units (SLUs). The
location of these connectors on the module is shown in Figure 2-1. The requirements to interface with these
connectors are defined in the following paragraphs.

2-22

1.5.1 Parallel I/O Interface (J3)
The module connector is a 30*pin AMP MODU connector with the I/O signals defined by Figure 2~8. The
I/O signals are buffered and are capable of driving up to 50 feet (maximum) of flat ribbon or round cable
with a 30·pin AMP contact housing at each end. The following list of conne<!tors is compatible with the
module connector.
AMP MODU polarized or non polarized contact housings for crimp snap.in pin and receptacle contacts:
Latching, polarized
housings:

2-87631-6 no strain relief
87733-6 strain relief

Nonlatching, polarized
housings:

1-87977-3 no strain relief
1-102184-3 strain relief

Nonlatching. non polarized
housings:

2-87456-6 no strain relief
2-87832-7 strain relief

Receptacle contacts:

87045-3 for 30 to 26 A WG
102098-3 for 32 to 27 A WG

Mass termination connectors for flat cables:
Separate parts:
( oonpolarized)

1-88378-1 connector
1-86873-2 cover
1-88340-1 strain relief cover

Separate parts:
(polarized)

1-88392- I connector
1-86373-2 cover
1-88340-1 strain relief cover

Connector and cover kits:
(non polarized)

1-88379-1 no strain relief
1-88476-1 with strain relief

Connector and cover kits:
(polarized)

1-88393-1 no strain relief
1-88478- I with strain relief

Separate parts:

1-88392-1 connector
1-86873-2 cover
1-88340-1 strain relief cover

Latching connectors and covers:
(polarized)

1-88423-1 no strain relief
1-88479-1 with strain relief

Mass modular connector system:

1-102393-3 housing for 30-26 AWG
1-102396-3 cover
1-102392-3 kit
1-102398-3 housing for 26-22 AWG
1-102396-3 cover
1-102397-3 kit

Connectors can be terminated to discrete wire in sizes 30-26 AWG, 26-24 AWG. as well as jacketed cable
and bonded ribbon cable.

2-23

PPI INTERFACE
CONNECTOR J3
~

LOOP8ACK

TEST CONNECTORS

9
3

JUMPER WIRES
(USED ONLY WHEN PORT A BUFFERS
ARE CONFIGURED AS INfIUTSAND
PORT 8 BUFFERS ARE CONFfGUREO
ASOUTPUTSI

4
PC3
PC4

10
5
6

PCS

8
12
PBl

PB2
PB3

18
20
19
11
13 ~

PBS

11
28

26 r--24
22
21

23
25
27

1
:2
15
16

GND

VIEW INTO THE CONNECTOR FROM THE MODULE EDGE
29

GND PAO PAl

PA2 PAl PB4

13 - 11

PBS ON!) PBS

P£l7 !'CO

pce PC4 PCl GNIl

GND PA7

PAS PAS PA4

pe3

PB2

OND P81 PBC Pel PCl PCS PC IGND

2 " PC
BOARD

Figure 2-8

30.. Pin Parallel I/O Connector

2-24

2.5.2 Serial Line Interfaces (Jl and J2)
Each serial line unit (SLU) is compatible with· EIA RS-232C and EIA RS-423 serial type interfaces.
SLU 1 interfaces through J 1, and SLU2 interfaces through J2. When a 20 rnA current loop device is
needed, the DLVll·KA option must be used. The option has an EIA cable{BC21A-03) that connects the
converter box to the module. The box has an 8·pin Mate·N·Lok™ connector that mates with the standard
20 rnA cable. The option does not support the reader run strobe and the It 0 baud rate and therefore, the
LA·33 or similar devices cannot be used.
The user installs a slew rate resistor determined by the operating baud rate defined in Table 2-14. The slew
rate resistor is identified as R6 and its location on the module is shown in Figure 1-1.
The SLU connectors showing the signals assigned to the connector pins are iHustrated in Figure 2-9. The
user provides the interconnecting cables. The following list describes some standard Digital cables and also
provides some information to help the user design cables.
Digital cables for the SOC-lI/21 PLUS:
5-foot ElA RS·232C null modem cable to directly interface with the EIA RS·232C
terminal (2 X 5 pin AMP female to RS-232C female; see Figure 2-W).
BC21B-05

5-foot EIA RS-232C modem cable to interface with moderns and acoustic couplers
(2 X 5 pin AMP female to RS-232C male~ see Figure 2-11).

BC20M-50

50-foot ElA RS-422 or RS-423 cable for high throughput transmission (l9.2K baud)
between two SBC-l 1/21 PLUS computers (2 X 5 pin AMP female to 2 X 5 pin AMP
female),

When designing a cable for the SOC-lI/2} PLUS, the user should consider the following points:
I.

The receivers on the SSC-I 1/21 PLUS have differential inputs. Therefore, when designing an
RS-232C or RS-423 cable, RECEIVE DATA- (pin 7 on the 2 X 5 pin AMP connector) must
be tied to signal ground (pins 2, 5, or 9) in order to maintain correct EtA levels. RS-422 uses
both RECEIVE DATA+ and RECEIVE DATA-.

To directly connect to a local EtA RS-232C terminal, it is necessary to use a null modern. To
design the null modem into the cable, a user must switch RECEIVE DATA (pin 2) with
TRANSMITTED DATA (pin 3) on the RS-232C male connector as shown in Figure 2-10.

To mate to the 2 X 5 pin connector block, the foUowing parts are needed.
Cable receptacle

AMP PN 87133-5
DEC PN 12-14268-02

Locking clip contacts

AMP PN 87124-1
DEC PN 12-14267-00

Key pin (pin 6)

AMP PN 87179-1
DEC PN 12-15418-00

Mate-N-Lok'" is a trademark of AMP, Inc.

2-25

,m HI" f

Table 1~14 EIA Slew Rate Resistor Values

Baud Rate

Resistor R6 (ohms)

38,400
19,200
9,600
4,800
2,400
1,200
600

22 kO*
51 kO
120 kO**
200kO
430 kG
820 kG
l'MO
1 MO

300

"'Factory installed value.
**Maximum baud rate for SLU I.

SLU
CONNECTOR

LOOPf:1ACK

BAUD RATE
CLOCK OUTPUT
0.6 X BAUDI

TEST CONNECTOR

JUMPER WIRES

TRANSMIT DATA +

INDEXING KEY
RECEIVE DATA +
RECEIVE DATA -

+12 VDC FUSED

4
5
9

VIEW INTO THE CONNECTOR 'FROM THE MODULE EDGE

c:;
v

• ..

0
0
2
PC BOARD

INDEX (NO PIN)

Figure 2·9

lO-Pin Serial Line Unit Connector

SSC-11/21

EIA RS'232C
3

I-~

,-,

DATA-~7

I
I
I

I
I
t

GRD 9

XMTDATA+)~----------~I~I--------~I~I--------~~<RCVDATA

Rev

I :I

II II

RCV DATA + )8

2(XMT DATA

I
I
I

:I :I

I I

!
I I

I I

GRO>~~------~I-+I------~I~I--------~7~<GRD
i;
•
~
1(

SHIELD

IMPORTANT:
ATTACH TO CHASSIS

AT ENTRY POINT

Figure 2-10

BC20N-05 Null Modem Cable .

EIARS-232C

SSC-Hlll

r--

( 5 ~- "'"I CLEAR TOSEND (CB)
I

GRO) 9 ...
,

Rev DATA) 7 ...
,

+12VDC

75n,/2W

~10 "".

...

Rev DATA) a ,

J REQUEST TO SEND (CA)

" 6~-.,I DATA seT READY {CC~
"'"
I
,.".~-...IDATA TERMINAL READY (COl
~

...
...
GRD)2 ,

4 ~..,.

a(RECEIVEO DATA tBBI

,'" 2 (TRANSMItTED DATA (BA}

XMITDATA+)3 ".

<SIGNA" GROUND (ASI
<PROTECTIVE GROUND CAAI
'" MODEM
i
.".

•

CABLE
'-CONNECTOR

figure 2-11

BC21.8-;OS Modem Cable

2.6 VERIFVING OPERATION
The S8C> 11 /21 PLUS single-board computer can be field tested to verify its functional operation. The
Macro-ODT option and the loopback connectors support the testing of the module.
2.6.1 Macro-ODT Option
The Macro*OOT option (part number KXT II ~A5) has two 24-pin, 2K X 8 PROM chips that contain the
Macro--OOT code and module diagnostic programs. The Macro--ODT code is used to create communication between tbe module and the user via console commands. The use of OOT commands isdetaited in
Chapter 4. The module diagnostic programs verify that the parallelljO and serial line unit interfaces will
function with commands from the microprocessor.
2.6.2 Loopback Connectors
The loopback connectors can be made by the user for the module diagnostic tests. The 30-pin connector
with the loopback jumper wires installed as shown in Figure 2-8, is used with the parallel I/O connector 13,
The serial line unit connector with the loopback jumper wires installed (shown in Figure 2-9) is used with
the SLU2 connector J2.
2.6.3 Verification Procedure
The module must be restored to the standard factory configuration for the test to be valid, however, the
start address must be 172000 not 10000. The module can be verified using the following procedure:
I.

Set the start address to 172000 as shown in Table 2-4.

Insert the high byte ODT ROM into socket set A, high byte socket XE31. Make sure pin I is
inserted into socket hole 3.

Insert the low byte OOT ROM into socket set A, low byte socket XE38. Make sure pin 1 is
inserted into socket hole 3.

Insert the 30-pin ioopback connector (see Paragraph 2.6.2) into the module parallel I/O
connector 13,

Insert the to-pin loopback connector (see Paragraph 2.6.2) into the SLU2 connector J2.

Install the module into the LSI-! 1 backplane with the power turned off. An external power
supply may be used to provide +5 Vdc to finger pins BVI. BA2, and AA2. +12 Vdc to finger
pin AD2, and ground to finger pins BJI, AJI, ATt, AC2~ BC2, AMI, and BMI.

Connect an external terminal (printer or video). The terminal must be capable of generating a 7bit ASCII code with odd parity or 8-bit ASCII code with no parity, and baud rates of 300, 600,
1,200,2,400,4,800, or 9,600. The terminal is connected to SLUt connector Jl using a Digital
BC20N-05 cable or equivalent. Turn the terminal on and on-line.

Turn on the backplane power or enable the +5 Vdc and +12 Vdc sources. Monitor the module
LED; it should light and then return to the normal off state. If the LED stays lit, there is a fault
in the SLUl circuits or the on-board RAM memory.

After the backplane power is turned on, press the RETURN key (carriage return) on the
terminal to have the module synchronize its baud rate to that of the terminal. The module
responds with the prompt character '@',

2-28

10.

To start the module diagnostic programs press the 'X' key. The diagnostic test will exercise the
module including the parallel I/O and SLU2. The results of the test are printed out on the
terminal. The error results are listed in Table 2·15 and indicate what area of the module
contains a fault. The error code '000000' indicates a good module.

Table %-15 Diagnostic Fault Indicators
Printout

Loopback Test

Internal Serial·
I/O Loopback Test

00000o

Passed

000001

Failed

Passed

000010

Passed

Failed

Not performed

000011

Failed

Not performed

000100

Passed

Failed

000101

Failed

Passed

Failed

000110

Not used

000111

Not used

Parallel I/O

External Serial"'·
I/O Loopback Test

·The internal serial 1/0 Ioopback test exercises the paranel-to-serial conversion, the seriaf-to-parallel conversion, and the
baud rate. Tbis test can be performed without the Ioopback connector.

"The external serial I/O loopback test exercises the above functions as welt as the drivers, receivers, and the external signal
paths.

2-29

CHAPTER 3
OPTIONS

3.1 INTRODUcnON
The SBC-II /21 PLUS is a, complete single-board microcomputer that operates on the LSI-II bus or in a
standalone configuration. In some applications, it may be desirable to add optional modules to the SBC11/21 PLUS to extend its function beyond that provided by the module itself. Paragraphs 3.2 and 3.3 list
all options available. For more information see the documents listed in Paragraph 1.4 of this guide.
3.2 SUPPORTED OPTIONS
The following options are functionally compatible with the SBC-11/21 PLUS. Software diagnostics for
these options run on a SBC-ll/21 PLUS equipped with a mass storage device (TU58, RXOl, RX02,
RX50, RD51, RLOI, and RL02) and the Macro-ODT option. To order diagnostics contact your Digital
sales representative.
3.2.1 Hardware Options
TU58

The TUS8 is a low-cost mass memory device that is used with the SBC-l1/21 PLUS
by attaching it to one of the serial I/O lines. TUS8 offers random access to blockformatted data on pocket size cassette media. It is ideal as a small computer systems
device, as inexpensive archive mass storage, or as a software update distribution
medium. A dual drive TUSS offers 512Kb of storage space, making it one of the
'lowest cost complete mass storage subsystems available. For mounting flexibility, the
TUS8 is offered both as a component level subsystem and as a fully powered 5-1/2
inch rack-mount subsystem. The roS8 interfaces with the microprocessor over an RS423 serial line interface.

AAVII-C

The AAVII-C is a 4-channel, 12-bit digital-to-analog converter module that includes
control and interfacing circuits. It has four D/A converters. a dc-dc converter that
provides power to the analog circuits. and a precision voltage reference. Each channel
has its own holding register that can be addressed separately and provides 12 bits of
resolution. Bits 0, I, 2, and 3 of the fourth holding register are brought out to the I/O
connector so that they can be used as a 4-bit digital output register.

ADVII-C

The ADV 11-C is a 12-bit successive approximation analog-to-digital converter that
samples analog data at specified rates and stores the digital equivalent value (or
processing. The multiplexer can accommodate up to sixteen single-ended or eight
quasi-differential inputs. The converter uses a patented auto-zeroing design that measures the sampled data with respect to its own offset and therefore, cancels out its own
offset error.

Three reference signals are provided for self-testing any channel input. These signals
consist of two de levels and one bipolar triangular waveform. This output can be used
with Digital diagnostic software to produce a data base (or precise anatoa linearity
testing.
3-1

AXVII-C

The AXV l1-C functions like the ADV II-C, but also has two t 2-bit digital-to-analog
converters similar to those on the AA V ll-C module.

DEQNA

The DEQNA is a dual height module which interfaces the LSI-II bus to
ETHERNET.

DHVII

The OHVl1 option is an asynchronous multiplexer which provides eight full-duplex.
asynchronous, serial data channels on an LSI-ll or Q22 bus. The option can be used in
several applications which include data concentration, real-time processing, and cluster
controlling.

DLVII-E

The OLVll-E is an asynchronous line interface module that interconnects the LSI-ll
bus to standard serial communications lines. The module receives serial data, converts
it to paraUel data, and transfers it to the LSI-II bus. It also accepts parallel data from
the LSI-II bus, converts it to serial data, and transmits it to the peripheral device, The
module has jumper selectable or software selectable baud rates (50-19,200) and
jumper selectable data bit formats. The DLVll-E offers full modem control for
EIA/CCIIT interfaces,
The DLV 11 ~F is an asynchronous line interface module that interconnects lhe LSI·11
bus to several types of standard serial communications lines. The module receives serial
data, converts it to parallel data, and transfers it to the LSI-il bus. It also accepts
parallel data from the LSI-li bus, converts it to serial data, and transmits it to the
peripheral device. The module has jumper selectable or software selectable baud rates
(50- i 9,200) and jumper selectable data bits. The OL V Il-F supports either 20 rnA
current loop devices or EIA standard lines, but does not include modem control.

DLVll-J

The DLVII-J contains four independent asynchronous serial line channels that are
used to interface peripheral devices to the LSI~ 11 bus. Each channel transmits and
receives data from the peripheral device over EIA data leads (lines that do not use a
control line). The module can be used with 20 mA current loop devices if a DLVll·KA
adapter is used. The OLVI I-J has jumper selectable baud rates from 150 to 39.4K
baud.

DMVll

The multipoint DDCMP~OMVll intelligent communications synchronous line controller is an interface device which provides efficient high-speed synchronous communications for distributed networks. The DMVl1 uses LSI-II CPUs as control or tributary
stations, while requiring a minimum of main CPU resources. The following provides
detailed information on the installation and operation of the DMVII.

DPVII-DA

The DPVll·OA is a single line, program~controlled. double-buffered communication
device designed to interface the LSI-II bus to a serial synchronous line. This selfcontained unit can use a wide range of protocols including bit-oriented protocols
(SOLe, HOLC, ADCCP, and X.25) and byte-oriented protocols (DDCMP and
BISYNC).
The module is used for high-speed synchronous lines such as remote batch, remote data
coUection, remote concentration, and communication networking. The module, compatible with EIA RS-232 and CCITI V.28 interface standards, is also compatible with
EIA RS-423 and 422 electrical standards and thus, provides low-cost, local communications capability.

DRVll

The DRVll is a parallel interface module used to interconnect the LSI-ll bus with
general-purpose parallel line TTL or OTL devices. It allows program-controlled data

transfers at rates up to 40K words per second and uses LSI-It bus interface and control
logic to generate interrupts and process vector handling. The data is handled by sixteen
diode clamped input lines and sixteen latched output lines. There are two 40-pin
connectors on the module for user interface applications.
DRVII-B

The DRVII-B is an interface module that uses direct memory access (DMA) to
transfer data directly between the system memory and an I/O device. The interface is
programmed by the processor to move variable length blocks of 8-bit or 16-bit data
words to or from specified locations in the system memory. Once programmed, no
processor interrupts are required. The module can transfer up to 250K 16-bit words per
second in the single cycle mode and up to 500K 16-bit words per second in the burst
mode. The module also allows read-modify-restore operations.
The DRVll-J provides sixty-four input/outut data lines on a double-height module for
the LSI-Ii bus. The DRVll-J also includes an advanced interrupt structure with bit
interruptabiHty up to sixteen lines, programmable interrupt vectors, and program
selection of fixed or rotating interrupt priority within the DRVll·J. The DRVll~J bit
interrupts for real~time response make it especiaUy useful for sensor I/O applications.
It can also be used as a general-purpose interface to special devices. and two DRVll·Js
can be connected back-to-back as a link between two LSI-II buses.

DUVIl·DA

The DUVII-DA synchronous line interface module creates a data communication line
between the LSI-Il bus and a Bell 201 synchronous modem or equivalent. The module
is programmable to sync characters, character length (up to 8 bits), and parity selection. The receiver logic accepts serial data for the LSI-ll bus. The transmitter logic
converts the parallel LSI-II bus data into serial data· for the transmission line. The
interface logic converts the TTL logic levels to the EIA voltage levels needed by the
Bell 201 modems and also controls the modem for half-duplex or full-duplex operation.

DZVII-B

The DZV i I-B is an asynchronous multiplexer interface module that interconnects the
LSI-II bus with up to four asynchronous serial data communications channels. The
module provides EIA interface voltage levels and data set control to permit dial-up
(auto answer) options with full-duplex modems sucbas Bell models 103, 113, 212, or
equivalent. The DZVII-B does not support haJf-duplex operations or the secondary
transmit and receive operations that are available with some modems such as Bell 202.
The module has applications in data storage and collection systems where front-end
systems interface to a host computer and for use in a cluster controller for terminal
applications.

IBVll-A

The IBV Il-A is an interface module that interconnects the LSI-it bus with the device
bus described in IEEE standard 488 1975, Digital Interface for Programmable
Instrumentation. The IBVII-A makes a processor-controlled programmable device
system possible. The module can accommodate up to fifteen IEEE-488 devices.

KMVII

The KMVI t is a medium speed intelligent single line data communications interface
for LSI-II bus based systems.
The KXTII-CA implements tbe LSI-II bus (Q-Bus) specifications as a bus slave (it is
incapable of arbitrating the bus), and as a DMA device (can become bus master to
transfer data when the arbiter grants the bus.). In this mode it serves as an intelligent
peripheral or as an I/O processor module (lOP).
This module can also be used as a singIe-boardcomputer (SBC) in a standalone fasbion.

3-3

KWVII-C

The KWVII-C is a programmable real-time clock/counter that provides a means of
determining time intervals or counting events. It can be used to generate interrupts to
.the processor at predetermined intervals or to establish timing between input and
output events. It can also initialize the ADY l1-C analog-to-digital converter by a clock
counter overflow or by firing a Schmitt trigger. The clock counter has a resolution of
16 bits and can be driven by anyone of five crystal-controUed frequencies (100 Hz to 1
MHz), from a line frequency input. or from a Schmitt trigger fired by an external
input. The module can operate in any of four programmable modes: single interval,
repeated interval, external event timing. and external event timing from zero base.
The MCVII-D is an on-board battery backed CMOS memory that supports 22-bit
addressing. The MCVll-DA is an 8Kb module, and the MCVll-DC is a 32Kb
module. The module incorporates two nickel cadmium batteries for backup in case of a
power failure.

MRVIl~C

The MR V ll-C is a flexible, high density ROM module used with the LSI· 11 bus. The
module contains sixteen 24-pin sockets which accept many of the user supplied ROM
chips. The module accepts masked ROMs, fusible link PROMs, and ultraviolet erasable PROMs. It accepts several densities of ROM chips up to and including 4K X 8
chips. Using these high density chips gives the module a total capacity of 64Kb. The
contents of the module can be accessed directly or window·mapped. Direct access
provides total random access to all ROM locations on the module. Window-mapping
provides two 2Kb windows of memory address space to access 2Kb segments of the
ROM array. The segments that are seen through each window can be changed by
program control.

MRVII-D

The MR V I I-D is a dual height module containing sixteen 28 pin sockets. It performs
with fun capability on a 16-, 18- or 22-bit bus. Although this module is basically a
ROM board with bootstrap capability, it supports many combinations of 24 and 28 pin
ROM, PROM, EPROM, EEPROM, and SRAM devices. The MRVII-D offers page
mode addressing, as well as direct mode addressing.

MSV1I·D

The MSVll-D module has either 8K, 16K, or 32K X 16 bits of MOS memory. The
module has an on-board memory refresh and performs the necessary LSI·lI bus
cycles. The memory addressing is selected by the user by configuring switch positions.
The module can use a battery backup system to maintain data when primary power is
lost.

MXVII-A

The MXV 11·A is a dual*height multifunction option module for the I.SI-l1 bus. It
contains a read/write memory, provisions for read only memory, two asynchronous
serial line interfaces. and a 60 Hz clock signal derived from a crystal oscillator.
Read/write memory is provided with either 8Kb or 32Kb (4K or 16K words). Two 24pin sockets are provided for +5 V read only memories. IK X 8, 2K X 8, or 4K X 8
ROMs may be used. The sockets may also be used for 256 words of bootstrap code.
The two asynchronous serial lines transmit and receive EIA-423 signal levels from 150
baud to 38.4K baud. Twenty rnA active or passive current loop operation at 110 baud
maybe used with the DL V ll-KA EIA to 20 rnA converter option. The serial lines will
not support the reader run function of the DLV ll-KA option. The serial lines provide
error indicator bits for overrun error, frame error, and parity error, but do not have
modem controls. Serial line 1 may be configured to respond to a BREAK signal. The
serial lines have signal level interrupt logic. Serial line 1 and serial line 0 may be used
with any of many standard types of serial communication devices. The 60 Hz clock
signal can be selected by a wirewrap jumper to provide real·time dock interrupts on
the bus.
3-4

RLOI/RL02

The RLO I and t,he RL02 are random-access. mass storage subsystems that store data
in fixed-length blocks on a preformatted disk cartridge. Each RLOI can store 5.24
million bytes. and each RL02 can store 1O.4S million bytes.
The RLV12 disk controller interfaces RL02and RLOI disk drives to any quad-or hexsize backplane that uses 16-, IS-, or 22-bit LSI-II bus. One RL V 12 controls up to four
disk drives. The RLVI2 consists of one quad-size module, a BCSOM cable, a drive
terminator. and drive identification hardware.
.
The RLV 12 transfers data to and from the LSI-II bus using direct memory access
(DMA) transactions. This allows data transfers to occur without processor intervention.

RD51/RX50

The RD51 is a IOMbytes hard disk mass storage device and the RXSO is an SOOKb
floppy disk mass storage device. Both are interfaced to the LSI-II bus by means of an
RQDXI controller. The RQDXI controller (M8639) ~ a quad-height module that is
mounted in the last occupied slot in the backplane. It is a high-functionality disk
controller that interfaces the RD5I fixed disk drive and the RX50 diskette drive to the
extended LSI-II bus. The controller is a direct memory access (DMA) type of interface and conforms to mass storage control protocol (MSCP). A cable (part number
BC06L-IC) connects the RQDXI controller module to the.signal distribution printed
circuit board, where the signals are distributed to the individual drives.

RXVl1

The RXVII option has an interface module, cable assembly, and either a single or dual
drive RXOI floppy disk. This option is a random access, mass storage device that stores
data in fixed-length blocks on a preformatted flexible diskette. Each diskette can store.
recover, and retrieve up to 2S6K, 8-bit bytes of data. The RXVII system is rack
mountable in the standard 48.3 cm (19 in) cabinet.

RXV21

The RXV21 floppy diSk option is a random access mass memory device that stores
data in fixed-length blocks on a preformatted, flexible diskette. Each diskette can store
and recover up to 5I2K 8-bit bytes of data. The RXV2I system is rack mountable and
consists of an interface module. an interface cable, and either a single or dual RX02
floppy disk drive. The interface module conyerts the RX02 I/O bus to the LSI-II bus
structure. It controls the RX02 interrupts to the processor, decodes device addresses
for register selection, and handles the data exchange between the RX02 and the
processor via DMA transfers. Power for the interface module is provided by the LSI-II
bus.

TSV05

The TSV05 is a 1600 BPI magnetic tape drive.

3.1.1 Software Options
The SBC-Il/21 PLUS is functionally compatable with the following software options.
3.1.1.1 RT-ll Operating System - The RT-II (Real Time-II) computer system is a single-user computer/operating system that serves the programming needs of both the beginning and the advanced programmer. RT-Il supports a number of programming languages, including industry standard FORTRAN,
BASIC, and for more advanced users the PDP-II assembly language, MACRO-II. RT-II also provides a
comprehensive set of operating commands for controlling system operations. Both the single job (8.1) and
the foreground background (FB) monitors are supported by the SBC-II/2I PLUS.

3-5

3.2.2.2 MicroPower/Pascal Operating System - MicroPower/Pascal is a software product for develop-

ing dedicated, real-time applications that run on Digital's 16-bit microcomputers. MicroPower/Pascal
applications are created in a host development/target runtime environment and are ROMmable. The host
is either a PDP-II running RT-Il or RSX-IIM. or a VAX running VMS. The target is any PDP/LSI-II
Q-Bus based system. MicroPower/Pasca) consists of an extended PASCAL compiler, a modular,
standalone runtime system (kernel. language features, device handlers, and system processes), build and
load utilities, and a symbolic debugger.

3.3 UNSUPPORTED OPTIONS
A list of LSI-II bus options that are not guaranteed to be functionally compatible with the SBC-ll/21
PLUS and are unsupported are listed below. Their diagnostics are not available.
AAVII-A
ADVII-A
BDVII-AA/BA
DAII-MS/QQ/QU
DAVll-A/D
DRLll-SN
DUVII-E/F
DUV25
OWll
DWVII-A

KXTII-AA
LAVll
LPVll
MRVII-AA/BA/VA
MSVII-E/P
MSVII-L
MXVII-BF
NCVII-A
REVll
RKVll
RLVll
TEVll
TRVll
TSVll
VMVll-A
VK170
VSVll
VTVOI-A

FEPTC-BA
FPFll
IPVI2
KDll-F

KDll-HA
KDFII-AD/AC/DB
KOFll~BC/p

KDJII-A
KPVII-A

VTV30-H

3-6

CHAPTER 4
MACRO-ODT

4.1

INTRODUCTION

The Macro~ODT is the KXTII-A5 option available to users of the SBC~11/21 PLUS single-board
computer. The option has a complete listing of the firmware and two 24-pin, 2K X 8 PROM chips that
contain the Macro-ODT firmware. The chips are installed on the module using the PROM sockets.
Macro-ODT allows the user to:
1.

Examine and deposit data in memory or general registers.

Examine or change the processor status word (PSW).

Start the execution of the program.

Restart the execution of a halted program.

Bootstrap programs from a mass storage device (TUSS cassette, RXOI/RX02 floppy disk,
RD51 disk, RX50 floppy disk, or RLO l/RL02 disk).

Run a diagnostic test for on-board devices.

4.2. INSTALLATION AND CONFIGURATION
The inst~Uation and configuration of the KXTl1-AS option is described in detail in Chapter 2 of this
User~s Guide, and the user should refer to it for installation and start-up instructions.
4.3 ENTRY CONDITIONS
Macro-ODT is entered:
I.

On power-up.

Via the BREAK key on the console terminal.

On execution of a HALT instruction.

On assertion of the BHALT L signal on the LSI-il bus.

When accessing nonexistent memory (i.e., a bus time·out).

4.3.1 Macro--ODT Input Sequence
When entering Macro-ODT, the RBUF register is read using a DATI, and the character present in the
buffer is ignored. This is done so that erroneous characters or user program characters are not interpreted
by Macro-ODT as commands.

The input sequence for Macro-ODT follows.
I.

Read and ignore character in RBVF.

Output a <CR> <LF> to the terminal.

Output contents of PC (program counter R 7) in six digits to terminal if ODT is entered via a
BREAK, BHALT, or HALT instruction or trying to fetch an instruction from nonexistent
memory. Output a '1' to the terminal if ODT is entered via a bus time-out.

Output a <CR> <LF> to the terminal.

Output the prompt character (@) to the terminal.

Enter a wait loop for terminal input. The done flag. bit 7 in RCSR, is tested using a DATI. If it
is uro, the test continues.

If RCSR bit 7 is a one. the low byte of RBVF is read using a DATI.

Test XCSR bit 7 (done flag) using a DATI and, if it is a uro, continue testing.

If XCSR bit 7 is a one, write character to low byte of XBUF using a DATI followed by a
DATO (high byte is ~ed by interface).

4." MACRO-ODT COMMANDS
Table 4-1 lists the Macro-ODT commands. The commands are a subset of ODT·ll and use the same
command character. The Macro-ODT internal states are listed in Table 4-2. Only specific characters are
recognized as valid inputs for each state; other inputs produce a '?' response.

The parity bit, bit 7, on all input characters is ignored by Macro-ODT, and if the input character is echoed,
the state of the parity is copied to the output buffer (XBUF). Output characters internally generated by
ODT (e.g., <CR» have the parity bit equal to zero. All input characters are echoed. Only uppercase
command characters are recognized.

NOTE
The use of ODT co........ creates a dialogue
lJetween the tIIeI' and tile ....0C0IIIpIdeI'. All die
chuacten typed the 1ISeI' are . . . . .ed _die
system response is not tIIIderIiaN ... die en.....
• ,ea in dais User's GuYe.

".4.1 / (ASCII 057) SIasII
The 'f command is used to open an on-board module address, LSI· 11 bus address, proeessor rcJister. or
processor status word and must normaHy be preceded by other characters that specify a location. In
response to • Macro-ODT prints the contents of the location (i.e., six cbaracters) aRd a space (ASCII
40). After printing is complete, Macro-ODT waits for either new data for that location or a valid close
command (<CR> or <LF> if memory is accessed). The space character is issued SO that the location's
contAmts and possible new contents entered by the user arc legible on the terminal.

4-2

Example:

@OOIOOOjI2.S25<SPACE>

where:
@

Macro-ODT prompt character.

001000

...

octal location in the LSI-II bus address space wanted by the user
(leading zeros are not required).

command to open and print contents of location.

012525

contents of oc:talloc:ation 1000.

<SPACE>

.. space character generated by Macro-ODT.

If the user issues a
immediately after a prompt character. the system prints? <CR> <LF> because a
location is not open.

Table 4-1

Macro-ODT ColIIID8IICIs

ComlDalld

Symbol

Function

Stash

Prints the contents of a specirled location.

Carriage return

<CR>

Closes an open location.

Line feed

<LF>

Closes an open location and opens tbe next location. This
command cannot be used with the lenetal registers.

Internal register
designator

Opens a specific processor register. (x - 0-7,5)

Pnx:essor status
word cfcsipator

Opens the PSW; must follow R command.

Starts the execution of a program.

Proceed

Resumes the execution of a program.

Boot from device

Loads and runs programs from floppy diskettes or ruS8
cassettes.

Execute diagnostics

Runs SBC-II/21 PLUS module verification diapostics.

Table 4-2 Macro-ODT States .... Valid Input a.anden

Ex• .,I:e ef

.,..t

State

T......
0uqMat

VaIId •

'1'

'~1

X
0

0-7

@1000/
123456

0-7

@Rl/123456

0-7

@1000

0-7

.Rlor.as

(jl0001
123456 1000

0-7

(jRII

0-7

1234561000

<CR>

9·

(jOY

0
1
<CR>

10·

@OX

11·

.00

0
1
<CR>

*00 not enter zero or one followed by <CR>.

0
I
<CR>

4.4.2 <CR> (ASCll IS) Carriage Return
The <CR> com.mand is used to close an open location. If a location's contents are to be changed. tbe user:
sboukf precede the <CR> with the new data. If no change is needed, <CR> doses the location without
modifying its contents.
Example:

@Ri/004321<SPACE> <CR> <CR> <IF>
@-

Processor register RJ was opened, and no cbange was needed so the user issued <CR>. In response to tbe
<CR>. Macro-ODT printed <CR> <IF>@.
Example:

@Rl/004321<SPACE> 1234 <CR> <CR> <IF>
@

In this example. the user wanted to change R J. The new data, 1234, was entered before issuing the <CR>.
Macro-ODT deposited the new data into the open location and then printed <CR> <IF> @. Macro-ODT
echoes the <CR> entered by the user before it prints <CR> <LF> @'
Example:

@IOOOL012525<SPACE> 1234 <CR> <CR> <LF>
@

where:
first line = new data, 1234, entered into location 1000. The location is closed with <CR>.
4.4.3 <LF> (ASCII 12) Line Feed
The <LF> command is used to close an open location and then open the next contiguous location. LSI-It
bus addresses are incremented by two. If a processor register is open and an <LF> command is issued, the
register is closed and any data that was typed in before the <LF> will not enter the register. ODT prints
the error message <CR> ? <CR> <LF>. If the open location's contents are to be changed, the new data
should precede the <LF>. If no data is entered, the location is closed without being modified.
Example:

@1000}123456<SPACE> <LF> <CR> <LF>
@IOO2 054321<SPACE>

In this example, the user entered <LF> with no data preceding it. In response, Macro~ODT closed location
1000 and then opened location 1002.
4.4.4 R (ASCII 122) Internal Register Designator
When followed by a register number, 0 to 7, or PSW designator, 'S" the R designator will open that
specific processor register.
Example:

@ROj05432} <SPACE>

or
@R7jOOO123<SPACE> 456 <CR> <CR> <LF>
@

If more than one character is typed (numeral or 'S') after the 'R', Macro-ODT uses aU the characters as
.
the register designator.
Exampte:

@ROOOO7/000123<SPACE> <CR> <CR> <LF>
@

4.4.5 S (ASCII 113) Processor Status Word (PSW)
The S ~gnator opens the PSW and 'must be used after the user bas entered the It resister dc&ianator.

Example;

@RS/lOO377<SPACE> 0 <CR.> <CR> <LF>
@as-/OOOOl0<SPACE>

Tbe T-bit filter prevents the user from setting tbe T-bit via Macro-ODT. The T-bit can be cleared by any
write to the PSW. Wben the filter is disabled, the T-bit can be set by loading the PSW to set bit 4 to a one.
TIIis is normally not considered desirable. The T-bit filter can be disabled by setting bit 1S of location
167772 to a one.
The PRIORITY 7 filter prevents the user from ietting a priority level·or 7 via Macro-ODT. Operation at
priority level 7 masks out (disables) the BREAK interrupt and makes it impossible to return to MacroDDT. This operation is normally unacceptable. If required, the PRIORITY 1 filter can be disabled by
setting bit 7 of location 167772 to a one. With the filter disabled, a priority levd of 7 is selected by writing
340 into the PSW.
.
4.4.6 G (ASCII 107) Go
The G command is used to start program execution at a location entered immediately before the 'G' in the
command string.

Example:
The Macro-ODT sequence for a G command, after echoing the command character, ~{oI1ows.
L
2.

Load R 7 (PC) \Vitbthe entered data. (In tbe previouS example, R7 is equal to 200 and that 'is
where program execution starts.)
' . '"
,
•
The PSW is cleared' to' zero.

The LSI-II bus is initialized by the processor's asserting BINIT L fQl' 17 p$ nlinimum and then
negates BINIT L
'

The user program starts execution at the location specified.

The user is warned that the G command clears the PSW to permit clock interruptS to be acknowledged.
failure to load the address of tbe clock service routine ~to the clock vector address (10() may cause;
unpredictable results.
. "
,. "
"
4.4.7 P (ASCII 120) Proceed
The P command is used to restart execution of a program. No programmer visible machine, state is
changed using tbis command.

Example:

Program execution restarts at the address pointed to by It7. After 'P' is echoed. Macro-ODT exits, and the
program restarts execution.

4.4.1 'DD, DX, DY ~
The D command is used to bootstrap a standalone prosram or XXDP+ diaanostics from an ItXO I or
RX02 floppy diskette or a TU 58 tape cassette. The next character after the ,D, axnmand determines the
type of device being booted. A numerical character, either zero or one, is used to specify. se1ectccl drive or
unit or the device being booted. If <CR> is typed instead of zero or one, unit 0 is assumed.

Examples:

Boot unit 0 of TU58 device:
@DD<CR>
Boot unit 1 of RXO 1 device:

Boot unit 0 of RX02 device:

Boot unit 0 of RD51 or RX50:

Boot unit 0 of RL:
@DLO

NOTE
Do not type both unit number and <CR>.
To boot a diskette drive, ODT expects the RXVll or RXV21 controller eSR address to be configured for
177170. To boot the TU58, it must be connected to SLU2 and its' baud rate set for 38,400.
Any error detected during the execution of a boot command will cause a halt at one of many addresses in.
the boot section of the ROM, with the PC contents printed on the console. The actual addresses and the
specific errors they represent are given in the listing provided with the option.
Some errors, however, are not reported. If a TU58 is not connected to SLU2 or if baud rates are
incompatible. or if the RL is not loaded. no error indication is given after using the applicable boot
command, and the program waits forever. This is also true when booting from floppy diskettes wben the
drive power is off. In either condition, the user can use <BREAK> to return to ODT prompt level (<fY).
The D command performs the following operations.
1.

If there is no RAM memory at address 0, the D command will cause a balt.

The command initializes the LSI-II bus by asserting BINIT L for 17 p.S minimum.

It reads block 0 (the first 512 bytes) from the selected mass storage device into memory
locations 000-777.

It reads location 0 and if it is 240, it loads R 1 register witb the CSR address ·of tbe" booted
device, loads RO register with the selected unit or drive number, and jumps to location O.

If the device is an RXOI/RX02 or a TUS8 and if the content of location 0 is 260, the mass
storage device contains a standalone program. Macro--ODT interprets the contents of locations
2, 4, and 6 as a RADIX~50 encoded six character file name. Macf(}-ODT assumes that the mass
storage device is an RT-II file structured volume and searches the directory of the volume for
the file name provided by locations 2, 4, and 6. When the fife is found, the complete file is
loaded into contiguous memory starting at location O. The RO register is loaded with the
number of the unit or drive, and the R 1 register is loaded with the CSR address of the booted
device. The stack pointer (SP) is loaded with the contents of location 42 and the program
counter (PC) is loaded with the contents of location 40. The program starts execution.

If the content of location 0 is not 240 or 260, the device does not contain a valid boot block. The
boot command is aborted, and the SBC-II 121 PLUS is initialized as if a power-up occurred.

4.4.9 X (ASCII 130) Diagnostics
After typing the letter 'X'. there is a three~second delay before an octal number is displayed. This
command is described in detail in Chapter 2.
4.5 INITIALIZATION
When it is necessary to reinitialize the system without removing power, the user enters 1730000 from the
console in response to the <@' prompt. After a delay, the user types a carriage return to resynchronize the
terminal as shown in the following example.
Example:

@17300OG

After a delay of at least one second, the user types <CR> to resynchronize.
4.6 WARNINGS AND PROGRAMMING HINTS
The foUowing warnings and programming hints are provided to help the user operate Macro-ODT.

4.6.1

Error Decoding
When an '@' appears unexpectedly, it is good practice for the user to examine the word at 167774. This is
an error word that indicates the cause of entry to ODT. A HALT instruction, BREAK, or trying to fetch
from nGnexistent memory will appear as 100000. Other attempted bus transactions to nonexistent memory
wilt appear as 000200, or. if accessed by the stack pointer R6, as 000201.
4.6.2 ODT Stack Warning
While performing its various functions, Macro-ODT requires two words of user stack. It will push and pop
internal information there. Therefore, it is necessary that the user always provide two more words than
those necessary fOf'the correct execution of the application program. If desirable, these two words can be
given back when the program is completely debugged and operating within its own ROMs without ODT.
For correct program operation. R6 should always contain a valid even RAM memory address. Failure to
observe this rule will cause unpredictable results.

4.6.3 Addresses to Avoid
Because the firmware uses the topof the SOC-ll/21 PLUS on-board RAM as its scratchpad. the user
should not write to any address above 167642 unless specifically defined in this User's Guide.
The vector at 140 controls the BREAK interrupt. Changing locations 140 and 142 could result in the
inability to suspend program execution.

4-8

4.6.4 CPU Priority
When the PSW is set to 340, the BREAK key will have no effect and will not invoke Macro-ODT.
Running at a level 6 priority (PSW set to 300) is acceptable for most programming needs. This will disable
aU interrupts except for BREAK.

4.6.5 Terminal Related Problems
Macro-ODT echoes every character typed in response to the '@' prompt. Some intelligent terminals also
respond to control characters as commands. The results may include loss of communication.

4.6.6 Spurious Halts
When the last word of an instruction is all zeros and causes a bus time-o'ut, Macro-ODT will interpret it as
a HALT instruction and print the contents of PC on the terminal before issuing the '@' prompt.

4.6.7 Serial I/O Protocol
The Macro-ODT operates the serial line interface in full-duplex mode, and each character is echoed by the
microprocessor to the terminal. Programmed I/O methods are used instead of interrupts, When the
Macro-ODT firmware is busy printing a multicharacter message using the transmit side of the interface,
the firmware is not monitoring the receive side for incoming characters. Any characters coming in at this
time are lost. The interface may set the overrun error bit, but the Macro-ODT does not check this bit, and
those characters are not recognized. All peripherals communicating with the Macro-ODT through this
interface must observe this protocol.

4.6.8 Interrupt Vector Initialization
On power-up, Macro-ODT initializes the LTC interrupt vector (REV NT at 100) and the BREAK
interrupt vector (BKRQ at 140). Other vectors are not initialized and may contain erroneous data.
4.6.9 Boot Rom Address Scheme
The code for the SBC-ll/21 PLUS resides in locations 164000-173776 (octal) when maps 0 or 2 are
selected. The code for addresses 164000-167776 is physically coded into the UPPER half of the 2K X 8
PROMs used for the KXTII-A5s', and the code for addresses 170000-173776 is coded into the LOWER
half of the 2K X 8 PROMs.

4-9

CHAPTER 5
SYSTEM ARCHITECTURE

5.1

INTRODUCfION

This chapter describes the architecture of the microprocessor, memory organization, and power-up
method. The microprocessor architecture describes the registel!t hardware stactc, interrupts, and direct
memory access {DMA} mechanis'm. The memory organization describes byte or word addressing and
memory mapping. The power-up procedure and initialization are also described.

5.2 MICROPROCESSOR ARCHITECTURE
The SOC-II /21 PLUS microprocessor executes a subset of the PDP-II instruction set. It has eight highspeed general-purpose registers that are used as accumulators, address pointers, index registers, and for
other special functions. The microprocessor executes single and double opera}J.d instructions using either
16-bit words or 8-bit bytes. The direct memory access (DMA) function transfers data directly from the
LSI-II bus to the on-board I/O devices and memory while the program continues to run.

5.2.1

Registers

As shown in Figure 5-1, the microprocessor contains a number of internal registers that are used for many
purposes. The registers are divided into two groups:
1.
2.

General
Status

5.2.1.1 General Registers - The microprocessor contains eight 16-bit general-purpose registers that can
perform many functions. These registers operate as accumulators, index registers, autoincrement registers.
autodecrement registers, or as stack pointers for temporary storage of data. Arithmetic operations can be
performed from one general register to another, from one memory location or device register to another,
or between memory locations or a device register and a general register.
Registers R6 and R7 are dedicated. R6 is the stack pointer (SP) and contains the location (address) of the
last entry in the stack. Register R 7 is the processor program counter (PC) and contains the address of the
next instruction to be executed. It is normally used for addressing purposes only and not as an
accumulator.

5.2.1.2 Status Register - The PSW contains information on the current processor status.

nus

information includes the current processor priority, the condition codes describing the arithmetic or logic results of
the last instruction, and an indicator for detecting the execution of an instruction to be trapped during
program debugging. Figure 5-1 shows the PSW format; Table 5-1 lists status word bit descriptions.
Certain instructions allow programmed control of condition code bits and loading and storing (moving) the
processor status. Not aU instructions affect the condition codes in an obvious way. See Chapter 7 for
details on specific instructions.

5·1

PROCESSOR ST ATUS
15

RO
Rl

R2
GENERAL REGISTERS
R3

STACK POINTER

FlS

PROGRAM COUNTER

I
MA-1829

Figure 5-1

Registers and Processor Status Word

5.2.2 Hardware Stack
The hardware stack is part of the basic design architecture of the SOC-Ii /21 PLUS. It is an area of
memory used by the programmer or by the operating system for temporary storage and linkage. It is
controlled on a LIFO (last in/first out) basis; items are recovered in the reverse of the order they were
stored. The stack starts at the highest location reserved for it (376 octal at power-up) and expands linearly
downward to a lower address as items are added to the stack.

It is not necessary to keep track of the actual locations into which data is being stacked. This is done
automatically through the use of the stack pointer. Register R6 always contains the memory address
where the last item is stored in the stack. Instructions associated with subroutine linkage and interrupt
service automatically use R6as the hardware stack pointer. For this reason, R6 is often referred to as the
system SP. The hardware stack is organized in full word units only.

5.2.3 Interrupts
Interrupts are requests, made by peripheral devices, that cause the processor to temporarily suspend its
present program execution to service the requesting device. A device can interrupt the processor only when
its priority is higher than the processor priority indicated by PSW<7:5>, as shown in Table 5-2.
SOC-II/21 PLUS supports a vectored interrupt structure with priority on four levels. In addition, it
supports two nonmaskable interrupts: power fail and HALT.

5-2

Table 5-1

Processor Status Word Bit Descriptions

Bits

Name

Description

15-08

N/A

These bits are not accessible to the programmer and contain no
valid information.

07-05

Priority

These bits define the current priority level of the microprocessor program, and only interrupts with a higher priority are
recognized by the microprocessor. Table 5-2 describes the
microprocessor interrupt levels as functions of bits 5-7.

Trace

When set, this bit allows the microprocessor to trap to locations 14 and 16 after an instruction is executed. It can only be
set by executing an RTI or RTT instruction with the correct
PSW on the stack. The trace bit allows programs to be single
stepped and is useful for debugging.

Condition code N

This bit is set when an instruction causes the result to be
negative.

Condition code Z

This bit is set when an instruction causes the result to be zero.

Condition code V

This bit is set when an instruction causes an overflow
condition.

Condition code C

This bit is set when an instruction causes a carryout of the
.
most significant bit.

Table 5-2

PSW Interrupt Le\'els

Microprocessor
Priority

Interrupt Le\,e's
Acknowledged

Level 7
Level 6
Level 5
Level 4
Level 0-3

Nonmaskable interrupt
7
1,6
7,6,5
7,6,5,4

5-3

PSW Bits
6

1
1
1
t

1
1

5
1

0
X

Every interrupt except HALT is associated with an interrupt vector. The interrupt vector is a pair of
words: the next PC (address of that device's service routine) and the next PSW (priority with which the
routine must be executed). Upon interrupt, the current PC and PSW are saved on the stack, and the new
PC and PSW are loaded from the vector address.
Up to six.ty-four vectors may reside in the first 256 memory locations (octal 374 is the highest vector
location). The vector address is provided by the interrupting device (external vector address) or generated
internally by the microprocessor.
NOTE
The power faU interrupt uses interrupt vector
address 24. The HALt interrupt is not associated
with a vector. It pushes the PC and PSW on tbe
stack and immedia.teiy goes to the restart address
with PSW 340.
The SBC-II /21 PLUS has eleven interrupt sources. Nine of these are maskable; two are nonmaskable. An
interrupt request can occur at any time, but it is not acknowledged until the completion of the current
instruction. This lets the microprocessor execute a program until the interrupt occurs and then vector to
the service routine for the interrupt. After the service routine is completed, a return from interrupt
instruction (RTf) is executed. The microprocessor then pops the top two words, the original PC and PSW.
from the system stack, and the interrupted program is continued.
Table 5~3 lists the eleven interrupt sources with their priorities. For a device to be serviced, its priority level
must be higher than the current microprocessor level. When two devices with equal priority numbers
request an interrupt at the same time, the device nearest to the top of the table is serviced first.
When an interrupt is requested by several LSI-It bus devices at the same time, the device electrically
nearest to the SBC·lt /21 PLUS is serviced first.
5.3 DMA (DIRECT MEMORY ACCESS)
OMA allows the programmer to implement block transfers by specifying the direction of transfer, the
starting address in memory, the number of words, and any additional parameters that an external device
requires. SBC-ll/21 PLUS does not have an on-board DMA interface but it can support OMA transfers
for external devices via the LSI-li bus interface. A typical device using the DMA mechanism is the RX02
double-density floppy diskette. User designed devices can also be connected to the SBC-II/21 PLUS
DMA facility. See Chapter 9 for more information.

5.4 MEMORY ORGANIZATION
The SBC-li/21 PLUS memory uses on-board memory and LSI-II bus memory. The memory map
configurations and the types of on-board memory chips are described in Chapter 2. The memory maps are
illustrated in Figure 5-2. Addresses from 0 to 376 octal are reserved for vector locations, and addresses
from 60Kb to 64Kb are reserved for I/O devices.
The address space of the SBC-Il/21 PLUS module is 64Kb. A 16·bit word is two 8·bit bytes with bits 0-7
representing the low byte and bits 8-15 representing the high byte. Words are always addressed by even
numbers. The bytes are addressed by either even or odd numbers. The high bytes are stored in the odd
numbered locations, and the low bytes are stored in the even numbered locations.
5.5 POWER-UP/POWER-OOWN FACILITY
The soc· I I /21 PLUS has facilities for an automatic program start-up when power is turned on and for
orderly shutdown, without loss of data, when power is turned off or lost. This is done with a combination of
hardware features and software.

5-4

Table S-3 SBC-H/21 Interrupts
Interrupt
Source

Control
Signal

Priority
Level

Vector
AddressU'

HALT

-CTMER

Nonmaskable

Power fail

-PFAIL

Nonmaskable

LSI-Il bus
signal BHALT

BKRQ

140

LSI-li bus
signal BEVNT

REV NT

100

SLU2 REC

RDL2

120

SLU2 XMIT

XDL2

124

Parallel I/O B

PBRQST

130

Parallel I/O A

PARQST

134

SLUt REC

RDLI

SLUt XMIT

XDLI

LSI-II bus
signal BIRQ4

IRQ4

Read from
LSI-II bus

The microprocessor jumps directly to the restart address with a PSW priority level 7.
(RESTART is loaded into PC and 340 into PSW.)

"'*

All vectors defined in this table are internal vectors supplied by the microprocessor
except for the BIRQ4 interrupt which is read from the bus.

Hardware features:
•

Two signal lines in the LSI-II bus, BDCOK Hand BPOK H, are used only for powerup/power-down protocol. These signals are usually generated by the power supply.

•

One signal line in the LSI-II bus, SINIT L, that resets the system.

•

The vectoring on interrupt facility of the SBC-JI/21 PLUS.

•

Battery backup connections.

Software features:
The programmer must provide power-up and power-down routines, and store their addresses at the
jumper~selected start address for power-up, and at location 24 for the power~down routine.

For a detailed description of the power-up!power-down protocol, see Chapter 9.

5·5

MAP 0
128 BYTES

(1777761 64KIt

(NOTE 21
(NOTE 11
4KB
SOCKET A

62KB

(1640001- 58KS

LSI-l1 SUS

(1600001 56KS

MAP 2

MAP 1
64K B

64KB
(NOTE 11

62KB

62KB
5SK B

14KB

58KB

56KB

SOCK~TB

56K B

'(~O~~TiJS
(NOTE 11
4KB
SOCKET A

MAP 3
64KB
LSI-" BUS
(NOTE 1)
62KB

l4KB
SOCKETB

58KB

56KB

SKS
LOCAL RAM

(1200001 40KS

,ft

48KB

11400001 48KB

l6KS
SOCKETS

~ 32KS

16KS

(200001

SKB

LSI-11 BUS

40KB

16KS
LOCAL RAM

40K B

32K B

24KB

24K B

l6KB

32KB
SOCKET A

LSI-ll BUS

40KBI-

12B BYTES
(NOTE 3)

LOCAL RAM

SKB~-

OKB

0 KB

32KB
SOCKET A

32KB

24KB

16KB

SKBI-

48KB

l6KB
SOCKETB

8KBI-

16KB
LOCAL RAM

(UlQllQI
(NOl'E41
OKS

OKB

NOTES:
1_ THIS SECTION CONTAINS THE LOCAL IJO ADDRESSES FOR THE SLUS AND
PPI. ALL UNASSIGNED ADDRESSES ARE ASSUMED TO RESIDE ON THE LSI-11 BUS.
2. ADDRESSES 177777 - 177600 IN MAPS 0 AND 2 ARE RAM SCRATCHPAD
. LOCATIONS USED BY MACRO-ODT.
3. ADDRESSES 77777 - 77600 IN MAP 2 ARE ALLOCATED TO THE LSI-11 BUS.
4. UNDERLINED ADDRESSES ARE JUMPER SELECTABLE START ADDRESSES.
(SEE TABLE 2-41
MR·12119

Figure 5-2 Memory Maps

5-6

CHAPTER 6
PROGRAMMING INFORMATION

6.1 INTRODUCfION
The SBC-l t /21 PLUS has three on-board interfaces: one parallel I/O line and two serial I/O Jines. These
interfaces contain many programmable features that allow the user to change their operating characteristics. This chapter explains how this is done.
The SBC·II/21 PLUS also has hardware that enables the microprocessor to operate in a controlled
sequence when the power is turned on and off. This hardware requires software to make it work. The basic
principles of this programming are described in Appendix C.
6.2 ASYNCHRONOUS SERIAL LINE UNITS
The two serial line units (SLUs), shown in Figure 6-1, provide the means of transferring data between the
microprocessor and two user connectors, Jl or J2. The user interfaces support the EIA RS-232C standard
and RS-423 protocol at baud rates from 300 to 38,400.
Each SLU has four addressable registers. These four registers are listed in Table 6-1 and illustrated in
Figure 6-2; their functions are described in Table 6-2, Table 6-3, Table 6-4, and Table 6-5. The registers
can be accessed by the microprocessor or any DMA bus master. SLUI, with the correct software handling,
can be used as a system console and is capable of initiating a hardware interrupt when BREAK is detected.
The SBC-It /21 PLUS can be configured for the BREAK to cause a level 7 interrupt with an internal
vector of 140, to enable the BHALT interrupt, or to request a HALT trap to the restart address. SLU2
provides three line time clocks at 50 Hz, 60 Hz, and 800 Hz, which can be wire-jumper configured to
enable the BEVNT level 6 interrupt. See Chapter 2 for details on how to configure the SLUs.
6.2.1 Data Baud Rates
The serial line units transmit or receive data serially by bit and by character. Each character has ten bits; a
start bit, eight bits of data. and the stop bit. Split-speed operation of the receiver and transmitter for the
SLU is not supported, and the user cannot supply an external baud rate clock to theSLU. During powerup or reset, the outputs are disabled, and later, the baud rate defaults to 300.
Baud rates are programmable for 300, 600, 1,200, 2,400, 4,800, 9,600, 19,200 or 38,400 when bit 1 of the
transmitter control and status register (TCSR) is set to a one. The baud rate is then selected by
programming bits 5-3 of the TCSR.
The bits used for the baud rate selection are level sensitive and do not latch. Therefore, the software in
control of the TCSR must use bit set and bit reset type instructions after the baud rate is written into the
SLU. Each SLU provides an output at TIL levels to pin 1 of its connector (Jl or J2) at sixteen times the
baud rate selected for that SLU.
The Macro-ODT option has the autobaud feature that enables SLU I to adjust itself to the terminal's baud
rate between 300 and 9,600 baud. The autobaud feature operates only when Macro-ODT is running on the
system.

6-1

Jl0RJ2
RCSR

RECEIVER
CONTROL AND
STATUS

t
ROBA
11)

:;:)

f.---

III

RECEIVER
DATA BUFFER

~UJ

RECEIVER

()

ROATH

fI.

GND

TCSR
TRANSMITTER

CONTROL AND
t.-- STATUS

t
TOBR

to--

TRANSMITTER
DATA BUFFER

1
TRANSMITTER

XOATL

OND

Figure 6-1

3
2,4

Serial Line Unit (SLU) Interface

6-2

Table 6-1

Serial Line Unit Register Addresses

Description

Address

ADl

ADI

SLUI
RCSR
RDBR
TCSR
TDBR

Receiver control and status
Receiver data buffer
Transmitter control and status
Transmitter data buffer

177560
177562
177564
177566

0
0

0
1

SLU2
RCSR
RDBR
TCSR
TDBR

Receiver control and status
Receiver data buffer
Transmitter control and status
Transmitter data buffer

176540
176542
176544
176546

0
0

1
1

0
1

RECEIVER CONTROL AND STATUS REGISTER
14
11
13
12
09
lS
10

I I I I I:~ I I
0

l~g~EI ~ECV

SLU 1 ADDRESS 177560
SLU 2 ADDRESS 176540

I I I
0

SLU 1 ADDRESS 171562
SLU 2 ADDRESS 176642

SLU 1 ADDRESS 177564
SLU 2 ADDRESS 176544

TRANSMITTER DATA BUFFER REGISTER
10
14
12
11
1S
13
09

II I I I I
0

I I
o

TRAN~IT ~ATA B~FFER:

SLU 1 ADDRESS 177566
SlU 2 ADDRESS 176646

:
1IO".1a08

Figure 6·2

Serial Line Unit Register Bit Maps

6-3

...

Table 6-1 ReeeiYer Control &ad Status Bit Descriptions
Na.

Direction

Function

12-15

Not
used

Read
only

Reserved for future use.

Receiver
active

Read
only

This bit is set to a one by the start bit and is cleared to
a zero by the stop bit at the end of each byte. It is also
cleared to a zero on power-up.

Not

Read
only

Reserved for future use.

used

Receiver
done

Read
only

This bit is set to a one when the byte received is
transferred into the RCV data buffer. It is cleared to a
zero when the RCV data buffer is read. It is also
cleared to a zero on power-up.

Receiver
interrupt
enable

Read/
write

Not
used

Read
only

08-10

OO-OS

This bit is set to a one under program control. When
set, it allows an interrupt request to be initiated whenever the receiver done bit is set. It is cleared to a zero
by reset, power-up, or under program control. Refer to
Chapter 2 for interrupt jumper configuration.
Reserved for future use.

Table 6-3 Receiver Data Buffer Bit Descriptions

Bits

Na.

Direction

Function

Error

Read
only

The bit is set to a one when the overrun error or the
framing error bit is set. It is cleared to a zero when the
error producing condition is removed.

Overrun
error

Read
only

The bit is set to a one when the received byte is transferred into the RCV data buffer before the RCV done
bit is cleared. The overrun error indicates that the
previous byte in the RCV data buffer was not cleared
prior to receiving a new byte. The bit is updated when
a byte is transferred into the RCV data buffer and
cleared to a zero on power-up.

6-4

Table 6-3

Receiver Data Buffer Bit Descriptions (Cont)

Bits

Name

Direction

Function

Framing
error

Read
only

The bit is set to a one when the received character does
not have a valid stop bit and is transferred into the
RCV data buffer. The bit is cleared to a zero when a
character with a valid stop bit is received and is transferred into the RCV data buffer or on power-up.

Not
used

Read
only

Reserved for future use.

Received
break

R~d

only

The bit is set to a one when the received signal goes
from a mark to a space and stays in the space condition for II bit times after serial reception starts. The
bit is cleared to a zero when the received signal returns
to the mark condition or on power-up.

08-10

Not

Read
only

used

00-07

Received
data
buffer

Reserved for future use.

Read
only

Table 6-4

These eight bits represent the most recent byte
received. These bits are cleared to zero on power-up.

Transmitter Control and Status Bit Descriptions

Bits

Name

Direction

Fundion

08-15

Not
used

Read
only

Reserved for future use.

Transmitter
ready

Read
only

The bit is set to a one when the XMIT data buffer is
ready to accept a byte. The bit is cleared to a zero by
writing into the XMIT data buffer. The bit is also set
to a one on power-up.

•

Transmitter
interrupt
enable

Read/
write

This bit is set to a one under program control. When
set, it allows an interrupt request to be initiated whenever the transmitter ready bit is set. The bit is cleared
to a zero by reset, power-up, or under program control.

6-5

Table 6-4 Transmitter Control and Status Bit Descriptions (Cont)
Bits

Name

Direction

Function

03-05

Programmable*
baud rate
select

Readj
write

The condition of these bits selects the baud rate under
program control provided the programmable baud rate
select enable bit is set. The baud rates are selectable by
setting these bits as follows.
05

Baud Rate

0
0
0
0
t
1
I
I

0
0
1
1
0
0
,1
1

0
1
0
I
0
I
0
1

300
600
1,200

2AOO
4,800
9,600
19,200
38,400

When the programmable baud rate select enable bit is
not set, the baud rate defaults to 300.
02

Maintenance

Readj
write

This bit is controlled by the program. When set to a
one the transmitter serial output is connected to the
receiver serial input and disconnects the external serial
input. This bit is cleared t.o a zero by INIT, power-up,
or the program.

Programmable*
baud rate
enable

Readj
write

This bit is controlled by the program. When set to a
one, bits 03-05 are used to determine the baud rate.
When cleared to a zero, the baud rate will be 300
baud. This bit is cleared to a zero by INIT, power-up,
or the program.

Transmit
break

Read!
write

This bit is controlled by the program. When set to a
one, the serial output is forced into the space condition.
This bit is cleared by INIT, power-up, or the program.

The transmitter programmable baud rate select and enable bits are level sensitive and are not latched. This requires that
software in control of the TCSR musl use bit set and clear instructions to access the TCSR once the baud rate has been
written into the SLU.

6·6

Table 6-5 Transmitter Data Buffer Bit Descriptions
Bits

Name

Direction

Function

08-15

Not
used

Read
only

Reserved for future use.

00-07

Transmit
data
buffer

Read/
write

These eight bits represent the next data byte to be
transmitted. These bits are cleared by power-up.

6.2.2 Interrupts
Each SLU provides both a receiver interrupt and a transmitter interrupt to request service from the onboard microprocessor. Receiver and transmitter requests can be independently enabled by software. The
receiver interrupt request is enabled when the RCV interrupt enable (bit 6) of the receiver control and
status register (RCSR) is set to a one.
SLU2 has a higher interrupt priority, level 5, than SLU 1 which has a level 4 interrupt priority. Within
each unit, the receiver has higher priority than the transmitter. SLUt uses vector address 60 for the
receiver and 64 for the transmitter. SLU2 uses vector address 120 for the receiver and 124 for the
transmitter. These relationships are described in Table 5·3.

6.3 PROGRAMMING THE PARALLEL I/O INTERFACE
The parallel I/O interface. illustrated in Figure 6-3, provides a means of transferring data between the
microprocessor bus and the user interface connector 13. The interface has four addressable registers for
data and control. Table 6-6 describes these registers.
Port A and B registers are used only for data transfer to and from the user interface. Port C is used for
both data transfer and control. The control word register is used only for control of the parallel I/O
interface. The interface is programmable by using this register. In addition to software programming, the
parallel interface can also be programmed by hardware (see Chapter 2).
The parallel I/O interface is complex, and understanding all its capabilities requires considerable effort.
However, efficient use can be made of the parallel I/O using a subset of its capabilities. The following
paragraphs are organized to help users find needed information. The flowchart in Figure 6-4 provides an
overview of the following discussion on the parallel I/O interface, and helps guide users to the paragraphs
of specific interest to them.

6.3.1

Modes of Operation

The interface ports can operate in three basic modes that are selected by system software setting bits in the
control word register. The modes are defined as mode 0, I, and 2 and define how the data is routed
through ports A and B.

NOTE
If the bidirectional buffers are being hardwired, care
must be taken to ensure that the wired direction
agrees with the programmed directions of ports A
and B. This is necessary to prevent driver output to
driver output connections, which could damage tbe
integrated circuits.

6-7

CONTROL
WORD
REGISTER

peo
PC3

}

INT,RRUPTS

176206
USER CONNECTOR

r74~441

3
4
10
PORTe

::J

II:

III
V'l

w
U

176204

II:

A DATA
(8 LINES)

PORT A

176200

.-J

M51JIR
[)--

GND

r -I

PORT B

176202

(8 LINES)

-1

lolR-,

I
---o---[J.:......f DELAY
NETWORK
MOO M49

+3 VDe

B DATA

L_-1
MR·12t50

Figure 6-3

Parallel I/O Interface

Table 6-6 ParaUell/O Register Addresses
Register

Address

Status

Port A
Port B
Port C
Control word

J76200
176202

Read/write
Read/write
Read/write
Write only

176204

176206

6-8

PAAA' L.U INTiRPACI!

6.3'''ooll''''''''''''G THe PAR"L.lEL 110 INTERFACe
TABLE fl./lPARALLEL ilO REGISTER ADDRESSES
'IGURE 6-3 PARALLEL I}O INTEftfACe

YOU ARE ""fiE

I
_T1tO\.~ fI~G1STJ;R

MOOUOF OI'1!AATION
5.3.1 MOQlfS OF ope flA r,ON

6.3.2 CONTROL WOAD REGISTER

6.3.llI'OAT C REGISTER

TABLE 1>11 CONTROL REGISTER MODE SELlicnON elT FUNCTiONS
6.3.2.1 MODE SELECTION
TASlE 6·18 CONTROL WORDS FOR MODi SEU!CTION

_0
9'

6.3.1.2 MODE 0 !lIASIC INPUTIOUTPUn
TAIIL!;6-] MOllE 0 CONflGUIiATION
6.3.1.31'OIIT A AND II REGISTERS
TASLE 1>3 MODE (j PORT A OR 8 BIT OESCIIIPTIONS
6.3.1.4 POIIT C REGISTER IN MODE 0
TABl.E 1>9 MODE Q PORT C Blr DESCRIPTiONS
FIGURE o.a MOOE 0 PORT C air ASSIGNMENTS

_2
I

"I
MODEl
6.3.I.SMOOE IISTRoaeD INPUTIOUTPUTI
TAliLE a·IOPORT C CONTROL SIGNALS IN MODE 1
TAIlE i·l1 COMBINATIONS Of MODE 1
TABLE 6-12 MODE 1 POI<TC 81T DeSCRIPTIONS
TASLE f>1JMOOE I CONFIGURATION
FIGUR~ 6-7 MOOE II'ORT C eIT ASSIGNMENTS

6.3.2.2 SETTING lilTS IN PORT C
TABLE $..9 CONTROL REGISTER SIT SETiRESH FUNCTlQNS
TA8LE ft.2CINTERRUPT SET/RESET CONTROL WORDS

ifi.J. U MODe 1 ,STROIeo BIDIRECTIONAL 110)

TAIILE6-14 PORT CCONTIlOLSlGHALSIN MOD£ 2

TABLE I>ISMODfi tPORT ClllT QESCRIPT10NS
TABLE 8-13 MODE 2 CONF IGURATION

INITIALIZATION

FIGURE o.a MODE 21'ORT C BIT ASSIGNMENTS

6.33 PARALLel 110 INITlAllZA liON

1
HAN_ING
6.3.4 PARALLEL I/O IlANIlSHAKING
TABLE l>21 MODE 11NI'UT HANDSHAKING SIGNALS
TABLE 6-22 MODE I OUTPUT HANDSHAKING SIGNALS
TABLE 8·23 MODE 2 BIDIRECTIONAL HANOS>lAKING SIGNALS
FIGURE 6-9 MODE I INPUT DATA HANIlSHAIUNG lilQUENCf
FIGURE 6·10 MODE' 5TIIOI.O INPUT TIMING
FIGURE
MODE! OU'll'UT OATA HANllSKAK1NG S£QUENCf
FIGURE 6-12 MOOE 1 POIIT ASTROIlEOOU'll'UT TiMING
FIGURE 6-13 MOllS 1 PORT B STROllED OUTPUT TIMING
fiGURE fl.14MOOf ?I'ORT A810i~ECTIONAL TIMING
- ------- .. _" "--- _.... _-_. __ .
._--------_._---------

.,1

Figure 6·4

Parallel I/O Flowchart

6.3.1.1 Port C Register - The bit assignments for the port C register are dependent on the mode selected
and the direction of ports A and B. This register provides the handshake controls to interface between the
8255A·5 and the output connector. The handshake control bits are set/reset by using the control word
register which is described in Paragraph 6.3.2. The port C condition for the different modes is described in
the following paragraphs that explain the modes.
6.3.1.2 Mode 0 Basic Input/Output - Mode 0 provides simple input and output of either port A or port
B or both as described in Table 6·7. The data is read from the port if programmed as an input or written to
the port if programmed as an output with no handshaking requirements. The port A and port B
bidirectional buffers may be hardwired as described in Chapter 2. They may also be program controlled by
port C bits 4 and 6 if dynamic change of the port direction is wanted. In this mode, the outputs are latched
but the inputs are not.

Table 6-7

Mode 0 Configuration

PPI
Element

To Act
as Input

To Act
as Output

Direction Control
via Port C

Port A

M52 to M50

M52 to MSI

MS2 to M54 or M58

Port B

M49 to M50

M49 to M51

M49 to M54 or M58

PC7

Never an input

Always an output

PC6

M54 to M53

Never an output

pes

Never an input

Always an output

PC4

M58 to M65

Never an external
output

PC3

Never an input

Interrupt A
(vector 134)
Always an output

pe2

Always an input

Never an output

PCI

Never an input

Always an output

peo

Never an input

Interrupt B
(vector 130)
Always an output

6-10

6.3.1.3 Port A and B Registers - The bit assignments for the port A and B registers are soown in Figure
6·5 and described in Table 6-8. The port A and B registers are used as data buffers for aU modes of
operation.
6.3.1.4 Port C Register in Mode 0 - Ports A and B use no handshaking signals, and some port Clines
can be used as input/output data lines. The bit assignments are shown in Figure 6-6 and described in Table
6-9. When peo and PC3 lines are not used as interrupt requests, they should be cleared by the control
word to prevent false interrupts.
6.3.1.5 Mode 1 (Strobed Input/Output) - In mode 1. the lines on port C generate or accept signals from
the user interface that control the transfer of data through ports A and B. Port C bits 0-3 (lower nibble)
are used with port B, and bits 4-7 (upper nibble) are used with port A. These signals are known as
handshaking signals. The basic functions of these control signals are defined in Table 6-10 followed by a
more detailed description of the handshake protocol.
Table 6·11 describes the four input/output combinations of ports A and B usable in mode t. The port C
bit assignments used in mode 1 are illustrated in Figure 6·7 and described in Table 6-12. Table 6~ 13 links
operation of mode 1 to the jumper configunitions discussed in Chapter 2.

: UNDE:FINEO:
PORT DATA
"'PI·7211

Bits

Name

08-15

Undefined

00-07

Port data

Figure 6-5

Mode 0 Port A or B Bit Assignments

Table 6-8

Mode 0 Port A or B Bit Descriptions

Direction

Function
Not valid if a read is performed on the entire word.

Read/write

Data to output or input data to be read, depending on
the port direction.

6-11

UNDEFINED

Figure 6-6

Mode 0 Port C Bit Assignments

Table 6-9 Mode 0 Port C Bit Descriptions
Bits

Name

08-15

Undefined

PC7

Read/write'"

Output bit, drives the LED.

PC6

Read/write'"

If port C upper is defined as input and M54 is connected to M53, it is an input bit. If port C upper is defined
as output and M54 is connected to M52 (M49), it is
output that controls the buffer direction for port A
(port 8), A one sets the buffer for input and a zero for
output.

peS

Read/write'"

Same as PC7, no LED.

PC4

Read/write'"

If port C upper is defined as input and M58 is connected to M65, it is an input bit. If port C upper is defined
as output and M58 is connected to M49 (M52), it is
output that controls the buffer direction for port B
(port A). A one sets the buffer for input and a zero for
output.

PC3

Not used

Not valid

PC2

Read only

Input bit

00-01

PeO-PCI

Not used

Not valid

Direction

Function
Not valid if a read is performed on the entire word.

Bil is written by using the control word bit set/reset function explained in Paragraph 6.3.2.

6-12

Table 6-10

Port C Control Signals in Mode 1

Abbreviated/
Port C Bit

Function

Strobe input

STBA/PC4
STBB/PC2

A low on this input loads user data into the
input latch.

Input buffer full

IBFA/PC5
IBFs/PCI

A high on this output acknowledges that
the data has been loaded into the input
latch. Set by STB and reset by the program
reading the input latch.

Interrupt request
(Input mode)

INTRA/PC)
INTRBlpcO

A high on this output can interrupt the
CPU when an input device strobes its data
into the port.

Interrupt enable
(Input mode)

INTEA/PC4
INTEB/PC2

Enables setting of INTRA and INTRaProgram controlled by PC4 or pe2.

Output buffer full

OBFA/PC7
OBFs/PCI.

This output goes low to tell the user interface that the CPU has written data to the
port. Reset by ACK input going low.

Acknowledge input

ACKA/PC6
ACKs/PC2

A low on this input tells the processor that
the user's device accepted the data from A
orB.

Interrupt request
(Output mode)

INTRA/PC3
1NTRa/PCO

A high on this output can interrupt the
CPU when an output device has accepted
data transmitted by the CPU. Set by ACK
and reset when new data is written to the

Signal

port.
Interrupt enable
(Output mode)

Enables setting of INTR. Program con~
trolled by PC6 or PC2.

INTEA/PC6
INTEB/PC2

6-13

Table 6-11

Combinations of Mode I

Port C Bit
FUIletions

Port A Input
with
Port B Output

Port A Output
with
Port B Input

Ports
A&B
Output

Ports
A&:B
Input

STBA

PC4

N/A

PC4

STBB

N/A

PC2

N/A

PC2

IBFA

PCS

N/A

PC5

IBFB

N/A

PCI

N/A

PCI

INTRA

PC3

INTRB

PCO

OBFA

N/A

PC7

N/A

OBFB

PCI

N/A

PCI

N/A

ACKA

N/A

PC6

N/A

ACKB

PC2

N/A

PC2

N/A

Other port C outputs

PC7
(controls LED)

N/A

PC5

N/A

Other port C inputs

NjA

PC4

NjA

PC6,7

X
0

X
0
I

X
1

1
1

X
1
I
1
0
1

0
I

Control Word
DO (Direction of PCO-3)
D I (Direction of port B)

02 (Mode of port B)
D3 (Direction of PC4-7)
04 (Direction of port A)
05 Port A mode
06 Port A mode
D7 Mode set enable

6-14

: UNDE;INED:

I/O IIBFA

1 110

: UNDE;INEo;

05
110

10BFAI

! I I
I

INTRB

IINTRA}

INTEA
(ACKA)

A AND B BOTH OUTPUTS

INTEI3
(STBB)
03

(BFB

IINTR4

INTEA
(STBA)

A AND B BOTH INPUTS
15

10BFB[

INTEB
lACKS}

I
I

INTRB

MfH213

Figure 6-7

Mode 1 Port C Bit Assignments

Table 6-12 Mode I Port C Bit Descriptions

Bits

Name

08-15

Undefined

PC7

Direction

Function
Not valid if a read is performed on the entire word.

Read/write*

If port A mode I input:

If port C bits 04-07. are defined as output, this bit is
an output bit and controls the LED. A zero turns the
LED on, and a one turns it off.
Unused if port C bits 04-07 are defined as input
OBFA**

Read only

If port A mode 1 output:
OBFA goes low to indicate that data has been written
into the output buffer by the processor. This bit is set
when the ACKA (PC6, M54 to M53) input goes low
indicating that the external device has accepted the
output data. OBFA is present on PC7 to the external
device.

PC6

Read/write*

If port A mode I input:
If port C bits 04-07 are defined as input and M54 is
connected to M53. it is an input bit. If port C bits
04-07 are defined as output and M49 is connected to
M54, it is an output that controls the buffer direction
for port B. A one sets the buffer for input. and a zero
sets the buffer for output.

Table 6-12
Bits

Mode 1 Port C Bit Descriptions (Cont)

Name

Direction

INTEA

Read/write *

Function
If port A mode 1 output:
When set, INTEA enables INTRA to interrupt the
SBC-II/21 PLUS when output data has been accepted by the external dev.ice.
When M54 is connected to M53, an external signal
acknowledging the receipt of data acts as INTEA.

ACKA
05

IBFA

Read only

If port A mode 1 input:
IBF A indicates that the input data has been latched
for port A. It is set by the STBA input (PC4, M58 to
M65) going low and is reset by the processor reading
the port data. This signal is present on PCS to the
external device.

PCS

Read/write*

If port A mode I output:
If port C upper is defined as output, it is an output bit.
If port C upper is defined as input, it is unused.

INTEA

Read/write*

If port A mode I input:
If set, INTEA will allow INTRA to interrupt the
SBC-ti/21 PLUS whenever the input buffer is full.

PC4

Read/write *

If port A mode 1 output;
If port C bits 04-07 are defined as output and M49 is
connected to M58, this bit is output that controls the
direction of the port B buffer. A one sets the buffer for
input and a zero sets it for output If port C bits 04-07
are defined as input and M58 is connected to M65, it
is an input bit and is interpreted as STBA (input
strobe).

INTRA

Read only

If port A mode 1 input:
A one indicates that port A has valid input data. It is
set by STBA (PC4, M58 to M65) being pulsed low
and is reset by the processor reading the port data.
INTRA is enabled by INTEA being a one and disabled by INTEA being a zero.
If port A mode 1 output:
A one indicates that port A is ready to accept new
output data. It is set by ACKA (PC6, M54 to MS3)

6-16

Table 6·12

Bits

Name

Mode I Port C Bit Descriptions (Cont)

Direction

Function

being pulsed low and reset by the processor writing
new output data to the port. Enabled and disabled as
above.
When enabled, INTRA interrupts the processor and
has a vector of 134.
This signal is also an output to the external device on
line PC3.
02

INTEB

Read/write*

When set, INTEB will allow INTRB to interrupt the
SBC-l ! /21 PLUS to request service.

IBFB

Read only

If port B mode 1 input:
IBFB indicates input data has been latched for port B
when a one. It is set by the STBB (PC2) being low and
is reset by the processor reading the port data. This
signal is prescnt on PC 1 to the external device.

OBFB**

Read only

If port B mode I output:
OBFB goes low to indicate that the processor has writ~
ten data to the port. This bit is set by ACKB (Pe2)
going low, indicating the external device has accepted
the output data. This signal is present on PC I to the
external device.

INTRB

Read only

If port B mode 1 input:
A one indicates port B has valid input data. It is set by
STBB (PC2) being pulsed low and is reset by the
processor reading the port data. INTRB is enabled
when INTEB is one and disabled when it is zero.
If port B mode I output:
A one indicates the port is ready to accept new output
qata. It is set by ACKB (Pe2) being pulsed tow and
reset by the processor writing new output data to the
port. Enabled and disabled as above.
This signal is also an output to the external device on

peo.

•

Bit is written by using the control word bit set/reset function described in Paragraph 6.3.2 .

••

If OBF is asserted low and a read or write access is made to the port by the processor before an ACK strobe is sent by the
external device. the OBF line for the accessed port will negate during the assertion of the read or write to the port and
become reasserted when the read OF write operation is complete.

Table 6-13 Mode 1 Configuration
PPI
Element

Input
Conditions

Output
Conditions

Program Control
via Port C

Port A

M52 to M50

M52 to M51

N/A

Port B

M49 to M50

M49 to M51

M49 to M54 or M58

PC7

Never an input

Output buffer A full

PC6

M53 to M54
(Acknowledge A)*

Never an external
output

PC5

Never an input

Input buffer A full

PC4

M65 to M58
(Strobe A)

Never an external
output

PC3

Never an input

Interrupt A
(vector 134)

PC2

Strobe B
in input mode
Acknowledge B in
output mode

Never an output

PCI

Never an input

Buffer B full on
input or output

PCO

Never an input

Interrupt B
(vector 130)

*User's hardware acknowledges receipt of data output by port A.

6.3.1.6 Mode 2 (Strobed Bidirectional I/O) - Mode 2 implements communication with a user device
over a single 8·bit bus for both transmitting and receiving data. Handshaking and interrupt signals are used
as they are in mode 1.
Mode 2 is used with port A only and five control lines on port C. Both inputs and outputs are latched.
When port A is operating in this mode, the port B bidirectional buffers cannot be operated under program
control because PC4 and PC6 are being used. Port B can operate in either mode 0 or mode 1 but the
buffers must be hardwired. PCG-PC2 are defined by port B conditions for mode I and are available as
I/O lines when port B is in mode O.
Control signals are defined in Table 6~ 14. The port C bit assignments as used in mode 2 are illustrated in
Figure 6-8 and described in Table 6-15. Table 6-16 links operation of mode 2 to the jumper configurations
discussed in Chapter 2.

6-18

Table 6-14

Signal

Port C Control Signals in Mode 2

Abbreviated/
Port C Bit

Function
A high on this output can interrupt the

Interrupt request

CPU for both input and output
operations.
Output buffer full

This output goes low to indicate that the

OBFA/PC7

CPU has written data to port A.
A low on this input enables the output
tristate buffers of port A to send out the
data. Otherwise, that buffer is in the high
impedance state.

Acknowledge

Interrupt enable

INTEAl/PC6

Enables INTR when OBF is true. Controlled by bit set/reset of PC6.

Strobe input

STBA/PC4

A low on this input loads data into the
input latch.

Input buffer fun

IBFA/PC5

A high on this output indicates that data
has been loaded into the input latch.

Interrupt enable

INTEA2/PC4

Enables INTR when IBF is true. Controlled by bit set/reset of PC4.

6-19

: UNOE:FINEO:

IOBFAI

IIBFA

I
INTEA 1
(ACKA)

I \INTRj

I
tNTEA 2

I I

(STBAI

Figure 6-8

Mode 2 Port C Bit Assignments

Table 6-15

Mode 2 Port C Bit Descriptions

Bits

Name

08-15

Undefined

OBFA

Read only

Will go low to indicate that the processor has written
output data to the port. It goes high when ACKA
(PC6, M54 to M53) goes low indicating the external
device has accepted the data. This signal is output on
PC7 to the external device.

INTEAl

Read/write *

When this bit is set, it allows an interrupt INTRA
when the output buffer is ready to accept new data.

IBFA**

Read only

IBF A indicates that input data has been latched when
it is a one. This bit is reset when the processor reads
the input data. This signal is output on PCS to the
external device.

INTEA2

Read/write *

When this bit is set, it allows an interrupt INTRA
when the input buffer is full.

INTRA

Read only

A high on this bit indicates that the port is requesting
service of the processor. This signal is output on PC3
to the external device.

02-00

PCO-PC2

*
**

Direction

Function
Not valid if a read is done on the entire word.

These bits are defined by port B mode selection.

Bit is written by using the control word bit set/reset function described in Paragraph 6.3,2.
When using port A in mode 2 operation. the software must clear the input buffer of port A if the input buffer full flag
(IBFA) is set before it performs the read during an intended write to ensure that the handshake lines and port flags are not
set out of sequence.

6-20

Table 6-16

Mode 2 Configuration

PPI
Element

Input
Conditions

Output
Conditions

Port A

Bidirectional bus

M52 to M54 to M53

Port B

Hardwired only

PC7

Never an input

Output buffer A full

PC6

Acknowledge A

Never an output

PC5

Never an input

Input buffer A full

PC4

Strobe A (M65 to M58)

Never an output

PC3

Never an input

Interrupt A (vector 134)

PC2

Always an input

Never an output

PCI

Never an input

Always an output

PCO

Never an input

Always an output

6-21

6.3.2 Control Word Register
The control word register controls the operation of the parallel interface. If bit 7 is set, the contents of the
register determine the mode of operation and the input/output direction of the ports. If bit 7 is cleared. the
contents of the register set/reset the port C register bits. The functions of the register bits are described in
Table 6-17 and are selected by the state of the bit.
6.3.2.1 Mode Selection - The user determines the mode of operation for the ports and defines them as
inputs, outputs, or bidirectional. The user then must ensure that the bidirectional buffers are configured
(see Chapter 2) to match the software requirements. Table 6-18 lists all the control words available for the
control word register. The user selects the control word that matches the requirements and loads it into the
register. The register is defined as write only; reading the register results in erroneous data.
6.3.2.2 Setting Bits in Port C - The control word register is also used to set or reset the port C register
bits. The control word bit functions are described in Table 6-19. To set a bit, the register is loaded with bit
7 cleared, bits 1-3 equal to the bit number being set, and bit 0 set. To reset the same bit, bit 0 is cleared.
The bit set/reset can be used to enable or disable the port A and port B interrupts for the SBC-II /21
PLUS. The control words used to enable or disable the interrupts are listed in Table 6-20.

Table 6-17

Control Register Mode Selection Bit Functions

Bits

Bit Set

Bit Reset

08-15

Unused

Always set

Port A mode 2

Port A mode 0 or I

Port A mode 1

Port A mode 0

Port A input

Port A output

Port C bits 04 and 06
inputs

POft C bits 04-07
outputs

Port B mode 1

Port B mode 0

Port B input

Port B output

Port C bit 02 input

Port C bits 00, 01,
and 03 outputs

6-22

Table 6-18 Control Words for Mode Selection

Port A
Mode 0 IN

Port A
Mode 0 OUT

Port A
Mode 1 IN

Port A
Mode lOUT

Port A
Mode 2

Port 8
Mode 0
IN

Port 8
Mode 0

Port B
Mode 1
OUT

Port C

PortC

OUT

Port B
Mode 1
IN

PC4,PC6

PC5,PC7

233

231

237

235

Input

233

221

227

225

213

2It

217

215

203

201

207

205

273

271

277

275

263

261

267

265

253

251

257

255

243

241

247

245

3X3

3Xl

3X7

3X5

·Port C unavailable, used for handshaking.
X = Do not care condition.

6-23

Output
Input
Output
Input
Output
Input
Output

Table 6-19 Control Register Bit Set/Reset Functions
Bits

Function

08-15

Not used

Always reset

06-04

Not used

03-01

These bits select the port C bit ~hat is to be set or reset as follows.

Bit

PeO

o
o
o

o
o

PCl

Pe2
PC3
PC4
PC5
PC6
PC7
00

o
t
1
I

o
1

1
1

This bit is set to set the selected bit or is cleared to reset the selected bit of port C.

Table 6-20

Interrupt Set/Reset Control Words
INTRA

INTRB

Direction

Enable

Disable

Enable

Disable

Input

01 t

010

005

004

Output

015

014

005

004

Input

011

010

None*

Output

015

014

None*

None·

Mode

·Port B does not function in the bidirectional mode 2.

6-24

6.3.3

Parallel I/O Initialization

During power-up or the execution of a RESET instruction, the port C data lines are driven high and the
LED (driven by bit 7 of port C) is turned off. If the bidirectional buffers of ports A and B are hardwired,
the directions are not changed, and the data lines are driven high if the buffer is configured as an output. If
the bidirectional buffers of ports A a~d B are program controlled by port C, the data lines will go to the
input state.

6.3.4

Parallel I/O Handshaking

The paraUell/O can operate in either mode 0, 1, or 2 to transfer data into or out of the SBC-ll /21 PLUS.
The mode 0 data transfers do not require any handshaking control signals. The mode 0 input data is not
latched, and data should be available on the I/O connector at the same time as the read strobe enables the
8255A-5. The mode 0 output data is latched, and data is valid at the J/O connector 362 ns after the
trailing edge of the write strobe to the 8255A-5.
The handshaking signals that pass across the user interface are detailed as follows. Mode 1 operation
requires the handshaking control signals; these are dependent on defining the ports as inputs or outputs.
Mode 1 input signals are listed in Table 6-21, and the handshaking function is shown in Figure 6-9. Mode 1
input timing is described in Figure 6-10. Mode I output signals are listed in Table 6·22, and the
handshaking function is shown in Figure 6-11. Mode 1 output timing is described for port A in Figure 6}2, and mode 1 output timing is described for port B in Figure 6-13. Mode 2 operation allows port A to be
bidirectional. The handshaking signals are listed in Table 6-23, and mode 2 timing is described in Figure 6·
14. When port A operates in mode 2, port B can operate only in mode 0 or mode I.

Table 6-21

Mode I Input Handshaking Signals

Signal Name

Function

5TB (A or B)
Port A - PC4
Port B - PC2

Strobe input -- This signal is asserted low by the external device and loads
data into the 5BC-ll 121 PLUS input port latch. It must be asserted low for
525 ns minimum.

IBF (A or B)
Port A - pes
Port B - PCI

Input buffer fun - This signal is asserted by the SBC-1I/21 PLUS in
response to an assertion of 5TB to notify the interface that data was loaded
into the input latch.

INTR (A or H)
Port A -- PC3

Interrupt request -, This signal can be used to generate an interrupt to the
microprocessor, The bitset/bitreset commands must be used to
enable/disable the INTE bit for each port. Interrupts will be generated
either when STH is negated with IBF asserted, or when ACK is negated
with OBF asserted.

6-25

SBc·n /21 PLUS

EXTERNAL O£Vtce

REQUeST DATA
• tSF UNASSERTED ~ .

~SENDDATA
• PLACE DATA ON I/O BUS
• ASSERTSm
ACCEPTS DATA
• ASSERTS IBF
ACKNOWLEDGES ACCEPTED DATA
• UNASSERTED

REQUEST INTERRUPT IF INTE SET
• ASSERT INTR
/
• PROCESSOR READS DATA PORT
• NEGATE INTR IF ASSERTED
• NEGATEI8F

MR·121!52

Figure 6-9

Mode I Input Data Handshaking SCquence

f---"'1,
;.----------------I ~',~M l- :
....: :l:S ~
512M MIN--f

P-~------------~----~
I

IBF

-.: 312M MAXIINTR

INPUT DATA
110 SUS

I.
I

- - - - - -<

12m
MlN·

.._

r-----~----~
I

....
I

192M I
MIN

.',

VALIDDATA)t- -

It
- -

- -,I

t
I

PORT DATA
READ

MII·12U

Figure 6-10 Mode I Strobed Input Timing

6-26

Table 6-11 Mode t Output Handshaking Signals
Signal Name

Function

OBF (A or B)
Port A - PC7
Port B - PCI

Output buffer full - This output is asserted low to indicate that the
microprocessor has written data into the specified port latches.

ACK (A or B)
Port A - PC6
Port B - PC2

Acknowledge input - This signal is asserted low by the external device to
indicate it has accepted the latched output data from the specified port.

INTR (A or B)
Port A - PC3
Port B - PCO

Interrupt request - This signal can be used to generate an interrupt to the
microprocessor when the external device has received the data and INTE
is set and ACK is negated.

SSC· 11121 PLUS

EXTERNAl. PEVICE

OUTPUT DATA
• OUTPUTS DATA ON I/O BUS
• ASSERTSO'BF

ACCEPT DATA_
• ASSERTSACK
_________
• READS DATA
OUTPUT COMPLETE ...------• NEGATESOiiF ______
- - - - - . . . ACKNOWLEDGES RECEIVED DATA
• UNASSERTSACK

GENERATE INTERRUPT
IF lNTE SET
• ASSERTS INTR
NOTES:

IF ('j8I! IS ASSERTED lOW AND A READ OR WRITE TO THE PORT
BY THE SBC·11121 PROCESSOR OCCURS BEFORE AN ACK STROBE IS
SENT BY THE EXTERNAl. DEVICE. THE OBl'lINE FOR THE ACCESSED
PORT WILL NEGATE DURING THE ASSERTION OF THE READ OR WRITE
TO THE PORT AND THEN BECOME REASSERTED.

emrWILL ASSERT ON THE READ PORTION OF EVERY READ BEFORE
INTENDED WRITE TO PORT S.• AND THE oaFs WILL NEGATE AND REASSERT
ON THE WRITE STROBE. IF JPlTEa IS SeT AND INTRa IS ASSERTED, INTRa
WILL NEGATE ON THE READ BEFORE THE INTENDEDWRITE TO PORT B
(SEE FIGURE 6-13.1

0fi1= WILL ASSERT ON THE WRITE PORTION OF EVERY READ BEFORE

INTENDED WRITE TO PORT A. IF INTEA IS SET AND INTRA IS ASSERTED.
INTRA WILL NEGATE ON THE WRITE PORTION OF THE READ BEFORE
INTENDED WRITE TO PORT A.
..R·1::I18

Figure 6~ It

Mode 1 Output Data Handshaking Sequence

6-27

WAjn
PORTOATA _ _ _~

1-1

1-------11

----------Ti:l

INTRA

58fA

fool- - - - - -

162m MAX

-t ~

I 862m f

f 3750s I

; MAX ~

till MAX.J

f 362m I

~~?~
t
MAX

- - _ I----i~~
11

ACKA---=---------------~I------~t~

,...-.-,

MAX
.......--,

OUTPUT DATA - - - - - - - - - - - - - , W

A LATCHED OUTPUT DATA

Iro8US-----------------------~·

Figure 6-12 Mode I Port A Strobed Output Timing

WR _ _ _ _ _ _...J

flO

662ns

I MAX I

r--...,.·- - ~

OBfijOL.o---t......ft--tt..-_____

INTR8

-.....a,:....,

'MAX I

ACKi ______________________

t..-.J 37Sns

I~------~X

362nsl

MAX ~

LATCHED OUTPUT

DATA
---'X,..-......;-.;.;,----:

OUTPUT DATA _ _ _ _ _ _ _ _ _ _ _
1/08U5

. .

NOTE:
1. OOF Will. ASSERT ON THE READ PORTION OF EVERY READ 8EFOM

INTENDED WRITE TO PORT B AND THE i5II": WILl. NEGATE AND REASSERT
ON THE WRITE STROBE. IF INTEa IS SET A;.n) INTRa JS ASSERTEO. INTRa
WILL NEGATE ON THE READ BEFORE THE INTENDED WAITE TO PORT B.

Figure 6~ 13 Mode 1 Port B Strobed Output Timing

6-28

Table 6-23 Mode 2 Bidirectional Handshaking Signals
Signal Name

Function

STB (PC4)

Strobe input - This signal is asserted low by the external device and
strobes data into port A.

fBF (PCS)*

Input buffer full - This signal is asserted when the microprocessor has
accepted STB strobe.

INTR (PC3)

Interrupt request - This signal can be used to generate an interrupt to the
microprocessor when the external device is demanding service ..

OBF (PC7)

Output buffer fun - This output is asserted to indicate that the
microprocessor has written data into the output port latches.

ACK (PC6)**

Acknowledge input - This signal is asserted low by the external device to
indicate it has taken data from the output port latches. It controls the DIR
pin of the port A buffer.

.. .

....

Because every write is preceded by a read. the contents of the input buffer should be saved if IBF A is asserted prior to
writing port A mooe 2 data.
When mode 2 is configured, PC6 (ACK) is jumpcrcd to the port A direction control pin through a rising edge delay
circuit. Hence, when PC6 is negated, the rising edge is delayed by 250 ns minimum. This means that the buffer will be
driving data out of the connector 250 ns minimum after the user interface negates ACK.

WRITE - - ,
PORT A
L..- - - - 4

375m.

L,.622n$ MAX.J

i
INTR

t..MAX.J

1 ...___-'----1
I

325m

~MIN

----------~I

('~

ISF

312"5 1;
MAX!

-,.
1205

r
I 192n5 I

""M1NtoI4 MiN ..,

~~~'0s

. - - -(

I~--------

r--'

Aa<,
I 525115

/3250$1

~A~I OUTPUT
DATA

INPUT DATA

I 3120$JI:A~I
I

'f .J - {o..----,h- .,. - -.

READ
PORTA

Figure 6-14

Mode 2 Port A Bidirectional Timing

6-29

CHAPTER 7
ADDRESSING MODES AND INSTRUCfION SET

7.1 INTRODUCfION
This chapter provides a detailed discussion of addressing modes and descriptions of individual instructions.
The discussion of addressing modes is divided into six major topics.
I.

Single operand addressing - One part of the instruction word specifies the registers; the
remaining part provides information for locating the operand.

Double operand addressing - Part of the instruction word specifies the registers; the remaining
parts provide information for locating two operands.

Direct addressing - The operand is the content of the selected register.

Deferred (indirect) addressing - The content of the selected register is the address of the
operand.

Use of the program counter (PC) as a general-purpose register - The PC is uniqueJrom other
general-purpose registers. Whenever the processor retrieves an instruction, it automatically
advances the PC by two. By combining this automatic advancement of the PC with four of the
basic addressing modes, four special PC modes are produced - immediate, absolute, relative,
and relative deferred.

Use of the stack pointer (SP) as a general-purpose register - The SP can be used for stack
operations.
NOTE
Instruction mnemonics and address mode symbols
are suff'lCient for writing assembly language programs. The programmer need not be concerned
about conversion to binary digits; this is accom~
plished automatically by the assembler program.

7.:1 ADDRESSING MODES
Data stored in memory must be accessed and manipulated. Data handling is specified by an SBC-II/21
PLUS instruction (MOV, ADD, etc.) that usually specifies the following.
1.

The function to be performed (operation code),

A general·purpose register to be used when locating the source and/or destination operand.

An addressing mode that specifies how the selected register(s) is/are to be used.

Most data handled by a computer is structured (in character strings, arrays, lists, etc.). SBC-ll/21 PLUS
addressing modes allow efficient and flexible handling of structured data.
The general-purpose registers may be used with an instruction in any of the following four ways.

As accumulators. The data to be manipulated resides within the register.

As pointers. The content of the register is the address of the operand, rather than the operand
itself.

As pointers that automatically step through memory locations. Automatically stepping forward
through consecutive locations is known as autoincrement addressing; automatically stepping
backward is known as autodecrement addressing. These modes are particularly useful for
processing tabular or array data.

As index registers. The contents of the register and the word following the instruction are
summed to produce the address of the operand. This allows easy access to variable entries in a
list.

The register arrangement is an important microprocessor feature that should be considered in conjunction
with the addressing modes. There are six general-purpose registers (RO-R5), a hardware stack pointer (SP)
register (R6), and a program counter (PC) register (R 7).
Registers RO-RS are not dedicated to any specific function; their use is determined by the instruction that
is decoded.
I.

They can be used for operand storage. For example, the contents of two registers can be added
and stored in another register.

They can contain the address of an operand or serve as pointers to the address of an operand.

They can be used for the autoincrement or autodecrement features.

They can be used as index registers for convenient data and program access.

The SBC-ll/21 PLUS also has instruction addressing mode combinations that facilitate temporary data
storage structures. These combinations can be used for conveniently handling data that must be accessed
frequently. This is known as stack manipulation. The register that keeps track of stack manipulation is the
stack pointer (SP). Any register can be used as a stack pointer under program control; however, certain
instructions associated with subroutine linkage and interrupt service automatically use register R6 as a
hardware stack pointec. and therefore. R6 is frequently referred to as the SP.
•

The stack pointer keeps track of the latest entry on the stack.

•

The stack pointer moves down as items are added to the stack and moves up as items are
removed. It always points to the top of the stack.

•

The hardware stack is used during trap oc interrupt handling to store information and allow the
processor to return to the main program.

Register R7 is used by the processor as its program counter (PC) and should not be used as a stack pointer
or accumulator. Whenever an instruction is fetched from memory. the program counter is automatically
incremented by two to point to the next instruction word.

7-2

7.2.1 Single Operand Addressing
The instruetion format for aU single operand instructions (such as clear, increment, and test) is illustrated
in Figure 7-1.
15

OPCODE

DESTINATION ADDRESS

Figure 7·1

Single Operand Addressing

Bits 15-6 specify the operation code that defines the type of instruction to be executed, Bits 5-0 form a 6bit field called the destination address field that consists of two subfields.
1.

Bits 0-2 specify which of the eight general-purpose registers is to be referenced by the instruc·
tion word.

Bits 3-5 specify how the selected register will be used (address mode). Bit 3 is set to indicate
deferred (indirect) addressing.

7.2.2 Double Operand Addressing
Operations that imply two operands (such as add, subtract, move, and compare) are handled by instructions that specify two addresses. The first operand is called the source operand; the second operand is
called the destination operand. Bit assignments in the source and destination address fields may specify
different modes and different registers. The instruction format for the double operand instruction is
illustrated in Figure 7·2.

OP~ODE

:MODE:

SOURCE ADDRESS

Figure 7·2

DESTINATION ADDRESS

Double Operand Addressing

The source address field is used to select the source operand, the first operand. The destination is used
similarly and locates the second operand and the result. For example, the instruction ADD A, B adds the
contents (source operand) of location A to the contents (destination operand) of location B. After
execution, B will contain the result of the addition; the contents of A will be unchanged.
Examples in this chapter use the sample SSC-tI/2l PLUS instructions listed in Table 7~1. See Paragraph
7.3 for a complete list of the SOC-] t/21 PLUS instructions.

7-3

Table 7-1 Sample SOC-Hill PLUS Instructions '
MneRMmic Description

Octal Code

CLR

Clear (zero the specified destination)

005000

CLRB

Clear byte (zero the byte in the specified destination)

10500D

INC

Increment (add one to the contents of the destination)

005200

INCB

Increment byte (add one to the contents of the destination byte)

105200

COM

Complement (replace the contents of the destination by its
logical complement; each zero bit is set and each one bit
is cleared)

oo510D

COMB

Complement byte (replace the contents of the destination byte by
its logical complement; each zero bit is set and each one bit
is cleared)

105100

ADO

Add (add source operand to destination operand and store the
result at destination address)

06SS00

DD = destination fiek! (6 bits)
SS ,.. source field (6 bits)
0= contents of

7.1.3 Direct Addressing
Table 7~2 summarizes the four basic modes used with direct addressing. Figures 7-3, 7-4. 7-5, and 7-6,
which follow the table, illustrate these four modes.

Table 7-1

Direct Addressing Modes

Assembler
Mode

Name

Syntax

Function

Autoincrement

(Rn)+

Autodecrement

'"'(Rn)

Index

X(Rn)

Value X is added to (Rn) to produce address of
operand.
Neither X nor (Rn) is modi fwd.

1-4

INSTRUCTION

OPERAND
MIII-_

Figure 7-3 Mode 0 Register

INSTRUCTION

OPERAND

ADDRESS

+2 FOR WORD.
+t FOA. BYTE

Figure 7-4 Mode 2 Autoincrement

INSTRUCTION

1---"

-2 FOR WORD.
-1 FOR BYTE

OPERAND

-Figure 7-5 Mode 4 Autodecrement

INnR~'ON t___
t-

A_D_D_R_ESS
__

Figure 7-6 Mode 6 Index

7-5

.......OP_E_R_A_N_D--I

7.2.3.1 Register Mode (Mode 0) - With register mode, any of the general-purpose registers may be used
as simple accumulators, and the operand is contained in the selected register. Because they are hardware
registers. within the processor, the general-purpose registers operate at high speeds and provide speed
advantages when used for operating on frequently accessed variables. The assembler interprets and
assembles instructions in the fonowing form as register mode operations.
OPR Rn

Rn represents a general-purpose register name or number, and OPR represents a general instruction
mnemonic. Assembler syntax requires that a general-purpose register be defined as follows.
RO = %0 (The '%' sign indicates register definition.)
Rl == %1
R2 "'" %2, etc.
Registers are typically referred to by name as RO, Rl, R2, R3, R4, R5, R6, and R7. However, R6 and R7
are also referred to as SP and PC, respectively.
Register Mode Examples (Figures 7-7, 7-8, and 7-9)
(all numbers in octal)

Symbolic

Octal Code

Instruction
Name

INC R3

005203

Increment

One is added to the contents of the general-purpose register R3.

o : 0

1 :

'--_ _ _ _..........II........I_--l._-..l._--io_......_
~~

Operation

......_

__________________v-________________

I I

00
:

~,I

......._....I.._...L._-'-_-r.._..........,.,

~A~

_ _ _ _ _ _ _ _ _ _v -________

OP CODE (lNC(0Q5211

SELECT

I
I

DESTINATION FIELD

RO
Rt

R2
R3

1
I
I

I
I

.... J

AS ($Pi
R7 (PCI
""·5481

Figure 7-7

7-6

INC R3

IBStruction
SymlJolie

OdaJ Code

Name

Operation

ADD R2, R4

060204

Add

The contents of R2 are added to the con~
tents of R4.

AFTER

BEFORE

Rli 000002

R21

000002

A41

R4(

000006

000004

MR·6468

Figure 7-8 ADD R2,R4

Instruction

Symbolic

Octal Code

Name

Operation

COMB R4

105104

Complement

Complement bits 0-7 (byte) of one in R4.
(When general-purpose registers are used.
byte instructions only operate on bits 0-7;
i.e., byte 0 of the register.)

byte

AfTER

BEFORE

R41

022222

R4(

022155

Figure 7-9 COMB R4

7-7

1.1.3.1 Autoincrement Mode (Mode 2) - Autoincrement mode allows automatic stepping of a pointer
through sequential elements of a table of operands. It assumes that the content of the selected generalpurpose register is the address of the operand. Contents of registers are stepped (by one for bytes, by two
for words. and by two for R6 and R7) to address the next sequential location.. The autoincrement mode is
especially useful for array processing and stack processing; it accesses an element of a table and then steps
the pointer to address the next operand in the table. Although most useful for table handling. this mode is
general and may be used for a variety of purposes. The assembler interprets and assembles instructions in
the following form as autoincrement mode operations.

OPR (Rn)+
Autoincrement Mode Examples (Figures 7-10, "7~1I. and 7-12)

Instruction

Symbolic

Octal Code

Name

Operation

ClR (R5)+

005025

Clear

The contents of R5 are used as the
address of the operand. The selected operand is cleared, and the contents of R5 are
then incremented by two.

BEfORE

AFTER

7lI ~5 !I

30000

ADDRESS SPACE

200001

030000

111~116

30000

Figure 7-10

Symbolic

Octal Code

Instruction
Name

ClRB (RS)+

105025

Clear byte

7-8

005025

I Rsl

030002

·1 000000

CLR (R5)+

Operation
The contents of RS are used as the
address of the operand. The selected byte
operand is cleared. and the contents of R5
are then incremented by one.

BEFORE

AFTER

ADDRESS SPACE

20000

R51

105025

030000

. ADDRESS SPACE

2<XXX)

105025

I 030001 ·1

I
t
30000

111

~~
30002~

I 116

30002

011'1·_

Figure 7-11

CLRB (R5)+

blstructlon
Symholic

Octal Code

Name

Operation

ADD (R2)+.R4

062204

Add

The contents of R2 are used as the
address of the operand that is added to
the contents of R4. R2 is then incremented by two.

AFTER

BEFORE

ADDRESS SPACES

ADDRESS SPACE

10000

062204

10000

062204

R41 010000
100002 (

010000

REGISTERS

R21

100004

R41 020000
1000021

010000
""·5470

Figure 7-12 ADD (R2)+,R4

7-9

7.1.3.3 Autodecrement Mode (Mode 4) - Autodecrement mode is useful for processing data in a list in
reverse direction. The contents of the selected general-purpose register are decremented (by two for word
instructions, by one for byte instructions) and then used as the address of the operand. The choice of
postincrement. predecrement features for the SBC-ll /21 PLUS are not arbitrary; they are intended to
facilitate hardware/software stack operations. The assembler interprets and assembles instructions in the
following form as autodecrement mode operations.
OPR -(Rn)

Autodecrement Mode Examples (Figures 7-13, 7-14, and 7-15)

Symbolic

Octal Code

Instruction
Name

INC -(RO)

005240

Increment

BEFORE
ADDRESS SPACE

005240

177741

00000o

1000

Operation
The contents of RO are decremented by
two and used as the address of the operand. The operand is incremented by one.

AFTER
ADDRESS SPACE

REGISTERS

017776

005240

177741

000001

1000

~
"

017774

Figure 7-13 INC -(RO)

•

Symbolic

Octal Code

Instruction
Name

INCB -(RO)

105240

Increment byte

Operation
The contents of RO are decremented by
one and used as the address of the operand. The operand byte is increased by
one.

BEFORE

AFTER
REGISTER

ADDRESS SPACE

1000

177141. ~

17776

t06240

ADDRESS SPACE

017776

I~ I
I

1000 [

105240

17774

•

011775

001 I 000

17776
MR-6471

Figure 7-14

INCB -(RO)

Instruction

Symbolic

Octal Code

Name

Operation

ADD -(R3),RO

064300

Add

The contents of R3 are decremented by
two and then used as a pointer to an operand (source) which is added to the con·
tents of RO (destination operand).

AFTER

BEFORE
ADDRESS SPACE

10020

064300

RO (

000020

Rli

077776

ADDRESS SPACE

10020

064300

St==]

77774~

77774

77776c=J

77776

Figure 7·15

OOOOSO

ADD -(R3),RO

7-11

0000070

Rli

077774

1.2.3.4 Index Mode (Mode 6) - With index mode, the contents of the selected general-purpose register
and an index word following the instruction word are summed to form the address of the operand. The
contents of the selected register may be used as a base for calculating a series of addresses, thus allowing
random access to elements of data structures. The selected register can then be modified by the program
to access data in the table. Index addressing instructions are in the following form:
OPR X(Rn)

where X is the indexed word and is located in the memory location following the instruction word, and Rn
is the selected general-purpose register.
Index Mode Examples (Figures 7-16, 7-17, ahd 7-18)

Symbolic

Octal Code

CLR 2oo(R4)

005064
000200

Instruction
Name

Operation

Clear

The address of the operand is determined
by adding 200 to the contents of R4. The
operand location is cleared.

BEFORE
ADDRESS SPACE

1020

1022
1024

1200
1202

AFTER
REGISTER

ADDRESS SPACE

1020

001000

000200

1022
1000

1024

+200

1200

001000

000200

~
MF\·5473-

Figure 7-16

Symbolic

Octal Code

Instruction
Name

COMB 200(R 1)

105161
000200

Complement
byte

CLR 200(R4)

7-12

Operation
The contents of a location that is deter~
mined by adding 200 to the contents of
R 1 are one's complemented (i.e., logically
complemented).

AHER

BEFORE
ADDRESS SPACE
REGISTER

1020
1022

20176
20200

000200

017777

ADDRESS SPACE

1020
1022

017777
+200
020177

lo~'iml

20176
20200

017777

000200

1'~! ~ I
MR·7230

Figure 7·17

COMB 200(R 1)

Instruction
Symbolic

Octal Code

Name

Operation

ADD 30(R2),20(R5)

066265
000030
000020

Add

The contents of a location that
is determined by adding 30 to
the contents of R2 are added to
the contents of a location that is
determined by adding 20 to the
contents of R5. The result is
stored at the destination
address, i.e., 20(R5).

AFTER

BEFORE
ADDRESS SPACE

1020
1022
1024

1130

2020

001100

1020

066265

1022

000030

1024

000020

000001

1130

000001

2020

000002

000030

000020

ADDRESS SPACE

002000

001100

.002000

I
I

1100 2000

+30

+20

1130

2020
MA·$A16

Figure 7-18

ADD 30(R2),20(RS)

7.1.4 Deferred (Indirect) Addressing
The four basic modes may also be used with deferred addressing. In the register mode, the operand is the
content of the selected register; in the register deferred mode, the content of the selected register is the
address of the operand. In the three other deferred modes, the contents of the register select the address of
the operand rather than the operand itself. Therefore, these modes are used when a table consists of
addresses rather than operands. Assembler syntax for indicating deferred addressing is '@' (or <0' when
this is not ambiguous). Table 7-3 summarizes the deferred versions of the basic modes. Figures 7-19, 7-20,
7-21, and 7-22, which follow the table, illustrate these deferred versions of the basic modes.

Table 7-3 Indirect Addressing Modes
Assembler
Syntax

Function

@Rn or (Rn)

Autoincrement
deferred

@(Rn)+

Register is first used as a pointer to a word containing the address of the operand and then incre*
men ted (always by two, even for byte instructions),

Autodecrement
deferred

@-(Rn)

Register is decremented (always by two, even for
byte instructions) and then used as a pointer to a
word containing the address of the operand.

Index
deferred

@X(Rn)

Value X (stored in a word following the instruction)
and (Rn) are added, and the sum is used as a
pointer to a word containing the address of the
operand. Neither X nor (Rn) is modified.

Mode

Name

IINSTRUCTlON

ADDRESS

OPERAND
Ml'!.6418

Figure 7*19

INSTRUCTION

Mode I Register Deferred

ADDRESS

OPERAND

MA-5417

Figure 7-20 Mode 3 Autoincrement Deferred

-2

INSTRUCTION

ADDRESS

OPERAND

""'H4111

Figure 7-21

INSTRUCTION

Mode 5 Autodecrement Deferred

ADDRESS
ADDRESS

OPERAND

x
MfH47Q

Figure 7-22

Mode 7 Index Deferred

Symbolic

Octal Code

Instruction
Name

CLR @R5

005015

Clear

Operation
The contents of the location specified in
R5 are cleared.

BEFORE

ADDRESS SPACE
1677

1700

AFTER

ADDRESS SPACE

001700

1677

1700

Figure 7-23

001]00

MII-6460

CLR @R5

Autoincrement Deferred Mode Example - Mode 3 (Figure 7-24)

Symbolic

Octal Code

Instruction
Name

INC @(R2)+

005232

Increment

7-J 5

Operation
The contents of R2 are used as the
address of the address of the operand.
The operand is increased by one; and the
contents of R2 are incremented by two.

BEFORE
ADDRESS SPACE

1010

1012

AFTER
REGISTER

ADDRESS SPACE

R2
1010

1012

010302

MA·1231

Figure 7·24

INC ®(R2)+

Autodecrement Deferred Mode Example - Mode 5 (Figure 7-25)

Symbolic

Octal Code

Instruction
Name

COM @-(RO)

005150

Complement

Operation

BEFORE
ADDRESS SPACE

10100
10102

10774

10776

B
B

010776

r=g
r=g

AFTER

ADDRESS SPACE

The contents of RO are decremented by
two and then used as the address of the
address of the operand. Operand is one's
complemented
(Le.,
logically
complemented).

10100

10102

10774
10776

MA-1232

Figure 7-25

COM @ -(RO)

7-16

Index Deferred Mode Example - Mode 7 (Figure 7-26)

Instruction

Symbolic

Octal Code

Name

Opention

ADD @1OOO(R2),RI

06720'1
001000

Add

1000 and the contents of R2 are
summed to produce the address
of the address of the source
operand. The contents of the
source operand are added to the
contents of R I; the result is
stored in R 1.

BEFORE
ADDRESS SPACE

1020
1022
1024

1050

~
001000

AFTER
REGISTER

R1
R2

I
I

001234
000100

1020
1022
1024

1050

1100

ADDRESS SPACE

1100
1000
+100
1100

~
E3
t=3
001000

I
I

001236
000100

M" ....3

Figure 7-26

ADD @1OOO(R2),RI

7.1.5 Use of the PC as a General-Purpose Register
Although R7 is a general-purpose register. it doubles as the program counter for the microprocessor.
Whenever the processor uses the program counter to acquire a word from memory, the program counter is
automatically incremented by two to contain the address of the next word of the instruction being
executed or the address of the next instruction to be executed. (When the program uses the PC to locate
byte data. the PC is still incremented by two.)
The PC responds to all standard SBC-I 1/21 PLUS addressing modes. However, the PC provides advantages for handling· position independent code and unstructured data with four of these modes. When
utilizing the PC, these modes are 'termed immediate, absolute (or immediate deferred), relative, and
relative deferred. Table 7-4 provides a summary of these modes.

7-17

Table 7"" PC Register Addressing Modes

Mode

Name

Assembler
Syntax

Immediate

Operand follows the instruction.

Absolute

@#A

Absolute address of operand follows the
instruction.

Relative

Relative address (index value) follows the
instruction.

Relative
deferred

Function

Index value (stored in the word following the
instruction) is the relative address for the address
of the operand.

When a standard program is available to different users, the ability to load it into different areas of
memory and run it there is useful. The SBC-ll/21 PLUS can relocate a program efficiently using position
independent code (PIC) that is written using the PC addressing modes. If an instruction and its operands
are moved so that the relative distance between them is not altered, the same offset relative to the PC can
be used in all positions in memory. Thus, PIC usually references locations relative to the current location.
The PC also facilitates the handling of unstructured data. This is particularly true of the immediate and
relative modes.

7.2.5.1

Immediate Mode - Using the immediate mode is equivalent to using the autoincrement mode
with the PC. It provides time improvements for accessing constant operands by including the constant in
the memory location immediately following the instruction word. The assembler interprets and assembles
instructions in the following form as immediate mode operations.

OPR #n,DD
Immediate Mode Example (Figure 7-27)

Symbolic

Octal Code

ADD #lO,RO

062700
000010

Instruction
Name
Add

Operation
The value lOis located in the second
word of the instruction and is added to
the contents of RO. Just before this
instruction is fetched and executed. the
PC points to the first word of the instruction. The processor fetches the first word
and increments the PC by two. The
source operand mode is 27 (autoincrement the PC). Thus, the PC is used as a
pointer to fetch the operand (the second
word of the instruction) before being
incremented by two to point to the next
instruction.

7-18

AFTER

BEFORE
ADDRESS SPACE

1020

062700

"RO

1022

000010

ADDRESS SPACE

000020

1020

001020

1022

1024

062700

r 000030

001024

1024
MR.7233

Figure 7-27

ADD #1O,RO

7.2.5.2 Absolute Addressing - Using the absolute addressing mode is the equivalent of using the
immediate deferred or autoincrement deferred modes with the PC. The contents of the location following
the instruction are taken as the address of the operand. Immediate data is interpreted as an absolute
address (i.e., an address that remains constant no matter where in memory the assembled instruction is
executed). The assembler interprets and assembles instructions in the folloWing form as absolute addressing mode operations.

OPR@fl.A
Absolute Mode Examples (Figures 7-28 and 7-29)
Instruction

Symbolic

Octal Code

Name

operation

CLR @fl.ltOO

005037
001100

Clear

The contents of location 1100 are cleared.

AFTER

BEFORE
ADDRESS SPACE

005037

001100

ADDRESS SPACE

20
22

005037

t--_OO_'_'00_-fV

1100

1102

Figure 7-28

CLR @#1100

7-19

Instruction
Symbolic

Octal Code

Name

Operation

ADD @J'2000,R3

063703
002000

Add

The contents of location 2000
are added to R3.

AFTER
ADDRESS SPACE

BEFORE

ADDRESS SPACE
20

063703

002000

R3
PC

000500

063703

000020

002000

•

I
V I
R3

001000

000024

Figure 7-29

ADD @#2oo0,R3

Relative Addressing - The relative addressing mode is assembled as index mode using R7. The
base of the address calculation, which is stored in the second or third word of the instruction, is not the
address of the operand, but the number that, when added to the PC, becomes the address of the operand.
This mode is useful for writing position independent code because the location referenced is always fixed
relative to the PC. When instructions are to be relocated, the operand is moved by the same amount. The
assembler interprets and assembles instructions in the following forms as relative addressing mode
operations.

7.2.5.3

OPR A or OPR X(PC)
where X is the location of A relative to the instruction.
Relative Addressing Example (Figure 7-30)
Instruction
Symbolic

Octal Code

Name

Operation

INCA

005267
000054

Increment

To increment location A, contents of
memory location immediately following
instruction word are added to (PC) to produce address A. Contents of A are
increased by one.

AFTER

BEFORE

ADDRESS SPACE

1020

005267

T022

000054

ADDRESS SPACE

~ PC

1020

0005267

1022

000054

1024

1026

1100

000000

1024

1100

~ PC

000001

+54

~----------------l1oo

Figure 7-30

INC A

7.2.5.4

Relative Deferred Addressing - The relative deferred addressing mode is similar to the relative
mode. However, the second word of the instruction, when added to the PC, contains the address of the

address of the operand rather than the address of the operand. The assembler interprets and assembles
instructions in the following forms as relative deferred addressing mode operations.
OPR @A or OPR @X(PC)

where X is the location containing the address of A relative to the instruction.
Relative Deferred Mode Example (Figure 7·31)

Symbolic

Octal Code

CLR@A

005077
000020

Instruction
Name

Operation
The second word of instruction is added
to updated PC to produce address of
address of operand. The operand is
cleared.

Clear

7-21

AFTER

BEFORE
ADDRESS SPACE

1020
1022

005077

ADDRESS SPACE

1--- 2-0--t "PC
00-00
1024
+20

1024

1020

005077

1022

000020

1024

.r--------~---------1cM4

'~
10100

100001

1
Figure 7~31

1044

010100

10100

00000o

CLR @A

7.2.6 Use of tbe Stack Pointer as a General-Purpose Register
The processor stack pointer (SP. register R6) is the general-purpose register most often used for stack
operations related to program nesting. Autodecrement with register R6 pushes data onto the stack, and
autoincrement with register R6 pops data off the stack. Since the SP is used by the processor for interrupt
handling, it has a special attribute: autoincrements and autodecrements are always done in steps of two.
Byte operations using the SP in this way leave odd addresses unmodified.

7.3 INSTRUCTION SET
Specifications for each instruction in the SBC-Il/21 PLUS instruction set follow and include each
instruction's mnemonic, octal code, binary code, a diagram showing the format of the instruction, a
symbolic notation describing its execution and effect on the condition codes, a description, special
comments, and examples.
MNEMONIC: A mnemonic is indicated before each description. When the word instruction has a byte
equivalent. the byte mnemonic is also shown.
INSTRUCTION FORMAT: A diagram accompanying each instruction shows the octal op code, binary
op code, and bit assignments. In byte instructions, the most significant bit (bit 15) is always a one.
SYMBOLS: The following symbols are used in the instruction specifications.

= contents of

SS or src

= source address

DO or dst

= destination address

loc

= location

"'" becomes

= "is popped from stack"

= "is pushed onto stack"
7-22

= boolean AND

= boolean OR

'if

= exclusive OR

"'" boolean not

Reg or R

= register

= Byte

o for word

•

} for byte

= concatenated
7.3.1 Instruction Formats
The following formats include ali instructions used in the SSC-tI/21 PLUS. Refer to individual instruc
tions for more detailed information.
I.

CLR, CLRB, COM, COMB, INC, INCB. DEC,
DECB, NEG, NEGB, AOC, ADCB, SBC, SBCB,
TST, TSTB, ROR, RORB, ROL, ROLB, ASR,
ASRB, ASL, ASLB, JMP, SWAB, MFPS, MTPS,
SXT,XOR

Single operand group:

1
MA·5191

SIT, BITB, SIC, SICB, SIS, SISS, ADD, SUB, MOV,
MOVS, CMP, CMPS

Double operand group:

: : ~D

Program control group:
a.

Branch (all branch instructions)
08

Jump to subroutine (JSR)

05
:

Subroutine return (RTS)

MR-$19S

Traps (breakpoint, lOT, EMT, TRAP, BPT)
00

: :
MA-.til$6

Subtract I and branch if = 0 (SOB)

{)5

Operate group:

HALT, WAIT, RTI, RESET, RIT, NOP,MFPT

Condition code operators: (all condition code instructions)

MFH5J19S

Byte Instructions - The SBC-II /21 PLUS includes a full complement of instructions that manipulate
byte operands. Because all microprocessor addressing is byte-oriented, byte manipulation addressing is
straightforward. Byte instructions with autoincrement or autodecrement direct addressing cause the
specified register to be modified by one to point to the next byte of data. Byte operations in register mode
access the low-order byte of the specified register. These provisions enable the SBC-II /21 PLUS to
perform as either a word or byte microprocessor. The numbering scheme for word and byte addresseS in
memory is illustrated in Figure 7-32.

WORD OR BYTE

HIGH BYTE
ADDRESS

ADDRESS

002001

BYTE 1

BYTE 0

002000

002003

BYTE 3

BYTe 2

002002

Figure 7-32

Byte Instructions

The most significant bit (bit 15) of the instruction word is set to indicate a byte instruction.
Byte Instruction Example
Symbolic

Octal Code

Instruction Name

CLR
CLRB

0050DO
1050DD

Clear word
Clear byte

7.3.2 List of Instructions
The SBC-11/21 PLUS instruction set is shown in Table 7-5.

Table 7·5 SBC-1l/21 PLUS Instruction Set
Mnemonic

Instruction

Op Code

Clear dst
Complement dst
Increment dst
Decrement dst
Negate dst
Test dst

1105000
11051 DO
1105200
11053 DO
1105400
1105700

Arithmetic shift right
Arithmetic shift left
Rotate right
Rotate left
Swap bytes

1106200
1106300
1106000
1106100
000300

Add carry
Subtract carry
Sign extend

1I0550D
1105600
006700

Move byte from PS
Move byte to PS

106700
1064SS

Move source to destination
Compare src to dst
Add src to dst
Subtract src from dst

.ISSOO
.2SS00
06SS00
16SSDO

SINGLE OPERAND
General
CLR(B)
COM(B)
INC(B)
OEC(B)
NEG(B)

TST(B)
Shift & Rotate
ASR(B)
ASL(B)
ROR(B)
ROL(B)
SWAB
Multiple Precision
ADC(B)
SBC(B)

SXT
PS Word Operators
MFPS
MTPS
DOUBLE OPERAND
General
MOV(B)
CMP(B)
AOO
SUB

7·26

Table 7~S
Mnemonic

SBC·U/21 PLUS Instruction Set (Cont)

Instruction

OpCode

Bit test

.3SSDD
I14SSDD
.SSSDD
074RDD

Logical

BIT{B)
BIC(B)
BIS(B)
XOR

Bit clear
Bit set
Exclusive OR

PROGRAM CONTROL
Branch
BR

BNE
BEQ

BPL
BMI
BVe
BVS

sec
BeS

Branch (unconditional)
Branch if not equal (to zero)
Branch if equal (to zero)
Branch if plus
Branch if minus
Branch if overflow is clear
Branch if overflow is set
Branch if carry is clear
Branch if carry is set

000400
001000
001400
100000
100400
102000

102400
103000

103400

Signed Conditional Branch

8GE

BLT
BOT
BLE

Branch if greater than or equal (to zero)
Branch if less than (zero)
Branch if greater than (zero)
Branch if less than or equal (to zero)

Unsigned Conditional Branch
BHI
Branch if higher
BLOS
Branch if lower or same
BHIS
Branch if higher or same
BLO
Branch if lower
Jump & Subroutine
JMP
JSR
RTS
SOB
Trap & Interrupt
EMT

TRAP
BPT
lOT
RTI

RTT

Jump
Jump to subroutine
Return from subroutine
Subtract one and branch (if
Emulator trap
Trap
Breakpoint trap
Input/output trap
Return from interrupt
Return from interrupt

002000

002400
003000
003400
101000

101400
103000
103400

*' 0)

ooo1DD
oo4RDD
00020R
077ROO
104000-104377
104400-104777
000003
000004
000002
000006

Table 7-5
Maemonie

SBC-t 1/21 PLUS Instruction Set (Cont)

Instruction

Op Code

Halt
Wait for interrupt
Reset external bus
Move processor type

000000
000001
000005
000007

MISCELLANEOUS
HALT

WAIT
RESET

MfPT

RESERVED INSTRUCTIONS

00021R
00022R
CONDITION CODE OPERATORS

000241
000242
000244
000250
000257
000261
000262
000264
000270
000277
000240

Clear C
Clear V
Clear Z
Clear N
Clear all CC bits
Set C
Set V
Set Z
Set N
Set aliCe bits
No operation

CLC
CLY
CLZ
CLN
CCC
SEC
SEV
SEZ
SEN
see

NOP

7.3.3 Single Operand Instructions
NOTE
In most SBC- t 1/21 PLUS instructions, a write
operation to a memory location or register is always
preceded by a read operation from the same location
except when writing PC and processor status (PS) to
the stack in the following two cases.

The execution of the microcode preceding an
interrupt or trap service routine.

Interrupt and trap instructions:
HLT
TRAP

BPT
lOT

7-28

7.3.3.1 General-

Cl,R
CLRB
Clear Destination
06

MF\.S202

(dst) ;- 0

Operation:
Condition Codes:

N: cleared

Z: set
V:
C:
Description:

cleared
cleared

Word:
Byte:

Contents of specified destination are replaced with zeros.
Same

CLR Rl

Example:
Before
(R 1) = 177777

(R I) = 000000

After

NZVC

o100

1 I 1 1

COM
COMB
1I051DD

Complement Destination

0/< 0 : 0 : 0 : 1 : 0 : 1 : 0 : 0 : 1

05
d

d
MR·52fl;)

Operation:

(dst) <- -- (dst)

Condition Codes:

N: set if most significant bit of result is set; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared

set

Description:

Word:
Byte:

The contents of the destination address are replaced by their logical
complement (each bit equal to zero is set. and each bit equal to one
is cleared),
Same

COMRO

Example:
Before
(RO) = 013333

After
(RO) == 164444

NZVC

NZVC
100 1

o1 10

INC
INCB

1105200

Increment Destination
15

Q/< 0 : 0 : 0 : 1 : 0 : 1 : 0 : 1 : 0
Operation:

(dst) ;- (dst) + I

Condition Codes:

N:
Z:
V:
C:

Description:

Word:
Byte:

05
d

00
:

set if result < 0; cleared otherwise
set if result = 0; cleared otherwise
set if (dst) held 077777; cleared otherwise
not affected
One is added to contents of destination.
Same

INC R2

Example:
Before
(R2) = 000333

NZVC

After
(R2) = 000334

NZVC

o0 0 0

000 0

7-30

DEC
DECD
_53DD

Decrement Destination
00

MR·5205

Operation:

(dst) <- (dst) -I

Condition Codes:

N: set if result < 0, cleared otherwise
Z: set is result = 0; cleared otherwise
V: set if (dst) was 100000; cleared otherwise
C: not affected

Description:

Word:
Byte:

One is subtracted from the contents of the destination.
Same

Example:

DEC R5
Before
(R5) = 000001

After
(R5) = 000000

NZVC

l 000

o10 0
NEG
NEGD
1105400

Negate Destination

i5
0/1 :

o : o : o :

o :

05
d

: : I
d

MR·I;'OO

Operation:

(dst) <- - (dst)

Condition Codes:

N: set if the result < 0; cleared otherwise
Z: set jf the result = 0; cleared otherwise
V: set if the result is 100000; cleared otherwise
C: cleared if the result is 0; set otherwise

Descri ption:

Word:

Byte:

The contents of the destination address are replaced by its two's
complement. JOoooo is replaced by itself (in two's complement
notation, the most negative number has no positive counterpart).
Same
NEG RO

Example:
Before

After

(RO) = 000010

(RO) = }77770

NZVC

o0 0 0

100 1

7-31

TST

TSTB
1I057DD

Test Destination
06

011: 0: 0: 0: 1: 0:
MR·l)',{01

Operation:

(dst) +- (dst)

Condition Codes:

N:
Z:
V:
C:

Description:

Word:

set if the result < 0; cleared otherwise
set if result = 0; cleared otherwise
cleared
cleared

Byte:

The condition codes Nand Z are set according to the contents of
the destination address, and the contents of the destination remain
unmodified.
Same
TST RI

Example:
Before
(R I) = 012340

NZVC

After
(Rl) = 012340

NZVC

o0 1 1

o 000

7.3.3.2 Shifts and Rotates - Scaling data by factors of two is accomplished with two shift instructions:
I.
2.

ASR - Arithmetic shift right
ASL - Arithmetic shift left

The sign bit (bit 15) of the operand is reproduced in shifts to the right. The low-order bit is filled with zero
in shifts to the left. Bits shifted out of the C-bit, as shown in the following examples, are lost.
The rotate instructions operate on the destination word and the C-bit as though they formed a 17-bit
circular buffer. These instructions facilitate sequential bit testing and detailed bit manipulation.

7-32

ASR
ASRB

.062DD

Arithmetic Shift Right
15
0<

06
0

d
MA·5208

Operation:

(dst) +- (dst) shifted one place to the right

Condition Codes:

N: set if the high-order bit of the result is set (result < 0); cleared otherwise
Z: set if the result = 0; cleared otherwise
V' loaded from the exclusive OR of the N-bit and C-bit (as set by the
completion of the shift operation)
C: loaded from the low-order bit of the destination

Description:

Word:
Byte:

All bits of the destination are shifted right one place. Bit 15 is
reproduced. The C-bit is loaded from bit 0 of the destination. ASR
performs signed division of the destination by two.
Same

Example:
WORD:

: :

I--D-

BYTE:
ODD ADDRESS

: t-B L.I-~:-..,.-:-; . .;. ; .;.:~:; ; .; -.:~I-GJ
os

r-:::J17

7-33

EVEN ADDRESS

ASL

ASLB
1I063DD

Arithmetic Shift Left
15

011:

05
d

00
:

Operation:

(dst) +-- (dst) shifted one place to the left

Condition Codes:

N: set if the high-order bit of the result is set (result < 0); cleared otherwise
Z: set if the result = 0; cleared otherwise
V: loaded with the exclusive OR of the N-bit and C-bit (as set by the
completion of the shift operation)
C: loaded with the high-order bit of the destination

Description:

Word:

Byte:

All bits of the destination are shifted left one place. Bit 0 is loaded
with a zero. The C-bit of the status word is loaded from the most
significant bit of the destination. ASL performs signed multiplication of the destination by two with overflow indication.
Same

Example:
WORD:

BYtt;:
,....-:.;15::...,-_,.---..,...OD_D_A.,..DD_R_ESS....-.....,.._~O:::.8-.

8-1

EVEN ADDRESS

ro&l..-.:::-,.---,----;;:~:~~I-o

ROR
RORD
8060DD

Rotate Right

Operation:

(dst) +- (dst) rotate right one place

Condition Codes:

N: set if the high-order bit of the result is set (result < 0); cleared otherwise
Z: set if aU bits of result = 0; cleared otherwise
V: loaded with the exclusive OR of the N-bit and C-bit (as set by the
completion of the rotate operation)
C: loaded with the low-order bit of the destination

Description:

Word:

Byte:

AU bits of the destination are rotated right one place. Bit 0 is loaded
into the C-bit, and the previous contents of the C-bit are loaded into
bit 15 of the destination.
Same

Example:
WORD:

BYTE:

s~------~~~·------~
15

II :

EV:EN

:1
M"·51:13

7-35

ROL
ROLH
Rotate Left

1106100

Operation:

(dst) .- (dst) rotate left one place

Condition Codes:

N: set if the high-order bit of the result word is set (result < 0); cleared
otherwise
Z: set if aU bits of the result word = 0; cleared otherwise
V: loaded with the exclusive OR of the N-bit and C-bit (as set by the
completion of the rotate operation)
C: loaded with the high-order bit of the destination

Description:

Word:
Byte:

All bits of the destination are rotated left one place. Bit 15 is loaded
into the C-bit of the status word, and the previous contents of the
C-bit are loaded into bit 0 of the destination.
Same

Example:
WORD:

DST

~~I~:~~~~~:~~:~:~~
BYTE:

E~EN

MR-5l15

7-36

SWAB
Swap Bytes

ooo3DD

[o: o: o: o: o: o: o: o: :
1

I : :
d

MR-521&

Operation:

Byte l/Byte 0 +- Byte O/Byte 1

Condition Codes:

N: set if the high-order bit of the low-order byte (bit 7) of the result is set;
cleared otherwise
Z: set if low-order. byte of result = 0; cleared otherwise
V: cleared
C: cleared

Description:

High-order byte and low-order byte of the destination word are exchanged
(destination must be a word address).

SWAB Rl

Example:
Before
(Rl) = 077777

After
(R 1) = 177577

NZVC

1 I } 1

000 0

7.3.3.3 Multiple Precision - It is sometimes necessary to do arithmetic on operands considered as
multiple words or bytes. The SBC-ll/21 PLUS makes special provisions for such operations with the
instructions ADC (add carry) and SBC (subtract carry) and their byte equivalents. For example, two 16bit words may be combined into a 32-bit double precision word and added or subtracted as shown in
Figure 7-33.
32-BITWORD
(~------------------------------~------------------------------~)

oPERANDr~'_______________A_l_______________1~i 1~15______________A_O______________~1
f~--------------------------------~------------------------------~)

OPEAANDr~'

1~i l~t5_______________

________________B_l_______________

RESULTIIo....-_ _ _

-J]

BO______________

;.:.t5:....-_ _ _ _ _ _ _ _ _ _ _ _ _----,0

---....I1 &....-1_ _ _----'I

Figure 7-33

Multiple Precision

7-37

Multiple Precision Example
The addition of -1 and -1 could be performed as follows:
-I - 37777717717
(R t) == 117177 (R2) "'" 177777 (R3) = 177777 (R4) "" 177177
ADD Rl.R2
AOCR3
ADD R4.R3
I.
2.

3.
4.

After (R 1) and (R2) are added, I is loaded into the C-bit
ADC instruction adds C-bit to (R3); (R3) = 0
(R3) and (R4) are added
Result is 37717777776 or -2

ADC
ADCB
Add Carry

.a55DD
06

f 0/1 : o : o : o : 1 :

o :

: :o :
1

Operation:

(dst) -- (dst) + (C-hit)

Condition Codes:

N:
Z:
V:
C:

Description:

Word:

st':t if result < 0; cleared otherwise
set if result = 0; cleared otherwise
set if (dst) was 077777 and (C) was 1; cleared otherwise
set if (dst) was 177777 and (C) was 1; cleared otherwise

Byte:
Example:

The contents of the C-bit are added into the destination. This
permits the carry from the addition of the low-order words to be
carried into the high-order result.
Same

Double precision addition is done with the following instruction sequence:
ADD AO,80
ADC BI
ADD AI,BI

add low-order parts
add carry into high order
add high-order parts

7-38

SBC
SBCB

1I0560D

Subtract Carry
15

o :

1 :

o :

08
:

:oI

d :

MRAj.219

Operation:

(dst) -(dst) - (C)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if (dst) was 100000; cleared otherwise
C: set if (dst) was 0 and C was I; cleared otherwise

Descri ption;

Word:

The contents of the C-bit are subtracted from the destination. This
permits the carry from the subtraction of two low-order words to be
subtracted from the high-order part of the result.
Same

Byte:

Double precision subtraction is done with the following instruction sequence:

Example:

SUB AO,BO
SBC Bl

SUB AI,Bl

SXT
Sign Extend

006700
06

I o: o: o:

o :

1 :

05
d

00
:

"'R·~220

0 if N-bit is clear
1 if N-bit is set

Operation:

(dst) (dst) -

Condition Codes:

N: unaffected
Z; set if N-bit is clear
V: cleared
C: unaffected

Description:

If the condition code bit N is set, a -1 is placed in the destination operand; if
the N-bit is clear, then a zero is placed in the destination operand. This
instruction is particularly useful in multiple precision arithmetic because it
permits the sign to be extended through multiple words.
SXTA

Example:
Before

(A) = 012345

After
(A) = 177777

NZVC

} 000

I 0 0 0

7.3:3.4 PS Word Operators -

MFPS
Move Byte from Processor Status (PS)

J067DD
08

I :5: • : 0 : • : 1 : 1 :

MI'U221

Operation:

(dst) <- PS
dst lower 8 bits

Condition Codes:

N: set if PS bit 7 = I; cleared otherwise
set if PS <0:7> = 0; cleared otherwise
V: cleared
C: not affected

Description:

The 8-bit contents of the PS are moved to the effective destination. If the
destination is mode 0, PS bit 7 is sign extended through the upper byte of the
register. The destination operand address is treated as a byte address.
MFPS RO

Example:

RO [0]

After
RO {OOOOI4)

PS [000014]

PS [000000)

Before

MTPS
I064SS

Move Byte to Processor Status
15

t 1 : 0 : 0 : 0

: I
1

07
0

: 0

: s

s
MR·S222

Operation:

PS +- (src)

Condition Codes:

Set according to effective source operand bits 0-3

Description:

The 8 bits of the effective operand replace the current contents of thePS.
The source operand address is treated as a byte address. The T-bit (PS bit 4)
cannot be set with this instruction. The source operand remains unchanged.
This instruction can be used to change the priority bits (PS bits 7-5) in the
PS.

7-40

7.3.4 Double Operand Instructions
Double operand instructions save instructions and time because they eliminate the need for foad and save
sequences such as those used in accumulator-oriented machines.
7.3.4.1

General-

MOV
MOVB
.1SSDD

Move Source to Destination

I ::,:

Operation:
Condition Codes:

:'1 :' : ' : ' : ' : ' :~

(dst) <- (src)
N: set if (src) < 0; cleared otherwise
Z: . set if (src) = 0; cleared otherwise

V:
C:
Description:

cleared
not affected

Word:
Byte:

Example:

The source operand is moved to the destination location, The previ~
ous contents of the destination are lost. The contents of the source
address are not affected.
Same as MOV. The MOVB to a register (unique among byte
instructions) extends the most significant bit of the low-order byte
(sign extension). Otherwise. MOVB operates on bytes exactly as
MOV operates on words.

MOV XXX,RI

loads register 1 with the contents
of memory location; XXX represents a programmer-defined mnemonic used to represent a
memory location

MOV #20,RO

loads the number 20 into register
0; '#' indicates that the value 20
is the operand

MOV @#20,-(R6)

pushes the operand contained in
location 20 onto the stack

MOV (R6)+,@#1775.66

pops the operand off a stack and
moves it into memory location
177566 (terminal print buffer)

MOV Rl,R3

performs an inter-register
transfer

MOVB @# 177 562,@# 177 566

moves a character from terminal
keyboard buffer to terminal
printer buffer

CMP
CMPB
Compare Source to Destination
15

f 011: 0: 1: 0 IS: s :

Sid: d : d : d : d : d J

Operation:

(src) - (dst)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if there was arithmetic overflow; that is, operands were of opposite
signs and the sign of the destination was the same as the sign of the
result; cleared otherwise
C: cleared if there was a carry from the most significant bit of the result:
set otherwise

Description:

Word:

Byte:

The source and destination operands are compared. and the condi~
tion codes are set. The condition codes may then be used for
arithmetic and logical conditional branches. Both operands are
unaffected. The only action is to set the condition codes. The
compare is customarily followed by a conditional branch instruc~
tion. Unlike the subtract instruction, the order of operation is (src)
- (dst). not (dst) - (src).
Same

ADD
Add Source to Destination
15

06SSDD
06

"'1'1-5225

Operation:

(dst) ....... (src) + (dst)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if there was arithmetic overflow asa result of the operation; that is,
both operands were of the same sign and the result was of the opposite
sign; cleared otherwise
C: set if there was a carry from the most significant bit of the result;
cleared otherwise

7-42

Description:

The source operand is added to the destination' o~rand and the
result is stored at the destination address. The original contents of
the destination are lost. The contents of the source are not affected.
Two's complement addition is performed.
There is no equivalent byte mode.

Word:

Byte:
Example:

ADD 20,RO
ADD Rl,XXX
ADD Rl.R2
ADD @#17750,XXX

add to register
add to memory
add register to register
add memory to memory

XXX is a programmer-defined mnemonic for a memory location.

SUB
16SSDD

Subtract Source from Destination
12

15
1

I :
s

: : :
s

05
d

M,,·ene

Operation:
Condition Codes:

(dst) t - (dst) - (src)

N: set if result < 0; cleared otherwise
Z:

V:
C:
Description:

set if result = 0; cleared otherwise
set if there was arithmetic overflow as a result of the operation, that is if
operands were of opposite signs and the sign of the source was the same
as the sign of the result; cleared otherwise
cleared if there was a carry from the most significant bit of the result;
set otherwise

Word:

Byte:

The source operand is subtracted from the destination operand, and
the result is left at the destination address. The original contents of
the destination are lost. The contents of the source are not affected.
In double-precision arithmetic, the C-bit, when set, indicates a
borrow.
There is no equivalent byte mode.

Example:

SUB RI,R2
Before

(R 1) = 01 I III

(R2) = 012345

After
(R I) = 011111
(R2) =< 001234

NZVC

1 1 I 1

000 0

7·43

.7.3.4.2 Logical - Logical group instructions have the same format as the double operand arithmetic
group. They permit operations on data at the bit level.

BIT
BITB
Bit Test

.3SSDD
12

0/': 0 : 1 : 1

00
:

~R"6221

Operation:

(sre) 1\ (<ist)

Condition Codes:

N: set if high-order bit of result is set; cleared otherwise
Z: set if result :: 0; cleared otherwise
V: cleared
C: not affected

Description:

Word:

Logical "and" comparison of the source and destination operands is
performed, and condition codes are modified accordingly. Neither
the source nor destination is affected. The BIT instruction may be
used either to test whether any of the corresponding bits that are set
in the destination are also set in the source or whether aU corresponding bits set in the destination are clear in the source.
Same

Byte:
Example:

test bits three and four of R3 to see if both are off

BIT nO,R3

R3 =0000 000000 011 000
Before

After

NZ VC

NZVC
o 00 1

1 I 1 1

DIC
BleB

Bit Clear

I14SSDD
15

, 0/<

: 0

06
:

: s

05
d

MA.b22"

Operation:

(dst) <- (<1st)

Condition Codes:

N:
Z:
V:
C:

- (src)

set if l1igh-order bit of result is set; cleared otherwise
set if result = 0; cleared otherwise
cleared
not affected

Descri ption:

Word:
Byte:

Each bit in the destination that corresponds to a set bilin the source
is cleared. The original contents of the destination are lost. Tne
contents of the source are not affected.
Same
BIC R3,R4

Example:
Before
(R3) = 001234
(R4) = 001111

After
(R3) = 001234
(R4) = 000101

NZVC

111 1

000 I

Before:

(R3) "'" 0 000 001 010 011 100
(R4) = 0 000 001 001 001 001

After:

(R4) = 0 000 000 001 000 001

BIS
BIS8
.SSSDD

Bit Set
06

011: 1

: s

Operation:

(dst) -

Condition Codes:

N:
Z:
V:
C:

Description:

Word:

05
d

"'''.52211

(dst) V (src)

set if high-order bit of result is set, cleared otherwise
set if result = 0; cleared otherwise
cleared
not affected

Byte:

Inclusive OR operation is performed between the source ami destination operands, and the result is left at the destination address (i.e.,
corresponding bits set in the source are set in the destination). The
contents of the destination are Jost.
Same

BIS RO,RI

Example:
Before
(RO) = 001234
(Rl) - 001111

NZVC

After
(RO) = 001234
(RI) "'" 001335

NZVC

o0 0 0

Before:

(RO) ... 0000 001 010011 100

After:

(RI) = 0000001 011 011 101

(Rl) = 0000001 001 001 001

7-45

XOR
Exclusive OR

074RDD

MA.sno

Operation:

(dst) - (dst) V (Reg)

Condition Codes:

N: set if the result < 0; cleared otherwise
Z: set if result == 0; cleared otherwise
V: cleared
. C: unaffected

Description:

The exclusive OR of the register and destination operand is stored in the
destination address. Contents of register are unaffected. Assembler format is:
XOR~D.
.

Example:

XOR RO,R2

Before
(RO) == 00 1234
(R2) == OOlll1

NZVC

After
(RO) == 001234
(R2) - 00032S

NZVC

1 tIl

000 I

Before:

(RO) .... 0 000 001 010011 100
(Rl) == 0 000 001 001 001 001

After:

(R2) == 0 000 000 011 010 101

7.3.5 Program Control lastl'lldica
7.3.5.1 Branches - Program control instructions cause a branch to a location defined by the sum of the
offset (multiplied by two) and the current contents of the program counter if:
I.

The branch instruction is unconditional.

The branch' instruction is conditional, and the conditions are met after testing the condition
codes (NZVC).

The offset is the number of words from the current contents of the PC forward or backward. The current
contents of the PC point to the ~ord fQUowing the branch instruction.

7-46

Although the offset expresses a byte address, the PC is expressed in words. Before it is added to the PC,
the offset is automatically multiplied by two and sign extended to express words. Bit 7 is the sign of the
offset. If it is set, the offset is negative and the branch is done in the backward direction. Similarly, if bit 7
is not set, the offset is positive and the branch is done in the forward direction.
.
The 8-bit offset allows branching in the backward direction by 2008 words (400 bytes) from the current
PC, and in the forward direction by 1778 words (376 bytes) from the current PC.
The microprocessor assembler handles address arithmetic for the user and computes and assembles the
proper offset field for branch instructions in the following form.
Bxx loe
where Bxx is the branch instruction and loc is the address to which the branch is to be made. The
assembler' gjv~ an error indication in the instruction if the permissible branch range is exceeded. Branch
instructions have no effect on condition codes. Conditional branch instructions, where the branch condition
is not met,are treated as NO OPs.

BR
Branch (Unconditional)

I :':

000400 Plus Offset

MA·523,

PC + (2 X offset)

Operation:

PC -

Condition Codes:

Unaffected

Description:

A way of transferring program control within a range of -12810 to +127to
words with a one-word instruction is provided.
New PC address == updated PC + (2 X offset)
Updated PC = address of branch instruction +2

Example:

With the branch instruction at location 500, the following offsets apply.
New PC Address

Offset Code

Offset (decimal)

474
476

375
376
377

-2
-1

500
502
504
506

7-47

-3

000

001
,002

+1
+2

BNE
Branch If Not Equal (to Zero)

00 1000 Plus Offset

:::

Operation;

PC *- PC + (2 X offset) if Z - 0

Condition Codes;

Unaffected

Description:

The state of the Z-bit is tested. and a branch is caused if the Z-bit is clear.
BNE is the complementary operation to BEQ. BNE is used to test inequality
fonowing a CMP. to test that some bits set in the destination were also in the
source following a BIT operation. and generally. to test that the result of the
previous operation was not zero.

Example:

CMP A,B

compare A and B
branch if they are not equal

BNEC
will branch to C if A oF B
and the sequence
ADD A,B
BNEC

add A to B

branch if the result is not equal toO

will branch to C if A + B = 0

BEQ
001400 Plus Offset

Branch If Equal (to Zero)

:':

1 :

1011\6233

Operation:"

PC +- PC + (2 X offset) if Z == 1

Condition Codes:

Unaffected

Description:

The state of the Z-bit is tested and a branch is caused if Z is set. BEQ is used
to test equality following a CMP operation, to test that no bits set in the
destination were also set in the source following a BIT operation. and generally, to test that the result of the previous operation was zero.

7-48

Example:

CMPA,B
BEQC

compare A and B
branch if they are equal
(A - B = 0)

will branch to C if A = B
and the sequence

add A to B
branch if the result = 0

ADD A,B
BEQC

will branch to C if A + B = 0

BPL
100000 Plus Offset

Branch If Plus
08

15
1

o : o : o : o : o : o : o

OFF:SET
MA~S:234

Operation:

. PC +- PC + (2 X offset) if N = 0

Condition Codes:

Unaffected

Description:

The state of the N-bit is tested, and a branch is caused if N is clear (positive
result), BPL is the complementary operation of BMI.

8MI
Branch If Minus

100400 Plus Offset
08

Operation:

PC +- PC + (2 X offset) if N = 1

Condition Codes:

Unaffected

Description:

The state of the N-bit is tested. and a branch is caused if N is set. BMI is
used to test the sign (most significant bit) of the result of the previous
operation. branching if negative. BMI is the complementary function of BPL.

7-49

Bve
Branch If Overflow Is Clear

102000 Plus Offset
00

)
MII·52:11i

PC + (2 X offset) if V == 0

Operation:

PC -

Condition Codes:

Unaffected

Description:

The state of the V-bit is tested, and a branch is caused if the V-bit is clc;ar.

BVC is the complementary operation to BVS.

BVS

102400 Plus Offset

Branch If Overflow Is Set
08

MII·S237

PC + (2 X offset) if V = I

Operation:

PC -

Condition Codes:

Unaffected

Description:

The state of the V-bit (overflow) is tested, and a branch is caused if the V-bit
is set. BVS is used to detect arithmetic overflow in the previous operation.

ICC

Branch If Carry Is Clear

103000 Plus Offset
00

Operation:

PC - PC + (2 X offset) if C = 0

Condition Codes:

Unaffected

Description:

The state of the C-bit is tested, and a branch is caused if C is clear. BCC is
the complementary operation to OCS.

1-50

BCS
103400 Plus Offset

Branch If Carry Is Set
08

o : o : o : o :

: : I
1

OFF~ET
MA"5;l39

Operation:

PC +- PC + (2 X offset) if C = 1

Condition Codes:

Unaffected

Description:

The state of the C·bit is tested, and a branch is caused if C is set. BCS is used
to test for a carry in the result of a previous operation.

7.3.5.2 Signed Conditional Branches - Particular combinations of the condition code bits are tested with
the signed conditional branches. These instructions are used to test the results of instructions in which the
operands were considered as signed (two's complement) values.
The sense of signed comparisons differs from unsigned comparisons. In signed 16·bit (two's complement)
arithmetic, the sequence of values is as follows.
largest

077777
077776

positive

zero

000001
000000
177777
177776

negative
smallest

100001
100000

In unsigned 16-bit arithmetic, the sequence is as follows.
highest

171777

lowest

000002
000001
000000

BGE
Branch If Greater Than or Equal (to Zero)

002000 Plus Offset
08

: I
Operation;

PC -- PC + (2 X offset) if N '+.:f V = 0

Condition Codes:

Unaffected

Description:

A branch is caused if N and V are either both dear or both set. BGE is the
complementary operation to BLT, Thus, BGE will always cause a branch
when it follows an operation that caused addition of two positive numbers.
BGE will also cause a branch on a zero result.

BLT
002400 Plus Offset

Branch If Less Than (Zero)
08

Operation:

PC -- PC + (2 X offset) if N '+.:f V = I

Condition Codes:

Unaffected

Description:

A branch is caused if the exclusive OR of the N- and V-bits is one. Thus,
BLT will always branch following an operation that added two negative
numbers. even if overflow occurred. In particular, BLT will always cause a
branch if it follows a CMP instruction operating on a negative source and a
positive destination (even if overflow occurred). Further, BLT will never
cause a branch when it follows a CMP instruction operating on a positive
source and negative destination. BLT will not cause a branch if the result of
the previous operation was zero (without overflow).

7-52

BGT
Branch If Greater Than (Zero)

I :':

003000 Plus Offset
00

07
0

: 0

: :
MA-5242

Operation:

PC r - PC + (2 X offset) if Z V (N !,if V) := 0

Condition Codes:

Unaffected

Description:

Operation of BGT is similar to BGE, however, BGT will not cause a branch
on a zero result.

BLE
Branch If Less Than or Equal (to Zero)

003400 Plus Offset

Operation:

PC .- PC + (2 X offset) if Z V (N !,if V) """ 1

Condition Codes:

Unaffected

Description:

Operation is similar to BLT, however, BLE also will cause a branch ,if the
result of the previous operation was zero.

7.3.5.3 Unsigned Conditional Branches - The unsigned conditional branches provide a means to test the
.
results of comparison operations in which the operands are considered unsigned values.

BHI
Branch If Higher

101000 Plus Offset

08
:

o : o : o : o : o :

07
:

OFF~ET

I
"'''-$24<1.

PC + (2 X offset) if C = 0 and Z := 0

Operation:

PC -

Condition Codes:

Unaffected

Description:

A branch occurs if the previous operation did not cause a· carry or a zero
result. This will happen in comparison (CMP) operations as long as ~e so~
bas a higher unsigned value than the destination.

7-53

BLOS
Branch If Lower or Same

101400 Plus Offset
00

J
Operation:

PC ..... PC + (2 x offset) if C V Z "'" 1

Condition Codes:

Unaffected

Description:

A branch occurs if the previous operation caused either a carry or a zero
result. BLOS is the complementary o,peration to BHL The branch will occur
in comparison operations as long as the source is equal to, or has a tower
unsigned value than the destination.

8HIS
Branch If Higher or Same

103000 Plus Offset

J
Operation:

PC +- PC + (2 X offset) if C = 0

Condition Codes:

Unaffected

Description:

BHrs is the same instruction as BeC. This mnemonic is included for convenience only.

8W
Branch If Lower

103400 Plus Offset
08

I :
I

o : o : o : o :

: : I
1

Operation:

PC +- PC + (2 x offset) if C = I

Condition Codes:

Unaffected

Description:

BLO is the same instruction as BeS. This mnemonic is included for convenience only.

7.3.5.4 Jump and Subroutine Instructions - The subroutine call in the microprocessor provides for
automatic nesting of subroutines, re-entrance, and mUltiple entry points. Subroutines may call other
subroutines (or themselves) to any level of nesting without making special provisions for storage of return
addresses at each level of subroutine call. The subroutine calling mechanism does not modify any fixed
location in memory. and thus, provides for re-entrance. This allows one copy of a subroutine to be shared
among several interrupting processes.

JMP

OOOIDD

Jump
15

o : o : o : o : o : o : o : o : 0

00
:

MR·5248

Operation:

PC ~ (dst)

Condition Codes;

Unaffected

Description:

. More flexible program branching than that available with the branch instruc~
tions is provided. Control may be transferred to any location in memory (no
range limitation) and can be accomplished with· the fun flexibility of the
addressing modes, with the exception of register mode O. Execution of a jump
with mode 0 will cause an illegal instruction condition, and will cause the
CPU to trap to vector address 4; (Program control cannot be transferred to a
register.) Register deferred mode is legal and will cause program control to be
transferred to the address held in the specified register. Instructions are word
data and therefore, must be fetched from an even-numbered address.
Deferred index mode JMP instructions permit transfer of control to the
address contained in a selectable element of a table of dispatch vectors.

Example:
JMP FIRST

transfers to FIRST

JMP@LIST

transfers to location pointed
to at LIST
pointer to FIRST

First:
List:

FIRST

JMP@(SP)+

transfers to location pointed to by the top of the
stack and removes the pointer from the stack

JSR

Jump to Subroutine

004RDD

1< 0: 0: 0: ': .: 0] , : ' :' I d: d: d: d: d: dI
Operation:

(tmp) . . . . . (dst) (tmp is an internal processor register)

! (SP) . . . . . reg (push reg contents onto processor stack)
reg +- PC (PC holds location following JSR; this address is now put in reg)
PC -- Cdst) (PC now points to subroutine destination)
Condition Codes:

Unaffected

Description:

The old contents of the specified register (the linkage pointer) are automati- .
cally pushed onto the processor stack, and new linkage information is placed
in the register. Thus, subroutines nested within subroutines to any depth may
all be called with the same linkage register. There is no need either to plan the
maximum depth at which any particular subroutine will be called or to
include instructions in each routine to save and restore the linkage pointer.
Further, since aU linkages are saved in a re-entrant manner on the processor
stack. execution of a subroutine may be interrupted, and the same subroutine
re-entered and executed by an interrupt service routine. Execution of the
initial subroutine can then be resumed when other requests are satisfied. This
process (called nesting) can proceed to any level.

A subroutine called with a JSR reg,(dst) instruction can access the arguments
following the call with either autoincrement addressing, (reg)+, (if arguments
are accessed sequentially) or by indexed addressing. X(r~g). (if arguments are
accessed in random order). These addressing modes may also be deferred,
@(reg)+ and @X(reg), if the parameters are operand addresses rather than
the operands themselves.
JSR PC.(dst) is a special case of the microprocessor subroutine call and is
used for subroutine calls that transmit parameters through the general-purpose registers. The SP and the PC are the only registers that may be modified
by this call.
JSR PC.@(SP)+ is another special case of the JSR instruction. It exchanges
the top element of the processor stack and the contents of the program
counter. This instruction is used to allow two routines to swap program
control and resume operation when recalled where they left off. Such routines
are calledco-routines.
Return from a subroutine is done with the RTS instruction. RTS reg loads
the contents of reg into the PC and pops the top element of the processor
stack into the specified register.

7-56

Example:
R5
SBCALL
SBCALL+4

JSR R5, SBR
ARG 1
ARG2

SBCALL+2+2M
CONT

ARGM
NEXT INSTRUCTION

SBR

MOV(R5)+,dstl
MOV(R5}.f..,dst2

R6
n

R7
SBCALL

CONT

SBCALL+4

n-2

SBR

SBCALL+2+2M
CONT
CONT

n-2

EXIT

MOV(R5)+,dst2

EXIT

MOV(R5)+,dstM
OTHER INSTRUCTIONS
RTSR5

This example is illustrated in the following figure.

7·57

JSR RS, SeR

BEFORE:

(PCI

(SPI

AFTER:

I
I

SBR

STACK

OATAO

OAf A 0

I n-2

PC+2

JSR PC, SBA

BEFORE:

AfTER:

(PCI

R71

(SP)

STACK

DATA 0

S8R

(

0-2

DATA 0

PC+l

... ,,·$250

7-58

RTS

Return from Subroutine

00020R
03

Operation:

PC ..... (reg)
(reg) ..... (SP) T

Condition Codes:

Unaffected

Descri ption:

Contents of register are loaded into PC, and the top element of the processor
stack is popped into the specified register. Return from a nonre~entrant
subroutine is typically made through the same register that was used in its
call. Thus, a subroutine called with a JSR PC.(dst) exits with an RTS PC. A
subroutine called with a JSR RS,(dst) may pick up parameters with addressing modes (RS)+, X(R5), or @X(R5) and finally exit with an RTS RS.

Example:

RTSR5
RTS R5
BEFORE;

(PC)

STACK

SSR

DATA 0

(SP)

I
I

R71

n+2

AFTER:

DATA 0

MA-5702

SOB
Subtract One and Branch (If ::1= 0)

Operation;

077RNN

(R) - (R) - 1; if this result ::1= 0 then PC - PC - (2 X offset); if (R) == 0

then PC - PC
Condition Codes:

Unaffected

Description:

The register is decremented. If it is not equal to zero, twice the offset is
subtracted from the PC (now pointing to the following word). The offset is
interpreted as a 6-bit positive number. SOB provides a fast, efficient method
of loop control. The assembler syntax is:

SOB R,A
where A is the address to which transfer is to be made if the decremented R
is not equal to zero. The SOB instruction cannot be used to transfer control in
the forward direction.

7.3.5.5 Traps - Trap instructions provide for calls ·to emulators, I/O monitors, debugging packages, and
user-defined interpreters. A trap is effectively an interrupt generated by software. When a trap occurs the
contents of the current program counter (PC) and processor status (PS) are pushed onto the processor
stack and replaced by the contents of a two-word trap vector containing a new PC and PS. The return
sequence from a trap involves executing an RTI or RTf instruction that restores the old PC and PS by
popping them from the stack. Trap instruction vectors are located at permanently assigned fixed
addresses.

EMT

Emulator Trap

104000-104377
08

15
1

o : o : o :

o : o : 0

M"·UN

7-60

Operation:

1(SP);- PS
1 (SP) -- PC
PC;- (30)
PS;- (32)

Condition Codes:

N:
Z;
V:
C:

Description:

All operation codes from 104000 to 104377 are EMT instructions and may
be used to transmit information to the emulating routine (e.g., function to be
performed). The trap vector for EMT is at address 30. The new PC is taken
from the word at address 30, and the new processor status (PS) is taken from
the word at address 32.

loaded from trap vector
loaded from. trap vector
loaded from trap vector
loaded from trap vector

CAUTION
EMT is used frequently by Digital system software
and is not recommended fer general use.
Example:

pcl

PCl

STACK

DATA 1

(32)

BEFORE:

Sf!

AFTER:

I
(

1301

DATA 1

I n-4

I
I

PCl

PS 1

TRAP
Trap

104400-104777
15

1(SP) <- PS
1(SP) <- PC

Operation:

PC - (34)
PS -- (36)

Condition Codes:

N:
Z:
V:
C:

loaded from trap vector
loaded from trap vector
loaded from trap vector
loaded from trap vector

Description:

Operation codes from 104400 to 104777 are TRAP instructions. TRAP and
EMT instructions are identical in operation, however, the trap vector for
TRAP is at address 34.

NOTE
Because Digital software makes frequent use of
EMT, the TRAP instruction is recommended for
general use.

BPT
000003

Breakpoint Trap

I :':

7I
"'''-'5251

Operation:

1 (SP) <- PS
! (SP) -- OC
PC -- (14)
PS <- (16)

Condition Codes:

N:
Z:
V:
C:

loaded from trap vector
loaded from trap vector
loaded from trap vector
loaded from trap vector

Description:

A trap sequence with a trap vector address of 14 is performed. BPT is used to
call debugging aids. The user is cautioned against employing code 000003 in
programs run under these debugging aids.
(No information is transmitted in the low byte.)

7-62

lOT
Input/Output Trap

000004
00

MR·52118

1 (SP) -

.Operation:

! (SP) - PC
PC.- (20)
PS.- (22)

Condition Codes:

N:
Z:
V:
C:

Description:

A trap sequence with a trap vector address of 20 is performed.

loaded from trap vector
loaded from trap vector
loaded from trap vector
loaded from trap vector

(No information is transmitted in the low byte.)

RTI
Return from Interrupt

000002

0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0:0: 0: ': ': 01
Operation:

PC - (SP) T
(SP)T

PS -

Condition Codes:

N:
Z:
V:
C:

loaded from processor stack
loaded from processor stack
loaded from processor stack
loaded from processor stack

Description:

Used to exit from an 'interrupt or TRAP service routine. The PC and PS are
restored (popped) from tile processor stack.. If a trace trap is pendin& the rmt
instruction after RTI will not. be executed prior to the next T trap.

7-63

RTf
Return from Trap

000006

MR·5259

Operation:

PC -- (SP) T
PS;- (SP) T

Condition Codes:

N: loaded from processor stack
loaded from processor stack
V: loaded from processor stack
c: loaded from processor stack

Desert ption:

Operation is the same as RTI, however, RTI inhibits a trace trap while RTf
permits a trace trap. If new PS has T·bit set, trap win occur after execution
of first instruction after RTI.

7.3.5.6 Resened Instruction Traps - Reserved instruction traps are caused by attempts to execute
instruction codes reserved for future processor expansion (reserved instructions) or instructions with illegal
addressing modes (illegal instructions). Order codes not corresponding to any of the instructions described
are reserved instructions. JMP and JSR with register mode destinations are illegal instructions and trap to
vector address 4. Reserved instructions trap to vector address 10.
7.3.5.7 HALT Interrupt - The HALT interrupt is caused by the -HALT line. The -HALT interrupt
saves the PC and PS and goes to the restart address with PS = 340.
7.3.5.8 Trace Trap - The trace trap is enabled by bit 4 of the PS and causes processor traps at the end of
instruction execution. The instruction that is executed after the instruction that set the T-bit will proceed
to completion and then trap through the trap vector at address 14. The trace trap is a system debugging
aid and is transparent to the general programmer.
7.3.5.9 Power Failure Interrupt - The power failure interrupt occurs when -PF line is asserted. Vectors
for power failure are locations 24 and 26. Trap will occur if an RTI instruction is executed in a power fail
service routine.
.
7.3.5.10 Interrupts - See Table 5-3.

NOTE
Bit 4 of the processor status can only be set indirectly by executing an RTI or RTf instruction with the
desired PS on the stack.

7-64

7.3.5.11 Special Cases (T-bit) - The following are special cases of the T-bit.

NOTE
The' tnced instruction foUows the instruction that
sets the T -bit.

An instruction that cleared the T-bit - Upon fetching the traced instruction. an internal flag.
the trace flag, was set. The trap will still occur at the end of execution of this instruction. The
status word on the stack, however, will have a clear T-bit.

An instruction that set the T-bit - Because the T-bit was already set, setting it again has no
effect The trap will occur.

An instruction tbat caused an instruction trap - The instruction trap is performed, and the
entire routine for the service trap is executed. If the service routine exits with an RTI or in any
other way restores the stacked status word, the T-bit is set again, the instruction following the
traced instruction is executed, and, unless it is one of the special cases noted previously. a trace
trap occurs.

Interrupt trap priorities - When multiple trap and interrupt conditions occur simultaneously.
the following order of priorities is observed (from high to low).
1.

2.
3.
4.
5.
6.

Halt line
Power fail trap
Trace trap
.
Internal interrupt request
External interrupt request
Instruction traps

7.3.6 Miscellaneous Instructions

HALT
Halt

00000o

Operation:

1 (SP) 1 (SP) -

Condition Codes:

Unaffected

Description:

The processor goes to the restart address after placing the current' PC and PS
on the stack. PS is initialized to 340.,

PS,
PC
PC - restart address
PS - 340

7-65

WAIT
000001

Wait for Interrupt

0 :

0: 0:

0 :

1 )

Condition Codes:

Unaffected

Description:

In WAlT, as in all instructions, the PC points to the next instruction following the WAIT instruction. Thus. when an interrupt causes the PC and PS to
be pushed onto the processor stack, the address of the next instruction
following the WAIT is saved. The exit from the interrupt routine (i.e.,
execution of an RTl instruction) will cause resumption of the interrupted
process at the instruction following the WAIT.

RESET
Reset External Bus

000005

Condition Codes:

Unaffected

Description:

The -BCLR line is asserted and the mode register is loaded. -BCLR is
negated, and an ASPI transaction takes place. PC, PS, and RO-RS are not
affected.

MFPT
Move from Processor Type Word

I ~5:

000007
00

0
MA·7198

Operation:

RO-4

Condition Codes:

Unaffected

Description:

The number four is placed in RO telling the system software that the processor type is Micro/T-l L

7-66

7.3.7 Contlition Code Operators

CLN SEN
CLZSEZ
CLV SEV
CLCSEC
CCCSCC
ooo2XX

Condition Code Operators
05

W1\ N I z Iv Ie
Description:

Condition code bits are set and cleared. Selectable combinations of these bits
may be cleared or set together. Condition code bits corresponding to bits in
the condition code operator (bits 0-3) are modified according to the sense of
bit 4, the set/clear bit of the operator (i.e .• set the bit specified by bit 0, 1, 2,
or 3, if bit 4 is a one). Corresponding bits are cleared if bit 4 ... O.
Mnemonic

Operation

OP Code

CLC
CLV
CLZ
CLN
SEC
SEV
SEZ
SEN

Clear C
Clear V
Clear Z
Clear N
Set C
Set V
Set Z
SetN
Set all CCs
Clear all CCs
Clear V and C*
No operation

000241
000242
000244
000250
000261
000262
000264
000210
000277
000257
000243
000240

sec

CCC
NOP

"'Combinations of the above set or clear operations may be ORed together to form combined instructions. Clear V and C represents CLC (241) ORed with CLV (code 242).

7-67

CHAPTERS
THEORY OF OPERATION

8.1 1NTR0DUcnoN
This chapter provides an explanation of SOC-II /21 PLUS hardware operation from the perspective of the
logic designer. It is useful for troubleshooting the device to the chip level.
NOTE
The negated or inverse signal is designated by a
minus sip (-). For example, RAS is DOrmaUy low
and asserted laigh when activated; -RAS is normally
IOgh and asserted low when activated. nis con,ention is used throughout this chapter. The LSI-II bas
signals are consistent with tile standard bus conventions. AU gates prefaced with a G designation exist
within the gate array (£20).
The SOC-I 1/21 PLUS functional block diagram is shown in Figure 8-1 (sheets I and 2) and provides an
overview of the module functions and how they are related. The main components of the single-board
corDl'Uter are shown on sheet I of Figure 8-1. The single-board computer has a microprocessor interconnected to the serial line units, RAM memory, ROM memory, and the parallel I/O interface via the onboard TDAL bus. The TDAL bus can access the LSI-ll bus (BDAL bus) by the bus control function,
shown by broken lines, and is for reference only. The address bus, the memory address decode function,
and the interrupt control function are also shown on sheet I of Figure 8-1.

The microprocessor support functions and the LSI-II interface functions are described on sheet 2 of
Figure 8-1. The microprocessor is shown by broken lines for reference only. The power-up, clock, clock
control, ready, DMA, and halt functions are used by the microprocessor. The IAK data in, sync,
read/write. reply time-out, and bus control functions are used to interface the LSI-II bus to the
micrOprocessor.
The functional descriptions used in this chapter define the microprocessor and the input/output signals
associated with its operation. The support functions, the LSI-II bus interface functions, and the remaining
single-board computer devices are also described in detail.

8.2 MICROPROCESSOR
The microprocessor is contained within a 40-pin LSI chip and is shown in Figure 8-2. There are eight 16bit general-purpose registers (RO-R 7). R6 operates as the stack pointer (SP); R 7 operates as the
microprocessor program counter (PC). A special purpose status register contains the current processor
status word (PSW). The operating characteristics of the microprocessor are affected by the mode register
which is discussed in detail in Paragraph 8.3.
8.1.1 Microprocessor IlIitiaJization
The microprocessor initializes the SOC-II /21 PLUS module during the power-up sequence or when the
RESET instruction is executed.

8-1

THAll

All

rEV"T
RilL'

~
~
~
~
CAS

Xl'll!
ROL<

l(OU
PCO
Pe3

BeeR

~BIR04L

~"SELO

aHAUt

lATCl-I

~f)

TO SHEET 2

OAT A ADDRESS BUST OAt $~ TDAl 11l2'iC ;IS

80AlOO-!5

r---,
* w:::x:
LSE:"::J'
CONTROL

§
TOAlOO-1SX

~
~

aOAlO, 1,2
\lOIN L

800ur L

to..

~
-1'l1l!NC

fAOIII

SHUT2

~~ 2..,!?£!£.

-CliPL

-CSRAM

-READ

-CSKTA

1I0Al 0, " 2
B01" L
lBWT8T l

8lWLY 1.

FROM

7
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SOC-I 1/21 PLUS Functional Block Diagram (Sheet 1 of 2)

8·2

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PROCESSOR

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~-RAS •

-CAS

PROCESSOR CONTROL SIGNALS

1IWflITt. .I.
8DIN l
800UT L

-PI
-SEL'
RAS
-BClR
T ClKSP
-DRRPlY

RAS

-C~

TSYNC

RRPlY

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RIWH \
AIWlB

TDIN
TOOUl

READI
WRITE

SYNC

-IAK
READ

I-

IAK DIN r- I-

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-BeLR
SEl I

-DMG

BUS
CONTROL

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DMG

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SEL ,

SElO
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DMA
TREAD
TMER

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Set 0
RAS
COUT
-BClA

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BIAKO

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TClKSP
PROCESSOR CONTROL SIGNALS
CAS
-BClR
BPOK H
BOCOKH

JII\

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OClO
PUP

*
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SYNC
-CAS
-BCLR

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PROCESSOR
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PROCESSOR CONTROL SIGNALS

CONTAINED WITHIN E20 IGATE ARRAY)

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Mft·lIt4t

Figure 8-1

SBC-ll /21 PLUS 'Functional Block Diagram (Sheet 2 of 2)

8-3

-eTMER
-PFAll

AI7
AI·6
AI·5
AI-4

ENCODED
INTERRUPT
INPUTS

At 3
AI·2
AI·1

-CDMRQH

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AI-O

XTLl

r
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MICROPROCESSOR

TDAl15
TDAl14
TDAl13
TDAL12
TOAl11
TOAllO
TOAl09
TDAl08
TDAL 07
TDAl06
TOAl05
TOAl04
TOAl03
TOAl02
TOAlOl
TDAloo

XE21
SElO
SEll

READY

R/-WHB
R/-WlB
PUP

TOAl
BUS

}

TRANSACTION
TYPE

CONTROL

-HAS
-CAS
PI
COUT

-BelR

}

TRANSACTION
CONTROL
STROBES

R ESET

MR-1212!

Figure 8-2 SBC-I1/21 PLUS Microprocessor
8.2.1.1 RESET Instruction - The RESET instruction asserts the -BCLR output. This clears or resets
the control logic of the module to an initial state. The microprocessor loads the mode register from the
TDAL bus with the mode register control data. The LSI~ It bus transceivers are disabled when -BCLR is
asserted. The RCVIE bit of the RCSRs and the XMITIE, MAINT, and XMITBRK bits of the XCSRs
are reset in the serial line units (SLUs). The port C buffer output lines of the parallel I/O are set high. If
port A and port B buffers are output to the connectors, they are also set high. The LED is turned off
during reset. The -BCLR output is then negated and an assert priority in (ASPI) transaction is performed
to service any interrupts or DMA requests. The RESET instruction does not change the PSW or any
internal registers.
8.2.1.2 Power-up Input (PUP) - The power-up (PUP) input goes from low to high when the 5.0 V power
is first applied. This initiates the power-up sequence. The -BCLR output is asserted. The module is cleared
and reset as it is for the RESET instruction, however, the serial line units' (SLUs) registers are completely
reset. After a delay, BOCOK and BPOK are asserted, PUP is negated, and the -BCLR output goes high.
The microprocessor then performs ten bus NOP transactions. The processor loads the starting address into
the program counter (R7), location 376 into the stack pointer (R6), and the processor status word is set to
340. An assert priority in (ASP!) transaction is performed to service any interrupts or DMA requests
befQre the first instruction is fetched.

8·4

The PUP input normally stays low for all operations. If PUP is asserted high, the present transaction is
terminated and the internal registers go to an undetermined state. The TDAL bus, the interrupt inputs,
and the microprocessor control signals will all go to an initial reset state.

8.2.2 Clock Input (-TCLK)
The - TCLK input is a 4.9152 MHz clock that comes from the 19.6608 MHz crystal oscillator. This clock
input is used for the internal time base of the microprocessor and the source of the clock output (COUT).
COUT is pulsed once for every microcyde. A microcycle can represent either three or four - TCLK input
pulses depending on the type of transaction. The microprocessor will halt or stop when the - TCLK input is
disabled.

8.2.3

Ready Input (READY)
READY input is normally high and will not interfere with microprocessor transactions. However, when
the input is held low, a single microcycle slip occurs during every transaction. When READY is clocked
with COUT, while RAS is asserted, the microprocessor slips a microcycle every time the input is pulsed.
This allows the microprocessor to be placed in an idle or wait state until a peripheral device has either
received or asserted data on the bus.

8.2.4 Microprocessor Control Signals
The microprocessor controls the functions of the SBC-II /21 PLUS through the use of nine microprocessor control signals. A description of these signals and their functions follows. The RAS,. CAS,Pl, COUT,
and BCLR are transaction control strobes used for logic transitions. The R/-WLB, R/-WHB, SEtO, and
SEL I are steady state logic signals used as transaction type control signals.
Row Address Strobe (RAS) - The leading edge of the RAS signal is used to acknowledge that
the address is stable on the TDAL bus during read/write and fetch transactions. During interrupt
transactions, the leading edge of the RAS signal strobes the interrupt acknowledge data onto the TDAL
12-8 bus lines.

8.2.4.1

8.2.4.2 Column Address Strobe (CAS) - The trailing edge of the CAS signal is used to acknowledge that
data on the TDAL bus Jines during read and fetch transactions was read by the microprocessor. For write
transactions, the signal is used to acknowledge that microprocessor data will be removed after a specified
time.
The leading edge of the signal is used to request that read data be placed on the TDAL bus and to strobe
interrupt requests into tatches that are read during the assertion of PI.

8.2.4.3 Priority In (PI) - The leading edge of the PI signal is used to acknowledge that data on the
TDAL bus lines during write transactions is stable. The leading edge is also used to enable the
microprocessor to read the interrupt inputs AI-O to AI-7 and to initiate IAK, restart, power fail, or DMA
transactions.
8.2,4,4

Read/Write (R/-WHB and R/-WLB) - The Rj-WHB and R/-WLB signals control the
read/write and fetch transactions by enabling the TDIN, TDOUT, and TWTBT control signals. For read
and fetch transactions, both signals are asserted high and enable the TDIN control circuits. During write
transactions, the TOOUT and TWTBT control circuits are enabled when either or both signals are asserted
low. If only one signal is asserted low, the TWTBT control circuits are enabled by the leading edge of
CAS, and a write byte transaction occurs for either high byte or low byte.

8.2.4.5 Select Output Flags (SELO and SELl) - The SELO and SEll signals indicate the transaction
being performed. When both signals are low, a read, write, ASPI, or NOP transaction is selected. When
both signals are high, a DMA transaction is selected. When SEL 1 is low and SELO is high, the fetch
transaction is selected. When SEL 1 is high and SELO is low, an IAK transaction is being performed.

8-5

8.2.4.6 Bus Clear (BCLR) - The BCLR signal is used to reset the control logic and generate BINIT. The
signal is asserted during the power-up sequence and the executi()n of a RESET instruction only.
8.2.4.7 Clock Out (COUT) - The COUT signal is asserted once for every microcycle and is used to time
the microprocessor transactions.
8.2.5 Microprocessor Transactions
The microprocessor performs six types of transactions to support the instruction set, direct memory access,
and the interrupt structure.

t.
2.
3.
4.
5.
6.

Fetch/read
Write
DMA
IAK
ASPI
Bus NOP.

A normal fetch/read or IAK transaction requires either one or two microcycles; extended transactions can
take as many microcycles as required before a time~out occurs. The COUT signal is asserted once for
every microcycle. The transactions are used to transfer information and data via the TDAL bus which
interconnects all local devices and connects them to the LSI-II bus interface. A description of each
transaction operation follows.
8.2.5.1 Fetch/Read - The fetch/read transaction is used either to fetch an instruction or read data for
the microprocessor. The data may originate from the on-board memory, I/O device, or the LSI-Ii bus.
The microprocessor control signals for the transaction are illustrated in Figure 8-3. The R/-WLB and
R/-WHB control signals are asserted. The SELO output is high, and the SELl output is low for the fetch
transaction; both of these outputs are low for the read transaction.
The following sequence of events takes place during a fetch/read transaction.

The microprocessor places the address onto the TDAL bus when the transaction is initiated and
is latched into the memory address circuits by the assertion of SYNC.

The data is received on the TDAL bus after RRPL Y is received. The microprocessor accepts
the data and negates TDIN.

Interrupt and DMA requests are latched by CAS, set up while PI is asserted, and latched into
the microprocessor when PI is negated.
NOTE
A write transaction is always preceded by a read
tra.DSaction except when the microprocessor pushes
onto the stack. Therefore, each write has at least
four microcycies, assert address, read data, assert
address, and write data.

8-6

..........------FETCH/READ.:ANSACTION--------t:
...I·

"...---ASSERT ADDRESS - - - - 4 -.., ....----READ DATA-----t....

---I'

COUT_ _

~~~::x

____

\. . ._____,. "

A_D_D_R_ESS
____-Jl~

NOTE 2

\'-____

x::

________________~(_____

D_A_T_A_IN
______

AI-O-AI.7J.________________...1{....._IN..:;J:.:.;EA.:.IQN~y~lI.lr""f_A_.-I)"'-_ _

RAS_ _ _

P'---""'i-:______......,
-+I____J

CAs _ _ _

I
I

R/-WLB:.1

R/-WHB---/

:..J

I
I

-------

SELl

SYNC

I
I

C
L

--JI

TDIN,_ _ _ _ _ _ _ _ _ _,
NOTES:
1. SEW IS HIGH FOR FETCH TRANSACTIONS
AND LOW.FOR READ TRANSACTIONS.
2. LSI·l1 BUS TRANSACTIONS CAN CAUSE THIS
PORTION OF TIME TO SLIP UNTIL THE
DEVICE RESPONDS OR TIME·OUT OCCURS.

Figure 8-3

I
I

RRPLYH_ _ _ _ _ _ _ _ _..,.'_ _

SEL01-----i--~;i"1---r----\
----

C
C

I
I

\
\I

Fetch/Read Transaction

I
I
I

"--

8.1.5.1 Write - The write transaction is used to write data from the microprocessor to memory, a local
I/O device. or an LSI-il bus peripheral device. The microprocessor control signals for the transaction are
illustrated in Figure 8-4. The R/-WLB and R/-WHB control signals are asserted low when writing a
word; for writing a byte. either the high or low byte signal is asserted. Both SELO and SEll control signals
are negated.
The following sequence of events takes place during a write transaction.
I.

The microprocessor places the address onto the TDAL bus, and the state of the read/write tines
causes TWTBT to be asserted. The address is latched into the memory address circuits by the
assertion of SYNC.

When CAS is asserted, TWTBT is negated for word transactions and left asserted for byte
transactions.

The data is placed on the TDAL bus before TOOUT is asserted. The data is written into the
addressed location when TOOUT is negated.

When the addressed device negates BRPLY, the SYNC and TWTBT signals are cleared.

The DMA requests are detected while PI is asserted; they are latched into the microprocessor
when PI is negated. No other interrupts are read by the microprocessor during write
transactions.

8.2.5.3 IAK - If an interrupt request was detected during a previous read transaction, the microprocessor
initiates an IAK transaction as illustrated in Figure 8~5. The R/-WHB and R/-WLB control signals are
asserted high. and CAS, PI, and SELO are asserted low for the transaction. The TDAL bits 12-8 represent
the acknowledged input and are used to reset the interrupt request. For local interrupts, TDAL bits 7-0
are ignored because the vector address is in the microprocessor. For LSI·l} bus interrupts, the vector
address is read from the bus using TDAL bits 7-2, TDAL bus bit 12 is set low for this IAK transaction
and commands the control logic to initiate an LSI·Il bus IAK transaction. The TDIN signal is asserted for
the transaction, and the TIAKO output acknowledges the interrupt. The requesting device then places the
vector address on the low byte of the bus and asserts BRPLY. The microprocessor stops slipping
microcycles, negates TDIN, and accepts the vector. It then negates TIAKO on the trailing edge of RAS
and continues to the next transaction.
8.1.5.4 DMA - The DMA request is read during a previous transaction. The microprocessor will
acknowledge the request by tri~stating the TDAL bus as shown in Figure 8-6. The SELO and SEll outputs
are asserted to indicate that the bus mastership has been relinquished. The transaction will continue with
no interruptions until the DMA transfer is completed. The microprocessor will then negate the SEll
control output to indicate that it is resuming bus mastership. The negation of SELO will follow if the next
transaction is not a fetch.
8.1.5.5 ASPI - The assert priority in (ASPI) transaction is used by the RESET and WAIT instructions
or the power-up sequence as shown in Figure 8-7. The CAS and PI outputs are asserted to allow the
microprocessor to recognize and latch any interrupts or DMA requests. The R/-WHB and R/-WLB
outputs are asserted and the SELO, SEll. and RAS outputs are negated for the transaction.
8.1.S.6 NOP - The bus NOP transaction performs no operation and is used during the power-up
sequence or if the programmer intentionally introduces a delay into the program. The AJ~O through AI-7
inputs are tri-stated to prevent interrupts. The R/-WHB and R/-WLB outputs are asserted, and the
SELO and SEll outputs are taken low, The RAS, CAS, and PI control strobes are inhibited during the
transaction as shown in Figure 8-8.

8-8

_--_ _ _ _ _ WRITE TRA..NtS..ACTION----------8II:I.

IIII-I----ASSERT ADDRESS----+--o----WRITE DATA - - - -......
-NOTE 3

COUT_ _ _..,'

_____

~~~::x

\ _ _ _ _ _ _ _,

A_O_D_R_ES_S____

~X~

, _ _ _ _ __

x::

__ ________
~X~

D_A_T_A_O_U_T___________

,--_C

AI.O-AI-7J_ _ _ _ _ _ _ _ _ _ _ _ _ _ _<.I.-_D_M_A_R_E_Q_U_ES_T_....)

\_-PI

SYNC______-J.,

___________________

RRPL YH

I~-----I~-J.

--Ili--_-.li

TDOUT _ _ _ _ _ _ _ _

TWTBT

\\-

II \

~.-----

____

\ _______ ~~~ _______1-

NOTES:
1. R/-WHO OR R/-WLB CAN BE HIQH WHEN
PERFORMING A WRITE BYTE TRANSACTION.
2. TWTBT IS LOW FOR WORD TRANSACTIONS.
3. LSI·ll BUS TRANSACTIONS CAN CAUSE THIS
PORTION OF TIME TO SLIP UNTI L THE DEVICE
RESPONDS OR TIME-OUT OCCURS.

Figure 8-4

Write Transaction

8-9

r. . . . . --COUT

-1

SEE NOTE.

----------1

\_________

TDAl12-00::J(_____________I_N_T_E_R_R_U_PT__
R_EQ_U_E_S_T_D_A_T_A______________) ( :

TDAL07-00===><~____________-J)(~--------V_E_C_T_0-R-!_N----__J

..I'

RAS~_ _ _ _

SElO~~__________________________________________~

SEll._ _...,,'

IAKOIN___J '
T!AKO

--------'

-IAK

\_------.....1

TDIN_--,'
NOTE:
LSI-11 BUS TRANSACTIONS CAN CAUSE THIS
PORTION OF TIME TO SUP UNTIL THE DEVICE
RESPONDS OR TIME-OUT OCCURS.
MA·6631

Figure 8~5

IAK Transaction

8-10

COUT

! \_____''''''{\\,..____---',,____

\____---II

RAS
CAS

\~____________~f

'--\---\_--

""C--

R/-WHB - - - - - - ) . -_ _ _ _ _ _ _ _T;,.;,R...' .....
ST
....A
....T;,;;;E_ _ _ _ _ _ _ _ _
A/-WLB _____ _

C
\------

SElO _ _ _ _ _..",
SEL1 _ _ _ _ _--',

-JI

DMG ______________

TDMGO ____________~r___\~

RDMR

________________________________________

c-----------------------

-J'

RSACK _ _ _ _ _ _ _

NOTE:
AI·O IS ASSERTED LOW UNTIL BSACK IS NEGATED
AND NO OTHER ADMR IS BEING ASSERTED.

\_---------MR·_

Figure 8-6 DMA Transaction

8-11

COUT-1

~~;

\'"-----,

________J)~__________T_R~I_~_T_A_1E__________~(~______________

------,

r---------

I ________ _
RAS______ _\,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _...4....

CAS _ _ _ _ _ _,..."

\"""------

,-------

Pl--------------~/

--------------_\r----------

R/-WHB-------.,..
RI- WLB _ _ _ _ _ _ .Jt

\'--- _ _ _ _ _ _ _ _

r---------

SELO------"\
SEL1 _______ ,"'_ _ _ _ _ _ _ _ _ _ _ _ _ _..J'_ _ _ _ _ _ _ _ _ _ _

Figure 8-7

ASPI Transaction

'_ _ _---..IT

COUT________________J /

-------V

y--------

00-15
"- ______ _
TDAL ______ ..A____________________
PREVIOUSLY LATCHED DATA

Joo------. . . . . . . ,;,,;,,;,;,.;;;;,.,-------(C-----______ _

-----}
AI-O-AI-7_____

RAS
CAS

TRI·STATE

-'"\

--~.--------------------------------------------------\
\

-~"'----------------------------------------------------

Pl-"\

--~.----------------------------------------------------

R / - W H S - - - - - - ; ' , . . - - - - - - - - - - - - - - - - - - . . ,- - - - - - - R/-WLB _____ -'

L ______ _

------,

""Lr------_______ _

SELO______ ...:\_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

SELl

------,\
--- - -_ ..----------------------Figure 8~8

BUS NOP Transaction

8·12

8.3 MODE REGISTER CONTROL
The mode register is an internal microprocessor register used to define the operating mode of the
microprocessor. Tbe16·bit mode register is written into from the TDAL 0-15 data lines during a powerup sequence or when a RESET instruction is executed. During this time, the -BCLR output is Jow and the
mode register is loaded, The mode register logic (Figure 8-9) has five tri-state drivers that are enabled
when the -BCLR input goes low, TDAL bits 11 and 8 are factory set to force the microprocessor to
operate in the following mode.
I.

The microprocessor clock mode is selected. The microprocessor pulses the COUT output once
for every four XTU input pulses during DMA and interrupt transactions. For all other
transactions, it pulses the COUT output once for every three XTU input pulses.

The standard microcycle mode is selected. It uses four XTL 1 input periods for DMA and
interrupt transactions and three XTLl input periods for all other transactions.

The normal read/write mode is selected. The normal read/write mode sets the read/write
control lines (R/-WLB and R/-WHB) prior to the assertion of -RAS and remains valid after
the negation of -CAS.

The static memory mode is selected, and therefore, no dynamic memory chips may be installed
on the module. The refresh function is disabled.

The memory addressing is limited to 64Kb.

The bus has 16 bits.

The user mode is selected. This mode performs transactions with no automatic test of the
processor status word.

The status of TDAL bits 13-15 are selected by the user. These bits determine the start and restart
addresses for the microprocessor. The start address is the location of the first fetch after power-up, and the
restart address is the location of a fetch after a HALT instruction is executed or the assertion of the HALT
interrupt. The wirewrap pins M22. M26, and M30 control tbe status of TDAL bits 13-15 during the
power-up sequence. Wirewrap pin MI8 is pulled up to +3 Vdc and represents a one; wirewrap pin M29 is
connected to ground and represents a zero. Pins M22. M26, and M30 are jumpered to either M 18 or M29,
according to the list in Table 8-1. to select both the start address and restart address for the
microprocessor.

-BeLR - - - - - " - - - - - '

Figure 8-9

Mode Register Control

8-13

Table 8-1 Start Address Configurations

Wirewrap Pins
Bit 15

Bit 14
M16

Mll
I
I
I
I

0
0
0
0

Start Address

Restart Address

172004
l73OO4
000004
010004
020004
040004
100004
140004

Bit 13
M30

172000

0
0

173000
000000

0~0000

020000
040000
100000
140000

1
I

0
0

Connection to M 18 .., I
Connection to M29 "'" 0

8.4 INTERRUPT CONTROL
The interrupt control. as a block diagram, is illustrated in Figure 8·10. (Studying this diagram will make
the explanation presented in Paragraph 8.4.1 easier to follow.)

1.174

MICROPROCESSOR
AI-7

HALT

SElO t-

PFAI~==:f)
CAS

TDA112
AI-O

OMRQ

It..
INTERRVPT
SYNCHRONIZERS

~ (121

~e"'NT

l'AlIOS"
PBROST

11/(140

LATCHING
FlIP·FLOPS

E2. E3. E20

4
INPUTS

PRIORITY
9 ADDRESS

LlNSS

(41

£1.<2.

Ell, E1Sl
RESETS

II rJ

XOll

ROl2
XOl2
XE59

ROl2

XDL2

INTERRUPT
ENCODING

MEMORY

VEe

512)<..

DECODE

ROM

E14

XDL2

ro-

SEW
AI··5
{VEel

SFl.1

XE21

~
2 RESETS

-.-J

s
6

iNTERRUPT
AC/(

DECODER

MEMORY

SLU2

32X8 ROM
E12

4 RESETS

...

TDAlS-It

!
2

Figure 8-10 SBCMll/21 PLUS Interrupt Control

8-14

E20

f- DECODE

tCAS r--

RAS

BUS
INT
ACK

TOAl B··11

?I~

2 RESETS

r--

-AI-1- TO- ,'"-4
_..../'

----.."

ROll

SLU!

XES8
ROll

rc:

SELf

.0.1--6

IAK ~

E20

The SBC-II /21 PLUS interrupt control design includes the following elements:
1.

Five 0 fliJrflops that latch five of the interrupt lines.
a.
b.
c.

d.
e.
2.

REVNT
PARQST
PBRQST
BKRQ
HTRP

Eleven interrupt synchronizing latches, that latch the following signals.

Outputs of the five latches described previously

Two interrupt signals:
(1)
(2)

IRQ4
OMRQ

Level 4 LSI-II bus interrupt
OMA request

Four signals from the interrupt acknowledge decoder,
wire OR-ed with interrupt requests from SLUs.
(1)
(2)
(3)
(4)

Wire OR-cd TEVNT or BEVNT
Parallel I/O port A interrupt request
Parallel I/O port B interrupt request
Level 7, maskabIe interrupt, configurable
Nonmaskable interrupt, configurabJe

ROll
XDLl
RDL2
XDL2

SLU 1 receiver interrupt request
SLU 1 transmitter interrupt request
SLU2 receiver interrupt request
SLU2 transmitter interrupt request

PFAIL is gated by CAS (through E7)

The operation of the SBC-II /21 PLUS interrupt control centers around eight microprocessor input lines.
AI-O to AI-7, driven by interrupt signals, either directly or indirectly, through the interrupt encoding
PROM.
•

AI-O is the OMA request line connected directly to OMRQ.

•

AI·} to AI-4 are driven by the output of the interrupt encoder to request maskable interrupts.

•

AI-5 is driven by the VEC gate which detects the presence of the LSI-II bus interrupt on the
outputs of the interrupt encoder. It calls for a vector read transaction from the bus,

•

AI-6 is driven directly by the power fail input line to force a power fail trap.

•

AI-7 is driven directly by the HALT interrupt line to force a restart trap.

The microprocessor reads the AI-O to AI-7 input lines and arbitrates the interrupt priority according to
Table 8-2. In addition, the state of AI-} to AI-5 is reproduced on TDAL 12-8 lines during the acknowledge cycle. TOAL 11-8 lines are used as an address in the interrupt acknowledge decoder, which is a 32byte PROM. Output bits 7-4 of that PROM are the previously stated SLU receive and transmitter
interrupt requests (ROL 1. ROL2, XOL I, XOL2) which are wire-ORed to reset the latched requests in the
SLUs. TOAL 12 reflects the state of the - VEC signal and is used in the LSI-II bus protocol.
Bits 0-3 are used as reset signals for the four interrupt latches previously described.

8.4.!

Interrupt Control Logic

The interrupt logic (Figure 8-11) receives the interrupt requests from the interface devices and applies
them to the microprocessor. The microprocessor will acknowledge the highest priority interrupt if its
priority is higher than the current microprocessor status word priority. There are nine interrupts available,
and either one or all can be inputs to the interrupt synchronizers E2, E3 and E20. Any interrupt is active
when the signal goes high. Five of these inputs are latched and stay high until reset. Four interrupts are
clocked through flip-flops EI, E2 and E19 to maintain a high output. The enabled interrupts are clocked
through the interrupt flip-flops by CAS asserting during the present transaction. These outputs address
interrupt encode memory locations enabled by the -PI input of the present transaction. The interrupt
encode memory outputs an interrupt code equivalent to the highest input priority.

E17 ~

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ROLl
XI>L2

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TOAUI

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00 I-- A'

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05 FLIP FLOPS 06 I-- A5 ~~~OE

PBRDST

A ••

INTERRUPT Ql I-- A4 INTERRUPT

A2
Al
AO

84
rOAll!
TOAl1O

r- AG
r- A1
Q3 r- A2
as r- A3

06
01

E19

CSKAO

.,r- P

-SClR

PCO
PCJ
'AS

~El~
~
8H,o,.LT

Figure 8-11

MI'I1,U_

Interrupt Control Logic

The interrupt codes and their priority levels are listed in Table 8-2. When the PI output is enabled, the
microprocessor looks at the interrupt inputs and will initiate an IAK transaction for an interrupt with the
correct priority following the completion of a read transaction. The coded input to the microprocessor is
placed on the TDAL bus using bits 8-12. Bit 8 represents the AI- I input; bit 11 represents the AI-4 input.
These four TDAL bus bits are inputs to the acknowledge decoder memory that is enabled when the
microprocessor starts the IAK transaction and the -IAK input goes low. These inputs are decoded to
determine which interrupt was acknowledged and will output a low to negate that interrupt. The interrupt
flip-flop is reset by the clear line for that interrupt, switching the output of the selected AND gate low.
The E4 and E13 transmitter and receiver interrupt tines are latched outputs and are reset by wire OR-ing
and asserting low the output of the acknowledge decoder PROM. The LSI-l! bus interrupt is an exception
to this process. This interrupt code enables the inputs of NAND gate E14, and the low output enables the

Input

Table 8-2

Designated Internipts
Coded Input
AI-l AI-2

AI-3

AI-4

AI-5

Interrupt
Source

Sipa'

Priority
Lefel

HALT

HLTRQ

Nonmaskable

Restart
address

Power fail

PFAIL

Nonmaskable

140

100

120

LSI-II bus
signal BHALT

BKRQ

LSI-II bus
signal BEVNT

REVNT

SLU2 REC

RDL2

SLU2 XMIT

XDL2

Parallell/O B

PBRQST

Parallel I/O A

PARQST

SLUI REC

ROLl

SLUI XMIT

XDLI

LSI-II bus
signal BIRQ4

IRQ4

Vector
Address

124
0

130
134

Read
from
LSI-II

bus
HALT and power fail (PFAll) interrupts are not generated by the coded inputs AI-I to AI-S. All signals are listed in the order of
descending priority.

-VEC (AI-5) input to the microprocessor. This input instructs the microprocessor to receive the vector
address from the TDAL bus. TDAL 12 represents the state of the - VEC input when the microprocessor
acknowledges the interrupt and is used to determine that the LSI-II bus interrupt acknowledge handshake
protocol must be initiated. The LSI-II bus interrupt is not reset by the acknowledge decoder PROM, but
it should be reset when the TDIN and TIAKO signals are received by the bus device during the interrupt
acknowledge sequence.
Before continuing the discussion of the interrupt system. ready logic is discussed in Paragraph 8.4.2.
8.4.2 Ready Logic
The ready logic (Figure 8-12) provides the READY input to the microprocessor and is used to control the
cycle slip function. The microprocessor will cycle slip when the READY input is being clocked while RAS
is asserted; the cycle slip function will be inhibited when the READY input is set high. The output of the
ready flip-flop and the COUT input go to the G62 OR gate and generate the READY input. When the
-CSLlP input to G61 is high and the TSYNC input is high, the output of the G61 AND gate goes high.
When -DRRPLY is not asserted and - TCLKSP and the output of G62 are high, the output of G3 is high.
This enables G4 and the preset input to the G5 flip-flops to go low. The flip-flop output is low at OR gat~

8-17

-TMRP

-TClKSP
-DRRPlY

IAKDIN

READY

-CSLlP
TSYNC

COUT
-BClR
MA·1212.

Figure 8-12 Ready

G2, and it enables the READY input with every COUTo When the IAKDIN input goes high and the
-CSLIP and TSYNC inputs are negated, the output of the G3 AND gate goes high. It allows the G4
NAND gate output to go low and forces the preset terminal of the G5 flip-flop low. The output of the flipflop to the OR gate is now low. This allows the COUT input to clock the READY output. The
microprocessor will continue to cycle slip while this input is being pulsed. The - TMRP input to the
NAND gate will go low when either the BRPLY or TMER input from the bus is received. This will
remove the low from the preset input of the first flip-flop. Immediately after the - TMRP input goes low,
the -DRRPLY input also goes low and forces a high to the input of the flip-flop. The high is clocked
through by the COUT clock, and the flip-flop output to E 14 will go high. This disables the READY input
to the microprocessor and allows the transaction to be completed.
The second G5 flip-flop is required to ensure that data is stable at the microprocessor or at the peripheral
preceding transaction completion. The ready circuit is inactive during local address references.

8.4.3 IAK Data In (IAKDIN)
The IAKDIN output is enabled by the output of the NOR gate G 10 as shown in Figure 8-13. The
microprocessor acknowledges an external interrupt request, asserts -SEll. and negates SELO. When the
microprocessor has to read the interrupt vector from the bus, the TDAL 12 input is low as a result of AI-5
being low during the interrupt request read. This allows the IAKDIN output to go high and assert TDIN to
the bus. The RAS input is high; this enables the TIAKO flip-flop G 12. IAKDIN is clocked by the
TCOUT input and causes T1AKO to go high. The inverter E15 sets the BIAKO output low. The BIAKO

-IAKDIN

-SEll
SELO

-BIAKO

TDAl12

G12

TCOUT

TlAKO

RAS
-BClR

Gll

MR·12U8

Figure 8-13

IAKDIN

8-18

output goes to the bus as an interrupt acknowledge. The TIAKO output goes to the bus transceiver logic
and enables the low byte transceivers to receive the vector. The JAKDIN output goes to the ready logic
and allows the microprocessor to cycle slip until the interrupting device asserts the ,-BRPL Y input or a
time-out occurs. When either response is received, the SELO input goes high to disable the IAKDIN
output and signals that the microprocessor has read the vector. The RAS goes low to clear the TIAKO
flip-flop.
The microprocessor cannot abort the reading of a vector if a time-out occurs and will read a vector of zero
in all cases if -BRPL Y is not asserted and the time-out counter triggers.

8.4.4 HALT Interrupt
The HALT interrupt (Figure 8-14) is defined as -CTMER and goes to the microprocessor Al-7 input. The
G22 flip-flop is clocked by the input to TMER; this asserts the G23 flip-flop input. The assertion of CAS
clocks the G23 flip-flop and enables the -CTMER output. The CTMER output is set high and goes to the
NAND gate G20. The assertion of PI during a microprocessor read or fetch transaction latches -CTMER
into the microprocessor and simultaneously switches the G20 NAND gate output low. This sets the output
of the G21 AND gate low to reset the G22 flip-flop for the next HALT interrupt. The G23 flip-flop is
cleared by the next CAS strobe. The microprocessor AJ-7 input is pseudo edge-sensitive; it must be
negated for one PI time before another trap to the restart address can be started.
.

/;+ 3V
-IAK

G22
TMER

G23

0..0

CAS
• BeLf!

'"\...
G20

TREAD

loI G21~

r--

...
r-

-eTMER
AI7

.....

Mfl·12127

Figure 8-14

HALT Interrupt

8.4.5 Power Fail (-PFAIL)
The -PFAIL output is connected to the AI·6 input of the microprocessor and is recognized as the power
fail interrupt which is nonmaskable. This is the second highest priority interrupt and it does not initiate an
IAK transaction. When acknowledged, the microprocessor traps through octal addresses 24 and 26 to
access the PC and PSW for the user's power fail routine. This routine should include a RESET instruction,
any other instructions needed to initialize the bus and the module, an MTPS instruction that will load 340
into the PSW, and a WAIT instruction to inhibit the assertion of any LSI· I I bus control signal when
battery backup is being used.

8·19

As an option to the MTPS instruction, 340 may be stored at location 26. Then, when the microprocessor
vectors through 24, 340 wilt automatically be loaded into the PSW.

NOTE
BOCOK should not be used as a microprocessor
reset signal. However, should it be used as a reset
the BOCOK pulse must be at least 100 IJ.S wide.
BPOK should remain inactive during this reset
operation.
8.4.6 Local
The on-board local interrupts are listed in Table 8-2 and use a coded input on the AI-l through AI-S inputs
to the microprocessor. Some of these interrupt functions are determined by the user when configuring the
module. There are eight local interrupts which are all maskable. The multiple interrupts are arbitrated,
and the interrupt with the highest priority is serviced by the microprocessor. All local interrupts initiate an
IAK transaction, and their vector addresses are internal to the microprocessor. During IAK, the serviced
interrupt is driven on TDAL lines 11-8 to address the interrupt acknowledge PROM. The outputs of the
PROM reset the interrupts. TDAL bits 7-0 are ignored. The microprocessor pushes the present PSW and
PC onto the stack and receives a new PC and PSW from the vector address location and the next location.
8.4.7 External
A level 4 LSI-il bus interrupt also uses a coded input on the AI-l through AI-4 inputs to the microprocessor. The interrupt is maskable. For the bus interrupt, the AI-5 input to the microprocessor is taken low to
indicate that the vector address must be read from LSI-II bus bits 7-2. The microprocessor does an IAK
transaction and places the BDIN and BIAKO signals on the bus to the requesting peripheral device. This
device responds with -BRPLY, and the vector address is read from the LSI· I I bus. The microprocessor
pushes the current PC and PSW onto the stack and reads a new PSW and PC from the vector address
location and the next location.
If the interrupting peripheral device fails to assert the BRPLY bus signal within 10 IJ.s after BDIN is
asserted, the module time-out signal TMER is enabled. The microprocessor completes the IAK transaction
and receives a vector address of zero because there is nothing driving the bus. The new PSW and PC are
then read from locations 0 and 2. Optionally, the user can connect the time-out signal TMER to the
HALT interrupt, and the interrupt can then be processed. The HALT interrupt pushes the current PSW
and PC, which were read from locations 0 and 2, onto the stack and then loads the PC with the restart
address and the PSW with 340. If. the HALT is ignored for the vector time-out, only a vector through
locations 0 and 2 will occur.
8.4.8 DMA Interrupt
The DMA request is connected to the AI~O input to the microprocessor. The DMA request is received by
the microprocessor during any read, write, fetch, or ASPI transaction. The request is not acknowledged by
an IAK transaction, but is acknowledged by the microprocessor asserting the SELO and SEll outputs to
initiate a DMA transaction. (See Paragraph 8.15 for a discussion of DMA transactions.)
8.5 OC004 PROTOCOL
The DCOO4 protocol logic chip (see Figure 8-1, sheet I) interfaces the LSI-Ii read/write signals with the
module read/write signals. The -CSQB input goes high and is strobed by RSYNC to enable the logic. The
BDIN L input goes low to request read data and switches the -READ output low. The BPOUT L input
goes low to strobe write data and switches the - WHB and - WLB outputs low if the BWTBT L input is
high. When the BWTBT L input is low, the BDALO L input will select either the -WHB or the -WLB. A
low on the BDALO L input switches the -WLB output tow. The BRPLY L output is controlled by the
-eSQB input. When -CSQB input is high, this indicates that the LSI-Ii bus was not selected. The

8-20

BRPLY L output is enabled and is switched low, after an RC delay, when BSYNC L and either the BDIN
Lor BOOUT L outputs are switched low. If the -CSQB input is low, the LSI-II bus is selected and the
BRPLY L output is disabled. The BDALO, I, and 2 inputs control the -SEL6 output. The output goes low
when the BDAL 1 Land BDAL2 L inputs are low and the BDALO L is high.
8.6 ADDRESS LATCH
The address latching logic (see Figure 8·1, sheet I) has sixteen transparent latches designated E34 and
E36. The latches are always enabled by grounding the output control input. The TDAL bus bits 1-15 and
the I/O page select signal RBS7 are monitored. The status of inputs is latched to the address bus as bits
AD 1 through AD 15 by the RSYNC input going high. The address bus and the latched LBS7 signal go to
the memory address decode logic. The address bus is common to the module memories and the I/O
circuits and remains stable while RSYNC is asserted.
8.7 MEMORY ADDRESS DECODE
The memory decode logic (see Figure 8-1, sheet 1) has a field programmable logic array (FPLA) that
decodes the applied address bits and the latched LBS7 signal. The FPLA selects a predetermined output
according to the selected memory map. The module address range includes the on-board memory, the I/O
interface registers, and LSI-II bus addresses. Four different memory maps, described in Figure 8-15, are
available to the user. The M25 and M21 wirewrap pins, described in Chapter 2, allow the user to select one
of these maps. The FPLA is enabled if the OCLO input is low. An address location in the RAM memory
enables the -CSRAM output, and an address location of either socket set A or B of PROM enables either
the -CSKTA or -CSKTB outputs. A register address for either SLU I or SLU2 will enable the -CSDLO
or -CSDL 1 outputs. The -CSPL output is enabled when a register of the parallel I/O logic is addressed.
The -CSLIP output is low for all the above address conditions. The -CSLIP output goes high only when
the address is accessed on the LSI- t I bus and the -CSQB output is enabled low. The --CSLIP output
allows the processor to cycle slip during the LSI-II bus read/write and IAK transactions.
8.8 RAM MEMORY
The static RAM memory, shown in Figure 8-16, is a 8K X 16-bit memory that has a 8K X 8-bit high byte
chip and a 8K X 8-bit low byte chip. The memory is selected by the --CS RAM input going low to the CS
pin. The memory is addressed by address bits ADI-AD13, and 16-bit data is read from or written to via
TDAL bits 0-15. The memory is read by the -READ input going low to produce a low input to the OE
pin of the memories. The -WLB selects the low byte, and the -WHB selects the high byte. The -WHB
and -WLB inputs to the WE pin enable the write function, and -READ input goes to the OE pin of the
memories to enable data output during read.
8.9 ROM/RAM MEMORY SOCKETS
The ROM/RAM memory, shown in Figure 2-5, provides the user with four 28-pin sockets to accept either
24·pin or 28~pin industry standard +5 V chips. The sockets can hold up to 32Kb of UV PROMs,
EPROMS, PROMs, or ROMs and up to 32Kb of static RAM. The socket sets are defined as A and B,
and each has a high byte socket and a low byte socket. The sockets use the -CSKTA and -CSKTB
outputs from the memory address decode (see Figure 8-15 for the memory maps), The -READ, -WHB,
and -WLB signals from the OCOO4 protocol are used to provide a high byte chip enable (HBCE) and a
low byte chip enable (LBCE). There are sixteen wirewrap jumper pins available for the memory configuration. See Chapter 2 for detailed information.
NOTE
When a memory chip is placed into a socket wired
for a larger capacity part, for example a 2K X 8
chip in a 4K X 8 socket, the addresses above the 2K
boundary will wrap around into the start of the
memory. This should be noted when selecting the
memory map configuration.

MAPO
(177776) 64K8

128 BYTES
(NOTE 2)
(NOTE 1)
4KB
SOCKET A

(174000) 62K8
(lDOOO)

{172000}
(164000) 58K8

LSI-l1 SUS

(160000) 56K8

MAP 1

MAP2
64K B

64K B
(NOTE 1)

62K B
58K 8

56K S-

62K B
14KS
SOCKET B

58K B

128 BYTES
{NOTE 21
(NOTE 1)
4KB
SOCKET A

MAP3
64K B
lSI·l1 BUS
(NOTE II
62K B
58K 8

14KB
SOCKET B

56K B

aKB
LOCAL RAM

48K B

t1400QQl 48K8

(120000) 40KS

16KB
SOCKET 8

(100000} 32KS

(400Q0)

16KB

(200001

8KB

LSI·l1 BUS

40K B

48K B

16K8
LOCAL RAM

40K B

32K B

24K B

24K 8

16K B

32K8
SOCKET A

LSI·l1 BUS

40K B

128 BYTES
(NOTE 3)

LOCAL RAM

8K B

OKS

32KB
SOCKET.A

32K B

24K B

16K B

16K 8

aKB

48K B

16KB
SOCKET B

8K B

16K8
LOCAL RAM

(lQQOO>
(NOTE4)

OKS

OKB

NOTES:

1. THIS SECTION CONTAINS THE LOCAL 1/0 ADDRESSES FOR THE SLUS AND
PPI. ALL UNASSIGNED ADDRESSES ARE ASSUMED TO RESIDE ON THE LSI·l1 BUS.

2. ADDRESSES 177777·177600 IN MAPS 0 AND 2 ARE RAM SCRATCHPAD
LOCATIONS USED BY MACRO·ODT,
3.

ADDRESSES 77777 . 77600 IN MAP 2 ARE ALLOCATED TO THE LSI·11 BUS.

4. UNDERLINED ADDRESSES ARE JUMPER SELECTABLE START ADDRESSES.
(SEE TABLE 2-4)
MA 12119

Figure 8·15

Memory Maps

8-22

-READ

-WHB

-CS RAM

Cs
AD1-ADll

STATIC RAM
HIGH BYTE
8K X8
E33

'\
/

TDAL 08-15

.,.

TDALOO-'{)

~
.,.
-CS RAM
-WLB

~TDALOO-07
RAM
CS STATIC
LOW BYTE

- 8KX8

E40
-READ

Of
00"-12129

Figure 8-16 RAM Memory

8.10 SERIAL LINE INTERFACE UNITS
There are two asynchronous serial line units, SLU 1 and SLU2, that provide serial I/O interface through J 1
and J2 as shown in Figure 8-17. Configurations are discussed in Chapter 2.
The SLUs transmit or receive 8-bit, byte-oriented data, with no parity, one start bit, and one stop bit.
SLUI provides the XDLI and RDLI interrupts for transmit and receive and the BREAK output that is
wired to pin M17. The user can jumper the BREAK output to the HALT interrupt (pin M20) and use
SLU I as a system console. SLU2 provides the XDL2 and RDL2 interrupts for transmit and receive and
three real-time clock interrupts at 50 Hz, 60 Hz, and 800 Hz. These interrupts are wired to pins M27,
M19, and M28 for use with the TEVNT interrupt (pin M23).
When the serial line units are addressed, the -CSDLO input selects SLUI and the -CSDLI input selects
SLU2 by enabling the chip select (CS) inputs. Address bits AD2 and ADI are used to select individual
registers within the SLUs. These registers are listed in Table 8-3 with their address and the logic states for
AD2 and ADI to access them. The -READ input will read the 16-bit register selected by -CSDLO or
-CSDLl, AD2, and ADI by placing the contents onto the TDAL bus if the -WLB input is not asserted
low. When asserted low, the -WLB input will write the low byte of the TDAL bus into the register
selected by -CSDLO or -CSDLl, AD2, and ADl. However, only the register bits defined as read/write
will be written into. The DLCLK input is a crystal-controlled clock reference used by the SLU to generate _
baud rates and real-time clocks. The BCLR input is asserted during a RESET instruction; the RCVIE bit
of the RCSR register and the XMITIE, MAINT, and XMIT BRK bits of the XCSR register are reset.
When the DCLO input is asserted during power-up, it disables all SLU outputs and resets all intemallogic
and registers. The baud rate will be set at 300 baud after the SLU is initialized by DCLO.

8-23

The RS232 and RS423 signals for the interface connector are provided by 9636 (E22) and 9637 (E23)
dual line drivers and dual line receivers. The slew rate for both channels is controlled by resistor R6. The
factory configuration uses a 22 kO resistor to provide a 21J.S s1ew rate for operating at a 38.4K baud rate.
See Chapter 2 for the configuration requirements at other baud rates.

J2
+12 F

BRCLK
SLU 2
OLART
E13

- OL1

R7
M23
Q--TEVNT H -12V

OLCLK

04
E16
03

05
4.3V

+5VDC

MR·12130

Figure 8·17 Serial Line Interface Units

8-24

Table 8-3

Serial Line Unit Registers

Description

Address

AD2

ADt

SLUl
RCSR
RBR
TCSR
TBR

Receiver control/status
Receiver buffer
Transmitter control/status
Transmitter buffer

177560
177562
177564
177566

0
0

0
I
0
1

SLU2
RCSR
RBR
TCSR
TBR

Receiver control/status
Receiver buffer
Transmitter control/status
Transmitter buffer

176540
176542
176544
176546

0
0
I

8.11

1
1

0
1
0
I

PARALLEL I/O INTERFACE

The programmable parallel I/O provides a 30~pin connector for transferring parallel data into or out of the
SBC~ I 1/21 PLUS module. The parallel I/O uses an 8255A-5 programmable interface chip, two 8-bit
transceiver chips, and an 8-bit buffer chip as illustrated in Figure 8·18. The 8255A-5 chip has three
input/output ports defined as port A, port B, and port C. Port A and port B outputs are connected to 8-bit
bidirectional transceivers that are controlled by wirewrap pins M49 and M52. When a logical one is
applied to these pins, the data lines function as inputs to the module. When a logical zero is applied to
these pins, the data lines function as outputs from the module. The user can configure these as inputs or
outputs by using wirewrap pins M51 and M50 or as programmable inputs/outputs by programming the
PC4 and PC6 lines (M54, M58) of port C as described in the configuration description in Chapter 2. The
port C outputs are connected to directional buffers and are used for interrupts and the handshake control
for ports A and B. PCO and PC3 are wired as outputs, PC3 enables the parallel interrupt request for port
A, and PCO enables the parallel interrupt request for port B. PC4 and PC6 can be used as acknowledge or
strobe inputs or can be configured to dynamically control the direction of ports A and B from either the
8255A-5 interface or the external peripheral device. PCl, PCS, and PC7 are wired as outputs, and PC7 is
wired to an LED that can be program controlled. PC2 is wired as an input and has a current limiting
resistor for protection when PC2 might be programmed as an output from the 8255A-5 interface. See
Chapter 2 for detailed configuration requirements and Chapter 6 for programming information.
The 8255A-5 programmable peripheral interface (PPI) is enabled by the -CSPL input from the memory
address decode chip when the 176200-176207 addresses are selected. The AD 1 and AD2 address lines are
decoded to select one of the four registers listed in Table 8-4. The port A, port B, and port C registers are
read/write registers, and the control word register is a write only register. The addressed register is written
into with the data on the TDAL 7-0 bus when the -WLB input is asserted. The content of the addressed
register is placed on the TDAL 7-0 bus when the -READ input is asserted. The -SEL6 L input to
NAND gate E7 inhibits the read strobe from the control word register, and therefore, any read of the
control word register produces invalid data to the microprocessor. Only the low byte of the TDAL bus is
used with the PPl, and any data on the high byte is always considered invalid. The -BCLR input is used to
reset the PPI when it is asserted, and all twenty-four 8255A-5 I/O lines are then defined as inputs. The
buffer outputs to the connector will be driven high.

8-25

_PC3

r-- --,.",-----.,.

~PCO 1
PCO

•

;V~

flCl

v:>----+--------....
I

i
I

RIO

PC2~-~~~-_r----~

ADI-AI

M58

PC4

-CSPl---O cs

M~
PC6 ~

ESET

"\.u.
-SEL 6 I E7 f""" RD

r--a

M65

~~-------------~10

'.-------1

:::o--It-f'...--<'-J~--+

PC5~-----.---~H

-WlB--C WR
-BClR

~-----+--------------__4 4

"-J

PC3~--~-----~------_i

A D 2 - AO

E26

LTDAl 00-07 )

t---tit----------4 7
j

E35
I
_ _ _ _ _ _ ..JI
IL_ _ _ BUFFERS

07
Lce:>-+5
V

r-- 21

i - - 15
i - - 16

PBO'~------_tBO

AO~--------I12

PB1~-------_tB3

A3~-----------I14

PB2
PB3
PB4
PB5
PB6
PB7

~~------~---------~6

~7~-----~

8255A-5
PROGRAMMABLE
PERIPHERAL
INTERFACE

B5
BUS
A5
B7 TRANSCEIVERS A7
B6
E29
A6
B4
A4
B2
A2
Bl
Al
+3V 0 M50
GNODM51

1IR
M.!9
D t--_--I°
-

PAO~---------_t86

30
29

A6~---------I27

M
M
~
82
8US
A2
23
80 TRANSCEIVERS AO
21
81
E27
Al~-----------I22
B3
A3~---------I24
B5
A5~---------I26
87 DIR
A7~---------i28
____

Ml
PA2
PA3
PA4
PA5
PA6
PA7
M52

18
20
19
17
13
II

~
I ..... I

E16$.>--r--__-r----I
*C22

Rll

MR·'2131

Figure 8-18

Parallel I/O Interface

Table 8-4 PPI Addressable Registers
Register

Address

Status

PortA
PortB
PortC
Control word

176200
176202
176204
176206

Read/write
Read/write
Read/write
Write only

8-26

8.11 POWER-UP
The power-up circuits (Figure 8-19) sense the application of +5 V NCR power source to the module and
initiate a power-up sequence. When the +5 V NCR input is fIrSt applied. the input at the inva1Cr 030 is
low and causes the clear input of the PUP flip-flop 031 to be low. therefore keeping its OlItputlow. When
tbe input to the NAND pte 032 is low. the -PUP output is hip and the microprocessor is belch-esct and
asserts the -BeLR output. The +S V NCR input charles C8 throuah R4 until the threshold1evel of
inverter G30 is reached. This occurs at approximately 2.6 Vdc and 70 ms after +5 V NCR was applied.
This causes the reset input to the PUP flip-flop to 10 high and the set input to go low. settinl the flip-flop.
The -PUP output of the NAND pte G32 goes low. This initiates the power-up sequence of the processor.

BPOK H

G33
CAS

-PFAIL

-BelR

r --------,
I
I
I
,~...... I
I
WAKE-UP CIRCUIT

-pup

+5VNCR

OCLO

I
~---BOCOK H

- - - - - - - - - - - - - - - - - : - XLB

E20PIN 9

- - - - - - - - - - - - - - - - - BOCOKH

E10PIN15

BPOK H

E24 PIN 9

BINIT L

E15 PIN 4

-BCLR
_ _ _ _ _ _ _ _ _ _ _ _ _ _ -PUP

E20 PIN 26
E20 PIN 26

_ _ _ _ _ _ _--:0_ _ _ _ _ _-

-----~_ _ _- - - - -_ _ _~-

-TCLK

E2OPIN28

SIGNALS DURING POWERUP
MA-12132

Figure 8-19 Power-up

8-27

The power· up delay circuit can be bypassed by inserting a jumper between M4 and M6. This allows the
BOCOK Hand BPOK H bus signals to control the PUP output. The +5 V NCR input goes directly to the
inverter 030 driving input to the NAND gate ElO low. The EIO output is then controlled by BDCOK.
The BDCOK H signal is low until the power supply stabilizes, causing the reset input to the PUP fli~flop
to be low. The BPOK H signal is also low and causes the preset input to the fli~flop to be high. The low
input to NAND gate 032 drives the -PUP output high. The microprocessor then asserts the -BCLR
output resetting the PFAIL fli~flop. After a minimum of 3 ms, the BDCOK bus input goes high and
allows the PUP fli~flop G31 reset to go high. After a minimum of 70 ms, the BPOK H bus input goes
high causing the PUP preset input to go low. This allows the output to go high, and when both inputs to
NAND gate 032 are high, the -PUP output is low. This initiates the power-up sequence of the
microprocessor.
The BPOK H bus input also goes to the PFAIL flip.f1op G33. During the power-up sequence, -BCLR
resets the PFAIL flip.flop. The f1ip.flop remains reset until the BPOK input goes low indicating a power
fail. The next CAS input clocks the PFAIL f1ip.f1op and sets it. This causes the power fail interrupt, and
the microprocessor traps to location 24. The f1ip.flop must be reset for at least one microprocessor read
before another assertion will be recognized by the microprocessor.

8.13 CLOCK
The module uses a 19.6608 MHz crystal oscillator as the basic time base reference. The oscillator output
goes to the clock control logic (see Figure 8-20) and to the G34 binary counters. The counters are always
enabled. The 19.6608 MHz output is divided by 32, and the DLCLK output, at 614.4 kHz, goes to the
serial line units and to the charge pump. The 19.6608 MHz output is also divided by 4, and the 4.91 MHz
output goes to the pulse sync circuit 035. When the TCLKSP input is low. the circuits are enabled and the
output goes to the next pulse sync circuit. When the TCLKSP input is high, the circuits are inhibited and
there is no output. The second pulse sync circuit is controlled by the PUP input. When the PUP input is
low, TCLK to the XTU input is enabled. When the PUP input is high, the XTU input is inhibited.

s elK
DIVIDE
BY 16

I--

G34

DIVIDE
BY 2

Dl elK

G34

DIVIDE

r9.66MHZL
OSC E2 J

BY 4

G35

to--

G35

-TCLK

G34

TCLK SP

-PUP
MA-'2133

Figure 8-20

8-28

Clock

8.14 CLOCK CONTROL
The clock control logic (Figure 8-21) stops the XTLl input to the microprocessor and forces the
microprocessor to stop or wait until the XTLl input is enabled again. The TCLKSP output is normally low
to enable XTLl and is controlled by the TMRP input being high. TMRP forces a low for both inputs to
the OR gate G44, and the low output is clocked through the TCLKSP flip-flop by the 19.6 MHz input.
When TMRP goes low, this removes the low inputs to the AND gate G43 and the IAK flip-flop 042. The
TSYNC input is high for read/write and fetch transactions, and when the -CAS input goes higb, tbe
AND gate G43 output also goes high. The output of AND gate G43 is clocked through the TCLKSP flipflop. and the output goes high to stop the 4.91 MHz clock output of G35. The TSYNC input is low for
DMA and IAK transactions so tbat input to the AND gate G43 holds the output Jow. However, the IAK
flip-flop G42 is set when the -IAK clock input goes higb at the end of an external interrupt transaction
and the G44 output goes high. The G44 output is clocked through tbe TCLKSP flip-flop, and the output
goes high to stop the 4.91 MHz clock output of 035. The microprocessor XTLI input will stay stopped
until the TMRP input goes high again because either BRPL Y or TMER have been negated. This forces
the IAK flip-flop 042 output to go low. This negates the TCLKSP output and enables the XTLI input to
the microprocessor.

G41
-DRRPLY

SCLK
-BeLR

Figure 8·21

Clock Control

8.15 DMA
The DMA logic (Figure 8-22) controls the bus and microprocessor for DMA transactions. The BDMR L
input goes low to start a DMA request. The output of the inverter goes high and is clocked through flipflop 050 by COUTo The low output goes to the G56 NOR gate, and the high output goes to flip-flop 050.
The high output is clocked through by COUT and enables the two NAND gates G52 and G57. The high
output is also clocked through flip-flop G54 by the CAS input. The high output enables the NAND gate
055, and the -CDMRQ output (AI·O input) is switched low. The -CDMRQ output is the DMA interrupt
to the microprocessor and it starts a DMA transaction. The microprocessor acknowledges the request by
setting SELl and SELO high to NAND gate 051. The preset of flip-flop G53 goes low to set the DMG
output high and the -DMG output low. The DMG high input to NAND gate 055 switches the output low
and goes to NOR gate G56. The BSACK L input is normally high and, when inverted by E24, is a low
input to the NOR gate G56. All three inputs to the NOR gate G56 are now low causing the output to

switch high. Two high inputs to the NAND gate G57 switch BDMGO hi, and then low thru E6 onto the
bus to the originator of the DMA request. The requesting device then sets the bus signal BSACK L low
and the BDMR L input high. BSACK L is inverted by E24 and removes the low from the NOR gate G56
and the high input to the NAND gate G57 causing the BDMGO output to go low. It also provides a high
input to NAND gate G52 causing the output to switch low. This low goes to the preset input of the flip-flop G50 and clamps the output high; this holds the microprocessor in the DMA mode. The requesting
device maintains the BSACK L input low for the duration of the DMA transfer and then sets it high. This
removes the low from the preset input of flip-flop G50 and enables the flip--flop. Previously, the BDMR L
input went high and was inverted as a low to flip--f1op G50. This low was clocked through by COVT and
provided a low input to the enabled flip--flop G50. The low is now docked through causing the -CDMRQ
output to go high. This removes the request from the microprocessor. The microprocessor completes the
DMA interrupt transaction and negates the SELl and SELO outputs. The preset input of flip--f1op G53 is
no longer low. and the low data input is clocked through when RAS goes high. The DMG output goes low,
and the -DMG output goes high to complete the DMA transaction.

B DMR L

G50

B SACK l

E24

BDMGO

COUT

--CDMRQ

CAS

-BClR
SEll
SELO

DMG
-DMG

-RAS

MR·t2135

Figure 8-22

8·30

DMA

8.16 TSYNC
The TSYNC output (Figure 8-23) is normally high for the microprocessor controlled fetch/read and write
transactions and low for IAK and DMA transactions. These conditions follow the -SELl input which is
high and low for the same transactions. The exclusive OR gate G61 is wired as a non inverting buffer. and
when RAS goes high, the -SELl input of the TSYNC flip-flop G60 is clocked through as the output.
When the -CSYNC clear input goes low, it forces the output of the TSYNC flip-flop G60 togo low. The
CSYNC flip-flop G60 normally has the clear input pulled low by TCLKSP and, the output to the AND
gate 062 is high. When the TCLKSP input goes high. the input of the CSYNC flip-flop is enabled. At this
time. the -DRRPLY clock input is low and goes high to clock the flip-flop before the TCLKSP input gets
reset-If a DMA transaction is in progress. the ....I)MG input is high and the CSYNC flip-flop output stays
low when clocked by -DRRPLY going high. For any transaction other than the DMA. the -DMG input
is low and the CSYNC flip-flop output goes high when clocked by -DRRPLY going high. This allows the
CSYNC output to go high and clear the TSYNC flip-flop G60, the write byte flip-flop G75. and the
disable flip-flop G73 as shown in Figure 8-25.
+3 v

-SEll

TSYNC
G60

RAS

-T SYNC
+3V

-DMG
GOO
-DRRPLY
-CSYNC

TClKSP
-Self!
MA-12136

Figure 8-23

TSYNC

8.17 READ/WRITE
The read/write logic (Figure 8-24) controls the read, write, and fetch transactions for the microprocessor
and supports the IAK and DMA transactions. The microprocessor controls the R/- WLB and R/- WHB
inputs to select either BDIN, BDOUT, or BWTBT bus signals. To select the BDIN output, the
microprocessor sets both R/-WLB and R/-WHB inputs high to NAND gate G72. The output goes low
to enable the NOR gate G76 and disables the AND gates G74 and 080. The -TSYNC input to G76 is
low for read/write transactions. When the '-CAS input goes low, the TREJ\D output goes high. The
TDIN output of OR gate 079 goes high. and the BDIN output of NAND gate 076 goes low. During
interrupt transactions, the IAKDIN input to G79is enabled high and causes TDIN to go high and BDIN
to go low.

The microprocessor determines any write condition· by setting either or both the R/- WLB or R/- WHB
inputs low. The output of NAND gate 072 goes high and enables the AND gates G80 and G74. The
output of flip-flop G73 is high, and the -CAS input to AND gate G74 is high, The output of AND gate
G79 goes high, and the output of OR gate G78 goes high, and allows the BWTBT output to go low. At this
time, the write destination address is written onto the bus. The logic now determines if the data being
written is a word or a byte. The exclusive OR gate G71 monitors the R/-WLB and R/-WHB inputs, and
the output goes high when the inputs are different. A high output indicates that the data is a byte; a low
output indicates that the data is a word. The output goes to flip-flop G75.

8-31

+3VDC

!
-SELl

-HAS

G73

I G70

-PI
-CAS

-...

' )-r

ES "",BWTST

roo-

J G71

G78

rl_

b+3V
r--l

f0-

G74

!-G75

P
9

-CSYNC
RIWLB
RIWHB

G72

~.
./

- J G7~

.......

-TSYNC

TREAD

G7G

BDIN
TDIN

IAKDIN
TDOUT

GOO

CAS
TSYNC
PI

)-l&>o

BOOUT

G77

MR-12131

Figure 8-24

Read/Write

The microprocessor asserts CAS. The CAS input to G75 and G77 goes high, and -CAS input to G74 goes
low. The -CAS input to AND gate G74 switches the output low to remove BWTBT, but the CAS input
clocks flip-flop G75 and enables the WBYTE signal to G78. The output of the flip-flop G75 is high for
byte transactions and low for word transactions. The BWTBT L signal will either stay asserted low for a
byte transaction or be negated high for a word transaction. The TSYNC and CAS inputs to AND gate
G77 are set high, and when the PI input goes high, the gate output goes high. The AND gate G80 is
enabled, and the output of G77 switches the TroUT output high. The TroUT is inverted. The BOOUT
output is enabled by going low and it writes the data word.
At the same time, the -RAS and -PI inputs to NOR gate G70 are both low, switching the output high.
The high clocks flip-flop G73, and the output goes low. This inhibits the AND gate G74 when the -CAS
input goes high again. The flip-flops are reset by CSYNC at the end of the transaction.

8.18 REPLY TIME-OUT
The reply time-out logic (Figure 8-25) monitors the bus BRPLY L input to indicate that an LSI-II bus
device responds to an address. The TMER flip-flop 083 output is normally set low by the RAS input to
clear tbe flip-flop. The BRPLY L input is high and inverted so the RRPLY output is low. The - TMRP
NOR pte inputs are both low, and the - TMRP output is high. The bus transaction is started by either
TDIN or TDOUT inputsgoin. high. This enables the 10 #lS time-out (50 cycle slips) to start. The
microprocessor starts to cycle slip while waiting for the BRPLY L input to go low, indicating tbe bus
transaction can complete. When BRPLY L switches low, the RRPLY output goes high and the - TMRP
output .oes low. The TMER output stays low. If the BRPLY L does not go low and tbe 50 p.s time-out
circuit allows the 50 cycle slips, the TMER flip-flop is clocked and the TMER output goes high. TMER
also forces tbe -TMRPoutput to go low. The assertion of the TMER output goes to tbe halt logic, and the
microprocessor action is dependent upon tbe configuration of the module. The - TMRP output goes to the
clock control and the ready logic. The RRPLY output goes to the bus control logic and enables bus data to
be received during LSI-II bus device reads.
RRPlY
-TMRP

BRPlY l

TMER

GB3

r----+--.---~ 10 usee

~~"ITIMER

Gas

TOIN
TOOUT

G82

RAS
"'''·12138

Figure 8-25 Reply Time-out

8.19 BUS CONTROL
The bus control logic (Figure 8-26) controls the transmit and receive functions of the bus transceivers. The

transceivers are in transmit mode for microprocessor controlled read/write and fetch transactions to local
memory, local I/O, and durina LSI-II bus writes. The transceivers go to the receive mode during an LSIII bus read. During DMA. the transceivers go to the receive mode to accept the local device address and
will stay in this mode until the device is addressed.. When a read transaction occurs, the transceivers go into
the transmit mode. When the -BCLR input is high, the transceivers are able to transmit data. When
-BCLR is asserted low, the transceivers are disabled. During an IAK transaction, the -IAK input to AND
pte 092 goes low to disable the transceiver high byte, and the low byte goes to the receive mode to accept
the vector.

8-33

TDAlo-15

-- I

READ

RHBI

-CSQ8

READ

.....

l-!DAlo-15

DC021
BUS
TRANSCEIVER
lOW BYTE
E30

I rl---/
_.... ' I

DMG
00

HIGH BYTE
E37

.......

TSYNC

.!!!
-BCLR
-IAK

1 002)

XHB

J
BINITL

MII·t2t.

Figure 8-26 Bus Control

The receive function of the bus transceivers will override the transmit function any time the receive inputs
are enabled high. When data is to be read from an LSI-II bus device, the -CSQB input is low and inverter
090 makes it a high input to AND gate 092. The TREAD input to AND gate 092 is set high for the
receive function. When the data is on the bus, the RRPLY input to AND gate 092 goes high and the
output of the gate goes high. The two OR gates G94 allow the high output to enable the receive low byte
and receive high byte inputs to the transceivers. The data is now read onto the TDAL bus. During an
interrupt transaction, the TIAKO input goes high and enables only the receive low byte input of the
transceivers.
The DMA transaction grants bus control to the external device that requested the direct memory grant.
The DMG input goes high for the duration of the DMA transaction. This input enables AND gate 093
and NAND gate 091. The BSYNC L input is high and inverted low to the two NAND gates 091. This
switches the NAND gate outputs high, and the receive and transmit functions are both enabled. However,
the receive function overrides the transmit function, and the TDAL bus receives data from the BDAL bus.
This condition stays until the bus master asserts the BDIN L input low. It is inverted high and enables the
NAND gate 091. The -CSQB input is dependent upon the address received from the BDAL bus. This
input is low if the address is a bus location and high if the address is for the local memory or I/O device. A
low input sets the output of NAND gate 091 high and enables the receive function of the transceivers. At
the same time, the -CSQB low input is inverted high. and the output of NAND gate G91 is switched low
to disable the transmit function. When the -CSQB input is high indicating the local memory is being
addressed, the NAND gate 091 is enabled. The -CSQB high input is also inverted low to NAND gate
091 and enables the receive function. The bus master now asserts either BDIN L or BOOUT L bus
signals. The -READ input goes low for the BDIN L signal and goes high for the BOOUT L signal. If
-READ goes high, it is inverted low and switches the output of NAND gate 091 high to enable the
receive function. If -READ goes low, it is inverted high and switches the output of NAND gate G91 low
to inhibit the receive function. The transmit function stays enabled. Therefore, when the bus master
asserts the BDIN L bus signal, the data is transmitted from the module and when it asserts the BOOUT L
bus signal, the data is received by the module even if it was not addressed.
The BBS7 L bus signal is enabled low when the bus addresses the I/O page during the address part of a
transaction. This is the upper eight kilobytes from 56Kb to 64Kb. This page is normally reserved for I/O
devices on the LSI~ 11 bus.
To address this page, the TDAL bus bits 13, 14, and 15 are set high and are inputs to NAND gate E 14.
The output is switched low and goes to the NOR gate E25. The SEll input to NOR gate E25 is low for
read, write, and fetch transactions. When both inputs to NOR gate E25 are low, the output is switched
high. This is inverted to a low for BBS7 L output and is inverted again to set RBS7 high.

8·35

CHAPTER 9
LSI-It BUS
9.1 INTRODUCfION
The LSI-It bus provides interconnections for LSI-II type modules, such as processors, memories, and
interfaces, to communicate with each other. Not all of the bus functions are supported by the SBC-ti/21
PLUS, and only the supported functions are described in this chapter. For a complete explanation of the
LSI-Il bus, see the PDP-I} Bus Handbook.
The LSI-II bus has forty signal lines; eighteen are used for data and twenty-two are used for controL The
SBC-II/21 PLUS supports only sixteen data lines and eighteen control lines.
There are four groups of control lines.

Six data transfer control lines:

a.
b.
c.
d.
e.
f.
2.

Four direct memory access control lines:

a.
b.
c.

d.
3.

BDMGI
BDMGO

BDMR
BSACK

Six interrupt control lines:

a.
b.
c.
d.
e.

f.
4.

BBS7
BDIN
BOOUT
BRPLY
BSYNC
BWTBT

BIAKI
BIAKO
BIRQ4

BIRQ5 (not used by SOC-II /21 PLUS)
BIRQ6 (not used by SBC·'} 1/21, PLUS)
BIRQ7 (not used by SOC-II /21 PLUS)

Six system control lines:

a.
b.
c.
d.
e.

BOCOK
BPOK
BHALT
BINIT
BREF (not used by SBC-tl/21 PLUS)

BEVNT

9-1

Most LSI· I 1 bus siJnals are bidirectional and use terminations for anegated (high) signal level. Modules
connect to these lines via high impedance bus receivers and open_collector drivers. The asserted state is
produced when a bus driver asserts the line low. Although bidirectional lines are electrically bidirectional
(any point on the line can be driven or received). certain lines are functionally unidirectional. These lines
communicate to or from a bus master or signal source. but not both. Interrupt acknowledge (BIAK) and
direct memory access grant (BDMG) signals are physically unidirectional in a daisy chain. These signals
start at the processor output signal pins. Each is received on device input pins (BIAKI or BDMGI) and
conditionally passed on via device output pins (BIAKO or· BDMGO). The BIAK and BDMG signals are
received from higher priority devices and are passed onto lower priority devices along the bus.

9.1 SBC-II/ll PLUS SINGLE-BOARD COMPUTER
The SBC·ll/21 PLUS module functions on the LSI·Il bus and can act as a bus master. a bus slave. or a
bus arbitrator. The module allows a DMA master to access the on·board functions. It supports only sixteen
data/address lines and terminates the other lines. It also contains its own on-board memory and accesses
the bus for external memory or devices. However. while accessing its on-board devices, the SBC-ll/21
PLUS asserts bus control signals as it docs when communicating with the LSI-II bus. The memory maps
defining on-board and external addressing are described in Chapter 2. The SBC-Il/21 PLUS
microprocessor supports an on-board multilevel interrupt structure, and the BIRQ4 bus interrupt control
line is an active bus interrupt with a level 4 priority. Therefore, the BIRQ5, BIRQ6, and BIRQ7 bus
control interrupt lines are not recognized or accepted by the SBC-II /21 PLUS module. The DMA request
is recognized by the module at the lowest interrupt level. Once the DMA master has accessed the bus,
there are no other interrupts until the transfer is complete or the DMA master relinquishes the bus. The
module docs not use or support the BREF control line for refreshing dynamic memory.

9.3 MASTER/SLAVE RELATIONSHIP
Communication betwee~ devices on the bus is asynchronous. A master/slave relationship occurs during
each bus transaction. At any time, there is one device that has control of the bus. This controlling device is
the bus master. The master device controls the bus when communicating with another device on the bus,
the slave. The bus master (the processor or a DMA device) starts a bus transaction. The slave device
responds by acknowledging the transaction in progress and by receiving data from, or transmitting data to,
the bus master. LSI-II bus control signals transmitted or received by the bus master or bus slave device
must complete the sequence according to bus protocol.
The processor controls bus arbitration, i.e., which device becomes bus master at any given time. A typical
example of this relationship is the processor, as master, fetching an instruction from memory, which is
always a slave. Another example is a disk, as master, transferring data to memory. as slave. Communication on the LSI-II bus is interlocked so that for certain control signals issued by the master device, there
must be a response from the slave in order to complete the transfer. It is the master/slave signal protocol
that makes the LSI-II bus asynchronous. The asynchronous operation eliminates the need for synchronizing with, and waiting for, clock pulses.
A bus cycle completion by the bus master requires a response from the slave device. Each bus master must
include a time-out error circuit that will abort the bus cycle if the slave device docs not respond to the bus
transaction within 10 p.S. The actual time before a time-out error occurs must be longer than the response
time of the slowest peripheral or memory device on the bus. Table 9-1 provides a summary of signals that
appear on the LSI· 1I bus.

9-2

Table 9-1

Signal Assignments

Number
of Pins

Functional
Category

Signal Names

Data/address

BDALO, BDALI, BDAL2 ... BDALI 5

Data control

BDOUT, BRPLY, BDIN, BSYNC, BWTBT,
BBS7

Interrupt control

BIRQ4, BIAKO, BIAKI

DMA control

BDMR, BDMGO, BDMGI, BSACK

System control

BHALT, BOCOK, BPOK, BEVNT, BINIT

+5 Vdc

+12 Vdc

-12 Vdc
+5 B (battery)

GND

SSPARES

MSPARES

PSPARES

9.4 DATA TRANSFER BUS CYCLES
Data transfer bus cycles are listed and defined in Table 9~2.
NOTE
Tbe SBC~11/2t PLUS microcomputer performs a
read transaction before every write transaction. It
does not perform DATlO or DATIO(B) bus transactions as one address. It executes read-modify-write
instructions by addressing the source as one transaction and addressing tbe destination as anotber
transaction.
These bus cycles, executed by bus master devices, transfer 16~bit words or 8-bit bytes to or from slave
devices. The bus signals that are listed in Table 9-3 are used in the data transfer operations that are
described in Table 9-2. Data transfer bus cycles can be lowered to two basic types; DATI, and DATO(B).
These transactions occur between the bus master and one slave device selected during the addressing
section of the bus cycle.

9-3

Table 9-2 Data Trusler Operations

Bus Cycle
Mnemonic

Description

Function (with respect
to the bus master)

DATI

Data word input

Read

DATO

Data word output

Write

DATO(B)

Data byte output

Write byte

Table 9-3 Bus Signals Used in Data Transfer Operations

Mnemonic

Description

Function

BDAL< 15:00> L

16 data/address lines

BDAL<15:00> L
are used for word
and byte transfers

BSYNC L

Bus cycle control

Strobe signal

BDIN L

I>ata input indicator

Strobe signal

BOOUT L

Data output indicator

Strobe signal

BRPLY L

Slave's acknowledge of
bus cycle

Strobe signal

BWTBT L

Write/byte control

Control signal

BBS7

I/O device select;
indicates address
is in the I/O page

Control signal

9.4.1 Bus Cycle Protocol
Before starting a bus cycle, the previous bus transaction must have been completed (BSYNC L negated)
and the device must become bus master. The bus cycle can be divided into two parts; an addressing section
and a data transfer section. During the addressing section. the bus master outputs the address for the
correct slave device, memory location, or device register. The selected slave device responds by latChing
the address bits and holding this condition for the duration of the bus cycle until BSYNC L becomes
negated. During the data transfer section, the actual data transfer occurs.

9-4

Device Addressing - The device addressing section of a data transfer bus cycle has an address set-up and
deskew time and an address hold and deskew time. During the address set-up and deskew time, the bus
master:

Asserts BDAL<15:00> L with the correct slave device address bits.

Asserts BBS7 L if a device in the I/O page (56Kb-64Kb for SOC- J 1/21 PLUS) is being
addressed. (Devices in the I/O page ignore BDAL< IS: 13> and decode BBS7 L with
BDAL<12:00>.)

Asserts BWTBT L if the cycle is a DA TO(B) bus cycle. (Inactive BWTBT L indicates a DATI
or DATIO(B) operation.)

Asserts BSYNC at least 150 ns after BDAL<15:oo> L, BBS7 L, and BWTBT L are valid.

The BBS7 L address and BWTBT L signal must be asserted at the slave bus receiver for at least 75 ns
before BSYNC goes active. The address hold and deskew time start after BSYNC L is asserted.
The slave device uses the active BSYNC L bus receiver output to clock BDAL address bits, BBS7 Land
BWTBT L, into its internal logic. BDAL<15:00> L, BBS7 L, and BWTBT L will stay active for 25 ns
(minimum) after the BSYNC L bus receiver goes active. BSYNC L stays active for the duration of the
bus cycle.
Memory devices usually do not respond to addresses in the I/O page; however, some system applications
may permit memory to reside in the I/O page for use as DMA buffers, read only memory bootstraps, or
diagnostics. etc.
DATI - The DATI bus cycle, shown in Figure 9-1, is a read operation. During DATI, data is input to the
bus master. Data uses J6-bit word transfers over the bus. During the data transfer section of the DATI bus
cycle, the bus master asserts BDIN L lOOns (minimum) after BSYNC L is asserted. In response to BDIN
L active, the slave device:

Asserts BRPL Y L after receiving BDIN Land 125 ns (maximum) before BDAL bus driver
data bits are valid.

Asserts BDAL<15:00> L with the addressed data.

When the bus master receives BRPL Y L, the bus master:
I.

Waits at least 200 os deskew time and then accepts input data at BDAL<15:oo> L bus
receivers.

Negates BDlN L 150 ns (minimum) to 2 J,lS (maximum) after BRPLY L goes active.
NOTE
Continuous assertion of BSYNC L keeps control of
the bus under the bus master, and the previously
addressed slave device remains selected. Also, a slow
slave device can hold off data transfers to itself by
keeping BRPL Y L asserted. This will cause the
master to keep BSYNC L asserted.

9-5

BUS MASTER
(PROCESSOR OR DEVICE)

SLAVE
(MEMORY OR DEVICE)

ADDRESS DEVICE MEMORY
• ASSERT 80Al <15-00> L
ADDRESS AND
• ASSERT 8857 IF THE ADDRESS
IS IN THE 56·64KB RANGE
• ASSERT BSYNC L

REQUEST DATA
• REMove THE ADDRESS FROM
BOAL <11)..00> lAND
NEGATE B857 L
• ASSERT BDIN L

TERMINATE INPUT TRANSFER
• ACCEPT DATA AND RESPOND
BY NEGATING SDIN L

TERMINATE BUS CYCLE
• NEGATE BSYNC L

----- -- ------

,..----

---- ---

---- -----.....----

----.,.

----

---- --

INPUT DATA
• PLACE DATA ON SOAl <15-00> L
_ _ _ ~. ASSERT BRPLY L

-----..

___ - - - - -

Figure 9-1

DeCODE ADDRESS
• STORE DEVICE SELECTED
OPERATION

OPERA nON COMPLETED
- - . NEGATE BRPlY L
• REMOVE DATA FROM
BDAL <15-00> L

DATI Bus Cycle

The slave device responds to BDIN L negation by negating BRPLY L and removing read data from
BDAL bus drives. BRPLY L must be negated 100 ns (maximum) before removal of read data. The bus
master responds to the negated BRPLY L by negating BSYNC L.
Two conditions must be met for the next BSYNC L assertion:
1.

BSYNC L must remain negated for 200 ns (minimum).

BSYNC L must not become asserted within 300 ns of the previous BRPLY L negation.

Figure 9-2 illustrates DATI bus cycle timing.

9-6

TIMING AT MASTER DEVICE
. (41

RDATA

(4t

TSYNC

100 ns MIN

TOIN

a"s MAX

R RPLY

('00 ns

TOS7J
TWTBT ~

MIN
(4)

!4)

TIMING AT SLAVE DEVICE

R SYNC

--+~"'I

R DIN _ _ _-+-_-F\
T RPLY

--------P--------J

R £157

NOTES:
1.

TIMING SHOWN AT MASTER AND SLAVE DEVICE BUS DRIVER
INPUTS AND £IUS RECEIVER OUTPUTS

SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T ~ BUS DRIVER INPUT
R ~ BUS RECEIVER OUTPUT

BUS DRIVER OUTPUT AND BUS RECEIVER INPUT SIGNAL
NAMES INCLUDE A "8" PREFIX

DO NOT CARE CONDITION
MIHIlIO

Figure 9-2

DATI Bus Cycle Timing

9-7

DATO(B) - DATO(B). illustrated in Figure 9·3, is a write operation. Data is transferred in 16-bit words
(DA TO) or 8-bit bytes (DATO(B» from the bus master to the slave device. The data transfer output can
occur after the addressing section of a bus cycle when BWTBT L has been asserted by the bus master.

The data transfer section of a DATO(B) bus cycle makes a data set-up and deskew time and a data hold
and deskew time. During the data set-up and deskew time, the bus master outputs the data on
BDAL<15:00> L at least 100 os after the BSYNC L is asserted. If it is a word transfer, the bus master
negates BWTBT L at least 100 os after BSYNC L assertion. BWTBT L stays negated for the length of the
bus cycle. If the transfer is a byte transfer. BWTBT L remains asserted. During a byte transfer, BDAL 00
L selects the high or low byte. This occurs while in the addressing section of the cycle. If asserted, the high
byte (BDAL<15:08> L) is selected; otherw~, the low byte (BDAL<07:00> L) is selected. The bus
master asserts BooUT L at least 100 ns after BDAL and BWTBT L bus drives are stable. The slave
device responds by asserting BRPLY L within 10 p.s to avoid bus time-out. This completes the data set-up
and deskew time.
During the data bold and deskew time, the bus master receives BRPLY L and negates BOOUT L.
BOOUT L must stay asserted for at least 150 ns after receiving BRPLY L before being negated by the bus
master. BDAL<t5:00> L bus drivers stay asserted for at least 100 ns after BOOUT L negation. The bus
master then negates BDAL inputs. During this time, the slave device senses BnOUT L negation. The data
is accepted, and tbe slave device negates BRPLY L The bus master responds by negating BSYNC L.
However. the processor will not negate BSYNC L for at least 175 ns after negating BOOUT L. This
completes the DATO(B) bus cycle. Before the next cycle, BSYNC L must stay unasserted for at least 200
ns. Figure 9-4 shows the DATO(B) bus cycle timing.

9.4.2 Direct Memory Access
DMA is started after the processor (normally bus master) has passed bus mastership to the highest priority
DMA device that is requesting the bus. The processor arbitrates all requests and grants the bus to the
DMA device electrically closest to it. A DMA device remains a bus master until it relinquishes its
mastership. The following control signals are used during bus arbitration.
I.
2.
3.
4.

BDMGI L
BDMGO L
BDMR L
BSACK L

DMA grant input
DMA grant output
DMA request line
Bus grant acknowledge

A DMA transaction can be divided into three phases:
I.
2.
3.

Bus mastership acquisition phase
Data transfer phase
.Bus mastership relinquish phase

During the b~ mastership acquisition phase, a DMA device requests the bus by asserting BDMR L. The
processor arbitrates the request and starts the transfer of bus mastership by asserting BDMGO L The
maximum time between BDMR L assertion and BDMGO L assertion is DMA latency. This is processor
dependent. BDMOO L/BDMGI L is one signal that is daisy chained through each module in the
backplane. It is driven out of the processor on the BDMGO L pin. enters each module on the BDMGI L
pin. and exits on the BDMGO L pin. This signal passes through the modules in descending order of priority
until it is stopped by the requesting device. The requesting device blocks the output of BDMGO Land
asserts BSACK L. If BDMR L is continuously asserted. the bus will be hung.

9-8

T OAt

T AVDR

'-'50NS
t-M'NIMUM

X------T-DA-~------~

, 0 NS MINIMUM

~loo
NS
MINIMUM

1'-100 NS MINIMUM

t--

141

TSYNC
8jJS ~
MAXIMUM

1,..-------'"""

TOOUT

'-'----300 NS MINIMUM
fI flPlY

TBS7

(41

TWTBT

(4)

lOONS
MINIMUM

TIMING AT MASTER DEVICE

R OAL

..IX R AnnR X

_=_1_4_' _ _

X~25

R DATA
25 NS MINIMUM

(4)

NS MINIMUM

RSYNC
100 NS MINIMUM--.c:l50 NS MINIMUM

75NS
MINI.MUM

RDOUT

lOONS

;..M_IN_I_M_U_M-+_--l~

Ite--- 300 NS MINIMUM

T flPLV

RSS]

fI WTIT

(41

j4)

J::

ASSERTION = BYTE

(4)

25 NS MINIMUM

TIMING AT SLAVE DeVICE
NOTES:
1. TIMING SHOWN AT MASTER AND SLAVE DEVICE
BUS DRIVER INPUTS AND BUS RECEIVER OUTJ>UT8.

2. SIGNAL NAME J>fl£F!XES ARE DEFINED aELOW;
T =BUS DRIVER INPUT
R : SUS RECEIVER OUTPUT

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUoe A "8" PREFIX.
4. DON'T CARE CONDITION.

Mfl \$79

Figure 9·4

DATO or DATOB Bus Cycle Timing

9-10

During the data transfer phase, the DMA device continues asserting BSACK L. The aetua' data transfer is
performed as described previously.

NOTE
If multiple data transfers are performed during this
phase. consideration must· he given to the use of the
IJus for other system functions.
The DMA device can assert BSYNC L for a data transfer 250 ns (minimum) after it receives BDMGI L
and its BSYNC Land BRPLY L become negated.
During the bus mastership relinquish phase, the DMA device relinquishes the bus by negating BSACK L.
This occurs after completing (or aborting) the last data transfer cycle (BRPLY L negated). BSACK L may
be negated up to a maximum of 300 ns before negating BSYNC L. Figure 9-5 shows the DMA protocol,
and Figure 9-6 shows the DMA request/grant timing.
SSC·Ul2t PLUS

BUS MASTER
(CONTROLl.ERI

MICROPROCESSOR
(MEMORY IS SLAVE)

_ REQUEST BUS
• ASSERT 8DMR L

....... ------------ - -..,---- --..,._
--------_ ... - -

GRANT BUS CONTROL
• NEAR THE END OF THE
CURRENT BUS CYCLE
....
(BRPlY LIS NEGATED).
ASSERT BDMGO LAND
INHIBIT NEW PROCESSOR
GENERATED 8YSNC L FOR
THE DURATION OF THE
DMA OPERATION.

...

ACKNOWLEDGE BUS
MASTERSHIP
... • RECEIVE BDMG
• WAIT FOR NEGATION OF
BSYNC LAND BRPLY L
• ASSERT BSACK L
• NEGATE SDMR L

....

TERMINATE GRANT
SEOUENCE
_-• NEGATE BDMGO LAND
_
WAIT FOR DMA OPERATION
- ... __ _
TO BE COMPLETED
- - __

-- -- ......
.......

------......
-.....
....

RESUME PROCESSOR
OPERATION
• ENABLE PROCESSOR·
GENERATED BSYNC L
(PROCESSOR IS BUS
MASTER) OR ISSUE
ANOTHER GRANT IF SDMR
L IS ASSERTED.

eXECUTe A DMA DATA
TRANSFER
• ADDRESS MEMORY AND
TRANSFER UP TO 4 WORDS
OF DATA AS DESCRIBED
FOR DATI, OR DATO BUS
CYCLES
• RELEASE THE BUS BY
TERMINATING 8SACK L
INO SOONER THAN
NEGATION OF LAST BRPL Y
II AND BSYNC l.

WAIT 4j.tsOR UNTIL
ANOTHER FIFO TRANSFER
IS PENDING BEFORE
REQUESTING BUS AGAIN.

Figure 9-5

DMA Protocol

9-11

seCOND
REQUEST
TDMR _ _ _J

R DMG _ _ _ _-'"

TSACK

------;1---+'1'

R/TSYNC

R/T RPLY
I--OnsMIN.

Ie--O ns M I N . _ , _ - - - - -....

iA~BS7--------------JAt:A€DR X~

_____

DA_T_A____

~~------

WTBT,REF)
NOTES:
1 TIMING SHOWN AT REQUESTING DEVICE BUS DRIVER
INPUTS AND BUS RECEIVER OUTPUTS.
2 SIGNAL NAME PREFIXES ARE DEFINED BELOW
T = BUS DRIVER INPUT
R • BUS RECEIVER OUTPUT
3 BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A "B" PREFIX
MR·7t18

Figure 9-6

DMA Request/Grant Timing

9.5 INTERRUPrS
The LSI-II bus signals used in interrupt transactions are:
I. BIRQ4 L
2. BlAKI L
3. BIAKO L
4. BDAL<lS:00> L
S.BDIN L·
6. BRPLY L

Interrupt request priority level 4
Interrupt acknowledge input
Interrupt acknowledge output
Data/address lines
Data input strobe
Reply

9.5. t Deyke Priority
The SBC-ll/21 PWS supports only one method of device priority arbitration; position defined arbitration (priority is determined only by electrical position on the bus). The closer a device is to the processor,
the higher its priority.
9.5.1 laterrupt Protoeoi
Interrupt protocol on the SBC-l1 /21 PLUS has three phases:
I.
2.
3.

Interrupt request phase
Interrupt acknowledge and priority arbitration phase
Interrupt vector transfer phase

Figure 9-7 shows the interrupt request/acknowledge sequence.

9·12

•

sec- Ul2l PLUS

DEVICE

MiCROPROCESSOR

STROBE INTERRUPTS
• ASSERT 8DIN l

I
I

--------

(HITIA TE REQUEST
_ . ASSERT BIR04 L

.--

-----. ----...

RECEIVE BorN L
• STORE INTERRUPT SENDING
IN DEVICE

GRANT REOUEST
• PAUSE AND ASSERT BIAKO l

---- ----------

---..,
RECEIVE BIAKI l
• RECEIVE BIAKI L AND INHIBIT
BIAKO l
• PLACE VECTOR ON BOAL <15-00> L
• ASSERT BRPlY l

_ . NEGATE BIRO L

--.-

RECEIVE VECTOR lit TERMINATE
REQUEST
• INPUT veCTOR ADDRESS

• NEGATE BDtN LAND BIAKO L

PROCESS THE INTERRUPT
• SAVE INTERRUPTED PROGRAM
PC AND PS ON STACK
• LOAD NEW PC AND PS FROM
VECTOR ADDRESSED lOCAnON
• eXECUTE INTERRUPT SERVICE
ROUTINE FOR THE DEVICE

-------. ----. ---- --..

----

.---

COMPLETE VECTOR TRANSFER
• REMOVE VECTOR FROM BOAL BUS
_ _ ... NEGATE BRPl Y L

""Hli1

Figure 9-7

Interrupt RequestlAcknowledge Sequence

The interrupt request phase starts when a device meets its specific conditions for interrupt requests (e.g.•
the device is ready, done. or an error has occurred). The interrupt enable bit in a device status register
must be set. The device then sets up the interrupt by, asserting the interrupt request line. BIRQ4 L is the
only hardware priority level on the SBC-1l/2l PLUS and is asserted for all interrupt requests. The
interrupt request line stays asserted until the request is acknowledged.
During the interrupt acknowledge and priority arbitration phase, the SBC-ll/21 PLUS prooessorwill
acknowledge interrupts under the following conditions:

The device interrupt priority is higher than the current PS<7:5>.

The processor has completed instruction execution, and no additional bus cycles are waiting.

9-13

The processor acknowledges the interrupt request by asserting BDIN L, and, 225 ns (minimum) later,
asserting BIAKO L. The device electrically closest to the processor receives the acknowledge on its BIAKI
L bus receiver.
When the device receives the acknowledge, it reacts as follows:

If not requesting an interrupt, the device asserts BlAKO L, and the acknowledge moves to the
next device on the bus.

If the device was requesting an interrupt, the acknowledge is blocked using the leading edge of
BDI N Land arbitration is granted. The interrupt vector transfer phase begins.

The interrupt vector transfer phase is enabled by BDlN Land BIAKI L. The device responds by asserting
BRPLY L and its BDAL<15:00> L bus driver inputs with the vector address bits. The BDALbus driver
inputs must be stable within 125 ns (maximum) after BRPLY L is asserted. The processor then inputs the
vector address and negates BDIN Land BIAKO L. The device then negates BRPL Y Land, lOOns
(maximum) la~er, removes the vector address bits. The processor then enters the device's service routine.
NOTE
Propagation delay from BIAKI L to BIAKO L must
not be greater than SOO ns per LSI·l t bus slot.
The device must assert BRPL Y L within 10 }.LS
(maximum) after the processor asserts BIAKI L.
9.6

CONTROL FUNCTIONS

The following LSI-II bus signals provide control functions.
1.

2.
3.
4.

5.
9.6.1

BHALT L
BlNIT L
BPOK H
BDCOK H
BEVNT L

Processor halt
Initialize
Power OK
DC power OK
External event

Hait

Refer to Chapter 2 for an explanation of the BHALT L response.
9.6.2

Initialization

Devices on the bus are initialized when BINIT L is asserted. The microprocessor can assert BINIT L as a
result of executing a RESET instruction or as part of a power-up sequence. BINIT L is asserted for
approximately 17 J.Ls when RESET is executed.
9.6.3

Power Status

Power status protocol is controlled by two signals, BPOK Ii and BDCOK H. These signals are driven by
some external device (usually the power supply).
BPOK H - When asserted. BPOK H indicates that there is at least an 8 ms reserve of de power and that

BOCOK H has been asserted for at least 70 ms. Once BPOK H has been asserted, it must stay asserted for
at least 3 ms. The negation of this line, the first event in the power fail sequence, indicates that power is

failing and that only 4 ms of de power reserve remain.
BOCOK H - When asserted, BOCOK H indicates that dc power has been stable for at least 3 ms. Once
asserted, this line stays asserted until the power fails. Its negation indicates that only 5 J.LS of dc power

reserve remain.
9-14

9.6.4 Power-Up/Power-Down Protocol
Power·up protocol (Figure 9-8) begins when the power supply applies power with BOCOK Hnegated. This
forces the processor to assert BINIT L. When the dc voltages are stable, the power supply, or other
external device. asserts BOCOK H. The processor responds by clearing the PSW. BINIT L remains
asserted until the assertion of BDCOK H. The processor.continues to test for BPOK H until it is asserted.
The power supply asserts BPOK H 70 ms (minimum) after BOCOK H is asserted. The processor then
performs its power-up sequence. Normal power must be maintained at least 3 ms before a power-down
sequence can start.
A power-down sequence starts when the power supply negates BPOK H. When the current instruction is
completed. the microprocessor traps to a power-down routine at location 24. The routine must provide for
loading 340 into the PSW, execute a RESET instruction, and terminate in a WAIT instruction or branch
on itself. There should be no DMA requests issued after the RESET is executed. This prevents any
possible memory destruction in the battery supported system as the de voltages fail.

NOTE
SBC-H/21 PLUS does not generate BINIT L during the power-down sequence. The power-down routine must therefore include a RESET instruction to
set bus devices into a known state.

SOFTWARE
CONTROLLED

-I

-3msMIN ~
BPOKH

...

BOCOK H

-lloi 31m

MIN

DC POWER

70msMIN

f0l-

AO"'O

P!II

,50IISMAX

BINITL

HARDWARE

~
200msr-

MAX

Io!- 4ms MIN---

A
70msMIN f+-

51's MIN

BmsMIN

,U
I"\.,

-fJ
POWER UP

~SEQUENCE

NORMAL

POWER·DOWN

POWER UP

POWER

SEQUENCE

NOTE:
ONCE A POWER DOWN SEQUENCE IS STARTED.
IT MUST BE COMPLETED BEFORE A POWER UP
SE~UENCE IS STARTED.

Figure 9-8

Power·Up/Power~Down Timing

9-15

NORMAL...
POWER

9.7 LSI-II BUS ELECTRICAL CHARACTERISTICS
Configuring LSI·li bus systems requires an understanding of its transmission line characteristics. For a
discussion of these characteristics, see the PDP-! I Bu:. Handbook.
9.8 MODULE CONTACT FINGER IDENTIFICATION
AU Digital plug-in modules, including the SBC-lI/2l PLUS, use the same contact finger (pin) identification system. The LSI-II bus is based on the use of double-height modules that plug into a 2-510t bus
connector. Each slot contains thirty-six lines (eighteen each on both the component and solder sides of the
circuit board),
Slots. shown as row A and row B in Figure 9-9, include a numeric identifier for the side of the module. The
component side is defined as side 1; the solder side is defined as side 2. Letters A through V (except G, l,
O. and Q) identify a specific pin on a side of a slot. Table 9·4 lists and identifies the bus pins of the doubleheight module. For a summary, refer to Table 1·1. The bus pin identifier terminating with a 1 is found on
the component side of the board; a bus pin identifier terminating with a 2 is found on the solder side of the
board. A typical pin is defined as follows:
AE2: row A, pin E, side 2
The positioning slot between the two rows of pins matches with a guide on the connector block for correct
module positioning.

ROW A

ROWS

MR·7111

Figure 9-9

Double-Height Module Contact Finger Identification

9-16

Table 9-4

Bus Pin Identifiers

Bus Pin

Mnemonic

Description

AEl

SSPAREl
(alternate +5B)

Special spare - not assigned or bused in Digital cable or
backplane assemblies; available for user connection. Optionally, this pin may be used for +5 V battery (+5B) backup
power to keep critical circuits alive during power failures. A
jumper is required on LSI-II bus options to open (disconnect) the +5B circuit in systems that use this line as
SSPAREI.

AFI

SSPARE2

Special spare - not assigned or bused in Digital cable or
backplane assemblies; available for user interconnection.

AJI

GND

Ground - system signal ground and de return.

AKI
ALI

MSPAREA
MSPAREA

AMI

GND

Ground - system signal ground and de return.

AN)

BDMR L

Direct memory access (DMA) request - a device asserts this
signal to request bus mastership. The processor arbitrates bus
mastership between itself and all DMA devices on the bus. If
the processor is not bus master (it has completed a bus cycle,
and BSYNC L is not being asserted by the processor), it
grants bus mastership to the requesting device by asserting
BDMGO L. The device responds by negating BDMR Land
asserting BSACK L.

API

BHALT L

Processor halt - refer to Chapter 2.

ATt

GND

Ground - system signal ground and de return.

AUt

PSPAREI

Spare - not assigned; customer usage not recommended;
prevents damage when modules are inserted upside down.

AVI

+5B

+5 V battery power - secondary +5 V power connection.
Battery power can be used with certain devices.

BAI

BOCOK H

DC power OK - power supply~generated signal that is asserted when there is sufficient dc voltage available to sustain
reliable system operation.

BBI

BPOKH

Power OK - asserted by the power supply 70 ms after
BOCOK. Negated when ac power drops below the value
required to sustain power (approximately 75% of nominal).
When negated during processor operation, a power fail trap
sequence is initiated.

Maintenance spare - normally connected together on the
backplane at each option location (not a bused connection).

Table 9-4

Bus Pin Identifiers (Cont)

Bus Pin

Mnemonic

Description

BHI

SSPARE8

Special spare - not assigned or bused in Digital cable and
backplane assemblies; available for user interconnection.

BJI

GND

Ground - system signal ground and dc return.

SKI

BLI

MSPAREB
MSPAREB

BM!

GND

Ground - system signal ground and dc return.

BNI

BSACK L

This signal is asserted by a DMA device in response to the
processor's BDMGO L signal, indicating that the DMA
device is bus master.

BRI

BEVNT L

External event interrupt request - when asserted"the processor responds (if PS bit 7 is zero) by entering a service routine
via vector address 100. A typical use of this signal is a line
time·clock interrupt.

BSI

PSPARE4

Power spare 4 - not assigned a function; not recommended
for use.

BTl

GND

Ground - system signal ground and de return.

BUI

PSPARE2

Power spare 2 - not assigned a function; not recommended
for use. If a module is using -12 V (on pin AB2) and if the
module is accidentally inserted upside down in the backplane,
-12 V de appears on pin BU L

BVI

+ 5 V power - normal +5 Vde system power.

AA2

+5 V power - normal +5 Vdc system power.

AB2*

-12

-12 V power - -12 Vde (optional) power for devices requiring this voltage.

AC2

GND

Ground - system signal ground and de return.

AD2

+12

+12 V power - 12 Vde system power.

AE2

BOOUT L

Data output - BDOUT, when asserted, implies that valid
data is available on BDAL<O; 15> L and that an output
transfer, with respect to the bus master device. is taking
place. BOOUTL is deskewed with respect to data on the bus.
The slave device responding to the BOOUT L signal must
assert BRPLY L to complete the transfer.

Maintenance spare - normally connected together on the
backplane at each option location (not a bused connection).

9-18

Tattle 9-4 Bus Pin . Identlrrers (Cont)
Bus Pin

Mnemonic

DescriptioA

AF2

SRPLY L

Reply -BRPLY l is asserted in response to BDIN l or
SnoUT L and during IAK transactions. It is generated by a
slave device to indicate that it has placed its data on the
BDAL bus or that it has accepted output data from the bus ..

AH2

BDIN l

Data input - BDIN L is used for two types of bus operation:

When asserted during BSYNC L time, BDIN L implies
an input transfer with respect to the current bus master
and requires a response (BRPl Y L). BDIN L is asserted
when the master device is ready to accept data from a
slave device.

When asserted without BSYNC L, BUIN L indicates.
that an· interrupt operation is occurring.

The master device must deskew input data from BRPL Y L.
AJ2

BSYNC L

Synchronize :.... BSYNC L is asserted by the bus master
device to indicate that it has placed an address on
BDAL<O: 15> L. The transfer is in process until BSYNC L is
negated.

AK2

BWTBT L

Write/byte - BWTBT L is used in two ways to control a bus
cycle:

AL2

BIRQ4 L

AM2

BIAKI L
BIAKO L

AN2

It is asserted at the leading edge or BSYNC L to indicate that an output sequence is to follow (DATO or
DATO(B», rather than an input sequence.

It is asserted during BnoUT L, in .aDATO(B) bus
cycle, for byte addressing.

Interrupt request priority level 4 - a level 4 device asserts this
signal when its interrupt enable and interrupt request flipsnops are set. If the PSW bit 7 is zero, the processor responds
by acknowledging the request by asserting BDIN Land
BIAKO L.
Interrupt acknowledge - in accordance with interrupt proto-col. the processor asserts BIAKO L to acknowledge receipt of
an interrupt. The bus transmits this to BIAKI L of the device .
electrically cfosest to the processor. This device accepts the
interrupt acknowledge under two conditions:
I.

The device requested the bus by asserting BIRQ4 L .

. 9-19

.....

Tallie,.. . . PIa ldeatifiers (Coat)
MaeBlOllle

DesctIpdoa

Tbe device, has the highest priority interrupt request on
the bus at that time.

If these conditions are not met, the device asserts BIAKO L
to the next device on the bus. This process continues in a
daisy chain fashion until the device with the highest interrupt
priority receives the interrupt acknowledge sipal.
AP2

BBS7 L

AR2
AS2

BOMGI L
BDMGOL

Bank 1 select - the bus master asserts this signal to reference
the I/O page (includina that portion of the I/O page reserved
for ROIleXistent memory). The address in BOAL<O: 12> L
when B8S7 L is asserted is the address within the I/O page.
Direct memory access grant - the bus arbitrator asserts this

signal to grant bus mastership to a requestina device accord·
ina to bus ma.sta"sbip protocol. The sianal is passed in a daisy
chain from the arbitrator (as BDMGO L) through the bus to
BOMGI L of the next priority device (electricaUy closest
device on the bus). This device accepts the grant only if it
requested to be bus master (by a BOMR L). If not, the device
passes the ~t (asserts BDMGO L) to the next device on
the bus. This process continues until the requesting device
aclmowl~es the grant.

AT2

BINIT L

Initialize - thissianal is used for system reset. AU devices on
the bus are to return to a known, initial state (Le., resisters
are reset to. zero, and logic is reset to state zero). Exceptions
should be. completely documented in proaramming and ~ngi.
neering sPeCifications for the device.

AU2
AV2

BDALOL
BOALIL

BA2

+5 V power - normal +5 Vdc system power~

882

-12

-12 V power - ,-12 Vdc (optional) pow« for devices requir. ina this voItaJC.

BCZ

GND

. Ground - system sipa1 .grouad and de return.

802

+12

+12 V power - +12 V system power.

Data/addreSs lines - these two lines are part of the sixteenline data/address bus over which address • .data information are communicated. Address information is rust pIaaJd
on the bus by the bus master device. The same device thea
either receives input. data from. or outputs data to, the
addressed slave. device or memory over the same bus lines.

•

9·20

Table 9-4

Bus Pin Identifiers (Cont)

Bus Pin

Mnemonic

Description

BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2

BDAL2 L
BDAL3 L
BDAL4 L
BOAL5 L
BDAL6 L
BDAL7 L
BOAL8 L
BDAL9 L
BDALlO L
BOALll L
BDALl2 L
BDALI3 L
BDALl4 L
BDALl5 L

Data /address lines - these fourteen lines are part of the
sixteen-line data/address bus previously described.

LSI-II modules that require negative voltages contain an inverter circuit (on each module) that generates the required
voltage(s). Hence, -12 V power is not required with Digital-supplied options.

9-21

APPENDIX A
INSTRUCTION TIMING

The fetch and execute times listed in Table A-I assume that the SBC-lI/2l PLUS is transru;ting with
local devices that do not require cycle slips when accessed.
Table A-I

Single Operand
Instructions

Destination
Mode

CLR(B), COM(B),
INC(B), DEC(B),
NEG(B), ROR(B).
ROL(B). ASR(B),
ASL(B), SWAP,
ADC(B). SBC(B),
SXT, MFPS,
XOR

TST(B)

I
2
3
4
5
6
7

Fetch and
Execute
Time (~s)
2.44
4.27
4.27
5.49
4.88

Number of

Bus
Transactions

Number· of
Microcydes
4
7
7

6.10
6.10

3
3
4
3
4
4

9
8
10
10

7.32

2.44

I
2

3.66

2
2

4
6
6

2
3
3

7
9
9
II

3
4

5
6
7

MTPS

Instruction Timing

3.66
5.49
4.27
5.49
5.49
6.71

4.88

6.10

2
3

6.10

4
5
6

7.32
6.71
1.93
7.93
9.16

1
2
2
3

8
10

to
12

13
13

3
4

Table A-I

Instruction Timing (Cont)

Instructions

Source Mode

Source Mode
Time ~s)
Includes
Fetch

MOY(B), CMP(B),
ADD, SUS.
BIT(S). BIC(S),
BIS(S)

0
I
2
3
4
5
6
7

1.83
3.05
3.05
4.27
3.66
4.88
4.88
6.10

Double Operaad
Instructions

Destination
Mode

Destination
Mode
Time ~s)

MOY(S), CMP(B),
ADD, SUB,
BIT{B). BIC(B),
BIS(B)

0
1

Double Operaad

2
3
4
5
6

7
0
I

JMP

3
5

3
2

7
6

8
8
10

3
4
Number of

Bus
Transactions

4.27

3
3
4

7
7
9

0
I

1
3
3

4.27
5.49

2
3

Transactions

3.05
3.66
3.66
3.66
4.27
4.21
5.49

2
3
2
3
3
4

5
6
7

1
4
4
6

0
2

Fetch and
Execute
Time (~)

1
2
3
4

Number of
Microcycies

0.61
2.44
2.44
3.66
3.05

Destination
Mode

Number of
Microcycles

3
4
6

Jump and
Subroutirte
Instructions

Bus
Transactions

0.61
1.83
1.83
3.05
2.44
3.66
3.66
4.88

CMP(B), BIT(B)

Number of

1
2

1
2
2

4
6
6
8

3
Number of

Bus
2

Number of
Microcydes

5
6

6
7
7
9

Table A-I

Instruction Timing (Cont)
Number of
Bus
Transactions

Number of
Microcydes

5.49

6.10
6.10
6.10
6.71
6.71

7.90

5
6

10
10
10
11
11
13

RTS

4.27

SOB

3.66

Brancb. Trap,
and Interrupt
Instructions

Destination
Mode

fetch and
Execute
Time (ps)

BR, BNE, SEQ.
BPl, BMI, BVe.
BVS. Bee, BeS,
BGE. BlT, BOT.
BlE, BHI, BlOS,
BHIS, BlO

2.44

EMT, TRAP,
BPT, lOT

9.77

RTf

4.88

RTT

6.71

Miscellaneous
and Condition
Code
Instructions

Destination
Mode

f'etcb and
Execute
Time (ps)

Number of
Bus
Transactions

Number of
Microcycles

HALT

8.54

WAIT

2.44

Single Operand
Instructions

JSR

Destination
Mode
1
2
3
4

Fetch and
Execltte
Time (ps)

5
4

6
Number of
Bus
Transactions

Number of
Microcydes
4

then loop
RESET

22.28

A·3

Table A-I

Instruction Timing (Cont)'

Slagle Operand

Destination

Instructions

Mode

Fetch and
Execute
Time (~s)

NOP

3,66

CLC, elY, CLZ,
CLN, CCC. SEC.

3.66

3.05

Number of
Bus
Transactions

Number of
Microcycles

SEV, SEZ, SEN,

sec

MFPT

The measure of LSI~ I I bus interrupt latency is the time from the assertion of BlRQ until BIAKI is

accepted by the interrupting device electrically closest to the processor on the LSI-II bus.
The measure of local interrupt latency is the time from assertion of the request until the time the
microprocessor is ready to fetch the first instruction in the interrupt service routine. This time is primarily
comprised of the time to perform two pushes and a PC and PSW restore.
Interrupt Latency:

lOCAL
LSI-II BUS

23.2 ~
9.3 }.lS

NOTE
Assume that the stack and vector memory reside on
the SBC-tl/ll PLUS and that the LSI-ll bus
device can assert BRPLY and vector within 600 us
after receiving IAKI. The service latency (time from
BIRQ until the time the microprocessor is ready to
fetch the first instruction in the interrupt service
routine) depends on the response time of the interrupting device (i.e., RDIN to TRPL Y and negation
of TRPLY).
DMA latency is the period of time between a device asserting its BDMR and receiving BDMGI when it
resides on the LSI·ll bus as the electrically closest DMA device to the processor.
DMA latency:

1.3 ~s (minimum)

WAIT instruction latencies:
Internal vector:
External vector:

11.8 JLS
12.4 ~s

DMA:

5.06.J,1.s

A-4

11.0 ~ (maximum)

APPENDIX B
PROGRAMMING DIFFERENCE LIST

DIFFERENCES BETWEEN THE SBC-ll/21 PLUS, LSI-ll/2, AND LSI-ll/23
Table B-1 presents a concise comparison of the SBC-ll/21 PLUS, LSI-JI/2, and LSI-l 1/23 modules.
Table B-1 SBC-ll/21 PLUS, LSI-ll/2, and LSJ-lJ/23 Comparisons
Activity

SBC-ll/21
PLUS

LSI·ll/2

LSI·U/23

OPR %R,(R}t or OPR %R,-(R)
using the same register as both
source and destination: contents
of 'R' are incremented (decremented)
by two before being used as the
source operand.

X·

OPR %R,@(R)+ or OPR %R,@-(R)
using the same register as both
source and destination: contents
of 'R' are incremented (decremented)
by two before being used as the
source operand.

In the previous two cases, initial
contents of 'R' are used as the
source operand.
OPR PC,X(R); OPR PC.@X(R);
OPR PC.@A; or OPR PC,A: location A
will contain the PC of OPR + 4.

x
x

In the previous case~ location A
will contain the PC of OPR + 2.
JMP (R)+ or JSR reg.(R)+: initial
contents of 'R' are used as the
new PC.

JMP %R or JSR reg,%R traps to 4
(illegal instruction),

Table 8-1

SBC-11/21 PLUS, LSI-H/1, and LSI-H/2l Comparisons (Cont)

Activity

SBC-1I/21
PLUS

LSI-1l/2

Only one LSI· I I .bus interrupt

lSI-t1/23

level (BR4) exists.
Four local interrupt levels exist.

Four LSI-II interrupt levels exist.

X
X

Stack overflow not implemented.

A stack overflow trap exists.

The first instruction in an
interrupt routine will not be
executed if another interrupt
occurs at a higber priority level
than assumed by the first interrupt.

Eight general-purpose registers.

PSW address 177776 not implemented.
Must use MTPS and MFPS instructions.

Only implicit references (RTI, RTT.
traps, and interrupts) can load
T~bit. Console cannot load T-bit.

If an interrupt occurs during an
instruction that has the T-bit set.
the T-bit trap is acknowledged
before the interrupt.

If RTf sets the T-bit, T-bit trap
is acknowledged immediately
following R TI.

T-bit trap will sequence out of
WAIT instruction.

If RTT sets the T-bit, the T-bit
trap occurs after the instruction
following RTT.

RESET instruction consists of 10 p.S
of INIT followed by a 90 ps pause.
Power fail is not recognized until
the instruction is complete.

B-2

X
X

Table B-1 SB(>Jl/2t PLUS, LSI-U/l, ucI LSl-U/13 C.....risons (Cum)

SBC-U/21
Aetidty

PLUS

RESET instruction consists of 17
#IS of INIT followed by a minimum
3.2 /AS pause. Power fail is not
recognized until the instruction
is complete.

Odd address references using the
SP do not trap.

Nonexistent address references
using the SP trap to the restart
address.

LSI-U/l

MOVS instruction does a read
(DATI) and a write (DA TO) bus
sequence for last memory cycle.

MOV instruction does a write
(DATO) bus sequence for the last
memory cycle.

MOV instruction does a read
(DATO and a write (DA TO) bus
sequence for last memory cycle.

CLR(S) and SXT do a read (DATI)
and a write (DATO) sequence for
the last bus cycle.

LSI-Hill

CLR(B) and SXT do a read (DATI)
and a write (DATO) bus sequence
fot the last bus cycle.

CLR(B) and SXT do a write (DATO)
bus sequence for the last bus cycle.
MARK instruction.

SOB, RlT. SXT, XOR instructions.

SW AD clears V.

ASH, ASHC, DIV, MUL instructions.

8-3

Table B-1 SBC-ll/ll PLUS, lSI-ll/2, and !.Sf-H/23 Comparisons (Cont)

SBC-H/ll
PLUS

Adhity

Register addresses (I 777001777 i 1) are handled as regular
memory addresses. No internal
registers are addressable from
either the bus or the console.

lSI-It/2
.
-

lSl-tl/23

Register addresses (177000177717) time-out when used as
program addresses by the CPU.
If PC contains a nonexistent
memory address and a bus error
occurs, PC will have been
incremented.

(f register contains a nonexistent
memory address in mode 2 and a bus
error occurs, register will be
incremented.

If register contains an odd value
in mode 2 and a bus error occurs,
register will be incremented.

HALT in user mode traps to 10.

HALT instruction pushes PC and
PSW on the stack: and loads the PSW
with 340 and the PC with the restart
address.

Only power-up mode 2 implemented.

X
X

Resident ODT microcode.
Instruction execution runs to
completion regardless of bus error.

BEVNT line interrupt on level 6.

Bus error traps to restart
address. Instruction runs to
completion before trap.

B-4

Table JJ..J SBC·l1/21 PLUS, LSI-n/l, and LSI-1I/l3 Comparisons (CGIIt)
SBC-Il/lt
PLUS

Activity

Bus error during IAK vectors
through 0 and traps to restart
address. The first instruction
of service routine is guaranteed
to execllte.

Only t6-bit addressing supported.

LSI-U/l

LSI-H/ll

x
x

The no-BSACK 18 j.LS time-out

implemented. If time-out occurs
BDMGO aborted.
Bus halt tine is a jumper
configured nonmaskable interrupt.
Acknowledgement causes PC and PSW
to be stacked and the processor.
vectors through level 7 internal
vector 140.

Vector address accepted only on
BDAL<1:2>. This limits vector
address space to 374.

Certain vector addresses are
reserved for local devices other
than BEYNT.

8-5

Table B-2

Illegal Address Traps

From

Through

Response

11/21
PLUS

LSI 11/2

11/23

210

217

Trap to 10

Reserved
instruction

210

227

Trap to 10

Reserved
instruction

70000

73777

Trap to 10

Extended
instruction
set

75000

75037

Trap to 10

Floating
point

75040

75777

Trap to 10

Reserved
instruction

170000

177777

Trap to 10

*'"

"'*.

Reserved
instruction

"'Maintenance instructions
"'*Response depends on processor options

SBC-l1/21 PLUS Priorities
Priority of DMA, system traps, external interrupts. internal interrupts. HALT trap, and WAfT:

DMA
HALT trap (time-out request)
Power fail trap
Traps (illegal instruction, T -bit, EMT)
Internal interrupt request
External interrupt request
WAIT instruction

(highest priority)

(lowest priority)

B·6

APPENDIX C
SOFTW ARE DEVELOPMENT

C.l GENERAL
This appendix describes programming notes that may help application programmers to gain familiarity
with the SBC·} I 121 PLUS. The following five topics are discussed:
1.
2.
3.
4.
5.

Running RT-ll V1.5 operating system
Running MicroPower/Pascal VI.5
Running standalone programs
The software development process
An application example

A method of creating, loading, and running standalone programs is explained. This is followed by a
discussion of the software development process as it applies to a ROM based single-board computer. The
last section of this appendix presents a practical example of a real-time program written to run on the
SBC-lI/21 PLUS. The output selected for the program is deliberately simple, however. the methodology
is applicable to more complex programs. The program has been tested, and studying it should be
informative to first time users of the SBC-II /21 PLUS.
C.2 RUNNING RT-ll VS.l OPERATING SYSTEM
SBC-11/21 PLUS supports both the single job (SJ) as well as the foreground background (FB) operating
system (see Chapter 3; Supported Software Options). An application may be developed on the SBC-! t /21
PLUS using any language supported by RT-l1. See RT-IJ documentation for additional information
concerning RT-Il developed applications.
. C.l RUNNING MICROPOWER/PASCAL
SBC-11/21 PLUS supports MicroPower/Pascal V1.5 or subsequent versions. An application is developed
on a host system running either RT-ll or RSX·IIM and then loaded into the SBC-lI/2} PLUS for
execution.
C.4 RUNNING STANDALONE PROGRAMS FROM ruS8 OR RXOI/02
The user can develop standalone programs, programs not needing an operating system, on a separate RT~
11 based system. The .SAV image can then be loaded into the SBC-1l/21 PLUS and run from either
TUSS or RX01/02 storage devices. The Macro-ODT option is needed to load the program and to run it.
If the standalone program is to be used with Macro-ODT, it must have the address of Macro-ODT
BREAK service routine in location 140 and a PSW value of 300 in location 142. This will enable the
program to transfer control to Macro-ODT when the BREAK key is pressed.
To load the standalone program from the mass storage device into the SBC-t1/21 PLUS. tbe device's
boot block must be modified. This change extends to locations O. 2, 4, and 6. Location 0, which normally
contains 240, must be changed to 260. When the device is booted, this tells the Macro-ODT that the mass
storage device contains a standalone program. Macro-ODT will then interpret the contents of locations 2,

4, and 6 as a RADIX-50 encoded six-character file name and search the directory of the volume for that
file. The volume must have the RT~ll file structure. When the file is found, the complete file is loaded
into contiguous memory starting at location O. Then Macro-ODT loads register RO with the number of the
unit or drive and register R I with the CSR address of the booted device.
The stack pointer (SP) is loaded with the contents of location 42, the program counter (PC) is loaded with
the contents of location 40, and the program starts execution. A standalone program developed on an RTII based system will have had the correct values for PC and SP in locations 40 and 42. This information
may be of use to the standalone program if it uses overlays.
The detailed procedure for performing these modifications in the boot block and the standalone program

follows, and will be done on an RT-ll based system using the SIPP utility.
In the following examples, the program that is to be loaded and run from the standalone volume is named
FOOBAR.SAV and resides on DK. The characters entered by the operator are underlined. '<CR>' is a
carriage return and not the four characters '<" 'C', 'R'. and '>'. The' e and' Y' symbols are obtained
by holding down the 'CTRL' key and typing 'C' or 'yo before releasing 'CTRL'. 'XXXXXX' is a string of
octal digits whose value can be anything but does nothing to the process.
First. modify the standalone program:
. R SIPP <CR>

;Run the SIPP utility

• DK:FOOBARSA V <CR>

;Name of file to be
patched

Base? <CR>

;Defaults to zero

Offset? 140 <CR>

Base

Offset

Old

New?

00000o

000140

xxxxxx

170000 <CR>

;Load address of BREAK
routine at BREAK vector

000000

000142

xxxxxx

300 <CR>

;PSW during BREAK routine

000000

000144

xxxxxx

I\. Y <CR>

;Exit patching

*I\.C

;Exit SIPP
NOTE
If you are using your own BREAK intercepting routine, put its address at location 140 in place of the
value 170000.

C-2

Now modify the boot block:
.R SIPP <CR>
*DK:/A <CR>
Base? <CR>
Offset? <CR>

Base

Offset

Old

New?

000000

xxxxxx

000260

000000

000002

xxxxxx

;RFOO <CR>

000000

000004

xxx xxx

;RBAR <CR>

000000

000006

xxxxxx

;RSAV <CR>

000000

000010

xxxxxx

I\Y <CR>

*I\C

C.S THE SOFfW ARE DEVELOPMENT PROCESS
Software development for the SBC-ll/21 PLUS can be considered as four discrete steps. These steps are
illustrated in Figure C-l.
1.

Design the software and code the source tasks.

Enter, edit, and assemble the tasks that make up the application.

Build the application into a runnable memory image.

Load the program into the SBC-li /21 PLUS and execute the application program. This step
includes the debugging of the application.

C.S.l

Design of the Software
An important consideration in the design of application software is the run-time memory configuration.
Because the SBC~ 11 /21 PLUS is a ROM/RAM system, the location of the ROM/RAM boundaries must
be defined. All instructions and constants must be arranged separately for location in the ROM section of
memory. Variable information must be arranged together for location in the RAM section of memory.
During the development process, the separation of ROM and RAM information must be maintained. See
the MACRO-Il Language Reference Manual for a description of the methods of data and code
separation.

C.S.l Editing and Assembly
The second step in the development cycle is the entry, editing, and assembly of the application software.
Entering and creating the application software includes the use of an editor on the development system.
Once the application software is entered and the designer is satisfied with the contents, it can be ~ved on a
mass storage device. The assembler must then be used to convert the source code instructions into
executable code. The result of the assembly process is an object file.

C-3

START
UNDERSTAND PROCESS
TO BE INTERFACED
WITH, 00 TASK DESIGN

CREATE THE SOURCE
CODE FilE WITH AN
eDITOR

BUILD THE
APPLICATION
PROGRAM

~------r-----~

STEP 1

COMPLETED

Figure C-l

Overview of Software Development

The assembler detects common assembly language coding errors and issues appropriate warnings. If errors
are detected, corrections should be made by re-editing the source and reassembling. Once the application
software has been translated error free into object form, it is ready for the next step.
C.S.3 Bulldine Process
The third step in the development cycle is the building process to create a runnable memory image. The
build process uses the linking of the tasks that make up the application software into a single memory
image. The building process takes an object module or modules and assigns absolute memory references to
the information contained in the object code. The user assigns these locations by the sectioning of the code
that took place during design. The result of the build phase is an executable run-time memory image that
can be loaded and tested.
C-4

COS.4 Running aDd Debugging the Program
The fourth step in the development cycle is the loading of the runnable memory image into the SBC11/21 PLUS. Once loaded, the program can be run and debugged. There are three methods that can be
used to transfer the software to the target.
I.

ROM transfer. This method uses the programming of ROMS via a PROM blasting utility, such
as PB-ll, and places the PROMs into the target configuration. This simple loading method
resembles the final target configuration because actual ROM storage is used.

Media transfer. When this method is used, the application program is loaded, in standalone
form, into the target from a mass storage system. The directions on creating a standalone
bootable program are provided in Paragraph C-2. The target configuration uses LSI·lI bus
RAM memory in place of the SBC-ll/21 PLUS on-board ROM during initial startup and
debug. The SBC~11/21 PLUS configuration must contain the Macro-ODT ROMs described in
Chapter 4. The ODT ROMs provide the means of loading the application program and are used
during program debug. Media transfer does not reflect the final configuration, but execution
from RAM makes debugging and testing easier. The speed of the program in this mode is
approximately half that of the ROM based system.

Down-line loading. This method of loading allows transfer of the controller software from the
development system to the target system via a serial communication link. The down-line loader
must be a development system utility_ The target configuration is similar to the media transfer
configuration. In addition to the LSI-II bus, RAM, and the Macro-ODT ROMs, one of the
serial I/O lines on the SBC-11/21 PLUS must be dedicated to the communication with the
development system.

When the correct loading method is implemented, the final phase of development is to debug and run. The
loading method used defines the solution that will be taken during debug.
If the application is being loaded via the ROM transfer method, initial testing and debugging is difficult.
When ROM transfer is used, there must be embedded code in the application that will report the state of
the control system regularly. Another way to check the system is to note changes that occur in the external
devices. If errors are found, a complete reprogramming of the PROMs is necessary. This type of testing
and debugging can be difficult.

When the application is loaded via media transfer, the testing and debugging becomes easier than the
ROM method. Once the application program is loaded into LSI-II bus RAM or into on-board RAM, it
can be run using the features of Macro·DDT. The designer can also include reporting tasks and halts in the
application to examine the current state of the system. Executing out of LSI-II bus RAM during debug is
approximately twice as slow as running out of the SBC-lI/21 PLUS on-board memory. If errors are
found, minor changes can be made in the application code because testing is being done in RAM. This
deletes the loop of making new run-time memory images for every change. Once the target system is
running successfully with all of the tasks integrated, the run-time configuration can be set up. The last step
is to load the application program to ROM and run in the SBC-Il/21 PLUS.
Co6 AN APPLICATION EXAMPLE
A sample application is illustrated in Figure C-2 and shows the development of a controller program using
MACRO-II. The sample program will only light the LED used by port C of the SBC-ll/21 PLUS. The
LED will light for 10 s when an input is detected on the console port (SLU I).

The controller program for this simple system is best operated by using an interrupt driven environment.
An interrupt service routine is used to monitor the console port. When an input is received, :it routine is
entered that will set the timer for lOs and light the LED. A second interrupt service routine is used to
count up to lOs and then turn off the LED. This routine is serviced by the BEVNT interrupts. In addition

START

r-----

POWER·UP FlOUTINE
IS THIS RECOVEAY FROM A POWER FAILURE (POWRUPl

NO
INITIALIZE THE DATA STRUCTURES FOR DIAGNOSTICS (DIAGI

YES

PERFORM DIAGNOSTICS (afAG)
TEST SBC·l1 /21 PLUS SID, PID, RAM, ROM

RESTORE STATUS
PRIOR TO THE POWER FAIL
(RECOVR)

ANY ERRORS

_ _ _... REPORT TO OPERATOR,
GO INTO INFINITE LOOP

INITIALIZE THE DATA STRUCTURES (START)
FOR CONTROL/MONITOR TASKS

ENABLE INTERRUPTS {START!

' - - - - - - - - - WAIT FOR INPUTS (STARTI

TIMER

HANDLE EXCEPTIONS

INTERRUPT TASK NO.1
ENTERED BY AN INPUT RECEIVED
VIA CONSOLE SLU INPUTS

INTERRUPT TASK NO.2
ENTERED EVERY 1/60 OF A SECOND
BY aeVNT INTERRUPT

POWER FAIL (POWERF)
BUS ERRORS lRESTRT!

DO THE FOLLOWING:

1. SET TIMER FOR TEN SECONDS
2, LIGHT THE LED

1, TICK OFF TIME IF THE TIMER

RECOR BAEAK

IS SET TO GREATER THAN 0
2. IF TIME EXPIRES TURN OFF
THE LED

Figure C-2

Application Overview

to the application tasks, there are tasks to initialize the input/output devices and data structures. There are
also diagnostic programs for the SOC-II /21 PLUS and programs used to handle any exceptions. The
controller program is developed as individual tasks and then integrated into a complete final program.
The monitor program, shown in Figure C-3, consists of power-up programs, diagnostic programs, task
programs, and exception programs. The power-up programs consist of POWRUP and RECOVR, which is
started by POWRUP. The diagnostic programs consist of SLUTST, PIOTST, RAMTST, and ROMTST.
The task programs consist of TIMER, REC, and BREAK. The exception programs consist of POWERF,
RESTRT, and PRINT. AU these programs with the constants and instruction data are stored in the ROM
memory. The variable data for the application and the stack are stored in the RAM memory. Memory
map I is assumed (Table 2-8), with the program in ROM socket set B, and data in battery backed RAM
starting at 160000. The load map in Figure C-4 shows actual memory locations assigned to code and data.

C.6.t

Power· Up Programs

The controller program starts when the system power is applied. The microprocessor accesses location 0,
which is the jumper configured start address. This location contains a jump to the power-up routine
POWRUP (see Figure C-5), This routine determines if this is a normal power-up or a recovery from a
power failure. This is determined by checking the power fail flag in the RAM memory. If the flag is set to
indicate that the system is recovering from a power fail condition, the program jumps to the RECOVR
program (see Figure C·6), This program restores the system to the conditions that existed before the power
fail and continues program execution. If the flag is not set, an initial power-up program is executed and the
program then branches to the diagnostic programs.

C-6

C.6.1 Diagnostic Programs
The diagnostic programs are entered via a diagnostic initialization routine. The SLUTST program (see
Figure C-7) is the first diagnostic, and it tests the auxiliary serial line unit on the SBC-1I/21 PLUS. The
diagnostic enables the SLU maintenance mode and transmits many test patterns. After a certain amount
of time, the program checks to see that the test patterns were correctly received. The SLU maintenance
mode aHows data to be transmitted to the EIA port as well as through the internal loopback. Therefore, if
a device is connected to the port, it will respond to this data.
The second diagnostic, RAMTST (see Figure C-8), tests the RAM memory. The test is performed by
writing known data into a RAM location and checking that the correct information is in that location.
The third diagnostic. ROMTST (see Figure C-9), checks the ROM memory. This test calculates a
checksum on the actual control and monitoring tasks. If there is a checksum error, there is a potential
failure at some ROM location.
The last diagnostic, PIOTST (see Figure C-IO), checks the parallel I/O port on the SBC-ll/21 PLUS.
This test verifies that the parallel I/O registers can be addressed. The send/receive capability cannot be
checked unless there is a loopback connector installed on theJ3connectof. When data is written into these
registers and a device is connected to the port, the device can respond to the data.
When any of the above diagnostics detect a failure, the program will set an error flag. The diagnostic
program will check the status of all error flags before it enters the task programs. If an error is found, the
operator is informed that a diagnostic test failed, and the program enters a loop to wait for the operator to
interrupt. Each diagnostic will print a message to the operator indicating success or failure. If there are no
failures, a success message is printed and the program enters the task programs.

C.6.3 Control Task Programs
The control task programs (see Figure C-ll) complete the initialization of the system by clearing the
receive buffer, enabling the interrupts, and lowering the microprocessor priority to accept interrupts. The
operator is then informed that the system is- running and waiting for interrupts. The TIMER receives a
BEVNT input sixty times per second. The REC program is entered when an interrupt is received from the
console. The program will then turn on the LED and load the 10 s counter. The BREAK program is
entered when a BREAK is detected and performs the same task as REC. A TIMER program will
decrement the 10 s counter, if it is enabled, every time BEVNT is received. When the 10 s counter is
decremented to zero, the program will turn off the LED. If the LED is turned on and another BREAK or
interrupt occurs, the lOs counter is reset for lOs. The program also allows any exception conditions.

C.6.4 Exception Programs
The system is now running and the exception programs are entered only when a power fail occurs ora bus
time-out occurs. The print program is entered only to communicate with the operator.
A time-out will occur when an address does not respond or if a device does not respond to an interrupt
acknowledge. When a time-out occurs,. the SBC-ll/21 PLUS will trap to location 4, the restart address.
The start address is defined as location 0, and restart address is defined as location 4 by the factory
configuration. The RSTR T program is entered vIa location 4; it informs the operator that a run-time error
has occurred and waits for the operator to interrupt.
A power failure is detected when the system power is going down. This enables the power fail interrupt and
causes a trap to location 24. The POWERF program (see Figure C-12) is entered via location 24, and the
power fail flags are set in the RAM memory. The RAM memory includes the battery backup feature of
the SOC-ti/2} PLUS module. Program information contained in the general~purpose registers, the stack
pointer, and other necessary data are stored in the nonvolatile RAM memory. The program then puts the
bus into a known state with the RESET instruction and waits for the power loss to occur. When power is
restored, the POWRUP routine is executed and data is recovered as the system restarts.

C-7

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1$ the ..ec.iver ~ •••• ?
re. H i . _d b ......d'I
If .... t ~••4y. bu.~ ,t •• out eo_t.er
l f Uud ....t the.. ..Ji"ItD..•• the i ..f •••• t.i. ... , .,.t GIl ?
1110 it .... _" -ERRORAll.' the tes~ ~.to.n. done
110. •• do .noth•• ~.tt.~n
AU 0.1 Lh. b.ud •• t... t •• tod
Y. . . . . t out 'Of 'hi . . .auU_
tlG. • .. t-UI' tho ".IIt. b,1Nd •• t.
Do anGth... 10... ..in1t ~~tto .. ns

fltCSIU.fll

2HU)

If011

U.4!1U)

/lOY
IfOV

tI'ATERII,Rl

UTI!

R$
'" (ItO

H 0(01)14
1.S Oooon
t6 60'0026
17 '0000.10
18 OO":J4
l ' OHOS'
20 OH.o40
21 0.0• .042
22 000046
23 000050
24 0000S2
25 00•• 5.
26 0003'

21 00..6.

28 O~4"

29 0000"

:so 0"070
31 000072
32 O~74

I I 000076
3t 0001.4
;ttl

36 0001.6
37000H2
3a ooon,
39 .t.o120
U 00;1)122
41 ••• 124

42 000130
U

H 000112

1)12702
O127OJ

0.051)05
1051.1
1'01)402
077504
000422
lU36l

OO!$••S

It:
:ttl

000004

.000006

".1

"."711

10.,..2

"11

SClII
8iIt
!lOVII
CUt

11111

077103

000.13

lilt

126113

.91010
10$721
001H6
0.$302
"1412
.62161
000746

000(1)2

ioU

00000.
100tl

040

000

UI:3),6HiH

.S
(lU)

••

flS,'t
100.

titlE

2t
R2

tll:II
A01\
fIR

290t

Ille

ERROR

CALl.

P'UtiT

tlt3H

.VORD

9LU£

f"RIHf

1 Sot I

RETI/IIII

PATEaMl •..,TE

UI).4IIU>

.1ft
.tAU.

.IiHIItD

190t

20Ot:

OOI)"OG
0'1)02.'

••

R5.ls
100 ..

lHRl).(ftJ)

000010

... ,R2

CIfI'I
al!le;

0"267 (1)00006
.004767 0000008
OOOt.otG
• .oOH3
.0.767 0000006

no•

.Jl1Io1lt.

000001

.£1111

lua~ th" e"Of' count ...
Print tho error •••••••

00 baek
The te.' w••• ue~ •••'ul

SLGOOD

.If.

117.40.0

Te.' ... ttopn. fo~ 'SlU

.(\1£11

"6
.7

0.0001'0
000U2'

loP

Figure C-7 SLU Diagnostic Task

C-12

t
2
:I 000000

• E!tAlll
.SloaL
.PSECT

lC.Ll!9
RAK.BN,fRINT,RAKTOP,K£SRA1.RAGOOD.ERROR
ROK

S 000000

RAKTST:;

I
1-

8
9

10 000000
11 000002
12 000004>

011602
016103
012100

This rout:i,,... eh." ... " the " .. ". RAil on th .. KXT 11-11A

0000000
00000010

MO\l
KOV
KDV

(SI')'1I2
EIi:ROR,R3
tRAII.GN.IIO

liOV
CI'II'

1<0, (RI»

lEO

2 ..

CALL

PRINt
KESRAl
R3

I
I
I

14 000012
15 00'0014
l ' OOOOu.

17 000020
18 000024
19 000026
20 000030
21 000032
2:! Ol)O034
2l 000040
2" 0000"2
25 000046

010010
020010
001405
004761 0000006
0000006
005203
000407
005720
020027 0000026
103764
004747 0000000
0000000

1$:

• IIORD
INC
8R

2$1

Wri~" th. a<!dress
R... d it ba.,k

It!h UWl

w•• the value r&ad correctly
Ho • report the failure,
s.t. the .rror flB'!h

."d 010

T51
CI'II"

(ROlf
RO,UAIITOPt2

alO

CALL
.WORD

PRINT
RAGOGD

IIOV
I\OV
RETUF:N

R2.!SP)
R3.ERROR

• [lSAlIL

lSI!

Savlt th .. •• tur" add.es"
S."" th .. cont .. nts ·of th .. ERROR flut
Point to the start of the " ••• RAK

b.,,~

00 onto the n •• t location
Until th.re ~s ~o
t.o '.5t

.Of".

Indicate RAil t •• t svcce4.

21 000050
28 000052
2,}

000056

0104!16
010367
000207

3.:
0000000

30
31

000001

Res\ore the r.turn .ddr.~s
".store the ERROR flag
T.. st co .. phted

.END

Figure C-8

RAM Diagnostic Task

MCRO 1104.00. 8-FEIl-82 O~:20;58 PAGE 1

.IIAIH.

.ENAal LC,LSD
.0LOPl REC,lAST,CSUK.PRINT.KESR01.R0600n.ERROR
.!'SECT ROil

3 000000

5 000000

IIOKT6T; :

;
I

This .outin. will check the ROil on lh .. KXT11-AA. this te.t ch"c~$
th. ~ortion of the ROK th.t contains the • .,tvar control/.oniio. tasks

10
11 000000

12 000094
13 000006
14 000010
15 000014
1. 000014
17 000022
18 000024
l,} 000030
20 000032
21 0"036
22 000040
23 0000 ....
24 0000"4
25

012700 0000006
905001
062001
022700 0000020
001374
022701 0000006
001406
00416' 0000006
0000000
005267 0000006
000403
0000006
00..,"
000000$
000207
OOOO() 1

1\0\1

• REC.RO

Ct.1!

to the control t ..... _dd ••••
InitializR eheck&u .. y.l".

Ali!)

IROH.Rl

U.. d.t. "al ...

ClIP
fill'
CIIF'

tI.ASH2.RO

1f
"SUII.1l1

Until there ••• no val .. e. to ~u.
It there ere .till eO •• aD .et th••
A •• th .. "h.. eks ............ 81 'I'
v••• 1•• "e the ' ..st
110. • ... ort. th.

IIEO

:1$

CALL

PIUNT

• IIORI)

1I£5R01

fail" ••

INC

ERROR

PI!

Set the •• ror fl ••
L ••
t.he t •• t
Re~ort th. t •• t ~ •••• d

CALL
.IIORD
3.;

Poi~\

PlltNT

ROGOOI)

REfUR"

.IISAflL
.ENO

Figure C-9

l58

ROM Diagnostic Task

C-13

.HAIN.

lIACRO 1104.00

.8-f£I.I-I.2 04120150 P"lIll

I.
2
1 000000

.iIlUL
.GUIIL
.PKCT

.
..5000000

PIOTSTll

10
11 000000
.12 -tlOOOIU
13000004
1-4
15
16
11 000012

Thh .. ovU ... ch."ks \h. p"ral1.1 ...

,- "est the .bili".. to

012·701
OOSOOO
00$160

000003

00S720

TSf

(1110 a

017104
0041'67 0000006
00'0-000'0-

SCI
tALL
.WORII

Jll,n

0002.'

ItUURIrI

000001

.t:NP

.IISAI1.

,•
.,t.....,
, 'l..... ..

!IIU.UUze 1 _ CGun"""

""AUtO I

Figure C-1O

or"" ont.h.I(XTlI-AA t.hi. 0,,1 ..

th. ~ort

ItO

lSI

Itl

.dd~•••

.,.lU

1Kl1l

CU.
0000000

141
19
20000014
:U 000016
22 oooon
2!
2~ 000024
25
26
27

Lf .LIB
'!'A.1"ltl.NT ."80011

itotI

In"1.11.2* coun'"~ 'nO.~
I AU._.. t t.o •••
"10
'h..
I
1'.U.. '. ,,..,. th,.ou.... 'he
I ..... " ... \ wUl OCCUI" ."......or\ II tWf\

".1$

,.or" "

1"" ....."1. "he ind.", t"'h wUl ...t
I t.i.. out .ift".'h.... is •••• MII .to
I

,• t"41,,",,.
I

"RUff

"GOOD

IHo"a."" 2-<1

Do 'h. ...... t.

.vec•••

LSI

Parallell/O Diagnostic Task

.NAIII.MACRO 1104.00 I-FEII-82 04:21:02 'AO£ I.
·CONTROL ANII 1I0NITORUiO JAIn
I.

.StTTl

CONTROL AND MONITORING TASI(S

.£NA.L

.." 000000

• GUill
,I'II£CT

LC
T UtE: .1.iDON. "CW.«CSRC. LEDOff

::
5 000000

ROil

I This intor.IJ"1. ro\l\lno """... "" lin in~u' ' .. oa t."-I:'on".,l·o ......"'\"'. in ..... '
f r.c.i .... d • ten s.cond "o,,,,t.... is 'niU.1.:0" _ . the 1.£11 ·I.s 1.'1...... 4 ..n.

12
1~ ~OOO

Ot2U.i

14000004
n #40014
16000020
H
18 000022

OU7J]

10li731
0(1)002

001130 00000011
00000011 0000006
0000020

s.t. ti ••? , . . ten ".eond"

.<10.' 60.>.11"£

"00
11011
UTI

.L£DtIH.If."C11

1'11'1> tho LEII en

H«CHCH

O."Kt.

TlKEIU!

22
U

I •• eonll count... "nlll 1...... n 01f 'h. LEI!
I •• t ....."9 i •••,Hat..l,..
1-

I Tl>i" i·II\ • .,u,.t

.0"Un............nt ....11 ..".r .. ".1""k Us "ill d." .....", "h. ten

I.,

tll. t i . .

24
2S OOOOO:n:

24 ",0.26

1$
U
11
J.I 0000 . .
3f 000054

000062

".h'. b~'.r

fl ....h tt,o ...

Rfl

20
21

27 000030
28 000$1.
29 "'0036
30 000044
31
32 000046
13
U

00S161
001404

0-000006

I)GSlfo7

000000(1

OOUU
0-12737
1>1)0002

00«)01)060000006

fST

tto

l'IE:f

eN£
"00
GO ••ct<1 ITt

llIel<.. i .e". otho .... l ". 1 t.

N" ...........

OBIAfK

It t.n.t.t.. . is
t.be
eovAter othervi·•••0 ·1)ec:k
, .... "_t.h.,,_ton ....111 i t it. is

008"CI(
nU·OFf.H"CII

Ot.he,viSe •• bnk

UNIt

UM£

lb. Int Uc:I!.t.heft Ru1; ,he LlIl ott

JR£"Kt I
H

I TMs int.eH...,.t •• ~"ie. ,.."U"e vill II. ent.."od 11 " 111'••'" CfUec:UCf • thl.1l
I i . t. ••"tod .s • " ..... 1",. l~..... t. on \h. «Xfl1-AA "0"•• 10 ...

,1..

012767
012737
000002

001110 0000000
01)00000 0000000

troY

LASH I

KOV
RTI

t<10 • • '0. h TlKE
tt.EDON. It"CIII

i.'
t.i •• , tot '.n ••"onll.
h"... ·UleLED on
t.he

G. ".ck

01)0001

Figure C-ll

Control Task

C-14

MACRO VOO4.OOOO

8~FEt-B2

0041211006 PAGE 1

.ENAIL
.GLOaL

2
:5

"'CALL
.PSECT

4 0000000000
:;
6 000000000000

POIIER1.POIIER2, TIME ,SAVER/"PRINT ,FIIESS

PUSH
ROil

POIIERI' I I
1+
I Thie routine i . entered when ,.

8
9

100
11 0000000000
12 00000006
13 00000014
14 00000016
15 0000000200
16 0000022
17 006624
18 000000026
00000300
20 000000034

~owe.

01276'
00127.'

123456
135724

00000000011
000000000011

KOII
IlOU

PUSH
PUSH
PIISH
PII811

PUSH
PUSH
PUSH
0100667

000000000000

t123456 , POIIER 1
t1l5i'24.POIIER2
RO
R1
112
U
R4
ItS

de~.cted

and saye. the

000000005
00000777

Initializ. the 32-~it pow.r •• cov •• w
test ... tt ....

Sava the "e"era1 pur"o.e ra"is"e ••
and .nw pa.ti .. e .. ' d,ta in a nonvolatile RAil ••••

liME

RESET

Sava the .taek pointe. io the 000~ol.til. r •• •• ea
Pvt the bu. in • known s,.te

IJR

and weit tor 10 •• of ~ow..

11011

SP.5AVU.

22 0000000400
2lI 0000042

fail is

I pe.tinen~ in10 ••• tion in non-yol.til. RAil

25 0000000044
26
27
28

RESTRT II
if

, IIhen • bu. er.o. OCCU'. such •• .0 interrupt ti.e-ou~ o. bus tiew-out
I • trap th'u tha ••• tart tak •• piece an« 00 ••• h.re
1-

31 OGOoOH

32 00000050
n 000000052
34
35
36

000047.7 0000006
000000000000
000000777

CAll

PRIIiT

.IIORD
I!UI

FliES;

00'00000001

.END

Figure C-12 Power Fail Task

C-JS

Indicate thet e run-\i •••• ro. h ••
•••d and wait for operator
int..,vantton

oc~u

APPENDIX D
MACRO-ODT ROM LISTING
FOR KXTII-A2 OPTION

Appendix D provides the user with the program listing of the KXT II-A2 Macro-ODT ROM firmware
option.

0-1

KXtl1-A2 iK FIRM_ARE
TABLE OF CONTENrs
1

689-

1
1
1

11-

1414141519-

1
1
3
4
S
1
1

2020-

1
19

;21-

1
1

22232424252626272"1-

y
N

34-

1
1
22
1
1
29
1
20

28-

30-

32-

3335-

1
1

16-

394041-

1
1
1

4243-

1
1

45464"1-

1
1
1

37-

4e-

fII-

56
114

494949-

.'1-

1
42
51

49-

S8
92

50515152-

S2-

1
1
21
1
29

5253-

37
1

53-

MACRO V04.00

s-ucr-at 22:56:21

COPYRIGHT HOT ICE
KXTI1-A2 EDIT HISTORY
Equatea
General D~ART Equates
General PPI Equate.
Proqraa-speclflc Equates
MACRO DEriNITIONS
RAM Det1nlt1on
TRAPS-Trap-handllnq routines
TRAPS-LTC Trap-killer
TRAPS-BREAK hancHer
REsTART-Introduction
RESTART-Entry point
RESTART-See if staCk ex1sts
RESTART-Exit 1t 11'1 IN-ROM state
RESTART-Caule deteralnation
RUTART-£x1 ts
POW£RUP-IntroQuctlon
PONERUP-Turn on LEO
PONERUP-Test console DLAkT
POWi;RUP-Tut and set up I10-paQe RAN
POwERUP-Turn off LEO
POwERUP-Iest for wlo w core w
POWERUP-Ell1t
PO.ERU~-Subroutlne to 1n1tla11ze vectors
AUT08AuD-Syncnronize with Console
maeroOOT-Introduct1on
.acroDOT-Save statuI and print prompt
•• eroODI-Get OOT co ••and
aaeroOOr- Go and Proceed
.acroOOT-ReQ1ster and PS co •• and
.acroOOT-Exa.lne and Deposit
.acroUOT-Get and eChO cnaracter
.aeroOOT-Type ASCII string
.acroODT-Get octal di9its
.acrOOOT-OCTSTR--type binary in RO al ASCII
.acroODT-Output 8es.ages
DIAGNOSTICS-for SLU2 and PP!
HARDwARE EkTRY POlkT
DIAGNOSTICS-Continued
aOOTS-a.script1on
SOOTS-RX Controller Definitions
BOOTS-TUSa Definitions and Protocol Equate.
BOOTS-RTll Def1nitlons and Equates
aOOTS-proora. entry point
-----) HALT AT II'C"'172234 INDICATES -I1l8Qal device name"
H~LT AT PC=172264 INDICATES "Illegal unit number"
____ a> HALT At PC=172304 INDICAtES WNo low meacry, can't boot____ a> H~LT AI PC s 172376 IHDICATES ·unexpected tl •• out curlng boot"
800TS-RlOl/RX02 800tstrap
SOOT5-D1atingu1sh1ng type of boet blOCk
._---) HALf Af PC-172454 lNDICAT£S "Mo boot OlOCk on volume"
aOOTS-fUSS Bootstrap
____ a ) HALT AT PC-172S42 INDICATES "TUSa lnitialization error"
__ MaW) HALT AT PC=172S62 INDICATES "TUSa blOCk 0 read error"
aOOTS-Stend-alone volume bootstrap
-.---) HA~f AT PC-172614 INDICAtES ·D1rectory read error"

--_._>

Kk'fU"U 11( 'llt-WAat

fA'~C

or eONTE.! •

53-

5...
54"

1
8

5...

55..

1
1
I

56.
57..

57,. 36
57 .. 114
601
61.. 21
61- J1
63..
1

·W

MlCRO vo •• oo

5·aCT~81

22;56:21

......) MALT AT 'C.1726~2 INDICAT':. ·'Ue not tOlln4"
IOOTS-LOed .tend-Alone pro;f •• fl1e
- .. - .. _> MAL! AT 'C-172712 INDICATES "Stand-.lone fIle reed error- ..... > MAL! At 'C.1727~O INDICAtES "111e;al tranater .ddrea,"
111000G ENTRY POINt
BOOn-c!mUnued
BOO'I-alOl/al02 Re.d rOQtlne.
MAL! Af 'c-'73070 IhDICATES ·Floppy drIve not ready·
-...._-» HALT AT 'C=1732&2 INDICA!ES ·flOPPV read error"
BOOTa-fuSe Ree. rOQtlne.
........> HAL! AT PC-17355& INDICATES "rU58 END paCket M1 •• 1n;"
....... -> HALT AT 'C=173610 1.OlCATES -ruS8 ChtCk'u~ errQr-

-.._._>

END ann:lttNT

..i

....

..,•
•

..
•..
....••
.:

til

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c

...

..'"
.....
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.... . ..I ..
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...... . . "" ......•..
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•

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til

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..... ~

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=
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c

...
....."

......•
c

.....
.....
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fit

..........

•• ..........
•
..
:• ......

................... .

lXfl1-la Il '11.WA~i

CO.lfr1lfHt lionct:
1
2
1

;

.B8rTL COPYRIGHT NOTIC£

..5
6

1 TH1& aOftvlRE 16 FURNISHED UNDER A LICEhaE AND MAY BE U&ED AMD COPIED
1 ONLI IN ACCORDA~CE WITH THE TEIRS OF SUCH LICENSI AND WITH THE
; INCLUSION OF THE AaOVE COPYRIGKT NOTICE. TKIS SOftWARE. OR ANY OTH~R
1 CO'liS IHEREOF NAY hor 8E 'ftOVIOED OR OtKIN_16E MADE AVAlLA8LI fa Ahl
I OTHEN PEkaON. NO TIlLE 10 AND OWNERSHIP Of tHE SOFtWARE IS HERtiX
; tkAN.fERREO.

10
U

12
U
14
15
16

11
11
19

21
a2

'-OCT.I' 22;56;21 'AGE 1

1 COPYRIGHt tCl 1980, 1981 II
f DIGITAL EQUIPMENT CO.'OMATI0N. MAYNARD, MAas.

7
8
9

):'

MAeRO Y04.00

1 THE IlrORMATIOh IN IHIS DOCUMENT IS SUBJEct TO CHANGE WITHOUt ftDTICE
I AND SHOULD NOT aE CONSfRUED AS • COMMITMtNt bY OI;.TAL EQUIP"'"T
'
, eORPORATI0N.
I

DIGItAL ASSUM,S NO RESPO.SIaILIfi rOR tHE OSt OR RELIABILITY OF ITS
~QUIPMENt ~HICH IS NOT SUPPLIED 81 DIGItAL.

, SOFTWARE ON
I

, VUoSIO" Vl.OO
I

, £L 2'-Sf:P-11

....•.....
0

...

-..
to

. 'N

C
t

.....
... ..
# .
... . ..
..
...
I
'"•..
..
..
...
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....
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..:

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0
0

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0

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...
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...••
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.......
...

• .0
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w

, .....
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....•...
>C>C

"''''

... ,.

KXTll·A2 lK fIRMWARE
£OUAIlS

NACRO Y04.00

5~OCT.Bl

22:S6:27 PAGE ~

1
2

.58fT!. i\.quetu

; 8U i;QUAtES

4
!I

6
7
8
<}

10
11
12
U
14

1S
16
17

18
19
20

21
22

000001
000002
000004
000010
000020
000040
000100
000200
000400
0010(1)
002000
004000

ououo

020000
040000

luOOOO

26
21

I?
....)

8In
8IU

en4

8lT!iI

BIn
BIT7
1!1'U
Bl'1'9

SITlO
BITll
SITU
SITU
enl4
eIT1S

...

......
..
....
....
.

..
."

2
4
10
20

40
100
2110
40V

1000
2000
400u
10000

211000
4<l00O

lOuOOO

, A$C11 CHARAeTta EQUATES

24
25

8UG
IIlTt

000012
000015
000040

eft
SPACE

....
..

12
IS
40

;Line feed
lCerrla". return
;SPlIce

IxtiS-Ai II rll •• ARE

.,.IRik OLIAY EQUAtlS

5-OCt·81 22156121 ~AGE ,
.S'tfL General OLAa! Equate.

1
2
1

MACRO Y04.00

, DLAltt EQUA'I'£S

•

117S60
l11S62
177564

17 ...0
116542
i7654t

1765U

1J
14
15
16

004000

IIC.ACT

BItll

000200

flt.OUN

lun

000100

IIC.UN

IIlT6

•

18
19
20

1775fift

RCSRU

,.
ICSalt ,.
XBuru ,.
RCaRU •
a.Uyn •
XC611.2 •
xauyu
111

RelilrU

•

117560

171562
1175...
177Sh
170540
1711542
1765.4
17654.

2'
2~

27
28
30

100000

31
32

Re.ERR

040000

REhOVR

020000

RI.'R"

004000

flB.alUi

36
31
]I

,Receiver active (RIO).

"et

cnaracter la being
,, wnlle
recelved.

IReeelv.r done (11/0). A
; enareeter ha. been CO.Plately
;
received and now re.14 ••
in R8Ur.
1
IReCelver lnt. enable (R/.).
: When .et. enable. ·key~oatd·
lnterr~pt •• usln9 vector
at 60.

, DLART RECEIVE SUYFER SITa (RIO)

U
35

151.112 Idt CSR

16LII2 Xelt buffer

; OLAAt RICEIVE CSR BItS

,SLut Reeeive CaR
,SLII1 aecelve buffer
,SLUI lUllt CSIt
;~LUl Xalt buffer
;SLU2 ReCeive CSR
,aLua Receive buff.r

III

alTa

eutt
UT13

8Itu

;£rror. fralll109 error or
; overrQn na. occurred.
;Overrun error • cnaracter was
I received before prevIOus one
w•• rea4.
I
l't8111n9 efror. 110 Val14 atop
, ~lt .a. detected.
JSreak deteCt • .et when Dr.ak
1. detected, re.et wnen next
Itaft bit .fr1ve ••

KXfSl.Aa tK FIRM_Aa£
GENERAL CLARY EQUAtE.

MACRO V04.00

5-0CT-81 22:$6;27

~AG£

; DLAkl' TRAH5MJf CSR UTI

000200

XC.AOY

&11'7

000100

X<:.U:II

IU1'6

OOOOtO

P8RO

16
17

000020
000040

P8f(1

2
1

4
5
6

1
8
9

lO
U
U
U

, Progra•• able bayd rate b1t.

19
20
U
U
:U

9\0

26
27
211

30
11
32
3l
34

PBII2

....
;:

II'U
BlU

BU5

, 1'810-2 .et baud rete. a. fOllows:
000000
000010
000020
000030
000<140
000050
000060
000070

BI).OOl
110,000
80.012

....•

....
BO.096 •
80.1.92 .
BI).l84 ..

80.02.
110.048

G
PBRG
YIUll
PrlR1U'8RO

PBR2
PIUl2~P8RO

PBR2 LPttRl
P8R2!PIRUP8RO

000004

XC.MIIT

000002

XC.PSE

UTl

35
36
31
19

JS4ud rate ..
300
,8aud rat...
600
,laud rat ... 1200
Isaud rat... 2400
;Baud rat ... 4800
IBalid ret. • 9600
;Baud rate .. 19200
;geu4 ret ... l8400

IN,lnt.nenc. (R/W). Wnen set,
ereat.s an lnternal -loop.
baek- betw"n tn. tren,attter
and ree.lver. AllO dlseonnects tne .xt.rnal
,
"rial Input.
;Prog. bal14 rat. enabl.. wn.n
1
the baud rat. 1. detereln.d oy blt. 3-S as
taDIIlet'd ebove. WHEN

,.t,

Cl.tAR, BAUO RAn 18 DtUk-

42
4l

;Transmltter ready {RIO).
, When set. lndieete. that the
; last character wes coapl.t.~V
I
s.nt And X8Uf 1. ready fQr
1
a ne. one.
ITran •• it lnt ••naole (R/.).
;Wh.n let, enaole. ·con.ol.
, prlnter~ Interrupts, us1n;
vee tor at 64.

000001

XC.I!IRI!

MIN!U eJ VOLTAGES APP"!'I)
TO Ot.ANT 1C PINS.
,Transmit break (R/V). Wh'n
I .et, serlal output 1s a
eontlnyous BRtAK.
,

.ITO

,R,

Kxtli-Al lK 'la••
PtI IOUAfEa

GC.£MA~

MICRO Vo •• oo

s-ocr-Is 22156.27 PAGE 8

1
2

.1.fT~

3
4
b

'7
8
9

176206
176200
171202
116204

~ROGR.MMleLt

pp.tlla
PP.A
,p.a

,p.C

'"
"'
'"

11
12

14
1S
16

900200

".MOO

•

Uf7

000100

8IT6

000040

'P.MD2
PP.MD"

•

tins

000020

PP.ORA

BU ..

(01)010

PP.CHI

BIT)

000004

'P.IIOS

81T2

000002

'P.DkS

BUl

000001

,p.CLO

»nu

23
2f
25

26
21

28
29
30

,'PI ContrOl word aeolster

"PI Port , ae,ister
1PPI Port. ae,lster
,'Pl Port C Reolater

rfhts MUST ~e or'd wlth o~fter
oltl to let mode.

176206
176200
176202
1.7620.

I KXfl1-A' board configuration doa. not per.lt all cO.blnatlons of
, the eOde bits. ConSUlt the •• nual before u.lft. the 'Pl.

PERIPhERAL INTERrltE (PPI) EQUlfEI

; PPI "ODS-SEfTING elTs

20
21
22

General "1 ~quates

lieU .048 l

;If bit 6 'I low, detar.lne.
; 1II0de of pott. A
; ( hill.oCt 10 lo".ode O)
;Olfeetlon Of pott A.
I Hl i11 1to, lo=OUT.
IDireetlon of port C up,.r nalf
; Hl-Ilil, 10=OUf.
;1'1001' of port a.
, Hl ••04. 1, lo ••ode O.
lOiteetlon Of port 8.
IM1-IN, 10=OUt.
;Dlreetlon of ,ort Clower helf
1 HillIN, 10aOUT.

n
u

'PI elt SiT/Rtiit COHT~OL aIT$

When bit 7 11 low, wrltlft; to the "1 ca. wlll let or relet
1nd1vldull oit. 1n port C, dependinq ontne mode end olr.etlon
of tne port". blt.., end on tn. co.bin.tion 01 blts you wr1te.

36
37
38
39
40
41
42
U

..
45
46
H

000016

'1".1117

PP.II:U~

000012

PP.S15

OOOOlO

pr.IH4

000014

000006
000004
000002
000000
000001
000000

..,.au ..
PP.812

'P.lIU

Pf.810

PI>.1I1S

".SIC

IIU3U1U2l11ltl
b1 U t iIl'l'2
IUt31111tl
IIlTl
iUTUllltl

run
lun
o
II ItO

;Use ONE

;of then
Ito .elect

;wnlch ott

111 deSired

no be
,iU or
:CI... ARed

;5£T specifIed blt •
:CLEAR spec1t1ed alt.

UT~ 1",u 111. FUllh'A!!£
IIIACRO VU.OO
,IOGRAM-a,£elF1C !QUATES

~·OCT-81

~2~!612'

• SBnl.

2
~

•

PAGE 9

Provra.-".Clfl~

tOUATES USED TO TURN ~ED ON AND OFF

000221

MODE

•

PP.MODIPP.DIlAIPP.C~O

OOilOn

... EllOF'

'Port Ii .. MOde 0 IN
;Port ... Node 0 OUT
;Port C upp.r nlbble .. OUT
,Port Clower nlbb' • • IN

I'P.1I16IPP.817

Iht

i
1

8
i
&0

11
12
U
'4
15

EQUATES USED TO SEt UP ULARTS

8AliDRS

8D.02'UC.P8E

,Initial conaole bauQ rate to
, be 2400, with ,rog. baud
raUl enabled.

OOOilla

TU8AUD

8D • .u4U.C.P8E

,TU58 Baud rate .. 3&,400

22
2l
24
25
26
21
21
29
30
31
32
II
34

PC7

000032

11
18
It

Equate •

1601)10

MEMORI CONFIGURATION EoUATES

167776

RAM80r
IlAnOp

000300
000340

PlU6

•
•..

160010

161776

,aottoe addre.1 ot RAM
,rop addre.. Of RAM

SOFT_ARE 'LAGS AND MASKS

..au

to
to

300
340

;PS for prior lty of ..
;P8 for priority Of 1

, U8EO dJ ODT MOUULt
000200

R'LAG

•

011'1

000020

T.BIt

IUU

,Ragl.ter flag bit- Indicate.
, re,l.ter i. being e ••• lned
,Trace bit 1n paw

«Xfil-A2 II 'IB"w"al
MACRO V06.00
PaDGRA'-••'Ci',C 10UA11a

, ai'tART tYPE wORD BllS

2
l
4

100000

oooaoo

R.IIXIII

R.lfAIe

000001

100000

flO. 10011

000200

DEYaU

12
13

000001

DEVflU"

to
It
15
16
17
18

R.",lot

5
6
7

...•

aun
IU17

eno

IHALI or IRIAk oceurr.o
'ACC••••d non-ex1ltent •••• ry
'Do~~le-'g. errOr

, aout COllfROk WORD 8lfS

5-ocr-11 22c5'127 PAGE 10

0.0100
000010
000001

.
•
.

BUU

,110 ...... , !OlInlt at 000000-

aU7

11 .. 1.01/02 tlOPPV
, ... fUSI c••••tt.
,unit no. (0 or 1)

.no

, 40 not boot

OllGIOSTIC MESSlGES

I.lxt

... Z.T
E.Plk

•
....

100

i.O
1

I$LU2 loo,»act te.t 'ailed
,SLVa tntarnel loop.act fe11.d
,'ara11el port 100p••Ck f.l1.O

............
... .. "
....
•

•• c

Celt.

... c ..

•

.....

c .....

......••

.... .e
.-=: ...
0
.cll ..

......
.11'''

....•
0

...
... ..
• ... u

;;)

...
'"
...
....
..•...•..
..
.
...
to
0

Jo4

lit

•e
•
U

t
WI

.....• ...•...
.......... ....
.. ...
... ...
D

..... c

lIE

cu ...

.....

..X•
....
..
...

IiIJ

00.

•e

......

.c:c ...
...... .c:

til

WI
ow.
ft

lit

• • .c:

...

•

00.
0
"0

to«

t<4

....
••
.....

o •
".A
C.c: ...

••
...

......

...cC
.... 0

ic"
e ......

•If
U

"'0

. . •.
......
....... ......
....
liD .0
CO.
0

..
.....

.c:
0 ....

.....
........

.., . :..
..c:

.c: ... r::

.:I

....

:II

......- ....."
,

0.:1'"

=;:~:

..•

.,
..
....

u
e

.:I

..III

.... D

• ••
+
. 101
.................
-• • ....101
.. A. ..

:I:

..••

101

....I••...........I
.......fA
"U
Jo4

"'0-

••

0-13

Klfll-All 1K Fl.MIIA.'
MACRO DttIN1110NS
1
2

J
4
5
6
1
8
9
10
11
12
13
U

U
16
11

_ACID Y04.00

'-OCt-81 22c56.21 'AG£ 12

1 DIU! A,',.
wnere A and » are n.a•• Of teol.ter. tnat .re fr.e (botn "111
;
be el.ar wnen tnrough) and • 1. an lnte,er.

,,
fnl ••acro produc ••• delay who.e duratIon (wnen running In KIT11-AA

I •• 2)99 •• eeond ••
, ROM)
wnen .<4, It 1& eore efflcient to u.e the fOllowlno eode.
I
I

t
1

;

MOV

I-

9
~

21
28
2t

1111

2.44

Hit

21'861.16·

nil

Itn ••

Rn, •

I1W

1M ,Ra

1211

1111

C10R

1
I

Rn,.

il3,U1.1.}

2391161.76]

24
2S

(508
(SOB

lin

,, the ••ero gene rat•• eOde like tne COllc.lnOI
,1\$:
Rb

('loR
508

SOB

.soa

Rb, •
fla.n$

.ltACIW

DEt.Al
IN,A

MOV

CLa

soa

SOB

.£NDM

.,.
B

AfL

It II
;til

A,IlI.It,?L

l.U
""2.44
6551"""1.66

"").6'

Kx111-A2 lK Fl.M~ARE

MACIIO \104.00

'-OCT-8t 12:56:21 PAGE 13

RAlI OZ'UlTIOJl

1
2

.S8TT~

,.-

; SCRAtCH RAM AREA
TRAP4

167774

ODTlulY

167112

O.CIIT~

167710
16771>6
167764

8.CNTL

1671U

19
20

R.flPti.

....

167762

161760

USERSP

167700

16715.

RPOIN'l

••

167756

1671540
167752
167150
161146

UVPC
OOTfLG
OOTLOC

......

167754
167752
H.7750

1677 ..

DOTSn

1:.1
13
14

15
16

21
22
23

2.
25

9
\J\

....

167776

6
8
9
10
11

26
27
:.18
29
30

RAM Definition

161644

k.PC
III.USR

UVPS

uncil

==
=.

.......
....

....
...
••

••

167776

161714
167112

167710
167166
16776 ..

167146
167744

ODT5T",-100

,Enables trap-to-. eaulat10n
, when non-zero
IUser-readable copy Of R.TYP~.
: Re,tart cau,e. See R.UPE
table tn REStART rout1ne.
,ODT Control word. Set 8it l!i
; to dtsable T-81t t1lter. ,at
;
~lt '7 to dllable Priority 1
fUter.
I
;800t control word.
,Where restart saves top of stack
IEnables uler-caused restart
, and BREAK when non-zero
IRestart cau.a • See table In
, RESTART routlne.
fUsed by oor to .tore the u.er's
, stack polnter.
;Used oy DDT to point to the 1.eQe
; of user'. RO 1n lts stack.
,Store halted pa here for OUT
;Store halted PC here for OOT
;Used by DOT for internal flegs.
;U.eQ by OOT to polnt to loeation
I currently open.
;Iotto. of ODT's stack
'lotto. of default user Itack

KXTll*A2 lk FIRNWARE

MACRO Y04.00

S-OCt-81 22156:21 PAGE 14

/lU OIFllUtlOH
1

170000

.*170000

2
l

.sartL TRAPs-trap-handling routines
.SBTtL tRAPS-LTC Trap-killer
.BaTTL T~APS-8REAK handler

•
!)

6
7
8
9
10
11

1',"""":;;"";,;:""::11,'11;1';;;;',,,,,,"""",t;:
Jlll';;;;"',I';":;1',",",1"".,";;"',1111"""11111;

12
13

1111

II::
11:;

.. saRKa ,

1700~O

00S767

18 170004
19
20 170006
21 170006
22

001001

171760

TST
BNi:

IN.USR
aRUUO

'&IIt.1C; ,

24
2b
26 170010
27 170010
28 170014

29 1100110

8RUOO::
OUU7

1777lb

MO~

012667

171714
1000liO

MaY

012167

171134

!lOY

(SPH,SAVPC
(SPH,SAVPS
'R.HA!.T,It.lfPE

:U 170026
32 1700)2

OOS067
000167

117712
000S44

CLR

JMP

:Are we ln Qser mode?
; YES-GO to aDT
INO-Go back to ROM prograa.
1 8REAKS are ignored bY ODt,
RESTART, POWERUP and tne
DJAGNOSTICS. The B001S
ean be interrupted, thoUgh.

RTl

000002

0'1

""
1111

; 11 HI;;; 1;;; I; l1Hl H II; 11;;' I H;';' 111; n 11/1 ;;;;"'11 1111

16 170000

""
1111

';",1"',',111111111:1111';;11Jl',;I',',;,1'I',;11111111,"

14
I!)

aREAK-HANDLIHG ROUTINE
AND LINi TI~t CLOCK INTERRUPT KILLER

I;;;

IN.USf<
OOT

,Save context
Itof OOT.

:eaus.s PC to be printed
; upon entry to 001'.
;Get out of us.r mOde

••,s,-al I ' 'laM.A.1
1",al'-"'IQPUetIOI

MACIO Y04.00

5-OCt·ll 22156127 'A~I 15
.aBttL REaTARt-lntroductSon

2
l
4
5
6
7
I
t

10
U
U
13
14
15

U
11
it

21
::12
2J
24

tj:7

.....

26
27
21
2t
30
31
32
U

34
:U

""""""""""""""""""""""""""" ",,,,
""""""""""""""""""""""""""""""

""
""

RlaTART MODULE

""
""

'"'
""
""""""""""""""""""""""""""""""
""""""""""""""""""""""""",,,,
"""
,.

,'the purpo.e of the REa'ART roatlne I. to rl.tor. tne 'ALtOM to •

,known .t.te fOllowing tho •• e.c.ptlon. Which C.U.I e RlatART h.rdw.r.
,.cClon. Thl • •ctlon con.l.t. of .t.cklng the current
nd PFO~r ••
,counter. thin .etting tb. paM to 340 Ind lu.plno to thl h.rdwlrld
,RUtAIlT 10caUon. 1"111. 10cIUon 1.,.t tb • •ddrall atARt+4 whir.
,'TART 1. loaper •• llct.bl. II 000000, 010000, 020000, 040000, 100000,
,140000, 172000 or 173000 (.11 In oct.l). tbl. proor •• II d •• l0nld
Itor I STAR!' location Of 172000, tl'lVI RIItART. ,v.p to 172004.

,a••

,TI'I.r • • rl leverll dlfflrent w.y. In wblch RESTARt plrfor•• it.
,function, deplndlno on tnl v.lue of IN.UaR, TRAP4, thl cont.nt.
,of thl loc.tion tne ap point. to, .nd one bit (R.StAK) In R.TYPE.

,
,,-,R.tYPE, the rl.tlrt type word, 1. RlaTART'. output to OOt.

I•

'tbe 0011 1. to •• xl.lz1 PDP-l1 .oft •• rl co.p.tlbll1ty .nd to provldl
lu.elul 4.buo~lno lnfor •• tlon to tne proor •• dlvlloper.
I

Iltll-'2 II fIR.W,aE

lIatAI'·lltIODuCfIOM
1
2

,•
,•
10
5
7

U
12
U
It
U

Ii
17

11
It
20

:111

"00

22
21
24
2S
26
27
2.
2'

ao •
31
a2

JJ
I.
:U
I'
17
I.

.0
tl

••
••
4S

.t••so
47

SJ
54

MACIO Y04.00

5-0Ct·~1 a2IS'127-'lG~

,,
,
,
,,
,,
,

.1.

£nt.r
h.rd••r. ..ehanls.,
With (,a).'40

I R.nlf I
.............

------.....---Is the ataclt

Ua, setf

•

------------------I.t R.MXII
a.t 111-10" .od.
Go to OOt

I
I

,
,,

-----------------.-

I -.-•••• -.-----••• ---------------

a.t st.Ck Dlt
I
•••d top of st.Ck
I<---Could tl •• out .nd c.us. the
Ch.ck If too clos. to -hol.- I<-----.xlt to DOt shown .bO••
Cl •• r staCk bit
I

,,
_........_-...-----------------,
I Old r.st.rt occur
I
In us.r 100.'
,
,,, Is top of 1<------.··-_· A I.Ela do.s thls wh.n
0000001
tn.r.·s no •••ory In
,, st.ck
•
r
tn. v.ctor .r •••
,
...----------.,
Pop st.Ck IC-+--._. only •
whll. In ODt can
er ••••nd I I
,.t us h.r., so tn. Rtl t.k.S
,,
r.turn
I I
us b.ck to oot.
--••----------- I
,
I

I
I

•

I
I

.R~ll

---------_
.._-----,,- _._----._------att carry
I L.... u.. r 10d'l
in pusn.d '6
--------...
_._._-,, .---.nd......retllrn
._._---_.-_.-....
I
Is top Of
,
I at.ck OOOOOO?
I

~-.-.---

, A l.iAK dO.s tnls--->I r

..
.hen ther.'. no
----------------I 1.lo"r in the
_._-----_.,.._._I .ector .r ••
,op st.Ck
IC-·-.-·---·tnls .ntry polnt 1. ln
I
tr ••••nd 90
I
the TRA.a .odul.. It Is
to ••EAK·s
wn.r. • IIEAK In us.r lod'
IAYE CO.tEX!
90.S wh.n th.r. Ia 1.101'1'
.nt .. y point
In tn. v.ctor ......
I

,,,
I
I

KXTll·~2

lK Flft~WA~E

~AeRO V~4.00

S-OCT-it 22'56'47 P~GE 11

R~5TART-INTRpgUetlofi

1
:I

Pop stacK fra.e
if 172004 on top.
Get pusheG PC.

3
4
5

set UP CDT·. PC
and PS location ••

"
7
8
9

10
11
12
13

COULD··-->I
TIME----->l
OUT-·---->I

Test word prior
to where pushed
PC polnts

15
16
17
U
19

20
;ll

II.. tne WOld
a HUT
or dld PC-->NXM?
Y
fI

22
2J

24
2S

26
21

9
\0

Set HALT Uag

110 to ODT

211

29
30
31
32
13
34
3S
36

Is trap-to-4
•• ulation
enaDled1
H
Y

Set HX", flail
Go to OOT

39
40
U

42
U
U
45

Set IIser 1II0de
Push .. 6, ....
onto stack:
and IITI

'.I

Iltll-,a II ,'R••

"'I'.I-'.'.ODI(I'oI
2
)

4
5
6

•
9

10
11
12
U
14
II

'617

II
l'

20
21

22
2i
2&
25

26
27
21

)0
II
)2
U

)4
35

16
J1
)t

it
60
41

MACRO YO •• OO

'-OCt-II 22 ••,,27 'AGI II

,'+
,Ixc.ption-typ. word ( ••
1. p••••d to 001 .nd 1. RIllA.'. -b•• t 9u•• ,,, •• to why • r •• t.rt h.pp.n.dl
lot •• A u•• r-r ••d.bl. copy of thl. word 1 • • t 001••1.
,,
TIP~)

,,---.-.,--··-1-.-··---1--------.-----.-.------------------_._.------.-..
'1 IXlt I 8'1 IliA.' I CAU'I
"·_··-·1-----1--------,------·_-----------_·_·_------_.---------.-.----'1------1
I
'1 001

,.
II
,.

R.HALt I KALt In.tructlon In u•• r cOd.-aE'TARt POPI IIACI.
I aot.·B.IAI 11.0 .et. tnl. bit (.e. thl IRAP.
I .odull). DOl a••• thl. bit for PDP-II UOI
I CO.Pltlblllty.

I 15
I
I
I

,1·---··
14
II 00'

,1
'1
"
, I
II

Oli
"rItAP
TO
."OUR

I
I

RI.lr.lcI

I •••• rv.d

U
12

I iI••• rv.o

I RI.lrv.d

I a••• rv.d
I •••• rv.d

••• ory
I
I a•• lrved

rv.d
.,I I R.IIXII II ••••
tI ••out durlnv u•• r ICCI.. of non-•• I.tent

"""
"

•••• rv.d
R".rv.d
•••• rved
•••• rv.d
I R••• rv.d

I
I
I
I

•

,I
II

2
I

'1-----·,-----,_·_·----1
,1 001 I 0 I ••• tAK
'ndlcat•• that a tl.lout ••• Cla.ld bY alitAaf

''1,I1
'1
'1

"II
I
I

I
I
I

It •• lf Icc••• lnv non-.x'lt.nt •••ory. Inl.
occur I In conJunction wltn t.ltln9 for
v.lldlty of tnl It.ck polnt.r.
tn PDP-II p.rl.nc., thl1 II •
-dOUble-bu. 'rror-

.
,,,--··--1-----'------_·,-·_·_---_·-··---_·-------------------...........
,-

KXtl1~A2 IK 'llM_All
REaYARt~E~JRY POI_'

MACRO V04.00

5-0CT-81 a~'56127 PAGt 19
.$&TTL RE$TART-Entry polnt

2
3

;11;:111;';"",;;"',1"""';11111;;;111;1"",11111 "~I;';

";111;;1',1;;',1",','"',',',:;;""11,,;;,,1;;;,;,,;"'11
nil
lHl

."
5

1111

1
8
9

11 nOU6
12
1l
14

;;';;;;',11;;;"""';";;;;;;;;;;"11"';;111',"";;11;;1'
;;;;"',"",1;;;;;""",;;",;;;;;;,;",,",111"'"11111;
1111

16
17

";;

"~;;
n;;
III'

19
20

I;;'

IF THE R~stAMT RUUTINE CAUSED tHE RESTART
GO I~ oot AHD PRINT "'tMlS EXCEPTION CAN 8E CAUSED BY RESTARt·,
$TACK MANIPULATIONS

liB

1111
1111

IHI

11J'

;1',

1111

;;"',';11";1'1';"",11,';';';"1'1;'11",',1;1,",;,,",;
;;""",1""";",1;1111;1"";"";;'1""'111,"""";1

22
<U
H

R.TYPE wl1l have been cleared prior to enterlnq
any oPt command. $0, it tne stack b1t 1$ set. only R~START
itselt COUld nave caused tne trap. Slnce the staCk i . alwaY'
valid In 1n-~OM mode, bad stack Meana we are 1n In-US~R Mode.

2(t

27
28

,Stete: X-don't clre. Ucuser. Rcln-ROM*---

30
31

32 170036

;u 1700n
J4 17004.
35
36 170052
H

nil

R.stRUt

"II

""";""",';;;';;""',11;"'1,";;1,";"",1;;11;;1;;;
';;';;;111:11;';;;;"';:111;"";11#1111;';;1';;;11,,,I;;',;

REaTART ENTRY POINT

nil

l70QS6

005167
001406
052761
00$067
000476

117720
000200

177106

T$'l

171710

8£"
SIS

R. TJJ>t;
1$

tR. to,,,, M. Ut't:

eLR

IN.USR

!If

;XIOld tne Itack test fall?
;X,MO· 90 to next test
JUllES- ,et R.HXM
,UI thiS torc •• -1- troM OOT
;Rlenter In·R~M .ode
;Rlgo to DOT

KXfl1-A2 lK flR~.ARE

MACRO V04.00

R£&fARr-SEi 1f aTACK ExIStS

5-0Cf-81 22:56127 PAGE 20

• SBl'fL

RESTART-See if stack exists

;;;111111;;:1;11;;',1;11';;;;;;;;::;;;1;;;;",;;,,;;;: 1JI11f

II;;
I;;;
;;;;

•,.

';;;;;I;;;;;';:;;;I;II:~;;lt;;;;;';;;;1;;;";;:I"I"1 "111;

052167

000001

177&74

1S:

005716

ooo:ao
00$766
000240
005067

00000.
177656

SIS

fit .S'1'AI(, R. T),PE:

tST
Nap
tST
Nap
CLR

($1")

4(51")

R.TYPE

;xllt we tiMeout, we want RESTART
iXI to know we were diddl1nQ $P
;Xlsee it staCk 1s valid
,XI(ln cas. times out)
;Xlsee if too close to top of
, x I valid Il!elllory
tXlstacll: is 01(

;;"';;;:Jll';tl"';;;;';;111;7;;;~I;;":;"';';;I:;::;:;11;

";;;:;",";1;;",1"",1",11;"';;;;"";1"""", "~"~;;

1111
I;';

11n

25
26

HH
Inl

.S8TTL RESfART-Exit if 1n IN·ROM state

20
21
22
23

N
N

lIn

YALIDITY fEST

"11;;";;,,,11111/,'1111;111;;;1';;";;;;;;;;;;',11;;','.1;
";;'11";;;1,";1;111"",/111;;;',1;;11;;11;,1,'111;;;;;;1

10
11 170060
12
13 170066
14 170070
15 170072
16 170076
17 170100

STAC~

RETURN WITH CARRY SET If IN "IN-ROM" MOPE
OR, GO BACK TO OOT If A BREAK kITH NO LOw MEMORY

1117
;" I

Uti
Inl

;;;;';;;;;1"""7"";;;;1";;;:';1;";;;;;;;"",,,;;,1111
",11;;';;;;;;;',;;;',',""';;;;';',1";;;',"',"';1;1;;"

10
11
32
U
34
3l:>
36
31

170104
170110
170112

005767
001007
005116

170114
170116
170120

001002
022626
000002

39 170122

005266

40
41 110126

000002

Tst
aNE
'lilT

177654

000002

2S1

IN.USfl
1$
($P)

BitE
CliP
RTI

IIIC

2(sP)

fiT!

(SP)+, (SP)+

;lIAr. we in user *04e?
,UllES-go to next test
IRINO-see 1f BREAK brought
;111 us here
;RIHG-Just a RESTART
;NIYES-Behave l1ke a 8REAI( tnat
IRI happened with RA~
;Mlllet carry in pushed PS
IRI UNLESS ALk~AOl SET
;Rlend return to ROM code that
;a. caused tiseout

KlflS-A2 lK 'laAWARI
IIACRO Yo..OO
RlaTA.f-CAU•• D~rIRII1N1T1ON
1
2
3
4
5
6
7

22156127 PAGE 21
.IBTTL RESTART-caule deteralnatlon

11"""""""""""""""","""""""",,,"""
,,""""",,"""","""""",""""""""" """

""
,""
'"

"",
,,,
""
""""""""""""","""""""""""",,, """

9
10

~-OCT-Il

nouo

12
13 170n4
U

IS 170U6
16 170140
17 17(1'42

DETERMINE HO~ USER CAUSED A RESTART

""""";"""""'J~"'J"""J;""";""""'" """

0050.7

177630

311

CLR

005716

TIT

001003
022626
000167

8NE
CliP
JIIP

177642

IN.USN

(SP)

(IPH, (5P)+
BflJ(NIJO

18
19

9
N

\,0;1

20
21
22
23
24
25
26
21 U0146
211 170152
29 &70154
10
11

;

If the CPU atte.ptl to tetcn an lnltructlon troa non-exl.tent
aeMory, two trapi (tne tlrlt fro. executlng a HALT, tne lecond
troM tl'lng out) wl1l occur, the re.ult belng tnat lecond
trap pUlne. tne rei tart addre •• and 340 on tne .tack.
Tnl. lnfor.atlon 11 ulele •• and tet. popped nera.

411

CMP
8NE
CMP

021621
001001
022626

172004

35 170'S.
)6 170162
17 170166

,,
,
I

01.2661
011667
014.67

177604
177566
177560

162767

000002

51:

(IP), IRElTAR
5.

(IPH, (5PH

4l l,oa04
44
45 170206
46 '70210
., 170216
4' 170220

005777

177566

117562

MOY
MOY
IIOY

001005
052n7
02212.
000415

SUB
tIT

000240

(lP)+,R.PC
(SP),SAY"
-(5P) ,IiUPC

,RIGet pUlhed PC
,RIODt _ould like
,Rlto lee tne.e

12,R.PC

,RISet polntar to la.t .ord tet~had
,Rt belore re.tart occurred
,Rll. content. of ,u_hed PC - 2
,kl a .ero 'eg a HALf)t
,11I'ate lure next In.tructlon
,111 won·t axecut. If .a tlae out
'RINO~ It w•• an 11M
,IIIY£.- Fla, a HALf,
,11,,0, tn, "Oft-PAt'-'.l .tact tr •••
,Rland yo to DDT •

,It.

NOP
, ..I:

100000

17754.

,x"et rld of double .tecking
,X,cau.ed by iXECUT1U_ Of HIM
,XI

Note. aeeau.e tn. content. of tne .tack 11 a.,u.ad to re.aln
unChanged follo_lnt the flrlt In.tructlon below, lt 1, 1.peratlve
that lnterrupta be dl,ebled durlng the next tnree In.trutlon ••

19 170172
40
41 170200

IUIWe ware In uler aode.
,RI but no lonter.
,RISee If BREAK brOutht
,RI UI nere wltnout low wcore w•
,RINO-JUlt a RISTART
,RIYI'-'ena.e l1ke a 8REAK tnat
,R, nappe ned whl1e In u.er prog.

II.

CH'
8ft

.,I.HALf,R.fYPE
(I')., (IiPh

••

jOo

"...a•

- ......,
_0. . .
...........
=
c

......_...................
-.- ........ ...
.,•
..............
• :
..•.
~--""- ......
....
......
'
"
......
k
.....
•
... ...... o.,
.....
...
......
ca
......
....
......
...... ... ...to ...
.......,k MO
•
......
...
..
.....
......
... ... ::.&:U .. g • •
_
....
............ ... ....·w ..........
......
.....
...
............... ... ......... ......... ... .. "" .........
.....
... ... .....ac ... ...
....... .....
... . ... .....
......
. ...
......
...... ... ~ ......... .........
...• ......
...... c ..... ....
...c ........
...•...
..... ...
.....
.. ...
... ......
... ......
.
...
......
........
...... '" ... ...
..a ....
•
...... '" ...... ...... c . . "•.
•••
'" . .....
.....
......
•....
...... . .
......... ....... ••••• . 0
......
...... ......
.
...
.....
..
... CII.»»'"
..
......
•.
...... ........ ......
......
.WOOO'"
......
v.c.
............
...... .....
...
..• ........
...
... ...
, ...............
•u
..
..
....
.....
....... -............
••..
a
........
•
•
...,.....
•
I

---_ - ....-s:.CIt ....

CIt ..

... CIt

. . . ::.t=o::t::t

101
B

101

toe

C't

UI
C

..
to

ill

.
.
l1li:

.
..
.. . .. ..
...........
ill:

1010

:::t

ill:Q

.....
.....-

/'OIl

III

..~

tot

..
1ft

.•

---_--- .

1ft

0
0

»
0

•e

•

""l1li:

.... ...... ••
0

".
Itt

0 ••
"".0
1ft 0 a

... 0 0
"'00

0'"

tot ...
.0

.. ,..

••
......
.... 0

..........
.....
Itt •
•

CIt

00
.......

.. tot ..... "..,.. • • • ~ ........

I11.,.. ••

... fIIII .................... ...

1).24

KXT11-.a l~ rla_WAR£

"ACRO vo,.OO

5-0CI-81 22:56:27 PAGE 23

'OW£RUP-IN,RQOUCIJO_

.SIITTt. 'OWERUI-Introduetion

,
1

111",1;;","";I",I",';J,,;"',"I;"";1111111,"11,",
1111;'"";11"';',',1111;11111"",;,,,,1111111111,',111111
;;11
1111
POwER-UP MODU4E
11;1

6
1

1111

IIIIII1111111111',I;",111"",","',llr;111111',11', ;;""
;1"'11111111';;1111111;;1","",1;;",,"",;;',,',1;1';"

•
10
at
12
1]

14
15
16

1111

Thts Module contaln • • serle. ot routine. which pertorm
; te.ts on tne on-board R4H and the console P4.Rr. rhea'
I testa ar. preceded by the liGht1ng Of the LED on the
t KX!11-AA boerd. end followed by its extingulshin9. 4hould
I the LEP fell to elther 119ht or 90 out, there •• y be a
I defect In the boerd or it. configurat10n.
I

18
19

20
21
22

"
N

, 'ollow1no the,e testl, the on-board RAH 1s wrltten wlth the
I default values ot eertaln control words, end, 1t there ls
I ••• ory 1n the vector region (1 •••• neer 000000), the BREAK
I and clOCk v.ctor. are set UP.
It not, • bLt 1••• t 1n tne
I boot control word to d1s.ble the bootstraps.

Klttl-Aa lK FIRMWAME
POWIIUP-fURN OW LED

MACRO Y04.00

5-OCr-Sl 22:56:27 PAGE 24

.sartL PO_£RUP-turn on LED

,,""",",.,,;"",,"""""",,,"";""",,""I"'"
",""';1',,',""""',,';"',7',",';;1,",1,',;1"1;"'1

UH
""

11
12 170260
U 170260

PWlI$UP: :
012706

167644

MOV

20 1702 . .
21
22

U$TACK.SP

;lnltlaliZe .tack pointer

eecause a .ode-setting com.and automatically clear. all the lnternal
registers 1n the PPl, and clear1nQ Port C 8it , turns on the LED, all
.; we have to do 1. set tne mOde, whleh 1. port A and 10 nalf of C a.
input, ports B and hi nalf of C as output.

U
16
17
18
19

tURN ON LEO
""
'U,
1111
11"'11""""""';I";J;"';I""J'~";"'1;1""",;t:JI
;;';;,11""""""""""":;",;,,,,;,,:1"11;;;1'",,,,

7
8
9
10

(127)7

000221

MOV

176206

'MOOE,.'PP.CWR

;Set proper PPI mode

.S8TfL PO.EKUP-Te.t console OLART

H;' n II II r;; II' H"n; I; H; II' U;;, 11;"'; 1;',;;';'''; In:;

IV
0\

;1,;;;;;;;";I";,,,;;;;,,111;IJ;;;;;II;;;::;';;;I/I;1 I : ; ; ; '

26
21
28
29

JlI1

:,;;

;;';;;1;,;;1;;1';;;;;;;1:';;::",;:;,,;;;;;;1;;;"";'II;;;'
;;1;;;;1;;;",',;1;;;1;;;;111;",1;;;';;;;;;;1;',1;1;; I I I ' ; ;

005031

177564

1105737

1115(;2
000)00

CLR

UXCSk$l

TaT

,IRBUf$l

II
H
31> 1102:16
30 170)02

032131

117560

BIT

39 171'1312

40 170320

001371
021721
001311

8Nt;

177564

000200

CliP
8liE

101.4ble XMIX interrupts,
; BRK XMIT, .a1nt. mOde
I
Set baud rate to default
;take out the trasn.

.(RC.l£~lkC.OUN>"18CSN$1

18 110310

lHl
11;1

TKE CO~SULE OLART

In:

)0
11

32 170212

CKEC~

UXCSRIH,UC.ROY

;Snould be clear.
lIt not, drop dead.
;Sbould be let
;If not, rest in peace.

KXT11·A~ lK rlRMwARE
MACRO V04.00
POWERUp-r£ST AND SET UP IiO-PAGE HAM

$.OCT~81 22:5b;~7 PAG~ 25

.S8rT~ PO.~RUP-Te.t

2
3
4
S

;',;111;;;1",111;;';1;1';;1:;1',1111111;;"",;1;;;1;1;;;;1
'."',1""'.",1"'1:"11,';1";;111;;';;;;;;;;;;111'1;""

;:11
;;;;

7
8
'9

"
N

"-ol

AND IHlrIA~IZATION

n/l
11;1

';1;

1111
HI;
; I , " I I 1 ; I;; 1 ; " II I n ; ; 1 ;; II 1 ; II ; , , ; 1 ; ; f n; 1;; " 11 J : I; ; H 11 I

1111:;;;;;:111,',11;;1;;11;;;;;;;;;',11;;1,',,1;1;;";11;;;1

22 170332
23 170334
24 170336
25 170H2

1/0 PAGE RAM TEST

I;;,

10
11
1l
14
15
16
17
18
19 170322
20 17032&
21 170330

and set UP liO-pege RAM

~rlte the locatlon"s address into tne locatlon and read 1t baCk.
; DO tnt. tor ell 110 page RAM loeations,
1 It it fal11, enter t19ht loop,

In the process, clear all of thl. HAM. Note that the detault
value of .Olt ot tne control and flag wor05 1. zero.
012700
010010
020010
OUll17
005020
020021

103111

160010

MOV

:a:
170000

MOV

eMF
IJNb;

CJ..R
CMP
IlLO

IRAM.\IOT,RO
RO,(RO)
kO,<RQ)
:U
(1<0)+

RO,.RAMIOP+<!
1&

ILowest addresl ot RAM
;Wrlte tne adarel.
:Read it back
lTlqnt failure loop
;Clear and go on to next locatIon
;Untll no 50r. to test.

.
..
•
........ ...

.co

. ..,
.....
... .......... .
... ..
•

... •

•
'"

::Jo •

..
•• '* .,
.. ...........................
"'II.
...
-................... -"'. .......
...........
..........
...
...............
•.
. ...
... -'....... _.....
_
......
..
...
...........
"'0'"
.....
....
.....
..
..
......
...
.....
....
.. .. ...••
• . . ....
......... ......
..
... -.
.
....
.....
......
.....
.........
...
...
..
"" ... ..
..
..... ....
--..
....
......
...
.'
"
.....
..
.....- ..--... •.. ....... ...... ....0
..... .....
....
.. ....
••
...
•
..
...
.
...
...
...
............ ....
.. ... " ... " . ... ...
. .... .. .. .......... •
--............ .................. .......
..._.. . ...
....
'" ....
.....
.
..
..
..
... ...........
• .. •
.
..
..
..
.. .. ... ...
....
....
... --....
.... ... ..
..... .....
.. - ... ......
....
...
"
.... .. ••
. ...
.
..--... ...•. .............-. .,.. ....
..
.. ........ ... ........•
.... ..... .,'". • .. '" ....
.....
.......
.... .....
""• .....
"' ...
..
_
... .'.....
...
_
..
"
....
....
-'"
....
.....
......
-'"
"" .....
..
..
...
..
.....
""
'"
..... ... ....
....
-•
....
.
.
..
..
..
'" .. ....
_...
'" .....
.«it._ • .... .....
.
... ....
'" ...... ..-.....
..
..
...
.
........
- 0'".. .... '"' ...
.....
....
....
...
..
......
.....
... .
..
..
....
...
_...
'"
.. .. ...
.......
.. ......
.. .............
......
....
..
....
.
.
......
.. .. ..-.....- .....
... .. ....
..
.....
.... ....
... >0" . '"
....
....... .
......
.....
.
.......
....
.0 ..
_.. ... .... ..... ..... ...:
....
....
.. ..... .......
..
..
...•
.....
.... .....
_..
. ..
......
..............
.......... -....
...... .::::1
'"
...•
.........
.
.
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_ ..
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N~~NNNNNN~~M~~~"~M"~

;:1

::2
1)..29

KXT11*A2 tK tlRMWARE
MACHO V04.00
4U'l'O&AUO-UNCHRONlZE IlilTii COUOL"

~-OCT·&l

22:56:27 PAGE 2i
.sarTL

2
1

AUTOSAUO-Syncnroolze with Console

:iJi;;;J:',11;;;11';;;lil;I;;;I;;;111,;;'::',;IIJI;;';1:;;1:
111;;1;1;111;;11;1;;;;11,";;;;1111;;;;;;;;;;1111;;;:;;;1':;

4
5
6
7

;;;;

i;:;;;;l',"i;J:lil:Ji;;J;;;;J1I';;:;;:f:l;;;:1'i;;J;; ,tfl;;
;',1;;;;,,11,;;;;;;;,;;;;;;;,;;;;;;11;;;;;;;;;;;;;1;;; I';;;;

nil

:; ;;

10
11

AUT08AUO MODULE

Oil
; ; ; ;
I;;;

lJescrlptlon:

12
AUTOBAUO allows the FALCON to auto~aticallY synchronize its
console OLANT to the baud rate at tne console terminal.
On power-up. tne user must type a carrIage return Character.
upon synChronization, AUT08AUO will proceed to DOT .here an .~.
Character w111 be displayed on toe console.

13
14
1!>

16
17
18
19
20
21
22
2l

AutObaUd w111 loop Indefinitely until syncnronlzatlon 15 successtul.
The algorithm requires that the console termInal generates a
zero (space) for tne eighth bit 1n the carriage return. This
c111 happen 1t the terminal is capable ot sending eight-bitno·parity or seven-b1t-odo-parlty cnaracters.

'9
f.N

25
26
21
28
29
30
31

k:nvlronlllent:
Interrupts must be dlaabled for the algorithm to execute correctly
slnce tiNe ~urdtion5 are cr1tical and delays due to long
serv1ce routine, may cause OLART overruns, chlcn this routlne

ignores but cannot tolerate.

32
H

?Ti03/fALCON configurations ieave garbage 1n tne OLART long after tne
pO~eru~ sequence has oe~un.
We .uat oelay & bit Detore clearing garbage
out Of tne DLARl, otherwlse tne garbage woula arrive after the Clear
(I.e., _nIle poLling tor input). Tne ·garbage- Is an X-ON «CIWL-q»
that the VT-l00 hard~are sendS atter its power-up diagnostics nave
completed successtully.

3!>
36
31
38
)9
40
41
42
U 170472
44 110472
411 170SuO

4' 170502
.,

170~O.

AlJlUBA::
Ot:t711
0050(10
017001

017001

000032

17751>4

MOV
eLk
SGtS
SO~

ISAUl>!<S, ilIXCSRIS1

NO
!tU,.
RO,.

;Set 24UO baud
IOela\{
.S
U:conda

Kxrll~A2 l~ FIRMWARE
lUCRI,) V04.00
AU108AUO-Srr.CItRUIIIIUE IIUII CUNSULi:

5-0Ct-¥1 22156:27 PAGE 29

; AUT06AUD proper:

2
J 171.1506

105U7

£7156;1

lOU

TStl:!

nRIWf.l

5 170>12

discard any gerbeg.

105H7
100375
113100
0127ut
120021
001411
020121
001173
005000
077001
000751

177560

lOG:

Uta
IIPL

URCSI<$1

welt tor input

MOVa

UIiBUFtl, lIu

II 170516
7 1705:.10
8 1'10524
9 170530
10 170>32
U 110534
12 170540
U 170542
14 170544
lS 110546

11756;1
1105511
110550
40$1

9
1M

eMPS

AO II 1nput enaracter
lit -> Icre.Dled cher taole
1n tne table:t
yes
end of table reacnedl
; not yet
un oh, wait tor DLART to clear out
walt tor • wnile
I and try tor another ~haraeter

UHliYft., R1

110, (111)+

8t;Q

IIveAII",

CH"
SHE

iU, HH8YTS

'LII
SOB
iill

itO

308
110, 40S
10$

; Tacle of _hat YOU would see it an o~tal 15 were .ent at tne tOllowtHo
; bauo ratel_

20 1105!tO
21 110550
22 170551
23 170552
24 170!t51
25 11055.
26 11055:27 170556
28
29
]0
:U 17055_
12 17055l>
H 1105112
34 170564
l:. 1705"6
36 170570
17 170572
38 110576
19 17061Hl
40

MOV

lOSt

20$

1flil UIl:;

200
170

Ott.
362
177

INnu;
I

162701
006301
006301
005201
006]01
0111137
005000
077001

.l!lTL

200

• 6l XTt;

170
346

.au£

346

170551

177564

.BYTt:

l50

.BXTe;
.BYTE

362
377

.e have a .atch.

360
600
1200

240v
4300
9600, 19200, 38400

bet baud rate lnto DLAkT.

HI/bAUD:
SUB

JIlL

UHIiIY1E+l, HI
ill

ASL

UlC
ASL

iU
111

lIOV

CI..II

R1, .. lCSRU
RO

SOil

1l0,.

; "aU 1nto OOT.

turn polnter lnto btt .aSK
turn on XC.PIIE
set tne baUd rate
1nto C:;R
delay .24 seconds for reat
of ch.r. at 510 baUd rate.

CIIll-A2 lk fIRN.ARi
. .CAOODT-IMT.ODUCTION
1
2
1

.ecroOOr-lntroductlon

1111

•

9
10
11

12
11
14
15
16

17
11
19

24
2~

.S8rtL

5-OCr-11 22:56127 PAGE 30

"""""""""""""""L,,,"""""""""""""
""""""""""""""""""""""""""""""
,,,,
""

•

tj:'

AACRO VO •• OO

'U,

.ecrooor

""""""""""""""""";"""""""",,,"""
""""""""""""""""""""","""",,,
"""

.ecroODr II the uler lnttrtece to the functlonl contained
In the KXTll-A2 fir.wert prOduct. It interpretl co••anGI
, entered via the conlole terelnel keYboerd (I.e tabl'l Delo.)
; to per.it tht uI.r to 10ed a proqra. Into .e.ory, e.ecute
, it and debu9 It.

1
1

,COIIIIIANO
,
I

,
,
,
,
,
I

2If

30
U

1- oSluh (I)

a-OPEM "IMDR! LOCAtiON
b-OPEN G'N'RAL RiGIStER
C-OPEN atATU. RlGISrER
2- Carrla,e return «CR»
a-CHANGL AND CLOaE NEIIORY LOCAtION OR R~GISTER
D-CLOSi. WUHOUt CHANGE
1- Line feed «Lf»
a- CBAhGE AND CLOSE Mi-MORY LOCATION AND OPEN N&l!
b- CLOSi MEMORY LOCAtIO~ wITHOUT CHAN'lMG AND OPEN ~EXT

•• c.o (0)

~- Proceed (P)
6- Exec~te 110 d1e,noltlc. (X)
1- &xecute bootitrapi (D)

KXT11-A2 lK fl~MWARE
MACROOU1·I~TRODvCT10~

1
2
J

•

5
i

"
10
9

12
13
14
15

16
11
13
19

20
21

22
23
24
25

\,0,1

27
29

29
30
31

32
J3
l4
h

~ACRO

V04.0U

~·OCI·81

22:Sb;27 PACE 31

:SHlTAX Of Cl..tMMANOS L1S1£0 AbOVE. SHOWING CONSO"E &ErQKE,
AHD AfT~R THE TY~LNG Of THE COMMAND.
Key; n-an octal integer typed by t~e u.er, only
la5t 6 diyits significant
x-a 51n91e oct.l digit
u-tne diQ!ts 0 or 1
all other characters are l1teralli

;DURIH~

SErwllE

DURIN!>

AftER

lInl
\!In/xuxxx
tilRXI
tilRx/xxxxxx
IIRol
tilRc/xxxxlOC
; 2011 ,n/XXlIluX
tiln/xxxxxx n<ell)
iI
; ila lIflx/XJ(l(XXII
!!lRx/xXJ(Xl(X n<CR)
12a illlli/xxxxxx
ilhx/xlIlIXXX n<ell>
II
J2a xxxxxx/xxxxxx xxxxXX/xxxxxx n<eR> II
;.It> I!jO/),XlIXXX
in/xxxxxx <ell)
: 21> ijoiht/.lOIXXXX
;,!I{x/lIxXXXX (CR)
~
t;<t> iRS/xxxxxx
fRS/xlIXXlCX <CR>
li
;2b lIXllXXX/xxxxxx XXXXlIX/xxxxxX <CR) li
;311 'n/llxlIXxX
fn/xxlIxxx n<LF')
XlClClCXx/xxxxxx
,311 xxxlIxx/xxxxxx xxxllxx/xxxxxx n<Lf) XXXXXX/XlIXXlCX
;3b 'n/xxxxxx
tn/xxxxlIli <LF>
lIXXK10tlXXlIXXlI
;3D lIxxxXX/xxxxxx xxxxxx/xxxxxlI <LF> xlCxxxx/xxxxxx
1!In!>
;5 (iI
,p
Ii
!!lJ(
XXXlCXX
;
;1a "

111>.

;lei

"
,

,.. ,
..

,7
:7

17
;7
;7

,,
,
(iI

i'
iI

,00u

'OXu
'OYu
(iI{W<CR>
ilOX<CR)

tlOl«Cr.>

Klfil-All lK FIRKwARE
MACRO Va4.00 5-0Ct-81 22:56:27 PAGE 32
MACROOOr-SAVE STAtUS AND PRINt PROMPT
1

.S8tTL $acroODT-Save status and ptint prompt

2
1
4
5

:';;"',11,';';"'11;;:;;;;11;"",,:;;;,,;;;;;,.11;1;,;;tl;

6
7

;:;;
SAVE COII'lUl, PRINT MESSAGES AND PROMPT
111;
"11
nil
11;';;JI;;;;;"77;;;",;:;;';;I;;";1';11.',1;;';;;::;;;ll;;

1111'Jl;;"",":',11",":';;;:111"11111;;,,11;',II:1111;;

,.8

111;;;;111111;;;1";;;;;;1;1,,;;;;;/11;;11;;111;;;;11;111;11

10
11 170602
12 170602
lJ

HII

OOT: :
105737

1175€>2

TSTS

IilfRlIU~ U

;Cl •• r out console garbage

; copy the restart type word into user area

lEo 170606
11

0107,..,

177150

U
Hi

17711>0

MOV

; Protect aQalnst stack tl.eouts, but save user's Sf first

20 170614

010Ul

17'1140

MOV

21 170620
22

012706

167744

MOV

23
24

9
w

..a:..

25 170624
26 170630
21 170UlI
28 170634

29 110636
)0 170640
11 170642
32 170644

R.TYl'a,ODT.HY

IiP,USERSP
'OUrSH,S!?

Save rest ot user program's context
016710
0105 ...
010446
010346
010246
010140
010046
01061>1

177130

MOY
MOV
MOV
MOV

MOV
MOV

MOil
117106

MOY

USERSP,(S!?)
RS.-(/iP)

005767
100004

171100

016700

177070

004707

0007"..

105761

177070

1<2.-(SI')
I'll ,-(:;1')

RO,-(SP)
SP,RPOINT

53
54 17070_
55 110112

56 170111.
57 170122

liP!.

R.TYPE
QODT

MOV
CALI.

SAYPC,RO
aCToSTO

R.TYP£

81'1.

KlIO$

TS't

OOD'r:
10000)

4'47

.8 110614
49 170674
50 1107011
51 170702
52 170102

ALL
Of

R3,-(SP)

USER'S

GEIIIE:kAL
kEGISTEkS
,PU1NTER TO RO

aetermine whether "lW or PC messeQe 1s appropriate, and pr1nt it

44 170672
45

;RESERVE LOCAtION fOR Rb
,SAVE

R4,-(St'>

H
35
36 170650
37 110654
l8
)9 1l0OS6
40 170662
4' 1706.6
42 170666

;SAVE USERS STACK POINtER
:LOAO NEoi SP

rOld we qet a HALf or IIREAKl
INO-next questlon
,rES-PRINt tlC
1GET stOPPED PC

11YPE TKE: PC ON fERMIMAL

, SEE If' REUART OCCURRED
;(NIM ONLY-&IT 7 SET)
I TtPE PROMPT

Kere's where the prompt gets printed, with or without leadift9 -1-

Kel)fH

012700

171130

Bit

t"SCQ.ltO
PIt!NT

: n PE 111 "'£6,sA(;£

MOY

USG',ao

IGET PROMPT MESSAGe AOOR£SS

eLR
MT6'S
eAl.L
eLR

R.UPE

'So reentry Qlves no error 8Sq.
;Al10w 8REAKs to happen
;tYPE T~t PROMPt ALNtAOY
#CL£AR FLAG rOt! "Ell £IlTRr

MOV

000402

GET '1

ADDRESS

11:80$1

012700

1717ll

005067

1770M
OQUOO

106427
OOth1
OO!>061

000620

171022

PRINT:

• Pfl It»
PUTaTIt

aDULG

KXTll-A2 lK rIR~WARE
MACRO V04.00
.ACROODT-GET ODT COMMAND

~·OCr·81

22:56:27 PAGE 33

.stTTL

.acroOOr-Get OOT command

;;;1111;;;1;;;;;;;;;;;;;;1;1';;;;;;;;;;1;1;1111111;1;'111,',

4
;

H;;

nil

19 110112

9
w

20 170136
21 170740
22
23 170744
24 l?onO
25 1707S2
26
27 1107S6
2& 170762
211 170704
30 170170
31 170772
32 170776
:u 171000
34 1HO\)4
3!t 171006
36 171010
n l11Q14
III

;

INTERPRET FIRST CHARACTER or COMMA.O

un
HH

,,;;;I';;;;I;;;;;;;;;;111;1111;;1;11;;;11111',J;;I;111 I;;;;;
;;,1111';"';7;";;;;;',;;1111;;;;;;1;;;111;;11;;;111; I;;':;

\I
'3

10
11
12
13
14
1S
16
1?
111 110726

,;;

,;;';;;I;II;;';;I;;;;;JI;;;I";I;";;;1';;:;11;;;;;;11111;;1

Hote: Following CALL GETCHR, tne cnaracter (1 btt ASCII)
app.ulr5 1n R2.
~ot., following CALL G~JNUM, if carry 1s cleat, tne octal integer
was followed by II carriage return.
Note: On exlt to LCSEr or felllng tnrougn to GO routine, RO contaln.
the adotess typed In.
004761
1211221
001002
000107

000556
000104

CALL
CHI'S

GnChR
R2,,'D

: ••• lNPOt CHAhACTERS
;600TSTRAPiS1

lllie;
.IMP

lIS

;HO

001120

UUOTS

;YES

120227
001002
000161

000130

CMi'D
81i1E
.IMP

R2 •• 'X

rDUGHOSTIC$?
;NO
;YES

120227
001430
120U?
001465
120227
103736
120227

000120

CMPi!
SEO
CNi'1l
BEQ

R2,"P
PCIIIP
H2,.'R
RCJllIi

sPROCEE!)?
liES
;REGISTER"

CliPS
81.0

k2,"O
!(SI)Q

IOCTAL DIGIT?
1110, ERllUR
;VALID 01G11'1

000122
000060
000070

103333

005000
0047.,7
103327

000776

000516

2$,

CMPS
flHIS
CLR
CALL
IICC

2s
DUGNO

k2,"O

HES

UOIl

INO.tRRUl!

1<0

;ITS A 01<01'1'
;CET REST Of THE DIGIT OR CMO
;CR wAS ISSUED,ERROR

GEno".
I<SIJO

The leat character at toe end of the number could be a valid co •• andi.et'a cheClef

40
U

42 171016
U 1711122
. . 171024
4S 171030

120227
001511
120227
OOU2l

OOOO~7

000107

CIIP8
SEQ
CI4PB
SHE

112,"/

,EXAMINE LOCATION?

l.CUl'
112.,'G
11.1100

;NO,ERROII

H£3
IGU fOt

11111-12 II rlAIII'R'

MiCAODot-", DOl COMM'IID
I

2
;t

"
!t
6

1
I
9

10
11
12
U
14
15

11
11
U

M'CRO YO •• OO

5-OCI·I' 22156121 PiGE i .

, tAILE or
'IAI'I
l'l'AtE
,
pro.,t ,
,
,,
, 2- (In,ut d19l tl
'E~.l"l.L'

VALID UPUfS

0-1

t1'56~O

I
I
I
I

,
,
,,
I

I
I

23
2.

211

110.

R
J(

0-'
I
G

'176000/000002

0-7

1200/000021

0"7

7II-

Lr
CM
Lr

CR
0-7
S
I

'IC!tIUOOU24

0 .. 7

'''5/000024 16

0-7

CR
CR

COIIIIE.t

._._••• ) dlG1t.

--_ •••• ) proceed.

-------> register d•• lgn.tor.
-------> execute dlagno.tlc
------->
Doot fro. device
-.-----> another
4191t.

-------) exa.lne loco
-------) go fro. loc n.
------->
Input n•• value.
•• - •••• ) dls,lay next loco
--.----) clo •• loe go to proept.
--.. ----) Input eor. digit ••
.-........ ) .ave data al'Play next.
......... -> .ave data go to proept.
........... ) re91ster nueDer.

------->
,....
-------> ea •• 1n••

-.-...... ) Input new value.
.. _-.-....) Clos. location.
.. ----•• ) eore digit. Input
--.----) .ave value go to proept

KIT11-A2 lK flftMWARt
MACRO V04.00
MACROQot- ~O AHO PKOCttV

~·OCt·~l

22:56:27
,S~T1L

:I
l

PAG~

~.crouvT-

Go and Pr(ceed

;;',;;;1;;;i;;;;;';;;;;;;J::;;;J;;;I:;;;lil;';;J;;I;:; ;;;;;;

;':;;'J;;;"";1;11;#;;;;J';;;;I;;;~1:;;;I;;#;1;;;;;'; ;;;1,;

)
6
7

1;;;
11/;

nil
",.

PkOCESS Gu ANO P~OCEEU 001 CUM~ANOS

;,;~

'i"

:;;';;J;~I'f;1;;;J11;11;111;;J;J1;';;;;II;;;;';~;;";; I;;;;;

10
11 1710)2
12
13
14
1~ 1710)6
16 171040
11
18
19

;;;;;;1;11;;J1;:;;II;;;;;;;I;;;;"#;;;;;;;II;;;;;;;",;;;;11

OlOo"

176714

MOY

RO,SA~PC

;PUT SUPP~LEo PC IN

NE~ORY

~OCArION

Prepare the environment for the Go command
000005
005067

RESET
CLR

176110
Entr~

20
21

; l:IUS lr.1TlAt.I2.E

SAVPS

;(LEAk PSW

poiot for tne Proceed command

f1rat, cheCK for valid stackl

22 1710U
23
2t 1710U
I1to~O

OU6UO

2ft

005740

26 171052
21 1710!l4

OOOHO

28 171056
211 111060
30 171062
11
32

PCMO;
000014

10HOl
00S740
000240
103004

000201

39
40
012600

4:;1 111071:>
43 111100
44 171102

012601
012602
012603
012604

45 111104

46 171106
47
411 171110

49
50 111114

116102

000100

41 171014

000001

011606
005161

176636

Sf! 111140
57 111142

000655
000657

016746
016746
000006

ISufflcient stack,

;

MOV

.I<.STAK1R.NXM,ODT.HY

lIf.!

;Sneakyl (R.TYPE untouched, only tne user 1maqe of it)

1\800

'Error prompt.

Stack 1s OK, 10 restore user's context.

25:

MOV

000340

042716

StaCk no ooOd, so .1mulate a dOuble bus trap without 10s1ng tne
user's context as stored In the ODr stack.

/!IOV

51 171120
52 171122
53 171126
ft4 HUn
5S 171136

-(AD)

7User's staCk pointer
I_nere SAVPS will go (see below)
; (1n case Qf time Qut)
INo good. Timed out.
;where SAVPC w111 gO

1 OR

012605

106427

-(kO)

8CC
~IrH£R

012161

14(S(>1,1I0

TST

IIOP
BCS
TST
NOP

H
3S 1710U
36
31 111072
38

MOV

176622
176614
HII8PQ:

Id,allS:

(SPl+.RIJ
(SPl+,Rl

MOV
MOV
MOV
MOV

(51')+, .. 2
(.$Ph,IU
(SPh.R4

MTPS

JPR17

aIC

UlTO, UP)

(SPl+ ,1<5

;REStORt.
ALL
Of

USER'S
GehERAL
REGISTERS

MOV
COM
MOV
MOV

(SP),SP
IlI.USR
SAVPS,-(SP)
SAVpe,-Cs!')

RT'l'
8R
&R

KBOQ

;No BREAKS allowed until out of
, OOT!
;Odd staCkS are too odd tor T-11
;RESIONE USER SP
;Set uur 1II0de
;RESTORE PC AND PS TO •••
; ••• STACK wliERE RtT WILL LOOK
;RETURN TO USERS PROGRAM
;riELP IN 8ft

I<1l!J$

;tiELi> iN

af<

KXTI1-A2 lK FIRMWARE
MACRO VOt.OO
NACROQOf-REGlSTEk A~D PS COM~ANO

5·0CT-81 22:56127 PAGE 30

• SilT'lL

:I
3

~acro001·R.91ster

and PS command

1;;;;;;111;;1:;;;11;;;1;;11;;11;;;;1111,"';';1;;';,;1'1i1;;

ii;;11;;;;;I;i;I;;;;;lliJl1;;;i;;;;i11J'11;;111iIIJ;I;Iii";

,, ,,

...

PROCESS DDT REGIS1EH COMMA~DS
; ; 1;
Ul1
; ; ; ;
1711
I;;;;;; ":;; II:; "1 ,,;; I,;;;' ;11;; 1111; ;111; ;::11 ;;;;.;" II;;

:;;I;;;;ll;;11~::;:Jl;J;;';li;II;;;"I;';;;;;;;;11;1;1 11;li;

10
: Entry point for RX and RS commands

11
12

13 171144
It 171144
15 17tH2

004761

000200
000420

16 111156
17 l11hO

103240
l:t02~ 7

000123

18 111164

19 171166

001412
120227

20 171112
at 1111'14

001240
02(1027

22 171200

101235
001013
012700

23 171202

24 11121.14
25 1712111
26

052761

tKrLAG,ODTf'LG
ON£;IJUM

CALL
BCC
CMi'II

Ki:lOc;.

R2,.'S
SIICMl.I

000057

CMPII

1'2,.'/

Illi£:

K8Chl

000007

CMP

kO,.7
XIIOQ
I(C"01

BHI
BNL
161752

tSAVPC,kO
REIiOIJT

MwV

OOOtlJ

;SrI REGISTER FLAG
;GET R£GISTER HUMBER
:A VALID CMD DID MOT fOLLOW
itS J.T til£' RS1

;IES,8RANCH
JEXAMlli .. ?

,HO,ERROR

;U:S,ERROR
lIS IT EXACTL~ SEYEN
;YES,GEt PC AOOkESS
; OlSPt.Af

Status register (PS) selected:

28
29 171212

30 171212
11 171216
l2 171:n2
:U 111224
i f 171230
35
36
31
l8
39

Ins
Bi.Q

27
go

176576

RCMDI

171232
171214
171240
171244

004167
120227

000212
000057

SilCMD:
CALI..

CMPS
BillE

Ou1224

v12700
000t03

161154

006300
066100
010061

I1b511>

000402

111>502

II0Y
SR

RCMDl :

ASL
ADD

REGOUT: MOY
5f(

GElChR
R2,"/

;_HAT YOO WANT 10 PO _IIH Mal

I\BOQ

ISAYPS,RIJ

;IIO,ERkuR
fGiT ADOwESS whEkL PS IS

1(1::<.;011 ..

IGO AND DlIiIi'LA¥

;SNIrr fOR OFrsEt Ih MEMURI
;GlT EXACT ADDRESS Uf ~~G.
I STUR£; LOCATION
101SI'LAI

RPUlhl',NO
RO,OD1LuC
LOCOSP

I EXAM IN!!:?

UTH·A2 11\ flRIIioARt;
MACROOOT-EXA.l~E

A~O

MACRO ',104.0(.0
OEPOSlI

5-VC't-81 22;5b:27 PACt: 31
.SBTfL~acroOOT-~xamine

11,;;;;l'i;I';;1:i;:;:;iIJI;;;;;;;;;;;;;11:;;;;;;;;I;;:;;1';
;;11;;;;;;;;1"';;1;;;;;;;;;1;',1;;',11;;;;;;;1;;;;;;;;;IIIJ

4
5

I;;;

7
9

"
W
\D

:.tS 111306
29 171312
)0 171314

31 171320
32 171322
33 171324
34 17133u

;ENTRY fROM CMO ROUTINl AFTER LOC. VALUE IS GIVEN
010067
011000
000240

116474

!.CSEt:
LOCP:;P:

MOV

RO,ODTI..OC

'SAV~

MO~

((o!O).I<U

;Gt.T DATA

tiOI'

103730

OCTSTR
tSPACE,R2
FUTCH"
GEICIlR

,GEf NEXT CHARACTER

l<2,'Ci<

;FINiSI!

nKBO$
R2,j'O

1 DEI'0511' 1

004767
004167

(lu0226

CALL.

000210
000015

CAL!.
CMPa
SEQ
CMP8

120221

000060

103450
120221
H/3307

000070

Mova

81.0

CliPS

005000
oou262

3(> 171332

120221

000012

31 171336
38 111340
19 171344
40
41

001300
105761

1741404

100615

IIEI,CL05& LOCATION
INiJ,Cliii:CK I.E'

R2,. 's

;MUSE:

;ns

SHU;
eLl!

HUCQ

CALL

Gtl'NUM

ace

;Print -1" if we timed out
;PRINT U
;Prlnt a 5pace atter the data

CALL

0(0)72

000040

001716

ISO next Inst. does not execute
l i t "e till!e out.

HKSDO

112702

120221

NEw LUCATION

SCS

004167

004707
10300 ..

CMPS

R2,tI,.F

SNE

TSIS

HKSPO
OOTF!..G

Bill

IiIlBPQ

IHO,~'OkGET

IGLl' HEIST OF hUMSER
ICK fOUND, clORE NEW VALU~
INot CR. mUlt be Lr
;Print error message
tIt LF, cannot be register
;(Error exit)

f-SIT FILTER. The T-~lT can be set tro~ tne keyboard via ODT.
rnis can either De usefu~ tor debu99ing or disastrous. So. you can
do It only it you first let FILl.1 1n a.CNT!.. (SIT 1S).

4l
44
45 17UU
46 111354
41 111356
48 11U62
49 171360
50 11137(1
51
52
53

I;;;

OOILOC points to register or memory location
following CALL GEINU", 1t carry Is clear, CR fOllowed dlolt.
ODTfLG: It register bit set indicates register Is being examined

26 111100
21 171304

AND REGISI~R EXAMINE/DEPOSIT

;1;;;;;;:;';;I':;;;;;;;;I';;;;I;;;~I;:;;;;;:;';:;;I;;; ;;11;;

23 111204
24 11UN
25 171274

MEMORY

HI1
;;;1;1';11;;1;;;';";;;;1,";;1:;;;;;;;'11:;';;;;;;11; I;;;;;

10
11

21 1H2St;
22 171260

It;;

PRUCESS uDt

14
15
10
17 111241>
18 171252
Hi 171254
20

and DeposIt

022767
001021

11>1754

042700

117400
116404

0057111
100402
042100

176372

CliP
8NE
SIC

;28:

."C<l71>,RO

O.er-'fL

axc

lS
fT.I:IIT,f<O

81111

000020

.SAVPS,vDTLOC
1$

IAre we diddlIng tne PS?
w."re not.
IPS 11 not a word.
lIs SIr 15 (FIL1.1) SEt?
;Yes, tne f11ter'$ d1sabled
: KlLL TIiE T-8lT
,100,

Ifa11 tnru to Prior1ty 1
; 'Hter

,,,,c;.,,.~

IIACRO Y04.00
&1111-.2 1& FIRMIIARE
IIlCIOODI-I'l"INI AND DE.0.l1
1
2

14 11141(/

15 111412
16

11 nU)4

18 111440
19 111442
20 11U46
2a 11a450
22 171454
21 nU60
:1.4 111466
2S 111412
26 111416
21 111102
28 l1n06

22156127 ••, ' i8

,'rlorlty·7 flltara unlaSI FILt.7 (lIT 7) In O.CNfL Is set, you cannot
,actually set tne P5 to priority 1 uilno Out froe tne keyDoard. Thll
Iprotects tne ebility to breek.

4
5 17U14
6 111400
1 111402
• nU04
, 111406
&011U12
11 111414
12 111420
U 171424

5-0Ct·~1

105167
100401
105700
100005
012100
001402
Otal00
010011
12.0227
00a401
00064)
120221
GGUU

105161
100U4
un02

0041.,
062167
016700
004167
112702
00.,67
000661

116112

2'1

fSfI
8111
Uti

000040
116122
000012

.1.

000012

ePL

"g
IIC

MOY
C"PI
III
8R

CMPI
INt:

.,-.:rl

l1UU2

1111

OOOOHI

000042
000002
'16254

000160
000051
000014

5"
116260

kO
U

lli

00"100

O.CtltL

IIOV8
CALL
ADD
1II0V
CALL
MOV8
CALL
8R

IBlf6,1I0

III15,RO
1I0"OorLoC

102,.'
,,' "
111180.

R2,1L'
"KaPG
OOTF"G
hit BOO
'(A,k2

PUfChll
U,OOILOC
OOfLOC.RO
,",CTItk
,·1,112

purclIJ(

LOCPS'

loot contrOl word
nothing-filter dlsablaa
IInteneled ne. l'S
,00 notnlng-Prlorlty < 4
,Cneck eOeln
10o nothinO-Prlorlty < •
ILOIloEIl IHE 100111
,stOIit. tiE. VALUE
IGO on to na.t loeetlon?
,sure, wny not.
,GO to .ROllPT

100

'IS A LF nlllEO
INO,ERROR
'15 R~Gl'''Ek FLAG SET
IYES, LF Not PElillIltED
,TO "INE UP CUMSOR

U""OADDRESS
I'l
0' IIEXf LUC.

'G~I

,GEt NEXT ADDMESS VALU~ •••
; ••• AND PICUlt Ir
,S~ND A aLASH IErOkE •••
I ••• S"O~IIIG tHE CO~tiNTS •••
J ••• OY TH~ LOCATION

KXT11-A2 lK FIRMwARE
KACRO V04.00
MAC~OODT-GET _NO ECHO CHA"ACT~R
1
2
3

.S8TTL

6
7
11

I;;:

;11;

1;;;;;I"';I;;111/1;;;:;I';:',;;;1";;;;';;',JIII:IIII;;/1;1
';1;;:;;1:;;;1;;"';;11"",';;;;;1;1',11;;:;;;:;;;1;11;;"1

10
11
12
13

Get a character trom the console keyboard and eChO it back
exactly as received 1nClud1ng parity o1ts If any. Return with
character 1n RZ, elQhtn olt <end n1gh byte) zero.
171510
171510
171514
nUll>

G£:fCtlIO

105737
100315
11)102

t 77560

105737
100375
110231
042102

17750.6

22 111530
23 171534
24 171540

rSTS

UnUf$1,R2

ISPL
!lOVI:!

UXCSR$1
PUTCIlR
RZ, tit j(i,UF$1

lPRINTU RElOY
;110, ru AGAIN
;YES, XIIIT CHARACTER

SIC

'-C<177>,R2

MOva

1175(>2

llIRCSUl
IoETCI1R

CHARACTER RUllI?
BRANCH IF ~uT ANO KEEP TRlIHG
TRANSFLR CHARACtER

8Pt.

111522

171522
21 11152&

macroUU1·Cet and eChO character

;;1;;1;;';;;11"';;:11;11;;11;;;;;;;1';;,1111;;;;;;;;,1;1;;;
;1;11;;;';;;;;;;1;',;;';;';1;1;;;1111,;1;;;1;;;;;1111;;;;1;;
11/1
;;11
1/11
CHARACTER IHPUT AND ECHO SU8ROUTINl
1/11

14
15
16
17
111
19
20

5-0CT.Wl 22:50:27 PAGt 39

PUl'CI'IlU

000207

177566
1776(;0

TSiTB

RETURN

;CLoUR PARI'll

;CONTINUE

~xrl1·A2

lK fIRMWARE

MACKO VOt.OO

s-OCr-Sl l2156:27 PAGE 40

MACRQCOt-TrPE ASCII STRING
.sarTL

1
2

;;;:JI;;;;;"",,',;;,;',t;;I;;;';;,;;::;;IJ#;;;;I,t;,111111
;;;111;111"';;1",,';;;;;111;;;;;;1;;';11;;;;;;;;;1,;1;;;;;
1111
nil

J
4
5
6
1
8
9
10
11

",;

:.11
:t;;

111;S;;1111111111';;;;;II;;;11111;,;ll;;;;;;;;;;;;"11Ill;;;
Pr1nt .essage starting with character pointed to by RO and
endlnq with first character with elqhth bit set (thll cnaracter
15 not printed).

16 171542

17 111544
U 1'11546
19 1715~2
:10

PUTSTIH
112002
100413
004167
001/713

MOV8
b"l

CAI..L

177150

81<

{I<OH.R2

IJO"e:

POrClill
PUUTI<

;GEl' ASCII CHAR
;15 IT THE END MARK?
utO, PRINT IT

,IIOR£

;EHTRY rOR CARRIAGE RETua"

PkINT SuaROUTINE

:1""',;;1;;;11;:1;;;;;;;;1:;;111;;;";111111;11;;17' I;;"~;

14
15 111542

'9
.I;:.

"E5SA~~

11:1

12
103

22
:U
24
:IS
26
27
211
29
30

lIIaCrOOI)T"1:vpe A5CH string

171554
17155.
171560

PUTCLf:
112702
004761

000015
117736

MOYS

CALL

'CIt,R2
PUTCHR

;PRIIiT eR
;fAI..L TlikU A~O PklNT Lf

'Lf,R2
PUTCHR

TPk!"T LF

IUlUr tOR I..f
111564
111570

31 171574

112702
004707
000207

000012
177726

PUTLf:

o.Ol'l£:

IIova
CALL
RETURN

KXf11-A2

FIRMWARE

MACRO V04.00

MACROODT-GET OCTAL DIGITS
1
:2
1

PAGE 41

•• croODt"Get octal di9lts

;;',1"";11"""";;;";111;1111;1",',';;;1;11:";;,',::1
"";"',11,",111"",111111;;;";1;1;;;;;;;;;;;;1;;;";';1

It;;
IHt

lIn

1
8
9

11
12
13
14
15
16 171!i7&
11 171516
111 111600
19 17160\1

20 171604
21 171610
22 171612

23 171612
24 171616
25 i71622
26 11H>24

21 171626
28 171630
29 ~71612

30 171634
33 171UO

36 171646
31 171obO

OIlI:.NUIU

005000
004167
120221
001412

171704
000011>

162702
062702
103007
006100
006300
006300
0502vO
000761

000070

flO

;CLEAR ACCUMULATOR

CALL

GUCHR

C/!IfS

il2,teR

8£Q

,sRt:T

;GET DIGIT OR TERM1NATOR
;CLEAH CARNY AND RETURN
;IF <CII> wAS T1PEO

Gt:TNUIU

sua
ADD

000010

BtC

AS"
AS!,.

000241
0002(,17
062702
000261
000207

CLk

HUIIUII:

SREU

14
35 171642

;1;;

On exit. RO contelna the binary representation ot the numoer entered
It the carry olt 1s clear, a <CII> tollowed number
If tne carry bit 1$ iet, some other character followed the nU.ber,
pOSSibly a command.

32 171616

11:1

NUIIERIC INPUT ROUTINE

11;:"""";;;:"11111;;;111;;;;;111",;",;;;;,',1;;""II
;;;;;1;;";1',;;;1;';;1"11;;11;;;;;;111;;;;;;;11;;;;'1111;;

~2:56127

.&8TTL

S-OCT-81

000060

HOC'!::

.'8,R2

.'8-'O,R2

/joeT

Ilu
RO
RO

AliL
BIb

1'.2,110

N£XI!IIIM

CLC
IIETURN
ADO

SEC
rtETURt.

;CONVERT TO bINARY •••
I ••• AND TKST IF OCtAL OR NOT
;NUT VA~IO DIGIT.
;MAKE ROOM FOR NE~ OlGI!
;DITTO
;DUTO
; PUT IT IN PLACE
;lOU NEXT

;CLEAR CARRY
;CONUNIIE
.'0,112

;IIESTORE ASCII BECAUSE •••
: ••• P05S10L£ COMMAND
;CONTlNU£

·'
KIIII-A2 IK IlkMWARE

MACRO Y04.00 ~-OCt·81 22156127 PA~E 42
IN kO .a AaCII

"AC.OO~f-OCI'I.--IYPE .1~AkY

.68111.

2
3

""""""""""""""""""""""""""""""
""""""""""""""""""""""""""" "",,

4
5

""
; "'

;

; 'r1nt., e. a '-dI91t oc~al tnteger, tne velua of tne binary
, nu ...er 1n flO.

11
12

~.
~

14 171652
15 171U6
16 1716!i6
1'1 171660
18 171664
19 17166'
20 171670
21 171672
22 17167.
aJ 111702
24 171704
25 111706
26 171710
27 171712
,21 171714
:at n1716
30 171120
31 171722
32 17172.
31 lh726

""
,,, ,
""

NUIIER1C OUtput ROUTINE

""""""""""""""""""""""""""""""
;",,"""""""""""""""""""""""",",,"

9
10
U

.acroODt-OCtSIR--ty,e blnery 1n RU e. A8ClI

0047.,
010046
012746
005002
006100
00'102
062702
00.767
005)1'
001406
005002
0061011
006102
006100
006lil2
000762
005726
012600
000207

177676

actnOr CALL
OCratR.
MOY

0001106
5U

00006U
117.20

MOV
C&.R
ROL
ROL
ADD
CAL ..
DEC
BEG
CLR
ROL
ROL
aOL
aOL
811

lOU

tat
!lOY
UtURN

PUTCLr

,NEED CRLI AT DDT ENtRY

RO,-(6P)
",-(SP)
R2
RO
R2
.·0,fc2
PUtCHk

,SAVE VALUt;
,NO. or CHARACtERa
,OUTPUT HOLD
,aHlfT Ma8 INfO LaB

(SP)

101
a2
RO
R2
RO
K2

&.(ap)+
(6P)+,RO

,.........

,MAKE A DIGIT
,OUTPut A CHARActER
,COUNt
,DONE
'NExt
,GET' NEX'!' DIGI! INtO
,R2
'fIRat tWO 81'1'S

,-,CONTINUE
. • •• • •
,CLEAR COUIit

,,ORIGlI.AL VALUE

KXtl1-A2 lk FIRMWARE
MACRO YO •• ao
MACROODt-OufPur Mt$$AGES

s-oct-as 22tS6127 PAGE 41
.S8TTL

t
2

~.erOODT*Output

.851.9.5

1"",1,',1";""""",,,,',',;1;;;;",1,",',"',11;;;SI1
;',"",1111;;;,,':1111;1',1"'1,"";',"",111,';1;11;111;

IIH

1111
;;n
;1',',;;1',II;;;II""""';;11'7"",,IJ1,,',11""';"""

IIH

MESSAGES

1111

;;;'III',;',;';111"";"'I:I';;1;;;";IJ;;II#:JIIII', "~,;;,

10
11
12 171130
1l 171H1
14

071
015

" ,

012

100

.NLIS!

BEX

IISGQl

.ASCII

"1"

liS":

.AaCII . CCR>cLf)",'c200)
.KV£H
.LIST
aEX

ERROl! 14t:SSAGE
PROMPT

•

lXT11-A2 11 FIR.WARi
MACRO YO •• OO
OIAO.OSTICS-FOR SLU2 A_D PPI

5-0CT-'1 22156.27 PAGi 4.
.saTtL DIAGNOSTICS-for SLU2 and PPI

"""""""",""",""""""""""""""" """
""""""""""""""""""""""""""""""

4
!I
6

'"'
""

'"'
I'"
""
""
""""""""""""""""""""""""""""""
""""""",,""","""",,""",""",""",
"""

,
1
9

10
11

Diaenol. PPI In aode 0 with 100pback connector. lnlta11ed.
Diagno.e SLU2 Inte~na1 circuitry 'aalntenance .ode) and
aLu2 drlver./recalverl (with axternal 100pback connectOr).

12
13
14

Lilt of error bit def1nlt10nl to return to u.er.

1!1
16

17 171736
18 1717.0
19 171742

000100
000010

ERReIT.

20
21
23

CI\

000000
000002
000006

lNl'U,

377

252

000

36
31 111754
31 171'15.
39 171762

0127J7
012737

000221
000011

17UO.
1'6200

42 171'170

005000

.041
u

E.EIT
E.IIIIT

.WIJRO
.WORD
.WORD

XC.PBE
XC.i'Bl 1 XC.MN'1'

100 baud
300 baud and .alntenance

Lilt of pattern Dyte. to loop around.
All b1t. on, alternating bit., all b1t. off.
lIIote, la.t byte aUlt be U.

211
30

32
II 171750
34

.WORD
.WORD

Lilt of .alk. to put In ICSR'2. Perfora Internal loopback
telt tlrlt, then external loopback telt.

2. 171142
25 171144
26 17174.
27 1717liO
28

DIAGNOSTIC MODULE

PATERN: .BYTE
.1Y!::N
OUGNO.

377, 252, 0

.ENAaL

LSB

MOY
"OY

.MODi, •• PP.CwR
.LEDO.. r, .... p.CWR

let proper 'PI .Ode- LEO
.u.t 1 •• ed1ete1y be turned
otf al a con.equence.

CLR

a.lu.e lucce.1

PerforM parallel port dlagnoltlc

44
45

•• 171n2

., lh77.

005001
000.05

CLR

Rl
ARQUN2

R1 • looP pet tern
611P OYER THE ENTRY POINT

...

...
:II.

....'"
0

101

1ft

'"c
0•
'":c

101

......

..'"... ......'".

...t

::0

•

"" '"

<:)

......
•
" ""., .. .,
..... ...

.
-...
....•

1ft

COt
N

'It

IIC
C

llO:

•

'"to

1ft

1£

;.0

"
IIC
U

If:

.....
... Z

....,.
.. 0
C""

. .
.. ..
Il1o
lit

tal ...

...
... ...'"
... ...
... •
.........
0

::0

::>
0

C'\I

0
0
0

GO:

......."'.

.. W

1'0101

• c

00 • •
000:>0
0000

,... ..... ,....,.....

rtNftN

.............

.... r."' .. .., .......

... 0
fo.

:111::1:

1)..47

_Xtll-Aa lK rllAWARE

DIA.'06tIC'·C'IITl.~ID

IIACIO V04.00

~-OCt·ll

22.5 •• 27 'AGE 4.

2 "2010
1 172010
4 172014
5 172020
• 1741022
7 172026

•

UOU7
12)101
001402
052700
077110

AIOUN2:
lU
\110'1

176202
176200

ellPl
lEO

000001
2U

""'

2. 172104
27 172110
21 172112
2!1 172114
10 17211.
11 172120
12
II 172122
34 172126
)5 172110
36 172U2
31 172U4
31 172136
n 172140
40 17214.

11. ,,'P.I
''''.A. R1
2.
fE.'AR. RO
Rl, II

I •• nd It out port 8
, ch.cklnput In port A
, br.nch If ••••
I .1.. ,.t .rror fl.o
I loop for '11 v.lu ••

'erfor. 'LU 2 dl.onoltlc

10
11 172010
12 112034
13 172040
14 1720 ..
15 172050
16 112054
17 l1aO!f16
11 172060
19 172064
20 112070
21 172072
22 17207.
21 172100
24 172102

11&
aue

.'ltIL DIAGIIOatlCa-Contlnu.d

012702
012701
016146
01270C
0144U
001U6
005142
01271.
01270)
005005
105161
100402
077504
000422

171742
176540
000002
171750
000004

111361
005005
105711
100402
07750)
000411

000006

126113
001010
10572)
001156
005316
001744
Ot.2761
00014b

000002

III

HS •••

,
,
,

101

ItOVB
CLR
taTI

(Rl), b(Rt)
H5
(111)

lnltl.llz. tlaeout count.r

8111

110'

1I0V

81:0

000010
171750

4U
5u
6u

000004

Tat
ItOY
IIOV
CLK
TIT8
1111
SOB

8R
7 ..
lu

4(R1)

R5, II
10,

, br.nCh If re.dy
, .1.e DU.p tl.eout count.r
I br.nch If tl.eout

CIt'8

2eRl), (Rl)
10$

, co.. back OK?
I no, .et error bit ~ eXit
I done .11 bit p.tterna'
no
, yel, done .11 baudl'
, yea
, no, to n.xt baud rate

tUB
BilE
DEC
BEQ
ADD
8R

000004

liNn., H4
·(RU, 4UtU
111
-(12)
.... (5P)
"ATERII, Hl

,
,
,
,
,
,
,
,
,

BIlE

000010

.RC.RI2, IU
4I(lIU, -(IP)

SOB
9t:

.ERRen, R2

R2->lrror fl.O'
Rl -> .LU2
10nore garba,e, .at. t •• p
R4->lnltl.1 XC.R v.lu.
lnlt XC.R
branch if done
R2->n.xt .rror flat
(I')-b.ud rat. count.r
Rl->p.tternl
Inlt tl ••out count.r
looP p.tt.rn .round
br.ncn It re.dy
elle bu.p tl.eout count.r
branCh If tl.eout

110'
1I0V
ItOV

(R)h

51
(S,)

3e
no, 4(k1)
.e

42 172150
U 172152
.. 172154
4!> 172160
46

051200
005726
004767
000167

177472
176516

IOU
lU:

815

TST
CALL.
JMP
• os AIL.

(R2),HO
(5P)+
OCTSTO
kBD •
L5B

1 aet error bit
, rid of teap
1 pr1nt error fl.,.
, .nd ju.t get out.

KXTll-A2 lK flRMwARt
600TS~D£SCRIPTION

MACRO vo,.OO

5-0CT-81 2l:St>:21 PAG~ 41

1
2

.SSTTL aOOTS-Descr1ption

1111::;';';1;;;',1;111":;;;;;/;:;;1;1;;111111';;;;;;;I';';;
1111;;;11;;;;;;11;;;';;;Jl1;;11;11171;;;';;;111;;;;;;;1,';1;

4
5

6
7
8
9
10
11
12

10$
14
15
11>

18
19
20
21

22
23

y
.f.>.
\l:I

;;1;

BUOTSTRAP MODULE

I;;;

;III
1111

7;;;

;";lii1;I';;;I;;;;:11111;;I';,;;;;;;;;;;11i;;;I;;;",;;1111
;1;Jlll;;;;';;";;;;;";;;;;;,,,;,,,,;;;;;;,,;;;;;;;;;;;1;;;
000000

.IIEPT

This is i Short bootstrap program de,19ned to handle flOPPY disk, or TUSe
tape cas,ettea in eithel our standard bootable formlt or in the stand.alone
volume format (IIT-11 -.SAV--structured tilesi,
The bootstrap sequence 1s a. follows:
1.

Since entry is effected by typing P 1n response to ODT prompt, get next
charaCter (D, X or ll. Get optional device number next (default 1s 0).

If floPpy boot 15 selected:

.l4
2!)
26
27
28

Attempt to read 514 bytes from specified unit et the floppy
disk, starting trem logical blOCK zero, into memory locations
startlny at Q at the denSIty of the mediue present in tne
drive at the tlee.

If tne drive 1s not ready or does not conta1n a bootable
medium, gO uaCK to OPT.

3Q
31

.n
3J
.14
35

It>
37
38
39

It 1U5$ boot 1$ selected, read the firat block from the selected
arive lnto locations Itartln9 at Q •

If the first byte relo into RAM 18 240 octal. jump to It. If tne
tlrst byte 15 2bO octal, execute toe 'tand-alone volume loader,
uaSng tne selected device as input.
.ENOI<

axt11·.' lK FIRM.A~E
80ota·O!aCRIPtlOH
1
2
3
4
5

24
211
26
21
28

'930

III/

;'"

.SSTTL 800TS-RX Controller Detinitions
I aXOl/III02 (RXY11.RXV21)

177110

Rxes"

177112

RXDS-

100000
040000
030000
004000
00)000
000400
000200
000100
000040
000020
000016
000001

HIIUER:

117170
RXCIH2

100000

allUI"" 040000
RXUU= 0)00(1(1
IIXUII2-

0040(10

RUnX'" 001000
kll8${Jl;- 000400
IlXUfk: 000200
RXUU:: 000100

aXUD,;'" 000040
UnUM: (10(10:.10

kXlU·,," 000016
RX ..
000001

'O-

000001

RX$fI~.

OUII003
000005
000001
000011
000013

RX$£M~= J'2+RX$$GO
RX$~RT: 2*~~RX$'GO

000015
000017

0*2+Rl.8,0

RXIREU- )*2.RI.IGO
RX$STD- 4*2~RX"'O
RX.RST- 5'2~RXS'GO
RXa.OO: .'2+I<XI$GO
RX'k~C= 7'2+RX'$GO

000400
000200

RXUUN= 000401.1

000100

RXUDO- 000100

000040
000020

RxnDE- 000020

SO
51
52
53
54
55

56
57

JError
;Initlallze controller
;Extended addres5 bits
:t it RX02, 0 If AXOi
:Unultd blU
,Denaity (l=double,O=slngle)
;Transter function
11nterrupt enable
;Done
;Unlt select
HuncUon select
1GO

I f i l l buUer
H;mpty buffer
tllrite .ector
;R •• d aect.or
;Set aed1a density
,Read statu,
,write Sector with deletad data
,I<e.d error COGe

, RX Error Codes

46
49

;eontrol and Statu,
IUatli Buffer

1 Rl Function Cooes (in AXISFII) with GO bit pre.et

Regilter Definttions

1 Rl Control and Status alts

36
3?
38
39
40
41
U
U
44
45

f";

1',i;;;1;:;;"';;;;11;11':;;;I',;111111"';;""",',1 I ; ; ' ; :

EQUATES OSlO ONLY BY BOOTSTKAPS

;""';;:;::;:;";'1111';';;;';;;";';;I"'1;J:'I;:~;;"":1

U
16

1111

;171

;1';

21
22

22:5bs27 PAGE 4ij

;11;';;111;1"';;;""""""""';";1',"';"'1111111,'"

1
8
9
10
11

17
18
19

5~OCT·81

",';';;"11;;IJ";I;;I;'J/II;;';;I:;;";,,,,11',;I";",1;;

1J
14

kACRO V04.00

000004
000001

UUUR" OOOlOO

RXUOlla 000040
RXUIO- 000004

RUICR" 000001

,Unit se1ecud

;Drive ready
H)eleted <lata
;Drlve aen'ity
~O.nslty error

Iln1t1allr.e <1one

,CRC error

; M1.ce11aneous Definitions
000010

RtfRY"

,Nu_ber of retries

.58Tf1 ~OOT$-TU58 Definitions and ProtoCol Equate.

Klftl-A2 lK FIR~.ARE
~ACRO VOt.OO
S·OCr-81 22:56t21 PAGE 48-1
aOOTa-rUS8 OtrlhITION5 ANO PROTOCOL EQUATts

1 Absolute address aeflnltlons

58
59

60
61
62
03
64
6!>
66
H
68

09
10
71

000002
001000

176540
176542
176544
110546

DIRBUr

TUCSR

nuu

TO.CiR
TOU,./(

81
82'

000020
000023

0000112
000004

U
84
85

MUDU
RUCTL
RUIhT

RUCOH
RUlor

RUUU
UliRIT

90
91

000004

RsCOMP

000005

iI$POlliJ.

000006
000007
000010

II.DlAG

94
95

96
97
98
U
100
101
102
103
104

lOS
lOb
101
108

109
110
111

112
Hi

114

.. l!.8Uf'52

;ot reeelver control and status

;OL recelver data buffer
;OL transaltter control and status
IOL trans.ltter data buft.r

.. "1:\<00001>
.. "8<00010>
.. '"8<00100>
.. "8<10000>
.. "8<10011>

,Data message fla9
,Control .es.age flag
;1nl t.taUze flail
1Cont.tnue flag

;xon

Control paCKet operation COdes:
000000
000001
000002
OOCWOl

.. RCSU2
,. RSUU2
.. lICSIU:i

flao 8yte Oeflnltlons,
000001

'" 001000

TU58 Radlal Serlal Protocol COdes

76
77
78
79
80

86
17

,AddreS5 of RA050 fl1ena •• for
st4nd·elone progra. 10ad1n9
;Start of 512. word buffer used
I tor RI-li dlrectory operationa
I
1n stand-alone loadlng

TUS8 Address def1nlt1on.

,. 000002

72
H
'14

rILHAI'!

000011
OOO() 12

RUGI'
RUllI:!'

RUaU

.. O.

.. 1.
.. 2.
II

.. 4.
" 5.
,. 6.
.. 1.

Il$G£'Ui
USETS

'" II.

R'GtTC

000013

RUETC

.. 10.
.. 11.

00010(1

RUNO

.. -8<010000110>

;No-operation
#In1t1al1ze
:Read operatton
; wtite operaUon
ICo_pare (NOP on TU58)
IPosltion operation
;Abort (NOP on TUSS)
1Diagnose
;Get status
;Set statu. (HOP on TUS8)
;Get cnaracterlstlcl
1Set cn.ractefistlcs (MOP on TUS')
I*EIID ",essage

; tHO packet succe55 cooe.:
000000
000001
177716
177710
111167
177765
177751
111740
177737
177120

117711

SUOR"

.. O.
1.
"'2.

=
SaPARt
stkET!<

sauu T
SICART
sawpllt

:: .. a.

.. -9.
-11.

UDCHK

.. -17.

S$MO'U
"$OPCO

" -33.
" -411.
" -55.

sunK
SSHECN

= -32.

fllofllla1 success
,Success but wltn retries
;partlal operation (end ot aedluM)
;Invalld unit nUMber
;lio cartrl-doe
ICartrld;e wrlta protectad
;Oata Check error
ISaek error (block not found)
;Motor stopped
;lnvalid operation code
;lnyall0 record number

.8BfTL BOOTS-RIll Oetinitlons and Equates

'If

I1111-A2 11 rl.MWARE
MACRO V04.00
100'.-R'11 oer,.",oNS AND EQUATES
H5
116
117

120
121
1:22
12l
124
125

l:iI6

127

128
12'
UO
131
U2
U)
U4
U5
U6.
U7'
U8
U'
140
141
142

~-OCT.'l

001000
001002
001004
001006
001010

221$6127 PA'E 48-2

ItT-l1 Directory Structure Definition.

aE:GALO

• DIIIIUr

II..HIE'
lTitaU

.nll:' • DIR8ur.2
5TR8I."

• Dlk811h4
• UIIlIU.·.6
• DIReUhl0

000016
oaOCilO
000400
0010110
002000
00.000

... Utz
D.'L':"

• '.:1

000040

'UI'fA

• 000040

.tltllT

• 000052
• 000053
• 000054
• 000056
• 000057

10
n.TAs •• 000400

a;/I'TU • 001000
'UClaGs
ERM,. •• ,004000
0020011
I

OOOOta

000044
000046
000010
000052
OOOoiU

000054
000056
000057

,Nueber Of .eQaeni. allocated
,Nuaber Of next loolcal .eo.ent
,lIlohe.t .eoaent 1~ u.e
l!iuaber Of extra byte. per entry
,Startlna block. for file.
, In thl. .eoaent
I&Ue Of a directory antry
,Otf •• t to fila 'anoth In antrY
IFleo for tentative file antry
IFlaa for .apty eree entry
'~lao for par.enent file
,flea for end of leoaent

itT-II Syltea Coa.unlcatlonl Aree Definition.

11'
11" •• 000042
U8JIII
0000 ....
• 000046
"nB'
RUII'" • 0000$0

" .....
.'.IIER

RTlrCH
IItarCt

,Start addre •• for 'pro ora.
'Initial .teck pointer
;..JOb .tatlll word
,USR load addra.1
IJob hlan aaeory 11alt
,(dyt.) Ell' error code
,(8yta) U.ar error COde
;8••••ddr ••• of re.ldent aonltor
,t8yte) Con.ola fill cn.recter
,(8yte) Con. ole fill count

11'11-A2 11 FIRN_ARI
NiCRO Y04.00
lOOf,-.ROGRAN 'NrRr .0INT

I-ocr-'1 ~215.127 PAGi 49

1
2
1

.'ITTL 100r'-'rogr.. .ntry pOint

,""","""""""""""""""""""""",, """
"",,""""""""""""""""""""""""
"""
,,,,
""

5
6
1

IlUor5TRA. INITIALIZATION ANOCOMMANO INTERPRirER

""
'"'
""""""""""""""""""""""""""""""

•

"",""",""""""""""""""""""""" """

'0
11

, A "D· WI • •nter.d In re.pon.e to the aDr pro.pt,
we oet
, her. Ind •• peet "P','X" or or' n •• t, fOllow.d by I CR or a
, unit nu.ber. • • • et bit. UP In B.CHTL I. tollow.:

,,
,,
,
;

11
16
17
11
19
20
21

;

BIt

U.ed by .tlnd-Ilone volue. 10lder to .elect proper
reid routln ••
01 Device nUliber

0 • IUsa

1 •

ItllOl/0~

It no .e.ory wa. found It 000000, bit 15 of B.CHIL,
e.lled -NO.LO.- will be .et Ind the boot.trlps will be
dl.abled.

~ote;

,
,

25 172164
U 172164
21

9v.

1.,0.1

012737

00007a

1765. .

10016"

MOV

ITUbAUO,,,TOfC5R

,aet IUS8 Baud Rite

2.29

, Ju.p her. with ODI If booting TU58'1 It other than detault blud rete

30 'H172

snUbO;:

11 l'Ul12
12
U 11211.
l4 112200
.f$ '7U04
J6 112;llCl

11 172212
It 172216

39 11:;12:.2
40 172:;124
41 172230
42 172lJa

010667
001004
004767
1202a7
0014141
U2704
020227
00140S
020221
001402

175566

JlOY

,p,lIt.uaR

CLR
CALL
CIIIP8
BEQ

177304

IIOY

.DEvaU,li4

000104
000200
OOOUO

CII'
BEu
CMP

000131

llEQ

GEI(HII
R2,,"r,
11

R2,.·X
11
R2,.·~

ABORt

<111eoal device ne.e>

CALL
CliP

GUCHK

;Perelt HALT. Ind BREAka
; by .ekino IN.U6R non-&ero
'A •••• ole ne. 1l.(NfL here
,KeyOo.rd ch.rleter In R2
,DO • IUS8 ca •• ette
,Rt 1. clelr for DO
,Rt bit 7 1 • • et tor OX, at
'OX • kXOl or RX02
,01 • RXUl or RXU2, the COde".
, the •••• - it knOWI Doth denSities, DNA, non-DMA

. . 112236
45 172242
46 17224.
n 172210
U 172254
49 1722SfI
50 1724'60
51 172262
52
53 17226.
54 172270
n 171274
It 172~00
57

004767
022702
001410
11>2702
001405
0115302
001402

1772 ••

000015

BEQ
6U.

000060

liEU
DEC

BEQ

ABORT
005204
110467

17U74

005767
100002

17U10

2U
36:

INC

MUYB
U1'

b.L

,Get aevice nueber or CR

; II It CII?

115, .. 2
3.
"11,1<41

112 2.
<Ille9.~

..
R4

Ii4 ,1.ChlL

II.CIIITL

unit nu.ber>

ICR •• ens drive 0
,Drive 01
Hup.
,Drlv. 17
,le., ,kip the AIlOkT

,For unit 1.
,set dev1ce, unit lnfor •• tlon.
,'eat NO. LOW
,~e hive low .e.ory
,.e don"t, 10 go to UDt

•

aXIII-A2 lK FIRMwARE
MAcao Y04.~0 s-ocr-e, 22156127 PAGE 49-1
•••••, ~AL7 AT PC-ll2264 JAOICATE6 ·l~L&GA~ u~lt NUM.E.58 '72302

ABORT

'CNO low ....ory, can' t boot>

, Befor. ,roc ••dln9, •••• t up the bu. tl.eout tra, v.ctor, .naDl.
tr.p to 4 •• ul.tion .no r ••• t the bu.. •• do a d.l'y (.e.
.xPlanatlon •• low> and .et up tn• • t.Ck .0 the It.nd-alon. boot.r ano
, devlc. prl.ary boot.trap. can ,ot tho Intor.atlon th.y need pa •• od
, to tna. In RO and Rl ( •• 0 C"K240, b.lo.).

..
61

I
I

62
61

65
6. 1721116
67 172314
61 172.J22

012737

OI2Ul
000005

172370
000300

00000.
0011006

4 ..

NOV
MOY

..ADBOT, ...
,PIU6,ttt»

RESET

:JO
71

Noto, tn. proviou. In.tructlon al.o .cr••• up .0 •• doylco.
whiCh p.tfor. a lon, Initialization ••quonca, .uch a. aX~2·.,
wnlcn do an auto.atlc boot tro. drlv. O. Tne loft, d.lay below
1. n.c •••• ry In ord.r to a •• uro drlv. 1 I. ready if a boot
1. de.lr •• tro. It.

'776 17212.
172UI

"
v.
~

DlLoAl
MOV
1I0V

aO,IU,9.

175UO

012716

on776

IIOY

U1716,(SP)

010402
042702
0102. .

177776

MUV
BIC

R4,R2
,·CCDUNUII>,n
n,·(ap)

012706
010'"

eo U23 . .

81
82 112152
U 112354
e4 1723"

",.

71 172U2

,If •• tl •• out, wo •• nt to reIlnltl.llz. ev.rythln,.
,For now, Inlt. tno bu ••

MOY

."UCK,SP
SP,tRAP.4

,Delay 2 .acond.
,Inltl.1iz. the ataCk.
,S.t up trap-to-4 •• ulatlon
,by .aKln, 'fRAP. non·zero
,ao•• boot. n••d a ••• ory-top
; addr ••• n.r., .0 Ik will do
Iloot eontrol word hete
;want only unit no. In H2
,And .0"11 •• y. It too.

85
86 112362
87 172364

100405

105704

Uti

. . 172166

000U6

BRI
BR

'fUBOOl

MOY
AlORt

"'TACI,SP
,Ro.tor. the .tack
<Unoapoeted tl.,out during boot>

90 172370
91 112170
92 112374

012706

167644

aADIOTI

kl800t

'Bit 1 •• t for RIOl/02
;Go to floPPY boot
,Go to 'fU58 boot

KXT11~12 lK fIRMWAR!

MACRO V04.00
BOOTS-RXOI/RI02 BOOTStRAP

S-OCT-81 22:56:27 PAGt 50

.BBTtL BOOTS~HXOI/RX02 Boot.trap

2
j

""';""""';';';1";';';;';;;;;;""";;"';;1;';;;1,,;;

-4
S

';;;';;;;;;1"1;",;;;,;;,;;;;;;;,;1;;;;';;1;;;;',;;,;",;;;

Ill;

8
9
10

1111";1","':1;;""111,';;1;;1";;;;';1;;;;;11,"',1";:1
"""';;"',1111;1111/111;;;;;11111;;;;;1,11;;;;;;;1;:;1;"

Vl
Vl

;;;1

fLOPPY ~OOTSTRAP

I;;,
1111

"~;;

l1n

Thts rout1ne w111 cootstrap etther floppy drive. at the density of the
.edt. Mounted in that dr~ve.

12
13
14 112400
15 112400
16 172404
17 172410

000240

18 172412

012101

19 172416
20 1724<10

OO~OOO .

005(1114

21 113412

004107

0121'"
005717

RXllOOt:
117110
177110
001000

000402

MOY
TST

UlIC6, -UP)
UHlIt:>

,"OP

MOV
Ct.!!

CLI!
CALL

,512.,111
110

114
OREAl)

;Need floppy CSR tor CHK~40
tl~e out via 4
Ito Stl1l _no reset the worlu
;6yte count
;Starting blOCK nueber
11f not there,

IMA~ bufter addre.s ~ 000000
;1.0AD IT ALL IN

_XT11-Ai lK FIRMWARE
aOOTS.U13TI~QUlaHI.G

MACRQ V04.00 5-0CT-Ul 22:56!27 PAGE 51
or aOOT bLOCK

ttP~

.$bTtL aOOTS-Ol&tlnqulshlnQ type of boot blOCk

1
2

;",;;;;;;,;;,,';;:",;1;';;;;;;;;";;111";;;;;;;';1' ;;;t'~

;;;,,";1"';;";;;"";;11;;;;;;:1;;;1;::;;;;;;11,',11,',11

lin
""
;,,;

5
6
7

•

The eHK240 routine w111 repeat powerup sequence if location 11 does not
contain a valid secondary Dootstrap (l.e., does not have a 240 or 2&0
In Itl. It starts executIon of the booted program 1f tnere'. a 240,
and 90e. to tne stand-alone proqram loader 1f there' • • 2&0.

l6
17 172426

23 17:14!>2
24
25 1n.456

26 172460
27 172462

rll'
11;1

1;;;;1',1;;1111111;;';'1"',1111;;1;;;;1';;11;;;;1;;;;;:,,;;
;;;;;11;1;;;1;1;;;;1";1/111;1111',1,',;;;;;;;;1111;1; ",;,;

20 112436
:11 112444
:i!2 172446

1111

nil

Hit

9
10
11
12
13
14

18 172426
19 112434

.
DISTINGUISH STANnARD FROM STAND-ALOkE FROM
N~h-iOOTABL€ VOLUMES.

CIIK240,
02:nl7

000240

001410

022737

0002&0

1100000

QOOOOO

(101447

004167
01:2001
012000
OO!>OOl

1'157&>6

eM?

1240,UO

8Ey

CMF

'200,UQ

SEQ

STANDI>

ellt"!"
ABORT

(No

VI::e5El
~oot

;Dld we read. valid bootstrap1
,Stand-alone volumes start w1tn 260
;Restore wiped-out vectors
block on voluM.>
;Unit CSR address

fIIOV

(SP).,IU
(SPJ+.RO

; llnit

CLR

;Standard secondary boots

MDV

nUlllber

KXT11-A2 lK 'lRM~ARE

aOOTs-ruse 800TSTRAP

MACRO y04.00

S-OCT-8l 22:56:27 PAGE

.SBtTL 800tS-TOS8 Bootstrap

2
3

..50

1;';'1";;;;11;;;;;;;1';;;;:11;;;11;;;",;;;;;;;;1;,;; "II;;
;;;1/""',1;111;;;;;1;;"""",;'1;;;11;;1";';;.,11;",;;

;, ;;
lin

JII;

1
II

U Hat'"

1& I'll4?6
11 1125UO

.EHASL

...,l

012740

17115'0

012101
005003
00:\211

170~U

004767

OOUl2

18 un04
19 172506
20 112510
21 lH514
22 172sa
2l 112520

1051U
100316
042111

25 l1<lsa
26 172UO

105137
100375
121127
001402

24 172522

21 112532
21 172530
29 172540

;;11

0&.703
004
004115
0(15141

U:
000001
004

MOV
MOV

ITUCSR.-(SP)

;C81<240 wents TU5& C8R

'TO$CSR,R1

Cl.R
HII:

lU
ItIlH

CALL
TStI:I

CHliIOUT

8Pt..

BIC
MOV

UC.IjRI<,{lRl

.8UE

R$$11<11,RUINT
iRS

lR1 -> output CSR for TUSS seriel 11ne
;Set RJ
0 (Two HULLS)
,Stert tran,mlttlng aR~AK to russ
;aena eIght NULLS
;1, tran,altt.r ready agaIn fetl
;It Pi" no • w~lt
IElae stop sendtng BREAK now
;Cettwo INtt contlll.nds for 11.11,)8

CALI.
176540

2$ ;

CIIPB
ill£O

; TOS8 1$ now !nittallzed.

30 172!U6
31 112560
38

:And transmit them
,DUll" any qaroaqe char 1n U$8U'
;1, charaeter available fro. the TUSS?
2$
Ilf PL, no - walt In loop
lIR1,tRUCON
;1£ so, was it a CONTINUE tlag1
3$
;If EQ, yes· go aneed
<T058 Inltldllz~tlon error>
-0'11)

. . fuelS£<

UORT

l5 172552

(I'Ch,iiJ

'1'51'

BPI.

000020

005000

012701
004761
1(0)23

lU
001000
000212

CLR
MOV

CAJ.,L
BPL
ABORt
• (l$ABL

1.Ik1

TST&

10
II 172544
l4 172546

LS8

TUBCJOT:

12 112464
U 172464
14 11241(1

1;1:
; J1,

TUS8 TA~E CASSETTE BOOTSTRAP

;;i;i;;;';;;;;;;;;I;;;;;1111;;;,1';I"";;',I;;;;I',','111"
;;;;/;;;;1;//,',,;1',;;;";;1';;1;;;';1/;1',1111',11.;1111;;

9
10
11

t?
Vl

1(0
HJ12 .. Nl
RUDZlJ

Prepare to read blOCk '0.

;BloCk number
0
;Byte count
one block
;Attempt to read the block
CHI<240
;If PL, reed was lucce'lful
<TU58 blocle 0 read error>
LSB

IXtll-A2 al rlIM.AI'
IACI" '04.00
aGOra-atalo-ALOIE 'OLU.' tootlrlA'

'-OCt-I' 22156,27 ,aGE 5J

a
2

.lltlL lOOII-ltand-alone .ola•• bootatrap

""""""""""""""""""""""""""""""
,,,,
""""""""""""""""""",""",""""
"""
,u,

4
5

''''

•7

••

I?
VI

, tfta. roatlne load • • tand-alone proora•• (a •• a ••d to .e 1n at-II .IAV
, til. tor.at) tro. an at-II tile .tractar.d tU51 Cartridge. U t i
, In.oke. If tfte tlr.t word In blOCk 0 ot tne certrldge 1. a 2bO.

012700
006300
Q22020

000001

012101
012104
00"61
100002

002000
001000
000162

01270.

001010

OU'OU
01OtOJ
OJa724
0010lD
On744

002000

001015
OU700
00U50

001002

.taIDI.
110_

11:

AIL

1II0Y
AOY
CALL
IPL
AlORt
AOY

CIII'

CM'

012105
022.425
001004
022.25
001002
022425
001410

attE

MOV
.1Ii:

U 172654
l ' 172660
.0 112662
t l 1126U
42 1726 ..
U 172670
. . 172672

000002

01OJ04
06270.
06240"
022.24
063104
0007 ••

001006

<Directory re.. error>
IITULI ...
(R4)+.RU

... R.J

IPER ..... , u.)+

••UIIDSG.,-(Rt)
5.
.. UtIEG,RO
11

1110 V

.nL .. AIII.R5
1I4l+.(R!U+
U

eM'
BItE
C;M'

(1!'l+,(R5)+
5'
(RU+, CR')+
LOAD

1110 V

Rl.R4
.D.'Lt,;",fc4
(RU+,I\O
(U)+,(R.,+

lEG

SII

1102 ••• Rl
.0IRIU.' • Itt
RUDU

<Fl1. not tound>

8NE

OUOOI0

U,RO
itO
(ItO)+.(RO)+

AIORI
CM'

.6 17267.
47 172676
.. 172702
. , 1721C1.
SO 112106
51 172H2

IIOY
MOY

811E

00.000

U 172640
J. 172642
J5 1726.6
36 112610

"11

""""""""""""""""""""""""""""""

20 172574
21 1726011
22 17260.
2) 172610
24.172612
2i 172616
26
27 172622
21 17262.
29 172626
JO 172612
31 172634

1001.tRA'

""
""
"""","""""""""""""""""""""",
"""

12
U
14
IS 172S6t
16 17256.
17 172570
11 172512

·'tA.D-a~O.I·VOLU.1

ADII
ADD
CM'

ADD
BR

.. nUYT,"
U

"et directory .eo.ent .1
,two blOCk. per .eo.ent
,Add' to ao. a. directory .tart.
, In block ..
I,repare to read two blOCk.
'Into tne directory batter
,Read the .eg.ent
l i t Pl., rea. wa. laece.ltal
,El.e prepare to piCk ap
, nartlll9 blOCK
,RO • • tartlng blOCk tor tile.
,s••e pointer to carrent entrr
II. tnl. a per.anent tl1e?
'If bit .et. ye. - eneek It It .atcne.
IE1 •• 1. thl. the end-ot-.eg.ent
, .arker?
,UII .. , no - go .klp tnl. entry
,£l.e get nueD.r of ne.t .eg.ent
,It He. tnere 1. one - 00 r.ad It
"Oint to RAD'O na.e of de. Ired til.
,Check tile na.e, flr.t wora
'If 11£ not de. Ired file
I ••• cn.c~ .econd word ot fl1ena ••
Hf 11£ not .e.1red one
, ••• rlnally.eneck exten.lon
'It ~Q, got It- 9- load tnt.
, one ln~o .e.ory
IGet entry pointer baCk
,Advanee to til • • lz. ot .ntry
,Update current fl1e ba ••
,And 'kIp to n.xt tile entry
,'lu, any extra byt., In eaen entry
,Contlnu. tile .earcn

KXT11-.2 lK fIR"WARE
aOOT$·~OAO

MACRO Y04.00

STAND-ALOME PROGkAM fl~'

5-OCt-li i2t56t27 PAG~ 54

.68T &I. l:IOUTfi .... o." Stand-Alone Pro~u'al!l El1e

2
1 1127U
" 172116
S 172120
6 1121;ti
7 172126
8 1721)0
9 172134
10 172140
11 172744
12 1121411
U
14 17;1152
15 1121Sl

16 1721$4
11 172156

18 112762
19 112766
20
it 112770
22 17:.1110
23 172'172

24 112776

It'

V\
\0

011401
(100]01
006.)01
004161
100002
013705
On105
001404/

LOAf):

AI:IORT

MOY

(SPH,Rl

s ...

AS"

000042
000040
000001

;R1 • 11•• of tlle 1n bloekl
; • 25., • word cOijnt
(U
; • 2 • byte count
IH.AOt,U
,H.ad tne pro9faM tlle lnto •••ory
11
Ilf Ml, error 1n re.d-ABORT
<Stend-alone fl1e read .rror)
flRT •• TA,lIS
IGet pr09fa. atart ecra
t1 ,RS
;IS adrs evenf
SrARU
lIt £0 yea .. ok.y
<111eOa1 tran.fer addr.,I)

MOY

CALL
IlIPL

Allon
"Oy
ilf

BEO

'fl4,U

&UflTU

012601
U2600
013706
005081
000115

000042
115010

00500.
016.02
000401

000004

Mon

(8P)+,1I0

MDY

III.R'UHiP.SP

Cf,JI

fllAP4
iRS

JIIIP

;P ••• the CSR a4dr •••
unit n~.b.r booted
11,0.4 pr09f •• • • • tack pointer
IOl'.b~. tr.p to • feature
,Go start program e •• Cutlon
IG~t

IUi:AfJZUt
CI.fI

REAOU;

114

MOV

4($P),1I2

AIIOUH3

;Loa41 et 0
IGet ~n.\t number
; SK1P QVEa THE ENTRY POlMT

IXfil-Aa lK fIRM_ARt
1110001 IlfRt POIRf

!!ACRO YQ4.00

~-OCt·'l

22:56121 PAGE S5
.$SfTL 111000G ENIRY POINT

a
.. lnooo

113000

5 11)000
i 11100t
1 111006

ooono

• lH010

10642?
000005
005000
017001

lO 17J0ta

OOUt.?

175242

Q\\

.1111110'00

bTl7l::
II'tPS

"leI?

CioN
S08

ltCl,.

"'MP

'IIR$UP

Run

(to

Jean', a.suee .nythino nere.
,But '.kIUP Ylually doe ••
tD£I.AX for the •• te Of PI.ARf.
I(M.lnt. ~lt cle.red bV R~.it
,just. little too lOn;).

...
"...'"
o
co
>C

'".. •a.

......
....
.....
... ""
......._c
o •

• 0

....

II:

«>

•

,.
'"

.;t

...

..
;Q

VWW
-.xC

III

...
MClQ
....

•

'"
C

.......

.....

""<

.. 0 ...

II)

...

.....

::>
1:1

.•
o<>
<>

""
1:1

11:

.. ...
.....
..

....

...
..

0
0

1).61

KtTl1-Aa lK rlk~.ARE
~ACRO Y04.00
aOO!S·aIOl/aX02 kSAO RouTt.Ea

~.OCT-81

22tS6;l1 PA'E ~1

.S8TT~

bOOfS-kX01/RX02 Read routlnes

.53

;',1);:"11",1;;;",1:",',;:",1111111;1:;",;;1",:111,,;
;lll;11;1;;;I':;;:JI";I;',;111,"';;",:;;;",II",',",111
HO
1111

6
7
8
9

IHI

FLOPP¥ OISK READ ROUTINES

1:H

1111

,,,,

; 1:' II II:; 1;; II I In" fJ; n JI n 11;' J;'1I, n" H 1; n, 1;;;n",
H , , n , ; : , " H : ; II ; ; ; , ; , : II; 11 J , , ; ; , , 11711 ;;; , n 11 ;; 111 n : I ;

10
11
12
13

with register. set up as below, ,e«4 the approprlate n~.b.r of
fUll .ectors trom tne floppy, at e1tner aenslty, witn eltner
HXV21 DNA or RlY11 Pro~r.m.ed 1/0 lnt.rlee••

RO: Starting block numoer for transfer.
ftl: 8yte count tor transfer
[(::II Unit nUMber
114: AdOress ot bufter to recelve data

U
16
11

18
19
20

.EIiAIiIL LSS

21 173030

OU44t1

22 1Hlln
23 173034
24

010046
010146

ORUIH

211

~
N

CheCk

26
21 1'13036

28 tHou
29 113044
30 17lu46

31 1'13050
32 173054
33 171060

17)06~

IS 1'71064

i7306t
11 U30n
1II 17107.
19
40

012701

005000
006002
1031102
052100
004567
000013
UU02
100402

l1il7a

U
U
U
. . 17:UOO

status and medla aenslty of .elected drlve

18:

000040

;Set UP R1 for beneflt of RXGO
,Init1alize currant unlt/denslty wcrd
talt 0 set. unit 1

1116

R2
1$
tliXUUH,RO

')ISR

RS,RXGO

.WORD

!lUlU;!

MOrtl
lUll

iR1,H2
21

;Set unit 1
~Start • read statuI operation
t to dater.lne status and density
;Pick up lOW byte ot status
rIf Pl.. drlve not ready

tRltUDN.k2
:U

~Check M.dla denlity
;If EQ, slngle density

sec

000312

.kXDB,IH
110

AlIGHT
IIll
8£0

(floPpy dr1ve not ready>

Oouble densltv.
Logleal sector number = log1cal blOCk number • 2
Sector count • byte eount/2116.
05:l700
012602

000302

41 l'7)UO
4' nuu

OUItO)
OfUO)

113114

012704

SO 17312G
U

0004111

000400

IUS

KOY

S.AB
IIOV
Ul.

000200

IIOV
6ft

.RlUDE,1l0

(SP"',U

;set double denslty ln co••• nd
;ilyte count
;01v14. by U.
; ..aN

R2
(6Ph,U
ftl
11211., ••

IItultlPly by 2
;words per .ector

aenltty.
LogIcal •• e~or nUBoer
10g1eal blOCk nu.Der , •
Sector coun~
Dyte count/l28.

lIZ

61f1g1.

55
56 113122
57 tUn.

111, *(bP)

ROR

0014U

4S 173104
46 17:U06
U

MOV

C1.R

012702

RO,-(&P)

1II0Y

00002u

,Save bufCer address
rSave starting keN
,.save £lyte COllnt

R4,·(~P)

MOV
NOV

012602
0001112

MQY
SIiAil

(si')+,1t2
R2

,ltyte count
tDlvlcae by 256

IXll1-.2 lK rIR.wARE
MACRO Y04.00 S-CCI-.l 221'6:21 PAGE ~1-1
~.--.) HALT At PC-171070 I_DIC.tES -'LOPPY OR1V£ NOT RE'~Y·

5' ,71126

006302

ASL

59 173130
60 11)132

012603

ltIOV

006103
00.10)
012704

R2
Hi,)+,R3
Rl

lUll

ASL

MOY

Rl
.64.,114

IIIUIUPly by 4
,word. per ,eetor

1731~4

62 17)136
U
64

.,L

000100

,And MultiPlY ~y 2

; Set up ateck el follow"
;
O(S,)
Looleel Sector NUM.er
;
2(S~l. Seetor count
,
4(~'). word, per .ector
;
6(SP)
8ufter addre.s

10 1"142

010446

11 171144
12 111146

0102.'

411

01034.

IIO¥
IIOY

R4,-(6P)
R2, .. (."

MOV

Rl."(~P)

;words per .eetor
,Sector count
;Lotieal Sector Huaber

13
74
7!t
76
77 11315U
18 171154

Start the read operatIon.
tnl' IS the top ot the loop.
004567
000001

000216

Sf;

tr'

0\.
tH

80
81
82 171156
83 17)160
I. 1131'4
85 111170
86 11.3172
87 113176
I I 17)200
89 173202
90 173204
91 171206
92 173210
93 171212
94 171216
95
9. 113220
91 1112~2·
11322.
99 111226
100 111230
101 171232
102
10l 1712S4

104 171a40
105 171242
106
107

012102

(2270)
101002
0627U
00610l

fi.·

000010
006400
171400

ADD

76&

oonoz

00n70
110102
105001
000101
022103
006101

6St

MOY
MOY
CliP
8Ml

ROL
DS:C

&G1
IIOY,
CLA8
SwAS

000014

,Start • • ector read

,SIi',U
n. ,fl2

126.*2:00,I'IJ

U
Ill. f!~

IU
112.,fll

ROl-

ASL

11:2
R2.kl
1ot2,R)
fl2,Ri

IGet LOGic.l Sfil:tor lIueber
'Loop count
100.S 2_ qo 1nto d1vtdendl
;8ren\:h U

'-26. S 200,IU
Rl
R2

eMf

noh e ·cUar UUI1 .,. fleC)

;&\J.otr.et 2b troe 41vt4end U: set'
,&/lUt d1vldend 4I\d q\loUent .
;Dolcr••• nt loop count
II".ncb till dhlde done
,Copy track no.ber
IReaove tr.CK nuaber fro. re •• ln4."
, Get nealnder
,Cal tf ,l<-II)<=25, el •• CaO

060203

AOI>

060203
060201
006202

ADO

005202

lJiC

III
flot

,S.ctor*2 (2*1 lnterlaava)
J(~l (C) 1t sector 13-2S)
11>0llble tile tUCk nll.ber.
I S.kew tlUr &ector
; by addlno 1n
, • * track nueber
lUndolibla tne track nueber
, and .ake 1t 1-70 (Skip traCk 0

sua

.2' .. RJ

I'llt •• ctor

006302

16270)
002315
062103

ADO
ASR

000012
000013

tIS:

aGE
AOI)

fOr AIISI)

into un.,.

81
127 •• 11)

1-2b

; Wead tne .actor
010111

IIOY'

110 171250

004514

,JaR

111 111252
112 113254

010211

MOV

lU nuu
114 17l~60

R5.IUtOO
RltartEQ

convert LoOieal Sector Nuaberl to pay.leel treCkl end lector ••
011603

tot
109 173246

JSR
.IIORO

004514
100002

Jilt
BPI.

ABuar

,'let

U. iIIRt
R5,tU
li2,iII"1

115.,,,,
U

<Flopp~

.ector nuaber

;Sat traek ftl,lllliter
;Perf"r•• lIei;tor ua"

r ••d arror>

IIf 1111.

error

IlACRO vot.OO S-oCt-It 22.56121 PAGl 5'
·IIlt-aa tk 'IRMe'R'
•••••••ALt At 'c-I'Jaaa INOICAtea -'LOPPI RE'~ I:kMO.1
2
J 1712. .

• 111210
I nJ272

6 lUaOo
1

,10, 17:U02

OOUI'
000001
012117

OOltO'

004000

016611
004114
016611
'1.1 UUIt 00•• 14
14 l1Ul6 00.410
12 luno

ooOOOt

MOY

000006

016603
00U03
0&6602

it2 17Ua.

0041'4

000004

lOu

lUI

'I'"

ItS, ....

6UiP),.fll

12.

,'I., lo.d word count
,walt
til
'And 10., currant ~u ••••ra ••
, ••1t 'or DO.,

"1'

MOY
ASL

4(IP),Rl

IIOY

Rl
6<"),R2

oJak

R$,.It.

IIOva

till, (le2)+

U,ll.

,Gat word count
,Turn word count tnto Dyta COunt
,Gat .tartln9 OUt 'ddra••
,Mova on• •yt. Ir •• "Dull.t to •••• ry
,lfaU tor ta"or ODII~
'Loop lor all Dvte. In Ilt.t •• ctor

, LOOp baCk l' bot ,at flnl.ned

:n l1n60 016601 000004
0000 ..

MOY
AIL
ADD

OOU66

000002

lllC
DEC

nu ••

1»62706
01»0251

000010

1131'0

000201

21 17a1..

OOUOJ

30 17.na

0'''6'
01111.

It nUt.

al UU"

:aa UU60 ootau

U lU)6a
)6

oJ••

loe

01130)

,at,rt '.pt~ Dul,.r lunettln
, aft' .. n lor tR
OMA ayallaol"
,1' IQ"no • h'ft'l, " RIOI

RIOI .rogr •••• d 1/0 Oparatlon

000006

Uln2

USP) ,.111

.5,'114

MaY

U l,uao
19 11U24
20 1UU6
21 11UIa

)4
Ii

.ft,RICO
RUEM •
IRII .. oa,,,RXCI
10,

.Jail

Jill
• tfOftO

It'B'Q"

111110

U l11U6

RIVtl/RIY21 Dulfar Into HAil

, RX02 DMA o,.rotlon

"-II lU30"

,.'t~

,..

000102

1211

.,,'
ADO
ecc

REfUati

.0"."""

4(11') ,RJ
U
n,6(IP)
2(SP)

II'n.,IP

,Gat word cOllnt.
,tllrn lftto D~te count
,upeat, DU. ed'r•••
,Updata" Looltal 'actor ~u••
,D.cr...nt ••ctor count
, •••• enoth.r ••Ct.t
,POP tfte ttaCk
,Cl •• r con'ltlon c ••••
, to tftow .ucc••••
'All dona

--.-.>

KXfll-A:a lK rlkMWARE
.ACRO Y04.00 5-UtT-8. ~4:!6:21
HA~t AT PC-1732.2 ihOICATES ·r~opp¥ RtAD EMIIYk"
1
2

The maln lubroutine for
their completion,

1
S

i
9

0'1
V1

lendln~

d1&k command I and walting for

Reqllter usage:
RO = censlty ~lt 1 unlt .elect bit (Ploto tor co~mand.)
1\1 • RX08 addre,s
1<4 = kXGO TK/OONE telt routine polnter

"
10 173172
H 173314
141 173316
13 173402
14 17)404
15 113406
11:1 173412
11 113414
11 l1l4U

PAG~ ~9

PXGO:

012504

050004
01v437
010704
00"41
032711
001775
005121
00020~

177170

MOll

(R!oH,R4

iUS

1<0,il4
R4."kXCS

/!lOY
MOV

000240

81'1'
8i..f.I

PC,R4
-OU)
.RX$.TRIRX$$PN •• Rl
U

TST

(Rl )+

RfS

1<5

;Copy co •• and word te use
;Set unit • and denstty
;Start eperetton
;COpy adrl for later calli
;R1 -> !!XCi
,.elt for TR or PONE
:It EQ, neither ere true yet
;Relet ~1 -> KXUa end cn.c~ tor errorl
:Return to celler

lXfl1-A2 lK FIRMWARL

aOOfS*tu"

READ RoUtt.i.

MACRO Va4.00

S*UCT·81 22,So,27 PAGE 60

•• aTt~ 8UOt$~7US8 Read ro~~lne.

:'I

1
4

;;;,JI;1##ll',II;";;;;JI:;;;';;;;I"t":;11;";,,tlll,,,,"
';IJ;;I;"",;;I"""';1';;',l11"'ll;",1""1111",""II

,
•
5

II;;

II"

;',1

:III

"',1/"'::1',"";1,,"11;:::',','::1"::;',,";:1:',",",

Starts a read operation on tne fUSS by tr.n'.l~tlhg • eo••and packet

12
11
14
15

Inputs:

RO • starting blOCK • for tren.fer
Rl • byte count for tran.fer
R2 .. unit l'Iullioer
1
Rf .. aOdre,s ot buffer to recelVe data
1
I Outr-uta:
ao, RS, R2 uncnanged

1ft

17
18
19
20
21

in
2.1
a4 17ltaO

D•• troyu

Rl, R4, /(5

.ENAIL LSa
MOV

THUD;

010••'
005004

2b 173422
26 113424
27 17 ... 10

012103

211 113U4
29 It)440

912703
0041U

30 173442

"11

',"11:",;"":111",,"';;;;;;1"';'1,""""',111';1";;

10
11

fuSa O£Ctepe 11 READ ROUTINES

"~;;

00f767

005002
000206
000002

IIOY

'10 •• 400+RSICtL,Rl
CH20UT

CALl.
IIIOY

fIllRUIi,Rl

CUI..

.&0201

MUY

31 lU4 . .

004715

12 171...
U an,no
It 1734$2
n UlU4
36 171tS.
U 113460

005.03
004715
010103
004715
010003

CALL
CLR
CALL
IIIOY
CALL

.u 171.. 2

It 173...

00.,15
010.01

oonu

R4,"UIP)

CLR

MOV

CALi.

;Save bllf~.r addrea.
;In1t cneck.1I1II
;Set eo••anG tlaq and lenvth
tOutput ~.o chal. and .et R&
;Send re.d eo ••end and lIIo<UUer••

R2,R3
US

,then unlt nUMber and •• 1tche.au

,P1U' a zero .equenee nu••er

fRa
1!l,IU

tRS
RO,Rl

MOV

iRS
R.. ,R)

CALL

VRS

;'Ollowed by tne byte count
lAnd the blOCK nUMber

,t1nallf, tranl.1t tne eheCk.v.

11%11-.2 11 FIRMW.RE

MACRO V04.00

tOOTS-fUSe ~EAO kOU!IN,'

5-0CT-81 22:56:21 'ACE .,

No" reedy to 4I!ccept Qat" 1IIt1 •• gelll fro. the TUS.

1
2
1 17H66

..5 173470 012600
006001
6 11U72

1
8
9
10
H
12
U
14
15
h

171416
113502
lU504
11)506
11)510
17U12
11lSH
111U6
1USn
.13524

11 171~<l6
18 1135)2

004767
12270)
001017
105(0)
000303
10600$
111030.
010305
0114161
(/10UO
07750.
004761
005701

000116
000001

181

"
01

......

31 1'11572

)2 173&14

RUUIUI

buffer
I(CN20UT leave. e cl •• r)
III
IRl • word count tor tran'.'f
7,
;Get tirlt •• rd of packet
UUDAT,RJ
;11 this lnde.d a G.t ••••• age1
J6
fIt II~ no ••• y be END ••• 111.'.
Rl
;Els. c1 •• r fl.gs
R3
rllove pacKet byte count to low byte
iU
tAnd convert to word count
R3,/U
,Re.ove troe tran.fer count
R3.R5
~And copy tor loop counter
9$
1Get next t.o wor~1
Ml.(RO)+
,Store 1n Dllff.r
R5,2'
;LOOP tor ent1re date Mel.ave
S$
,Get checksllm anc eo.pare
Rl
:Have all data records been
; tunSferreCl1
11
11£ Nt: no
18
lAnd get proloectlve
1 EMU packet Itart
91
;Get opeOde/luceeSa by tel
; of '110 paclCtt
IR$U./,l,RJ
111 tnll an ~NU peck.tl
4$
,It HE no - A~ORT
<TUSe EIID pae~et Ml.lln9>
Rl,RO
Isave luece •• code In 110
8$
;Read r ••• lncer of ~IID paCket
5$
;Ano cneCk ltl cnecklu_
110
;Set ce'lII on suec•• 1 code of tren.fer
;Return to celler

CAL"

eli2lN

SEQ

,Get two checK. II" bytes
;ooe. it .atcn calculated val11e1
,If Wt no • ERROM

CAL"
8Mt;

'''R8
SIoiAB

1<01'18

sua

MOV

000102

281

CA.!.!.
KOV
SOB

000044

CA.""

'tSf

001350
004161

000052

004761

000056

122103
001'02

000100

010300
004767
004767
OOOlOO
000207

;RO -> .at.

CII'II

19
26 113534
21 173516
22
21 171542
24
2~ 11l54'
26 113552
27 173554
28 171560
29 111562
3fi 171566

(I5'H,itO

tlOV

'"e
ROR

fiNe;

OOGOn

CALL
3U

CALL

C"'8

4.=

000004

BE:Q
.BORT
1110 V

CALL
CA""

SiliU

3f 17)576
35 17U02
36 113.04
31 17360b

004707
02040l
001402

0000 . .

eM'

ABOFl'l'

38
39 173612
40
U 173614
U 173616

Rf,R)

<TU&8 checKIIi. error>

000207

RnURN

005004
0004112

7$:

eLR
ilR

,.
R4

Ilnit cneckllllS
lAnd get the tirst word

004717
004711
004161
0(0)04
005504
000207

8$;

CAL"
CAL"

fPC
,'C

I RIUld 4

;&11. return with luccess

44 1716~0
4$ 1716:U
46 17)024
f7 173630
fa 11)632
49 113634
50

000036

CALl.

ADO
AIlC
Rt'fUR •

• DUe" "'8

CM2'U1
Rl.1I4
R4

wordl

,Reed next two byte.
,Add 1nto Check. II'
I wltl1 end-,rouno carry
lAnd baCk to caller

KXfll-12 lK fIRMWARl
MACRO Y04.00 5-OCT-81 22:56127 PAGE 62
••••• > KA~f Af PC=ill6'0 IBOICAtES wTUSa 'K~CkSUM ERROK-

CH20Ut .- WrIte two bytes to tne fUSe

2
3
4
S

krites two bytes to interface and update. checksum,

R} = two bytes to oe output, low otte first
K4 • current enec~$um word
Output.:
Rl uncnanged
R4 updatea to new ehec~su.
R5 pointing to C"20~T routine tor ea.ler future CAkLs

Inputs.

a
II

11
12

CHiour:

13 !HUe
14 lHU6
1 ~ 1 '1l'40

til nuu
17 17)642
18 1'13644
19 Ul ....
lIO 173650
21 173.,52
22 l1U56
23 11)660
J4 173.U

25
26
27

004117
OOt717

,~ntrf

MOY

PCtR!)

ADO

f<J,R4
1<4
'i'C
.nO.CSR

,Set 1<5 to followlng rout1ne aor.
;Update cneCk,u. wor4
, wltn end-around carry
IRepeat for bot~ Characters
;Is interface reaoy for output?
,If PL no - walt
;£ls. transmit enaraeter to T~5.
IMerge wlth otner routine to return

point to output 8 cnarecter.

CfoI20Uf:

OlGlOS
060304
00SS04

ADC

004111
10U)1

SOOln
110337
OU040?

176544

CUI..
fSlb
BPI.

Kon

176541>

lll,urOUF"

CHHU

Reed two bytes trom tne rU58
Rea4 « *1ngle oyte fro. tne russ

CH211'1
ChIle

, InpIlU:

:.to
31
J2

none.

I Outputu

Rl = enaractertl} r.ad

l4 173666
15 17U70

,PC
fPC

CALL
CALL

36 in.a
31 11361.
J6 l1HOO

004717
1050113
10SH?
100115
lU10l

III U.f104
40 1731IH.

000,)03
000207

'"211111
176540

CHIN I
UI

176542

Cllillo:T:

CALL
C1.RB
tBU
BPL
UIHt
SWAB
R1:11.1111.

tlPC

Rl
tlTUCSR
1$
UTl$lif'R,ICJ
1(3

;Read two. not one

lAnd Cero OUt space for new one
;ls « Character avatlaolel
fIt PI.

,Else .et into register

;Move current cnaract.r over
,And return to caller

...a

!oJ
&

!oJ
to

...
•
......'"
C

lit

..:I

.
.'"
...,..
...

•.
lit

/.or

.........

ItI

...
...,
to

. ..
.
C

•

rot

1ft

•

10>

Q
II:

V
C

II:

""
••
•...

0
0
<0
0.

til
C

.......
..... ......
..·..
1111111

... 1Il

.. 0

fCC

K'"

D-69

IXlI1-A2 11 rl.~.AR'
SYIIIOJ. tAllo'

MAcao YOe.oo

"IIOUI2

E.'A" • 000001
fAkGU., 170424
nIoUM. 1100002
GUCHR 171510
GEt.IiN 171612
HGHaEG. 001004
HKlOO
17U40
HKlD,
171142
HYIAUD U05li6
I118yn 170550
lNan. 1705U
INnS
111750
IN.USR- 16776. G
IC8DD
170674
KIOI
170702
IoCIEf
171241»
LIOO,r. 1100017
lor
• 000012
LOAD
112714
100CO'' U1252
a
000221
"ODE
1717JO
"aGO
IIIGI
IU7U
I'XlUM 111600
NOC!
17164~
NO.Io&lIl- 100000
NXIIE;. 001002
OC"'R 17l1i5.
OCfstO 17un
oor
110602 G
OO'1'rIoG- 167750 G
OOlIoOC. 167746 G
ODrark. 16174.. G
OOt.HI. 16777. G
ONENUJI 171576
O.C..,Io. 167172 C
,AtIERt! '11150
PaRO • 000010
PIRl • 000020
PlRa • 000040
PCIIO
111044
PER .. ,.- 002000
PP.A • 176200
PP.8 • 1162C12
".IIC. 1I0000U
".IU. 000001
PP.810- 000000
".111. 000002
'P. In. 0041004
PP.IU. 000006
".814. 0011010
".eU. GOOon

AlOUJl)

Ii'
~

I120S0
17101.
170e72 ;

AUtOIA
IADIOf Inno
lAUD... 0000:12
10.00). 000000
aD.OO'- 000010
10.012. 000020
10.024. 000010
80.0"'. 000040
80.01/,. 000050
ID.U2. 000060
ID.J". 000010
8UO • 000001
8nl - 000002
1l!1O • 002000
IU11 - 004000
anu • 010000
auu - 020000
aUl" - 0.. 0000
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0-77

APPENDIX E

MACRO...ODT ROM LISTING
FOR KXTl1 .. AS OPTION

Appendix E provides the user with the program listing of the KXTII-AS Macro-ODT firmware option.

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AUToeAUO ALLO~S THE Fl~CON TO AUTQ"'TICA~LY SYNCHRONIZE tTS
CONSOLE O~'_T TO THE SAUD RATE OF THE CONSOLE TER~tNAL.
ON POWER-UP, THE uSER MUST TYPE • CARRllGE RETURN tHA_'CTER.
UPON SVNCHRONtZATION. AUToeAUD ~lLL PROCEED TO OCT w"EAE AN ",
C~A~lCTEA WILL 8E DISPLAYED ON THE CONSOLE.

911

'UToeAUD WILL LO~P tHDEFtNtTEL' UNTIL SYNCHRONtZATION IS SUCCESSFUL.

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T"! ALGORITHM REQUIRES THAT THE COHSOL! '!RMtHA~ GENERATES A
lERO (SPlCE) FOR THE EIGHTH ~IT IN THE 'ARAJAGE RETUAN. THII
WILL HAPPEN tF THE T!AHINAL I' CAPABLE OF SENotNG EIGHT-8IT.
NO-PARITV OR SeYEN-err-Ooo-pARITY CHARACTERS,

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'uToe'~O.S'NCHRONIZE ~lTH

HI t i l " t H I I tit I, n III " f i l ' "
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['4VI"ON"!;NT,

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INTERRUPTS "UST 8£ DISABLED FOR THE 'LGOAITH" TO ExECUTE CORRECTLY
srNCE TIM! DURATIONS ARE C'ITICAL AND DELA.S OUE TO LONG
'ERVICE ~OUTtN!S MAY CtU'E OLAAl OVERRUNS, W~lCM THIS ROUTINE
IGNORES euT CANNOT TOLER.TE,

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9113

9411

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VTI83/F'LCO~ CONFIGURATIONS LEA~E GAR8AGE IN THE DLA~T LONG AFTER THE
.OwERU' SEQuENCE HIS IlGUN. "E MUST DELt' • 81T 8EFORE CLEARING GAR"GE
OUT ~f THE ~L'RT. OTHE~wrSE TME GIRB'GE WOULD ARRtvE .FTER THE CLEAR
(1.£ •• -HIlE POLLING FOR INPuT), THE we'AeAG'- 15 IN W-ON (CeTRL-o>'
THAT tHE YT_I'. H.ROWIRE SENDS .FTER ITS POwER.Up OrAGNOSTICs MAVE

94/1.

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APPENDIX F
SBC-J1/21 PLUS SCHEMATIC

Appendix F provides the user with the electrical schematics for the SBC-ll/21 PLUS module.

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5-AB.I 5-C'.L 5-01.L
5-0'.L i-8'5.0 '-~.O
i-82.0 i-8'5.D
~-D'5.1 <AP2>
~-C'.I <AU!)
~-D'5.1 <AU!)
't-C'.I <AV2>
"-Cl.L <AV2>
~-C7'1 (1E2)
~-Cl.L (BE2)
"-C3.L (ElF2)
"-Dl.L <1IHi!)
"-D3.l (BR>
't-D'5.1 <81(2)
"-03.l <IL2>
"-C'5.1 <Ima>
't-C'5.1 <8M2>
"-C'5.1 <1IP2)
"-C'5.1 <IR2)
.. -C5.1 (852)
"-C'5.R <BT2)
"-C'5.1 (1Ue)
"-D'S.I <IV2>
~-o&.D

..-n.L <1V2)
"-8'5 •• <ACt>
~-85 •• <lIOt'
"-1'5.1 (1A1)
l-Cfi.L <tAl)
101M L ......... ................ 3-~.L '<AH2)
"-C7.1 <AH2>
8DI'IiO It ........................ 3-C2.L 3-C" ••
..-m.1 (AS.!)
8DfI6O L ........................ 3-C... L <1152>
IOAL 1'5 L
IOAL Ii L
IOAL " L ......................
IOCOIC It ........................

. . . L .........................

~-85.1

(AMI)

IDOUT L ........................ l~.L <AE2)
BEVNT L .................... .... 3-Ci.l. (BIt)
IHALT L ........................ 3-06.L <API)
3-Bfi.L <111M2 >
IJMO L
3. . . L <AT2)
IINIT L
IJRQ '" L ... .................... "-A'5.1 <AL2>
.-oK It ............. ............ ..-A7 •• <881>
BlEF L ............. ............ "-85 •• <M1>
8IPLT L ! ....................... 3-06.L <AF2)
IlSACK L •••••••.•••••••••••••••• ..-A'.I <INI)
~-A'5 •• <MI>
ISPM£ t It
"-85.1 (11181)
ISPME 2 It
't-t'5 •• <1IPt>
ISPM£ 3 It
"-15.1 <acl)
8Sl'AIIE .. It
~-8'5.R <B01)
8Sl'ME 5 It
ISPM£ , It ..... ................ "-8'5.1 <BEl)
8Sl'ME , It ..................... "-8'5.R <IFI)
3-Bfi.L <AR)
8STHC L
3-1".L <M2>
8\.ITIT L
'-C ... L 3-C2.L
CDI1RCI L

i-8'.1 '-03.D

..-1'.1 (ANt)
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•• (AE2)

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"-D'S •• CAF2>
,,-D'S.I (1N1)

"-D'S.R <AR>
't-C'.R (AK2>

CTrI£R L " .. """ .. """.,.."" .... """" .. ""
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1CJCT3 . . H ,1. " ..... " • " " " " " .... " " " .. .

'-C'5" 3-te.L
'5-AB ••

N.TTl ....................... . '5-A2.L
KICTt Il1081 It .................. .. '-II2.L '5-el.1
'5-01.. i-~..
KICTt A082 It ................... . ,-I2.L '5-t3..
'5-01.. i-~..
1-~.L !-c'5..
KICTt AOI3 H
'5-06.1t '5-Dl.1
1-82,L 2-£',.
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1-12oL
K)(T! A08i It
'5-0&.1 '5-08.1
l-te.L
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1-112.l. 2-c'5..
IC)(TI M)I8 H
'5-0&.1 '5-01.1
,-te.L 2-C'5.1
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. '5-D't .L '5-D' .L
,-C2.L 2-C'5..
KICTl 110" It
'5-~.L '5-07.L
l-teoL 2-C'5..
ICICTl 11011 It
'5-D't .L '5-D1.L
1-112.L 2-C'5.1
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'-te.L 2-t'5.1
K)(Tl 11013 H
'5-06.. '5-01.1
ICICTI jilj)1~ H
1-I2.L 2-C'5.1
K)(Tt jilj)15 ..
'-I2.L 2-C'5.1
ICICT! B2CL. L ................. .. 1-17,1 '-C7..
ICICTI BtL. H ................... . I-02.L l-I&..
ICNT! CAS It .................... .
1-17..
ICICT! CAS L .................... . '-01.L 3-8').1
ICKT! CllCRQ H .................. . .-cr..L
1C1C11 CPII05T It ••••••••••••••••• , .... .1.
1C1CT1 CIDt..2 It ................. ..
KICTl C1COLI H ................... ' .....L
1ClCT1 CICOL2 H ................... I-....L
K1CT! HTIP L .................... '-C'5.L
IC1CTI LIIS7 H .................... l-te.L 2-C'5.1
1ClCT! PI H ...................... '-M.I l-D't.L
ICKTl PJ L ...................... '-A'5oL
tC)(t1 flM, L ... " .. """""""""" ...... ,,",,.. 1-Ott.L 3-83.1
ICICTI ISTNC L ................... 1-112.L 't-C7 ••
ICICTt SEL8 It .................... l-C~ .L 3-1').1
ICKT! SELl It ......... ........... 1-~.l. 1~..
ICKTl T857 H .................... , -~.L 3-Ci ••
ICICTI TCOUT H ................... 1-D't.L l-B3 ••
KKT2
L .................... i!-Ci.L 3-~ ••
Z-C3.L &-01.1
ICIC12 CSDt.1 L
2-Cl.L fi-~.I
ICXT2 CSOLI L
i!-Cl.L '5-C?L
1CIC12 CSICTA L
2-C3.L '5-C".L
KNT2 CSICTI L
KKT2 CSPL L •••••••••••••••••••• 2-Cl.L '-8,.1
KICT2 CSOB L •••••••••••••••••••• 2-C3.l 3-Cl.1
ICICT2 C~ L ••••••••••••••••••• 2-Cl.L 5-13.1
KICTZ EVNTAK L .................. Z-Ci.L 3-C'5.1
ICK12 PAM L •••••••••••••••••••• Z-Cr..L 7-C3"
i!-Cr..t ?-Cl.I
KKT2 PBIIIK l
2. . . L 3-11.1
ICKT2 SCLK H

I.................. ..

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I-D1.R
'5-ti..
i-D1..
'5-Cl,.

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't-I7 .L

1-17.1 3-13" ~-A7.L
,..,.1 't-l7.l.
1ClCT~" H .................. ..
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IC)(T't I€jiIj) H
ICICT't Il£N) L ................... . 3-C3.1 't-Ci.L '5-81.1 '5-C3.. '5~.L '5-C1.L
'5-D't.L '5-D7.L i-~,1 IH>'.I
KXT.. ISACIC.
" ...... " " " .. " .......... " .. " " " 3-83.1 ",,",,,.L
1ClCT.. SELfi L ,.................. .. 't-ti.L 7-11 ••
ICICT..... L .................... . 't-ti.L '5-t3 ••
~-Ci.L '5-83.1 i-~.I '-D?. 7-17.1
~
1ClCT' IDAT'
••••••••••••••••••• '-C'5.L i-l)1 ••
IOCTI IDAT2
.................. . '-C2.L 6-D't.1
ICICT' lCOATlP ................ .. r.-C'5.L ...Ci ••
1C1CTi lCOAT2f"
................. . &-c2.L i-C3 ••
ICICT' .......................... . 7~.L '-06.L
KICT' PAl H ••••••••••••••••••••• 7~.L 7-06.L
1ClCT? PA2 H ................... .. '~.L '-06.L
1ClCT7 PAl H ..................... '-~.L '-06.L
ICICT' PA't H ••••••••••••••••••••• '-....L '-06.L
KICT' F'fI'5 H ....... .............. 7~.L '-06.L
KNT? ~ H '. • • • • • • • • • • • • ..... ... '~.L '-06.L
K1CT7
7~.L '-06.L
1ClCT' I'MCIST It .......... ........ '-A7.. '-te.L
KICT7 PIt H
'-II2.L 7-Ci.L
1C1CT7 PlI H .'.................... '-I2.L ?-CI.L
'-82.L 7-Ci.L
1ClCT' PI2 H
'-:82.L '-tfi.L
'1ClCT' Pll It
'-I2.L '-Cfi.L
ICICT' ..... It
7-12 .L 7-Ci ,L
1ClCT' PI'5 H
'-I2.L 7-06.L
ICICT' .... H
'-I2.L 7-06.L
KICT7 1'17 H
1-A7.1 '-H.l.
KICT7 PIIROST
ICXT7 PCB H
"-C'5.1 "-Ci.L
lOCT7 PC 1 " ",...... "" .. """ ...... """ .... "". 7-ti.L 7-0'5,1
'~.l. 7-ti ,L
7-C'5.1 ?-c&.L
7-ti.L 7-o3.L
'-C'5,1 '-c&.L
KICT7 ' " It -1- ................. .. 7-ti .L '-Dl.L
KICT7 PC, .. .!................... . '-C'5.. 7-cr..L
7-17.1 '-C't.L
ICICT' PC.. It
ICICT' PCJl H I................... . ,-P.I '-Dl.L
I
1ClCT' PCR It ).................... . 7-Bi.L "-C'5.1
1CXT7 Pen H ~ ................... . ' ....L 7~.L
, . . . L 7-~.L
ICKT' PCJ'5 H
ICKT' pcp H i. . . . . . . . . . . . . . . . . . . . , . . .L '-C".L
PAJI H
'-A7.. '-I'5.R
PAJI H :::::~::~:::::::::::::::: "-A7.1 '-85 ••
'-A7.1 7-1'5 ••
~
PAJ2 H
7-A'5.. '-A7,.
PAJ'JH
PIVt H
'-... L 7-8'5 ••
PA.15 H
' .....L '-85.1
PAJ& H
"·... L '-8'5 ••
SHEET 8 OF a
KKT" ""AlL

'................... .
J

.... L1.. ·· .. · ......·· . ·

PA7 H.:....................

.1....................

E~ ~ L::::::::::::::::

I....................

.AI(

'-1'5..

+.......... .; ...... ..

'5-Cl.1 '5-Ci.1 '-CI.R '5-01 ••

'-C'.. 3-O'I.L

2-15.. 3-83,1 1-Ci.L i-II.I
KKT3 DCLO H
1ClCT3 DLCLK ~ .................. . l-C2.L
'~,1 fi-D?.
2-t7.1 3-De.L
1C1CT1 JAIC L
ItXTlB57M •••••••••••••••••••• '-el.. 3-t5.L
1-17.. 3-D'5.L
ICXT) I€VMT
3-83.1 3-06.L
KKT3 IIIPLY
1C1CT3 ISTNC
1-83.1 '-Bi.L

I................... .

.... ................... .

.. ,. ............. .... " .. ...................... 7-A6.1. 7-8'5 ••

PAJiI' H

,","

PBJt H ............. " " ............ " ...... " ...........
PlJ] H

.. .. .... .. •

PlJ'+ H

. . . . . . . . . . . . . . . . III .... ,. . . . . . . . . . . . . . . . . . . . . . . . . . .

'it . . . . . . . . . . . . . . . . . . . . . . . . . '" . . . . . . . . "

............ " ....................................
PSJ6 iii .... " ............................................
Pf,j7 iii ............ " '" ......... " .. ,. ...... " ..........
PCJ'; H ,. ........... ..- ....................... ............
PB.J5 K

PCJf, H

PUf> l

,. . . . . . . . . . . . . . .

. . . . . . to " . . . . . . . . . . . . . . . . . . . . . .

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fit/II'" H

. . . . . . . . . . . . . . . . It ...... "

.... ,. . . . . . . . . . . . . _ ..

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R/Illa H

Rl>ATlN II

.. '" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 . . . . . . . . . .

lOATeN H ............ ......................... "

"-Al.R " ..... !.
7-~t!.
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7·A7,fIt 7-It.fIt
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c . . . . . . . . . . . . . . . . . or . . . . . . . " . . . . . . . . .

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...........................
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".~

SHEET 9 OF 9

APPENDIXG

GLOSSARY

AllOl-ADtS - A 15~bit on~board address bus used to address memory and peripheral devices. Generated
by two 8-bit latches that are loaded from the TDAL bus. See also BBS7.
AIO-AI7 - Input lines used by the microprocessor for interrupts and DMA requests.
ASPI - Microprocessor transaction that allows the microprocessor to recognize and accept pending
interrupts or DMA requests.

AUCom:aud - Self-adjustingbaud rates for SLUI only. Implemented by firmware in the optional Macr~
ODT ROM.

BDS' - LSI·lI bus signal indicating that the device addressed is in the I/O page.
BDAL 0-IS - Multiplexed data and address lines of the LSI-It bus connected through the backplane.

ROCOK - LSI~ II bus signal· that goes high 3 ms after dc power is applied and goes low 4 ms after ac
power is removed.

BDIN - LSI-II bus data input strobe.
RDMGI - LSI-It bus signal from the BDMGO bus pin. It enters each module on the BDMGI pin and
exits on the BDMGO pin. It represents the bus grant for a DMA transaction.
BDMGO - See BDMGI.
BDMR - DMA request signal from the LSI-II bus.
BOOUT - LSI-II bus data output strobe.
BEVNT - LSI-l I bus signal used to generate REVNT. Can be used to initiate an interrupt.
BHALT - LSI-II bus halt signal used for a priority 7 interrupt that vectors through location 140.
BINIT - LSI-II bus signal used to initialize all the devices on the bus.

BIRQ4 - LSI-II bus, level 4 priority interrupt request that is used to initiate the internal IRQ4 signal.
BKRQ - Internal control signal initiated by BHALT or BREAK detect from terminal.
BPOK - LSI-II bus signal that goes high 70 ms after BOCOK and goes low when ac power is fast.

G-I

BREAK -Initiated by pressing the BREAK key. Causes the transmission line to the SLU to be forced to
the space state (logical zero). This condition is sensed by SLU I and causes the SBC-II /21 PLUS to
generate BKRQ that can be used for interrupts.
BRPLY - Slave's acknowledge of an LSI-t I bus cycle.
BSACK - Acknowledges receipt of a DMA grant signal.
BSYNC - LSI-II bus cycle control signal.
BWTBT - LSI·lt bus write byte control signal.
CAS - An output from the microprocessor that acts as data strobe. Used for the read/write, DMA, and
ASPI transactions.
Condition codes - The least significant four bits of the processor status word that monitor the results of
the last instruction executed.
Configuration - Allows the user to select optional features of the module by inserting jumper wires.
Control and status register (CSR) - Internal register in an I/O interface that allows the program to control
and monitor the operation of that interface.
Control word - The data contained in the control register of the parallel I/O chip that determines the
configuration of the parallel I/O interface.
COUT - An output from the microprocessor clock that is asserted once during each microcycle.
CSKTA - The RAM/ROM ~ocket set A chip select strobe.
CSKTB - The RAM/ROM socket set B chip select strobe.
CTMER - Time-out interrupt that has the same effect as HALT.
Cycle slip - This condition exists when the READY input is pulsed while RAS is asserted. It causes the
microprocessor to be idle, and no transactions occur.
DATI - LSI-It bus transaction that transfers sixteen bits of data from the slave to the master.
DATO - LSI·II bus transaction that transfers sixteen bits of data from the master to the slave.
DATO(B} - LSI-II bus transaction that transfers eight bits of data from the master to the slave.
DMA - Direct memory access for transferring blocks of data without program intervention.
DMA transaction - A microprocessor transaction during which the microprocessor gives up bus mastership to another device for direct transfer of memory data.
EIA R8-232C - Electronics Industries Association serial line interface standard.
EIA RS-423 - Electronics Industries Association serial line interface standard.

Fetch/read - Microprocessor transaction that transfers data from memory or I/O into the microprocessor.
The data may be an instruction (fetch) or an operand (read).
Firmware - The programs that reside in the PROM or ROM hardware.
FPLA - Field programmable logic array. Used to decode memory addresses.
HALT - The highest priority interrupt. Causes the microprocessor to go to the restart address and loads
the PSW with 340.
Handshaking protocol - The series of events used to establish data transfers.
IAK - Microprocessor transaction to acknowledge an interrupt and secure a vector from an on-board
location or from the LSI-II bus.
Interrupts - Interruption of the normal program execution to service an external request.
Interrupt protocol - Signal sequence required to initiate and service interrupts.
Interrupt vector - The location in which the address of the interrupt service routine is stored.
IRQ4 - See BIRQ4

KXTt l-A2 - See Macro-ODT.
KXTl J-AS - Sec Macro-ODT.
LSla II bus - An asynchronous bus that provides interconnections for LSI-II type modules.
Macro-ODT - The KXT11·A5 and KXTII-A2 optional firmware for the SBC-ll/21 PLUS.
Maskable - A priority level that can be inhibited by loading the PSW with a higher priority code.
Memory mapping - Creating regions of memory via jumper configurations to determine the on-board
portions and the LSI-II bus portions of memory.
Microcyde - The time necessary to execute one microinstruction. A transaction may use three or four
microcycles.
Mode register - An internal microprocessor register used to define the start and restart addresses.
Nibble - The upper or lower half of a byte that consists of four bits.
Nonmaskable - A priority level that is higher than the level selectable by the PSW.
NOP - A transaction that produces no useful output. It is used to introduce a delay or wait period.
Parallel I/O - Parallel data interface.
Parallel I/O handshaking - Control signals used to establish parallel data transfers.
PARQST - Parallel I/O port A interrupt request.
PBRQST - Parallel I/O port B interrupt request.

G-3

r
f

r
1

PI (priority in) - A microprocessor output signal used to strobe interrupt and DMA requests into the
microprocessor.

Power fail (PFAIL) - A nonmaskable interrupt caused by a power failure that causes the microprocessor
to vector through location 24 to the power fail routine.
Priority - Bits 5-7 of the PSW. Used to define the priority level of the microprocessor.
PSW register - A microprocessor register that contains the processor status word (PSW).
PUP - An input to the microprocessor that controls the power-up sequence. When it is switched from high
to low, the microprocessor power-up sequence is initiated.
RAM - Random access memory defined as read/write memory.
RAS - Microprocessor output used as an address strobe in read/write, IAK, and DMA transactions.
RCSR - Serial line receiver control status register.
ROBR - Serial line receiver data buffer register.
ROL t - Serial line receiver number I interrupt signal.
ROLl - Serial line receiver number 2 interrupt signal.
REAOY - Input to the microprocessor that causes cycle slips when pulsed.
Restart address - Jumper~selectable address that the microprocessor jumps to when executing a HALT
interrupt.
REV NT - See BEVNT.
ROM - Read only memory that cannot be written into.
R/-WHB - A microprocessor output that is low for high byte write transactions and high for read
transactions.
R/-WLB - A microprocessor output that is low for low byte write transactions and high for read
transactions.
RTf - Return from interrupt instruction.
SELO/SELl - Microprocessor outputs used to define the transaction being performed.
Serial I/O - Asynchronous serial line units for the transfer of serial data. SLU 1 and SLU2 are two such
units used in the SBC-II/2l PLUS.
Slew rate resistor - A resistor installed on the module that is compatible with the baud rate selected.
Split speed - A process that sends data at one baud rate and receives data ata different baud rate. SBC·
11/21 PLUS does not support split speed operation.

Spurious halts - Halt conditions that are not programmed or introduced from an error condition.
Stack pointer - The register that contains the address of the last word stored on the stack.
Start address - A jumper-selectable address that the microprocessor goes to during power-up.

TCSR - Serial line transmitter control status register.
TDAL 0-15 - Internal on-board bus used for multiplexed data and address lines. See BDAL 0-15.
TDRR - Serial line transmitter data buffer register.
Trace bit - Bit 4 of the PSW that causes a trap to location 14.
Transaction - A sequence of microcycles used to complete a designated microprocessor function such as
read, write, ASPI, or IAK.
Tri-state - A high impedance condition of the bus lines.
Vector address - Memory location the microprocessor accesses for the address of the interrupt service
routine during an interrupt.
Wait state - A condition during which the microprocessor performs no useful transactions while waiting
for a response or data.
Wake-up circuit - Holds BOCOK negated for 70 ms after dc power has been applied.

G-5

APPENDIX H

SBC-II/21 PLUS
AND SBC-ll/21
DIFFERENCES

H.l

INTRODUCTION

This appendix is primarily for a current user of the SBC· t 1/2 t who is either considering or in the process
of using the SBC-II /21 PLUS, instead of the SBC-li /21.
H.2
OVERVIEW
SBC·II/21 PLUS is an enhanced SBC·II/21. The differences between SBC·II/21 and SBC-II/21
PLUS are as follows:

H.3

On-board RAM. SBC-ll/2l PLUS is shipped with 16Kb of SRAM, increased from the 4Kb
shipped with the SOC-l 1/21.

In order to make use of the additional RAM on the SBC-II /21 PLUS, new memory maps are
used selected by the FPLA located in socket XE41. (See Figure I-I.)

Two of the new maps make provision for the Macro-ODT ROMs sold as option KXTII-A5.
These now reside in memory from octal 164000 to 174000.

If the KXTII-AS option is installed in socket set A and the FPLA shipped with the SOC-tI/2l
PLUS (installed in socket XE41) is used, then the SBC is configured for the SBC-li/21 PLUS
mode. If the KXTII-A2 option is installed in socket set A and the optional FPLA (option 2377C6·00) is installed in socket XE41 (see Figure 1·1), then the SOC is configured for the SOC·
11/21 mode. This enables the user to operate the SOC~ II /21 PLUS with the same memory
maps as the SOC-l 1/21, but restricts its operation to the same amount of on·board memory and
the same storage devices as the SBC-II /21.

Additional mass storage devices are supported on the SBC-li/21 PLUS with the KXTll·A5
option. RLOI/RL02 and RD51/RX50 in addition to TUSS and RXOl/RX02 mass storage
devices.

The non-JEDEC pinout memories are no longer supported on SBC-Jl/21 PLUS. Not used on
the SOC-Il /21 PLUS are 1K X 8 memory chips.

Up to 16Kb of additional SRAM may now be plugged into socket set B.

A number of changes have been made to the wirewrap pins. They have been simplified where
possible, with provision made for some larger memory devices.

OPTIONAL FPLA

The SBC-tI/2l PLUS is shipped containing an FPLA in socket XE41. This creates the four memory
maps shown in Figure 2-7. It maps in the memory devices (l6Kb) designated E33 and E40. The coding for
this FPLA is found in Table H-I, and may be contained in a device such as the Signetics 82Sloo. If the

Table H-I

FPLA Code for the SBC-I1/11 PLUS
*A LLLLHLLL

llllll

5432109876543210

*p 00
*p 01
*p 02
*p 03
*p 04
*p 05
*p 06
*p 07
*p OS
*p 09
*p 10
*p 11
*p 12
*p 13
*p 14
*p 15
*p 16
*p 17
*p 18
*p 19
*p 20
*p 21
*p 22
*p 23
*p 24
*p 25
*p 26
*p 27
*p 28
*p 29
*p 30
*p 31
*p 32
*p 33
*p 34
*p 35
*p 36
*p 37
*p 38
*p 39
*p 40
*p 41
*p 42
*p 43
*p 44
*p 45
*p 46
*p 47

*1 -H--HHH---HHH--L
*1 -H--HHH---HHH--H
*I -HHHHHH---HHLHH*I -HHHHHH---HHLHL*1 -HLHHHH---HHLH-*1 -H-HHHH ... --HHLL-*1 -H-LHHH---HHL--*1 -H--LHH---HH---*1 -H--HHH---HLH--*! -HHHHHH---HLLH-*1 -HLHHHH---HLLHH*1 -HLHHHH---HLLHL'III -H-HHHH---HLLL-*I -H-LHHH---HLL--'III -H-HLHH---HLH--*1 -H-LLHH---HLHH-*1 -HHLLHH---HLHL-*1 -HLLLHH---HLHLH*1 -HLLLHH---HLHLL*1 -H--LHH---HLL--*1 -H---LH---H----*1 -L-----HHH-----*1 -H----H---L----L
*1 -H----H---L----H
*1 -H----L---H----L
*1 -H----L--------H
*1 -H----L---L----L
*1 LL-----HHL-----L
*1 -L-----HHL-----H
*1 HL-----HHL-----L
*1 LL-----LH------L
*1 LL-----LH------H
*1 HL-----LH------L
*1 HL-----LH------H
*1 LL------L------L
*1 LL------L------H
*1 HL-----LL------L
*1 HL-----LL------H
*1 HL-----HL------H
*1 HL-----HLL-----L
*I HL----LHLH-----L
*1 HL----HHLHL----L
*1 HL---LHHLHH----L
*1 HL---HHHLHHL---L
*1 HL--LHHHLHHH---L
*1 HL--HHHHLHHHL--L
*1 HL--HHHHLHHHH--L
*1 ----------------

H-2

*F 'A •••••••
·F • •••• A ••
*F • ..... A ••
*F • .1\ • ••••
*F • •••• A ••
"'F • •••• A -. •
*F • •••• A ...
*F ....... A ••
*F • ...... A ••
*F • •• •• A. "
*F • ..... A ••
*F ....... A.
*F ...... A;t •
*F • ••• • A ••
*F • .... • A ••
*F • ..... A ••
*F • ••• • A ••
*F ..... • A ••
*F • • • A ••••
*F
A ••
*F
A ••
*F .... •• A ••
*F .A ••••••
*F • •••••• 1\
*F .A .......
*F • ........ A
*F • ••• • A ••
*F A. •••••••
*F • •••••• A
*F • •••• 1\ ••
*F • •••••• A
*F A •••••••
*F • •••• A ...
*F .1\ • •••••
*F • ••• • A ••
*F .A ........
*F • •••••• A
*F A. •••••••
*F .1\ ••••••
*F A •••••••
*F A•••••••
*F A •••••••
*F A•••••••
*F A •••••••
*F A •••••••
*F A •••••••
*F ..... • A ••
*F
...

•

•••

... •

·........

user wishes to support the memory maps which are provided on the SBe· 11/21 (Figure H~ l)~ then either
option 23-77C6-00 may be purchased from Digital or the FPLA code in Table H-2 may be coded into an
818100. If this mapping scheme is used then it should be noted that only 4Kb of the on-board memory will
be available to the user.
Additional mapping schemes are possible but not supported by Digital.

MAP 0
64KB

MAP 1
64K B

128 BYTES

{NOTE 21
(NOTE 1)
> 4KB
SOCKET A

621<8
58KB

(NOTE 1)
62KB
58K 1$

LSI-l1 BUS

56KB

62K B
14KB
SOCKET B

MAP3

MAP2
64K B

581< B

128 BYTES
(NOTE 2)
(NOTE 1)
4KB
SOCKET A

56K B

64KB
LSI-ll BUS
(NOTE 1)
62KB
14KB
SOCKET B

58KB
56KB

SKB
LOCAL RAM
48KB

40KB

48K B

16KB
SOCKET B

40KB

48KB

16KB
LOCAL RAM

32K B

32KB

LSI-11 BUS

40K B

32K B

48K8

40KB

128 BYTES

32KB
SOCKET A

32K8

(NOTE 3)

241< B

16KB

8KB

OKB

LSI-11 BUS

16KB

24K B

32K8
SOCKET A

LOCAL RAM

16KB

16K B

aKB

8K B

OKS

24KB

16K8
SOCKET B

aKB

16KB
LOCAL RAM

OKB

NOTES;
1. THIS SECTION CONTAINS THE LOCAL I/O ADDRESSES FOR THE SLUS AND
PPI. All UNASSIGNED ADDRESSES ARE ASSUMED TO RESIDE ON THE lSI·11 BUS.
2. ADDRESSES 177777·177600 IN MAPS 0 AND 2 ARE RAM SCRATCHPAD
LOCATIONS USED BY MACRO·ODT.
3. ADDRESSES 77777 - 77600 IN MAP 2 ARE AllOCATED TO THE lSI-l1 BUS.

Figure H-\

SBC·lf /21 PLUS Memory Maps

H-3

Table H-2 Option 23-77C6-00 FPLA Code

*P 00
*p 01
*P 02
*p 03
*p 04
*p 05
*p 06
*p 07
*P 08
*P 09
*P 10
*P 11
*p 12
*p 13
*p 14
*p 15
*p 16
*p 17
*p 18
*p 19
*p 20
*p 21
*p 22
*p 23

*p 24
*p 25
*p 26
*p 27
*p 28
*p 29
*p 30
*p 31
*p 32
*p 33
*p 34
*p 35
*p 36
*p 37
*p 38
*p 39
*p 40
*p 41
*p 42
*p 43
*p 44
.p 45
*p 46
*p 47

Hllll
5432109876543210

LLLLLLLL

*1 -H--HHH---HHH--- *F
*1 -HHHHHH---HHLHH- *F
*1 -HHHHHH---HHLHL- *F
*1 -HLHHHH---HHLH-- *F
*1 -H-HHHH---HHLL-- *F
*1 -H-LHHH---HHL--- *F
*1 -H--LHH---HH---- *F
*1 -H--HHH---HLH--- *F
*1 -HHHHHH---HLLH-- *F
*1 -HLHHHH---HLLHH- *F
*1 -HLHHHH---HLLHL- *F
*1 -H-HHHH---HLLL-- *F
*1 -H-LHHH---HLL--- *F
*1 -li-HLHH---HLH--- *F
*1 -H-LLHH---HLHH-- *F
*1 -HHLLHH---HLHL-- -F
*1 -HLLLHH---HLHLH- *F
*1 -HLLLHH---HLHLL- *F
*1 -H--LHH---HLL--- *F
*1 -H---LH---H----- *F
*1 LH----H---L----L *F
*1 HH----H---L----- *F
*1 LH----H---L----H *F
*1 -H----L---H----- *F
*1 -H---HL---L----- *F
*1 -H---LL---LH---- *F
*I -H--HLL---LL---- *F
*1 -H--LLL---LLH--- *F
*1 -H-HLLL---LLL--- *F
*1 -H-LLLL---LLLH-- *F
*1 -HHLLLL---LLLL-- *F
*1 -HLLLLL---LLLLH- *F
*1 -HLLLLL---LLLLL- *F
*1 -L-----HHL------ *F
*1 -L-----LHH------ *F
*1 -L-----LHL------ -F
*1 LL-----HL------- *F
*I HL-----HL------L *F
*1 HL-----HL------H *F
*1 LL-----LL------L *F
*1 HL-----LL------H *F
*1 HL-----LLH-----L *F
*1 LL-----LLH-----H *F
*1 HL-----LLL-----L *F
*1 LL----HLLL-----H *F
*r LL----LLLL-----H *F
*1 -LLLLLLHHHLLLLL- *F
*I -L----LHHH------ *F

• ..... l\ .• ...
• ..... ,. A ••
•• A.A •••
..... • A ••
• ••• • A ••
• •••• A ••

• •••• A ••
• ••• • A ••
• • '" • ,. A ••

• ••• • A ••

•••• A."A.
• ••• • A ••

A ••
• ..... A ••
• • '• •• A ••
;Ii

...

••

• ..... A ••
•

•••

oil

A ••

• •• AA •••
• •••• Ii ••
• •••• A ...

.A •• A •• A
• •••• Ii. ••
.... ... A ••

A••• A •••
A ••• A ...
A ••• A.
1/1

II!

•

A ••• A •••
A ••• A •••

A••• A•••
A. ••• A •.• ,.

A ••• A •••
'A ••• A•••
• •••• A ••

• •••• A. ••
• •••• A ••
• ..... A.
1/1

• •••• A ...
• •••• 1\ ••

.A •• A • ...
• •• *' • /4~ ••

• • •• A •• A
• A ... A •••
• •••• A ••
....... A •• A
.1\ •• A •••
... ... A •• 1\

• ..... A ••

A••• A •••

H.4
MEMORY MAPS
The memory maps used in the SBC-ll/21 PLUS are shown in Figure 2-7. These are replaced by those
found in Figure H-l if the optional FPLA (option 23-77C6-00) is used.
H.S
KXTII-A2 AND KXTll-AS MACRO·ODT ROMS
If the user wishes to use the SOC-li/21 PLUS memory maps and desires to have the capability of using
either RLOI/RL02 or RD51/RX50 storage devices in the system, then the KXTlI-AS optional ROMs
should be used. The ROMs are mapped in addresses 164000 to 173776 (octal) when using either map 0 or
map 2. The code resides in two 2K X 8 memory chips. It is important to note that the code for addresses
164000 to 167776 is contained in the UPPER address space of the chip, and the code for addresses
170000 to 173776 is contained in the LOWER address space of the chip.
For those users who wish to maintain the SBC-II /21 memory maps and who do not wish to use either the
RLOl/RL02 or the RD51/RX50 storage devices, the KXTII-A2 ROMs should be used. The ROMs are
mapped in addresses 170000 to 173776 (octal) when using map O.
For detailed configuration help, consult either the KXT1i-AB SBC-il /21 PLUS Configuration Guide or
Chapter 2 of this manual.
H.6
MEMORY DEVICES SUPPORTED
Devices now supported by the SOC-II /21 PLUS are listed in Tables 2-10 and 2·11. The non-JEDEC
standard pinout memories as well as all 1K X 8 chips are no longer usable with the SBC·ll /21, when
configured in any mode.
Devices no longer supported on Tables 2·10 and 2-11 are:
Socket set A:
EPROMs
INTEL

2758

lK X 8

TMS2508

IK X 8

TMS2564

8K X 8

INTEL

3628

IK X 8

SIGNETICS

82LS181

lK X 8

INTEL

2758

lK X 8

TMS2508

lK X 8

TMS2564

8K X 8

PROMs

Socket set B:
EPROMs

H-5

PROMs
INTEL

3628

lK X 8

SIGNETICS

82LS181

lK X 8

This applies when the SSC~11/21 PLUS is used in either SOC·! 1/21 PLUS or SBC-1Ill!. Examples of
memories supported by SOC-tI/2l PLUS are found on Tables 2-10 and 2-11.
H.7 WIREWRAP CONFIGURATION COMPARISONS
In total, there are (our fewer wirewrap pins on SOC-tI/2l PLUS than on SBC-tI/2l. While eighteen of
the functionality pins have been removed, seven have been added to accommodate additional memory
chips and seven ground or power pins have been added. Some of the functionality pins were incorporated
within the Gate Array (E20) and thus are unreachable.
Table H-3 lists the functional equivalent pins for the SSC- t 1/21 PLUS as compared to the SOC-ll/21.
Those posts on SBC-tI/21 that are no longer available are;
Clock system input
M2
M9
-IAK output
-CTMER interrupt request input
MIO
MIl
Clock osc. output
M14
TMER (timeout error) output
READ H strobe
M31
M43
Socket set A, high and low byte. pin 2
Socket set A, high and low byte, pin 22
M60
M38
Socket set A, high and low byte, pin 20
M47
Sockets A and B, high and low byte, pin 21
M4t
Socket set A, chip select (-CSKTA)
M45
Address line II
M34
Socket set S, chip select (-CSKTS)
M42
Socket set S, high and low byte, pin 2
Socket set H, high and low byte, pin 22
M62
Socket set B, high and low byte, pin 20
M32
M36
Address line 13
Read strobe (-READ)
M64

H.8 RT-ll ON SBC-H/lt PLUS
The SOC-I 1/21 PLUS supports RT-Il V5.1, and supports either the RT-ll(SJ) or the RT-Il(FS)
monitor. Additionally, SOC-1l/21 PLUS when operated in SHC-1l/21 mode can also run RT-Il(FB).
H.8.1

SBC-H/21 PLUS and RT-ll(SJ) (SBC-H/21 PLUS mode)

The SHC-lI/2l PLUS should be configured with socket set B containing 8K X 8 SRAMs. Memory map 2
is normally used so that on-board memory is mapped in between 0 and 100000 (octal). If more than 16Kb
of memory is desired when running RT-ll(SJ) then map 0 may be used as for the FB monitor below. The
KXTII-A5 option should be plugged into socket set A to support RT-Il. In this arrangement SOC-l1/2l
PLUS can boot from RXOI/RX02, TUS8, RLOI/RL02 or RD51/RX50.

H-6

H.S.l SHC-1l/1l PLUS with RT-ll(FB) (SBC-Il/l"l PLUS mode)
The SBC-lI/21 PLUS should be configured with socket set B containing 8K X 8 SRAMs for a full 56Kb
RT-ll(FB) system. Memory map 0 is required. The KXTI1-AS option should be plugged into socket set
A. In this arrangement SBC-lI/21 PLUS can boot from RXOI/RX02, TUSS, RLOI/RL02 or
RD51/RXSO. A Q-Bus memory board must be resident on the Q-Bus mapped into the memory space 0 to
100000 (octal).
H.S.3 SOC-Hill PLUS with RT-H(FB) (SOC-Hill mode)
The optional FPLA (21-77C6-00) should be inserted in the socket XE41. This, along with the KXTII-A2
option in socket set A will put the SBC-11/21 PLUS into the SBC-11/21 mode. Memory map 0 should be
selected and socket set B is unused. There must be a minimum of 56Kb of memory on a memory module
plugged into the Q-Bus and mapped into the space 0 to 160000. In this set-up the SBC-II/21 PLUS will
emulate an SBC-lI/2l in that the SBC-1l/21 memory maps will be available. The amount of memory
on-board the SOC-1l/21 maps in will also be the same; Le. only 4Kb of the on-board 16Kb of RAM
available is utilized.

H.9 SBC-ll/ll PLUS AND MICROPOWER/PASCAL
SBC-lI/2l PLUS supports Micropower/Pascal VLS. A current application built under VI.4 or earlier for
running on SBC-ll/21 will NOT run as is. In order to run an existing or new application on SOC-1l/21
PLUS, it must be built under Version 1.5. When building, the only difference between SBC-tI/2l PLUS
and SBC-11/21 is that it is necessary to specify "PROCESSOR type=T-ll+" in the configuration file.
Note that the KXTll macro options are unchanged. If T·ll is selected as the processor type, the
application will get built for running on either an SBC-lI/2l or an SBC-lI/21 PLUS operating in SBC11/21 mode. (See the definition of SBC-tI/2l and SOC-lI/2l PLUS modes in Section H.3.)

H-7

Table H-3 FUJK:tional Equivalent Pins (Cont)
Appendix F
Schematic
SOC-Hill

Sheet

PLUS

SBC-ll/ll

Ml
M2
M3
M4
MS

Ml
M3
M4
M5

2
2
3
3

M7
M8
M9
MIO

M7
M8
MI8

5
3
6
5

Mll
MI2
MI3
M14
MiS

M24
N/A

N/A
MIS

MI6
M17

Ml6
M17

S
6

MIS
Mt9
M20

M50
M19
M20

2
6
3

M21
M22
M23
M24
M25

M26
M27
M28
M29
M30

1
6
6
I

Start address control (TDAL ! 4)
50 Hz real-time clock output
800 Hz real-time clock output
System GND
Start address control (TDAL 13)

M31
M32
M33
M34
M35

M51
M55
M33
N/A
M35

3
I
5
5
5

System GND
System GND
Socket set B, high byte, pin 27
Highlogic level (+5 VCR)
Socket set B, low byte, pin 23

Mi2

N/A

Number

Description

System +5 V power (+5 VNCR)
System GND
High logic level (+3 Vdc)
Wake-up circuit diode, anode side
Receive side of BHALT line transceiver
Wake up circuit diode, cathode side (+5
VNCR)
Socket set A, high and low byte. pin 26
BREAK request clock line
High logic level (+3 Vdc)
Address line 14
System GND
High logic level (+5 VNCR)
Socket set B, high and low byte. pin 1
Socket set A, high and low byte, pin 1
+5 Vdc power distribution to support static
RAM

5
5
S

Battery backup +5 Vde power source
Serial line unit (SLU) 1 BREAK detect, interrupt request output
High logic level (+3 Vde)
60 Hz real-time clock output
Transmit side of BHALT line transceiver
Memory map select (MSB)
Start address control (TDAL IS)
Transmit side of BEVNT line transceiver
System GND
Memory map select (LSB)

6
5
2

H-8

Table H-3

Functional Equivalent Pins (Cont)

Appendix F
Schematic
Sheet
Number

SHC-H/2l
PLUS

SBC-H/21

M36
M37
M39
M40

N/A
M37
M39
M40

M41
M42
M44
M46

N/A
N/A
M44
M46

M48
M49
M50
M51
M52

M53
M54
M55
M56
M57

7
7

M58
M59
M61
M63
M64

M58
N/A
M61
M63
N/A

7
5
5

Port C PC4 output (8255A-5 pin 13)
Socket set B, high and low byte, pin 28
Socket set A, high byte, pin 23
Socket set B, high byte, pin 23
RAM, high and low byte, pin 26

M65
M66
M74

M65
N/A
M13

7
5
I

Port C buffered output, to J3 pin 5
Socket set B, high and low byte, pin 26
HALT request line

5
5

5
5
5

5
5
5
5
7

7
7

5
5

Description
High logic level (+5 VNCR)
Socket set A, low byte, pin 27
Socket set A, high byte, pin 27
Socket set A, low byte. pin 23
High logic level (+5 VCR)
Address line I 5
Address line 12
High logic level for PROMs (+5 VNCR)
Socket set B, low byte, pin 27
Port B buffer direction control
High logic level (+ 3 Vde)
System GND
Port A buffer direction control
Port C buffered output, to -'3, pin 7
Port C PC6 output (8255A-5 pin II)
System GND
High byte write strobe (-WHB)
Low byte write strobe (-WLB)

N/A means no longer available on the SBC-II /21 PLUS.

INDEX

AD01-ADI5, 8-21
Addressing modes, 7-1
A 10-07 • 8-15
Architecture. 5-1
ASPI. 8-8
Autobaud. 6·1

CAS, 8-5
Clock,8-28
Clock controi, 8-29
Condition codes, 7-28
Configuration. 2-3, 2·5
Control register, 6-22
Control word, 6-22. 6-23
COUT.8-6
CSKTA,8-21
CSKTB,8-21
CTMER, 2-8, 5-5
Cycle slip, 8-33

B
Backplane, 2-22
BBS7, 9-4, 9-20
BCLR, 8-6, 8-25
BOCOK. 8-28, 9-17
BDIN, 9-19
BDMGI, 9-8. 9-20
BDMGO. 9·10. 9-20
BDMR, 8·29, 9·17
BDOUT, 8-32, 9· t 8
BEVNT, 2-11, 5-5, 9-18
BHALT, 2-9, 5-5, 9-17
BINIT, 9-20
BIRQ4. 2-11, 5·5, 9-19
BKRQ, 2·11, 5-5
Bootstrap, 4-6
BPOK, 8-28, 9-17
BREAK,6-1
BRPl y, 9-19
BSACK.9·18
BSYNC, 9-19
Bus control, 8·33
Bus cycle, 9-3
Bus signals, 9· J. 9-3
BWTBT, 8-31, 9-19
Byte, 7-25, 8-23, 8-31

D
Data transfer, 9-3
DATI,9-5
DATO,9-8
DATOB,9-8
Dererred addressing, 7-14
Direct addressing, 7-4
DMA, 5-4, 8·29, 9-8
DMA bus master, 9-8
DMA transaction, 9-8
Double operand address, 7-41

E
EIA RS-232C, 2-25
ErA RS-423, 2-25

F
Fetch/read, 8-6
Firmware, 4-1
FPLA,8-21
Framing error, 6-5
Functional block diagram, 8·2, 8-3

INDEX-l

HALT, 5·5. 8-19
Handshaking protocol. 6-25
Hardware memory stack, 5·2

IAK. x-!o\
Initialization. 8-1. 9-14
Instruction set, 7-22
Instruction set list. 7·16
Intcrrupts. 2-8. l:\-14
Intcrrupt protocol, 9-12
Interrupt set/reset, 8-8. 8-16
Intcrrupt vector. 5-4. 8-17
IRQ4. 8·15
J

p
Parallel I/O. 6·7

Parallel I/O flowchart, 6·9
Parallel I/O handshaking, 6-25
Parallel I/O initialization, 6·25
PARQST. 5-5. 8-17
PBRQST, 5-5, 8-17
PC addressing. 7-17
PI (priority in). 8-5
Power fail (PFAIL), 8-19
Power fail routine, 8-\9
Power-up/down protoco!. 5-4, 8-27. 9-15
Ports A, B. C 6-8
Priority. 5-2
Program counter (PC), 7-17, 8-1
Programmable baud rates, 6-1
Programmable baud rates select, 6-6
PSW register. 5-\
PUP, 8-4

Jumper wire. 2-1
R
K
KXTII-AS.4-\

Loopback connector. 2-28
LSI-l I bus. 9-1
M
Macro-ODT, 4-\
Macro-ODT commands, 4,3
Maskablc. 5-4
Memory maps, 2-16. 2-19. 5-6
M icrocyclc, 8-6
Microcyclc slip. 8·\7
Microprocessor, 8-1
Mode 0,6-10
Mode \,6-11
Mode 2. 6-18
Mode selection, 6-22
N

Nibble. 6-1 I
Nonmaskablc, 5-4
NOP.8-8
()

Overrun error, 6-4

RAM. 2-16, 8-21
RAS.8-5
RCSR.6-3
RDBR.6-3
RDLI, 5-5. 8-17, 8-23
RDL2, 5-5.8-17, 8·23
Read. 8-6
Read/write. 8-5. 8-3\
READY. 8-5

Reply time-outs, 8-\9
Restart address, 8-14
REVNT. 8-15. 8-17
ROM, 2-16, 8-21
R/-WHB.8-5
R/-WLB.8·5

RTf. 7-64
S
SELO/SELl, 8-5
Serial I/O, 2-12. 6·1, 8-23
Single operand address. 7-3
Slew rate resistor. 2·25
SLUljSLU2, 6-1, 8·23
SLU programming. 6-\
Split speed, 6·1
Spurious halts, 4-9
Stack pointer, 5-\
Standard factory configuration, 2-7
Start address. 2-8
Status register, 5-1

INDEX-2

I
i

TCSR,6-3

TOAL,8-1
TDBR,6-3
Terminal problems, 4-9

TMER,8-33

TSYNC, 8-31
Transactions, 8-6
Transmitter interrupt enable, 6-5
Tristate, 8-8

Unsupported options, 3-6

I
i
I

Vector address, 5-4
Verification procedure. 2-28

w
Wake-up circuit. 8-27
Write transaction, 8-8

x
XOLl, 5·5, 8-15. 8-23
XOL2, 5-5, 8-15, 8·23
XTLO/XTL t, 8-28

.,.