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EK-VTTAA-TM-001

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Document:	VAXstation 2000 and MicroVAX 2000 Technical Manual
Order Number:	EK-VTTAA-TM
Revision:	001
Pages:	434
Original Filename:

OCR Text

VAXstation 2000
and MicroV AX 2000
Technical Manual
EK,VTTAATiJ

VAXstation 2000and MicroVAX2000
Technical Manual
Order Number EK-VnAA~TM~001

dlgita! equipment corporation
maynan:i\ massachuse.tts

First Edition, July 1987
The information in this document is sul:tject to change without notice and should not be
construed as a commitment .by Digital Equipment Corporation.
Digital Equipment Corporation assumes no responsibility for any errors that may appear in
this document.
The software, if any, described in this document is furnished under a license and may be used
or copied only in accordance with the terms of such license. No responsibility is assumed for
the use or reliability of software or equipment that is not supplied by Digital Equipment
Corporation or its affiliated companies.
Copyright ©1987 by Digital Equipment Corporation.
All Rights Reserved.
Printed in U.S.A.
The following are trademarks of Digital Equipment Corporation:

BASEWAY
BI Bus
CompacTape
DEC
DEC/MAP
DECmate
DECnet
DECUS
DECwriter
DIBOL
FMS

MASSBUS
Micro/RSTS
Mlcro/PDP-ll
Micro/RSX
MicroVAX II
MicroVAX 2000
PDP
P/OS
Q-bus
Rainbow
RSTS

RSX
ThinWire
ULTRIX-ll
VAX
VAXduster
VAXstation II
VA.Xstation 2000
VMS

mDmDamO

Contents
About This Ma,nua!
~~apter 1

----,_._---

~--------,

System Introduction

1.1

VAXstatlon
VS410 Systern Box
1,1.2
Video Monitor. ""

, 1-·]

1-2

1.1.1

LK201

" .. ,.,

""""

, .. , , . . .

1··2

.', , ., , ... ,.... ,

VSXXX Mouse, , , . , . , , . , , ... , . , .. , , . , , .. ,
1··3
MkmVAX 2000 :--.\t<~t"'f'Yl
1",3
1.2,1
V5410 System Box " " . . . . ' . "
..' . '
. . " .. . 1-3
L!.2
Video Console T ermina! , . , , . . . , . . . . . . . . . . , , , , ..
1
LK201 Keyboard ., .. , .. ,.,., .. , ' " . , . , . " . , ,
13 Physical Characteristics . . ' , , .. " . . . . . . , , , . . , .. "
, 1-4
1.3.1
Systen1 Box, . , , . . . . . . . , . , , ... , ....' . . . .. ."
1-4
1.3,1.1
KA.410 System l\1odule .. " . . . . . . . ,.. . ... ',., 1-5
Network lnh?rronnect Module . . .. . . . . . . . . . . ,.,.
1.3
M5400 Memory Module. . . . . . . . . .. '"
.. ,.'" 1·5
1.3.1.4
Power Supply, . . .
... " '. . .....,.... .. 1 .. 5
'} 15
RX33 Diskette Drive ,. "
' . . . . . , . . . . . . . . . . . 1--6
1 1.6
RD32
Drive. . . . . "
,,'. ......
" , , , . . 1··6
.I
DEC423 Convertt~1' (MkroV1''\X :WOO,\. , ,. . ' . . . . . .
1-6
1.31.8
Resistor Load. r..1odu!e. .,.. .'..,,' . . . " . . . , ' . 1" 6
BA40BExpanston
..... " , . . . . . . . . . . . . . , . 1-6
1
RD53 Disk [JrfV€ ~ ~ .. ~
~
~
~
'1,"'"' 7
TZK50 Contf(~Uer Boa.rd . . . . . " . . . . . . . . . . , . . '
1-7
1
1,1.4

1.2

1
1
1.3.3.1

.,.

•

TK50 Tape DrivE' ",.,',"
...,...,.... .,.. '"
BA40A Expanskm
...... , .. ,
}.. 7
D'lsk Interface. ~1ociuJe . , . ~ ., ~ ~ " . ~ ~ " ., ~ " ~ " , , 1. ~",-7

Iii

OVerV!€HN

Central Processor
. . . . . . . . , ... 2··1
System Memory .
Time-Of-Year
2-·~7
DC524 Standard Cell . . . . . . . . . . . , .... .
2-8
DC503 Cursor Sprite Chip.
2··10
Line Controller ..
2-10
9224 Disk Controller . . . . . . . . . .
2-13
5380 Tape Controller
2-·15
Thin \'\'ire Ethernet

2A
2.5
') tl
"
...

.2.7
2.8
2. 9

Chapter 3

VS410 ,System Module Detailed Description

~
'1
.....,. • ..J.

introduction.,.
3-1
Central Processor . . . . . . .
Chip
3·-4
Descriptions _ . . . . . , . _
32.1.1
3-11
L2
3-14
H.egisters .
Status Long-vord
3.2L3
3·114
3.2.1,4
Internal Processor
(IPR) . . . . . . . . . . . . . . . . 3···14
. . , , . , .... , .. J ..
3.2.1.5
Interrupts and Exceptions .
3.2.2.1

3.2A
3 :;
3.2.5.1

3·27
FPUfCPU C:omrmmic,ltions Protocol. , ..
40 MHz CPUIFPU
DlvL'\ Bus Access

3-29
3·30

3.. 30
3·32

3.2.5.3

504
5.5
6

3.. 28

Table Entry.,

3.2.6
Processor Restarts ........................... 3-37
Power-On Restart . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
3.2.6.1
HALT Restarts ............................ 3-39
3.2.6.2
3.2.6.3
HALT Code Register (HLTCOD) ................ 3-39
3.3 System Memory ........................ . . . . . . 3-40
3.3.1
RAM Memory .............................. 3-41
3.3.1.1
System Module RAM ....................... 3-41
3.3.1.2
Video RAM .............................. 3-43
3.3.1.3
Option Module RAM . . . . . . . . . . . . . . . . . . . . . . . . 3-44
3.3.1.4
Memory Parity Checking ..................... 3-44
3.3.1.5
Memory System Error Register (MSER) ............ 3-44
3.3.1.6
Memory Error Address Register (MEAR) . . . . . . . . . . . 3-46
3.3.2
ROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
3.3.2.1
System Module ROM ....................... 3-47
3.3.2.2
ThinWire Ethernet Address ROM ................ 3-53
3.3.2.3
Option Module ROM. . . . . . . . . . . . . . . . . . . . . . . . 3-54
3.4 Time-of-Year Clock (fOY) ........................ 3-58
3.4.1
Watch Chip Theory of Operation .................. 3-60
3.4.2
Watch Chip Registers . . . . . . . . . . . . . . . . . . . . . . . . . 3-62
3.4.2.1
Control and Status Registers . . . . . . . . . . . . . . . . . . . 3-64
3.4.2.2
Date and Time-of-Year Registers ................ 3-66
3.4.3
Non-Volatile RAM Storage ...................... 3-67
3.4.3.1
Console Mailbox Register (CPMBX) .............. 3-68
3.4.3.2
Console Flags Register (CPFLG) . . . . . . . . . . . . . . . . . 3-69
3.4.3.3
Keyboard Type Register (LI<201}D) .............. 3-70
3.4.3.4
Console Type Register (CONSOLE}D) . . . . . . . . . . . . 3-71
3.4.3.5
Scratch RAM Address Registers (SCR) ............ 3-71
3.4.3.6
Temporary Storage Registers (fEMPn) ............ 3-71
3.4.3.7
Battery Check Data Registers (BATSHK) ........... 3-71
3.4.3.8
Boot Device Registers (BOOT.DEV) .............. 3-71
3.4.3.9
Boot Flags Registers (BOOTlLG) . . . . . . . . . . . . . . . . 3-72
3.4.3.10
Scratch RAM Length Register (SCR.LENGTH) ....... 3-72
3.4.3.11
Tape Port Information Register (SCSI). . . . . . . . . . . . . 3-72
3.4.4
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73
3.4.5
Battery Backup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73
3.5 DC524 Standard Cell . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-74

35.1
1
3.5.2.2
.,
-'.
3.5.2.4
3.5.3

3.5.3.1
353.3
3.5.4
3.5.4.1
3.5.4.2
3.5.4.3
4
3.5A.5

35.4.6
3.5A.. 7

3S48
3

PCl',ver-\"}p Initialization
3-84
t.lemory Control ....
Multiplexed Address
Mernory Control Signals. . . . , .. ,
3-86
~temory and Peripheral
3····90
Control of
Cycle Slips ..' . . . . . . . . . . . . . . . .
Video Control . . . . . . . . . . .
. . , . . . . . . . . . . . . . 3-90
Video Shift Hegister Update and RAl\J Refresh. . . . . . . 3.90
Video Timing Diagrams . . . . . . . . . . . . . . . . . . . . . .
Video RAl'v1 and Cursor Data Combination and Output
3~92
Input!Output
.... ,.
. .... , . . .
95
Configutation and Test Hegister Enable
3·95
System RO~vl Enable (ROMCS)
.......... .
Ne!:"'lork
ROM Erwble (NfROIlAENA)
Video Option ROl\·f Enable (OPTROMENA) .
3-96
TO't' Clock Control
CLKAS, and
3-96
Interrupt
and

(C59224, D59224. ilnd \·VR9224) ..
and

3.5.4.10

11
3.5.4

3 .. 97

Interrupt and Video Controi
Serial Line
Enable

RAT'>'!

Control (DBUFCF.)

EthernetiSID HOtvi Enable
Nehvork Interface Controller Enable (NIENA)
3.5.4.15
Cursor Chip Enable (CURSEL), , ...
.4,]6
Video RAM Enable
and SRAM1)
3.
17
Option Enable (OPTVIDENA) . . . . . . .
3.5.5
Disk Control . . . , . . . . . . . . . . . ' , . , . . .
3.5A.14

1
3.5 5.2
3.5.5.3
.6

IIi

\\'inchester Disks
Common Signals .
Tape Control
Parity Generation and

3-100
3-100
3-100
3-100

3-101
3··101
102
3-102
3-103

(PBIT3:0) . , . , .

104.

)

Interval Timer Interrupt Generation (INTTIM) .,. . . . . . 3-104
3.5.8
Interrupt Controller ........................ . 3-105
3.5.9
3.5.9.1
Interrupt Request Register (INT.REQ) ........... . 3-106
3.5.9.2
Interrupt Mask Register (INT.MSK) ............ . 3-106
3.5.9.3
Interrupt Clear Register (INT.CLR) ............. . 3-107
Interrupt Vector Generation ................. . 3-107
3.5.9.4
3.5.9.5
Interrupt Sources and Ranking. . . . . . . . . . . . . . . . . 3-108
3.5.9.6
Video Interrupt Select Register (\'DC.SEL) ........ . 3-109
3.5.10 Monochrome Video Display Controller. . . . . . . . . . . . . 3-110
Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-110
3.5.10.1
3.5.10.2
End-of·Frame Interrupt ..................... . 3-111
Data Plane Storage ..... . . . . . . . . . . . . . . . . . . . 3-111
3.5.10.3
Display Origin Register (VDC.ORG) ............ . 3-112
3.5.10.4
3.5.11 Test Mode (TEST). . . . . . . . . . . . . . . . . . . . . . . . . . . 3-112
3.5.11.1
Interval Counter. . . . . . . . . . . . . . . . . . . . . . . . .. 3-112
Vertical Timing. . . . . . . . . . . . . . . . . . . . . . . . . .. 3-113
3.5.11.2
3.5.11.3
Video RAM Shift Register Update/Refresh. . . . . . . .. 3-113
3.6 DC503 Cursor Sprite Chip ....................... 3-113
3.6.1
Overview ................................ 3-113
3.6.2
Cursor Coordinate Offsets. . . . . . . . . . . . . . . . . . . .. 3-116
3.6.3
Cursor Generation ........................ " 3-117
3.6.4
Cursor Control Registers . . . . . . . . . . . . . . . . . . . . .. 3-117
3.6.5
Cursor Command Register (DUR.CMD) ............ 3-119
3.6.6
Loading the Cursor Sprite Pattern . . . . . . . . . . . . . . .. 3-121
3.6.7
Cursor Region Detector. . . . . . . . . . . . . . . . . . . . . .. 3-122
3.6.8
Displaying a Sprite Cursor. . . . . . . . . . . . . . . . . . . .. 3-122
3.6.9
Displaying a Crosshair Cursor .................. 3-122
3.6.10 Controlling Cursor Plane Outputs . . . . . . . . . . . . . . .. 3-123
3.6.11 Blanking the Display ................... , ..... 3-123
3.6.12 Cursor Chip Test .................... , , . . . .. 3-123
3.6.13 Power.Up Initialization ....................... 3-124
3.7 Serial Line Controller (DZ Controller) ... , .......... , 3-125
DZ Silo ................................. 3-129
3.7.1
3.7.2
Line Identification .......................... 3-129
3.7.3
Diagnostic Terminal Connection . . . . . . . . . . . . . . . .. 3-131
3.7.4
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-132

vii

3.7.5

Register Summary ., . . . . . . . . . . . " ... , . . . . . '
Control and Status Hegist('f
, , , .. " .. , .
Serial Une ReceIver Buffer
3.7.
3.75.3
Serial Line Parameter Register (SER_LPR). , ... , , , '.
375.4
Serial Line Transmitter Control Hegister
3.7,5.5
Modem Stalus Reglster (SEI(MSR) .... , " , . . . .
3.7S6
Transmitter Data Register (SER_TDR) ' . . . . . . . . ,.,
3.8
9224 Disk Controller. . , "
..... , ,. ,.,." ..... ,
3.8.1
Disk Data
.. . .. .
. , ..... ,
3.8.2
Disk Address Counters
3,8.3
Phase,·Locked Loop. ,
3,8.3,1
Phase
Voltage·Controlled Osciilator (\-'CO) , , ,
3,8.4
Hard Disk Data Bus " . . " .... , , "
3,8.5
Floppy Disk Data Bus . . . .
3.8.6
Controller Chip Organization
1
Disk Controlier Chip Ports
3,8,6,2
Controner Chip J,"::',,,,,,,<,,
3.8.7
Command Overview .. , ... ,
.1
Read lD
3.8.7,2
Verify Sequence
3.8.7,3
Data Transfer Seouem:e
,
38.8
Command
38.8.1
Ji:ESET Command ,
3.8,8,2
FOINTER Command
3.8.8.3
DRIVE Command
3.8,8A
DRIVE SELECT Command ....
3.8 5
DRIVE Command,
:38.86
STEP Cmnmand .
3.8Jt7
POLL DRIVES Cornmand ,. " " "
3.8.8.8
SEEK/RE.AD ID Command
... ,
3,8.8,9
FORMAT TRACK Cor,n,mand ., .... " . '
3.8.8.10
READ TRACK Comrnand .. , , . . . . . . , , .. .
3.8,811
READ PHYSICAL Command .... ,' ..... ,
3.8.8.12
READ
Command . , ... , ..
3,8,8,13
\V.RITE PI-nSICAL Command ... , ..
"

•••

•

viii

••

3-132
3,·'1
3-137
3·1
141
3-142
3,143
3-147

3-148
33-151
3··152

3-154
3-170
172

3.. 174
3 .. 175

3-176
3178

3..·179
3-180
3-lErI
3·182
185
3-·186
187
188

3.8.8.14
WRITE LOGICAL Command ................. 3-190
3.8.9
Write Precompensation ....................... 3-191
3.8.10 Diskette Drive READY Condition ................ 3-191
3.8.11 Disk Programming . . . . . . . . . . . . . . . . . . . . . . . . .. 3-193
. 3.8.11.1
Diskette Motor Control ..................... 3-193
3.8.11.2
Implicit Seeks on Diskettes. . . . . . . . . . . . . . . . . .. 3-194
3.8.11.3
Diskette Write Completion Delay ............. " 3-194
3.8.11.4
Using the Disk and Tape Controllers ............ 3-195
3.8.11.5
Selecting the Diskette Drive .................. 3-195
3.8.11.6
Drive Select Jumpers. . . . . . . . . . . . . . . . . . . . . .. 3-196
3.8.11.7
Spurious Data CRC Errors ................... 3-196
3.8.12 Diskette Drive Overview .................... " 3-196
3.8.13 Hard Disk Drives ........................... 3-197
3.9 5380 Tape Controller . . . . . . . . . . . . . . . . . . . . . . . . .. 3-198
5380 Tape Controller Overview .................. 3-200
3.9.1
3.9.2
SCSI Overview ............................ 3-204
3.9.3
5380 Tape Controller Chip Registers .............. 3-206
3.9.3.1
Mode Register (SCS.MODE) .................. 3-207
3.9.3.2
Initiator Command Register (SCS)NI.CMD) ....... 3-209
3.9.3.3
Target Command Register (SCS.TAR.CMD) . . . . . . .. 3-211
3.9.3.4
Bus and Status Register (SCS.STATUS) ........... 3-212
3.9.3.5
Current Bus Status Register (SCS.cUR.STAT) ...... 3-214
3.9.3.6
Select Enable Register (SCS.SEL.ENA) ........... 3-214
3.9.3.7
Output Data Register (SCS.OUT.DATA) .......... 3-215
3.9.3.8
Current Data Register (SCS.cURPATA) . . . . . . . . .. 3-215
3.9.3.9
Input Data Register (SCS)N.DATA) ............. 3-215
3.9.3.10
Start DMA Send Action (SCSPMA.SEND) . . . . . . .. 3-216
Start DMA Initiator Receive Action (SCSPMA)RCV) . 3-216
3.9.3.11
3.9.3.12
Start DMA Target Receive Action (SCSPMA.TRCV) " 3-216
3.9.3.13
Reset Interrupt/Error Action (SCS.RESET) . . . . . . . .. 3-216
3.9.4
DMA Register Operation ...................... 3-217
3.9.4.1
DMA Address Register (SCD.ADR) ............. 3-217
3.9.4.2
DMA Count Register (SCDSNT) . . . . . . . . . . . . . .. 3-217
3.9.4.3
DMA Direction Register (SCDPIR) ............. 3-219

3.9.5
Tape Controller Interrupts . . . . . . . . . . . . . . . . . . . ..
3.9.5.1
Selection or Reselection . . . . . . . . . . . . . . . . . . . ..
DMA Count Reaches O. . . . . . . . . . . . . . . . . . . . ..
3.9.5.2
3.9.5.3
Bus Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.5.4
Phase Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.5.5
Bus DiscoMect. . . . . . . . . . . . . . . . . . . . . . . . . ..
3.9.5.6
SCSI Tape Bus Reset. . . . . . . . . . . . . . . . . . . . . ..
3.9.6
Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.9.6.1
System Hardware Reset . . . . . . . . . . . . . . . . . . . . .
3.9.6.2
RST Received from SCSI Tape Bus . . . . . . . . . . . . .
3.9.6.3
RST Issued to SCSI Tape Bus . . . . . . . . . . . . . . . . .
Programming Notes . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.7
3.9.7.1
Using the Tape and Disk Controllers . . . . . . . . . . . .
3.9.7.2
Device 10 Values . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 ThinWire Ethernet Circuits . . . . . . . . . . . . . . . . . . . . . .
3.10.1 Coaxial Transceiver Interface . . . . . . . . . . . . . . . . . ..
3.10.1.1
Transmitter..... . . . . . . . . . . . . . . . . . . . . . . ..
3.10.1.2
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
3.10.1.3
Collision Detector. . . . . . . . . . . . . . . . . . . . . . . ..
3.10.1.4
Jabber. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.10.2 Network Address ROM . . . . . . . . . . . . . . . . . . . . . . .
3.11 Miscellaneous System Registers . . . . . . . . . . . . . . . . . ..
3.11.1 HALT Code Register (HLTCOD) . . . . . . . . . . . . . . . . .
3.11.2 Configuration and Test Register (CFGTST) . . . . . . . . . .
3.11.3 1/0 Reset Register (lORESET) . . . . . . . . . . . . . . . . . ..
3.11.4 Address Strobe Delay Line . . . . . . . . . . . . . . . . . . . . .
3.12 System Jumper Configuration. . . . . . . . . . . . . . . . . . . ..
3.13 System Module COMector Pinouts . . . . . . . . . . . . . . . .,
3.14 Power Requirements. . . . . . . . . . . . . . . . . . . . . . . . . ..

3-219
3-220
3-221
3-221
3-222
3-222
3-222
3-223
3-223
3-223
3-223
3-223
3-223
3-224
3-224
3-227
3-228
3-228
3-229
3-229
3-229
3-229
3-230
3-230
3-232
3-232
3-232
3-233
3-239

~ha.pter 4

4,.1
4.2
4.2,)
4.2,2
4.3
4.4
4.5

Introduction.",., ... " .,' , .... , .... , .. , .. , ,
4·1
Theory of Operation .. , ". .' .. "".," .. ".,.',", .... 4,,·2
Memory Module Control Signal Descriptions .... '.
4-2
Memory Cydt.'s , , , , .. , . , ... , . .
" . , .. "
4··3
Connect(lr Pinouts , . , . , , . '
.. ' , , ' . , . . . .
4·4
Configuration Jumpers . , ... ' ... , .... , .... ,.
4·7
P(W'ler Requirements . . . . . , . . . . " ... , . , . . . . . .
4·7

~haptef 5

ThlnWire Ethernet (DESVA) Option Module

5-.1

Introduction..,.....

5,;;

Connector Pin

5.32
504

Ethernet Implementation
Packet Fonnat . . ,
Neh\'ork Addresses
LANCE Chip
LANCE Description
Transmit 11ode. ., ..

5.4,1
5.4,2
5.4.3

Receive Mode .

LANCE Chip f'mout ..
SIA Chip Overview . . ,
1
SIA Description. .,.
Transmit Mode ....,
5,5.3
Receive l\·lode .....
Dl\riA Opl:":nHion
5.6
5.7 ControUer Hrm~vare
5.7.1
HOM Description .
r'rograrn
of the
Register
Port (NIHAP) , , .
1
Heglster Data Port (NI}<:DPj
5JU
Control tlnd Status
{}
58,4
Control and
5.8.5
and Status:
5.4.4

MS400 Option Memory Modules

51
7
5-7

5··8
58
5··9
5··9
5·10
5·15

5 18
5··18
19

5.10 Initialization Block . . • . . . . . . . . . . . . . . . . . • • . • . . . . . 5-30
5.10.1 Initialization Block MODE Word (NIB.MODE) ...•..... 5-31
5.10.2 Network Physical Address (NIB.PADR) . . . . . . . . . . . . . . 5-33
5.10.3 Multicast Address Filter Mask (NIB.LADRF) . . . . . . . . . . 5-34
5.10.4 Receive Descriptor Ring Pointer (NIB.RDRP) . . . . . . . . . . 5-35
5.10.5 Transmit DeSCriptor Ring Pointer (NIB.TORP) . . . . . . . . . 5-36
5.11 Buffer Management . . . . . . . . . . . • . . . . . . . . . . . . . . . . 5-37
5.11.1 Receive Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . . 5-38
5.11.2 Transmit Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . 5-40
5.12 LANCE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
5.12.1
Switch Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
5.12.2 Initialization Routine . . . . . . . . . . . . . . . . . . . . . . . . .. 5-43
5.12.3 Look-For-Work Routine . . . . . . . . . . . . . . . . . . . . . . . . 5-43
Receive Poll Routine . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
5.12.4
5.12.5 Receive Routine . . . . . . . . . ., . . . . . . . . . . . . . . . . ., 5-44
5.12.6
Receive DMA Routine . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5.12.7 Transmit Poll Routine . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5.12.8
Transmit Routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46
5.12.9 Transmit DMA Routine . . . . . . . . . . . . . . . . . . . . . . . . 5-46
5.12.10 Collision Detect Routine . . . . . . . . . . . . . . . . . . . . . . . 5-46
5.13 LANCE Programming Notes . . . . . . . . . . . . . . . . . . . . . . 5-47
5.14 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49

Chapter 6 Resistor Load Module
Chapter 7 Power Supply
7.1
7.2
7.3
7.4
7.5

xII

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
AC Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
DC Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Battery for Time-of-Year Clock . . . . . . . . . . . . . . . . . . . . . . 7-3
Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

Chapter 8 Drives
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2 RX33 Half-Height Diskette Drive . . . . . . . . . . . . . . . . . . . . . 8-1
RX33 Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
. 8.2.1
RX33 Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . 8-5
8.2.2
lnsertinglRemoving a Diskette. . . . . . . . . . . . . . . . . . . . . 8-5
8.2.3
8.3 RD32 Half-Height Hard Disk Drive ................... 8-8
8.3.1
RD32 Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . 8-9
8.4 RD53 Full.Height Hard Disk Drive . . . . . . . . . . . . . . . . . . 8-10
8.4.1
RD53 Jumper Configuration . . . . . . . . . . . . . . . . . . . . . 8-11
8.5 TK50 Tape Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Using the TK50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
8.5.1
8.5.1.1
LoadinglUnloading a Tape Cartridge ............. 8-15
8.5.2
Write Protecting a TK50 Tape Cartridge ............. 8-16

Chapter 9 DEC423 Converter (MicroVAX 2000)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2.1
Converter Enclosure . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2.2
Mounting .......................•.......... 9-2
9.2.3
Circuit Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.4
Input/Output Connector Pinout . . . . . . . . . . . . . . . . . . . . 9-3
Power DiSSipation and Cooling . . . . . . . . . . . . . . . . . . . . 9-4
9.2.5
9.2.6
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.3 Circuit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.3.1
Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.3.2
FaiIsafing ......... " . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Pins 1 and 6 on the MMJ Connectors ................ 9-6
9.3.3
ESD/EOS Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.3.4
9.3.5
Chokes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
EMl/RFI Isolation and Susceptability ................ 9-7
9.3.6
9.4 Loopback Connector H3103 (12-25083-01) ............... 9-7

xiii

Chapter 10 Expansion Peripherals
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.1 Hard Disk Expansion Box ....................... 10-1
10.1.2 Tape Drive Expansion Box ...................... 10-3
10.1.3 Expansion Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.1.3.1
The Tape Port (port A) ....................... 10-5
The Disk Port (port B) ....................... 10-6
10.1.3.2

Appendix A Timing Diagrams
Appendix B Physical Address Maps
B.l System Module Addresses . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.2 Option Module Address Ranges ..................... B-2
B.2.1
Ethernet Network Option Addresses ................ B-3
B.2.2
Graphics (Color) Video Option Addresses ............. B-4
B.2.3
Eight-port Asynchronous Serial Line Addresses ......... B-4

Figures
1-1 The VAXstation 2000 Computer System ................. 1-1
1-2 The MicroVAX 2000 Computer System ................. 1-4
2-1 VS410 System Module Functional Block Diagram ........... 2-2
2-2 Block Diagram of the CPU Chip and the FPU Chip . . . . . . . . . 2-3
2-3 System Memory Functional Block Diagram . . . . . . . . . . . . . . . 2-6
2-4 TOY Clock Functional Block Diagram ......... , ........ 2..8
2-5 DC524 Standard Cell Functional Block Diagram ........... 2-9
2-6 DC503 Cursor Sprite Chip Functional Block Diagram ....... 2-11
2-7 Serial Line Controller Functional Block Diagram .......... 2-12
2-8 9224 Disk Controller Functional Block Diagram ........... 2-14
2-9 5380 Tape Controller Functional Block Diagram ..... , ..... 2-16
2-10 ThinWire Ethernet Circuits Functional Block Diagram ....... 2-17
3-1 System Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3-2 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . 3-3
3-3 CPU Chip Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3-4 Processor Status Longword Register .................. 3-15

xiv

Jntervar Ciock Control and Status Register (lCeS) , . . . , . . . . 3··17
System Identification Register (SID) . .
.. .. . . . .
17
3-7 Interrupt Control Registers (lPL, IRR
3-8 Machine Check Exception Parameters. .
3·21
System C:.ontrol BJock Base Register (SeSE) ~ ~
~ ~ ~ ~
3,-22
3--10 DC337 FPU Chip Pinout . . . . . . . . . .
3-11 Virtual Ivfemory Address Space, . . . . . . . . . . . .
3·,31
3·-12 Physical Memory Address
3·13 Memory- Management (Mapping) Enable Register (]\·1i\.PEf·J}
3. 32
Translation Buffer InvaHdate Single Register ~TB!S)
3.15 Translation Buffer Invalidate All Register (TErA)
3·16
Space ViJtual to Physical Address Translation . , . , , . 3·34
.3-17 PO Virtual to Physical Address Tra.nslation
3-18 PI Virtual to Physical
Translation.
3. 37
3Page Tablt.' Entry
3,.20 HaIt Code Register (HLTCOD} . _ ...
3--39
3-4t)
3-21 System l'vJemor:y . , . . .. _ . . , . ,
3--22 RAM Zip Packs Block Diagram , . _ , .
3-4.1
Data In Wv'rHe} Memory Timing
3-24 Datil Out (Read) Memory Timing
3-43
Memory System Error Register (MSER) ..
3-44
3-26 1\1emory Error Address Register (MEAH) _ , .
3-46
3,27 System Module ROM Circuit
Byte)
3.-47
System ROl,,1
3-49
3-29 System TYfH':' Register (51'S.TYPE) . ". " " ' "
3··30 ThInWlf'E' Ethernet Address ROh-:l diagram, .. , ,
3-53
3-31 Option ROf..1
3·32 Option ROlvi Set Contents
3- 33 Option ROM DeB
r

•

3·35 Watch Chip and Tmns(eiver Chip Diagram .. ,
3 . ·36 ·Wat.ch Chip and Tnm!'(eivN Chip Timing" " .

3 59

Watch
Divisor (WAT
3·38 \.'Valch Date J\,1ode and Format
and
I'Vatch

3····6i1
3·65

3-41 Console Flags Register (CPFLG) . . . . . . . . . . . . . . . . . . . . 3-69
3-42 Tape Port Information Register (SCSI) . . . . . . . . . . . . . . . . 3-72
3-43 Standard Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74
3-44 DC524 Standard Cell Pinout . . . . . . . . . . . . . . . . . . . . . . . 3-75
3-45 Video RAM and Cursor Block Diagram . . . . . . . . . . . . . . . . 3-92
3-46 Video Dot Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . 3-93
3-47 Horizontal Timing Generation. . . . . . . . . . . . . . . . . . . . . . 3-94
3-48 Vertical Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . 3-94
3-49 Interrupt and Video Control Register (IVCR) ............ 3-97
3-50 Interrupt Register Formats (lNT.REQ, INT.MSK, INTSLR) .. 3-105
3-51 Interrupt Vector Longword . . . . . . . . . . . . . . . . . . . . . .. 3-107
3-52 Video Interrupt Select Register (VDC.SEL). . . . . . . . . . . .. 3-109
3-53 DC503 Cursor Sprite Chip . . . . . . . . . . . . . . . . . . . . . .. 3-114
3-54 DC503 Cursor Sprite Chip Pinout . . . . . . . . . . . . . . . . . . 3-115
3-55 Cursor Command Register (CURSMD) . . . . . . . . . . . . . . 3-119
3-56 Serial Line Controller ... . . . . . . . . . . . . . . . . . . . . . .. 3-125
3-57 DZ Controller Chip Pinout . . . . . . . . . . . . . . . . . . . . . . 3-126
3-58 DZ Silo Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3-130
3-59 Serial Line Control and Status Register (SERSSR) ....... 3-133
3-60 Serial Line Receiver Buffer Register (SER.RBUF) . . . . . . . .. 3-136
3-61 Serial Line Parameter Register (SER.LPR) . . . . . . . . . . . . . 3-137
3-62 Serial Line Transmitter Control Register (SER.TCR) . . . . . .. 3-140
3-63 Serial Line Modem Status Register (SER.MSR) .......... 3-141
3-64 Serial Line Transmitter Data Register (SER.TDR). . . . . . . .. 3-142
3-65 9224 Disk Controller. . . . . . . . . . . . . . . . . . . . . . . . . .. 3-144
3-66 9224 Disk Controller Chip Pinout . . . . . . . . . . . . . . . . . . 3-145
3-67 Disk Data Buffer Circuit Diagram. . . . . . . . . . . . . . . . . .. 3-149
3-68 Phase-Locked Loop Block Diagram . . . . . . . . . . . . . . . . . 3-150
3-69 VCO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-152
3-70 Disk Register Data Access Port . . . . . . . . . . . . . . . . . . .. 3-155
3-71 Disk Controller Command Port (DKC.CMD) ........... 3-155
3-72 Interrupt Status Port (OKC.STAl) . . . . . . . . . . . . . . . . . . 3-155
3-73 DMA Address Registers (UDCPMAxx) . . . . . . . . . . . . . . 3-159
3-74 Desired Sector Register (UDCPSECl) . . . . . . . . . . . . . . . 3-159
3-75 Desired Head Register (UDCpHEAD) . . . . . . . . . . . . . . . 3-160
3-76 Desired Cylinder Register (UDC_DCYL) . . . . . . . . . . . . . . 3-160

xvi

Current Head Register (UDCSHEAD) .. , ..... , , ... , ,
3·78 Current Cylindt,t Register (UDC. CCYL) " , , .. .., ... .
3,.79 Sector Count Register (UDe.SeNT) ,. , ........ '
3-80 Retry
Register (UDe _RTCNT), ., . , , .. ,.... . ..
3-tH Operating Mode Register (UDC}vfODE) . . . . . . , . . . . . . .
3-82 Chip Status Register
. , . . , . . . . . . , . .'
3··83 Termination Conditions Register (UDC.1'ERM) . , .. .
3-84 Drive Status Register (UDCPSTAT) ................ .
3-85 Disk Data Registe.! (UDCPATA) ... , , .... , .
3-86
Command. , . . . , . . . " , .. , , . . . , . . . , ...
3·87 SET
POI1\i'TER Command. . " , .
3-88
DRIVE Command. . . . . . . . . " , . ,
3-89 DRIVE SELECT Command . . . . . . . . . . . . . . . . , .
3··90 Restore Drive Command. .. .. .. . ..... .
3-91 STEP Corrnnarld . . . . . . . . .' . . . . . . . . . . . . . . . . . .
3-92 POLL DRIVES Command. . . . . . . . . .. . . . . . . . . . . . .
3··93 SEEKIREAD ID Command . . . . .. . . . . . . . . . . . .
3-94 FORtv1AT TRACK Command . . . . . . .. . ........... .
3.. 95 ID Field Byles for Each Sector. . . . .. , . , . . . . . . . .
3.. 96 READ TRACK Command ..
. ........ " ......
3.. 97 Rfj\D PHYSICAL Command . . . . . . , , .. , . . . . . . . . . .
3-98 READ LOGICAL Command ' . . . , . . . . . . . . . . . . . . .
3·99 VlRITE PHYSICAL Command ........ '. . . . . . . . . . ,
3-100 WRITE
Commtmd
. . . . . . ..
3 .. 1015380 Tape Controller. . . . . . . . . .
. ,.... ,
5380 Tape Controller Chip Pinoui " ... , .
3 .. 103 fviodf> HeglstE'<
MODE) .
3 .. 1041ntHlator Command ."·,e,,,.,,·,~:
105Targel

3··161

3·163
3-166
167

3-1683-170

3·175
3··176
3-178
3-179
3..·180
181
182
3 .. un
3 .. 185
}·186
3 .. 187
188
3 .. 190
3-199

3212
3 .. 212

Bus Status Reglsh;'r .... .
Enable
SEt
1090utput Data
j·..·ll0Current Dati'!

14
H

215
3 215

3··111 Input

xvii

3-113DMA Count Register (SCDSN1) . . . . . . . . . . . . . . . . . . . 3-218
3-114DMA Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . 3-219
3-115Transceiver Circuitry on System Module. . . . . . . . . . . . .. 3-225
3-116ThinWire Ethernet Transceiver Circuitry .............. 3-226
3-117Coaxial Transceiver Interface Chip Pinout. . . . . . . . . . . .. 3-227
3-118Halt Code Register (HLTCOD) . . . . . . . . . . . . . . . . . . . . 3..230
3-119Configuration and Test Register (CFGTS1) ............ 3-231
3-120VAXstation 2000 and MicroVAX 2000 System Jumper ..... 3-233
4-1 MS400 Memory Module . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
5-1 Network Interconnect Module . . . . . . . . . . . . . . . . . . . . . . . 5-2
5-2 Ethernet Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5-3 LANCE Chip Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5-4 SIA Chip Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5-5 Controller Firmware ROM . . . . . . . . . . . . . . . . . . . . . . .. 5-20
5-6 LANCE Register Address Port (NI_RAP) Format .......... 5-22
5-7 LANCE Control and Status Register 0 (NI_CSRO) ......... 5-23
5-8 LANCE Control and Status Register 1 (NISSR1) ......... 5-27
5-9 LANCE Control and Status Register 2 (NISSR2) ......... 5-28
5-10 LANCE Control and Status Register 3 (NI_CSR3) ......... 5-29
5-11 LANCE Initialization Block Format . . . . . . . . . . . . . . . . . . . 5-30
5-12 Initialization Block Mode Word (NIB_MODE) ............ 5,..31
5-13 Network Physical Address (NIB_PADR) ................ 5-33
5-14 Multicast Address Filter Mask (NIB_LADRF) ............ 5-34
5-15 Receive Descriptor Ring Pointer (NIB_RDRP) ............ 5-35
5-16 Transmit Descriptor Ring Pointer (NIB_TDRP) ........... 5-36
5-17 Receive Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
5-18 Transmit Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . 5-40
6-1 Resistor Load Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6-2 Resistor Load Module Circuit Diagram . . . . . . . . . . . . . . . . . 6-3
8-1 RX33 Diskette Drive .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8-2 RX33 Diskette ........ . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8-3 RX33 Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8-4 Inserting a Diskette . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8-5 RD32 Power and Data Connectors . . . . . . . . . . . . . . . . . . . 8-8
8-6 RD32 Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8-7 RD53 Power and Data Connectors . . . . . . . . . . . . . . . . . . 8-10

xviii

8-8 RD53 Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . 8-11
8-9 Cutaway View of the TK50 Tape Drive . . . . . . . . . . . . . . . . 8-12
8-10 TK50 Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
8-11 TK50 Rear View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
8-14 Write Protecting a Tape Cartridge . . . . . . . . . . . . . . . . . . . 8-16
8-13 Disabling Write Protect on a Tape Cartridge . . . . . . . . . . . . . 8-16
9-1 DEC423 Converter Circuit Board . . . . . . . . . . . . . . . . . . . . . 9-2
9-2 DEC423 Converter Block Diagram for Une 3 . . . . . . . . . . . . . 9-5
A-1 DAL Bus Address Control . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A-2 Program RAM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A-3 Program RAM Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
A-4 1/0 Single Cycle Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
A-5 110 Single Cycle Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
A-6 Video RAM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
A-7 Video RAM Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7
A-8 1/0 Double Cycle Read . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8
A-9 1/0 Double Cycle Write . . . . . . . . . . . . . . . . . . . . . . • . . . . A-9
A-10 CPU Cycle Slips . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10
A-ll Video Shift Register Update Cycle . . . . . . . . . . . . . . . . . . . A-11
A-12 Start of Display/Region Line . . . . . . . . . . . . . . . . . . . . . . . A-15
A-13 End of DisplaylRegion Line . . . . . . . . . . . . . . . . . . . . . . . A-16
A-14 Tape (SCSI) Port Data Transfer Operation (From Port) ...... A-17
A-15 Tape (SCSI) Port Data Transfer Operation (To Port) ........ A-18

Tables
2-1 FPU Instruction Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
3-1 CPU Chip Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3-2 Intemal Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3-3 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3-4 System Control Block Format. . . . . . . . . . . . . . . . . . . . . . . 3-23
3-5 DC337 FPU Chip Pin Functions . . . . . . . . . . . . . . . . . . . . . 3-26
3-6 Fixed ROM Address Allocations . . . . . . . . . . . . . . . . . . . . . 3-50
3-7 ROM Address Locations Option Module ROMs .......... 3-54
3-8 Watch Chip Register Addresses . . . . . . . . . . . . . . . . . . . . . 3-63
3-9 Non-Volatile RAM Contents . . . . . . . . . . . . . . . . . . . . . . . 3-67
3-10 LI<201 Language Values for LK201)D Register ........... 3-70

xix

3-11 Console Typ(~ Register Contents, , , , . , . , . ,
3-12 DC524 Standard Cdl Pinout " , . , , . ,. , ...
3-13 DAL Bus Transceiver Enable Control Signal
Functions . , . . .
. . . . ,. , .. , . ' , . . . . .
3,,14 Internal Interrupt Registers . ' .
3-15 Interrupt priority ranking .... , .. , .... ' , . , .. , . . . . . .
3-16 Monochrome Video Timing. , , . . . . . , .
3-17 Standard Cell Test Mode Addressing . . . . . . ,
3-18 DC503 Cursor Sprite Chip Pin Description, , . ,
3-19 Cursor Coordinate Offsets .... ,
3-20 Cursor Generation Values
3-21 Monochrome Cursor Control Registers "
3-22 DZ Controller Chip Pin Functions
3-23 Serial Line Identification .. '
3-24 Serial Line Controller Register Addresses .... , . , , ..
3-25 9224 Disk Controller Pin Description ..
3-26 Disk Controller Chip Ports .,
Disk Controller I<egister Numbers 0 . ' 0 , . , . , ' • •
3·28 )I.,iocle Values for the Drives. ' ,
Register Parameters , .
Write Precompensation Parameters . , , . , , , .. , , ..
3·31 Diskette Drive Status Signal.
3·32
Prototype Speed
Timing Restrictions "
0

•

••

•

••••

••

• • • • • • • • • • •

••••

•

•••

•

Pmv'er
(] 1) , ,
3-42 ThinWire Ethernet Connector (J2)
3,·43 Pri.nter Connector (3)
3-44 BaUery Connector (]4) ..
3-45 Video Connector (I5) . ,
0

•

••

•

•••

••

•

••

•

••

••••

•

••

•••

3-33 Diskette Capacities
3··34 Hard Disk
3 ·35
Tape Controller Chip Pinout,
3 .. 36 SCSI Tape Bus Signal Definitions
3·37 SCSI Tape Bus Information Transfer Phases,
3,38 5380 Controller Chip
. . , .. , ' ,
3·39 Device 10 Values, . ' , , , , .
3,,40 Coaxial Transceiver Interface
Pinout
0

•

••

•

" . " " ,

•••

3-71

3-76
•

3-89
3-105
3-109
3··11Q

3-n2
3-116
3-117
3-117

3-118
3-127

3-131
3-132
3-146
3-154

3-158
3-165
3-184
3-191

3-192
3--197

3-198
0

3·202

3-205

3-206
3·224

3-228
3-233

3-46 Network Option !lIiodule Connector {J6} , . . . , . . . .. . . . . .
3-47 RDIRX Connector
,. , . , . . .. , . . . . , , . . ....
3-48 Graphics Option Port Connector (/8)
3-49 Expansion Disk Readl\\!rite Cabl~ Connector (I9) . . . . . . . . . 3-236
3-50 Communication Connector 010) , .. , . . . . . . . . . . . , ... . 3-237
3 .. 51 Graphics Option Port ConneCWt aU). . .... , ....... . 3-237
3-52 Memory Option Module Connector CH2) ....... .
3-238
3-53 Tape Port Connector (113) . . . . . . . . . . . .
. ..... . 3.. 238
3-54 Netvvork Option Module Connector Cf1.4J ..... , .
3-239
3-55 Memory Option Module Connector (115)
4.. 1 Determining M.emary
, . 4·4
, , 44
4··2 Connector J1 Pinout. , . . . . . .
4--6
4-3 Connector 12 Pinout . . . . . . . . . . . . . . . . . . . . . . . .
4~4 Memory Module Configuration Jumpers . . . . . . . .
4-7
5-1 Pin Assignments for Connector J1 . .. , ....... .
5-2 Pin Assignments for Connector }2 . . . . . . . . . . . . . . , ... , - 5-5
1
5-3 LANCE Chip Pin Descriptions .
5-4. SIA Chip Pin Descriptions. , , ...
5-165-5 ROM Pin Descriptions . . . , , , .. , , , , . , ,
5··20
7-1
7-1 AClnputSpedfks.",.......
, .. ,.'
7-2
7·2 DC Output Spedflcations ... , .... ' . . .
8-1 Drives.,.,
9-1 Connector J4 D·$ub Pinouts
9·4
9.. 2 Connector JS D-sub Pinouts., . " , ..
9-4
9-3 MMI Connector Pinouts for jI, J2, and p,
10-1 Hard Disk Expanskm Box Internal Cable Pinout,
10-2 Tape Drive Exparwi()!1 Box Internal Cat)lt~ Pinout
1\),·5
10·-3 Tape Pori Intern,!,! Cable Pinout (Port
107
10-4 Disk Interface y.,1odule PinouJ
BJ
.
B-1
B .. 1 System Module
Locations . .
.. , FI·,3
B--2 Option Module Address
. B,3
B··3 Ethernet Neh'l'Nk Option !\1oduie
.. B-4
B·4 Graphics Video
, B,,4
I\1odu!e
Addresst's
,
B,,5 ASY'l1chronous

xxi

About This Manual
This manual docu.ments system design concepts and hardware functions for
the VAXstatkm 2000 and MicroVAX 2000 computer systems, It describes
options that support the systems, and provides hardware programming in·
formation.
Refer to the Reference Manua!~ section for a listing of documents that apply
to the VAXstahon 2000 and MkmVAX 2000 computer systen1.s.

ORGANIZA TION
The manual is divided into ten chapters and two appendices.
Chapter 1 - System Introduction describes tnt: VAXslafion 20GO and Mi·
the (om·
croVAX 2000 svstem~. II also lists the phvskaI characteristics
ponents that make up both systems.
"
Chapter 2 • Functional System Overview provides 3. functional overview of
the system module in the VAXstation :WOO and the MicroVAX 2000 systems,

Chapter:3 - VS410 System Module Detailed Description explains the system
module in detail,

Chapter 4 ~ MS401.) Option Memory Modules describes the MS40Cl-AA and
1v1540U·'6A memory modules that are options 10 the KA410·AA system module,

Chapter 5 • ThinWhe Ethernet (OESVAJ Option Moduli" describes the 017'
tion that enables a VAXstatkm 2000 or MicroVAX 2000 system to connect
10 an Ethernet neh>,'ork

Chapter 6 . R.ulstor Load Module
ulate the power supply of expansion
installed.

the module that is used to
when less than t\.VG drives are

Cnapter7 - Power Supply HOlts the operating spedJk<'!tions
ptn'll'er supply.
Chapter 8 • Drlve$ provid(;:'s an

the

of the drives

VAXst.ahon 2000 and ~UcroVAX 2000 svsten\s
Chapter 9 ~ DEC423 Converter (1\1icro VAX 200m
21ctedstif$
the converter which
installation
printers using M:MJ c(mnect(w,.

dlar·

,md

Chapter 10 • Expansion Peripherals describes the three expansion peripherals available with the VAXstation 2000 and MicroVAX 2000 systems.
Appendix A • System Timing Diagrams displays timing diagrams for the
system.
Appendix B • Physical Address Maps lists system module and option module addresses.

REFERENCE MANUALS
Manual

Order Numbet

VAXstation 2000 Hardware Installation Guide

EK-VAXAA·IN

VAXstation 2000 Owner's Manual

EK-VAXAA-OM

VAXstation 2000/MicroVAX 2000 Maintenance
Guide
MicroVAX 2000 Hardware Installation Guide

EK-VSTAA-MG
EK-MVXAA·IN

MicroVAX 2000 Owner's Manual

EK-MVXAA-OM

VR290 Service Guide

ED-VR290·SM

VAXstation 2000, MicroVAX 2000, VAXmate
Network Guide

EK-NETAA-UG

NOTES, CAUTIONS, and WARNINGS
Notes, cautions, and warnings appear throughout this book.

•

Notes contain general information about a topic.

•

Cautions contain information to prevent damage to equipment.

•

Warnings contain information to prevent personal injury.

xxiv

Chapter 1

System Introduction
1.1 VAXstation 2000 System Description
The following paragraphs prm.,de iii physicaJ description of the VAXstation
2000 system The VAXstaUon 2000 consists of the follov,rlng rour hardwan?
components (Figure 1-1).
..

System box

Video monitor

•

Keyboard

tvlouseiTabfe!

Ftgure 1-1:

The VAXstation 2000 Compu1.er System

System Imroduction

1-1

1.1.1 VS410 System Box
The VS4H.l system box contains the
•

KAHO sV5tem module - The
module 15 centra! to
thl':: entire computer system, It is a
circuit board n1(mnted
on the FCC shield. The svstem rnoduh" c(ml,,\ins all the control
,H'td interface electronics needed to
the
chip" support
all I/O for the disks and tapes" support the video
and
support the three option ports (memory, Ethernet netv\fork, and a
graphics option port). Thh; system module contains 2 megabytes of
RAM and is used in both the VAXstatlon
and 1\Ectl"VAX 2000
systems. A jumper setting on the system module determines ",,-hieh
system it is configured for,

•

modllle provides
:MS400 memory option module - The
h\!o to four additional
of RAM
. It is a printed
circuit board mounted on standoffs on the system module and
electricaily connected to the
module through two 40-pIn
connectors, Although the memory module is called <111 option,
additional memory IS necessarv to run the
or ULTRfX

Ethernet nehvork option module - The Ethernet nehvork module
provides an !EEE 802,3 in.terface to the T11inV/ire Ethernet
commun.ications n.et.,.vork it is a printed circuit board mounted
on standoffs on the svstem module
electrically ctmnected to
the
module through 1>'>'0 40.pin connectors,· This Ethernet
network module is an option on the I'I'ficroVAX
but
comes standard in thf; VAXstatlol'l 2000

•

floppy diskette drive - The
.
haH.height floppy diskette drive.
media stores
megabvtes of data. This drive is a'iflilable on both the
20G() and t.1icro V AX 2000

hard disk
. The
helght hard disk
The
This drive is avaiJabie on beth the

contain an RD32 haltto 40
c,f da.ta
!\JkroVAX

2000

1.1.2 Video Monitor
The video monitor provides the system
It i.s a VR260 monochrome monitor
bll:lek and white
for the VAXstl'ltlon 2000
The monitor has \\'\'0 display

on the side

1-2

and contrast

V,AXstatton 2000 and MlcroVAX 2000 Technica!

1.1.3 LK201 Keyboard
The operator uses the keyboard to enter data into the system. The keyboard
contains three keypads (main, editing, and numeric) and a series of special
function keys.

1.1.4 VSXXX Mouse
The operator uses the mouse to position the cursor on the monitor screen.
The mouse contains three keys and a position movement transducer for
pOSitioning the cursor on the display.

1.2 MicroVAX 2000 System Description
This section provides a physical description of the MiaoVAX 2000 system.
The MicroVAX 2000 consists of the f.:>llowing three hardware components
(Figure 1-2).
•

System box

•

Video console terminal

•

Keyboard

1.2.1 VS410 System Box
The VS410 system box contains the same components as listed in Section 1.1.1, plus one additional component. The MicroVAX 2000 system has
a DEC423 converter attached to the back of the system box. and is mounted
over the video and printer ports. The DEC423 converter changes the RS232
signals on the IS-pin video port and 9-pin printer port into DEC423 signals
which go out to the three MMJ connectors.

1.2.2 Video Console Terminal

)

The video console terminal provides the system display. The console termi·
nal is a VT220 which provides a black and white display. It has two display
controls for adjusting the brightness and contrast and also has a tilt control
on the side panel for adjusting the viewing level.

1.2.3 LK201 Keyboard
The operator uses the keyboard to enter data into the system. The keyboard
contains three keypads (main, editing, and numeric) and a series of special
function keys.

System Introduction 1-3

Figure 1-2:

The MicroVAX 2000 Computer System

1.3 Physical Characteristics
This section lists the physical characteristics of the components that comprise the VAXstation 2000 and 1\licro VAX 2000 systems,

1.3.1 System Box
The VS410 system box is housed in a desk top enclosure, AU cable access
to it is from the rear paneL
air intake is through the front panei
and exhaust is through the rear
. No clearance is
at the
or bottnrn . or either side of the

1-4 VAXstation 2000 and MfcroVAX

Technical Manua!

Width

12.75 inches

323.85 mm

Depth

t1,25 ltl(hCSi

255.75 mrTl

Hei&'.t

5.5 inchES

WtoJght

28 pounds

12.7

The dimenskms
are as follows.

VS4.10

Width

12.75 inrht's

323.85 m.!H

11.25 inche~;

285?5 mm

Ht;ight

7 inchel;

177.8 mm

WeLght

30 pour',ds

1';<.6 kg

t'liith BA411A.

adapter

1.3.1.1 KA410 System Module
Width

10 indw~;

Length

14 inches

3,55.6 mm

Heig,,;"t

1.25 inches

32 rrttll

1.3.1.2 Network Interconnect Module
W.ldth

4 Inches

Length

7 inches

178mm

Height

{US inches

6,35 mm

1.3.1.3 MS400 Memory Module
Width

4.. 6 incht'!'

116.84 mrr.

Length

8 inches

20:U rum

Heigh I

0.38 inches

SUi!:> mm

1.3.1.4 Power Supply

10.25 in(h€'s

26!L';5 rmn

:7.7S Inche::

SySfem !ntroducHon

1-5

1.3.1.5 RX33 Diskette Drive
Width

5.75 inches

146.05 mm

Length

8 inches

203.2 mm

Height

1.69 inches

42.93 mm

Weight

2.9 pounds

1.32l<g

1.3.1.6 RD32 Disk Drive
Width

5.75 inches

146.05 mm

Length

8 inches

203.2 mm

Height

1.63 inches

41.4mm

Weight

3.5 pounds

1.59l<g

1.3.1.7 DEC423 Converter (MlcroVAX 2000)
Width

3 inches

76.2 mm

Length

3.3 inches

83.82 mm

Height

1.23 inches

31.24 mm

Weight

5.6 ounces

159 8

1.3.1.8 Resistor Load Module
Width

4 inches

101.6 mm

Length

7 inches

177.8 mm

Height

0.5 inches

12.7 mm

1.3.2 BA40B Expansion Boxes
The power supply and resistor load modules in the expansion boxes are the
same as in the system box. Dimensions of the BA40B storage expansion
boxes are as follows.
Width

12.75 inches

323.85 mm

Depth

11.25 inches

285.75 mm

Height

5.5 inches

139.7 mm

Weight

20 pounds

9.1l<g

1-6 VAXstation 2000 and MlcroVAX 2000 Technical Manual

1.3.2.1 RDS3 Disk Drive
Width

5.75 inches

146.05 mm

length

8.2 inches

208.28 mm

Height

3.37 inches

85.6mm

Weight

6.3 pounds

2.8 kg

1.3.2.2 TZK50 Controller Boerd
Width

5.7 inches

144.78 mm

length

8 inches

203.2 mm

Height

0.625 inches

15.88 mm

1.3.2.3 TK50 Tape Drive
Width

5.75 inches

146.05mm

length

8.4 inches

213.36mm

Height

3.25 inches

82.55mm

Weight

5 pounds

2.27 kg

1.3.3 BA40A Expansion Adapter
Width

12.75 inches

323.85 mm

length

11.25 inches

285.75 mm

Height

1.Sinches

38.1 mm

Weight

2 pounds

0.9 kg

1.3.3.1 Disk Interface Module
Width

3.2 inches

81.28 mm

length

5.2 inches

132.08 mm

Height

0.4 inches

10.16 mm

System Introduction 1-7

Chapter 2

FunctionaJ System Overview
This chapter describes the functional overview of the system module in the
VAX station 2000 and ~·ikroVAX 2000 systems. Functional ov€wiev·')s of
optional modules to these systems are described within thei.r chaptf?'l' and
are. not discussed here. Figure 2-1 shows the functional block diagran, of
the system modu1e.

2.1 Central Processor Overview
The centra! proc€gsor consists of a DC333 MicroVAX CPU chip and a [)C337
MkroVAX FrU chip, The DC333 ~1icroVAX CPU chIp is a 32-bit virtual
memory microprocessor that impl.ement~ a subset VAX-compatible ct"ntral
processoL The DC337 FrU chip i.mplements a subset VAX-wmpatible floating point unit The FPll chip ptQivides floating point computation
ties to the 1\HcroVAX CPU chip. Each chip is wntaim?d 111 a 6S.pin package
and both chips reside on the V5410 system module.
Both chips use the 40 MH.z oscillator and communicate to each other over
the 32 .. bit VDAL
bus. The F373 latch and the F245 bidirectional bus
transceiver buffer the VDAL CPU bus to the ELAD bus and BDAt bus,
respectively. FIgUf€ 2·.. 2 sho,v$ the functional block diagram of the CPU
chip and the FrU

Functiona! System Overview 2-1

~
~

i ! l~ I
~

L,_ _ _--.,.-Jh

2-2

VAXslalion 2000 and MlcroVAX 2000

Figure 2-2: Block Diagram of the CPU Chip and the FPU Chip
F373
LATCH

ELAO

J====~

F245

WAX

UPROC
DC333
UVAX

FPU

DC337

40 MHZ

osc

IoIA-X0754-87

Key features supported by the DC333 MicroVAX CPU chip:

•

Subset VAX data types - The chip supports the following subset
of the VAX data types: byte, word, longword, quadword, character
string, and variable length bit field. Support for (floating, d _floating,
and g.floating is available via the floating point unit chip. Support
for the remaining VAX data types can be provided by macrocode
emulation.

•

Subset VAX instruction set - The chip implements the following
subset of the VAX instruction set: integer and logical, address, variable length bit field, control, procedure call, miscellaneous, queue,
MOVC31MOVC5, and operating system support. Floating point is
implemented through the floating point unit chip. The remaining
VAX instructions can be implemented via macrocode emulation (the
chip provides microcode assists for the emulation of the character
string, decimal string, EDITPC, and CRC instructions).

Functional System Overview 2-3

Floating point - The chip supports f}loating,
floating data types through the. FPU;
not support
.Full VAX memory management - The chip includes a
paged memory management unit which is fuUy compatible with
VAX memory management System space
are virtually
mapped through single"level page tables and pn'l(.:ess space addresses through double,level page tables,
External interface based on industry standards - The chip's external
interface is a 32-blt extension of the industf'j standard microproces'
sor interface,
Large virtual and physical address space chip supports four
gigah}1es (
of virtual memory., and one gigabyte (
of physical
mernory,

..
a

performance - At its maximum frequency, the
n& !Yl.icrocyde and a 400 ns liO cycle,

Single package -- The chip is package.d in a standard 6S-pin surface
mounted chip carrier.

Key- features supported by the DC337 FPU
..

VAX data types - The chIp supports the
\'AX data types: byte,
longvvord, f floating, d.
gJloatlng, The data type h
is not supported.

Subset VAX instruction set - The chip implements a subset of the
VAX floating point instruction set. (The
floating
instructions, except h ,floating, are implemented in
CPU
1
Accuracv for the EMOD and
instructic'TlS wi!! meet VAX archHectural standards"

Integer multiply and divide acceleration - The chip supports
integer m'.lltiply and unsigned integer divide,

2-4

Simple extemallnterface - The chip's externallnterfacE' is straightfonvard and requires no external support

VAXstaHcn

and MlcroVAX 2000

Htgh performance - At its maxlmurn frequency,

a 100 ns mkrocvcle and a
..

chip achieves

ns ItO (vde,

Package - The chip is
carrier.

Fast instruction times - Table 2 1 lists tyvical in~tnJCtion times for

the FPU, Note that times may be
operands used in the calculation,

(;r'slower depending on the

Table 2-1: FPU Instruction Times
lns~rudion

Single

Double

ADDI

2.0

MOL

2.6

4.2

D!V

3·,7

6,1

2.2 System Memory
The system memory consists of RAM and RO!',,1
locatf.'d on the
system module and also RAM memNV k)catt:d on the ()ption
rliociuie Even though the ('phonal RAM. is no! located Nt thf'
module,. it is considered te be svstem memorY Figure 2,,3 sh(l'w~ the
functional block diagram of the . '
menwry'
The system supports tlP to 1.6

of R/\M (DRAM;
not
induding ....ideo RAM The actual am.ounl of RAt,! depends
the optIOn
memory module installed The data path to RAM memory 32·bHs .vide
Data integrity is checked by a parit.'r' bit associated with each bytt' of
The RAM that is phvsically located on the
module conli.um:
of 11lemory.
m(xlule It contains Hw vidt';:. .
bus caries the bltrnap information
through ,'I.
counter t<· the standard ceil. 'Ihe standi:ud ('ell th,;:ll
to dispL'lj/ the videO
with the nmwr

screen

2-5

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..•E
0

•
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iii
li
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2-6 VAXstation 2000 and MlcroVAX 2000 Technical Manual

The optional memory module can contain up to 14,336 kilobytE'f'l of RAM,
however, only 2048 kilobyte and 4096 kilobyte RAM option memory
modules are supported. The system generates byte parity when writing
to RAM memory and checks byte parity when reading from RAM memory.
The system module ROM contains 256k bytes of data that indudes processor
restart, diagnostic and console code, and 110 device drivers. The system
ROM is addressed by the CPU chip over the ELAD bus and also by the
standard cell over the MEMAD bus. The ROM outputs the data onto the
MD bus which is buffered onto the BDAL bus and sent back to the CPU chip.
The system ROM also contains interrupt vector routines that are addressed
by the standard cell over the IAD bus.

)

The ThinWire Ethernet ID ROM on the system module contains 32 bytes of
memory for a unique Ethernet network identification address for the system.
Each option module is required to have its own ROM memory that contains
a standard signature to identify the option, as well as firmware initialization
code and diagnostic code. This option ROM information is accessed
through the memory option port.

2.3 Time-Of-Vear Clock
The time of year dock keeps the date, time of day, and 50 bytes of general
purpose RAM. A 32.768 kHz time base oscillator provides the dock input
and a rechargeable nickel-cadmium battery provides power to the chip
and oscillator while system power is off. The TOY dock uses an LS646
transceiver to buffer and control the data and addresses to and from the
CPU bus. Data from the TOY clock is used to determine the date and time
during the power-up of the system. Within the 50 bytes of RAM are stored
utilities such as the boot flags, boot device, halt action, and keyboard type
as well as other volatile information. Figure 2-4 shows the functional block
diagram of the TOY dock and also the configuration and test register.
A nickel-cadmium battery in the system box supplies power to the watch
chip and its time base oscillator while system power is off. When starting
from a fully charged condition, the battery maintains valid time and RAM
data in the watch chip for a minimum of 100 hours. The battery recharges
while system power is on.
Figure 2-4 also shows the configuration and test register. This register is an
8·bit register that contains system information such as whether the system
is a VAXstation 2000 or a MicroVAX 2000, whether an option module is
installed in the option slots, whether the BCC08 cable is connected to the
printer port, and cursor Chip test results.

Functional System Overview 2-7

Figure 2-4: TOY Clock Functional Block Diagram

7:,'1
i::~J>G'K

2.4 DC524 Standard Cell
The
standard celi is the heart of lhe
It controls the address
decoding and the
parameters for e,lch
It contains the
interrupt controller, parity generation and
of the monitor
timing circuitry internal to itself. The liSl belcnv summarizes the functions
of the standard. cen and Figure
sho\lts the functional block diagram. of
the standard cell

•

2-8

initialization

•

\1ernory r,,,..,tr,-.'

Video control.

110 control

•

Disk control

•

Tape contI""'l

•

Parity

Interval timer interrupt

•

Interrupt controller

Monitor timing

•

test rnode

and checking

VAXstation

and MicfOVAX 2000 Technical Man(Ja!

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.:.

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u..
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ii:

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Functional System Overview 2-9

2.5 DC503 Cursor Sprite Chip
The
cursor sprite chip generales a cursor display Nt the video 1.110(1
itor. The cursor is generated from a two-plane rnemory array within the
cursor chip. The cursor sprite chip receives commands over the BDAL bus
for such things as cursor position, cursor pattern, and blankil.g of the cursor
The output of the cursor sprite chip is sent to the standard cell for inclusion
in the video output signal to the monitor. Figure 2-6 shov~'s tht~ functional
block diagram of the De503 cursor sprite chip.

2.6 Serial Line Controller
The
module serial Hne controller handles four asynchronous serial
lines.
controller i.s a DC367B gate array. Input characters {r(lm all four
lines are buffered in a. common 64-position silo. The silo is a true silo V\'heIf~
a character drops through an 64 words in the sih) before it is latched at the
output. Only one.
the communication Hne, has full modem control
of the serial lint;
Figure 2··7 shows the functional
controller. c.-

2-10

VAXstation 2000 and MlcroVA,X 2000 Techn!cal Manua!

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;:lc

u::

FUl1ct\ona1 System

2-11

!i
~

2-12

I...J!

___________ ______ "i
~

VAXs~a.tion 2000 and MicroVAX 2000 Technical ManLla:

~'i

2.7 9224 Disk Controller
The disk controller supports both diskette drives (RX33) and ST506/412 hard
disk drives (RD32 and RD53). The maximum configuration of the controller
is one diskette drive and two hard disk drives. The controller is an HDC
9224 universal disk controller chip which uses a phase-locked loop (PLL)
data recovery circuit, an address counter, and a 16-kilobyte dual port data
buffer. Figure 2-8 shows the functional block diagram of the 9224 disk
controller.
The disk data buffer is a 16-kilobyte block of RAM storage which is shared
between the disk controller, the tape controller, and the CPU. This buffer
uses two 8-kilobyte by 8-bit static RAM chips and is not included as part of
the system module dynamic RAM. The disk and tape controller access the
data buffer through the address counters. The address counters hold the
data buffer address from the disk cOf'troller during normal RAM cycles as
well as during DMA cycles. The disk data buffer is accessed by the CPU
chip through the tn-state transceivers between the BOAL bus and the IDAL
bus.
The phased locked loop (PLL) consists of a phase comparator and a voltagecontrolled oscillator (VCO). The phase comparator is inside the standard
cell. The VCO is a dual oscillator chip for both hard disk and floppy diskette
data frequencies. The phased lock loop is used to control the frequency
of the raw read data from the disks. The individual modified frequency
modulation (MFM) pulses that are read from the disks are sensitive to speed
variations and the value of the pulse (1 or 0) may be lost if the frequency
of the data stream is not precise. The VCO allows the tracking of any
variation of the data stream and sends feedback to the phase comparator to
compensate the variation so the loop recovers the data and sends the disk
controller a steady and reliable data stream.

)

Functional System Overview 2-13

)

2-14

VAXstallon 2000 and MicroVAX 2000 Technical ~,,'anua!

2.8 5380 Tape Controller
The
controller is an
5380 SCSI controller chip. It provides an
ANSI
Computer System Interface
intNlace between the TZKSO
tape controHer In thE'
expansion box and the data buffer on the s:ystem
mmiuie. The tapE: controller Is connected directly 10 the SCSI tape
which is pori l\ on the expansion adapter, and it is also connected to the
disk datil buffer through the disk buffer data bus. The tnpe controller is
controlled by the DC524 standard cell Figmf! 2--9 shows the
block diagram of the 5380 tape controller.
The
interface is a hi-directional 8·bit "lide bus to vvhirh. up to
devices can be attached, The s'vstem n1odul.€ is one of those devices, so
up to seven additional devices can be attached De'vices may play one of
h~'o roles: initiator or target. An initiator originates an operation by sending
a command to a specific target. A target pedorrns an operatlnn thaI is
requested by an initiator. In this product, it is a:!surned that the
module is al'ways an initiator and that an other
devices
are targets, Each devkt? attached tQ the SCSI tape bus is identified
a
unique device ID number tn the
0 through 7; the systern module is
normally 0.

Functional System

2-15

...m

01
l1l:I

is
.¥

(,)

E
m
7U

-c

~
( ,)

':l

u..

...

"0....
c
0

II
!

r"
...,.

L.J

!r;l

J'"
!!. ~

r-i

(/,)

Q.
~

l.t)

Cl
I

1 ,

...:=;c:l

l~l
L:!J

2-16 VAXstatlon 2000 and t1!croVAX

H~ I

Tecrmlcat

2.9 ThinWire Ethernet Circuits
The only portion of the Thln\Vire Ethernet network circuitry that is not on the
Ethernet network option module is the transceiver circuitry. This transceiver
circuitry is located in the upper right hand corner of the system module. It
. consists of the coaxial cable connector, the ('()axial transceiver interface chip.
and the isolation transformer. The coaxial transcel.ver interfa<::.€ "CTl) is used
a the coaxial cable line driver and recei.ver for the Thin Wire Ethernet locai
area network The en contains a transrnitter, receiver, collision detector,
and a jabber timer. Figure 2-10
the functional block diagram of the
ThinWire Ethernet. circuit!'>.

Figure 2-10:

ThlnWire Ethernet Circuits. Functional Block Diagram

EXPANS!ON

ThinWite

ETHERNET

Functional System

2-17

Chapter 3

VS410 System Module Detailed
Description
3.1 Introduction
This chapter explains in detail the
chaf'ter contains the follO\\'ing sections,

Central processor

•

ROM memory

Time-of· Year

DC524 standard cell

DC503 cursor sprite chip

Serial line control1er

rn{)dult~

FtgUJ€ 3·

This

-9224 disk control/I?:
.,

5380 tape ('ontroller

•

ThinvVire Ethernet

...

Miscellaneous registers

VAXstation 2000 and M.kroVAX 2000 system jumper configuration

System module connector pinouts

Power requirements

10 System Modu!e Detailed

3-1

Figure 3-1:

System Module

II
II
f"~i

L......i

r~',

r'l
,

U
LJ ;"1
~~P;;';il' -,-'

3-2

VAXstalion

,
t •••.!

and MicroVAX 2000

I ,
L~

3.2 CentraJ Processor
This section describes the
ure

chip and the

chip in detail.

Figure 3-2 : Central Processor Unit (CPU)

r""

ILJ:
i

~~,)

I
I

VS4

to """""~l" Module

3-3

3.2.1 DC333 CPU Chip Specifics
Figure 3-3 shows the pinout for the CPU chip. Table 3-1 lists the CPU pins
and explains their functions.
Figure 3-3:

CPU Chip Pinout
OC333
VOAl31
VOAl30
VOAL29
VOAL28
VOAL27
VOAL26
VOAL25
VOAL24
VOAL23
VOAL22
VOAL21
VOAL20
VOAl19
VOAl18
VOAl17
VOAl16
VOAllS
VOAl14
VOAl13
VOAl12
VOAl"
VOAll0
VOAlO!l
VOAL08
VOAl07
VOAl06
VOAl05
VOAl04
VOAl03
VOAL02
VOAlOl
VOALOO

OAl

READY
ERROR

VAS
VOS
\/WRITE
VOIlE

'IIlMEl
'¥'BME2

'¥'BMEI
'¥'BMEO
OMAREQ

VONC

IRQ3
IRQ2
IRQ'
INTREQ
py,ftf1.
INTTlM

EPS

HALT
CPRESET

TEST

1IClJ(40

1IClJ(O

'¥'BB

3-4 VAXstatlon 2000 and MicroVAX 2000 Technical Manual

Table 3-1: CPU Chip Pin Functions
Pin

Signal

Description

CPU Data and Address Bus

62:68
59:45
42:33

VDAL06:00
VOAL21:07
VOAL31:23

The data and address bus (VOAL 31 :00) is a bidirectional time-multiplexed bus. During the first part
of a CPU read cycle or CPU write cycle, VOAL31:3O
indicate the length of the memory operand (00 =
byte, 01 .. word, 10 = 10ngword, 11
quad word),
and VDAL29:00 contain the LONGWORO address of
the memory operand (bit VOAL29 distinguishes memo
ory space from 110 space). During the second part
of a CPU read cycle or Interrupt acknowledge cycle, VDAL31:00 is used to receive incoming information. Duri;lg the second part of a CPU write cycle, VOAL31:00 is used to transmit outgoing information. During the first part of an interrupt acknowledge cycle, VDAL04:00 contain the IPL of the interrupt being acknowledged, VDAL29:05 contain Os, and
VOAL31:3O are 10. The VOAL bus is also used to
exchange information with external processors such
as the lance chip on the network interconnect option
module.

Bus Control

VAS

The address strobe signal provides timing and control
information to the video and memory option ports.
During a CPU read cycle, CPU write cycle, or interrupt acknowledge cycle, the chip asserts VAS L when
the initial information on VOAL 31:00 is valid. The
chip deasserts VAS L at the conclusion of the bus cycle.

VOS

The data strobe signal provides timing information for
data transfers. During a CPU read cycle or interrupt
acknowledge cycle, the chip asserts VDS L to indicate
that VDAL 31:00 are free to receive incoming data,
and deasserts VDS L to indicate that it has received
and latched the incoming data. During a CPU write
cycle, the chip asserts VOS L to indicate that VDAL
31:00 contain valid outgoing data, and deasserts VOS
L to indicate the end of vaJld outgoing data.

VS410 System Module Detailed Description

3-5

Pin Functions

Table 3-1
Pin

Signal

VDBE

OesteipHon

to control
transceivers, The
?S5enS 'lDBE L to en<lblF. Ihe
'v'DAt transceivers" and deasserts it to disable them,

VVVRITE

The write signal spenfies the dirf'('f1OT\ of dati! transfer
on the VDAL bus If VWRITE Lis asserted, then the
chip is driving d.ata onto lhe VDAL JfVWR1TE L is nN
asserted, the chip is not driving data 01'110 the VDAL

v"VRITE L is valid when V/"S L is asserted or EPS L
is ;lsserted,

ERROR

The DC324 standard eel! asserts the bus error
(ERROR L) to indicate abncmnal termination
CPU read
CPU write
During a
rupt

write

this causes a machine check,
this causes the prefe!ched

hi be

During 3£1 interrurt
ERROR L cancels Ii",
tranS<I.rtiorL

the chip
the assertion
ERROR L it terminat<'s the current bus cvde and oroceeds, The DC524
standard c£'1.! then deai.~erts ERROR L

READY

The DC524 standard cell asserls the ready signal (READY
L) to indicate noml".l termina!ion of the current CPU
read
CPU write
or interrupt
a CPU read
or

on (iv:: VDAL

t.ht' aso.ert.km of
READY L., it t<'rmtna!es
current bus
and procet~ds. The DC524 standard cell then deasserts RE/;DY

L
15: 12

VB!\B:O

which
of the VDld.
bus (ontain
durirg the seCGl1d
of a CPU read cycle or CPU wdte .
If
is asserted, the); VDAL 31:74
v<liid data.' if
VBM2 L is
then V[)AL 23; 16 conta.los vilHd
data; if V13Ml L is asserted, thE'n VDAL 15.8 cop~aim
valid data; if VBMO L is asserted, then VL;r~L i;'J

The

nmtJlnsralld d"ta,

3-6

VAXstallon 2000 and MicroVAX 2000 Technical Manual

Table 3-1 (Cant.): CPU Chip Pin Functions
Pin

Sl8na.

Description
During a CPU read cycle, the byte masks indicate
which bytes of data must be placed on the VDAL;
if this amounts to less than 32 bits, the other bytes
of the VDAL are ignored. During a CPU write cycle,
the byte masks specify which bytes of the VDAL bus
contain valid data. During an interrupt acknowledge
cycle, al1 four byte masks are asserted. VBM3:0 L are
only valid when VAS L is asserted.

System Control
26:24

)

VCS2:0

The control status lines, in conjunction with the VWRITE
L signal, provide status about the current bus cycle.
VCS2:0 are valid when VAS Lor EPS L is asserted.
(VCS2 is also used during the external processor protocol, see below). During a CPU read cycle, CPU
write cycle, or interrupt acknowledge cycle (VAS Lasserted), VWRITE Land VCS2:0 mean the following:

VWRITE VCS2:0 Bus Cycle Type

)

reserved

LLH

reserved

LHL

reserved

LHH

interrupt acknowledge

HLL

read (i-stream)

HLH

read lock

HHL

read (D-stream, modify intent)

HHH

read (D.stream, no modify Intent)

LLL

reserved

LLH

reserved

LHL

reserved

LHH

reserved

VS410 System Module Detailed Description

3-7

Table 3-1 (Cont.): CPU Chip Pin Functions
Pin

Signal

Description
L

HLL

reserved

HLH

write unlock

HHL

reserved

HHH

write (D-stream)

During an external processor read cycle, external processor write cycle, or external processor response cycle
(EPS L asserted), VCS2 is precharged and sustained
high, and VWRITE Land VCSl:O mean the following:

VWRITE VCSl:0 Bus Cycle Type

CPRESET

reserved

read data

reserved

response enable

write command (FPU)

write data

write command (non-FPU)

reserved

The DC524 standard cell asserts the reset signal (RESET L) to force the CPU chip to its initial power-up
state.

3-8 VAXstation 2000 and MicroVAX 2000 Technical Manual

Table 3-1

Pin Functions

Signa!
11

ii.ALT

Pressing the hal! button or presE;ing the BRE/\K
the
conH)le aSf>€'rts the hilJt
LJ to transfer control to consoJe ,.",'>c'r,-"-,,,,;<'

conclusion of the current .macroinstruction,
f'.'),eCtltes a.n external processor \vri!e
During
this cvcle, V(51;0 "" 10 {non·FrU command! and
VDALiJs:oO '" 11111 L The chlp then enters the reSI,ut
prOCt'SS whh the restart code '= 2 (HALT L

HALT L is

rather than levek;enl'-itive, is
and is

rnlCI'()("I.'Cll',

Interrupt Control
The interval timer

(INTTHd L} aHows th(' DCS24

standard eel! to sl~nal an interval timer rollover to
the chip. INTTIM"Linterrupts at lPL16 (SeB vector
CO neK), An interval Hmet inH:Trupt is not l3cknmvj·
edged
the chip_ INTTIM L if! edg",,"s~'nsillve l'atht'l'
them level-sensitive, is sampled dming every

de . and IS synchronlu:,d internally.

POVIlERFAIL

This signal is :not used, It is pulled high by a puB.up
resistor,

INTREQ

The interrupt request sig.nal (!RQO L) from the DC524
standard ,elI aHows several ilO devices 1(\ input a Single iIlterrupt request W the CP1')
al
level
lPLH. \',,1,en taken, interrupt requests are
ed.gf'd

an interrupt ac}.c;nowleclgt~

IRQO L is

is samried during every
and i.s synchronized interm;1!y.
b

IRQ1

This
resiswr.

is not used, It is puBed

This

i.s not use,d. It is

Is no! u$ed, It is pr.l.llt"d

resfs.wr

'I'his

reslMOl'

VS410

Module Deralled

Table 3-1 (Cont.): CPU Chip Pin Functions
Pin

Signal

Description

Direct Memory Access Control

VDMG

The DMA grant signal (VDMG L) is asserted by the
chip to grant control of the VDAL bus and related
control signals to the DC524 standard cell and to the
lance chip on the network interconnect option module. The chip floats (three-states) the VDAL bus and
the related control signals. When the network interconnect module deasserts VDMAREQ L, the CPU chip
responds by de-asserting VDMG L and then starts the
next bus cycle.

DMAREQ

The DMA request signal (DMAREQ L) is asserted by
the lance chip on the network interconnect option
module when it needs to take control of the VDAL
bus and related control signals for DMA or other purposes. DMAREQ L is level-sensitive, is sampled during every microcycle, and is synchronized internally.

Miscellaneous

VCLKO

This signal supplies a synchronized timing signal for
other chips in the system. It oscillates at half the frequency of the 40 MHz clock input signal. The first
rising edge of clock output following the deassertion
of the reset signal begins the start of phase 1 of the
CPU chip timing sequence.

EPS

The external processor strobe signal (EPS L) is tlsed by
the CPU chip to coordinate external processor transactions with the FPU chip.

eLKl

This input supplies a 40 MHz square wave clock timing
to the CPU chip from an oscillalor. Jumper W4 can
be removed to disconnect the osciUator from the CPU
chip for diagnostic purposes.

VBB

This pin is connected to the back bias generator. It can
be used to test the function of the back bias generator
or to supply back biasing during a diagnostic debug
procedure.

Test

This signal is not used and is connected to ground.

3-10

VAXstation 2000 and MicroVAX 2000 Technical Manual

3.2.1.1 CPU Sus Cycle Descriptioos
The
chip
eight types of bus
If

Idle

CPU read

CPU write

Interrupt acknowledge

External processor read (status or data)

External processor ,'I'rite (command or

External processor response

DM,\

3.2.1.1.1 CPU 'dIe Cycle
An idk cycle requires four dock phage~ {nominally 200 m,L The VDAL bus
is undefined, The bus control signals are unassened.
3.2.1.1.2 CPU Read Cycle
In a CPU read cyde, the chip inputs informatio,n fr·om main memory (ll:
1/0 devices. A CPU read cyde reqUires a minimum of eight dock phases
(nominally 4.00 ns) and may last longer. in increments of four dod. phases
(nominally 200 ns). The ('hi~ drivel? the physical !ong\i\'ord address onto
VDAL29:02. Br-B:O Land C5... :0 are asserted as reqUired: \rV.R Lis unasserted,
The chip asserts AS 1., indicating that tht:, physical address is valid, The chip
then asserts DS L, indicating that the VDAL bus is free to receive incoming
placing the requjred datil.
datiL If no error occurs external logiC responds
on VDAL31:00 and asserting RDY L The chip then reads the data from the
VDAL bus. If an error occurs, external
responds by asserting ERR L
The chip ignores the data on VDAL31:00
case and, if the tra.nsac!iO)1
is a data
initiates a machine check
, the chip deasst'lts AS L
and DS L to end the
read bus

Module Detailed

3.2.1.1.3 CPU Write Cycle
In a
the chip
infonn"Hon to main mt·mnry 01
'f') d
'
A
'!
I
. ,
f' 1 . .-1,,-1,
pl-:"'~I~"
11__
e\."lC1:'5.
t....
wn.e
cyr:.e
a mmunun1
0
>.,,_1<. r''''''''''~:O
400 IlS) and ll1<iy last longer, in increments of
dock ph,lses
The chip drives the
!(1n~,vord address onh.l
L and CS'2~O are
;18 required, WR L is a.sserted.
The chip asserts AS L, indicating that the physical address is valid. The chip
then drives the output dar3 onto VDAL31:00 and asserts DS L,
the data. bu.8 contains vaHd dat" if !1!) error occurs, extemal logic
reading the required data from the
bus and asserting
L. If
an errm occurs, external logic n;sponds by
ERR t., and the chip
initiates a machine check, Finally, the chip deasserts
Land DS t to end
the CPU write bus
3.2.1.1.4 Interrupt Acknowledge Cycle
In an interrupt
a \'~;(tor from an inter·
rtlpting device. An interrupt
cycle
il minimum of
eight dock. phases (nominally 400 os)
rna); last longer, in increments of
four dock phases (200 ns). The chip drives out the 1fL of the interrupt beinR. acknowledged on VDAL04:00 iIRQO L is 11'L 14), VDAL29:05 are zero.
VDAL31'30 are 10, BIYB:O L are all
C52:0 indicate an interrupt
acknowledge cycle, andVVR L is unasserted. The chip asserts A5 L, indicating that the 1PL level is valid, The chip then asserts DS L" indicating that
the V[)AL bus is free to receive the
vector. If no error occurs,
external logic responds by placing the interrupt vector on VDAL09:02 and
the normal processing flag on VDALOO and
RDY L. The chip reads
the vector from the VD,,\L bus. If an HfOf occurs. external
responds
by
ElmOR L. The chip
the data on the VD
in thi~ case
and
the interrupt
' The
deasserts ,·\S Land DS L to
end the interrupt ackno\'lledge cycle.

The de.tailed
read cycle.

of an interrupt iicknowledge

to 0 CPU

3.2,1 1.5 External Processor Read Cycle
[n an exlnrh1.l processor read
, the chip
Information ieilht.'r StilttlS
or data) from an externa! processor. An external pwcessor read cycle lasts
dock
(nominally 200 ns), TIH': chip dnves the cycle status onto
O . a n d sustains
high, and ilsseris El'S L The external
processor responds by placing the required informatIOn onto the VOAL bus.
The chip reads the intorm,'Ition off the VDAL bus and deasserts EPS Lund
the external processor then removes its infnrmatlon from the VD/..,L to end
the external processor read

3-12

VAXstation 2000 and MicroVAX 2000 Technical Manua!

3.2.1.1.6 External Processor Write Cycle
In an external processor write cycle, the chip outputs information (either
command or data) to an external processor. An external processor write
cycle lasts four clock phases (nominally 200 ns). The chip drives the cycle
status onto CS1:0, precharges and sustains CS2 high, and asserts EPS L. The
. chip then places the outgoing information onto the VDAL bus and deasserts
EPS L. The external processor responds to the deassertion of EPS L by
reading the information off the VDAL bus to end the external processor
write cycle.

)

3.2.1.1.7 External Processor Response Cycle
In an external processor response cycle, the chip inputs information (either
status or data), and a completion or confirmation signal from an external
processor. An external processor response cycle lasts four clock phases
(nominally 200 ns). The chip drives the cycle status onto CS1:0, precharges
and sustains CS2 high, and asserts EPS L. The external processor responds
to the assertion vf EPS L by placing the required information on the VDAL
bus and, optionally, by driving CS2 low with an open drain driver. In any
case, the chip deasserts EPS L. The external processor then removes its
data from the VDAL, and stops driving CS2, if driven to end the external
processor response cycle.
3.2.1.1.8 DMA Cycle
The chip can relinquish its control of the VDAL bus and related control
signals upon request from the lance chip on the netwotk interconnect option
module for a DMA cycle. The lance chip requests control of the bus by
asserting DMR L. At the conclusion of the current bus cycle, the CPU chip
responds by floating (three-stating) VDAL31:00, AS L, OS L, WR L, and OBE
L by driving BM3:0 Land CS2:0 high and by asserting DMG L (BM3:0 and
CS2:0 are then floated also). The lance chip may now use the VDAL bus to
transfer data. To return control of the VDAL bus to the CPU, the lance chip
stops driving AS L, DBE L, and OS L, if driven, and deasserts DMR L. The
chip responds by deasserting OMG L and starting the next bus cycle.

VS410 System Module Detailed Description 3-13

3.2.1.2 General Registers
There are sixteen general registers in the CPU chip. These registers contain
32 bits.

•

Twelve general purpose registers (RO - Rll)

•

One argument pointer register (R12,AP)

•

One frame pointer (R13,FP)

•

One stack pointer (R14,SP)

•

One program counter (R15,PC)

3.2.1.3 Processor Status Longword (PSL) Register
The PSL deternlines the execution state of the processor at any time. Figure 3-4 shows the format of the processor status longword.
3.2.1.4 Interna' Processor Registers ('PR)
The internal processor registers are explicitly accessible only by the move
to processor register (MTPR) and move from processor register (MFPR) instructions. Internal processor register space provides access to many types
of CPU control and status registers such as the memory management base
registers, parts of the process status longword, and the multiple stack pointers.

Table 3-2 enumera~es the available processor registers and indicates how
they are implemented in the VS410 system module. Registers that are not
listed are reserved. Attempts to access a reserved register results in a reserved operand fault.

3-14 VAXstation 2000 and MicroVAX 2000 Technical Manual

Figure 3-4: Processor Status Longword Register

3 3 2 2 2 222 2 222
109 8 166 4 3 2 1 0

1 1

816543210

6 5
IPL

Data Bit

Definition

CM-Compatibility mode

TP-Traci! pending

29:28

O-Must be .tero (0)

FPD-First part done

IS-Interrupt stack

25:24

CUR-Current mode

23:22

PRV-Previous mode

O-Must be zero (0)

20:16

IPL-Interrupt priority level

15:08

O-Must be zero (0)

DV-Decimal overflow trap enable

FU-Floating underflow fault enable

IV-Integer overflow trap enable

T-Trace enable

N-Negative condition code

Z-Zero condition code

V-Overflow condition code

C-Carry condition code

VS410 System Module Detailed Description 3-15

Table 3-2: Internal Processor Registers
Number

Name

Description

Type

Note

KSP

Kernel stack pointer

R/W

ESP

Executive stack pointer

R/W

SSP

Supervisor stack pointer

R/W

USP

User stack pointer

R/W

ISP

Interrupt stack pointer

R/W

POBR

PO base register

RfW

POLR

PO length register

RIW

PIBR

PI base register

R/W

PILR

PI length register

R/W

SBR

System base register

RIW

SLR

System length register

R/W

PCBB

Process control block base

R/W

SCBB

System control block base

RIW

IPL

Interrupt priority level

R/W

IR2

ASTLVL

AST level

R/W

SIRR

Software interrupt request

SISR

Software interrupt summary

RfW

ICCS

Interval dock control

R/W

2R3

SAVISP

Console saved interrupt stack pointer

R/W

SAVPC

Console saved PC

R/W

SAVPSL

Console saved PSL

R/W

MAPEN

Memory management enable

RIW

TBIA

Translation buffer invalidate all

TBIS

Translation buffer invalidate single

SID

System identification

TBCHK

Translation buffer check

1A 1 is Implemented as specified in the VAX Architecture Reference Manual (DEC STD 032).
2An R following the note number indicates that the register is cleared during power-up.
3 A 2 is Implemented as specified in the MicroVAX CPU Chip Specification (A·PS·2120887-O-O).

3-16 VAXstation 2000 and MicroVAX 2000 Technical Manual

3.2.1.4.1 Interval Clock Control and Status Register (ICeS)
The ICeS register conH'(lls the interval timt;~r (IN1TIM. L) interrupt The
ICeS register i!i implemented as specified in the VAX architecture reference

ma.nual but H
contains a single bit to enable or disable the interval timE'r
interrupt. Hgure
shO\\lS the to.rm.at of the ICeS register.
Figure 3-5:

Interval Clock Controf and Status Register (ICeS)

S
i

[ :

lIEN

£)

I .. I
0 ..

Data Bit

Deflnlllot'l

31;7

Not used. Read as zero (0). Ignored on writes,

lEN

Interrupt enable fbit 6}, When this read!wrlte hi! is S{'t
intt.l'val ti.mer interrupts are disabled. At F<,tver-{m. lEN
:is cleared.

5:0

.
_-- Not used. Rea.d as:.z:ero ((ii. Ignored on v,:rites.._---

3.2.1.4.2 System fdentification Register (SID)
The sm register (internal pwcessor register 62, read-only) has the format

sho,,"\'n in Figure 3,,6. The n'PE field has the value 08h which identifies
the processor as a DC333 h1kwVAX CPU chip, The contents of the
dependent Held are unpredictable.
Figur'e 3-6:

System Identlficanon Register (SID)

3.2.1.4.3 Console Saved Registers
The
saved
(SAVISP
, program cou.nter
the internlpt stack
word (PSL),
at the tim€ a
restart OCCUfS.
for more information on the restart
VS410 System Module De!a!!ect Description

3-11

3.2,1,5 Interrupts and Exceptions
Both interrupts and exceptions divert program execution from its normal
fl.o~\' by pushi.ng the processor status and program counter onto the stack and
then beginning execution at the address found in one of the interrupt vectors
in the system control block (SCB), An exception is typically handled by the
current process (for example, an arithmetic overflow), while an interrupt
typically transfers control outside the process (for example, an interrupt
from an external hardware device),
3.2,1.5.1 Interrupts
The interrupt system is controller by the interrupt priority level register {IPL,
internal processor register 18),. the software interrupt request register (SlIm,
internal process register 20), and the
interrupt summary register
(SISR, internal process register 21). Figure
shows Ihe format for ali
three of these registers.
Figure 3-7:

interrupt Control Registers (IPL, IRR, SISR)

3
1 5 4
IGNORED, RETURNS ZERO (0)

.3
1

3
1

3-18

-:I PSt 20 ~ U<l ~ lPL
4,

IGNORED

1 1
6 5

IR~~~~ : SHUt
1 0

PEENDING SOFTwARE INTERlWPitS 'I !
01 :SISR
Ir
________
__D_·_C__B_A__g__e____
1_6__s__
4_3__2____
~~

VAXsta!!on 2000 and MicroVAX 2000

1.~

Manual

3.2.1.5.1.1 Interval Timer Interrupts
An interval timer interrupt request is generated every 10 milliseconds by a
signal on the IN'ITIM pin which is derived from the processor dock crystal.
This interrupt is at IPL16h and uses interrupt vector OCOh .
. The interval clock control and status (ICCS) register (internal processor register 24, readlwrite) controls interval timer interrupts. Figure 3-5 shows the
format of this register.
3.2.1.5.1.2 Device Interrupts
All interrupt requests from the system's 1/0 controllers are sent to the interrupt controller which ranks their priority and sends a single interrupt
request to the CPU. The number of the interrupt is determined by the interrupt controller according to the identity of the requesting 110 controller.
See Section 3.5.9.5 for a listing of the 1/0 controllers. Table 3-3 lists the
external interrupts that are signalled to the CPU via one of three CPU chip
pins.

Table 3-3: External Interrupts
CPU Pin

Interrupt

ERR

Machine check (bus error)

1N1TIM

Interval timer Interrupt; level 16h

IRoo

Device interrupt; Ieve114h

The PWRFL, IRQ3, lRQ2 t and IRQl interrupt pins on the CPU chip are not
used and are held in the inactive state so the processor can never generate
an interrupt on these lines.

VS410 System Module Detailed Description 3-19

3.2.1.5.2 Exceptions
The CPU chip recognizes six classes of exceptions, as follows.
Exception Class

Instances

Arithmetic trap/fault

Integer overflow trap
Integer divide by zero trap
Subscript range trap
Floating overflow fault
Floating divide by zero fault
Floating underflow fault

Memory management

Access control violation fault
Translation not valid fault

Operand reference

Reserved addressing mode fault
Reserved operand fault or abort

Instruction execution

Reserved privileged instruction fault
Emulated instruction fault
Extended function fault
Breakpoint fault

Tracing

Trace trap

System failure

Memory read error abort
Memory write error abort
Kernal stack not valid abort
Interrupt stack not valid abort
Machine check abort

3.2.1.5.3 Machine Check Exceptions
A machine check exception results from either an internal CPU or FPU
chip error or from the assertion of the ERR signal by external logic. The
ERR signal is asserted when a RAM storage parity error is detected during
a memory read cycle, which results in a machine check exception with a
machine check code of either 80h or 81h. (Section 3.3.1.4 describes RAM
storage parity checking.)
Figure 3-8 shows the parameters that are pushed onto the stack when a
machine check exception occurs.

3-20 VAXstation 2000 and MlcroVAX 2000 Technical Manual

Figure 3-8:

Machine Check Exception Parameters

BYTE COUNT (<TOGO.OOOCh)
MACHINE CHECK CODE:
VAP -

MOST RECENT ADDRESS

INTERNAL STATE nATA
PC
PSL

Byte count-The byte count is nOna,GOOCh.
Machine check code (in HEX)-The machine check code is listed below.
\lAP-Most recent virtual address, Not valid for machine check code
81h,

PC-Program Counter at the star!. of the current instruction,
PSL-Current contents of program status long'l,\,otd,
Code

DenniHon

Impossible microcod£ sta!t2
3

U ndeHned FFU eHor ('('Ide 0

UndeHnedFPU error nxie 7

Undefined memory management status T13 ruls,
status 1M '" OJ

ProCt~ss, PTE address In PO ~}"j,K~

Proct'"!ls PTE addres:: in Pl nrace

Undefined interrupt lD cod.!.'

Reild bus error, VAF is virtual address

10 System Module Detailed Descr!pHon

3-21

3.2.1.5.4 System Control Block

The system control block (SCB) is two physically-contiguous pages (1024
bytes) containing the vectors for servicing interrupts and exceptions. The
first of its pages is pointed to by the system control block base register
(SCBB, internal processor register 17). Figure 3-9 shows the format of the
SCBB register. Table 3-4 lists the SCB format of the vectors used by this
system.
Figure 3-9: System Control Block Base Raglster (SCBB)

332

1 0 9 9 8

10\01 PHYSICAL LONGWORD ADDRESS OF SCB

Data Bit

Definition

Must be zero.

29:9

Contains the physical longword address of the first
page of the system control block.

8:0

Must be zero.

3-22 VAXstation 2000 and MicroVAX 2000 Technical Manual

Table 3-4: System Control Block Format
Vector 1)peI

Vectors

Veetor Names

000

Unused

004

Machine check1

Abort

008

Kemel stack invalid

Abort

OOC
010

Power fan
Resv/Priv. instruction

Fault

014
018

Customer resv. instr
Reserved operand

Fault

OlC

Reserved addressing mode

Fault

020

Access control violation

Fault

024

Translation not valid

Fault

028

Trace pending

Fault

02C

Breakpoint instruction

Fault

030

Unused

034

Arithmetic

038:03C

Unused

040

CHMK

Trap

044

CHME

Trap

048
O4C

CHMS

Trap

CHMU

Trap

050:080

Unused

084:0BC

Software levels 1·15
Interval timer 3

OCO

Interrupt

FaultlAbort

Trap/Fault

Interrupt
Interrupt

lRefer to Section 3.2.1.5.3.
2Refer to Section 3.2.1.5.
3Refer to Section 3.2.1.5.1.1.

VS410 System Module Detailed Description 3-23

Table 3-4

Control Block Format

Vt'dors

Ve'C.tor Names

OC4

Unused

nes

Emdatiol1 start

oee

Emulation. continue

ODO:OFC

Unused

l00:1FC

Adaptt't vectors

Interrupt

200:3FC

Device vectors 4

InterruFt

3-24

Vector Types

Faul!

VAXs!ation 2000 and M!croVAX 2000 Technical Manua!

3.2.2 OC331 FPU Chip Specifics
Figure
shows
pinout for the FPU chip.
and explains their function,
Figure 3-10:

,3 -5 lists the FI'U pins

De33? FPU Chip Pinout

fPC;
\'I\f1,1't

VS410

Module Detailed

Table 3-5:
Pin

Pin Functions

DC337 FPU

Signal

Description

fPU Data: and Address Bus
67:60
43:36

VDAL07:00
VDAL31:24
VDAI.1.3:16

is a bidlrectloml1
The data and address bus (VrrADi
bos. fl is used to
data between the CPU
and the EPU chip. The
chip is
bus master.

VDA.LlS;08
32:25
10:3
fPtl Control
58::;6 VC52:0

The control status Hnes
S!,1tUS about the current
VCS1:0 ilre valld when FrS L is asserted.
are inputs whicb lncUca~e the tvpe of informatiDn being transferrt'd. VeS2 is an
drain O\.HF')t
'Nhkh is active L when the current bus
is an externa.! processor response enabie ilnd the
has comFleted
Ihe current commanded

open

EPS

(51:0 WR

Bus Cyde Type

WrHe external processor commami

1'1

Rt'ilU external proceS50! data

Write external processor dati'!

Command to externaJ processors

HI'"

E'>:temal pron.'ssor response enable

j~ used
the CPt:
to lnd.ici\te the
The write
HH; FPU, the
of d,lt,1 ilt the CPU.
direction of
tra nsfe.rred lr:L1 n1
write slgnallndicll!es that da.ta is
the CPU,

VWRfTE

EPS

3-26

VAXstation 2000 and MicroVAX 2000 Technical Manual

th~ CPU
all communication between the CPU chip
chip.

DC337 FPU

Pin Functions

Pil'l

Mis(eUaneous

-------------_._,-,59

This signal is not used and. is connected to ground.

ll1i~ pin is connected to the back bias generator.

It ell n Vt:
used to test the function of the back bias generator or to
supply back biasins during a diagnostic debug proce-dvre.

CPRESET

The DC524 sta,ndard cell a,sserts Ihe t('sel slgl'lal (Crru::>
SET t) to force the
to It known, inHlal state.

CLKO

This pin is not used.

eLKl

This input suppHe& a 40 MHz square wave ckH.:J;
to the fPU chip from an 0501at01. This is the same
that is sent to the CPU
jumperW4 can be removed
to d.isconnect the oanlstor from the FPC chip for diagnostic purposes.

3.2.2.1 FPU Bus Cycle Descriptions
The FrU chip recognizes five types of bus eyries,
..

FPU external processor command ",;rite

•

OtJu~t external processor command ,,,,,rite

External processor read

External pr(lCeSSOf \\'rite

External processor response enable

3.2.2.1.1 FPU External Processor Command WrUe Cycle
In an
external processor command wrlte cycle, the

chip

the instruction opende to be read and executed by the FPC chlp.. An
extl:~rnal processor comm,md cyde last";
FPLT dock phases
200
Th~, CPt] chip drives the
onto CSUJ
The CPU then loads the comrnand onto the VDAL
and asserlf/. FPS L.
The FPU chip reads the oat,l on the VDAL bus. The
EPS Land \'v'RITE L \0
tl'!e
processor command

System Module Detailed

3.2.2.1.2 Other External Processor Command Write

In an 'other' external processor command write cycle, the CPU chip outputs
the instruction to be read and then executed by an external processor other
than the FPU. If this is encountered, the FPU suspends operation of any
instruction in progress and disables the output from responding to the CPU
read cycle or response enable cycle until another FPU command is received.
3.2.2.1.3 External Processor Read Cycle

In an external processor read cycle, the CPU chip inputs information from
the FPU chip. An external processor read cycle lasts eight FPU clock phases
(nominally 200 ns). The CPU chip drives the cycle status onto CS1:0 and
WRITE L, then asserts EPS L. The FPU chip responds by placing the required
data onto the VDAL bus. The CPU chip reads the data off the VDAL bus
and deasserts EPS L to end the external processor read cycle.
3.2.2.1.4 External Processor Write Cycle

In an external processor write cycle, the CPU chip outputs information to
the FPU chip. An external processor write cycle lasts eight FPU clock phases
(nominally 200 ns). The CPU chip drives the cycle status onto CS1:0 and
asserts EPS L and WRITE L. The CPU chip then places the outgoing data on
the VDAL bus and deasserts EPS L and WRITE L. The FPU chip responds
to the deassertion of EPS L by reading the data off the VDAL bus.
3.2.2.1.5 External Processor Response Enable Cycle

In an external processor response enable cycle, the CPU tells the external
processor that it is ready to accept a completion signal and that it controls
the bus. The CPU drives the cycle status onto CSl:0 and WRITE L, then
precharges and tristates the CS2line. The FPU, when it has completed the
current instruction, puts the status on the VDAL bus and pulls CS210w with
an open drain output device during the time the CPU asserts EPS L.
3.2.2.2 FPu/CPU Communications Protocol

The FPU/CPU communications protocol permits the CPU chip to communicate efficiently with the FPU chip. The general protocol for external processor communication follows these steps:
1. The CPU chip initiates the interaction by placing an FPU command
on VDAL31:00, the FPU external processor command status code
on CS1:0, and asserting WRITE L and pulsing EPS L. The FPU recognizes this as a command write cycle. Any instruction in-progress
within the FPU is immediately aborted. The FPU decomposes the
command to determine the operation to be performed and the number and size of the operands reqUired.

3...28 VAXstation 2000 and MicroVAX 2000 Technical Manual

2. The CPU chip next fetches the required operands and executes one
or more external processor write cycles to transfer them to the FPU.
3. After the CPU chip has transferred the last operand, it asserts an
external processor response enable code on the CS1:0 lines and
pulses EPS Leach microcycle that the CPU has control of the bus.
4. To signal non-completion of operations, the FPU does not affect
CS2 when the external processor response enable code is on CS1:0
and EPS is low.
5. To signal completion of operations, the FPU asserts CS2 L when the
external processor response enabJe code is on CS1:0 and EPS is low.
At this same time, the FPU asserts the status of the just completed
operation.
6. The CPU chip recognizes the CS2 L and reads the status information
on the VDAL31:00 bus.
7. The CPU chip requests the status information again and is sent the
status of the completed operation again.
8. The CPU chip next executes zero or more external processor read
cycles to read the results of the computation, if any.

3.2.3 40 MHz CPU/FPU Clock
The processor clock input frequency is 40.0 MHz. This results in a microcycle time of 200 ns and an 110 cycle of 400 ns.

3.2.4 DMA Bus Access
The ThinWire Ethernet controller located on the network option module is
the only controller in the system that can request DMA control over the
system bus.

VS410 System Module Detailed Description

3-29

3.2.5 Memory Management
This section describes the management of the memory addressing space.

3.2.5.1 Virtual Memory Address Space
The CPU provides four gigabytes ( 232) of virtual memory address space.
This virtual space is divided into two sections, process space and system
space. Process space is further divided into a PO region and a PI region as
shown in Figure 3-11. Process space (PO) virtual memory is mapped to physical memory by the PO page table which is defined by the PO base register
(POBR) and the PO length register (POLR). Process space (PI) virtual memory
is mapped to physical memory by the PI page table which is defined by the
PI base register (PIBR) and the PI length register (PILR). System space virtual memory is mapped to physical memory by the system page table which
is defined by the system base register (SBR) and the system length register
(SLR). The PO region is accessed when address bits VDAL3I:30 are both
O. The PI region is accessed when address bit VDAL3I is 0 and VDAL30
is a 1. The system space is accessed when address bit VDAL31 is a 1 and
VDAL30 is a O.
3.2.5.2 Physical Memory Address Space
The CPU provides one gigabyte ( 230) of physical memory address space.
Figure 3-12 shows the physical memory address space.

3-30 VAXstatlon 2000 and MicroVAX 2000 Technical Manual

FIgure 3··11:

Virtual Memory Address Space

00000000

PO REGION
3FFFFFFF

40000000
Pl REGION
'lFFFFFFF
1--

80000000

...,

~"""

SYSTEM
REGION

BFFFFFFF
COOOOOO(l

RESERVEO
REGION

FFFF'FFFF

Figure 3-12:

PhYSical Memory Address Space

00000000

MEMORY
SPACE

lFFFFFFP'
20000000

I/O
SPACE
3fFFFFFF

Module

3.2.5.3 Memory Management Control Registers
Memory management is controlled by three internal processor registers.
These registers are the memory management enable (MAPEN), translation
buffer invalidate single (TBIS), and translation buffer invalidate all (TBIA).
MAPEN contains one bit which enables memory management (MAPENO)
as shown in Figure 3-13. TBIS controls translation buffer invalidation (Figure 3-14). Writing a virtual address into TBIS invalidates any entry which
maps that virtual address. TBIA also controls translation buffer invalidation
(Figure 3-15). Writing a zero into TBIA invalidates the entire translation
buffer.
Figure 3-13:

Memory Management (Mapping) Enable Register (MAP EN)
210

MME

Figure 3-14: Translation Suffer Invalidate Single Register (TSIS)

VIRTUAL ADDRESS

Figure 3-15: Translation Suffer Invalidate All Register (TSIA)

3-32 VAXstation 2000 and MicroVAX 2000 Technical Manual

3.2.5.4 System Space Address Translation
A virtual address with bits 31:30 - 2 is an address in the system virtual
address space. Refer to Figure 3-16. System virtual address space is
mapped by the system page table (SPT), which is defined by the system
base register (SBR) and the system length register (SLR). The SBR contains
the physical address of the SPT. The SLR contains the size of the SPT
in longwords, that is, the number of page table entries (PTEs). The PTE
addressed by the SBR maps the first page of system virtual address space,
that is, virtual byte address 80000000 (hex).
3.2.5.5 Processor Spaca Address Translation
A virtual address with bit 31 - 0 is an address in the process virtual address
space. Process space is divided into two equally sized, separately mapped
regions. If virtual address bit 30 - 0, the address is in region PO. If virtual
address bit 30 - I, the address is in region PI.
3.2.5.5.1 PO Region Address Translation
Refer to Figure 3-17. The PO region of the address space is mapped by the
PO page table (pOPT), which is defined by the PO base register (POBR) and
the PO length register (POLR). The POBR contains the system virtual address
of the POPT. the POLR contains the size of the POPT in longwords, that is,
the number of PTEs. The PTE addressed by the POBR maps the first page
of the PO region of the virtual address space, that is, virtual byte address O.
3.2.5.5.2 P1 Region Address Translation
Refer to Figure 3-18. The PI region of the address space is mapped by
the PI page table (plPT), which is defined by the PI base register (PIBR)
and the PI length register (pILR). Because PI space grows toward smaller
addresses, and because a consistent hardware interpretation of the base and
length registers is desirable, PIBR and PILR describe the portion of PI space
that is not accessible. Note that PILR contains the number of nonexistent
PTEs. PIBR contains the virtual address of what would be the PTE for the
first part of Pl, that is, virtual byte address 40000000 (hex). The address
in PIBR is not necessarily a valid physical address, but all the addresses of
PTEs must be valid physical addresses.

VS410 System Module Detailed Description 3-33

Figure 3-16:

System Space Virtual to Physical Address Translation

S\'A
f::y~rf:M

ViFi:'l.,)At

Ai;CAiSS;
3
1

I:;:>: : :

~~r1'~'~:"(.r,,;.

AO:.:,PE'S£:

Cf- i)t,r ~\

3-34

VAXstatlon 2000 and MicroVAX 2000 Technical Manual

Figure 3-17: PO Vlrtua. to Physlca. Addr... Translation

332
1

SYSTEM VI"TUA~ lONGWOIIO ADDRESS OF POPT

M8Z

;!"OBR

2 2

3 3
, 0

2
9

PVA;
(PROCESS VIRTUAL .........+-"...............,..............,..............,..............,....................1...1,......,.'-'
AODRESS)
EXTRACT AND
3
CHECK LENGTH
1

ADO

YI£tDS

'ETCH BV SYSTEM SPACE
TRANSLATION ALGORITHM,
INC..UOING LENGTH AND
KERNEL MODE ACCESS CHECKS,

PFN

CHECK ACCESS

THIS ACCESS CHECK
IN CURRENT MODE

9 8

PHYSICAL ADDRESS
OF DATA

VS410 System Module Detailed Description

3-35

Figure 3-18:

P1 Virtual to Physical Address Translation

;PISR

3
I

2 2
2 1

I: :: :+f: :: :I:::H+:o~+HH+~+:
3 3

1 0

9 8

eYTE

PVA;
(PROCESS VIRTUAL ~...I..+I....I....I..""'I..I....I...""'I..I....I...""'L..J....I....I...IL..J....I...t-J.....L....I....I...I.....L.""TU
ADORESSI
EXTRACT AND
3
CHECK LENGTH
1

o
ADD

VIELDS

I::::::::>H+~ +~RH +H::::::::If I
2 2
1 0

3 J
10

FETCH BY SYSTEM SPACE
TRANSLATION ALGORITHM,
INCLUOING LENGTH ANO
KERNEL MODE ACCESS CHECKS.

PFN

PTE; 1

CHECK ACCESS 2

THIS ACCESS CH ECK
IN CURRENT MODE

9 8

PHVSICAL ADDRESS
OF DATA,

3-36 VAXstation 2000 and MlcroVAX 2000 Technical Manual

3.2.5.6 Page Table Entry
The format of a valid PTE is shown in Figure 3-19. If bit 31 (the V bit) is
clear, the format of the remaining bits is not examined by the hardware.
Figure 3-19:

sS
1 0

Page Table Entry (PTE)

222 222 2 2
166 4 3 2 1 0

o
PAGE FRAME NUMBER

Data Bit

Definition

Valid bit (bit 31). This bit must be set.

PROT

Protection code (bits 30:27)

Modify bit (bit 26)

Must be zero

OWN

Owner bits (bits 24:23)

20:0

Page frame number

3.2.6 Processor Restarts
When the CPU receives a RESET or HALT or detects severe corruption of
its operating environment, it performs a restart process. This restart process saves some of the contents of the internal processor registers (SAV·
lSPt SAVPC, and SAVPSL), changes the CPU to unmapped memory mode,
and begins program execution in the system ROM at address 2004.0000.
Bits 14:8 of SAVPSL contain a restart code which indicates the cause of the
restart. The restart codes (in hex) are listed below.

VS410 System Module Detailed Description 3-37

Restart

Definition

HALT asst'cted (See Section 3,2.6,2

Power on

!nh~rrupt stack not valid

Machin€' check

HALT instrurtion executed in kernel mode

5(:B vector bits 1~O := 11

SCB vector bits 1:0 "" 10

CHt\b: executed while on

ACV or TNV during machine check excepti0n

ACV or T:"~V during kernel stack not vaHd exception

machine check or kernel slack no! vaUd "'"C"',,,,,,

sets the state of the chip as follows,

The restart
Register

Contents

SAVISP

Saved Interrupt stack

SA VPC

Saved PC

SAvrSL

Saved PSL bits 31:16 and 7:t' in bits 31:16 and 7J)
S,m:d MAFEN D ! n bit 15
Saved restart code inb.its 14:8

Sf'

bv'bit;

Stack

26: 2.t

PSl

041F OOOG (he)

20040000

l>.tAPEN

SISR

ASTLVl

Ices

011

Ail other

3-38

VAXstatlon 2000 and MicroVAX

Technical

3.2,,6.1 Power~On Restart
The system performs a pOl,\'er-cn restartwhenE'ver power is S\<;itched on
The CPU's RESET pin (CPRESET L signal) is held 10'1-'" by the sta.ndard
the system. The stnndard (elI holds
durIng the po\,\'er·mt initializati(m
CPRESET low to ensure that tbe.
sees an adequate number of dock
cycles while in the reset state.
Initia!izatkm is complete, the standard

cell aBm'>'!> CPRESET to

The

performs a POw€'!·on resta.rt Vl'iHl

a restart code of 3 in bitt;

3.2.6.2 HAl..T Restarts
The system performs a HALT restart when the CPlJ"s HALT pin (HALT L
signal) goes low. The
L sign<11
).0\',· whenever the
does
one of the 1:\'\'0 foHowing things.
1.

Pressing the operator's halt button on the rear of the

Pressing the BREAK key on the tennlnaJ connected to serial line :3
(printer
.vith a BCC08 console cable,

box,

lJpon receiving the }-V·\LT L signal, the
enters console
The:
operator can then examine and alter storage,. run diagnostics. or initiate a
system bootstrap, The CPU performs a HALT restart hith a restart code of
2 in bit::: 14:8 SAVP5L.

3.2.6.3 HAL.T Code Register (HLTCOD}
The halt code register
is a readllvrite long-word register at phys;
cal address 2008 . 0000. It i5 intended [(::>! use
the Hor"fresident firmv,,,are
which handles a processor restart.
program move:, internal
processor register
to HLTCOD S(~ that the restart code can be extracted without
of the
or
RAM iocatlons.
Figure 3-20:

Halt Code Register (HLTCOD)

(md ille SeD
r
Ci.mtei7t~; pf
miisl he uiilC:ne;'cr
CI'Y1',: of1tc:,.:"i'::f' t!J(.' ~mii:C

net

Modu!e Detailed

3-39

3.3 System Memory
This section describes system memory (Figure 3-21), including the system
RAM, video RAM, and ROM in detail. Chapter 4 describes the option
memory module in detail.
Figure 3-21: System Memory

-3-40 VAXstatlon 2000 and MicroVAX 2000 Technical Manual

3.3.1 RAM Memory
The system supports up to 16 megabytes of RAM memory. The actual
amount of RAM depends upon the option memory module installed. The
data path to RAM memory is 32 bits wide. Data integrity is checked by a
parity bit associated with each byte of memory.
3.3.1.1 System Module RAM
The system module contains 2048 Kbytes of RAM which occupies physical
addresses 0000.0000 through 001F.FFFF. The RAM is stored in two banks
of 32 individual 256Kx1 chips which are in a zig-zag in line package (zip
packs). The chips have one data input line and one data output line which
connects to one data bit on the BDAL31:00 bus. When the chips are properly
addressed and selected, a single data bit from the BDAL31 :00 bus is written
to or read from the address location on each of the 32 chips. The system
also provides memory refresh to the zip packs. Figure 3-22 shows the block
diagram of two zip packs in bank 0 for RAM bits 31:30.
Figure 3-22:

RAM Zip Packs Block Diagram

DRAM

8 (O) (0) 2
IIA08
IIA07

IIA06

IoIA05
MA04

MA03

llA02
IIAI»
MAOO

---

DRAM

SM031
IOA1.3O- 8 (0) (0) 2

,HI

--=
::s ~ ~~~

13 A

IT1
,AI

14 A5
15 A4

18 A3

18A3

10 A2
11 A1~
II AO

10 A2

11 Al)

II AO)

-C

7 (lit)

DI-

~~~~

,. 7 (WE)

VS410 System Module Detailed Description

)

3-41

aft'
storage cens in
which are a.rranged in a.n
anav of 256 words
these cells
is d(me in 0''10 steps, The
step
and
the second step selects the column
location, Durin.g tl,t,;' first
an address from the DC524 stan.dard cell is put on the memory'address
bus and the R,l\S control signal is asserted, One of the
tOws is now
selected, BefoH: the second
is slarted. the
standard cell floats
the :memory address bus to dear Ihe W\V address, Durin,s the second step,
another address from the DC524 standard cell is put on the memory address
bus and the
control signal is asserted The ro~v and column addresses
have nov.' uniquely defined i.l single
cell for vvriting to or reading
f:om. If the system is writing to RAM
3--23.1., the final
asserts the WE control signal and puts
data
onto the CPU data bus
which is then stored in the zip pack chip It the
is
from
RAM
Figure
the final
outputs the value of the
data bit onto the
data bus. This
occurs simultaneously on all
bu;;, There are aIEl) four lip
Figure 3-23:

Data In (Write) Memory Timing Cycle

RAS ~"--_ _ _ _ _ _ _ _ _ _- ' /
CAS

---~

........

.... 0-08' ~< ~ ::~

r:,AR~Y

=:X·~'::~:::S';;·0\::;Y>\:~§\%:{:.;::§.{{{\~;\
/

WRl'i£:
Cl'Cl.£

n:. 'M'!!l1:
~

MOOWY
'Mtt'iE Cyeu:

Rr;.~p

3-42

VAXstation 2000 and MicroVAX 2000 Technical Mat1ua.~

Figure 3-24: Data Out (Read) Memory Timing Cycle
RAS ~,-_ _ _ _ _ _ _ _ _----,/

,------'/
"C::

WE _ _ _ _ _ _ _ _/

-------------«

DATA OUT

3.3.1.2 Video RAM
The video RAM (VRAM) is a dual port 64kx4 RAM. There are four VRAMs
on the system module. Addressing these VRAMs is done similar to the
DRAMs so addressing is not covered here. The VRAMs each have four
l024-bit shift registers on their output which contain four rows of video data
that is put onto the video bus (VID15:00). These shift registers are loaded
once every four scan lines at the start of a refresh cycle by raising DT/OE
and asserting VRAS. This allows the current row of video data to drop into
the shift registers. There are two counters inside the standard cell; one is a
refresh counter that keeps track of the row address for the refresh and the
other is for keeping track of where the system is in the VRAM for the correct
dots.

The video bus is then multiplexed down by a johnson style counter to four
lines which go to the standard cell. The standard cell then generates the
proper signals to display the video data, along with the cursor data, onto
the video screen.

VS410 System Module Detailed Description

)

3-43

3.3.1.3 Option Module RAM
A memory option module can contain up to 14,336 Kbytes of RAM which
begins at physical address 0020.0000 and continues through contiguous addresses to the capacity of the module. The presence and size of a memory
option module can be determined by reading the MTYPE bits of the configuration and test register (CFGTST) (see Section 3.11.2).
3.3.1.4 Memory Parity Checking
The system generates byte parity when writing to RAM memory and checks
byte parity when reading from RAM memory. Parity checking applies both
to CPU accesses and to DMA accesses generated by the network interconnect option. Only those bytes selected by the processor byte mask are affected and checked. Two 110 registers are associated with the parity system:
the memory system error register (MSER) and the memory error address
register (MEAR).

Parity generation and checking is active only in the physical address range
0000.0000 through OOFF.FFFF. Any read reference within this range to uninstalled memory may result in a parity error. References to uninstalled memory or nonexistent devices, in the physical address range 0100.0000 through
3FFF.FFFF, return unpredictable data upon reading and ignore this data
upon writing. No parity error ever results from references in this range.
3.3.1.5 Memory System Error Register (MSER)
The memory system error register (MSER) is a longword at physical address
2008.0004 that controls the parity generation and checking logic and indicates when a parity error has been detected. Figure 3-25 shows the MSER
register.
Figure 3-25:
3
1

Memory System Error Register (MSER)
9 8 765

2 1 0

3-44 VAXstation 2000 and MicroVAX 2000 Technical Manual

Data Bli

Ddinlhcm

31:9

CDO

Memory Cooe

fbit

the state of the PER

hi t (set' bt'kw{)

No! used, read a.;:, O.

PER

erro.r detection is el1<lbled (hit PEN

V\ihen

set at lhe. end 01 ,wy CPtl 01' DM/', read
in RAM mem!,)fV which contaIns lncorrer!

PER

of PER captures the number of the
the incorrect
in nw MEAR
and asserts
the CPU and to the nehl'o.ri< controller
module
nf'~~:t (.r n,) fL-lt.? ,ftt ret' rr' {liC.t ~'Pr"C
or I)tvt<;\ n i.1C brio.;
(!€:'Hr~
ERH ~g£Hn:
1.1 UiJ.il -next bus Cy'df \,"lir :5 r5~;u~:C bv t.h~ CPU
a. n~:) ..
fhh~+, (ht:(~,t)f('t:r~i,
of \\dl,:_~d'H~t' tht:' F'iH~
E?f",.
il CPU ('r
,ha~', t:kliif"f'J. f~f;'-l,

th(1 PER

()n((;\

stru<'tlo~1

H:r:~('}

hu~

cyclE'

It.

lilP

hm"/!;,V!'f,

nelit

DMA

(y(-!(~~;

t"hc=;t

~urh

i7t

hol.ler

nH:,\Plh:::r
tf1f
inj'orrn it.~ drh/€f

mt~'si

ilnd

;;ummM)"

when
it

th~'n

contrcfHf?f,

-err<)rs ,,",shieh
,J€?'~,

PER

U'{€'

f'lf"tlNork

tht'

netI,'%fY

('Of\-

[1f\,.'! /~

tnfnf.~

:S1gn~tl

scftt"-"tif€" 1;vh€J'l it
dt~{e:ie'd

df:'tt:cte.:i
but

cf
cons!?:>
thE' CPU)

~O~~tH~e:,c,;~!~t';'; (i~'n g:::::,~:

undet()('ted.

pill'lly ,'In,,' is-

t'c";:.'!
(0

O"lU~t

{?rs

d~ti?·,,~:' ~on

i.~"

'~~.;lth1Jtlt

dei.~:'(·d
and
(h",(~
(€'VF"
pttrit.} f,~tr0f not

df'~

tht:~

n:~d

tlw

t:'J.nd f'Er~ is nc,1 ~d·
CPU (1; OH' ni"',

f'l,lrnh7~,.

DC,t

l')("<"urri:.~d

eHht::r

a pr~i-

thf

CPU

()1'

(:PC
[)

fnilY

\t,,\

fV-

fontF()}h:!

CIlue-j durIng DMA

PEH t~ df;;~n0:: hy
b~,\nJ

h.~ th!.::- '~~SEH. n~gi\;ter \-\ij.th i~ 1
:he P E f'{" L"H r'(1:··j~
,~'\ 7:FnJ ,h')l!;':'s, n0~ ;:\fr~ct PEn, - PEP
fds;~';' ·dtJ:c'ired UPO~'(

vvht<:h

t~('1n

VI/rHt'in{()rtP,:·t

t(i

r;l,:~t

PfJ\

f\f:~

triUS,
tt1k~'
(Jr({~ trlf'~"1

tdEA R 1~

n"ilt ~i ':
i ],)S reiii'1,''{.vr~te bit. \'\-I',~~:,;,~"£ se:,
ht:; \...·ril:ti:':·'~
r,Nrit~:l
\)«·<es;.;'i:';~~
~o n,,"\~~'~
\:·;:n~cl.fJ

On'
it~l Errelt}

fi'ftd~,

thii" C{',Htpnt:;'

l"v,h~:,n

t'f.'t'rn,·

l~i,';,~:l

ct~~~:Hj~~d dutit;12; P(},. 'Vt)r~·op and ffii..1.Si t\~

InA! op{~rati()n.

Detailed

3-45

Data Bit

Definition

PEN

Parity Enable (bit 0). This read/write bit must be set to enable the
detection of incorrect parity to set the PER bit. When PEN is dear,
parity errors are not recorded and have no effect on system operation.
This bit is deared during power-up.

3.3.1.6 Memory Error Address Register (MEAR)
The memory error address register (MEAR) is a longword at physical address
2008.0008 which captures part of the address of a byte that has incorrect
parity. Figure 3-26 shows the MEAR register.
Figure 3-26:

Memory Error Address Register (MEAR)
1 1
5 4

3
1

o
FAILING ADDRESS
BITS 23:09

Data Bit

Definition

31:15

Not used. Read as O.

14:0

Failing address. These read-only bits record bits 23:09 (the page number) of the physical address of the failing byte when a parity error
is detected. They are latched at the same time that bit PER of the
MSER register is set and they are valid only when PER is set. In the
event that multiple parity errors occur before PER is cleared, MEAR
contains the address assodated with the first error (that is, the error
which changed PER from 0 to 1).
If the MEAR register is read while PER is dear, bits 23:09 of the MEAR

3-46 VAXstation 2000 and MlcroVAX 2000 Technical Manual

3.3.2 ROM Memory
The system module ROM contains processor restart, diagnostic and console
code, and 1/0 device drivers. There is also a separate ROM located on the
system module that contains the ThinWire Ethernet hardware address. All
option modules contain their own separate ROM memory as well.
3.3.2.1 System Module ROM

The system module contains four 28-pin ROM sockets which can hold 128K
bytes or 2S6K bytes of data depending upon the type of ROM chips used.
Jumper W3 on the system module adjusts the sockets for 27256 or 27512 (or
equivalent) ROM chips. When 27256 chips are used, W3 must be on pins 2
and 3. When 27512 chips are used, W3 must be on pins 1 and 2 as shown
in Figure 3-27. ROM data appears at physical address 2004.0000 through
2007.FFFF (256 Kbytes). If 27256 chips are used, their image appears twice
in this address space. The data path to the system module ROM is 32 bits
wide.
Figure 3-27: System Module ROM Circuit Diagram (High eyte)

27512

rl"

WAl17 1
2

05
04
03
02

17
16
15
13

~01~
12
DO 11

+5V 3

MA17
MA16
MA15
MA14
MA13
MA12
MA11
WAL09
WAL08
WAL07
WAL06
WAL05
WAL04
WAL03
WAL02

ROMCS

..031
MOJO

..029
M028
M027
i00i026
M025
..024

1
A15~
27 A14
26 A13
22
23
21
24
25
3
4
5
6
7

A12~

A11
A10

A09~

A08
A07
A06
A05
A04
AOJ
8 A02
9 A01
10 AOO
20
22

~-~e?

VS410 System Module Detailed Description 3-47

When the address comes out of the CPU, part of the address VDAL09:02
is latched in the 74F373 8-bit latch and the entire address is latched inside
the DC524 standard cell. The standard cell decodes the ROM chip select
line and puts out a partial ROM address on the MEMAD lines. This partial
address combines with the latched high order address from the 74F373 at the
ROM latch to form the whole ROM address. The ROM instruction is then
put out onto the MD31:00 bus which is then buffered onto the BDAL bus and
on into the CPU chip over the VDAL bus. The ROM is also selected during
the interrupt cycle when the standard cell puts out the interrupt address lines
onto the high order address lines and a partial address on the MEMAD lines
to from the whole address. The interrupt vector is then put out on the MD
bus for the CPU to read.
The system ROMs are word addressed (16 bits) by the CPU for the low byte
address and by the DC524 standard cell for the high address byte (excluding
A15). Address bit A15 is controlled by jumper W3 which allows the VDAL17
bit from the CPU to address it when 64K x 8 ROMs are used or address bit
is pulled high by + 5Vdc when 32K x 8 ROMs are used. During an interrupt
cycle, the standard cell takes control of address lines A14:A to send the
interrupt vector address to the ROM. The ROM then outputs the starting
address location of the interrupt service routine for the interrupting device.
The ROMs chip select and output enable control signals are controlled by
the standard cell. Refer to Section 3.5.2 for information on memory timing
cycles.
There are two types of information reqUired in the system ROMs. One type
is a per part, or per chip, information which contains general information
about each chip such as the ROM index number and the checksum for each
chip. The second type of information is from the set, or collective ROM
storage, of all four chips. The main portion of the ROM which holds the
software and tables is contained in the set of the ROMs. Figure 3-28 shows
the format and starting addresses of the sections within the system ROM
and also whether the section is used on a per part or as a set basis. Table 3-6
lists physical addresses in the ROM that have fixed uses.

3-48 VAXstatlon 2000 and MicroVAX 2000 Technical Manual

Figure 3-28:

System ROM Contents Layout

31 .. 24 23 .. 16 15 ..

8 7..

PROCESSOR RESTART ADDRESS

2004.0000 (SET)

SYS_TYPE

2004.0004 (SET)

VERS

2004.0008 (PART)

03h

02h

01h

ooh

2oo4.000C (PART)

!iSh

5Sh

SSh

2004.0010 (PART)

AAh

2004.0014 (PART)

33h

2004.0018 (PART)

LENGTH

2004.001C (PART)

INTERRUPT VECTOR NUMBERS

2004.0020 (SET)

CONSOLE I/O ENTRY POINTS

2004.0040 (SET)

FONT DESCRIPTOR

2004.0010 (SET)

DIAG REV

CONSOLE REV

2004.0078 (SET)

DIAGNOSTIC DESCRIPTOR

2004.oo7C (SET)

POINTERS TO KEYBOARD MAP

2004.0080 (SET)

REST OF ROM SET DATA AND CODE

2004.0088 (SET)

CHKSUM

LAST LONGWORD (PART)

VS410 System Module Detailed Description

3-49

Table 3-6: Fixed ROM Address Allocations
Address

Description of Firmware

2004.0000

Processor restart address. The hardware begins execution at this address at power-up, at execution of a kernel mode halt instruction, when a break signal is received from the diagnostic consolE' dE'Vi~, when the halt button is preSSE'd, or when the CPU detects a severe corruption of its operating environment.

2004.0004

SYS.TYPE. This longword is the system type register.
The value
for the VAXstation 2000 and MicroVAX 2000 is 0400.0000 as deS('ribed in Section 3.3.2.1.1 below.

2004.0008

Version. This field contains the low eight bits of the version number of the console code for the system firmware. The same value appears in each of the four ROM parts so that a set of chips may be verified to be compatible.

2004.oooC

ROM index number. This value indicates the position of the ROM
part among the set of ROMs used to implement the firmware.
This value ranges from zero for the low byte through three for the high byte.

2004.0010
through
2004.0018

Manufacturing check data. These three bytes are used for a quick verification check of the ROM. The data are 55 h, AA h, and 33 h respectively.

2004.OO1C

This field indicates the length of the ROM part.
of bytes in the ROM in Kbytes, for examNote that the numple, a 64K byte ROM has the value 64.
ber of bytl'S in the ROM set is four times this value, since
there are four ROM parts in the system firmware ROM set.

2004.0020

Interrupt vector numbers. These eight longwords are used by the hardware as part of its interrupt processing.
When a device generates an interrupt, the interrupt controller in the DC524 standard cell sends an interrupt vector to the system ROM so the
ROM can then send the CPU the starting address of the interrupt software routines to service the dE'Vice. The following list indicates the vector generated by the standard cell and the device needing servicing.

ROM part length.

n is the number

3-50 VAXstation 2000 and MicroVAX 2000 Technical Manual

Table 3-6
Add.esili

2004.0040

Fi)(ed ROM Address Allocations
Dt'$cription of Fi.rmwarll

Vf'Ctor

Interrupt SQllfCf

OOOO.03FC

Disk controller

OOOO.03F8

Tape controllt"r

OOGOJ)248

Video controller

OOOD.02H

Vidt'o controller end

{){)(~10254

!\:e\work ('(Inlrolier

00000250

Netwod: conl.rolle,

OOOG02C4

Serial controller tran0,n.litter

O(1(lOJ)2CO

Serial control1t:'! receiver

0: frame

ConsolE' l!() routines. Thert:: are
l" () rOlltine5 ~¥.~,,,"~.,,~
ROM.
for these routines are located at

intervaJs in this an~".
:ZC~)4 . 0070

The system R{)M contains an 8:.:15 char~Kter font

Font

ch,na(ter in the DEC muWnational chal'<)ct(:r 5Ct.
Th.i~ font is used
the
the monochrome
SCrlplt'r is I he siz,~ of
is the
address of ttlt'

2004.0078

console firmware revision nt.lmot't. This word (om;;ins Ihe
"y£ie!11 console firm\,·,H'l" revision nttmlll;I a, lm

'''''"1'''''' firn1\~·a.I.'{' Ievi~1on 1·1umhN. This word cOl1t<l.ins
hrrn (yare revision numb(·", ilS an

In-

20(H.iX'7C
nf
ofztw indiGtl.€'~ that

the

R(itv1.

Module

Table 3-6
Addles!>

. Fixed ROM Address Allocations
Description {If .firmware

,-------

Pointers to keybt'ard map. These two
point to the tahles
used in translating LK20'l main array
to chara.cler codes.
The first \rmgword contains the r>~\J!;!\r"l addt!:?::;s o~ dw b~nn,ir\~
of H'<!' keyboard tables, The
conlcHf':s the phYSKlJ,l
address
the beginning of the
mapping tables .

.RO~v! sf't'dfir data and code.

2C!(l4,0088

needed by the
Last

This space is used for specific da.ta
and can be updated and expanded as needed,

Checksum, Each ROM
tate checksum in its last

eight-bit add and ro·

3.3.2. L 1 System Type Register (SYS.TYPE)
The SYS TYPE register is a read-onlY long-word in the system RO~,l at physkal address 2004.0004, It has the format shovc'n in
The SY
TYPE field has a value of 04h which indIcates that
is a VS410 system
module, The revision and t;'pe dependent fields must be z.ero<

Figura 3-29:

System Type Register {SYS}VPE}

2 :&
43

3~52

1 1
6 5

VAXsfation 2000 and MicfOVAX

TeChriica~

3.3.2.2 ThlnWire Ethernet Address ROM
A 32-byte ROM on the system module contains a unique ThinWire Ethernet
network address for the system. Data from this ROM is read in the loworder bytes of 32 consecutive longwords at physical addresses 2009.0000
through 2009.007C. The network address occupies the first six bytes (addresses 2009.0000 through 2009.0014). The byte at 2009.0000 is the first
byte to be transmitted or received in an address field of an Ethernet packet.
Its low-order bit (bit 0) is transmitted or received first in the serial bit stream.
This ROM is installed in a socket so it can be removed from a failing system
module and reinstalled on the new system module. Figure 3-30 shows the
circuit diagram of the Ethernet address ROM.
Figure 3-30: ThinWlre Ethernet Address ROM diagram

6331

om 9

BDAlO7

(1.46)

BDALOS

(M5)

BDALOS

(1.44) 5

SDAL04

(M3)

SDAL03

(M2)

BDAlO2

2
(MO) 1

BDAlO1

(1.41)

ELAOS

14 (M)

ElAOS

13 (A3)

ElA04

12 (A2)

ELA03

11 (A1)

ELAD2

10 (AD)

ElDENA

SDALOO

MA-xoeaCl-a7

VS410 System Module Detailed Description 3-53

)

3.3.2.3 Option Module ROM

Each option module is required to have ROM memory that contains a standard signature to identify the option, as well as firmware initialization and
diagnostic code. Four standard address ranges are defined for these ROM
memories, each spanning 256K bytes. The system firmware and any operating system software that searches to determine what options are installed in
a particular system should examine the signature area of each of these four
ROM address ranges to see whether a valid option ROM is present and, if
so, what type of option. The address ranges allocated in system module
ROM are listed in Table 3-7.

Table 3-7: ROM Address Locations Option Module ROMs
Address Range

Definition

2010.0000 to 2013.FFFF

Network option

2014.0000 to 2017.FFFF

Graphics video or serial line option

2018.0000 to 201B.FFFF

Future co-processor

201C.OOOO to 201F.FFFF

Reserved

Each option module is required to have at least one ROM chip, which must
be connected to the low-order byte (data lines 7:0) of the data bus. The first
byte must contain the starting address of the address range. Its data is read
in the low-order byte of each longword address. If there is only one ROM
on the option module, then bits 31:8 of each longword are unpredictable. If
two chips are used, they should be connected to data lines 15:0 of the data
bus. Bits 31:16 are unpredictable. Four chips allow full use of the data bus
and direct execution of code in the ROMs. Three-chip configurations are
not allowed. If the size of the ROM is less than 256 Kbytes (for instance,
each chip stores less than 64 Kbytes), the ROM image may repeat in the
address range.

3-54 VAXstation 2000 and MlcroVAX 2000 Technical Manual

The format of the option ROMs contents, assuming there are four as shown
in Figure 3-31, is setup similar to the system ROMs on the system module.
The exception is the first longword that contains four bytes, each of which
contains the value 04h to indicate the number of ROM chips on the option
module. Another exception is the set contents of the ROM which is also
.described in this section.
Figure 3-31: Option ROM Address Allocation

31 •. 24 23 .. 16 16 ..
04b

04b

..
04b

0
base+OOb (PART)
BASE+04b

RESERVED
VERS

VERS

BASE+08h (PART)

OSb

02b

01b

OOh

BASE+OCh (PART)

55b

55h

BASE+l0h (PART)

AAh

AAb

AAh

AAb

BASE+14h (PART)

3Sb

33h

BASE+18h (PART)

LENGTH

BASE+1Cb (PART)
BASE+20h (SET)

ROM SET DATA
CHKSUM

CHKSUM

LAST LONGWORD (PART)

VS410 System Module Detailed Description 3-55.

3,3.2.3.1 Option ROM Set Format
For options that use only one or h\'o 1\0['1,'1
the data from these
chip5< must be moved into RAM. An option
four
chips uses the
full 32·bit ROM data path and may not have to be moved, The offset to the
beginn..ing of the data in the collective set depends both on the number
ROM parts used for the option and "'hether the header information (ROM
part data, eight bytes per chip) is included. For one chip. the
size
is 08h
for Me chips it is 10h bytes; and for four chips .It is 20h bytes,
Figme
shows the set contents within the
ROr.t
Option ROM Set Contents

Figure 3-'32:

31 ..

OPTION REVISION ;'uMBERl

RESERVED

~..

...

FOR EXPANSION (32 BYTES)

RESER\~D

DEVICE CONFIGURATION BLOCK (DCB) TEMPLATE
WHICH CONTAINS .. ,
31

.. 0

MINOR VERSION

MAJOR VERSION

HARDWARE II)

EDIT 'IrERSION

I
J

DEVICE NAME (8 BHES)
POINTER TO DlRECTOlUES
RESERVED FOR DEVICE STATUS

POINTER TO EXTENDED STATUS

SIZE OF EXTENDED STATUS

DIRE.CTORIES

3-56

VAXstation 2000 and MicroVAX 2000 Technical Manual

Each devICe in the system, including ('pti n n;;1 h,~nh·;lff'. It"" if" 01S11 dtlti1
struct.ure called a device configuration l.:+ock (DCB}, which is integrated into
the main confIguratwn table (i\1COduring pm\rer-up inittalization. The
DeB contains static and dynamic data, and pOi.nters to ('odE' required for
the device. There is a predefined :'lei. of routines used for diagnostics and
console device support that must be implemented by e.ach clevie€:. Each
option must provide a template DCB for the device supported by the
This contains information used by ROM startup code to integrate the
into the systems diagnostic structure, and information used by the next level
of testing to identify the device and its capabilities

each option, one each for the
There are six: directory entries required
seHtest code,. system exerciser code, utHities, console support, unjarn, and
system exerciser console support Each
has the format shmvn in
Figure 3-33.

Figure 3-33:

Option ROM DeB Directory Contents
., 0

POINTER TO CODE
LENGTH OF CODE.
ENTRY POINT
FLAGS

I DATA PATH

VS4 i 0 SYStem Module Detailed

3-51

3.4 Time-of-Year Clock (TOY)
The time-of-year clock (Figure 3-34) is an MC146818 CMOS watch chip that
keeps the date and time of day, and contains 50 bytes of general purpose
RAM. A 32.768 kHz time base oscillator provides the dock input and a
rechargable nickel-cadmium battery provides power to the chip and oscillator while system power is off. The watch chip uses an LS646 transceiver
to buffer and control the data and addresses to and from the CPU bus.
Data from the watch chip is used to determine the date and time during the
power-up of the system. See Figure 3-35.
Figure 3-34: Time-of·Year Clock

--..,
3-58 VAXstatlon 2000 and MicroVAX 2000 Technical Manual

Figure 3-35:

Watch Chip and Transceiver Chip Diagram

Modufe De!aHed

3.4.1 Watch Chip Theory of Operation
The watch chip uses an 8-bit data and
bus tor reading and i<vriting to
the 64 eight,·bit register storage The first ten registers contain
and time
information, the next ENlf registers control the operation and give a status of
the chip and the last Hfty registers are general purpose RAM registers used
by Hit; system finmvare. This bus is contn."lHeci by four discrete signals,
The,;,' are the address strobe (AS). daL;!
(DS), 'w!iI~; (\r'V'J(), and chip
select
signals. The DC524 standard cen controls the A5, DS, and CS
by the CLKAS., CLKDS, a.nd CLKCS "lgnals and the ViR signa) is
controlled by the
chips BWRITEO signal, Figure
shows !he timing
diagrams used to read from and .vrite to the watch chip, The transceiver
chip is used to buffer the CPU data and address bus to and from the walch
chi}1. It is enabld
the same chip select signal to the watch chip When
enabled, the direction of data or address flow is determined by the DALDIR
signal from the DC524 standard cell, The first half of a watd1 chip read or
\vrite cycle latches the address into the watch chip. The DALDIR. signal
determines whether or no!. the second half of the C'vde is a
aSSt;rted.
or a write, unasserted, cycle, For a read
the data from the watch chip
is buffered directly onto the CPU bus, For a l'\-'rite cyde, the data from the
bus is buffered directly into the watch chip and stored in the latched
address loca.Hon.

3-GO

VAXstatlon 2000 and MlcroV/V< 2000 Techn!ca! ""~a.nuai

10 System Module Detailed Description

3-61

The watch chip uses a 32.768 KHz clock crystal as the time base for the time
functions. Once every second, the time registers are put into update mode
and are incremented by one second. The time and date registers must not
be accessed by the program when in update mode. Update mode uses
1948 microseconds to complete the updates. The program must check the
update in progress (UIP) bit in register WAT_CSRA to determine whether
or not the chip is in update mode before attempting to access the time and
date registers. To set the date and time registers the update mode must
be halted by setting the set time (SET) bit in register WAT_CSRB. The SET
bit, when set to 1, allows the program to set the date and time registers
without being interrupted by the update mode cycle. Once the date and
time registers are set, the program must reset the SET bit to 0 to start the
update mode once again.
The clock crystal and the watch chip are protected from a power loss by
a rechargeable nickel-cadmium battery connected to the supply voltage pin
(BT). If the system loses power, or when the system is switched off, the
clock crystal and the watch chip are powered by this battery so they retain
the current time and date and also to retain the contents of the fifty RAM
registers. If the battery voltage drops below the level needed to sustain
the contents of the registers, the valid RAM and time (VRT) bit in register
WAT_CSRC clears to zero to invalidate the contents of the registers. The
program must check this bit during the power-up initialization to determine
the validity of the contents of the watch chip registers. During power-up, the
reset (CLR) signal is held low to allow the system supply voltage to stabilize.
The CLR signal does not affect the dock, date, or RAM contents within the
chip.

3.4.2 Watch Chip Registers
The watch chip contains 64 eight-bit registers. Ten of these contain date and
time data, four are control and status registers, and the remaining 50 provide
general purpose RAM storage for the system firmware. The registe,rs occupy
64 consecutive longwords at address space listed in Table 3-8. BIts 9:2 are
used in each register for data storage. Bits 31:10 and 1:0 are ignored on
writing and undefined on reading.

3-62

VAXstation 2000 and MicroVAX 2000 Technical Manual

Since each register spans n,r(i bytes on the
bus, only
or Iong:,vord
access inst.ructions
he used to manIpulate these registers. The effects of
using byte access instructions are undefined. Instructions for modifying bits
BESS, ESSe saec and sacs must not be used because they generate byte·
access read-modify.\vritE'
whkh cormp! the portion of the register thaI'
is not in the b}rte being accessed

Addresl!\

Name

Defillllion

lOOS. (JOtll}

WAT

Time s('(onds, tl.59

2008.0(104

WATAlMS

i\Jarm seconds (not 'llsed)

200£,0008

WATM.lN

Time mim,ltes, 0,,59

loon ,I);)OC

VVATALMM

Alarm minutes (not used)

20013,0010

WATHOUR

Time hours, O. ,23

200KOO14

WATALMH

r\.1arm hours {not used;

200E.orns

WAlDOW

of v,reeK, 1..7

200B.OO1C

WAT

Day of mcmth, 1 ,31

2008.0020

\<VAT .tI.10N

Month of year, 1,,12

2008,0024

W'¥"·
P,/

Year (If centur;y, 0.. 9':1

2008,0028

\'v"AT CSRA

Time base diviS(Jr

2OOS.002e

WAT C5R8

Dale m(yJe and fo:mal.

200B.O'030

WAT CSRC

lnterrupt flags (not used)

200110034

WAT,CSRD

Valid RAM and time

200B.OO38

Firs! hyt€ of RAM datil

20OB . OOFC

Last byte of RAt\<1 dara

10 System Module Detailed

3-63

3.4,2. '1 Control and Status Registers
Figure 3-37 shows the format of the time ba;;:e
(W
Figure 3-38 shows theformatc,f tht! date mode and form<lt
register, Fi,gure 3-39 sh(w,,'s the format of the valid RAt..! and time
CSRD; register.

Figure 3-37:

Watch Time Sase Divisor (WAT_CSRA)
1

3
1

{)

NCT

Da.ta Bit

Definition

us~~

:I tn:p

6 5

DVX

r ,R_SX

2 1

NOT USED

N('t used.,

UIP

bit iru.1h'ah?5 li;1.dH-:n the date
It 1s !'>lot
anti

and tim"

retnains one untH the
DVX

Time base dhdsor (bits
These rC3d.wrile bits set the an'OLln!
which the time base oscillator
to the v(i;ltch
is dIvided,
bits must be set to "(Hrr to acccn,od,ltf' the 32
Kl-lz time
bas(' in this $VstenL
l'he~;e

3-64

VAXslation 2000 and MicroVAK

n:{1d/\·vrHe bits ~f'lect thf: l'ttte ft vv.h.irh
Sine'.: Ihis I!:'atml' is !hJt

Techrdcal Mam:a i

Figure 3-38:
3
1

Watch Date Mode and Format (WAT.CSRB)
1

o 9

NOT USED

Data Bit

Definition

31:10

Not used. Ignored on writing and undefined on reading.

SET

Set time (bit 9). When this read/write bit is zero, the time and date
registers are updated once per second. When this bit is one, any
update cycle in progress is aborted and updates are inhibited so that
a program can set new date and time values.

PIE

Periodic interrupt enable (bit 8). Must be set to O.

AlE

Alarm interrupt enable (bit 7). Must be set to O.

UIE

Update interrupt enable (bit 6). Must be set to O.

SQWE

Square-wave enable (bit 5). Must be set to O.

Data mode (bit 4). This read/write bit selects the numeric representation in the time and date registers. If OM is one, the data format
is binary. If OM is zero, the data format is two 4-bit decimal digits
(BCD).

24112

Hours format (bit 3). This read/write bit selects the format of the
WAT.HOUR and WAT.ALMH registers. A value of 1 selects 24-hour
mode. A value of 0 selects 12-hour AM/PM mooe. In the latter case,
bit 7 of the hours registers is 0 for AM and 1 for PM.

DSE

Daylight saving enable (bit 2). This read/write bit is 0 for normal
operation. If set to 1, two spedal time updates occur: on the last
Sunday in April the time increments from 01:59:59 AM to 03:00:00
AM, and on the last Sunday in October when the time first reaches
01:59:59 AM, it changes to 01:00:00 AM.

1:0

Not used. Ignored on writing and undefined on reading.

VS410 System Module Detailed Description 3-65

Figure 3-39:

Watch VaUd RAM and Time Flag

DataBH

OefinItion

3LW

Not used

VRT

Valld RAtvt "nO. Hme (bit 9)
Thl:'! bit indk"l;;$ whEII1,,;' tiw (ont"nt" of tht: Ume and RAlv1 regl.shL'i ~n"y h;wl.' been
Thj~ bit is set \0 I,l whlC'n,:,vi:! ~yst€'m POW"f is ott' ,wd the
"g\' drops below tn!'wliue
for the .·,,,tetl
ftm,' ,

Oil writing iH'I(i undefined on

Th,i:; bit

Hon

~!nfLr

iH\V

t.his

tf:g~

i51!;r

Not used 19nQr!'l:l on

3.4.2.2 Date and Tlme-of·Yaer Registers
is kept in six
VVf\T_DAY,

_DOVv',

V', AT_
A ,:,eventh

the da.)! of the ,veek

through 7l. The contents of each
form or BCD ' 4-bit decimal
as

bit mvL

The time yalue is inCrenl€nted once each second, Such an
1948 microseconds . d,udng\vhich time the d,He and time
c(m!em~
are unstable and shc'uJd not be read b\' a prcgrarn Register VV.AT
bit
indicates when an update is .in ~
. '.' This l;I! is one
microseconds before the
of an
is
complete Therefore a program should
untH it finds bit
lHP zew, at which time it has at lea~t 24.4 rnicwsf.'conds to read the date
and hme registers, The program
while
to ensure that an interrupt does nClt
microsecond wlndol\',

3-66

VAXstation 2000 "pjd

2000

3.4.3 Non~Volame RAM Storage
The
bytes of RA~<l1 storage are used by the system firmware. Each b.rte
actually occupies bit positions 2 through 9 of successive longvvords just like
the date:, time, and control registers. This section lists the type of data t>tored
in the NVR by the system firrrnvare. There are utilities to set Ihe boot flags.
boot device, halt action, and keyboard tYPE:. These utilities are described
If." the VA.Xst£lfi(l1l 2000 (ma MicroViLX 2000 M.uinie/uHlet' Guide. Table 3··9 Hst~:;
the type of data stored in the NVR. An fifty registers are cleared tvhen an
NVR failure is detected during power-up.

Table 3-9: Non . . VolaWe RAM Contents
Address

Name

20CH:t.003S

CPMBX

(:onsn.le rnaHho); (1 byte)

200B.003C

CPFLG

Console rrogram flags (1

200B.0040

LK201 iD

Keyboard variation (1 byte)

2008,0044.

CONSOLE ID

Console de":!ce type (1 byte}

2008.(1)48

SCR

Scratch RA!l.1 physical addr€'S$ (4

through

200B.0054
20015.0058

TEMP

Ii tl'r. ware

through

200B.OOgq

2ooB.0088

BAT

Baltery check data. (4 bytesJ

200B,!)098
through
200B.(}0A4

BOOT DEV

Default boot device (4

200lJ.OOA8

BOOT

through

200iUX194

through
2008.00134
Numbe.r of pajl:ts of scratch rarn f1

200r:U'!I)!~B

200B.,OOBC

SCSI

200IU)i.)CO

Reserved

con I roHer

datil 0

Reserved (16

10 System Module Det.aHed

3.4.3.1 Console Mailbox Register (CPMBX)

Figure 3-40 shows the console mailbox register.
Figure 3-40: Console Mailbox Register (CPMBX)
1
09

3
1

NOT USED

8 7

2 1

RESERVED

NOT USED

Data Bit

Definition

31:10

Not used.

9:8

Reserved for future use.

HLT.SWX

Halt switch. This is the permanent recovery action the console is
to take when a processor halt occurs (except for externally generated
halts such as the halt button):
0,1 - Restart. If that fails, boot. If boot fails, halt.
2 - Boot. If that fails, halt.
3 - Halt.
HLT.SWX is set to 2 (Boot/Halt) when a NVR fallure is detected during
power-up. This field is read and written to using the console test 53
command.

RIP

Restart in progress. This restart in progress nag is set when the console attempts a restart. If it was previously set, the attempted restart
is abandoned, an error message is displayed, and a boot is then attempted. This field is cleared during power-up and at entry to the
console program.

BIP

Bootstrap in progress. This bootstrap in progress flag is set when the
console attempts a cold restart. If it was previously set, the attempted
bootstrap is abandoned, an error message is displayed, and the console
program is executed. This field is cleared at power-up and at entry to
the console program.

HLT ACT

Halt action. This is the temporary recovery action the console takes
when the next processor halt occurs. The action taken is the same as
for the HLT_SWX field.

1:0

Not used.

3-68 VAXstation 2000 and MlcroVAX 2000 Technical Manual

3.4.3.2 Console Flags Register (CPFLG)

Figure 3-41 shows the contents of the console flags register.
Figure 3-41:
3
1
109

Console Flags Register (CPFLG)
8

210

Data bit

Definition

31:10

Not used.

PFlLE

Parameter file. This bit, when set, is used by VMS to load a parameter
file along with the operating system when booting over the ThinWire
Ethernet. This field is cleared when an NVR failure is detected during
power-up so that no parameter file is loaded.

0001

Keyboard type. This bit indicates whether or not the 0001 type keyboard is connected.

V1DEO

Video Flag. This bit, when set, indicates that the console display is
a video display device, rather than a terminal. The particular device
type is encoded in the console type register (CONSOLE)D).

CORRUPT

Corrupted data flag. This bit is used by the console firmware during
initialization.

REENTER

Reentry flag. This bit is used by the console firmware during initialization.

MCS

Multinational flag. This bit, when set, indicates that the console display understands the DEC multinational character set.

CRT

CRT flag. This bit, when set, indicates that the console display is a
CRT display device.

GUARD

Guard bit. This bit is used by the console firmware during initialization.

1:0

Not used.

VS410 System Module Detailed Description 3-69

3.4.3.3 Keyboard Type Register (LK201 )0)

The contents of this byte is a number encoding the LK201 keyboard variant.
This field is used to select the appropriate data processing keyboard map for
keycode translation. This field is ignored if an attached terminal is being
used as the console device. Table 3-10 lists the values available and the
language that they identify.

Table 3-10: LK201 Language Values for LK(01)O Register
Value (bIts 9:2) Model Number

Language

LK201-xA

American

LK201-xB

Belgian (Flemish)

LK201-xC

Canadian (French)

LK201-xD

Danish

LK201·xE

British

LK201-xF

Finnish

LK201-xG

German

LK201·xH

Dutch

LK201-xl

Italian

LK201-xl<

Swiss (French)

LK201-xL

Swiss (German)

U<201·xM

Swedish

12
13
14

U<201·xN

Norwegian

LK201-xP

French

LK201-xS

Spanish

LK201-xV

Portuguese

This register is set to 0 (American) if an NVR failure is detected during
power-up. The console program asks the operator for the keyboard type
(LK201 ID) if, at entry to the console program, the keyboard type is unknown
or invafid (bit LK201 in register CPFLG is a zero or LK201)D is out of range).
This field is used only if the console device is built-in.

3-70 VAXstatlon 2000 and MicroVAX 2000 Technical Manual.

)

3.4.3.4 Console Type Register (CONSOLE-,O)
The console type register contains the type of console device as listed in
Table 3-11.

Table 3-11: Console Type Register Contents
Contents

DefInition of Device

Undefined or unknown

Special attached terminal on serial port 3

Attached terminal on serial port 0

VAXstation 2000 base monochrome bitmapped display with keyboard

3.4.3.5 Scratch RAM Address Registers (SCR)
The scratch RAM address registers contain the physical address of the con·
sole prQgram scratchpad area. This address is set during power-up by the
system firmware, and should never be modified.
3.4.3.6 Temporary Storage Registers (TEMPn)
The temporary storage registers holds miscellaneous data that the system
firmware needs to have stored in NVR. This temporary storage consists of
twelve consecutive longwords.
3.4.3.7 Battery Check Data Registers (BAT.CHK)
The battery check data Registers are used by the system firmware as an ad·
ditional check on the validity of the contents of NVR. If the battery volta~e
drops below the acceptable voltage level, the four battery check data registers are initialized to 55 h, AA hi 33 h, OF h respectively during power-up
initialization.
3.4.3•• Boot Device Registers (BOOT.OEV)
The boot device registers are used by the console to store the default boot
device. The device name is stored as up to four alphanumeric ASCII characters, padded to the right with Os as necessary. If the battery VOltage drops
below the acceptable voltage level, these four boot device registers are ini·
tialized to all Os during power-up initialization. These registers are read and
written to using the console Test 51 command.

VS410 System Module Detailed Description

3-71

3.4.3.9 Boot Flags Registers (BOOT_FLG)

The boot flag registers are used by the console to store the default boot
flags. If the battery voltage drops below the acceptable voltage level, these
four boot flag registers are initialized to aU Os during power-up initialization.
These registers are read and written to using the console Test 52 command.
3.4.3.10 Scratch RAM Length Register (SCR.LENGTH)

The scratch RAM length register contains the number of pages of system
scratch RAM. The contents of this register is determined during power-up
initialization.
3.4.3.11 Tape Port Information Register (SCSI)

Figure 3-42 shows the contents of the tape port register.
Figure 3-42:

Tape Port Information Register (SCSI)
1

NOT USED

6 4

RESERVED

2 1

NOT USED

Data Bit

Definition

31:10

Not used.

9:5

Reserved for future use.

HOST}O

SCSI bus host 10 address. This three bit field contains the 10 address
of the host on the SCSI bus. This field must always be 0 to indicate
that the tape controller on the system module is the host of the bus.

1:0

Not used.

3-72 VAXstation 2000 and MlcroVAX 2000 Technical Manual

3.4.4 Initialization
vVhen a program finds the VRT bit equal to 0, it must i,ssume that t.he
contents of all other regist€'rs in the watch Chlp are invalid. To initialize the
chip, a program must do the following rour steps.
1,

Load register V'iA T
with bit SET equal to 1 to inhibit time
update'.: and bits
VIE and SQ\'\'E equal to 0 to di.sable
unused features. Bits Trvt 24f12 and DSE should be sel fell' the
desired date forrnat

Load the seven time regislers v·lith the current dale and tirne The
addresses are listed in Table

Load register "VAT

tQ set the proper time base

The

DVX bits should be set to "OW" and the RS); bits to '0000".

Load register WAT CSRB 1l'lith the sarne value used in
that bit SET shouh:f nov<" be (J to enable normal time

3.4.5 Battery Backup
A nickel-cadmium battery in the system box supplies povlier to the watch
chip and its time base
while system pmver is off When starting
from. a fully charged condition, the battery maintains valid time and RAtv1
da.ta in the watch
for a minimum of 100 hours, The batt(:~rv
white system power (lll
"
As long as the backup battery voltage is sufficient, the contents and
tion of the watch chip are no! affected by system power· on and power-off
events

Modu!e Detailed Description

3-13

3.5 OC524 Standard Cell
This section describes the (ioeration of the DC524 standard ceJl
Figure 3-44 shows the DC524 standard ceH pinout and 'lable
pins and their signals and describes the function of each,
Figure 3-43:

Standard Cen

r;
!i J
;l j 1
'!

U :"'J

t I

;--)

,-,
!

;

\ 1

~.J

3-74

!"""',\

!-:
' ,

, :

n
u

VAXsta1ion 2000 and M;croVA,..'(

Technical

..=
c0

is:

iCJ
'2

......""
"0

en
N

It)

8
.;;

....I

CO)

!
c=

! i

VS410 System Module Detailed Description 3-75

Table 3-12: OC524 Standard Cell Pinout
Pin

Signal

Description

69;72
74:82
84:92
94:103

BDAL31;OO

The data and address bus (BDAL31:00) is a bidirectional Ume-multiplexed bus. It is connected to the CPU
chip DAL31:00 bus through four 8-bit 74F245 tristate bus transceivers.
These transceivers are controlled by the bus direction (DALDlR) and bus disconnect (DALDIS) signals from the standard cell.

117:123
125.126

MEMAD8:2
MEMADl;O

These signals form the memory address bus. This bus supplies a partial address to the system ROM, system
RAM, and the video RAM. See Section 3.3.2.1 for a detailed explanation of address flow.

112,113
115.116

PBIT03:02
PBIT01;OO

These signals are the parity bit logic lines.
They
read or write parity when memory is read or written to.
If a parity error occurs, the parity error signal is asserted.

PERROR

This signal is the parity error signal.
serted when a parity error is detected.

VAS

This signal is the address strobe from the CPU chip. It indicates when a valid address is on the BDAL bus.

VDS

This signal is the data strobe from the CPU chip. It indicates when valid data is on the BDAL bus.

VDBE

This signal is the data buffer enable signal from
the CPU chip.

CS2

This signal is the control status 2 line from the
CPU chip.
This signal indicates that an interrupt cycle is in progress when this line is asserted.

VCSl

This signal is the control status 1 line from the
CPU chip. The combination of this signal and CS2 indicate which cycle the system is in.

VDMC

This signal is the- DMA grant line from the CPU
chip.
It indicates when the Ethernet network controller is in control of the system.
Only the controller in the network option port has the ability for DMA.

WRITE

It is as-

This signal indicates when a write cycle is in progress.
is asserted any time BWRITEI is low or REFCYC is low. It is deasserted when both of these signals are high.

3-76 VAXstation 2000 and MicroVAX 2000 Technical Manual

Table 3-12
Pin

OC524 Standard Cell Pinout
Description

135

SCYCIAD2

136

DC,)'CLADl

137

STFHiIADO

have two fUn.CtiOfi!j, OnE' function lS
the
speed control function and the otheri" an
interrupt vector address bit during the interrupt
The cycle
(ontrol hmtio!1 aUmv5 th€'
access
that are no! as last as thf?
The CPU normally runs at 40'J os tmless one of these
Hmos ate asserted: When the SCYC (slow
is assertt'd,. the CPU slows down the
tht~
51) the whole
nills at 600 ns, \Vhen the
(double cyde) line is aBs~rted . the CPU nms lhe
second half of the
twict' for a total eyde time of
SOO m. When the
(Slltl! on the firs! half~ lin!;'
:is asserted, the CPU is stalled on the first halJ of t.he
cyell:' until this line is deasserted.
The second function of thes('
is utiii:n"d om ..
ing an interrupt cyde where
lAD" and IADO
are controlled by tnt:' standi3rd cell il.nd (ontain the
intern.1pt vector address of the device requesting the
interrupt. Thls vector address is sent to the
ROM where it is decoded into the starting addres:, 01
the service routine for the device requesting the inter-

rupt.

\iBM3
VBM2
VB.h1l

VHf,,1\}

These signals are the bytt' mask signals .from the CPU
They indicate which portions of the VDAL blli"

Me vaHd. Each byte mask signal v..lldates eight lines
on the VDAL bus. VBM.':! vaJjdates lines 31:'24. VBf,;2
validates lines 23d6,. VBM1 validates liM"
and
VBMO validates lines 7:0. Any combinalion of these

byte mas.k signals may used during a cycle to validate
c0mbinatlcHl of th(' !"Uf 8·line segments of the

bus.

VS410 System ModUle De1aHed Descr!ption

3- n

Table 3-12 (Cont.): DC524 Standard Cell Pinout
Pin

Signal

Description

READY

This signal is used to indicate to the CPU the end of
certain cycles. The standard cell controls READY and
asserts it to indicate a normai termination of the current CPU read t CPU write, or interrupt acknowledge
cycles. During a CPU read cycle or interrupt acknowledge cycle, ROY L indicates that the standard cell has
placed the required input data on the OAL bus. During a CPU write cycle, ROY L indicates that the information is available on the OAL bus. When the CPU
chip recognizes the assertion of ROY L, it terminates
the current bus cycle and proceeds. The standard cell
then deasserts ROY L.

104

DALDIS

This signai controls the tri-state function of the VDAL31:00
to BDAL31:00 bus transceivers. When set high, this
signai disconnects the VDAL bus (which disconnects
the CPU) from the system.

105

OALDIR

This signai controls the data flow direction of the
VOAL to BDAL buses. This signal ailows data to flow
out from the CPU chip when high and into the CPU
chip when low.

127
128
129
130

CAS3
CAS2
CASl
CASO

These signals are the column address strobes for the
memory devices in the system. The standard cell controIs the memory addresses for all memory devices in
the system. Each segment of the system memory is
controlled by one of the CAS lines. The video RAMs
are controlled by CAS1 and CASO Jines. }\ll four of
these signais appear at the three option ports for option module memory control.

145

DZRINT

This signai indicates when the serial line controller
is requesting service. This line is asserted when the
seriai line receiver or silo is full.

146

OZTINT

This signal indicates when the serial line controller
is requesting service. This line is asserted when the
seriai line transmitter is done.

147
148

NIIRQl
NlIRQ2

These signais indicate when the network controller is
requesting service. The NIIRQl line is the primary
interrupt line and the NIIRQ2 line is the secondary
interrupt line for the network controller.

3-78 VAXstation 2000 and MicroVAX 2000 Technical Manual

Table 3-12
Pin
149

DC524 Standard CeB Pinout

Signal

OPTFOF

ISO

OMmQ

151

scsm{Q

1<:;'"1

indka!~: when t!w
!iH)dulE' in
purpc.." option pori i~ n;questmg se~'·
Th" OPTEOF i~ the
il'ltMrtl1J'\ line
lhw fOJ
and th" OPTIRQ line i~ the ""',,'''''''0
tn€ option modult,
Wher,
rned·
ule is ir\st"Hed, trl€:
lin.,
that £i
vjdecl ('nd of {nun" has

TheS!; S11;"I1<115
tn!'
vicE>.

This signa.! indicates ,,,hen the 5380 tape controller is
requf'sHng service,
This signal indicates when the 9224 disk controller is
requesling service,

-,~

144

iNTREQ

This signa! is generated by the standard celJ wnenen:'r
an interrupt reqi.1est is received hom one of the
interrupt lines mentioned in this table,

INTI!!\1

This sjg!'"al 1s generated by Ihe standard cen and 1~: the
interval timer for the CPU chip. This timer provides
a source of interrupts al a 10 millisecond rate

108

('PRESET

This sig:nal is generated by the standard ((;11 tQ lnltiill·
ize the CPU and the svstem to a known state,
power-up, this signal "if' held low long
for
CPU and the rest of the system to initialize! and then
it is held high for normal operation.

VCl,KO

This signal is a ckd. signal from the epe chip,. H i"
half of the VCLK40 signal.

VCU<40

This signal is the 40 l\·1Hz dock from a

tor,

107

the pClwer-

PVv"RON

high h:hl"l1

106

TEST

151

5HSJLO

is th(' test line. h must he Z1"()UJK\(:t1
for normai
This
Bne

\/5410

is used to shift the wntents of the sf'rlal
follo,",'Ing; il read from the sUo.

Module Detailed Description

3-79

Table 3-12
Pin

Signal

------:2
SHY
.3

SELX

163

SRl\MO

164

SIZ.~Ml

162

DTiOE

OC524 Standard Cell Pinout
DescripUon
~--~-----

,---------------

Thesf' signals are
t.rol the video
sIgnals are deC0d!~d
the multiplexer
nUnw four out ot sixteen video
from the VlD15:00 bus onto the VD,".T3:0 bus,
The data on the VDA,T3cO bus is
to the standard
cell
These signals contral the video RAM, The SRA~n .!ilH'
controls the high bytE' and the SRAMO corilrols the low
fr(1m the \'ideo RAMs,
This signal has several functions, It controls the video
RAl\'f (hirr, for eithE't a normal access or ,1 video shitl
register update cycle,
it is w::ed as a

seJect bit for RO:t\1
16'1

160
159
158

VDA.T3
VI.)AT2

VDAn
VDATO

These

are the video data bus

These

fom Enes aft' from the four vide(l multlplewrs. E<lch
video multiplexer' is a tn'll! to one mullipJeller ~'ih\(h
lakes four signals from the VIdeo RAMs on the VID15:DU
bus and Qutputs it h) one of the VDAT lines, This

type of dxcuit allowed Ihe &tandard cell to use twelve
pins for pU!p'j5eS other than the VDAT bus. since tbe
VDAT bus can be
dOVifl 10 four Hnt's without any timing problems.

12
13
14

1~
...

16
17

18
19

CURA3
CURA:

These
are the cursor
DC503 cursor

,-,\ bits from the

CURAl
CURAD

Cl.JRIB
CURB2
CURB1

These
are the i:"'.Jrsor plane B bits from the
[1C503 cursor sprite chip,

CURBO
is the vici!;Xl dock il'lpuL H is from the 69
timing and refresh o5dllalcr,

VCLK69

Th!s
MHz

BLA. NK

This signal is generated
the standard cell and is
used by the cursor chip ror blanking
inforrnaHon.

HSYNC

This
chronjzt~ thl:'

3~80

VAXstatlon 2000 and MtcroVAX 2000 Technwal Ma.nual

Table 3-12 (Cont.): DC524 Standard Cell Pinout

)

Signal

Description

HSVS

This signal is generated by the standard cell and is
used together with the DOTS signal for the video output signal to the morutor.

NIBCLK

This signal is generated by the standard cell and is
used by the cursor chip for timing.

DOTS

This signal is generated by the standard cell and is
used together with the HSVS signal for the video output signal to the monitor.

CURSEl

This signal is generated by the standard cen and is
used by the cursor chip for its data strobe input signal.

SCSICS

This signal selects the 5380 tape controller. It is the
tape controllers' chip select.

SCSIRD

This signal is generated by the standard cell to set up
the read cycle for the 5380 tape controller.

SCSIWR

This signal is generated by the standard cen to set up
the write cycle for the 5380 tape controller.

SCSIEOP

This signal is the end of process indicator. This line
is asserted when the data transfer to or from the disk
data buffer and the tape controller is complete. It is
deasserted 150 ns after it is asserted.

SCSIDACK

This signal is the DMA acknowledge line to the 5380
tape controller.

SCSIDRQ

This signal is received from thE' tape controller to indicate the tape controller is requesting a DMA transfer.

CTRLOAD

This signal is used to load data into the DMA address
register.

131
143
132
133

SRASO
SRASI
ERAS
VRAS

CS9224

These lines are the row address strobes for the memory devices in the system. The two SRAS signals are

for the system RAM. SRASO contains the row address
strobe for the first bank of RAM on the system module. SRAS1 contains the row address strobe for the
second bank of RAM on the system module. The
ERAS signal is the row address strobe for the expansion memory. The VRAS signal is the row address
strobe for the video RAM.
This signal setE'cts the 9224 disk controller. It is the
controller's chip select.

VS410 System Module Detailed Description

3-81

Table 3-12 (Cont.): DC524 Standard Cell Pinout
Pin

Signal

Description

WR9224

This signal sets up the read cycle for the 9224 disk
controller.

OS9224

This signal is the data strobe signal to the 9224 disk
controller.

OBUFCE

This signal enables the disk data buffer. It is the data
buffer's chip select.

ROUNIT

This signal selects one of the two hard disk drives
when asserted.

SELECTRX

This signal selects the RX33 floppy disk drive when
asserted and the hard disk drives when deasserted.

SEUiIDEN

This signal selects the data rate and rotation speed of
the RX33 floppy diskette drive. When asserted (high),
the data rate is 500 kHz at 360 rpm. When deasserted
(low), the data rate is 250 kHz at 300 rpm.

R010AT

This signal is the raw data stream from the hard disk
in the expansion box. This signal is selected when
SELRX is low and ROUNIT is high.

ROOOAT

This signal is the raw data stream from the hard djsk
in the system box. This signal is selected when SELRX
is low and ROUNIT is also low.

RXOATA

This signal is the raw data stream from the floppy
diskette drive in the system box.

ROGATE

This signal indicates that the raw data from the hard
disk drives is valid.

VC020

This signal is the output of the 20 MHz voltage controlled osdllator and is used for data recovery for the
hard disk drives.

VC02

This signal is from the output of the voltage-controlled
oscillator and is used for data recovery for the floppy
diskette drive.

FMOELAY

This signal is from the delay line that is used with the
hard disk drives to provide the normal half bit delay
for the phase detector.

ROATA

This signal is sent to the 9224 disk controller. It contains the raw read data from the disks.

3-82

VAXstation 2000 and MicroVAX 2000 Technical Manual

Table 3-12

OC524 Standard Cell Pinout

Stgnii!

DE!$Cription

RCLK

This Sib-ToeJ is sent to the 9224 dis.!;: contr011el'., It indicates when the rAw retld data frorn the disks SiWllld
be examine,d to determine the va1l.le of the
at
that point In time,.

PUMPLYP

This signal is used to im:rE'dise the "P' ,\lP1'WV of tilt'
t'XlernaJ yoHag,€'·controU€,d oscillator,

PUMPDVVN

This signal is w;C:'d t(t decrease lhe
external voHage<o:ntroUed oscillator,

TODElAY

is sent to the. t"xtemal
line ,'>.'hi(h
the haIf,bit tirne
comparator for the hard
dr.1ve:;, This OUlput drives that delay tine

47
46

eLK5

These signals are; a :: MHz dock arid a 10 f¥IHz: dock
used
the 9224 dis.k controller,

44
45

TPl
TP2

These signals ate u!led to assess the performance of
the
looked
There is also a. TP~j that 1:5
connected to ground.

156

OPTROMENA

Thil'

enables the ROM on the mociuh' in the,
purpose

154

OP1VIDENA

This

1S a general enable signal for the mOt101e
p\.lIpose option pori,

153

SLUENA

This

enables the four-line serial controller.

13.3

NlBN/\

This signal EMPies the network controiIer
the DMA

139

NTROMCS

This
selects tht: ROM
lroller option module.

14('

EIDEN A

109

Clj(J~S

110

cu<cs

CLKDS

CLK10

of th(~

enables the Ethernet addrl"Ss ROM NI the

This

is the

naL

3-83

Table 3-12
.Pin

DC524 Standard Cell Pinout

Signal

Description

ROMes

This signal seh,,~(ts the
ROM's chip ~{~f.f:'ct.

SYSRECEN

This
isleL
lion

ROM, H IS the syMem

th!::
and (est H;ghoid." (hE' dat<1 on the conUgUlii.

and a!';o the t e s t ' Big·
cursor

~pr~~i~

,~lg~

tht:: dh,k controih:'f and 'he L:lJ..":'€.'
wntm!!er
a~ well "', ti!!.' network (OntrD!lef OF'"
lion moduJe and th~ 0;' od'uh.::' in the
pUT
pc>~e option porl
\Y.ithou: r~etiiJ1g the "'hal,, sysn,,::d cap

a.l~o

r€<~et

tem

3.5.1 Power-Up Initialization
When power is fjrst applied to the
thE power.up1pOi.\'er.dmvn circuitry holds the PWRON signa! to the standard cell low as power is applied
to the system and goes high after the +:) Vdc supply has risen to greater
than 4,75 Vdc. PWRON is received into
standard cell by a schmitt re·
celver and aHows the interval counter to begin counting. The standard cell
then >vaits for 12,829 dock cycles of CLK40
microseconds) to assure
that ali circuits are stable before
the reset signa! (CPRESET).
This ensures that the
and other devices requiring initialization see an
adequate number of clock cycles while in the reset state, As soon as the
CPHESET signa! is deasserted, the CPU
addresses the system ROM
and fetches the first instruction.

3.5,2 Memory Control
The DC524 standard (en supplies row address strobe (RAS,
address strobe (CAS} addresses tor dvnamk RA.l\1s
9-bit addressing,
'
"
the
or the network controller
}.·1ernory cycles mil)! be initiated
ooerating- as DMt\ bus master,
memory
by causing ,A.,5 to
change f~om high to lO1l\, 'Nith CS2 high, All timing then determined
the hming
trom the input signal CLKO. Additional memory
are
initiated to update the VAXstation 2000 'lideo RAM memory internal shift
registers and to perform memory' refresh, The ~v1icroVAX. 2000 does not use
the video circuits. These additional cycles are requested by counters
from the- video timing which may
the CPU RDY line if necessary
while the memory is busy,

3-64

VAXs1ation 2000 and MlcroVAX 2000

3.5.2.1 Multiplexed Address Signals (MEMA08:0)

Data from several sources is multiplexed onto the memory address bus,
MEMAD8:0. Data comes from the latched CPU DAL bus, the refresh address counter, the video RAM update address counter and is selected ac·
cording to memory type and the current requested cycle.
3.5.2.1.1 Program RAM Cycle, CPU or OMA Read or Write

)

Program RAM uses 256K x 1 DRAMs as explained in Section 3.3. These
chips use a 9·bit row address and a 9·bit column address. However, the
only cycle to use aU 9 bits is the refresh cycle. The addresses comes from
the latched DAL bus as shown below.
RAS address: MEMAD8:0 - LDAL19:11
CAS address: MEMAD8:0 - LDAL10:02
3.5.2.1.2 Video RAM Cycle t CPU or OMA Read or Write

Video RAM uses four 64K x 4 video RAMs. These chips require an 8-bit
RAS address taken from the latched DAL bus and two CAS addresses on
the DAL bus per cycle (the memory is 16 bits wide). The high order 7 bits
of the two CAS addresses also come from the DAL bus, the LSB is selected
by whether the cycle is a write or a read and which half of a longword
is being accessed. A longword read requires that the high word within a
longword be accessed first, and a longword write requires the low word
within a longword be accessed first.
RAS address: MEMADD7:0 - LDAL17:10
CAS address: (cycle1) MEMADD7:1 - LDAL09:02, MEMADDO - 0 for
WRITE(L) and 1 for WRITE(H)
CAS address: (cyde2) MEMADD7:1 - LDAL09:02, MEMADDO - 0 for
WRITE(H) and 1 for WRITE(L)
3.5.2.1.3 Video RAM Cycle, Shift Register Update

)

These cycles require an 8·bit RAS address which comes from an 8-bit
counter that is incremented after each cycle, and a CAS address of all zeroes which indicates that the entire video shift register is to be updated.
These cycles occur every 4 line times within the active video region and
once immediately preceding the active video region.
RAS Address: MEMADD7:0 - VIDADD7:0
CAS Address: MEMADD7:0 - OOOOOOOO(Binary)

VS410 System Module Detailed DescrIption

3-85

3,5,2.,1,4 Refresh Cycles
AU RAM memories in the system are upddted 211 the same time during a
RAS only refresh operation, The address comes from a 9,bit counter that is
incremented after each cycle. Six cycles occur as a block during each refresh
operation. These groups of six cydes occur immediatdy after a
RAM:
shift register update cycle
HAS Address: MElv1AD8:0 .., REFADD8:i)

3.5.2.1.5 ROM Cycles
The ROMCS signal is used to <I.ccess the system ROti for both normal program operation and during interrupt acknowledge cycles when the ROM
supplies the interrupt. vector to the CPU. The t.ype of cycle is indicated by
the DTfOE signaL When the ROM. is accessed during non.interrupt acknowledge
.ME!I,JADD7:1 supply a partial address with DT/Of held high,
The remainder of the ROM address is supplied from external latches. \,\'hen
the ROM is accessed during an interrupt acknowledge (INTACK) cycle, the
number of the highest level device with an interrupt pending is output on
the 1.AD2:0 signals and DT/OE is set to a logic 0, Having both DTJOE,.,O
and ROMCS active indicate that the ROM cycle is an INTACK cycle,
ROM partial address: !vfEMADD7:1 '" LDAL16:08, and

is high

3,5.2.1.6 VO Cycles
For cycles w'hich perform only a single data transfer operation, the l\1EMADD
lines are used to prm.'ide latched DAL17; for general peripheral contro.!ler
use outside the standard cell. For
where a double data transfer
occurs, MElv1ADDO indicates which half of 11 double cycle is ac-

partial address:
and MEMADDO ""

ME~,,1ADD7:1

"" LDAL16:10 for single IlO

for double

3.5.2,2 Memory Control Signals
For non·DMA cycles, the standard cell bus thning sta.rts every time AS
from high tCl low with CS2 high, if neither a video R/\;M update
nor a refresh operation is in progress For DMA cycles . where the
relationship of AS generated by the DMA Bus !',,1aster to CLKO is unknown,
a dual rank synchronizer is added to AS. Depending on the address \vhkh
has been latched at the faU of
one of three row address strobes may be
generated, followed by some combination of column
strobes ..

3-86

VAXslatlon 2000 and f..1lcroVAX

All timi.ng is generated from the CPU <:hip

CLK() , The Imv to

tra.nsition of CLKO foHClWing the transition
from high to Im..any row address strob(; thatls required,
next CLKO 1m'! to high tran,
to the
sition changes the address output by the cell from thE:' row
column address if any row address strobe is active, For a bus read
the next high t() 1m·v transition of CLKO enable:: column address
selected by the byte mask signals BlvB:O For a bus ,,,,'rite to program H.A~,!t
cycle, column address strobes are enabled at the 10\'>' to high transition of
CLKO folkr\.ving the end of tht:, row address strobe address to aUow time for
th~ parity to
cumputed and output to the memory parity bitlL For
gri'!In RA.1\f. the byte mask bits rnap into the
Hnes directly, For
RAM. where hvo
to the RAM are requued for each CPU
the
signal CYCLE is used in conjunction with th<: byte masks and the VVfUTE
Sigilill to contml CA5LO, EMU, BM2! CYCLE and \NlUTE control
EMl, 8M3,
and '''''RITE control
a.re not
column address strobes are
used in some peripheral
3.5.2.2.1 Program RAM Row Address Strobes (SRASO and SRASi)
The system module has 2 megabyfes of program RAM using 256K >: 1 DRAM
chips organized in 32-blt longwords, plus bytE:' parity. This occupies address
range OOOOOOOO:OO1.FFFFF hex, The signal 5RASO is generated when. the
CPU, or I.he network controller, if it is the DMA bus master, ha.R ou!put an
address in the lower halt of the address range with C52 ~. 1 and 'when AS
changes frorn high to h,w, The signal SRASiis generated when the address
is in the upper halJ of the ra.nge. SRASOfl is active (low} from the 1mII' to
high transition of CLKO following the change of state of AS from high to
low unt!! the lo'w to high tranf.ition of DS for that bus
SRASO and
SRASI are both generated when a: refresh cycle occurs.

3.5.2.2.2 Extended Program RAM Row Address Strobe (ERAS)
Optional pmgram RAlv1 can be added to the systern up to a maximum of 14
megabytes using
x 1 DRA.MS. The
00200000:
hex is decoded and the
ERAS
when the
lvork
operatiI'g as a D!\1A
rar'ge with
.., 1 and 'when AS
lov,; fmm the 1m,>" to
tnmsition of
lht' chang;t' of staif:'
of AS hom high to lmv untH the !QW to high transition of DS feil that bus
cycle. ERAS is also gen€'rated when a refn'sh
occurs, (Note that the
14
expanskni limit is the address
limit (If the standard Ct:U
and does liCit reflt~ct
n1ernory
modules In,.,)' be tr;;aH;tble {(il'
the "u<"·~"m.

~fS41

C-

rvtodtlle Deta.iled

3-87

3.5.2.2.3 Video RAM Row Address Strobe (VRAS)

The VAXstation 2000 standard video RAM supports a single screen display
of 1024 x 864 pixels. This is provided by four 64K x 4 video RAM chips.
The address range 30000000:300lFFFF hex is decoded and the signal VRAS
generated when the CPU, or the network controller operating as a DMA bus
master, has output an address in range with CS2 - 1 and when AS changes
from high to low. VRAS remains active low from the low to high transition
of CLKO following the change of state of AS from high to low until the low
to high transition of DS for that bus cycle. As video RAM is only word wide,
the memory control generates two back to back page mode memory cycles
for each bus cycle, stretching the bus cycle by deasserting ROY.
3.5.2.2.4 CAS3:2 Column Address Strobes (CAS3:2)

CAS3:2 are selected by BM3:2. CAS3:2 become active (low) after SRAS,
ERAS or VRAS has gone low or after an I/O device select has been asserted.
3.5.2.2.5 CAS1:0 Column Address Strobes (CAS1:0)

CAS1:0 are selected by BM3:0 during both cycle1 and cycle2 but only two of
the four byte masks select CASl:O and this is controlled by WRITE. During
cyclel, when WRITE is low, BM1:0 select CASl:O. When WRITE is high,
BM3:2 select CAS1:0. During cycle2, when WRITE is low, BM3:2 select
CASl:O. When WRITE is high, BMl:O select CASl:O. CASl:O become
active (low) after VRAS or an lIO device select has been asserted.
3.5.2.2.6 DAL Bus Transceiver Direction Control (DALDIR)
The standard cell uses bidirectional bus buffers to isolate it from the CPU

chip. DALDIR controls the direction of data flow through these buffers.
When DALDIR is high, data is passed from the CPU chip to the system.
When DALDIR is low, data is passed from the system to the CPU ship.
DALDIR is high if WRITE is low or DBE is high. DALDIR is low when
WRITE is high and DBE is low.
3.5.2.2.1 DAL Bus Transceiver Enable Control (DALDIS)

DALDIS enables the OAL bus buffers for data transfer operations to and
from the standard cell and peripheral devices during an extended bus cycle.
DALDIS is also asserted twice during bus read cycles, once while ASI is
high and DS is high to avoid possible bus contention with very fast devices
being accessed and again from the time DS has gone high again until ASI
goes low to remove data from the bus as soon as possible. DALOIS is driven
high when OMG is low and when a write to the system configuration register
has been decoded. When DALOIS is low, the bus buffers are enabled in
the direction set by DALDIR. Table 3-13 lists the functions of the DAL bus
transceiver enable control and the status of the controlling signals.

3-88 VAXstation 2000 and MicroVAX 2000 Technical Manual

An extended bus cycle is generated when the memory or peripheral device
addressed is not a full 32·bits wide and it is necessary to perform two read
or write operations on sequential word addresses of the device to satisfy
the CPU long word data requirement. Note that longword accesses to word
wide peripheral devices may cause unpredictable results.

)

Ouring cycle 1 of an extended bus read operation, the least significant address of the selected device is set to a logic 1, indicating that the high 16
bits of a longword is being requested. This is done by setting MEMADDO
to a logic 1. Data is taken from the RAM or peripheral onto buffered DAL
bus bits BDAL15:00 and then into the standard cell where it is stored in a
temporary register, the internal data latch. Ouring cycle 2, this stored data
is output onto BDAL31:16 and the least significant address now presented
to the RAM or peripheral is set to a logic 0, indicating that the low 16 bits
of the long-word is now being requested. The RAM or peripheral supplies
these data bits on BDAL15:00.
For a write operation, during cycle 1 the low word address of the longword
pair is sent to the selected device, the CPU data on BDAL15:00 written to
the selected device and the high word data on BDAL31:16 stored in the
internal data latch. During cycle 2, the word address to the device is set
to the high word of the longword and the data from the internal data latch
placed on BDAL15:00 to be written to the device with DALDIS driven high
to disable the DAt buffers.

Table 3-13: DAL Bus Transceiver Enable Control
Signals
DALDIS DMG Cyde2

WRITE

Function

CPU data to the device and standard cell

HIGH

H
H

Standard cell data to the device

HIGH

Device data to the standard cell

LOW

Standard cell data to the CPU chip

HIGH

Data transfers to and from the DMA controller

lOW

3.5.2.2.8 Data Transfer/Output Enable for VRAM (DT/OE)

This output has several functions. It controls the video RAM chips to cause
either a normal access (DT/OE is high as AS falls). or a video shift register
update cycle (DT/OE low as AS falls). It is also used as a cycle type select
bit for ROM cycles

VS410 System Module Detailed Description 3-89

3.5.2.3 Memory and Peripheral Timing
Memory and peripheral timing diagrams are located in Appendix A.
3.5.2.4 Control of CPU Cycle Slip.
This section describes the CPU cycle timing control signals.
3.5.2.4.1 Single and Double Cycle Slip.
To guarantee a single microcycle slip, the CPU chip RDY line is deasserted
ilt the start of T3 <.,f an extended cycle and reasserted at the end of the
following T2 flU a single microcycle slipl or the end of the next T2 for a two
microcyde slip (TOY clock cycles).
AS is asserted (low) during state T2 following the CLKO low to high transition that starts T2. AS is re-synchronised within the standard cell using
CLKO, so ASl is set at the start of CPU state T3. The CPU samples RDY
frolll T4 + 30 ns to T4 + 90 ns, so if RDY is de-asserted from ASl to ASl
+ 3CLKO later, a single microcycle slip will occur. In fact RDY may be
deasserted up to ASl + 5CLKO later and there will still only be a single
slip.
3.5.2.4.2 Two Cycle Requests from Optlona' Devices
The logic used to extend the bus cycle and to generate two word cycles
per extended bus cycle may be used by any optional device by its asserting
the control line DCYClIAD2. A peripheral device needing the controller
to perform a double cycle must assert DCYClIAD2 low within 100 ns of
receiving its device select from the standard cell or decoding its device
select separately.

3.5.3 Video Control
3.5.3.1 Video Shift Register Update and RAM Refresh
The shift registers within the four video RAM chips contain sufficient data
for four display lines, thus an update of the shift registers is required every
four line times (74.1 microseconds). A single video RAM cycle with DT/OE
low as VRAS falls updates all shift registers. The RAS address for such an
update cycle is taken from an 8-bit counter which is preset with an offset into
the video RAM address space at the end of each frame and incremented
after each update cycle. As there are 864 displayed lines and an update
cycle occurs each 4 lines, the counter range is INITIALYALUE to (INITIAL_
VALUE + 215). If the INITIAL ADDRESS is greater then 40, the counter
wraps to the start of the video RAM after line 864 - 4 * (40 - INITIALYALUE).
The CAS address for update cycles is set to zero to cause all shift registers
to be used.

3-90 VAXstation 2000 and MlcroVAX 2000 Technical Manual

Following the shift register update, memory refresh is performed. Ouring
each refresh operation, sufficient refresh cycles must take place to ensure
that the worst case refresh interval is not exceeded. As there are a total of 216
refresh operations for each display frame time (16.67 microseconds), this
requires that six RASO-onJy refresh cycles must be performed during each
refresh operation (256 addresses must be accessed every 4 microseconds;
every 4 microseconds there are 51 shift register update cycles; 5 cycles per
operation yields a worst case refresh interval of 3.9 microseconds. But there
are no refresh cycles during the vertical retrace interval, hence 6 refresh
cycles per operation). The addresses for these cycles come from a 9-bit
binary counter, initially cleared and incremented after each refresh. (Only
eight bits are used for the present RAMs, the ninth bit is for possible future
RAMs using 1 megabit chips).
The sequence of video shift register update and the six refresh cycles is
started by the video timing prior to the beginning of the displayed region and
subsequently every four display lines until the end of the displayed region.
A request for control of the memory system is posted by either of these two
events. A synchronizer then monitors AS and waits for it to be high when
CLKO changes from low to high. At this time a hold state is entered and
DCYC/IAD1 is driven low to indicate to external logic that a video RAM
update is in progress. While hold is true, any attempt by the CPU, or the
network controller operating as a DMA master, to access memory (AS going
low), causes the RDY line to be de-asserted and the requested memory cycle
to be held off until the update/refresh cycles have been completed. If AS
goes low with CS2 high while hold is true, the CPU line RDY is deasserted
and a cycle counter is started. When the update/refresh cycle is completed,
RDY is kept deasserted until the cycle counter indicates that the CPU is in
state T2. That is, the CPU is in a state equivalent to where it asserted AS,
thus the cycle continues as though it had started normally.
3.5.3.2 Video Timing Diagrams

The video timing diagrams are located in Appendix A.

)

VS410 System Module Detailed Description

3-91

3.5.3.3 Video RAM and Cursor Data Combination and Output
Figure 3-45 shows a simplified block diagram of the video RAM and cursor
data combination and output circuits.
Figure 3-45: Video RAM and Cursor Block Diagram

CURA3: 0
CURD3: 0

AND
XOR

SERIAL
OUT

V1DRESULT
3:0
4-81T
SHIFT
REG.

VDAT3: 0

LOAD
VIDCLK

LD
SHIFT
PORTION OF STANDARD CELL

3.5.3.3.1 Video RAM Input Data (VDAT3:0)
The 16·bit output from the video RAMs are multiplexed to four bits which
are input to the standard cell on VDAT3:0. VDATO is the first of the four
bits output in the serial dot stream.

The basic video dock input to the standard cell is VIDCLK. It is divided by
four to produce NIBBCLK. This is the count input to the horizontal timing
generation and is also output to the cursor chip. Data input to the standard
cell is four bits wide as described above. The four bits are selected from
the 16 bits from the video RAMs by the two signals SELY and SELX. During
one cycle of NIBBCLK, the current four bits of data are converted to serial
output when LOAD ENABLE is asserted as shown in Figure 3-46.

3-92

VAXstation 2000 and MicroVAX 2000 Technical Manual

Figure 3-46:

Video Dot Cycle Timing

1IIDClK
NIBBCLK

LOAD

----.J

3.5.3.3.2 Cursor Data (CURA3:0 and CURB3:0)
The B-bit output from the cursor control chip is input to the standard cell
on these 8 lines and is combined with the video RAM output data to form
the final video dot stream (DOTS). The combination is done on a bit basis
prior to the result being loaded into a 4-bit shift register. For example,
VIDRESULTO is derived from the logical AND of VDATO and CURBO. The
result of this logical AND is then exclusive-ORed with CURAO. This is done
for all four bits.
3.5.3.3.3 Synchronization Output Pulses (HSYNC and HSVS)
The video dock (VIDCLI<) is divided by four to form NIBBCLI<, this then
is used as the dock to the horizontal timing which generates HACTIVE
(internal signl) and HSYNC. The overflow from the horizontal timing is
used as an enable to the vertical timing counters which produce VACTIVE
(internal signal) and VSYNC (internal signal). HSYNC and HSVS are output
to the monitor. HSVS is the logical OR of HSYNC and VSYNC. Horizontal
timing is generated by a synchronous B-bit counter whose states are decoded
to generate HSYNC and HACTIVE as shovvn in Figure 3-47.

VS410 System Module Detailed Description 3-93

)

Figure 3-41: Horizontal Timing Generation
HAcnllE

~':-----1/

_--:.1-....

HSYNC

'-':-----1~

,. -.:,. 1_ _ _ _ _ _. .:.1. . ,

'-./

~I_

'-./

I I.....

COUNTER STATE· 64
..... COUNTER STATE. 35

..... COUNTER STATE. 3
..... COUNTER STATE. 0
.....--

TOTAl. COUNT. 320

Vertical timing is generated by an 8-bit asynchronous counter which is
clocked by the low to high transition of HACTIVE as shown in Figure 3-48.
Figure 3-48:

Vertical Timing Generation

-t/

.....--~/

VACnllE --...........,._ _ _

I
I
~YNC~--~-------------------....~

I"'"

COUNTER STATE· 36

..... COUNTER STATE - :3
..... COUNTER STATE - 0
.....-TOTAl. COUNT - 901

3-94 VAXstation 2000 and MicroVAX 2000 Technical Manual

3.5.3.3.4 Video RAM Shift Pulses (SRAMl :0)
Pairs of video RAM chips are shifted separately using two shift pulses, the
second of which is delayed from the first by two NIBBCLI< periods (116 ns).
This allows the maximum time for the video RAMs to present new data to
the standard cell.
3.5.3.3.5 Shift Register Update Mode Select (Dl/OE)
This output line selects whether the video RAMs are operating in normal
random access read/write mode (DT/OE high when VRASchanges from high
to low), or shift register update mode (DT/OE low when VRAS changes from
high to low).

3.5.4 Input/Output Control

)

Input and output (I/O) decode is done for all the devices and for some of the
options. Addresses are decoded only to the level necessary to specify the
device. All 110 cycles are extended to at least 600 ns. The TOY clock cycles
are extended to 800 ns and certain operations involving the Ethernet network
controller cause even longer cycles to occur by controlling the SCYC/IAD2
input to the standard cell. This section describes how the 110 control signals
are implemented.
3.5.4.1 Configuration end Test Register Enable (SYSREOEN)
This is an enable signal to a general purpose register that is active low when
an address in the range 20020000:200200FF hex is decoded and also when
CS2 goes high when AS changes from high to low. It is low from the CLI<O
low to high transition following the AS transition until AS returns to the high
state. If WRITE is low when this address is decoded then DALDIS is driven
high.
3.5.4.2 System ROM Enable (ROMeS)
The system ROM occupies 1/0 space and is controlled by ROMCS. ROMCS
goes true (low) for addresses in the range 20040000:2007FFFF hex when CS2
is high and AS has changed from high to low when WRITE is high and
DBE is low. ROMCS also goes low when DBE is low during an interrupt
acknowledge cycle where CS2 is low when AS goes from high to low, so
that the ROM may output a vector for the interrupting device. For these
cycles, ROM address bits 2:0 are output on lines IAD2:0.
3.5.4.3 Network Option ROM Enable (NIROMENA)
To allow for the network interface controller to have on-board ROM, this
output signal goes active (low) under the following conditions. An address
in the range 20010000:2013FFFF hex is decoded with CS2 high, when AS
has gone from high to low, and, WRITE is high and DBE is low.

VS410 System Module Detailed Description 3-95

3.,5,4,4 Video Option ROM Enable (OPTROMENA)
A signal similar to NIROMENA, except that it is active
the
20140000:2017PFFF hex. It is intended for use by the option in the general

purpose
3.5A.5 TOY Clock Control (CLKCS, CLKAS, and CLKDS)
The time-of-year
chip requires a longer
than other peripheral
devices. Bus cycles directed to the TOY chip are ext€:nd~~d bv an additional
microcycle and three control signals iilf€: generated to 3ccomn10date
sIOt\'
chip timing.
«

is asserted (low) when an address in the range 200130000:
200BOOPF hex has been decoded with CS2 high. fm.m the
to
low tran.:::ition of AS. to the
lov\.' to high transition

CLKAS is asserted (low) 75 n~'
asserted at the next low to high

CLKDS is a~5ert€d (highl as il function of the crus WRITE
If\'VRfTE is high (read from the TOl:'
chipL
goes
(high) 200 os after CLKCS
true, and remains high until the next
If WRITE is 10\'\'
to the T(Tt' dod:
Imv to high transition of
chip), DS g()€S high 200 ns after
for 350 ns.

low and is de-

3.5.4.6 System Error, tnterrupt Control and Video Control Registers
There are {our registers internal to the standard cell that report and control
parity error generation and checking,
interrupt masks for all the
standard peripheral devices
in.to the video RAM
the start of screen.
3.5.4.6.1 Memory System Error Register (MSER)
f<egister 'tI.fSER
20080004
contains information relating to the
parity checking of the machine
bits are read·only an.d some are
readlwrite. Parity generation and checking is performed for all
RA~1,'1 on a byte basis.

CPU ERR line to be
(low)
Detection of a parity error causes
and held lo~v until the end of a subsequent da:a strearn
cycle. At thE:'
time a parity error is detected, the memory page address is .latched and
held until the error has been cleared. Note that there is no provision for
detection of further parity errors in the interval behveen the time that the
parity
logic has detected an error and the time that the initial error
has been cleared (by a write to the MSER Registetl See SecHon
1.5 for
an expianation of this register.

3-96 VAXsfation 2000 and Micro\/il,X

Technica! Manual

3.5.4.6.2 CPU Error Address Register (CEAR)
Register CEAR (address 20080008 hex) is used to save the address at which
a parity error was detected. The contents of this register are only valid when
a parity error has occurred and CPU LPE is set (MSER5 - 1). This register
is read-only. Bits 31:15 are read as 0 and 14:00 are the failing address bits
23:09.
3.5.4.6.3 Diagnostic Register
The diagnostic register (address 20080000 hex) is used for diagnostic purposes. This register is a read/write and is a full 32-bits wide.
3.5.4.7 Interrupt and Video Control Register (IVCR)
This 32-bit register (address 2008000C hex) is made up of four separate 8-bit
registers; the system interrupt mask register (lNT_MSK), the display origin
register, the single bit (the other seven bits are not used) register used to
select the source of the end of frame interrupts which can be the internal
video controller or the optional video controller, and the pending interrupt
status register (INT_REQ). Figure 3-49 shows the contents of this register.
Figure 3-49: Interrupt and Video Control Register (IVCR)
3

2 2

4 3

INLREQ

NOT USED

SVINT

8 1

DOR

VS410 System Module Detailed Description

3-97

Data Bit

Definition

Readlwrite (bits 31:24).
This 8-bit register contains the latched result of an active INT_CLR transition on anyone of the eight interrupt lines.
Interrupt level 7 is reported in bit 31; interrupt level 0 is .reported in bit 24.
A write to this 8-bit register clears any bits set according to the bit pattern in 31:24.
23:17

Not used. Read as O.

SVlNT

Read/write (bit 16).
Selects the sourCe of end of frame interrupts.
If cleared, the interrupt source is the internal video controller. This bit is cleared during power-up.

OOR

Tht!Se bits afe loaded with a value used
Read/write (bits 15:08).
by the internal video controller as an offset from the base address of the video RAM. The video RAM starts at address 3OOOOOOOH, and with
the offset register cleared, this address maps to the first 32 pixels of the first scan line of the display.
The offset register allows the first scan line data to be taken from 3OOUOOOOH + OOR ·400H.
If the programmed value of the offset is greater than 40, the
video controller wraps back to 30000000H following access to address 3001FFBOH as the video RAM is only 128 kbytes.
The offset register is cleared during power-up.

Readfwrite (bits 07:(0).
Individual interrupt enables for the eight
All interrupt ensources of interrupts supported by this chip.
ables are cleared during power-up.

3.5.4.8 Serial Line Controller Enable (SLUENA)
This signal is asserted (low) when an address in the range 200AOOOO:200AOOOF
hex has been decoded with CS2 high when AS goes from high to low. It is
used as the enable to the four line serial line controller.
3.5.4.9 Shift Silo (SHSILO)
This signal is asserted (high) for approximately 100 ns following any read
to address 200A.0004. It is used externally to shift the contents of the SLU
SILO following a read from the SILO.

3-98 VAXstation 2000 and MicroVAX 2000 Technical Manual

3.5.4.10 9224 Control Signals (CS9224, DS9224, and WR8224)
These three signals control the 9224 disk controller chip.
•

CS9224 is asserted (low) when an address in the range 200COOOO:
200C0007 hex has been decoded and CS2 is high and AS has gone
from high to low. It remains low until AS returns high.

•

When OS9224 is asserted by the CPU, it is low after CS9224 has
gone low, which is approximately 100 ns after OS goes low, to allow
for the long address strobe setup time of the 9224 chip. It goes
high again when OS goes high. When not asserted by the CPU,
this pin becomes an input and may be driven by the 9224 chip to
access the disk buffer RAM. When used by the tape controller chip,
it again is an output, used to control data transfer to and from the
tape controller chip and the disk data buffer.

•

WR9224 is asserted (low) when the 9224 chip is being addressed
by the CPU or when the tape control logic needs to write to the
disk data buffer. It is low when CS9224 is low and WRITE is low,
approximately 100 ns after OS has gone low. It returns high when
OS returns high.

3.5.4.11 Tape Port Control Signa's (SCSICS, SCSIRD, and SCSIWR)
Control of the tape port (SCSI) requires reading and writing registers within
the tape controller chip, reading and writing the OMA address register,
writing the byte count register, and specifying the transfer direction. Several
address ranges are decoded as follows.
•

200C0080:200C009F is used to address read/write registers within
the tape controller Chip. The signal SCSICS is asserted (low) and
either SCSIRO or SCSIWR is asserted depending on whether the
operation is a read or write. The tape controller chip is byte wide
and accepts data from or presents data to BOAL07:00.

•

200COOAO is used to load data into the OMA address register. This
register is external to the standard cell and is byte wide, write only.
When this address is decoded, SCSICS is generated, followed by
CTRLOAD.

•

200COOCO is a read/write DMA byte count register. On a write,
BOAL15:00 are loaded into the OMA byte count register, as selected
by byte mask bits 1:0. Byte mask bits 3:2 and BOAL 31:16 are ignored. The DMA byte count register is internal to the standard cell.
On a read, the contents of the OMA byte count register are returned
as BOAL15:00 as selected by BM1:0.

)

VS410 System Module Detailed Description 3-99

•

200COOC4 is used to address the tape port direction bit which is
a single bit write only register. SCSlpIR is loaded from BOALOO.
Any reads at this address returns all zeros.

3.5.4.12 Disk RAM Buffer Control (DBUFCE)

This signal is asserted when the disk buffer RAM is addressed by either the
CPU, the tape control logic or the 9224 disk controller chip. For CPU accesses, this signal goes low when an address in the range 20000000:20001FFF
hex has been decoded and CS2 is high, and AS has gone from high to low
and remains low until AS returns high. For 9224 accesses, this signal follows
059224.
3.5.4.13 Ethernet/SID ROM Enable (ElDENA)

This signal is asserted (low) when an address in the range 20090000:2009007F
hex has been decoded and CS2 is high and AS has gone from high to low
and WRITE is high. It remains low until OS goes from the low to high again.
It is used to access the machine ID ROM which also serves as the Etl:lernet
address ID ROM.
3.5.4.14 Network Interface Controller Enable (NIENA)

This signal is asserted (low) when an address in the range 200EOOOO:200EFFFF
hex has been decoded and CS2 is high and AS has gone from high to low.
It becomes inactive when AS returns high. It is used as the device enable
to the network controller option.
3.5.4.15 Cursor Chip Enable (CURSEL)

This signal is asserted (low) when an address in the range 200FOOOO:200FOOFF
hex has been decoded and CS2 is high and AS has gone from high to low.
It becomes inactive when AS returns high. It is used as the device enable
to the cursor control chip.
3.5.4.16 Video RAM Enable (SRAMO and SRAM1)

The video RAM occupies 110 address space as described in Section 3.5.3.
3.5.4.17 Video Option Enable (OPTVIDENA)

The signal is asserted (low) when an address in the range 38000000:3FFFFFFF
hex has been decoded and CS2 is high and AS has gone from high to low.
It is a general enable for use by an add-on video controller.

3-100 VAXstation 2000 and MicroVAX 2000 Technical Manual

3.5.5 Disk Control
Some of the disk control functions for both the floppy and hard (winchester)
disks are implemented within the standard cell and are described here.
3.5.5.1 Floppy Disks

Transitions received from the floppy disk are synchronized and delayed using a 40 MHz clock before being presented to the 9224 for data separation to
perform the nominal half-bit period delay. Signal RXDATA is synchronized
to the 40 MHz clock and then delayed by 500 ns or 1 microsecond (determined by SELHIDEN) before being used to control the PUMPUP/PMPDWN
control lines to the veo circuits on the system module.
3.5.5.1.1 Density Select (SELHIDEN)

)

When this signal is high, it indicates that the diskette is being read or written
at a data rate of 500 kHz and that the disk rotation speed is 360 rpm. When
it is low, the data rate is 250 kHz and the rotation speed is 300 rpm.
3.5.5.1.2 Select Floppy Disk/Winchester Disk (SELRX)
When this signal is high, it indicates that a floppy disk is selected. When it
is low, it indicates that a winchester disk is selected.
3.5.5.1.3 Read Gate (RDGATE)

This signal is from the 9224 disk controller chip and indicates that valid data
is being read from the selected disk drive. It is also used to switch the phase
comparator logic from the internal clock to the recovered dock.
3.5.5.1.4 Drive to External Delay Line (TODELA Y)

For winchester disks, an external delay line is used to provide the nominal
half-bit time delay used to control the phase comparator rather than the
digital delay used with the floppy disk drives. This output drives that delay
line. It is a bidirectional pin so that 1/0 pad driver delays on this signal and
on the signal FMDELAY may be equalized.
3.5.5.1.5 Receive from External Delay Line (FMDELA Y)

The output from the delay line that is used with the winchester disks is used
to provide the nominal half-bit delay for the phase detector.
3.5.5.1.6 Floppy Disk Read Data (RXDATA)

Transitions received from the floppy disk are received on this signal. If
SELRX is high, a low to high transition on this line causes the ARM phase
detector flipflop to be set. This enables the digital half-bit time delay.

VS410 System Module Detailed Description 3-101

3.5.5.1.7 2 Megahertz Voltage·Controlied Oscillator (VC02)

This signal is from the output of the VCO circuits on the system module
and is used for floppy disk data recovery.
3.5.5.2 Winchester Disks

This section describes the signals associated with the 'winchester disk drives.
3.5.5.2.1 Drive 0 Read Data (RDODAT)

This signal is the raw data stream from the winchester disk and is selected
when line SELRX is low and line RDUNIT is low.
3.5.5.2.2 Drive 1 Read Data (RD1DAT)

This signal is the raw data stream from the winchester disk and is selected
when line SELRX is low and line RDUNIT is high.
3.5.5.2.3 Select Winchester Unit (RDUNIT)

This signal selects one of two winchester disk drives as described above.
3.5.5.2.4 20 Megahertz Voltage-Controlled Oscillator (YC020)

This signal is the output of the 20 MHz VCO and is used for winchester disk
data recovery.
3.5.5.3 Common Signals

This section describes the common signals used by the standard cell.
3.5.5.3.1 40 Megahertz Clock (CLK40)

This signal is the input of a nominal square wave from an XTAl oscillator
and it is divided to produce 0.5, I, 5 and 10 MHz. All of these are used
within the standard cell. The Sand 10 MHz signals are also outputs on
ClKS and·CLKI0 signals, respectively.
3.5.5.3.2 Read Clock to 9224 Disk Controller (RCLK)

This signal is sent to the 9224 disk controller chip.
3.5.5.3.3 Pump UP Control Signal to YCO (PMPUP)

This signal is used to increase the frequency of the external VCO.
3.5.5.3.4 Pump Down Control Signal to YCO (PMPDWN)

This signal is used to decrease the frequency of the external veo.

3-102 VAXstation 2000 and MicroVAX 2000 Technical Manual

3.5.5.3.5 Read Data (RDATA)

This signal is sent to the 9224 disk controller chip.
3.5.5.3.6 10 Megahertz Clock (CLK10)

This signal is a 10 MHz dock which is generated by dividing the CLK40
signal by four. This signal is high for 50 ns and then low for 50 ns.
3.5.5.3.7 5 Megahertz Clock (CLKS)

This signal is a 5 MHz clock which is generated by dividing the CLK40 signal
by eight. This signal is high for 100 ns and low for 100 ns.
3.5.5.3.8 Test Points (TP1, TP2, and TP3)

)

These signals are used to assess the performance of the phase locked loop.
TP3 is connected to ground. TPl and TP2 are connected to the input side of
the edge-catching flip-flops of the phase comparator. The output of these
flip-flops are the PUMPUP and PUMPDWN signals on the standard cell. To
use them for troubleshooting the phase locked loop, set the phase locked
loop to one of the reference frequencies by inhibiting the disk controller
from reading data from the disks so the pulses are steady. Measure the
phase error on the positive edges of the signals. It does not matter which
signal (TP1 or TP2) you sync on. For the hard disks, there should be no
more than 3 ns of phase error between TPl and TP2. (Typically, it should
be .5 to .2 ns.) For the floppy diskette, there should be no more than + '-14
ns of phase error.

3.5.6 Tape Control (SCSI)
The control signals SCDRQ, SCSIDACK and SCSIEOP, with the DMA byte
count register (SCD_CNT) and the SCSI direction bit (SCDIR), control the
operation of the tape port. When the tape controller has been programmed
for a transfer to the disk buffer by the CPU chip, the transfer sequence is
as follows.
1. The tape controller asserts SCSIORQ (high).
2. The signal SCSIDACK is then generated by the standard cell. The
signals SCSIRD and WR9224 are also generated at this time.
3. One CLKO period later, DS9224 is generated.
4. When the byte count register (SCD_Cm) contains FFFF, SCSIEOP
is asserted.
5. DS9224 and SCSIEOP are asserted for three CLKO periods (150 ns)
and then both deasserted.

VS410 System Module Detailed Description

3-103

6. One CLKO period later, WR9224, SCSIRD and SCSIDACK are deasserted.
When the tape controller has been programmed for a transfer from the disk
buffer by the CPU chip, the transfer sequence is as follows.
1. The tape controller asserts SCSIDRQ (high).
2. The signal SCSIDACK is then generated. The signal WR9224 is also
generated at this time.
3. One CLKO period later, SCSIWR is asserted.
4. When the byte count register (SCDSNT) contains FFFF, SCSIEOP
is asserted.
5. Three CLKO periods later, SCSIWR and SCSIEOP are de-asserted.
6. One more CLKO later, SCSIDACK is deasserted.
The tape port timing diagrams are located in Appendix A.

3.5.7 Parity Generation and Checking (PBIT3:0)
For all program RAM (address range OOOOOOOO:OOFFFFFF hex), parity is generated on write and checked on read as specified by the byte mask bits if
parity check is enabled. Parity is not carried in the video RAM.
A parity error causes a fatal machine check. The line ERR is asserted from
the time of the parity error detection until after the next data stream read
cycle, ERR causes control to be passed to the ROM restart address 20040000
hex.

3.5.8 Interval Timer Interrupt Generation (INTTIM)
This signal provides a source of interrupts at a 10 millisecond rate. It counts
down the 40 MHz clock.

3-104 VAXstation 2000 and MicroVAX 2000 Technical Manual

3.5.9 Interrupt Controller
The interrupt controller portion of the standard cell uses three registers to
process interrupts generated by 110 devices. These registers are interrupt request (INT.REQ), interrupt mask (INT.MSK), and interrupt clear (INT CLR).
Table 3-14 lists these registers and Figure 3-50 shows the format of these
registers. Note that the definition of each bit is the same in all three registers
and that each bit is in the same position in all three registers.

Table 3-14: Internal Interrupt Registers
Regilter Name

Definition
Thill register holds the latched interrupt requests received from 110 devices (read-only).

)

This register contains a mask which determines which interrupt requests generate a processor interrupt (read/write).
This register, which occupie!! the same physical rpgister as INT.
REQ. enables a program to selectively reset interrupt request
bits in the lNT.REQ register (write-only for INT.ClR).

Figure 3-50: Interrupt Register Formats (INT.REO. INT.MSK, INT.eLR)
7

Sft

Data Bit

Definition

Serial Une receiver or silo full

Serial Une transmitter done

Network controller primary

Network controller secondary

Video end of frame

Video secondary

SCSI controller

Disk controller

VS410 System Module Detailed Description 3-105

3. 5.9.1 Interrupt Request Register (INT}=JeQ)
The interrupt fl.:'quest register is an g·bit read'only H:gister at physical ad·
dress 2008JlOOF Each bit reflects the state of the inlerrup! request latrh for
one interrupt source. Bits
correspond 10 interrupt ranking ,lS
in Section 3.5.95,
A bit in the iNT REQ f(>gistt'r is set oni)' bv an active transition on the
corresponding de\'ice's i~-terrupt request 'line, Thl:' bit is set by an "clive
transition regardless of the state of the corresponding bit in the interrupt
mask re,~ister !NT.MSK, However. an interrupt request is sent to the CPU
only when the- corresponding bits in both fNT)ZEQ and INT :MSK are set.

A bit in the INT.REQ register is cleared bv writing to the INT CLR register
with it one in the corresponding bit
t.ne
bit set
in INT REQ is cleared autornatically during a CPU Interrupt
cycle
long as the corresponding' bit in rNT}\ISK is alsl~ set Note
INT,.CLR and INT)~EQ are the same physic)!
and that the
function occurs during writes to this regist€'!'.
INT.
be
at
time. Reading it does not alter the stale of the :;;vstem in
The
.REQ i~ dea~ed to 0 during the
-

3.5.9.2 Interrupt Mask Register (INT.MSK)
The interrupt mask register is em 8-bit read!wnte register at physical address
. &'1(h bit is a mask for one
sot'irce. Bits io
!.o interrupt numbers 7:0 as listed in Section
9.5. Each mask bit is
(nih ended with Ihe
bit of the INT
zer,j result is needed before
priority -encoder or
CPU Interrupt requesl
If a rnask bit is 0, the
s
latched request lif am) is not presented to the
device fwm

The

1113Sk

is cle;ued to () during the

3-106 VAXslation 2000 and MicroVAX 2()OO

Manua.l

3,5.9,3 tnterrupt Clear Register (INT, CLR)
The interrupt dear register is an iH~it ,.trite.on!y regIster at physical address
2008000F.. \\'hich is used Ie.) seJectively dear bits in the INT.REQ
For each bit of TNT
that is a one, the corresponding bit of INT_REQ is
cleared. The effect 01. wn!tr.g to INT.CLR is transient Its contents are no!
stored and "\-'THing to it does not prevent
bits from being s~,t
in the future.,

3.5.9.4 Interrupl Vector Generation
Once an interrupt is declared valid. the controller asserts the lntenupt If;'
quest line to the CPU, When the CPU acknowledges the interrupt, the imer
rupt controller sends the address of the interrupt vector to the system ROM
over the address bus. This address is cakulated using the interrupt number
(7 through OJ of the ItO device, which also corresponds to the bit position
in INT.REQ, in the following formula.
ROl,,1 address "" 2004.\)020 + (interrupt number • 4}
This address, once it is
points to Oile of
longvvc.rds in the
system
whICh h{'Jds the interrupt vector for that particular I/O devlce .
Figure 51 shows the format. of an Interrupt vector longword iI, ROM.

Figure 3-51:

Interrupt. Vector I..ongword

3
1

o9
... 0, ,..

~~:

Data Bi!

Dehnihon

31 :10

19norro . 5h~mld N: O.

VNUI\~

!r;terrup~ v£'ci('t nclmbe)',

o
VNUM

Vecl.CIr

2e.1)

S~;.rial

!ine ((lntrcJler .re-cl'iliver dJ)rt(,~ or sOo

IuLi,

Networ}: controlk7
lion mCldu)f~ \.

\/5410 System

3-101

Vector

Source

254

Network controller secondary (network o~
tion module,.

244

Video end-of·frame (system module or video
option module, according to the VDC.SEt
register).

248

Video controller secondary (video option mod·
ule).

3F8

Tape controller (5380).

3FC

Disk controller (9224).
Bit 0 is the priority level flag which selects
the IPL in the CPU. If this bit is 0, the IPL
is 14h. If it is 1, the IPL is 17h.

3.5.9.5 Interrupt Sources and Ranking

Table 3-15 lists the interrupt sources from highest to lowest priority. The
interrupt numbers 7:0 indicate their bit positions in the INT.REQ, INT.MSK,
and INT.CLR registers and also indicate their relative priority when more
than one request is pending. Interrupt 7 represents the highest priority.
The edge column indicates the signal transition, positive or negative, that
sets the device's bit in the INT.REQ register (the opposite transition has no
effect).
Interrupts 0, 1, 6 and 7 are dedicated to devices on the system module.
Interrupts 2, 4, and 5 come from devices attached to option module
connectors. Interrupt 3 comes from either the system module or from the
video option connector, according to the setting of the VDC_SEL register.

3-108

VAXstation 2000 and MlcroVAX 2000 Technical Manual

Tc:?J.~_,~":~. ~_:_.,~nt~ nu p!_. ~~i.~:!!t Ran k~~_____.._._ ..______..__. __.,.
Priority

Name

Edge

Interrupt source

"
{

Sf(

f'ositivt

Serla.! line col'moller ren;l\'er done OJ silo fun

Negathe

NI;'nA·or.k controller primary

Neg"I!Ve

Nerwor.k controller
module I

\iF

Negative

Monochrome video end-of·frame Of vid€'0 (1),
tion module
to the
.

Serial lin!:' controH~r transmitter done

mod-

(networ}:, option

Video mntroller
ulf')

Taf'€ controller

Fositi\'t

[hsk wntroHel

3.5.9.6 Video Interrupt Seleet Register ('JOe.SEl)
The source of the video end·or-frame interrupt signal (priority 3 in Table 3-151 is determined bv the
SEt register, which is a one-bvte
n:adhvrite register at address 200e.GOCIE. Figu.re
shows the video ·in·
terrupt select register.
Figure 3-52:

Video Interrupt Select Register (VOC~SEL}
1

[
Data Hll

Definition

Rt'served. RE'turn&
O'~<

13CWT

If thi" hil is O. internlFl :;, romes horn th;
({mtrcill:'T on the
module. H bit (l is!. th" inter·
J'upt comes from t hI" cOfHwller {IO thf; v.idE'o
is cleared \0 r.;
rower·u!, initializ.ation.
3 source

System Module OelaHed Description

3-,,09

3.5.10 Monochrome Video Display Controller
The video display controller generates a monochrome image which is 1024
pixels wide by 864 pixels high. The controller consists of one bit-mapped
display data plane. It can superimpose a cursor at any position on the
display independently of the contents of the data plane.
3.5.10.1 Video Timing
All video timing is derived from the pixel dock crystal whose frequency
is 69.1968 MHz, which yields alixel time of approximately 14.5 ns. The
timing of the synchronization an blanking signals cannot be changed by a
program. Table 3-16 shows monochrome video timing.

Table 3-16: Monochrome Video Timing
Frequency Type

Frequency

Pixel

69.1968 MHz

Horizontal

54.06 kHz

Vertical

60.0 Hz

Horizontal Timing

Microseconds

Pixels

Entire line

18.50

1280

Visible raster

14.80

1024

Active line time

14.798

Blanking

3.70

256

Sync front porch

0.173

Sync pulse width

1.85

128

Sync back porch

1.676

116

3-110 VAXstatlon 2000 and MicroVAX 2000 Technical Manual

Vertical Timing

MiUiseconds

Lines

Entire frame

16.667

901

Visible raster

15.982

864

Blanking

0.684

Sync front porch

0.000

Sync pulse width

0.055
0.629

Sync back porch

)

3.5.10.2 End..of·Frame Interrupt
An interrupt request is generated at the trailing edge of each vertical sync
pulse, which is three horizontal scan times after the beginning of each vertical blanking interval. (The interrupt vector is listed in Section 3.5.9.4).
The time between this interrupt and the end of the vertical blanking interval is approximately 620 microseconds (34 line times). Interrupts occur at
the frame rate of 60 Hz. Interrupts may be masked by clearing bit VF of
the interrupt mask register (INT.MSI<) to zero (See Section 3.5.9.3). Upon
power-up, this mask bit is cleared to zero. In order for this end-of-frame signal to be recognized as an interrupt, the VDe SEL register (Section 3.5.9.6)
must be set to select this source rather than the video option module.
3.5.10.3 Data Plane Storage
The display data plane is stored in a 1281< byte block of dual port RAM. It
occupies the physical address range 3000.0000 through 3001.FFFF. Access
to the RAM can be byte, word, or longword.

)

One displayed line of 1024 pixels is represented by 32 consecutive longwords, beginning at an address whose low-order 7 bits are all 0 (that is,
a multiple of 128 decimal). Each longword appears as 32 consecutive pixels on a display line. Bit 0 of a longword (least significant) is displayed as
the leftmost pixel and bit 31 (most significant) is displayed as the rightmost
pixel of the 32-pixel group. Longword addresses increase from left to right
across a displayed line and exactly 3210ngwords are required for each line.
The 1281< byte data plane storage holds 1024 line images, 864 of which are
visible on the display at anyone time.

NOTE: An e"or in the standard cell allows part of the 865th line to be visible. To

fix this problem, ensure that the 32 longwords following the last display scan line
contain O.

VS410 System Module Detailed Description 3-111

3.5.10.4 Display Origin Register (VDC_ORG)

The address in the data plane storage which corresponds to the top line of
the display raster is determined by the 8·bit readlwrite register VDC.ORG,
whose address is 2008.0000. This register supplies bits 16:9 of the address
of the top line. Thus, the address of the first longword in the topmost
displayed line is:
Address ... 3000.0000 + (VDC.ORG * 512)
The visible display can begin on any 4-line boundary and wraps from the
last line in the data plane storage (beginning at 3001.FF80) to the first line
(beginning at 3000.0000). The contents of VDC ORG are used at the beginning of the vertical blanking interval to reset the video controller address
counter. Register VDC.ORG can be written to at any time. The contents of
VDC.ORG are cleared to 0 at power-up.
Changing VDC.ORG does not affect the displayed position of the cursor
sprite on the screen. The sprite's position registers operate relative to the
first line displayed, regardless of what memory address it comes from.

3.5.11 Test Mode (TEST)
This signal is a general test input which modifies some internal connections
to facilitate the standard cell's chip test as explained below. The standard
cell is in test mode when jumper W5 is removed.
3.5.11.1 Interval Counter

This consists of four sections: divide by 10, divide by 25, divide by 25 and
divide by 32 counters. These are normally cascaded to count down the 20
MHz dock to 100 Hz. In test mode, each counter has the input dock gated
directly to its count input and each section output may be observed at the
INTTIM output which is selected by OAL31:30 as shown in Table 3-17.

Table 3-17: Standard Cell Test Mode Addressing
DAlJl

DA130

Divide by 32

Second divide by 25

First divide by 25

Divide by 10

3-112

INTTIM

VAXstatlon 2000 and MicroVAX 2000 Technical Manual

3.5.11.2 Vertical Timing

When TEST is high, the input to the vertical timing counters is changed from
HACTIVE to NIBBCLK to allow a faster test.
3.5.11.3 Video RAM Shift Register Update/Refresh

When TEST is high, the count inputs to the update address counter and
the refresh counter can be accessed using CLK40 and a combination of
DAL02:00.

3.6 DC503 Cursor Sprite Chip
This section describes the DC503 cursor sprite chip (Figure 3-53).

)

3.6.1 Overview
The DCS03 cursor sprite chip generates a cursor display on the video moni·
tor. The cursor is generated from a two plane memory array within the cursor chip. Refer to Section 3.S.3 for video timing and control infomlation.
This chip is not implemented when the system module jumper is set for
MiaoVAX 2000 usage. Figure 3-54 shows the pinout of the DCS03 cursor
chip and Table 3-18 lists the chip signals and their deSCription.

VS410 System Module Detailed Description 3-113

Figure 3-53:

OC503 Cursor Sprite Chip

rinnr:n

o LJuuuu

Ii
,

, i
1 ......

r"';

~-'

f'
I

l i
w

L.J

3-114

VAXstalion 2000 and MicroVAX

Technical Manual

Figure 3-54: DC503 Cursor Sprite Chip Pinout

tm~t'5

4~.

a::A!.~"

~;:'

a;:.;,LJ.!.:5,

4.l

aJ;),A,t.~2:

SD.~:.i:

fm •. L'0

SDALOS

S{)A~"ae,

S0A~07

aOAL(}6

2f,

Bt:,ALDe,

Z:~

arlAUi.t

aJ,~:'O.3

f10~~Q;:

S{),A,LO~,

BUALO,;

vt?AtC~1

1(;

VtlA,CJ4

iii

\/!JAlO::

\;,tfALC:2
\.:,.'.'S

CL;:J:i:SL.
BWRI;f: C

0,'11'1(;
il,,""~'

Ni8Ci<.

CURac
;;"

CUR?.,

CURS"

VS410 System Module Detailed Description

3-115

Table 3-18: DCS03 Cursor Sprite Chip Pin Description
Signal

Description

Signal

Description

BDAL15

Data bus bit 15

BDAL14

Data bus bit 14

Data bus bit 12

Data bus bit 10

BDAL13

Data bus bit 13

BDAL12

BDAL11

Data bus bit 11

BDALI0

BDAL09

Data bus bit 9

BDALOS

Data bus bit 8

BDAL07

Data bus bit 7

BDAL06

Data bus bit 6

BDAL05

Data bus bit 5

BDAL04

Data bus bit 4

BDAL03

Data bus bit 3

BDAL02

Data bus bit 2

BDALOI

Data bus bit 1

BDALOO

Data bus bit 0

VDAL05

Address bus bit 3

VDAL04

Address bus bit 2

VDAL03

Address bus bit 1

VDAL02

Address bus bit 0

VAS

Address strobe

CURSEL

Data strobe

BWRITEO

Write enable

HSYNC

Horizontal sync

BLANK

Blank

NIBCLK

Clock input

CURAO

Plane A bit 0

CURAI

Plane A bit 1

CURA2

Plane A bit 2

CURA3

Plane A bit 3

CURAO

Plane B bit 0

CURAI

Plane B bit 1

CURA2

Plane B bit 2

CURA3

Plane B bit 3

CURTST

Test pin

3.6.2 Cursor Coordinate Offsets
The visible raster is 1024 pixels wide in the X direction and 864 lines high in
the Y direction. The nominal range of cursor coordinates is 0 through 1023
(left to right) and 0 through 863 (top to bottom). An offset must be added to
nominal raster coordinate values before loading the values into the cursor
position and region limits registers, because the X and Y position counters
are reset at some time prior to the beginning of the visible display. The
offset values are listed in Table 3-19.

3-116 VAXstation 2000 and MicroVAX 2000 Technical Manual

Tabre 3-19: Cursor Coordinate Offsets
Offset

Val.ue

X offset

216

Yoffset

33 lines

For example, to display Cl sprite cu.rsorwith its upper left ('(wner in pixell0(J,
line 300, a program must load CUR.
with (100 + 216) and CUR_
with (300 + 33)

3.6.3 Cursor Generation
The cursor can take h.vo
a. 16·blt by It.-bit pattern (sprite), or a
crosshair whose lines may extend to the edges of the \>'1sible raster or may
be dipped to a programmed
The curSN hardware uses a DC 503
programmable sprite cursor chip which generates two display planes called
the A and B planes, Bits from these planes are comhined with bits from the
data plane and the p()ssible combinations are listed in Table 3-20,

Generation Values
Table 3-20: Cursor
,--,----,
Data

A plane

BplaM

n,..'

Displayed

CUrf;Ot appearance

Black

Invisible

mad:

Black

VVll.ile

Inverted data

"'v'hite

iNhite

V',rhitt:

Inv\slbh:

Blach

Black

Blild.

inverted da ta

]

W'hitt"

\'VhHe

3,6.4 Cursor Control Registers
The cursor chip contain.£'< the foUo\'\'ing programmable elements
"

•

Tv,'o 16-",'Nd
cursor plane,

t(1

stOrt' a 16,bH by 16,bit sprite patter!)
to control where the cursor pattern is

VS4 j 0 Sys!em Module De1ailed Description

3-117

•

Two region detectors, each of which defines a rectangle in the raster
which can be used to dip the display of a crosshair cursor.

•

A control register which determ.ines hmv the cursor is generated.

To a program, the cursor chip appears as 12 ""He-only registers, each one
word {16 bits) wide. These registers should always be written with word·
access instructions; the\' cannot be read (hence read·modifv·wtite instruc·
tions such as DIS cann~t be used). The register's contents ~fter power·up
are indeterminate. The addresses and names of the registers are listed in
Table 3-21.

Table 3-21:

Monoch~ome Cursor Control Registers

Addres&

Name

200F.OOOO

CURCMD

200F.0004

CUR XP05

Cursor X position

200F.0008

CUR YPOS

CursorY position

200F,I)(XiC

CUR,- XMIN ., 1

Region 1 left edge

.20GF, 001 0

CUR -XMAX .-1

Region 1 right

200F.OO14

CUR YMiN 1

Region 1 top edge

200P,0018

CUR.,Y~1A..X ,1

Region 1 bottom

200F.OOlC

CUR -XMJN -2

Region 2 left edge

200EOO30

CUR .. X.MAX -2

Region 2 right edge

2 top

Region 2 bottom edge

Note

Cursor command register

2ooP,OO}4
2OOF.oms

CUR YMAX 2

20C~F.OO3C

CUR LOAD

Function

Cursor sprite pattern load

In order to prevent unsightly effects on the display, the registers marked
"1)" in the Note column are buffered, as are some of the bits in t.he CtlrSC!f
command register, The processor rna)' "Itrite into such a register or bit a.t
time l.except ,,yithin three horizontal scan times foHowing the beginning
vertical blanking), but the new value takes effect only at the beginning of the
next vertkal blanking interval, Since the processor receives its end-of,frame
interrupt signal three line times after vertical blanking begins. a program may
ensure that it has ample time to perform a multi· register update by waiting
for the end-oi-frame interrupt before starting to load new values. From the
time of the interrupt, it has nearly anentirt~ frame time (16612

to load the registers.'

3-118 VAXstation 2000 and MicroVAX 2000 Technical Manual

3.6.5 Cursor Command Register (OUR_CMD)
The cursor command register is a 16-bit write-only register at address 200F .0000.
As in the preceding list of cursor registers, the bits marked with "0" in Figure 3-55 are buffered and do not take effect until the beginning of the next
vertical blanking interval.
Figure 3-55: Cursor Command Register (CUR_CMD)

TEST

BSHI

VBBI LODSA FOR02 ENR02 FOROl ENROl
D
D

XBWID XBCLt XBCLP XBAIR FOPB
D
D
D
D

ENPB
D

FOPA

ENPA
D

Data Bit

Definition

TEST

Diagnostic test (bit 15). This bit must be 1 for normal operation.
When this bit is 0, the chip is placed in test mode, which is discussed
below.

HSHI

Horizontal sync polarity (bit 14). This bit must be 1 to indicate to the
chip that the horizontal sync input from the video controller is active
high.

VBHI

Vertical blanking polarity (bit 13). This bit must be 1 to indicate to
the chip that the vertical blanking input from the video controller is
active high.

LODSA

Load/display sprite array (bit 12). When this bit is 0, the cursor sprite
is displayed normally from the contents of the sprite arrays. When
this bit is 1, display of the sprite is inhibited and the sprite arrays can
be loaded by successive writes to the CUR.LOAD register. Upon the
transition of LODSA from 1 to 0, the internal array address counter
is reset so that the next write to CUR LOAD will load the top row of
sprite plane A.
-

VS410 System Module Detailed DescriptIon 3-119

Data Bit

Definition

FORG2

Force region detector 2 output to 1 (bit 11). When this bit is 1, the
output of region detector 2 is forced to 1 (true). When this bit is 0,
the detector operates normally.

ENRG2

Enable region detector 2 (bit 10). When this bit is 0, the output of
region detector 2 is inhibited; it is 0 (false) unless the FORG2 bit is
also set, which takes precedence and forces the output to 1 (true).
When ENRG2 is 1, the detector operates normally.

FORGI

Force region detector 1 output to 1 (bit 09). When this bit is 1, the
output of region detector 1 is forced to 1 (true). When this bit is 0,
the detector operates normally.

ENRGI

Enable region detector 1 (bit OS). When this bit is 0, (false) the output
of region detector 1 is inhibited; it is 0 unless the FORGI bit is also
set, which takes precedence and forces the output to 1 (true). When
ENRG1 is 1, the detector operates normally.

XHWID

Crosshair cursor line width (bit 07). When this bit is 0, the crosshair
cursor lines are one pixel wide. When this bit is 1, the lines are two
pixels wide. The extra pixels are added to the right of and below
the pixels which lie on the lines corresponding to the cursor X and Y
positions.

XHCLl

Select crosshair clipping region (bit 06). If this bit is 1, region detector
1 is used to clip the crosshair cursor; if it is 0, region detector 2 is
used. This bit is effective only if the crosshair cursor is selected (bit
XHAIR is 1) and crosshair clipping is selected (bit XHCLP is 1).

XHCLP

Clip crosshair inside region (bit 05). If this bit is 1, the crosshair cursor
is clipped so that it is displayed only within the region selected by the
XHCLI bit. If this bit is 0, the crosshairs extend to the edges of the
displayed raster. This bit is effective only if the crosshair cursor is
selected (bit XHAIR is 1).

XHAIR

Crosshairlsprite cursor select (bit 04). If this bit is 1, the cursor chip
generates a crosshair whose lines intersect at the cursor X, Y position.
If this bit is 0, the cursor chip generates the sprite pattern with its
upper left corner at the cursor X, Y position.

FOPB

Force cursor plane B output to 1 (bit 03). When this bit is 1, the output
from cursor plane B is forced to 1 throughout the display, regardiess
of the settings of bits ENPB, XHAIR, XHCLP, XHCL1, XHWID, and
of the contents of the sprite plane B array. When this bit is 0, the
cursor is displayed normally.

3-120 VAXstation 2000 and MicroVAX 2000 Technical Manual

Data !ill

ENPB

Definition
Enable cursor plime l3

""'hen thi!; bI! i~ 0/ the outpl"! from CUrSi)1'

plane 13 is inhIbited; it is (1 thWUg11(1U\ the display. When this bil is.!,
Ihe outpul from cursor

FOP.'\

B is displayed normally,

Force cursor plane A output to1 (vH Ol). 'Alhen this bit Is 1, the output
from cursor plane A js forced to 1 throughout the display, reg,)J'dless
of the settings of bits ENPA, XHAIR XHCLP, XHCU, XH\NlD, and
of the contents of the sprite plene A array. When this bit is 0, tbe
cursor if;: displilyed notrnal).\,
E.nnbll~ cursor plane A (bit
\.,'hen this bit is 0. the O1.!tpu! from
curs,")!" plane A is inhibited: H is (} throughout the cJsplay, \'I,'hen thie:
bit is 1, the
from cursor plane A is
normaHy

3.6.6 loading the Cursor Sprite Pattern
The cursor sprite pattern is stored in h·','o arrays, each made-up of sixteen
'It.-bit ''''lords. Each word dan arra}" is displayed as 16 pixels on a scan iine
"'lith bit (I fjeast significant) in the leftmost di~play pOSition, All 32 ",,tOrds are
loaded by writing to the CUR_LOAD register. An internal address counter
i.n the chip is incremented MhO'! each write to point to the next '''lOrd in thE!
array to be loaded,

Cursor command register bit LODSA controls access to the sprite anays
vVhen this bit is 0, the arrays are read during normal raster scanning to
display the sprite pattern. \\lhen LODSA is 1, normal display of the
is inhibited and data can be written into the arr'1ys. ChangIng LODSA
1 to 0 resets the intemnl array address counteL The next writE: to
_
LOAD loads the top hne of the A plane array, the next fifteen writes load
its rem.aining
The 16th through 32nd l"'Tites load the B plane
from top to bottom. When loading is completed, cursor command register
bit LODSA must be reset to 0 to resum.e norm.,.!. sprite display.

Loadmgthe sprite arrays should be synChronized by waiting for the end·(lf
frame lnteInlpt so that loading j$ done during the vertical bJanking i.n.terv<1L

NOTE;
registers o[

e<'UI'll!'!,

cursor

to while fhe

Any

othcl'

£lre being k'll/jed.

H) System Module Detailed Description

3-121

3.6.7 Cursor Region Detector
There are two region detectors, 1 and 2, each of which defines a rectangular
area of the raster which can be used to dip the display of a crossOOr cursor.
Each region detector is programmed by setting four registers: CUR XMIN,
CUR XMAX, CUR YMIN, and CUR YMAX. The horizontal boundaries of a
region are controlled by the CUR)<... registers and can be specified only
to a four-pixel boundary: the least significant two bits of their contents are
ignored and the system behaves as if those two bits were always O. The
vertical boundaries are controlled by the CUR.Y... registers and can be
specified to any line boundary. The offsets described in Section 3.6.2 must
be applied to the values loaded into these registers.
The contents of the ... MIN registers determine the leftmost pixel or topmost
line in a region. The contents of the ... MAX registers determine the first
subsequent pixel or line which is no longer in the region. In other words,
a ... MAX register should be loaded with the sum of the ... MIN value and
the width or height of the region. The contents of a ... MAX register must
always be greater than those of its corresponding ... MIN register.

3.6.8 Displaying a Sprite Cursor
A 16-by-16 pixel sprite cursor is displayed when cursor command register
bit XHAIR is cleared to O. The displayed position of the upper left comer
of the sprite is controlled by the contents of the CUR.XPOS and CUR YPOS
registers. The values loaded into these registers must include an offset as
described in Section 3.6.2. The cursor may be pOSitioned at any pixel in
both axes and may be positioned so that part of it falls outside the visible
raster.

3.6.9 Displaying a Crosshair Cursor
A crosshair cursor is displayed when cursor command register bit XHAIR
is set to 1. This cursor consists of a vertical line and a horizontal line which
cross at the point determined by the contents of the CUR.XPOS and CUR_
YPOS registers. The values loaded into these registers must include an
offset as described in Section 3.6.2. The cursor may be positioned at any
pixel in both axes.
Cursor command register bit XHWID controls the width of the lines. If
XHWID is 0, the lines are 1 pixel wide. If XHWID is I, the lines are doubled
in width by adding another line one pixel to the right of the vertical line and
below the horizontal line.

3-122 VAXstatlon 2000 and MicroVAX 2000 Technical Manual

The length of the lines is controlled by cursor command register bit XHCLP
If XHCLP is 0, the lines exhmd the full v,idth and heigh! of the rasteL If
XHCl.P is 1, the lines are dipped by the region detector selected by cursor

command register bit XHCL1: a 1 in XHCU selects region 1 and a 0
region 2,

3.6.10 Controlling Cursor Plane Outputs
For each cursor plane (A an.a B), there are tVI'o bits in the cursor command
register which control ea.eh plane's output, the enable bit and the force bit
The enable bit
piane A is ENPA and the enable bit for plane B is ENFB.
If either of these is 1, normal cursor data (sprite or crosshaJr) is generaH'd
for the corresponding plane. If either of these is 0, the corresponding plane
output IS ahvays O. Setting both of these bits to 0 suppresses the cursor
display so that the screen shows only the contents of the data plane ThesE'
ta.ke effect (mly at the start of a vertical blanking
bits are buffered so that
interval.

The force bit for plane A is FOrA tlnd the force bit for plane B is FOPB.
If either of these is 1, the output of the corresponding plane is always 1
throughout the entire display raster regardless of thE' state of the plane's
enable bit. The force bits are not buffered. They ta1:e effect imrnedialely
upon loading, These bits must be 0 for normal display operatl()!'l.

3.6.11 Blanking the Display
The screen may be blanked >\rithout disturbing the display daia pla.ne en
the cursor b)' using the cursor plane control hils to force the output of the
B plane to 1
cursor command register bit FOPB) and the A plane to ;)
(dear cursor command register bits FOPA and ENP

3.6,12 Cursor Chip Test
The cursor
has a tes:t fHpH0p which can be used to verify that
is hmcti(lning correcily, The state of this flipflop
in bit 4
figuratioll and test regIster
, The value of
bit is the
of thc' fhpfIop output. so it
value of 0 appears as a 1 in bit 4 and viet;·

ver:?,a .
activate the test
cursor command register bit
must be
cleared to U. The test mpflop is ch.:ared to 0 lvhenever the cursor CO.lnrnand registt'! lBI,vritten to. The test filpflop is srI tt.' 1 by the
of the output!' from cursor pli'lne Ar CmS~)I plane '8,
detectol 1, and
region detector 2.

\/5410 Sy'stem ModulI': Defafied Description

3-123

Note that a test requires one full frame time to execute. A test procedure
should wait for an end-of-frame interrupt, set up the test conditions, wait
for another end-of-frame interrupt, write to the cursor command register to
clear the test flipflop, wait for the next end-of-frame interrupt, and then look
at the test flipflop value.

3.6.13 Power-Up Initialization
Power-up initialization sets the following to true.
•

Controller select register VDC_SEL is OOh.

•

End-of-frame interrupt is masked off.

•

Display origin register VDC_ORG is OOh.

•

Cursor chip register contents are indeterminate.

•

Data plane storage contents are indeterminate.

The cursor chip requires two vertical blanking cycles to perform internal initialization before its registers can be loaded. To provide a clean appearance
on the monitor, the startup code should wait for at least 50 milliseconds (for
cursor chip internal initialization) and then set cursor command register bits
TEST, HSHI, VBHI and FOPB to 1 and clear the others. This sets the proper
sync signal polarity and blanks the screen by forcing the B plane output to
1 and the A plane output to O.

NOTE: The cursor command register bits TEST, HSHI, and VBHI must always be
set to 1 for normal operation.

3-124 VAXstation 2000 and MicroVAX 2000 Technical Manual

3.7 Serial Line Controller (DZ Controller)
The system module serial line controller (Figure 3-56) handles four asynchronous serial lines. The heart of the controller is a DC367B gate array.
Input characters from all four Jines are buffered in a common 64·position
silo. Only 1 line, the communication line, has full modem control signals.
Figure 3-57 shows the DC376B gate array DZ controller and Table 3-22 lists
the functions of the pins.
Figure 3-56: Serial line Controller

)

VS410 System Module Detailed Description 3-125

Figure 3~Sl! OZ Controller Chip Pinout

_lU,~~

"J\l,H
~~~:.

~"
f(}1;;.3'~'

·"«l"Al,.tlW

flJW.J6
00;.;..::1':Iif)AI.,~

.-: ......,.'M!
OO~

_1",,/.)..:-,

a:UIl:..1l2.
- B(!)J,Jr.

::~.~
tLhl! ~
i

\ . . . . . 1_

I----.......:j . ""'J,;»

,.
,.

l!MN1

~':t:::'I'\!

nm~;

~.~#

....
,~'\

~.r.x'l.

47"

s.,J.';;,,'I

s.o::

t.c
~I';'~

a.~

'S,J..~

1\;:;.,C
"''m","~;,.r
!JJI.,~':

?"'?_"n
~,~~~r

Cfro4,'

;::.cw,~;J'1":

,WAi

>1It4.1~.,,,"~A'l

KJU'lj\,~

~,~

.li!J
:P
."",

3-126

VAXstatfof1 2000 and MicroVAX 2000 Technical Manual

Table 3-22: DZ Controller Chip Pin Functions
Pin

BOAL15
BOAL14:8

26:20
28

BOAL1:1

OZMCLR

This signal is the modem dear line.

CPRESET

This signal is the reset signal from the standard cell.

CLKOZ

This signal is the dock input from the 5.0688 MHz oscillator.

30:31

ELA03:2

These signals are the latched address lines from
the CPU chip.

WRHB

This signal is the logical AND of CASt, BWRITEO, and
SLUENA. They indicate when the valid high address byte is on the BOAL15:00 bus.

WRLB

This signal is the logical AND of CASO, BWRITEO, and
SLUENA. They indicate when the valid low address byte is on the BDAL15:00 bus.

RDEV

This signal is the logical AND of VWRITE, VDS, and SLUENA. They indicate when valid data is on the
BOAL15:00 bus.

DZTINT

This signal is the transmit done interrupt line to the standard cell.

DZRINT

This signal is the receiver done or silo full Interrupt line to the standard cell.

DZDV

This signal is the shift out signal, The DZ controller outputs this signal when the silo is ready to output a character.
However, the silo does not
output the character until the standard cell asserts the SHSILO Signal.

ORD);,

This Signal is from the silo and indicates when
it is ready to shift out a character.

INDY

This signal is from the silo and indicates when
it is ready to receive another character.

SLCLR

This signal is the silo clear signal.
the silo when asserted.

11:11

)

Description
These signals are the address and data bus lines.

BOALOO

VS410 System Module Detailed DescrIption

It clears

3-127

Table 3-22 (Cont.): DZ Controller Chip Pin Functions
Pin

Signal

Description

SHI23

This signal Is the shift in line to the silo, It indicates when the high byte silo must shift in a character.

SHJOl

This signal is the shift in line to the silo. It indicates when the low byte silo must shift in a character,

41:42
45:50

SL07:06
SL05:00

These signals are the serial line character bus,
carry the input character to the silo.

PRDAT

This signal Is the input data from the printer serial line (line 3).

CRDAT

This signal is the input data from the communication serial line (line 2),

ARDAT

This signal is the input data from the auxiliary,
or pointer, serial line (line 1).

KRDAT

This signal is the input data from the keyboard, or console, serial line (line 0).

PTR_XDAT

This signal is the output data to the printer serial line (line 3).

COM_XDAT

This signal is the output data to the communication serial line (line 2).

AUX_XDAT

This signal is the output data to the auxiliary,
or pointer, serial line (line 1).

KBD_XDAT

This signal is the output data to the keyboard, or console, serial line (line 0).

3-128 VAXstatlon 2000 and MicroVAX 2000 Technical Manual

They

Table 3-22 (Cont.): DZ Controller Chip Pin Functions

)

Signal

Description

LLP_BCI<

This signal is the local loopback modem control
line. This line appears in the communication connector only.

COM_OTR

This signal is the data terminal ready modem control line.
This line appears in the communication connector only.

COM_OSRS

This signal is the data signaling rate selector modem control line.
This line appears in the communication connector only.

COM_RTS

This signal is the request to send moo£'m control line.
This line appears in the communication connector onty.

PTR_FER

This signal indicates that the break key (halt) chareKter has been received hom the printer serial line.
This halts the CPU when the BCCOB cable Is connected to the printer port (the BCCOB cable shorts
pins 8 and 9 which enable halts on this line.)

3.7.1 DZ Silo
The data is shifted into the silo in two bytes. The OZ chip controls which
byte is enabled by the shift-in (SHIOI and SHI23) Signals. SHIOI is shifted
in first, then SHI23 is shifted in. It takes approximately a microsecond for
the data to fall through the silo. The silo is a true silo where a character
drops through all 64 words in the silo before it is latched at the output. The
in-ready (IROY) signal indicates that the input is ready for another byte and
out-ready (ORO)') indicates that a byte has fallen through the silo and can
be read at the output. Figure 3-58 shows the OZ silo.

3.7.2 Line Identification
The four serial lines on the serial line controller are numbered 0, 1, 2, and
3. Table 3-231ists the use of each serial line.

VS410 System Module Detailed Description 3-129

Figure 3-58: DZ Silo Circuit Diagram

----...... ....
.-.
........

L..-.......,.
__ ......
~--

. . . CUT
CUM

--....-ILOO

'---

-...,

~~~

rFr~ I-,...~

.....
.....

..........."
.ALtO

10....

"_, I - - -

CUT •••,"

t--

""'aD

-- ......
....,

r-;;;;;-

....,CUT

......... I-

...T III£ADT

...,-

........-

ILDD-

Y1
,.

t--

'--~ I--

1...,--," .. __

Ir~t-~

...., .
<UN!

01_'
CUT_'

:.,
AI

~I~:~

-...,
...., ...T

..... -

...., ...r

ab'....
....--

,.;D-

IOAul
-iHi I-- ....

CUT_'

-E3J-Im'
.;;

..."

3-130 VAXstation 2000 and MicroVAX 2000 Technical Manual

Table 3-23: Serial Line Identification
Line

Device

Definition

Keyboard

Connected to an LK20'l keyboard through the video
monitor cable, Data leads onlv. On the MicroVAX :;WOO
this liM corresponds to
1 on the
converter which used for the

c(msoJe terminal.

PoInter

Connt"cted to a VSXXX-.AA moUSe or VSXXX-AB
tablet throug,h the video mo.n.ito! cable. Data

leads
line
verter
nE'ction.

Communicat1rfr>

On the Jl.liCTOVAX 200n system this
to port 2 on the DEC423 can·
is used for a second terminal (ont

Connected to a. 25-pin male D-shell connector 1m
use with an external modem on both systems,
modern cont.rol signals DTR. RTS 1\1,
CIS, DSRS, SPDMI, LLBK and TM!.

Prinle!

Connected to a 9-pin male D-shell connector for
a serial
Data leads only. This line .is. ;;l80
used to attach adiagnostk termInal to the
tem when using a special BCC08 cable. On
MicroVAX 2000

this line

1.0

port :5 on the.
converter which is used lor
connection of a printer or a thi.rd terminill,

3.7,3 Diagnostic Terminal Connection
Line 3. on the VAXstalion 2000 system is normaHy c:onnectt."d to a printer
a BeeO; cable. This line may instead be: connected to II terminal for field
has a
service diagnostics by using a'BCC08 ·:able. The BCC08
between pins 8 and 9 on the 9.pin cormecto£ end. of the cable. Bit
of the configuration and test
CFGIST
Section '3.11.:n is set til
1 when thls'jumper 1&
is 0 ,,,,hen the normal'
printer c~lble is used.
thIS junIper is present, a BREAK received on
line 3 asserts the
!lALT
\vhich causes a processor rest/HI ~vlth
rest;.u1 code 02h (see Se(H(}n'n~e ~1icroVAX 2000
canner
use this diagnostic terminal since
DEC4.23 inhihi.!.s the con.nection of the
BCCOB ('abie.

10 .... "'Oforn Module Detailed

3-131

3.7.4 Interrupts
The controller gem'Hltes two type!' of intermpt requests. each with a sepa,
rate Vt.-do. and tilt in the INT, REQ and INT.MSK registers, These are transmitter done, and either receiver done or sHo alan!'!. Section 3.5.9.4 lists the
vector values. In order for these interrupts io be signalled to the CPU, the
INT,MSK must be set
appropriate bits in the interrupt mask
Section

3.7.5 Register Summary
The serial line controller contains six addressable
the six addressable registers,

Table 3-24: Serial line Controller

Table 3-::'4 lists

ister Addresses

Name

Access

Descr~pl,ion

200A,OOOO

5ERCSR

Read/write

Control and status

200A.OOO4

SERRBUF

Read

Recein~r buffer (bottom (Ii

200A.OOO4

SERLPR

Write

Une

2ooA.0008

5ERTCR

Readiwrite

Transmitter control

200A,OOt1C

SERMSR

Read

Modern status

200;,\.000C

SERTDI~

Write

Transmitter data register

3.7.5.1 Control and Status Register (SER CSR)
The control and status register is a 16-bH
at <lddress 200AOOOO. This
reglster must be read on a word basis but can be vaitten to on either a word
or 'byte basis. All bits in SER_CSR are cleared to 0 by power-on or by setting
the master dear bit CLR. Figure 3-59 shows the seriai line control and status
register.

3-132

VAXstatiOn 2000 and MicroVAX 2000 Technical Manual

Figure 3-59: Serial Line Control and Status Register (SER_CSR)

nINE
7

IRDONEI

MSE

eLR IMAINTI

Data Bit

Definition

TROY

Transmitter ready (bit 15). This read-only bit is set by the hardware
when the transmitter scanner stops on a line whose transmitter buffer
is ready to be loaded with another character and whose related transmitter control register 5ER_TCR's bit TXEN_x is set. The TUNE bits
are only valid when the TROY bit is 1.
When TROY changes from 0 to 1, the interrupt request register (INT_
REQ Section 3.5.9.1) bit 5T is also set to 1. If the interrupt mask register (INT MSI<) bit 5T is also 1, then a transmitter interrupt request is
sent to the CPU. Otherwise TROY can be polled by the host program.
However, the interrupt request register's bit 5T is not automatically
cleared while interrupts are masked, so when changing from polled
to interrupt operation, there may be an interrupt request sent to the
CPU unless the 5T bit in INT_REQ is cleared by writing a 1 to the 5T
bit in INTSLR.
The TROY bit is deared when data is loaded into the transmitter for
the line number indicated in TUNE by writing to register 5ER_TOR. If
additional transmitter lines need service, TROY is set again within 1.4
microseconds of the completion of the transmitter data load operation.
The TROY bit is also cleared when the master scan enable bit M5E is
cleared, or when the related transmitter control register (5ER _TeR)
bit TXEN x is cleared.

Not used.

VS410 System Module Detailed Description

3-133

nataSH

Definition

S/\.

Silo alarm
13). This readbU. is set
tot:' hCHdwMi.:' \>"h(:n
16 characters have been enten:.:'l i.nto the FIFO silo b'lffer. t'v'hUe the
silo alarm enable bit SAE is L the tra:1sit.ion of SA frorn 0 1.0 1 sets
tntf.:rnlpt request n~gister IlNT
bit SR to 1, If
mask
bit 5R is a\s() 1, an
is sent to the CPU"
SA bit may be polled. However, the interrupt request register
bit SR is not automaUcaUy deared while that interrupt is masked, so
when changing from polled to interrupt operation, there may be <In
interrupt request to the CPU unless the .host program (.leal's SR
writing a 1 to the interrupt clear register (tNTSLR.) bit SR.
The 5A bit Is cleared by reading the refeiver buffer register SER.RBUF,
the host prog.ram reads chaIacters
vVhen responding. to a silo
from the silo until it is empty ~U!1!iJ DVAL in register SER RBUF is
since the silo aJarm bit is not set
untH 16 additional characH:fS
have been storl"d in the sUo,

o while the sUo alarm enable bit SAE is

The SA bit is

S,\E

Silo alarm enable (bit 12), This read,lwrite bit selects the source of the
receive interrupt request signal. If SAE is 1. the silo alarm. bit Sf, is
l.lsedas the signal. If SAE is O. the receiver dl1nc bit RDONE discussed
bei()w is used" instead .

11:10

Not used,

TUNE

Transmit!er line number (bits 9:8). These read-only bits indicate the
number of the line whose transmitter buffer needs
$ is
the least sig..'1.lficant bit). Thes.e bits are only valid while the transmitH:f
bit TRDY is 1.

11,('51" bits are cleared when the master-sca.n enable bit 1',,1SE is clea.red.
RDONE

Receiver done (bit

This

c]illracter appears at

bit is set

the hardwa.re v.'hen

of the silo buffer.

VVhile the silo alarm enable bit SAE is 0, the transition of RI.)ONE from

oto 1 sets interrupt request

ONT REQ) bit 5R to 1. if interrupt
mask register (lNT MSK\ bit
ii> also 1, an i.nterruptls signalled
to the CPU. Olhel:-wise the RDONE hH
be
However,
the: intern;pt request
bit
cleared while that interrupt is
so when changing fro.rn
to interrupt opf'rarion, there m.ay be an
CPU unless the
writing a 1 to the
hit SR.

3-134

VA.xstaHon 2000 and MicroV,t;.x 2000 Tecnnical Manua!

Data BlI

Definition

RDONE is deared when the receiver buffer registf~r SER .. RBUF is read.

1£ another Ch,ln1('ter is avaHilble in the silo, RDONE is set again after
a delay of between 0.1 and 1.0 microseconds. This bit is also cie<:u'€'d
when' the rna.ster scan enable bit MSE is cleared,
(;

Not used.

MSE

Master SGI11 enable {bil
Thill read/write bi! must be set tQ 1 to
permit the receiver and transmitter contwl sections to scan the Hnes
to see if they need servicing, Vv'hen this bit is 0, tn!" tramrmlttel' ready
bit TRDY is cleared and the receiver silo is cleared.

CLR

Master deaT (bit 4), When thi<; blt iF sel, the
an
internal initiaHza.tion process. At the conclusion of this
the
system clears t.his hit. IJ this bit is l. then the
process is
not. complete. TP,is inHializatloli clears all regis!t:rs., the silG, and an
Ul'>.RTs, but there are some exceptions as noted belo\lv,
in the receiver buffer reglstet (SER.R13UFJ, on.ly bit DVAL is cleared.
The remaining bits art' not affected,
Bits 15:6 of th~' transmitter control register (SER.TCR modem conlrol
outputS) are nol cleared,

Tne modem status register (SER.MSR) is not cleared.

NOTE: After setting flu master clear bit
a program mllst repeatedly read
_
eSf<. until it (inds eLR equal io 0 before attemptin8 allY other opemtWI15 zl;'ith the
seriallinc control/cr,
aNT REQ or INT AJSK) /.'l! C alfered lulre;;
Neitllt'f of tile il!terrupf con/rolkr
cmd aiso INT~REQ nmst lJe cleared to 0 by
eLI< IS sel BIts SR and ST of
10 complete the i1!itia!izafiol1

Is to tile HlnlC bits of

This readiwrite bil, wh('fl set
((Jnnectio!1s of the Iransmlt!efS to th", N"r1'''~n'''',1'

MAINT

Maint1:'na!'lce (bit

2:0

Not (.lsed.

\.1St'.

ModUle Detailed

3-135

3.7.5.2 Serial Line Receiver Buffer Register (SER.RBUF)

The receiver buffer register is a 16-bit read·only register at address 200A.0004.
It must be read as a word. It contains the received character at the bottom
of the silo buffer (the oldest character in the silo). Reading this register removes the character from the silo buffer, and all the other characters in the
silo are shifted down to the lowest unoccupied location. When this register is read (or when the master clear bit CLR in SER CSR is set or after a
power-on reset), the data valid bit OVAL in SER RBUF is cleared and the
remaining bits of the register (although not cleared) are invalid. Figure 3-60
shows the serial line receiver buffer register.
Figure 3-60:

Serial Line Receiver Buffer Register (SER_RBUF)

NOT USED

!DVAL

RLINE

ReHAR

Data Bit

Definition

OVAL

Data valid (bit 15). This bit, when 1, indicates that the data in bits 14:0
of the register are valid. This permits an interrupt handling program
to read the receiver buffer register repeatedly and store each character
until this bit is read as 0, which indicates that the silo is empty.

OERR

Overrun error (bit 14). This bit is 1 when a received character is
overwritten in a UART buffer by a following character before the first
character was transferred to the silo. This condition indicates that
the program is not emptying the silo fast enough.

FERR

Framing error (bit 13). This bit is 1 if the received character did not
have a stop bit present at the correct time. The combination of FERR
set and RCHAR entirely 0 is usually interpreted as indicating that a
BREAK has been received. The receipt of a framing error on line 3
(the printer port) is a special case. If the hardware detects a framing
error on line 3 and the accompanying character contains all Os (i.e. a
BREAK has been received), the line controller hardware asserts a signal whose effect is described under Section 3.7.3 Diagnostic Terminal
Connection.

PERR

Parity error (bit 12). This bit is 1 if the sense of the parity of the
accompanying character does not agree with the parity which was
defined for the line when its line parameter register SER.LPR was last
loaded.

11:10

Not used.

3-136 VAXstatlon 2000 and MicroVAX 2000 Technical Manual

Data Bit

Definition

RUNE

Rect'Iver Hra' number (bits 9:8). These bits indicate the number ef the
Une fnlm ,,,hich the character wa" received (bit 8 is the leas!
bit).
.

ReBAR

Received character (bits 7:0). Characters with a width of fe,vet that'
8 bits (as defined \,vhen the lines line parameter: register was IMi
loaded) are right justifitd v.'Hh the unused bH
deared. The
parity bH is not included in the receiv{~d

3.7.5.3 Serial line Parameter Regisfer (SER _LPR)
The line parameter register is it 16·bit register at address 200:\ .0004 th"t
controls the operating parameters of each line. This register is
and must be written as a 16·blt word. The parameters for each line rnusr
be reloaded after each povv'er-on reset or setting of the master dear bit
in SER
The operating parameters should not be modjfied for a line
transmissklll or reception is in progress on that line. Figure 3-61
while
shows the serial line parameter registe.r.
Figure 3-61:

Serial Line Parameter Regfster (SER.LPA)

VS410 System Module Detailed DescripHon

3-137

Data Bits

Definition

ODDPAR

Odd parity (bit 7). If this bit is set and the
enable hit PARENt)
in SER~LPR is also set, Ihen characters wilh (Jdd parity Ilt€' transmHted
to the line and cha.l'acters received from the Hne are expected to have
odd panty. If this bit is dear and the parity enable bit PARP"';B In
SER.LPR is set, then characters with evtn parHy an~ transmitted to
the line and characters: received from the line are expected to have
even parity. If the parity enable bit PARENS in SER)YRis dear,
then the setting of this bit is immaterial,

PARENB

Parit\' enable (bH 6). It this bit is set characters transmitted to the
line have a parity bit appended and characters received from the Uri!;'
have their parity ('he(k~LThe sense of the~ parity is
to the
setting of the odd parity bit ODOPAR in SER.LPR,

STOP

Stop cod.e (bit
If thi.s bit is dear, the slop code following the last
IransmjH(~d bh is 1 bit tinw long. if thi.s bit is set., in/."
code Il'lFts
1.5 bit times for characters whose width is 5 bits, and 2
times !el'
characters whose width is 6; 7 or 8 bits.

CHARYv'

Cnaractet width (bits 4:3L These bits control the number of data bits
(exclusive of any parity bH} in the characters transmitted end expected
in the characters received, The encoding is b;:low.

----.---~---.~

Chllla<:ter Width {BitS!

-------_.-----------o

s
2

Not used,

PUNE

Parameter liTH;' number (hilS 1
These bits
t.he line to \Nhkh the n;"''''n'''!''''''~ in the rest of
(} is the least

3.1.5.4 Serial Une Transmitter Control Register (SER}CR}
The tran.!:lmittcr nmtrol

at address

that

must be read on a
can
vlri.th'n on elther a ~,;ord or
basis. Figure
shm.vs tlHc serial line transmith:.~r control

V8410 System Module

DescrlpHon

3-139

Figure 3-62:

Serial Line Transmitter Control Reglsler (SeR.TCR)

[

NO! USED
7

Definition

15:12

Not tlsed,

LLBK 2

LLSlCzl D:T1L2

IDSRs_2jRTs_2
1

TXEI(.2/ TXE~C 1

NOT USED

Dala Bits

This teadiwrite bit conlrols thl" state c,f the
(CCITT circuit 141) for line ::
hit asserts the ON stat" \':If the LLBK signaL This bit is
a
reset; it is NOT dearedwhen the master clear
is set,

JDC'!:'tl,~CK m;)dem control

This fea.diwri!e bi.t (ontro!.s tht' :;;ate of
moden1 control
{CeITT drctli!
asserts th(' ON state of the DTR
Thi~,
reset; it Is ~,jOT cieared t'ihen
CSR 1$ sel.

Dm2

Data

stete

This reath"rHe bit wntr()ls the
rate sel!;>rtor uwdem, contro.l
trw bit assert, the ON state

rate selector (bit

the data

circuit 111) for line

rV',h'"Y"r,,,

reSf't: it is NOT cleared when

is set.
"2

7:4

10 send (bit S;}. This readiwrite bit controls the state of lh.!."
request to st~nd modem control
on."uIt
tOt lin.!." ;:;,
"
the bit asserts the ON stat':'~ Dr the RTS
Tni!'. bit ls
by a power-on reset; it is NOT cleared when
milster dear
bit CLR in SER CSR is set.

Not used,

3-140 VAXstation 2000 and MlcroVAX

Data Bits

Definition

TXENx

Transmitter line enable (bits 3:0). These read/write bits enable the
transmitter logic for lines 3, 2, 1, and 0, respectively. Setting each
of these bits causes the transmitter scanner to stop and assert the
transmitter ready bit TRDY in SER CSR if the UART for that line
has a transmitter buffer empty con&Uon. The transmitter scanner
resumes scanning when either the transmitter data register for the
line at which the scanner stopped is loaded with another character,
or when that line's transmitter line enable bit is deared.
A transmitter line enable bit should only be cleared while the scanner
is not running (i.e. when the transmitter ready bit TRDY in SER.
CSR is set or the master scan enable bit MSE in SER CSR is clear).
The transmitter line enable bits are cleared by a power-on reset and
whenever the master clear bit CLR in SER.CSR is set.

3.7.5.5 Modem Status Register (SER.MSR)
The modem status register is a 16-bit read-only register at address 200A. oooe
which contains the status of modem input signals for line 2. The ON condition of a modem signal is presented as the set state of the corresponding
bit. Figure 3-63 shows the serial1ine modem status register.
Figure 3-63:

Serial Line Modem Status Register (SER.MSR)

321

VS410 System Module Detailed Description

3-141

Data Bits

Definition

15:12

Not used; read values undefined.

SPDI2

Speed mode indicate (bit 11). This bit reflects the state of the speed
mode indicate signal from an external modem (CClTT drcuit 112) on
line 2. The set state corresponds to the ON state of the signal.

CD2

Carrier detect (bit 10). This bit reflects the state of the carrier detect
signal from an external modem (CClTT drOOt 109) on line 2. The set
state corresponds to the ON state of the signal.

DSR2

Data set ready (bit 9). This bit reflects the state of the data set ready
signal from an external modem (CClTT drcuit 107) on line 2. The set
state corresponds to the ON state of the signal.

CTS)

Clear to send (bit 8). This bit reflects the state of the clear to send
signal from an external modem (CClTT drOOt 106) on line 2. The set
state corresponds to the ON state of the signal.

7:4

Not used; read values undefined.

Reserved, reads as O.

RI2

Ring indicator (bit 2). This bit reflects the state of the ring indicator
signal from an external modem (CClTT drcuit 125) on line 2. The set
state corresponds to the ON state of the signal.

Reserved, reads as O.

TMl2

Test mode indicate (bit 0). This bit reflects tne state of the test mode
indicate signal from an external modem (CCITT drcuit 142) on line
2. The set state corresponds to the ON state of the signal.

3.7.5.6 Transmitter Data Register (SER}DR)
The transmitter data register is a 16-bit write-only register at address 200A.OOOc.
It can be written on either a word or byte basis. Figure 3-64 shows the serial
line transmitter data register.
Figure 3-64:
16

3-142

Serial Line Transmitter Data Register (SER_TDR)
11

VAXstation 2000 and MicroVAX 2000 Technical Manual

Data Bits

Dtfi.nttlon

15:12

Not u~;ed.

BRK>:.

B:rea~ control (bits 11:81. These
bits control the asst"rtiN\ of
a BREAK condition on lines 3, 2, 1, and fe'spectlvely, Setting a bli
immediatdy forces the transmitter output for the corresponrung line
to the SPACE condition. This condition wiU persi.st until the break
control bil is cleared, These bits are dee red
a power-on reset and
when the m.asler dear bit eLF. in SER C5R is set.

TXDATA

TransmItter buflerlJ'its 7;0). Data to be transrnitleti
a Ene's Ul·.HI'
iii loaded into these B bits, if the character width is
than 8, the
imused bH5 are at the high-orde.r (bit 7) end of the byte This r.,,,~<:!.~r
rna,' be wrl.Hen to onlv while the transl'l1iUer· ready bil TRDY in
CSt<:. is s('L The line which the charactt:'f 1$ sent'i.s Indktlted

transmitter line nurnher bits TUNE in SEl< CSR,

3.8 9224 Disk Controller
This section describes the 9224 disk controller

3-65).

The di~k controller supports both diskette drives (RX33) and ST506i412 hard
disk drives (RD32 and RD53). The maximum configuration of the controller
is one diskette drive and nvc hard disk drives, The controller is an
9224 universal disk controller chip which uses 8. phase·h1 cked loop data
:recovery circuit, an address counter, and a 16 Kbyte dual pori data buffer.
Figure 3-66 shows the pinout of the 9224 disk controller chip and Table 3-2.5
lists the signals for each pin on the 9224 disk controller chlp.

VS410 System Module Dela.iled DescrlpOon

3-14:3

Figure 3-65:

9224 Disk Controller

3-144 VAXstation 2000 and MicroVAX 2000 Technical Manual

Figure 3-66: 9224 Disk Controller Chip Pinout

:0'; ,::; /~-::'05
l~lZ/;~)04
lS'~"i/;C,j)

l[\OS /1 Ci;·:)'
lD(;~;/lJrJ:\

VS410 ....v'"'' .,'en Module DetaHed Description

3-,145

Table 3-25! 9224 Disk Controller Pin
Pin.

Signal

21 "1i

DlH 0
DB7S

,25:23

Thf'Se

ilre the

dilL, bU5 hor th+" (i\,k ((Intra!!e,
to th~, low h;!l,,' for th,."in.

bus

th!oUj.;h an

bit

transC'€iver to
internal
bus
{lDU815),
Tills b'J.5 tr?ll1sfers diU" to and frorn the
disk d"t.a buffer and il150 to ilnd [rom the CPU BDAt bus
lh~,

These signals are
troller.
maHon en the
tu~ in/ormatlon

(59224

hIS

for Ihe disk conthat cont<1tn I nfors\;;!' and drive sta-

is the disk ('OTltrolk('\

Thls
dard

~.s the 10\1\' i-:"tt (If thf~ ;(.ltch€d addn:<:~~ btJ5; frurn th~ Vt)t\L

Thi:)

bu~

1J~pd

C'PU

(\f'id

d}~',k

c~>n~

low inairate-8: ~:\at df.\A
be writlen to or rea.d frem thJ;! 1,':t1nt-o\lers. InterIl?gisters and il
i1",dicales lililt the CPU om writ,!
rornrnctnc rf'SlJH5 fronl the ~:on ..
t:ornrnands to or
t,roiler
trofh::f

BRESET

cornnnlnl(i:'ltion

wlH:re

;:t

is th(, f{,S('(
resets thE d~(k
dovin the entire s,,'>tem,
TIliR
n~l

eLKS

}I)

CLKlU

ReLK

Tr,,},s

In~,~1f1z

.fS

th€

:r~'2d

~"".,dn~.~~JV"

i:; tht

Thi31
card
,:t~(ts

as.

disk controlk-r fit)(K horn the' st.Bn ..

dock -stroh€' frofl'l,
t(l

if~<jj,2E;~€

rav,. '

th~

s~'?'r·.dfHd

data ceil

Ct,fj.

b{)t'nd~

Mit's un t.he RDDATA tin~

RDDATA
;' r\lV
t1.t'lta fn:}!r'I thE di~jk
locked lOOp rec(;t\'ery rir (',..Jit

,059224

This
It is
bv th~ dLSk (-onhc':.!u~ ('Ji
dI('atf.: Ir'\,:ht'n' val]'{! d;~ta T;:\ h\'itOathi'2

the :::;~'~"ndard c~:H ~o ind·at?., 'b~lS rDB/'f)) dJ.a~

jng a tranMer 10 m 1101'1'1 til!? dl,sk dat;, uL:H"r

n"ds-

1~ th?
it)'5 u5e-d

readi \vrHe
h:H' t.h(J dis.k (onhy U;,~; ,;jj3~: contf('rHer or b'v l:ht: st(1nd~ir'~~ o:~U to iJ1(Hc{~te if the dtsk d.a:ta bufi-€! ir2tf"\sff.'r cy"'
dE' is il. read N wrilt'
troHE~r.

3-146

VAXstatton

and MlCroVAX 2000 Technical Manual

!~!. 3-2~.JCont.t_ 922~~~~k C..?ntrol~=r Pin O_es.criEti~_~__""
Pin
Signal
Ddcril'tkm

RDXiRQ

This signal is the :Interrupt req\.lest signel Ihal is sen\ to tne
standard cell's interrupt controller when the disk controller
needs service.

RDxm.iR

This sign~.1 is the DMA request line. It is wrapped around
and input directly to the OMA acknowledge tine.

RDXDMR

This sj~nal Is the DM!'" aCKnowledge lint'. It is frc,m I.he
DMA request line on pin 28 of the dis~. controller.

ECCT1M

This Signal is used with the [159224 and DIP signals to in·
crement tht~ address counters.

DIP

Thl~ signal is the DMA is progress flag.

SELl
SEW

These lint's select one of the four rontwl line;:, that enab\(:
regis,ters em the Ai:l'7:D bus, 1'ht's~ select lines are de{'od~~,j
by a 2·4 decode.r that is enabled by the 51'S signaL

STH

This
aUovls

It is active whenever
the dis.\<: controller 16 pe!:fcurting a Dl\1A operati()n.

is the strobe signal which enables a decoder that
selt'ction OJ control lines \0 the registers on the

AB7;O bus.

RDGATE

is ihe read gate strobe. Ii is used to stMt the
It switdH':s the vo!ta~e-(ontwlled oscillator
fn'ln-t
onto the natural dock -frequencies t(; locking:
onlo the r3,,\' da.ta off the disk.

WDATA

Thi~ signal is the data to be ''''riHen to the disk,

LATE

EARLY

These signals att' the select lines fot a write precompensBtion delay l.ine multiplexer. The delay liM is not used for
the RX33 RD32, or the RD53 drives,
i

27
22

VlRGATE

This signal is the write enable signal to the drives.

vee

This is the +5 Vdc power connection to the disJ: ccntroHt l.

\ISS

This is tn,,' ground conneclinn t() the d,ld: o::mlroHli:,t

3.8.1 Disk Oata Buffer
is <l 16K bvt(' block of RAtvi
the tapt: controller. a.nd the
stntic RAM
and is nol incluc!i:d as par! of
R/\1\'1. H is :J{'c€:'ssibl·f' to the
in all read.
and it

VS410 System Module

3-147

The disk controller chip accesses this buffer using its built-in 24·bit DMA
hardware when transferring data to and from a disk. To the tape controller,
which generates a 24-bit OMA address, the data buffer is a byte-addressed
block with an address range of OOOOOOh through 003FFFh. The disk and
tape controller access the data buffer through the address counters and the
CPU accesses the data buffer through the ELA09:2 bus and the MEMAD3:0
bus. The disk data buffer is accessed by the CPU chip through the tri·state
transceivers between the BOAL bus and the IOAL bus. Only one controller
can access the disk data buffer at one time. The device driver software
must ensure that only one device at a time attempts to access the buffer.
Figure 3-67 shows the circuit diagram of the data buffer.
When the CPU is performing a write to the data buffer, the low 16 bits of
data go directly to the buffer on the internal data bus (1015:00) during the
first half of the cycle and the high 16 bits are latched inside the standard
cell. During the second half of the cycle, the latched high word is put on
the 1015:00 bus to the buffer.
When the CPU is performing a read to the data buffer, the high 16 bits from
the data buffer are addressed first and they are latched in the standard cell
during the first half of the cycle. During the second half of the cycle, the
low 16 bits from the data buffer are output onto the low byte of the data bus
and the latch high bits are put on the high byte bus of the data bus at the
same time to form the full 32-bit wide data bus.

3.8.2 Disk Address Counters
The address counters hold the data buffer address from the disk controller
during normal RAM cycles as well as during OMA cycles. The disk
controller uses a 24-bit OMA address and the system only uses a 16·bit
address so the high byte is not used. The dropping of the high byte is
done by emitting the high address byte onto the AB7:0 bus which is loaded
into the first address counter. The middle address byte is then put on
the AB7:0 bus next and is also loaded into the first address counter which
pushes the high byte that was originally in the first counter into the second
address counter. Finally, the low address byte is put on the AB7:0 bus and
is loaded into the first address counter which pushes the middle byte into
the second address counter. Since the system only uses a 16·bit address, a
third address counter is not available and the high address byte is lost.

3-148 VAXstation 2000 and MicroVAX 2000 Technical Manual

Figure 3-67:

Disk Data Buffer Circuit Diagram

D1
De

1n5

D5
04

1013

In'
C)l2

03
02

In'
C)lO

1--- .......

GOt
GOt

I--- "ALOII

':;:";;

-...
.'2
All

I-- ..AL15
I-- "AL"
I-- ..AL13
I--- "AL'2
I--- "AL"
I--- .....'0

IlI!tC11O<
rH.a.E

Al0

)

AOII

"",

A05
.".

"A01"2

"""

WI:
010

CS2
CSl

....
07
De

MlAL07
....06

O!I
04

.....04

8IlAL05
"AL03

03
02

"AL02

"1.1.01

"ALOO

-...... _.
"2
An

.'0

"",

--...

ICSlCS

.".

" "2

lit
rHO
CS2

CSl

....

VS410 System Module Detailed Description 3-149

)

This leaves the low and middle address bytes in the address counte.fS, The
address counters then put
16-bit address onto the CNTlS:OO bus, The
;l,ddress is then sent through <\, multiplexer to the data buffer, The multi,
plexer channels the diskltape addreBs to the datil buffer (II' it channels the
CPU address to the data buffer when the CPU is accessing the data. buffet.
The disk wntroHer sets up the multiplexer, control registers, and
byte drop automatically at the start of a read!,..,rrite operation.

3.8.3 Phase-Locked Loop
The phase-locked loop consists (If a phase comparator and a voltage-controlled
oscillator (VCO) as shown in Figure 3·-68, The phase ccmpara.tor is inside
the standard cell. The
is a dual oscillator chip for both hard disk and
floppy diskette data frequencies. The phase lock loop is used to control
th.e frequency of the raw read data from the disks, The individual
frequency modulation (MFM) pulses that are read from the
sensitive to speed variations and the vaiue of the
(1 or m
if the
the data stream IS not pred'le.
\leO tlUOWS tracking
to the phase com·
of
variatlOn of the data stream ''Ind H~nds
parator to compensate the variation so the lOop recovers
data and sends
the disk controUer a
and reHable data stream,
Figure 3-68:

?hase~Locked Loop Block Diagram

1 " " 1- - - - - - . ; - - .

r--

\,'co,',:; -~.-~---------'""""'

REA:::' DA;-;" ____ p~,e.',?£. " ...., .

PEr

l"J,EQ:;nIC:ES _

R::lOA ,;,

3-150

",M?ARA ,,)1'1

lC:===:4_

VAXstatlon 2000 and MicroVAX 2000

Manua!

When the phase-locked loop is running but not reading from the disk, we
lock it to a reference frequency generated within the standard cell. This
reference frequency prevents the loop from drifting off to a very high or
very low frequency when not reading data. If it did drift off then there
would be a long delay time to get the loop back to the proper frequency
before the system could read data from the disks. The reference frequency
for the hard disks is 10 megahertz. The reference frequency for the floppy
diskettes is 500 kilohertz when RX50 media is selected or 1 megahertz when
RX33 media is selected.
When the phase-locked loop is reading data from the disks, the reference
frequency for hard disks is 20 megahertz and for the floppy diskette is 2
megahertz. The veo is a dual oscilator but only produces one frequency
at a time. That is, either the hard disk reference frequency or the floppy
diskette reference frequency.
3.8.3.1 Phaae Comparator
The phase comparator is internal to the standard cell. It has two 4-position
multiplexers as its input and the output is the pump-up and pump-down
signals to the veo. Both input multiplexers have a 10 megahertz, 1 megahertz, and a 500 kilohertz reference frequency and one multiplexer has the
output of the veo as the fourth input and the other has the raw data from
the disks as the fourth input. These multiplexers are controlled by the read
gate (RDGATE) signal. When RDGATE is not asserted, the reference frequencies are allowed through the multiplexers to the comparator. When
the disk controller starts a disk read operation, it asserts RDGATE which
allows the output of the veo and the raw read data from the disk to pass
through to the comparator. The comparator consists cif two edge catcher
flip-flops whose clock input is the output of the multiplexers. The output of
the flip-flops are the pump-up and pump-down signals that go to the veo.
As soon as the edge of the either input signal is received in the flip-flop,
it is output to the veo. A reset signal automatically resets the flip-flops to
there original state before a second edge is received. These pump-up and
pump-down signals should be identical. If they are identical, then the veo
does not change its output frequency. If the two pump signals are not identical, then the veo increases or decreases frequency its output frequency
to compensate for the difference.

VS410 System Module Detailed Description 3-151

3.8.3.2 Voltage-Controlled Oscillator (VCO,
The v<)ltage-controHe(.~ oscillator is a 74LS626 duall~scm"tor, The veo chip
uses a level shIfter CIrcmt and an active filter circuit to provide accurate
input !lignals,
~C() front end circuits Input and
the pumpan? pump·dm\·n 1:Hgn<11s, They measure the amount
pulse width in
e~::h s!g~al, sum them tog,ether, and send a phase-error signal voltage to the
\leo Chlp to Shlft up ?r shIft dOlNn the reference :enter frequency d~pending
on the phase error !:llgnaf: The output of the \'CO chip is looped bad, to
the
(Ompiuator in1;nde the standard cell.
The veo chip has hvo output signals, one signal for the hard disk
locked loop data recovery circuit and the other for the floppy disketle phaselocked loop data recovery circuit. Only one of these output signals can be
active at the same time, The output frequencies are determined by the
value of a capacitor connected to the C:Xl and
input l.in€s for each out,
put signal. The enable for hard disk half of the VCO chip is the 5ElECTRX
H signal and the floppy diskette half IS the inverl of the SELECTRX H
(SELECTRX L) so that only one of t.he outputs is enabled at one time,
'leO circuit is p(nvered by a special + 5 Vdc that is divided down frorn the
+ 12 Vdc supply, The veo dn::uit uses this ·t 5 Vdc
the reference voltages needed in the analog level shifter drcuH~ and the analog active filter
drcuits, The level shifter is controlled
RDGATE signal \vhich Indicates whether the phase,locked loop is locked on the reference frequencies
or is locked on the raw read data, The + 5 Vde reference
is further
divi ded to produce another reference (+ 3 Vde voltageJ sUFply
the VCO
circuit Figure 3-69 shows the block diagram of the veo circuit
Figure 3-69:

3-152

veo Block Diagram

VAXstation 2000 and MicroVAX

Technical Manual

3,8.4 Hard Disk Data Bus
The hard disk data bus contains the disk control signals such as the head
select, drive selec', and head positioning information as weU i>!' the raw dati)
read and writ", signals. The diSK controHer uses the
bus (AB7:0)
to transfer the controi data to and from the disk. Raw data w1it!en to the
disk. is output on the disk controller's WDATA pin. i<aw data read from the
dis~: is processed through the phase·locked
and then is presented to
the disk controller on the RDAT A pin, The
supports two hard 1.11:::1<
drives, Both drives share the write data
but each has a separate reA'd
data path, The shared write data signal is sem to the drive that is selected
the drive select signal.

3.8,5 Floppy Disk Data Bus
The floppy diskette
bus (\')ntains the floppy drive
as the head select, head positioning informalic1n, a.nd the high
Signal whi.ch indicates whether the media is RX50 or RX33 media
disk
controiler uses the auxHiarv bus (AB7:0) to transfer the control data to and
from thE' floppy drive. Rav~' data \vritten hJ the floppy drive is output on the
disk controller's WDATA pin, Raw data read from the disk is
through the phase-locked kJC\p and then is presented to the disk controller
on the RDATA
The system s<upports
one floppy diskette drive
and that drive must be located in the
box.

3.S.6 Controller Chip Organization
9224 controller chip has
internal registers \vhich control its
and re\'eai its statusi, These are
accessible to the
way of three ports that art: mapped into thE' proc€ssm's address
help prevent confusion, the three ports that a progr<lm (8.11 access directly
are named vvith the prefix DKC_, and the controller
(,'\'hich a.re
only via the ports) are named 'with the prefix
V"""""

The controller chip na? an internal
pointer \'tlhkh
!he
register 'which is
to the
the register d.:lla acc'ess
This
p,;lnter can be set €!l:pIidtly by a
POrNTEl.~ command wnth.:'H
to lhe controller command porL It is implicitly incwm.ented by i1,';::es!'«'s. to
the
data aCcess port until H reaches the
(the
registe~), after vllhkh the poin/et villue continu"2'S to
to
until another
REGISTE.H
comrna.nd is issued.

3-153

3.8.6.1 Disk Controller Chip Ports

Program access to the controller chip is via three 8-bit ports, each of which
appears as the low·order byte of a longword address. Note that the command and status ports have the same address: one port is write-only and
the other is read-only. Table 3-26 lists the address and access of the disk
controller chip ports.

Table 3-26: Disk Controller Chip Ports
Address

Access

Name

200C.OOOO

Read/write

DKC.REG register data access

200C.OOO4

Write only

DKC CMD controller command

200C.OOO4

Read only

DKC.STAT interrupt status

NOTE: Consecutive accesses to controller chip ports must be separated by at least
0.7 microseconds, regardless of whether the accesses are reads or writes and of
whether the same or different ports are designated.

A program must not attempt to read or write any of the disk controller chip ports
(nor any of the tape controller chip ports) while the controller is executing any data
transfer command (e.g. any of the READ, WRITE, or FORMAT commands). This
limitation is because the data path to the ports is also used by the controller to access
the disk data buffer.
3.8.6.1.1 Disk Register Data Access Port

The register data access port is an S-bit read/write port accessible to the
CPU at physical address 200C.OOOO. This port provides CPU access to the
controller register designated by the controller's internal register pointer.
These registers are described below. Figure 3-70 shows the disk register
data access port.
NOTE: Some registers are read/write and others are read-only or write-ollly. In the
latter two cases, a given value in tile register pointer designates different registers
depending upon whether the access to DKC.REG is a read or a write. In either case,
each read or write access to DKC.REG advances the internal register pointer after
the access is complete (until the pointer reaches the highest register number, OA1.,
after which it remains at that value). Therefore, CPU instructions which perform
more than one access (such as BISB2 and BICB2) may not be used.

3-154 VAXstation 2000 and MicroVAX 2000 Technical Manual

Figure 3-70: Disk Register Data Access Port
7

CONTROLLER RlGISTII DATA

3.8.6.1.2 Disk Controller Command Port (DKC.CMD)
The controller command port is an 8-bit write·only port accessible to the
CPU at physical address 200C.0004. The CPU instructs the disk controller
to perform some action by writing a command byte to this port. Figure 3-71
shows the disk controller command port.
Figure 3-71: Disk Controller Command Port (DKC_CMD)
7

CONTROLLER COMMAND

3.8.6.1.3 Interrupt Status Port (DKC.STAT)
The interrupt status port is an 8-bit read-only port accessible to the CPU
at physical address 200C.0004. Figure 3-72 shows the disk interrupt status
port.
Figure 3-72: Interrupt Status Port (DKC.STAT)
7

TERMeOD

VS410 System Module Detailed Description

3-155

Dala Bit

Definition

INTFEND

Inlerrupt pending (bit 7). This bH reheC!3 O''.e state of the hardh:'!:e
;ntertupt signal S€l\t hom the centroiler
10 the
controller. The transition of Ihis bit from 0
req1.!est in the interrupt conlroUer. The
bH is set to
either of two cases; (1) whe:'n the DONE bit uf Ihi" pori is set v;h*'
the INTDONE bi.t of the
fERM
is a 1 OR m when the
RDVCHNG bit of this port i~
while
INTRDCH bit of the
TERM
is a L
The INTPEND bit is cleared to () afler (lny processor read of the D1<C"
ST.I\T port.fhis also returns the nmtroHer chip's int!:'frupl
to
its inactive slate SO that the next
of the INTPEND bit generates
anolher interrupt

DI.,lA
i.tit 6). This bit is s~~t to1 whenever the controller
requires a data transfer either to or from.its data regisler UDC
This bit is cleared by such a data transfer.

DONE

Command done (hi!
This bit is sN to 1 wh!:'n a command is complete. It IS cleared to 0 (after a delay of 16 times the dahl bit transfer
time) when a new command is issued, Note thal the length of the
delay depends lJpOn the drive type and datI,! rate options currently
effective in the controller. The maximum time is 64 m!crosec;:;nd",
which occurs when the controHe·f Is set up for a diskette drive with a
data rate of 250 KHz (the skn'.€C't device.!.

TERMeOD

Termination code (bits 4:3), Th~si? bits indi.cate the conditions under
which the most reo:nt command tt'rmi.naled.
are valid
while the DONE bit of lhis
.is set

3-156

Bit 4

Bit 3

Condition

o
o

o
1

Error in READ lD seql.l~nce

Error in VERIFY sequence

errOl' in DATt~ TRANSFER sequer.::e

VAXstalion 2000 and MlcroV,t!X 2000 Technicai Manual

Data Bit

Definition

NOTE: The following circumstances also result in a TERMCOD
value of 11: the READY bit in the UDCDSTAT register is 0 at the
completion of a DRIVE SELECT command, and the READY bit in the
UDCDSTAT register is 1 at the completion of a DESELECT DRIVE
command.
RDYCHNG

Ready change (bit 2). This bit is set to 1 whenever the READY bit of
the drive status register UDC_DSTAT changes state, either from 0 to
lor vice versa. The RDYCHNG bit is deared to 0 after any processor
read of the DI<C_STAT port.

NOTE: When a DRIVE SELECT or DESELECT DRIVE command is
issued, or when the state of the INVRDY bit in register UDC_RTCNT
is changed, the controller may detect a change in its ready input and
set the RDYCHNG bit.

)

OVRUN

Ovemm/underrun (bit 1). This bit is set to 1 during a read or write
command when the controUer chip does not receive an acknowledgement of its DMA request in time to prevent Joss of incoming data or a
break in outgoing data. This bit is deared to 0 by a RESET command
to the controller or by a power-on.

BADSECT

Bad sector (bit 0). This bit is set to 1 when a bad sector <as indicated
by the most significant bit of the head ID byte in the sector's ID field)
is encountered. This bit is deared when a new command is issued or
a good sector is read.

NOTE: As noted earlier, when tlte processor reads the DI<C_STAT portl the port's
lNTPEND bit is cleared. If a device driver program sets up the disk controller to
generate an interrupt request when DONE or RDYCHNG is set, then the program
must not poll the DKC_STAT port while awaiting the interrupt. 11 the port is polled
very close to the time that the DONE or RDYCHNG condition occurs, the can frailer
chip may fail to signal the interrupt. Also, when a data transfer command (e.g. any
of the READ, WRITE or FORMAT commands) has been issued to the con trailer, a
program must not attempt to poll the DKCSTAT port while awaiting completioll 01
the command, since the controller's path to the disk data buffer is also used by the
CPU when it reads the chip controller ports. A program which wishes to use tlte
controller in polled rather than interrupt mode should read bit DC in the INT_REQ
register to monitor the state of the INTPEND bit of ti,e DI<C_STA T register.

VS410 System Module Detailed DescriptIon 3-157

3.8.6.2 Controller Chip Registers

The controller chip contains fifteen 8-bit registers whose contents are accessible to the CPU via the controller chip ports, as described above. Ta·
ble 3-27 shows the address of each register by a number in the range O.. A
hex.

Table 3-27: Disk Controller Register Numbers
Number Access

Name
UOCpMA7 OMA address bits 7:0

r/w
r/w
r/w

rlw

UOC OSECT Desired sector

UOC DHEAD Desired head

UDCSHEAD Current head

UDCPCVL Desired cylinder

UDC.CCYL Current cylinder

UDC SCNT Sector count

rol

(temporary storage)

UOC_RTCNT Retry count

rol

(temporary storage)

UOC.MODE Operating mode

UOCSSTAT Chip status

UDC.TERM Termination conditions

UOC_DSTAT Drive status

rlw

UDCPATA Data

0
1

UOCpMA15 OMA address bits 15:8
UOC 0MA23 OMA address bits 23:16

3.8.6.2.1 DMA Address Registers (UOC.DMAxx)

The three 8·bit read/write OMA address registers form a 24·bit number
which is used to address the disk data buffer during the data transfer portion of read and write commands. Since the buffer size is 16K bytes, only
bits 13:0 of the OMA address are significant; bits 23:14 have no effect and
should always be O. Figure 3-73 shows the OMA address registers.

3-158 VAXstation 2000 and MicroVAX 2000 Technical Manual

Figure 3-73:

DMA Address Registers (UDC.DMAxx)

UDC_DMA23

DNA ADDRESS BITS 23: 16

(R/V REGISTER 2)

DISK BUFFER ADDRESS BITS 13:8

UDC_DNA15

(R/'" REGISTER 1)

DNA ADDRESS BITS 15: 8

DISK BUFPER ADDRESS BITS 7:0

UDC_DMA7

DNA ADDRESS BITS 7:0

(R/'" REGISTER 0)

During multiple-sector readlwrite operations (except during the READ TRACK
command), the DMA address contained in the UDC.DMAxx registers is incremented by the size of the sector after each successful read or write of a
sector.

3.8.6.2.2 Desired Sector Register (UDC.DSECT)
The desired sector register (readlwrite register 3) is loaded with the starting sector number for each multiple-sector read/write operation (see Figure 3-74).
Figure 3-74:

Desired Sector Register (UDC.DSECT)
6

SECTOR NUMBER

VS410 System Module Detailed Description 3-159

fe! the last sector of tilt,
this
each sector is successfully read or written. If
command because of an 'error in a sector, this
the number of the bad sector.

is incremented after
cC'ntroll er terminates a
contains

The range of valid sector numbers depends upon the drive type and the
format of the medium in it. The nominal
are 0 .. 16 for a hMd
1..10 for an RX50K diskette, and L15 for an
diskette.
the
controller accepts any value in the

3.8,6.2.3 Desired Head Reg!ster (UDC.DHEAD)
The desired head register (-'!,'.'rHe-only register 4) is loaded with the head
number and the high-order bits of the cylinder number for the nexl. command
Figure 3·-75).
Figure 3-75:

Desired Head Register (UDe OHEAD)
6

]
3.8,6,2.4 Desired Cylinder Register (UDC_DCYL)
The desired cylinder
(write-only re~!isrer 5; is loaded with the IOworder bits of the cylinder number for the ne~t command
Figure 3-76:

DeSired Cylinder Register (UDC _DCVL)
5

CYLINDER BITS 7: 0

The UDC
and UDC DH.EAD
sp€'dtv the cylinder ml.moer
and head -number at whjd, the next command is
begin The range
valid values depends upon the selected drive.

CAUTION: Be sure Itot to load a
munbe r
cyll1uters Itt the selected drive, /tffempfing to exceed

than the number of
existing tIIrmbet !Jj

the drive,

3-160

V,A.xstation 2000 and MlcroVAX 2000 Technical Manuai

3.8.6.2.5 Current Head Register (UDC.CHEAD)

The current head register (read-only register 4) is loaded with the second
byte of an ID field when a valid 10 field sync mark is found during execution
of a READ ID command sequence (see Figure 3-77).
Figure 3-77:

Current Head Register (UDC.CHEAD)

IBADSECTICYLINDER BITS 10:81

HEAD NUMBER

3.8.6.2.6 Current Cylinder Register (UDC.CCYl)

The current cylinder register (read-only register 5) is loaded with the first
byte of an ID field when a valid ID field sync mark is found during execution
of a READ 10 command sequence (see Figure 3-78).
Figure 3-78: Current Cylinder Register (UDC.CeYl)
7

CYLINDER BITS 7:0
The UDC CCYL and UDC mEAD registers return data from a disk 10 field
when a Read ID Field command sequence is executed as part of a command.
3.8.6.2.7 Sector Count Register (UDC.SCNT)

The sector count register (write-only register 6) is loaded with the number of
sectors to be operated upon by a read or write command. An initial value
of 0 results in an effective count value of 256. Figure 3-79 shows the sector
count register.
Figure 3-79:
7

Sector Count Register (UDC.SCNT)
6

NUMBER OF SECTORS

VS410 System Module Oetalled Description

3-161

3.13,6.2.8 Retry Count Register (UDC_RTCNT)
The retry count register (VY'Tite"cniy register 7) is loadedlNith the number of

times the controller should retry a data field read operation before reporting
an error, It also sets the state of four c:ontroi signals (see Figure 3-80),
Figure 3-80:

Retry Count Register (UOC.RTCNT)

RTRYCNT

Data Bit

Ddinltlon

RTRYCNT

Retry count in 1'5 complement form, for example, It va.lue of {I must

fn::D1SAB

--_._----------------

be !O<.~ded as its complement" n 11. A noo·O value may be used
for READ LOGIC.4L comma.nds: 0 must be use-d for all others,

Disable diskette (bit 3), This bH determines whether the dlsKet.tf' drive
if; connected to the d.isk contmUer or is disconnected to allow an aHernate controller to use the di.skelle drive, RXD1SAB must be 0 {or ne:rmal operation, VVhen RXDISAB is L !he diskette drive \s
connected from the disk controller and cannot be used until
is set to 0 again, This bit i5 set to 0
by
and bv <1n
{ORE GET . This bit does not affect
disk drives.

This bi! determ.ines the

lNVRDY

'"hich is.

as
the (on·
\I\'hich appears as a 1. in the RE,A.DY
of t.he ODe.
When lNV.RDY is 0., il "h~w" status signal froni the
asserts the "drive
contiWon and appears as a. 1

disl<ette
in the READY bit.

\-\-'hen INVRD'{ is t II "high" status signal from the diskette ddvi'
asserts the "drive
condition to the controller.lll1d "',..,''''''' ... ~
as a 1 tn ~he READY
of UDC DSTAT, When the
i~
INVRDY must be
as descl'ibed in Section 3,8.10 1.0
cause the RX33 drive's ;:,tatus
to be seen ,'.s "drive
the
wntrol!er,
Hind disk drives are not affected bv IN\'RDY, However, for
il:>Ui\v '',lith
systems, 1!\;\'RD'\:' should be set to 0 II/hen a
disk is sdech:d,

MOTOR

Metor on (bit lj. VVhen Ihis bit is set to !, the motor (\f the dl~kette
drive is tLlrned on. The state of this bit 11a9 no efh."ct on hard disk
drivi-;s.

3-162

VAXstalion 2000 af'\d MlcroVAX 2000

Manual

Data Bit

Definition

LOSPEED

Diskette speed select (bit 0). This bit selects the rotation speed and
data rate of RX33 diskette drives. When it is 0, the speed is 360 rpm
and the data rate is 500 KHz (required for RX33K media). When it
is 1, the speed is 300 rpm and the data rate is 250 KHz (required for
RXSOK media), The state of this bit has no effect on hard disk drives.

NOTE: The settings of the RXDISAB, INVRDY, MOTOR, and the

LOSPEED bits are transmitted to the harduJflre only when a DRIVE
SUECT or DESELECT DRIVE command is issued. Loading new
values into UDC.RTCNT does not by itself have any effect; one of
those two commands must subsequently be issued to make the bits
effective. A reset caused by power-on or a write to the IORESET
register clears these four 4 bits to 0 and immediately transmits those
values to the hardware (thus the diskette wiU be connected to the disk
controller and its drive motor will stop).
3.8.6.2.9 Operating Mode Register (UDe.MODE)
The operating mode register (write-only register 8) sets the operating mode
of the controller to accomodate various drive types (see Figure 3-81). Table 3-28 lists the mode values for the drives supported.
Figure 3-81:
7

(HDMODEI

Operating Mode Register (UDe MODE)

CHKCOD

DENS

SRATE

VS410 System Module Detailed Description

3-163

Data Bit

Definition

HDMODE

Hard disk mode (bit 7). This bit controls whether the controller read
data input is to be level transitions or pulse inputs. For this system,
this bit must be 1 for both hard disk and diskette drives.

CHKCOD

Error checking code (bits 6:5). These bits select the error checking
code which is generated during writing and checked during reading.

DENS

Error Checking Code

CRC code. This is to be used for all types of diskettes.

Internal 32-bit ECC without automatic correction. This
is to be used with hard disks (correction under software
control).

Density select (bit 4). When this bit is 1, data is recorded in singledensity FM mode. When this bit is 0, data is recorded in doubledensity MFM mode. This bit should always be 0 for both diskettes
and hard disks.
Bit 3 is not used and must be O.

SRATE

Seek step rate (bits 2:0). These bits set the rate at which cylinder step
pulses are issued by the controller during seek operations. The rate is
also affected by the type of drive (bit HDMODE in this register and
bits 3:2 of the most recent DRIVE SELECT command), and by the
recording density (bit DENS in this register).

3-164 VAXstatlon 2000 and MicroVAX 2000 Technical Manual

Data Bit

Definition

Cylinder Step Pulse Rates

RX33 diskette drive operated at 300 rpm/250 KHz
(required far RX50K and 48 tpi media). Step period is 4 milliseconds.

RX33 diskette drive operated at 360 rpmfSOO KHz
(required for RX33K media). Step period is 4
milliseconds.

Normal commands ta hard disk drives. Step
period is 17.6 microseconds.

RESTORE DRIVE commands to all hard disk
drives. Step period is 6.4 milliseconds.

Table 3-28: Mode Values for the Drives
Drive and Media

HDMODE CHKCOD DENS

SRATE

RX33 drive with RX50K media

001

RX33 drive with 48tpi media

001

RX33 drive with RX33K media

010

RDxx hard disk (normal)

000

RDxx hard disk (RESTORE)

110

3.8.6.2.10 Chip StatuI Regllter (UDC.CSTAT)
The chip status register (read-only register 8) supplies additional chip status
information. The contents of this register are valid only between the time
that the DONE bit in the interrupt status port DKC STAT is set and the time
the next command is written to the controller coinmand port DKC.CMD.
Figure 3-82 shows the chip status register.

VS410 System Module Detailed Description 3-165

Figure 3-82:

Chip Sta,tus Reg!ster (UOC_CSTAT)

o
PRESDRV

Data Bit

Definmon

RETREQ

Retry required (bit 7/. This bit is set to 1 if a fetry was attempted
the controller du.ring the execution of a.n.y read command,

ECCATT

Error ((lrrection attempted ftllt 6/. This bit is set to 1 if the CO[l!f(.llrr's
intern.,l fCC logk has attempted :0 C0rrec! a bad sector.

ECCERR

ECOCRC Error (bit 5;, Th.is bit l~ set to 1 if the controller detects a
CRC or ECe error willie reading troms disk

DELDATA

Deleted data mark (bit 4), This bit is set tel v,hen the controller
reads a st'('lor lD fieJd which has a' deleted data" mark . This hit is
set to 0 for normal sector lD neJds,

S)t'.iCERR

Synchronization error (bit
This bit is set to 1 If the controUer di.~.s
not find <l sync ma.rk While it h; attempting to read either an ID or a
data Held. The command being e);ec.1ted is terminated when this hil
is seL

COMPEER

Compare ern), (bit
The bit is set to 1 if (he information contained
in the desired
and desired head
and
UDC DHEADi
not nh1tch tho.! in an
a disk,
The i;:Jmmand being execuh:d is terminat.ed when this bH is set.

PRESDRV

Present drive selected
These bits represent the number of
the drive currently selected by the controUe"

3-166

Drive Selected

First hard disk drive

S('Cond hard disk drive

Diskette drive

VAXslalion 2000 and MicroVAX

TechnIcal Manua!

3,8.6.2.11 Termination Conditions Register (UDe_TERM)
The termination conditions regisfe! (write·oniy re~i$ter 9) selects the con·
ditions which terminate a command and those wWch generate an i.nterrupt
request to the processor (see Figure 3 ,,83).

Figure 3-83: Termination Condmons Register (UDe_TERM)

Data Bit

CRCPRE

eRe re-gister f'r~$et (bit
When this bit is set to 1, the CRCiECC
registers ate presE.'i. to i
erwr (ode generation and chedJng. A
value (If 1 i$ required for both diskettes and hard disks.

Bit 6 is f1Ot. used and must be 0.
If'...'TDON.t

\I'y'hen this 1:>iI is set to 1, the setting of
intermp! status pt,),rt DKC.
51 AT wiH also set
!NTPEND b.!! In that port and signal a hardware
interrupt request to the systf'1n interrupt controHer ~ VV'hen INTDONE
is 0, INTPEND is not set and no lnterr,Jpt request is Signalled,
rl'l,"''',!.,!;",.. bl: DONEin the

TDELDAT

Terminate on deleted data (bi! 4.1. While this bit is set to 1, if Hw
DELD iH A bit in the chlp Flatus
UDC CS'LA, T is s!:'t
the

detection 0.1 11 rlelE'!ed data mark in a sector 1D fleld thf' current. (orr,·
mBnd terminates (and the DONE bit iI, DKC 511,'1 is se\} whe.r. the
cun€nt S('<:101'
is completed,
..
TDST,~ T'~

Terminate (>1) dr1\'e status 3 change
3), W1iile this bit is set to J
if Ihe DST AT3 bit .in the drive sta.tus register
is M"t to
the current camml'lnd terminates (and the
bit in DKC 51i\T
if> sN,l when the curren! sector opel'ation is complt'!pd.

T,\I".JRPNOT

Terminal:!.; on wrlte protect
WRPROT bit in the drive lilati.lS
protect
from the' selertfd
the current WRTTE or
TRACK command terminatt.'s (and the DONE bit in

NOTE: Wrife

only

Module Detailed

if t.h'f

a diskette driut,.

3-167

Data Bit

Definition

lNTRDCH

Interrupt on ready change (bit 1). When this bit is set to 1, the setting
of the ready change bit RDYCHNC in the interrupt status port DKC.
STAT also sets the INTPEND bit in that port and signal a hardware
interrupt request to the system interrupt controller. When INTRDCH
is 0, INTPEND is not set and no interrupt request is signalled.

TWRFLT

Terminate on write fault (bit 0). While this bit is set to 1, if the WRFAULT bit in the drive status register (UDCPSTAT) is set by a write
fault signal from the selected drive, the current WRITE or FORMAT
TRACK command terminates (and the DONE bit in DKC STAT is set)
•
when the current sector operation is completed.

NOTE: Write fault can be signalled only by a hard disk drive.
NOTE: The contents of the UDC. TERM register are destroyed whenever a RESET
command is issued or an 110 reset signal is received. In particular, INTDONE is
cleared so that the chip does not generate any command done interrupts until UDC.
TERM is set up again.
3.8.6.2.12 Drive Status Register (UDC.DSTAT)

The drive status register (read-only register 9) shows the state of several
signals from the currently selected drive. Its contents are invalid if no drive
is selected. Figure 3-84 shows the drive status register.
Figure 3-84:
1

Drive Status Register (UDC.DSTAT)
6

3-168 VAXstatlon 2000 and MlcroVAX 2000 Technical Manual

Data Bit

Deiinition

SELACK

Select acklwwJedg1~
1 his bit is 1 when a select
signal is receJ"ed fl'om thesdected h.m! (lJ"k drive, Failure
to receive this
indicates that no drive is inst.aHed to
select numbe!\ SELACK is

to tlit' nment
drives,

INDEX

0 for

(hi! 6.1, This bi.t hi wht'n the current dJ'ivt"s medium
index poinL The duration of the 1 slatf' varles Utci,)'C'I',U'
tlf>Ol1 the drive type and (ki! diskettes; ihe
sl!'.Iectro.

Index
passes

Seek

,hit 5), This bit is Q while the
moving H5 heads; it bec(n1H's 1. when ihe

dis}{ dnve

has corn-

pleted the seek oreration and its heads are stable, SKCOr.1 is
1 when i1 diSKette driv€ .is fwlected: it cannot be u,;ed to
hir sed,;
settling time for a disl<l'tte dri.ve {such lit
the driver software),

TRKOO

mu~t b(~

This bit .is 'j when the (11rrentlv Belectf'd drives head:"
at cylinder 0, H IS vallO. fOf all d.rive

DSTAT3

Drive st.atus 3 t,bit

vVRPROT

Write protect INt
This bit reflects the state of the writl?
signal rereivf'd horn the currently selert(cti drive: /I 1 indicates thi'lt
writing is pmhibih:."(.l. For a diskette drive. VV'RPROT is 1 when the'
n(lld, covered. For II hatd
dist;eHe .in the drive has its

This bit is unused and is always set to

dis).: drive this bit is

READY

Drive

1). This bH indicate'S whether or not the cnntro!!(;'l'

chip
When

that the currently se.lected drive is ready for
ist the wntroUe:r issues head pOSHi(lnlng. and datil

trans.ler commands to the drive, "\then READY is 0, the (ontroiieJ

does not execute such commi'l.nd~.
The state of READY for the dis};etle drive is deteTmin~1
statu.:;; signa! from the currently seleclt'd drive and the
{If ihe
INVRDY oJ! (If the UDC}HCNT T(·glstet. When JNVRDY it' 0; a "lOw

drive status
drive statu!;
scribed in

makt:s READY !l 1; lvhen INVRlJY is 1, a
makes READY i'I 1., INVRDV' must be Ulwd as
3,g. Hl to ma.ke RE,I1,DY a. 1 so thaI the (cmtroIkr

.issues commands tu (he drlY(~,
Fm hard disk drives, READ)' is always 1 when the ad,,£, is
operation and INVRDY does !'lOt affec't the READY
for compal:ibmt} with early systems, lNVRDY
ha.rd disk driver..

for

VS41 () System Module Detailed Description

3-169

Data Bit

DefiniHon

WRFAULT

Write fault (bit 0). This bit is 1 when the selected hard disk drive finds

an internal condition which prevents successful write operations, such
as improper supply voltages. This bit is always 0 for diskettes.

3.8.6.2.13 Disk Data Register (UDC.DATA)
The disk data register (read/write register OAh) is used by the controller's
DMA logic to pass data to and from the disk during data transfer operations.
It is also used by a program to specify the head load time delay for a DRIVE
SELECT command. Figure 3-85 shows the disk data register.
Figure 3-85:
1

DiSk Data Register (UDC_DATA)

DATA

NOTE: The COlt troller chip internal register pointer must be set to OA11 by a SET
REGISTER POINTER command to designate the UDCPATA register during all
DMA data transfer operations.

3.8.7 Command Overview
The controller executes fourteen commands, which can be divided into two
groups. The first group comprises housekeeping and control operations
which do not transfer data to or from a drive.

•

RESET

• SET REGISTER POINTER
•

DESELECT DRIVE

•
•
•

DRIVE SELECT
RESTORE DRIVE
STEP

• POLL DRIVES
The second group of commands transfer data to or from a drive.
•

SEEK/READ ID

•

FORMAT TRACK

3-170

VAXstation 2000 and MicroVAX 2000 Technical Manual

)

•

READTRACK

•

READ PHYSICAL

•

READ LOGICAL

•

WRITE PHYSICAL

• WRITE LOGICAL
The controUer has an internal status byte which it checks at various times
during command execution. This byte contains copies of the DELDATA
bit (in .the UDC CSTAT register), the BADSECT and OVRUN bits (in the
DKC STAT port), and the READY, WRPROT, WRFAULT, and CARTCH
bits (In the UDCPSTAT register). This internal status byte is examined
before the execution of all READ and WRITE commands and is checked
again just prior to the completion of most commands. It is also checked
between sector operations during the execution of READ LOGICAL, READ
PHYSICAL, WRITE LOGICAL, and WRITE PHYSICAL commands. The
controller makes decisions regarding command termination and interrupt
generation based upon the contents of this status byte and the state of the
bits in the UDC.TERM register.
At the completion of all commands, the controller sets the DONE bit in the
DKC.STAT port. Depending upon the contents of the UDC.TERM register,
this may also generate an interrupt request, except for the RESET and SET
REGISTER POINTER commands which never generate interrupt requests.
Issuing a new command dears the DONE bit.
During aU data transfer commands (except READ TRACK), the controller
uses three common sequences of internal operations. As it begins each
sequence, the controUer places a code identifying it in the TERM COD bits
of the DKC.STAT port. If the I:!ommand is not completed successfully, these
bits identify' the sequence during which the failure occurred. The sequences
and codes are:
01

VERIFY

DATA TRANSFER.

VS410 System Module Detailed Description

3-171

3.8.7.1 Read 10 Sequence

The READ 10 sequence reads the next available 10 field (using the head
designated by the UDCSHEAD register) to find the cylinder at which the
heads are positioned and then, if necessary, moves the heads to the position
specified in the desired cylinder registers UDC DCYL and UDC DHEAD.
The sequence comprises the following steps: 1. Attempt to find an 10 field sync mark. If no mark is found within
33,792 byte times, the controller sets the SYNCERR bit of the UDC
CSTAT register and terminates the command.
2. Read the 10 field. The data from the 10 field is stored in the UDC
CCYL and UDC.CHEAD registers. If the CRC bytes of the 10 field
are incorrect, the controller sets the ECCERR bit of the UDC CSTAT
register and terminates the command.
3. Move to desired cylinder. The controller calculates the direction and
number of step pulses required to move the heads from their current position to that specified in the UDC.DCYL and UDCPHEAD
registers, and (if necessary) issues the step pulses to the drive.
3.8.7.2 Verify Sequence

The VERIFY sequence reads 10 fields on the current track to verify that the
heads are at the desired cylinder, that the head number is correct, and to
find the desired sector for a data transfer. The sequence comprises the
following steps:
1. Attempt to find an 10 field sync mark. If no mark is found within
33,792 byte times, the controller sets the SYNCERR bit of the UDC.
CSTAT register and terminates the command.
2. Search for desired sector. The data from the 10 field is compared
with the contents of the UDC DCYL, UDC DHEAD, and UDC
DSECT registers. If the contents match, the sequence continues
with step 3. Otherwise, the controller hunts for the next 10 field
sync mark and repeats the comparison process. If the desired sector is not found within 33,792 byte times, then the COMPERR bit in
the UDC.cSTAT register is set and the command is terminated.
3. Check the 10 field validity. When the desired sector is found, if the
CRC bytes of the 10 field are incorrect, the controller sets the ECCERR bit of the UDC.cSTAT .register and terminates the command.
For READ PHYSICAL and WRITE PHYSICAL commands, the 10
field comparison is done only until the first sector to be transferred
is found. For subsequent sectors, the 10 field contents are not compared, although the 10 field CRC is checked.

3-172 VAXstation 2000 and MicroVAX 2000 Technical Manual

3.8.7.3 Data Transfer Sequence
The DATA TRANSFER sequence transfers the contents of the next available data field to or from the disk data buffer. For a READ operation, the
sequence comprises the following steps:

1. Find data sync mark. The controller searches for a data sync mark
(FBh or F8h). If the mark is F8h, then the controller sets the DElDATA bit in the UDC CsTAT register; otherwise it clears that bit.
When the data sync mark is found, the controller updates the UDC
CCYl and UDC CHEAD registers from the values found in the 115
field preceding the data sync mark.
2. Perform DMA transfer. Using DMA, the controller transfers the data
bytes and the CRCIECC bytes of the sector to the disk data buffer.
If the system does not respond to DMA requests from the controller
within 1 byte time, the controller sets the OVRUN bit in the DKC.
STAT port and terminates the command.
3. Check CRC/ECC bytes. If the CRCIECC bytes following the data
are incorrect and the controller cannot correct the data (or has been
instructed not to try, according to the CHKCOD bits of the UDC
MODE register), then the controller sets the RETREQ bit in the UDC:
CSTAT register and decrements the RTRYCNT field of the UDC.
RTCNT register. If the UDC.RTCNT register is now 0, then the
controller sets the ECCERR bit in the UDC CSTAT register and terminates the command. Otherwise, the controller goes back to the
VERIFY sequence to locate the sector for another attempt.
For a WRITE operation, the sequence comprises the following steps:
1. Write data sync mark. The controller writes either a normal or
deleted data mark according to the write command byte.
2. Perform DMA transfer. Using DMA, the controller transfers the data
bytes from the disk data buffer to the sector. If the system does not
respond to DMA requests from the controller within 1 byte time, the
controller sets the OVRUN bit in the DKC_STAT port and terminates
the command.
3. Write CRCIECC bytes. The controller writes the CRCIECC bytes following the data. Note that no error retries are permitted for write operations, so the RTRYCNT field of the UDC_RTCNT register should
be set to 0 (Is complement form).

VS410 System Module Detailed Description 3-173

After each successful sector transfer, the controller adds the
of the
{not induding its CRCiECC bytes) to the 'ODe DMAx registers
and decrements the UDC_SCNT register, If the UDC_SCNt register is then
(), the controller terminates the (;{)mmand. Otherwise, the controller in·
crements the UDCPSECT register, resets the RTRYCtH field of the UDC_
RTCNT register to its value as of the beginning of the command, and returns
to the VERIFY sequence to locate the next sector.

sector

\Alhen the controller reads a sector, it transfers the sector's error checking

bytes (2 bytes for dIskette CRC; 4 bytes for hard di$k Eee) into the disk
data buffer folloMng the sector's last data byle. If the read is successful,
the DMA address is advanced only by thE' number of data b y1es, so the
data from the next sedor of a multi-se<:tor read will be contiguous \vitl! the
preceding sector's datil. However, the buffer must have space to hold the
error checking b:-ies of the last sector, so the highest allowable starting point
in the buffer is the buffer size (16384) minus tnt:' sector size (512 + 2 or 512,.. 4
byit'S), If the Dl\1.A address exceeds the buffer

it wraps around to the

beginning of the buffer,

3.8.8 Command Descriptions
This section describes the disk commands,

3.8,8.1 RESET Command
The RESET command
the controller chlp in a knm'ln state. It has the
same effect as a power-on reset The DONE bit in the DKC STAT i s
set
this command but no interrupt
is generated. This is
execution of this tomrnand dears the
TER1:v1. register. The
TEHM
register must
reloaded after executing
command. A programma.),
issue a RESET command to terminate the execution of any non-data·transfer
command . but data transfer commands cannot be terminated in this miU1·
neL Figure 3-86 shows the RESET comnland.
Figure 3-86:
'l

RESET Command

o J
3JUL2 SET REGiSTER POINTER Command
The
POINTEH conlmand sets the contrellet's internal
ister
to designate the
which is accessed
the next
access to the
. RJ~G port.
that each Stich
access increments
the internai pOinter until it n~il.ches its
OAh
which the
remaim at this value.
3-174

VAXsta!lon 2000 and MicroVAX 2000 Technical Manuai

Do not set the pointer to a value outside the valid range of OOh !.hrough
OAh< The DONE bit in the DKC_STAT port is set by this command but
no interrupt request is generated. Figure 3-87 shows the SET
rOt:lv'TER command,
Figure 3-81:

SET REGISTER POINTER Command
2

4
(I

3.8<8.3 DESELECT DRIVE Command
The DESELECT DRIVE command negates aU drive select outputs so that no
drive is selected, When no drive is selected, the contents of the drive status
register UDCPSTA rare invaUd. Figure 3-88 sno\,rs the DESELECT DRIVE

comm.and,
Figure 3-8S:

DESELECT DRIVE Command

o
NOTE: TIle
DRIVE commmui should issued when no drlt1(" is in use.
uecuticrn of this command may cause RDYCHNG to be set in the DKC_STAT port.
Execution of this command transmits the values of the INv1~DY
RXDlSAB, and LOSPEED bits bont the UDC~RTCNT register to the h£ud"
ware, If the READY bit of the UDC D5TAT regi.ster is 1 at the conclusion
this comntand becausf~ the INVRI)): bit" of the 1..JDC RrCNT '""'''·''''',o>r
1 at the time the DESELECT DRIVE comn1and was iss"ue(l the
bits of the DKC"STAT register l'\'lU be n. This does not indicate an error
and shou.ld be ignored,

VS410 System Module DetaHed Description

3-175

3.8.8.4 DRIVE SELECT Command

The DRIVE SELECT command
1
the four possible drives con·
nected to the controller and sets its data. transfer rate (see Figure 3-89).
Figure 3-89:

ORIVE SELECT Command

Ii
1

IHLOELAyl

Data Bit

Defin.iUoli

HLDEL)..Y

Head load delay {bit 4), When this bit Is set, the controller d~lays for
diskette head loading M the beginning of data transfer commands.
The du.ration of the delay is specified by the contents of the UDC_
DATA register at the time thaI the command !s issued, The RX33
drives do not require th.ls delay; this bit should be 0 for aU diskette
a.nd hard disk drives.

DATRATE

Da.ta rale (bits
These bits determine the data bit rate and hard
disk format options.

Bit 3

Bit 2

o
o

DRVNUMB

Data Rate

Hard disk with

J[.I fields. Not used in this sys·

rem.
1

Hard disk with 4·byte ID fields. Use Ihis \Ialue for aU
hard disks.
.

Diskette with 500 KHz: data rate, Use thl:!l value for
diskette drives with RX33K high-capacity media.

DiskeHewtth 250 KHz data rate. Use this value for
diskette drives with standard media, including RX50K
and 48 ipi media.

Drive num.ber (bits

These bits selectihe active drive.

3-176 VAXstatlon 2000 and MlcroVAX

Technical t,,1anual

------~-------.

Data Bit

o
o

_._- ...

Drive Selected

First hard disk {in VS41tl system unitl

Second hard disk (in V54GB storage expansion

{}
---

Diskette rlriVIc' (,in VS<nO system un]!)
------~.~.--------

--------_.-----,,----------_._._---

The
SELECT command transfers the contents of the desired hear!
register UDC.DHEAD to the current head register UDC~CHEAD, When
command \",rhkh uses a READ ID sequence (f()f example, a read or write
command) is executed, the head designated by the UDC.cHEAD regi8ter
is used to find the present position on the disk. This requires thai liDC.
CHEAD designate a head which is valid for the selected drive and medimrL
Therefore,
'or to issuing a DRf\lE SELECT command, a program must
load the II CpHEAD register v,rltn a head number (in bits 3:0) which is
valid for both the drive and medium being selected (head 0 is the best
cholce, since .it's guaranteed to be valid for any case).
Execution of DRIVE SELECT transmits the values of the IN\'RDY, MOTOR
RXDlSA.B, and LOSPEED bits from the UDC_RTCNT register to the hardware. It the READY bit of the VOC DSTAT is 0 at the conduskm of this
command (this depends upon the drivels status signa! and the value of the
Il\iVRDY bitt the TERMCOD bits 0f the nCR.STAT register
be 1.1. If
the selected drive is a hard disk, this is a "not ready" error condWon. For
a diskette drive, this may not be an error. Section 3JUO explains READ"{
and INVRDY for diskettes.

Whenever a DRi\t'(
command selects a diskette drive that wa:> not
already selected,. up to 70 miUiseconds may be requited for UH~ read da'!i1
recov€lJ' circuit to stabililre before the controHe.r receives usable data fwm
the diskette. No delay is reqUired when selecting a hard disk driVe.

VS410 System Module Detailed Description

3- 1'7'1

3.8.8.S RESTORE DRIVE Command

The RESTORE DRIVE command sends step pulses to the selected drive to
move its heads outward until it reaches cylinder O. Prior to issuing this command, a drive must have been selected by a DRIVE SELECT command and
the UDC.MODE register must be set for the selected drive type. Figure 3-90
shows the RESTORE DRIVE command.
Figure 3-90:

Restore Drive Command

SKWAIT

Data Bit

Definition

SKWAIT

Wait for seek complete (bit 0). If this bit is t the controller tests the
seek complete signal from the drive (reflected in the SKCOM bit in the
UDCPSTAT register) to determine when head motion is complete. If
SKWAIT is 0, the controller assumes that motion is complete after it
has issued the last step pulse. SKWAIT should be 0 for diskette drives
and 1 for hard disk drives.
Before issuing each step pulse, the controller checks the TRKOO and
READY bits in the UDCPSTAT register. If TRKOO is 1 or READY is
0, the controller terminates the command. The controller issues up
to 4096 step pulses, checking TRKOO and READY after each one. If the
drive does not set TRKOO to 1 during this time, then the controner
terminates the command with the TERMCOD bits in the DKC STAT
port set to 10.
This command requires that the READY bit in the UDCPST AT register be 1. Section 3.8.10 explains the READY state for diskette drives.

NOTE: When attempting to RESTORE a hard disk, be sure to set the
step rate to 6.4 niilliseconds for non-buffered seeks.

3-178 VAXstation 2000 and MicroVAX 2000 Technical Manual

3.8.8.8 STEP Command
The STEP command issues one step pulse to move the heads of the selected
drive in or out 1 cylinder. Prior to issuing this command, a drive must
have been selected by a DRIVE SELECT command and the UDC.MODE
register must be set for the selected drive type. Figure 3-91 shows the
STEP command.
Figure 3-91: STEP Command
7

OUT

SKWAIT

Data Bit

Definition

OUT

Direction of motion (bit 1). If it is 1, motion is outward toward cylinder O. If it is 0, motion is inward. Care must be taken not to attempt
to move the heads inward beyond the number of cylinders on the
device.

SKWAIT

Wait for seek complete (bit 0). If this bit is 1, the controller tests the
seek complete signal from the drive (reflected in the SKCOM bit in the
UDCPSTAT register) to determine when head motion is complete. If
SKWAIT is 0, the controller assumes that motion is complete after it
has issued the last step pulse. SKWAIT should be 0 for diskette drives
and 1 for hard disk drives.

The STEP command is normally used during formatting. It does not attempt
to read an ID field to verify its position and so it works on an unformatted
disk.
This command requires that the READY bit in the UDCPSTAT register be
1. Section 3.8.10 explains the READY state for diskette drives.

VS410 System Module Detailed Description 3-179

3.8.8.7 POLL DRIVES Command
The POLL DRIVES command polls selected drives for seek complete signals
to assist a driver program to perform simultaneous seeks on hard disk drives
(see Figure 3-92).
Figura 3-92:

POLL DRIVES Command

1 IORV3 IORV2 IORV1 IORVO

Data Bit

Definition

DRVx

Drives to be polled (bits 3:0). These bits determine which drives are
polled. A 1 includes a drive in the poll sequence. Since only hard
disk drives delay assertion of the seek complete signal until their head
motion is complete, only bits DRVO and DRVl should ever be set. Seek
complete is asserted at once, whenever a diskette drive is selected.
The command operates by selecting in turn each drive whose DRVx bit
was set in the POLL DRIVES command until a drive is polled whose
seek complete signal is set (this signal appears in bit SKCOM in the
UDC_DSTAT register), at which point the controller terminates the
command. At the completion of the command, the PRESDRV bits of
the UDC_CSTAT register indicate which drive is selected. The driver
program must explidtly select each drive from which it expected a
seek complete signal and test its value in the SKCOM bit of the UDC_
DSTAT register.

The POLL DRIVES command must be preceded by a DESELECT DRIVE
command.

3-180 VAXstatlon 2000 and MicroVAX 2000 Technical Manual

)

3.8.8.8 SEEK/READ 10 Command
The SEEK/READ ID command determines where the heads of the selected
drive are presently positioned by performing a READ 10 sequence. Then,
if the STEP option bit in the command code is set, it moves the heads to the
new position determined by the UDC_DCYL and UOC_DHEAO registers.
Figure 3-93 shows the SEEK/READ ID command.

Prior to executing this command, a drive must have been selected by a
DRIVE SELECT command and the following registers must be appropriately
set; UDC_MOOE, UOC_RTCNT, and (if STEP is set) UOC_DCYL and UOC_
OHEAD.
Figure 3-93:

SEEK/READ 10 Command

)
7

I !

STEP ISKWAIT VERIFY

Data Bit

Definition

STEP

Seek to desired cylinder (bit 2).
If this bit is 1, the controIlt'f issues the stt'p pulses necessilTy to move the heads from their current position to that specified by the UDC.DCYL and UDC.DHEAD regis.
If the STEP bit Is n, no motion occurs and the only
ters.
effect of the command is to update the UDC.CCYL and UDC_
CHEAD registers to reflect the current position of the heads.

SKWAIT

Wait for seek complete (bit 1). If this bit is 1, the controller tests the seek complete signal from the drive (reflected in the SKCOM bit in the UDC.
If
DSTAT register) to determine when head motion is complete.
S)(WAIT is 0, the controller assumes that motion is complete after it has issued the last step pulse.
SKWAIT should be 0
for diskette drives and 1 for hard disk drives.
This bit must
be 0 if the STEP bit is also O.

VERIFY

Verify position (bit 0).
If this l'Iit is 1, the controller performs a VERIFY sequence after performing the operations indicated
by the STEP and SKWA1T bits. This bit must be 0 if the STEP bit Is also 0,

VS410 System Module Detailed Description 3-181

3.8.8.9 FORMAT TRACK Command

The. FORMAT TRACK command writes on the current track a complete new
image consisting of sector 10 fields and data fields with the appropriate
gaps between them. It writes the entire track, beginning at the leading
edge of the index signal and continuing until the index signal is received
again. This command must be used to format each track of a disk before
any other data transfer command can be issued to that disk. Note that this
command does not perform READ ID and VERIFY sequences; it writes to
the currently selected cylinder and head. Figure 3-94 shows the FORMAT
TRACK command.
Figure 3-94:

FORMAT TRACK Command

Data Bit

Definition

DDMARK

Deleted data mark (bit 4). If this bit is 1, each data field is preceded
by a deleted data mark (F8h). Otherwise the data fields are preceded
by a normal data mark (FBh).

WRTCUR

Reduced write current (bit 3). Not used and must be O.

PRECOMP

Write precompensation. Section 3.8.9 explains write precompensalion.

Prior to issuing this command, the controller must have selected the drive
with a DRIVE SELECT command and positioned the heads to the correct
cylinder using the RESTORE DRIVE and STEP commands. These commands can be used on an unformatted disk. The SEEK/READ 10 command
cannot be used on an unformatted disk because it attempts to read 10 fields
from the disk.
The information bytes for each sector's 10 field are read from a table in
the disk data buffer. This table must have four bytes for each sector to be
established on the track. Figure 3-95 shows the contents of the table in the
disk data buffer.

3-182

VAXstation 2000 and MicroVAX 2000 Technical Manual

Figure 3-95: ID Field Bytes for each Sector

.,
o
1

CYLINDER BITS 7:0
BABSEeTI CYLINDER BITS 10:8

READ NUMBER

SECTOR NUMBER

I0 I0 I0 I0 10 11 I 0

For diskettes: Byte 0 contains the track number 0.. 79; byte 1 contains the
head number in bit 0 and is otheIWise O. Byte 2 contains the sector number
in the range 1.. 15 for RX33K media. And byte 3 indicates a sector size of
512 data bytes.
For hard disks: Byte 0 and bits 6:4 of byte 1 contain the cylinder number.
Byte 1 contains the head number and bad-sector flag. Byte 2 contains the
sector number in the range 0.. 16. And byte 3 indicates a sector size of 512
data bytes followed by 4 ECC bytes. The order of sector numbers may be
arranged to provide whatever interleave factor is desired.
The BAOSECT bit in the second byte of the sector 10 field is set to 1 to flag
a physically defective sector. (The driver program must provide a means
of substituting another sector for the defective 1.) There must be at least 1
sector on each track which is NOT marked with the BADSECT bit. If the
controller chip encounters a track all of whose sectors have BADSECT set,
the chip functions unpredictably.
The FORMAT TRACK command requires a large number of parameters,
so some registers must be used twice. The following steps are required to
format a track:

)

1. Set up the information for the ID field bytes in the disk data buffer
and load the UDCPMAx registers with the address of the information for the first sector. Then issue a DRIVE SELECT command to
select the proper drive. An additional effect of this command is to
save the contents of the UOCpMAx registers in the UDC CHEAO
and UOC.cCYL registers and a temporary register so that the UOC.
DMAx registers can be reused to supply additional format parameters.
2. Load the UOCpHEAD register with the correct head number.

VS410 System Module Detailed Description 3-183

3. Load the parameters listed in Table 3-29 into the registers and in
the formats indicated (note that RX50K and 48 tpi media cannot be
formatted by this system). The values are listed in decimal true
form, before conversion to the format required by their registers.

Table 3-29: Register Parameters
Parameter

Format

Hard disk
Value
RX33K value

Gap 0 size

UDC DMA7

2'scomp

Gap 1 size

UOCpMA15

2's comp

Gap 2 size

UDC_DMA23

2's comp

Gap 3 size

UDC OSECT

2's comp

Sync size

UDC_DCYL

l's camp

Sector count

UOCSCNT

l's comp

Sector size code

UOC_RTCNT

l's comp

4. Load the UDC MODE register as appropriate for the drive and
medium.
5. Position to the desired cylinder, using RESTORE DRIVE or STEP
commands.
6. Issue the FORMAT TRACK command. All data field bytes are filled
with a value of E5h and all gaps are filled with 4Eh.
Additional tracks under the same head can be formatted by revising the
10 field bytes in the disk data buffer and repeating steps 5 and 6. When
it is necessary to select a new head, the entire sequence of steps must be
repeated.

3-184 VAXstation 2000 and MicroVAX 2000 Technical Manual

3.8.8.10 READ TRACK Command
The READ TRACK command reads the ID fields and (optionally) the data
fields from an entire track in10 the disk datu buffer, starting ftOrn the Index
point and ending when the index point' is again reached. No error checking
ip, performed on ID or data fields. Note that this command does not perform
READ II) a,nd VERIfY sequences; data is read fmm the currently seiecled
cylinder and head,
3-96 shows the
THACK command.
Figure 3-96:

[

READ TRACK Command

-432

Data BIt

Definition

XDATA

Transfer data fields (bit
If this bil is i" data fields as well as 10'
fields aft: transfe:rred from each sector into the disk oata buffeL If it
is 0, only to fields are transf't'ued.

----------"------..

--~---,----

Prior to executing this command,. a drive must have been selected by a
DRIVE SELECT command, the following registers must have been .loacl("d,
and the internal register pointer must be set to point to the UDCPATA
register.
•

UDC}vfODE (mode appropriate to selected drive and media),

•

UDCpM.Ax (starting address in disk data buffer)

<I'

UDC

count. The RTRYCNT field must be 0 Os co-tn,
for this command Automatic retries cannot be per,
form.ed during this

plen1€lit

/he Iwrm.aIEEAD and WRITE
the READ n;;;.liOi;. emn
DM/h
regIsfers fo reflect the flmOimf Of dala

VS4iQ

Module Detailed Description

3-185

3.8.8.11 READ PHYSICAL Command

The READ PHYSICAL command reads 1 or more sectors from a track, beginning with a specified sector and continuing through physically consecutive sectors, until either the sector count is satisfied, or a bad sector is
encountered, or the track index is reached. Figure 3-97 shows the READ
PHYSICAL command.
Figure 3-97:

READ PHYSICAL Command

IXFER

Data Bit

Definition

XFER

Transfer data (bit 0). If this bit is 1, data is transferred from each
sector into the disk data buffer. If it is 0, no data is transferred but
all error checking is still performed.

Prior to executing this command, a drive must have been selected by a
DRIVE SELECT command, the following registers must have been loaded,
and the internal register pointer must be set to point to the UDCPATA
register:
•

UDC_MODE (mode appropriate to selected drive and media).

•

UDCPMAx (starting address in disk data buffer).

•

UDCPCYL (desired cylinder).

•

UDCPHEAD (desired head).

•

UDCPSECT (number of first sector).

•

UDC_SCNT (number of sectors to be read).

•

UDC_RTCNT (retry count. The RTRYCNT field must be 0 (Is complement form) for this command. Automatic retries cannot be performed because the number of the sector to be retried (after the
first one) is not necessarily the same as that in the UDCPSECT
register).

3-186 VAXstation 2000 and MicroVAX 2000 Technical Manual

The controller begins command execution by using the READ ID, VERIFY,
and DATA TRANSFER sequences to find and read the first sector. After this
and each sUbsequent sector is successfully read, the controller decrements
the UDC~SCNT register. If it is not 0, thf; controner increments the UDC_
DSECT register and reads the next physical sedor "'rlthout regard to its
sector number. This process continues until UDC,SCNT is reduced to 0, or
an error occurs, or an index pulse is received from. the drive. If the 10 field
of a sector about to be read has the BAD SECTOR bit set, the coatroUeI
terminates the command 'with a TERMCODvalu€ of 10 in the DKC 5TAT

port
3.8.8.12 READ LOGICAL Command
The READ LOGICAL command reads one or more sectors from a track, be·
ginning with a specified sector and continuing t.hrough l.ogicaUy consecutive
sectors b\' incrementing the desired se.ctor number until the sector count
is satisfie';j or an unrecoverable error occurs. Figure 3-98 shows the READ
LOGICAL command.
Figure 3-98:

READ LOGICAL Command

Data Bit

Definition.
bad sedors
If lhh; bit. is 1, then In(' corHroUer
any sector:; marked wi! h thf' BA[lSECT bit in the secter ID
If
the ByPASS bH is 0 andwch a sector is (,l1cmmtered, the controller
term.i.nates th~; command lvith thf'TERl\1C:OD field set to 10 and til('
BADSECT bit $t:l to 1 in th~:
port,

XFEH

Tnmsfer dala
0), If th:l, bit is 1. data 15 tmnsferred. from ellch
s('clor in!(l thi! dhk d .. tll buffer. If it is 0, no data is tfllnsfe1:l'€:,,,I but
all e,'Wf
is ~\ill

Modufe Detailed Description

3-187

Prior to
this command, a dnve must have been
DRIVE 5£LEl-'-1 comtnand, the
mllst hnve been to21a.ea
and the internal
pointer mus!.
set 10 point to the
DATA
..

UDC)'v10DE (mode appropriate to selected drive and media)

UDC_DMAx {starting address in

DCYL (desired cylinder),

...

UDCYHEAD (desired head),

UDCPSECT (number of first sector),

UDC

buffet},

(number of sectors to be

(retry count),

command execution
the READ If), VERIFY,
and DATA
to (ind and
the first sector. After
this <ind each subseQuent sector is successfullv read {possibly after
'
the UDC
"
If it is then not 0" the
tIle controHer
controller increrm:nts the
and uses the VEIUFY and
DATA
to Hnrland read the next
is reduced to 0 or an

error o(curs
3.8.8,13 WRITE PHYSICAL Command
comnHmd wTitE;'S one or more sectors on ,)

sector and

con,,;;,,>

sectors until
sector count is
index IS enCOlll'·
tered,
],.99 show;,> the \VRITE FHYSICAL command.

Figure 3-99:

.,
i

3-188

WAlle PHYSICAL Command

iSJ'PASS 1

II DDMARKIWRTcua!
•
I

VAXsta!ion 2000 and Mlcrol/AX

0
"

PRECOMP

Technical

Data Bit

Definition

BYPASS

Bypass bad sectors (bit 6). If this bit is I, then the controller ignores
any sectors marked with the BADSECT bit in the sector ID field. If
the BYPASS bit is 0 and such a sector is encountered, the controller
terminates the command with the TERMCOD field set to 10 and the
BADSECT bit set to 1 in the DKC.STAT port.

DDMARK

Deleted data mark (bit 4). If this bit is 1, the data is preceded by a
deleted data mark (F8h). Otherwise the data Is preceded by a normal
data mark (FBh).

WRTCUR

Reduced write current (bit 3). Not used and must be O.

PRECOMP

Write precompensation. Section 3.8.9 explains write precompensation.

UDC}.10DE (mode appropriate to selected drive and media).

•

UDCpMAx (starting address in disk data buffer).

•

UDC.DCYL (desired cylinder).

•

UDCpHEAD (desired head).

•

UDCPSECT (number of first sector).

•

UDC.SCNT (number of sectors to be read).

•

UDC.RTCNT (retry count. The RTRYCNT fieJd must be set to 0 (Is
complement form), since retries of write operations are not permU.
ted}.

The controller begins command execution by using the READ ID, VERIFY,
and DATA TRANSFER sequences to find and write the first sector. After
this and each subsequent sector is successfully written, the controller decrements the UDC.SCNT register. If it is not 0, the controller increments the
UDC_DSECT register and writes the next physical sector without regard to
its sector number. This process continues until UDC_SCNT is reduced to
0, an error occurs, or an index pulse is received from the drive.

VS410 System Module Detailed Description

3-189

3.8.8.14 WRITE LOGICAL Command
The "VErrE LOGICAL comrn.andwrites one or more sectors on a track beginning with a specified sector and
through logically consecutive
sef'tors by incrementing the desired sector number
the sector count is
satisfied (see Figure 3,,100),
Figure 3-100:

WRITE LOGICAL Command

!BYP~SS

I: I I I ~
1,

DDMARK \(R rCUR

PRE.GOMP

Definition

Data Bit

BYPASS

Bypass bad sectors (hit 6), If this bH isL then the controller

arty sect.ors marked with the BADSECT hi! in tlw sector ID
the BYPIi,sS bit is I} and sucb a. sector is er.co\:njer~d. the ,cnt,olk~
ternunates the cowmand ,,"ith the TERMCOD fieJd set to 10 and the
BADSECT bit set to 1 in the
AT pon

DDl\1ARK

Deleted data mark 1.bit 4). If this bit is '1, the data is ""·"(·P"~'"
Otherw.!;e the data is ""~"·,·,,·l,,,";

de!et~d datil mark (Fi5h,L

data mar~:
VllnCUR
PREC01\,fP

Redt:ced write ctlrrent \bit 2',). Not llSed andml.lst be
Write M"-"rn",'."""
t~(n'L

Prior to
this command, a dave mu!"t have been seleded
DRI\iE
command, the following
must have been
and the in!ernaJ
pointer must be set to
to lhe LJDC)..1ATA

•

(mode appropriate to select.ed drive (md media).

(starting address in disk data buffer).

•

(desired cylinder).

•

head).

•

3-190

(number

first

{number

sectors to be

VA.Xstation 2000 and

2000

UDC_RTCNT(relry count The RTRYCNT field must be set to 0
complement form), since retries of \II,'fite operations are not permitted).

The controller begins command execution by using the READ lO, VERIFY,
and DATA TRANSFER sequences to find and ,..'lite the first sector. After
this and each subsequent sect.or is successfully ",'litten, the controner decrements the UDe SCNT register. If it is then not 0, the controller increments
the UDCPSEC't register and uses the VERIFY and DATA TRANSFER sequences to find a.nd v.'l"ite the next logical sector. Tms process continues
until UDe SeNT is reduce-d to 0 or an error occurs.

3.8.9 Write Precompensation
The FORrvtA T TIV\CK "VRITE PHYSICAL, a.ltd ,\,1\lRlTE LOGiCAL commands have a 3-bit field named PRECOMP in their command codes, The
value of this field determines the amount of \..'tHe precompensation applied
to data which is written on a disk, The appropriate value depends upon
thti' device type, media type, and what cylinder is being vflitten. Table 3-30
lists the write precompensation parameters,

Table 3-30:

~rite P!:!.l'compe"l.satlon Parameters .__.,_____~, __

Drive

Cylinders

Precomp

Time shift

with RX33K me-ilia. SOO kf1l,

tL7q

001

112 ns

with RX50K meOia, 2.50 .kHz

0,.79

100

2121\$

0 .. 39

lOG

212 ns

RD32 hard disk drive

0 .. 819

none

RD53 hard dis.k drive

0,,1023

RDS4 hMd dis}. drivE'

0.,1225

000
000
000

RX33 di.skette drive

with

medi,;, 2Sn kHz,

none
none

3.8.10 Diskette Drive READY Condition
The drive status signal from a.n RX33 diskeHe drive serves as both a drive
ready Indicator anti as a di.sk'changed indicator.
'"

ThE.' drivf' status sig ni'l I is set to LOVV when power is applied !o the

drive., and thereilfler 9vhenever the drive door latch is open(:d and
the dlskette is removed

VS410

Module Detailed Description

3-191

•

is set to HIGH v,ht:!1 a diskette is preeent,
and a step
either direction) is sent

The drive st.atus
the door latch is
to the drive

When the drive has a diskette in it and is ready for operation, the drive status
signal IS
When the operator opens the door latch and removes the
diskette (and when power is first applied)" the status signal is set LO\\" ,
',,"'hen the host program finds the status LOW, it should assume that any
diskette which \vas previously in the drive has been removed, To find out
v,;'hether another diskette has been inserted, the host program must issue 1
step pulse to the drive. If there is still no diskette in the drive . the statt.H'i
siEnal remains LOW. but if it new diskette has been inserted and the door
latch has been dosed," the drive is again ready for operation and the status
signal becmnes 111GB",
The drive status signal is visible to the host program in the READY bit of
the UDC})STAT register. Table 3-31 shows the correspondence bet.\\feen
the signal value and the READY bHvaluE'. This correspondence depends
upon the iNVRDY bit in the t.JDC.RTCNT register.

Table 3-31:

Oiskette Drive Status

Dlive Status

lNVRDY Bli

READY Bit

LOW

HIGH

(;

L()\\'

HIGH

The IT\;'VRDY bit is necessary since the controller
commands to the drive unless READY is 1 In
read and write cO!lunands and to issue a
the drive sta.tus from
to HIGH., the
INVRDY to ma.ke READY a 1,

does net Issue an\'
issue norm,,]
,
to attempt to change
must

a host program performs an operation w-ith an RX33 drive, It snc1uld
test to see which of the foHmving three states the drive is in_
powered on,)

Not Ready {no diskette present or

Ready (diskette present and not {hanged since iast

Changed

3-192

V.AXstaHon 2000

present but possibly changed since !",st

MicroVAX

The first step faft.er ensuring thi'l.t the drive motor is running) IS to set the
INVRDY bit of UDC RTCNT to 1, issue: ih€~ DRIVE SELBel command, and
examine the READ)(bH. If READ)' is 1, there is a diskette in the drive
it has not been changed since the last operation (state 2), so the program
may continue Vvith t.he operation.
If REA.DY is 0, the door has been opened and thE: diskette has been removed
sincE' the last operation, The program should then dear INVRTJY to 0,
reselect the drive (to make the INVRDY change effective and set READY to
1), issue 11 STEP command to the drive (outward, unless it is at track 0 then
it should be inward), and reexamine the READY bit If the READY bit is
now 0, there is a new diskett(~ installed and U1f~ drive is readv (state 3), The
host program can no'",' change II'JV'RDY back to 1, reselect'the drive, and
continue with its read or twite operation, However, if READY is not 0 after
the STEP command, there is either no diskette in the drive or the drive door
is open (state 1).

NOTE: for Iwrd disks, IN"'v'RD'j,' d()es nat affect REAL'Y, Howe!tet. INilI?[)l should
be 0 for compatibility with ellrly madtim:s.

3.S,11 Disk Programming
This section contains hints that programmers should be Envart> of when writ~
ing drivers for the disk controller.
3.8.11.1 Diskette Motor ContrO"
The diskette drive motoflf are turned on and off bv the MOTOR bit in the
UDC. RTCNT register, and bit LOSPEED of that same register selects the
rota.tion speed (300 or 360 rpm) as weit as the data rate. \,Vhenever the
drivel' program starts th(~ m.oi(w or changes its speed. the drive speed must
be aUow{:d to stabilize before the driver attempts to read from or write to
the drive.

Pwduction verSIons of the
drive {pin 30·24962-01, labeled nFD·
55GFV·57~U"J have an automatic lockout feature which
this timing
restriction by suppressing read data from the drive until its motor speed
is
If other diskette drives aI'/;' used lvhith do not ha.ve this lockout
a timt' dd£iV after s\artin~
ft'ature then the drh'ef soltwa.re must
th~; motor or
its
The
required must conform to th~
specification" of
used. h)T example, the minimum times
for prototype
diskette drives without the \{1ckolIt teature afe listed in
Tabh~ 3,32.

VS410 System Module Detailed DescrIption

3-192

Table 3-32: RX33 Prototype Speed Cha.nge Timing Restrictions
Spe-td Changes

Timing Ofla),

".~."-.-----.-".".--.-.----.---"".-."""

•..-,,

...•...

.._------_.-...-.

--~

Start to :reach 30(,') rpm

400 mi1l.iseconds

Start to reach 360 rpm

500 miUiSl?{:(mds

Sreed change (either way)

400 milliseconds

......

__._---_.

_-_._-•._----_._------_._

.•

3.8.11.2 lmplicU Seeks on Diskettes
After a seek operation moves a drive's heads, a settling time is required
before the controller can receive stable data from the drive 10 verify the new
head position and search for the desired sector. For hard disks. "the drive
determines this time by delaying its
complete signal until
heads
have settled. There is no such signal
diskette drives. so the controller
chip attempts to read data immediately after issuing the last step pulse on
diskette drives.

Production versions of the RX33 drive (pjn
labeled "FD·
55GF\'·57·U") have an. automatic lockout feature "vhieh enforces this timing
restrktion by suppressing read data from the drive until the head p0sitinn
has settled. If other diskette drives are used which do not have this lockout
softvv'are must insert i:'l. hend settling delay time
feature, then the
appropriate t.o the parHcular drive
milliseconds mini.mum
for the prototy1~e RX33 drives) after any
motion before
a
write operation, Therefore, the driver must use 11
iD command
to move the he'ads to the desired tr,Kk wait
then
issue !.he READ or WRITE command,
3.8.11.3 Diskette Write Completion Delay
At thE' conclUSion of a \VRITE
WHITE

or
the
DONE bitL the diskette
TRACK command (as signalled
drive requires some additional time to cornpiete Ihe tunnel erasure of the
data
written. Therefore" a deJay is rt:quired before
of the
following:
..

Moving the heads

Deselecting the drive

Changing the selected hea.d number

Stopping the motor

3-194

VAXSlatlon 2000

Technical N~an\Jai

•

Changing the motor speed.

It is important that driver programs observe this delay requirement since
there is no hardware provision to enforce it. The minimum delay times for
the RX33 drive are as follows:
High-speed (RX33 media) 0.59 milHseconds
Low-speed (RXSO media) 1.00 milHseconds.
3.8.11.4 Using the Disk and Tape Controller.
The 9224 disk controller chip, the 5380 tape controller chip, and the disk
data buffer share a common local data bus which is used both by processor
accesses to either chip or to the data buffer, and by DMA transfers between
either chip and the data buffer. Therefore, it is not possible to use both
the disk controller and the tape controller at the same time. Furthermore,
whenever either controller has an outstanding DMA data transfer operation
to or from the disk data buffer, the processor must not attempt to access the
data buffer or any port in either controller chip until the chip signals that
the current operation is done. Otherwise the processor access may colHde
with a DMA access cycle, which corrupts the data transfer for all parties.
One implication of this is that the interruft system must be used by the
controller chips to signal the completion 0 data transfer commands, since
the processor cannot poll a controller chip during such a command.
3.8.11.5 Se.ecting the Diskette Drive
Whenever a DRIVE SELECT command selects the diskette drive and the
drive has not been already selected, there may be a time delay before the
controller can recover valid data from the drive. The disk data recovery
circuit operates at two frequencies, one for hard disks and one for diskettes.
It operates at the hard disk rate whenever either of the hard disk drives or
no drive at all is selected, and at the diskette rate whenever the diskette
drive is selected. When the transition from the hard disk rate to the diskette
rate occurs, it takes up to 70 milliseconds for the data recovery circuit to
stabilize at the lower speed.

)

The implications of this are that for efficient diskette operation, the diskette
drive should remain selected between diskette sector accesses in order to
keep the recovery circuit running at the diskette rate. Once selected, the
diskette drive should not be deselected until a hard disk access is required
or the diskette motor-on period expires. Otherwise, there may be missed
diskette revolutions between consecutive operations on the diskette.

VS410 System Module Detailed Description 3-195

3.8.11.6 Drive Select Jumpers
The diskette drive (addresst':d
the cOfl(wller as drive 10) is
drive selH! line 0 on pin 10 of
34·pin connector. Therefore, the
on the drive should be inserted in position DSO
is n.,(, first of
select lines are numbered
(l through 3
Both hard disk drives are seiected
dri··,:e select line 3 on pin 30 of their 34pin connectors,
the Jumper plug on each drive should be im;ertcd
in position 3 tthis is the third of four posltic'ns). The hard disk. s(dect
are nmnbered from 1 Ihrough 4, The cabling behveen the
module
and the drives maps controHer address 00 to the drive in
box
and controller address 01 to the drive in the
expansion box,

3,8.11.7 Spurious Data CRe Errors
The 9224 disk controller mav indkate a
data
error ,.."hen
reading a diskette sector if it finds an apparent
mark (bit pattern A 1 he:.:
\-vith a missing dock bit) wHhin approximately
bits fcHewing the end of
the
bytes of the data sector. Such a
patterns can be ·created
by diskeUe controllers (111 other systems
write
a one-byte pad
following the CRC bvtes (the 9224 disk controller \\'fites a.
pad),
so this primarily' a interchange

The only solution is to not take diskette data CRe errors ;)t face value, If
a e n o r is slgnalled, the driver software should use thE contents
buffer, which will include the 1:\'\'0
the data,
to recompute the
If
in
buffer, the sector

3.8.12 Diskette Drive Overview
The RX33

drive uses 5.25 inch Ci8ia:tteS fecmded in
dat" rate'!:

frequency modulation (?>lFM) mode ilnd
KHz with standard RX50K .rnedia and 50(\
med!", The (opacities of the diskette are

3-196

VAXslation 2000 and MicroVAX

RXJ3K

Table 3-33: Diskette Capacities

)

Item

Capacities/Speeds

Number of trad<s

Number of heads

Trad< density

96 tpi

Trad< step rate

4 milliseconds per trad<

Medium

RX50K

RX33K

MFM data bit rate

250 kHz

500kHz

Rotation speed.

300 rpm

360 rpm

5I2-byte sectors per track

Data capacity (I·sided)

400k bytes

Data capacity (2-sided)

1200k bytes

The system supports 400k bytes on single sided RX50K media and 1200k
bytes on double sided RX33K media. The system can format the tracks of
an RX33K diskette, but it cannot format an RX50K diskette because the controller cannot omit the index address mark and its associated gaps. Another
reason is because the drive speed tolerance is too great. Refer to the RX33
Diskette Drive Technical Description Manual (order number EK-RX33T-TM) for
more information on the RX33 diskette drive.

3.8.13 Hard Disk Drives

)

The disk controller supports the hard disk drives using MFM recording at a
data rate of 5 megabits per second. Each track is formatted to hold seventeen
512-byte sectors. A drive may have up to sixteen heads and up to 2048
cylinders. The drives that are supported are listed in Table 3-34.

VS410 System Module Detailed Description 3-197

Table 3-34: Hard Disk Capacities
Item

Capadties/Speeda

Model

RD32

RD53

RD54

Data bit rate

5 MHz

Rotation speed

3600 rpm

Capacity

41820K bytes

69632K bytes

156187K bytes

Cylinders

820

1024

1225

Heads

Average seek time

40 milliseconds

30 milliseconds

The RD32 drive is a half-height hard disk device. It can be installed in
conjunction with one RX33 diskette drive in the system box. Two half-height
hard disk drives cannot be installed because their combined motor starting
surge during power-up exceeds the power supply capacity. The RD53 and
RD54 drives are full-height devices. No other drive can be installed with
either of these full.height drives in the system box or in the expansion box.
Refer to the drive technical description manual for more information on the
particular drive.

3.9 5380 Tape Controller
The 5380 tape controller (Figure 3-101) provides an ANSI small computer
system interface (SCSI) between the TZK50 tape controller in the tape expansion box and the data buffer on the system module.

3-198 VAXstation 2000 and MicroVAX 2000 Technical Manual

Figure 3-101: 5380 Tape Controller

)

-VS410 System Module Detailed Description 3-199

The

the

of operation of the tape

an oVtcrvit'\v 01 the
t,'pe bus operati{m, a breakdown
the
th~lt control the tflpe controller, and an
the condition::: that

r"pe

•
•

3.91)

Overview
5380 Tape Controller Chip Hegister (Secti(~n

•

Tape Controller interrupt (Section 3.9.5)

3.9.1 5380 Tape Controller Overview
The tape controller is an NCR 5380 SCSI
chip. It is rrHH"IP"''''
directly to the SCSI
bus (port A on the
adJpter), and H is
also connected to the
data buffer da !.he
buffer data bus. The
5380 is controlled by the
etandard c~'ll. Figure 3-102 shov:s a circuit
diagmm of th~' 5380 tape controller
and Table
Ustsa
of its

3-200

VAXsts.tion2000 and MICfOVA,,~

fv1anua l

Figure 3-102:

5380 Tape Controller Chip Pinout

9"",,-,,---

Ii <lX:}----'
€ (/;>0---'---""""--'
~ ¢U,''·---,------;

4 ~J'--"-------------,-J

Sc,..C~;

--+---+.-

SeSE\.

----+-

r---.~-------I__- sCeSy

SCREO --+-,
SGi/G

----'--+--

SCS;~)Kt
:SCSij\:~;";':

VS410 System Modu!e Delailed DeseripHon

3-20 i

Table 3-35: 5380

Controller

Pinout

.Pin

Signal.

Description

2:9

DBUS7:0

These signals art' th~' SCSI dati'! bus. The SCSI data
bus transfers data 10 and from the 5380 controller and
the TZKSO
controller in the tare expansion bo.x,

DBLISP

This signal is the SCSI dahl bus parity bit.

34:40

!D07:1
IDW

These signals are the internal data l:>u5 . whkh tram·
fers data to and frorn the disk di,la buffer or to and
from the CPU

SCATN
SCI\CK

This signa! is the attenliort bit Of', thf' SCSI

This

is th~ busy bit on tbe SCSI tape bus

This

is the select ht on the SCSI tare bus,

SeESY
SCSEL
SCRSI

This

is the rel1l"t bit on the SCSI tape bus.

'17

sello

.,,,,
~v'

14
·1,J
~

This signal is the
pus.

bus.

f'it on Ihe SCSI tape

This signaJ is the input! output bit on the SCSI wp<'

bus.
IS

seCD

This signal is the command!data bit on the SCSI HIP~

bus.
19

SCMSG

20
1,] ~.
':"'"' ;51

This

is the me"sage bit on the SCSI tate lxlS.

This

is the request bit on the SCSI !apf2 bus.
~re address Enes trse{'~.
cell wheninitiali;rin;l; the

EL.t\D4:2

thE.' CPU ilnd
for Z\ DM;I

l. ransfer.
71"1

... '1

SCSIvVR

This
dard

is the write u)ntro! st:robe from the sian·

SCC:SIRD

This
dare!

is tht' read ()"trol srrl)~<, froTn thr. sL17\'

SCS!CS

This
is the chip seiect o~ntrol !if1l~ from the .st"n·
dard (f·IL

...,/::

~.-'

HEADY

This

SCSH)RQ

n,is signal is the DM.-:>'

is noi used.

cell,'

3-202

VA"<station 2000 and MlcroVAX

line to the slandard

!.~_~~~e 3-35 (Cont:l~,._~~80 Tape~,~.ntroner Chie Pinout
Pin
Signal
Description
23

-------------------------

"
This signal
lS the interrupt request line to the standard

SCSHRQ

eel!,
28

BRESE]'

This signal is the teSl't line from thl;' CPU ch.lp, It is
used during power-up to initialize the 53&:L

SCS1EOP

This signal is. the end of process indicator,

SCSIDACK

This signal is the DMA acknowleagt» line frOID the
standard cell,

_._,-------_._----

-----~-

The disk data buffer is used by both the 9224. disk controller and the 5380
controller during data transfer. The 5380 uses the lower byte (lD07:1DOO) of
the disk buffer data bus to transfer data to and from. the disk da.ta buffer and
the SCSI tape bus, When the 5380 needs to transfer data,. the CPU isolates
the disk buffer dala bus from the other buses by holding aU bus transceivers
in the high impedance state untH the transfer is complete, Only one device
can access the data buffer at the same time. Device driver software must
ensure that only Qne device is allowed to access the data bufter at the same
time.
The SCSI tape bus contains eight data bus 1i.nes, including one parity line,
and nine control Hnes.
A host program can examine and manipulate aU the SCSI signals using the
5380 chip. Associated with the chip is DMA logic, which (an transfer data
between the SCSI tape bus and the disk data DUnee The normal method
operation is for theliasl program to do programmed data transfers for the
command, status, and message phases, ,,,'hieh handle only a few bytes at a
time,. and to set up DMA transfers for the data phases, The 5380 chip ca.n
be used by both initiator and target devices. In this manual, only its U.se as
an initiator is described.

VS410

MOdule Detailed

3-203

3.9.2 SCSI Overview
The SCSI electrical and logical interface and operation is described in detail
in the ANSI draft standard issued by ANSI task group X3T9.2, and the particular subset of that standard used by the tape controller is described in the
TZK50 specification. The programmer must use both of those documents in
conjunction with this specification as his guide. This section reviews a few
important features of the ANSI document to set the context for the following
discussion of the VS410 implementation of the SCSI interface.
The SCSI interface is a bi-directional 8-bit-wide bus to which up to eight
devices can be attached. The system module is one of those devices, so up
to seven additional devices can be attached. Devices may play one of two
roles: initiator or target. An initiator originates an operation by sending a
command to a specific target. A target performs an operation which was
requested by an initiator. In this specification it is assumed that the system
module is always an initiator and that aU other SCSI devices attached to it
are targets. (There is, however, no hardware feature of the system module
SCSI interface which prevents its sharing the bus with a second initiator or
assuming the role of a target.)
Each device attached to the SCSI tape bus is identified by a unique device
ID number in the range 0 through 7. During the arbitration, selection, and
reselection bus phases in which an initiator and a target establish a connection, the device IDs of the initiator and target are both placed on the data
bus by asserting the data bits corresponding to the device ID numbers. By
convention, the 10 number of the system module is O. (The 10 number
of the system module is controlled by the program which drives the SCSI
interface. It is not fixed in system module hardware).
The electrical interface consists of 18 signal lines on a 50-pin connector.
Some of these lines are driven only by initiators, others only by targets, and
others by both initiators and targets. These 18 SCSI tape bus signal lines
are summarized in Table 3-36. The signal names are the same as those
described in the ANSI specification. Table 3-37 lists information transfer
phases associated with the C/O, 110, and MSG tape bus signals.
In all the registers of the 5380 controller chip, the true or asserted value of a
signal appears as a 1, and the false or negated value of a signal appears as a
O. The bus electrical signals are all low true and are driven by open-collector
drivers.

3-204 VAXstation 2000 and MicroVAX 2000 Technical Manual

Table 3-36: SCSI Tape Bus Signal Definitions
Signals

Definitions

OB7:0 and OBP

These signals are an 8-bit parallel data bus with an associated
odd parity bit. The use of the parity bit is optional but strongly
encouraged. These lines may be driven by either an initiator
or a terminator, depending on the direction of data transfer.

RST

This signal flags aU devices on the SCSI tape bus to reset to
their initial power-on states. The system firmware asserts this
signal at least once during power-on self-test. Thereafter, it
should be asserted only as a last resort during error recovery
since it affects all devices on the bus. An RST signal generated
by some other device on the bus causes an internal reset of
the 5380 chip and sets the interrupt request bit (INTREQ in
register SCS.STATUS).

BSY and SEL

These signals are used by initators and targets during the arbitration, selection, and reselection bus phases to establish or
resume a logical connection between an initiator and a target.
Once the connection is established, the target asserts BSY and
the SEL signal is dropped.

C/O, 1/0 and MSG

These signals IXIllective)y indicate one of six possible information transfer phases (see Table 3-37). The signals in Table 3-37
are always driven by the target device.

ATN

This signal is used by an initiator to signal a target that it has a
message ready. The target can receive the message by entering
the message out phase. ATN is always driven by an initiator.

REQ and ACf<

These signals are used to synchronize information transfers
over the data bus during any of the six information transfer
phases. REQ is always driven by the sender of the information
after it has placed data on the OB7 .. 0 and OBP lines. ACf< is
driven by the receiver of the information after it has captured
it from the data lines. The system module supports only asynchronous data transfer in which a sender may assert REQ only
once before receiving ACf< from the receiver. The synchronous
option is not supported.

VS410 System Module Detailed Description 3-205

Table 3-37:

SCSI

Bus Information Transfer Phases

MSC CD

1I0

Phase Name

Data out

To targ{~t

Data in

To initiator

Command

To targf.'t

Status

T () initiator

(reserved)

Message out

To target

Message In

Toi nWato!

3.9.3 5380 Tape Controller Chip Registers
The controller chip appears ttl the system as a group of thirteen 8-bit
ters which are addressed on longword boundaries. Nine ot these registers
contain data bits which can be read and/or l",'ritten by a host pr(lgram. The
remaining four have no datil bits but are action registers. This means that
when the host program reads or writes one of them, the controller chip is

signalled to take some action, but the data bits are ignored. Table 3-38 lists
the thirteen registers in the 5380 chip,

3-206

and

Table 3-38: 5380 Controller Chip Register Addresses
Name
Acceu DeacrIptton
Address
200C.OO88

SCS_MODE

r/w

200C.0084
200C.OO8C
200C.0094
200C.OO9O

SCSJNtCMD
SCS_TARSMD
SCS.STATUS

rfw

SCSSUR.STAT

200C.OO9O
200c.0080

SCS.SEL.ENA
SCS_OUTpATA

Select enable resister

Output data resister

200C.OO8O

SCS.CURPATA
SCS)NPATA
SCSPMA_SEND
SCSPMA)RCV
SCS.DMA.TRCV
SCSRESET

Current data resister

Input data resister

Start DMA send action
Start DMA initiator receive action
Start DMA taqet receive action
Reset interrupt/error action

200c.0098
200C.0094
200C.OO9C
200C.OO98
200C.OO9C

Mode resister
Initiator command resister
Taqet command resister
Bus and status resister
Current bus status resister

rfw
r

w
w
r

3.8.3.1 Mode Register (SCS.MODE)
The mode register is an 8-bit readlwrite register at physical address 200C.0088
that controls the operation of the chip. This register determines whether the
system operates as an initiator or target, whether DMA transfers are being
used, whether parity is checked for SCSI tape bus data, and whether interrupts are signalled for various conditions. Figure 3-103 shows the mode
register.
Figure 3-103:

)

Mode Register (SCS.MODE)
6

IBLOCKIURC IPARCKIINTPARIINTEOplMONBsyl DNA

I I
ARB

VS410 System Module Detailed Description 3-207

Data Bit

Definition

BLOCK

DMA block mode (bit 7). This bit controls the characteristics of the
DRQ-DACK handshake between the 5380 chip and the DMA controller during DMA data transfers. For the system module, this bit
must always be O.

TARG

Target role (bit 6). This bit determines whether the system performs
the role of an initiator (TARG is 0) or target (TARG is 1) on the SCSI
tape bus. The system module normally acts as an initiator, so this bit
should normally be O.

PARCK

Parity check enable (bit 5). This bit determines whether SCSI tape
bus data parity errors are ignored (PARCK is 0) or enabled (PARCK is
1). If this bit is 1 and a parity error is detected, the PARERR bit in
the SCS.STATUS register is also set to 1.

INTPAR

Interrupt on parity error (bit 4). This bit determines whether parity
errors detected on the SCSI tape bus signal an interrupt. BOTH INTPAR and PARCK need to be 1 when an error is detected to signaJ an
interrupt.

INTEOP

Interrupt on end of DMA (bit 3). This bit determines whether an
interrupt is generated at the end of a DMA transfer. If INTEOP is
1, an interrupt is signalled when the DMA count register SCD.CNT
reaches O.

MONBSY

Monitor BSY (bit 2). While this bit is 1, the chip signals an internlpt
upon a loss of the bus BSY signal. When such an interrupt is generated, bits 5.. 0 of the SCS}NISMD register (bits DlFF, ACK, BSY,
SEL, ATN, and ENOUT) are cleared to O. This removes all signaJs
generated by the system from the SCSI tape bus.

DMA

Enable DMA transfer (bit 1). This bit, when set to 1, enables DMA
transfers between the controller chip and the disk buffer. This bit
must be set to 0 for programmed data transfers. Setting this bit to 0
also clears the DMAEND bit in the SCS.STATUS register.
This bit must be set as part of the DMA initialization process which
also includes initializing the DMA controller registers SCD_ADR, SCD_
CNT, and SCD pIR, and appropriately setting the ENOUT bit of the
SCS}NI_CMD register. After this initialization, the host program
must write the appropriate action register (SCSPMA_SEND or SCS.
DMA}RCV) to begin actual data transfers.

3-208 VAXstation 2000 and MlcroVAX 2000 Technical Manual

Data Bit

Defittition
The DMA bit is not deated when the DMA count register SCD. CNT
reaches O. It must be deated by the host program. Once this bit is
deated, no further DMA data transfers occur.

NOTE: The host cannot reliably stop an ongoing DMA transfer by
clearing this bit because the chip's data path may be in use for II DMA
transfer. If so, the host may not able to QCcess the chip's registers.
ARB

Start arbitration (bit 0). The host program sets this bit to 1 to start the
bus arbitration .process. Prior to setting this bit the program should
load the system s device 10 (conventionally bit 0) in the output data
register SCS_OUTpATA. The chip waits for a bus-free condition before entering the arbitration phase. The results of the arbitration may
be determined by reading bits AIP and LA of the initiator command
register SCS)NISMD.

3.9.3.2 Initiator Command Register (SCS-,N,-CMD)

The initiator command register is an 8-bit readlwrite register at physical
address 200C.OO84. It is used when the system is acting as an initiator
(its normal role) to assert certain SCSI tape bus control signals, to monitor
those SignalS, and to monitor the progress of bus arbitration. Bits 5 and 6 of
this register have different definitions according to whether the register is
read from or written to. Therefore, programs cannot use read-modify-write
instructions such as BISB and BICB to access this register. Figure 3-104
shows the initiator command register.
Figure 3-104: Initiator Command Register
7

WD:

1ST
WITE:

AlP

TEST

DIPF

ACK

BSY

SEL

ArN ENOUT

VS410 System Module Detailed Description 3-209

Data Bit

Definiti.on

R5T

Assert RST (bit 7,readiv;'ritel. \I,{hen this trit is changed from 0 to 1
(by writing to the SCS_1Nl_CMD register), the RST signal is asserted,
the chip interrupt request signal is asserted, and ali the
intermI.! logic and control registers are cleared (except for this
and the
interrupt request latch). While this bit is 1, the RST signal is asserted
on the SCSI tape bus, Writing a 0 to this bit negates the RSTslgnaL
Reading this bit reflects only its value in the SCS)Nl_CMD register
and not necessarily the actual bus signal state.

AlP

Arbitration In progress {bit 6, read-only}, This bit when set !.01,
indicates the bus arbitration is in pwgress. In order for this bit to
be set, the ARB bit in SCS MODE must also be set. .A. 1 in the ,:',If>
bit indicates that a bus free ~ condition bas been detected and that the
the chir has asserted BSY and the contents of the SCSOUT
regjster onto the SCSI tape buS, AlP remains set until the
bit in
SCS MODE is cleared.

TEST

6, write-onlYI. Setting tl'lJs bit to 1 disables an the
Test mode
output drivers, effectively removIng the
module from the
tape bus, Note that setting this bH may generate SFurious Dl'>1A
requests or interrupts to the CPU
therl"tcre, the use of this bit
is not recommended. This bit must
0 for normal. operation,

Lost arbitration \bit ;, read-only),. This bit, when set to 1, inc'Jeates
that the chjp detected a bus-free condition, arbitrated fDr use of the
bus by asserilng BSY and the system's ID (11'1
on the
bus, but lost the arbitration because SEt was asserted

DlFF

device on the bus. T:"1e U\ bit ,can
of SCS MODE is set,

be asserted

Differential. enable
tern,

Must

',j!

!:Ie (1 in this sys-

4, re3ciiwdte}, 'N1,He Ihis !:tit IS 1 the ACK Bignal
OtiS This bit is eHecHve
while the

ACK

state

as'{

3-210

Assert BSY
), readiwrl\e). Wh1ie this bil 1.$ 1, Hw BSY
ls
.asserted on tht' SCSi
BSV indicates a su:::cesstu\
selection or l'€selection,
BSY bit
the BSY
which indicates a bus
only its value i.n \.he
tht, actual l~u~
sin te.

VAXstatiol1

and Micro\lAX

Manua!

Data Bit

Definition

SEL

Assert SEL (bit 2, read/write). While this bit is 1, the SEL signal is
asserted on the SCSI tape bus. SEL is normally asserted after arbitration has been successfully completed. Writing a 0 into the SEL bit
negates the SEt signal. Reading this bit reflects only its value in the
SCS)NISMD register and not nea!SSlU'ily the actual bus signal state.

ATN

Assert ATN (bit I, read/write). While this bit is 1, the ATN signal
is asserted on the SCSI tape bus. This bit is effective only while the
TARG bit of SCS.MODE is 0 (that is, when the system is acting as an
initiator). Writing a 0 to the ATN bit negates the ATN signal. Reading
this bit reflects only its value in the SCS)NI.CMD register and not
necessarily the actual bus signal state.

ENOUT

EnabJe output (bit 0, read/write), This bit, when set to 1, allows the
contents of the SCS.OUTPATA register to be sent out on the SCSI
tape bus. When operated as an initiator (i.e. the TARG bit of SCS_
MODE is 0), the outputs are only enabled while the bus 110 signal is
false and the three bus phase signals CID, 1/0 and MSG match the
contents of the corresponding bits in the SCS.TAR_CMD register. The
ENOUT bit must be set to 1 during DMA operations which send data
out to the SCSI tape bus.

3.9.3.3 Ta,.et Command Re.iate, (SCS.TAR.CMD)
The target command register is an 8-bit readlwrite register at physieal address 200C.OOSC. When the system is acting as an initiator (its normal role),
this register is used during DMA data transfers (i.e. when bit DMA of the
SCS.MODE register is 1) to monitor the bus rhase. When a target asserts
REQ to request a data transfer, if the state 0 the bus MSG, CID and 1/0
signals does not match the values of those bits in this register, a phase mismatch interrupt is generated. This enables the host program to be notified
when a DMA data transfer is ended by the target (this may occur prior to
the DMA counter's reaching 0, since the target controls the length of data
transfers). In initiator mode, the REQ bit in this register is ignored.
When the system is used as a target device (the TARG bit in SCS_MODE
is 1), this register allows a program to assert the REQ, MSG, CID and 110
signals on the SCSI tape bus. Figure 3-105 shows the target command
register.

VS410 System Module Detailed Oescrlption 3-211

Figure 3-105: Target Command Register

REQ

MSG

C/D

I/O

3.9.3.4 Bus and Status Register (SCS_STATUS)
The bus and status register is an 8-bit read-only register at physical address
200C.0094. It contains six chip status flags and monitors two of the SCSI
tape bus control signals, ACK and ATN. The other seven bus control signals
are visible in the current bus status register (SCS.cUR_STAT). Figure 3-106
shows the SCSI tape bus and status register.
Figure 3-106:
7

SCSI Tape Bus and Status Register
664

3-212 VAXstation 2000 and MlcroVAX 2000 Technical Manual

Data Bit

Definition

OMAENO

OMA end (bit 1).
This bit Is set when the OMA count regAfter this
ister SCO_CNT becomes 0 during a data transfer.
bit is set, the chip performs no additional OMA cycles.
The
OMAENO bit is cleared when the OMA bit in the SCS_MOOE register is cleared.

OMAREQ

OMA request (bit 6).
This pin reflects the status of the inter.
nal OMA request signal from the 5380 chip to the OMA controller.
This bit becomes 1 when the chip requests the transfer of a byte to or from the disk buffer, and returns to 0 when the OMA controller has performed the transfer.

PARERR

Parity error (bit 5). This Nt is set upon receipt of a byte with incorrect parity from the SCSI tape bUll during a data transfer to
the system or during device selection.
P.ARERR is IIt't only if
the PARCK bit of the SCS.MOOE register is set to 1 to enable parity checking. PARERR is not set while PARCK is O. The PARERR bit is cleared when the reset interrupt/error register SCS.
RESET is read.

JNTREQ

This bit is set when any of the InInterrupt request (bit 4).
terrupt conditions described in Section 3.9.5 occurs. It is cleared when the reset interrupt/error register SCS.RESET is read.

MATCH

Phase match (bit 3).
This bit is 1 whenever the three SCSI tape
bus phase signals MSG, C/O, and 1/0 match the values in the
corresponding three bits of the target command register SCS.TAR.
CMO. The MATCH bit is continuously updated and is only significant when the system is operating as an initiator (its normal mode).
MATCH must be 1 for data transfers to occur on
the SCSI tape bus.

BSYERR

Busy error (bit 2). This bit is set whenever the MONBSY bit ofihe mode register SCS.MODE is 1 and the SCSI tape bus BSY signal is false. This feature is used to monitor the bus for an unexpected loss of the logical connection between the system (as initiator) and a target device.
When BSYERR Is set, the OMA bit in the mode regiSter SCS.MOOE is cleared to stop any OMA data transft'rs, and
the OlfF, ACK, BSY, SEL, ATN and ENOUT bits of the SCS.
INtCMO register are deared to remove all signals generated by the system from the SCSI tape bus.

ATN

ATN signal (bit 1). This bit reflects the current state of the ATN signal on the SCSI tape bus.

ACK

ACK signal (bit 0), This bit reflects the current state of the ACK signal on the SCSI tape bus.

VS410 System Module Detailed Description 3-213

3.9,3,5 Current Bus Status Register (SCS.CUR.STAT)
The current bus status register is an 8·bit read-only register at physical ad·
dress 200C.0090, 1t is used to monitor seven of the SCSI tape bus control
signals plus the data bus parity bit. The other trNO bus ('ontrol signals,
and ATN, are in the bus and status register
.STATUS). The host pro·
gram uses the current bus status register 10 determine the current bus phaS'::
and to poll I<EQ during pr{~grammed data transfers from the system to a
targt~t de'lice. This register is also used 10 heip determine why a particular
interrupt occurred. Figure 3~ 107 shows the current bus status register.,
Figure 3-107; Current Sus Status Register
7

RST

as\'

432

I/o

SEL

DBf

REQ:I MSG

C/D

3,9.3.6 Select Enable Register (SCS.SEL,ENA)
The select enable register is an B·bH ",,;rite·only register at physical addres~
200C0090. It contains the device ID of the 5vstem module, The
module should recognize this m as Hs o\vn duiing a selection or
attempLFor a VS410 system whose device lOis normally {) this
should contain Ii 1 in bH 0 and (\'s els€'.vhere,
The simultaneous occurrence of the correct TD bit on the data bus,
;lad SEL true (during a selection or reselection
interrupt
Such interrupts can be disabled by
If parity checking is enabled (lhe PARCK bit in
rnode register
_MODE is
the piuity of the data on the data bus is checked during
selection or reselectiol'l.. Figure 3-108 shows the
enable register.

Figure 3-108:
7

Select Enable Register (SCS.SEL.,.ENA)
5

[~B7 ! DB~] DB;

DB4

DRS

3-214

DB2

VAXslation .2000 and Micro\iAX20GO

PBt

DBO

Manua!

3.9.3.7 Output Data Register (SeS.OUT.DATA)
The output data register is an S-bit write-only register at yhysical address
200c.00'SO. It is used to send outgoing data to the SCS tape bus. It is
used during programmed 1/0 to write outgoing data bytes and to assert the
proper ID bits on the SCSI tape bus during arbitration and selection phases.
This register is also implicitly used by the hardware during DMA transfers
to the SCSI tape bus. Figure 3-109 show the output data register.
Figure 3-109: Output Data Register
1

43210

I DBT lOBe I DB6 DB4 lOBS I DB2 I DBl lOBO I
3.9.3.8 Current Data Register (SCS.CUR.DATA)
The current data register isanS-bit read-only register at physical address
200c.OO80. Its contents reflect the data currently on the data lines oflhe
SCSI tape bus. It is used during programmed (rather than DMA) 110 to
read incoming data bytes and during arbitration to check for higher priority
arbitrating devices. Figure 3-110 show the current data register.
Figure 3-110: Current Data Register (SCS CUR DATA)
T

I DBT I DB6 I DB6 I DB4 I DBl I DB2 lOBI I DBO I
3.9.3.9 Input Data Register (SCS)N.;DATA)
The input data register is an 8-bit read-only register at physical address
200C.OO98. It is used to read latched data from the SCSI tape bus during
DMA operation. During programmed 1/0 operation, no data is latched
in this register. The SCS.CUR.DATAregistershould be used instead for
programmed 1/0. The input data register is implicitly used by the hardware
during DMA transfers from the SCSI tape bus. When the system is acting
as an initiator (its normal role), data is latched when the bus REQ signal is
asserted by the target device. When the system is actinf as a target data is
latched when the bus ACK signal is asserted. Figure 3- 11 shows the input
data register.

VS410 System Module Detailed Description

3-215

Figure 3-111:

Input Data Register (SCS.IN.DATA)

DB7

DB6

DBS

DB4

DBS

DB2

DBl

DBO

3.9.3.10 Start DMA Send Action (SCS DMA SEND)
>

The start DMA send action register is an 8·bit write-only register at physical
address 200C.0094. The act of writing to this register begins DMA transfers
from the system disk buffer to a target device. The data written to this
register is ignored. Prior to writing to this register, the DMA controller
registers SCD.ADR and SCD.Cm must be loaded, the DIR bit of the SeD.
DIR register must be set to 0, the ENOUT bit of the INI.CMD register must
be set to 1, and the DMA bit of the SCS.MODE register must be set to 1.
3.9.3.11 Start DMA Initiator Receive Action (SCS.DMA)RCV)

The start DMA initiator receive action register is an 8-bit write-only register
at physical address 200C.009C. The act of writing to this register begins
DMA transfers from a target on the bus to the system disk buffer. when the
system is acting as an initiator device (its normal role). The data written to
this register is ignored. Prior to writing to this register. the DMA controller
registers SCD.ADR and SCD.cm must be loaded. the DIR bit of the SCD_
DIR register must be set to 1, the ENOUT bit of the INI.CMD register must
be set to 0, and the DMA bit of the SCS.MODE register must be set to 1.)
3.9.3.12 Start DMA Target Receive Action (SCS DMA TRCV)

The start DMA target receive action register is an 8-bit write-only register at
physical address 200C.0098. The act of writing to this register begins DMA
transfers from an initiator on the bus to the system disk buffer, when the
system is acting as a target device (not its normal role). The data written to
this register is ignored. Prior to writing to this register, the DMA controller
registers SCD.ADR and SCD_cm must be loaded, the DIR bit of the SCD.
DIR register must be set to 1, the ENOUT bit of the INISMD register must
be set to 0, and the DMA bit of the SCS.MODE register must be set to 1.
3.9.3.13 Reset Interrupt/Error Action (SCS.RESET)

The reset interrupt/error action register is an 8-bit read-only register at physical address 200C.009C. The act of reading this register clears bits PARERR
(parity error), INTREQ (interrupt request), and BSYERR (busy error) in the
bus and status register SCS.STATUS. No useful data is returned from reading this register.

3-218 VAXstation 2000 and MicroVAX 2000 Technical Manual

3.9.4 DMA Register Operation
This section describes registers associated with the DMA transfer operation.

3.9.4.1 DMA Address Register (SCD.ADR)
The DMA address register is an 8-bit write-only register at physical address
200C.00AO. It is used to set the starting address in the disk buffer for the
next DMA transfer. Figure 3-112 shows the DMA address register.
Figure 3-112: DMA Address Register (SCD.ADR)

FIRST WRITE:

SECOND WRITE:

BUFFER ADDRESS 13: 8

BUFFER ADDRESS 1: 0

Since the disk buffer contains 16K bytes, the required 14·bit starting address
must be loaded by two consecutive writes to SCD.ADR. The first write sets
bits 13:8 of the starting address from bits 5:0 of the data byte. The second
write· sets address bits 7:0 from bits 7:0 of the second data byte.
This register must not be accessed while a DMA operation is either pending
or in progress for either the tape controller or the disk controller, since both
controllers use the same address register.

NOTE: Two consecutive wrifes to SCD.ADR always load the address correctly, even

if a previous single write to SCD.ADR only parfill1ly sets the address. Each write

to SCD.ADR moves the confents of btlffer Address bits ]:0 into bits 15:8 and tlren
loads bits 7:0 from the data presented by the write operation.
3.9.4.2 DMA Count Register (SCD.CNT)
The DMA count register is a 16-bit read/write register at physical address
200C.00CO. It counts the number of bytes transferred during a DMA operation and signals the tape controller chip when the specified number of
bytes have been transferred. This register should be loaded with the 16-bit
2's complement of the maximum number of bytes to be transferred by the
next DMA transfer between the tape controller chip and the disk data buffer.
This counter is not used for and is not affected by DMA operations between
the disk controller and the disk buffer. Figure 3-113 shows the DMA count
register.

VS410 System Module Detailed Description 3-217

Figure 3-113:

DMA Count Register (SeD.eNT)

BYTE' COUNT (T~O'B COM?L'EMENT)
As each byte is transferred, SeD CNT is incremented bv 1, When
eNT changes from ·1 to 0, a counter overflow bit is set ~nd the
con:
troHer chip 1S signa.lled through its EOF pin to terminate D.lviA operation at
the completion of the current byte transfer (that is, the transfer during l'vhich
the counter becomes m This sets the DMAEND bit in the SCS STATUS
register.'
•

\\'h.ile the counter overflow bit is set, the DMA controller does not per.,
form data transfer:o:, The counter overflo'l-v bit 15 cleared ,vheHever the count
register is loaded by writin.~ to SeD CNT If a transfer request is pending
(the Dl\fAREQ bit of the SCS.STATuS register is true) when the counter is
loaded, a transfer o(cutsat once, Therefore, when restarting a O1'\'1A transfer, the host program must first load SCD.ADR and SCDpm and then load
SeD
with a single \vord write.
reached 0 or because
After a DMA operation ends (either because SCD.
the tap<: (on toller chip sensed a bus phase change), the host program may
read SCDSNT to get the number (in 2'5 complement form) of bytes not
transferred. Adding this to the true form of the count originally
tnmsfened This
into SCD. (NT gives the number of bytes
must not be read or wrHten '\'hile an Dl'vfA
is either
in
At
and its overflol'v bit are cleared to

NOTE: There is an intemcUon h:twem the
Tile contcnfs

read the nmtents of

CNT

HtTCOD must he' 0 ;/!len:cuer a
(lthaw!:;;e fht' vahu:: receil'ed may

wlllerlis
HLTCOJ) do tk1t affect pn.'gmm
actual DA<fA

_(NT, (Hid do nol

3-218 V,AXsiatlon 2000 and MicroVAX 2000 Technical Manual

3.9.4.3 OMA Oifection Register (SeOOlR)
The DMA direction register is an 8-bit v."rite~only register at physka.l address
200COOGt It controls the direction in whkh data is transferred during DMA
cycles requested by the tape c(mtroUer chip. Figure 3~114 shows the LIMA
direction register.
Figure 3-114:
7

DMA Oirectton Register
3.

I: : ~: :
Data Bit

Definition

7:.1

Reserved. Must aJwaysbe written 8S G's.

Tr~nsfli'r direction {bit OJ ,",vhen this bit. is t DMA cyde!! transfer
data from the SCSI tape bus into the disk buffer (J! READ operation)
\"/hen. this bit is O. DMA cydef> transfer data from the disk buffer
to the SCSI
bu~ Iii vvRITE operation). Upon power-on, DIR .is

cleared In O.

3.9.5 Tape Controller Interrupts
The 5380 chip has one interrupt request signal which is sent to the CPU
through the system interrupt controUer. The state or this signal is visible in
the INTREQ bit of the SCS_STATUS register. An inferrupt request can be
signalled by any of the following six events.
•

The controller IS selected or res elected by another device on tlU':
tape bus.
.

The OtvfA C(lunt register reaches O.

•

A bus phase mismatch occurs.

The RST signal is asserted on th~:

e.rror is dct('cted during data transfer.

tape bus

VS410

occurs.
bus.

Module Detailed Description

3-2Ht

prclgrafn responds to the interrupt il must u~e the contents
of the
_STATUS and sCs~CUR_STAT registers tQ determine ,,,,,hat om
ditlon(s) caused the interrupt Once it has senriced the interrupt, the
program must read the sCS_RESET register to reset the INTHEQ bit Each
of the above interrupts cause an except receipt of the RST signal and can
individually masked by appropriate
of the 5380 chip registers.

In order for the 5380 interrupt signal to cause a CPU intem,pt, the SC bit
of the interrupt mask register INTJ\1SK must be seL Section 3,5.9,4 lists
the value of the tape controlJer's interrupt vector
3,9,5,1 Selection or Aeselection
An intermpt can be signalled when another device on the SCSi tape bus
attempts to select or resdect the system module, in. the system's normal
role of an inii.iator, the system module may be reselected by a devke to
\vhkh it has previously issued a cornmand, Selection is a.ppropriate only jf
the
is acting as a target Such an
occurs when the following
are met.

•

The SEL signal is true,

•

The Bsy signa! is false for at least a bus settle delay

•

The logicaJ AND of each data bus bit, DB7:(),.with the correspondjng
bit in the select enable
SEL.ENA, are 1.

The intermpt service routine can identify this
of interrupt by
that BSY is 0 and SEL is 1 in the SCSSUR_
register. If the 110 bit
SCSSUR STAT is 0 this is a select attempt Othervvise it is a reselecL The
SCS_ SEL_
register should contain a 1 only in the bitC'orresponciing to
the
SCSI de'vice ID (normaH." bit QI and
in the other .,even bits.
Oniy two bits should be ass'erted
the SCSI data bus during selection
or reseiection; they are the lD of the initiator and the ID of the target.
The host program should check this
examining the data bus through the
<CUi~PATA register. In addition, if bus parity is enabl~d
PARCK
of SCS MODE is true}, then the parity error bit PARER.R in
STATUS

should

tested as welL

Sele(tlcln and
of

interrupts can be prevented.

ENA to 0,

3-220 VAXstalion 2000 and MlcrcVAX 2000

3.9.5.2 OMA Count Reaches, 0
An interrupt can be signalled. when the D.l\,1A count register
'"
reaches 0 during a DMA transfer, Suchan interrupt occurs when trw fol·
}c"'...'ing conditions a.Ie met
The DMA bit in Ihe SCS_MODE register is set.

A D1'.'1.1\ transfer to or ft(lm the disk buffer occurs. during which the
count
SCD
reaches O.

.. The INTEOP bit in the SCS,MODE register is seL
If the first hvo conditions are satisfied, the DMAEND bit in the
STATUS register is set If all three conditions are satisfied, INTREQ is
also set in SCS STATUS.

Note thal when m. 1AEl'~D is set the system DMA controller performs no
additional transfers, but the. target's block transfer is not necessarily complete. When the system operates as anmitiator, it must test the MATCH bit
in SeS,STATUS to determine when the target has completed its data block.
In addition, when sending data to the target, the system must monitor REQ
in ses CUR STAT and ACK in ses STATUS until both are false, to be sure
that the last byte has been transfem-;d.
3.9.5.3 8us Parity Error
The 5380 chip can signal an interrupt when it detects invalid parity in dala
received from the SCSI tape bus. Such an interrupt is generated when the
folloll'.ing conditions are met

•

The PARCK bit in the SCS),10DE register is set.

•

Invalid parity is detected during it Dlv1A transfer from the SCSI tape
bus to the dIsk buffer, or during a processor read of the
CUR
DATA register.

The INTPAR bi! in the SCS}'viODE register is set.
tv."o conditions are satisfied., the PARERR bit in the SCS
is seL If all three conditions are satisfied, INTREQ is

ATtiS
set in

VS410 Sysrem Module Detailed Description

3-221

3.9.5.4 Phase Mismatch
The chip can signal an interrupt whenever the three bus phase signals MSG,
CIO, and 1/0 do not match the corresponding bits in the SCS.TAR.CMD
register during a DMA data transfer. The match state is continuously reflected in the MATCH bit of the SCS.STATUS register. The interrupt is
signalled when all of the follOwing conditions are met.
•

The MATCH bit in SCS.STATUS is O.

•

The DMA bit in SCS MODE is 1.

•

The bus REQ signal is asserted to request a data transfer.

The identify status for such an interrupt is that DMA is 1 in SCS_MODE and
that DMAEND and MATCH are both 0 in SCS STATUS.
3.9.5.5 Bus Disconnect
The chip can generate an interrupt when the SCSI tape bus BSY signal
becomes false. Such an interrupt is generated when the following conditions
are met.
•

The MONBSY bit in SCS MODE is 1.

•

The bus BSY signal goes false for at least 400 ns.

This condition sets the BSYERR bit in the SCS.STATUS register.
3.9.5.6 SCSI Tape Bus Reset
The chip generates an interrupt whenever the RST signal on the SCSI tape
bus is asserted, either by another device on the bus or when the host program sets the RST bit in the SCS}NI.CMD register. When a reset occurs,
the chip releases all bus signals within 800 ns. This interrupt cannot be
disabled.
Note that the RST signal is not latched in the SCS.CUR.STAT register. So
the RST bit may not still be set when the host responds to an interrupt which
was caused by RST from another device on the bus.

3-222 VAXstation 2000 and MicroVAX 2000 Technical Manual

3.9.6 Reset Conditions
The three possible reset conditions for the 5380 chip are described in the
following paragraphs.
3.9.6.1 System Hardware Reset
At system power-on or when the system I/O reset signal is. generated (SE'c'
Hon 3,1 1.3), the 5380 chip is reinitialized and ali lntermd logic and control
registers a!e deared. AU signals are removed from t.he SCSI tape bus. This
does not a.ssert the RST signal on the SCSI tape bus.

3.9.6.2 RST Received from SCSI Tape Bus
When the RST signa! is ass_erted on the bus by somE:' other device . a.!l the
5380 internal logk and registers are cleared, except that the interrupt request
signal is asserted
Iy\:"TREQ of BeS_STATUS) and the RST bit of the SCS_
INI_CMD register nol altered.
3.9.6.3 RST '$Sued to SCSI Tape Bus
When the host program asserts RSi on the SCSI tape bus by setting the RST
bit in the SCSJNI~CMD register, all the 5380 internallQgic and registers are
(leared, except that the interrupt request 5i.s,nal is asserted ,(bit INTR?Q
of BeS.STATUS) and the RST bIt of the ScS}NlSMD regIster remams
asserted until deared by the host program or by a system hardware reset.

3.9.7 Programming Notes
This section contains hints that programmers sliould be aware of when \\'Titing drivers for the tape controller.
3.9,1.1 USing the Tape and Disk Controllers
The 5380 tape controller chip. the 9224 disk controller chip, and the disk
data buffer share a common local data bus. This bus is used both by processer accesses to eHher chip m t\:> the data buffer, and by DM.A tranSfef'l
between either chip and the data buffer Therefore, it is not possiblt> to u:\'e
both the tape controller and thE;' di:sk controller al the same time. Further
an outstanding data transfer operaticn which
whenever either controUer
will perform DMA transfers 10 or from the di$k data buffer, the
must not attempt to access the data buffer or any register in either controller
chip until the chip signals that the current operation is done. ()therwis{' fh(;
processor access may coHide \\lth a D~\·fA acceS$ cycle, which wm
Ihe data transfer for all partit'S One implication of this i$ that the interrupt
system must be used
the cordroHer chips to signal the ('ornplE!tion of data
transfer commands. since the
cannot poB a controller chip during
such a

VS410 System Module Detailed Description

3-223

3,9,7.2 Device to Values
The SCSI device ID numbers shov.m in Table
are aSf)igned by conven·
tion to theVS410 CPU on the system module and an attached TZK50 tnpe
controUec For the CPU, this is done in its device driver code. The TZK50
tape controUer requires that jUl1"1pers be set on its board, as described in the

TZK50/SC51 Controller Teclwicrli MaHual.

Device to Values

Table 3-39:
V~vke

IV number

CPU

TZK50

01 hex

02 he-:.:
-------------.--------~,,-

In addition, both the CPU and TZK50 should assert and test parity on the
SCSI tape hus. This is done tor the CPU by asserting the PARCK bit in the
SCS.MODE register. The TZK50 tape controller requires that a jumper be
set on its module, as described in the rZK50i5CSJ Controller TechuicalA-1mmal.

3.10 ThinWire Ethernet Circuits
The only portion of the Thin Wtr~ Ethernet netvvork circuitry that. is not Oli the
neh'Vo.rk option module is the transceiver circuitry. The transceiver circuitry
is located in the upper right corner of the system module lsee Figure 3·11S).
it consists of the coaxial cable connector, the coaxial transceIver interface
chip, and the isolation transformer. Figure 3·116 shows a block diagram of
the transceiver circuitry on the system module.

3-224 VAXstatlon 2000 and MicroVAX 2000 Technical '\i1anual

Figure 3-115: Transceiver Circuitry on System Module

/4"_-'

I I

,L!
f-'
1

I
\

Module

w
I

ThinWire Ethernet Transceiver Circuitry

Figure 3-116:

flo)
flo)

-til
S»

c:::J;"
N
0
0
0

S»

:::J
0..

...o·
0

<
~
N
0
0
0

-I

(I)

:::J

o·

!!.
3:
S»

:::J
C

!!.

ETHERNET
COAX
CABLE

I I

I I
I 1-9

J14

..., RECEIVER

I
j
I
-9

TRANSMITTER

t±1l11~ I~;~"

Fflljll~ ~:"SMIT

Vdc

Vdc Return

COLLISION
DETECTOR
DP8392

CTI

36
37
38

33
COLLISION
PAIR

ISOLATION
TRANSFORMER
CTI CHIP

I.IA-X06.·Q-87

3.10.1 Coaxial Transceiver Interface
The coaxial transceiver interface (CTI) is a DP8392 chip It 1$ used as the
c.oaxial cable line drIver and receiver for the Thi.nWire Ethernet local area
n.etwork The CTI contains a tran.smitter. receiver, collision detector, and a
jabber timer. Figure .3-117 shows the D1'8392 (-:TI chip and Table 3-40 lists
a description of the pins,
Figure 3-111:

Coaxial Transceiver Interface Chip Pinout

DP839;(

CD'S

HEE

Rx.!

1':1(+
1"K-

RR+
RR-

1 1 -

CfH

3 (,

RX+
R)(-

T)(O

CD-

VEE
ON;)

VS41C

Module

Descr!ptlon 3-221

Table 3-40: Coaxial Transceiver Interface Chip Pinout
Pin

Signal

Description

1
2

CD+
CD-

These signals are the balanced differential line driver outputs
from the collision detect drcuitry.

3
6

RX+
RX-

These signals are the balanced differential1ine driver outputs
from the receiver.

4,5,13

VEE

These signals are the power supply connections to the chip.
VEE is -9 Vdc.
These signals are the balanced differential line receiver inputs
to the transmitter.

TX+

TX-

HBE

This Signal enables the collision detector heartbeat since it is
asserted (grounded).

GND

This signal is the -9 Vdc return to the power supply.

11
12

RR+
RR·

These signals are connected to each other by a resistor to establish the operating currents within the chip.

RXI

This signal is the receive input from the coaxial cable.

TXO

This signal is the transmit output to the coaxial cable.

CDS

This signal is the ground sense connection for the collision
detect drcuit.

3.10.1.1 Transmitter

The transmitter section of the CTI consists of a differential line receiver and a
current driver. The differential line receiver receives the transmit data from
the network option module through an isolation transformer. The driver
outputs the transmit data onto the coaxial cable.
3.10.1.2 Receiver

The receiver section of the cn consists of four function blocks. They are
the equalizer, a squelch circuit, an AC coupled comparator, and a differentialline driver. The equalizer filters the incoming signal to compensate for
the phase bias distortion from the coaxial cable. The squelch circuit prevents any noise on the coaxial cable from falsely triggering the receiver in
the absence of the signal. The compensated signal is AC coupled to reduce
slicing errors that can lead to a phase distortion. The output of the comparator then feeds to a differential line driver which sends the received data
to the network option module through an isolation transformer.

3-228 VAXstation 2000 and MicroVAX 2000 Technical Manual

3.10.1.3 CoUislon Detector
The collision detection circuitry consists of a lew,' pass filteT, a voltage It,rer·
and a differential im£::' driver . The low pass filter
('nee, a 10 !I..fHz
is used to delermine the DC voltage level of the signal on t.he coaxial
When a coUlsion occurs, the output of the filter exceeds the reference volt·
age, and a 10 MHz osdUator collision sigr..al is generated. The signal first
passes ont.o the fine driVl~r a.nd then through an isolation transformer bdore
it arrives at the netv.:ork option module.
3.10.1.4 Jabber
jabber cirCUitry
as 11 watchdog tiJm~r to terminate
legal length data packets by disabling the transmitter. Tht~ collision
then asserted to in.dkate this condition to the neh'.;crk option module.
the nehvorJ: module terminates the transrnissi,m, the Jabber is autornaticaHy
reset after a time deli'l)'. The
is also reset at

3.10.2. Network Address ROM
A 32·byieROM on the system modUle (ontains a unique nern'or~; address fot
each system. The physical address each system is de.termlned at the time
of manufacture. Data from this ROt.1 is read in the low-order bytes of (onsecutive long-words al. physical addresses 2009,0000 through 2009JHJ7C The
network address occupies the first six bytes (addresses 2009.0000
2009.(014). The bvte at 2009.0000 is the first bvte to be tra.nsmitted or re
ceived in an address field of an Ethernet packet. Its low-order bit: (bit
'
transmitted or received first in the serial bit stream, This ROM is
in a socket SO it can be removed from a faHlng system module and installed
on the new system module.

3.11 Miscellaneous System Registers
This section describes three miscellaneous syst.em registers and (lDe
strobe dda}' Un£:'

Detailed DescrlpfilJr'

3-229

3.11.1 HALT Code Reg.ister (HLTCOD)
The ha.lt c{)cie register (HLTCOD) is a readlwrite jnngvJ(ltd regif3ter at
cal address 2008JJOOQ, It is intended for use bv the ROM~resident firmwZl.re
program which handles a processor restart this program moves internal
processor register SAVISP to HLTCOD so that the restart
can
extracted without accessing any
processor's
registers or
RAM locations, Figure 3~·n8 shows the halt code register,

Ffgure 3-118:

Halt Code Register (HLTCOO)

NOTE: There is fm Interaction between the
in Section 3.9.4,2), The contents

ulhenever a program attcllipts to read the colltellfs 0/ seD_

received may be in error. The contents of IlL TeOD do not
and do not affect ~1ctUQi Dl\ifA operation.

3.11.2 Configuration and Test Register (CFGTST)
The configuration and tE'st register (CFGTST) is a read,only byte regisler at
address 2002.0000, This
is a tri~stat{' octal driVer that stores
InJormatton as whether this
or a
and which option slots contain option modules~
by the SYSREGEN L
the
.
inforrm~tion IS driven on
Figure 3~119 shmvs the configuration and test
NOTE: Ihc
3,11

address ({:ith Utf I()nrSET
10
iic to Ihe CfCTST

since this '{(nil

3-230

V.A.Xstatlon 2000 and MlcroVAX 2000 Tecnnica.!

Figure 3-119: Configuration and Test Register (CFGTST)
766

IMULTU INITOPT IL3CON

)

ICUlTEST IVIDOPT \

HTTPI

Data Bit

Definition

MULTU

MulU-char user (bit 7). This bit is set by Jumper W6 on the system
module. It is a 1 when the system module is used in a MicroVAX
2000 system. This bit is a 0 when the system module is used in a
VAXstation 2000 system.

NETOPT

Network option present (bit 6). This bit is 1 when a board is present
in the network option module connector.

L3CON

Une 3 console (bit 5). This bit is 1 when pins 8 and 9 of the
printer connector are connected together by the BCC08 console cable. This bit is 0 when pins 8 and 9 are not connected together
(BeCOS printer cable or no cable is connected).

CURTEST

Cursor test (bit 4). This bit is the complement of the Test pin
output from the monochrome video cursor chip.

VlDOPT

Video option present (bit 3). This bit is 1 when a module is present
in the video option module connector.

MTYPE

Memory option type (bits 2:0). These bits indicate the size of memory option module (if any) inserted into the memory option module
connector. The values of the data bits are listed below.

Value

Definition

000

No board present

001

1024 Kbytes

010

2048 Kbytes

011

4096 Kbytes

100

Reserved

101

Reserved

110
111

Reserved
Reserved

VS410 System Module Detailed Description

3-231

3.11.3 1/0 Reset Register (IORESET)
The 110 reset register (IORESET) is a write-only byte register at physical address 2002.0000. Any write access to this register generates a reset signal to
the following four controllers (the data contained in this register is ignored).
•

9224 disk controller chip (Section 3.8)

•

5380 SCSI bus controller chip (Section 3.9)

•

Network controller option (Chapter 5)

•

The controller installed in the general purpose option port.

NOTE: Consult the indit'idual sections for details of the effects of writing to IORE-

SET. Also note that the CPU, FPU, interrupt controller, and serial line controller
are not affected by the IORESET.

3.11.4 Address Strobe Delay Line
Address strobe timing for the memory chips due to the bus delays may not
be present when needed by these circuits. The address strobe delay circuit
holds the address strobe for 50 ns after the first dock pulse of CLKO is
received following the assertion of AS. The product of this delay circuit is
called a buffered address strobe (BASI). This allows BASI to stay asserted
50 ns after AS is deasserted.

3.12 System Jumper Configuration
The system module for the VAXstation 2000 and MicroVAX 2000 systems are
identical. The only way for the system to know whether it is a VAXstation
2000 or a MicroVAX 2000 is by the position of the system jumper. The
system jumper sets a bit in the configuration and test register. Figure 3-120
shows the system jumper setting.

3-232 VAXstation 2000 and MicroVAX 2000 Technical Manual

Figure 3-120:

VAXstation 2000 and MicroVAX 2000 System Jumper

)

MICI'OVAX2ooo

VAXmIion 2000

$'!STEM JUMPER

3.13 System Module Connector Pinouts
The following tables list the signals on each connector on the system module.

Table 3-41: Power Connector (J1)
Pin

Signal

Ground

-12 Vdc

+5Vdc

+12Vdc

-9 Vdc return

-9Vdc

Table 3-42: ThinWire Ethernet Connector (J2)
Pin

Signal

Outer shell (ground)

Center conductor

VS410 System Module Detailed Description 3-233

Table 3-43: Printer Connector (J3)
Pin

Signal

Chassis ground

PTR XDAT

PTR RDATA

No connection

+12 Vdc

No connection

Chassis ground

Ground

FER ENA

Table 3-44: Battery Connector (J4)
Pin

Signal

Plus side of battery

Negative side of battery

Table 3-45: Video Connector (J5)
Pin

Signal

VID RED

Color return

Monochrome return

Fused +5 Vdc

AUX RDAT

Keyboard ground

Chassis ground

Fused + 12 Vdc

Monochrome signal

VID GREEN

VlD BLUE

-12 Vdc

AUXXDAT

KBD RDAT

KBD XDAT

3-234

VAXstation 2000 and MicroVAX 2000 Technical Manuai

Table 3-46: Network Option Module Connector (J6)
Pin

Signal

Ground

eoAL31

BOAl3O

BOAI.29

BOAl28

BOA!.27

IOAL26

BOA!.25

BOA!.24

BOA!.23

BDAl22

Ground

BOA!.21

BOA!.2O

BMU9

BOAt1S

BOA1I7

BOAl15

BOAL1S

BOAU4

BOA113

eoAL12

BOAU!

BOAL10

Ground

BDAl09

SOAl08

BOAL07

BOAl06

BOAlOS

BOAl04

BOAL03

BOAL02

BOALOI

BDALOO

Ground

Table 3-47: RD/RX Connector (J7)
Signal

Signal

Ground

LOSPEED

Ground

RXINOEX

Ground

F\XSELO

Ground

No conn.

Ground

MORON

Ground

RXOIR

Ground

RXSTEP

Ground

RXWO

Ground

RXWFlGT

Ground

RXTKOO

Ground

WFlTPROT

Ground

FlXRDATA

Ground

RXHSElO

Ground

RXRDY

RDHSEl3

RDHSEL2

Ground

ROWRGT

SKCOMPL

Ground

FlOTKOO

WFlTl'AUlT

Ground

ROHSELO

FlDHSEL!

Ground

FlOINOEX

RORDY

Ground

ROSTEP

ROSEto

Ground

ROSEll

Ground

RDOIR

DSELACK

Ground

No conn.

Ground

ROO,WDATH

ROO,WDATt

VS410 System Module Detailed Description

3-235

Table 3-47 (Cont.): RD/RX Connector (J7)
Pin

Signal

Ground

ROO.ROATH

ROO.ROATL

Ground

Table 3-48: Graphics Option Port Connector (J8)
Pin

Signa)

+5Vdc

Signal

+5 Vdc

+12 Vdc

·12 Vdc

Ground

BCLKO

BRESET

BASI

VDS

BWRITEI

VDSE

MEMADO

Ground

CAS3

CAS2

CASI

CASO

NIIRQl

NlIRQ2

MEMAD7

REFCYC

OPTROMENA

OPTVIDENA

OPTIRQ

OPTEOF

Ground

INTENA

SCYCIIAD2

DCYC/IADl

STFH/IADO

VID RED

Ground

VID GREEN

Ground

VID BLUE

Ground

OPTPRESENT

+SVdc

Table 3-49: Expansion Disk Read/Write Cable Connector (J9)
Signal

Signal

DSELACK

Ground

No conn.

Ground

No eonn.

Ground

+5 Vde

Ground

No eonn.

No conn.

Ground

R01.WOATH

R01.WOATL

Ground

R01.ROATH

R01.ROATL

Ground

No eonn.

3-236 VAXstation 2000 and MicroVAX 2000 Technical Manual

Table 3-50: Communication Connector (J10)
Pin

SipaJ

Signal

No conn.

COM.XOAT

COM.ROAT

COM,RTS

COM,CTS

COM.OSR

Ground

COM,CAR

No conn.

COM.SPOMI

No conn.

III

up.BeI<

No conn.

COM.oTR

No conn.

COM,RI

COM,OSRS

No conn.

COM,TMI

)
Table 3-51: Graphics Option Port Connector (J11)
Pin

Signal

Ground

BOAl31

BOAl30

BOAl29

BOAl28

BOAl21

BDAl26

8OAI.25

8OAI.24

BOA123

BOAl22

Ground

BOAl21

BOAl2O

8OAl19

8OA118

BOAl17

BOAl16

8OAl15

BOAU4

BOAl13

BOA112

8OAl1t

BOAll0

Ground

BOAl09

BOALOO

8OAl07

8OAl06

BOAlO5

8DALOC

BOAlO3

8OAl02

8OAlOl

8OAlOO

Ground

VS410 System Module Detailed Description 3-237

Signal

SIgnal

Signal

---------------------------------- ------------

Signal.

5
11

So.Al.'j

33
4D

Table 3-53:

Port Connector
Pin

Signa!

Gn,t.!r'[o

:;,8J"3:;

'j'\

(;f.~Yt'1-o

C:BU3.!:

0'3\)$11

{i'(;u,'>,1

r:f~f":S 7

r'~~,,,~SP

(; •.;';.1,.;110

Gr00r~

:t2

G10')(rj

~<.!-

"'<~
11:;

~~-..::. CCfli"'l

co!"']"

'?7

"~::;o~.'f'lr.i

Z'3

G~OlJn.j

i..1r.')'..:r:!.:l

Gt'i~V~,:;J

:);,

;:;J

CirO>Jr"'xi

Grc.il.md

),;

GrtRIO(:1

:~',

UrCt"):I\j

'J:£~

s.c"AG~<

GJ,~U(~<!

~;;'CHS-:

':).~{:<jJ;\:l

sc~;~so

.'l<",\

G,"<>Uil-j

SCSE:L

O:r~~tl;-~

4-6

seC,-D

':)1 ~:'l.;nd

.s~'.I~fG

ij-~Si

(ir,,)I.Jf:,j

Signal

GrOUflrs

'),

De\J~'}

~::n::,v-r;':.5

'3rouno:

Cleus,

G~,,,,"'\}f~d

::9,$4

Ii)

'JW::JfJC

{'if:;,),,}:,,!C'

3-238

VAXstatlon

Signal

~3!".:" . mr!:

~~(:'),)."!d

(.;~ ~n;nJ.'j

S:::;.\i~4

:SC;;D

Ivla.rual

Table 3-54: Network Option Module Connector (J14)
Signal

Signal

+5 Vde

+5 Vdc

+ 12 Vde

·12Vde

Ground

BeLKO

!RESET

VAS

vas

VWRITE

VDBE

MEMAOO

Ground

CAS3

CAS2

CAS,

CASO

VBM3

VBM2

VBMI

VBMO

NIROMCS

NlENA

NIIAO,

NIIA02

AEFCYC

VOMG

OMAAEO

SCYCnAD2

PERROfl

AEADY

CO.

Co.

AX.

RX·

TX+

TX·

NIPRESENT

<10

+5VOC

Table 3-55: Memory Option Module Connector (J15)
Signal

Signal

.svoc

.s voc

Ground

P81T03

PB!T02

PaITO!

PBfTOO

MSIZE2

MEMADe

MEMAD7

MEMA06

Ground

MEMAD5

MEMAD4

MEMAD3

MEMA02

MEMADI

MEMAOO

MSIZE1

MSIZEO

CAS3

CAS2

CASt

CASO

Ground

BOAI.22

EAAS

SRASO

BOAI.21

BOAI..20

BAS!

VOBe

BWRITE

Ground

+5 Vde

+5 Vdc

3.14 Power Requirements
The system module requires + 12 Vdc, + 5 Vdc, and ·12 Vdc supplies for
operation and a special -9 Vdc for power loading at 180 milliamps for the
ThinWire Ethernet transceiver circuits on the system module.

VS410 System Module Detailed Description 3-239

Chapter 4

MS400 Option Memory Modules
4.1 Introduction
This chapter describes the MS400·AA and MS400-BA memory modules that
are options to the KA410-AA system module. These modules do not provide RAM control signal generation; however, they do provide transceivers
for data and buffers for driving the RAM array with RAS, CAS, WRITE, and
ADDRESS. The KA410-AA system module generates byte parity when writing to RAM memory and checks byte parity when reading from RAM memory. Parity checking applies both to CPU accesses and to DMA accesses
generated by the network controller option. Only those bytes selected by
the processor byte mask are affected and checked.
The MS400-AA memory module contains 2 megabytes of memory and the
MS400-BA memory module contains 4 megabytes of memory. The MS400·
BA has components on both sides of the module. Only one MS400 memory
module may be connected to a KA410·AA system module. Figure 4-1 shows
a front view of the MS400 memory module (note that the MS400·BA has
components on both sides).

MS400 Option Memory Modules 4-1

Figure 4-1: MS400 Memory Module

CDDDD
CDDDD
DODD
DODD
DODD
DODD
o ODD
DODD
DODD

o0 0

ODD 0
[OJ
0000(0)
DODD
DODD
DODD
DODD
DODD
'" D O D D
o 0 0 0

~ 01

g
'"

0'"

0111111111111111111111111111111111111111111

-4.2 Theory of Operation
MS400 option memory is contained in DRAMs. These are the same DRAMs
as described in Section 3.3.1.1. The control signals on the memory module
and the timing cycles are described in this section.

4-2

VAXstation 2000 and MlcroVAX 2000 Technical Manual

Bits 22, 21 and 20 of the system data/address bus (BDAL22, BDAL21,
and BDAL20 on the system module that map to MSEL22, MSEL21, and
MSEL20,respectively on the memory module) are latched in an F373 latch
on the falling edge of VAS L. These latched address bits are decoded by an
F138 which generates RAS for one of the four (or two) 1-megabyte memory
arrays on the module. The appropriate decoder output is gated by ERAS
true and SRAS false during normal read and ",,'lite cycles and is input to the
DRAM chip's RAS pins.
During a refresh cycle, both ERAS and SRAS are asserted. This negates all
the outputs of the decoders and switches the multiplexers to assert RAS to
all the DRAM chips on the option module.

)

The four CASx L signals from the system module pass through F244 buffers
and series damping resistors to the CAS pins on the DRAM chips. Each
CAS signal is associated with one of the processor byte masks and so
determines which bytes of a longword are affected by a memory read or
write cycle.
The multiplexed address lines MEMADDx H from the system module pass
through F244 buffers and series damping resistors to the address pins on the
DRAM Chips. The timing of row address, RAS assertion, column address,
and CAS assertion are controlled by the system module.
Signal BWRITE L from the system module passes through F244 buffers to
the WE pins on the DRAM chips. This signal also controls the signal flow
direction in the F245 data transceivers.
The data input (0) and output (Q) pins of each DRAM chip are wired together and are sent to the system module data/address bus through F245
transceivers. The transceivers are enabled when both ERAS Land VDBE L
are asserted. The direction of data flow is selected by the BWRITE L signal.

4.2.2 Memory Cycles
The memory module responds to three types of memory cycles. They are
the read, write, and refresh cycles. Each cycle on the module is initiated
by the assertion of ERAS L. The cycle type is determined by SRAS Land
BWRITE L as shown in Table 4-1. The timing cycles for the memory module
are described in Section 3.5.2.

MS400 Option Memory Modules

4-3

Table 4-1: Determining Memory Cycles
Cycle Type

ERASL

SRASL

BWRITEL

Read

True
True
True

False

True

False

Write
Refresh

4.3 Connector Pinouts
Connector }1 carries power, address, and control signals as listed in Table 4-2. Connector J2 carries the buffered processor data/address bus
(BDAL31:00) as listed in Table 4-3.

Table 4-2: Connector J1 Pinout
Description

Signal

+5VC

+5VB

GND

PBIT03 H

Parity bit for byte 3

PBIT02 H

Parity bit for byte 2

PBITOl H

Parity bit for byte 1

PBITOO H

Parity bit for byte 0

MSIZE2 L

Memory size bit 2

MEMAD8H

Multiplexed address bit 8

MEMAD7H

Multiplexed address bit 7

MEMAD6H

Multiplexed address bit 6

GND

MEMAD5H

Multiplexed address bit 5

MEMAD4H

Multiplexed address bit 4

4-4 VAXstation 2000 and MlcroVAX 2000 Technical Manual

Table 4-2 (Cont.): Connector J1 Pinout

)

Signal

Description

MEMAD3H

Multiplexed address bit 3

MEMAD2H

Multiplexed address bit 2

MEMADIH

Multiplexed address bit 1

MEMADOH

Multiplexed address bit 0

MSIZEI L

Memory size bit 1

MSIZEO L

Memory size bit 0

CAS3L

CAS for byte 3

CAS2l

CAS for byte 2

CASll

CAS for byte 1

CASOl

CAS for byte 0

GND

29
30

MSELCH

BDAL22 H from system

ERAS L

Extended RAS (ERAS from the standard cell)

SRAS l

Standard RAS (SRASO from the standard cen)

MSElB H

BDAL21 H from system

MSELA H

BDAL20 H from system

VASl

Address strobe (BASI l on system module)

VDBEl

Data bus enable

BWRITE l

Write (BWRITEI l on system module)

GND

+SVA

+5VA

MS400 Option Memory Modules 4-5

Table 4-3: Connector J2 Pinout
Pin

Signal

eND

BDAL15 H

eND

BDAL14 H

BDAL31 H

BDAL13 H

BDAL30H

BDAL12 H

BDAL.29 H

BDALll H

BDAL.28 H

BDAL10H

BDAL.27 H

eND

BDAL.26 H

eND

BDAL.25 H

BDAL09 H

BDAL.24 H

BDAL08 H

BDAL23 H

BDAL07 H

BDAL.22 H

BDAL06 H

13
14

eND

BDAL05 H

eND

BDAL04 H

BDAL21 H

BDAL03 H

BDAL20 H

BDAL02 H

BDAL19 H

BDAL01 H

BDAL18 H

BDALOO H

BDAL17 H

eND

BDAL16 H

eND

4-6 VAXstation 2000 and MicroVAX 2000 Technical Manual

4.4 Configuration Jumpers
There ate no fJeJd-modifiable jumpers an the modulf;. The version oJ th('
module is determined by thr(~e signals on connector Jl. The first t",'o are the
same for both Inemory modules but the third signal is either disconnected
or grounded to indlcate 'which memory rnociule is lnstaH(~d . Table 4-4 lists
the three
and the preset configuration jumpers tOt both
modules.

Signal

I'il1

MSIZEl L

}"ISIZEl L

MSIZEO l

"')-"!'

.;;,~

MS400·AA

MS400·BA

Orm
Ground

Ground

4.5 Power Requirements
The memory modules require 4- .5 volts DC "'lith a tolerance of plus or minus
five percent, Tnt: typical current drawn is ,5 amps.

Memory Moaules

4-·1

Chapter 5

ThinWire Ethernet (OESVA) Option
Module
5.1 Introduction
The DESVA Ethernet controller option module enables the conm'ction of
i.'I. VAXstation
or MicroVAX 2000 system to an Ethernet netw(,rk via a
ThinlVlre connection llsing RG·58 coa"lal cable. The option is packaged on
a 4·inch by 7·inchboard that 15 located in the system unit and plugs inlo
the two DESVA option connectors (JS and 114) on the system module . TIU'
DESVA module is powered by the system box pov,Ier supply. The DESVA
contains a Loea.! Area Network Controller for Ethernet (LANCE) chip, a
serial interface adapter (SIA) chip, and a ROM that contains devke·drivH
programming. and supports logi\ circuitry, The Ethernet t.ransceiver (hlp,
Ethernet address ROM, and the BNC connector for the RG·58 cable to the
Ethernet are mounted on the system modu!e_ The nenvork cOJnponents on
the system module are inactive unW the DESVA option module is installed.

5.2 Connector Pin Descriptions
Figure 5-1 is a diag.ram of the Network Interconnect module. Tablt~ 5-1 and
Table 5~·:: sho\v the pin assignments for connectors J1 and }2.

ThlnVvire Ethernet (OESVA! Option Module,

5- i

C!I

'3
'0
0

III

r:;

c::

......
(J

(l)

...

.:&.

3::

c;
Z

......!

If!
C!I
\0.

t:.tI

i.i::

5-2 \!AXslation 2000 and MicroVAX2000 Technical Manual

Table 5-1: Pin Assignments for Connector J1
Pin Number

Sipl Name

Description

+5V

Not used (0 V)

VCLKO

Clock out from CPU. When LANCE is DMA
master, LANCE waits for 3 VCLKO cycles before next memory transfer.

BRESET

Buffered reset from CPU

VAS

Address strobe from CPU

VDS

Data strobe from CPU

VWRITE

Write from CPU

VDBE

Data buffer enable from CPU

Not used (0 V)

CAS3

Address strobe from standard cell, generated when
LANCE is DMA mastef. These signals afe generated in response to byte mask and address
strobe signals from the LANCE as an acknowledgement that memory timing has been started.

CAS2

Address strobe from standard cell, generated when
LANCE is DMA master. These signals are generated in response to byte mask and address
strobe signals from the LANCE as an acknowl.
edgement that memory timing has been started.

CASl

CASO

VBM3

Byte mask. Generated during DMA using LANCE
byte mask signals, and sent to standard cell
50 that appropriate CAS signals can be generated.

ThinWire Ethernet (DESVA) Option Module 5-3

ents for Connector Ji

Table 5-1
Pin Number
2(\

VBM2

VBMl

V8?v1O

NIRO!\1CS

NIENl"

Generated

DESVlI ROM

beleclf.rom standard eel.l

DESVA enable to L\NCE

sdect from staft-

card ceH

NlfRQl

DESVA
Not llsed (0 V}

27
28

Not used

VDlvtG

to V)
from CPU

DMA request. from [)[SVA

SLOW CYCLE

",{hel' t.:\NCE is DMA
after NIF.:!',iA Is assettee. SLO\V CYCLE is then asserted to 'C"""'~""
the c:ru v.hile

1.0 CSRs.

PERHOH

VRDY L

Re"dv from CPU> Bhiir!?ctio!1a!:
is Df.1A masler,
when

COLL+

(:oHislon detect (torn trans(,:erver on s\'stern ,mod ..
ule to seri;,,! int~'rf,Ke
ISlA!

error - inhibits DM.I>. transfer.
when LA.NCE

COLL-

Collision detect from transcdH?r on
ule to serial inter,tace

3'i

RECV

Receive + from transceiver on sy"tern module tc·
SL-\

RECV-

Rf~(ehie

mod·

., frorn ttensceiver on. SyStf'f11 IT1.oduh: to

SIll

x~m+

Transmit + from srI\. to transceivcr ;:;;n system
module

XMIT-

Transmit - from 51,A. to tnmsceiver (to
nlod,uJe

5-4

VPJ(station 2.000 and MlcroVAX

Manual

rable 5-1 (Cont.): Pin Assignments for Connector J1
Pin Number

Signal Name

Description

NIPRESENT

DESVA module present

+5V

rable 5-2: Pin Assignments for Connector J2
Pin Number

)

Signal Name

DescrIption

Not used (0 V)

BDAL 31

Bus data and address line

BDAL 30

BDAL29

BDAL28

Bus data and address line

BDAL27

Bus data and address line

BDAt 26

BDAL25

BDAt 24

BDAL23

BDAL22

"
"

Not used (0 V)

Not used (0 V)
Bus data and address line

BDAL21

BDAL20

BDAt 19

BDAt 18

BDAt 17

BDAt16

Bus data and address line

BDAL 15

BDAt 14

ThlnWire Ethernet (OESVA) Option Module

5-5

Table 5-2 (Cont.): Pin Assignments for Connector J2
Pin Number

Signal Name

BDAL 13

BDAL 12

BDAL 11

BDAL 10

Description

"
"

Not used (0 V)

BDAL09

Bus data and address Hne

BDAL08

BDAL 07

BDAL06

BDAL05

BDAL04

Bus data and address Hne

BDAL03

BDAL02

BDALOI

BDALOO

Not used (0 V)

5-6 VAXstation 2000 and MicroVAX 2000 Technical Manual

5.3 Ethernet Implementation
This option module supports the physical link and data link layers of the
Ethernet protocol.

5.3.1 Packet Format
Data is passed over the Ethernet at a serial data rate of 10 million bits per
second in variable-length packets. Figure 5-2 shows the format of each
packet.
Figure 5-2: Ethernet Packet Format

6 BYTES

DESTINATION ADDRESS

6 BYTES

SOURCE ADDRESS

2 BYTES

TYPE

46 •. 1600 BYTES

DATA

4 BYTES

CRC CHECK CODE

The minimum size of a packet in this implementation is 64 bytes, which
implies a minimum data length of 46 bytes. Packets shorter than this are
called "runt packets" and are treated as erroneous when received by the
network controller.

5.3.2 Network Addresses
There are two types of network addresses. Both are 48 bits (6 bytes) long.
1. Physical address: The unique address associated with a particular station
on an Ethernet, which should be distinct from the physical address of
any other station on any other Ethernet.
2. Multicast address: A multi-destination address associated with one or
more stations on a given Ethernet (sometimes called a logical address).
There are two kinds of multicast addresses:

ThlnWire Ethernet (OESVA) Option Module 5-7

An addn..'ss associa\ed
of logically related
b.

((.In-

Broadcast address: A predefined rmllticas! ,1ddress which denotes
the set of aU the stations on the Elhern€L

Bit 0 (the least significant bit of the
ot an address derwtes the
It is 0 for physical addresses and 1 for multicas!
In either
case the remaining 47 bits form the address value. A value ot 48 ones is

always treated as the broadcast address .
The physical address of each VAXstation 2000 or MicroV /.,X 2000
determinE'd at the tin,.e of manufacture and is stored in the Eth(:rnei

c·n the main system board (see Section

5.4 LANCE Chip Overview
This section describes the LANCE

5.4.1 LANCE Description
The LANCE is a lO·megabits
second 1\,105 d£:vl-::e in a
that implements the Ethernet netv"ork access

forms direct·memorv access
error
In
the LANCE listens for a dear (oilxial
and handles ~'nu;:""'-'
The LANCE chip 15 a microprogrammed controller that on
sive operations lndep~:ndently of
AX ('PC
lroi ana status registersiCSHs) within the LA;,JCE
the the MkroVAX CPU
to inithllize the
independent operation. Once
the
to directly access RA)I..-t
to
"ddiHonal
rameters and to manage the buffers it uses to transfer
structures in
the Ethernet. The Li~NCE uses

Descriptor rings- two logically circular rings or buffet
one
ring used by the chip receiver for
data and one ring used
the chip transmitter for outgoing dida.
buffer
in a
is 8 bytes long and starts on a quadword
Ie' i1

5-8 VAXslation

and MicroVAX 2000 Technical Manual

buffer elsewhere in memory, contains the size of that buffer, and holds
various status information about the buffer's contents.
3. Data buffers-contiguous portions of memory to buffer incoming or outgoing packets. Data buffers must be at least 64 bytes long (100 bytes
for the first buffer of a packet to be transmitted) and may begin on any
byte boundary.
When the MicroVAX or VAXstation system is ready to begin network operation, the central processor sets up the initialization block, the receive
descriptor ring, the transmit descriptor ring, and each of their data buffers
in memory. The central processor then starts the LANCE by writing to its
CSRs. The LANCE performs its initialization process and then enters its
polling loop. In this loop, the LANCE listens to the network for packets
whose destination addresses it recognizes. It also scans the transmit descriptor ring for descriptors that have been marked by the CPU to indicate
that they contain outgoing data packets. When the LANCE detects a recognizable network packet, it receives and stores that packet in one or more
receive buffers and marks their descriptors accordingly. When the LANCE
finds a packet to be transmitted, it transmits it to the network and marks
its deSCriptor when transmission is complete. Whenever the LANCE completes a reception or transmission (or encounters an error condition), it sets
flags in its control and. status register 0 to signal the CPU (usually by an
interrupt) that it has done something important.

5.4.2 Transmit Mode
In transmit mode, the LANCE chip directly accesses data in a transmit buffer
in memory. The LANCE prefaces the data with a preamble and a sync pattem, and calculates and appends a 32-bit CRe. This packet is then ready for
serial transmission to the SIA. On transmission, the first byte of data loads
into the 48-byte FIFO. The LANCE then begins to transmit a preamble while
simultaneously loading the rest of the the packet into FIFO for transmission.

5.4.3 Receive Mode
In receive mode, packets are sent via the SIA to the LANCE. The packets are
loaded into the 48.byte FIFO for preparation of automatic downloading into
buffer memory. A CRC is calculated and compared with the CRC appended
to the data packet. If the calculated CRC checksum doesn't agree with the
packet CRC, an error bit is set and an interrupt is generated to the CPU.

ThinWire Ethernet (DESVA) Option Module 5-9

5,4.4 LANCE Chip Pinout
FIgure

and Table

Figure 5-3:

pinout.

describe the

LANCE Chip Pinout

32
33
J4

37
J.8

- APPR 23
- A!JOO .22
- AOOR 21
-.4.l'.\DR 20
- ADDR 19
- AOOR 18
- ADOR 17

- AOOR HI

- 11),,,1.. 1;;
- lOAL 14
IOAL 13

3S
.J.e

*21-

.3
+4
4.5

- IDAI.. 12
- fOAl \I
- lOAL 10

- IOAL 09
- IDAL 08
- IDAL 07

,*'7

:I:
J

- m,o,L oe
.1
5. 04
_ _~7 :: ;g~ g~
_

lPAL 05
leAL

,..---

8
9

- IOAl 01
- 10AL 00

Ii , 0- NliRO L
0- NiOM ",,1'(£:;; L

!7
;8
l.t
1J

~M01

5-10

l -

NiENA L -

AOR-

NAXEl) R[SET -

Tel./( RCU< -

a..sN-

25
21
26

!'lENA RX -

30
31

VAXstatlon 2000 and MicroVAX

0- lAS L

I 00- lOS L
0,>",0 t

0- OAL! l

10
Hi
15

0- v~ITE L
0- LSMl L
Q- LaMO L

l.R,n L

T~~e_~:~.:
Fir!

__LANC~_Ch!£.!in_~_!_~.:.ription!.___.__.___.~- - Df!S.CrlpUOfl

IDALOU· ID.AU5

Data/address lines (inputhmtpu! tn-state). Thl." time multIplexed address!d.lte bus. During the address portion of a nH"lrlory transfer . DAlOO • DADS contain the lower 16 bit$< of the
memo!'}! address. The upper 8 bits of the address aft' c(!l"1tained
in A16 - A23.

ADDR16· ADDR23

High order address bus (output tri-st.ate). The adciHiona.l address bits necessary to extl"nd the DAL lines 10 access a 24·l'it
address. These Hnes are driven by a bus master only.

VWRITE L

(Input/Output trl·sta!t'l. inc'Jca.les the type of operation to bf:
f't'rformed in the current bus
n·Js
is an
when thl' LANCE is a bus master.

High· Dala is taken off the DA.L by the
Low - fJat .. is

on the DAL by the

Vi:'v1UTE L is an input when the LANCE is l'I bus slave .
• Data is token off the- DAt by the
High - Data is taken off th€; OAt by the chip.

LBMI L, LBMO L

Hi-.state} Pins 15 and 16 are programmable through
of CSR3,

If CSR3 trH 0(1 BCON '" 0, pin i5 "" SMO L (output trl-state/
16 '"
L (OUlput tn-state).

un.n

and

LBMO L. LBMI L(by!t' mask). This indJ.cates the
on
the DAt Itte to De read or written during this bus tr,msaction,
The LANCE drives these lines only as a bu~; ma.ste-r. It ,"',-,cm"",
the
mask lineF when it is a bus slav€', and assumes word

The following lines describt,

LBMl t

rnask:

LB!l.10 I.
tmv

\'\:'hole word

L()~v

Lower byte

Low

H.ig.h

None

ThinWire Ethemel (DESVA) Option Modu!(J

5-11

Table 5-3 (Cont.): LANCE Chip Pin Descriptions
Description

1f CSR3 bit 00 BCON - I, pin 15 '"' BYTE (output tri-state)
and pin 16 == BUSAKO L (output)
Byte selection may also be done using the BYTE line and OALoo
line, latched during the address portion of the bus cycle. The
LANCE drives BYTE only as a bus master and ignores it when
a bus slave selection is done (similar to LBMO L, LBMI L).
Byte seJection is descnbed as follows:

Byte

DALOO

low

Whole word

low

High

Upper byte

High

low

lower byte

High

None

BUSAKO L is a bus request daisy chain output. If the chip
is not requesting the bus and it receives VOMGl L, BUSAKO
L is driven low. If the LANCE is requesting the bus when it
receives VOMGl L, BUSAKO L remains high.
NIENA L

Chip select (input), When asserted, this signal indicates that
the LANCE is the slave device of the data transfer. NIENA
L must be valid throughout the data portion of the bus cycle.
NIENA L must not be asserted when VDMGl L is low.

AOR

Register address port select (input), When LANCE is a slave,
ADR indicates which of the two register ports is selected. ADR
LOW selects register data port. AOR HIGH selects register
address port. AOR must be valid throughout the data portion
of the bus cycle and is used only by the LANCE when NIENA
Lis low.

IASL

Address latch enable/Address enable (output tri-state). Used
to demultiplex the OAL lines and define the address portion of
the bus cycle. This 110 pin is programmable through bit 01 of
the CSR3.

5-12

VAXstatlon 2000 and MicroVAX 2000 Technical Manual

Table 6-3 (Cont.): LANCE Chip Pin Descriptions
Pin

Description

As Address Latch Enable (CSR3 bit Ot, ACON '" 0), the signal
pulses low during the address portion of the transfer and remains low during the data portion. ALE can be used by a slave
device to control a latch on the bus address lines. When ALE
is high the latch is open and when ALE goes low the latch is
closed.
AS address enable (CSR3 bit 01, ACON - 1), the signal pulses
Jow during the address portion of the bus transaction. The low
to high transition of AS can be used by a slave device to strobe
the address into a register.
The LANCE drives the lAS L line only as a bus master.
IDS

Data strobe (input/output tri-state). Defines the data portion
of the bus transaction. IDS is high during the address portion
of a bus transaction and low during the data portlon. The low
to high transition Can be. used by a slave device to strobe bus
data into a register. DAS L is driven only as a bus master.

DALaL

Data/Address line out (output tti-state). An external bus transceiver
control line. DALO L is asserted when the LANCE drives the
DAL lines. DALO L is Jow only during the address portion if
the transfer is a READ. It is low for the entire transfer if the
transfer is a WRITE. DALO L is driven only when the LANCE
is a bus master.

DAUL

Data/Address line in (output tti-state). An extema1 bus transceiver
control line. DAU L is asserted when the LANCE reads from
the DAL Jines. It is low during the data portion of a READ
transfer and remains high for the entire transfer if it is a
WRITE. DAU L is driven only when LANCE is a bus master.

NIDMAREQL

Bus hold request (output open drain). Asserted by the LANCE
when it requires access to memory. NIDMAREQ L is held low
fOr the entire ensuing bus transaction. The function of this
pin is programmed through bit 00 of CSR3. Bit 00 of CSR3 is
cleared when NAKED RESET L is asserted.

VDMCl L

Bus hold acknowledge (input).
A response to NIDMAREQ
L. When VDMCl L is low in response to the chip's assertion of NIDVDMCl L de·
MAREO L, the chip is the bus master.
asserts upon the deassertion of NIDMARBQ L.

ThlnWlre Ethernet (DESVA) Option Module

5-13

Description

NHRQ L

Interrupt (OUtput oren drain). An attention signal that indicates, when active, thilt ene or mmt" (,f the folloWing CSRO
status f1ag~ is set; SArlI., t>.1£RR. !>.HSS., RINT., TINT. (If lDOf\~
NURQ L is enabled bv bit 06 of CSRO (!NEA "" 11. NHRQ L is

-----------------------------------

asserted until the source of the interrupt is removed.

RX
TX

Receive (outpulL Receive input bit stream

Transmit !.OU!put), Traf'.smit output bit stream.

TEN/;

TraMmH Enable (output) Transmit <.'ulput bit str~3m enable.
(~ levl"l asserted with tile transmlt QutPl1t blt stream, TX. to
enable the extt'mal lJa.l1srnit

RCLK

Receive dock (input!. A H) \tH2
the receive data and
active
stream,

CLSN

Collision (in~".1t), A logicrd input that indic(l.!es that B. collision
is occurring on the channel.

RENA,

Receive t'nable (inpui). A
enc€' of carrier on the

TeLK

Transmit dock

LRD), L

10 Jl"fHz d!xk.

\Input:Oulput open drain), \:\,111"n the LA,NCE is a btl'S ma.'Ster,

LRDY L is an asvnch!'(mous
mer:'OfV that LANCE can
1s has put datil on the D.A.L

from :he bus

dat:~ i.n a WRITE
in Ii> REAr) cvd{'

or that

As a bus slave. the LANCE ass!'!'!!; tRDY L when i.t has
on the DAt lines
,l READ
or is about to

off the DI"IL line:;
to IDS and returns
output when the

a WRITE

d,HlI
ddti'l
LRl)Y L is a fP5ponse

tRDY L

is a bus
the LA.NCE is a bus sl.ave.

Bus

Vee

Cause.,> th'" U\f\:CE In ('e"se ere"
and tni!'t an idlE- StDle" v.Hh the

Power supply pin, +5 volts (+1· 5 ,ok).!
Ground,

5-14

VAXstatlon 2000 and MicroVAX 2000 Technical Manua!

5.5 SIA Chip Overview
Figure 5-4 shows the pinout for the serial interface adapter (SIA) chip.
figure 5-4: SIA Chip Pinout

RCV+ ReV- -

22
21

COU+-

cou--

lX-

TENA -

14
13

- XNIT-

- a.sN

- RENA

X1-

)(2-

VCC2 'iICC! -

GN03 -0
GND2 -0
GN01 -0

•

- )uT+
TCIJ(

-RX

-Pr
-RF

RCIJ(

11
15
7

5
18
5

- TSEI.

'!'EST -

ThinWire Ethernet (DESVA) Option Module 5-15

Table 5-4: SIA Chip Pin Descriptions
Pin Name

Description

CLSN

Collision (output). A TTL active high output. Signals at the col·
lision +1· terminals meeting threshold and pulse width require·
ments produce a logic high at CLSN output. When no signal is
present at Collision +1·, CLSN output is low.

Receive data (output). A MOS/TTL output, recovered data. When
there is no signal at Receive + h and TEST L is high, RX is high. RX
is activated with RCLK and remains active until end of message.
During reception RX is synchronous with RCLK and changes after
the rising edge of RCLK. When TEST L is low, RX is enabled.

RENA

Receive enable (output). TTL active high output. When there is no
signal at Receive +,., and TEST l is high, RENA is low. Signals
meeting threshold and pulse width requirements produce a logic
high at RENA. When Receive +/. becomes idle, RENA returns to
the low state synchronous with the rising edge of RCLK.

RCLK

Receive clock (output). A MOS/TTL output recovered clock. When
there is no signal at Receive +/., and TEST Lis high, RCLK is low.
RCLK is activated after the third negative data transition at Receive
+/., and remains active until end of message. When TEST Lis low,
RCLK is enabled.

Transmit (output), TTL compatible input. When TENA is high,
signals at TX meeting setup and hold time to TCLK is encoded as
normal Manchester at Transmit+ and Transmit·.
TX high: TRANSMIT + is negative with respect to Transmit- for
first half of data bit cell.
TX low: Transmit + is positive with respect to Transmit- for first
half of data bit cell.

TENA

Transmit enable (input). TTL compatible input. Active high data
encoder enable. Signals meeting setup and hold time to TCLK
allow encoding of Manchester data from TX to Transmit + and
Transmit-,

TCLK

Transmit clock (output). MOS/TTL output. TCLK provides symmetrical high and low clock signals at data rate for reference tim·
ing of data to be encoded. It also provides clock signals for the
LANCE chip and an internal timing reference for receive path
voltage-controlled oscillators.

5-16 VAXstation 2000 and MicroVAX 2000 Technical Manual

Table 6-4 (Cant.): SIA Chip Pin Descriptions
Pin Name

Description

XMIT + IXMIT-

Transmit (outputs). A differential line output. This line pair is
intended to operate into terminated transmission lines. For signals
meeting setup and hold time to TCLK at TENA and TX, Manchester
clock and data are output at Transmit + and Transmit~.

RCV+/ReV-

Receiver (inputs). A differential input. A pair of internally bi·
ased line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to detect the signal, and a data
recovery receiver with ne .offset fer Manchester data decoding.

COL+/eOL-

Collision (a differential input). An internally biased line receiver
input with offset thresheld and noise filtering. Signals at COL +1.
have no effect on data path functions.

TSEL

Transmit mode select. An open collector output and sense amplifier input.
TSEL Jaw: Idle transmit state. TRANSMIT + is positive with respect to TRANSMIT-.
TSELhiab: Idle transmit state. TRANSMIT + and TRANSMIT· are
equal, providing "zero" differential to operate transformer coupled
loads.
When connected with an RC network, TSEL is held low during
transmission. At the end of transmission the open collector output
is disabled, allowing TSEL to rise and provide a smooth transition
from logic high to "zero" differential idle. Delay and output return
to "zere" are externally contrelled by the RC time constant TSEL.

Xl,X2

Biased crystal oscillator. Xl is the input and X2 is the bypass port.
When connected for crystal operation, the system dock which appears at TCLK is half the frequency of the crystal oscillator. Xl
may be driven from an external source of two times the data rate.

Frequency setting voltage-controlled oscillator (VCO) loop filter.
This loop filter output is a reference voltage for the receive path
phase detector. It also is a reference for timing noise immunity
drcuits in the collision and receive enable path. Nominal reference
VCO pin is 1.25 TCLK frequency MHzfV.

Receive path VCO phase-lock loop filter. ThIs loop filter input Is
the control for receive path loop damping. Frequency of the receive
veo is internally limited to transmit frequency + ,. 12%. Nominal
receive VCO pin is 0.25 reference VCO gain MHz/V.

ThinWlre Ethernet (OESVA) Option Module 5-17

Table 5-4 (Cont.): SIA Chip Pin Descriptions
Pin Name

Description

TESTL

Test control (input). A static input that is connected to Vee for
normal SIA operation and to ground for testing of receive path
function. When TEST L is grounded, RCLK and RX are enabled so
that receive path loop may be functionally tested.

GNDl

High current ground

GN02

Logic ground

GND3

Voltage-controlled oscillator ground

Vce!

High current and logic supply

Vcc2

Voltage-controlled oscillator supply

5.5.1 SIA Description
The SIA has three basic functions. It is a Manchester encoder/line driver
in the transmit path, a Manchester encoder with noise filtering and lockon characteristics in the recieve path, and a signal detect/converter in the
collision path. The SIA provides the interface between the TTL logic environment of the LANCE and the differential signalling environment in the
transceiver cable.

5.5.2 Transmit Mode
The Manchester encoder in the SIA takes transmitted data from the LANCE
and creates the Manchester-encoded differential signals TRANSMIT + and
TRANSMIT-to drive the transceiver cable. These differential signals are
coupled through the transceiver (on the system module) and on to the Ethernet coaxial cable.

5.5.3 Receive Mode
When a carrier signal is present on the Ethernet coaxial cable, the transceiver
creates the differential signals RECEIVE+ and RECEIVE-. These inputs to
the SIA are decoded by the Manchester decoder. A phase-locked loop in
the SIA synchronizes to the Ethernet preamble, allowing the decoder to
recover clock and data from the cable, indicating to the LANCE that receive
data and dock are available.

5-18 VAXstatlon 2000 and MicroVAX 2000 Technical Manual

5.6 DMA Operation
The LANCE chip contains a built-in DMA controller that can transfer data directly between the chip and system memory in the address range 0000.0000
through OOFF .FFFF. (Only system module RAM and option module RAM
appear in this address range.) The LANCE contains a 48-byte FIFO buffer
to allow for DMA service latency and to minimize the number of requestgrant arbitration cycles. When transferring large amounts of data in burst
mode, the chip transfers 16 bytes per DMA request. Each longword transfer requires 0.6 microseconds, so a 16-byte burst requires either 2.4 or 3.0
microseconds, depending upon whether or not the data block is longwordaligned.
The LANCE's DMA controller is used to read the initialization block, to read
and write the descriptor rings, and to read and write data buffers. Note that
all the memory addresses handled by the chip are physical addresses. Programs which operate with CPU memory management enabled must translate their addresses from virtual to physical form before presenting them to
the LANCE chip.
If the-(parity enable) PEN bit of the system's memory system error register
(MSER) is set, then parity is checked during DMA read cycles. When a parity
error is detected, the ERR signa) is asserted as described in Section 3.3.
Such an error manifests itself in one of two ways: If another DMA cycle
immediately follows the DMA cyde during which the error occurred (that is,
during the same DMA request), then the MERR bit of the NI.CSRO register
is set but no CPU machine check occurs. If, however, the DMA cycle during
which the error occurred was followed by a CPU cycle (that is, the failing
DMA cycle was the last in a DMA request), then a machine check occurs,
but MERR is not set. In both cases, the PER bit of MSER is set and the
address of the failing location is latched in the MEAR register.

ThinWire Ethernet (DESVA) Option Module

5-19

5.7 Controller Firmware ROM
Figure
shows the pinout for the conttuller
describes the pins.
Figure 5-5:

ControUer Firmware ROM

ni.~ : ~.~
18
15

,,,,14

An A12
',1~

25
:;,

-" 00

>'4

-- "5

,4;

AI';

-- (12

~ 2,

2.1

;;'I

i~}

26
;:
23

A10

All -

- 04
- O~

", - e7
112 AG ..

Table 5-5: ROM Pin Descriptions
-----.---""....

.."..--,--------."'.'''',.~---,;~-~--''''''---"-,,,'--~-."---.-

Pln Name

Oescrlpllon

()4) ·07

Data outputs to memory

AO·A14

Address

latched in frQtn D.Al bus

VAS L

CPU
Chip select L
Enable

5-20

Enables the do.ta path (0 DAL bus,
\IDS L
from CPU

Output

.dtll V\VRlTE Land

enabled

VA,XstaliOI1 2000 and MicroVAX 2000 Technical Manual

5.7.1 ROM Description
The netvmrk controUer option board contains one 28-pin socket for a ROt",!
to contain option identiflcatlon information a.nd device driver programming,
This ROM contains 32 kilobytes and is connected to the lo\v-order 8 bits of
the
data bus, Therefore, its contents appear as the lmv-order bytE: in
each of 32-kilobyte consecutIve longwmds in the address range 2010,0000
thnmgh 2011,FFFf (the data returned in the three high-order byte~ of €iHh
long-word is unpredictable) SN, Section 3.3,2,,3 for information on address
aHocation and ROM formal,

H the option-present signal. is asserted, the R01\,1 is checked and it~ contents
unloaded ini{' memory, TEST 1 code is then executed. Since the ROM is
connected only to the low-order bvle pf the data bUE>, code cannot be direcH"!
executed from- the ROM; it must t;€ copied into consecutive
of a RAh1
area and executed from there,

5.8 Program Control of the LANCE
Program control of the LANCE chip is via hvo 16·bH read/write ports, each
of which appears a.s the lo'w-order word of a longword address. These ports
are:
AddN'SS

Nam~

200E.(01)(\

NtRDP

Description

NU~AP

These ports provide access to {,)Uf 16·bH control and status registers \'I'hkh
are named NCCSRO through
A
is accessed by first writing
its number into tht> register add.ress port Nl_RAP after which the contents
of the CSR are read Or vvritten by accesses to the register data port Nt RDP.
Note that registers other than N1...CSFO) may be accessed only \','hile the
STOP bit of NCCSIW is set,

TnlnWlre Ethernef (DESVA) Option t·Aoduie

5-21

5.8.1 Register Address Port (NI_RAP)
The register address port is a 16-bit read/write port at physical address
200E.0004. It selects which of the four CSR's is accessed via the register
data port. Figure 5-6 shows the LANCE register address port format.
Figure 5-6: LANCE Register Address Port (Nt.RAP) Format

RESERVED
7

RESERVED

CSRHO

Bit

Definition

<15:2>

Reserved. Ignored on write; read as O's.

CSRNO

CSR select (bits 1:0). These readfwrite bits select which of the four
CSRs is accessible via the register data port. They are cleared to 0 at
power-on. Values are as follows:

Bits 1:0

NI CSRO

NI CSR1

NI CSR2

Nl CSR3

5-22

VAXstation 2000 and MicroVAX 2000 Technical Manual

5.8.2 Register Data Port (NI_RDP)
The register data port at physical address 200E.0000 is a 16-bit window
through which the CPU can read and write the CSR designated by the register address port NI.RAP.
Note that registers NI CSRl, NI CSR2, and NI CSR3 are accessible only
while the STOP bit in NI CSRO set. If that STbp bit is clear (that is, the
LANCE chip is active), attempts to read from those CSR's return UNDE·
FINED data and attempts to write to them are ignored. Accesses to a CSR
via NI.RDP do not alter the register address pointer NI.RAP. In normal operation, only NI CSRO can be accessed, so NI.RAP should be set to point
to NI.CSRO and1eft that way.

5.8.3 Control and Status Register 0 (NI_CSRO)
This register is used by the controlling program to start and stop the operation of the LANCE chip and to monitor its status. It is accessible to the
processor via port NI.RDP when bits 1:0 of NI)~AP are set to 00. All of its
bits can be read at any time and none of its bits is affected by reading the
register. The effects of a write operation are described individually for each
bit.
When power is applied to the system, all the bits in this register are cleared
except the STOP bit, which is set. Figure 5-1 shows the LANCE control and
status register.
Figure 5-7: LANCE Control and Status Aegister 0 (NI.CSAO)

IRR

BAIL

ClRR

MISS

MERR

RINT

TINT

IDON

INTR

IHEA

axON

TION

TDMD

STOP

STRT

IN IT

ThinWire Ethernet (DESVA) Option Module

5-23

Bit

DefinitIOn

ERR

Error summary (bit 15). ThiS
bH is '1 'A'hene1.'f't anI,! of (Ii the
bits BARL CERR, .MISS, or MERR in
ilfi:' 1 's \'\'rlting to this
bit has no eflen. l! is (leafed when a.lId
hits which set it ilfe 0 or
when the STOF bit b set.

BARt

Transrrdtter timeout error (bit 14). This bit is :'it'! when the transmitter
has been on the channel longer than the lime required to send the maxImum length packet. It is set after 1519 data vytes have bf('n transmitted
(the chip continueo. to transmit until the whole
i5 transmitted or
until a failure OCClll:S before the whole packet 1s transrnilted).
11';5 bit is cleared when a 1 is written to it
'.vhen ~he STOP ht is Set. \'\'hen this bi! is 1, the
als,) l's.

CERR

and INTJ< bHs are

Collision error (bit 13/. This bit is set ,,,.hen thf:' collision
failed to activa!e within 2 micrcseccnds "fter a
tn1nsmission is
This cQlllsio!1-aHer-tr,1i'1smission
a transcein'!! test
feat:sre.
funCtion is also known as hearfbeat (If SQE !sigr,al
error) test.
This 'bit is deared when a 1 15 \uitten to it {
when the STOP bit is seL \Vhen this bir is t

MISS

a [I has m' effect) Of

a 0 has nf) eHf'cl I or
bit IS al'>l) 1.

Missed p(ld'et (bit 12). This bit is set when t);e receIver loses i!
because it does not o\\'na receive buffer. The MISS hi! is not vaJid :1'1
internal loopback mode,

This bit is cleared when a one is wrin;,·;; to it (writing a (\ hilS no
or when the STOP bit \s set. Wlwn tll.is bit i~ L th(" ERR and JNTR bits
are also l' s.

MERR

Memorv erwr (bH
This bit is set '.'ijR'n the
transfet and doe!> not receive a readv reEf'I)!1.Se irem
25,6 microseconds after
'the ;",emNY
occurs when a
bus read
assertt'd the ERR
receiver
lransmltter are turned off
register are cleared to
This bit is cleared ;9ht'na 1 is \V'ri! ten to H
w.hen ihe STOP h:t is: sel. When this bH is 1, lh"':
also l's,

RINT

or
and lNTR bits an:.

Receive interrupt
10). This bit is Sf't "'ihen ihe chip nnn;",,,,, <111 ('1'\.'
in the receive rlp,oC',·inl,m·
for the 1,'Is: buHer
('I \.'"'hf~n
reception is ,,1('''''''''.<'[1

5-24 VAXstaHon 2000 and M!croVAX

Techrucai

This bit is dearf.'\1 when a 1 iB written to it (writing l.7 (I has n0
0)'
when tnt' STOP bit is set \Vlwn this bl! is 1, t.he INTR bit is .. iso L

TINT

TransmiHer interrupt (Nt 9). This bit is set when the chip
an
entry in th!" transmit descrirtor
for Ihl" last buffer sl"nt or when
transmlssi('n if; stopped due 10 a failure
This bH is deared when a 1 is written to il \ writing ,~ (I has no effect) or
when thl? STOP bit is set, y.,rhen this bit is 1, the E·,,;TR bH is also).

lDON

Inltlaliz,ation dOM (hit 8) This bit is set when the chip COmpfelf"S lhe
initialization pn}(f"',s: which was startt"d by
tht> INIT bit in this
reglstH, When !DON is set the chip has read
.initialization biod·
from mefnMy and SlOr(-d the ,.,e\,\'
This bH h, deart'd 'WhNl <J 1 is written t<~ it (writing 11 0 hilS ne eff(,ct/ (II
,,,'hen the STOr bH is st'\. \Vhen this bit i,: L the lNTR hit is also 1.

!NTR

Interrupt reqnesl (bit
Thls read~o:n!y hit i:; 1 whenever aliY of 11\,'
bit!' BASL. MlSS, MEHR R!NT, TINT, or IDON in fhis
er are 1 's,
Writing to this pi!
ncr ef/('I;:L It is cleared when all of
bi~s which
set it are 0 or v,·hen. th/f STOP bit is set.

VY'h(;>11 bOth the IN'TR lind INEA bits in this register are set. an
request is sent to t.he $ystem interrupt controller
iNEA

Interrupt ena'He (bj~ f). This rt"ac\!wr!t(" bH control;', whether the s('tt1ng
of the INTR bit generates an in.terrlJp! reqnest .~'V'hen both the I~TR
and INEr\ bits in thi~
are: set, an interrupt requ€"sl is sen! to \ he
system in1errop~
This hit is set when a 1 l~ written to' 11. h is cleared "..-hen a Gis wrHtl"n
Hl it or when the STOP bit is set

RXOi'>i

Receiver O'n (hil
This read-only bit, WheI) set 101 indicates th,,!. the
receiver is enabled, RXON is set ,":;hen Initialization is ",~'"",..,loj
,,,>'hen lOON is set. unless the DR>: bit 01 the initia.lization
fE'gister .is 11 and then lht: STRT bit in this regiMer i.s set
bH haf; no ",Heel. R)'.(lN is de<m:ciwhen cilh(,l' the MERF: or
hit::;
Qf this register are set,

n:or,,'

Transmitter on (bH 4). This read-onl\' bit., wh~:n set to 1, indicat.N; thai
the !ra.l'!s.rniHer is; enabled. TXON is set when lniUiJ.lizlltion is
(that is, when IDON is set, unless the Dr\ bit t)f the iniiislit:ation
MODE regjslf'r is 1,1 and then the STRT hit In this
is set. \Nrif i ng
t(> thiS Pit 11M no efit!c! TXON is cleared when
the l'vtf:RP or
STOP bits of this rt'glS!,'f an: set or when am of bit" UfU),
or
R1RY in a transmlt buffer
are t;et, "

TtlloWire Elhemet (DESVAt Option Module

5-25

Bit

Definition

TDMD

Transmit demi\,nd (bl
S{,tting this bit signais tlw
the transmit descriptor ring without
lor thl"
to elapse. This bH need nul be set tc
"
hastens the
f('SPOMC tc the in,sert.ion 01 iii !ransrnit
entry by the host program.
This bH is set by writing a 1 to it (writing a 0 has HO effect) arld IS cleared
by the chip when it
the bit \the bH
read 851 fer il short
t.ime after it is set, depending
the level
activity in the
TDMD is also cleared when the
hi! is set.

STOP

Stop ex,ternal activity \bit 2)' Setting til\g bit sloFs an e)(lern,11
and dears the internal
of the chi!",: this has the same effect a~l
electrical reset signalled al po\\er-on.' The chip remains inurtlve and
STOP remains set until the 5TRT or INIT bHs in this
are set,
a 0 has rw effeen or at po,ver·
This bit is St:! by writing a 1 to it
on. It is cleared when either lNIT or
is set- If the
wrll~'$
l's to
lNrI, and STRT at the ".,me time, STOP
and neither snn nor INIT ls set
Setting STOP cle<l!'s all the other 0itS in this
1\.Her STeW has
been set, the other three CSR~ IN! CSRI. NI
and
be reloaded before setting iNn or 'STRT lf10\e that those
may be accessed only while STOP is set).

STRT

Start opet'iHion (bit
Settil1 g this bit. enables the chip te send and
receive
perform DMA and manage th{, buffer, The STOP tit
must be set prior to
the 5TRT l::.it (setting STRT then clears STOP.!.
STRT .is set b:,'
a. 1 1.0 it lwritir>g a n has no efh~ct). \[ is deaxed
when the STOP bi!. is s'C(,

1~"jlT

InitiilU.ze I,bit

this bit causes the chip to rerform its initializ.a·

Hon process, .vhieh
the inidoUza:ion block from the memory addressed bv the contents of
The STO(.' ht must be3et prior to
[NIT lhen
dears STOP),
IN!Tis set
vihen the

,\',riling a 1 to it
bit

is set

a (\ hilS no

NOTE: T71t' INIT ana STI?T bits IHU;;:t [wi be :,.;;'f at fhe sl'mu tllHL
The proper initialization procedure is as follows:
1.

Set STOP in NI CSRO.

Set tip the init.ialization blod; in

5-26

VAXstallon 2000

MleroVAJ<

1t is cfeared

Load
block.

and Nl,CSR2 \v1th the starting address of the

4. Set L'IIT in NI CSRO.
5. Wait for lOON in Nl CSRO to become set

6. Set STRr irl Nt

to begin the operation.

5.8.4 Control and Status. Register 1 (NI_CSR1)
This readiwrite register is used in conjunction wilh NI.CSR2 to supply the
24·bit physical memory address
the InitializaUoll block, which the
reads when it performs its initializanonproc€ss, The register is
to the processor via Nl.RDP when bits 1:0 of NI.RAP are en and the
bit of NISSRO is set. Its contents at pOl-ver-on are unpredictable. Figure 5·8
shows: the LANCE control and status register 1,
Figure 5-8:
15

LANCE Contro' and Status Register 1 (Nf.CSRi)
14.

.:m~ "

IADR 15:8

lADR 1; j

IADI?

Initialization blo(:x add.res,~
bits of the (24·hi!
izaHon block. Because the

0
0

The&e. are thelow~(}l'dl"r '3irte~'1\

address of the firs! byte of thp i niti aIt'!Hliit beword-alig,nfd, bit 0 m\,l$t bt

ThinWir6 Etherne! (DESVA) Option Module

5-27

5.8.5 Control and Status Register 2 (NI, CSR.2)
This readlv,'ri!e register is used in conjunction vdth NI~CSRI to supply the
24-bit physical memory address of the initiailz"ticn block which the chip
reads \'\;hel1 it performs its initializ.ation process. The
is acc€ssib!€'
to the
via NI RDP when b.its 1;(\ of
are 10 ilnd the STOF
b.it of
.CSRO is set.
contents at power·on an: unpredictable.
shows the LANCE control and status register 2.

Its

Figure 5-9:

LANCE Control and Status Register 2 (Nl.CSR2)

"----_______=r.
8

Bit

Definition

<15:8>

Reserved. Write with 0'5.

U'o.DR

InHiaHzatiori block address (bits
These are n',(
bits of the (t4-bH
\ b,rte address of the first
izatiofl b!Clck.

. .

5.8.6 Control and Status Register 3 (NI_ CSR3)
This readiwrite
of the electrical interf,'lCe
beh,,'een the
chip and the
must be sel as indicated for
each btL The register is
10 the
via NI RDP ;vhen bits
1.:0 of NJ RAP ar·e 11 and the STOP bit
CSRO is set.~ Hs content.s at
power.on"are entirely 0'5.
5·10 shmv$ tl1e LANCE control and statu.:.>
register 3,

5-28 VAXstation 2000 and MicroVAX 2000

Manuai

Figure 5-10:

LANCe Control and Status Register 3 (NI_CSR3)
14

BSWP

ACON

BCON

RESERVED

Bit

Definition

<15:3>

Reserved. Ignored on write; read as O's.

BSWP

Byte swap (bit 2).
When this bit is set, the chip will swap
the high and low bytes for DMA data transfers between the silo and bus memo
ory in order to accommodate processors which consider bus bits
15:08 to be the least significant byte of data, This bit is read/write; it is
cleared when the STOP bit in NtesRO is set,
For this system, this bit must be O.

AeON

ALE control (bit 1).
Thi" bit controls the polarity of the signal emitted on the chip's ALE/AS pin during DMA operation. This bit
is read/write; it is cleared when the STOP bit in NteSRO is set. For this system this bit must be O.

BeON

Byte control (bit. 0).
This hit controls the configuration of the
byte mask and. hold signals on the chip's pins during DMA operation. This bit is read/write; it is cleared when the STOP bit in NI_
CSRO is st't. For this system, this bit must be O.

5.9 Interrupts
The LANCE chip asserts an interrupt request signal whenever the INTR and
INEA bits in NI CSRO are both 1'9. This signal is presented to the system
interrupt controller as interrupt number 5, the "network controller primary"
source. Its vector number is 250 hexadecimal.
The change of the interrupt signal from false to true sets bit NP in the interrupt request register (INT_REQ), which generates a CPU interrupt when the
corresponding bit in the interrupt mask register INT.MSK is also set. Note
that since the input to INT_REG is transition sensitive rather than level sen·
sitive, a program which services an interrupt request from the LANCE must
either service all the conditions which contributed to the setting of the INTR
bit in NI_CSRO so that INTR becomes 0, or must generate another transition
ThinWlre Ethernet (OESVA) Option Module

5-29

of the interrupt signal by setting the INEA bit of NI_CSRO to 0 and then back
to 1 again. Interrupt number 4, the "network controller secondary" source,
is not used by this option.)

5.10 Initialization Block
When the LANCE chip is initialized (by setting the INIT bit in NI CSRO),
it reads a 24-byte block of data called the initialization block from main
memory usin~ DMA accesses. The physical address of the initialization
block (IADR) IS taken from NI CSRI and NI CSR2. Since the data must be
word-aligned, the low-order bit of the address must be O. The initialization
block comprises twelve 16-bit words arranged as shown in Figure 5-11.
Figure 5-11: LANCE Initialization Block Format

IADR + 0

MODE

IADR + 2

PADR <16:00>

IADR + 4

PADR <31: 16>

IADR + 6

PADR <47:32>

IADR + 8

LADRF <16: 00>

IADR + 10

LADRF <31: 16>

IADR + 12

LADRF <47: 32>

IADR + 14

LADRF <63: 48>

IADR + 16

RDRA <16:00>

lADR + 18

RLEN

TDRA <16:00>

ADR + 20
ADI + 22

I RDRA <23:16>

TLEN

I TDRA <23:16>

5-30 VAXstation 2000 and MicroVAX 2000 Technical Manual

5.10.1 Initialization Block MODE Word (NIB_MODE)
The mode word of the initialization block allows alteration of the LANCE
chip's normal operation for testing and special applications. For normal
operation the mode word is entirely O. Figure 5-12 shows the initialization
block mode word.
Figure 5-12:
16

Initialization Block Mode Word (NIB.MODE)

PROM

)

RESERVED

RESV

INTL

DiTY

COLL

DrCR

LOOP

DTX

DRX

Bit

Definition

PROM

Promiscuous mode (bit 15). When this bit is set, an incoming packets
are accepted regardless of their destination addresses.

<14:7>

Reserved. Should be written with O's.

INTL

Intemal Joopback (bit 6). This bit is used in conjunction with the
LOOP bit in this word to controlloopback operation. See the description of the LOOP bit within this figure.

ORTY

Disable retry (bit 5). When this bit is set, the chip attempts only one
transmission of a packet. If there is a collision on the first transmission attempt, a retry error (RTRY) is reported in the transmit buffer
descriptor,

COLL

Force collision (bit 4), Setting this bit anows the collision Jogic to be
tested. The chip must be in internal Joopback mode for COLL to be
used. When COLL is 1 a collision is forced during the subsequent
transmission attempt. This results in 16 total transmission attempts
with a retry error reported in NI.TM03.

OTCR

Disable transmit CRC (bit 3). When OTCR is 0 the transmitter generates and appends a 4-byte CRC to each transmitted packet(normal
operation). When OTCR is 1, the CRC logic is allocated instead to the
receiver and no CRC is sent with a transmitted packet.

ThlnWlre Ethernet (DESVA) Option Module

5-31

Bit

Definition

During loopback, setting DTCR to 0 causes a CRC to be generated and
sent with the transmitted packet, but no CRC check can be done by
the receiver since the CRC logic is shared and cannot both generate
and check a CRC at the same time. The CRC transmitted with the
racket is received and written into memory following the data where
it can be checked by software.
If DTCR is set to 1 during loopback, the driving software must compute and append a CRC value to the data to be transmitted. The
receiver checks this CRC upon reception and report any error.

LOOP

Loopback control (bit 2). Loopback allows the LANCE chip to operate
in fun duplex mode for test purposes. The maximum packet size is
limited to 32 data bytes (in addition to which 4 CRC bytes may be
appended). During loopback. the runt packet filter is disabled because
the maximum packet is forced to be smaller than the minimum size
Ethernet packet (64 bytes).
Setting LOOP to 1 allows simultaneous transmission and reception for
a packet constrained to fit within the silo. The chip waits until the
entire packet is in the silo before beginning serial transmission. The
incoming data stream fills the silo from behind as it is being emptied.
Moving the received packet out of the silo into memory does not begin
until reception has ceased.
In l00pback mode, transmit data chaining is not possible. Receive
data chaining is allowed regardless of the receive buffer length. (In
normal operation, the receive buffers must be 64 bytes long, to allow
time for buffer lookahead.)
Valid loopback bit settings are as follows:

Loop

INTL

Operation

Normal on-line operation

Externalloopback

Internal loopback

Internalloopback allows the chip to receive its own transmitted packet
without disturbing the network. The chip does not receive any packets
from the network while it is in internalloopback mode.

5-32

VAXstation 2000 and MlcroVAX 2000 Technical Manual

Bit

Definition
External loopback allows the chip to transmit a packet through the
transceiver out to the network cable to check the operability of all
drcuits and connections between the lANCE chip and the network
cable. Multicast addressing in externalloopback is valid only when
DTCR is one (user needs to append the 4 CRC bytes). In external
l00pback, the Chip also receives packets from other nodes.

DTX

Disable transmitter (bit 1). If this bit is set, the chip does not set
the TXON bit in NJ.CSRO at the completion of initialization. This
prevents the LANCE chip from attempting to access the transmit descriptor ring; hence no transmissions are attempted.

DRX

Disable receiver (bit 0). If this bit is set, the chip does not set the
RXON bit in Nl. CSRO at the completion of initialization. This causes
the chip to reject all incoming packets and to refrain from attempting
to access the receive descriptor ring.

5.10.2 Network Physical Address (NIB_PADR)
The 48-bit physical Ethernet network node address is contained in bytes 2:7
of the initialization block. (This is a network address; it has no relationship
to any memory address.) Figure 5-13 shows the network physical address.

Figure 5-13: Network Physical Address (NIB.PADR)

I <---IADR+6---> I <---IADR+4---> I <---IADR+2---> I
47

32 31

16 15

10 1
The contents of NIB PADR identify this station to the network and must be
unique within the domain of the network. Its value is normally taken from
the network address ROM. The low-order bit (bit 0) of this address must be
since it is a physical address.

ThlnWire Ethernet (OESVA) Option Module 5-33

)

5.10.3 Multicast Address Filter Mask (NIB _LADRF)
of the initialization bbclr; contain the 64 ,bit multicast addness fiI·
te.r mask The multicast address. HIler is a
filter which assists the
ner.Nork (ontroller driver program to
receive packets \vhich contain multicast nehvork addresses
14 shows the
address
mask
Figure 5-14:

Multicast Address Filter Mask (NIB}.. AORF}

! <-IADR+ 14-> I <-lADR'" 12-> i <-!ADR.tler---> I <-lADR·e~-) I
63

48 41

32 31

15 15

fv1ulticast Ethernet addresses are distinguish€d €torn physical netvvork ad·
dresses
the
ofa 1 iI, bit (I {If thf 48·bH ,uidress field. If an
incoming packet contains a physical destination addrt;;'ss (bit 0 is 0), then its
entire 48 bits are compared vdth the contents of NIB}' ADR and the packet
is ignored if they are not equal. if the packet con!ains a multicast destination
address which is
1 's (the broadcast
it is
and

stored

of the contents of the multicast address

An other multicast addres:::,es are
filter to determine whether the incommg
i.s
In a receivet!l..lH12'L
is p;:rformed
" t h e ,mullicast address field
the
1 he
6 bIts of the
one of the 64 bits of N.IB LADRF.
in binary the number of the bit-in t\!.!B
, ","'-"U'';'"
figure 15·10.) If the

frorn NIBJ,ADRF is L

packet is stcred

in a receive buffer; othen\'ise it is ignored. TI.115 mechanism effectively
the entire domain of 2""47 multicast addresseR into 64
and

falling into each
ate
v21lue of the corresponding
in :-JIB.
driver prog.nml must
exan11ne the addresses of the packets accepted by this partial filtering to
the
task.

5-34

V,A'xsta!ion 2000 and MlcroVAX 2000 Techmcal Manual

5.10.4 Receive Descriptor Ring Pointer (NIB_RDRP)
Bytes 16:19 of the initialization block describe the starting address and extent
of the receive descriptor ring. Figure 5-15 shows the receive deSCriptor ring
pointer.
Figure 5-15: Receive Descriptor Ring Pointer (NIB RDRP)

I <:---IADR+18---> I <---IADR+16---> I
31

29 28

24 23

16 16

RDRA

)
RLEN

)

000\

Receive ring length (bits 31 :29). This field gives the number of entries
in the receive descriptor ring, expressed as a power of 2:

RLEN

Entries

3
4

8
16

128

28:24

Reserved; should be O's.

RORA

Receive descriptor ring address (bits 23:0). This is the physical address
in system memory of the first element in the ring. Since each 8-byte
element must be aligned on a quadword boundary, bits 2:0 of this
address must be O.

ThlnWire Ethernet (OESVA) Option Module

5-35

5.10.5 Transmit Descriptor Ring Pointer (NIB_TDRP)
Bytes 20:23 of the initialization block describe the starting address and extent
of the transmit descriptor ring. Figure 5-16 shows the transmit descriptor
ring pointer.
Figure 5-16: Transmit Descriptor Ring Pointer (NIB_TDRP)

I <---IADR+22:---> I <---IADR+201---> I
31

29 28

24 23

I TLEN I RESV I
TLEN

16 16
TDRA

0001

Transmit ring length (bits 31:29). This field gives the number of entries in the transmit deSCriptor ring, expressed as a power of 2:

TLEN

Entries

128

<28:24>

Reserved; should be O's.

TDRA

Transmit descriptor ring address (bits 23:0). This is the physical address in system memory of the first element in the ring. Since each
8-byte element must be aligned on a quadword boundary, bits 2:0 of
this address must be O.

5-36 VAXstatlon 2000 and MicroVAX 2000 Technical Manual

5.11 Buffer Management
The LANCE <hip manages its da,ta buffers by using tV10 rings< of buffer d<:scriptors that are stored IJ.I
the receive descriptor ring and the
transmit descriptor ring. Each buffer descriptor points to a data buffer else·
where in memorv, contains the size of that buffer, and contains statu£' In·
formation about that buffer! s contents.
.
The starting location in memory of each ring and the number of descriptG)"s
in it are given to the LANCE chip through the initlaHz,ation block during
the chip initialization process. Each descriptor is 8 bytes long cmd must be
aligned on a quad-word boundary tthe three low-ordN bits of its address
must be OJ. The descriptors in it ring arephyslcalJy contiguous in 111emory
and the number of descriptors must be a povver of 2, The LAl'~CE keeps:
an in!t'mal index to its cu.rrent position in each ring \vhich if increments
modulo the number of descriptors ifl the ring a.s it advances around each

Once started, the
pnlls each ring to find descriptors for buffers
in which to receive incoming packets and ff(~m ,,,,hieh tCI transmit
ing packets, and revises the status information in buffer descriptors as it
processes their associated buffers.
polling. the LANCE is limited 10
lookin.g only one ahea.d of the descriptor with \l1"hieh it is currently
The high speed of the data stream requires that each buffer be at least
bytes long to al101.v time to chain buffers for pad:.ets which are larger than
one buffeT, (The first t'<uHer of a packet to be transmitted should be at least
100 bytes to avoid problems in ca.se a late collision Is detected)
Each descriptor in a ring is·'mvned'' either by the LANCE chip or
the hosl
processor; thls status is indicated bV the O\IVN bit in each descrilJior. hlutLla!
exclusion is accomplished by the rule that each device can oni y relinquish
mvnership of a descriptor to the other device, it can never take ownership.:
and thai each device cannot change any field in a descriptor or its associated
buffer after it h.1S relinquished N'Yt1ership. \Vhen the host nn",;',",,,,
the rings of descriptors before starting the Littler, It sets the
that the LANCE O\A'T\S all the descriptors in the rece.ive ,",<'"·~r..,.".",
be used by the
to H~cdve
from the netv,ork) and thE'
owns all the d~'s(tiptors in the transmit deSCriptor ring (to
usC'd by !I\c'
host t.G set up packett, to be transmHh:·d to the network).

ThlnWire

(DESVA) Option Mociu!€:

5<~7

5.11.1 Receive Buffer Descriptor
A receive buffer descriptor comprises. four \'\fords aligned in memory on a
quad-word
boundary. See Figure
.

Figure 5-11: Receive Buffer Descriptor
KtMOlI;Y

Ol'fll!i
I t I I t 1

& 432 ! 0 I I , I 5 , 3 2 I 0

+2:

! 1 I li

o !)

.L\DR

Low-order buffer address (offset 0, bils
TI1!'se are the low-order
16 bits of the 24·bit
address of the start. \:>! the buHer
associated \\i'Hit this n"·<r'n!,.,t'~,.
the host;
the LANCE.

HAD.R
assl.xiated with
the LANCE.
OWN

(offset 2, bi.t 15) This bit indicat.es wheth'i'r th€ "",c,",',,,,_
!ht' host (O\'tN '" 0) or bv \he l}\NCE
OVVN after
the -buifer assol:iat",d;",·it.h the
with a.n incoming
hosi :sets OV\''N after t'mptybuffer. In eiKh case, thiS must be the last bil
th;;·
current owner, sinn? chancing o',\rN passes
to the other
and the relinquishing party row,t not thereafjer nlief
descriptor l)r its buffer.

ERR

Error. Sl.l1nmarv (oHsf't 2. bit
ThiS is the
eRe and flUfF Cits in this \"Ofd,

dea.red

OR of the

th.t' LANCE and

the host.

FF;AM
stOf(1d :in l'hcJ buHer has beth (1 nor\"
<lnd i.i (~RC' error, It is Clet1rc d
tbe
1

host.

5-38

V.A'xslation 2000 and MiCro\lAX2000 Tecl1rdcal~,.1anual

ORO

Overflow error \()Hset 2. bH
This bit is set
indics.te that the receiver has lost part or aU of an
because it could l'Ot store 11 in the buffer before the
flowed. Cleared
tbe host.

eRe

Checksum em,f (offset 2, bit 11). This bit is St~t
dicate that the received packet has an invalid
by the ho:;!

SUFF

Buffer error (offset 2. bit WI. This bH is set bv the LANCE when it
has used aU its owned receive descriptors or when it w\dd not
lht:
next descriptor in tirne while attempting TO chain 10 a I"lf'W
if'!
the midst of a pac:kf:'t ''''hen a buffer error OCCUIS. an overf!o\', enol'
(bit OFLOi also occurs because the L<\NCE continues to attempt tC\
the next buffer until hs silo (riierHows, BUFF is cleared by the h.o:sr

STP

Start of
that this

ENP

End of racket (offset 2, bit ,s,J. Tnis bit is set by the Lt>.NCE to indi·
cate thaI thiS i~, the last buffer used for t.hIs pacl;eLWh!?r'. both STP
and ENP are S(:t in a descriptor, its buffer contains an el1tln~ packt'l;
otherwise I,vo or nvm:; buffers have been chai.n('d
to held the
packet, ENP is cleared
the hC!Bt.

1111

Offset 4, bits 15:11 muM. be set 'by the host tc) 1'$, Unchanged by the
LANCE.

BeNT

Buffer 811:(' (offset 4. bits 11 ;0). This is the number of
buffer (\vhos€' startin.g a.ddn:$s Is iii HADR and LI\DR) in
men! form. Note that lhe minimum buffer size .is 64 bVH:'S and
the maximum rt'quired for a
packet is 1518
\Vritten
the
host; und1anged. by the

oo."Kl

Offset 6, bits 15:12 at'e
the\, should be set 1(l0'S,
whe.n it (onstructs the deSCriptor. .

MCNT

Byte count (offset 6, bits 11
received

(offset 2, bit 9}. Thi£. bit is set
the first bUffe! used for this

the LA.NCf to Inchecksum. Cleared

!.he LA.NCE tet ind.icale
Cleared
the h05: .

the host

This is Ih{' length .in
of th,'
for which this is the last Ot only descrirlor MO"';1" js
tn a desn/phll' in which ENP .15 Sf'l das: but'h;f; and ERF if'

valid
dear (no error). Set by the LANef'; and cleared

Elhemet

thE' host.

5.11.2 Transmit Buffer Descriptor
A transmit buffer descriptor comprises four words aligned in memory on a
quad-word address boundary. See Figure 5-18.
Figure 5-18: Transmit Buffer Descriptor
MEMORY
OFFSET

111111
5 .. 3 2 109 8 1 8 5 .. 3 2 1 0

LAoa

+0:

+2:

OErMOOSE
IlR.ONETN
Nl.lEFPP
v E

+4:

1 1 1 11

+6:

BUr L L III
UF.CCT
FL. 0 " R
FOvLItY

HADl

BeNT

TOa

LADR

Low-order buffer address (offset 0, bits 15:0). These are the low-order
16 bits of the 24-bit physical memory address of the start of the buffer
associated with this descriptor. Written by the host; unchanged by
the LANCE.

HADR

High-order buffer address (offset 2, bits 7:0). These are the high-order
8 bits of the 24-bit physical memory address of the start of the buffer
associated with this descriptor. Written by the host; unchanged by
the LANCE.

OWN

Owned flag (offset 2, bit 15). This bit indicates whether the descriptor
is owned by the host (OWN = 0) or by the LANCE (OWN = 1). The
host sets OWN after filling the buffer with a packet to be transmitted.
The LANCE dears OWN after transmitting the contents of the buffer.
In each case, this must be the last bit changed by the current owner,
since Changing OWN passes ownership to the other party and the relinquishing party must not thereafter alter anything in the descriptor
or its buffer.

ERR

Error summary (offset 2, bit 14). This is the logical OR of the lCOl,
lCAR, UFLO and RTRY bits in this descriptor. Set by the LANCE and
cleared by the host.

Resv

Offset 2, bit 13 is reserved. The LANCE writes a 0 in this bit.

5-40 VAXstation 2000 and MlcroVAX 2000 Technical Manual

)

More retries (offset 2, bit 12). The LANCE sets this bit when more
than one retry was required to transmit the packet. Cleared by the
host.

ONE

One retry (offset 2, hit 11). The LANCE sets this bit when exactly one
retry was required to transmit the packet. Cleared by the host.

DEF

Deferred (offset 2, bit 10). The LANCE sets this bit when it had
to defer while trying to transmit the packet. This occurs when the
network is busy when the LANCE is ready to transmit. Cleared by
the host.

STP

Start of packet (offset 2, bit 9). This bit is set by the host to indicate
that this is the first buffer used for this packet. STP is not changed
by the LANCE.

ENP

End of packet <offset 2, bit 8). This bit is set by the host to indicate that
this is the last buffer used for this packet. When both STP and ENP
are set in a descriptor, its buffer contains an entire packet; otherwise
two or more buffers have been chained together to hold the packet.
ENP is not changed by the LANCE.

1111

Offset 4, bits 15:12 must be set by the host to l's. Unchanged by the
LANCE.

BCNT

Byte count (offset 4, bits 11:0). This is the number of bytes, in 2's complement form, which the LANCE transmits from this buffer. Note
that for any buffer which is not the last of a packet, at least 64 bytes
(100 bytes if it is the start of the packet) must be transmitted to allow
adequate time for the LANCE to acquire the next buffer. Written by
the host; unchanged by the LANCE.

NOTE: The remaining fields of the descriptor (which make up its entire fourtlt ulOrd)
are valid only when the ERR bit in the second word has been set by the LANCE.
BUFF

Buffer error (offset 6, bit 15). This bit is set by the LANCE during
transmission when it does not find the ENP bit set in the current
descriptor and it does not own the next descriptor. When BUFF is
set, the UFLO bit (below) is also set because the LANCE continues to
transmit until its sUo becomes empty. BUFF is cleared by the host.

UFLO

Underflow (offset 6, bit 14), This bit is set by the LANCE when it
truncates a packet being transmitted because it has drained Hs silo
before it was able to obtain additional data from a buffer in memory.
UFLO is cleared by the host.

Resv

Offset 6, bit 13 is reserved. The LANCE writes a 0 in this bit.

ThlnWlre Ethernet (OESVA) Option Module

)

5-41

LeOL

Late coilision (oft""t b. bit J21
This: bit i~ ~",t by thE' LI"\NCE to indic;!te thid il eomsion h,1S o';:,:mrr<:i aibtr ltw sklt U.m'! of th",
network (hann"l hil/>
Th" U\NCE 1l('li'5 n(i!. retry af,
ter. a lab: col!.iRiI.T!'. LCOL is
tfH: hlJ~t

LeAR

This bit is set
the LANCE when
hecomes false
il tramm.!»·
skm initiated by the LANCE, The
does no~ retry aller such <l
failure, LCAR IS cleared by the hoe!.

Loss of carrier (offset &, bit

th~ carrier-present input to the

RTRY

Retries f'xha1.lsted (offset 6, bit 10). This bit is set
"16 attempls to transmit a packet have failed due to
colli~i01'$
on the network. (II Ihe DRn" bit of the
block MODE
word is set. RTRY is set instead after only oni)' one failed transmission
attempC) RTRY is cleared by the host.

TDR

Time domain refleclometer (offset 6. bits
These pHs are the
va.lue of an iniema! counter which IS set bv the U,. NCE to counl
docks from the start of a u."ansmiss.!o!\ to the OC(UrretKE: of a
collision, This value is usef'.l!' in
to 1:1 cable fault: it is valid
when the

5.12 LANCE Operation
The. LANCE chip operates independently of the host under control
its
own internal microprogram, These microcode routines make use of numerous temporary storage ceUs w.ithin the
chip: most of the$e are not
accessible from outside the chip but
are mentioned here\\lhen necessary to darify' the operation of the microcode,
1'v,;o such (conceptual! mternal
pOinter to the "Cllrrent~'
in
the transmit descriptor ring. These variables are r<>i'pnrp("1
as TXT' and RXr. Each of these designates the
uses for the next operation of that type. If the

the LA~CE

bv om~

the LANCE
0), then the
LANCE can neither perform
of that type nor advance the
the transmit
the
does nothing until the nl)st sets
in the
and sets the
in the
Lance's TXT'. (The host must keep track of the
setting up iii:
in some other deSCriptor is not
For the
if t.he LANCE doE'S' not own the
by RXr, it cannot re(e1V~~ i:l packet. In both
Ivhen the
wilh a descriptor and relinquishes it to the host
advances the
pointer (modulo the number
of these pointers is not owned

5-42

VAXstation 2000 and MlcroVAX 2000 Technica! Manual

When the LANCE begins activity using the current descriptor (the LANCE
begins receiving or transmitting a packet), it may look ahead at the next
descriptor and attempt to read its first three words in advance so it can
chain to the next buffer in mid-packet without losing data. However, it does
not actually advance its RXP or TXP until it has cleared the OWN bit in the
current descriptor.

5.12.1 Switch Routine

)

At power-on, the STOP bit is set and the INIT and STRT bits are deared in
NI.CSRO. The LANCE microprogram begins execution in the switch routine,
which tests the INIT, STRT, and STOP bits. When the host sets either INIT
or STRT, STOP is cleared. If the host writes to NI CSRl and NI CSR2 while
STOP is set, that data is stored for use by the initialization roufine.
When the microprogram sees STOP cleared, it tests first the INIT bit and
then the STRT bit. If INIT is set, it performs the initialization routine. Then
if STRT is set, it begins active chip operation by jumping to the look-forwork routine. Control returns to the switch routine whenever the host again
sets the STOP bit (which also clears the INIT and STRT bits). Note that the
ring pointers RXP and TXP are not altered by the setting of either STOP or
START; they are reset to the start of their rings only when INIT is set.

5.12.2 Initialization Routine
The initialization routine is called from the switch routine when the latter
finds the INIT bit set. It reads the initialization block from the memory
addressed by NI_CSRl and NI.CSR2 and stores its data within the LANCE
chip. This routine also sets the ring pointers RXP and TXP to the start of
their rings (that is, at the lowest memory address in the ring).

5.12.3 Look-For-Work Routine
The look-for-work routine is executed while the LANCE is active and looking
for work. It is entered from the switch routine when the STRT bit is set,
and is returned to from the receive and transmit routines after they have
received or transmitted a packet.
This routine begins by testing whether the receiver is enabled (bit RXON of
NI CSRO is set). If so, it tries to have a receive buffer available for immediate
use when a packet addressed to this system arrives. The routine tests its
internal registers to see whether it has already found a receive deSCriptor
owned by the LANCE and, if not, calls the receive poll routine to attempt
to get a receive buffer.

ThinWire Ethernet (DESVA) Option Module

5-43

Next the mutlnt' t€stO' \\'hl::'tl1er the tra!1smlHet is enabled (bit
CSRO is set), U so, it C<lUS the transmit pl-lll routine to see

a packet to be transmitted, If a
tranSl11lts it

of NI
there

the transmit poB routine

If there is 11(1 transmission and the '1'D1\1D bit of
is not set, the
micmpmgram
1,6 rnilliseconds and then goes to check the receive
descriptor status again. if a packet \·vas transmitted or the host
set
rDMD. the delay is omitted 50
are transmitted as
quickly as possible.
If at any point in this routine the receiver detects an

destination address matches the station's physicaJ
broadcast address, or passes the multicast addxe"s fllter
of NIB MODE I!.'
the receive routine is called,

packet
or matches the
if the
bit

5.12,4 Receive Poll Routine
The receive poll routine is called whenever the receiver is
ilnd the
LANCE needs a
buffer from the receive descriptor ring. The routine
reads the second word of the
designated bv RXr and, jf the Cn'VN
bit the second word is set, the
read;' the first <lnd third 1Nords also

5.12.5 Receive Routine
The receive routine is called when the receiver is enabled and an
packet s
address field matches one of the criteria
Section 5.12.3. The fQuti.ne has three sections: initialization.
and
whether a receive
the Ieee!v€' pon routine. If
descriptor designated
RXP
and ERR are set in NI
buffer thus acquired is
the ""'(""'''''",

descriptor has
it makes Ofle
is not get in the
is tost). The
the

In lookaheild. the wuline feads the second word of the next
the receive
and, if the O\\!'t'J bit is set, re"d" the rest (yf the
for
and holds it in
da~a
The descriptor update section is performed \,,;hen either
current buffer
.is filled or the paCKet ends. If the packet ~mds but its total length is less than
64
it is an erroneous nmt packet ,md is ignored: no status is
in the descriptor. RXP is notm.oved, and the buHE'f is reused for
incoming packet (this is why a receive buffer must be at least 64
othervvjse the runt might bk' detected after

5-44

VAXstatlon 2000 and MicroVAX

Technical r.,"anuai

If the packet ends (with or without error), the routine writes the packet length
into MCNT, sets ENP and other appropriate status bits and dears O\VN in
the current descriptor, and sets RINT in NI.CSRO to signal the host that a
complete packet has been received. Then it advances RXP and returns to
the look-for-work routine.

If the buffer is full and the packet has not ended, chaining is required. The
routine releases the current buffer by writing status bits into its deSCriptor
(clearing OWN and ENP, in particular), makes current the next deSCriptor
data acquired in the lookahead section, advances RXP, and goes to the lookahead section to prepare for possible additional chaining. Note that RINT is
not set in NISSRO, although the host would find OWN cleared if it looked
at the descriptor, and it could begin work on that section of the packet, since
the mutual exclusion rule prevents the LANCE from going back and altering
it.

5.12.6 Receive DMA Routine
The receive DMA routine is invoked asynchronously by the chip hardware
during execution of the receive routine whenever the silo contains 16 or
more bytes of incoming data or when the packet ends and the silo is not
empty. It executes DMA cycles to drain data from the silo into the buffer
designated by the current descriptor.

5.12.7 Transmit Poll Routine
The transmit poll routine is called by the look-for-work routine to see
whether a packet is ready for transmission. It reads the second word of
the descriptor designated by TXP and tests the OWN bit. If OWN is 0, the
LANCE does not own the buffer and this routine returns to its caller. If
OWN is set, the routine tests the STP bit, which should be set to indicate
the start of a packet. If STP is clear, this is an invalid packet; the LANCE
sets its OWN bit to return it to the host, sets TINT in NI CSRO to notify
the host, and advances TXP to the next transmit descriptor. If both OWN
and STP are set, this is the beginning of a packet, so the transmit poll routine reads the rest of the descriptor and then calls the transmit routine to
transmit the packet. During this time the chip is still watching for incoming
packets from the network and it aborts the transmit operation if one arrives.

ThinWire Ethernet (DESVA) Option Module 5-45

5,12.8 Transmit Routine
The transmit routine is ('ailed from the transmit poll routine when the latter
finds the start of a packet to be transmitted. The transmit routine has
sections: initialization, lookahead. and descriptor update,
In initialization. the routine sets the chip':,; internal buffer
and
count from the transmit descriptor. enables the transmit DMA engIne.
starts transmission of the packet preamble. It then waits until the transmit·
ter is actually sending the bit stream
backoH.al1d·retry
actions in case of collisions).
In lookahead, the transmit routine tests the current descriptor to see whether
it is the last in the packet (Ihe ENP bit is
!f so., no addihonal buffer .is
required so the routine wa.its until aU the
from the current
have
beE'n tran::mitted. If not., the routine attempt:? to
the next
ond
hold it in
tor data chaining, and then waits until ail the
the current buffer have been transmitted.
Descriptor update is entered when all the
from a
have been
transmitted or an error has occurred, If there no error and the buffer 'INas
not the
of the packet, the pre-fetched descriptor for the next buffer is
made current for use by the transmit DMA routine., The routine wntes the
appropriate status bits and
the
bits in the current descriptor
and advances TXP. If this ,vas the last buffer in the
the routine sets
the lINT bit in NCCSRU to
the host ,md returns to the look·fm·work
otherwise it
bi'lck to the l()okahei~d secUC'11 in this murine.

5,12.9 Transmit OMA Routine
The transmit DMA routine is invoked
bv the
hardware
during execution of the tran5mit routine ,vhenever
'silo has
or more
empt}'
It executes Dt'vIA cycles to fill the sUo \vith data from the buffer
designated by the current descriptor.

5,12.10 CoHision Detect Routine
cution of the transmit
It (~nsures th"t the

sequence is
and bvte cot.:n.t
and then aHem[;t5 the iransrnission
attempts fail (a total of 1 6 '
it sends
tor update routine to
HTlr'; and EIU{ are

5-46

and

5.13 LANCE Programming Notes
}, The interrupt signal is the OR of the interrupH:ausing conditions If
another such condition occurs white the interrupt signal is already as·
serted, there is not another active transition of the interrupt signal and
the interrupt requi'st bit in INT.REQ is not set again. An interrupt ser·
vice routine should use logic similar to the following 10 avoid losing
interrupts:

Read NI_CSRO and save the results in a register (for example,

•

Clear the interrupt enable bit INEA in the M.ved data in RO.

•

Write Nt CSRO witb the saved data in RO:. This makes the interrupt
signal faJse because INEA is dear and dears: aU th{~ \vrl.te·one·I.o·
does
reset bits such as RINT, TINT and the error bits,; this
not aHer the 5THT, INIT or STOP bits nor any interrupt-cause bits
\'Vhich come true after NI CSRO \,'as read.

Write NI C5RO with only INE.A to enable interrupts again.

•

Service all the interrupt and error conditions indicated by the flags
in the. data in RO.

•

Exit from the interrupt service routine.

Be sure to access Nl C5RO only '\<\rifh instructions which do a single

access, such as MOVE . Instructions such as SIS ",'hieh do a re~d
modify-write operation can have unintended side effects.

2. An interrupt is signaHed to the host only when the last buffer of a mulh
buffer (chained) packet is received or transmitted. However., the
bit in each descrlptor is cleared as soon as thE! LANCE has finished \vith
that portion of the packet, and the mutua! exclusion rule makes it safe
is descriptor and ils buffer
ior the host to

3. \Vhen a transmitter underflow occurs (Uf;LO is set in iii transmit
t'')t because the silo is not filied fast enough), the LANCE tums off
transmitter and the

must be restarted fo turn the transmitter

This ran be done by, setting STOP in Nl.CSRO and th~::n
in NI CSRO (DTX is still deatin the chip's internal
MODE). It not
to set INIT to ren'ad the initialization

back on

that setting
imm€dbtely terminates an)'
which is
in progless, If the status of a receive descriptor has beerl updat.ed and
its O'iNN bit is iWIN
then the contents of its
,He valid. If the
was chained ml'o {non: than one
. hov·,'e\'e1'. !he

Th!n\l\/iie Ethernet (DES VAl

Module

5-47

packet is only valid if its last buffer has been completed (the one with
the ENP bit set).
4. The network controller hardware requires up to five seconds after power
on to become stable. Self-test routines must delay at least five seconds
before attempting to use the controller for either internal or external
testing.
5. The LCAR flag (loss of carrier) may be set in the transmit descriptor
when a packet is sent in internal loopback mode. When the LANCE
is operating in internalloopback mode and a transmission is attempted
with a non-matching address, the LANCE correctly rejects that packet. If
the next operation is an internal loop back transmission, and the LANCE
has not been reset, the packet is not sent and LCAR is set in the transmit
deSCriptor for that packet. The receive deSCriptor is still owned by the
LANCE. To avoid this problem, the LANCE should be reinitiaIized after
each internalloopback packet.
6. The one flag is occasionally set in a transmit descriptor after a late collision. The LANCE does not attempt a retransmission even though one
may be set. The host should disregard one if the LCOl flag is also set.
7. The chip's internal copy of NI.CSRI may become invalid when the
chip is stopped. The NI.CSRI and NI.CSR2 registers should always
be loaded prior to setting INIT to initialize the LANCE chip.
8. Attempting an external loopback test on a busy network can cause a
silo pointer misalignment if a transmit abort occurs while the chip was
preparing to transmit the loopback packet. The resulting retransmission
may cause the transmitter enable circuit to hang, and the resulting illegal length transmission must be terminated by the jabber timer in the
transceiver. It is unlikely that there may be a corrupted receive buffer
because the reception that caused the transmit abort usually does not
pass address recognition.
Since externalloopback is a controlled situation, it is possible to implement a software procedure to detect a silo pointer misalignment problem and prevent continuous transmissions. Because the test is being
done in loopback, the exact length and contents of the receive packet
are known; thus the software can determine whether the data in the
receive buffer has been corrupted.
9. When the chip is in intemalloopback mode and a CRe error is forced,
a framing error is indicated along with the CRC error. In external loopback, when a CRC error is forced only that error is indicated; a framing
error is indicated only if the LANCE actually receives extra bits.

5-48 VAXstation 2000 and MlcroVAX 2000 Technical Manual

10. When transmit data chaining, a BUFF error is set in the current transmit
descriptor if a late collision or retry error occurred while the LANCE
was still transmitting data from the previous buffer. The BUFF error in
this case is an invalid error indication and should be ignored. BUFF is
valid only when UFLO is also set.
11. When the host program sets up a packet for transmission in chained
buffers, it should set the OWN bits in all the transmit buffers except the
first one (that is, the one containing the STP bit), and then as its last act,
the host program should set the OWN bit in the first descriptor. Once
that bit is set, the LANCE starts packet transmission and may encounter
an underflow error if the subsequent descriptors for the packet are not
available.
12. INIT and STRT should not be set in NI CSRO at the same time. After
stopping the chip, first set INIT and wa1t for IDON, then set STRT. If
both are set at once, corrupt transmit or receive packets can be generated
if RENA becomes true during the initialization process.

5.14 Power Requirements
The DESVA requires 5 volts with a tolerance of plus or minus five percent.
The typical current drawn is 1.0 amps.

)

ThlnWire Ethernet (OESVA) Option Module 5-49

Chapter 6

Resistor Load Module

)

The system box must use a resistor load module when less than two drives
are installed. The resistor load module regulates the power supply in the
expansion boxes when only one drive is installed in each box. The power
supply needs a minimum amount of current drawn for it to regulate properly. The single disk in the hard disk expansion box and the tape drive with
the controller board in the tape expansion box do not draw enough current
for the power supply to regulate. The resistor load module is installed in
these boxes to draw a sufficient amount of current to allow the power supply to regulate properly. Figure 6-1 shows the resistor load module and
Figure 6-2 shows the circuit diagram of the resistor load module.
The +5 Vdc portion of the load module draws 3 Amps and the + 12 Vdc
portion draws 1 Amp. The module measures 1 inches (1".8mm) by 4
Inches (101.6mm).

ReSistor Load Module 6-1

ffi{I[

m1
~
~

~
~
~
m:J

":e
".9as
0

a..

0
tn

"iii
CD

,...
t
CoD
CD
a..

:::t
01

J- EE{It
J- m1
J- m1
J- m1
J- m1

...J

iii
UJ

0::

{Q!D

J- ~
J- ~
J- ~
J- ~
J- ~
l-+

::;)

III

ffi{I[

m1
m1
8 m1
«
m1
I-

l- EB[I(
l-

UJ:}

....e>

Is
I

z;r

lI-

JJJJJ-

lD
><
I

::II

Q?DB
Q!}B
;::]!}a
~

i:E)B

-D.EJe

Q[)B

i:EJrs

GE)B

{]DI

EE{It

JJ-

m1
m1

JJJJJ-

JJ-

EBI

m1
~

6-2 VAXstatlon 2000 and MlcroVAX 2000 Technical Manual

Figure 6-2:

Resistor Load Module Circuit Diagram

II.

+S II

+12 V

2
1

r-2
1

'--

U-J
L!-J
:IJ
CD

(/)

iii

..""

::: to 1.1'
3511

24/\

24A

r.A

.22 1.1'
11011

241\

:-./\

'" :~

24A

24A
2.

24/\

24A
2.

fw" • .. .221.1'

to I.I'A

1110 A

150 A

1.A ;:

.22 1.1'

150/\
2.

150 A

3511

50Y

150 A

.aoA
2.

150 A

I.A ;:

.22 1.1'

50Y

r- 101.1'
3511

241\

;;..

.221.1'
IIOY

IIOV

01\

o....

o
a.

I»

3:
o
a.
c:

(j)

en
Co)

M
01\
WID
01\

31111
0WA

Chapter 7

Power Supply
7.1 Introduction
The V5410 system box and each VS40B storage expansion b(IX are powered
by an H7848 pmver supply. !v1odel H7848-AA is for nominal 115 V input and
model. H7848,AB is for nomin.al 230 V lnput. The power supply assembly
indudes an <lC
connector, an ac power 1l\vitch, and a variablE-speed
cooling fan.

7.2 AC Input
Single-phase ac power is supplied through a 3-pin me 320 C14 connector
for a ECC02·xx po,",'er cord, where the variable is appropriate to natjonal
usage. Table 7-1 lists the input power specifications.

Model
Minimum
Nominal
Maximum
-------_._-----,_._--_.
---- --_._---------'

Input voltage (single phasei

H784$·BA
H7848-B8

176

100., 12G

132 Ve.(' rms

220., 2.fO

264. Var rm"

Freqtlency
·BA ilnd -BB

Miscellaneous
Power I.nptH: 160 wal!.sma.1o:imum,

P(w;er f.;lctor: 0.6 minimllrn.

Power

7-1

Table 1-1 (Cant.): AC Input Specifics
"",~

... _

....

'"'~

_ _

... _ _

~,_

en~"~.

Minimum

Model

_,,,.-,-.,,,,.,,,,.,.,,,,,,,,,,,..

_,~,_,.,

........ ,,,, _ _

Nominal

-------------_.------------Inrush <:urrent: 32 amps ll\axirmll'H for Qne·h·alf AC

~_~~_~_

.....

.....,.,-,",,,~,"

.....

_,,,_..,.,~_.~

_ _ _ ""

Maximum

------_._-

Steady sta.te RMS current:

2A amps in 100-J20 vol! range
1.3 amps in 220-240 volt range

7.3 DC Output
Table 7-2 lists the output p01,'1ter specifications.

Nominal Min.
Voltage Voltage

Ma.x. NOise
Greater Than

10 MHz (pef'

Min,

Max.

VoHage

Max.
Noise Less
Than 10
MHz (mVolts)

(I!rltageJ

Amps

+5.35

50.0

3.0

3.00

10.00 '

Max.

-------

+5.10

+4.85

+ 12,10

+1150

+12.70

70.0

2.0

050

4.00'

·12,C'!)

-11.40

·12,60

120.0

2.0

0,00

0,25

50.0

"'>Ii
,4 "'\,,

ClOO

0.20

-9 . (Xi

·8,55

-9A5

Maximum output power: 104 walts
the ... l:L 1 Vdc ill limited to 3.0
if the + 12.1 Vdc ls limited to 2.{)

1-2 VAXstation

Inaxlmum. the'S.l Vdc «HI 1\lpply up 1012.0 Amp~.

maXImum, the .... 5.1 Vd( can supply up to \30

and MicroVAX

Technical Manual

7.4 Battery for Time-of-Year Clock
Whe-n the system is powered off, the lime of
dock and its associated 50
ruekel cadmium
bytes of RAl\l storage art' powered by a
battery pack (part number 12·19245·00), which is rated to supply 3,6 V
has a capacity of 180 miHiampere hours.

7~5

Cooling

The airfJ",'.' intake passes through a grill in the front panel of the enclosure
whkh extends the fuH ,",'idth of the unit above the disk drive access
and the ac power switch. The airflmv exhaust passes through a grll! in the
rear enciosure panel (at the right side when viewed from the rear). There
are no air vents in the top or bott('ffi, or in either
panel of the enclo;;un~

Power Supply

7-3

Chapter 8

Drives
8.1 Introduction

)

This chapter provides an overview of the drives that are currently available
for use with the VAXstation 2000 and MicroVAX 2000 systems. Refer to
the technical description manual on each drive for a detailed description.
Table 8-1 lists the drives covered in this chapter and their technical
description manual order number.

Table 8-1: Drives
Drive

Manual Order Number

RX33 half-height diskette drive

EK-RX33T-TM

R032 half-height hard disk drive

EK-R032A-TO

R053 full-height hard disk drive

EK·R053A·TO

TK50 tape drive

EK-TZKSO-TM

8.2 RX33 Half-Height Diskette Drive

)

The RX33 is a 5.25 inch, double-sided, half· height diskette drive. It has
two operating speeds: for normal and for high-density diskettes (up to 96
tracks per inch). The RX33 provides full read/write compatibility with an
RX50 single-sided drive. Figure 8-1 shows the top and front view of the
RX33 diskette drive. This drive can only be installed in the system box.
Figure 8-2 shows the RX33 diskette.

Drives 8-1

Figure 8-1:

RX33 Diskette Drive

MfD1A
SLOT
i;"~1.

Ci':,j;J'·~~

1',f("lj'"J-':;-Ii-?

8-2

V;:..xslaHon 2000 and Micro\i';\X 2000 Technica! Manual

Figure 8-2: RX33 Diskette

,-I

LABEL
........... WRITE
~
PROTECT
NOTCH

~---

~INDE)(

)

HO"

~~
PROTECTIVE
JACKET

HEAD
APERTURE

-O-X-ID-E----~
COATED
MYLAR

Orives 8-3

8.2.1 RX33 Media
The RX33 uses 130 mm (5.25 inch) soft-sectored diskettes. These diskettes
can be single-sided or double-sided. They can also be high or normal density. The type of operating mode selected (high or normal) depends on the
diskette inserted in the drive.
Operating Mode

Diskette Required

Normal density

Single-sided, normal-density diskette (RXSO-type), 96 tracks
per inch

High Density

Double-sided, high-density diskette (RX33-type)

The two operating modes use different data transfer rates.
Operating Mode

Data Transfer Rate

Normal Density

250 kilobits per second

High Density

500 kilobits per second

8-4 VAXstation 2000 and MicroVAX 2000 Technical Manual

8.2.2 RX33 Jumper Configuration
The following jumpers must be installed for normal operation. Figure 8-3
shows the RX33 with the proper jumpers installed.
Jumpers provide the following functions.

Jumper

Description

DSO

SeIectsdriveO

HG and I

Allows the disk controller control the operating mode (normal
or high density)

Provides frame grounding

Diskette change mode

Bus Terminator

Must be installed for proper communication

8.2.3 Inserting/Removing a Diskette
The RX33 has a single diskette slot in its front panel. You can insert a
diskette as follows.
1. Make sure the diskette'S label is facing up and the write-protect
notch is on the left as shown in Figure 8-4.
2. Push the diskette into the slot, until the diskette snaps into position.
3. Lock the front panel lever by turning the lever 90 degrees to the left
(counterclockwise).

CAUTION: Do not force the lever. You can only turn the lever whel1 a
diskette is fully inserted in the drive.
To remove a diskette, simply turn the front panel lever 90 degrees to the
right (clockwise). The diskette springs out for easy removal.

CAUTION: Do not open tI,e lever if the LED indicator on the front paltel is OIl.
Hard write errors may result.

Drives 8-5

Figure 8-3;

AX33 Jumper Settings

,,«,:;t'l_J;;M
'<.<","",'I,!

8-6

VAXslaHon 2000 and MlcroV,lIX

Figure 8-4;

InserUng a Diskette

rHi,)AtlC!'Nl';:~l.}

rqc\'~'

vr: f~

PAh[{"

~>"~·N'-"'f;

elf;

irJ>A '~',:~.!I.:-;P

Drives

8~7

8.3 RD32 Half-Height Hard Disk Drive
The RD32 is a half-height hard disk drive. This drive contains 42 megabytes
of memory when formatted. It is usually installed in the system box along
with the RX33 floppy diskette drive but can also be installed in the hard disk
expansion box. Figure 8-5 shows the connectors on the back of the RD32
disk drive.
Figure 8-5:

RD32 Power and Data Connectors

J2-20 PIN
CONNECTOR

8-8 VAXstation 2000 and MicroVAX 2000 Technical Manual

•. 3.1 RD32 Jumper Configuration
There is only one configuration setting for the jumpers on the RD32 device
electronics board when it is used in the VAXstation 2000 or the MicroVAX
2000 systems. Also, the same jumper setting is used whether the drive is
installed in the system box or in the expansion box. Figure 8-6 shows the
location and configuration of the jumpers on the RD32 device electronics
board.

Figure 8-6: R032 Jumper Configuration

00®00~'@@
G)f:~~~
12 ~@
T
1

RADIAL

WRITE
FAULT

RECOVERY
MODE
J7-16 PIN CONNECTOR
(DRIVE CONFIGURATION}
SHOWN WITH DRIVE CONFIGURED AS 05-1

054

052

DS3

051

LIFE
TEST

SMA 041$ 85
MA'O'3~<e1

Drives 8-9

8.4 RD53 Full-Height Hard Disk Drive
The RD53 is a full,height thud dish drive. This drive n::mtains 71 megaby'tes
of memor" .,,'hen formatted. This drive can be installed .In the
box
or in the hard disk expansion box. Installing the RD53 in the
prevents the lostaHation any other drive within Ihe
b('x,
shows the connectors on the back of the RD53 disk
Figure 8-7:

8-10

R053 Power and Data Connectors

VAXstation 2000 and ~.111~roV,AX 2000

8.4.1 R053 Jumper Configuration
There is only on!:! configuration setting tor the jumpers on the RD53 deviu:
electronics board when jt is used in the VAXstation 2000 or the r. .1kroVf\X
2000 systems. A.\so, the same jumper setting IS used "·,,helher the drive is
installed In the system
or in the expansion box, Figure 8·8 shows the
location and configuration of the jumpers on the RD53 device
board

Figure 8-8: ROS3 Jumper Configuration

01,
I
III,

o I

Drives

8.. 11

8~5

TK50 Tape Drive

The TK50 tape drive is a mass. storage device, This drive (an only be in·
stalled in the tape expansion box, The
is not capable of suppett·
ing the TK50 drive within the system box. The drive lIses removable 945
megabyte tape cartridges to provide backup storage and softv..'are dIstribution for the VAXstation 2000ano the MicroVAX. :;WOO systems. The storage
rnedium is a tape cartridge containing a magnetic tape that is 0.5 inch wi.de
and 600 feet long. The tape
is about 4
4 inches squaH..'. and 1s
labeled CompacTape. Figure 8··9
a cutaway vie';\;' of the TK50
drive.
Figure 8-9:

8-12

Cutaway View of the TK50Tape Drive

VAXstation 2000 and

2000 Techmcai Manual

8.5.1 Using the TK50
The loadlUnload push button switch controls the TKSO tape drive. A green
indicator light shows activity in the drive and a red LED in the load/unload
switch shows the operating status of the drive. Figure 8-10 shows the front
of the TKSO. The rear panel has the logic and power connectors as shown
in Figure 8-11.

Figure 8-10: TK50 Front View

LOAD/UNLOAD SWITCH
8. REO LED

GREEN "ACTIVITY"
LEO

Orlves 8-13

Figure 8-11:

TK50 Rear View

Jl (26· PIN SIGNAL CONNECTOR)

8-14 VAXstation 2000 and MicroVAX 2000 Technical Manual

8.5.1.1 Leading/Unloading a Tape Cartridge
To load a tape, do the roHt:)'wing,
1.

Make sure the LoadiUnload s\,\'1tch i.s in the out position,

Power-up the tape expansion bo;x, The TK50 performs its POW('f-UP
self·lest (abGut five
\'\!hen no cartridge is in the driv!:" the
red light in the Load/Unload switch turns on during power-up . On
successful completion of the seif·test, the rt'd light turns off and the
green LED turns on, The drive is now ready to load.

Lift the handle,

Insert the cartridge aU the way into !he drive:. \'y'hen the cartridge is
most of the way in., the red light turns on and the green LED turns
off.

Lower the handle, The red light turns off and the greer, LED turns
on.

Press th!£; Load/Unload switch to the ill position. The red light turns
on and the gre(;:n LED turns ofr

The tape is now being loaded to the beginning of tape. \Vhen th€
tape is successfully loaded, the green LED turns arc The green LED
blinks when the drive is seeking the correct position of the tape and
also \'\then the drive is reading or "\Nriting

To unload a tape, do the following.

Press the Load/Unload Slvitch.

\\>'hen the tape is completely rewound and unhladed, the red light
turns off and the green LED turns on Bol.h of these indicators blink
as the tape re,vinds,

3. List the hand!!;:,
4..

Remove the cartridge.
NOTE:

the
power

remol'£' Ii

expu1!5ioll box.

removed

from the dnvc
VOl< carmof

the drive,

removr the

Drives

once

8-1 S

8.5.2 Write Protecting a TK50 Tape Cartridge
Slide the Write Protect switch to the left to write protect the tape as shown
in Figure 8-12. Slide the Write Protect switch to the right to disable write

protect as shown in Figure 8-13.
Figure 8-12:

Write Protecting a Tape Cartridge

•
Figure 8-13:

DisabUng Write Protect on a Tape Cartridge

•
$HA·0311 ....

8-16

VAXstation 2000 and MicroVAX 2000 Technical Manual

Chapter 9

DEC423 Converter (MicroVAX 2000)
9.1 Introduction
The DEC423 converter changes the three Rs232 ports on the video and
printer connectors to three DEC423 modified modular jacks (MMJ). DEC423
is a superset of Rs423. This communication strategy is supported through
the DECconnect terminal interconnect system (OTIS) which permits easy
installation of terminals and printers using the MMJ connectors and cabling
similar to that used for teJephone installation. Terminals that currently use
the Rs232 protocol ,which do not have MMJ connectors are connected to
DTIs using active converters (H3105) or passive adapters (H8571-A, 25-pin,
and H8571-B, 9-pin). The DEC423 converter assembly measures 3 x 3.3 x
1.23 inches. It mounts directly to the video and printer connectors on the
back of the system box and provides the following features.
•

Conversion from D-sub connectors and Rs232, to DEC423 and
MMJs for three of the serial lines on the back of the system box.

•

Electrostatic discharge (ESD) and Electrical overstress (BOS)
protection.

•

FCC Part 15 qualification for use with unshielded DTIS cable.

•

Power is received from the system box.

•

Modem control is not supported.

9.2 Physical Description
This section describes the physical characteristics of the DEC423 converter.

9.2.1 Converter Enclosure
The converter enclosure consists of a two-piece plastic housing with a PC
card inside. Two D-sub connectors, three MMJ connectors, and all the
circuitry are contained on this board. The design of the plastic housing is
such that the interior can be metalized for shielding in special applications
if necessary, with positive connection to the PC card ground plane. The
size of the enclosure measures 3 x 3.3 x 1.23 inches.
DEC423 Converter (MicroVAX 2000)

9-1

9.2.2 Mounting
The converter is secured directly over the RS232 O-sub connectors on the
back of the system box. The O-sub connectors are keyed and are different
sizes, so it is impossible for the converter to be attached wrong. Unshielded
OTIS MMJ cables (up to 3) are then plugged into the converter for attachment to user terminals and equipment.

9.2.3 Circuit Board
One nonstandard four-layer circuit board is used, measuring 3.1 inches x 2.8
inches. Figure 9-1 shows the layout of the OEC423 converter circuit board.
Figure 9-1: DEC423 Converter Circuit Board

00
MA·0944·87

9-2 VAXstation 2000 and MlcroVAX 2000 Technical Manual

9.2.4 Input/Output Connector Pinout
TIle il'tput to the convert!;'r from the systern modult~ is through two
connectors, Connector )5 (the 15-pin I)-sub) accepts two of the three sNu,l
lines and three po",;!?r supply voltages from the system module. Ccmnector J4 (the 9-pin I)-suh) accepts one serial line from the.
moduI.E~.
Table 9-1 and Table 9-2 list J4 and JS pinouts

and j3> at the output of the
There are three MMI connectors
converter r labeled 1 through 3. from
to
The pin
on each J\.fMJ connector are Identical and TabJe
Ii&ts the
The difference is that Jl is for the
terrninal
auxiliary) terminal, and l3 is for the printer, Hovvever,
terminal instead of a printer.

NOTE: TIli! VAXsfafwH
the RS232 rorts, TIle lIletalizea

not separate the sig/tal rmd

i111d ail applicable Sroulld pillS OTt both D·

sub cormedelrs are tied to tlle smile po ill I, The COl1iJerter
2000 ground Jor all
retumed to the chassis

use the \/AXstafiott

Sig/wi return currents and
(unellt.$ flit:
the D-sub shells alld defined gr0uI1d signal

Table 9-1: Connector J4 O-Sub Pinouts
Pin

Signal

Ground

Signal

No connection

$Y5 PTR XDAT

...
I

Grotmd

SYS PTi'i; RDAT

No connection

No C(}rtnection

NQ connection

Ncr ('onnectkHl

Converter (MicroVAX 2000)

9-3

Table 9-2: Connect.or J5 O~subPlnouts
Pin

SIgnal

Signai

No connection

No ronnection

."t.

No connf'(:tion

No (mnection

':l

No connection

+S Vdc

-12 Vdc

SY$ AUX RDAT

SYSAUX XDAT

Ground

SYS KBD. RDAT

Gmund

'1--1:i

SYS KBD X[l!H

+12 Vde

L-

Table 9-3: MMJ Connector Pinouts for J1! J2, andJ3
Pin

Signal

• Recehe d.ata

+.5 Vde
.... Transmit data

+ Receive data

• Transmit data

Buffered

....-.-~-~-.--~.

9.2.5 Power Dissipation and Cooling
The total
mum . 1

dissipation of Ihe converter
watts typical. 1",1ost of the

is 2.23 \va.Hs m<lxi·
occurs within the three

9636 driver chips. Only one half of
chip is connected to the
outside cables so as to spread the gn:atest po\ver dissipalkm across ali the
chips. There are no louvers on the
housing. so !.he
is one of thermal conduction from
chips to the multilayer PC
the surrounding plastic, i\'here the
act as convection heat
local ambient lernpexature.

9,2,6 Power Supply
All the po'\\'er used
the converter is
tors by the system module. The current

the D·~ub (0111'\('('
for each
are listed

700 milliamp maximum
854 miHi'1mp" ma.>;irmlm
+:; Vdc 677 mHiiamp ma:dmurn

9-4

VAXl:naiion 2000 and f'/HcroVAX 2000 Technical Manual

9.3 Circuit Descriptions
The system module does not contain the protection circuitry or the proper
layout to conform to the requirements of DEC SID 52·4, even though they
use DEC423 compatible drivers and receivers. Each of the three serialUnes
that come from the system module are first converted into TIL, and then are
converted to DEC 423. These drivers/receivers reside as dose as possible
to the D·sub connectors. The remainder of the physical space between the
drivers/receivers and the output MMJ connectors contains the protection
circuits, line terminators, and failsafe components.
All three serial lines in the DEC423 converter are identical. The only difference is their connector pinouts. Figure 9-2 shows the serial line from the
printer port, line 3.
Figure 9-2:

DEC423 Converter Block Diagram for Line 3

-12V

EJ~
J4

DRIVER

DEC423 Converter (MlcroVAX 2000)

9-5

9.3.1 Slew Rate
The DEC423 output driver circuits must interface with RS232 circuits through
passive adapters. Such compatibility requires a slew rate resistor of 27K
ohms for a risetime of 1.8 to 2.7 microseconds per DEC STD 52-4.

9.3.2 Fallsafing
Per DEC SID 52-4, the 9639 receiver must be failsafed. That is, the input
of the receivers must default to a predictable condition if they are disconnected from the terminal. Also, the input impedance of the 9639 receiver
is not well-matched to RS232 and V.28 specifications. To meet these requirements, a 10K ohm resistor is connected from the positive side of the
receiver to ground, and a 24K ohm resistor is connected between the negative side of the receiver and -12 V, as mandated by DEC STD 52-4. This
will force the output of the receiver to the MARK condition if the cable is
disconnected or if the terminal is powered off, keeping the system UART's
inactive.

9.3.3 Pins 1 and 6 on the MMJ Connectors
Pins 1 and 6 of the MMJ connectors are unused within the converter. These
lines are normally reserved for flow control signals in printers. When unused, DEC SID 52-4 requires that pin 1 be terminated with a 150 ohm resistor to + 5 V. This line must also be protected from transients. Pin 6 must be
terminated by a 3K ohm resistor to ground. Because of the larger impedance
and the connection to ground, a transient supressor is not needed on line

9.3.4 ESD/EOS Protection
All lines intended for external connection are protected with transient suppressors where necessary. All receiver lines are protected by an integrated
package containing eight devices with a fusible link at a nominal voltage of
35 V. All driver lines are protected by discrete devices at a nominal voltage
of 7 volts. Each of these parts are detailed in DEC STD 52-4. The converter
passes all the tests required by DEC SID 52-4.

9-6

VAXstation 2000 and MicroVAX 2000 Technical Manual

9.3.5 Chokes
Ea.ch of the active lines connected directly to a driver or receiver must. have
mkroHemy
transient protection The protection device is assisted
a
choke on each of these lines for tv\'O reasons.
L

The choke slows the leading edge of EOS or EST). 'n,is
terti on de\!1CeS time to tum on and nnnpensate for the
inductance of the protection device.

In those leads using discrete protec:tion devices, the chnke lirnits the
curren! through the cable during a sustained high.current short
acting
as a fuse. The fusing action of the choke is not needed on.lilH"5 protected
by the integrated protection
This chip has its own built-in fUSE'.

Ihe pw'
and etch

9.3.6 EMI/RFI Isolation and Susceptibility
The system box is not designed to operate ,,"Hh unshleJded external data
cables The converter ensures that the MicroVAX 2000
connects t.o
the DTIS with FCC compliance using unshielded cables.

9.4 Loopback Connector H3103 (12 ..25083 ..01)
The loopback connector is a molded MMJ with the transmit and receive
lines cross connected as shown below, These Hnes permit the looping of
signals back to the system modUle to verify serial line operation .
Transmit data + {pin 2 - - .. >pin 5IReceive data +
Transmit data -!pin 3 --.- >pin 4!Receive data -

Converter (rvlicroVAX

9-7

Chapter 10

Expansion Peripherals
10.1 Introduction

)

This chapter describes the three expansion peripherals available with the
VAXstation 2000 and MicroVAX 20nO systems. These are the hard disk
expansion box, tape drive expansion box, and the expansion adapter. The
hard disk expansion box is a mass storage device, the tape drive expansion
box is removable tape cartridge mass storage device, and the expansion
adapter interfaces both of the expansion boxes onto the system box.

10.1.1 Hard Disk Expansion Box
The hard disk expansion box contains a hard disk (Chapter 8), a power supply (Chapter 7), a resistor load module (Chapter 6), and the chassis. Since
the drive, power supply, and the resistor load module are explained in other
chapters, this section discusses the connector pinouts of the interface cable
within the expansion box. Connector J1 is the 50-position D·sub connector which connects to the hard disk expansion box cable (BCl7Y) from the
system box. Connector J2 is the 34-posltion edge-card connector which con·
nects to the rear of the disk drive. Connector J3 is the 20-position edge-card
connector which connects to the rear of the disk drive. Table 10-1 lists the
internal drive cable signals pinout.

Expansion Peripherals 10... 1

Table 10-1 : Hard Olsk
}1

Signal

Direction

18
19

Cround

SOl( Internal

Signa!

Ground

Pinout
"",.--...-~~

'")

Cround

Drive select 4

""
3

-Read dati!

Ground

'"' Read data

Ddve select 3

Gro\md

Ground

',.t;:>

Ground

23
24
25

No connection

-Write data

Ground

+ V'/ritc data

No connectJim

Ground

2-5

Ground

<-'

Ground

~''i

Step

Ground

23
22

Ground

Ready

Grml.nd

Ground

Reserved

''''I
J.

Ground

26
..,,.,

index

14
15

21
20
19

Ground

Head se.lect '1

.17

Ground

No connection

36
37

Ground

Head select 0

Drive select

1,",.,

Ground

Write fault

Gn.,1und

Track 0

Ground

·8

Seek

10-2

VAXstation 2000 and MlcroV,A,X 2000 Technical Manuel.l

Table 10-1 (Cont.): Hard Disk Expansion Box Internal Cable
Pinout

Signal

44
45

Ground

WrHe gElt~·

Ground

Head select ::

4ff

Ground

50
-,..,,-,....

S!gnal

Nc. connection

-~--

10,1.2 Tape Drive Expansion Box
The tape drive expansion box contains a TK50 tape drIve (See Chapter 8)
a TZK50 SCSI controUer board (Reter to the TZMOlSCSI Controller TeciHl!C(t{
Mamml order l'tumber EK·TZK50-n,1). a pmver supply (See Chapter 7), a
resistor load module (See Chapter 6), and the chassis. Since the tape drive,
power supply, and the resistor load module are explained in other chapters
and the 12K50 controUer is explained in the above referenced document
this section discusses the connector pinout of the interface cabJe between
the: 1ZK50 controller board and the external connector. Table 10-2 lists Hu,:
pinout Signals for t~. . e internal tape drive, ConnE:'ct~r 11 is the 50.i'0sjti~)~)
IEEE connector l'vhlCh connects to the fape expanSiOn box cable tBC19.i!
from the system box. Connector .12 is the 50-position ed -plug connector
whlch connects to the SCSi port on the TZKSO contI'
r board. Ther.;:
is another connector on this cab~e (J3) and it has a one-to-<)ne pinout ,~ti!h
the J1 connector. Connector is used for daisy cnainiIl&, expansion boxes.
Although the VMS and
operating system. softv,'tlre do not suppi.'rt
mere than one tape expansicm
future operating systems that do
multiple tape expansion boxes will use the 13 connector for daisy

Expansion Per!pherals

10~3

Iable_ ,O-::~ Tape Ori~~ E~~ansior:_~~,~...lrltern_~~~~_~Ie.Pino~!
J1

Signal

Sig.nai

Ground

Te.rminationpower

Data bus 0

Ground

No connection

Data bus 1

Ground

No connection

Data bus 2

Ground

Attention

Ground

No connection

Ground

4
6

7
I.>

Data bus3

Ground

33
34

Data bus 4

Ground

Data btlS 5

Ground

Acknowled,ge

Dala bus 6

Grc'und

Ground

Reset

Data bus 7

Ground

34,

18
19

Data bus

Ground

43
44

Sel,ect

No connection

Cround

4,)

Ground

43
23

.j::;

Command'Data

Ground

No connection

10-4

Ground

Busy

No connection

VAXstatlon 2000 and MlcroVAX 2000

Grt'und

10.1.3 Expansion Adapter
The expansion adapter attaches to the bottom of the system box and is
basically a cable interface device. It has three ports for external devices. Port
A is for the tape drive expansion box, port B is for the hard disk expansion
box, and port C is for the serial line unit options on the MicroVAX 2000
system. Port C is reserved for future options on the VAXstation 2000 system.

10.1.3.1 The Tape Port (Port A)
Table lO-3lists the internal cables Si~nal pinout on port A which interfaces
the tape drive expansion box to the 5 80 tape controller chip. Connector J1
is the 50-position IEEE connector which is port A on the expansion adapter.
Connector }2 is the 50Xosition berg connector which connects to the tape
port on the system mo ule.
Table 10-3: Tape Port Internal Cable Pinout (Port A)

)

Signal

Ground

No connection

DBUSO

Ground

DBUS1

Ground

6
7

DBUS2

Ground

SCATN

DBUS3

Ground

9
10

Ground

DBUS4

34
35

Ground

SCBSY

DBUS5

36
37

Ground

SCACK

DBUS6

Ground

SCRST

DBUS7

Ground

SCMSG

Expansion Peripherals 10-5

Table 10-3 (Cont.): Tape Port Internal Cable Pinout (Port A)

Signal

18
19

DBUSP

10
35

Ground

Signal

Ground

47
23

seSEl
Ground

seelD
Ground

SCREQ
sello

Ground
Ground

Ground

43
44
45
46
47

Ground

12
37

Ground
No connection

24
49
25

20
21

Ground

10.1.3.2 The Disk Port (Port B)

The disk port (port B) on the expansion adapter has a disk interface module
attached to it. This module converts two berg-style connectors from the
system module that have the disk data bus on them into a single 50-position
D-sub connector for connection to the hard disk expansion box. The hard
disk expansion box is connected to port B via the disk expansion box cable
(BCI7Y). Table 10-4 lists the disk interface module pinout that interfaces
the hard disk expansion box to the 9224 disk controller chip through port B
of the expansion adapter. Connector Jl is the 26-position connector which
contains the disk control signals from the system module. Connector J2 is
the 20-position connector which contains the read and write data from the
system module. Connector J3 is the 50-position D-sub connector which is
port B on the expansion adapter.

10-6 VAXstatlon 2000 and MlcroVAX 2000 Technical Manual

Table 10-4: Disk Interface Module Pinout (Port B)

Signal

Signal.

Head select 3

Drive select acknowledge

Head select 2

Ground

Reserved

Write gate

Seek complete

Ground

)

Ground
Ground
21

Spare

Track 0

No connection

Write fault

No connection

Ground

No connection

Head select 0

No connection

Head select 1

Ground

Index

+ Write data

Ready

-Write data

Ground

Ground
Ground

15
16

Step

Drive select 4

+Read data

Ground

-Read data

Drive select 3

Ground

No connection

18
19

20
21

Direction

No connection

25
26

No connection
No connection

NOTE: All pins not listed for /3 are connected to ground with tlte exceptioll of pitts
9, 41, and 45, which have no connection.

Expansion Peripherals 10-7

Appendix A

Timing Diagrams
This appendix contains sample timing diagrams.
Figure A-1:

DAL Bus Address Control

DAL BUS ADDRESS CONTROL 'TIMING

CPU STATE

ClKD

DAL

----ff///

~
DAl LATCH
ENABLE

_ _ _ _ _..../

LATCHED

NEW ADDRESS

~"'''~____

/
TRANSPARENT ",,"~...._ _ __

LATCHED

LOAL

)

Timing Diagrams

A-1

Figure A-2:

Program RAM Read

'THE

A-2

VAXstalion 2000 and Micro'v'AX 2000 Technica! Mamlal

Figure A-3: Program RAM Write

-_0 --

.....

~12
/

.....

--i no
.....

-1"
~n'
/

1lUC'fU) e. lOG 0

fot-1IIIII1t !lATA v@ AT n-» HI ,
ln~

(

)

Timing Diagrams A-3

...
I

Figure A-4:

110 Single Cycle Read

I/O SlNGl£ CYCU: READ TIllING

0;:,

I\)

o
o
o

AS
o.t[lIAOO

S»

;:,
0.

s:::

CASE'"

IY///

==:x

IOAl\7,09

________r-"

~-~~'---

CASJ, 0

/
SELECTED BY ""'J,O. TRUE fROII CASEN L-> H TO DS L-> H

o
o
o

--------------------,~

-t

----------------------------~/

(1)

:::J'

ROY

I\)

;:,

o·

s:::
S»

~~-----

,~---~

~~-----------------------------------

HIGH rROOI ASI TO CLKO roo O_C FIRST co HIGH TIllE.
~

ROY SAllru:

SUP

DALOIR'

;:,

(SET BY DBE)

I»

DALOIS

-../

~~_ _ _ _ _ _ _ _ _ __

CONl1NIJ{

r--~

5(T FROU ASI l->H TO DBE H->L AND FRO\< DBE L->H TO AS. H->L

HOlTS
CA. ca. ce. co ARE lH£ OUTPUTS OF .. FOUR-BiT BINARY
COUNlTR WHICH Q[TEIbiINES THE TlIIINC NEEDED TO STRETCH lH£ BUS
CYCU: BY EITHER OIIE OR TWO "'CROCYCLES.
.....-W1.....7

~'{.'

,,"'

"",!!i,!;(

1:.'

~_: ~

(..,'(

Timing

A-5

Figure A-6:

Video RAM Read

'llDEO RAM REAO lIMING

-UJ

I»

o::::J

~
o
o

...s

\/RAS

--~

IIEIoIAOO

I»
::::J
0.

CASE"

:s::
o·
....

C"SlNT

C"SI:0

I\)

I\. OUll'UT

:T
::::J

o·
!:!!.
:s::
I»

:X~-CAS-HiCH·

WORD IiEiAAOOo.:.:i--- . --x::-----c~'M:iRoliOOiiOO_o

X~~,,~~'\

------------~

,~----

----------------------/
"'

F(IlMJ:2)

,,~-------------------

/--

real/I: 0)

SAlIE HIGH WORD

ILlOAO

o
o
o
o

RAS

/Zl7.77
/

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'~-~ -> BDAlJI:ll1

r-~-~--~

.~"-

_ _ _ _ _ __

------"--

'--

::::J

!:!!.

ROY

ROY 5AMPI.£
O"UlIR
VAlDIS

_________.-J/

SUP

HIGH mOIl ASI TO CU<O FruO..,..C "FIST CA HIGH TIllE.
r-~~~~,,'__

"
-------'~
HIGH mOIl "51 L-> H TO DBf H-> L ANO mOIl DBE l

____________
/

-> H TOASI H-> l
NA-XI)7'

------------------~-""--~"-"-

Figure A-7:

Video RAM Write

\110£0 RAIl WRllt: 1MNG

AS
\/liAS

CAstN

CASINT

CAS1:D

IU.OAO
It OUTPUT

ell

-t

CI
III

ROY

Ii'

....
3

(J)

)10
I

...,

110'1' SAMPt.£
DAtDIS

IW//ff
/

RAS

DT/CE
IlDlAOO

CAS LOW WORO liIEM_O

------------~/
______________________-J/

fl8Wl:O)

r---~-~-~

BOAL31:111 -:>I\.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _/

------------~~
----------------~/

---------------------------/

X"'_____

CAS HIGH WORO liIEMAOOO-l

,~----________________
__
F(8IoI3:2)

it -> BOi\lI5:OD -~----~---------- - - , , - -

~
/

~~----,~----

,-----

-----------------------------------------~
_______rnlrolE.
~

____________________

-------------/

HIGH FROIoI ""51 TO C1.J(O FOllOWNC FIRST C8 HIGH
~~

_____________________

.--~"---

......

,."....,

i
~

!
I

I
!

;:::

';
c(
,)
;!

I)
I

)

"a:

t':I
ID

;:;;-;

go
I

'¢

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:;
<l)

i.:C

A-a

~
~

l!
.";,

j,"t,

.~
P

,~,

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:c:;

i
!
if

)

cif,

J '\

~
~

~, ('

g )
~~ ,,( ,
~\

I
~

:;
'i

VAXslation2000 and

"l! ~
~

, " "
~<0

't,";-:i'
;;

.
~

1:'1

Manual

~
~

I !

1
I

)

(

r·'

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I

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1
!I

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~

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i
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~

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i
i

T
IIl

(It

,90

CI>

u>-

(.)

::l
D.

(.)

0.,..
I

ca:
!::s

u::

A-10

r;~

VAXstatlon 2000 and MlcroVAX 2000 Technical Manual

I
i

I
0

I
I
.!
Co)

. I

>0(J

-"•

•-;..
c
•
a:

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......

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c
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elg

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Ul
0

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i

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-if

II!
I ~
1'h1

I
i

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III
n

Timing Diagrams A-11

I
I

"
I!

CI)

i
I

c:>

>()

-.,

CI)

'C
Co

""CI)

'0
CI)
a:

{/)

"":"

()

.,..
,..
I

<C
CI)

""::J
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u.

CI)

I
I

I!J

I
i
i

i
i

a lei 'ii I , ! ~I~
~

A-12 VAXstation 2000 and MicroVAX 2000 Technical Manual

)

I
I

u>-

.
I
I

()

'8.
CD

:;)
"-

CD
CIS

'0
CD

a::
==
:c

(/)

":>

-.
..

()

)

,..
,..
I
cc

e
:::J

'eII"
!

I
I

i
i

Ie! Iii I i ! fig
;

Timing Diagrams A-13

•

"
~

;
Ig

(.)

::;)

...0

(I)

Q
0

a:
::

t:!

:c
(I)

0
0
'C

;;

- ,i

"':'

-........
0

-:
~

(.)

I
<[

...::s
0

1:1

ii:

i
i

i
ifi

Ie! i i I i ! ! IE
11

A-14 VAXstatlon 2000 and MicroVAX 2000 Technical Manual

Figure A-12:

Start of Display/Region Line

5TART or OISPlA Y REGION NNE
LOAD
OCU<

L -->Ii
SHIFT REG

tttttttttttttttttttttttttttt
l

ACllON

\IIOENA
SElY
SELX

_______r----·.-----

'\.

,
,

-----------~/

SRAMO

MUX.

-I

NIB900

Nl9810

lOEN~

iii·

...

' _--

NIBB20

NIBBJO

......

/
X

NI8801

NI8811

NI8821

ClK

:i"

'\..

SRAIoIl

OUTPUT

'
81TO

BITt

81T2

......_ _

II)

3en

WHERE:

NI88XY REfERS TO ruE Yrn... BITS fROM VRAM X.

....<II
I

SHIn REGISTER ACTION l - PARAlLEl LOAD.
S - SHin DATA RIGHT.

....-XOT1II-II7

»I

....

Figure A-13:

End of Display/Region line

~
ii

c)"
:J
N

o
o
o

JI,I

:J
0.

END Of DISPLAY REGiON/UNE

LOAD

l --:>ti

SHIFT REG

-I

(l)

'-./

SlSS

SLSS

SSSSSSSSSSSSSSS

ACl1CH

say
SEtX

~~-------------------------------,~----------------------------

SRANO

o
o
o

'-./

tttttttttttttttttttttttttt

DClI<

~~"------

VlDDlA

SRAN1

UUX.
OUTPUT

NIBB16J

NIBB26J

NIBBJ63

/
NIBBOO

(NEXT UHE)

::T
:J

0'
~

ClK

JI,I

LOEN

SR
OUT

WHERE

:::x

/
B1T(l-4)

BIT(L-J)

BIT(L-2)

BITCH)

B1T(l)

'\.

BIT(l) IS THE LAST PIXEL ON THE UNE.
NI8B163 IS THE lAST 4 BITS Of A LINE FROM VRAIA "
NI88263 IS THE LAST .. BITS Of A LINE FROM VRAIA ,2
NIBB36J IS THE LAST 4 BITS Of A LINE FROM VRAIA ,3

MA-lIO' ' ' '.'

Figure A-14: Tape (SCSI) Port Data Transfer Operation (From Port)
SCSI PORT DATA TRMlSFER OPERAliON - !'ROM PORT
ClKO

SCSlOtR
SCSIORQ

7//Wg-----------------,,_ _ _ _ _ _ _ __
,..
n
.-1

SCStOAC1<
SCSIRO
WR9224

059224

'\..

"
"

I.
DATA f'ROM

SCSICC

.-1

------(----------------)>-------I"

-f

SCStEOP.

r---------

I---T4---1

oA)"
(Q

• ONlY ASSERTED IF SCSI BYTE COUNT REGISTER BECOMES OOOOH AS A RESUlT
Of' THIS SCSIORQ.

3(/)

PARAMETER lAIN. MAX NOTES

11 - 130 PARAMETER Of' SCSI CONTROLLER CHIP

l>
I

.....

"""

n - 135 PARAMETER Of' SCSI CONTROLlER CHIP
T4

BYTE COUNT REGISTER RIPPLE CARRY liME

"A-XC"3-.,

lo..

o
C.
o

I-

II
! I
I,,,, )
i
T
I
I

...

(;I

!t !
!

0..

I
I

A-18

VA.Xstation 2000

Techrtlca! f\1anua!

Appendix B

Physical Address Maps
B.l System Module Addresses
11'te addresses used by hardware on the KA410 system module and the
MS400 RAM memory option module are listed in Table B-I.

)

Table B-1: System Module Address Locations
Address Range

Symbolic Name

Description

OOOO.()()()()"OOIF. FFFF

System module RAM

0020.0000·00FF.FFFF

Memory option module RAM

2002.0000

CFGTST

Configuration & test register
(rIo)

2002.0000

10RESET

2004.0000-2007.FFFF
2004.0004

110 reset register (w/o)
System module ROM (up to
256 kilobytes)

SYS.TYPE

2004.0020·2004.003F

System 10 extension register
Interrupt vector numbers

2008.0000
2008.0004

HLTCOO

Halt code register

MSER

Memory system error register

2008.0008

MEAR

Memory error address register

2008.OOOC

INT MSK

Interrupt mask register

2008.0000

VOCORG

Monochrome display origin

2OO8.oooE

VDCSEL

Video interrupt select

2008.oooF

INT.REQ
INT CLR

Interrupt request register (rio)

2008.oooF

Interrupt request clear (w/o)

Physical Address Maps B-1

Table B-1 (Cont.): System Module Address Locations
Address Range

Symbolic Name

2009 .()(J()()..2009 .OO7F

Description

Network address ROM

200A.OOOO-200A.OOOF

SER xxx

Serial line controller

200B.OOOO-200B.OOFF

WATxxx

Time-of-year clock and NV RAt....

200c.0000-200C.0007

DKC.xxx

Disk controller ports

200C.OO80-200C.OO9F

Tape (SCSI) controller chip

200C.OOAO

SCS.xxx
SCD ADR

200c.OOCO

SCDCNT

Tape (SCSI) DMA byte count
register

200C.OOC4

SCD DIR

Tape (SCSI) DMA transfer direction

200D.OOOO-200D.3FFF

Tape (SCSI) DMA address reg·
ister

Disk data buffer RAM

200F .0000-200F.000F

CUR xxx

3OOO.0000-3001.FFFF

Monochrome video RAM

Monochrome video cursor chip

B.2 Option Module Address Ranges
The following address ranges are defined for use by option modules connected to the network option and video option connectors. For some of
these ranges hardware on the system module generates a selection signal,
whose name is listed. If no signal name is listed, the option module must
decode the address range from the data/address bus. Table B-2 lists the
nominal ranges. Subsequent tables show the actual ranges used by each
option type.

B-2

VAXstatlon 2000 and MlcroVAX 2000 Technical Manual

Table B-2: Option Module Address Ranges
Address Range

Description

200E.~200E.FFFF

Network option, signal NIENA

2200.~23FF.FFFF

Future option CSRs

240().~25FF.FFFF

Future option CSRs

2010.~2013.FFFF

Network option ROM, signal NIROMCS

2014.~2017.FFFF

Video option ROM, signal OPTROMENA

2018.~201B.FFFF

Additional option 1 ROM

201C.~201F.FFFF

Additional option 2 ROM

38OO.0000·3BFF.FFFF

Video option (32.bit path), signal OPTVlDENA

3COO.OOOO-3COO.FFFF

Video option (16-bit path), signal OPTVlDENA

B.2.1 Ethernet Network Option Addresses
Table B-3 shows the addresses used by the DESVA Ethernet network option
that is described in chapter 5.

Table B-3: Ethernet Network Option Module Addresses
Address Range

Description

200E.OOOO-200E.OOO7

LANCE chip registers

2010.~2011.FFFF

Firmware ROM (one 32 J<byte chip)

Physical Address Maps 8-3

8.2.2 Graphics (Cofor) Video Option Addresses
B-4 shows the

used

option.
Modut~ Addresses

Table 8-4:
Address Range

Description

2014'c)O()()·2015.FFFF

Firmware ROM (one 32

3CQG,OOllO·3CDIHlO'lF

,t...DDER chip

3COO,0200·3COO.01FF

FIFO compression chip

3COO,0300·3COO.,O}IF

Video DAC

3C()(l,04()(j·.),:::Oi',041F

Cursor

3COO, 050iJ-3COO. 0501

Video readback

3COO.8000·3COO. FFFF

RJ\.h·1

B.2.3 Eight~port Asynchronous Serial Une Addresses
Table E·-S
\\'hkh is

the address!:.!'> by the 8-port
in the graphics
port

serial line option

Address Range

2014,OOW-2015.FFFF

Firmware ROM lone 32
(~,on~ro~ .and status

8-4

VAXstation 2000 a.nd MicroVA-X 2000 Technical Manua!

Index
A
Address Strobe Delay Une, 3-232

B
Battery Backup, 3-73
Battery for Time Of Year Oock, 7-3

c
Central Processor Overview, 2-1
Coaxial Transceiver Interface, 3-227
Configuration and Test Register,
3-230
Configuration Jumpers
MS400 Memory Module, 4-7
Connector Pinout
DEC423 Converter, 9-3
Connector Pinouts
MMJ Connectors on DEC423
Converter, 9-6
MS400 Memory Module, 4-4
Port A on Expansion Adapter,
10-5
Port B on Expansion Adapter,
10-6
System Module, 3-233
CPU/FPU 40MHz Oock, 3-29
CPU Bus Cycle Description, 3-11
CPU DMA Cycle, 3-13
CPU External Processor Read Cycle,
3-12
CPU External Processor Response
Cycle, 3-13
CPU External Processor Write Cycle,
3-13
CPU General Registers, 3-14
ICCS, 3-17

CPU General Registers (cont'd.)
IPR, 3-14
PSL,3-14
SAVISP, 3-17
SAVPC,3-17
SAVPSL, 3-17
SID, 3-17
CPU Idle Cycle, 3-11
CPU Interrupt Acknowledge Cycle,
3-12
CPU Read Cycle, 3-11
CPU Write Cycle, 3-12
Cursor Command Registers, 3-119
Cursor Control Registers, 3-117
Cursor Coordinate Offsets, 3-116
Cursor Generation, 3-117

D
DC333 CPU Chip Specifics, 3-4
DC337 FPU Chip Specifics, 3-25
DC503 Cursor Sprite Chip, 2-10,
3-113
Blanking the Display, 3-123
Controlling Cursor Plane Outputs,
3-123
Cursor Command Registers,
3-119
Cursor Control Registers, 3-117
Cursor Coordinate Offsets, 3-116
Cursor Generation, 3-117
Cursor Region Detector, 3-122
Displaying a Crosshair Cursor,
3-122
Displaying a Sprite Cursor, 3-122
Loading Cursor Sprite Pattern,
3-121
Overview, 3-113

Index-1

DCS03 Cursor Sprite Chip (cont'd.)
Power-up Initialization, 3-124
Test, 3-123
DCS24 Standard Cell, 2-8, 3-74
Disk Control, 3-101
Input/Output Control, 3-95
Interrupt Controller, 3-105
Interval Timer Interrupt
Generation, 3-104
Memory Control, 3-84
Monochrome Video Display
Controller, 3-110
Parity Generation and Checking,
3-104
Power-up Initialization, 3-84
Tape Control, 3-103
Test Mode, 3-112
Video Control, 3-90
DEC423 Converter, 9-1
Chokes, 9-7
Orcuit Board, 9-2
Orcuit Description, 9-5
Converter Enclosure, 9-1
EMIIRFl Isolation and
Susceptiblilty, 9-7
ESD/EOS Protection, 9-6
Failsafing, 9-6
Input/Output Connector Pinout,
9-3
Loopback Connector, 9-7
MMJ Connector Pinout, 9-6
Mounting, 9-2
Physical Description, 9-1
Power DiSSipation and Cooling,
9-4
Power Supply, 9-4
Slew Rate, 9-6
Detail Description
Central Processor, 3-3
DCS03 Cursor Sprite Chip, 3-113
DC524 Standard Cell, 3-74
Serial tine Controller, 3-125
System Memory, 3-40
5380 Tape Controller, 3-198
ThinWire Ethernet Circuits, 3-224

Index-2

Detail Description (cont'd.)
Time-Of-Year Clock, 3-58
Diagnostic Terminal Connection,
3-131
9224 Disk Controller, 2-13
DMA Bus Access, 3-29
DMA Operation, 5-19
Drives, 8-1
RD32,8-8
RD53, 8-10
RX33 Diskette, 8-1
TKSO Tape Drive, 8-12
DZ Silo, 3-129

E
Expansion Adapter, 10-5
Port A, 10-5
Port B, 10-6
Expansion Peripherals, 10-1

F
FPU/CPU Communications Protocol,
3-28
FPU Bus Cycle Descriptions, 3-27
FPU External Processor Command
Write Cycle, 3-27
FPU External Processor Read Cycle,
3-28
FPU External Processor Response
Enable Cycle, 3-28
FPU External Processor Write Cycle,
3-28
Functional Overview
DCS03 Cursor Sprite Chip, 2-10
DC524 Standard Cell, 2-8
9224 Disk Controller, 2-13
Serial tine Controller, 2-10
System Memory, 2-5
5380 Tape Controller, 2-15
Thin Wire Ethernet Circuits, 2-17
Time-Of-Vear Clock, 2-7

HALT Code Register, 3-39,3-230
Hard Disk Expansion Box, 10-1

I
Input/Output Register, 3-232
Interrupts and Exceptions, 3-18
Device Interrupts, 3-19
Exceptions, 3-20
Interrupts, 3-18
Interval Timer Interrupts, 3-19
Machine Check Exceptions, 3-20
System Control Block, 3-22

N
Non-Volatile RAM, 3-67

LANCE Chip Description, 5-8
LANCE Chip Overview, 5-8
LANCE Operation, 5-42
LANCE Programming Notes, 5-47

M
Memory
Control, 3-84
Error Address Register, 3-46
Management, 3-30
Option Module RAM, 3-44
Option Module ROM, 3-54
Option Module ROM Set Format,
3-56

)

MicroVAX 2000 (cont'd.)
System Description, 1-3
System Jumper Configuration,
3-231
Video Console Terminal, 1-3
VS410 System Box, 1-3
MS400 Memory Module
Configuration Jumpers, 4-7
Control Signal Descriptions, 4-2
Memory Cycles, 4-3
Theory of Operation, 4-2

Parity Checking, 3-44
RAM,3-41
ROM,3-47
System, 2-5, 3-40
System Error Register, 3-44
System Module RAM, 3-41
System Module ROM, 3-47
System Type Register, 3-52
ThinWire Ethernet Address ROM,
3-53
Video RAM, 3-43
Virtual to Physical Address
Translation, 3-33
MicroVAX 2000
0001 Keyboard, 1-3

p
Physical Address Maps
Eight-port Asyncronous Serial
Line Addresses, B-4
Ethernet Option Addresses, B-3
Graphics Video Option Addresses,
B-4
Option Module Address Ranges,
B-2
System Module Addresses, B-1
Physical Characteristics, 1-4
BA40A Expansion Adapter, 1-7
BA40B Expansion Boxes, 1-6
DEC423 Converter, 1-6
Disk Interface Module, 1-7
I<A410 System Module, 1-5
MS400 Memory Module, 1-5
Network Interconnect Module,
1-5
Power Supply, 1-5
RD32 Disk Drive, 1-6
RD53 Disk Drive, 1-7
Resistor Load Module, 1-6
RX33 Diskette Drive, 1-6
System Box, 1-4
TKSO Tape Drive, 1-7
TZK50 Controller Board, 1-7
Power Requirements
DEC423 Converter, 9-4

Index-3

Power Requirements (cont'd.)
MS400 Memory Module, 4-7
System Module, 3-239
Thin Wire Ethernet Module, 5-49
Power Supply, 7-1
AC Input, 7-1
Battery for Time-Of-Year Cock,
7-3
Cooling, 7-3
DC Output, 7-2
Processor Restarts, 3-37
HALT, 3-39
HALT code register, 3-39
Power-On, 3-39

Serial line Controller, 2-10, 3-125
Diagnostic Terminal, 3-131
DZ Silo, 3-129
Interrupts, 3-132
line Identification, 3-129
Register Summary, 3-132
SIA Chip Description, 5-18
SIA Chip Overview, 5-15
System Jumper Configuration, 3-232
System Module Connector Pinouts,
3-233
System Registers
Miscellaneous, 3-229
System Type Register, 3-52

RD32
Jumper Configuration, 8-9
RD32 Half-Height Hard Disk Drive,
8-8
RD53
Jumper Configuration, 8-11
RD53 Full-Height hard Disk Drive,
8-10
Resistor Load Module, 6-1
ROM
Option Module, 3-54
Set Format, 3-56
System Module, 3-47
ThinWire Ethernet Address ROM,
3-53
ThinWire Ethernet Module ROM,
5-20
RX33
Inserting/Removing Diskette, 8-5
Jumper Configuration, 8-5
Media, 8-4
RX33 Half-Height Diskette Drive,
8-1

5380 Tape Controller, 2-15,3-198
Controller Chip Registers, 3-206
Controller Interrupts, 3-219
DMA Register Operation, 3-217
Overview, 3-200
Programming Notes, 3-223
Reset Conditions, 3-223
SCSI Device 10 Values, 3-224
SCSI Overview, 3-204
Tape Drive Expansion Box, 10-3
ThinWire Ethernet Circuits, 2-17,
3-224
Coaxial Transceiver Interface,
3-227
Transmitter, 3-228
Thin Wire Ethernet Module
Block Diagram, 5-1
Buffer Management, 5-37
Control and Status Register 0,
5-23
Control and Status Register I,
5-27
Control and Status Register 2,
5-28
Control and Status Register 3,
5-28
DMA Operation, 5-19
Ethernet Implementation, 5-7

s
SCSI Device lD Values, 3-224
SCSI Overview, 3-204
SCSI Tape Bus Reset, 3-222

Index-4

ThJnWire Ethernet Module (cont'd.)
Firmware ROM, 5-20
Initialization Block, 5-30
Interrupts, 5-29
LANCE Chip Description, 5-8
LANCE Chip Overview, 5-8
LANCE Chip Receive Mode, 5-9
LANCE Chip Transmit Mode, 5-9
LANCE Operation, 5-42
LANCE Programming Notes, 5-47
Multicast Address Filter Mask,

5-34
Network Addresses, 5-7
Network Physical Address, 5-33
Packet Format, 5-7
Program Control of LANCE Chip,
5-21
Receive Buffer Descriptor, 5-38
Receive Descriptor Ring Pointer,
5-35
Register Address Port, 5-22
Register Data Port, 5-23
ROM Description, 5-21
SIA Chip Description, 5-18
SlA Chip Overview, 5-15
SlA Chip Receive Mode, 5-18
SlA Chip Transmit Mode, 5-18
Transmit Buffer Descriptor, 5-40
Transmit Descriptor Ring Pointer,
5-36
Time-Of-Year Oock, 2-7,3-58
Timing Diagrams, A-I
TKSO
Loading/Unloading a Tape
Cartridge, 8-15
Using the TI<SO, 8-13
Write Protecting a TKSO Tape
Cartridge, 8-16
TKSO Tape Drive, 8-12

VAXstation 2000 (cont'd.)
System Jumper Configuration,
3-232
Video Monitor, 1-2
VS410 System Box, 1-2
VSXXX Mouse, 1-3

w
Watch Chip Initialization, 3-73
Watch Chip Registers, 3-62
Battery Check Data Registers,
3-71
Boot Device Registers, 3-71
Boot Flags Registers, 3-72
Console Flags Register, 3-69
Console Mailbox Register, 3-68
Console Type Register, 3-71
Control and Status Registers,

3-64
Date and Time-of-year Registers,

3-66
Keyboard Type Register, 3-70
Scratch RAM Address Registers,
3-71
Scratch RAM Length Register,

3-72
Tape Port Information Register,

3-72
Temporary Storage Registers, 3-71
Watch Chip Theory, 3-60

v
VAXstation 2000
LK201 Keyboard, 1-3
System DeScription, 1-1

Index-5

VAXstation 2000
and MicroVAX 2000
Technical Manual
EK-VTTAA-TM-001 -

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TECHNICAL DOCUMENTATION
CHANGE NOTICE

This new Chapter 4, MS400 Option MemClry Modules, replaces the existing
Otapter 4 in the VAXstation 2000 and MicroVAX 2000 Technical Manual,
EK-VTTAA-TM·001.

digital equipment corporation. maynard, massachusetts

Chapter 4

MS400 Option Memory Modules
4.1 Introduction
This chapter describes the MS400-AA, MS400-BA and MS400-CA memory
modules that are options to the KA410-AA system module. The MS400-AA
memory module contains 2 megabytes of memory, the MS400·BA memory module contains 4 megabytes of memory, and the MS400-CA memory
module contains 12 megabytes of memory. The MS400-BA and MS400-CA
have component:; on both sides of the module. Both the MS400-AA and
MS400·BA utilize the 256K DRAMs while the MS400·CA utilizes the 1M
DRAMs. Only one MS400 memory module may be connected to a KA410AA system module. Figure 4-1 shows a front view of the MS400 series
memory module.
j

These MS400 series modules do not provide RAM control signal generation;
however, they do provide transceivers for data and buffers for driving the
RAM array with RAS, CAS, WRITE, and ADDRESS. The KA410-AA system
module generates byte parity when writing to RAM memory and checks
byte parity when reading from RAM memory. Parity checking applies both
to CPU accesses and to DMA accesses generated by the network controller
option. Only those bytes selected by the processor byte mask are affected
and checked.

4.2 Theory of Operation
MS400 option memory is contained in DRAMs. These are the same DRAMs
as described in Section 3.3.1.1. The control signals on the memory module
and the timing cycles are described in this section.

MS400 Option Memory Modules

4-1

Figure 4-1: MS400 Memory Module

(Q] 0

/CI 0

0
0

DODD
DODD
DODD
DOD 0
DODD
DDDD
DODD

o0 0

0
0
01
og Do
0
0

0
0

D O D D (OJ
D O D D (Q]
DODD
DODD
DODD
DODD
DODD
DODD
DODD

°111111111111111111111111111111111111111111

_ _ 11

4.2.1 Memory Module Control Signal Descriptions
Signal ERAS L is the RAS timing signal for the memory on the option module. ERAS is asserted for normal read and write cycles on the memory module (such as physical addresses in the range 0020.0000 through OOFF.FFFF).
Signal SRAS L is the RAS timing signal for RAM memory on the base system module (physical addresses in the range 0000.0000 through 001F.FFFF).
SRAS is negated during normal read and write cycles on the memory module. During refresh cycles, both ERAS and SRAS are asserted.
Bits 22, 21 and 20 of the system dataladdress bus (BDAL22, BDAU1, and
BDAUO on the system module that map to MSEU2, MSEUl, and MSEUO,
respectively on the memory module) are latched in an F373 latch on the
falling edge of VAS L. These latched address bits are decoded by an F138
which generates RAS for one of the four (or two) 1-megabyte memory arrays
on the module. The appropriate decoder output is gated by ERAS true and
SRAS false during normal read and write cycles and is input to the DRAM
chip's RAS pins.

4-2

During a refresh
both ERAS and SRAS are asserted This
the outputs of the
a n d . the mU'!tiplexors to assert:
all the DRAM chips on the option module.

The four CAS>: L signa.ls from the system module pass through F244 buffers
and series damping resistors to the CAS pins on the DRAY"i chips Each
CAS signal is associated with nne of the processor byte masks and so de·
termines vvhkh bytes of a longword ax!!,' affected by a memory read or \vrlte
cyde.
The multiplexed address linesMEMADDx H from the system module
through F244 buffers and series damping resistors to the address pins on the
DRAM chips Tht' timing of row address, RAS assertion, column
and
assertion are controlled by the
module.
Signal BvVRITE L iron) the
module passes through F244 buffers to
This signal also controls the
flow
the \!\tE pins on the DRAl\i
direction in the F245 data tnmceiVl<'TS,
The data input (D) and output (Q) pins of each DRAM chip are WiH'd io,
gether and are sent to the system module data/address bus through
transceivers, The transceivers are enabled \'\'hen both ERAS Land VDEE L
are asserted, The direction of data flow is sel.ected by
BVVRITE L signal.

4.2.2 Memory Cycles
The memoI'}' module responds to three types of memory cycles,
the read, 'write, and refresh cycles. Each cycle on the module is
by the assertion of ERAS L The cyde type is df~lennined
SRAS Land
BWRlTE L as shown In Table 4-1, The timing ('vel(',; for the mern,ory rnodule
are described in Section

Table 4-1:
Cycle

Refn~h

Oe~=rmini!'.g Memory~)'5!e~ ____,."._.._,".,.,...."__
£R4.S t

SRAS L

BWRITE L

Trul'

Pa.!sf'

F~IM?-

True

FaiSl':

Inte

True

False

MS400 OptIon Memory ~,;1odules

4-3

4.3 Connector Pinouts
Connector Jl carries power, address, and control signals as listed in Table 4-2. Connector J2 carries the buffered processor data/address bus
(BDAL31:00) as listed in Table 4-3.

Table 4-2: Connector J1 Pinout
Description

Signal

+5VC

+5 VB

GND

PBlT03 H

Parity bit for byte 3

PBIT02 H

Parity bit for byte 2

PBITOl H

Parity bit for byte 1

PBITOOH

Parity bit for byte 0

MSIZE2 L

Memory size bit 2

MEMAD8H

Multiplexed address bit 8

MEMAD7H

Multiplexed address bit 7

MEMAD6H

Multiplexed address bit 6

13
14

GND
GND

MEMAD5H

Multiplexed address bit 5

MEMAD4H

Multiplexed address bit 4

MEMAD3H

Multiplexed address bit 3

MEMAD2H

Multiplexed address bit 2

MEMAD1H

Multiplexed address bit 1

MEMADOH

Multiplexed address bit 0

MSIZEl L

Memory size bit 1

MSIZEO L

Memory size bit 0

CAS3L

CAS for byte 3

CAS2L

CAS for byte 2

4-4

Table 4-2

Connector J1 Pinout

Signal

Description

CAS) t

CAS for

CASnL

CAS for

eND

GND

MSELC H

BDAL22 H from system

3.()

ERAS L

Ext~~nded ftl\S (ERAS [rem the standard cem

SRAS L

Standard RM; tSRA50 frorl1 the :;ianriOl,cd (ell,!

MSELB H

FDAL::'1 H from ~\,litli'm

MSEU,\ H

BDAL2D H from system

VAS L

Address strob" (BASI L on ~w~t!.'!n moduli:)

VDBE L

Data /1US enable

BWRfTE L

W,rHe (j:l\I;,'IUTEl Lon Syst;:ffi module)

GND

~,:;,

+5 VA

_ _ _ _ _ _ ..... ""'....,_""'_'-;;_'"',______

~_......,.,_~"<v_~"

..... _ _ ...... ... _,,...._ .... __._,. _ _ _ ... ,''''''_ _ _ _ _
_~'

~,'',

... _____

>,~,

Option Memory

4-5

Table 4-3: ConnectorJ2 Pinout

_--_ .,-----.. .,._----_ __ --_ __ _

Signal
.•....

......

....

Signal

...

GND

BDAL15 B

;;

C>H)

8DAL14 !-Ii

BDAL31 H

BDALD H

RDAun H

8D.A.U.2 H

BDAL29 H

BDAUI B

BDr'>:UfS 1'1

HD.i\.LW H

B[)i\L27 H

(;!'~r)

EDAL26 H

C1\'D

BDAL25 H

BDAlJ)!) I-j

BD/~L24 H

.)e.•

"'!"}

BD.ALf\t{ f·'

BDAL23 H

J!,

B[).AL07 H

BDALl2 H

I~I)t\lJ}6 Ii

GNU

BDALiiS H

GND

.34

Bf)Al.,ti4 r~

BDAL21 H

:'..!:;.

flDAU;3 }i

BDAL20 H

2>6

BDAU!2 1-1

\3DAU9 H

BI)AtJ'1 H

l,~

BDAL18 1-1

BO;\LO[l H

BDAL1i H

C!i-'·~r)

~('

BDAL/6 H

C:NI)

.i.,,J

..-

...

_--

... _,.,.............

4.4 Configuration Jumpers
There are no field-modifiable iumpNs on the n1c'dule The version of the
rnoduie is determined by three' .,
on connecter Tl
three
are either disconnected (open) or grounded to indicate which memor;,: D.1.0d·
ule is insta!!ed. Table 4-4 lists the three
and the preset
jumpers for each rnemory module.

4-6

Signal

Pin 01)

MSIZE2 L

MSIZEI L

MSIZEOl

MS400-AA

MS400·SA

MS400-CA
Gmucd

Ground

G!ollnd

GroUHli

Ground

4.5 Power Requirements
The memory modules require + 5 volts DC with a tole.rance
five percent. The typical cum:?nt drawn is .5

or rnlnu~

MS400 Option Memory Modul€s

4-7

TECHNICAL DOCUMENTATION
CHANGE NOTICE

VAX.tatfon 2000 and MicroVAX 2000 TECHNICAL MANUAL

EK·VITAA·TM-OOI

This notice contains a change to the VAXsflltion 2000 tmd MiaoVAX 2000 TtdtniaJl Manual.

Update your manual as indicated with the infonnation praented below.
PAGI3-138
Change the description of the Data Rate (Bits/Second), as foUows.

PROM:
11

Data Aata (Bltl/Second')

19200

TO:
11

Data Aate (BItt/SecondS)

19800 (Non'tandard)

digital equipment corporation a maynard, massachusetts