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EK-SBC01-UG-001

June 1982

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Document:	SBC-11/21 Single-Board Computer Users Guide
Order Number:	EK-SBC01-UG
Revision:	001
Pages:	357
Original Filename:	EK-SBC01-UG-001_SBC-1121_Single-Board_Computer_Users_Guide_Jun1982.pdf

OCR Text

EK -SBCO 1-UG-OO 1

SBC-11/21
Single-Board Computer
User's Guide

momoomD

EK-SBCO 1-UG-001

SBC-11/21
Single-Board Computer
User's Guide

Prepared by Educational Services
of
Digital Equipment Corporation

1st Edition, June 1982

The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

The manuscript for this book was created on a DIGITAL Word
Processing System and, via a translation program, was
automatically typeset on DIGITAL's DECset-8000 Typesetting
System. Book production was done by Educational Services
Development and Publishing in Marlboro, MA.

The following are trademarks of Digital Equipment Corporation:
DEC
DECnet
DECUS
DECsystem-IO
DECSYSTEM-20
DECwriter
DIBOL

~DmDDmD

EduSystem
lAS
MASS BUS
MINC-II
OMNIBUS
OS/8
PDP
PDT

RSTS
RSX
TOPS-IO
TOPS-20
UNIBUS
VAX
VMS
VT

CONTENTS
Page
PREFACE
CHAPTER 1

INTRODUCTION

1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.3
1.4

INTRODUCTION.................................................................................................
SPECIFICATIONS...............................................................................................
Physical...........................................................................................................
Power Requirements.......................................................................................
Bus Loading....................................................................................................
Environmental....... .... .... .......................... .... ..... .... ... .... ..... ...... ..... ... ........... .....
BACKPLANE PIN IDENTIFICATION .............................................................
RELATED DOCUMENTS ...................................................................................

CHAPTER 2

INSTALLATION

2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.7.1
2.2.7.2
2.2.7.3
2.3
2.4
2.5
2.5.1
2.5.2
2.6
2.6.1
2.6.2"
2.6.3

INTRODUCTION................................................................................................. 2-1
SELECTING OPERATIONAL FEATURES ..................................................... 2-1
Battery Backup ................. ...... ..... ... ................. ... .... .... ...... ..... ..... ... .......... ....... 2-1
Wake Up Circuit ............................................................................................ 2-8
Starting Address.. ........................................................................................... 2-8
Interrupts .. ................. ...... ..... ..... ..... ..... .......... .... .... ... .... ....... ..... ..... ........ ......... 2-8
Parallel I/O .................................................................................................... 2-11
Serial I/O ....................................................................................................... 2-12
Memories........................................................................................................ 2-16
Memory Maps ........................................................................................ 2-16
PROMs/EPROMs ................................................................................. 2-16
RAMs ..................................................................................................... 2-16
SELECTING BACKPLANES AND OPTIONS ................................................. 2-22
POWER SUPPLy .................................................................................................. 2-22
EXTERNAL CABLES .......................................................................................... 2-22
Parallel I/O Interface (13) ............................................................................. 2-23
Serial Line Interfaces (11 and 12) .................................................................. 2-25
VERIFYING OPERATION ................................................................................. 2-28
Macro-ODT Option .......................... :............................................................. 2-28
Loopback Connectors. ... .... ............ ......... .... ............... ..... ..... ......... ... ..... .......... 2-28
Verification Procedure.... .................. .... .... ..... ....... .... .... ..... ........ ... .... ....... ....... 2-28

CHAPTER 3

OPTIONS

3.1
3.2
3.3

INTRODUCTION.................................................................................................
SUPPORTED OPTIONS ......................................................................................
UNSUPPORTED OPTIONS ................................................................................

iii

1-1
1-3
1-3
1-3
1-3
1-4
1-4
1-7

3-1
3-1
3-4

CONTENTS (Coot)
Page
CHAPTER 4

MACRO-ODT

4.1

4.2
4.3
4.3.1
4.3.2
4.4
4.4.1
.4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8
4.4.9
4.5
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.6.7
4.6.8

INTRODUCTION.................................................................................................
INSTALLATION AND CONFIGURATION ....................................................
ENTRY CONDITIONS ............................................ ,...........................................
Macro-ODT Input Sequence ..........................................................................
Macro-ODT Output Sequence .......................................................................
MACRO-ODT COMMANDS...............................................................................
/(ASCII 057) Slash........................................................................................
<CR> (ASCII 15) Carriage Return ............................................... .............
<LF> (ASCII 12) Line Feed.......................................................................
R (ASCII 122) Internal Register Designator .................................................
S (ASCII 123) Processor Status Word (PSW)...............................................
G (ASCII 107) Go..........................................................................................
P (ASCII 120) Proceed ....................................... ...... ......................... ............
DD, DX, DY Bootstraps.................................................................................
X (ASCII 130) Diagnostics ....................................... ......................... ............
INITIALIZATION ...............................................................................................
WARNINGS AND PROGRAMMING HINTS .................................................
Error Decoding .... ...... .... ...... ... .......................................... ..............................
ODT Stack Warning........................................................................................
Addresses to Avoid.........................................................................................
CPU Priority...... .............................. ....... ........................................................
Terminal Related Problems. ........................................... .................... ............
Spurious Halts ... ................................................................................... ..........
Serial I/O Protocol.. .... .... .............................................................. ..... ....... .....
Interrupt Vector Initialization ............................................................ ............

CHAPTERS

SYSTEM ARCHITECTURE

5.1
5.2
5.2.1
5.2.1.1
5.2.1.2
5.2.2
5.2.3
5.3
5.4
5.5

INTRODUCTION.................................................................................................
MICROPROCESSOR ARCHITECTURE..........................................................
Registers ..... ....................................................................................................
General Registers.. ..... .... ....................................... ... ... ...........................
Status Register ............................................................................... ........
Hardware Stack..............................................................................................
Interrupts ........................................................................................................
DMA (DIRECT MEMORY ACCESS)................................................................
MEMORY ORGANIZATION.............................................................................
POWER-UP/POWER-DOWN FACILITy.........................................................

CHAPTER 6

PROGRAMMING INFORMATION

6.1
6.2
6.2.1
6.2.2
6.3
6.3.1
6.3.1.1

INTRODUCTION................................................................................................. 6-1
ASYNCHRONOUS SERIAL LINE UNITS ...................................................... 6-1
Data Baud Rates.............. ............................................................................... 6-1
Interrupts ........................................................................................................ 6-7
PROGRAMMING THE PARALLEL I/O INTERFACE .................................. 6-7
Modes of Operation............. ........................................................................... 6-7
Port C Register .... ............................................... ................. ......... .......... 6-10
iv

4-1
4-1
4-1
4-1
4-2
4-2
4-2
4-5
4-5
4-5
4-6
4-6
4-6
4-6
4-8
4-8
4-8
4-8
4-8
4-8
4-8
4-8
4-8
4-9
4-9

5-1
5-1
5-1
5-1
5-1
5-2
5-2
5-4
5-4
5-4

CONTENTS (Cont)
Page
6.3.1.2
6.3.1.3
6.3.1.4
6.3.1.5
6.3.1.6
6.3.2
6.3.2.1
6.3.2.2
6.3.3
6.3.4

Mode 0 Basic Input/Output.. ................................................................. 6-10
Port A and B Registers........................................................................... 6-11
Port C Register in Mode 0 ...................................................................... 6-11
Mode 1 (Strobed Input/Output) ............................................................ 6-11
Mode 2 (Strobed Bidirectional I/O) ...................................................... 6-18
Control Word Register ................................................................................... 6-22
Mode Selection ...... ................................... ... ................................ ........... 6-22
Setting Bits in Port C .............................................................................. 6-22
Parallel I/O Initialization ............................................................................... 6-25
Parallel I/O Handshaking .............................................................................. 6-25

CHAPTER 7

ADDRESSING MODES AND INSTRUCTION SET

7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.3.1
7.2.3.2
7.2.3.3
7.2.3.4
7.2.4
7.2.5
7.2.5.1
7.2.5.2
7.2.5.3
7.2.5.4
7.2.6
7.3
7.3.1
7.3.2
7.3.3
7.3.3.1
7.3.3.2
7.3.3.3
7.3.3.4
7.3.4
7.3.4.1
7.3.4.2
7.3.5
7.3.5.1
7.3.5.2
7.3.5.3
7.3.5.4
7.3.5.5
7.3.5.6
7.3.5.7
7.3.5.8
7.3.5.9

INTRODUCTION................................................................................................. 7-1
ADDRESSING MODES ....................................................................................... 7-1
Single Operand Addressing ............................................................................ 7-3
Double Operand Addressing........................................................................... 7-3
Direct Addressing ........................................................................................... 7-5
Register Mode (Mode 0) ........................................................................ 7-6
Autoincrement Mode (Mode 2).............................................................. 7-8
Autodecrement Mode (Mode 4) ............................................................. 7-10
Index Mode (Mode 6) ............................................................................. 7-11
Deferred (Indirect) Addressing. ................... .................................................. 7-14
Use of the PC as a General-Purpose Register................................................. 7-17
Immediate Mode .................................................................................... 7-18
Absolute Addressing ............................................................................... 7-19
Relative Addressing ............................................................................... 7-20
Relative Deferred Addressing ................................................................ 7-21
Use of the' Stack Pointer as a General-Purpose Register ................................ 7-22
INSTRUCTION SET ............................................................................................ 7-22
Instruction Formats ........................................................................................ 7-23
List of Instructions .......................................................................................... 7-26
Single Operand Instructions ........................................................................... 7-28
General ................................................................................................... 7-29
Shifts and Rotates .................................................................................. 7-32
Multiple Precision .................................................................................. 7-37
PS Word Operators ................................................................................ 7-40
Double Operand Instructions .......................................................................... 7-41
General......... ................ ........ ............................. ...... ............................... 7-41
Logical ..................................................................................................... 7-44
Program Control Instructions ......................................................................... 7-47
Branches ................................................................................................. 7-47
Signed Conditional Branches ................................................................. 7-52
Unsigned Conditional Branches ............................................................. 7-54
Jump and Subroutine Instructions ......................................................... 7-56
Traps ....................................................................................................... 7-61
Reserved Instruction Traps .................................................................... 7-65
HALT Interrupt ..................................................................................... 7-65
Trace Trap .............................................................................................. 7-65
Power Failure Interrupt .......................................................................... 7~65

CONTENTS (Cont)
Page
7.3.5.10
7.3.5.11
7.3.6
7.3.7

Interrupts................................................................................................ 7-65
Special Cases (T-bit) .............................................................................. 7-66
Miscellaneous Instructions ............................................................................. 7-66
Condition Code Operators .............................................................................. 7-68

CHAPTER 8

THEORY OF OPERATION

8.1
8.2
8.2.1
8.2.1.1
8.2.1.2
8.2.2
8.2.3
8.2.4
8.2.4.1
8.2.4.2
8.2.4.3
8.2.4.4
8.2.4.5
8.2.4.6
8.2.4.7
8.2.5
8.2.5.1
8.2.5.2
8.2.5.3
8.2.5.4
8.2.5.5
8.2.5.6
8.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15

INTRODUCTION................................................................................................. 8-1
MICROPROCESSOR........................................................................................... 8-1
Microprocessor Initialization.......................................................................... 8-1
RESET Instruction................................................................................ 8-4
Power-up Input (PUP) .............................. ~............................................. 8-4
Clock Input ( - TCLK) ..... ... .................... ..... ....... .... ...... ....... ................ ... ....... 8-5
Ready Input (READY) .................................................................................. 8-5
Microprocessor Control Signals................ ... ....... .... ...... .... .... ................ ... ....... 8-5
Row Address Strobe (RAS) ...... ....... .... ....... .... ...... .......................... ....... 8-5
Column Address Strobe (CAS) .............................................................. 8-5
Priority In (PI) .................................................. ,..................................... 8-5
Read/Write (R/ - WHB and R/ - WLB) ............................................. 8-5
Select Output Flags (SELO and SELl) .......... ;....................................... 8-5
Bus Clear (BCLR) .................. :............................................................... 8-6
Clock Out (COUT) ................................................................................ 8-6
Microprocessor Transactions.......................................................................... 8-6
Fetch/Read ............................................................................................ 8-6
Write....................................................................................................... 8-8
IAK......................................................................................................... 8-8
DMA ...................................................................................................... 8-8
ASPI....................................................................................................... 8-8
NOP ........................................... ;............................................................ 8-8
MODE REGISTER CONTROL. .......................................................................... 8-10
INTERRUPT CONTROL ..................................................................................... 8-14
Interrupt Control Logic .................................................................................. 8-15
Ready Logic .................................................................................................... 8-17
IAK Data In (IAKDIN) ................................................................................. 8-19
HALT Interrupt.. ..... ...... ................. ................... ....................................... ... ... 8-19
Power Fail (-PFAIL) .................................................................................... 8-22
Local ............................................................................................................... 8-22
External .......................................................................................................... 8-22
DMA Interrupt ............................................................................................... 8-23
DC004 PROTOCOL ...................... ..................................... ............................. ... ... 8-23
ADDRESS LATCH ............................................................................................... 8-23
MEMORY ADDRESS DECODE ........................................................................ 8-23
RAM MEMORY ................................................................................................... 8-23
ROM/RAM MEMORY SOCKETS ..................................................................... 8-25
SERIAL LINE INTERFACE UNITS ........................................ ......................... 8-26
PARALLEL I/O INTERFACE ............................................................................ 8-28
POWER-UP.................................... :........................................................................ 8-30
CLOCK ................................................................................................................... 8-30
CLOCK CONTROL .............................................................................................. 8-32
DMA ....................................................................................................................... 8-32
vi

CONTENTS (Coot)
Page
8.16
8.17
8.18
8.19

TSYNC ................................................................................................................... 8-35
READ/WRITE ...................................................................................................... 8-35
REPLY TIME-OUT ............................................................................................... 8-37
BUS CONTROL .................................................................................................... 8-37

CHAPTER 9

LSI-H BUS

9.1
9.2
9.3
9.4.1
9.4.2
9.5
9.5.1
9.5.2
9.6
9.6.1
9.6.2
9.6.3
9.6.4
9.7
9.8

INTRODUCTION ................................................................................................. 9-1
SBC-ll/21 SINGLE-BOARD COMPUTER .......... :............................................ 9-2
MASTER/SLAVE RELATIONSHIP .................................................. ............... 9-2
DATA TRANSFER BUS CYCLES ..................................................................... 9-3
Bus Cycle ProtocoL......................................................................................... 9-4
Direct Memory Access................................................................................... 9-8
INTERRUPTS ....................................................................................................... 9-12
Device Priority.................. ..... ....... .... .................. ....... ...... .... ............ ........ ....... 9-12
Interrupt Protocol ........................................................................................... 9-12
CONTROL FUNCTIONS .................................................................................... 9-14
Halt ................................................................................................................. 9-14
Initialization... .... ...... .... ...... ......................... .... .... ...... ..... ...... ........ .... ......... ...... 9-14
Power Status ................................................................................................... 9-14
Power-Up/Power-Down Protocol ................................................................... 9-15
LSI-II BUS ELECTRICAL CHARACTERISTICS ........................................... 9-16
MODULE CONTACT FINGER IDENTIFICATION ....................................... 9-16

APPENDIX A

INSTRUCTION TIMING

APPENDIXB

PROGRAMMING DIFFERENCE LIST

APPENDIXC

SOFTW ARE DEVELOPMENT

APPENDIXD

MACRO-ODT ROM

APPENDIXE

SBC-H/2l SCHEMATICS

APPENDIXF

GLOSSARY

.9.4

INDEX

FIGURES
Figure No.
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7

Title

Page

KXT11-AA (M8063-BA) SBC-l1/21 Module....................................................... 1-2
SBC-11/21 Module Layout .................................................................................... 2-2
Interrupt Configurations ............ ,............. ........ ... .... .... ........ ...... ...... ........ ................ 2-10
Time-out During LSI-II Bus Interrupt Acknowledge ............................................ 2-11
Parallel I/O Configuration ..................................................................................... 2-12
Socket Sets A and B Interconnection..................................................................... 2-17
Memory Configuration ........................................................................................... 2-18
Memory Maps ......................................................................................................... 2-19
vii

FIGURES (Cont)
Figure No.
2·8
2·9
2·10
2·11
5·1
5·2
6·1
6·2
6·3
6·4
6·5
6·6
6·7
6·8
6·9
6·10
6·11
6·12

6·13
6·14
7·1
7·2
7·3
7-4
7·5

7·6
7·7
7·8
7·9
7·10
7·11
7·12

7·13
7·14
7·15
7·16
7·17
7·18
7·19
7·20
7·21
7·22
7·23
7·24
7·25
7·26
7·27
7·28
7·29
7·30
7~31

Title

Page

30·Pin Parallel I/O Connector ................................................................................ 2·24
10·Pin Serial Line Unit Connector .......................................................................... 2·26
BC20N·05 Null Modem Cable ............................................................................... 2·27
BC21B·05 Modem Cable ........................................................................................ 2·27
Registers and Processor Status Word ..................................................................... 5·2
Memory Maps...... ..... ........ ... .............................. ..................................................... 5·6
Serial Line Unit (SLU) Interface ........................................................................... 6·2
Serial Line Unit Register Bit Maps ........................................................................ 6·3
Parallel I/O Interface............................................................................................. 6·8
Parallel I/O Flowchart ........................................................................................... 6·9
Mode 0 Port A or B Bit Assignments..................... .... .............. ..... ....... ..... .............. 6·11
Mode 0 Port C Bit Assignments .............................................................................. 6·12
Mode 1 Port C Bit Assignments .............................................................................. 6·15
Mode 2 Port C Bit Assignments .............................................................................. 6·20
Mode 1 Input Data Handshaking Sequence ........................................................... 6·26
Mode 1 Strobed Input Timing ................................................................................. 6·26
Mode 1 Output Data Handshaking Sequence ........................................................ 6·27
Mode 1 Port A Strobed Output Timing .................................................................. 6·28
Mode 1 Port B Strobed Output Timing .................................................................. 6·28
Mode 2 Port A Bidirectional Timing ...................................................................... 6·29
Single Operand Addressing .................................................................................... 7·3
Double Operand Addressing ................................................................................... 7·3
Mode 0 Register ...................................................................................................... 7·5
Mode 2 Autoincrement ........................................................................................... 7·5
Mode 4 Autodecrement .......................................................................................... 7·6
Mode 6 Index .......................................................................................................... 7·6
INC R3 ................................................................................................................... 7·7
ADD R2,R4 ............................................................................................................. 7·7
COMB R4............................................................................................................... 7·8
CLR (R5)+ ............................................................................................................ ' 7·8
CLRB (R5) + .......................................................................................................... 7·9
ADD (R2)+,R4...................................................................................................... 7·9
INC -(RO) ............................................................................................................. 7·10
INCB -(RO) .......................................................................................................... 7·11
ADD -(R3),RO ...................................................................................................... 7·11
CLR 200(R4) .......................................................................................................... 7·12
COMB 200(Rl) .................... ~ ................................................................................. 7·13
ADD 30(R2),20(R5) ............................................................................................... 7·13
Mode 1 Register Deferred ...................................................................................... 7·14
Mode 3 Autoincrement Deferred ............................................................................ 7·14
Mode 5 Autodecrement Deferred ........................................................................... 7·15
Mode 7 Index Deferred ........................................................................................... 7·15
CLR @R5 ................................................................................................................ 7·15
INC @(R2)+ ........................................................................................................... 7·16
COM @ -(RO) ....................................................................................................... 7·16
ADD @1000(R2),Rl ............................................................................................... 7·17
ADD.#10,RO ........................................................................................................... 7·19
CLR @#1100 ........................................................................................................... 7·20
ADD @#2000,R3 .................................................................................................... 7·20
INC A ........................... ~ ......................................................................................... 7·21
CLR @A ................................................................................................................. 7·22
viii

FIGURES (Cont)
Figure No.
7-32
7-33
7-34
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
8-20
8-21
8-22
8-23
8-24
8-25
8-26
8-27
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
C-l
C-2
C-3
C-4
C-5
C-6
C-7
C-8
C-9
C-I0
C-l1
C-12

Title

Page

Byte Instructions ..................................................................................................... 7-25
Multiple Precision ................................................................................................... 7-37
JSR Example .......................................................................................................... 7-59
SBC-ll/21 Functional Block Diagram................................................................... 8-2
SBC-ll/21 Microprocessor .................................................................................... 8-4
Fetch/Read Transaction......................................................................................... 8-7
Write Transaction ................................................................................................... 8-9
IAK Transaction ..................................................................................................... 8-10
DMA Transaction ................................................................................................... 8-11
ASPI Transaction................................ ... .............................. .................................. 8-12
BUS NOP Transaction ........................................................................................... 8-12
Mode Register Control............................................................................................ 8-13
SBC-l1/21 Interrupt Control ................................................................................. 8-14
Interrupt Control Logic ...... ...... ................ ....... ............ ............ ..................... ..... ..... 8-17
Ready ...................................................................................................................... 8-18
IAKD IN ................................... ..... ........................ ............. ..... ............... ................ 8-20
HALT Interrupt ..................................................................................................... , 8-21
Memory Maps .......... .......... ....... .................... .... .... ................... .................... ........... 8-24
RAM Memory.......................... ... ... .................... ........................... ............ ...... .... ... 8-25
ROM/RAM Memory Sockets ................................................................................ 8-26
Serial Line Interface Units ..................................................................................... 8-27
Parallel I/O Interface .......... ~ .................................................................................. 8-29
Power-up ....................... ....... .... ... .... ...................... ..................................... ..... ........ 8-31
Clock ....................................................................................................................... 8-31
Clock Control .......................................................................................................... 8-33
DMA ....................................................................................................................... 8-34
TSYNC ................................................................................................................... 8-35
Read/Write............................................................................................................. 8-36
Reply Time-out ....................................................................................................... 8-38
Bus Control ............................................................................................................. 8-39
DATI Bus Cycle ..................................................................................................... 9-6
DATI Bus Cycle Timing......................................................................................... 9-7
DATO or DATOB Bus Cycle ................................................................................. 9-9
DATO or DATOB Bus Cycle Timing ..................................................................... 9-10
DMA Protocol. ........................................................................................................ 9-11
DMA Request/Grant Timing ................................................................................. 9-12
Interrupt Request/ Acknowledge Sequence ............................................................ 9-13
Power-Up/Power-Down Timing .............................................................................. 9-15
Double-Height Module Contact Finger Identification ........................................... 9-16
Overview of Software Development. ................. .......... ......... .................................. C-3
Application Overview .................................. .......................... ....... ................. ......... C-5
Monitor Program ............... .... ... .... .................... .......................... .... ......... ..... .......... C-6
Load Map................................................................................................................ C-8
Power-up Task......................................................................................................... C-9
Power Fail Recovery.. ............ .................. .................... ...... .............. ....................... C-9
SLU Diagnostic Task .............................................................................................. C-I0
RAM Diagnostic Task ............................................................................................ C-I0
ROM Diagnostic Task ............................................................................................ C-l1
Parallel I/O Diagnostic Task .................................................................................. C-l1
Control Task ............................................................................................................ C-12
Power Fail Task ....................................................................................................... C-13
ix

TABLES
Table No.

1-1
1-2
2-1

2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10 .
2-11
2-12
2-13
2-14
2-15
4-1
4-2
5-1
5-2
5-3
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11

6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
7-1
7-2
7-3
7-4
7-5

Title

Page

SBC-l1/21 Module Backplane Pin Identification.................................................. 1-5
Related Documentation ............................................................... ........................... 1-7
Configuration Pin Definitions ...................... .... .... ............ ................... .................... 2-3
Configuration Pin Functions .................... ............................. .......................... ........ 2-5
Standard Factory Configuration.............................................................................. 2-7
Mode Register Configuration .... ................................. ................................ ............ 2-9
Mode 0 Buffer Configuration (No Handshake) ...................................................... 2-13
Mode 1 Buffer Configuration (Strobed I/O) .......................................................... 2-14
Mode 2 Buffer Configuration and Handshake ........................................................ 2-15
SLUI BREAK Detection ....................................................................................... 2-15
Memory Map Configurations ................................................................................. 2-20
Socket Set A Configuration for EPROM/PROM ................................................. 2-20
Socket Set B Configuration for EPROM/PROM .................................................. 2-21
Socket Set A Configuration for RAM .................................................................... 2-22
Socket Set B Configuration for RAM .................................................................... 2-22
EIA Slew Rate Resistor Values .............................................................................. 2-26
Diagnostic Fault Indicators..................................................................... ................ 2-29
Macro-ODT Commands ......................................................................................... 4-3
Macro-ODT States and Valid Input Characters..................................................... 4-4
Processor Status Word Bit Descriptions ................................................................. 5-3
PSW Interrupt Levels .............. ..................................... .... ................................ ...... 5-3
SBC-ll/21 Interrupts............................................................................................. 5-5
Serial Line Unit Register Addresses....................................................................... 6-3
Receiver Control and Status Bit Descriptions ........................................................ 6-4
Receiver Data Buffer Bit Descriptions ................................................................... 6-4
Transmitter Control and Status Bit Descriptions ................................................... 6-5
Transmitter Data Buffer Bit Descriptions .............................................................. 6-6
Parallel I/O Register Addresses............................................................................. 6-7
Mode 0 Configuration ............................................................................................. 6-10
Mode 0 Port A or B Bit Descriptions ................................................... ................... 6-11
Mode 0 Port C Bit Descriptions .............................................................................. 6-12
Port C Control Signals in Mode 1 ................................ ........................................... 6-13
Combinations of Mode 1 ......................................................................................... 6-14
Mode 1 Port C Bit Descriptions .............................................................................. 6-15
Mode 1 Configuration ........ ........ ........ ..................................................... ................ 6-18
Port C Control Signals in Mode 2................... ........................................................ 6-19
Mode 2 Port C Bit Descriptions :............................................................................. 6-20
Mode 2 Configuration ............................................................................................. 6-21
Control Register Mode Selection Bit Functions ................... ,................................. 6-22
Control Words for Mode Selection ......................................................................... 6-23
Control Register Bit Set/Reset Functions .............................................................. 6-24
Interrupt Set/Reset Control Words ........................................................................ 6-24
Mode 1 Input Handshaking Signals ........................................................................ 6-25
Mode 1 Output Handshaking Signals ..................................................................... 6-27
Mode 2 Bidirectional Handshaking Signals ............................................................ 6-29
Sample SBC-l1/21 Instructions............................................................................. 7-4
Direct Addressing Modes........................................................................................ 7-5
Indirect Addressing Modes ......... ........ ..................... ....... ... ........................ ....... ...... 7-14
Register Addressing Modes .................................................................................... 7-18
SBC-ll/21 Instruction Set ..................................................................................... 7-26

TABLES (Coot)
Table No.

8-1
8-2
8-3
8-4
9-1
9-2
9-3
9-4
A-I
B-1
B-2

Title

Page

Start Address Configurations ................................................................................. 8-13
Designated Interrupts ............................................................................................. 8-16
Serial Line Unit Registers ...................................................................................... 8-28
PPI Addrt;ssable Registers...................................................................................... 8-30
Signal Assignments ..... ........... ....... ..... ........ ........ ..... .......... .... .... ..... .... ....... ...... ..... ... 9-3
Data Transfer Operations ....................................................................................... 9-4
Bus Signals Used in Data Transfer Operations....................................................... 9-4
Bus Pin Identifiers ...... .... ..... .......... .... ...... ....... ........ ... .... .... ... ... ...... ..... ....... ......... .... 9-17
Instruction Timing ............ ... ..... ...... ...... ...... ....... ..... .... .... ... ... ... ...... .... ........ ......... .... A-I
SBC-l1j21, LSI-llj2, and LSIjllj23 Comparisons ............................................ B-1
Illegal Address Traps ..... .... ......... ....... ........ ........ ..... .... .... .... .... ...... .... .......... ...... ....... B-6

PREFACE

This User's Guide provides the user with configuration, system architecture, and programming information for the SBC-II/2I single-board computer. The configuration requirements are described in
Chapter 2, and the system architecture is presented in Chapter 5. The programming techniques are
described in Chapter 6, and the instruction set is listed in Chapter 7. Operational theory is presented in
Chapter 8, and the schematics are in Appendix E. The Macro-ODT option is described in Chapter 4,
and the listing is in Appendix D. Options for use on the LSI-ll bus are listed in Chapter 3, and the
module bus requirements are described in Chapter 9. An example of software development is covered
by Appendix C. Appendix A summarizes the instruction timing, and Appendix B compares the SBC11/21 to other LSI-II microprocessors.
NOTE
This User's Guide is for use with the SBC-ll/21
module, MS063 Revision D and subsequent revisions
only. This revision is identified by the circuit board
#50144SD-XX located on the module as described in
Figure 1-1. Use manual EK-KXTll-UG for Revision C modules.

xiii

CHAPTER 1
INTRODUCTION

1.1 INTRODUCTION
The KXTII-AA (M8063-BA) module, called the SBC-ll/21 single-board computer, is shown in Figure
1-1. It is a complete computer system on an 8.5 X 5.2 inch printed circuit board that executes the wellknown PDP-ll instruction set (see Appendix B). The SBC-ll/21 module contains 4Kb (kilobytes) of
RAM, sockets for up to 32Kb of PROM or additional RAM, two serial I/O lines, twenty-four lines of
parallel I/O, and a 50 Hz, 60 Hz, or 800 Hz real-time clock. In addition, the SBC-ll/21 supports the
complete LSI-ll bus interface that enables it to communicate with most of Digital's large family of
modules (see Chapter 3) described in the Microcomputer Interfaces and Microcomputers and Memories handbooks.

The SBC-ll/21 computer features the following:
•

A powerful processor running the PDP-ll instruction set.

•

Direct addressing of 32K, 16-bit words or 64K, 8-bit bytes (K = 1024).

•

Efficient processing of 8-bit characters without the need to rotate, swap, or mask.

•

On-board 4Kb of static read/write memory.

•

Sockets for up to 32Kb of PROM for a wide range of memory types from many vendors.
Additional RAM can also be installed in these sockets.

•

Hardware memory stack for handling data, subroutines, and interrupts.

•

Direct memory access for high data rate devices.

•

Eight general-purpose registers for data storage, pointers, and accumulators; two are dedicated: stack pointer (SP) and program counter (PC).

•

Fast on-board bus for high throughput when external memory access is not needed.

•

LSI-II bus structure that provides position dependent priority for peripheral device interfaces connected to the bus.

•

Fast vectored interrupt response without device polling.

•

A powerful set of instructions.

•

Two serial I/O interfaces, compatible with EIA RS-232C and EIA RS-423, with software
programmable baud rates over the range of 300 to 38,400 baud.

1-1

0000

E62

E6l

OOD
IC40/

~
~
~

12 E50
12 E49
E60

IC361

XE59

I C271

IC351

XE58

/c261

IC341

XE57

IC251

E56

I§

E48

p[§]

XE55

~. ~ ~

IC321 XE54 IC301
D

IC231 XE44

IC181

I~f

E53

E38

D DO

lru§

I~gl

E52

XE45

E5l

E43

E19

E47

12
Z4

E3,7

1@]2
DCC

E18

12 E2
12

MA·7527

Figure 1-1

KXTll-AA (MS063-BA) SBC-llj21 Module

1-2

•

One parallel I/O interface with two bidirectional S-bit input/output ports and one S-bit control port.

•

Real-time clock that can be set by the user to 50 Hz, 60 Hz, or SOO Hz.

•

Jumper-selected operating modes, including four memory maps, exception handling, start
and restart addresses, parallel I/O configurations, and real-time clock frequency.

•

Optional PROM resident Macro-ODT containing module diagnostics, bootstrap programs
for mass storage devices (TU5S, RXOI, and RX02), console communications, and on-line debugging facility.

1.2 SPECIFICATIONS
The SBC-l1 /21 module specifications follow:
1.2.1

1.2.2

Physical
Height

13.2 em (5.2 in)

Length
(includes module handle)

22.S em (S.9 in)

Width

1.27 em (0.5 in)

Weight

360 g (12 oz) maximum

Power Requirements
Power Supply:
+5.0 V ± 5%

2.5 A (typical), 2.S A (maximum)

+12.0 V ± 5%

60 rnA (typical) used by on-board circuitry, 1.1 A (maximum)
includes current provided to outside interface through pin 10 of
the serial I/O connector

Battery Backup:
+5.0 V ± 5%

170 rnA (typical), 260 rnA (maximum)
NOTE
The + 12.0 V typical current is measured with no
connections at pin 10 of the serial I/O connectors
(fused line).

1.2.3 Bus Loading
AC Loads
DC Loads

2.4

1.0

1-3

1.2.4 Environmental
Temperature:
-40° C to 65° C (-40° F to 150° F)
5° C to 60° C (41° F to 140° F)

Storage
Operating

NOTE
The module must be brought into the operating temperature environment and allowed to stabilize before
operating.
Relative Humidity:
10% to 90% (no condensation)
10% to 90% (no condensation)

Storage
Operating
Altitude:

Up to 15 km (50,000 ft)
Up to 15 km (50,000 ft)
(90 mm mercury minimum)

Storage
Operating

NOTE
Lower the maximum operating temperature by 1° C
(1.8° F) for each 300 m (1,000 ft) of altitude above
2.4 km (8,000 ft).
Environment:

Air must be noncaustic.

Airflow (operating):

There must be enough airflow to limit the input to output temperature rise across the module to 5° C (9° F) when the input
temperature is 60° C (140° F). For operation below 55° C
(131 ° F), there must be enough airflow to limit the input to
output temperature rise across the module to 10° C (18° F)
maximum.

NOTE
These are design limits. Lower temperature limits
will help increase the life of the product.
1.3 BACKPLANE PIN IDENTIFICATION
Table 1-1 lists backplane pin connections for the SBC-ll 121 module, pin identification and signal
names unique to the SBC-11/21 module, and standard LSI-ll bus backplane names assigned to each
pin. Although the signal names may differ, the module is completely LSI-ll bus compatible with the
exception of bus refresh transaction (BREF) which is not performed by the SBC-11/21. Signals STOP
L, SRUN L, and START L are not used on the LSI-II bus. These are TTL level signals unique to the
SBC-11/21.

1-4

Table 1-1
Backplane
Pin

SBC-H/21 Module Backplane Pin Identification
SBC-H/21
Signal Function

LSI-H Bus
Signal Name

Side 1 (Component Side)
AAI
ABI
ACI
ADI
AEI
AFI
AHI
AJI
AKI
All
AMI
ANI
API
ARI
ASI
ATI
AUI
AVI

Bus terminator
Bus terminator
Bus terminator
Bus terminator
STOPL
SRUNL
Not connected
GND
Not connected
GND
GND
BDMRL
BHALTL
Bus terminator
Not connected
GND
Not connected
+ 5 VB (battery)

BIRQ5 L
BIRQ6 L
BDAL16 L
BDAL17 L
SSPAREI
SSPARE2
SSPARE3
GND
MSPAREA
MSPAREA
GND
BDMRL
BHALTL
BREFL
+12B
GND
PSPAREI
+5B

BAI
BBI
BCl
BDI
BEl
BFl
BHl
BJI
BKI
BLI
BMI
BNI
BPI
BRI
BSI
BTl
BUI
BVI

BDCOKH
BPOKH
Bus terminator
Bus terminator
Bus terminator
Bus terminator
STARTL
GND
Not connected
Not connected
GND
BSACKL
Bus terminator
BEVNTL
Not connected
GND
Not connected
+5V

BDCOKH
BPOKH
SSPARE4
SSPARE5
SSPARE6
SSPARE7
SSPARE8

1-5

MSPAREB
MSPAREB
BSACKL
BIRQ7 L
BEVNTL
+12B
GND
PSPARE2
+5V

Table 1-1

SBC-ll/21 Module Backplane Pin Identification (Cont)

Backplane
Pin

SBC-ll/21
Signal Function

LSI-II Bus
Signal Name

AA2
AB2
AC2
AD2
AE2
AF2
AH2
Al2
AK2
AL2
AM2
AN2
AP2
AR2
AS2
AT2
AU2
AV2

+5V
Not connected
GND
+12V
BDOUTL
BRPLYL
BDINL
BSYNCL
BWTBTL
BIRQ4L
Not connected
BIAKOL
BBS7L
Not connected
BDMGOL
BINITL
BDALOL
BDALIL

+5V
-12 V
GND
+12 V
BDOUTL
BRPLYL
BDINL
BSYNCL
BWTBTL
BIRQ4 L
BIAKI L
BIAKOL
BBS7L
BDMGI L
BDMGOL
BINIT L
BDALOL
BDALIL

BA2
BB2
BC2
BD2
BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2

+5V
Not connected
GND
+12V
BDAL2L
BDAL3L
BDAL4L
BDAL5L
BDAL6L
BDAL7L
BDAL8L
BDAL9 L
BDALI0 L
BDALll L
BDAL12 L
BDAL13 L
BDAL14 L
BDAL15 L

+5V
-12 V
GND
+12V
·BDAL2L
BDAL3L
BDAL4L
BDAL5L
BDAL6 L
BDAL7 L
BDAL8L
BDAL9L
BDALI0 L
BDALll L
BDAL12 L
BDAL13 L
BDAL14 L
BDAL15 L

Side 2 (Solder Side)

1-6

1.4 RELATED DOCUMENTS
This User's Guide is the primary reference document for the SBC-llj21. Important information about
other LSI-II bus compatible products may be found in the publications listed in Table 1-2.
Table 1-2

Related Documentation

Title

Document Number

Microcomputers and Memories Handbook, 1982 Edition

EB-20912-20

Microcomputer Interfaces Handbook, 1980 Edition

EB-20175-20

PDP-II Bus Handbook, 1979 Edition

EB-17525-20

These documents can be ordered from:
Digital Equipment Corporation
Printing and Circulation Services
444 Whitney Street
Northboro, MA 01532
Attention:

Communications Services (NR2jMI5)
Customer Services Section

1-7

CHAPTER 2
INSTALLATION

2.1 INTRODUCTION
The installation of the SBe-11 /21 single-board computer module is discussed in this chapter. The following five items, which are an integral part of the installation procedure, are covered in detail.
NOTE
It is best to leave tbe factory configuration as is until
module performance has been verified.

Installing jumpers to select operational features.

Selecting and mounting an LSI-II bus-structured backplane and adding any required LSI-II
bus options.

Selecting and connecting an appropriate power supply.

Providing appropriate cables to connect external devices to the serial line and parallel I/O
interfaces.

Verifying operation of the module.

2.2 SELECTING OPERATIONAL FEATURES
The module has sixty-five wirewrap pins with which the user configures the module for the operating
modes necessary to meet any requirements. This is done by either installing or removing jumper wires
between the wirewrap pins. The locations and identification numbers of the wirewrap pins are illustrated in Figure 2-1. Table 2-1 defines the wirewrap pins, and Table 2-2 lists the pin functions by the
features they support. The selectable features are battery backup, power-up, starting address, interrupts, parallel I/O buffers, and memory maps. Detailed requirements for each of these configurations
are described in the following paragraphs. The standard factory configuration is described in Table 2-3.
2.2.1 Battery Backup
The user can select the battery backup mode to maintain a +5 Vdc battery supply to the 4Kb of static
RAM and, if needed, to the two 28-pin sockets that are defined as socket set A. The +5 Vdc battery
supply is provided through the LSI-ll bus via pin AV1. A maximum of 260 rnA is required. This supply is connected to wire wrap pin M16. To enable battery backup of 4Kb of static RAM, the jumper
wire between Ml and M15 is removed, and a jumper wire is installed between M16 and M15. To provide backup for socket set A, the jumper wire between M7 and M1 is removed, and a jumper wire is
installed between M 15 and M7.

2-1

M65

M54
M5o/ M53 M51

060e! ~M50
M52,..o

0-M49

E62

M2~fl:21

,....---P-R-O-G-R-A-M-M-A-BL-E....,.,~",.~g~~ ~1~
E60

XE59

PERIPHERAL
INTERFACE

M28g.gg M20
M27 ~~M19

SERIAL LINE UNIT M'f;i'
N02

XE58

SERIAL LINE UNIT
NO 1

XE57

MICROPROCESSOR

XE55
HIGH BYTE
SOCKET SET B

XE45
LOW BYTE
SOCKET SET B

XE54
XE44
M10
HIGH BYTE
LOW BYTE
M14 0 d.M9 M4
SOCKET SET A
SOCKET SET A M13 0 ~M8 /.'--------~ L - - - - - - - M 1 2 017 0 0 OM2
M4400M37
/08M11
ooM64
M63
M43 0 0 M36
M6/
~~~
~~~
~~~
M5
M600 0 M57
M40 001\1133
M 3 . Y1
M5900 M56
M39 00 M32
o M55
M3800M31
OM48
oM7
..._ _ _
E5_2_ _......
E19

Ig~*

~r---E-37----'1

C;r--E1-8----,

rL..-___-'

000
\ "M1
\ M15
M16

MA-7526

Figure 2-1

SBC-llj21 Module Layout

2-2

Table 2-1

Configuration Pin Definitions

Schematic
Sheet
Number

Description

Ml
M2
M3
M4
M5

1
I
3
3
3

System + 5 V power
Clock system input
System GND
Wake up circuit diode, anode side
Receive side of BHALT line transceiver

M6
M7
M8
M9
MIO

3
5
3
I
3

Wake up circuit diode, cathode side
Socket set A, pin 26, high and low byte
BHALT interrupt request input (edge sensitive)
Interrupt acknowledge ( - IAK) output
-CTMER interrupt request input (edge sensitive)

MIl
Ml2
M13
Ml4
M15

1
3
3
3
1

Clock oscillator output
High logic level ( + 3 Vdc)
- CTMER interrupt enable
Time-out error (TMER) output
+ 5 Vdc power distribution to support static RAM

M16
M17
Ml8
M19
M20

1
6
2
6
6

Battery backup +5 Vdc power source
Serial line unit (SLU) 1 BREAK detect, interrupt request output
High logic level ( + 3 Vdc)
60 Hz real-time clock output
Transmit side of BHALT line transceiver

M21
M22
M23
M24
M25

2
1
6
6
2

Memory map select (MSB)
Start address control (TDAL 15)
Transmit side of BEVNT line transceiver
System GND
Memory map select (LSB)

M26
M27
M28
M29
M30

1
6
6
1
1

Start address control (TDAL 14)
50 Hz real-time clock output
800 Hz real-time clock output
System GND
Start address control (TDAL 13)

M31
M32
M33
M34
M35

5
5
5
5
5

Read strobe (READ)
Socket set B, high and low byte, pin 20
Socket set B, high byte, pin 27
Socket set B, chip select, (-CSKTB)
Socket set B, low byte, pin 23

M36
M37
M38
M39
M40

5
5
5
5
5

Address line 13
Socket set A, low byte, pin 27
Socket set A, high and low byte, pin 20
Socket set A, high byte, pin 27
Socket set A, low byte, pin 23

2-3

Table 2-1

Configuration Pin Definitions (Cont)

Schematic
Sheet
Number

Description

M41
M42
M43
M44
M45

5
5
5
5
5

Socket set A, chip select, ( - CSKTA)
Socket set B, high and low byte, pin 2
Socket set A, high and low byte, pin 2
Address line 12
Address line 11

M46
M47
M48
M49
M50

5
5
5
7
2

High logic level for PROMs
Socket sets A and B, high and low byte, pin 21
Socket set B, low byte, pin 27
Port B buffer direction control
High logic level (+3 Vdc)

M51
M52
M53
M54
M55

7
7
7
7
5

System GND
Port A buffer direction control
Port C buffered output, to 13 pin 7
Port C PC6 output(8255A-5 pin 11)
System GND

M56
M57
M58
M59
M60

5
5
7
3
5

High byte write strobe (- WHB)
Low byte write strobe (- WLB)
Port C PC4 output (8255A-5 pin 13)
+ 5 Vdc voltage level
Socket set A, high and low byte, pin 22

M61
M62
M63
M64
M65

5
5
5
5
7

Socket set A, high byte, pin 23
Socket set B, high and low byte, pin 22
Socket set B, high byte, pin 23
Read strobe (-READ)
Port C buffered output, to 13 pin 5

2-4

Table 2-2

Function

Configuration Pin Functions

Description

Clock oscillator
Clock system input
Clock oscillator output

M2
MIl
Battery backup

System + 5 V power
+5 Vdc power distribution to support static RAM
Battery backup + 5 V power source
Socket set A, pin 26, high and low byte

MI
MI5
MI6
M7
Nonmaskable interrupt
and trap to the restart
address

-CTMER interrupt request input (edge sensitive)
Time-out error (TMER) output
- CTMER interrupt enable
Interrupt acknowledge ( - IAK) output
System GND
High logic level ( + 3 Vdc)

MIO
MI4
Ml3
M9
M3
MI2
Serial line unit (SLU) I

System GND
Transmit side of BHALT line transceiver
Serial line unit (SLU) I BREAK detect, interrupt request output

M24
M20
Ml7
Power-up

System + 5 V power, wake up circuit diode, cathode side
Wake up circuit diode, anode side

M6
M4
Serial line unit (SLU) 2

Transmit side of BEVNT line transceiver
50 Hz real-time clock output
60 Hz real-time clock output
800 Hz real-time clock output

M23
M27
Ml9
M28
Memory map decoder
MI8
M25
M2I
M29

High logic level ( + 3 Vdc)
Memory map select (LSB)
Memory map select (MSB)
System GND

2-5

Table 2-2
Pin

Function

Configuration Pin Functions (Cont)

Description

Start address
(mode register)
Start address control
Start address control
Start address control
High logic level (+3 Vdc)

M30
M26
M22
MI8
BHALT interrupt
(level 7, maskable)
M3
M5
M8

System GND
Receive side of BHALT line transceiver
BHALT interrupt request input (edge sensitive)
Memory

M45
M46
M61
M33
M48
M38
M63
M32
M62
M35
M40
M43
M42

Address line II
High logic level, for PROMs
Socket set A, high byte, pin 23
Socket set B, high byte, pin 27
Socket set B, low byte, pin 27
Socket set A, high and low byte, pin 20
Socket set B, high byte, pin 23
Socket set B, high and low byte, pin 20
Socket set B, high and low byte, pin 22
Socket set B, low byte, pin 23
Socket set A, low byte, pin 23
Socket set A, high and low byte, pin 2
Socket set B, high and low byte, pin 2

M36
M34
M37
M39
M44
M55
M64
M31
M57
M56
M41
M60
M47
M59

Address line 13
Socket set B, chip select, (-CSKTB)
Socket set A, low byte, pin 27
Socket set A, high byte, pin 27
Address line 12
System GND
Read strobe (-READ)
Read strobe (READ)
Low byte write strobe (- WLB)
High byte write strobe (- WHB)
Socket set A, chip select, (- CSKTA)
Socket set A, high and low byte, pin 22
Socket sets A and B, high and low byte, pin 21
+ 5 V dc voltage level

2-6

Table 2-2 Configuration Pin Functions (Cont)
Pin

Function

Description

Parallel input/output
M49
M51
M65
M53
M58
M54
M50
M52

Port B buffer direction control
System GND
Port C buffered output, to 13 pin 5
Port C buffered output, to 13 pin 7
Port C PC4 output (8255A-5 pin 13)
Port C PC6 output (8255A-5 pin II)
High logic level ( + 3 V dc)
Port A buffer direction control

Table 2-3 Standard Factory Configuration

Function

Jumpers
Installed
Between

Standard LSI-II bus power
(No battery backup)

MI and MI5
MI andM7

Wake up circuit enabled

No jumpers

System clock

M2and Mll

Start address*
Start address 10000
Restart address 10004

M30 and M26
M26 andM29
M22 and MI8

Memories:
Memory map 0

M25 and M21
M21 and M29

2K X 8 INTEL EPROM

M61 and M40
M59 and M61
M41 and M38
M45 and M47
M63 and M35
M59 and M63
M60and M62
M34and M32
M64 and M62

2-7

Table 2-3 Standard Factory Configuration (Cont)
Jumpers
Installed
Between

Function
Interrupts:
Time-out traps to restart address
except during LSI-II bus IAK

M9 and M13
MI4 and MIO

SLUI BREAK asserts BHALT and it
is received as level 7 interrupt
(vector 140)

M20 and MI7
M5 and M8

SLU2 60 Hz real-time clock
asserts LSI-II BEVNT

MI9 and M23

Parallel I/O in mode I:
Port A receive data, with STROBE A
onPC4
Port B transmit data

M49 and M5I
M50 and M52
M65 and M58

No connection to pins:
M3,M4,M6,MI2,MI6,M24,M27,M28,M3I,M33,M36,M37,M39,M42,M43,M44,M46,M48,
M53, M54, M55, M56, M57
*Before use with Macro-ODT, the start address must be changed to 172000 as described in Table 2-4.

2.2.2 Wake Up Circuit
The module has an on-board power wake up circuit designed for use in systems without the LSI-II bus
power sequencing protocol. This circuit holds the BDCOK line negated until one second after + 5 V
power is applied. When the module is used in an LSI-II backplane that has a power sequencing routine,
the module wake up circuit must be disabled. To do this, a jumper wire is installed between M6 and
M4. The jumper wire is removed when using power supplies without power sequencing. The module
requires the +5 Vdc and + 12 Vdc power supplies to have a rise time of less than 50 ms.
2.2.3 Starting Address
The user selects the starting address for the microprocessor via wirewrap pins. When the module is
powered up, the microprocessor loads this value into R7 (program counter) as the first fetch address.
The wirewrap pins are M22, M26, M29, M30, and MI8, and are defined in Table 2-1. The user can
select from eight available starting addresses. Table 2-4 lists these available addresses and the jumper
connections required for each address. The restart address is always the start address incremented by
four. The wirewrap pin locations are shown in Figure 2-1.
.
2.2.4 Interrupts
The SBC-II/2I implements a multilevel interrupt system that has eleven separate interrupts. See
Table 5-3 for a complete list of sy~tem interrupts. Three interrupts, CTMER, BKRQ, and REVNT, are
user configurable by means of jumper wires as shown in Figure 2-2 and are discussed here.

2-8

Table 2-4

Mode Register Configuration

Start
Address

Restart
Address

Connect
M22to

Connect
M26to

Connect
M30to

000000
010000*
020000
040000
100000
140000
172000
173000

000004
010004
020004
040004
100004
140004
172004
173004

M18
M18
M29
M29
M29
M29
MI8
MI8

M29
M29
M18
MI8
M29
M29
M18
MI8

M18
M29
M18
M29
M18
M29
M18
M29

*Factory setting. The start address should be selected in conjunction with the memory map configuration. Figure 2-6 shows
how the available start addresses fit into the memory maps.

The CTMER interrupt is at the highest level (nonmaskable). It is caused by a time-out, that is, a failure
to detect RRPL Y during a fetch/read, write, or IAK transaction. For the factory configuration, - IAK
is connected to the D input of flip-flop E7 via M9 to M13 jumper. This prevents setting that flip-flop
and inhibits CTMER for time-outs occurring during IAK transactions. Such a condition could occur
only if the peripheral that caused the interrupt failed to return BRPLY during the vector reading operation. See Chapter 8 for a discussion of external interrupts. To help the user evaluate the advantages
and disadvantages of this jumper option, Figure 2-3 describes the sequence of events that takes place
during the IAK time-out.
A time-out during IAK causes a zero vector to be read in by the microprocessor. This occurs in both
examples described in Figure 2-3. If CTMER is allowed to set, this causes the second stacking of PC
and PSW followed by a jump to restart.
The other two interrupts the user can select are BKRQ and REVNT. Their vectors and priorities are
described in Table 5-3. All jumper combinations, which are "electrically correct" as described in Figure 2-2, are legal.
A description of some typical configurations follows to familiarize the user with the different combinations available.
Install jumpers 1?etween

MI4 and M8
M13 and M12
MIO and M17
M24 and M20
M23 and M28

This arrangement allows the SLUI BREAK input to set the -CTMER nonmaskable interrupt and
trap to the restart address. The time-out (TMER) input sets the BKRQ level 7 maskable interrupt. The
BHAL T L bus signal is ignored. The SLU2 800 Hz line time clock and the BEVNT L bus signal enable
the REVNT interrupt.

2-9

+3VDC-A

M12

GND

M36

-IAK M9
M13
~---------

ONE SHOT
RRPLY L

TDOUT H
TDIN H

D
E7

TMERM14

M10

--- ------

E32
CAS

-CTMER

INTERRUPT
NONMASKABLE

E29

E9
C

RESET

-BCLR

+3 VDC
RRPLY L

E17
M5

SLUl
M17
M20 THALT
BREAK - - 0 - - -M24
GND--C

--------

BHALT L

M27

LTC

RESE~

-BCLR

50HZ - - 0

SLU'{

INTERRUPT
LEVEL
MASKABLE

+3VDC

BEVNT L

M19

E32
CAS

BKRQ

E10
M23 TEVNT

60HZ --4:]- - - M28
800HZ - - C

REVENT
E27

CAS

INTERRUPT
LEVEL 6

RESET
MR"7515

Figure 2-2

Interrupt Configurations

LSI-ll BUS INTERRUPT
(BIRQ4)

PROCESSOR RETURNS IAK

M13 CONNECTED TO M9 (-IAK)

,,
,

M13 CONNECTED TO M12 (+3 VDC)

,
~

TIME-OUT DURING IAK

NO CTMER

CTMER SET

PC AND PSW PUSHED ON THE STACK
PC AND PSW LOADED FROM VECTOR AND VECTOR +2
(VECTOR IS 0 BECAUSE NOTHING IS DRIVING TDAL)

JUMP TO NEW PC

NEW PC AND PSW PUSHED AGAIN
RESTART ADDRESS-PC
340
-+PSW

JUMP TO NEW PC
MR-7516

Figure 2-3

Time-out During LSI-II Bus Interrupt Acknowledge

Install jumpers between

MIa and M5
MI7 and M8
M13 and MI2
M20 and M24
M23 and M24

This arrangement allows the BHALT L bus signal to set the -CTMER nonmaskable interrupt and
trap to the restart address. The SLUI BREAK input sets the BKRQ level 7 maskable interrupt, and
only the BEVNT L bus signal enables the REVNT interrupt.
Install jumpers between

MI4 and MIa
MI3 and MI2
MI7 and M20
M5 and M8
M23 and MI2

This arrangement allows the time-out (TMER) to set the -CTMER nonmaskable interrupt for all
time-outs. The SLUI BREAK or the BHALT bus signal set the BKRQ level 7 maskable interrupt, and
the BEVNT L bus line is clamped low and therefore, no interrupts can be generated by BEVNT L.

2.2.5 Parallel I/O
The parallel I/O is implemented with the 8255A-5 programmable peripheral interface (PPI) and connects to the user's interface through the 13 connector. Figure 2-4 illustrates the wirewrap pins used for
the configuration of the parallel I/O. (These pins are defined in Table 2-1.) The dash lines in Figure 2-4
represent the factory configuration jumpers installed. (The wirewrap pin locations are shown in Figure
2-1.) The directions of port A and port B transceivers are dependent on the logic level connected to
M49 and M52. Wirewrap pin 52 connects to port A through a 200 ns minimum rise time edge delay
circuit. When M50 (+3 Vdc) is jumpered to pins M49 and M52, port A and port B buffers are inputs
to the PPI from the 13 connector. When M5I (GND) is jumpered to pins M49 and M52, port A and
port B buffers are outputs from the PPI to the 13 connector.
2-11

pca
PC3 }

INTERRUPTS

pca

~---;---------;

~r---------;

PCl
PC2

~--~--------~ 4
PC3
~=---~------~--~ ~~--~-----; 10
M65
PORT C
PC4 M58

PC5

PC6

PC7

8
LED

M5l
M49
GN D --0- -

-o-------------...J
PORT A BUS
TRANSCEIVERS

C12
MR-7514

Figure 2~4

Parallel I/O Configuration

The direction of port A and port B can also be controlled by a user's program. To make this possible,
M58 and M54 must be jumpered to M49 and M52. The data outputs via port C will control the voltage
levels at the direction control inputs to ports A and B. The software required to do this control is discussed in Chapter 6.
Wirewrap pins M65 and M53 can be jumpered to M49 and M52 to allow the user to control the direction of the transceivers via 13 connector pins 5 and 7. When not using wire wrap pins M58 and M65 or
M54 and M53 to control the direction of ports A and B, jumpers connected between M58 and M65 and
between M54 and M53 allow PC4 and PC6 to be used as inputs to the PPI from the 13 connector.

NOTE
If pins M65, M53, M58, or M54 are used for program control of port A or B, the user must ensure
that the PPI and the buffer do not contend as driver
output to driver output. If this condition is allowed
to occur, damage to both drivers may result.

The programmable peripheral interface can function in three modes selected by software. The jumper
configurations and the handshake signals for each of these modes are shown in Table 2-5, Table 2-6,
and Table 2-7. See Chapter 6 for programming information.
2.2.6 Serial I/O
The jumper options relating to the serial I/O determine the interrupt response of the system and were
explained in Paragraph 2.2.4. All responses to the BREAK detection by SLUI are listed in Table 2-8.
2-12

Table 2-5

Mode 0 Buffer Configuration (No Handshake)

PPI
Element

To Act
as Input

To Act
as Output

Program Control
via Port C

PortA

M52 to M50

M52 to M51

M52 to M54 or M58

Port B

M49 to M50

M49 to M51

M49 to M54 or M58

PC7

Never an input

Always an output

PC6

M54 to M53

Never an external
output

PC5

Never an input

Always an output

PC4

M58 to M65

N ever an external
output

PC3

Never an input

Interrupt A
(vector 134)
Always an output

PC2

Always an input

Never an output

PC1

Never an input

Always an output

PCO

Never an input

Interrupt B
(vector 130)
Always an output

2-13

Table 2-6 Mode 1 Buffer Configuration (Strobed I/O)

PPI
Element

To Act
as Input

To Act
as Output

Program Control
via Port C

PortA

M52 to M50

M52 to M51

NjA

Port B

M49 to M50

M49 to M51

M49 to M54 or M58

PC7

Never an input

Indicates
buffer A full

PC6

M54 to M53
(Acknowledge A)*

Never an
external output

PC5

Never an input

Indicates
buffer A full

PC4

M58 to M65
(Strobe A)

Never an
external output

PC3

Never an input

Interrupt A

PC2

Strobe B
in input mode
Acknowledge B in
output mode

Never an output

PCI

Never an input

Buffer B full
on input or output

PCO

Never an input

Interrupt B
(vector 130)

·User's hardware acknowledges receipt of data output by port A.

2-14

Table 2-7 Mode 2 Buffer Configuration and Handshake
PPI Element

Input Signal

Output Signal

PortA

Bidirectional bus

If M52 to M54 to M53

Port B

Not used in mode 2

PC7

Never an input

Output buffer A full

PC6

Acknowledge A

Never an output

PC5

Never an input

Input buffer A full

PC4

Strobe A (if M65 to M58)

Never an output

PC3

Never an input

Interrupt A

PC2

Always an input

Never an output

PCI

Never an input

Always an output

PCO

Never an input

Always an output

Table 2-8 SLUt BREAK Detection
Jumper Connection*

BREAK Response

M17 to M20
M5 toM8

BHALT L signal to the LSI-II bus
and BKRQ interrupt (vector 140)

M20 to M24
M5 toM8

No response

M8 to Ml7
M20toM24

BKRQ interrupt (vector 140)
(no BHALT L to bus)

MIO to M17
M20toM24
M13 to M12

CTMER interrupt
(HALT trap) through restart

*Refer to Figure 2-2.

2-15

2.2.7 Memories
The memory system for the module is the LSI-II bus, 4Kb of local RAM, and four 28-pin sockets that
accept either 24-pin or 28-pin industry standard + 5 V memory chips. These chips are provided by the
user and can be either EPROMs, PROMs, ROMs, or static RAMs. The sockets will accept lK X 8,
2K X 8, 4K X 8, and 8K X 8 PROMs/EPROMs, or 2K X 8, 4K X 8, and 8K X 8 static RAMs.
There are two socket sets: set A which is controlled by - CSKTA and set B which is controlled by
- CSKTB. Each set has a high byte socket and a low byte socket that are interconnected as shown in
Figure 2-5. The wirewrap pins used to configure the memory are shown in Figure 2-6 and described in
Table 2-1. The standard factory configuration of the installed jumper wires is represented by the dash
lines in Figure 2-6. In addition to configuring the sockets, the user must configure the decode memory
address chip to select one of the four memory maps available.
NOTE
The SBC-H/2l contains semiconductor devices
that may be susceptible to damage by electrostatic
charges. When handling the board and configuring
the wirewrap pins, the board should be kept on a
grounded conductive plane. Also, wrist straps in contact with the skin should be used to keep the operator at the same ground potential.
2.2.7.1 Memory Maps - Figure 2-7 shows the four memory maps available. The module can be configured to select the one that meets the user's requirements. Wirewrap pins M18, M21, M29, and M25
are used to select the memory map. The jumper requirements are listed in Table 2-9.
2.2.7.2 PROMs/EPROMs - The 28-pin sockets accept 24-pin and 28-pin PROMs or EPROMs. If 24pin chips are selected, caution must be observed to ensure that pin 1 of the chip is placed into socket
hole 3. The configuration requirements of some industry compatible PROMs/EPROMs are described
in Table 2-10 and Table 2-11. The user may select chips from other vendors, however, the pin configuration must be compatible with the sockets provided. A 250 ns maximum output enable time is also
required, and the maximum access time for compatible PROMs/EPROMs is 450 ns. The maximum
output enable time is defined as the time from the assertion of TDIN or TDOUT by a bus master to the
time the module asserts valid data onto the bus.
The user installs a jumper wire from the pin referenced by the chip type to the socket pin described in
the tables. Figure 2-6 provides a reference for all signals and the socket pins associated with the wirewrap pins. These interconnections are listed separately under socket set A and socket set B, and some
jumper wires are common to both socket sets. Some devices may not require a connection or installation
of a jumper wire and are designated by an 'NC' in the tables. The wirewrap pin locations are shown in
Figure 2-1.
2.2.7.3 RAMs - The 28-pin sockets can also accept 24-pin static RAM chips, and caution must be
observed to ensure that pin 1 of the chip is installed into socket hole 3. The configuration requirements
of some industry compatible RAMs are described in Table 2-12 and Table 2-13. The user may select
chips from other vendors, however, the pin configuration must be compatible with the sockets provided.
The selected RAMs are required to meet the maximum output enable time and the maximum access
time specified for the PROMs.
The user installs a jumper wire from the pin referenced by the chip type to the socket pin described in
the tables. Figure 2-6 provides a reference for all signals and the socket pins associated with the wirewrap pins. These interconnections are listed separately under socket set A and socket set B, and some
jumper wires are common to both socket sets. Some devices may not require a connection or installation
of a jumper wire and are designated by an 'NC' in the tables. The wirewrap pin locations are shown in
Figure 2-1.
2-16

M43

M41
-CSKTA

-0
M34

-CSKTB

AD8
AD7

-a

AD6

M45

AD5

AD11

-0

AD12

-a

AD3

M36

AD2

M44

AD13 - 0

AD4

M56
-WHB - - [ ]

AD1
TDAL8

M57

TDAL9

-a
M64
-READ -a
M31
READ -a
-WLB

+5 V

TDAL10
GND

6
7
8
9

28 PIN
SOCKET SET A
HIGH BYTE
XE54

+5 V

M42

M39
M7
AD8
AD9

AD7

AD10

AD6
AD5

M61

AD4

M60

AD3
AD2

TDAL15

M38

AD1

TDAL14

TDAL8

TDAL13

TDAL9

TDAL12

TDAL10

TDAL11

+5 V

GND

6
7
8

28 PIN
SOCKET SET B
HIGH BYTE

XE55

+5 V
M33

+5 V
AD9
AD10
M63

M62

TDAL12

TDAL11

TDAL15

M32

TDAL14
TDAL13

M47

M46
+3VDC
tv

I
I--'

-.l

--0

M59
+5 VDC --[J
M55
GND --[J

+5 V

AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
TDALO
TDAL1
TDAL2
GND

+5 V

AD9

AD10

23
22

28 PIN
SOCKET SET A
LOW BYTE

XE44

o M37
AD8

M40

AD7
AD6
AD5
AD4

+5 V

AD3
AD2
TDAL7

AD1

TDAL6

TDALO

TDAL5

TDAL1

TDAL4
TDAL3

TDAL2
GND

6
8

28 PIN
SOCKET SET B
LOW BYTE

XE45

+5 V
M48

+5 V
AD9
AD10
M35

22
21
20

TDAL7
TDAL6
TDAL5
TDAL4
TDAL3
MR-7509

Figure 2-5

Socket Sets A and B Interconnection

PIN 21 HIGH BYTE SET A

AD11

M45 .

~------

AD12 ~
M59
+5 V NCR -=:::..0- -

+3VDC

M61

- - - - r - - D - - - PIN 23 HIGH BYTE SET A

~
-WLB ~
~

PIN21 HIGH BYTE SET B
PIN 21 LOW BYTE SET B

-WHB

AD13

~47 PIN 21 LOW BYTE SET A

~_-<lf-M_4.;...0_ _ PIN 23 LOW BYTE SET A
~ - -DI-M_6_3_ _ PIN 23 HIGH BYTE SET B

_3
_5_ _ PIN 23 LOW BYTE SET B
L_-CI-M
~ PIN 2 HIGH BYTE SET A

~ PIN 2 LOW BYTE SET A
~ PIN 2 HIGH BYTE SET B

~ PIN 2 LOW BYTE SET B

M31
READ~

C M39
C M37

PIN 27 HIGH BYTE SET A

C M33

PIN 27 HIGH BYTE SET B

C M4B

PIN 27 LOW BYTE SET B

PIN 27 LOW BYTE SET A

-READ ~ _ _ _ _ _ _ ~PIN22HIGHBYTESETA

GND ~

PIN 22 LOW BYTE SET A

L_~PIN22 HIGH BYTESETB

~PIN 22 LOW BYTE SET B
-CSKTA

~ _______ ~PIN 20 HIGH BYTE SET A

....
-CSKTB

L - PIN 20 LOW BYTE SET A

~ _ _ _ _ _ _ _ ~ PIN 20 HIGH BYTE SET B

~ PIN 20 LOW BYTE SET B
~ PIN 26 HIGH BYTE SET A

~ PIN 26 LOW BYTE SET A

+3V~
GND~

, ... ...

M25~----------~

M21

DECODE
MEMORY
ADDRESS

NOTE:
M7 IS USED TO PROVIDE BATTERY
BACKUP POWER TO SOCKET SET A
WHEN THIS OPTION IS INCORPORATED.
MR-7513

Figure 2-6

Memory Configuration

2-18

MAPO
(177776)
(173000)
(172000)
(170000)

64KB

56KB

(NOTE 3)
2KB(NOTE 1)
4KB LOCAL RAM
(NOTE 2)

(160000)

4BKB

MAPl

MAP3

MAP2
64KB

64KB

(NOTE 3)

4KB LOCAL RAM
(NOTE 2)

56KB

4BKB

48KB

(140000)
LSI-ll BUS

LSI-ll BUS

40KBI-

40KB,.

40KB

32KB

24KBI-

24KB

16KBi-

16KB

(120000)

(100000)

(60000)

16KB SOCKET A

(40000)
BKB SOCKET A

(20000)

BKBi-

BKB

8KB

(10000)
(NOTE4)

8KB

16KB SOCKET B

4KB SOCKET A
BKB SOCKET B
4KB SOCKET B
OKB

OKB

NOTES:
1. SOCKET SET A IS MAPPE DOVE R SOCKET SET B AN D IS
THEREFORE LIMITED TO USING EITHER SOCKET A OR
SOCKET B, BUT NOT BOTH TOGETHER.
2. ADDRESSES 160000 THROUGH 160007 ARE ASSUMED TO
RESIDE ON THE LSI-ll BUS.
3. THIS SECTION CONTAINS THE LOCAL I/O ADDRESSES FOR
THE SLUs AND PPI. ALL UNASSIGNED ADDRESSES ARE
ASSUMED TO RESIDE ON THE LSI-11 BUS.
4. UNDERLINED ADDRESSES ARE JUMPER-SELECTABLE START
ADDRESSES, ACCORDING TOTABLE 2-4.
MA-7243

Figure 2-7

Memory Maps

2-19

Table 2-9 Memory Map Configurations
Map Selection

Jumper M25 to

Jumper M21 to

Map 0
Map 1
Map 2
Map 3

M21
M18
M29
M21

M29
M29
M18
M18

Table 2-10 Socket Set A Configuration for EPROM/PROM

Parts

Pins

Size

Connect Referenced
Pin to Socket A Pin
M40 M37 M43 M61 M60 M38 M39 M47

INTEL

2758

lK X 8

M59 NC

M59 M64 M41 NC

M55

INTEL

2716
2716-1
2716-2

24
24
24

2K X 8
2K X 8
2K X 8

M59 NC

M59 M64 M41 NC

M45

INTEL

2732
2732A

24
24

4K X 8
4K X 8

M44 NC

M44 M64 M41 NC

M45

INTEL

2764

8K X 8

M44 M46 M36 M44 M64 M41 M46 M45

TMS2508

lK X 8

M59 NC

M59 M64 M41 NC

M46

TMS2516
24
TMS2516-35 24

2K X 8
2K X 8

M59 NC

M59 M64 M41 NC

M45

TMS2564

8K X 8

M36 M55 M64 M36 M41 M44 M55 M45

Mostek

MK2716

2K X 8

M59 NC

M59 M64 M41 NC

M45

Mostek

MK2764

8K X 8

M44 NC

M36 M44 M64 M41 NC

M45

INTEL

3628

lK X 8

M41 NC

M41 M64 M46 NC

M46

Signetics

82LS181

lK X 8

M41 NC

M41 M64 M46 NC

M46

Vendor
EPROMs

PROMs

NC - requires no connection.

2-20

Table 2-11

Socket Set B Configuration for EPROM/PROM

Parts

Pins

Size

Connect Referenced Pin
to Socket B Pin
M35 M48 M42 M63 M62 M32 M33 M47

INTEL

2758

lK X 8

M59 NC

M59 M64 M34 NC

M55

INTEL

2716
2716-1
2716-2

24
24
24

2K X 8
2K X 8
2K X 8

M59 NC

M59 M64 M34 NC

M45

INTEL

2732
2732A

24
24

4K X 8
4K X 8

M44 NC

M44 M64 M34 NC

M45

INTEL

2764

8K X 8

M44 M46 M36 M44 M64 M34 M46 M45

TMS2508

lK X 8

M59 NC

M59 M64 M34 NC

M46

TMS2516
TMS2516-35

24
24

2K X 8
2K X 8

M59 NC

M59 M64 M34 NC

M45

TMS2564

8K X 8

M36 M55 M64 M36 M34 M44 M55 M45

Mostek

MK2716

2K X 8

M59 NC

M59 M64 M34 NC

M45

Mostek

MK2764

8K X 8

M44 NC

M36 M44 M64 M34 NC

M45

INTEL

3628

lK X 8

M34 NC

M34 M64 M46 NC

M46

Signetics

82LS181

lK X 8

M34 NC

M34 M64 M46 NC

M46

Vendor
EPROMs

PROMs

NC - requires no connection.

2-21

Table 2-12 Socket Set A Configuration for RAM

Vendor

Parts

Pins

Size

Connect Referenced Pin
to Socket A Pin
M40M37 M43 M61 M60 M38 M39 M47

Mostek

MK4802

2K X 8

M57 NC

M56 M64 M41 NC

Toshiba

TMM2016P 24
TMM2016P-l 24

2K X 8
2K X 8

M57 NC

M56 M64 M41 M54 M45

Hitachi

HM6116P

2K X 8

M57 NC

M56 M64 M41 M54 M45

M45

NC - requires no connection.

Table 2-13 Socket Set B Configuration for RAM

Vendor

Parts

Pins

Size

Connect Referenced Pin
to Socket B Pin
M35 M48 M42 M63 M62 M32 M33 M47

Mostek

MK4802

2K X 8

M57 NC

M56 M64 M34 NC

M45

Toshiba

TMM2016P 24
TMM2016P-l 24

2K X 8
2K X 8

M57 NC

M56 M64 M34 NC

M45

Hitachi

HM6116P

2K X 8

M57 NC

M56 M64 M34 NC

M45

NC - requires no connection.

2.3 SELECTING BACKPLANES AND OPTIONS
A number of different LSI-II bus compatible backplanes and boxes are available from Digital. The
choice is defined by system requirements such as the number and type of options (described in Chapter
3), environment conditions, and packaging considerations. A list of all available backplanes and boxes is
provided in the Microcomputer Interfaces Handbook.
2.4 POWER SUPPLY
The choice of power supply is controlled by the size of the system and packaging requirements. An
important consideration is the performance of the supply during power-up and power-down. All Digital
power supplies listed in the Microcomputer Interfaces Handbook are compatible with the LSI-II bus
protocol which allows dependable operation with no loss of data when using battery backed-up memories. Any user-designed power supply must agree with the LSI-ll bus protocol.
2.5 EXTERNAL CABLES
The module has a 30-pin connector (13) for an external interface with the programmable I/O interface
and two 10-pin connectors (11 and 12) for the external interface of the serial line units (SLUs). The
location of these connectors on the module is shown in Figure 2-1. The requirements to interface with
these connectors are defined in the following paragraphs.
2-22

2.5.1 Parallel I/O Interface (J3)
The module connector is a 30-pin AMP MOOU connector with the I/O signals defined by Figure 2-8.
The I/0 signals are buffered and are capable of driving up to 50 feet (maximum) of flat ribbon or
round cable with a 30-pin AMP contact housing at each end. The following list of connectors is compatible with the module connector.
AMP MOOU polarized or non polarized contact housings for crimp snap-in pin and receptacle contacts:
Latching, polarized
housings:

2-87631-6 no strain relief
87733-6 strain relief

Nonlatching, polarized
housings:

1-87977-3 no strain relief
1-102184-3 strain relief

Nonlatching, nonpolarized
housings:

2-87456-6 no strain relief
2-87832-7 strain relief

Receptacle contacts:

87045-3 for 30 to 26 A WG
102098-3 for 32 to 27 AWG

Mass termination connectors for flat cables:
Separate parts:
(nonpolarized)

1-88378-1 connector
1-86873-2 cover
1-88340-1 strain relief cover

Separate parts:
(polarized)

1-88392-1 connector
1-86373-2 cover
1-88340-1 strain relief cover

Connector and cover kits:
(nonpolarized)

1-88379-1 no strain relief
1-88476-1 with strain relief

Connector and cover kits:
(polarized)

1-88393-1 no strain relief
1-88478-1 with strain relief

Separate parts:

1-88392-1 connector
1-86873-2 cover
1-88340-1 strain relief cover

Latching connectors and covers:
(polarized)

1-88423-1 no strain relief
1-88479-1 with strain relief

Mass modular connector system:

1-102393-3 housing for 30-26 AWG
1-102396-3 cover
1-102392-3 kit
1-102398-3 housing for 26-22 AWG
1-102396-3 cover
1-102397-3 kit

Connectors can be terminated to discrete wire in sizes 30-26 AWG, 26-24 AWG, as well as jacketed
cable and bonded ribbon cable.
2-23

PPI INTERFACE
CONNECTOR J3
PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PBl
PA7
PA6
PA5
PA4
PA3
PA2
PAl
PAO

9
3
4
10
5
6
7
8
12
14
18
20
19
17
13
11
28
26
24
22
21
23
25
27

r--- LOOPBACK
TEST CONNECTORS
9
JUMPER WIRES
3
(USED ONLY WHEN PORT A BUFFERS
4
ARE CONFIGURED AS INP UTS AND
10 PORT B BUFFERS ARE CO NFIGURED
5
AS OUTPUTS)
6
7
8
12
14
18
20
19
17
13 ~
11
28
26 ~
24
22
21
23
25
27

GND

1
2
15
16
29
30

.,..

VIEW INTO THE CONNECTOR FROM THE MODULE EDGE
29

2 1 19

GND PAO PAl PA2 PA3 PB4 PB5 GND PB6 PB7 PCO PC6 PC4 PCl GND
GND PA7 PA6 PA5 PA4 PB3 PB2 GND PBl PBO PC3 PC7 PC5 PC2 GND
30

PC
BOARD

MR-6671

Figure 2-8

30-Pin Parallel I/O Connector

2-24

2.5.2 Serial Line Interfaces (Jl and J2)
Each serial line unit (SLU) is compatible with EIA RS-232C and EIA RS-423 serial type interfaces.
SLUI interfaces through Jl, and SLU2 interfaces through J2. When a 20 rnA current loop device is
needed, the DLVll-KA option must be used. The option has an EIA cable (BC2lA-03) that connects
the converter box to the module. The box has an 8-pin Mate-N-Lok™ connector that mates with the
standard 20 rnA cable. The option does not support the reader run strobe and the 110 baud rate and
therefore, the LA-33 or similar devices cannot be used.
The user installs a slew rate resistor determined by the operating baud rate defined in Table 2-14. The
slew rate resistor is identified as R6 and its location on the module is shown in Figure 1-1.
The SLU connectors showing the signals assigned to the connector pins are illustrated in Figure 2-9.
The user provides the interconnecting cables. The following list describes some standard Digital cables
and also provides some information to help the user design cables.
Digital cables for the SBC-11/21:
BC20N-05

5-foot EIA RS-232C null modem cable to directly interface with the EIA RS-232C terminal (2 X 5 pin AMP female to RS-232C female; see Figure 2-10).

BC2lB-05

5-foot EIA RS-232C modem cable to interface with modems and acoustic couplers (2
X 5 pin AMP female to RS-232C male; see Figure 2-11).

BC20M-50

50-foot EIA RS-422 or RS-423 cable for high throughput transmission (19.2K baud)
between two SBC-11/21 computers (2 X 5 pin AMP female to 2 X 5 pin AMP female).

When designing a cable for the SBC-11/21, the user should consider the following points:
1.

The receivers on the SBC-11/21 have differential inputs. Therefore, when designing an RS232C or RS-423 cable, RECEIVE DATA- (pin 7 on the 2 X 5 pin AMP connector) must
be tied to signal ground (pins 2, 5, or 9) in order to maintain correct EIA levels. RS-422 uses
both RECEIVE DATA+ and RECEIVE DATA-.

To directly connect to a local EIA RS-232C terminal, it is necessary to use a null modem. To
design the null modem into the cable, a user must switch RECEIVE DATA (pin 2) with
TRANSMITTED DATA (pin 3) on the RS-232C male connector as shown in Figure 2-10.

To mate to the 2 X 5 pin connector block, the following parts are needed.
Cable receptacle

AMP PN 87133-5
DEC PN 12-14268-02

Locking clip contacts

AMP PN 87124-1
DEC PN 12-14267-00

Key pin (pin 6)

AMP PN 87179-1
DEC PN 12-15418-00

''''Mate-N-Lok is a trademark of AMP, Inc.

2-25

Table 2-14

EIA Slew Rate Resistor Values

Baud Rate

Resistor R6 (ohms)

38,400
19,200
9,600
4,800
2,400
1,200
600
300

22kQ*
51 kQ
120 kQ
200kO
430kQ
820kQ
1 MO
1 MQ

*Factory installed value.

SLU
CONNECTOR
LOOPBACK
TEST CONNECTOR
JUMPER WIRES

BAUD RATE
CLOCK OUTPUT
(16 X BAUD)
TRANSMIT DATA +

INDEXING KEY

RECEIVE DATA +

RECEIVE DATA-

+12 VDC FUSED

10
2

GND

-=-

5
9

VIEW INTO THE CONNECTOR FROM THE MODULE EDGE

•

PC BOARD

INDEX (NO PIN)
MR-6669

Figure 2-9

lO-Pin Serial Line Unit Connector

2-26

SBC-11/21

EIA RS-232C

,-,

RCVDATA+)8

2(XMTDATA

XMTDATA+)~~---------I~'---------rI~I----------~(RCVDATA
:
I I

RCV DATA-~
GRD)-LJ

GRD)~2~--------+I~--------~----------~7(GRD

'.'

SHIELD
IMPORTANT:
ATTACH TO CHASSIS
AT ENTRY POINT
MR-6672

Figure 2-10

SBC-11/21

BC20N-05 Null Modem Cable

EIA RS-232C

r-- ( 5 ~ - • CLEAR TO SEND (CB)
I

GRD) 9 '-

RCV DATA) 7 '-

75.0.1/2 W

~10 ,'-

J REQUEST TO SEND (CA)

6 ( - -, DATA SET READY (CC)

+12 VDC

RCV DATA) 8

4 ~-

20~--'DATA TERMINAL READY (CD)

"
, 3 (RECEIVED DATA (BB)

...,

XMITDATA+)3 ,

, 2 <TRANSMITTED DATA (BA)
J

GRD) 2 ,

---

CABLE
'--CONNECTOR

7<SIGNALGROUND (AB)

, 1 <PROTECTIVE GROUND (AA)
MODEM

MR-6673

Figure 2-11

BC21B-05 Modem Cable

2-27

2.6 VERIFYING OPERATION
The SBC-ll/21 single-board computer can be field tested to verify its functional operation. The
Macro-ODT option and the loopback connectors support the testing of the module.
2.6.1 Macro-ODT Option
The Macro-ODT option (part # KXTll-A2) has two 24-pin, 2K X 8 PROM chips that contain the
Macro-ODT code and module diagnostic programs. The Macro-ODT code is used to create communication between the module and the user via console commands. The use of ODT commands is detailed in Chapter 4. The module diagnostic programs verify that the parallel I/O and serial line unit
interfaces will function with commands from the microprocessor.
2.6.2 Loopback Connectors
The loop back connectors can be made by the user for the module diagnostic tests. The 30-pin connector
with the loopback jumper wires installed (shown in Figure 2-8) is used with the parallel I/O connector
13. The serial line unit connector with the loopback jumper wires installed (shown in Figure 2-9) is used
with the SLU2 connector 12.
2.6.3 Verification Procedure
The module must be restored to the standard factory configuration for the test to be valid, however, the
start address must be 172000 not 10000. The module can be verified using the following procedure.
1.

Set the start address to 172000 as shown in Table 2-4.

Insert the high byte ODT ROM into socket set A, high byte socket E54. Make sure pin 1 is
inserted into socket hole 3.

Insert the low byte ODT ROM into socket set A, low byte socket E44. Make sure pin 1 is
inserted into socket hole 3.

Insert the 30-pin loopback connector (see Paragraph 2.6.2) into the module parallel I/O connector 13.

Insert the 10-pin loopback connector (see Paragraph 2.6.2) into the SLU2 connector 12.

Install the module into the LSI-ll backplane with the power turned off. An external power
supply may be used to provide +5 Vdc to finger pins BV1, BA2, and AA2, + 12 Vdc to
finger pin BD2, and ground to finger pins BJI, AJI, AT1, AC2, BC2, AMI, and BM!.

Connect an external terminal (printer or video). The terminal must be capable of generating

a 7-bit ASCII code with odd parity or 8-bit ASCII code with no parity, and baud rates of
300, 600, 1,200, 2,400, 4,800, or 9,600. The terminal is connected to SLUl connector 11
using a Digital BC20N-05 cable or equivalent. Turn the terminal on and on-line.

Turn on the backplane power or enable the +5 Vdc and + 12 Vdc sources. Monitor the module LED; it should light and then return to the normal off state. If the LED stays lit, there is
a fault in the SLU1 circuits or the on-board RAM memory.

After the backplane power is turned on, press the RETURN key (carriage return) on the
terminal to have the module synchronize its baud rate to that of the terminal. The module
responds with the prompt character '@'.

10.

To start the module diagnostic programs press the 'X' key. The diagnostic test will exercise
the module including the parallel I/O and SLU2. The results of the test are printed out on
the terminal. The error results are listed in Table 2-15 and indicate what area of the module
contains a fault. The error code '000000' indicates a good module.
2-28

Table 2-15

Diagnostic Fault Indicators

Printout

Parallel I/O
Loopback Test

Internal Serial *
I/O Loopback Test

External Serial**
I/O Loopback Test

000000

Passed

000001

Failed

Passed

000010

Passed

Failed

Not performed

000011

Failed

Not performed

000100

Passed

Failed

000101

Failed

Passed

Failed

000110

Not used

000111

Not used

The internal serial I/0 loopback test exercises the parallel-to-serial conversion, the serial-to-parallel conversion, and the
baud rate. This test can be performed without the loopback connector.

The external serial I/0 loopback test exercises the above functions as well as the drivers, receivers, and the external
signal paths.

2-29

CHAPTER 3
OPTIONS

3.1 INTRODUCTION
The SBC-11/21 is a complete single-board microcomputer that operates on the LSI-ll bus or in a
stand-alone configuration. In some applications, it may be desirable to add optional modules to the
SBC-11/21 to extend its function beyond that provided by the module itself. Paragraphs 3.2 and 3.3 list
all options available. For more information, see the documents listed in Paragraph 1.4 of this guide.
3.2 SUPPORTED OPTIONS
The following options are functionally compatible with the SBC-ll/21. Software diagnostics for these
options run on a SBC-11/21 equipped with a mass storage device (TU58, RX01, or RX02) and the
Macro-ODT option. To order diagnostics, contact your Digital sales representative.
TU58

The TU58 is a low-cost mass memory device that is used with the SBC-ll/21 byattaching it to one of the serial I/O lines. TU58 offers random access to block-formatted data
on pocket-size cassette media. It is ideal as a small computer systems device, as inexpensive archive mass storage, or as a software update distribution medium. A dual
drive TU58 offers 512Kb of storage space, making it one of the lowest cost complete
mass storage subsystems available. For mounting flexibility, the TU58 is offered both as
a component level subsystem and as a fully powered 5-1/2 inch rack-mount subsystem.
The TU58 interfaces with the microprocessor over an RS-423 serial line interface.

AAVll-C

The AAV11-C is a 4-channel, 12-bit digital-to-analog converter module that includes control and interfacing circuits. It has four D / A converters, a dc-dc converter that provides
power to the analog circuits, and a precision voltage reference. Each channel has its own
holding register that can be addressed separately and provides 12 bits of resolution. Bits
0, I, 2, and 3 of the fourth holding register are brought out to the I/O connector so that
they can be used as a 4-bit digital output register.

ADVll-C

The ADVII-C is a 12-bit successive approximation analog-to-digital converter that samples analog data at specified rates and stores the digital equivalent value for processing.
The multiplexer can accommodate up to sixteen single-ended or eight quasi-differential
inputs. The converter uses a patented auto-zeroing design that measures the sampled data
with respect to its own offset and therefore, cancels out its own offset error.
Three reference signals are provided for self-testing any channel input. These signals consist of two dc levels and one bipolar triangular waveform. This output can be used with
Digital diagnostic software to produce a data base for precise analog linearity testing.

AXVII-C

The AXVII-C functions like the ADVI1-C, but also has two 12-bit digital-to-analog converters similar to those on the AAVll-C module.

3-1

DLVII-E

The DLVll-E is an asynchronous line interface module that interconnects the LSI-II
bus to standard serial communications lines. The module receives serial data, converts it
to parallel data, and transfers it to the LSI-II bus. It also accepts parallel data from the
LSI-II bus, converts it to serial data, and transmits it to the peripheral device. The module has jumper selectable or software selectable baud rates (SO-I9,200) and jumper selectable data bit formats. The DLVII-E offers full modem control for EIA/CCITT interfaces.

DLVII-F

The DLVII-F is an asynchronous line interface module that interconnects the LSI-ll
bus to several types of standard serial communications lines. The module receives serial
data, converts it to parallel data, and transfers it to the LSI-ll bus. It also accepts parallel data from the LSI-ll bus, converts it to serial data, and transmits it to the peripheral
device. The module has jumper selectable or software selectable baud rates (SO-I9,200)
and jumper selectable data bits. The DL Vll-F supports either 20 rnA current loop devices or EIA standard lines, but does not include modem control.

DLVll-J

The DLVll-J contains four independent asynchronous serial line channels that are used
to interface peripheral devices to the LSI-II bus. Each channel transmits and receives
data from the peripheral device over EIA data leads (lines that do not use a control line).
The module can be used with 20 rnA current loop devices if a DLVll-KA adapter is
used. The DLVll-J has jumper selectable baud rates from ISO to 39.4K baud.

DPVII-DA

The DPVll-DA is a single-line, program-controlled, double-buffered communication device designed to interface the LSI-II bus to a serial synchronous line. This self-contained
unit can use a wide range of protocols including bit-oriented protocols (SDLC, HDLC,
ADCCP, and X.2S) and byte-oriented protocols (DDCMP and BISYNC).
The module is used for high-speed synchronous lines such as remote batch, remote data
collection, remote concentration, and communication networking. The module, compatible with EIA RS-232 and CCITT V.28 interface standards, is also compatible with
EIARS-423 and 422 electrical standards and thus, provides low-cost, local communications capability.

DRVll

The DRVII is a parallel interface module used to interconnect the LSI-II bus with general-purpose parallel line TTL or DTL devices. It allows program-controlled data transfers at rates up to 40K words per second and uses LSI-II bus interface and control logic
to generate interrupts and process vector handling. The data is handled by sixteen diode
clamped input lines and sixteen latched output lines. There are two 40-pin connectors on
the module for user interface applications.

DRVII-B

The DRVII-B is an interface module that uses direct memory access (DMA) to transfer
data directly between the system memory and an I/O device. The interface is programmed by the processor to move variable length blocks of 8-bit or 16-bit data words to or
from specified locations in the system memory. Once programmed, no processor interrupts are required. The module can transfer up to 2S0K I6-bit words per second in the
single cycle mode and up to SOOK I6-bit words per second in the burst mode. The module
also allows read-modify-restore operations.

DRVII-J

The DRVII-J provides sixty-four input/outut data lines on a double-height module for
the LSI-ll bus. The DRVll-J also includes an advanced interrupt structure with bit interruptability up to sixteen lines, programmable interrupt vectors, and program selection
of fixed or rotating interrupt priority within the DRVll-J. The DRVll-J bit interrupts
for real-time response make it especially useful for sensor I/O applications. It can also be
3-2

used as a general-purpose interface to special devices, and two DRVll-Js can be connected back-to-back as a link between two LSI-ll buses.
DUVll-DA The DUVll-DA synchronous line interface module creates a data communication line
between the LSI-ll bus and a Bell 201 synchronous modem or equivalent. The module is
programmable to sync characters, character length (up to 8 bits), and parity selection.
The receiver logic accepts serial data for the LSI-II bus. The transmitter logic converts
the parallel LSI-II bus data into serial data for the transmission line. The interface logic
converts the TTL logic levels to the EIA voltage levels needed by the Bell 201 modems
and also controls the modem for half-duplex or full-duplex operation.
DZV11-B

The DZV11-B is an asynchronous multiplexer interface module that interconnects the
LSI-II bus with up to four asynchronous serial data communications channels. The module provides EIA interface voltage levels and data set control to permit dial-up (auto answer) options with full-duplex modems such as Bell models 103, 113,212, or equivalent.
The DZVI1-B does not support half-duplex operations or the secondary transmit and receive operations that are available with some modems such as Bell 202. The module has
applications in data storage and collection systems where front-end systems interface to a
host computer and for use in a cluster controller for terminal applications.

IBV11-A

The IBV11-A is an interface module that interconnects the LSI-II bus with the device
bus described in IEEE standard 488 1975, Digital Interface for Programmable Instrumentation. The IBV11-A makes a processor-controlled programmable device system possible. The module can accommodate up to fifteen IEEE-488 devices.

KWV11-C

The KWV11-C is a programmable real-time clock/counter that provides a means of determining time intervals or counting events. It can be used to generate interrupts to the
processor at predetermined intervals or to establish timing between input and output
events. It can also initialize the ADV11-C analog-to-digital converter by a clock counter
overflow or by firing a Schmitt trigger. The clock counter has a resolution of 16 bits and
can be driven by anyone of five crystal-controlled frequencies (100 Hz to I MHz), from
a line frequency input, or from a Schmitt trigger fired by an external input. The module
can operate in any of four programmable modes: single interval, repeated interval, external event timing, and external event timing from zero base.

MCYII-D

The MCYI1-D is an on-board battery-backed CMOS memory that supports 22-bit addressing. The MCVII-DA is an 8Kb module, and the MCV11-DC is a 32Kb module.
The module incorporates two nickel cadmium batteries for backup in case of a power
failure.

MRYI1-C

The MRVll-C is a flexible, high-density ROM module used with the LSI-II bus. The
module contains sixteen 24-pin sockets which accept many of the user-supplied ROM
chips. The module accepts masked ROMs, fusible link PROMs, and ultraviolet erasable
PROMs. It accepts several densities of ROM chips up to and including 4K X 8 chips.
Using these high-density chips gives the module a total capacity of 64Kb .. The contents of
the module can be accessed directly or window-mapped. Direct access provides total random access to all ROM locations on the module. Window-mapping provides two 2Kb
windows of memory address space to access 2Kb segments of the ROM array. The segments that are seen through each window can be changed by program control.

MSV11-D

The MSVI1-D module has either 8K, 16K, or 32K X 16 bits of MOS memory. The
module has an on-board memory refresh and performs the necessary LSI-II bus cycles.
The memory addressing is selected by the user by configuring switch positions. The module can use a battery backup system to maintain data when primary power is lost.
3-3

MXVI1-A

The MXVII-A is a dual-height multifunction option module for the LSI-II bus. It contains a read/write memory, provisions for read only memory, two asynchronous serial line
interfaces, and a 60 Hz clock signal derived from a crystal oscillator. Read/write memory is provided with either 8Kb or 32Kb (4K or 16K words). Two 24-pin sockets are provided for +5 V read only memories. lK X 8, 2K X 8, or 4K X 8 ROMs may be used.
The sockets may also be used for 256 words of bootstrap code. The two asynchronous
serial lines transmit and receive EIA-423 signal levels from 150 baud to 38.4K baud. 20
mA active or passive current loop operation at 110 baud may be used with the DLVllKA EIA to 20 mA converter option. The serial lines will not support the reader run function of the DLVll-KA option. The serial lines provide error indicator bits for overrun
error, frame error, and parity error, but do not have modem controls. Serial line 1 may be
configured to respond to a BREAK signal. The serial lines have signal level interrupt
logic. Serial line 1 and serial line 0 may be used with any of many standard types of serial
communication devices. The 60 Hz clock signal can be selected by a wirewrap jumper to
provide real-time clock interrupts on the bus.

RXV2I

The RXV2I floppy disk option is a random access mass memory device that stores data
in fixed-length blocks on a preformatted, flexible diskette. Each diskette can store and
recover up to 5I2K 8-bit bytes of data. The RXV2I system is rack mountable and consists of an interface module, an interface cable, and either a single or dual RX02 floppy
disk drive. The interface module converts the RX02 I/O bus to the LSI-II bus structure.
It controls the RX02 interrupts to the processor, decodes device addresses for register
selection, and handles the data exchange between the RX02 and the processor via DMA
transfers. Power for the interface module is provided by the LSI-ll bus.

3.3 UNSUPPORTED OPTIONS
A list of LSI-II bus options that are not guaranteed to be functionally compatible with the SBC-II/21
and are unsupported follows. Their diagnostics are not available.
LAVll
LPVII
MRVII-AA/BA/V A
MSVI1-E/P
NCVI1-A
REVII
RKVll
RLVll
RLV12
RXVII
TEVl1
TRVll
TSVll
VMVll-A
VK170
VSVII
VTVOI-A
VTV30-H

AAVll-A
ADVII-A
BDVII-AA/BA
DAII-MS/QQ/QU
DAVII-A/B
DRLll-SN
DUVII-E/F
DUV25
DWII
DWVII-A
FEPTC-BA
FPFII
IPVI2
KDII-F
KDII-HA
KDFII-AB/ AC/BB
KDFII-BC/P
KPVll-A

3-4

CHAPTER 4
MACRO-ODT

4.1 INTRODUCfION
The Macro-OOT is the KXTII-A2 option available to users of the SBC-llj21 single-board computer.
The option has a complete listing of the firmware and two 24-pin, 2K X 8 PROM chips that contain
the Macro-OOT firmware. The chips are installed on the module using the PROM sockets.
Macro-OOT allows the user to:
1.

Examine and deposit data in memory or general registers.

Examine or change the processor status word (PSW).

Start the execution of the program.

Restart the execution of a halted program.

Bootstrap programs from a mass storage device (TU58 cassette, RXOI floppy disk, or RX02
floppy disk).

Run a diagnostic test for on-board devices.

4.2 INSTALLATION AND CONFIGURATION
The installation and configuration of the KXTll-A2 option is described in detail in Chapter 2 of this
User's Guide, and the user should refer to it for installation and startup instructions.
4.3 ENTRY CONDITIONS
Macro-OOT is entered:
1.

On power-up.

Via the BREAK key on the console terminal.

On execution of a HALT instruction.

On assertion of the BHALT L signal on the LSI-ll bus.

When accessing nonexistent memory (Le., a bus time-out).

4.3.1 Macro-ODT Input Sequence
When entering Macro-OOT, the RBUF register is read using a OATI, and the character present in the
buffer is ignored. This is done so that erroneous characters or user program characters are not interpreted by Macro-OOT as commands.

4-1

The input sequence for Macro-ODT follows.
1.

Read and ignore character in RBUF.

Output a <CR> <LF> to the terminal.

Output contents of PC (program counter R7) in six digits to terminal if ODT is entered via a
BREAK, BHALT, or HALT instruction or trying to fetch an instruction from nonexistent
memory. Output a '?' to the terminal if ODT is entered via a bus time-out.

Output a <CR> <LF> to the terminal.

Output the prompt character (@) to the terminal.

Enter a wait loop for terminal input. The done flag, bit 7 in RCSR, is tested using a DATI. If
it is zero, the test continues.

If RCSR bit 7 is a one, the low byte of RBUF is read using a DATI.

4.3.2 Macro-ODT Output Sequence
The output sequence for ODT follows.
1.

Test XCSR bit 7 (done flag) using a DATI and, if it is a zero, continue testing.

If XCSR bit 7 is a one, write character to low byte of XBUF using a DATI followed by a
DATO (high byte is ignored by interface).

4.4 MACRO-ODT COMMANDS
Table 4-1 lists the Macro-ODT commands. The commands are a subset of ODT-ll and use the same
command character. The Macro-ODT internal states are listed in Table 4-2. Only specific characters
are recognized as valid inputs for each state; other inputs produce a '1' response.
The parity bit, bit 7, on all input characters is ignored by Macro-ODT, and if the input character is
echoed, the state of the parity is copied to the output buffer (XBUF). Output characters internally
generated by ODT (e.g., <CR» have the parity bit equal to zero. All input characters are echoed.
Only uppercase command characters are recognized.
NOTE
The use of ODT commands creates a dialogue between the user and the microcomputer. All the characters typed by the user are underlined and the system response is not underlined in the examples given
in this User's Guide.
4.4.1 / (ASCII 057) Slash
The 'j' command is used to open an on-board module address, LSI-II bus address, processor register,
or processor status word and must normally be preceded by other characters that specify a location. In
response to 'j', Macro-ODT prints the contents of the location (i.e., six characters) and a space (ASCII
40). After printing is complete, Macro-ODT waits for either new data for that location or a valid close
command «CR> or <LF». The space character is issued so that the location's contents and possible new contents entered by the user are legible on the terminal.

4-2

Table 4-1

Macro-ODT Commands

Command

Symbol Function

Slash

Carriage return

<CR> Closes an open location.

Line feed

<LF> Closes an open location and opens the next location. This command
cannot be used with the general registers.

Internal register
designator

Opens a specific processor register.

Processor status
word designator

Opens the PSW; must follow R command.

Starts the execution of a program.

Proceed

Resumes the execution of a program.

Boot from device

Loads and runs programs from floppy diskettes or TU58 cassettes.

Execute diagnostics

Runs SBC-ll/21 module verification diagnostics.

Prints the contents of a specified location.

Example: @001000/12525<SPACE>
where:
@

Macro-DDT prompt character.

001000

octal location in the LSI-ll bus address space wanted by the user (leading
zeros are not required).

command to open and print contents of location.

012525

contents of octal location 1000.

<SPACE>

space character generated by Macro-DDT.

If the user issues a '/' immediately after a prompt character, the system prints? <CR> <LF> because a location is not open.

4-3

Table 4-2 Macro-ODT States and Valid Input Characters

State

Example of
Terminal
Output

0-7
P
X
D

0-7
S

@lOOOj
123456

0-7
<CR>

@Rlj123456

0-7
<CR>
<LF>

@1000

0-7
j
G

@Rl or@RS

@lOOOj
123456 1000

0-7
<CR>
<LF>

@Rlj
123456 1000

0-7
<CR>

@DY

0
1
<CR>

10*

@DX

0
1
<CR>

11*

@DD

0
1
<CR>

Valid Input

*00 not enter zero or one followed by <CR>.

4-4

4.4.2 <CR> (ASCII 15) Carriage Return
The <CR> command is used to close an open location. If a location's contents are to be changed, the
user should precede the <CR> with the new data. If no change is needed, <CR> closes the location
without modifying its contents.
Example: @Rlj004321<SPACE> <CR> <CR> <LF>
@Processor register Rl was opened, and no change was needed so the user issued <CR>. In response to
the <CR>, Macro-ODT printed <CR> <LF>@.
Example: @Rlj004321<SPACE> 1234 <CR> <CR> <LF>
@In this example, the user wanted to change Rl. The new data, 1234, was entered before issuing the
<CR>. Macro-ODT deposited the new data into the open location and then printed <CR> <LF>
@. Macro-ODT echoes the <CR> entered by the user before it prints <CR> <LF> @.
Example: @1000jOI2525<SPACE> 1234 <CR> <CR> <LF>
@-where:
first line = new data, 1234, entered into location 1000. The location is closed with <CR>.

4.4.3 <LF> (ASCII 12) Line Feed
The <LF> command is used to close an open location and then open the next contiguous location.
LSI-II bus addresses are incremented by two. If a processor register is open and an <LF> command
is issued, the register is closed and any data that was typed in before the <LF> will not enter the
register. ODT prints the error message <CR> ? <CR> <LF>. If the open location's contents are
to be changed, the new data should precede the <LF>. If no data is entered, the location is closed
without being modified.
Example: @1000/123456<SPACE> <LF> <CR> <LF>
@1002/054321<SPACE>
In this example, the user entered <LF> with no data preceding it. In response, Macro-ODT closed
location 1000 and then opened location 1002.

4.4.4 R (ASCII 122) Internal Register Designator
When followed by a register number, 0 to 7, or PSW designator, 'S', the R designator will open that
specific processor register.
Example: @ROj054321<SPACE>
or
@R7jOOOI23<SPACE> 456 <CR> <CR> <LF>
@If more than one character is typed (numeral or'S') after the 'R', Macro-ODT uses all the characters
as the register designator.

Example: @R00007 j000123<SPACE> <CR> <CR> <LF>
@

4-5

4.4.5 S (ASCII 123) Processor Status Word (PSW)
The S designator opens the PSW and must be used after the user has entered the R register designator.
Example: @R~j100377<SPACE> 0 <CR> <CR> <LF>
@R jOOOOl0<SPACE>
The T-bit filter prevents the user from setting the T-bit via Macro-ODT. The T-bit can be cleared by
any write to the PSW. When the filter is disabled, the T-bit can be set by loading the PSW to set bit 4
to a one. This is normally not considered desirable. The T-bit filter can be disabled by setting bit 15 of
location 167772 to a one.
The PRIORITY 7 filter prevents the user from setting a priority level of 7 via Ma.cro-ODT. Operation
at priority level 7 masks out (disables) the BREAK interrupt and makes it impossible to return to
Macro-ODT. This operation is normally unacceptable. If required, the PRIORITY 7 filter can be disabled by setting bit 7 of location 167772 to a one. With the filter disabled, a priority level of 7 is selected by writing 340 into the PSW.
4.4.6 G (ASCII 107) Go
The G command is used to start program execution at a location entered immediately before the 'G' in
the command string.
Example: @200G
The Macro-ODT sequence for a G command, after echoing the command character, follows.
1.

Load R 7 (PC) with the entered data. (In the previous example, R 7 is equal to 200 and that is
where program execution starts.)

The PSW is cleared to zero.

The LSI-ll bus is initialized by the processor's asserting BINIT L for 17 f.LS minimum and
then negates BINIT L.

The user program starts execution at the location specified.

The user is warned that the G command clears the PSW to permit clock interrupts to be acknowledged.
Failure to load the address of the clock service routine into the clock vector address (100) may cause
unpredictable results.
4.4.7 P (ASCII 120) Proceed
The P command is used to restart execution of a program. No programmer visible machine state is
changed using this command.
Example: @f
Program execution restarts at the address pointed to by R 7. After 'P' is echoed, Macro-ODT exits, and
the program restarts execution.
4.4.8 DD, DX, DY Bootstraps
The D command is used to bootstrap a stand-alone program or XXDP+ diagnostics from an RXOI or
RX02 floppy diskette or a TU58 tape cassette. The next character after the D command determines the
type of device being booted. A numerical character, either zero or one, is used to specify a selected
drive or unit of the device being booted. If <CR> is typed instead of zero or one, unit 0 is assumed.

4-6

Examples: Boot unit 0 of TU58 device:
@DD<CR>
Boot unit 1 of RXOI device:
@DXl
Boot unit 0 of RX02 device:
@DYO

NOTE
Do not type both unit number and <CR>.
To boot a diskette drive, ODT expects the RXVII or RXV21 controller CSR address to be configured
for 177170. To boot the TU58, it must be connected to SLU2 and the baud rate set for 38,400.
Any error detected during the execution of a boot command will cause a halt at one of many addresses
in the boot section of the ROM, with the PC contents printed on the console. The actual addresses and
the specific errors they represent are given in the listing provided with the option.
Some errors, however, are not reported. If a TU58 is not connected to SLU2 or if baud rates are incompatible, no error indication is given after using the DD command, and the program waits forever.
This is also true when booting from floppy diskettes when the drive power is off. In either condition, the
user can use <BREAK> to return to ODT prompt level (@).
The D command performs the following operations.
1.

If there is no RAM memory at address 0, the D command will cause a halt.

The command initializes the LSI-II bus by asserting BINIT L for 17 f,LS minimum.

It reads block 0 (the first 512 bytes) from the selected mass storage device into memory loca-

tions 000-777.
4.

It reads location 0 and if it is 240, it loads Rl register with the CSR address of the booted
device, loads RO register with the selected unit or drive number, and jumps to location O.

If the content of location 0 is 260, the mass storage device contains a stand-alone program.
Macro-ODT interprets the contents of locations 2, 4, and 6 as a RADIX-50 encoded six character file name. Macro-ODT assumes that the mass storage device is an RT-ll file structured voiume and searches the directory of the volume for the file name provided by locations 2, 4, and 6. When the file is found, the complete file is loaded into contiguous memory
starting at location O. The RO register is loaded with the number of the unit or drive, and the
R 1 register is loaded with the CSR address of the booted device. The stack pointer (SP) is
loaded with the contents of location 42 and the program counter (PC) is loaded with the contents of location 40. The program starts execution.

If the content of location 0 is not 240 or 260, the device does not contain a valid boot block.
The boot command is aborted, and the SBC-11/21 is initialized as if a power-up occurred.

4-7

4.4.9 X (ASCII 130) Diagnostics
After typing the letter 'X', there is a three-second delay before an octal number is displayed. This command is described in detail in Chapter 2.
4.5 INITIALIZATION
When it is necessary to reinitialize the system without removing power, the user enters 173000G from
the console in response to the '@' prompt. After a delay, the user types a carriage return to resynchronize the terminal as shown in the following example.
Example: @173000G
After a delay of at least one second, the user types <CR> to resynchronize.
4.6 WARNINGS AND PROGRAMMING HINTS
The following warnings and programming hints are provided to help the user operate Macro-ODT.
4.6.1 Error Decoding
When an '@' appears unexpectedly, it is good practice for the user to examine the word at 167774. This
is an error word that indicates the cause of entry to ODT. A HALT instruction, BREAK, or trying to
fetch from nonexistent memory will appear as 100000. Other attempted bus transactions to nonexistent
memory will appear as 000200, or, if accessed by the stack pointer R6, as 000201.
4.6.2 ODT Stack Warning
While performing its various functions, Macro-ODT requires two words of user stack. It will push and
pop internal information there. Therefore, it is necessary that the user always provide two more words
than those necessary for the correct execution of the application program. If desirable, these two words
can be given back when the program is completely debugged and operating within its own ROMs without ODT.
For correct program operation, R6 should always contain a valid even RAM memory address. Failure
to observe this rule will cause unpredictable results.
4.6.3 Addresses to Avoid
Because the firmware uses the top of the SBC-ll/21 on-board RAM as its scratchpad, the user should
not write to any address above 167642 unless specifically defined in this User's Guide.
The vector at 140 controls the BREAK interrupt. Changing locations 140 and 142 could result in the
inability to suspend program execution.
4.6.4 CPU Priority
When the PSW is set to 340, the BREAK key will have no effect and will not invoke Macro-ODT.
Running at a level 6 priority (PSW set to 300) is acceptable for most programming needs. This will
disable all interrupts except for BREAK.
4.6.5 Terminal Related Problems
Macro-ODT echoes every character typed in response to the '@' prompt. Some intelligent terminals
also respond to control characters as commands. The results may include loss of communication.
4.6.6 Spurious Halts
When the last word of an instruction is all zeros and causes a bus time-out, Macro-ODT will interpret it
as a HALT instruction and print the contents of PC on the terminal before issuing the '@' prompt.

4-8

4.6.7 Serial I/O Protocol
The Macro-ODT operates the serial line interface in full-duplex mode, and each character is echoed by
the microprocessor to the terminal. Programmed I/O methods are used instead of interrupts. When the
Macro-ODT firmware is busy printing a multicharacter message using the transmit side of the interface, the firmware is not monitoring the receive side for incoming characters. Any characters coming in
at this time are lost. The interface may set the overrun error bit, but the Macro-ODT does not check
this bit, and those characters are not recognized. All peripherals communicating with the Macro-ODT
through this interface must observe this protocol.
4.6.8 Interrupt Vector Initialization
On power-up, Macro-ODT initializes the LTC interrupt vector (REVNT at 100) and the BREAK interrupt vector (BKRQ at 140). Other vectors are not initialized and may contain erroneous data.

4-9

CHAPTER 5
SYSTEM ARCHITECTURE

5.1 INTRODUCTION
This chapter describes the architecture of the microprocessor, memory organization, and power-up
method. The microprocessor architecture describes the registers, hardware stack, interrupts, and direct
memory access (OMA) mechanism. The memory organization describes byte or word addressing and
memory mapping. The power-up procedure and initialization are also described.
5.2 MICROPROCESSOR ARCHITECTURE
The SBC-II /21 microprocessor executes a subset of the PDP-II instruction set. It has eight high-speed
general-purpose registers that are used as accumulators, address pointers, index registers, and for other
special functions. The microprocessor executes single and double operand instructions using either 16bit words or 8-bit bytes. The direct memory access (OMA) function transfers data directly from the
LSI-II bus to the on-board I/O devices and memory while the program continues to run.
5.2.1 Registers
As shown in Figure 5-1, the microprocessor contains a number of internal registers that are used for
many purposes. The registers are divided into two groups:

1.
2.

General
Status

5.2.1.1 General Registers - The microprocessor contains eight 16-bit general-purpose registers that
can perform many functions. These registers operate as accumulators, index registers, autoincrement
registers, autodecrement registers, or as stack pointers for temporary storage of data. Arithmetic operations can be performed from one general register to another, from one memory location or device register to another, or between memory locations or a device register and a general register.

Registers R6 and R7 are dedicated. R6 is the stack pointer (SP) and contains the location (address) of
the last entry in the stack. Register R 7 is the processor program counter (PC) and contains the address
of the next instruction to be executed. It is normally used for addressing purposes only and not as an
accumulator.
5.2.1.2 Status Register - The PSW contains information on the current processor status. This information includes the current processor priority, the condition codes describing the arithmetic or logic re. suIts of the last instruction, and an indicator for detecting the execution of an instruction to be trapped
during program debugging. Figure 5-1 shows the PSW format; Table 5-1 lists status word bit descriptions. Certain instructions allow programmed control of condition code bits and loading and storing
(moving) the processor status. Not all instructions affect the condition codes in an obvious way. See
Chapter 7 for details on specific instructions.

5-1

PROCESSOR STATUS
15

RO
R1
R2
GENERAL REGISTERS
R3
R4
R5

STACK POINTER

PROGRAM COUNTER

MA·7829

Figure 5-1

Registers and Processor Status Word

5.2.2 Hardware Stack
The hardware stack is part of the basic design architecture of the SBC-ll /21. It is an area of memory
used by the programmer or by the operating system for temporary storage and linkage. It is controlled
on a LIFO (last in/first out) basis; items are recovered in the reverse of the order they were stored. The
stack starts at the highest location reserved for it (376 octal at power-up) and expands linearly downward to a lower address as items are added to the stack.
It is not necessary to keep track of the actual locations into which data is being stacked. This is done

automatically through the use of the stack pointer. Register R6 always contains the memory address
where the last item is stored in the stack. Instructions associated with subroutine linkage and interrupt
service automatically use R6 as the hardware stack pointer. For this reason, R6 is often referred to as
the system SP. The hardware stack is organized in full word units only.

5.2.3 Interrupts
Interrupts are requests, made by peripheral devices, that cause the processor to temporarily suspend its
present program execution to service the requesting device. A device can interrupt the processor only
when its priority is higher than the processor priority indicated by PSW <7:5>, as shown in Table 5-2.
SBC-l1/21 supports a vectored interrupt structure with priority on four levels. In addition, it supports
two nonmaskable interrupts: power fail and HALT.

5-2

Table 5-1

Processor Status Word Bit Descriptions

Bits

Name

Description

15-08

NjA

These bits are not accessible to the programmer and contain no valid
information.

07-05

Priority

These bits define the current priority level of the microprocessor program, and only interrupts with a higher priority are recognized by the
microprocessor. Table 5-2 describes the microprocessor interrupt levels
as functions of bits 5-7.

Trace

When set, this bit allows the microprocessor to trap to locations 14 and
16 after an instruction is executed. It can only be set by executing an
RTI or RTT instruction with the correct PSW on the stack. The trace
bit allows programs to be single stepped and is useful for debugging.

Condition code N

This bit is set when an instruction causes the result to be negative.

Condition code Z

This bit is set when an instruction causes the result to be zero.

Condition code V

This bit is set when an instruction causes an overflow condition.

Condition code C

This bit is set when an instruction causes a carryout of the most significant bit.

Table 5-2

PSW Interrupt Levels

Microprocessor
Priority

Interrupt Levels
Acknowledged

PSWBits
7
6
5

Level 7
Level 6
Level 5
Level 4
Level 0-3

Nonmaskable interrupt
7
7,6
7,6,5
7,6,5,4

1
1
1
1
0

5-3

1
1
0
0
X

1
0
1
0
X

Every interrupt except HALT is associated with an interrupt vector. The interrupt vector is a pair of
words: the next PC (address of that device's service routine) and the next PSW (priority with which the
routine must be executed). Upon interrupt, the current PC and PSW are saved on the stack, and the
new PC and PSW are loaded from the vector address.
Up to sixty-four vectors may reside in the first 256 memory locations (octal 374 is the highest vector
location). The vector address is provided by the interrupting device (external vector address) or generated internally by the microprocessor.
NOTE
The power fail interrupt uses interrupt vector address 24. The HALT interrupt is not associated with
a vector. It pushes the PC and PSW on the stack
and immediately goes to the restart address with
PSW 340.
The SBC-11/21 has eleven interrupt sources. Nine of these are maskable; two are nonmaskable. An
interrupt request can occur at any time, but it is not acknowledged until the completion of the current
instruction. This lets the microprocessor execute a program until the interrupt occurs and then vector to
the service routine for the interrupt. After the service routine is completed, a return from interrupt
instruction (RTI) is executed. The microprocessor then pops the top two words, the original PC and
PSW, from the system stack, and the interrupted program is continued.
Table 5-3 lists the eleven interrupt sources with their priorities. For a device to be serviced, its priority
level must be higher than the current microprocessor level. When two devices with equal priority numbers request an interrupt at the same time, the device nearest to the top of the table is serviced first.
When an interrupt is requested by several LSI-ll bus devices at the same time, the device electrically
nearest to the SBC-1l/21 is serviced first.
5.3 DMA (DIRECT MEMORY ACCESS)
DMA allows the programmer to implement block transfers by specifying the direction of transfer, the
starting address in memory, the number of words, and any additional parameters that an external device requires. SBC-11/21 does not have an on-board DMA interface but it can support DMA transfers
for external devices via the LSI-ll bus interface. A typical device using the DMA mechanism is the
RX02 double-density floppy diskette. User-designed devices can also be connected to the SBC-11/21
DMA facility. See Chapter 9 for more information.
5.4 MEMORY ORGANIZATION
The SBC-11/21 memory uses on-board memory and LSI-ll bus memory. The memory map configurations and the types of on-board memory chips are described in Chapter 2. The memory maps are
described in Figure 5-2. Addresses from 0 to 376 octal are reserved for vector locations, and addresses
from 60Kb to 64Kb are reserved for 1/0 devices.
The address space of the SBC-ll/21 module is 64Kb. A 16-bit word is two 8-bit bytes with bits 0-7
representing the low byte and bits 8-15 representing the high byte. Words are always addressed by even
numbers. The bytes are addressed by either even or odd numbers. The high bytes are stored in the odd
numbered locations, and the low bytes are stored in the even numbered locations.
5.S POWER-UP /POWER-DOWN FACILITY
The SBC-II 121 has facilities for an automatic program startup when power is turned on and for orderly
shutdown, without loss of data, when power is turned off or lost. This is done with a combination of
hardware features and software.

5-4

Table 5-3 SBC-H/21 Interrupts
Interrupt
Source

Control
Signal

Priority
Level

Vector
Address**

HALT

-CTMER

nonmaskable

Power fail

-PFAIL

nonmaskable

LSI-II bus
signal BHAL T

BKRQ

140

LSI-ll bus
signal BEVNT

REVNT

100

SLU2 REC

ROL2

120

SLU2XMIT

XOL2

124

Parallel I lOB

PBRQST

130

Parallel I/O A

PARQST

134

SLUI REC

ROLl

SLUI XMIT

XOLI

LSI-ll bus
signal BIRQ4

IRQ4

Read from
LSI-ll bus

* The microprocessor jumps directly to the restart address with a PSW priority level 7. (RESTART is loaded into
I?C and 340 into PSW.)

All vectors defined in this table are internal vectors supplied by the microprocessor except for the BIRQ4 interrupt which is read from the bus.

Hardware features:
•

Two signal lines in the LSI-II bus, BOCOK Hand BPOK H, are used only for powerup/power-down protocol. These signals are usually generated by the power supply.

•

One signal line in the LSI-ll bus, BINIT L, that resets the system.

•

The vectoring on interrupt facility of the SBC-ll /21.

•

Battery backup connections.

Software features:
The programmer must provide power-up and power-down routines and store their addresses at the
jumper-selected start address for power-up and at location 24 for the power-down routine.
For a detailed description of the power-up/power-down protocol, see Chapter 9.
5-5

MAPO
64KB

(NOTE 3)

MAP2

MAP 1
64KB

64KB

MAP3
64KB

(NOTE 3)

4KB LOCAL RAM
(NOTE 2)

2KB (NOTE 1)
56KB

4KB LOCAL RAM
(NOTE 2)

4SKB

56KB

4SKB

LSI-11 BUS

40KB

32KB:-

32KB

24KB

24KBI·

16KB,-

16KB

16KB SOCKET A

SKB SOCKET A
aKB,-

SKB

16KB SOCKET B

4KB SOCKET A
aKB SOCKET B
4KB SOCKET B
OKB

OKB

NOTES:
1. SOCKET SET A IS MAPPED OVER SOCKET SET B AND IS
THEREFORE LIMITED TO USING EITHER SOCKET A OR
SOCKET B, BUT NOT BOTH TOGETHER.
2. ADDRESSES 160000 THROUGH 160007 ARE ASSUMED TO
RESIDE ON THE LSI-11 BUS.
3. THIS SECTION CONTAINS THE LOCAL I/O ADDRESSES FOR
THE SLUs AND PPI. ALL UNASSIGNED ADDRESSES ARE
ASSUMED TO RESIDE ON THE LSI·11 BUS.
MA·6643

Figure 5-2

Memory Maps

5-6

CHAPTER 6
PROGRAMMING INFORMATION

6.1 INTRODUCTION
The SBC-11/21 has three on-board interfaces: one parallel I/O line and two serial I/O lines. These
interfaces contain many programmable features that allow the user to change their operating characteristics. This chapter explains how this is done.
The SBC-ll/21 also has hardware that enables the microprocessor to operate in a controlled sequence
when the power is turned on and off. This hardware requires software to make it work. The basic principles of this programming are described in Appendix C.
6.2 ASYNCHRONOUS SERIAL LINE UNITS
The two serial line units (SLUs), shown in Figure 6-1, provide the means of transferring data between
the microprocessor and two user connectors, Jl or 12. The user interfaces support the EIA RS-232C
standard and RS-423 protocol at baud rates from 300 to 38,400.
Each SLU has four addressable registers. These four registers are listed in Table 6-1 and illustrated in
Figure 6-2; their functions are described in Table 6-2, Table 6-3, Table 6-4, and Table 6-5. The registers
can be accessed by the microprocessor or any DMA bus master. SLU1, with the correct software handling, can be used as a system console and is capable of initiating a hardware interrupt when BREAK is
detected. The SBC-ll/21 can be configured for the BREAK to cause a level 7 interrupt with an internal vector of 140, to enable the BHALT interrupt, or to request a HALT trap to the restart address.
SLU2 provides three line time clocks at 50 Hz, 60 Hz, and 800 Hz, which can be wire-jumper configured to enable the BEVNT level 6 interrupt. See Chapter 2 for details on how to configure the
SLUs.
6.2.1 Data Baud Rates
The serial line units transmit or receive data serially by bit and by character. Each character has ten
bits; a start bit, eight bits of data, and the stop bit. Split-speed operation of the receiver and transmitter
for the SLU is not supported, and the user cannot supply an external baud rate clock to the SLU. During power-up or reset, the outputs are disabled, and later, the baud rate defaults to 300.
Baud rates are programmable for 300, 600, 1,200, 2,400, 4,800, 9,600, 19,200 or 38,400 when bit 1 of
the transmitter control and status register (TCSR) is set to a one. The baud rate is then selected by
programming bits 5-3 of the TCSR.
The bits used for the baud rate selection are level sensitive and do not latch. Therefore, the software in
control of the TCSR must use bit set and bit reset type instructions after the baud rate is written into
the SLU. Each SLU provides an output at TTL levels to pin 1 of its connector (Jl or 12) at sixteen
times the baud rate selected for that SLU.
The Macro-DDT option has the autobaud feature that enables SLU1 to adjust itself to the terminal's
baud rate between 300 and 9,600 baud. The autobaud feature operates only when Macro-DDT is running on the system.
6-1

Jl OR J2
RCSR

f---

RECEIVER
CONTROL AND
STATUS

f
RDBR

~I-CIl

cr::
en
en
w
u
0
cr::

RECEIVER
DATA BUFFER

ROATH

RECEIVER

C-

GND

cr::
u

:2
TCSR
TRANSMITTER
AND
t-- CONTROL
STATUS

1
TDBR

TRANSMITTER
DATA BUFFER

XDAT L

TRANSMITTER

I
GND

2,4

MA·7207

Figure 6-1

Serial Line Unit (SLU) Interface

6-2

Table 6-t

Serial Line Unit Register Addresses

Description

Address

AD2

ADt

SLUI
RCSR
RDBR
TCSR
TDBR

Receiver control and status
Receiver data buffer
Transmitter control and status
Transmitter data buffer

177560
177562
177564
177566

0
0
1
1

0
1
0
1

SLU2
RCSR
RDBR
TCSR
TDBR

Receiver control and status
Receiver data buffer
Transmitter control and status
Transmitter data buffer

176540
176542
176544
176546

0
0
1
1

0
1
0
1

RECEIVER CONTROL AND STATUS REGISTER
11
14
12
09
15
13
10

TRAN~MIT

D:ATA

I I I I I~gi I I I I~g~EI ~ECV I I I I I
0

SLU 1 ADDRESS 177560
SLU 2 ADDRESS 176540

RECEIVER DATA BUFFER REGISTER
12
10

SLU 1 ADDRESS 177562
SLU 2 ADDRESS 176542

TRANSMITTER CONTROL AND STATUS REGISTER
09
08

SLU 1 ADDRESS 177564
SLU 2 ADDRESS 176544

TRANSMITTER DATA BUFFER REGISTER
11
10
12
14
13
15

I I I I I
0

SLU 1 ADDRESS 177566
SLU 2 ADDRESS 176546

0
I

06
:

B~FFER:
MR·720B

Figure 6-2

Serial Line Unit Register Bit Maps
6-3

Table 6-2

Receiver Control and Status Bit Descriptions

Bits

Name

Direction

Function

12-15

Not
used

Read
only

Reserved for future use.

Receiver
active

Read
only

This bit is set to a one by the start bit and is cleared to a zero by the
stop bit at th\! end of each byte. It is also cleared to a zero on the
power-up.

08-10

Not
used

Read
only

Reserved for future use.

Receiver
done

Read
only

This bit is set to a one when the byte received is transferred into the
RCV data buffer. It is cleared to a zero when the RCV data buffer is
read. It is also cleared to a zero on power-up.

Receiver
interrupt
enable

Read/
write

This bit is set to a one under program control. When set, it allows an
interrupt request to be initiated whenever the receiver done bit is set.
It is cleared to a zero by reset, power-up,or under program control.
Refer to Chapter 2 for interrupt jumper configuration.

00-05

Not
used

Read
only

Reserved for future use.

Table 6-3

Receiver Data Buffer Bit Descriptions

Bits

Name

Direction

Function

Error

Read
only

The bit is set to a one when the overrun error or the framing error bit
is set. It is cleared to a zero when the error producing condition is
removed.

Overrun
error

Read
only

The bit is set to a one when the received byte is transferred into the
RCV data buffer before the RCV done bit is cleared. The overrun
error indicates that the previous byte in the RCV data buffer was not
cleared prior to receiving a new byte. The bit is updated when a byte
is transferred into the RCV data buffer and cleared to a zero on
power-up.

Framing
error

Read
only

The bit is set to a one when the received character does not have a
valid stop bit and is transferred into the RCV data buffer. The bit is
cleared to a zero when a character with a valid stop bit is received
and is transferred into the RCV data buffer or on power-up.

Not
used

Read
only

Reserved for future use.

6-4

Table 6-3

Receiver Data Buffer Bit Descriptions (Cont)

Bits

Name

Direction

Function

Received
break

Read
only

The bit is set to a one when the received signal goes from a mark to a
space and stays in the space condition for 11 bit times after serial
reception starts. The bit is cleared to a zero when the received signal
returns to the mark condition or on power-up.

08-10

Not
used

Read
only

Reserved for future use.

00-07

Received
data
buffer

Read
only

These eight bits represent the most recent byte received. These bits
are cleared to zero on power-up.

Table 6-4 Transmitter Control and Status Bit Descriptions
Bits

Name

Direction

Function

08-15

Not
used

Read
only

Reserved for future use.

Transmitter
ready

Read
only

The bit is set to a one when the XMIT data buffer is ready to
accept a byte. The bit is cleared to a zero by writing into the
XMIT data buffer. The bit is also set to a one on power-up.

Transmitter
interrupt
enable

Read/
write

This bit is set to a one under program control. When set, it
allows an interrupt request to be initiated whenever the transmitter ready bit is set. The bit is cleared to a zero by reset,
power-up, or under program control.

03-05

Programmable *
baud rate
select

Read/
write

The condition of these bits selects the baud rate under program control provided the programmable baud rate select enable bit is set. The baud rates are selectable by setting these
bits as follows.

Baud Rate

300
0
0
0
1
600
0
0
1,200
0
1
0
2,400
1
1
0
4,800
0
0
I
9,600
1
1
0
19,200
0
1
1
38,400
1
1
1
When the programmable baud rate select enable bit is not
set, the baud rate defaults to 300.

6-5

Table 6-4

Transmitter Control and Status Bit Descriptions (Cont)

Bits

Name

Direction

Function

Maintenance

Read/
write

This bit is controlled by the program. When set to a one the
transmitter serial output is connected to the receiver serial input and disconnects the external serial input. This bit is
cleared to a zero by INIT, power-up, or the program.

Programmable*
baud rate
enable

Read/
write

This bit is controlled by the program. When set to a one, bits
03-05 are used to determine the baud rate. When cleared to
a zero, the baud rate will be 300 baud. This bit is cleared to a
zero by INIT, power-up, or the program.

Transmit
break

Read/
write

This bit is controlled by the program. When set to a one, the
serial output is forced into the space condition. This bit is
cleared by INIT, power-up, or the program.

* The transmitter programmable baud rate select and enable bits are level sensitive and are not latched. This requires that software
in control of the TCSR must use bit set and clear instructions to access the TCSR once the baud rate has been written into the
SLU.

Table 6-5

Transmitter Data Buffer Bit Descriptions

Bits

Name

Direction

Function

08-15

Not
used

Read
only

Reserved for future use.

00-07

Transmit
data
buffer

Read/write

These eight bits represent the next data byte to be transmitted. These bits are cleared by power-up.

6-6

6.2.2 Interrupts
Each SLU provides both a receiver interrupt and a transmitter interrupt to request service from the onboard microprocessor. Receiver and transmitter requests can be independently enabled by software.
The receiver interrupt request is enabled when the RCV interrupt enable (bit 6) of the receiver control
and status register (RCSR) is set to a one.
SLU2 has a higher interrupt priority, level 5, than SLU1 which has a level 4 interrupt priority. Within
each unit, the receiver has higher priority than the transmitter. SLU1 uses vector address 60 for the
receiver and 64 for the transmitter. SLU2 uses vector address 120 for the receiver and 124 for the
transmitter. These relationships are described in Table 5-3.
6.3 PROGRAMMING THE PARALLEL I/O INTERFACE
The parallel I/O interface, illustrated in Figure 6-3, provides a means of transferring data between the
microprocessor bus and the user interface connector 13. The interface has four addressable registers for
data and control. Table 6-6 describes these registers.
Port A and B registers are used only for data transfer to and from the user interface. Port C is used for
both data transfer and control. The control word register is used only for control of the parallel I/O
interface. The interface is programmable by using this register. In addition to software programming,
the parallel interface can also be programmed by hardware (see Chapter 2).
The parallel I/O interface is complex, and understanding all its capabilities requires considerable effort. However, efficient use can be made of the parallel I/0 using a subset of its capabilities. The following paragraphs are organized to help users find needed information. The flowchart in Figure 6-4
provides an overview of the following discussion on the parallel I/O interface, and helps guide users to
the paragraphs of specific interest to them.
6.3.1 Modes of Operation
The interface ports can operate in three basic modes that are selected by system software setting bits in
the control word register. The modes are defined as mode 0, 1, and 2 and define how the data is routed
through ports A and B.
NOTE
If the bidirectional buffers are being hardwired, care
must be taken to ensure that the wired direction
agrees with the programmed directions of ports A
and B. This is necessary to prevent driver output to
driver output connections, which could damage the
integrated circuits.
Table 6-6

Parallel I/O Register Addresses

Address

Status

PortA
Port B
Port C
Control word

176200
176202
176204
176206

Read/write
Read/write
Read/write
Write only

6-7

CONTROL
WORD
REGISTER

PCO

PC3

} INTERRUPTS

176206
USER CONNECTOR

174-;:;;44-'
PCO

J3
9

PCl

3
4

10
PORT C

(f)

co
a:

7
PC7

(f)
(f)

176204

a:
0.

A DATA
(8 LI NES)

PORTA

176200

--1

M6~_~JIR

GND

r-I
PORT B

176202

B DATA
(8 LINES)

.-J
}?IR

M50 M52

I DELAY I

+3 VDC ~---~

NETWORK

L_.-J
MA-7512

Figure 6-3

Parallel I/O Interface

6-8

PARALLEL INTERFACE
6.3 PROGRAMMING THE PARALLEL I/O INTERFACE
TABLE 6-6 PARALLEL I/O REGISTER ADDRESSES
FIGURE 6-3 PARALLEL I/O INTERFACE

I
YOU ARE HERE

MODES OF OPERATION

CONTROL WORD REGISTER

6.3.1 MODES OF OPERATION

6.3.2 CONTROL WORD REGISTER

6.3.1.1 PORT C REGISTER

TABLE 6·17 CONTROL REGISTER MODE SELECTION BIT FUNCTIONS
6.3.2.1 MODE SELECTION

MODE 0

TABLE 6·18 CONTROL WORDS FOR MODE SELECTION

MODe 1

MODE 2

6.3.1.2 MODE 0 (BASIC INPUT/OUTPun

6.3.1.5 MODE 1 (STROBED INPUT/OUTPUT)

6.3.1.6 MODE 2 (STROBED BIDIRECTIONAL I/O)
TABLE 6·14 PORT C CONTROL SIGNALS IN MODE 2

TABLE 6·7 MODE 0 CONFIGURATION

TABLE 6·10 PORT C CONTROL SIGNALS IN MODE 1

6.3.1.3 PoRT A AND B REGISTERS

TABLE 6-11 COMBINATIONS OF MODE 1

TABLE 6-15 MODE 2 PORT C BIT DESCRIPTIONS

TABLE 6·8 MODE a PORT A OR B BIT DESCRIPTIONS

TABLE 6·12 MODE 1 PORT C BIT DESCRIPTIONS

TABLE 6·16 MODE 2 CONFIGURATION

6.3.1.4 PORT C REGISTER IN MODE 0

TABLE 6·13 MODE 1 CONFIGURATION

TABLE 6-9 MODE a PORT C BIT DESCRIPTIONS

FIGURE 6·7 MODE 1 PORT C BIT ASSIGNMENTS

6.3.2.2 SETTING BITS IN PORT C
TABLE 6·19 CONTROL REGISTER BIT SET/RESET FUNCTIONS
TABLE 6-20 INTERRUPT SET/RESET CONTROL WORDS

1
INITIALIZATION

FIGURE 6-8 MODE 2 PORT C BIT ASSIGNMENTS

6.3.3 PARALLEL I/O INITIALIZATION

FIGURE 6·6 MODE a PORT C BIT ASSIGNMENTS

I
HANDSHAKING
6.3.4 PARALLEL I/O HANDSHAKING
TABLE 6·21 MODE 1 INPUT HANDSHAKING SIGNALS
TABLE 6-22 MODE 1 OUTPUT HANDSHAKING SIGNALS
TABLE 6-23 MODE 2 BIDIRECTIONAL HANDSHAKING SIGNALS
FIGURE 6-9

MODE 1 INPUT DATA HANDSHAKING SEQUENCE

FIGURE 6·10 MODE 1 STROBED INPUT TIMING
FIGURE 6-11 MODE 1 OUTPUT DATA HANDSHAKING SEQUENCE
FIGURE 6-12 MODE 1 PORT A STROBED OUTPUT TIMING
FIGURE 6-13 MODE 1 PORT B STROBED OUTPUT TIMING
FIGURE 6-14 MODE 2 PORT A BIDIRECTIONAL TIMING

Figure 6-4 Parallel I/O Flowchart

6.3.1.1 Port C Register - The bit assignments for the port C register are dependent on the mode selected and the direction of ports A and B. This register provides the handshake controls to interface
between the 8255A-5 and the output connector. The handshake control bits are set/reset by using the
control word register which is described in Paragraph 6.3.2. The port C condition for the different
modes is described in the following paragraphs that explain the modes.
6.3.1.2 Mode 0 Basic Input/Output - Mode 0 provides simple input and output of either port A or port
B or both as described in Table 6-7. The data is read from the port if programmed as an input or written
to the port if programmed as an output with no handshaking requirements. The port A and port B bidirectional buffers may be hardwired as described in Chapter 2. They may also be program controlled by
port C bits 4 and 6 if dynamic change of the port direction is wanted. In this mode, the outputs are
latched but the inputs are not.
Table 6-7

Mode 0 Configuration

PPI
Element

To Act
as Input

To Act
as Output

Direction Control
via Port C

PortA

M52 to M50

M52 to M51

M52 to M54 orM58

Port B

M49 to M50

M49 to M51

M49 to M54 or M58

PC7

Never an input

Always an output

PC6

M54 to M53

Never an output

PC5

Never an input

Always an output

PC4

M58 to M65

N ever an external
output

PC3

Never an input

Interrupt A
(vector 134)
Always an output

PC2

Always an input

Never an output

PCI

Never an input

Always an output

PCO

Never an input

Interrupt B
(vector 130)
Always an output

6-10

6.3.1.3 Port A and B Registers - The bit assignments for the port A and B registers are shown in
Figure 6-5 and described in Table 6-8. The port A and B registers are used as data buffers for all modes
of operation.
6.3.1.4 Port C Register in Mode 0 - Ports A and B use no handshaking signals, and some port Clines
can be used as input/output data lines. The bit assignments are shown in Figure 6-6 and described in
Table 6-9. When PCO and PC3 lines are not used as interrupt requests, they should be cleared by the
control word to prevent false interrupts.
6.3.1.5 Mode 1 (Strobed Input/Output) - In mode 1, the lines on port C generate or accept signals
from the user interface that control the transfer of data through ports A and B. Port C bits 0-3 (lower
nibble) are used with port B, and bits 4-7 (upper nibble) are used with port A. These signals are known
as handshaking signals. The basic functions of these control signals are defined in Table 6-10 followed
by a more detailed description of the handshake protocol.
Table 6-11 describes the four input/output combinations of ports A and B usable in mode 1. The port C
bit assignments used in mode 1 are illustrated in Figure 6-7 and described in Table 6-12. Table 6-13
links operation of mode 1 to the jumper configurations discussed in Chapter 2.

PORT DATA
MR-7211

Bits

Name

08-15

Undefined

00-07

Port data

Figure 6-5

Mode 0 Port A or B Bit Assignments

Table 6-8

Mode 0 Port A or B Bit Descriptions

Direction

Function
Not valid if a read is performed on the entire word.

Read/write

Data to output or input data to be read, depending on the port
direction.

6-11

UNDEFINED
MR-7212

Figure 6-6

Mode 0 Port C Bit Assignments

Table 6-9

Mode 0 Port C Bit Descriptions

Bits

Name

Direction

Function

08-15

Undefined

PC7

Read/write *

Output bit, drives the LED.

PC6

Read/write*

If port C upper is defined as input and M54 is connected to
M53, it is an input bit. If port C upper is defined as output
and M54 is connected to M52 (M49), it is output that controls the buffer direction for port A (port B). A one sets the
buffer for input and a zero for output.

PC5

Read/write*

Same as PC7, no LED.

PC4

Read/write*

If port C upper is defined as input and M58 is connected to
M65, it is an input bit. If port C upper is defined as output
and M58 is connected to M49 (M52), it is output that controls the buffer direction for port B (port A). A one sets the
buffer for input and a zero for output.

PC3

Not used

Not valid

PC2

Read only

Input bit

00-01

PCO-PCl

Not used

Not valid

Not valid if a read is performed on the entire word.

* Bit is written by using the control word bit set/reset function explained in Paragraph 6.3.2.

6-12

Table 6-10

Signal

Abbreviated/
Port C Bit

Port C Control Signals in Mode 1

Function

Strobe input

STBA/PC4
STBB/PC2

A low on this input loads user data into the input latch.

Input buffer full

IBFA/PC5
IBFB/PCI

A high on this output acknowledges that the data has
been loaded into the input latch. Set by STB and reset by
the program reading the input latch.

Interrupt request
(Input mode)

INTRA/PC3
INTRB/PCa

A high on this output can interrupt the CPU when an input device strobes its data into the port.

Interrupt enable
(Input mode)

INTEA/PC4
INTEB/PC2

Enables setting of INTRA and INTRB. Program controlled by PC4 or PC2.

Output buffer full

OBFA/PC7
OBFB/PCI

This output goes low to tell the user interface that the
CPU has written data to the port. Reset by ACK input
going low.

Acknowledge input

ACKA/PC6
ACKB/PC2

A low on this input tells the processor that the user's device accepted the data from A or B.

Interrupt request
(Output mode)

INTRA/PC3
INTRB/PCa

A high on this output can interrupt the CPU when an
output device has accepted data transmitted by the
CPU. Set by ACK and reset when new data is written to
the port.

Interrupt enable
(Output mode)

INTEA/PC6
INTEB/PC2

Enables setting of INTR. Program controlled by PC6 or
PC2.

6-13

Table 6-11

Combinations of Mode 1

Port C Bit
Functions

Port A Input
with
Port B Output

Port A Output
with
Port B Input

Ports
A&B
Output

Ports
A&B
Input

STBA

PC4

NjA

PC4

STBB

NjA

PC2

NjA

PC2

IBFA

PC5

NjA

PC5

IBFB

NjA

PC1

NjA

PC1

INTRA

PC3

INTRB

PCO

OBFA

NjA

PC7

NjA

OBFB

PC1

NjA

PC1

NjA

ACKA

NjA

PC6

NjA

ACKB

PC2

NjA

PC2

NjA

Other port C outputs

PC7
(controls LED)

NjA

PC5

NjA

Other port C inputs

NjA

PC4

NjA

PC6,7

0
1
0

1
1
1
0
1
0
1

0
1

1
1
0
1
1
0
1

Control Word
DO (Direction of PCO-3)
D 1 (Direction of port B)
D2 (Mode of port B)
D3 (Direction of PC4-7)
D4 (Direction of port A)
D5 Port A mode
D6 Port A mode
D7 Mode set enable

1
1

0
1

6-14

0
1
0
1

: UNDE:FINED:

I/O

I/O I'BFA I

UNDE~INED:

10BFAI

05
I/O

I'BFB I

INTE13
(STB13)

INTRB

I'NTRAI

INTEA
(ACKA)

A AND B BOTH OUTPUTS

I'NTRAI

INTEA
(STBA)

A AND B BOTH INPUTS

10BFBI

INTEB
(ACKB)

INTRB
MA·7213

Bits

Name

08-15

Undefined

PC7

Figure 6-7

Mode 1 Port C Bit Assignments

Table 6-12

Mode 1 Port C Bit Descriptions

Direction

Function
Not valid if a read is performed on the entire word.

Read/write*

If port A mode 1 input:
If port C bits 04-07 are defined as output, this bit is an output bit and controls the LED. A zero turns the LED on, and a
one turns it off.

Unused if port C bits 04-07 are defined as input.
OBFA**

Read only

If port A mode 1 output:

OBFA goes low to indicate that data has been written into the
output buffer by the processor. This bit is set when the
ACKA (PC6, M54 to M53) input goes low indicating that
the external device has accepted the output data. OBFA is
present on PC7 to the external device.
06

PC6

Read/write*

If port A mode 1 input:
If port C bits 04-07 are defined as input and M54 is connected to M53, it is an input bit. If port C bits 04-07 are
defined as output and M49 is connected to M54, it is an output that controls the buffer direction for port B. A one sets
the buffer for input, and a zero sets the buffer for output.

INTEA

Read/write *

If port A mode 1 output:

When set, INTEA enables INTRA to interrupt the
SBC-ll/21 when output data has been accepted by the external device.

6-15

Table 6-12

Bits

Name

Mode 1 Port C Bit Descriptions (Cont)

Direction

When M54 is connected to M53, an external signal acknowledging the receipt of data acts as INTEA.

ACKA
05

IBFA

Function

Read only

If port A mode 1 input:

IBF A indicates that the input data has been latched for port
A. It is set by the STBA input (PC4, M58 to M65) going low
and is reset by the processor reading the port data. This signal
is present on PC5 to the external device.
PC5

Read/write*

If port A mode 1 output:
If port C upper is defined as output, it is an output bit. If port
C upper is defined as input, it is unused.

INTEA

Read/write*

If port A mode 1 input:
If set, INTEA will allow INTRA to interrupt the SBC-ll /21
whenever the input buffer is full.

PC4

Read/write *

If port A mode 1 output:
If port C bits 04-07 are defined as output and M49 is connected to M58, this bit is output that controls the direction of
the port B buffer. A one sets the buffer for input and a zero
sets it for output. If port C bits 04-07 are defined as input
and M58 is connected to M65, it is an input bit and is interpreted as STBA (input strobe).

INTRA

Read only

If port A mode 1 input:

A one indicates that port A has valid input data. It is set by
STBA (PC4, M58 to M65) being pulsed low and is reset by
the processor reading the port data. INTRA is enabled by
INTEA being a one and disabled by INTEA being a zero.
If port A mode 1 output:

A one indicates that port A is ready to accept new output
data. It is set by ACKA (PC6, M54 to M53) being pulsed low
and reset by the processor writing new output data to the
port. Enabled and disabled as above.
When enabled, INTRA interrupts the processor and has a
vector of 134.
This signal is also an output to the external device on line
PC3.

6-16

Table 6-12

Mode 1 Port C Bit Descriptions (Cont)

Bits

Name

Direction

Function

INTEB

Read/write*

When set, INTEB will allow INTRB to interrupt the
SBC-ll/21 to request service.

IBFB

Read only

If port B mode 1 input:

IBFB indicates input data has been latched for port B when a
one. It is set by the STBB (PC2) being low and is reset by the
processor reading the port data. This signal is present on PC 1
to the external device.
OBFB**

Read only

If port B mode 1 output:

OBFB goes low to indicate that the processor has written data
to the port. This bit is set by ACKB (PC2) going low, indicating the external device has accepted the output data. This signal is present on PC 1 to the external device.
00

INTRB

Read only

If port B mode 1 input:

A one indicates port B has valid input data. It is set by STBB
(PC2) being pulsed low and is reset by the processor reading
the port data. INTRB is enabled when INTEB is one and disabled when it is zero.
If port B mode 1 output:

A one indicates that the port is ready to accept new output
data. It is set by ACKB (PC2) being pulsed low and reset by
the processor writing new output data to the port. Enabled
and disabled as above.
This signal is also an output to the external device on PCO.

*Bit is written by using the control word bit set/reset function described in Paragraph 6.3.2.
**If OBF is asserted low and a read or write access is made to the port by the processor before an ACK strobe is sent by the
external device, the aBF line for the accessed port will negate during the assertion of the read or write to the port and become
reasserted when the read or write operation is complete.

6-17

Table 6-13

Mode 1 Configuration

PPI
Element

Input
Conditions

Output
Conditions

Program Control
via Port C

PortA

MS2 to MSO

MS2 to MSI

N/A

Port B

M49 to MSO

M49 to MSI

M49 to MS4 or MS8

PC7

Never an input

Output buffer A full

PC6

MS3 toMS4
(Acknowledge A)*

Never an external
output

PCS

Never an input

Input buffer A full

PC4

M6S to MS8
(Strobe A)

N ever an external
output

PC3

N ever an input

Interrupt A
(vector 134)

PC2

Strobe B
in input mode
Acknowledge B in
output mode

Never an output

PCl

Never an input

Buffer B full on
input or output

PCO

Never an input

Interrupt B
(vector 130)

*User's hardware acknowledges receipt of data output by port A.

6.3.1.6 Mode 2 (Strobed Bidirectional I/O) - Mode 2 implements communication with a user device
over a single 8-bit bus for both transmitting and receiving data. Handshaking and interrupt signals are
used as they are in mode 1.
Mode 2 is used with port A only and five control lines on port C. Both inputs and outputs are latched.
When port A is operating in this mode, the port B bidirectional buffers cannot be operated under program control because PC4 and PC6 are being used. Port B can operate in either mode 0 or mode 1 but
the buffers must be hardwired. PCO--PC2 are defined by port B conditions for mode 1 and are available
as I/O lines when port B is in mode o.
Control signals are defined in Table 6-14. The port C bit assignments as u~ed in mode 2 are illustrated
in Figure 6-8 and described in Table 6-1S. Table 6-16 links operation of mode 2 to the jumper configurations discussed in Chapter 2.

6-18

Table 6-14 Port C Control Signals in Mode 2

Signal

Abbreviated/
Port C Bit

Interrupt request

INTRA/PC3

A high on this output can interrupt the CPU for both
input and output operations.

Output buffer full

OBFA/PC7

This output goes low to indicate that the CPU has written data to port A.

Acknowledge

Function

A low on this input enables the output tristate buffers of
port A to send out the data. Otherwise, that buffer is in
the high impedance state.

Interrupt enable

INTEAl/PC6

Enables INTR when OBF is true. Controlled by bit
set/reset of PC6.

Strobe input

STBA/PC4

A low on this input loads data into the input latch.

Input buffer full

IBFA/PC5

A high on this output indicates that data has been
loaded into the input latch.

Interrupt enable

INTEA2/PC4

Enables INTR when IBF is true. Controlled by bit
set/reset of PC4.

6-19

: UNDE:FINED:

!OBFA!

!INTRA!

!IBFA !

INTEA 1
(ACKA)

INTEA2
(STBA)
MR·7214

Figure 6-8

Mode 2 Port C Bit Assignments

Table 6-15 Mode 2 Port C Bit Descriptions
Function

Bits

Name

08-15

Undefined

OBFA

Read only

Will go low to indicate that the processor has written output
data to the port. It goes high when ACKA (PC6, M54 to
M53) goes low indicating the external device has accepted the
data. This signal is output on PC7 to the external device.

INTEAl

Read/write *

When this bit is set, it allows an interrupt INTRA when the
output buffer is ready to accept new data.

IBFA**

Read only

IBFA indicates that input data has been latched when it is a
one. This bit is reset when the processor reads the input data.
This signal is output on PC5 to the external device.

INTEA2

Read/write*

When this bit is set, it allows an'interrupt INTRA when the
input buffer is full.

INTRA

Read only

A high on this bit indicates that the port is requesting service
of the processor. This signal is output on PC3 to the external
device.

02-00

PCO-PC2

Direction

Not valid if a read is done on the entire word.

These bits are defined by port B mode selection.

* Bit is written by using the control word bit set/reset function described in Paragraph 6.3.2.
** When using port A in mode 2 operation, the software must clear the input buffer of port A if the input buffer full flag (IBFA)
is set before it performs the read during an intended write to ensure that the handshake lines and port flags are not set out of
sequence.

6-20

Table 6-16 Mode 2 Configuration
PPI
Element

Input
Conditions

Output
Conditions

PortA

Bidirectional bus

M52 to M54 to M53

Port B

Hardwired only

PC7

Never an input

Output buffer A full

PC6

Acknowledge A

Never an output

PC5

Never an input

Input buffer A full

PC4

Strobe A (M65 to M58)

Never an output

PC3

Never an input

Interrupt A (vector 134)

PC2

Always an input

Never an output

PCI

Never an input

Always an output

pca

Never an input

Always an output

6-21

6.3.2 Control Word Register
The control word register controls the operation of the parallel interface. If bit 7 is set, the contents of
the register determine the mode of operation and the input/output direction of the ports. If bit 7 is
cleared, the contents of the register set/reset the port C register bits. The functions of the register bits
are described in Table 6-17 and are selected by the state of the bit.
6.3.2.1 Mode Selection - The user determines the mode of operation for the ports and defines them as
inputs, outputs, or bidirectional. The user then must ensure that the bidirectional buffers are configured
(see Chapter 2) to match the software requirements. Table 6-18 lists all the control words available for
the control word register. The user selects the control word that matches the requirements and loads it
into the register. The register is defined as write only; reading the register results in erroneous data.
6.3.2.2 Setting Bits in Port C - The control word register is also used to set or reset the port C register
bits. The control word bit functions are described in Table 6-19. To set a bit, the register is loaded with
bit 7 cleared, bits 1-3 equal to the bit number being set, and bit 0 set. To reset the same bit, bit 0 is
cleared. The bit set/reset can be used to enable or disable the port A and port B interrupts for the SBC11/21. The control words used to enable or disable the interrupts are listed in Table 6-20.

Table 6-17 Control Register Mode Selection Bit Functions
Bits

Bit Set

Bit Reset

08-15

Unused

Always set

Port A mode 2

Port A mode 0 or 1

Port A mode 1

Port A mode 0

Port A input

Port A output

Port C bits 04 and 06
inputs

Port C bits 04-07
outputs

Port B mode 1

Port B mode 0

Port B input

Port B output

Port C bit 02 input

Port C bits 00, 01,
and 03 outputs

6-22

Table 6-18 Control Words for Mode Selection

PortB
Mode 0
OUT

PortC

PortB
Mode 1
OUT

PC4,PC6

PC5,PC7

233

231

237

235

Input

233

221

227

225

213

211

217

215

203

201

207

205

273

271

277

275

263

261

267

265

253

251

257

255

243

241

247

245

3X3

3Xl

3X7

3X5

PortB
Mode 0

PortA
Mode 0 IN

PortA
Mode 0 OUT

PortA
Mode 1 IN

PortA
Mode lOUT

Port A
Mode 2

PortB
Mode 1

*Port C unavailable, used for handshaking.
X = Do not care condition.

6-23

Output
Input
Output
Input
Output
Input
Output

Table 6-19 Control Register Bit Set/Reset Functions
Bits

Function

08-15

Not used

Always reset

06-04

Not used

03-01

These bits select the port C bit that is to be set or reset as follows.

Bit

PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7

0
0
1
1
0
0
1
1

o·
0
0
1
1
1

0
1

0
1
0
1

This bit is set to set the selected bit or is cleared to reset the selected bit of port C.

Table 6-20 Interrupt Set/Reset Control Words

Mode

Direction

Enable

Input

011

Output

2
2

INTRA
Disable

INTRB
Enable

Disable

010

005

004

015

014

005

004

Input

011

010

None*

Output

015

014

None*

·Port B does not function in the bidirectional mode 2.

6-24

6.3.3 Parallel I/O Initialization
During power-up or the execution of a RESET instruction, the port C data lines are driven high and the
LED (driven by bit 7 of port C) is turned off. If the bidirectional buffers of ports A and B are hardwired, the directions are not changed, and the data lines are driven high if the buffer is configured as an
output. If the bidirectional buffers of ports A and B are program controlled by port C, the data lines
will go to the input state.
6.3.4 Parallel I/O Handshaking
The parallel I/O can operate in either mode 0, 1, or 2 to transfer data into or out of the SBC-ll/2l.
The mode 0 data transfers do not require any handshaking control signals. Tqe mode 0 input data is not
latched, and data should be available on the I/O connector at the same time as the read strobe enables
the 8255A-5. The mode 0 output data is latched, and data is valid at the I/O connector 362 ns after the
trailing edge of the write strobe to the 8255A-5.
The handshaking signals that pass across the user interface are detailed as follows. Mode 1 operation
requires the handshaking control signals; these are dependent on defining the ports as inputs or outputs.
Mode 1 input signals are listed in Table 6-21, and the handshaking function is shown in Figure 6-9.
Mode 1 input timing is described in Figure 6-10. Mode 1 output signals are listed in Table 6-22, and the
handshaking function is shown in Figure 6-11. Mode 1 output timing is described for port A in Figure 612, and mode 1 output timing is described for port B in Figure 6-13. Mode 2 operation allows port A to
be bidirectional. The handshaking signals are listed in Table 6-23, and mode 2 timing is described in
Figure 6-14. When port A operates in mode 2, port B can operate only in mode 0 or mode 1.

Table 6-21

Mode 1 Input Handshaking Signals

Signal Name

Function

STB (A or B)
Port A - PC4
Port B - PC2

Strobe input - This signal is asserted low by the external device and loads data
into the SBC-ll/21 input port latch. It must be asserted low for 525 ns
minimum.

IBF (A or B)
by Port A - PC5
Port B - PCI

Input buffer full - This signal is asserted by the SBC-ll/21 in response to an
assertion of STB to notify the interface that data was loaded into the input latch.

INTR (A or B)
to Port A - PC3
Port B - PCO

Interrupt request - This signal can be used to generate an interrupt to the microprocessor. The bitset/bitreset commands must be used to enable/disable the
INTE bit for each port. Interrupts will be generated either when STB is negated
with IBF asserted, or when ACK is negated with OBF asserted.

6-25

SBC-ll/21

EXTERNAL DEVICE

REQUEST DATA
• IBF UNASSERTED ________

~SENDDATA
• PLACE DATA ON I/O BUS
• ASSE RTS STB
ACCEPTS DATA
• ASSERTS IBF
ACKNOWLEDGES ACCEPTED DATA
• UNASSERTED STB
REQUEST INTERRUPT IF INTE SET
• ASSERT INTR
/
• PROCESSOR READS DATA PORT
• NEGATE INTR IF ASSERTED
• NEGATE IBF

MR~7216

Figure 6-9

Mode 1 Input Data Handshaking Sequence

1--512nSMIN~
STB --~

~I'------------------------------

_-1 312ns L_
"I MIN I"
IBF

I
I

,
,

- ' 312ns
I MAX

I
I

~ 312ns MAX j.-

INTR
I

INPUT DATA
I/O BUS

r-------r---~

-------<,"

12ns I
MIN,

"I-

192ns I
MIN
I

VALID DATA)- -

PORT DATA
READ
MR-7217

Figure 6-10

Mode 1 Strobed Input Timing

6-26

Table 6-22

Mode 1 Output Handshaking Signals

Signal Name

Function

OBF (A or B)
Port A - PC7
Port B - PCI

Output buffer full - This output is asserted low to indicate that the microprocessor has written data into the specified port latches.

ACK (A or B)
Port A - PC6
Port B - PC2

Acknowledge input - This signal is asserted low by the external device to indicate
it has accepted the latched output data from the specified port. .

INTR (A or B)
to Port A - PC3
Port B - PCO

Interrupt request - This signal can be used to generate an interrupt to the microprocessor when the external device has received the data and INTE is set and
ACK is negated.

SBC·11/21

EXTERNAL DEVICE

OUTPUT DATA
• OUTPUTS DATA ON I/O BUS
• ASSERTS OBF

________
OUTPUT COMPLETE
• NEGATESOBF

ACCEPT DATA

• ASSE RTS ACK
• READS DATA

~ ACKNOWLEDGE? RECEIVED DATA

~
GENERATE INTERRUPT

• UNASSERTSACK

IF INTE SET
• ASSERTS INTR
NOTES:
1.

IF OBF IS ASSERTED LOW AND A READ OR WRITE TO THE PORT
BY THE SBC-11/21 PROCESSOR OCCURS BEFORE AN ACK STROBE IS
SENT BY THE EXTERNAL DEVICE, THE OBF LINE FOR THE ACCESSED
PORT WILL NEGATE DURING THE ASSERTION OF THE READ OR WRITE
TO THE PORT AND THEN BECOME REASSERTED.

OBF WILL ASSERT ON THE READ PORTION OF EVERY READ BEFORE
INTENDED WRITE TO PORT B, AND THE OBF B WILL NEGATE AND REASSERT
ON THE WRITE STROBE'. IF INTEB IS SET AND INTRB IS ASSERTED,lNTR a
WILL NEGATE ON THE READ aEFORE THE INTENDED WRITE TO PORT B
(SEE FIGURE 6-13.)

3. OBF WILL ASSERT ON THE WRITE PORTION OF EVERY READ BEFORE
INTENDED WRITE TO PORT A. IF INTEA IS SET AND INTRA IS ASSERTED,
INTRA WILL NEGATE ON THE WRITE PORTION OF THE READ BEFORE
INTENDED WRITE TO PORT A.
MR-7218

Figure 6-11

Mode 1 Output Data Handshaking Sequence

6-27

WRITE
PORT DATA _ _ _ _-!

~----~z !~--------

962n5 MAX

'-'I

I ~

INTRA -------------------T""il

1 662n5 1

1 375n5 I
.. MAX .1

:4 MAX.

OBFA-----------rl---i~~
1
1
1
1
ACKA-----------rl--~Z ~~

~ 375n5 :

1 362n5 1
MAX
~

I MAX 1

~
OUTPUT DATA
A• LATCHED OUTPUT DATA
1/0 BUS _ _ _ _ _ _ _ _ _ _ _ _.....J•

------------......,W

MR-7219

Figure 6-12

Mode 1 Port A Strobed Output Timing

WR------------~

662n5 1

I MAX

INTRB

:375n~1
MAX 1

-~r-"'1

1.--.1 375n5

ACKB-----------------------~--------I
~AX
1
L....J

362n5~
MAX I
I

LATCHED OUTPUT
DATA
OUTPUTDATA _________________________--J~r----~~~---

1/0 BUS

NOTE:
1. OBF WILL ASSERT ON THE READ PORTION OF EVERY READ BEFORE
INTENDED WRITE TO PORT B AND THE OBF WILL NEGATE AND REASSERT
ON THE WRITE STROBE. IF INTEB IS SET A~D INTRB IS ASSERTED, INTRB
WILL NEGATE ON THE READ BEFORE THE INTENDED WRITE TO PORT B.
MR·7220

Figure 6-13

Mode 1 Port B Strobed Output Timing

6-28

Table 6-23

Mode 2 Bidirectional Handshaking Signals

Signal Name

Function

STB (PC4)

Strobe input - This signal is asserted low by the external device and strobes
data into port A.

IBF (PC5)*

Input buffer full- This signal is asserted when the microprocessor has accepted
STB strobe.

INTR (PC3)

Interrupt request - This signal can be used to generate an interrupt to the microprocessor when the external device is demanding service.

OBF (PC7)

Output buffer full - This output is asserted to indicate that the microprocessor
has written data into the output port latches.

ACK (PC6)**

Acknowledge input - This signal is asserted low by the external device to indicate it has taken data from the output port latches. It controls the DIR pin of
the port A buffer.

Because every write is preceded by a read, the contents of the input buffer should be saved if IBFA is asserted prior to
writing port A mode 2 data.

When mode 2 is configured, PC6 (ACK) is jumpered to the port A direction control pin through a rising edge delay
circuit. Hence, when PC6 is negated, the rising edge is delayed by 250 ns minimum. This means that the buffer will be
driving data out of the connector 250 ns minimum after the user interface negates ACK.

WRITE - - ,
PORT A
----I
1..622ns MAX .. ,

375ns

1....

INTR

' ..MAX .. '

11--____. . .
I
325ns
_ _ _ _ _ _ _ _ _ _ _-;~~M_I_N_ _ _ _ _ __

ACK

I 525ns I
MIN

I" "I
IBF

~~~:~~·Ir-,-----~--------~
I 12ns

192ns

I.. MIN.I .. MIN .. 1
DATA
110 BUS

-'( INPUT DATA

!325ns,

,~A~I OUTPUT
DATA

'f .J - { ____>r-- i
I 20ns MIN I
14

I 312nsJ-

I~AX.I

READ
PORTA

1500ns MAX

..._ __
MR·7221

Figure 6-14

Mode 2 Port A Bidirectional Timing

6-29

CHAPTER 7
ADDRESSING MODES AND INSTRUCTION SET
•

7.1 INTRODUCTION
This chapter provides a detailed discussion of addressing modes and descriptions of individual instructions. The discussion of addressing modes is divided into six major topics.
1.

Single operand addressing - One part of the instruction word specifies the registers; the remaining part provides information for locating the operand.

Double operand addressing - Part of the instruction word specifies the registers; the remaining parts provide information for locating two operands.

Direct addressing - The operand is the content of the selected register.

Deferred (indirect) addressing - The content of the selected register is the address of the
operand.

Use of the program counter (PC) as a general-purpose register - The PC is unique from other
general-purpose registers. Whenever the processor retrieves an instruction, it automatically
advances the PC by two. By combining this automatic advancement of the PC with four of
the basic addressing modes, four special PC modes are produced - immediate, absolute, relative, and relative deferred.

Use of the stack pointer (SP) as a general-purpose register - The SP can be used for stack
operations.
NOTE
Instruction mnemonics and address mode symbols
are sufficient for writing assembly language programs. The programmer need not be concerned
about conversion to binary digits; this is accomplished automatically by the assembler program.

7.2 ADDRESSING MODES
Data stored in memory must be accessed and manipulated. Data handling is specified by an SBC-II/2I
instruction (MOV, ADD, etc.) that usually specifies the following.
1.

The function to be performed (operation code).

A general-purpose register to be used when locating the source and/or destination operand.

An addressing mode that specifies how the selected register(s) is/are to be used.

Most data handled by a computer is structured (in character strings, arrays, lists, etc.). SBC-ll/2I
addressing modes allow efficient and flexible handling of structured data.
7-1

The general-purpose registers may be used with an instruction in any of the following four ways.
1.

As accumulators. The data to be manipulated resides within the register.

As pointers. The content of the register is the address of the operand, rather than the operand
itself.

As pointers that automatically step through memory locations. Automatically stepping forward through consecutive locations is known as autoincrement addressing; automatically
stepping backward is known as autodecrement addressing. These modes are particularly useful for processing tabular or array data.

As index registers. The contents of the register and the word following the instruction are
summed to produce the address of the operand. This allows easy access to variable entries in
a list.

The register arrangement is an important microprocessor feature that should be considered in conjunction with the addressing modes. There are six general-purpose registers (RO-RS), a hardware stack
pointer (SP) register (R6), and a program counter (PC) register (R7).
Registers RO-RS are not dedicated to any specific function; their use is determined by the instruction
that is decoded.
1.

They can be used for operand storage. For example, the contents of two registers can be
added and stored in another register.

They can contain the address of an operand or serve as pointers to the address of an operand.

They can be used for the autoincrement or autodecrement features.

They can be used as index registers for convenient data and program access.

The SBC-llj21 also has instruction addressing mode combinations that facilitate temporary data storage structures. These combinations can be used for conveniently handling data that must be accessed
frequently. This is known as stack manipulation. The register that keeps track of stack manipulation is
the stack pointer (SP). Any register can be used as a stack pointer under program control; however,
certain instructions associated with subroutine linkage and interrupt service automatically use register
R6 as a hardware stack pointer, and therefore, R6 is frequently referred to as the SP.
•

The stack pointer keeps track of the latest entry on the stack.

•

The stack pointer moves down as items are added to the stack and moves up as items are
removed. It always points to the top of the stack.

•

The hardware stack is used during trap or interrupt handling to store information and allow
the processor to return to the main program.

Register R 7 is used by the processor as its program counter (PC) and should not be used as a stack
pointer or accumulator. Whenever an instruction is fetched from memory, the program counter is automatically incremented by two to point to the next instruction word.

7-2

7.2.1 Single Operand Addressing
The instruction format for all single operand instructions (such as clear, increment, and test) is illustrated in Figure 7-1.
06

OP CODE

DESTINATION ADDRESS
MR-5458

Figure 7-1

Single Operand Addressing

Bits 15-6 specify the operation code that defines the type of instruction to be executed. Bits 5-0 form a
six-bit field called the destination address field that consists of two subfields.
1.

Bits 0-2 specify which of the eight general-purpose registers is to be referenced by the instruction word.

Bits 3-5 specify how the selected register will be used (address mode). Bit 3 is set to indicate
deferred (indirect) addressing.

7.2.2 Double Operand Addressing
Operations that imply two operands (such as add, subtract, move, and compare) are handled by instructions that specify two addresses. The first operand is called the source operand; the second operand is
called the destination operand. Bit assignments in the source and destination address fields may specify
different modes and different registers. The instruction format for the double operand instruction is
illustrated in Figure 7-2.

15
OP

~ODE

SOURCE ADDRESS

DESTINATION ADDRESS
-MR-6459

Figure 7-2

Double Operand Addressing

The source address field is used to select the_source operand, the first operand. The destination is used
similarly and locates the second operand and the result. For example, the instruction ADD A, B adds
the contents (source operand) of location A to the contents (destination operand) of location B. After
execution, B will contain the result of the addition; the contents of A will be unchanged.

7-3

Examples in this chapter use the sample SBC-ll/21 instructions listed in Table 7-1. See Paragraph 7.3
for a complete list of the SBC-ll/21 instructions.
Table 7-1

Sample SHe-11/21 Instructions

Mnemonic

Description

Octal Code

CLR

Clear (zero the specified destination)

0050DD

CLRB

Clear byte (zero the byte in the specified
destination)

l050DD

INC

Increment (add one to the contents of the
destination)

0052DD

INCB

Increment byte (add one to the contents of
the destination byte)

l052DD

COM

Complement (replace the contents of the
destination by its logical complement; each
zero bit is set and each one bit is cleared)

0051DD

COMB

Complement byte (replace the contents of the
destination byte by its logical complement; each
zero bit is set and each one bit is cleared)

l051DD

ADD

Add (add source operand to destination operand
and store the result at destination address)

06SSDD

DD = destination field (6 bits)
SS = source field (6 bits)
= contents of

7-4

7.2.3 Direct Addressing
Table 7-2 summarizes the four basic modes used with direct addressing. Figures 7-3, 7-4, 7-5, and 7-6,
which follow the table, illustrate these four modes.

Table 7-2

Direct Addressing Modes

Mode

Name

Assembler
Syntax

Function

Autoincrement

(Rn)+

Autodecrement

-(Rn)

Index

X(Rn)

Value X is added to (Rn) to produce address of
operand. Neither X nor (Rn) is modified.

INSTRUCTION

OPERAND
MA-5460

INSTRUCTION

Figure 7-3

Mode 0 Register

ADDRESS

OPERAND

~----~~ +2 FOR WORD,

+1 FOR BYTE

MR-5461

Figure 7-4

Mode 2 Autoincrement

7-5

-2 FOR WORD,
-1 FOR BYTE

INSTRUCTION

OPERAND

MR-64S2

Figure 7-5

INSTRUCTION

Mode 4 Autodecrement

ADDRESS
OPERAND

x
MR-5463

Figure 7-6

Mode 6 Index

7.2.3.1 Register Mode (Mode 0) - With register mode, any of the general-purpose registers may be
used as simple accumulators, and the operand is contained in the selected register. Because they are
hardware registers, within the processor, the general-purpose registers operate at high speeds and provide speed advantages when used for operating on frequently accessed variables. The assembler interprets and assembles instructions in the following form as register mode operations.
OPRRn
Rn represents a general-purpose register name or number"and OPR represents a general instruction
mnemonic. Assembler syntax requires that a general-purpose register be defined as follows.
RO = %0 (The '%' sign indicates register definition.)
Rl = %1
R2 = %2, etc.
Registers are typically referred to by name as RO, RI, R2, R3, R4, R5, R6, and R7. However, R6 and
R7 are also referred to as SP and PC, respectively.
Register Mode Examples (Figures 7-7, 7-8, and 7-9)
(all numbers in octal)

Symbolic

Octal Code

Instruction
Name

INCR3

005203

Increment

Operation
One is added to the contents of the generalpurpose register R3.

7-6

15
0

: :
0

: : :
1

I : l I :

00
1

~ .., SELECT

I REGISTER

OP CODE (INC(0052))

I
I

DESTINATION FIELD

RO
R1
R2
R3

I+- J

R4
R5
R6 (SP)
R7 (PC)
MR-5467

Figure 7-7

Symbolic

Octal Code

Instruction
Name

ADD R2, R4

060204

Add

INC R3

Operation
The contents of R2 are added to the contents of
R4.

BEFORE

AFTER

R21

000002

R21

000002

R41

000004

R41

000006
MR-5468

Figure 7-8

ADD R2,R4

7-7

Symbolic

Octal Code

Instruction
Name

COMB R4

105104

Complement byte

Operation
Complement bits 0-7 (byte) of one in R4. (When
general-purpose registers are used, byte instructions only operate on bits 0-7; i.e., byte 0 of the
register.)

BEFORE

AFTER

022222

022155

R41

MR·5469

Figure 7-9

COMB R4

7.2.3.2 Autoincrement Mode (Mode 2) - Autoincrement mode allows automatic stepping of a pointer
through sequential elements of a table of operands. It assumes that the content of the selected generalpurpose register is the address of the operand. Contents of registers are stepped (by one for bytes, by
two for words, and by two for R6 and R7) to address the next sequential location. The autoincrement
mode is especially useful for array processing and stack processing; it accesses an element of a table
and then steps the pointer to address the next operand in the table. Although most useful for table
handling, this mode is general and may be used for a variety of purposes. The assembler interprets and
assembles instructions in the following form as autoincrement mode operations.

OPR (Rn)+
Autoincrement Mode Examples (Figures 7-10, 7-11, and 7-12)

Symbolic

Octal Code

Instruction
Name

CLR (R5)+

005025

Clear

Operation
The contents of R5 are used as the address of the
operand. The selected operand is cleared, and the
contents of R5 are then incremented by two.

BEFORE

AFTER

ADDRESS SPACE

20000

005025

ADDRESS SPACE

20000

30000

005025

R51

030002

000000
MR-5464

Figure 7-10

CLR (R5)+

7-8

Symbolic

Octal Code

Instruction
Name

CLRB (R5)+

105025

Clear byte

Operation
The contents of R5 are used as the address of the
operand. The selected byte operand is cleared, and
the contents of RS are then incremented by one.

BEFORE

AFTER

ADDRESS SPACE

20000

105025

111

30000

030000

ADDRESS SPACE

20000

105025

030001

•

~ffi

116

30002

MR-5465

Figure 7-11

Symbolic

CLRB (RS)+

Instruction
Name

Octal Code

ADD (R2) + ,R4 062204

Operation
The contents of R2 are used as the address of the
operand that is added to the contents of R4. R2 is
then incremented by two.

Add

BEFORE

AFTER

ADDRESS SPACE

10000

062204

ADDRESS SPACES

1000021

'--_.--~

10000

062204

010000

1000021

REGISTERS
R2

100004

R41

020000

010000
MR-5470

Figure 7-12

ADD (R2)+,R4

7-9

7.2.3.3 Autodecrement Mode (Mode 4) - Autodecrement mode is useful for processing data in a list in
reverse direction. The contents of the selected general-purpose register are decremented (by two for
word instructions, by one for byte instructions) and then used as the address of the operand. The choice
of postincrement, predecrement features for the SBC-ll/21 are not arbitrary; they are intended to facilitate hardware/software stack operations. The assembler interprets and assembles instructions in the
following form as autodecremeQt mode operations.
OPR -(Rn)

Autodecrement Mode Examples (Figures 7-13, 7-14, and 7-15)

Symbolic

Octal Code

Instruction
Name

INC -(RO)

005240

Increment

Operation
The contents of RO are decremented by two and
used as the address of the operand. The operand is
incremented by one.

BEFORE

AFTER

ADDRESS SPACE

1000

17774

005240

REGISTERS

ADDRESS SPACE

017776

1000

000000

17774

I
I

005240

RO '--_,.....----'

000001
MR-5466

Figure 7-13

Symbolic

Octal Code

Instruction
Name

INCB -(RO)

105240

Increment byte

INC -(RO)

Operation
The contents of RO are decremented by one and
used as the address of the operand. The operand is
incremented by one.

7-10

BEFORE

AFTER

ADDRESS SPACE

1000

·105240

ADDRESS SPACE

017776

1000

105240

017775

I
17774E8

17774

17776

001 I 000

MA-5471

Figure 7-14

INCB -(RO)

Operation

Symbolic

Octal Code

Instruction
Name

ADD -(R3),RO

064300

Add

The contents of R3 are decremented by two and
then used as a pointer to an operand (source)
which is added to the contents of RO (destination
operand).

BEFORE

AFTER
REGISTER

ADDRESS SPACE

10020

064300

000020

R31

077776

ADDRESS SPACE

10020

064300

000070

R31

077774

·6

77774~

77774

77776

c==J
Figure 7-15

000050

ADD -(R3),RO

7.2.3.4 Index Mode (Mode 6) - With index mode, the contents of the selected general-purpose register and an index word following the instruction word are summed to form the address of the operand.
The contents of the selected register may be used as a base for calculating a series of addresses, thus
allowing random access to elements of data structures. The selected register can then be modified by
the program to access data in the table. Index addressing instructions are in the following form:
OPR X(Rn)

where X is the indexed word and is located in the memory location following the instruction word, and
Rn is the selected general-purpose register.
7-11

Index Mode Examples (Figures 7-16, 7-17, and 7-18)

Symbolic

Octal Code

CLR 200(R4)

005064
000200

Instruction
Name

005064

1022

000200

1024

+
1200
1202

The address of the operand is determined by adding 200 to the contents of R4. The operand location is cleared.

Clear

BEFORE
ADDRESS SPACE
1020

Operation

AFTER
ADDRESS SPACE

1000
+200
1200

Octal Code

COMB 200(Rl) 105161
000200

005064

1022

000200

001000

1024

1200

Figure 7-16

Symbolic

1020

MA·5473

CLR 200(R4)

Instruction
Name

Operation

Complement byte

7-12

The contents of a location that is determined by
adding 200 to the contents of Rl are one's complemented (i.e., logically complemented).

AFTER
ADDRESS SPACE

BEFORE
REGISTER
ADDRESS SPACE
1020

105161

1022

000200

20176
20200

017777

1020

105161

1022

000200

20176
20200

Figure 7-17

Symbolic

Octal Code

ADD 30(R2),20(R5)

066265
000030
000020

ffi

The contents of a location that is determined by
adding 30 to the contents of R2 are added to the
contents of a location that is determined by adding
20 to the contents of R5. The result is stored at the
destination address, i.e., 20(R5).

AFTER

000030

1024

000020

1130

2020

066265

1022

000030

1024

000020

000001

1130

000001

2020

000002

001100

ADDRESS SPACE
1020

1100
+30
1130

MR-7230

Operation

BEFORE

1022

017777

COMB 200(Rl)

Instruction
Name
Add

ADDRESS SPACE
066265

017777
+200
020177

IO~, ! ~ I

1020

002000

001100

002000

2000
+20
2020
MA-5475

Figure 7-18

ADD 30(R2),20(R5)

7-13

7.2.4 Deferred (Indirect) Addressing
The four basic modes may also be used with deferred addressing. In the register mode, the operand is
the content of the selected register; in the register deferred mode, the content of the selected register is
the address of the operand. In the three other deferred modes, the contents of the register select the
address of the operand rather than the operand itself. Therefore, these modes are used when a table
consists of addresses rather than operands. Assembler syntax for indicating deferred addressing is '@'
(or '0' when this is not ambiguous). Table 7-3 summarizes the deferred versions of the basic modes.
Figures 7-19, 7-20, 7-21, and 7-22, which follow the table, illustrate these deferred versions of the basic
modes.

Table 7-3 Indirect Addressing Modes

Mode

Name

Assembler
Syntax

Function

@Rn or (Rn)

Autoincrement deferred

@(Rn)+

Register is first used as a pointer to a word containing the address of the operand and then incremented (always by two, even for byte
instructions ).

Autodecrement deferred

@-(Rn)

Register is decremented (always by two, even for
byte instructions) and then used as a pointer to a
word containing the address of the operand.

Index deferred

@X(Rn)

Value X (stored in a word following the instruction) and (Rn) are added, and the sum is used as a
pointer to a word containing the address of the
operand. Neither X nor (Rn) is modified.

INSTRUCTION

ADDRESS

OPERAND
MR-5476

Figure 7-19

INSTRUCTION

Mode 1 Register Deferred

ADDRESS

OPERAND

MR-5477

Figure 7-20

Mode 3 Autoincrement Deferred

7-14

-2

INSTRUCTION

Figure 7-21

INSTRUCTION

ADDRESS

OPERAND

Mode 5 Autodecrement Deferred

ADDRESS
OPERAND

ADDRESS

Figure 7-22

Mode 7 Index Deferred

Symbolic

Octal Code

Instruction
Name

CLR@R5

005015

Clear

Operation
The contents of the location specified in R5 are
cleared.

BEFORE
ADDRESS SPACE

1677

1700

AFTER
REGISTER

001700

ADDRESS SPACE

1677

1700

Figure 7-23

001700

MA-6480

CLR @R5

Autoincrement Deferred Mode Example - Mode 3 (Figure 7-24)

Symbolic

Octal Code

Instruction
Name

INC @(R2)+

005232

Increment

Operation
The contents of R2 are used as the address of the
address of the operand. The operand is increased
by one; and the contents of R2 are incremented by
two.

7-15

1010
1012

BEFORE
ADDRESS SPACE
REGISTER

AFTER
ADDRESS SPACE

§g

R2
1010
1012

10300

010302

Ej
MR-7231

Figure 7-24

INC @(R2)+

Autodecrement Deferred Mode Example - Mode 5 (Figure 7-25)

Symbolic

Octal Code

Instruction
Name

COM @-(RO)

005150

Complement

Operation
The contents of RO are decremented by two and
then used as the address of the address of the operand. Operand is one's complemented (i.e., logically complemented).

AFTER
ADDRESS SPACE

10100

10102

10774

10776

MR-7232

Figure 7-25

COM @ -(RO)

7-16

Index Deferred Mode Example - Mode 7 (Figure 7-26)

Symbolic

Octal Code

ADD @1000(R2),Rl

067201
001000

Instruction
Name

Operation

Add

1000 and the contents of R2 are summed to produce the address of the address of the source operand. The contents of the source operand are
added to the contents of R 1; the result is stored in
Rl.

BEFORE
ADDRESS SPACE
1020

067201

1022

001000

AFTER
REGISTER

001234

000100

1024

1050

I
I

1020

067201

1022

001000

R2
1024

1050

1100

ADDRESS SPACE

1100
1000
+100
1100

I
I

001236

000100

B
MR-5483

Figure 7-26

ADD @1000(R2),Rl

7.2.5 Use of the PC as a General-Purpose Register
Although R7 is a general-purpose register, it doubles as the program counter for the microprocessor.
Whenever the processor uses the program counter to acquire a word from memory, the program
counter is automatically incremented by two to contain the address of the next word of the instruction
being executed or the address of the next instruction to be executed. (When the program uses the PC to
locate byte data, the PC is still incremented by two.)

The PC responds to all standard SBC-ll/21 addressing modes. However, the PC provides advantages
for handling position independent code and unstructured data with four of these modes. When utilizing
the PC, these modes are termed immediate, absolute (or immediate deferred), relative, and relative
deferred. Table 7-4 provides a summary of these modes.

7-17

Table 7-4 Register Addressing Modes

Mode

Name

Assembler
Syntax

Function

Immediate

Operand follows the instruction.

Absolute

@#A

Absolute address of operand follows the
instruction.

Relative

Relative address (index value) follows the
instruction.

Relative deferred

Index value (stored in the word following the instruction) is the relative address for the address
of the operand.

When a standard program is available to different users, the ability to load it into different areas of
memory and run it there is useful. The SBC-ll/21 can relocate a program efficiently using position
independent code (PIC) that is written using the PC addressing modes. If an instruction and its operands are moved so that the relative distance between them is not altered, the same offset relative to the
PC can be used in all positions in memory. Thus, PIC usually references locations relative to the current location.
The PC also facilitates the handling of unstructured data. This is particularly true of the immediate and
relative modes.
7.2.S.1 Immediate Mode - Using the immediate mode is equivalent to using the auto increment mode
with the PC. It provides time improvements for accessing constant operands by including the constant
in the memory location immediately following the instruction word. The assembler interprets and assembles instructions in the following form as immediate mode operations.

OPR #n,DD

7-18

Immediate Mode Example (Figure 7-27)

Symbolic

Octal Code

ADD #10,RO

062700
000010

Instruction
Name

Operation

Add

The value lOis located in the second word of the
instruction and is added to the contents of RO. Just
before this instruction is fetched and executed, the
PC points to the first word of the instruction. The
processor fetches the first word and increments the
PC by two. The source operand mode is 27 (autoincrement the PC). Thus, the PC is used as a
pointer to fetch the operand (the second word of
the instruction) before being incremented by two
to point to the next instruction.

BEFORE
ADDRESS SPACE

AFTER
REGISTER

1020

062700

1022

000010

ADDRESS SPACE

000020

1020

001020

1022

1024

062700

1--0_0_00_1_0--l/PC

I
I

000030
001024

1024
MR-7233

Figure 7-27

ADD #10,RO

7.2.5.2 Absolute Addressing - Using the absolute addressing mode is the equivalent of using the immediate deferred or autoincrement deferred modes with the PC. The contents of the location following
the instruction are taken as the address of the operand. Immediate data is interpreted as an absolute
address (i.e., an address that remains constant no matter where in memory the assembled instruction is
executed). The assembler interprets and assembles instructions in the following form as absolute addressing mode operations.
OPR@#A
Absolute Mode Examples (Figures 7-28 and 7-29)

Symbolic

Octal Code

CLR @#1100

005037
001100

Instruction
Name

Operation

Clear

The contents of location 1100 are cleared.

7-19

AFTER

BEFORE

ADDRESS SPACE

ADDRESS SPACE
20

005037

001100

005037

001100

1100
1102

t=3

Symbolic

Octal Code

ADD @#2000,R3

063703
002000

063703

002000

t=j

1100
1102

MA-5485

Figure 7-28

CLR@#1100

Instruction
Name

Operation

Add

The contents of location 2000 are added to R3.

AFTER
ADDRESS SPACE

BEFORE
ADDRESS SPACE
REGISTER
20

R3
PC

I
I

000500

063703

000020

002000

I
I

001000
000024

• t=j

2000

Figure 7-29

ADD @#2000,R3

7.2.5.3 Relative Addressing - The relative addressing mode is assembled as index mode using R7. The
base of the address calculation, which is stored in the second or third word of the instruction, is not the
address of the operand, but the number that, when added to the PC, becomes the address of the operand. This mode is useful for writing position independent code because the location referenced is always
fixed relative to the PC. When instructions are to be relocated, the operand is moved by the same
amount. The assembler interprets and assembles instructions in the following forms as relative addressing mode operations.
OPR A or OPR X(PC)
where X is the location of A relative to the instruction.
7-20

Relative Addressing Example (Figure 7-30)

Symbolic

Octal Code

INCA

005267
000054

Instruction
Name

Operation

Increment

To increment location A, contents of memory location immediately following instruction word are
added to (PC) to produce address A. Contents of
A are increased by one.

BEFORE

AFTER

ADDRESS SPACE

1020

005267

1022

000054

ADDRESS SPACE

1020

0005267

1022

000054

1024

1026

1100

000000

1024
+54
1100

1100

000001

MR·5487

Figure 7-30

INCA

7.2.5.4 Relative Deferred Addressing - The relative deferred addressing mode is similar to the relative
mode. However, the second word of the instruction, when added to the PC, contains the address of the
address of the operand rather than the address of the operand. The assembler interprets and assembles·
instructions in the following forms as relative deferred addressing mode operations.
OPR @A or OPR @X(PC)

where X is the location containing the address of A relative to the instruction.
Relative Deferred Mode Example (Figure 7-31)

Symbolic

Octal Code

CLR@A

005077
000020

Instruction
Name

Operation

Clear

The second word of instruction is added to updated PC to produce address of address of operand. The operand is cleared.

7-21

AFTER
ADDRESS SPACE

BEFORE
ADDRESS SPACE

1020

005077

000020 ~

1022

1024
+20
1044

1024

•
'~
10100

100001

1020

005077

1022

000020

1024

1044

010100

10100

000000
MR-7235

Figure 7-31

CLR@A

7.2.6 Use of the Stack Pointer as a General-Purpose Register
The processor stack pointer (SP, register R6) is the general-purpose register most often used for stack
operations related to program nesting. Autodecrement with register R6 pushes data onto the stack, and
autoincrement with register R6 pops data off the stack. Since the SP is used by the processor for interrupt handling, it has a special attribute: autoincrements and autodecrements are always done in steps of
two. Byte operations using the SP in this way leave odd addresses unmodified.

7.3 INSTRUCTION SET
Specifications for each instruction in the SBC-l1/21 instruction set follow and include each instruction's mnemonic, octal code, binary code, a diagram showing the format of the instruction, a symbolic
notation describing its execution and effect on the condition codes, a description, special comments, and
examples.
MNEMONIC: A mnemonic is indicated before each description. When the word instruction has a byte
equivalent, the byte mnemonic is also shown.
INSTRUCTION FORMAT: A diagram accompanying each instruction shows the octal op code, binary op code, and bit assignments. In byte instructions, the most significant bit (bit 15) is always a one.
SYMBOLS: The following symbols are used in the instruction specifications.

= contents of

SS or src

= source address

DD or dst = destination address
loc

= location

<--

= becomes

= "is popped from stack"

= "is pushed onto stack"

7-22

SYMBOLS (Cont) :
1\

= boolean AND

= boolean OR

\;f

exclusive OR

= boolean not
Reg or R

= register

= Byte

o for word

•

1 for byte

= concatenated
7.3.1 Instruction Formats
The following formats include all instructions used in the SBC-ll /21. Refer to individual instructions
for more detailed information.
1.

Single operand group:

CLR, CLRB, COM, COMB, INC, INCB, DEC, DECB, NEG,
NEGB, ADC, ADCB, SBC, SBCB, TST, TSTB, ROR, RORB,
ROL, ROLB, ASR, ASRB, ASL, ASLB, JMP, SWAB, MFPS,
MTPS, SXT, XOR
06

MR-5191

Double operand group:

BIT, BITB, BIC, BICB, BIS, BISB, ADD, SUB, MOV, MOVB,
CMP, CMPB
06

:
MR-5192

7-23

Program control group:
a.

Branch (all branch instructions)
08

15
OP

C~DE

OF~SET
MA·5193

Jump to subroutine (JSR)

15
0

: 4

: : D~

:
MA-5194

Subroutine return (RTS)
15

R:
MR-5195

Traps (breakpoint, lOT, EMT, TRAP, BPT)
00

15
OP

C~DE
MR-5196

Subtract 1 and branch if = 0 (SOB)
09

15
0

N~
MR-5197

7-24

Operate group:

HALT, WAIT, RTI, RESET, RTT, NOP, MFPT
00

MR-5198

Condition code operators: (all condition code instructions)
06

MR-5199

Byte Instructions - The SBC-11/21 includes a full complement of instructions that manipulate byte
operands. Because all microprocessor addressing is byte-oriented, byte manipulation addressing is
straightforward. Byte instructions with autoincrement or autodecrement direct addressing cause the
specified register to be modified by one to point to the next byte of data. Byte operations in register
mode access the low-order byte of the specified register. These provisions enable the SBC-1l/21 to
perform as either a word or byte microprocessor. The numbering scheme for word and byte addresses in
memory is illustrated in Figure 7-32.
WORD OR BYTE
ADDRESS

HIGH BYTE
ADDRESS

002001

BYTE 1

BYTE 0

002000

002003

BYTE 3

BYTE 2

002002

MA-5201

Figure 7-32

Byte Instructions

7-25

The most significant bit (bit IS) of the instruction word is set to indicate a byte instruction.
Byte Instruction Example
Symbolic

Octal Code

Instruction Name

CLR
CLRB

OOSODD
10S0DD

Clear word
Clear byte

7.3.2 List of Instructions
The SBC-ll/21 instruction set is shown in Table 7-S.
Table 7-5 SBC-H/2l Instruction Set
Instruction

OpCode

General
CLR(B)
COM(B)
INC(B)
DEC(B)
NEG(B)
TST(B)

Clear destination
Complement destination
Increment destination
Decrement destination.
Negate destination
Test destination

.OSODD
.OSlDD
.OS2DD
.OS3DD
.OS4DD
.OS7DD

Shift & Rotate
ASR(B)
ASL(B)
ROR(B)
ROL(B)
SWAB

Arithmetic shift right
Arithmetic shift left
Rotate right
Rotate left
Swap bytes

.062DD
.063DD
.060DD
.061DD
0OO3DD

Multiple Precision
ADC(B)
SBC(B)
SXT

Add carry
Subtract carry
Sign extend

.OSSDD
.OS6DD
0067DD

PS Word Operators
MFPS
MTPS

Move byte from PS
Move byte to PS

1067DD
1064SS

Move source to destination
Compare source to destination
Add source to destination
Subtract source from destination

.1SSDD
.2SSDD
06SSDD
16SSDD

Mnemonic
SINGLE OPERAND

DOUBLE OPERAND
General
MOV(B)
CMP(B)
ADD
SUB

7-26

Table 7-5 SBC-H/21 Instruction Set (Cont)
Mnemonic

Instruction

OpCode

Logical
BIT{B)
BIC(B)
BIS(B)
XOR

Bit test
Bit clear
Bit set
Exclusive OR

.3SSDD
.4SSDD
.5SSDD
074RDD

Branch (unconditional)
Branch if not equal (to zero)
Branch if equal (to zero)
Branch if plus
Branch if minus
Branch if overflow is clear
Branch if overflow is set
Branch if carry is clear
Branch if carry is set

000400
001000
001400
100000
100400
102000
102400
103000
103400

PROGRAM CONTROL
Branch
BR
BNE
BEQ
BPL
BMI
BVC
BVS
BCC
BCS

Signed Conditional Branch
BGE
Branch if greater than or equal (to zero)
BLT
Branch if less than (zero)
BGT
Branch if greater than (zero)
BLE
Branch if less than or equal (to zero)

002000
002400
003000
003400

Unsigned Conditional Branch
BHI
Branch if higher
BLOS
Branch if lower or same
BHIS
Branch if higher or same
BLO
Branch if lower

101000
101400
103000
103400

Jump & Subroutine
JMP
JSR
RTS
SOB

Jump
Jump to subroutine
Return from subroutine
Subtract one and branch (if =1= 0)

0001DD
004RDD
00020R
077ROO

Trap & Interrupt
EMT
TRAP
BPT
lOT
RTI
RTT

Emulator trap
Trap
Breakpoint trap
Input/output trap
Return from interrupt
Return from interrupt

104000-104377
104400-104777
000003
000004
000002
000006

7-27

Table 7-5 SHC-H/21 Instruction Set (Cont)
Mnemonic

Instruction

OpCode

Halt
Wait for interrupt
Reset external bus
Move processor type

000000
000001
000005
000007

MISCELLANEOUS
HALT
WAIT
RESET
MFPT

RESERVED INSTRUCTIONS

00021R
00022R
CONDITION CODE OPERATORS
CLC
CLV
CLZ
CLN
CCC
SEC
SEV
SEZ
SEN
SCC
NOP

000241
000242
000244
000250
000257
000261
000262
000264
000270
000277
000240

Clear C
Clear V
Clear Z
ClearN
Clear all CC bits
Set C
Set V
Set Z
SetN
Set all CC bits
No operation

7.3.3 Single Operand Instructions .
NOTE
In most SHC-H/21 instructions, a write operation
to a memory location or register is always preceded
by a read operation from the same location except
when writing PC and processor status (PS) to the
stack in the following two cases.
1.

The execution of the microcode preceding an
interrupt or trap service routine.

Interrupt and trap instructions:
HLT
TRAP
HPT
lOT

7-28

7.3.3.1

General-

CLR
CLRB
Clear Destination
06

MA·5202

Operation:

(dst) r - 0

Condition Codes:

N: cleared
Z: set
V: cleared
C: cleared

Description:

Word: Contents of specified destination are replaced with zeros.
Byte: Same

CLRRI

Example:
Before
(Rl) = 177777

After
(Rl) = 000000

NZVC
1 1 1 1

o 100

NZVC

COM
COMB

1105100

Complement Destination
15

0/< a : a : a : 1 : a : 1 : 0 : a : 1 I d : d : d : d : d

00
d
MR-5203

Operation:

(dst) r - -

Condition Codes:

N: set if most significant bit of result is set; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared
C: set

(dst)

7-29

Description:

Word: The contents of the destination address are replaced by their logical complement (each bit equal to zero is set, and each bit equal to one is cleared).
Byte: Same

Example:

COMRO
Before
(RO) = 013333

After
(RO) = 164444

NZVC

o1 10

100 1

INC
INCH
Increment Destination
15

0/<

06
0

05
d

00
:

d
MR-5204

Operation:

(dst) +- (dst) + 1

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if (dst) held 077777; cleared otherwise
C: not affected

Description:

Word: One is added to contents of destination.
Byte: Same

Example:

INC R2
Before
(R2) = 000333

NZVC

After
(R2) = 000334

NZVC

o0 0 0

7-30

DEC
DECB

Decrement Destination

MR-5205

Operation:

(dst) +- (dst) -1

Condition Codes:

N: set if result < 0, cleared otherwise
Z: set is result = 0; cleared otherwise
V: set if (dst) was 100000; cleared otherwise
C: not affected

Description:

Word: One is subtracted from the contents of the destination.
Byte: Same

Example:

DECRS
Before
(RS) = 000001

After
(RS) = 000000

NZVC

o10 0

1 000

NEG
NEGB
Negate Destination
06

0/< 0 : 0': 0 : 1 : 0 : 1 : 1 : 0
MR.5206

Operation:

(dst) +- - (dst)

Condition Codes:

N: set if the result < 0; cleared otherwise
Z:- set if the result = 0; cleared otherwise
V: set if the result is 100000; cleared otherwise
C: cleared if the result is 0; set otherwise

Description:

Word: The contents of the destination address are replaced by its two's complement. 100000 is replaced by itself (in two's complement notation, the
most negative number has no positive counterpart).
Byte: Same

7-31

Example:

NEGRO
Before
(RO) = 000010

After
(RO) = 177770

NZVC

000 0

100 1

TST
TSTB
Test Destination
06

0/1 : 0: 0: 0: 1 : 0:
MR-5207

Operation:

(dst) +- (dst)

Condition Codes:

N: set if the result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared
C: cleared

Description:

Word: The condition codes Nand Z are set according to the contents of the destination address, and the contents of the destination remain unmodified.
Byte: Same

Example:

TST Rl
Before
CRt) = 012340

NZVC

o0 1 1
7.3.3.2
1.
2.

After
(Rt) = 012340

000 0

Sbifts and Rotates - Scaling data by factors of two is accomplished with two shift instructions:
ASR - Arithmetic shift right
ASL - Arithmetic shift left

The sign bit (bit 15) of the operand is reproduced in shifts to the right. The low-order bit is filled with
zero in shifts to the left. Bits shifted out of the C-bit, as shown in the following examples, are lost.
The rotate instructions operate on the destination word and the C-bit as though they formed a 17-bit
circular buffer. These instructions facilitate sequential bit testing and detailed bit manipulation.

7-32

ASR
ASRB

Arithmetic Shift Right
06

0/<

1
MR·5208

Operation:

(dst) -- (dst) shifted one place to the right

Condition Codes:

N: set if the high-order bit of the result is set (result < 0); cleared otherwise
Z: set if the result = 0; cleared otherwise
V: loaded from the exclusive OR of the N-bit and C-bit (as set by the completion
of the shift operation)
C: loaded from the low-order bit of the destination

Description:

Word: All bits of the destination are shifted right one place. Bit 15 is reproduced.
The C-bit is loaded from bit 0 of the destination. ASR performs signed division of the destination by two.
Byte: Same

Example:
WORD:

BYTE:

__ __

~~5~: ~ ~OrD_D_A~D_DR_E_SSr-~__~:~0~'~~~7~:r-~

___

1--c=J-

:~EV~E~N~:~DD~R~ET:S~~__~0~0~1~
MR 7236

7-33

ASL
ASLB
Arithmetic Shift Left
00

0/<

1
MR-5210

Operation:

(dst) +- (dst) shifted one place to the left

Condition Codes:

N: set if the high-order bit of the result is set (result < 0); cleared otherwise
Z: set if the result = 0; cleared otherwise
V: loaded with the exclusive OR of the N-bit and C-bit (as set by the completion
of the shift operation)
C: loaded with the high-order bit of the destination

Description:

Word: All bits of the destination are shifted left one place. Bit 0 is loaded with a
zero. The C-bit of the status word is loaded from the most significant bit of
the destination. ASL performs signed multiplication of the destination by
two with overflow indication.
Byte: Same

Example:
WORD:

BYTE:

MR·5211

7-34

ROR
RORB

Rotate Right

MR·5212

Operation:

(dst) ;- (dst) rotate right one place

Condition Codes:

N: set if the high-order bit of the result is set (result < 0); cleared otherwise
Z: set if all bits of result = 0; cleared otherwise
V: loaded with the exclusive OR of the N-bit and C-bit (as set by the completion
of the rotate operation)
C: loaded with the low-order bit of the destination

Description:

Word: All bits of the destination are rotated right one place. Bit 0 is loaded into
the C-bit, and the previous contents of the C-bit are loaded into bit 15 of
the destination.
Byte: Same

Example:
WORD:

BYTE:

+~--------~~~--------~
15

~
00

I I

EV:EN
MR-5213

7-35

ROL
ROLB
Rotate Left
06

0/1: 0
MR·5214

Operation:

(dst) ;- (dst) rotate left one place

Condition Codes:

N: set if the high-order bit of the result word is set (result < 0); cleared otherwise
Z: set if all bits of the result word = 0; cleared otherwise
V: loaded with the exclusive. OR of the N-bit and C-bit (as set by the completion
of the rotate operation)
C: loaded with the high-order bit of the destination

Description:

Word: All bits of the destination are rotated left one place. Bit 15 is loaded into
the C-bit of the status word, and the previous contents of the C-bit are
loaded into bit 0 of the destination.
Byte: Same

Example:
WORD:

DST

~~I__~~~~~~~
BYTE:

~---"8t------,
15

)

E~EN

MR-5215

SWAB

Swap Bytes

000300
06

MR-5216

7-36

Operation:

Byte IIByte 0 ;- Byte OIByte 1

Condition Codes:

N: set if the high-order bit of the low-order byte (bit 7) of the result is set; cleared
otherwise
Z: set if low-order byte of result = 0; cleared otherwise
V: cleared
C: cleared

Description:

High-order byte and low-order byte of the destination word are exchanged (destination must be a word address).

Example:

SWAB R1
Before
(R1) = 077777

After
(Rl) = 177577

NZVC
I I 1 1

NZVC

o0 0 0

7.3.3.3 Multiple Precision -It is sometimes necessary to do arithmetic on operands considered as multiple words or bytes. The SBC-ll 121 makes special provisions for such operations with the instructions
ADC (add carry) and SBC (subtract carry) and their byte equivalents. For example, two 16-bit words
may be combined into a 32-bit double precision word and added or subtracted as shown in Figure 7-33.

32-BITWORD

(
31

OPERANDI

1
0

r------------------------------------------------------------------,1

(

OPERANDI~

________
B1_ _ _ _ _ _ _

r15~

_________________________...,O

LI_ _ _ _ _ _ _ _ _B_O___________

;.: . .- ------;1
15

---~II

RESULTI;;"';"'--

MR·5217

Figure 7-33

Multiple Precision

7-37

Multiple Precision Example
The addition of - 1 and - 1 could be performed as follows:
-1 = 37777777777
(Rl) = 177777 (R2) = 177777 (R3) = 177777 (R4) = 177777
ADD RI,R2
ADCR3
ADD R4,R3
1.

2.
3.
4.

After (Rl) and (R2) are added, 1 is loaded into the C-bit
ADC instruction adds C-bit to (R3); (R3) = 0
(R3) and (R4) are added
Result is 37777777776 or - 2

ADC
ADCH
Add Carry
15

0/<

06
0

05
d

00
:

MR-5218

Operation:

(dst) +- (dst) + (C-bit)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if (dst) was 077777 and (C) was 1; cleared otherwise
C: set if (dst) was 177777 and (C) was 1; cleared otherwise

Description:

Word: The contents of the C-bit are added into the destination. This permits the
carry from the addition of the low-order words to be carried into the highorder result.
Byte: Same

Example:

Double precision addition is done with the following instruction sequence:
ADD AO,BO
ADC BI
ADD AI,BI

add low-order parts
add carry into high order
add high-order parts

SHe
SHeH
Subtract Carry

7-38

Operation:

(dst) (- (dst) - (C)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if (dst) was 100000; cleared otherwise
C: set if (dst) was 0 and C was 1; cleared otherwise

Description:

Word: The contents of the C-bit are subtracted from the destination. This permits
the carry from the subtraction of two low-order words to be subtracted
from the high-order part of the result.
Byte: Same

Example:

Double precision subtraction is done with the following instruction sequence:
SUB AO,BO
SBC Bl
SUB AI,Bl

SXT
. Sign Extend

0067DD
06

o : o : o : o :

1 :

o :

1 :

d :

MR·5220

Operation:

(dst) (- 0 if N-bit is clear
(dst) (- 1 if N-bit is set

Condition Codes:

N : unaffected
Z: set if N-bit is clear
V: cleared
C: unaffected

Description:

If the condition code bit N is set, a -1 is placed in the destination operand; if the
N-bit is clear, then a zero is placed in the destination operand. This instruction is
particularly useful in multiple precision arithmetic because it permits the sign to
be extended through multiple words.

Example:

SXTA
Before
(A) = 012345

After
(A) = 177777

NZVC
1 000

7-39

7.3.3.4 PS Word Operators -

MFPS
Move Byte from Processor Status (PS)

106700

15
11

: 0

00
:

: d

: d
MR-5221

Operation:

(dst) - PS
dst lower 8 bits

Condition Codes:

N: set if PS bit 7 = 1; cleared otherwise
Z: set if PS <0:7> = 0; cleared otherwise
V: cleared
C: not affected

Description:

The 8-bit contents of the PS are moved to the effective destination. If the destination is mode 0, PS bit 7 is sign extended through the upper byte of the register.
The destination operand address is treated as a byte address.
MFPSRO

Example:
Before
RO [0]
PS [000014]

After
RO [000014]
PS [000000]

MTPS
Move Byte to Processor Status

1064SS

1
: : : : I
1

: 0

: s

: s
MR-5222

Operation:

PS - (src)

Condition Codes:

Set according to effective source operand bits 0-3

Description:

The 8 bits of the effective operand replace the current contents of the PS. The
source operand address is treated as a byte address. The T-bit (PS bit 4) cannot be
set with this instruction. The source operand remains unchanged. This instruction
can be used to change the priority bits (PS bits 7-5) in the PS.

7-40

7.3.4 Double Operand Instructions
Double operand instructions save instructions and time because they eliminate the need for load and
save sequences such as those used in accumulator-oriented machines.
7.3.4.1

General-

MOV
MOVB

Move Source to Destination
15

MR-5223

Operation:

(dst) +- (src)

Condition Codes:

N: set if (src) < 0; cleared otherwise
Z: set if (src) = 0; cleared otherwise
V: cleared
C: not affected

Description:

Word: The source operand is moved to the destination location. The previous contents of the destination are lost. The contents of the source address are not
affected.
Byte: Same as .MOV. The MOVB to a register (unique among byte instructions)
extends the most significant bit of the low-order byte (sign extension). Otherwise, MOVB operates on bytes exactly as MOV operates on words.

Example:

MOVXXX,Rl

loads register 1 with the contents of memory location; XXX represents a programmer-defined mnemonic used to represent a memory location

MOV #20,RO

loads the number 20 into register 0; '#' indicates
that the value 20 is the operand

MOV @#20,-(R6)

pushes the operand contained in location 20 onto
the stack

MOV (R6)+,@#177566

pops the operand off a stack and moves it into
memory location 177566 (terminal print buffer)

MOV Rl,R3

performs an inter-register transfer

MOVB @#177562,@#177566

moves a character from terminal keyboard buffer
to terminal printer buffer

7-41

CMP
CMPB

Compare Source to Destination
15

0/1: 0
MA·5224

Operation:

(src) - (dst)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if there was arithmetic overflow; that is, operands were of opposite signs
and the sign of the destination was the same as the sign of the result; cleared
otherwise
C: cleared if there was a carry from the most significant bit of the result; set otherwise

Description:

Word: The source and destination operands are compared, and the condition
codes are set. The condition codes may then be used for arithmetic and
logical conditional branches. Both operands are unaffected. The only action is to set the condition codes. The compare is customarily followed by a
conditional branch instruction. Unlike the subtract instruction, the order of
operation is (src) - (dst), not (dst) - (src).
Byte: Same

ADD

Add Source to Destination
12

06SSDD
06

MR·5226

Operation:

(dst) -- (src) + (dst)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if there was arithmetic overflow as a result of the operation; that is, both
operands were of the same sign and the result was of the opposite sign; cleared
otherwise
C: set if there was a carry from the most significant bit of the result; cleared otherwise

7-42

Description:

Word: The source operand is added to the destination operand and the result is
stored at the destination address. The original contents of the destination
are lost. The contents of the source are not affected. Two's complement
addition is performed.
Byte: There is no equivalent byte mode.

Example:

ADD 20,RO
ADD R1,XXX
ADD R1,R2
ADD @#17750,XXX

add to register
add to memory
add register to register
add memory to memory

XXX is a programmer-defined mnemonic for a memory location.

SUB
16SSDD

Subtract Source from Destination
12

MR-5226

Operation:

(dst) +- (dst) - (src)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if there was arithmetic overflow as a result of the operation, that is if operands were of opposite signs and the sign of the source was the same as the sign
of the result; cleared otherwise
c: cleared if there was a carry from the most significant bit of the result; set otherwise

Description:

Word: The source operand is subtracted from the destination operand, and the result is left at the destination address. The original contents of the destination are lost. The contents of the source are not affected. In double-precision arithmetic, the C-bit, when set, indicates a borrow.
Byte: There is no equivalent byte mode.
SUB Rl,R2

Example:
Before
(R1) = 011111
(R2) = 012345

After
(Rl) = 011111
(R2) = 001234

NZVC

o0 0 0

1 I I I

7-43

7.3.4.2 Logical - Logical group instructions have the same format as the double operand arithmetic
group. They permit operations on data at the bit level.

BIT
BITB

Bit Test
15

MR-5227

Operation:

(src) 1\ (dst)

Condition Codes:

N: set if high-order bit of result is set; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared
C: not affected

Description:

Word: Logical "and" comparison of the source and destination operands is performed, and condition codes are modified accordingly. Neither the source
nor destination is affected. The BIT instruction may be used either to test
whether any of the corresponding bits that are set in the destination are
also set in the source or whether all corresponding bits set in the destination are clear in the source.
Byte: Same

Example:

BIT #30,R3

test bits three and four of R3 to see if both are off

R3 = 0000000000011 000
Before

After

NZVC

1 111

000 1

BIC
BICB

Bit Clear

.4SSDD
15

0/1: 1
MR-5228

7-44

Operation:

(dst) t - (dst) 1\ ,..,., (src)

Condition Codes:

N: set if high-order bit of result is set; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared
C: not affected

Description:

Word: Each bit in the destination that corresponds to a set bit in the source is
cleared. The original contents of the destination are lost. The contents of
the source are not affected.
Byte: Same

Example:

BIC R3,R4
Before
(R3) = 001234
(R4) = 001111

After
(R3) = 001234
(R4) = 000101

NZVC
1 I 1 1

NZVC
000 1

Before:

(R3) = 0000001 010011 100
(R4) = 0000001 001 001 001

After:

(R4) = 0000000001 000001

HIS
HISH
Bit Set
15

Operation:

(dst) t - (dst) V (src)

Condition Codes:

N: set if high-order bit of result is set, cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared
C: not affected

Description:

Word: Inclusive OR operation is performed between the source and destination
operands, and the result is left at the destination address (i.e., corresponding bits set in the source are set in the destination). The contents of the
destination are lost.
Byte: Same

7-45

Example:

BIS RO,R1
Before
(RO) = 001234
(Rl) = 001111

After
(RO) = 001234
(R1) = 001335

NZVC

oaaa

o0 0 0
Before:

(RO) = 0000001010 011 100
(R1) = 0000001 001 001 001

After:

(Rl) = 0000001 011 all 101

XOR

Exclusive OR
15

074RDD
09

Operation:

(dst) +- (dst) 'if (Reg)

Condition Codes:

N: set if the result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared
C: unaffected

Description:

The exclusive OR of the register and destination operand is stored in the destination address. Contents of register are unaffected. Assembler format is: XOR R,D.
XOR RO,R2

Example:
Before
(RO) = 001234
(R2) = 001111

After
(RO) = 001234
(R2) = 000325

NZVC

aaa1

1 1 1 1
Before:

(RO) = 0000001010011 100
(R2) = 0000001 001 001 001

After:

(R2) = 0000000 011 010101

7-46

7.3.5

Program Control Instructions

7.3.5.1 Branches - Program control instructions cause a branch to a location defined by the sum of the
offset (multiplied by two) and the current contents of the program counter if:
1.

The branch instruction is unconditional.

The branch instruction is conditional, and the conditions are met after testing the condition
codes (NZVC).

The offset is the number of words from the current contents of the PC forward or backward. The current contents of the PC point to the word following the branch instruction.
Although the offset expresses a byte address, the PC is expressed in words. Before it is added to the PC,
the offset is automatically multiplied by two and sign extended to express words. Bit 7 is the sign of the
offset. If it is set, the offset is negative and the branch is done in the backward direction. Similarly, if
bit 7 is not set, the offset is positive and the branch is done in the forward direction.
The 8-bit offset allows branching in the backward direction by 2008 words (400 bytes) from the current
PC, and in the forward direction by 1778 words (376 bytes) from the current Pc.
The microprocessor assembler handles address arithmetic for the user and computes and assembles the
proper offset field for branch instructions in the following form.
Bxx loc
where Bxx is the branch instruction and loc is the address to which the branch is to be made. The
assembler gives an error indication in the instruction if the permissible branch range is exceeded.
Branch instructions have no effect on condition codes. Conditional branch instructions, where the
branch condition is not met, are treated as NO OPs.

BR
000400 Plus Offset

Branch (Unconditional)
08

o :

1
MR-5231

Operation:

PC f - - PC + (2 X offset)

Condition Codes:

Unaffected

Description:

A way of transferring program control within a range of -12810 to + 12710 words
with a one-word instruction is provided.
New PC address = updated PC + (2 X offset)
Updated PC = address of branch instruction + 2

7-47

With the branch instruction at location 500, the following offsets apply.

Example:

New PC Address

Offset Code

Offset (decimal)

474
476
500
502
504
506

375
376
377
000
001
002

-3
-2
-1
0
+1
+2

BNE
001000 Plus Offset

Branch If Not Equal (to Zero)
08

o :

I
MR-5232

Operation:

PC +- PC + (2 X offset) if Z = 0

Condition Codes:

Unaffected

Description:

The state of the Z-bit is tested, and a branch is caused if the Z-bit is clear. BNE is
the complementary operation to BEQ. BNE is used to test inequality following a
CMP, to test that some bits set in the destination were also in the source following
a BIT operation, and generally, to test that the result of the previous operation
was not zero.

Example:

CMPA,B
BNEC

compare A and B
branch if they are not equal

will branch to C if A =1= B
and the sequence
ADD A,B
BNEC

add A to B
branch if the result is not equal to 0

will branch to C if A + B =1= 0

7-48

BEQ
Branch If Equal (to Zero)

001400 Plus Offset
08

MR-5233

Operation:

PC ;- PC + (2 X offset) if Z = 1

Condition Codes:

Unaffected

Description:

The state of the Z-bit is tested and a branch is caused if Z is set. BEQ is used to
test equality following a CMP operation, to test that no bits set in the destination
were also set in the source following a BIT operation, and generally, to test that
the result of the previous operation was zero.

Example:

CMPA,B
BEQC

compare A and B
branch if they are equal
(A - B = 0)

will branch to C if A = B
and the sequence
ADD A,B
BEQC

add A to B
branch if the result = 0

will branch to C if A + B = 0

BPL
Branch If Plus

100000 Plus Offset

:o: o: o: o: o: o: oI

OFF:SET
MR-5234

Operation:

PC ;- PC + (2 X offset) if N = 0

Condition Codes:

Unaffected

Description:

The state of the N-bit is tested, and a branch is caused if N is clear (positive result). BPL is the complementary operation of BM!.

7-49

BMI
Branch If Minus

100400 Plus Offset
08

15
1

o : o : o : o : o : o :

OFF~ET
MR·5235

Operation:

PC ~ PC + (2 X offset) if N = 1

Condition Codes:

Unaffected

Description:

The state of the N-bit is tested, and a branch is caused if N is set. BMI is used to
test the sign (most significant bit) of the result of the previous operation, branching if negative. BMI is the complementary function of BPL.

Bve
Branch If Overflow Is Clear

102000 Plus Offset

I
Operation:

PC ~ PC + (2 X offset) if V = 0

Condition Codes:

Unaffected

Description:

The state of the V-bit is tested, and a branch is caused if the V-bit is clear. BVC is
the complementary operation to BVS.

BVS
102400 Plus Offset

Branch If Overflow Is Set
15

o :

00"

1
MR-5237

7-50

Operation:

PC - PC + (2 X offset) if V = 1

Condition Codes:

Unaffected

Description:

The state of the V-bit (overflow) is tested, and a branch is caused if the V-bit is
set. BVS is used to detect arithmetic overflow in the previous operation.

Bee
Branch If Carry Is Clear

103000 Plus Offset
08

15
1 :

o : o : o : o :

1 :

00
OFF:SET
MR-5238

Operation:

PC - PC + (2 X offset) if C = 0

Condition Codes:

Unaffected

Description:

The state of the C-bit is tested, and a branch is caused if C is clear. BCC is the
complementary operation to BCS.

Bes
103400 Plus Offset

Branch If Carry Is Set
08

MR·5239

Operation:

PC - PC + (2 X offset) if C = 1

Condition Codes:

Unaffected

Description:

The state of the C-bit is tested, and a branch is caused if C is set. BCS is used to
test for a carry in the result of a previous operation.

7-51

7.3.S.2 Signed Conditional Branches - Particular combinations of the condition code bits are tested
with the signed conditional branches. These instructions are used to test the results of instructions in
which the operands were considered as signed (two's complement) values.

The sense of signed comparisons differs from unsigned comparisons. In signed 16-bit (two's complement) arithmetic, the sequence of values is as follows.
largest

077777
077776

positive

zero

000001
000000
177777
177776

negative
smallest

100001
100000

In unsigned 16-bit arithmetic, the sequence is as follows.
highest

177777

lowest

000002
000001
000000

BGE
Branch If Greater Than or Equal (to Zero)

002000 Plus Offset
08

MR-5240

7-52

Operation:

PC -- PC + (2 X offset) if N 'V V = 0

Condition Codes:

Unaffected

Description:

A branch is caused if N and V are either both clear or both set. BGE is the complementary operation to BLT. Thus, BGE will always cause a branch when it follows an operation that caused addition of two positive numbers. BGE will also
cause a branch on a zero result.

BLT
Branch If Less Than (Zero)

002400 Plus Offset
08

o :

1
MA-5241

Operation:

PC -- PC + (2 X offset) if N 'V V = 1

Condition Codes:

Unaffected

Description:

A branch is caused if the exclusive OR of the N- and V-bits is one. Thus, BLT will
always branch following an operation that added two negative numbers, even if
overflow occurred. In particular, BLT will always cause a branch if it follows a
CMP instruction operating on a negative source and a positive destination (even if
overflow occurred). Further, BLT will never cause a branch when it follows a
CMP instruction operating on a positive source and negative destination. BLT will
not cause a branch if the result of the previous operation was zero (without overflow).

BGT
003000 Plus Offset

Branch If Greater Than (Zero)
08

o :

0
MA-5242

7-53

Operation:

PC ~ PC + (2 X offset) if Z V (N V V) = 0

Condition Codes:

Unaffected

Description:

Operation of BGT is similar to BGE, however, BGT will not cause a branch on a
zero result.

BLE
Branch If Less Than or Equal (to Zero)

003400 Plus Offset
08

MR-5243

Operation:

PC ~ PC + (2 X offset) if Z V (N V V) = 1

Condition Codes:

Unaffected

Description:

Operation is similar to BLT, however, BLE also will cause a branch if the result of
the previous operation was zero.

7.3.5.3 Unsigned Conditional Branches - The unsigned conditional branches provide a means to test
the results of comparison operations in which the operands are considered unsigned values.

Bill
Branch If Higher

101000 Plus Offset
08

MR·5244

Operation:

PC ~ PC + (2 X offset) if C = 0 and Z = 0

Condition Codes:

Unaffected

Description:

A branch occurs if the previous operation did not cause a carry or a zero result.
This will happen in comparison (CMP) operations as long as the source has a higher unsigned value than the destination.

7-54

BLOS

Branch If Lower or Same

101400 Plus Offset
08

MA-5245

Operation:

PC ~ PC + (2 X offset) if C V Z = 1

Condition Codes:

Unaffected

Description:

A branch occurs if the previous operation caused either a carry or a zero result.
BLOS is the complementary operation to BHI. The branch will occur in comparison operations as long as the source is equal to, or has a lower unsigned value
than the destination.

BHIS

Branch If Higher or Same

103000 Plus Offset
08

MR-5246

Operation:

PC ~ PC + (2 X offset) if C = 0

Condition Codes:

Unaffected

Description:

BHIS is the same instruction as BCe. This mnemonic is included for convenience.

BLO

103400 Plus Offset

Branch If Lower
08

7-55

Operation:

PC +- PC + (2 X offset) if C = 1

Condition Codes:

Unaffected

Description:

BLO is the same instruction as BCS. This mnemonic is included for convenience
only.

7.3.5.4 Jump and Subroutine Instructions - The subroutine call in the microprocessor provides for
automatic nesting of subroutines, re-entrance, and multiple entry points. Subroutines may call other
subroutines (or themselves) to any level of nesting without making special provisions for storage of return addresses at each level of subroutine call. The subroutine calling mechanism does not modify any
fixed location in memory, and thus, provides for re-entrance. This allows one copy of a subroutine to be
shared among several interrupting processes.

JMP
Jump

000100
06

o :

00
d

d
MR-5248

Operation:

PC +- (dst)

Condition Codes:

Unaffected

Description:

More flexible program branching than that available with the branch instructions
is provided. Control may be transferred to any location in memory (no range limitation) and can be accomplished with the full flexibility of the addressing modes,
with the exception of register mode O. Execution of a jump with mode 0 will cause
an illegal instruction condition, and will cause the CPU to trap to vector address 4.
(Program control cannot be transferred to a register.) Register deferred mode is
legal and will cause program control to be transferred to the address held in the
specified register. Instructions are word data and therefore, must be fetched from
an even-numbered address.
Deferred index mode JMP instructions permit transfer of control to the address
contained in a selectable element of a table of dispatch vectors.

7-56

Example:
JMP FIRST

transfers to FIRST

JMP @LIST

transfers to location pointed
to at LIST
pointer to FIRST

First:
List:

FIRST
JMP @(SP)+

transfers to location pointed to by the top of the stack and removes the pointer from the stack

JSR

Jump to Subroutine

004RDD
09

MA-5249

Operation:

(tmp) ~ (dst) (tmp is an internal processor register)

1 (SP) ~ reg (push reg contents onto processor stack)
reg ~ PC (PC holds location following JSR; this address is now put in reg)
PC ~ (dst) (PC now points to subroutine destination)
Condition Codes:

Unaffected

Description:

The old contents of the specified register (the linkage pointer) are automatically
pushed onto the processor stack, and new linkage information is placed in the register. Thus, subroutines nested within subroutines to any depth may all be called
with the same linkage register. There is no need either to plan the maximum depth
at which any particular subroutine will be called or to include instructions in each
routine to save and restore the linkage pointer. Further, since all linkages are saved in a re-entrant manner on the processor stack, execution of a subroutine may be
interrupted, and the same subroutine re-entered and executed by an interrupt service routine. Execution of the initial subroutine can then be resumed when other
requests are satisfied. This process (called nesting) can proceed to any level.
A subroutine called with a JSR reg,(dst) instruction can access the arguments following the call with either autoincrement addressing, (reg) +, (if arguments are
accessed sequentially) or by indexed addressing, X(reg), (if arguments are accessed in random order). These addressing modes may also be deferred, @(reg)+
and @X(reg), if the parameters are operand addresses rather than the operands
themselves.
JSR PC,(dst) is a special case of the microprocessor subroutine call and is used
for subroutine calls that transmit parameters through the general-purpose registers. The SP and the PC are the only registers that may be modified by this call.

7-57

JSR PC,@(SP)+ is another special case of the JSR instruction. It exchanges the
top element of the processor stack and the contents of the program counter. This
instruction is used to allow two routines to swap program control and resume operation when recalled where they left off. Such routines are called co-routines.
Return from a subroutine is done with the RTS instruction. RTS reg loads the
contents of reg into the PC and pops the top element of the processor stack into
the specified register.
Example:
R5
SBCALL
SBCALL+4

JSR R5, SBR------.
ARG 1
ARG2

SBCALL + 2 + 2M
CONT

ARGM
NEXT INSTRUCTION

SBR

MOV(R5) + ,dstl +----'
MOV(R5) + ,dst2

R6
n

R7
SBCALL

CONT

SBCALL+4

n-2

SBR

SBCALL + 2 + 2M
CONT
CO NT

n- 2

EXIT

MOV(R5) + ,dst2

EXIT

MOV(R5) + ,dstM
OTHER INSTRUCTIONS
RTSR5

This example is illustrated in Figure 7-34.

7-58

JSR R5, SBR

BEFORE:

STACK

DATA 0

SBR

(PC)

(SP)

AFTER:

DATA 0
R6

n-2

PC+2

JSR PC, SBR
BEFORE:

AFTER:

(PC)

(SP)

STACK

DATA 0

SBR

n-2

DATA 0
PC+2
MA-52S0

Figure 7-34

JSR Example

7-59

RTS
Return from Subroutine

00020R
03

o : o : o : o : o : o : o :

: :

:o : I :
0

00
r

MR-5251

Operation:

PC +- (reg)
(reg) +- (SP) T

Condition Codes:

Unaffected

Description:

Contents of register are loaded into PC, and the top element of the processor stack
is popped into the specified register. Return from a nonre-entrant subroutine is
typically made through the same register that was used in its call. Thus, a subroutine called with a JSR PC,(dst) exits with an RTS PC. A subroutine called
with a JSR RS,(dst) may pick up parameters with addressing modes (RS)+,
X(RS), or @X(RS) and finally exit with an RTS RS.

Example:
RTS R5
BEFORE:

(PC)

STACK

SBR

1
DATA 0

(SP)

I
I

PC _....
1_ _

R5 ...

AFTER:

R7.1

n+2

DATA 0

I
MR-5252

7-60

SOB
077RNN

Subtract One and Branch (If =1= 0)
09

MR-5253

Operation:

(R) +- (R) - 1; if this result =1= 0 then PC +- PC - (2 X offset); if (R) = 0 then
PC +- PC

Condition Codes:

Unaffected

Description:

The register is decremented. If it is not equal to zero, twice the offset is subtracted from the PC (now pointing to the following word). The offset is interpreted as a 6-bit positive number. SOB provides a fast, efficient method of loop
control. The assembler syntax is:
SOB R,A
where A is the address to which transfer is to be made if the decremented R is not
equal to zero. The SOB instruction cannot be used to transfer control in the forward direction.

7.3.5.5 Traps - Trap instructions provide for calls to emulators, I/O monitors, debugging packages,
and user-defined interpreters. A trap is effectively an interrupt generated by software. When a trap
occurs the contents of the current program counter (PC) and processor status (PS) are pushed onto the
processor stack and replaced by the contents of a two-word trap vector containing a new PC and PS.
The return sequence from a trap involves executing an RTI or RTT instruction that restores the old PC
and PS by popping them from the stack. Trap instruction vectors are located at permanently assigned
fixed addresses.

EMT

104000-104377

Emulator Trap
08

a :

1
MR-5254

Operation:

1 (SP) +- PS

1 (SP) +- PC
PC +- (30)
PS +- (32)

7-61

Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

All operation codes from 104000 to 104377 are EMT instructions and may be
used to transmit information to the emulating routine (e.g., function to be perJormed). The trap vector for EMT is at address 30. The new PC is taken from the
word at address 30, and the new processor status (PS) is taken from the word at
address 32.
CAUTION
EMT is used frequently by Digital system software
and is not recommended for general use.

Example:

I
I

PS 1

PC 1

STACK

BEFORE:
SP

AFTER:

I
I

DATA 1

(32)

(30)

DATA 1
PS 1

n-4

I
I

PC 1

MR·5255

TRAP
Trap

104400-104777
00

MA-5256

7-62

1 (SP) ~ PS
1 (SP) ~ PC

Operation:

PC ~ (34)
PS ~ (36)
Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

Operation codes from 104400 to 104777 are TRAP instructions. TRAP and EMT
instructions are identical in operation, however, the trap vector for TRAP is at
address 34.
NOTE
Because Digital software makes frequent use of
EMT, the TRAP instruction is recommended for
general use.

BPT
Breakpoint Trap

000003
00

o :

0 :

1
MA-5257

Operation:

1 (SP) ~ PS

1 (SP) ~ PC
PC ~ (14)
PS ~ (16)

Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

A trap sequence with a trap vector address of 14 is performed. BPT is used to call
debugging aids. The user is cautioned against employing code 000003 in programs
run under these debugging aids.
(No information is transmitted in the low byte.)

7-63

lOT
000004

Input/Output Trap
00

a :

Operation:

a : a

1(SP) -

PS
PC
PC - (20)
PS - (22)

1 (SP) Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

A trap sequence with a trap vector address of 20 is performed.
(No information is transmitted in the low byte.)

RTI

Return from Interrupt

000002
00

MR-5259

Operation:

PC - (SP) T
PS - (SP) T

Condition Codes:

N: loaded from processor stack
Z: loaded from processor stack
V: loaded from processor stack
C: loaded from processor stack

Description:

Used to exit from an interrupt or TRAP service routine. The PC and PS are restored (popped) from the processor stack. If a trace trap is pending, the first instruction after RTI will not be executed prior to the next T trap.

7-64

RTT
Return from Interrupt

000006
00

MA-5260

Operation:

PC <- (SP) T
PS <- (SP) T

Condition Codes:

N: loaded from processor stack
Z: loaded from processor stack
V: loaded from processor stack
C: loaded from processor stack

Description:

Operation is the same as RTI, however, RTT inhibits a trace trap while RTI permits a trace trap. If new PS has T-bit set, trap will occur after execution of first
instruction after RTT.

7.3.5.6 Reserved Instruction Traps - Reserved instruction traps are caused by attempts to execute instruction codes reserved for future processor expansion (reserved instructions) or instructions with illegal addressing modes (illegal instructions). Order codes not corresponding to any of the instructions
described are reserved instructions. JMP and JSR with register mode destinations are illegal instructions and trap to vector address 4. Reserved instructions trap to vector address 10.

HALT Interrupt - The HALT interrupt is caused by the -HALT line. The -HALT interrupt saves the PC and PS and goes to the restart address with PS = 340.

7.3.5.7

7.3.5.8 Trace Trap - The trace trap is enabled by bit 4 of the PS and causes processor traps at the end
of instruction execution. The instruction that is executed after the instruction that set the T-bit will
proceed to completion and then trap through the trap vector at address 14. The trace trap is a system
debugging aid and is transparent to the general programmer.

Power Failure Interrupt - The power failure interrupt occurs when -PF line is asserted. Vectors for power failure are locations 24 and 26. Trap will occur if an RTI instruction is executed in a
power fail service routine.

7.3.5.9

7.3.5.10 Interrupts - See Table 5-3.

NOTE
Bit 4 of the processor status can only be &et indirectly by executing an RTI or RTT instruction
with the desired PS on the stack.

7-65

7.3.5.11 Special Cases (T-bit) - The following are special cases of the T-bit.
NOTE
The traced instruction follows the instruction that
sets the T -bit.
1.

An instruction that cleared the T-bit - Upon fetching the traced instruction, an internal flag,
the trace flag, was set. The trap will still occur at the end of execution of this instruction. The
status word on the stack, however, will have a clear T-bit.

An instruction that set the T-bit - Because the T-bit was already set, setting it again has no
effect. The trap will occur.

An instruction that caused an instruction trap - The instruction trap is performed, and the
entire routine for the service trap is executed. If the service routine exits with an RTI or in
any other way restores the stacked status word, the T-bit is set again, the instruction following the traced instruction is executed, and, unless it is one of the special cases noted previously, a trace trap occurs.

Interrupt trap priorities - When multiple trap and interrupt conditions occur simultaneously,
the following order of priorities is observed (from high to low).
1.
2.
3.
4.
5.
6.

7.3.6

Halt line
Power fail trap
Trace trap
Internal interrupt request
External interrupt request
Instruction traps

Miscellaneous Instructions

HALT
Halt

000000
00

o :

0 :

MR-5261

Operation:

1(SP) ~ PS

1 (SP) ~ PC
PC ~ restart address
PS ~ 340

Condition Codes:

Unaffected

Description:

The processor goes to the restart address after placing the current PC and PS on
the stack. PS is initialized to 340.

7-66

WAIT

000001

Wait for Interrupt

MR·5262

Condition Codes:

Unaffected

Description:

In WAIT, as in all instructions, the PC points to the next instruction following the
WAIT instruction. Thus, when an interrupt causes the PC and PS to be pushed
onto the processor stack, the address of the next instruction following the WAIT is
saved. The exit from the interrupt routine (i.e., execution of an RTI instruction)
will cause resumption of the interrupted process at the instruction following the
WAIT.

RESET
000005

Reset External Bus
00

o :

0 :

1 :

0 :

MR-5263

Condition Codes:

Unaffected

Description:

The - BCLR line is asserted and the mode register is loaded. - BCLR is negated,
and an ASPI transaction takes place. PC, PS, and RO-R5 are not affected.

MFPT

000007

Move from Processor Type Word
00

MR-7198

Operation:

RO +-- 4

Condition Codes:

Unaffected

Description:

The number four is placed in RO telling the system software that the processor
type is Micro/T-l1.

7-67

7.3.7 Condition Code Operators

CLNSEN
CLZ SEZ
CLV SEV
CLC SEC
CCCSCC

0002XX

Condition Code Operators
15

Ia : a : a : a : a : a : a : a :

a : 1

0/1

I Iz Iv Ic
N

MR-5266

Description:

Condition code bits are set and cleared. Selectable combinations of these bits may
be cleared or set together. Condition code bits corresponding to bits in the condition code operator (bits 0-3) are modified according to the sense of bit 4, the
set/clear bit of the operator (i.e., set the bit specified by bit 0, 1,2, or 3, if bit 4 is
a one). Corresponding bits are cleared if bit 4 = O.
Mnemonic

Operation

OPCode

CLC
CLV
CLZ
CLN
SEC
SEV
SEZ
SEN
SCC
CCC

Clear C
Clear V
Clear Z
Clear N
Set C
Set V
Set Z
SetN
Set all CCs
Clear all CCs
Clear V and C*
No operation

000241
000242
000244
000250
000261
000262
000264
000270
000277
000257
000243
000240

NOP

*Combinations of the above set or clear operations may be ORed together to form combined instructions.
Clear V and C represents CLC (241) ORed with CL V (code 242).

7-68

CHAPTER 8
THEORY OF OPERATION

8.1 INTRODUCTION
This chapter provides an explanation of SBC-ll/2I hardware operation from the perspective of the
logic designer. It is useful for troubleshooting the device to the chip level.
NOTE
The negated or inverse signal is designated by a
minus sign (-). For example, RAS is normally low
and asserted high when activated; - RAS is normally high and asserted low when activated. This
convention is used throughout this chapter. The LSI11 bus signals are consistent with the standard bus
conventions.
The SBC-II/21 functional block diagram is shown in Figure 8-1 (sheets I and 2) and provides an overview of the module functions and how they are related. The main components of the single-board computer are shown on sheet 1 of Figure 8-1. The single-board computer has a microprocessor interconnected to the serial line units, RAM memory, ROM memory, and the parallel I/O interface via the
on-board TDAL bus. The TDAL bus can access the LSI-ll bus (BDAL bus) by the bus control function, shown by broken lines, and is for reference only. The address bus, the memory address decode
function, and the interrupt control function are also shown on sheet I of Figure 8-1.
The microprocessor support functions and the LSI-II interface functions are described on sheet 2 of
Figure 8-1. The microprocessor is shown by broken lines for reference only. The power-up, clock, clock
control, ready, DMA, and halt functions are used by the microprocessor. The IAK data in, sync,
read/write, reply time-out, and bus control functions are used to interface the LSI-ll bus to the microprocessor.
The functional descriptions used in this chapter define the microprocessor and the input/output signals
associated with its operation. The support functions, the LSI-II bus interface functions, and the remaining single-board computer devices are also described in detail.
8.2 MICROPROCESSOR
The microprocessor is contained within a 40-pin LSI chip and is shown in Figure 8-2. There are eight
I6-bit general-purpose registers (RO-R7). R6 operates as the stack pointer (SP); R 7 operates as the
microprocessor program counter (PC). A special purpose status register contains the current processor
status word (PSW). The operating characteristics of the microprocessor are affected by the mode register which is discussed in detail in Paragraph 8.3.
8.2.1 Microprocessor Initialization
The microprocessor initializes the SBC-ll /21 module during the power-up sequence or when the RESET instruction is executed.

8-1

THAlT

All

TEVNT

~
~
~
~
CAS

ROll
XDL1
RDl2
XDl2
PCO
PC3

BClR

INTERRUPT
CONTROL

~ :~~~

~BIR04l

ADl

F:O;--

MICRO
PROCESSOR
XE57

~
-READ

....

~EET2

~ DATA ADDRESS BUS TDAl8-TDAl 12~

~
0M25

-RsTNC
FROM
SHEET 2

1--1
Vl

::l
al

BDAlOO-15

"BUS
CONTROL
"'

Ui
...J

.;j

!E;X TDAlOO-15 ~

LS~H:~ 'Q

~~~~T2~

BDIN l

~~~~T2~

BWBT l

)

-READ

-CSKTA

BDAlO, 1,2

BRPlY l

READ

BRPlY

~
-WlB

-SEl6

TDAl8, 11, 13, 14, 15

I -READ"'
l -WlB

00
l

Figure 8-1

-WHB
-CSKTA

If'

-CSKT8

DATA ADDRESS BUS TDAl 00 TDAl 15

y<"

SBC-ll/21 Functional Block Diagram (Sheet 1 of 2)

8-2

~15

AD1-AO~

ADDRESS BUS

~~~~T2~

RAM
MEMORY
E38
E53

... ;.MODE
REGISTER
CONTROL

-WHB

l -READ

DC004
PROTOCOL
E19

~07

-WlB

-CSOB

PC3
PARAllEL
1/0
INTERFACE
E60

-CSRAM

~
l 8DOUT l
l BWTBT l

BDOUT l-J

-CSPl

-CSRAM

BClR

I-CSOB

l BDIN l

~
-CSPl

i§-

I
BDAl 0,1,2

MEMORY
ADDRESS
DECODE
XE39

RDl2
XDl2

PCO

ADl

RDL1
XDL1

~0-15
r

~ ~

XE58
XE59

READ
r---+
TO SHEET 2

I CSDlO.
I-CSDL1 •

BEVNT l

INTERFACE

~ UNITS 1 & 2

lBS7

-IAK

TEVNT

-CSDL1

ADDRESS
lATCH
E48
E56

~ -SElO

BHAlT l

THAlT

~
SERIAL LINE
ADl

RBS7
SHEET 2

BClR

ROMIRAM
MEMORY
SOCKETS
XE44 XE45
XE54 XE55

$'~
~

BWTBT l

BDDUT l

BDIN l

PROCESSOR CONTROL SIGNALS

RAS

-SEL 1

IIIIIl RAS
L -BClR
T ClK SP

TSYNC

TDIN

READ/
WRITE

-C SYNC

REPLY
TIME-OUT

TDOUT

SYNC

RRPlY

BINIT l

-CSQB

BSYNC l

-IAK

TREAD

-BClR

IAK DIN ;--

DMG

r-r-

SEL 0

SYNC

SEl1

TIAKO

...

-RAS

-BelR

DMA

BDMRl

TREAD

TMER

BDMGDL

CAS

-SEl1

SElO

-BClR

RAS
COUT
-BClR

IAK
DATA
IN

BIAKO

TClKSP

CAS

TClK SP

-BClR

DClO

BPDK H

SYNC
-CAS
-BClR

CLOCK

COUT
-BClR

READY

CLOCK
CONTROL

~
SClK

PUP
POWERUP

-DRRPlY
-TClK

;--

DlClK

I
I
I
I
I

I
TO SHEET 1
PUP

DCLD

I ~~'Z:c~SSDR
I
I XE57
I (SEE SHEET 1) I

IAKDIN

PRDCESSOR CONTROL SIGNALS

I
I

SYNC

T ClK SP

I
I
I
I
I
I
I

-TMRP

-CTMER

HALT

TO SHEET 1
POWER FAil

I
I

SBC-llj21 Functional Block Diagram (Sheet 2 of 2)

8-3

I
I

___ .J

PROCESSOR CONTROL SIGNALS

Figure 8-1

--- -,

-CDMRQ

COUT

""\

BUS
CONTROL

-TMRP

CAS

r- rDMG

RBS7

l SEl1

-DMG

BBS 7 l

READ

-DRRPlY

PROCESSOR
CONTROL
SIGNALS

-CTMER
-PFAI L

AI-7

TDAL 15
TDAL14
TDAL13
TDAL12
TDAL 11
TDAL 10
TDAL 09
TDAL 08

AI-6
AI-5
AlA

ENCODED
INTERRUPT
INPUTS

AI-3
AI-2
AI-l

-CDMRQH

-TCLK

READY

-PUP

AI-O

XTL1

MICROPROCESSOR
XE57

TDAL
BUS

TDAL 07
TDAL 06
TDAL 05
TDAL 04
TDAL 03
TDAL 02
TDAL 01
TDAL 00
SELO
SELl

READY

R/-WHB.
R/-WLB
PUP

}

TRANSACTION
TYPE
CONTROL

}

TRANSACTION
CONTROL
STROBES

-RAS
-CAS
PI
COUT

-BCLR

Figure 8-2

RESET

SBC-II/21 Microprocessor

8.2.1.1 RESET Instruction - The RESET instruction asserts the - BCLR output. This clears or resets
the control logic of the module to an initial state. The microprocessor loads the mode register from the
TDAL bus with the mode register control data. The LSI-ll bus transceivers are disabled when
- BCLR is asserted. The RCVIE bit of the RCSRs and the XMITIE, MAINT, and XMITBRK bits of
the XCSRs are reset in the serial line units (SLUs). The port C buffer output lines of the parallel I/O
are set high. If port A and port B buffers are output to the connectors, they are also set high. The LED
is turned off during reset. The - BCLR output is then negated and an assert priority in (ASPI) transaction is performed to service any interrupts or DMA requests. The RESET instruction does not change
the PSW or any internal registers.
8.2.1.2 Power-up Input (PUP) - The power-up (PUP) input goes from low to high when the 5.0 V
power is first applied. This initiates the power-up sequence_ The - BCLR output is asserted. The module is cleared and reset as it is for the RESET instruction, however, the serial line units' (SLUs) registers are completely reset. After a delay, BDCOK and BPOK are asserted, PUP is negated, and the
- BCLR output goes high. The microprocessor then performs ten bus NOP transactions. The processor
loads the starting address into the program counter (R7), location 376 into the stack pointer (R6), and
the processor status word is set to 340. An assert priority in (ASPI) transaction is performed to service
any interrupts or DMA requests before the first instruction is fetched.

8-4

The PUP input normally stays low for all operations. If PUP is asserted high, the present transaction is
terminated and the internal registers go to an undetermined state. The TDAL bus, the interrupt inputs,
and the microprocessor control signals will all go to an initial reset state.
8.2.2 Clock Input (-TCLK)
The - TCLK input is a 4.9152 MHz clock that comes from the 19.6608 MHz crystal oscillator. This
clock input is used for the internal time base of the microprocessor and the source of the clock output
(COUT). COUT is pulsed once for every microcycle. A microcycle can represent either three or four
- TCLK input pulses depending on the type of transaction. The microprocessor will halt or stop when
the - TCLK input is disabled.
8.2.3 Ready Input (READY)
READY input is normally high and will not interfere with microprocessor transactions. However, when
the input is held low, a single microcycle slip occurs during every transaction. When READY is
clocked with COUT, while RAS is asserted, the microprocessor slips a microcycle every time the input
is pulsed. This allows the microprocessor to be placed in an idle or wait state until a peripheral device
has either received or asserted data on the bus.
8.2.4 Microprocessor Control Signals
The microprocessor controls the functions of the SBC-ll /21 through the use of nine microprocessor
control signals. A description of these signals and their functions follows. The RAS, CAS, PI, COUT,
and BCLR are transaction control strobes used for logic transitions. The R/ - WLB, R/ - WHB,
SELO, and SEL I are steady state logic signals used as transaction type control signals.
8.2.4.1 Row Address Strobe (RAS) - The leading edge of the RAS signal is used to acknowledge that
the address is stable on the TDAL bus during read/write and fetch transactions. During interrupt transactions, the leading edge of the RAS signal strobes the interrupt acknowledge data onto the TDAL
12-8 bus lines.
8.2.4.2 Column Address Strobe (CAS) - The trailing edge of the CAS signal is used to acknowledge
that data on the TDAL bus lines during read and fetch transactions was read by the microprocessor.
For write transactions, the signal is used to acknowledge that microprocessor data will be removed after
a specified time.
The leading edge of the signal is used to request that read data be placed on the TDAL bus· and to
strobe interrupt requests into latches that are read during the assertion of PI.
8.2.4.3 Priority In (PI) - The leading edge of the PI signal is used to acknowledge that data on the
TDAL bus lines during write transactions is stable. The leading edge is also used to enable the microprocessor to read the interrupt inputs AI-O to AI-7 and to initiate IAK, restart, power fail, or DMA
transactions.
8.2.4.4 Read/Write (R/ - WHB and R/ - WLB) - The R/ - WHB and R/ - WLB signals control the
read/write and fetch transactions by enabling the TDIN, TDOUT, and TWTBT control signals. For
read and fetch transactions, both signals are asserted high and enable the TDIN control circuits. During write transactions, the TDOUT and TWTBT control circuits are enabled when either or both signals are asserted low. If only one signal is asserted low, the TWTBT control circuits are enabled by the
leading edge of CAS, and a write byte transaction occurs for either high byte or low byte.
8.2.4.5 Select Output Flags (SELO and SELl) - The SELO and SELl signals indicate the transaction
being performed. When both signals are low, a read, write, ASPI, or NOP transaction is selected. When
both signals are high, a DMA transaction is selected. When SELl is low and SELO is high, the fetch
transaction is selected. When SELl is high and SELO is low, an IAK transaction is being performed.

8-5

8.2.4.6 Bus Clear (BCLR) - The BCLR signal is used to reset the control logic and generate BINIT.
The signal is asserted during the power-up sequence and the execution of a RESET instruction only.
8.2.4.7 Clock Out (COUT) - The COUT signal is asserted once for every microcycle and is used to
time the microprocessor transactions:
8.2.5 Microprocessor Transactions
The microprocessor performs six types of transactions to support the instruction set, direct memory
access, and the interrupt structure.
1.
2.
3.
4.
5.
6.

Fetch/read
Write
DMA
IAK
ASPI
Bus NOP

A normal fetch/read or IAK transaction requires either one or two microcycles; extended transactions
can take as many microcycles as required before a time-out occurs. The COUT signal is asserted once
for every microcycle. The transactions are used to transfer information and data via the TDAL bus
which interconnects all local devices and connects them to the LSI-II bus interface. A description of
each transaction operation follows.
8.2.5.1 Fetch/Read - The fetch/read transaction is used either to fetch an instruction or read data for
the microprocessor. The data may originate from the on-board memory, I/O device, or the LSI-ll bus.
The microprocessor control signals for the transaction are illustrated in Figure 8-3. The R/ - WLB and
R/ - WHB control signals are asserted. The SELO output is high, and the SELl output is low for the
fetch transaction; both of these outputs are low for the read transaction.
The following sequence of events takes place during a fetch/read transaction.
1.

The microproc~ssor places the address onto the TDAL bus when the transaction is initiated
and is latched into the memory address circuits by the assertion of SYNC.

The data is received on the TDAL bus after RRPL Y is received. The microprocessor accepts
the data and negates TDIN.

Interrupt and DMA requests are latched by CAS, set up while PI is asserted, and latched
into the microprocessor when PI is negated.
NOTE
A write transaction is always preceded by a read
transaction except when the microprocessor pushes
onto the stack. Therefore, each write has at least
four microcycles: assert address, read data, assert
address, and write data.

8-6

I---------FETCH/READhTIR.ANSACTION

--------j.-t

·-I----ASSERT
...
ADDRESS---••foII·-I------READ

COUT _ _ _ _

_____-J/

6g~1~::x____A_D_D_R_E_S_S____JX~

NOTE 2

DATA---....,'~

,'---____

__________________~{______

D_A_TA
__
1N____~x==

(.a.-_I_N:.:.~E::.:~:::.;~::..:~~~:...:.TM_A___}'--_____

AI.O-AI.;J\o.....___________________________

RAS ________

PI _ _ _

--+:_------~/

-+:____~I

CAS _ _ _

I
I
I

R/-WLB-:]

R/-WHB...J

SELO"'l-----i--N~~E_, ---j -- --'I
--...,

I
I

L
L
C

'-'-

SE L 1__ ) ______--I'_________--I'fo-____________________+-_____
-I,
I

)

I
I

NOTES:
1. SELO IS HIGH FOR FETCH TRANSACTIONS
AND LOW FOR READ TRANSACTIONS.
2. LSI·11 BUS TRANSACTIONS CAN CAUSE THIS
PORTION OF TIME TO SLIP UNTIL THE
DEVICE RESPONDS OR TIME·OUT OCCURS.

'--

MR-6635

Figure 8-3

Fetch/Read Transaction

8-7

8.2.5.2 Write - The write transaction is used to write data from the microprocessor to memory, a local
I/O device, or an LSI-II bus peripheral device. The microprocessor control signals for the transaction
are illustrated in Figure 8-4. The R/ - WLB and R/ - WHB control signals are asserted low when writing a word; for writing a byte, either the high or low byte signal is asserted. Both SELO and SELl
control signals are negated.
The following sequence of events takes place during a write transaction.
1.

The microprocessor places the address onto the TDAL bus, and the state of the read/write
lines causes TWTBT to be asserted. The address is latched into the memory address circuits
by the assertion of SYNC.

When CAS is asserted, TWTBT is negated for word transactions and left asserted for byte
transactions.

The data is placed on the TDAL bus before TDOUT is asserted. The data is written into the
addressed location when TDOUT is negated.

When the addressed device negates BRPLY, the SYNC and TWTBT signals are cleared.

The DMA requests are detected while PI is asserted; they are latched into the microprocessor when PI is negated. No other interrupts are read by the microprocessor during
write transactions.

8.2.5.3 IAK - If an interrupt request was detected during a previous read transaction, the microprocessor initiates an IAK transaction as illustrated in Figure 8-5. The R/ - WHB and R/ - WLB control signals are asserted high, and CAS, PI, and SELO are asserted low for the transaction. The TDAL
bits 12-8 represent the acknowledged input and are used to reset the interrupt request. For local interrupts, TDAL bits 7-0 are ignored because the vector address is in the microprocessor. For LSI-II bus
interrupts, the vector address is read from the bus using TDAL bits 7-2. TDAL bus bit 12 is set low for
this IAK transaction and commands the control logic to initiate an LSI-ll bus IAK transaction. The
TDIN signal is asserted for the transaction, and the TIAKO output acknowledges the interrupt. The
requesting device then places the vector address on the low byte of the bus and asserts BRPLY. The
microprocessor stops slipping microcycles, negates TDIN, and accepts the vector. It then negates
TIAKO on the trailing edge of RAS and continues to the next transaction.
8.2.5.4 DMA - The DMA request is read during a previous transaction. The microprocessor will acknowledge the request by tri-stating the TDAL bus as shown in Figure 8-6. The SELO and SELl outputs are asserted to indicate that the bus mastership has been relinquished. The transaction will continue with no interruptions until the DMA transfer is completed. The microprocessor will then negate the
SELl control output to indicate that it is resuming bus mastership. The negation of SELO will follow if
the next transaction is not a fetch.
8.2.5.5 ASPI - The assert priority in (ASPI) transaction is used by the RESET and WAIT instructions or the power-up sequence as shown in Figure 8-7. The CAS and PI outputs are asserted to allow
the microprocessor to recognize and latch any interrupts or DMA requests. The R/ - WHB and
R/ - WLB outputs are asserted and the SELO, SELl, and RAS outputs are negated for the transaction.
8.2.5.6 NOP - The bus NOP transaction performs no operation and is used during the power-up sequence or if the programmer intentionally introduces a delay into the program. The AI-O through AI-7
inputs are tri-stated to prevent interrupts. The R/ - WHB and R/ - WLB outputs are asserted, and the
SELO and SELl outputs are taken low. The RAS, CAS, and PI control strobes are inhibited during the
transaction as shown in Figure 8-8.

8-8

....- - - - - - - - W R I T E

TRANSACTION--------~:~I

....---ASSERT ADDRESS---••,......---WRITE DATA-----~-
NOTE 3

COUT_ _ _.....

6~~~==x~

\'-_____---1/

,______

_________

x==

A_D_D_R_E_S_S___

_IX~____JX~

D_A_T_A_O_U_T____________

AI-O-AI-7J_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _<.L-_D_M_A_R_E_Q_U_E_ST
_ _}~_'C.

\_---

RAS _ _ _ _ _

\~--

PI-----t:---------

CAS

\ ____

R/-WLB\----t---NOTE1--1-----i-----------+---- -

----

-r-

---

--NOTE1---r----+I - - - - - - - - - - - i ------T
1

R/-WHB\---T

---

SELO\,_ _ _

---

(

~II _ _ _ _~I---~(-----------~(-------'rI
I
I

\, _ _ _ _~I______~I---~I-------+I---.l1

SELl

...I!

SYNC._ _ _

I
RRPLYH

--------~I---~I
I

TDOUT __________________

TWTBT

\_--

~:~----Jlr-------------,~--------_

\ _______ ~~~ ________L_

NOTES:
1. R/-WHB OR R/-WLB CAN BE HIGH WHEN
PERFORMING A WRITE BYTE TRANSACTION.
2. TWTBT IS LOW FOR WORD TRANSACTIONS.
3. LSI-ll BUS TRANSACTIONS CAN CAUSE THIS
PORTION OF TIME TO SLIP UNTI L THE DEVICE
RESPONDS OR TIME-OUT OCCURS.
MR-6636

Figure 8-4

Write Transaction

8-9

1ooI14~--- SEE NOTE

COUT

-----------, ,----------X=

TDAL 12-0SJ......_ _ _ _ _ _
IN_T_E_R_R_U_PT_RE_Q_U_E_S_T_D_A_TA
_ _ _ __ _ _

TDAL 07-00=:x......_ _ _ _ _ _

.JX~----V-EC-T-O-R-IN---..J

RAS,_ _ _ _ _- ' ,

SELO=--'~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.J

SEL1 _ _..J'
IAKDIN_ _ _J /
TIAKO_ _ _ _ _ _.....J/

\_--------------~

-IAK

...I1

TDIN _ _

NOTE:
LSI-11 BUS TRANSACTIONS CAN CAUSE THIS
PORTION OF TIME TO SLIP UNTIL THE DEVICE
RESPONDS OR TIME-OUT OCCURS.
MR-6637

Figure 8-5

IAK Transaction

8.3 MODE REGISTER CONTROL
The mode register is an internal microprocessor register used to define the operating mode of the microprocessor. The 16-bit mode register is written into from the TDAL 0-15 data lines during a power-up
sequence or when a RESET instruction is executed. During this time, the - BCLR output is low and
the mode register is loaded. The mode register logic (Figure 8-9) has five tri-state drivers that are enabled when the - BCLR input goes low. TDAL bits II and 8 are factory set to force the microprocessor to operate in the following mode.
.
1.

The microprocessor clock mode is selected. The microprocessor pulses the COUT output
once for every four XTLI input pulses during DMA and interrupt transactions. For all other
transactions, it pulses the COUT output once for every three XTL I input pulses.

The standard microcycle mode is selected. It uses four XTLI input periods for DMA and
interrupt transactions and three XTLI input periods for all other transactiQns.

The normal read/write mode is selected. The normal read/write mode sets the read/write
control lines (R/ - WLB and R/ - WHB) prior to the assertion of - RAS and remains valid
after the negation of - CAS.

8-10

COUT

f\~----~~,-----~~,---

AI-O \"' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___JLl....

RAS
CAS

_ ~~~O~~ ___ _

\'-----~/

\~_______________J/
\----------------~/

\
\

TRI-STATE
C__ _
'"--------..:..:.:..:..;;:.:..;.;.:.=------------1.

R/-WHB-- - - - - )
R/-WLB_ _____

SELO _ _ _ _ _ _

\ ------

-.J/

SEL 1 _ _ _ _ _ _

DMG _ _ _ _ _ _-J/~--------------------TDMGO _ _ _ _ _ _ _~r---\~
RDMR

RSACK _ _ _ _ _ _ _ _ _ _

____________________

\ ----------------------,
~I
\

\_----------

NOTE:
AI-O IS ASSERTED LOW UNTIL BSACK IS NEGATED
AND NO OTHER RDMR IS BEING ASSERTED.
MR-6638

Figure 8-6

DMA Transaction

The static memory mode is selected, and therefore, no dynamic memory chips may be installed on the module. The refresh function is disabled.

The memory addressing is limited to 64Kb.

The bus has 16 bits.

The user mode is selected. This mode performs transactions with no automatic test of the
processor status word.

8-11

COUT~--------J'

\\.-___1\...

TDAL _ _ _---')-----...;..;.;~;.;..;.;.=-----~'_
)
TRI-STATE
( _ _ _ _ _ __
00-15

AI-O-AI-7~~~~~~~ (~_ _ _ _ _ _ _.....J{...I..:NR.:.:TE:.:;~~~:;.:;~;:;:f:.:.TM_A....}t..__.t.}_______

------,\
r--------I
- ----- _\~---------------~

RAS

,'"-------

CAS _ _ _ _ _ _ _ _,

,'---------

PI~_ _ _-------~/
R/-WHB;
R/-WLB ______ - l

\--------'-- _ _ _ _ _ _ _ _

SELO------\
SEL1 _______

,'--------_ _ _ _ _ _ _ _ _ _ _ _ _ ___I.I_ _ _ _ _ _ _ _ _ _ _
MR·6639

Figure 8-7

ASPI Transaction

,"-_ _ _ _ _......Ir

COUT_ _ _ _ _ _ _,.."

____ _

TDAL -------V
PREVIOUSLY LATCHED DATA
:------00-15 ______ -"_ _ _ _ _ _ _ _ _ _~--------I\..--

AI-O-AI-7=~===)~--------..:T.;.R;.;.I-.;;S:.:.T:..;A:.:.T.:;.E--------<C~_=__-_-_~-=

RAS

-,\

_ _ ~I_ _ _ _ _ _- - - - - - - - - - - - - - - - - - - - - - -

CAS

I~_ _ _ _ _- - - - - - - - - - - - - - - - - - - - - - -

-,
__

\
~I_ _ _ _ _ _- - - - - - - - - - - - - - - - - - - - - - -

R/-WHB-------;
R/-WLB _____ -oJ

\L _ _ _ _ _ _ _

------,

SELO_ _ _ _ _ _ \

-i\~

r------_______ _

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __',I

------,

SELl _ _ _ _ _ _ \lo'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
MR-6640

Figure 8-8

BUS NOP Transaction
8-12

Z1
+5 V----'No

M18

M22

TDAL15
M26

M29

TRI-STATE
DRIVERS
E41

M30

TDAL14
TDAL13
TDAL11
TDAL8

-=
-BCLR
MR·7519

Figure 8-9

Mode Register Control

The status of TDAL bits 13-15 are selected by the user. These bits determine the start and restart
addresses for the microprocessor. The start address is the location of the first fetch after power-up, and
the restart address is the location of a fetch after a HALT instruction is executed or the assertion of the
HALT interrupt. The wirewrap pins M22, M26, and M30 control the status of TDAL bits 13-15 during the power-up sequence. Wirewrap pin M18 is pulled up to +3 Vdc and represents a one; wirewrap
pin M29 is connected to ground and represents a zero. Pins M22, M26, and M30 are jumpered to either
M18 or M29, according to the list in Table 8-1, to select both the start address and restart address for
the microprocessor.
Table 8-1

Start Address Configurations

Wirewrap Pins
Bit 15
M22

Bit 14
M26

Bit 13
M30

1
1
1
1
0
0
0
0

1
1
0
0

1
0
1
0

1
1

0
0

1
1

Start Address

Restart Address

172000
173000
000000
010000
020000
040000
100000
140000

172004
173004
000004
010004
020004
040004
100004
140004

Connection to M 18 = 1
Connection to M29 = 0

8-13

8.4 INTERRUPT CONTROL
The interrupt control, as a block diagram, is illustrated in Figure 8-10. (Studying this diagram will
make the explanation presented in Paragraph 8.4.1 easier to follow.)

MI CROPROCESSOR
HALT

AI-7

P FAil

AI-6

DMRQ

AI-O

BUS
INT
ACK
E8,E15

BIAKO

_ _ _ _ ...1OTHER
SIGNALS

AI-l TOAI-4

TDAl8-11

-----"
9 ADDRESS

REVNT
PARQST

LINES

PBRQST
BKRQ

PRIORITY
INTERRUPT
ENCODING
MEMORY
512X4
ROM
E33

DECODE
IAK
E34
XE57

SlUl
XE58
RDLlI--r-t-L"':':'=':'::"'-j

XDLl

RDl2 r - - r -......,..:;.;;=~--I 6
XDl2
XE59
SlU2
4 RESETS

INTERRUPT
ACK
DECODER
MEMORY
32X8 ROM
E40

TDAl8-11

Figure 8-10 SBC-ll/21 Interrupt Control

The SBC-11/21 interrupt control design includes the following elements:
1.

Five D flip-flops that latch five of the interrupt lines.
a.
b.
c.
d.
e.

REVNT
PARQST
PBRQST
BKRQ
HLTRQ

Wire OR-ed TEVNT or BEVNT
Parallel I/O port A interrupt request
Parallel I/O port B interrupt request
Level 7, maskable interrupt, configurable
Produces CTMER, nonmaskable interrupt, configurable

Twelve interrupt synchronizing latches that latch the following signals.
a.

Outputs of the five latches described previously

8-14

Three interrupt signals:
(1)
(2)
(3)

IRQ4
DMRQ
PFAIL

Level 4 LSI-ll bus interrupt
DMA request
Power fail nonmaskable interrupt

Four signals from the interrupt acknowledge decoder, wire OR-ed with interrupt
requests from SLUs.
(1)
(2)
(3)
(4)

RDLI
XDLI
RDL2
XDL2

SLUI receiver interrupt request
SLUI transmitter interrupt request
SLU2 receiver interrupt request
SLU2 transmitter interrupt request

The operation of the SBC-11 /21 interrupt control centers around eight microprocessor input lines, AI-O
to AI-7, driven by interrupt signals, either directly or indirectly, through the interrupt encoding PROM.
•

AI-O is the DMA request line connected directly to DMRQ.

•

AI-l to AI-4 are driven by the output of the interrupt encoder to request maskable interrupts.

•

AI-5 is driven by the VEC gate which detects the presence of the LSI-II bus interrupt on the
outputs of the interrupt encoder. It calls for a vector read transaction from the bus.

•

AI-6 is driven directly by the power fail input line to force a power fail trap.

•

AI -7 is driven directly by the HALT interrupt line to force a restart trap.

The microprocessor reads the AI-O to AI-7 input lines and arbitrates the interrupt priority according to
Table 8-2. In addition, the state of AI-l to AI-5 is reproduced on TDAL 12-8 lines during the acknowledge cycle. TDAL 11-8 lines are used as an address in the interrupt acknowledge decoder, which is a
32-byte PROM. Output bits 7-4 of that PROM are the previously stated SLU receive and transmitter
interrupt requests (RDLl, RDL2, XDLl, XDL2) which are wire-ORed to reset the latched requests in
the SLUs. TDAL 12 reflects the state of the - VEe signal and is used in the LSI-II bus protocol.
Bits 0-3 are used as reset signals for the four interrupt latches previously described.

8.4.1 Interrupt Control Logic
The interrupt logic (Figure 8-11) receives the interrupt requests from the interface devices and applies
them to the microprocessor. The microprocessor will acknowledge the highest priority interrupt if its
priority is higher than the current microprocessor status word priority. There are nine interrupts available, and either one or all can be inputs to the interrupt synchronizers E27 and E32. Any interrupt is
active when the signal goes high. Five of these inputs are latched and stay high until reset. Four interrupts are clocked through flip-flops EI0 and E17 to maintain a high output. The enabled interrupts are
clocked through the interrupt flip-flops by CAS asserting during the present transaction. These outputs
address interrupt encode memory locations enabled by the - PI input of the present transaction. The
interrupt encode memory outputs an interrupt code equivalent to the highest input priority.

8-15

Table 8-2 Designated Interrupts
Interrupt
Source

Input
Signal

Priority
Level

Coded Input
AI-l AI-2 AI-3 AI-4 AI-5

Vector
Address

HALT

HLTRQ

Nonmaskable X

Restart
address

Power fail

PFAIL

Nonmaskable X

LSI-II bus
signal BHALT

BKRQ

140

LSI-II bus
signal BEVNT

REVNT

100

SLU2REC

RDL2

120

SLU2XMIT

XDL2

124

Parallel I/O B

PBRQST

130

Parallel I/O A

PARQST

134

SLU1REC

RDL1

SLU1 XMIT

XDL1

LSI-ll bus
signal BIRQ4

IRQ4

Read
from
LSI-II
bus

HALT and power fail (PFAIL) interrupts are not generated by the coded inputs AI-l to AI-S. All signals are listed in the order
of descending priority.

The interrupt codes and their priority levels are listed in Table 8-2. When the PI output is enabled, the
microprocessor looks at the interrupt inputs and will initiate an IAK transaction for an interrupt with
the correct priority following the completion of a read transaction. The coded input to the microprocessor is placed on the TDAL bus using bits 8-12. Bit 8 represents the AI-I, input; bit 11 represents
the AI-4 input. These four TDAL bus bits are inputs to the acknowledge decoder memory that is enabled when the microprocessor starts the IAK transaction and the - IAK input goes low. These inputs
are decoded to determine which interrupt was acknowledged and will output a low to negate that interrupt. The interrupt flip-flop is reset by the clear line for that interrupt, switching the output of the
selected AND gate low. The E59 and E58 transmitter and receiver interrupt lines are latched outputs
and are reset by wire OR-ing and asserting low the output of the acknowledge decoder PROM. The
LSI-II bus interrupt is an exception to this process. This interrupt code enables the inputs of NAND
gate E34, and the low output enables the - VEC (AI-5) input to the microprocessor. This input instructs the microprocessor to receive the vector address from the TDAL bus. TDAL 12 represents the

8-16

PI
IR04 l
ROll
XOLl
ROl2
XOl2
-IAK

02
04
03
05

~++1-----------------------~06

~~+=============107

I04
1----L..------------------------t03
r--r----r-+3 VC

INTERRUPT 01

E27

E33

AI-4

AI·3

2M
3MI-+-+-r-------""""-

A4 INTERRUPT

A5 ~~g~DE
A6512X4

A7
AS

ACKNOWLEDGE
DECODER
83
MEMORY
E40
32 X S

OM
1M

H--'-=PB""RO::.ST'---_ _ _ _ _ _--tD5 FLlp·FlOPS 06

Al=-.cl -,,-O- - - - - - - t A 2
"-,,TO=
-':'TD=A=l9'--_ _ _-lAI
.!.!TD"'-A"-'l8'--_ _ _-lAO

AO
Al
A2

ClK
B2

CBKRQ
BO

-BelR
PCO
PC3

Figure 8-11

Interrupt Control Logic

state of the - VEC input when the microprocessor acknowledges the interrupt and is used to determine
that the LSI-II bus interrupt acknowledge handshake protocol must be initiated. The LSI-II bus interrupt is not reset by the acknowledge decoder PROM, but it should be reset when the TDIN and TIAKO
signals are received by the bus device during the interrupt acknowledge sequence.
Before continuing the discussion of the interrupt system, ready logic is discussed in Paragraph 8.4.2.
NOTE
The waveform diagrams shown in Figure 8-12 and
subsequent figures are referenced to the circuit schematics in Appendix E. They are intended only to
help users understand the logic and are not precise
representations of timing relationships.
8.4.2 Ready Logic
The ready logic (Figure 8-12) provides the READY input to the microprocessor and is used to control
the cycle slip function. The microprocessor will cycle slip when the READY input is being clocked
while RAS is asserted; the cycle slip function will be inhibited when the READY input is set high. The
output of the ready flip-flop and the COUT input go to the E14 OR gate and generate the READY
input. When the -CSLIP input to E6 is high and the TSYNC input is high, the output of the E6 AND
gate goes high. When -DRRPLY is not asserted and - TCLKSP and the output of E14 are high, the
output of E13 is high. This enables E35 and the preset input to the E20 flip-flops to go low. The flipflop output is low at OR gate E14, and it enables the READY input with every COUTo When the

8-17

-TMRP

- TCLKSP
-DRRPLY
E20
IAKDIN

Rl READY

-CSLlP
TSYNC

COUT
-BCLR

TSYNC
-CSLlP L

E4 PIN 5
E6 PIN 1

-CSOB
IAKDIN

E39PIN6
E14 PIN 4

RAS
_ _ _ -CAS

E31 PIN 13
E46 PIN 15
-TMRP
E26 PIN 10
-DRRPLY E5 PIN 6

------------------------------ COUT
------------------~----------- -ROSLP

------------

E13 PIN 12
E20 PIN 3
E20 PIN 8

READY

E14PIN 11

.------------------------- --- - - - --------------- --------- TCOUT

E14PIN 13
E20 PIN 12

A, SIGNALS DURING LSI-11 BUS TRANSACTION

_------TSYNC
CSLlP L
CSOB
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IAKDIN

------RAS
________ -CAS

:-----------TMRP

E4 PIN 5
E6 PIN 1
E39
E14 PIN
PIN 6
4
E13 PIN 1
E46 PIN 15
E26 PIN 10

~-----~-- -DRRPLY E5

- - - -_ - - - - - - - - - - - - - --

- - - - - - COUT
-ROSLP
READY

E13 PIN 12
E20 PIN 3
E20 PIN 8
E14 PIN 11

TCOUT

E14 PIN 13

_:::::::::::::::::::::::::::~::::::::::::
B.

PIN 6

CSRAM

E20PIN5
E39 PIN 1n

SIGNALS DURING LOCAL TRANSACTION
MR-7506

Figure 8-12 Ready
8-18

IAKDIN input goes high and the -CSLIP and TSYNC inputs are negated, the output of the E13
AND gate goes high. It allows the E35 NAND gate output to go low and forces the preset terminal of
the E7 flip-flop low. The output of the flip-flop to the OR gate is now low. This allows the COUT input
to clock the READY output. The microprocessor will continue to cycle slip while this input is being
pulsed. The - TMRP input to the NAND gate will go low when either the BRPLY or TMER input
from the bus is received. This will remove the low from the preset input of the first flip-flop. Immediately after the - TMRP input goes low, the -DRRPLY input also goes low and forces a high to the
input of the flip-flop. The high is clocked through by the COUT clock, and the flip-flop output to E14
will go high. This disables the READY input to the microprocessor and allows the transaction to be
completed.
The second E20 flip-flop is required to ensure that data is stable at the microprocessor or at the peripheral preceding transaction completion. The ready circuit is inactive during local address references.
8.4.3 IAK Data In (IAKDIN)
The IAKDIN output is enabled by the output of the NOR gate E15 as shown in Figure 8-13. The
microprocessor acknowledges an external interrupt request, asserts -SELl, and negates SELO. When
the microprocessor has to read the interrupt vector from the bus, the TDAL 12 input is low as a result
of AI-5 being low during the interrupt request read. This allows the IAKDIN output to go high and
assert TDIN to the bus. The RAS input is high; this enables the TIAKO flip-flop E8. IAKDIN is
clocked by the COUT input and causes TIAKO to go high. The inverter E18 sets the BIAKO output
low. The BIAKO output goes to the bus as an interrupt acknowledge. The TIAKO output goes to the
bus transceiver logic and enables the low byte transceivers to receive the vector. The IAKDIN output
goes to the ready logic and allows the microprocessor to cycle slip until the interrupting device asserts
the - BRPLY input or a time-out occurs. When either response is received, the SELO input goes high
to disable the IAKDIN output and signals that the microprocessor has read the vector. The RAS goes
low to clear the TIAKO flip-flop.
The microprocessor cannot abort the reading of a vector if a time-out occurs and will read a vector of
zero in all cases if - BRPLY is not asserted and the time-out counter triggers.
8.4.4 HALT Interrupt
The HALT interrupt (Figure 8-14) is defined as -CTMER and goes to the microprocessor AI-7 input.
The user determines the configuration of the control signals, such as TMER, SLU BREAK request, or
BHALT, that can trigger this interrupt. The E7 flip-flop is clocked by the input to M10; this asserts the
E32 flip-flop input. The assertion of CAS clocks the E32 flip-flop and enables the -CTMER output.
The CTMER output is set high and goes to the NAND gate E16. The assertion of PI during a microprocessor read or fetch transaction latches - CTMER into the microprocessor and simultaneously
switches the E16 NAND gate output low. This sets the output of the E28 AND gate low to reset the E7
flip-flop for the next HALT interrupt. The E32 flip-flop is cleared by the next CAS strobe. The microprocessor AI-7 input is pseudo edge-sensitive; it must be negated for one PI time before another trap to
the restart address can be started.
As explained in Chapter 2, connecting M9 to M13 prevents -CTMER assertion during LSI-ll bus
interrupt acknowledge transactions. This will prevent the restart trap resulting from this time-out.

8-19

-IAKDIN

-SELl
SELO
TDAL12

-BIAKO

COUT

TlAKO

RAS
E36

-BCLR

- .. _-- - -- ----- ------ - -- - --- - - - - - - - - ------ -- --.--..
- ---- .. - - - - - .. - - - -- --...

.. ---- - - -... - - - --- -- --

-- --

_--_

CAS
PI
SELl
RAS
-IAKDIN

E15 PIN 12
E8 PIN 11
E8 PIN 9
E57PIN 26

XHB
RHLB
-IAK
RLB

E52PIN 5
E51 PIN 4
E34 PIN 6
E43 PIN 4

PBRQST

E27 PIN 14

IRQ4
A15
-f'BAK H

E27 PIN 7
E34 PIN 8
E40PIN4

CAS
PI

E46 PIN 5
E31 PIN 10

SEL1
- ------- ---- RAS

E34 PIN 5
E46 PIN 16

- - .. _------ -----_._
.... --_
---.. COUT
---------------- ------_.
TIAKO
---.. . - -- - -....- - .... -- - -- _.-- --.-- .. READY

-- _ ------------_...._---------- - '------------------------ -

----

- -- ------- ------ ------;..------A.

SIGNALS DURING LOCAL INTERRUPT

- - - - - - - - - ------- - - - - - - -------~--....;

_. _--_._. -----_

--.-_._--- - -IAKDIN

....-_ ...... - .... --_ ........
.... _....-_._-_ ...
__ ....... _---_
....
_._ .....__ ....... --- - .. . COUT
............
__ .....
- ......

__ .. _-._ ..-_.. __.... __. ..

--._._----_.
... -_.
.-

E46PIN 5
E31 PIN 10
E34PIN 5
E46PIN 16

....

...

_..

TIAKO

. _ - - - - - - READY

...

E15 PIN 12
E8 PIN 11
E8 PIN 9
E57 PIN 26

XHB
RHLB
-IAK
RLB

E52 PIN 5
E51 PIN 4
E34 PIN 6
E43 PIN 4

PBRQST
IRQ4
A15
-PBAK H

E27 PIN 14
E27PIN7
E34PIN8
E40 PIN 4

SIGNALS DURING LSI-ll BUS INTERRUPT
MR-7S07

Figure 8-13

8-20

IAKDIN

+3V
-IAK

M13

TMER

M14

M10

~~----------------~O
~~----------------~C

E32
-CTMER
AI-7

CAS
-BCLR

TREAD
PI

_ - _ - _ - TDIN
-_______ TDOUT

E14 PIN 3
E6 PIN 8

_ - _ - _ - _ - TRGTM

E14 PIN 8
E9PIN12

-RRPL Y

E9 PIN 11
E29 PIN 9
E29 PIN 13
E7 PIN 12

=~~==========~::.-=~~~==~==~=TMER
RAS
:....-_ _ _ _ _ _ _: - - - - - - - - - M8

- - - - - - - - - - - - - - - - - M6(TMER) E7 PIN 11
HLTRQ
E7 PIN 9
----------------------------------------- HLTRQ
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CAS

E32 PIN 5
E32 PIN 9

________________________________________ CTMER
__________________
TREAD

E32 PIN 7
E15 PIN 6
E16 PIN 4
E34 PIN 6

~-_--_--_-

::~::::::::::::::::~:=~:=~~:=~===== -IAK
A_ SIGNALS DURING LSI-11 BUS TIME-OUT
(INTERRUPT ACKNOWLEDGE WITH M13 AND M9 JUMPER ED)

TSYNC
-_-.-_-.--.__-_-_-_-_-_._-_-_-_-_-_-_-.-_-_-_-_-.-_-.-•••••-- READY
_ TRGTM

E4 PIN 5
E14 PIN 11
E14 PIN 8
E9 PIN 12

________________________________________ -RRPLY
-___________________________- -_ _ _ TMER
---,
• RAS
- - - - - - - - - - - - -___________________ M8
M6(TMER)
HLTRQ
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -____ HLTRQ
- - - - - - - - - - - - - - - - - - - - - - - - _ - - _ CAS

=:::::::;;;;;;;;;;;;;;;;;;;;;;;;;;~;:~ TREAD
PI
________________________________________ -IAK

B_ SIGNALS DURING NONEXISTENT LSI-11 BUS ADDRESS
(WITH M13 AND M9 JUMPERED)

Figure 8-14

HALT Interrupt

8-21

E9 PIN 11
E29 PIN 9
E29 PIN 13
E7 PIN 12
E7 PIN 11
E7 PIN9
E32 PIN 5
E32 PIN 9
E32 PIN 7
E15 PIN 6
E16 PIN 4
E34 PIN 6

8.4.5 Power Fail (-PFAIL)
The -PFAIL output is connected to the AI-6 input of the microprocessor and is recognized as the
power fail interrupt which is nonmaskable. This is the second highest priority interrupt and it does not
initiate an IAK transaction. When acknowledged, the microprocessor traps through octal addresses 24
and 26 to access the PC and PSW for the user's power fail routine. This routine should include a RESET instruction, any other instructions needed to initialize the bus and the module, an MTPS instruction that willioad 340 into the PSW, and a WAIT instruction to inhibit the assertion of any LSI-II bus
control signal when battery backup is being used.
As an option to the MTPS instruction, 340 may be stored at location 26. Then, when the microprocessor
vectors through 24, 340 will automatically be loaded into the PSW.
NOTE
BDCOK can be used as a microprocessor reset signal, unrelated to power failure. To guarantee correct
restart, the BnCOK pulse must be at least 100 fJ,S
wide. BPOK should remain inactive during this reset
operation.
8.4.6 Local
The on-board local interrupts are listed in Table 8-2 and use a coded input on the AI-1 through AI-5
inputs to the microprocessor. Some of these interrupt functions are determined by the user when configuring the module. There are eight local interrupts which are all maskable. The multiple interrupts
are arbitrated, and the interrupt with the highest priority is serviced by the microprocessor. All local
interrupts initiate an IAK transaction, and their vector addresses are internal to the microprocessor ..
During IAK, the serviced interrupt is driven on TDAL lines 11-8 to address the interrupt acknowledge
PROM. The outputs of the PROM reset the interrupts. TDAL bits 7-0 are ignored. The microprocessor pushes the present PSW and PC onto the stack and receives a new PC and PSW from the
vector address location and the next location.
8.4.7 External
A level 4 LSI-II bus interrupt also uses a coded input on the AI-1 through AI-4 inputs to the microprocessor. The interrupt is maskable. For the bus interrupt, the AI-5 input to the microprocessor is
taken low to indicate that the vector address must be read from LSI-ll bus bits 7-2. :rhe microprocessor does an IAK transaction and places the BDIN and BIAKO signals on the bus to the requesting peripheral device. This device responds with - BRPLY, and the vector address is read from the
LSI-II bus. The microprocessor pushes the current PC and PSW onto the stack and reads a new PSW
and PC from the vector address location and the next location.
If the interrupting peripheral device fails to assert the BRPLY bus signal within 10 fJ,S after BDIN is
asserted, the module time-out signal TMER is enabled. The microprocessor completes the IAK transaction and receives a vector address of zero because there is nothing driving the bus. The new PSW and
PC are then read from locations 0 and 2. Optionally, the user can connect the time-out signal TMER to
the HALT interrupt, and the interrupt can then be processed. The HALT interrupt pushes the current
PSW and PC, which were read from locations 0 and 2, onto the stack and then loads the PC with the
restart address and the PSW with 340. If the HALT is ignored for the vector time-out, only a vector
through locations 0 and 2 will occur.

8-22

8.4.8 DMA Interrupt
The DMA request is connected to the AI-O input to the microprocessor. The DMA request is received
by the microprocessor during any read, write, fetch, or ASPI transaction. The request is not acknowledged by an IAK transaction, but is acknowledged by the microprocessor asserting the SELO and SELl
outputs to initiate a DMA transaction. (See Paragraph 8.15 for a discussion of DMA transactions.)
8.5 DC004 PROTOCOL
The DC004 protocol logic chip (see Figure 8-1, sheet 1) interfaces the LSI-ll read/write signals with
the module read/write signals. The -CSQB input goes high and is strobed by RSYNC to enable the
logic. The BDIN L input goes low to request read data and switches the - READ output low. The.
BDOUT L input goes low to strobe write data and switches the - WHB and - WLB outputs low if the
BWTBT L input is high. When the BWTBT L input is low, the BDALO L input will select either the
- WHB or the - WLB. A low on the BDALO L input switches the - WLB output low. The BRPLY L
output is controlled by the -CSQB input. When -CSQB input is high, this indicates that the LSI-II
bus was not selected. The BRPLY L output is enabled and is switched low, after an RC delay, when
BSYNC L and either the BDIN L or BDOUT L outputs are switched low. If the -CSQB input is low,
the LSI-ll bus is selected and the BRPL Y L output is disabled. The BDALO, 1, and 2 inputs control
the - SEL6 output. The output goes low when the BDALI Land BDAL2 L inputs are low and the
BDALO L is high.
8.6 ADDRESS LATCH
The address latching logic (see Figure 8-1, sheet 1) has sixteen transparent latches designated E48 and
E56. The latches are always enabled by grounding the output control input. The TDAL bus bits 1-15
and the I/O page select signal RBS7 are monitored. The status of inputs is latched to the address bus as
bits ADI through AD15 by the RSYNC input going high. The address bus and the latched LBS7 signal
go to the memory address decode logic. The address bus is common to the module memories and the
I/O circuits and remains stable while RSYNC is asserted.
8.7 MEMORY ADDRESS DECODE
The memory decode logic (see Figure 8-1, sheet 1) has a field programmable logic array (FPLA) that
decodes the applied address bits and the latched LBS7 signal. The FPLA selects a predetermined output according to the selected memory map. The module address range includes the on-board memory,
the I/O interface registers, and LSI-II bus addresses. Four different memory maps, described in Figure 8-15, are available to the user. The M25 and M2I wirewrap pins, described in Chapter 2, allow the
user to select one of these maps. The FPLA is enabled if the DCLO input is low. An address location in
the RAM memory enables the - CSRAM output, and an address location of either socket set A or B of
PROM enables either the -CSKTA or -CSKTB outputs. A register address for either SLUI or
SLU2 will enable the -CSDLO or -CSDLI outputs. The -CSPL output is enabled when a register
of the parallel I/O logic is addressed. The -CSLIP output is low for all the above address conditions.
The -CSLIP output goes high only when the address is accessed on the LSI-ll bus and the -CSQB
output is enabled low. The -CSLIP output allows the processor to cycle slip during the LSI-ll bus
read/write and IAK transactions.
8.8 RAM MEMORY
The static RAM memory, shown in Figure 8-16, is a 2K X 16-bit memory that has a 2K X 8-bit high
byte chip and a 2K X 8-bit low byte chip. The memory is selected by the -CS RAM input going low
to the CS pin. The memory is addressed by address bits AD I-AD 11, and 16-bit data is read from or
written to via TDAL bits 0-15. The memory is read by the -READ input going low to produce a low
input to the OE pin of the memories. The - WLB selects the low byte, and the - WHB selects the high
byte. The - WHB and - WLB inputs to the WE pin enable the write function, and - READ input
goes to the OE pin of the memories to enable data output during read.

8-23

MAPO
64KB

56KB

(NOTE 3)
2KB (NOTE 1)
4KB LOCAL RAM
(NOTE 2)

4BKB

MAP2

MAP 1
64KB

64KB

MAP3
64KB

(NOTE 3)

4KB LOCAL RAM
(NOTE 2)

56KB

4BKB

LSI-11 BUS

40KB

32KBI-

32KB

24KB

16KB

16KB SOCKET A

BKB SOCKET A
BKB,-

8KB

16KB SOCKET B

4KB SOCKET A
8KB SOCKET B
4KB SOCKET B
OKB

OKB

NOTES:
1. SOCKET SET A IS MAPPED OVER SOCKET SET B AND IS
THEREFORE LIMITED TO USING EITHER SOCKET A OR
SOCKET B, BUT NOT BOTH TOGETHER.
2. ADDRESSES 160000 THROUGH 160007 ARE ASSUMED TO
RESIDE ON THE LSI-11 BUS.
3. THIS SECTION CONTAINS THE LOCAL I/O ADDRESSES FOR
THE SLUs AND PPI. ALL UNASSIGNED ADDRESSES ARE
ASSUMED TO RESIDE ON THE LSI-11 BUS.
MR·6643

Figure 8-15

Memory Maps

8-24

-READ

-WHB

-CS RAM

CS
AD1-ADll

STATIC RAM
HIGH BYTE
2K X 8
XE53

-')
....

(TDAL08-15

....

TDALOO-'-[)

....

-CS RAM
-WLB

~TDALOO-07
RAM
CS STATIC
LOW BYTE

- 2K X 8

XE38
-READ

MA-751B

Figure 8-16

RAM Memory

8.9 ROM/RAM MEMORY SOCKETS
The ROM/RAM memory, shown in Figure 8-17, provides the user with four 28-pin sockets to accept
either 24-pin or 28-pin industry standard +5 V chips. The sockets can hold up to 32Kb ofUV PROMs,
PROMs, or ROMs and up to 8Kb of static RAM. The socket sets are defined as A and B, and each has
a high byte socket and a low byte socket. The sockets use the -CSKTA and -CSKTB outputs from
the memory address decode (see Figure 8-15 for the memory maps). The -READ, - WHB, and
- WLB signals from the DC004 protocol are used to provide a high byte chip enable (HBCE) and a
low byte chip enable (LBCE). There are thirty wirewrap jumper pins available for the memory configuration. See Chapter 2 for detailed information.
NOTE
When a memory chip is placed into a socket wired
for a larger capacity part, for example a lK X 8
chip in a 2K X 8 socket, the addresses above the lK
boundary will wrap around into the start of the
memory. This should be noted when selecting the
memory map configuration.

8-25

-READ

M64

-WHB

M56

TDAL 00-15

-CSKTA
M41

-CSKTB
M34

-WLB

M57

READ

M31

0
0

M43

M44

M36

AD12
22
LOW BYTE
28-PIN
20
SOCKET A
XE44
26

M38
M7

M42
2

AD13

22
HIGH BYTE
28-PIN
M55
M46
20
SOCKET A
GND
XE54
26
+5 V NCR

;J
Z1

M62
22
LOW BYTE
28-PIN
20
SOCKET B
XE45
27

M48

M33

22
HIGH BYTE
28-PIN
20
SOCKET B
27 XE55

M35

M63

M32

M45

AD11

M47
21

MR-7510

Figure 8-17

ROM/RAM Memory Sockets

8.10 SERIAL LINE INTERFACE UNITS
There are two asynchronous serial line units, SLUI and SLU2, that provide serial I/O interface
through 11 and 12 as shown in Figure 8-18. Configurations are discussed in Chapter 2.
The SLUs transmit or receive 8-bit, byte-oriented data, with no parity, one start bit, and one stop bit.
SLUI provides the XDLI and RDLI interrupts for transmit and receive and the BREAK output that is
wired to pin M 17. The user can jumper the BREAK output to the HALT interrupt (pin M20) and use
SLUI as a system console. SLU2 provides the XDL2 and RDL2 interrupts for transmit and receive
and three real-time clock interrupts at 50 Hz, 60 Hz, and 800 Hz. These interrupts are wired to pins
M27, M19, and M28 for use with the TEVNT interrupt (pin M23).
When the serial line units are addressed, the -CSDLO input selects SLUI and the -CSDLI input
selects SLU2 by enabling the chip select (CS) inputs. Address bits AD2 and ADI are used to select
individual registers within the SLUs. These registers are listed in Table 8-3 with their address and the
logic states for AD2 and ADI to access them. The -READ input will read the 16-bit register selected
by -CSDLO or -CSDLl, AD2, and ADl by placing the contents onto the TDAL bus if the - WLB
input is not asserted low. When asserted low, the - WLB input will write the low byte of the TDAL bus
into the register selected by -CSDLO or -CSDLl, AD2, and ADl. However, only the register bits
defined as read/write will be written into. The DLCLK input is a crystal-controlled clock reference
used by the SLU to generate baud rates and real-time clocks. The BCLR input is asserted during a
RESET instruction; the RCVIE bit of the RCSR register and the XMITIE, MAINT, and XMIT BRK
bits of the XCSR register are reset. When the DCLO input is asserted during power-up, it disables all
SLU outputs and resets all internal logic and registers. The baud rate will be set at 300 baud after the
SLU is initialized by DCLO.
The RS232 and RS423 signals for the interface connector are provided by 9636 (E42) and 9637 (E30)
dual line drivers and dual line receivers. The slew rate for both channels is controlled by resistor R6.
The factory configuration uses a 22 kQ resistor to provide a 2 ILS slew rate for operating at a 38.4K baud
rate. See Chapter 2 for the configuration requirements at other baud rates.

8-26

BREAK OUT ~7

-CSDLO

.--

M20
D--THALTH

+12F- 10

BRCLK

SLU 1
DLART
XE58

E42·-

RCVIRO ~RDLI
XMITIRO ~XDLI

DC LO
BCLR
AD2
AD1
-WLB
-READ
DLCLK

7
E39f

8
TR8

-12V.....- 2
~ 4

~5
~

"---

.....
TDALOO-1V

~
~
BRCLK
SLU 2
DLART
XE59

+12F- 10
1

~
E42 ~

""'"

....

RCVIRO f-"+RDL2
XMITIRO f--+XDL2

E3~r

M27

-CSDL1

50HZ
60HZ
800HZ

~R7
~9 M23
D--TEVNT H -12V

r--

I--- 5
I--- 9

-=
DLCLK

L-

04
E49
05
4.3 V

+5 VDC
Zl
E49

MR-7525

Figure 8-18

Serial Line Interface Units

8-27

Table 8-3 Serial Line Unit Registers
Register

Description

Address

AD2

ADt

SLUI
RCSR
RBR
TCSR
TBR

Receiver control/status
Receiver buffer
Transmitter control/status
Transmitter buffer

177560
177562
177564
177566

0
0
1
1

0
1
0
1

SLU2
RCSR
RBR
TCSR
TBR

Receiver control/status
Receiver buffer
Transmitter control/status
Transmitter buffer

176540
176542
176544
176546

0
0
1
1

0
1
0
1

8.11 PARALLEL I/O INTERFACE
The programmable parallel I/O provides a 30-pin connector for transferring parallel data into or out of
the SBC-ll/21 module. The parallel I/O uses an 8255A-5 programmable interface chip, two 8-bit
transceiver chips, and an 8-bit buffer chip as illustrated in Figure 8-19. The 8255A-5 chip has three
input/output ports defined as port A, port B, and port C. Port A and port B outputs are connected to 8bit bidirectional transceivers that are controlled by wirewrap pins M49 and M52. When a logical one is
applied to these pins, the data lines function as inputs to the module. When a logical zero is applied to
these pins, the data lines function as outputs from the module. The user can configure these as inputs or
outputs by using wirewrap pins M51 and M50 or as programmable inputs/outputs by programming the
PC4 and PC6 lines (M54, M58) of port C as described in the configuration description in Chapter 2.
The port C outputs are connected to directional buffers and are used for interrupts and the handshake
control for ports A and B. PCO and PC3 are wired as outputs, PC3 enables the parallel interrupt request
for port A, and PCO enables the parallel interrupt request for port B. PC4 and PC6 can be used as
acknowledge or strobe inputs or can be configured to dynamically control the direction of ports A and B
from either the 8255A-5 interface or the external peripheral device. PC1, PC5, and PC7 are wired as
outputs, and PC7 is wired to an LED that can be program controlled. PC2 is wired as an input and has
a current limiting resistor for protection when PC2 might be programmed as an output from the 8255A5 interface. See Chapter 2 for detailed configuration requirements and Chapter 6 for programming
information.
The 8255A-5 programmable peripheral interface (PPI) is enabled by the -CSPL input from the memory address decode chip when the 176200-176207 addresses are selected. The ADI and AD2 address
lines are decoded to select one of the four registers listed in Table 8-4. The port A, port B, and port C
registers are read/write registers, and the control word register is a write only register. The addressed
register is written into with the data on the TDAL 7-0 bus when the - WLB input is asserted. The
content of the addressed register is placed on the TDAL 7-0 bus when the - READ input is asserted.
The -SEL6 L input to NAND gate E35 inhibits the read strobe from the control word register, and
therefore, any read of the control word register produces invalid data to the microprocessor. Only the
low byte of the TDAL bus is used with the PPI, and any data on the high byte is always considered
invalid. The - BCLR input is used to reset the PPI when it is asserted, and all twenty-four 8255A-5
I/O lines are then defined as inputs. The buffer outputs to the connector will be driven high.

8-28

,..-PC3

r---------,
1

,PCO

I
9

PCO ~---4~~----~

I
1

PCl ~--~--------~--~
Rl0
PC2 ~----~~----~l~----<
ADl

AD2

-CSPL

--Cl CS

-WLB

E21

'"\...,..

..:_~SE=.:L:...;6~_E_35.....,./ RD

PC7

XE60
00
I

tv
\0

rTDAL 00-07 ")
r

~------~----------------~ 4

~----~----------------~ 5

PC5 ~------------~
M54
M53 TI
PC6 - - 0
::

~--+_----------------~7

~---------~il

E61
I
I _ _ _ BUFFERS
L
_ _ _ _ _ _ -oJI

8255A-5
PROGRAMMABLE
PERIPHERAL
INTERFACE

~L-----------------~10

I
I

M58
PC4 - - 0

RESET

READ
-READ

PC3

-C WR

-BCLR

L.@-+5V

.----- 1
I-- 2
I - - 15
I - - 16

-==
BO
AO ~----------------~12
A3 ~----------------~14
B3
A5 ~----------------~18
B5
BUS
B7 TRANSCEIVERS A7 ~----------------~20
A6 ~----------------~19
B6
E50
B4
A4 ~----------------~17
B2
A2 ~----------------~13
Bl
Al ~----------------~11
DIR
r-29

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
M49

+3V OM50

~30

GNDOM51
B6
A6~----------------~27
B4
A4
25
B2
BUS
A2
23
BO TRANSCEIVERS AO
21
Bl
Al
n
E62
B3
A3
24
B5
A5
26
B7
A7
28
DIR
i....-

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
M52
E49

PJl
r-.
Rll

Figure 8-19

I
t

-=L.C22

Parallel I/O Interface

MR·7524

Table 8-4

PPI Addressable Registers

Address

Status

PortA
Port B
PortC
Control word

176200
176202
176204
176206

Read/write
Read/write
Read/write
Write only

8.12 POWER-UP
The power-up circuits (Figure 8-20) sense the application of + 5 V NCR power source to the module
and initiate a power-up sequence. When the + 5 V NCR input is first applied, the input at the inverter
E21 is low and causes the clear input of the PUP flip-flop E29 to be low, therefore keeping its output
low. When the input to the NAND gate E35 is low, the - PUP output is high and the microprocessor is
held reset and asserts the - BCLR output. The + 5 V NCR input charges C8 through R4 until the
threshold level of inverter E21 is reached. This occurs at approximately 2.6 Vdc and 70 ms after + 5 V
NCR was applied. This causes the reset input to the PUP flip-flop to go high and the set input to go
low, setting the flip-flop. The -PUP output of the NAND gate E35 goes low. This initiates the powerup sequence of the processor.
The power-up delay circuit can be bypassed by inserting a jumper between M4 and M6. This allows the
BDCOK Hand BPOKH bus signals to control the PUP output. The +5 V NCR input goes directly to
the inverter E21 driving input to the NAND gate E37 low. The E37 output is then controlled by
BDCOK. The BDCOK H signal is low until the power supply stabilizes, causing the reset input to the
PUP flip-flop to be low. The BPOK H signal is also low and causes the preset input to the flip-flop to be
high. The low input to NAND gate E35 drives the - PUP output high. The microprocessor then asserts
the -BCLR output resetting the PFAIL flip-flop. After a minimum of 3 ms, the BDCOK bus input
goes high and allows the PUP flip-flop E29 reset to go high. After a minimum of 70 ms, the BPOK H
bus input goes high causing the PUP preset input to go low. This allows the output to go high, and when
both inputs to NAND gate E35 are high, the -PUP output is low. This initiates the power-up sequence
of the microprocessor.
The BPOK H bus input also goes to the PFAIL flip-flop E32. During the power-up sequence, - BCLR
resets the PFAIL flip-flop. The flip-flop remains reset until the BPOK input goes low indicating a power fail. The next CAS input clocks the PFAIL flip-flop and sets it. This causes the power fail interrupt,
and the microprocessor traps to location 24. The flip-flop must be reset for at least one microprocessor
read before another assertion will be recognized by the microprocessor.
8.13 CLOCK
The module uses a 19.6608 MHz crystal oscillator as the basic time base reference. The oscillator output goes to the clock control logic (see Figure 8-21) and to the E23 binary counters. The counters are
always enabled. The 19.6608 MHz output is divided by 32, and the DLCLK output, at 614.4 kHz, goes
to the serial line units and to the charge pump. The 19.6608 MHz output is also divided by 4, and the
4.91 MHz output goes to the pulse sync circuit E22. When the TCLKSP input is low, the circuits are
enabled and the output goes to the next pulse sync circuit. When the TCLKSP input is high, the circuits are inhibited and there is no output. The second pulse sync circuit is controlled by the PUP input.
When the PUP input is low, TCLK to the XTLI input is enabled. When the PUP input is high, the
XTLI input is inhibited.

8-30

BPOK H
E32
CAS.~

____________________________________________________~______~

-P FAIL

-B ClR

r-I
I
I

-;'A-;;;U~R7t;;T'

E29

-PUP

DC LO

IL _ _ _

_ _ ..J

BDCOK H

_____________________________________- - - - XlB

E36 PIN 6
E21 PIN 8

BDCOK H

E37PIN 15

BPOK H

E51 PIN 13

BINIT l

E18PIN 4

-8ClR

E25 PIN 18

-PUP

E35PIN 8

- -TClK

E22 PIN 17

SIGNALS DURING POWER"UP
MR-7504

Power~up

Figure 8-20

SClK

DIVIDE
t-BY 16
E8

119.66 MHZ
OSC E2

"W1,..

DIVIDE
BY 2

DlClK

DIVIDE
8Y 4

t--

E15

f---

E15

-TClK

TCLKSP
-PUP
MR-6649

Figure 8-21
8-31

Clock

8.14 CLOCK CONTROL
The clock control logic (Figure 8-22) stops the XTL1 input to the microprocessor and forces the microprocessor to stop or wait until the XTL1 input is enabled again. The TCLKSP output is normally low to
enable XTL1 and is controlled by the TMRP input being high. TMRP forces a low for both inputs to
the OR gate E2, and the low output is clocked through the TCLKSP flip-flop by the 19.6 MHz input.
When TMRP goes low, this removes the low inputs to the AND gate E13 and the IAK flip-flop E3. The
TSYNC input is high for read/write and fetch transactions, and when the -CAS input goes high, the
AND gate E13 output also goes high. The output of AND gate E13 is clocked through the TCLKSP
flip-flop, and the output goes high to stop the 4.91 MHz clock output of E22. The TSYNC input is low
for DMA and IAK transactions so that input to the AND gate E13 holds the output low. However, the
IAK flip-flop E3 is set when the - IAK clock input goes high at the end of an external interrupt transaction and the E2 output goes high. The E2 output is clocked through the TCLKSP flip-flop, and the
output goes high to stop the 4.91 MHz clock output of E22. The microprocessor XTLI input will stay
stopped until the TMRP input goes high again because either BRPLY or TMER have been negated.
This forces the IAK flip-flop E3 output to go low. This negates the TCLKSP output and enables the
XTLl input to the microprocessor.
8.15 DMA
The DMA logic (Figure 8-23) controls the bus and microprocessor for DMA transactions. The BDMR
L input goes low to start a DMA request. The output of the inverter goes high and is clocked through
flip-flop E25 by COUTo The low output goes to the El5 NOR gate, and the high output goes to flipflop E25. The high output is clocked through by COUT and enables the two NAND gates E24 and El.
The high output is also clocked through flip-flop E32 by the CAS input. The high output enables the
NAND gate E35, and the -CDMRQ output (AI-O input) is switched low. The -CDMRQ output is
the DMA interrupt to the microprocessor and it starts a DMA transaction. The microprocessor acknowledges the request by setting SELl and SELO high to NAND gate E24. The preset of flip-flop E8
goes low to set the DMG output high and the - DMG output low. The DMG high input to NAND gate
E35 switches the output low and goes to NOR gate E15. The BSACK L input is normally high and,
when inverted by E52, is a low input to the NOR gate E15. All three inputs to the NOR gate E15 are
now low causing the output to switch high. Two high inputs to the NAND gate E1 switch BDMGO low
on the bus to the originator of the DMA request. The requesting device then sets the bus signal BSACK
L low and the BDMR L input high. BSACK L is inverted by E52 and removes the low from the NOR
gate E15 and the high input to the NAND gate El causing the BDMGO output to go high. It also
provides a high input to NAND gate E24 causing the output to switch low. This low goes to the preset
input of the flip-flop E25 and clamps the output high; this holds the microprocessor in the DMA mode.
The requesting device maintains the BSACK L input low for the duration of the DMA transfer and
then sets it high. This removes the low from the preset input of flip-flop E25 and enables the flip-flop.
Previously, the BDMR L input went high and was inverted as a low to flip-flop E25. This low was
clocked through by COUT and provided a low input to the enabled flip-flop E25. The low is now
clocked through causing the -CDMRQ output to go high. This removes the request from the microprocessor. The microprocessor completes the DMA interrupt transaction and negates the SELl and
SELO outputs. The preset input of flip-flop E8 is no longer low, and the low data input is clocked
through when RAS goes high. The DMG output goes low, and the -DMG output goes high to complete the DMA transaction.

8-32

TSYNC
-CAS

E13

+3 V
T ClK SP
E5
-TClKSP

E3
-IAK
+3V
-TMRP
E5
-DRRPlY

S ClK
-BClR

.-•••-_-.__- _-.-.-_••-_-.-_-••: _._.::_-_-_-.-.-.-.-_-_-.-.-_-.-_-.-_-_-::.- SClK

E23 PIN 13
E23PIN 10

_ _ _ _ TClKSP

E22 PIN 13

-TClK

E22 PIN 7

TSYNC

E4 PIN 5

-CAS

E46PIN 15

DRRPlY

E13 PIN 3
E13 PIN 12

TSYNC

E4 PIN 5

DRRPl Y

E5 PIN 5

-IAK

E3 PIN 11

-CAS

E13 PIN 5

TClKSP

E22 PIN 13
E22 PIN 11

-TClK

E22 PIN 7

SIGNALS FOR CLOCK CONTROL
MR-7508

Figure 8-22

Clock Control

8-33

B DMR l

B SACK l

E52>--+-----+-----il--Jyr--...,
BDMGO

COUT

-CDMRQ

CAS
-BClR
SEll
SElD
DMG
-DMG

-RAS

~---------------------------------RDMR

- - - - - -- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - " COUT
DMRQ

E47 PIN 3
E25PIN 3
E25 PIN 5
E25 PIN 9

________- - - - - - - - - - - - - - - - - - - -_______ SEll

E32PIN 9
E32PIN2
E46PIN 13
E46PIN 6

DMG
_ _ _ _ _ _- - - - - - - - - "_ _ _ _ _ _ RSACK
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TDMGO
_ _ _- ____-_-_-_-_-_---:-_-_-___-_-RAS

EB PIN 5
E15 PIN 9
E15PIN 8
E8 PIN 3

CAS

:::::~====::::::::::::::::::::::~::::::CDMRQ
SElD

-- -- ------- -

========~~~~~~~~~====:::XHB

E6 PIN 6
E12PIN 12
E16PIN8
E16PIN 12

SIGNALS FOR DMA LOGIC
MR-7503

Figure 8-23

8-34

DMA

8.16 TSYNC
The TSYNC output (Figure 8-24) is normally high for the microprocessor controlled fetch/read and
write transactions and low for IAK and DMA transactions. These conditions follow the -SELl input
which is high and low for the same transactions. The exclusive OR gate E31 is wired as a noninverting
buffer, and when RAS goes high, the -SELl input of the TSYNC flip-flop E4 is clocked through as
the output. When the -CSYNC clear input goes low, it forces the output of the TSYNC flip-flop E4
to go low. The CSYNC flip-flop E4 normally has the clear input pulled low by TCLKSP and, the output to the AND gate E6 is high. When the TCLKSP input goes high, the input of the CSYNC flip-flop
is enabled. At this time, the - DRRPLY clock input is low and goes high to clock the flip-flop before
the TCLKSP input gets reset. If a DMA transaction is in progress, the - DMG input is high and the
CSYNC flip-flop output stays low when clocked by - DRRPLY going high. For any transaction other
than the DMA, the -DMG input is low and the CSYNC flip-flop output goes high when clocked by
- DRRPLY going high. This allows the CSYNC output to go high and clear the TSYNC flip-flop E4,
the write byte flip-flop E3, and the disable flip-flop E7 as shown in Figure 8-25.

+3 V
-SELl

TSYNC
E4

RAS

-T SYNC

+3 V

-DMG
E4

-DRRPLY
-C SYNC
TCLKSP
-BCLR
MR-7511

Figure 8-24 TSYNC
8.17 READ/WRITE
The read/write logic (Figure 8-25) controls the read, write, and fetch transactions for the microprocessor and supports the IAK and DMA transactions. The microprocessor controls the R/ - WLB
and R/ - WHB inputs to select either BDIN, BDOUT, or BWTBT bus signals. To select the BDIN
output, the microprocessor sets both R/ - WLB and R/ - WHB inputs high to NAND gate E24. The
output goes low to enable the NOR gate El5 and disables the AND gates El2 and E6. The - TSYNC
input to El5 is low for read/write transactions. When the -CAS input goes low, the TREAD output
goes high. The TDIN output of OR gate E14 goes high, and the BDIN output of NAND gate El5 goes
low. The - DMG input to the NAND gate is always high except for DMA transactions. During interrupt transactions, the IAKDIN input to El4 is enabled high and causes TDIN to go high and BDIN to
go low.
The microprocessor determines any write condition by setting either or both the R/ - WLB or
R/ - WHB inputs low. The output of NAND gate E24 goes high and enables the AND gates E6 and
E12. The output of flip-flop E7 is high, and the -CAS input to AND gate El2 is high. The output of
AND gate El2 goes high, and the output of OR gate E2 goes high. The DMA input to NAND gate EI
is high and allows the BWTBT output to go low. At this time, the write destination address is written

8-35

-DMG
[;+3 V
-SEL1

f--

-RAS

JE26

-PI

.,..

-CAS

....

",-BWTBT

E12 } - - - ) . :

,.......,
j;+3V

) E31
E3

r----J

-CSYNC

- E1~ -

R/WLB
R/WHB

TREAD

E24 " ' -

-T SYNC

J E1)--r-

BDIN

TDIN

IAKDIN
TDOUT

E6~

CAS
TSYNC
PI

BDOUT

E13

- - --- --- -- -------- - - --- -RAS
TSYNC
--------------- - -- -- -- -CAS
TDIN

E46 PIN 4
E4 PIN 5
E46 PIN 15
E14 PIN 3

PI
TDOUT
R/-WLB
R/-WHB

E31 PIN 10
E6 PIN 8
E31 PIN 2
E24 PIN 4

WBYTE
WRITE
WT
-CSQB

E3 PIN 2
E24 PIN 6
E12 PIN 6

---

-----~

---------~

E39 PIN 16

-CSLlP
E6
-NO BYTE E7
E3
TWTBT
E2

PIN 1
PIN 6
PIN 5
PIN 6,

SIGNAL FOR READ/WRITE LOGIC
MR-7505

Figure 8-25

Read/Write

8-36

onto the bus. The logic now determines if the data being written is a word or a byte. The exclusive OR
gate E31 monitors the R/ - WLB and R/ - WHB inputs, and the output goes high when the inputs are
different. A high output indicates that the data is a byte; a low output indicates that the data is a word.
The output goes to flip-flop E3.
The microprocessor asserts CAS. The CAS input to E3 and E9 goes high, and -CAS input to EI2goes
low. The -CAS input to AND gate El2 switches the output low to remove BWTBT, but the CAS
input clocks flip-flop E3 and enables the WBYTE signal to E2. The output of the flip-flop E3 is high for
byte transactions and low for word transactions. The BWTBT L signal will either stay asserted low for a
byte transaction or be negated high for a word transaction. The TSYNC and CAS inputs to AND gate
El3 are set high, and when the PI input goes high, the gate output goes high. The AND gate E6 is
enabled, and the output of E13 switches the TDOUT output high. The TDOUT is inverted. The
BDOUT output is enabled by going low and it writes the data word.
At the same time, the -RAS and -PI inputs to NOR gate E26 are both low, switching the output
high. The high clocks flip-flop E7, and the output goes low. This inhibits the AND gate El2 when the
- CAS input goes high again. The flip-flops are reset by CSYNC at the end of the transaction.
8.18 REPLY TIME-OUT
The reply time-out logic (Figure 8-26) monitors the bus BRPLY L input to indicate that an LSI-ll bus
device responds to an address. The TMER flip-flop E29 output is normally set low by the RAS input to
clear the flip-flop. The BRPL Y L input is high and inverted so the RRPLY output is low. The
- TMRP NOR gate inputs are both low, and the - TMRP output is high. The bus transaction is
started by either TDIN or TDOUT inputs going high. This enables the 10 /.LS time-out (50 cycle slips)
monostable multivibrator to start. The microprocessor starts to cycle slip while waiting for the BRPLY
L input to go low, indicating the bus transaction can complete. When BRPLY L switches low, the
RRPL Y output goes high and the - TMRP output goes low. The TMER output stays low. If the
BRPL Y L does not go low and the 50 /.LS time-out circuit allows the 50 cycle slips, the TMER flip-flop
is clocked and the TMER output goes high. TMER also forces the - TMRP output to go low. The
assertion of the TMER output goes to the halt logic, and the microprocessor action is dependent upon
the configuration of the module. The - TMRP output goes to the clock control and the ready logic. The
RRPLY output goes to the bus control logic and enables bus data to be received during LSI-ll bus
device reads.
8.19 BUS CONTROL
The bus control logic (Figure 8-27) controls the transmit and receive functions of the bus transceivers.
The transceivers are in transmit mode for microprocessor controlled read/write a~d fetch transactions
to local memory, local I/O, and during LSI-II bus writes. The transceivers go to the receive mode
during an LSI-ll bus read. During DMA, the transceivers go to the receive mode to accept the local
device address and will stay in this mode until the device is addressed. When a read transaction occurs,
the transceivers go into the transmit mode. When the - BCLR input is high, the transceivers are able
to transmit data. When - BCLR is asserted low, the transceivers are disabled. During an IAK transaction, the - IAK input to AND gate E 12 goes low to disable the transceiver high byte, and the low byte
goes to the receive mode to accept the vector.
The receive function of the bus transceivers will override the transmit function any time the receive
inputs are enabled high. When data is to be read from an LSI-ll bus device, the -CSQB input is low
and inverter E21 makes it a high input to AND gate EI2. The TREAD input to AND gate EI8 is set
high for the receive function. When the data is on the bus, the RRPLY input to AND gate El2 goes
high and the output of the gate goes high. The two OR gates E2 allow the high output to enable the
receive low byte and receive high byte inputs to the transceivers. The data is now read onto the TDAL
bus. During an interrupt transaction, the TIAKO input goes high and enables only the receive low byte
input of the transceivers.

8-37

RRPLY

-TMRP

BRPLY L

TMER
E29

R5
+5 --w_--.

TDIN

TDOUT

RAS
MR-7502

Figure 8-26

Reply Time-out

The DMA transaction grants bus control to the external device that requested the direct memory grant.
The DMG input goes high for the duration of the DMA transaction. This input enables AND gate E6
and NAND gate E16. The BSYNC L input is high and inverted low to the two NAND gates E16. This
switches the NAND gate outputs high, and the receive and transmit functions are both enabled. However, the receive function overrides the transmit function, and the TDAL bus receives data from the
BDAL bus. This condition stays until the bus master asserts the BDIN L input low. It is inverted high
and enables the NAND gate E16. The -CSQB input is dependent upon the address received from the
BDAL bus. This input is low if the address is a bus location and high if the address is for the local
memory or I/O device. A low input sets the output of NAND gate E16 high and enables the receive
function of the transceivers. At the same time, the -CSQB low input is inverted high, and the output
of NAND gate E16 is switched low to disable the transmit function. When the -CSQB input is high
indicating the local memory is being addressed, the NAND gate E16 is enabled. The -CSQB high
input is also inverted low to NAND gate E16 and enables the receive function. The bus master now
asserts either BDIN L or BDOUT L bus signals. The - READ input goes low for the BDIN L signal
and goes high for the BDOUT L signal. If - READ goes high, it is inverted low and switches the output of NAND gate E16 high to enable the receive function. If -READ goes low, it is inverted high
and switches the output of NAND gate E16 low to inhibit the receive function. The transmit function
stays enabled. Therefore, when the bus master asserts the BDIN L bus signal, the data is transmitted
from the module and when it asserts the BDOUT L bus signal, the data is received by the module even
if it was not addressed.
The BBS7 L bus signal is enabled low when the bus addresses the I/O page during the address part of a
transaction. This is the upper eight kilobytes from 56Kb to 64Kb. This page is normally reserved for
I/O devices on the LSI-ll bus, but the 4Kb of local RAM memory reside within this page. It is also
possible to have an additional 2Kb of memory within this page.
To address this page, the TDAL bus bits 13, 14, and 15 are set high and are inputs to NAND gate E34.
The output is switched low and goes to the NOR gate E26. The SELl input to NOR gate E26 is low for
read, write, and fetch transactions. When both inputs to NOR gate E26 are low, the output is switched
high. This is inverted to a low for BBS7 L output and is inverted again to set RBS7 high.

8-38

TDALO-15

BDAL 0-15

TIAKO
DRRPL Y
TREAD
005
-CSQB

BUS
TRANSCEIVER

READ
LOW BYTE
(E43, E47)
DMG

HIGH BYTE
(E51, E52)

TSYNC
00
I
W

-BCLR
XHB
-IAK
B INIT L
TDAL13
TDAL14
TDAL15

-RSYNC
E34

RBS7
BBS7L

SELl

MR-7521

Figure 8-27

Bus Control

CHAPTER 9

LSI-II BUS

9.1 INTRODUCTION
The LSI-ll bus provides interconnections for LSI-ll type modules, such as processors, memories, and
interfaces, to communicate with each other. Not all of the bus functions are supported by the SBC11/21, and only the supported functions are described in this chapter. For a complete explanation of
the LSI-II bus, see the PDP-ll Bus Handbook.
The LS I-II bus has forty signal lines: eighteen are used for data and twenty-two are used for control.
The SBC-II/21 supports only sixteen data lines and eighteen control lines.
There are four groups of control lines.
I.

Six data transfer control lines:
a. BBS7
b. BDIN
c. BDOUT
d.BRPLY
e. BSYNC
f. BWTBT

Four direct memory access control lines:
a. BDMGI
b. BDMGO
c. BDMR
d. BSACK

Six interrupt control lines:
a. BIAKI
b. BIAKO
c. BIRQ4
d. BIRQ5 (not used by SBC-1I/21)
e. BIRQ6 (not used by SBC-II/2I)
f. BIRQ7 (not used by SBC-II/2I)

Six system control lines:
a. BDCOK
b. BPOK
c. BHALT
d. BINIT
e. BREF (not used by SBC-II/21)
f. BEVNT

9-1

Most LSI-II bus signals are bidirectional and use terminations for a negated (high) signal level. Modules connect to these lines via high impedance bus receivers and open collector drivers. The asserted
state is produced when a bus driver asserts the line low. Although bidirectional lines are electrically
bidirectional (any point on the line can be driven or received), certain lines are functionally unidirectional. These lines communicate to or from a bus master or signal source, but not both. Interrupt acknowledge (BIAK) and direct memory access grant (BDMG) signals are physically unidirectional in a
daisy chain. These signals start at the processor output signal pins. Each is received on device input pins
(BIAKI or BDMGI) and conditionally passed on via device output pins (BIAKO or BDMGO). The
BIAK and BDMG signals are received from higher priority devices and are passed onto lower priority
devices along the bus.
9.2 SBC-H/21 SINGLE-BOARD COMPUTER
The SBC-II/21 module functions on the LSI-II bus and can act as a bus master, a bus slave, or a bus
arbitrator. The module allows a DMA master to access the on-board functions. It supports only sixteen
data/address lines and terminates the other lines. It also contains its own on-board memory and accesses the bus for external memory or devices. However, while accessing its on-board devices, the SBC11/21 asserts bus control signals as it does when communicating with the LSI-ll bus. The memory
maps defining on-board and external addressing are described in Chapter 2. The SBC-ll /21 microprocessor supports an on-board multilevel interrupt structure, and the BIRQ4 bus interrupt control line
is an active bus interrupt with a level 4 priority. Therefore, the BIRQ5, BIRQ6, and BIRQ7 bus control
interrupt lines are not recognized or accepted by the SBC-ll/21 module. The DMA request is recognized by the module at the lowest interrupt level, but once the DMA master has accessed the bus, there
are no other interrupts until the transfer is complete or the DMA master relinquishes the bus. The
module does not use or support the BREF control line for refreshing dynamic memory.
9.3 MASTERISLA VE RELATIONSHIP
Communication between devices on the bus is asynchronous. A master/slave relationship occurs during
each bus transaction. At any time, there is one device that has control of the bus. This controlling device is the bus master. The master device controls the bus when communicating with another device on
the bus, the slave. The bus master (the processor or a DMA device) starts a bus transaction. The slave
device responds by acknowledging the transaction in progress and by receiving data from, or transmitting data to, the bus master. LSI-II bus control signals transmitted or received by the bus master or
bus slave device must complete the sequence according to bus protocol.
The processor controls bus arbitration, i.e., which device becomes bus master at any given time. A typical example of this relationship is the processor, as master, fetching an instruction from memory, which
is always a slave. Another example is a disk, as master, transferring data to memory as slave. Communication on the LSI-II bus is interlocked so that for certain control signals issued by the master device,
there must be a response from the slave in order to complete the transfer. It is the master/slave signal
protocol that makes the LSI-ll bus asynchronous. The asynchronous operation eliminates the need for
synchronizing with, and waiting for, clock pulses.
A bus cycle completion by the bus master requires a response from the slave device. Each bus master
must include a time-out error circuit that will abort the bus cycle if the slave device does not respond to
the bus transaction within 10 ILS. The actual time before a time-out error occurs must be longer than the
response time of the slowest peripheral or memory device on the bus. The signal assignments are shown
in Table 9-1.

9-2

Table 9-1

Signal Assignments

Number
of Pins

Functional
Category

Signal Names

Data/address

BDALO, BDAL1, BDAL2 ... BDAL15

Data control

BDOUT, BRPLY, BDIN, BSYNC, BWTBT,
BBS7

Interrupt control

BIRQ4, BIAKO, BIAKI

DMA control

BDMR, BDMGO, BDMGI, BSACK

System control

BHALT, BDCOK, BPOK, BEVNT, BINIT

+5 Vdc

+ 12 Vdc

-12 Vdc

+5 B (battery)

GND

SSPARES

MSPARES

PSPARES

9.4 DATA TRANSFER BUS CYCLES
Data transfer bus cycles are listed and defined in Table 9-2.
NOTE
The SBC-H/21 microcomputer performs a read
transaction before every write transaction. It does
not perform DATIO or DATIO(B) bus transactions
as one address. It executes read-modify-write instructions by addressing the source as one transaction and addressing the destination as another transaction.

9-3

These bus cycles, executed by bus master devices, transfer 16-bit words or 8-bit bytes to or from slave
devices. The bus signals that are listed in Table 9-3 are used in the data transfer operations that are
described in Table 9-2. Data transfer bus cycles can be lowered to two basic types: DATI, and
DATO(B). These transactions occur between the bus master and one slave device selected during the
addressing section of the bus cycle.
Table 9-2

Data Transfer Operations

Bus Cycle
Mnemonic

Description

Function (with respect
to the bus master)

DATI

Data word input

Read

DATO

Data word output

Write

DATO(B)

Data byte output

Write byte

Table 9-3 Bus Signals Used in Data Transfer Operations
Mnemonic

Description

Function

BDAL<15:00> L

16 data/address lines

BDAL< 15:00> L
are used for word
and byte transfers

BSYNCL

Bus cycle control

Strobe signal

BDINL

Data input indicator

Strobe signal

BDOUTL

Data output indicator

Strobe signal

BRPLYL

Slave's acknowledge of
bus cycle

Strobe signal

BWTBTL

Write/byte control

Control signal

BBS7

I/O device select;
indicates address
is in the I/O page·

Control signal

9.4.1 Bus Cycle Protocol
Before starting a bus cycle, the previous bus transaction must have been completed (BSYNC L negated) and the device must become bus master. The bus cycle can be divided into two parts, an addressing section and a data transfer section. During the addressing section, the bus master outputs the address for the correct slave device, memory location, or device register. The selected slave device
9-4

responds by latching the address bits and holding this condition for the duration of the bus cycle until
BSYNC L becomes negated. During the data transfer section, the actual data transfer occurs.
Device Addressing - The device addressing section of a data transfer bus cycle has an address setup and
deskew time and an address hold and deskew time. During the address setup and deskew time, the bus
master:
1.

Asserts BDAL< 15:00> L with the correct slave device address bits.

Asserts BBS7 L if a device in the I/O page (56Kb-64Kb for SBC-II/21) is being addressed.
(Devices in the I/O page ignore BDAL<I5:13> and decode BBS7 L with
BDAL<12:00>.)

Asserts BWTBT L if the cycle is a DATO(B) bus cycle. (Inactive BWTBT L indicates a
DATI or DATIO(B) operation.)

Asserts BSYNC at least 150 ns after BDAL<15:00> L, BBS7 L, and BWTBT L are valid.

The BBS7 L address and BWTBT L signal must be asserted at the slave bus receiver for at least 75 ns
before BSYNC goes active. The address hold and deskew time start after BSYNC L is asserted.
The slave device uses the active BSYNC L bus receiver output to clock BDAL address bits, BBS7 L
and BWTBT L, into its internal logic. BDAL<15:00> L, BBS7 L, and BWTBT L will stay active for
25 ns (minimum) after the BSYNC L bus receiver goes active. BSYNC L stays active for the duration
of the bus cycle.
Memory devices usually do not respond to addresses in the I/O page; however, some system applications may permit memory to reside in the I/O page for use as DMA buffers, read only memory bootstraps, or diagnostics, etc.
DATI - The DATI bus cycle, shown in Figure 9-1, is a read operation. During DATI, data is input to
the bus master. Data uses 16-bit word transfers over the bus. During the data transfer section of the
DATI bus cycle, the bus master asserts BDIN L 100 ns (minimum) after BSYNC L is asserted. In
response to BDIN L active, the slave device:
l.

Asserts BRPLY L after receiving BDIN Land 125 ns (maximum) before BDAL bus driver
data bits are valid.

Asserts BDAL< 15:00> L with the addressed data.

When the bus master receives BRPLY L, the bus master:
l.

Waits at least 200 ns deskew time and then accepts input data at BDAL<15:00> L bus
receivers.

Negates BDIN L 150 ns (minimum) to 2 j.lS (maximum) after BRPLY L goes active.
NOTE
Continuous assertion of BSYNC L keeps control of
the bus under the bus master, and the previously addressed slave device remains selected. Also, a slow
slave device can hold off data transfers to itself by
keeping BRPLY L asserted. This will cause the
master to keep BSYNC L asserted.
9-5

BUS MASTER
(PROCESSOR OR DEVICE)

SLAVE
(MEMORY OR DEVICE)

ADDRESS DEVICE MEMORY
• ASSERT BDAL <15-00> L
ADDRESS AND
o ASSERT BBS7 IF THE ADDRESS
IS IN THE 56-64KB RANGE
o ASSERT BSYNC L

REQUEST DATA
• REMOVE THE ADDRESS FROM
BDAL <15-00> LAND
NEGATE BBS7 L
• ASSERT BDIN L

---- ---- ------------

DECODE ADDRESS
STORE DEVICE SELECTED
OPERATION

------------- -------

INPUT DATA
PLACE DATA ON BDAL <15-00> L
___ 0
ASSERT BRPLY L

TERMINATE INPUT TRANSFER
o ACCEPT DATA AND RESPOND
BY NEGATING BDIN L

TERMINATE BUS CYCLE
o NEGATE BSYNC L

~--------

OPERATION COMPLETED

~--------. NEGATEBRPLYL

• REMOVE DATA FROM
BDAL <15-00> L
MR·7195

Figure 9-1

DATI Bus Cycle

The slave device responds to BDIN L negation by negating BRPLY L and removing read data from
BDAL bus drives. BRPLY L must be negated 100 ns (maximum) before removal of read data. The bus
master responds to the negated BRPLY L by negating BSYNC L
Two conditions must be met for the next BSYNC L assertion:
1.

BSYNC L must remain negated for 200 ns (minimum).

BSYNC L must not become asserted within 300 ns of the previous BRPLY L negation.

Figure 9-2 illustrates DATI bus cycle timing.

9-6

TIMING AT MASTER DEVICE
(4)

R DATA

(4)

100 ns MIN
t200 ns MAX
T SYNC

100 ns MIN
8/.15 MAX
T DIN
R RPLY

TmJ
TWTBT ~

tlOO ns MIN
(4)

/..

(4)

TIMING AT SLAVE DEVICE

R/T DAL

T DATA

(4)

'--......;....:;.;..;.;.;..;...-~~100 ns MAX,O ns MIN

R SYNC
R DIN

----+----'

T RPLY

R BS7

(4)

R WTBT ~_ _- - J ~_ _ _ _ _ _ _ _ _..;.(4..;.)_ _ _ _ _ _ _ _ _ __
NOTES:
1.

TIMING SHOWN AT MASTER AND SLAVE DEVICE BUS DRIVER
INPUTS AND BUS RECEIVER OUTPUTS

SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT

BUS DRIVER OUTPUT AND BUS RECEIVER INPUT SIGNAL
NAMES INCLUDE A "B" PREFIX

DO NOT CARE CONDITION

Figure 9-2

DATI Bus Cycle Timing

9-7

DATO(B) - DATO(B), illustrated in Figure 9-3, is a write operation. Data is transferred in 16-bit words
(DATO) or 8-bit bytes (DATO(B)) froin the bus master to the slave device. The data transfer output
can occur after the addressing section of a bus cycle when BWTBT L has been asserted by the bus
master.
The data transfer section of a DATO(B) bus cycle makes a data setup and deskew time and a data hold
and deskew time. During the data setup and deskew time, the bus master outputs the data on
BDAL<15:00> L at least 100 ns after the BSYNC L is asserted. If it is a word transfer, the bus
master negates BWTBT L at least 100 ns after BSYNC L assertion. BWTBT L stays negated for the
length of the bus cycle. If the transfer is a byte transfer, BWTBT L remains asserted. During a byte
transfer, BDAL 00 L selects the high or low byte. This occurs while in the addressing section of the
cycle. If asserted, the high byte (BDAL<15:08> L) is selected; otherwise, the low byte
(BDAL<07:00> L) is selected. The bus master asserts BDOUT L at least 100 ns after BDAL and
BWTBT L bus drives are stable. The slave device responds by asserting BRPLY L within 10 J,LS to avoid
bus time-out. This completes the data setup and deskew time.
During the data hold and deskew time, the bus master receives BRPLY L and negates BDOUT L.
BDOUT L must stay asserted for at least 150 ns after receiving BRPLY L before being negated by the
bus master. BDAL<15:00> L bus drivers stay asserted for at least 100 ns after BDOUT L negation.
The bus master then negates BDAL inputs. During this time, the slave device senses BDOUT L negation. The data is accepted, and the slave device negates BRPLY L. The bus master responds by negating BSYNC L. However, the processor will not negate BSYNC L for at least 175 ns after negating
BDOUT L. This completes the DATO(B) bus cycle. Before the next cycle, BSYNC L must stay unasserted for at least 200 ns. Figure 9-4 shows the DATO(B) bus cycle timing.
9.4.2 Direct Memory Access
DMA is started after the processor (normally bus master) has passed bus mastership to the highest
priority DMA device that is requesting the bus. The processor arbitrates all requests and grants the bus
to the DMA device electrically closest to it. A DMA device remains a bus master until it relinquishes
its mastership. The following control signals are used during bus arbitration.
I.
2.
3.
4.

BDMGI L
BDMGO L
BDMR L
BSACK L

DMA grant input
DMA grant output
DMA request line
Bus grant acknowledge

A DMA transaction can be divided into three phases:
1.
2.
3.

Bus mastership acquisition phase
Data transfer phase
Bus mastership relinquish phase

During the bus mastership acquisition phase, a DMA device requests the bus by asserting BDMR L.
The processor arbitrates the request and starts the transfer of bus mastership by asserting BDMGO L.
The maximum time between BDMR L assertion and BDMGO L assertion is DMA latency. This is
processor dependent. BDMGO L/BDMGI L is one signal that is daisy chained through each module in
the backplane. It is driven out of the processor on the BDMGO L pin, enters each module on the
BDMGI L pin, and exits on the BDMGO L pin. This signal passes through the modules in descending
order of priority until it is stopped by the requesting device. The requesting device blocks the output of
BDMGO L and asserts BSACK L. If BDMR L is continuously asserted, the bus will be hung.

9-8

BUS MASTER
(PROCESSOR OR DEVICE)
ADDRESS DEVICE/MEMORY
° ASSERT BDAL <15-00>L
WITH ADRESS AND
° ASSERT BBS7 L (IF ADDRESS IS
IN THE 56-64KB RANGE
° ASSERT BWTBT L (WRITE
CYCLE)
° ASSERT BSYNC L

SLAVE
(MEMORY OR DEVICE)

-- ---- --

--~ DECODE ADDRESS

--------

---0

STORE DEVICE SELECTED
OPERATION

OUTPUT DATA
° REMOVE THE ADDRESS FROM
BDAL <15-00> L AND NEGATE
BBS7 LAND BWTBT L
° PLACE DATA ON BDAL <15-00> L
° ASSERT BDOUT L

------ ----

TERMINATE OUTPUT TRANSFER - - - ° NEGATE BDOUT L (AND BWTBT L
IF A DATOB BUS CYCLE)
• REMOVE DATA FROM
BDAL <15-00> L

TERMINATE BUS CYCLE

° NEGATE BSYNC L

-------

-...
TAKE DATA
° RECEIVE DATA FROM BDAL
LINES
ASSERT BRPLY L

------ ---...

...----------

OPERATION COMPLETED
° NEGATE BRPLY L

MR·7196

Figure 9-3

DATO or DATOB Bus Cycle

9-9

=:J
T DAL

Ons MIN

X~-----T-D-A-T-A----- ~

T AD DR

, ...... 150ns 1100ns
MIN

~MIN

1'-

lOOns
MIN

r(4)

TSYNC
8ILs

200nsMIN

-./

MAX

1,---------,

TDOUT
300ns MIN
RRPLY

T BS7

(4)

TWTBT

ASSERTION = BYTE

(4)

lOOns MIN

TIMING AT MASTER DEVICE

R DAL

_(_4)_ _

..J),( R ADDR

~_ _ _ _ _R_D_A_T_A_ _ _ _ _J),(

(4)

~25nsMIN

25ns MIN
R SYNC

.!I~.- 150ns MIN

lOOns MIN --<•
RDOUT

T RPLY

R BS7

(4)

R WTBT

ASSERTION = BYTE

j;:

(4)

25ns MIN

TIMING AT SLAVE DEVICE
NOTES:
1. TIMING SHOWN AT MASTER AND SLAVE DEVICE
BUS DRIVER INPUTS AND BUS RECEIVER OUTPUTS.
2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A "B" PREFIX.
4. DON'T CARE CONDITION.

MR-1179

Figure 9-4

DATO or DATOB Bus Cycle Timing

9-10

During the data transfer phase, the DMA device continues asserting BSACK L. The actual data transfer is performed as described previously.
NOTE
If multiple data transfers are performed during this
phase, consideration must be given to the use of the
bus for other system functions.
The DMA device can assert BSYNC L for a data transfer 250 ns (minimum) after it receives BDMGI
L and its BSYNC Land BRPLY L become negated.
During the bus mastership relinquish phase, the DMA device relinquishes the bus by negating BSACK
L. This occurs after completing (or aborting) the last data transfer cycle (BRPLY L negated). BSACK
L may be negated up to a maximum of 300 ns before negating BSYNC L. Figure 9-5 shows the DMA
protocol, and Figure 9-6 shows the DMA request/grant timing.

BUS MASTER
(CONTROLLER)

SBC'-11/21 MICROPROCESSOR
(MEMORY IS SLAVE)

GRANT BUS CONTROL
• NEAR THE END OF THE
CURRENT BUS CYCLE
(BRPLY L IS NEGATED).
ASSERT BDMGO LAND
INHIBIT NEW PROCESSOR
GENERATED BYSNC L FOR
THE DURATION OF THE
DMA OPERATION.

TERMINATE GRANT
-------""
SEQUENCE
_---• NEGATE BDMGO LAND
_
WAIT FOR DMA OPERATION
---_
TO BE COMPLETED.
- - - __

.... --

RESUME PROCESSOR
OPERATION
• ENABLE PROCESSORGENERATED BSYNC L
(PROCESSOR IS BUS
MASTER) OR ISSUE
ANOTHERGRANTIFBDMR
LIS ASSERTED_

, REQUEST BUS
• ASSERT BDMR L

-- ----..... ----- ------- ---- ......
----- -_----

-- --

----

------------

ACKNOWLEDGE BUS
MASTERSHIP
• RECEIVE BDMG
• WAIT FOR NEGATION OF
BSYNC LAND BRPLY L
• ASSERT BSACK L
• NEGATE BDMR L

EXECUTE A DMA DATA
TRANSFER
• ADDRESS MEMORY AND
TRANSFER UP TO 4 WORDS
OF DATA AS DESCRIBED
FOR DATI, OR DATO BUS
CYCLES
• RELEASE THE BUS BY
TERMINATING BSACK L
(NO SOONER THAN
NEGATION OF LAST BRPLY
LlAND BSYNC L.

WAIT 41ls OR UNTI L
ANOTHER FIFO TRANSFER
IS PENDING BEFORE
REQUESTING BUS AGAIN.
MR-71B1

Figure 9-5

DMA Protocol

9-11

SECOND
REQUEST

----

TDMR

RDMG _ _ _ _- J

TSACK

R/TSYNC

R/T RPLY
~OnsMIN.
~OnsMIN.

~~~6BS7 ________________J~DDR

X~-----D-A-TA----~

WTBT,REF)
NOTES:
1 TIMING SHOWN AT REQUESTING DEVICE BUS DRIVER
INPUTS AND BUS RECEIVER OUTPUTS.
2 SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT
3 BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A "B" PREFIX.
MA·7178

Figure 9-6

DMA Request/Grant Timing

9.S INTERRUPTS
The LSI-ll bus signals used in interrupt transactions are:
1.
2.

3.
4.
5.
6.

BIRQ4 L
BIAKI L
BIAKO L
BDAL<15:00> L
BDIN L
BRPLY L

Interrupt request priority level 4
Interrupt acknowledge input
Interrupt acknowledge output
Da ta / address lines
Data input strobe
Reply

9.S.1 Device Priority
The SBC-ll/21 supports only one method of device priority arbitration: position defined arbitration
(priority is determined only by electrical position on the bus). The closer a device is to the processor, the
higher its priority.
9.S.2 Interrupt Protocol
Interrupt protocol on the SBC-ll/21 has three phases:
1.
2.
3.

Interrupt request phase
Interrupt acknowledge and priority arbitration phase
Interrupt vector transfer phase

Figure 9-7 shows the interrupt request/acknowledge sequence.

SBC·11/21
MICROPROCESSOR

STROBE INTERRUPTS
" ASSERT BDIN L

I
I
+

GRANT REQUEST
" PAUSE AND ASSERT BIAKO L

RECEIVE VECTOR & TERMINATE
REQUEST
" INPUT VECTOR ADDRESS
" NEGATE BDIN LAND BIAKO L

PROCESS THE INTERRUPT
" SAVE INTERRUPTED PROGRAM
PC AND PS ON STACK
" LOAD NEW PC AND PS FROM
VECTOR ADDRESSED LOCATION
" EXECUTE INTERRUPT SERVICE
ROUTINE FOR THE DEVICE

DEVICE

~--

INITIATE REQUEST
_ " ASSERT BIR04 L

-- ------...

RECEIVE BDIN L
"STORE INTERRUPT SENDING
IN DEVICE

-- --- ----------

RECEIVE BIAKI L
" RECEIVE BIAKI L AND INHIBIT
BIAKO L
" PLACE VECTOR ON BDAL <15-00> L
" ASSERT BRPLY L
_ " NEGATE BIRO L

------------------

COMPLETE VECTOR TRANSFER
" REMOVE VECTOR FROM BDAL BUS
-" NEGATE BRPL Y L

MR-7197

Figure 9-7

Interrupt Request/Acknowledge Sequence

The interrupt request phase starts when a device meets its specific conditions for interrupt requests
(e.g., the device is ready, done, or an error has occurred). The interrupt enable bit in a device status
register must be set. The device then sets up the interrupt by asserting the interrupt request line.
BIRQ4 L is the only hardware priority level on the SBC-11/21 and is asserted for all interrupt requests.
The interrupt request line stays asserted until the request is acknowledged.
During the interrupt acknowledge and priority arbitration phase, the SBC-ll /21 processor will acknowledge interrupts under the following conditions:
1.

The device interrupt priority is higher than the current PS<7:5>.

The processor has completed instruction execution, and no additional bus cycles are waiting.

9-13

The processor acknowledges the interrupt request by asserting BDIN L, and, 225 ns (minimum) later,
asserting BIAKO L. The device electrically closest to the processor receives the acknowledge on its
BIAKI L bus receiver.
When the device receives the acknowledge, it reacts as follows:
1.

If not requesting an interrupt, the device asserts BIAKO L, and the acknowledge moves to
the next device on the bus.

If the device was requesting an interrupt, the acknowledge is blocked using the leading edge
of BDIN L and arbitration is granted. The interrupt vector transfer phase begins.

The interrupt vector transfer phase is enabled by BDIN Land BIAKI L. The device responds byasserting BRPLY L and its BDAL< 15:00> L bus driver inputs with the vector address bits. The BDAL bus
driver inputs must be stable within 125 ns (maximum) after BRPLY L is asserted. The processor then
inputs the vector address and negates BDIN Land BIAKO L. The device then negates BRPLY Land,
100 ns (maximum) later, removes the vector address bits. The processor then enters the device's service
routine.
NOTE
Propagation delay from BIAKI L to BIAKO L must
not be greater than 500 ns per LSI-ll bus slot.
The device must assert BRPLY L within 10 f.,LS
(maximum) after the processor asserts BIAKI L.
9.6 CONTROL FUNCTIONS
The following LSI-II bus signals provide control functions.
1.
2.
3.
4.
5.

BHALT L
BINIT L
BPOK H
BDCOK H
BEVNT L

Processor halt
Initialize
Power OK
DC power OK
External event

9.6.1 Halt
Refer to Chapter 2 an for explanation of the BHALT L response.
9.6.2 Initialization
Devices on the bus are initialized when BINIT L is asserted. The microprocessor can assert BINIT Las
a result of executing a RESET instruction or as part of a power-up sequence. BINIT L is asserted for
approximately 17 f.,LS when RESET is executed.
9.6.3 Power Status
Power status protocol is controlled by two signals, BPOK Hand BDCOK H. These signals are driven
by some external device (usually the power supply).
BPOK H - When asserted, BPOK H indicates that there is at least an 8 ms reserve of dc power and
that BDCOK H has been asserted for at least 70 ms. Once BPOK H has been asserted, it must stay
asserted for at least 3 ms. The negation of this line, the first event in the power fail sequence, indicates
that power is failing and that only 4 ms of dc power reserve remain.
BOCOK H - When asserted,BDCOK H indicates that dc power has been stable for at least 3 ms. Once
asserted, this line stays asserted until the power fails. Its negation indicates that only 5 f.,LS of dc power
reserve remain.
9-14

9.6.4 Power-UpjPower-Down Protocol
Power-up protocol (Figure 9-8) begins when the power supply applies power with BDCOK H negated.
This forces the processor to assert BINIT L. When the dc voltages are stable, the power supply, or
other external device, asserts BDCOK H. The processor responds by clearing the PSW. BINIT L remains asserted until the assertion of BDCOK H. The processor continues to test for BPOK H until it is
asserted. The power supply asserts BPOK H 70 ms (minimum) after BDCOK H is asserted. The processor then performs its power-up sequence. Normal power must be maintained at least 3 ms before a
power-down sequence can start.
A power-down sequence starts when the power supply negates BPOK H. When the current instruction
is completed, the microprocessor traps to a power-down routine at location 24. The routine must provide
for loading 340 into the PSW, execute a RESET instruction, and terminate in a WAIT instruction or
branch on itself. There should be no DMA requests issued after the RESET is executed. This prevents
any possible memory destruction in the battery supported system as the dc voltages fail.
NOTE
SHe-Hj21 does not generate HINIT L during the
power-down sequence. The power-down routine must
therefore include a RESET instruction to set bus devices into a known state.

- /1_

BINIT L

HARDWARE

SOFTWARE
CONTROLLED

_3msMIN

P!II

50"sMAX

ccEO

2oomsj;:
MAX

B POK H

.....

70ms MIN

14- 4msMIN-

BDCOK H

- ~
DC POWER

3ms
MIN

8ms MIN

5"sMIN

V
-~
POWER-UP

~SEQUENCE

NORMAL
POWER

POWER-DOWN
SEQUENCE

~
"I

70msMIN

POWER-UP
SEQUENCE

I-

NORMAL .....
POWER

NOTE:
ONCE A POWER-DOWN SEQUENCE IS S.TARTED,
IT MUST BE COMPLETED BEFORE A POWER-UP
SEQUENCE IS STARTED.
MR-'1S4

Figure 9-8

Power-Up/Power-Down Timing

9-15

9.7 LSI-ll BUS ELECTRICAL CHARACTERISTICS
Configuring LSI-II bus systems requires an understanding of its transmission line characteristics. For a
discussion of these characteristics, see the PDP-II Bus Handbook.
9.8 MODULE CONTACT FINGER IDENTIFICATION
All Digital plug-in modules, including the SBC-II/2I, use the same contact finger (pin) identification
system. The LSI-ll bus is based on the use of double-height modules that plug into a 2-s10t bus connector. Each. slot contains thirty-six lines (eighteen each on both the component and solder sides of the
circuit board).
Slots, shown as row A and row B in Figure 9-9, include a numeric identifier for the side of the module.
The component side is defined as side 1; the solder side is defined as side 2. Letters A through V (except G, I, 0, and Q) identify a specific pin on a side of a slot. Table 9-4 lists and identifies the bus pins
of the double-height module. For a summary, refer to Table 1-1. The bus pin identifier terminating with
a I is found on the component side of the board; a bus pin identifier terminating with a 2 is found on the
solder side of the board. A typical pin is defined as follows:
AE2: row A, pin E, side 2
The positioning slot between the two rows of pins matches with a guide on the connector block for
correct module positioning.

ROWA

ROWB

PIN BV1

PIN BV2
MR-7177

Figure 9-9

Double-Height Module Contact Finger Identification

9-16

Table 9-4

Bus Pin Identifiers

Bus Pin

Mnemonic

Description

AEl

SSPAREI
(alternate + 5B)

Special spare - not assigned or bused in Digital cable or backplane
assemblies; available for user connection. Optionally, this pin may be
used for + 5 V battery ( + 5B) backup power to keep critical circuits
alive during power failures. A jumper is required on LSI-ll bus options to open (disconnect) the +5B circuit in systems that use this line
as SSPAREI.

AFl

SSPARE2

Special spare - not assigned or bused in Digital cable or backplane
assemblies; available for user interconnection.

AJI

GND

Ground - system signal ground and dc return.

AKl
ALl

MSPAREA
MSPAREA

Maintenance spare - normally connected together on the backplane at
each option location (not a bused connection).

AMI

GND

Ground - system signal ground and dc return.

ANI

BDMRL

Direct memory access (DMA) request - a device asserts this signal to
request bus mastership. The processor arbitrates bus mastership between itself and all DMA devices on the bus. If the processor is not
bus master (it has completed a bus cycle, and BSYNC L is not being
asserted by the processor), it grants bus mastership to the requesting
device by asserting BDMGO L. The device responds by negating
BDMR L and asserting BSACK L.

API

BHALT L

Processor halt - refer to Chapter 2.

ATI

GND

Ground - system signal ground and dc return.

AUl

PSPAREI

Spare - not assigned; customer usage not recommended; prevents
damage when modules are inserted upside down.

AVI

+5B

+ 5 V battery power - secondary + 5 V power connection. Battery
power can be used with certain devices.

BAI

BDCOK H

DC power OK - power supply-generated signal that is asserted when
there is sufficient dc voltage available to sustain reliable system operation.

BBI

BPOKH

Power OK - asserted by the power supply 70 ms after BDCOK. Negated when ac power drops below the value required to sustain power
(approximately 75% of nominal). When negated during processor operation, a power fail trap sequence is initiated.

BHI

SSPARE8

Special spare - not assigned or bused in Digital cable and backplane
assemblies; available for user interconnection.

9-17

Table 9-4 Bus Pin Identifiers (Cont)
Bus Pin

Mnemonic

Description

B11

GND

Ground - system signal ground and dc return.

BKI
BLI

MSPAREB
MSPAREB

Maintenance spare - normally connected together on the backplane at
each option location (not a bused connection).

BMI

GND

Ground - system signal ground and dc return.

BNI

BSACK L

This signal is asserted by a DMA device in response to the processor's
BDMGO L signal, indicating that the DMA device is bus master.

BRI

BEVNTL

External event interrupt request - when asserted, the processor responds (if PS bit 7 is zero) by entering a service routine via vector
address 100. A typical use of this signal is a line time-clock interrupt.

BSI

PSPARE4

Power spare 4 - not assigned a function; not recommended for use.

BTl

GND

Ground - system signal ground and dc return.

BU1

PSPARE2

Power spare 2 - not assigned a function; not recommended for use. If
a module is using - 12 V (on pin AB2) and if the module is accidentally inserted upside down in the backplane, -12 Vdc appears on pin
BUI.

BV1

+5 V power - normal +5 Vdc system power.

AA2

+ 5 V power - normal + 5 Vdc system power.

AB2*

-12

-12 V power - -12 Vdc (optional) power for devices requiring this
voltage.

AC2

GND

Ground - system signal ground and dc return.

AD2

+12

+ 12 V power - 12 Vdc system power.

AE2

BDOUTL

Data output - BDOUT, when asserted, implies that valid data is available on BDAL<0.:15> L and that an output transfer, with respect to
the bus master device, is taking place~ BDOUT L is deskewed with
respect to data on the bus. The slave device responding to the BDOUT
L signal must assert BRPLY L to complete the transfer.

AF2

BRPLY L

Reply - BRPLY L is asserted in response to BDIN L or BDOUT L
and during IAK transactions. It is generated by a slave device to indicate that it has placed its data on the BDAL bus or that it has accepted output data from the bus.

9-18

Table 9-4

Bus Pin Identifiers (Cont)

Bus Pin

Mnemonic

Description

AH2

BDIN L

Data input - BDIN L is used for two types of bus operation:
1. When asserted during BSYNC L time, BDIN L implies an input

transfer with respect to the current bus master and requires a response (BRPLY L). BDIN L is asserted when the master device is
ready to accept data from a slave device.
2. When asserted without BSYNC L, BDIN L indicates that an interrupt operation is occurring.
The master device must deskew input data from BRPLY L.
AJ2

BSYNC L

Synchronize - BSYNC L is asserted by the bus master device to indicate that it has placed an address on BDAL<O:15> L. The transfer
is in process until BSYNC L is negated.

AK2

BWTBT L

Write/byte - BWTBT L is used in two ways to control a bus cycle:
1. It is asserted at the leading edge of BSYNC L to indicate that an

output sequence is to follow (DATO or DATO(B», rather than an
input sequence.
2. It is asserted during BDOUT L, in a DATO(B) bus cycle, for byte
addressing.
AL2

BIRQ4 L

Interrupt request priority level 4 - a level 4 device asserts this signal
when its interrupt enable and interrupt request flips-flops are set. If
the PSW bit 7 is zero, the processor responds by acknowledging the
request by asserting BDIN Land BIAKO L.

AM2
AN2

BIAKI L
BIAKO L

Interrupt acknowledge - in accordance with interrupt protocol, the
processor asserts BIAKO L to acknowledge receipt of an interrupt.
The bus transmits this to BIAKI L of the device electrically closest to
the processor. This device accepts the interrupt acknowledge under
two conditions:
1. The device requested the bus by asserting BIRQ4 L.
2. The device has the highest priority interrupt request on the bus at
that time.
If these conditions are not met, the device asserts BIAKO L to the

next device on the bus. This process continues in a daisy chain fashion
until the device with the highest interrupt priority receives the interrupt acknowledge signal.

9-19

Table 9-4

Bus Pin Identifiers (Cont)

Bus Pin

Mnemonic

Description

AP2

BBS7 L

Bank 7 select - the bus master asserts this signal to reference the I/O
page (including that portion of the I/O page reserved for nonexistent
memory). The address in BDAL<O:12> L when BBS7 L is asserted
is the address within the I/O page.

AR2
AS2

BDMGI L
BDMBO L

AT2

BINIT L

Initialize - this signal is used for system reset. All devices on the bus
are to return to a known, initial state (i.e., registers are reset to zero,
and logic is reset to state zero). Exceptions should be completely documented in programming and engineering specifications for the device.

AU2
AV2

BDALO L
BDAL1L

Data/address lines - these two lines are part of the sixteen-line
datal address bus over which address and data information are communicated. Address information is first placed on the bus by the bus
master device. The same device then either receives input data from,
or outputs data to, the addressed slave device or memory over the
same bus lines.

BA2

+5 V power - normal +5 Vdc system power.

BB2

-12

-12 V power - -12 Vdc (optional) power for devices requiring this
voltage.

Be2

GND

Ground - system signal ground and dc return.

BD2

+12

+ 12 V power - + 12 V system power.

Direct memory access grant - the bus arbitrator asserts this signal to
grant bus mastership to a requesting device according to bus mastership protocol. The signal is passed in a daisy chain from the arbitrator
(as BDMGO L) through the bus to BDMGI L of the next priority device (electrically closest device on the bus). This device accepts the
grant only if it requested to be bus master (by a BDMR L). If not, the
device passes the grant (asserts BDMGO L) to the next device on the
bus. This process continues until the requesting device acknowledges
the grant.

9-20

Table 9-4

Bus Pin Identifiers (Cont)

Bus Pin

Mnemonic

Description

BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2

BDAL2 L
BDAL3L
BDAL4 L
BDAL5L
BDAL6 L
BDAL7 L
BDAL8 L
BDAL9 L
BDAL10 L
BDALll L
BDAL12 L
BDAL13 L
BDAL14 L
BDAL15 L

Data / address lines - these fourteen lines are part of the sixteen-line
data/address bus previously described.

*LSI-II modules that require negative voltages contain an inverter circuit (on each module) that generates the required voltage(s). Hence, -12 V power is not required with Digital-supplied options.

9-21

APPENDIX A
INSTRUCTION TIMING

The fetch and execute times listed in Table A-I assume that the SBC-llj2I is transacting with local
devices that do not require cycle slips when accessed.
Table A-I

Instruction Timing

Single Operand
Instructions

Destination
Mode

Fetch and
Execute
Time (,us)

Number of
Bus
Transactions

Number of
Microcycles

CLR(B), COM(B),
INC(B), DEC(B),
NEG(B), ROR(B),
ROL(B), ASR(B),
ASL(B), SWAP,
ADC(B), SBC(B),
SXT,MFPS,
XOR

0
1
2
3
4
5
6
7

2.44
4.27
4.27
5.49
4.88
6.10
6.10
7.32

1
3
3
4
3
4
4
5

4
7
7
9
8
10
10
12

0
1
2
3
4
5
6
7

2.44
3.66
3.66
5.49
4.27
5.49
5.49
6.71

1
2
2
3
2
3
3
4

4
6
6
8
7
9
9·
11

0
1
2
3
4
5
6
7

4.88
6.10
6.10
7.32
6.71
7.93
7.93
9.16

1
2
2
3
2
3
3
4

8
10
10
12
11
13
13
15

TST(B)

MTPS

A-I

Table A-I

Instruction Timing (Cont)

Source Mode

Source Mode
Time (its)
Includes
Fetch

Number of
Bus
Transactions

Number of
Microcycles

MOY(B), CMP(B),
ADD,SUB,
BIT(B), BIC(B),
BIS(B)

0
1
2
3
4
5
6
7

1.83
3.05
3.05
4.27
3.66
4.88
4.88
6.10

1
2
2
3
2
3
3
4

3
5
5
7
6
8
8
10

Double Operand
Instructions

Destination
Mode

Destination
Mode
Time (its)

Number of
Bus
Transactions

Number of
Microcycles

MOY(B), CMP(B),
ADD,SUB,
BIT(B), BIC(B),
BIS(B)

0
1
2
3
4
5
6
7

0.61
2.44
2.44
3.66
3.05
4.27
4.27
5.49

0
2
2
3
2
3
3
4

1
4
4
6
5
7
7
9

0
1
2
3
4
5
6
7

0.61
1.83
1.83
3.05
2.44
3.66
3.66
4.88

0
1
1
2
1
2
2
3

1
3
3
5
4
6
6
8

Destination
Mode

Fetch and
Execute
Time (its)

Number of
Bus
Transactions

Number of
Microcycles

1
2
3
4
5
6
7

3.05
3.66
3.66
3.66
4.27
4.27
5.49

2
2
3
2
3
3
4

5
6
6
6
7
7
9

Double Operand
Instructions

CMP(B), BIT(B)

Jump and
Subroutine
Instructions

JMP

A-2

Table A-I

Jump and
Subroutine
Instructions

Instruction Timing (Cont)

Destination
Mode

Fetch and
Execute
Time (Jots)

Number of
Bus
Transactions

1
2
3
4
5
6
7

5.49
6.10
6.10
6.10
6.71
6.71
7.90

4
4
5
4
5
5
6

RTS

4.27

SOB

3.66

Branch, Trap,
and Interrupt
Instructions

Destination
Mode

Fetch and
Execute
Time (Jots)

Number of
Bus
Transactions

Number of
Microcycles

BR, BNE, BEQ,
BPL, BMI, BVe,
BVS, Bee, Bes,
BGE, BLT, BGT,
BLE, BHI, BLOS,
BHIS, BLO

2.44

EMT, TRAP,
BPT, lOT

9.77

RTI

4.88

RTT

6.71

Miscellaneous
and Condition
Code
Instructions

Destination
Mode

Fetch and
Execute
Time (Jots)

Number of
Bus
Transactions

Number of
Microcrcles

HALT

8.54

WAIT

2.44

RESET

22.28

JSR

A-3

Number of
Microcycles

10
10
11
11
13

4
then loop
1

Table A-l. Instruction Timing (Cont)

Miscellaneous
and Condition
Code
Instructions

Destination
Mode

Fetch and
Execute
Time (.us)

Number of
Bus
Transactions

Number of
Microcycles

NOP

3.66

CLC, CL V, CLZ,
CLN, CCC, SEC,
SEV, SEZ, SEN,
SCC

3.66

MFPT

3.05

The measure of LSI-II bus interrupt latency is the time from the assertion of BIRQ until BIAKI is
accepted by the interrupting device electrically closest to the processor on the LSI-ll bus.
The measure of local interrupt latency is the time from assertion of the request until the time the microprocessor is ready to fetch the first instruction in the interrupt service routine. This time is primarily
comprised of the time to perform two pushes and a PC and PSW restore.
Interrupt Latency:

LOCAL
LSI-II BUS

23.2.us
9.3 .us

NOTE
Assume that the stack and vector memory reside on
the SBC-H/2l and that the LSI-H bus device can
assert BRPLY and vector within 600 ns after receiving IAKI. The service latency (time from BIRQ until
the time the microprocessor is ready to fetch the
first instruction in the interrupt service routine) depends on the response time of the interrupting device
(i.e., RDIN to TRPLY and negation of TRPLY).
DMA latency is the period of time between a device asserting its BDMR and receiving BDMGI when
it resides on the LSI-ll bus as the electrically closest DMA device to the processor.
DMA latency:

1.3 .us (minimum)

WAIT instruction latencies:
Internal vector:
External vector:
DMA:

11.8 .us

12.4 .us
5.06.us

A-4

11.0 .us (maximum)

APPENDIX B
PROGRAMMING DIFFERENCE LIST

DIFFERENCES BETWEEN THE SBC-llj21, LSI-llj2, AND LSI-llj23
Table B-1 presents a concise comparison of the SBC-l1/21, LSI-ll/2, and LSI-ll/23 modules.
Table B-1

SBC-llj21, LSI-llj2, and LSI-llj23 Comparisons
LSI-llj2

LSI-llj23

Activity

SBC-llj21

OPR %R,(R) + or OPR %R, - (R)
using the same register as both
source and destination: contents
of 'R' are incremented (decremented)
by two before being used as the
source operand.

OPR %R,@(R)+ orOPR %R,@-(R)
using the same register as both
source and destination: contents
of 'R' are incremented (decremented)
by two before being used as the
source operand.

In the previous two cases, initial
contents of 'R' are used as the
source operand.

OPR PC,X(R); OPR PC,@X(R);
OPR PC,@A; or OPR PC,A: location A
will contain the PC of OPR + 4.

In the previous case, location A
will contain the PC of OPR + 2.
JMP (R)+ or JSR reg,(R)+: initial
contents of 'R' are used as the
new Pc.

JMP %R or JSR reg, %R traps to 4
(illegal instruction).

B-1

Table B-1

SBC~llj21, LSI-llj2, and LSI-llj23 Comparisons (Coot)

Activity

SBC-Uj21

LSI-Uj2

Only one LSI-II bus in~errupt
level (BR4) exists.

Four local interrupt levels exist.

Four LSI-II interrupt levels exist.

LSI-Uj23

Stack overflow not implemented.

A stack overflow trap exists.

The first instruction in an
interrupt routine will not be
executed if another interrupt
occurs at a higher priority level
than assumed by the first interrupt.

Eight general-purpose registers.

PSWaddress 177776 not implemented.
Must use MTPS and MFPS instructions.

Only implicit references CRTI, RTT,
traps, and interrupts) can load
T-bit. Console cannot load T-bit.

If an interrupt occurs during an
instruction that has the T-bit set,
the T-bit trap is acknowledged
before the interrupt.

If RTI sets the T-bit, T-bit trap
is acknowledged immediately following
RTI.

T-bit trap will sequence out of
WAIT instruction.

If RTT sets the T-bit, the T-bit
trap occurs after the instruction
following RTT.

RESET instruction consists of 10 p,s
of INIT followed by a 90 p,s pause.
Power fail is not recognized until
the instruction is complete.

B-2

Table B-1

SBC-llj21, LSI-llj2, and LSI-llj23 Comparisons (Cont)

Activity

SBC-llj21

RESET instruction consists of 17
J..Ls of INIT followed by a minimum
3.2 J..Ls pause. Power fail is not
recognized until the instruction
is complete.

Odd address references using the
SP do not trap.

Nonexistent address references
using the SP trap to the restart
address.

LSI-llj2

MOVB instruction does a read
(DATI) and a write (DATa) bus
sequence for last memory cycle.

MaY instruction does a write
(DATa) bus sequence for the last
memory cycle.

MaY instruction does a read
(DATI) and a write (DATa) bus
sequence for last memory cycle.

CLR(B) and SXT do a read (DATI)
and a write (DATa) sequence for
the last bus cycle.

CLR(B) and SXT do a read (DATI)
and a write (DATa) bus sequence
for the last bus cycle.

LSI-llj23

CLR(B) and SXT do a write (DATa)
bus sequence for the last bus cycle.

MARK instruction.

SOB, RTT, SXT, XOR instructions.

SW AB clears Y.

ASH, ASHC, DIY, MUL instructions.

B-3

Table B-1

SBC-llj21, LSI-llj2, and LSI-llj23 Comparisons (Cont)

Activity

SBC-llj21

Register addresses (177700177717) are handled as regular
memory addresses. No internal
registers are addressable from
either the bus or the console.

LSI-llj2

LSI-llj23

If PC contains a nonexistent
memory address and a bus error
occurs, PC will have been
incremented.

If register contains a nonexistent
memory address in mode 2 and a bus
error occurs, register will be
incremented.

If register contains an odd value
in mode 2 and a bus error occurs,
register will be incremented.

HALT in user mode traps to 10.
HALT instruction pushes PC and
PSW. on the stack and loads the PSW
with 340 and the PC with the restart
address.

Only power-up mode 2 implemented.

X
X

Resident ODT microcode.
Instruction execution runs to
completion regardless of bus error.

BEVNT line interrupt on level 6.

Bus error traps to restart
address. Instruction runs to
completion before trap.

B-4

Table B-1

SBC-ll/21, LSI-ll/2, and LSI-ll/23 Comparisons (Cont)

Activity

SBC-ll/21

Bus error during IAK vectors
through 0 and traps to restart
address. The first instruction
of service routine is guaranteed
to execute.

Only 16-bit addressing supported.

LSI-ll/2

LSI-ll/23

x
x

The no-BSACK 18 I-LS time-out
implemented. If time-out occurs
BDMGO aborted.
Bus halt line is a jumper
configured nonmaskable interrupt.
Acknowledgement causes PC and PSW
to be stacked and the processor
vectors through level 7 internal
vector 140.

Vector address accepted only on
BDAL<7:2>. This limits vector
address space to 374.

Certain vector addresses are
reserved for local devices other
than BEVNT.

*Maintenance instructions
**Response depends on processor options

B-5

Table B-2 Illegal Address Traps
From

Through

Response

11/21

LSI 11/2

11/23

210

217

Trap to 10

Reserved
instruction

210

227

Trap to 10

Reserved
instruction

70000

73777

Trap to 10

Extended
instruction
set

75000

75037

Trap to 10

Floating
point

75040

75777

Trap to 10

Reserved
instruction

170000

177777

Trap to 10

Reserved
instruction

SBe-11/21 Priorities
Priority of DMA, system traps, external interrupts, internal interrupts, HALT trap, and WAIT:
(highest priority)

DMA
HALT trap (time-out request)
Power fail trap
Traps (illegal instruction, T-bit, EMT)
Internal interrupt request
External interrupt request
WAIT instruction

(lowest priority)

B-6

APPENDIX C
SOFTWARE DEVELOPMENT

C.l GENERAL
This appendix describes programming notes that may help application programmers to gain familiarity
with the SBC-ll/21. The following three topics are discussed:
1.
2.
3.

Running stand-alone programs
The software development process
An application example

A method of creating, loading, and running stand-alone programs is explained. This is followed by a
discussion of the software development process as it applies to a ROM based single-board computer.
The last section of this appendix presents a practical example of a real-time program written to run on
the SBC-ll/21. The output selected for the program is deliberately simple, however, the methodology
is applicable to more complex programs. The program has been tested, and studying it should be informative to first-time users of the SBC-ll/21.
C.2 RUNNING STAND-ALONE PROGRAMS
The user can develop stand-alone programs, programs not needing an operating system, on a separate
RT-ll based system. The .SAV image can then be loaded into the SBC-l1/21 and run. The MacroODT option is needed to load the program and to run it.
If the stand-alone program is to be used with Macro-ODT, it must have the address of Macro-ODT

BREAK service routine in location 140 and a PSW value of 300 in location 142. This will enable the
program to transfer control to Macro-ODT when the BREAK key is pressed.
To load the stand-alone program from the mass storage device into the SBC-l1/21, the device's boot
block must be modified. This change extends to locations 0, 2, 4, and 6. Location 0, which normally
contains 240, must be changed to 260. When the device is booted, this tells the Macro-ODT that the
mass storage device contains a stand-alone· program. Macro-ODT will then interpret the contents of
locations 2, 4, and 6 as a RADIX-50 encoded six-character file name and search the directory of the
volume for that file. The volume must have the RT-ll file structure. When the file is found, the complete file is loaded into contiguous memory starting at location O. Then Macro-ODT loads register RO
with the number of the unit or drive and register Rl with the CSR address of the booted device.
The stack pointer (SP) is loaded with the contents of location 42, the program counter (PC) is loaded
with the contents of location 40, and the program starts execution. A stand-alone program developed on
an RT-ll based system will have had the correct values for PC and SP in locations 40 and 42. This
information may be of use to the stand-alone program if it uses overlays.
The detailed procedure for performing these modifications in the boot block and the stand-alone program follows, and will be done on an RT-l1 based system using the SIPP utility.

C-l

In the following examples, the program that is to be loaded and run from the stand-alone volume is
named FOOBAR.SAV and resides on DK. The characters entered by the operator are underlined.
'<CR>' is a carriage return and not the four characters '<', 'C', 'R', and '>'. The ''''C' and 'Ay'
symbols are obtained by holding down the 'CTRL' key and typing 'C' or 'V' before releasing 'CTRL'.
'XXXXXX' is a string of octal digits whose value can be anything but does nothing to the process.
First, modify the stand-alone program:
. RSIPP <CR>

;Run the SIPP utility

* DK:FOOBAR.SAV <CR>

;Name of file to be
patched

Base? <CR>

;Defaults to zero

Offset? 140 <CR>
Base

Offset

Old

New?

000000

000140

xxxxxx

170000 <CR>

;Load address of BREAK
routine at BREAK vector

000000

000142

xxxxxx

300 <CR>

;PSW during BREAK routine

000000

000144

xxxxxx

Ay <CR>

;Exit patching

*" C

;Exit SIPP
NOTE
If you are using your own BREAK intercepting routine, put its address at location 140 in place of the
value 170000.

Now modify the boot block:
.RSIPP<CR>
*DK:/A <CR>
Base? <CR>
Offset? <CR>
Base

Offset

Old

New?

000000

xxxxxx

000260

000000

000002

xxxxxx

RFOO<CR>

000000

000004

xxxxxx

RBAR<CR>

000000

000006

xxxxxx

RSAV <CR>

000000

000010

xxxxxx

AY <CR>

*"C
C-2

C.3 THE SOFTWARE DEVELOPMENT PROCESS
Software development for the SBC-ll/21 can be considered as four discrete steps. These steps are illustrated in Figure C-l.
1.

Design the software and code the source tasks.

Enter, edit, and assemble the tasks that make up the application.

Build the application into a runnable memory image.

Load the program into the SBC-ll/21 and execute the application program. This step includes the debugging of the application.
START
UNDERSTAND PROCESS
TO BE INTERFACED
WITH, DO TASK DESIGN

CREATE THE SOURCE
CODE FILE WITH AN
EDITOR

STEP 1.

~------r-----~ ~

BUILD THE
APPLICATION
PROGRAM

L..------r-----'

COMPLETED
MA-7201

Figure C-I

Overview of Software Development
C-3

C.3.1 Design of the Software
An important consideration in the design of application software is the run-time memory configuration.
Because the SBC-ll/21 is a ROM/RAM system, the location of the ROM/RAM boundaries must be
defined. All instructions and constants must be arranged separately for location in the ROM section of
memory. Variable information must be arranged together for location in the RAM section of memory.
During the development process, the separation of ROM and RAM information must be maintained.
See the MACRO-II Language Reference Manual for a description of the methods of data and code
separation.
C.3.2 Editing and Assembly
The second step in the development cycle is the entry, editing, and assembly of the application software. Entering and creating the application software includes the use of an editor on the development
system. Once the application software is entered and the designer is satisfied with the contents, it can
be saved on a mass storage device. The assembler must then be used to convert the source code instructions into executable code. The result of the assembly process is an object file.
The assembler detects common assembly language coding errors and issues appropriate warnings. If
errors are detected, corrections should be made by re-editing the source and reassembling. Once the
application software has been translated error free into object form, it is ready for the next step.
C.3.3 Building Process
The third step in the development cycle is the building process to create a runnable memory image. The
build process uses the linking of the tasks that make up the application software into a single memory
image. The building process takes an object module or modules and assigns absolute memory references to the information contained in the object code. The user assigns these locations by the sectioning
of the code that took place during design. The result of the build phase is an executable run-time memory image that can be loaded and tested.
C.3.4 Running and Debugging the Program
The fourth step in the development cycle is the loading of the runnable memory image into the SBC11/21. Once loaded, the program can be run and debugged. There are three methods that can be used
to transfer the software to the target.
I.

ROM transfer. This method uses the programming of ROMS via a PROM blasting utility,
such as PB-ll, and places the PROMs into the target configuration. This simple loading
method resembles the final target configuration because actual ROM storage is used.

Media transfer. When this method is used, the application program is loaded, in stand-alone
form, into the target from a mass storage system. The directions on creating a stand-alone
bootable program are provided in Paragraph C-2. The target configuration uses LSI-II bus
RAM memory in place of the SBC-ll/21 on-board ROM during initial startup and debug.
The SBC-II/21 configuration must contain the Macro-ODT ROMs described in Chapter 4.
The ODT ROMs provide the means of loading the application program and are used during
program debug. Media transfer does not reflect the final configuration, but execution from
RAM makes debugging and testing easier. The speed of the program in this mode is approximately half that of the ROM based system.

Down-line loading. This method of loading allows transfer of the controller software from the
development system to the target system via a serial communication link. The down-line
loader must be a development system utility. The target configuration is similar to the media
transfer configuration. In addition to the LSI-II bus, RAM, and the Macro-ODT ROMs,
one of the serial I/O lines on the SBC-ll/21 must be dedicated to the communication with
the development system.

When the correct loading method is implemented, the final phase of development is to debug and run.
The loading method used defines the solution that will be taken during debug.
C-4

If the application is being loaded via the ROM transfer method, initial testing and debugging is diffi-

cult. When ROM transfer is used, there must be embedded code in the application that will report the
state of the control system regularly. Another way to check the system is to note changes that occur in
the external devices. If errors are found, a complete reprogramming of the PROMs is necessary. This
type of testing and debugging can be difficult.
When the application is loaded via media transfer, the testing and debugging becomes easier than the
ROM method. Once the application program is loaded into LSI-II bus RAM or into on-board RAM, it
can be run using the features of Macro-ODT. The designer can also include reporting tasks and halts in
the application to examine the current state of the system. Executing out of LSI-II bus RAM during
debug is approximately twice as slow as running out of the SBC-II/2I on-board memory. If errors are
found, minor changes can be made in the application code because testing is being done in RAM. This
deletes the loop of making new run-time memory images for every change. Once the target system is
running successfully with all of the tasks integrated, the run-time configuration can be set up. The last
step is to load the application program to ROM and run in the SBC-1l/2I.
C.4 AN APPLICATION EXAMPLE
A sample application is illustrated in Figure C-2 and shows the development of a controller program
using MACRO-II. The sample program will only light the LED used by port C of the SBC-II/2I. The
LED will light for 10 s when an input is detected on the console port (SLUI).
START

POWER-UP ROUTINE
. . . - - - - IS THIS RECOVERY FROM A POWER FAILURE (POWRUP)

NO
INITIALIZE THE DATA STRUCTURES FOR DIAGNOSTICS (DIAG)

YES

PERFORM DIAGNOSTICS (DIAG)
TEST SBC-ll/21 SIO, PIO, RAM, ROM

!
!

RESTORE STATUS
PRIOR TO THE POWER FAIL
(RECOVR)

ANY ERRORS

•

REPORT TO OPERATOR,
- - -... GO INTO INFINITE LOOP

INITIALIZE THE DATA STRUCTURES (START)
FOR CONTROL/MONITOR TASKS

ENABLE INTERRUPTS (START)

' - - - - - - - - - WAIT FOR INPUTS (START)

TIMER

HANDLE EXCEPTIONS

INTERRUPT TASK NO.1
ENTERED BY AN INPUT RECEIVED
VIA CONSOLE SLU INPUTS

INTERRUPT TASK NO.2
ENTERED EVERY 1/60 OF A SECOND
BY BEVNT INTERRUPT

POWER FAIL (POWERF)
BUS ERRORS (RESTRT)

DO THE FOLLOWING:

1. SET TIMER FOR TEN SECONDS
2_ LIGHT THE LED

1. TICK OFF TIME IF THE TIMER
IS SET TO GREATER THAN a
2.IF TIME EXPIRES TURN OFF
THE LED

RECOR BREAK

MR-7200

Figure C-2

Application Overview

c-s

The controller program for this simple system is best operated by using an interrupt driven environment. An interrupt service routine is used to monitor the console port. When an input is received, a
routine is entered that will set the timer for 10 s and light the LED. A second interrupt service routine
is used to count up to 10 s and then turn off the LED. This routine is serviced by the BEVNT interrupts. In addition to the application tasks, there are tasks to initialize the input/output devices and data
structures. There are also diagnostic programs for the SBC-ll/21 and programs used to handle any
exceptions. The controller program is developed as individual tasks and then integrated into a complete
final program.
The monitor program, shown in Figure C-3, consists of power-up programs, diagnostic programs, task
programs, and exception programs. The power-up programs consist of POWRUP and RECOVR, which
is started by POWRUP. The diagnostic programs consist of SLUTST, PIOTST, RAMTST, and
ROMTST. The task programs consist of TIMER, REC, and BREAK. The exception programs consist
of POWERF, RESTRT, and PRINT. All these programs with the constants and instruction data are
stored in the ROM memory. The variable data for the application and the stack are stored in the RAM
memory. Memory map 1 is assumed (Table 2-8), with the program in ROM socket set B, and data in
battery backed RAM starting at 160000. The load map in Figure C-4 shows actual memory locations
assigned to code and data.
.TITlE FALCON DEVELOPMENT EXAMPLE
.ENAIIl lC
.GlOIll POWERF,IIREAK,REC,TIMER,RECOVR,SlUTST,PIOTST,RAMTST,ROMTST
.GlOBl POWER1,POWER2,ERROR,STACK,RESTRT

2
3
4

; This is an exa.ple of a simple controller application for the KXTI1-AA.
;-

7
8
9

.SBTlL

Prosraa section definitions

; Define the three program sections that will be used
;.ABECT
Assisn absolute ••• ors locations
For ins ructions and constant data
.PSECT ROM
that will be stored in rD • • e.or~

14 000000
15 000000
16
17 000000

.PSECT

RAM,D

.SIITTl

EQuates

To define all RAM locations

18
19

20
21

; Constant definitions

22
23

;176540

RCSRI

== 176540

Auxiliar~

177560

RCSRC
CONBR

== 177560

Console SlU addresses
Prosra •• able baud rate .ask (9600)

24
25
26
27

000052

28
29

176200

30
31

PPA
PCW
lEDON
lEDOFF

176206
000261
000017

== 52
==

SLU addresses

Parallel port A

176200

== 176206

Parallel control word

== 261
17·

Parallel CSW to lisht the lED
Parallel CSW to turn off the lED
Botto. of the user RAH
Top of the user RAH

34
35
36
37

167776

RAMBGN
RAHTOP

160010
167776

106016

CSUM

106016

160010

I Checksu. value for the s~ste. tasks

38
39

40
41
42
43

45
46

.SBTTl

Hacro definitions

; Define .acros that will be used b~ the application
;stack push operation
.HACRO PUSH ARG
MOV
ARG,-(SP)
; MOye the arsu.ent onto the .tack
.ENDH

47
48
49

50
51
52
53

54
55
56
57 000000

.HACRO
HOV
.ENDH

POP ARG
(SPl+,ARG

.SBTTl

Entr~

1+
; Define

entr~

stack POP operation

; .ove the arsu.ant fro. the stack

points

point, interrupt. and trap service routine addresses

.ASECT

Figure C-3

Monitor Program
C-6

5B
59 000000
60 OOOOO~
61
62 00002~
63

000000
000167 000000'
000167 OOOOOOG
000024
OOOOOOG 000340

000060
OOOOOOG 000300

.=60

000100
OOOOOOG 000300

.=100

000140
OOOOOOG 000300

.=1~0

65 000060
66
67
6B 000100
69
70
71 000140

.=0
JHP
JHP

POWRUP
RESTRT

Ju.P to the restart routine

.WORD

POWERF,340

Power fail service routine

.WORD

REC,300

Console receiver service routine

.WORD

TIHER,300

Ti_ar service routine

.WORD

BREAK,300

Console break service routine

.SBTTL
.PSECT

Power UP routine
ROH

Juap to the power-up routine

.=24

73
74
75 000000
76
77 000000
7B
79
BO
Bl
B2 000000
B3 000006
8~ 000010
85 000016
86
87 000020
88
89
90
91
92 000024
93
94
95
96 00002~
97 000030
98 000034
99
100 000042
101 0000~6
102 000050
103 000054
104 000060
105 00006~
106
107 000070
109 00007~
109 000076
110 000102
111 000104
112 000106
113 000112
114
115
116
117
118 000114
119
120
121
122 000114
123 000120
12~ 000126
125 000132
126 000136
127
129 000140
129
130
131 0001~2
132
133

POWRUP::
; Co_e here first under all circu.stances and decide if this is a nor.al
; power UP or recover~ fro& a power fail
i-

026727
001006
026727
001002

OOOOOOG 123456

000167

OOOOOOG

OOOOOOG 135724

POWER1, t123~56
DIAG
DIAG

Is this recover~ fro. power failure
or is it a normal power-u~ ?
Increase the chance to distinauish
by check ins asainst a 32 bit pattern

JHP

RECOVR

This a recovery from

POWER2,t13572~

012706
005067
052737

OOOOOOG
OOOOOOG
000052

fail

004767

000074

17756~

00017~'

004767
004767
004767
004767
005767

OOOOOOG
0000006
OOOOOOG
OOOOOOG
OOOOOOG

001~0~
00~767

000040

000332'
000777
00~767

000030

000253'

s~ste.

diasnostics

HOV
CLR
BIS

tSTACK,SP
ERROR
tCONBR,9tRCSRC+~

Initialize the stack
Initialize the error flas
Initialize the console SLU

CALL
.WORD
CALL
CALL
CALL
CALL

PRINT
DIAGH
RAHTST
ROHTST
SLUTST
PIOTST

Tell the o~erator that the powerdiagnostics are runnin~
the KXTll RAH memor~ test
Perform the KXTll ROH memor~ test
Perform the KXTll serial line test
Perfor~ the KXTll parallel
I/O test

TST
BEQ
CALL
.WORD
DR
CALL
.WORD

ERROR

Is the error flas zero
Yes, no errors proceed to init
No. diasnostic failure

.SBTTL

Initializatiorl camp-Ietion. allow applicat'ion tasks to run

PRINT
EHESS
PRINT
HHESS

Perfor~

Wait until there is operator action
Indicate that thinss are OK
and move on

START::
it

; This is the start of the main body of the application
i-

105737
052737
001015'

TSTB
BIS
HIPS
CALL
.WORD

000777

106~27
00~767

177562
000100
000000
000004

177560

9tRCSRC+2
tlOO,@tRCSRC

to
PRINT
GO

Flush the receiver buffer
Enable interru~t on the receiver
Allow interrupts to happen
Tell the operator that the
application is UP and runnins
Sit and wait for interrupts

PRINT::
it

; This subroutine prints the actual messaSes
i-

017604
005216
005216
112405
001406
105737
100375
110537
000770
000207

000000

1$:
17756~

177566
3$:

.ENADL
HOV
INC
INC
HOVEl
BEQ
TS18
BPL
HOVB
BR
RETURN
.DSABL

LSB
9(SP),R~

(SP)
(SP)
(R4)t.R5
3$

URCSRCt4
2.R5,IItRCSRC+6
1$

P~int to the besinnins of the messase
Increment beyond .essese address in the
callins routine
Hove the next character to be printed
Is this the end of messase marker ?
No, output another character
Transmitter ready
Output the character
Get another character
60 back

LSEI

1~7

148
149
150

~ower

.SBTTL DiaSnostics
DIAG::
i+
; Do the

13~

135
136 0001~2
137 000146
139 000150
139 000152
140 00015~
141 000156
142 000162
143 000164
144 000170
145 000172
146

CHP
BNE
CHP
BNE

.SBTTL
.NLIST

Figure C-3

Hessa_es sent to the operator
BEX

Monitor Program (Cont)
C-7

151
152 000174
153 000253
154 000332
155 000412
156 000445
157 000517
15B 000571
159 000613
160 000650
161 000701
162 000736
163 001015
164 001061
165
166
167

015
01S
015

ois
015
015
015
015
015
015
015
015
040

012
012
012
012
012
012
012
012
012
012
012
012
040

040
040
040
007
040
040
040
040
040
040
040
040
040

DIAGH:
HItESS:
EItESS:
FItESSI
SLUE: :
SLGOOD:
ItESRA11
RAGOOD:
ItESR01:
ROGOOD:
PGOOD: :
GO: :

<15>(12)1 The power-up diagnostics are running •• t 1(15)<12>
<15>(12)1 SYstem checked out, there were no faults 1<15><12>
<15><12>1 Syste. did not pass initial power UP test 1<15>(12)
<15><12><7><7><7><7>1 RUN-TIME FAILURE 1<15><12>
<15>(12)1 Serial line unit dia~nostic failure 1<15><12>
<15>(12)1 Serial line unit passed diasnostics 1(15)<12)
<15>(12)1 RAIt failure 1(15)<12>
<15><12» RAM passed diasnostics 1(15)<12>
<15><12)1 ROM checksua error 1<15><12>
<15>(12)1 ROM passed diasnostics 1(15)<12>
(15)<12)1 Parallel inputloutput passed diaSnostics 1<15><12)
<15>(12)1 The application is runnins ••• 1 <15><12>
1
Type any key to liSht the KXTI1-AA LED for io secs.1

.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
,/\SCIZ
.ASCII
.ASCIZ
.EVEN

000001

.END

Figure C-3
RT-ll LINK
C
.SAV

Section
• ADS.

ROM

RAM

V06.01C
Title:

Addr

Size

000000 000400

000400 157400

160000 000332

Transfer address

Monitor Program (Cont)

Load Map
FALCON Ident:

Mon OB-Feb-B2 04:21123
18:000400

Global

Value

IRW,I,G8L,ADS,OVRI
LEDOFF 000017 CONBR
CSUM
106016 RAMBGN
PPA
176200 PCW
RCSRC
177560
IRW,I,LCL,REL,CONI
POWRUP 000400 DIAG
PRINT
000542 DIAGH
EMESS
000732 FMESS
SLGO~O
001117 HESRAI
HESR01 001250 RDGDOD
001415 RECOVR
GO
TIMER
001656 BREAK
POWERF 001720 RESTRT
RAItTST 002132 ROHTST
IRW,D,LCL,REL,CONI
POWER 1 160010 POWER2
ERROR
160016 TIME

000001,

Hi~h

limit

Value

Global

Value

000052
160010
176206

LEDON
RAM TOP
RCSRl

000261
167776
176540

000424
000574
001012
001171
001301
001556
001702
001764
002212

START
HMESS
SLUE
RAGOOO
PGDOD
REC
LAST
SLUTST
PIOTST

000514
000653
001045
001213
001336
001634
001716
001774
002262

160012
160020

SAVER6
STACK

160014
160332

= 160330 = 2B7BO. words

Figure C-4 Load Map
C.4.1 Power-Up Programs
The controller program starts when the system power is applied. The microprocessor accesses location
0, which is the jumper configured start address. This location contains a jump to the power-up routine
POWRUP (see Figure C-5). This routine determines if this is a normal power-up or a recovery from a
power failure. This is determined by checking the power fail flag in the RAM memory. If the flag is set
to indicate that the system is recovering from a power fail condition, the program jumps to the RECOVR program (see Figure C-6). This program restores the system to the conditions that existed before the power fail and continues program execution. If the flag is not set, an initial power-up program
is executed and the program then branches to the diagnostic programs.
C.4.2 Diagnostic Programs
The diagnostic programs are entered via a diagnostic initialization routine. The SLUTST program (see
Figure C-7) is the first diagnostic, and it tests the auxiliary serial line unit on the SBC-ll/21. The
diagnostic enables the SLU maintenance mode and transmits many test patterns. After a certain
amount of time, the program checks to see that the test patterns were correctly received. The SLU
maintenance mode allows data to be transmitted to the EIA port as well as through the internal loopback. Therefore, if a device is connected to the port, it will respond to this data.

C-8

1
2 000000

.ENABl
• PSECT

lC
RAIl. D

4
5
6
7 000000
B 000010
9 000012
10 000014
11 000016
12
13 000020
14 000022
15 000332
16
17

The variable data is assi!!ned to the user RAtI space on the KXT11-AA
.BlKW
POWER1::.WORD
POWER2::.WORD
SAVER6::.WORD
ERROR:: .WORD

000000
000000
000000
000000
000000

TItlE::

.WORD
.8lKW

Non exi5tan~ KXTll-AA ••• ory
Power failure 32-bit co.parisien
fla.
Stack pointer area for power failure
Dia.nostic error f1a.

0
0
0
0
0
100.

000001

Ti .. " fla!!
This is the stack

.END

Figure C-5

.ENABl
.0lOBl
.HCALL
.PSECT

1
2

3
4 000000
5
6 000000
7
8

Power-up Task

lC
SAVER6.TltlE.RCSRC.CONBR.LEDON.PCW
POP
ROtl

RECOVR::
It

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

STACK: :

000000
000004
000010
000012
000014
000016
000020
000022
000024
000032
000040
000044
000046

016706

000054

000002

052737
052737
005767
001403
012737

000001

;This routine is entered if a recoverw fro. a power failure is takins place
;Restore the stack pointer
HOV
SAVER6.SP
POP
TItlE
Restore the an~ variable inforaation
Restore the seneral purpose
POP
RS
POP
R4
.. e!listers
POP
R3
POP
R2
POP
Rl
POP
RO
000100 0000000
BIS
tlOO.l!tRCSRC
Re-initialize console SLU, enable
OOOOOOG 000004G
tCONBR.@tRCSRC+4
interrupts and set-up baud rate
BIS
OOOOOOG
TIHE
Is the LED ti.er set
TST
BEQ
No, continue
3.
OOOOOOG OOOOOOG
HOV
tLEDON.@tPCW
Yes turn the LED on for the rest
of the time prior to power-fail
3$:
Return fro. point of pOWer-fail
RTI
interrupt

0000000

.END

Figure C-6

Power Fail Recovery

The second diagnostic, RAMTST (see Figure C-8), tests the RAM memory. The test is performed by
writing known data into a RAM location and checking that the correct information is in that location.
The third diagnostic, ROMTST (see Figure C-9), checks the ROM memory. This test calculates a
checksum on the actual control and monitoring tasks. If there is a checksum error, there is a potential
failure at some ROM location.
The last diagnostic, PIOTST (s~e Figure C-IO), checks the parallel I/O port on the SBC-ll/21. '{his
test verifies that the parallel I/O registers can be addressed. The send/receive capability cannot be
checked unless there is a loopback connector installed on the 13 connector. When data is written into
these registers and a device is connected to the port, the device can respond to the data.
When any of the above diagnostics detect a failure, the program will set an error flag. The diagnostic
program will check the status of all error flags before it enters the task programs. If an error is found,
the operator is informed that a diagnostic test failed, and the program enters a loop to wait for the
operator to interrupt. Each diagnostic will print a message to the operator indicating success or failure.
If there are no failures, a success message is printed and the program enters the task programs.

C-9

.ENABL
.6LOBL
.PSECT

1
2
3 000000
4
:; 000000
6
7
8

LC,LSB
RCSR1,ERROR,PRINT,SLUE,SLOOOD
ROH

SLUTST: :
This routine checks the auxiliary SLU port on the KXT11-AA
1-

10 000000
11 000004
12 000010
13
14 000016
15 000022
16 000026
17 000030
18 000034
19 000036
20 000040
21 000042
22 000046
23 000050
24 000052
25 000054
26 000056
27 000060
28 000064
29 000066
30 000070
31 000072
32 000074
33 000076
34 000104
35
36 000106
37 000112
38 000116
39 000120
40 000122
41 000126
42 000130
43
44 000132
45

012701
105761
012761

OOOOOOG

012702
012703
005005
105761
100402
077504
000422
111361
005005
105711
100402
077503
000413
126113
001010
105723
001356
005302
001412
062761
000746

000010
000132'

000002
000006

000004

1$:
2$1
3$1

000006

4$:

000010

177

040

000004

100S:

200.:
150.:
000

te. ,R2

INC
CALL
.WORD
BR
CALL
.WORD
RETURN

PAT ERN : • BYTE
.EIIEN

HDII
MOil
CLR
TSTB
BMI
SOB
BR
CLR
TST9
BMI
SOB
BR
CMPB
BNE
TSTB
BHE
DEC
BEQ
ADD
BR

6$:

005267 OOOOOOG
004767 OOOOOOG
0000006
000403
004767 0000006
0000006
000207

tRCSR1,R1
2(Rll
t6.4(Rll

MOlle

5$:

000002

HOII
TS18
HOII

.DSABL
.END

000001

Figure C-7
.ENABL
.OLOBL
.PSECT

1
2

3 000000

Point to the address
Flush the contents of RBUF
Set the SLU for a.intenanee and
pro.rae.able baud rates
Initialize the baud rate counter

tPATERN,R3

Point to the test patterns

Initialize tie. out counter
Loop the pattern around
Branch if read~ to send
If not read~, bu.p ti.e out counter

4(Rll

R5,3.
100.
(R3) ,6(Rll
R5

(Rll

R5,S.
100$
2(R1) r<R3)

100'
(R3lf
2.

IF tiaed out then - ERROR Send the infor •• tion out
Initialize the ti.e out counter
Is the receiver readv 1
Ves it is and branch
If not read~, bump tia. out counter

If tiaed out then -ERRORWas the infor.ation sent OK ?

No it was not -ERRORAll of the test paterns done 1
No,

do another pattern

All of the baud rates tested 1

200S
tl0,4(Rll

Yes, get out of this routine
No, set-up the next baud rate
Do another loop, reinit patterns

ERROR
PRINT
SLUE
150.

PRINT
SL600D
177,40,0

Bu.p the error counter
Print the error .essaSe

00 back
The test was successful

Test patterns for SLU

LSB

SLU Diagnostic Task
LC,LSB
RAHBON,PRINT,RAHTOP,HESRA1,RAOOOD,ERROR
ROM

5 000000

RAMTST: I

This routine checks the user RAM on the KXT11-AA

10 000000
11 000002
12 000006
13
14 000012
15 000014
16 000016
17 000020
18 000024
19 000026
20 000030
21 000032
22 000034
23 000040
24 000042
25 000046
26
27 000050
28 000052
29 000056
30

011602
016703
012700

010010
020010
001405
004767 0000000
0000006
005203
000407
005720
020027 0000020
103764
004767 0000000
0000006
010216
010367
000207

31
.32

0000000
0000000

000001

1$:

2'$:

3.:
0000000

HOV
MOil
MOil

(SPhR2
ERROR,R3
tRAMBGN,RO

Save the return address
Save the ~ontents of the ERROR f\a.
Point to the start of the user RAH

HOII
CHP
BEQ
CALL
.WORD
INC
BR
TST
CHP
BLO
CALL
.WORD

RO,(RO)
RO, (RO)
2'
PRINT
MEBRAl

Write the address
Read it back
Was the value read correctly

set the error fla!!,
and !!o back
Go onto the next location

PRINT
RAGOOD

Indicate RAH test success

HOII
HDII
RETURN

R2, (SP)
R3,ERROR

Restore the return address
Restore the ERROR fla!!
Test co.pleted.

.DSA8L
.END

LSB

Figure C-8

(ROlf
RO,tRAHTOP+2

No, report the failure,

Until there is no _ore to test

RAM Diagnostic Task

C-I0

.ENA8L LC,LS8
.GLOBL REC,LAST,CSUH,PRINT,HESR01,ROGOOD,ERROR
.PSECT ROH

1
2
3 000000
4
5 000000
6
7
8

ROHTST: :
H

This routine will check the ROH on the KXT11-AA, this test checks
the portion of the ROM that contains the actual controI/.anitor tasks
;-

10
11 000000

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

000004
000006
000010
000014
000016
000022
000024
000030
000032
000036
000040
000044
000046

012700
005001
062001
022700
001374
022701
001406
004767
OOOOOOG
005267
000403
004767
OOOOOOG
000207

OOOOOOG

1$:
000002G
OOOOOOG
OOOOOOG
OOOOOOG
OOOOOOG

2$:
3$:

MOV
CLR
ADD
CliP
8NE
CHI"
BEQ
CALL
.WORD
INC
BR
CALL
.WORD
RETURN
.DSABL
.END

000001

Figure C-9

.ENABL
.GL08L
.PSECT

2
3 000000

tREC,RO
Rl
CROl+,Rl
tLAST+2,RO
1$

tCSUH,Rl
2$
PRINT
MESROl
ERROR
3$
PRINT
ROGOOD

Point to the control task address

Initialize checksu. value
Update value

Until there are no values to SUII
If there are still so_e
.et the ..
Are the checksu.s eGual 1
; Yes, leave the test
No, report the
failure

Set the error fla.
Leave the test

Report the test passed

LSB

ROM Diagnostic Task

LC,LS8
PPA,PRINT,P600D
ROM

PIOTST::

5 000000
6

This routine checks the parallel ports on the KXT11-AA this only
test the ability to address the port

7
8

9
10
11 000000
12 000004
13 000006
14
15
16
17 000012
18
19
20 000014
21 000016
22 000022
23
24 000024
25
26
27

;MOV
CLR
TST

t3,Rl
RO
PPACRO)

005720

TST

(ROl+

077104 '
004767 0000006
0000006

SOB
CALL
.WORD

Rl,l$
PRINT
P600D

000207

RETURN

000001

.DSABL
.END

012701
005000
005760

000003
0000006

1$:

Initialize loop cDunter
Initialize countin~ index
Atte.pt to address PIO port i f the
atte",pt fails a trap throu!ih the
restart will occur and report a run
tiae error
Increment the index, this will not
ti .. e out since there is _eIDor,=, at
locations 2-4
Do the port
Indicate success

LSB

Figure C-1O Parallel I/O Diagnostic Task
C.4.3 Control Task Programs
The control task programs (see Figure C-ll) complete the initialization of the system by clearing the
receive buffer, enabling the interrupts, and lowering the microprocessor priority to accept interrupts.
The operator is then informed that the system is running and waiting for interrupts. The TIMER receives a BEVNT input sixty times per second. The REC program is entered when an interrupt is received from the console. The program will then turn on the LED and load theW s counter. The
BREAK program is entered when a BREAK is detected and performs the same task as REC. A
TIMER program will decrement the 10 s counter, if it is enabled, every time BEVNT is received.
When the 10 s counter is decremented to zero, the program will turn off the LED. If the LED is turned
on and another BREAK or interrupt occurs, the 10 s counter is reset for 10 s.'The program also allows
any exception conditions.

C-ll

2
3
4
5 000000
6
7 000000
8
9
10
11
12
13 000000
14 000006
15 000014
16 000020
17
18 000022
19
20
21
22
23
24
25 000022
26 000026
27 000030
28 000034
29 000036
30 000044
31
32 000046
33
34
35
36
37
38 000046
39 000054
40 000062
41
42

.SBTTL

CONTROL AND MONITORING TASKS

.ENABL
.GLOBL
.PSECT

LC
TIHE,LEDON,PCW,RCSRC,LEDOFF
ROH

REC: :
;t

; This interrupt routine accepts an input from the coosole. When the input is
; received a ten second counter is initialized and the LED is turned on.
1012767
012737
105737
000002

001130 OOOOOOG
OOOOOOG OOOOOOG
0000020

HOV
HOV
TSn
RTI

1<10.* 60.),TIHE
ILEDON,@IPCW
@tRCSRC+2

Set timer for ten seconds
Turn the LED on
Flush the receive bufter
Go back

TIHER::
;t

; This interrupt routine when entered every clock tick will decre.ant the ten
; second counter and turn off the LED if the time is expired, otherwise it
; returns i~mediatel~.
1005767
001406
005367
001003
012737
000002

OOOOOOG

TST
BEQ
DEC
BNE
OOOOOOG OOOOOOG
HOV
GOBACK: RTI
OOOOOOG

TIHE
GOBACK
TIHE
GOBACK
ILEDOFf,IUPCW

If the tiae is set update the
counter otherwise gO back

Yes.

bu~p

the counter and if it is

The last tick then shut the LED off
Otherwise gO back

BREAK: :
; This interrupt service routine will be entered if a break detected, this
; is treated as a resular in~ut on the KXT11-AA console ~ortt
1-

012767
012737
000002
000001

001130 OOOOOOG
OOOOOOG OOOOOOG
LAST: :

HOV
HOV
RTI

1<10.
60.),TIHE
tLEDON,lIlPCW

Set the tiaer for ten seconds
Turn the LED on
Go back

.END

Figure C-ll

Control Task

C.4.4 Exception Programs
The system is now running and the exception programs are entered only when a power fail occurs or a
bus time-out occurs. The print program is entered only to communicate with the operator.

A time-out will occur when an address does not respond or if a device does not respond to an interrupt
acknowledge. When a time-out occurs, the SBC-llj21 will trap to location 4, the restart address. The
start address is defined as location 0, and restart address is defined as location 4 by the factory configuration. The RSTRT program is entered via location 4; it informs the operator that a run-time error
has occurred and waits for the operator to interrupt.
A power failure is detected when the system power is going down. This enables the power fail interrupt
and causes a trap to location 24. The POWERF program (see Figure C-12) is entered via location 24,
and the power fail flags are set in the RAM memory. The RAM memory includes the battery backup
feature of the SBC-llj21 module. Program information contained in the general-purpose registers, the
stack pointer, and other necessary data are stored in the nonvolatile RAM memory. The program then
puts the bus into a known state with the RESET instruction and waits for the power loss to occur. When
power is restored, the POWRUP routine is executed and data is recovered as the system restarts.

C-12

.ENABL
.GLOBL
.HCALL
.PSECT

3
4 000000
5
6 000000
7
8
9
10
11 000000
12 000006
13 000014
14 000016
15 000020
16 000022
li' 000024
18 000026
19 000030
20 000034
21
22 000040
23 000042
24
25 000044
26
27
28
29
30
31 000044
32 000050
33 000052
34
35
36

LC
POWER1,POWER2,TIHE,SAVER6,PRINT,FHESS
PUSH
ROH

POWERFll
If

012767
012767

010667

123456
135724

; This routine is entered when a power fail is detected and saves the
; pertinent information in non-volatile RAM
;0000006
MOV
1123456, POWER 1
Initialize the 32-bit power recover~
1135724, POWER2
test pattern
0000006
MOV
Save the ~eneral purpose reSisters
RO
PUSH
and an~ pertinent data in d nonRl
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
MOV

OOOOOOG

000005
000777

volatile RAH ar ••

R3
R4
R5
TIHE
SP,SAVER6

RESET

Save the stack ~ointer in the nonvolatile ra. area
Put the bus in a known state
and wait for loss of power

RESTRT 1:

; When a bus error occurs such as an interrupt ti.e-out or bus ti.e-out
; a trap thru the restart takes place and co.es here
;004767 OOOOOOG
OOOOOOG
000777

CALL
.WORD

000001

.END

Indicate that a run-ti.e error has
occurred and wait for operator
intervention

PRINT
FMESS

Figure C-12

Power Fail Task

C-13

APPENDIX D
MACRO-ODT ROM

Appendix D provides the user with the program listing of the Macro-DDT ROM firmware.

D-l

KXTll-A2 1K FIRM~ARE
TABLE OF CONTENTS
3456-

1
1
1
1

1
1

911-

1314-

1
1
3

141415-

19-

1
1
19

202021222324242526262727283032-

1
1
1

1
22
1
1

29
1

20
1

1
1

33-

3536373940-

1
1
1

41-

4243-

1
1

44-

454647-

1
1

48-

1
1

1
9

48- 56
48- 114
491
49- 42
49- 51
49- 58
4'1-

5051-

1
1
23
1

51-

5252-

525353-

37
1
24

MACRO V04.00

~-UCT-81

22:56:27

COPYRIGHT NOTICE
KXTll-A2 EDIT HISTORY
Equates
General DLART Equates
General PPI Equates
Program-specific Equates
MACRO DEFINITIONS
RAM Defin1tion
TRAPS-Trap-handling routines
T~APS-LTC Trap-killer
TRAPS-BREAK handler
RESTART-Introduction
RESTART-En~ry point
RESTART-See if stack exists
REstART-Exit if in IN-ROM state
RESTART-Cause determination
RESTART-Ed ts
POwERUP-Introductio?
POWE~UP-Turn on LEO,
POwERUP-Test console OLAkT
POwERUP-Te5t and set up liD-page RAM
POWERUP-Turn off LED
POWERUP-Test for "lOW core"
POWERUP-Edt
rO.ERU~-Subroutlne to initialize vectors
AUTOBAUD-Synchronize with Console
macroODT-Introductlon
macroODT-Save status and print prompt
macroODT-Get ODT command
macroODT- Go and Proceed
macroODT-Register and PS command
macroOOT-Examine and Deposit
macroODT-Get and echO character
macroODT-rype ASCII string
macroODT-Get octal digits
maCrOODJ-UCTSTR--type binary in RO as ASCII
macroODT-Output messages
DIAGNOSTICS-for SLU2 and PPI
HARDwARE ENTRY POlhT
DIAGNOSTICS-Continued
BOOTS-Description
BOOTS-RX Controller Definitions
SOOTS-rU58 Definitions and Protocol Equates
BOOTS-RIll Definitions and Equates
BOOTS-Program entry point
HALT AT PC=172234 INDICATES "Illegal device name"
HALT AT PC=172264 INDICATES "Illegal unit number"
HALT AT PC=172304 INDICATES "No low memory, can"t boot"
HALT AT PC=172316 INDICATES "unexpected timeout during boot"
BOOTS-RX01/RX02 Bootstrap
BOOTS-Distinguishing type of boot block
HALT AT PC=172454 lNDICATES "No boot DloCk on volume"
BOOTS-TU58 Bootstrap
HALT AT PC=172542 INDICATES "TUS8 initialization error"
HALT AT PC=172562 INDICATES "TUSS blOCk 0 read error"
BOOTS-Stand-alone volume bootstrap
HALT AT PC=172614 INDICATES "Directory read error"

----->
----->
----->
----->
----->
----->
----->

-.--->

KXTll-A2 lK FIR~WARE
TAB~E OF CONTENT~
53-

54545455-

1
iI

561
571
57- 36
57- 114
601
61- 27
61- 37
631

MACRO V04.00

5-0CT-ijl 22:56:27

-----> HALT AT PC=172652 INDICATES "flle not tound"
BOOTs-Load Stand-Alone ~roQram flle
-----> HALT AT PC;172732 INDICATES 'Stand-alone flle read error"
-----> HALT AT PC=172750 INDICATES "Illegal transfer address"
173000G ENTRY POINT
BOOTS-Contlnued
BOOTS-RXOI/RX02 Read routlnes
-----> HALT AT PC=173070 IhDICAIES
-----> hALT AT PC=1732b2 INDICATES
BOOTS-TU58 Read routlnes
-----> HALT Ai PC=17355b INDICATES
-----> HALT AT PC=17~610 INDICAT~S
END STATEMENT

"Floppy drlve not ready"
"Floppy read error"
"TU58 ~ND packet misslng"
"TUS8 Checksum error"

KXT11-A2 1K FIRMWARE
1
2
3
4
5
6 000000
7
8 173776
9

173777

MACRO V04.00

5-0CT-~1

22:56:27 PAGE 2
.TITLE KXT11-A2 lK FIRMWARE
.IDENT IV1.001
.ENABL LC

173776
000

001

; Place identification number in last ROM location:
• ASI:.CT
.=173776
.!lYTE
0
.BYTt.
1.

KXT11-A2 1K FIRMWAR~
NOTICE

MACRO V04.00

5-0CT-81 22:56:27 PAGE 3

COPY~I~HT

2
3
4
5
6

7
8
9

10
11
12
13
14
15
16
17
18
19

20
21
22

U
I

.SBTTL COPYRIGHT NOTICE
COPYRIGHT (Cl 1980, 1981 BY
DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.
tHIS SOFTWARE IS FURNISHIO UNDIR A LICENSE AND MAY BE USED AND COPIED
ONLW IN ACCORDANC~ wITH Tk~ TERMS OF SUCH LICENSE AND WITk THE
INCLUSION OF TkE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE, OR ANY OTH~R
COPIES tHEREOF MAt hOT ~E PROVIDED OR OTHERwlS~ MAD~ AVAILABLE TO AkY
OTHEH PERSON. NO TIlLE TO AND OriNERSHIP Of THI SOFTWARE IS HEREBY
TRANSfERRED.
THE INFORMATION IN IHIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
AND SHOULD NOT BE CONSfRUED AS A COMMITMEN~ BY DIGITAL EQUIPMENT
CORPORATION.
DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY or ITS
SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.
VERSION Vl.OO
EL 29-SEP-81

KXTll-A2 lK fIRMwARE
KXT11-A2 ~DIT HISTORY

MACRO V04.00

5-0CT-81 22:56:27 PAGE 4
.SBTTL

2
3
4

o
I

;EDIf HISTORY:

KXTll-A2 EDIT HISTORY

KXTll-A2 lK FIRMWARE
EQUATES
1
2
3
4
5
6
7
a
9
10

0I
-J

12
13
14
1:>
16
17
18
19
20
21
22
23
24
25
26
27

MACRO V04.00

5-0CT-ill 22:56:27 PAGE S
.SBTTL Equates

; BlT EQUATES
000001
000002
000004
000010
000020
000040
000100
000200
000400
001000
002000
004000
0100\10
020000
040000

luOOOO

BlTO
BIT1
BIT2
BIT3
aa4
BITS
BlT6
BlT7
tilT a
BIT!i
BIT10
Bl111
Bl'I'12
BIT13
BIT14
!lIT15
;

000012
000015
000040

=
=

'"'

=
=

=
=
=
=
=
=
=
=
=
=
=

2
4
10
20
40
100
200
400
1000
2000
400\1
10000
20000
40000
1011000

ASCII CHARACTEP EQUATES

Lf
CR
SPACE

=
=

12
1:>
40

L1ne feed
Cdrr1age return
Space

KXTll-A2 lK FIRMWARE
OLART EQUATES

MACRO V04.00

5-0CT-81 22156:27 PAGE 6

GENERA~

1
2
3
4
5
6
7
8

9
10
11

.SBTTL General OLART Equates
; OLAR'l EQUATES
177560
177562
117504
177566
176540
176542
176544
176546

RCSR$1
RtlUf$l
XCSR$1
XBUF$1
RCSR$2
RliUf'S2
XCSRS;'!
XBUF&2

14
15
16
17

t:!
I
00

1"1654&

004000

HC.ACT

BITll

OOf/200

RC.DUN

BIT7

000100

RC.IEN

IHT6

;SLU1 Receive CSR
;SLUl Receive buffer
;SLU1 Xmlt CSR
;SLU1 Xmlt bufter
;SLU2 Receive CSR
;SLU2 Receive butter
;SLU2 Xmit CSR
;SLU2 Xmit bufter

;Receiver active (RIO). Set
; while character 15 being
;
received.
;Recelver done (RIO). A
; character has been completely
received and now resides
;
in RBUF.
;Receiver into enable (R/w).
When set, enables -keyboard"
interrupts, using vector
at 60.

; OLART RECEIVE BUFFER BITS (RIO)

100000

RB.ERR

BIT15

;Error.

Framing error or

; overrun has occurred.

040000

RB.OVR

BIT 14

020000

RB.FRM

BIT13

004000

RB.BRK

BITll

34
35
36
37
38
39

177560
177562
177564
177560
176540
170542
176544

; OLART RECEIVE CSR BITS

19
20
21
22
23
24
25
26
27
28
29
30
31
32

=
=
=
=
=
=
=
=

;Overrun error. Character was
; received before previous one
;
was read.
;Framing error. No valid stop
; bit was detected.
;Break detect. Set when break
15 detected, reset when next
start b1t arrives.

KXTII-A2 lK FIRMWARE
GENERAL OLART EQUATES
1
2
3
4
5
6

MACRO V04.00

5-0CT-81 22:56:27 PAGE 7
; OLAI<T TRANSMIT CSR BITS

000200

XC.ROY

BIT7

000100

XC .lEN

B11'6

;Transm1tter ready (RIO).
When set, Ind1cates that the
last character was completely
sent and XBUF Is ready for
;
a new one.
;Transmlt into enable (R/W).
,When set, enables "console
printer" interrupts, using
vector at 64.

8
9
10
11

12
13
14
15
16
17

,
000010
000020
000040

Programma~le

PBRO
PBRI
PBil2

1.0

19
20
21
22
23
24
25
26
27
28
29
30
31
32

;

=
=
=

~aud

PBRO-2 set ~aud rates as follows:

000000
000010
000020
000030
000040
000050
000060
000070

BO.003
BO.OOb
BO.012
BO.02 ..
BO.048
1:10.096
BO.192
BO.384

=
.=
=
=

=
=

0
PBRO
I'BiH
PBR1!PBRO
PBR2
PBR2 PBRO
PBR2 Pl:IRl
PBR2 PBR1!PBRO

300
;Baud rate =
600
;Baud rate =
;Baud rate = 1200
;Baud rate = 2400
;Baud rate = 4800
;Baud rate = 9600
;Baud rate = 19200
;Baud rate = 38400

000004

XC.MNT

B1T2

000002

XC.PBE

bITl

000001

XC.BRK

bITO

;Ma1ntenance (R/W). when set,
creates an 1nternal "loopbaCK" between the transmitter
and rece1ver. Also disconnects tne external
lier1al 1nput.
;Frog. baud rate enable. wnen
set, the baud rate i5 determ1ned by bits 3-5 as
taDulated above. WHEN
eLgAR, BAUD RATE IS OEtEkMINEU Br VOLTAGES AP~LIEO
;
TO OLART IC PINS.
;Transmit breaK (R/W). When
set, serial output 15 a
cont1nuous BREAK.

42
4J

~1ts

BIT3
BIf4
BITS

33
34

35
36
37
38
39
40

rate

KXT11-A2 1K FIRMWARE
GENERAL PPI EQUATES

MACRO V04.00

5-0CT-81 22:56127 PAGE B
.SBTTL

General PPI Equates

2
3

PROGRAMMABLE PERIPHERAL INTERFACE (PPI) EQUATES

4
5
6

7
8
9

176206
176200
176202
176204

PP.CWR
PP.A
PP.B
PP.c

=
=

176206

176200
176202
176204

;PPI Control Word Register
IPPI Port A Register
;PPI Port Ii Register
;PPI Port C Register

PPI MODE-SETTING BITS

10
11

KXT11-AA board configuration does not permit all combinations of
tne mode bits. Consult tne manual before using tne PPI.

12
13

000200

PP.MOD

BIT7

000100
000040

PP.MD2
PP.MDA

=
=

BIT6
IIIT5

000020

PP.DRA

BIT4

000010

PP.CHI

BIT3

000004

PP.MDB

BIT2

000002

PP.DRB

BITl

000001

PP.CLO

BITO

16
18
19

20
21
22
23
24
25
26
21.
28
29
30
31
32

;Tnis MUST be or'd witn otner
; bits to set mode.
;Sets mode 2
;It bit 6 is low, dete~mines
; mode of port A
; (ni=mode 1, la-mode 0)
;Directlon Of port A.
; Hi=IN, 10=OUT.
;Dlrectlon of port C upper nalt
; Hl=IN, 10=OUT.
;Mode of port B.
; Hl=mode 1, lo=mode o.
;Directlon of port B.
; Hl=IN, 10=OUT.
;Dlrectlon of port C lower naIf
; Hl=IN, 10=OUT.

PPI BIT SET/RESET CONTROL BITS

34
35
36
37
38
39

40
41
42
43

45
46
47
4S

when blt 7 ls low, writlng to the PPI CSR wl11 set or reset
ind1v1dual blts 1n Port C, depending on the mode and dlrectlon
of tne port's blts, and on tne comblnation of bits you wrlte.
000016
000014
000012
000010
000006
000004
000002
000000

PP.BI7
PP.bI6
PP.BI5
PP.BI4
t'P.BI3
PP.BI2
PP.BI1
PP.8IO

000001
000000

PP.BIS
PP.BIC

=
=

=
=
=
=
=
=
=

BIT3!BIT21BITl
BIT31BIT2
BIT3!BIT1
BIT3
B1'1'2! BITi
BITi
BITl

fUse ONE
;of tnese
Ito select
;wnicn bit
;i& desired
Ito be
;SET or
;CLEARed

BITO

;SET specified bit.
;CLEAR speclfied b1t.

KXT11-A2 1K FIRMWARE
MACRO V04.00
PROGRAM-SPECIFIC EQUATES

5-0CT-81 22:56:21 PAGE 9
.SBTTL

program-spec1f1c Equates

2
3
4
5

, EQUATES USED TO TURN LED ON AND OFF
000221

MODE

PP.MODIPP.DRA1PP.CLO

7
8
9

000017

LEDOH

PP.BIS1PP.BI7

,Set PC7

000032

BAUDR$

BD.0241XC.PBE

;In1tlal console baud rate to
; be 2400, w1th prog. baud
, rates enabled.

000072

TUBAUD

BD.3841XC.PBE

;TU5S Baud rate

12
13
14

15
16
17
18
19

tI
I

.....

20
21
22
23
24
25
26
27
28

, EQUATES USED TO SET UP OLARTS

;

MEMORY CONFIGURATION EQUATES

RAM BOT
RAMTOP

...

160010
167716

;Bottom address of RAM
;Top address of RAM

000300
000340

PRl6
t'RI7

=
=

300
340

IPS for priority of 6
IPS for pr1or1ty of 7

000200

RFLAG

BIT7

000020

T.BIT

BIT4

Reg1ster flag b1t- Ind1cates
reg1ster 1s being exam1ned
Trace b1t 1n PSW

, SOFTWARE FLAGS AND MASKS
, USED tlY ODT MODUI"E

= 38,400

160010
167776

30
31
32

;Port A
Mode 0 IN
;Port B = Mode 0 OUT
;Port C upper nibble
OUT
;Port Clower n1bble = IN

KXTII-A2 lK fIRMWARE
MACRO V04.00
PROGRAM-SPECIFIC EQUATES

; RESTART TYPE WORD BITS

1
2
3
4

5-0CT-81 22:56:27 PAGE 10

100000
000200
000001

R.HALT
R.NXM
R.STAK

=
=
=

BIT15
BIT7
BITO

;HALT or BREAK occurred
IAccessed non-existent memory
;Double-bus error

; BOUT CONTROL IOORD BITS

7
8
9
10

100000

000200

DEVBIT

12
13

000001

DEVNUM

NO.LOw

=
=
::

BIT15

;NO memory found at 000000; do not boot

BIT7
BITO

=
=

;1
RX01/02 floppy
;0
TU58 cassette
;Unit no. (0 or 1)

15
16
17
18
19

ttl
N

; DIAGNOSTIC MESSAGES

000100
000010
000001

E.nT
1:..1111 T

E.PAk

=
=

100
10
1

;SLU2 loopback test tailed
;SLU2 internal loopback failed
I Parallel port loopback failed

KXTll-A2 lK FIRMWARE
MACRO DEfINITIONS

MACRO V04.00

5-0Cl-81 22:56:27 PAGE 11
.SSTTL MACRU DEfINITIONS

2
3
4

MACRO DEfINITIONS

5
6

7
8
9

Th1s macro will 1nsert ABORTS into the code which will halt the
program, exit to ODT with the PC printed on the console, and generate
an entry in the table of contents which descr1bes tne error condition.

10
11

9
w

13
14

15
16
17
18

.MACRO

.IRP
• SB'ITL
.ENDR

20
21

• Et.IlM

ABORT
HALT
PCS,\.

T~XT

.-2

-----> HALT Al PC='PC$ INDICATES ·'TEXT"

KXT11-A2 1K FIRMwARE
MACRO DEFINITIONS
1
2
3
4
5
6

MACRO V04.00

5-0CT-81 22:5&:27 PAGE 12

:+
DELAY A,B,N
where A and B are names of reg1sters that are free (both
be clear wnen through) and N is an integer.

Tnis macro produces a delay whose duration (when running in KXT11-AA
ROM) 1s .2399N seconds.
When N<4, it is more efficient to use the following code:

7
8
9

CLR
SOB
(SOB
(SOB

12
13
14
15
16
17
18
19
20
21
22
23
24
25
2&
27
28
29

~ill

Rn
Rn, •

2.44
239861.7&
239861.76]
239861.7&]

Rn, •
Rn, •

The macro generates code like tile following:
;

,n&:

MOV
CLR
SOB
SOB

IN,Ra
Rb
Rb, •
Ra,nS

."'ACRO
MOV
CLR
SOB
SOB
.END",

DELAY
'N,A
B
B,.
A,L

2W
1W
1W
1w

A,B,N,1L

3.6&
N*2.44
&5536N*3.66
N*3.66

KXTll-A2 1K f'IRM~ARE
RAM DEFINITION

MACRO V04.00

5-0CT-81 22:56:27 PAGE 13
.SSTH RAM Definition

2
; SCRATCH RAM AREA

4
5
6
7

167776

TRAP4

167776

167774

OOTOHY

167774

167772

O.CNIL

1&7772

167770
16770&
167764

B.CNIL
fI.PC
IN.USR

---==

167770
1677&6
1&7764

1677b2

R.Tnl:.

167760

USERSP

167756

RPUINT

167754
167752
167750
167746

SAVPS
SAVPC
OOTFLG
OOTLOC

==
-==
-----==

167744
167644

ODTSTK
SS'IACr.

--==

10
11

12
13
14
15
16
17

0
I

19
19
20
21
22
23
24
25
26
27
28
29
30

1617b2
167760
167"/56
167754
1&7752
1&7750
16774&
167744
00'fSTr.-100

;Enables trap-to-4 emulation
; when non-zero
;User-readable copy of R.TYPE.
; Restart cause.
See R.TYPE
table in RESTART routlne.
lOOT Control word. Set Bit 15
to disable T-Sit tilter, set
!lit 7 to disable Pr lor ity 7
filter.
;Boot control word.
;Where restart saves top of stack
;t:nables user-caused restart
; and BREAK when non-zero
;Restart cause. See table in
; RESTART routine.
;Used by ODT to store the user's
; stack pointer.
;Used oy 001' to point to the image
; of user's RO In its stack.
;Store halted PS here for OUT
;Store halted PC here for ODT
;Used by DDT for internal f189s.
;Useo by ODT to polnt to location
; currently open.
;Sottoru of DDT's stack
;Bottom of default user stack

KXT11-A2 1K FIRMWARE
RAM DEFlNITION
1
2

MACRO V04.00

5-0CT-81 22:56:27 PAGE 14
.=170000

170000

.SBTTL TRAPS-Trap-handling routines
.SBTTL lRAPS-LTC Trap-k1ller
.SBTTL TRAPS-BREAK handler

3
4
5
6

;"";";;;;,;;;;";;;;,;,;;;;";,;;;,;,;,;,,,,,;,,,,, ;i

;;I;I;;;;;';;;;;;;;;;;;;I;;';;;;;;;I;;;;;;;;I;;;;~;;;; ;;

8
9

; ; ;;
; ; ;;

.....
I

,
,

, , ,,

12
13

";;;;;;;;;,;;,,,,:"";",;,;;;;;;;;;,;;;;;;,,;;;,,,;Ii II;

;I ;;

;;;;;;;,;;';;;',;;';;1;;;;;;;;;,,;,;;;,;;;,;;;;;;;,,;;;;

BREAK-HANDLING ROUTINE
AND LINE TI~E CLOCK INTERRUPT KILLER

; ;
; ;;

15
16 170000
17 1700UO
18 170004
19
20 170006
21 170006
22
23
24
25
26 170010
27 170010
28 170014
29 1700:tO
30
11 170026
32 170032

i;'
; ;

$$$BRK::
005767
001001

TST
BNE

177760

IN.USR
BRKNUO

;Are we in user mOde?
;YES-Go to DDT

$$$LTC::
NO-Go oack to ROM program.
BREAKS are ignored oy ODT,
REStART, POWERUP and the
DIAGNOSTICS. The BOOTS
can be interrupted, though.

RTI

000002

BRKNOO::
012667
012667
012767

177736
177734
100000

005067
000167

177732
000544

177734

MOV
MOV
MOV

(SPH,SAVPC
(SPH,SAVPS
IR.HALT,R.UPE

CLR
JMP

IN.USK
DOT

Save context
for DDT.
Causes PC to be printed
upon entry to DDT.
Get out of user mode

KXT11-A2 1K FIRMWARE
RESTART-INTRODUCTION

MACRO V04.00

5-0CT-81 22:56:27 PAGE 15

1
2

.SBTTL RESTART-Introduction

3
4
5
6

;;1:;;;;;;;:;;;;;;:;:;;;;;;;;;;;;;;1;;;;;;;;:;;;;;;;;;iii;;;
;;;;;;;;;i:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;
; ; ;;
; ;; ;
; ; ; :
ii;;
RESTART MODULE
; ; I ;
;;;;
il;;i;;;;:;;;;;;;;;;;I;;;;;;;;;;:;;;;;;;;;;:;;;;;:;;;;iii;;;
;;;;;:;;;;;;;;;;;;;;;;;;;;:;;:;:;;;;;:;;;;;;:,;;;;;:;; ii;;:;

7
8
9

10
11

12
13
14
15
16
17
18
19

t:i
I

--..J

20
21
22
23
24
25
26
27
28

;i;

;The purpose of the RESTART routine Is to restore the fALCO~ to a
;Known state following those except10ns which cause a RESTART hardware
;actlon. This action consists ot stacking the current PSW and program
;counter, then setting the Psw to 340 and jumping to the hardwired
;RESTAMT location. Ihis location is at the address STARTi-4 where
;START is jumper selectable as 000000, 010000, 020000, 040000, 100000,
;140000, 172000 or 173000 (all in octal). This program is deSigned
;tor a START location ot 172000, thus RESTARTs jump to 172004.
;

;There are several different ways in which RESTART performs its
;function, depending on the value of IN.USR, TRA~4, the contents
lot the location the SP pOints to, and one bit (R.STAK) in R.TYPE.
;R.TYPE, the restart type word, is RESTART's output to DDT.
;-

; i-

;

32
33

;The goal is to maximize PDP-11 software compatibility and to provide
;useful debugging information to the program developer.

34
35

KXT11-A2 1K FIRMwARE
RESTART-INTRODuCTION

MACRO V04.00

5-0CT-ijl 22:56:27

PAG~

1
2

I R.$TRT I

3
4
5
6

Is the staCk

Enter v1a hardware mechan1sm,
w1th (PS)=340

flail set?
N
Y

7
9
9

10
11

9.....

12
13
14
15
16
17
19
19
20
21
22
23
24
25
26
27
29
29

30
31
32
33
34
35
36

37
38

40
41

42
43
44

45
46
47
49

50
51
52
53

54
55

56
57

i
Set R.NXM
I
I Set IN-ROM mode I
I
Go to ODT
I

Set stacie D1t
Read top of stack
Cheek 1f too close to "hole"
Clear stack bit

I<---Could time out and cause the
.<-----exit to ODT shown above
I

Did restart occur
1n user mOcie?
N
Y
I
----------------I
A BREAK does this when
I
Is top of
1<------"'-----

I staCk 0000001 I

.•

-----------------

there's no memory in
the vector area.

--------------1
Only a
Pop stack 1<-"'-----

frame and 1 1
return
••
--------------- I
• Set carry
I
1 1n pusned PS I
• and return •

BR~AK whlle 1n ODT can
get us here, so the RTI takes
us back to DDT.

I Leave user mocie •

I
Is top ot
•
1 stack OOOOOO? I
A BREAK does thls--->, Y
N 1
when there's no
----------------memory 1n the
•
vector area
---------------I
Pop staCie
1<---"'------Th1s entry polnt is 1n
trame ~nd go l i t h e TRAPS module. It Is
to BREAK's 1
I
where a BREAK 1n user mode
SAVE CONTEXT'
I
goes when there IS memory
entry poInt I
•
1n the vector area.

----------------

.
•

KXT11-A2 1K FIRMWARE
RESTART-INTRODUCTION

MACRO V04.00

5-0CT-81 22:56:27 PAGE 17

1
2
3

Pop stacK frame
if 172004 on top.
Get pushed PC.
Set UP ODT's PC
and PS locations.

4
5
6
7
8
9

10
11

12
13

COULO---->,
TIME----->,
OUT------>,

14
15
16
17

Test word prior
to where pushed
PC points

was tne word
a HALT
or did PC-->NXM?

18
19

20
21

22
23

t:l
I

24
25
26
27
28

, Set HALT flag ,
Go to DDT

29
30

trap-to-4
emulation
enaDled?

33
34
35

36
37
38
39

40
41
42
43

44
45

, Set NXM flag I
Go to ODT
,

Set user mode
Push "6, 814
onto stacI<
and RTI

KXT11-A2 1K FIRMWARE

MACRO V04.00

5-0CT-81 22:56:27 PAGE 18

R~START-INTROOUCTION

2
3
4
5

:+
:Exception-twpe word (R.TYP~) is passed to OOT and 15 RESTARTs "best Quess"
:as to why a restart happened:
Note: A user-readable copy of this word is at OOTWHY.

;

8
9

;1------1-----1-------;1 EXIT 1 BIT
:1------1-----1-------------1

10
11

NAM~

DDT

13
15
16

30
31
32
33
34
35

1
I

:I
; 1
,.

1
1
1

5
4
3

;1
:1

1
1

:IODT

;1
;1

1
1

11
11

39
40
41

R.NXM

I
1

I.
1

:1------1-----1--------

36
38

2.
25
29

~ompat1bll1ty.

1 13
TkAP 1 12
TO
1 11
."OUR 1 10

20
21
22
23

2&
27
28

HALT instruction in user code-RESTART POPS SlACK.
~ote-BREAK also sets tnis bit (see the TRAPS
module). DOT uses this bit for PDP-11 UDT

------1
OOT 1 14

'='
N

R.HALT

I 15

1 R.STAK

1
1
1

1
1

:1------1-----1-------;-

CAUSE

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Timeout during user access ot non-existant
memory
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Indicates that a timeout was caused by RESTART
itself accessing non-existant memory. Tnis
occurs in conjunction with testing for
validity of tne stack pointer.
in PDP-II parlance, th!s is a
"double-bus error"

KXT11-A2 1K rIRM~ARE
RESTART-ENTRY POINT

MACRO V04.00

5-0CT-81

~~:56:27

PAG~

.SBTTL RESTART-Entry point

1
2
3
4

ili;;i;I;II;;;;;;;;;;;;;;;I;;;;;;;;;;;;;;;;;;;I;;;;;;1iii;;;
iiliiI111;;;;;I,;;;;;;;I;;;II,;;;111;;;;;;;;;';;;;II;;iii;;;
; ;; ;
;; ;;
; ; ;;
;;;;
RESTART ENTRY POINT
;;; ;
1; ; ;
;;; I;;;;;;;;;;;; i-I;; jl I;;;;;;;;;;;;;;;;;;;;; II;;;;;;;;;;;;;;
;;i;;i;;;;;;;;;;;;;1111;;;,;;;;;;;;:I;;;;;I;;;;;;;;;I;ij;;;;

5
6
7

8
9

10
11 170036
12
13
14
15
16
17
18
19
20
21
22
23

R.$TRt: I
;;;i;;;;;;;;I;;;;;;;;;1;11;1;;;;;;I;;;;;;;;;;;;;;;;;;; I;;;;;

i;;;;;;1111;1;;;I;;;;;;;;1111;;;;;;;;;;;;;;;;;III,;;11iii;;;
""

""
;;;;
""
; ;; ;
;;; ;
;; ;;

IF THE RESTART ROUTINE CAUSED THE REStARt
GU r~ UDt AND PRINT "r"
THIS EXCEPTION CAN BE CAUSED BY RESTART'S
STACK MANIPULATIONS

ii;;
;; ;;
; ;;;

""
;;;;

....
; ;;;

,, ,,

;;; Ii;;;;;;;;;; Ii;;;;;;;,;,;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;;:1:;;::;;;::;;;;;;;;;;;;;;:;;;;;;;;;;;;;;;:;;;;;;;;;:;:;;

:.l4

......

25
26
27
28
29
30
31
32 170036
33 170042
34 170044
35
36 170052
37 1700~6

R.TYPE will have been cleared prior to entering
any ODT command. So, if tne stack bit is set, only R~START
itself could nave caused tne trap. Since the stack 15 always
valid in in-kOM mode, bad stack means we are in in-USER mode.

005767
001406

177nO

0~2767

000200

005067
000476

1777010

177710

;State: X=don't care, U=user, R=in-ROM---I
TSI
R.Ti'i'l
XIDid the stack test fall?
1$
BEw
XINO- gO to next test
BIS
'k.NXM,I<.TYP~
UIYES- set R.NXM
UI this forces "1" from OOT
CLR
IN.USR
Rlenter in-RuM mode
ij$
BR
Rlgo to ODT

KXTll-A2 lK FIRMWARE
MACRO V04.00
RESTART-SE~ IF STACK EXISTS

.SBTTL

RESTART-see 1f stack ex1sts

...
" , i;;;;;;;;;;,;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;,,;;;;;;

2
3
4
5
6

, , , i;;;;;;;;;,;;;;;,;;;;;;;;,;;;;;;;;;;;;;;,;;;;;;;;;;;
",
i ; ;
;; ;
;; ;

8
9

10
11 170060
12
13 170066
14 170070
15 170072
16 170076
17 170100
18
19
20
21
22
23
24
25
26
27
28
29
30
31 170104
32 170110
33 170112

5-0CT-81 22:56:27 PAGE 20

'"
052767
005716
000240
005766
000240
005067

000001

177674

lSI

0000U4
177656

STACK VALIDITY TEST

170114
36 170116
37 170120

,;...
"
;;

iiiii;;;;:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;,;;;;;,;;,;;; ii;
iiiii;;;;;;;;;;;;;;;,;,;;;;;;;;;;;;;;;,;;;;;",;;;;; ii;
SIS

'R.STAK, R.TYPE

TST
NOP
TST
NOP
CLR

(SP)
4(SP)
R.TYP~

;XIIf we t1meout, we want RESTART
;XI to know we'were d1ddling SP
;Xlsee 1f stack 15 val1d
;XI(1n case times out)
;xlsee if too Close to top of
,XI val1d memory
;Xlstack is OK

.SBTTL RESTART-Exit if in IN-ROM state
; ; ; ii;;;;;;;;;;;;;;;;;;;;;;;;;;;,;;;,;;;;;;;;",;,;;;;;;;ii
; ; ; i;;;;;;;;;;;;I,;I;;;;;;;;;;;;I;;;;;;;I;;;;;;;;;;;;;;;; ;;
;; ;
;; ;
RETURN WITH CARRY S~T IF IN "IN-ROM" MODE
I'"~
,,,,
;; ;
;; ;
UR, GO BACK TO ODT IF A BREAK wITH NO LOw MEMORY;;,;
;;;
; ; ;J
; ; ; ;i;;;;;;;;;;,,;,;,;;;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;'i
; ; I li;;;;;;;:I:1;1:1;1;I;1:1;;;;;;I;;;;;;;;"";:;;;;;;;; "

....

005767
001007
005716

171654

TST
BNE
TST

IN.USR
3S
(SP)

BNE
CMP
RTl

;XIAre we ~n
,UIYEs-go to
;RINO-see if
;RI us nere
,RINO-Just a

(SP)ot-, (SP)-t

;~IYES-Behave

INC

2(SP)

34
3~

;i;
;i;
;;;

001002
022626
000002

user mode?
next test
BREAK brought

RESTART
like a BREAK that
;RI happened with RAM

39 170122
40
41 170126
42

005266
000002

000002

2$:

RTI

RISet carry 1n pu~hed PS
HI UNLESS ALR~ADY SET
Rland return to ROM code that
RI caused timeout

KXTII-A2 1~ FIRMWARE
MACRO V04.00
RESTART-CAUSE DETERMINATION

5-0CT-b1 22:56:27 PAGE 21
.SBTTL RESTART-Cause determ1nat10n

1
2
3

;1;;1;;1';;;;;;;;;;;;;1;1;;1;;:;;;1;;;;;;;11;;;1;;;1;;Ii;;;;

;;ilill;;11;;;;II;;;;I;;;;;;;;;;;;;I;;;;;;1;11;1;;;I,;iii;;;

5
6

;; ; ;
;; ;;

I; I ;

8
9

;;;;;;;;;;;;;;;;;;;;;;;; Ii;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; II;;

DETERMINE HOw USER CAUSED A RESTART

1; ; ;
;;;;
;; ;

;;;:;;;;;;;;;;;;;;;;;;;;;;;;;111;;;;;;;;;;;;;;;;;;;;;;;i;;;;

10
11 170130
12
13 170134

177630

CLR

IN.USH

005716

TST

(SP)

001003
022b26
000167

BNE
CMP
JIIP

005067

3$:

tJ
I

tv
W

15 170136
16 170140
17 170142
18
19
20
21
22
23
24
25
26
27 170146
211 170152
29 170154
30
31
32

177642

If the CPU attempts to fetch an instruction from· non-existent
memory, two traps (the first from execut1ng a HALT, the second
from timing out) will occur, the result being that second
trap pushes tne restart address and 340 on the stack.
This information is useless and gets popped here.
021627
001001
022626

172004

4$:

CMP
BNE
CM!'

170156
170162
170166

012667
011667
014667

177604
177566
177560

170172

162767

000002

41 170200

005777

177562

TST

100000

42
43
44
45
46
47
48
49

(SP),IRI:;STAR
5$

(SP)+, (SP)+

;XIGet r1d of double stack1ng
;Xlcaused b¥ EXECUTIU~ of NXM
;X I

Note: Because the contents of the stack is assumed to remain
unChanged folloNing the first instruction below, it is imperative
that 1nterrupts be disabled during the next three instrutions.

34
3!i
36
37
38
39
40

(SP)+, (SP)+
BRIiNUO

;UIWe were 1n user mode,
;RI but no longer.
;RISee if BREAK brought
;RI us here without low "core".
;RINO-Just a RESTART
;RIYES-Sehave like a BREAK that
;RI nappened while in user prog.

5$:

177566

MOV
MOV
MOV

(SP)+,R.PC
(SP),SAVPS
-(SP),SAVPC

;RIGet pushed PC
:RluDT would like
;Rlto see these

SUIl

'2,R.PC

;RISet pointer to last word fetched
;RI before restart occurred
;RIIs contents of pushed PC - 2
;kl a zero (eg a HALT)?
:RIMake sure next instruction
;RI won't execute if we time out
;RINU- it was an NXM
:RIYES- Flag a HALT,
:RIPoP tne non-PuP-ll stack frame
;Rland yo to OOT.

170204

000240

NOP

170206
170210
170216
170220

001005
052767
022626
000415

Bt<E
BIS
CMP

81<

177544

fR.HALT,R.TYPE
(SP)+, (SP)T

KXT11-A2 1K FIRMWARE
RESTART-EXITS

MACRO V04.00

.SBTTL RESTART-ExIts

1
2
3
4

i:;;i;;;I;;;;;;;;;;;:;;;;;;;;;;;;;;;;;;;;;;;;;;;;:;:;;i:;:;:
;:;;:;;;;;;;;1;:;:;;;;;:;;;;;;:;;;;;:;:;:;;;;;;:;:;;;;I;;;;;

,,,,

,, ,,

;;; ;

6
7

;; ;;

EXIT APPROPRIATELY

, ,,,
............................................................

, , I

, ,

, , , ,

, ,

, , ,

, ,

, , ,

, ,

, , ,

, "

, ,

, , , ,

, ,

:i;;;;;;;;;;;;;;;;;;;;;;;;:;;:;;;;:;;;;;;;;;;;;;:;;:;; I;;;;;

9
10
11 170222

12
13
14
15
16
17
18
19

5-0CT-81 22:56:27 PAGE 22

177550

170226
170230
170234
170240
170244

005767
001407
005167
013746
013746
000002

177530
000006
000004

170246
170254

052767
000167

000200
000322

6S:

177506

7$:
8S:

TkAP4

TST
Bt:Q
COM
MOV
MOV
RTI

IN.USR
@'6,-(SP)
@#4,-(SP)

;RITrap-to-4 emulatIon enabled?
;RINO-go to COT
; U IYES-Set user mode
;UIEmulate a
;Ultrap to
;Ultour

BIS
JMP

#R.NXM, R.UPE
ODT

;Rlflag NXM error
;Rlgo to ODT

KXT11-A2 lK FIRMWARE

MACRO V04.00

~-OCT-81

22:56:27 PAGE 23

POWERUP-INTRODUCTIO~

.SBTTL POWERUP-Introduction

2
3

4
~

1
8
9

10
11
12
13
14
15
16

17
18
19
20

21
22

;;;1;;;;;';;,; II;;'; 11;;;;;I;i;;;;;;;; II;;;;;;;;;;;;;;;;;;;;
;; II;; I:;;;;;;;;;; I; I;;; 1:;;;:;;;1;;;;;;;;;;;;;;;; Ii;;;;;;;;
I;;;
Ii;;
;; ;;
POwER-UP MODULE
il:;
I I ; ;
;i;;;;;;;;;:,;;;;;;;,;;;;;;I;;;;;;:;;;;;;;;:;;;:;;;:;; I;;;;;
1;;;;;;;;;;,;;;:;;;;;;;:;;:;;;;,;;;:;;:;;;;;;;;";;;;:; I;;;;;;

This module contains a series of routines which perform
tests on the on-board RAM and the console DLART. These
tests are preceded by the lighting Of the LED on the
KXT11-AA board, and followed by its extinguishing. Should
the LED fail to either light or go out, there may be a
defect in the board or its configuration.
following these tests, the on-board RAM is written with the
default values of certain control words, and, 1f there is
memory in the vector region (i.e., near 000000), the BREAK
and ClOCK vectors are set uP. It not, a bit 1s set in the
boot control word to disable the bootstraps.

KXT11-A2 1K FIRMWAHE
POWERUP-TURN ON LEO

MACRO V04.00

5-0CT-81 22:56:27 PAGE 24
.SBTTL

1
2

.... " " .................. " " " .... " .... " ............ " " " " " .... " ......... " .. " ............ " " " " .... " .... .
",",,,,,.,,""""",,,,,"",,,,,",",,",,""",.,,,,

4
5
6
7
8

N
0\

;;;;

", ,

,,,,
,.. ," ,....,

TURN ON LEO

i;;;;;;;; i;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; i;;;;;;;;;;;;;;;;;;

9
10
11
12 170260
13 170260
14
15
16
17
18
19
20 170264
21
22
23
24
25
26
27
28
29
30

; i-j ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

PWRSUP::
012706

167644

MOV

170272

;lnitialize stack pointer

USTACK,SP

Because a mode-setting command automatically clears all the internal
registers in the PPI, and clearing Port C Bit 7 turns on the LEO, all
we have to do is set toe mode, which is port A and 10 naIf of C as
input, ports B and hi half of C as output.
012737

000221

170206

;Set proper PPI mode

MUV

.SBITL POwEKUP-Test console OLART
;;;;;;;;;;;;;;i;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;
" """ " " "" " """ """ " "" " "" """"""""" """" """""" " " "" " "" " " " """""" "" ""
"
;;;
; ;"
; ; " " " " " " " " " " " " " " " " " " " " , . " " " " " "; "

CHECK THE

CO~SULE

,, , ,
,,,,

DLART

ii;;;;;;;;;;;;;;:;;;;;;;;;;;:;;;;;:;;;;;;;;;;;;;;;;;;;ii;;:;

" " " " " " " " " " " " " " " " " " " ." " " " " " " " " " " , " " " " " " " " " " " " " " " " " " " " " " " " " " " "
""""",."""""""""""""""""""""",,,,

32
33
34
35
3b
37
38

on LEO

PU~ERUP-furn

.... " " " " " ................................ , ............................ " .. " .......... " ........
.. " .... " ..
",.,,,"""""""",."""",.",.",.",.,.,
.. " " """

005037

CLR

1775b4

@UCSkS1

; Disable XMlT interrupts,
; BRK XMIT, maint. mode

17n7b
170302

v05737
032737

170310
39 170312
40 170320

001377
023727
001377

177502
00030U
177504

177500
000200

TST
BIT
BNE
CMP
BNE

@#RBUFS1

Set baud rate to default
;Take out the trash.

.<RC.IE~!RC.DUN>'@'RCSHS1

;Should be clear.
not, drop dead.
;Snould be set
; I t not, rest in peace.
;If

IHXCSRS1, HC.RDY

KXT11-A2 1K FIRMwARE
MACRO V04.00
POWERUP-TEST AND SET UP I/O-PAGE HAM

~-OCT-81

22:~b:~7

PAG~

.SBTTL POwERUP-Test and set up I/O-page RAM

1
2

;;;;;i;;; i;;;;;; li;;;;;;;;;;;i;; J;;;;;;;;i;; i; i;;;;;;; Ii;;;;

)

:;;;;;;;:;,;;;;;;;;;;;;;:;;;;;;;;;;;;i;;;;;;;;;;;;,;;;iii;;;

; ;;;
;;;;
;; ;;
;;;;

7
8
9

;;;
1/0 PAGE RAM TEST

AND INITIALIZATION

;;;;
;;;;

....

,,,,

;i;;;;;;;;;;;;;;;;;;;;:;:;;;;;;;;;;;;:;;;;;;;;;;:;;;';iii;;;

:;;:;;;:;;;;;;;;;;;:;;:;;;;;;;;;;1;;;;;;;;;1;;;;;:;;1; iii;;;

write the location's address into the location and read it baCk.
Do this for all 110 page RAM locations.
If it fails, enter tight loop.

12
13
14

15
16
17
18
19 170322
20 170326
21 170330
22 170332
23 170334
24 170336
2~ 170342

In the process, clear all of this HAM. Note that the default
value of most of tne control and flag words is zero.
0127011
010010
020010
001377
005020
020027
103771

160010

ls:
2$:
170000

MOV
MOV
eMF
i:!N~

CLR
CMP
8LO

'RAMI;QT, RO
RO, (RO)
RO, (fW)
2$
(kO)+

RO,iRAMTOP+2
1$

,Lowest address of RAM
,Write the adaress
:Read it baCk
:Tight failure loop
;Clear and go on to next location
; Until no more to test.

KXTll-A2 lK FIRMWARE
OfF LED

MACRO V04.00

5-0CT-81 22:5&:27 PAGE 26

PO~ERUP-TU"N

.SBTTL POWERUP-lurn off LED

1
2

iii;;:;;;;:;;;:;;:;;;:;;;;;;:;;;;;;;;;;;;;:;;;:;:;;;;:iii;;;
; ; ; ; .i ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
;;; ;
;;;;
, ,,
;;;;
D~LAY SO THAT LED IS ON A VISIBLE LENGTH OF TIME

:.
6

,,,,

;;;;;;;;;;;;;i;;;;;;;;;;;;;;;;;;;;;;';;;;;;; i;;;;;;;;;;;;;;;
; ; ; ; ; ; ; ; ; ; ; ; ; ; I;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Ii;;; i;;;;;;;

,, ,,

10
11 170344

12
13
14
15
16
17
18

17034b
170350
170352
170354

005000
077001
017001
077001
077001

CLR
SOB
SOB
SOB
SOB

3S:
4$:
5$:
6$:
;

RO
RO,3$
RO,4$
RO,5$
kO,6$

;Tllis leaves a 0 in RO, IOlllcll
is essential for testing for
the presence of memory at
zero below.

Under no Circumstances can 1(0 be altered until "lOW core" test below.

:;;:i;;;;;;:;;;;;;;;;;;:;;;;;;;;;;;:;:;;;;;;;;;:;;;;;;:i:;:;
;i:i:;;;;;;;;;:;:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;:;
,,,,
;; ;;
;;;;
; 1; ;
rURN OFf LED

, , ,,

24
2:'

;;;;;;;;;;;;;;;;;;;;;;;:;;;;;;;:;;;;;;;;;;;;;;;;;;;;;;iii;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;:iii;;;

20
21

o
I

27 17035b
28
29

012137

000017

#LEDOFF,@,PP.CWR
.SBTTL POWERUP-Test for "lOW core"

30
31
32

....... ................................................... .

iii:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;iii;;;
~

""""""""""""""""""""""""""""""
; ; ; ;
,,,,
;; ;;
TEST fOR MEMORY AT OOOOuO

33
34

;;;;

35
36
37
38

;;;;;;;;;:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;I;;;;;
;:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;:;;;;:;;;;;iii;;;

Read memory at 000000, discard result. If tills fails, exit to
AUTOBAUD ratller tnan continuing witll normal powerup sequence.

3\1

40
41
42 170364
43 170366
44
4f> 170370
46 170372
47 170376
48
49 170400
50

MOV

17620b

TST

005710
000240

(RO)

NOt'

103403
004767
000403

000042

052767

100000

177362

7$:

BCS
CALL
bR

VECSET

IllS

tNO.L,OW,B.CNtL

7$
~$

;This will execute even 1£
; last instruction times out
;l'lmed out, don't set vectors
;Di<in't time out, so go allead
;Don't set the NO. LOW flag
;Dld time out,
; so let tile world Know.

KXTII-A2 lK FIRM~ARE
POwERUP-EXIT

MACRO V04.00

.SBTIL POWERUP-Exit

1
2
3
4
5
6

...

.......

........ ...

...

. ... ............... .. .

...

,.
,. ,.
,. ,.
"
,. ,. " ,. ,. ,. ,. ,. ,. ,.
,.
,. ,.
,. " .... " ,.
,. . .
",,",",,""",,,,"""",",,,",,,"",,""""",,"
;;;;;i;;;;;;;;;;;;;;;;;;;;;;;i;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;
ii;;
;;;1
;;;;
; ; ; ;
EXIT FROM POwER-UP SEQUENCE
; ; ;;
;; II;;;;;;;;,;;; I;;;;;;; I;;;;;;;;;;;;;;;;;;;;;;;;;;; i;;; i; i;

7
8
9
10

11
12
13
14
15
16
17
18
19
20
21
22
23
24

5-UCT-81 22:56:27 PAGE 27

;;;; I;;;;;;;;;;; li;;;;;;;;;;;i;;;;;;;;;;;;;;;;;;;;;;;i;;;;;;

170406
170414
170422

012767
012767
000423

000300
170424

170424
170424
170430
1704J4

005067
01270&
000167

177334
167644
000142

171340
177330

8$:

MOV
MOV
Sf<

'Pf<16,SAVPS
'FAKUUl',SAVPC
AUTOBA

CLR
MOV
JMP

IN.USk
U$TACK,SP
DDT

;1£ P is typed in reponse to
DDT prompt before lOading R7,
will force yet more DDT.

fAI<.OUT:
BUT IN THE RIGHT MODE!
And wltnout running out Of
staCK, either.

.SBTTL POWERUP-Subroutlne to initialize vectors
;;;;;;;;;;:;;;;;;:;:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;I;;;;;

............................................................................................

....

,,,,
;""""""""""""""""""""""""""""""
;;;
,, ,
; ; ; ;
INITIALIZE VECTORS

2:)

,......
,,,

,,,,

26
27
28
29
30
31
32

;;;;;;;;;;;;;;;;;;;;;;;;;; I;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;

Note: This subroutine is also used by the bootstrap module, to
restore the vector area in tne event that an invalid boot blOCK
was read into low memory.

34
35
36
37
38
39

170440
170440
170,*4&
170454
170462
170470

VECSET::
012737
012737
012737
012737
000207

170000
000340
170006
000340

000140
000142
0001!J0
000102

MOV
MOV
MOV
MOV

RETURN

#$$$8RK,U140

#PRL7,!il#1,*2
I$$SLTC,@UOO
11'1<17 ,Ul02

Set up the BREAK-detect
vector.
Set up the line time clOCK
vector.

KXTll-A2 lK ~lRMWARE
MACRO V04.00
AUTOBAUD-SINCHRONIZE WITH CONSOLE

5-0CT-B1 22:56:27 PAGE 2ij
.SBTTL

AUTOBAUD-synchron1ze with Console

2
; i;;;;;;;; ii;;;i;;;;;i;;;; Ii;;;;;;;;;; li;;;;;;;;;;;i;;;;;;;;
;;;;;;;I;;;;;;;i;;;;;;; i;;;i;;;;;;;;;; li;;;;;;;;;;;i;;;;;;;;
ji;;
Ii;;

3
4
5

,........
,,,
AUTOBAUD MODULE
,, ,,
,,,,
........................................................................................................................
"""""""","1""'","""""""""""""
"""
;;;;;;;;;;;;;;;;;;;;;;;;;; ji;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

I:>

7
8
9

10
Oescription:

12
13
14
15
16
17

AUTOBAUD allows the FALCON to automatically synchronize its
console DLAHT to the baud rate of the console terminal.
On power-up, the user must type a carriage return character.
Upon synchronization, AUTOBAUD will proceed to DDT where an .~.
character will be displayed on tne console.

18
19

Autobaud will loop indefinitely until synchronization is successful.

20
21
22
23
24
25

The algorithm requires that the console terminal generates a
zero (space) for the eighth bit in the carriage return. This
will happen it the terminal Is capable ot sending eight-bitno-parity or seveo-bit-odo-parity Characters.
Environment:

29
30
31
32
33
34

Interrupts must be disabled for the algorithm to execute correctly
since time durations are critical and delays due to long
service routines may cause DLART overruns, ~hicn this routine
ignores but cannot tolerate.

VTI03/FALCON configurations leave garbage in tne DLART long atter tne
po_erup sequence has beyun. we must delay a bit oetore clearing garbage
out of tne DLAR1, otherwise the garbage would arrive after the clear
(i.e., while pOlling tor input). Tne "qarbage" is an X-ON «CIHL-q»
that the VT-IOO hardware sends after its power-up diagnostics have
completed successfully.

3/:>
37
38

40
41
42
43 170472
44 170472

1705uO
46 170502
47 170504
4~

AUTOBA::
01:.1737
005000
077001
077001

000032

1775/:>4

MOV
CLR
5GB

#BAUDRS,@#XCSRSI
HO
RO,.

5013

£<0, •

;Set 2400 baud
;Delay
.5

seconds

KXT11-A2 1K F'IRMWARE
AOlaBAUD-Sr~CHRUNIZE

tI
I

1
2
3 170506
4
5 170!)12
0 170516
7 170520
8 170524
9 170530
10 170532
11 170534
12 170540
13 170542
14 170544
15 170546
16
17
18
19
20 170550
21 170550
22 170551
23 170552
24 170553
25 170554
26 170555
27 170556
28
29
30
31 170551>
32 170550
) j 170502
34 17051>4
35 170506
30 170570
37 170572
38 170576
39 170600
40
41

MACRO V04.00
wIl'H CUNSOLt:

5-0C1-81 22:56:27 PAGE 29
;

AUTOBAUD proper:

105737

177562

10$:

TSIB

URBUf$1

dlscard any garbage

105737
100375
113700
012701
120021
001411
020127
001373
005000
071001
000757

177560

20$:

TST8
BPL
MOVB
MOV
CMPB
BEQ
CMiBNE
CLR
SOB
BR

URCSR$1
20$
UI<BUf$l, RO
UNBYTI;;, R1
RO, (R1H
HVBAUO
R1, UNBYTS
30$
RO
RO, 40$
10$

walt for input

177562
170550
30$:
170550
406:
;

RO ; input character
R1 -> scrambled char table
In the table?
yes
end of table reached?
not yet
uh oh, walt for DLART to clear out
wait for a whlle
and try for another character

Table of what you would see If an octal 15 were sent at the fOllowlng

; baud rates.

HHIYTE:
200
170
Ho
015
362
377

.BYTE
.BYTE
.BnE
.BYTE
.Bnt:
.BYTE

200
170
340
15
362
377

300
600
1200
2400
4800
9600, 19200, 38400

INBYTS:
;

we have a match.

set baud rate Into DLARr.

1!VIlAUD:
162701
000301
00&301
005201
006301
010137
005000
077001

170551

177564

SUB
ASL
ASL
INC
ASL
MaV
CLR
SOB
f'all Into ODT.

UliitHTE+l, Rl
R1
Rl
R1
R1
Rl, i.lUCSR$l
RO
RO, •

turn pointer 1nto bit maSK
turn on XC.PBE
set tne baud rate
into CSR
delay .24 seconds for rest
of char. at 510 baud rates

KXT11-A2 1K fIRM~ARE
MACROODT-INTRODUCTlON

MACRO V04.00

5-0CT-81 22:56:27

PAG~

.SBTTL

macroODT-Introduction

;;;;;;;;;;;;;;;;;;;;;;;;;;;:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;
;;1;;;;;;;;; ii;;;i I;;;;i ;;;;;; I;;;;;; ii;;;;;;I;; ;;;:;;;; Ii;;
,, ,
; ;;;

macroODT

3
4

1
8
9

,,,,

,......
,,,

i;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;:;;;Ii;;;;
;i;;:;;;;;;;,;;;;;;;;;;;;;;;;;;;;;;;;;;:;;;;;;;;;;;;;;iii;;;

10
11

12
13
14

15
16
11

18
19

20
21
22
23

24
2!>
2b

tJ
I

W
N

27
2~

29
30
31

macroODT 1s the user interface to the functions contained
in the KXT11-A2 firmware product. It interprets commandS
entered via the console terminal keyboard (see tables oelow)
to permit the user to load a program into memory, execute
it and debug it.
COMMAND
1- Slash (Il
a-OPEN MEMORY LOCATION
b-OPEN GENERAL REGISTER
c-OPEN STATUS REGISTER
2- Carriage return «CR»
a-CHANGE AND CLOSE ~EMORY LOCATION UR R~GISTER
o-CLUSL WITHOUT CHANGE
3- Line feed «Lf»
a- CHA~GE AN~ CLOSE MLMURI LOCATION AND OP~N NEXT
b- CLOSE MEMORY LUCATlON wITHUUT CHANGING AND OPEN NEXT
4- (,0 (G)
!>- Proceed (Pl

6- Execute 1/0 diagnostics (X)
7- ~xecute bootstraps (D)

KXT11-A2 1K FIRMWARE
MACROOOT-IhTRODUCTION
1

2
3
4
5
6
7
8
9

MACRO V04.00

5-0CT-81 22:56:27 PAGE 31
;SINTAX OF COMMANDS LIStED ABOVE, SHOWING CONSOLE BEFOHE,
;DURING AND AfTER THE TI~!NG OF THE COMMAND.
Key: n-an octal integer typed by the user, only
last b digits signiticant
x-a single octal digit
u-the diglts 0 or 1
all other characters are literals
BEFloHE

DURING

AFTER

IiInl

IiIn/xxxxxx
IlIRx/xxxxxx
IiIRS/xxxxxx

;

;la ~

nb III
IiIRxl
;1c III
IIIRSI
;2a @n/xxxxxx
f!ln/xxxxxx n<CR>
iii
;2a IiIRx/xxxxxx
IlIRx/xxllxxx n<CR>
III
;2a IiIRS/xxxxxx
@Rx/xxxxxx n<CR>
iii
;2a xxxxxx/xxxxxx xxxxxx/xxxxxx n<CR> III
;~b @n/xxxxxx
IiIn/xxxxxx <eR>
iii
;2b @Rx/xxxxxx
IiIRx/xxxxxx <CR>
~
;2b IlIRS/xxxxxx
IlIRS/xxxxxx <CR>
iii
;20 xxxxxx/xxxxxx xxxxxx/xxxxxx <CR> iii
;3a IiIn/xxxxxx
IlIn/xxxxxx n<LF>
xxxxxx/xxxxxx
;3a xxxxxx/xxxxxx xxxxxx/xxxxxx n<LF> xxxxxx/xxxxxx
;3b IiIn/xxxxxx
xxxxxx/xxxxxx
IiIn/xxxxxx <LF>
;3b xxxxxx/xxxxxx xxxxxx/xxxxxx <LF> xxxxxx/xxxxxx
;4 iii
IlInG
@P
;5 iii
IilJ(
;6 iii
xxxxxx

14
15
16
11
18
19

20
21
22

23
24
25
21>

27
28
29

;

;7
;7
;7
;7
;7

32
33
34
3!>

iii
iii
iii
iii

iii
III
@

IjIDDu
IiIDXu
IiIDlu
IiIDU<CR>
IiIDX<CR>
(iDI<CR>

KXT11-A2 lK FIRMWARE
MACRO V04.00 5-0CT-81 22:56:27 PAGE 32
MACROOOT-SAVE STATUS AND PRINT PROMPT
.SBTTL macroODT-Save status and print prompt

ii;;;;;;;;,,;;;;;;;;;;;;;;;;;;;,;;;;;;;;;;,;;;;;;;;;;;iii;;;

3
4
5
6

ii;;i;;;;;:;;;;;;;;;;;;;';;':;;;;;;;;;;;;;;;;;;;;;;;;;Ii;;;;
;;; ;
; ;; ;
;;; ;
;;;;
SAVE CON1~XT, PRINT MESSAGES AND PROMPT
;;;;
lin

;;;;;;;;;;;;;;1;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;1 iii;;;
i;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;:;;;;;;;;;;;;;;;;;;iii;;;

8
9

10
11 170602
12 170&02

ODT::
105737

177562

TSTB

URBUt$l

;Clear out console garbage

; Copy the restart type word into user area

16 17060&
17
18
19
20 170&14
21 170&20
22
23
24
2~ 170&24
26 170630
27 170632
28 170634
29 170636
30 170640
31 170642
32 170644

010767

177150

010&&7
012706

177140
1&7744

177100

MOV

R.TYPE,UDTWHY

Protect aga1nst stack timeouts, but save user's SP first
MOV
MOV

SP,USERSP
'ODTSIK,SP

;SAVE USERS STACK POINTER
;LOAD NE" SP

Save rest of user program's context
016716
010540
010446
010346
010246
01014&
010046
010067

177130

MOV
MOY
MUV
MOY
MOV
MOV

177106

MOV

''IOY

USERSP,(SP)
R5,-CSP)
R4,-CSi:')
R3,-CSP)
f<2,-(SP)
Rl,-(SP)
RO,-(SP)
SP,RPOINT

;RESERVE LOCATION FOR R&
;SAVE
ALL
OF
USER'S
GEhEf<AL
REGISTt:;f<S
:POINTER TO RO

Determine whether "J" or PC message is appropr1ate, and print it

35
36 170650
37 170&54
38
39 170&56
40 1706&2
41 170666
42 170666
43
44 170072
45
46
47
48 170674
49 170674
50 170700
51 170702
52 170702
53
54 170700
55 170712
56 170716
57 170722

005767
100004

17710&

TST
BPL

R.TYPE
QUilT

016700
004 "/6 7

177070
0007&4

MOV
CALL

SAVPC,RO
OCTSTO

105767

177070

TSTB

R. TYPE

BPL

KBDS

;Did we get a HALT or BREAK?
;NO-next question
:YES-PRINT PC
: GET S'rOPPED PC
;lYPE THE PC Oh TERMINAL

QODT:
100003

;SE£ IF RESTART OCCURRED
;CNXM ONLY-BIT 7 SET)
:TYPE PROMPT

; Here's where tne prompt gets pr1nted, with or w1thout leading

"1"

KBD!H
012700
000402

171730

012700

171731

005067
106427
004707
00!:>067

000300
000620
177022

MOV
BR

U'SGQ,I<O
PRINT

; GET 1 ADDRESS
;TYPE IN MESSAGE

MOV

'MSGS,RO

:GET PROMPT MESSAGE ADORESS

CLR
MTPS
CALL
CLR

R.TYPE
fPRI&
PUTSTR
ODU'LG

So reentry gives no error msg.
Allow BREAKs to happen
TYPE THE PROMPT ALREADY
CLEAR FLAG FOR hEW ENTRY

KBDS:
1770~0

PRINT:

KXT11-A2 1K FIRMWARE
MACRO V04.00
MACROODT-GET OOT COMMAND

5-0CT-81 22:56:27 PAGE 33

.SBTTL

macroODT-Get ODT command

2
j

;i;;;;;:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;';;;;;;;;;;;;;;;i

i;;;;;;;;;;;;:;;;;;:;:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;:;i

;ii;
;; ;;

INTERPRET FIRST CHARACTER OF COMMAhD

;; ;;
;;;;;;;;:1';1;;;;;;;:;;;;:;;;;;;;;1;;;;;;;;;;;;;;;;;;;Ii
;;ili;;;;;;;;;;;;;;;;;;;:;;I;I;;:;:;;;;;;;;;;;;;:;;;;;;i

7
8
9

10
Note: following CALL GETCHR, the character (7 bit ASCII)
appears in R2.
t<ote: following CALL GETNUM, If carry Is clear, the octal integer
was followed by a carrIage return.
Note: On exIt to LCSET or falling through to GO routine, RO contaIns
the address typed in.

12
13
14
15
16
17
18 170726
19 170732
20 170736
21 170740
22
23 170744
24 170750
25 170752
26
27 170756
28 170762
2!1 170704
30 170770
31 170772
32 170776
33 171000
34 171004
35 171006
36 171010
37 171014
38

004767
1211227
001002
000167

000556
000104

CALL
CMPB
BNE
JMP

GETCHR
R2,.·O
BUOTS

; ••• INPUT CHARACTERS
;BOOTSTRAPS?
;NO
;YES

1$:

CMPB
BNE
JMP

R2,f'X
2$
OIAGNO

;DIAGNOSTICS?
;NO
;YES

2$:

CMPB
BEQ
CMPB
BEQ
CMPB
BLO
CMPB
BHIS
CLR
CALL
BCC

R2,#'P
PCIiIO
H2,,'R
RCMD
R2,.·0
KBDQ
k2,,'8
KBDQ
RO
GETNUM
KBUQ

;PROCEED?
;rES
;REGISTER?
;YES
;OCTAL DIGIT?
;hO,ERHUR
; VALID OIGIT?
;NO,ERHOH
;ITS A DIGIT
1GET REST Uf THE DIGIT OR" CMD
;CR WAS ISSUED,ERROR

001no

120227
001002
000167

000130

120227
001430
1202:t7
001465
120227
103736
120227
103333
005000
004767
103327

000120

000776

000122
000060
000070
000576

The last character at the end of the number could be a valId commandLet's cheek:

40
41

42 171016
43 171022
44 171024
45 171030

120227
001511
120227
001321

000O~7

000107

CMPa
BEQ
CMPB
BNE

R2,.·/
LCSET
R2,.'G
KBDQ

EXAMINE LOCATION?
YES
GO TO?
NO, ERROR

KXT11-A2 1K FIRMWARE
MACRO Y04.00
MACROOPT-G~T ODT COMMAND

1
2
3
4

5-0CT-81 22:56:27 PAGE 34
TABLE OF PEHMISSABLE STATES
hOe

STAT~

prompt @

!I
6

7
8
9

P
R
X

0-7

[input dig1tl

1
G

@176000/000002

0-7
LF

@200/000023 12

!I-

0-7
LF
CR
0-7

20
21
22
23
24
2!>

@1756:l0

10
12
13
14
15
16
17
18

VALID INPUTS
0-7

67-

IlIR5
@1<5/000U24

11-

@R5/000024 16

S
1

0-7
CR
0-7
CR

COMMENT

-------> proceed.
digit.
------->
-------> register designator.
-------> execute diagnost1c
-------> Doot from device
------->
anotner digit.
------->
examine loco
------->
n.
-------> goinputfromnewlocvalue.

-------> display next loco
------->
save data display next.
-------) save data go to prompt.

------->
loc go to prompt.
-------> close
1nput more digits.
-------) register number.
-------) PSw.

-------) examine.
input new value.
-------) close location.
-------) more digits input
-------) save value go to prompt

------->

KXTll-A2 1K FIRMWARE
MACRO V04.00
MACROOOT- bO AND PROCEEO

5-0CT-81 22:56:27 PAGE 35

.S~TTL

macrouUT- Go and Proceed

;;;;;;;;;;:;;;:;:1;;;;';;;;:;:;;:;;;',;;;;;;;;:;;;;;;;il

3
4

;;;;;;:;;;;;;;;;;;;;;;:;;;;:,,;;;:;;;;;;:;;;;;;;;;:;;; I;

!I
6

;; ;;
;; ;;

PHOCESS GU AND PROCEED OOT COMMANDS

;;;';;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;i; I';;;;;;;;;;;;;;

8
!i

10
11 171032
12
13
14
15 171036
16 171040
17
18
19
20
21
22 171044
23
24 171044
25 171050
26 171052
27 171054
28 171056
29 171060
30 171062
31
32

;;;;;;,:;;;;;;;:;;;;;:;;;;;:;;:;;:;:;;;;;:,;;;;;;;;;;; Ii

010067

176714

MOV

000005
005067

RESET
CLR

176710

;PUT SUPPLIED PC IN MEMORY LOCATION

SAVPS

;BUS IhITIALIZE
;CLEAR PSW

Entry p01nt tor tne Proceed command
F1rst, cheCK for val1d stack:
PCMD:
016600
005740
000240
103403
005740
000240
103004

000014

MOV
TST
Nap
Bes
TST
Nap

Bce

14(SP),RO
-(RO)
-(RO)

;User's staCK pointer
;wnere SAVPS will go (see below)
; (1n case of time out)
;No good. Timed out.
;where SAVPC w1ll gO

;Sufficient stack.

;

EITHER Stack no gOOd, so simulate a double bus trap without losing the
user's context as stored in the ODT stack.

33
34

35 171064
36
37 171072
38
39
40
41 171074
42 17107&
43 171100
44 171102
45 171104
46 171106
47
48 171110
49
50 171114
51 171120
52 171122
53 171126
54 171132
55 17113&
56 171140
57 171142

RO,SAVPC

Prepare the environment for the Go command

012767

000201

176702

1$:

MOV

000700

tR.STAK!R.NXM,ODTWHY
KBDQ

012600
012601
012602
012603
012604
012605
106427

000340

042716
011606
005167
016746
01674&
000006
000655
000657

000001

;Sneakyl (R.TYPE untouched; only the user image of it)
;Error prompt.

; OR

Stack i& UK, 50 restore user's context.

2$:

MOV
MOV
MOV
MOV
MOV
MOV

(SP)+,RO
(SP)+,Rl
(SP)+,i<2
(SP)+,RJ
(SP)+,R4
(SP)+,R5

RESTORE
ALL
OF
USER'S
GENERAL
REGIS'IERS

MTPS

#PRI7

Ble

.BlTO, (SP)
(SP),SP
IN.USR
SAVPS,-(SP)
SAVpe,-(SP)

No BREAKS allowed unt~l out of
ODT!
Odd stacks are too odd for T-11
RESTORE USER SP
Set user mode
RESTORE PC AND PS TO •••
••• STACK WHERE RIT WILL LOOK
RETURN TO USEHS PROGRAM
tlELP IN BR
HELP iN BR

17663&
17&622
176&14
HKBDQ:
HKBDS:

MOV
COM
MOV
MOV
RTT
BR
BR

KBDQ
IOlliS

KXTII-A2 lK FlkMWARE
MACRO V04.00
MACROODT-REGISTEk AND PS COMMAND
1
2
3
4
5
6
7
8

.SIlT'rL

0
I

w
00

ffiacroODT-Re~ister

and PS command

:;;;;;:;:;;;;,;;:;,;;;;;;;,;;;;;;;:;;;;;:;:;;;;;;;;;;;I;;

ii;;;;;;;;:;;;;;;;;;;;;:;;;;;;;;:;;;;:;:;;;;;;;;;;;;;;Ii;
;; ;;
; ; ;;
;; ;;

PROCESS ODT REGISTER COMMANDS

ii;:;;;;;;;;;;;;:;;;:;;;;;;;;;;:;;;;;;;;;;;;;:;;;;;;;:";
;;;;;;;; Ii;;;;;;;;;;;;;;;;; Ii;;;;;;;;;;;;;;;;;;;;; J;;;;;;

10
11
12
13 171144
14 171144
15 171152
16 17115b
17 1711 60
18 1711&4
19 171166
:./0 171172
21 1711"14
22 171200
23 171202
24 171204
25 171210
2&
27
28
29 171212
30 171212
31 171216
32 171,,22
33 171224
34 171230
35
36 171232
37 171234
38 171240
39 171244

5-0CT-81 22:56:27 PAGE 36

;

052767
004767
103246
1:./02:<17
001412
120227
001240
020027
101235
001013
012700
00041J

000200
000420

E,ntry point for Rx and RS commands

RCMD:
176576

BIS
CALL
sec
eMPI!
SEQ
CMPB
ShE
CMP
SHI
BNE
MuV
IlR

000123
000057
000007
167752

'KFLAG,ODTFLG
ONENUM
KIlDQ
R2,.'S
SWCMLl
1<2,,',
KBDw
RO,17
KBDQ
RCHDI
tSAVPC,kO
REGOIJT

;SET REGISTER FLAG
;GET REGISTER NUMSER
;A VALID eMD DID NOT FOI..I..OW
;IS IT THE RS?
;YES,BRANCH
;EXAMINE?
;NO,ERROR
;>71

;YES,ERROR
;IS IT EXACTLY SEVEN
HES,GET PC ADDRESS
;DISPI..AY

Status re\;llster (PS) selected:
SwCHD:
004767
120221
001224
012700
000403
006300
066700
0100&1
000402

CALL
CMPS
SNE
MOV
SR

GE'1CHR
R2,.',
KSDQ
tSAVPS,RU
Rt:(;OU1

;WHAT YOU WANT '10 DO wITH liS?
;EXAMINE?
;riO,ERRuR
;GET ADDRESS WHERt; PS IS
;GO AND DISPLAY

ASL
ADD
REGOU'I: MOV
BR

RO
RPOlhT,RO
RO,ODJ:l..uC
LOCDSP

SHIFT .'OR OFFSET It; MEMORY
GET EXACT ADDRESS OF REG.
STORE LOCA'fION

000272
000057
167754
RCMD1:

17b51&
176502

DIS~I..AY

KXT11-A2 lK FIRMwARE
MACRO V04.00
AND DEPOSIT

5-0CT-81 22:56:27 PAGE 37

HACROOuT-£XA~INE

V
I

.SBTTL macroODT-Examine and Deposit

2
3
4

;;;;i;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;i11i1;
;;;;;;;;;;;;;;;;;;;;;;1;;;;;;;;;;;;;;;;;;;;;;;1,;;;;1;I;;;;;

;;;;

1111

~~~~

; ; ; I

Ii
9

;;;i;;';;;;;;;;;;;;; Ii;;';;';;;;;;;;;;;;;;;;;;;;;;;;,;;;;; Ii

10
11
12
13
14
15
10
17 171240
18 171252
19 171254
20
21 171256
22 171260
23 171264
24 171270
25 171274
26 171300
27 171304
28 171306
29 171312
30 171314
31 171320
32 171322
33 171324
34 17133u
35
36 171332
37 171336
38 171340
39 171344
40
41
42
43
44
45 171346
46 171354
41 171356
48 171362
49 171366
50 171370
51
52
53

PROCESS ODT MEMORr AND

REGIST~R

EXAMINE/DEPOSIT

~~I;

; II ;

i1i;;;;;;;";;1;1;1;;;;;;;;;;;;;;;;;;;;;;;;;;;;;I;;;;; iii;;;

; ODTLOC points to re9ister or memory location
~ Following CALL GETNUM, if carry is clear, CR followed di9it.
~ ODTFLG: If register bit set indicates re91ster is being examined
~ENTRY

010067
011000
000240
103730
004767
112702
004767
004767
120227
001716
120227
103450
120227
103307
005000
004707
10300b
120227
001300
105767
100675

176474

FROM CMD ROUTINE AFTER LaC. VALUE IS GIVEN

LCSET: MOV
LOCDSP: MOV
NOP

RO,ODTLOC

~SAY~

(£(0) ,RO

;G~T DATA
~So next inst.

BCS
CALL
MOYS
CALL
CALL
CPlPB
SEQ
CMPS
SLO
CMPS
8HIS
CLR
CALL
BCC

HKBDQ
OCI'STR
#SPACE,k2
PUTCHR
GETCltR
H2,.CR
hKBD$
R2,"O

~CH

CMPS
SNE
TSTS
SMI

R2,'LF
I1K8DIol
DDTFLG
tlKBDQ

~Not

000372
000040
Ou0226
000210
000015
000060
000070
000262
000012
176404

R:t,"8
tlKBDQ
RO
GI!;TNUM

NEW LOCATION

~1f we
~Print
~PRINT
~Pr1nt
~GEf

does not execute
time out.
"1" If we timed out
IT
a space after the data

NEXT CHARACTER

~fIN!SH
~YES,CLOSE

LOCATION

~DEPOSIT1

,NO,CHECK LF
~MAYBEl
~HO,f'OHGET

;YES
~G~T

REST OF NUMSER
FOUND, STORE NEW

YALU~

CR, must be LF
error message
LF, cannot be register
~ (Error exit)
~Print
~If

T~SIT FILTER.
The T-blT can be set from the keyboard via ODT.
This can either be useful tor debUgg1ng or disastrous. So, you can
do 1t only if you first set FILT.l 1n O.CNTL (SIT 15).

022767
001021
042700
005707
100402
042700

167754

176372

1$:

177400
176404
000020
;2$:

CMP
BiliE
SIC
TST
SMI
SIC

'SAVPS,ODTLOC
3$
,AC<377>,RO
O.ChTL
2$

IT.SIT,kO

IAre we diddling the PS?
~No, we're not.
~PS is not a word.
,Is SIT 15 (FILT.f) SET?
~Yes, the filter's disabled
~KILL THE T-SIT
;Fall toru to Priority 7
~ Fllter

KXT11-A2 lK FIRMwARE
MACRO V04.00
MACROODT-EXAMINE AND DEPOSIT

.j:::..

1
2
3
4
5 171374
6 171400
7 171402
8 171404
9 171406
10 171412
11 111414
12 171420
13 171424
14 17143(;
15 171432
16
17 171434
18 171440
19 171442
20 171446
21 171450
22 171454
23 171460
24 171466
25 171472
26 171476
27 171502
28 171506

5-0CT-~1

22:56:27 PAGE 38

;Prior1ty-7 f1lter: unless FILT. 7 (BIT 7) in O.CNl'L 15 set, you cannot
;actually set the PS to pr1or1ty 7 us1ng OUT from the keyboard. Thls
;protects the ab1lity to break.
105767
100407
105700
100005
032700
001402
042700
010077
120227
001407
000643
120227
001237
105767
100634
112702
004767
062767
016700
004767
112702
004767
000661

176372

2$:

000100
000040
176322
000012

3S:

000012

4S:

176302
000015
000042
000002
176254
000160
000057
000014

5$:
176260

TST8
BMI
TSTB
BPL
BIT
BEQ
BIC
MOV
CMPB
BEQ
BR

O.C,nL
3$
1<0
3$
'BlT6, RO
3$
'BIT5,RO
RO,fI\ODTLOC
1\2, 'LE'
HJ<BDS

lOOt control word
;00 nothing-f1lter disabled
;Intended new PS
;00 nothlng-Prior1ty < 4
; Check again
;00 nothing-Priority < Ii
;LOwER THE BOOM
;STOR~ NEw VALUE
;Go on to next location?
;Sure, why not.
;GO TO PROMPT

CMPS
BNE
'Ut8
8MI
MOVS
CALL
ADD
MOV
CAuL
MOVB
,CALL
BR

R2,.LF
HK8UQ
ODTFLG
hK80Q
'CR,/<2
PUTChR
.2,00TLOC
OOTLOC,RO
OCTStl<
,'I,R2
purCnl<
LOCIlSP

;IS A LF ISSUED
;NO,ERROR
;15 REGIStER FLAG SET
;YES, LF NOT PERMITTED
;TO LINE UP CURSOR
;SENU IT
;GET ADDRESS OF NEXT LOC.
;GET NEXT ADDHESS VALUE •••
; ••• AND PklNt IT
;SEND A SLASH BEFORE •••
; ••• SHO~ING THE CO~TENTS •••
; ••• Of THE LOCATlON

KXTII-A2 lK fIRMWARE
MACRO V04.00
MACROODT-GET AND ECHO CHAKACTER

5-0CT-81 22:5b:27 PAGE 39
.SBTTL

macroOUl-Get and echo character

3
4
S
6
7
S
9

" " " """ " " " " " " " " "" " " " " " " "" " " " " " " " " " " " " " " " "" " "" " " " " " " "" " "
"""",""""""""""""",""",,,""","
"""
;;;;;;;;;;;:;;;;;;;;;:;;;;;;;;;;;;;;;:;:;;;;;;;;;;:;;;I;;;;;

,,,,

;;; ;
; ; ;;

CHARACTER INPUT AND ECHO SUBRUUTINE

,,,,

:;;;;;;;;;:;:;:;,;;;;;;;;;;;;;;;;;;:;:;;;;;;;;;;;;;;:;;;;:;:
;;;;;;;;;;;;;;;;;;;;;;;;;;; ;,;;;;;;;;;:;;;;;;;;;;;;;;;;;;;;;;

10
11
12

Get a character from the console keyboard and echo it baCK
; exactly as received including parity cits if any. Return with
; character in R2, eighth bit (and high byte) zero.

14
1~

GETCHk:

171!HO

16 17l~10
17171514
18 17151b
19 171522
20 171522
21 17152b
22 171530
23 171534
24 171540

105737
100375
113702

177560

105737
100375
110237
042702
000207

177564

177562

TST8
BPL
MOVB

URCSRSl
GETCHR
@#KBUfS1,R2

CHARACIEk READY?
BRANCH If NOT AND KEEP TRiiNG
TRANSfER CHARACTER

TSTB
l:lPL
MOVB
BIC
RETURN

fi\#XCSRSl
PUTCHR
R2,I!ifXBUfS1

PRINTER READY
NO, nu AGAIN
YES, XMIl' CHARACTER
CLEAR PARITY
CONTINUE

PUICHR:
177566
177600

.~C<l77>,R2

KXTII-A2 lK FIRMWARE
MACNO V04.00
MACROODT-TYPE ASCII STRING

5-0CT-81 22t56:27 PAGE 40
.S8TTL

2
3
4

macroODT-Type ASCII strinQ

;;1;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;'i",
;i;;;;;;i;;;;;;;;I;;;I;;;;;I;;;;;;;';;1;;;;;11;1;;I,;; ;;;;;,
; ; ;;
;;;;
;; ;;
;;;;
MESSAG~ PRINT SUBROUTINE
;;;;
; ; ; J
;;1,;',,;;;;;;;;;;;;;;;;;,;;;;;;;;;;;;;;,;;;;;;;;;;;;; I';;;;
;;;;1;;;;1;;1;;;;1;;;;;;;;;;1;;;;;;;;;;;;;;;',1;;1;;;;JlIi;'

5
6

7
8
9

10
; Print message starting w1th character pOinted to by RO and
; ending with first character w1th e1Qhth b1t set (th1s character
; 1s not pr1nted).

12
13
14
1~ 171542
16 171542
17 171544
1li 17154&
19 1715!>2
20
21
22
~3 171554
24 171554
~~ 1715&0
26
21
28
29 171564
30 171570
31 171574

PUTSTH:
112002
100413
004767
000773

MOV8
bMI
CALL
BR

177750

(NO)+,R2
DO"E
PUTCHR
PUTSTk

;GET ASCII CHAR
;15 IT THE END MARK?

;NO, PRINT IT
;MORE

;ENTRY FOR CARRIAGE RETURN
PUTCLF:
112702
004767

000015
177736

MOVS
CAI.L

'CH,R2
PU'rCHR

;PRINT CR
;FALL THkU AND PRINT LF

'LF,R2
PUTCHR

;PRINT Lf

; ENTHY ~ OR L~'
112702
004767
000207

000012
177726

PUTI.F:
DONE:

MOVB
CALL
RETURN

KXT11-A2 1K FIRM~ARE
MACRO V04.00
MACROODT-GET OCTAL DIGITS

5-0CT-b1

~2:56:27

.SBTTL

PAGE 41
macroODT-Get octal d1gits

3
4
5
&
7
8

;;;';;;',;;;';':1;;;;;';;;,;;;;;;;;;;;;;;;;;;;,,;;;;;;Ii ;;
;;;i;;;;';;;II;;;;I;I;;;;1;;;;;I;;;;;I;:;;;:,;;:;:;;;;;i Ii
I;;;
Ii
;; ;;
NUMERIC INPUT ROUTINE
n
;;; ;
; ;

;i;;";;;;;,;,;;";,;;;;;",,,;;;,;;;;;;;,,;,;;;;";;;;i
;;;;;;;;;;;,;;;;;;;;;;;,,;;;';;;;;;;";;;;;;;;;';;;;;;'i ;i

+:>.
w

10
11
12
13
14
15
16 17151&
11 111576
18 171&00
19 171600
20 171604
21 171610
22 171612
23 171612
24 171616
25 171622
26 171624
27 171626
28 111630
29 111632
30 171634
31
32 171636
33 171640
34
35 171642
36 171646
37 171050

On ex1t, RO contains the binary representat10n ot the number entered
If the carry Dit 1s clear, a <CR> followed number
If the carry blt 1s ~et, some other character followed the number,
possibly a command.
ONI:.NUM:
005000

CLR

1<0

;CLEAR ACCUMULATOR

CALL
C/oiPS
BEQ

GUCHR
R2,'CR
SRI::T

;GET DIGIT OR TERMINATOR
;CLEAR CARRY AND RETURN
;IF <CR> WAS TYPED

SUB
ADD
BCC
ASL
ASL
ASL
BIb
SR

"8,R2
,'8-'O,R2
NOeT
RO
RO
RO
£<2,RO
t<EXNUM

;CONVERT TO BIHARr •••
; ••• AND TEST IF OCTAL OR NOT
;NUT VALID DIGIT.
;MAKE ROOM FOR NEw DIGIT
;DITTO
;OITTO
;PUT IT IN PLACE
;GET NEXT

NEXNUM:
0047b7
120227
001412

177704
000015

162702
062702
103007
006300
006300
006300
050200
0007&1

000070
000010

G.,;TNUM:

000241
000207
062702
000261
000207

000060

SRET:

CLC
I<ETURN

NOel':

ADD
SEC
t<E'rURti

;CLEAR CARRr
;CON'rINUE
.'O,R2

RESTORE ASCII BECAUSE •••
••• POSSItlLE COMMAND
CONTINUE

KXTII-A2 lK FIRMwARE
MACRO V04.00 ~-OCT-al 22:56:27 PAGE 42
MACROODT-OCTSTR--TYPE 8IhARY IN RO AS ASCII
.S8TTL

2
3
4

macroODT-OCTSTR--type binary In RO as ASCII

; ; ; ; ; ; ; ; ; I ; ; ; ; ; ; ; ; ; , ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; I ; ; ; ; ; ; ; I ; ; ; _i ; ; ; ; ; ; ~ ; ; ; ;
;;;;;;;;;;;;;;;;;;;;;;;;; ;.,;;;;;;;;;;;;;;;;;;;; 1;;;;;;;',;; I
I;;;
; ;;;
, I I ,
;;;;
NUMER!C OUTPUT ROUTINE
,,,,
;;;;

....

6
7
8

;;;;;;;;;;;;;;;;;;;;;;;;I;;;;;;;;;I;;;;;;;;;;;;;;I!;;;iii;;;

iii;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;1;;

10
~ Prints, as a 6-diglt octal integer, the value of the binary
; number In RO.

12
13
14 171652

00471>7

15 171656
1& 171656
17 171660
111 171&64
19 1716&6
20 171670
21 171672
22 171670
23 171702
24 171704
25 17170&
26 171710
21 171712
28 171714
29 171716
30 171120
31 171722
32 171724
33 111126

010046
012746
005002
006100
00&102
062702
004767
00531&
001406
005002
006100
006102
006100
006102
000762
005726
012600
000207

177676
000006

0000&0
177.:.20

OCTSTO: CALL
OC'1'STR:
MOV
lo\QV
CLR
5$:
iWL
ROL
ADD
CALLo
DEC
SEQ
CLR
ROL
HOL
ROL
HOL
10$:

PUTCLF

;NEED CRLF AT ODT ENTRY

RO,-lSP)
,6,-(SP)
R2
RO
R2
i'O,£<2
PUTCHk
lSP)
10$
£<2
RO
R2
RO

SAVE VALUE
NO. OF CHAIlACTERS
OU'fPUT HOLD
SHIFT MS8 INTO 1.058

1\2

Sil

TST
MOV
RETURN

(SP)+
lSP)+,RO

"nnIlNIt

MAKE A DIGIT
OUTPUT A CHARACTER
CUUNT
DONE
NEXT
GET NEXT DIGIT INTO
R2
f'IRST TWO SITS
"n .. "" II ..
CONTINUE
CLEAR COUNT
ORIGlhAL VALUE

KXTll-A2 lK fIRMWARE
MACRO VU4.00
MACROODT-OUTPUr MESSAGES

5-0CT-~1

22:56:27
.SBTTL

PAG~

macroODT-Output messages

2
;;;;;;;;;;;;;;;;;;;;;;;;;;;;:;;:;;;;;;;;:;:;:;;;:;;;:;;;;;;:
ii;';;;;:;;;;;;;;:;;;;;;;;;;;;:;:;;;;;:;:;;;;;;;:;;;;; I;;;;;
;; ;;
; ;; ;

4
~

.................... ...

...

13 171731

14
15

,,,,

.. " .. " ............ " .......... " .. " .................................... """" ................ ,, ................ .
"",r"",.""",""""""""""""""""'"
"""
.. . " .............. " " . " .. " ............... " ...... "
"
" " ..... " """
" " " .... "
,"",,,,,",,,,,,,,,,,,",","",",,,",.,,,,"""

10
11

12 171730

,,,,

MI::SSAGES

,...
, , ,"

b
7
8

077
1115

012

100

MS<;Q:
foISGS:

.NLIST
.ASCII
.A~CII

BEX
'1'
<CR><Lf>'@'<200>

.I::VEN
.LIST

b~X

ERROR MESSAGE:
PIWMPT

KXTll-A2 lK fIRMWAR~
MACRO V04.00
DIAGNOSTICS-fOR SLU2 AND PPI

5-0CT-81 22:56:27 PAG£ 44
.SBI1L DIAGNOSTICS-tor SLU2 and PPI

1
2
j

:'i;':;;;;;;;;,;;;;;;",;;;;1;;;;;I;;;:':;I;;I;;;;I';1 Ii';;;

4
5
6

;;;;
~ ~ II

il1;;;;;;;;;;;';;;;11,;;;;;;,:,;;;;;;;;ll';;I;;;;;;,;;;1;;;;

Ii;;

OIAGI'IOSTIC MODULE

;;;;

; HI ""
;;;i;;;;;;;;;;;;;;:;;;;;;';;;;;I;;':;;;;;;,;;;;,;;;';;iiill;

8
9

;;;;;;:;;;;;:;;;;;;';;1;;;;;1;,;;;';;1;:;;;;;,;;;;;;;,",,;,

10
D1agnose PPI 1n mode 0 w1th loopback connectors 1nstalled.
D1agnose SLU2 1nternal c1rcu1try (ma1ntenance mode) and
SLU2 drivers/rece1vers (with external loopback connector).

12
13
14

15
16
17 171736
18 111740
19 171742
20
21
22
23
:.14 111142
25 171744
26 171746
27 1717:)0
28

List of error b1t definitions to return to user.
.wORD
.WORD

000100
000010

ERRBlT:
; List of masks to put 1n XCSR$2. Perform internal 100pbaCk
; test f1rst, then external loopback test.
.WORD
.WORD
.WORD

000000
000002
000006

300 baud
300 baud and ma1ntenance

; L1st of pattern oytes to loop around.
; All bits on, alternating b1ts, all bits off.
; 1II0te: last byte must be O.

377

252

000

35
36

PATERN: .BYTE
• EVl::N

377, 252, 0

.ENA8L

LSB

MO'i
MOV

#MOD",UPP.CWR
'LE:DOFF,i#PP.CwR

CLR

DIAGIIIO:

37 1717S4

38 171754
39 171762
40

XC.PBE
XC.rBE ! XC.MNT

INns:

30
31
32

33 171150

E.t;XT
E.IIIIT

012737
012737

000221
000011

176206
176206

set proper PPI mode- LED
must 1mmed1ately be turned
off as a consequence.

42 171770
43
44
45
46 171772
47 171174

005000

assume success

Perform parallel port d1agnost1c
005001
000405

CLR
8R

Rl
AROUN2

;

Rl = loop pattern
SKIP OVER THE ENTRY POINT

KXTll-A2 lK FIRMwARE
HARDwARE ENTRY POINT

MACRO V04.00

5-0CT-81 22:56:27 PAGE 45
.SBTTL HARUwARI:; ENTRY POINT

1
2

4 172000
~ 172000
6 172004
7 172004

.=172000

172000
START::
000167

176254

000107

176026

JMP

PwRSUP

JMP

k. SIRT

RESTAR::

KXTll-A2 1K FIRMWARE
DIAGNostICS-CONTINUED
1
2 172010
3 172010
4 172014
5 172020
6 17:.l022
7 172026

MACRO V04.00

!I-OCT-81 22:56:27 PAGE 46
.SBTTL DIAGNOSTICS-Continued
AR(JUN2:

110137
123701
001402
052700
017110

176202
176200

1$:

000001
2$:

MOVB
CMPB
BI::Q
BIS
SOB

R1, UPP.B
i.PP.A, Rl
2$
fE.PAR, RO
IU, 1$

send 1t out port B
check 1nput 1n port A
branch 1£ same
else set error flag
loop for all values

6
9
10

0
I

..J:>.

11 172030
12 172034
13 172040
14 172044
15 172050
16 172054
17 172056
18 172060
19 172064
20 172070
21 172072
22 172076
23 172100
24 172102
25
20 172104
27 172110
28 172112
29 172114
30 172110
31 172120
32
33 172122
34 172126
]!I 172130
30 172132
37 172134
38 17:.!130
39 172140
40 172146
41
42 172150
43 172152
44 17 2154
4~ 1721&0
46

Perform SI..U 2 d1agnost1c
012702
012701
016146
012704
014461
001430
00!:i742
01271b
012703
005005
105761
100402
077504
000422

171742
176540
000002
171750
000004

MOV
MOV
MOV
MOV
3S:

000010
1717!:i0

4$:

000004

5$:
6$:

111301
005005
105711
100402
077!103
000413

000006

7$:

120113
001010
105723
001356
005316
001744
002701
000740

000002

051200
005726
004707
000107

8S:

MOV

'ERRsn, R2
'I<CSR$2, Kl
-(SP)
UNITS, H4
-(1<4), 4(1<1)

BEQ
TST
MOV
MOV
CLR
ISIS
BMI
SOB
BI<

-(1<2)
.8., (SP)
'PATERN, .R3
R5
4(R1)
7$
1<5, oS
10$

MOVS
CLR
TSTS
BMI
SOB

(R3), b(lH)
R5
(R1)
9$
1<5, 8$
10$

DraneI'! 1f ready
else Dump t1meout counter
branch 1f timeout

CMPS
StiE
TSIB
BtiE
DEC
BEQ
ADD
BI<

2(R1), (R3)
10$
(R3)+
!IS
(SP)
3$
flO, 4(1<1)

come back OK?
no, set error bit & ex1t
done all bit patterns?
no
ye5, done all bauds?
yes
no, to next baud rate

8IS
TST
CALL
JMP
.DSABL

(R2),1<0
(SP)+
OCTSTO
KBD$
LSS

ilR

000010

9$:

000004
10$:
11$:

177472
170516

:diU),

11$

R2->error flags
R1-> SLU2
Ignore garbage, make temp
R4->1n1tial XCSR value
inlt XCSR
brancl'! 1f done
R2->next error tlag
(SP)=baud rate counter
R3->patterns
1n1t t1meout counter
loop pattern around
branCI'! 1t ready
else bump t1meout counter
brancl'! 1f t1meout
1n1t1a11ze t1meout counter

set error blt
r1d of temp
pr1nt error flags
and just get out.

KXTII-A2 lK fIRMwARE
BOOTS-DESCRIPTION

MACRO V04.00

5-0Cr-~1

22:56:27 PAGE 47
.SBTTL BOOTS-Description

,;;;;;;;,,;;;;;;;;;;;;;,;;;;;;;,;;;;,; Ii;;;;;;;;;;;;;;;;;;;;
II Ii;;;; I,;;;';i;;;; li;;:i;;;i;;;;;;,;;;;;;;;i;;;;; I;;;;;;;;
Ii;;
ii;;
;; ;;
;; ;;
BOOTSTRAP ~ODULE
;;;;
;;;;
i;i;;;;;;;;:;;;;I;;;;;;;;:;;;;;;;;;;;;I;;;;;;;;;;;;;;; iii;;;

;;;;;;;;;;;;;:,:;;;;;;;;;;;;;;;;;;;;;:;;:;;;;;;;;;;;;;I;;;;;

4
5

6
7

10
11

000000

.REPT

1J
14
15
1b
17
18
19
20

This Is a short bootstrap program designed to handle floppy disks or TU58
tape cassettes In either our standard boot able format or in the stand-alone
volume format (RT-I! ".SAV"-structured files).
The bootstrap sequence is as follows;
1.

Since entry is etfected by typing D in response to OOT prompt, get next
character (0, X or ~). Get optional device number next (default is 0).

If floppy boot Is selected;

22
23

24
25
26

Attempt to read 512 bytes from specified unit of the floppy
disk, starting trom logical blOCk zero, into memory locations
star tiny at 0 at the densIty of the medium present In the
drIve at the tIme.

If tne drive is not ready or does not contain a bootable
medium, gO oack to OOT.

28
29
30
31
32
33

If TU58 boot is selected, read the first block from the selected
drive into locations starting at O.

If the first byte read into RAM is 240 octal, jump to it. If tne
first byte is 2bO octal, execute the stand-alone volume loader,
using the selected device as input.

36
31
38
39

.ENOR

KXTII-A2 lK FIRMwARE
BOOTS-DESCRIPTION
1
2
3
4
5
6
7

MACRO V04.00

5-0CT-81 22:50:27 PAGE 4ij
l;i;;;;;;;;;II;;;:1;;;;;;;;;;;;;;;;;;;;;I;I;;;;;;;I;;; I;;;;;

iii;;;;;;;;;;;,;;;;;;;;;;;;;;;;;;;;;;;,;;;;;;,;,;;;;;;iii;;;
I;;;
;;;;
;;;;
;;i1i;;;;;;I;;;;;:;;;;;;;I:;;;;;;;;;;;;;;;;;;;;;;;;;;; I;;;;;
; li;;;;;;;;;;;;;;;;;;;;;;;i;;;;;;;;;; ii;;;;i;I;;;;I; li;;;i;;

ii;;
I; ; ;
; ; fi

~QUATES

USED ONLY BY BOOTSTRAPS

9
10

.S8TTL BOOTS-RX Controller Definitions
, RX01/kX02 (RXV11,RXV21) Reg1ster Def1n1t1ons

12
13
14
1::'
16
17
18
19
20
21
22

tI
I
VI

23
24
2!>
26
27
28
29
30
31
32
33
34

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57

177170
177172

RXCS=
RXD8=

177170
RXC:H2

;Control and Status
;Data Buffer

; RX Control and Status B1ts
100000
040000
030000
004000
003000
000400
000200
000100
000040
000020
000016
000001

RXSSER= 100000
RXUIN= 040000
RXUXA= 030000
kXSS02= 0040(}O
RXSSXX= 003000
RXSSDEz: 000400
RX$$Tk= 000200
RX$$U= 000100
RXSSDN= 000040
RXSSUN= 000020
kXS$FIII= 00001b
RXSSGO= 000001

;Error
;In1t1al1ze controller
;Extended address b1ts
;1 1t RX02; a 1f RXOl
;Unused b1ts
;Density (1=double,0=single)
;Transfer function
;Interrupt enable
;Done
,Unit select
;function select
;GO

; RX Function Codes (in RXSSFN) with GO bit preset
000001
00U003
00000::'
000007
000011
000013
000015
000017

RXSfIL= 0*2+RX$$GO
RX$EMF= 1*2+RX$$GO
kXSWRT= 2*2+RX$SGO
kXSkEU= 3*2+RX$$GO
RX$STD= 4*2+RX$SGO
RX$Rsr= ::'*2+RX$$GO
RX$wOD= 6*2+kXSSGO
RXSk~C= 7*2+RX$$GO

;Fill Duffer
JEmpty buffer
;write sector
JRead sector
;Set media density
;kead status
;write sector with deleted data
;~edd error code

; RX Error Codes
000400
000200
000100
000040
000020
000004
000001

RXf;SUN= 000400
kXESUk= 000200
RXE;$DO= 000100
RXI::$vN= 000040
RXESDE= 000020
RXIo.SID= 0000114
RXESCR= 000001

;Unit selected
JDrive ready
;Oeleted data
;Drive density
;Density error
;Initialize done
;CRC error

; Miscellaneous Definitions
000010

RETRY=

;Number of retries

.S8TfL ijOOTS-IU58 Definitions and Protocol Equates

KXTI1-A2 1K FIRMwARE
MACRO V04.00 5-0CT-81 22:56:21
BOUTS-TU58 DEFl~IT10NS AND PROTOCOL EQUATES
58
59
60
61
62
63
64
65
66
b1
68
b9
10
71
72
73

0
I

Vl
......

48-1

; Absolute address aefinitions
000002

FILNAM

= 000002

001000

DIRBUF

= 001000

Address of RAD50 filename for
stdna-alone program loading
Start of 512. word buffer used
for RX-l1 directory operations
in stand-alone loading

; TU58 Address definit10ns
176540
176542
176544
17b546

= RCSRS2
= KBUF$2
TO$CSk = XCSRS"
TISCSR
Tl$B~R

TOSBFk

" lIBUF62

;DL receiver control and status
;OL receiver data buffer
;DL transmitter control and status
;DL transmitter data bufter

TU58 Radial Serial Protocol codes

75
76
17
78
19
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
lOb
101
108
109
110
111
112
113
114

PAG~

Flag Byte Definitions:
000001
000002
000004
000020
000023

RUDAT
R$$CTL
R$$lhT
RSSCUN
RUXOf

= AB<OOOOl>

= AB<00010>
= AB<OOlOO>
= AB<10000>

= AS<10011>

;Data message flag
;Control messaye flag
;Ini tial1ze flag
;Continue 11ag
;XOFF

; Control pacKet operation codes:
000000
000001
000002
000003
000004
000005
000006
000001
000010
000011
000012
000013
00010U

RSNOP
R$INIT
RSRE-AD

= o.

= 1.

= 2.

= J.
RSCOMP = 4.
R$1WIH T

KSPO:;l
R$ABRT
RSDlAG
RSGElS
kS5ETS
RSGElC
RSSETC
RSEND

= 5.

= 6.
= 7.

= 8.
= 9.
= 10.

= 11.

= AB<OlOOOOUO>

;No-operation
;lnitiallze
;Read operation
;write operation
;Compare (NOP on TU58)
;Position operation
;Abort (NOP on TU5S)
;Dlagnose
;Get status
;Set status (Nap on TU58)
;Get cnaracteristics
;Set cnaracteristics (NOP on TU58)
;*END lIIessage

; END packet success coaes:
000000
000001
171776
177770
177767
177765
177757
177740
177737
177720
177711

SSNORM
SSkETR
SSPAR'I
SS ut'il T
SSCAR'I
ShPf<T
SSDCHK
S$SEEK
S$M01'"
I)SOPCD
SSRECN

= o.

= 1.
= -2.
= -8.

= -9.
'= -11.
= -17.

= -32.

= -33.
= -48.

" -55.

;Normal success
;Success but witn retries
;Partial operation (end of medium)
;Invalid unit number
;No cartridge
;Cartridge write protectea
;Data Check error
;SeeK error (block not found)
;Motor stopped
;lnvalid operation code
;Invalia record nUlllber

.SBXTL BOOTS-RTll Detinitions and Equates

KXTII-A2 lK FIRMWARE
MACRO V04.00
BOOTS-RT11 DEFINITIONS AND EQUATES
115
116

5-0CT-81 22:56:27 PAGE 48-2

; kT-l1 Directory Structure Definit10ns

117
118
119

120
121
122
123
124
125
126
127
128
129

001000
001002
001004
001006
001010
000016
000010
000400
001000
002000
004000

SE:GALO
NXTSEG
HIiHSEG
XTRflXT
STR8LK

:: DIRBUF
:: DIR8UF+2
:: DIkBUF'+4
:: j)IRBU~'+6
:: DIRBUF+I0

~NTSIZ

:: 7*2
:: 10
= 000400
= 001000
= 002000
= 004000

D.HEti

Tl:.NTA$
I:.MPTY$
PERMf"$
E:NDSGS

;Number of segments allocated
;Number of next log1cal segment
;H1ghest segment in use
;Number of extra bytes per entry
;Starting block. for f1les
• 1n thiS segment
;Size of a directory entry
;Offset to f1le length 1n entry
;Flag for tentative file entry
;Flag for empty area entry
;flag for permanent f1le
;Flag for end of segment

130

131
132
133
134
135
136
137
138
139
140
141
142

; RT-11 System Communications Area Defin1t1ons
000040
000042
000044
000046
000050
000052
000053
0000S4
000056
000057

R'l:SSTA
kT$lSP
RUJSW
RT$USR
RTSHGH
RTSEMT
RT$uER
RTSRMN
R1'$FCH
RTSfCT

= 000040

= 000042
= 000044
= 000046
= 000050

= 000052
000053
:: 000054
:: 000056
:: 000057

;Start address for program
;Initial stack pointer
iJob status word
;USR load address
;JOb h1gh memory limit
;(~yte) EMT error code
;(Byte) User error code
;Base address of res1dent monitor
;(Byte) Console fill Character
;(Byte) Console fill count

KXT11-A2 1K fIRMWARE
MACRO Y04.00
BOOTS-PROGRAM ENTRt POINT

5-0CT-81 22:5b:27

PAG~

.SBTTL BOOTS-Program entry polnt

2
3

i;;;;i;;;;;;;;;III,;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;I;iiI;;;
11;;i;;;;;;;;I;I;I;;;;;;;I;;;;;;;;;;;;;;;I;;;;;;I;I;I; I;;;;;
;; ;;
; ;;;

4
~

I;;;

6
7
8
9

;;;;

BOOTSTRAP INITIALIZAtION AND COMMAND

INTERPR~TER

I;;;

,,,,

;i;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;:;;;;;;;;;;;;;;;;;;iii;;;
;;;;;;;;;;;;;;;;;;;;;:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;

10
A '0' was entered ln response to the ODT prompt, so we get
here and expect 'D','X' or 't' next, followed by a CR or a
unit number. we set b1ts up 1n ~.CNTL as tollows;

12
13
14
15
16
17
18
19
20
21
22
23
24
25 172164
26 172164
27
28
29
)0 172172
31 172172
32
33 172171>
34 112200
35 172204

36 172210
37 172212
38 172211>
39 172222
40 172224
41 172230
42 172132
43
44 172231>
45 172242
46 172241>
47 172250
48 172254
49 172256
50 172260
51 172262
52
53 172261>
54 172270
55 17,2274
56 172300
57

SIT

SIt

7: 0 = TU58
1 = I<XOI/D:l
Used by stand-alone volume loader to select proper
read routine.
0: Device number

hotel if no memory was found at 000000, b1t 15 of B.CNTL,
called "NO.LOW" will be set and the bootstraps w1ll be
d1sabled.
BOOTS:I
012737

000072

176544

MOV

'TUBAUD,~#TO$CSR

;Set TU5S Baud Rate

; Jump here with 001 if booting russ's at other than default baud rate
Sl'TUI;D; ;
010667
005004
004767
120227
001412
012704
020227
001405
020227
001402
004767
022702
001410
162702
001405
005302
001402
005204
1104&7
0057&7
100002

175566

MOV

SP,IN.USR

CLR
CALL
CMPB
BEQ
/oIOV

1<4

177304
000104
000200
000130

C~P

BEQ
CMP
BEQ
ABORT

000131

177246
000015

1$:

00001>0

175474
175470

2S;
3$:

GETCHR
R2,#'P
1$

#DEVBl'I,R4
R2,.'X
1$

R2,#'l'
1$

;Perm1t HALTs and BREAKS
; by making IN.USR non-zero
;Assemole new B.CNTL here
;Keyboard character 1n R2
;00 = TU~S cassette
,R4 is clear for DO
;R4 bit 7 15 set for OX, Dt
;DX
RX01 or RX02
;DX
RXUl or RXU2, the code's
the same- it knows ooth dens1ties, DMA, non-DMA

=
=

CALL
CMP
BEQ
SUS
BEU
DEC
BEQ
ABURT

GI::TCHR
115,1<2

INC
MOVS
TS1'
SPL

R4
R4,S.CNlL
tI.CNTL
4$

"0,1<2
3$

R2
2$
<Illegal unit number>

;Get device number or CR
;Is i t CR1

;CR means drive 0
;Drive 01
IYuP.
;Drive 11
;l'es, skip the ABORT
for un1t 1.
set device, unlt information.
Test NO. LOW
we have low memory
we don't, so go to UDl

KXT11-A2 1K FlRMwARE
MACRO V04.uO 5-0CT-81 22:56:27 PAGE 49-1
-----> HALT AT PC=172264 INDICATES "ILLEGAL U~IT NUMdEk"
58
59
60
61
62
63
b4
65
66
67
68
69
70
71
72

172302

ABORT

Before proceeding, we set up the bus timeout trap vector, enable
trap to 4 emulation and reset the bus.
we dO a delay (see
explanation below) and set up the stack so the stand-alone booter and
device primary bootstraps can get the information they need passed
to tnem in kO and k1 (see CHK240, below).
172306
172314
172322

012737
012737
000005

172370
000300

000004
000006

4$:

92 1 "/237'<

.BADBOT,~f4

,PIU6,Ub

JIf we time out, we want to reJinitialize everything.
JFor now, inlt. the bus.

Note: the previous instruction also screws up some devices
whlcn perform a long initialization sequence, such as RXu2's,
wnich do an automatic boot from drive O. The long delay below
Is necessary In order to assure drive 1 is ready if a boot
1s desired trom it.

74
75
76 172324
71 172336
78 172342
79
80 17234b
81
82 172352
83 172354
84 172360
85
86 172362
87 172364
88 172366
89
90 172370
91 172370

HOV
HOV
RESET

012706
010bb7

167644
175430

DELAY
1010°1'

MOV

kO,R1,9.
fSSTACK,SP
SP,TRAP4

012716

037716

MOV

'31776, (SP)

010402
042702
01024b

MUV
BIC
HUV

R4,R2

177176

R2,-(IjP)

;Delay 2 seconds
;Initialize the stack.
;Set up trap-to-4 emulation
;by maKing TRAP4 non-zero
;Some boots need a memory-top
; address here, so 8k will do
;Boot control word here
;Want only unit no. in R2
;And we'll save it too.

TSTB
BMI
BR

R4
ilXBOOT
rUSOOl

JBit 7 set for RX01/02
;Go to floppy boot
;Go to TUS8 boot

MOV
ABORT

'$$TACK,SP
;Restore the stack
<Unexpected timeout during boot>

10!i704
100405
00043b

.ftC<DE.~~UH>,R2

BADBOT:
012706

167644

KXT11-A2 1K FIRMWARE
MACRO V04.00
BOOIS-RX01/RX02 BOOTSTRAP

5-0CT-81 22:56:27 PAGE 50
.SBTIL BOOIS-RX01/RX02 Bootstrap

2
ii;:;;:;:;;:;:;;;;;;;;;:;,;:;:;;;,;;:;:;:;:;;;;;;,;;;;Ii;;;;

3
4

ii;;;;;:;;;;;;;;;:;;;;;;;;;;;;;;;;:;;;;;;;:;;;:;:;;;;;iii;;;
; ; ; ;
; ; ; ;

,,,,
,, ,,

8
9

i;;;;;;:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;:;;;; iii;;;
i:;;;:;:;;;;:;;;:;;;;;;;;;:;;:;;;;;;;;;;;;;:I:;;;;;;;;iii'i:

10
11
12
13
14
15
16
17
18
19
20
21

t:i
I
Vl
Vl

FLOPPY BUOTSTRAP

,,,,

; Ihis routine w1ll bootstrap either floppy drive, at the density of the
; media mounted 1n that drive.
172400
172400
172404
172410
172412
172416
172420
172422

RXBOOT:
01274&
005737
000240
012701

177170
177170
001000

OO~ooO

005004
0047&7

000402

MOV
lSI
"OP
MOV
CLR
CLR
CALL

.RXCS,-(SP)
iHRXCS
'512.,R1

RO
R4
DREAD

;Need floppy CSR tor CHK240
;1£ not there, time out via 4
Ito ST173 and reset the worla
;Byte count
;Starting bloCK number
;RAM buffer address
000000
;LOAD IT ALL IN

KXT11-A2 lK FIRMWARE
aODTS-DISTINGUISHING

MACRO V04.00 5-0CT-ij1 22:56:27 PAGE 51
OF BDOT BLOCK

TIP~

.SBTTL BOOTS-Distinguishing type of boot blocK

1
2
3

;,; Ii;;;; Ii;:;;;;;;;;;;;;;;;;;;;;;;;;;;;:;;;;;;;;;;;;;;;;;;;

4
5
6
7

;;;;;;;;;;;;;;;;;;;;;;;:;;;;;;;;;;;;;:;;:;:;;;;;;;:;;; iii;;;
; ; ;;

,,,,
,,,,

8
9

t:J
I
VI

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

DISTINGUISH STANDARD FROM

STAND-ALO~E

fROM

,,,,

; ;;;
,,,,
Nuh-~OOTABLE VOLUMES.
; ;;;
;;;;
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; I;;;;;;;;;;;;;;;;;;;;;;;;;;; I;;;;;;i;;;;;;;;
;;;;;;;;;;;:;;;;;;;1;:;1;;;;;;;;;;;;;;;;;;:;;;;;;;;;;;il;;;:

The CHK240 routine will repeat powerup sequence If location 0 does not
contain a valid secondary Dootstrap (i.e., does not nave a 240 or 260
in it).
It starts execution of tne booted program if tnere's a 240,
and goes to tne stand-alone program loader if there's a 260.
CHK240:

172426
172426
172434
172436
172444
172446
172452

022737
00141 0
022737
001447
004767

172456
172460
172462

012601
012600
OO!)O07

000240

000000

000260

000000

1757b6

CMP
BEY
CMP

'240,HO
1$

SEQ

STANDB

CALL
ABORT
1$:

MOV
MOV
CLR

;Did we read a valid bootstrap1

'260,~#0

;Stand-alone volumes start with 260
V~CSE.T
;kestore wiped-out vectors
<NO DoOt blocK on volume>
(SP)+,IU
(SP)+,RO

Unit CSR address
unit number
Standard secondary boots

KXTII-A2 lK FIRMWARE
800TS-TU58 800TSTRAP

MACRO Y04.00

5-0CT-81 22:56:27 PAGE 52
.S8TTL BOOTS-TU5S Bootstrap

2
3

,;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;:;;:;;;;;;;;; iii;;;
:li;;;;;;;;;;;;I;I;;;;;;;;;;;;;;;I;;;;;;;;;;;;;;;;:;;; iii;;;
;; ;;
;; ;;
;; ;;
; ;;;
TU58 TA~E CASSETTE BOOTSTRAP
,; ; ;
; ; ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;, I;;;;;;;;; I;;;;;;;;;;;;;;;;;;i;;
ii;;;;;;;;;;;;;:;;;;;;;;I;;;;;I;;;;I;;:;I;;;;;;;;;;;,;iii;;;

4
5
6

7
8
9

10
11

12 172464
13 112464
14 1724111
15 172414
lEi 172476
17 172500
18 172504
19 172506
20 172510
21 17:.l514
22 172516
23 112520
24 172522
25 17<:524
26 172::'30
27 172532
28 172536
29 172540
30

.ENABL

LSB

MOY
MOY
eLR
INC
CALL
TSTS
BPL
BIC
MOY

1T1$CSR,-(SP)
iTOSCSR,Rl
R3
ilRl
CHtiOUT
ilkl

.SnE

RSSlNT,RS$lNT
fiiR5

TU800T:
012746
012701
005003
005211
004767
105711
100376
042711
012703
004
004715
005741
105737
100375
121127
001402

176540
1765,,4
001132
lS:

000001
004
176540

2$:

000020

CALL
TSI'
TST8
BPL
CMF8
IlEO

ABORT
;

34 172546
35 172552
36 172556
37 172560
38

0050uO
012701
004767
100323

3$:

001000
000212

IXC.HRK,IllR1
(~CH,R3

eLR
p.;OV
CALL
BPL
A8URT
.DSABL

~Rl

;And transm1t them
;Dump any garbage char in TISBUF
;15 character ava1lable from the TU58?
;It PL, no - walt 1n loop
; I f so, was i t a CONTINUE fla\l?
3$
;It EO, yes- go anead
<'fU5t1 initial1zat1on error>
-(1'<1)

IH'llSeSR
2S
i\Rl, fRSSCON

lU58 is now 1nlt1al1zed.

32
33 172544

wants TU5& CSR
-> output CSR for TU58 serial line
~Set R3
0 (Two NULLS)
~Start transmitting 8R~AK to lU58
~Send eight NULLS
;Is transmitter ready agaln yet?
;It PL no - wait
;Else stop sending 8REAK now
;Get two INIT commands for lU::'8
~CHK240

Prepare to read blOCK .0.

1(0
;!lloCk number
0
'512.,1'<1
;Byte count
one blOCK
READZU
;Attempt to read the blOCK
ChK240
; I f PL, read was successful
<TU5ij block 0 read error>
LSB

KXTll-A2 lK fIRMWARE
MACRO V04.00
BOOTS-STANO-ALONE VOLU~E BOOTSTRAP

5-0CT~81

22:56:27 PAGE 53

.S~TIL

SOOIS-Stand-alone volume bootstrap

;;;;;;;;;;;;,';;;;;11;;;;;;;;;;;;;;;;;;;;1;;;;;;;;;;;; I;;;;;

3
4

;,;,;;;;;;;;;;;1;;;;;;;1;;;;1;;;;;',;;;;;;;;;;;;;;;;;;iii;;;

ii';

; ; ; I

Ii;;

STAND-ALaNE-VOLUME BOOTSTRAP

,....
, ,,

;;;

;;;:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;,;;;;;;;;;; iliii;

9
10

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;',;;;';;;;;;;;;;1;;;;iii;;;

This routine loads stand-alone programs (assumed to be in RT-11 .SAV
; f1le format) from an RT-ll file structured TU58 cartridge.
It 15
; invoked if the f1rst word in block 0 of the cartridge is a 2&0.

12
13
14
15 172564
16 1725&4
17 172570
18 172572
19
20 172574
21 172600
22 172604
23 172&10
24 172612
25 172616
26
27 172622
28 172624
29 172626
30 172632
31 172634
32
33 172&40
34 172642
35 17264&
36 172650
37
38 172654
39 172660
40 112662
41 172664
42 172666
43 172670
44 172672
45
46 172674
47 172676
48 172702
49 172704
50 172706
51 172712

STANDS:
012700
006300
022020

000001

012701
012704
004767
10U002

002000
001000
000162

012704

001010

1$:

2$:

MOv
ASL
C,",P

U,RO
RO
(ROH,(RO)+

MOV
MOV
CALL
BPL
ABORT
MOV

111024. ,Rl
'DIR8Ut',R4
READU
2$
<Directory read error>
'STRbLK,R4

MOV
MOV

(R4H,RU
R4,R3
,PERMfS,(R4)+

01240U
010403
032724
001010
022744

002000

BIT
SNE
CliP

004000

001015
013700
001350

001002

SHE
MOV

5$
UNXTSEG,RO

012705
022425
001004
022425
0010.02
022425
001410
010304
062704
062400
022424
063704
000744

3$:

000002

000010
001006

IENDSGS,-(R4)

~NI::

ABOR"r

(File not found>

4$:

MOV
CMP
SNE
CliP
SNE
CMP
BEQ

'fILNAM,R5
(R4H, (R5H
5$
(R4)+, (R5)+
58
(R4H, (RS)+
LOALl

5$:

MOV
ADO
ADD
CMP
ADD
BR

R3,R4
iD.FLI::N,R4
(R4)+,KO
(R4H, (R4)+
UXTRBYT,R4
J$

;Set directory segment .1
;Two blocks per segment
;Add 4 to RO, as directory starts
; in block.&
;Prepare to read two blOCKS
;Into the directory buffer
;Read the segment
;If PL, read was successful
;Else prepare to p1ck up
; starting blOCK
IRO = starting block for files
;Save pointer to current entry
;15 th1s a permanent file?
;If bit set, yes - check if 1t matches
;Else 1s this the end-of-segment
; marker?
;If NE, no - go SKip this entry
;Else get numDer of next segment
;If HE, there is one - go read it
;Point to RAD50 name of desired file
;Check tile name, first word
11f hE not deSired file
; ••• ChecK second word of f1lename
;if NE not desired one
; ••• Finally, check extension
;If ~Q, got it - go load this
lone tnto memory
;Get entry pointer back
;Advance to file s1ze of entry
;Update current file base
;And Skip to next file entry
;Plus any extra bytes in each entry
;Continue file searcn

KXT11-A2 1K FIRMWARE
MACRO V04.00
BOOTS-LOAD STAND-ALONE PROGRAM FILE
1
2
3 172714
4 172711>
5 172720
6 172722
7 172726
8 172730
9 172734
10 172740
11 172744
12 17274b
1l
14 172752
15 172752
16 172754
17 172756
18 17:l762
19 17~71>6
20
21 172770
22 17~770
23 172772
24 11').776

t:l
I

5-0C'r-81 22:56:27 PAGE 54
.SB'1'11. tlOOTS-Load Stand-Alone Program F1le

011401
000101
006101
004767
100002
013705
032705
001402

LUAlI:
000042
000040
000001

lS:

f!lR4,R1
R1
R1
Rt:;ADZU

MOV
SWAB
ASL
CALL
BPI.
ABORT
MOV
SIT
aECol
ABORT

;Rl
s1ze of f1le 1n blockS
; • 256.
word count
; • 2
byte count
;Read tne program f1le 1nto memory
1$
; i t Ill, error 1n read-ABORt
<Stand-alone tHe read error>
URT$STA,RS
;Get program start adrs
f1 ,R5
lIs adrs even?
STARl'$
;If EQ yes - okay
<lllegal transfer address>

MOY
MOVS
MaY
CLR
JIIP

(SP)+,Rl
(SP)+,RO
\!I'RT$lSP,SP
THAP4
li!R5

Pass the CSR address
Get unit number booted
Load program's stack pointer
D1sable trap to 4 feature
Go start program execut10n

CLR
MOV
BR

R4
4(SP),R2
AROUNl

Load at 0
Get un1t number
SKIP OVER TriE ENTRY POINT

STARTS:
012601
112600
013706
00501>7
000115

000042
175010
REAlIZU:

005004
0161>02
000407

000004

READU:

KXT11-A2 1K FIRMWARE
173000G ENTRl POINT

MACRO V04.00

5-UCI-Bl

2~:56:27

PAGE 5!)

.SBTTL 173000G ENTRY POINT

2
3
4 173000
!) 173000
I> 1"1300"
7 173006
8 173010
9
10 173012

9
0\
o

.=173000

173000
1>1'173::
10b427

000340

OOOOO!>
005000
077001
0001b7

175242

MTPS

.PRI7

RESET
CLK
SOB

JMP

PI>RSIiP

RV, •

can't assume anything here.
But PWRSUP usually does.
DELAY tor the saKe of VLART.
(Maint. bit cleared by R~SET
just a little too long).

KXT11-A2 1K FIRMwARE
BOO'fS-COt'4'f INUED

MACRO V04.00

5-0CT-&1 22:56:27 PAGE 56
.SBTIL dUOrS-Continued

2 173010
;; 1730lb
4 173022
~ 173024

U
I

AROUN3:
105767

174746

10040~

000167

000370

TSTB
BMI
JMP

B.CNTL
DktAD
TRtAU

;Bit 7 set tor RX01/RX02
;Read from tape

KXTII-AZ lK FIkMwARE
MACRO Y04.00
BOOTS-RX01/RX02 kEAD ROUTINES
1
2
3
4
5
6
1
8
9
10
11
12
13
14
15
16
17
18
19
20
21 173030
22 173032
23 173034
24

0I
0\
tv

22:56:27 PAGE 57
.SBTTL aOOTS-RX01/RX02 Read routines

;;;;;;;;;;;,;;;;;;;;;;;;;;,;;;,;;;,,;;;;;;;;;;;;;,;;;;;;
;:;;;;;;;;:;;;;;;:,;;;"';1;;11;;;;';;;;;;;;;;;;;;;,;;;i
;;;;

FLUPPY DISK READ ROUTINES

;1n
, , I ,

i;;i:;;;;;;,;;;;;;:;;;,,;;;;;;;;;,,;;;;;;;,;;;,,;;,,:; ;;
;;;';ii'i;;;;;;;",,;;;;,;;;;;;;;;,;;;;;;,;;;;;,;;;;,; ;;

with registers set up a5 below, read the appropriate number of
full sectors from the floppy, at either density, with either
RXY2I DMA or RXYll Programmed I/O interface.
RO:
RI:
R2:
R4:

Starting block number for transfer.
Byte count for transfer
Unit number
Address of buffer to receive data

.ENIIBL LSB
DRt.AD: MOV
MOY
MOY

010446
010046
010146

R4,-(SP)
RO,-(SP)
R1,-(SP)

;Save buffer address
;Save starting LaN
;Save byte count

Check status and media density of selected drive

26
27 173036
28 113042
29 173044
30 171046
31 173050
32 173054
33 173060
34 1730&2
35 173064
36 1730&6
37 173072
3ij 11307&

~-OCT-81

177172

012701
005000
006002
103002
052100
004567
000013
111102
100402

000020
000312

1$:

032102
001411

000040

2$:

MOY
CLR
ROR
BCC
8IS
JSR
.WORD
MOYtI
BMI
ABOIIT
lilt

BEQ

.RXDB,Rl
RO
R2

;Set UP Rl for benefit of RXGO
;Initlalize current unit/density word
;Bit 0 set = unit 1

.RXUUN,RO
;Set unit 1
R5,RXGO
;Start a read status operation
RXSRST
; to determine status and density
f!lRl,R2
;Pick up low byte ot status
2$
;If P~, drive not ready
<Floppy drive not ready>
.RXE$DN,k2
;Check media density
;If EQ, single density
3&

40
41
42
43
44 173100
45 173104
46 173106
47 173110
48 173112
49 173114
50 173120
51
52
53
54
55
56 173122
51 173124

Double density.
Logical sector number = logical block number
Sector count = byte count/2~6.
052700
012602
000302
012&03
006303
012704
000410

BIS
MOY
SUB
MOY
ASL
MOV
BR

000400

000200

'RX$$DE,RO
(SI?)+,R2
R2
(SP)+,R3
R3
U21l.,R4

;Set double density in command
;Byte count
;Divide by 256
;LBN
; Hul tlply by 2
;words per sector

Single density.
Logical sector number = logical block number
Sector count = byte count/128.
012602
000302

3$:

MOV
SWAB

(SP)+,R2
R2

;Byte count
;Divide by 256

KXTll-A2 1K FIRMWARE

MACRO V04.00

b-OCT-81 22:56:27 PAGE b7-1
o

-----> HALl AT PC=173070 INDICAT~S "FLOPPY DHIVE NOT REAUY"
58 173126
59 173130
60 173132
61 173134
62 173136
63
64
65
66
67
68
69
70 173142
71 173144
72 173146
73
74

006302
012603
006303
00b303
012704

ASL
1010 ....

000100

8b 173170

86 173172
87173176
88 173200
89 173202
90 171204
91 17320b
92 173210
93 173212
94173:.!1iI

010446
010246
01034b

4$:

MOV
MOV
MOV

R4,-(SI')
R2,-(SP)
R3,-(bP)

;MUltiply by 4
;words per sector

;words per sector
;Sector count
;Log1cal Sector Number

; start the read operation.
; This is the top of the loop.
004567
000007

000216

5$:

JSR
.1i0RD

R5,RXGO
RXSf(EO

;Start a sector read

Convert Log1cal Sector Numbers to Physical tracks and sectors.
011603
012702
022703
101002
062703
006103
005302
003370
110302
105003
000303
022703
006103

000010
006400

6$:

171400

000014

MOV
MOV
CMP
BHI
ADD
ROL
DEC
BGT
MOYB
CLRB
SWAB
CHI'
ROL

(fSP,R3
#8.,R2
.26.*200,R3
7$

'-26.*200,H3
R3
R2
6$

R3,R2
R3
R3
112.,R3
R3

96 173220
97 1132.,2
98 173224
99 17322b
100 173230
101 173232
102
103 173234
104 173240
105 173242
106
107
108
109 173246
110 173250
111 173252
112 173254
113 173256
114 173260

;And multiply by 2
;LBN

Set up staCK as follows:
O(SP) = Log1cal Sector Number
2(S~) = Sector count
4{bP) = words per sector
6(SP) = Butter address

76
77 173150
78 17315.4
79
80
81
82 173156
83 173160
84 1731b4

ASL
ASL
MOV

R2
(SP)+,R3
R3
R3
'64.,R4

006302
060203
060203
060203
006202
005202
162703
002375
062703

ASL
ADD
ADD
ADD
ASR
INC
000032
000033

H$:

SUB
BGE
ADD

R2
R2,H3
1<2,R3
R2,Rj
R2
R2

'26.,Rl
8$

.27.,R3

;Get Logical Sector Number
;Loop count
;Does 26 go into div1dend?
;Branch 1f not, C clear (SHI => BCC)
;SuDtract 2b from dividend (C set)
;Shift dividend and quotient
;Decrement loop count
;Branch till div1de done
;Copy traCK number
;Remove traCK number from rema1nder
;Get rema1nder
;C=l 1f 13<=R3<=25, else C=O
;Sector*2 (2:1 interleave)
;[+1 (Cl 1f sector 13-25J
;Double the traCK number
;SKew the sector
; by adding 1n
; 6 * traCK number
;Undouble tne tracK number
; and maKe it 1-76 (Sk1p traCK 0
; tor ANSI)
;Put sector
1nto ranQe
1-2b

Head the sector
010311
004514
010211
00451<,\
100002

MOV
.JSR
MOV
.JSR
BPL
ABORT

k3,(fR1
R5,(fR4
f<2,(fkl
RS,rpH4
9S
<FloPpy read error>

Set sector number
Set traCK number
Perform a sector read
If MI, error

KXT11-A2 1K FIRMwARE

MACRO V04.00

5-0CT-81 22:56:27

-----> HALT At PC=113262 INOICAT~S "FLOPPY R~AO EH~OR·

PAG~

, Empty RXV11/RXV21 buffer into HAM

3 173264
4 173270
5 173272
6 173300

004567
000063
032737
001407

000102
004000

9$:
177170

JSI<
.wORD
!:lIT
B~Q

R5,kXGO
RX$EMf
.RX$$CI.2,@,RXCS
10$

Start empty buffer function
and wait for TR
Is DMA availa~le?
If EQ no - handle as RX01

RX02 DMA Operation

8
9

10 173302
11 17330b
12 173310
1317J314
14 173316
15
16
17
18 173320
19 173324
20 173326
21 173332
22 173334
23 173336
24
25
21'>
27 173340
28 173344
29 17334b
30 173H2
31 1733H
32 17336U
33 173362
34 17331>1>
35
31'> 173370
37

016611
004514
016611
004514
OOCl410

000004

MOV
JSR
MOV
JSR

000006

ElR

4(SP),~Rl

R5,@R4
6(SP),.Rl
R5,@R"
12$

;Else load word count
; Wait for TR
lAnd load current bus
;wait for DONE

addre~s

, RX01 programmed 110 Operation
0161'>03
006303
016602
111122
00451.4
077303

000004

10$:

000006

MOV
ASL
MOV

116:

MOVB
JSk
SOB

4(SP),R3
R3
b(SP),R2
@1<1, (H2)ot
R5,@H4
1<3,11$

;Get word count
;Turn word count into byte count
;Get starting bus address
;Move one byte from buffer to memory
;Wait for TR or DONE
;Loop for all bytes in first sector

, Loop back if not yet tinlsned
016603
006303
060366
005216
005366
001273
062706
000257
000207

000004
000006

12$:

MOV
ASL
ADD
INC

000002

D~e

000010

SNi
ADD

ecc

RETURN
.OSABL LSb

4(SP),R3
R3
R3,6(SP)
@SP
2(SP)
!:IS

'd.,SP

;Get word count
;Turn into byte count
;Update bus address
;Update Logical Sector Number
;Decrement Sector Count
;Read another sector
;Pop the stack
;Clear condition codes
; to show success.
; All done

KXTI1-A2 1K FIRMWARE
MACRO V04.00 5-UCT-81 ~l:56:27 PAGE 59
HAL! AT PC=1732b2 I~DICATES "FLOPPY REAL ERRUR"

----->

The main subroutine tor sending disK commands and waiting tor
their completion.

1
2
3
4
5
6

Register usage:
RO
density bit I unit select bit (proto for commands)
RXDB address
Rl
R4 = kXGO TH/DONE test routine pointer

=
=

8
9

10 173312
11 173314
12 173316
13 173402
14 173404
15 173406
1b 113412
17 173414
18 173416
19

012504
050004
010431
010104
005141
032111
001775
005721
000205

RXGO:

MOV
MOV
TST

(R5)+,R4
RO,R4
R4, i\fRXCS
PC,R4
-(Rl)

BE.Q

'RX$$TRIRX$$DN,~Rl
1$

TST
RTS

MO~

815

177170
000240

BIT

(R1 )+

;Copy command word to uSe
;Set unit • and density
;Start operation
;Copy adrs tor later calls
;RI -> RXCS
;wait tor TR or DONE
;It EQ, neither are true yet
;Reset HI -) kXDB and cnecK.tor errors
;Return to caller

KXT11-A2 lK FIRMWARE
MACRO V04.00
BOOTS-TU~8 READ ROUTINES

5-0CT-81 22156:27 PAGE 60
.S8TTL BOOTS-TU58 Read routines

2
; Ii;;;;;;;;;; Ii;; 'i;;;;;;;;i Ii Ii li;i;;;i;;;;;;;i;;;;;;;;;;;;
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;" ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
;;;;
;;;;

3
4
5
6

TU58 DEC tape 11 READ ROUTINES

;; ;;
ilii

B
9

ii;;;;;;;;;;;;;;;;;;;;;;;;;;:;;;;;;;;;;;;;;;;;;;;;;;;;i;;i;;

;;;;;;i"';';;;;;;;;;;;;;;;;;;;;;;;;;';;;;;;;;;;';;;;;iii;;;

10
11
12

Starts a read operation on the TU58 by transmitting a command packet
Inputs:
RO = starting blOCK • for transfer
R1 = byte count for transfer
R2 = unit numoer
R4 = aodress at buffer to receive data
Outputs:
RO, R1, R2 unchanged
De5troys:
R3, R4, R5

14
1~

1&
17
18
19
20
21
22
23
24 173420
2!:! 173422
26 173424
27 173430
2tl 173434
29 173440
30 173442
31 173444
32 173446
33 173450
34 173452
35 173454
36 173456
37 173460
38 173462
39 173464

;; II
; ;;;

010446
005004
012703
0047&7
012703
004715
010203
004715
005003
004715
010103
004715
010003
004715
010403
004715

005002
000206
000002

.ENABL LSB
TREAD: MOV
CLR
MOV
CALL
MOV
CALL
MUV
CALL
CLR
CALL
MOV
CALL
MOV

CALL
MOV
CALL

R4,-tSP)
k4
fl0.*400+R$$CTL,R3
CH20UT
'R$REAIJ,R3
!ilR!:!
R2,R3
iPR5
R3
!ilR5
Rl,R3
iRS
RO,R3
!!IR5
R4,R3
\!IRS

;Save buffer address
;Init cheCKSum
;Set commana tlag and length
;Output two chars ana set R5
;Send read command and moditier=O
;Then un1t number and sw1tches=~
:Plus a zero sequence number
:followed by the byte count
;And the blOCK number
;Finally, transmit the checksum

KXTII-A2 lK fIRMWARE
MACRO V04.00
BOOTS-TU58 READ kOUTINES
1

2
3
4
5
6
7
8

5-0CT-81 22:56:27 PAGE 61
Now ready to accept aata

173466

0121>00

173470
173472
173476
173502
1735u4
173506
173510
173!)12
173514
173!116
113522
1735:.14
173!>:l6
173532

u06001
004767
122703
001017
105003
000303
1060u3
1b0301
010305
004767
U10320
077504
004767
005701

9
10
11
12
13
14
15
Ib
11
18
19
20 173534
21 173!>36
22
23 173542
24
2~ 173546
26 173552
27 173554
28 173560
29 173562
30 173!>66
31 173572
32 173574
33
34 173576
35 173602
36 17 3604
37 17360b
38
39 173612
40
41 173614
42 173616
4J
44 173620
45 173b22
46 173624
47 173630
48 173632
49 173&34
50

000116
000001

1$:

000102

2$:

000044

MOV
CLC
ROR
CALL
CMPB
BNE
CLRB
SWAB
ROkB
SUB
MOV
CALL
MOV
SOB
CALL
TST

001351>
00471>7

000052

SNE
CALL

004767

00005&

CALL

122703
001402

000100

CMPB
BEQ
ABORT
MOV
CALL
CALL
SWA8
RETURI-4

010300
0047&7
004767
00u300
000207
0047b7
020403
001402

4S:
000032
000004

000064

5$:

CALL
CMP
BEQ
ABORT

000207

bS:

RETUR~

005004
000402

7S:

CLR
BR

004717
004717
004767
060304
005504
000207

8S:
00003&

CALL
CALL
9$:
CALL
ADD
ADC
HETURI-4
.DSA8L LSB

~essages

from the TU58

(SP)+,RO

;RO -> data buffer
;(CH20UT leaves C clear)
;1<1
word count for transfer
7~
;Get first word of packet
;15 this indeed a data message?
'RaSDAT,H3
36
;It NE no - may be END message
R3
;Else clear flags
R3
;Move pacKet byte count to low byte
K3
;And convert to word count
R3,R1
;Remove trom transfer count
R3,R5
;And copy for loop counter
9$
;Get next two words
R3, (RO)+
;Store 1n Duffer
R5,2&
;Loop for ent1re data message
56
;Get checksum and compare
R1
;Have all data records been
; transferred?
1$
; I f HE no
7$
;And get prospect1ve
; END packet start
9$
;Get opcode/success bytes
; ot END packet
fR$Et.D,R3
;Is this an ~ND packet?
4$
;It NE no - AbORT
<TU5S END packet m1ss1ng>
R3,1<0
;Save success code In R~
8S
;Read rema1nder ot ~ND packet
5$
;And cheCk its checksum
1<0
;Set CC's on success code of transfer
;Return to caller
R1

CH2H.
R4,1<3
6$

;Get two CheCKsum bytes
;Does it match calculated value?
lIt NE no - ERROl<

<TU58 Checksum error>
;Else return with success
R4
g$

;In1t checksum
;And get the f1rst word

(!I PC
(!I PC

;Read 4 words

CH2IN
R3,R4
R4

Read next two bytes
Add 1nto checksum
with end-arouna carry
And baCK to caller

Kxr11-A2 1K FIRMWARl

MACRO V04.00

5-0CT-81 22:56:27 PAGE 62

••••• > HALT AT PC=173610 INDICATES "TU58 tH~CKSUM ERROR"
1

CH20UT •• Write two bytes to the TUS8

2
3
4

~rites

Inputs:
R3 = two bytes to be output; low byte first
R4 = current checksum word
Outputs :
R3 unchanged
R4 updatea to new cheCksum
R5 pointing to CH20ur routine for easier future CALLs

5
6

7
8
9

0'1
00

10
11
12
13
14
1!1
16
17
18
19
20
21
22
23
24
2!!
26
27
26
29
30
31

two bytes to interface and updates checksum.

173636
173636
173640
173642
173642
173644
113b46
173650
1736!!2
173656
173660
173664

CH80UT:
CALL
CALL

004717
004717

176544

lS:

17654&

MOV

PC,RS

ADD

fd,R4
R4

;Set R5 to following routine adrs
;Update checksum word
; with end·around carry
;Repeat for both Characters
;Is interface ready for output?
;If PL no • wait
;Else transmit character to rUSy
;Merge with other routine to return

ADC
CALL
TS1'b
BPL
MOVB
6R

CH2l1'1
ChIlli

ilPC
iHTOStSR
1$

R3,ilI'lOSBFR
CtIRE'l'

Read two bytes from the TUS8
Read a single byte from the TU58

Inputs:
none.
Outputs:
R3 = character(s) read

32
3J
34 173666
3!! 173670
36 173672
37 11367&
39 173700
39 173704
40 17370&

;~ntry

Ch20UT:
01070!!
01>0304
005504
004717
10!!737
10037!!
110337
000407

p01nt to output 8 characters

ilPC
ilPC

004717
105003
105737
100375
153703
000303
000207

176540

Ctl2IN:

CALL

CtIIN:

CLRS
TSIS

1$:

176!!42
CtlN!:;T:

"PC
R3
UTlSCSR

BPI.

81511

taU'IS8f'R,IU

SWA8
RETORN

113

;Read two, not one
lAnd zero out space for new one
;15 a cnaracter available1
;It PL no
;Else set into register
;Move current Character over
;And return to caller

KXT11-A2 1K FIRMWA~E
END STATlMEl'4T

MACRO V04.00

5-0C1-81 22:5&:27 PAGE 63
.SBTTL lND STATEMENT

1
2

9
0\
\0

000001

.lND

KXT11-A2 lK FIRMWARE;
SYMBOL TABLE

MACR!.J VOlt.OO

AROUN2 172010
AROUN3 173010
AUTOBA 170472 G
BAD BOT 17237u
BAUOkS= 000032
BO.003= OOOOO()
BO.006= 000010
BO.012= 000020
BO.024= 000030
BO.048= 000040
80.09&= 000050
BO.192= 0000&0
BO.384= 00Cl070
BITO = 000001
BITl = 000002
BITI0 .. 002000
BITll .. 004000
BIT12 = 010000
BITU = 020000
BIT14 = 040000
BIT1!> = 100000
BIT2 = 000004
BIT3
000010
BI14 = 000020
BU5 = 000040
BIT6
000100
BIT7 = 000200
BIT8 = 000400
BIT9 = 001000
BOOTS
172164 G
BRKNUO 170010 G
B.CNTL= 167770 G
CHIN
173670
CHK240 172426
173704
CHRET
Ctl21N
17361>6
Ctl20UT 173642
CH8DUT 11363&
CR
= 000015
DEVBlT= 000200
DEVNUII= 000001
OIAGNO 171754
DIRBUF= 001000
DONE
171574
DRt;AD
173030
O.FLEN= 000UI0
EMPTYS= 001000
EI'lDSGS= 004000
ENTSIZ= 000016
ERRBlT 171742
E.EXT = (100100
E.INT = 000010

E.PAR = 000001
FAKOUT 170424
FILNAM= 000Oll2
GI::TCHR 171510
GETNuM 171&12
HGHSEG= U01004
IiKBOQ
171140
HKBD$
171142
HVBAUD 170556
IN8YTE 170550
INBYTS 17055&
171750
hIlS
IN.USR= 1&n1>4 G
KBDQ
170&74
170702
KBDS
17124&
LCSET
LEDOFF= 000017
LF
= 000012
LOAD
172714
LOCDSP 171252
MODE = 000221
MSGQ
171"130
MSGS
171731
NEXNUM 171600
NOCT
171&4:l
NO.u!.Jij:a 100000
NXTSEG= 001002
OCTSTR 171b5b
OCTS'fO 171652
DOT
170&02 G
OOTFLG= 1&7750 G
ODTLOC= 1&7741> G
OD~SlK= 167744 G
OOT",HY= 16777,* G
ONENUM 17157&
O.CHTL= 167772 G
PATERN 171750
PeRO = 000010
PBRl = 000020
PBR2 = 000040
PCMD
171044
PERMFS= 002000
PP.A = 17&200
PP.B = 1"I62U2
PP.BIC= 000000
PP.IHS= 000001
t'P.BI0= 000000
PP.iI!l: OOOOOl
i'P.BI2: 000004
PP.8H= 000006
PP.B14= 000010
PP.tH5= 000012

=
=

0
I

-....l

174000
000000
ERRORS DETE;Cn;D:

000
001

ASS •

5-oCT-81 22:56:27 PAGE &3-1
PP.t!l6; 000014
PP.BI7= 00001&
PP.C = 17&204
PP.CHI= 000010
PP.CLO= 000001
Pi'.CWR= 176201>
PP.DflA= 000020
Pi'.DRIl= 000002
PP.PlDA= 000040
.. P.II0S= 000004
PP.M1)2= 000100
PP.MOO= 000;l00
17070&
PRINT
PRI& = 000300
PRI7 = 000340
PUTCHR 171522
PUTCLF 171554
PUTuF
1715&4
PUTSrR 171542
Plr/RSUP 17021>0 G
QOOT
170&&b
RAMBOT= 1&0010
RAMTOP= 16777&
RBUFst= 177562
RBUFS2= 176542
RB.ilRK= 004000
RB.ERR= 100000
RB.FRM= 020000
i<B.OVR= 040000
RCMO
171144
RCII01
1712j2
RCS!!S1= 177560
RCSR$2= 176540
RC.ACT= 004000
RC.OUN= 000200
RC.J.EH= 000100
REAOU
172772
REAOZU 172770
REGOUT 171240
RESTA!! 172004 G
RETRr = 0011010
RFLAG = 000200
RPOINT= 167756 G
RTSEMT= 000052
RTSFCh= 000056
RTSFCT= 000057
RTSHGH= (,00050
RT$lSP= 000042
RTSJS.,= 000044
RTSRMN= 000054
RTSSTA: 000040
RTSUEt<= OQ0053

RTSUSR= ()00046
RXBOOT 172400
RXCS = 177170
RXOB = 177172
RXE;SCI\= 000001
RXESOO= 000100
RXESOE= 000020
RXESDN= 000040
RXESOR= 000200
RXE$lD= 000004
RXESUN= 000400
RXGO
17337:l
RXSEMP= 000003
RXSFIL= 000001
RX$REC= 000017
RXSRED= 000007
RX$RST= 000013
Rl!.SSTD= 000011
RXSWUD= 000015
RXSWRT= 000005
RXSSDE= 000400
RXSSDN= 000040
RUSER= 100000
RXSSFN= 000016
RXSSGO= 000001
RX$$lE= 000100
RXSSIN= 040000
RX$$TR= 000200
RXSSUN= 000020
RXUXA= 030000
RX$$XX= 003000
RXSS02= 004000
R$ABRT= 000006
RSCOMP= 000004
RSOIAG= 000007
RSENO = 000100
RSGETC= 000012
RSGETS= 000010
RSINIT= 000001
RSNOP = 000000
RSPOSI= 000005
RSREAU= 000002
RSSETC= 000013
RSSETS= 000011
RSwRIT= 000003
R$$CON= 000020
RS$CTL= 000002
R$SDAT= 000001
RS$lNT= 000004
RSSXOF= 000023
R.HALT= 100000
R.NXM = 000200

R.PC = 16771>1> G
R.STAK= 000001
f<.1'YPE= 1&7762 G
R.STRT 170031> G
,sAVPC = 167752 G
SAVPS = 11>7754 G
SI::GAuO= 001000
I:;PACE = 000040
SRET
17160$&
STANDS 17251>4
STAR1'
17J000 G
STARTS 172'152
STRbLK= 001010
ST'l'UBD 172172 G
ST173
173000 G
17121;t
SWCMD
SSCART= 1n707
SSDCHK= 177757
SSMOTR= 11"1737
SSNORM= 000000
SSOPCO= 177720
SSPART= 177770
S$RECN= 177711
SSRETR= 000001
SSSE;EK= 17774U
SSUNIT= 177770
/:iSWPRT= 17770!>
TENTAS= 000400
TISBFR= 17&542
TISCSR: 17&540
TOSB.'R= 17&546
TOSCSR= 176544
TI<AP4 = 161776 G
TREAD
173420
TUBAUD= oOllon
TOBOOT 172464
T.BIT = 001l0:;:0
USERSP= 1&1'1&0 G
'vI:.CSI:.T 1704'10 G
XBUF$l= U7500
XBUF$2= 170546
XCSR$!= 1'1751>4
J(CSRS2= 176544
XC.&RK= 000001
XC.IEN= 000100
XC.MNT= 000004
XC.PBE: 000002
XC.RDY= 000200
XTI<BkT= 001006
S$TACK= 167644 G
SS$BRK 170000 G
SSSLTC 17000& G

KXTll-A2 lK FlkMwAR~
SYMBOL l'AtlLE

MACRO V04.00

VIRTUAL MEMORY US~D: 9210 WOkDS
DYNAMIC MEMORY AVA1LABL~ FUR 40
,FALCUN/C=FALCON

V
I

-..l

5-0CT-~1

(36 PAGlS)
~AGlS

22:56:27 PAGE 63-2

II,ACRlJ V04.00
KXTll-A2 11\ FIRMwARE
CROSS REFERENCE TABLE (CREF V04.00 )
SSSBRK
S$SLTC
SSTACK
AROUN2
ARDUN3
AUTOBA
8.CNTL
BAObOT
BAUDRS
BO.003
BO.006
BO.012
80.024
BO.048
80.096
BO.192
BO.384
81'lU

V
I

-..)

8ITl
BIT10
8IT11
8ITl2
BIT13
SITU
BIT15
BIT2
SIT3
BIf4
BITS
BIT6
8IT7
BITS
8IT9
BOOTS
BRKNOO
CH21N
CH20UT
CH80UT
CHIN
CtlK240
CHRET
CR
D.f'LEN
DEVBIT
DEVNUM
OIAGNO
OIRBUF
DONE
DREAD
E.EXT
E.INT
E.PAR
EMPTYS
ENDSG$
t:NTSIZ
ERRSIl'

14-16'
14'-20'
13-30,
44-47
54-24
27-13
13-141
49-66
9-14'
7-211
7-22,
7-231
7-2411
7-2511
7-2611
7-271
7-2fH
5-5'
5-6,
5-15.
5-16,
5-1H
5-1!1,
5-19'
5-20'
5-7#
5-8.
5-9.
5-1u.
5-11'
5-121
5-13'
5-14'
33-21
14-1i1
61-34
60-27
52-17
62-35,
51-1 H
62-24
5-25f
48-1~5'

10-11.
10-1311
33-25
4&-62.
40-17
50-21
10-17#
10-18.
10-19.
48-1271
48-129,
48-1241
44-19.

5-0CT-81 22:56:27 PAGE S-l

27-35
27-37

24-13

27-17

49-77

49-91

49-54*

49-55

56-3

9-1tj
7-43
7-36

1i-29
8-27

8-47
&-38

10-5
8-40

10~13

iI-42

35-50
lj-44

6-10

6-37

6-35
6-32
b-30
7-30
7-15
7-10
7-17
0-23
0-19

10-3
8-25
8-2"
8-21
8-18
7-1$
7-3

46-2.
56-2.
28-431
20-49*
49-90.
28-44

9-14

49-25.
14-l6'
b1-4b
1>2-16,
62-131
52-3b
62-3911
37-26
53-47
49-37
49-83
44-3711
48-11 II
40-3H
56-4
44-17
44-18
46-6
53-31
46-11

10-9
8-38
8-3£1
9-34
38-11
8-17
11-15

8-39
8-39

8-42
8-40

11-43
B-41

38-9
9-32

10-4

10-11

38-21

40-~4

41-20

43-13

48-119

48-12U

48-121

4S-122

:11-17
62-jU

57-211

53-21

KXTll-A2 1K FIRM"ARE
MACRO V04.00
CROSS REFERENCE TA8LE (CREF V04.00 )

0I
-.j

FAKOUT
FILNAM
GETCHR
GETNIJII
HGHSEG
HK80$
HKeOQ
HV8AUD
IN. USR
INBYT$
INBYTI::
INITS
KBD$
KIlDQ
LCSI::T
LEDOH
LF
LOAD
LOCDSP
'"'ODE
MSG$
MSGY
NEXNUM
NO. LOw
NOCT
NXTSEG
O.CNTL
OCTSTO
OCTSTR
ODT
OOTFLG
ODTLOC
ODTSTK
OOTWHY
ONENUM
PAlERN
PBRO
PBRl
PBR2
POlO
PERMFS
PP.A
PP.B
PP.8IO
PP.811
PP.8I2
pp.Bn
PP.8I4
PP.815
PP.BI6
PP.BI7
PP.8IC
PP.81S
PP.c
PP.CHI
PP.CLO

27-12
48-60.
33-111
33-36
48-120,
35-5H
35-51>11
29-10
13-1b.
29-11
29-t!
44-271
32-44
32-48,
33-43
9-10,
5-2U
53-44
36-39
·9-5.
32-52
32-49
41-18,
10-9,
41-25
48-119,
13-10.
32-40
37-22
14-32
13-26,
lJ-2H
13-29'
13-H
3b-15
44-33#
7-15,
7-16'
7-171
33-28
48-1288
8-6,
8-H
8-45.
8-44.
8-4),
8-42.
8-411
8-4u,
8-39.
8-38,
8-48'
8-471
8-8#
8-231
8-29f

27-15f
53-38
36-30
,!7-33

37-25
41-:.12,

5-0CT-81 22:56:27 PAGE S-;!

39-15.

39-17

41-19

49-34

49-44

37-27
37-21
29-311
14-17
29-2711
29-20.
46-14

38-15
37-31

37-37

37-39

38-18

38-2()

14-31*

19-36*

20-31

21-11*

22-13*

27-11'>*

35-52*

49-31*

32-~1f

35-57
33-34

33-37

33-45

35-37

35-56

36-16

36-20

3b-n

44-39
38-13

38-17

40-29

43-13

32-11'
37-38
37-45

38-19
38-12*

38-23*

33-32
37-171
26-:"17
37-36
54-H
37-18.
24-20
43-131
43-12.
41-30
21>-49
41-35,
53-34
37-48
42-141
38-25
22-19
32-57*
36-311*
13-30
32-1&*
41-10,
41>-19
7-22
7-23
7-25
35-221
53-29
46-4
4b-3*

9-10
9-10
9-5

29-32
46-4~

38-28
44-38

38-5
46-44
42-1511
27-18
36-14*
37-17*
32-22
35-35*
7-24
7-24
7-26

7-2b
7-27
7-27

7-28
7-28
7-~8

38-24

36-32

KXTll-A2 1 K FlRMwAHE
MACRO V04.00
CROSS REFERENCE TABLE (CREF V04.00 )

0
I

-.l

PP.CWI<
PP.DRA
PP.DRB
PP.MD2
PP.MDA
PP.MOB
PP.MOO
PRI6
PRI7
PRINT
PUTCHR
PUTCLF
PUTLF
PUTSTR
PWR$UP
QODT
HS$CUN
RSSCTL
R$$DAT
RS$lNT
RSSXOF
R$ABRT
RSCOMP
RSDIAG
RSEND
RSGETC
RSGETS
R$lNlT
RSNOP
.R$;'USI
RSREAD
RSSETC
R$SETS
RSWRIT
R.STRT
R.HALT
R.NXM
R.PC
R.STAK
R.TYPE
RAMIlOT
RUTOP
RB.BRI<
RB.ERR
RB.FRM
RB.OVR
RBUFS1
RBUFS2
RC.ACt'
RC.DUN
RC.UN
RCMD
RCMDl
RCSR$l
RCSRS2
READU

8-5'
&-211
8-2H
8-17.
8-18,
8-25.
8-1!>#
9-271
9-2H'
32-50
37-24
40-231
40-29.
32-56
24-12.
32-37
48-81#
48-79'
41j-78if
48-80'
48-82'
48-92#
48-90'
48-931
48-981
48-9&'
48-941
4&-8H
48-8&'
4i1-9U
48-811'
48-971
48-95.
48-1:19,
19-1U
10-31
10-4t
13-15#
10-5'
13-18'
9-2H
9-231
6-371
6-30.
6-35'
6-321
6-&.
6-10'
11-16'
&-19'
&-231
33-30
3&-23
6-5'
6-9'
53-22

24-20*
9-5

9-5
27-11
27-36
32-541
38-22
42-14
40-15.
45-5
.32-411
52-:0:7
60-26
61-7
52-22

5-0CT-81 22:56:27 PAGE S-3

26-27*

44-38*

44-39*

32-55
27-3~

49-67
35-48

55-5

38-27

39-19'

39-~1

40-1&

40-25

40-30

42-22

19-34"

20-11*

20-17*

21-46*

22-18*

32-1&

29-3

29-7

32-12

39-18

29-5
48-6&

39-16

40-19
55-10

52-22

&1-25

&0-26

45-7
14-29
19-34
21-35"
20-11
14-29"
25-19
25-24

24-35
48-&9
24-36
24-36
36-1H
36-3&#
24-3&
46-12
54-231

21-46
22-18
21-39*
35-35
19-32

35-::15
21-41
3:l-36

32-42

32-54*

KXTll-A2 1K FIRMwARE
MACRO V04.00
CROSS REF~RENCE TABLE (CHt:F V04.011 )

tl
I
......:J
Vi

READZU
REGOUT
RESTAR
RETRY
RFLAG
RPOINT
RTSEfoIT
RTSFCH
RTSFCT
RT$HGH
RTSISP
RTSJSW
RTSRMN
RTSSTA
RTSUER
RT$USR
RX$$02
RXUDE
RX$SDN
RXSSER
RX$SFN
RX$$GO
RXS$IE
RX$$IN
RX$$TR
RXSSUN
RX$$XA
RX$$XX
RXSEMP
RXSFIL
RXSRf;C
RURED
RXSRsr
RXSSTD
RXSWDD
RXSWRT
RX800T
RXCS
RXDB
RXESCR
RXESDD
RXESDE
RXESON
RXESDR
RXESID
RXESUN
RXGO
SSCART
SSDCHK
SSMOTR
S$NORM
S$OPCD
S$PART
SSRECN
SSRETR
S$SEEK

52-35
36-25
21-27
48-54#
9-32.
13-:.12.
48-138,
48-1411
48-142.
48-137'
48-13U
48-135'
48-140,
48-lJH
48-1391
48-136.
48-21f
48-2H
48-26'
48-18.
48-28.
48-29.
48-25.
48-19.
48-2U
48-271
48-20'
48-22'
48-34'
48-331
48-40.
48-36'
48-38,
411-3H
48-39'
48-35'
49-87
48-131
48-1U
48-50'
48-46'
48-48,
48-471
48-45'
48-49'
48-4U
57-32
48-106'
48-108'
48-110'
48-102.
48-111#
48-10U
48-112#
411-1038
48-109"

54-6
36-34
45-6.
36-14
32-32*

5-0CT-81 22:5&:27 PAGE S-4

54-211
36-38,

36-37

54-17
54-9
58-5
57-44
59-15
48-33

48-34

48-35

48-36

48-37

50-15

50-16

58-!)

59-12*

58-3

59-10'

59-15
57-31
58-4
57-78
57-33

50-141
48-14
57-27

57-37

57-71

48-38

48-39

41j-40

KXTl1-A2 1K FIRMWARE
MACRO V04.00
CROSS REFERENCE TABLE (CREF V04.00 )

-.....'I
0\

S$UNIT
s$WPRT
SAVPC
sAVPs
sEGALO
SPACE
SRET
sTl73
sTArWB
START
STARTS
STRBLK
sTTUBD
SWCMD
·T.BIT
TENTA$
Tl$SFR
TI$CsR
TO$BFR
TO$CSR
TRAP4
TREAD
TUBAUD
TUBOOT
USERSP
VECSt:T
XBUF$l
XBUF$2
XC.BRK
XC. lEN
XC.MN'l
XC.PBE
XC.ROY
XCSR$1
XCsR$2
XTIlBllT

48-105'
48-1071
13-25.
13-24'
48-118'
5-26'
41-21
55-41
51-21

14-21*
14-28*

5-0CT-81 2:.1:56:27 PAGE

21-31*
21-36*

27-12*
27-11*

52-25

62-36

52-14
49-78'

62-21
54-18*

32-39
3!>-16*

35-11 *
35-53

37-23
41-32'
53-1!>'

4~-U

54-11
48-122.
49-30.
36-18
9-341
48-126'
48-69'
48-68.
48-71.
48-70,
13-51
56-5
9-18,
49-81$

13-20.
26-46
6-8.
6-12.
7-431
7-81
7-30.
7-36'
7-H
6-71
6-1U
48-12.11

54-141
53-25
36-29.
37-50
62-38
52-13
62-23*
49-26*
22-11
60-241
49-26
52-12.
32-20*
27-341
39-:t2*
48-71
52-20
44-26
9-14
24-39
24-32*
48-.70
53-50

32-25
51-22

9-18

44-25

44-2b

24-39

28-44*

29-37*

39-20

s-~

35-54
36-H

36-24
37-45

KXT11-A2 1K FIKMWARE
MACRO V04.DO
CROSS REFEk~NCE TAbL~ (CREF V04.DO )
ABORT
DELAY

11-15.
bl-27
12-23f

49-42
61-37
49-70

49-51

5-0Cr-Sl 22:5b:27 PAGE M-1

49-92

51-23

52-29

52-37

53-24

53-36

54-12

57-36

57-114

APPENDIXE
SBC-11/21 SCHEMATICS

Appendix E provides the user with the electrical schematics for the SBC-ll/21 module.

E-1

n,
8 D FF
7'15'37'1
E27
2
RI
KICT'J REVNT H --1 D8
RI .'5
KlCT7 PAROST H --..!t. 01
Re i6
ICIIT'I IRQ'I H -Z. 112
9
R'3
ROll H -'. D.
R'I fa-KI<Tt
lCDLI H ...ll D't
R'5 flLKIITt
ICIIT7 I'BRQST H -L'! 0'5
R6 rlLKMTI
MOl2 H -'L D6
R7 fl.!-KICTt
RDl2 H..J.! 07
SFTBNO l
E" OUT
KIITt C~S H
ClK

KICTt SELl H
KICTt RAS H
-KlCTt SEL8 H
R2
IK ..

'512 lC 'I
RDn
&'386
E'3'3

CICOl2 H

KXTI CIKRO H

CRDl2 H

KXTI CRDl2 H
KKTt CMOl2 H

:Ii

1'1

917'1lS1
I~

-+.

+'3VA

DAll'!I~
2
DAll'l~
'3
0~lI3~
'I
OAlI2~
'5
DAlll~

~ €I

DAlll~
DAl9 ~ 79
D~l8 ~

III

O~l7 ~ 11
DRl& ~ 12
ORlll ~ 1'3
DAl'l ~ 1'1
OAll ~ 1'5
0~l2 ~
16

-KXTt PI H

KXT2 DnRQ H--!t. De
RI
KXT3 HlTRQ H~ 01
RZ

KKTt IAKDIN H

KKT'3 BKRQ H.-l..£ OZ
R3

];pI
18

....lS D

E8 p~

KKTI TlAKO H

KlCT'I PFAll H-1.1 D.
KXTt B2ClR l~ ClR
KICTt CAS H~ ClK

7'1
l57'1

KilT I COUT

KICTI BelR l
-KICTI RAS L

7'1 lSI
E'96

KKTt CDnRQ H

~
7

pL-

p"
~

-KIeTI CAS H
-KIeT2 TSTNC H
lClCTt \lRlTE H

TORl
TDAl 119
KICTI B2CLR l

TDAl II

KIITI BClR l

TDAL

KMTI BClR H

KIITI AOI ... H
'5

I(KTI ADI2 H

R2 I;

I<KTI ADIII H

.,
R'3

R'I

19 KleTt ADI" H
R7

-KIITI RAS H
-KICTt CAS l
-KXTI CAS H

KKT! RAS l
KIITt CAS l
KICTt PI H

KICTI SEll L

-KICTI COUT L
-f(MTI COUT H
KIeTl TCOUT H
SFTGND l

KIeTI SIL' l

KXTI SEle H

KXTt TCOUT H

)k~lS8
£11

6"0

KIeTI SEll H

KMTI SEll H
KMTI SEll H

KICTt RDBS H
TDAl III H
KMTI AOII't H
TOAL I" H

II
I

KleTt COUT L

ICICTt ADII2 H

TOAl 12 H

RAMS
REl

KKT3 RBS7 H

KIITI lBS7 H
KIeTI ADIII H

TDAl 81

KICTI RDn H

KKTI \lITrE H

TDAl
KKTI ADII'5 H

IClCT'3 RSTNC H
-KICTt CAS H-KIeT2 NO 8TTE H

'I
'37'1511 6
'5 EI2

KXTt 1'10117 H

TORl

KKTt TREAD H

KleTt TOIN H

KKTI AD09 H

KIeTI AOIl H

··'5~""_KIITI
\lRlTE l
'I E2'1
7'1S3Z
EI'I

KKTI AD88 H

III I< liT I RDII H

TOAL

'3
'I 7'1lS2 ,.,6
'5 EI'5

KKTt IAKDIN H

TDAl Ie

'3-5TATE
LINE
DRIVER
?'tlS2'111
E'IS

BBIT
'3-STRTE
lRTCH
7 .. 5373
E'IB
RII

EI't

KICT2 TSTNC H
KICTt PI H
KleTt CAS H

TOAl 12

2 • ...---

-KKTZ RQSlP

TOAl I ..

RI
2211

II TDAl 11 H
1'9 TDAl 1'1 H

TOAl

All ~ ~'3
AII!~ f1;9
RRS~
31
CAS ~ 31
PI
R/UlB
R/UHB 2'5
SEl0 2'1
SEll 22
MTll
COUT 21

TCOUT~~

IR-B
IR-B

-KKT3 PUP H--,1;!. PUP
GND~ KTlII
~ READT

1'5

3 TOAl 1'5 H
'5 TOAl 13 H
7 TOAl 88 H
9

-KleTt RAS l

KXTI CTnER H
-TCllC H KIITI C8KRQ H

III

KIITt

'~~f

8D-B
ID-8
-KKTI TBS7 l
KICT I B2CLR l ----'--'-"'q ENO-B

A12~ ~'t

RII

lS2

7'1lSI!
'3 E26

12
1'1

All

'I D FF
7'tlSI7l1
E'32

121
1

AI6~ ~8
AI'5~ ~~
'3S
AI'I~
'3'5
~

IIR-A
IR-A
2R-A
3R-R

ENO-R

TDAl 1'5 H
fDAl 1" H
TOAl 13 H
fD~l 12 H
TDAl II H
TDAl Ie H
fDAl 89 H
fD~l 88 H
fOAL 117 H
TDAl 06 H
fOAL 811 H
TDAl 11'1 H
fOAL 11'3 H
fDAl 82 H
TDAl 111 H
fDAl II H

DRll ~ 17
DAlI ~
BClR ~
39
AI7~

TOAl 12 H
KI<Tt SELl H
-KICTt SELl H

2
'I liD-A
10-1'1
6
SNO-t--L-,---~; 2D-A
III 3D-A

KXTt BClR H

CPU
DCTt I
XE'57

lB.
J)7'tlS8
9
E31

KICTI SEll H

13
KICTt 1'1 H

~
I 7~l51
2 E3'1

6
2 '5
'I 'I3 ADR
7 2
r. 1

KXTt CKDll H

,~7'1LS8
'5
E'31

18 E'3'1

L......l,!
I 7

KXTI CI'BRQST H

7'1LS'367A E'II
HEX DRIVERS

+3VA

2n I18
In 12
8n

CI'BRQST H

KXTt IAK l

'1 • ..--

IND

,
'9n

CXDll H

'3 ?'IlSI
't E'3't

nZ6M29M30M22

f(XTI RSYNC l

KleTt liT H

KMTI TDOUT H
IeIeTt TDOUT H~
7'1S32
KKTI TRITn H
KXTt TDIN H 10 EI'I

SHEET 1 OF 7

B-3

M18 M'58

+'5YHCR

112'5 M21 f.i+'5YCR

:-.}~
12 X B
PROM
82512'3
E't8

1 i!2
2KII

6
'5
~~~r-+------r--KMT2
~~~r-+------r--KMT2

CSKTB H
CSOLI H
CSQB H
I-!-:~~r-+------r- -KXT2 CSL I P H
~~~r-+------r--KMT2 CSPL H
~~~r-+------r--KXT2 CSOLB H
~~-t--+-----~--KXT2 CSKTA H
f-!.!4--t--''----- -KXT2 CSRAM H
I-'-:=+-t-~--+- -K)(T2

8M 2I
1M '3
2M
1M '5
.. M
5M 67

-I(XT2 EYNTAK
-KXT2 BKAK H
-KXT2 PMK H
-KMT2 PBAK H
ROLl H
MOll H
RDL2 H
MOL2 H

611
9
711

TDAL 88 H ~
TDAL 89 H -+.1:
TDAL 18 H~
TDAL 11 H~
GND -ll

1 i!2
2Ka

i!1
i!1
't711. :-'}~R ~~IIR 't7BR
7
8
'5
'3

B
I

2 ADR

'3
'I

KKTt IAK L ~ EN

KXTI loIT H
KKT2 TlJTBT H
"'3YB
KICT'3 DCLo H
KXTl IIBrTE H
OJ
8

-KKT2 CSLIP H

K)(TI CAS H
GND

K)(T2 TSl'HC H
I.

+'3YB

KKTI RAS H-""T"1 --0-'_

r---~L-KXT2

..-8_ -KXT2 RQSLP H

TS'rNC H
-KXTt SELl H

KICT2 TMRP L

Kl<T2 DRRPLl' H

K)(Tt B2CLR L

KXTt B2CLR L

KXT2 NO BrTE L

+1YB
-KXT2 TSTHC H
'3
8

-KXT2 0116 H

19.56'8MHZ

U .--

-KXT2 DRRPL'r H
9

-KXT2 DRRPL'r H 1 I
KICT2 SCLK H K)(r 1 B2CLR L

I(XT2 TSYHC H
-K)(TI CAS H
KXTZ DRRPLY H

KXTI BCLR

TCLKSP H

-K)(TI RAS H
-KXT2 TCLKSP L

HOTEl OSCILLATOR PACKAGE IS METAL

K)(T2 SCLK H I I

-KXTI PI H

711LS8
18
K)(T2 TI1RP L
H~
B E26
K)(T) RRPL'r H
KXT'3 TMER

-TCLKSP H
KXTt B2CLR L
+1YB
KXT2 DMRQ H
KXTI SEUI H

K)(Pt RSACK H

I(XT2 ORRPL'r H

-!-'3YB
-K)(TI IAI< H
K)(T't ROMR H

9
8

KXTI COUT H I I

2 0

-KXT2 DRRPLr L
K)(TI COUT H

KXTI SELl H

K)(T2 DMRQ H

K)(TI BCLR L

K)(T I BCLR L

Kxn RSACK

-K)(T2 TOMGO L

-L---+L-_-_-_-_-_-_-_-_-_-_-_-_-_--'
________________________---'

SHEET 2 OF 7

E-5

Kxn RRPLY

.-----t- BRPL Y L <BID
KKT3 RRPLT H
+'311 A

~---- BHAL T L <aEi)

K)(T20"RQH~
8881
.. BO"60 L <:ag)
KI<T2 TDnGO H

THRLT H --+----+--9

+'3VA

El
TEVNT H ---t-----t-'-'f,

Dl
KI<Tl TDOUT H~8881
~
BDOUT L~
9 EI

2 , - -....,-- KKT'3 REVNT H

.------BEVNT L ~
'3

~---- -BDCOK L @D

DSS'I
S

+~VHCR-~~-Kr---~r---------~

R't

KlC13 DCLO H

C8
39UF

l1i181<A

KXTI BCLR L
KI<T2 EVNTAK L

NOTE' IF BPOK H [5 ALUATS
ASSERTED THEN FF [S ALUATS PRESET.

-1<lCT'I PFRIL L

lev

-1<KT2 OMe H

KX13 PUP L

'3 BDIN L<aiiV

1<KTI TDIN H

KlCT2 TUTBT H

B1H8T L~

~~IWB~------~~----~KXT'3 DCLO L

+!5VHCR
R'5
'171< ..

MI'l

. - - - - - B IIH T 'L

<aID

1<I<TI BCLR H ---'-.....
.-----BSTHC L ~
K)(T2 TSYHC H

1<)(Tl TlAKO H--................,

58V

1<)(13 RBS7 H

GND
7

"12

C9
828Pf'

, - - - - - BBS 7 L@)
1<I<TI TBS7 H

M'3

+'3VA

M'59

t+'5VNCR

-=-

KI<TI TReTn H-1~~8U-~~~I~~~~~2____t-__,
7'1 ...
LSI23
E9

+'lVA

"lilA

+lVA

Kl<n RSYHC H
. . . - - - - - BIRKO L <aHV
~"...._.......

MIB Ml'3

,-----...-':'-''- KI<T3 TnER H
KI<T3 RRPL Y L -..L.--------t---+4

'--""L-"--_ 1<KT'3

HLTRCI H
+lVA

,-----..-"-- KI<T'3 BKRCI H

9
8

-KlCTI RA5 L
KI<T2 BKAK L
KXTI BCLR L

KI<TI CTnER H
KI<TI TREAD H
KXTI PI H

SHEET 3 OF 7

B-7

+~VCR

BIT
TRANS
CE[VER
~

RESISTOR
NETIoIORK
1118110-00

RES[STOR
NETIJORK
1'318110-00
2
'3
~

R'3

'3.~8KD

REG SEL
DCB0~

£19

H
H

CII
128pF
1!!18V

'5
I>

8
H 9
10
H
If
H
12
H

"'~.0V

l"
&80R

-::-

~ -BPi'lL 1'+ H 2
'3
+'3VB
~
BPI BSPARE I> 11
'5
BP2 -BPi'lL 10 H &
BLZ -BDAL 87 H 7
BR2 -BPi'lL II H
8
BT2 -BDAL 13 H 9
BS2 -BDAL 12 H 10
BJ2 -BDAL 0'5 H
BM2 -BOAL 08 H 11
BN2 -BDAL 09 H 12

I' ~Z

2Kn

DC00~

E't'3

i!'5

i!6
+~VNCR

D'3<X> 6
[N/ 02 <X> 7
OUT DI <X> 17
18
De <X>

+'5.0'1

1'"

8 MATCH
BU,
9 BU2
II BUI
12 BU0
1'3 MENB

68001

::-

+~VNCR

L<aW
RERD L
IoIHB L
IoILB L

't B[T
TRANS
CEIVER

H '3

KXH RLB H

i!2
21(0

E~Z

IRC~

'3
I>

TPAL
TDAL
TDAL
TDAL

P'3<X>
IN/D2<X> 7
OUTpl <X> 17
18
D0<X>
H

19
2 JA3
JAZ
JA1
1&
°JV'3
1'5 JV2
1'+ JVI

MRTCH H '3
II H B BU'3
9
10 H
BUZ
11
09 H 12 BUI
H 1'3 BU0
l
MENB
19 JR'3
+'5VNCR
2 JR2
JRI
I G JV3
15
JVZ
l't JVI

SEL

OC011~

TDRL e'3 H
TDAL 02 H
TDAL 01 H
TDAL 0e H
I<XH

+~VCR

't XtllT
REC

KXH XHB H
KXT't RHLB H

II H
10 H
09 H
08 H

KXT't RSRCK

't XMIT
REC

KXTI RSTMC L
RESISTOR
NETWORK
1318110-00
i!'3

~ BIoITBT L

@D 8£>[1'1 L

<aID BDOUT L
RUZ
RVZ
BEZ

OUT

BDRL !!Ie L
BORL el L
BOAL 82 L
GNP

VEC

-I(XT2 CSQ9 H 1'3 EN

2
3
~

H 5
H G
H 7
H B
H q
H 10
H
11
H
12

RESISTOR
NEHIORK
1319110-00
24

In.

+~.0V

H
H
H

ti
H

&800

2
3
4
~

I>
7
B

9
H 10
H II
H 12
H

-::-

'+ BIT
TRANS
CEIVER
DC00'5
E't7

+'5.0V

1'"

MATCH H 3
au'3
SU2
SUI
SU0
MENS

07 H
0& H
0'5 H
H
L

2Kn
10
TOAL 07 H
TDAL 06 H
TDAl 0'5 H
TDAL 0~ H
KXH RDMR H

BLT

+'5VCR

TRANS
CEIVER
DC005
E51
D'3<l> G
[N/ D2 <x> 7
OUTDI<x> 17
18
D0<l>
I~

f't H
13 H
12 H

MATCH H '3
8 BU3
9
aU2
II BUI
sua

I,
22
2Kn
7

- TDRL 1'5 H
TDRL l't H
TDRL 1'3 H
TDAL 12 H
KXT't PFRIL H

JA'3
JA2
JRl

+~VNCR

KXT2 CSQB l

D3<X>
IN/D2<X> 7
OUT DI <l> 17
18
D0<l>

&811"

+'5VCR

16 JV'3
1~
I~

.JV2

JVI

KXT2 DMe H
XMIT
REC

KXn RSYNC H

KXT'I CSCB H
KXTI TREAD H
KXT2
DRRPLY H
Kxn RLB H

KXTI TlRKO H
-KXTl IAK H
-KXTI BCLR H

KXT't RHlB H
KXT't XHB H
KXT3 RSYNC H
-KXT2 CSQB H

KXT't READ L

'3 7'tl514 .....-'-_L_ KXT't READ H
E21

SHEET 4 OF 7

E-9

NOTE:
"7 IS URAPPED TO MI NORMAllY.
IF BATTERY BACKUP IS DESIRED
FOR E~~ AND E~~ THEN ~RAP ~7
TO ~16 AND nl~.

~~1

"'l'l

n'll

KKTI

KKT2 CSKTA l
.~VNCR-

KXTI AD8S
KICTI ADII7
KICT I AD81>
KXTI ADII.,
KICTI ADII~
KXTI ADIl3
KXTI A002
KKTI R001
TDAl es
TI>Al 89
TOAL I II

H-

AOle H

H-

HHHHH-

-f 0 IIE"\~2~-+_ _-I
~0
~0

+!! 0

-!-:l: 0

0~1:--_+--+_+--_+---l

0!'!2-=":--1I---+-+_---l

or,I-:9~-+--+_+---+-t- TDAL 1'5 H

0r,1-.;8;--11---+-+_--+-+- TOAL
~0
0..,1.,,7_-1r-_-+_+-_ _+-+_ TI>Al
H0
or,I-,'!&:--___1I---+-+---+-+- TDAl
GNO-t~I~It~~~_~o¥I~~~-1I---+-+_--+_t- TDAL

1'1 H
13 H
12 H
II H

KI<T2 CSKTB l

KICTI ADee
KXTI ADII7
KICTI AOIII>
KKTI ADII"
KKTI AOll'+
KXTI ADII'3
KXTI AOll!!
KXTI Roe I
TOAl es
TDAl 09
TDAl Ie

H- r-to 28 ,,~
H- ~o PINor.2::'!"'-1H-+--f--+--Ir--KICTI
H0 SDCKo 2'1
KXT I

H-

~oXE"~~

H-

~oo

H-

r-::

HHH-

~0
~0

KilT I

+"YCR

ne
MI
M2
Ml
M't
M'5
M6
M7

AOl2 H

ADII9 H
AD I II H

KXTI
KXTl
KXTI
KXTI
KXTI
KXTI
KXTI
KXTI
KXTI
KXTI
KKTI

°0F.!2"'1-I--IH

0!,!2~1I"""1--+-+_-+-___1

I '5
0
I It
H~0
I3
H~0
12
GNO-t~I~'I~o~_~o¥I~~'-1I-_t-+_-+____1H_-TDAL II

r!-!

GHO

0r,1-:!9,....,1--t-+_-t-___1H_- TOAl
0 I8
TOAl
0 I7
TDAl
0 L~
TDAl

H
H
H
H

KXT,+

"'37

ADel
ADB2
ADel
ADII"
ADII'5
A066
1'1067
AOl!l8
1'1009
ADI0
ADII
~HB

H
H

H
H
H

H
H
H
H

KICT't READ l
KKT2 CSRAM l

,-!rovo 28

".,VHCR

KXTI ADeS H ~o 28o~

KilT I ADe7 H ~oPIN02"
KXTI Aoe, H ~oSDCK02'1
KI<TI ADe'5 H
f(XTI ADe't H - - - - : : 0
0
0 21
KI<TI ADII'3 H ~o
0 28
f(XTI ADII2 H ~o
0 19
KIITI AOel H ~o
.. 18
TOAl ee H ----40
0 17
TDAl 81 H ~o
0 IS
TDIK 112 H
1'10
0 '"
SND

KI<TI 1'1009 H
KI<TI ADle H

~OICE'I't°I~~

TO I'll
TDAL
TDAL
TOAL
TDAl

--!f.o

87 H
8S
e5
e't
Ell

,...J:O"'Or28
0 27
H
- t O 28 o~
KKTI ADeS
KKTI ADII7 H~O P1No2'5
KKTI ADe& H~OSOC:f(021t
~2'3
KKTI ADe'S H---!O
7
XE~ 22
KKTI AD01t H -----;; 0
0 I
KI<TI ADIIl H~O
02e
KKTI AD02 H~O
KXTI A001 H~"
0 19
0
0 I8
TOAl Be H
TOAL 81 H~O
0 17
TDAl 02 H~O
0 1&
GND - ' . . j 0
0 I '5

H
H
H

--!-:!;

2K X 8
STATIC
RAM
2BISP
E'53

8 2K I>

H-

~ oSOCKor.2",'I;---1r-+-+_+-_ _+-+_ KKTI
~0
o~2~'l:---+--,

n'3'3M6'3M'3"n&2n'l8 M'32

(

1'1011 H

Og..

~O
~O 28 O~

n,l

""
i
~, .~." "
I:,:! i"" ~"'i ,>~. j
I'"

+'5YCR

~~~2~8+'-+~I-I-_+-+___ .5YHCR
~o

~ 0 PI N o~i;:;;;""~-1r-+_t-+_--+_t KIITI 1'10119 H

H-

n'+2

,...J: O"'Op'2~8;+-_+-+-+_+--_+-+- H!YHCR

H-

n'5&

M3&

~~5

r r f

n18n'+7

"19 "7 "& I "6en'tll

ns ..

8
7
&

,..
2
I
2l
22
1'3
21
20
18

KI<T't READ

H
M~7

TDAl 8S H
<
< 'fI TOAL 119 H
< -W TDAL III H
< -W TDAl I I H
TDAl
H
<
TDAl 1'3 H
< 15""
-:-t
TOAL
1'1
H
< -tT
TDAL 1'5 H
<
I~

--h;-

Me <
TOAl
MI <
TDAl
M2 <
TDAl
TDAl
M'3 <
M.. <
~ TOAl
M'5
~ TOAl
TDAl
M6 <
TOAl
n7 <

"""iT

It"
--t;;-

A8
AI
A2
Al
A'+
A'5
A&
1'17
A8
A9
AI0

:it

KXTI
KKTI
KXTI
KKTI
KKTI
KXTI
K)<TI
KXTI
KXTI
KKTI
KXTI

~REN

END

[C SEll

ADel H
ADB2 H
ADB'3 H
ADII~ H
AD6'5 H
A00S H
A007 H
AD08 H
ADe9 H
ADle H
ADII H

".,VMCR

KKT't IoIlB l
KXT't RERD l

KXTI ADe9 H
KXTI ADle H

KXT2 CSRRM l

TOAL
TOAL
TDAl
TDAl
TDAl

e7
8&
e5
elt
0l

2K X 8
STATIC'
RAn
21!l16P
El8

8
7

-- -~
'5
't
'3
2
I
2'3
22
19
~I

BB H
BI H

82 H
e'3
II ..
6'5
1!16
El7

H
H
H
H
H

All
AI
A2
A'3
A"
1'1'5
1'16
A7
1'18
0:>9
Ale
IoIREN
END

~IC SELl

H
H
H
H
H

+12V
MI

C13'
.'t7UF

C't

25V

'5ev

.8~7UF

.5YCR-------,------~------_r------T_------I

CI9
.e't7U
.,BY

C2f>
.e't7UF
OSllY

.. '5YNCR---,------_r------r_----_r------~--L-_.------,_----_;r_----._------r_----_r------r_----_r----_,-------r------r_----_r------~----_.--------------------_,------_r------r_----r_----_,
6ND--~------~----~----~-----L--~~--_r--L-----~_,--~~~-L--~~--,_--~_r--~~--~_,--~--~-L--

______L__ _ _ _

C29
.'I7UF
2'5Y

C'39
.'t7UF
2'5Y

GND TTL

__________________~_ _ _ __ L_ _ _ _~_ _ _ _~_ _ _ __ L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_ __ _ J

-12V - - ' - - - - - '

SHEET 5 OF 7

E-11

M21t

MI7 M2e
DLART
DCll9
KE'58
KKT'I READ L
KKT2 CSDLII L
KKT'+ ilLS L.
6NO
KXTI ADel H
KXTI ADII2 H
KXTI BCLR H
KXT2 DL.CLK H
KI<T6 RDATI H

[DALI!I]
[ DALll
[DAL.21
[ORL.'3]
[ORL.'+]
[OAL..,]
[DAL.61
[ DAL71
[ OAL81
[DAL9]
[DAL.III]
[OAL.II]
[DAL.12]
[PSRI][ DAL.I '3]
[DAL.I'+]
[ DAL.I.,]

Kiln DCLO H '39 TEST

tTHALT H

.,
'+

6
7
9
II
II
2
1'3
1'+
15
1&
17
8
9

[RT lCLK880 2'5
[RT ]CLK'511 '3'5
[ RTlCLI<611 '36
RCV[ IRQ] 2&
KM[T[ IRQ] 29
8
[SOl
[ BRKIRO]
[ 8RCLK]

DLART
DC'319
XE'59

GND

~TEVNT H

I
[ DALe]
2 RD
[DALI]
ENO
'3 IIR[L.B]
[ DAL.2]
[ DAL.'3]
21
[ DAL.'1]
aHD
58
[ DAL'5]
51
KXTI AD01 H 22
[DAL& ]
KXTI AD02 H 2'3 52
[ DAL7]
2'1
[ DAL8]
KXTI BCLR H n CLR
[ DAL9]
KXT2 DLCLK H
CLK
[DALl8 ]
27
[51 ]
[OALlI]
KKT£. ROAT2 H
[OALI2]
28 [ PBR I ] [ DALI '3 ]
[ OALI'I]
31
[DAL 1'5]
37
'38
[RT lCLK81!J1!J
[RT ]CLK'50
'39
KilT] DCLO H
TEST [ RTlCLK68
KIIT'+ READ L
KKT2 CSOU L
KKT'I ~LS L

TDAL I!II!I H
TDAL 01 H
TOAL. 82 H
TORL. 8'3 H
TDRL. e'+ H
TOAL. 11'5 H
TOAL. 116 H
TDAL 117 H
TDAL 08 H
TDAL 09 H
TOAL 18 H
TOAL. I I H
TDAL. 12 H
TDAL. I'3H
TOAL. 1'+ H
TDAL. 1'5 H
96'36
RDLI
KDL.I

M28 M27 MI9 M23

E'+2

j!l-+12Y

E'+2

!L--12V

RCV[ IRQ]
KMIT[ IRQ]

H
H

'3'+

TDAL ee H
TORL 81 H
TDRL. 02 H
TDRL 11'3 H
TDAL 0'1 H
TDRL 11'5 H
TDAL 11& H
TDAL 117 H
TDAL 08 H
TDAL 09 H
TDAL 10 H
TDAL. II H
TDAL 12 H
TDAL 1'3 H
TDAL 1'1 H
TDAL 1'5 H

2'5
3'5
'3&
26 ROL2 H
29 KDL2 H

[SO]

'30

[ BRKIRO]
[BRCLK]

'3'3
'3'1

KKTS XDATI P L

'3'3

'+
'5
6
7
8
9
10
II
12
1'3
1'1
1'5
1&
17
18
19

KXT6 XDAT2P L

REF E30 P[N I H
REF E'30
JI

KKT6 KDATIP L
GHD
RDATI N H

6ND
RDATIN H

KilTS XDAT2P L
GNO

KXT6 RDATI H

GND
RDAT2N H

KXT£. ROAT2 H

RDAT2H H

+12F
RS
12Ko

R7
12Ko

-12V
-12V

+'5VNCR
I

I MH002'

Ell

I +12V

I£.

i!1

'+7e"
KKT2 DLCLK H-+-,~~

1'"'-'0-- + I 2F

C'3
.'+7I'F
2'5V

D'+
D'S't

D'5
IN7'+9A
CI
.'t7UF
2'5V

D'3
D6''1

'I.'3V'S::

D2
D&',+

GND
-12V

SHEET 6 OF 7

E-13

M'51

Me;~ M'5;M'58M'5~

M't9

OCTAL
BUS
TRNVER

DUAL
QUAD
BUFFER

7'tl52~5

?~lS2't~

E'50

EGI

PSJ3 H

9 A7

PSJ" H

8 AG

PBJ2

B7 II
SG 12
B'5

2'5

PB7<]>
PBG<]> 2~
PB'5<]> 23
22
PB~ <]>
PB3<]> 21
20
PB2<]> 19
PB 1<]> 18
PB0<]>
PC7<]> 10
PCG<]> 1 I
PC'3<]> 12
PC't<]> 13
PC3<]> 17
Ie;
PC2¢ 1'5
PCI ¢ I ..
PC0<]>

XXT? PA7 H
KXT7 PAG H
KXT? PA'S H
KXT? PA't H
KKT? PA3 H
KXT? PAZ H
KXT? PAl H
KXT7 PAB H

PBJI H

'5 A3

PBJ0

KKT?

PB~

KXT7 pel

PCJ~

KXT7 PB2

I ..

KXT? PB'5

1'5
IS

BI I?
B0 18

Ria
laBn

) tbKKT7 PCf, H
KKT? PC~ H

KXT7 PCJI

6ND

Ie;

AI
A2T

1'12

8 1'13

KXT? PCB H

A;T 12

KXT7 PCJa H

B0T 9

KXT7 PCJ; H

-l< EN
II

KXT? PC; H

KXT? PC?

KKT7 PB7 H

+5VNCR

[

B2T '5

KKT7 PCJ'5 H

B2
B3T fL-

KXT7 PCJ2 H

D[R
EN

r KXT? PCJ?

1'5

KXT? PC'S H

KXT7 PB0 H

BIT 7

All
83

~ EN

KKT? PB7 H
KXT? PBG H
KXT? PB'5 H
KXT? PB~ H
KXT? PB3 H
KXT7 PB2 H
KXT? PBI H
KXT? PB0 H

XXT? PCJ2 H

KXT? PCJI H-

-::

PCJ~

KXT?

H-

KXT? PCJ;

KXT? PCJ0 H-

OCTAL
BUS
TRNVER
7'tL52't'5
EG2

PAJ7

PAJ0

PAJG H
PAJI H
PAJ'5

PORT

-XXI" SEL6 H

9 1'17
B

Bf, 12

KXT7 PA0 H

+11'1 OJ

KXT? PAG H

1'15

G 1'1'1
'5 1'13

+3VA

8't I"

KXT7 PAl H

B'3 15

XKT7 PA'S H

B2
PAJ2

XXT't READ H

KXT7 PA7 H

PBJf, H-

PBJI H

PBJ? H-

PBJZ

KXT1 PA2 H
KXT7 PM

PBJ3 H

PAJ; H-

PAJ~

PAJ2 H-

PAJ'S

PAJI H-

PAJ&

PAJ0 H-

PAJ? H

I ~KKT? PAROST H

7~
l5?~

E I7

-=-

+;VI'!

B0 18

H-

~T.f,
7'tlse
E't9

PAJ't H
XXT? PA'3 H

NOTE'

113

PAJ3 H
1)6
DG6't

PBJ0 H

KXT2 PI'!F1K L
KXTI 82CLR L

;

PBJ? H-

PBJ~

PCJ'3 H

XXT? PCJ7 H

PCJG H-

KXT7 PC? H
KXT7 PCG H
KXT7 PC'S H
KXT? PC't H
KXT? PC3 H
KXT7 PC2 H
KXT7 PCI H
KXT7 PCB H

M'52

"'IT

PCJG H

KXT? PSI H
KXT7 PBG

ABT

2 Ae

I'! 2

3 I'll

B3
82

PBJ7 H

GND

27
<]>7
28 <]>G
29 <]>'5
H
30
H 31
<]>'t DATA
113 H
32 ¢3
02 H
¢z
01 H n
'3'1 <]>1
00 H
¢e
07
0S
0'5
0't

PBJG

PA?<]> 37
PAG<]> 38
PA'5<]> 39
'+il
PA~<]>
PA3<]> I
PAZ<]> 32
PAl <]> 'I
PA0<]>

TDAl
TDAL
TOAL
TOAL
TOAL
TOAl
TOAl
TDAl

PBJ'5 H

KXT? PB3 H

I'! '5
B~

PROG
PRF/INF
8255
EGa

'XT? PC2 H

+3VR
6HD

I ~KXT7 PBRQST H
7'+
lS?'t
11 EIB
C 13 f-8·

12 D

READING THE 82'3'5 1'1-5 CONTROL REGISTER
\.jILL RESULT IN THE TRANSFER OF THE
ERRONEOUS DATA. ANY READ OR ~RITE OF
THE H[GH BHE ~[ lL RESULT [N AN ERRONEOUS
DATA TRANSFER [. E. ALL ONES.

NOTE' CONNECT TO PCS [N MODE 2.

KXT2 PBAK L

7~LSB

E3S

C22
~70p;
100V

SHEET 7 OF 7

E-15

APPENDIXF
GLOSSARY

ADOI-ADI5 - A I5-bit on-board address bus used to address memory and peripheral devices. Generated by two 8-bit latches that are loaded from the TDAL bus. See also BBS7.
AIO-AI7 - Input lines used by the microprocessor for interrupts and DMA requests.
ASPI - Microprocessor transaction that allows the microprocessor to recognize and accept pending interrupts or DMA requests.
Autobaud - Self-adjusting baud rates for SLUI only. Implemented by firmware in the optional MacroODT ROM.

BBS7 - LSI-ll bus signal indicating that the device addressed is in the I/O page.
BDAL 0-15 - Multiplexed data and address lines of the LSI-II bus connected through the backplane.
BDCOK - LSI-II bus signal that goes high 3 ms after dc power is applied and goes low 4 ms after ac
power is removed.
BDIN - LSI-ll bus data input strobe.
BDMGI - LSI-II bus signal from the BDMGO bus pin. It enters each module on the BDMGI pin and
exits on the BDMGO pin. It represents the bus grant for a DMA transaction.
BDMGO - See BDMGI.
BDMR - DMA request signal from the LSI-II bus.
BDOUT - LSI-II bus data output strobe.
BEVNT - LSI-II bus signal used to generate REVNT. Can be used to initiate an interrupt.
BHALT - LSI-II bus halt signal used for a priority 7 interrupt that vectors through location 140.
BINIT - LSI-II bus signal used to initialize all the devices on the bus.
BIRQ4 - LSI-II bus, level 4 priority interrupt request that is used to initiate the internal IRQ4 signal.
BKRQ - Internal control signal initiated by BHALT or BREAK detect from terminal.
BPOK - LSI-II bus signal that goes high 70 ms after BDCOK and goes low when ac power is lost.

F-I

BREAK - Initiated by pressing the BREAK key. Causes the transmission line to the SLU to be forced
to the space state (logical zero). This condition is sensed by SLUI and causes the SBC-ll/2I to generate BKRQ that can be used for interrupts.
BRPLY - Slave's acknowledge of an LSI-ll bus cycle.
BSACK - Acknowledges receipt of a DMA grant signal.
BSYNC - LSI-II bus cycle control signal.
BWTBT - LSI-ll bus write byte control signal.
CAS - An output from the microprocessor that acts as data strobe. Used for the read/write, DMA, and
ASPI transactions.
Condition codes - The least significant four bits of the processor status word that monitor the results of
the last instruction executed.
Configuration - Allows the user to select optional features of the module by inserting jumper wires.
Control and status register (CSR) - Internal register in an I/O interface that allows the program to
control and monitor the operation of that interface.
Control word - The data contained in the control register of the parallel I/O chip that determines the
configuration of the parallel I/O interface.
COUT - An output from the microprocessor clock that is asserted once during each microcycle.
CSKTA - The RAM/ROM socket set A chip select strobe.
CSKTB - The RAM/ROM socket set B chip select strobe.
CTMER - Time-out interrupt that has the same effect as HALT.
Cycle slip - This condition exists when the READY input is pulsed while RAS is asserted. It causes the
microprocessor to be idle, and no transactions occur.
DATI - LSI-II bus transaction that transfers sixteen bits of data from the slave to the master.
DATO - LSI-II bus transaction that transfers sixteen bits of data from the master to the slave.
DATO(B) ~ LSI-ll bus transaction that transfers eight bits of data from the master to the slave.
DMA - Direct memory access for transferring blocks of data without program intervention.
DMA transaction - A microprocessor transaction during which the microprocessor gives up bus mastership to another device for direct transfer of memory data.
EIA RS-232C - Electronics Industries Association serial line interface standard.
EIA RS-423 - Electronics Industries Association serial line interface standard.

F-2

Fetch/read - Microprocessor transaction that transfers data from memory or I/O into the microprocessor. The data may be an instruction (fetch) or an operand (read).
Firmware - The programs that reside in the PROM or ROM hardware.
FPLA - Field programmable logic array. Used to decode memory addresses.
HALT - The highest priority interrupt. Causes the microprocessor to go to the restart address and loads
the PSW with 340.
Handshaking protocol - The series of events used to establish data transfers.
IAK - Microprocessor transaction to acknowledge an interrupt and secure a vector from an on-board
location or from the LSI-II bus.
Interrupts - Interruption of the normal program execution to service an external request.
Interrupt protocol - Signal sequence required to initiate and service interrupts.
Interrupt vector - The location in which the address of the interrupt service routine is stored.
IRQ4 - See BIRQ4
KXTll-A2 - See Macro-ODT.
LSI-ll bus - An asynchronous bus that provides interconnections for LSI-II type modules.
Macro-ODT - The KXTII-A2 optional firmware for the SBC-II/21.
Maskable - A priority level that can be inhibited by loading the PSW with a higher priority code.
Memory mapping - Creating regions of memory via jumper configurations to determine the on-board
portions and the LSI-ll bus portions of memory.
Microcycle - The time necessary to execute one microinstruction. A transaction may use three or four
microcycles.
Mode register - An internal microprocessor register used to define the start and restart addresses.
Nibble - The upper or lower half of a byte that consists of four bits.
Nonmaskable - A priority level that is higher than the level selectable by the PSW.
NOP - A transaction that produces no useful output. It is used to introduce a delay or wait period.
Parallel I/O - Parallel data interface.
Parallel I/O handshaking - Control signals used to establish parallel data transfers.
PARQST - Parallel I/O port A interrupt request.
PBRQST - Parallel I/O port B interrupt request.

F-3

PI (priority in) - A microprocessor output signal used to strobe interrupt and DMA requests into the
microprocessor.
Power fail (PFAIL) - A nonmaskable interrupt caused by a power failure that causes the microprocessor to vector through location 24 to the power fail routine.
Priority - Bits 5-7 of the PSW. Used to define the priority level of the microprocessor.
PSW register - A microprocessor register that contains the processor status word (PSW).
PUP - An input to the microprocessor that controls the power-up sequence. When it is switched from
high to low, the microprocessor power-up sequence is initiated.
RAM - Random access memory defined as read/write memory.
RAS - Microprocessor output used as an address strobe in read/write, IAK, and DMA transactions.
RCSR - Serial line receiver control status register.
RDBR - Serial line receiver data buffer register.
RDLI - Serial line receiver number 1 interrupt signal.
RDL2 - Serial line receiver number 2 interrupt signal.
READY - Input to the microprocessor that causes cycle slips when pulsed.
Restart address - Jumper-selectable address that the microprocessor jumps to when executing a HALT
interrupt.
REVNT - See BEVNT.
ROM - Read only memory that cannot be written into.
R/ - WHB - A microprocessor output that is low for high byte write transactions and high for read
transactions.
R/ - WLB - A microprocessor output that is low for low byte write transactions and high for read
transactions.
RTI - Return from interrupt instruction.
SELO/SELI - Microprocessor outputs used to define the transaction being performed.
Serial I/O - Asynchronous serial line units for the transfer of serial data. SLU1 and SLU2 are two such
units used in the SBC-11/21.
Slew rate resistor - A resistor installed on the module that is compatible with the baud rate selected.
Split speed - A process that sends data at one baud rate and receives data at a different baud rate.
SBC-ll/21 does not support split speed operation.
Spurious halts - Halt conditions that are not programmed or introduced from an error condition.

F-4

Stack pointer - The register that contains the address of the last word stored on the stack.
Start address - A jumper-selectable address that the microprocessor goes to during power-up.
TCSR - Serial line transmitter control status register.
TDAL 0-15 - Internal on-board bus used for multiplexed data and address lines. See BDAL 0-15.
TDBR - Serial line transmitter data buffer register.
Trace bit - Bit 4 of the PSW that causes a trap to location 14.
Transaction - A sequence of microcycles used to complete a designated microprocessor function such
as read, write, ASPI, or IAK.
Tri-state - A high impedance condition of the bus lines.
Vector address - Memory location the microprocessor accesses for the address of the interrupt service
routine during an interrupt.
Wait state - A condition during which the microprocessor performs no useful transactions while waiting
for a response or data.
Wake up circuit - Holds BDCOK negated for 70 ms after dc power has been applied.

F-5

INDEX

ADOI-ADI5, 8-23
Addressing modes, 7-1
AIO-07, 8-15
Architecture, 5-1
ASPI,8-8
Autobaud, 6-1
B

Backplane, 2-22
BBS7, 9-4, 9-20
BCLR, 8-6, 8-28
BDCOK, 8-30, 9-17
BDIN, 8-32, 9-19
BDMGI, 9-8, 9-20
BDMGO, 9-8, 9-20
BDMR, 8-32,9-17
BDOUT, 8-37, 9-18
BEVNT, 2-9, 5-5,9-18
BHALT, 2-9, 5-5, 9-17
BINIT,9-20
BIRQ4, 2-11, 5-5, 9-19
BKRQ, 2-9, 5-5
Bootstrap, 4-6
BPOK, 8-30,9-17
BREAK,6-1
BRPLY, 9-18
BSACK,9-18
BSYNC, 9-19
Bus control, 8-37
Bus cycle, 9-3
Bus signals, 9-1, 9-3
BWTBT, 8-35, 9-19
Byte, 7-25, 8-26, 8-35

C
CAS, 8-5
Clock, 8-30
Clock control, 8-30

Condition codes, 7-28
Configuration, 2-3, 2-7
Control register, 6-22
Control word, 6-22, 6-23
COUT,8-6
CSKTA, 8-25, 8-26
CSKTB, 8-25, 8-26
CTMER, 2-9, 5-5
Cycle slip, 8-37
D

Data transfer, 9-3
DATI,9-5
DATa, 9-8
DATOB,9-8
Deferred addressing, 7-14
Direct addressing, 7-5
DMA, 5-4, 8-32, 9-8
DMA bus master, 9-8
DMA transaction, 9-8
Double operand address, 7-41

E
EIA RS-232C, 2-25
EIA RS-423, 2-25
F

Fetch/read, 8-6
Firmware, 4-1
FPLA,8-23
Framing error, 6-4
Functional block diagram, 8-2, 8-3
H

HALT, 5-5, 8-19
Handshaking protocol, 6-25
Hardware memory stack, 5-2

INDEX-l

IAK,8-8
Initialization, 8-1, 9-14
Instruction set, 7-22
Instruction set list, 7-26
Interrupts, 2-8, 8-14
Interrupt protocol, 9-12
Interrupt set/reset, 8-8, 8-15
Interrupt vector, 5-2, 8-16
Interrupt vector initialization, 5-2
IRQ4, 8-15

Parallel I/O, 6-7
Parallel I/O flowchart, 6-9
Parallel I/O handshaking, 6-25
Parallel I/O initialization, 6-25
PARQST, 5-5, 8-16
PBRQST, 5-5, 8-16
PC addressing, 7-17
PI (priority in), 8-5
Power fail (PFAIL), 8-22
Power fail routine, 8-22
PQwer-up/down protocol, 5-5, 8-30, 9-15
Ports A, B, C, 6-7
PPI programming priority, 6-7
Priority, 5-3
Program counter (PC), 7-17, 8-1
Programmable baud rates, 6-1
Programmable baud rates enable, 6-5
PSW register, 5-1
PUP, 8-4

J
Jumper wire, 2-1

K
KXT11-A2,4-1
L

Loopback connector, 2-28
LSI-II bus, 9-1

M
Macro-ODT,4-1
Macro-ODT commands, 4-2
Maskable, 5-2
Memory maps, 2-16, 5-6
Microcyc1e, 8-6
Microcyc1e slip, 8-17
Microprocessor, 8-1
Mode 0, 6-10
Mode 1,6-11
Mode 2, 6-18
Mode selection, 6-22

RAM, 2-16, 8-23
RAS, 8-5
RCSR,6-3
RDBR,6-3
RDL1, 5-5, 8-15, 8-26
RDL2, 5-5, 8-15, 8-26
Read,8-6
Read/write, 8-5, 8-35
READY, 8-5
Reply time-outs, 8-19
Restart address, 8-13
REVNT, 8-14, 8-16
ROM, 2-16, 8-25
R/-WHB,8-5
R/-WLB,8-5
RTI,7-64

N
S

Nibble, 6-11
Nonmaskable, 5-5
NOP, 8-8

o
Overrun error, 6-4

SELO /SEL 1, 8-5
Serial I/O, 2-12, 6-1, 8-26
Single operand address, 7-3
Slew rate resistor, 2-26
SLU1/SLU2, 6-1, 8-26
SLU programming, 6-1

INDEX-2

Split speed, 6-1
Spurious halts, 4-8
Stack pointer, 5-1
Standard factory configuration, 2-7
Start address, 2-8
Status register, 5-1

T
TCSR,6-1
TDAL, 8-1, 8-38
TDBR,6-1
Terminal problems, 4-8
TMER,8-37
TSYNC, 8-35
Transactions, 8-6
Transmitter interrupt enable, 6-5
Tristate, 8-8

u
Unsupported options, 3-4

v
Vector address, 5-4
Verification procedure, 2-28

w
Wait state, 8-37
Wake up circuit, 8-31
Write transaction, 8-8

x
XDL1, 5-5, 8-15, 8-26
XDL2, 5-5, 8-15, 8-26
XTLOjXTL1,8-30

INDEX-3

SBC-11/21 Single-Board Computer User's Guide
EK-SBCO 1-UG-OO 1

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