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Document:	01 1973AsmRef SysRef
Order Number:	XX-33537-78
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Pages:	201
Original Filename:	01_1973AsmRef_SysRef.pdf

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dlila]it[al1

aecsUsceno
assembly
language
handbook
third edition

system reference

link-10

Macro

ddt

monitor calls

utilities

decsuyscenio handbook series

2020020

decsystenmo

assembly
language

handbook
third edition
itional copies of this handbook may be ordered from:

Software Distribution Center, DEC, Maynard, Mass. 01754. Order Code: DEC-10-NRZC-D.

handbook series

The material in this handbook, including but not limited to instruction

times and operating speeds, is for information purposes and is subject
to change without notice.

Actual distribution of the software described in this specification will

be subject to terms and conditions to be announced at some future date

by Digital Equnpment Corporation.

DEC assumes no responsxblllty for the use or reliability of its software on
equnpment which is not supplied by DEC.

The software described in this manual is furnished to purchaser under a
license for use on a single computer system and can be copied (with inclusion of DEC’s copyright notlce) only for use in such system, except

as may otherwuse be provided in writing by DEC.

" The following are trademarks of

Digital Equipment Corporatiqn, Maynard, Massachusetts:

DEC FLIP CHIP
DIGITAL

PDP
FOCAL
COMPUTER LAB

O [NeEX
system reference [}
macro [

monitor calls [}

link-10 |

oo
utilities [

index [l

FOREWORD
This handbook is a collection of documents and sections of documents taken
from the DECsystem-10 SOFTWARE NOTEBOOKS (DEC-10-SYZB-D). It is
intended to be used by experienced programmers interested in writing and operating assembly-language programs on the DECsystem-10. The material in this
handbook is aimed at providing the information needed for user-mode programming.

Most documents in this handbook are reprinted without change from the DECsystem-10 Software Notebooks. However, the first document in the handbook,

the System Reference Manual, is an excerpt from the System Reference Manual in .
the Notebook set. This excerpt contains only the user-mode programming information needed by most assembly language programmers, and does not cover the

documentation related to the various peripheral devices. If additional information
is required, the reader is referred to the complete System Reference Manual in the
Software Notebooks. All DECsystem-10 installations have two copies of the note-

book set for reference.

The documents contained in this handbook reflect the following hardware and
versions of the software:

System Reference Manual - KA10 and K110 processors
MACRO - Version 47

Monitor Calls — 5.06 release
DDT - Version 34
LINK-10 - Version 1
CREF - Version 47
FILCOM - Version 20
FUDGE2 - Version 15
GLOB - Version 5A
The Assembly Language Handbook is one in the set of DECsystem-10 hand-

books. The other handbooks comprising this series are:
(1) the COBOL Language Handbook.
(2) the Mathematical Languages Handbook, which covers FORTRAN,
BASIC and ALGOL.
(3) the DECsystem-10 Users Handbook, which includes an introductory
section, the operating system commands, TECO, and PIP.

In addition to the above-mentioned handbooks, the following documentation is
also available:

(1) the COBOL Users Guide, which is aimed at COBOL users who wish
to become familiar with COBOL on the DECsystem-10.

(2) the System Reference Card, which includes the word formats, instructions, and conversion tables for the DECsystem-10.
(3) the Operating System Commands Reference Card, which describes the
commands, along with their formats, that are a part of the operating
system.

(4) the Monitor Calls Reference Card, which covers the programmed operators (UUOs), and their formats, that can be used with the monitor.
(5) the BASIC Language Reference Card, which includes the statements,
intrinsic functions, and edit and control commands of the DECsystem10 BASIC Language.

The handbooks, Users Guide, and reference cards may be ordered from:
Software Distribution Center
Digital Equipment Corporation
146 Main Street
Maynard, Massachusetts 01754

DECsystem-10

System Reference Manual

ORDER NO. DEC-10-HGAD-D FROM PROGRAM LIBRARY, MAYNARD, MASSACHUSETTS

PRICE $5.00

DIRECT COMMENTS CONCERNING THIS MANUAL TO SOFTWARE QUALITY CONTROL, MAYNARD, MASSACHUSETTS

DIGITAL EQUIPMENT CORPORATION

MAYNARD, MASSACHUSETTS

SYSTEM REFERENCE

-2

Instruction times, operating speeds and the like are
included here for reference only; they are not to be
taken as specifications.

First edition, May 1968
Three printings

Second edition, December 1971

This edition has been expanded to provide system reference information for
a DECsystem—10 with KA10 or KI10 central processors. The KI10 material
has been mcorporated into the text throughout.

Manufactured in the United States of America

December 1971
‘

SYSTEM REFERENCE

1.
1.1

INTRODUCTION
11

Number System
Floating point arithmetic

1.2

Instruction Format

Effective address calculation

1.3

1.4

Memory

15
16

KI10 memory allocation

KA 10 memory allocation

Programming Conventions

CENTRAL PROCESSOR

19
23

2.1

Half Word Data Transmission

2.2

Full Word Data Transmission

Move instructions

Pushdown list

2.3

Byte Manipulation

2.4

Logic

Shift and rotate

2.5

Fixed Point Arithmetic
Arithmetic shifting .

48
52

2.6

Floating Point Arithmetic

Scaling

Number conversion

Single precision with rounding

Single precision without rounding

Doublg precision operations

2.7

Arithmetic Testing

2.8

Logical Testing and Modification

2.9

Program Control

2.10

Unimplemented Operations

2.11

Programming Examples
Double precision floating point

SYSTEM REFERENCE

-4~

2.12

Input-Output
Readin mode

96
101

Console-program communications

102

2.13

Priority Interrupt

103

2.14

Trapping and Processor Conditions

111

Overflow trapping
KI10 processor conditions
KA10 processor conditions

111
112
115

2.15

KI10 Modes
Paging
Page failure

Monitor programming
Executive XCT
2.16

124
127

KA 10 Modes
User programming

129
131

Monitor programming

2.17

Real Time Clock DK 10

2.18

KA 10 Operation

131

132
135

Indicators

Operating keys

K110 Operation

136

‘

Operating switches
2.19

117
118
122

138

140

(Not available at this time)

APPENDICES

~ Instruction and Device Mnemonics

Numeric listing

147
149

Alphabetic listing

152

Device mnemonics

Algebraic representation

156

157

In-out Codes
Teletype code
Card codes

167
168
172

Timing
KA 10 timing
KI10 timing

175
176

KA 10 Algorithms
Fixed point algorithms

(Not available at this time)
179
180

Floating point algorithms

Processor Compatibility

Indicator Panels

Bit Assignments

185

(Not available at this time)

(Available in the System Reference Manual
published as a part of the DECsystem-10

Software Notebooks.)
191

SYSTEM REFERENCE

1
Introduction

The DECsystem—10 is a general purpose, stored program computing system
that includes at least one PDP—10 central processor, a memory, and a variety
of peripheral equipment such as paper tape reader and punch, teletypewriter,
card reader and punch, line printer, DECtape, magnetic tape, disk, drum,
display and data communications equipment. Each central processor is the
control unit for an entire large-scale subsystem, in which it is connected by
an in-out bus to its own peripheral equipment and by a memory bus to one or

more memory units in a main memory, some of whose units may be shared
by several processors. Within the subsystem the central processor governs

all peripheral equipment, sequences the program, and performs all arithmetic,
logical and data handling operations. Besides central processors, there are
also direct-access processors, which have much morelimited program capability and serve to connect large, fast peripheral devices to memory bypassing
the central processor. Every direct-access processor is connected to the in-out

bus of some central processoi', to which it appears as an in-out device; the

direct-access processor is also connected to memory by its own memory bus,
and to its peripheral equipment by a device bus. The DECsystem~10 may
also contain peripheral subsystems, such as for data communications, which
are themselves based on small computers; such a subsystem in toto is connected to a PDP-10 in-out bus and is treated by the PDP-10 as a peripheral
device. Unless otherwise specified, the words “‘processor” and ‘‘central processor’” refer to the large-scale PDP-10 central processor, and ““in-out bus”
refers to the bus from the central processor to its peripheral equipment. A
direct-access processor and the bus to its peripheral equipment are all always
referred to by their names, eg the DF10 data channel and its channel bus
(often a direct-access processor and device control are a single unit).

At present there are two types of PDP-10 central processors, the KA10

and the KI10. The latter is faster and more powerful, having a somewhat
larger instruction repertoire including double precision floating point. Both

~ processors handle words of thirty-six bits, which are stored in a memory
whose maximum capacity depends upon the addressing capability of the
processor. Internally both processors use 18-bit addresses and can thus
reference 262,144 word locations in memory. This is the total addressing
capability of the KA10, but in the KI10 it is only the virtual address space
available to a single program. Paging hardware supplies four additional
address bits to map pages in the program virtual address space into pages
anywhere in a physical memory that is sixteen times as large. Thus for
a number of different programs, the processor actually has access to a
1-1

Confusion could result only
in a chapter dealing with a
subsystem.
small-computer
Here the small processor is
usually referred to by its

name (PDP-8, PDP-11) and
the words “computer” and
“memory”’ refer to the small
computer. To differentiate,
the PDP-10 is referred to by
its name or as the “DECsystem—10 central processor”,
and the large scale memory
connected to the PDP-10
memory bus is referred to as
“DECsystem—10 main memory”.

SYSTEM REFERENCE

-6~

1-2

INTRODUCTION -

physical memory with a capacity of 4,194,304 words.

Storage in memory

is usually in the form of 37-bit words, the extra bit producing odd parity

for the word.

The bits of a word are numbered 0-35, left to right (most
significant to least significant), as are the bits in the registers that handle
the words.
The processor can handle half words, wherein the left half
comprises bits 0—17, the right half, bits 18-35.

There is also hardware

for byte manipulation — a byte is any contiguous set ‘of bits within a word.
KA10 registers that hold addresses have eighteen bits, numbered 18-35

according to the position of an address in a word.

KI10 internal address
registers have eighteen bits, but a register that must supply a complete
address to physical memory has twenty-two bits (numbered 14-35). Words
are used either as computer instructions in the program, as addresses, or as
operands (data for the program).

Of the internal registers shown
in the illustration on the next page, only

PC, the 18-bit program counter, is directly relevant to the programmer. The
processor performs a program by executing instructions retrieved from the

locations addressed by PC. At the beginning of each instruction PC is incremented by one so that it normally contains an address one greater than the

location of the current instruction. Sequential program flow is altered by

changing the contents of PC, either by incrementing it an extra time in a
skip instruction or by replacing its contents with the value specified by a

jump

instruction. Also

of importance to the programmer are the sense

switches and the 36-bit data switch register DS on the processor console:

through these switches the program can read information supplied by the

operator. The processor also contains flags that detect various types of
errors, including several types of overflow in arithmetic and pushdown opera-

tions, and provide other information of interest to the programmer.

The processor has other registers but the programmer is not usually concerned with them except when manually stepping through a program to
debug it. By means of the address switch register AS, the operator can
examine the contents of, or deposit information into, any memory location;
stop or interrupt the program whenever a particular location is referenced;

and through AS the operator can supply a starting address for the program.
Through the memory indicators MI the program can display data for the
operator.

The instruction register IR contains the left half of the current

instruction word, ie all but the address part. The memory address register

MA supplies the address for every memory access. The heart of the processor is the arithmetic logic, principally the 36-bit arithmetic register AR.
This register takes part in all arithmetic, logical and data handling operations;
all data transfers to and from memory, peripheral equipment and console are

made via AR. Associated with AR are an extremely fast full adder, a buffer
register BR that holds a second operand in many arithmetic and logical
instructions, a multiplier-quotient register MQ that serves primarily as an
extension of AR for handling double length operands, and smaller registers
that handle floating point exponents and control shift operations and byte
manipulation.

the

KI10,

AR and

the

adder each have a 28-bit left

extension for handling double precision floating point numbers.

From the point of view of the programmer however the arithmetic logic
can be regarded as a black box. It performs almost all of the operations

SYSTEM REFERENCE

-7-

1-3

CORE MEMORY

CORE MEMORY
3

CENTRAL

MEMORY BUS

[

—_——

PROCESSOR

FAST

MEMORY
X 36
16

4
;

18
3

‘

ARITHMETIC

PC18

BR, MQ)
(AR,

IN- OUT BUS

LOGIC

-—

PRIORITY

PAPER TAPE

READER

‘

[

INTERRUPT

PAPER TAPE

"PUNCH

~ TELETYPE

DECSYSTEM-10 SIMPLIFIED

necessary for the execution of a program, but it never retains any
information from one instruction to the next. Computations performed in
the black box either affect control elements such as PC and the flags, or
produce results that are always sent to memory and must be retrieved by the

processor if they are to be used as operands in other instructions.
An instruction word has only one 18-bit address field for addressing any

location throughout all of the virtual address space. But most instructions
have two 4-bit fields for addressing the first sixteen memory locations. Any
instruction that requires a second operand has an accumulator address field,

SYSTEM REFERENCE

-8-

INTRODUCTION

1-4

which can address one of these sixteen locations as an accumulator; in other
words as though it were a result held over in the processor from some
previous instruction (the programmer usually has a choice of whether the

result of the instruction will go to the location addressed as an accumulator
or

that

addressed

the

18-bit

address

field,

or to both). Every

instruction has a 4-bit index register address field, which can address fifteen

of these locations for use as index registers in modifying the 18-bit memory
address (a zero index register address specifies no indexing). Although all
computations on both operands and addresses are performed in the single

arithmetic register AR, the computer actually has sixteen accumulators,

fifteen of which can double as index registers. The factor that determines
whether one of the first sixteen locations in memory is an accumulator or an
index register is not the information it contains nor how its contents are

used, but rather how the location is addressed. These first sixteen memory

locations are not actually in core memory, but are rather in a fast solid state
The KI10 actually has four
fast memory blocks, but only
one of these is available to a

program at any given time.

memory contained in the processor. This allows much quicker access to
these locations whether they are addressed as accumulators, index registers
or

ordinary

memory locations. They

can even be addressed

from the

| program counter, gaining faster execution for a short but oft-repeated
subroutine.

- Besides the registers that enter into the regular execution of the program

and its instructions, the processor has a priority interrupt system and
equipment

facilitate

time

sharing. The

interrupt

system

facilitates

processor control of the peripheral equipment by means of a number of

priority-ordered

channels over which external signals may interrupt the

normal program flow. The processor acknowledges an interrupt request by
executing the instruction contained in a particular location for the channel
or

doing

some

special

operation

specified

the

device

(such

incrementing the contents of a memory location). Assignment of channels
to devices is entirely under program control. One of the devices to which
the program can assign a channel is the processor itself, allowing internal

conditions such as overflow or a parity error to signal the program.
Time Sharing. Inherent in the basic machine hardware are restrictions that
apply universally: only certain instructions can be used to respond to a
priority interrupt, and certain memory locations have predefined uses.

But

above this fundamental level, the time share hardware provides for different
modes of processor operation and establishes certain instruction restrictions

and memory restrictions so that the processor can handle a number of user
programs (programs run in user mode) without their interfering with one

another. The memory restrictions are dependent to a great extent on the
processor, but the instruction restrictions are not, and these are relatively
obvious: a program that is sharing the system with others cannot usually be
The KI10 allows unrestricted

allowed

in-out with a limited number

arbitrarily. A program that runs in executive mode — the Monitor — is

devices

for

time applications.

special

real

responsible

halt
for

the

processor

operate

scheduling user programs,

the

in-out

equipment

servicing interrupts, handling

input-output needs, and taking action when control is returned to it from a
user program.

Any violation of an instruction or memory restriction by a

user transfers control back to the Monitor. Dedication of the entire facility
to a single purpose, in other words with only one user, is equivalent to

SYSTEM REFERENCE

operation in exectitive mode (specifically kernel mode in the KI110).

The KA10 has thie two modes discussed above, user and executive. It also

has protection and relocation hardware to confine the user virtual address
space within a particular range, and to relocate user memory references to

the appropriate area in physical core. A user ordinarily has access to two
separate core areas, one of which may be write-protected, ie the user cannot
alter its contents.

The KI10 has paging hardware for the mapping of pages from the limited
virtual address space into pages anywhere in physical memory. A page map
for each program specifies not only the.correspondence from virtual address
to physical address, but also whether an individual page is accessible or not,

alterable or not, and public or concealed. Both user and executive modes are
subdivided according to whether the program is running in a public area or a
concealed area. Within user mode these are the public and concealed modes;

within executive mode, the supervisor and kernel modes. A program in

concealed mode can refererice all of accessible user memory, but the public

program cannot reference the concealed area except to transfer control into
it at certain legitimate entry points.

In kernel mode the Monitor handles the in-out for the system, handles

priority interrupts, constructs page maps, and performs those functions that

affect all users.

This mode has no instruction restrictions and the program

can even address some of memory directly (ie unpaged); in the paged address
space, individual pages may be restricted as inaccessible or write-protected,

but it is the kernel mode program that establishes these restrictions. In
supervisor mode the Monitor handles the general management of the system
and those functions that affect only one user at a time. This mode has
the same instruction and memory restrictions as user mode,

essentially

although the supervisor mode program can read, but not alter, the concealed
areas; in this way the kernel mode Monitor supplies the supervisor program
with information the latter cannot alter (even though the information is not

write-protected from the kernel program).

In either mode the Monitor

automatically uses fast memory block O (the hardware requires this).

The

user

time

kernel program is responsible for assigning fast memory blocks to the various
programs:

ordinarily

blocks

and

are

for

special

real

applications, and block 1 is assigned to all other users.

The illustration on the next page shows a typical layout of the virtual
address space for the various modes. The space is 256K, made up of 512
pages numbered 0-777 octal. Any program can address locations 0—17 as
these are in a fast memory block and are completely unrestricted (although

the same addresses may be in different blocks for different programs). The
public mode user program operates in the public area, part of which may be
write-protected. The
concealed

areas

public

except

program cannot access any locations in the

fetch instructions from prescribed entry
points. The concealed mode user program has access to both public and

concealed areas, but it cannot alter any write-protected location whether
public or concealed,

and

fetching an

instruction

automatically returns the processor to public mode.

from

the

public area

;

The supervisor mode program is confined within the paged area of the
address space, pages 340 and above. Part of the public area in this space may

The concealed area would ordinarily be used for proprie-

tary programs that the user
can call but cannot read or

alter.

3F 3 @ x =

-s~ [<<t

o
w

[&1
|TR)

SYSTEM REFERENCE

-11-

§1.1

NUMBER SYSTEM

be write-protected, but the program can read information in the concealed
areas — it cannot alter any location in a concealed area whether that area is
write-protected or not. Pages 340-377 constitute the per-process area, which

contains

information

accompanies

the

specific

user

page

individual

map. In

users

other words

and

whose

mapping

the physical memory

corresponding to these virtual pages can be changed simply by switching

from one user to another, rather than the Monitor changing its own page

map. The kernel mode program can access all of the unpaged area without
restriction and can reference all of the accessible paged area, both public and
concealed, with the usual restriction that it cannot alter a write-protected

area. As in the case of concealed user mode, fetching an instruction from a
public area returns control to supervisor mode.

1.1

NUMBER SYSTEM

The program can interpret a data word as a 36-digit, unsigned binary number, or the left and right halves of a word can be taken as separate 18-bit

numbers.

The PDP-10 repertoire includes instructions that effectively add

or subtract one from both halves of a word, so the right half can be used for
address modification when the word is addressed as an index register, while

the left half is used to keep a control count.
The standard arithmetic instructions in the PDP-10 use twos compleIn a word used as a

ment, fixed point conventions to do binary arithmetic.

number, bit O (the leftmost bit) represents the sign, 0 for positive, 1 for
negative.

In a positive number the remaining 35 bits are the magnitude in
ordinary binary notation. The negative of a number is obtained by taking its
twos complement.

If x is an n-digit binary number, its twos complement is

2" —x, and its ones complement is (2" — 1) — x, or equivalently (2" —x) — 1.
Subtracting a number from 2" -1 (je, from all 1s) is equivalent to performing the logical complement, ie changing all Os to 1s and all 1s to Os. Therefore, to

form

the twos complement one takes the logical complement

(usually referred to merely as the complement) of the entire word including
the sign, and adds 1 to the result. In a negative number the sign bit is 1, and

the remaining bits are the twos complement of the magnitude.

+153,, = +2315 =[000 000 000 000 000 000 000 000 000 010 011 001]
0

—-153,0 = —231; =U11 111111 111 111 111 111 111 111 101 lOOllfl
0

Zero is represented by a word containing all 0s. Complementing this
number produces all 1s, and adding 1 to that produces all Os again. Hence
there is only one zero representation and its sign is positive.

Since the

numbers are symmetrical in magnitude about a single zero representation, all
even numbers both positive and negative end in 0, all odd numbers in 1 (a

SYSTEM REFERENCE

-12-

1-8

INTRODUCTION
number all

1s represents —1).

81.1

But since there are the same number of

positive and negative numbers and zero is positive, there is one more negative
number than there are nonzero positive numbers. This is the most negative
number and it cannot be produced by negating any positive number (its

octal representation is 400000 0000005

and its magnitude is one greater

than the largest positive number).
If ones complements were used for negatives one could read a negative
number by

attaching significance

complement

notation

each

negative

the Os instead of the
number

one

ls. In twos

greater

than

the

complement of the positive number of the same magnitude, so one can read
a negative number by attaching significance to the rightmost 1 and attaching

significance to

the

Os at the left of it (the negative number of largest

magnitude has a 1 in only the sign position). In a negative integer, 1s may be
discarded at the left, just as leading Os may be dropped in a positive
integer.

In a negative fraction, Os may be discarded at the right.

So long as

only Os are discarded, the number remains in twos complement form because

it still has a 1 that possesses significance; but if a portion including the
rightmost 1 is discarded, the remaining part of the fraction is now a ones

Multiplication produces a
double length product, and

complement.

the programmer must remem-

must adopt a point convention and shift the magnitude of the result to con-

ber that discarding the low
order part of a double length
negative leaves the high order
part in correct twos complement form only if the low

order part is null.

The computer does not keep track of a binary point — the programmer

form to the convention used.

Two common conventions are to regard a =

number as an integer (binary point at the right) or as a proper fraction

(binary point at the left); in these two cases the range of numbers repre-

sented by a single word is —23% to 23— 1 or —1 to 1 — 273. Since multiplication and division make use of double length numbers, there are special
instructions for performing these operations with integral operands.
The format for double length fixed point numbers is just an extension of
the single length format. The magnitude (or its twos complement) is the
70-bit string in bits 1-35 of the high and low order words.

Bit 0 of the high

order word is the sign, and bit O of the low order word is 0. The range for
double length integers and proper fractions is thus —27° to 27 — 1 and —1 to
1—-2779,
‘
‘
Floating Point Arithmetic. The KI10 has hardware for processing single
and double precision floating point numbers; the KA10 can generally process
only single precision numbers, although the hardware does include features
that facilitate double precision arithmetic by software routines. The same
format is used for a single precision number and the high order word of a

double precision number.

A floating point instruction interprets bit O as the

sign, but interprets the rest of the word as an 8-bit exponent and a 27-bit

fraction. For a positive number the sign is 0, as before.

But the contents of

bits 9-35 are now interpreted only as a binary fraction, and the contents of
bits

1-8

are

interpreted

an integral exponent in excess

128 (200;)

code.

Exponents from —128 to +127 are therefore represented by the
binary equivalents of 0 to 255 (0-3774). Floating point zero and negatives
are represented in exactly the same way as in fixed point: zero by a word

containing all Os, a negative by the twos complement.

A negative number

has a 1 for its sign and the twos complement of the fraction, but since every
fraction must ordinarily contain a 1 unless the entire number is zero (see

-13-

§1.1

SYSTEM REFERENCE

NUMBER SYSTEM

1-9

below), it has the ones complement of the exponent code in bits 1-8. Since
the exponent is in excess 128 code, an actual exponent x is represented in a
positive

number

x+ 128,

negative

number by

127 —x.

The

programmer, however, need not be concerned with these representations as

the hardware compensates automatically. Eg, for the instruction that scales
the exponent, the hardware interprets the integral scale factor in standard
twos complement form but produces the correct ones complement result for

the exponent.

+153,,

4231y

+.462,X2%

[ofto 001 000[100 110 010 000 000 000 000 000 000
01

~153,,

=231y

—.462,X28

101 110 111]011 001 110 000 000 000 000 000 000}
01

Except in special cases the floating point instructions assume that all
nonzero operands are normalized, and they normalize a nonzero result. A

floating point number is considered normalized if the magnitude of the

fraction is greater than or equal to %2 and less than 1. The hardware may not
give

the

correct

result if the program

supplies an operand that is not

normalized or that has a zero fraction with a nonzero exponent.

Single

precision

floating

magnitude of 2 to

point

1 —27%7.

numbers have a fractional range in
Increasing the length of a number to two

words

does not significantly change the range but rather increases the
precision; in any format the magnitude range of the fraction is % to 1

decreased by the value of the least significant bit.

In all formats the

exponent range is —128 to +127.

The

~applies

precaution

most

about truncation given for fixed point multiplication

floating point operations as they produce extra length

results; but here the programmer may request rounding, which automatically
restores the high order part to twos complement form if it is negative.

single

precision

division the two

words of the result are quotient and

remainder, but in the other operations they form a double length number

which is stored in two accumulators if the instruction is executed in “long”

mode. (Long mode division uses a double length dividend.) A double length
number used

precision format.

the single

precision instructions is in software double

As such it contains a 54-bit fraction, half of which is in

bits 9-35 of each word.

The sign and exponent are in bits 0 and 1-8

respectively

containing

of the

word

the

significant half, and the

standard twos complement is used to form the negative of the entire 63-bit
string.

In the remaining part of the less significant word, bit 0 is 0, and bits

1-8 contain a number 27 less than the exponent, but this is expressed in
positive form even though bits 9-35 may be part of a negative fraction. Eg

the

number

2!® +27'8

has this two-word

representation

software

SYSTEM REFERENCE

-14-

1-10

INTRODUCTION

§1.2

double precision format:

(0]10 010 011100 000 000 000 000 000 000 000 000)]
01

001 111 000]000 00O 000 100 000 000 000 000 000]
01

whereas its negative is

101 101 100j011 111 111 111 111 111 111 111 111}
01

001 111 000{111 111 111 100 000 000 000 000 000]
01

The double precision floating point
- instructions use a more straightforward double length format with greater precision than is allowed by the
software format.

For these instructions all operands and results are double

length, and all instructions except division calculate a triple length answer,
which is rounded to double length with the appropriate adjustment for a .
twos complement negative.

In hardware double precision format the high

order word is the same as a single precision number, and bits 1-35 of the
low order word are simply an extension of the fraction, which is now
sixty-two bits. Bit O is ignored. The number used above as an example of

software double precision format has this representation in hardware format:

l0[10 010 011/100 000 000 000 000 000 000 000 000|
01

[0[00 000 000 010 000 000 000 000 000 000 000 000]
01

and its negative is

MOI 101 100]011 111111 111 111 111 111 111 111]
01

(0[11 111 111 110 000 000 000 000 000 000 000 000]
01

1.2

INSTRUCTION FORMAT

In all but the input-output instructions, the nine high order bits (0—8)
specify the operation, and bits 9—12 usually address an accumulator but are
sometimes used for special control purposes, such as addressing flags.

The

SYSTEM REFERENCE

-15-

8§1.2

INSTRUCTION FORMAT

rest of the instruction word usually supplies information for calculating
the
effective address, which is the actual address used to fetch the operand or
alter program flow. Bit 13 specifies the type of addressing, bits 14—17 spec-

ify an index register for use in address modification, and the remaining
eighteen bits (18-35) address a memory location. The instruction codes
ADDRESS TYPE

ACCUMULATOR

INDEX REGISTER

ADDRESS

INSTRUCTION CODE l
0

/ ADDRESS
i

l l

121314

MEMORY ADDRESS

1718

BASIC INSTRUCTION FORMAT

that are not assigned as specific instriictions are performed by the processor

-as so-called ‘“‘unimplemented operationsTM.

‘,
An input-output instruction is designated by three 1s in bits 0-2. Bits
3=9 address the in-out device to be used in executing the instruction, and

bits 10-12 specify the operation. The rest of the word is the same as in
other instructions.
ADDRESS TYPE -

INSTRUCTION
7

I DEVICE CODE I

l I

910

[}

121314

the

user operations” or UUOs (a
mnemonic that means nothing

to the assembler). Half of
these are for the local use of a

other

]
'

1718

(LUUOs)

half are

nication

MEMORY ADDRESS

unimplemented

specified as “unimplemented

program

INDEX REGISTER
/ ADDRESS

CODE

Among

operations are some that are

with

(MUUOs).

and

the

for commuthe

Monitor

In general, unas-

signed codes act like MUUO:.

IN-OUT INSTRUCTION FORMAT

Effective Address Calculation. Bits 13~35 have the same format in every

instruction whether it addresses a memory location or not.

7l x
1314

]

Bit 13 is the

1718

indirect bit, bits 1417 are the index register address, and if the instruction
must

reference

memory,

bits

18-35

are

the

memory

address

The

effective address E of the instruction depends on the values of
7, X and Y.
If X is nonzero, the contents of index register X are added to Y to produce a

modified address. If I is 0, addressing is direct, and the modified address is
the effective address used in the execution of the instruction; if I is 1,
addressing is indirect, and the processor retrieves another address word from

the location specified by the modified address already determined. This new
word is processed in exactly the same marner: X and Y determine the
effective address if 7 is 0, otherwise théy are used for yet another level of

address retrieval. This process continues until some referenced location is
found with a 0 in bit 13; the 18-bit number calculated from the X and Y
parts of this location is the effective address E.
The calculation outlined above is carried out for every instructio
n even
if it need not address a memory location. If the indirect bit
in the instruc-

On the other hand, please note

that this calculation is carried

SYSTEM REFERENCE

-1€-

1-12

INTRODUCTION

§1.3

out only for words indicated

tion word is 0 and no memory reference is necessary, then Y is not an ad-

in the text as having the for-

dress.

mat shown. Do not assume
that the procedure is used for
any miscellaneous pointer sim-_

ply because it happens to contain an address [see page G2].

It may be a mask in some kind of test instruction, conditions to be

sent to an in-out device, or part of it may be the number of places to shift in

a shift or rotate instruction or the scale factor in a floating scale instruction.
Even when modified by an index register, bits 18—-35 do not contain an address when 7 is 0.

But when [ is 1, the number determined from bits 14-35

is an indirect address no matter what type of information the instruction

requires, and the word retrieved in any step of the calculation contains an
indirect address so long as 7 remains 1. When a location is found in which 7
is 0, bits 18-35 (perhaps modified by an index register) contain the desired

effective mask, effective conditions, effective shift number, or effective scale
factor.

Many of the instructions that usually reference memory for an oper-

and even have an “immediate” mode in which the result of the effective
address calculation is itself used as a half word operand instead of a word
taken from the memory location it addresses.
The important thing for the programmer to remember is that the same

calculation is carried out for every instruction regardless of the type of information that must be specified for its execution, or even if the result is
ignored. In the discussion of any instruction, E refers to the actual quantity

derived from /, X and Y and used in the execution of the instruction, be it
the entire half word as in the case of an address, immediate operand, mask or
conditions, or only part of it as in a shift number or scale factor.

1.3 MEMORY
The internal timing for each in-out device and each memory is entirely
independent

of the

central processor.

Because

core memory readout is

destructive, every word read must be written back in unless new information

is to take its place.
time.

But the processor need never wait the entire cycle

To read, it waits only until the information is available and then

continues its operations while the memory performs the write portion of the
cycle; to write, it waits only until the data is accepted, and the memory then

performs an entire cycle to clear and write. To save time in an instruction
that fetches an operand and then writes new data into the same location, the
memory executes a

read-modify-write cycle in which it performs only the

read part initially and then completes the cycle when the processor supplies

the new data. This procedure is not used however in a lengthy instruction
(such as multiply or divide), which would tie up a memory that may be
needed by some other processor.

Such instructions instead request separate

read and write access. The KI10 further increases the speed of memory
operation by overlapping memory cycles. Eg it can start one memory to

read a word before receiving a word previously requested from a different

memory.

Access times for the accumulator-index register locations are decreased

considerably by substitution of a fast memory (contained in the processor)

for the first sixteen core locations.

Readout is nondestructive, so the fast

memory has no basic cycle: the processor reads a word directly, but to write

it must first clear the location and then load it.

-17-

SYSTEM REFERENCE

§1.3

MEMORY

The following table gives the characteristics of the various memories.
Modify completion is the time to finish a read-modify-write cycle after the

processor supplies the new data.

Times are in microseconds and include the

delay introduced by ten feet (three meters) of cable. Fast memory times are

for referencing as a memory location (18-bit address); when a fast memory
location is addressed as an accumulator or index register, the access time is

usually considerably shorter. The size of the MD10 can be increased in units

of 32K up to 128K.

161 Core Memory

MB10 Core Memory

Write

Access

Cycle

2.5

163 Core Memory
164 Core Memory

Read
Access

.94
}

.60

Modify
Completion

Size

.49

4.7

2.69

16K

1.8

1.33

16K

.20

1.65

MA10 Core Memory

.61

.20

1.00

MD10 Core Memory

16K

.83

.33

1.8

1.23

32-128K

ME10 Core Memory

.61

.20

1.00

.65

16K

KA10 Fast Memory

. KI10 Fast Memory

From the simple hardware addressing point of view, the entire memory is

-a set of contiguous locations whose addresses range from zero to a maximum

dependent upon the capacity of the particular installation. In a system with
the greatest possible capacity, the largest KA10 address is octal 7771777,
decimal
262,143;
the
largest
KI10
address is
17777777, decimal

4,194,303. (Addresses are always in octal notation unless otherwise
specified.) But the whole memory would usually be made up of a number of
core memories of different capacities as listed above.

Hence a given address

actually selects a particular memory and a specific location within it.
-

For a

16K memory with 18-bit addressing, the high order four address bits select

the memory, the remaining fourteen bits address a single location in it;
a 32K memory takes three bits, leaving fifteen for the

selecting

location. The times given above assume the addressed memory is idle when
access is requested.

cycle

end,

memories

another. All

the

To avoid waiting for a previously requested memory

program

taking

memories

can

make

instructions

can

consecutive

from

one

be interleaved

requests to different

memory

pairs in

and

*Add .1 in a multiprocessor system.

data

from

such a way that

consecutive addresses actually alternate between the two memories in the
pair (thus increasing the probability that consecutive references are to

different
memories). Appropriate
switch
settings
at
the
memories
interchange the least significant address bits in the memory selection and

location parts, so that in any two memories numbered » and n + 1 where » is
even, all even addresses are locations in the first memory, all odd addresses

are locations in the second. Hence memories O and 1 can be interleaved as
can 6 and 7, but not 3 and 4 or 5 and 7. Some memories can be interleaved

in contiguous groups of four, where the number of the first memory in the

SYSTEM REFERENCE

-13-

§1.3

INTRODUCTION

group is divisible by four (eg memories 0—3 or 14-17). In this case all
addresses ending in O or 4 reference the first memory in the group, all ending
in 1 or S reference the second, and so forth.

In terms of the virtual address space (the addresses that can be specified
within the limits of the instruction format) or the subset of it that is
accessible to a user, the situation may be quite different. In the KA10 the

user

program

has

a continuous address space beginning at 0, or two

program

continuous spaces beginning at 0 and 400000. In the KI10 the possible

can always address locations
0-337777 as these are unpaged. Virtual pages 340 and
above are mapped.

program address space is the set of all 18-bit addresses just as in the KA10,
but which addresses a program can actually use depends entirely upon which

The

kernel

mode

of the 512 virtual pages (512 words per page) are accessible to it. For a
so-called ‘“‘small user”, the accessible space must lie within the ranges
0-37777 and 400000-437777. In any event all programs have access to fast
memory, whether as accumulators, index registers or ordinary memory
references (ie addresses 0—17 are never restricted or relocated).

‘

KI10 Memory Allocation. The KI10 hardware defines the use of certain
memory locations,

but almost all of these are relative to pages whose

physical location is specified by the Monitor. The only physical locations
uniquely defined by the hardware are those in fast memory, whose addresses

are the same for all programs: location O holds a pointer word during a

bootstrap readin, 0—17 can be addressed as accumulators, and 1-17 can be

addressed as index registers. The only addresses uniquely specified in the '
user virtual space are for user local UUOs — locations 40 and 41.
All other addresses defined by the hardware, for use in page mapping,
responding to priority interrupts, or other hardware-oriented situations, are
to locations within a page specified by the Monitor for a particular user

(including itself). For each user the Monitor keeps a process table, which
The Monitor keeps a user
process table for each user

must begin at location 0 of some page. The locations used by the hardware

program and one executive

table for that user. The parts of a user process table not used by the

process table for itself for
each KI10 processor. In the
text, the phrase “the user
process table” refers to the

for the page map, traps, etc. of a given user are all in the first page of the
hardware may be used by the Monitor to keep accumulators (when the user

is not running), a pushdown list that the Monitor uses for the job, and
various

user

statistics

running

the whereabouts of the ex-

The

detailed

memory

space,

configuration

billing

hardware-defined parts of the process tables (user and executive) is given in

The Monitor must also specify

tables.

time,

fied by the Monitor as the
user is not currently running.

job

information,

one for the user, even if that

and

such

process table currently speci-

the

§2.15.

KA10

Memory

Allocation. The

use

of certain memory locations is

defined by the KA10 hardware.

‘

ecutive process table for the
processor under consideration.

The initial control word ad-

dress for the DF10 Data
Channe! must be less than
1000.

Holds a pointer word during a bootstrap readin

0-17

Can be éddresSed as accumulators

1-17

Can be addressed as index registers

40-41

Trap for unimplemented user operations (UUOs)

42-57

Priority interrupt locations

60-61

Trap for remaining unimplemented operations: these include
the unassigned instruction codes that are reserved for future
use, and also the byte manipulation and floating point instructions when the hardware for them is not installed

- -19§1.4

SYSTEM REFERENCE

PROGRAMMING CONVENTIONS

140-161

1-15

Allocated to second processor if connected (same use as 40-61

All information given in this

for first processor)

manual about memory locations 40-61 for a KA10 ap-

In a user program the trap for a local UUO is relocated to locations 40 and

41 of the user area; a Monitor UUO uses unrelocated locations. All other

addresses listed are for physical (unrelocated) locations.

1.4

pliesinstead to locations 140—

161 for programming a second
KA10 connected to the same
memory.

PROGRAMMING CONVENTIONS

The computer has five instruction classes: data transmission, logical, arith-

metic, program control and in-out.

The instructions in the in-out class con-

trol the peripheral equipment, and also control the priority interrupt and
time sharing, control and read the processor flags, and communicate with the

console.

The next chapter describes all instructions mentioned above,

presents a general description of input-output, and describes the effects of
the in-out instructions on the processor, priority interrupt and time share

hardware.

Effects of in-out instructions on particular peripheral devices are

discussed with the devices.
The Macro—10 assembly program recognizes a number of mnemonics and

other initial symbols that facilitate constructing complete instruction words
and organizing them into a program.

In particular there are mnemonics for

the instruction codes (Appendix A), which are six bits in in-out instructions,

otherwise nine or thirteen bits. Fg the mnemonic
MOVNS

The

assembles as 213000 000000, and
MOVNS

word, placing Os in all bits

2570

tion, produces the twos complement negative of the word in memory loca-

tion 2570.
Note
Throughout this manual all numbers representing instruction words,
register contents, codes and addresses are always octal, and any num-

bers appearing in program examples are octal unless otherwise indi:
On the other hand, the ordinary use of numbers in the text to

count steps in an operation or to specify word or byte lengths, bit

positions, exponents, etc employs standard decimal notation.

The initial symbol @ preceding a memory address places a 1 in bit 13 tc
produce indirect addressing. The example given above uses direct addressing,
but

MOVNS

translates

- whose values are unspecified.

assembles as 213000 002570. This latter word, when executed as an instruc-

cated.

assembler

every statement into a 36-bit

@2570

assembles as 213020 002570, and produces indirect addressing. Placing the

SYSTEM REFERENCE

-20-

INTRODUCTION

§1.4

number of an index register (1-17) in parentheses following the memory
address causes modification of the address by the contents of the specified
register. Hence

MOVNS @2570(12)
which assembles as 213032 002570, produces indexing using index register
12, and the processor then uses the modified address to continue the effective address calculation.

An accumulator address (0—17) precedes the memory address part (if any)

and is terminated by a comma. Thus

MOVNS

4,@2570(12)

assembles as 213232 002570, which negates the word in location £ and
stores the result in both £ and in accumulator 4.

The same procedure may

be used to place ls in bits 9-12 when these are used for something other
than addressing an accumulator, but mnemonics are available for this purpose.

The device code in an in-out instruction is given in the same manner as an

accumulator address (terminated by a comma and preceding the address

part), but the number given must correspond to the octal digits in the word
(000-774).

Mnemonics are however available for all standard device codes. ,

To control the priority interrupt system whose code is 004, one may give
CONO

4,1302

which assembles as 700600 001302, or equivalently
CONO

PI, 1302

The programming examples in this manual use the following addressing
conventions:
¢ A colon following a symbol indicates that it is a symbolic location name.

ADD

6,5704

indicates that the location that contains ADD 6,5704 may be addressed symbolically as A.

¢ The period represents the current address, eg
ADD

5,.+2

is equivalent to

ADD

5,A+2

¢ Square brackets specify the contents of a location, leaving the address of
the location implicit but unspecified. Eg
ADD

12,[7256004]

ADD

12,A

and

-21-

§1.4

SYSTEM REFERENCE

PROGRAMMING CONVENTIONS

7256004

are equivalent.
Anything written at the right of a semicolon is commentary that explains
the program but is not part of it.

1-17

~23-

SYSTEM REFERENCE

Central Processor

This chapter describes all PDP-10 instructions but does not discuss the
effects of those in-out instructions that address specific peripheral devices.

In the description of each instruction, the mnemonic and name are at the
top, the format is in a box below them. The mnemonic assembles to the
word in the box, where bits in those parts of the word represented by letters
assemble as Os. The letters indicate portions that must be added to the mnemonic to produce a complete instruction word.
For many of the non-1O instructions, a description applies not to a unique

instruction with a single code in bits 0—8, but rather to an instruction set
defined as a basic instruction that can be executed in a number of modes.
These modes define properties subsidiary to the basic operation; eg in data
transmission the mode specifies which of the locations addressed by the in-

struction is the source and which the destination of the data, in test instructions it specifies the condition that must be satisfied for a jump or skip to

take place. The mnemonic given at the top is for the basic mode; mnemonics
for the other forms of the instruction are produced by appending letters
directly to the basic mnemonic.

Following the description is a table giving

the mnemonics and octal codes (bits 0—8) for the various modes.

In a description E refers to the effective address, half word operand, mask,

conditions, shift number or scale factor calculated from the 7, X and Y parts
of the instruction word.

In an instruction that ordinarily references mem-

ory, a reference to E as the source of information means that the instruction
retrieves the word contained in location E; as a destination it means the instruction stores a word in location E.

In the immediate mode of these

instructions, the effective half word operand is usually treated as a full word
that contains E in one half and zero in the other, and is represented either as
0,
E or E,0 depending upon whether E is in the right
or left half.

Most of the non-1O instructions can address an accumulator, and in the

box showing the format this address is represented by A4 ; in the description,
“AC> refers to the accumulator addressed by A.

“AC left” and *“AC right”

refer to the two halves of AC. If an instruction uses two accumulators, these
have addresses 4 and A+1, where the second addressis 0 if 4 is 17. In some
cases an instruction uses an accumulator only if 4 is nonzero: a zero address
in bits 9-12 specifies no accumulator.
The instructions are described in terms of their effects as seen by the user

in a normal program situation, and on the assumption that nothingis amiss —
the program is not attempting to reference a memory that does not exist or

to write in a protected area of core. In general, all descriptions apply equally
2-1

Letters

representing

modes

are suffixes, which produce
new mnemonics that are recognized

as distinct symbols

by the assembler.

SYSTEM REFERENCE
2-2

CENTRAL PROCESSOR

§2.1

well to operation in executive mode. For completeness, the effects of restrictions on certain instructions are noted, as are the effects of executing

instructions in special circumstances. But for the details of programming in

such special situations the reader must look elsewhere. In particular, §2.13
describes the priority interrupt, §2.14 discusses trapping, and § §2.15 and
2.16 describe the special effects and restrictions associated with the various
machine modes in the KI10 and the KA10 respectively.

To minimize processor execution time the programmer should minimize

the number of memory references and the number of shifts and other
iterative operations. When there is a choice of actions to be taken on the

basis of some test, the conditions tested should be set up so that the action
that results most often takes the least time. There are also various subtleties
that affect timing (such as the nature of the arithmetic algorithms), but

these are generally not worth considering except in very special circumstances (to determine the effect often takes more than the time saved).

No execution times are given with the instruction descriptions as the time
may vary greatly depending upon circumstances. At the outset the time

depends upon which processor performs the instruction, the mode the
processor is in, and the speeds of the memories used for fetching the instruc-

tion, fetching its operands, and storing its results. Beyond this the time
depends in many cases on the configuration of the operands and the number |
of iterative steps specified by the programmer as in a shift. Lastly the

processor is designed to save time wherever possible by inspecting the
operands in order to skip unnecessary steps.

The text sometimes refers to an instruction as being “‘executed.” To
“execute” an instruction means that the processor performs the instruction
out of the normal sequence, ie the sequence defined by the program counter
(which sequence may not be consecutive, as when a skip or jump or some

special circumstance changes PC). The processor fetches an executed instruction from a location whose address is supplied not by PC, but rather by an

execute instruction (whose operand is itself interpreted as an instruction)
or by some feature of the hardware such as a priority interrupt, trap, etc.

It is assumed that control will shortly be returned to PC, at the location it
originally specified before the interruption unless the instruction executed
or the hardware feature itself changes PC.

Some simple examples are included with the instruction descriptions, but
more complex examples using a variety of instructions are given in §2.11.

2.1

HALF WORD DATA TRANSMISSION

These instructions move a half word and may modify the contents of the
other half of the destination location. There are sixteen instructions deter-

mined by which half of the source word is moved to which half of the des-

tination, and by which of four possible operations is performed on the other

SYSTEM REFERENCE

§2.1

HALF WORD DATA TRANSMISSION

half of the destination.

The basic mnemonics
are three letters that indicate

the transfer
HLL

Left half of source to left half of destination

HRL

Right half of source to left half of destination

HRR

Right half of source to right half of destination

HLR

Left half of source to right half of destination

plus a fourth, if necessary, to indicate the operation.

Operation

Suffix

Do nothing

Effect on Other Half of Destination

Zeros

Ones

None

Places Os in all bits of the other half

Places Is in all bits of the other half

Places the sign (the leftmost bit) of
the half word moved in all bits of the

Extend

other half. This action extends a right
half word number into a full word
number but is valid arithmetically
only for positive left half word num-

bers — the right extension of a number
requires Os regardless of sign (hence
the Zeros operation should be used to
extend a left half word number).
An additional letter may be appended to indicate the mode, which determines the source and destination of the half word moved.

Mode

Suffix

Source

Destination

Immediate

The word O, F

Memory

Self

E, but full word result also

Basic

‘

goes to AC if A is nonzero

Note that selecting the left half of the source in immediate mode merely

clears the selected half of the destination.

HLL

|
0

Half Word Left to Left

soo0

|mM|
67

|1]
121314

1718

Move the left half of the source word specified by M to the left half of the

specified destination.

The source and the destination right half are un-

affected; the original contents of the destination left half are lost.

-26-

SYSTEM REFERENCE

CENTRAL PROCESSOR

§2.1

HLL
HLLI
HLLM
HLLS

Half Left to Left
Half Left to Left Immediate
Half Left to Left Memory
Half Left to Left Self

500
501
502
503

HLLZ

Half Word Left to Left, Zeros

HLLI merely clears AC left.

If A is zero, HLLS is a no-op,
otherwise it is equivalent to

si0

1213 14

x |

1718

]

Move the left half of the source word specified by M to the left half of the
specified destination, and clear the destination right half. The source is un\

affected, the original contents of the destination are lost.

HLLZI merely clears AC. If A
is zero, HLLZS merely clears
the right half of location E.

HLLZ
HLLZI
HLLZM
HLLZS

Half Left to Left, Zeros
Half Left to Left, Zeros, Immediate
Half Left to Left, Zeros, Memory
Half Left to Left, Zeros, Self

HLLO

Half Word Left to Left, Ones

520
0

[ x| 1718 .
[ml 4 121314

510
511
512
513

]

Move the left half of the source word specified by M to the left half of the
specified destination, and set the destination right half to all 1s. The source
is unaffected, the original contents of the destination are lost.

HLLOI sets AC to all Os in
the left half, all 1s in the
right.

HLLO
HLLOI
HLLOM
HLLOS

Half Left to Left, Ones
Half Left to Left, Ones, Immediate
'
Half Left to Left, Ones, Memory
Half Left to Left, Ones, Self

HLLE

Half Word Left to Left, Extend

[ s30
0

[m]

[1If

121314

1718

520
521
522
523

Move the left half of the source word specified by M to the left half of the
specified destination, and make all bits in the destination right half equal to
bit 0 of the source. The source is unaffected, the original contents of the
destination are lost.

SYSTEM REFERENCE

-27-

§2.1

HALF WORD DATA TRANSMISSION

HLLE

Half Left to Left, Extend

HLLEI

Half Left to Left, Extend, Immediate

HLLEM

Half Left to Left, Extend, Memory

HLLES

Half Left to Left, Extend, Self

HRL

Half Word Right to Left

504

[mM]

[

121314

2-5
530

531
532

HLLELI is equivalent to HLLZI

(it merely clears AC).

533

]

1718

Move the right half of the source word specified by M to the left half of the
specified destination.

The source and the destination right half are unaf-

fected; the original contents of the; destination left half are lost.

HRL

Half Right to Left

HRLI

Half Right to Left Immediate

HRLM

"HRLS

HRLZ

514

504

Half Right to Left Memory

505
:

506

Half Right to Left Self

507

Half Word Right to Left, Zeros

[m]
67

Ji]

121314

]

1718

B
35

Move the right half of the source word specified by M to the left half of the
specified destination, and clear the destination right half.
affected, the original contents of the destination are lost.

The source is un-

HRLZ

Half Right to Left, Zeros

514

HRLZI

Half Right to Left, Zeros, Immediate

515

HRLZI loads the word E,0

HRLZM

Half Right to Left, Zeros, Memory

516

into AC.

HRLZS

Half Right to Left, Zeros, Self

517

HRLO

Half Word Right to Left, Ones

|
0

524

[m]
67

[I]
121314

]
1718

|
35

Move the right fialf of the source word specified by M to the left half of the

specified destination, and set the destination right half to all 1s. The source
is unaffected, the original contents of the destination are lost.

-28-

SYSTEM REFERENCE

CENTRAL PROCESSOR

§2.1

HRLO
HRLOI
HRLOM
HRLOS

Half Right to Left, Ones
Half Right to Left, Ones, Immediate
Half Right to Left, Ones, Memory
Half Right to Left, Ones, Self

HRLE

Half Word Right to Left, Extend

|
0

534

[M] 4 | x |

121314

1718

524
525
526
. 527

Move the right half of the source word specified by
M to the left half of the

specified destination, and make all bits in the destination right half equal to
bit 18 of the source.

The source is unaffected, the original contents of the

destination are lost.
HRLE

Half Right to Left, Extend

HRLE!

Half Right to Left, Extend, Immediate

HRLEM

Half Right to Left, Extend, Memory

i HRLES

HRR

[ s40
0

534
535
-

Half Right to Left, Extend, Self

536
537

Half Word Right to Right

1213

1] x |
14

1718

]
35

Move the right half of the source word specified by M to the right half of the
specified destination. The source and the destination left half are unaffected;
the original contents of the destination right half are lost.

If A is zero, HRRS is a no-op;
otherwise it is equivalent to

HRR

Half Right to Right

HRRI

Half Right to Right Immediate

540

HRRM

Half Right to Right Memory

HRRS

Half Right to Right Self

HRRZ

Half Word Right to Right, Zeros

541
»

542
543

MOVE.

|_sso

[m| 4 i x |

.89

121314

1718

]
35

Move the right half of the source word specified by M to the right half of the

SYSTEM REFERENCE

-99-

§2.1

HALF WORD DATA TRANSMISSION

specified destination, and clear the destination left half. The source is unaf-

fected, the original contents of the destination are lost.

HRRZ

Half Right to Right, Zeros

HRRZI

Half Right to Right, Zeros, Immediate

551

HRRZM

Half Right to Right, Zeros, Memory

552

HRRZS

Half Right to Right, Zeros, Self

553

HRRO

Half Word Right to Right, Ones

[m|

[ 560

|1l

121314

1718

550

Move the right half of the source word specified by M to the right half of the

specified destination, and set the destination left half to all 1s. The source is
unaffected, the original contents of the destination are lost.

HRRO

Half Right to Right, Ones

HRROI
HRROM
HRROS

Half Right to Right, Ones, Immediate
Half Right to Right, Ones, Memory
Half Right to Right, Ones, Self

HRRE

Half Word Right to Right, Extend

s70

M| a4
67

|1l

560
561
562
563

1718

121314

Move the right half of the source word specified by M to the right half of the
specified destination, and make all bits in the destination left half equal to
bit 18 of the source. The source is unaffected, the original contents of the

”

destination are lost.

Half Right to Right, Extend

570

HRREI

Half Right to Right, Extend, Immediate

571 .

HRREM

Half Right to Right, Extend, Memory

572

HRRES

Half Right to Right, Extend, Self

573

HLR

Half Word Left to Right

HRRE

s4a
0

| M|
67

|1l
1213 14

|
1718

Y
‘

Move the left half of the source word specified by M to the right half of the

HRRZI loads the word 0,F
into AC. If 4 is zero, HRRZS
merely clears the left half of
location E.

SYSTEM REFERENCE

-320-

§2.1

CENTRAL PROCESSOR

2-8

specified destination. The source and the destination left half are unaffected;
the original contents of the destination right half are lost.

HLRI merely clears AC right.

HLR

Half Left to Right

544

HLRI

Half Left to Right Immediate

545

~ HLRM

Half Left to Right Memory

HLRS

Half Left to Right Self

HLRZ

" Half Word Left to Right, Zeyos

[

554

[m|
67

546
547

|
35

1718

121314

Move the left half of the source word specified by M to the right half of the

specified destination, and clear the destination left half. The source is un-

affected, the original contents of the destination are lost.
HLRZI merely clears AC and
is thus equivalent.to HLLZL.

HLRZ
HLRZI
HLRZM

Half Left to Right, Zeros
Half Left to Right, Zeros, Immediate
Half Left to Right, Zeros, Memory

HLRO

Half Word Left to Right, Ones

554
555+
556

‘

557

Half Left to Right, Zeros, Self

HLRZS

[

564

M|
67

[1]

1718

. 121314

Move th¢ left half of the source word specified by M to the right half of the

specified destination, and set the destination left half to all 1s.” The source isunaffected, the original contents of the destination are lost.

HLRO
HLROI sets AC to all Is in
the left half, all Os in the
right.

Half Left to Right, Ones

564

~ HLROI

Half Left to Right, Ones, Immediate

HLROM

Half Left to Right, Ones, Memory

HLROS

Half Left to Right, Ones, Self

HLRE

Half Word Left to Right, Extend

s74
0

Il
121314

|
1718

565

566
.

567

]

Y
.

Move the left half of the source word specified by M to the right half of the

_31-

§2.2

SYSTEM REFERENCE

FULL WORD DATA TRANSMISSION

2-9

specified destination, and make all bits in the destination left half equal to
bit 0 of the source.

The source is unaffected, the original contents of the

destination are lost.

HLRE

Half Left to Right, Extend

574

HLREI

Half Left to Right, Extend, Immediate

575

HLREI

HLREM

Half Left to Right, Extend, Memory

576

HLRZI (it merely clears AC).

HLRES

Half Left to Right, Extend, Self

577

equivalent

ExampLes. The half word transmission 1nstruct10ns are very useful for
handling addresses, and they provide a convenient means of setting up an
accumulator whose right halfis to be used for indexing while a control count

is kept in the left half.

Eg this pair of instructions loads the 18-bit numbers
M and N into the left and right halves respectively of an accumulator that is

addressed symbolically as XR.

HRLZI

XR,M

HRRI

XR,N

It is not necessary to clear the

other half of XR when load-

Of course the source program must somewhere define the value of the
symbol XR as an octal number between 1 and 17.

Suppose that at some point we wish to use the two halves of XR independently as operands (taken as 18-bit positive numbers) for computations.
We can begin by moving XR left to the right half of another accumulator
AC and leaving the contents of XR right alone in XR.
HLRZM

XR,AC

HLLI

XR,

2.2

FULL WORD DATA TRANSMISSION

words of data from one place to another, usually from an accumulator to a

In a few cases instructions may perform

minor arithmetic operations, such as forming the negative or the magnitude
of the word being processed.

.
0

Exchange

250

|
89

1]
121314

the other half is faster than
the corresponding instruction
that does not, as the latter
must fetch the destination
word in order to save half of
it. (The difference does not
the source and destination are
the same.)

These are the instructions whose basic purpose is to move one or more full

EXCH

any instruction that modifies

apply to self mode, for here

;Clear XR left

memory location or vice versa.

ing the first half word. But

|
1718

Y
:

‘

Move the contents of location E to AC and move AC to location E.

|
)

SYSTEM REFERENCE

2-10

CENTRAL PROCESSOR

BLT

§2.2

Block Transfer

251

|1l
1213 14

1718

Beginning at the location addressed by AC left, move words to another area
of memory beginning at the location addressed by AC right. Continue until

a word is moved to location E.

The total number of words in the block is

thus F — ACy + 1.
CAUTION

Priority interrupts are allowed during the execution of this instruction,

following the processing of each word. If an interrupt occurs, the BLT
stores the source and destination addresses for the next word in AC, so
when the processor restarts upon the return to the interrupted program,
it actually resumes at the correct point within the BLT.

Therefore,

unless the interrupt system is inactive, A and X must not address the
same register as this would produce a different effective address calculation upon resumption should an interrupt occur; and the program must
not attempt to load an accumulator addressed either by A or X unless it

is the final location being loaded.

Furthermore, the program cannot

assume that AC is the same after the BLT as it was before.

ExampLEs. This pair of instructions loads the accumulators from memory

locations 2000-2017.
HRLZI

17,2000

BLT

17,17

;Put 2000 000000 in AC 17

But to transfer the block in the opposite direction requires that one accumulator first be made available to the BLT:
MOVEM

17,2017

;Move AC 17 to 2017 in memory

MOVEI

17,2000

:Move the number 2000 to AC 17

BLT

17,2016

If at the time the accumulators were loaded the program had placed in location 2017 the control word necessary for storing them back in the same
block (2000), the three instructions above could be replaced by
EXCH

17,2017

BLT

17,2016

Move Instructions
Besides the move instructions

Each of these instructions moves a 'Single word, which may be changed in the

for single words there are also

process (eg its two halves may be swapped).

There are four instructions,

-33-

§2.2

SYSTEM REFERENCE

FULL WORD DATA TRANSMISSION

2-11

each with four modes that determine the source and destination of the word

four transmission instructions

moved.

that

Mode

‘

Sujfix

Source

Destination

The word 0, E

~ Memory

Self

Basic
Immediate

MOVE

double

length

(operands

adjacent

words). These are

of two

available,

however, only in
the KI10; and since they are

principally for use in hardware

double precision floating point
operations, they are described

E, but also AC
if A is nonzero

with the floating point instructions in §2.6

Move

200

handle

operands

M|
67

[

121314

]

1718

B
35

Move one word from the source to the destination specified by M. The
source is unaffected, the original contents of the destination are lost.

MOVE

Move

200

MOVEI

Move Immediate

201

into AC and is thus equiva-

MOVEM

Move to Memory

202

MOVES

Move to Self

MOVES is a no-op; otherwise

203

MOVS

Move Swapped

204
0

M|
67

121314

]

1718

~ MOVEI loads the word 0,F
lent to HRRZI. If A is zero,
it is equivalent to MOVE.

N
35

Ihterchange the left and right halves of the word from the source specified
by M and move it to the specified destination. The source is unaffected, the
original contents of the destination are lost.

MOVS

Move Swapped

204

MOVSI

Move Swapped Immediate

205

MOVSM

Move Swapped to Memory

206

MQOVSS

Move Swapped to Self

207

MOVN

Move Negative

210
0

(M|
67

|1l
1213 14

]
1718

|
35

Negate the word from the source specified by M and move it to the specified
destination.

If the source word is fixed point —235 (400000 000000) set the

Swapping halves-in immediate
mode loads the word E,Q into
AC. MOVSI is thus equivalent

to HRLZI.

-3~

SYSTEM REFERENCE

In the K110 a move executed
as an interrupt instruction can

set no flags.

§2.2

CENTRAL PROCESSOR

2-12

Overflow and Carry 1 flags. (Negating the equivalent floating point ~1 X 2127

sets the flags, but this is not a normalized number.) If the source word is
zero, set Carry 0 and Carry 1. The source is unaffected, the original contents
of the destination are lost. Setting Overflow also sets the Trap 1 flag in the
KI10.

Move Negative

210

MOVNI

Move Negative Immediate

211

MOVNM
MOVNS

Move Negative to Memory
Move Negative to Self

212
213

MOVM

Move Magnitude

MOVN
MOVNI loads AC with the

F and
negative of the word 0,
can set no flags. -

214
0

[1]
121314

)
35

1718

Take the magnitude of the word contained in the source specified by M and

move it to the specified destination. If the source word is fixed point —23°

In the KI10 a move executed
as an interrupt instruction can
set no flags.

The word O,F is equivalent to its magnitude, so MOVMI
is equivalent to MOVEL

(400000 000000) set the Overflow and Carry 1 flags. (Negating the equivalent floating point —1 X 21?7 sets the flags, but this is not a normalized number.) The source is unaffected, the original contents of the destination are
lost. Setting Overflow also sets the Trap 1 flag in the KI10.

214

MOVM

Move Magnitude

MOVMI

Moye Magnitude Immediate

MOVMM

Move Magnitude to Memory
Move Magnitude to Self -

MOVMS

215

216
217

An example at the end of the preceding section demonstrates the use of a
pair of immediate-mode half word transfers to load an address and a control
count into an accumulator. The same result can be attained by a single move
instruction. This saves time but still requires two locations. Eg if the number 200 001400 is stored in location M, the instruction
MOVE

ACM

loads 200 into AC left and 1400 into AC right. If the same word, or its negative, or with its halves swapped, must be loaded on several occasions, then
both time and space can be saved
as each transfer requires only a single move
instruction that references M.

Pushdown List
These two instructions insert and remove full words in a pushdown list. The
address of the top item in the list is kept in the right half of a pointer in AC,

SYSTEM REFERENCE

-35-

§2.2

2-13

FULL WORD DATA TRANSMISSION

and the program can keep a control count in the left half.

There are also

'~ two subroutine-calling instructions that utilize a pushdown list of jump addresses [ §2.9].

PUSH

Push Down

261

| 4 1] x|

121314

1718

Y
’

B
)

Add one to each half of AC, then move the contents of location £ to the
location now addressed by AC right. If the addition causes the count in AC
left to reach zero, set the Pushdown Overflow flag in the KA10, set the

In the KI10 a PUSH executed

Trap 2 flag in the KI10. The contents of £ are unaffected, the original

contents of the location added to the list are lost.

interrupt

instruction

cannot set Trap 2.

Note: The KA10 increments the two halves of AC by adding 10000014
to the entire register. In the KI10 the two halves are handled independently.

POP

Pop Up

262

|
89

|1l x
121314

1718

N
35

Move the contents of the location addressed by AC right to location E, then
subtract one from each half of AC. If the subtraction causes the count in AC

left to reach —1, set the Pushdown Overflow flag in the KA 10, set the Trap 2
flag in the KI110. The original contents of £ are lost.
Because of the order in which the operands are stored, the instruction

POP AC,AC would load the contents of the location addressed by AC right
into AC on top of the pushdown count, destroying it.

Note: The KA10 decrements the two halves of AC by subtracting
1 0000014 from the entire register. In the KI10 the two halves are handled
independently.

In the KA10, incrementing and decrementing both halves of AC together is effected by adding and subtracting 1 0000013. Hence a count of =2 in AC

left is increased to zero if 28 —1 is incremented in AC right, and conversely,
1 in AC left is decreased to —1 if zero
is decremented in AC right.
A pushdown list is simply a set of consecutive memory locations from
which words are read in the order opposite that in which they are written.

In more general terms, it is any list in which the only item that can be removed at any given time is the last item in the list.

This is usually referred

to as ‘““first in, last out” or ““last in, first out”. Suppose locationsa, b, ¢, ...
are set aside for a pushdown list. We can deposit datain g, b, ¢, d, then read

In the KI10 a POP executed
as an interrupt instruction
cannot set Trap 2.

SYSTEM REFERENCE

-36-

2-14

CENTRAL PROCESSOR

§2.2

d, then write in d and ¢, thenread ¢, d, ¢, etc.

Note that by trapping or checking overflow and keeping a control count in
AC left, the programmer can set a limit to the size of the list by starting the
count negative, or he can prevent the program from extracting more words
than there are in the list by starting the count at zero, but he cannot do both

at once. The common practice is to limit the size of the list.
Pushdown storage is very convenient for a program that can use data
stored in this manner as the pointer is initialized only once and only one

accumulator is required for the most complex pushdown operations. To initialize a pointer P for a list to be kept in a block of memory beginning at
BLIST and to contain at most N items, the following suffices.
MOVSI

P,—-N

HRRI

P,BLIST-1

Of course the programmer must define BLIST elsewhere and set aside loca-

tions BLIST to BLIST + N — 1.

Using Macro to full advantage one could

instead give

'
MOVE

P,[IOWD N,BLIST]

where the pseudoinstruction
IOWD J. K

is replaced by a word containing —J in the left half and K — 1 in the right.
Elsewhere there would appear

BLIST:

BLOCK

which defines BLIST as the current contents of the location counter and sets

aside the N locations beginning at that point.
In the PDP-10 the pushdown list is kept in a random access core memory, so the restrictions on order of entry and removal of items actually apply

only to the standard addressing by the pointer in pushdown instructions —

other addressing methods can reference any item at any time.

The most

convenient way to do this is to use the right half of the pointer as an index
register. To move the last entry to accumulator AC we need simply give

MOVE

AC,P) .

’O'f course this does not shorten the list — the word moved 'remains the last
item in it.

One usually regards an index register as supplying an additive factor for a

basic address contained in an instruction word, but the index register can
supply the basic address and the instruction the additive factor. Thus we can
retrieve the next to last item by giving
MOVE

AC,-1(P)

and so forth. Similarly
PUSH

P,-3(P)

SYSTEM REFERENCE

-3/~

§2.3

BYTE MANIPULATION

2-15

adds the third to last item to the end of the list;

POP

Note

that

calculated

before the contents of P are

P,—2(P)

changed.

removes the last item and inserts it in place of the next to last item in the

shortened list.

2.3

BYTE MANIPULATION

In a KA10 without byte manipulation hardware, all of the

This set of five instructions allows the programmer to pack or unpack bytes
of any length anywhere within a word.

Movement of a byte is always

between AC and a memory location: a deposit instruction takes a byte from
the right end of AC and inserts it at any desired position in the memory
location; a load instruction takes a byte from any position in the memory

location and places it right-justifiedin AC.
The byte manipulation instructions have the standard memory reference
format, but the effective address E is used to retrieve a pointer, whichis used
in turn to locate the byte or the place that will receive it.

The pointer has

the format

OLPISIIIIXI'
56

11121314

17 18

]

where S is the size of the byte as a number of bits, and P is its position as the
number of bits remaining at the right of the byte in the word (eg if P is 3 the
rightmost bit of the byte is bit 32 of the word).

The rest of the pointer
is

interpreted in the same way as in an instruction: 7/, X and Y are used to calculate the address of the location that is the source or destination of the
byte. Thus the pointer aims at a word whose format is

555/

35-P-8+1

pBITs

35-P 35-P+1

where the shaded area is the byte.

|
a5

‘

To facilitate processing a series of bytes, several of the byte instructions
increment the pointer, ie modify it so that it points to the next byte position -

in a set of memory locations.

Bytes are processed from left to right in a

word, so incrementing merely replaces the current value of P by P — S, unless

there is insufficient space in the present location for another byte of the
specified size (P —S < 0).

In this case Y is increased by one to point to the

next consecutive location, and P is set to 36 — S to point to the first byte at

the left in the new location.

Caurion (k10 ONLY)
Do not allow Y to reach maximum value. The whole pointer is incre-

instructions presented in this
section

are

trapped

assigned codes [§2.10].

un-

~ SYSTEM REFERENCE

-38-

2-16
In

CENTRAL PROCESSOR

the

KII10,

§2.3

mented, so if Y is 28— 1 it becomes zero and X is also incremented.

incrementing

maximum Y produces a zero

The address calculation for the pointer uses the original X, but if a pri-

address without affecting X.

ority interrupt should occur before the calculation is complete, the in-

cremented X is used when the instruction is repeated.

Among these five instructions one simply increments the pointer, the
or deposit a byte with or without incrementing.

others load

LDB

Load Byte

[ 4 1] x |

121314

1718

)
35

Retrieve a byte of S bits from the location and position specified by the

pointer contained in location E, load it into the right end of AC, and clear
the remaining AC bits.. The location containing the byte is unaffected, the

original contents of AC are lost.

' D.PB

Deposit Byte

137

121314

]

17 18

Deposit the right.$ bits of AC into the location and position specified by the

pointer contained in location E. The original contents of the bits that receive
the byte are lost, AC and the remaining bits of the deposit location are
unaffected.

IBP

Increment Byte Pointer

133
0

121314

17 18.

)
35

Increment the byte pointer in location E as explained above.

ILDB

Increment Pointer and Load Byte

134
0

[
89

1]
121314

|
1718

|
35

Increment the byte pointer in location £ as explained above. Then retrieve a

byte of S bits from the location and position specified by the newly incremented pointer, load it into the right end of AC, and clear the remaining AC

bits.

The location containing the byte is unaffected, the original contents of

AC are lost.

SYSTEM REFERENCE

~39-

§2.4

IDPB

Increment Pointer and Deposit Byte

136

|
89

LOGIC

a4 [

121314

1718

2-17

]

Increment the byte pointer in location E as explained above. Then deposit

the right S bits of AC into the location and position specified by the newly

incremented pointer.

The original contents of the bits that receive the byte
are lost, AC and the remaining bits of the deposit location are unaffected.

Note that in the pair of instructions that both increment the pointer and
process a byte, it is the modified pointer that determines the byte location

and position. Hence to unpack bytes from a block of memory, the program
should set up the pointer to point to a byte just before the first desired, and

then load them with a loop containing an ILDB. If the first byte is at the
left end of a word, this is most easily done by initializing the pointer with a

P of 36 (445). Incrementi
then
ng replaces the 36 with 36 — S to point to the

first byte. At any time that the program might inspect the pointer during
* execution of a series of ILDBs or IDPBs, it points to the last byte processed
(this may not be true when the pointer is tested from an interrupt routin

[§2.13]).

Special Considerations. If S is greater than P and also greater than 36,
incrementing produces a new P equal to 100 —.S rather than 36 —S. For

S > 36 the byte is at most the entire word; for P> 36 no byte is processed
(loading merely clears AC).

If both P and S are less than 36 but P+ 5 > 36,
a byte of size 36 — P is loaded from position P, or the right 36 — P bits of the

byte are deposited in position P.

2.4

LOGIC

For logical operations the PDP~10 has instructions for shifting and rotating
as well as for performing the complete set of sixteen Boolean functions of
two variables (including those in which the result depends on only one or

neither variable). The Boolean functions operate bitwise on full words, so
each instruction actually performs thirty-six logical operations simultaneously. Thus in the anp function of two words, each bit of the result is the

AND of the corresponding bits of the operands.

The table
on page 2-23 lists
the bit configurations that result from the various operand configurations for

all instructions.

Each Boolean instruction has four modes that determine the source of the:
non-AC operand, if any, and the destination of the result. For an instruction
without an operand (one that merely clears a location or sets it to all Is) the

modes differ only in the destination of the result, so basic and immediate

SYSTEM REFERENCE

-L40-

CENTRAL PROCESSOR

§2.4

modes are equivalent.

an AC operand.

The same is true also of an instruction that uses only
When specified by the mode, the result goes to the accumu-

lator addressed by A4, even when there is no AC operand.
‘

Mode
Basic

-Source of non-

Suffix

Destination

AC operand

of result

Immediate

The word 0, E

Memory

Both

ACand E

SETZ

Set to Zeros

400

[m]
67

Jif

]

1213 14

1718

Change the contentof
s the destination specified by M to all Os.
SETZ and SETZI are equivalent (both merely clear AC).
MAcro also tecognizes
CLEAR, CLEARI, CLEARM

and CLEARB as equivalent to

the set-to-zeros mnemonics.

SETZ

Set to Zefos

SETZI

Set to Zeros Immediate

SETZM

Set to Zeros Memory

SETZB

Set to Zeros Both

SETO

Set to Ones

474

M|
67

400
401

402
‘

[

121314

]

403

1718

Change the contents of the destination specified by M to all 1s.
SETO and SETOI are equivalent.

SETO

Set to Ones

SETOI

Set to Ones Immediate

SETOM

Set to Ones Memory

SETOB

Set to Ones Both

SETA

Setto AC

L
0

424

[M]
67

‘

Il
121314

474
.

475

476
477

1718

Make the contents of the destination specified by M equal to AC.

B
35

SYSTEM REFERENCE

-41-

8§24

LOGIC

2-19

SETA

Set to AC

424

SETAI

Set to AC Immediate

425

SETAM

Set to AC Memory

SETAB

Set to AC Both

SETCA

450
0

426

SETA and SETAI are no-ops.

SETAM and SETAB are both
equivalent

MOVEM

(all

move AC to location F).

427

Setto Complement of AC

M|
67

|1l

121314

1718

Change the contents of the destination specified by M to the complement

of AC.

SETCA

Set to Complement of AC

450

SETCA

SETCAI

Set to Complement of AC Immediate

451

equivalent (both complement .

SETCAM

Set to Complement of AC Memory

452

SETCAB

Set to Complement of AC Both

453

SETM

Set to Memory

414

m|
67

[1]

1213 14

]

and

SETCAI

are

AC).

1718

Make the contents of the destination specified by M equal to the specified
operand.

SETM

Set to Memory

SETMI

Set to Memory Immediate

‘

SETMM

Set to Memory Memory

SETMB

Set to Memory Both

414
415
_

416

417

SETM and SETMB are equiv-

alent

MOVE.

SETMI

moves the word 0,E to AC
and

thus

equivalent

that references memory.

SETCM

460
0

Set to Complement of Memory

| M|
67

|1]
1213 14

1718

Change the contents of the destination specified by M to the complement of

the specified operand.

MOVEIL SETMM is a no-op

SYSTEM REFERENCE -

-42-

CENTRAL PROCESSOR

2-20

SETCMI moves the complement of the word 0, E to AC.
SETCMM complements location F.

§2.4

SETCM

Set to Complement of Memory

SETCMI

Set to Complement of Memory Immediate

461

SETCMM

Set to Complement of Memory Memory

462

SETCMB

Set to Complement of Memory Both

463

AND

And with AC

404
0

(M|
67

|1l

121314

1718

460

]
35

Change the contents of the destination specified by M to the anp function

of the specified operand and AC.

AND

And

404

ANDI

And Immediate

405

ANDM

And to Memory

ANDB

And to Both

ANDCA

And with Complement of AC

|
0

410
_

(M|
67

406

[1]

121314

‘

1718

407

|
35

Change the contents of the destination specified by M to the anp function

of the specified operand and the complement of AC.

ANDCA

And with Complement of AC

ANDCAI

And with Complement of AC Immediate

411

410

ANDCAM

And with Complement of AC to Memory

412

ANDCAB

And with Complement of AC to Both

413

ANDCM

And Complement of Memory with AC

420

(M|
67

il
1213 14

|
1718

Y
35

Change the contents of the destination specified by M to the anp function

of the complement of the specified operand and AC.
ANDCM

And Complement of Memory

420

ANDCM|

And Complement of Memory Immediate

421

SYSTEM REFERENCE

~43-

§2.4
ANDCMM

And Complement of Memory to Memory

ANDCMB

And Complement of Memory to Both

ANDCB

And Complements of Both

440

|mM|
67

12.13 14

2-21

422
:

423

]

1718

Change the contents of the destination specified by M to the anp function of
the complements of both the specified operand and AC. The result is the
Nor function of the operands.

And Complements of Both

ANDCBI

ANDCBM

And Complements of Both Immediate
And Complements of Both to Memory

ANDCBB

And Complements of Both to Both

I0R

Inclusive Or with AC

[

434

[mM]
67

[i]

1213 14

440

441
447

ANDCB

443

|
1718

Change the contents of the destination specified by M to the inclusive or
function of the specified operand and AC.

‘

I0R

Inclusive Or

I0ORI

Inclusive Or Immediate

IORM

Inclusive Or to Memory

IORB

Inclusive Or to Both

ORCA

Inclusive Or with Complement of AC

454
0

| M|
67

1]
121314

434

435

436
437

1718

‘

Change the contents of the destination specified by M to the inclusive or
function of the specified operand and the complement of AC.

ORCA

Or with Complement of AC

ORCAI

Or with Complement of AC Immediate

454
455

ORCAM

Or with Complement of AC to Memory
Or with Complement of AC to Both

456
457

ORCAB

MACRO also recognizes OR,
ORI, ORM and ORB as equivalent to the inclusive OR mne" MONnics.

SYSTEM REFERENCE

~-4h-

2-22

§2.4

CENTRAL PROCESSOR

ORCM
464

Inclusive Or Complement of Memory with AC

(M| 4 1] x |

121314

1718

Change the contents of the destination specified by M to the inclusive or
function of the complement of the specified operand and AC.

OBCM

Or Complement of Memory

464

ORCMI

Or Complement of Memory Immediate

465

ORCMM

Or Complement of Memory to Memory

466

ORCMB

Or Complement of Memory to Both

467

ORCB

Inclusive Or Complements of Both

470

|mM|
67

|1l

121314

1718

|
35

Change the contents of the destination specified by M to the inclusive or ,
function of the complements of both the specified operand and AC.

The

result is the NaND function of the operands.

ORCB

Or Complements of Both

470

ORCBI

Or Complements of Both Immediate

471

ORCBM

Or Complements of Both to Memory

472

ORCBB

Or Complements of Both to Both

473

XOR

Exclusive Or with AC

430
0

|m|
67

|1}

1213 14

1718

Change the contents of the destination specified by M to the exclusive or

function of the specified operand and AC.

XOR

Exclusive Or

XORI

Exclusive Or Immediate

431

XORM

Exclusive Or to Memory

432

XORB

Exclusive Or to Both

430

433

The original contents of the destination can be recovered except in XORB,

where both operands are replaced by the result.

In the other three modes

the replaced operand is restored by repeating the instruction in the same

mode, ie by taking the exclusive or of the remaining operand and the resuit.

_45-

§2.4

EQV

Equivalence with AC

444

M|
67

SYSTEM REFERENCE

LOGIC

2-23

|
x

1213 14

]

1718

Change the contents of the destination specified by M to the complement of
the exclusive or function of the specified operand and AC (the result has Is
wherever the corresponding bits of the operands are the same).

EQV

Equivalence

EQVi

Equivalence Immediate

EQVM

Equivalence to Memory

446

EQVB

Equivalence to Both

447

444
:

445

The original contents of the destination can be recovered except in EQVB,
where both operands are replaced by the result.

In the other three modes
the replaced operand is restored by repeating the instruction in the same

mode, ie by taking the equivalence function of the remaining operand and
the result.

For the four possible bit configurations of the two operands, the above
sixteen instructions produce the following results.

In each case the result as

listed is equal to bits 3—6 of the instruction word.

)

Mode Specified Operand

SETZ

AND

ANDCA

SETM

ANDCM

SETA

XOR

IOR

ANDCB

EQV

SETCA

ORCA

SETCM

ORCM

ORCB

SETO

SYSTEM REFERENCE

~46-

2-24

CENTRAL PROCESSOR

§2.4

Shift and Rotate

The remaining logical instructions shift or rotate right or left the contents of
AC or the contents of two accumulators,

4 and A+1 (mod 20g), concat-

enated into a 72-bit register with A on the left.

The illustration below

shows the movement of information these instructions produce in the accu-

LSH

LSHC

ROT -

'
|

ROTC

A
0

ASHC

A+1

ASH

A+
0

A
1

0
35

A+*

0
A
1

h
35

—
35

A4 +1
1

ACCUMULATOR BIT FLOW IN SHIFT AND ROTATE INSTRUCTIONS

0
35

SYSTEM REFERENCE

~-147-

§2.4

LOGIC

2-25

mulators. In a (logical) shift the contents of a register are moved bit-to-bit
with Os brought in at the end being vacated; information shifted out at the

other end is lost.
[For a discussion of arithmetic shifting see §2.5.]1 In
rotation the contents are moved cyclically such that information rotated out

at one end is put in at the other.

The number of places moved is specified by the result of the effective
address calculation taken as a signed number (in twos complement notation)

modulo 2% in magnitude.

In other words the effective shift E is the number

composed of bit 18 (which is the sign) and bits 28-35 of the calculation
result. Hence the programmer may specify the shift directly in the instruc-

tion (perhaps indexed) or give an indirect address to be used in calculating

the shift. A positive E produces motion to the left, a negative £ to the right.

In the KA10, maximum movement is 255 places. The KI10 eliminates re-

dundant movement of the operand by shifting
maximum of 71.

LSH

£ mod 72 places, for a

‘Logical Shift

242

| 4

|1l

121314

]

1718

|
)

Shift AC the number of places specified by E. If E is positive, shift left
bringing Os into bit 35; data shifted out of bit O is lost. If E is negative, shift

right bringing Os into bit 0; data shifted out of bit 35 is lost.

LSHC

[

Logical Shift Combined

246

[

i
1213 14

|
1718

Y
.

]
35

Concatenate accumulators

A and A+1 with 4 on the left, and shift the
72-bit combination the number of places specified by E. If E is positive,
shift left bringing Os into bit 71 (bit 35 of AC A+1); bit 36 is shifted into bit

35; data shifted out of bit 0 is lost. If E is negative, shift right bringing Os
into bit 0; bit 35 is shifted into bit 36; data shifted out of bit 71 is lost.

ROT

Rotate

241

|
89

]
121314

x T
1718

|
35

Rotate AC the number of places specified by E. If E is positive, rotate left;

bit 0 is rotated into bit 35.
into bit 0.

If E is negative, rotate right; bit 35 is rotated

QYSTEM REFERENCE

-48-

2-26

CENTRAL PROCESSOR

ROTC

§2.5

Rotate Combined

245

x |

1213 14

Concatenate accumulators

4 and

1718

]
35

A+1 with A on the left, and rotate the

72-bit combination the number of places specified by E.

If E is positive,

rotate left; bit O is rotated into bit 71 (bit 35 of AC A+1) and bit 36 into bit
35.

If E is negative, rotate right; bit 35 is rotated into bit 36 and bit 71 into

bit 0.

2.5

FIXED POINT ARITHMETIC

For fixed point arithmetic the PDP-10 has instructions for arithmetic shifting (which is essentially multiplication by a power of 2) as well as for performing addition, subtraction, multiplication and division of numbers in

fixed point format [§1.1]. In such numbers the position of the binary point
is arbitrary (the programmer may adopt any point convention). The add and

subtract instructions involve only single length numbers, whereas multiply
supplies a double length product, and divide uses a double length dividend..
The high and low order words respectively of a double length fixed point
number are in accumulators 4 and A+1 (mod 20g), where the magnitude is

the 70-bit string in bits 1-35 of the two words and the signs of the two are
identical.

There are also integer multiply and divide instructions that involve

“only single length numbers and are especially suited for handling smaller

integers, particularly those of eighteen bits or less such as addresses
(of

course they can be used for small fractions as well provided the programmer
keeps track of the binary point). For convenience in the following, all operands are assumed to be integers (binary point at the right).

- The processor has four flags, Overflow, Carry 0, Carry 1 and No Divide,

that indicate when the magnitude of a number is or would be larger than can
be accommodated.

Carry 0 and Carry 1 actually detect carries out of bits O

and 1 in certain instructions that employ fixed point arithmetic operations:

the add and subtract instructions treated here, the move instructions that

produce the negative or magnitude of the word moved [§2.2], and the
arithmetic
Overflow

is determined

di-

rectly from the carries, not

from the carry flags, as their
states may reflect events in
previous instructions.

test instructions that increment

or decrement the test word

[82.7]. In these instructions an incorrect result is indicated — and the Overflow flag set — if the carries are different, ie if there is a carry into the sign

but not out of it, or vice versa. The Overflow flag is also set by No Divide
being set, which means the processor has failed to perform a division because
the magnitude of the dividend is greater than or equal to that of the divisor,

or in integer divide, simply that the divisor is zero.

In other overflow cases

only Overflow itself is set: these include too large a product in multiplica-

tion, too large a number to convert to fixed point [§2.6], and loss of signi~In

the

KI10

instruction

arithmetic

executed

interrupt instruction can set

no flags.

ficant bits in left arithmetic shifting. In the KI10 any condition that sets
Overflow also sets the Trap 1 flag.

:
These flags can be read and controlled by certain program control instruc-

tions [§8§2.9, 2.10]. In the KA10, Overflow is available as a processor

SYSTEM REFERENCE

~49~

2-27

FIXED POINT ARITHMETIC

§2.5

condition (via an in-out instruction) that can request a priority interrupt if
enabled, whereas KI10 overflow is handled by trapping through the setting
of Trap 1 [both subjects are discussed in §2.14]. The conditions detected
can only set the arithmetic flags and the hardware does not clear them,
so the program must clear them before an instruction if they are to give

meaningful information about the instruction afterward. However, the

~ program can check the flags following a series of instructions to determine
whether the entire series was free of the types of error detected.
All but the shift instructions have four modes that determine the source
of the non-AC operand and the destination of the result.

Source of non-

Basic
Immediate
Memory
Both

Destination
of result

AC operand

Suffix

Mode

AC
AC
E
ACand E

E
The word O, E
E
E

I
M
B

Add

ADD

[ 270

[m]

|1l

|
1718

121314

)

Add the operand specified by M to AC and place the result in the specified
destination. If the sum is = 23 set Overflow and Carry 1;the result stored

has a minus sign but a magnitude in positive form equal to the sum less 2%.

If the sum is < —23 set Overflow and Carry O; the result stored has a plus

sign but a magnitude in negative form equal to the sum plus 235 Set both

carry flags if both summands are negative, or their signs differ and their magnitudes are equal or the positive one is the greater in magnitude.

ADD
ADDI
ADDM

|
Add
Add Immediate
Add to Memory

ADDB

Add to Both

SuB

Subtract

[
0

274

[m]

[

121314

1718

270
271
272
273

Subtract the operand specified by M from AC and place the result in the
specified destination. If the difference is = 23° set Overflow and Carry 1;
the result stored has a minus sign but a magnitude in positive form equal to
the difference less 235. If the difference is < —235 set Overflow and Carry O;

the result stored has a plus sign but a magnitude in negative form equal to

Besides indicating error types,

the carry flags facilitate performing multiple precision
arithmetic.

SYSTEM REFERENCE

-50-

CENTRAL PROCESSOR

§2.5

the difference plus 2%. Set both carry flags if the signs of the operands are
the same and AC is the greater or the two are equal, or the signs of the
operands differ and AC is negative.

SuB

Subtract

274

SuBlI

Subtract Immediate

275

SUBM

Subtract to Memory

SUBB

Subtract to Both

MUL

Multiply

224
0

M|
67

276
:

|1 x
121314

277

1718

Multiply AC by the operand specified by M, and place the high order word

of the double length result in the specified destination. If M specifies AC as
a destination, place the low order word in accumulator A+1.

If both oper-

ands are —23% set Overflow; the double length result stored is —27°.
MUL

Multiply

MULI

Multiply Immediate

MULM

Multiply to Memory

MULB

Multiply to Both

IMUL

Integer Multiply

220

|m|
67

224
225

226
227

1213 14

1718

Multiply AC by the operand specified by M, and place the sign and the 35
low order magnitude bits of the product in the specified destination.

Set

Overflow if the product is = 235 or < —23% (je if the high order word of the
double length product is not null); the high order word is lost.
IMUL

Integer Multiply

iMULI

Integer Multiply Immediate

221

IMULM

Integer Multiply to Memory

222

IMULB

Integer Multiply to Both

223

Div

Divide

234
0

M|
67

I
1213 14

’

|
1718

220

|
35

If the magnitude of the number in AC is greater than or equal to that of the

-51-

§2.5

SYSTEM REFERENCE

FIXED POINT ARITHMETIC

2-29

operand specified by M, set Overflow and No Divide, and go immediately to
the next instruction without affecting the original AC or memory operand in

any way. Otherwise divide the double length number contained in accumula-

tors

A and A+1 by the specified operand, calculating a quotient of 35
magnitude bits including leading zeros. Place the unrounded quotient in the
specified destination. If M specifies AC as a destination, place the remainder,
with the same sign as the dividend, in accumulator A+1.
DIV

Divide

DIV

Divide Immediate

DIVM

Divide to Memory

DIVB

Divide to Both

IDIV

Integer Divide

230

234

[m]

235

‘

236
»

[

121314

]

237

]

1718

If the operand specified by M is zero, set Overflow and No Divide, and go
immediately to the next instruction without affecting the original AC or
memory operand in any way. Otherwise divide AC by the specified operand,

calculating a quotient of 35 magnitude bits including leading zeros. Place
the unrounded quotient in the specified destination. If M specifies AC as the

destination, place the remainder, with the same sign as the dividend, in
accumulator A+1.

iDIV

Integer Divide

IDIVI

Integer Divide Immediate

IDIVM

Integer Divide to Memory

232

IDIVB

Integer Divide to Both

233

230
"

231

ExampLe. The integer multiply and divide instructions are very useful for
computations on addresses or character codes, or performing any integral
operations in which the result is small enough to be accommodated 1n a

single register.
As an example suppose we wish to determine the parity of the 8-bit character abcdefgh, where the letters represent the bits of the character. Assuming the characteris right-justifiedin AC, we first duplicate it twice to the left

producing

abc def gha bcd efg hab cde fgh
where the bits (in positions 12-35) are grouped corresponding to the octal

digits in the word. Anding this with

001

~52-

SYSTEM REFERENCE

CENTRAL PROCESSOR

2-30

§2.5

retains only the least significant bit in each 3-bit set, so we can represent the

result by
cfadgbeh

where each letter represents an octal digit having the same value (0 or 1) as
the bit originally represented

the same letter.

Multiplying this by

111111114 generates the following partial products:
c fadgbeh

c fadgbeh

c fadgbehn

¢c fadgbehn
c fadgbeh
c fadghbehn
c fadgbeh
c fadgbehn
Since any digit is at most 1, there can be no carry out of any column with
fewer than eight digits unless there is a carry into it. Hence the octal digit
produced by summing the center column (the one containing all the bits of

the character) is even or odd as the sum of the bits is even or odd. Thus its
least significant bit (bit 14 of the low order word in the product) is the par-

ity of the character, 0 if even, 1 if odd.

’

The above may seem a very complicated procedure to do something
trivial, but it is effected by this quite simple sequence (with the character

right-justified in AC):

ONES:

IMULI

AC,200401

AND

AC,ONES

IMUL

AC,ONES

11111111

where the parity is indicated by AC bit 14.

Of course, following the IMUL

would be a test instruction to check the value of the bit.

Arithmetic Shifting
These two instructions produce an arithmetic shift right or left of the number in AC or the double length number in accumulators 4 and A+1. Shifting

is the movement of the contents of a register bit-to-bit.

The operation dis-

cussed here is similar to logical shifting [see §2.4 and the illustration on
page 2-24], but in an arithmetic shift only the magnitude part is shifted —
the sign is unaffected.

In a double length number the 70-bit string made up

of the magnitude parts of the two words is shifted, but the sign of the low
order word is made equal to the sign of the high order word.

Null bits are brought in at the end being vacated: a left shift brings in Os at
the right, whereas a right shift brings in the equivalent of the sign bit at the
left.

In either case, information shifted out at the other end is lost. A single

-53-

§2.5

SYSTEM REFERENCE

FIXED POINT ARITHMETIC

2-31

shift left is equivalent to multiplying the number by 2 (provided no bit of
significance is shifted out); a shift right divides the number by 2.

The number of places shifted is specified by the result of the effective
address calculation taken as a signed number (in twos complement notation)

modulo 28 in magnitude.

In other words the effective shift £ is the number

composed of bit 18 (which is the sign) and bits 28-35 of the calculation

result. Hence the programmer may specify the shift directly in the instruction (perhaps indexed) or give an indirect address to be used in calculating

the shift. A positive £ produces motion to the left, a negative E to the right;
E is thus the power of 2 by which the number is multiplied. In the KA10,
maximum movement is 255 places. The KI10 eliminates redundant move-

ment of the operand by shifting £ mod 72 places, fora maximum of 71.

ASH

[

Arithmetic Shift

240

]

An arithmetic right shift trun-

[

121314

|
1718

‘

,Shift AC arithmetically the number of places specified by E.

Do not shift

bit 0. If E is positive, shift left bringing Os into bit 35; data shifted out of bit
1 is lost; set Overflow if any bit of significance is lost (a 1 in a positive number, a 0 in a negative one).

If E is negative, shift right bringing Os into bit 1

if AC is positive, 1s if negative; data shifted out of bit 35 islost.

ASHC

|
89

|1l
121314

ently

from IDIV if 1s are
shifted out. The result of the

shift is more negative by one
than the quotient of IDIV.
To obtain the same quo-

tient that IDIV would give

with a dividend in A divided

by N= 2K , use
SKIPGE

ADDI

AN-1

ASH

AKX

This takes 5-6 ps as opposed

Arithmetic Shift Combined

244
0

cates a negative result differ-

to about 16 us for IDIVL

1718

B
35

Concatenate the magnitude portions of accumulators 4 and A+1 with
A on
the left, and shift the 70-bit combination in bits 1-35 and 37-71 the number of places specified by £.” Do not shift AC bit 0, but make bit 0 of AC
A+1 equal to it if at least one shift occurs (ie if E is nonzero). If E is posi-

tive, shift left bringing Os into bit 71 (bit 35 of AC A+1); bit 37 (bit 1 of AC
A-+1) is shifted into bit 35; data shifted out of bit 1 is lost; set Overflow if

“any bit of significance is lost (a 1 in a positive number, a 0 in a negative one).
If E is negative, shift right bringing Os into bit 1 if AC is positive, s if negative; bit 35 is shifted into bit 37; data shifted out of bit 71 is lost.

2.6

FLOATING POINT ARITHMETIC

In a KA10 without floating
point hardware, all of the in-

For floating point arithmetic the PDP-10 has instructions for scaling the
exponent (which is multiplication of the entire number by a power of 2)

structions
section

presented

are

trapped

in this
as

assigned codes [§2.10].

un-

-5~

SYSTEM REFERENCE

CENTRAL PROCESSOR

2-32

§2.6

and negating double length numbers (software format) as well as performing
addition, subtraction, multiplication and division of numbers in single precision floating point format. Moveover the KI10 has instructions for per-

forming the four standard arithmetic operations on floating point numbers

in hardware double precision format, for moving double precision numbers

(with the option of taking the negative) between a pair of accumulators and
a pair of memory locations, and for converting single precision numbers

from fixed format to floating and vice versa. Except for the conversion in-

structions and the simple moves, all instructions treated here interpret all

operands as floating point numbers in the formats given in § 1.1, and generate results in those formats. The reader is strongly advised to reread § 1.1 if
he does not remember the formats in detail.

For the four standard arithmetic operations in single precision, the program can select whether or not the result shall be rounded. Rounding
produces the greatest consistent precision using only single length operands.
Instructions without rounding have a ‘“‘long” mode, which supplies a twoword result for greater precision; the other modes save time in one-word
operations where rounding is of no significance.
Actually the result is formed in a double length register in addition, sub-

traction and multiplication, wherein any bits of significance in the low order
part supply information for normalization, and then for rounding if re-

quested.

Consider addition as an example.

Before adding, the processor

right shifts the fractional part of the operand with the smaller exponent until

its bits correctly match the bits of the other operand in order of magnitude.
Thus the smaller operand could disappear entirely, having no effect on the

result (“‘result” shall always be taken to mean the information (one word or
two) stored by the instruction, regardless of the number of significant
bits it
A subtraction involving two
like-signed

numbers

whose

exponents are
equal and
whose fractions differ only in
the LSB gives a result containing only one bit of significance.

contains or even whether it is the correct answer). Long mode is likely to
retain information that would otherwise be lost, but in any given mode the
significance of the result depends on the relative values of the operands.
Even when both operands contain twenty-seven significant bits, a long addi- tion may store two words that together contain only one significant bit. In

division the processor always calculates a one-word quotient that requires no
normalization if the original operands are normalized. An extra quotient bit

is calculated for rounding when requested; long mode retains the remainder.
Among the floating point instructions available only in the KI10, those
that convert between number types operate only on single words. The in-

struction that converts to floating point assumes the operand is an integer

and always normalizes and rounds the result. In the opposite direction, only

the integral part of the result is saved, and rounding is an option of the program. The instructions for the four standard operations using double pre-

cision have no modes. In division the processor always calculates a two-word
quotient that is normalized if the original operands are normalized, but
rounding is not available. In addition, subtraction and multiplication, the

result is formed in a triple length register, wherein bits of significance in the
lowest order part supply information for limited normalization and then
for rounding, which is automatic.

The processor has four flags, Overflow, Floating Overflow, Floating
Underflow and No Divide, that indicate when the exponent is too large or

~55-

8§2.6

SYSTEM REFERENCE

FLOATING POINT ARITHMETIC

2-33

too small to be accommodated or a division cannot be performed because of
the relative values of dividend and divisor. Except where the result would be

in fixed point form, any of these circumstances sets Overflow and Floating
Overflow. If only these two are set, the exponent of the answer is too large;

if Floating Underflow is also set, the exponent is too small. No Divide being
set means the processor failed to perform a division, an event that can be
produced only by a zero divisor if all nonzero operands are normalized. Any

condition that sets Overflow in the KI10 also sets the Trap 1 flag. These flags
can be read and controlled by certain program control instructions [ § § 2.9,

2.10]. In the KA10, Overflow and Floating Overflow are available as processor conditions (via an in-out instruction) that can request a priority interrupt

if enabled, whereas KI10 overflow is handled by trapping through the setting
of Trap 1 [both of these subjects are discussed in §2.14]. The conditions
detected can only set the arithmetic flags and the hardware does not clear

them, so the program must clear them before a floating point instruction if
they are to give meaningful information about the instruction afterward.
However, the program can check the flags following a series of instructions

the

KI10

arithmetic

instruction executed as an interrupt instruction can set no

flags.

to determine whether the entire series was free of the types of error detected.

The floating point hardware functions at its best if given operands that
are either normalized or zero, and except in special situations the hardware
normalizes a nonzero result.

An operand with a zero fraction and a nonzero

" exponent can give wild answers in additive operations because of extreme

loss of significance; eg adding %2 X 2% and 0 X 29° gives a zero result, as the
first operand (having a smaller exponent) looks smaller to the processor and

is shifted to oblivion. A number with a 1 in bit 0 and Os in bits 9-35 is not
simply

incorrect representation of zero, but rather an unnormalized

“fraction” with value —1.

This unnormalized number can produce an incor-

rect answer in any operation.

Use of other unnormalized operands simply

causes loss of significant bits, except in division where they can prevent its
execution because they can satisfy a no-divide condition that is impossible

for normalized numbers.

The processor normalizes the
result by shifting the fraction
and adjusting the exponent to
compensate for the change in

value. Each shift and accom-

panying exponent adjustment
thus multiply the number
both by 2 and by % simultaneously, leaving its value un-

changed.
Note that with normalized
operands, the processor uses
at most two bits of informa-

tion from the lowest order
part to normalize the result.

multiplication

obvious,

Scaling
One floating point instruction is in a category by itself: it changes the
exponent of a number without changing the significance of the fraction. In
other words it multiplies the number by a power of 2, and is thus analogous
to arithmetic shifting of fixed point numbers except that no information is

lost, although the exponent can overflow or underflow. The amount added
to the exponent is specified by the result of the effective address calculation
taken as a signed number (in twos complement notation) modulo 28 in magnitude.

In other words the effective scale factor
E is the number composed

of bit 18 (which is the sign) and bits 2835 of the calculation result. Hence
the programmer may specify the factor directly in the instruction (perhaps
indexed) or give an indirect address to be used in calculating it. A positive E
increases the exponent, a negative E decreases it; E is thus the power of 2 by
which the number is multiplied.
+255.

The scale factor lies in the range —256 to

since

minimum

this

squaring

the

fractional

magni-

tude % gives a result of %. In
an addition or subtraction of
numbers that differ greatly in
order of magnitude, the result

determined

pletely

by the

almost

com-

operand

greater order. A subtraction
involving two like-signed numbers with equal exponents re-

quires no shifting beforehand
so there is no information in
the lowest order part. Hence

addition

subtraction

never requires shifting both

before the operation and in
the normalization;when there

is no prior shifting, the nor-

malization brings in Os.

SYSTEM REFERENCE

~56-

CENTRAL PROCESSOR

2-34

132

to float a fixed number with
27 or fewer significant bits.
To float an integer contained
within AC bits 9-35,
FSC

|1l

121314

the

binary

17 18

|
35

given by E to the exponent part of AC (thus multiplying AC by 2£), normalize the resulting word bringing Os into bit positions vacated at the right, and
place the result back in AC.

AC,233

move

§2.6

If the fractional part of AC is zero, clear AC. Otherwise add the scale factor

NoTE

inserts the correct exponent
to

Floating Scale

FSC

This instruction can ‘be used

A negative E is represented in standard twos com-

point

plement notation, but the hardware compensates

from the right end to the left
of bit 9 and then normalizes

for this when scaling the exponent.

(2333 = 155, = 128 +27).

If the exponent after normalization is > 127, set Overflow and Floating
Overflow; the result stored has an exponent 256 less than the correct one. .
If < —128, set Overflow, Floating Overflow and Floating Underflow; the
result stored has an exponent 256 greater than the correct one.

Number Conversion

In the KA10 these instructions are trapped as unassigned
codes.

Although FSC can be used to float a fixed point number, the KI10 has three
single precision instructions specifically for converting between integers and
floating point numbers. In all cases the operand is taken from location E,
and the converted result is placed in AC.

Fix

FIX

|
0

This overflow test checks for

the
a value = 235 assuming
operand is normalized.

122

|
89

[1]
121314

|
1718

truncation (“fixation”). For
it,

the

processor drops the

|
35

If the exponent of the floating point number in location E is > 35, set
Overflow and Trap 1, and go immediately to the next instruction without
affecting AC or the contents of E in any way.

Otherwise replace the exponent X in the word from location E with bits
equal to the sign of the fraction, and shift the (now fixed) extended fraction
N =X — 27 places to the correct position for its order of magnitude with the .
binary point at the right of bit 35. For positive N, shift left bringing Os
into bit 35 and dropping null bits out of bit 1. For negative N, shift right
bringing null bits (0Os for positive, 1s for negative) into bit 1, and then
truncate to an integer. Place the result in AC.

This is the standard Fortran

Truncation produces the integer of largest magnitude less than or equal to
the magnitude of the original number. Eg a number > +1 but < +2 becomes
+1; a number < —1 but > —2 becomes —1.

SYSTEM REFERENCE

-57-

§2.6

FLOATING POINT ARITHMETIC

FIXR

2-35

‘Fix and Round

126

fractional paft in a positive
number, but adds one to the

121314

1718

integral part (as required by

any bits of significance are

If the exponent of the floating point number in location £ is > 35, set
Overflow and Trap 1, and go immediately to the next instruction without

affecting AC or the contents of £ in any way.

Otherwise replace the exponent X in the word from location F with bits
equal to the sign of the fraction, and shift the (now fixed) extended fraction
N=X —27 places to the correct position for its order of magnitude with the
binary point at the right of bit 35.

twos complement format) if
shifted

number.

out

negative

This overflow test checks for

a value > 2% assuming the
operand is normalized.

For positive N, shift left bringing Os

into bit 35 and dropping null bits out of bit 1.

For negative N, shift right

bringing null bits (0s for positive, 1s for negative) into bit 1, and then round

the integral part.

Place the result in AC.

Rounding is in the positive direction: the magnitude of the integral part
is increased by one if the fractional part is 2 5 in a positive number but
> % in a negative number.
+1.5

and

Eg +1.4 (decimal) is rounded to +1, whereas

+1.6 become +2; but with negative numbers, —1.4 and —1.5

become —1, whereas —1.6 becomes —2.

This is the Algol standard for
real to integer conversion. For

it the processor adds one to
the integral part if the fractional part is 2 % in a posi-

tive number or (as required
by twos complement format)

is < % in a negative number.

FLTR

Float and Round

127

|
89

121314

1718

Shift the magnitude part of the fixed point integer from location E right
eight places, insert the exponent 35 (in proper form) into bits 1 -8 to move
the shifted binary point to the left of bit 9 (35 = 27 + 8), and normalize the
fraction bringing first the bits originally shifted out and then Os into bit

positions vacated at the right. If fewer than eight bits (left shifts) are needed
to normalize, use the next bit to round the single length fraction.
the result in AC.

Place

‘

The rounding function is the same as that used by the standard floating

point arithmetic instructions [see below].

Since the largest fixed point magnitude (without considering sign) is

235 — 1, a floating point number with exponent greater than 35 (and
assumed normalized) cannot be converted to fixed point.

There is no limit

in the opposite direction, but precision can be lost as floating point format

provides fewer significant bits. A fixed integer greater than 227 — 1 cannot
be represented exactly in floating point unless all its significant bits are
clustered within a group of twenty-seven.

SYSTEM REFERENCE

2-36

CENTRAL PROCESSOR

§2.6

Single Precision with Rounding
In the hardware the rounding

There are four instructions that use only one-word operands and store a

operation

single-length rounded result.

what

actually

some-

complex

than

stated here.

If the result is

negative, the hardware combines rounding with placing

Rounding is away from zero: if the part of the

normalized answer being dropped (the low order part of the fraction) is
greater than or equal in magnitude to one half the LSB of the part being

retained, the magnitude of the latter part is increased by one LSB.

the high order word in twos

The rounding instructions have four modes that determine the source of

complement form by decreas-

the non-AC operand and the destination of the result. These modes are like

ing its magnitude if the low
order part is < J4LSB. Moreover an extra single-step re-

normalization

rounded

occurs

those of logic and fixed point arithmetic, including an immediate mode that
allows the instruction to carry an operand with it.

if the

Source of non-

Destination

Suffix

AC operand

of result

Immediate

The word E,0

Memory

ACand £

word is no longer

Mode

normalized.

Basic

" Both

Note however that floating point immediate uses £,0 as an operand, not

0,E.

In other words the half word F is interpreted as a sign, an 8-bit expo- .

nent, and a 9-bit fraction.

In each of these instructions, the exponent that results from normalization and rounding is tested for overflow or underflow.

If the exponent is

> 127, set Overflow and Floating Overflo:; the result stored has an exponent 256 less than the correct one.

If <—128, set Overflow, Floating Over-

flow and Floating Underflow; the result stored has an exponent 256 greater

than the correct one.

FADR

Floating Add and Round

144

M|
67

Il
121314

1718

Floating add the operand specified by M to AC. If the double length fraction
in the sum is zero, clear the specified destination.

Otherwise normalize the

double length sum bringing Os into bit positions vacated at the right, round
the high order part, test for exponent overflow or underflow as described

above, and place the result in the specified destination.

FADR
FADRI

Floating Add and Round

FIOating Add and Round Immediate

144

145

FADRM

Floating Add and Round to Memory

146

FADRB

Floating Add and Round to Both

147

SYSTEM REFERENCE

-59-

§ 26

FLOATING POINT ARITHMETIC

FSBR

2-37

FlGating Subtract and Round

154

M|
67

121314

1718

Floating subtract the operand specified by M from AC. If the double length
fraction in the difference is zero, clear the specified destination. Otherwise
normalize the double length difference bringing Os into bit positions vacated

at the right, round the high order part, test for exponent overflow or under-

flow as described above, and place the result in the specified destination.
FSBR

Floating Subtract and Round

154

FSBRI

Floating Subtract and Round Immediate

155

FSBRM

Floating Subtract and Round to Memory

156

FSBRB

Floating Subtract and Round to Both

157

FMPR

Floating Multiply and Round

1ea

(M|
67

Jif

121314

17 18

Floating Multiply AC by the operand specified by M.

If the double length

fraction in the product is zero, clear the specified destination.

Otherwise

normalize the double length product bringing Os into bit positions vacated at

the right, round the high order part, test for exponent overflow
or underflow
as described above, and place the result in the specified destination.

FMPR

Floating Multiply and Round

FMPRI

Floating Multiply and Round Immediate

FMPRM

Floating Multiply and Round to Memory

FMPRB

Floating Multiply and Round to Both

FDVR

Floating Divide and Round

|
0

174

M|
67

4 |1
121314

164
165

166
167

1718

|
35

If the magnitude of the fraction in AC is greater than or equal to twice that

Division fails if the divisor is

of the fraction in the operand specified by M, set Overflow, Floating Over-

zero, but the no-divide condition can otherwise be satisfied
only if at least one operand is
unnormalized.

flow and No Divide, and go immediately to the next instruction without
affecting the original AC or memory operand in any way.
If the division can be performed, floating divide AC by the operand spec-

ified by M, calculating a quotient fraction of 28 bits (this includes an extra
bit for rounding).

If the fraction is zero, clear the specified destination.

Otherwise round the fraction using the extra bit calculated.

If the original

~60-

SYSTEM REFERENCE

§2.6

CENTRAL PROCESSOR

2-38

operands were normalized, the single length quotient will already be
normalized; if it is not, normalize it bringing Os into bit positions vacated
at the right. Test for exponent overflow or underflow as described above,
and place the result in the specified destination.

174
175

Floating Divide and Round
Floating Divide and Round Immediate
Floating Divide and Round to Memory
Floating Divide and Round to Both

FDVR
FDVRI
FDVRM
FDVRB

176
177

Single Precision without Rounding

Instructions that do not round are faster for processing floating point
numbers with fractions containing fewer than 27 significant bits. On
the other hand the long mode provides double precision (software format)

or allows the programmer to use his own method of rounding. Besides

the four usual arithmetic operations with normalization, there are two
nonnormalizing instructions that facilitate software double precision arith-

.
metic [§2.11 gives examples of double precision floating point routines]
These two instructions have no modes.

Usually the double length
number is in two adjacent
accumulators, and E equals
A+l1.

Note that this instruction
can be used to negate numbers in software double pre-

cision format only, for the
KI10 hardware double precision format, the program
must use the double moves.

~ Double Floating Negate

DFN

[
0

1sr

|
] a [if x 1718

121314

B
35

Negate the double length floating point number composed of the contents of
AC and location E with AC on the left. Do this by taking the twos comple-

ment of the number whose sign is AC bit 0, whose exponent is in AC bits

1-8, and whose fraction is the 54-bit string in bits 9-35 of AC and location
E. Place the high order word of the result in AC; place the low order part of
the fraction in bits 9-35 of location E without altering the original contents
of bits 0—8 of that location.

Unnormalized Floating Add

UFA

130

4 1] x

121314

|
1718

|
35

Floating add the contents of location E to AC. If the double length fraction
in the sum is zero, clear accumulator A+1. Otherwise normalize the sum

only if the magnitude of its fractional part is > 1, and place the high order
part of the result in AC A+1. The original contents of AC and E are
unaffected.

SYSTEM REFERENCE

-61-

§2.6

. FLOATING POINT ARITHMETIC

2-39

NoTtEe
The result is placed in accumulator 4+1.
the

only

This is

arithmetic instruction that stores the

The exponent of the sum is

result in a second accumulator, leaving the original

equal to that of the larger

operands intact.

summand unless addition of

If the exponent of the sum following the one-step normalization is > 127,

set Overflow and Floating Overflow; the result stored has an exponent 256
less than the correct one.

The remaining single precision floating point instructions perform the four
standard arithmetic operations with normalization but without rounding.

All use AC and the contents of location E as operands and have four modes.

Mode

Suffix

Effect

Basic

High order word of result stored in AC.

Long

In addition, subtraction and multiplication, the two-word result (in the double
length format described in §1.1) is
stored in accumulators A and A+1. In_
division the dividend is the double length
word in A and A+1; the single length
quotient is stored in AC, the remainder
in ACA+1.
|

Memory

High order word of result stored in E.

Both

High order word of result stored in AC
and E.

In each of these instructions, the exponent that results from normaliza-

tion is tested for overflow or underflow. If the exponent is > 127, set Over-

flow and Floating Overflow; the result stored has an exponent 256 less than
the correct one.

If < —128, set Overflow, Floating Overflow and Floating

Underflow; the result stored has an exponent 256 greater than the correct

one.

‘

FAD

Floating Add

140
0

(M|
67

|1
121314

|
1718

|
35

Floating add the contents of location E to AC. If the double length fraction
in the sum is zero, clear the destination specified by M, clearing both accu-

mulators in long mode. Otherwise normalize the double length sum bringing
Os into bit positions vacated at the right, test for exponent overflow or

the fractions overflows, in
which case it is greater by 1.
Exponent overflow can occur
only in the latter case.

—62-

SYSTEM REFERENCE

CENTRAL PROCESSOR

2-40

§2.6

underflow as described above, and place the high order word of the result in
the specified destination.

In long mode if the exponent of the sum is > 154 (127 +27) or <—101

(—128 +27) ‘or the low order half of the fraction is zero, clear AC A+1.
Otherwise place a low order word for a double length result in A+1 by
putting a 0 in bit 0, an exponent in positive form 27 less than the exponent
of the sum in bits 1-8, and the low order part of the fraction in bits 9-35.
FAD

Floating Add

FADL

Floating Add Long

FADM

Floating Add to Memory

FADB

Floating Add to Both

FSB

Floating Subtract

[

aso

M|
67

140
-

142
143

121314

141

1718

|
35

Floating subtract the contents of location F from AC. If the double length.

fraction in the difference is zero, clear the destination specified by M, clear-

ing both accumulators in long mode. Otherwise normalize the double length

difference bringing Os into bit positions vacated at the right, test for exponent overflow or underflow as described above, and place the high order
word of the result in the specified destination.
In long mode if the exponent of the difference is > 154 (127 +27).or
< —101 (128 + 27) or the low order half of the fraction is zero, clear AC
A+1. Otherwise place a low order word for a double length result in A+1 by
putting a 0 in bit 0, an exponent in positive form 27 less than the exponent

of the difference in bits 1-8, and the low order part of the fraction in bits
9-35.

’

FSB

Floating Subtract

FSBL

Floating Subtract Long

FSBM

Floating Subtract to Memory

FSBB

Floating Subtract to Both

FMP

Floating Multiply

|
0

160

M|
67

|1}

121314

150
151

152

|
1718

153

|
35

Floating fnultiply AC by the contents of location E. If the double length
fraction in the product is zero, clear the destination specified by M, clearing
both accumulators in long mode.

Otherwise normalize the double length

‘SYSTEM REFERENCE

~63-

FLOATING POINT ARITHMETIC

§2.6

2-41

product bringing Os into bit positions vacated at the right, test for exponent
overflow or underflow as described above, and place the high order word of
the result in the specified destination.
~ In long mode if the exponent of the product is > 154 (127 +27) or

< =101 (=128 + 27) or the low order half of the fraction is zero, clear AC
A+1. Otherwise place a low order word for a double length result in A+1
by putting a 0 in bit 0, an exponent in positive form 27 less than the
exponent of the product in bits 1-8, and the low order part of the fraction
|
in bits 9-35.

FMP
FMPL
FMPM
FMPB

Floating Multiply
Floating Multiply Long
Floating Multiply to Memory
Floating Multiply to Both

FDV

Floating Divide

[ 170
0

(M|
67

1213 14

|
1718

160
161
162
163

B
35

If the magnitude of the fraction in AC is greater than or equal to twice that
of the fraction in location E, set Overflow, Floating Overflow and No Divide,
and go immediately to the next instruction without affecting the original AC
or memory operand in any way.

If division can be performed, floating divide the AC operand by the

contents of location E. In long mode the AC operand (the dividend) is the
double length number in accumulators A and 4+1; in other modes it is the
single word in AC. Calculate a quotient fraction of 27 bits. If the fraction

is zero, clear the destination specified by M, clearing both accumulators in
lonig mode if the double length dividend was zero. A quotient with a nonzero fraction will already be normalized it the original operands were nor-

malized; if it is not, normalize it bringing Os into bit positions vacated at the

right. Test for exponent overflow or underflow as described above, and
place the single length quotient part of the result in the specified destination.
In long mode calculate the exponent for the fractional remainder from the
division according to the relative magnitudes of the fractions in dividend and
divisor: if the dividend was greater than or equal to the divisor, the exponent
of the remainder is 26 less than that of the dividend, otherwise it is 27 less.
If the remainder exponent is > 127 or < —128 or the fraction is zero, clear

AC A+1. Otherwise place the floating point remainder (exponent and fracin AC A+1.
tion) with the sign of the'dividend

FDV
FDVL

FOVM
FDVB

Floating Divide
Floating Divide Long

Floating Divide to Memory
Floating Divide to Both

170
171

72
173

Division fails if the divisor is
zero, but the no-divide condition can otherwise be satisfied
only if at least one operand is
unnormalized.

In long mode a nonzero unnormalized dividend whose
entire high order fraction. is
zero produces a zero quotient. In this case the second
AC receives rubbish.

_6li-

SYSTEM REFERENCE

CENTRAL PROCESSOR

2-42

§2.6

Double Precision Operations
In the KA10 these instructions

are trapped
codes.

unassigned

Although double precision floating point arithmetic can be done by routines
using the single precision instructions and the software double length format,
the KI10 has instructions specifically for handling double length operands
in the hardware double precision format described in §1.1. Four of the
- instructions use two double length operands, perform the standard arithmetic operations, and store double length results. The other four instructions
each move one double length operand between the accumulators and
memory, either unchanged or negated.

All of these instructions address a pair of adjacent accumulators and a
pair of adjacent memory locations. The accumulators have addresses
A and
A+1 (mod 20g) just as they do for the double length operands used in some
shift, rotate and single precision arithmetic instructions.
The memory

locations have addresses £ and E+1 (mod 2'3), where the second address
is 0 if E is 7777717.

For the two instructions that simply move a pair of words without
altering them, the format of those words is actually irrelevant. The other
six instructions process each word pair as a double length number in the
hardware floating point format. Hence they ignore bit O in the low order
word of every operand and clear that bit in the result.
The four nonmove instructions perform the standard arithmetic opera-,
tions. All use two double length operands in the hardware double precision
format, one from the accumulators and one from memory.
Addition

and subtraction always normalize the result; in multiplication and division
the result is guaranteed to be normalized only if the original operands
are normalized.
In all cases the result, rounded except in division, is
placed in the accumulators. The rounding function is the same as that
used in single precision: if the part of the answer being dropped (the
low order part of the fraction) is greater than or equal in magnitude to
one half the LSB of the double length part being retained, the magnitude
of the latter part is increased by one LSB (with appropriate adjustment for

a twos complement negative).

In each of these instructions, the exponent that results from normalizaAn arithmetic instruction exe-

tion and rounding (if done) is tested for overflow or underflow.

cuted as an interrupt instruc-

exponent is > 127, set Overflow and Floating Overflow; the result stored

tion can set no flags.

has an exponent 256 less than the correct one.

If the

If < -—128, set Overflow,

Floating Overflow and Floating Underflow; the result stored has an
exponent 256 greater than the correct one.
Setting Overflow also sets
the Trap 1 flag.

DFAD

Double Floating Add

110
0

[
89

[
121314

1718

Floating add the operand of locations E and E+1 to the operand of
accumulators 4 and A+1. If the high order 70 bits of the fraction in the

SYSTEM REFERENCE

-65-

FLOATING POINT ARITHMETIC

§2.6
sum are zero, clear A and A+1.

2-43

Otherwise normalize the triple length sum

bringing Os in at the right, round the high order double length part, test for

exponent overflow or underflow as described above, and place the result
in ACs A and A+1.

DFSB

Double Floating Subtract

111
0

a |1

121314

1718

|
35

Floating subtract the operand of locations £ and E+1 from the operand of

accumulators A and A+1.

If the high order 70 bits of the fraction in the

difference are zero, clear

and A+1.

Otherwise normalize the triple

length difference bringing Os into bit positions vacated at the right, round

the high order double length part, test for exponent overflow or underflow
as described above, and place the result in ACs 4 and A+1.

‘ DFMP
|

Double Floating Multiply
112

121314

1718

B
3s

Floating multiply the operand of accumulators 4 and A+1 by the operand

of locations E and E+1. If the high order 70 bits of the fraction in
the product are zero, clear A and A+1.
Otherwise, if there are any
bits of significance among the high order 35, do at most one normalization

shift if required; if the high order 35 bits are zero, shift the fraction
left 35 places (adjusting the exponent), and then do at most one normalization shift if required.

Round the high order double length part, test for

exponent overflow and underflow as described above, and place the result

in ACsA and A+1.

DFDV

|
0

The 35-bit shift can be done
only if the original operands
are unnormalized.

Double Floating Divide

113

|
89

[i]
121314

|
1718

Y
;

B
35

If the magnitude of the fraction in the operand of accumulatorsA and A+1
is greater than or equal to twice that of the fraction in the operand of
locations £ and E+1, set Overflow, Floating Overflow, No Divide and
Trap 1, and go immediately to the next instruction without affecting the
original AC or memory operands in any way.

If the division can be performed, floating divide the
' AC operand by the
memory operand, calculating a quotient fraction of 62 bits. If the fraction

Division fails if the divisor is
zero, but the no-divide condi-

tion can otherwise be satisfied
~only if at least one operand is
unnormalized.

'SYSTEM REFERENCE

~66-

CENTRAL PROCESSOR

2-44
A nonzero quotient is normalized if the original operands
are normalized.

§2.6

is zero, clear A and A+1. Otherwise test for exponent overflow or underflow as described above, and place the double length quotient part of the
result in ACs A and A+1 (the remainder is lost).

Double Move

DMOVE

[

120

[1]

121314

1718

Move the contents of locations E and E+1 respectively to accumulators 4
and A+1.

The memory locations are unaffected, the original contents

of the ACs are lost.

DMOVEM

Double Move to Memory

124

[

Do not use the instruction
DMOVEM AC,AC+1. Atpresent the processor places AC
in both AC+1 and AC+2, but
this result is not guaranteed.

1718

]
35

Double Move Negative

121

tions can be used to negate

locations are lost.

numbers in hardware double
precision format only; for

1]
121314

Move the contents of accumulators 4 and A+1 respectively to locations £
and E+1. The ACs are unaffected, the original contents of the memory

DMOVN

Note that these two instruc-

121314

)

1718

Negate the double length floating point number taken from locations
E and
E+1, and move it to accumulators A and 4+1. The memory locations are
unaffected, the original contents of the ACs are lost.

software double precision, the
program must use DFN.
Note also that there is no

overflow test, as negating a

correctly formatted floating
point

number cannot cause

overflow.

DMOVNM

|
0

125

Double Move Negative to Memory

|
89

|7
121314

|
1718

]
35

Negate the.double length floating point number taken from accumulators

not use the instruction

DMOVNM AC,AC+1. Atpre-

A and A+1, and move it to locations E and E+1. The ACs are unaffected,
the original contents of the memory locations are lost.

SYSTEM REFERENCE

-6/-

2-45

ARITHMETIC TESTING

§2.7

Although the configuration of the operands is irrelevant in DMOVE and
DMOVEM, none of the above instructions is available in the KAIlO.
Therefore unless a program is actually doing floating point arithmetic in the
hardware double precision format, it is recommended that the double
moves not be used irn KI10 programs so they will be compatible with

the KA10.

Simply to move a two-word operand unaltered requires two

one-word moves.

To negate a two-word operand that is actually in the

hardware format requires a somewhat longer substitution; eg this sequence
is equivalent to DMOVN AC,E.

SETCM
MOVN
TDNN

ADDI

:Take ones complement of high word
AC,E
;Take twos complement of low word
AC+1,E+1
;If low part of fraction is
AC+1,[377777777777]

;zero, change high word to twos com-

AC,1

;plement

2.7

ARITHMETIC TESTING

"These instructions may jump or skip depending on the result of an arithmetic
test and may first perform an arithmetic operation on the test word. Two of
the instructions have no modes.

Add One to Both Halves of AC and Jump if Positive

AOBJP

|
0

252

[

121314

1718

]

" Add one to each half of AC and place the result back in AC. If the result

is greater than or equal to zero (ie if bit O is 0, and hence a negative count

in the left half has reached zero or a positive count has not yet reached
217) take the next instruction from location E and continue sequential
operation from there.

Note: The KA10 increments the two halves of AC by adding 1 0000014
to the entire register. In the KI10 the two halves are handled independently.

Add One to Both Halves of AC and Jump if Negative

AOBJN

|
0 .

253

|
89

a4 |1l
121314

|
1718

B
35

Add one to each half of AC and place the result back in AC. If the result
is less than zero (ie if bit 0 is 1, and hence a negative count in the left half

has not yet reached zero or a positive count has reached 217) take the next
instruction from location E and continue sequential operation from there.

sent the processor places the

negative of AC (the comple-

ment, if AC+1 originally contains zero) into AC+1, and
the

negative

that

into

AC+2, but this result is not
guaranteed.

SYSTEM REFERENCE

-68-

2-46

CENTRAL PROCESSOR

§2.7

Note: The KA10 increments the two halves-of AC by adding 1 0000014

to the entire register. In the KI10 the two halves are handled independently.

In the KAI10, incrementing both halves of AC together is effected by
A count of —2 in AC left is therefore increased to zero if

adding 10000015.

218 — 1 is incremented in AC right.

These two instructions allow the program to keep a control count in the
left half of an index register and require only one data transfer to initialize.

Problem: Add 3 to each location in a table of N entries starting at TAB.
Only four instructions are required.
MOVSI

XR,—-N

MOVEI

AC,3

;Put 3in AC

ADDM

AC,TAB(XR)

;Add 3 to entry

AOBIJIN

XR,.—1

;Put —N in XR left (clear XR right)

;Update XR and go back unless all
;entries accounted for

The eight remaining instructions jump or skip if the operand or operands
satisfy a test condition specified by the mode.

Mode

Suffix

Never

Less

Equal

Less or Equal

L
E
LE

Always

Greater or Equal

Not Equal

Greater

Intstructions with one operand compare AC or the contents of location £

with zero, those with two compare AC with E or the contents of location E.

The processor always makes the comparison even though the result is used in
only six of the modes.

If the mnemonic has no suffix there is never any

program control function, and the instruction may be a no-op; an A suffix

produces an unconditional jump or skip — the action is always taken regardIn

the

KI10

instruction

arithmetic

executed

less of how the two quantities compare.

The last four of these instructions perform arithmetic operations, which

interrupt instruction can set

are checked for overflow.

no flags.

also sets the Trap 1 flag.

In the KI10 any condition that sets Overflow

SYSTEM REFERENCE

~69-

82.7

2-47

ARITHMETIC TESTING

CAl

Compare AC Immediate and Skip if Condition Satisfied

[ 30

|
[m] 4 Ji] x 1718
56

121314

" 89

Compare AC with E (ie with the word 0, E) and skip the next instruction in
sequence if the condition specified by M is satisfied.
CAl

Compare AC Immediate but Do Not Skip

300

CAIL

Compare AC Immediate and Skip if AC Less than £

301

CAIE

Compare AC Immediate and Skip if Equal

302

CAILE

Compare AC Immediate and Skip if AC Less than

303

CAIA

Compare AC Immediate but Always Skip

304

CAIGE

Compare AC Immediate and Skip if AC Greater than

305

Compare AC Immediate and Skip if Not Equal

306

Compare AC Immediate and Skip if AC Greater than £

307

or Equal to £

CAIN

CAIG

CAM

[
0

or Equal to £

CAl is a no-op.

Compare AC with Memory and Skip if Condition Satisfied

[m[ 4 1] x |

121314

1718

Compare AC with the contents of location E and skip the next instruction in
sequence if the condition specified by M is satisfied. The pair of numbers
compared may be either both fixed or both normalized floating point.

CAM

Compare AC with Memory but Do Not Skip

310

CAM is a no-op that references memory.

CAML

Compare AC with Memory and Skip if AC Less

311

CAME

Compare AC with Memory and Skip if Equal
Compare AC with Memory and Skip if AC Less

313

CAMLE

CAMA
CAMGE

312

or Equal

Compare AC with Memory but Always Skip
Compare AC with Memory and Skip if AC Greater

314
315

or Equal

CAMN

CAMG

Compare AC with Memory and Skip if Not Equal
Compare AC with Memory and Skip if AC Greater

JUMP

Jump if AC Condition Satisfied

[ m |

[
1213 14

x|
1718

316
317

]

Compare AC (fixed or floating) with zero, and if the condition specified by

SYSTEM REFERENCE

-70-

2-48

CENTRAL PROCESSOR

JUMP is a no-op (instruction
code 320 has this mnemonic
for symmetry).

M is satisfied,

JUMP

Do Not Jump

320

JUMPL

Jump if AC Less than Zero

321

JUMPE

Jump if AC Equal to Zero

322

JUMPLE

Jump if AC Less than or Equal to Zero

323

JUMPA

Jump Always

324

JUMPGE

Jump if AC Greater than or Equal to Zero

325

JUMPN

Jump if AC Not Equal to Zero

326

JUMPG

Jump if AC Greater than Zero

327

SKiP

Skip if Memory Condition Satisfied

| M| 4 1] x |

121314

1718

l
35

the next instruction in sequence if the condition specified by
M is satisfied.

If A is nonzero also place the contents of location E in AC.

has mnemonic SKIP for sym-

metry.)

SKIPA is a convenient way to

tering a loop.

Compare the contents (fixed or floating) of location E with zero, and skip

If 4 is zero, SKIP is a no-op;
otherwise it is equivalent to
MOVE. (Instruction code 330

load an accumulator and skip
over an instruction upon en-

the next instruction from location E and continue

sequential operation from there.

take

§2.7

SKIP

Do Not Skip

SKIPL

Skip if Memory Less than Zero

331

SKIPE
SKIPLE

Skip if Memory Equal to Zero
|
Skip if Memory Less than or Equal to Zero

332
333

SKIPA

Skip Always

334

SKIPGE

Skip if Memory Greater than or Equal to Zero

335

SKIPN

Skip if Memory Not Equal to Zero

336

SKIPG

Skip if Memory Greater than Zero

337

A0QJ

34
0

‘

330

Add One to AC and Jump if Condition Satisfied

| M|
56

|1l
1213 14

1718

Increment AC by one and place the result back in AC.

|
35

Compare the result

with zero, and if the condition specified by M is satisfied, take the next instruction from location £ and continue sequential operation from there. If

AC originally contained 23° — 1, set the Overflow and Carry 1 flags; if —1,
set Carry O and Carry 1.

A0J

Add One to AC but Do Not Jump

340

AQJL

Add One to AC and Jump if Less than Zero

341

AQJE

Add One to AC and Jump if Equal to Zero

342

AQJLE

Add One to AC and Jump if Less than or Equal to Zero

343

SYSTEM REFERENCE

-71-

§2.7

AQJA

ARITHMETIC TESTING

2-49

Add One to AC and Jump Always

344

Add One to AC and Jump if Greater than or Equal
to Zero

345

AOJN

Add One to AC and Jump if Not Equal to Zero

346

AQ0JG

Add One to AC and Jump if Greater than Zero

347

A0S |

Add One to Memory and Skip if Condition Satisfied

AQJGE

[ 35
0

[ M| 4 i x |

121314

1718

]

Increment the contents of location £ by one and place the result back in E.
Compare the result with zero, and skip the next instruction in sequence if

the condition specified by M is satisfied.

If location E originally contained

235 —1, set the Overflow and Carry 1 flags; if —1, set Carry 0 and Carry 1.
If A is nonzero also place the result in AC.

A0S

Add One to Memory but Do Not Skip

350

AOSL

Add One to Memory and Skip if Less than Zero

351

AOSE

Add One to Memory and Skip if Equal to Zero

352

AQOSLE

Add One to Memory and Skip if Less than or Equal

353

to Zero

‘

AQSA

Add One to Memory and Skip Always

354

AOSGE

Add One to Memory and Skip if Greater than or
Equal to Zero

355

AOSN

Add One to Memory and Skip if Not Equal to Zero

356

A0SG

Add One to Memory and Skip if Greater than Zero

357

S0J

Subtract One from AC and Jump if Condition Satisfied

L 36
0

[

mM] 4 [1f x |

121314

17 18

Decrement AC by one and place the result back in AC. Compare the result

with zero, and if the condition specified by M is satisfied, take the next instruction from location £ and continue sequential operation from there. If

AC originally contained —23%, set the Overflow and Carry O flags; if any other
nonzero number, set Carry O and Carry 1.
Subtract One from AC but Do Not Jump

360

SOJL

Subtract One from AC and Jump if Less than Zero

361

SOJE

Subtract One from AC and Jump if Equal to Zero

362

Subtract One from AC and Jump if Less than or

363

S0J

SOJLE

Equal to Zero

SYSTEM REFERENCE

~-72-

2-50

CENTRAL PROCESSOR

SOJA

S0JGE

8§2.7

Subtract One from AC and Jump Always

364

Subtract One from AC and Jump if Greater than or

365

Equal to Zero

SOJN

Subtract One from AC and Jump if Not Equal to Zero

366

S0JG

Subtract One from AC and Jump if Greater than Zero

367

S0S

Subtract One from Memory and Skip if Condition Satisfied

L 37
0

[M]|
4 Jff x ]

121314

1718

Decrement the contents of location E by one and place the result back in E.
Compare the result with zero, and skip the next instruction in sequence if
the condition specified by M is satisfied.

If location E originally contained

—23%, set the Overflow and Carry O flags; if any other nonzero number, set
Carry 0 and Carry 1.

If A is nonzero also place the result in AC.

S0S

Subtract One from Memory but Do Not Skip

370 -

SOSL

Subtract One from Memory and Skip if Less than Zero

371

SOSE

Subtract One from Memory and Skip if Equal to Zero 372

SOSLE

Subtract One from Memory and Skip if Less than or
Equal to Zero

373
.

SOSA

Subtract One from Memory and Skip Always

374

SOSGE

Subtract One from Memory and Skip if Greater

375

than or Equal to Zero

SOSN

Subtract One from Memory and Skip if Not Equal

376

to Zero

S0SG

Subtract One from Memory and Skip if Greater
than Zero

377

Some of these instructions are useful for determining the relative values of

fixed and floating point numbers; others are convenient for controlling
iterative processes by counting.

AOSE is especially useful in an interlock

procedure in a multiprocessor system.

Suppose memory contains a routine

that .must be available to two processors but cannot be used by both at once.

When one processor finishes the routine it sets location LOCK to —1. Either
processor can then test the interlock and make it busy with no possibility of
This procedure is invalid in
the KA10 if the programmer

letting the other one in, as AOSE cannot be interrupted once it starts to

modify the addressed location.

SYSTEM REFERENCE

~-73-

LOGICAL TESTING AND MODIFICATION

§2.8

LOCK

AOSE
JRST

SETOM

LOCK

2-51

;Skip to ‘interlocked code only if

is making use of the drum
split feature (which is not
used by any DEC equipment).

:LOCK is zero after addition

:Interlocked code starts here
;Unlock

Since it takes several days to count to 2%, it is alright to keep testing the
lock.

2.8

LOGICAL TESTING AND MODIFICATION

These eight instructions use a mask to modify and/or test selected bits in
AC. The bits are those that correspond to ls in the mask and they are
referred to as the “masked bits”. The programmer chooses the mask, the
. way in which the masked bits are to be modified, and the condition the
masked bits must satisfy to produce a skip.

The basic mnemonics are three letters beginning with T. The second letter

selects the mask and the manner in which it is used.

Letter

Effect

Right

AC right is masked by E (AC is masked

Left

AC left is masked by E (AC is masked by

Direct

AC is masked by the contents of loca-

AC is masked by the contents of location E with left and right halves inter-

Mask

Swapped

by the word O, F)
the word E,Q)
tion E

changed

The third letter determines the way in which those bits selected by the mask
are modified.

Modification

Effect on AC

Letter

None

Zeros
Complement
Ones

Z
C
O

Places Os in all masked bit positions
Complements all masked bits
Places 1s in all masked bit positions

An additional letter may be appended to indicate the mode, which spec-

ifies the condition the masked bits must satisfy to produce a sKip.

SYSTEM REFERENCE

-/4-

2-52

CENTRAL PROCESSOR

These mode names are con-

Mode

sistent with those for arithmetic testing and derive from

Never

the test method, which ands

Equal

AC with the mask and tests

Suffix

Never skip
E

Skip if all masked bits equal O

Always skip

whether the result is equal to

Always

Not Equal

convenient

to think of the

modes

Every

Effect

|
_

zero or is not equal to zero.

The programmer may find it

§2.8

Skip if not all masked bits equal 0
(at least one bit is 1)

and Not
Every: every masked bit is 0

If the mnemonic has no suffix there is never any skip, and the instruction is
a no-op if there is also no modification; an A suffix produces an uncondi-

or not every masked bit is 0.

tional skip — the skip always occurs regardless of the state of the masked
bits.
Note that the skip condition must be satisfied by the state of the

masked bits prior to any modification called for by the instruction.

TRN

Test Right, No Modification, and Skip if Condition Satisfied

| 60

7809

[]

1213 14

]

1718

If the bits in AC right corresponding to 1s in E satisfy the condition specified
by M, skip the next instruction in sequence. AC is unaffected.
TRN is a no-op.

TRN

Test Right, No Modification, but Do Not Skip

TRNE

Test Right, No Modification, and Skip if All

Masked Bits Equal O

600
_

602

TRNA

Test Right, No Modification, but Always Skip

604

TRNN

Test Right, No Modification, and Skip if Not

606

All Masked Bits Equal O

TRZ

[

Test Right, Zeros, and Skip if Condition Satisfied

[m[
56

789

[
121314

x |

1718

]
35

If the bits in AC right corresponding to 1s in E satisfy the condition specified
by M, skip the next instruction in sequence. Change the masked AC bits to

Os; the rest of AC is unaffected.
TRZ

Test Right, Zeros, but Do Not Skip

620

TRZE

Test Right, Zeros, and Skip if All Masked Bits

622

TRZA

Test Right, Zeros, but Always Skip

624

TRZN

Test Right, Zeros, and Skip if Not All Masked

626

Equaled O

Bits Equaled O

~75§2.8
TRC

|64

[

SYSTEM REFERENCE

LOGICAL TESTING AND MODIFICATION

2-53

Test Right, Complement, and Skip if Condition Satisfied

ml]

789

4 [ x ]
121314

1718

If the bits in AC right corresponding to 1s in E satisfy the condition specified
by M, skip the next instruction in sequence.
bits; the rest of AC is unaffected.

Complement the masked AC

TRC

Test Right, Complement, but Do Not Skip

640

TRCE

Test Right, Complement, and Skip if All Masked

642

Bits Equaled 0

TRCA

Test Right, Complement, but Always Skip

644

TRCN

Test Right, Complement, and Skip if Not All

646

Masked Bits Equaled O

TRO

66
0

Test Right, Ones, and Skip if Condition Satisfied

[ml 4

789

[ x

121314

1718

]
35

If the bits in AC right corresponding to 1s in E satisfy the condition specified
by M, skip the next instruction in sequence. Change the masked AC bits to

1s; the rest of AC is unaffected.

TRO

Test Right, Ones, but Do Not Skip

TROE

Test Right, Ones, and Skip if All Masked Bits
Equaled O

TROA

Test Right, Ones, but Always Skip

664

TRON

Test Right, Ones, and Skip if Not All Masked

666

Bits Equaled O

TLN

660
662

Test Left,‘ No Maodification, and Skip if Condition Satisfied

| 60

[mMD]

789

Jif

121314

]

1718

]
35

If the bits in AC left corresponding to 1s in E satisfy the condition specified
by M, skip the next instruction in sequence. AC is unaffected.

TLN

Test Left, No Modification, but Do Not Skip

601

TLNE

Test Left, No Modification, and Skip if All

603

TLNA

Test Left, No Modification, but Always Skip

605

TLNN

Test Left, No Modification, and Skip if Not

607

Masked Bits Equal O

All Masked Bits Equal 0

TLN is a no-op.

SYSTEM REFERENCE

-76-

2-54

CENTRAL PROCESSOR

TLZ

§2.8

Test Left, Zeros, and Skip if Condition Satisfied

[mfif 4

789

Jif x |

1213 14

1718

If the bits in AC left corresponding to 1s in E satisfy the condition specified
by M, skip the next instruction in sequence. Change the masked AC bits to
Os; the rest of AC is unaffected.

TLZ

Test Left, Zeros, but Do Not Skip

621

TLZE

Test Left, Zeros, and Skip if All Masked Bits

623

Equaled O

TLZA

Test Left, Zeros, but Always Skip

625

TLZN

Test Left, Zeros, and Skip if Not All Masked

627

Bits Equaled O

TLC

Test Left, Complement, and Skip if Condition Satisfied

|64
0

7809

Jif x |

121314

1718

)

35
-

If the bits in AC left corresponding to 1s in E satisfy the condition specified
by M, skip the next instruction in sequence.

bits; the rest of AC is unaffected.

Complement the masked AC

TLC

Test Left, Complement, but Do Not Skip

641

TLCE

Test Left, Complement, and ‘Skip' if All Masked

643

Bits Equaled O

TLCA

Test Left, Complement, but Always Skip

645

TLCN

Test Left, Complement, and Skip if Not All

647

Masked Bits Equaled 0

TLO

Test Left, Ones, and Skip if Condition Satisfied

66
0

|mMl|]
56

789

|1l
121314

|
1718

If the bits in AC left corresponding to 1s in E satisfy the condition specified
by M, skip the next instruction in sequence. Change the masked AC bits to

Is; the rest of AC is unaffected.
TLO

Test Left, Ones, but Do Not Skip

661

TLOE

Test Left, Ones, and Skip if All Masked Bits

663

TLOA

Test Left, Ones, but Always Skip

665

TLON

Test Left, Ones, and Skip if Not All Masked
Bits Equaled O

667

Equaled O

-7/~

§2.8

‘

TDN

|61

SYSTEM REFERENCE

LOGICAL TESTING AND MODIFICATION

2-55

Test Direct, No Modification, and Skip if Condition Satisfied

[mfo]

4 [if x T

789

1213 14

1718

]

If the bits in AC corresponding to 1s in the contents of location E satisfy the
condition specified by M, skip the next instruction in sequence.

affected.

AC is un-

TDN

Test Direct, No Modification, but Do Not Skip

610

TDN is a no-op that refer-

TONE

Test Direct, No Modification, and Skip if All

612

ences memory.

Masked Bits Equal
O
TDNA

Test Direct, No Modification, but Always Skip

614

TDNN

Test Direct, No Modification, and Skip if Not

616

All Masked Bits Equal 0

TDZ

|63

, 0

| Test Direct, Zeros, and Skip if Condition Satisfied

[mlo]

7809

4 ] x ]
121314

1718

]
35

If the bits in AC corresponding to 1s in the contents of location E satisfy the

condition specified by M, skip the next instruction in sequence. Change the
masked AC bits to Os; the rest of AC is unaffected.
TDZ

Test Direct, Zeros, but Do Not Skip

630

TDZE

Test Direct, Zeros, and Skip if All Masked Bits

632

Equaled O

TDZA

Test Direct, Zeros, but Always Skip

634

TDZN

Test Direct, Zeros, and Skip if Not All Masked

636

Bits Equaled O

TDC

L 65

Test Direct, Complement, and Skip if Condition Satisfied

[m]o[ a4 [ X ]

789

121314

17 18

|
35

If the bits in AC corresponding to 1s in the contents of location E satisfy the

condition specified by M, skip the next instruction in sequence. Complement
the masked AC bits; the rest of AC is unaffected.

TDC

Test Direct, Complement, but Do Not Skip

650

TDCE

Test Direct, Complement, and Skip if All Masked

652

TDCA

Test Direct, Complement, but Always Skip

654

TDCN

Test Direct, Complement, and Skip if Not All
Masked Bits Equaled O

656

Bits Equaled O

SYSTEM REFERENCE
2-56

CENTRAL PROCESSOR
TDO

§2.8

Test Direct, Ones, and Skip if Condition Satisfied

67
0

|mpl
56

789

121314

1718

If the bits in AC corresponding to 1s in the contents of location E satisfy the

condition specified by M, skip the next instruction in sequence. Change the
masked AC bits to 1s; the rest of AC is unaffected.

TDO

Test Direct, Ones, but Do Not Skip

670

TDOE

Test Direct, Ones, and Skip if All Masked Bits
Equaled O

672

TDOA

Test Direct, Ones, but Always Skip

674

TDON

Test Direct, Ones, and Skip if Not All Masked
Bits Equaled O

TSN

676
’

Test Swapped, No Modification, and Skip if Condition Satisfied

|[mMfi|-4
56

789

121314

1718

If the bits in AC corresponding to 1s in the contents of location E with its
left and right halves swapped satisfy the condition specified by M, skip the
next instruction in sequence. AC is unaffected.
TSN is a no-op that refer-

TSN

Test Swapped, No Modification, but Do Not Skip

611

ences memory.

TSNE
o

Test Swapped, No Modification, and Skip if All
Masked Bits Equal O

613

TSNA

Test Swapped, No Modification, but Always Skip

TSNN

Test Swapped, No Modification, and Skip if Not

615

617

All Masked Bits Equal O

182

L
0

Test Swapped, Zeros, and Skip if Condition Satisfied

|mp

7809

4 [ff x |
121314

1718

]

If the bits in AC corresponding to 1s in the contents of location E with its
left and right halves swapped satisfy the condition specified by M, skip the
next instruction in sequence.

Change the masked AC bits to Os; the rest of

AC is unaffected.
TSZ

Test Swapped, Zeros, but Do Not Skip

631

TSZE

Test Swapped, Zeros, and Skip if All Masked Bits

633

Equaled O

TSZA

Test Swapped, Zeros, but Always Skip

635

TSZN

Test Swapped, Zeros, and Skip if Not All Masked

637

Bits Equaled O

SYSTEM REFERENCE

~79-

§2.8

LOGICAL TESTING AND MODIFICATION

TSC

2-57

Test Swapped, Complement, and Skip if Condition Satisfied

|mp]
56

7809

[1]

121314

1718

If the bits in AC corresponding to 1s in the contents of location E with its

left and right halves swapped satisfy the condition specified by M, skip the
next instruction in sequence.

Complement the masked AC bits; the rest of

AC is unaffected.

TSC

Test Swapped, Complement, but Do Not Skip

TSCE

Test Swapped, Complement, and Skip if All

651

653

Masked Bits Equaled O

TSCA

Test Swapped, Complement, but Always Skip

655

TSCN

Test Swapped, Complement, and Skip if Not

657

All Masked Bits Equaled O

TSO

Test Swapped, Ones, and Skip if Condition Satisfied

| 67

|Mp|

789

121314

1718

]

.35

If the bits in AC corresponding to 1s in the contents of location E with its
left and right halves swapped satisfy the condition specified by M, skip the

next instruction in sequence. Change the masked AC bits to 1s; the rest of
AC is unaffected.

TSO

Test Swapped, Ones, but Do Not Skip

671

TSOE

Test Swapped, Ones, and Skip if All Masked Bits
Equaled O

673

TSOA

Test Swapped, Ones, but Always Skip

TSON

Test Swapped, Ones, and Skip if Not All Masked
Bits Equaled O

675
677

With these instructions any bit throughout all of memory can be used as a

program flag, although an ordinary memory location containing flags must
be moved to an accumulator for testing or modification.

The usual pro-

cedure, since locations 1-17 are addressable as index registers, is to use AC 0

as a register of flags (often addressed symbolically as F).

Unless one frequently tests flags in both halves of F simultaneously, it is
generally most convenient to select bits by 1s right in the address part of the
instruction word.

A given bit selected by a half word mask M is then set by

one of these:

TRO

F.,M

TLO

F,M

SYSTEM REFERENCE

-80-

CENTRAL PROCESSOR

2-58

8§2.9

and tested and cleared by one of these:

TRZE

F,M

TRZN

F,M

TLZE

F,M

TLZN

F,M

Suppose we wish to skip if both bits 34 and 35 are 1 in location L. The
following suffices.
SETCM

F,L

TRNE

F,3

We can refer to a flag in a given bit position within a word as flag X, where X
is a binary number containing a single 1 in the same bit position as the flag.
This sequence determines whether flags X and Y in the right half of accumulator F are both on:
TRC

F,X+Y

;Complement flags X and Y

TRCE

F.X+Y

;Test both and restore original states

:Do this if not both on
;Skip to here if both on

2.9

PROGRAM CONTROL

The program control class of instructions includes the unimplemented user
operations [discussed in the next section] and the arithmetic and logical test

instructions. Some instructions in this class are no-ops, as are a few of the
instructions for performing logical operations. The most commonly used
no-op is JFCL, which is discussed below. No-ops among the instructions
previously discussed are SETA, SETAI, SETMM, CAI, CAM, JUMP, TRN,
TLN, TDN, TSN. Of these, SETA, SETAI, CAI, JUMP, TRN and TLN do
not use the calculated effective address to reference memory. Hence in these
instructions one can store any information in bits 18-35 without fear of

attempting to address a location outside a user block or in a memory that

does not exist.

The present section treats all program control instructions other than
those mentioned above and in-out instructions that test input conditions
[§2.12]. All but one of these are jumps, although the exception causes the
processor to execute an instruction
at an arbitrary location and may therefore be regarded as a jump with an immediate and automatic return. Also,
all but two of the jumps are unconditional; one exception tests various flags,
'

the other tests an accumulator.

Several of the jump instructions save the current contents of the program
counter PC in the right half of an accumulator or memory location and save
the states of various flags in the left half. The bits saved in the left half of
FLOATING
UNDERFLOW

FLOATING

OVERFLOW

CARRY
| CARRY
0
'
2

FIRST

ggsg

USER

ADDRESS

USER | v Tout | PuBLIC m:hlé?TE TRAP 2|

TRAP 1

owvipe|

SYSTEM REFERENCE

_81-

2-59

PROGRAM CONTROL

§2.9

this PC word in KI10 user mode are as shown here. In the KA10, bits 7—10
are not used. In KI10 executive mode, bit 6 receives the same flag although
it has a different meaning, and bit O receives a different flag altogether [see
below]. In either processor all unused bit positions are cleared.
The following lists the left PC-word bit positions that receive information
and explains the meaning of the flags at the time they are saved. Certain
instructions can set up these flags to restore them to their original states
following an interruption or to control specific situations. The explanations
assume the flags reflect normal circumstances — not arbitrary rigging. In the
following an X in a mnemonic indicates any letter (or none) that may appear
in the given position to specify the mode, eg ADDX comprises ADD,

Note that nothing is stored in
bits 13-17, so when the PC
word is addressed indirectly it
can produce neither indexing
nor further indirect addressing.

ADDI, ADDM, ADDB.
Bit

Meaning of
a 1 in the Bit

Overflow — any of the following has occurred:
A single instruction has set onz of the carry flags (bits 1 and 2)
without setting the other.

An MULX has multiplied —235 by itself (product 27°).

An IMULX has multiplied two numbers with product = 2% or
‘

An FIX or FIXR has 'fetched an operand with exponent > 35.
Floating Overflow has been set (bit 3).

No Divide has been set (bit 12).

when the flags are saved in

KI10 executive mode, bit 0

An ASH or ASHC has left shifted a 1 out of bit 1 in a positive
number or a 0 out in a negative number.

< =23%,

In user mode, bit O reflects
the state of Overflow. But

Carry 0 — if set without Carry 1 (bit 2) being set, causes Overflow to
be set and indicates that one of the following has occurred:

represents the Disable Bypass
flag, which the Monitor uses

to control certain aspects of
the execution of an instruction by an executive XCT
[see below and §2.15]. Although these are two separate

flags that are read in different
circumstances, when a PC
word is used to restore or set

up the flags, bit O conditions
both of them.

Remember [§2.5], overflow
is determined directly from

An ADDX has added two negative numbers with sum < —2%.

the

carries,

not

from the

An SUBX has subtracted a positive number from a negative number with difference < —2%.

flags.

The

carry

flags give

meaningful information only
if no more than one instruction that can set them occurs

An SOJX or SOSX has decremented —235.
But if set with Carry 1, indicates that one of these nonoverflow
events has occurred:

In an ADDX both summands were negative, or their signs differed
and their magnitudes were equal or the positive one was the
greater in magnitude.

In an SUBX the signs of the operands were the same and AC was
the greater or the two were equal, or the signs of the operands
differed and AC was negative.

An AOJX or AOSX has incremented —1.

An SOJX or SOSX has decremented a nonzero number other than
-235.

An MOVNJX has negated zero.

between clearing and reading
them.

SYSTEM REFERENCE

-82-

CENTRAL PROCESSOR

2-60

§ 2.9

Carry 1 — if set without Carry O (bit 1) being set, causes Overflow to
be set and indicates that one of the following has occurred:

An ADDX has added two positive numbers with sum => 235,

An SUBX has subtracted a negative number from a positive number with difference > 235,

An AOJX or AOSX has incremented 23° — 1.

An MOVNX or MOVMX has negated —235.
But if set with Carry 0, indicates that one of the nonoverflow events
listed under Carry O has occurred.

Floating Overflow — any of the following has set Overflow:
In a

floating point instruction other than FLTR, DMOVN,
DMOVNM or DFN, the exponent of the result was > 127.
Floating Underflow (bit 11) has been set.

No Divide (bit 12) has been set in an FDVX, FDVRX or DFDV.
First Part Done — the processor is responding to a priority interrupt
between the parts of a two-part instruction or to a page failure in the
second part. A 1 in this bit indicates that the first part has been
completed, and this fact should be taken into account when the .
processor restarts the instruction at the beginning upon the return to
- Although this flag is set upon
completion of the first part of
every interruptable two-part

instruction, it is seldom rele-

vant to the programmer as it

is always cleared by the completion of the second part.
The flag is seen only in an
interruption, and its effect on
the repeated first part is automatic provided only that it is
properly
restored at
the
return.

the interrupted program. Eg if an ILDB or IDPB is interrupted after
the processing of the pointer but before the processing of the byte,
the pointer now points not to the last byte, but rather to the byte
that should be handled at the return [§2.13]. Thus when the processor restarts the instruction, it must retrieve the pointer but not
increment it.

Besides indicating a priority interrupt in the middle of a byte
instruction, the KI10 First Part Done indicates a page failure in the
processing of a byte, in the transfer of the second (low order) word
in a DMOVEM or DMOVMN, or in a noninterrupt data IO instruction that results from a block IO instruction (following the processing
of the pointer [§2.12]).
User — the processor is in user mode [§ §2.15, 2.16].

In the KA10, User In-out is
applicable only to user mode

[§2.16]. In the KI10 this flag
has the stated effect when the
processor is in user mode, but
is used in executive mode to
control certain aspects of the

execution

of an instruction

by an executive XCT [see

below and §2.15].

User In-out — even with the processor in user mode, there are no
instruction restrictions (but memory restrictions still apply).

Public (KI10 only) — the last instruction performed was fetched
from a public area of memory, ie the processor is in user mode public
or executive mode supervisor.

Address Failure Inhibit (KI10 only) — an address failure cannot occur
during the next instruction [§2.15].

Trap 2 (K110 only) — if bit 10 is not also set, arithmetic overflow
has occurred. If trapsare enabled, the setting of this flag immediately
causes one [82.14].
At present, bits 9 and 10 cannot be set
together by any hardware condition.

-83-

§2.9
10

SYSTEM REFERENCE

PROGRAM CONTROL

2-61

Trap 1 (KI10 only) — if bit 9 is not also set, pushdo
wn overflow

occurred.
causes

one

has

If traps are enabled, the setting of this flag immedia
tely
[§2.14].

present,

together by any hardware condition.

bits 9 and

cannot be set

Floating Underflow — in a floating point instruct
ion other than
FLTR, DMOVN, DMOVNM or DF N, the exponen
t of the result
was < —128 and Overflow and Floating Overflow have
been set.

No Divide — any of the following has set Overflow:
In a DIVX the dividend was greater than or equal to

the divisor.

In an IDIVX the divisor was zero.
In an FDVX, FDVRX or DFDV the divisor was
zero, or the
dividend fraction was greater than or equal to twice
the divisor
fraction in magnitude; in either case F loating Overflo
w has been set.

XCT

Execute

256

121314

]

)

1718

Execute the contents of location E as an instruction. Any
instruction may
be executed, including another XCT. If an XCT executes a
skip instruction,
the skip is relative to the location of the XCT (the first
XCT if there are
If an XCT executes a jump, program flow is altered

specified by the jump (no matter how many XCTs precede
a jump
tion, when PC is saved it contains an address one greater than

the first XCT in the chain).

JFFO

cause floating division to fail.

several in a chain).

If normalized operands are
used, only a zero divisor can

instruc-

the location of

user XCT or any

KA10

XCT acts as described here,
and the 4 portion of the instruction

ignored.

But in

KI10 executive mode this instruction performs as stated

only when
4 is zero. Nonzero
A results in a so called “executive XCT”, whose ramifications are far more widespread

than indicated here [for details refer to §2.15].

‘

Jump if Find First One

243

]

1213 14

]

1718

If AC contains zero, clear AC A+1 and go on to the next instructio
n in

sequence.

If AC is not zero, count the number of leading Os in it (Os to the left

of
the leftmost 1), and place the count in AC A+1. Take
the next instruction
from location E and continue sequential operation from
there.
In either case AC is unaffected, the original content

s of AC A+1 are lost.

Note that when AC is negative, the second accumulator
is cleared, just as it would be
if AC were zero.

left-normalize

teger in AC:

JFCL

|
o

Jump on Flag and Clear

255

|
89

1]
121314

]

1718

If any flag specified by F is set, clear it and take the next

B
35

instruction from

JFFO

AC,+1

ASH

AC,—1(AC+1)

in-

-8l

SYSTEM REFERENCE

§2.9

CENTRAL PROCESSOR

2-62

location E, continuing sequential operatien from there. Bits 9-12 are programmed as follows.

This instruction can be used
simply to clear the selected
flags by having the jump address point to the next consecutive location, as in

JFCL

17,.+1

which clears all four flags
without disrupting the normal program sequence. A
JFCL that selects no flag is
the fastest no-op as it neither
fetches nor stores an operand,
and bits 18-35 of the instruction word can be used to
store information.

Flag Selected by a 1

Overflow

Carry O

Carry 1

Floating Overflow

To select one or a combination of these flags (which are among those described above) the programmer can specify the equivalent of an AC address
that places 1s in the appropriate bits, but MAacro recognizes mnemonics for
some of the 13-bit instruction codes (bits 0-12).

JFCL
JFCL
JFCL
JFCL
JECL
JFCL

JFCL
JovV
JCRYO
JCRY1
JCRY
JFOV

|
0

No-op
Jump on Overflow
Jump on Carry O
Jump on Carry 1
Jump on Carry O or 1
Jump on Floating Overflow

O,
10,
4,
2,
6,
1,

25500
25540
25520
25510
25530
25504

Jump to Subroutine

JSR

The A portion of this instruction is ignored.

Bit

264

[

1] x

121314

1718

Place the current contents of the flags (as described above) in the left half of
location E and the contents of PC in the right half (at this time PC contains
an address one greater than the location of the JSR instruction). Take the
next instruction from location E + 1 and continue sequential operation from
there.

The flags are unaffected except First Part Done, Address Failure

Inhibit, and the trap flags, which are cleared.

While the processor is in user mode, if this instruction is executed as an
interrupt instruction or by a KA10 MUUO, bit 5 of the PC word stored
is 1 and the processor leaves user mode, clearing Public. (In the KI10 an
interrupt that is not dismissed automatically returns control to kernel mode.)

|
0

Jump and Save PC

JSP

265

|
89

|1 x
121314

|
1718

Y
35

Place the current contents of the flags (as described above) in AC left and

-85-

§2.9

SYSTEM REFERENCE

PROGRAM CONTROL

2-63

the contents of PC in AC right (at this time PC contains an address one
greater than the location of the JSP instruction). Take the next instruction

from location E and continue sequential operation from there.

The flags

are unaffected except First Part Done, Address Failure Inhibit, and the trap

flags, which are cleared.

While the processor is in user mode, if this instruction is executed as an

interrupt instruction or by a KA10 MUUO, bit 5 of the PC word stored

is 1 and the processor leaves user mode, clearing Public. (In the KI10 an
interrupt that is not dismissed automatically returns control to kernel mode.)

JRST

Jump and Restore

254

|
89

1213 14

]

1718

|
35

Perform the functions specified by F, then take the next instruction from
location E and continue sequential operation from there.
programmed as follows.

Bit
9

Bits 9-12 are

Function Produced by a 1
Restore the channel on which the highest priority interrupt is cur-

rently being held [§2.13].

Unless the User In-out flag is set, this function cannot be
performed in a user program. Instead of restoring the channel, it
acts just like an MUUO [§2.10].

Halt the processor.

instruction that caused the halt, and PC displays the jump address
(the location from which the next instruction will be taken if the

next had the JRST been re-

When it stops, the MA lights on the console display an address one greater than that of the location containing the

operator causes the processor to resume operation without changing

PC).

Unless

the

User

In-out

flag

performed in a user program.

set,

this function cannot be

Instead of halting the processor, it

acts just like an MUUO [§2.10].
11

Restore the flags listed above from the left half of the word in the
last location referenced in the effective address calculation. Hence

actually
displays the
address of the location that
would have been executed
placed by a no-op. So except

for

JRST

priority

interrupt, MA points to the
location one beyond that
containing

that

the

caused

the

instruction

halt.

This

instruction -is ordinarily the

JRST or perhaps an XCT, but

could even be a UUQ.

to restore flags requires that the JRST instruction use indexing or

indirect addressing.

Restoration of all but the user and Public flags is directly according
to the contents of the corresponding bits as given above: a flag is set

by a 1 in the bit, cleared by a 0. A 1 in bit 5 sets User but a 0 has no

effect, so the Monitor can restart a user program by restoring flags
but the user cannot leave user mode by this method. A O in bit 6
clears User In-out, but a 1 sets it only if the

by the Monitor, ie if User is clear.

JRSTis being performed

A 1 in bit 7 sets Public, buta 0

By manipulating the contents
of the left half word used to
restore the flags, the program-

mer can set them up in any
desired way except that a

user program

cannot clear

User or set User In-out, and
no public program can clear

-86-

SYSTEM REFERENCE

clears it only if the JRST is being performed in executive mode with

Public for itself. As an ex-

a 1 in bit 5 (fe User is being set). These conditions imply that the

ample, setting First Part Done

processor is entering user mode: hence the user cannot enter con-

prevents incrementing in the
next ILDB, IDPB or noninter-

cealed mode by clearing Public; and although the supervisor can
place the processor in user mode concealed, it cannot use this

rupt KI10 block IO instruction provided there is no inter-

procedure to enter kernel mode.

vening JSR, JSP or PUSHJ.

Note that if overflow traps are

enabled, setting a trap flag

§2.9

CENTRAL PROCESSOR

2-64

KA10. Enter User mode.

The user program starts at relocated

location E.

immediately causes one.

KI10. The instruction is simply a jump except when fetched from
a nonpublic area, in which case it clears Public. In other words a

location containing a JRST 1, is a valid entry to a nonpublic area
and the instruction places the processor in concealed or kernel mode.

To produce one or a combination of these functions the programmer can

specify the equivalent of an AC address that places 1s in the appropriate bits,

but Macro recognizes mnemonics for the most important 13-bit instruction
codes (bits 0-12).

JRST

JRST O,
JRST

JEN completes an interrupt

by restoring the channel and
restoring the flags for the
interrupted program.

10,

Jump

25400

Jump and Restore Interrupt
Channel

25440

HALT

JRST 4,

Halt

25420

JRSTF

JRST 2,

Jump and Restore Flags

25410

PORTAL

JRST

Allow Nonpublic Entry (KI10)

25404

JEN

JRST

12,

Jump and Enable

25450

Jump to User Program (KA10)

In a JRSTF or JEN the flags are restored from bits 0—12 of the final word
retrieved in the effective address calculation; hence any JRST with a 1 in bit
11 must use indirect addressing or indexing, which takes extra time. If the
PC word was stored in AC (as in a JSP), a common procedure is to use AC to
index a zero address (eg, JRSTF (AC)), so its right half becomes the effective (jump) address. If the PC word was stored in core (as in a JSR), one
must address it indirectly (remember, bits 13-17 of the PC word are clear,
so again its right half is the effective address). A JRSTF (AC) is con-

siderably faster than a

JRSTF @PCWORD.

CaurION

Giving a JRSTF or JEN without indexing or
indirect addressing restores the flags from the
_instruction code itself.

While the KA10 is in user mode, if this instruction is executed as an

interrupt instruction or by an MUUO, bit 5 of the PC word stored is 1 and
the processor leaves user mode.

SYSTEM REFERENCE

-87-

§2.9

PROGRAM CONTROL

2-65

JFCL is the only jump that can test any of the flags directly. In fact it is
the only basic program control instruction that can do so — several of the
flags can be tested as processor conditions by in-out instructions, but these
are ordinarily illegal in user programs anyway. But JFCL can test only four
of the flags, and it saves no information for a subsequent return from a sub-

routine. Hence it serves as a branch point for entry into either one of two
main paths, which may or may not have a later point in common. FEg, it may
test the carry flags simply to take appropriate action in a double precision

fixed point routine.

JSR and JSP are regularly used to call subroutines. They are unconditional, but the execution of such an instruction can be the result of a
decision made by any conditional skip or jump. In the case of the flags, a
basic overflow test and subroutine call can be made as follows.
JoV

JRST

;Faster than skipping

JSR

OVRFLO

;Jump over this if Overflow clear

If we wish to go to the DIVERR routine when No Divideis set, we must first
" read the flags into a test accumulator T and then use a test 1nstruct10n

JSP

T,.+1

;Store flags but continue in sequence

TLNE

T,40

;40 left selects bit 12

JSR

DIVERR

;Skip this if No Divide clear

A subroutine called by a JSR must have its entry point reserved for the PC

word.

Hence it is nonreentrant: the JSR modifies memory so the subroutine
cannot be shared with other programs. The JSP requires an accumulator,

but it is faster and is convenient for argument passing. To return from a
JSR-called subroutine one usually addresses the PC word indirectly, returning to the location following the JSR.

from a JSP.

But there are two ways to get back

We can address the PC word indirectly with a

JRST @AC (or
JRSTF @AC if the flags must be restored), but we can also get it by
addressing AC as an index register: JRST (AC). By using the second return
method we can place N words of data for the subroutine immediately after
the

call,

and

return

the

location

following

the

data

JRST N(ACQ).

by giving a

Suppose we wish to call a print subroutine and supply the words from
which the characters are to be taken.

following:
JSP

T,PRINT

Our main program would contain the

;Put PC word in accumulator T
;Text inserted here by ASCIZ pseudo-

;instruction,

which automatically

;places a zero (null) character at the

;end

;Next instruction here

The fastest skip is CAIA in.
the KA10, TRNA in the KI10.

SYSTEM REFERENCE

_88-

§29

CENTRAL PROCESSOR

2-66

The subroutine can use T as a byte pointer which already addresses the first
word of data. 'For the print routine, characters are loaded into another
accumulator CH.
PRINT:

HRLI
ILDB

T,440700
CH,T

;Initialize left half of pointer
;Increment pointer and load byte

JUMPE

CH,I1(T)

;Upon reaching zero character return
;to one beyond last data word
;Print routine

JRST

PRINT+1

;Get next character

Jump and Save AC

JSA

266

121314

1718

Place AC in location F, the effective address E in AC left, and the contents
of PC in AC right (at this time PC contains an address one greater than the location of the JSA instruction).

Take the next instruction from location

E+1 and continue sequential operation from there. The original contents
of E are lost.

While the KA10 is in user mode, if this instruction is executed as an
interrupt instruction or by an MUUO, bit 5 of the PC.word stored is 1 and
the processor leaves user mode.

JRA

Jump and Restore AC

267
0

|
89

||
121314

1718

Place the contents of the location addressed by AC left into AC.

Take the

next instruction from location F and continue sequential operation from
there.

A JSA combines advantages of the JSR and JSP.

JSA does modify

memory, but it saves PC in an accumulator without losing its previous
contents (at a cost of not saving the flags). It is thus convenient for multipleentry subroutines. In a-subroutine called by a JSR, the returning JRST must

refer to the (single) entry point. Since a JRA can retrieve the original PC by
addressing AC as an index register, it is independent of any entry point

-89-

§2.9

SYSTEM REFERENCE

PROGRAM CONTROL

without tying up an accumulator to the extent a JSP

would.

especially useful for nesting subroutines, as shown by

this example.

2-67

The accumulator contents saved by a JSA are restored
by a JRA paired
with it despite intervening JSA-JRA pairs.
Hence these instructions are

;Main program

;ISA
S1:

17,81

;Call to first subroutine (4)

S2:

;First subroutine starts here

fiA'

nsé

;Call to second subroutine (B)

:J RA

i7,( 17)

;Return to 4 + 1 in main program

S3:

;Second subroutine starts here

;ISA

17,S3

;Call to third subroutine (C)

:JRA

17,(17)

;Return to B + 1 in first subroutine

; Third subroutine starts here

.:I RA

17,(17)

;Return to C + 1 in second subroutine

To call the next deeper subroutine at any level,
a JSA places £ and PC in the
left and right of AC 17, saves the previous content
s of AC 17 in E (the first
subroutine location), and jumps to
£+ 1. To return to the next higher level,
a JRA restores the previous contents of AC 17
from the location addressed
by AC 17 left (the first subroutine location)
and jumps to the location
addressed by AC 17 right (the location following
the JSA in the higher subroutine). If NV lines of data for the next subrout
ine follow a JSA, the return
to the location following the data is made by giving
a JRA 17,N(17).

PUSHJ

|
0

Push Down and Jump

260

|
'

Jif
121314

]
1718

|
3s

Add one to each half of AC and place the result back in AC. If the addition

causes the count in AC left to reach zero, set the Pushdown Overflow
flag
in the KA10, set the Trap 2 flag in the KI10. Then place
the current
contents of the flags (as described above) in the left half of the location
now ,
addressed by AC right and the contents of PC in the right half
of that
location (at this time PC contains an address one greater than the location
of

the PUSHJ instruction). Take the next instruction from location E and
continue sequential operation from there.

In the KI10a PUSHJ executed
as

interrupt

cannot set Trap 2.

instruction

SYSTEM REFERENCE

-90-

§2.9

CENTRAL PROCESSOR

2-68

The flags are unaffected except First Part Done, Address Failure Inhibit,
and the trap flags, which are cleared. However, pushdown overflow overrides
the Trap 2 clear, so if the list overflows, Trap 2 sets and the KI10 traps
instead of jumping. The original contents of the location added to the list
are lost.

Note: The KA10 increments the two halves of AC by adding 1 000001,
to the entire register. In the K110 the two halves are handled independently.
While the processor is in user mode, if this instruction is executed as an
interrupt instruction or by a KA10 MUUOQ, bit 5 of the PC word stored is 1
and the processor leaves user mode, clearing Public. (In the KI10 an
interrupt that is not dismissed automatically returns control to kernel mode.)

Pop Up and Jump

POPJ

The effective address E is
ignored. In the K110 a POPJ
executed as an interrupt instruction cannot set Trap 2.

263

|4 |1l

121314

1718

B
35

Subtract one from each half of AC and place the result back in AC. If the
subtraction causes the count in AC left to reach — 1, set the Pushdown Overflow flag in the KA10, set the Trap 2 flag in the KI1O0. Take the next in- struction from the location addressed by the right half of the location that
was addressed by AC right prior to the decrementing, and continue
sequential operation from there.

Note: The KA10 decrements the two halves of AC by subtracting
1000001, from the entire register. In the KI10 the two halves are handled

independently.

The address of the top item in the pushdown list is kept in the right half

of the pointer in AC, and the program can keep a control count in the left
half. In the KA10, incrementing and decrementing both halves of AC
together is effected by adding and subtracting 1 0000015. Hence a count of
—2 in AC left is increased to zero if 2!® — 1 is incremented in AC right, and
conversely, 1 in AC left is decreased to —1 if zero is decremented in AC right.
Since the pushdown list is independent of the subroutine called, PUSHJPOPJ can be used like JSA-JRA for multiple entries. Moreover, ordering by
level is inherent in the structure of a pushdown list [§2.2], so paired
PUSHI-POP]J instructions are excellent for nesting subroutines: there can be
any number of subroutines at any level, each with more subroutines nested
within it. Recursive subroutines are also possible.

Unlike JSA-JRA, the pushdown instructions tie up an accumulator, but
the usual procedure is to keep both data and jump addresses in a single list so
only one AC is required for the most complex pushdown operations. The
programmer must keep track of whether a given entry in the list is data or
a PC word; in other words, every item inserted by a PUSH should be
removed by a POP, and every PUSHJ should be matched by a POPJ. If flag

-91-

§2.10

SYSTEM REFERENCE

UNIMPLEMENTED OPERATIONS

2-69

restoration is desired, the returning
POPJ

can be replaced by
POP

P,AC

JRSTF

(AC)

which requires another accumulator.

If the flags are not important, data

may be stored in the left halves of the PC words in the stack, reducing the

required pushdown depth.
By trapping or checking overflow and keeping a control count in AC left, the
programmer can set a limit to the size of the list by starting the count

negative, or he can prevent the program from extracting more items than
there are in the list by starting the count at zero, but he cannot do both at
once.

If only jump addresses are kept in the list, the first procedure limits

the depth of nesting.

A technique to catch extra POPJs is to put a PC word
addressing an error routine at the bottom of the list,

2.10

UNIMPLEMENTED OPERATIONS

Codes not assigned as specific instructions act as unimplemented operations,
wherein the word given as an instruction is trapped and must be interpreted

by a routine included for this purpose by the programmer. Codes in the
range 001-077 are unimplemented user operations, or UUQs. Half of these
(001-037) are for the local use of the user or Monitor (LUUOs);
the other

half (040-077) are set aside for user communication with the Monitor
(MUUOs) and are interpreted by it (although they may be used by the
Monitor as well).

Codes 100 and above that are not used for instructions

are regarded as the “‘unassigned codes”; 000 is not regarded as a legal code

at all.

These are convenience mnemonics that mean nothing to

the assembler. UUOs are also
sometimes

called

“program-

med operators”,

Instructions that violate the instruction restrictions act in the same

manner as MUUGO:s.

Local Unimplemented User Operation

|001-037
0

|
89

[if
121314

]

1718

]
35

Store the instruction code, A and the effective address E in bits 0-8, 9-12
and

18-35

respectively of location 40; clear bits 13-17.

instruction contained in location 41.

Execute the

The original contents of location 40

are lost.
Every LUUO uses some pair of locations numbered 40 and 41, but which such pair depends upon the circumstances. An LUUO in a user program uses
relocated locations 40 and 41 and is thus entirely a part of and under control

If a single memory serves as
memory

number

for two

KA10 processors, the second

SYSTEM REFERENCE

~99-

(with the trap offset) uses
unrelocated 140-141 and 160161 respectively for each instance in which 40-41 and
60-61 are given here.
The

§2.10

CENTRAL PROCESSOR

2-70

of the user program. An LUUO in KA10 executive mode uses unrelocated
locations. In KI10 executive mode an LUUO uses locations 40 and 41 in
the executive process table.

offset does not apply to user

LUUOs as it is assumed the
Monitor would relocate these
to different physical blocks.

The actions of MUUOs and unassigned codes depend to a considerable
degree on the processor. All use at least two consecutive locations, where
the first receives the information specified above for an LUUO (in the KI10
a third nonconsecutive location is also used). The unassigned codes are
included so that the Monitor steps in when a user gives an incorrect code.
The code 000 acts in exactly the same way as an MUUO but is not a standard
communication code: it is included so that control returns to the Monitor

-should a user program wipe itself out.
The unassigned codes are
100-107, 114-117, 123 and
247.

Note that even in a dedicated
system, the program must still
define a user process table.

KI10. MUUOs and unassigned codes in user or executive mode act in

'exactly the same way.

They store the information specified above for an

LUUO in location 424 of the user process table, save the flags and PC (the
current PC word) in location 425, set up the flags and PC according to a new
PC word taken from a third location, and restart the processor in normal
sequence at the location then addressed by PC. In the PC word saved in
location 425, bit 0 may represent either Overflow or Disable Bypass
depending upon the mode the processor is in when the MUUO is given. If
the MUUO is given directly by the program, the address in the right half of
the PC word saved is one greater than the location of the MUUO; otherwise
it depends upon the circumstances in which the MUUO is executed. The
new PC word can be taken from among the eight locations in the user
process table listed here depending upon the mode at the time the MUUO is
" given, and whether or not it is executed as the result of a trap (page failure
or overflow).
Execution

Location

Kernel

No trap

430

Kernel

Trap

431

Supervisor

No trap

432

Supervisor

Trap

433

Mode

Note that if overflow trapsare’
enabled, setting a trap flag
immediately causes one.

Concealed

No trap

Concealed

Trap

Public

No trap

Public

Trap

- 434
435
- 436

437

There are no restrictions on the manner in which the new PC word of an
MUUO can set up the flags. It can switch the processor from any mode to
any other. A 1 in bit O sets both Overflow and Disable Bypass; a O clears
both. Hence bit 0 should be adjusted to produce the desired state in the flag

~ that is relevant to the mode the processor is entering.

KA10. MUUOs and unassigned codes, regardless of mode, perform
exactly the operations given above for an LUUO with the exception that

-93-

§2.11

SYSTEM REFERENCE

PROGRAMMING EXAMPLES

MUUOs use unrelocated 40-41 and unassigned codes use unrelocat
ed 60-61
(140-141 and 160-161 for a second processor). The unassigne
d codes are
100~127, 247 and 257. The codes 130-177, which are the floating
point
and byte manipulation instructions, are equivalent to the unassigne
d codes if
unimplemented, ie if the hardware for them is not included.
In this case
all codes 100~177 trap to unrelocated 60-61.
:
‘

The important point is that an MUUO or unassigned code results
in

vexecuting an instruction in an unrelocated location, ie an instruction under
the control of the Monitor.

This would most likely be a jump that leaves

user mode, saves the PC word and enters a routine to interpret
the

MUUO

configuration.

In the instruction descriptions, any reference to events
resulting from execution by an MUUO should be taken to include
the
unassigned and illegal codes as well.
’

2.11

PROGRAMMING EXAMPLES

Before continuing to input-output and related subjects, let us consider

some
simple programs that demonstrate the use of a variety of the
instructions
- described thus far.
The instruction repertoires of the KA10, the KI10 and the 166
processor
used in the PDP-6 are very similar, and most programs require no changes
to

run on any of them.

Because of minor differences and the fact that some

instructions are not available on the earlier machines, a program that

is to be

compatible with all three should have some way of distinguis
hing which

machine it is running on. This simple test suffices.
JFCL

17,.+1

;Clear flags

JRST

;Change PC

JFCL

1,PDP6

MOVNI

AC,1

AOBIN

AC,+1

JUMPN

AC,KA10

JRST

KI10

,
;PDP-6 has PC Change flag

;Others do not, make AC all 1s

;Increment both halves

; KA10 if AC= 1000000
;KITO

if AC=0

(no carry between

;halves)
Suppose we wish to count the number of 1s in a word.

:
We could of

course check every bit in the word. But there is a quicker way if
we remember that in any word and its twos complement the rightmost 1
is in the same
position, both words are all Os to the right of this 1, and no correspond
ing

bits are the same to the left (the parts of both words at the left of the

most 1 are complements).

right-

Hence using the negative of a word as a mask for

the word in a test instruction selects only the rightmost 1 for modificati
on.
The example uses three accumulators: the word being tested
(which is lost)
is in T, the count is kept in CNT, and the mask created in each
step is stored

in TEMP,

MOVEI

CNT,0

;Clear CNT

MOVN

TEMP,T

;Make mask to select rightmost 1

2-71
Note that in executive mode,
LUUOs

and

identically.

MUUOs

act

'SYSTEM REFERENCE

-9l

2-72

CENTRAL PROCESSOR

§2.11

TDZE

T,TEMP

;Clear rightmost 1 in T

AOJA

CNT,.—-2

;Increase count and jump back
;Skip to here if no Isleftin T

CNT is increased by one every time a 1 is deleted from T. After all 1s have
been removed, the TDZE skips.
In the standard algorithm for converting a number N to its equivalent in
base b, one performs the series of divisions

q./b

g,+r,/b

r, <b

q./b

gy+r3/b

rs<b

gn-1/b

0+r,/b

r,<b

The number in base b is then r,...ryryr,.

Eg the octal equivalent of 61

decimal is 75:

61/8

7+5/8

7/8

0+7/8

The following decimal print routine converts a 36-bit positive integer in
accumulator T to decimal and types it out. The contents of T and T + 1 are
destroyed.

The routine is called by a PUSHJ P, DECPNT where P is the

pushdown pointer.

DECPNT:
.

DECPN1:

PUSH

IDIVI

T,12
P, T+1

;125 = 10,4
;Save remainder

SKIPE

;All digits formed?

PUSHJ

P,DECPNT

:No, compute next one

POP
ADDI

P, T
T,60

;Yes, take out in opposite order
;Convert to ASCII (60 is code for 0)

JRST

TTYOUT

;Type out

This routine repeats the division until it produces a zero quotient. Hence it
suppresses leading zeros, but since it is executed at least once it outputs one

“0” if the number is zero. The TTYOUT routine returns with a POPJ P, to
DECPN1 until all digits are typed, then to the calling program.

Space can be saved in the pushdown stack by storing the computed digits
in the left halves of the locations that contain the jump addresses. This is
accomplished in the decimal print routine by making the followmg substitutions.

PUSH P,T+1 - HRLM T+1,(P)
POP

P,T

HLRZ

T,(P)

The routine can handle a 36-bit unsigned integer if the IDIVI T,12 is

SYSTEM REFERENCE

-05-

§2.11

PROGRAMMING EXAMPLES

2-73

replaced by

LSHC

T,-1D35

;Shift right 35 bits into T+1

LSH

T+1,—-1

;Vacate the T+1 sign bit

DIVI

T,12

;Divide double 1ength integer by 10

Many data processing situations involve searching for information in tables

and lists of all kinds.

Suppose we wish to find a particular item in a table
beginning at location TAB and containing
N items. Accumulator T contains

the item. The right half of A is used to index through the table, while the
left half keeps a control count to signal when a search is unsuccessful.

MOVSI

A,~N

CAMN

T,TAB(A)

JRST

FOUND

;Item found

AOBIN

A,.-2

;Try next item until left count =0

-Put
—N, 0 in A
;SKkip if current item not the one

;Item not in list

The location of the item (if found) is indicated by the number in the right
half of A (its address is that quantity plus TAB). A slightly different pro-

cedure would be

HRLZI

A,—-N

CAME

T, TAB(A)

AOBIN

A, .—1

JUMPL

A,FOUND

;Skip if current item is the one

;Jump if left count < 0

;Item not found

Locations used for a list can be scattered throughout memory if data is
kept in the left half of each location and the right half addresses the next

location in the list.

The final location is indicated by a zero right half. The
following routine finds the last half word item in the list. It is entered at
FIND with the first location in the list addressed by the right half of
accumulator T. At the end the final item is in T right.

FIND:

‘

MOVE

T,(T)

;Move next item to T

TRNE

T,777777

;9kip if AC right = 0

JRST

‘

HLRZS

;Move final item to right

The following counts the length of the list in accumulator CNT.
MOVEI

CNT,0

;Clear CNT

JUMPE

T,0OUT

;Jump out if T contains 0

HRRZ

T,(T)

;Get next address

AOJA

CNT,.—-2

;Count and go back

Double Precision Floating Point. The following are straightforward routines for handling double precision floating point arithmetic in software
format [ § 2.6 describes the floating point instructions].

DFAD:

UFA

A+1,M+1

;Sum of low parts to A+2

MACRO interprets a number
following 1D as decimal.

SYSTEM REFERENCE

_96_

2-74

CENTRAL PROCESSOR

8§2.12

These routines are given to

FADL

;Sum of high parts to A, A+1

show the mechanics of double
precision floating point operations. They produce correct

UFA

A+1,A+2

;Add low part of high sum to A+2

FADL

AA+2

;Add low sum to high sum

POPJ

DFN

AA+1

;Negate double length operand

PUSHJ

P,DFAD

;Call double floating add

DFN

AA+1

—M-AC)=AC-M

POPJ

results in all ordinary circumstances, but do not handle
pathological cases.

DFSB:

DFMP:

MOVEM A ,A+2

;Copy high AC operand in A+2

FMPR

A+2,M+1

;One cross product to A+2

FMPR

A+1,M

;Other to A+1

UFA

A+1,A+2

;Add cross products into A+2

FMPL

;High product to A, A+1

UFA

A+1,A+2

;Add low part to cross sum in A+2

FADL

A,A+2

;Add low sum to high part of product

POPJ

A double precision division is of the form

a+t cX2¥

b+dx2?

Using the relationship

A/b

q+rX2TM%/p

where g and r are the quotient and remainder produced by FDVL, the

following routine computes a double length quotient by the algorithm
q +(r - qgd) X2 -27

A
B

which gives a result correct to the next-to-last bit in the low order half.
DFDV:

FDVL

MOVN

A+2A

;Get high part of quotient
;Copy negative of quotient in A+2

FMPR =

A+2,M+1

;Multiply by lew part of divisor

UFA

A+1,A+2

;Add remainder

FDVR

A+2,M

FADL

A,A+2

POPJ

;Divide sum by high part of divisor
-

;Add result to original quotient
‘

2.12

INPUT-OUTPUT

The input-output instructions govern all transfers of data to and from the

-peripheral equipment, and also perform many operations within the proc-

SYSTEM REFERENCE

-97-

8§2.12

INPUT-OUTPUT

2-75

essor. . An instruction in the in-out class is designated by 111 in bits 0-2, ie

its left octal digit is 7.

instruction.

Bits 3—-9 address the device that is to respond to the

The format thus allows for 128 codes, two of which, 000 and

004 respectively, address the processor and priority interrupt, and are used

for the console as well.

The KA10 also uses the first two codes for the time

share hardware, but the KI10 has a separate code, 010, for this purpose.
A chart in Appendix A lists all devices for which codes have been assigned,
and gives their mnemonics and DEC option numbers.

Electrical and logical

specifications of the IO bus are given in the interface manual.

Bits 13-35 are the same as in all other instructions: they are the 7, X, and

.Y parts, which are used to calculate an effective address, set of conditions,
or mask to be used in the execution of the instruction. The remaining bits,
10—-12, select one of the following eight IO instructions.
NoTE

All instructions described in the remainder of this manual are in-out
instructions, which are affected by the time share instruction restric-

tions.

In the KA10 no in-out instruction can be performed by a user

mode program unless the User In-out flag is set.

In the KI10, in-out

instructions using device codes 740 and above are not restricted.

But

an instruction using a device code under 740 cannot be performed by a

user mode program unless User In-out is set and cannot be performed
in supervisor mode at all (in-out is normally handled in kernel mode).

Any in-out instruction that violates these restrictions does not perform
the functions given for it in the instruction description. Instead it acts
just like an MUUO [§2.10].
These restrictions will not be mentioned in the instruction descriptions, as'they apply to all instructions from this point on.

CONO

Conditions
Out

|20
.

910

E will always be regarded as

121314

being bits 18-35, even though

1718

it is actually placed on both
35

Set up device D with the effective initial conditions E. The number of condition bits in £ that are actually used depends on the device.

CONI

Conditions In

L7 |
0

|24l
910

121314

|
1718

Y
35

Read the input conditions from device D and store them in location £. The

number of condition bits stored depends on the device; the remaining bits
in location E are cleared.

halves of the bus and many

devices receive the information from the left half.

-98-

SYSTEM REFERENCE

§2.12

CENTRAL PROCESSOR

2-76

DATAO

Data Qut

(7]

Jualy
x |

910

121314

1718

Send the contents of location E to the data buffer in device D, and perform
whatever control operations are appropriate to the device.
The amount of data actually accepted by the device depends on the size
of its buffer, its mode of operation, etc. The original contents of location £
are unaffected.

DATAI

Data In

(7]

Joafq x |
910

121314

1718

Move the contents of the data buffer in device D to location E, and perform
‘whatever control operations are appropriate to the device.
The number of data bits stored depends on the size of the device buffer,
its mode of operation, etc. Bits in location E that do not receive data are
cleared.

CONSZ

Conditions In and Skip if Zero

L 7 Ja

[30 [1]] x |

210

121314

1718

| B
35

Test the input conditions from device D against the effective mask E. If all
condition bits selected by ls in E are Os, skip the next instruction in
sequence.

If the device supplies more than 18 condition bits, only the right 18 are

tested.

CONSO

Conditions In and Skip if One

(7]

[34]]
x |
1718
121314

910

]35

Test the input conditions from device D against the effective mask E. If any
condition bit selected by a 1in E is 1, skip the next instruction in sequence.
If the device supplies more than 18 condition bits, only the right 18 are
tested.

-99-

§2.12

INPUT-OUTPUT

BLKO

BLKI

Block In

(7]

2-77

Block Out

(7]
0o

SYSTEM REFERENCE

Jiof] x |

910

121314

1718

Joofi] x |

910

121314

y -]

1718

Add one to each half of a pointer in location E, and place the result back

in E.

Then perform a data 10 instruction in the same direction as the block

IO instruction,

using the

effective address.

right half of the incremented pointer as the

If the given instruction is a BLKO, perform a DATAO;

if a BLKI, perform a DATAL

‘

The remaining actions taken by this instruction depend on whether it is

executed as a priority interrupt instruction [ §2.13].
¢ Not as an Interrupt Instruction.

If the addition has caused the count in

the left half of the pointer to reach zero, go on to the next instruction in
sequence. Otherwise skip the next instruction.
& As an Interrupt Instruction.

If the addition has caused the count in the

‘left half of the pointer to reach zero, execute the instruction in the second
interrupt location for the channel.

Otherwise dismiss the interrupt and

return to the interrupted program.
Note:

block

effectively

instruction

whole

in-out

data handling subroutine. It
keeps track of the block location,
transfers
each
data
word, and determines when
the block is finished.

Initially the left half of the
pointer contains the negative

of the number of words in
the block, the right half contains an address one less than
that of the first word in the

block.

The KA1O increments the two halves of the pointer by adding

10000015 to the entire register.

In the KI10 the two halves are handled

independently.

The above eight instructions differ from one another in their total effect,
but they are not all different with respect to any given device. A BLKO acts
on a device in exactly the same way as a DATAO — the two differ only in

counting and other operations carried out within the processor and memory.
Similarly, no device can distinguish between a BLKI and a DATAI; and a
device always supplies the same input conditions during a CONI, CONSZ or

CONSO whether the program tests them or simply stores them.
Hence the eight instructions may be categorized as of four types, represented by the first four instructions described above. Moreover, a.complete

treatment of the programming of any device can be given in terms of these
fourinstructions, two of which are for input and two for output. The four
exhaust the types of information transfer that occur in the IO system, at

The word “input” used with-

least three of which are applicable to any given device. Thus all instruction

out qualification always refers

descriptions in the rest of this manual will be of the CONO, CONI, DATAO

to the transfer of data from

and DATALI instructions combined with the various device codes.

The dis-

cussion of each device will present timing information pertinent to device

operation, as internal device timing is dependent only upon the device and
not upon processor instruction time (which is given in Appendix.-C).

Every device requires initial conditions; these are sent by a CONO, which

the peripheral equipment into
the processor; “output” refers
to the transfer in the opposite

direction.

SYSTEM REFERENCE

~100-

2-78

CENTRAL PROCESSOR

§2.12

can supply up to eighteen bits of control information to the device control
register.

The program can determine the status of the device from up to
thirty-six bits of input conditions that can be read by a CONI (but only the

right eighteen can be tested by

a CONSZ or CONSO).

Some input bits

simply reflect initial conditions sent by a previous CONO; others are set up

output conditions but are subject to subsequent adjustment by the

device; and still others, such as status levels from a tape transport, have no
direct connection with output conditions.
Data is moved in and out in characters of various sizes or in full 36-bit

words.

Each transfer between memory and a device data buffer requires a

single DATAI or DATAO.

Every device has a CONO and CONI, but it may

have only one data instruction unless it is capable of both input and output.

A DATAI that addresses an
output-only

device

Eg, the paper tape reader has only a DATAI, the tape punch has only a

simply

DATAO, but the teletype has both. (A high speed device, such as a disk file,

clears location E. DATAI PI,

can be connected to a direct-access processor, which in turn is connected

(code 70044) produces only

directly

this effect as the priority in-

to memory by a separate memory bus and handles data auto-

terrupt has no data for input.

matically.

On the other hand a DATAO

DATALI for each transfer.)

that addresses an input-only

A Typical 10 Device. Every device has a 7-bit device selection network a

device is a no-op.
When the device code is

undefined or the addressed
device is not in the system,

This eliminates the need for the program to give a DATAO or

priority interrupt assignment, and at least two flags, Busy and Done, or some

equivalent.

The selection network decodes bits 3—-9 of the instruction so

that only the addressed device responds to signals sent by the processor over

a DATAQO, CONO or CONSO

the in-out bus.

is a no-op, a CONSZ is an
absolute skip, a DATAI or

must assign a channel to it.

CONI clears location F.

To use the device with the priority interrupt, the program
Then whenever an appropriate event occurs in

the device, it requests an interrupt on the assigned channel.

The Busy and Done flags together denote the basic state of the device.

When both are clear the device is idle.
CONO or DATAO sets Busy.

To place the device in operation, a

If the device will be used for output, the pro-

gram must give a DATAO that sends the first unit of data — a word or char-

Busy and Done both set is a
meaningless situation.

acter depending on how the device handles information. When the device has
processed a unit of data, it clears Busy and sets Done to indicate that it is
ready to receive new data for output, or that it has data ready for input.

In the former case the program would respond with a DATAO to send more
data; in the latter, with a DATAI to bring in the data that is ready.

If an

interrupt channel has been assigned to the device, the setting of Done signals
the program by requesting an interrupt; otherwise the program must keep
testing Done to determine when the device is ready.
All devices function basically as described above even though the number

of initial conditions varies considerably.

Besides Busy and Done flags, the
tape reader and punch have a Binary flag that determines the mode of
operation of the device with respect to the data it processes — alphanumeric

Occasionally a device with a
second
code
may
use a
DATAI or DATAO to transmit
additional control or
maintenance information.

or binary. The teletype has no binary flag, but it has two Busy flags and two
Done flags — one pair for input, another for output. A complicated device,
such as magnetic tape, may require two device codes to handle the large
number of conditions associated with it. Initial conditions for a tape system

include a transport address and an actual command the tape control is to
perform; input conditions include error flags and transport status levels.
Most IO devices involve motion of some sort, usually mechanical (in a
display only the electron beam moves).

With respect to mechanical motion

-101-

§2.12

SYSTEM REFERENCE

INPUT-OUTPUT

2-79

there are two types of devices, those that stay in motion and those that do
not.

Magnetic tape is an example of the former type. Here the device
executes a command (such as read, write, space forward) and the done flag
indicates when the entire operation is finished.

A separate data flag signals
each time the device is ready for the program to give a DATAI or DATAO,
but the tape keeps moving until an entire record or file has been processed.

Paper tape, on the other hand, stops after each transfer, but the program
need not give a new CONO every time.

The reader logic is set up so that a
DATALI not only reads the data, but also clears Done and sets Busy. Hence
if the instruction is given within a critical time, the tape moves continuously
and only two CONOs are required for a whole series of transfers: one to start

the tape, and one to stop it after the final DATAI.
Other devices operate in one or the other of these two ways but differ in

various respects.

The tape punch and teletype output are like the reader.

Teletype input is initiated by the operator striking a key rather than by the
program.

The card reader reads an entire card on a single CONO, with a

DATALI required -for each column.

The DECtape stays in motion, and the

program must give a CONO to stop it or it will go all the way to the end

Zone.

:
Readin Mode

This mode of processor operation provides a means of placing information

in memory without relying on a program already in memory or loading one

word at a time manually.

Its principal use is to read in a short loader
program which is then used for loading other information. A loader program

should ordinarily be used rather than readin mode, as a loader can check the
validity of the information read.

Pressing the readin key on the console activates readin mode by starting
the processor in a special hardware sequence that simulates a DATAI fol-

lowed by a series of BLKI instructions, all of which address the device whose

code is selected by the readin device switches at the left just above the
console operator panel.

Various devices can be used, and for each there are

special rules that must be followed.

But the readin mode characteristics of

any particular device are treated in the discussion of the device.

Here we

are concerned only with the general characteristics.

The information read is a block of data (such as a loader program) preceded by a pointer for the BLKI instructions.

The left half of the pointer
contains the negative of the number of words in the block, the right half

contains an address one less than that of the location that is to receive the

first word.

‘

To read in, the operator must set up the device he is using, set its code
into the readin device switches, and press the readin key. This key function
first duplicates the action of the console reset key, which clears both the
processor and the in-out equipment; in particular it places the processor in

executive mode, and in the KI10 selects kernel mode, selects physical page 0

for the executive process table, and disables overflow traps.
the

Following this

processor places the device in operation, brings the first word (the
pointer) into location 0, and then reads the data block, placing the words in

SYSTEM REFERENCE

-102-

2-80

CENTRAL PROCESSOR

§2.12

the locations specified by the pointer.

Data can be placed anywhere in
memory (including fast memory) except in location 0. The operation affects

none of memory except location 0 and the block area.

For the KI10 it is

recommended that read in be confined to the unpaged area, as bringing data
into locations above 337777 would require prior loading of the appropriate

pointers into the executive page map in physical page 0.

Upon completing the block, the processor halts only if the single instruc-

tion switch is on.

Otherwise it leaves readin mode and begins normal

operation. This is done in the KI10 by jumping to the location addressed
by the last word in the block, in the KA10 by executing the last word
as an instruction.

Console-Program Communication

Neither the processor nor the priority interrupt system require all four types
of IO instructions, so the program can make use of their device codes for
communicating with the console. Both processors have two instructions that
transfer data between console and program.

But in the KI10, the program

can actually operate some of the switches on the console. For this purpose
it uses a data-out instruction with the device code for the paper tape reader
(an input-only device). The KI10 program can also inspect the states of a .
number of operating and sense switches, but the bits for these are included

in the left half words of the standard input conditions for the interrupt

and processor [§§2.13, 2.14].

Macro also recognizes the
mnemonic

RSW

(Read

Switches) as equivalent
APR..

DATAI

DATAI APR,
[

Data Ih, Console

70004

7l
.

121314

1718

]
35

Read the contents of the console data switches into location E.

DATAO PI,
70054
0

Data Out, Console
7l x
121314

|
1718

]
35

Unless the console MI program disable switch is on, display the contents of
location E in the console memory indicators and turn on the triangular light

beside the words PROGRAM DATA just above the indicators (turn off the
light beside MEMORY DATA).
Once the indicators have been loaded by the program, no address condi-

tion selected from the console

[§82.18, 2.19]

can load them until the

operator turns on the MI program disable switch, executes a key function

that references memory, or presses the reset key.

SYSTEM REFERENCE

-103-

§2.13

PRIORITY INTERRUPT

DATAO PTR,

[

2-81

Operating Data Qut, Console

71054

121314

1718

Unless the MI program disabie switch is on, set up the console address and
address-condition switches according to the contents of location E as shown
(a 1 in a bit turns on the switch, a 0 turns it off).
INST

DATA

ADDRESS|

FETCH | FETCH | WRITE

| BREAK | PAGING | PAGING

8
-

For complete information on the use of these switches, see §2.19.

2.13

PRIORITY INTERRUPT

Most in-out devices must be serviced infrequently relative to the processor
speed and only a small amount of processor time is required to service them,
but they must be serviced within a short time after they request it. Failure

to service within the specified time (which varies among devices) can often
result in loss of information and certainly results in operating the device

below its maximum speed.

The priority interrupt is designed with these

considerations in mind, ie the use of interruptions in the current program

sequence facilitates concurrent operation of the main program and a number

of peripheral devices.

The hardware also allows conditions internal to the

processor to signal the program by requesting an interrupt.
Interrupt requests are handled through seven channels arranged in a
priority chain, with assignment of devices to channels entirely at the discretion of the programmer.

To assign a device to a channel, the program sends

the number of the channel to the device control register as part of the conditions given by a CONO (usually bits 33—35).

Channels are numbered 1-7,

with 1 having the highest priority; a zero assignment disconnects the device
from the interrupt channels altogether.

Any number of devices can be

connected to a single channel, and some can be connected to two channels
(eg a device may signal that data is ready on one channel, that an error has
occurred on another).

Interrupt Requests. When a device requires service it sends an interrupt
request signal over the in-out bus to its assigned channel in the processor. If
the channel is on, the processor accepts the request at the next memory
access unless the processor is either starting an interrupt on any channel or
holding an interrupt on the same channel.

are

console,

all

pushbutton-

the flipflops,
not the buttons.

USER

ADDRESS SWITCHES

KI10

struction of. course controls

EXEC

the

switiches

flipflop combinations; the in-

The request signal is a level, so

it remains on the bus until turned off by the program (CONO, DATAO or

-104-

SYSTEM REFERENCE

CENTRAL PROCESSOR

2-82

§2.13

DATAI). Thus if a request is not accepted because of the conditions given
above, it will be accepted when those conditions no longer hold.

A single

The request signal is generally

channel will shut out all others of lower priority if every time its service

derived from a flag that is set

routine dismisses the interrupt, a device assigned to it is already waiting with

by various conditions in the

device. Often associated with

these flags are enabling flags,
where the setting of some

another request. The program can usually trigger a request from a device but

delay its acceptance by turning on the channel later.

Starting an Interrupt. After a request is accepted the channel must wait

device condition flag can re-

for the interrupt to start.

No interrupts can be started unless the priority

quest

interrupt system is active.

Furthermore, the processor cannot start an

interrupt

the

assigned channel only if the
associated enabling flag is also
set.

The enabling flags are in

turn controlled by the conditions supplied to the device by

interrupt if it is already holding an interrupt on a channel with priority
higher than those on which requests have been accepted (in other words if

the current program is a higher priority interrupt routine).

If there is a

higher priority channel waiting, the processor stops the current program to

Eg a device may

start an interrupt on the waiting channel that has highest priority. The inter-

have half a dozen flags to
indicate various internal condi-

rupt starts following the retrieval of an instruction, following the retrieval of

a CONO.

tions that may require service
by an interrupt; by setting up

the associated enabling flags,

an address word in an effective address calculation (including the second calculation using the pointer in a byte instruction), or following a transfer in a

BLT.

The KI10 can also interrupt the relatively long process of calculating

determine

the quotient in double floating division. When an interrupt starts, PC points

which conditions shall actual-

to the interrupted instruction, so that a correct return can later be made to

the

program

can

ly request interrupts in any
given circumstances.

the interrupted program.
For the

KA10 two fixed memory locations are associated with each

channel: unrelocated locations 40 + 2N and 41 + 2N, where N is the channel
Interrupt locations for a sec-

number.

ond processor are 140 + 2N

so on to channel 7 which uses 56 and 57. The KA10 starts an interrupt for

and 141 + 2N.

Channel 1 uses locations 42 and 43, channel 2 uses 44 and 45, and

channel N by executing the instruction in the first interrupt location for the
channel, /e location 40+ 2N.

Even though the processor may be in user

mode when an interrupt occurs, the interrupt operations are performed in
executive mode.

‘

The KI10 starts an interrupt by sending an interrupt-granted signal for the
channel on which it has accepted a request.

This signal goes out on the bus

and is transmitted serially from one device to the next. Upon receiving the
grant, a device that is not requesting an interrupt on the specified channel
sends the signal on to the next device.

A device that is requesting an inter-

Note that there are therefore

rupt on the specified channel terminates the signal path and sends an

two orders of priority asso-

interrupt function word back to the processor.

ciated with a KI10 interrupt:

first the channel, and then for
all

devices

requesting inter-

rupts simultaneously on the
same channel, proximity

the processor on the bus.

fixed

locations associated

The KI10 also has a pair of

with each channel, and these have the same

numbers as in the KA10 but are locations in the executive process table.

These locations however need not be used. The interrupt function word sent
by the device may specify a standard interrupt using the fixed locations, or
an equivalent interrupt using a pair-of locations specified by the function

word, or some other interrupt function entirely. The format of the function
word and the operations the processor performs in response to the function

selected by bits 3—5 of the word are as follows.
FUNCTION

[

\
3

I
56

INTERRUPT ADDRESS

INCREMENT
1718

*I
.

'SYSTEM REFERENCE

-105-

§2.13

2-83

PRIORITY INTERRUPT

Bits 3-5

Interrupt Function

Processor waiting or no response. If the latter, perform a standard

1
2

for use with the KA10 will

Standard interrupt — execute the instruction in location 40 + 2N
of the executive process table.

KI10 bus, where it always
requests a standard interrupt

Dispatch — execute the instruction in the location specified by

by providing no response to

bits 18-35.

A device designed originally

interrupt (see function 1).

work when connected to the

the grant.

This means that

for simultaneous requests on

Increment — add the contents of bits 6—17 to the contents of the

a given channel, all KI10 de-

location specified by bits 18-35.

vices have priority over KA10

The increment is a fixed point

number in twos complement notation, bit 6 being the sign, and

devices.

bit 17 corresponding to bit 35 of the memory word.
4

DATAO — do a DATAO for this device using the contents of
bits 18-35 as the effective address.

DATAI

—

do a DATAI for this device using the contents of

bits 18-35 as the effective address.

At present, functions 6 and
7

Not used — reserved by DEC.

produce standard interrupts.

Not used — reserved by DEC.

Regardless of what mode the processor is in when an interrupt occurs, the

interrupt operations are performed in kernel mode.

An instruction executed in response to an interrupt request and not under
coritrol of PC is referred to elsewhere in this manual as being ““executed as an

interrupt instruction”.

Some instructions, when so executed, have different

effects than they do when performed in other circumstances.

And the dif-

ference is not due merely to being performed in an interrupt location or in
response (by the program) to an interrupt.

To be an interrupt instruction,

an instruction must be executed in the first or second interrupt location for
a channel, in direct response by the hardware (rather than by the program)
to a request on that channel.

performed.

82.12 describes the two ways a BLKO is

If a BLKO is contained in an interrupt routine called by a JSR,

it is not “executed as an interrupt instruction” even in the unlikely event the
routine is stored within the interrupt locations and the BLKO is executed by
an XCT.

The special effects produced by different types of interrupt

instructions depend upon the processor.
KI10 Interrupt Instructions. Besides instructions, the KI10 can perform
other interrupt operations as described above.

No interrupt operation can

set Overflow or either of the trap flags; hence an overflow trap can never
occur as a direct result of an interrupt.

A page failure that occurs in an

interrupt operation is never trapped; instead it sets the In-out Page Failure
flag, which requests an interrupt on the channel assigned to the processor
[§2.14].

These considerations of course do not apply to a service routine

called by an interrupt instruction.

The interrupt instructions executed in a

standard or dispatch interrupt fall into three categories.
¢ AOSX, SKIPX, SOSX, CONSX, BLKX.

If the skip condition spec1f1ed by

the instruction is satisfied, the processor dismisses the interrupt and returns
immediately to the interrupted program (ie it returns control to the un-

SYSTEM REFERENCE

-106-

2-84

CENTRAL PROCESSOR

§2.13

Satisfaction of the condition

changed PC).

does not change PC, as this

the instruction contained in the second interrupt location.

would skip the next instruc-

If the skip condition is not satisfied, the processor executes

tion in the interrupted program. In effect the instruction

Caurion

skips back to the interrupted

In the second interrupt location, a skip instruction

program by skipping the ‘sec-

whose condition is not satisfied hangs up the pro-

ond interrupt location.

cessor, which will keep repeating the instruction

Note that the interpretation of a BLKI or BLKO as a

until the condition is satisfied.

skip instruction is consistent
with the description given in

§2.12, the condition being
that the count is not zero.

¢ JSR, JSP, PUSHJ, MUUO.

The processor holds an interrupt on the
channel, takes the next instruction from the location specified by the jump

(as indicated by the newly changed PC), and enters either kernel mode or the

mode specified by the new PC word of the MUUQ. Hence the instruction is
usually a jump to a service routine handled by the Monitor.
¢ All Other Instructions.
instruction,

general

the

processor simply

executes

the

dismisses the interrupt, and then returns to the interrupted

program. If the instruction is a jump (other than those mentioned above),
the processor jumps to the newly specified location; but it dismisses the
interrupt and returns to the mode it was already in when the interrupt
occurred.

Hence it effectively returns to the interrupted program but in a

different place, and the original contents of PC are lost.

Since the interrupt operations are performed in kernel mode regardless of

the actual mode of the processor, an XCT is performed as an executive XCT

[§2.15]. The ultimate effect of the XCT depends of course on the instruction executed — and its effect is as described here for the various categories.
CAuTION

Neither an LUUO nor a BLT will function in a
reasonable

manner

interrupt

instruction.

Therefore do not use them.

KA10 Interrupt Instructions. In the KA10 the interrupt instructions fall
into two categories.

¢ Non-10 Instructions.

After executing a non-10 interrupt instruction, the

processor holds an interrupt on the channel and returns control to PC.
Hence the instruction is usually a jump to a service routine. If the processor
is in user mode and the interrupt instruction is a JSR, JSP, PUSHIJ, JSA or

JRST, the processor leaves user mode (the Monitor thus handles all interrupt
routines [§2.16]).

If the interrupt instruction is not a jump, the processor continues the
interrupted program while holding an interrupt — in other words it now
treats the interrupted program as an interrupt routine. Eg the instruction
might just move a word to a particular location.

Such procedures are

usually reserved for maintenance routines or very sophisticated programs.
# Block or Data 10 Instructions.

One or the other of two actions can result
from executing one of these as an interrupt instruction.

If the instruc_tion' in 40+ 2N is a BLKI or BLKO and the block is not
finished (ie the count does not cause the left half of the pointer to reach

SYSTEM REFERENCE

-107-

2-85

PRIORITY INTERRUPT

§2.13

zero), the processor dismisses the interrupt and returns to the interrupted
program. The same action results if the instruction is a DATAI or DATAO.
If the instruction in 40 + 2N is a BLKI or BLKO and the count does reach
zero, the processor executes the instruction in location 41 +2N. This
cannot be an 10 instruction and the actions that result from its execution
as an interrupt instruction are those given above for non-lIO instructions.
CauTtion

The execution, as an interrupt instruction, of a
CONO, CONI, CONSO or CONSZ in location
40 + 2N or any 10 instruction in location 41 + 2N
hangs up the processor.

Dismissing an Interrupt. Unless the interrupt operation dismisses the
interrupt automatically, the processor holds an interrupt until the program

dismisses it, even if the interrupt routine is itself interrupted by a higher
priority channel. Thus interrupts can be held on a number of channels
simultaneously, but from the time an interrupt is started until it is dismissed,
no interrupt can be started on that channel or any channel of lower priority
(requests, however, can be accepted on lower priority channels).
A routine dismisses the interrupt by using a JEN (JRST 12)) to return to

the interrupted program (the interrupt system must be active when the JEN
is given). This instruction restores the channel on which the interrupt is
being held, so it can again accept requests, and interrupts can be started on
it and lower priority channels. JEN also restores the flags, whose states were
saved in the left half of the PC word if the routine was called by a JSR,
JSP, PUSHJ, or in the KI10, an MUUO. If flag restoration is not desired,
a

JRST 10, can be used instead.
Caurron

An interrupt routine must dismiss the interrupt

when it returns to the interrupted program, or its

channel and all channels of lower priority will be
disabled, and the processor will treat the new
program as a continuation of the interrupt routine.

Priority Interrupt Conditions. The program can control the priority interrupt system by means of condition 10 instructions. The device code is
004, mnemonic PI.

CONO PI,

|
0

Conditions Qut, Priority Interrupt

70060

]
121314

1718

B
35

Perform the functions specified by the effective conditions E as shown (a 1
in a bit produces the indicated function, a O has no effect).

SYSTEM REFERENCE

-108-

2-86

CENTRAL PROCESSOR
OROP PROGRAM
REQUESTS ON

INITIATE
INTERRUPTS

SELECTED

CHANNELS

FOWER | PARITY PARITYIERROR \
CLEAR | CLEAR

|DISABLE| ENABLE

FLAG | FLAG

INTERRUPT

DEACTIVATE
|

§2.13
ACTIVATE
Pl

[

CLEnR

SYSTEM

231

TURN | TURN

SELECTED CHANNELS

26127

SELECT CHANNELS FOR BITS 22,24, 25,26
'

2913

321!

Notes.
Bits

18-21

are actually for

processor conditions [ §2.14].

Prevent the setting of the Parity Error flag from requesting an
interrupt on the channel assigned to the processor.

Enable the setting of the Parity Error flag to request an interrupt
on the channel assigned to the processor.

KI10 only:

On channels selected by 1s in bits 29-35, turn off any

interrupt requests made previously by the program (via bit 24).

Deactivate

the priority

interrupt system, turn off all channels,

eliminate all interrupt requests that have already been accepted but
are still waiting, and dismiss all interrupts that are currently being
held.

Request interrupts on channels selected by 1s in bits 29-35, and
force the processor to accept them even on channels that are off.

KA10: There is at most one interrupt on a given channel, and a
request is lost if it is made by this means to a channel on which an
interrupt is already being held.

KI10: The request remains indefinitely, so as soon as an interrupt
is completed on a given channel another is started, until the request

is turned off by a CONO that selects the same channel and has a
I in bit 22.

Turn on the channels selected by 1s in bits 29-35 so interrupt
requests can be accepted on them.

Turn off the channels selected by

1s in bits 29-35, so interrupt

requests cannot be accepted on them unless made by a CONO PI,
with a 1 in bit 24.
27

Deactivate the priority interrupt system. The processor can then still

accept requests, but it can neither start nor dismiss an interrupt.
28

Activate the priority interrupt system so the processor can accept
requests and can start, hold and dismiss interrupts.

CONI PI,

70064
0

Conditions In, Priority Interrupt

]
121314

|
1718

|
.

Read the status of the priority interrupt (as well as several bits of KA10
processor conditions and nine KI10 console operating switches) into loca-

tion £ as shown.

-109§2.13

INST | DATA

WRiTE

FETCH | FETCH

|ADORESS|ADDRESS|
STOP.

EXEC | USER |

SYSTEM REFERENCE

PRIORITY INTERRUPT

| BREAK | PAGING | PAGING |

2-87

PAR | NXM
STOP

STOP

PROGRAM REQUESTS ON CHANNELS
I

THARR

]

51|

PARITY ERROR
INTERRUPT

ENABLED

POWER | PARITY

FAILURE|

ERROR

/
_

I
20

INTERRUPT IN PROGRESS ON CHANNELS

]

6|71

ACTIVE

|2
29

Notes.

Channels that are on are indicated by 1s in bits 29-35; 1s in bits 21-27
indicate channels on which interrupts are currently being held; 1s in bits
11-17 (which are available only in the KI10) indicate channels that are
receiving interrupt requests generated by

a CONO PI, with a 1 in bit 24.
A 1 in bit 28 means the priority interrupt system is active.
The remaining conditions read by this instruction have nothing to do with
the interrupt. Bits 0—8 are available only in the K110, where they reflect the
. settings

of various console operating switches; for information on these

switches refer to §2.19.

Bits 18-20 actually read KA10 processor status

conditions [§2.14] as follows.

Ac power has failed.

The program should save PC, the flags and fast

memory in core, and halt the processor.

The

'
setting of this flag requests an interrupt on the channel

assigned to the processor.

If the flag remains set for 5 ms, the

processor is cleared.

A word with even parity has been read from core memory. If bit 20
is set, the setting of the Parity Error flag requests an interrupt on the
channel assigned to the processor, at which time PC points to the
instruction being performed or to the one following it.

Timing. The time a device must wait for an interrupt to start depends on
the number of channels in use,.and how long the service routines are for
devices on higher priority channels. If only one device is using interrupts,
it never waits longer than 10 us with the KI10. With the KA10 it need never
wait longer than the time required for the processor to finish the instruction
that is being performed when the request is made.

The maximum time can
be considered to be about 15 us for FDVL, but a ridiculously long shift

could take over 35 us.

Special Considerations. On a return to an interrupted program, the processor always starts the interrupted instruction over from the beginning. This
causes special problems in a BLT and in byte manipulation.

CHANNELS ON

5|6

3¢

SYSTEM REFERENCE
2-88

-110-

CENTRAL PROCESSOR

8§2.13

An interrupt can start following any transfer in a BLT.

When one does,

the BLT puts the pointer (which has counted off the number of transfers

already made) back in AC. Then when the instruction is restarted following
the interrupt, it actually starts with the next transfer.

This means that if

interrupts are in use, the programmer cannot use the accumulator that holds
the pointer as an index registér in the same BLT, he cannot have the BLT

load AC except by the final transfer, and he cannot expect AC to be the
same after the instruction as it was before.
An interrupt can also start in the second effective address calculation in a
two-part byte instruction. When this happens, First Part Done is set.

This

flag is saved as bit 4 of a PC word, and if it is restored by the interrupt
routine when the interrupt is dismissed, it prevents a restarted ILDB or

IDPB from incrementing the pointer a second time.

This means that the

interrupt routine must check the flag before using the same pointer, as it
now points to the next byte.

Giving an ILDB or IDPB would skip a byte.

And if the routine restores the flag, the interrupted ILDB or IDPB would
process the same byte the routine did.

Programming Suggestions. The Monitor handles all interrupts for user
programs. Even if the User In-out flag is set, a user program generally cannot
reference the interrupt locations to set them up.

Procedures for informing

the Monitor of the interrupt requirements of a user program are discussed in

the Monitor manual.

For those who do program priority interrupt routines, there are several

rules to remember.
¢ No requests can be accepted, not even on higher prlonty channels, while

a break is starting.

Therefore do not use lengthy effective address calcula-

tions in interrupt instructions.
'
¢ Most in-out devices are designed to drop an interrupt request when the
program responds, usually with a DATAI or DATAO.

If an interrupt is

handled neither by a BLKI or BLKO interrupt instruction nor by a service
routine, the programmer must make sure the deviceis configured to drop the

request on receipt of whatever response
the program does give.

¢ The interrupt instruction that calls the routine must save PC if there is to
be a return to the interrupted program.

Generally a JSR is used as it saves

both PC and the flags, and it uses no accumulator.
¢ The principal function of an interrupt routine is to respond to the situation that caused the interrupt.

FEg computations that can be performed

outside the routine should not be included within it.

¢ If the routine uses a UUO it must first save the contents of the pair of
locations that will be changed by it in case the interrupted program was in

the process of handling a UUO of the same type.

For a KI10 MUUO the

routine must save locations 424 and 425 of the user process table. In other
cases it is not the pair of consecutive locations that are relevant, as the

second contains the instruction to handle the UUO. Thus fora KA10 UUO
or a KI10 LUUO the routine must save location 40, unrelocated or in the

executive process table respectively, and the location used by the UUO
handler instruction to store the PC word.

‘

¢ The routine must dismiss the interrupt (with a

JEN) when returning to the

interrupted program. The flags and UUO locations should be restored.

§2.14

2.14

-111-

SYSTEM REFERENCE

TRAPPING

2-89

TRAPPING AND PROCESSOR CONDITIONS

In the performance of a program there are many events that cannot be foreseen and whose occurrence requires special action by the program. There are
instructions that test for various conditions, but in say a long string of computations it would be both cumbersome and’ time consuming to test
for
It is far better simply to allow an event such as

overflow at every step.

overflow to break right into the normal program sequence.

For situations of this nature, various internal conditions can interrupt the

program.

Both processors use condition 10 instructions to
appropriate flags and to inspect other conditions of interest to

control the

the program.

The KI10 also has a trapping mechanism that allows conditions due
directly
to the program, and which are often permitted to happen as a matter
of
course, to interrupt the program sequence without recourse to the
priority

interrupt system. Violation of instruction restrictions by a user or
the super-

visor is handled by trapping as an MUUO; violation of memory restrictions
is handled as a processor condition in the KA10 (as explained here) but
is

~ handled in the KI10 by trapping [§2.15].

Overflow Trapping (KIlO Only)
Overflow produced by an interrupt instruction cannot be detected.
In any
_other circumstances, an instruction in which an arithmetic overflow
condi-

tion occurs sets Overflow and Trap

pushdown overflow occurs sets Trap 2.

1, and an instruction in which a
If overflow traps have been enabled

by the Mecnitor, then at the completion of an instruction in which either
trap
flag is set, rather than going on to the next instruction as specified
by PC,

the processor instead executes an instruction taken from a particular
location in the process table for the program (user or executive). The
location
as a function of the trap flags set is as follows.

Trap Flags Set

Trap Type

Trap Number

Trap 1 only

Arithmetic overflow

421

Trap 2 only

Pushdown overflow

422

Trap 1 and 2

Not used by hardware

423

Overflow in a user instruction traps to a location in the user

process table, and any addresses used in the instruction in that
location are

interpreted in the user address space.

Thus a user program can handle its

own traps, eg by requesting the Monitor to place a PUSHIJ
to a user routine

in the trap location.
a user-caused trap.

flag.

Hence an overflow is

trapped even

if Overflow is

already set.

Location

A trap instruction is executed in the same address space as the
instruction

that caused it.

Note that it is the overflow
condition that sets Trap 1 —
not the state of the Overflow

An MUUO must be used if the Monitor is to handle

The trap instruction (the final instruction in an XCT and/or LUUO
string)
clears the trap flags, so the processor returns to the interrupted
program
unless the trap instruction changes PC. Thus the trap instruction
can be a
no-op (which ignores the trap), a skip, a jump, or anything else.
However,

A trap can be produced artificially simply by setting up
the trap flags with a
MUUO.

JRSTF or
In this way the pro-

gram can also use trap number

3, which at present cannot
from any hardware-

result

detected condition (it is reserved for future use by DEC).

SYSTEM REFERENCE

-112-

2-90

CENTRAL PROCESSOR

8§2.14

An arithmetic instruction that

should the trap instruction itself set a trap flag (not necessarily the same

overflows on every iteration

one), a second trap occurs.

produces an infinite loop if
used

trap

instruction

for arithmetic overflow.

pushdown

instruction

An interrupt can occur between an instruction that overflows and the trap

instruction, but the latter will be performed correctly upon the return provided

the interrupt

dismissed

automatically

or the

interrupt routine

pushdown overflow trap can

restores the flags properly. If a single instruction causes both overflow and a

overflow

page failure, the latter has preference; but the overflow trap will be taken

only

once.

(The

memory allocated to a pushdown

stack should have at

least

one

extra location

handle this case — two extras

if the program and the trap

care of after the offending instruction has been restarted and completed

successfully.

A trap instruction that causes a page failure does not clear the

trap flags; hence after the page failure is taken care of, the trap instruction
will correctly handle the trap when it is restarted.

both use the same pointer.)

K110 Processor Conditions
In the KI10, page failures and overflow are handled by trapping, but there
are a number of other internal conditions that can signal the program by
requesting an interrupt on a channel assigned to the processor. The program

can actually assign two channels — one for error conditions and one
specifically for the clock.

Control over the Power Failure and Parity Error

flags is exercised by a CONO that addresses the priority interrupt system
[§2.13].

Inspection of other conditions and control over all are handled by

condition IO instructions that address the processor; the CONI also reads
some console switches and maintenance functions.
a

data-out

instruction through which the

The processor also has

program can perform margin

checking of the system in both speed and voltage.
One of the features controlled by the CONO for the processor is the automatic restart after power failure. This restart applies only when the levels on
the power mains go below specification while the processor is running, and
the power switch is on when power is restored — the machine never begins
~operation by itself when the operator turns the power switch on or off.
Inadequate power, over temperature, etc are indicated by the Power Failure

flag.

The program must both enable the auto restart feature and respond to

the setting of Power Failure in order for the processor to restart itself. If the
program fails to clear Power Failure or enable the auto restart within 4 ms

after failure is detected, there is no restart. But if the auto restart is enabled
and Power Failure is clear, then when power levels are again adequate the
processor will restart itself by executing the instruction in location 70 in
kernel mode (provided the power switch is on).

The processor device code is 000, mnemonic APR.

CONO APR,

70020
0

Conditions Out, Arithmetic Processor

7l
121314

|
1718

B
35

Assign the interrupt channels specified by bits 30—35 of the effective condi-

tions £ and perform the functions specified by bits 18-29 as shown (a l in a
bit produces the indicated function, a 0 has no effect).

- SYSTEM REFERENCE

-113-

§2.14

PROCESSOR CONDITIONS

2-91
CLEAR
NONEXISTENT
MEMORY

INTERRUPT

| CLOCK

PAGE

ASSIGNMENT-ERROR | ASSIGNMENT-CLOCK

FAILURE

PRIORITY INTERRUPT | PRIORITY INTERRUPT
|

to,

[

A 1 in bit 19 produces the 10 reset signal, which clears the control logic
in all of the peripheral equipment (but affects neither the priority interrupt
system nor the processor conditions).

CON!I APR,

Conditions In, Arithmetic Processor

70024

121314

1718

Read the status of the processor (as well as various console switches and
maintenance functions) into location £ as shown.
MAINTENANCE
MODE

MEM

|CONSOLE

DISABLE

DISABLE|

LOCK

/
5

PARITY
ERROR
*

INTERRUPT
ENABLED

nve | parity
19

NONEXISTENT

cLock

ENABLED| FAILURE | Fo
o/ er
20

CLOCK
INTERRUPT
ENABLED
/
*

Timer | PowER REASUTTA%T

OUT | ERROR
18

In-ouT

FAILURE
21

MEMORY
/

/ PRIORITY INTERRUPT | PRIORITY INTERRUPT
29

ASSlGiNMENT-lERROR

ASSIGII\IMENT—-ICLOCK

Notes.

*These bits cause interrupts.

Interrupts are requested on the error channel (assigned by bits 30-32 of

the CONO) by the setting of Power Failure, In-out Page Failure, Nonexistent

Memory, and if enabled, Parity Error. The setting of Clock Flag, if enabled,
requests an interrupt on the clock channel (assigned by bits 33-35 of the

CONO).
o
Bits 12-17 reflect the states of the console sense switches, which are
specifically for operator communication with the program. Bits 1-5 reflect
the settings of various console operating switches; for information on these
switches refer to §2.19.

Bits 7—10 are maintenance functions for which the

reader should refer to Chapter 10 of the maintenance manual.

The system is operating on 50 Hz line power.

This is important to

the program, not only because some 10 devices run slower on 50 Hz,

The processor does not actually have a maintenance mode
—

the bit is simply the or

function of a number of console

switches,

any

one

which being on implies that
the

processor

being

op-

but because the program must compensate for the time difference

erated for maintenance pur-

when using the line frequency clock (bit 26).

poses.

SYSTEM REFERENCE

-114-

The timer provides a restart
similar to that following power

failure. Running the machine
under margins may result in
significant logical errors. If
the timer is enabled, failure
of the

§2.14

CENTRAL PROCESSOR

2-92

program to reset it

about every second allows it

Bit 21 is 1 and the program has not reset the timer (CONO APR,
bit 18) during the last 1.2 seconds (the period of the timer may vary
from 1.2 to 1.5 seconds). The setting of this flag clears the processor
and the peripheral equipment, and restarts the processor in kernel

mode at location 70.

to time out.

A word with even parity has been read from core memory. If bit 20
is 1, the setting of Parity Error requests an interrupt on the error
channel, at which time PC points to the instruction being performed
or to the one following it.

Ac power has failed. The program should save PC, the flags, mode
information and fast memory in core, and halt the processor.

The setting of this flag requests an interrupt on the error channel.
After 4 ms the processor is cleared. But at that time, if Auto

Restart Enabled is set and the program has cleared Power Failure

(CONO PI,400000), then when adequate power levels are restored,
the processor will go back into normal operation in kernel mode at
location 70 (provided the power switch is on).

This flag is set at the ac power line frequency and can thus be used
for low resolution timing (the clock has high long term accuracy). If
bit 25 is 1, the setting of the Clock flag requests an interrupt on the
clock channel.

A page failure has occurred in an interrupt instruction.

The setting

of this flag requests an interrupt on the error channel.

Note: A page failure in an interrupt instruction is regarded as a
fatal error, and it causes an interrupt instead of a page failure trap.
The kernel mode program is expected to set up the interrupt instructions so that a page failure simply cannot occur.
PC bears no relation to the
unanswered reference if the
attempted

access

originated

from a console key function.

This instruction is for mainFor further
tenance only.
information refer to Chapter
10 of the KI10 Maintenance

The processor attempted to access a memory that did not respond
within 100 us. The setting of this flag requests
an interrupt on the
error channel, at which time PC points either to the instruction
containing the unanswered reference or to the one following it.

DATAOQO APR,

Maintenance Data Out, Arithmetic Processor

121314

Manual.

70014
0

1718

Supply diagnostic information and perform diagnostic functions according
to the contents of location E as shown.

WRITE
EVEN

TURN OFF | TURN ON | TURN OFF ! TURN ON
'

L___E__“

VOLTAGE MARGINS

SPEED MARGINS

PARITY

___

MARGINS
ADDRES
13

'36/,,._1

MARGIN
N

:
ONS
FUNCTI
21

-115-

- 82.14

SYSTEM REFERENCE

PROCESSOR CONDITIONS

2-93

KA10 Processor Conditions
There are a number of internal conditions that can signal the program by

requesting an interrupt on a channel assigned to the processor. Flags for
power failure and parity error are handled by the condition 10 instructions

that address the priority interrupt system [§2.13]. The remaining flags are
handled by condition instructions that address the processor. Its device code
is 000, mnemonic APR.

CONQO APR,

Conditions Qut, Arithmetic Processor

70020

1l
.

121314

1718

Assign the interrupt channel specified by bits 33-35 of the effective conditions £ and perform the functions specified by bits 18—32 as shown (a 1 in a

bit produces the indicated function, a 0 has no effect).
CLEAR

CLEAR

PUSHDOWN
OVERFLOW

[',’é\‘,."c“gé
19

CLEAR
ADDRESS

BREAK

CLEAR

NONEXISTENT
MEMORY

FLas,

cfi?_R

CLEAR

MEMORY
PROTECTION

DISABLE‘ENABLE CLEAR DISAFB%;EAITENABLE
LOATING

SINTCE%&'J(PT

CLEAR

FLOATING
OVERFLOW

CLOCK

&fi%&?fi#

’

‘

OVERFLOW

DISABLE| ENABLE
OVERFLOW

I:JF%IEORRRTHYDT

lNTERlRUPT

ASIS|GNMEINT

Notes.

Enabling a particular flag to interrupt means that henceforth the setting
of the flag will request an interrupt on the channel assigned (by bits 33-35)
to the processor. Disabling prevents the flag from triggering a request.

A 1in bit 19 produces the IO reset signal, which clears the control logic in
all of the peripheral equipment (but affects neither the priority interrupt sys-

tem, nor the processor flags cleared by this instruction or CONO PI,).

CONI APR,

Conditions In, Arithmetic Processor

70024

[}

121314

1718

35
-

Read the status of the processor into the right half of location E as shown
(all interrupt requests are made on the channel assigned to the processor).
PUSHOOWN
OVERFLOW

MEMORY
PROTECTION

*
USER

FLAG

|ADDRESS

\%
\

NONEXISTENT
MEMORY

CLOCK
INTERRUPT

FLOATING
OVERFLOW

ENABLED

INTERRUPT

ENABLED

CLOCK

FLOATING
OVERFIOW

IN-OUT | BREAK

TRAP

*These bits request interrupts.

OVERFLOW
INTERRUPT
ENABLED

OVERFLOW

PRIORITY

INTERRUPT

OFFSET

ASSIGNMENT

SYSTEM REFERENCE

-116-

8§2.14 .

CENTRAL PROCESSOR

294
Notes.
19

Pushdown Overflow — in a PUSH or PUSHJ the count in AC left
reached zero; or in a POP or POPJ the count reached —1. The setting
of this flag requests an interrupt.

User In-out — even if the processor is in user mode, there are no

instruction restrictions (but memory restrictions still apply) [§2.16].

Address Break — while the console address break switch was on, the
processor requested access to the memory location specified by the
address switches and the memory reference was for the purpose
by the address condition switches as follows:
selected

PC bears no relation to the
break if the access was requested for a console key
function.

The instruction switch was on and access was for retrieval of an
instruction (including an instruction executed by an XCT or contained in an interrupt location or a trap for an unimplemented
operation) or an address word in an effective address calculation.

The data fetch switch was on and access was for retrieval of an
operand (other than in an XCT).

The write switch was on and access was for writing a word in
memory.

The setting of this flag requests an interrupt, at which time PC points
to the instruction that was being executed or to the one following it.
This flag can also be set by

an instruction executed from
the console while the USER
MODE light is on, in which

to
case PC bears no relation
the violation.

PC bears no relation to the
unanswered reference if the
attempted access originated
from a console key function.

Memory Protection — a user program attempted to access a memory

location outside of its area or to write in a write-protected part of its
area and the user instruction was terminated at that time. The setting
of this flag requests an interrupt, at which time PC points either to
the instruction that caused the violation or to the one following it.
Nonexistent Memory — the processor attempted to access a memory
that did not respond within 100 ugs. The setting of this flag requests
an interrupt, at which time PC points either to the instruction con-

taining the unanswered reference or to the one following it.
26

Clock — this flag is set at the ac power line frequency and can thus
be used for low resolution timing (the clock has high long term
accuracy). If bit 25 is set, the setting of the Clock flag requests an
interrupt.

Floating Overflow — this is one of the flags saved in a PC word, and
the conditions that set it are given at the beginning of §2.9. If bit 28

is set, the setting of Floating Overflow requests an interrupt, at which
time PC points to the instruction following that in which the overflow occurred.

Trap Offset — the processor is using locations 140-161 for unimplemented operation traps and interrupt locations.

Overflow — this is one of the flags saved in a PC word, and the conditions that set it are given at the beginning of §2.9. If bit 31 is set,
the setting of Overflow requests an interrupt, at which time PC
points to the instruction following that in which the overflow
occurred.

‘

§2.15
2.15

- 117-

SYSTEM REFERENCE

KI10 MODES

2-95

KI10 MODES

General information about the machine modes and paging procedures is

given in Chapter 1, in particular at the end of the introductory remarks and

at the end of §1.3.
Here we are concerned principally with the special
instructions the Monitor uses to operate the system, the special effects that

ordinary instructions have in executive mode, and certain hardware procedures, in particular paging and page failures, that are necessary for an
understanding of executive programming.

User Programming. As far as user programming is concerned, all of the
necessary information has already been presented. For convenience however
we list here the rules the user must observe. [Refer to the Monitor manual
for further information including use of the Monitor for input-output. )
¢ If possible, limit your memory needs to 32K, using addresses 0-37777
and 400000-437777, to gain the savings afforded by having the status of a

“small user”.

There are no restrictions of any kind on addresses 0—-17 as

these are in fast memory and are available to all users (even though page 0
may otherwise be inaccessible).

¢ If an area of memory is write-protected, eg for a reentrant program shared
by several users, do not attempt to store anythingin it. In partlcular do not
execute a

JSR or JSA into a write-protected page.

¢ Use the MUUO codes 040-077 only in the manner prescribed in the
Monitor manual. In general, unless they are prescribed for special circum-

stances, code 000 and the unassigned codes should not be used.

¢ Unless User In-out is set do not give any IO instruction with device code

less than 740, HALT (JRST 4,) or JEN (JRST 12, (specifically JRST 10,)).
The program can determine if User In-out is set by examining bit 6 of the PC

word stored by JSR, JSP or PUSHI.
¢ If your public program has

the use of concealed programs, do not
reference a location in a concealed page for any purpose except to fetch an
instruction from a valid entry point, ie a location containing a

The user can give a

JRST 1,.
JRSTF (JRST 2,) but a 0 in bit 5 of the PC word does

not clear User (a program cannot leave user mode this way); and a 1 in bit 6
does not set User In-out, so the user cannot void any of the instruction
restrictions himself. Note that a 0 in bit 6 will clear User In-out, so a user
can discard his own special privileges. Similarly a 1 in bit 7 sets Public, but a
0 does not clear it, so a public program cannot enter concealed mode this way.

The above rules are the result of KI10 hardware characteristics.
real

sense

many

of these

Butin a

rules are actually transparent to the user, in

particular the whole paging setup is invisible. Although the hardware allows

for user virtual address spaces that are scattered and/or very large (eg larger
than available physical core), the actual constraints will be dictated by the
particular Monitor and the system manager.

It may be desirable (for comoperation with KA1O systems) to enforce a two-segment virtual
address space that mimics the one imposed by the KA10 hardware. In any

patible

case the user must write a sensible program, which can be handled easily and
cheaply by the system; if he uses addresses a few to a page all over memory,

his program can be run but will require a much larger amount of core than
necessary or cause excessive page swapping.

SYSTEM REFERENCE

~118-

CENTRAL PROCESSOR

2-96

§2.15
Paging

Actually page O has only 496
locations using addresses 20—
777, as addresses 0—17 reference fast memory, which is
unrestricted and available to
all programs.

(In general a

user cannot reference the first
sixteen core locations in his .
virtual page 0.) Throughout
this" discussion it is assumed
that all references are to core
and are not made by an
instruction

executed

executive XCT [see below] .

All of memory both virtual and physical is divided into pages of 512 words
each. The virtual memory space addressable by a program is 512 pages; the
locations in virtual memory are specified by 18-bit addresses, where the left
nine bits specify the page number and the right nine the location within the
page. Physical memory can contain 8192 pages and requires 22-bit addresses,
where the left thirteen bits specify the page number. The hardware maps the
virtual address space into a part of the physical address space by transforming the 18-bit addresses into 22-bit addresses. In this mapping the right
nine bits of the virtual address are not altered; in other words a given
location in a virtual page is the same location in the corresponding physical
page. The transformation maps a virtual page into a physical page by substituting a 13-bit physical page number for the 9-bit virtual page number.
The mapping procedure is carried out automatically by the hardware, but
the page map that supplies the necessary substitutions is set up by the kernel
mode program. Each word in the map provides information for mapping
two consecutive pages with the substitution for the even numbered page in

the left half, the odd numbered page in the right half.

The paging hardware contains two 13-bit registers that the Monitor loads
to specify the physical page numbers of the user and executive process
tables. To retrieve a map word from a process table, the hardware uses the
appropriate base page number as the left thirteen bits of the physical address
and some function of the virtual page number as the right nine bits. Eg the

entire user space of 512 virtual pages at two mappings per word requires a

page map of just half a page, and this is the first half page in the user process

table. Thus locations 0-377 in the table hold the mappings for pages 0 and
1 to 776 and 777. To find the desired substitution from the 9-bit virtual
page number, the hardware uses the left eight bits to address the location
and the right bit to select the half word (O for left, 1 for right). If the
Monitor specifies a program as being a small user, that program is limited to

two 16K blocks with addresses 0-37777 and 400000-437777.

This is

pages 0—-37 and 400-437, and the mappings are in locations 0—17 and
200-217 in the page map.

The executive virtual address space is also 256K but the first 112K are not
paged — in other words any address under 340000 given in kernel mode
addresses one of the. first 112K locations in physical memory directly. The
other 144K is paged for supervisor or kernel mode anywhere into physical
memory. For this there are two maps. The map for the second half of the
virtual address space uses the same locations in the executive process table as
are used in the user process table for the user map (locations 200-377 for
pages 400-777).

The map for the remaining 16K in the first half of the
executive virtual address space is in the user process table, the mappings for

Thus

when switching from

one user to another, the Moni-

tor need change only the user
process table. This single substitution can make whatever
change is necessary in the
executive address space for a
particular user.

pages 340—-377 being in locations 400—417. Thus the Monitor can assign a
different set of thirty-two physical pages (the per-process area) for its own
use relative to each user.

The illustrations on the next two pages show the organization of the
virtual address spaces, the process tables and the mappings for both user and
The first illustration gives the correspondence between the
executive.
various parts of each address space and the corresponding parts of the page

SYSTEM REFERENCE

§2.15

KI10 MODES

2-97

USER
VIRTUAL
ADDRESS
SPACE

EXECUTIVE
VIRTUAL
ADDRESS
SPACE

16K -

40000

\ \\
\

\ A

\A\
\\ \

\
\

USER
\{

SMALL USER 0—37

EXECUTIVE

(KERNAL MODE ONLY)

46 /W6RD§/

Vi g//

112K

//
///

40-377

112

SMALL USER 400-437

|16

/
prad

16K

/
/

EXECUTIVE 340-377
TRAP & MUUO

-7

|16

Pie

400000

16K

_ __—— ®

//
X
/

20 WORDS.// 16
TRAP

440000

/
/

{
[

128K

/’

SHADED AREAS

8Y HARDWARE

ARE
NOT USED

{

/
77777

12K

/////////

INTERRUPT

/1208 WORV 80

/ /
400000

/
777777

VIRTUAL ADDRESS SPACE AND PAGE MAP LAYOUT

SYSTEM REFERENCE

-120-

CENTRAL PROCESSOR

2-98
USER PROCESS TABLE

| UseR PAGE 41

e —

|
| USER PAGE 37

|AVAILABLE TO SOFTWARE
40

EXECUTIVE LUUO STORED HERE

141

LUUO HANDLER INSTRUCTION

1STANDARD PRIORITY INTERRUPT INSTRUCTIONS

I
177 | USER PAGE 376

USER PAGE 377

200 | USER PAGE 400

USER PAGE 401

[

EXECUTIVE PAGE 777

|
I

—
—
——

—

I
| USER PAGE 777
I EXECUTIVE PAGE 341

——

| AVAILABLE TO SOFTWARE IF SMALL USER

EXECUTIVE PAGE 776

——

377

——

—

|
377 | USER PAGE 776
400! EXECUTIVE PAGE 340

lEXECUTIVE PAGE 401

I
I

EXECUTIVE PAGE 400

USER PAGE 441

200

177

USER PAGE 437

220 | USER PAGE 440

|AVAILABLE TO SOFTWARE

—

217 | USER PAGE 436

—

|
]

a—

AVAILABLE TO SOFTWARE IF SMALL USER

——

—

——

—

20| USER PAGE 40

I'USER PAGE 1

—

|
17| USER PAGE 36

EXECUTIVE PROCESS TABLE

——

olUSER PAGE 0

§2.15

400

VAVAILABLE TO SOFTWARE

417

EXECUTIVE PAGE 376

420

USER PAGE FAILURE TRAP INSTRUCTION

420

421

USER ARITHMETIC OVERFLOW TRAP INSTRUCTION

422

USER PUSHDOWN OVERFLOW TRAP INSTRUCTION

422

EXECUTIVE PUSHDOWN OVERFLOW TRAP INSTRUCTION

423

USER TRAP 3 TRAP INSTRUCTION

423

EXECUTIVE TRAP 3 TRAP INSTRUCTION

424

MUUO STORED HERE

424

425

PC WORD OF MUUO STORED HERE

I
|
I
I
I
I

426 EXECUTIVE PAGE FAILURE WORD
427

USER PAGE FAILURE WORD

430

KERNEL NO TRAP NEW MUUO PC WORD

431

KERNEL TRAP NEW MUUO PC WORD

432

SUPERVISOR NO TRAP NEW MUUO PC WORD

433

SUPERVISOR TRAP NEW MUUO PC WORD

434

CONCEALED NO TRAP NEW MUUO PC WORD

435

CONCEALED TRAP NEW MUUO PC WORD

436

PUBLIC NO TRAP NEW MUUO PC WORD

437

PUBLIC TRAP NEW MUUO PC WORD

EXECUTIVE PAGE FAILURE TRAP INSTRUCTION
EXECUTIVE ARITHMETIC OVERFLOW TRAP INSTRUCTION

—

I EXECUTIVE PAGE 377

IA VAILABLE TO SOFTWARE
I
|

I
I

440

AVAILABLE TO SOFTWARE

777

PROCESS TABLE CONFIGURATION

SYSTEM REFERENCE

-121-

§2.15

KI10 MODES

map for it.

2-99

The second illustration lists the detailed configuration of the

process tables.

Any table locations not used by the hardware can be used by

the Monitor for software functions.

Note that the numbers in the half

locations in the page map are the virtual pages for which the half words give

the physical substitutions. Hence location 217 in the user page map contains
the physical page numbers for virtual pages 436 and 437.

Although the virtual space is always 256K by virtue of the addressing

There is no requirement that

capability of the instruction format, the Monitor usually limits the actual

the accessible space be con-

address space for a given program by defining only certain pages as accessible.

tinuous — it can be scattered

The Monitor also specifies whether each page is public or not and writeable
or not.

Each word in the page map has this format to supply the necessary

information for two virtual pages.

to be in two continuous virtual
respectively at locations 0 and

DATA FOR ODD VIRTUAL PAGE

PHY SICAL PAGE

ADDRESS BITS 14-26

23435

The convention how-.

ever is for the accessible space
areas, low and high, beginning

DATA FOR EVEN VIRTUAL PAGE

AIPIW|SIX

pages.

400000.

APIW|S| X

ADDRESS BITS 14-26

1718192021 2223

The

low

part

generally unique to a given

PHYSICAL PAGE

user and can be used in any
35

Bits 5—-17 and 23-35 contain the physical page numbers for the even and

way he wishes.

The (perhaps
null) high part is a reentrant
area, which is shared by sev-

odd numbered virtual pages corresponding to the map location that holds

eral

the word.

write-protected.

The properties represented by ls in the remaining bits are as

follows.

users

and

therefore
The

small

user configuration is consistent with this arrangement.

Bit

Meaning of a 1 in the Bit

Access allowed

Public

Writeable (not write-protected)

Software (not interpreted by the hardware)

Reserved for future use by DEC (do not use)

Associative Memory. If the complete mapping procedure described above
were actually carried out in every instance, the processor would require two

memory references for every reference by the program.

To avoid this the

paging hardware contains a 32-word associative memory, in which it keeps
the more recently used mappings for both the executive and the current user.

Each word is divided into two parts with one part containing a virtual page

number specified by the program and the other containing the corresponding
physical

page

number as

determined

from

the

page

map.

Hence

the

associative memory is a page table made up of a list of virtual pages and a list

of physical pages, each with thirty-two corresponding locations.

In the

virtual list, each entry contains a 9-bit virtual page number, a single bit that
indicates whether the specified page is in the user or executive address space,

and a bit that indicates whether the entry is valid or not (it is not suitable to
clear a location as 0 is a perfectly valid page number).

Each corresponding

entry in the physical list contains a 13-bit physical page number and the

P, W and S bits from the map half word for that page.

The A bit is not

needed in the table as the mapping is not entered into the table at all if the
page is not accessible.

At each reference the hardware compares the page number supplied by

The program can inspect the

contents of the page table by
using the MAP instruction
and IO instructions that ad-

dress the paging hardware [see
below].

~122-

SYSTEM REFERENCE

§2.15

CENTRAL PROCESSOR

2-100

the program with those in the virtual part of the page table. If there is a
match for the appropriate address space, the corresponding entry in the
physical list is used as the left thirteen bits in the physical address (provided
of course that the reference is allowable according to the P and W bits). If
there is no match, the hardware makes a memory reference to get the neces:
sary information from the page map and enters it into the page table at the
location specified by a reload counter. This counter is incremented whenever it is used to reload the table, and also whenever the location to which it

points is used for a mapping. Hence the counter tends to stay away from
locations containing the page numbers most frequently referenced.
Page Failure

A page failure that occurs during an interrupt instruction terminates the
instruction and sets the In-out Page Failure flag, requesting an interrupt on
the error channel assigned to the processor. In all other circumstances, if the
paging hardware cannot make the desired memory reference, it terminates
the instruction immediately without disturbing memory, the accumulators
When a page failure trap in-

struction is performed, PC
points to the instruction that
failed (or to an XCT that
executed it), unless the failure
occurred in an overflow trap
instruction, in which case PC points to the instruction that
overflowed. After taking care
of the failure, the processor
can always return to the interrupted instruction. Either the
instruction did not change
anything, or the failure was in
the second part of a two-part
instruction, where First Part
Done being set prevents the

or PC, places a page fail word in the user process table, and causes a page
failure trap. If the attempted reference is in user virtual address space, the

page fail word is placed in location 427 of the user process table, and the

processor executes the trap instruction in location 420 of the same table.,
If the attempted reference is in executive virtual address space, the page fail

word is placed in location 426 of the user process table, and the processor
executes the trap instruction in location 420 of the executive process table.
The trap instruction is executed in the same address space in which the
failure occurred. The page fail word supplies this information.
U

8 9

VIRTUAL PAGE

first part.

Since a user page failure trap

instruction is executed in user
address space, the Monitor
should be careful not to have
the trap instruction do indirect addressing that might
cause another page failure.
Whether or not a comparison

can be made is a function of
the settings of the paging
switches [§2.19] and the state
of the User Address Compare
Enable flag [see below].

TYPE

17 -

IF BIT 31 IS 0, BITS 31-35
HAVE THIS FORMAT

processor from repeating any

unwanted operatxons in the

FAILURE

3132333435

Whether the violation occurred in uSer or executive virtual address space is

indicated by a 1 or a 0 in bit 8. If bit 31 is 1, the number in bits 31— 35
(= 20) indicates the type of “hard” failure as follows

Address failure — this is a simulated page failure caused by the satisIt
faction of an address condition selected from the console.
the
and
on
indicates that while the console address break switch was

Address Failure Inhibit flag was clear (bit 8 of the PC word), the
processor requested access to the memory location that was specified

by the paging and address switches and for which a comparison was
enabled, and the memory reference was for the purpose selected by
the address condition switches as follows:

The instruction fetch switch was on and access was for retrieval of
an instruction (including an instruction executed by an XCT or
contained in an interrupt location or a trap) or an address word in
an effective address calculation.

~123-

§2.15

SYSTEM REFERENCE

KI10 MODES

2-101

The data fetch switch was on and access was for retrieval of an
operand (other than in an XCT).

The write switch was on and access was for writing a word in
memory.

The Address Failure Inhibit flag, which can be set only by a
JRSTF or MUUO, prevents an address failure during the next instruction — the completion of the next instruction automatically clears it.

If an interrupt or trap intervenes, the flag has no effect and it is saved
and cleared if the PC word is saved.

If it is not saved, it affects the

instruction following the interrupt or trap.

instruction

following a return in

Otherwise it affects the

which it is restored

with the

PC word.
22

Page refill failure — this is a hardware malfunction. The paging hardware did not find the virtual page listed in the page table, so it loaded

Tests for hard page failures

paging information from the page map into the table but still could

are actually made in the order

not find it.

Small user violation — a small user has attempted to reference a
location outside of the limited small user address space.

Proprietary violation — an instruction in a public page has attempted
to reference a concealed page or transfer control into a concealed
page at an invalid entry point (one not containing a

JRST

given here.

1,).

If the violation is not one of these, then bits 31-35 have the format shown
above where A, W and S are simply the corresponding bits taken from the

map half word for the page, and T indicates the type of reference in which
the failure occuired — O for a read reference, 1 for a write or read-modifywrite reference.
,

The page fail trap instruction is set by the Monitor to transfer control to
kernel mode. After rectifying the situation, the Monitor returns to the inter-

The type of reference implies
nothing about the cause of
failure — it indicates only the
reason

the

failed

reference

was being made.

rupted instruction, which starts over again from the beginning.
Even a
two-part instruction that has been stopped by a failure in the second part is
redone properly, provided the Monitor restores the First Part Done flag.
Note that a failure does not necessarily imply that anything is “wrong”.

The virtual address space of even a small user is 32K words, which may well
be more than is needed in a given run. Hence the Monitor may have only ten
or twenty pages of the user program in core at any given time, and these

would be the virtual pages indicated as accessible. When the user attempts to

gain access to a page that is not there (a virtual page indicated in the page

map as inaccessible), the Monitor would respond to the page failure by
bringing in the needed page from the drum or disk, either adding to the user
space or swapping out a page the user no longer needs.

The

same

situation exists for writeability.

When bringing in a user

program, the Monitor would ordinarily indicate as writeable only the buffer
area and other pages that will definitely be altered.

Then in response to a

write failure, the Monitor makes the page writeable and indicates to itself
(perhaps by means of the software bit in the page map) that that page has in

fact been altered.

When the user is done, the Monitor need write only the

altered pages back onto the drum.

In any page failure, the mapping

entry for the page is
removed from the page table

on the assumption that the
Monitor will change it. When
the

instruction is restarted,
the hardware must go to the

page map to get a new entry

for the page table.

-124-

SYSTEM REFERENCE

§2.15

CENTRAL PROCESSOR

2-102

Monitor Programming

The kernel mode program is responsible for the overall control of the system.
It is the only program that has access to any of physical core unpaged and
that has no instruction restrictions. The kernel program handles all in-out
for the system and must set up the page maps, trap locations, interrupt locations and the like. The supervisor program labors under the same instruction
restrictions as the user but has no way of bypassing them — they always
apply. Supervisor mode is limited to the 144K paged part of the executive

address space, although within that space it can read but not alter concealed

pages (the kernel program supplies data tables of all kinds to the supervisor
program, and the latter cannot affect them). The supervisor can give a
JRSTF that clears Public provided it is also setting User; in other words the
supervisor can return control to a concealed program but cannot enter kernel
mode by manipulating the flags. The PC words supplied by MUUOs can

manipulate the flags in any ‘way, switching arbitrarily from one mode to

another, but these are in the process table and assumed to be under control
‘

solely of kernel mode.

For accumulator, index register and fast memory references, the Monitor
automatically uses fast memory block 0. For each user, the kernel mode
program must assign a block. The usual procedure is to assign blocks 2 and 3
to individual user programs on a semipermanent basis for special applications .
and to assign block 1 to all other users. In this way the Monitor need not
store blocks 2 and 3 when the special users are not running, and it need not
store block 1 when it takes over control from an ordinary user temporarily.
When switching from one user to another, the Monitor usually stores the
first user’s accumulators in his shadow area — this is locations 0—17 in user
virtual page 0, an area not generally accessible to the user at all — and loads
the new user’s accumulators from his shadow area, where they were stored

If the Monitor shared block 0

with any users, it would have
to store the user accumulators
even when taking control only
temporarily.

after the last time the new user ran.

Even while User is set, the interrupt instructions are not part of the user
program and are thus subject only to executive restrictions. As interrupt instructions, JSR, JSP and PUSHJ automatically take the processor out of user
mode to jump to an executive service routine. An MUUO can also be used.
The paging hardware has one non-IO instruction and two condition 10
instructions primarily for diagnostic purposes. Otherwise control over the
system is exercised by data IO instructions. The device code for the paging

The page failure and overflow
trap instructions are executed
in the user address space if
caused by the user.

hardware is 010, mnemonic PAG.

Data Qut, Paging

DATAO PAG,

70114

]

121314

1718

Set up the paging hardware according to the contents of location £ as shown.
LOAD
00

FAST
USER
MEMOR

[

USER

|ADDRESS
SMALL
MALL | ADORESS

ENABLE

{

USER

BASE

ADDRESS

]

14 | 15

]

~125-

§2.15

KI10 MODES

LOAD
FOaD

TRAP
ENnBLE

2-103

EXECUTIVE

SYSTEM REFERENCE

[

BASE ADDRESS
|

]

{

Bits 0 and 18 are change bits. If bit 0 is 0, ignore the rest of the left half
word. But if bit 0 is 1, load bits 517 into the user base register to select the
user process table, select the fast memory block specified by bits 1 and
2 for

the user, limit the address space to that of a small user if bit 3 is I, and
enable address comparison if bit 4 is 1.

The Address Compare Enable

Similarly if bit 18 is 0, ignore the rest of the right half word. Otherwise
load bits 23-35 into the executive base register to select the executive
P

bit functions in conjunction

with

process table, and enable overflow traps if bit 22 is 1.

§2.19

If either bit O or 18 is 1, invalidate all data in the associative memory. In
other words set the Word Empty bit in each location to indicate that the rest
of the word is meaningless and should not be used.

DATAI PAG,

the

switches,

console paging

explained

Data In, Paging

[_7oi0s

[l x ]

121314

1718

]
35

Read the status of the paging hardware into location E. The information
read is the same as that supplied by a DATAO (bits 0 and 18 are 0).

CONO PAG,

Conditions Out, Paging

70120

121314

1718

Load the executive stack pointer from bits 18—-22 and the page table reload
counter from bits 31-35 of the effective conditions E as shown.

EXECUTIVE AC
POINTER

PAGE TABLE

STACK

RELOAD COUNTER

The executive stack pointer specifies a block of sixteen locations in the user
process table by supplying the left five bits for a 9-bit address that references

a location in the table; this function is used only for accessing stacked

fast
memory blocks in an instruction executed by an executive XCT [see below].
Loading the reload counter causes it to point to the specified location in the

page table.

]

322

3¢

~126-

SYSTEM REFERENCE

Conditions In, Paging

CON! PAG,

This instruction also reads the
processor serial number into
bits 0—9 of location E.

M
COMPLEMENT
OF F
|

Read the page table reload counter and the contents of the location in the
virtual page table specified by it into the right half of location E as shown.

EXECUTVE

VIRTUAL
PA NUMBE R
VIRTUAL PAGE
|

17 18

121314

70124
0

§2.15

| CENTRAL PROCESSOR

2-104

]

| 24
23

]

PAGE TABLE

WORD
wor

ADDRESS

26 | 21

RELOAD COUNTER

3213

Note that bits 18-26 contain the complement of the virtual page number in
the selected location. A 1 in bit 27 indicates the page is in the executive
address space; a 1 in bit 30 means the information in bits 1827 is invalid.

It is possible for the reload
counter to change between
the CONI and the CONO, so

the CONI might read a different location than was selected

by the CONO.

Map an Address

MAP

[

257

[i]

121314

]

‘

1718

Map the virtual effective address E and place the resulting map data in AC

right in the same format as it is in the page map, ie bits P, W and S in
bits 19-21 and the physical page number in bits 23-35. Clear AC left.
NO

FAILURE

PAGE

MATCH

These three instructions can

be used to inspect the contents
of the

associative

memory.

The CONO selects a location,
the CONI reads the contents

of the virtual-page part of
that location, and an MAP
that addresses the specified
virtual page reads the contents of the physical-page part
of that location.

23 | 24

26 | 27

PHYSICAL PAGE
ADDRESS BITS 14-26

]

29 | 30

]

32 | 33

]

This instruction cannot produce a page failure, but if a page failure would
have resulted had an ordinary instruction in the same mode attempted to
write in location E, place a 1 in AC bit 18. If no match can be made by the
paging hardware, place a 1 in bit 22. This results in four possible situations
as a function of the states of bits 18 and 22.

Bit18

Bit 22

Meaning

AC right contains valid map data.

There is no page failure but also no match, so the

instruction must have made an unmapped reference —
perhaps to fast memory or to the unpaged area in
kernel mode.

There is a page failure but the map data is correct as
a match exists.

There is a page failure, and since there is no match,

the failure must have resulted from the instruction
referencing an inaccessible page or from some prior

~127-

§2.15

SYSTEM REFERENCE

KI10 MODES

2-105

failure (such as a page refill malfunction).

Hence AC

right contains invalid information.

Executive XCT
Ordinarily an instruction in a user program is performed entirely in user
address space and an instruction in the executive program is performed

entirely in executive address space.

In order to facilitate communication

between Monitor and users, the XCT instruction allows the executive to
execute instructions whose memory operand references can cross over the

boundary between user and executive address spaces.

It is very important to note that the only difference between an instruction executed by an executive XCT and an instruction performed in normal
circumstances is in the way the memory operand references are made. There

is no difference in the XCT itself. Everything inthe XCT is done in executive
address space, and the instruction fetched by the XCT is fetched in executive
space.

Moreover, in the executed instruction all effective address calculation

and accumulator references are in executive space.

If the instruction makes

no memory operand references, as in a jump, shift or immediate mode instruction, its execution differs in no way from the normal case.

The only

difference is in memory operand references.
Control over the special effects of the executed instructions is determined
by the User In-out flag (whose implied meaning is confined to user mode)

and bits 11 and 12 of the A portion of the XCT instruction word (in user
mode A is ignored).

If the A bits are both 0, the XCT acts as described in

§2.9, and the executed instruction differs in no way from the normal case.

-But if these bits are not both 0, then some memory operand references are
made to user virtual address space, where the type of reference is determined

by the A bits and the type of memory is selected by User In-out. With this

flag set, the A bits affect both core memory and fast memory references,
whereas with User In-out clear, the A bits affect only fast memory references.
For the memory operand references selected by User In-out, the effect of 1s
in bits 11 and 12 is as follows: a 1 in bit 12 causes the executed instruction
to perform all selected read and read-modify-write memory operand references to be performed in user virtual address space; a 1 in bit 11 causes all
selected memory operand write references to be performed in user space;
and ls in both bits cause all types of selected memory operand references in

the executed instruction to be performed in user space.

The meaning of user space is obvious in terms of core memory references,
but not so for fast memory.

When User In-out is set, the user space for fast

memory

references

selected for the user.

depends

which

fast

memory

block

currently

If block 0 is selected, fast memory operand references

of the types specified by bits 11 and 12 are made to the user shadow area. If
some other block is selected, the specified fast memory references are made
to the selected block.

If User

In-out

address space.
and

clear,

all

core

memory

references are in executive

Fast memory references of the types specified by bits 11
12 are made to the user process table, in particular to that set of

Read the next four paragraphs
very carefully (reading them
two or three times is highly
recommended).

SYSTEM REFERENCE

~128-

2-106

CENTRAL PROCESSOR

§2.15

sixteen locations specified by the executive stack pointer.

The pointer is

given by a CONO PAG,.
User Space Fast Memory References

User Fast Memory Block Selected
~User In-out

Zero

Nonzero

Shadow area

Selected block

AC stack

There is another flag that plays a role in the execution of instructions by
an executive XCT.

This is Disable Bypass, bit 0 of the PC word.

When

‘Disable Bypass is clear, a bypass in the logic allows an executed instruction

to access the concealed user area from supervisor mode. With the flag set, an

attempt to do this results in a page failure.

Generally the new MUUO PC

word would set this flag when the Monitor is being called from public mode,
so the concealed area can be accessed only when such access is requested by
the concealed program.

Individual Instruction Effects. The effects of execution by an executive

XCT on different types of instructions is as follows.
¢ Instructions without memory operand references are not affected.

This

includes shifts, jumps, immediate mode instructions, CONSO, CONO, and even an XCT.

In fact not only is an executive XCT not affected when

executed by an executive XCT, but the first destroys any effect the second
would otherwise have on a third instruction (in other words, a pair of

executive XCTs is equivalent to a pair of ordinary XCTs). ¢ Instructions that refer to one memory location for reading only or reading
and writing are controlled by the read bit (MOVE, MOVES, ADDM, AOS).
The read bit controls writing when the write is done to the same location as

the read, whether the memory references are done as a single cycle including
both read and write or as separate read and write cycles.
¢ Instructions that refer to one memory location for writing only are controlled by the write bit (MOVEM, MAP, HRLZM).
¢ Instructions that refer to two different memory locations are controlled
by the read bit in the read part of the instruction and by the write bit in the
write part (BLT, PUSH).

‘

¢ BLKI and BLKO are controlled by the write bit and the read bit respectively.

The pointer reference is done in the same address space as the

data transfer.

¢ In byte instructions all pointer calculations are done in executive address
space.

The read and write bits affect only the second part, ie the load

or deposit.
Philosophy. The

purpose

the

executive

XCT is to

facilitate

the

handling of user requirements by the Monitor, but the selection made by
User In-out of the references affected by the read and write bits is to allow
the Monitor to make recursive calls to itself, ie to perform MUUOs in the

process of carrying out an MUUOQ given by the user. Specifically the state of
User In-out differentiates between the Monitor response directly to the user
MUUO and its response to its own MUUOs.

SYSTEM REFERENCE

-129-

2-107

KA10 MODES

§2.16

The new PC word of an MUUO from the user would set User In-out so
that core memory references can be made across the user-executive
boundary, and fast memory references can be made to the user AC block.

The point in choosing between the shadow area and the selected block if not
block O is to reference the information that was held in the user AC block
before the Monitor took over. If the user shared block O with other users
and the Monitor, the Monitor will have saved his ACs in the shadow area of
his address space. The other AC blocks are not disturbed when the Monitor
takes over temporarily, so the Monitor need not save them and they will still
hold the user information.

If in the course of carrying out a user MUUO, the Monitor should itself
give an MUUO, the new PC word would clear -User In-out. Thus at this level
all core memory references are in the executive address space and fast
memory references are to an AC block in the user process table as specified
by the executive stack pointer. MUUO calls by the Monitor to itself can be
nested to a number of levels, but in all cases User In-out is left clear. The
particular AC block used at any level is specified by the stack pointer. Hence
the AC stack in the user process table is effectively a pushdown list kept by
the stack pointer; at each level the program must change the pointer to
specify the appropriate block. Each user process table would contain the
blocks needed for carrying out MUUOs for that user.

ExampLE. Suppose that the Monitor has been called by an MUUO from
the user (hence User In-out is set) and wishes to save the user’s ACs in the
- shadow area. Assume that every user runs with AC block 1, 2 or 3, and that

the Monitor always sets up executive virtual page 342 to point to the same
physical page as user page 0. Using accumulator T in block 0, the Monitor
saves the user ACs by giving these two instructions,

MOVE!
XCT

:Initialize pointer: from O to 342000

T,342000
1,[BLT

T,342000]

and restores them with these two.

MOVSI
XCT

T,342000
2,[BLT

2.16

;From 342000 to O

T,17]

KA10 MODES

The KA10 has only user and executive modes and uses protection and
relocation hardware.

Every user is assigned a core area and the rest of core is protected from
him — he cannot gain access to the protected area for either storage or
retrieval of information. The assigned area is divided into two parts. The
low part is unique to a given user and can be used for any purpose. The
high part may be for a single user, or it may be shared by several users. The
Monitor can write-protect the high part so that the user cannot alter its
contents, ie he cannot write anything in it. The Monitor would do this when

the high part is to be a pure procedure to be used reentrantly by several

This makes a different set of
sixteen words available at each
level using the same addresses.

SYSTEM REFERENCE

-130-

2-108

CENTRAL PROCESSOR

Note that the relocated low

T ———

part is actually in two sections

dresses 0-17

are

ad-

not relo-

the

accumulators.

P, + 1777

cated, all users having access
to

Monitor uses the first sixteen

Ny
\/

ILLEGAL .

NA
N7
\/
A

/ /A\

not running.

400000

HIGH | ,

P, + 1777

assigned area comprises only
the low part.

7N
//’

R, + P, + 1777

/NN

mulators when his program is

Ry, + 400000

HIiGH

locations in the low user
block to store the user’s accu-

The

Some systems have only the
low pair of protection and .
relocation registers. In this
case the user program is
always nonreentrant and the

I ————

Low

with the larger beginning at
R;+20. This is because

§2.16

ILLEGAL

F—— Rig, +20
Low

)

R, + P, + 1777

Ry, MUST BE NEGATIVE

MEMORY LARGER THAN

'
|

NON.

~r!

| EXISTENT
|

UNLESS SYSTEM HAS A
128K

| MEMORY !
!
|

777777

‘

USER ADDRESSES
BEFORE RELOCATION

users.

t
]

TYPICAL PHYSICAL ADDRESS
CONFIGURATION AFTER RELOCATION

One high pure segment may be used with any number of low impure

segments.

The user can request that the Monitor write-protect the high part

of a single program, eg in order to debug a reentrant program. All users write
programs beginning at address O for the low part, and beginning usually at

400000 for the high part.
object

The programmed addresses are retained in the

program but are relocated by the hardware to the physical area

assigned to the user as each access is made while the program is running.

The size and position of the user area are defined by specifying protection
and relocation addresses for the low and high blocks. The protection address
determines the maximum address the user can give; any address larger than
the maximum is illegal.

The relocation address is the address, as seen by the

Monitor and the hardware, of the first location in the block.
defines

these

addresses by loading four 8-bit registers,

The Monitor

each

of which
corresponds to the left eight bits (18-25) of an address whose right ten bits

are all 0.
To determine whether an address is legal its left eight bits are compared
with the appropriate

protection register, so the maximum user address
consists of the register contents in its left eight bits, 1777 in its right ten bits

(ie it is equal to the protection address plus 1777).

Since the set of all
addresses begins at zero, a block is always an integral multiple of 1024,

(20004) locations. Relocation is accomplished simply by adding the contents
of the appropriate relocation register to the user address, so the first address
in a block is a multiple of 2000.

The relative user and relocated address

SYSTEM REFERENCE

-131-

2-109

KA10 MODES

§2.16

configurations are therefore as illustrated here, where P;, R;, P, and R, are
respectively the protection and relocation addresses for the low and high
parts as derived from the 8-bit registers loaded by the Monitor. If the low
part is larger than 128K locations, ie more than half the maximum memory
capacity (P, > 400000), the high part starts at the first location after the low

part (at location P; +2000). The high part is limited to '128K. If the Monitor
defines two parts but does not write-protect the high part, the user has a.
two-part nonreentrant program.

If the user attempts to access a location outside of his assigned area, or
if the high part is write-protected and he attempts to alter its contents, the
current instruction terminates immediately, the Memory Protection flag is
set (status bit 22 read by CONI APR,), and an interrupt is requested on the
channel assigned to the processor [ §2.14].

User Programming. The user must observe the following rules when programming on a time shared basis. [Refer to the Monitor manual for further
information including use of the Monitor for input-output.]
& Use addresses only within the assigned blocks for all purposes — retrieval

The user can actually write
any size program: the Monitor

of instructions, retrieval of addresses, storage or retrieval of operands. The
low part contains locations with addresses from O to the maximum; the high
part contains from the greater of 400000 or P, +2000 to the maximum.

will assign enough core for his
needs. Basically the user must

write a sensible program; if he
uses absolute addresses scattered all over memory his

_FEither part can address the other.

¢ If the high part is write-protected, do not attempt to store anything in it.

program cannot be run on a

In particular do not execute a JSR or JSA into the high part.

¢ Use instruction codes 000 and 040-127 onlyin the manner prescnbedin

time shared basis with others.

¢ Unless User In-out is set do not give any IO instruction, HALT (JRST 4,)
or JEN (JRST 12, (specifically JRST 10,)). The program can determine if
User In-out is set by examining bit 6 of the PC word stored by JSR, JSP or

These instructions are illegal

the Monitor manual.

PUSHJ.

The user can give a JRSTF (JRST 2,) but a 0 in bit 5 of the PC word does
not clear User (a program cannot leave user mode this way); and a 1 in bit 6
does not set User In-out, so the user cannot void any of the restrictions
himself. Note that a 0 in bit 6 will clear User In-out, so a user can discard
his own special privileges.

LUUOs (001-037) function normally and are relocated to addresses 40

and 41 in the low block [§2.10].

Monitor Programming. The Monitor must assign the core area for each
user program, set up trap and interrupt locations, specify whether the user
can give 10 instructions, transfer control to the user program, and respond
appropriately when an interrupt occurs or an instruction is executed in
unrelocated 41 or 61. Core assignment is made by this instruction.

DATAO APR,

70014
0

Data Out, Arithmetic Processor

1l
121314

|
1718

|
35

Load the protection and relocation registers from the contents of location

unless User In-out is set.

SYSTEM REFERENCE

-132-

2-110

CENTRAL PROCESSOR

For a two part nonreentrant

§2.17

E as shown, where P;,, P,, R, and R, are the protection and relocation

program, set P = 0. For a one-

part

nonreentrant

program,

make P, < P,. If the hardware

has only one set of protection
and relocation registers, the
user area is defined by P; and
R;, the rest of the word is

ignored.

Plls—zs
1

}

)

Phls-zs
i

789

Rlls-zs
i

161718

Rhw—zs

252627

{

34 35

addresses defined above. If write-protect bit P (bit 17) is 1, do not allow the
user to write in the high part of his area.

Giving a

JRSTF with a 1 in bit 6 of the PC word allows the user to handle

his own input-output. The Monitor can also transfer control to the user with
this instruction by programming a 1 in bit 5 of the PC word, or it may jump
to the user program with a

JRST

1, which automatically sets User. The set

state of this flag implements the user restrictions.
While User is set, certain instructions are not part of the user program and
are therefore completely unrestricted, namely those executed in the interrupt

locations (which are not relocated) and in unrelocated trap locations 41 and
61.

Illegal instructions and UUO codes 000 and 040-077 are trapped in

The trap locations are 140-

unrelocated 40; codes 100-127 are trapped in unrelocated 60.

141 and 160-161 in a second

BLKO can be used in the even interrupt locations, and if there is no over-

KA10 processor.

flow, the processor returns to the interrupted user program.

BLKI and
JSR should

ordinarily be used in the remaining even interrupt locations, in odd interrupt

locations following block IO instructions, and in 41 and 61. The JSR clears
User and should jump to the Monitor.

JSP, PUSHIJ, JSA and JRST are

acceptable in that they clear User, but the first two require an accumulator

(all accumulators should be available to the user) and the latter two do not

save the flags.

After taking appropriate action, the Monitor can return to the user program
with a

JRSTF or JEN that restores the flags including User and User In-out.

2.17

REAL TIME CLOCK DK10

The clock referred to through-

This processor option can be used to signal the end of a specified real time

out this section is the DK10

interval or to measure the real time taken by an event.

real

time clock and should

not

confused

with the

line frequency clock whose
flag is one of the processor

conditions [§2.14].

With appropriate

software the DK10 can easily be used to keep the time of day.

The basic

element in the clock is an 18-bit binary counter that is incremented repeatedly by a clock source; a 100 kHz + .01% crystal-controlled source is available
internally, or a source of any frequency up to 400 kHz can be provided externally. Operation is synchronized so that the program can read the counter
at any time without missing a count. Associated with the counter is an 18-bit

interval register, which can be loaded by the program. Each time the count
reaches the number held in the register, the clock requests an interrupt while

the counter clears and begins a new count.

With the internal clock source,

whose period is 10 us, the total count is about 2.6 seconds.
The program turns the clock on and off by enabling and disabling the
counter.

The clock has two modes of operation: with the User Time flag

SYSTEM REFERENCE

-133-

§2.17

2-111

REAL TIME CLOCK DK10

clear, the counter operates continuously; with User Time set, the counter
stops while the processor is handling interrupts. Hence in the latter mode
the clock discounts interrupt time and can be used to time user programs.
In a system that contains two clocks, one can be used by the Monitor to
time user programs wkhile the other is used to keep the time of day.
Instructions. The clock device code is 070, mnemonic CLK.

A second

clock would have device code 074.

Conditions Out, Clock

CONO CLK,

[ x

70720

|
0

121314

]

]
1718

Assign the interrupt channel specified by bits 3335 of the effective conditions £ and perform the functions specified by bits 23-32 asshown (a 1 in
a bit produces the indicated function, a 0 has no effect).
CLEAR
COUNT
OVERFLOW

SET
COUNT
OVERFLOW

SET -

“COUNT

COUNT

CLEAR
CLOCK

DONE

CLEAR
USER
TIME

SET
USER
TIME

CLOCK
OFF

TURN
CLOCK
ON

TURN

/
3

A 1 in bit 26 clears the clock counter and the Count Done, Count
Overflow and User Time flags, turns off the clock, and dismisses the PI
assignment (assigns zero).
The effect of giving conflicting conditions

PRIORITY

INTERRUPT

ASSIGNMENT
]

A 1 in bit 25 increments
the counter provided the clock
is off (this is for mainte-

is indeterminate.

nance only).

Conditions In, Clock

CONI CLK,

[

CLEAR

COUNT
DONE

70724

121314

17 18

Read the contents of the interval register into the left half of location £ and
read the status of the clock into bits 2635 as shown.
EXTERNAL
SOURCE

COUNT
OVERFLOW

USER

CLOCK

TIME

Interrupts are requested on the assigned channel by the setting of Count

PRIORITY

COUNT

Notes.
Overflow and Count Done.

INTERRUPT

DONE

ASSIGNMENT
|

*These bits request interrupts.

QYSTEM REFERENCE

-134-

2-112

CENTRAL PROCESSOR

§2.17

The counter is connected to an external source (0 indicates the
internal source is connected).

Note that to time a user prop-

The counter cannot be incremented while an interrupt is being held

erly, the Monitor must also

or a request has been accepted and the channel is waiting for an

compensate for any noninter-

rupt

time

taken

interrupt to start.

from the

user,

DATAQO CLK,

[

7oi4

The comparison of the coun-

Data Qut, Clock

[ x ]

121314

1718

]
35

Load the contents of the right half of location E into the interval register.

ter against the interval register

that follows every count is
inhibited while this instruction is loading the register.

DATAI CLK,

Data In, Clock

70704

121314

The counter is always stable

Read

while

being read, and any

count

held

location E.

back

picked

the

current

]
1718

35 .

contents of the clock counter into the right half of
'

up immediately afterward,

Following

turnon

the

first

count may occur at any time

up to the full period of the
source.

Remember that

although a
CONO need not affect the

mode or the clock state, every
CONO must renew the PI
assignment.

Initially the program should give a CONO CLK,1000 to clear the clock,
and then give a DATAO to select the interval and a CONO to turn on the

clock, select the mode, and assign the interrupt channel.

When the count

reaches the specified interval, Count Done sets, requesting an interrupt on
the assigned channel.

At the same time, the counter clears and a new count

begins with the next pulse.

The program should respond with a CONO to

clear Count Done.
The interval can be changed at any time simply by giving a DATAO.
However, if the program does not clear the counter at the same time, then it

should make sure that the count has not yet reached the value of the new
interval.

If the count is already beyond that point, the counter will con-

tinue until it overflows.

When the counter overflows, either because the

count started too high, the program specified the maximum count (28 is
selected by loading zero), or there is a malfunction of some sort, Count

Overflow sets, requesting an interrupt, and a new count begins.
To use the clock to time some operation, turn it on with the counter
at zero. For a counter reading of C, the elapsed time is

T(C
+ nl)
where T is the period of the source, n is the number of clock interrupts
since the clock was started, and / is the interval selected by the program. To
cause the clock to request an interrupt after 7 X n us, where n < 2'8 and T is

-135-

§2.18

SYSTEM REFERENCE

KA10 OPERATION

2-113

the period of the source in microseconds, load the interval register with »
expressed in binary.

There is an average indeterminacy of half a count every

time the counter starts and stops. Therefore, when the clock is keeping user
time, there is an average indeterminacy of one count for every group of
overlapping interrupts and requests (not for every interrupt, as the counter
is inhibited while there is any request or interrupt being held).
For keeping the time of day, the program can use a memory location to

maintain a count of the clock interrupts.

The location should be cleared

at midnight, and the time can be determined by combining its contents with

Note that an error of .01%

the current contents of the clock counter. If the location itself is to be used

amounts to 8.64 seconds in

as a low resolution clock kept in hours, minutes and seconds, it is better to

24 hours.

use a more convenient interval than the full count. Using the internal source,
an interval of 2% seconds, which is octal 750220, is the most straightforward
interval with the fewest interrupts.

would be 303240.
Operation. The

To interrupt every second the interval

N
KI10

clock, which is usually installed in a DECtape

cabinet, has a small control panel mounted directly on the logic behind the
cabinet -doors.

In the lower part of the panel is a switch for selecting the

internal source or an external input from the BNC connector at the right.
The external input must be supplied through a 100 ohm coaxial cable and
must have a frequency no greater than 400 kHz; its triggering voltage change

must be from —3 volts to ground. If the input is a pulse train, the minimum
pulse width is 100 ns.

If the input is a sequence of level changes, it must

have a minimum low level (—3 volts) duration of 400 ns before each positive-

going change, a rise time of 60 ns maximum, and a high level duration of
40 ns minimum.
The leftmost light in the upper row at the top of the panel indicates when
the clock is on (ie when the counter is enabled). The next two lights are the
Count Overflow and Count Done flags. TIME OUT indicates when the num-

bers in the interval register and the clock counter are identical — this light
goes out as soon as either changes state.

The remaining lights in the upper

row are the PI assignment. The two lights at the left in the lower row display
signals that synchronize the DATAI and DATAO to the clock so that count~

ing is postponed while the counter is being read and there is no sampling
while the interval is being loaded.

PIOKS8 is a processor-generated signal

which indicates that there is no interrupt being held and no channel waiting

for an interrupt; the next light is the User Time flag.

The final two lights

indicate the origin of the clock source.

2.18

KA10 OPERATION

Most of the controls and indicators used for normal operation of the processor and for program debugging are located on the console operator panel
shown here.

The indicators are on the vertical part of the panel;in front of

them are two rows of two-position keys and switches (keys are momentary
contact, switches are alternate action).

a 1 when the front part is down.

A key or switch is on or represents

Clock Control Panel

SYSTEM REFERENCE

2-114

=136~

CENTRAL PROCESSOR

(

§2.18

The thirty-six switches in the front row and the eighteen
at the right in the back row are respectively the data and
address switches through which the operator can supply

words and addresses for the program and for use in conjunction with the operating keys and switches.

The correspond-

ence of switches to bit positions is indicated by the numbers
at the bottom row of lights.

At the left end of the back row

are ten operating switches, which supply continuous control
levels to the processor.

At their right are ten operating keys,

which initiate or terminate operations in the processor. The
names of the operating keys and switches appear on the vertical part of the panel below the lights.
Also of interest to the operator is the small panel shown

opposite, which is located above the main panel at the left
of the tape reader.

The upper section of this panel contains

a total hours meter and the margin-check controls. The lower
section contains the power switch, speed controls for slowing

down the program, switches to select the device for readin
mode (lower part in represents a 1), and four additional
operating switches.

The normal position for these last four

is with the upper part in; in this position FM ENB (fast
memory enable) is on, the others are all off.

Indicators

When any indicator is lit the associated flipflop is 1 or the

associated function is true.

Some indicators display useful

information while the processor is running, but many change
too frequently and can be discussed only in terms of the

information they display when the processor is stopped. The
program can stop the processor only at the completion of the
HALT instruction; the operator can stop it at the end of

every instruction or memory reference, or for maintenance
purposes, after every step in any operation that uses the shift
counter (shifting, multiplication, division, byte manipulation).

Of the long rows of lights at the right on the operator
panel, the top row displays the contents of PC, the middle
row displays the instruction being executed or just completed,
and the bottom row are the memory indicators.

The right

half of the middle row displays MA, the left half displays IR
[see page 1-2]. In an IO instruction the left three instruction

lights are on, the remaining instruction lights and the left AC
light are the device code, and the remaining AC lights complete the instruction code. The I, index and MA lights change
with each indirect reference in an effective address calculation; at the end of an instruction I is always off.

Above the memory indicators appear two pairs of words,
PROGRAM DATA and MEMORY DATA.

If the triangular

light beside the former pair is on, the indicators display a

-137-

§2.18

SYSTEM REFERENCE

KA10 OPERATION

2-115

word supplied by a DATAO Pl1,; if any other data is
displayed

the light beside MEMORY DATA is on

instead.

While the processor is running the physical

addresses used for memory reference (the relocated
address whenever relpcation is in effect) are compared
with the contents of the address switches. Whenever
the

two

are

equal

location

are

displayed in the

the

contents

of the addressed

memory

indicators.

However, once the program loads the indicators, they
can be changed only by the program until the operator turns on the MI program disable switch, executes

a key function that references memory, or presses the
reset key (see below).
The four sets of seven lights at the left display the

state

of the priority interrupt channels

2-81 to 2-85].
channels

are

(see pages

The PI ACTIVE lights indicate which
on.

The

IOB PI

REQUEST lights

indicate which channels are receiving request signals

over the in-out bus; the PI REQUEST lights indicate
channels

quests.

Except in the case of a program-initiated

which the processor has accepted re-

-interrupt, a REQUEST light can go on only if the
corresponding

ACTIVE

light

on.

The

PROGRESS lights indicate channels on which interrupts are currently being held; the channel that is

actually being serviced is the lowest-numbered one
whose light is on.

When a PROGRESS light goes on,

the corresponding REQUEST goes off and cannot go
on again until PROGRESS goes off when the interrupt is dismissed.

At the left end of the panel are a power light and these control indicators..

Above: Margin Check and
Maintenance Panel
Opposite: Console Operator
Panel

Note: If a REQUEST light

RUN

The processor is in normal operation with one instruction following another.
When the light goes off, the processor stops.

stays on indefinitely with the
associated

PROGRESS light

off and PC is static, check the
PI CYC light on the indicator

panel at the top of bay 2. If
it is on, a faulty program has
PI ON

hung up the processor. Press

The priority interrupt system is active so interrupts can be started (this

STOP.

corresponds to CONI PI, bit 28).

PROGRAM STOP
IR

now contains a HALT instruction.

RUN

and

PROGRAM

If RUN is off, MA displays an

STOP are both on, the proc-

address one greater than that of the location containing the instruction that
caused the halt, and PC displays the jump address (the location from which

Zssgrt ‘z dlc)irrz:sabllgo mn arll)rérsl;

the next instruction will be taken if the operator presses the continue key).

Sl{woép

SYSTEM REFERENCE

-138-

2-116

CENTRAL PROCESSOR

§2.18

USER MODE
The processor is in user mode (this corresponds to bit 5 of a PC word).

MEMORY STOP
The processor has stopped at a memory reference. This can be due to single
cycle operation, satisfaction of an address condition selected at the console,

reference to a nonexistent memory location, or detection of a parity error.

The remaining processor lights are on the indicator panels at the tops of
the bays [illustrated on page F2].

Bay 2 displays AR, BR and MQ, the
output of the AR adder, and the parity buffer which receives every word

transmitted over the memory bus.

The RL and PR lights at the lower right

display the relocation and protection registers for the low part of the area
assigned to a user program and the left eight bits of the relocated address

for that part. The remaining lights are for maintenance.
The upper four rows on the bay 1 panel include the indicators for reader,
punch and teletype, which are described in Chapter 3.

The bottom row

displays the information on the data lines in the IO bus.

The AR lights at
the upper right are the flags — FXU is Floating (exponent) Underflow, DCK

is No Divide (divide check).

OV COND is the condition that the 0 and 1

carries are different, ie the condition that indicates overflow.

The First

Part Done flag is BYF6 in the MISC lights in the top row; User In-out is

IOT USER in the EX lights at the center of the panel.

The CPA lights in

the top row and the five lights under them at the left are the processor
conditions — PDL OV is Pushdown (list) Overflow. The AS= lights in the
middle row indicate when the (relocated) core memory address or the fast

memory address is the same as the address switches.

The remaining lights

are for maintenance.
The panels on the memories are shown in Appendix F.
These are
almost exclusively for maintenance, and (as with most of the lights on

the processor bays) if the operator must use them he should consult the
maintenance manual and the flow charts. The ACTIVE lights indicate which
processor currently has access to the memory.

Operating Keys
CAUTION

Each key except STOP turns on one of the key indicators at the upper right

Never press two keys simul-

on the bay 2 panel. These are for flipflops that allow the key functions to be

taneously

repeated automatically and also allow certain of them to be synchronized to

the

processor

may attempt to perform both

functions at once.

If RUN is oh, pressing this

key has no effect.

the processor time chain so they can be performed while the processor is
running.

READ IN
Clear all 10 devices and all processor flags including User; turn on the RIM
light in the upper right on bay 1 and the KEY RDI light in the upper right

SYSTEM REFERENCE

~-139-

§2.18

KA10 OPERATION

on bay 2. Execute DATAI D,0 where D is the device code specified by the
readin device switches on the small panel at the left of the reader. Then

execute a series of BLKI D,0 instructions until the left half of location 0

reaches zero, at which time turn off RIM and KEY RDI.

Stop only if the

single instruction switch is on; otherwise turn on RUN and execute the last

word read as an instruction.

[For information on the data format refer to

page 2-79.1]

2-117

The rightmost device switch
is for bit 9 of the instruction
and thus selects the least sig-

nificant octal digit (which is
always O or 4) in the device
code.

CaurionN
Do not initiate any other key

function while RIM is on. If
read in must be stopped (eg

START
Load the contents of the address switches into PC, turn on RUN, and begin
normal operation by executing the instruction at the location specified by

PC.

This key function does not disturb the flags or the IO equipment; hence
if USER MODE is lit a user program can be started.

because of a crumpled tape),
press RESET (see below).
If RUN is on, pressing this
key has no effect.

CONT (Continue)
Turn on RUN (if it is off) and begin normal operation in the state indicated

by the lights.

STOP
;
Turn off RUN so the processor stops before beginning the next instruction.
Thus the processor usually stops at the end of the current instruction, which

is displayed in the lights.

However, if a key function that can be performed
while RUN is on has been synchronized, the processor performs that function before stopping. In either case PC points to the next instruction.

If the processor does not reach the end of the instruction within 100 us,
inhibit further effective address calculation — it is assumed the processor is
caught in an indirect addressing loop. Pressing CONT when the processor is
stopped in an address loop causes it to start the same instruction over.

RESET
Clear all 10 devices and clear the processor including all flags:

Turn on the
triangular light beside MEMORY DATA (turn off the light beside PROGRAM DATA). If RUN is on duplicate the action of the STOP key before

If STOP will not stop the
processor,

pressing

this key

will.

clearing.

XCT
Execute the contents of the data switches as an instruction without incrementing PC. If RUN is on, insert this instruction between two instructions
in the program.

Inhibit priority interrupts during its execution to guarantee

that it will be finished.

If USER MODE is lit all user restrictions apply to an instruction executed

from the console.

Note that an instruction executed from the console can
alter the processor state just

any

instruction

in the

program: it can change PC by

jumping or skipping, alter the

flags,
or even cause a nonexistent-memory stop.

SYSTEM REFERENCE

~140-

2-118

CENTRAL PROCESSOR

§2.18

Note
The remaining key functions all reference memory.

They use an absolute address and all of memory is
available to them; in other words protection and

relocation are not in effect even if USER MODE is
lit.

However they can set such flags as Address

Break and Nonexistent Memory.

EXAMINE THIS

Display the contents of the address switches in the MA lights and the con-

tents of the location specified by the address switches in the memory indica-

tors.

Turn on the triangular light beside MEMORY DATA (turn off the

light beside PROGRAM DATA). If RUN is on, insert this function between
two instructions in the program.

EXAMINE NEXT
If RUN is on, pressing this
key has no effect.

Add 1 to the address displayed in the MA lights and display the contents of
the location specified by the incremented address in the memory indicators.

Turn on the triangular light beside MEMORY DATA (turn off the light
beside PROGRAM DATA).

DEPOSIT

Deposit the contents of the data switches in the location specified by the

address switches.

Display the address in the MA lights and the word

deposited in the memory indicators.

Turn on the triangular light beside
MEMORY DATA (turn off the light beside PROGRAM DATA). If RUNis

on, insert this function between two instructions in the program.

DEPOSIT NEXT
If RUN is on, pressing this
key has no effect.

Add 1 to the address displayed in the MA lights and deposit the contents of

the data switches in the location specified by the incremented address. Display the word deposited in the memory indicators. Turn on the triangular
light beside MEMORY DATA (turn off the light besidle PROGRAM DATA).

Operating Switches
Whenever the processor references memory at the location specified by the
address switches (relocated if USER MODE is on), the contents of that location

are

displayed

the

PROGRAM DATA is on).

memory

indicators

(unless the

light

beside

The group of five switches at the left of the keys

allows the operator to make the processor halt or request an interrupt when

-141-

-§2.18

SYSTEM REFERENCE

KA10 OPERATION

2-119

reference is made to the specified location in core memory for a particular
purpose (no action is produced by fast memory reference).
selected by the three address condition switches.

The purpose is

INST FETCH selects the

condition that access is for retrieval of an instruction (including an instruction executed by an XCT or contained in an interrupt location
or a trap for

AC and index register references can be included by
turning

off

the

ENB

switch (see below).

an unimplemented operation) or an address word in an effective address calculation.

DATA FETCH selects access for retrieval of an operand (other

than in an XCT).

WRITE selects access for writing in memory. Whenever
reference to the specified location satisfies any selected address condition,
the processor performs the action selected by the other two switches. ADR
STOP halts the processor with MEMORY STOP on (PC points to the instruc-

tion that was being executed, or if the MC WR light on bay 2 is on, PC may
point to the one following it); ADR BREAK turns on the CPA ADR BRK
light (Address Break flag, CONI APR, bit 21) on bay 1, requesting an interrupt on the processor channel.
The description of each switch relates the action it produces while it is on.

SING INST
Whenever the processor is placed in operation, clear RUN so that it stops at

the end of the first instruction. Hence the operator can step through a program one instruction at
a time, by pressing START for the first one and

CONT for subsequent ones. Each time the processor stops, the lights display
the same information as when STOP is pressed.
CLK FLAG (Clock flag) on bay 1 is held off to prevent clock interrupts
while SING INST is on.

Otherwise interrupts would occur at a faster rate

than the instructions.

SING INST will not stop the processor if a hangup prevents it from getting
to the end of an instruction. Use STOP or RESET.

SING CYCLE
Whenever the processor is placed in operation, stop it with MEMORY STOP

on at the end of the first core memory reference.

Hence the operator can

step through a program one memory reference at a time, by pressing START

for the first one and CONT for subsequent ones.

To determine what infor-

the

stop at

and index

references, turn off
FM ENB switch (see

below).

mation is displayed in the lights, consult the flow charts.

PAR STOP
Stop with MEMORY STOP on at the end of any memory reference in which
even parity is detected in a word read. A parity stop is indicated by the following: CPA PAR ERR (Parity Error flag) on bay 1 is on; and among the
PAR lights in the bottom row on bay 2, IGN (ignore parity) and ODD are

off, STOP is on, and BIT displays the parity bit for the word in the parity

buffer at the left.

If IGN is on (it displays a signal from the memory), parity
errors are not detected and no
stop can occur.

SYSTEM REFERENCE

-142-

2-120

CENTRAL PROCESSOR

§2.18

NXM STOP
Stop with MEMORY STOP on if a memory reference is attempted but the

memory does not respond within 100 us.

This type of stop is indicated by
CPA NXM FLAG (Nonexistent Memory flag) on bay 1 being on.

REPT
The key function is repeated

If any key (except STOP) is pressed, then every time the key function is

once

finished, wait a period of time determined by the setting of the speed control

after

REPT is turned
off, but this is noticeable only
with very long repeat delays.

and repeat the given key function.

If CONT is pressed and no switch is on

that would stop the program (eg SING INST, SING CYCLE), then continue
following the repeat delay whenever a HALT instruction is executed.

Con-

The end of a key function is

tinue to repeat the key function until RESET is pressed or REPT is turned

equivalent to completion of

off.

all processor operations associated with the function only

for read in, examine, examine
next,

deposit,

and

deposit

The speed control includes a six-position switch that selects the delay
range and a potentiometer for fine adjustment within the range.

Delay

ranges are as follows.

next. In other cases the processor continues in operation.

the

execute function is

Position

Range

270 ms to 5.4 seconds

38 ms to 780 ms

instruction. Hence when using speed

3.9 msto 78 ms

390 us to 7.8 ms

range 6, the operator must be

27 us to 540 us

2.2 us to 44 us

finished once the instruction
to be executed is set up
internally, but the processor

then

executes

that

careful not to allow the key
function to restart before the
processor is really finished.

MI PROG DIS

Turn on the triangular light besidle MEMORY DATA (turn off the light
beside PROGRAM DATA) and inhibit the program from displaying any information in the memory indicators.

The indicators will thus continually

display the contents of locations selected from the console.

REPT BYP

If REPT is on, trigger the repeat delay at the beginning of the key function.
Hence the function is repeated even if it does not run to completion.

FM ENB
This switch is left on for normal operation with a fast memory.

Turning it
off (lower part in) substitutes the first sixteen core locations for the fast
memory. The switch is left off if there is no fast memory, and it can be used
to allow stopping or breaking at fast memory references.

-143-

K110 OPERATION

§2.19

SHIFT CNTR MAINT

Stop before each step in any shift operatlon Pressing CONT resumes the

operation.

Once a shift has been stopped, the processor will continue to

stop at each step throughout the rest of the given shift operation even if the
switch is turned off.

At the right end of panel 1J behmd the bay doors are two toggle sw1tches
FP TRP causes the floating point and byte mampulatlon instructions (codes
130-177) to trap to locations 60-61. MA TRP OFFSET moves the trap
and interrupt locations to 140-161 for a second processor connected to the
same memory.

Inside each memory bay are switches for selecting the memory number

and interleaving memories. Alsoin the memory are a power switch, a restart
pushbutton, and a switch for single step operation (these three are located
on the indicator panel for the MB10 memory).

NOTE

Information on the KI10 operation is not available
at this time.

SYSTEM REFERENCE
2-121

-145-

Appendices

SYSTEM REFERENCE

-147-

SYSTEM REFERENCE

APPENDIX A

INSTRUCTION AND DEVICE MNEMONICS

The illustration on the next page shows the derivation of the instruction
mnemonics.

The two tables following it list all instruction mnemonics and
their octal codes both numerically and alphabetically. When two mnemonics
are given for the same octal code, the first is the preferred form, but
the

assembler does recognize the second. For completeness, the table includes

the MUUOs (indicated by an asterisk) that are recognized by Macro

for communication with the DECsystem—10 Time Sharing Monitor. A double dagger

(}) indicates a KI10

instruction code thatis unassignedin the KA10.

In-out device codes are included only in the alphabetic listing and are
indicated by a dagger (f).
Following the tables is a chart that lists the

devices with their mnemonic and octal codes and DEC option numbers for

both PDP-10 and PDP-6.

A device mnemonic ending in the numeral 2is

the recommended form for the second of a given device, but such codes are

_ not recognized by Macro — they must be defined by theuser.

Beginning on page All is a hst of all instructions showing their actions

in symbohc form

-148-

SYSTEM REFERENCE

MNEMONICS

ADD

Negative

MOV{°© M g4 ‘t |
¢

)

SUBtract

viagnitude

MULtiply

to AC

e Swapped

Immediate to ac

no effect

Half word fi%ht} to l]-lxfigfht] gnes
i

tLeft

Eeros

Integer DIVide

Immediate

to Memory

to Both

~and Round

Floating AdD

xtend sign }

BLock Transfer

DIVide

to Ig’lemory
t

Integer MULtiply | -

Floating SuBtract

Long

Floating MultiPly

EXCHange ac and memory

to Memory

Floating DiVide

to Both

Floating SCale

use present pointer}

LoaD Byte into ac

" Double Floating Negate

Increment pointer

DePosit Byte in memory

Unnormalized Floating Add

Increment Byte Pointer

FIX
FIX and Round

PUSH down} { ~

POP up

)

FLoaTand Round

and Jump

Double Floating AdD

Zeros

Double Floating SuBtract

Double Floating MultiPly

Ones

Double Floating DiVide

e Negative

Complement of Ac
Compl

(Lompiement of

of M

AND

lemoryJ

with Complement of Ac

inclusive OR { | with Complement of Memory |

AC‘

AC Immediate

Memory

and Save Ac

Both

and Restore Ac
if Find First One

Inclusive OR
eXclusive OR

Jumpd

EQuiValence
‘

on Flag and CLear it
©7 OVerflow (JECL 10,)

PYon CaRrY 0 (JECL 4))
on CaRrY 1

never

Add One to

{ memory and Skip if

Subtract One from | | Ac and Jump

Compare AcACY Immediate
nd skipip if AC
L
Memory | 2

on Floating OVerflow (JFCL 1,)
and ReSTore

Less
Equal

Less or Equal

rmg g;s:‘lore F:la g8 (1JR(§FII;SA’2F’) 12)

Always

Greater
1(\I}reate.r olr Equal

p ( Not equa

ROTate

est A

{Combined

Left with £

’

Out

CQNdltlonS in and Skip if all masked bits Zero
P}

No modification

with Swapped mask { ) set masked bits to Zeros

Right with £

able Pt channe

e XeCuTe

BLocK

with Direct mask

Test

HALT
(JRST 4,)
PORTAL (JRST1,)

DATA }

;

Arithmetic SHift

(JFCL 2)

on CaRrY (JFCL 6,)

ositive
Add One to Both halves of ac and Jump if. {Negative

Logical SHift

to SubRoutine

and Save Pc

Complements of Both

SKIP if memory
JUMP if ac

to Memory

set masked bits to Ones [

Complement masked bits

never

nd ski

if all masked bits Equal 0

PYif Not all masked bits equal 0
Always

some masked bit One

-149-

SYSTEM REFERENCE

NUMERIC LISTING

INSTRUCTION MNEMONICS
NUMERIC LISTING

000

ILLEGAL

001
LUUO’S

037

040

*CALL

041

*INIT

042

043

044
045

RESERVED
FOR
SPECIAL
MONITORS

046

106

162

FMPM

107

163

FMPB

FMPR

110

tDFAD

164

111

+DFSB

165

FMPRI

112

$DFMP

166

FMPRM

113

$DFDV

167

FMPRB

170

FDV

114
115

171

FDVL

116

172

FDVM

117

173

FDVB

174

FDVR

120

$DMOVE

121

$DMOVN

175

FDVRI

047

*CALLI

122

$FIX

176

FDVRM

050

*OPEN

123

177

FDVRB

051

*TTCALL

124

iDMOVEM

200

MOVE

125

DMOVNM

201

MOVEI

126

IFIXR

202

MOVEM

127

tFLTR

203

MOVES

MOVS

052
053

RESERVED

FOR DEC

054
055

*RENAME

130

UFA

204

056

*IN

131

DFN

205

MOVSI

057

*QUT

132

FSC

206

MOVSM

060

*SETSTS

133

IBP

207

MOVSS

061

*STATO

134

ILDB

210

MOVN

062

*STATUS

135

LDB

211

MOVNI

062

*GETSTS

136

IDPB

212

MOVNM

063

*STATZ

137

DPB

213

MOVNS

064

*INBUF

140

FAD

214

MOVM

065

*QOUTBUF

141

FADL

215

MOVMI

066

*INPUT

142

FADM

216

MOVMM

067

*QUTPUT

143

FADB

217

MOVMS

070

*CLOSE

144

FADR

220

IMUL

071

*RELEAS

145

FADRI

221

IMULI

072

*MTAPE

146

FADRM

222

IMULM

. 073

*UGETF

147

FADRB

223

IMULB

074

*USETI

150

FSB

224

MUL

075

*USETO

151

FSBL

225

MULI

076

*LOOKUP

152

FSBM

226

MULM

077

*ENTER

153

FSBB

227

MULB

100

*UJEN

IDIV

154

FSBR

230

101

155

102

FSBRI

231

IDIVI

156

FSBRM

232

'IDIVM

103

157

FSBRB

233

IDIVB

104

160

FMP

234

105

DIV

161

FMPL

235

DIVI

-150-

SYSTEM REFERENCE

MNEMONICS

236

DIVM

306

CAIN

367

SOJG

237
240
241

DIVB
ASH
ROT

307
310
311

CAIG
CAM
CAML

370
371
372

SOS
SOSL
SOSE

242

LSH

312

CAME

373

SOSLE

244

ASHC

314

CAMA

375

SOSGE

246

LSHC

316

CAMN

377

SOSG

247
250
251
252

EXCH
BLT
AOBJP

317
320
321
322

CAMG
JUMP
JUMPL
JUMPE

400
400
401
401

324

JUMPA

402

243

JFFO

245

253

254

313

ROTC

CAMLE

315

AOBIN

CAMGE

323

JRST

374

JUMPLE

376
.

402

SOSA

SOSN

SETZ
CLEAR
SETZI

CLEARI

SETZM

CLEARM

25404

PORTAL

325

JUMPGE

403

SETZB

25410

JRSTF

326

JUMPN

403

CLEARB

25420

HALT

327

JUMPG

404

AND

25450

JEN

330

SKIP

" 405

ANDI

255

JFCL

331

SKIPL

406

ANDM

25504
25510
25520
25530

JFOV
JCRY1
JCRYO
JCRY

332
333
334
335

SKIPE
SKIPLE
SKIPA
SKIPGE

407
410
411
412

ANDB
ANDCA
ANDCAI
ANDCAM

256

XCT

337

SKIPG

414

SETM

25540

JOoV

336

SKIPN

413

257

TMAP

340

AOJ

AOJL

416

261

PUSH

342

AOJE

417

SETMB

262

POP

343

AOJLE

420

ANDCM

263

POPJ

344

AOJA

421

ANDCMI

264

JSR

345

AOJGE

422

ANDCMM

265

JSP

346

AOIN

423

ANDCMB

266

JSA

347

AOJG

424

SETA

267

JRA

350

AOS

425

SETAI

270

ADD

" 351

AOSL

426

SETAM

271

ADDI

352

AOSE

427

SETAB

272

ADDM

353

AOSLE

430

XOR

273

ADDB

354

AOSA

431

XORI

274

SUB

355

AOSGE

432

XORM

275

SUBI

356

AOSN

433

XORB

276

‘SUBM

357

AOSG.

434

IOR

277

SUBB

360

SOJ

434

300

CAI

361

SOJL

435

IORI

301

CAIL

362

SOJE

435

ORI

302

CAIE

363

SOJLE

436

IORM

303

CAILE

364

SOJA

436

ORM

304

CAIA

365

SOJGE

437

IORB

305

CAIGE

366

SOIN

437

ORB

260

PUSH]J

341

415

ANDCAB
SETMI

SETMM

-151-

SYSTEM REFERENCE

NUMERIC LISTING

440

ANDCB

521

HLLOI

602

TRNE

441

ANDCBI

522

HLLOM

603

TLNE

442

- ANDCBM

523

HLLOS

604

TRNA
TLNA
TRNN

443

ANDCBB

524

HRLO

605

444

EQV

525

HRLOI

606

445

EQVI

526

HRLOM

607

446

EQVM

527

HRLOS

610

447

EQVB

530

HLLE

611

450

SETCA

531

HLLEI

612

TDNE

451

SETCAI

532

HLLEM

613

TSNE

452

SETCAM

533

HLLES

614

TDNA

453

SETCAB

534

HRLE

615

TSNA

454

ORCA

535

HRLEI

616

TDNN

455

ORCAI

536

HRLEM

617

TSNN

456

ORCAM

537

HRLES

620

TRZ

457

ORCAB

540

HRR

621

TLZ

460

SETCM

541

HRRI

622

TRZE

461

SETCMI

542

HRRM

623

TLZE

462

SETCMM

543

HRRS

624

TRZA

463

SETCMB

544

HLR

625

TLZA

464

ORCM

545

HLRI

626

TRZN

465

ORCMI

546

HLRM

627

TLZN

466

ORCMM

547

HLRS

630

TDZ

467

ORCMB

550

HRRZ

631

TSZ

470

ORCB

551

HRRZI

632

TDZE

471

ORCBI

552

HRRZM

633

TSZE

472

ORCBM

553

HRRZS

634

TDZA

473

ORCBB

554

HLRZ

635

TSZA

474

SETO

555

HLRZI

636

TDZN

475

SETOI

556

HLRZM

637

TSZN

476

SETOM

5357

HLRZS

640

TRC

477

SETOB

560

HRRO

641

TLC

500

HLL

561

HRROI

642

TRCE

501

HLLI

562

HRROM

643

TLCE

502

HLLM

563

HRROS

644

TRCA

503

HLLS

564

HLRO

645

TLCA

504

HRL

565

HLROI

646

TRCN

505

HRLI

566

HLROM

647

TLCN

506

HRLM

567

HLROS

650

TDC

507

HRLS

570

HRRE

651

TSC

510

HLLZ

571

HRREI

652

TDCE

511

HLLZI

572

HRREM

653

TSCE

512

HLLZM

573

TDCA

HLLZS

574

HRRES
HLRE

654

513

655

TSCA

514

HRLZ

575

HLREI

656

TDCN

515

HRLZI

576

HLREM

657

TSCN

516

HRLZM

577

HLRES

660

TRO

517

HRLZS

600

TRN

661

TLO

520

HLLO

601

TLN

662

TROE

TLNN

TDN
TSN

SYSTEM REFERENCE

-152-

MNEMONICS
663

TLOE

673

TSOE

70010

664

TROA

674

TDOA

70014

DATAO

665

TLOA

675

TSOA

70020

CONO
CONI

BLKO

666

TRON

676

TDON

70024

667

TLON

677

TSON

70030

CONSZ

670

TDO

70000

BLKI

70034

CONSO

671

TSO

70004

DATAI

672

TDOE

70004

RSW

INSTRUCTION MNEMONICS
ALPHABETIC LISTING

tADC

- 024

AOSA

354

TCDP

ADD

270

AOSE

352

+CDR

ADDB

273

AOSG

357

CLEAR

400

ADDI

271

AOSGE

355

CLEARB

403

ADDM

272

AOSL

351

CLEARI

401

AND

404

AOSLE

353

CLEARM

402

ANDB

407

AOSN

356

ANDCA

ANDCAB
ANDCAI

410

413
411

+APR

ANDCAM

ANDCB

ANDCBB
ANDCBI
ANDCBM

110
114

TCLK

070

ASH
ASHC

000

240
244

*CLOSE

070

412

BLKI

70000

CONSO

70034

440

BLKO

70010

CONSZ

70030

DATAO

70014

443
441
442

BLT
CAl
CAIA

251
300
304

CONI
CONO

70024
70020

+CPA
+CR
DATAI

000
150
70004

ANDCM

420

CAIE

302

ANDCMB

423

CAIG

307

+DC

200

ANDCMI

421

CAIGE

305

+DCSA

300

ANDCMM

422

CAIL

301

+DCSB

304

ANDI

405

" CAILE

303

tDFAD

110

ANDM

406

CAIN

306

tDFDV

113

AOBIN

253

*CALL

040

1 DFMP

112

DFN

131

AOBJP

AO]J

340

252

*CALLI

047

310

+DFSB

AOJA

344

CAMA

314

AOJE

342

CAME

312

+DIS
DIV

CAML

311

CAMLE

313

AOIJG
AOIJGE

347
345

AOJL

341

AOJLE

343

AOJIN
AOS

CAM

346
-

350

CAMG
CAMGE
'

CAMN
TCCI

317
315 -

316
014

DIVB
DIVI

DIVM

111
-

130
234

237
235

236

+DLB

060

TDLS

240

+DLC

064

-153-

SYSTEM REFERENCE

ALPHABETIC LISTING

+tDMOVE

120

FSBRB

157

HRLS

tDMOVEM

507

124

FSBRI

155

HRLZ

tDMOVN

514

121

FSBRM

tDMOVNM

125

FSC

156
132

HRLZI
HRLZM

515
516

DPB

137

HRLZS

517

HRRE

570

*GETSTS

062

+DSI

250

464

HALT

25420

+DSK

170

HLLE

530

HRREI

571

+DSS

460

HLLEI

531

HRREM

572

tDTC

320

HLLEM

532

t+DTS

HRRES

324

573

HLLES

533

HRRI

541

+DPC

HLL

HRR

500

501

540

*ENTER

077

HLLI

HRRM

542

EQV

444

HLLM

502

HRRO

EQVB

560

447

HLLO

520

HRROI

561

EQVI

445

HLLOI

521

HRROM

562

EQVM

446

HLLOM

522

HRROS

563

EXCH

250

HLLOS

523

HRRS

543

FAD

140

HLLS

503

HRRZ

550

HRRZI

551

FADB

143

HLLZ

510

FADL

141

HLLZI

511

HRRZM

FADM

552

142

HLLZM

512

HRRZS

553

HLLZS

513

IBP

133

HLR

544

IDIV

230

FADR

144

FADRB

147

FADRI

145

HLRE

574

FADRM

IDIVB

233

146

HLREI

575

IDIVI

231
232

FDV

170

HLREM

576

FDVB

IDIVM

173

HLRES

577

FDVL

IDPB

171

136

HLRI

545

ILDB

134

FDVM

172

HLRM

546

FDVR

IMUL

174

220

HLRO

564

FDVRB

IMULB

177

223

HLROI

565

FDVRI

IMULI

175

221

HLROM

566

IMULM

222

FDVRM

176

HLROS

567

056
064

041

TFIX

122

HLRS

547

*IN
*INBUF

$FIXR

126

$FLTR

HLRZ

554

127

*INIT

HLRZI

555

*INPUT

FMP
FMPB

160
163

HLRZM
HLRZS

556
557

IOR
IORB

434
437

FMPL

161

HRL

504

IORI

435

FMPM

162 -

HRLE

534

IORM

436

FMPR

164

HRLEI

535

JCRY

25530

FMPRB

167

HRLEM

536

JCRYO

FMPRI

25520

165

HRLES

537

JCRY1

25510

FMPRM

166

HRLI

505

JEN

25460

FSB

150

HRLM

506

JFCL

FSBB

153

HRLO

524

JFFO

255

FSBL

151

HRLOI

525

FSBM

152

HRLOM

526

JFOV

Jov

25504

FSBR

154

HRLOS

527

JRA

267

066

243

25540

SYSTEM REFERENCE

-154-

MNEMONICS

JRST

254

ORCAI

455

SETOM

JRSTF

25410

ORCAM

456

*SETSTS

060

JSA

266

ORCB

470

SETZ

400

JSP

265

ORCBB

473

SETZB

403

JSR

264

‘ORCBI

471

SETZI

401

JUMP

320

ORCBM

472

SETZM

402

JUMPA

324

ORCM

464

SKIP

330

JUMPE

322

ORCMB

467

SKIPA

334

JUMPG

327

ORCMI

465

SKIPE

332

JUMPGE

325

ORCMM

466

SKIPG

337

JUMPL

321

ORI

435

SKIPGE

335

JUMPLE

323

ORM

436

SKIPL

331

JUMPN

326

*OUT

057

SKIPLE

333

LDB

135

*OUTBUF

065

SKIPN

336

076

*OUTPUT

067

SOJ

360

*LOOKUP
+LPT

124

TPAG

010

SOJA

364

SOJE

362

LSH

242

TPI

004

LSHC

246

tPLT

140

IMAP

257

+MDF

260

476

S0JG

367

262

SOJGE

365

POPJ

263

SOJL

361

PORTAL

25404

SOJLE

363

100

SOJN

366

SOS

370

SOSA

374

POP

MOVE

200

MOVEI

201

TPTP

tPTR

MOVEM

202

MOVES

203

PUSH

261

MOVM

214

PUSHJ

260

MOVMI

215

*RELEAS

071

*RENAME

055

104
.

SOSE

372

SOSG

377

SOSGE

375

SOSL

371
373

MOVMM

216

MOVMS

217

ROT

241

MOVN

210

ROTC

245

MOVNI

211

RSW

70004

SOSLE
SOSN

MOVNM

212

SETA

424

*STATO

061

376

MOVNS

213

SETAB

427

*STATUS

062

MOVS

204

SETAI

425

*STATZ

063

MOVSI

205

SETAM

426

SUB

274

MOVSM

206

SETCA

450

SUBB

277

MOVSS

207

SETCAB

453

SUBI

275

*MTAPE

072

SETCAI

451

SUBM

276

SETCAM

452

TDC

650

FMTC

220

FMTM

230

SETCM

460

TDCA

FMTS

654

224

SETCMB

463

TDCE

652

MUL

224

SETCMI

461

MULB

227

TDCN

656

SETCMM

462

MULI

TDN

225

610

SETM

414

TDNA

MULM

226

614

SETMB

417

TDNE

612

*OPEN

050

SETMI

415

TDNN

434

616

SETMM

416

TDO

ORB

437

670

SETO

474

TDOA

ORCA

454

674

SETOB

477

ORCAB

TDOE

457

672

SETOI

475

TDON

676

-155-

SYSTEM REFERENCE

ALPHABETIC LISTING

TDZ

630

TRCA

TDZA

644

634

TSO

TRCE

671

TDZE -

642

632

TSOA

675

TRCN

TDZN

646

636

TSOE

TRN

673

600

TSON

677

TLC

641

TRNA

TLCA

604

645

TRNE

TSZ

602

631

TSZA

635

633

TLCE

643

TRNN

TLCN

606

647

TRO

TSZE

TLN

660

601

TROA

TSZN

664

637

*"TCALL

051

TLNA

605

TROE

TLNE

662

603

TRON

UFA

130

TLNN

666

607

*UGETF

TRZ

073

620

TLO

*UJEN

661

TRZA

100

624

*USETI

074

075

TLOA

665

TRZE

622

TLOE

663

*USETO

TRZN

626

TLON

+UTC

667

TSC

210

651

TUTS

214

TLZ

621

TSCA

655

TLZA

XCT

625

TSCE

256

653

TLZE

623

XOR

TSCN

430

657

TLZN

627

TSN

611

FTMC

340

TSNA

615

+TMS

344

TSNE

613

TSNN

617

TRC

640

XORB

433

XORI

431

XORM

432

SYSTEM REFERENCE

AlO

-156-

. _ 0ldA: o1|01dA 01[01d3 o 0 o o

u«u;ua302 pasq-Wik9-d0d91—=°_._ol|-$wHqunu0)9~d(d

MNEMONICS

NOODV3S:1QH0INL

i |

SYSTEM REFERENCE

-157-

All

ALGEBRAIC REPRESENTATION

ALGEBRAIC REPRESENTATION
The remaining pages of this Appendix list, in symbolic form, the actual
operations performed by the instructions. The grouping, as given below, dif-

fers slightly from that used in Chapter 2.
Boolean

Al13

In-out

Byte manipulation

Al7

Al4

Program control

Al7

Fixed point arithmetic

Al4

Pushdown list

Floating point arithmetic

Al7

Al4

Shift and rotate

Al7

Full word data transmission

AlS

Test, arithmetic

Al8

Half word data transmission

Al6

Test, logical

Al9

The terminology and notation used also vary somewhat from that in the

body of the manual, as follows.
AC

The accumulator address in bits 9—12 of the instruction word

(represented by A in the instruction descriptions).

AC+1

The address one greater than AC, except that AC+1 is 0 if AC is
17.

The result of the effective address calculation. E is eighteen bits
when used as an address, half word operand, mask or output conditions, butis a signed 9-bit quantity when used as a scale factor
or a shift number.

E+1

The address one greater than E, except that E+1 is O if E is
777777.

The 18-bit program counter.

(X)

The word contained in register X.

The left half of (X).

(X)r

The right half of (X).

(X)s

The word contained in X with its left and right halves swapped.
The value of bit n of the quantity A.

A.B

A 36-bit word with the 18-bit quantity A4 in its left half and the
18-bit quantity B in its right half (either
A or
B may be 0).

The contents of registers X and Y concatenated into a double
word operand.

(X))

The word contained in the register addressed by (X), ie addressed
by the word in register X.

A->B

The quantity A4 replaces the quantity B (4 and B may be half
words, full words or double words). Eg

(AC) + (E) = (AC)
means the wordin accumulator AC plus the wordin memory

cation E replaces the wordin AC.

lo-

(AC) (E)

The wordin AC and the wordin E.

AV ¥~

The Boolean operators anp, inclusive or, exclusive OR, and complement (logical negation).

-158-

SYSTEM REFERENCE
Al2

MNEMONICS

+ — X + ||

The arithmetic operators for addition, negation or subtraction,
multiplication, division, and absolute value (magnitude).

Square brackets are used occ‘asionally for grouping. With respect to the
values of their terms, the equations for a given instruction are in chronological order; eg in the pair of equations
(AC) + 1> (AO)
If (AC) =0:

E—->(PO)

the quantity tested in the second equation is the word in AC after it has been
incremented by one.

~159-

- SYSTEM REFERENCE

ALGEBRAIC REPRESENTATION

Al3

Boolean

SETZ

400

00— (AC)

SETO .

474

717777777777 = (AC)

SETZI

401

0-(AO)

SETOI

475

711777777777 = (AC)

SETZM

402

6> ()

SETOM

476

777777777777 > (E)

SETZB

403

0- (AC) (E)

SETOB

477

177777777777 — (AC) (E)

SETA

424

(AC) —> (AC) [no-op]

SETCA

450

~ (AC) = (AC)

SETAI .

425

(AC) = (AC) [no-op]

SETCAI

451

~ (AC) = (AC)

SETAM

426

(AC) = (E)

SETCAM

452

~ (AC) - (E)

SETAB

427

(AC) ~> (E)

SETCAB

453

~ (AC) = (AC) (E)

SETM

414

(E) > (AC)

SETCM

460

~ (E) > (AC)

SETMI

415

0,E = (AC)

SETCMI

461

~ [0,E] = (AC)

SETMM

416

(E) = (E) [no-opl

SETCMM

462

~ (E) > (E)

SETMB

417

(E) = (AC) (E)

SETCMB

463

~ (E) > (AC) (E)

AND

404

(AC) A (E) = (AC)

ANDCA

410

~ (AC) A (E) > (AC)

ANDI

405

(AC) A OE = (AO)

ANDCAI

411

~(AC) A 0,E > (AC)

ANDM

406

(AC) A (E) = (E)

ANDCAM

(AC) A (E) - (AC) (E)

~ (AC) A (E) > (E)

407

ANDCAB

412

- ANDB

413

~ (AC) A (E) > (AC) (E)

ANDCM

4290

(AC) A ~ (E) > (AC)

ANDCB

440

~ (AC) A ~ (E) > (AC)

ANDCMI

421

(AC) A ~ [0,E] ~ (AC)

ANDCBI

441

~ (AC) A ~ [0,E] = (AC)

ANDCMM

422

(AC) A ~ (E) > (E)

ANDCBM

442

~(AC) A ~(E) > (E)

ANDCMB

423

(AC) A ~ (E) ~ (AC) (E)

ANDCBB

443

~ (AC) A ~ (E) > (AC) (B)

IOR

434

(AC) v (E) = (AC)

ORCA

454

435

(AC) V 0.E - (AC)

ORCAI

~ (AC) v (E) ~> (AC)

IORI

455

~ (AC) Vv 0,E ~ (AC)

IORM

436

ORCAM

456

~(AC) vV (E) > (E)

IORB

437

(AC) v (E) ~ (E)

(AC) v (E) > (AC) (E)

ORCAB

457

~(AC) v (E) > (AC) (E)

ORCM

464

(AC) v ~(E)~ (AC)

ORCB

470

~ (AQ) Vv ~ (E) = (AO)

ORCMI

465

(AC) v ~ [0,E] > (AC)

ORCBI

471

ORCMM

466

(AC) v ~(E)—> (E)

ORCBM

472

ORCMB

467

(AC) vV ~ (E) > (AC) (E)

ORCBB

473

~(AC)V ~ (E) - (AC) (E)

XOR

430

(AC) ¥ (E) > (AO)

EQV

444

~ [(AC) ¥ (E)] - (AC)

XORI

431

(AC) ¥ 0,E = (AQ)

EQVI

445

~ [(AC) v 0,E] = (ACQ)

XORM

432

(AC) ¥ (E) > (E)

EQVM

446

~ [(AC) ¥ (E)] > (E)

XORB

433

(AC) ¥ (E) ~ (AC) (B)

EQVB

447

~ [(AC) ¥ (E)] > (AC) (E)

~(AC)V ~ [0,E] > (AC)
~(AQ)V ~ (E) > (E)

SYSTEM REFERENCE

-160-

Ald

MNEMONICS

Byte Manipulation
IBP

133

Operations on (E) [see page 2-16]
IfP-S=20:. P-S—~>P
IfP-S<0:

Y+1-Y

36 -S->P

LDB

135

BYTEIN ((E)) = (AC) [see page 2-16]

DPB

137

BYTEIN (AC) > BYTEIN ((E)) [see page 2-16]

ILDB

134

IBP and LDB

IDPB

136

IBPand DPB

Fixed Point Arithmetic

ADD

270

(AC) + (E) » (AO)

SUB

274

(AC) — (E)—~ (AO)

ADDI

271

(AC) + 0,E - (AC)

SUBI

275

(AC) - 0,E—~ (AC)

ADDM

272

(AC)+ (E)— (E)

SUBM

276

(AC) — (E)—~> (E)

ADDB

273

(AC) + (E) > (AC) (BE)

SUBB

277

(AC) — (E) > (AC) (B)

IMUL

220

(AC) X (E)—~ (AO)*

MUL

224

(AC) X (E) = (AC,AC+1)

IMULI

221

(AC) X 0,E—> (AC)*

MULI

225

(AC) X 0,E = (AC,AC+1)

IMULM

222

(AC) X (B)—»> (BE)*

MULM

226

(AC) X (E)-~ E)t

IMULB

223

(AC) X (E) = (AC) (BE)*

MULB

227

(AC) X (E) > (AC,AC+1) (E)

IDIV

230

(AC) + (E)—>(AC)

DIV

234

(AC,AC+1) ~ (E) = (AO)

DIVI

235

(AC,AC+1) + 0,E = (AC)

REMAINDER = (AC+1)
IDIVI

231

(AC) ~ 0,E > (AO)

REMAINDER —> (AC+1)

REMAINDER ~> (AC+1)

REMAINDER = (AC+1)

IDIVM

232

(AC) = (E)—(E)

DIVM

236

(AC,AC+1) + (E)~ (E)

IDIVB

233

(AO)+(EBE)~>(AO)(E)

DIVB

237

(AC,AC+1) + (E) » (AC) (E)

REMAINDER —> (AC+1)

REMAINDER ~> (AC+1)

*The high order word of the product is discarded.
tThe low order word of the product is discarded.

Floating Point Arithmetic
FAD

140

(AC) + (E) = (AC)

FADR

144

(AC) + (B) > (AC)

FADL

141

(AC) + (E) » (AC,AC+1)

FADRI

145

(AC) + E, 0~ (AC)

. FADM

142

(AC) + (E) > (E)

FADRM

146

(AC) + (E) > (E)

FADB

143

(AC) + (E) > (AC) (E)

FADRB

147

(AC) + (E) > (AC) (E)

FSB

150

(AC) — (E) = (AC)

FSBR

154

151

(AC) — (E) = (AC,AC+1)

FSBRI

(AC) — (E) - (AC)

FSBL

155

(AC) — E,0— (AC)

FSBM

152

(AC) — (E) = (E)

FSBRM

156

(AC) — (E) > (E)

FSBB

153

(AC) — (E) - (AC) (E)

FSBRB

157

(AC) — (E) > (AC) (E)

SYSTEM REFERENCE

-161-

AlS

ALGEBRAIC REPRESENTATION

FMP

160

(AC) X (E) > (AO)

FMPR

164

(AC) X (E)—> (AO)

FMPL

161

(AC) X (E)—~> (AC,ACH+1)

FMPRI

165

(AC) X E, 0~ (AC)

FMPM

162

(AC) X (E) = (E)

- FMPRM

166

(AC) X (E)—~(E)

FMPB

163

(AC) X (E)~> (AC) (BE)

FMPRB

167

(AC) X (E)—> (AC) (E)

FDV

170

(AC) +~ (E) > (AO)

FDVR

174

(AC) = (E) = (AC)

FDVL

171

(AC) + (E) » (AC)

FDVRI

175

(AC) ~ E,0~ (AC)

REMAINDER = (AC+1)

’

FDVM

172

(AC) ~ (E)~>(E)

FDVRM

176

(AC) ~ (E)—~> (E)

FDVB

173

(AC) ~ (E) > (AC) (E)

FDVRB

177

(AC) ~ (E) > (AC) (BE)

122

FIX

UFA

130

(AC) + (E) = (ACH+1) without normalization

DFN

131

- (AC,E) - (AC,E)

FSC

132

(AC) X 22— (AQ)

FLTR

127

(E) floated, rounded — (AC)

(B) fixed - (AC)

FIXR

126

(E) fixed, rounded — (AC)

DFAD

110

(ACAC+1) + (E,E+1) ~ (AC,AC+1)

DFSB

111

(ACAC+1) — (E,E+1) »> (AC,AC+1)

DFMP

112

(AC,AC+1) X (E,E+1)—> (AC,AC+1)

DFDV

113

(AC,AC+1) = (E,E+1) = (AC,AC+1)

DMOVE

120

(E,E+1) - (AC,AC+1)

DMOVEM

124

(ACAC+1)—> (E,E+1)

DMOVN-

121

—(E.E+1) > (AC,AC+1) .

DMOVNM

125

—(AC,AC+1)— (E,E+1)

Full Word Data Transmission
250

(AC) < (E)

BLT

251

Move E — (AC)g + 1 words starting with ((AC)) > ((AC)R) [see page 2-10]

MOVE

200

(E) = (AC)

MOVS

204

(E)s— (AQ)

MOVEI

201

0,E = (AC)

MOVSI

205

E,0 (AO)

MOVEM

202

(AC) = (E)

MOVSM

206

(AQ)g— (E)

MOVES

203

If AC#0: (E)— (AC)

MOVSS

207

EXCH

(E)s—>(E)
If AC#0: (E)—> (AO)

MOVN

210

- (E) » (AO)

MOVM

214

[(E)I = (AC)

MOVNI

211

— [0,E] = (AC)

MOVMI

215

0,E—=(AQ)

212

—(AC) > (B)

MOVMM

216

[|[(AO)|—>(E)

213

= (E)~> (E)

MOVMS

217

MOVNM
MOVNS

If AC#0: (E)—~> (AC)

I(BE)I=(E)

If AC#0: (E)
> (AC)

-162-

SYSTEM REFERENCE

Al6

MNEMONICS

Half Word Data Transmission
HLL

500

(E), > (AC)

HLLZ

510

(E),0 > (AC)

HLLI

501

HLLZI

511

HLIM

502

(AC). > (E),

HLLZM

512

(AC),0 > (E)

HLLS

503

If AC#0: (E)->(AC)

HLLZS

513

(AC),

(AC)

0> (E)r

If AC # 0: (E)~(AC)
HLLO

520

HLLOI

(E).,777777 = (AC)

HLLE

530

(E),[(E) X 777777] = (AC)

521

0,777777 - (AC)

HLLEI

531

‘0

HLLOM

522

(AC).,777777 - (E)

HLLEM

532

(AC)L,I(AC), X 777777]1 = (E)

HLLOS

523

777777 = (E)g

HLLES

533

(AC)

(E)o X 777777 = (E)g
If AC # 0:

If AC#0: (E)— (AC)

(E)— (AC)

(Ex ~> (AC)x

HLRZ

554

0,(Ex. > (AC)

545

0> (ACx

HLRZI

555

0~ (AC)

HLRM

546

(ACy, > (E)r

HLRZM

556

0,(AC), > (E)

HLRS

547

(E)x > (B}

HLRZS

557

0,(E). > (E)

HLR

HLRI

544

If AC#0: (E) > (AQO)

If
AC # 0: (E)~>(AC)

HLRO

564

777777 (E), > (AC)

HLRE

574

[(E) X 7777771 (E). > (AC)

HLROI

565

777777,0 > (AC)

HLREI

575

0 - (AC)

HLROM

566

777777 ,(AC), ~> (E)

HLREM

576

[(AC) X 7777771 (AC), ~ (E)

HLROS

567

T77777,(E)x, = (E)

HLRES

577

If AC#0: (E)— (AC)
HRR

540

[(E) X 7T777771,(E)}, = (E)
If AC#0: (E)— (ACQ)

(E)r = (AC)

HRRZ

550

0,(E)s = (AC)

HRRI

541

E - (AC)k

HRRZI

551

0,E - (AO)

HRRM

542

(AC)r = (E)

HRRZM

552

0,(AC) ~> (E)

HRRS

543

If AC # 0:

HRRZS

553

(E) - (AC)

0~ (E),

If AC+#0: (E) > (AO)

HRRO

560

HRROI

561

HRROM

562

HRROS

563

777777 (E)g = (AC)

HRRE

570

[(E)s X 7777771 (E)x = (AC)
[Eis X 7777771 E > (AC)

HRREI

571

717777 ,(AC)g = (E)

HRREM

572

[(AC)ys X 777777] (AC)g ~> (E)

777777 = (E)

HRRES

573

(BE)s X 777777 > (Ex

" 777777,E - (AC)

If AC#0:

(E)— (AC)

If AC # 0:

(E)~ (AC)

504

(E)r
= (AC),

HRLZ

514

(E)r,0 > (AC)

HRLI

505

515

E,0 > (AC)

HRLM

506

HRLZM

516

HRLS

E - (AC),
(AC) > (E),

HRLZI

(AC),0~ (E)

507

(E)x = (E)

HRLZS

517

HRL

If AC #0: (E)~ (AC)

(E)r,0 > (E)
If AC+#0: (E)~> (AC)

SYSTEM REFERENCE

-163-

ALGEBRAIC REPRESENTATION

Al7

HRLO

524

Er, 777777 > (AC)

HRLE

534

HRLOI

525

E, 777777 = (AC)

HRLEI

535

HRLOM

526

(AC,777777 = (E)

HRLEM

536

HRLOS

527

(Ejr,777777 = (E)

HRLES

537

If AC#0:

(E)g,[(E)s X 777777] = (AC)

E,[E;s X 777777} = (AC)

(E) > (AC)

(AQC)g,[(AC),s X 777777] = (E)

(E)g,[(E)g X 7777771 = (E)

IfAC#0: (E) = (AQ)

In-out

‘

CONO

70020

E - commaNnD

CONSZ

70030

If statusg A E = 0: skip

CONI

70024

sTATUS = (E)

CONSO

70034

If statusg A E # 0: skip

DATAO

70014

(E) > paTA

DATAI

70004

para— (E)

BLKO

70010

(E) + 1000001 - (E)*

((E)r) = pATA [see page 2-77]

BLKI

70000

(E) + 1000001 — (E)*

DATA = ((E)R) [see page 2-77]

Program Control
JSR

264

FLAGS,(PC) = (E)

E + 1-(PC)

- JSP

265

FLAGS,(PC) = (AC)

E - (PC)

JRST

254

E - (PC)

[If AC # 0, see page 2-63]

E,(PC) = (AC)

JSA

266

(AC) — (E)

JRA

267

E = (PC)

JFCL

- 255

If AC A FLAaGs

XCT

256

Execute (E)

JFFO

243

E+1-(PC)

((AC)) = (AC)
0

E - (PC)

~ AC A FLAGS = FLAGS

If(AC)=0:

0~ (AC+1)

If (AC) # 0:

E — (PC) [see page 2-61]

MAP

257

PHYSICAL MAP DATA = (AC)

PUSH

261

(AC) + 1000001 - (AC)*

POP

262

((AC)p) = (E)

PUSHJ

260

(AC) + 1000001 = (AC)*

POPJ

263

((AC)p)r = (PC)

Pushdown List

(E)~ ((AC)R)

(AC) — 1000001 - (AC)*

FLAGS,(PC) > ((AC)R)

E = (PC)

(AC) - 1000001 - (AC)*

Shift and Rotate
ASH

240

(AC) X 2k > (AQ)

ASHC

245

(AC,AC+1) X 2E—> (AC,AC+1)

ROT

241

Rotate (AC) E places

ROTC

246

Rotate (AC,AC+1) E places

LSH

242

Shift (AC) E places

LSHC

247

Shift (AC,AC+1) E places

*In the KI10, 1 is added to or subtracted from each half separately.

SYSTEM REFERENCE

-164-

Al8

MNEMONICS

Arithmetic Testing

AOBJP

252

(AC) + 1000001 = (AC)*

If(AC)=0: E - (PC)

AOBIN

253

(AC) + 1000001 — (AC)*

If (AC)<0: E~> (PO

CAI

300

No-op

CAM

310

No-op

CAIL

301

If(AC)E: skip

CAML

311

If(AC) <(E): skip

CAIE

302

If(AC) = E: skip

CAME

312

If (AC) = (E): skip

CAILE

303

If(AC)<E: skip

CAMLE

313

If (AC) < (E): skip

CAIA

304

Skip

CAMA

314

Skip

CAIGE

305

If(AC)=E: skip

CAMGE

315

If(AC) = (E): skip

CAIN

306

If(AC)+E: skip

CAMN

316

If(AC) # (E): skip

CAIG

307

If(AC)> E: skip

- CAMG

317

If(AC) > (E): skip

JUMP

320

No-op

SKIP

330 ' IfAC#0: (E)~> (AO)

JUMPL

321

If(AC)<0: E—- (PC)

SKIPL

331

JUMPE

322

If(AC)=0: E~ (PC)

SKIPE

332

IfAC#0: (E)— (AO)

If (E) < 0: skip

IfAC#0: (E)— (AO)
If (E) = 0: skip

JUMPLE

323

If(AC)<0: E—- (PO

SKIPLE

333

)

JUMPA

324

If (E) < 0:

E->(PC)

SKIPA

334

IfAC+#0: (E)- (AO)
skip

IfAC+#0: (E)~ (AC)
Skip

JUMPGE

325

| If(AC)=0: E— (PO

SKIPGE

335

JUMPN

326

IfAC#0: (E)— (AO)
If (E) 2 0: skip

If(AC)#0: E - (PC)

SKIPN

336

IfAC+#0: (E)— (AO)
If (E) # 0: skip

JUMPG

327

If(AC)>0: E- (PO

SKIPG

337

IfAC#0: (E)» (AO)
If (E) > 0: skip

AOJ

340

AOJL

341

(AC)+1-(AQ)

SOJ

360

(AC)+1—-(AO)

SOJL

361

If (AC)<0:
AOJE

342

E~ (PC)

(AC)+ 1-(AO)

343

(AC)+ 1-(AO)
If (AC)<0:

AOJA

344

SOJE

362

SOJLE

363

SOJA

364

AOJGE

345

(AO)+1- (A0

E = (PO)

(AC) - 1= (A0
If (AC)< 0:

E - (PC)

E—(PC)

(AC)—-1-(AO)
If (AC) = 0:

E—» (PC)

(AC)+ 1- (AC)

(AC)—-1-(AO)

If (AC)<0:

If (AC) =0: E-> (PC)

AOJLE

(AC)—1->(AO

E~(PO)

(AC)—-1-(AO)

E - (PC)
SOJGE

If (AC) = 0: E~>{(PC)

*In the K110, 1 is added to or subtracted from each half separately.

365

(AC)-1->(AO)
If (AC) = 0:

E - (PC)

-165-

SYSTEM REFERENCE

ALGEBRAIC REPRESENTATION

AOJN

346

(AC) + 1~ (AC)
If (AC)# 0:

AQOJG

347

SOJN

350

366

E~- (PC)

(AC) + 1> (AC)

SOJG

367

351

(E)
+ 1> (E)

SOS

370

(E) +1—(E)

SOSL

371

If (B)<0: skip

(E) + 1~ (E)

If AC#0:

SOSE

372

(E)— (AC)

353

If (E) = 0: skip

(E) + 1~ (E)

SOSLE

373

If AC+#0: (E)~ (AC)

354

If (B)<0: skip

E)+1->(E)

SOSA

374

If AC#0: (E)=>(AC)

355

356

(E) + 1> (E)

SOSGE

375

357

If (E) =2 0: skip

(B)+1—-(E)

SOSN

If AC#0: (E) =~ (AO)

-376

If (BE) #0: skip

SOSG

If AC#0: (E)-> (AO)

377

(E) - 1->(E)

If AC#0: (E) > (AO)

If (E) > 0: skip

If (E)>0: skip

Logical Testing and Modification

TLN

601

No-op

TLNE

603

If (AC)y

TLNA

605

Skip

TLNN

607

If (AC)y,

TLZ

621

(AC)

TLZE

623

If (AC)y,

ANE =0: skip

AE #0: skip
A~E - (ACQ),

AE = 0: skip

TRN

600

No-op

TRNE

602

If (AC)x

TRNA

604

Skip

TRNN

606

If (ACOr

TRZ

620

(AC)g A ~ E - (AC)g

TRZE

622

If (AC)x AE = 0: skip

A~ E~- (AC),

TLZA

625

(AC),A~E->(AC),

TLZN

627

If (ACy,

(AC),

(E) - 1->(B)

If AC#0: (E) - (AC)

(E) + 1= (E)

(AC)

(E)
- 1 (E)

If AC+#0: (E)—> (AO)

If (E)>= 0: skip

If (E) #0: skip
AOSG

(E)~ (AQ)

Skip

If AC#0: (E)— (AO)
AOSN

(E) = 1> (E)

If AC#0:

Skip
AOSGE

(E) — 1> (E)

If AC#0: (E)—> (AC)

If(B)<0: skip
AOSA

(E) — 1> (E)

If AC#0: (E)—>(AO)

If (E) =0: skip

AOSLE

(E) — 1->(E)

If AC # 0: (E)~ (AC)

If (E) <0: skip

352

(E) — 1->(E)

If AC#
0: (E)~ (AC)

If AC+#0: (E) > (AC)

AOSE

(AC) - 1 (AC)

If (AC)>0: E— (PC)

If (AC)#0: (E) ~» (AC)

AOSL

(AC) - 1~ (AC)

If (AC) #0: E— (PC)

If (AC)>0: E— (PC)

AOS

Al9

AE #0: skip

A~ E~>(AC),

AE =0: skip

AE #0: skip

(AC)g A ~ E > (AC)x

skip

TRZA

624

(AC)r A ~ E = (AC)x

TRZN

626

If (AC)x

AE #0: skip

(AC)x A~ E - (AC)g

skip

-166-

SYSTEM REFERENCE

A20

MNEMONICS

TLC

641

(AC), ¥ E— (AC),

TRC

640

TLCE

643

If (AC)L

TRCE

642

AE = 0: skip

(AC), ¥ E - (AC),
TLCA

645

TLCN

647

(AC), ¥ E~ (AC),

If (AC),

|
skip

AE #0: skip

|
TRCA

644

TRCN

646

(AC), ¥ E > (AC),

(AC)r ¥ E—> (AC)R

If (AC)x AE = 0: skip
(AC)g ¥ E = (AC)
If (AC)r N E #0: skip
(AC)r ¥ E = (AC)

TLO

661

(AC), V E - (AC),

TRO

660

(ACR V E~> (AC)k

TLOE

663

If(AC),

TROE

662

If (ACOr

AE=0: skip

(AC), V E~ (AC),

TLOA

- 665

(AC)LVE~(AC),

TLON

667

If (AC),

skip

AE#0: skip

AE =0: skip

(AC)r VE— (AC)

TROA

664

(AC)r VE - (AC)

TRON

666

If (AC)g

(AC). V E—= (AC),

skip

AE#0: skip

(AC)g VE— (AC)

TDN

610

No-op

TSN

611

No-op

TDNE

612

If (AC)A (E) = 0: skip.

TSNE

613

If (AC) A (E)g= 0: skip

TDNA

614

Skip

TSNA

615

Skip

TDNN

616

If (AC)
A (E) #0: skip

TSNN

617

If (AC)A (E)s # 0: skip

TDZ

630

(AC) A ~ (E) = (AC)

TSZ

631

TDZE

(AC) A~ (E)s > (AC)

632

If (AC) A (E) = 0: skip

TSZE

633

If (AC) A (E)s= 0: skip

(AC)A ~ (E) = (AC)

:
TSZA

635

(AC) A~ (E)s— (AC)

TSZN

637

If (AC)A (E)s #0: skip

TDZA

634

(AC)A~ (E)~> (AC)

TDZN

636

If (AC)
A (E) # 0: skip

skip

(AC)A~ (E)s—> (AC)

(AC)A ~ (E) ~ (AC)

skip

(AC)A i‘(E)S - (AC)

TDC

650

(AC) ¥ (E) > (AC)

TSC

651

TDCE

652

If (AC)A (E) = 0: skip

(AC) ¥ (E)s~ (AC)

TSCE

653

If (AC)
A (E)s = 0: skip

(AC) ¥ (E) = (AC)
TDCA

- 654

TDCN

656

(AC)¥ (E)=> (AC)

skip

If (AC)
A (E) #0: skip

TSCA

655

(AC)¥ (E)s > (AC)

TSCN

657

If (AC)A (E)s
# 0: skip

(AC) ¥ (E) > (AC)

TDO

(AC) ¥ (E)s~> (AC)
skip

(AC) ¥ (E)s > (AC)

670

(AC)V (E) = (AC)

TSO

671

(AQ) v (E)s > (AC)

672

If (AC)A (E) = 0: skip

TSOE

673

If (AC)A (E)s = 0: skip

TDOA

674

(AC)V (E) > (AC)

TDON

676

If (AC)A (E) #0: skip

TDOE

(AC)v (E) = (AC)

(AQ) Vv (E) > (AO)

(AC) v (E)s ~ (AC)
skip

TSOA

675

(AC)V (E)s— (AC)

TSON

677

If (AC)A (E)g #0: skip

(AQC)V (E)s = (ACQ)

skip

-167-

SYSTEM REFERENCE

APPENDIX B

INPUT-OUTPUT CODES

The table beginning on the next page lists the complete teletype code. The
lower case character set (codes 140~176) is not available on the Model 35,
but giving one of these codes causes the teletype to print the corresponding

upper case character.
tioned in the table.

Other differences between the 35 and 37 are men-

The definitions of the control codes are those given by

ASCII. Most control codes, however, have no effect on the console teletype,

and the definitions bear no necessary relation to the use of the codesin con-

junction with the DECsystem~10 software.

The line printer has the same codes and characters as the teletype. The
64-character printer has the figure and upper case sets, codes 040-137
(again, giving a lower case code prints the upper case character), The “96”character printer has these plus the lower case set, codes 040-176. The

sending its code prefixed by the delete code. Hence a character hidden under
DELis printed by sending the printer two 177sin a row.
Besides printing characters, the line printer responds to ten control characters, HT, CR, LF, VT, FF, DLE and DC1-4. The 128-character printer uses

the entire set of 7-bit codes for printable characters, with characters hidden
under the ten control characters that affect the printer and also under null .

and delete.

printed.

In all cases, prefixing DEL causes the hidden character to be

The extra thirty-three characters that complete the set are ordered

special for each installation.

The first page of the table of card codes [pages B6—-8] lists the column
punch required to represent any character in the two DEC codes. The octal
codes listed are those used by the DECsystem—10 software. In other words,
when reading cards, the Monitor translates the column punch into the octal

code shown; when punching cards, it produces the listed column punch when
given the corresponding code. The remaining pages of the table show the

relationship between the DEC card codes and several IBM card punches.
Each of the column punches is produced by a single key on any punch for

which a character is listed, the character being that which is printed at the

top of the card.

latter printer actually has only ninety-five characters unless a special character is “hidden” under the delete code, 177. A hidden characteris printed by

-163-

SYSTEM REFERENCE

INPUT-OUTPUT CODES

Even

7-Bit

Parity

Octal
Code

Character

000

NUL

Null, tape feed. Repeats on Model 37. Control shift P on Model 35.

001

SOH

Start of heading; also SOM, start of message. Control A.

002

STX

Start of text; also EOA, end of address. Control B.

003

ETX

End of text; also EOM, end of message. Control C.

004

EOT

End of transmission (END); shuts off TWX machines. Control D.

©Q

TELETYPE CODE

005

ENQ

Enquiry (ENQRY); also WRU, “Who are you?”

Bit

Remarks

Triggers identification

(“Here is . . . ”’) at remote station if so equipped. Control E.
006

ACK

Acknowledge; also RU, “Are you ... ?” Control F.

007

BEL

Rings the bell. Control G.

010

Backspace;

also

FEO,

‘

format

effector.

Backspaces some machines.

011

Horizontal tab. Control I on Model 35.

012

Line feed or line space (NEW LINE); advances paper to next line. Repeats .

e m= O =

Repeats on Model 37. Control H on Model 35.

013

Vertical tab (VTAB). Control K on Model 35.

014

Form feed to top of next page (PAGE). Control L.

on Model 37. Duplicated by control J on Model 35.

Carriage return to beginning of line. Control M on Model 35.

Shift out; changes ribbon color to red. Control N.

017

Shift in; changes ribbon color to black. Control O.

C O m

015
0l6

020

DLE

Data link escape. Control P (DCO).

021

DC1

Device control 1, turns transmitter (reader) on. Control Q (X ON).

022

DC2

Device control 2,

turns punch or auxiliary on.

AUX ON).

023

DC3

024

DC4

Control R (TAPE,

‘

Device control 3, turns transmitter (reader) off. Control S (X OFF).

Device control 4, turns punch or auxiliary off.
. AUX OFF).

Control T (FARE,

025

NAK

Negative acknowledge; also ERR, error.

026

SYN

Synchronous idle (SYNC).

Controi U.

O O

027

ETB

End of transmission block; also LEM, logical end of medium. Control W.

030

CAN

Cancel (CANCL). Control X.

Control V.

031

End of medium. Control Y.

O =

032

SUB

Substitute. Control Z.

033

ESC

Escape, prefix.

This code is generated by control shift K on Model 35,

[ary

but the Monitor translates it to 175.
034

File separator. Control shift L on Model 35.

035

Group separator. Control shift M on Model 35.

-169-

SYSTEM REFERENCE

TELETYPE CODE

Even
Parity

Remarks

=00~ 0O=,00~==O0

Character

036

Record separator. Control shiftN on Model 35.

037

Unit separator. Control shift O on Model 35.

040

Space.

041

042

043

044

045

y/2

046

047

’

050

(

051

)

Bit

7-Bit
Octal
Code

052

Accent acute or apostrophe.

055

Repeats on Model 37.

056

Repeats on Model 37.

060

064

066

070

071

067

073

072

074

065

063

Repeats on Model 37.

075

077

076

101

100

102

@ > @ 0V

MmO

062

061

057

053
054

=00

Repeats on Model 37.

INPUT-OUTPUT CODES

104

107

105
106

110

123

=00

122

125

124

126
127
130
131
132

134

133

135

Repeats on Model 37.

Shift K on Model 35.
Shift L. on Model 35.
Shift M on Model 35.

Repeats on Model 37.

140

Accent grave.

144

145

146

147

143

—_

142

141

137

136

I OTOZZN

120
121

XE<OA-H

116
117

==~ 0—~ 00

115

114

=
—0

113

=00

‘

111
112

Character

TZQTEgO

103

7-Bit

Octal
Code

=00

Even

Parity
Bit

~170-

SYSTEM REFERENCE

Remarks

~171-

SYSTEM REFERENCE

TELETYPE CODE

Even

7-Bit

Parity

Octal

Bit

Code

150

Character

Remarks

151

152

153

154

155

156

157

160

161

162

163

164

165

166

167

170

171

Repeats on Model 37.

172

173

{

174

175

}

This code generated by ALT MODE on Model 35.

176

This code generated

by ESC key (if present) on Model 35, but the

Monitor translates it to 175.
1

177

DEL

Delete, rub out. Repeats on Model 37.

Keys That Generate No Codes
REPT

Model 35 only: causes any other key that is struck to repeat continuously
until REPT is released.

PAPER ADVANCE

Model 37 local line feed.

LOCAL RETURN

Model 37 local carriage return.

LOCLF

Model 35 local line feed.

LOCCR

Model 35 local carriage return.

INTERRUPT, BREAK

Opens the line (machine sends a continuous string of null characters).

PROCEED, BRK RLS

Break release (not applicable).

HERE IS

Transmits predetermined 2 1-character message.

-172-

SYSTEM REFERENCE

INPUT-OUTPUT CODES
CARD CODES
PDP-10

ASCII

DEC 029

Space

040

None

100

041

11 82

1287

101

12 1

12
1

042

085

102

12 2

12
2

#
$

043
044

8 3
1183

086
1183

C
D

103
104

12 3
12 4

12
3
12
4

12 5

125
12
6

DEC 026

Character

PDP-10

Character

ASCII

DEC 029

DEC 026
84

045

084

087

105

046

1187

106

12 6

047

107

12 7

(

050

1285

084

110

12 8

12
8

)

051

1185

1284

111

129

129
111

12
7

052

11 8 4

]

112

111

053

1286

113

112

054

083

114

113

055

i
/

056
057

1283
01

1283

115

11 4

11
4

117

116

060

120

117

11 6

061

121

11 8

062

122

119

063

123

064

124

065

125

066

126

116

115

117

118

067

127

070

130

071

131

072

11820r110

132

[
\

133
134

1282
1187

1185
87

073

074

1186
128 4

082
1286

075

8 3

]

076

086

1186

135
136

082
1287

1285
85

077

087

12820r120

137

085

Binary

Mode Switch

1202468

End of File

121101,6789,1211016789

The octal codes given above are those generated by the Monitor from the column punches. The card
reader interface actually supplies a direct binary equivalent of the column punch, as listed in the following
two pages.
The first end-of-file punch is not recognized by Card Reader Stacker (CDRSTK); the other two are
recognized only by Card Reader Stacker.

173~

SYSTEM REFERENCE

CARD CODES

Column

Punch

None

Character

Octal

Column

Punch

Character

Octal

Space

0000

129

4001

1000

111

2400

0400

112

2200

0200

113

2100

0100

11 4

2040

0040

115

2020

0020

116

2010

0010

117

2004

0004

11 8

2002

0002

119

2001
1400

0001

12 1

4400

1200

12 2

4200

1100

12 3

4100

1040

12 4

4040

1020

125

4020

1010

12 6

4010

1004

12 7

4004

1002 -

12 8

4002

1001

Column
Punch

026 Data

Processing

026

Fortran

029

DEC 026

DEC 029

~ Octal

4000

2000

120

110

5000

3000

0202

0102

0042

)

0022

’

0012

0006

4202

12 8 2

[

1283

128 4

)

1285

(

1286

4102
'

4042
4022

4012

SYSTEM REFERENCE

~174-

INPUT-OUTPUT CODES

Column

026 Data

026

Punch

Processing

Fortran

029

DEC 026

DEC 029

Octal

128
7

4006

11
8 2

2202

1183
118 4

2102

2042

)

[

)

$ 2022

;

2012

2006

;

]

1202

1185
1186

11 87

082

083

See note

’

084

1102

(

085

.(—

086

(

1042
1022

1012

1006

121101

End of File*

7400

1202468

Mode Switch

5252

Binary

xx05

6789

End of Filet

End of Filef

1211016789

End of Filet

087

NorTE: There isa single key for the O 8 2 punch on the 029 but printing is suppressed.

The Monitor translates the octal code for the 12 0 punch in DEC 026 to 4202 (which corresponds to a

12 8 2 punch), and the code for 11 0 to 2202 (11 8 2).
*Not recognized as end of file by Card Reader Stacker (CDRSTK).

T Recognized only by Card Reader Stacker (CDRSTK).

’

SYSTEM REFERENCE

-175-

APPENDIX C
TIMING

The chart on the next two pages shows the detailed timing for the KA10. A

similar chart for the KI10 and timing tables for both processors will be
added later.
‘

SYSTEM REFERENCE

fl76-"

TIMING

DATA FETCH

l STARY '
.

READ

FLOATING POINT

MEMORY OPERAND

A7+ R 1)

IMMEDIATE

READ /MODIFY

OTHER IMMEDIATES
MEMORY OPERAND

®1F IN USER MODE

MEMORY READ

A CCESS

(CHART 1)

T+ R
*1F 1IN USER MODE

‘ INSTRUCTION
FETCH

26+ %)

%*1F 1IN USER MODS, -

J
MEMORY

ACCESS

READ
(CHART 1)

CALCULATE
lNl;EX

NO __~ ACCUMULATOR
REQUIRED

YES

FAST

REGISTERS
?

r MEMORY READ
ACCESS

(CHART 1)

, ADDRESS

‘

CALCULATION

MEMORY

ACCESS

READ

(CHART )

yjl

[ NONE OF THESE
-

c——

INDIRECT

e ?SET

FAST

REGISTERS
?

)
.28

KA10

INSTRUCTION TIMIN

FLOW CHART

MEMORY READ

ACCESS

(CHART 1)

INSTRUCTIONS THAT USE READ/MODIFY
All-Boolean in Memory and Both modes except SETZ, SETA, SETCA, SETO
ADDM, ADDB, SUBM, suBs

HRRM, HRLM, HLRM, HLLM and all haif words in Self mode
MOVES, MOVNS, MOVMS, MOVSS
ILDB, 1DPB {(first time only)}

IBP, BLKI, BLKO, DFN, EXCH
AQS, SOS in all modes

*1F N USER MODE

SYSTEM REFERENCE

-177-

KA10 TIMING

INSTRUCTION EXECUTION

DATA STORE

Half Words {except HLR, HLRI, HRL, HRLI), MOVE,

MOVS, EXCH, JFCL, JRST, JSP, XCT, UUO

STORE

{ ACCUMULATOR
?

Buolean (except ANDCA, ANDCB, ORCA. ORCB).

ANDCA ANDCB. ORCA, ORCB, HLR, HLRI,
HRL, HRLI, JSR, JSA, JRA, Test class

FAST

MOVN, MOVM, ADD, SUB, AOBJP, AOBJN,
CAM, CAI, SKIP, JUMP, AQJ, ADS, SOJ, SOS

REGISTERS

PUSH, PUSHJ, POP. POPJ, DFN

.80

JFFO

¢ .19 times number of leading Os mod 18

BLT

(+ .11. User) + memory write access ¢ .52

IBP

+ 261t overflow word houndary
+ .15 per size count

125K

It not done + 09 and go to C3

LOB, DPB

First time

ILDB. tOPB

First time

14 { + .26 1f overtlow

iILOB, LDB

Second time

+ 15 per position count

Second time

+ 15 per position count

.39 Lett }

{.23 Right

Shift group

:MUL

6.02
8.36

Average except MULI

IMUL
Average except IMULI

FMP
Average except FMPRI
Note:

Goto C1

+ .15 per size count }

0P8, DPB

MEMORY WRITE

Goto L1

1)
ACCESS. (CHART

.15 per shift
.

+.13 per transition

(18 transitions for 2.34)

6.34

+ .13 per transition

1.51

{9 transitions for 1.17)

6.39

+ 13 per transttion

8.21

(14 transitions for 1.82)

[

MEMORY
RESULT

] 1

READ/MODIFY
c

FSC

152

+ 2% per shift to normalize

218

{ + ;2 per shift to unnm.n?ahze

413

Averdge

+ .25

per shift to normdluze

FSB

Same as FAD + .18

Rounding (ex:’ep!_dwvde) only when a'cmally done

+.96

_ Long mode (except dwide)

12.00:

FOVL with fast ACs

13.28

FOVL without fast ACs

12.32

CONO, CONI, CONSO, CONSZ, DATAQ, DATAI
CONO, CONI, DATAQ, DATAI
'

+2.69

CONSO, CONSZ

TIMING CHART
FOR CYCLE
COMPLETION TIME

{+ .11.4f User) + memory read access + .89
Then wait until 4.50 has passed since fast here

.60

Then turn into DATAQ, IjATAl and go to C2

MEMORY TIMING
MEMORY
.

MA10
SINGLE

MB10

FAST

MD10

ME 10

SINGLE

| SINGLE

CYCLE

1.00

165

1.7%

—

1.8

1.00

READ ACCESS -

.60

.70

.21

.83

.61

WRITE ACCESS

.21

.33

.20

PROCESSORS

|op myLti|

MEMORY WRITE

+2.90

BLKO, BLKI

SINGLE | MULT! 1 g7T in) OR MULTI|OR MULTI

T+ R
% iF IN USER MODE

MEMORY WRITE

ACCESS

(CHART 1)

MODIFY

NOTES.

MEMORY ACCESS TIMES INCLUDE DELAY
INTRODUCED BY 10 FEET OF CABLE

ALL TIMES ARE NOMINAL MAXIMUMS

MEMORY

ACCESS

SEE MEMORY

0.8.9

FOVR, FOV (except FOVL)

RESULT

% IF IN USER MODE

13.78

" FAD. UFA

]

7+ *t)

lmmediate mode multiphcation bas only half the average number of transitions

DIV, 101V

—n

* i IN USER MODE

‘

DONE

,(CHART 1)

]

~179-

SYSTEM REFERENCE

APPENDIX D

KA10 ALGORITHMS

All arithmetic operations on full and half words are performed in the 36-bit
parallel adder.

This appendix treats only the

There are two sets of summand inputs to the adder, each set

algorithms used in the KA10;

of AR, its complement, or zero; the other set supplies the contents of BR, its

algorithms refer to the main-

of 36 supplying one input to each adder stage. One set supplies the contents
complement, or zero.

Each stage also has a carry input, which is generated

by the next less significant stage.

Every stage has two outputs; the carry

already mentioned, and a sum. The 36 sum outputs together form the sum
of the two input words. The least significant stage has a carry input from the

logic for performing twos complement arithmetic and incrementing by one.
The negative of a number is formed at the sum outputs simply by supplying

the complement of the number at one set of inputs and asserting the carry

into stage 35.

Adder stage 17 has extra input gating so that 1 can be added
to or subtracted from both halves of AR simultaneously.
The adder produces a sum in the same way that one adds binary numbers
using pencil and paper. Each adder stage has three inputs, two summand bits

and a carry, and two outputs, sum and carry. The sum output of a given
stage is 1 if any one or all three of the inputs are 1. The carry out is 1 if two

or three of the inputs are 1. Calculations are performed as though the words
represented 36-bit unsigned numbers, ie the signs are treated just like magni-

tude bits. In the absence of a carry into the sign stage, adding two numbers
with the same sign produces a plus sign in the result. The presence of a carry
gives a positive answer when the summands have different signs. The result

has a minus sign when there is a carry into the sign bit and the summands
have the same sign, or the summands have different signs and there is no
carry.

Thus the program can interpret the numbers processed in fixed point

arithmetic as signed numbers with 35 magnitude bits or as unsigned 36-bit

numbers.

A computation on signed numbers produces a result which is

correct as an unsigned 36-bit number even if overflow occurs, but the hard-

ware interprets the result as a signed number to detect overflow. Adding
two positive numbers whose sum is greater than or equal to 235 gives a nega-

tive result, indicating overflow; but that result, which has a 1 in the sign bit,

is the correct answer interpreted as a 36-bit unsigned number in positive
form. Similarly adding two negatives gives a result which is always correct
as an unsigned number in negative form.

All operations discussed below have two operands, one of which is
supplied to the adder from BR, which acts simply as a buffer and has no
special input gating. MQ has shift gating so it can function as a low order
extension of AR for handling double length operands. All actual computations take place in the single 36-bit adder, but the sum output can be placed

in either AR or MQ, and all transfers to MQ from AR or BR are made

through the adder.

In multiplication MQ holds the multiplier and thus
D1

for information on the KI10
tenance manual.

SYSTEM REFERENCE

-180-

ALGORITHMS

controls the summation of partial products; as the multiplier is shifted out,

the low order word of the product is shifted in. In division MQ supplies the
low order part of the dividend to AR as the quotient is being constructed in

MQ.
In any extended arithmetic operation, the requisite number of steps is

counted in the 9-bit shift counter SC, which has a carry network for this
purpose.

SC also has a 9-bit adder for use in computations on floating point

exponents and size and position calculations in byte manipulation.

FIXED POINT ALGORITHMS

Fixed point numbers are explained in detail in §1.1. For convenience let us

take the computer representation of the positive number x as +[x] where
the brackets enclose the number in bits 1-35.

Similarly the representation

of —x is =[23% —x] or —[1 —x] depending on whether we are regarding numbers as integers or as proper fractions. The most negative number, —235, has
the form —[0], which is equivalent to the unsigned integer 2%°.
Addition. There are four cases of addition of two positive 35-bit numbers

xand y.
L

x+y

IL.

(=x)+ (=)

I11.

x+ (),

xX=y

IV.

x+(y),

x <y

The operands are held in AR and BR, but it makes no difference which one

is in which register.

The result appears in AR.

For convenience in the

exposition we shall regard the numbers as proper fractions; to view them as

integers, simply substitute ‘235 for each occurrence of “1”. Since the twos
complement format allows a representation for
— 1 either x or y may be 1 in
II, and y may be 1 in IV.

‘

I. If x+y <1 the adder output placed in ARis +[x+y].

the carry out of stage 1 changes the sign.

If x+y>1

Consequently if the addition of

two positive numbers gives a negative result, it is apparent that the sum
exceeds the capacity of the register.

The processor detects the overflow by

checking the sign carries: there is a carry into the sign stage but none out of*
it. AR then contains

—[x+y—1]
II. Ignoring the carry into the sign b1t in the addition of two negatives

would give

—[1—x]
= [1-=y]
+[1+1-x-y]

If x + y

<1 the carry changes the sign and the resultis

-181-

SYSTEM REFERENCE

FIXED POINT

~[1-x-y]
which is the representation of —(x + y).

x+y>1 there is no carry into

the sign, and its absence in the presence of a carry out indicates overflow.

AR contains

+[l-(x+y—-1)]
,

II. Ignoring the carry into the sign in an addition where the signs
are

different would give

+ [x]
—[1-y]
—[1+x—-y]

Since x =y, it follows that 1 +x — ¥ 2 1. Hence the carry changes the sign

and the result is

+[x —y]
When the operand signs are different, the magnitude of the result cannot
exceed the larger operand magnitude and there can be no overflow.
Since

in this case the positive number is at least as large in magnitude as the
negative, there is always a carry into the sign, and this added to the operand

minus sign produces a carry out.

IV. The addition of numbers of differing signs where the negative has the

" larger magnitude gives

+ [x]
= [1-y]
=1
+x -yl
Since x <y, then 1 +x —y <1. Hence there are no carries associated with
the sign and no overflow The above result is the twos complement represen-

tationof x

—y, ie —(y
—

Subtraction. The mlnuend from AC is in AR, and the subtrahend, which

is either 0,E or the word from location E, is in BR. Subtraction is done
directly by adding the twos complement of BR to AR. The logic supplies

the complement of BR to the adder and a carry into the adder LSB.

Let x be the absolute value of the numberin AR, and y the absolute value
of the number in BR. There are four cases.

These

x=(-y)

I1.

(—x)—y

x-y,

x=y;

(—x)-(»),

x<y

IV.

Xy,

x<y;

=x)—=(-y),

x>y

correspond

previously.

respectively

to the

four cases of addition

discussed

Multiplication. The multiplier, 0,
F or the contents of location E, is in
MQ, and the multiplicand from AC is in BR. AR is clear. The 36-step
procedure is as follows.

SYSTEM REFERENCE

- -182ALGORITHMS

If MQ35 (the multiplier LSB) is 1, subtract BR algebraically from AR, but
put the result in AR shifted one place to the right, with the LSB of the result
going into MQO, and shift MQ right so a bit of the multiplier is dropped from
MQ35. Put the sign of the result in ARO and ARI1 (as though the shift
followed the subtraction and did not affect the sign but did move it to
ARI1). If MQ35 is O, 81mply shift AR and MQ right one, with AR35 gomg
into MQO.

In each subsequent step perform only the shift if the bits moved in and
out of MQ35 on the previous step were the same. If they were different, add
or subtract along with the shift: if the shift moved a 0 in and a 1 out, add
BR to AR;ifa 1 in and a O out, subtract BR from AR.
- Thus the low order bits of the running sum of partial products are shifted
into. MQ as the multlpheris shifted out. At each step the effect of the multiplicand in BR on the partial sum in AR is one bmary order of magnitude
greater than' in the precedmg step because the partial sum was shifted right.
Therefore BR can be combined directly with AR. If MQ35 is initially O,
there is no subtraction until a 1 is shifted into it. Simple shifting then
contmues until, the next transition (from 1 to 0), following whrch BR is
added..

The process continues in thls way, subtracting at every 0-1 transition,
adding at every 1-O transition. After 35 steps MQO-34 contains the low
half of the product magnltude and MQ35 contains the sign of the multiplier.
At the final step, add or subtract as required but put the result directly into
AR; shift only MQ to move the low magnitude into the correct position and
make MQO equal to the sign of the whole product.
If the original operands wereboth negative and the resultis also negative,
set Overflow: this can occur only when —235is squared. In IMUL, if the high

word is not null (ie if ARis neither clear nor all 1s), set Overflow move MQ
to AR for storage of the low word.

To see that this procedure results in a correct product, consider the posi-

tive bmary mteger
100111011
876543210

where the decimal digits below the bmary dlglts are the powers of 2 correspondmg to the blt positions. This numberis obviously equal to
100000000
+

111000

Now an n-bit string of 1s whose rightmost bit corresponds to 2%is equal to
2k*+n_ 2k or equivalently 2%(2” — 29), je 2"— 2°is a string of n 1s and the 2¥
shifts the strmg left k places. Hence

100000000
111000
|
11

100111011

=
=
=

2%1-28 =
23*3-23 =
2240-20 =

29_28,

26-23
22-20

29-28426-23422-20

In this last representation, each power of 2 that is subtracted corresponds to

-133-

SYSTEM REFERENCE

FIXED POINT

a transition from 0 to 1 (scanning right to left), whereas each
that is added

corresponds to a 1-0 transition.

The largest term corresponds to the transi-

tion to the sign bit, which is O for a positive number.

The multiplication

algorithm interprets the multiplier in this manner, alternately subtractin
g
and adding the multiplicand to the partial sum in the order-of-m
agnitude
positions corresponding to the transitions. If a multiplier of the same
magni-

tude were negative, it would have the form

1011000101
—

876543210

in which the extra bit at the left represents the sign.
equivalent to

The number is now

2942826423 -92421-20
wherein opposite signs correspond to opposite transitions.

The algorithm

may thus use exactly the same sequence for a negative multiplier

: this time

the subtraction of greatest magnitude is detected by the ‘transition to
sign bit, which is now 1.

the

Division. The divisor, 0,
E or the contents of location E, is in BR. In
DIV the high and low halves of the dividend from two accumulators
are in
AR and MQ respectively. In IDIV the one-word dividend from
AC is in AR.
The two types of division differ mainly in setting up the dividend;
in both
cases the algorithm processes a positive dividend to get a positive quotient.

In DIV if the dividend is negative (ARO = 1), make it positive and set the

negative dividend flag. To negate the dividend, move the low word
to AR

and the complement of the high word to MQ. Then move the negative
of
the low word back to MQ and the complement of the high word
back to AR.

Now the double length negative of the original dividend is in AR and

unless MQ is clear; in this event add 1 to AR to give the twos complemen
t
negative of the high word. Once the dividend is in positive form
shift MQ

left one place to close the hole between the two halves; in other
words drop
the low sign and get the 70-bit magnitude into AR1 -35, MQO-34.
If the IDIV dividend in AR is negative, negate it and set the
negative
Move the one word dividend in positive form to MQ and clear

dividend flag.

AR. Shift MQ left, as the algorithm operates on a double length
dividend in
both types of division although the high part is null in this case.

After the dividend is set up, compare the divisor with it to determine

whether the division can be performed.

Subtract the absolute value of the

divisor from the high half of the dividend (if the divisor is positive, subtract

it; if negative, add it).

Since the dividend is positive, the result is also
positive if the magnitude of the divisor is less than or equal to the
number in
AR. For a fixed fraction, the divisor is subtracted from the actual
dividend

and no overflow is allowed.

For a fixed integer, AR is clear and the result is
positive only for a zero divisor; the worst possible case is
the division of

2% —1 by 1, whose integral result can be accommodated.

(Placing the one

word dividend in MQ effectively multiplies it by 273, making
it the fractional part of a two word dividend with the binary point in
the middle. The
quotient is then a proper fraction, which is multiplied by 235
simply by
interpreting it as an integer.) Thus if the result of this initial
subtraction is

I)SGYSTEM REFERENCE

-134ALGORITHMS

positive, set Overflow and No Divide, and terminate the procedure so the

processor goes on to the next instruction.

Dividing by zero is of course

meaningless. The reason for prohibiting a fractional division where the result
would be greater than 1 is that it is impossible to determine the position of
the binary point in the quotient.

So it is up to the programmer to shift the

dividend to the correct position beforehand.

If the result of the initial sub-

traction is negative, the division can be performed and the processor goes

into the division loop.

In division on paper, one subtracts out the divisor the number of times it
goes into the dividend, then shifts the dividend one place to the left (or the
divisor to the right) and again subtracts out. In binary computations the
divisor goes into the dividend either once or not at all. Each subtraction of
the divisor thus generates a single bit of the quotient.

If the subtraction

leaves a positive difference, ie if the dividend is larger than the divisor, a 1 is
entered into the quotient.

If the difference is negative, a O is entered.

compensate for subtracting too much, the hardware could add the divisor

back into the dividend before going to the next subtraction step. But the
PDP-10 algorithm instead shifts first and adds the divisor back in at the new
position.

It then continues to shift and add putting Os into the quotient

until the result again becomes positive.

This procedure generates the same

quotient without ever going back a step.

The hardware procedure is as follows.

As each addition or subtraction is

formed in the adder, put the result in AR shifted one place to the left with
AR35 receiving a new bit of the dividend from MQO, and shift MQ left
bringing in a bit of the quotient at MQ35. The bit brought in is the comple-

ment of the sign from the adder: if the divisor does not go into the dividend,
the resulting minus sign (1) produces a 0 quotient bit; if the divisor does go
in, the plus sign gives a 1. Each step loads one bit of the quotient into MQ33,
and the low half of the dividend is shifted out of MQ as the quotient is
shiftedin.

The first step is the test subtraction. In each subsequent step, subtract
the absolute value of the divisor if the quotient bit generated in the previous
step is 1, but add it back in if the quotient bit is 0. Since the divisor may
have either sign, subtract it algebraically if its sign differs from the quotient
bit, add it if its sign is the same.

The hardware executes 36 steps to generate 35 magnitude bits. The initial
test step must give a 0, which serves as the sign since we are producing a
positive quotient. In the final step put the result of the addition or subtraction directly in AR without shifting so the remainder is in the correct
position, but shift MQ left putting the sign from the first step in-MQO and
bringing in the last quotient bit. (The bit dropped out of MQO is superfluous;
it was brought into MQ35 when the hole was closed between the dividend
halves.)

To complete the division we must make sure the remainder is correct and

determine the correct signs of the results.

Since the operations were per-

formed on positive operands, the remainder should also be positive.

negative remainder indicates that too much has been subtracted. To correct

this add the absolute value of the divisor back in. If the negative dividend
flag is set, negate AR so the remainder has the sign of the original dividend.

SYSTEM REFERENCE
D7

FLOATING POINT

Now move the corrected remainder to MQ and move the quotient to AR.
If the negative dividend flag and the divisor sign are of opposite states,
negate AR to produce the correct quotient sign.

The correct quotient and

remainder are now in AR and MQ ready for storage.

As an example of the way this algorithm operates, consider a division of

3-bit fixed fractions with a dividend of +.100100 and a divisor of +.101.
By paper computatlon we obtain the quotient this way.

A11

101[100.100
10
1
10 00
101
110

Taking the processor registers to be four bits in length, AR contains 0.100,
MQ has 0.100, and BR has 0.101. Before starting we close the hole changing
MQ to 1.000. The sequence has four steps.

0.100

1.000

—0.101
—

1.111

1 «

1.111

0.000

+0.101

0.100

2 «

1.000

0.001

—0.101
0.011

3 <«

0.110

0.011

-0.101

0.001
4

0001

<0.111

The quotient is in MQ at the right, the remainder in AR at the left.

FLOATING POINT ALGORITHMS
§1.1 explains floating point numbers and §2.6 discusses the general charac-

teristics of floating point arithmetic.

Exponent computations are done in
the SC adder using the exponents and signs from the floating point operands.
Remember, the sign is that of the whole number, not of the exponent.
Although bits 1-8 of a floating point number represent an exponent in the

range —128 to +127, the discussion is entirely in terms of the excess 128
exponents in positive form, ie the set of numbers 0-255.

Computations
generally use twos complement operations even though the exponent in a

DSSYSTEM REFERENCE

-136-

ALGORITHMS

negative number is a ones complement.

The SC sign bit is used to detect

exponent overflow and underflow.
- After exponent calculations are complete, operations on the fractions are
done by the fixed point logic in AR, BR and MQ.

Bits 1-8 of AR and BR

are filled with null bits, Os in a positive number, 1s in a negative. Double
length operands are in AR and MQ with MQ8-35 forming a magnitude

extension of AR.

In almost all circumstances the logic treats ARO-35 and

MQ8-35 as a single 64-bit register; in all two-word shifting AR3S5 is con-

nected to MQ8 and MQO-7 is ignored. Except in division the fixed point
calculation generates a double length fraction, which is shifted arithmetically
(in right shifting the sign goes into AR1; in left shifting the sign is unaffected

and Os enter MQ35).

Almost all floating point instructions normalize the

result, thus making use of the low order part even though the instruction

may store only the high order word.
Addition, Subtraction. £,0 or the word from location F is in BR, and AC

is in AR. For subtraction move the negative of the subtrahend from BR to
AR and move the minuend from AR to BR.

This reduces subtraction to

addition, so the rest of the algorithm is the same for both.
The initial objective is to determine the difference between the exponents

and to determine which exponent is the larger.

If the signs of the operands

differ, add the exponents into SC. If the signs are the same, subtract the BR
exponent from the AR exponent by adding the twos complement.

Let x

~and y be the AR and BR exponents in positive form. The table below shows
the calculations as a function of the operand signs, and the sign of the result

in SC as a function both of the operand signs and the relative values of x
and y.

AR+, BR+

AR+, BR—

AR-, BR+

AR-, BR-

+{x]
‘
—[256 ~y]

+([x]
—[255 -yl

—[255 —x]
+(y]

—[255 —x]
+[1+y]

-[256 +x —y]

—[{255+x —y]

—[255—-x+y]

—[256
—x +y]

SC+

SC-

SC+

SC-

SC+

SC-

- SC+

SC-

xz2zy

x<y

x>y

XSy

x<y

x=2y

X<y

x>y

As can be seen from the above, if AR already contains the number with the

smaller exponent, the SC and AR signs differ. Hence if the SC and AR signs
are the same, switch BR and AR so the number with the smaller exponent

can be shifted.

If the exponents are equal, the signs may or may not be the

same but it matters not whether the transfer takes placc.
To control the shifting we must now get the negative of the difference
between the exponents.

Let d be [x — y|. There are four cases as a function

of the SC sign and whether the AR and BR signs are equal.

The second

column lists the present contents of SC, the third tells what must be done to

arrive at —[256 —d] in SC.
SC+, ARO = BRO

+[d]

Negate SC

SC+, ARO # BRO

+{d—1]

- Complement SC

-187-

SYSTEM REFERENCE

FLOATING POINT

SC—, ARO = BRO

—[256 —d]

Do nothing

SC—, ARO # BRO

—[255 —d]

Add 1 to SC

If d < 64 (indicated by a negative SC with a 0 in either SC1 or SC2) nullify
AR1-8 and shift AR and MQ right d places so its bits correctly match the

BR bits in order of magnitude.

If d > 64 clear AR for its contents are of

no significance.

,
Now move the larger exponent from BR to SC in positive form, nullify
BR1-8, and add BR and AR into AR as fixed fractions. Finally enter the

normalizing sequence.

This sequence first tests for a zero result. If AR and MQ8-35 are clear,
bypass the rest of the procedure. If the fractional result has overflowed into

ARS8 (indicated by ARO # ARS8 or AR8 = 1 and AR9-35 = 0), shift right
and increase the exponent by one. The number is now normalized.

Complement the exponent in SC.

If the instruction is not UFA and the

number is not normalized go into the normalizing loop.

the

double

length

fraction

left

(decreasing its magnitude by 1).

and

add

In each step shift

the negative

exponent
Terminate the loop when the fraction is

normalized, indicated by the sign and the MSB of the fraction being different

(ARO # AR9) or the magnitude being %2 (AR9 = 1 and AR10-35 = 0).

If the instruction specifies rounding, adjust the high fraction so it is

rounded and is in twos complement form if negative. The rounding is away
from zero. For a positive result the high fraction must be increased if the

. low fraction is greater than half the value of the high fraction LSB.
In a
negative result the high fraction is a ones complement, which is one greater
in magnitude than the twos complement.

Hence it is already rounded and
should be decreased in magnitude if the low fraction is < %LSB. In either

case add 27?7 into AR if MQS8 is 1 unless MQ9-35 is clear in a negative

number.

A 1 in MQ8 indicates a low fraction > 4LSB in a positive number,

< 2LSB in a negative number.

The condition that MQ9-35 not be zero in

a negative number is the case where the low fraction is exactly 4LSB. If the

high fraction is actually changed, renormalize it. A single normalizing shift
is all that is required and it occurs in only two cases: a right shift when

1—-27?7 is rounded, a left shift when —% is changed to a correct twos

complement.

Once the number has been normalized (and rounded if necessary) the
Thus if the SC sign bit is 0, set Overflow and
Floating Overflow. If SCI is also 0, the sign bit must have been changed by
exponent is in negative form.

decreasing the exponent, so also set Floating Underflow (the maximum
possible exponent overflow is 128 giving an SC contents of 777g, and this
can occur only in division). Insert the exponent in correct form into AR1-8.

The result is now ready to store from AR unless the instruction is in long

mode.

To ready the double length result subtract 27 from the positive expo-

nent in SC.

Save the high word in MQ, and move the low word to AR, but
only if the decreased exponent is still positive. If the sign is 1, the true

exponent of the low word is less than —128, so clear AR.

(Note that this
condition is also true if the low exponent is > 127, which can occur only
if

the high exponent is > 154.) If the low word is nonzero, shift AR right
one place to put the fraction in bits 9-35 (remember that all shift operations

SYSTEM REFERENCE

-188-

D10

ALGORITHMS

use MQ8-35), clear ARO so the low word has a positive sign even if the

double length fraction is negative, and insert the low exponent in positive
formin bits 1-8.

Finally switch AR and MQ so the high and low words are

-in correct position for storage.

Scaling. The 9-bit signed scale factor from bltS 18 and 28-35 of E is in
SC, and AC is in AR and BR. If the floating point number being scaled is
positive, simply add the sign and exponent from BR0-8 to SC; if the number
is negative, add the complement of BRO-8 to SC. Let x be the exponent in
positive form and let y be the absolute value of the scale factor. There are

only two cases,

‘

+(x]
+[y]

+[x]
—[{256 —y1

+{x +y]

+[x —y]

and in either the result is in positive form in SC.
Now enter the normalizing sequence described under floating addition.
Only left shifting can occur bringing Os in from MQ. The result can be zero,
and exponent overflow or underflow can occur; but there is no rounding,

“and at the end the one-word result is in AR ready for storage.

Multiplication. E,0 or the word from location E is in BR, and AC is in

AR.

Place the AR exponent in positive form in SC, and add the positive

form of the BR exponent to it. Since both are in excess-128 code, subtract
128. Save the result in the floating exponent register FE so SC can be used
to control the multiplication of the fractions.
Nullify the exponent parts of AR and BR. Move the multiplier from BR

to MQ and the multiplicand from AR to BR. Clear AR. Now multiply the

fractions by the same procedure given for flxed point multiplication with
the following differences:
¢ There are only 28 steps instead of 36.

¢ The shift register extension of AR for the construction of the product is.
MQ8-35.

As the multiplier is shifted out, bits of the product come in

at MQS8.
¢ In the final step place the adder output directly into AR but do not shift
MQ — the low fraction is in MQ8-34, the correct position for normalization.
Clear MQ35, move the exponent back to SC, and enter the normalizing
sequence described under floating addition. If the operands are normalized,
at most one left shiftis needed to normalize the result.

Division. The divisor, E ,0 or the contents of location E, is in BR. The

dividend from AC is in AR. In long mode the low half of the dividend from
the second accumulator is in MQ; otherwise MQis clear.
If the dividend is negative, make it positive and set the negatlve dividend

flag. Except in long mode, negate the dividend simply by negating AR. For
long mode follow the procedure given for DIV in the second paragraph of
the fixed division algorithm. With a floating point operand the left MQ shift
puts the low fractionin MQ8-34.

Place the AR exponent in positive formin SC. Subtract the magnitude of

the BR exponent from it by adding the negative form of the exponent (ones
complement) plus 1. Since the excess-128 factors cancel in the subtraction,

add 128.

Save the result in the floating exponent register FE so SC can be

-189-

SYSTEM REFERENCE

FLOATING POINT

used to control the division of the fractions.

Nullify the exponent parts of AR and BR. Subtract the absolute value of
the divisor from the high half of the dividend. If the. result is positive,
indicating the divisor is less than or equal to the dividend, shift AR and MQ

right and increase the exponent in SC by 1. Save the adjusted exponent in
FE. The shift divides by 2, so if the operands are normalized, the dividend
must now be less than the divisor.

:
4
Now divide the fractions by the same procedure given for fixed point

fractional division with the following differences:

¢ Since the dividend has already been adjusted, the test in the first step
stops the division only if the divisor is zero, or is unnormalized and less than

the dividend. A normalized divisor cannot cause the quotient to overflow.
If the result of the initial subtraction is positive, terminate the procedure
and set Floating Overflow as well as Overflow and No Divide.

¢ Instead of 36 steps there are only 29 if the instruction specifies rounding,
otherwise 28.

¢ The shift register extension of AR is MQ8-35.
As quotient bits are
brought in at MQ3S5, dividend bits are supplied to AR35 from MQ8.
The

shifting clears MQO~7.

¢ The MQ shift in the final step places a 27-bit quotient fraction in MQ9-35

or a 28-bit fraction in MQ8-35.
'
¢ As in the fixed point algorithm generate the correct signed remainder,
put
it in MQ, and move the quotient to AR but leave it positive.

If the instruction specifies rounding, shift AR right placing the 27-bit
fraction in the correct position, and if the bit shifted out of AR35 is 1, add

it back into AR35 to round the positive quotient. If the quotient is zero
bypass the rest of the procedure. The reaminder will also be zero except
in

an FDVL where the double length dividend is unnormalized and its high

fraction is zero.

Complement the exponent in SC.

If the instruction uses normalized

operands the initial dividend adjustment guarantees that the quotient will

be
If it is not, shift AR left (bringing Os into AR35) until a 1
appears in AR9, each time increasing the negative exponent by 1 (decreasing
normalized.

its magnitude).

Since the exponent is in negative form, if SCO is O, set Overflow and
Floating Overflow. If SC1 is also 0, the sign bit must have been changed
by

decreasing the exponent, so also set Floating Underflow. Insert the exponent

in correct form into ARI-8.

If the negative dividend flag and the divisor
sign (BRO) are of opposite states, negate AR to produce the correct quotient

sign.

The quotient is now ready for storage from AR and the remaining opera-

tions are performed only for long mode. Save the quotient in BR and bring
the high half of the original dividend from AC to AR. Put the dividend
exponent in SC.

Decrease its magnitude by 26 if the dividend was shifted

right at the beginning to allow the division to be performed; otherwise
decrease it by 27. Move the remainder to AR and insert the exponent
in it
provided the remainder is not zero and the exponent is within the
proper
range, —128 to 127 (the test is that the sign resulting from the exponent

calculation is the same as the sign of the remainder).

If the exponent is

D11

SYSTEM REFERENCE

-190-

D12

ALGORITHMS

outside that range clear AR; the assumption is that the remainder is of no
significance (ie the exponent is too small).

Move the remainder with its

correct exponent from AR to MQ and put the quotient back in AR.

The

two words are now ready for storage.

Double Precision Division. The software routine that performs double

precision floating point division and the algorithm it utilizes are given at

the end of §2.11. FDVL performs the d1v1S1on ,

Ab
where g

gq +r2'27/lz

and r are the quotient and remainder.

In a double precision

division the divisor is of the form

b+d27%

Using the expansion’
x+y

and letting x = b and y = d27% gives

25
-54
3~
81
(q+r2 =27 )[1_d2 =27 L2
2
+]

Multiplying out and gathering like terms gives

A
=
7

- b2(
=(r-qd)2*
+ b3(
= (r—qd)27¥
- ...
q q+-@-qd)2V
b(
qd)
qd)
qd)

where the first two terms on the right are those in the equation at the
bottom of page 2-67.
The ratio of adjacent terms is

Tn+1

_d2 —27

In an alternating convergent series, the error due to truncation 1s smaller

than the first term dropped. Therefore
d2 -27

IErrorI

Since the maximum value of d is less than 1 and the minimum value of b

(normalized) is %,

\Error]

T,27%

-191-

APPENDIX G

BIT ASSIGNMENTS

The drawing on pages G2 and G3 shows the formats of the various types of
words used by the processor. Bit assignmentsin the condition and data words

for the IO instructions will be added later.

SYSTEM REFERENCE

-192-

BIT ASSIGNMENTS

BASIC INSTRUCTIONS
INSTRUCTION CODE

(INCLUDING MODE)

d
12

¥
14

IN-OUT INSTRUCTIONS
L
0

DEVICE CODE

INSTRUCTION| 1

X
14

Y
17

PC WORD
FLAGS

OIOIOIOI,O

PC
18

i
et

T T T T T

CARRY | CARRY

OVERFLOW|
0

|ovesriow|

|FLOATING;

FIRST

PART |

USER

ADDRESS

USER | y.qu | PUBLIC | FAILURE | TRAP
5

e e ee e

2 | TRAP

FLOATING |

#DISABLE BYPASS

UNDER- | o vipe

K110 EXECUTIVE MODE

BLT POINTER {XxwD]
SOURCE ADDRESS

DESTINATION ADDRESS
17

BLKI/BLKO POINTER, PUSHDOWN POINTER, DATA CHANNEL CONTROL WORD {IOWD]
— WORD COUNT

ADDRESS-1

BYTE POINTER
POSITION P

SIZE §

X
14

Y
17

BYTE STORAGE
b

S BITs

BYTE
0

P BITs

NEXT BYTE

35-P-5-1

35-FP

35-P+1

PAGE MAP WORD
DATA FOR EVEN NUMBERED VIRTUAL

AlPiIW S

PAGE

DATA

PHYSICAL PAGE

ADDRESS BITS 14-26
5

FOR QDD NUMBERED VIRTUAL PAGE

- PHYSICAL PAGE

P|S|W|X
19

ADDRESS BITS 14-26
23

PAGE FAIL WORD
VIRTUAL PAGE

v
0

20 SMALL USER

VIOLATION

PROPRIETARY VIOLATION

FAILURE

ADORESS 8ITS 18-26
9

PAGE REFILL FAILURE

23 ADDRESS FAILURE

IF BIT 31715 0, BITS 31-35 HAVE THIS FORMAT

014
W

TYPE
35

-193-

SYSTEM REFERENCE
G3

WORD FORMATS

FIXED POINT OPERANDS
BINARY NUMBER (TWOS COMPLEMENT)
35

LCW ORDER WORD IN DOUBLE LENGTH FIXED POINT OPERANDS
LOW ORDER HALF OF BINARY NUMBER ( TWOS COMPLEMENT)
3%

FLOATING POINT OPERANDS
ys

EXCESS 128 EXPONENT

(ONES COMPLEMENT)

FRACTION (TWOS COMPLEMENT)
89

LOW ORDER WORD IN SOFTWARE DOUBLE LENGfl'I -FLOAT]NG POINT OPERANDS
0|

EXCEDS
128 EXPONENT-27

LOW ORDER HALF OF FRACTION (TWOS COMPLEMENT)
89

LOW ORDER WORD IN HARDWARE DOUBLE LENGTH FLOATING POINT OPERANDS

LOW ORDER EXTENSION OF FRACTION (TWOS COMPLEMENT)
35

-194-

SYSTEM REFERENCE

BIT ASSIGNMENTS

T oo

OCONOOEWN~O

POWERS OF TWO

128

256
512
024

1.0

0.5
0.25

0.125
0.062
0.031

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0.003 906
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125

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192

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768
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288

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304
216

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432

864

0.000 000 029 802 322 387 695 312
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NN+

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728

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456

536 870 912
824

073

147 483 648
294 967 296

589 934 592
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184

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0.000 000 119 209 289 550 781

0.000 000 007 450 580 596 923 828 125
0.000 000 003 725 290 298 461 914 062
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625
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000 465 661 287 307 739
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877 906 944

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613 281 25
806 640 625
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255

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562

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620
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610 850

186 320 021

785 644 531

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135 696 411

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567 848 205 566 406 25

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-195-

a(@w)

SYSTEM REFERENCE

THIS IS A TEMPORARY PAGE

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SYSTEM REFERENCE
-196-

A TEMPORARY PAGE