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Document:	XVM System Reference Manual
Order Number:	EK-15XVM-OP
Revision:	001
Pages:	304
Original Filename:

OCR Text

EK-15XVM-0OP-001

XVM system
reference manual

digital equipment corporation « maynard, massachusetts

1st Edition, June 1976

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

DECtape

DECCOMM

DECUS

PDP
RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

TYPESET-11
UNIBUS

CHAPTER 1

XVM PROCESSOR

1.1

CENTRAL PROCESSOR DESCRIPTION

1.2

ADDRESSING

e e e

... .. e
e e e

. .. .

... ... ... .....

1-1

... ... ........

1-7

1-5

1.2.1

XVM CPU AddressingModes

. . . ...

1.2.2

XVM MPU Address Mapping

. . . .

v v v

. . .

1.2.3

Addressing Examples

1.3

INPUT/OUTPUT PROCESSOR

1.4

MEMORY

CHAPTER 2

SYSTEM PROCESSORS

2.1

AUTOMATIC PRIORITY INTERRUPT

. .

I-11

i i i

1-13

e
e
e

1-37

APTHARDWARE

. .. ... .. ... .. ......

. . . . . . e
e
. . ... .. ... ... .. ......

2.4

DYNAMIC MAPPING

2.5

G-MODES

2.6

TRAPS

2.7

MEMORY ADDRESS TRANSLATION

. .

1-20

MEMORY MANAGEMENT (MMGR)
.

e s

2.2

v v

... . ...

. . . . . . . . . .

2.3

. .

e e e e e

e e e e
e

2-3
2-3
2-5

2-7

2-9

e
e
e 2-10
. ... .. ... ...

2.8

XM15S EXTERNALPORT

2.9

UNICHANNEL LINK

. . . . . . .

2.10

IOT INSTRUCTIONS

. . .

2.11

2.12

THE UNIBUS AND THE PDP-11 PROCESSOR

2.12.1

The Unibus

2.12.2

PDP-11 Processor

. . .

. ..

. ... . . .

.. e

. .

e e

.. .. e

. . .

. .

e e e ee
e e e e

e e e e

e e e

. . .

.. ... ... ... ...... 2-20

CHAPTER 4

SYSTEM OPERATION

4.1

XVM PROCESSOR

4.2

PC15 HIGH-SPEED PAPER-TAPE READER ANDPUNCH

CHAPTER 5

SYSTEM INSTALLATION

5.1

INTRODUCTION

5.2

PREDELIVERY PLANNING

5.3

SITEPLANNING

. . .

e e

e 2-16

. 2-17

4-1

s
. . . . . . . . .. .

. . . . . . . .

ENVIRONMENTAL PLANNING

. . . . ... . .

5.5

ELECTRICAL PLANNING

. .

1ii

e e

. . . .

...

e e

...

5.4

2-15

. . .

PERIPHERALS

s 2-15

CHAPTER 3

e e e 2-15
e

FP15 FUNCTIONAL DESCRIPTION

SYSTEM OPERATION

e
e

. 2-13

2-15

2.14

... ... ......

2.13

. . .

.. 2-12

. . . .
.

........ 2-11

... ... 4-18

5-1

e st

5-3

.. ... .. .. .....
e

e e

5-4
5-7

CONTENTS (Cont)

5.6

COMMUNICATIONS

5.7

UNPACKING

. .

5.8

INSPECTION

. .. .. F S

5.9

CABINET INSTALLATION

5.10

PERIPHERAL EQUIPMENT INSPECTION

5.11

ELECTRICAL AND MECHANICAL SPECIFICATIONS

5.12

MISCELLANEOUS PART NUMBERS

5.13

5.14

MAINTENANCE AND SERVICEOPTIONS
. . . . . . .
FORMS AND CHECKLISTS

CHAPTER 6

INSTRUCTION FORMATS

6.1

BASIC INSTRUCTION SET

6.2

EXTENDED INSTRUCTION SET

. . . . . b
e e
e e
.

e e

. . . . . . . . .

o e

. . . .. ... ... ... ... ...

. . . ... ... ... .. ...

. .

e e

oo i oo

. . . . .. ... ...

6.3

FLOATING POINT UNIT

6.4

AUTOMATIC PRIORITY INTERRUPT INSTRUCTION SET

. . .

6.5

KW15 READ-TIMECLOCK

6.6

KFISPOWER FAIL

. .

6.7

MEMORY MANAGEMENT

6.8

PERIPHERAL INSTRUCTION SET

...

e e

. . . . . . .. ... ...

. . . . . .

. . . . ... .. ... ... ...
. . ... ... ...

. . . . . . . .
.

e e

. . . ...
.

... ...

oo oo

. . .. . . . .. . ..
. . . . . . ... ... .. ... .. ..

ILLUSTRATIONS
Title

Figure No.
1-1

Central Processor, Simplified Block Diagram

1-2

Real and Virtual Addresses

1-3

Memory Addressing

1-4

Direct Addressing: Typel

. . . . . .. .. ... ... ..

. . . . . . . . . .

. . . . . . . . . i e e e
. . . . . . . .

. .

1-5

Indirect Addressing: TypelIl

1-6

Auto-Increment Addressing: TypelIl

1-7

Indexed Addressing: TypelIV

1-8

Indirect-Indexed Addressing: TypeV

1-9

Auto-Increment, Indexed Addressing: Type VI

1-10

Address Modification Flowchart

1-11

Direct Mapping (DMAP)

1-12

Relocated Mapping(RMAP)

1-13

Shared Mapping (SMAP)

..
e

. . . . . . . . . . .

. .

oo
..

..
o

.. e
oo

o e

External Shared Address Space (ESAS) Example
.

...

Boundary Mapping (BMAP)

1-15

. .

o
..

1-14

. . . . . . . ... ... ...
.

. . . . . . . .
.

. . . . . . . . . .

Lo 0

. . . . . . ... ..o
o
.

. . . . . . . . o . .

Lo e

e e e e e e e e e e e

. . . . ... ... .....

ILLUSTRATIONS (Cont)

Figure No.

Title

Page

1-16

Shared Mapping Example

1-17

Multicycle Out Block Transfer Flowchart

1-18

Multicycle In Block Transfer Flowchart

1-19

Multicycle Transfer Implementation

1-20

Single Cycle Block Transfer Flowchart

. . .

. . . . . .

. . . . .. ...

. .

. ... ... .....

...

... ...

IOT Instruction Format

. . . .

. .. . . .

... ..

1-23

Memory Location Just After a Program Interrupt

1-24

Common I/OBus

.
.

.....

1-26

... . .....

1-28

1-29

1-30

... ...

. . . . . . . . . .

1-25

I/O Read Status Bit Assignments

1-26

MF15-U Simplified Block Diagram

1-27

Assigned Module Slots

1-22

1-23

1-19

1-24

. ... .

IOT Instruction Timing

. . .

1-21

. ... ...

. . . . . . . . ... ... ......
.

1-22

1-32

. . . . . . . . . ... ... ... ... ..
. . .

. .

. . ...

1-33

.. .....

1-39

. . . . . . . . ...

1-40

2-1

XM15 Basic Block Diagram

2-2

API System, Simplified Block Diagram

2-3

Memory Management Block Diagram

2-4

User’s Virtual Address Space in S-SMAP

2-5

S-Mapping

2-6

Memory Address Translation

2-7

Memory Address Shifting Process

2-8

Datalnput

2-9

DataOutput

. . . . . . . . ... ...
. . . . .

... ... ... .. ...

. . . . . . . . .. ...

2-2
23

... .....

2-5

. . . . . . . . . . .. ... .....

2-8

. . . . ..,

2-9

...

. .

. . . .

. .
.

. . .

. .

...

... ..

...

... 2-12

...

2-13

2-14

2-10

Status Information

2-11

PDP-11 System, Simplified Block Diagram

2-12

FP15 Floating Point Processor Simplified Block Diagram

3-1

AD15 Analog-to-Digital Conversion Subsystem

3-2

Industrial Control System

3-3
3-4

. . . . . . .

2-12

3-7

3-5

DCO1-ED Block Diagram

3-6

VT15 Graphic Processor, Block Diagram

. . ..

.
.

... ..
.

3-7

VTO7 and VT04 Graphic Display Consoles
LP15 Data Buffer Header Format

. . .
.

. . . .

...

XVMConsole

4-2

Peripheral Processor

4-3

Paper Tape Readerand Punch

4-4

Orientingthe Tape

4-5

Installing Tape in Paper Tape Reader

4-6

Installing Tape in High-Speed Paper Tape Punch

. ... ....... e

.... 3-17

... ......

...

3-16
3-22

....... 3-26

3-31

e e

4-1

...

. . .

. e 4-20

. .

. . . . .

...

. . ...

. ...

4-1

e e e e 3-11

XVM DECdisk System
.

. . ... ... .......

Typical LT19 System Configuration

3-9

3-10

... ... .. ..... e

3-8

. . .

3-3

3-6

. . . . . . .. .. ... ...

... 2-15

. . . . . . . . . ... ... .. .. ....
.

... ...

. . . . . ...
.. . 2-21

Flying Capacitor Circuit

. .

. ...

UDC-15 Input/Output Operation
.

. .

3-5

. . .

...

.. ... . 2-14

... 4-14

...

. . . . . . e

... ..

...

..... 4-19

...... 4-21

e e 4-24

ILLUSTRATIONS (Cont)
Title

Figure No.

5-1

Relationship of Disk Head, Disk, and Contaminants

5-2

60 Hz Power System

. . . . . . . . . v

5-3

S50Hz Power System

. . . . . . .

. . . . . . . . . . . ..
e

e e e e
e e e e e e e e e

5-4

NEMA Plugs Supplied with Digital Equipment Corporation’s Products

. . . .

5-5

20 mA Mate-N-Lok Connector

. . . . . . . . .« « v o v v v i v v

oo e

5-6

Cabinet Bolting Diagram

. . . . . . . . . . .

5-7

XVM Basic Configuration

. . . . . . . . . . ..

.o oo
e

e e e e e e e e e e e e e

. . . . . . . o o i o

5-8

Basic XVM Cabinet

5-9

XV100 and XV200 Physical Configurations

5-10

System Configuration Diagram

5-11

6-1

Peripheral Processor Configuration Guide . . . . . .. ... ... ... ...
. . . . . . . ... ... o000
Memory Reference InstructionWord

6-2

Augmented Instruction Format

6-3

Instruction Bit Configuration

. . . . . . .. . ... ... ...

...
. . . . . . . . . ... ...

...
. . . . . ... .. .. .. ...

. . . . . . . . . . . . .

. . . . . . . . . . ... .. ...

6-4

Allowable Microinstruction Combinations

6-5

IOT Instruction Word Format

6-6

IOT Instruction Timing

6-7

IORS Word Status Bit Assignments

6-8

EAE Setup Microinstructions

. . . . . . . . .. ...

. . . . . . . . . . . . . v oo

. ... ...,

. . . . . . . . . . . .. ...

e e

. . . . . . . .« « 0 0 v i v v e e e e

. . . . . . . . ... ... ... ... ..
o 000000

6-9

EAE Shift Microinstructions

6-10

EAEFE Normalize Microinstructions

6-11

EAE Multiplication Microinstructions

6-12

EAE Division Microinstructions

. . . . . . . . . . ..

6-13

EAE Simplified Block Diagram

. . . . . . ... ... ... .. ... ...,

6-14

Floating Point Instruction Format

6-15

Floating Point Address Format

. . . . . . ... ... ...

6-16

Single Precision Integer Format

. . . . . . . . .. ... ... .. ......

6-17

Extended Integer Format

. . . . . . . . . . . .

...

. . . . . . . . . . .. ... ... ...
.00

. . . . . .. .. .. ... ... .....

. . . . . . . . . .. . ...

... .....
0.

6-18

Single Precision Floating Point Format

. . . . .. ... ... ... .....

6-19

Double Precision Floating Point Format

. . . . . . . .. . ... ... ...

6-20

Skip on Priorities Inmactive

. . . . . . . . . .. 00000

TABLES
Title

Table No.
1-1

Interface Devices

. .

. . . 0 i e

e e

1-2

MF15-U Core Memory, Specification Summary

1-3

ME15 Memory Specifications

4-1

Console Controls

e e

e e e

. . . . .. . .. . ... ...

. . . . . . . . ...

o 00000000

. . . . . . . . . .. ... 0.0 e

e e e e

TABLES (Cont)
Table No.

Title

Page

4-2

Console Indicators

4-3

Paper-Tape Reader and Punch Controls

5-1

Summary of Site Preparation and Installation Functions

. . . . . . . . . . . . ... 4-10
. . . . . . ... ... ... ..... 4-19

5-2

Recommended System Environmental Ranges

5-3

Voltage RANES

. . . v v v o v e

e e

. .
...

.. .. .. ..

... ... ...

5-2
54

5-8

5-4

Cabinet-mounted Options

5-5

Current Free-Standing Peripherals

5-6

Optional Peripheral Equipment Cable Lengths

6-1

EAE Microinstructions

. . . . . . .. ... ... ... 6-40

6-2

EAE Microinstructions

. . . . . . . . . . ...

6-3

FP1S Instruction Summary

6-4

Input/Output Transfer Instructions

6-5

Standard API Channel/Priority Assignments

6-6

IOT Device SelectionCodes

. . . . . . e

e e e e e e e e e e e e e

e 5-21

. . . . . . . . . . . . . .. .. .. .... 5-22
. . . . . . . . ... .. ... 5-23

e e e

e 6-41

. . . ... . ... .. ... ... ... ..... 6-71

. . . . . . . .. ... ... .. ..... 6-85
. . . . . . . . ... ... ... 6-97

. . . . . . . . . . .. .

vii

... 6-98

FOREWORD

XVM systems offer comprehensive solutions to data processing needs. They combine new design
concepts with a wide array of traditional features that have evolved from DIGITAL’s years of leadership in the medium scale scientific computer field. Both elements share the common purpose of
simplifying the application of XVM computer systems to accommodate demanding environments.
XVM systems excel in applications where hardware and software components are matched to meet the
requirements of the user. These matches of hardware and software components can be viewed at two
levels. First, XVM systems come with a complete assortment of support software tools to allow complete programming. These tools, such as monitors, compilers, and system utility components, are the
base on which all XVM systems are built. Second, for certain specific turn-key applications, XVM
systems come ready to perform applications work with no further programming. At both levels, hardware components allow for modular additions and field upgrades without penalty.
DIGITAL offers a variety of configurations as hardware building blocks to total system capability.
These systems differ in their hardware options and peripherals that are required to support various
operational software.
The hardware systems are designed with several functional objectives in mind. Among these are the
complete autonomy between central processor, input/output processor, and memory, so that processing and I/O operations can occur concurrently in overlapping cycles: A PDP-11 programmable peripheral processor, so that slow speed devices can be spooled to a high performance disk; TTL
integrated-circuit construction for high reliability; fast internal speeds, to meet the demands of realtime data processing; core memory expansions to 131,072 words for future growth; floating point
hardware for demanding scientific applications; and a sophisticated memory protect system for multiuser integrity in multiprogramming environments. Peripheral device handling and interfacing to
instruments are easily accomplished and system growth potential is virtually unlimited with the modular structure of the XVM hardware and software systems.

INTRODUCTION

The XVM 18-bit computer has unique capabilities attractively suited to high-speed data acquisition
and processing. Expandable core memory (to 131,072 words) and a full complement of processor
options and peripherals enable the XVM to handle virtually any medium scale computing

requirement.

This manual supplies background information to familiarize the reader with present and potential

capabilities of the system.
THE XVM SYSTEM

The basic XVM System is organized into three autonomous subsystems: central processor, memory,
and I/O processor, each with independent timing and control logic. Communication between these
subsystems occurs through use of an effective asynchronous request scheme. Subsystem autonomy
facilitates wide scale expansion of the system, increased throughput, high capacity, reliability, and
maintainability. Four other major subsystems of the XVM are: the floating point processor, the peripheral processor, the XVM I/O bus peripherals, and the Unibus peripherals..
CENTRAL PROCESSOR (CPU)
The CPU controls and executes the system’s stored programs. By virtue of its control autonomy, the
CPU coordinates its operation with that of other subsystems, thus providing supervisory control over
the XVM.
As the main unit in this integrated control, the central processor contains arithmetic and control logic
hardware for a wide range of operations, including high-speed, fixed point arithmetic and hardware
multiply and divide option, extensive test and branch operations implemented with special hardware
registers, high-speed input/output instructions, and other arithmetic and control operations.

The basic processor includes a number of major registers for processor-memory communications; it
also includes a program counter, an accumulator, an Index register, and a Limit register. Two 18-bit
registers provide memory buffer functions. This allows for processor overlap with memory cycle time
and affects faster instruction execution times.
MEMORY
Memory is the primary storage area for computer instructions and system data. Independent
read/write control and buffer logic in each memory segment establishes complete autonomy for the
memory, i.e., different memories can be accessed simultaneously by different processors. The primary
XVM memory systems are the ME15 and MF15 memory units that permit installation and utilization
of up to 131,072 words of core memory in 8K or 32K increments.

MEMORY PROCESSOR

The XM15 Memory Processor, located between the memory and the CPU, 1/O, and peripheral processors, contains the Memory Management logic, the Instruction Pre-fetch unit, the Automatic Priority
Interrupt unit, and the Memory Ports which arbitrate the different memory requests. The XM15 has
dual input ports, and may have two output ports to memory. The device will operate with either ME13
(8K) or MF15 memories on one or both of its output ports. Memory interleaving is possible with
similar memory types and it is also possible to interleave the two output ports.

I/0 PROCESSOR

The 1/0 processor satisfies the peripheral data transfer needs. A diverse line of system peripherals
available to the XVM require this processor to interface three modes of input/output:
1.
2.

Single cycle block data transfer; blocks of data transfer at rates of up to 1 million words per

second.

Multicycle block data transfer; blocks of data transfer at rates up to 250,000 per second for

input and 180,000 per second for output.

Program control data transfers; single word transfers to/from the accumulator in the central

processor unit.

The 1/0 processor provides timing, control, and data lines for information transfers between memory
or the central processor and the peripheral devices. It also provides for such features as the automatic
priority interrupt system and the real-time clock.
FP1S Floating Point Processor

The FP15 enables the XVM to perform arithmetic and logic operations using floating point arithmetic.
The prime advantage is increased speed over complex floating point software routines. The FP15 has
single precision and extended integer capability, as well as single and double precision floating point.

The FP15 is an expansion of the central processing unit and increases the XVM instruction set by over

120 instructions. Floating point instructions intermix with XVM instructions. This In-line mode of
operation greatly simplifies programming and ensures fast execution.

Peripheral Processor

The Unichannel 15 (UCI1S5) is a peripheral processor for XVM that uses a PDP-11 minicomputer. It
provides the XVM with a second general purpose processor and a second high-speed 1/0O bus: The
Unibus is an 18-bit pathway permitting transfer of 18-bit words, 16-bit PDP-11 words, or two 8-bit
bytes.

CHAPTER 1

XVM PROCESSOR

UNIBUS

PERIPHERALS

PERIPHERAL
PROCE SSOR

MEMORY

PROCESSOR

(*—~ PROCE SSOR

CENTRAL

{

PROCESSOR

—

FLOATING
POINT

PROCESSOR

I/0

BUS

*::>

I/0 BUS

PERIPHERALS

15-0982

1.1
CENTRAL PROCESSOR DESCRIPTION
The central processor (CPU) controls and executes stored programs. By coordinating its operation
with that of other subsystems, it provides supervisory control over the XVM system.

The CPU contains arithmetic and control logic for a wide range of operations. These include highspeed, fixed point arithmetic with hardware multiply and divide, extensive test and branch operations
implemented with special hardware registers, high-speed input/output instructions, and other arith-

metic and control operations.

The XVM CPU contains several major registers for processor-memory communications, — a Program
Counter, an Instruction register, an accumulator, an Index register, and a Limit register.
SUMMARY OF CHARACTERISTICS
Description - 18-bit parallel operation, asynchronous operation, fixed point signed and unsigned
arithmetic (1’s and 2’s complement)
Instruction Types
Memory Reference
Operates
Register Transfer and Control
Extended Arithmetic Element
Input/Output Transfer
Indexing - 1 Index register, 1 Limit register, 8 auto-increment locations

1-1

The CPU performs calculations and data processing in a parallel binary mode through step-by-step
execution of individual instructions. Both the instructions and the data on which the instructions
operate are stored in the core memory of the XVM. The arithmetic and logical operations necessary
for executing instructions are performed by the arithmetic unit operating with central processor registers. Figure 1-1 shows a simplified block diagram of the CPU.

TO MfiMORY

FROM MEMORY

INSTR
REGISTER

MEMORY

INPUT

OUTPUT

r—"’

PROGRAM

COUNTER

—

OPERAND

_——

ADDRESS

FROM

1/0 BUS

wa——

opaTa swiTcH

[+ ROMCONSOLE

INDEX

o1t

LIMIT

‘.

INPUT GATING

ARITHMETIC UNIT

STEP
COUNTER

ACCUMULATOR

MULTIPLIER
QUOTIENT

LINK

15-0002

Figure 1-1

Central Processor, Simplified Block Diagram

Arithmetic Unit (AU)
The XVM Arithmetic Unit (AU) handles all Boolean functions and contains an 18-bit, 85 ns adder.
The AU acts as the transfer path for inter-register transfers and shift operations.

Instruction Register (IR)
This register accepts the six most significant bits of each instruction word fetched from memory. Of
these bits, the four most significant constitute the operation code, the fifth signals when the fetched
instruction indicates indirect addressing, and the sixth indicates indexing.
Accumulator (AC)
This 18-bit register retains the result of most arithmetic/logical operations.
For all program-controlled input/output transfers, information is transferred between core memory
and an external device through the AC. The AC can be cleared and complemented. Its contents can be
rotated right or left with the Link. The contents of the memory, buffered through the Memory Input
register, can be added to the contents of the AC with the result left in the AC. The contents of both
registers can be combined by the logical operations AND and exclusive-OR, the result remaining in

the AC. The inclusive-OR can be performed between the AC and the data switches on the operator’s
console (through the Data Switch register) and the result left in the AC.

Data Switch Register
|
The Data Switch register receives and stores an 18-bit word through the console bus from data switches on the console. This allows programs to accept switch data from the operator’s console.

Link (L)
This 1-bit register is used to extend the arithmetic capability of the accumulator. In 1’s complement
arithmetic, the Link is an overflow indicator; in 2’s complement arithmetic, it logically extends the
accumulator to 19 bits and functions as a Carry register. The program can check overflow
into the
Link to simplify and speed up single- and multi-precision arithmetic routines.
The Link can be cleared and complemented and its state sensed independent of the accumulator. It is
included with the accumulator in rotate operations and in logical shifts.
Program Counter (PC)

The PC determines the program sequence (the order in which instructions are performed)
. This 17-bit
register contains the address of the next instruction.
Operand Address Register (OA)
The Operand Address register is an internal register that contains the address of the location
where
data is currently being fetched.
Memory Input and Output Buffer Register (MI and MO)

Information is read from a memory cell into the Memory Input register and is interpreted as
either an
instruction or a data word. Information is read from the CPU into memory through the
Memory
Output register, and is interpreted as either an address or a data word. The use of two internal 18-bit
registers for memory buffer functions allows processor overlap with memory cycle time to decrease
execution time and to allow autonomous operation of the CPU and memory. They also allow the I/0

processor to gain access to memory between cycles of multicycle instructions. By not having to wait
for
completion of an instruction, I/O device latency is vastly improved.

1-3

Index Register (XR)

The 18-bit Index register is used to perform indexing operations with no increase in instruction time.
An indexed operation adds the contents of the Index register to the address field of the instruction
operand, producing an effective address for the data fetch cycle. Index value can be positive or negative in 2’s complement form (+131,072). The Index register can be used with the Limit register,
described in the following paragraph.

Limit Register (LR)

The 18-bit Limit register enables a program to detect loop completion. The base address of a data
array is loaded into the Index register and the ending address is loaded into the Limit register. Within
an indexing loop, add to index and skip (AXS) instruction adds a signed value (-25610 < Y < +25510)
to the Index register and compares the sum in the index to the contents of the Limit register. If the
contents of the Index register are equal to or greater than those of the Limit register, the next instruction is skipped.

XVM Control Console

The XVM system console contains the controls, switches, and lights required for operator initiation,
control, and monitoring of the system. Up to twenty-four 18-bit registers can be displayed to provide
the user with visual indication of major registers and buses.
Some of the features of the console are:

A READ-IN switch to initiate the hardware reading of the bootstrap devices.

REGISTER indicators and REGISTER DISPLAY switches to allow continual monitoring
of key points in the system such as the accumulator, Index register, Limit register, Multiplier-Quotient register, Program Counter, memory address, interrupt status, input/output
bus, input/output address, and I/O status.

Separate ADDRESS and DATA switches to establish an 18-bit data or instruction word to
be read into a memory location by the DEPOSIT switch, to be entered into the accumulator
by a program instruction, or to be executed by the EXECUTE switch.
EXAMINE switch to allow the manual examination of the contents of any memory location

placed in the ADDRESS switches.

KE15 EXTENDED ARITHMETIC ELEMENT (EAE)

The KE15 Extended Arithmetic Element (EAE) is a standard XVM feature which facilitates highspeed arithmetic operations and register manipulations. The EAE uses an 18-bit Multiplier-Quotient
register (MQ) as well as a 6-bit Step Counter register (SC). EAE instructions can be microcoded so that
several operations are performed by one instruction to simplify arithmetic programming and reduce
execution time.

Multiplier-Quotient Register (MQ)

The Multiplier-Quotient register and accumulator perform as a 36-bit register during shifting, normalizing, multiplication, and division operations. The contents of the Multiplier-Quotient register are
displayed by the REGISTER indicators on the operator’s console when the REGISTER DISPLAY
control is in the MQ position.

During the multiply instruction, the MQ receives the 18 least significant bits of the double word
product formed in the AC and MQ. During the divide instruction, the MQ is the least significant 18
bits of the double word DIVIDEND formed by the AC and MQ.
1-4

Step Counter (SC)

The Step Counter is used to count the number of steps in an EAE instruction. The step counter is
preloaded, except during normalize operations, with the numbers of steps specified by an instruction
and is counted down as the instruction is executed. When the SC reaches zero, the EAE operation is
terminated.
PROCESSOR EXPANSION

KF15 Power Failure Protection
The basic XVM is not affected by power interruptions of less than 10 ms duration. Active registers in
the processor may lose their contents when interrupts of longer duration occur, but memory is not
disturbed. The KF15 Power Failure feature, standard on all XVM systems, allows the preservation of
the active register contents in the event of longer power interrupts and the automatic restart of the
system when power is restored. When the line power failure occurs, the system must be operating with
the program interrupt facility or the automatic priority interrupt system enabled in order to sense the
KF15’s initiation of a program interrupt in time to save the register contents. When power is restored,
the processor automatically restarts and the instruction in location 0 is executed.
1.2
ADDRESSING
The following paragraphs explain XVM addressing modes and formats.
Words in Memory

Words stored in magnetic core memory are simply strings of 18 bits. There is no method of distinguishing between an instruction word and a data word. The Central Processor Unit (CPU), which
decodes and operates an instruction word, can differentiate between instruction and data words
because of the sequence in which they appear at the CPU, from memory.
To keep track of the sequence, the processor is provided with a Program Counter which normally
holds the address of the next location in sequence in the memory. The word thus located, may point to
another location that is the address of a data word or instruction.
There are three main types of instructions:
1.

Instructions that reference memory indicating in the operand address field the (virtual) location of the data necessary to complete the instruction. For example, ADD the contents of
location 000100 to the accumulator.

Instructions that deal with control, and do not require a memory access. For example,
RAL:
Rotate the accumulator and link one place to the left.

Instructions that reference peripheral equipment, and cause information transfers to or from
the devices, termed 1OT’s. For example, TLS: Load console terminal print buffer from
ACI10-17, and start printing.

Addresses
There are two types of addresses: real and virtual. The XVM system uses both types in a variety of

ways to facilitate as many operations as possible (Figure 1-2).
Virtual addresses are those calculated by the CPU and sent to the Memory Processor Unit (MPU).
Virtual addressing makes it possible for many users to obey the same rules, use the same addresses, and
yet all can use the XVM system at the same time. The virtual addresses are accepted by the MPU and
modified if necessary, depending upon which manner of addressing is currently set up within the
MPU. The resulting address is then sent to memory as a real address. A real address corresponds to the
required location in memory, as shown in Figure 1-3.

1-5

MEM ORY

REAL
ADDRESS

MEMORY
PROCESSOR

(MPU)
VIRTUAL
ADDRESS

CENTRAL
PROCESSOR

(CPU)
15-0822

Figure 1-2

LOCATION

Real and Virtual Addresses

PAGE

BANK

BLOCK

0]
PAGE
4K

7777
10600

17777

'
BANK O

PAGE

20000
27777
30000

16K

BANK

37777

BLOCK

40000

0
PAGE

PAGE

47777
50000

24K

BANK 2

57777
60000
67777

BANK

70000

32K

77777

MEMORY ADDRESSING

100000

PAGE

4K LOCATIONS

BANK

8K LOCATIONS

BLOCK =
1
64K

32K LOCATIONS

177777

200000

e N

277777
300000

128K

377777
15-0184

Figure 1-3

Memory Addressing

1-6

1.2.1
XVM CPU Addressing Modes
The XVM Central Processor produces an address in a variety of ways which are described briefly in
the following paragraphs to assist the reader in understanding the whole addressing picture. Detailed
programming examples are provided in paragraph 1.2.3.
To start with, assume that virtual addresses are un-modified by the MPU.
Direct Addressing:

Type I
A direct address (Figure 1-4) is the most basic type of address. The address field is either 13 or 12 bits
long, depending upon whether the XVM CPU is in Bank or Page mode respectively. This type address
is usually termed an operand address, because an instruction normally occupies bits 00 to 03.

ADDRESS

PAGE

MODE| 13
MODE @ 12

BITS
BITS

BANK

MEMORY

15-0826

Figure 1-4

Direct Addressing: Type I

Indirect Addressing: Type II
An indirect address (Figure 1-5) is more complex than the direct address. The operand address (in the
upper box) contains the address of a location, which in turn contains an address of a data word. The
width of the address that is passed to memory depends upon the conditions prevailing in the MPU at
that time. Normally, either 15- or 17*-bit addressing is selected by the monitor’s software.

17
ADDRESS

ADDRESS

17
= MEMORY

15-0827

Figure 1-5

Indirect Addressing: Type I1

Auto-Increment Addressing: Type III
The auto-increment address (Figure 1-6) is a special type of indirect addressing. If any one of the

addresses 00010 to 00017 should be addressed indirectly, the contents of this ‘“auto-increment” location will be extracted, incremented, and restored. This value is then used as the address of the required
data word. When these auto-increment addresses are accessed in any other way, they function as other
locations. This feature facilitates the processing of sequential strings of data.
Note that the actual core memory locations affected by the auto-increment process are determined by
the current settings of the MPU.

*16- and 18-bit addressing is permitted, but it is not used by current DEC software.

1-7

ADDRESS

(10g -178)

»
AUTO-INCREMENT

LOCATION

Ho-

{ IN AUTO- INCREMENT LOCATIONS
)

- MEMORY

SUM

15-0828

Figure 1-6

Auto-Increment Addressing: Type III

Indexed Addressing: Type IV
Indexed addressing (Figure 1-7) makes use of the Index register to address up to 131072 locations. Bit
05 is used to indicate that an indexed reference is being made. It follows that the XVM CPU must be
running in Page mode to enable this mode of addressing. The operand address is concatenated with
PCO01-PCOS, from the Program Counter (PC). The result is added to the contents of the Index register
(XR) and the sum is used as the memory address. Note that the contents of the Index register may be

negative.

]

ADDRESS

05/

17
INDEX

SUM

Figure 1-7

- MEMORY

Indexed Addressing: Type IV

Indirect-Indexed Addressing: Type V
Indirect-indexed addressing (Figure 1-8) is the first of the composite types of addressing. The 12 bits of
operand address point to (i.e., contain the address of) a location that holds an address. This second
address may be 15 or 18 bits wide, depending on the internal settings of the MPU. This address has the
contents of the Index register (18 bits) added to it, and the result is sent to the MPU. This will again
affect the address such that either 16, 17, or 18 bits of address will be presented to the memory.

1-8

17
ADDRESS

17
INDEX

SUM

15-0830

Figure 1-8

Indirect-Indexed Addressing: Type V

Auto-Increment, Indexed Addressing:

Type VI

This is the most complex type of XVM CPU address formation (Figure 1-9). The operand address

(between 10 and 17s), when referenced indirectly, becomes the pointer to an auto-increment location,
the contents of which are incremented by one, and used as an address. The contents of this location has
the current value of the Index register added to it, and the sum is used as the final address to be sent to
the memory via the MPU.

ADDRESS

—

(10g-175)

AUTO - INCREMENT LOCATION
+1
00

ADDRESS

(LEFT
IN AUTO- INCREMENT LOCATION)

00
INDEX

SUM

15-0831

Figure 1-9

Auto-Increment, Indexed Addressing: Type VI

In summary, there are six XVM CPU addressing modes. These are designated Type I through Type
VI, in order of their complexity. Figure 1-10 is a flow chart of the address modification sequence.

1-9

SHARE MODE
ON?
NO

INDIRECT
BIT04=1

ADDRESS
10,-17,

ADDRESS

INCREMENT

>377,?

MEMORY

LOCATION
10,-17,

ADDRESS

UP TO

18 BITS,
DEPENDING
ON G MODE

GET
INDIRECT
ADDRESS

WITHIN
SEGMENT

LENGTH?

(NOTE POST
INDEXING)

INDEXED

BIT05=1

ADD CONTENTS

OF INDEX
REGISTER

TO ADDRESS

YES

USER MODE
ON?

PC00-17

TO XM BUS

RR00-09

AND
PC00-17
TO XM BUS

SUM SR00-09
AND PC05-17
TO XM BUS

SUM RRO00-09
AND PC00-17
TO XM BUS

15-0832

Figure 1-10

Address Modification Flowchart

1.2.2 XVM MPU Address Mapping
The following paragraphs briefly describe the four ways that the XVM MPU changes virtual addresses
to real addresses before sending the addresses to core memory. The MPU performs a wide variety of
functions. However, the majority of these functions are only operative when the system is in User
mode (for a full description of User mode, see Chapter 2, Section 1).
There are four ways that the virtual address presented by the CPU can be converted to a real address:

Direct Mapping (DMAP)

:
Refer to Figure 1-11. In this mode, the CPU-generated address is passed through the MPU and no
modification takes place. This form of addressing is in effect whenever the system is in either of the two
following states; first, when the system is in the Executive mode of operation, which means that
none
of the memory management functions are being used; second, when the system is in User mode,
but
the Relocate Disable (RDIS) function is operative.
Relocated Mapping (RMAP)

Refer to Figure 1-12. The system, to be in this category of addressing, must be in User mode, and
relocation must be enabled (RDIS is false). The addresses presented by the XVM CPU have the
contents of another register added to them, so that the correct partition* is accessed. The Relocation
register (RR00-RR09) holds the equivalent of an “offset,” which is used to map the virtual address to
the user’s area of core.

X AND Y ARE ARBITRARY
ADDRESSES, R IS EFFECT
OF RELOCATION.

Yypmom— — m

/TM

——

— — — — ] Y

/ ——————— 1

RMAP
DMAP

/ ————————— X+R

VIRTUAL CORE

Figure 1-11

REAL CORE

Direct Mapping (DMAP)

VIRTUAL CORE

Figure 1-12

REAL CORE

Relocated Mapping (RMAP)

Shared Mapping (SMAP)

Refer to Figure 1-13. This particular form of address manipulation is the most complex of the XVM
addressing schemes. When the system is in User mode and Share mode, the virtual addresses issued by
the XVM CPU are examined by the MPU to determine if they liec within the Shared Address Space
(SAS). The SAS is defined by two limits; the starting address of the SAS is a function of the G-Mode
bits, and the length of the SAS is held by the Segment Length register (SLR). If the CPU address is
within the SAS, and furthermore if it is within the first 400 locations, then the CPU is referencing the

Internal Shared Address Space (ISAS). The address (bits 10~17)
is combined with the contents of the
Relocation register (RR00-09) and the result is sent to the memory. The location accessed will be
within the first 4005.locations of the user’s partition.
*“Partition” refers to the area of real memory that has been assigned to that particular program,

Y+S

—

A+R

R+400g
X+R

REAL CORE

VIRTUAL CORE

A= BEGINNING OF SAS AND ISAS

B = END OF ISAS (A+4004)
Y=END OF SAS

R=RELOCATION OFFSET
S=SHARE OFFSET
15-0836

Figure 1-13

Shared Mapping (SMAP)

Refer to Figure 1-14. If the XVM CPU address happens to be within the limits of the SAS, but not
within the first 4005 locations thereof, then the CPU is said to be accessing ESAS (the External Shared
Address Space); to reach this area, the CPU address (bits 05-17) is added to the contents of the Share
register (SR00-09), which holds another “‘offset” similar to the Relocation register. The sum of these is
then sent to memory.

ESAS = EXTERNAL SHARED ADDRESS SPACE

64K

ISAS = INTERNAL SHARED ADDRESS SPACE

SLR = ISAS + ESAS

32K

ESAS

SAS

’

S6K
«—

48400

USER

ISAS

24K

ESAS

///

Pre

«—12400 | PARTITION
ISAS

12K

I/0 & SYSEM

USER
K

PROGRAM|

VIRTUAL MEMORY

EXECUTIVE

REAL MEMORY
GM =0
SLR=3
= 1
UM

SR= 48K
RR=12K
15-0835

Figure 1-14

External Shared Address Space (ESAS) Example

Boundary Mapping (BMAP)

Refer to Figure 1-15. To use the facilities of this separate, special type of mapping, the XVM CPU and
MPU must be configured as a “P-Mode” system. The previous two methods of address modification,
RMAP and SMAP operate only while the system is configured as an “R-Mode” system.

B8MAP

B=BOUNDARY
15-0837

Figure 1-15

Boundary Mapping (BMAP)

The XVM system, when in BMAP, establishes a boundary in real core below which access is prohibited. This type of mapping is normally used in specialized applications.
There is another register that is used by the RMAP, BMAP, and SMAP categories, called the Boundary register (BR00-09). It specifies the virtual address that is considered to be the upper limit of the
user’s partition or the lower limit of the user’s allowable memory area in BMAP operation. If an
attempt is made to map a virtual address to a real address beyond the zone established by the Boundary value, the XVM CPU will TRAP, because of the boundary violation. The TRAP is an alarm
condition which informs the CPU that a violation of some kind exists and must be rectified.
1.2.3 Addressing Examples
Programming examples for each type of addressing (Type I through Type VI) are provided in the
following paragraphs. In these examples, it is assumed that the MPU does not modify the address
received from the XVM CPU.

Short program examples are also provided to illustrate the effects of the MPU in different address
mapping modes.
Direct Addressing, Type I - Bank or Page Mode
The XVM uses bits 5 through 17 in Bank mode, or bits 6 through 17 in Page mode, as the effective
address (EFA) for direct addressing.
The following example illustrates direct addressing:
PC

Instruction

000100

202222

(LAC 02222)

In the example, the instruction fetched from location 000100 specifies “load the AC with the contents
of location 2222.”” Direct addressing is indicated, and the EFA is 002222.

1-13

Indirect Addressing, Type 11 - Bank or Page Mode

Indirect addressing is specified when bit 4 of a memory reference instruction is set. Some of the frequent uses of indirect addressing include building or retrieving blocks of data in core memory and
referencing memory locations outside of the page or bank containing the program.

The following examples illustrate indirect addressing (* Specifies indirect addressing):
PC

Instruction

000200

221111

(LAC*01111)

The instruction fetched from location 000200 specifies “load the AC with the contents of the memory
location specified by the contents of 01111 (located in page 0 of bank 0).” If location 01111 contained
000300, the EFA would be 000300, and the contents of 000300 would be loaded into the accumulator.

Indirect addressing enables the user to reference any memory locations in core, depending on the
setting of the MPU. In the above example, memory location 300 can be referenced in any memory
page by specifying the page in address bits 3,4, and 5:
PC

Instruction

000200

221111

(LAC*01111)

If location 01111 contains 070300, the contents of location 300 in page 1 of bank 3 are loaded into the
accumulator.

Auto-Increment Addressing, Type III - Bank or Page Mode

Whenever addresses 000010 through 000017 are indirectly referenced by an instruction, the content of
the location is incremented by one before it is used as the operand. The auto-increment feature is
performed only when the location is referenced indirectly. The locations act as any other memory
location when referenced directly.

An auto-increment operation can be initiated from any page, bank, or block of memory. The XVM
auto-increments whenever a memory reference instruction specifies indirect addressing, and the
address points to any location from 000010 through 000017.
NOTE

The Auto-increment register is incremented before
the content is used as the operand address.

Programming examples:

Auto-increment from page 0, bank 0, block 0, and read the data word stored in location 001000 into

the accumulator.

Step 1

Set the Auto-increment register to the operand address value -1. In this case,

000777.

Step 2

Reference the Auto-increment register with indirect addressing specified.

Step 3

The Auto-increment register increments by one, and the EFA is now the new

value (001000) in the register.

1-14

Steps 1, 2 and 3 are represented in assembly language form as:
Step 1

LAC
DAC
LAC*

K777

000777

/Auto-increment register 10
/C(001000) loaded into AC

10
10

/Constant for initialization

When operating from a memory bank other than bank 0, the initial contents of the Auto-increment

register must be set up using indirect addressing. If direct addressing is used, locations 10 through 17 of
the bank containing the program are referenced. For example, if operating in bank 2, Step 1 in the
previous example must be modified as:

Step 1

Step 2, 3

LAC
DAC*

K777
K10

/Deposit in location 10 of 1

LAC*

/page 0, bank 0
/C(001000) loaded into AC

K777

000777

K10

000010

/These constants are located
/in the same memory bank as

/the main program

Indexed Addressing, Type IV - Page Mode Only
The XVM Central Processor has an 18-bit Index register (17 bits + sign) and an 18-bit Program
Counter with appropriate data paths and adder circuitry to compute 17-bit effective addresses.
Indexed addressing can only be used in Page mode operation and is indicated when bit 5 of a memory
reference instruction is set. With this type of addressing, the user gains access to 131,071 memory
locations (000000 through 377777 octal) without adding an additional memory cycle to compute the
effective address (as does indirect addressing).

The following example illustrates indexed addressing:

PC=003000

XR=000100

LAC
|

100,X

/(210100 octal)

The instruction fetched from location 3000 specifies “load the AC with the content of the

effective
address calculated by adding PC01-05 (00), the XR (100) and the address field of the instruction
(100).” This results in an effective address of 000200 because:

000100

+000100

000200

(XR)

(PCi—s) + (ADDR)

(EFA)

If operating in an extended memory bank or block, indexed addressing can be used to reference other
pages, banks, or blocks above or below the operating area.

1-15

Programming example:

The program is operating in block 2, bank 0, page 1 and must reference location 1000 in block 3, bank
3, page 1 (location 371000):

PC=213000

XR = 160000

/(211000 octal)

1000,X

LAC

The EFA is calculated in the following manner:
(XR)

160000

(PCi=s) + (ADDR)

+211000

EFA=371000

(block 3, bank 3, page 1, location 1000)

The program is operating in block 2, bank 0, page 1, and must reference location 1000 in block 0, bank
0, page 0 (location 001000):

PC=213000

XR=570000

LAC

(negative value)

/(213000 octal)

1000,X

The EFA is calculated by:
(XR)

570000

(PC,-s) + (ADDR)

+211000

EFA=001000 (block 0, bank 0, page 0, location 1000)
NOTE

The XR contains a negative value. In this case, it is
the 2’s complement value of the current block, bank,
and page. All 18 bits (17 bits + sign) of the XR are
involved when using indexed addressing. The EFA of
the last example can also be calculated in the following manner:

PC=213000

LAC

200,X

/(210200 octal)

XR=570600

570600

+210200
001000

(XR)

(PC,-s) + (ADDR)
EFA

Indirect Indexed Addressing, Type V - Page Mode Only

Indirect indexed addressing is implemented only in Page mode and is indicated when both the indirect
addressing indicator (bit 4) and the indexed address indicator (bit 5) of a memory reference instruction
are set.

1-16

When indirect indexed addressing is indicated, the XVM CPU
first calculates the address indirectly
referenced. This calculation is done in exactly the same manner as
described in the Indirect Addressing

paragraph. The XVM carries the address calculation one step

further, when indirect indexing is speci-

fied. The contents of the Index register are added to the data word which was

The addition (2’s complement) of the XR is always the last step

retrieved indirectly.

to occur (post indexing).

The following example illustrates indirect indexed addressing:
PC=203000

DAC*

XR=000100

100,X

/(070100 octal)

location 200100=007000

The EFA is calculated as:
007000

(contents of location 200100)

+000100

(XR)

007100

EFA

The instruction fetched from memory location 203000 specifies ““deposit
the contents of the accumulator into the memory location calculated by retrieving the contents of memory
location 200100 (location 100 of the current block, bank, and page) and add the contents
of the Index register to the
contents of memory location 200100.”

The indirect address pointer is calculated by appending bits 1 through 5
of the PC to the 12-bit address
(6 through 17) of the instruction word resulting in a 200100 address
pointer. An additional memory
cycle is required to retrieve the contents (007000) of memory location 200100.
The contents of the XR
are then added, resulting in a final EFA of 007100.
Auto-Increment Indexed Addressing, Type VI - Page Mode Only
Auto-increment indexed addressing can be implemented only when operating
in Page mode. This type
of addressing is specified when the indirect address indicator (bit 4) and the
indexed address indicator
(bit 5) of the memory reference instruction are both set and address bits 6 through
17 equal a value of
10 through 17 octal.
When this type of addressing is specified, the XVM CPU performs the following
EFA:

steps to calculate the

The contents of the Auto-increment register are retrieved, incremented by
one, and then
restored in the register.

The new contents of the Auto-increment register are used as an address pointer.

The contents of the XR bits 0 through 17 are added (2’s complement) to the address pointer.

The sum is used as the final, or effective address (EFA).

The following example illustrates this type of addressing:

PC=170245

/(070015 octal)

15,X

DAC*

000015=000777
XR=001000

Following the procedure given above, the EFA is calculated as:

000777

contents of location 15

)

increment

+ 1
001000

002000

Step 1

new contents of location 15
used as address pointer

+001000

contents of XR

Step 3

EFA

Step 4

the XVM CPU.
All of the foregoing assumes that the MPU does not modify the address received from
modes.
mapping
address
different
in
MPU
A small program is used to illustrate the effects of the
Relocation Register = 000000
FADD
LAC
BEGIN
500
,

DAC

ILOC

DACH*

ILOC

JMP

-2

LAC

ISZ

ILOC

Boundary Register = 000000
Share Register = 000000

User Mode* Share Mode*
G-Mode =0

HLT

:
511

FADD

ILOC
K

000600

000000
252525

Direct Mapping (DMAP)

location until
In DMAP, the constant K is deposited first in location 600s, and then every succeeding+1,
the system
location
last
the
access
to
attempts
the system runs out of memory. When the program
or both
one
in
pointer,
A
on.
is
Enable
Interrupt
Program
if
Og
or
will TRAP to location 205 absolute,
s.
condition
type
“alarm”
the
handle
to
routine
service
a
to
of these locations, should point
Relocated Mapping (RMAP)

Relocation Register = 007400
Boundary Register = 020400

Share Register = 000000

User Mode = 1

Share Mode = 0
G-Mode =0

RDIS =0

In RMAP, the first real address to have the consta
nt deposited in it would be 010200 (FADD + RR).
The system will then continue depositing the consta
nt in sequential locations until it attempts to access
location 020400 (virtual), at which point the system
will be interrupted by the Boundary Violation
which causes a TRAP to 0 or 20s.
Shared Mapping

(SMAP)

Relocation Register = 010400
Boundary Register = 0170400
Share Register = 340000
G-Mode = 3

User Mode = 1
Share Mode = 1
RDIS =0
SLR =2

In SMAP, the first address to be accessed would
be 011200 (Figure 1-16). The system will then continue to deposit until the virtual address 160000 is
produced. This will be changed to 010400 and the
constant will be stored in the subsequent 377;
locations. The address was changed because the
address
160000 corresponds to the first address of the ISAS.
The next significant address will be 160400 which

is the first address in ESAS. The address will be modifi
ed from 760400 to 340400. This will continue
until the end of ESAS is reached by address 167777
(virtual) which is 347777 (real). The next location
(170000 virtual) will be relocated to 200400 (real)
which will cause a trap because it is above the
Boundary register.

377777

ESAS 340400

200400

LAST ESAS +1170000

FIRST ESAS160400

2
FIRST ISAS-

160000

1
11200

2
ISAS-10400

FIRST
STORAGE-600

PROGRAM
ADDRESS-500

VIRTUAL MEMORY

REAL MEMORY
15-0838

Figure 1-16

Shared Mapping Example

The program runs as it would normally in
The BMAP case is less complex than RMAP orto SMAP.
s of the
d ensure that they are greater than the content
DMAP except all virtual addresses are checke
n
locatio
of
s
content
Boundary register. Therefore, if the Boundary register was set at 001400, then the
Boundary Mapping (BMAP)

FADD (000600) must be changed to 001400 or greater before the system will execute the progra

without trapping.

MEMORY

UNIBUS
UNIBUS

PERIPHERALS

PERIPHERAL

PROCE SSOR

PROCESSOR
MEMORY

I/0 BUS
FLOATING

CENTRAL

POINT
PROCESSOR

PROCESSOR

I/0 BUS

PERIPHERALS
15-0983

1.3

INPUT/OUTPUT PROCESSOR

SUMMARY OF CHARACTERISTICS

The 1/0 processor contains two subunits, the data channel controller and the addressable 1/O bus.
Data Channel Controller

Data Transfer Modes - Single and multicycle block transfer, memory-increment, add-to-memory
Real-Time Clock - KW15

Addressable 1/0 Bus

Features — Two-cycle skip line, program interrupt, console terminal interface
Data Transfer Modes - Program-controlled data transfers

Device Ports - A maximum of 50 physical ports shared between the data channels and the addressable
I/0 bus
API - Eight levels of automatic priority interrupts — Four hardware levels and four software levels
I1/0 PROCESSOR

18 bits of parallel
The 1/O processor contains the control logic and registers necessary to transfer up tothe
I/O processor

data on a common bidirectional I/O bus. Data may be transferred directly between
are
and memory, or between the I/O processor and the accumulator (AC) of the CPU. All transfers
I/O
The
memory.
and
s
processor
of
autonomy
complete
providing
made on a request/grant basis,

processor operates with a 1 us nominal cycle time.

While transfers are being made between memory and the 1/O processor, the CPU is free to operate
independently. Requests from the I/O processor for memory access are; however, given priority over

CPU requests by the memory bus switch; this can cause the CPU an occasional “cycle-stealing” delay.

The structure of the 1/O processor provides the following benefits to the user:

Simultaneous data transfers and CPU computing permits high speed processing to meet the
demands of real-time applications.

1-20

User-designed or special-purpose equipment can be easily and inexpensively interfaced to
the system.

Synchronous and asynchronous devices can be handled with equal ease.

Direct memory access devices that would otherwise require additional interface logic require
only one interface with the XVM single cycle data channel.

Modes of Data Transfer
Peripheral devices may transfer data in any one of three modes: single cycle block transfers, multicycle
block transfers, and program-controlled transfers.
Block Transfer Controller

The block transfer controller implements the first two modes of data transfers, and in addition, has an
add-to-memory mode and an increment memory mode. The real-time clock is also implemented in this
section.
'
Multicycle Block Transfers

A 2-word packet in core memory is reserved for each of these channels: locations 22 and 23 for the
first, 24 and 25 for the second, 26 and 27 for the third, and 30 and 31 for the fourth and so on in
standard software systems. The two words in the packet are used to store the “word count” (WC)
(number of words to be transferred in the block), and the “current address” (CA) (where the data is to
be transferred). The I/O processor contains the control logic and an adder to automatically fetch,
increment, and replace the contents of the two locations.
Data is read into memory and out from memory in three I/O processor cycles. Maximum input rate is
170,000 words/second and maximum output rate is 130,000 words/second.
Prior to initiating a multicycle block transfer (flowcharted in Figures 1-17 and 1-18), the program
stores the 2’s complement of the word count and the current address minus one in the two appropriate
memory locations. The transfer is then initiated by an IOT instruction. During the first cycle, the
contents of the Word Count location are incremented by one and restored. During the second cycle,
the current address is incremented by one and restored, in addition to being transferred to the memory.
During the third cycle, the actual data transfer occurs.
The 1/0 processor continues to transfer data sequentially until the Word Count register reaches 0, at
which time an interrupt is generated to notify the monitor that the block transfer is complete. Because
these multicycle block transfers are completely automatic and do not require any CPU attention
except for I/O transfer initialization, the CPU is free to compute while they are taking place. The only
limitation on simultaneity lies in the sharing of memory. The I/O processor has first priority on
memory requests and effectively ““locks out” the CPU for three cycles. As data transfer rates approach
maximum, the CPU can be completely locked out.

Figure 1-19 illustrates how the data channel controller registers implement the multicycle transfers.

1-21

CENTRAL PROCESSOR
PROGRAM INITIALIZES

WORD COUNT AND
CURRENT ADDRESS
LOCATION

PROGRAM INITIALIZES

DEVICE

8 STARTS DEVICE

WITH INSTRUCTIONS

WHEN DEVICE

NEEDS DATA A

—

REQUEST IS
PLACED ON THE 1/0
BUS

1/0
PROCESSOR
WHEN THE [/0 PROCESSOR IS READY
A
GRANT IS ISSUED
TO REQUESTING
DEVICE

THE DEVICE
SUPPLIES THE ADDRESS OF THE WORD

COUNT, PROCESSOR
ASSIGNS NEXT
ADDRESS AS CA.

THE 1/0 PROCESSOR
FETCHES, INCRE -

MENTS, & REPLACES
THE WORD COUNT

|
IF WORD

COUNT

OVERFLOW, THEN AN

“|OVERFLOW IS SENT
TO DEVICE

DEVICE CLEARS ITS
ENABLE AFTER
CURRENT WORD
HAS

BEEN

TRANSFERRED

THE 1/0 PROCESSOR
FETCHES, INCREMENTS,
8 RESTORES THE
CURRENT

ADDRESS

‘

THE I/0 PROCESSOR
FETCHES DATA
SPECIFIED BY THE CA,
PLACES IT ON THE
BUS

THE DEVICE STROBES
THE DATA INTO ITS
REGISTER

!
SETA PROGRAM
INTERRUPT TO
INDICATE DONE

1S
DEVICE
STILL ENABLED
?

YES

cPu_y

PROGRAM INTERRUPTED & NOTIFIED
THAT DEVICE IS
DONE
15~-0859

Figure 1-17

Multicycle Out Block Transfer Flowchart

1-22

CENTRAL PROCESSOR
PROGRAM INITIALIZES
WORD COUNT AND
CURRENT ADDRESS
LOCATION

PROGRAM INITIALIZES
8 STARTS DEVICE
WITH INSTRUCTIONS

L_
170 PROCESSOR
WHEN THE I/0 PRO-

DEVICE
WHEN DEVICE HAS
DATA READY
*1A REQUEST

IS PLACED
ON THE I/O BUS

]

CESSOR 1S READY
A
GRANT 1S ISSUED
TO REQUESTING
DEVICE

THE DEVICE
SUPPLIES THE ADDRESS OF THE WORD

COUNT, PROCESSOR
ASSIGNS NEXT
ADDRESS AS CA,
r

THE 1/0 PROCESSOR
FETCHES,INCREMENTS, & REPLACES
THE WORD COUNT

IF WORD COUNT
OVERFLOW, THEN AN
OVERFLOW IS SENT
TO DEVICE

DEVICE CLEARS ITS
ENABLE AFTER
CURRENT WORD
HAS

BEEN

TRANSFERRED

THE 1/0 PROCESSOR
FETCHES, INCREMENTS,
8 RESTORES
CURRENT

THE

ADDRESS

THE 1/0 PROCESSOR
TAKES DATA FROM
DEVICE AND

STORES IT IN
MEMORY LOCATION
SPECIFIED BY CA

DEVICE
STILL ENABLED
?

SETA PROGRAM
INTERRUPT TO
INDICATE DONE

ceu
¢
PROGRAM INTERRUPTED & NOTIFIED
THAT DEVICE IS
DONE

Figure 1-18

15-0004

Multicycle Transfer Implementaion

1-23

TO MEMORY PROCESSOR SWITCH

|
MEMORY BUS

r—|\------—-—————————--"———-- [

I
|

|
|

STORAGE
REGISTER

— |—
|—

]

GRANT

L—

I
|

1/0 ADDER

MIXER LOGIC

'
|

REQUEST

}

—

REQUEST/

—

GRANT

LOGIC

CENTRAL
PROCESSOR

[— — |[— — — — —

‘___I

|
|
|

|
|

BUS BUFFER

|
|

170
PROCESSOR

ke e e e e e |

170 OFLO

MEMORY

—

FROM
170 BUS

ADDRESS

TO/FROM BIDIRECTIONAL
1/0 BUS DATA LINES

LINES

DATA
CHANNEL

GRANT

|
|
|

_ _SUBSYSTEM|

DATA
CHANNEL

REQUEST

TO
1/0 BUS
15-0005

Figure 1-19

Multicycle Transfer Implementation

1-24

Assume the 2-word core memory packets assigned to a given multicycle data channel have been loaded
by the respective 1/O service routine. For the case of data input to memory, the following occurs:
1.

An instruction from the service routine enables the device controller. This allows the controller to request a data transfer from the I/0 processor.

When the device controller’s data buffer registers are full, it issues a ““data channel request.”

The I/O processor, if not busy, acknowledges the request by returning a ‘“data channel
grant.”

The device controller then generates a fixed code pointing to its packet address in core
memory. This is transmitted over the common I/O bus address lines and is stored in the
Data Storage register of the data channel controller through the 1/O adder. The adder is
inhibited during this operation.

The I/O processor then generates a “memory cycle request.”

The address data on the I/O bus address lines points to the word count, the first word of the
packet. This data is brought out of memory and into the data channel controller’s adder.
The word count data word is incremented by one and stored back into memory. If, during
this incrementing, the adder overflows (indicating that the current address is the last), then
an I/O overflow pulse is transmitted back to the device to disable future data channel
requests from the line and also to post an interrupt to the monitor, when the DCH transfer is

completed.

This “word count” operation occurs in one I/O processor cycle, using one memory cycle.
During the second I/O processor cycle, the fixed address from the device controller is gated through

the adder and is incremented by 1. It points to the second word in the packet, the “current address,”
which is then transmitted back to the adder, incremented by 1, and strobed back to memory.
During the third I/O processor cycle, the contents of the “current address” location is strobed to the
memory to point to the data array word where the I/0O data will be transferred. The data is then gated
from the device controller, through the adder (which is inhibited during this cycle), and into memory.
Data output follows the same sequence (Figure 1-19) with the exception that one additional 1/0
processor cycle is required to allow the bus to settle after data is strobed out of memory and into the
device.

Single Cycle Block Transfers
Single cycle block transfers, flowcharted in Figure 1-20, are used by high-speed peripherals that normally transfer complete records (blocks) of information, such as disks and video devices. A single cycle
of the I/O processor takes approximately 1 us, allowing a maximum transfer rate of up to one million
18-bit words per second.
High-speed hardware registers, designed into the device controllers of the high-speed peripherals, store
the “current address” (the memory cell where data is currently being transferred), and the “word
count” (the number of words remaining to be transferred in a block). These registers are loaded by
input/output transfer (IOT) instructions issued by the CPU. Device testing and initialization are handled by the CPU via IOTs to provide supervisory control. A subsequent IOT initiates the data transfer.
The I/O processor uses the current address information to address core memory, then strobes the data
between memory and the device controller. Logic within the device controller then increments the

Current Address register and the Word Count register to provide sequential block transfer.

1-25

cPU

PROGRAM INITIATES]
WORD COUNT(WC) &

CURRENT ADDRESS

DEVICE

(CAYTHEN ENABLES

THE DEVICE

DEVICE POSTS A
SINGLE CYCLE REQUEST WHEN
READY

1/0 PROCESSOR

DATA CHANNEL
GRANT IS ISSUED

WHEN 1/0 PROCESSOR IS READY

DEVICE SUPPLIES

CURRENT ADDRESS
» AND DATA TO I1/0
BUS, THEN INCRE
MENTS

ITS WORD

COUNTS AND C.A.
l

DATA CHANNEL
CONTROLLER RE-

QUESTS MEMORY
AND SUPPLIES
CURRENT ADDRESS

STOP NEXT REQUEST

AND DATA IN

IF WORD COUNT

SEQUENCE

OVERFLOWS

END OF BLOCK
TRANSFER
15-0006

Figure 1-20

Single Cycle Block Transfer Flowchart

When the Word Count register overflows at the end of a block transfer, an interrupt is generated to
allow the monitor system to take further action. Typically, this action will include deselecting the
device from the 1/O bus or reloading the device controller registers for another block transfer. The
maximum number of words that may be transferred in a single block is determined by memory size
and device capacity.

Figure 1-20 illustrates how the data channel controller registers handle single cycle transfers.

Assuming that the program has initiated the word count and current address of the device controller,
and has then enabled it, the following occurs:

The device controller sends a single cycle data channel request to the I/O processor.

TheI/O processor, as soon as it becomes available, acknowledges the request by returning a

The device then strobes both its current address and its data onto the I/O bus to the I/O

“data channel grant” signal.

processor.

The data channel controller feeds the current address through its adder (which is inhibited
throughout the single cycles) to the Data Storage register. A memory cycle is requested, and
this address is strobed into a memory bank’s address buffer. The data is then strobed off the
18 I/O data lines and into the memory location specified by the current address.

1-26

During this operation, the device increments its own word count, and disables itself on
overflow. It then posts an interrupt to the monitor to indicate that its operation has been
completed.

Burst Mode
The usual method of data transfer is one word per data channel request, whether it is single cycle or
multicycle; however, there is one special case.

If the data channel request signal should remain true at the end of the first word (i.e., the device holds
it so), then the data channel controller will go into Burst mode (also known as Back-to-Back).
Once in this mode, the CPU is held “locked-out” until the device drops the data channel request
signal, and the I/O transfer is completed. This mode will transfer one 18-bit word approximately every
microsecond. This mode is only used by certain devices that can handle the 1 MHz rate.
Increment Memory
The Increment Memory mode allows an external device to add one to the contents of any memory

location in a single cycle; this feature is most commonly employed in the accumulation of data in
histogram form. Effectively, the Increment Memory mode simply goes through the word count cycle
of a multicycle channel transfer, and then stops. The maximum rate at which it can increment is 333
kHz. This feature is particularly useful for in-core scaling and counting in pulse height analysis.
Add-to-Memory
Add-to-memory is a standard feature of the XVM that adds unique capabilities to the already powerful I/0 facilities. In Add-to-Memory mode, the contents of an external register can be added to the
contents of a memory location in four cycles. This feature is extremely valuable in signal averaging and
other processes requiring successive sweeps for signal enhancement.
The add-to-memory operation is a combination of multicycle data channel input and multicycle data
channel output operations. The data transmitted by the device is added to a word read-out of memory
as specified by the current address, and the result is rewritten into the same location. It is simultaneously transmitted to the device via the I/O bus. The maximum add-to-memory rate is 130 kHz.
KW15 Real-Time Clock
When enabled, the KW15 Real-Time Clock counts, in memory location 00007, the number of cycles

completed by the line voltage (50 or 60 Hz) or any standard DEC clock module that may be optionally
installed. Maximum recommended clock frequency is 10 kHz.
When location 00007 overflows, an internal program interrupt (or API request, if available) is generated, informing the monitor that its preset interval is over. The monitor must either disable the clock
or reinitialize location 00007 to the 2’s complement of the number of counts it needs to tally.
The incrementing of location 00007 during a real-time clock request occurs via the I/O processor’s
increment memory facility. A real-time clock request takes priority over API, PI, and IOT requests,
but not over block transfers (DCH).
ADDRESSABLE I/0 BUS
The addressable 1/O bus implements the program-controlled transfers. It also contains the program
interrupt and the automatic priority interrupt (API) feature.

1-27

Program-Controlled Transfer

Program-controlled transfers, implemented by input/output transfer (IOT) instructions, can move up
to 18 bits of data between a selected device and the accumulator (AC) in the CPU. The devices
involved are connected to the addressable I/O bus portion of the I/O processor. A total of up to 50
device controllers may be attached to this bus and to the data channel. IOT instructions are microcoded to effect response only for a particular device. The microcoding includes issuing both a unique
device selection code and the appropriate processor-generated input/output pulses to initiate a specific
operation. For an “output” transfer, the program reads a data word from memory into the AC. A
subsequent IOT instruction places the data on the bus, selects the device, and transfers the data to the
device. For an “input” transfer, the process is reversed; an IOT instruction selects the device and
transfers data into the AC. A subsequent instruction in the program transfers the word from the AC to
memory. Maximum transfer rate in this mode is about 50 kHz.

IOT instructions are also used to initialize the single and multicycle channels and the transfer word
count and current address information to the single cycle device controllers. In addition, these instructions are used to test or clear device flags, select modes of device operation, and control a number of
processor operations. An IOT instruction, Figure 1-21, contains the following information:
a.

An operation code of 70s.

An 8-bit device selection code to discriminate between up to 256 user peripheral devices
(selection logic in a device’s I/O bus interface responds only to its pre-assigned code). In
normal practice, bits 6 through 11 perform the primary device selection between up to 64
device codes. Bits 12 and 13 are coded to select an operational mode or subdevice.

A command code (bits 14 through 17) capable of being microprogrammed to clear the AC
and issue up to three pulses via the I/O bus.

—
OPERATION

_J\
CODE: 70

J
DEVICE

SELECTION

J
suB-

DEVICE

SELECTION
CLEAR AC
AT EVENT
TIME 1

GENERATE
I0P2 AT
EVENT TIME
2

GENERATE

EVENT TIME

EVENT TIME
1

I0P4

I0P1

15-0824

Figure 1-21

IOT Instruction Format

1-28

Up to four machine cycles may be required to execute an IOT instruction. These include the IOT fetch
from core memory (memory is not accessed thereafter until completion of the IOT), and three sequential cycles designated event times 1, 2, 3 (IOP 1, 2, and 4) (Figure 1-22). In IOT skip instructions,
however, only IOP1 is used. These are 2-cycle instructions. Bits 14 and 17 can be coded to initiate
clearing of the AC and generation of an IOP1, respectively, during event time 1. Bits 16 and 15 can be
coded to initiate generation of an IOP2 and IOP4 pulse during event times 2 and 3, respectively. IOT
skip instructions are microprogrammed to produce an IOP1 pulse for testing a device status flag. IOP2
pulses are normally used to effect programmed transfers of information from a device to the processor.
Because the AC serves as the Data register for both “input” and “output” transfers, the “clear AC”
microinstruction (bit 14) is usually microprogrammed with the IOP2 microinstruction; this combination effects clearing the AC during event time 1. IOP4 pulses are normally used to effect programmed transfers of information from the AC to a selected device. These conventions do not, however,
preclude use of the IOP pulses to effect other external functions if the following restrictions are

observed.

0-60NS MAX.—

CP RUN

|
-+

FETCH

10T REQ.

10T

10T SYNC

|e60NS

-»| |=-160NS MAX.

800 Ns——|\ e

[«

——|\|<—)o TO 1 pSEC
M-~

—»I

I
I

10P 1

|
|

fe-250 NS
|

[

10P 2

10P 4

\
)

fe 1 pSEC
N

-\
4

=1 pSEC

\|<—-500NS/

10T DONE

|
I

I
AC ON BUS

[

]
15-0176

Figure 1-22

10T Instruction Timing

1-29

The uses of IOPs are:

IOP1 - Only used in an I/O skip instruction to test a device flag.

IOP2 - Usually used to transfer data from the device to the computer, or to clear device’s Information

IOP4 - Used only to transfer data from the computer to the device. May not be used to determine a
“skip” condition or to transfer data to the computer.

PROGRAM INTERRUPT FACILITY

The program interrupt (PI) system, standard on all systems, provides for servicing a peripheral device
at rates up to 20 kHz. The program interrupt (PI) facility, when enabled, relieves the main program of
the need for repeated flag checks by allowing the status of 1/O device flags to automatically cause a
program interrupt. The CPU can continue with execution of a program until a previously selected
device signals that it is ready to transfer data. At that time, the program in progress is interrupted and
automatically the contents of the program counter (15 bits), User/Exec mode (1 bit), bank or page
addressing mode, and the link bit (1 bit) is stored in location 000000 (Figure 1-23).

J
PC CONTENTS

LINK

CONTENT

STATE

(RETURN ADDRESS
)

USER MODE

(PROTECT)

1=BANK
0= PAGE

MODE
MODE
15-0823

Figure 1-23

Memory Location Just After

a Program Interrupt

The instruction in location 000001 is then executed, transferring control to an I/O service routine for
IOT instructions. When completed, the routine restores the system to the status prior to the interrupt
with a single instruction, allowing the interrupted program segment to continue. Where multiple peripherals are connected to the PI, a search routine containing device status testing (skipping) instructions must be added to determine which device initiated the interrupt request. The program interrupt
(PI) control is enabled or disabled by programmed instructions (IOTs). When disabled, the PI ignores
all service requests, but such requests normally remain on-line and are answered when the PI is enabled
again, unless they are cleared.

Mnemonic
ION
I0F

Octal
700042
700002

Code Function
Enable the PI
Disable the PI

The PI is automatically disabled when an interrupt is granted or when the RESET key (on the console)
is pressed. The PI is temporarily inhibited while the automatic priority interrupt system is processing a
priority interrupt request. The PI Enable indicator (PIE on the console) is lighted while the PI is
enabled.

1-30

Free Instruction
When a program interrupt has been accepted, one “free instruction” follows. Simply, this means that
program interrupt enable is turned off to prevent another program interrupt from occurring while the
hardware is transferring control from one program to the interrupt service routine.
Conditional Skip-On Device Status
The XVM order code includes a group of instructions for testing the status of peripherals. Instructions
of this type direct the processor to skip the next instruction if the tested condition is true. This group of
instructions allows the test of peripheral devices at the programmer’s option. Normally, rather than
tying the processor up in a ‘“‘wait”” loop, the device signals that its buffer is ready by generating an
interrupt. If it is a program interrupt, the “‘conditional skip” is used in a *“skip chain” to find which
device initiated the interrupt. Each skip instruction takes an average of 1.8 us.

COMMON I/0 BUS
The I/O processor contains a common 1/O bus (Figure 1-24) to transfer both data and IOT instruc-

tions to the block transfer channels and to the addressable 1/O bus. The bus is the major communication path for I/O devices. It consists of cables that link all the I/O device controllers to a common
interface point at the I/O processor. All signal lines for command and data transmission arising from
the data channels, addressable 1/O bus, operation of the multi-level automatic priority interrupt system, program interrupt, I/O status read, and I/O skip facilities, are contained on this bus. The bus
length can be up to 75 ft.
Data Lines
Eighteen data lines constitute the bidirectional facility for transferring data bytes of up to 18 bits

between the I/0 processor and all I/O devices. Transfers are made on a dc basis with the processor or
device allowing bus settling time before data on the lines is strobed into the receiving register. The data
lines convey data between the Memory Buffer register and a selected Device Buffer register for block
transfer channel operation; they transfer data between the accumulator and a selected Device Buffer
register for program-controlled transfers.
Output Control Signals
Eight output control signals are generated to effect specific functions in a selected device.
I/0 Power Clear
The I/O power clear signal resets all flip-flops storing device-to-processor flag indications (e.g., ready,
done, busy). It is generated when power is turned on and off, the occurrence of a clear-all-1/O flags
(CAF) instruction, and by actuation of the RESET key on the control console.
I/O0 Sync

I/O sync is used to synchronize I/O device control timing to the processor.
I0P1, I0P2, IOP4
Microprogrammable signals are used to effect IOT instruction-specified operation within a selected

I/O device. The I1/O processor generates IOP2 or IOP4 for data channel input or output transfers. The
uses of the IOPs are:
IOP1 - To test a device flag (in an I/O skip instruction). It may not be used as a command pulse or to
initiate loading, reading from a Device Buffer register.

IOP2 - To transfer data from a selected device to the processor or load a device. Not used for skip.
IOP4 - To transfer data from the processor to a selected Device register. It may not be used to
determine a skip condition or to transfer data to the processor.

1-31

BIDIRECTIONAL

DATA

TRANSFER LINES (18)
————————— /0 POWER

CLEAR ————

1/0 SYNC PULSE —————
10P1

oP2

10P4

READ STATUS —————
TM
I/0

OVERFLOW

————

PROGRAM INTERRUPT
REQUEST

READ

OXTMH

¢ SKIP REQUEST
REQUEST

le————— INCREMENT

—< MO

[e—WRITE REQUEST

CURRENT ADDRESS
INHIBIT INCREMENT
DEVICE SELECTION
LINES
(8)

<¢————— ADDRESS LINES

DOLMLMO
OD TV

O\ H

———

(15)

le——— API REQUEST LINES (4)
API GRANT LINES(4) —TM

——— API ENABLE LINES(4)————m
a———DATA CHANNEL REQUEST
DATA CHANNEL GRANT—%¢

DATA CHANNEL ENABLE——TM

[/0 RUN ~———em—————]
DATA OVERFLOW —TM

pe———

SINGLE CYCLE REQUEST
15-0007

Figure 1-24 Common 1/O Bus

Input/Output Read Status

The input/output read status facility provides for programmed interrogation of the status of those
external devices using this facility. Upon execution of an input/output read status (IORS) instruction,
the states of those device flags (Done, Busy, Not Ready, etc.), interfaced to this facility by the I/O bus,
are transferred to specific assigned bit positions of the AC. This allows the program to check for
specific flag conditions or display the flag states on the operator’s control console. Figure 1-25 shows
the bit positions associated with the commonly interfaced flags. The IORS word can contain up to 18
flag bits. Those bits not used are zeroed. The presence of a flag is indicated by a 1 state in the corresponding AC bit.

Switching the REGISTER DISPLAY control (on the console) to the Status position simulates execution of the IORS instruction (with the processor in the “program stop”” condition). The contents of the
IORS word (i.e., the states of the device flags) are displayed in the REGISTER indicators (on the
console) at this time.

1-32

REAL
TIME

PROGRAM

TAPE

CONSOLE

CLOCK

INTERRUPT

TAPE

PUNCH

PRINTER

OVERFLOW

READER

FLAG*

TAPE

FLAG*

NO TAPE»*

FLAG*t

—r—

—r

FLAG*

—r—

—A—

DEC

—A—

DISK

LINE

PACK*

PRINTER*

—A—

TAPE

CONSOLE

LIGHT

REAL-

READER

TAPE

KEYBOARD

MAG

PEN

TIME

PUNCH

FLAG*

TAPE %1+

CLOCK

NO PUNCH

DISPLAY

ENABLED

—r—

17-

DEC

RESERVED FOR

DISK

SPECIAL USERS

FLAG®

DEVICES

FLAG*

LEGEND:
* will cause
a program interrupt

*tt
®%

Inclusive OR of transfer completion and error Flags
Inclusive OR of MTF and EF
Will cause an interrupt via the RDR Flag
15— 0981

Figure 1-25

1/0 Read Status Bit Assignments

I/0 Overflow
I/O overflow is issued during the first cycle of the block transfer operation
if the contents (2’s complement) of the word counter assigned to the currently active channel
device becomes 0 when
incremented. This indicates that the program-specified number of words will have
been transferred at
completion of the channel transfer in progress. It is normally used to turn
off the device, thereby
preventing further channel action by that device until a service subroutin
e reinitializes the channel’s
word counter and Current Address registers, and the program turns
on the device request flag. The
overflow signal may also be used to initiate a program interrupt through
the program interrupt or
automatic priority interrupt facility for access to the initializing subroutine
. Additionally, I /O overflow occurs when an 1/0 increment memory operation causes the location
to overflow.
Data Overflow
Data overflow is issued during the third cycle of a four-cycle add-to-m
emory data transfer when the
addition operation generates an arithmetic overflow.

Input Control Levels

Six input control level signals arrive at the I/O processor:
Program Interrupt Request — A device delivers this signal to request

interruption of the program in

progress. The program traps to location 00000 when no I/O transfer
action of higher priority is in
progress. The instruction resident in location 00001 is fetched
and executed. If more than one device is

connected to the program interrupt, this instruction transfers control to

a subroutine, which deter-

mines through a search process (skip chain) the device making the program

appropriate service routine is then accessed.

interrupt request. The

Skip Request — The return of this signal to the processor indicates that
an IOT instruction test for a
skip condition in a selected device has been satisfied (e.g., a test of ready
status). The program counter
is subsequently incremented by one to effect a skip of the next instruction
of the program in progress.
Read Request - This signal is used by the device to specify to the I /O
processor that an input to the
CPU data transfer is required.

1-33

Write Request — This signal requests that the processor execute a data-channel-write transfer of a data

word into the selected device’s Information register.

MB Increment - This level requests that the processor increment (by one) the contents of the memory
location address specified by the 15-bit address on the I/O bus address lines. Used in increment memo-

ry operation.

+1 to CA Inhibit - This is a special signal line required by devices that automatically search for
records, etc.; typical are DECtape and magnetic tape. The presence of this signal level inhibits normal
incrementing of the device assigned Current Address register during a data channel transfer.
Device Selection Levels — Identification of the current instruction as an IOT causes the bit pattern
placed in the CPU MI 06 through 13 at the fetch of the instruction to be bus-driven and sent via eight
bus lines to device selection modules contained in the control logic for each device. These eight levels
form a 6-bit device selection code and 2-bit sub-device or mode selection code.
Address Lines

Fifteen lines constitute an input bus for the devices which must deliver address data to the processor.

There are three uses for the address bus:

When a device interfaced to the multi-level automatic priority interrupt system receives an
1/0O processor grant of its interrupt request, it delivers a hardware-defined address to the
CPU, relating to its API channel assignment. This channel address indicates the location of
the pointer to the device’s service routine.

When a block transfer channel device receives a processor grant of its transfer request, it
delivers to memory a hardware-defined address indicating the assigned channel’s word
count location.

A single-cycle data channel device delivers a 15-bit address plus two dual purpose lines for
17-bit 131072 accessibility. The dual purpose lines are SKP REQ and WRT REQ as address
bits 01 and 02, respectively.

Multiplexed Control Lines

Sixteen control lines serve as processor-to-device control information paths, four for the block transfer

channel facility and twelve for the priority levels on which the automatic priority interrupt system
processes requests for service. Control lines are used in the following ways:

Request — A device transmits a service request to the processor via the appropriate request line. There
are four automatic priority interrupt request lines (one for each level) and two data channel request
lines (single cycle requests and multicycle requests).

Grant — The processor indicates a grant of the service request. There are four API grant lines (one for
each hardware level) and one data channel grant line to answer both single and multicycle requests.
Enable - The enable signals control the priority order for answering service requests of devices interfaced to the block transfer data channel or to one of the API’s device channels. Priority for a channel
(data or API) is allocated in descending order from the device nearest the processor I/O bus interface.
An enable signal permits servicing the requesting device with the highest priority and inhibits all lower
priority devices from making requests during the interval of service. The enable signals are the only
1/0 signals that are actually broken and regenerated by each device on the associated channel.

1-34

I/0 Run
The I/O Run signal is available at the interface for use as the interface designer requires. This busdriven level switches to the +2.5 V level and remains there while the 1/O Run flip-flop in the CPU is
set. A ground level indicates that the RUN flip-flop has been cleared, and all operations in the CPU
have been stopped.

Console Device Interface
The 1/0 processor includes a console terminal and the interface as standard I/O equipment. See Table
1-1 for devices that operate with this interface. The console terminal transmits and receives an 8-level
ASCII code over a 4-wire cable connecting the terminal to its interface in the 1/O processor.
Table 1-1
Interface Devices
Terminal Type

DEC Type No.

Baud Rate (max.)

LT33
LT35

110
110

Teletype®
Teletype

DECwriter
DECwriter 11

LA30

300

LA36

Alphanumeric terminal
DECscope

300

VTO0S
VTS52

9600

2400

®Teletype is a registered trademark of Teletype Corporation, Skokie, Illinois.

Hardware Read-In

A hardware-controlled read-in facility exists as standard in all systems. It is used with the PC05 HighSpeed Reader and its associated PC15 controller. When a suitable tape is placed in the reader and the
READ-IN key is pressed, the I/O processor instructs the reader to read data from the tape. The I /O

processor assembles the data into 18-bit words and stores them in memory. When the tape is finished,
control is transferred to the beginning of the program to initiate execution.

Priority
In view of the autonomous substructures of the XVM, three types of priority must be considered:
memory access priority, priority on the common I/O bus, and priority on the use of the CPU.

Memory Access — The I/O processor always has priority over the CPU in accessing memory. How-

ever, once a CPU memory request has been granted, it will be allowed to complete its cycle
before

control can be returned to the I/O processor.

Common I/O Bus - Priority on the I/O bus
is of concern only when more than one device is transferring information on the 1/O bus and the I/O bus requests are received by the 1/O processor. The
following order of priority occurs:
1.

Block Data Transfer Channel - This is the highest level of priority on the I /O bus. However,
as it is normally used to transfer only one word at a time, it can operate at very high speeds
without disturbing the other levels of priority. The priority of devices on the Data Channel
are determined by their physical position on the I/O bus.

Real-Time Clock - The real-time clock has priority after the block data transfer channel.
The real-time clock uses the I/O processor to fetch the contents of a reserved core memory
cell (000007s), increment the count, and then restore the new count.

1-35

Automatic Priority Interrupt - The automatic priority interrupt (API) system adds eight
additional levels of priority to the XVM. The upper four levels are assigned to devices and
are initiated by flags (interrupt requests) from these attached devices. The lower four levels
are assigned to the programming system and are initiated by software requests. The priority
network ensures that high data rate or critical devices will always interrupt slower device
service routines while holding off still lower priority interrupt requests until they can be
serviced. The API identifies the source of the interrupt directly, eliminating the need for a
service routine to flag-search.

Program Interrupt - The program interrupt (PI) facility offers an efficient method of 1/0
servicing, if the API system is not used. The computer continues with execution of a program until a previously-selected peripheral device signals that it is ready. At that time, the
program in process interrupts and transfers control to a service subroutine. When completed, the subroutine restores the computer to the status existing prior to the interrupt,
allowing the interrupted program segment to continue. Where multiple peripherals are connected to the PI, a search routine with device status testing (skipping) instructions must be
added to determine which device initiated the interrupt request. The priority is established
by the program skip routine.

IOT’s - Program controlled transfers at the main program level.

CPU - Priority on the use of the CPU is established by the API level, the program interrupt, and the

main program, in that order.
Latency

1/0 transfer latency is a measure of the time between a device’s request for service and the actual
performance of that service. Regardless of a device’s priority, once its request for service has been
granted, the 1/O processor holds all other devices off until the current service request is complete. For
example, a single cycle data channel device requesting service just after the initiation of a multicycle
output transfer would have to wait for four I/O processor cycles before using the I/O bus. Finally,
synchronization can take additional time resulting in a worst case latency of less than 9.9 us for the
requesting single-cycle device.

MEMORY

UNIBUS

PERIPHERALS

UNIBUS
PERIPHERAL
PROCE SSOR

_i>> PROCESSOR
MEMORY

[

<:1

| CENTRAL

PROLESSOR <::
FLOATING
POINT

PROCESSOR

I/0 BUS

::)

1/0 BUS

PERIPHERALS
cP-1888

1-36

1.4

MEMORY

INTRODUCTION

|
The magnetic core memory is the primary storage facility of the XVM. It provides rapid, random
access data instruction storage for both the CPU and the 1/O processor.

Memory Data Transfer
:
The XVM memory communicates with the CPU and the I/O processor through the memory bus. Data
and instruction words of each are read from and written into individual memory cells through a
buffered register referred to as the Memory Data Buffer.

Words in a memory bank are selected according to the address in the Memory Address Buffer.
The 13-bit capacity of the Memory Address Buffer allows 23 or 8192 words to be referenced in each
bank. The Memory A ddress Buffer receives the memory cell address from the CPU or I /O processors.

The address provides the coordinates for locating a word in a memory bank.

The Memory Address Buffer receives the memory cell address from the CPU or I /O processors. The
address provides the coordinates for locating a word in a memory bank.

The XVM systems are provided with two types of memory, designated ME15 and MF15. These are

compact and economical data storage devices, capable of holding up to 131,072 18-bit words. The
MEI15 is built in 8K segments, and the MF15-U in 16K segments: for a fixed memory capacity, (e.g.,

64K) the MF15-U is more economical than the ME15, but does not provide the same interleaving

capacity. It is possible to mix ME15 and MF15-U memories, even on the same output port, but careful
consideration must be given to the configuration to ensure that the facilities of the memories are not
inhibited.

MF15-W memory is also available in later models of XVM systems. This high density memory is
manufactured in 32K units and packs twice the storage capacity of MF15-U memory into the same
mounting space. This allows 64K to be mounted in the XM15 MPU assembly and 128K to be
mounted in the basic XVM cabinet. Except for this increased density and slightly slower operation, the
MF15-W is very similar to the MF15-U memory.

The XM15 unit has sufficient space for 32K of MF15-U, or 24K of ME15 (one has four modules; the
other, three). The rear door of the XVM processor cabinet can accommodate 48K of ME15, or 64K of
MF15-U. If greater memory storage capacity is required, then a separate expansion box must be added
to the system in an extra cabinet which is normally mounted immediately to the left of the XVM
cabinet.
NOTE
The ME1S, MF15-U and MF15-W Core Memories
are current types of memory that will operate on the
output ports of the XM15.

MF15-U General Description
.
This section briefly describes the characteristics of the MF15 Core Memory. The following modules
make up a 16K memory unit, providing storage for 16384 18-bit words:
M8293

16K Timing Module

G114
G235
H217C

Sense/Inhibit Module
X-Y Driven Module
Stack Module

70-09295

Backplane Assembly

1-37

Table 1-2

MF15-U Core Memory, Specification Summary
Magnetic core, read/write, coincident current, random

Type

access

Organization

Planar, 3D, 3-wire

Capacity

16,384 (16K) words

Maximum Access Time and Cycle Time

Bus Mode
DATI

Access Time
425 ns

Cycle Time
1000 ns

DATIP

425 ns

DATO-DATOB

1000 ns

125 ns

680 ns

100 ns

(PAUSE L)

DATO-DATOB
(PAUSE H)
X-Y Current Margins

+6% @ 0° C, 7% @ 25° C, 6% @ 50° C

Voltage Requirements

+5 V £5% with less than 0.2 V ripple

Average Current Requirements

Stand by:

+20 V +£5% with less than +5% ripple
-5V £5% with less than +5% ripple

+5V:

538A-5V:

041A

+20V:05A

Memory Active:

+5V:

6.1 A-5V:

+20V:34A
Power Dissipation (Worst Case):

M8293 Control Module ~7 W

G235 Drive Module ~33 W
H217D Stack Module ~40 W

G114 Sense Inhibit Module ~40 W
Total at Maximum Repetition Rate:
Environment

Ambient Temperature

0° C to 50° C (32° F to 122° F)

Relative Humidity

0—-90% (non-condensing)

1-38

120 W

O0S51A

XMt5 MEM BUS
—

M8293 16K MEMBUS

ADDR.CTRL‘>

TIMING (MAT)

MEMBUS

G114 SENSE INHIBIT (SIN)

INTERFACE

DATA

MEMBUS

INTERFACE

MATE F

SINB-SINF

READ WRITE
INHIBIT
CONTROL
LOGIC

DEVICE
SELECTION

DATA
REGISTER

MATE

SINB-SINF

POWER

ADDRESS

MONITOR &

TIMING

LATCHES

MATJ

BUFFERS
MATB,C,D

MATE,F

SINA

DECODERS
y

X-Y DRIVERS
TIMING 8

8 SWITCHES

DRVA

SENSE

SINB-SINF

AMPS

X-Y DRIVERS

INHIBIT

THERMISTOR

BIAS SOURCE

GENERATOR

DRIVERS

DRVB,C

STACK
CHARGE

CONTROL

CIRCUIT
STKA

DRVB,C

INFIBIT

TERMINATIONS
STKA

CURRENT

SENSE

X-Y DIODE

STROBE
ONROBE

SOURCES

DRVA

MATRIX

DRVA

CORES

STKA,B

G235 X-Y DRIVER (DRV)

H217

STACK (STK)
1-3440

Figure 1-26

MF15-U Simplified Block Diagram

1-39

The Backplane Assembly provides sufficient space to mount two MF15 Units, having a total capacity
of 64K 18-bit words, as shown in Figure 1-26. MF15-U specifications are summarized in Table 1-2.
Functional Description

The MF15-U Memory is a read/write, random access coincident current, magnetic core type with a
maximum cycle time of 980 ns and a maximum access time of 425 ns. It is organized in a 3D, 3-wire
planar configuration. Word length is 18 bits and the memory consists of 16,384 words (normally
referred to as 16K).

The memory can be interleaved in 32K increments for faster operation. Interleaving causes consecutive
bus addresses to be located within alternate 16K memory blocks. The major functional units of the
memory (Figure 1-26) are described briefly in the following paragraphs.
MEI1S5 General Description
The ME15 Core Memory provides the XVM with a compact, economical storage device capable of

storing up to 131,072 18-bit words. The ME15 is mounted on the rear door of the central processor
cabinet and in the XM 15 drawer. The entire memory is enclosed in a cooling box with fans at both top
and bottom. Each of the four logic panels is six module plots high and nine module slots wide. The
ME15 modular complement consists of G109, G231, and H215 modules. Every 8K of installed memory requires one each of the G109, G231, and H215 modules. Figure 1-27 shows the assigned module
slots for one panel.

’—

[1a]

—

x
©
-

—

Zz
<

o
w

2
|

a
|

g
7

g
| «
*
b

I
n

c(\;

>z | B

[

[]
b3

el
o

z
W

G|
2]

o
2

<
©
-

)

15-0860

Figure 1-27

Assigned Module Slots

1-40

Memory Specifications
The general memory specifications are listed in Table 1-3.

Table 1-3

ME1S5 Memory Specifications
Type

Magnetic core, read/write, coincident current, random access

Organization

Planar, 3D, 3-wire

Maximum Capacity

131,072, 18-bit
Bus Mode

Cycle Time*

Read

980 ns

Write

980 ns

Read/Pause

1.56 us

X-Y Current Margins

6% @ 0° C, £7% @ 25° C, +6% @ 50° C

Strobe Pulse Margins

+30ns @0° C, +40 ns @ 25° C, +30 ns @ 50° C

Voltage Requirements

+5 V £ 5% with less than 0.05 V ripple
- 15 V + 5% with less than 0.05 V ripple

Average Current Requirements

Stand by:

+5V:

22A

-15V:05A

Memory Active:

+5V:

54 A

-15V:6.0A

Power Dissipation (Worst Case)

G109 Control Module ~60 W
G231 Drive Module ~40 W
H214 Stack Module ~20 W
Total at maximum repetition rate:

Ambient Temperature

0° Cto 50° C (32° F to 122° F)

Relative Humidity

0—90% (noncondensing)

140 W

*Nominal

For a detailed description of the ME15 and MF15-U Core Memories, refer to the manuals listed
below:
MEIL5 Core Memory Maintenance Manual, EK-ME15-MM-001

MFI15-U Core Memory Maintenance Manual, EK-MF15-MM-001

1-41

CHAPTER 2

SYSTEM PROCESSORS

Section 1.

XM15 MEMORY PROCESSOR

MEMORY

UNIBUS

PERIPHERALS

UNIBUS

PERIPHERAL
PROCESSOR

r‘

CENTRAL

PROCESSOR

‘

I1/0

PROCESSOR

FLOATING

POINT
PROCESSOR

I/0

BUS

I/0 BUS

PERIPHERALS

15-0856

The XM15 Memory Processor is located logically between the XVM Central Processor and the
Memory and performs the following specialized functions:

Arbitrates between the three requesting elements for access to memory.
Instruction pre-fetch to accelerate XVM CPU operation (IPF).
Contains Automatic Priority Interrupt (API) logic.
Contains Memory Management (MMGR) logic which enables different addressing modes.
The XM15 makes it possible for the CPU to run programs above 32K, and also provides the means
whereby more than one user’s programs are resident at the same time. This processor has a high
resolution accounting clock and associated logic. The XM 15 also has a bus converter which enables
separate processors with different memory busses to communicate with the same memory on a common XM memory bus.
The XM 15 basic block diagram is shown in Figure 2-1.

4/\
-I

EXTERNAL BUS

XM BUS

e—MEMORY —»

PORT #*1

PORT # 2
PSW

FROM EPU

INSTRUCTION

PSW

PREFETCH
IPF

AUTOMATIC

MEMORY

MANAGEMENT

MMGR

PROGRAM

I70 Bus_

Y INTERRUPT

TERMINATORS

ETC...

BUS CONVERTERS
BCC

MEMORY
DATA LINES
FROM CPU
15-0820

Figure 2-1

XMI15 Basic Block Diagram

The Port Module of the XM15 functions as a buffered multiplexer. It has three separate input ports,
termed CP (Central Processor) port, EP (External processor) port, and the UF port. The output of the
XM15 is also dual-ported, and these ports may be interleaved depending upon memory size and
configuration. The Port Module will also function as a short-term buffer so that its inputs and outputs
are not held busy for long periods. There are two methods by which the Port accomplishes this:
1.

When executing a write, once the address and data have been supplied, the requesting processor usually has to wait for the memory to signify that the write function has terminated.
With the Port module, the requesting processor may begin another function as soon as
address (Interface module) and data (Port module) have been latched.

With an external processor request for a read, the Port module will latch the data when it
becomes available, and hold it until the processor is ready to accept it. However, the output
port is released immediately for possible use by the other processor. The interface acts in a
similar manner for the CPU.

The IPF (Instruction Pre-Fetch) is a special unit within the XM 15 that speeds up the overall operation
of the system by attempting to supply, immediately, the contents of the location in memory containing
the instruction required by the CPU. It is capable of obtaining data from memory and storing it in an
internal file until requested by the CPU. Obviously, the CPU will be faster if demands for instructions
from memory can be filled immediately, and this is what the IPF tries to accomplish.

If processors always executed “straight-line’’ code (i.e., if they never jumped out of sequence), then
there would be a strong case for holding a large number of words in a file and pre-processing. However, efficient programming demands that JMPs and JMSs be made to subroutines to prevent repetitive code. To determine the optimum size of the IPF file, exhaustive tests were performed on various
systems, under different monitors, and the results showed that four words would be sufficient. Thus,
on an XVM system, when the CPU breaks the sequence, the IPF waits until the new sequence is
established, then the IPF loads up its file with the next sequential words. The IPF will then stay ahead
of the CPU, supplying instructions upon each request, until the CPU breaks the sequence again.

2-2

2.1

AUTOMATIC PRIORITY INTERRUPT

The automatic priority interrupt (API) system ensures efficient handling of service requests at high
rates.

The API system contains eight levels of priority. The lower four of these are allocated to the monitor
systems, the upper four to the I/O processor. Up to 32 individual interrupts are available at the I/O
processor.

A device initiates an interrupt request on its preassigned level by raising a request flag, and identifies
itself by posting a unique core address. There is one unique core address for each of the 32, interrupts
(445 through 77 are reserved in the standard software). This address serves as the entry point (trap
address) to the device’s service routine.

Each monitor API level services one interrupt and uses a single trap address between locations 405 and
43;5. The monitor requests are initiated by a program issuing an ISA instruction.
The 1/0O interrupts permit the asynchronous operation of many devices, each at its proper priority
level. The software priority levels are used to establish a priority queue for processing real-time data
without inhibiting the hardware interrupts to service devices.
2.2 APl HARDWARE

Figure 2-2 relates the activity of the Automatic Priority Interrupt (API) system from the initiation and
acceptance of the request, the servicing of the accepted request, and the debreak from the serviced
priority level.

PRIORITY LEVEL ACCEPTANCE

DEBREAK APl

—

API DISABLE
T

]

DEBREAK

ACTIVE

PRIORITY LEVEL O

[

PRIORITY LEVEL 1
T
1T
1T
1
|
PRIORITY LEVEL 2

O~
|

[

PRIORITY LEVEL 3
|

O~
1

PRIORITY LEVEL 4

4417

PRIORITY LEVEL 5

<:)‘\\
|

PRIORITY LEVEL 6
I

PRIORITY LEVEL 7

[o]1]2]3[a]|s]|6]|7]|
\

é
|

—

STATE

PRIORITY

&
|

]

RequesT recisTER

HARDWARE

SOFTWARE

REQUEST

REQUEST
15-0054

Figure 2-2

API System, Simplified Block Diagram

The API Request register contains eight levels; four levels are activated by the devices (hardware) on
the I/O bus, and four are activated under software supervision. The hardware requests are assigned the
highest priority, and are designated request levels 0, 1, 2, and 3. The software requests are designated
request levels 4, 5, 6, and 7, and are initialized by the ISA instruction with the associated AC bits set.
The priority level bars in Figure 2-2 depict the priority level that is selected by the ISA instruction, or
that is raised by the API control when it has granted a break request on that specific level. The priority
level (PL) bars indicate that any request equal to, or less than the priority level which is active, will not
be accepted. At the end of the subroutine currently being performed by an active request, a debreak
and restore instruction is issued. This will lower the priority to the next requesting priority level. The
ball, representing the priority debreaking, will fall as long as there is no bar present (i.e., no priority
level set). If a lower priority level is set, the debreaking will cease at that level.

The API Request register (RQ) buffers the inputs from the hardware interrupt on levels O through 3
and the inputs from the monitors on levels 4 through 7. If two or more hardware interrupts on one
level make simultaneous interrupt requests, the device controller closest to the processor is given
priority and interrupts at its unique location. An interrupt request sets a bit in the RQ according to its
preassigned priority level. The API system signals the CPU to stop execution at the completion of its
current instruction. It then gates the I/O processor’s address lines, which contain the address of the
interrupt’s unique core location, into the CPU Memory Output register. The CPU then requests a
memory cycle and executes the instruction it fetched from that location. During this operation, the
program counter remains unchanged. The instruction is normally a jump to subroutine (JMS) that
stores the contents of the L, BM, UM and program counter, which, in turn, points to the location
where the current program was interrupted in the first location of the subroutine and begins execution
at the subroutine’s second location.
The API system also sets a PL corresponding to the level of the interrupt. This prevents interrupts on
the same level or lower levels from interrupting the current interrupt. Higher priority devices can still
interrupt lower priority devices. The JMS instruction allows nesting of all levels. At the completion of
the interrupt subroutine, a debreak and restore (DBR) instruction must be issued to reset the bit in the
PL and in the RQ.
The API hardware ensures that simultaneous requests by multiple devices are handled in the proper
priority sequence. If interrupt requests occur at different priority levels, the highest priority requests
will be serviced first. Higher priority devices may interrupt lower priority devices. The entire API
system may be enabled or disabled with a single instruction; however, most devices provide facilities to
enable and disable their flags from the interrupt separately. If the API system is disabled, the device
will automatically signal the program interrupt to obtain a response at that priority level.
The program interrupt (PI) sets level 3 if priority levels PL 0-3 are 0, PL 3 is enabled, and no other API
request has been synchronized.
Under program control, the level of a priority request may be raised to provide dynamic priority
reallocation. It does this by issuing an ISA.

ISA

705504

Initiate selected activity. The API activity specified by a set bit
in the AC is initiated.

The ISA instruction places a bit into a priority level specified. This effectively masks all lower priority
levels. A debreak instruction (DBK) is used to reset this bit when the higher priority level is no longer
required. For example, a priority-2 interrupt routine is designed to enter data in memory locations A
through A + 10 during an interim period when the priority-2 device is inactive and, based on a
calculation made by a software priority-6 routine, it becomes necessary to move the data to memory

2-4

locations B through B + 20. The changes in the routine at level 6 must be completed without interrupt
once they are started. This is possible by causing the level 6 program to raise itself to level 2 (devices on
the same or lower priority may not interrupt), complete the change, and debreak back to level 6. Note
that the ISA is also used to trigger the API levels dedicated to software priority queues. This unique
advantage of the API system lies in the proper use of its software levels. In the real-time environment,
it is necessary to maintain data input/output flow, but it is not possible to perform long complex
calculations at priority levels which shut out these data transfers. With the API, a high-priority data
input routine that recognizes the need for complex calculations can call for a software-level interrupt.
Since the calculation is performed at a lower priority than the device handling, the latter can go on
undisturbed. The monitor task of establishing a multi-priority request queue at the software level is
greatly simplified by utilization of the API hardware.
2.3

MEMORY MANAGEMENT (MMGR)

The Memory Management logic (Figure 2-3) within the XM135 provides the system with a wide range
of real-time control by performing the following three tasks:
1.
2.
3.

dynamic address modification
extended internal address control
selective instruction checking

The three functions listed above are executed when the system is in a real-time mode of operation
called USER MODE. This mode can be entered by two main methods: 1. the execution of the MPEU
IOT; and 2. when a DBR IOT is executed, and bit 02 of the Restore word contains a 1.

MEMORY BUS

ADDRESS TO MEMORY

COMPARATOR

ADDER

INSTRUCTIONS FROM MEMORY

ADDER

INSTRUCTION

DECODES

PROTECT
VIOLATION IF
SIGN POSITIVE
AND

—

USER

ILLEGAL

MODE

BOUNDARY

v
\

INTERRUPT
AND SKIP

I
DATA

RELOCATION

wl:lrfi_RERlUNPESEI; &%%%DED

INSTRUCTIONS

]

LOAD
/

1/0 BUS

INSTRUCTIONS TO CPU

MEMORY BUS
FROM CPU

I5-0178

Figure 2-3

Memory Management Block Diagram
2-5

The status of the User mode flip-flop is saved whenever the program is interrupted. The User mode
state, bit 02 is stored, usually with the contents of the Program Counter (PC) in the first location of the
service routine. The relevant instructions are CAL and JMS, and both Program Interrupt (PI) and
Automatic Priority Interrupt (API) cause the same effect.
There are three registers associated with this logic:
1.

Boundary Register

The contents of this register corresponds to the highest ten bits of the memory address.
BOUNDARY REGISTER (BR)

LDBR 701704

NOT USED

BOUNDARY REGISTER
B8ITS BR0O0O-09

15-0818

Relocation Register

The contents of this register are used with the 18 bits of memory address.
RELOCATION

00
LDOMPLR 701724

RELOCATION

NOT

BITS RR 00-09

USED
15 0819

Memory Management Register

The contents of this register, bits 08-17, are used similarly to the bits in the relocation
registers, i.e., they are used with the highest 10 bits of memory address. The remainder of
this register is divided into individual signals.
MEMORY

MANAGEMENT

RDMM 700032
LDMM 700024

RDIS

[

G MODE

SEGMENT
LENGTH
REGISTER

SHARE
REGISTER

WRITE

PROTECT

107
PERMIT

SHARE
MOD

~
15-0817

Segment Length Register (SLR) - Bits MMO06 and 07 are used to select one of four possible sizes of
External Shared Address Space (ESAS).
Share Mode (SH) - Bit MMOS5 is used to determine whether or not the system can go into Share mode.
This bit will only have effect when the system is in User mode.
Write Protect (WP) - Bit MMO04 signifies whether it is possible to write to the ESAS. The system must
be in Share mode before this bit has any effect. That means that TR APs will occur only if an attempt is
made in User mode, with Share mode on.

10T Instruction Permit (IOTP) - Bit MMO3 defines whether or not TR APs will occur, should an IOT

instruction be executed while in User mode.

G-Mode (GM) - Bits MMO1 and 02 are the G-Mode selectors. When in User mode, the type of GMode (0-3) determines the starting address of the Shared Address Space (SAS). The width of the
address passed to the memory is also affected by the G-Mode bits when User mode is set. GMO, which
is not G-Mode, allows only 15 bit indirect addressing. GM1 will allow 16 bits of indirect addressing.
GM2 allows all 18 bits, and GM3 only 17 bits, under similar circumstances.

Relocate Disable (RDIS) - Bit MMOO, when set, inhibits relocation of the address in User mode, and
prevents TR,APs from occurring when boundary violations occur, or when OAS, HLT, or an XLT of
an XCT is performed.

IOT Instructions

2.4

Mnemonic

Code

RDMM
LDMM
MPLD
MPLR
MPEU

700032
700024
701704
701724
701742

Description
Read MM Reg to ACO00-17.
Load MM Reg from AC00-17.
Load Boundary Reg from AC00-09.
Load Relocation Reg from A C00-09.
Enable User Mode.

DYNAMIC MAPPING

There are four possible modes of address modification, or “mapping”, as follows:
1.
2.
3.
4.

Direct Mapping (D-MAP)
Relocated Mapping (R-MAP)
Shared Mapping (S-MAP)
Protected Mapping (P-MAP)

Mapping is the name given to the process of translating from “virtual’” addresses, which are those the
CPU uses, to “real” addresses, which are absolute core memory locations. For a detailed description
of the various types of mapping, refer to Chapter 1, Paragraph 1.2, Addressing. A brief description of
the hardware aspect follows.

D-MAP - The Memory Management can accomplish direct mapping in either of two states:

Not in User mode, in which case the ‘“virtual” address from the CPU passes straight

In User mode, but R-DIS (MMO00=1) is set. This mode allows the use of wide (G-Mode)
addressing and NEXM protection, but does not relocate the CPU address. In this case. the
“virtual” address is the same as the “real’” address except as affected by G-Mode.

through and is the “real”” address.

R-MAP - The Memory Management must be in User mode for this type of mapping to come into
effect. The SH bit must be reset (MMO05=0). The “virtual” address sent from the CPU will have the
current contents of the Relocation register added to it. The sum of these two (RR00-09 + PC00-17)
will be the “real’” address presented to the memory. If the virtual address should exceed the value in the
Boundary register, a trap will occur and the program will be interrupted.

S-MAP - This type of mapping has three separate mapping functions, depending what area of the
“virtual”” address space is referenced (Figure 2-4).

2-7

OO0

= A+01000 SLR=0
= A+02000 SLR =1

= A+10000 SLR =2

- A+20000 SLR=3

B=A

400, }—» BA—

>> >

= 060000 GM=0

= 160000 GM=1
= 760000 GM=2
= 360000 GM=3

X -

g._

VIRTUAL

MEMORY
15-0816

Figure 2-4

User’s Virtual Address Space in S-MAP

If the “virtual” address should refer to a location between 0 and A, then the virtual address will be
treated in the same way as it would be in R-MAP.
If the location addressed is greater than A but less than B, then the address is termed “share internal®.
This means that a reference has been made to the Internal Shared Address Space (ISAS), and the
address is modified by concatenating the address (PC10-17) with the contents of the Relocation register (RR00-09). The result of this process will in fact refer to a “virtual’’ address somewhere within the
range O to 377s. This relocated value of the address is then forwarded to memory.
If the “virtual” address is greater than B, but less than C, then a reference has been made to the
External Shared Address Space (ESAS). Note that C is not a fixed address, because the length of the
Shared Address Space (SAS=ESAS + ISAS) is defined by the contents of the Segment Length Regis-

ter (SLR).

A reference to ESAS will cause the address bits (PC05-17) to be added to the contents of the Share
Register (SR00-09). The result of this addition will be sent to the memory. This relocates the address to
an area of core reserved for shared addressing. The use of the S-M AP mode of operation allows several
independent tasks access to a designated area of core memory that is not physically contained within
any of the user’s partitions. A diagram that illustrates the points of S-M AP, is shown in Figure 2-5.

NOTE
|
The function of the G-Mode bits with regard to
address truncation is still in effect, and the “‘virtual”
addresses will be truncated depending upon which
GM is set.

2-8

64K

.
y

56K
ESAS

48400

GM=0
=

ESAS

v/ 4

SR=48K
RR=12K

_ISAS
24K

—~
USER PROG.

///

//,/

ISAS

1/0 & SYS.

12400
12K

EXEC.

J7]

VIRTUAL

REAL
15-0815

Figure 2-5

S-Mapping

P-MAP

NOTE
This is a special mode of operation that is not selectable by program on a standard XVM system. If a
user should want this mode of operation, he or she
must contact their local Digital Field Service office.
Enabling this mode of operation makes R- or SMapping inaccessible.

This type of mapping does not use the Relocation register or the Share register. In this type of operation, the Boundary register is loaded to establish a lower boundary in memory. If an attempt should
be made to reference an address below the boundary while in User mode, the Memory Management
logic will trap.
25

G-MODES

There are four possible G-Modes, GM0-GM3. A brief description of each follows.

GMO (MM1 & 2=0) - This mode is “Normal mode” and makes the system operate in a similar
manner to the PDP-9 and PDP-15. This is necessary for compatibility with these earlier systems. When
a JMS is executed, the state of the LINK, BANK MODE, and USER MODE flip-flops are stored in
bits 00-02 respectively, of the entry-point address along with the 15 bits of the current virtual PC.
When the XVM system is in Share mode (which implies User mode) the G-Mode field also defines the
starting ‘‘virtual” address of the SAS as 060000.
GM1 (MMO01=0, 02=1) - When this mode is in effect, 16 bits of each indirect address will be used, and
the maximum user ‘“‘virtual’’ address will be 65536. In addition, when a JMS is executed, the return
address location will contain 18 bits of the PC. The previous state of the LINK, BANK MODE,
USER MODE, are not saved. The starting address of the SAS is defined in this mode as Y60000. The
letter Y is used because real addresses 160000, 360000, 560000, and 760000 all look the same because of
address truncation.
2-9

GM2 (MMO1=1, 02=0) - The effects of this mode are like those of GM1, but with two exceptions.
First, all 18 bits of “virtual” address are passed and all 18 bits are used with an indirect reference,
making a maximum of 262144 memory locations available. Second, the starting address of the SAS is
760000. The execution of a JMS instruction will have the same effect as in GM1.
GM3 (MMO1 & 02=1) - This mode defines the starting address of the SAS as 360000. Bit 00 of the
address is truncated by this mode. limiting the maximum virtual address to 131072, The effect of the
execution of a JMS is the same as for the two previous G-Modes. This mode, and GMO, are supported
by the appropriate Digital-supplied software systems.

Al
e

2.6 TRAPS
TRAP is the term used to indicate that the XVM system user program has attempted to execute some
instruction that is deemed “‘illegal”. Traps only occur in User mode, and are produced by any of the
following conditions:
An attempt to execute a HLT instruction or,
An attempt to execute an IOT instruction or,
A microcoded instruction containing an QAS instruction or,
An instruction XCT of an XCT instruction or,
An attempt to reference a location that is “non-existent” memory (NEXM) or,
An attempt to read or write to a location which is:

a.
b.
c.
7.

Below the boundary, with the system in P-MAP or,
Above the boundary, with the system in R-MAP or,
Above the boundary, but outside the SAS, with the system in S-MAP or,

An attempt to write into the Extended Shared Address Space (ESAS), while in S-MAP, and
with the Write Protect bit set (MMO04=1).

The effect of a trap is that the user’s program will be interrupted and program control will transfer to
location 000001, after storing the current PC + 1 in location 000000. The trap is then handled as if it
were a normal interrupt. This sequence can only happen if Program Interrupt Enable is on (PIE=1). If
this is not the case, then the trap is treated like a CAL. The PC + 1 is stored in location 000020, and the
instruction in 000021 is executed. There are a number of IOT instructions that can be used to determine which type of violation occurred.
IOT Instructions

Mnemonic

Code

MPSK

701701
701741
701702
701744

MPSNE
MPCV
MPCNE

Description
Skip if protect violation occurred.

Skip if NEXM reference attempted.
Clear violation flag.

Clear NEXM flag.

It is possible for IOT instructions to be executed in User mode without a trap occurring by setting bit
MMO3 in the Memory Management register. This is termed **User IOT mode.”

2-10

Section 2.

PERIPHERAL PROCESSOR

MEMORY

|
UNIBUS

MEMORY

PROCESSOR

CENTRAL

ROCE SSOR

PROCESSOR

’__

ERIPHERAL

UNIBUS
PERIPHERALS

: {—"~ PROCESSOR

FLOATING

POINT

PROCESSOR

I/0 BUS

::)

I/0 BUS

PERIPHERALS
15-0858

The XVM Peripheral Processor consists of one of the computers from the PDP-11 family with some of
its own memory (normally 8192 words) on the Unibus, and is used as the XVM system’s second
input/output processor.

The Unibus is connected to the External Processor Port of the XM15 Memory Processor. There is an

address translation unit built in to enable the peripheral processor to access the XVM memory.

The peripheral processor enables the XVM to appear as a Unibus Memory Subsystem, thus allowing
the use of standard Unibus peripherals as I/O devices.

A means by which the processors may interrupt each other is provided. The Peripheral Processor Unit

(PPU) is allowed to provide interrupts to the XVM CPU at one of four levels, with up to 128 vector
addresses.

The XVM CPU can interrupt the peripheral processor at one of two levels, with one of two vector
addresses, usually to transfer a data control word to the PPU.

2.7

MEMORY ADDRESS TRANSLATION (Figure 2-6)

Remember that the PDP-11 family PPU is a byte-oriented machine. The XVM CPU and memory are
18-bit word-oriented systems. Therefore, some processing must be done to relocate the PPU byte
addresses to MPU word addresses.

The first process is to subtract from the top five bits of the address, a value corresponding to the
amount of local memory resident on the PPU. Once this has been done, the address is then shifted one
place to the right to compensate for the fact that the PDP-11 family PPU uses byte addresses. This can
be seen in Figure 2-6. There is a “28K limit”” mark on the common memory in Figure 2-6; this shows
the maximum PPU memory addressing capability without PPU memory -management.

This limit of addressing capability refers only to the PPU. NPR devices have no such limit although
the absolute core limit is still 760000, due to device registers starting at that Unibus address.

2-11

PDP- 11

56K

PPU

ADDRESSING

40K

48K

X VM

32K

COMMON

32K
28K LIMIT

——

OF PPU
ADDRESSING
WITHOUT

16
K
—

—

— -

24K

USE OF

16K

PPU MEMORY

MANAGEMENT

ADDRESSING

K
24

MEMORY

40K

yum

LOCAL

MEMORY

oK
15-0812

Figure 2-6

Memory Address Translation

Unibus device addresses, which reference locations 160000 or greater, are transformed to 760000 or
greater and refer to PPU or 1/0 device registers. Although the PDP-11 may have 8K (8192) of memory, there are two bytes in each word and each one is separately addressable. Thus, it takes addresses
000000 to 016384 to address the first 8K words. On an 8K PPU therefore, address 016385 actually
addresses the first location in common memory. The memory address shifting process is shown in
Figure 2-7.

RELOCATED

UNRELOCATED ADDRESS BITS

ADDRESS BITS
—A
0

UNIBUS

ADDRESS

(APPENDED TO BITS 17 THROUGH 13)
A

‘F
6

LINES

\\\‘\\\‘\\\‘\Qt;'\\\‘\\\\'\\\‘\\\\‘\\\‘\\\‘\\\\\\\\'\\\‘\\\"\\\ \\\‘\\\‘

MEMORY

ADDRESS

)

o]
15-0755

Figure 2-7

Memory Address Shifting Process

For further information on PPU address manipulation, refer to the Unichannel System Maintenance
Manual (DEC-15-HUCMA-B-D), Chapter 4.
2.8

XMI15 EXTERNAL PORT

The external port of the XM 15 Memory Processor provides the unique facility of “floating” the EPU
input address. This address float is used primarily in multiprocessor XVM systems to enable different
processors access to core on other systems.

2-12

On standard systems supplied by DEC, the address float will be set to zero. When an address is
received by the XVM external port, it is checked to ensure that it lies within the “EP Address Window”. This is an upper and lower address, the parameters of which are set by the factory.
DEC standard software will operate only with the factory-authorized settings of the “EP Address
Window”.

The width of the EP Address Window should always be less than the address “float”, on systems
where this facility is used. If it is not, the system will act as if it had “memory wrap-around”.
2.9

UNICHANNEL LINK
The link between the two processors is one DR15-C Device Interface, whose external connections
(those at the opposite end, logically, to the I/O bus) are coupled to the similar connections of two
DR11-C Interfaces. This system provides a method of transferring 17-bit data words from the I1/0O bus
to the Unibus and the facility to generate one of four levels of interrupt, with up to 128 vector addresses. The manner in which the data word is transferred is depicted in Figure 2-8.

DR11-C
0O

DR11-C # @ INPUT DATA BUFFERS
0

DATA REGISTER

l l l \ DR11-C #1 INPUT DATA BUFFERS

767774

15
767764

NOT

USED
15-0813

Figure 2-8

Data Input

Figure 2-9 shows how the output data buffers of both DR11-Cs are used to hold API-break addresses.
These addresses are enabled on to the XVM I/OA Bus when the respective interrupt level is being
serviced.

The remaining registers in the DR11-Cs and the DR15-C contain status information. This is shown in
Figure 2-10.

2-13

DRI1-C # @

767772|

OUTPUT DATA

BUFFER

AP1

ADDRESS

DRI1-C #1

OUTPUT

DATA

BUS

@ ADDRESS

—

11-17

1/0

BUS 11-17

BUFFER

AP1

1/0

767762 |

AP13 ADDRESS

—

AP12

170

)

ADDRESS

BUS 11-17

1/0 BUS 11-17
15-0814

Figure 2-9

Data Output

1
DR11-¢
.15

NOT

USED

NOT USED
NEW TCBP

ENABLE

TCBP

INTERRUPT

or11-c
¥o
15

767760 {

NOT

~USED

’

NOT USED

API

DONE
EMABLE API
DONE INTERRUPT

DR15C
00

—r.

N -

NOT USED

ENABLE

PI/API
15-0810

Figure 2-10

Status Information

2-14

2.10

IOT INSTRUCTIONS

Mnemonic

Code

SIOA
CIOD
LIOR
SAPIO
RDRS
CAPIO
SAPII
LDRS
CAPII
SAPI2
CAPI2
SAPI3
CAPI3

706001
706002
706004
706101

Skip if I /O data accepted (if TCBP DONE = 1)
Clear I/O done (set TCBP DONE = 0)
Load I/O Register
Skip if APIO flag = 1

706112
706104
706121

Read OR status register to AC
Clear APIO flag

706122
706124

Load DR status register from AC
Clear APII1 flag

2.11

Skip if API1 flag = 1

706141

Skip if API2 flag = 1

706144

Clear API2 flag

706161

Skip if API3 flag = 1

706164

Clear API3 flag

767770

Control Status Register

BRS

767772
767774

Output Data Buffer
Input Data Buffer

VA=300

2.12

Description

DR11-C

767760

Control Status Register

BR7

767762

VA=310

Output Data Register

767764

Input Data Register

THE UNIBUS AND THE PDP-11 PROCESSOR

2.12.1
The Unibus
All the PDP-11 computer system components and peripherals connect to and communicate with each

other on a single high-speed bus, the Unibus. All elements of the PDP-11 system, including the central
processor, communicate with each other in identical fashion via the Unibus; thus, the processor can

easily access both peripherals and memory (Figure 2-11).

—

CPU

MEMORY

I/0

)
1/0

I/0

1/0

15-0811

Figure 2-11

PDP-11 System, Simplified Block Diagram

With bidirectional and asynchronous communications on the Unibus, devices can send, receive, and
exchange data independently without processor intervention. Because it is asynchronous, the Unibus is
compatible with devices operating over a wide range of speeds.
Device communications on the Unibus are interlocked. For each command issued by a “master”
device, a response signal is received from a “‘slave” completing the data transfer.

2-15

1/0 devices transferring directly to or from memory are given highest priority and may request bus
mastership and steal bus and memory cycles during instruction operations. The processor resumes
operation immediately after memory transfer. Multiple devices can operate simultaneously at maximum direct memory access (DMA) rates by “‘stealing’ bus cycles.
2.12.2

PDP-11 Processor

Central Processor

The central processor, connected to the Unibus as a subsystem, controls the time allocation of the
Unibus for peripherals and performs arithmetic and logic operations and instruction decoding. It
contains multiple high-speed general purpose registers which can be used as accumulators, address
pointers, Index registers, and other specialized functions. The processor can perform data transfers
directly between 1/0 devices and memory without disturbing the processor registers; and it performs
both single and double operand addressing and handles both 16-bit word and 8-bit byte data.
Instruction Set

The instruction complement uses the flexibility of the general purpose registers to provide over 400
powerful hard-wired instructions the most comprehensive and powerful instruction repertoire of any
computer in the 16-bit class. Unlike conventional 16-bit computers, which usually have three classes of
instructions (memory reference instructions, operate or AC control instructions, and I/O instructions), all operations in the PDP-11 are accomplished with one set of instructions. Because peripheral
device registers can be addressed as easily as core memory by the central processor, instructions that
are used to manipulate data in core memory may be used equally well for data in peripheral device
registers. For example, data in an external device register can be tested or modified directly by the
CPU, without bringing it into memory or disturbing the general registers. One can add data directly to
a peripheral device register, or compare logically or arithmetically contents with a mask and branch.
Thus, all PDP-11 instructions can be used to create a new dimension in the treatment of computer I/O
and the need for a special class of I/O instructions is eliminated.

Priority Interrupts

A multilevel automatic priority interrupt system permits the processor to respond automatically to
conditions outside the system. Any number of separate devices can be attached to each level.

Each peripheral device in the PDP-11 system has a hardware pointer to its own pair of memory words
(one points to the device’s service routine, and the other contains the new processor status information). This identification eliminates the need for polling devices to identify an interrupt, because the
interrupt servicing hardware selects and begins executing the appropriate service routine after having
automatically saved the status of the interrupted program segment.

The device’s interrupt priority and service routine priority are independent. This allows adjustment of
system behavior in response to real-time conditions by dynamically changing the priority level of the
service routine.

The interrupt system allows the processor to continually compare its own programmable priority with
the priority of any interrupting devices and to acknowledge the device with the highest level above the
processor’s priority level. Servicing an interrupt for a device can be interrupted for servicing a higher
priority device. Service to the lower priority device is resumed automatically upon completion of the
higher level servicing. Such a process, called nested interrupt servicing, can be carried out to any level
without requiring the software to save and restore processor status at each level.

Re-entrant Code

Both the interrupt handling hardware and the subroutine call hardware facilitate writing re-entrant
code for the PDP-11. This type of code allows a single copy of a given subroutine or program to oe
shared by more than one process or task. This reduces the amount of core needed for multitask
applications such as the concurrent servicing of many peripheral devices.
2-16

Addressing
'
Much of the power of the PDP-11 is derived from its wide range of addressing capabilities. PDP-11
addressing modes include addressing forward or backward, address indexing, indirect addressing, 16bit word addressing, 8-bit byte addressing, and stack addressing. Variable length instruction formatting allows a minimum number of bits to be used for each addressing mode. This results in efficient use
of program storage space.

Stacks
In the PDP-11, a stack is a temporary data storage area that allows a program to make efficient use of
frequently accessed data. The stack is used automatically by program interrupts, subroutine calls, and
trap instructions. When the processor is interrupted, the central processor status word and the program counter are saved (pushed) onto the stack area, while the processor services the interrupting
device. A new status word is then automatically acquired from an area in core memory that is reserved
for interrupt instructions (vector area). A return from the interrupt instruction restores the original
processor status and returns to the interrupted program without software intervention.
Direct Memory Access
All PDP-11s provide for direct access to memory. Any number of DMA devices may be attached to
the Unibus. Maximum priority is given to DMA devices, thus allowing memory data storage or
retrieval at memory cycle speeds. Latency is minimized by the organization and logic of the Unibus,
which samples requests and priorities in parallel with data transfers.
Power Fail and Restart
The PDP-11 power fail and restart system not only protects memory when power fails, but also allows
the user to save the existing program location and status (including all dynamic registers), thus preventing harm to devices, and eliminating the need for reloading programs. Automatic restart is accomplished when power returns to safe operating levels, enabling remote or unattended operations of
PDP-11 systems. All standard peripherals in the PDP-11 family are included in the systemized powerfail protect/restart feature.
2.13 SYSTEM OPERATION
The Unichannel system when installed on an XVM system, can be used in a variety of ways. DIGITAL
software systems supplied with the system aid in making the link-up between the two processors as
flexible as possible. The Unichannel can be made to operate in one of four possible modes:
1.

Pure I/O - The PDP-11 excels when used as an I/O controller. This mode of usage frees the
XVM from the chores of tending to slow devices, plotters, and printers, for example.

Sophisticated I/O - In an effort to make the Unichannel performmore of the XVM system’s
chores, some valuable routines were included in the PPU Monitor. SPOOL helps the XVM
by relieving it of the necessity of holding data buffers for slow devices in the CPU’s memory.
The disk, normally included in a Unichannel, functions as a large temporary store, while the
PPU doles out words to devices when they are ready.

Pure computing - Programs can be written and assembled by the PPU to run on the PPU.

The three cases above have been catered for by the inclusion of programs in the standard software

packages.
4.

Independent - The PPU and the XVM can function as separate systems, provided care is

taken to prevent interference between PPU and CPU peripherals.

2-17

PPU peripheral devices include the following:
CRI11
DL11
KGl1
LP11
LV1l
RK11
XYl1l1
XY311

Card Reader
Asynchronous Communications Interface
Communications Arithmetic for DL11
Line Printer
Electrostatic Printer /Plotter
Cartridge Disk
Plotter
3 Pen Plotter

2-18

Section 3.

FP15 FLOATING POINT PROCESSOR

MEMORY

[
MEMORY
PROCESSOR

UNIBUS

PERIPHERAL

PERIPHERALS

PROCESSOR

[——~

I/0
PROCESSOR

I/0 BUS

CENTRAL
PERIPHERALS

[~
| PROCESSOR

15-0857

FP15 operations consist of memory transfers to obtain or store data, and arithmetic calculations in the
FP15 unit itself. The cycle time of memory, the central processor, and the I/O processor, as well as
data channel latency, are unaffected by the FP15 option. Data channel transfers to and from memory
may occur simultaneously with FP15 arithmetic operations. Program and priority interrupts are inhibited and queued for priority-ordered response upon completion of the FP15 instruction. (The longest
FP15 instruction takes 21 us.)
An XVM computer system was timed running five FORTRAN programs with and without floating
point hardware. The results are as follows:

Program Description

XVM

XVM & FP15

One hundred iterations of the analysis of three body

37.0 sec

3.0 sec

A least squares fit of data to a straight line.

5.1 sec

0.7 sec

A matrix inversion.

12.0 sec

5.0 sec

A test of all floating point functions.

11.4 sec

1.4 sec

A Fourier transform program.

16.9 sec

2.9 sec

final states. A physics application program.

2-19

FP15 System Features

Directly or indirectly addressable up to 128K of core.

Performs arithmetic operations on 18- or 36-bit integers and 36- or 54-bit floating-point
numbers.

e
e
e

Allows execution of in-line code - CPU instructions and floating point instructions may be
interspersed as desired.

I/O Processor can access memory on a shared basis with the floating point processor; how-

ever, the I/O processor takes priority over the FP15.

When an undesired condition (underflow, overflow, abnormal division, or memory protect

violation) occurs, the FP15 interrupts the CP stored program and automatically identifies
the source of the interrupt.

Worst-case multiplication and division times on normalized operands do not exceed 21 us.

Possesses ability to convert floating point numbers to integers and integers to floating-point
numbers.

2.14

Remainder, product, and align bits in FMQ are accessible by appropriate software.

Unnormalized and unrounded arithmetic may be specified.

A class of non-memory reference instructions is available. These instructions use existing
contents of FMA and FMB and require no memory reference.

Built-in maintenance logic (maintenance mode) allows single or multiple substeps of an
instruction. All major registers and control can be examined at the end of each step.

Designed to operate with existing XVM options (Memory Management, etc.) with no
increase in cycle time.

FP15 FUNCTIONAL DESCRIPTION

Figure 2-12 is a simplified block diagram of the FP15 Floating Point Processor. The FP15 is in parallel
with the CPU on the memory bus, and monitors each instruction fetched by the CPU from core. If bits
00 through 05 of the instruction are equal to 71s, it is recognized as a floating point instruction; the
CPU treats the instruction as an NOP. The FP15 takes control of memory, inhibits the CPU, and then
simulates the CPU by completing the normal interface between CPU and memory. After the floating
point instruction has been executed, the CPU is enabled, and both the CPU and FP15 are free to
monitor the next instruction.

Functionally, the FP15 contains a Memory Buffer register and two operand registers. The Memory
Buffer register provides temporary storage for all words transferred to the FP15. One operand register
consists of an 18-bit exponent register (EPA), a 35-bit mantissa register (FMA), and a 1-bit sign
register (A SIGN).

This operand register is referred to as the floating point accumulator. An additional 35-bit register,
designated FMQ, serves as an extension to the floating point accumulator.

2-20

MEMORY

]

fil@

BUS

FP15

FLOATING
POINT PROCESSOR
7-BIT

(JMS EXIT

12-BIT

I FP15 |
| CONTROL |

INSTRUCTION

(IR)

BUFFERED
36-BIT

MEMORY BUFFER

TO ALL MAJOR

* REGISTERS

L_ —_— _I

(BMB)

17-BIT

ADDRESS

{AR)

IIIII'

CONTROL m

[a] wx [B]

[

' - CONTROL

36-BIT
ARITHMETIC
LOGICAL

UNIT
(ALU)

18-BIT

EPA

18-8IT

EPB

ALU
BUS

35-BIT

FMA

FMB

18-B1T

35-BIT

SHIFT

FMQ

(SC)

15-0574

Figure 2-12
FP15 Floating Point Processor
Simplified Block Diagram

2-21

A second operand register consists of an 18-bit exponent register (EPB), a 35-bit mantissa register
(FMB), and a 1-bit sign register (B SIGN). This second operand register, [EPB(B SIGN)FMB], serves
as a temporary accumulator to hold the argument fetched from core.
The exponent registers store the exponents associated with floating point numbers and are not used
during integer operations. Basically, if two numbers (integer or floating point) are to be manipulated,
one number is loaded in the floating point accumulator by a load type instruction. The second number
is normally loaded in the temporary accumulator [EPB(B SIGN)FMB] by an instruction specifying an
arithmetic operation. Both numbers are gated into a 36-bit adder, where the arithmetic operation is
performed. The result is then transferred to the floating point accumulator. The major registers are
described below:
Memory Buffer Register — A 36-bit register that provides the FP15/memory interface. All data
transferred into the FP passes through this register.
Adder - A 36-bit arithmetic logic unit (ALU) that serves as the central point in the FP15 and
performs all arithmetic and logic operations. The output of the adder is connected to all major
registers via an adder bus.
A SIGN - A 1-bit register used to store the polarity of the associated operand (A mantissa).
EPA - An 18-bit register used to store the 2’s complement of the exponent associated with the
mantissa loaded in the FMA. The most significant bit of the EPA represents the sign of the
exponent; in single precision floating arithmetic, the most significant bit of the exponent is bit 09.
It is therefore necessary to extend the value of this bit from bits 00 through 08. If bit 09 is a 1, bits
00 through 08 in the EPA are forced to 1s, and if bit 09 is a 0, bits 00 through 08 in the EPA are
forced to 0s. The EPA and FMA serve as the floating point accumulator.
FMA - A 35-bit register used to store the integer in integer arithmetic, or the mantissa in floating
point arithmetic. The binary point is located between bit 00 and bit 01 of the FMA.
FMQ - A 35-bit extension of the FMA register used during multiplication and division
operations.

B SIGN - A 1-bit register used to store the polarity of the associated operand (B mantissa).
EPB - An 18-bit register used to store the exponent associated with the mantissa in the FMB. The
most significant bit of the EPB represents the sign of the exponent. In single precision arithmetic,
where the most significant bit in the EPB is bit 09, the value of this bit is extended to bits 00
through 08 (refer to EPA register). The EPB and FMB serve as a temporary accumulator to store
the argument fetched from core. The EPB is a dynamic register and is therefore not directly
accessible by software.
FMB - A 35-bit register used to store the integer in integer arithmetic or the mantissa argument in
floating point arithmetic. The binary point is located between the most significant bit (bit 00) and
bit 01 of the FMB. The FMB is a dynamic register and is therefore not directly accessible by
software.
JEA (JMS Exit Address) - A 17-bit register used to store two status bits and a 15-bit base exit

address for floating point interrupts. When an interrupt condition (overflow, underflow, abnormal division, or memory protect violation) occurs in the FP15, the base exit address (a unique
address for each type of interrupt) is returned. This indicates a service routine associated with the
interrupt. The guard bit is used in rounding operations.

2-22

Shift Counter — The shift counter performs the following functions:

-0 a6
o

Keeps track of the number of words to be fetched from memory during the OPAND
cycle.
Keeps track of the number of words written into memory during the WRITE cycle.
Keeps track of the number of shifts required for multiply and divide operations.

Limits the number of shifts during normalizing to a maximum of 35.
Controls the number of shifts required during alignment.
Checks for exponents having differences which exceed 35,0.

Diagnostic Instruction Register (DIR) - The 7-bit DIR determines the number of steps through
which an instruction is to be sequenced.

Diagnostic Address Register (DAR) - The 15-bit DAR specifies the address in core where the
contents of the registers are to be stored.

2-23

CHAPTER 3

Section 1.

Input/Output Peripherals

MEMORY

C
UNIBUS

PERIPHERALS

PERIPHERAL
PROCESSOR

PROCESSOR

r PROCESSOR

CENTRAL

[

MEMORY

UNIBUS

[

PROCESSOR

I/0

—

I/0 BUS

FLOATING
POINT

PROCESSOR

15-0855

There is a comprehensive range of peripherals available, built especially for the XVM 1/0 bus. The

peripherals cover almost the entire spectrum of computer usage. For the user who wishes to expand
into a new realm of data processing, the Computer Special Systems department of DIGITAL will cater
to the demands of interfacing the XVM system to non-standard devices.

The more general types of peripherals attached to the XVM 1/0 bus are described in this section. One
sub-section is allotted to each option, arranged in alphabetical order:
AA15-B*
ADI15*
BD15*
CRI15
DCOI1-ED
DP09-A
GTI15
LA36

LPI15
LTI15-A
LT19-D
PC15
RF15
RP15

TCI15
TCS59-D
VP15

VTS50
VWO01-B
XY15

Digital-to-Analog Multiplexer Control
Analog-to-Digital Converter
Industrial Control System (AFC-15/UDC-15)
Card Reader Controller
Eight-Terminal Asynchronous Line Scanner
Synchronous Communications Control
Graphics Sub-system
DECwriter 11
Line Printer Controller
Single Terminal Asynchronous Line Control
Multi-Terminal Asynchronous Line Control
High-Speed Reader/Punch Control
DECdisk Controller
Disk Pack Controller
DECtape Controller
Magnetic Tape Controller
Point-Plot Display Control
DECscope Video Terminal
Writing Tablet
X-Y Plotter Controller

*Currently available only on a special order basis.

AA15-B DIGITAL-TO-ANALOG MULTIPLEXER CONTROL
The AA15-B is an XVM-compatible option for controlling up to 32 digital-to-analog converters. The

converters have a double-buffered, 12-bit input, and a bipolar output with a range from -10.24 to
+10.235 V. Data is transferred by the XVM system processor to the AA15-B via its accumulator (AC)
and the 1/O bus.

The maximum capacity of the system is 32 digital-to-analog converter channels. The 18-bit word
transferred from the AC to the AA15-B contains both the channel address (bits 00-05) and the data
word (bits 06-17).
IOT Instructions

Mnemonic

Code

ACB
ALSC
AUEC
ALSU
ALEC
ALU
ACA
ACAB

705101
705102
705104
705106
705122
705126
705132
705133*

Description

Clear B Buffer, all channels.
Load selected channel.
Update every channel.
Load selected and update every channel.
Load every channel.
Load and update every channel.
Clear A Buffer, all channels.
Clear Buffers, all channels.

Analog Output Specifications
Absolute Accuracy
Linearity
Resolution
Temperature Coefficient
Output Voltage Swing
Output Current
Output Impedance
Output Slewing Rate
Settling Time
Electrical
Input Voltage
Input Frequency
Power Dissipation
Mechanical

Mounting

Environmental
Temperature Range
Humidity Range

£0.05%
+0.5L.S.B.
1 part in 4096
+40 ppm/°C
-10.240 Vto +10.235V
+5mA
100 m ohm
10V /us
10 us to +0.05% of full scale

115/230 Vac, single phase
47-63 Hz
60 W

10.5 in. logic assembly mounted in HO15 cabinet (H950)

0°-50° C (32°-122° F)
10-90% without condensation

*Also clears the XVM accumulator.

3-2

AD15 ANALOG-TO-DIGITAL CONVERTER
The ADIS5 is a flexible high-performance, multichannel analog-to-digital conversion subsystem interfaced to the data channel of an XVM computer. Offering conversion rates of up to 22,000 per second,
the AD15 satisfies laboratory, industrial and general purpose data acquisition applications.

The AD15 provides 13-bit digitization of up to 128 single-ended, bipolar analog signals having a
nominal full-scale programmable input selection range of +1.25, £2.5, £5.0, and £10.00 V. This
performance allows input voltage as low as £300 uV to be detected. An integral sample and hold
amplifier (S & H) provides a subsystem conversion aperture of 100 ns.

A choice of operating modes enables data transfers through either the accumulator or data channel
with random or sequential sampling and internal or external synchronization (Figure 3-1).

ran

[ X])

SINGLE -ENDED

ANALOG INPUTS

PROGRAM

SELECTABLE

N
Ve

; )]
{&

GAIN AMP.

(READ

SAMP.

8 HOLD

—a

JX)

AMP

12-BIT

AND SIGN

ADC

o | ONLY)
[al

a311} 1

SAMPLE/

XVM

A124 MULTIPLEXE

SWITCHES {GROUPS

TIMING
X1,X2,X4,X8

TO128

S(\

(9.9)

AND

CONTROL

Eu )

(WRITE/
READ)

_
CHANNEL SELECT
EXTERNAL

SYNC
15-0850

Figure 3-1

ADI15 Analog-to-Digital Conversion Subsystem

The add-to-memory feature allows a converted analog input to be added to the contents of a memory
location. If the value added to memory is sufficient to cause a sign change in the result, an interrupt
will occur should the programmer so desire.

External synchronization may be used to trigger the analog-to-digital converter, thus allowing external

real-time response and signal averaging.

Gains of 1, 2, 4, and 8 may be selected on the basis of the voltage range of the analog inputs.

The system provides bipolar operation of up to

10 V. Overload protection is £20 V. Recovery time is

adequate to perform the next conversion within the specified accuracy.

“Power off”’ isolation and channel-to-channel isolation are maintained during power off periods.

3-3

IOT Instructions

Mnemonic

Code

ADCV

701304

ADRB

701302

ADRS

701342

ADCF

701362

ADSF

701301

WCSF

701341

MSSF

701321

System Specifications
Resolution
Code
No. of Analog Inputs
Input Voltage Range
(Program Selectable)
Analog Input Connectors
Overload Capability
Noise
Cross Channel Attenuation
Input Gain

Description
Load status register from accumulator, clear A /D
done flag, and initiate conversion.
Read data buffer into accumulator and clear A/D
done flag.
Read status register into accumulator.
Clear all ADI5 flags.
Skip on A/D flag.
Skip on word count overflow flag.
Skip on memory overflow.

12 bit + sign, 1 part in 4096 of full
scale, 1 partin 8192
2’s complement, extended sign, right justified
4 minimum, expandable to 128 in groups of 4
+1.25V,£2.5V,£50V,£10.0V full scale

16-channel Amphenol
(Mating connector supplied) or BNC
+20V on all ranges without damage
Less than £4 mV (p-p) RTO, 3 sigma confidence
-80 dB, 20 Vdc, 400 Hz for (p-p) signals,
100 ohm source impedance
Program selectable

Modes of Operation

Synchronization
Data Transfer
Multiplexer
Data Channel Addresses:
Status Word Count
Status Current Address
Data Word Count
Data Current Address
API Address
API Priority
Accuracy

Quantizing Error
Throughput Rate
Conversion Aperture
Temperature Coefficient
Offset
Input Impedance

Input Isolation

Internal or external
Program or data channel

Random or sequential

24
25
26
27
57
0

+0.4% +1/2 L.8.B. (including S & H
and multiplexer)
+1/2L.S.B

22 kHz (including S & H
and multiplexer)
100 ns
+£30 ppm/° C
+£20uV/°
CRTI£50uV/°
CRTO
1000 megohms in parallel with 20 pF
(exclusive of wiring capacitance)
Enhancement mode MOSFET switches, ““off”’
when unselected or power off

Power Requirement
Input Voltage
Input Frequency
Power Dissipation

Single Phase
115 Vac/230 Vac, single phase
47 to 63 Hz, single phase
150 W

Mechanical
Dimensions
Weight

Mounted in H950 cabinet
1751b (79.4 kg)

Environmental
Temperature Range

0°-50° C (32°-122° F)

Humidity

10-90% without condensation

BD15 (AFC15/UDC15) INDUSTRIAL CONTROL SYSTEM (Figure 3-2)

The Universal Digital Control (UDC-15) and Automatic Flying Capacitor (AFC-15) subsystems have
been integrated to offer a unique, highly flexible digital input/output and analog data acquisition
system for use with XVM computers. A single controller, the BD-15, acts as an interface between the
computer and the UDC-15 and AFC-15 subsystems. All communications between the computer and
the BD-15 controller are done through the 1/O bus via the accumulator.

AFC- 15
AUTOMATIC
FLYING

CAPASITOR

UNITS 1N
>

XVM

PROCESSOR

I/0 BUS

ANALOG
SUBSYSTEM

2048

eINPUTS

MAXIMUM

BD-15

CONTROL
ubC-15
UNIVERSAL
DIGITAL
CONTROL

4096 INPUTS

UP TO 11
UNITS IN

l+—> AND/OR
OUTPUTS MAXIMUM

DIGITAL
SUBSYSTEM

15-054I

Figure 3-2

Industrial Control System

UDC-15 Digital Input/Output Subsystem
The UDC-15 is a digital information input/output option for industrial and process control applications. Through the central control unit (BD-15), it interrogates or drives up to 256 directly addressable digital sense and control functional /O modules, each module containing 16 digital points for
total system capability of 4096 digital points.

Automatic hardware logic rapidly identifies interrupting inputs according to input module type and
address. Input change of state and direction are determined by hardware gating. Since both features
are hardware implemented, the computer overhead usually associated with digital 1/O is significantly
reduced.

The UDC-15 and its controller, the BD-15, operate under computer program control as a high level
digital multiplexer which interrogates digital inputs and drives digital outputs located in directly
addressable modules. A 16-bit word transferred from the XVM accumulator and decoded in the BD15 controller selects the address of either an output or an input module. Depending upon the module
type selected, a 16-bit data output word can represent the single digital word required by a D/A
converter or a counter, or 16 individual points for contact closure, pulse outputs, etc.
3-5

Input data is similarly handled. For example, a single 16-bit word can represent a counter or 16 contact
sense points or 16 contact interrupt points. A “COS” gate function permits the system to detect any
change of state and/or direction from the previous sampling before the word is transferred into the
accumulator of the XVM (Figure 3-3).

I/0 BUS

DATA (16

RECEIVERS

BITS)

]

X VM

;

STATUS

(16 B1Ts) L__REGISTER

[

DATA

OUTPUT

S ].__
]I COS GATE
T

cos

INPUT

ADDRESS
(8 BITS)

l——_—'

ADDRESS / SCAN

i REGISTER

—

(TTITIT]

FUNCTIONAL
MODULES

DRIVERS

MODULE

FILE

UNIT

15-0851

Figure 3-3

UDC-15 Input/Output Operation

AFC-15 Analog Input Subsystem
The AFC-15 is an analog data acquisition subsystem for industrial and process control. Under control
of the BD-15, the AFC-15 subsystem will multiplex up to 2048 differential analog inputs. The signals
will then be converted to a 12-bit digital word and routed to the processor. The variable gain, selected
by program and the signal conditioning modules, allows the subsystem to handle a wide range of input
signals.
The AFC-15 analog input subsystem is particularly suited for data acquisition in the high-noise environments encountered in process monitoring and control, production testing, and laboratory applications. In such environments, common and normal mode noise, cabling, and grounding problems can
greatly affect the operation of such transducers as thermocouples, strain gages, analytical bridges, and
industrial milliamp current transmitters. These problems can also affect the accuracy and performance
of the measuring system.

The flying capacitor multiplexing_technique permits microvolt signals to be isolated, switched and
digitized by an analog-to-digital converter with a high degree of noise immunity.

The flying capacitor is a two-pole RC filter network in which a second or “flying” capacitor is charged,
then isolated, and switched to the measuring circuit. Since the source is never directly connected to the
measuring circuit, extremely high isolation (10'2 ohms) is achieved (Figure 3-4).

3-6

NORMALLY
CLOSED
o

_
S

TWISTED

PAIR INPUT
J

SCREW

“
<4

NORMALLY
OPEN
o

;
:

FLYING

I\,

ISOLATION

(SOLID STATE SWITCH)

ADC

SIGNAL CONDITIONING
MODULE

FILE

:
!
I

CAPACITOR

TERMINALS

UNIT
ISOLATION
RELAY
Ao

J\.

MULTIPLEXER
MODULE

PROGRAMMABLE
GAIN AMPLIFIER
15-0545

Figure 3-4

Flying Capacitor Circuit

Lo-pass filtering per point (2.5 Hz cutoff) plus thé high isolation of the flying capacitor technique
provides high common mode noise rejection (120 dB at 60 Hz) without requiring expensive individually shielded input wiring.
AFC-15 Specifications

Resolution

Sign + 11 bits (2’s complement)

Accuracy

(for direct input)
Repeatability
Scan Rate,
- Including A/D Conversion
Normal Mode Rejection
Common Mode Rejection
Input Overload
Effect of Overload
Channel-to-Channel Isolation

Gain Accuracy
Gain Linearity
Temperature Coefficient
Gain:1,2
Gain: 10 to 1000
Noise
Offset

+0.05% of f.s. or £25 uV (whichever is larger); +1/2 L.S.B.
+0.05% or £10 uV same channel; £0.05% or £20 'V channelto-channel (whichever is larger); £1/2 L.S.B.
200 channels/second, maximum (20 samples/second,
channel)
53 dB for frequencies 60 Hz or above
120 dB dc to 60 Hz
Amplifier fused against overload
Recovers to within stated accuracy for next channel

10!2 ohms at dc, channel-to-channel; 108 ohms at dc, channels
on same multiplexer module
+0.02%
+0.01%
10 uV/° C RTI

0.3 uV/° CRTI + 100 pV/° C RTO
7 uV p-p RTI + 500 uV p-p RTO
Adjustable to zero

Electrical

Input Voltage
Input Frequency
Power Dissipation
Mechanical
Mounting
Weight

same

115/230 Vac, single phase
47-63 Hz
200 W

Mounted in its own H950 cabinet
150 1b (68 kg)

Environmental
Temperature Range
Humidity Range

10-50° C (50° - 122°F)
10-90% without condensation

BD15 SPECIFICATIONS
Electrical
Input Voltage
Input Frequency
Power Dissipation

115/230 Vac, single phase
47-63 Hz
200 W

Mechanical
Mounting
Weight

Mounted in H950 cabinet
150 1b (68 kg)

Environmental
Temperature Range
Humidity Range

0°-50° C (32°-122° F)
10-95% without condensation

UDC-15 Specifications
Modes of Operation

Programmed digital output, programmed digital input, and
interrupt-controlled input.
Data format
16-bit I/O data words
Digital inputs/outputs
256 16-bit words maximum
I/O module selection
Directly addressable
Interrupt module identification Module type code and module address
Interrupt scan
Locates address and type in 5 microsecond (typical); 20 us
(worst case)
I/O data rate
105 16-bit word/second
Computer interface
Direct interface to XVM
System clock rates
Three available to each 1/O word: line frequency 1.0 Vac; 175
Hz 1.75 kHz, adjustable; 1.75 kHz 17.5 kHz adjustable
Environmental
Temperature Range

Humidity Range

Cooling/filtering

0°-50° C (32°-122° F)
10%-95% without condensation
Dust filters and blowers provided in H963-R Cabinet, bottom
exhaust

Electrical
Input Voltage
Input Frequency
Power Dissipation

115/230 Vac, single phase
47-63 Hz
200 W

Mechanical
Mounting
Weight

Mounted in H950 cabinet
150 Ib (68 kg)

CR15 CARD READER CONTROLLER
The CR 15 Card Reader Controller is designed to read reliably the industry standard 80-column card.

The option consists of two main parts - the CR15 Controller, and the CR04 Card Reader. In addition,
there are two types of card readers; one which reads at 300 cards per minute; and another which reads
at 1000 cards per minute:

CR15-D - 1000 cpm reader plus interface
CR15-F - 300 cpm reader plus interface

Both systems are available in 115 V, 60 Hz versions as well as 230 V, 50 Hz.

The CR15 has device I/O handlers to enable the unit to be used under any of the currently supported
XVM software systems. The Controller operates in either of two modes:
1.

Program Controlled Transfer - Where the I/O handler relies upon the interrupt system to
indicate when the next column of data is waiting to be read.

Data Channel Transfer — In this mode, the controller will transfer the contents of a card to a
predefined buffer; an interrupt will only be generated when the entire card has been read, or
when the required number of words have been read. (For a detailed explanation of multicycle data channel, refer to Paragraph 1.3, Chapter 1.)

IOT Instructions

Mnemonic

Code

CRCON

706704

Operation
Load control word from accumulator.

CLEAR
STATUS

ENABLE

READ A

INTERRUPT

CARD

OFFSET
A CARD

ENABLE
DATA
CHANNEL
15-08438

CRSKP

706701

Skip if card reader interrupt is set.

CRLD

706702

OR CR data buffer into bits 6—17 of AC.

CRLS

706772

Read CR status into AC.

CRPC

706724

Clear status register (except end of card bit).

PHOTO
ERROR

PICK
ERROR
MOTION
ERROR

DATA
MISSED

HOPPER
EMPTY/

TROUBLE

STFACKER

BUSY

ON LINE

END OF
FILE

DATA
END OF
CHANNEL
CARD
ENABLED
READY
WORD
DATA
TO READ
COUNT
READY
OVERFLOW

ULL
15-0849

3-9

Data Channel Addresses
Word Count

Current Address

API Address

API Priority

Card Reader Specifications

CR15DA* and CR15DB

CR15FA* and CR15FB

Table Top

Reading Rate (cpm)

1000

300

Input Hopper Capacity (cards)

950—-1000**

550—600**

Output Hopper Capacity (cards)

950—1000**

550-600%**

Size Envelope (H X W X D)
Inches

17X 24 X 19

13
X 20X 15

Centimeters

43 X 61 X 48

33 X 50 X 38

Weight (max.)
Pounds

100

Kilograms

45.4

31.8

Power Consumption (VA)
Starting

1500

Running

460

1500

1600

Heat Dissipation

Btu/hour
Controller
Electrical
Input Voltage

115/230 Vac, single phase

Input Frequency

47—63 Hz

Power Dissipation

100 W

Mechanical
Mounting

5.25 in. logic assembly mounted in LP15 cabinet

(H950)
Environmental

Temperature Range

0°—50° C (32°—=122° F)

Humidity Range

10—-95% without condensation

*A suffix denotes 115 V, 60 Hz; B suffix denotes 230 V, 50 Hz
**Depending on card stock

3-10

DCO01-ED EIGHT TERMINAL ASYNCHRONOUS LINE SCANNER
The DCO1-ED scanner is designed as an efficient monitoring device requiring a minimum of computer
control. The scanner, once started, continuously samples all eight device lines. When an active line is
sampled and found to have set flags, an indication is given to the computer. A raised flag indicates that
a device has been active, If the flag is sensed following transmittal of data, that data is in the receiver
awaiting read-in. Because an active teletype does not give an indication whether data has been transmitted or received, the computer must monitor the status of every device (Figure 3-5).

1/0 BUS

DCO1-ED

XVM

COMPUTER

TERMINALS

Figure 3-5

15-0847

DCOI1-ED Block Diagram

Operation is in the half-duplex mode with local or remote echo or echo-plex connection. Transmitted
data is hardware echoed and the same data received, thereby allowing the programmer a means of

verifying the accuracy of the data input to the terminal.

A serial-start-stop code is used. Data words may be composed of from five to eight bits.
Serial-to-parallel and parallel-to-serial conversions are accomplished within the DCO1-ED for each of
'
the eight serial lines.
Receive Operation

An IOT instruction enables the scanner which sequentially samples each of the eight serial lines searching for a receive flag. When a flag is recognized, the scanner stops and an interrupt is requested. (The
XVM must recognize only this one flag.) The service routine may be called for by either program
interrupt (PI) or by automatic priority interrupt (API). The active line number and the received data
are read into the computer accumulator by means of an IOT instruction; the scanner is then released.
Transmit OQperation

The scanner is stopped and loaded with a line number by means of program instruction. The character
to be transmitted is loaded into the appropriate transmitter of the DCO1-ED by the logic. Then the
scanner is released. No transmit-done flag exists. All transmitted data is echoed back to the receive
logic; therefore, only one flag is required for each connection. Comparison of the transmitted character with the received echo must be performed by the software.
Error Detection

Both total loss of data and dropping of bits down the transmission line can be detected by the software.
Operator error (using the terminal keyboard during message transmission) is detected in a similar
manner.

3-11

IOT Instructions
Code

Description

SSF
RSD

70XX01
70XX02

DIS

70XX04
70XX21
70XX22
70XX24

Skip on scanner flag.
OR the scanner line number and the selected
receiver flag and the scanner flag.
Disable scanner (stop scanner and clear all flags).
Stop scanner and load scanner line register.
Load selected transmitter line data.
Clear scanner flag and start scanner at present line
number.
Stop scanner, load line address and transmitter,
and restart scanner at selected line address.

Mnemonic

LSA
LSD
STS

70XX27

Specifications
Capacity

To eight terminals, private modems, or other serialized terminal
equipment

Line Driving Capability
Transfer Rates

20 mA current-loop (1500 feet) at 110 baud; EIA levels (50 feet)
75,110, 150, 300, 600, 1200 and 2400 baud. Additional rates
optional

Rate Assignments

Strappable per Transmit/Receive pair

Operational Mode

Half-duplex with echo or echo-plex

Data Code

Five to eight bit serial-start-stop

Stop Code

1, 1.5 or 2 units

Environmental

Temperature Range

0° —50° C (32° - 122°F)

Humidity Range

10—-95% without condensation

Electrical

Input Voltage

115/230 Vac, single phase

Input Frequency

47—-63 Hz

Power Dissipation

400 W

Mechanical

Mounting

Up to four DCO1 units may be mounted in an H950 cabinet

Weight

200 1b (90.7 kg)

3-12

Unit No.

Device No.

Subdevice No.

API Address

0-2

4—6

0-2

4
5
6
7
8

45
46
46
47
47

4—-6
0-2
4—-6
0-2
4—6

73
74
75
76
77

INPUT/ OUTPUT BIT PATTERN

MSB

U;E

ADDRESS

Q;SB

LSB/

TASB

J; USED TO

ADDRESS

CLEAR
TR FLAG

8-BIT ASCII CHARACTER

AC BIT

453
15-0846

3-13

DP09-A SYNCHRONOUS COMMUNICATIONS CONTROL

The DP09-A is a bit-synchronous data communications interface and control. It may be used to
connect the XVM I/0O bus to serial communications devices such as the Bell System type 201 or 301.
Operation is full duplex, both transmit and receive sections being double-buffered. Character length
may be from 5 to 9 bits, and is selected by different jumpers on a 50-pin Cannon connector.
The DPO09-A is in the idle state until made active by either the XVM processor transmitting a sync
character to the DP09-A or the DP09-A receiving a sync character from the data set.
The sync characters are:
Character Length (N)
6
7
8
9

Sync Character
010110
0010110
10010110
X10010110

(X not used in sync character
determination)
The DP09-A will return to the inactive (idle) state if:
1.

While transmitting, Idle mode is disabled and no character has been transferred to the
DP09-A from the computer within Nt us of the transmit flag being set. (N is the number of
bits/character, t is the time to transmit a bit on the line. Nt is therefore the time to transmit a
full character on the communications line.)
While receiving, the Clear Receive Active (CRA) command is issued, or if no character is
received from the communication line for 1.5 bit times.

Idle mode is a feature of the DP09-A which permits retaining the communications system in an active
(and synchronous) state when no new characters are available. When Idle mode is enabled, the last
character continues to be transmitted until such time that a new character is ready. The transmit flag
continues to be raised at the end of each character transmission.
IOT Instructions

Mnemonic

Code

Description

SRE
CRE
SRI
CRF
STR
CTR
SSR
CRA
STF
TAC
CTF
CIM
SIM
SRF
RRB
SEF

702544
702604
702561
702562
702564
702602
702601
702622
702521

Set Ring Enable
Clear Ring Enable
Skip on Ring Indicator
Clear Ring Flag
Set Terminal Ready
Clear Terminal Ready
Skip on Data Set Ready
Clear Receive Active
Skip on Transmit Flag

CEF

702501
702502
702504
702524
702621
702522
702541
702542

Transmit a Character
Clear Transmit Flag
Clear Idle Mode
Set Idle Mode
Skip on Receive Flag
OR Receive Buffer to AC
Skip on Receive End Flag
Clear End Flag

3-14

Specifications
TRANSMIT FLAG

RECEIVE FLAG

Set when DP09-A is ready to receive a character from the computer for transmission.

Set when the DP09-A is ready to transfer a character to the
computer.

RECEIVE END FLAG

RING FLAG

Set when no bit is received from the sending device within 1.5t (t
is the normal interbit spacing, the reciprocal of the baud rate).
Set when a remote communications device calls up the DP09-A
and is ready to transmit. Only causes an interrupt if Ring
Enable is set (see instruction list).

DATA SET READY FLAG

Set when the local Data Set is ready for operation.
(This flag cannot cause an interrupt)

API Address

API Priority

Mechanical
Mounting

10.5 in. logic assembly mounted in negative bus cabinet

3-15

b NS

GT15 GRAPHICS SUBSYSTEM
The GT15 Graphics Subsystem consists of four interconnected units:
VT15 Graphics Processor
VV15-A Arbitrary Vector Generator

VTO07 Graphics Console (or VT04)
VLO7 Light Pen (or VL04)

VT1S Graphics Processor
The VT 15 Graphics Processor is connected to the XVM Processor via the 1/0 bus (Figure 3-6). Once
the VT 15 has received the start signal and address, it will run continuously. The display file for the
VT15 is held in XVM memory so that the XVM Processor and VT 15 processor interact easily through
the hardware; their programs can interact in memory.

DATA AND

XVM

COMPUTER

XYM

VT15

GRAPHIC
170 BUS | PROCESSOR|

ONTROL

BUS

DISPLAY
ANALOG Bus |CONSOLE

15-0613

Figure 3-6

VT15 Graphic Processor, Block Diagram

Two 18-bit registers are used for memory buffer functions which permit overlap for memory cycle
times and allow faster instruction execution times. The VT15 has a set of basic machine language
instructions that give the Graphic 15 System the utmost versatility in the display of points, basic
vectors, graph plots, and ASCII characters.

Vectors are drawn on the scope by use of a “stroke vector” technique for maximum speed and
accuracy.

VT15 Specifications
Virtual Paper Size

12 bits X 12 bits

Screen Display Size
Scales
Brightness
Line Types

10 bits X 10 bits
4-bit increment register (0-15) characters and vectors
3-bit register (8 levels)
4; 1 solid and 3 types of broken lines

~ Vector Specification
Point Specification
Name Register

Synchronization
Characters

Relative
Absolute
6 bits (128 values)

Display refresh rate can be synchronized to line frequency or

harmonics

64 printing characters

4 special (alt mode ESC, CR, LF, TAB)

Controller
Electrical

Input Voltage
Input Frequency
Power Dissipation

115/230 Vac, single phase
47-63 Hz
1.0K W
3-16

Mechanical

Mounting
Weight

Mounted in H950 cabinet
300 Ib
(136 kg)

VV15-A Arbitrary Vector Generator
The VVI15-A Arbitrary Vector Generator computes the angle of a vector from its X and Y components. The VV15-A speeds up the display and saves space in memory by reducing the size of the
display files.
VTO07, VT04 Graphics Console (Figure 3-7)
The VTO07 and VT04 are rectangular self-contained CRT monitors with CRT power supplies, deflection amplifiers, and six console pushbuttons which generate program interrupts. Provision for implementing a light pen, writing tablet and keyboard options is also included.

Figure 3-7

VTO07 and VT04 Graphic Display Consoles

3-17

VTO07, VT04 Specifications
VTO04

VTO07
Screen Size

21 inches diagonal

17 in. diagonal

CRT Shape

Rectangular, 12 in. X 14 in.

Rectangular, 9 in. X 10-1/2 in.

Major Display Area

12 in. X 12 in.

9in. X 9 in.

Minor Display Area

2in. X 12 in. (programmable)

1-1/2in. X 9 in.

Vector Drawing Rate

0.33 in. per us

0.25 in. per us

Flicker-free* Presentation

10,000 vector inches

7,000 vector inches

Character Drawing Capability

2,800 maximum

Same as VT07

Spot Size

0.015 in. (within 10-in.

Same as VT07

diameter circle about CRT
center)

Spot Jitter
Display Drift

0.005 in.

Same as VTO07

1% of full screen (over 24

Same as VTO7

hours)

Spot Repeatability

+0.020 in.

Same as VTO7

Linearity

+0.5% of full screen

+1% full screen

Brightness

30 ft lamberts (min) with 100

50 ft lamberts with 200 line

line raster

raster PT385 standard, others
optional

Physical Dimensions

51-1/2 X 30-3/4 X 45-3/4 in.
(130.8 X 78.1 X 116.2 cm

Power Dissipation

At 110Vac 12 A surge, 6 A
running

Environmental
Temperature Range

5°— 35°C (40°— 95°F)

Humidity Range

20—-55% (relative)

*Assuming no CPU intervention

3-18

Same as VTO7

VL07, VL04 Light Pen
The VLO7 (or VLO4) Light Pen is a photosensitive device that detects the presence of illuminated
phosphors on the screen of the VT07 (or VT04). The light pen photo-amplifier is interfaced to the
VT15 Graphics Processor via the VT07 (or VT04) logic panel. The uses of the light pen depend upon

the program, but normal software includes routines to allow the light pen to indicate unwanted lines,
draw new lines, and choose routines by indicating legends in the “menu” or “offset” area on the
display.
VM1S Display Console Multiplexer
The VM15 Display Console Multiplexer permits up to four Type VT07 or VT04 Display Consoles,
and four Type VLO7 or VL04 Light Pen options to be interfaced with a single VT 15 Graphic Processor. This option permits these equipments to be situated at remote locations and to share the use of the
VT 15 Graphic Processor and XVM computer.

NOTE
The maximum number of display consoles is four,
however the video display is limited in the number of
vector inches it can support. Two consoles can be
handled easily without noticeable flicker.

3-19

LA36 DECwriter 11

The LA36 DECwriter I1 is a fast, reliable, data terminal. The unit prints at a speed of 30 characters per
second continuously. If, due to a carriage return or other control character, the 16-character buffer
should have more than one character in it, then a 60-character per second ‘“Catch-up’’ mode is used to
clear the buffer. Data entry is made from a 96- or 128-character keyboard.
The DECwriter II will make a hard copy original plus up to five copies on any width of continuous,
tractor-driven paper between 3 and 14-7/8 inches wide.

The LA36 is compatible with all XVM Terminal Controllers, e.g., DCO1-ED, LT19-D, LT15-A, and is
also the standard console terminal device on XVM Systems.

Standard Features

True 30-character per second throughput
Accommodates 6-part form (0.020 maximum thickness)
Handles variable width forms; 3 through 14-7/8 in. wide
132-column printing; 10 characters per inch horizontal
6 lines per inch vertical spacing
128-character ASCII upper/lower case set
7 X 7 dot matrix
ANSI-standard typewriter-like keyboard
Quiet operation
Excellent character readability

Integrated, 20 mA current loop interface with jumpers for active and passive modes
Fine vertical adjustment for accurate forms placement
Optional Features
Paper stacking tray
Casters for rear of cabinet
Right and/or left work surface
Operator Controls
Power On-Off

Applies and removes ac power to entire machine

Line/Local

Selects on-line or local operation

Baud Rate-110, 150, 300

3-position switch selects the baud rate clock frequency for communications line operation

Forms thickness adjustment

Located on right side of print head carriage. Selects
proper gap for 1-through 6-part form. Approximately 1 click for each part.

Right tractor adjustment

Thumb screw may be loosened to allow movement
of right iractor for various forms widths

Fine vertical tractor release

Line feed knob may be pressed inward and rotated
in the appropriate direction for precise location of
printing with respect to vertical zones.

3-20

Specifications
Main
Printing Speed
Number of columns
Printing characters
Keyboard characters

30 char/sec, asynchronous
132
64/96 character ASCII set
97 or 128 (switch selectable)

Printing
Type

Vertical spacing

Horizontal spacing

Impact 7 X 7 dot matrix
6 lines/inch
10 char/inch

Paper

Type

Slew speed

3-14-7/8 in. wide, continuous form tractor-driven, original plus
5 copies (20 mils maximum pack thickness)
30 lines/sec

Mechanical
Mounting
Size

Weight

1 free-standing unit
33.2 inches high (84.3 cmm) X 27.5 inches wide (69.8 cm) X 24
inches deep (61 cm)
102 Ib (46.3 kg)

Power

Input current

Heat dissipation

2Aat115V,1 A at230 Vac
300 W printing; 160 W nonprinting

Environment
Operating temperature
Relative humidity

10° C to 40° C (50° - .104°F)
10% to 90%

Ribbon

Digital-specified nylon fabric, spool assembly 0.5 inches wide X
40 yards. Order No. 36-10558

3-21

LP15 LINE PRINTER CONTROLLER

The XVM Systems currently have three models of LP15 Line Printers available. The types and their
differences are:

Option

Lines/Min

LP15-R
LP15-V
LP15-W

1200
300
300

Columns

Characters

132
132
132

64
64
96

All of these printers may use the same system programs, allowing for the differences in line lengths and
considering that the 64-character printers convert all lower case character codes to upper case before
printing.

Once started by an LPP1 or LPPM command, the line printers use the multi-cycle data channel facility
of the XVM to access a character buffer in core. This buffer contains up to 256 lines of characters, each
line terminated by a line feed or other control character. In this way, up to 256 lines may be printed
without further attention from the program.

The data buffer area must begin with a 2-word header in the format shown (Figure 3-8).

wooo LI

[T T ITTTPTTTVTTIT]]
-

LINE COUNT

NOT USED BY

» 0=1I0PS ASCII

NOT USED BY

1= IMAGE ALPHA

LP15 INTERFACE

T TP

woros L1 4

NOT USED BY LP1% INTERFACE

Figure 3-8

15-0419

LPI15 Data Buffer Header Format

Bit 0 and bits 9-16 of header word 1 are not used by the hardware. Bit 0 indicates the line printer mode
of operation to the software. It is set in multi-line mode and cleared in single-line mode. Bits 9-16
contain software flags not used by hardware.
Data Word Formats

TOPS ASCII (5/7 ASCII Packing Scheme)
In the IOPS ASCII format, five 7-bit character codes are contained in two consecutive
words, as shown below.
0

HEEEEREEENEEREEEEEEN
T

1t CHARACTER
0

2nd CHARACTER

3rd.

HEEEEEREEEEEREREEND
3rd

4th CHARACTER

Sth CHARACTER

15-0420

3-22

IMAGE ALPHA Format

CTTTT I T
o

T L LI T
M

1st CHARACTER

NOT USED

HNEEEENEEENEEEEEER

‘

NOT USED

T 2nd CHARACTER
15-0421

IOT Instructions

Mnemonic

Code

Description

LPPI1

706541

The line printer prints a single line of text.

LPPM

706521

The line printer enters Multi-line mode.

LPSF

706501

Skip if Done or Error. Skips the following instruction if the printer’s Done or Error flag is set.

LPEI

706544

Enable interrupt system. Connects the printer to
the XVM priority interrupt system. Either the
Done or Error flag will cause an interrupt if
enabled.
Clear Done flag.
Clear status register and Error flag.
OR status register. This IOT reads into the AC a

LPCD

706621

LPCF

706641

LPRS

706642

Bit
0
1
2
3
4
5
6

Flag
Error
LP Alarm
Line Overflow
Illegal HT

Busy
Done
Interlock

Data Channel Addresses and Priority

Word Count
Current Address
API Address
API Priority
Controller
Electrical
Input Voltage
Input Frequency
Power Dissipation

34
35
56
3

115/230 Vac, single phase
47-63 Hz
400 W

3-23

Mechanical
Mounting
Height

Mounted in H950 cabinet
200 1b (90.7 kg)

LPOS Printer
Electrical
Input Voltage
Input Frequency
Power Dissipation

115/230 £ 10% Vac, single phase
50/60 Hz + 2%
500 W

Environmental

‘

Temperature Range
Humidity Range

Mechanical
Dimensions
Weight

50°-100° F (10° - 38°C)
30-90% without condensation

22(56 cm) X 34 (86 cm) X 45 (114 cm) in.
340 b (154 kg)

3-24

LT15-A SINGLE ASYNCHRONOUS LINE CONTROL
The LT15-A Single Asynchronous Line Control is a device whose sole purpose is to interface one
terminal to the XVM 1/O bus. In standard form, any 20 mA device operating at 110 speeds to 2400
baud can be connected.
The LT15-A is handled in a similar fashion to the console terminal IOT instructions.

IOT Instructions
Mnemonic

Code

TSF1

704001
704002
704004
704101
704102

TCF1

TLS1
KSFI
KRBI

Mechanical
Mounting

Description
Skip on transmit flag
Clear transmit flag
Load transmit buffer
Skip on receiver flag

OR buffer to AC and clear flag

Occupies space in the BA15 logic assembly

API Addresses
Transmit
Receive
Priority

74
75

NOTE
The IOT instructions and API assignments are also

those which are used on the first channel of an LT19D. This means that if both devices are connected to
the system, only one can be used. Either LT15-A or
channel 0 of the first LT19-D must be removed. Fortunately, it is not necessary to add LT19-D channels
in strict numerical order. Therefore, a system could
have both devices installed and used as shown below:
LT15-A
LT19-E(1)
LT19-E(2)

As channel 0
As channel 1
As channel 2

etc., up to LT19-E(4).

LT19-D MULTI-TERMINAL ASYNCHRONOUS LINE CONTROL

The LT 19 Multi-Terminal Asynchronous Line Control increases the basic terminal facili.ty by permitting data transfers between the XVM Processor and any combination of up to five terminals or leveloperated data terminal devices that are EIA-compatible* (Figure 3-9).

3-25

XVM

108US_

SYSTEM <:>
CPU

pwisa

<: CONTROL SIGNALS

] >

| . PARALLEL

BUS <

DATA

CONV.

! > LT19D
|

DEVICE SELECT SIGNALS,CONTROL SIGNALS, PARALLEL DATA

LT19€ |

|LT19E|

[LT19E |

DATA

|LT19€E |

[LT1oF] [LT19F] |

cERIAL | SERIAL

DEVICE SELECT SIGNALS)1 >

|LT19E)

DATA

SERIAL
DATA

EIA

| SERIAL

o _oaa
.

]

[Lrise
15-0845

Figure 3-9

Typical LT19 System Configuration

The LT19 system performs two types of programmed-controlled operations during which data is
transferred between a processor and a terminal or EIA device (for example, Dataphone® interface). A
transmit operation is performed to transfer data from the XVM Processor to a terminal (or EIA
device) and a receive operation is performed to transfer data from a terminal keyboard (or EIA device)
to a processor.

Each LT19-E can support one LT19-F. The LT19-F supplies EIA logic levels which are compatible
with certain types of Dataphones, such as the Bell 103A. Although the LT19-E,F combination supplies
the necessary data signals to the Dataphone, it does not supply control signals.
NOTE 1

The overall speed for all LT19-E channels is limited
to 30,000 baud, for all N channels combined, where
N=1 to 16,,. This limitation is imposed so that the
normal processor service routines may handle all N
channels concurrently.
NOTE 2

Assign the highest speed channels to the first channels in the system to keep the skip chain short. In a
multiple LT19-D system, all high-speed channels
must be first to prevent a low-speed channel from
locking out a high-speed unit.

®Dataphone is a registered trademark of Bell Systems.

*Logic levels specified in Electronic Industries Association (EIA) Standard RS-232C, “Interconnection of Data Terminal
Equipment with a Communication Channel.”

3-26

LT19-H DATA COMMUNICATIONS CABLE OPTION

The LT19-H is a data communications cable option used for interprocessor buffer applications. It is
used between an LT19 and PTO08, between two LT19s, or between the LT19 and other devices with
equivalent interface and timing characteristics. The cable is available in five lengths:
Option
LT19-HA
LT19-HB
LT19-HC
LT19-HD
LT19-HE
IOT Instructions
Terminal Instructions

Length (ft)
50
100
150
200
250

Code
704001
704002
704004

.
- Description
set.
Skip if transmitter flag is
Clears transmitter flag.
Loads transmitter module and sends

704101
704102

Skip if receiver flag is set.
ORs contents of receiver module

character to terminal.

and clears receiver flag.

Specifications

5- or 8-bit* character code
One unit start code

Character Code
Start Code
Stop Codes
Operation
Service
Speed, LT19-E
Transmission distance

- 1-, 1.5-, or 2-units* stop code
Full duplex

1500 ft, maximum; 20 mA current Loop only; 110 baud. Max-

imum length of LT19-H is 250 feet.
55°-122° F (15°-50° C)

Temperature Range
Humidity Range

10-95%

Primary Power Requirements

API Addresses’
Transmit
Receive
Priority

Mechanical
Mounting

Up to five units per LT19-D
Variable to 30,000 baud. See Note in text.

’

115V, 60 Hz, 250 W (approximately)

LT19D 10.5 in. logic mounts in a negative bus H950 cabinet

3-27

PC15 HIGH-SPEED PAPER-TAPE READER PUNCH CONTROLLER
The PC15 High-Speed Paper-Tape Reader/Punch is used to input perforated paper-tape programs
into core memory, or to punch core memory programs or data on paper tape. Information is punched
on eight-channel fanfolded paper tape in the form of six- or eight-bit characters at a maximum rate of
50 characters/second. Information is read at a maximum rate of 300 characters/second. The PC15
consists of a PCO5 Paper-Tape Reader/Punch with interface and control logic for using the reader/punch with an XVM System. Two modes of operation are possible: alphanumeric and read-in.

Alphanumeric Mode - The reading of data in this mode is accomplished by the reader
sending one eight-bit character to the AC on receipt of the requisite 301.

UNUSED

6
—t—

4
-

2
i

CHANNEL

TAPE CHANNEL
87654

321
* «¢——t—— FEED HOLE

LLEADER

(FEED HOLE ONLY)
¢ecesceee |-~

3375

w—

$o0esss000 | — 2778

DIRECTION
OF TAPE

MOVEMENT

&0 00ss

OO @

- 3038

READ

ONE

IOT

INSTRUCTION

TRAILER

.
.

( FEED HOLE ONLY)
o=HOLE POSITION
o=HOLE PUNCHED
15-0232

Binary In Mode - In this mode, the reader assembles three six-bit characters into an 18-bit
word, and then they are transferred directly to memory. Only characters that have hole 8
punched are read.
Hole 7 is used in Hardware Read-In (a form of binary) and will cause the system to execute
the last instruction that was read from the tape.

3-28

FIRST CHAR READ

SECOND CHAR READ

CHANNEL ‘6

‘e

THIRD CHAR READ

‘e

—

LOI1|2IS|4I5|6|7l8|9||O|11|12II3II4‘I5|16117] ACCUMULATOR
CHANNEL

{

TAPE CHANNEL

321

87654

oa——1—
FEED HOLE

LEADER

(FEED HOLE ONLY)

L)
L]

8 CHANNEL PUNCH4 »®

ED FOR EACH CHA-

0000000

RACTER

000008000
e

O0Oe0O0O

0000e

00O

O
000000

DIRECTION
OF TAPE
MOVEMENT

} NEXT INSTRUCTION

FIRST INSTRUCTION
READ BY ONE IOT OR
INITIATED BY READIN

0000000

0000600
O
©

0000000

00009000

CHANNEL 7 PUNCH‘/a
ED CAUSES LAST

—FIRST CHARACTER READ
-— SECOND CHARACTER READ
— THIRD CHARACTER READ

b'o 000600 O

LAST THREE FRAMES MUST BE
PUNCHED USING ALPHANUMERIC
CODE TO EFFECT THE CHANNEL
7 PUNCH,

INSTRUCTION TO
BE EXECUTED
TRAILER

(FEED HOLE ONLY)

o= HOLE POSITION
-e= HOLE PUNCHED
15-0233

Reader IOT Instructions

Mnemonic

Code

RSF
RCF

700101
700102

Description

Skip next instruction if reader flag is a 1.

Clear reader flag. Read reader buffer, inclusively
OR contents of reader buffer with AC, and deposit
result in AC.

Read reader buffer and clear reader flag. Clear AC

RRB

700112

RSA

700104

and transfer contents of reader buffer to AC. Select alphanumeric mode. RSB 700144 Select

Code

Description

PSF
PCF
PSA

700201
700202
700204

PSB

700244

Skip next instruction if punch flag is a 1.
Clear punch flag and punch buffer.
Select alphanumeric mode and punch one character. Set punch flag when punch is complete.
Select binary mode and punch one six-bit character. Set punch flag when punch is complete.

Punch 10T Instructions
Mnemonic

binary mode.

3-29

Programming Considerations
To use the reader at the transfer rate of 300 cps, a select IOT (RSA or RSB) must be issued within 1.67
ms after each flag. This action is required because a 40 ms reader stop delay is present. When this delay
is activated, it overrides the select IOT input and subsequently stops the tape. Thus, if a new select IOT
is not received within 1.67 ms of the setting of the flag, the reader operates start-stop and reads
characters at a maximum of25 cps rate. No data is lost.
The RSA (700104) and RCF (700102) can be microprogrammed to form a 700106 instruction. This
instruction reads the character, transfers the character to the accumulator, and advances the tape in
one operation. An RSF (700101) and RRB (700112) cannot be microprogrammed.

Channel 7 can be punched using only the Alphanumeric mode. Therefore, when punching the last
character of a tape for hardware read-in operation, the last character must be punched in the alphanumeric mode.
The PCF instruction can be microprogrammed with a PSA or PSB instruction for form 700206 or
700246. This instruction clears the punch flag and buffer, selects the applicable mode, loads the punch
buffer, advances the tape, and perforates the character on tape. After completing the punching, the
punch flag is set to denote that the punch can accept another character. Microprogramming the PCF
and PSF instructions is not allowed.
API Address
API Priority

50
2

NOTES
Fanfold paper tape is DEC Part No. 36-0536301

2. Ali PCO0S5 units are 115 Vac.

This device is cabinet-mounted, thus it cannot be
operated remotely.

Environmental
Temperature Range
Humidity Range

55°-110° F (13° -43°C)
20-95% without condensation

Electrical

Input Voltage

115 Vac + 10%

Input Frequency

50/66 Hz, single phase

Mechanical
Mounting

Occupies 10.5 in. cabinet space in the XV100 cabinet

3-30

RF15 DECdisk CONTROLLER

The XVM DECdisk system (Figure 3-10) consists of two elements: an RF15 Control Unit and up to
eight RS09 Disk Units. The control unit and up to two disks may be mounted in one cabinet. Up to
three disk units may be housed in each additional cabinet.

The control communicates directly with the XVM 1/0 processor. All transfers — data, address, and
control - take place through the I/O bus. Data and address transfers use the multi-cycle block transfer
facility. Control transfers use the programmed IOT (Input Output Transfer) mode.

The fixed head assemblies eliminate head positioning mechanics and stringent vibration limitations.

XVM

I/0 BUS

RF15

CONTROLLER

DISK BUS

[RSOS |

10T
|

[ RSO9 ]—--I RSOSJ
7

)

DISK DRIVES
15-0234

Figure 3-10

XVM DECdisk System

Data are recorded serially on each track in 24-bit words; 18 data bits, one parity bit, four guard bits,
and one data control bit. Each 24-bit word unit is identified by an address that is prerecorded serially
exactly one word before the word with which it is associated. The controller can then assemble and
identify the address before the heads reach the word itself. Each address is 13 bits long; 11 bits supply
addressing data, one bit is a control bit, and one bit is a parity bit.
IOT Instructions

Mnemonic

Code

Description

DSSF

707001

Skip on disk flag.

Clear the disk control and disable the “freeze’ stat-

707021

DSCC

us. A “freeze” is caused either by a timing or data
track hardware error or an address parity error.

OR the contents of Address Pointer 0 (APO) into

707022

DRAL

the AC.

APO
WAN

TRACK ADDRESS

WORD ADDRESS
15-0841

3-31

DRAH

707062

OR the contents of Address Pointer 1 (AP1) into
the AC. Bit 14 signifies a non-existent disk error.

AP1

DISK NUMBER

DLAL

707024

DLAH

707064

DSCF
DSFX

707041
707042

DSCN

707044

Load the contents of the AC into APO.
Load the contents of the AC into API.
Clear the function register and the interrupt mode.
XOR thg contents of AC15, 16, 17 into the function register.
Execute the condition held in the function register.

Function Register

DLOK

INT

READ

WRITE

WRITE CHECK

707202

NO EFFECT

OR the disk segment address (ADS) register into
the AC.

ADS

)

RESGTQ;ES

ERR | HOW | APE | MXF | WCE | DPE

LOCATION

o:}

’

|WLO | NED | DCH | PGE | XFC

= FUNCTION
REGISTER

DSCD
DSRS

707242
707262

Clear the Status Register and Disk Flag.
OR the Status Register with the AC.

3-32

’

Specifications
Storage Capacity
Addressing Means
API Address
API Priority
Transfer Means

Average Access Time
Minimum Access Time
Worst-Case Access Time
Word Transfer Rate

262,144

18-bit words expandable to

Disk unit, track, and word. Single word addressability is provided.
1

XVM multi-cycle block transfer facility
60 Hz Power
- 50 Hz Power
16.7 ms
20.0 ms
250 us
250 us
33.3 ms
40.0 ms
@ 16 us/word
@ 32 us/word
@ 64 us/word

61.8 kc 50 ke
31.2 ke 25 ke
15.6 kc 12.5 kc

Power Requirements

Input Frequency
Power Dissipation

50 Hz/60 Hz + 3 Hz
1.2 kW

Input Voltage
Environmental

Temperature Range
Humidity Range

Mechanical
Mounting

2,097,152

words

18°-35° C (65°-90° F)

10-55% without condensation

Controller and first two
disks mount in H950
cabinet

3-33

RP15 DISK PACK CONTROLLER
.
The RP15 interfaces bulk storage disks to the XVM System. Currently there are two versions of disk
drive; RPRO2 and the RP03. The former, when fitted with an RPO2P removable disk pack, will provide
the XVM System with 10.24M 18-bit words of storage. The RP03 is a double-density version of the
RPRO2 and can, therefore, store 20.48M 18-bit words on one disk pack. The total system capacity,
with eight RPR0O2s would be 81.92M words, and with eight RP03s, 163.84M words (that is, 163.84
million words).
'
'

The total capacity of the RPR02 Disk Pack is 232,000,000 bits, which is equivalent to 12,900,000 18-bit
words. In actual practice, the two outside surfaces are not used; on all surfaces, tracks 200, 201, and
202 are reserved for maintenance. When these conditions are recognized, along with the data required
for two synchronization areas, word and longitudinal parity, and a header word for each sector, the
relative characteristics yield a total data word capacity of 10,240,000 18-bit words.
In the RPRO2, each disk contains 203 cylinders (406 in the RP03). Movable heads, connected to a
common positioning actuator, access one cylinder at a time. Track-to-track, average, and maximum
positioning times are 20, 50, and 80 ms, respectively. Rotation speed is 2400 rpm (or a rotational time
of 25 ms), providing average and maximum latency times of 12.5 and 25 ms, respectively. Data are
recorded by a double frequency, non-return-to-zero technique. Data are formatted into 128 36-bit
word sectors that are individually addressable; each word provides storage space for two 18-bit words.
The drive has 20 read/write heads that record data at 2.5M bps. Each track contains 10 sectors. Word
transfer rate is 14.8 us for each 36-bit word or 7.4 us for each 18-bit XVM Processor word.

IOT Instructions
Mnemonic

Code

Description

DPSN

706421

Skip

706422

OR the Cylinder, Head, and Sector Address registers into the AC.

DPRA

706432

Read the Cylinder, Head, and Sector Address registers into the AC.

DPLZ

706424

Load the Accumulator zeros into Status register A
and execute bits 0-8 if GO bit is set.

DPOC

706442

OR the Current Address register into the AC.

DPRC

706452

Read the Current Address register into the AC.

DPLO

706444

Load the Accumulator 1s into Status register A
and execute bits 0-8 if GO bit is set.

DPCN

706454

Equivalent to a continue command. Clear the AC.
xecute the Function register.E The FR is
unchanged.

DPOW

706462

OR the Word Count register into the AC.

DPOA

the following instruction if FORMAT/NORMAL switch is in NORMAL position.

3-34

DPRW

706472

Read the Word Count register into the AC.

DPLF

706464

Load Status register A from AC 0-8. Execute the
new contents if the GO bit is set.

DPSF

706301

Skip on DISK flag.

DPOSA

706302

OR Status register A into the AC.

DPRSA

706312

Read Status register A into the AC.

DPLA

706304

Load the Address register from AC 00-17.

DPSA

706321

Skip on ATTENTION flag.

DPOSB

706322

OR Status register B into the AC.

DPRSB

706332

Read Status register B into the AC.

DPCS

706324

Clear the Status bits.

DPSJ

706341

Skip the following instruction if the JOB DONE
flag is set.

DPOM

706342

OR the Maintenance register into the AC.

DPRM

706352

Read the Maintenance register into AC 0-5. Clear
AC 6-17.

DPCA

706344

Load the Current Address register from AC 0-17.

DPSE

706361

Skip the following instruction if an error condition
is present.

DPWC

706364

Load the 2’s complement of the word count into
the Word Count register.

DPEM

706401

Execute the maintenance instructions as defined by
AC 9-17.

DPLM

706411

Clear the AC and leave Maintenance mode.

DPOU

706402

OR the Selected Unit Cylinder Address register
into the AC 10-17.

DPRU

706412

Read the Selected Unit Cylinder Address register
into the AC 10-17.

DPCF

706404

Clear the Function register.

3-35

Controller
Electrical
Input Voltage
Input Frequency
Power Dissipation
Environmental

Temperature Range
Humidity Range

Mechanical

Mounting
Weight

Drive (RP02/RP03)
Electrical
Input Voltage
Input Frequency
Power Dissipation

Environmental

Temperature Range
Humidity Range

Mechanical

Dimensions
Weight

115/230 Vac, single phase
47-63 Hz
800 W

55°-100° F (13° - 38°C)
25-95% without condensation

Mounted in H950 cabinet
305 Ib (138 kg)

208/230 Vac + 10% of 3 phases
50/60 Hz + 1%
1250 W

60°-90° F (16° - 3C)
8-80%

24 (61 cm) X 36 (91 cm) X 40 (102 cm) in.

400 1b (181 kg)

3-36

ATTENTION

UNIT

ATTENTION

UNIT

ATTENTION

UNIT

ATTENTION

UNIT

—— ATTENTION

3
UNIT

ATTENTION

UNIT

ATTENTION

UNIT

ATTENTION

y
)

6
UNIT

SELECTED

UNIT

FILE

UNSAFE

PROGRAMMING

ERROR

END OF PACK

TIMING ERROR

FORMAT

ERROR

WRITE CHECK ERROR
WORD PARITY ERROR

LONGITUDINAL PARITY ERROR
SELECTED UNIT SEEK UNDERWAY
SELECTED

UNIT NOT

READY
09-0340

DONE

AND

ERROR

FLAG

INTERRUPT

ENABLE

ATTENTION

FLAG

INTERRUPT

ENABLE

—— GO

WRITE PROTECT ERROR
NON-EXISTENT

CYLINDER ADDRESS

r—— NON-EXISTENT
.

[—

HEAD

ADDRESS

NON-EXISTENT SECTOR ADDRESS
HEADER
UNIT

SELECTED
0=

UNIT
O

FUNCTION

NOT FOUND

SELECTED UNIT WRITE PROTECTED

—

.0
= [DLE

UNIT

READ

UNIT

WRITE

SELECTED

UNIT

RECALIBRATE

UNIT

SEEK

UNIT

READ

UNIT

WRITE ALL

UNIT

WRITE CHECK

SEEK

INCOMPLETE

JOB

ALL

UNIT

DONE

FLAG

——

ERROR

FLAG

09-0341

3-37

TC15 DECtape CONTROLLER

The DECtape system is a computer peripheral device that stores digital data on 0.75 in. magnetic tape
in a three-track parallel/serial format. The tape, called DECtape, is wound on 3-1/2 in. pocket-size
reels, which are easy to carry and load. Each reel has a capacity of 3 million bits for 260 ft of tape.
TRANSPORT SELECT,
MOTION SELECT

;:>

DATA, TIMING AND
MARK TRACKS

TUS6

—

TUS6

DATA

XVMm

ADDRESS

COMPUTER | DEVICE,

]

(DCH)

SUBDEVICE

SELECT

TC15

DECTAPE

CONTROLLER

COMMANDS 8 STATUS
L

TUS6
—

L—p
JN_/J

TUS6

15-0640

The DECtape device is a fast, convenient, reliable, low-cost input/output data storage facility and
updating device. Each DECtape system consists of a controller and from one to four TU56 Dual
DECtape Transports. The controller is connected to the computer 1/O bus and communicates with the
processor for control and status information and with memory through the 1/O processor for data
information. Each drive is connected to the controller through a parallel bus; both control and data
information pass through this bus.

Data Storage Format

The DECtape system stores data in a parallel format; each 18-bit data word is divided into six three-bit
bytes which are stored in parallel across three data tracks. The system stores the complete 18-bit word
serially along the tape in six three-bit bytes.

3-38

DECtape stores data in blocks (or groups), using prerecorded,
fixed-position addressing that allows
selective updating of tape information; this feature is also used
in magnetic disk or drum storage
devices. Each data block has its own address and is numbered to
provide random accessing. Another
DECtape feature is bidirectional operation; i.e., each block can
be identified by the computer regardless of the direction in which the tape is moving. Consequently, the
tape can be read from or written on
in either direction. This feature provides the programmer with a relativel
y fast search time, because the
tape does not have to be rewound before a block can be found,
and thus the programmer can begin to
write at either end of the block as soon as the correct block number
is found. It is important that the
programmer read and write data in the same direction, however,

computer.

or be prepared to unscramble it in the

The number of words in each block (block length) is predetermined when
the tape is formatted. A
standard block consists of 256 18-bit words. Tape formatting involves the
writing of a timing track
(which furnishes timing pulses to the controller) and the writing of a mark track
(which contains codes
to inform the controller where the tape is within a given block). Special timing
and mark tracks are
contained on the tape for this purpose. Formatting also involves numbering
the data blocks and also
specifying the length of the data blocks. When the block lengths are establishe
d by the programmer,
they cannot be changed without destroying the data on the tape.
IOT Instructions

Mnemonic

Code

Description

DTCA

707541

Clear Status register A.

DTRA

707552

Read Status register A.

DTXA

707544

XOR Status register A.

DTLA

707545

Load Status register A.

DTEF

707561

Skip on Error flag.

DTRB

707572

DTDF

707601

Read Status B.
Skip on DECtape flag.

Data Channel Address

Word Count
Current Address
API Address
API Priority

30
31
44

Electrical
Input Voltage
Input Frequency
Power Dissipation

115/230 Vac, single phase
50/60 + 2 Hz
1600 W

Environmental
Temperature Range
Humidity Range

65°-90° F (18° - 32°C)
10-55% without condensation

Mechanical

Mounting
Weight

Controller and first three TU56 Drives are mounted in an H950

cabinet

300 Ib (136 kg)

3-39

TC59-D MAGNETIC-TAPE CONTROLLER

the direction of the XVM, controls the operation
The TC59 consists of tape control logic, which, underTC59
operates under program control to transfer
of up to eight magnetic tape transport units. The
transfer data to or from core memory,
data between core memory and the selected tape transport.theTodata
channel WC (word count) register
or,
the TC59 uses the data channel facility of the process
specifies the record length (number of words), and the CA (current address) register specifies the
starting core memory address of the data transfer.

CONTROL

SIGNALS

MAGNETIC

TAPE

DW15

1/0

CONTROLLER

1/0 BUS

PROC.

CONTROLLER

TU10
DRIVE

DATA

TuiO
DRIVE

TU10
DRIVE

2127000

SIGNAL

15-0840

or 800 bpi
The TC59 functions in either 7-track operation or 800 bpi 9-track operation; either 200, 556,
Parity mode.
density modes are selectable in 7-track operation. It can operate in either Binary or BCD
buffer in the
data
For writing on tape, the 18-bit data words are transferred from core memory to the
as three
logic
write
tape control logic. The data buffer logic supplies the character to the tape transport
for a 9s
character
9-bit
7-bit (6-bit character plus parity bit) characters for 7-track operation or two
s and
character
as
tape
from
track operation. For reading, the sequence is reversed, information is read
dataa
buffer,
data
the
in
d
sent to the data buffer. When a complete (18-bit) word has been assemble
channel break (word transfer) is initiated to transfer the data buffer word into core memory.
The TC59 controls the operation of a maximum of eight magnetic tape transports and uses the proc-

essor data channel facility to transfer data between system core memory and magnetic tape. The data
transfers are controlled by the memory-resident word counter (WC) and current address (CA) registers
for WC
associated with the assigned data channel. The TC59 is assigned memory location 32g and 335contents
initial
the
therefore,
transfer;
data
each
before
ted
incremen
is
CA
and CA, respectively. The

each transfer
should be set to the desired initial address minus one. The WC is also incremented before
this way, the word
and must be set to the 2’s complement of the desired number of data transfers. In

transfer that causes the word count overflow (WC = 0) is the last transfer to take place.

10T Ihstructions
Mnemonic

Code

Description

MTSF

707341

Skip on error flag or magnetic tape flag.

MTCR

707321

Skip on tape control ready (TCR).

MTTR

707301

Skip on tape transport ready (TUR).

MTAF

707322

Clear the Status and Command registers, and the
EF and MTF, if Ready. If Busy, clear MTF and
EF flags only.

3-40

MTCM

707324

Inclusively OR the contents of the AC bits 0
through 5, 9 through 11 into the Command regis-

ter; JAM transfer bits 6, 7, 8.

MTLC

Load the contents of AC bits 0 through 11 into the

707326

Command register.
-

707342

OR the Status register into AC 00-11.

MTRS

707352

Read the Status register into AC 00-16.

707302

OR the Command register AC 0-11.

MTRC

707312

Read the Command register to AC 00-11.

MTGO

707304

Set “go” bit to execute, if legal.

Specifications
Recording Mode

NRZ1, industry compatible

Magnetic Head

Dual gap, read after write

Data Transfer Method

Multi-cycle data channel facility

Tape Handling Method

Direct-drive reel motors, servo-controlled single capstan, vacuum tape buffer chambers with constant tape winding tension.

There are no dancer arms to cause non-uniform tape tension
and stretching
BOT, EOT Detection

Photoelectric sensing of reflective strip, industry compatible

Skew Control

Deskewing electronics included in TU10 Transport to eliminate
static skew

Write Protection

Write protect ring sensing on TU10 Transport

Data Checking Features

Read-after-write parity checking of characters; Longitudinal
Redundancy Check (7- and 9-channel); Cyclic Redundancy
Check (9-channel)

Packing Density

7-channel: 800, 556, and 200 bpi; selectable under program
control,
9-channel: 800 bpi

Maximum Transfer Rate

36,000 characters per second

Rewind Speed

150 ips

Interrecord Gap

Will read tape with gap of 0.48 in. or more; will write tape with
gap of 0.52 in. or more (compatible with industry standard)

3-41

Tape

0.5 in. wide, industry standard

Tape Speed

45 ips, reading and writing

Word Count

Data Channel Addresses
32

Current Address

API Address

API Priority

Controller
Electrical
Input Voltage
Input Frequency
Power Dissipation

115/230 Vac £+ 10%

50/60 £ 2 Hz Single phase

500 W

Environmental
Temperature Range
Humidity Range

Mechanical
Mounting

TU10

1000 W

7°-35° C (45°-95° F)
without
20-75%
condensation

Drive and Controller normally mount in separate
H950 cabinets but may be combined in the same
cabinet.

Weight

300 1b (136 kg)

3-42

250 1b (113 kg)

VP15 POINT-PLOT DISPLAY CONTROLLER
The VP15 Controller is the foundation of the point plotting family.It serves as an interface between the
XVM and the display device. The VP15 converts program-generated digital commands (IOT instructions) to analog voltages applicable to the display device. However, because the instructions for all
displays are not exclusive, only one model, VP15, is permitted.

At present, four VP15 models are available:
1.

VPI15-A - Controller plus VTO01-A storage tube

VPI15-B - Controller plus VRO1-A refresh tube

VPI15-C - Controller plus VR 14 refresh scope

VP15-D - Controller plus VR20, two-color refresh tube

VP15-A
The VP15-A is designed to meet the needs of those with a very large data base to be displayed - textual

data or static pictures. It is ideal for use when one cannot afford the central processor time required for
picture refreshing. There are two program-selectable modes of operation - Store and Non-store mode.
Points are drawn on a 1024 X 1024 raster matrix. Those plotted in Non-store mode must be refreshed
30 times/second; points plotted in Store mode remain visible for 15 minutes (although hardware considerations require pressing the VIEW button every 90 seconds). Modes may be intermixed.
Erasing may be done either under program control or by pressing the ERASE button on the display.
Immediate point deletion is only possible in Refresh mode. In Store mode, the entire picture must be
erased and redrawn.
The VPI15-A is a table-top mounted device which can be remoted up to 15 feet from the computer.
VP15-A 10T Instructions

Mnemonic

Code

Description

CXB

700502 .

Clear x-coordinate buffer

CYB

700602

Clear y-coordinate buffer

LXB

700504

Load x-coordinate buffer from AC8-17

LYB

700604

Load y-coordinate buffer from AC8-17

- EST

700724

Erase storage tube

SDDF

700521

Skip on display Done flag

CDDF

700722

Clear display Done flag

LXBD

700564

Load x-coordinate buffer and display the point
specified by XB and YB (Store mode)

LYBD

700664

Load the y-coordinate buffer and display the point
specified by XB and YB (Non-store mode)

LXDNS

700544

Load the x-coordinate buffer and display the point
specified by XB and YB (Non-store mode)

3-43

LYDNS

700644

VP15-A Specifications
Point Plotting Rate

Display Area
Resolution (raster units)
Refresh Rate
Phosphor Type
Mounting
Width
Height
Depth

Weight

Temperature Range

Humidity Range
Power Requirements
Power Dissipation

Load the y-coordinate buffer and display the point
specified by XB and YB (Non-store mode)

100 us/point in Store mode
82 us/point in Refresh mode
8-1/4 in. X 6-3/8 in. (21 cm X 16.3 cm)
1024 X 1024
30 Hz
Similar to Pl
Table-top
11-5/8 in. (29.5 cm)
11-7/8 in. (30.1 cm)
22-3/8 in. (56.8 cm)
51 Ib (23.1 kg)
+65° F to +80° F
+18°C to +27.5° C
40% to 55% without condensation
120/240 Vac 60 Hz
210/230 Vac 50 Hz
250 W

Controller

Mounting

Mounted in BA15 logic assembly

VP15-B, VP15-BL

In environments and applications where low cost is the most important criterion, the VP15-B X-Y
Display System can be used to full advantage.
The system uses a rack-mounted Tektronix Type RMS503 X-Y Oscilloscope. Points are plotted on a
1024 X 1024 raster matrix on the 8 cm X 10 cm display area and should be refreshed 30 times/second.
Operator controls on the RM 503 front panel provide simple user manipulation of the display presentation — expansion, compression, centering, shifting - without changing program parameters.

Four levels of intensity are provided, and the light pen can be optionally specified, forming the VP15BL X-Y Oscilloscope display. Both displays are rack-mounted.
VP15-B, VP15-BL 10T Instructions

Mnemonic

Code

Description

DXL

700504

Load the x-coordinate buffer from ACS8-17.

DXS

700544

Load the x-coordinate buffer and display the point
specified by XB and YB.

DYL

700604

Load the y-coordinate buffer from ACS8-17.

DYS

700644

Load the y-coordinate buffer and display the point
specified by XB and YB.

DXC

700502

Clear the x-coordinate buffer.

3-44

DYC

700602

DLB

700704

Clear the y-coordinate buffer.
Load the Brightness register from bits 16-17 of the

AC.

NOTE
This instruction clears the Display flag associated
with the light pen.
DSF

700501

Skip if Display (light pen) flag is a 1.

DCF

700702

Clear Display (light pen) flag.

VP15-B, VP15-BL Specifications
Point Plotting Rate
Display Area
Resolution (raster units)
Refresh Rate
Terminal Specifications
Phosphor Type

12 us/point
3.1in. X 3.9 in. (8 cm X 10 cm)
1024 X 1024
30 Hz

Mounting

Option cabinet not supplied

Physical
Width
Height
Depth
Weight

7 in. (17.8 cm)
17 in. (43.2 cm)
28 1b (12.7 kg)

Power Requirements
Power Dissipation

19 in. (48.3 cm)

120/240 Vac 60 Hz
210/230 Vac 50 Hz
120 W

VP15-C, VP15-CL
This system uses a DEC Type VR14 X-Y Display. Points are plotted on a 1024 X 1024 raster matrix
and can be refreshed 30 or 60 times/second. Useful screen dimensions of 6-3/4 X 9 in. and an impressive physical appearance make the VP15-C an attractive and useful terminal. The display is available in
rack-mounted and table-top configurations. Various optical filters can be specified to suit particular
applications. Modular construction provides maximum flexibility and increased maintainability. The
VPI15-C is an ideal display terminal for environments where security is of a paramount importance.
The only front panel control that is readily accessible is the ON/OFF/BRIGHTNESS control - the
others are screwdriver adjustments. The light pen can be optionally specified, forming the VP15-CL XY Display System.

VP15-C, VP15-CL IOT Instructions
The IOT instructions for the VP15-C are identical to those for the VP15-B.
VP15-C, VP15-CL Specifications
Point Plotting Rate

20-25 us/point

Display Area

6-3/4 X 91in. (17.1 cm X 22.8 cm)

Resolution (raster units)
Refresh Rate

1024 X 1024
30 or 60 Hz
3-45

Terminal Specifications
Phosphor Type

Mounting

P31 or P7

Option cabinet not supplied

Physical

Width
Height
Depth
Weight
Power Requirements
Power Dissipation

19 in. (48.3 cm)
10-1/2 in. (26.7 cm)
17 in. (43.2 cm)
53 1b (24 kg)
110/240 Vac 60 Hz
210/230 Vac 50 Hz
150 W

VP15-D

:
The VP15-D is a completely self-contained two-color CRT display that provides a 6-3/4 X 9 in.
viewing area in a compact 19 in. package. The dual-energy phosphor screen presents information as
either a red or green trace. The VP15-D requires only analog X- and Y-position information and an
intensity pulse to generate sharp, bright point-plot displays. Except for the high-voltage power supply
and the CRT, the unit is composed of solid-state circuits and utilizes high-speed magnetic deflection to
enhance brightness and resolution. The inputs for the X-and Y-deflection may be balanced or singleended, bipolar or offset, and positive- or negative-going without any modification to the VP15-D. The
intensity pulse may be time-multiplexed or gated by a separate input to allow the screen to be timeshared between two inputs; TTL-compatible signals are required. The VP15-D is available in a standard 19-inch rack-mounted unit or in a table-top version.

VP15-D 1IOT Instructions
The instructions for the VP15-D are identical to those of the VP15-C, except when the DLB instruction
is being used, bit 15 denotes color. If bit 15 is a 0, the color is red; if bit 15 is a 1, the color is green.
VP15-D Specifications

Color Registration

< 25 mils within a central 4 in. diameter circle; < 60 mils elsewhere on the screen (distance between like-addressed points in
red and green)

Spot Size

20 mils inside the usable screen area at a brightness of 30 fl
(green); 30 mils at 10 fl (red)

Color Mode Maximum
Setup Time

Deflection

1600 us for green mode; 300 us for red mode

Full screen deflection and settling time to within £ 1 spot diameter, <20 us for green and <16 us for red

Power Requirements
Voltage
Frequency

Power

115V £ 10%; 230 V + 10%
50-60 Hz

500 W

API Address

API Priority

3-46

High Voltage

Overload Protection

High-voltage switches between approximately 6 kV and 10 kV
for red and green modes, respectively.

Unit is protected against fan failure or air blockage by thermal

cutouts. Power supply and amplifiers are current limited. Phos-

phor protection is provided against fault conditions.
Temperature Range

0°C to 45°C (operating) (32° - 113°F)

Input Specifications

* Inputs are differential
* Differential input impedance, 5K minimum
* Input sensitivity, 500 mV/in. maximum (changeable with
resistors to 200 mV/in.)
* Maximum operating input, 26V (maximum operating input is
the sum of the Common mode and the differential input)
* Input offset not to exceed +1/2 peak-to-peak input signal
¢ 7Z Input, TTL compatible, +2.4 V to 0 transition will cause
CRT to unblank for 1 us in green mode, 5 us in red
® 7 Direct, AC coupled, 45 V; 10 us pulse will unblank CRT

Color Bit

Single bit selects green (high) or red (low)

Dimensions

10-1/2 in.H X 19 in.W X 17 in.D (26.7 cm X 48.3 cm X 43.2
cm)

Weight

80 Ib (36.2 kg)

Repeatability

< %1 spot diameter (repeatability is the deviation from the
nominal location of any given spot)

3-47

VT50 DECSCOPE VIDEO TERMINAL

The VT50 DECscope is an on-line graphics terminal, and gives fast interaction at a price comparable
with that of 10 cps teletypewriters. It has a range of operating modes and transmission speeds that may
be selected by switches, and it is compatible with any device or system that uses asynchronous transmission of ASCII codes.

Two control dials let the programmer select transmission rates from 75 to 9600 baud (75, 110, 150, 300,
50 transmits data at one
600, 1200, 2400, 4800, and 9600 baud). These control dials can be set so the VT
speed and receives data at another speed.

Up to 12 lines of information can be displayed at one time. When the bottom line on the screen is
displayed, and the cursor is directed to move to the next line, the top line automatically “scrolls” off
the screen to allow space for the new line. When receiving data at high baud rates, scrolling can occur
so rapidly that a visual inspection of screen information is impossible. For example, at 9600 baud, the
VTS50 can receive 960 characters per second - enough to fill the whole screen. A simple command
directs the VT50 to give the operator or host computer control over scrolling so the display can be
updated on a line-by-line or screen-by-screen basis.

Movable Cursor

I
I

|
|
|
|
|
|
|
|
|

1
|

The cursor can be moved from the keyboard or, under program control, to the home position (top left
corner of the screen), right one position, left one position, up one line, and down one line.

SCREEN |#— MEMORY |= RECEIVER ——r— m_:,—l_;—g——l °
l

COPY

I _\_—'
o

KEYBOARD

TRANSMITTER

COMPUTER

WITH LOCAL

LINE

FROM
HOST

T0
HOST

COMPUTER

OFF

—_
15-0825

The VTS50 has tabs that are fixed at every eight spaces, as well as the ability to erase characters from the
cursor to the end of a line and from the cursor to the end of the screen.
Extended Functions

Programmer-assigned functions can be written into system software and accessed by using the VT50’s
ESC key. (Commands created in this way are called Escape Sequences.) The host computer can be
programmed so that the receipt of ESC 1 implements one routine, ESC 2 another, and so on.

A means of identifying unique Escape Sequence functions is incorporated into the VT 50’s architecture.
Labels above the top ten keys direct the operator to the proper key for each sequence. Labels can be
easily changed to accommodate new functions and applications.

A special self-test feature is built into the VT 50 - it permits you to check the circuitry prior to any
network installation. No special interfacing is necessary. The VTS50 can be wired directly to a computer
or to other terminals via its standard 20 mA current loop interface. It can be installed as an active
device, a passive device, or active during transmission and passive upon reception. EIA or other interfacing for use with modems, data phones, or acoustic couplers is optional.
3-48

Minimal Maintenance
Few mechanical parts (the keyboard and audio/tactile response mechanism) give the VT 50 built-in
reliability, lowering the cost of ownership. Extensive keyboard testing - for over 100,000,000 failurefree keystrokes — proves switch reliability.

Specifications
Dimensions

Weight

Height: 360 mm (14.1 in.)
Width: 530 mm (20.9 in.)
Depth: 690 mm (27.2 in.)
19.4 kg (43 1b)

Environmental
Temperature Range

Humidity Range

10° C to 40° C (50° F to 104° F)
10% to 90% with maximum wet bulb 28° C (82° F) and minimum dew point 2° C (36° F)

Electrical

Input Voltage
Power Consumption

230 V: 210-250 V@ 5 O Hz +1 Hz
115 V: 100-126 V @ 6 OHz £1 Hz
110 W

Display
Format

12 lines X 80 characters

Character Matrix
Character Size
Screen Size
Transmission Rates

5X7

Keyboard

Terminal Modes

Page Overflow
Parity
Cursor

2.7 mm X 5.0 mm (0.11 in. X 0.20 in.)
220 mm X 110 mm (8.7 in. X 4.3 in.)
Switch-selectable
Full Duplex: 75, 110, 150, 300, 600, 1200, 2400, 4800, and 9600
baud
Full Duplex with Local Copy: 110, 600, 1200, 2400, 4800, and
9600 baud
e Character set: 64 ASCII upper case, alpha, numeric, and
punctuation characters
e Typewriter format keyboard
* Audio/tactile response mechanism for fast operator feedback
e Three-key rollover feature to minimize typing errors
e BREAK key included for half duplex software
Off-line mode
On-line mode: Full duplex or full duplex with local copy
Upward scroll
Even or mark (no parity) selectable
Control: Up or down one line, right or left one position, home,
erase from cursor to end of line, erase from cursor to end of
screen

Type: non-destructive, underscore

Communications
Transmission Code
Operator Controls

20 mA current loop standard; EIA interface optional
USASCII extended through Escape Sequences
Power on/off, intensity control, baud rate switches, full duplex
or full duplex with local copy switch

3-49

VW01-B WRITING TABLET

The writing tablet option is an acoustical X-Y digitizer connected directly to the controller. Its horizontal surface provides free arm movement.

The VWOI operates in one of two modes: Single Point or Data Input. In the Single Point mode, a
single spark is generated each time the pen is pressed against the writing surface. This operation is used
when the operator desires to plot specific points in the X- or Y- axis.

In the Data Input mode, the spark pen produces a continuous series of sparks at a constant rate
(normally 200 Hz). This mode allows the user to draw continuous lines, circles, curves, etc. The dual
mode capability of the VWO01 enables the user to perform a myriad of graphic analytical tasks quickly
and accurately.

Both right- and left-handed users are catered to by this device by physically rotating the table 90°. A
switch rotates the signals electrically by 90°,

10T Instructions
Mnemonic

Code

Description

WTSC
WTRX
WTRY
WTRS
WTCD
WTCP
WTSK
WTSE
CAF
IORS

703224
703222
703242
703262
703241
703221
703261
703264
703302
700314

Set Tablet Controls
Read X
Read Y
Read Status
Clear DATA READY flag
Clear PEN DATA flag
Writing Table Skip
Select Tablet
Clear All Flags
Input/Output Read Status

Maintenance 10T*
WTMN

703244

Clear Set XY

X VM
CPU

1/0
ko,

»|

vwo1i

CONTROL
LOGIC

COMPONENT
BOX

-——-—-l
o)

WRITING
TABLET

PEN

CP-0I17

*The IORS 10T instruction will display the VW01 Writing Tablet interrupt status in accumulator bit 05.

3-50

Specifications
Digital Resolution
Graphic Resolution
Reproducibility
Drift
Constant Temperature
4.4° to 32° C

10-bit resolution in both X- and Y-axes.
1000 X 1000 line pairs; 90 lines per in.
One (least significant) bit in 1000, in both X- and Y-axes.

With the spark pen stationary, the X- and Y-registers will not

vary more than £ 1 bit of 1024.

With the spark pen stationary, the X- and Y-registers will vary
vy ¢ group undefined or illegalvy ¢ group undefined or illegal vy
¢ group undefined or illegal6é 2 bits per thousand per degree
change centigrade.
+40° to 90° F

With the spark pen stationary, the X- and Y-registers will vary
vy ¢ group undefined or illegalvy ¢ group undefined or illegal vy
¢ group undefined or illegal6 1.4 bits per thousand per degree
change Fahrenbheit.
Data Rate

SCAN Single Tablet

SCAN Multiple Tablet
Single Point

Multiplex Latency

API Address
API Priority

200 X-Y coordinate pairs per second. The data rate can be
decreased to 1 X-Y coordinate pair per second.
100 X-Y coordinate pairs per second per tablet; used only with
VWO01IMX Multiplex option.
Determined by user’s manual activation of the spark pen
microswitch.
With the VWOIMX Multiplex option, the interval from each
writing tablet Data Ready flag to the time the next writing tab-.
let is enabled is 1.4 ms.
73
2

Controller
Mounting

Electrical
Input Voltage
Input Frequency
Power Dissipation

Mounted in VT15 controller cabinet

115/230 Vac £ 10%, single phase
47-63 Hz 500 W

Environmental
Temperature Range

Humidity Range

45°-90° F (7° - 32°C)
20-50%

3-51

XY15 X-Y PLOTTER CONTROLLER

The XY15 Plotter Controller interfaces two types of CALCOMP Plotters to the XVM I/0 bus - the
CALCOMP types 563 and 565.

The plotters, whose specifications follow, may be purchased directly from DIGITAL for inclusion in
the system. Users may also purchase these plotters, or their equivalents, directly from the manufacturer for use with the XY15.
10T Instructions

Mnemonic

Code

Description

PLSF
PLCF

702401
702402

Skip if plotter flag is a 1.
Clear plotter flag.

PLPR

702421

Plotter pen right.

PLPU

PLDU
PLDD
PLPL
PLUD
PLPD

Plotter pen up.

702404

Plotter drum (paper) upward.
Plotter drum (paper) downward.

702422
702424

Plotter pen left.
Plotter drum (paper) upward.
Plotter pen down.

702441
702442

702444

CALCOMP-563 Specifications

(Manufactured by California Computer Products, Inc.).
Mechanical

Dimensions
Type

Electrical

9.8 in. H, 39.5in. W, 14.7 in. D

Drum, tabletop

Input Power

105-125 Vac, 50/60 Hz

Plot Size

Y-axis = 28.55 in.

Stepping Increments
Stepping Speed

0.01 in. and 0.005 in.
200 and 300 steps/sec

Current
Operational

API Address
API Priority

1.5 A

X-axis = 120 ft

65
2

CALCOMP-565 Specifications
(Manufactured by California Computer Products, Inc.).
Mechanical

Dimensions
Type

Electrical

9.8 in. H, 18 in. W, 147 in. D
Drum, tabletop

Input Power

105-125 Vac, 50/60 Hz

Current

1.5A

3-52

Operational
Plot Size

Stepping Increments
Stepping Speed
API Address
API Priority

Y-axis = 11 in.
X-axis = 120 ft
0.01 in. and 0.005 in.
300 steps/sec
65
2

Controller
Mechanical
Mounting

5.25 in. logic assembly mounts in negative bus cabinet

3-53

3-54

Section 2.

UNIBUS PERIPHERALS

MEMORY

UNIBUS

PERIPHERALS:

LEima

MEMORY

UNIBUS

PROCESSOR

PERIPHERAL
PROCESSOR

[
]

[

CENTRAL

[~ PROCESSOR

PRoéégSOR‘<::

FLOATING
POINT

PROCESSOR

I/0

BUS

*::>

I/0 BUS

PERIPHERALS
15-0854

Unibus peripherals are PDP-11

Processor.

type system components which are controlled by the XVM Peripheral

One of the many advantages of the Unichannel system is that large data sets destined for slow devices
(e.g., printer plotter, etc.) can be transferred out of the XVM memory and onto the Unichannel disk.

Once this process is completed, the XVM Main Memory is free again, and the files can be output
slowly to the devices without delaying the main processor.

A brief discussion of Unibus peripherals follows. The devices included are those that are currently
supported by XVM software:

CRI11

Card Reader Controller

DP11

Synchronous Interface
Line Printer Controller

LP11

LVl
RKI11-E

Printer-Plotter
DECpack Controller

XYI11
XY3l11

Plotter Controller
Plotting System Controller

3-55

CR11 CARD READER CONTROLLER

The CR11 Card Reader reads EIA standard 80-column punched data cards at 300 cards per minute.

The punched-card reader uses a vacuum picker that works with riffle air to make card wear
insignificant, card jam virtually impossible, and provide extreme tolerance to damaged cards. The
riffling action separates the cards in the input hopper to prevent sticking. The picker uses a strong
vacuum to grasp the bottom card and deliver it to the read station on demand. The picker and associated throat block prevent the unit from multiple picking to the extent that taped or stapled cards are
not allowed to enter the card track. In such cases, the reader stops with pick check alarm. The operator
can then separate the cards and enter them into the input hopper for normal reading. The card track is
very short, so that only one card is in motion at a time. The combination of tolerance to damaged
cards, gentle card handling, and short card track provide virtually jam-proof operation for the CR11.
Operation

by column, beginning with Column 1. A select instruction starts the card moving past
Cards are read
the read station. Once a card is in motion, all 80 columns are read. Column information is read in one
of two program-selected modes: Compressed or Image. In the Compressed mode, the 12 information
bits in one column are automatically decoded and transferred into the least significant half of the Card
Reader Data Buffer (CRB2) as 8-bit compressed code. In the Image mode, the 12 bits of a column are
transferred directly into the CRBI so that Zone 9 is transferred into the CRB0O and Zone 12 is
transferred into CRB11. A punched hole is interpreted as binary 1, and the absence of a hole as binary
0.

CR11 Registers

Mnemonic

Code

Description

CRSR
CRBI

777160
777162

Reader Status Register
Data Buffer Register 1 (normal)

CRB2

Data Buffer Register 2 (encoded)

777164

Specifications

Reading Rate (cpm)
Input Hopper

300
Capacity (cards*)550 - 600
Output Hopper

Capacity (cards*)

550 - 600

Weight (max.)
Head Dissipation

70 Ib (32 kg)
1360 Btu/hour

Size Envelope

Environmental

Temperature Range

Electrical

Input Power

Power Consumption
Interrupt Priority

Interrupt Vector Address
Mounting

11in.

HX 19in. W X 14in. D (28 cmH X 48 cm W X 36 cm D)

+10° to +50° C (50° - 122°F)
Humidity Range 10 to 90%, without condensation

115 Vac, £10%, 60 Hz

230 Vac, £10%, 50 Hz
Single Phase

950 VA starting, 400 VA running
BR6 (may be changed by jumper)
Location 230
Occupies one SPC slot.

*Depending on card stock

3-56

DP11 SYNCHRONOUS INTERFACE
The DP11 is a fully character-buffered synchronous serial line interface capable of two-way simultaneous communications. The DP11 translates between serial data and parallel data. Output characters are
transferred in parallel from the computer to a Buffer register where they are serially shifted to the
communication line. Input characters from the modem are shifted into a register, transferred to a
Buffer register, and made available to the PDP-11 on an interrupt basis.

Both the receiver and the transmitter are double buffered. This allows a full character time in which to
service transmitter and reciever interrupts.
The clocking necessary to serialize the data is normally provided by the associated high-speed synchronous modem. Alternately, the internal clocking option can be used for local terminals when no external clocking is available.
The DPI1 provides a double-buffered program interrupt interface between a PDP-11 and a serial
synchronous line. This interface allows the PDP-11 to be used in remote batch and remote concentrator applications. With the DP11, a PDP-11 can also be used as a front end synchronous line controller
to handle remote and local synchronous terminals.
The DP11 interface offers flexibility. It handles a wide variety of terminals and line disciplines (i.e., line
control procedures and error control techniques). A programmer can vary sync character, character
size, and modem control leads. Automatic sync character stripping and automatic idling are also
program selectable. While idling, the DP11 transmits the contents of the sync buffer.

REMOTE

PDP - 11

DP11

MODEM

PHONE LINES

MODEM

TERMINAL

LOCAL

PDP — 11

H3I2A

gfi_“zz

NULL

MODEM

TERMINAL
15-0839

The DP11 design provides individual interrupt vectors and hardware interrupt priority assignments for
the transmitter and receiver. Interrupt priority is jumper-selectable. This feature, coupled with the
automatic transmit idle capability, enables dynamic system adjustment to peak message activity. For
example, the programmer can temporarily ignore the transmitter if receive activity is high.
Because the PDP-11’s Unibus serves as a multiplexer, multiple synchronous lines can be added to a
PDP-11. One PDP-11 system unit mounting space is used for each independent synchronous line
interface unit.
DP11 Registers

Mnemonic

Code

DPRS
DPRB
DPSR
DP
DPTB

174770
174772
174773
174774
174776

Description

Receiver Status Register
Receiver Buffer
Sync Register
Transmitter Control and Status Register
Transmitter Buffer
3-57

Specifications
Type

Operating Mode
Maximum Data Rate
Data Format

Double-buffered transmit and receive
Full or half duplex selected under software control

50,000 bits per second (9600 bits per second with the DP11-DA)
Character size is variable under program control to 6, 7, or 8

bits (10, 11, or 12 bits optional)
Synchronous clock-from the modem
(internal clock optional)

Clocking

Programmable

Sync Character
Sync Detection
Order of Bit
Transmission
Parity
Power Required
Temperature Range
Humidity Range

Two successive sync characters are required to activate the unit
Low order bit first

Parity check bit provided on incoming characters

25A0f 45V
0-40° C (32° - 104°F)
20 - 90% without condensation

Modem Compatibility (Typical)

Type

Speed (Baud)

Communications Channel

Bell 201B
Bell 303B

2400
19,200

(Leased line only - Type 3002 (C2))
(Leased line only - half group (6 voice-band lines))

Bell 201A
Bell 303C

2000

50,000

Data and Modem
Control Signals

(Direct distance dialing network — Type 3002 (C2))
(Leased line only - group (12 voice-band lines))

All leads of Bell 201 and 303 modems are brought into the unit.
All leads are EIA RS-232-C and CCITT compatible for the 201
modem. All leads for the 300 Series are Current mode as defined
in the appropriate reference manual.

Bus Load

Physical Connection

One line unit represents one unit load to the PDP-11 Unibus.
The Unibus provides 18 unit loads. To add more than 18 unit

loads, a bus extender (DB11-A) must be used.
For 201 modems. 25-foot cable with RS-232-C compatible 25pin male connector. For 303 modems, 25-foot coaxial cable
with appropriate connector.

Mounting

Backplane is a four-slot system unit.

3-58

LP11 LINE PRINTER CONTROLLER

The LP11

is the high-speed printer available for the Peripheral Processo
r. Characters are loaded into a
printer memory serially until either a control character occurs
or a count of 132 is reached, then the
entire line is printed.

Specifications
Main Specifications
Number of columns
Number of characters

Printing speed
Slew speed
Line advance time
Printing
Method
Size of Characters

Vertical Spacing
Horizontal Spacing
Character Set

64 Characters
96 Characters

132

64 or 96
300 lines/min (230 lines/min with 96 char.)
20 inches/sec

45 ms
Drum

0.095 in. H X 0.065 in. W
6 or 8 lines/inch (switch selectable)
10 char/inch

Upper-case letters, numbers, symbols
Upper- and lower-case letters, numbers, symbols

Paper
Type

Number of copies
Width
Paper feed

Ribbon
Type

Width
Length

Thickness
Register Addresses
Printer status (LPS)
Data buffer (LPB)
Unibus Interface
Interrupt Vector
Address
Priority level
Bus loading
Mechanical
Mounting
Size
Weight

Power
Input current
Current for control
Power dissipation
Environmental

Temperature Range
Humidity Range

Standard fanfold, edge-punched, 11 switch-selectable positions
between folds (3 to 14 inches), 15 Ib bond for single copy, 12 1b
bond with single shot carbon
1to6

4 to 16-3/4 inches
One pair of pin-feed tractors for 1/2-inch hole center, edgepunched paper
Inked roll

15 inches
240 feet
0.004 inches
777514

777516

200
BR4
One bus load

One free-standing unit + 1 SPC slot
45 in.(114 cm) H X 33 in. 84 cm) W X 22 (56 cm) in. D
340 1b
45A @ 115 Vac
1ISA@+5V
500 W

10° C to 40° C (50° - 104°F)
10% to 90%, max wet bulb 28° C

3-59

Models
LP11-VA
LP11-VD
LP11-WA
LP11-WD

Line printer and control, 64 characters, 115 Vac, 60 Hz
Line printer and control 64 characters, 230 Vac, 50 Hz
Line printer and control 96 characters, 115 Vac, 60 Hz
Line printer and control 96 characters, 230 Vac, 50 Hz

3-60

LV11 PRINTER-PLOTTER
The LVI11 Printer-Plotter provides quieter and more reliable operation than conventional impact
printers and pen plotters, especially under heavy, continuous use. The entire ASCII character set
(including upper- and lower-case alphabet) is printed in 132 columns per line at 500 lines per minute.
The supplied, program-controlled interface allows both printing and plotting, and accommodates
most DIGITAL line printer software. In the Plotting mode, the LV11 prints 122,880 dots per second
(independent of picture complexity) with a resolution of 10 bits (1024 dots per line). The printer-plotter
uses roll paper for continuous plots and printouts (up to 500 ft), or fanfold paper for easier handling.

The electrostatic printing technique employs a fixed writing head with 1024 addressable writing electrodes. As the paper passes over the writing head, any (or all) of the electrodes may be requested to
deposit a charge on the coated paper. The charged paper then passes over a liquid toner containing
carbon particles; the particles are attracted to the charged areas on the paper, causing the appearance
of black dots.
The only moving parts in the LV11 are the paper-moving motor and a small toner pump - simplicity of
design that guarantees long, trouble-free operation that more than offsets the small additional cost of
the coated paper.

Specifications
Printing

Columns
Character spacing
Line spacing
Font
Speed
Input Code
Character Set
Graphics
Plotting Width
Total Writing Nibs
Nib Spacing
Paper Drive Increment
Input

Input rate

Plotting Speed

General
Writing Method
Paper Drive
Paper Advance Speed
Manual controls,
switches, and indicators
Matrix switch panel

Frame mounted

132 per line
12.5 per inch
7.6 per inch (63 line/page)
7 X 10 dot matrix
Asynchronous up to 600 Ipm
USASCII - serial and parallel
96 (special)
10.24 inches
1024 (100 per inch)
10.0 mils center to center
10.0 mils
Parallel 8-bit bytes (128 bytes comprise 1 scan)
Asynchronous up to 120 scans/sec
Up to 120 increments per second
(1.20 inches per second)
Electrostatic
Incremental
1.20 inches per second

¢ [lluminated power on-off
e Paper advance
e [lluminated out-of-paper indicator
e Form feed
¢ Contrast
® Master reset
¢ Fan-fold/roll mode selector

3-61

Power required
LVOlI BALO
LVO01 BA HI
LVO1 BBLO
LVO01 BB HI
Size
Net Weight
Paper Width
Paper Length

Toner Supply
Concentrate Supply
Environmental
Temperature Range
Humidity Range
Controller
Mounting

102 +12%
118 +12%
204 +12%
236 +12%

48 to 62 Hz
600 W max
48 to 62 Hz
600 W max
48 to 62 Hz
600 W max
48 to 62 Hz
600 W max
19 in. (48 cm) W x 18 in.(46 cm) D x 38 in. (97 cm) H
160 1b (73 kg)
11 inches

500 foot roll or 1000 sheet continuous form fan-fold 11 X 8-1/2
inches
2 gallons
8 ounces

50° to 110° F (10° - 43°C)
20% to 80% R.H.

Occupies one SPC slot.

3-62

RK11-E DECPACK CONTROLLER
The RK11-E is a controller for rotating mass memories, and is capable of communica
ting with up to
eight daisy-chained disk drives. The system is block-oriented, and can handle transfers from
1 to 216
consecutive words without processor intervention. These transfers occur on the Unibus,
and are
termed Non-Processor Request (NPR) transfers.

u
N
|
B

RK 11

DISK

CONTROLLER

DISK

DRIVE

DISK

DRIVE

DISK

DRIVE

l
DISK
DRIVE
E

DISK
DRIVE
F

DISK
ORIVE
H

DISK
DRIVE
J

TERMINATOR

1n-1701

The drives used with the RK11-E are the DECpack disk drives, model RK05J. This is
a random-access
data storage device which uses a high-density single disk cartridge as the storage medium.
It has two
movable heads which fly, one above, and one below the rotating disk surface, and can read
or write
(magnetically) up to 400 data tracks, at 1500 rpm. The double-frequency, non-return-to-zero
(NRZ)
method of recording used in this device can store up to 25 million bits of data. The data formatting
is
governed by the operating system.
As the drive address logic resides in each device, up to eight RK05 disk drives can be serially
connected
to the drive bus and operated by one RK11-E controller.

RK11-E Registers

Mnemonic

Code

Description
Drive Status Register

RKDS

777400

RKER

777402

RKCS

777404

RKWC

777406

RKBA

777410

RKDA

777412

RKDB

777416

Error Register
Control Status Register
Word Count Register
Bus Address Register
Disk Address Register
Data Buffer Register

Specifications
Storage Medium
Type
Disk Diameter
Magnetic Heads Number
Recording Density and Format

Density

Tracks

Cylinders
Sectors (records)

Single disk magnetic cartridge
14 in.
Two

2200 bpi max
406 (200 plus 3 spares on each side of the disk)

203 (two tracks each)

4872 (12 per revolution)

3-63

Bit Capacities (unformatted)
Per Disk
Per Inch
Per Cylinder
Per Track
Per Sector
Access Times
Disk Rotation
Average Latency

25 million
2040 (max at inner track)
115,200
57,600
4,800/3,844
1500 + 30 rpm
20 ms (half rotation)

Head Positioning

(including settling time)

10ms - for adjacent tracks
50 ms - average

85 ms - for 200 track movement
Bit Transfer
Transfer Code
Transfer Rate

Double frequency, non-return-to-zero recording
1.44M bits per sec

Electrical

Voltage

115/230 Vac @ 50/60 Hz

Power

250 VA

Starting Current

Power only: 1.8 A

Model Designation
RKO05J-AA
RKO05J-AB
RKO05J-BA
RKO05J-BB

Environmental

Ambient Temperature

Relative Humidity

Barometric Pressure

Start spindle: 10 A (for 2 sec)

95-130 Vac @ 60 £+ 0.5 Hz
190-260 Vac @ 60 + 0.5 Hz
95-130 Vac @ 50 + 0.5 Hz
190-260 Vac @ 50 + 0.5 Hz

50° to 110° F (67° to 73° C nominal)

8% to 80% (without condensation)
30 + 3 mm hg

Dimensions and Weight

Width
Depth
Height
Weight

Controller

Mounting

19 in. (48 cm)

26-1/2 in. (66 cm)
10-1/2 in. (29 cm)
110 1b (50 kg)

Backplane is a four slot system unit.

3-64

XY11 PLOTTER CONTROLLER

The XY11 Plotter Controller provides the user with a versatile plotting capability. Plots of either
0.01
in. or 0.005 in. steps can be generated at speeds up to 300 steps per second maximum.

The XY11 Controller plugs directly into any available PDP-11 Small Peripheral Controller
slot. All
operations are under program control; either axis (or both axes) can be addressed in positive
or negative incremental steps.
A variety of popular plotters can be interfaced to the X Y11 Controller to provide
the user with drum,
fan-fold, or flat-bed capabilities. Detailed specifications concerning available plotters
can be obtained
directly from DIGITAL or from the appropriate manufacturer. The following models are
currently
available:

CALCOMP 563
CALCOMP 565
Houston Complot DP-1
Houston Complot DP-10
Full warranties and maintenance contracts are available for all plotters supplied by DIGITAL.
CALCOMP-563 Specifications
(Manufactured by California Computer Products, Inc.).
Mechanical

Dimensions
Type
Electrical
Input Power

Current
Operational
Plot Size
Stepping Increments
Stepping Speed

9.8 in. (25 cm) H, 39.5 in.(100 cm) W, 14.7 in.(37 cm) D
Drum, table-top
105-125 Vac, 50/60 Hz

1.5 A

Y-axis = 28.55 in.
X-axis = 120 ft.
0.01 in. and 0.005 in.
200 and 300 steps/sec

CALCOMP-565 Specifications
(Manufactured by California Computer Products, Inc.).
Mechanical

Dimensions
Type
Electrical
Input Power
Current

Operational
Plot Size
Stepping Increments
Stepping Speed

9.8 in. (25 cm) H X 18 in. (46 cm) W X 14.7 in. (37 cm) D
Drum, table-top
105-125 Vac, 50/60 Hz
1.5A

Y-axis = 11 in.
X-axis = 120 ft
0.01 in. and 0.005 in.
300 steps/sec

Complot DP-1 Specifications
(Manufactured by Houston-Instrument Division of Bausch & Lomb)
Mechanical
Dimensions
9.51in. (24 cm) H X 19.75 in. (50 cm) W X 14 in. (36 cm) D
Type
Fan-fold, table-top

3-65

Electrical
Input Power

115/230 Vac, 50/60 Hz

Operational
Plot Size

Y-axis = 11 in.

Stepping Increments
Stepping Speed

X-axis = 8.5 in. (144 ft overall)
0.01 in. and 0.005 in.
300 steps/sec

Complot DP-10 Specifications
Mechanical
Dimensions
Type

Electrical
Input Power
Operational
Plot Size
Stepping Increments

Stepping Speed

Controller
Mounting

6.5 in. (17 cm) H X 19.0 in.(48 cm) W X 15.33 in.(39 cm) D
Flat bed, table-top or rack-mounted
115/230 Vac, 50/60 Hz
Y-axis = 11 in.
X-axis = 8.5 or 17 1n.
0.005 1in.
300 steps/sec

Occupies one SPC slot.

3-66 -

XY311 PLOTTING SYSTEM CONTROLLER
The XY311 Plotting System is the latest in high-speed plotting facilities for the XVM Peripheral
Processor. The plotter has a large number of features, for example, three pens, giving the choice of
either three colors or three line widths.

Specifications*
Standard Drums

Increment Size

One drum for 36.72 inches (93.3 ¢cm) of paper, accommodates
roll paper up to J-Size (or equivalent millimeter size).
Y-axis electronic trim adjusts for external scaling for paper
variances.

0.002 in. or 0.05 mm - must be specified when ordering

Pens
Number

Spacing
Type
Plot Area

Physical
Height
Width

3
0.6 in. (1.52 cm)
Liquid ink or pressurized ballpoint (interchangeable)
Width (outside pens) 34.2 in. (86.9 c¢cm)
Width (any one pen) 33 in. (83.8 cm)
Length: 120 ft (36.6 m)

Depth

42 in. (106.7 cm)
50 in. (127 c¢cm)
24 in. (61 cm)

Weight

350 1b (158 kg)

Power Requirements
Heat Dissipation

Environmental
Temperature

Relative Humidity
Options
Drum.
Power

Line Frequency
Controller
Mounting

115 Vac; 60 Hz; 6 A (standard)
3413 Btu/hr (860K Calories/hr)

77° F + 18° F (25° C £ 10° C)
25 to 75%
Narrow paper drum

100V, 208 V, 230 V

50 Hz

Occupies one SPC slot.

*Specifications are subject to change without notice.

3-67

CHAPTER 4

SYSTEM OPERATION

4.1

XVM PROCESSOR

CONSOLE CONTROLS AND INDICATORS
The XVM Console (Figure 4-1) provides the switches and indicators required for operator initiation,
control, monitoring, and maintenance of the system. Any of twenty-four 18-bit registers can be displayed selectively to provide the operator with visual indications of all registers and buses.

7882.8

Figure 4-1

XVM Console

Console controls and indicators are described in Tables 4-1 and 4-2, respectively. The two rows of keytype switches are identified by corresponding rows of labels located just below the indicator portion of

the console. The upper row of labels identifies the rear switches; the lower row of labels identify the
front switches. Unless otherwise indicated, a switch function is active when the rear half of the switch is
pressed, or in the case of momentary contact switches, when the elevated half of the switch is momentarily pressed.

Table 4-1
Console Controls
Function

Type

Control

Repeat Speed/

Potentiometer/

System Power

switch

Controls the rate of repeat activity when the systemn is in Repeat mode. The repeat rate is contin-

uously variable from 1 Hz to 10 kHz. When rotated
beyond detent at full counterclockwise position,
removes all power to system.

DATA

Eighteen two-

position rocker

switches

Word length (bits 00—17) register switches to provide binary data that can be read either into the
accumulator by execution of an OAS (OR the
switch content with the accumulator content) in-

struction, or into memory under control of the
DEPOSIT or executed by the EXEC switch.

ADDRESS

START

position rocker

Specifies a memory location. These switches are
used with the START, DEPOSIT and EXAMINE

switches

switches.

Spring-loaded

Initiates program execution at the memory location
specified by the setting of the ADDRESS switches.

Fifteen two-

momentary-

contact switch
CONT

momentary-

Resumes program execution at the point that
it was halted, determined by the contents of

contact switch

the program counter (PC).

Spring-loaded

DEPOSIT THIS

In conjunction with other control switches
(SING TIME, SING STEP, SING INST), steps
the program sequentially through the desired
time states (SING TIME), major states (SING
STEP), or instruction (SING INST).

momentary-

Places the contents of the DATA switches in the
memory location designated by the ADDRESS

contact rocker

switches.

Spring-loaded

switch

DEPOSIT NEXT

Spring-loaded

Places the contents of the DATA switches in suc-

contact rocker

ceeding memory locations; the location is specified
by the ADDRESS switches plus the number of

switch

times the NEXT switch is pressed.

momentary-

4-2

Table 4-1 (Cont)

Console Controls
Control

EXAMINE THIS

Type

Spring-loaded
momentary-

contact rocker

Function

Places the contents of memory location specified
by the ADDRESS switches in the Memory Buffer

(MB) register.

switch

EXAMINE NEXT

Spring-loaded
momentary-

contact rocker

switch

Places the contents of the memory location specified by the ADDRESS switches plus the number of

times the NEXT switch is pressed into the Memory

Buffer (MB) register.

NOTE
Operation of the DEPOSIT THIS/NEXT and

EXAMINE THIS/NEXT switches does not
affect the AC, LINK, XR, LR and PC registers.

STOP

Spring-loaded

Terminates program execution when the instruc-

momentary-

tion that is in progress has been executed.

contact rocker

switch

NOTE

Operation of the STOP switch does not inhibit

I/O data channel activity.
SING TIME

Two-position
rocker switch

Used with the Continue (CONT) switch to permit
the manual stepping of the program through individual time states of each major state.

SING STEP

SING INST

Two-position

Used with the Continue (CONT) switch to permit

rocker switch

the manual stepping of the program through individual major states of each instruction.

Two-position

Used with the Continue (CONT) switch to permit

rocker switch

the manual stepping of the program through one
instruction at a time.

Table 4-1 (Cont)

Console Controls
Control
REPT

Function

Type

Two-position

rocker switch

With this switch in the ON position, the processor
will repeat the key function pressed by the
operator at the rate specified by the repeat speed
setting.

START — The program execution will restart at a
repeat rate of from 1 Hz to 3 kHz after the
machine halts.

EXECUTE — The instruction in the data switches
will be executed at the repeat clock rate (1 Hz to
10 kHz).

CONTINUE — Program execution will continue at
the repeat clock rate (1 Hz to 10 kHz) after halting.
DEPOSIT:

THIS, NEXT
EXAMINE:
THIS, NEXT

The Deposit This; Deposit

Next or Examine This;
Examine Next function will be
repeated at the rate of from 1
Hz to 3 kHz.

Pressing STOP or turning off the Repeat (REPT)
switch will halt the repeat action.

USER

BANK MODE

Two-position

When set (back half of switch pressed), pressing

rocker switch

START causes the system to start in User mode.

Two-position

When set (back half of switch pressed), pressing

rocker switch

START causes the system to start in Bank mode
permitting direct addressing of 8,192 (177773)
words of core memory. When switch is not set

(front half pressed), pressing START causes the
system to start in Page mode permitting direct
addressing of 4,096 (77774) words of core
memory.

CLOCK

Two-position
rocker switch

Inhibits program control of the real-time clock.
Program- control of the real-time clock resumes
when the CLOCK switch is OFF.

4-4

Table 4-1 (Cont)

Console Controls
Control
EXEC

Type

Function

Spring-loaded

Causes the instruction specified by the contents of

momentary-

the DATA switches to be executed. Program will

contact rocker

stop following execution of the one instruction.

switch
RESET

Spring-loaded

Clears major registers (MB, AC, LINK, PC, IR, XR,

momentary-

LR) and control flip-flops (flags, option select).
The clearing prevents any overlap of previous

contact rocker

switch

operations from interferring with new operations.

Typically RESET is activated prior to reading in
programs from paper tape.

READIN

Spring-loaded

Initiates the hardware read-in process when trans-

momentary-

ferring information from paper tape into memory.

contact rocker

The data is read into memory starting at the loca-

switch

tion specified by the ADDRESS switches.

NOTE

STOP is the only switch active while the
machine is running. If, at any time, the

machine must be reset while the RUN light is
on, the RESET and STOP switches should be
pressed simultaneously. This is an uncondition-

al reset procedure that should be used with
caution, because data can be lost.

REG GROUP

Two-position

Determines which group of registers the Register

rocker switch

Select switch can access for display in the
REGISTER indicators. When the front of the REG

GROUP switch is pressed, the contents of the
register specified in the left-hand window of the
Register Select switch are displayed in the

status information specified in the right-hand
window of the Register Select switch are displayed
on the REGISTER indicators; typically this second
group is used for maintenance purposes.

4-5

Table 4-1 (Cont)

Console Controls
Control
Register Select

Type

Function

Twelve-position

Used with the REG GROUP switch to select the
register, bus, or status data and control signals to
be displayed in the REGISTER indicators.

rotary switch

The following summarizes the REGISTER display
contents for each position of the Register Select
and REG GROUP switches.

With REG GROUP switch down (left-hand Register
Select switch window determines REGISTER

display) the REGISTER indicators display the
contents of:

00-17

Accumulator register

00—-17

Program Counter register

00-17

Operand Address register

0017

Multiplier Quotient register

PL/SC

PLO-7,SC11-17

Priority Level/Step counter

00—-17

Index register

00-17

Limit register

EAE

States 0—7

Extended Arithmetic Element

Operations 8—17

Discrete States

DSR

00-17

Data Storage register

1/0OB

00-17

Input/Output bus

STA

00-17

Input/Output Status (indicates only when the

00-17

processor is stopped)
Memory Output register

4-6

Table 4-1 (Cont)
Console Controls

Control

Type

Function

With REG GROUP switch up (right-hand Register

Switch in position:

Select switch window determines REGISTER display) the REGISTER indicators display contents

of:

ABU

00-17

A bus

BBU

00-17

B bus

CBU

00—-17

C bus

SFT

00-—-17

Shift bus

I0A

00-17

Input/Output address

SUM

00—-17

Sum bus
NOTE

The EAE, A bus, B bus, C bus, and Shift bus
output indications are complementary. Therefore, when these functions are selected for display, a lamp is off to indicate a logic 1
(assertion) and lighted to indicate a logic 0
(negation).

Twelve-position

With REG GROUP switch up (right-hand Register

Switch in position:

rotary switch

Select switch window determines REGISTER display), the REGISTER indicators display contents

of:
Register Bits

00—-17

Control Discretes Group 1
Bit 00 — Division shift to the D bus
01 — Multiply shift to the D bus
02 — Single left rotate (RAL) to the D bus
03 — Single right rotate (RAR) to the D bus
04 — Double left rotate (RTL) to the D bus

05 — Double right rotate (RTL) to the D bus
06 — No shift to the D bus
07 — Console switches to the D bus

08 — C bus to the A bus
09 — A bus to the C bus inverted
10 — Index register to the A bus

Table 4-1 (Cont)
Console Controls
Control

Type

Function

M1 (Cont)

11 — Read-in

12 — Shift left 6 to the A bus

13 — I/O address to the A bus
14 — ADDRESS switches to the A bus
15 — Operand address register (OA) to the A
bus

16 — Data in
17 — Data out
M2

00-17

Control Discretes Group 2

Bit 00 — SKIP (1) H
01 — Memory Input register (MI) inverted to
the B bus — MI-B

02 — Limit Register (LR) to the C bus — LR-C
03 — AND to the B bus
04 — Load the Accumulator (AC)
05 — Load the Memory Output register (MO)
06 — Load the Program Counter (PC)
07 — Load the Operand Address register (OA)
08 — Load the Limit Register (LR)

09 — Load the Index Register (XR)

10 — Buffered AC to the C bus — (B)AC-C

11 — Index Register (XR) to the B bus — XR-B

12 — I/O bus to the C bus — IOB-C
13 — Exclusive OR to the C bus — XOR-C

[4 — Central Processor Memory Request CP
MEM REQ (1) H

15 — Start READ

16 — Start WRITE
17 — Request Central Processor Memory
Release REQ CP MRLS (1) H

4-8

Table 4-1 (Cont)
Console Controls
Control
MMA

Function

Type

00-17

00 -ADDOOH
01 —-ADDO1 H
02

-ADDO2H

H
03 -ADDO3
H
— ADD 04
04
05 -ADD 16H
06

—NEXM (1)H

— MSYNC
(1) H

— RROOH

09 —RRO1 H
10

— RRO2
H

— RRO3
H

— RR04
H

13 — RRO5
H
14 — RRO6
H

15 —RRO7H
16

— RRO8
H

H
17 — RRO9
MMB

00-17

00 — USER MODE (1)
H
0l -GM@ODE)1 (1)
H
02-GMO(1)H

— SHARE
H

—-RDIS(1)H

05 — Not used
06 —-PV(1HH

07 —PRE(1)H
08 — BROO
09 — BRO1
10 — BRO2

11 — BRO3
12

— BR04

13 — BROS
14 — BRO6
15 — BRO7
16
— BR0O8

17 — BR0O9
MST

00—-12

Not Used

4-9

Table 4-2
Console Indicators

Indicator

Function

POWER

Indicates that the power supply voltages are at operating levels.

RUN

Indicates that the program execution is in progress.

G MODE

Indicates that systemisin GM 1, 2, or 3.

CLOCK

Indicates that the real-time clock facility is enabled.

10TD

Indicates that IOTs are trapped in User mode.

USER

Indicates that system is in User mode.

DCH ACTIVE

Lights when the data channel is being serviced, i.e., data is being
transferred between core memory and a device via the 1/O bus.

API ENABLE

Lights when the automatic priority interrupt system is activated.

API STATES ACTIVE

Indicates API level(s) active.

0-3

Hardware levels

4-7

Software levels

MAJOR STATES
FETCH

Indicates that the processor is in the Fetch state.

INC

Indicates that the processor is in the Increment state.

DEFER

Indicates that the processor is in the Defer state.

EAE

Indicates that the processor is in the EAE (extended arithmetic
element) instruction state.

EXEC

TIME STATES 1, 2, 3

Indicates that the processor is in the Execute state.

Indicates the processor time states. When all time states are off,
machine is in time state 2A of the ADD instruction.

PI ACTIVE

Indicates that a program interrupt is pending service.

PI ENABLE

Indicates that the program interrupt system is enabled (under program control).

4-10

Table 4-2 (Cont)
Console Indicators

Indicator

Function

MODE INDEX

Indicates that the processor is operating in Page mode and therefore indexing can be accomplished.

LINK

Displays state of the Link bit.

INSTRUCTION

Displays contents of the 6-bit program word instruction field.

0-3

Displays the instruction operation code.

DEFER

Indicates that the operand is indirectly addressed.

INDEX

Indicates that the operand address is indexed when in Page mode
or that the upper 4K (of an 8K bank) is addressed when in Bank

mode.

MEMORY BUFFER 00-—17

Displays the contents of the currently accessed memory address.

Used with the setting of the REG GROUP and Register Select
switches to display:
a.

Data in a register.

Data on a bus.

Control signal levels.

OPERATING PROCEDURES
Power On

Set the Repeat/Power switch to OFF.

Set primary ac power circuit breaker on 861 Power Controller at rear to ON.

Set peripheral ac power circuit breakers to ON.

Rotate the Repeat/Power switch clockwise from the OFF position.

NOTE
To prevent power from being turned off, and switches
being activated on console, set the console LOCK
switch to ON. This switch is located on the BA15
logic panel, at the bottom of the CP cabinet (Bay
00), behind the short door. For normal use leave the
switch in the UNLOCK position (down).

4-11

Program Load Procedure

To load a program from paper tape, perform the following steps:
1.

Turn System power switch ON.

Load program tape in high-speed paper-tape reader.

Set program start address into Console Address switches.

Press STOP switch.

Press RESET switch.

Press READIN switch. Paper-tape is now read into core memory.
NOTE
At completion of paper-tape read-in, the processor
executes the last word read-in as an instruction.

This procedure is also used for tabulating other types of data stored on paper tape.
Start Program Procedure
To begin data processing at a specified address, perform the following steps:

Press STOP switch.

Press RESET switch.

Enter desired starting address in ADDRESS switches.

Press START switch. Selected program will now be executed.

Manual Control of Processing
To observe the program progress on a step-by-step basis, perform the following steps:

Setthe SING INST, or SING STEP, or SING TIME switch for the desired operation; single
instruction, single step (major state) or single time (time state), respectively.

Set the ADDRESS switches to specify the selected starting address.

Press the START switch. The results of the instruction, step, or time is available at the
console displays.
'

Advance the program operation by pressing the CONT (continue) switch; or if desired,
control the functions repetition rate with the repeat speed control portion of the Repeat
Speed /System Power potentiometer switch.

Memory Examination
To examine the contents of a selected core memory address, perform the following steps:

Set the ADDRESS switches to the memory location to be examined.

4-12

Press the EXAMINE THIS switch to observe the contents of the selected address.

To observe the next sequential memory address in the MEMORY BUFFER display, press
the EXAMINE NEXT switch. Each time the EXAMINE NEXT switch is pressed, the
MEMORY BUFFER display will show the contents of the next sequential memory location; or, with the REPT switch pressed, will advance through memory locations automatically at the rate determined by the repeat speed control portion of the Repetition
Speed/System Power potentiometer switch up to a maximum of 3 kHz.
Data Storage from Console
To manually insert data into a specific memory location, perform the following steps:
1.

Set the DATA switches to the binary configuration of the data that is to be deposited into
core memory.

Set the ADDRESS switches to specify the memory location where the data is to be stored.
Press the DEPOSIT THIS switch; or, to deposit data in sequential memory locations, set the
DATA switches to the data word configuration and press the DEPOSIT NEXT switch.
Each time the DEPOSIT NEXT switch is pressed, the current DATA switch configuration
will be deposited in the next sequential memory location.
NOTE
Examining and depositing information into or out of
memory can be conducted without affecting the contents of the PC, AC, XR, LR, and L. Thus a program can be stopped, an arbitrary location can be
loaded or examined, and the program can be continued by pressing the Continue (CONT) switch. While
the program is running (RUN indicator light on), the
EXAMINE, EXAMINE NEXT, DEPOSIT,
DEPOSIT NEXT, START, EXEC (execute), and
CONT switches are not effective. The program must
be stopped by pressing the STOP switch or by pressing the SING TIME, SING INST, or SING STEP
switches. This interlock was provided to prevent accidental destruction of an operating program. Switches
which are active during RUN are located on the
upper left of the console panel.

Manual Execution of Instruction
To manually execute an instruction encoded at the console, proceed as follows:
1.

Set the DATA switches to the binary format of the instruction word.

Press the EXEC key. The processor will halt after executing the instruction.

Reset

To clear the machine states, and the /O control and devices, press the RESET key. If the machine is
hung, press both the STOP and RESET keys at the same time.
Peripheral Processor

The Peripheral Processor (Figure 4-2) indicator and switch functions are described in the following
paragraphs.
4-13

TBBZ-9

Figure 4-2

Peripheral Proccessor (PDP-11/10)

The key lock power switch (Figure 4-2) has three positions:
OFF - Fully counterclockwise
POWER - 90° clockwise from OFF
PANEL LOCK - 180° clockwise from OFF

In the OFF position, ac power is removed from the primary of the computer power supply. In the
other two positions, the ac power is applied to the computer power supply and the cabinet power
control contacts are short-circuited. In the POWER position, the console function switches (the right
six switches) are fully operative. In the PANEL LOCK position, the console function switches have no
effect on the computer’s operation. PANEL LOCK is used to secure a running computer from mischievous tampering.
Function Switches

The six right switches are called function switches. They are listed below in order of their appearance
from left to right.

LOAD ADS (load address)

EXAM (examine)

CONT (continue)

ENABLE/HALT

START

DEP (deposit)

Function switches 1 through 5 are actuated by being pressed as is the ENABLE/HALT switch in
Figure 4-2. The DEP switch must be lifted for actuation. All of the function switches, with the exception of ENABLE/HALT, are spring loaded and return to their rest state when released.
Address/Data Switches
The 16 ADDRESS/DATA switches are to the left of the function switches (Figure 4-2). These 2-

position switches represent a manually set flip-flop register with the up position representing a logical 1
and the down position a logical 0. The ADDRESS/DATA switches may be used with the function
switches or in conjunction with a program stored in the computer’s memory. The ADDRESS/DATA
switches are often referred to as the Switch register in DIGITAL documentation. In Figure 4-2, the
contents of the Switch register is equal to 2005 because bit 7 is set to a 1 and all others are set to a 0.
4-14

Console Indicators
There are 17 indicators on the computer console. The contents of the 16 ADDRESS/DATA lights
either represent a 16-bit Unibus address or the contents of a 16-bit Unibus address. Note that the state
of the ADDRESS/DATA lights is defined only when the computer RUN light is not illuminated.

CONSOLE OPERATION
The following paragraphs describe the operation of the function switches. Table 4-2 indicates the
meaning of ADDRESS/DATA lights for all cases where the contents of these lights are defined.

Load Address Switch
Pressing the LOAD ADRS switch when the computer is halted causes the contents of the Switch
register to be stored in a temporary register within the computer. This data is also displayed in the
ADDRESS/DATA lights for verification. The load address operation performs the following
functions:
.

Selects a Unibus address for a subsequent examine operation.

Selects a Unibus address for a subsequent deposit operation.

Selects the starting address of a program.

Examine Switch

The

EXAM switch permits the display of the contents of a selected Unibus address in the
ADDRESS/DATA lights. Select the appropriate address in the Switch register and press the LOAD
ADRS switch. Then press and release the EXAM switch. The contents of the selected address will then
be displayed in the ADDRESS/DATA lights. Several features are built into the examine function to
aid in programming the computer.

While the EXAM switch is pressed, the address to be examined is displayed. The data itself

is displayed when the switch is released.

If the EXAM switch is pressed repeatedly, the Unibus address is incremented by two each
~time*. This permits the examination of a list of addresses without repeated load address
operations.

If an attempt is made to examine non-existent memory, it is necessary to perform the
initialize operation, by pressing START with ENABLE/HALT in the HALT position.

Only full words are displayed in the ADDRESS/DATA lights; thus, bit 0, the byte address

bit, is ignored when using the EXAM switch with the following exception. Note that the
general registers are located on byte addresses. Therefore, when examining the general registers, address bit O is recognized and the increment feature is modified so that sequential
registers may be examined by repeated use of the EXAM switch.
Note that the EXAM switch has no effect while the computer is in the RUN state or when the key
operated power switch is in the PANEL LOCK position.

*The Unibus address is incremented by one when examining general registers.

4-15

Significance of ADDRESS/DATA Indicators
Information Displayed in

Qualification

Action

ADDRESS/DATA Indicators
Power On

ENABLE/HALT switch in

Contents of location (24)g

Undefined — Depends on

HALT position

ENABLE/HALT switch in

contents of memory

ENABLE position
Load Address

LOAD ADRS switch pressed

Contents of Switch register

Examine

EXAM switch pressed

Unibus address that is to be
examined

EXAM switch released

Contents of Unibus address
that was examined

Deposit

DEP switch raised

Unibus address that is to be
deposited

DEP switch released

Contents of Switch register
which is the data deposited

Undefined

RUN Light On
Program Halt

ENABLE/HALT switch in

Address of instruction to be
executed when CONT

HALT position

switch is actuated

HALT instruction executed

Same as 1

Double bus error which is

Contents of program

two successive attempts to

counter (R7) at time double

access nonexistent memory

bus error occurred

or improper odd byte address.
Program Execution

START switch pressed

CONT switch pressed

Address of last load address

Address of instruction to be
executed

Deposit Switch

The physical operation of the DEP switch requires that it be lifted for actuation. The DEP switch
permits the contents of the Switch register to be deposited in a Unibus address, which is typically
specified by a previous load address operation. To deposit the instruction BRANCH SELF (777s) in
location 200;, first set the Switch register to 200g, as shown in Figure 4-2, and actuate the LOAD
ADRS switch. Set the Switch register to 777s, then lift and release the DEP switch.

4-16

Several additional features are built into the deposit function:

While the DEP switch is actuated, the Unibus address to be effected is displayed in the
ADDRESS/DATA lights. When the switch is released, the data deposited is displayed for
verification.

Ifthe DEP switch is repeatedly pressed, the Unibus address is incremented by two each time*
This permits the depositing of an entire program with only one load address operation.

If an attempt is made to deposit into non-existent memory, it is necessary to perform the
initialize operation by pressing the START switch with the ENABLE/HALT switch in the
HALT position.

All deposit operations affect full 16-bit words. Bit 0 of the address is used only when depositing into general registers, otherwise, bit 0 of the address is ignored.

Enable/Halt Switch
Place the ENABLE/HALT switch in the HALT position; the computer will halt at the end of the
current instruction, providing the key switch is not in the PANEL LOCK position. All interrupts and
traps will be executed prior to halting. This switch may be used with the CONT switch to step through
programs. With the ENABLE/HALT switch in the ENABLE position, programs may be executed
once started by pressing the START switch, pressing the CONT switch, and actuating the auto-restart
power-up sequence.

Start Switch
The sequence for starting a program from the console is as follows:

Set the starting address of the program in the Switch register.

Press the LOAD ADRS switch.

Position the ENABLE/HALT switch in the ENABLE position.

Press and release the START switch.

While the START switch is pressed, the following actions occur:

An initialize signal is generated on the Unibus. This initialize signal resets all peripherals.

The program status word is reset to zero.

The program counter, R7, is loaded with the last address loaded with the LOAD ADRS
switch.

When the START switch is released, program execution begins with the instruction contained in the
location specified by R7 and the RUN light is turned on. If the ENABLE/HALT switch is in the
HALT position, the computer remains in the HALT state following the release of the START switch.
Observe the following precautions when using the START switch:
1.

If the keylock is not in the PANEL LOCK position, pressing the START switch while a
program is running initializes the computer system and restarts the program.

*The Unibus address is incremented by one when depositing into general registers.

4-17

It is good practice to precede every program start with a load address operation.

A program should not be started at an odd address or the first fetch operation will be
aborted and an odd address trap will be attempted. If the stack pointer, R6, is not properly
set up, the program in memory may be destroyed.

Continue Switch
The CONT switch is used to continue a program without altering the program counter, R7, or the
machine state. To continue a halted program, press and release the CONT switch. The program is
resumed when the CONT switch is released.
The CONT switch is used with the ENABLE/HALT switch to step through programs one instruction
at a time. If the CONT switch is actuated while the ENABLE/HALT switch is in the HALT position,
a single instruction will be executed. Note that interrupts are serviced in Single Instruction mode. In
Single Step mode, the address of the next instruction to be executed is displayed in the lights.
UNCONDITIONAL COMPUTER AND UNIBUS INITIALIZATION
Unconditional initialization of the computer system usually occurs because of an attempt to examine
from, or deposit into, non-existent memory from the console. However, a peripheral or processor error
may occur that can only be overcome by initializing the system from the console. The procedure is
simply to press the START switch with the ENABLE/HALT switch in the HALT position.
LOADING PROGRAMS FROM PAPER TAPE
The peripheral processor has no direct means of loading paper tapes as the XVM does; however, there
is a procedure whereby the XVM helps the peripheral processor to load.

The first operation is to load the ABSL11 tape DEC-15-ODABA-A-PH into the XVM memory at a
starting address of 17700. The XVM will then wait for the operator to load the requisite tape to be
transferred to the peripheral processor.
When this tape is loaded, start the peripheral processor at 100000; (for 8K of local memory), 140000
(for 12K). Then press CONT on the XVM Console. The XVM will halt when the operation is complete. The peripheral processor will obey the last instruction on the tape.
4.2

PCI15 HIGH-SPEED PAPER-TAPE READER AND PUNCH

The PC15 High-Speed Paper-Tape Reader and Punch is standard on XVM Systems. The perforated
paper-tape reader photoelectrically senses eight-channel paper-tape at a rate of 300 lines per second.
Under program control, data is read in either Alphanumeric (one-line) or Binary (three-line) modes.
The use of a paper-tape reader buffer and buffer-full flag permits the continuation of processing during
the reading functions.
The paper-tape punch (50 characters per second) is mounted on the same chassis as the reader. In
Alphanumeric mode, an output instruction causes an 8-bit character to be transferred from the XVM
Accumulator to a punch buffer, from which it is punched on the tape. In Binary mode, an 18-bit word

is transferred from the Accumulator. Fan-fold paper-tape is normally used with the high-speed papertape reader and punch.
Controls
Front Panel Controls are illustrated in Figure 4-3 and described in Table 4-3.

4-18

READER

Figure 4-3

Paper Tape Reader and Punch

Table 4-3
Paper-Tape Reader and Punch Controls

Control

Type

Function

FEED

Momentary-contact

When pressed, causes tape to

(Reader)

pushbutton

advance without reading; also clears the reader

ON LINE/
OFF LINE
FEED
(Punch)

out-of-tape flag to permit automatic
operation.
When in ON LINE position, the
reader can be activated from the computer.

Two-position
rocker switch
Momentary-contact
pushbutton

read

When pressed, causes tape to

advance, punching only feed holes.

Paper Tape Reader Operating Procedure

Directions for initiating read-in from the console are given in the console operating procedures, Paragraph 4.1. The only operator function directly associated with the tape reader is loading the tape. The
tape is stored in flat packets of fan-fold form; that is, the tape is folded back and forth upon itself. One
of the tape surfaces is imprinted with arrows at frequent intervals along the length of the tape. The
arrows indicate the direction which the tape must advance in the read operation. To install a tape in
the reader, proceed as follows:
1.

Set the processor POWER switch ON.

Set ON LINE/OFF LINE switch to OFF LINE.

4-19

On the tape reader, rotate tape hold-down knob clockwise (Figure 4-3).

Hold the packet of tape in both hands as shown in Figure 4-4 and open it to a fold at which
printed arrows are visible. Orient the tape so that the arrows point from the operator’s right

to left.

Figure 4-4

Orienting the Tape

Without changing its relative position, fold the complete packet into the right hand. With
the left hand, pull the end of the tape toward the direction in which the arrows point,
opening out the first two folds.
Place the lower end of the packet diagonally into the corner of the lower feed pocket, as
shown in Figure 4-3a.

Bend the upper end of the packet toward the read station and thrust it into the upper feed
pocket (Figure 4-5b). The packet will be supported in the feed position.
Place the extended part of the tape edgewise under the tape retainer, shown in Figure 4-5c.
The tape should now be lying flat across the read station, the printed side should be up, and
the arrows should point from right to left.
Position the tape so that the first crease is a few inches beyond the read station and ensure
that the feed holes are engaged by the feed sprocket. Rotate the tape hold-down knob
counterclockwise.
10.

Stand the free end of the tape in the receiving pockets so that the first fold is oriented toward
the read station.

4-20

Figure 4-5b

4-21

Figure 4-5¢

11.

Press the FEED switch momentarily, and observe that the tape moves from right to left and
begins to fold automatically into the receiving pockets. Advance the tape sparingly; do not
let the data portion of the tape reach the read station (Figure 4-5d).

Al
IR

T e

505

Figure 4-5d

4-22

NOTE
.
Always press the reader FEED switch momentarily.
This action is necessary to clear the out-of-tape flag
which was set automatically when the last tape was
removed.

12.

Set ON LINE/OFF LINE switch to ON LINE.

The tape is now prepared for read-in. If read-in is to be under control of the program, no further action
~ is required. If the program directions specify manual read-in, follow the console procedure for readingin from paper-tape.

Paper Tape Punch Tape Installation
New paper-tape is printed with directional arrows, and has no perforations of any kind. Tape is
furnished in 1000-ft lengths in fan-fold form, packed in pasteboard boxes. To install tape in the punch
unit, remove the top of the box completely, then proceed as follows:
1.

Slide the reader/punch unit out from the cabinet frame and insert the box of tape. Position
the box with the open side up so that the arrows on the tape are pointing from right to left
(Figure 4-6a).

Draw the end of the tape off to the right, arrow side down, twist the end slightly counterclockwise and pass it through the tape guides (Figure 4-6a).

Pass the tape over the arm of the out-of-tape microswitch and under the backing plate,
making sure that the arrows are on the under side of the tape (Figure 4-6a).
Open the hinged tape retainer outward, exposing the drive sprocket (Figure 4-6b).

Place the end of the tape between the metal tape guide-plates which are under the chad
chamber. Push the tape forward until the end passes over the sprocket; close the tape retainer (Figure 4-6b).

Turn the tape-advance control counterclockwise and observe that the tape advances; then
slide the unit back into position in the cabinet frame (Figure 4-6b).
NOTE

Make it a habit to empty the chad box when replacing tape!
Placing Punch in Service
To place the punch in service, proceed as follows:
1.

Set the processor POWER switch ON. This applies power to both the processor and the tape
unit.

Press and hold the FEED switch until four or five folds (about three feet) of tape are run
into the tape punch output hopper (Figure 4-3).

Since the punching of feed holes starts only at some distance from the beginning of tape, tear
off the tape end neatly at the first crease and discard it. This will leave about two feet of
data-free leader fully punched with feed holes for handling and threading the finished tape.

4-23

BACKING

OUT-OF-TAPE

TAPE

FEED

PLATE

SWITCH

GUIDES

BOX

(BELOW

TAPE)

Figure 4-6a

Installing Tape in High-Speed Paper Tape Punch

4-24

CHAD
CHAMBER

TAPE
RETAINER

FEED
CHUTE

TAPE
ADVANCE

CONTROL

Figure 4-6b

DRIVE
SPROCKET

(HIDDEN)

Removing Punched Tape

To remove punched tape, perform the following steps:

After punching has been completed, press the punch FEED switch and run off about two
feet of data-free trailer; tear off the output tape at a crease and remove it.

Press the punch FEED switch again to run off a new leader. The unit is now prepared for the
next program.

4-25

Chad Removal
The small disks of paper which are punched out of the tape are called chad. The punches at the punch
station strike upward and deposit the punch-outs in the chad chamber (Figure 4-6b). From there, the
chad is conducted by gravity through a tube into a removable box.
CAUTION
Remove the chad as directed.

Remove and empty the chad box before it becomes one-quarter full.

Remove any chad or dust which has accumulated elsewhere in the compartment using a
suitable vacuum cleaning device or a clean, slightly dampened cloth.

Replace the chad box.

Splicing and Repairing Paper Tape

Splicing tape is not desirable, but may be necessary in the following situations:
End of Tape - After most of the tape in the box has been punched, the approaching end of the supply is
indicated by special coloring on the remaining tape. When this coloring is observed, install new tape as
soon as possible to avoid running out of tape during a program. If the specially colored portion of the
tape should appear during a program, proceed as follows:

Press the control console STOP switch.

Press the punch FEED switch and feed out the last of the tape.

Load new tape into the unit.

Place the unit in service.

Restart the program by pressing the CONT switch on the control console.

Remove the finished tape.

Splice the leader of the second length of tape to the trailer of the first length, using rubber
cement, so that the spliced section has the following characteristics:
a.

The splice overlap is about three inches.

The portion containing the splice forms a flag segment of the same length as others in
the tape (8-1/2 in.). Do not splice over a fold.

The folds at each of the spliced segments are opposite directions.

The arrows of both tape portions are on the same side of the tape and point in the same
direction.

The feed holes in the overlap coincide exactly.

The splice does not overlap the data portion of either tape.

4-26

Torn Tape - If a punched tape has been torn between data holes or through the data portion and
duplicate tape is not readily available, proceed as follows:
1.

Align the torn edges to restore the original unbroken form as closely as possible.

Secure the two pieces together with transparent mending tape on each side of the line of feed
holes.

NOTE
If the feed holes are covered, punch the mending tape
to clear the holes.

4-27

CHAPTER 5
SYSTEM INSTALLATION

5.1
INTRODUCTION
The purpose of this chapter is to assist the reader in making decisions about the environment before
the delivery of a DIGITAL computer system. This chapter does not deal with specific devices, nor does
it supersede installation instructions in existing manuals.

There are, at present, two manuals published by DIGITAL to help prospective computer owners plan
their installation. These are:
1.
2.

Computer Site Preparation Handbook, DEC-00-ICSPA-A-D, and
Site Preparation and Planning Guide, DEC-00-HSPPG-A-D.
NOTE
Due to the multiplicity of standards throughout the
world, no reference materials have been included in
this chapter. There are, however, DIGITAL Field
Service and Sales Engineers available to answer any
questions that arise.

The complexity of the system determines, to a large extent, the quality of the environment necessary
for a trouble-free installation.
Magnetic storage devices have the narrowest operating range and this should be kept in mind when

planning an installation.
It is very unusual for a system to remain in the same configuration as when initially installed. The
majority of customers decide to ‘““add on” options after a time. This leads to changes in existing
environmental control of installations. It is therefore wise to plan computer sites with plenty of room
for expansion.
5.2

PREDELIVERY PLANNING
Each computer system installation differs in some ways from every other installation, so that no single
overall schedule of predelivery activity will apply in all cases. Table 5-1 shows a typical list of general
site preparation and installation functions, indicating those areas in which a Digital Equipment Corporation representative might be of substantial assistance.

It is important that a detailed schedule tailored for the specific installation be prepared as soon as
possible after the site has been selected and the equipment ordered. DIGITAL Sales Engineers will be
available for advice and consultation in formulating such a schedule.

Table 5-1

Summary of Site Preparation and Installation Functions
Responsibility

Function

User

Identify space and power required for the system configuration.

User/DEC Representative

Survey the proposed site.

User/Optionally DEC
Representative

Prepare site
in accordance with
environmental, space, and power requirements.

DEC Representative
DEC Representative

Unpack and inventory the equipment.
Install the equipment.

User/DEC Representative

Run customer acceptance test and perform preparation checks.

Milestone Chart

Every operation involved in computer system installation must be considered not only individually,
but alsoin relation to the overall installation schedule. This can be accomplished graphically by preparing a site preparation and facilities milestone chart showing all of the necessary operations in order
and assigning a starting date and a duration to each. Using this chart, progress can be reviewed
frequently and action can be taken, where necessary, to ensure that the overall installation program
proceeds in an orderly and timely manner.

In the case of a small computer installation, neither the schedule nor the chart will be particularly
elaborate. However, some of the larger systems will demand correspondingly more preparation and a
more involved chart.
:
The following paragraphs describe predelivery activity for what would probably represent a ““worstcase’’ installation. Most DIGITAL computer system installations are less demanding in varying
degrees.

3-6 Months Before Delivery — The Site Preparation Worksheets, which have been used in site selection
to plan the layout and determine power and cabling requirements, can also be used to help determine
the nature and location of structural renovations (floors, doors, walls, windows, etc.), air-conditioning
facilities, electrical service, and fire protection and personnel safety features. During the period from
three to six months before the scheduled delivery date, this information should be used to prepare
specifications and drawings, request bids, order equipment and material, arrange for insurance coverage, and begin construction or renovation.
1-3 Months Before Delivery — As soon as the condition of the premises permits, work should begin on
floors, walls, ceilings, doors, and windows, as well as on such major electrical and plumbing projects as
the air-conditioning and sprinkler systems. This is also the time when telephone and other communications equipment, furniture, drapes, and similar equipment and furnishings should be ordered.
Some of the data sets may entail considerable delay and should be ordered enough in advance of
delivery to ensure their timely receipt.
As the interior construction nears completion, installation can begin on fire and smoke detectors,
power receptacles, and lighting fixtures. Arrangements should also be made for any special rigging or
other equipment that will be needed for the delivery of the computer system.

5-2

Final Month Before Delivery - During this period, support facilities such as supply and service areas
should be completed and equipped, all electrical and power connections should be installed, and the
interior decor (painting, plastering, finished carpentry, and decorating) should be completed. The airconditioning system should be tested and operating before the computer system is delivered, and
should be balanced as soon as possible after system installation.
Delivery Constraints — The route the equipment is to travel from the receiving area to the installation
site should be studied in advance, and measurements should be taken to ensure problem-free delivery
of the equipment. Among the factors to be considered are the height and location of the loading door,
the size, capacity, and availability of any elevators, the number and size of the aisles and doors en
route, and any restrictions, such as bends or obstructions, in the hallways. Any constraints should be
reported to DIGITAL as soon as possible, so the equipment can be packed to suit the requirements of
the installation site. At least one interior door should be no less than 3 ft wide and 7 ft high, and
without saddles and sills, to facilitate movement of dollies.
:
5.3
SITE PLANNING
Adequate site planning and preparation can simplify the installation process and produce efficient,

reliable system operation. For the most effective site preparation, design work should be assigned to
professional engineers and architects, and construction work should be performed by qualified electrical, mechanical, and structural contractors, all supervised and coordinated by a qualified and
knowledgeable representative of the customer.
Digital Equipment Corporation sales engineers and field service representatives are available for consultation regarding the objectives, course of action, and progress of the installation.

Space Requirements
Space and layout requirements will differ with each computer installation, depending upon the system
selected, the intended applications, and the available physical area. The following categories of
required space should be considered.
|
Primary - The floor area required for the computer system itself will depend upon the components
selected, the length-to-width ratio of the area, and the location of walls, partitions, windows, and
doors. To determine the exact area required for a specific group of components, a layout should be
prepared using worksheets scaled to the measurements of the area under consideration. Operating
needs will determine the precise location of free-standing peripherals, but they must be located so that
the length of the connecting cables will not exceed the maximum limits permitted.
Within a system, there may be reasons that components are located in specific areas within cabinets or
with respect to one another. Certain pieces of equipment should be located close to one another
because of speed and timing considerations, or spread out so as not to overheat a cabinet or overload a
power supply. Equipment such as disks or tapes must be located at convenient heights because of the
nature of their operation.
Light levels should be such that illuminated display and readout devices and control units are visible to
operating personnel. The power distribution panel for the computer system should be located in an
unobstructed, well-lighted area in the computer room.
Related - Space should be provided for the daily storage of documentation, tape, cards, printed forms,
etc., within the computer area. All other combustible materials such as permanent master documents,
punched card records, magnetic tape, etc., should be stored in properly designed and protected areas.
In locating storage areas, principal consideration should be given to minimizing the amount of space
required and the travel time between related areas.

5-3

Space must also be allocated for printed forms stands, storage cabinets, card and record files, work
tables, desks, communications facilities, etc. The integration of the computer work area with other
associated areas and with storage areas must be taken into consideration. Work flow to and from other
areas should also be considered when aisles and intermediate storage locations are planned. The central processor or other control consoles should not be placed directly on main aisles or traffic centers.
If a raised floor is used for the computer area, the storage and service areas should be at the same floor
level.

Similar environmental conditions should be maintained for all areas, including magnetic tape and
paper tape storage areas. If it is not possible to maintain the storage area environment exactly the same
as that of the computer system, adequate time must be allowed to acclimate the stored materials to the
equipment environment before they are used.

In large installations where test equipment is maintained, the test equipment storage area should be
within or adjacent to the computer room. Exact space requirements should be determined by the local
DIGITAL Field Service Manager.

Potential - Future expansion through addition of equipment and enlargment of the computer area will
dictate added electrical and air-conditioning requirements. This possibility should be considered when
planning the initial site because this is the most efficient and economical time to plan for expansion.
Alternative System Configurations

Systems may be ordered under either standard or nonstandard layout plans. Standard plans provide a
fixed configuration, including standard cable lengths to free-standing peripherals. Nonstandard plans
contain either cabinet-mounted or free-standing peripherals that differ from DEC standard
configurations.
NOTE
Nonstandard configurations are subject to approval
by DEC Engineering and Field Service.
5.4

ENVIRONMENTAL PLANNING

Digital Equipment Corporation XVM Systems are noted for performing well in marginal environments. However, the operating environment of any computer system is defined by the most restrictive
device of the system, usually magnetic tape and disks. Table 5-2 shows recommended system environmental ranges. Storage temperature refers to the recommended temperature limits when the system is
in its operating configuration without power applied. When suitably packed for shipment, the system
may be subjected to short-term storage with temperature limits of -20° F to +140° F (-30° C to +60°
C) as long as no condensation occurs and rapid changes in temperature are moderated by the packing
materials.

Table 5-2
Recommended System Environmental Ranges

Operating

Storage

Temperature

65° - 75° F
(18° - 24° C)

Relative
Humidity

40 - 60%

40° - 110° F
(5° - 45° C)
10 - 80%

(without condensation)

Maintaining close control of the environment usually results in even more reliable operation. For most
DIGITAL systems, the optimum temperature is 70°F (20°C) and the optimum relative humidity is 50
percent.

5-4

Low humidity allows static electricity to build up, while lack of air cleanliness results in dust that
reduces tape life and leads to excessive head wear and early data errors in all moving magnetic storage

media (drums and disks).

Vibration can also cause slow degradation of mechanical parts and, when severe, may cause errors on
disks and drums.

Hardware logic errors can be caused by high-power radio frequency pulses conducted through power
mains or radiated through space. Such pulses could come from nearby radar installations, broadcasting stations, or welding operations, from the arcs that occur when static electricity is discharged, or
from arcing relay or motor contacts.

Air Conditioning

The ideal computer room air-conditioning system should be able to heat the room with all equipment
off, cool the computer when fully powered and active on the warmest day expected, and humidify or
dehumidify to within predetermined parameters under all anticipated weather conditions.

Room construction can be a major factor in attempting to air-condition an area. Insulation of ceilings
and walls reduces operating costs by increasing the efficiency of the system. As a result, metal walls
and partitions are not recommended unless their conditioned surfaces are insulated. Windows and
doors should be weather-tight, with double glass recommended for large window areas. Slow-operating mechanical door-closers should not be used.

DIGITAL computer systems are air-cooled, with the cooling air circulated internally by blowers in
each unit. The airflow pattern varies slightly from one unit to another, but generally air enters standard cabinets through a filter and blower in the top of the cabinet and exits through the bottom. In short
cabinets, air enters through a filter and blower at the bottom of the unit and exits at the top rear.

For efficient equipment cooling, a minimum clearance of 30 inches (76 cm) above the equipment
cabinets is recommended. If this requirement cannot be met, other means of allowing the free flow of
air above and around the equipment must be devised.

To determine approximate cooling requirements for the entire system, add the heat dissipation figures
for all of the components, and then adjust the total to allow for such factors as the number of personnel, heat radiation from adjoining areas, sun exposure through windows, system efficiency, and
potential expansion. It is advisable to allow a safety margin of at least 25 percent above maximum
'

estimated requirements.

NOTE

Long-term reliability of the air-conditioning system
can be adversely affected by powering up and down
daily. If possible, it is recommended that the system
be left on.
Air Filtration

High-efficiency mechanical filters will generally suffice unless the installation is subjected to corrosive
gasses, salt air, or other unusual conditions. If these conditions exist, an air-filtration specialist should
be consulted.

Storage of Supplies

Sufficient storage facilities must be provided for magnetic tape, disk cartridges, punched cards, line
printer paper, and any other necessary supplies in an environment roughly comparable to that of the
overall system. In addition, such supplies should be stored in a closed cabinet to eliminate con tamination by foreign matter.

5-5

Magnetic Tape and Disk Cartridges - Tape and disk cartridges should be protected from rough han-

dling, magnetic fields, dust, and extremes of temperature and humidity, all of which can have adverse
effects on performance. They should be stored in fire-resistant cabinets away from magnetic fields, and
kept in their original dustproof containers when not in use.
The storage area should be held between 60°F and 80°F (15°C and 27°C) with a relative humidity of
from 40 percent to 55 percent. Tape subjected to extremes beyond these ranges should be allowed 24
hours to reach equilibrium with the computer room before use.
Punched Cards - Punched cards, like any paper or card stock, are affected by variations in temperature
or relative humidity, especially the latter. For this reason, cards should not be stored near heated pipes,
radiators, air ducts, or windows, where abrupt environmental changes are likely to occur.
Line Printer Paper — One leading manufacturer recommends that line printer paper be stored at 75°F
(24°C) with a nominal relative humidity of 45 percent. Recommended operating ranges include temperatures from 60° to 85°F (15° to 30°C) and humidity from 40 to 60 percent.

Radiated Emissions
Sources of radiation such as broadcast stations, vehicle ignitions, and radar transmitters located in

proximity to the computer system may affect the operation of the processor and the related peripheral
equipment. The effects of these emissions can be reduced by taking the following precautions:

Grounding window screens and other large metal surfaces.

Shielding interconnection cables with grounded shields.

Providing additional grounding to the system cabinets and chassis.

In extreme radiation environments, providing a grounded cage for the system.

Disk packs must be shielded from magnetic fields. A magnetic field with an intensity of 50 oersteds
might destroy all of the information on an individual disk pack.
Altitude

Computer system operation at high altitudes encounters problems with heat dissipation. Systems operated at altitudes above 2000 m (7000 ft) may require additional internal blowers for adequate cooling.
Disk subsystems have a maximum altitude specification of 3500 m (12,000 ft).

If operation at high altitudes is anticipated, DIGITAL should be notified when the equipment is

ordered.

Static Electricity
Static electricity can be an annoyance to operating personnel and can, in many cases, affect the operational characteristics of the processor and related peripheral equipment. The two major contributors
to static electricity in computer installations are floor covering material and furniture.
Floor covering material can contribute to the buildup of high static electrical charges through the
motion of people, carts, furniture, etc., in contact with it. All raised metallic flooring, including metal

panels, should be grounded. Whatever tile or other surface material is used to cover the floor should
have a surface resistance of 0.5 megohms (minimum) to 20,000 megohms (maximum) at operating
limits of 20 to 80 percent relative humidity and temperatures from 60°F to 90°F (15°C to 32°C).

Use of carpeting in a computer room is discouraged unless the carpet can meet the same requirements
as tile covering.

" Cloth-covered chairs are normally less susceptible to the generation of static charge than plasticcovered chairs. Rubber or other insulating feet for furniture should be avoided. If casters or ball
bearings are used, they should be lubricated with a graphite or other conductive grease. Casters or
wheels with rubber tread should contain conductive material.
Lighting

The recommended light intensity in the computer room area should be in the neighborhood of 60
footcandles (650 lumens/m?) measured at desk level, approximately 30 inches (76 cm) above the floor.
This intensity is sufficient for general work in the area. In the areas immediately surrounding cathode
ray devices, illumination should be reduced to 40 footcandles (430 lumens/m?). Direct sunlight should
be avoided. The design and position of the lighting fixtures, which must be free from glare, should
consider that personnel will be operating equipment and reading indicators.

-Fluorescent lighting is popular for computer installations because it generates little heat, yet illuminates the work area evenly. The lights for general illumination should be sectionally controllable by
switches, i.e., should not be powered from the computer power distribution panel, so that portions of
the lighting can be turned off as desired.

Even where not required by code, some type of emergency lighting should be provided to protect
personnel and equipment against a sudden lighting failure.

Windows that do not face north (in the Northern Hemisphere; south in the Southern Hemisphere)
should be fitted with venetian blinds, glazed with tinted glass, or treated with protective material
against sunlight.

Cleanliness

Although cleanliness is important to all computer installations, it becomes a crucial consideration in
many cases. Figure 5-1 shows the degree of cleanliness required for RKO0S disk drive read/write heads,
for example, which “fly”” on a 100 uin film of air (air bearing).

5.5

ELECTRICAL PLANNING

The available supply of power should be adequate to handle not only the power loads represented by
the computer system, but also any loads that are likely to be imposed by future expansion. The electrical system must conform to applicable national and local codes and ordinances.
A separate power transformer for the computer installation is desirable. Where this is not possible, the
power mains for the computer system should not be used for any heavy variable loads of the sort
generated by electric motors, air-conditioning systems, etc.

The feeder supplying power to the computer system should be protected by a mainline circuit breaker,
accessible to operating personnel. The circuit breaker may be remotely operated, with remote controls
placed near the main exit door. A light should indicate when power is on.
Voltage ranges can also be critical. Table 5-3 shows the 5, 10, and 20 percent limits for the most
common voltages, rounded up for +, down for -

5-7

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Figure 5-1

08-0884

Relationship of Disk Head, Disk,

and Contaminants

Table 5-3
Voltage Ranges

-20%

-10%

-5%

84
88
92
96
102
120
176
184
192

94
99
103
108
114
135
198
207
216

99
104
109
114
121
142
209
218
228

Nominal
Voltage
100
105
110
115
120
127
150
220
230
240

+5%

+10%

+20%

105

110

120

111
116
121
126
133
158
231
242
252

116
121
127
132
140
165
242
253
264

126
132
138
144
152
180
264
276
288

Power Control System
The power control system used on Digital Equipment Corporation computers and components

depends on input power that is normally single-phase 115 Vac or 30 Vac, £10%, 47 to 63 Hz, except
for the power controller in the XVM Processor bay and memory expansion bay and the RPR02- and
RPO3-type of disk-pack drives, which require three phase (208 V or 415 V) power.

5-8

Cabinet Power Control — The cabinet power control is used in systems consisting of peripheral equipment or memory. It is operated from a remote control switch and is designed to switch and to distribute up to 24 A of 115 Vac or 16 A per phase or 230 Vac to outlets located within the cabinet. Eight
outlets provide switched ac and four outlets provide unswitched ac for operating devices.
Every cabinet contains a power control, so that only one ac cord has to leave the cabinet.
Power Control Bus Cable - The power control bus cable interconnects all devices in the system. Other
devices may be added to the system through connection to the bus in parallel at any convenient point.
The number of power controls that can be added to any system is limited only by the amount of
current that the master switch can handle. Each power control will cause 10 mA maximum to flow
through the master switch. No terminators are required on the bus, and “T”” connections may be made
without any restrictions.

Power control bus cables may be standard 3-wire cables (joining two 3-wire male Mate-N-Lok connectors) or cables with special wiring used to connect earlier type 841B or 841C power control units
into the power control system. The 841B or C requires 115 V or 230 V ac on its control bus before it
connects the main power to the power supplies. The 841 Power Control Unit is standard on PDP-15
Systems.

Power Requirements, 60 Hz Systems - DEC 60 Hz systems operate from a 115/230 Vac £10%, 60 Hz
+2%, 3-phase, Y-connected, 4-wire plus ground power system containing single-phase (115 Vac) and 3-

phase (230 Vac phase-to-phase) loads. Figure 5-2 shows a typical 60 Hz power system.

MAIN CIRCUIT
BREAKER OR

CUT-OFF CONTACTOR

PHASE A

PHASE B
MAIN SUPPLY
TRANSFORMER —————y

(ONLY SECONDARY SHOWN)

208v

208V

{20V
PHASE C

120V
§

NEUTRAL

FRAME GROUND

I |l

NOTES:

a. The neutral conductor should be grounded at the mains supply transformer

] |I ]

TO SINGLE PHASE LOADS

and if required by local authorities at the distribution panel and elsewhere.

(TYPICAL)

TO THREE

PHASE LOADS

(TYPICAL)

b. The frame ground conductor may consist of electrical metallic conduit or
raceway if approved by local authorities.

10-0863

Figure 5-2

60 Hz Power System

5-9

The manner in which ac power requirements can vary from component to component is indicated by
the following examples:
1.

Some devices require an input of 115/230 V £10%, 60 Hz £+2%, 3-phase, 4-wire plus ground
and are supplied with a NEMA L21-30P, which mates with a NEMA L21-30R. A 20 A
circuit is recommended for this type of service. Phase rotation sequence should be A-B-C or

X-Y-Z.

Other devices require an input of 115 V £10%, 60 Hz +2%, single-phase, 2-wire plus
ground, and are supplied with a NEMA L5-30P plug, which mates with a NEMA L5-30R
receptacle. A 30 A circuit is recommended for this type of service.

Some smaller devices require an input of 115V £10%, 60 Hz £2%, single-phase, 2-wire plus
ground, and are supplied with 3-wire cord for use with all standard 3-wire, grounding-type
convenience outlets. A standard appliance circuit is recommended.

In most systems it is convenient to provide one or more sepatate load centers or breaker panels for the
computer, and to connect each 20 A or 30 A receptacle to its own circuit breaker, supplying singlephase receptacles from phase to neutral connections. Each circuit breaker should be rated for 30 A,
115 Vac (or 15 A, 230 Vac) even though the average current drawn is less than half of those amounts
(15 A for 115 Vac, 7.5 A for 230 Vac).
A 25-ft (7.5 m) ac power cord is provided with most individual components, and is routed through the

bottom of the cabinet to the power receptacle via a cable access hole.
For details regarding grounding procedure, refer to Paragraph 5.5.

Power Requirements, 50-Hz Systems - DEC 50 Hz systems operate from 230/400 V £10% 50 Hz +2%,
3-phase, Y-connected, 4-wire plus earth ground power mains providing single-phase (230 V) and 3phase (400 V phase-to-phase) loads. Other main supply voltages can be accommodated upon request.

Figure 5-3 shows a typical 50-Hz power system. The following examples show how those requirements
can vary from one component to another:
.

Some devices require an input of 230/400 V +10%, 50-Hz +2%, 3-phase, 4-wire plus
ground, and are supplied with a 5-terminal pressure connector block. Plugs and receptacles
are not supplied by DIGITAL. A 10 A circuit is reccommended for this type of service. Phase

rotation sequence should be A-B-C.

Other devices require an input of 230 V +10%, 50 Hz +2%, single-phase, 2-wire plus
ground, and are supplied with a 3-terminal pressure connector block and 25 ft (8.2 m) of 3conductor wire. Plugs and receptacles are not supplied by DIGITAL. A 15 A circuit is
recommended for this type of service.

Plotters and other small devices require an input of 230 V £10%, 50-Hz +2%, single-phase,
2-wire plus ground, and are supplied with DEC part number 90-08853 plugs (Figure 5-4).

During equipment installation, these plugs may be replaced by plugs which fit local outlets.
A standard appliance circuit is recommended for these devices. (The console device plugs

into the processor and does not require a receptacle.)

In most systems, it is convenient to provide a separate load center or circuit breaker panel for the
computer, and to connect each 10 A or 15 A receptacle to its own circuit breaker, supplying singlephase receptacles from phase to neutral connections.

5-10

MAIN CIRCUIT
BREAKER OR
CUT-OFF CONTACTOR

PHASE A

MAIN SUPPLY

380/416V
l

TRANSFORMER

(ONLY SECONDARY SHOWN)

PHASE B

sem

380/

a16v

atev

220/*24OV

220/240V
| 2207240V

PHASE C L

NEUTRAL

SAFETY EARTH GROUND

RN
NOTES:

SINGLE

a. The neutrol conductor should be connected to earth ground at the mains supply

transformer. If required by local authorities it may also be earthed at the

PHASE

{TYPICAL)

DIRIPPE
LOADS

TO THREE

PHASE LOADS

(TYPICAL)

distribution paneli(s) and elsewhere.

b. The safety earth ground conductor may consist of efectrical metallic conduit or
raceway if approved

by local authorities.
10-0864

Figue 5-3 50 Hz Power' System
Power Source

‘

Computer equipment requires a power source with minimum voltage and frequency disturbances. Line
voltage disturbances greater than +10% from nominal and of a duration greater than 1/4 cycle (measured at the receptacle during system operation) are undesirable. Unstable frequencies, where local
power may drift several Hertz away from nominal, may cause wobble of up to 0.4 mm (0.015 in.) or
more, in the pictures of raster-scan cathode-ray tube displays.
Power Wiring (ac)
DIGITAL power wiring conforms to Underwriters Laboratories, Inc., Handbook U.L. No. 478,

National Electrical Code (NFPA 70) standards, and the Type II Requirements of the National Fire
Protection Association. This means that in the United States the wire used as equipment ground is
green; it carries no load current (except in emergency), but does carry leakage current. No equipment is
permitted to leave DIGITAL that does not have a grounding connection to its frame.

The grounded conductor (also called the “identified” conductor, neutral, common, ac return, cold

lead, etc.) is light grey or white. It must not be used to ground equipment, as its purpose is to conduct

current.

Lines 1, 2, and 3 are represented by black, red, and orange wires, respectively, and phase rotation is in
that order.

NOTE
On single phase cables, the power lead (or hot, etc.)
is black. This conflicts with some countries’ wiring
codes. The black conductor is used as neutral in some
countries.

5-11

Primary Power Receptacles
The type of primary power receptacles used depends largely on the requirements of the country in
which the system is being installed. In the United States, power lines should terminate, where possible,
in National Electric Manufacturers Association (NEMA) receptacles to be compatible with the
NEMA plugs supplied with most DIGITAL equipment. Waterproof power receptacles, and connectors, should be used under false floors.
Figure 5-4 details each of the approved electrical plugs and receptacles together with the NEMA
designation and the DEC part number.

To facilitate plug and cord replacement in the field, equipment designed for greater than 12 A service is
provided with terminals for solderless power connections and shipped with 12 A convenience plugs,
which require receptacles NEMA 5-15R (120 V) and NEMA 6-15R (240 V).
Separately fused and switch-controlled ac convenience outlets should be provided for test equipment
used in maintenance tasks. The outlets should be situated near the system and its related equipment,
and should be installed at approximately 10-ft intervals. In the United States, service receptacles
should be NEMA 5-15R.
Ground Requirements
A system involving a digital/analog interface usually requires that the digital system ground be tied to
the analog system ground at a single point, often at the analog/digital interface. A low-resistance
ground connection is required in such cases. Systems involving no analog interface may require no
more than the grounding provided by a large electrical conduit, although electrical conduit systems are
often poorly connected in terms of a low-resistance path to ground.
Each cabinet of a DIGITAL computer system is equipped with ground lug terminals which should be
connected to a low-resistance earth ground by No. 4 AWG (5§ mm, 0.20 in.) copper wire or stranded
No. 4 AWG welding cable. A Burndy QA4C-B solderless lug (or equivalent) is recommended for
terminating the cable. DIGITAL supplies a standard grounding conductor with each 1/O and memory
cabinet.
A large water pipe or a steel building beam is adequate in many instances, but some of the larger
systems may require additional connections to earth ground, over and above the ground leads carried
through the various signal buses and the ground conductors contained in the power cables.

Whenever possible in the larger systems, the system power panel must be mounted in contact with bare
building steel by bonded joints or connected to it by a short length of cable. An adequate ground can
be made by driving a metal rod 1.5 cm (0.625 in.) in diameter or larger into earth that is permanently
moist to a depth of at least 12 ft (3.5 m), or by burying a metal plate or grid with an area of at least 16
ft2 (1.6m?) in permanently moist earth,
Whatever grounding system is used, it must provide less than 10 ohm impedance to moist earth from

dc to 10 MHz. It must also be isolated from electrical noise sources to prevent electrical noise from
being transmitted into the system via the grounding system.
When two cabinets are bolted together, DIGITAL bonds them electrically by a No. 4 AWG conductor
(0.20 in., 5 mm) or by several copper mesh straps connected between the two cabinet frames. Auxiliary
units such as line printers or card readers may be grounded to their associated control cabinets with
No. 4 AWG copper wire.

After the grounding system is completed, it is advisable to take a voltage reading from the computer
frame to the nearest grounded metal object before touching the computer.

5-12

RECEPTACLE

PHASE 1

GREEN

WHITE

NEUTRAL

—

EARTH
GROUND

\ NEMA L14- 20R

PHASE 2

\\\ NEMA L14 -20P
U/W 861-A

U/W 861-A

pec¥12-11045-00

DEC 12-11046-00
PHASE OR
NEUTRAL

(NEUTRAL
PREFERRED)
PHASE OR

EARTH
GROUND

NEUTRAL

NEMA L6-20R

pec¥12-11192-00

pect12-11191-00
WHITE

NEMA L6 -20P
U/w 861-8

U/W 861-B

WHITE

NEUTRAL
PHASE

EARTH

GROUND

GREEN

BLACK

NEMA L5-30P

NEMA L5-30R

U/W 861-C

pEc®12-11193-00

pECH12-11194-00

EARTH
GROUND

BLACK

NEMA L21-30R

DEC#IZ- 12315-00

U/wW

861-D

GREEN

GREEN/YELLOW

NEMA L21-30P

ORANGE

pec #12-12314-00

U/w 861-D

GREEN

BLACK

WHITE

NEMA L5-15P

NEMA L5-15R
U/W 861-F

pec*12- 05351-00

U/W 861-

pec¥® 90-08938-00
GREEN

GREEN

BLACK

NEMA 6-15R

DEC¥12-14204-00

NEMA 6-15P

peEc¥ 90-08853-00
15-08861

Figure 5-4

NEMA Plugs Supplied with Digital Equipmment
Corporation’s Products

Operational Considerations
Daily powering up and down of a computer system is detrimental to long-term reliability. Where
proper safety devices exist, it is recommended that the system remain powered up, with the computer
stopped and peripherals placed off-line when not in use.
5.6 COMMUNICATIONS
Communications data sets may be used with communications systems. They should be located near
communications interface hardware, and away from noisy equipment such as printers or punches.
If the data sets are to be supplied by the customer, they should be ordered well in advance of the
installation date, as the delay between ordering and installing data sets may vary from two weeks to
two years, depending upon the model and the supplier.

Before the system is installed, synchronous data circuit installations should be tested in full duplex
operation. Digital Equipment Corporation’s Field Service organization may be of assistance in such
performance verification.
EIA/CCITT Standards
Commercial standards for carriers and data communications and terminal equipment manufacturers
are defined in EIA Standard RS-232C, prepared by the Electronics Industries Association. The Com-

itee Consultatif International de Telephonie et Telegraphie (CCITT) publishes similar standards for
European data communications users. Equipment for transmitting or receiving data over voice-grade
lines normally conforms to EIA RS-232C and CCITT recommendations.
20 mA Loop Current
Because they are suitable for a wide range of applications, currents in the vicinity of 20 mA are

frequently used for transmission of binary serial data. Connections are usually made by means of
Mate-N-Lok connectors (Figure 5-5). The computer interface normally includes a module with a
female connector; the terminal cable normally terminates in a male connector.
5.7

UNPACKING
Based on the terms and conditions of sale, it may be necessary for a Digital Equipment Corporation
representative to unpack and install certain equipment at the computer site, and perhaps even to
perform customer acceptance tests. In such cases, the customer must not attempt to unpack or install
the system or equipment without prior approval from Digital Equipment Corporation, as this would
invalidate the DIGITAL warranty.

WARNING
Do not attempt to install the system until DIGITAL

has been notified and a Field Service Representative
is present.

Unpack the equipment using the following procedures:
1.

Remove the outer shipping container.

NOTE
The container may be either heavy corrugated cardboard, plywood, or simply a polyethylene covering
depending upon travel requirements. In either case,
remove all metal straps first, and then remove any

fasteners and cleats securing the container to the
skid. If applicable, remove the wood framing and
supports from around the cabinet perimeter.

5-14

MALE MATE-N-LOCK

CONNECTOR

(INCLUDED WITH DEC 20 mAmp
TERMINALS)

' MODULE WITH FEMALE

L LI H

MATE-N-LOK

CONNECTOR

(INCLUDED WITH COMPUTER
INTERFACE )

1-1578

Figure 5-5

20 mA Mate-N-Lok Connector

Remove the polyethylene cover from the cabinets.

Remove the tape or plastic shipping pins, as applicable, from the cabinet(s) rear access
door(s).

Unbolt the cabinet(s) from the shipping skid. Access to the bolts, located on the lower

supporting siderails, is facilitated by opening the access door(s). Remove the bolts.
-

Raise the leveling feet above the level of the roll-around casters.

Use wooden blocks and planks to form a ramp from the skid to the floor and carefully roll
the cabinets onto the floor.

Roll the system to the proper location for installation.

If applicable, repeat Steps 1 through 8 for the remaining system cabinets.

When the cabinets are oriented properly, follow the procedure of Paragraph 5.9 to install the

cabinet(s).

5.8

INSPECTION
After removing the equipment packing material, inspect the equipment. Report any damage to the
local DIGITAL sales office. Inspection procedures are as follows:
1.

Inspect the external surfaces of the cabinets and related equipment fo surface, bezel, switch,
and light damage, etc.

5-15

Remove the shipping bolts from the rear door and open the rear door of the cabinet. Internally inspect the cabinet for console, processor, and interconnecting cable damage; loose
mounting rails; loose or broken modules; blower or fan damage; loose nuts, bolts, screws,

etc.

Inspect the wiring side of the logic panels for bent pins, cut wires, loose external com-

ponents, and foreign material. Remedy any defects found.

Inspect the power supply for the proper seating of fuses and the proper seating of power-

4.
5.9

connecting plugs.

CABINET INSTALLATION

The XVM Cabinets are provided with roll-around casters and adjustable leveling feet. It is not necessary to bolt the cabinet to the mounting floor unless conditions indicate otherwise (e.g., shipboard
installation). Cabinet installation procedures are as follows:
NOTE

In multiple cabinet installations, receiving restrictions may necessitate shipping cabinets individually
or in pairs. In such cases, the cabinets are connected
at the installation site.

With the cabinets positioned in the room, install the filler strips between cabinets. Remove
the 4 bolts securing the front and rear filler strips, butt the cabinets together, hold the filler
strips in place, and rebolt through both cabinets and the filler strips (Figure 5-6). Do not

tighten the bolts securely at this time.

Lower the leveling feet, making sure that the cabinet(s) are not resting on the roll-around

casters but are supported on the leveling feet.

Level all cabinets with a spirit level and ensure that all leveling feet are seated firmly on the

5.10

floor.

Tighten the bolts that secure the cabinet groups together and then recheck the cabinet level-

Remove the shipping bolts and tape from the slide runners of the reader/punch assembly.

ing. Again ensure that all leveling feet are seated firmly on the floor.

PERIPHERAL EQUIPMENT INSPECTION

All peripheral equipment should be inspected for internal and external damage. This includes
inspection of magnetic tape and DECtape transport heads, motors, paper-tape sprockets, etc.
CAUTION

Do not operate any peripheral device that employs
motors, tape heads, sprockets, etc., if they are
damaged.

5.11

ELECTRICAL AND MECHANICAL SPECIFICATIONS

Figures 5-7 through 5-11, and Tables 5-4 and 5-5 provide mechanical and electrical specifications
which are useful when planning the installation of an XVM System. Additional installation information is contained in the various manuals supplied with the system.

Table 5-6 provides cable lengths for optional peripheral equipment. For I/O bus cabling information
refer to print XV100-0-2.

5-16

O\,

////

&
AVX
/

’

AKX X7/ A

71 716

FILLER STRIPS

N
NOTE
ALL DIMENSIONS
IN INCHES

15~0096

Figure 5-6

Cabinet Bolting Diagram

FANS

cARArsL

FAN

LOGO

OP/IO0O

1
10-1/2"

CP/10

HIGH

BEZELS

SPEED

ENCLOSED

LOGIC

READER
/ PUNCH

READER
PUNCH

REAR

CONSOLE

POWER SUPPLIES

CONSOLE —,

XM15

DOOR

XM15

DEC 19" CABINET
BA1S

DOOR—————————»

BA16

DIMENSIONS
30"DEEP
21-11716" WIDE

71-7/16" HIGH

18- 0013

Figure 5-7

XVM Basic Configuration

5-1 7

SWINGING MOUNTING FRAME DOOR R.H.

“”

18-7/ 32

LEVELER 4 PLACES
REMOVABLE END PANEL

REMOVABLE END PANEL

67-17/32
> FANS

CABLE ACCESS

CASTER SWIVEL RADIUS 2-i13/32

(4 CASTERS)

SWINGING DOOR R.H.

(o516

HEIGHT- 71-7/16

o2/ 16—

NOTE :
ALL DIMENSIONS IN INCHES

FRONT

Figure 5-8

Basic XVM Cabinet

XvV100

XV 200

DR15C

CP & 1/0

cP&1I/0

RKO5

PCO4

SPARE

PCO4

Uc1s

CONSOLE

XM15

RC.

BA1S

PS.

BA15

¥ PLANNING ESTIMATIONS FOR XVM SYSTEM.
Basic System

XV100

XV 200

Current
Weight

WHEN INCREASING MEMORY ADD

A FOR EACH 8K (ME15)

A FOR EACH 16K (MF15)

NOTE:

Memory in excess of 32K (MF15) or 24K (ME)is fitted to rear door of
CP bay to@ maximum of 96K (MF15)or 72K (ME15).

Figure 5-9

15-0852

XV100 and XV200 Physical Configurations

5-18

BAY 06 L

BAY OS5 L

BAY 04 L

BAY O3 L

BAYO2 L

BAY 01 L

BAY 00

BAY 01

BAY 02

BAY O3 R

BAYO4 R

BAY OS5 R

BAY O6 R

BAYO7 R

BAY 08 R

BAY O9 R

INDICATOR|

BLANK

BLANK | AFC15

uDC15

BAY10O R

XVM

RSO9

RS09

RF15

|sge NoTg | NDICATOR

RSO9

PDP -11

CABINET

CENTRAL

RSO9

PROCESSOR

MEMORY

RKO5

BA11-K

BLANK

|IND FP15

MEMORY

H.S.READER
/PUNCH

BLANK

SEE

AD15

LP15

NOTE 1

TUse 1

TUS6

PDP-11 | CONSOLE | Tusé 2

| Tuse

FAN/

FILTER

SYSTEM

B ANK

XM15

811

SCREW

BLANK

TCS®

TC15

etc)

14/6.5
2542
420/190

23785
3324
6007270

25/7
2737
NOTE 6

325716
6256
NOTE 6

BLANK

CONNCTORS

VT158B

AR5

BLANK

BL ANK

BLANK

BA15

POWER SUP.

BLANK

H721

SURGE /NORMAL
BTU/HR
LBS /KKG

CR15

BLANK

(RK11-E

BLANK

TERMINAL

MEMORY
BA11-K

TU10

BLANK

DWi5
KC15-C

FAN/

BD15

VT15A
B L ANK

BAT1-K

;

sLank | !N

CATOR

SEE NOTE

RK105

BLANK

SEE NOTE 3 | SEE NOTE 3

RSO9

TC15

TUS6

RP15 .

FANS

IND

KP15-C

| SEE NOTE

OPTION

RSO9

BLANK

DR15C

RSO9
1st

INDICATOR

41/14.A
5630
460/ 211

375/18
7038
600/271

2017
2737
NOTE 6

18/ 6
2346
NOTE 6

1173.5
—
NOTE 6

POWER SUP. | POWER SUP.
HT721

H7 21

30742
4672
NOTE 6

30712
4672
NOTE 6

POWER SUP | POWER SUP. | POWER SUP.

18/ 6
2346
NOTE 6

H72I

H721

30712
4692
NOTE 6

30/12
4692
NOTE 6

Notes:

1. Options LT 19, DP09, XY 15 or and the
DBO09 and DBO8 are located in available

space in the H963-J cab. Order of prefer-

6. When weights are unknown, usage of an average

BAY 00

BAY 1R

cabinet weight of 500 Ibs./178 kg is recommended

Note:
Rear .door of Bav

(800 Ibs./284 kg is considered maximum worst case.)

may contain:

ence is TC59, LT19 DP09 etc. placed in the

1.Upto 64k- of MF15 Memory

:)rder listed above from -bottom .to top.

F.P15

n the event that all options are includ-

ed a second cab. is required.

2. Up to 48k of ME15 Memory
3. Up to 24kof ME15 and
32K of MF15 Memory

2. |f four TUS6's are ordered, TUS6 #3 and
#4 are installed in second cab. as shown.
3. AFC-15 and UDC-15 cabinets could be a max
of 11UDC and 11AFC cabinets each to meet
the requirements of the customer.

4. If extensive system is installed, disk

system (RF 15 and/or RP15) cabinets may be
physically separated and repositioned at
installation to maintain cable lengths.

5. Bay 2L is required only to exspanded
beyond 96K for MF15 memory or
72K of ME15 memory.

REAR
VIEWED

DOOR

FROM

FRONT
15-0980

Figure 5-10

System Configuration Diagram

5-19

Eininininininicinininininininln

v 1]

| [me9r0 casLe CONNECTOR] [km11-8 MAINT| [kmit-8 MAINT]
M7260 KD11-B PROCESSOR DATA PATHS

]

M7261 KD11-B PROCESSOR CONTROL LOGIC 8 MICROPROGRAM

M930 UNIBUS TERMINATOR

j [
G110 MEMORY

H214 (8K) MEMORY STACK

CONTROL

G231 MEMORY DRIVER

(OPTIONAL) G110 MEMORY CONTROL

(OPTIONAL) G231 MEMORY DRIVER

M920 UNIBUS JUMPER

[ topTioNaL)
H213 (4K) MEMORY STACK

M920 UNIBUS JUMPER

]

| [

M7860 DRIC ¥* 1

1ST(SPC) OPTION SLOT

2ND(SPC) OPTION SLOT

]

M7254 RK11E DISK CONTROL

BRI

M7255 RK1E

BRI

M7256 RK11E

PROCESSOR

]

M7860 DR11C #0

>UC 15

]

IRE

DISC DR BUS

»FRONT
INTER-LINK

|
DISK

[M920 JuMPER OR M930 TERMINATOR | [

M7257 RK11E

) CONTROL

]

[

]

L M930 UNIBUS TERMINATORj L

]

DD
OPTION

15-0853

Figure 5-11

Peripheral Processor Configuration Guide (PDP-11/05-NC version)

5-20

Table 5-4

Cabinet-mounted Options

Option

Description

Amps

Heat

Power

(in.)

(Ib)

at 115 Vac

(Btu/hr)

(W)

Run

Surge

TCI15

DECtape Control

15.75

0.8

4.0

327

TC59-D
BAI1S5

Magtape Control
I/O Bus Expander

21.0
5.25

50
13

2.0
2.0

5.0
5.0

784
1000

230
230

DW15-A

I1/O Bus Converter

0.6

3.0

112

FP15

Floating Point Arithmetic

21.0

150

18.0

35.0

13650

4000

PCO5

H.S. Reader/Punch

10.5

3.0

9.0

1040

306

XY15
CR15
LT19-D
LT19-E

Plotter Control
Card Reader Control
Terminal Controller
Terminal Unit (max 5)

5.25
5.25
10.5
—

16
16
25
2

1.5
0.6
2.0
2.0

4.0
4.0
5.0
5.0

600
286
47
51

180
82
14
15

DCO1-ED | Terminal Control

10.5

1.1

4.2

410

115

DP09-A

Asynchronous Data Control

10.5

0.7

4.0

253

DB09-A

Interprocessor Buffer

10.5

0.8

5.0

333

AA15

D-to-A Max Control

10.5

0.6

3.0

TUS6

DECtape Transport

10.5

3.0

9.0

1900

350

RF15

DECdisk Control

10.5

150

12.0

1955

575

RS09

DECdisk Drive (each)?

15.75

100

1.5

9.0!

585

172

AD15

A-to-D Converter

21.0

1.0

3.0

342

100

ADF15

A-to-D Converter

21.0

1.0

3.0

342

100

RP15

Disc Pack Control

21.0

7.0

2747

805

VTI15-A

Graphics Processor

21.0

3.0

9.0

2346

690

BDI15

Industrial Control

10.5

2.0

7.0

306

AFC15
UDCI15

Auto-flying Cap?
Univ. Digital Control®

—
—

12.0
12.0

30.0
30.0

1700
1700

500
500

3.0
9.0
1.8
0.6

5.0
28.0
55.0
2.5

3400
986

1000
241

322

103
762

5.25

LP15-V

Line Printer Control

10.5

TU10-E
CA15-A

Magnetic Tape Drive
CAMAC Control

26.0%
21.0

150
83

NP15

Nuclear Interface

10.5

LS15

Line Printer Control

5.25

Notes:

1'This is starting current. Disk is rarely switched off.
2If more than one full disc drive, start only one motor at a time.
3 Applies to one cabinet. Installation may include up to 11 cabinets.
4 Applies to tape unit only. Normally supplied in standard cabinet.

5-21

250

Table 5-5
Current Free-Standing Peripherals

Designation

Ib/kg

HXWXD

Surge/Normal | Btu/hr | W (Max)

An.

Amps

CRO4D

100/45.4

17 X 24 X 19
34

CRO4F

70/31.8

LA36

102/45.9

LSO1

155/70

LVO1

160/73

295/133
415/190

VTO1

51/23

260/118

1400

/4.5

1800

700

/2.6

1000

300

5/1.8

700

210

15/5.2

2040

600

25/6

4250

700

30/6

3800

700

800

250

14/7

2730

800

15/8

3120

920

390

110

3/1.5

595

175

3/1.5

626

184

52 X 21.5 X 48.5
132

1500

12X 12 X 22
30

VT04

68.7

40 X 30 X 24
102

10/3.5

40 X 30 X 24
102

RPO3

38 X 19 X 18
95

1500

33.2 X 27.5 X 24
83

RP0?2

340/154.5 | 45X 32 X 22
112

1600

13X 20 X 15
33

LPO5

12/4

122

VTO5

VTO7

VTS50

300/136

43/19.4

52 X 29 X

132

116

14 X 21 X 27
36

XY15A

33/15

53/24

9.75 X 18 X 14.7
25

XY15B

9.75 X 39.4 X 14.7
25

100

5-22

Table 5-6

Optional Peripheral Equipment Cable Lengths

Peripheral Equipment

Cable Length* ft/m
Standard

Maximum

Mass Storage Devices

TCI15

DECtape control for up to 4 TUS56 Dual DECtape
Transport Units

TUS6

Dual DECtape Transport

TC59D

Magnetic Tape Transport Control for up to 8
TU20B, TU20A, TU30B, TU30A Magnetic Tape

4/1.2

15/4.5

10/3.048

100/30.48

10/3.048

100/30.48

20/6.1

50/15.24

20/6.1

50/15.24

15/4.5

Transport Units

TUI1OF

7-Track, 45 ips Magnetic Tape Transport 200,
556 and 800 bpi

TUIOE
RF15

9-Track, 45 ips Magnetic Tape Transport 800 bpi
DECdisk Control for up to 8 RS09 DECdisk
Units

RS09

262,144 Word DECdisk

RP15

Disk Pack Control for up to 8 RP02 Disk Pack
Units

RP0O2

10.24 million-word Drive Unit — Includes one
RPO2P Disk Pack

RPO3

20.48 million-word Drive Unit — Includes one
RPO2P Disk Pack

Display Devices

VP15A

Storage Tube Display VTO1 Storage Display Unit
Control and Mounting Hardware

VP15B

Oscilloscope Display Tektronix RM503 X-Y

VP15BL

Oscilloscope Display Tektronix RM503 X-Y

Oscilloscope, Control, and Mounting Hardware

Oscilloscope, Control, Mounting Hardware, and
DEC Type 370 Light Pen

*Special quotations are required for nonstandard cable lengths,

5-23

Table 5-6 (Cont)

Optional Peripheral Equipment Cable Lengths
Peripheral Equipment

Cable Length* ft/m
Standard

Maximum

Display Devices (Cont)

VP15C

Oscilloscope Display VR12 X-Y Display Unit

15/4.5

(7 X 9 in. CRT) Control, and Mounting
Hardware

VP15CL

‘Oscilloscope Display VR12 X-Y Display Unit
(7 X 9 in. CRT) Control, Mounting Hardware,

and DEC Type 370 Light Pen

VT15

Graphic Processor

75/22.5

120/22.5

VTO04

Graphic Display Console

25/7.5

75/7.5

VTO7

Graphic Display Console

25/7.5

75/7.5

Card Reader (Table Top) — 300 characters/

10/2.134

15/4.5

25/7.62

15/4.5

25/7.62

10/3.048

0.005 in. Step 18,000 Steps/Minute

10/3.048

31 in. Drum Plotter, Model 563, and Control

10/3.048

Card Input
CR15

minute Reader and Control

Paper Tape Input
PCI15

Paper Tape Station — 300 characters/second

Reader, 50 characters/second Punch
Printers and Plotters

LP15R

Line Printer — 1000 ipm Line Printer and
Control

LP15V

Line Printer — 300 ipm Line Printer and
Control

CalComp Plotter and Control
XY15AA

12 in. Drum Plotter, Model 565, and Control

0.01 in. Step 18,000 Steps/Minute
XY15AB

XY15BA

0.01 in. Step 12,000 Steps/Minute

*Special quotations are required for nonstandard cable lengths.

5-24

Table 5-6 (Cont)

Optional Peripheral Equipment Cable Lengths

Peripheral Equipment

Cable Length* ft/m
Standard

Maximum

CalComp Plotter and Control (Cont)

10/3.048

12/3.66

Up to 2000/609.6

12/3.66

Up to 2000/609.6

Teletype Model 33 Keyboard Send-Receive Unit

12/3.66

Up to 2000/609.9

Teletype Model 33 Automatic Send-Receive

12/3.66

Up to 2000/609.9

Teletype Model 35 Keyboard Send-Receive Unit

12/3.66

Up to 2000/609.9

Teletype Model 35 Automatic Send-Receive

12/3.66

Up to 2000/609.9

XY15BB

0.005 in. Step 18,000 Steps/Minute

XY15

Control Only

Data Communications

LT19D

Multi-Station Teletype Control (Expands to 5
LT19B Line Units)

LT19E

Line Unit (One Required for each Teletype
or EIA Line Adapter)

LTI9F

EIA Line Adapter (Per Line)

LTI5A

Single-Teletype Control

Unit with Paper Tape Reader and Punch

DPO9SA

Data Communications System compatible with
EIA RS232B Interface, Bell System Type 201
Dataphone

*Special quotations are required for nonstandard cable lengths.

5-25

5.12 MISCELLANEOUS PART NUMBERS
The following is a list of part numbers, mainly expendable parts, which may help during an
installation:

DEC Part No.
90-06066-03
90-06074-01

Description
Screw Truss head
1/4-20 X 2-1/2
Screw, Phillips Phill head
10-32 X 5/8

90-07786-00

Use
Holds logo to cabinet top
Holds items to cabinet
Spring nuts for cabinet

90-08887-00

Nut Tinnerman, 10-32
Screw Cntrsunk, flat head
10-32 X 5/8
Ground strap

90-06374-08

Screw Skt hd cap

Holds cabinets together

90-08203-00

1/4-20 X 1
Nut, 10-32 keps

90-06074-02

Holds logic and latch molding

Holds cabinets with screw above

5.13

MAINTENANCE AND SERVICE OPTIONS
Digital Equipment Corporation’s Field Service Organization offers a wide range of services for DIGITAL equipment users. Customers may choose from a broad selection of Service Contract Options
and Per-Call Service of Depot Repair Maintnenance plans to ensure optimum operating efficiency for

their DIGITAL equipment.
Service Contracts

Service Contracts are tailored to the user’s individual operation. In addition to providing all the necessary parts, labor, and test equipment required for remedial maintenance, Service Contracts also ensure

system reliability by providing scheduled, systematic preventive maintenance. Planning and budgeting

are greatly simplified because these contracts allow the user to fill his maintenance needs at a fixed,
monthly charge.
Service Contract Options
On-Call Service Contract Coverage provides remedial maintenance when the customer notifies DIG-

Lo
-

ITAL of a system malfunction. Preventive maintenance is scheduled and performed during the period
selected by the user. The principal period of coverage consists of eight consecutive hours of on-call
coverage during the period 7 a.m. through 6 p.m., Monday through Friday. The user can extend his
coverage from the principal period by selecting:
Twelve consecutive hours of on-call coverage

Sixteen consecutive hours of on-call coverage
Twenty consecutive hours of on-call coverage
Twenty-four consecutive hours of on-call coverage

Coverage of 24 consecutive hours, Monday through Friday, begins on Monday of each week at 7 a.m.
and terminates on Saturday of each week at 7 a.m.
The Saturday period of coverage consists of eight consecutive hours of on-call coverage during the
period 7 a.m. through 6 p.m. The Sunday period of coverage consists of eight consecutive hours of on-

call coverage during the period 7 a.m. through 6 p.m. As with the principal period of coverage, Saturday/Sunday coverage can be extended to 12, 16, 20, and 24 hours.

An on-site resident engineer plan can be implemented if the size, complexity, and /or critical nature of

an installation require such a plan. The services of a resident engineer consist of 40 hours of coverage
during the normal work week. In addition, all necessary spare parts, materials, and test equipment are

5-26

physically stationed at the user’s site to further ensure prompt and efficient remedial and preventive
maintenance services. Monthly rates for contracted coverage are supplied on request.
There are no additional charges for travel in connection with service contracts except for remote
installations. Remote installations are defined as installations located at a distance greater than 100
miles from a DIGITAL Field Service Office.
Eligibility for Service Contract Coverage

A Pre-Service Contract Inspection is required for installations that were not under DIGITAL’s
maintenance responsibility immediately prior to the requested commencement date of the service
agreement. All charges associated with this inspection (including travel, labor, and parts) are billed to
the user at the prevailing standard DIGITAL rates. A minimum charge is associated with the PreService Contract Inspection. No inspection is required for service agreements that are scheduled to
commence immediately after the expiration of a standard DIGITAL Warranty or Service Contract.
-

Per-Call Coverage

Per-Call Coverage is designed to permit the users of DIGITAL equipment to obtain service on a time
and materials basis. Requests for Per-Call Coverage are considered after requests for Service Contract
Coverage; thus, only users with their own service capabilities or users who are not critically tied to
their equipment are encouraged to use this form of coverage. All charges for Per-Call Coverage are
computed on a portal-to-portal basis. Commercial travel expenses related to the performance of services are billed as incurred. Material and parts consumption associated with Per-Call Coverage are
charged to the user at the prevailing prices listed in the DEC Spare Parts Catalog. Labor charges for
Per-Call Service are on an hourly basis and are available on request.

A minimum charge for Per-Call Service applies to each service call; in addition, DIGITAL neither
implies nor guarantees the availability of Per-Call Coverage outside the hours of 7 a.m. through 6
p.m., Monday through Friday. Users in need of extended periods of coverage are encouraged to use
the many Service Contract options available.

Users receive an invoice for all service rendered under Per-Call Coverage. It is the responsibility of the
user to inform the DIGITAL Field Service Office servicing the equipment of any special billing
instructions related to the use of Per-Call Coverage. Such notification must be rendered before the
commencement of any services on the part of DIGITAL; in the absence of such notification, invoicing
shall be accomplished in accordance with procedures determined by DIGITAL. Installations requiring
Purchase Orders for the authorization of work performed on a time and materials basis are encouraged to submit a blanket order for one year’s duration to cover such services. There will be no additional charge for processing and administering such blanket orders. Terms for all services provided on
a per-call basis are net 30 days. In addition to the charges outlined above, customers are also charged
for all federal, state, municipal, or other government, excise, sales, use, occupational, or like taxes,
now in force or enacted in the future, incurred as a result of the performance of per-call service.
Installations enjoying tax exemption are requested to present their current exemption certificate number at the time that Per-Call Service is rendered or with the submission of the blanket Purchase Order.
Depot Repair

Depot repair facilities have been strategically located throughout the world to enable users of DIGITAL equipment to receive prompt, efficient service on many standard DIGITAL options. Depots are
also fully equipped to service and completely rebuild, if necessary, ASR and KSR Teletypes®. Furthermore, users of DIGITAL equipment interested in purchasing rebuilt ASR and KSR Teletypes, or
using their existing Teletypes on a trade-in basis toward the purchase of new machines, are urged to
contact their nearest DIGITAL Field Service Office for further information.
®Teletype is a registered trademark of Teletype Corporation, Skokie, Illinois.

5-27

Depots are fully equipped and staffed with experienced personnel to offer rapid and economical repair
services to the DIGITAL customer. At the user’s option, a national transportation firm, contracted by
DIGITAL, can be used to route equipment to and from the depot facility. Customers wishing to use
the depot facilities are requested to contact the nearest depot and furnish the following:
1.

Customer name

Customer address

Purchase order number

Billing address

Name and telephone number of individual

Type, model number, and serial number of equipment to be serviced

Brief description of service problem or malfunction

Mode of transportation to be used (DIGITAL carrier or other)

Upon receiving the above information, the depot issues a return authorization number that enables the
user to ship the equipment for servicing.
‘
Field Installation of Additional DIGITAL Options
Customers wishing to expand their present systems by purchasing additional DIGITAL options may
elect to have the installation of the new equipment performed at a fixed rate to facilitate the budgeting
and purchasing processes.

Field installation rates are available on request. To compute the installation charges for an option or
group of options, the total charge is equal to the sum of the option installation charges plus a one-time
travel charge.
For the purpose of performing field installations, remote locations are defined as areas outside those
areas normally serviced by DIGITAL or its subsidiaries. Requests for installations in remote locations
are considered on an individual basis. Field installations are performed from 7 a.m. to 6 p.m., Monday
through Friday. A minimum charge is associated with a field installation.

nkw

5.14 FORMS AND CHECKLISTS
A large envelope, enclosed with the XVM Accessory Kit, contains the following items:
Customer acceptance forms
Key sheet
Customer data forms
Software trouble reports
DECUS information
Basic accessory checklists
Optional equipment checklists
Software checklists
Final distribution lists

Each of the items listed is discussed in the following paragraphs. The sole intent of this information is
to produce uniformity in customer acceptance procedures.

5-28

Customer Acceptance Forms

‘

The customer acceptance forms are logged at DIGITAL in Maynard, Massachusetts, prior to equipment acceptance. The form lists the equipment items that are included in the shipment. The customer
name, the DEC installation code, the DEC order number, and the customer purchase orders are also
included on the form. Personnel installing the equipment must check the keyed equipment serial numbers listing against the serial number on the equipment and enter the serial numbers in the appropriate
column on the customer acceptance form. All serial numbers, including those on vendor-supplied
material, are verified in this manner.

All future XVM System additions, modifications, and inquiries are solely dependent on the accuracy
of the key sheet, which lists all system components by model and serial number, and the acceptance
forms. Upon successful completion of acceptance testing, any “‘exceptions” are listed in the appropriate section on the customer acceptance form. The “exceptions’ should include missing manuals or
prints and any hardware, etc., that was not acceptable.
Customer Data Forms

The customer data form is used to establish an accurate mailing list and customer contact file. The
form should be completely filled out and the appropriate copy returned to DIGITAL’s Field Service
Organization in Maynard, Massachusetts.

Software Trouble Reports

Software trouble reports enable the customer to communicate directly with the DIGITAL Software
Group. Any software problems should be described in detail and, if possible, examples attached.
DECUS Information

The DECUS information and introductory letter familiarizes the user with the Digital Equipment
Computer User’s Society. The letter invites membership and includes application forms.
Basic Accessory Checklist

The basic accessory checklist contains an accurate list of all items that are normally supplied with the
basic XVM. DIGITAL personnel check each item on this list with the customer, and the customer
then signs the complete form. The appropriate copy is then returned to DIGITAL in Maynard, Massachusetts. The remaining copies should be distributed as indicated on the bottom of the form. Specified items that are not included should be listed as “‘exceptions’ on the customer acceptance forms.
Optional Equipment Checklist

Accessory checklists for each option are supplied. The basic accessory checklist procedures apply.
Software Checklist

The software checklist enclosed has been checked at the factory and is rechecked with the customer.
Any items missing should be listed as “‘exceptions”. This form is also signed by the customer and
returned to DIGITAL in Maynard, Massachusetts. Requests for additional copies of programs should
be submitted to the DIGITAL Program Library.
Final Distribution of Forms

The return-addressed envelope is sent to DIGITAL in Maynard, Massachusetts with the following
Nounbkwhe

completed forms:

Customer acceptance forms
Customer data forms
Basic accessory list
Optional equipment checklist
Software checklist
Installation report
Final distribution lists
5-29

All of these items, except 2 and 6, require the customer’s signature. Only items listed as ‘“‘exceptions”
are replaced at no cost. All other items must be substantiated by a customer purchase order.
A complete set of prints is supplied with the XVM System. The key sheet should be used to reference
the Master Drawing List (MDL) or Drawing Directory for each subsection or option in the XVM
System. Wire lists, parts lists, and mechanical assembly prints are not supplied with any print set.
These may be obtained only by special order.
Computer System Layout Checkoff/Transmittal Sheet
When planning an XVM System installation, use the Computer System Layout Checkoff/Transmittal
Sheet as a guide to keep track of key items that must be considered during the planning stage. After
planning has been completed, forward the Computer System Layout Checkoff/Transmittal Sheet to

the DIGITAL salesperson from whom the system was purchased.

5-30

CHAPTER 6

INSTRUCTION FORMATS

6.1

BASIC INSTRUCTION SET

The XVM Instruction Set is divided into ‘“memory reference instructions,’”” which address core memory, and “‘augmented instructions,” which do not address core memory. Memory reference instructions
address, either directly or indirectly, core memory locations for the purpose of retrieving, entering, or
modifying the contents. The augmented instructions are used to execute a certain action or actions.
This type of instruction is subdivided into four groups: operate instructions (Link and Accumulator
operations including rotates, skips, clears, and complements); IOT instructions (input/output transfer
of data, command and status between the central processor, and peripheral devices); EAE (extended
arithmetic element, hardware multiply, divide, shift, and normalize); and index instructions (accumulator, limit register, and index register transfers, clears, additions, and skips).
Memory Reference Instruction Format

The memory reference instruction word consists of an operation code, an indirect address bit, and
index bit, and an operand address (Figure 6-1). The operation code, bits 0 through 3, specifies one of
the 13 XVM memory reference instructions. When the XVM is in Page mode, the indirect bit (bit 4)
indicates whether the 12-bit (bits 6-17) operand address is to be directly or indirectly (bit 4=1)
addressed and the index bit (bit 5) determines whether or not the index register should be added to the
operand address. In Bank Mode, the indirect bit (bit 4) indicates whether the 13-bit (bits 5-17) operand
address is to be used as the direct address or the indirect address (bit 4=1). The operand address is used
to generate the effective address or the address in memory which will be referenced. A detailed description of addressing is located in Chapter 1, Paragraph 1.2.

OPERATION CODE

INDEX BIT
%

00g-60g

(1= INDEXED)

A
0}

\
2

—

)

INDIRECT

10 | 11

113

|14

|35

{16

|17

OPERANCY) ADDRESS

ADDRESS

(1 INDIRECT)

*USED AS A THIRTEENTH ADDRESS BIT IN BANK MODE
.

Figure 6-1

Memory Reference Instruction Word

6-1

15-0188

Augmented Instruction Format

The augmented instruction word (Figure 6-2) consists of an operation code and an instruction code.
The operation code designates whether the instruction is an extended arithmetic element instruction,
645(bits 0-3), an Input/Output transfer instruction, 70s(bits 0-5), an Index instruction, 72g(bits 0-5) or
an operate instruction 74g(bits 0-3). The instruction code designates which action is to be taken by the

augmented instruction. An important and useful feature of the XVM augmented instruction is its
microprogramming capability. Multiple instruction codes having the same operation code can be combined to form one instruction word. Execution of all microprogrammed functions occurs during the
time allocated to the type of instruction (operate instructions require one machine cycle, IOTs require
two, three, or four cycles, EAE requires one or three, plus a variable time interval to complete their
function, and index instructions require two cycles). Thus, microprogramming decreases program
running time, lessens the number of instruction words required, and simplifies programming efforts.

SIGN

0—-POSITIVE
1 - NEGATIVE

SIGNED NUMBER

v
o

A
|

|10]|11

|12

13|

14|15

16|17

5%
6

112

|13 | 1415 | 16 | 17

OPERATION CODE
643=EAE
70g =10T

72g
= INDEX
74g = OPERATE
A

1t
Y

INSTRUCTION CODE

*THESE BITS USED AS PART OF THE INSTRUCTION CODE IN EAE AND
OPERATE INSTRUCTIONS
15-0204

Figure 6-2

Augmented Instruction Format

Timing
The amount of time required to perform each instruction is expressed in the number of machine cycles.

Instructions that indirectly address memory require one extra machine cycle to fetch and compute the
indirect address. Only one level of indirect addressing is allowed on the XVM.
Instructions that use the auto increment locations indirectly require two extra machine cycles; one for
the increment of the location, and one for the indirect address.

Memory Reference Instructions
In the memory reference instruction descriptions, and in succeeding paragraphs that describe other
types of instructions, the following symbols are used:
Symbol
Y
OR

Definition
The effective address of the memory location
Logic inclusive-OR
Indicates contents transferred from register or location to register or location.
Logic AND
Logic exclusive-OR
Indicates complemented contents of register or location.
Addition

AND
XOR
-OR
+

LOAD THE ACCUMULATOR

LOAD THE ACCUMULATOR
LI
20

]

Iol

]

Operand Address

DR I

]

LAC

15-0862

Mnemonic Name
Octal Code
Time
Operation

LAC
20

2 cycles
The contents of the effectively addressed memory location, Y,
are read into the AC. The contents of Y are unchanged, the
previous contents of the AC are lost.

Symbolic

Y to AC

DEPOSIT THE ACCUMULATOR

DEPOSIT THE ACCUMULATOR
T

]

—

Operand Address

DAC
15-0863

Mnemonic Name
Octal Code
Time

DAC
04
2 cycles

Operation

The contents

of the AC are deposited in the effectively

addressed memory location Y. The contents of the AC are
unchanged; the previous contents of Y are lost.

Symbolic

ACtoY

6-3

DEPOSIT ZERO IN MEMORY

DEPOSIT ZERO IN MEMORY
l

1
L

Operand Address

{

DZM

15-0864

Mnemonic Name
Octal Code
Time

DZM
14
2 cycles

Operation

An all-zeros data word is deposited in the effectively addressed

Symbolic

memory location Y. The previous contents of Y are lost; the
contents of the AC are unchanged.
OtoY

ADD (2’s COMPLEMENT)

—

—1

Operand Address

TAD

15-0865

Mnemonic Name

TAD

Octal Code

34
2 cycles
The contents of the effectively addressed memory location Y are
added to the contents of the AC, following the rules of 2’s complement arithmetic. The result is left in the AC. An arithmetic
carry from ACy complements the link. The contents of Y are
unchanged; the previous contents of the AC are lost.
Y + (L,LAC) to (L,AC)

Time
Operation

Symbolic

6-4

ADD (1’s COMPLEMENT)
ADD (1's Complement)
|

[

]

Ill-l.llll

Operand Address

{

ADD

15-0866

Mnemonic Name
Octal Code
Time
Operation

ADD

|
30
2.3 cycles
The contents of the effectively addressed location Y are added
to the contents of the AC, following the rules of 1’s complement
arithmetic. The result is left in the AC. An arithmetic overflow
sets the link to the binary 1 state. The contents of the AC are
lost. The previous contents of the link are lost. Overflow occurs
if the magnitude (absolute) of the algebraic sum of the operands
exceeds 2!7-1; if the operands were of like sign and the result is
signed differently, overflow has occurred to set the link. Overflow cannot occur if the operands are of different sign.
NOTE
The link should be cleared prior to the ADD instruction, if an arithmetic overflow check is desired.
Y + AC to AC
L OR Overflow to L

Symbolic

INCREMENT AND SKIP IF ZERO
INCREMENT AND SKIP IF ZERO
|

Operand Address

1ISZ

15-0867

Mnemonic Name
Octal Code
Time
Operation

Symbolic

ISZ
44
3 cycles

The contents of the effectively addressed memory location Y are
incremented by one (in 2’s complement arithmetic) and tested.
If Y now contains an all-zero word, the PC is incremented by
one to skip the next instruction. If the contents of Y, after being
incremented, are other than zero, the next instruction is executed. The previous contents of Y are lost; the contents of the
AC are unchanged.
IfY+1=0 PC+1toPC
Y+ 1toY

6-5

SKIP IF AC DIFFERS
SKIP IF AC DIFFERS

Operand Address

SAD

15-0868

Mnemonic Name
Octal Code
Time
Operation

SAD
54
2 cycles

The contents of the effectively addressed memory location Y are
compared with the contents of the AC. If they differ, the PC is
incremented by one to skip the next instruction. If they are the
same binary quantity, the next instruction is executed. The contents of Y and the contents of the AC are unchanged.
If Y is not equal to AC, PC + 1 to PC

Symbolic

BOOLEAN AND

Operand Address

AND

15-0869

Mnemonic Name
Octal Code
Time
Operation

Symbolic

AND

50
2 cycles

The contents of the effectively addressed memory location Y are
logically ANDed with the contents of the AC on a bit-by-bit
basis. The result is left in the AC. If corresponding Y and AC
bits are in the 1 state, the AC bit remains a 1; otherwise, the AC
bit is cleared to the O state. The contents of Y are unchanged;
the previous contents of the AC are lost.
Y AND AC to AC

6-6

EXECUTE THE INSTRUCTION AT Y

XCT

15-0870

Mnemonic Name
Octal Code
Time
Operation

XCT
40
1 cycle plus time of instruction at Y
The computer executes the instruction located at the effectively
addressed memory location Y. The contents of the PC are
unchanged unless Y contains a JMS, CAL, JMP, or skip
instruction, each of which changes the contents of the PC to
alter the program sequence. XCT could be thought of as a
single-instruction subroutine causing a quasi-jump to Y, execution of the instruction specified there, and return to the program
sequence (i.e., execution of the instruction following XCT) if the
instruction has not changed the PC.
When in User mode, an XCT of an XCT instruction is not
allowed.
Yo-s to IR

Symbolic

BOOLEAN EXCLUSIVE OR
BOOLEAN EXCLUSIVE OR
|

Operand Address

XOR

15-0871

Mnemonic Name
Octal Code
Time
Operation

XOR

Symbolic

Y XOR AC to AC

24
2 cycles

The contents of the effectively addressed memory location Y are
exclusively-ORed with the contents of the AC, on a bit-by-bit
basis. The result is left in the AC. If corresponding Y and AC
bits are in the same binary state (i.e., 1 or 0), the AC bit is
cleared to the O state. If the corresponding bits differ in state,
the AC bit is set to the 1 state. The contents of Y are unchanged.
The previous contents of the AC are lost.

6-7

UNCONDITIONAL JUMP
UNCONDITIONAL JUMP

lllllllllll
60

Operand Address

JMP

15-0872

Mnemonic Name
Octal Code
Time
Operation

JMP

60
1 cycle
A new address is computed from the operand address of the
Jump instruction and transferred to the PC. The next instruction fetched will be from the memory location specified by the
new address. The contents of the AC are unchanged.
Ys.17 to PC

Symbolic

JUMP TO SUBROUTINE
JUMP TO SUBROUTINE
UL

]

Operand Address

]

JMS

15-0873

Mnemonic Name

JMS

Octal Code
Time
Operation

2 cycles
The contents of the PC and the Link, and the status (on or off)

of Bank mode and User mode are deposited in the effectively
addressed memory location Y. The next instruction is read from
the contents of memory location Y + 1, breaking the previous
program sequence and starting a new sequence from Y + 1. The

Symbolic

contents of the PC are changed, and the contents of the AC are
unchanged.
When not in the User mode, a free instruction follows the JMS.
Therefore, a PI or API break cannot occur after the execution
of the JIMS instruction, but may occur after the execution of the
next instruction,

L to Yo

BM to Y]

UM to Y,
PC to YY5-|7 + 1 to PC
NOTE
If the system is in G-Mode 1, 2, or 3, and in User
mode when a JMS is executed, PC 00-17 will be
stored in addressed location Y. The state of the Link,
Bank mode, and User mode will not be stored.

Symbolic

PC to Yo-17, Ys.17 + 1 to PC

6-8

(JUMP TO) SYSTEM
CALL (JUMP TO) SUBROUTINE
I

Operand or Operand Address

CAL

15-0874

Mnemonic Name
Octal Code
Time

CAL
00
2 cycles

Operation

The CAL instruction is similar to a JMS 20 instruction. The
contents of the PC and the Link, and the status (on or off) of
Bank mode and User mode are deposited in real memory location 20. The next instruction is read from real memory location
21, breaking the previous program sequence and starting a new
sequence from 21. The contents of the AC are unchanged. If the
API system is enabled, priority level 4 will be activated after the
execution of a CAL instruction if no higher priority level is set.
When the CAL instruction is executed, the processor re-enters
Exec mode and the instruction in location 00021 will be executed before an interrupt is allowed to occur.
The CAL instruction is used in all XVM Software to enter and
request services of the operating system.

Symbolic

L to 20,
BM to 201
UM to 20,
PC to 203-17
“21” to PC
0 to UM

Augmented Instructions

Operate Instructions
Operate instructions (operation code of 74;) are used to sense and/or alter the contents of the AC and
Link. Typical functions are: conditional or unconditional skips, complementing, setting, clearing, or
rotating the contents of the two registers jointly or independently and incrementing the AC. A Halt
(HLT) instruction is included. Operates are performed in one machine cycle, the actions specified by
the microprogramming of the instruction code. Each bit of the 14-bit instruction code can effect a
unique response; hence, they are “microinstructions’ to the computer. The important feature of the
operate class is its microprogramming capability, where two or three microinstructions can be combined to form one instruction word and, therefore, be executed in one cycle. Those microinstructions
that logically conflict and occur at the same time should not be microprogrammed. Figure 6-3 illustrates the bit configuration of the instruction code. Figure 6-4 shows the allowable combinations of
microinstructions.

Bit 7=0

Additional

CLAICLL

0=0R of | SNLISZA]|SMA

Rotate

RAR]

RAL

1=AND of | SZL|SNA]SPA HLT RTR |RTL OASICMLICMA
Bit 7=1

516
NOTE:

Bits 7,

13, and 14 set:

Bits 13 and 14 set:

9 110 [ 11

|12

13h4

116 | 17

SWHA

1AC
15.0875

Figure 6-3

Order
of
Events

Column 1

Level 1

SNL SZA SMA

Level 2

SZL

Level 3

SNA

Instruction Bit Configuration

Column 2

SPA

Column 3

OAS CMA
CLA CLL

SKP

Column 4

CI:XACL

RAR or RAL

HLT

RTR or RTL or SWHA
15-0876

Figure 6-4

Allowable Microinstruction Combinations

NOTE 1
When noninverted skip actions are microprogrammed (bit 8 is 0), the conditions to be met are
inclusively ORed. For example, if SZA (740200) and
SNL (740400) are combined (740600), the skip takes
place if either or both conditions are present (contents of the AC are 0 or the content of the link is not
0).
NOTE 2
When inverted skip actions are microprogrammed
(bit 8 is 1), the skip occurs only if the AND of the
conditions is met. For example, when SNA (741200)
and SZL (741400) are specified in a microprogrammed instruction (741600), the skip occurs
only if both conditions are present (the contents of
the AC are other than 0 and the content of the link is
0).
Programming Note
The XVM MACRO Symbolic Assembler accepts
either HLT or XX (Figure 6-4) as a valid mnemonic
for the operate class instruction to stop program execution. The latter facilitates visual scanning of a program listing to determine the occurrence of program
halts.

6-10

Combine instructions from left to right.

Any instructions in a box can be combined, except the rotate instructions.

Instructions on different levels cannot be combined if they are in the same column. Instructions on any level can be combined if they are in different columns. For example,
SZA!SMA!CLA!OAS!'HLT! is legal - SZA!SPA is illegal.
CML and IAC cannot be combined. Either one can be combined with OAS and/or CMA
(e.g., OASICMA!ICML or OAS!ICMA!AC).

Instructions occur in order from column 1 to column 4.

OPERATE INSTRUCTIONS COMBINING CHART
1

SNL

SZA SMA

SZL

SNA

CLL CLAOAS

SPA

CMA

IAC

HLT

RAR

SKP

RAL
RTR

RTL
SWHA

.
.
.
.

Instructions occur in order 1 through 4.
Instructions may be combined unless they are in different boxes in the same column.
The following skips are combined as if ORed: SNL,
SZA SMA.
.
The following skips are ccmbined as if ANDed: SZL,
SNA, SPA.
CML occurs at time 3 and can be combined normally
with everything except I1AC and Rotates.
CML combined with IAC executes as a CML! STL and
therefore should not be used.
CML combined with a rotate will cause the new state
of the L to be an OR of the compliment of the L and
the state rotated in and therefore should not be used.
SWHA combined with CLA will leave the AC in the
same state as it held before the instruction was executed and so should not be used.

9. SWHA and
0.
1.

Rotates will

cause the following to be ig-

nored: OAS, CMA, IAC.
LAW will cause all other microcodes to be ignored.
All illegal combinations not otherwise mentioned will
correspond to some correct microcode of different
meaning and be executed as such.

OPERATE GROUP
0

1011

79 OP CEDE
LAW
CLA
CLL

ROTATE 2

(SWHA)

INVERT SKIP SENSE (SKP)
SNL (SZL)

SZA (SNA)
SMA (SPA)
HLT

RAR (RTR,

IAC, SWHA)

RAL (RTL,

IAC, SWHA)

OAS
CcML

CMA

Condition

Code

AC>0
AC=0
AC=0
AC<0
ACL0
AC=

SPA! SNA
SPA
SZA
SMA! SZA
SMA
SNA

NOTE

Level 1 skips (SNA, SZA, SMA) will occur if any
one of the combined tests is satisfied (an OR condition). Level 2 skips (SZL, SNA, SPA) will occur
only if all the combined tests occur (an AND condition). Combined rotates become a SWHA or an
IAC, depending on bit 7.

NO OPERATION
NO OPERATION
T

740000

]

TM1

NOP
15-0877

Mnemonic Name
Octal Code
Time

NOP
740000
1 cycle

Operation

The program delays for one cycle before the next instruction is

fetched.
COMPLEMENT ACCUMULATOR
COMPLEMENT ACCUMULATOR

740001

RTINS

CMA

15-0878

Mnemonic Name
Octal Code
Time

CMA

Operation

Each bit of the AC is set or cleared to the inverse of its current
state. The previous contents of the AC are lost.

Symbolic

740001
1 cycle

-AC to AC

6-12

COMPLEMENT

LINK

COMPLEMENT LINK

740002

ll|l||ll|ll|lllll

CML

15-0879

Mnemonic Name
Octal Code
Time
Operation

CML

740002
I cycle
The link is set or cleared to the inverse of its current state. Its
previous content is lost.

Symbolic

-LtoL

INCLUSIVE OR ACCUMULATOR SWITCHES
INCLUSIVE OR ACCUMULATOR SWITCHES
llllllfllll'll[ll

740004

Illllllllllllllll

OAS

15-0880

Mnemonic Name
Octal Code
Time

Operation

OAS
740004
1 cycle

The word set up by manual positioning of the DATA switches is

inclusive-ORed with the contents of the AC on a bit-by-bit
basis. The result is left in the AC. If corresponding, AC and
DATA switch bits are in the binary O state, the AC bit remains

Symbolic

0. If either or both ofthe corresponding bits are in the binary 1
state, the AC bit is set to 1. The previous contents of the AC are
lost. The switch settings are not affected.

AC OR DATA switch to AC

6-13

INCREMENT THE ACCUMULATOR
INCREMENT THE ACCUMULATOR
T

]

740030

llI]llIlllll

TR S

TN AN T

IAC

15-0881

Mnemonic Name
Octal Code
Time

IAC
740030
1 cycle

Operation

The contents of the Accumulator are incremented by one and

Symbolic

bit zero complements the Link.
AC + 1 to AC

the results placed in the Accumulator. When overflow occurs,

CLEAR THE LINK
CLEAR THE LINK

744000

N R

CLL
15-0882

Mnemonic Name
Octal Code
Time

Operation
Symbolic

CLL
744000
1 cycle

The content of the link is cleared to the binary O state.
Oto L

CLEAR THE ACCUMULATOR
CLEAR THE ACCUMULATOR

750000

CLA
15-0883

Mnemonic Name
Octal Code
Time

CLA
750000
1 cycle

Symbolic

contents are lost.
0 to AC

Operation

Each bit of the AC is cleared to the binary O state. The previous

6-14

HALT PROGRAM
HALT PROGRAM

740040

RN S

HLT
15-0884

Mnemonic Name
Octal Code
Time

Operation

HLT
740040
1 cycle

Program execution stops at completion of the current machine
cycle. The run indicator is turned off. The HLT instruction will
cause a trap to occur if executed while the XVM is in User mode
with relocation engaged.

Symbolic

0 to RUN flip-flop

SWAP HALVES OF THE ACCUMULATOR
SWAP HALVES OF THE ACCUMULATOR
TM

742030

SWHA

156-0885

Mnemonic Name
Octal Code
Time

SWHA
742030
1 cycle

Symbolic

The previous contents of the AC are lost.
ACo-g to AC9-17
ACoy-17t0 ACo-sg

Operation

This instruction places the contents of AC bits 0-8 into AC bits
9-17 and at the same time places AC bits 9-17 into AC bits 0-8.

6-15

SKIP ON NON-ZERO LINK
SKIP ON NON=-ZERO LINK

740400

SNL

15-0886

Mnemonic Name
Octal Code
Time
Operation

SNL
740400
1 cycle
Test the content of the Link. If the Link is in the binary 1 state,
the contents of the PC are incremented by one to skip the next
instruction. If the Link has a binary 0, the next instruction is
executed. The content of the Link is unchanged.
IfL=1 PC+1toPC

Symbolic

UNCONDITIONAL SKIP

UNCONDITIONAL SKIP
|

741000

]

SKP

15-0887

Mnemonic Name
Octal Code
Time
Operation

SKP
741000
1 cycle
The contents of the PC are incremented by one to cause an
unconditional skip of the next instruction.

Symbolic

PC+1 to PC

6-16

SKIP ON AC GREATER THAN ZERO (AC>0)

SKIP ON ACCUMULATOR GREATER THAN ZERO
T

741300

RN (N SN W

rr1rrr
T
o1

TN N

SN SN R

SAGZ

15-0888

‘Mnemonic Name

SPAISNA

Octal Code
Time

741300
1 cycle

Operation

Test the contents of the sign bit ACy of the data word in the AC
and also test that some bit in the AC (AC-i7) is non-zero. If
both conditions are true, then skip. The contents of the AC are
unchanged.

Symbolic

If ACo-17>0, PC + 1 to PC
SKIP ON POSITIVE ACCUMULATOR (AC>0)
SKIP ON POSITIVE ACCUMULATOR
IIIITIIIIIIIIIIII

741100

SPA

R
15-0889

Mnemonic Name
Octal Code
Time

Operation

Symbolic

SPA
741100
1 cycle

Test the contents of the sign bit, AC,, of the data word in the

AC. If the bit is in the binary O state, the quantity in the AC is
taken to be positive. Therefore, the contents of the PC are
incremented by one to skip the next instruction. If the bit is
found to be in the binary 1 state, the next instruction is executed. The contents of the AC are unchanged.

If ACo = 0, PC + 1 to PC

SKIP ON ZERO ACCUMULATOR (AC=0)
SKIP ON ZERO ACCUMULATOR
!

740200

]

[

]

TR T

SZA

15-0890

Mnemonic Name
Octal Code
Time
Operation

SZA
740200
1 cycle
Test the contents of the word in the AC. If all bits are binary Os,
the quantity is taken to be zero (2’s complement notation), and
the contents of the PC are incremented by one to skip the next
instruction. If any bit is in the binary 1 state, the next instruction is executed. The contents of the AC are unchanged.

Symbolic

If AC=0, PC + 1toPC
SKIP ON NON-ZERO ACCUMULATOR (AC is not equal to 0)
SKIP ON NON-ZERO ACCUMULATOR
1

741200

[

]

77717

SNA

15-0891

Mnemonic Name
Octal Code
Time

Operation

Symbolic

SNA
741200
1 cycle

Test the contents of the data word in the AC. If any bit is in the
binary 1 state, the quantity is taken to be unequal to zero (2’s
complement notation only), and the contents of the PC are
incremented by one to skip the next instruction. If all bits are
found to be in the O state, the quantity is considered to be zero
and the next instruction is executed. The contents of the AC are
unchanged.

If AC is not equal to 0, PC + 1 to PC

6-18

SKIP IF AC LESS THAN OR EQUAL TO ZERO (AC<0)
SKIP IF ACCUMULATOR LESS THEN OR EQUAL TO ZERO
T

740300

]

SALZ

15-0892

Mnemonic Name
Octal Code
Operation

SMAISZA
740300
Test ACy, the sign bit of the data word in the Accumulator.

Also test the entire ACo-,7 for all zeros. If either of these conditions is true, skip the next sequential instruction. The contents
of the AC are unchanged.

Symbolic

If ACo.17 = 0 or ACy is not equal to 0, PC + 1 to PC

SKIP ON MINUS ACCUMULATOR
ROTATE AC AND LINK LEFT

|
740100

NN S

|
0

|
1

TR NN OO SN A

i
0

TR N

|
0

SMA

15-0893

Mnemonic Name
Octal Code
Time

SMA
740100

Operation

Test the contents of the sign bit, AC,, of the data word in the

Symbolic

AC. If the bit is in the binary 1 state, the contents of the PC are
incremented by one to skip the next instruction. If AC, is found
to be in the O state, the next instruction is executed. The contents of the AC are unchanged.
If ACo =1, PC + 1 to PC

1 cycle

6-19

SKIP ON ZERO LINK
SKIP ON ZERO LINK
IIIIIIIIIIIIIIII

741400

R NN SN NN A

TR NN TN N

SZL

15-0894

Mnemonic Name
Octal Code
Time

SZL
741400
1 cycle

Operation

Test the contents of the Link. If the Link is in the binary O state,
the contents of the PC are incremented by one to skip the next
instruction. If the Link has a binary 1, the next instruction is
executed. The contents of the Link are unchanged.
IfL=0,PC+ 1toPC

Symbolic

ROTATE AC AND LINK LEFT
SKIP ON MINUS ACCUMULATOR

740010

RAL

15-0895

Mnemonic Name
Octal Code
Time
Operation

Symbolic

RAL
740010
1 cycle

The contents of the AC and the Link are rotated one bit position to the left with AC, entering the Link and the Link entering
AC|7.
ACj to ACj-1; i=4,17
ACoto L
L to AC|7.

6-20

ROTATE AC AND LINK RIGHT
ROTATE AC AND LINK RIGHT
L

740020

RAR

15-0896

Mnemonic Name
Octal Code
Time

Operation

RAR
740020
1 cycle

The contents of the AC and the Link are rotated one bit position to the right with AC,.;; entering the Link and the Link

Symbolic

~ entering AC,.

ACj to ACj+1; i=¢,16
ACj;to L+
L to AG

ROTATE AC AND LINK TWO LEFT
ROTATE AC AND LINK TWO LEFT

742010

]

KN SN WO N

SR SN WA N

RTL

15-0897

Mnemonic Name
Octal Code
Time

Operation

RTL
742010
1 cycle

tions to the left with ACo entering AC,7, AC, entering the Link,
and the Link entering ACjs.

Symbolic

The contents of the AC and the Link are rotated two bit posiACjto ACj-2;1=5,17
L to ACs

ACoto ACy7 |
AC] to L

6-21

ROTATE AC AND LINK TWO RIGHT

ROTATE AC AND LINK TWO RIGHT
|

742020

]

RTR

15-0898

Mnemonic Name
Octal Code
Time

Operation

RTR
742020
1 cycle

The contents of the AC and the Link are rotated two bit positions to the right with the Link entering AC;, AC,; entering
ACy, and AC¢ entering the Link.

Symbolic

ACj to ACi+2; i=o0,15

L to AC,
ACi1to AG
ACisto L

2’S COMPLEMENT ACCUMULATOR
2'S

740031

COMPLEMENT ACCUMULATOR

TCA

15-0899

Mnemonic Name
Octal Code
Time
Operation

Symbolic

TCA
740031
1 cycle
A microcoded instruction combines the complement of the AC
and increments the AC, thereby performing a 2’s complement
operation on the contents of the AC and placing the result in the
AC. The previous contents of the AC are lost.
-AC + 1 to AC

6-22

SET THE LINK
SET THE LINK

744002

STL

15-0900

Mnemonic Name
Octal Code
Time

STL
744002
1 cycle

A microcoded instruction equivalent to CLL+CML. The Link
is first cleared to contain a binary 0; it is then complemented to

Operation

contain a binary 1.
Symbolic

lto L

CLEAR LINK, THEN ROTATE AC AND L LEFT

744010

RCL

15-0901

Mnemonic Name
Octal Code
Time
Operation

RCL
744010
1 cycle

Symbolic

AC] to ACl-l, i=1,|7
ACo to L
0 to AC17

A microcoded instruction equivalent to CLL + RAL. The Link
is first cleared to the binary O state: then the contents of the AC
and the Link are rotated one bit position to the left.

6-23

CLEAR LINK, THEN ROTATE AC AND L RIGHT

744020

RCR

15-0902

Mnemonic Name
Octal Code
Time
Operation

Symbolic

RCR

744020
1 cycle

A microcoded instruction equivalent to CLL + RAR. The Link
is first cleared to the binary 0 state; then the contents of the AC
and the Link are rotated one bit position to the right.
ACj to ACj+1; i=¢,i6
AC17 toL
0to AG

CLEAR AND COMPLEMENT ACCUMULATOR

750001

]

cLC

15-0903

Mnemonic Name

CLC

Octal Code

750001

Time

1 cycle

Operation

A microcoded instruction equivalent to CLA + CMA. Each bit
of the AC is cleared to the binary O state. Then each bit is set to

Symbolic

the binary 1 state. The previous contents of the AC are lost.

777777 to AC

6-24

LOAD AC FROM ACCUMULATOR SWITCHES
LOAD AC FROM ACCUMULATOR SWITCHES
1

750004

SR N

LAS
15-0904

Mnemonic Name
Octal Code
Time

LAS
750004
1 cycle

Operation

A microcoded instruction equivalent to CLA + OAS. Each bit
of the AC is cleared to the binary 0 state. Then the word set up
by manual positioning of the DATA switches is entered in the
AC. The previous contents of the AC are lost. The switch set“tings are not affected.

Symbolic

DSW to AC

GET THE LINK

750010

]

GLK

15-0905

Mnemonic Name
Octal Code
Time
Operation

Symbolic

GLK
750010
1 cycle
'
A microcoded instruction equivalent to CLA + RAL. Each bit

of the AC is cleared to the binary O state. Then the contents of
the AC and the Link are rotated one bit position left with the
Link contents entering AC,;. The previous contents of the AC
are lost.
L to ACyy
0to ACy6
OtoL

6-25

LOAD ACWITH n
LOAD AC WITH "n"

760000

ll|ll||l|ll|lllll

LAW
15-0906

Mnemonic Name

LAW

Octal Code

760000 + n (n = 13-bit number)

Operation

A single-cycle instruction that loads itself into the AC for the

.
Symbolic

always be loaded with ones.
MI to AC

Time

1 cycle

purpose of generating a negative number, n, of the range of
0<n<17777;. Following the fetch, the computer enters the contents of the MI (the LAW instruction word) in the AC. The
previous contents of the AC are lost. The first five AC bits will

Index Instructions

The index instructions enable the programmer to transfer information between the Accumulator, Limit register, and Index register, clear the Limit register and Index register, add a number contained in the
instruction itself (£256) to the Accumulator, Limit register, or Index register, and test to determine if
the Index register is greater than or equal to the Limit register.

All index instructions require two central processor cycles, but only one memory cycle, thus allowing
the central processor to perform operations at the same time as the I/O processor.

PLACE ACCUMULATOR IN INDEX REGISTER
PLACE ACCUMULATOR IN INDEX REGISTER
1

721000

717

1||||||1|||||1|||

PAX
15-0907

Mnemonic Name
Octal Code

PAX
721000

Operation

The contents of the Accumulator are transferred to the Index

Symbolic

AC to XR

Time

2 cycles (1 memory cycle)

6-26

PLACE ACCUMULATOR IN LIMIT REGISTER
PLACE ACCUMULATOR IN LIMIT REGISTER

722000

PAL
15-0908

Mnemonic Name
Octal Code
Time

PAL
722000
2 cycles (1 memory cycle)

Operation

The contents of the Accumulator are transferred to the Limit
register. The contents of the Accumulator remain unchanged.

Symbolic

AC to LR

PLACE INDEX REGISTER IN ACCUMULATOR
PLACE INDEX REGISTER IN ACCUMULATOR
T
724000

r
7

17177

PXA

15-0909

Mnemonic Name
Octal Code
Time

PXA
724000
2 cycles (1 memory cycle)

Symbolic

XR to AC

Operation

The contents of the Index register are transferred to the Accumulator. The contents of the Index register remain unchanged.

PLACE INDEX REGISTER IN LIMIT REGISTER
PLACE INDEX REGISTER IN LIMIT REGISTER
J

726000

BTN A

PXL
15-0910

Mnemonic Name
Octal Code
Time

PXL
726000
2 cycles (1 memory cycle)

Symbolic

Operation

The contents of the Index register are transferred to the Limit

6-27

PLACE LIMIT REGISTER IN ACCUMULATOR
PLACE LIMIT REGISTER IN ACCUMULATOR
T

730000

]

PLA

15-0911

Mnemonic Name
Octal Code
Time
Operation

Symbolic

PLA
730000
2 cycles (1 memory cycle)
The contents of the Limit register are transferred to the Accumulator. The contents of the Limit register remain unchanged.

LR to AC

PLACE LIMIT REGISTER IN INDEX REGISTER
PLACE LIMIT REGISTER IN INDEX REGISTER
1
731000

L
7

PLX

B
15-0912

Mnemonic Name
Octal Code
Time
Operation

Symbolic

PLX
731000
2 cycles (1 memory cycle)
‘The contents of the Limit register are transferred to the Index
register. The contents of the Limit register remain unchanged.

LR to XR

6-28

ADD n TO INDEX REGISTER AND SKIP IF EQUAL TO

OR GREATER THAN THE LIMIT REGISTER

ADD n TO INDEX REGISTER AND SKIP IF EQUAL TO OR GREATER

THAN THE LIMIT REGISTER
725
+ n

AXS n

15-0913

Mnemonic Name
Octal Code
Time

AXS n
725000 + n (n = 9 bits)
2 cycles (1 memory cycle)
n, a signed 9-bit (8 bits plus sign) 2’s complement integer is
added to the contents of the Index register, and the result is
placed in the Index register. If the sum is greater than or equal
to the contents of the Limit register, then the program counter is
incremented by 1 and thus the next instruction is skipped.
XR + N to XR
If XR=2LR, PC + 1 to PC

Operation

Symbolic

ADD TO INDEX REGISTER
ADD TO INDEX REGISTER

737 +n

AXR +n

15-0914

Mnemonic Name
Octal Code
Time

Operation

Sym bolick

AXR + n
,
,
737000 + n (n = 9 bits)
2 cycles (1 memory.cycle)
n, a signed 9-bit (8 bits plus sign) 2’s complement integer is
added to the content of the Index register, and the result is
placed in the Index register.
XR + N to XR

6-29

ADD n TO ACCUMULATOR
ADD n TO ACCUMULATOR
AAC +n

723+ n

15-0915

AAC + n

Mnemonic Name
Octal Code

723000 + n (n = 9 bits)
2 cycles (1 memory cycle)

Time

n, a signed 9-bit (8 bits plus sign) 2’s complement binary number, is added to the content of the Accumulator, and the result is
placed into the Accumulator. The Link will not be com-

Operation

plemented when overflow occurs.

AC + N to AC

Symbolic

CLEAR THE INDEX REGISTER
CLEAR THE INDEX REGISTER

|||||]|||||||||||

735000!

|||||||||||||||||

CLX
15-0916

Mnemonic Name
Octal Code

CLX
735000

Operation

The content of the Index register is replaced with all 0s. Former

Symbolic

0to XR

2 cycles (1 memory cycle)

Time

content is lost.

CLEAR THE LIMIT REGISTER
CLEAR THE LIMIT REGISTER

736000

|||||||||l||1||1|

CLLR
15-0917

Mnemonic Name
Octal Code

CLLR
736000

Operation

The content of the limit register is replaced with all Os. The for-

Time

Symbolic

2 cycles (1 memory cycle)
mer content is lost.

0to LR

6-30

Input/Output Transfer Instructions

Input/Output transfer (IOT) instructions initiate transmission of signals via the I/O bus to control
peripheral devices, sense their status, and effect information transfers between them and the central
processor. XVM IOT instructions contain the following information (Figure 6-5).
1.

An operation code of 70s.

An 8-bit device selection code to differentiate between up to 256 peripheral devices (selection
logic in a device’s 1/O bus interface responds only to its preassigned code). In normal practice, bits 6 through 11 perform the primary device differentiation between up to 64 devices
with bits 12 and 13 coded to select an operational mode or subdevice. A number of these
device codes are hardwired into the processor and cannot be used to control peripheral
devices.

A command code (bits 14 through 17) capable of being microprogrammed to clear the AC
and issue up to three pulses via the I/O bus.

70g

SELECTION

1011

0
0

0
!

0
2

0
3

CLEAR
AC

\f_—_dk—__“v"'A_W

SUB-

DEVICE

OPERATION CODE

0
4

0
5

|12

|13 [ 14|

o
0

0
!

GENERATE

AN IOP 2
PULSE

f_‘k—fi
15|16

——

GENERATE

AN IOP 4
PULSE

|17
——

GENERATE

AN IOP!
PULSE

15-0203

Figure 6-5

1OT Instruction Word Format

The two machine cycles required to execute an IOT instruction consists of decoding of the IOT from
the central processor’s memory input buffer, synchronization of the central and I/O processors,
issuing three sequential cycles of 1 us each to ensure IOP pulses at event times 1, 2, and 4, and finally,
the fetch of the next instruction to be executed. Bit 14 can be programmed to clear the Accumulator at
event time 1 of the IOT instruction. Bits 15-17 can be microprogrammed in any manner to produce a
pulse on the I/O bus for each bit set. Bit 17 causes an IOP 1 pulse, or the first pulse generated, and is
normally used for testing the Device Status flags. Bit 16 generates an IOP 2 pulse, the second pulse,
and can be used in'transmitting to or from a device to the processors. On “In” transfers, data is ORed
from the 1/O bus into the Accumulator; therefore, bit 14, clear the Accumulator, is typically used
when loading the accumulator from a device. Bit 15 produces IOP 4 pulse, the third pulse, and is used
for control and transfer of data from the Accumulator to the device. A summary of IOP pulses is as
follows (Figure 6-6):

IOPI is normally used in an I/O skip instruction to test a Device flag; however, it can be
used as a command pulse or a load of a device. It cannot be used to initiate a “read from” a
device.

IOP2 is usually used to transfer data from the device to the computer, or to clear a device

1OP4 is usually used to transfer data from the computer to the device; it cannot be used to

information register; it cannot be used to determine a *“‘skip” condition.
determine a “‘skip” condition or to initiate a read from a device.

6-31

0O~-60NS MAX.—|

CP RUN

|
-»|

EXECUTE

1oTREQ.

10T

10T SYNC

[

|e-60NS

= le—160NS MAX.

800 Ns——l\ pe-

[

____ |¥

—s|

J
S,|

fe—250 NS

)

| -

fe- 1 usEC

-~ \

10P 1

|
|

10P 2

<=1 . SEC

-] \ [«——— S00NS /
1]

AC ON BUS

|
|

|l
10T DONE

——|\,<-)o TO 1 SEC

10P 4

[

1
I5-0176

Figure 6-6

10T Instruction Timing

Programming Note
Execution of an IOT instruction and the next
instruction in sequence cannot be interrupted; i.e.,
the XVM does not grant an interrupt request untii
the instruction following an IOT (and which is not an
IO0T itself) has completed its function.
XVM IOTs

NOTE
An attempt to execute an IOT when the XVM System is in User mode with relocation engaged, will
cause a trap unless the IOT ENABLE FUNCTION
has been set in the memory processor,

6-32

IORS

Read Flags

5
|

]

6
]

‘4]

TN T

IOT Code

15
I

L] |—|

IOP'S

Device Select

SN NN N

Subdevice Select ——

Clear AC
16-0944

The IORS read status instruction causes the transfer of an 18-bit system status word from the I/O bus
to the Accumulator. During this instruction, each of the internal and external system devices gates its
status bit onto preassigned data lines. The I/O processor transfers these bits to the Accumulator.
Figure 6-7 shows the word/status/bit assignment.

PROGRAM
INTERRUPT

TAPE
PUNCH

FLAG*

~—

FLAG*

—

TAPE
READER

FLAGH

—

TAPE
READER
FLAG*

REAL
TIME
CLOCK
OVERFLOW

TERMINAL
PRINTER

—

| 4

DEC
TAPE

NO TAPEX#*

—

|18

r—H_
(9

LIGHT
PEN

REALTIME

TAPE
PUNCH

FLAG*

CLOCK

NO PUNCH

DISPLAY

ENABLED

LINE

PACK*

PRINTER*

|12

|13 ] 14|15

—*

(10|11t

TERMINAL
KEYBOARD

FLAG*

DISK

FLAG *t

MAG TAPE*t

~—

(16

|17

DEC
DISK

RESERVED FOR
SPECIAL USERS

FLAG*

DEVICES

* WILL CAUSE A PROGRAM INTERRUPT
*t INCLUSIVE
#1t INCLUSIVE

OR OF TRANSFER
OR

OF MTF AND

COMPLETION

AND ERROR

FLAGS

** CAUSES A PROGRAM INTERRUPT THROUGH THE READER FLAG
15- 0202

Figure 6-7

IORS Word Status Bit Assignments

CAF

Clear all Flags

5
|

)

10T Code

6
'

1
|

NN N

15
I

]

NN TR TR NN NN TN NN W

Device Select
Subdevice Select

]

\__l l\l

17
|

IOP’‘S
Clear AC
15-0945

The CAF instruction gates a pulse to the I/O bus to initialize (clear) all flags of any device that can call
for interrupt service. Customer-installed equipment should make use of this pulse to reset flags and

registers that must be cleared for system initiation. This instruction should not be used in an operating
system controlled environment because it will interrupt on-going activities.

6-33

Turn Interrupt OFF
15

10T Code

Device Select

I___l E

IOP’S
Clear AC

Subdevice Select —

15-0946

The IOF input/output instruction turns off the program interrupt facility of the exchange.
Turn Interrupt ON
15

10T Code

Device Select

I__l

10P’'S
Clear AC

Subdevice Select

15-0947

The ION program interrupt facility is enabled.

Enable Bank Addressing

{OT Code

Device Select

L__l

Subdevice Select ——

10P‘S
Clear AC
15-0948

The Index register is disabled and the sixth bit (bit 5), normally used to indicate an indexed operation,
is gated to the memory address field, permitting direct addressing of 8192 words of memory.

6-34

SBA

Skip if in Bank Addrt_assing

11
!

{

]

10T Code

T
7

15
I

Device Select

10P‘S

Subdevice Select

]
1

17
|

Clear AC
15-0949

If in Bank Addressing mode, the next instruction is skipped.
Disable Bank Addressing
15
I

L
IOT Code

17
I

2
]

]

Device Select

Clear AC

Subdevice Select

15-0950

Bank Address mode is disabled, and the XVM operates with indexing and addresses 4096 words of
memory directly.
Test Terminal and Skip
15

15-0951

Test if console terminal is connected to the XVM. Skip the next instruction if it is.
SKP15

Skip if PDP-15

15-0962

Skip the next instruction if the processor is a PDP-15 or XVM.

6-35

Skip if PC15

15-0953

Skip the next instruction if a PC15 is connected to the system.
Console Device Keyboard
Mnemonic
Code
KSF
700301

KRB

700312

KRS

700332

Console Device Printer
Mnemonic
TSF

Description

Skip on Keyboard Flag - Tests the console terminal keyboard flag and causes the next instruction
to be skipped if the flag is set, indicating that the
keyboard control has assembled a character from
the terminal device.
Read Keyboard Buffer - This IOT clears the AC
and then reads the contents of the keyboard buffer
into AC bits 10-17, and clears the keyboard flag.
Keyboard Reader Select - This IOT clears the AC,
reads the contents of the keyboard buffer into AC
bits 10-17, and enables the keyboard reader to
advance another character. Reading from the keyboard reader is done in full duplex mode (no character echo). This IOT can also be used to read, full
duplex, from terminal device keyboard.

Code
700401

Description
Skip on Console Printer Flag — Tests the status of
the printer flag to determine if the last character
has been printed. If the flag is set, the next instruction will be skipped.

TCF

700402

Clear Console Printer Flag — Clears the Printer flag
which had been set at the completion of the pre-

TLS

700406

vious character.

6.2

Load and Select Console Printer — Clears the Printer flag, loads the printer buffer from AC bits 10-17,
and initiates printing of the character. The flag is
set when printing is completed.

EXTENDED INSTRUCTION SET

Extended Arithmetic Element

The extended arithmetic element (EAE) and its instructions, identified by an operation code of 64s,
perform high-speed data manipulation and multiply-divide operations as specified by microprogramming of individual instructions. Figures 6-8 through 6-12 illustrate the microinstruction capabilities for register setup, data shift, normalize, multiply, and divide.

6-36

OPERATION
CODE 64
SPECIFYING EAE

COMPLEMENTS LOADS
THE AC
THE MQ

EAE COMMAND Og

AT TIME

FOR SETUP

L AT TIME
STATE A

|17

15|

|13 [ 14|

—

——

SHIFTS
ACOO INTO

OF AC AND
THE MQ AT
TIME STATE C

)

—A

|12

|10

UNUSED IN
SETUP

/—‘H

r"*'fl

3 | 4

CLEARS MQ
AT TIME
STATE B

LOADS THE AC
WITH THE OR

CLEARS AC
AT TIME
STATE C

STATE B

:
LOADS THE MQ WITH THE
OR OF THE CONTENT OF | wiEN BIT 6 1S
THE AC AND THE MQ AT

WITH THE

OR OF THE

CONTENT OF

THE AC AND
THE SC AT
TIME STAT

A1 ANDBIT7 1S

TIME STATE B

A O, THE NUMBER IN

D
SHIFTS ACOO INTO EAE AC | THE AC 1S CHANSETO

SIGN FLIP-FLOP AT
TIME STATE A

15-0189

EAE Setup Microinstructions

Figure 6-8

CAN BE USED

OPERATION

CODE 64

SPECIFYING EAE

STEP COUNTER PRE-SETTING

(SET TO THE NUMBER OF

SETUP INSTRUCTIONS

)

IN MICROPROGRAMMING

SAME FUNCTIONS AS FOR
A

3 | 4

STATE

(10|

{12

(13 [ 14|15 | 16

|17

SHIFTS
AchToT'lr‘l‘MTEo

\_V'—J

BINARY POSITIONS TO BE SHIFTED )

EAE COMMAND
58=LONG RIGHT SHIFT

6g=LONG LEFT SHIFT

7g=AC LEFT SHIFT

SIGNED

OPERATIONS
15-0180

EAE Shift Microinstructions

Figure 6-9

L
COMMANDS

SPECIFELNG EAE

N\
o

2
|4

H_/

SHIFTS
ACOO INTO

L AT TIME
STATE A FOR
SIGNED
OPERATIONS

6 | 7

STEP COUNTER PRE-SETTING
(USUALLY 44g FOR NORMALIZE)

)
8

A—

| 9

|10

(12

{13

|14

|15 | 16 | 17

EAE COMMAND
4g FOR NORMALIZE

15-0191

Figure 6-10

EAE Normalize Microinstructions

6-37

SHIFTS ACOO INTO EAE AC
SIGN FLIP-FLOP AT TIME

STATE A
LOADS THE MQ WITH THE OR
OF THE CONTENT OF THE AC
AND THE MQ AT TIME

STATE B

OPERATION
CODE 64
SPECIFYING EAE

EAE COMMAND
g FOR MULTIPLY

| 7|8

(10|11

|12

W__J

BIT 4 1S A
OANDBIT S

|14]|15]

16|17

CLEARS AC
AT TIME
STATE C

IS A1t SO
THAT LINK IS
NOT DiISTURBED
AND MQ IS CLEARED
AT TIME STATE B

|13

STEP COUNTER PRE-SETTING
(USUALLY 22g FOR MULTIPLY)

15-0192

Figure 6-11

EAE Multiplication Microinstructions

USED WITH
INTEGER

USED WITH

s
0o

LOAD THE
MQ WITH THE

STATE B

CODE 64

DIVIDE TO

DIVIDE TO
CLEAR THE

MQ AT TIME

OPERATION

SPECIFYING EAE

INTEGER

3 | 4

516
-

EAE C’QMM&ND

THE AC AT

—

—*

CONTENT OF

TIME STATE B

USED WITH

SO THAT
LINK IS
NOT DISTURBED
EXCEPT FOR
OVERFLOW

DIVISION
TO SET
THE SIGN
OF THE
DIVIDEND

DIVIDE TO
CLEAR THE
AC AT
TIME
STATE C

SIGNED

ACOQ INTO
THE EAE

(1011

UNUSED

IN DIVIDE

3g FOR DIVIDE

INTEGER

(12

|13

141516

|17
-/

STEP COUNTER PRE-SETTING
(USUALLY 238 FOR DIVIDE)

SIGN FLIP-FLOP
15-0193

Figure 6-12

EAE Division Microinstructions

The time required to execute an EAE instruction is a function of the operation and/or the shift, or step
count specified by programming. In general, the following considerations apply to the different types
of EAE operations:
1.

All setup instructions require 1.325 microseconds.

Long register shift instructions require a time equal to 2.915 microseconds plus 0.133 microseconds per “n-1" bit-position shifts. This count is specified by the addition of n(octal) to
the instruction code. For example, the input of the symbolic instruction LLS + 14 to the
XVM assembler would result in an instruction code that specified a long left shift of the AC
and MQ (taken as a 36-bit register) 12,0-bit positions to the left. This instruction would
require 4.77 microseconds.

The ASL and ALSS instructions, respectively, AC left shift and AC left shift signed, also
require the specification of *“n.”

6-38

The normalizing instructions, NORM and NORMS, require an execution time equal to 2.9
microseconds plus 0.133 microseconds per number of bit positions shifted to normalize
(AC, is not equal to AC,) quantity. These instructions are microprogrammed to set the 6-bit
step count to 444(36,0). Hence, -xx+nx (the step count is entered in 2’s complement notatior
at execution) equals the biased scale factor of a normalized quantity.

Multiply instructions require a time equal to 7.4 microseconds. Multiply instructions are
microprogrammed to set the step count to 224(18,0), representing the multiplication of one
18-bit quantity (sign bit and 17 magnitude bits for signed quantities) by another to produce a
36-bit product. Where such precision is not required, the microprogrammed step count can
be decreased by subtracting the appropriate number “n” (octal) from the instruction code.
The product is always left-justified in the AC, MQ. If “-n” is appended to a multiply instruction, the “n”’ low-order bits in the long register are meaningless.
Divide instructions require a time equal to 7.65 microseconds. Divide instructions are
microprogrammed to set count to 233(1910), representing division of a 36-bit dividend
(actual or implied) by an 18-bit divisor. Where such precision is not required, the microprogrammed step count can be decreased by subtracting the appropriate number *“n”’ (octal
from the instruction code). For example, the symbolic instruction DIV-12 would result in a
right-justified quotient with the most significant bit in MQs. The execution time is decreased
in accordance with the decrease in the step count.

EAE Microinstructions
Figure 6-1 3 and Tables 6-1 and 6-2 describe the EAE instructions and illustrate the microinstructions

of the EAE instructions. If an existing instruction is not satisfactory, the programmer can combine the
appropriate microinstructions to achieve the required resuit.

B BUS

5US

»|

CBUS—>ABUS

2 BUS

——-{ C BUS—=A BUS

MEMORY
INPUT

LINK

STEP

ACCUMULATOR

COUNTER

EAE

SIGN

MULTIPLIER

QUOTIENT

NO SHIFT
OR
SHIFT LOGIC

MEM IN

L |

|Je—

NO SHIFT

SHIFT LOGIC
15-0177

Figure 6-13

EAE Simplified Block Diagram

6-39

Table 6-1
EAE Microinstructions
EAE TIME

4 TR

|——~—{&|

[*52:

l COMMON EVENTS i

i bt (’3_'.

EAE OP CODE
(64

NOTED)

AC —=

eae

BB »o

Ogg“;M:\ND

011 Divide

8?8 Multiply

etup

cRIS
AC—C

CBUS

CBUS —= A BUS

[

154

EAE COMMAND # 000

LOAD STEP COUNT

100 Normalize

101 Long Right

111 AC Left

110 Long Left

I
| Mo —caus

p--4

o
o

o [ J1>
27

|
I
I

z
'
2

oz
V&
=

CBUS —» ABUS
LD MQ

. MQ —MQ

@
m

(" o4[ ] O

o
20

5l
X}

(2]

AC — CBUS

CBUS — A BUS
LD AC

[Be

[»]

‘

>
&

2
:
5<
0

» o >

’%‘

g 8

S|
=

1348
5 (3

o4l

b g

w
o

o ! No OPERATION
1

| (EAE COMMAND
# 000)

E,F | ALL SHIFT,MULTIPLY AND DIVIDE

| OPERATIONS

15-0422

6-40

Table 6-2
EAE Microinstructions
Bit Positions

Binary Code

Function

Enter the content of ACy in the Link for signed
operations.
Clear the MQ.

Read the content of ACO into the EAE AC Sign

Take the absolute value of the AC. Takes place
after the content of ACy is read into the EAE AC
Sign register.

Inclusive OR the AC with the MQ and read into
MQ.

Clear the AC.

8
9,10,11

000

Setup. Accompanies code in bits 15, 16, and 17.

9,10,11

001

Multiply. Causes the number in the MQ to be multiplied by the number in the memory location following this instruction. If the EAE AC Sign
register is 1, the MQ is complemented prior to multiplication. The exclusive OR of the EAE AC sign
and the Link is entered in the EAE Sign register.
The product is in the AC and MQ, with the lowest
order bit in MQ bit 17. At completion, the Link is
cleared and if the EAE sign is a 1, the AC and MQ
are complemented.

9,10,11

010

Unused operation code.

9,10,11

011

Divide. Causes the 36-bit number in the AC and
MQ to be divided by the 18-bit number in the
Memory register following the instruction. If the
EAE AC sign is 1, the MQ is complemented prior
to starting the division. The exclusive OR of AC,
and the Link is placed in the EAE Sign register.
The AC portion of the dividend must be less than
the divisor or divide overflow occurs. In such cases,
the Link is set, and divide does not occur. Otherwise, the Link is cleared. At completion of this
instruction, if the EAE sign was a 1, the MQ is
complemented. Thus, the remainder has the sign of
the dividend.

6-41

Table 6-2 (Cont)
EAE Microinstructions

Bit Positions

Binary Code

Function

9,10,11

101

Long right shift. Causes the AC and MQ to be
shifted right together as a 36-bit register the number of times specified in the instruction. On each
step, the Link fills AC bit 0, AC bit 17 fills MQ bit
0, and MQ bit 17 is lost. The Link remains
unchanged.

9,10,11

110

Long left shift. Causes the AC and MQ to be
shifted left together, the number of times specified
in the instruction. On each step, MQ bit 17 is filled
by the Link; the Link remains unchanged. MQ bit
0 fills ACbit 17, and AC bit 0 is lost.

9,10,11

100

Normalize. Causes the AC and MQ to be shifted
left together, until the step count is equaled or AC
bit 0 is not equal to AC bit 1. MQ bit 17 is filled by
the Link; the Link is not changed. The step count
of this instruction is normally 44 (octal). When the
step counter is read into the AC, it contains the
number of shifts minus the initial shift count as a
2’s complement 6-bit number.

9,10,11

111

Accumulator left shift. Causes the AC to be shifted
left the number of times specified in the shift count.
AC bit 17 is filled by the Link, but the Link is
unchanged.

12-17

Specify the step count for all EAE commands (911) except the setup command.

The setup command only, causes the MQ to be
complemented.

The setup command only, causes the MQ to be
inclusively ORed with the AC and the result placed
in AC.

The setup command only, causes the AC to be
inclusively ORed with the SC and the results
placed on AC bits 12-17.

6-42

BASIC EAE INSTRUCTION
BASIC EAE INSTRUCTION

640000

+n
EAE

15-0018

EAE + n

Mnemonic Name
Octal Code
Operation

640000

The addition of n (octal) to the mnemonic converts the basic
instruction into a microcoded instruction to accomplish a setup,
shift, or arithmetic operation not already in the instruction
repertoire. Refer to Table 6-1 for descriptions of the functional
use of the individual bits of an EAE instruction. The sole
restriction for the development of n is that the microcoded operations must not occur during the same time state, if they logically conflict.
No operation.

Symbolic

INCLUSIVE OR SC WITH AC
INCLUSIVE OR SC WITH AC

640001

REE U

WO S

TR T

0SsC
15-0919

Mnemonic Name
Octal Code

OSC
640001

Symbolic

tents of the step counter (SC) on a bit-by-bit basis. The result is
left in ACs-17. If corresponding SC and AC bits are in the binary 1 state, the AC bit is set to 1. The previous contents of the AC
are lost. The contents of the SC are unchanged.
SC OR AC to AC

Operation

The contents of the AC are inclusively ORed with the 6-bit con-

6-43

INCLUSIVE OR MQ WITH AC
INCLUSIVE OR MQ WITH AC

640002

oma
15-0920

Mnemonic Name
Octal Code

Operation

OMQ

640002

The contents of the MQ are inclusively ORed with the contents
of the AC on a bit-by-bit basis. The result is left in the AC. If
corresponding MQ and AC bits are in the binary O state, the AC
bit is cleared to 0. If either of the corresponding bits is in the
binary 1 state, the AC bit is set to 1. The previous contents of
the AC are lost. The contents of the MQ are unchanged.

Symbolic

MQ OR AC to AC

COMPLEMENT MQ
COMPLEMENT MQ

640004

CcMQ

15-0921

Mnemonic Name

Octal Code
Operation

CMQ
640004
Each bit of the MQ is set or cleared to the inverse of its current
state. The previous contents of the MQ are lost.

Symbolic

MQ to MQ
LOAD AC FROM SC
LOAD AC FROM SC

641001

LACS

15-0922

Mnemonic Name
Octal Code
Operation

Symbolic

LACS
641001

This microcoded instruction clears each bit of the AC to 0 and

then enters the contents of the SC in AC,,.;7. The previous contents of the AC are lost. The contents of the SC are unchanged.
SC to AC

6-44

LOAD AC FROM MQ
LOAD AC FROM MQ

641002

LACQ

15-0923

Mnemonic Name
Octal Code

Operation

LACQ
641002

This microcoded instruction clears each bit of the AC to 0 and

then enters the contents of the MQ in the AC. The previous
contents of the AC are lost. The contents of the MQ are
unchanged.

Symbolic

MQ to AC
LOAD AC WITH ABSOLUTE VALUE TO AC
LOAD AC WITH ABSOLUTE VALUE TO AC

644000

ABS

15-0924

Mnemonic Name
Octal Code

ABS
644000

Symbolic

If ACo = 1,-AC to AC

Operation

A microcoded instruction which complements the contents of
the AC (I’s complement notation), if the content of ACy is 1.

CLEAR MQ

CLEAR MQ
1

650000

]

CcLQ
15-0925

Mnemonic Name
Octal Code

CLQ
650000

Operation

Each bit of the MQ is cleared to 0. The previous contents of the

Symbolic

0 to MQ

MQ are lost.

6-45

LOAD MQ
LOAD MQ
T

652000

RN T

SR N

rri

)}

TR S

o7’

LMma

15-0926

Mnemonic Name
Octal Code

LMQ
652000

Operation

A microcoded instruction which clears each bit of the MQ to 0
and then enters the contents of the AC in the

MQ, The previous

contents of the MQ are lost. The contents of the AC are
unchanged.

Symbolic

AC to MQ
GET SIGN AND MAGNITUDE OF AC

GET SIGN AND MAGNITUDE OF AC

T
664000

]

1]
4

NN SRS NS NS NN N

1
0

NN S

SN S

GSM

15-0927

Mnemonic Name
Octal Code

Operation

GSM
664000

A microcoded instruction which enters the contents of the ACy
in the Link and then complements the contents of the AC (1’s
complement notation), if ACy is a 1. The previous conterit of the
Link is lost.

Symbolic

ACoto L
If ACo = 1, -AC to AC

6-46

EAE Shifting Instructions
NORMALIZE

NORMALIZE
_

640444

NORM
15-0928

Mnemonic Name
Octal Code

Operation

NORM
640444

The contents of the AC and the MQ are shifted left (i.e., leading
zeros are shifted out) with the AC and MQ functioning as a
serial 36-bit register until the content of the AC, does not agree
with the content of AC,, i.e., the bits differ in their binary states,
or the contents of the step counter reach zero.

This 6-bit counter is initialized to the 2’s complement of
444(36,0steps). The contents of the six low-order bits of the
NORM instruction word specify the step count. For each shift
step, the contents of MQ, enter AC,; and the contents shifted
out of ACy are lost. The content of the Link, usually initialized
to zero, enters MQ,; to replace the contents of vacated bits. If
shifting halts because AC, does not equal AC;, the contents of
the step counter reflect the number of steps executed to reach
the condition. The counter’s contents (2’s complement of the
step count plus the steps executed) are accessible through use of
the OSC or LACS instruction.
|
Two free instructions follow the execution of the NORM
instruction. A PI or API break cannot occur until the second
instruction following the NORM instruction is completed.

6-47

Graphic

MULTIPLIER

ACCUMUL ATOR }e— QUOTIEN"ll‘ eaisTER [

x_oIR

STOP

SC=0

LINK

SHIFTS

}—»

15-0194

NORMALIZE, SIGNED
NORMALIZE, SIGNED
1

660444

]

NORMS

15-0929

Mnemonic Name
Octal Code

Operation

NORMS
660444

The contents of AC, enter the Link. Then, the contents of the
AC and the MQ are shifted left (i.e., leading zeros are shifted

out) with the AC and MQ functioning as a serial 36-bit register
until the contents of the ACy do not agree with the contents of
AC,, i.e., the bits differ in their binary states, or the contents of
the step counter reach zero.
This counter is initialized to the 2’s complement of 445(36;
steps). The contents of the six low-order bits of the NORMS
instruction word specify the step count. For each shift step, the
content of MQo enters AC,; and the contents shifted out of AC,
are lost. The content of the Link enters MQ,; to replace the
contents of vacated bits. If shifting halts because AC, does not
equal AC,, the contents of the step counter reflect the number
of steps executed to reach the condition. The counter’s contents
(2’s complement of the step count plus the steps executed) are
accessible through use of the OSC or LACS instruction. Two
free instructions follow the execution of the NORMS instruction. A PI or API break cannot occur until the second instruction following the NORMS instruction is completed.

6-48

Graphic

SETUP
ACo

LINK

EXECUTION

ACCUMULATOR
XOR
=

MULTIPLIER

L INK

QUOTIENT REGISTER

STOP

SC=0

SHIFTS

|—»

15-0195

Programming Note
The EAE instruction set does not provide a convenient way to restore the contents of the step counter.
To obviate the need to do so, the XVM is designed to
inhibit program or automatic priority interrupts
occurring for two instructions following the NORM
or NORMS (normalize, signed) instruction. These
two instructions are normally a DAC followed by a
LACS which saves the contents of the AC, then puts
the contents of the step counter in the AC. Thus, if
interrupt-accessed subroutines make use of the EAE,
the AC and MQ are the only registers that must be
preserved during the interrupt, then restored in the
EAE at the completion of the interrupt service.

LONG RIGHT SHIFT
LONG RIGHT SHIFT
[

6405X X

[

SN S

TS N

VRN N

SN N

[

Mnemonic Name
Octal Code

LRS n
6405XX + n

Operation

The AC and MQ function as a 36-bit register to permit serial
shifting of their contents ‘““n” bit positions to the right, “n”
being specified by the contents of the six low-order bits of the
instruction word. Shifting halts when the contents of the step
counter, initialized to the 2’s complement of “n”’, reach zero.
For each shift step, the contents of AC;; enter MQo and the
contents shifted out of MQ,; are lost. The contents of the Link,
usually initialized to zero, remain unchanged and enter AC, at
each step to replace the contents of vacated bits.

6-49

Graphic
17

ACCUMULATOR

LINK

17
MULTIPLIER

1 o orienT RecisTER [+ HOST
15-0196

LONG RIGHT SHIFT, SIGNED
LONG RIGHT SHIFT, SIGNED

6605XX

LRSS n

15-0931

LRSS n
6605XX + n

Mnemonic Name
Octal Code
Operation

The content of ACy is entered in the Link. Then, the AC and the
MQ function as a 36-bit register to permit serial shifting of their
contents “‘n”’ bit positions to the right, “n” being specified by
the contents of the six low-order bits of the instruction. Shifting
halts when the contents of the step counter, initialized to the 2’s
complement of *“n”, reach zero. For each shift step, the contents
of AC,; enter MQ, and the contents shifted out of MQ,; are
lost. The content of the Link remains unchanged and enters
AC, at each step to replace the contents of vacated bits.

Graphic

LINK

ACq

o)
LINK

——

17
MULTIPLIER

ACCUMULATOR

QUOTIENT REGISTER

LoS

15-0197

6-50

LONG LEFT SHIFT
LONG LEFT SHIFT

6406XX

L LSn

15-0932

Mnemonic Name
Octal Code
Operation

LLS n
6406XX + n
The AC and the MQ function as a 36-bit register to permit serial
shifting of their contents “‘n” bit positions to the left, “n” being
specified by the contents of the six low-order bits of the instruction word. Shifting halts when the contents of the step counter
initialized to the 2’s complement of “n”’, reach zero. For each
shift step, the contents of MQ, enter AC,; and the contents
shifted out of AC, are lost. The content of the Link, usually
initialized to zero, remains unchanged and enters MQ,; at each
step to replace the contents of vacated bits.

Graphic

LOST =—

ACCUMULATOR

ft——

17
MULTIPLIER

QUOTIENT REGISTER

4—1

LINK
15-0198

LONG LEFT SHIFT, SIGNED
LONG LEFT SHIFT, SIGNED

6606XX

LLSSn

15-0933

Mnemonic Name
Octal Code

Operation

LLSS n
6606XX + n

The content of AC is entered in the Link. The AC and MQ
function as a serial 36-bit register to permit serial shifting to
their contents ““n’ bit positions to the left, “n” being specified
by the contents of the six low-order bits of the instruction word.
Shifting halts when the contents of the step counter, initialized
to the 2’s complement of *‘n”, reach zero. For each shift step,
the contents of MQo enter AC;; and the contents shifted out of
ACy are lost. The content of the Link remains unchanged and
enters MQ,; at each step to replace the contents of vacated bits.

6-51

Graphic

ACo

LINK

17
ACCUMULATOR

LOST =—

0o
—

17
MULTIPLIER

QUOTIENT REGISTER

[¢—]

LINK

15-0199

ACCUMULATOR LEFT SHIFT
ACCUMULATOR LEFT SHIFT
)

6407XX

]

{

]

ALS n
15-0934

Mnemonic Name
Octal Code

Operation

ALS n
6407XX + n

The contents of the AC are shifted “n”’ bit positions to the left,
“n” being specified by the contents of the six low-order bits of

the instruction word. Shifting halts when the contents of the
step counter, initialized to the 2’s complement of “n”, reach
zero. For each shift step, the content of the Link, usually
initialized to zero, enters AC,7 to replace the contents of vacated
bits. The contents shifted out of AC, are lost.
Graphic
LOST -=—

ACCUMULATOR

LINK
15-0200

6-52

ACCUMULATOR LEFT SHIFT, SIGNED
ACCUMULATOR LEFT SHIFT, SIGNED

6607 XX

ALSS n

15-0935

Mnemonic Name
Octal Code

Operation

ALSS n

6607XX + n

The content of AC, enters the Link. Then, the contents of the

AC are shifted “n”” bit positions to the left, “n” being specified
by the contents of the six low-order bits of the instruction word.
Shifting halts when the contents of the step counter, initialized
to the 2’s complement of “n”, reach zero. For each shift step,
the content of the Link remains unchanged and enters AC,; to
replace the contents of vacated bits. The contents shifted out of
AC, are lost.
:

Graphic

ACo

LOST -—

LINK

ACCUMULATOR

4+—

LINK

15-02014

6-53

EAE Arithmetic Instructions

MULTIPLY, UNSIGNED

653122

MUL

15-0936

MUL
653122

Mnemonic Name
Octal Code
Operation

Multiply the contents of Memory register Y (the multiplicand)
by the contents of the MQ (the multiplier), and place the resulting 36-bit product in the AC and the MQ with the more significant half appearing in the AC. The address of Y is taken to be
sequential to the address of the MUL instruction word. Prior to
this instruction, the contents of the Link must be zero and the

multiplier must be entered in the AC. During the set-up phase
of MUL, the multiplier is transferred to the MQ, the AC is
cleared to zero, and the step counter is initialized to the 2’s complement of 225(18,o steps); the six low-order bits of the instruction word specify the step count. The arithmetic phase, executed
as multiplication of one unsigned quantity by another (18 bits,
binary point of no consequence), halts when the step counter

counts up to zero. The content of the Link remains zero. The
contents of Y are unchanged. The program resumes as the next
instruction (Memory register Y + 1).

0 to SC
Y+MQ to (AC,MQ)

Symbolic

OtoL
PC + 2 to PC
C = A+B

Data Structure

Pre-execution

Post execution
L

Instruction Sequence

Contents

Y-2

LAC Multiplier

Y-1
Y

MUL
Multiplicand

Y+1

Next Instruction

6-54

MULTIPLY, SIGNED
MULTIPLY, SIGNED

657122

MULS

15-0937

Mnemonic Name
Octal Code
Operation

MULS
657122
Multiply the contents of Memory register Y (the multiplicand)
by the contents of the MQ (the multiplier),
and place the signed
product in the AC and MQ with the sign notation and more
significant portion in the AC. Bits ACy and AC; each receive the
sign of the product; the remaining AC and MQ bits represent
the magnitude of the product in 1’s complement form. The
address of Y is taken to be sequential to the address of the
MULS instruction word. The contents of the Y are taken to be
the absolute value of the multiplicand; the contents of the Link
are taken to be the original sign of the multiplicand (MULS
assume previous execution of an EAE GSM instruction, q.v.).
Just prior to this MULS instruction, the multiplier must be
entered in the AC. During the setup phase of the MULS
instruction, the multiplier is transferred to the MQ and 1’s complemented if negative, the AC is cleared to zero, and the step
counter is initialized to the 2’s complement of 224(18,¢ steps);
the six low-order bits of the MULS instruction word specify the
step count. The arithmetic phase, executed as multiplication of
one signed quantity by another (sign bit plus 17 magnitude bits,
binary point position of no consequence), halts when the step
counter counts up to zero. The link is cleared to zero. The contents of Y are unchanged. The program resumes at the next
instruction (Memory register Y + 1).
0to SC
Y+MQ to (AC,MQ)
OtoL
PC + 2 to PC
C = A+B

Symbolic

Data Structure

Pre-execution

Pre~execution:
L

XXXX

*Original sign of B.

6-55

Post execution
Post execution:

A
S =L ¥ Sign

Instruction Sequence

Contents
LAC Multiplicand
GSM (take absolute value and
save sign in Link)
DACY
LAC Multiplier
MULS
Multiplicand (absolute value)
Next Instruction

Y-5

DIVIDE, UNSIGNED
LN

640323

DIV

15-0938

Mnemonic Name
Octal Code

Operation

DIV
640323

Divide the contents of the AC and the MQ (an unsigned 36-bit
dividend) by the contents of Memory register Y (the divisor).
The resulting quotient appears in the MQ. The remainder is in
the AC. The address of Y is taken to be sequential to the
address of the DIV instruction word. Prior to this, the contents
of the Link must be zero, and the dividend must be entered in
the AC and MQ (LAC least significant half). If the divisor is not
greater than the AC portion of the dividend, divide overflow
occurs (magnitude of quotient exceeds the 18-bit capacity of the
MQ), and the Link is set to one to signal the overflow condition;
data in the AC and the MQ are of no value. A valid division
halts when the step counter, initialized to the 2’s complement of
235(19,0 steps), counts up to zero (the six low-order bits of the
DIV instruction word specify the step count). The contents of
the Y are unchanged. The program resumes at the next instruction (Memory register Y + 1).

6-56

Symbolic

IfY < AC, 1 to L (divide overflow)
If Y> AC, 0to SC (AC,MQ)/Y to MQ (quotient), AC
(remainder)
Oto L
PC + 2 to PC
A=BQ+r

Data Structure
Pre-execution

AC,MQ

Post execution
(no overflow)
L

Instruction Sequence
Register
Y-4

Y-3
Y-2
Y-1
Y
Y + 1

6-57

Conients
LAC Dividend (least significant half)
LMQ
LAC Dividend (most significant half)
DIV
Divisor
Next Instruction

DIVIDE, SIGNED

644323

DIVS
15-0939

Mnemonic Name
Octal Code
Operation

Symbolic

DIVS
644323

Divide the contents of the AC and MQ (a 36-bit signed dividend
with the sign in bits ACy and AC, and the remaining 34 bits
devoted to magnitude) by the contents of Memory register Y
(the divisor). The resulting quotient appears in the MQ with the
algebraically determined sign in bit MQ, - ;7. The remainder is
in the AC with bit ACy containing the sign of the dividend and
bits AC; - ;7 containing the magnitude (1’s complement). The
address of Y is taken to be sequential to the address of the DIVS
instruction word. The contents of Y are taken to be the absolute
value of the divisor; the contents of the Link are taken to be the
original sign of the divisor (DIVS assumes previous execution of
an EAE GSM instruction, q.v.). Prior to this DIVS instruction,
the dividend must be entered in the AC and MQ (LAC of least
significant half, LMQ, and LAC of most significant half). The

MQ portion of a negative dividend is 1’s complement prior to
the division. If the divisor is not greater than the AC portion of
the dividend, divide overflow occurs (magnitude of the quotient
exceeds the 17-bit plus sign capacity of the MQ), and the link is
set to one to signal the overflow condition; data in the AC and
the MQ are of no value. A valid division halts when the step
counter, initialized to the 2’s complement of 235 (19,0 steps),
counts up to zero (the six low-order bits of the DIVS instruction
word specify the step count). The content of the Link is cleared
to zero. The contents of Y are unchanged. The program
resumes at the next instruction (Memory register Y + 1).
If Y AC, 1 to L (divide overflow)
IfY> AC,0to SC (AC,MQ)/Y to MQ (quotient), AC

(remainder)
OtoL
PC + 2 to PC

6-58

Pre-execution

SIS

*Original sign of B

Post execution
(no overflow)
L

Lo
(overflow)

[s]

(S=Sign A)

[

[s]

(S=Sign A ¥ L)

AC,MQ

Meaningless j
0

Instruction Sequence

I 0 I rB l

Contents

Y-7
Y-6

LAC Divisor
GSM

Y-5 Y-4
Y-3
Y-2
Y-1
Y
Y +1

DAC Divisorin Y
LAC Dividend (least significant half)
LMQ
LAC Dividend (most significant half)
DIVS
Divisor (absolute value)
Next Instruction

6-59

INTEGER DIVIDE, SIGNED
INTEGER DIVIDE, SIGNED

657323

IDIVS

15-0940

Mnemonic Name
Octal Code
Operation

Symbolic

IDIVS
657323

Divide the contents of the AC and the MQ (AC is zero, MQ
contains a signed integer dividend) by the contents of Memory
register Y (the divisor). The resulting quotient appears in the
MQ with the algebraically determined sign in bit MQ, and the
magnitude (1’s complement) in bits MQ; - ;7. The remainder is
in the AC with bit AC, containing the sign of the dividend and
bits AC, - |7 containing the magnitude (1’s complement). The
address of Y is taken to be sequential to the address of the
IDIVS instruction word. The contents of Y are taken to be the
absolute value of the divisor; the contents of the Link are taken
to be the original sign of the divisor (IDIVS assumes previous
execution of an EAE GSM instruction, q.v.). Prior to this
IDIVS instruction, the dividend must be entered in the AC (the
setup phase of IDIVS transfers the dividend to the MQ, clears
the AC, and 1’s complements the MQ if the dividend is negative). Divide overflow occurs only if division by zero is
attempted; i.e., the quotient’s magnitude will not exceed the 17bit plus sign capacity of the MQ. The division halts when the
step counter, initialized to the 2’s complement of 235(19,¢ steps),
counts up to zero (the six low-order bits of the IDIVS instruction word specify the step count). The contents of the Link are
cleared to zero. The contents of Y are unchanged. The program
resumes at the next instruction (Memory register Y + 1).
0 to SC
MQ/Y to MQ (quotient), AC (remainder)
OtoL
PC + 2 to PC

6-60

A =BQ+r

Data Structure

Pre-execution

AC, MQ

XXX

171

*Qriginal sign of B

Post execution

(s=L ¥ Sign A)

(s=Sign A)
If Y=0 (overflow)

[::::]
Instruction Sequence

AC,MQ

meaningless

4J
Register
Y-5
Y-4

Y-3

Y-2
Y-1

Y
Y+1

6-61

[:::::::]

LAC Divisor

Contents

GSM

DAC Divisor (absolute value)in Y
LAC Dividend

IDIVS

Divisor (absolute value)
Next Instruction

INTEGER DIVIDE, UNSIGNED
INTEGER DIVIDE, UNSIGNED

653323 ;

]

[

IDIV

15-0941

Mnemonic Name
Octal Code

Operation

Symbolic

IDIV
653323

Divide the contents of the AC and the MQ (AC is zero, MQ

contains an 18-bit integer dividend) by the contents of Memory
register Y (divisor). The resulting quotient appears in the MQ;
the remainder is in the AC. The address of Y is taken to be
sequential to the address of the IDIV instruction word. Prior to
this instruction, the contents of the Link must be zero, and the
dividend must be entered in the AC (the setup phase of IDIV
transfers the dividend to the MQ and clears the AC). Division
overflow occurs only if division by zero is attempted, i.e., the
quotient’s magnitude will not exceed the 17-bit plus sign capacity of the MQ. The division halts when the step counter,
initialized to the 2’s complement of 230(19,, steps), counts up to
zero (the six low-order bits of the IDIV instruction word specify
the step count). The content of the Link is cleared to zero. The
contents of Y are unchanged. The program resumes at the next
instruction (Memory register Y + 1).

0 to SC

MQ/Y to MQ (quotient), AC (remainder)

OtoL
PC + 2 to PC

6-62

Pre-execution

XXX

Post execution

If Y=0 (overflow)
L

meaningless
Instruction Sequence

AC ,MQ

6-63

Contents

LAC Dividend
IDIV
Divisor
Next Instruction

FRACTION DIVIDE, UNSIGNED

650323

RN T

TR T

FRDIV

15-0942

Mnemonic Name
Octal Code

Operation

FRDIV
650323

Divide the contents of the AC and the MQ (AC contains an 18-

bit fractional dividend, MQ is zeroed at setup) by the contents
of Memory register Y (the divisor). The binary point is assumed
at the left of ACy. The quotient appears in the MQ); the remainder is in the AC. The address of Y is taken to be sequential to
the address of the FRDIV instruction word. Prior to this
instruction, the contents of the Link must be zero, and the dividend must be entered in the AC (the setup phase of FRDIV
clears the MQ). If the divisor is not greater than the dividend,
divide overflow occurs (magnitude of quotient exceeds the 18bit capacity of the MQ), and the link is set to one to signal the
overflow condition; data in the AC and the MQ are of no value.
A valid division halts when the step counter, initialized to
235(19,0 steps), counts up to zero (the six low-order bits of the
FRDIV instruction word specify the step count). The contents
of the Link remain zero. The contents of Y are unchanged. The
program assumes at the next instruction (Memory register Y +
1).

Symbolic

If Y< AC, 1 to L (divide overflow)
IfY> AC,0to SC AC/Y to MQ (quotient), AC (remainder)

Oto L
PC + 2 to PC

6-64

Pre-execution
L

II’

XXX

l
35

]

Post execution

(no overflow)
L

0 I

(overflow)

AC,MQ

meaningless

Instruction Sequence

6-65

Contents
LAC Dividend
FRDIV
Divisor
Next Instruction

FRACTION DIVIDE, SIGNED
FRACTION DIVIDE, SIGNED

654323

FRDIVS

15-0943

Mnemonic Name
Octal Code
Operation

Symbolic

FRDIVS
654323
Divide the contents of the AC and the MQ (AC contains an 18bit signed dividend with the sign in bits ACy and AC, and the
remaining 16 bits devoted to magnitude, MQ is zeroed at setup)
by the contents of Memory register Y (the divisor). The binary
point is assumed between ACy and AC,. The resulting quotient
appears in the MQ with the algebraically determined sign in bit
MQo and the magnitude (1’s complement) in bits MQ, - 7. The
remainder is in the AC with bit AC, containing the original sign
of the dividend and bits AC, - ;7 containing the magnitude (1’s
complement). The address of Y is taken to be sequential to the
address of the FRDIVS instruction word. The contents of Y are
taken to be the absolute value of the divisor; the contents of the
Link are taken to be the original sign of the divisor (FRDIVS
assumes previous execution of an EAE GSM instruction, q.v.).
Prior to this FRDIVS instruction, the dividend must be entered
in the AC (the setup phase of FRDIVS clears the MQ and 1’s
complements the dividend, if negative, prior to the division). If
the divisor is not greater than the dividend, divide overflow
occurs (magnitude of the quotient exceeds the 18-bit capacity of
the MQ) and the Link is set to one to signal the overflow condition. Data in the AC and the MQ are of no value. A valid division halts when the step counter, initialized to the 2’s
complement of 235(19,¢ steps), counts up to zero (the six loworder bits of the FRDIVS instruction word specify the step
count). The contents of the Link are cleared to zero. The contents of Y are unchanged. The program resumes at the next
instruction (Memory register Y + 1).
If Y< AC, 1 to L (divide overflow)
IfY> AC, 0to SC AC/Y to MQ (quotient), AC (remainder)
Oto L
PC + 2 to PC

6-66

Data Structure
Pre-execution

A=BQ+r

s ]
[of

[
A Jxx]
[sIs

[(*1

*original sign of B

Post Execution
(no overflow)
L

L—_(_):l

$
0

(s=Sign A)

I s
7

17
(s=L 3 Sign A)

(overflow)
L

AC,MQ

meaningless

Instruction Sequence

0
35

Y-3

Y-2
Y-1

+ =<

1 I

6-67

Contents
LAC Divisor
GSM

DAC Divisor (absolute value)in Y

LAC Dividend
FRDIVS
Divisor (absolute value)
Next Instruction

6.3 FLOATING POINT UNIT
The FP15 Floating-Point Processor (FPU) is a hardware option that enables the XVM to perform
arithmetic and logic operations using floating-point arithmetic. The prime advantage is increased
speed without the necessity of writing complex floating-point software routines. The FP15 has singleprecision and extended-integer capability, as well as single- and double-precision floating point.

Floating-point instructions consist of two 18-bit words: an instruction word with a 71 code (Figure 614), followed by an address word (Figure 6-15). The instruction word specifies type of operation, type
of precision, and data format. The address word specifies direct or indirect addressing and contains the
address of the memory operand, if direct, or the address of a word containing the address of the
memory operand, if indirect. Each instruction received from memory is monitored by both the FP15
and CPU. An instruction with an octal code of 71 in bits 00 through 05 is recognized as a floatingpoint instruction.
The single- and double-precision floating point and single-precision integer data formats are identical
to those in the existing XVM floating-point software.

For single-precision integer words, the 18-bit 2’s complement operand is loaded from memory into bits
18 through 35 of the FMA register. The value of bit 18 (sign bit) is loaded into the remaining bit
positions (bits 17 through 00) to extend the sign bit (Figure 6-16).

INSTRUCTION

71g

—

FPU CODE ————————l
INSTRUCTION

[

TYPE

BIT 10=0

GET OPERAND

BIT 10=1

DO NOT GET OPERAND

BIT 11=0

SINGLE PRECISION

BIT 11=1

DOUBLE

BIT 12=0
BIT 12=1

INTEGER FORMAT
FLOATING FORMAT

BIT 13=0

NORMALIZE

BIT 13=1

DO NOT NORMALIZE

BIT 14=0

ROUND

BIT

DO NOT ROUND

14=1

WORD

PRECISION

NOT USED

BIT 16 | BIT 17

NO EFFECT

MAKE A SiGN POSITIVE
MAKE A SIGN NEGATIVE

COMPLEMENT
A SIGN
15-0562

Figure 6-14

Floating Point Instruction Format

6-68

ADDRESS WORD

l——— BIT Ol-I17 ADDRESS OF FIRST WORD OF ARGUMENT
BIT 00=0 DO NOT PERFORM INDIRECTION

BIT 00=1

PERFORM INDIRECTION (MAXIMUM-ONE LEVEL)
15-0551

Figure 6-15

Floating Point Address Format

WORD

ONE

OPERAND

(2'S COMPLEMENT)
17

15-0555

Figure 6-16

Single Precision Integer Format

For extended integer words, the high-order operand from memory is loaded into bits 00 through 17 of

the FMA, and the low-order operand is loaded into bits 18 through 35.

All integers loaded into the floating-point processor are converted to 36-bit sign and magnitude numbers (Figure 6-17).

FIRST

HIGH-ORDER OPERAND

WORD

(2'sS COMPLEMENT)

SECOND WORD

LOW-ORDER OPERAND

(2'S COMPLEMENT)

15-0556

Figure 6-17

Extended Integer Format

For single-precision floating-point words, the first word from memory consists of nine bits of loworder mantissa and nine bits of exponent. The nine bits of mantissa are loaded into bits 18 through 26
of the FMA, and bits 27 through 35 are zeroed. The nine bits of exponent in 2’s complement form are
loaded into bits 09 through 17 of the EPA, with bit 09 representing the sign bit. Bits 00 through 08 are
loaded with the value of bit 09. This extends the sign bit to bit position 00. The second word from
memory is loaded into bits 00 through 17 of the FMA and represents the 18 bits of high-order mantissa
(Figure 6-18).

6-69

FIRST

LOW-ORDER

WORD

MANTISSA

EXPONENT

SECOND

(2'S

COMPLEMENT)

WORD

I-.O

HIGH -ORDER MANTISSA

SIGN

15-0557

Figure 6-18

Single Precision Floating Point Format

For double-precision floating-point words, the 18-bit 2’s complement exponent

is first loaded into the
EPA, the 18-bit high-order mantissa is loaded into A SIGN and bits 01 through
17 of the FMA, and
the low-order mantissa is loaded into bits 18 through 35 of the FMA. All
36 bits of the FMA are
loaded at one time (Figure 6-19).

FIRST

COMPLEMENT)

(2'S

—_

EXPONENT

WORD

siGN
SECOND

WORD

HIGH-ORDER

t’-(:O

MANTISSA

THIRD

WORD

LOW-ORDER MANTISSA

17
15-0554

Figure 6-19

Double Precision Floating Point Format

Generally, the FP15 instructions are in the following format:
XX

MODIFIER

XX
OPERATION

FORMAT

For example, if an unrounded, unnormalized, double-precision floating
point Add instruction is specified, the mnemonic is specified as UUDAD: where the UU is the modifier,
D is the format, and AD is
the operation. Modify FMA instructions, branch instructions, and
diagnostic instructions do not follow this general pattern.

6-70

All the FP15 instructions (except Floating-Point Test, Branch, Load or Store JEA, and diagnostic
instructions) can be microprogrammed with bits 16 and 17 of the instruction word as described below:
Bit 16
0
0
1
1

Bit 17
0
1
0
1

No effect
Make A SIGN positive
Make A SIGN negative
Complement A SIGN

Not used in FP test,
Load or Store JEA,
Branch on condition,
and diagnostic instructions.

For example, the instruction 710540 specifies double-precision floating-point subtraction. If desired to
make A SIGN negative, the instruction would be specified as 710542.
Table 6-3
FP1S5 Instruction Summary

Mnemonic

Instruction Type

FPT
ISB
ESB
FSB
URFSB
UNFSB

Floating-Point Test
Single Integer Subtract
Extended Integer Subtract
Single-Precision Float Subtract
Unrounded, Single-Precision Float Subtract
Unnormalized, Single-Precision Float
Subtract
UUFSB
Unrounded, Unnormalized, Single-Precision
Float Subtract
DSB
Double-Precision Float Subtract
URDSB
Unrounded, Double-Precision, Float Subtract
UNDSB
Unnormalized, Double-Precision Float
Subtract
UUDSB
Unrounded, Unnormalized, Double-Precision
Float Subtract
IRS
Single Integer Reverse Subtract
ERS
Extended Integer Reverse Subtract
FRS
Single-Precision Float Reverse Subtract
URFRS
Unrounded, Single-Precision Float Reverse
Subtract
UNFRS
Unnormalized, Single-Precision Float Reverse
Subtract
UUFRS
Unrounded, Unnormalized, Single-Precision
Float Reverse Subtract
DRS
Double-Precision Float Reverse Subtract
URDRS
Unrounded, Double-Precision Float Reverse
Subtract
UNDRS | Unnormalized, Double-Precision Float Reverse
Subtract
UUDRS
Unrounded, Unnormalized, Double-Precision
Float Reverse Subtract
IMP
Single Integer Multiply
EMP
Extended Integer Multiply
FMP
Single-Precision Float Multiply
URFMP | Unrounded, Single-Precision Float Multiply

6-71

Octal Code
710314
710400
710500
710440
710450
710460
710470
710540
710550
710560
710570
711000
711100
711040
711050
711060

711070
711140
711150
711160
711170

711400
711500
711440
711450

Table 6-3 (Cont)
FP15 Instruction Summary

Mnemonic

Instruction Type

Octal Code

UNFMP |

Unnormalized, Single-Precision Float Multiply

711460

UUFMP |

Unrounded, Unnormalized, Single-Precision

711470

Float Multiply
DMP
URDMP |

Double-Precision Float Multiply
Unrounded, Double-Precision Float Multiply

711550

UNDMP |
UUDMP|

Unnormalized, Double-Precision Float Multiply
Unrounded, Unnormalized, Double-Precision

711560
711570

Float Multiply
Single-Precision Integer Divide
EDV
Extended Integer Divide
FDV
Single-Precision Float Divide
URFDYV | Unrounded, Single-Precision Float Divide
DDV
Double-Precision Float Divide
URDDYV | Unrounded, Double-Precision Float Divide
IRD
Single-Precision Integer Reverse Divide
IDV

711540

712000
712100
712040
712050
712140
712150
712400

ERD

Extended Integer Reverse Divide

712500

FRD

Single-Precision Float Reverse Divide

712440

URFRD |

Unrounded, Single-Precision Float Reverse

712450

DRD

Divide
Double-Precision Float Reverse Divide

712540

URDRD |

Unrounded, Double-Precision Float Reverse

712550

ILD

Divide
Single-Precision Integer Load

713000

ELD

Extended Integer Load

713100

FLD

Single-Precision Float Load

UNFLD |

Unnormalized, Single-Precision Float Load

DLD

Double-Precision Float Load

713050
-

713070
713150

UNDLD | Unnormalized, Double-Precision Float Load

713170

IST
EST

Single-Precision Integer Store
Extended Integer Store

713700

FST

Single-Precision Float Store

713640

URFST
UNFST

Unrounded, Single-Precision Float Store
Unnormalized, Single-Precision Float Store

713650
713660

UUFST

Unrounded, Unnormalized, Single-Precision

713670

DST

Float Store
Double-Precision Float Store

713750

UNDST |

Unnormalized, Double-Precision Float Store

713770

713600

ILF

Single-Precision Integer Load and Float

714010

UNILF

Unnormalized, Single-Precision Integer Load

714030

ELF

and Float
Extended Integer Load and Float

714110

UNELF

Unnormalized, Extended Integer Load and

714130

FLA

Float
Float FMA

714210

UNFLA
FLX
URFLX

Unnormalized Float FMA
Single-Precision Float Load and Fix
Unrounded, Single-Precision Float Load

714230
714460
714470

and Fix

6-72

Table 6-3 (Cont)
FP15 Instruction Summary

Mnemonic

Instruction Type

Octal Code

Double-Precision Float Load and Fix
DLX
URDLX | Unrounded, Double-Precision Float Load

714560
714570

Fix EPA, FMA
FXA
URFXA | Unrounded, Fix EPA, FMA
Single-Precision Integer Load FMQ
ILQ
Extended Integer Load FMQ
ELQ
Single-Precision Float Load FMQ
FLQ
UNFLQ | Unnormalized, Single-Precision Float FMQ
Double-Precision Float Load FMQ
DLQ
UNDLQ | Unnormalized, Double-Precision Float Load

714660
714670
715000
715100
715050
715070
715150
715170

Swap FMA and FMQ
SWQ
Unnormalized, Swap FMA and FMQ
|
UNSWQ
Load JEA Register
LJE
Store JEA Register
SJE
Single-Precision Integer Add
IAD
Extended Integer Add
EAD
Single-Precision Float Add
FAD
URFAD | Unrounded, Single-Precision Float Add
UNFAD | Unnormalized, Single-Precision Float Add
UUFAD | Unrounded, Unnormalized, Single-Precision

715250
715270
715400
715600
716000
716100
716040
716050
716060
716070

Double-Precision Float Add
DAD
URDAD | Unrounded, Double-Precision Float Add
UNDAD | Unnormalized, Double-Precision Float Add
UUDAD | Unrounded, Unnormalized, Double-Precision

716140
716150
716160
716170

and Fix

FMQ

Float Add

BZA
BMA
BLE
BPA
BRU
BNA
BAC
FZR
FAB
FNG
FCM
FNM
DMF
DMN
DRR
DSR
DBK

Float Add

Branch on 0 FMA
Branch on Minus FMA
Branch if FMA<O0
Branch on positive FMA
Branch Unconditional
Branch on non-zero FMA
Branch if GUARD bit is Set
Zero EPA (A SIGN) FMA
Make A SIGN positive (Absolute Value)
A SIGN negative
Make
Complement A SIGN
Normalize EPA (A SIGN) FMA
Diagnostic Mode Off
Diagnostic Mode On
Diagnostic Read Registers
Diagnostic Step and Read Registers
Debreak

716601
716602
716603
716604
716606
716610
716620
711200
713271
713272
713273
713250
717200
717300
710000
710100 + n
703304

A complete description of the FP15 Floating-Point Processor instruction set is prov1dedin the FPI5
Floating- Point Processor Reference Manual, DEC-15-HQEA-D.

6-73

6.4

AUTOMATIC PRIORITY INTERRUPT INSTRUCTION SET

Skip on Priorities Inactive

10T Code

Device Select

L___' |J

Subdevice Select

IOP’'S
Clear AC

15-0954

This instruction compares a condition code in the Accumulator with part of the ENABLE bit and

Priorities Active register. If any bit of the condition code matches the corresponding bit of the
ENABLE or Priority Active register and both are set, the next instruction is skipped. Otherwise the

next instruction is executed. The corresponding bits are shown in Figure 6-20.

Accumulator

—l

]

COMPARE

0
|\

API Enable

7
J

Priorities Active
Register
15-0955

Figure 6-20

Skip on Priorities Inactive

6-74

INITIATE SELECT ACTIVITY

ISA

Initate Select Activity

b5
|

6
l

.
|

(S TN SR N

]

)

1B
I

TN W

NN NN NN NN NN A

17
I

\:|——I ll IOP’S

Device Select

| ’

|IOT Code

Subdevice Select

Clear AC

15-0956

‘The content of Accumulator bit 0 is placed into the ENABLE flip-flop; Accumulator bits 6 through 9
are ORed into bits 4 to 7 of the API request register, and Accumulator bits 10 through 17 are ORed
into bits O through 7 of the API Priorities Active register.

Accumulator

6
|

I '

]

9
[

10
T

I{ l IVI

[

——

API

AP1 Priorities

Request Register

Active Register

15-0957

6-75

DEBREAK
DBK

Debreak

QT Code

Device Select

156

|__

Subdevice Select ——

IOP’S
Clear AC

15-0958

This instruction is used to release the highest active priority level. Its use is to return a subroutine’s
priority to the normal assignment after the requirement for an interim ISA-initiated raising of priority
has been satisfied. DBK should not be used to terminate a subroutine as it does not provide for
restoration of the PC, Link, etc.
DEBREAK AND RESTORE
DBR

Debreak and Restore

I0T Code

Device Select

|_____| ll

Subdevice Select

10P’S
Clear AC
16-0959

This instruction zeroes the highest priority presently in the Priority Active register, thus clearing the
way for future requests. It also primes the PDP-15 to restore the Link, the program counter, and User
mode to their status at the time the API request was honored. The actual restoration occurs at the

execution of any indirect instruction. However, a JMP indirect is usually used exiting the subroutine
which must immediately follow the DBR instruction.
Programming Note
Normally, the SPI and ISA instructions are used
sequentially to test first that the program segment
currently in progress is not already at the requested
priority level, and then if not, to initiate a raising of
priority to the requested level. Hence, if a program
segment cannot raise its priority, the segment must
already be at the requested level or higher. The ISA
instruction cannot be used to lower the priority level

of an active program segment. The hardware will not
recognize the priority change.

6-76

RESTORE

RES

Restore

5
{

]

]
15-0960

Restore the status of the Link, Bank mode, and User mode, at the first indirect instruction after it is
executed. The RES does not, however, affect the API priority levels.
READ PRIORITY LEVELS

RPL

Read Priority Levels

IOT Code

Device Select

I0P’S

Subdevice Select

Clear AC
15-0961

The contents of the API ENABLE flip-flop is read into Accumulator bit 0, the content of the API
Request register is read into Accumulator bits 2 through 9, and the content of the Priorities Active
register is read into Accumulator bits 10 through 17, as shown in the following illustration.
Accumulator

2
|

API

Enable

1§

{

]

{

]

—/\

“~

API

—

Priorities

Request Register

Active Register
15-0962

6-77

DISABLE BREAKS

Disable Breaks

DBI
0

15-0963

Inhibits API and PI. Incorporated to make re-entrant programming more convenient. When in Monitor mode, one free instruction will be granted after CAL, JMS, PI; two free instructions after NORM.
“Free instructions’ means executable instructions that are performed before the computer goes into
the Interrupt mode. See example program.

ENABLE BREAKS
EBI

Enable Breaks

15-0964

Enable API or PI. See example program.
Example:

Each of the sequences listed is expected to be uninterruptable (except for data breaks).

JMS A or IMS* (A)
A

/INTERRUPT FLAG OCCURS

LAC A

/INTERRUPT IS SERVICED

JMS B or IMS* (B)
B

DBI

LAC X

/INTERRUPT FLAG OCCURS

DAC XX

LACY
EBI

DACYY

6.5

/INTERRUPT WILL BE SERVICED

KWI15 REAL-TIME CLOCK

The real-time clock, when enabled, counts in memory location 00007 the number of cycles completed
by any one of three inputs:
1.

The line voltage (50 or 60 Hz).

An M401 R-C Clock (offered as standard) which can be set to any frequency from 0 to 10
kHz.

A user-supplied TTL compatible signal that is fed to a point on the XVM logic.
6-78

When location 00007 overflows, an interval program interrupt or API request, if available, is generated informing the monitor that its preset interval is over. The monitor must either disable the clock or
reinitialize location 00007 to the 2’s complement of the number of counts it needs to tally.
The incrementing of location 00007 during a real-time clock request occurs via the I/O Processor,
using its increment-memory facility. A real-time clock request takes priority over API, PI and IOT
requests.

The following IOT instructions are provided for use with the clock:
CLOCK ON

CLON

Clock On

5
1

(|
T

IOT Code

Device Select

IOP’S
.Clear AC

Subdevice Select

15-0965

The real-time clock is enabled to begin incrementing location 00007 and its flag is cleared.
CLOCK OFF

Clock Off

CLOF
0

b
|

10T Code

6
I

1
)

)

Device Select
Subdevice Select

15
I

17
1

I L 10P’S
Clear AC
15-0966

The real-time clock is disabled, preventing it from incrementing location 00007.

6-79

SKIP ON CLOCK FLAG
CLSF

Skip on Clock Flag

5
1

]

10T Code

]

Device Select

]

17
|

]

{

]

L'__J U I0P’S

Subdevice Select —

Clear AC
15-0067

The program counter is incremented and the next instruction skipped if the clock flag is set.

While the facility is enabled, requests for clock breaks have priority of acceptance over API and PI
requests. The first clock break may occur at any time up to 17 ms after the facility has been enabled.
The clock switch on the console can inhibit the clock from incrementing location 7.
6.6 KF15 POWER FAIL
The XVM contains circuitry which provides optimum protection of programs during machine turn-on
or turn-off, whether accidental or intended. The Power fail detection feature of the I/O Processor
allows time to store active registers before the system stops during a power failure, a system restart,
and the subsequent restoration of these registers when system power is reapplied.
The basic XVM is not affected by power interruptions of less than 10 ms duration. Active registers in
the processor (AC, AR, PC, etc.) will lose their contents when interruptions of longer duration occur,
but memory will not be disturbed. The power failure detection feature provides for saving the contents
of active registers in the event of longer power interrupt and for automatic restart of the system when
power is restored. The restart feature is switch-selected by the operator to be enabled or disabled.

When enabled, the program in progress resumes execution at location 000000. The system must be

operating with the program interrupt facility (or the API) enabled to sense the option’s initiation of a
program interrupt to save the register contents at the time of the line power failure. If API is enabled,
power fail interrupts on its highest level and traps to memory address 52.

There is only one instruction associated with power fail. That is:
SKIP ON POWER LOW FLAG
Skip On Power Low Flag
0

10T Code

Device Select

Subdevice Select ——-I

I ll

IOP'S
Clear AC
15-0968

The state of the power low flag is tested, and if set, indicates that system line
voltage has dropped and
that this flag has posted an interrupt; then the reset instruction is skipped.
The flag is cleared by the
power clear signal when the power interruption is over.

6-80

6.7

MEMORY MANAGEMENT

User mode may be enabled either by programmed instruction or by pressing the PROT switch on the

console and pressing the START key. When enabled, the USER indicator lights.

. The sole operator control is the PROT switch, which has an indicator above it. This indicator lights
when in User mode. The PROT switch is used with the START key to establish the proper mode at the
beginning of program execution. If the switch is up, then the program is started in User mode. The
switch has no further effect.

The RESET key clears the violation and non-existent memory flags, and User mode (i.e., memory
protect is turned off).
ENTER USER MODE
MPEU

Enter User Mode

b
|

Device Select

10T Code

5
|

Ly
IOP’S

]

Clear AC

Subdevice Select —

15-0969

User mode will be entered during the fetch cycle of the instruction following MPEU.
CLEAR NON-EXISTENT MEMORY
MPCNE

10T Code

Clear Nonexistent Memory Flag
11

Device Select

l__]

Subdevice Select ——

IOP’S
Clear AC

15-0970

The nonexistent memory flag posted when nonexistent memory has been referenced, is cleared by the
I0T.

6-81

SKIP ON VIOLATION FLAG
MPSK

Skip On Violation Flag

5
|

]

[

]

10T Code

)

{

IOP’'S

Device Select
Subdevice Select

{

Clear AC
15-0971

The Memory Protect Violation flag will be set whenever the execution of an instruction has violated
the provision of memory protection (see above).
CLEAR VIOLATION FLAG

MPCV

Clear Violation Flag

5
|

]

{

[

}

{

]

0T Code

]

{

]

{

iIOP’S

Device Selact
Subdevice Select

Clear AC
15-0972

The Violation flag, set if the boundary has been violated or an illegal instruction attempted, is cleared
by this IOT.

LOAD BOUNDARY REGISTER
MPLD

Load Boundary Register

b
I

10T Code

6
]

11
1

15
I

17
I

Device Select

| L 10P’S

Subdevice Select

Clear AC
15-0973

Load the Memory Protection register with the contents of AC 1 through 9.

6-82

SKIP ON NON-EXISTENT MEMORY

Skip On Nonexistent Memory Flag

MPSNE
|

]

{

]

10T Code

]

{

]

{

Device Select

]

IOP’S
Clear AC

Subdevice Select

15-0974

The Nonexistent Memory flag is set whenever the processor attempts to reference a nonexistent area of
core.

OR MANAGEMENT REGISTER TO AC
RDMM
0

Management Register to AC
5

15-0976

This instruction will OR the contents of the Management register (00-17) into the AC.

LOAD MANAGEMENT REGISTER
LDMM
0

Load Management Register
5

15-0977

This instruction will load the Memory Management register with the contents of the AC. The AC

remains unchanged. Note that to clear the Memory Management register, the IOT 700034 should be
used.

6-83

READ AND RESET ACCOUNTING CLOCK
RDCLK

Read and Reset Accounting Clock

5
|

]

{

]

{

]

{

]

15.0978

In the XVM Memory Processor there is a Task Accounting Clock. It is 18 bits in length and is
incremented every 10 us. The counting is inhibited whenever an API level of 0-3 or a PI break is in
progress.

CONTROL INSTRUCTION PRE-FETCH
Disable Instruction Pre-Fetch

15-0979

When this instruction is executed with AC 17=1 the ABORT CLR flip-flop is set. This in turn prevents
the IPF logic from synchronizing with a request from the XVM CPU. Normally, this is used in mainte-

nance only. The ABORT CIR flip-flop may be reset (to enable the IPF) by a CAF instruction or the
above instruction with AC17=0.
LOAD RELOCATION REGISTER
Load Relocation Register

15-0975

Load the Relocation register with the contents of AC 00 through 09. The Relocation register will be set
to the first address to which the user is to be relocated.

6.8

PERIPHERAL INSTRUCTION SET

Input/Output Transfer Instructions (I0Ts)
Table 6-4 lists the IOTs for XVM peripheral devices.

6-84

Table 64
Input/Output Transfer Instructions
Mnemonic Symbol

Octal Code

Operation Executed

f’rogram Interrupt
IOF

700002

Interrupt off.

ION

700042

Interrupt on.

KW15 Real-Time Clock

CLSF

700001

tSkiF the next instruction if the CLOCK flag is set
o

CLOF

700004

Clear the CLOCK flag and disable the clock.

CLON

700044

Clear the CLOCK flag and enable the clock.

PC15 High Speed Paper Tape Reader

RSF

700101

Skip, if READER flag is a 1.

RCF

700102

Clear READER flag, then inclusively OR the con-

RRB

700112

Read reader buffer. Clear READER flag and AC,
and then transfer content of the reader buffer into

tents of the reader buffer into the AC.

AC.

RSA

700104

Select reader in Alphanumeric mode. One 8-bit
character is read into the reader buffer.

RSB

700144

Select reader in binary mode. Three 6-bit characters are read into the reader buffer.
PC15 High Speed Paper Tape Punch

PSF

700201

Skip, if the PUNCH flag is set to 1.

PCF

700202

Clear the PUNCH flag.

PSA or
PLS

700204
700206

Punch a line of tape in Alphanumeric
mode.

PSB

700244

Punch a line of tape in Binary mode.

6-85

Table 6-4 (Cont)
Input/Output Transfer Instructions
Mnemonic Symbol

Octal Code

Operation Executed
I/0 Equipment

IORS

700314

Input/output read status. The content of given

flags replaces the content of the assigned AC bits.
CAF

703302

Clear all flags.

SPCO

703341

Skip, if a PC15 is connected to the system.

SK15

707741

Skip, if processor is a PDP-15 or XVM.

SBA

707761

Skip, if processor is in Bank mode.

DBA

707762

Disable Bank Addressing (enter Page mode).

EBA

707764

Enable Bank Addressing

Console Device Keyboard
KSF

700301

KRB

700312

Skip, if the KEYBOARD flag is set to 1.
Read the keyboard buffer. The content of the buf-

fer is placed in AC10-17 and the KEYBOARD
flag is cleared (half-duplex operation).
KRS

700332

Read keyboard buffer and select keyboard reader
(full-duplex operation).

Console Device Printer
TSF

700401

Skip, if the PRINTER flag is set.

TCF

700402

Clear the PRINTER flag.

TLS

700406

Load printer buffer. The content of AC00-17 is

placed in the buffer and printed. The flag is cleared
before transmission takes place and is set when the
character has been printed.
VP15-A Storage Tube Display
CXB

700502

Clear X-coordinate buffer.

CYB

700602

Clear Y-coordinate buffer.

LXB

700504

Load X-coordinate buffer from AC8-17.

LYB

700604

Load Y-coordinate buffer from AC8-17.

6-86

Table 6-4 (Cont)
Input/Output Transfer Instructions

Mnemonic Symbol

Operation Executed

Octal Code

VP15-A Storage Tube Display (Cont)

EST

700724

Erase storage tube.

SDDF

700521

Skip on DISPLAY DONE flag.

CDDF

700722

Clear DISPLAY DONE flag.

LXBD

700564

LYBD

700664

LXDNS

700544

LYDNS

700644

Load X-coordinate buffer and display the point

specified by XB and YB (Store mode).

Load Y-coordinate buffer and display the point

specified by XB and YB (Store mode).

Load the X-coordinate buffer and display the point

specified by XB and YB (Nonstore mode).

Load the Y-coordinate buffer and display the point

specified by XB and YB (Nonstore mode).

VP15-B (RM503), BL (RM503 and Light Pen),
C (VR12) and CL (VR12 and Light Pen)

DXL

700504

Load the X-coordinate buffer from AC8-17.

DXS

700544

Load the X-coordinate buffer and display the point

DYL

700604

DYS

700644

DXC

700502

Clear the X-coordinate buffer.

DYC

700602

Clear the Y-coordinate buffer.

DLB

7000704

Load the Brightness register from bits 16-17 of the

specified by the XB and YB.

Load the Y-coordinate buffer from AC8A-17.

Load the Y-coordinate buffer and display the point

specified by the XB and YB.

AC. This instruction clears the DISPLAY flag
associated with the light pen.

DSF

700501

Skip, if DISPLAY (light pen) flag is a 1.

DCF

700702

Clear DISPLAY (light pen) flag.

6-87

Table 6-4 (Cont)
Input/Output Transfer Instructions

Mnemonic Symbol

Octal Code

Operation Executed

VP15-M Storage Tube Display Multiplexer
LUDU

700764

Load Unit Designation register from AC10--17.
NP1S List-Mode P.H.A. Control

SOWC

701101

Skip on Word Count overflow.

CLWO

701102

Clear WORD COUNT OVERFLOW flag.

SETM

701104

Set Mode register from AC13-17.

SOAL

701121

Skip on A live-time overflow.

CALO

701122

Clear A live-time overflow.

CBLO

701124

Clear B live-time overflow.

SOBL

701141

Skip on B live-time overflow.
Memory Management

MPSK

701701

MPCV

701702

Clear PROTECT VIOLATION flag.

MPLD

701704

Load Boundary register AC00-09.

MPRC

701722

Read accounting clock to AC.

MPLR

701724

Load Relocation register.

MPSNE

701741

Skip on nonexistent MEMORY flag.

MPEU

701742

Enter User mode.

MPCNE

701744

Clear nonexistent MEMORY flag.

RDMM

700022

OR Memory Management register to AC0-17.

LDMM

700024

Load Memory
ACO-17.

RDCLK

701762

OR the Task Clock to AC0-17.

IPFH

701764

Inhibit IPF (Set Abort Clear).

Skip on PROTECT VIOLATION flag.

6-88

Management

from

Table 6-4 (Cont)
Input/Output Transfer Instructions

Mnemonic Symbol

Octal Code

Operation Executed
VT15 Graphic Processor

RS1

703002

Read status 1.

RS2

703022

Read status 2.

RS3

703142

Read status 3.

RYP

703042

Read Y register.

RPC

703062

Read program counter.

RXP

703102

Read X register.

SPSF

703001

Skip on STOP flag.

SPLP

703021

Skip on LIGHT PEN flag.

SPPB

703041

Skip on PUSHBUTTON flag.

SPEF

703061

Skip on EDGE flag.

SPDF

703101

Skip on any flag.

SPDI

703121

Skip on any interrupting flag.

SSLP

703141

SPES

703161

Skip

LSD

703004

Load and start display (Initializes. VTI15).

SIC

7030241

Set initial conditions.

STPD

703044

External stop display (XVM stops display).

RES

703064

Resume display after flag.

Skip on SLAVE LIGHT PEN flag (Multiplexer

with more than one VT04-370).

external

stop (Check

KF15 Power Fail Feature

SPFAL

703201

STPD

accomplished).

Skip, if POWER-LOW flag is set.

6-89

Table 6-4 (Cont)
Input/Qutput Transfer Instructions

Mnemonic Symbol

Octal Code

Operation Executed
VW01 Writing Tablet Control

WTCP

703221

Clear Pen Data flag.

WTRX

703222

Read X-coordinate.

WTSC

703224

Set tablet controls.

WTCD

703241

Clear Data Ready flag.

WTRY

703242

Read Y-coordinate.

WTMN

703244

Clear Set XY.

WTSK

703261

Skip on writing tablet flag.

WTRS

703262

Read tablet status.

WTSE

703264

Select tablet. .

KA1S Automatic Priority Interrupt Feature
DBK

703034

Debreak.

DBR

703344

Debreak and restore.

SPI

705501

Skip on priorities inactive.

RPL

705512

Read API status.

ISA

705504

Initiate selected activity.

ENB

705521

Enable breaks.

INH

705522

Disable breaks.

RES

707742

Restore.

RP1S5 Disk Pack Control
DPSF

706301

Skip on DISK flag.

DPOSA

706302

OR the Status register A into AC.

DPRSA

706312

Read the Status register A into AC.

DPOU

706402

gg the Unit Cylinder Address register into the

6-90

Table
6-4 (Cont)
Input/Output Transfer Instructions
Mnemonic Symbol

Operation Executed

Octal Code

RP15 Disk Pack Control (Cont)
DPRU

706412

Read the Unit Cylinder Address register into the
AC.

DPSA

706321

Skip on Attention flag.

DPOSB

706322

OR Status register B into the AC.

DPRSB

706332

Read Status register B into the AC.

DPLZ

706424

Load the accumulator zeros into Status register A

DPLO

706444

DPCN

706454

DPLF

706464

DPLA

706304

DPCA

706344

Load the Current Address register.

DPWC

706364

Load the Word Count register.

DPOA

706422

OR the cylinder, head, and Sector Address registers into the AC. AC bits 13 through 17 are ORed

bits 0 through 7 and execute.

Load the accumulator ones into Status register A
bits O through 7 and execute.

Execute the Function register.

Load the Status register A and execute.

Load the cylinder, head, and Sector Address registers from the accumulator.

with the sector.

Read the cylinder, head, and Sector Address regis-

DPRA

706432

DPOC

706442

'OR the Current Address register into the AC.

DPRC

706452

Read the Current Address register into the AC.

DPOW

706462

OR the Word Count register into the AC.

DPRW

706472

Read the Word Count register into the AC.

DPCS

706324

Clear status.

DPCF

706404

Clear Function register.

ter into the AC.

6-91

Table 6-4 (Cont)
Input/Output Transfer Instructions

Mnemonic Symbol

OctalCode

Operation Executed
RP15 Maintenance 10Ts

DPSJ

706341

Skip, if the JOB DONE flag is set.

DPSE

706361

Skip, if an error condition is present.

DPOM

706342

OR the six-bit Maintenance register into AC.

DPRM

706352

Read the six-bit Maintenance register into AC.

DPEM

706401

Execute maintenance instruction.

DPLM

706411

Leave Maintenance mode. The AC is left cleared.

LP1S Line Printe; Controls
LPSF

706501

Causes a skip request, if done or error is set.

LPPM

706521

Initializes the control, sets header; sets multiline.

LPPI

706541

Initializes the control, sets header; does not set
multiline.

LPRS

706542

Read status.

LPEI

706544

Sets the ENABLE INTERRUPT flip-flop.

LPDI

706561

Clears the ENABLE INTERRUPT flip-flop.

LPCD

706621

Clears DONE flag.

LPCF

706641

Clears STATUS and ERROR flag.

Line Printer Maintenance 10Ts
MRVFU

706502

Read VFU register.

MCVFU

706504

Clear VFU register.

MSM

706524

Set maintenance control.

MRDBI

706562

Read data buffer 00-17.

MCDB

706564

Clear data buffer.

MCM

706601

Clear maintenance control.

MRDB?2

706602

Read data buffer 18-35.

6-92

Table 6-4 (Cont)
Input/Output Transfer Instructions

Mnemonic Symbol

Operation Executed

Octal Code

Line Printer Maintenance IOTs (Cont)

MLDBI

706604

Load data buffer 0-17 from AC.

MRMI1

706622

Read maintenance word 1.

MLDB2

706624

Load data buffer 18-35 from AC.

MRM?2

706642

Read maintenance word 2.

MLS

706644

Load status.
CR15 Card Reader

CRSKP

706701

Skip on ready or trouble conditions.

CRLD

706702

OR data buffer to AC6-17.

CRCON

706704

Load initial conditions from AC13-17.

CRLS

706722

OR status to AC4-17.

CRPC

706724

Clear status except End of Card.

RF15 DECdisk Control
DSSF

707001

Skip on DISK flag.

DRBR

707002

OR the contents of the Buffer register with the AC.

DLBR

707004

Load the contents of the AC into the Buffer
register.

DSCC

707021

Clear the disk control and disable the ““freeze’’ status of the control.

DRAL

707022

OR the contents of the address pointer 0 (APO)
into the AC. Bits 0 through 6 contain the track
address, and bits 7 through 17 contain the word
address of the next word to be transferred.

DRAH

707062

OR the contents of the disk number (AP1) into the
AC. Bits 15, 16, and 17 contain the disk number.
Bit 14 is read back if a data transfer exceeded the
capacity of the disk control. (Causes a NED error
status.)

DLAL

707024

Load the contents of the AC into the APO.

6-93

Table 6-4 (Cont)
Input/Output Transfer Instructions
Mnemonic Symbol

Operation Executed

Octal Code

Line Printer Maintenance IOTs (Cont)

DLAH

707064

Load the contents of the AC (15, 16, 17) into the
disk number (AP1).

DSCF

707041

Clear the Function register, interrupt mode.

DSFX

707042

XOR the contents of AC bits 15-17 into the Function register (FR).

DSCN

707044

Execute the condition held in the FR.

DLOK

707202

OR the contents of the 11-bit disk segment address
(ADS) into the AC.

DGHS

707204

Generate simulated head signals.

DGSS

707224

Generate simulated disk signals.

DSCD

707242

Clear the Status register and DISK flag.

DSRS

707262

OR the contents of the Disk Status register with
the AC.

Type TC59 Magnetic Tape Control IOT Instructions

MTTR

707301

Skip on tape transport ready (TTR).

MTCR

707321

Skip on tape control ready (TCR).

MTSF

707341

Skip on ERROR flag or MAGNETIC TAPE flag
(EF and MTF).

MTAF

707322

Clear Status and Command registers and EF and
MTF in TCR.

LCM

707324

Inclusively OR content of AC0O-11 into Command
register.

MTLC

707326

Load content of ACO-11 into Command register.

MTCC

707356

Terminate write continuous mode.

707342

Inclusively OR content of Status register into
ACO-11.

MTRS

707352

Read content of Status register into ACO-11.

6-94

Table 6-4 (Cont)
Input/Output Transfer Instructions
Mnemonic Symbol

Octal Code

Operation Executed

Type TCS9 Magnetic Tape Control IOT Instructions (Cont)

MTRC

707312

MTGO

707304

Read Command register into ACO-11.
Set. “go” bit to execute command in Command
register.

TC1S DECtape Control

DTCA

707541

Clear Status register A.

DTRA

707552

Read Status register A.

DTXA

707544

XOR Status register A.

DTLA

707545

Load Status register A.

DTEF

707561

Skip on ERROR flag,.

DTRB

707572

Read status B.

DTDF

707601

Skip on DECtape flag.
AD15 Analog Subsystem

ADCV

701304

Load Status register from accumulator, clear A/D
done flag, and initiate conversion.

ADRB

701302

Read data buffer into accumulator and clear A/D
done flag.

ADRS

701342

Read Status register into accumulator.

ADCF

701362

Clear all ADI5 flags.

ADSF

701301

Skip on A/D flag.

WCSF

701341

Skip on word count overflow flag.

MSSF

701321

Skip on memory overflow flag.
UDC-15 Universal Digital Control

UMOD

701001

Set UDC mode.

USINT*

702004

Interrupt Select.

ULA*

702024

Load address.

6-95

Table 6-4 (Cont)
Input/Output Transfer Instructions

Mnemonic Symbol

Octal Code

Operation Executed

UDC-15 Universal Digital Control (Cont)

URA*

702012

Read deferred address.

URD*

702032

Read data in.

USCAN*

702021

Start interrupt scan.

USNB*

702041

Skip if not busy.

URCG

701072

Clear AC, read COS gates.

ULD

701064

Load data out.

ULPS

701044

Load previous status.

USI

701041

USD

701061

Skip on deferred flag.

URAA

701052

Read immediate address.

Skip on immediate flag.

AFC-15 Automatic Flying Capacitor

FCMOD

701021

Set AFC mode.

FCEI*

702004

Enable AFC interrupt.

FCDI*

702001

Disable AFC interrupt.

FCLAG*

702024

Load address.

FCRB*

702032

Read A /D buffer.

FCSD*

702041

Skip on A/D done flag.

FCRA*

702012

Read AFC Address register.
BD-15 Maintenance

MCLK

702044

Maintenance clock.

MSM

701004

Set Maintenance mode.

MCM

701022

Clear Maintenance mode.

*The UMOD IOT must be issued before these IOTs will be decoded as UDC-15 10T instructions.

*The FCMOD IOT must be issued before these IOTs will be decoded as AFC-15 IOT instructions.

6-96

Table 6-4 (Cont)
Input/Output Transfer Instructions
Mnemonic Symbol

Operation Executed

Octal Code

BD-15 Maintenance (Cont)
MLS

701024

Load Status register.

MRS

701012

Read Status register.

FCCV

702021

A /D convert.

Standard API Channel /Priority Assignments
Table 6-5 lists the channel number, priority level, and the address of options used on the XVM.
Table 6-5
Standard API Channel /Priority Assignments

Channel
0
1
2
3

4
5
6
7
8
9

10
11
12
13
14

Device
Software Priority
Software Priority
Software Priority
Software Priority

DECtape
Magtape
Graphics
Not assigned
Paper Tape Reader
Clock Overflow
Power Fail
Not assigned
Display

Card Reader
Line Printer

Option Number

Priority

Address

4
5
6
7

40
41
42
43

PCl15
KWI15
KF15

VT15A/VP15

LP15

ADI15/ADF15
DBO09A

0
3

TCI15
TCS59
VTI5B

CRI15

1
1
2
1
2
3

44
45
46
47
50
51

1S
16

A/D
DB99A/DB98A

Not assigned

18
19
20
21
24
25
26
27

Dataphone
Disk
Disk
Plotter
Terminal Control
Terminal Control
Terminal Control
Writing Tablet

DPO9A
RF15
RP15
XY15
DCO1-ED No. 1
DCO1-ED No. 2
DCO1-ED No. 3
VWO1-B

2
1
1
2
3
3
3
3

62
63
64
65
70
71
72
73

30
31

Terminal Control
Dataphone

DCO1-ED No. 7
DP09*

3
2

76
77

28
29

Terminal Keyboard
Terminal Printer

LT19/LTI15A
LTI9/LTI15A

*Channel allocated for systems with more than one of the above options.

6-97

3
3

57
60

74
75

IOT Device Selection Codes

Table 6-6 lists the IOT selection codes for devices used with the XVM.

Table 6-6
IOT Device Selection Codes
00 1 RT Clock
2 Prog
Interrupt

10 AFC-15

20 AFC-15

UDC-15

30 VT15-A

Line 1,2,3,4

BD-15

Printer or

4 RT Clock

01 PC15

40LTI19

70 RF15

AALS

52 CA1S

72 RF15

53 CAlS

63 RP15

73 TC59

54 CAlS

64 RP15

55 KA1S

65 Line

75 TC15

LTI15A

11 NPO2

31 VTI5-A

41 Line 1,2,3,4

Keyboard or
LT15A

02 PC15

03 1 Keyboard
2 Keyboard

12 NH14CR

13 ADI15

22 DBO9A

32KF15

42 Line 5,6,7,8

VW0l

Printer

33133KSR

43 Line 5,6,7,8

Skip

Keyboard

ADF15

2 Clear

4 IORS

All Flags
4 DBR, DBK

24 XY 15

04 Console

34 VT15-B

44 Line 9,10,
11,12

Printer

25 DPO9A

05 VPI15A, B,

35 VT15-B

45 Line 9,10,

BL,CL

26 DP0O9A

06 VPI15A, B,

BL,CL

17 Memory

Printer

Keyboard

LP15

46 Line 13,14,

BL, CL

07 VP15A, B,

11,12

66 Line

Printer

LPI1S

47 Line 13,14,
15,16

Management

15,16

Keyboard

67 CR15

76 TC15

77 61 Skip on

Bank Mode
62 Disable
Bank Mode
64 Enable
Bank Mode

6-98

Reader’s Commen
XVM SYSTEM MAINTENANCE MANUAL
EK-15XVM-OP-001

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