Digital PDFs

EK-1184A-MG-001

November 1986

157 pages

Original

5.6MB

view download

OCR Version

5.1MB

view download

Document:	PDP-11/84 System Maintenance Guide
Order Number:	EK-1184A-MG
Revision:	001
Pages:	157
Original Filename:

OCR Text

EK-1184A-MG-001

PDP-11/84 System
Maintenance Guide

dlilglilt]all}

EK-1184A-MG-001

PDP-11/84 System
Maintenance Guide

Prepared by Educational Services

of Digital Equipment Corporation

First Edition, November 1986

The material in this document is for informational purposes and is subject to change without notice: it
should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document.

Notice: This equipment generates, uses, and may emit radio frequency energy. The equipment has been
type tested and found to comply with the limits for a Class A computing device pursuant to Subpart J of
Part 15 of FCC Rules, which are designed to provide reasonable protection against such radio frequency
interference when operated in a commercial environment. Operation of this equipment in a residential area
may cause interference in which case the user at his own expense may be required to take measures to
correct the interference.

The manuscript for this book was created using generic coding and, via a translation program, automatically typeset. Book production was done by Educational Services and Publishing in Marlboro, MA, and
Educational Services Media Communications Group in Bedford, MA.

The following are trademarks of Digital Equipment Corporation.

lilaliltall

IAS

DIGITAL
EduSystem

OMNIBUS
0S/8

DEC
DECnet
DECUS
DECsystem-10
DECSYSTEM-20
DECwriter
DIBOL

LA
LETTERPRINTER 100
LETTERWRITER 100
LSI-11
MASSBUS
MICRO/PDP-11
MINC-11

PDP

PDT
RSTS
RSX
TOPS-10
TOPS-20
UNIBUS
VAX

VMS
VT

CONTENTS

Page

o
-

otk

CHAPTER 1

GENERAL SYSTEM SPECIFICATIONS

INTRODUCTION .....oiiiiiiitiiiieteeeeee
et
SYSTEM SPECIFICATIONS ..ot
PRODUCT VARIATIONS ..ottt
RELATED DOCUMENTS. ......ooii et

CHAPTER 2

DIAGNOSTIC AND TROUBLESHOOTING AIDS

2.1

INTRODUCTION ..ottt
GENERAL TROUBLESHOOTING NOTES ......c.cooooteteeeeeeeeeeeeeeeeeeeeeernns

2.2
2.3
24

2.4.1

24.2
243
2.5

2.5.1

2.5.2
253

2.5.4
2.5.5

2.5.6
2.5.7
2.6

2.6.1

2.6.2
2.7
2.7.1
2.7.2

2.7.3

DIAGNOSTIC TYPES ..o

CONSOLE TERMINAL ERROR MESSAGE FORMAT.....c.ooveoveeeeeeeeen
Console Error Message Description ............ccoovvvoveeeeeeeeeeeeeeeeeeeeeeeeeeern,
Unexpected Trap and MMU Error Code Descriptions..........c.ecveveeveeeenn....
Boot Program Error Codes/MeSSAgES ..........ccocvveeeeeeeeeeeeeeeeeeeeeeeeeeenenenn,
SYSTEM TROUBLESHOOTING AIDS ......oooo oo,
Front Panel........cocooiiiiiiii
e,
MDM MOGUIE ..
et
o
e e
KDJT1-BF/BC MOQUIC ......cviuiieiieiiiiiieeeceee
et
MSV11-JB/JC Memory Module ............coooemoeeeeeeeeeeeeeeeeeeeeeeeeeeee,
MSVI1-R Memory Module..........c..c.oovovvieiieiiieieeeeeeeeeeeeeeeeeeeeeeee
e,
KTJT1-B MOQUIE....c..coiiiiiiiiiiiiececee
e,
Minimum Load Module .............coovviiiiiiiiiieeceeeeeeeeeeee e,
JIT MICRO ODT ..ottt
e,
ODT Command NOES..........coeiiieiiiiieieeeceeeee
e,
ODT Command EXamples.............cooviiiiimineeieieeeeeeee oo
DIALOG MODE COMMAND DESCRIPTIONS .....oooooooteeeoeeeeeeeeeeeeeen,
HELP Command ........ccooooiiiiiiiiiiiec
et
BOOT Command ........coocuoiiiiiiiiiiiiociiis oo
LIST Command .........ccccooiiiiiiiiiiieeececeeeeeeee e,

1i1

1-1
1-4
1-8
1-8

2-1

2-1
2-2

2-3
2-3
2-9
2-10
2-11
2-12
2-12

2-15
2-16
2-18
2-21
2-21

2-22
2-24
2-24
2-25
2-26

2-27
2-28

CONTENTS (Cont)
Page

REMOVAL AND REPLACEMENT PROCEDURES

FIELD REPLACEABLE UNITS ...t 3-1
GENERAL MODULE REMOVAL/REPLACEMENT ... 3-3
CPU MODULE REMOVAL/REPLACEMENT ... 3-3
POWER SUPPLY REMOVAL/REPLACEMENT ... 3-5
Cabinet Power Supply Removal/Replacement ... 3-5
s 3-8
Box Power Supply REMOVEA] v.oiiiiiiiiiiii
. 3-10
.
.
MENT
CABINET BLOWER REMOVAL/REPLACE
3-11
.
.
.
BOX FAN REMOVAL/REPLACEMENT
3-12
.,
..
MENT
FRONT PANEL REMOVAL/REPLACE
3-12
in.
iiiiiii
..cooov
.......
ement..
Cabinet Front Panel Removal/Replac
3-13
o
.
.
ement
Box Front Panel Removal/Replac
3-14
.
..
MENT
PLACE
CIRCUIT BREAKER REMOVAL/RE
3-14
e
ooniiin
...cccc
.......
ement..
/Replac
Cabinet Circuit Breaker Removal
3-15
iii,
vvviiii
.ccoooo
.......
ement
Box Circuit Breaker Removal/Replac
3-16
...........
T
ACEMEN
L/REPL
REMOVA
CABINET POWER CONTROLLER
3-18
.....
...............
MENT
PLACE
AL/RE
SLU INTERFACE ASSEMBLY REMOV
3-18
.
.
.
Cabinet SLU Assembly Removal
3-20
.
.
.
ent..
Replacem
Box SLU Assembly Removal/
CPU BACKPLANE REMOVAL/REPLACEMENT ... 3-21
Cabinet Backplane Removal ..., 3-21
Box Backplane Removal/Replacement..........oooooiiiiii 3-24
CABINET BBU REMOVAL/REPLACEMENT ... 3-25
BOX BBU REMOVAL/REPLACEMENT ... 3-27
CABINET PERIPHERAL ACCESS ..ot 3-29

o —

o
=

PLOR——— OO0

CHAPTER 3
wwwwwwwwwwwwuwwwwwuuowwwu

SETUP COMMANG .ottt 2-28
SETUP Command 1 ...ooooiiiiiiiioii oo 2-30
SETUP COmMMANA 2 oot 2-30
SETUP Command 3 ..ooooeeeee oottt 2-32
SETUP Command 4 ....ooveeeiiiiieiiie et 2-32
SETUP COmMMANd 5 .ot 2-33
SETUP COmMMANA 6 ..ot 2-33
SETUP COmMmMAnd 7 .oeeeeeeeee et eeeseiiieee e 2-34
SETUP Command 8 ...oeeeeeiiiiiiiiiiite et 2-34
SETUP Command 9 .ovveeeeieiiiiiiieie e 2-35
SETUP Command 10 ..o 2-36
SETUP Command 11 .ooeeeiiiiiiiiiiiie e 2-36
SETUP Command 12 ..ocoviiiiiieiiieeee e 2-37
SETUP Command 13 ..oeeeiiiiiiiiiiiee et 2-38
e 2-39
SETUP Command 14 ..oooooriiiiiiiiiiie
SETUP Command 15 .ot 2-39
e et e et ete e e et e e sb e s e e 2-41
MAP COMMANG ... ittt
TEST COommMAaNnd .....ooooouviioiiiieiiieeeeieee e e 2-42

CONTENTS (Cont)

Page

CHAPTER 4

SYSTEM REGISTER DESCRIPTIONS

4.1

PAGE ADDRESS REGISTERS (PAR) .....ooooivieeeeeeeeeeee oo

4-1

MEMORY MANAGEMENT REGISTER O......coooveoioioieeeeeeeeeeeeeeeeeee

4-3

4.2
4.3

4.4
4.5
4.6
4.7

4.8
4.9
4.10
4.11
4.12

4.13
4.14
4.15
4.16
4.17

4.18
4.19
4.20

4.21
4.22

4.23

4.24
4.25
4.26

PAGE DESCRIPTOR REGISTERS (PDR)........coooveiiieeeeeeeeeeeeeeeeeeee

MEMORY MANAGEMENT REGISTER 1 ......ccooveoioieieeeeeeeeeeeeeeeee
MEMORY MANAGEMENT REGISTER 2........oooiotoieeeeeeeeeoeeeeeeee
.

MEMORY MANAGEMENT REGISTER 3.......coooooioioeeeeeeeeoeeeeeeoee
KDJ11-B CACHE REGISTERS - DATA ORGANIZATION........ccoooveveee

CACHE CONTROL REGISTER .......coovoiiiiiiieieeeeeeeeeeeeeeeeeeeeeeeeee
e,

MEMORY SYSTEM ERROR REGISTER ........cc.coeoiiteemeeeeeeeeee oo
HIT/MISS REGISTER ..ottt

PROCESSOR STATUS WORD........c.ooviiiiiieeeeeeeeeeee
oo
PROGRAM INTERRUPT REQUEST REGISTER .....cocoveoeeveeeieeeeeeeeen]

CPU ERROR REGISTER ..ottt
CONFIGURATION AND DISPLAY REGISTER .....oooooveeteeeeeeeeeeere,
MAINTENANCE REGISTER .........cooiiiiiiiiieeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeev
BOOT AND DIAGNOSTIC CONTROLLER REGISTER .....ccoovovevevivenn

PAGE CONTROL REGISTER ......c.coooviiiiiiiiieeeeeeeee
e,
LINE FREQUENCY CLOCK STATUS REGISTER.......ccoooveeeeeeeeeeeeee,

RECEIVER STATUS REGISTER ........c.cooiiiiieeeeoeeeeeeeeeeeeeeee oo
RECEIVER DATA BUFFER .........coooiiiiiiieeeeeeeeeeeeeeeeeeeeeeeeeeeeees
e,
TRANSMITTER STATUS REGISTER .......cooevoiiioeeeeeeeeeeeeeeeeeeeeeeeeeeeeen
TRANSMITTER DATA BUFFER REGISTER.........cccooteoteeieeeeeeeeeeeeeeeenn

UNIBUS MAPPING REGISTERS..........cooooiiiiiioe
e
OPTIONAL UNIBUS MEMORY ......ooiiiiiiiiiioeee et

MEMORY CONFIGURATION REGISTER

.....cocoooeoeiieeeeeeeeeeeeeeeeeeren.

DIAGNOSTIC CONTROLLER STATUS REGISTER .....cooovoeeeeeeeeie

4-1

4-4
4-4
4-5
4-5
4-7

4-9
4-11

4-12
4-13

4-14
4-14
4-15
4-17
4-19

4-20
4-21
4-21

4-22
4-23

4-24

4-25
4-26
4-30

4.27

DIAGNOSTIC DATA REGISTER ..........coooiiiiieeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee,

CHAPTER 5

OPTION INSTALLATION PROCEDURES

5.1

EXPANSION POWER SUPPLY INSTALLATION.......coocvvimeeeeeeeeerernn,
EXPANSION BACKPLANE INSTALLATION ....ooovetoteeeeeeeeeeeeeeeee,

5-3

NPG and BG Jumper ROUtING.........coocvvviiiieieeeeeeeeeeeeeeeeeee
e
ee

5-6

5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.3.1
5.3.2
5.4
5.5

Backplane Installation Procedure..............ccoooooovvioveimoneeeeeeeeeeeeeeeeee

Backplane Power COnNeCtions ...............ccocoevivveieveereeeeeeeeeeeee oo,
SPC Backplane Locations ..............cc.ocvvviveieiiieeeeeeeeeeeeeeeeeeeeeeeeeeeeeees
e,

SPC MODULE INSTALLATION .......ooiiiiiii oo
Cabinet SPC Cable ROUtING ..........c.oooviiiiiieicee

BACKPLANE PIN ASSIGNMENTS

APPENDIX B

WORKSHEET

5-4
5-8
5-10
5-10
5-12

5-14

oo,

5-18

CABINET BBU INSTALLATION .......oiiiiiioeoeeeeeeeeeeeeeeeeeeeeeeeeeeeesenens

APPENDIX A

5-1

oo,

Box SPC Cable ROUING .......cooviiiiiiiicceceee
BOX BBU INSTALLATION.......ooiiiiiiiiit

4-31

5-15

FIGURES
Figure No.
1-1

— O
DN AW

ot ot
pod
d

O 00~

52
12 (2 12
o) ek ek ek e pd

NS I O T N5 I\ ) o

O oo ~1N

Vo1

—

1-2

Page

Title

Basic Cabinet Hardware COMPONENES ........coovriiiiiiimmiiiiiiiiinanie s 1-1
Basic Box Hardware COMPONENLS ....c..occuiiriiiiiiiiieiiaiiisisais st 1-2
2-3
Error Message Display Example ... 2-10
Unexpected Trap Error EXample ..o 2-10
e
Example of Test EITOT .c..viiiiiiiiieiii
iii 2-10
ooi
oco
...
...
...
EXample
Boot Program Error
Boot Error Message EXample.......ocooviiiiiiiiii 2-11
Automatic Boot Error Message EXample ... 2-11
System Front Panel ..o 2-12
iiii 2-13
s
MDM Module LED LaYOUL ....oiviiiiiiiiiiiiiiiieieiiee
s 2-14
MDM MoOAUIE LaYOUL ....oviveiiieniitiiinieie
KDJ11-BF/BC Jumper and Switch Pack LoCations ... 2-15
2-16
MSV11-JB/JC LED/Switch Pack/Jumper Layout ..o
2-19
ines
iiniiii
MSV11-R Switch Pack and LED LoCations .........cccovviviiii
2-21
t
KTJ11-B ROM Socket LOCAIONS ....veveiieieiiiiiiiiiiieniieeniiees i
2-22
s
iiiii
Minimum Load Module Layout.......cccceoiiiiiimiiii ii 2-24
s
iii
/ (Slash) Command EXample........coo
LINE FEED Command EXample......ccovviiiiiiiiiiiiiiieiiiii 2-24
GO Command EXAMPLE .....c.ooiririiiiiiiiii e 2-24
2-25
PROCEED Command EXample ......ccoooveviiiiiiiiiiiiiiii e 2-25
i
iein
s
Dialog Mode COMMANGS .........oooviimririiiii
HELP Command DISPlay.........cccvrieiioiiimiiiiiiei i 2-26
DL2 B0t EXAMPIE .....oiiiiitiiiiiiiiiiiiiiie e 2-27
eieieii 2-28
LIST Command DISPIay.......ccvererieriiiiiiiiiiiie
iinisi 2-29
s
inieni
SETUP Command DeSCIiPioNs.........ccoeiiiiriiiiiin
2-30
t
Short Command MESSAZE ........ooveruerreeriiriiiiieiiiee e
SETUP Command 2 Example. ... e 2-31
SETUP Command 3 EXAMPIE.....ccoooiiiiiiiiiiiiiiii i 2-32
SETUP Command 4 EXample ... .coooooiiiiiiiiii i 2-33
SETUP Command 6 EXaMPIE.....coovrieriiiiiiiiiiieeisisis 2-34
SETUP Command 8 EXamPIE.....ccoovieriiniiiiiiiiiieieii 2-35
i 2-35
SETUP Command 9 EXample.......cocoviioiiiiiiiiii
SETUP Command 10 EXAMPLE.....coorieiiiiiiiiiiriiiiiiis 2-36
2-36
SETUP Command 11 EXAMPLE.....ooiiiiiiiiiiiiiiiiicniiiii
2-37
ci
iiiiii
iienii
SETUP Command 12 EXampPle......ocverviiiiiiiiii
2-38
i
e
iiiii
iiiii
SETUP Command 13 EXamMPIE.....coceoiiiiiii
2-39
o
SETUP Command 14, EXample 1 ..
2-39
iiis
iiii
iiii
SETUP Command 14, EXample 2 ..cooooviiii
SETUP Command 15 EXample....c.oooeiiiniiiiiiiiiiiiiin i 2-41
MAP Command DISPIAY ....coveeeuerueiiiiriir i 2-42
TEST Command EXample .......ooovieriiiiiii i 2-43
e 2-43
Loop-0n-Test EXAMPE......coviiiiiririiiiii

Title
Blower Assembly Removal..........c..ccooiviiioeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee
Cabinet Power Supply Removal.............ocoooviioiieeeeeo e,
Power Supply Regulator Removal..............ocoooooieonioeiieeeeeeeeeeeeeeeeeeeee,
Power Supply Removal ........coc.ooviiiiiiiiiiiiccce
e,
Power Supply Regulator Removal .............ccooooiiiiiieoeeeeeeeeeeeeeeeeeee,
Blower Assembly Removal...........ccoocooviiiiiiiiiiieeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeo
Box Fan Removal ........cccooiiiiiiii
e

NO OO ~I AN WL

—

-h-h-h-lk-llk-h-&-h-b

wwwwwwwtr)wwwwww
L
D
MO RO PO PO LD MO :

NMBERWN—O
VRN
NHE W
— O

O OO0

ON D

KW N

—

Figure No.
o PP

FIGURES (Cont)

4-10

4-11
4-12

4-13
4-14
4-15

4-16
4-17

4-18

Page

Cabinet Front Panel Removal...............ooooeiiuioioieieeeeeeeeeeeeeeeeee
e,
Front Panel Removal...........cooooiiiiiii
ee
iiiicceeo
Cabinet Circuit Breaker Removal.............c.oooovooieeimoeoieeeeeeeeoeeeeoeee,
Box Circuit Breaker Removal ............coooooviiiiiioineeoe oo
Cabinet Side Panel Removal.............c..coooviiviiooieeoeoeeeeeeeeeeeeeeeeeeeee,
Power Controller Removal - Side VIEW ........ccooovoivoiiooooeoeeeeeeeeeeeeeee
Power Controller Removal - Rear VIEW .......c..ocvovioioeeeeoeoeeeeeeeeeeeeeeeeeis
Cabinet SLU Assembly Removal ...........c.ocoovevoieioeeeeeeeeeeeeeeeeeeeeeeeee
Box SLU Assembly Removal............cc.ccooviiiiiiiieeeoeeeeeeeeeeeeeeeeeeeee
e
ee
Side Panel Removal...........ccooviuiiiiuiiiiiieiceceeeeeeee e,
Cabinet Rear VIEW .......cociviiiiiiiiicceee
e
Cabinet Backplane Removal .............c.ocoooiiieioeeeeeoe oo,
Box Backplane Removal..............ooooiiiiiiiiiieeeee
e
Side Panel Removal..........ccooooiiiiiiiiicceeeeeeeeeeeee e,
BBU REMOVAL......ooiiiiiiiiiiici
e
Box Circuit Breaker LoCation............ccooiiiiiieeereeeeeeeeeeeeeeeeeeeeeeeeee
BBU Bulkhead Panel.............coooooiiiiiiiiiiceee
oo
Stabilizer Bar EXtENSION ........oviviiiiiiiiceeee oot
ee e
Page Address Register FOrmat.............ooooovviiiiiiiiiiiieeee e
Page Descriptor Register FOrmat.............cooooovvoniioieoeeeeeeeeeeeeeee e
Memory Management Register 0 Format ...............ocooiioviveeeeeeeeeeeeeeese
Memory Management Register 1 FOrmat ..............cocoooviviiiieneeeeeeeeeeeeeeeeee

Memory Management Register 2 Format ..............oocooeiiiiiiieeieieeeeeeeeeeeeeen,

Memory Management Register 3 FOrmat ........ccoevvveerieeneeieeeeeeeeeeeeeeee
CPU/DMA Physical Address Interpretation Register ...........oovevvveeeoveeereneeeennnn,
CPU Cache Tag Register FOrmat...........ccooooovviiiiiionieeeeeeeeeeeeeeeeeeee
e
DMA Tag Register FOrmat.......c..ccooooviiviiiiiiiiii
e
iicicceeeeee
e s
CPU Cache Data Organization................ccoovveviiieeiineeeseeeeee
e eer e eeesseeesens
Cache Control Register (CCR) FOrmat ........ocvovvveoeieeeeeeeeeeeeee oo
Memory System Error Register (MSER) Format..........cccocovoveeeiioeeeieeeeieseeernn
Hit/Miss Register FOrmat.........c.oc.ooviiiiioiei et
Processor Status Word Register (PSW)......oooviooiiiieeeeeeee
e
eeee s
Program Interrupt Request (PIR) RegiSter .........c.ooovviuiieeerieeieeeeeeeeeeeeee
CPU Error Register FOrMAat ........cc.oovviiiiiiiiiiiiicee et
Boot and Diagnostic Configuration Register Format..........ccccccovvevvevvvvvveseeenan.
DiSplay REGISIET.....c.eiiiiiiiiiieiiciiie
ettt et et e e neaaeas

vil

3-5
3-6
3-7
3-8
3-9
3-10
3-11

3-12
3-13
3-14
3-15
3-16

3-17
3-18
3-19
3-20

3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29

4-1

4-1
4-3
4-4
4-4
4-5
4-5
4-6

4-7
4-7
4-7
4-9

4-11
4-12
4-13

4-14
4-14
4-15

FIGURES (Cont)

Page

Title

4-33

Maintenance Register FOrmat ... 4-15
Boot and Diagnostic Controller Register Format ... 4-17
Page Control Register FOrmat ..o 4-19
Clock Status Register FOrMat.......cocoiiiiiiiiiiiii 4-20
Receiver Status Register FOrmat .........oooooiiiinii 4-21
Received Data Buffer Register Format ..o 4-21
Transmit Status Register Format. ... 4-22
Transmitter Data Buffer Register Format..........cooooiii 4-23
i 4-24
Hi-Address Register FOrMat......oooioiiiiiiiiiiiiii
iiiii 4-24
s
iiiii
Lo-Address Register FOrMAat ......co.coiiii
i 4-26
iiiiii
iiiiii
Memory Configuration REISTET.........oi
4-27
e
Status Select = 0 Field FOrmat....ooooiiiiiiiiiie
4-28
e
Select Status = 1 Field FOrmat......ooooiiiiiiiiee
Diagnostic Controller Status Register Format...........cooin 4-30
Diagnostic Data Register FOrmat........ooooiiiiiis 4-31

AR AR A A A A A A A A
> > UI(J\(J‘I(J’I&IIYIKI\MUIK!\U‘I(J\
O 00~ N
B Wb—
N
N

Figure No.

Expansion Power Supply Installation ..o 5-2
Expansion Backplane Slot ASSIZNMENTS ..ot 5-3
Expansion Backplane MOUNtING ..o 5-5
iii 5-7
s
NPG Jumper Leads ROULING. ........ccooiiiiiiii
iiii 5-8
iiiiiii
..ooovi
Backplane Connector Designations.........
5-11
t
SPC Module INStAllAtION ......ccoovviiiiiiiiee e
5-13
i
iiieiiiiiii
Cabinet SPC Cable ROULINE .....oovvrriiie
5-14
i
ieieie
iiaiieiiie
Box SPC Cable ROULINE.....coviiiie
5-15
t
o
BBU Front Panel. . . .co oue o o eie o
5-15
t
t
t
BBU REar Panel. . .o oe e e e oo
Side Panel RemoOval. oo e 5-16
Mouniing ihe BBU ..o 5-17
BBU FIrONt Panel. . . o eo e e e e ie e oottt 5-18
BBU REAT PaAnel ...t 5-19
Circuit Breaker LOCAtION ......coovviieiiiiie ettt 5-19
Top Cover RemOVal ... 5-20
t 5-21
e st
BUIKREAd LOCAION ...eveeeeeeeee ett
5-22
t
e
c
iiiiiiiiieiiii
BBU Connector PAnel ..........ooii
5-23
iiee
eeeniii
e
s
eiiiirnre
iiiriee
e
iiieeii
..uvvii
...
BBU Cables and LOCAtIONS.
5-24
t
t
t
o
BBU REAT PANEL . .ooeoeeeoeeeeee o
A-1
i
e
iiinniii
rieminii
cooiviei
........
TS
SPC Backplane Pin ASSIZNIMEN
A-2
viininiinn
.ccoccovie
s.........
Assignment
Pin
Backplane
Standard and Modified

4-19

4-20
4-21
4-22
4-23

4-24

4-25

4-26
4-27
4-28

P Yo Re 0N I

NNV, I

pod

R U I (W BLC i a)

4-29
4-30
4-31
4-32

viii

TABLES

okt
ek
ek
bk
et

—

t 1

—t

O OO0 ~1ION L BN
—

Table No.

Title

Page

Basic A-Series COMPONENLS.........cc..o
e
vviiuiiieiii
e
eiiie
Cabinet Environmental Specifications.............c.oeveoeeeeeeeeeeeeeeer oo,

Cabinet Mechanical SpecifiCations..............ccoveuvouieeeneeeeeeeee
e eeeeee e,
e

1-3

1-4
1-4

Cabinet Electrical SpecifiCations.............ccooviviiiiieeeeeeeee
e oo,
eeee
Box Environmental SpecifiCations...............c.ocoviiiiieioeieeeeeeeeees oo

1-6

Box Electrical SpecifiCations .............cc.cooviiiiiiieeeeee

1-7

Box Mechanical SpecifiCations ................ocvoouieiiiiiieeee oo,

A-Series Product Variations ............ccooviiiiiiieeeeeeeee e,
PDP-11/84 Related DOCUMENTS..........ccveree
e oo,
eeeeeeeeeeeeee

1-5
1-6

1-8

Error Codes, Test Descriptions, and Probable Causes...........oc.vovvvvovvoovooeooeon,
Startup Diagnostic Error Message Descriptions..........o.veeeeveeveeeeeeeoeeeeeeeeenn,
Power Supply Regulator Fault ISOIation .............cccooveveeeeemeeeeeeeeeeeeeeeeeeee,
MSVI11-JB/JC Starting Address...........c.ooveiiii
oo
eieeeeeeeee
eeeeeseeee s,

2-12
2-17

MSV11-JB/JC Jumper Configurations.............cc.eoveeveeeeoeeeeeeeeeeeeeeeerseeseerees
e,

2-18

MSVI11-JB/JC CSR Address SeleCtions..........eeoevemeee
oo eeeeeeeeeeeeeeeeeeeeeo,
eeeeeeeee

2-5
2-9

2-18

MSV11-R Starting Address SeleCtion.............c.coveveeeieeeeeeeeeeeeeeeeeeeeeee
oo,
MSVI11-R CSR Address SeleCtion..............coviieeeereerieeeeeeeeeeeeeeeereeresees
e,
J11 Micro ODT Command SUMMATY ......cooovvveveieieeeeeeeee
oo e,
eee
ROM ODT COommands ..........c..cooiiiiriiiii
et ieieeeeeeeeee
e e e eee e,

2-20
2-20

P-Series FRU DeSCIIPLIONS .......c.eovviuiiiieiiiiee
e
eeeeteeeee
e e ee
A-Series FRU DESCIIPUONS ......c.vivveviiviieeiieieeeee
e
eeeeeeeeee
eee e,

3-1

Page Descriptor Register Bit DesCription.........co.eevvveeeeeeeeeseeeeeeee oo,
Memory Management Register 0 Bit Descriptions...........coveeveeveeeecevveeereereeseenennn,
Memory Management Register 3 Bit DesCriptions.........coocoeeecevieeveeeeereereeeeereennn,

4-2

CPU/DMA Physical Address Interpretation Bit Descriptions..........ccccveveveveennn...
Cache Control Register Bit DeSCIPLONS ..........cccoeveeeieeeeeseereeeeeeeereeee
e,
s
Cache Parity Errors During CPU CYCIES ......cvooveveeeieeeeeeeeeeeeeeeeeeeeeeeeeeeeereon,
Cache Parity Errors During DMA CYCIES........ccooovvemieeeeeeeeeeeeeeeeeeeeeeeeeereenns
Memory System Error Register Bit Descriptions ..........ccoocvveveeeeeerveeeeeeeeesreen,
Hit/Miss Register Bit DeSCIPLONS ...........ccooveiereeeeerei
oo eeeeeeer e e eereeee
e,
Processor Status Word Bit DesCriptions.............c.ooveeveeerereeeeeeereeeeeeeeeeeeesseens
Program Interrupt Request Register Bit Descriptions.............ccooeeveevvvevcvereerennnn.
CPU Error Register Bit DeSCriptions.............ccoeiovievevereeieeereeeeeeeeeeeeees
e e,
Display Register Bit DesSCriptions..........c..coeiiiiiiiiieeeeceeeeeeee
et
ev
e
Maintenance Register Bit DeSCriptions ..............ccooooiiveoiiveneeeeeeeeeeeeeeee
e,
eeee

2-23

2-40

3-2

4-3
4-5

4-6
4-8
4-9
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16

TABLES (Cont)
Table No.
4-15
4-16

4-17
4-18

4-19
4-20
4-21

4-22
4-23

4-24

4-25
4-26
4-27

4-28

Title

Page

Boot and Diagnostic Controller Register Bit Descriptions.............cocooiiieninens
Page Control Register Bit Descriptions............ocoooiiiii
Clock Status Register Bit DeSCriptions ...........ccoiiiiiiiiiiiiiiiii
Receiver Status Register Bit DesCriptions...........ccccoooiiiiiiiiiinii
Received Data Buffer Register Bit Descriptions............ccooiiiiiiiiiiiniiiiinnens
Transmit Status Register Bit Descriptions ..........c.ccooovviviiiiiiiii
Transmitter Data Buffer Register Bit Descriptions ..........cccocoiiiiin,

4-17
4-20
4-20
4-21
4-22
4-23
4-23

e
UNIBUS Map Register Pairs .........cooiviiiiiiiiiiiiiiii
Register Selection of UNIBUS MemoOry .....c.ccoocoiiiiiiiiiiiiiiiiiii
i
Memory Configuration Register Bit Descriptions...........cccccocciiiiiiiiiiiiniinn
Status Select = 0 Field DeSCription ..........ccoiieiiiiiiiiiiiieiiiiecie
e,
Select Status = 1 Field DeSCription .........ooovviiioiiiiiiiiiiceicceceee
e
Diagnostic Controller Status Register Bit Descriptions .............ccoooiiiiiiinnn
Diagnostic Data Register Content Descriptions.........c.cccccovviiiiiiiiniiiiiiiinn

4-24
4-25
4-27
4-28
4-29
4-30
4-31

DDI11-CK Power Connector Signal ASSIZNMENtS .......ccccovvviiiiieeeiiiiniiiinienininnine.
DD11-DK Power Connector Signal ASSIZNMENtS........cccoovvviviiiiiiiiiiiiinieniiininnnn,

5-9
5-9

SETUP Command 2 ...ttt
SETUP Command 3 ......oooviiiiiiiiiiiieit ettt
s
SETUP Command 4 ........oooriiiiiiiiee ettt
SETUP Command 5 ...ttt et
SETUP Command 6 ......c..ovviiiiiiiiiiice ettt

B-2
B-3
B-4
B-5
B-6

CHAPTER 1

GENERAL SYSTEM SPECIFICATIONS

1.1
INTRODUCTION
The major cabinet and box components are shown in Figures 1-1 and 1-2. Table 1-1 briefly describes the

basic A-series system components. Table 1-2 specifies the module revisions and options used with P-series

systems.

POWER CONTROLLER

—MODULE COVER

POWER SUPPLY
CIRCUIT BREAKER

CARD
CAGE

MAIN POWER SUPPLYTM ~_
BLOWER
MR-14332

Figure 1-1

Basic Cabinet Hardware Components

1-1

IMPORTANT

After replacing a KDJ11-BF CPU module, reset the
Set-up feature selections of the replacement module
as recorded on the Set-up Parameter Worksheets.
The worksheets should be stored with the system
documentation.

If the worksheets are not available, fill in the worksheets (contained in Appendix B) as specified by the
customer. Remove the worksheets from the appendix and store them with the system documentation.

POWER SUPPLY

SCREWS (4)

L
A\t
LN
\ NN
L

=4 A\

/‘\ =

—\/ ¢

FRONT BEZEL

MR- 14331

Figure 1-2

Basic Box Hardware Components

1-2

Table 1-1

Basic A-Series Components

Component (Part Number)

Description

KDJ11-BF (M8190-AE)

CPU - FPA module

KTJ11-B (M8191)

UBA module

MSVI11-JB (M8637-BA)

1 Mbyte ECC memory module

MSVI11-JC (M8637-CA)

2 Mbyte ECC memory module

Terminator (M9302)

UNIBUS terminator module

MDM (M7677-YA) *

Monitor and distribution module

Load module (M7556)

Minimum load module

877-D

Cabinet power controller 120 Vac

877-F

Cabinet power controller 240 Vac

H7202-KA

Main backplane power supply

H7202-KB

Expansion backplane power supply

54-16508-01

Console serial line board

70-20650-01

CPU backplane assembly

70-21888-01

Front panel assembly

12-22001-01

Cabinet blower

12-22271-02

Box fan

Options
H7231-E

Cabinet battery-backup unit

H7231-F

Box battery-backup unit

DDI11-CK

4-slot backplane

DDI11-DK

9-slot backplane

* M7677-YA must be installed if the system contains the H7231-E BBU option.
The following list specifies the P-series module revisions, and the supported and unsupported options.
KDJ11-BC (M8190), CPU module (no FPA)

MSVI11-RA (M7458-A), 1 Mbyte parity memory module
M7677 MDM module

DDI11-CK 4-slot backplane (supported option)
DDI1-DK 9-slot backplane (supported option)

1-3

1.2

SYSTEM SPECIFICATIONS

The following tables list the PDP-11/84 system specifications. Table 1-2 through Table 1-4 list the cabinet
specifications: Table 1-5 through Table 1-7 list the box specifications.
Table 1-2

Cabinet Environmental Specifications

Characteristic

Description

Temperature

Operating

10°C - 40°C (50°F - 104°F)

Nonoperating

—40°C - 66°C (—40°F - 151°F)

(storage)
Humidity

10% to 90% with maximum wet bulb temperature 28°C (82°F) and a

Operating

minimum dew point 2°C (36°F) noncondensing.

Vibration

Operating

5 Hz to 22 Hz: 0.01 in DA; 22 Hz to 500 Hz
0.25 Gpk. Sweep rate of 1.0 octave/min. All three axes.

Nonoperating

Vertical axis random vibration: 1.4 Grms overall from 10 Hz to

(packed for

200 Hz; duration: 1 hr each axis.

shipment)
Altitude

Operating

0 to 2.4 km (8000 ft)

Nonoperating

9.1 km (30,000 ft)

Maximum operating
with altitude

Maximum operating (40°C) should be reduced 1.8°C/1000 m
(1°F /1000 ft) above sea level.

Shock
Operating

10 Gpk for 10 ms (+3 ms), '/2 sine wave, vertical axis only.

Nonoperating
(packaged for
shipment)

direction only).

Table 1-3

Flat drop from a 15.2 ¢cm (6 inch) height, three drops total (vertical

Cabinet Mechanical Specifications

Characteristic

Description

Height
Width
Length

105.7 ¢m (41.64 inches)
53.9 ¢m (21.25 inches)
76.2 cm (30 inches)

Weight (packed)
Weight (unpacked)

182.2 kg (401 Ib)
150.5 kg (331 Ib)

Table 1-4

Cabinet Electrical Specifications

Characteristics

Description

120 Vac operation

Line voltage

93 Vrms - 132 Vrms, single-phase, 2-wire and ground
(120 Vrms nominal)

Frequency

47.5 Hz - 63 Hz

Current (ac)

13.5 Arms maximum at 120 Vac

Power factor

Greater than 0.60 at full output load and low input voltage (93)

Startup current

100 A, 0.16 us duration

Inrush current

160 A (peak) maximum at 120 Vac, 0.16 us duration

Power

2880 V-A maximum*

Btu

2218

240 Vac operation

Line voltage

186 Vrms — 264 Vrms, single-phase, 2-wire and ground
(240 Vrms nominal)

Frequency

47.5 Hz - 63 Hz

Current (ac)

6.7 Arms maximum at 240 Vac

Power factor

Greater than 0.60 at full output load and low input voltage
(186 Vac)

Startup current

50 A, 0.16 us duration

Inrush current

160 A (peak) maximum at 240 Vac, 0.16 us duration

Power

2880 V-A maximum*

Btu

2218

Noise transient

(both line voltages)
High-energy transients

1 kV peak spike containing not more than 0.2 W of energy per spike

Conducted noise

CW-10 kHz to 30 MHz, 3 Vrms

* Including mass storage devices

Table 1-5

Box Environmental Specifications

Characteristic

Description

Temperature

Operating

5°C - 50°C (41°F - 122°F)

Nonoperating

—40°C - 66°C (—40°F - 151°F)

(storage)

Humidity

10% to 95% with maximum wet bulb temperature. 32°C (82°F) and

Operating

a minimum dew point 2°C (36°F) noncondensing.

Vibration

5 Hz to 30 Hz: 0.01 in DA 30 Hz to 500 Hz:

Operating

0.5 Gpk. Sweep rate of 1.0 octave/min. All three axes.

Nonoperating

(packed for

Vertical axis random vibration: 0.687 Grms overall from 10 Hz to
200 Hz; duration: 1 hr each.

shipment)
Altitude

Operating

0 to 2.4 km (8000 ft)

Nonoperating

9.1 km (30,000 ft)

Shock

Operating

10 Gpk for 10 ms (+3 ms), /2 sine wave, vertical axis only.

Nonoperating

Flat drop from a 15.2 cm (6 inch) height, three drops total (vertical

Maximum operating with

altitude

Table 1-6

direction only).

(1°F/1000 ft) above sea level.

Box Mechanical Specifications

Characteristic

Description

Height
Width
Length

26 ¢cm (10.44 inches)
47 cm (19 inches)
67.5 ¢cm (27 inches)

Weight (packed)
Weight (unpacked)

59 kg (130 Ib)
42.75 kg (95 Ib)

aVaVa

Table 1-7

Box Electrical Specifications

Characteristic

Description

120 Vac operation

Line voltage

90 Vrms - 132 Vrms, single-phase, 2-wire and ground
(120 Vrms nominal).

Frequency

47.5 Hz - 63 Hz

Current (ac)

8.0 Arms maximum at 120 Vac

Power factor

Greater than 0.60 at full output load and 120 Vac nominal input

voltage.

Startup current

50 A, 0.16 us duration

Inrush current

80 A (peak) maximum at 120 Vac, 0.16 us duration.

Power

650 W maximum

Btu

2218

240 Vac operation

Line voltage

180 Vrms - 264 Vrms, single-phase, 2-wire and ground
(240 Vrms nominal).

Frequency

47.5 Hz - 63 Hz

Current (ac)

5.0 A (rms) maximum at 240 Vac

Power factor

Greater than 0.60 at full output load and 240 Vac nominal input

voltage.

Startup current

50 A, 0.16 us duration

Inrush current

80 A (peak) maximum at 240 Vac, 0.16 us duration.

Power

650 W maximum

Btu

2218

Noise transient
(both line voltages)
High-energy transients

1 kV peak spike containing not more than 0.2 W of energy

per spike.

Conducted noise

CW-10 kHz to 30 MHz, 3 Vrms

1.3

PRODUCT VARIATIONS

Table 1-8 describes the A-serics system variations.
Table 1-8

A-Series Product Variations

Description

Variation

KDJ11-BF, MSV11-JB | Mbyte

11/84-AA

26.7 ¢cm (10.5 inch) box, 120 Vac

KDJ11-BF, MSV11-JB | Mbyte

11/84-AB

26.7 ¢cm (10.5 inch) box, 240 Vac

11/84-BA

Same as -AA except MSVI11-JC 2 Mbyte

11/84-BB

Same as -AB except MSV11-JC 2 Mbyte

11X84-AA

KDJ11-BF, MVSI11-JB I Mbyte

11X84-AB

KDJ11-BF, MSV11-JB 1 Mbyte

11X84-BA

Same as -AA except MSV11-JC 2 Mbyte

11X84-BB

Same as -AB except MSV11-JC 2 Mbyte

1.4

105.7 c¢m (40 inch) cabinet, 120 Vac
105.7 c¢cm (40 inch) cabinet, 240 Vac

RELATED DOCUMENTS

Table 1-9

PDP-11/84 Related Documents

Document Title

Order Number

PDP-11 Bus Handbook

EB-17525-20

PDP-11/84-P Technical Manual

EK-PDP84-TM

PDP-11/84-A Technical Manual

EK-1184A-TM

PDP-11/84 Site Preparation, Unpacking and

EK-PDP84-IN

Installation Guide

PDP-11/84-P System Field Maintenance Print Set

Cabinet:
Box:

MP-02015

PDP-11/84-A System Field Maintenance Print Set

Cabinet:
Box:

MP-02199
MP-02198

MP-02011

KDJ11-B User Guide

EK-PDP84-UG

MSV11-J User Guide

EK-MSV1J-UG

MSV11-R User Guide

EK-MSVIR-UG

Chipkit Handbook

EJ-01387-92

DCJ11 User Guide

EK-DCIJ11-UG

Microsystem Handbook

EB-2605-41/85

1-8

Printed copies of the above listed documents may be ordered from:
Digital Equipment Corporation
444 Whitney Street
Northboro, Massachusetts 01532
ATTN: Printing and Circulation Services (NR2/M15)

Customer Services Section

1-9

CHAPTER 2
DIAGNOSTIC AND TROUBLESHOOTING AIDS

2.1

INTRODUCTION

This chapter contains troubleshooting information, diagnostic error message interpretation, and module

configuration information.

NOTE
The UNIBUS powerup protocol on PDP-11/84 systems is slightly different from

other PDP-11

systems.

With other PDP-11 systems, UNIBUS signal INIT
L is held asserted for a minimum of 10 ms after the

negation of DCLO L.

On PDP-11/84 systems, UNIBUS signal INIT L is
held asserted for a minimum of 16 ms after the
negation of DCLO L. This difference will not affect
any system operations.
2.2

GENERAL TROUBLESHOOTING NOTES
1.

The corrective maintenance strategy is field replaceable unit (FRU) replacement.

As a quick power check, check the cabinet blower or the box fans for operation.

Verify the symptoms reported by the customer before removing any components.

The troubleshooting information in this guide assumes that only one FRU has failed.

Check system cables for loose connections and any damaged cables or wires. Replace if
necessary.

Spare FRUs may be dead-on-arrival (DOA); do not ignore the possibility that a newly installed

FRU is faulty.

Symptoms displayed on the console terminal or LEDs can indicate multiple failures; therefore,
the symptoms may change as FRUs are replaced. Always troubleshoot the current symptoms.

2-1

2.3

DIAGNOSTIC TYPES

PDP-11/84 A- and P-serics systems support three types of diagnostic programs.

DECXII - provides system tests to check the interaction of cach option and isolate system

XXDP+ - provides tests that check individual options and local- ize hardware failures to the

Read Only Memory (ROM) resident - CPU ROM-resident startup diagnostics test various
functions specific to the system modules and private memory interconnect (PMI) bus, and

failures to the subsystem component.

function level.

isolate failures to the module or option level.

The following A- and P-series XXDP+ diagnostic programs test various functions on the three kernel
modules. To initiate an XXDP+ diagnostic, the system must first successfully complete the startup
diagnostics.

A-Series Diagnostics:

OKDA?? (KDJ11-BF)
OKTA?? (KTJ11-B)
VMIJA?? (MSV11-))

P-Series Diagnostics:

OKDA?? (KDJ11-BC)
OKTA?? (KTJ11-B)
VMSA?? (MSV11-R)

The 72 at the end of the diagnostic names ensures that the latest diagnostic version is executed when
called.

To load and execute any diagnostic issue, the RUN command followed by the diagnostic name. For
example:

R OKDA?? <CR>

The startup diagnostics are executed during a system power-up or restart. A failure during diagnostic
execution halts the testing and displays one of the following.

An error code and an error message on the console terminal (if connected).

An error code on the front panel STARTUP TEST display.

The error code in the CPU module diagnostic LEDs.

Normally, the system displays the same error information in all three locations. If the console terminal is
not working, refer to the STARTUP TEST display. If neither location is working, refer to the CPU
module LEDs.

2-2

2.4

CONSOLE TERMINAL ERROR MESSAGE FORMAT

A typical consote error message is shown in Figure 2-1.

Testing

Memory

Size

Step

memory

Step

Error

1024

Please

Bytes

test

3456

CSR

Error

troubleshooting

Error

PC=

173436

documentation

PCR page= 15

Program

listing address=

060000

0582525

172100

100000

040000

R6e

172300

Par3

Command
1

Rerun

Loop

Map
a

015436

172344
=

010000

Description

Type

command

test

memory
then

and

page

press

the

RETURN

Figure 2-1

2.4.1

wait

Memory
See

progress

key:

Error Message Display Example

Console Error Message Description

The console error message contains the following information:
1.

An error code — This is the octal number of the startup diagnostic test that failed.

Table 2-1 lists the error codes, test descriptions, and probable causes.
2.

An error description — This is a one-line description of the error.

Table 2-2 lists the error messages and their descriptions.
3.

A “See troubleshooting documentation” message.

Error address line - This address line specifies the error program counter (Error PC=), the page
number in the ROM (PCR page=), and the address to reference in the program listing
(program listing address=).

In the case of unexpected traps, the error address is the address following the instruction that
caused the unexpected trap.
5.

The content of RO-R6 of register set 0, and the content of kernel page address register (PAR)
3. The tests do not use register set 1. Register set 1 is used mainly by ROM code support
routines.

2-3

For some tests the system displays the failing address, the expected data, and the received data
(bad data).

A command line that describes user-selectable commands. To execute a command, enter the
associated command number (e.g., 1, 2, etc.) and press the Return key. The commands are:

1 followed by the Return key — rerun the test. If the test passes the ROM code will
continue testing. If all other tests pass, the ROM code will display the total number of
errors and enter dialog mode regardless of the mode selection in the electronically eraseable programmable read-only memory (EEPROM).

2 followed by the Return key - loop on test. This option causes the ROM code to
continuously loop on the test that failed. These loops are generally very large and are not
intended to be used as scope loops.

The test runs until an error occurs or end-of-test has been reached. In either case, the test
is started again and continues to loop until the user types <CTRL/C> at the console. At
this point, the ROM code will display the total number of errors and the total number of
successful passes if any.

Both the error counter and the pass counter have a maximum value of 65535, If either
counter reaches this value the count will not overflow to zero; it will stay at this value.

3 followed by the Return key — map memory and 1/O page. This command is normally
used if a memory error occurs. If a memory is not configured properly the MAP command
may point to where the memory actually is.

In a multi-memory system in which one memory fails, this command can be used as a
method of physically identifying the failing memory, if it has a communications status
register (CSR).

This command is only available when the bus is turned oi.
for tests (or codes) 76 through 56.

4 followed by the Return key — advance to the next test. This command allows the user to
bypass the failing test and continue. This command will only show up for errors that are
generally considered nonfatal.

If the error is fatal and Field Service would like to bypass the error, it is possible by typing
<CTRL/O>, 4 and the Return key, and the command will be executed.
CAUTION

Errors should not be bypassed unless all user
software has been removed or write-protected.

At this point, the ROM code flushes its input buffer of any previously typed characters and waits for input
from the user.

2-4

Table 2-1

Error Codes, Test Descriptions, and Probable Causes

Error

Code
77

Test Description

Probable Cause

Initially set to this value on power-

The halt switch is on at power-up.

up.

A UNIBUS bus grant (BGn) or nonprocessor grant
(NPG) line is open and slave acknowledge (SACK)
is being asserted by the bus.
Check monitor and distribution module (MDM).
All grant cards must be installed.
Terminator is faulty.
Power supply is faulty.

First CPU tests, memory

Mg8190

management unit (MMU) register
tests.

Turn MMU on. Run MMU and

MS8190

CPU tests.
74

Turn on private memory

M&190, M8191

interconnect (PMI) and look at the
UNIBUS adapter (UBA)
RESTART bit. Then turn off PMI.
73

Power-up to octal debugging

Not a failure - selected mode is ODT in

technique (ODT).

EEPROM and the system is in (J11) ODT.

Power-up to 24/26.

M8190, M8191

EEPROM checksum tests.

EEPROM accidentally written; restore data using
setup mode commands; verify W40 installed on
M&190 module.

CPU ROM checksum and PC tests.

M&190

Miscellaneous CPU and extended
instruction set (EIS) tests.

M8190

Console serial line unit (SLU)
test 1 — check for each register’s

MS8190

response.

Console SLU test 2 - transmit and

MS8190

receive data in maintenance mode.
64

Console SLU test 3 - check

MS8190

interrupts and errors in maintenance
mode.
63

Test MMU aborts.

M8&190

Standalone mode CPU cache tests.

M&190

Clock test.

M8190
Clock from power supply.

Floating-point processor.

Unused.

Mg8190

2-5

Table 2-1

Error Codes, Test Descriptions, and Probable Causes (Cont.)

Error

Code

Test Description

Probable Cause

Exit standalone mode. Check
location of address 17 760 000 for

Mg191
M8190

timeout.

UBA register response test, check
UNIBUS through diagnostic data

M&191
UNIBUS failure

ME&190

Memory size test.

UNIBUS failure

Check memory present at location

PMI memory

0 - 4K word memory test.

PMI memory, M&8190

Cache testing using PMI memory.

M&190

Memory test 1 — data tests byte

PMI memory

tests.

Memory parity/error correction

PMI memory

code (ECC) tests.

Memory address/shorts test.

PMI memory

UBA ROM response test.

ME191

UBA map registers data path test.

MS8191

UBA unmapped diagnostic cycles

MS8191

test.

UBA mapped diagiiostic cycles test.

M8191

UBA floating address/data test
using mapped diagnostic cycles.

MS8191

UBA address overflow test.

MEg191

UBA cache data test.

MS8191
PMI memory

UBA cache least recently used

MS8191

(LRU) test.

UBA cache floating address test in ~ M8191
tag store.

UBA cache parity error detection

Mg191

test.

UNIBUS memory

UNIBUS memory data path test.

UNIBUS memory parity logic test.

UNIBUS memory

UNIBUS memory address/ shorts

UNIBUS memory

MS8191

test.

Table 2-1

Error Codes, Test Descriptions, and Probable Causes (Cont.)

Error

Code

Test Description

Probable Cause

NOTE
With the exception of error codes 25, 22, and 6,
codes 30 through 1 are bootstrap problem indicators
and are not diagnostic errors.

Some may be corrected by the user. Others may be
indicators of errors in the device being bootstrapped.
30

Test exit routine.

Unused.

Air movers and voltage regulator

test.

Cabinet blower

Box fans
H7213 regulator module

Minimum load module (MLM) not installed.
No memory module(s) in system.

NOTE
Error code 25 is not used in P-series systems.
24

Unused.

XON not received after XOFF. To
correct, type <CTRL/Q> at the

console.

Console terminal not ready due to XOFF signal
received from terminal while attempting to print a

message.

This is normally not considered a failure, because

the condition could be operator error (if the

operator has typed <CTRL/S> without following

with <CTRL/Q>, the terminal is not ready, out of

paper, etc.).

Console SLU transmit ready bit

MS8190

not set.

Drive error.

The device that the user is attempting to boot is
displaying an error code in its error register. Verify

that media is in good condition and bootable.
20

Controller error.

The UNIBUS controller for the device the
customer is attempting to boot is displaying an
error code in its CSR. Ensure that the NPG
jumper was removed if the device is a direct
memory access (DMA) controller. Consult the

device’s technical manual for more information.

2-7

Table 2-1

Error Codes, Test Descriptions, and Probable Causes (Cont.)

Error
Code

Test Description

Invalid device.

Probable Cause

The mnemonic typed in for the boot device is
either incorrect or the boot ROM for that device is
not installed. Go to the dialog mode and “LIST"
the valid devices.

Invalid unit number.

The unit number after the mnemonic is not within
acceptable range for that device. See that device’s
technical manual for help.

Nonexistent drive.

‘The drive number the user is trying to boot from is

Nonexistent controller.

The controller for the device the user is trying to

not on the PDP-1 1/84.

to boot from is not on the UNIBUS or is addressed
incorrectly.

No tape installed.

No tape present.

No disk present or drive is not

No media in drive or the drive LOAD button not

Nonbootable media is in the drive.

The bootstrap data from the device does not
conform to the boot block specifications. Ensure

loaded correctly.

in.

that media is bootable. Change setup mode to
accept nonstandard boot blocks.

Drive not ready.

Console disabled.

Self explanatory.

Dialog mode.

The system is in dialog mode and waiting for input

UBA ROM boot in progress.

May take a few seconds.

EEPROM boot in progress.

May take a few seconds.

CPU ROM boot in progress.
Blank

not completed its spinup function.

from the console terminal to rewind.

May take up to 5 minutes for some devices.
Program control has been transferred to a
secondary boot, an EEPROM boot, or a
UBA/M9312 boot.

Unused.

No media present in the drive or the disk drive has

Table 2-2

Startup Diagnostic Error Message Descriptions

Error Message

Description

M8190 CPU Cache Error

CPU cache logic error

M&190 FP Error

CPU floating-point error

M8190 CPU ROM Error

CPU ROM logic or checksum error

M&190 EEPROM Checksum Error

CPU EEPROM logic or checksum error

M8&190 Clock Error

CPU clock logic or power supply clock error

M&190 CPU Error

Other CPU errors

UNIBUS Signal Error

A UNIBUS signal is always asserted

No memory in location 0

Memory failed or is addressed incorrectly

Memory Error

General memory test errors

Memory CSR Error

Memory errors during parity or ECC testing

M8&191 UBA Cache Error

UBA cache error

M&191 UBA Error

Other UBA errors

Unexpected trap to location

This is a general error message that occurs during any

unexpected traps. The address of the trap -follows this
message.

2.4.2

Unexpected Trap and MMU Error Code Descriptions

Figure 2-2 shows an example of the error code and message displayed when an unexpected trap occurs.
The error number of unexpected traps is always the current test number plus 100.
NOTE
Operator input is underlined in

the following

examples.

In the example, the error code (or test number) is 62. The actual error code is read as 162. The STARTUP
TEST display will display 62 since it is only a two-digit display.

Unexpected traps are always considered fatal errors.

2-9

Testing
Error

Please

wait

162

Unexpected

See

progress

trap

location

troubleshooting

Updated

PC=

173436

250

MMU

documentation

PCR

page=

Program

listing

address=

101365

076410

177746

101367

000250

172276

Par3

Command
1

Rerun
Loop

177744

052400

Description

Type

015436

command

test
on

test

then

press

Figure 2-2

the

RETURN

key:

Unexpected Trap Error Example

For codes 76 and 75, the ROM code displays the single letter E followed by the test number (Figure 2-3).
After the message is displayed, the ROM code will not accept any input. The only option for the user is to
restart the system or repair the problem.

Figure 2-3

Example of Test Error

2.4.3 Boot Program Error Codes/Messages
Error codes 21 through 10 (described in Table 2-1) are associated with the boot programs for disks, tapes,
and DECnet devices. These errors are applicable for all CPU ROM-resident boot programs. and any
EEPROM boots that are written to pass these errors back to the CPU ROM. Only errors 14, 16, and 17
apply to UBA or M9312-type ROM boots.

Figures 2-4 and 2-5 show examples of an error from a boot program when the BOOT command is used in
dialog mode.

Commands are Help, Boot, List, Setup, Map
Type a command then press the RETURN key:
Trying

DL1

Message

present,

disk

drive

not

loaded

correctly

Description

Command
1

Reboot

Type a

and Test.
B DL1 <CR>

command

Dialog

mode

then

press

Figure 2-4

the

RETURN

key:

Boot Program Error Example

2-10

Commands

Type

are

Trying

DL3

Message

Non

existent

Commands
Type

Help,

command

are

Boot,

then

List,

press

the

Setup,

RETURN

Map

and

key:

Map

and

Test.

DL3

<CR>

drive

Help,

command

Boot,

then

Figure 2-5

List,

press

the

Setup,
RETURN

Test.

key:

Boot Error Message Example

When the ROM code enters the automatic boot sequence, all boot error messages are suppressed on the
first pass through the list of boot devices. If no device is successfully booted on the first pass, the ROM

code will restart the automatic boot sequence and try to boot all of the selected devices again and display
all applicable error messages.

When the ROM code has failed to boot any of the devices selected in the automatic boot list, dialog mode
is entered. Figure 2-6 shows an example of a boot error display when the automatic boot sequence failed to
find a bootable device and dialog mode is entered.

Testing

Memory

Size

memory

Step

123

Starting

progress
is

1024

Please

Bytes

test

4567839

automatic

Trying

DUO

Trying

DU1

Non

boot
disk

present,

bootable

Trying

DU2

Drive

not

Trying

DU3

Drive

Error

Trying

DLO

Commands

Type

wait

are

Help,

command

Figure 2-6

then

drive

the

not

present,

Boot,

List,

the

drive

Setup,

RETURN

Map

and

not

SYSTEM TROUBLESHOOTING AIDS
The system provides the following troubleshooting aids.
1.

LED monitors.

Voltage test points.

Monitor logic with audible alarm.

loaded

Test.

key:

Automatic Boot Error Message Example

2.5

loaded

drive

ready

disk

press

media

Front Panel

2.5.1

The front panel indicator DC ON monitors the dc output voltages on the main power supply (Figure 2-7).
If the DC ON LED is off, the probable causc is one of the power supply regulators. Each regulator has a
specific LED monitor located on the MDM module.

OFF

lifgliltlal1

SECURE

STANDBY

PDP-11/84

START-UP TEST

(_Dbcon

|- RESTART
=
%“

(C_DRuN

M RUN

HALT

(D BATTERY

/
MR-13441

Figure 2-7

System Front Panel

MDM Module

2.5.2

The MDM module provides the following troubleshooting aids.

LEDs that monitor most power supply voltages (Figure 2-8).

)

the main nower sunnlv voltages
I

llllllllll

tJ\J

ver

supply

voltages,

Blower/fan rotation monitoring logic.

The tolerance for each voltage should be within + 10%, checked on the test points located above the LED:s.
If a voltage is found to be out of tolerance or not present, one of the power supply regulators specified in
Table 2-3 is the probable fault.

The rotation monitor logic indirectly checks the +12 Vde. If the blower/fans fail to send a rotation-based
pulse, the monitor logic causes an audible alarm to sound and powers down the system one minute later.
Table 2-3

Power Supply Regulator Fault Isolation

LED

Voltage(s) Monitored

Probable Cause

+5 V main power supply
+5 VBB and +12 V blower/fan

H7200 in H7202-KA
H7213 in H7202-KA
H7211 in H7202-KA

D2
D3

+15 V main power supply
+5 V expansion power supply

+15 V expansion power supply

H7200 in H7202-KB
H7211 in H7202-KB

CARD CAGE

AnNnMNnN

MDM

:(AJ

REAR FOR BOX

fi'b

TOP FOR CABINET

MDM (M7677)

D1=+5V (MAIN POWER SUPPLY)
D2 =+5V BB AND + 12V (BLOWER/FANS)

D1=ERROR LED

(RED)

D3 =+15V AND -15V (MAIN POWER SUPPLY)
D4 = +5V (EXPANSION POWER SUPPLY)

D5 = +15V and - 15V (EXPANSION POWER SUPPLY)

\‘

DIAGNOSTIC LEDs

2 o8Bl

DCOK POWER LED (GREEN)

091

————DIAGNOSTIC LEDs

——LsB

D2 = +5V BB POWER

(GREEN)

MINIMUM LOAD

[

F--—%

MODULE (M7556)\~\

D2=-15V (OFF)

D1=+5V BB MAIN POWER SUPPLY (RED)

o111

) U

MSV11-JB/JC MEMORY (M8637-BA/CA)

Li.
H

KDJ11-BF (M8190)

\. — MINIMUM LOAD MODULE

D'\..

(M7556)

[——D2=-15V (GREEN)

H—D1=+5V MAIN POWER SUPPLY (RED)

-UUUUUUUJ
MR-15300

Figure 2-8

MDM Module LED Layout

MDM Module Notes:
I.

An M7677-YA MDM must be used if the system contains an H7231-E or -F BBU.

If the MDM is the suspected problem, check the voltage test points and the NPG switch pack
configuration prior to module replacement (Figure 2-9).

Loss of voltage turns off the associated LED.

If an LED indicates loss of voltage, check the corresponding test point prior to regulator

replacement.

2-13

The setting of the NPG select switch pack is used to select NPG status. Each NPG switch
corresponds to a CPU backplane slot 5 through 12. Figure 2-9 shows the location and slot
number of the cach NPG switch.

For non-DMA devices, the NPG switch should be in the ON position. A common NPG
problem occurs when DMA devices are installed with the NPG switch ON (arbitration mechanism is bypassed).

This causes an error code 20 when attempting to boot that device, indicating a controller error.

To correct the problem, turn off the NPG switch for that slot.

|J4

Ne Py4

N
|

VOLTAGE TEST
POINTS

_15V +156V GND +5.1V +€£////,
OO0

‘

(20 PIN)

06O

(20 PIN)

D2 DI

panao D'\SEENOTE
< AUDIBLE
ALARM
SLOT
NUMBER

NPG

00000000 ‘fl___—_’,,_.,———-guflTCH
PACK

OFF

M7677

r'\

NOTE:

D1=+5 (MAIN POWER SUPPLY)
D2 = +5VBB AND +12V (BLOWER/FANS)

D3 = +15V MAIN POWER SUPPLY
D4 = +5V (EXPANSION POWER SUPPLY)
D5 = +15V (EXPANSION POWER SUPPLY)
MR-13221

Figure 2-9

MDM Module Layout

2-14

2.5.3
KDJ11-BF/BC CPU Module
The KDJ11-BF/BC module provides the following.
.

A green power OK (POK) LED, indicating that dc power to the CPU module is present.

Six red error code LEDs, which correspond to the startup diagnostic error codes (Figure 2-10).

If the CPU module is the suspected problem, check the following prior to module replacement.
I.

The module jumper configurations are as specified in Figure 2-10.

The dual in-line package (DIP) switches are off.

CONNECTOR

DIP SWITCH FOR
BAUD RATE SELECT AND
BOOT STRAP CONTROL

FOR CABLE TO

BAUD RATE SELECT
AND TWO-DIGIT DISPLAY

CONNECTOR

FOR CABLE TO \

CONSOLE SLU

:77

\..I J1| I

S/B OFF

DIAGNOSTIC

LSB
/

I\
"

DCOK LED
(GREEN)

LEDS (RED)
/
—

—7

ll’;ID:ll/

[ J3 |«

REMOTE SWITCH

CONTROL CONNECTOR

W10

ROM

TP11
o[ _Jo TP10

(HI BYTE) ~—__]

15:08

J [ ]

E117
E116

07:00

—

GATE

ARRAY

EEPROM
_—|
(SEENOTE 1)

40—PIN SOCKET (P—SERIES)

DCJ11 CPU HYBRID

ROM

(LO BYTE) —

[___—Jw\FPJH-A(A—SERIES)

E53

2:1y

W40
TPa0O[J0 o TP42

£35

P41

GATE

(SEE NOTE 2)

ARRAY
W20

TP200[JO TP210TP22

L
NOTES:

flesf
1. WHEN 24-PIN EEPROM IS USED, INSERT PIN ONE OF EPROM IN
PIN 3 OF SOCKET.
2. WHEN 2K EEPROM IS USED, TP40 IS CONNECTED TO TP41.
WHEN 8K EEPROM IS USED, TP41 IS CONNECTED TO TP42.

Figure 2-10

KDJ11-BF/BC Jumper and Switch Pack Locations

2-15

MR-13444

MSV11-JB/JC Memory Module

2.5.4

The quad-height memory module provides the following.
1.

A red LED to indicate uncorrectable crrors

A green LED to indicate the presence of +5 Vde

Two switch packs for starting and CSR address selection

Four factory-sct jumpers.

—.

If the module is the suspected problem. check both LEDs. the switch pack settings, and jumper configura-

tions prior to module replacement. See Figure 2-11 for LED. switch pack, and jumper layout.

1
S2
D2

1
S1

Q\m
R10

w4 W3 D3

o
Figure 2-11

MR- 15229

MSV11-JB/JC LED/Switch Pack/Jumper Layout
NOTE

Do not run the XXDP+ diagnostic if the module

fails the startup diagnostic test. The startup

diagnostic tests most of the memory module
functions thoroughly. The XXDP+ diagnostic

requires between 20 and 60 minutes to complete.

2-16

The starting address is configured using switch pack S1, switches 1 — 8. Table 2-4 lists the switch settings,

starting addresses, and decimal numbers. The top 16 entries apply to the 1 Mbyte (MSV11-JB) memory
and the bottom 16 entries apply to the 2 Mbyte (MSV11-JC) memory.
Table 2-4

MSV11-JB/JC Starting Address

Switch Setting *

Starting

12345678

Address (Octal)

Decimal (K)

00000000

00 000 000

00000001

00 040 000

00000010

00 100 000

00000011

00 140 000

00000100

02 000 000

00000101

00 240 000

00000110

00 300 000

00000111
00001000

00 340 000
00 400 000

00001001

00 440 000

00001010

00 500 000

00001011

00 540 000

00001100

00 600 000

00001101

00 640 000

104

00001110

00 700 000

112

00001111

00 740 000

120

0000X XXX

00 000 000 — 00 740 000

000
- 120

0001

XX XX

00 100 000 - 01 740 000

128
- 248

001 0X XXX

02 000 000 - 02 740 000

256
- 376

0011 XXXX

03 000 000 - 03 740 000

384
- 504

0100X XXX

04 000 000 - 04 740 000

512
- 632

0101

XXXX

05 000 000 - 05 740 000

640
- 760

011T0X XXX

06 000 000 — 06 740 000

768
—
88

0111 XXXX

07 000 000 - 07 740 000

896
— 1016

1000X X XX

10 000 000 - 10 740 000

1024
- 1144

1001

000 000 - 11 740 000

1152
- 1272

1010X XXX

12 000 000
- 12 740 000

1280
- 1400

101 1T

X XXX

13 000 000 - 13 740 000

1408
- 1528

I11T00X XXX

14 000 000
- 14 740 000

1536
- 1656

1101

XX XX

XXXX

15 000 000
- 15 740 000

1664
- 1784

11T10X XXX

16 000 000
- 16 740 000

1792
- 1912

ITTIXXXX

17 000 000
- 17 740 000

1920
- 2040

* 1

= Switch
on

0 = Switch
off
X = Switch can be either on or off

2-17

The CSR address is configured using switch pack S2, switches 1 = 4. The base address is 17772100. Each
successive address is the base plus 2. Table 2-5 lists all 16 possible CSR addresses.
Table 2-5

MSV11-JB/JC CSR Address Selections

S2 Setting

1234

CSR Address (Octal)

0000

17 772 100

0001
0010

17 772 102
17 772 104

0011
0100

17 772 106
17 772 110

0101
0110

17 772 112
17 772 114

0111

17772 116

1000

17 772 120

1001
1010
1011
1100
1101
1110
1111

17 772 122
17 772 124
17 772 126
17 772 130
17 772 132
17 772 134
17 772 136

The jumper configurations for the MSV11-JB and MSV11-JC memory modules are different. Ensure that
the factory-set jumpers are as specified in Table 2-6.

Table 2-6

Moduie

MSV11-JB/JC Jumper Configurations

Jumper(s)

Position

Description

Out

256K Dynamic RAMs

Half-populated module

W3, W4

Vertical

Reserved for future use

Out

256K Dynamic RAMS

Out

Fully populated module

W3, W4

Vertical

Reserved for future use

MSV11-JB

MSV11-JC

2.5.5

MSV11-R Memory Module

The quad-height memory module provides the following.

A switch pack for memory starting address and CSR address selection

A red LED for monitoring parity errors

Figure 2-12 shows the location of the switch pack and LED. If the module is the
suspected problem, check
the parity LED and switch pack settings before module replacement.

PARITY ERROR

INDICATOR

jL \ JL

RED
LED

—1

OFF
Sl|eo

STARTING

=|<+—1 ANDCSR

ADDRESS

sg|=2

SWITCHES

COMPONENT SIDE

|
MR-13222

Figure 2-12

MSV11-R Switch Pack and LED Locations

NOTE
Do not run the XXDP+ diagnostic if this module fails the startup diagnostic test. The startup
diagnostic checks most of the memory functions thoroughly. The XXDP+ diagnostic
requires approximately 40 minutes to
complete.

Switches S3 and S4 of the switch pack should

always be in the OFF position.

2-19

Switches ST and S2 of the switch pack configure the starting address. They cnable the starting address on
| Mbyte boundaries. See Table 2-7 for S1 and 52 settings.
Table 2-7

MSV11-R Starting Address Selection

Starting Address

OFF

00 000 000

OFF

04 000 000

OFF

10 000 000

14 000 000

is 17 772
Switches S5 through S8 on the switch pack configure the CSR addr ess. The base CSR address possible
16
all
for
address
starting
the
for
100. Fach successive address is the base plus 2. See Table 2-8
starting addresses.

Table 2-8

MSV11-R CSR Address Selection

CSR Address

ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
OFI
OFF
OFF
OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF

ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF

ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF

17 772 100
17 772 102
17 772 104
17 772 106
17 772 110
17 772 112
17 772 114
17 772 116
17 772 120
17 772 122
17 772 124
17 772 126
17 772 130
17 772 132
17 772 134
17 772 136

2-20

2.5.6 KTJ11-B Module
The module provides four sockets to support M9312 compatible ROMs. If this module is the suspected
problem, check the ROMs and their orientation as shown in Figure 2-13.

M9312 TYPE OPTION ROM SOCKETS (4)

ROM
1

E E145

SOCKET
E145

E144

E143

E142

~ ADDRESS
17773000—17773176

17773200~17773376

17773400—17773576
17773600—17773776

E144

[Z) e
E142
PIN
NO. 1

]

ull

fi
MR-13445

Figure 2-13

KTJ11-B ROM Socket Locations

2.5.7 Minimum Load Module
The MLM modules are used to provide minimum power supply regulator loads under the following
conditions.
1

If only one memory module slot is occupied, an MLM is inserted in CPU backplane slot 3 (rows
C and D) to ensure a minimum current drain of 2 A from the +5 VBB regulator.
An MLM is inserted in CPU backplane slot 12 (rows E and F) to ensure a minimum current

drain of 1 A from the —15 Vdc regulator.
3.

If an expansion backplane (DD11-CK or DD11-DK) is installed, an MLM is inserted in the last
slot of the backplane (rows E and F) to ensure a minimum current drain of 1 A from the —15

Vdc regulator.

NOTE
An MLM is not required in the last backplane slot

(CPU or expansion) if the installed options draw the
minimum current drain of 1 A of —15 V.

An MLM module in an expansion backplane only monitors the —15 Vdc.

When not required, the load modules must be removed from the backplane.

2-21

As shown in Figure 2-14, the MLLM has two LEDs to indicate the presence of +5 VBB (RED, D1) and —15
Vdc (GREEN, D2).

7
B8

RED

GREEN

]
Figure 2-14

2.6

MR-15298

Minimum Load Module Layout

Ji1 MICRO ODT

J11 Micro ODT (ODT) is entered anytime the CPU is halted by one of the following.
1.

Placing the front panel toggle switch in the HALT position

Executing a halt instruction, if the halt mode is enabled and the system is in kernel

Pressing the Break key, if the terminal is set up to generate a break character, and the front

panel keylock switch is set to ENABLE.

2-22

Table 2-9 summarizes the ODT commands. The figures following the table provide examples for most of
the commands. Note that operator input is underlined.

Table 2-9

J11 Micro ODT Command Summary

Command

Symbol

Description

Slash

Opens and outputs the contents of a memory location,
I/O device register, internal processor register, or
processor status (PS) register. The / must be preceeded

by octal digits (n) to specify the register or location. See

Figure 2-15 for example.

Carriage return

<CR>

Closes an open location. If a location’s contents are to

be changed, precede the <CR> with the new data. If no
change is desired, <CR> closes the location without
altering its content. See Figure 2-15 for example.
Line feed

<LF>

Closes an open location and opens the next contiguous
location. Memory addresses are incremented by two, and
processor registers are incremented by one. If the PS is

opened, it is closed and no new location is opened. See
Figure 2-16 for example.
Internal register

$n or Rn

Either character — when followed by a register number
0 to 7, or the PS designator (S) — will open the specified
processor register. If more than one number is entered

after R or $, the last number entered will be used.
Processor status word
designator

Opens the processor status register. The designator must

follow $ or R.

Starts program execution at the location entered
immediately before the G. If G is issued with the front
panel switch set to HALT, the system is initialized,
ODT re-entered, and the PC displayed. G truncates the
address entered in the last 16 bits. For example, 7 777
773 000G would be read as 173 000G. Since memory
management Is disabled by G, the starting address is
always in the lower 28K of memory or the I/O page.
See Figure 2-17 for example.

Proceed

Resumes program execution. The command corresponds

to CONTINUE on other PDP-11 consoles. Program
execution resumes at the address pointed to by the PC.
If P is issued with the front panel switch set to HALT,
it is recognized at the end of instruction execution, ODT

is re-entered, and the PC displayed. The user can thus
single-instruction step through a program and obtain a
PC trace on the console terminal. See Figure 2-18 for
example.
Binary dump

<Ctrl/

Manufacturing use only. It is not recommended this

Shift/S>

command be used.

2-23

2.6.2

ODT Notes

When entering addresses or data. leading zeros are not required. They will be filled by ODT.

When entering addresses in the 1/0O page, all 22 bits must be entered (e.g.. 17 776 100).

A ? (question mark) will be printed whenever illegal characters are cntered, addresses arce

accessed that result in a timeout, or a parity error is detected.
ODT Command Examples

®@1000/ 012737 <CR>

;0pen memory location 00001000.

@100/ 000200 7422 <CR»>»

;0pen memory location 00000100

:The contents (012737) are
;jdisplayed. <CR> closes the
slocation without modification.

;and deposit
sclose

Figure 2-15

/ (Slash) Command Example

®@1000/ 012737 <LF>

;Location

1000

;contents

are

sthen

100200

0O <LF>»
-

closed

is opened,
displayed,

with

:The <LF> caused the next
ilocation to be opened and

the

icontents

:The next

176100 <CR>»

the
and

<LF>.

displayved.

s:this case the contents
;changed the operator.

00001004

and

(7422)

data

location.

jnew data.

00001002

the

;Re-open the location and deposit

@/ 007422 6422 <CR>

i1to

closed

the

are

is opened

location

examine

:then

contents

with

and

<CR»>.

location

1000.

10006

;The program is started at

@10006
-

;The program is started with the Halt switch
;on. The CPU initializes registers and then
ihalts without executing the first instruction.
;The PC is displayed and then the ODT prompt

@1000

;is

displayed.

Figure 2-17

GO Command Example

2.6.1

®R7/002464

1000

<CR>

iR7

(PC)

jcontents
saddress

proceed

;jand

the

;The

001004

;jHalt

and

entered

iThe

command

program

;location

opened

displayed.

the

The new
in
is

R7.
issued

continues

1000.

proceed

command

jwith front panel
position.

issued

switch in the

The

;jdisplayed.

®P

001010

;Etc.

Figure 2-18

PROCEED Command Example

2.7 DIALOG MODE COMMAND DESCRIPTIONS
When dialog mode is entered, the ROM program prints out the message shown in Figure 2-19 at the
console terminal and waits for the user to select a command.

Commands
Type

are

Help,

command

then

Figure 2-19

Boot,
press

List,
the

Setup,
RETURN

Map

and

Test.

key:

Dialog Mode Commands

Dialog mode command notes:
l.

The user may obtain a brief description of each command by typing H followed by pressing the
Return key or by typing ? only.
All commands may be executed by typing only the first letter of the command followed by the
Return key. For example, the MAP command can be invoked by typing M or MA or MAP.
On command input, all lower-case letters are converted to upper-case, and leading spaces and

tabs are ignored.
If the terminal type selection in the EEPROM is video, the ROM code will erase the previous
character on the screen when the Delete key is pressed. If the terminal type is hard copy, the
ROM code will use slashes (/) to identify all deleted characters.
Use <CTRL/U> at any time to delete the entire command line. <CTRL/U> is not echoed by

the ROM code.
<CTRL/R> will retype the command line. <CTRL/R> is normally used when the terminal
type is hard copy to clear up command lines where the Delete key has been used. <CTRL/R>
is not echoed by the ROM code.

2-25

Input is limited to 16 characters and spaces. If more than 16 characters are entered, the ROM
code will delete all input and retype the KDJ11-B prompt. Typing the seventcenth character is

equivalent to typing <CTRL/U>.

8. The ROM code will ignore any space or tab typed prior to a character, or the second tab or
space typed in a row without a printable character in-between. All tabs are converted to and
echoed as spaces.

If an invalid input is received an “invalid entry” message will be typed and the header prompt
repeated.

10.

In some cases the following command examples may not represent the exact printout or screen
display.
NOTE

If additional information is required for any dialog
mode command refer to Chapter 4 of the
PDP-11/84 System Installation and Technical
Reference Manual.

The following subsections summarize each command and provide execution examples.
2.7.1

HELP Command

The HELP command prints out a brief description of all available commands (Figure 2-20). It can be
executed by typing H and the Return key, or typing ? only. Dialog mode is restarted at the end of the
command.

Commands are Help, Boot, List, Setup, Map and Test.
Type a command then press the RETURN key: H <CR>
Command

Description

Help

Type

this

message

Boot

Load and start a program from a device

List

boot

programs

Setup
Map

Enter Setup mode
Map memory and 1/0

Test

page

Continuous self test

- Type <CTRL/C> to exit

Commands are Help, Boot, List, Setup, Map and Test.
Type a command then press the RETURN key:

Figure 2-20

HELP Command Display

2-26

2.7.2
BOOT Command
The BOOT command initiates a device bootstrap (Figure

2-21). Command arguments are the device name
program prompts for it. If the unit number is left

and the unit number. If the device name is left off, the

off, the program assumes unit zero. The unit number ranges
from 0 to 255(10) depending on the device
and the boot program.
These are the three optional switches used with the BOOT

command.

Request to allow the user to type in a nonstandard CSR address

The unit number is octal instead of decimal for unit number

If the boot exists in the base ROM and also on the UBA,
override the base ROM boot and use
the UBA boot or M9312 module.

for the controller.

s greater than 7.

When using a switch, type the device name and unit number
followed by / (slash) and the switches. When
there is more than one switch, use only one slash.

If the BOOT command is entered without an argument, the
ROM code prompts for additional information with the following message.
Enter

device

name

and

unit

number

then

press

At this point, if ? (question mark) is typed, the ROM code
“Enter device name ....” message, and waits for a selectio

Commands

Type

are

Trying

Boot,

then

press

List,

the

RETURN

system

RT-11FB

(S)

.SET

QUIE

from

Setup,

RETURN

Map

key:

DL2

V05.01

DATIME

Date?

[dd-mmm-yy1?

Figure 2-21

DL2 BOOT Example

2-27

key:

lists the boot programs available, retypes the

DL2

Starting

Help,

command

the

and

Test.

DL2

<CR>

2.7.3

LIST Command

or any
Prints out a list of all available boot programs found in the CPU ROM. the CPU EEPROM, mode
s

M9312-type ROMs located on the UBA or an M9312 module if present (Figure 2-22). Dialog
restarted at the completion of the LIST command.

against a list of
The mnemonic for each ROM found on either the UBA or the M9312 will be checked
will print out a
code
ROM
the
list.
this
mnemonics in the ROM code. If the mnemonic matches an item in
mnemonic.
that
for
blank
left
be
will
description of that device. If no match is found, the description
Commands are Help, Boot, List, Setup, Map and Test.
Type a command then press the RETURN key: L <CR>
Device

name

Unit

numbers Source

0-255

CPU ROM

DX
DY
DD
DK
MU

0-1
0-1
0-1
0-7

CPU
CPU
CPU
CPU
CPU

0-3

0-2 55

CPU ROM

ROM
ROM
ROM
ROM
ROM

Device type

RDS51, RD52, RX50, RC25, RA8BO, RAB1, RAGO
RLO1, RLOZ2
RXO01
RXO02
TUSS
RKO5
TK50, TU8Bt1

Commands are Help, Boot, List, Setup, Map and Test.

Type a command then press the RETURN key:

Figure 2-22

LIST Command Display

SETUP Command

dialog mode. This mode
Setup mode is entered by typing the SETUP command (S and the Return key) inbootstrap
programs stored
2.7.4

allows the user to list or change parameters in the EEPROM, and also change
in the EEPROM.

-28

When setup mode is first entered it prints out a list of its 15 commands and provides a short description of

each (Figure 2-23).

Commands
Type

are

Help,

command

KDJ11-B

Setup

Command

Boot,

then

List,

press

mode

the

Setup,
RETURN

KDJ11-B

ROM

Exit

List/change

parameters

List/change

boot

List/change

the

Automatic

Reserved
the

switch

List/change

List

Initialize

boot

Test.

<CR»>

V7.0

Setup

table

into

the

data

into

EEPROM

boot

Delete

Load

Edit/create

EEPROM
an

Save

boot

into

Enter

ROM

ODT

then

boot

table

EEPROM

command

Setup
in

boot

Setup

Load

the

Save

translations

table

the

Setup

selections

table
in

the

table

programs

and

Description

Type

Map
key:

press

Figure 2-23

boot

into

EEPROM

the

EEPROM

Setup

table

memory

boot

the

EEPROM

the

RETURN

key:

SETUP Command Descriptions

Setup mode command notes:
l.

The version number of the ROM code is printed out at the beginning of the setup mode
message.

To execute a command, type the command number followed by the Return key.

Enter <CTRL/C> to return to dialog mode, or <CTRL/Z> to return to the beginning of setup
mode.
Never terminate a parameter change with <CTRL/C> or <CTRL/Z>. If this is done the

change is ignored and lost.
Always use the terminating character Return key after any change and then <CTRL/C> or
<CTRL/Z>.

2-29

When setup mode is restarted by typing <CTRL/Z>. or at the completion of commands 2 thru 15, the
ROM code will print out a short command message instead of the full list of commands (Figure 2-24).
Enter a new command, or press the Return key to list the full command menu.

KDJ11-B

Type

Setup

the

Press

mode

key for Help
then press the

RETURN

command

Figure 2-24

RETURN

key:

Short Command Message

2.7.4.1

SETUP Command 1 - Exit command for setup mode. Returns the user to dialog mode. Dialog

2.7.4.2

SETUP Command 2 - Causes the ROM code to print out the current status of all parameters,

mode is also entered if <CTRL/C> is typed.

repeats the first parameter, and waits for user input (Figure 2-25). Type carriage returns to position the

program at the desired parameter to be changed, or go directly to the parameter by typing the parameter
letter.

NOTE

After changing any parameters in the setup table,
command 9 (save) should be executed.

To change a parameter, type in the new value and press the Return key. Typing <CR>, <LF> or . (period)
will cause the ROM code to proceed to the next parameter. Typing * or - will cause the ROM code to
proceed to the previous parameter.

2-30

Figure 2-25 shows an example of command 2 being executed
, and the value of parameters if command 8,
(initialize setup table) had been executed.

KDJ11-B

Press
Type

Setup

the
a

mode

RETURN

command

List/change

key

then

for

Help

press

the

RETURN

key:

the

Setup

table

parameters

<CR»>

ANSI

Video

terminal

Power

0=Dialog,

Restart

(1)=Automatic,

0=Dialog,

2=0DT,

Ignore

(1)=Automatic,

2=0DT,

battery

PMG

Disable

Force

0-(7)

clock

Clock

0=Power

Enable

ECC

Disable

ROM

Enable

trap

Allow

Disable

supply,

test

long

memory

0=No,
on

Setup

Disable

all

Enable

UNIBUS

Disable

UBA

Enable

UBA

Enable

List/change

ANSI

Video

test

1=Dis

165,

boot

block

te5ting
memory

test

(1)

ROM
cache

bit

(1)

mode

exit

terminal

Figure 2-25

3=24

1=Yes

0=No,

1=Yes

2=60Hz,

3=800Hz

0=No,

1=Yes

0=No,

1=Yes

173,

3=Both

1=Yes

0=No,

1=Yes

0=No,

1=Yes

0=No,

1=Yes

0=No,

1=Yes

0=No,

1=Yes

0=No,

1=Yes

0=No,

1=Yes

the

Setup

table

press

the

RETURN

(1)

3=24

0=No,

mode

1=Yes

4=3.2,...7=25.6

2=Dis

Halt

parameters

1=50Hz,

(1)

alternate

Type

3=1.6,

interrupts

2=.8,

CSR

0=No,

1=.4us,

clock

(1)

0=No,

key

1=Yes

for

change

New

SETUP Command 2 Example

NOTE
If for any reason the N parameter (disable setup
mode) is set to 1 (yes), the mode is disabled and

cannot be entered.

If it is necessary to enter setup mode, set the
FORCED DIALOGUE switch to ON, enter 2

<CR>, and reset parameter N to 0 (no).

If 124 KW of UNIBUS memory is present, the last two
parameters will not be present (enable UBA cache
and enable 18-bit mode). When this condition occurs, UBA
cache is always disabled and 18-bit mode is
unconditionally forced.

2-31

2.7.4.3 SETUP Command 3 - Prints out the contents of the translation table and allows changes to the
table content (Figure 2-26). The translation table is used to allow devices to be booted using nonstandard
CSR addresses.

no
The ROM code tries to find a match in the translation table for the device name and unit number. If the
found
is
match
2
If
device.
the
for
address
CSR
default
the
uses
match is found the boot program
translation table defines the CSR address used.

KDJ11-B

Press

Setup

mode

the RETURN key for Help

Type a command then press the RETURN key: 3 <CR>

List/change boot translations in the Setup table
TT1

blank

TT2

blank

TT3

blank

TT4

blank

TTS

blank

TT76
TT7

blank
blank

TT8

blank

TT9

blank

Type <CTRL/Z> to exit or press the RETURN key for No change
TT1
Device

blank
name

Figure 2-26

SETUP Command 3 Example

The ROM code prompts for a new device name. If no translation table changes are desired, type
<CTRL/Z> to return to the setup mode prompt. Skip over any entry by pressing the Return key. To enter
a new device or change an entry, type in the new device name, unit number, and CSR address.
27.4.4 SETUP Command 4 — Allows selection of the devices to be tried in the automatic boot sequence
(Figure 2-27). The user creates a small list that defines the devices and the order in which they are to be

tried.

-32

The example of Figure 2-27 shows that the user added the boot for the RX02 unit 1 (DY) by replacing the
exit name (E) with DY and typing in the unit number. The exit function is moved to the next entry.

KDJ11-B
Press

Type

Setup

the

command

List/change
Disk

MSCP

External

key

then

the

continously

Boot
Boot

Boot

automatic

Boot

DLO

MSO

MUO

blank

Type

Boot

Device

the

exit

¢CR»

<CR>

name

Unit

number

<CR>»

Boot

name

<CR>

number

<CR>

Boot

Unit

KDJ11-B

Press

Type

key

table

press

RETURN

for

change

<CR»>

blank

Setup

the

Setup

Device

the

MUO

name

Device

MSO

name

Device

selections

DLO

name

Device

<CR>

boot

¢CR>

name

Device

boot

key:

boot

Boot

RETURN

boot

Loop

Boot

Help

automatic

Exit

Boot

for

press

Automatic

ROM

OUTbH WM

[

rmMo>

mode

RETURN

mode

RETURN

command

key

then

Figure 2-27

for

Help

press

the

RETURN

key:

SETUP Command 4 Example

2.7.4.5 SETUP Command 5 - This command is reserved and is not used. If this command is entered,
setup mode will be restarted and no changes are made.
2.7.4.6 SETUP Command 6 - Allows the user to define the value of three of the eight switches at the
edge of the CPU module to boot specific devices (Figure 2-28). The command defines six of the eight
possible combinations of switches 2-4. The other two combinations have a fixed definition that cannot be
changed.

2-33

Figure 2-28 shows an example of command 6 with three of the six possible positions defined to select DUO,
DUI, DU2, and the remaining three defined to select DLO.

KDJ11-B

Press

Type

Setup

the

mode

RETURN

command

List/change

key

then

the

for

Help

press

the

switch

boot

RETURN

selections

Setup

RETURN

key

for

2,3,4

off

DUO

2,3,4

off

DU1

Switches

2,3,4

off

DU2

Switches

2,3,4

off

DLO

Switches

2,3,4

off

of f

DLO

Switches

2,3,4

off

DLO

press

the

off

Switches

Device

2,3,4

name

exit
on

<CR>

the

Switches

Switches

Type

key:

table

change

DUO

Figure 2-28

SETUP Command 6 Example

2.7.4.7 SETUP Command 7 - Performs the same function as the LIST command in dialog mode, and is
duplicated in setup mode for user convenience. Setup mode is restarted at the completion of this
command.

2.7.4.8 SETUP Command 8 - Initializes the current contents of the setup table in memory to the default
values (Figure 2-29). The command does not affect the contents of the EEPROM itself. Command 9 must
be executed in order to save the setup table into the EEPROM. Command 8 only affects parameters
associated with commands 2 through 6.

The following items list the value of the parameters after command § is executed:
°

All parameters listed under command 2 of are set to 0 with the exception of A, B, C, I, P, and R
which are set to 1 (Figure 2-25).

)

All entries in the translation table under command 3 are cleared and will list as blank.

The automatic boot selection list under command 4 will be set to A, DL0O, MS0, MUO, E, blank.

Enter the command by typing 8 and the Return key. After the ROM code prompt, type 1 and the Return
key. Command 9 (save) should be executed after command 8 to copy the defaults into the EEPROM.

2-34

KDJ11-B

Press

Type

Setup

the

mode

RETURN

command

Initialize

the

Are

you

sure

Type

command

KDJ11-B
Press

Type

for

Help

press

the

Setup

the

key

then

key:

<CR»>

RETURN

key:

<CR>

RETURN

key:

table

0=No,
then

RETURN

1=Yes

press

the

for

Help

press

the

mode

RETURN

command

key

then

Figure 2-29

SETUP Command 8 Example

2.7.4.9

SETUP Command 9 - Copies the current contents of the setup table in memory into the
EEPROM (Figure 2-30). The command should be executed after any changes are made.

[f command 9 is entered and no changes have been made to the setup table, the ROM code will output a

message stating that no changes were made and then restart setup mode. If changes are to be made, the

ROM code will prompt to ensure changes are desired.

KDJ11-B
Press

Setup

the

Type

Save

the

mode

RETURN

command
Setup

Are

you

sure

Type

command
the

KDJ11-B

Setup

Type

the
a

Help

press

the

RETURN

table

into

the

EEPROM

Writing

Press

for

then

key

0=No,
then

key:

<CR>

RETURN

key:

<CR>

RETURN

key:

1=Yes

press

the

for

Help

press

the

EEPROM
mode

RETURN

command

Figure 2-30

key

then

SETUP Command 9 Example

2-35

2.7.4.10 SETUP Command 10 - Restores the setup table in memory with the values actually stored in
the EEPROM. and allows the user to restore the setup table after making some temporary changes
(Figure 2-31). It is also used to load the actual data from the FEPROM into the setup table 1f an crror
occurred during the EEPROM checksum tests.

When an error occurs during the EEPROM checksum tests, the ROM code assumes the data is bad and
loads a set of default values into the setup table and uses them. In this case. the user could load the actual
data and then verify that the data is good before trying to save it in the EEPROM.

Setup

KDJ11-B

mode

the RETURN

Press

key

for

Help

Type a command then press the RETURN key:

10 <CR>

Load EEPROM data into the Setup table
?

1=Yes

0=No,

Are you

sure

KDJ11-B

Setup mode

Type a command then press the RETURN key:
Press the RETURN key for Help
Type a command then press the RETURN

Figure 2-31

<CR>

key:

SETUP Command 10 Example

2.7.411 SETUP Command 11 — Allows the user to delete an EEPROM boot (Figure 2-32). The ROM
code will prompt for the device name of the EEPROM boot to be deleted. After the device name is
entered, the ROM code searches for the first boot program in the EEPROM with that device name and
deletes it.

If there are any boot programs following the del

programs up to use the space made available by the deleted program.

Setup

KDJ11-B

Press

mode

key

the RETURN

Help

for

Type a command then press the RETURN key:
an

Delete

<CR>

boot

EEPROM

Type «<CTRL/Z> to exit or press the RETURN key for No change
=

name

Device

0=No,

Are you

sure

KDJ11-B

Setup mode

«<CR>
1=Yes

Type a command then press

Press

key for Help
then press the RETURN

the RETURN

Type a command

the RETURN key:

Figure 2-32

<CR>

key:

SETUP Command 11 Example

2.7.4.12 SETUP Command 12 - Copies an EEPROM boot program into memory (Figure
2-33). The
ROM code prompts for the device name of the EEPROM boot program to be loaded
in memory. The
program can then be examined and/or edited using SETUP command 13.

KDJ11-B

Press

Setup

the

mode

RETURN

key

for

Help

Type

command

then

press

the

Load

EEPROM

boot

into

memory

Type

Device

name

Are

you

sure

command

KDJ11-B
Type

Setup

the

«<CR)»

Type

Press

exit

0=No,
then

press

the

key:

RETURN

<CR>

key

for

1=Yes

press

the

for

Help

press

the

RETURN

key:

RETURN

key:

<CR»

mode

RETURN

command

RETURN

key

then

Figure 2-33

SETUP Command 12 Example

2-37

change

2.7.4.13 SETUP Command 13 - Used to create a new EEPROM boot program. or to edit a program
previously loaded with command 12. Command 13 allows changes to the device name, device description,
allowable unit number range, beginning and ending addresses of the program in memory, and the starting
address of the program (Figure 2-34).

When changes are complete the ROM code enters ROM ODT. When the command is first entered 1t will
list the available space in the EEPROM for bootstrap programs

Type

1410

Byte s

Beginning
byte

ROM

Enter

the

EEPROM

= AA

New = EA <CR>

address

= 000600

New =

10000 <CR>

address

= 000615

New =

10177 <CR>

= 000600

New =

10000 <CR>

= 3

New = 255 <CR>

= EA BOOT

New = RM02,RM0O3 <CR>

number

RETURN
[

ROM

ODT»

ROM

ODT»>

ROM

ODT»>

ROM

ODT»>

oDT

open word location xxxxxx if address even, byte if odd

XXXXXX/

etc.

De scription

Device

free

U nit

Highest

13 <CR>

to exit or press the RETURN key for No change

add ress

Start

the RETURN key:

boot

na me

Device

Last

EEPROM

Edit/crea te

Help

for

then press

co mmand

key

RETURN

the

Press

mode

S etup

KDJ11-B

location
Vot imm
LIV

vivoe

dULVA

location

010000/000000
010002/000000
0100047000000
010006/000000

med

Aamam

u'.n.n

A N
i

open

012705 <CR»>
101 <CR>
12706 <CR>
1000 <CR>

Type <CTRL/Z> exit back

Figure 2-34

A +

Qita

and

to the setup mode menu.

SETUP Command 13 Example

2-38

2.7.4.14 SETUP Command 14 - Allows the user to save the existing
boot program located in memory
into the EEPROM. This is the only command that actually writes a
boot into the EEPROM (Figures 2-35
and 2-36). The other commands only change a copy of the boot program
that resides in memory.
When saving a boot program in memory, the device name of the program
must not match the name of an
existing program in the EEPROM. If the program name already exists,
delete that program first or change
the name of the program to be saved. If two or more programs were
written into the EEPROM with the

same name, only the first will be used.

KDJ11-B

Press

Setup

the

Type

Save

boot

Type

command
into

Are

you

sure

command
the

KDJ11-B

Setup

Type

the
a

for

Help

press

the

RETURN

the

EEPROM
press

the

Nriting

key

then

Type

Press

mode

RETURN

exit

0=No,
then

EEPROM

command

for

Help

press

the

RETURN

change

key:

<CR»>

key

Help
the

into

the

EEPROM

already

Boot

changes

the

RETURN

key:

RETURN

key:

<CR>

EEPROM

made

Setup

the

key:

mode

RETURN

for

boot

for

wait

press

Save

Type

key

SETUP Command 14, Example 1

command

KDJ11-B

RETURN

then

Press

the

Please

key

then

Setup

the

Type

<CR>

1=Yes

press

Figure 2-35

KDJ11-B

RETURN

mode

RETURN

Press

key:

mode

RETURN

command

key

then

Figure 2-36

for

Help

press

the

SETUP Command 14, Example 2

2.7.4.15 SETUP Command 15 - Calls ROM ODT. The ROM code
will open up the address defined by
the beginning address of the program (Figure 2-37).

NOTE
ROM ODT is not the same as J11 micro ODT. Its

only purpose is to allow the user to create or edit a

small

bootstrap

program

EEPROM.

stored

the

In ROM ODT, the only addresses that can be examined are memory
addresses from 0 - 28 KW (0 00157776). Table 2-10 lists the ROM ODT commands.

2-39

Table 2-10

ROM ODT Commands

Command

Symbol

Use

Slash

Prints contents of specified location. If no address is defined. then
print contents of the last location that was opened. If location opened
is an odd number. print out only the contents of the byte. If location
is even, then mode is word: if location is odd. then mode is byte.
Leading zerocs are assumed. Only bits 15 through 0 of the address
are uscd.

Return

<CR>

Line Feed

<LF>

Closes an open location.

Closes an open location and opens the next location. If word,
increment address by 2: if byte, increment address by 1.

Alternate character for line feed. This command is useful when the

Period

terminal is a VT2xx series terminal. It is also convenient to usc with
the keypad.

Up Arrow

Closes an open location and opens the previous location. If in word

Minus

—

Alternate character for up arrow. This command is useful when the

mode, decrement by 2; if byte, decrement by 1.

terminal is a VT2xx series terminal. It is also convenient to use with
the keypad.

Delete

DELETE

Deletes the previous character typed.

Exit ROM ODT and return to setup mode.

The followihg paragraphs present examples of ROM ODT use.
Example :

Location 200 is opened. It is then closed with no changes and location 202 1s opened, which is then closed
aDT

ROM

oDT

ROM

oDT

VvV

ROM

anT

VvV

ROM

after changing its contents.
200/

000200/100000
000202/003333

Example 2:

Byte location 1001 is opened. It is then closed and locations 1002 and 1003 are opened. Data in location

abT

ROM

oDT

ROM

oDT

ROM

aDT

<LF>

0010037113

141

<LF

0010027104

1001/

0010017101

<CR>

-40

oDT

ROM

Vv Vv

ROM

1003 is changed and the location is closed.

Example 3:

The user attempts to open location 170 000 which is in the 1/O page and not allowed.
ROM

ODT

ROM

ODT

»>

77770000/

Example 4:
Location 150 000 is opened and closed. It is then reopened by typing / (slash) only.
ROM

ODT

150000/

ROM

ODT

150000/032737

ROM

ODT

ROM

ODT

150000/032737

<CR>

Figure 2-37 presents an example of command 15.
KDJ11-B
Press
Type

Enter
Type

Setup

the

command

ROM

xxxxxx/

RETURN

open

LF
=

for

Help

press

the

RETURN

press

the

exit

word

key

then

location

<CR»

key

for

address

location

and

open

and

open

0100007000000

012705

)10002/000000

101

ROM

ODT>

0100047000000

12706

ROM

ODT>

location

ODT>

Type

xxxxxx

ODT>

Setup

the

RETURN

ROM

KDJ11-B

even,

change
byte

odd

<CR»>

<CR>

mode

RETURN

command

location

ROM

Press

key:

ODT

mode

RETURN

key

then

for

Help

press

the

Figure 2-37

RETURN

key:

SETUP Command 15 Example

2.7.5 MAP Command
Identifies all memory in the system and then maps all locations in the 1/O page (Figure 2-38). Dialog mode

18 restarted at completion of the MAP command.

NOTE
If two memories share some common addresses or
have CSRs with the same address, the command will
not work properly.

During mapping, if two or more memories are present and they are not contiguous, the ROM code will
separate their descriptions with a blank line,

2-41

The ROM code waits for the user to press the Return key anytime the data on the video screen might
overflow.
Commands are Help, Boot, List, Setup, Map and Test.
Type a command then press the RETURN key: M <CR>
Memory

Map

Starting
Address

00000000
Press
[1/0

Ending
address

Size in
K Bytes

CSR
address

CSR
type

Bus
type

03777776

1024

17772100

Parity

PMI

the RETURN

page

key when

continue

<CR>

Map

Starting

Ending

Address

address

17765000

17765776

CPU

17770200
17772100

17770376

Unibus

17772150

17772152

17772200
17772300

ready

ROM or

EEPROM

Map

Memory CSR

17772276
17772376

Supervisor I and D PDR/PAR’s
Kernel I and D PDR/PAR’s
MMR3

17772516

17773000

17773776

17774400

17774406

17777520

17777524

17777546
17777560
17777572

17777566
17777576

17777600
17777730
17777744

17777676
17777734
17777752

CPU ROM or

UBA ROM

PCR,

BCR/BDR

BCSR,

Clock CSR
Console SLU
MMRO,1,2

User I and D PDR/PAR’Ss
DCSR, DDR, KMCR
MSER, CCR, MREG, Hit/Miss

17777766
17777772

CPU

17777776

PSW

Error

PIRQ

Commands are Help, Boot, List, Setup, Map and Test.
command then press the RETURN key:

Type a

Figure 2-38

2.7.6

MAP Command Display

TEST Command

The TEST command causes the ROM code to run most of the power up tests in a continous loop. The
code starts at test 70 and restarts the loop after test 30. If an error occurs, the general error routine is
entered.

Exit the test loop by typing <CTRL/C> at the console. When the test loop is exited, the ROM code will
print out the total number of loops and the total number of errors (if any).

A test number may also be entered after the TEST command. If applicable, the ROM code will loop on
that specific test until an error occurs or <CTRL/C> is typed. If the test number is not a loopable test, the
general test loop will be entered and all loopable tests will be run.

NOTE
<CTRL/C> is not echoed by the ROM code on the
console terminal.

2-42

Figure 2-39 shows an example of entering the test comman
d by typing T and the Return key which runs
all loopable tests. The testing sequence is aborted after four
passes by typing <CTRL/C>.

Commands

Type

are

Help,

command

Continuous

self

Total

Passes

Errors

Commands
a

are

Help,

command

List,

press

test

Total

Type

Boot,

then

Type

Boot,

then

the

Map

the

Setup,
RETURN

and

key:

List,

press

Figure 2-39

Setup,

RETURN

exit

Map

Test.

<CR»>
<CTRL/C>

and

Test.

key:

TEST Command Example

Figure 2-40 shows an example of looping on only test 60.
The test loop is aborted by typing <CTRL/C>
after 202 passes.

Commands
Type

are

Help,

command

Looping

test

Total

Passes

202

Total

Errors

Commands
Type

are

Help,

command

Boot,

then

Figure 2-40

press

Type

Boot,
press

List,
the

Setup,
RETURN

List,
the

Setup,
RETURN

Map
key:

exit

Map
key:

Loop-on-Test Example

2-43

and
T

Test.
<CR>

and

Test.

CHAPTER 3
REMOVAL AND REPLACEMENT PROCEDURES

3.1
FIELD REPLACEABLE UNITS
Table 3-1 lists the field replaceable units (FRU) for the P-series systems. Table 3-2 lists the FRUs for the
A-series.
Table 3-1

P-Series FRU Descriptions

Part Number

Description

M7677

Monitor distribution module (MDM)

M8191

KTJ11-B, UBA module

M8190

KDJ11-BC, CPU module

M7458-A

MSV11-RA, 1Mbyte parity memory

M7556

Minimum load module

M9302

Terminator module

70-20650-01

CPU backplane

H7202-KA

Power supply

H7202-KB

Power supply

54-16508-01

Console SLU board

H7211-B *

+15V, —15V regulator module

H7213-D *

+12V, +5V regulator module

H7200-C *

+5V regulator module

70-21888-01

Front panel assembly

12-22001-01

Blower

12-22271-02

Fan

877-D

Power controller 120V

877-F

Power controller 240V

70-21116-01

Circuit-breaker assembly

* Specifies minimum etch revision.

3-1

Table 3-2

A-Series FRU Descriptions

Part Number

Description

M7677-YA *

Monitor distribution module

Mg191

KTJ11-B, UBA module

Mg190

KDJ11-BF, CPU - FPA module

M8637-BA

MSV11-JB, I Mbyte ECC memory

M8637-CA

MSV11-JC, 2 Mbyte ECC memory

M7556

Minimum load module

M9302

Terminator module

70-20650-01

CPU backplane

H7202-KA

Power supply

H7202-KB

Power supply

54-16508-01

Console SLU board

H7211-B **

+15V, —15V regulator module

H7213-D **

+12V, 45V regulator module

H7200-C **

+5V regulator module

70-21888-01

Front panel assembly

12-22001-01

Blower (cabinet)

12-22271-02

Fan (box)

877-D

Power controller 120V

877-F

Power controller 240V

70-21116-01

Circuit-breaker assembly

Options:
H7231-E

Battery-backup unit

DD11-CK

4-slot backplane

DD!11-DK

LEAN

QGiiw

M7677-YA must be installed if the system contains the H7231-E BBU option.

** Specifies minimum etch revision.

3-2

3.2 GENERAL MODULE REMOVAL/REPLACEMENT
To remove any module listed in Tables 3-1 and 3-2 (except the CPU module) use the following

procedure.

CAUTION

Modules are static sensitive.

Always wear a properly connected ground
strap when handling modules.

Modules must be placed on a static mat anytime they are removed from a backplane or
their shipping static bags.

Open the cabinet front and rear doors using the hex key, or slide the box out of the rack.
Turn either:

The cabinet power supply and power controller circuit breakers to OFF, or

The box circuit breaker to OFF.

Remove the ac power cord from the outlet.
Ensure that the ground strap is properly connected.
Remove all cables from the module and label each one.

Pull the module handles out and slide the module from the backplane.

Place the module on the static mat.

This completes the removal of a module. To reinstall a module, reverse the procedure.

3.3 CPU MODULE REMOVAL/REPLACEMENT
Replacing the CPU module is a special case. The replacement module setup features must be confirmed

and, if necessary, revised to the original CPU parameters and selections.

During the initial system installation, the user should have recorded the setup feature selections on the
worksheet supplied in the Installation Guide or Appendix B in this guide. Retrieve this form. Compare
the selections of the original CPU module (as specified on the worksheet) with the factory-set defaults of

the replacement module.

Confirm and/or revise the setup features using the following procedure.
NOTE
Dialog and setup mode commands are described in

subsection 2.7.

3-3

Wear a properly connected ground strap. Remove the defective module from the backplanc as
specified in subsection 3.1.

Ensure that the replacement module jumper configurations and DIP switch settings are as

specified in subsection 2.7.3.

Install the replacement CPU module as described in subsection 3.2.
Sct the forced dialogue switch to ON.
Power-up the system, and ensure that it passes the startup diagnostics.

On successful cpmletion of the startup diagnostics, the system enters dialog mode (Figure 2-19).
Enter setup mode by typing S and the Return key on the console terminal (Figure 2-23).
If the customer chose the factory defaults, perform steps 8 and 9; otherwise, begin at step 10.

Type 8 and the Return key to initialize the setup table to the factory default values. Type 1 and
the Return key at the ROM code prompt (Figure 2-29).
Type 9 and the Return key to copy the default values to the EEPROM. Type 1 and the Return
key at the ROM code prompt (Figure 2-30).
11.

Type 2 and the Return key to display the setup table parameters (Figure 2-25). Compare the
replacement module parameters to the original selections; revise as required.

12.

Type 3 and the Return key to display the translation table parameters (Figure 2-26). Compare
the parameters to the original selections; revise as required.

Type 4 and the Return key to display the automatic boot selections (Figure 2-27). Compare the
selections to the original; revise as required.

Type 6 and the Return key to display the CPU switch boot selections (Figure 2-29). Compare
the selections to the original; revise as required.
15.

Type 9 and the Return key to copy the revised parameters and selections into the EEPROM
(Figure 2-30). Type 1 and the Return key at the ROM code prompt.

10O,

NS RV PN

1rse:

mvit

catiim

mamda

oA
——

sa a4 ~

R DN

~A
A

I'ype 1 and the Return key to exit setup mode and return to dialog mode.

This completes the CPU module replacement and setup procedure.

3-4

3.4

POWER SUPPLY REMOVAL/REPLACEMENT
Both the cabinet and box products have H7202-KA power supplies each containing three regulator boards.

The regulator boards and power supplies are FRUs. Make sure that the regulator boards are not defective

prior to replacing a power supply.

3.4.1
Cabinet Power Supply Removal/Replacement
To remove a power supply regulator board or the main power supply, use the following procedure.
l.

Open the front and rear doors using the hex key.

Turn off the power supply and power controller circuit breakers.
Remove the ac power cord from the outlet.
Loosen the two captive screws holding the blower assembly.

Slide the blower assembly out about four inches, and disconnect the blower motor power cable.

Slide the blower assembly out and up to remove it from the cabinet assembly (Figure 3-1).

r-—/___’____

POWER SUPPLY

CIRCUIT BREAKER

MODULE

COVER

PLASTIC

RETAINERS

CAPTIVE

BLOWER

ASSEMBLY
MR-14333

Figure 3-1

Blower Assembly Removal

3-5

Push in the power supply tray lock (located on the left edge of the tray slide). Slide the tray out
by pulling on the tray handle until the second tray lock engages (Figure 3-2).

00000

tele
rete
slele

|F=

‘

lele

TRAY

HANDLE

olelolele
slelele)e

Figure 3-2

]

5
f
] LifiJYDLE

Cabinet Power Supply Removal

Loosen and remove the power supply hold-down bracket located near the top left edge of the
power supply.

Using a Phillips-head screwdriver, remove the four 5 Vdc bus wires.
10.

Remove the two ribbon cables and the ac input cable.

11.

Using a 3/8-inch wrench, remove the ground lug.

12.

Pull the power supply forward and remove it from the cabinet.

3-6

I3.

Loosen the three captive screws holding the top cover of the power supply and remove the cover

(Figure 3-3).

H7211

q:: | —

:F%EF

& +12VDC

H7200
H7213

+5VDC

flsvoc\

J
HF—

STAND OFFS

/(6)

[JJ —

A—

Ul
MR-14330

Figure 3-3

14.

Power Supply Regulator Removal

To remove the memory/fan (H7213) or the communications option (H7211) regulators, gently

lift them out by grasping each corner standoff and lift up.

15.

To remove the H7200 regulator, turn the power supply over (open side down), and while
supporting the regulator, loosen the six Phillips-head screws securing it to the chassis.

16.

Remove the regulator from the chassis.

This completes the removal of the regulators boards and power supply. To reinstall, reverse the above
procedure.

3.4.2

Box Power Supply Removal

To remove a power supply regulator or power supply, use the following procedure.
1.

Turn off the circuit breaker.

Unplug the ac power cord from the outlet.

Remove the box top cover by removing the four captive screws and lifting the cover oft,

Loosen the two Phillips-head screws on the power supply cover. Slide the cover backwards and
lift to remove it (Figure 3-4).

CAPTIVE
SCREWS

SCREWS

SPC CABLE

MR- 14335

Figure 3-4

Power Supply Removal

3-8

To remove either the memory/fan (H7213) or the communications option (H7211) regulators,
gently lift them out by grasping the two corner standoffs and lift up.

To remove the H7200 regulator, the power supply must be removed from the box. Loosen the

four screws that secure the power supply to the chassis shelves. Lift the power supply out of the
box (Figure 3-5).

H7211

ft S—
.

H7213

H7200

+5VvVDC

L:MF

& +12VDC

+5.1VBB

i15VDC\

STAND OFFS
/(6)

MR-14330

Figure 3-5

Power Supply Regulator Removal

After removal, turn the power supply over (open side down) and while supporting the regulator,
loosen the six Phillips-head screws securing it to the chassis.

Remove the regulator from the chassis.

NOTE
If the power supply is replaced, set the 120/240 ac
voltage select switch to match the site line voltage.
This completes the removal procedure for box power supply and regulators. To reinstall the regulators and

power supply, reverse the above procedure.

3.5 CABINET BLOWER REMOVAL/REPLACEMENT
To remove the blower assembly use the following procedure.
1.

Open the front and rear doors using the hex key.

Turn off the power supply and power controller circuit breakers,

Remove the ac power cord from the outlet.

Loosen the two captive screws holding the blower assembly. Slide the blower assembly out

about four inches. Disconnect the blower motor power cable.

Slide the blower assembly out while lifting up, and remove it from the cabinet (Figure 3-6).

POWER SUPPLY

CIRCUIT BREAKER

“PLASTIC

MODULE

COVER

RETAINERS

CAPTIVE

SCREWS

TM~

POWER
SUPPLY

BLOWER

ASSEMBLY
MR-14333

Figure 3-6

Blower Assembly Removal

This completes the removal procedure for the cabinet blower assembly. Reinstall the blower assembly in
the reverse order.

3-10

3.6 BOX FAN REMOVAL/REPLACEMENT
There are three fans used in the box product. Two fans cool the module card cage and the third cools the
power supply. To remove any one of the fans use the following procedure.

Turn off the circuit breaker.

Unplug the ac power cord from the outlet.
Remove the four screws from the rear of the box flange. Remove the bezel from the box.

Loosen the six captive screws from the metal grid in front of the fans. Lift off the metal grid.
Loosen the two Phillips-head screws securing the fan to its mounting position on the plenum
(Figure 3-7).

METAL GRID

FRONT BEZEL

SCREWS (4)

MR-14451

Figure 3-7

Box Fan Removal

Unplug the fan power cable and remove the fan.

CAUTION
When installing a fan, ensure that the airflow arrow
points toward the plenum.
When installing a replacement fan, tighten the
mounting screws snug. Do not overtighten.

This completes the fan removal procedure. To reinstall a new fan, reverse the above procedure.

3.7

FRONT PANEL REMOVAL/REPLACEMENT

3.7.1

Cabinet Front Panel Removal/Replacement

The cabinet and box front panels are identical. but have different removal and replacement procedures.
To remove the cabinet front panel use the following procedure.
I.

Open the front and rear doors using the hex key.

Turn off the power supply and power controller circuit breakers.

Remove the ac power cord from the outlet.

Disconnect the cable from the front panel assembly (Figure 3-8).

CABLE

MOUNTING
HARDWARE
/

MOUNTING
HARDWARE

MR .14328

Figure 3-8

Cabinet Front Panel Removal

Remove the four 3/8-inch nuts holding the front panel to the door.

Remove the front panel from the standoffs.

This completes the removal of the cabinet front panel assembly. To reinstall the front panel. reverse the
above procedure.

3-12

3.7.2
Box Front Panel Removal/Replacement
To remove the box front panel use the following procedures.
1.

Turn off the power supply circuit breaker.

Unplug the ac power from the outlet.

Remove the front bezel by loosening and removing the four screws from the bezel rear side. Pull
the bezel away from the box (Figure 3-9).

IS
{

=
SCREW (4)

=W\

AT=

e
fig?

Figure 3-9

Front Panel Removal

Remove the cable that is plugged into the front panel assembly.

Loosen and remove the four Phillips-head screws securing the front panel to the chassis.

Remove the front panel assembly.

This completes the removal of the front panel. To reinstall the box front panel, reverse the above
procedure.

3.8

CIRCUIT BREAKER REMOVAL/REPLACEMENT

Both products have circuit breakers for their power supplies. The box circuit breaker assembly is located
externally on the right side. The cabinet circuit breaker is located internally, and has two breakers: the
main power supply and the expansion power supply.

Cabinet Circuit Breaker Removal/Replacement

3.8.1

To remove the circuit breaker assembly use the following procedure.
l.

Open the front and rear doors using the hex key.

Turn off the power supply and power controller circuit breakers.
Remove the ac power cord from the outlet.

Unplug the cords connected to the assembly (Figure 3-10).

POWER SUPPLY

CIRCUIT BREAKER

PLASTIC

MODULE

COVER

9/|

RETAINERS

CAPTIVE

SUPPLY
BLOWER

ASSEMBLY
MR-14333

Figure 3-10

Cabinet Circuit Breaker Removal

3-14

Remove the blower power connector by pushing in on the connector release clips and pulling the

connector loose.

Loosen the two screws securing the circuit breaker assembly to the cabinet support and remove
the assembly.

This completes the removal of the circuit breaker assembly.
To reinstall the assembly, reverse the above procedures. Ensure that the power cable plugged into the
unswitched power controller outlet is inserted into J1.

3.8.2 Box Circuit Breaker Removal/Replacement
To remove the circuit breaker assembly, use the following procedures.
I.

Turn off the circuit breaker.

Unplug the ac power cord from the outlet.

Remove the rear four bulkhead sections marked A1 through A4. Each section has two flathead

screws (Figure 3-11).

CIRCUIT

BREAKER

MR-14336

Figure 3-11

Box Circuit Breaker Removal

3-15

Remove the four screws securing the breaker assembly to the box.

Reach inside the box through the bulkhead access and release the three cable clips along the box
wall.

Remove the circuit breaker through the rear bulkhcad access.

Remove the four screws securing the wires on the back of the circuit breaker. Label cach wire.

This completes the replacement procedure for the circuit breaker assembly. To reinstall the circuit
breaker, reverse the procedure.

3.9 CABINET POWER CONTROLLER REMOVAL/REPLACEMENT
To remove the 877 power controller assembly, use the following procedure.
1.

Open the front and rear doors using the hex key.

Turn off the power supply and power controller circuit breakers.
Remove the ac power cord from the outlet.

Lift the left side panel straight up from both sides. Be careful—the outside panel is heavy

(Figure 3-12).

e
/

SrRal—

//l & Z

| SHOILILNFR SCRFW (4)

V‘-LEMI SHIELD

“TT
—:v/
&i/——;

Figure 3-12

MR-13321

Cabinet Side Panel Removal

3-16

SCREW (2

Remove the two Phillips and four shoulder screws securing the EMI shield

Label each power plug and its receptacle, and remove the plugs (Figure 3-13).

000000000000 O0O0\Yooo OO0 OO

to the cabinet side.

<+—REAR

H—

—
]o
o

° ]

FRONT —»

[

OOOOOOOOHOOOOOOOOOOOOOO

AC POWER

CABLE

PLUGS

877-D/F

CLAMP

POWER CONTROLLER

N
MR-14326

Figure 3-13

Power Controller Removal - Side View

3-17

Loosen the 10 Phillips-head screws securing the power controller to the cabinet bulkhead

(Figure 3-14).

877-D/F
CONTROLLER

SCREWS
(10)

® o)

'®

MR-14325

Figure 3-14

Power Controller Removal — Rear View

Grasp the controller’s metal power cord restraint and remove the controller from the cabinet

rear.

This completes the removal procedure for the power controller. To reinstall the controller reverse the
above procedure.

3.10

SLU INTERFACE ASSEMBLY REMOVAL/REPLACEMENT

Both products coniain an SLU wiicitace asseiiiony, Sut usc different removal and replacement procedures
-

Lot

'al
25 1
ST I«

R B

Aiawan

Cabinet SLU Assembly Removal

3.10.1

To remove the SLU assembly use the following procedure.
1.

Open the front and rear doors using the hex key.

2. Turn off the power supply and power controller circuit breakers.
3.

Remove the ac power cord from the outlet.

4. Loosen the ten captive screws securing the bulkhead to the frame.
5.

Open the bulkhead by pulling down from the top.

6. Unplug the SLU cable (console terminal) from the connector.

7 Loosen and remove the two hex standoffs securing the connector to the cross member.
8. Unplug the cable from the SLU assembly connector (Figure 3-15).

3-18

N ¢

e
E

Ts g

Il
e
g

I O 1

ofe °

°° |

—SCREW (2)

—

| L

o°o©°o
|| —

// | HEX SCREWS

MR-14490

Figure 3-15

Cabinet SLU Assembly Removal

Hold the SLU assembly while removing the two

crossmember.

10.

screws that secure the SLU assembly to the

Remove the SLU assembly from the cabinet.

This completes the removal of the SLU assemb
ly. To reinstall the SLU assembly reverse the
above

procedure.

3-19

3.10.2 Box SLU Assembly Removal/Replacement
To remove the SLU assembly, use the following procedure.
1.

Turn off the circuit breaker.

Unplug the ac power cord from the outlet.

Remove the cable plugged into the SLLU connector.

Remove the two hex standoffs securing the connector to the back panel.

Remove the four screws on the top cover, and remove the cover.

Remove the connector plugged into the SLU assembly board.

Remove the two assembly mounting screws from the rear of the box (Figure 3-16).
SCREW (2)

/// |

il|

)
.|

]

y
=

]

il|

]

/|,

3 lo

e
.

&LLL

000

s o /

= ©

aluln

—

mREWS

udupUudupud
udduU
jjjfl'fljjflfiflflfi |

LUUUUULLLCUULULUULUUUL

/1T T”TJEWWW w

LW
MR 14481

Figure 3-16

Box SLU Assembly Removal

Remove the hex standoffs from the SLU connectors.

Remove the SLU assembly from the box.

This completes the removal of the SLU assembly. To reinstall the assembly reverse the above procedure.

3-20

3.11

CPU BACKPLANE REMOVAL/REPLACEMENT
Depending on the number of options installed in the system, a backplane replacement can be a timeconsuming task. It is reccommended that you replace the backplane only if it is clearly known to be the

faulty FRU.
3.11.1

Cabinet Backplane Removal
To remove the CPU backplane, use the following procedure.
1.

Open the front and rear doors using the hex key.

Turn off the power supply and power controller circuit breakers.

Remove the ac power cord from the outlet.

NOTE
If the system contains a BBU, it must be removed.
Perform steps 4 thru 10 of the BBU removal procedure (subsection 3.11).
4.

Remove and label all the module cables.

Remove all cabinet modules and label each with its backplane slot number.

Remove the right side panel (Figure 3-17).

LL SHOULDER SCREW (4)
j-——EMI SHIELD

SCREW (2)

Figure 3-17

MR-13321

Side Panel Removal

3-21

Remove the two Phillips-head and four shoulder screws sccuring the EMI panel to the cabinet

frame.

Remove the left side panel.

Remove the four shoulder screws securing the EMI panel to the cabinet frame.

Loosen the ten screws securing the bulkhead to the cabinet frame and lower the bulkhead

(Figure 3-18).

HUIHIHIIIHHHHII”lHH||llllllHlIIHI!IIHIHHHIHHHlIHHIIIHI
BAUD

) ‘[:

0 |LTM~
24=360
5= 2400

0= 38.4K

1=19.2K

2 =9.6K

BAUD

: / /SWITCH

3 = 4800
6= 1200
7 = 600

(fn‘&

FORCED

S
- \\

SWITCH

|
BULK

Ly
HEAD_~

[

SCREW (10)

A o | ERE

oloo @ ‘g ° ol
°

| ] 111

[ q
o

£z

\‘ N—

MR-13442

Figure 3-18

Cabinet Rear View

3-22

DIALOG

SLU

CONNECTOR

Remove the four black plastic retainers securing the plastic lexan cover over the space for the
expansion backplane location (Figure 3-19).

CPU

COPPORP
OO O

BACKPLANE
SCREW (4)

—_—1

I
o

CABLES—

SCREW

BACKPLANE

METAL

AN r

(6)

0
]

1]
L

POWER

CABLES

LEXAN

MR-14327

Figure 3-19

Cabinet Backplane Removal

12.

If an expansion backplane is installed, remove the power connectors. Remove the lexan cover
through the left side cabinet access.

13.

Disconnect the power cables for the expansion backplane.

14,

Loosen the cable clamps on the metal panel covering the rear access to the backplane.

15.

Remove the six screws securing the metal panel over the rear access to the backplane. Remove

the metal panel.
16.

Remove the four flathead screws securing the backplane to the card cage.

17.

Remove the backplane by pulling the it toward the cabinet rear and twisting it through the side

panel access.

This completes the removal procedure for the backplane. To reinstall the backplane reverse the above

procedure.

3-23

Box Backplane Removal/Replacement

3.11.2

To remove the backplane, use the following procedure.
1.

Turn off the power circuit breaker.

Unplug the ac power cord from the outlet.

Remove the screws securing the top cover, and remove the cover.

Unplug all the module cables and label each with its module number.

Unplug all the modules. Label each module with its slot number.

Remove the four 1/4-inch nuts securing the four power cables. Unplug the two backplane

cables (Figure 3-20).

CARD CAGE

BACKPLANE

SCREW (4)

CABLES

SCREW (2)
|

MR -14329

Figure 3-20

Box Backplane Removal

Remove the two screws located at the rear of the card cage.

Slide the card cage to the rear of the box. Lift and slide the card cage to the rear and remove

Turn the card cage over and remove the four backplane mounting screws. Remove the

from the box.

backplane.

This completes the removal procedure for the CPU backplane. To reinstall the backplane reverse the
above procedure.

3-24

3.12 CABINET BBU REMOVAL/REPLACEMENT
To remove the BBU use the following procedure.

1. Open the front and rear doors using the hex key.
2.

Turn off the power supply and power controller circuit breakers.

Unplug the ac power cord from the outlet.

Remove the cabinet right side panel by lifting it straight up from
both sides. Be careful—the
panel is heavy (Figure 3-21).

1 SHOULDER SCREW (4)

" EMI SHIELD

SCREW (2)

o
AN

~_
MR-13321

Figure 3-21

Side Panel Removal

Remove the two Phillips-head and four shoulder screws securing the EMI panel attached
to the
cabinet frame. Remove the shield.

Loosen and remove the ground wires attached to the two BBU rear panel studs.

Carefully unplug the three cables attached to connectors on the BBU rear panel.

Unplug the BBU power cord from the rear panel.

CAUTION
The weight of the BBU is 19 kg (42 Ibs); lifting and

positioning the BBU requires two people.

3-25

Loosen and remove the four hex nuts securing the BBU to the cabinet frame (Figure 3-22).

//’/;1

CARD CAGE

/ASSEMBLY

RETAINER

"’/
\"‘“
[T
.

U-NUT

W/10-32 SCREW (4)

h
W{E@

—
KKK

/fil g@

>\‘M g

KEPNUT

(4)

LINE
FILTER

877-D/F
POWER

UNIT (H7231-E)

CONTROLLER

Figure 3-22

10.

BATTERY BACKUP

MR-15499

BBU Removal

Slide the BBU outward from the frame, and off of the mounting screws.

This completes the removal procedure for the BBU. To reinstall the BBU, reverse the procedure.

3-26

3.13
BOX BBU REMOVAL/REPLACEMENT
To remove the BBU from the box system complete the following procedure.

Turn off the box power supply circuit breaker (Figure 3-23).

CIRCUIT
BREAKER

MRA-14336

Figure 3-23

Box Circuit Breaker Location

Unplug both the box and BBU from the ac power outlet.

3-27

Loosen and remove both ground hex nuts located on the BBU bulkhead panel (Figure 3-24).

RgUUU

o ©
IaL_
J2

MR-15515

Figure 3-24

BBU Bulkhead Panel

Unplug both connectors J1 and J2 located on the box BBU bulkhead panel.
CAUTION

The weight of the BBU is 19 kg (42 lbs); lifting and
o the unit reauires two n eople.
B

SRS

ERYyRELS

Follow the rack manufacturer’s directions for removing the BBU from the rack assembly

This completes the removal of the BBU. To reinstall the BBU reverse the procedure.

3-28

3.14 CABINET PERIPHERAL ACCESS
Always extend the front stabilizer bar before sliding an option out of the top portion of the cabinet. The

LRI
Y
AR

\j{\

LTt

A AT e VTR

bar keeps the cabinet from tipping forward (Figure 3-25).

Figure 3-25

Stabilizer Bar Extension

3-29

CHAPTER 4

SYSTEM REGISTER DESCRIPTIONS

4.1

PAGE ADDRESS REGISTERS (PAR)

)
MR-14122

Figure 4-1

4.2

Page Address Register Format

PAGE DESCRIPTOR REGISTERS (PDR)

PAGE

PAGE LENGTH

BYPASS
CACHE

WRITTEN

FIELD

ACCEstlEcLoDNTROL

EXPANSION
DIRECTION

MR-14123

Figure 4-2

Page Descriptor Register Format

4-1

Table 4-1

Page Descriptor Register Bit Descriptions

Bit

Name

Function

Bypass cache

This bit implements a conditional cache bypass mechanism. If set,
references to the selected virtual page will bypass the cache. A
cache bypass causes the cache location to be invalidated whenever

(R/W)

a read or write hit occurs.
14:8

Page length ficld

(R/W)

Page written (RO)

This field specifies the block number which defines the boundary
of the current page. The block number of the virtual address is
compared against the page length field to detect length errors. An
error occurs when expanding upwards if the block number 1s
greater than the page length field, and when expanding down if
the block number is less than the page length field.
This bit indicates whether or not this page has been modified (i.c.
written into) since either the PAR or PDR was loaded (1 is
affirmative). It is useful in applications which involve disk
swapping and memory overlays. It is used to determine which
pages have been modified and must be saved, and which pages
have not been modified and can be overlaid.
This bit is reset to 0 whenever either the PDR or the associated
PAR is written into.

Expansion direction

(R/W)

This bit specifies in which direction the page expands. If ED=0,
the page expands upwards from block number O to include blocks
with higher addresses; if ED=1, the page expands downwards from
block number 127 to include blocks with lower addresses. Upward
expansion is usually used for program space while downward
expansion is used for stack space.

2:1

Access control

This field contains the access rights to this particular page. The
access codes or “‘keys” specify the manner in which a page may be
accessed and whether or not a given access should result in an
abort to the current operation. The access codes are:
00 Non-resident — abort all accesses
01 Read only — abort on writes
10 Not used - abort all accesses
11 Read/write

4-2

4.3

MEMORY MANAGEMENT REGISTER 0

ABORT: READ ONLY
ABORT: PAGE LENGTH

ABORT: NON-RESIDENT
PROCESSOR MODE
PAGE SPACE

PAGE NUMBER
ENABLE RELOCATION
MR-14124

Figure 4-3

Memory Management Register 0 Format

Table 4-2

Memory Management Register 0 Bit Descriptions

Bit

Name

Function

Abort - nonresident

(R/W)

Bit <15> is set by attempting to access a page with an access

control field key equal to 0 or 2. It is also set by attempting to use
memory relocation with a mode (PS<15:14>) of 2.

Abort - page length
(R/W)

This bit is set by attempting to access a location in a page with a

Abort - read only

This bit is set by attempting to write in a “read only” page.

(R/W)

block number (virtual address bits <12:6>) that is outside the area
authorized by the page length field of the PDR for that page.
“Read-only” pages have access keys of 1.

NOTE
Bits <15:13> can be set by an explicit write;
however, such an action does not cause an abort.
Whether set explicitly or by an abort, bits <15:13>
cause memory management to freeze the contents of

MMRO <6:1>, MMR1, and MMR2. The status
registers remain frozen untii MMRO0 <15:13> are
cleared by an explict write or any initialization
sequence.

4-3

Table 4-2

Memory Management Register 0 Bit Descriptions (Cont.)

Bit

Name

Function

Processor mode

These bits indicate the processor mode

6:5

(kernel/supervisor/user/illegal) associated with the page causing
the abort (kernel = 00, supervisor = 01, user = 11, illegal = 10).

(R/W)

If the illegal mode is specified, an abort is generated and bit <15>

1S set.

Page space (RO)

This bit indicates the address space (I or D) associated with the

3:1

Page number (RO)

These three bits contain the page number of the page causing the

Enable relocation

This bit allows address relocation. When set to 1, all addresses are

4.4

page causing the abort (0 = I space, 1 = D space).
abort.

relocated. When bit 0 is set to 0, memory management is

(R/W)

inoperative and addresses are not relocated.

MEMORY MANAGEMENT REGISTER 1
15

VIRTUAL ADDRESS
MR-14878

Memory Management Register 1 Format

Figure 4-4

4.5

MEMORY MANAGEMENT REGISTER 2 (Address 17 777 576)
15

AMOUNT CHANGED
(2'S COMPLEMENT)

]

Figure 4-5

Memory Management Register 2 Format

4-4

4.6

MEMORY MANAGEMENT REGISTER 3 (Address 17 777 xxx)

ENABLE UNIBUS MAP
ENABLE 22-BIT MAPPING
ENABLE CSM INSTRUCTION
ENABLE KERNEL DATA SPACE
ENABLE SUPERVISOR DATA SPACE
ENABLE USER DATA SPACE
MR-14126

Figure 4-6

Memory Management Register 3 Format

Table 4-3

Memory Management Register 3 Bit Descriptions

Bit(s)

Name

Function

15:06

Unused

Reserved for future use.

Enable UNIBUS

This bit enables the I/O map for the UNIBUS adapter.

map (R/W)
4

Enable 22-bit

This bit, when set, selects 22-bit memory addressing. When this bit

mapping (R/W)

is clear, 18-bit addressing is selected (18- or 22-bit addressing is

actually enabled only when MMRO bit 0 is set).

2:0

Enable CSM
instruction (R/W)

This bit enables recognition of the call supervisor mode (CSM)
instruction.

Enable data space

These three bits enable data space mapping for kernel, supervisor,
and user mode, respectively.

(R/W)

4.7

KDJ11-B CACHE REGISTERS - DATA ORGANIZATION

CACHE TAG

CACHE INDEX
BYTE

SELECTION

Figure 4-7

CPU/DMA Physical Address Interpretation Register

4-5

MR-14127

Table 4-4

CPU/DMA Physical Address Interpretation Bit Descriptions

Bit(s)

Name

21:13

Cache tag (R/W)

Function

I. During CPU rcad/writc operations, thesc bits arc compared

with bits 21:13 of the CPU cache tag register (Figure 4-8) to
determine the cache hit/miss status.

2. During DMA read/write operations, these bits are compared
with bits 21:13 of the DMA tag register (Figure 4-9) to determine
the cache hit/miss status.

For either CPU or DMA operations, a tag hit occurs when the
cache tag contents matches the CPU/DMA tag register and the
CPU/DMA valid bit is set.

12:01

Cache index (R/W)

Byte selection

The CPU cache interprets the CPU/DMA physical address
directly and selects one of 4096 word cache memory locations.
During CPU/DMA write operations, setting this bit selects writing
into the high-byte cache memory location (Figure 4-10).

The high-byte parity bit reflects odd parity on data bits <15:08>.
The low-byte parity bit reflects even parity on data bits <07:00>.

The CPU tag parity bit reflects odd parity on CPU tag bits <21:13>.

The DMA tag parity bit reflects odd parity on DMA tag bits <21:13>.

The CPU and DMA tag valid bits are not included in the CPU and DMA tag parity calculations.

CPU TAG

CPU TAG
PARITY (ODD)

CPU TAG
VALID

Figure 4-8

CPU Cache Tag Register Format

4-6

DMA TAG

PARITY (ODD)
DMA TAG VALID
MR-14130

Figure 4-9

DMA Tag Register Format

HIGH BYTE

LOW BYTE

PARITY (ODD)

PARITY (EVEN)

LOW BYTE

DATA

HIGH BYTE

DATA

MR-14128

Figure 4-10

4.8

CPU Cache Data Organization

CACHE CONTROL REGISTER (Address 17 777 746)

WRITE WRONG

TAG PARITY

UNCONDITIONAL
CACHE BYPASS

FLUSH CACHE
ENABLE PARITY

ERROR ABORT
WRITE WRONG
DATA PARITY

UNINTERPRETED

FORCE CACHE MISS
DIAGNOSTIC MODE

DISABLE CACHE
PARITY INTERRUPT

MR-14131

Figure 4-11

Cache Control Register (CCR) Format

4-7

Table 4-5

Cache Control Register Bit Descriptions

Bit(s)

Name

Unused, always read as cleared bits.

15:11
10

Function

Write wrong tag

parity (R/W)

When this bit is set, the CPU and DMA Tag Parity bits are both
written as wrong parity during all operations which update these
bits. A cache tag parity error will thus occur on the next access to
that location.

Unconditional cache
bypass (R/W)

When this bit is set, all references to memory by the CPU will

bypass the cache and go directly to main memory. Read or write
hits will result in the invalidation of the corresponding cache
location; misses will not affect the cache contents.

Flush cache (WO)

Writing a “1” into this bit clears all CPU tag and DMA tag valid
bits invalidating the entire contents of the cache. Writing a “0”
into this bit has no effect. Flush cache always reads as zero. The
KDJ11-B requires approximately 1 ms to flush the cache. During
the period, DMA activity is possible and CPU activity is

suspended.
07

Parity error abort

(R/W)

This bit is set for diagnostic purposes only. When it is set, a cache
parity error (during a CPU cache read) will cause the CPU to
abort the current instruction and trap to parity error vector 114.
When this bit is clear, a cache parity error (during a CPU cache
read) results in a force miss and data fetch from main memory.
The CPU will trap to 114 only if CCR bit <0> is clear. DMA
cycle cache parity errors will cause a trap to 114 if CCR <7>is
set or if CCR <0> is clear. CCR <7> has no effect on main
memory parity errors which always cause the CPU to abort the

(@2

et}

current instruction and trap to 114.

Wriie wrong ddia
parity (R/W)

When this bit is set, both the high and low data parity bits are
written with wrong parity during all operations which update these
bits. This will cause a cache data parity error to occur on the next
access to that location.

03:02

Force miss (R/W)

Diagnostic mode

When either of these bits is set, CPU reads will be reported as
cache misses.

(R/W)

When this bit is set, a 10 us nonexistent memory timeout during a
word write will not cause a nonexistent memory trap and will not
set CPU error register bit 05. All nonbypass and nonforced miss
word writes will allocate the cache regardless of the nonexistent
memory timeout.

Disable cache parity
interrupt (R/W)

This bit controls cache parity interrupts when CCR <7> is clear
(normal operation). If CCR <7> is clear, a cache parity error
(during a CPU cache read) results in a force miss and data fetch
from main memory. The CPU will trap to 114 only if CCR bit
<0> is clear. DMA cycle cache parity errors will cause a trap to
114 if CCR <7> is set, or if CCR <0> is clear.

4-8

Table 4-6 summarizes the effect of CCR <7,0> on parity errors during CPU cache reads.

Table 4-6

Cache Parity Errors During CPU Cycles

CCR<7>

CCR<0>

Result of Cache Parity Error

Cache miss and update cache; interrupt to 114.

Cache miss and update cache; no interrupt.

Abort instruction and trap to 114.

Table 4-7 summarizes the effect of CCR <7,0> on DMA tag parity errors during DMA writes.
Table 4-7

Cache Parity Errors During DMA Cycles

CCR<7>

CCR<0>

Result of Cache Parity Error

Interrupt to 114.

No interrupt.

Trap to 114.

MEMORY SYSTEM ERROR REGISTER (Address 17 777 744)

DTS PAR
DTS CMP

CPU ABORT
CACHE HB DATA PARITY ERROR
CACHE LB DATA PARITY ERROR
CACHE CPU TAG PARITY ERROR

CACHE DMA TAG PARITY ERROR
MR-14132

Figure 4-12

Memory System Error Register (MSER) Format

4-9

Table 4-8

Memory System Error Register Bit Descriptions

Bit(s)

Name

Function

CPU abort (RO)

This bit is sct if a cache or main memory parity error results in an
instruction abort (i.c., only during the demand read cycle). Cache
parity errors cause an abort only if CCR <7> is set. Main
memory parity errors always causc an abort.

DMA tag store
comparator
(DTS CMP)

In standalone mode (BCSR <8 set), this bit indicates the output
of the cache DMA tag store comparator for the previous non-1/0
page reference with cache miss. When BCSR <8> is clear, DTS

DMA tag store
parity
(DTS PAR)

In standalone mode (BCSR <8> set), this bit indicates the output
of the DMA tag store parity check logic for the previous non-1/0
page reference with cache miss. When BCSR <8> is clear, DTS

12-08

Unused

These bits always read as “07.

Cache HB data
parity error (R/W)

This bit is set if a parity error is detected in the high-data byte
during a CPU cache read. If CCR <7> is clear, MSER <7> 1S

(RO)

CMP reads as a “0”.

PAR reads as a ““0”.

also set by a low-byte parity error and by the set condition of
MSER <5> or <4>.

Cache LB data
parity error (RO)

This bit is set if a parity error is detected in the low-data byte
during a CPU cache read. If CCR <7> is clear, MSER <6> is
also set by a high-byte parity error and by the set condition
MSER bits <5> or <4>.

Cache CPU tag

parity error (RO)

This bit is set if a parity error is detected in the CPU tag field

during a CPU cache read. If CCR <7> is clear, MSER <7> is
also set by a high- or low-data byte parity error.
NOTE

Cache parity errors are ignored (do not affect
MSER <7-5>), if either CCR <3> or <2> (force
miss) is set, or if the CPU tag valid bit is clear.

Cache DMA tag

parity error (RO)

This bit is set if a parity error is detected in the DMA tag field
during a DMA write
NOTE

Cache parity errors are ignored (do not affect
MSER <4>), if either CCR <3> or <2> (force
miss) is set, or if the DMA tag valid bit is clear.

03:00

Unused

These bits always read as 0.

4-10

Main memory parity errors always cause the CPU to abort the current instruction, to
set MSER <15>
and to trap through vector location 114,

Cache parity errors which occur during a CPU cache access may result in an instruction
trap to location 114, depending on the following condition of CCR bits <7>
and <0>:

abort and/or a

If CCR <7> (parity error abort) is set, a cache parity error causes the CPU to
abort the current
instruction, to set MSER <15> and the relevant error bit(s) MSER <7:5>, and
to trap through
vector location 114.

If CCR <7> is clear, and if CCR <0> is also clear, a cache parity error causes
the CPU to
force a cache miss, set the relevant error bits MSER <7:5>, and to trap through vector
location
114.

If CCR <7> is clear, and if CCR <0> is set, a cache parity error causes the CPU to
force a
cache miss and to set the relevant error bits MSER <7:5>. The CPU does not
trap through
vector location 114.

Cache DMA tag field parity errors which occur during a DMA cycle cause a trap
to location 114 if CCR
<7>1s set, or if CCR <0> is clear.

The MSER is cleared by any MSER write reference. It is also cleared on power-up or by a
console start. [t
is unaffected by a reset instruction.

4.10

HIT/MISS REGISTER (Address 17 777 752)

]
FL(I)W

MR-14133

Figure 4-13

Hit/Miss Register Format

Table 4-9

Hit/Miss Register Bit Descriptions

Bit

Name

Function

15:06

Unused

Always read as zeros.

05:00

Cache hit

Bits enter from the right (at bit <0>) and are shifted left. A set
bit indicates a cache hit, a cleared bit indicates a cache miss.

4.11

PROCESSOR STATUS WORD (Address 17 777 776)
15

SUSPENDED

INSTRUCTION

PRIORITY
LEVEL

CARRY
OVERFLOW

2ER

L REGISTER

SET

NEGATIVE

ACE TRAP

PREVIOUS MEMORY

MANAGEMENT MODE

TRACE TRA

CURRENT MEMORY
MANAGEMENT MODE
MR-14141

Figure 4-14

Processor Status Word Register (PSW)

Table 4-10

Processor Status Word Bit Descriptions

Bit

Name

Function

Current mode

Current processor mode:

15:14

(R/W, protected)

00 = kernel

01 = supervisor
10 = illegal (traps)
11 = user

13:12
11

Previous mode

Previous processor mode, saime €ncoding as currcnt mode.

General register set select:

(R/W, protected)

0 = register set 0
1 = register set 1

Suspended

Reserved for future use.

7:5

Priority

Processor interrupt priority level.

Trace trap

Set to force a trace trap.

3:0

Condition codes

Processor condition codes.

instruction {R/W)
(R/W, protected)
(R/W, protected)

(R/W)

4-12

4.12

PROGRAM INTERRUPT REQUEST REGISTER (Address

PRIORITY ENCODED

VALUE OF BITS<15:9>

17 777 772)

PRIORITY ENCODED
VALUE OF BITS<15:9>

MR-14142

Figure 4-15

Program Interrupt Request (PIR) Register

Table 4-11

Program Interrupt Request Register Bit Descriptions

Bit(s)

Name

Function

15:09

PIR 7-1

Each bit, when set, provides one of seven levels of software
interrupt corresponding to interrupt priority levels 7 through 1.

08
07:05

Unused.
Priority encoded
value of bits
<15:09>

04
03:00

These three bits are set by the CPU to the encoded value of the
highest pending interrupt request (bits 15:09).

Unused.
Priority encoded
value of bits

The function of these bits is identical to bits 07:05.

<15:09>

4-13

4.13

CPU ERROR REGISTER (Address 17 777 766)

ILLEGAL HALT —)
ADDRESS ERROR

NONEXISTENT MEMORY
1/0 BUS TIMEOUT
YELLOW STACK VIOLATION

RED STACK VIOLATION
MR-14143

Figure 4-16

CPU Error Register Format

Table 4-12

CPU Error Register Bit Descriptions

Bit

Name

Function

Illegal halt

Set when execution of a halt instruction is attempted in user or

Address error (RO)

Set when word access to an odd byte address or an instruction

Nonexistent

Set when a reference to main memory times out.

1/0 bus timeout

Set when a reference to the 1/0 page times out.

Yellow stack

Set on a yellow zone stack overflow trap.

Red stack violation

Set on a red zone stack overflow trap.

4.14

supervisor mode.

fetch from an internal register is attempted.

memory (RO)

(RO)

violation (RO)

(RO)

CONFIGURATION AND DISPLAY REGISTER

MR-16209

X = DON'T CARE

Figure 4-17

Boot and Diagnostic Configuration Register Format

4-14

8-BIT

SWITCH PACK
X

=DON'T CARE

MR-14144

Figure 4-18

Display Register

Table 4-13

Display Register Bit Descriptions

Bit(s)

Name

Function

15::06

—

Unused

05::00

LED 5-0

These bits enable the boot and diagnostic programs to light the

LED:s located at the top of the CPU module. Clearing any of
these bits lights the corresponding LED.

4.15

MAINTENANCE REGISTER (Address 17 777 750)

—

__
J

RESERVED

UNIBUS SYSTEM
FPA AVAILABLE

MODULE TYPE (FIXED)

HALT/TRAP OPTION
POWER UP OPTION (FIXED)
BPOK H
MR-14145

Figure 4-19

Maintenance Register Format

4-15

Table 4-14

Maintenance Register Bit Descriptions

Bit(s)

Name

Function

15:11

Unused.

Reserved for future expansion. Read as zeros.
Reserved for future use.

(RO)

This bit reflects the status of the externally applied UNIBUS
adapter line. A “1” indicates that the system includes a UNIBUS

FPA

When set, this bit indicates that the FPA is available for use.

UNIBUS system

adapter.

NOTE

This bit is not used with the KDJ11-BC CPU
module.
07:04

Module type

Halt/trap (R/W)

This 4-bit code is hard-wired as a “2”, indicating a KDJ11-B
module.

This read/write bit determines the response of a processor to a

kernel mode halt instruction. Setting the bit selects the trap option,
causing the CPU to trap to location 4. Clearing the bit selects the
halt option, causing the CPU to halt and enter ODT. This bit is
cleared by the negation of DCOK and is set by the boot and
diagnostic ROM code if the trap option is selected by a bit in the
configuration RAM. The trap option is not intended for normal
use and is reserved for controller applications.

02-01

Power-up code

This 2-bit code is hard-wired as a “2”. At power-up, the processor
sets the PC to 173000 and sets the PSW to 370. It then starts
program execution at location 173000, which is the starting
location for the KDJ11-B boot and diagnostic ROM program.
These programs test out the KDJ11-B module and then implement
the user-selected power-up option specified in the configuration
data.

BPOK H

This bit is set (1) if the PMI BUS signal BPOK H is asserted,
indicating that ac power is okay.

4.16

BOOT AND DIAGNOSTIC CONTROLLER REGISTER (Address: 17 777 520)

BB RBE

l—PMG CNTO

NOT USED

PMG CNT1

FRC LCIE

PMG CNT2

DIS LKS

CLK SEL 1

RS3 WE

CLK SELO

RS3 65

ENB HOB

DIS 65

SA MODE

DIS 73
MR-14146

Figure 4-20

Boot and Diagnostic Controller Register Format

Table 4-15

Boot and Diagnostic Controller Register Bit Descriptions

Bit(s)

Name

Function

Not used

Reserved for future use.

Not used

Could be a “1” or “0”.

Force line clock
interrupt enable

If this bit is set, assertion of the signal selected by BCSR <11,10>
(clock select bits 1 and 0) will unconditionally request interrupts. If
FRC LCIE is clear, assertion of the selected signal will request
interrupts only if the line clock status register bit <6> (LCIE) is

(FRC LCIE)

set under program control. FRC LCIE is cleared by the negation
of DCOK.
12

Line clock status
register disable

(DIS LKS)
11

CLK SELI

CLK SELO

If this bit is set, the line clock status register (LKS) is disabled. If
this bit is clear, LKS is enabled and responds to bus address

17777546. DIS LKS is cleared by the negation of DCOK.

Clock select bits 1 and 0. These two bits select the source of the
line clock interrupt request:

CLK SEL1

CLK SELO

Source of Interrupt

External LTC line

On-board 50 Hz

On-board 60 Hz

On-board 800 Hz

4-17

Table 4-15

Boot and Diagnostic Controller Register Bit Descriptions (Cont.)

Bit(s)

Name

Function

Both bits are cleared by the negation of DCOK.

Enable halt on
break

When this bit is set, the console serial linc unit halt on break
feature is enabled. When this bit is clear, the feature is disabled.
ENB HOB is cleared by the negation of DCOK.

Standalone mode
(SA MODE)
(R/W)

When this bit is set, the KDJ11-B operates in standalone mode,
using its cache as main memory. External memory and peripherals
are all disabled. When SA MODE is clear, standalone mode is

(ENB HOB)
(R/W)

turned off, enabling external memory and peripherals. SA MODE
is set by the negation of DCOK.

Disable
17 773 000
(DIS 73)
(R/W)

When this bit is set, response of the 16-bit ROM memory to
addresses 17 773 000 — 17 773 776 is disabled, allowing the
operation of an external ROM that uses those addresses. When
DIS 73 is clear, the 16-bit ROMs respond to those addresses, using

Disable

When this bit is set, response of the boot and diagnostic 16-bit and

17 765 000
(DIS 65)
(R/W)

the high byte of the page control register as the most significant
address bits. DIS 73 is cleared by the negation of DCOK.

8-bit ROM memory to addresses 17 765 000 — 17 765 776 is
disabled, and allows the operation of external ROM which uses
those addresses. When DIS 65 is clear, the ROM memory selected
by BCSR <5> responds to those addresses, using the low byte of
the page control register as the most significant address bits. DIS
65 is cleared by the negation of DCOK.

ROM socket 3
at 17 765 000
(RS3 65)
(R/W)

ROM socket 3 write
enable
(RS3 WE)

This bit selects whether there is a 16-bit ROM in ROM sockets
one and two, or there is an 8-bit ROM in ROM socket three, and
17 765 776 (assuming that
responds to addresses 17 765 000
the 8-bit ROM is selected.
set,
is
65
RS3
If
clear).
BCSR <4> is

If RS3 65 is clear, the 16-bit ROM is selected. In either case, the
low byte of the page control register provides the most significant
address bits. RS3 65 is cleared by the negation of DCOK.

If BCSR <6> (DIS 65) is clear, and if BCSR <5> and <4> (RS3

65 and RS3 WE) are both set, then the program can write access
ROM socket 3 which typically contains an EEPROM. RS3 WE is
cleared by power-up and by bus initialize.

4-18

Table 4-15

Boot and Diagnostic Controller Register Bit Descriptions (Cont.)

Bit(s)

Name

Function

Unused

This bit always reads as “0”.

Processor mastership

These three bits enable the PMG counter and select the length of

grant count bits 2,

time for PMG counter overflow. When enabled, the PMG counter

1, and 0

begins counting when the KDJ11-B must access an /O page

(PMG CNT2)

location or external memory. Counter overflow causes the KDJ11-

(PMG CNT1)

B to suppress all DMA requests and give the processor bus

(PMG CNTO)

mastership during the next DMA arbitration cycle. When the
PMG counter is disabled, the processor is blocked from bus
mastership as long as DMA requests are pending. All three bits
are cleared by the negation of DCOK.
PMG CNT2

PMG CNT1

PMG CNTO

Count Time

(Disabled) *

0.4 us

0.8 us

1.6 us

3.2 us

6.4 us

12.8 us

]

25.6 us

* The PMG count of 0 (disabled) is not recommended for most
typical systems, and is reserved for special applications.

4.17

PAGE CONTROL REGISTER (Address 17 777 522)

HIGH BYTE

Figure 4-21

LOWBYTE

Page Control Register Format

4-19

MR-14879

Table 4-16

Page Control Register Bit Descriptions

Bit(s)

Name

Function

Not used

Always read as “0”.

14:09

High byte (R/W)

These six bits provide the most significant ROM address bits when

the 16-bit ROM sockets are accessed by bus addresses 17 773 000

- 17 773 776.

08:07

Not used

Always read as “0".

06:01

Low byte (R/W)

These six bits provide the most significant ROM (or EEPROM)

Not used

4.18

address bits when the 16-bit or the 8-bit ROM (or EEPROM)
sockets are accessed by bus addresses 17 765 000 - 17 765 776.
Always read as “0”.

LINE FREQUENCY CLOCK STATUS REGISTER (Address 17 777 546)

LCIE
MR-14889

Figure 4-22

Clock Status Register Format

Table 4-17

Clock Status Register Bit Descriptions

Bit(s)

Name

Function

15:08

Unused

Always read as “0”.

Line clock monitor
(LCM)

This bit is set by the leading edge of the external BEVENT line
(or of one of the three on-board clock frequencies) and by bus

(R/W)

initialize. LCM is cleared automatically on processor interrupts
acknowledge. It is also cleared by writes to the LKS with bit <7>
—

05:00

Line clock interupt

enable (LCIE)
(R/W)

Unused

660”.

This bit, when set, causes the set condition of LCM (LKS <7>) to
initiate a program interrupt request at a priority level of 6. When
LCIE is clear, line clock interrupts are disabled. LCIE is cleared

by power-up and by bus INIT. LCIE is held set INIT. LCIE is
held set when BCSR <13> (FRC LCIE) is set.
Always read as “0”.

4-20

4.19

RECEIVER STATUS REGISTER (Address 17 777 560)

RCV ACT—I
RX DONE
RX IE
MR-14147

Figure 4-23

Receiver Status Register Format

Table 4-18

Receiver Status Register Bit Descriptions

Bit(s)

Name

Function

15:12

Unused

Read as “0”.

Receiver active

This bit is set at the center of the start bit of the serial input data

(RCV ACT)
(RO)

and is cleared at the expected center (per DLART timing) of the
stop bit at the end of the serial data. Receiver done (RX DONE)

is set one bit time after RCV ACT is cleared.
10:08

Unused

Read as “0”.

Receiver done
(RX DONE)

This bit is set when an entire character has been received and is

(RO)

ready to be read from the RBUF register. This bit is automatically
cleared when RBUF is read. It is also cleared by power-up.

Receiver interupt

This bit is cleared by power-up and bus INIT. If both RCVR

enable
(RX IE)

DONE and RCVR INT ENB are set, a program interrupt is
requested.

(R/W)
05:00

4.20

Unused

Read as “0”.

RECEIVER DATA BUFFER (Address 17 777 562)

[

ERR

FRM

RCV

ERR

BRK

OVR

By
RECEIVED DATA BITS

ERR

Figure 4-24

Received Data Buffer Register Format

4-21

J
MR-14148

Table 4-19

Received Data Buffer Register Bit Descriptions

Bit(s)

Name

Function

Error (ERR)

This bit is set if RBUF <14 or <13> is set. ERR is cleared if

these two bits are cleared. This bit cannot generate a program

(RO)

interrupt.

Overrun error

This bit is set if a previously received character was not read

Framing error

This bit is set if the present character had no valid stop bit. This

before being overwritten by the present character.

(OVR ERR)
(RO)

bit is used to detect break.

(FRM ERR)

(RO)
NOTE

Error conditions remain present until the next
character is received, at which point the error bits
are updated. The error bits are not necessarily
cleared by power-up.

Unused

This bit always reads as ““0".

(RCV BRK)
(RO)

Received break

This bit is set at the end of a received character for the serial data
input remained in the SPACE condition for all 11-bit time. RCV
BRK then remains set until the serial data input returns to the

10:08

Unused

These bits always read as “0".

07:00

Received data bits

Thesc rcad-only bits contain the last received character.

421

MARK condition.

TRANSMITTER STATUS REGISTER (Address 17 777 564)
15

MAINT

TX RDY

XMIT
BRK

TXIE
MR-14149

Figure 4-25

Transmit Status Register Format

4-22

Table 4-20

Transmit Status Register Bit Descriptions

Bit(s)

Name

Function

15:08

Unused

Read as “0”.

Transmitter ready

This bit is cleared when XBUF is loaded and sets when XBUF can

(TX RDY)
06

(RO)

receive another character. XMT RDY is set by power-up and by
bus INIT.

Transmitter

This bit is cleared by power-up and by bus INIT. If both TX

interrupt enable

RDY and TX IE are set, a program interrupt is requested.

(TX IE)

(R/W)
05:03

Unused

Read as “0”.

Maintenance
(MAINT)
(RO)

This bit is used to facilitate a maintenance self-test. When
MAINT is set, the external serial input is disconnected and the
serial output is used as the serial input. This bit is cleared by
power-up and by bus INIT.

Unused

Read as “0”.

Transmit break
(XMIT BRK)

When this bit is set, the serial output is forced to the SPACE
condition. XMIT BRK is cleared by power-up and by bus INIT.

(R/W)

4.22

TRANSMITTER DATA BUFFER REGISTER (Address 17 777 566)

MR-14830

Figure 4-26

Transmitter Data Buffer Register Format

Table 4-21

Transmitter Data Buffer Register Bit Descriptions

Bit(s)

Name

Function

15:08

Unused

Always read as “0”.

XBUF

These eight bits are used to load the transmited character.

07:00

(WO)

4-23

4.23

UNIBUS MAPPING REGISTERS
5

14
o

oo}

o0
_J
RELOCATION ADDRESS
BITS 21-16
138

Hi-Address Register Format

Figure 4-27

0
0

_J
RELOCATION ADDRESS
BITS 15-01
MR-14139

Figure 4-28

Table 4-22

Lo-Address Register Format

UNIBUS Map Register Pairs
UNIBUS Addresses

Mapped via
Register Pair

1/0 Page Addresses
Hi-Register
Lo-Register

0
1
2
3

17 770 200
17 770 204
i7 770 210
17 770 214

17 770 202
17 770 206
17 770 212
17 770 216

000 000 - 017 777
020 000 — 037 777
57 777
040 000
77 777
060 000

4
5
6
7

17 770 220
17 770 224
17 770 230
17 770 234

17 770 222
17 770 226
17 770 232
17 770 236

100 000 - 117 7717
120 000 - 137 7717
140 000 - 157 777
160 000 - 177 777

]
11
12
13

17 770 240
17 770 244
17 770 250
17 770 254

17 770 242
17 770 246
17 770 252
17 770 256

200 000 - 217 771
220 000 - 237 771
240 000 - 257 777
260 000 - 277 777

14
15
16
17

17 770 260
17 770 264
17 770 270
17 770 274

17 770 262
17 770 266
17 770 272
17 770 276

300 000 - 317 777
320 000 — 337 777
340 000 - 357 7717
360 000 — 377 777

20
21
22
23

17 770 300
17 770 304
17 770 310
17 770 314

17 770 302
17 770 306
17 770 312
17 770 316

400 000 - 417 777
420 000 - 437 777
- 457 777
440 000
- 477 777
460 000

4-24

Table 4-22

UNIBUS Map Register Pairs (Cont.)

UNIBUS Addresses

I/O Page Addresses

Pair No.

Lo-Register

Hi-Register

17 770 322

500 000 - 517 777
520 000 - 537 777

17 770 320

17 770 324

17 770 326

17 770 330

17 770 332

17 770 334

17 770 340

17 770 344

17 770 350

17 770 354

17 770 360

17 770 336

17 770 342
17 770 346
17 770 352

17 770 364

540 000 - 557 777
560 000 - 577 777

600 000 - 617 777
620 000 - 637 777
640 000 - 657 777

17 770356

660 000 - 677 777

17 770 362

700 000 - 717 777
720 000 - 737 777

17 770 366

17 770 370
17 770 374

37 *

Mapped via

17 770 372
17 770 376

740 000 - 757 777
[/O Page (No Relocation)

* Can be read or written into, but not used for mapping.
4.24 OPTIONAL UNIBUS MEMORY
Table 4-23 lists the UNIBUS address s pace allocated by
the various memory configuration register
(KMCR) bit codes.

Table 4-23

KMCR Register Bits
04

UNIBUS

Memory Size
0 Kbyte

8 Kbyte

16 Kbyte

24 Kbyte

32 Kbyte

40 Kbyte

48 Kbyte

56 Kbyte
O

64 Kbyte

72 Kbyte

80 Kbyte

88 Kbyte

96 Kbyte

104 Kbyte

112 Kbyte

120 Kbyte

4-25

UNIBUS Memory
Address Range

XX 740 000 ~ XX 757 777
XX 720 000 - XX 757 777

XX 700 000 - XX 757 777
XX 660 000 - XX 757 777

XX 640 000 - XX 757 777
XX 620 000 - XX 757 777
XX 600 000 - XX 757 777
XX 560 000 - XX 757 777
XX 540 000 - XX 757 777
XX 520 000 - XX 757 777
XX 500 000 - XX 757 777
XX 460 000 - XX 757 777
XX 440 000 - XX 757 777

XX 420 000 - XX 757 777
XX 400 000 - XX 757 777

Table 4-23

KMCR Register Bits
04 03 02 01 00

UNIBUS
Memory Size

UNIBUS Memory
Address Range

0
1
0
1
0
1
10
0
1
0
1
0
1
0
1

O
0
0
0
1
1
1
1

O
O
1
1
0
0
1
]

O
1
O
1
O
1
O
]

128 Kbyte
136 Kbyte
144 Kbyte
152 Kbyte
160 Kbyte
168 Kbyte
176 Kbyte
184 Kbyte

XX 360 000 - XX 757 777
XX 340 000 - XX 757 777
XX 320 000 - XX 757 777
XX 300 000 - XX 757 771
XX 260 000 - XX 757 777
XX 240 000 - XX 757 7717
XX 220 000 - XX 757 7717
XX 220 000 - XX 757 771

1
1
1
1
1
]
]
1

0
0
0
0
1
1
]
1

0
0
1
1
0
0
1
1

O
1
O
1
O
1
O
1

192 Kbyte
200 Kbyte
208 Kbyte
216 Kbyte
224 Kbyte
232 Kbyte
240 Kbyte
248 Kbyte

XX 160 000 - XX 757 777
XX 140 000 - XX 757 777
XX 120 000 - XX 757 777
XX 100 000 - XX 757 7717
XX 060 000 - XX 757 777
XX 040 000 - XX 757 777
XX 020 000 — XX 757 7717
XX 000 000 - XX 757 777

]
1
]
]
]
]
]
]

NOTE

XX = 17 for KMCR <05> = “0” (22-bit mode).
XX = 00 for KMCR <05> = “1” (18-bit mode).

4.25

MEMORY CONFIGURATION REGISTER (KMCR - Address 17 777 734)

DMA CACHE

STATUS BITS

SELECT STATUS ——
RBT PLS

CA ENB

18-BIT MODE

UNIBUS MEMORY SIZE
MR- 1440

Figure 4-29

Memory Configuration Register

4-26

Table 4-24

Memory Configuration Register Bit Descriptions

Bit(s)

Name

Function

15:09

DMA cache status

These seven bits reflect the status of the DMA cache. KMCR

bits (RO)

<15> 1s DMA cache hit. The content of KMCR <14:09> depends
upon the value of the value of the KMCR <08> (status select).

Status select (R/W)

This bit selects the content of KMCR <15-09> (Tables 4-25 and

4-26).

Reboot pulse

This bit is set by the front panel reboot pulse which also generates
a KTJ11-B power-down/power-up cycle. RBT PLS is not cleared

(RBT PLS)

(RO)

by the assertion of DC LO during the KTJ11-B powerdown/power-up cycle initiated by the front panel reboot pulse, but
it is cleared by any other DC LO assertion.

Cache enable

This bit, when set, enables the DMA cache. When CA ENB is

(CA ENB)

clear, the DMA cache is disabled. CA ENB is cleared by the

(R/W)
05

assertion of DC LO.

18-Bit mode (R/W)

When this bit is set, the CPU can access UNIBUS memory only
when address bits <21:18> = 00. When this bit is clear, they can

access UNIBUS memory if address bits <21:18> = 17. This bit is
cleared by the assertion of DC LO. Write access to this bit is
disabled when diagnostic controller status register (DCSR) <08>

(diagnostic mode) is clear.
04:00

UNIBUS memory

size

If the system contains main memory only (no UNIBUS memory),

these five bits, as well as KMCR <05>, must be cleared. If the
system contains UNIBUS memory only (no main memory), then

KMCR <05:00> must be set. If the system contains both main
memory and UNIBUS memory, KMCR <04:00> indicate the

number of 8 Kbyte address segments assigned to UNIBUS

memory. As described in section 3.4, UNIBUS memory is
assigned downward, starting with the segment below the 1/0 page.
These bits are cleared by assertion of DC LO. Write access to

these bits is disabled when DCSR <08> (diagnostic mode) is clear.

DMA CACHE HIT

UNUSED
SET A VALID

SET B VALID
SET C VALID
SET D VALID
STATUS SELECT
MR-16207

Figure 4-30

Status Select = 0 Field Format

4-27

Table 4-25

Status Select = 0 Field Description

Bit(s)

Name

Function

DMA cache hit

This bit is updated during all writes to main memory, and all reads

from main memory. It is set if a cache hit is detected, and cleared
if a cache miss is detected. This bit is cleared when KMCR <6> 1s

clear.

14-13

Unused

Set A valid

Set B valid

Set C valid

Set D valid

Always read as “0”.

Reflects the current status of the valid bit corresponding to set A.

The bit is cleared when KMCR <6> is clear.

Reflects the current status of the valid bit corresponding to set B.

The bit is cleared when KMCR <6> is clear.

Reflects the current status of the valid bit corresponding to set C.

The bit is cleared when KMCR <6> is clear.

Reflects the current status of the valid bit corresponding to set D.

The bit is cleared when KMCR <6> is clear.

DMA CACHE HIT —-I
ATOPS B
ATOPSC

ATOPSD

BTOPSC

B TOPSD

CTOPSD
STATUS SELECT
MR-16206

Figure 4-31

Select Status = 1 Field Format

4-28

Table 4-26

Select Status = 1 Field Description

Bit(s)

Name

Function

DMA cache hit

This bit is updated during all writes to main memory, and all

DMA reads from main memory. It is set if a cache hit is detected,
and cleared if a cache miss is detected. The bit is cleared when

KMCR <6> is clear.
A Tops B

(ATPSB)

If ATPSB is set, set A is more available than set B. If ATPSB is
clear, set B is more available than set A. ATPSB is set when
KMCR <6> is clear, when set A becomes the next available set,

-and when set B becomes the least available set. ATPSB is cleared
when set B becomes the next available set, and when set A
becomes the least available set.

A Tops C
(ATPSC)

If ATPSC is set, set A is more available than set C. If ATPSC is
clear, set C is more available than set A. ATPSC is set when
KMCR <6> is clear, when set A becomes the next available set,
and when set C becomes the least available set. ATPSC is cleared

when set C becomes the next available set, and when set A
becomes the least available set.
A Tops D

(ATPSD)

If ATPSD is set, set A is more available than set D. If ATPSD is
clear, set D is more available than set A. ATPSD is set when
KMCR <6> is clear, when set A becomes the next available set,
and when set D becomes the least available set. ATPSD is cleared

when set D becomes the next available set, and when set A
becomes the least available set.
11

B Tops C
(BTPSC)

If BTPSC is set, set B is more available than set C. If BTPSC is
clear, set C is more available than set B. BTPSC is set when
KMCR <6> is clear, when set B becomes the next available set,

and when set C becomes the least available set. BTPSC is cleared
when set C becomes the next available set, and when set B
becomes the least available set.
10

B Tops D
(BTPSD)

If BTPSD is set, set B is more available than set D. If BTPSD is
clear, set D is more available than set B. BTPSD is set when

KMCR <6> is clear, when set B becomes the next available set,
and when set D becomes the least available set. BTPSD is cleared

when set D becomes the next available set, and when set B
becomes the least available set.
09

C Tops D
(CTPSD)

If CTPSD is set, set C is more available than set D. If CTPSD is
clear, set D is more available than set C. CTPSD is set when

KMCR <6> is clear, when set C becomes the next available set,
and when set D becomes the least available set. CTPSD is cleared

when set D becomes the next available set, and when set C
becomes the least available set.

4-29

4.26

DIAGNOSTIC CONTROLLER STATUS REGISTER (Address 17 777 730)

e
J
DATI GO

DNXM ERR
DIAGNOSTIC MODE

DNPR DONE

BOOT ROM DIS

DDR SELECT
MR.14150

Figure 4-32

Diagnostic Controller Status Register Format

Table 4-27

Diagnostic Controller Status Register Bit Descriptions

Bit(s)

Name

Function

Diagnostic

This bit is cleared at the start of a diagnostic NPR cycle, and set

error register

DNXM ERR is also cleared when DCSR <08> (diagnostic mode)

nonexistent memory

if there is a nonexistent memory timeout during that cycle.

(DNXM ERR)

is cleared.

14:09

Unused

These bits always read as “0”.

Diagnostic mode

(R/W)

When this bit is set, the UNIBUS is disabled and the KTJ11-B is
configured for diagnostic mode. When this bit is clear, the

UNIBUS is enabled and the KTJ11-B is configured for normal

operation. This bit is set by the assertion of DC LO.

DNPR done

This bit is set when there are no diagnostic NPR cycles pending.

DNPR done is cleared by a write to DCSR with a *“1” in bit 00,
and by any write to the diagnostic data register (DDR). DNPR
done is set by bus INIT or by completion of a diagnostic NPR
cycle.

06:04

Unused

These bits always read as 0.

Boot ROM disable

When this bit is set, response of the UBA boot ROM at addresses

(R/W)

177 773 000 - 177 773 776 is disabled, allowing operation of any

external ROM which uses those addresses on the UNIBUS. When
this bit is cleared, the UBA boot ROM responds to those
addresses. This bit is cleared by the assertion of DC LO.

02:01

DDR select (R/W)

These two bits select the contents of the DDR during read

DATI GO
(WO)

Writing a “1” into this bit sets up a diagnostic data-in NPR cycle
and clears DCSR bit 07. The NPR cycle is actually initiated by

operations. The DDR select bits are cleared by bus INIT.

the next CPU read cycle which accesses the PMI. That cycle
provides the address used in the NPR cycle. The data fetched
during that cycle is loaded into the DDR.

4-30

4.27

DIAGNOSTIC DATA REGISTER (Address 17 777 732)

0/1

| 0/1

0/1

Al6

A17

Cco
C1
PB

SSYN
MSYN
MR-14151

Figure 4-33

Table 4-28

Diagnostic Data Register Format

Diagnostic Data Register Content Descriptions

DDR Select Bits

Bit 02

Bit 01

Content of Diagnostic Data Register

Diagnostic NPR register

UNIBUS data lines D15-00

UNIBUS address lines A15-00 *

UNIBUS address lines A17-16 and various

UNIBUS control lines

* Asserted address line A16, during the diagnostic UNIBUS address lines read
operation, may cause a parity error abort.

4-31

CHAPTER 5
OPTION INSTALLATION PROCEDURES
5.1
EXPANSION POWER SUPPLY INSTALLATION
The H7202-KB expansion power supply is installed for
both types of expansion backplanes (i.e., DD11-CK
and -DK) on P-series systems. Note that this power
supply is standard on all A-series systems.
To install the expansion power supply on P-series

systems, perform the following steps.

CAUTION
Remove the ac power cord from the outlet before
performing Step 1.
1.

Open the front door using the hex key.

Remove the card cage cover by pulling out the two

plastic retainers.

Loosen the captive screws that secure the blower to

the card cage.

Slide the blower assembly out approximately 6 inches.

Disconnect the blower power plug.

Remove the blower from the cabinet by sliding it out

and up.

Push in the tray lock (Figure 5-1). This releases the
tray locking mechanism allowing it to be
pulled forward for servicing.

5-1

BRACKET

~
TRAY
HANDLE

Figure 5-1

enran

Expansion Power Supply Installation

Slide the tray forward by pulling on the tray handle until the second lock engages.
Loosen and remove the screw attached to the power supply hold-down bracket.

Remove and discard the baffle.

HANDLE

~ TRAY

Place the power supply on the extended tray; insert the closed end of the supply first.
back of the supply into the slot.
11. Once positioned inside the cabinet, guide the notched
replace the hold-down bracket securing the
12. After securing the back of the supply in the slot,

10.

front end of both power supplies.

13.

Plug in the two keyed cable connectors to the proper connector on the front of the expansion
power supply.

on supply. Use a
Secure the cable bus wires to the bus bar located on the front ofbartheendexpansi
marked +5 V. Secure
straight-slot screwdriver to secure both red bus wires to the bus
the two black cables to the bus bar end marked RTN.

5-2

5.2

15.

Attach a ground wire from the cabinet frame to the front of the expansion supply.

16.

Plug in the power connector to the proper connector on the front of the expansion supply.

17.

Repeat steps 1 through 4 in reverse order.

EXPANSION BACKPLANE INSTALLATION

As shown in Figure 5-2, the two types of expansion backplanes are:

DDI11-CK = 4-slot backplane

DDI11-DK = 9-slot backplane

DD11-CK BACKPLANE
CK ROW

N NN
/ / /)

QUAD HEIGHT
MODULE

’ 4 \\Yx\‘\\

Q%AD HEIGHT

§3

/ / /

MO[SULES

MODULE

DD11-DK BACKPLANE
ROW

QUAD

\/
vV

¥/
/)

(zj4 /

&_QUADOR

WA/
VAV,
N

— QUAD

N\
MODULE

NN NN

SIDE

[ [ /

STANDARD UNIBUS

MODIFIED UNIBUS

SLOTS

SMALL PERIPHERAL

SLOTS FOR MODIFIED

CONTROLLER (SPC) SLOTS

UNIBUS DEVICES(MUD)
MR-13228

Figure 5-2

Expansion Backplane Slot Assignments

5-3

The standard UNIBUS connectors contain all the UNIBUS connections. Rows A and B of slot | are the
beginning of the DDI1-CK and -DK, and should be occupied by the BC11-A UNIBUS in-cable.
Rows A and B of slot 9 of the DD11-DK, or of slot 4 of the DD11-CK, are the end of the UNIBUS on the
backplane. These slots should be occupied by the BC11-A UNIBUS out-cable or a terminator module
(M9302 or M9312).
5.2.1
Backplane Installation Procedure
To install the expansion backplane assembly, perform the following steps.

Remove the ac power from the power controller by setting the circuit breaker to OFF (0).

Remove the back cover using a 4 mm (5/32-inch) hex wrench to release the door fasteners.

Lower the bulkhead panel after unscrewing the 10 screws.

Remove the left cabinet side cover (viewed from the cabinet front) by lifting up from the
bottom (Figure 5-3).

5-4

EXPANSION

|L
—1 BACKPLANE

Figure 5-3

Expansion Backplane Mounting

5-5

Remove the side panel by unscrewing the four shoulder screws and two Phillips-head screws.
Remove the lexan (plastic) cover over the backplane and the metal insert(s) behind. Discard the
metal insert; it is not reinstalled.

Position the expansion backplane through the front and align the two tapped screw holes for the
DD11-CK. or the four tapped screw holes for the DD11-DK.
NOTE

The backplane harness includes a ground lead with a
lug attached. The ground must be installed under the
mounting screw.

If there are a sufficient number of NPG jumper
modules, install the modules after removing NPG

jumpers from backplane pins CAl - CB1 for all
slots.

Install the two/four 8-32 screws that are supplied with the backplane. Do not tighten the screws.
Install the backplane wiring harness connectors into the cabinet power distribution connectors.
10.

Install two hex modules in each end slot of the backplane to align the slots.

11.

Tighten the 8-32 screws installed in step 8.

12.

Remove the hex modules from the backplane.

13.

Replace the lexan cover on the backplane.

14.

Replace the side panel using the four shoulder bolts and two Phillips-head screws.

15.

Replace the outer side panel by aligning the two brackets above the shoulder boits. Lower the

16.

Close the rear panel bulkhead and tighten the captive mounting SCrews.

17.

Close the front door and lock it with the hex key.

cover brackets onto the shoulder bolts.

This completes the installation of a DD11-CK or DDI 1-DK optional backplanc.
5.2.2

NPG and BG Jumper Lead Routing

r intervenThe NPG line is the UNIBUS grant line for devices performing data transfers without processo
e.
backplan
the
tion. Continuity of the NPG line is provided by wirewraps or jumpers on
pin CB1 of that
When an NPR device is placed in a slot, the corresponding jumper wire from pin CA1intoFigure
5-4. Grant
shown
is
e
slot must be removed. The routing of the NPG signal through the backplan
slot 9 has lowest).

priority decreases from slot 1 to slot 9 in the DD 1-DK (slot 1 has highest priority and
NOTE

If an NPR device is removed from a slot, the jumper
wire from CA1 to CB1 must be reconnected.

5-6

The bus grant lines (BG4 through BG7) for non-NPR devices are routed through each slot in row D. Grant

priority for each level decreases from slot 1 to slot 9.

NOTE
A bus grant jumper card G727 in row D, or G7273
in row C and D must be installed in all unoccupied
SPC slots. If an SPC slot is left open, bus grant
continuity will be lost and the system will not
operate.

NOTE
NPG routing wire wraps are for expansion backplanes only. CPU backplane has NPG routing DIP
switch on the MDM.

ROW
REMOVABLE WIRE WRAP
O

8
9

\/ \, \‘, \/ \/ \v o

AU1 o-

[6,]

SLOT NO

* N N N N N Pe,

/>
AUT @

“" \?
MR-16403

Figure 5-4

NPG Jumper Leads Routing

5-7

5.2.3

Backplane Power Connections

Power is supplied to the expansion backplane via a wire harness that connects the power distribution board
with the power supply. The power wires run from the backplane to a set of Mate-N-Lok connectors wired

directly into the distribution board.

The power harness from the DD11-DK contains two large connectors (15-pin Mate-N-Lok) and one small
connector (6-pin Mate-N-Lok). The DD11-CK backplane has only one 15-pin connector and one 6-pin
connector. The connector pin locations are shown in Figure 5-5 and the signal assignments for each pin are
listed in Table 5-1 (DD11-CK) and Table 5-2 (DD11-dK).

PIN SIDE

6N O O
.

TO O O

\\O O O//

Key”

key”

|10

//13

V]|

;O O O]

“:U ‘\KEY

6 PIN CONNECTOR

OFT

o o of

6 ~10 © 0//4
’

l)= 4

12|

KEY

15 PIN CONNECTOR
MR-16402

Figure 5-5

Backplane Connector Designations

5-8

Table 5-1

DD11-CK Power Connector Signal Assignments

Signal

+5V

+15V

Red

Gray

Orange

Wire Gauge

Color

15-Pin Mate-N-Lok Connector

Spare

+5V

Spare (not connected)

Red

—~

+15V

Ground

Green

Ground

Black

Spare (not connected)

10
11

Black

Spare (not connected)

—~

+5V

-15V

Red

Spare

Blue

Brown

-15V

White

GND

LTC (line clock)

Black

DC LO

Brown

Violet

6-Pin Mate-N-Lok Connector

AC LO

5
6

Spare (not connected)
Spare (not connected)

Yellow
-

Wire Gauge

Color

Table 5-2

DD11-DK Power Connector Signal Assignments

Signal

+15V

Red

+15V

Gray

3
4

Spare
+5V

Orange
Red

—~

—
-

—~
14

Black

15-Pin Mate-N-Lok Connector 1

Spare (not connected)

6
7

Spare (not connected)
Spare (not connected)

8
9

Ground
Ground

Black

Ground

Black

Spare (not connected)

+5V

Red

Spare (not connected)

Brown

Spare (not connected)

5-9

Table 5-2

DD11-DK Power Connector Signal Assignments (Cont.)

Wire Gauge

Color

Signal

]

+5V

3
4

Spare
+5V

Orange
Red

+15V

White

1 5-Pin Mate-N-Lok Connector 2

Spare (not connected)

11
12

Spare (not connected)
Spare (not connected)

—

18
-~
18

-15V
Spare (not connected)
-15V

13
14
15

GND
LTC (line clock)
DC LO
AC LO

1
2
3
4

6-Pin Mate-N-Lok Connector

18
18
18
18

Spare (not connected)
Spare (not connected)

5
6

5.2.4

14
14
14

Ground
Ground
Ground

8
9
10

Red

Black
Black
Black
—

Blue
-~
Green
Black
Brown
Violet
Yellow
-

SPC Backplane Locations

The small peripheral control sections (C, D, E, and F) collectively contain all the UNIBUS lines as well as
power voltages (+5 V, +15 V and -15 V). These sections can be used by hex height or quad height modules
containing the control logic for peripheral devices. Appendix A shows the pin designations for the SPC
backplane connectors.

Appendix A also shows the pin designations of the standard and modified UNIBUS connectors. The
modified UNIBUS differs from the standard UNIBUS in that certain pins have been redesignated.
5.3

SPC MODULE INSTALLATION

CPU backplane slots 5 through 12 support the installation of UNIBUS SPC modules. Backplane slots 5
through 11 support both hex and quad SPC modules; slot 12 supports quad SPC modules only. Row A of
slot 12 supports the UNIBUS out cable connector.

Hex height SPC modules occupy all four rows of the backplane while quad height occupy rows C through
F. Quad height SPC modules, when installed, occupy the same backplane rows as the system CPU and
memory modules.

To install an SPC module, perform the following steps.

Grasp the module by the two handles mounted at the top.

Install the module in the backplane slot by sliding it in along the card cage guides.
5-10

)

L R\Y

When the module is about three-quarters installed, grasp the handles (toward the module
center) and swing them upwards, away from the module (Figure 5-6).

MR-14488

Figure 5-6

SPC Module Installation

Continue to slide the module into the backplane and press the handles downward. This action
seats the module into the backplane connectors and secures the module handles’ lower lip under
the card cage frame.

This completes the installation procedure for an SPC module.
Cabinet SPC Cable Routing

5.3.1

Use the following directions for proper cable routing.

After installing an SPC in the appropriate backplane slot, the SPC cables are plugged into the

connector and the cable is routed to the bulkhead assembly.

All SPC cables that plug into connectors mounted on the front edge of the module are routed

toward the right side of the card cage as shown in Figure 5-7.

When the connector is mounted on the top of the module, the cable is routed up and over the

1If the connector is mounted near the module handle the installed cable is routed around the

Located on the right side of the card cage are plastic cable clamps used to secure the SPC cable
to the card cage. A bar is mounted horizontally behind the card cage and used to hang the SPC

cable hanger assembly located above the card cage.

front of the card cage.

cables that are routed to the bulkhead.

5-12

Figure 5-7

Cabinet SPC Cable Routing

MR-14485

5-13

Box SPC Cable Routing

5.3.2

Use the following directions for proper cable routing.

After installing an SPC in the appropriate backplane slot. the SPC cables are plugged into the

connector and the cable is routed to the bulkhead assembly.

The back panel has two bulkhcad assembly areas, bottom left and top right (referenced from

Cables that plug into connectors mounted on the handle of the module are routed toward the

Cables that plug into connectors mounted at the module top (installed in backplane) are routed

the rear).

lower left bulkhead.

to the upper right bulkhead (Figure 5-8).

CAPTIVE
SCREWS

SCREWS

SPC CABLE

MR.1433%

Figure 5-8

Box SPC Cable Routing

5-14

5.4 CABINET BATTERY BACK UP UNIT INSTALLATION
To install the BBU complete the following procedure.
CAUTION

The weight of the BBU is 19 kg (42 Ibs); lifting and
positioning of the BBU requires two people.
1.

Unpack the BBU and installation kit.

Remove the BBU from the shipping container and place it on a flat surface.

Set the front panel TOY switch to OFF (Figure 5-9).

I
TOY

VOLTAGE

ON/OFF

SELECT

C1D

1
MR-15497

Figure 5-9

Set the rear BBU AC VOLTAGE SELECT to match the front panel VOLTAGE SELECT
switch setting (Figure 5-10).

BBU AC INPUT
CONNECTOR (J22)

FAULT INTERFACE CONNECTOR (J20)
(FAILSAFE JUMPER)

Set the BBU VOLTAGE SELECT switch to match the site line voltage.

BBU Front Panel

BBU INPUT

AC VOLTAGE SELECT

SWITCH =240
1156—

GROUND STUD FOR

USER INTERFACE

DC POWER QUTPUT

CONNECTOR (J18)

DC POWER QUTPUT

CONNECTOR (J9)

POWER CONTROLLER
BUS CONNECTOR (J19)
MR-15498

Figure 5-10

BBU Rear Panel

Open the front and rear cabinet doors using the hex key.

Turn off the power supply and power controller circuit breakers.
Unplug the ac power cord from the outlet.

Remove the cabinet right side panel by lifting it straight up from both sides (Figure 5-1 1).

LSHOULDER SCREW (4)

@J/I'

\)’

%fl

SIDE PANEL

Figure 5-11

10.

‘

// ~ &‘// ;‘7/// SCREW (2)

emishieLD

_ i

MR-13321
Side Panel Removal

Remove the two Phillips-head and four shoulder screws securing the EMI panel to the cabinet
frame.

11.

Carefully lift and line up the BBU enclosure with the four screws protruding from the cabinet
frame (Figure 5-12).

”\r/;
P|

IQE

—

]

CARD CAGE

/ASSEMBLY

U-NUT

/W/1OI-3§ SCREW (4)
RETAINER

[ TBre-

/
S
\I

}

/fil %@:
A )
‘ j

“~

10-32

KEPNUT

(4)

LINE
FILTER

877-D/F
POWER

BATTERY BACKUP

UNIT (H7231-E)

CONTROLLER
MR-15499

Figure 5-12

Mounting the BBU

12.

Position the BBU on the four mounting screws and slide it against the cabinet frame.

13.

Install and tighten four 10-32 hex nuts (from the installation kit) on the mounting screws,
securing the BBU to the frame.

14.

Remove all cables from the installation kit.

15.

Install the two-position keyed jumper into mating connector (J20) on the BBU rear panel.

16.

Plug one end of the keyed cable (7020396), with ground wire, into the BBU mating connector
J9).

17.

Remove the hex nut on the BBU ground stud. Place the ground wire from the cable on the stud.

Replace and tighten the hex nut.
18.

Plug the other end of the keyed cable, with ground wire, into the line filter bracket connector
marked BB-J1. Place the cable ground wire on the stud.

19.

Install a 10-32 hex nut (from the installation kit) on the stud. Tighten the nut to secure the
ground wire.

20.

Plug one end of the other keyed cable (7008288) into the mating BBU power controller bus
connector (J19). Plug the other end of the cable into the 877-D/F power controller connector

marked either J8 or J9.

5-17

21. Plug the ten-position connector of the signal cable (1700730) into the mating polarized connector located at the top right of the card cage assembly.

22. Attach the cable ground wire to the stud with the 10-32 hex nut provided. Sccure the wire by
tightening the nut.

23. Plug the other end (D-sub) of the cable into the mating connector (J18) on the BBU. Tighten
the self-retaining screws on the connector.

24. Plug the appropriate power cord (120 V or 240 V) into the BBU and plug the other end of the
cord into the remaining unswitched outlet on the 877-D/F power controller.

75 Check each installed cable to ensure that none were damaged during reinstallation of the EMI
shield.

26. Reverse steps 6 through 8 to reinstall the EMI shield and side panel.
This completes the installation procedure.

5.5

BOX BATTERY BACK UP UNIT INSTALLATION

To install the BBU complete the following procedure.

CAUTION

The weight of the BBU is 19 kg (42 lbs); lifting and
positioning of the unit requires two people.

Unpack the BBU and installation kit.

7. Remove the BBU from the shipping container and place it on a flat surface (Figure 5-13).

IR
TOY
ON/OFF

VOLTAGE
SELECT

Figure 5-13

BBU Front Panel

Set the front panel TOY switch to OFF.

Set the VOLTAGE SELECT switch to match the site line voltage.

5 Set the rear BBU AC VOLTAGE SELECT switch to match the front panel VOLTAGE
SELECT switch (Figure 5-14).

5-18

FAULT INTERFACE CONNECTOR (J20)
(FAILSAFE JUMPER)

/EQE\\

BBU AC INPUT

CONNECTOR (J22)

BBU INPUT

AC VOLTAGE SELECT
SWITCH =240

15—

E.a

GROUND STUD FOR

USER INTERFACE

DC POWER OUTPUT

CONNECTOR (J18)

DC POWER OUTPUT
CONNECTOR (J9)

POWER CONTROLLER
BUS CONNECTOR (J19)
MR-15498

Figure 5-14

BBU Rear Panel

Follow the directions supplied with the rack and carefully secure the BBU to the rack.

Turn off the box circuit breaker (Figure 5-15).

CIRCUIT
BREAKER

MR-14336

Figure 5-15

Circuit Breaker Location

5-19

Unplug the ac power cord from the ac outlet.

Loosen the four captive screws that secure the box top cover. Remove the cover (Figure 5-16).

CAPTIVE
SCREWS

SCREWS

SPC CABLE

MR-14335

Figure 5-16

Top Cover Removal

5-20

10.

Remove the blank rear bulkhead panel B1 by loosening the two Phillips-head screws that secure

it to the bulkhead (Figure 5-17).

SLU

CONNECTOR
FORCED

BAUD

DIALOG

BULKHEAD

SWITCH

VAR

[

BULKHEAD— ]
-

111
11
il
MR-13443

Figure 5-17

Bulkhead Location

5-21

Remove the BBU panel from the installation kit.

Route the two attached cables through the bulkhead opening that was occupied by panel Bl.

Install the BBU panel (Figure 5-18) in the bulkhead opening and tighten the two flat-hcad

screws into the bulkhead frame.

ool

]

N_B

E—
MR-15515

Figure 5-18

BBU Connector Panel

14.

Label and remove the cables from the module slot MDM through slot 4.

15.

Remove the five modules from the backplane.

Plug the signal cable connector (10-position) into the backplane PC board mating connector

(J12) (Figure 5-19).

POWER SUPPLY

BBU

BULKHEAD B1

BACKPLANE

/fi

|/
MR-15436

Figure 5-19

17.

BBU Cables and Locations

Plug the other BBU cable connector (3 position) into the panel-mounted mating connector

located behind the rear of the power supply.

18.

Reinstall the five modules. Make certain that they are seated properly in the backplane.

19.

Plug the cables into their module connectors.

20.

Remove the remaining two cables from the installation kit.

21.

Install the two-position keyed jumper into mating connector (J20) on the BBU rear pancl

(Figure 5-20).

BBU AC INPUT

FAULT INTERFACE CONNECTOR (J20)

CONNECTOR (J22)

(FAILSAFE JUMPER)

:
LH

il
BBU INPUT

AC VOLTAGE SELECT

SWITCH =—240
115 —

GROUND STUD FOR

USER INTERFACE

DC POWER QUTPUT

CONNECTOR {J18)

DC POWER OUTPUT
CONNECTOR (J9)

POWER CONTROLLER
BUS CONNECTOR (J19)

Figure 5-20

MR-15498

BBU Rear Panel

NOTE
BBU connector J19 is not used with this system.

5-24

22.

Plug one end of the keyed cable (7020396), with ground wire, into the BBU

mating connector

Remove the hex nut on the BBU ground stud. Place the ground wire from the

cable on the stud.

(J9).
23.

Replace and tighten the hex nut.

24.

Plug the other end of the keyed cable, with ground wire, into the
BBU bulkhead panel
connector (J1). Place the cable ground wire on the stud.

25.

Install a 10-32 hex nut (from the installation kit) on the stud. Tighten the
nut to secure the
ground wire.

26.

Plug the signal cable (1700730) into the mating polarized connector located
on the BBU
bulkhead panel. Attach the cable ground wire to the stud with the 10-32 hex
nut provided.
Tighten the nut.

27.

Plug the other end (D-sub) of the cable into the mating connector on the BBU. Tighten
the selfretaining screws on the connector.

28.

Replace the top cover of the box and tighten the captive screws.

29.

Plug in the appropriate power cord (120 V or 240 V) to the BBU and plug in the other
end of
the cord to the ac power outlet.

This completes the installation of the BBU.

5-25

APPENDIX A
BACKPLANE PIN ASSIGNMENTS
-

ROW

SIDE
PIN

NPG

+5V

GND

+5Vv

ABG

+5V

15v

-15v

ASSYN

-15Vv

ABG

{IN)

NPG

(OuT)
PA

GND

6
D15

A12

Al17

A15

BBSY

A16

FO1

D02

FO1

D14

A SEL

BR6

D13

A SEL

BRS

AQ2

Cc1

D05

D06

D11

D12

A IN

BR4

A SEL

A BR

SSYN

NPR

ouT

’

L
D10

D09

A INT

Do8

A OUT | BG?

ENBB

INIT

MSYN

L
A0

Do8

AINT

BG?

All

D03

FOI

AQUT

INTR

FO1

ouT

BG6

AIN

ENBA

D04

AINT

BG6

HALT

REQ

HALT

D01

GRT
PB

GND

D03

LOW

A10

AQ7

ABR

FO1

ourT

BGS

A09

ASEL

FOI1

FO1

ouT

BG4

ASEL

FO1

GND

BG4

GND

ASEL

GND

SACK

AINT

ABR

ourT

D02

D06 | ASSYN

L
L

M2
D04

BGS

+15

L
FO1

ouT

HIGH
A OUT | AD8

L
D00

ENB B
GND

AINT

D005

L
A INT

A13

L
D07

007

L
AQO

Al14

GND

A INT

SSYN

Low

GND

A OUT | BR7?

15v

A SEL

L
LTC

ouT

IN H

ABG

2
AO6

A04

ouT

ABG

A0S

A03

AINT

FOI

ouT

ENBA | FOI
MR-16203

Figure A-1

SPC Backplane Pin Assignments

A-1

STANDARD UNIBUS

MODIFIED UNIBUS

PIN DESIGNATIONS

ROW

SIDE

de
2

INIT [+5V

|BGE

+5V

INTR|GND BG5S

GND

Pin
A

D00
c

U
\Y

GND

D02
L

D04

(D03

D06

|DO5

|GND

BR4

|GND

BG4

|AC

(Lot

Lo L

D08

|D0O7

|A01

A0O

D10

|D09

[A03

AD2

INTR[

D00 | GND|

D04
L

D06
L
D08

|AOS

A04

D12}

D11|

D14

|D13

lA07

A06

|D15

|Aa09

A08

GND |PB

A1l

A10

|BBSY| A13

GND

L
|SACK]

GND

‘
GND

GND

|NPR | A17

BG7

A16

|BR7

{GND

|GND

|BR6

A15 | A4

NPG

A12

|SSYN | €O
L

D14|

D13]|

PA | D15]|
L

A07 | AO6
L

AD9 | AO8
L

PB | A11 ] A10

PAR|
P1

PAR

|BBSY|

+15

[SACK|
.

BAT4
15

A05 | AD4

A13 | A12

A15 | A14

| NPR | A17 | A6

BAT

GND | BR7

+20 | BR6

CORE

|GND | €1
L

|SSYN|

IMSYN | GND

ES PIN
A REDESIGNATED
NOTE: D INDICAT
Figure A-2

D10 | D09 | AO3 | AD2

BR5 | GND
L

{D11

D02

|RESV(
PIN

D12

+5V

|DO1

INIT | +5V |RESV|

|GND |BRS

(CORE]}

1R 16204

Standard and Modified Backplane Pin Assignments

A-2

APPENDIX B
WORKSHEET

The purpose of this worksheet is to report and confirm the setup parameters to be contained in the setup

EEPROM on the KDJ11-BF CPU module.

Fill out this worksheet when you install a KDJ11-BF CPU module. It will contain all pertinent information
for changes made to the setup parameters and programming any future replacement KDJ11-BF CPU
modules.
Once filled out, leave it with the system for future use.
Use a pen to fill out the current blocks and pencil for the new blocks.

NOTE
Use SETUP command 1 to exit and SETUP command 7 to list current values (at time of change) and
to ensure that the changes you made have been
programmed correctly.

B-1

SETUP Command 2

Table B-1

Settings

A - Enable halt on break

B - Disable user friendly format

C - ANSI video terminal

D - Power-up

E - Restart

F - Ignore battery

(0-7)

G - PMG count
H - Disable clock CSR

I - Force clock interrupts

J - Clock
K - Enable ECC test

L - Disable long memory test

*Ex

M - Disable ROM
N - Enable trap on halt

O - Allow alternate boot block

P - Enable UNIBUS memory test

Q - Disable UBA ROM

R - Enablc UBA cache (1)
~

Yes

B-2

Q
@]

172

O\E:O

through

2 =60 Hz
2=

2 =

50 Hz
Dis 165
0.8 sec

Automatic

(O
A
T

ek
pd
et

|
|I A

4 sec

None

)

0-7

[

X %k %k

Dialog
Power supply

Z S Z

% %k

coocoo

Designation

S - Enable 18-bit mode

New

Current

Designation

Parameters

Table B-2

SETUP Command 3

Translation Tables

Current

TT!
Device name
Unit #
CSR address
TT2
Device name
Unit #
CSR address

TT3
Device name

Unit #
CSR address
TT4

Device name

Unit #
CSR address
TTS
Device name

Unit #
CSR address
TT6

Device name

Unit #
CSR address
TT7

Device name
Unit #
CSR address
TTS8

Device name

Unit #
CSR address
TT9

Device name

Unit #
CSR address

B-3

New

Table B-3

SETUP Command 4

Current

Automatic Boot Device
Boot |

Device name

Boot 2
Device name
Boot 31

Device name

Boot 4

Device name

Boot 5

=
=

Device name
Boot 6

Device name

=
=

B-4

New

Table B-4 SETUP Command 5
(At the present time, this set-up command is not used.)

Current

O XTI

NP WN—OD

Non-English

T
O
T
|

V0NN
AW
—O

English

B-5

New

SETUP Command 6

Table B-5

Switches 2, 3, 4
2

ON (Special)

OFF (SB 1)

OFF

ON (SB 2)

OFF

OFF (SB 3)

OFF

ON (SB 4)

OFF

OFF (SB 5)

OFF

ON (SB 6)

OFF

OFF (Normal)

Current

B-6

New

Digital Equipment Corporation ¢ Maynard, MA 01754