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EK-11070-MM-002

November 1979

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Document:	PDP-11/70 Maintenance and Installation Manual
Order Number:	EK-11070-MM
Revision:	002
Pages:	363
Original Filename:

OCR Text

EK-11070-MM-002

PDP-11/70
maintenance and

installation manual

digital

equipment corporation - maynard, massachusetts

Preliminary Edition, November 1975
1st Edition, January 1977
2nd Edition, May 1979

The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this

manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

PDP

RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

TYPESET-11

UNIBUS

10/79-14

CONTENTS

PROCESSOR AND MEMORY
Electrical .
.
Power Requ1rements
Power and Heat Dissipation .
Mechanical Characteristics
Environmental Specifications .
RH70 PERIPHERAL DEVICES .

RELATED DOCUMENTATION

Table 1-6 lists the reference manuals for the minimum PDP-11/70 configuration and for the processor
backplane options particular to the PDP-11/70.
Small Peripheral Controller (SPC) manuals other than the DL11, as well as manuals related to other
peripheral options, are supplied with the equipment.

Table 1-6 Related Documentation
Title

Document Number
PDP-11/70 Manuals*

KB11-B Processor Manual (PDP-11/70)

EK-KBI11B-TM-001

MJ11 Memory System Maintenance Manual
MKI11 MOS Memory System Technical Manual
FP11-C Floating-Point Processor Maintenance Manual**
FP11-B Floating-Point Processor Maintenance Manual**
LA36 DECwriter Maintenance Manual
DL11 Asynchronous Line Interface Manual
KW11-L Line Time Clock Manual
861A-F Power Controller Maintenance Manual
RWS04/RWSO05 Fixed Head Disk Subsystem
Maintenance Manual**
RWP04 Moving Head Disk Subsystem
.

EK-MJ11-MM-002
EK-MK11-TM-001
EK-FP11C-MM-PRE
EK-FP11-MM-003
EK-LA36-MM-001
DEC-11-HDLAA-B-D
EK-KWI11L-TM-002
EK-861 AB-MM-002

Maintenance Manual**

EK-RWS04-MM-001

EK-RWP04-MM-001

TWUI16 Magnetic Tape Subsystem

Maintenance Manual**

EK-TWU16-MM-001

M9312 Bootstrap/Terminator Module
Technical Reference Manual
M9301 Bootstrap/Terminator Module

EK-M9312-TM-001

Maintenance and Operator’s Manual

EK-M9301-TM-001
Reference Handbooks

PDP-11/70 Processor Handbook

PDP-11 Peripherals and Interfacing Handbook
*A set of engineering drawings is provided with each of the components and options in the PDP-11 system.
**Optional

1.3

REFERENCE DRAWINGS

An Engineering Print Set, which includes all electrical schematics and mechanical assembly drawings
related to a system, is supplied with each PDP-11/70.

1.3.1
DIGITAL Drawing Numbers
Figure 1-4 shows the numbering system used for DIGITAL drawings.
1.3.2

Drawing Conventions

Figure 1-5 illustrates some of the drawing conventions used on the PDP-11/70 circuit schematics.

In this figure, part A defines the meaning of each part of a typical signal mnemonic.
1-15

E-C§-M8139-0-1

? lt——— Series

Original drawing size —J

Manufacturing variation
Drawing type

CS:

Circuit Schematic

BS:

Block Schematic

DD:

Drawing Directory

MU:

Module Utilization

AD:

Assembly Drawing

UA:

Unit Assembly

WL:

Wire List

PL:

Parts List

Module type, equipment type,

or a 7-digit DEC part number

Inseparable Assembly

IA:

Master List (replaced by DD in new drawing sets)

ML:

~ Interconnecting Cabling

IC:

Figure 1-4

Drawing Nomenclature

IRC

__J |

MB8132

MODULE

TMCE

ASSERTION

SIGNAL

74500 \5
M

LEVEL

MNEMONIC

B L

CO H

SHEET B OF MODULE
SCHE MATIC

SAPK C1

RABOQ4,

IRC

SAPL

E76

ER2

DATIP

SSRE

RELOC

19 |

SAPL ABORT COND H M

74500 \8 AP
INH PSEUDO T3 L
9:D)—-—'SSRC
c
&13

trca

1ROS

(1) H

{
L
745740—9—I RCA IRO5 (1)

E15 In2
__ IrcA IRO5 (0)L
0

IRCA

IROS5

(0) H

?13

IRCH V (1) H

sas7aP—— IRCH V (1)L

)

SLLE

E79 b8 1rch v ()L
0

Tio

IRCHV (O)H

E (D REDEFINED!

11- 5428

Figure 1-5

PDP-11/70 Drawing Convention Examples
1-16

Part B provides the following information:

SAPL DATIP L originates on the SAP (M8137) module and is shown on sheet L of the

“drawing. It is asserted when low (0 V); it is used only on SAP.

SAPK Cl B L also originates on the M8137 module, but is shown on sheet K of the sche-

TMCE C0 H originates on the TMC (M8135) module, where it is shown on sheet E. It is

The SAPL DATIP L NAND gate uses pins 4, 5, and 6 of the 74S00 IC at position E76 on

matic.

input to the M8137 module at pin R2, row E (ER2).
the M8137 module.

a function similar to that in part B. In this case, however, the output (SSRC INH
Part C shows
PSEUDO T3 L) is brought out to pin P1, row A, of the module edge connector for use by another
module.

Parts D and E show the flip-flop conventions. Note in D that IRCA TIR05 (1) H is the same pin as
IRCA IRO05 (0) L, and that IRCA IRO05 (1) L is the same pin as IRCA IR05 (0) H. The same type of
flip-flop has been redefined in part E - the D input is inverted; the 1 and 0 outputs are interchanged as
are the set and reset inputs.
1.3.3

Reference Drawings

Table 1-7 lists the schematic drawings for the minimum PDP-11/70 configuratibn and for the processor backplane options particular to the PDP-11/70.
Table 1-7

Reference Drawings
Drawing Number

Title

PDP-11/70 System Drawings
B-DD-11/70-0
B-DD-KB11-B
B-DD-H7420-0
-DD-KWI11-L
-DD-DLI11-A
-DD-LA36-0
-DD-M1J11-0
-ML-KM11-0
-CS-M9301-YC-1
-CS-M9302-0-1
-CS-H873-0-1
-UA-11/70-0-0
A-PL-11/70-0-0
D-IC-11/70-0-2
J-IA-7011051-0-0
D-IC-7011051-0-1
- D-UA-BCO6R-0-0
A-AL-11/70-0-3
E-AR-11/70-0-1

lelvivhk
3L LA

Drawing Directory PDP-11/70
Drawing Directory KB11-B
Drawing Directory H7420
Drawing Directory KW11-L
Drawing Directory DL11-A
Drawing Directory LA36
Drawing Directory MJ11
Master Parts List KM11
Terminator Bootstrap
Bus Terminator
Terminator H873

Unit Assembly PDP-11/70
Unit Assembly PDP-11/70 (PL)
Power System Configuration
Harness Power
Wire List Power Harness
I/0 Cable BCO6R

Accessory List PDP-11/70
System Expansion PDP-11/70

1-17

Table 1-7

Reference Drawings (Cont)
Drawing Number

Title

KB11-B, C Processor

Unibus Cable and Grant Chain
Data Paths

Gen Reg and ALU. Controls
IR Decode (KB11-C requires CS Rev. B or higher)
Console Board
Proc. Data and Unibus Control
ROM and ROM Control*
ROM and ROM Control**
Timing Generator

Traps and Misc. Control
Unibus and Console Control
Timing Diagram
Flow Diagram
Address Memory Board
Cache Control Board
Cache Data Paths
Block Diagram
Data Memory Board
Memory Mgmt Block Diagram
Memory Mgmt Registers

Cache Address Timing
Int. Reg. Cycle Timing
Memory Mgmt Trap Timing
System Address Paths

System Descriptor and Console Cables**
System Descriptor and Console Cables*
System Status Registers
Unibus Map (M8141) B.D.
Unibus Map
Processor Backplane
Awt Rev Status

B-DD-KBI11-B
A-PL-KB11-B-0
D-FD-KBI11-B-1
D-BD-KB11-B-2
D-BD-KB11-B-3
-IC-KB11-B-7
-CS-M8130-0-1
-CS-M8131-0-1
-CS-M8132-0-1
-CS-5411294-0-1
CS M8134-0-1
S-M8123- 0 1

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Lo Lo e AvAvAOAwAN

Drawing Directory KB11-B
16-Bit Processor
Flow Diagrams
Block Diagram
Block Diagram

C S- M8137 0 |
-C S-M8138-YA-0-1
-C S-M8140-0-1
-C S-M8138-0-1
-BD-KB11-B-6
D-CS-M8141-0-1
E-AD-7010329-0-0
'A-WT-7010329-0

H7420 Power Supply
Drawing Directory
Wiring Diagram
Power Line Monitor
H7420 Power Supply
H7420 Power Supply (P.L.)
*KB11-C Processor
**K B11-B Processor

B-DD-H7420-0
D-CS-H7420-0-1
D-CS-5411086-0-1
E-UA-H7420-0-0
A-PL-H7420-0-0

Table 1-7

Reference Drawings (Cont)

Title

Drawing Number
KW11-L Line Frequency Clock

Timing Diagram
Line Frequency Clock
Line Clock
Line Frequency Clock
Software List

D-TD-KW11-L-02
D-BS-KW11-L-01
D-CS-M787-0-1
A-PL-KW11-L-0
A-SL-KWI11-L-28
DL11-A Asynchronous Line Interface

Drawing Directory
Asynchronous Line Interface
Asynchronous Line Interface (PL)
Asynchronous Line Interface
Cable Assembly (KL8/E)
Software List
Accessory List
Installation Procedure

B-DD-DL11-0
C-UA-DL11-0-0
A-PL-DL11-0-0
E-CS-M7800-YA-11
D-IA-7008360-0-0
A-SL-DL11-0-4
A-AL-DL11-0-5
A-S-DL11-0-2
LA36 DECwriter

LA36 Option Arrangement

D-AR-LA36-0-1
D-CS-LA36-0-5
D-CS-M7722-0-1
D-CS-5410805-0-1

LA36 Power Schematic
Logic Board (LA36)
LA36 Power Board

MJ11 Memory System
Drawing Directory MJ11-A

B-DD-MJ11-A
E-UA-MJ11-A-0
B-DD-7010694-0
-PL-MJ11-A
-BD-MJ11-A-BD
-TD-MJ11-A-TD
CS-M8148-0-1
CS-M8149-0-1
CS-G114-0-1
CS-H217-C-1
C S-G235-0-1
C S-5411553-0-1
C S-5411581-0-1
C S-5411583-0-1
IA-7010580-0-0

wlwi- ivivivivivivivivivivlw o 3>

Unit Assembly MJ11-A
Power Supply (MJ11)
Parts List MJ11-A
Block Diagram (MJ11) (M8148)
Timing Diagram Read/Write
Memory Control and Timing Module
Memory Transceiver Card
16K Sense Inhibit Board
16K X 18 Bit Stack
16K Memory Drive Board
Circuit Schematic Memory
Circuit Schematic (MEM-EL-FAB)
Circuit Schematic (MEM-EL-FAB)
Power Harness
Wire Harness ac/dc Low
Power Control 861-D
Power Control 861-E
Exp. Data Cable Assembly
Exp. Cable Assembly (Inter Bay)

-IA-7010581-0-0

-DD-861-D
-DD-861-E
-AD-7010824-0-0
-AD-7010826-0-0

1-19

Table 1-7

Reference Drawings (Cont)
Drawing Number

Title

MJ11 Memory System (Cont)

D-1A-7010974-0-0
A-SP-3700195-0-0

Cable Detail

Packaging Instruction
(Customer Ship)
Packaging Instruction
(Interplant)

A-SP-3700194-0-0
D-CS-M8147-0-1
D-CS-G116-0-1
D-CS-H224-0-1
D-CS-G236-0-1

Memory Control and Timing Module
32K Sense Inhibit Board
32K X 18 Bit Stack
32K Memory Drive Board

MK11 Memory System

o
o

vl WoOOoOwoOUOUwOU woOOoOO oeBlovlive

B-DD-MK11-B
E-UA-MK11-B-O
A-PL-MK11-B-O
E-AR-11/70-0-5
E-AD-7014226-0
D-BD-MK11-0-3
D-TD-MK11-0-4

Drawing Directory MK11
Unit Assembly MKI11
Parts List MKI11
11/70 System Expansion (MK11)
Backplane MK11 Memory
MKI11 Block Diagram
MKI11 Timing Diagrams
Power Control 861
Power Supply H765
Battery Backup Regulator
Power Supply Regulator
MKI11 Address Interface

-DD-H765-0
-DD-7014251-0
-CS-5411086-0-1
-CS-M8158-0-1
UA-M8158-0-0
PL-M8158-0-0
CS-M8159-0-1
UA-M8159-0-0
PL-M8159-0-0
CS-M8160-0-1
UA-M8160-0-0
-PL-M8160-0-0
-CS-M8161-0-1
-UA-M8161-0-0
-PL-M8161-0-0
-CS-5413018-0-1
B-UA-5413018-0-0
B-PL-5413018-0-0
MP00014
MP00271
MP00325

MK 11 Data Buffer

MKI11 Control A

MKI11 Control B

MK11 Box Controller

M775 Battery Backup Unit
H7441 +5 V Regulator
MSI11-K MOS Storage Array

1-20

Table 1-7

Title

Reference Drawings (Cont)
Drawing Number

FP11-C Floating Point Processor (Optional)

Drawing Directory
Flow Diagrams
M8126 FRH Module Schematic
M8127 FRL Module Schematic
M8128 FRM Module Schematic
M8129 FXP Module Schematic

B-DD-FP11-C-0
D-FD-FP11-CD-CS-M8126-0-1
D-CS-M8127-0-1

D-CS-M8128-0-1
D-CS-M8129-0-1

FP11-B Floating Point Processor (Optional)
Drawing Directory
MS8112 FRM Module Schematic
M8113 FXP Module Schematic
" M8114 FRH Module Schematic
MS8115 FRL Module Schematic
FP Data Paths (Flows)

B-DD-FP11-B-0
E-CS-M8112-0-1
E-CS-M8113-0-1

E-CS-M8114-0-1
E-CS-M8115-0-1
D-FD-FP11-BRH70 Controllers (Optional)

B-DD-RH70-0
D-UA-RH70-0-0
D-CS-M8150-0-1
-CS-M8151-0-1
-CS-M8152-0-1
-CS-M8153-0-1

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Drawing Directory RH70
Massbus Controller
Massbus Data Path
Control and Status
Addr. and Word Count Regs.
Unibus Control
Massbus Transceiver
Unibus Cable and Grant Chain
RH70 Data Buffer Timing Diag.
‘Write Massbus Timing Diag.
Massbus Timing Diag.
Write Command Flow Diag.
Write Check Command Flow Diag.
Read Command FLow Diag.
Controller Transceiver
Massbus Terminator

-BS-RH70-0-1
-IC-KB11-B-7
-TD-RH70-0-5

-TD-RH70-0-6
-TD-RH70-0-7
-FD-RH70-0-2
-FD-RH70-0-3
-FD-RH70-0-4
-CS-M5904-0-1
-CS-H870-0-1

1-21

CHAPTER 2
SPECIFICATIONS
This chapter lists the power, mechanical, and environmental specifications of the basic components of
the PDP-11/70 system, as well as those of the Massbus devices.
2.1

PROCESSOR AND MEMORY

Electrical

2.1.1

2.1.1.1

Power Requirements — The basic 120 V PDP-11/70 requires 90-132 Vac (phase to neutral), 47

to 63 Hz, 3-phase wye at 30 A /phase for each cabinet.

The basic 240 V PDP-11/70 requires 180-264 Vac (phase to neutral), 312-457 Vac (phase to phase), 47
to 63 Hz, 3-phase wye at 15 A /phase for each cabinet.

2.1.1.2 Power and Heat Dissipation — A PDP-11/70 with FP11, four high-speed 1/O Controllers, five
small peripheral controllers, and 128K baud of memory consumes approximately 3000 W and dissipates approximately 10,000 Btu/hr. Refer to Paragraph 4.3.2.
The same PDP-11/70 with a full interleaved MJ11 memory cabinet (1024K baud) consumes approximately 5000 W and dissipates approximately 18,000 Btu /hr.
An additional 1024K bytes of MJ11 memory would add approximately 2800 W and 8200 Btu/hr to
these figures.

Each fully populated

MK 11 memory consumes approximately 500 W of power and dissipates approx-

imately 1700 Btu/hr.

Power Surge

Processor cabinet (phases | and 2), 200 A/phase, 10 ms max.

Each MJ11 frame adds 160 A /phase/10 ms max.

NOTE

The preceding figures can be considered worst case,
although actual current demand is a function of activity and of variations in individual components.

The FP11-B and -C require 200 W max and dissipate 500 Btu/hr.
Each RH70 controller consumes 200 W and dissipates 700 Btu /hr.

Power requirements for small peripheral controllers are listed in Appendix F.

Detailed specifications for the 861-D, E Power Control are listed in Chapter 4 of this manual.

2-1

2.1.2

Mechanical Characteristics

The overall dimensions of the cabinets supplied with the PDP-11/70 are:
Height

Width
Depth

Weight without shipping pallets

Shipping pallets

2.1.3 Environmental Specifications
Operating Environment Range
Temperature
Relative Humidity

Altitude

181.3 cm (71-7/16 in)

108 cm (43-3/8 in)
76 cm (30 in)

With cabinet feet: 99 cm (39 in)

CPU cabinet: 227 kg (500 1b)
Memory cabinet with 64K bytes: 163 kg (360 1b)
Memory frame with 64K bytes: 57 kg (125 Ib)
Single cabinet: 17 kg (38 1b)
Double cabinet: 29 kg (65 1b)

10° C to 40° C (50° to 104° F)
10% to 90% with max wet bulb 28° C (82° F)
and minimum dew point 2° C (36° F)

To 2.4 km (8000 ft)

Non-Operating Environment Range
Temperature
-40° C to 66° C (-40° F to 151° F)
Relative Humidity
To 95%
Altitude
To 9.1 km (30,000 ft)

Recommended Operating Environment
Temperature
18.5°-23.8° C (65°-75° F)
Relative Humidity
40-60%
Peripheral media may restrict the ranges just described. Refer to Paragraph 2.2 and to Appendix F.

2.2
2.2.1

RH70 PERIPHERAL DEVICES
TU16 Magtape Drive

Electrical
Voltage and current (single phase)

94-126 V, 60 Hz +2%, 8 A (9 A with TM02)
207-253 V, 50 Hz £2%, 4 A (4.5 A with TMO02)
Surge Current (max): 85 A at 94-126 V
Power Consumption and Heat Dissipation
1000 W, 3400 Btu/hr (1100 W, 3700 Btu/hr with TM02)

Mechanical
Weight
Size

Environmental
Operating Temperature

Relative Humidity

'
228 kg (500 1b) with cabinet
181.3cmh X 54 cmw
X 76 cm
d
(72-7/16 in h X 21-11/16 in w X 30 in d)

15° C to 35° C (60° F to 95° F)
20 to 80% (no condensation)

(Magnetic tape operation is more reliable if the temperatureis limited to 18° C to 24° C (65° F to
75° F) and the relative humidity 40% to 60%.)
2-2

2.2.2

RP04 Disk Pack Drive

Electrical
Voltage and Current
60 Hz £1%

50 Hz £1%

Power Consumption
Heat Dissipation
Power Factor

Mechanical
Weight
Size

Environmental

Operating Temperature
Relative Humidity

3-phase wye at 208 Vac £10%
Starting Current: 30 A /phase, 10 ms max
Running Current: 8.2 A/phase at 208 Vac
3-phase wye at 380/408/420 Vac £10%
Starting Current: 16 A /phase, 10 ms max
Running Current: 4.3 A/phase at 408 Vac
2100 W

7000 Btu/hr
0.7

270 kg (600 1b)
102cmh
X 79cmw
X 81 cm d
(40inh X 31inw
X 32 in d)

15° C to 32° C (60° F to 90° F)
20% to 80%, maximum wet bulb 25° C
and minimum dew point 2° C

2.2.3 RSO03 and RS04 Disk Drives
Electrical
Voltage and Current (single phase) 90-132 V, 60 £1 Hz or 50 £1 Hz, 6 A

180-264 V, 60 =1 Hz or 50 +1 Hz, 3 A

Surge Current

13 A at 90-132V
6 A at 180-264 V

Power Consumption
Heat Dissipation

700 W

Mechanical (Drive Only)
Weight

RS04: 54.4 kg (120 Ib)
RS03: 50 kg (110 1b)

Size

400 mm h X 482.6 mm w X 665 mm d
(15-3/4inh X 19inw X 26-1/4ind

With Cabinet
Weight
Size

Environmental

Operating Temperature
Relative Humidity

2.3

2400 Btu/hr

159 kg (350 1b)
181.3cmh
X 54cmw
X 76 cm d
(71-7/16 in h X 21-11/16 in w X 30 in d)

10° C to 22° C (50° F to 104° F)
10% to 90%
Max wet bulb: 22° C (82° F)
Min dew point: 2° C (36° F)

UNIBUS INTERFACE

Specifications for the Unibus devices available to the PDP-11/70 are listed in Appendix F.
2-3

CHAPTER 3

SYSTEM INSTALLATION

3.1

GENERAL

This chapter contains installation information and recommendations to ensure a successful PDI?11/70 installation. Installation of new options in an existing PDP-11/70 system is also described in this
chapter.

Customer assistance is provided during site planning, preparation, and installation; the final layout
plan should be approved by both the customer and DIGITAL prior to delivery of the equipment.
Planning considerations should include:

Shipping and access routines, e.g., door, hall, passageway, elevator restrictions, etc.

Floor plan layout for equipment

Electrical and environmental considerations

Fire and safety precautions

Storage facilitiqs for accessories and supplies.

Site preparation is dictated by the customer’s requirements and can range from providing the required
source power to complete construction or remodeling of the selected installation site. Therefore, it is
recommended that any and all requirements and restrictions be considered and effected prior to shipment and installation of the equipment.
3.2

SITE PREPARATION

Adequate site planning and preparation simplifies the installation process. DIGITAL Sales and Field
Service Engineers are available for consultation and planning with customer representatives regarding
objectives, course of action, and progress of the installation. The information in this paragraph is
provided primarily to permit review of the site planning; use the site configuration worksheet to perform the initial site planning.

For more detailed information, refer to the XXX Site Preparation and Planning Guide (Where “XXX”’
stands for a Product Line, e.g., TELCO, IPG, DECCOM).
3.2.1

Physical Dimensions

The overall dimensions and total weight of a particular system - the dimensions, weight of any optional cabinets, cable lengths, and the number of free-standing peripherals — should be known prior to
shipment.

The route the equipment is to travel from the customer receiving area to the installation site should be
studied; measurements of doors, passageways, etc., should be taken to facilitate delivery of the equipment. All measurements and floor plans should be submitted to the DIGITAL Sales Engineer and
Field Service to ensure that the equipment is packed to suit the installation site facilities. Any restru,
tions (such as bends or obstructionsin hallways, etc.) should be reported to DIGITAL.
If an elevator is to be used to transfer the PDP-11/70 and its related equipments to the installation site,

DIGITAL should be notified of the size and gross weight limitations of the elevator so that the equipment can be shipped accordingly.
The site space requirements are determined by the specific system configuration to be installed and,
when applicable, provisions should be made for future expansion. To determine the exact area
required for a specific configuratlon a machine-room floor plan layoutis helpful. When applicable,
space should be providedin the machine room for storing tape reels, prmter forms, card files, etc. The
integration of the work area with the storage area should be consideredin relation to the work flow
requirements between areas.
In large installations where test equipment is maintained, DIGITAL recommends that the test equipment storage area be within or adjacent to the machine room.
:
Operational requirements determine the specific location of the various options and free-standing
peripherals of the system. Dimensions, weights, and cable lengths of free-standing peripheral equipment must be known prior to installation - preferably during site preparation
and planning. The
computer peripherals must not be located at distances where connecting cables exceed maximum limits. The following points should be considered when planning the system layout:

Ease of visual observation of input/output devices by operating personnel

Adequate work area for installing tapes, access to console, etc.

Space availability for contemplated future expansion

Proximity of the cabinets and peripherals to any humidity-controlling or air-conditioning
equipment

Adequate access to equipment (e.g., rear door, etc.) for service personnel.

The final layout will be reviewed by the DIGITAL Sales Engineer, Field Service, and in-house engineering personnel to ensure that cable limitations have not been exceeded and that proper clearances
have been maintained.
3.2.2
Fire and Safety Precautions
The following fire and safety precautions are presented to aid the customer in maintaining an installa-

tion that affords adequate operational safeguards for personnel and system components.

If an overhead sprinkler system is used, a dry pipe system is recommended. Upon detection
of a fire, this system removes source power to the room and then opens a master valve to fill
the room’s overhead sprinklers.

If the fire detection system is the type that shuts the power to the installation off, a batteryoperated emergency light source should be provided.

If an automatic carbon dioxide fire protection system is used, an alarm should sound prior
to release of the CO2 to warn personnel in the installation area.

3-2

If power connections are made beneath the floor of a raised floor installation, waterproof
electrical receptacles and connections should be used.

An adequate earth ground connection should be provided to protect operating personnel.

3.2.3

Environmental Requirements

An ideal computer room environment has an air distribution system that provides cool, well-filtered,
humidified air. The room air pressure should be kept higher than that of adjacent areas to prevent dust
infiltration.

3.2.3.1 Humidity and Temperature - The PDP-11/70 specifications, as well as those of the peripheral
devices that may be associated with it, are listed in Chapter 2 and in Appendix F.

3.2.3.2 Air-Conditioning - When used, computer room air-conditioning equipment should conform
to the requirements of the ‘“‘Standard for the Installation of Air-Conditioning and Ventilating Systems
(non-residential)”, N.F.P.A. No. 90A, as well as the requirements of the Standard for Electronic
Computer Systems, N.F.P.A. No. 75.

3.2.3.3 Acoustical Damping - Some peripheral devices (such as line printers and magnetic tape transports) are quite noisy. In installations that use a group of high noise level devices, an acoustically
damped ceiling will reduce the noise.

3.2.3.4 Lighting - If CRT peripheral devices (e.g., VT05, VT50) are part of the system, the illumination surrounding these peripherals should be reduced to enable the operator to observe the display
conveniently.

3.2.3.5 Special Mounting Conditions - If the system will be subjected to rolling, pitching, or vibration
of the mounting surface (e.g., aboard ship), the cabinetry should be securely anchored to the installation floor by mounting bolts. Such installations require modifications to the cabinet: arrangements for
modifications of this type should be made through DIGITAL’s Computer Special Systems Group.
3.2.3.6 Static Electricity - Static electricity can be an annoyance to operating personnel and may
affect the operational characteristics of the PDP-11/70 and related peripheral equipments. If carpeting
is installed on the computer floor, it should be of a type designed to minimize the effects of static
electricity. Flooring consisting of metal panels, or flooring with metal edges should be adequately
grounded.

3.2.4

Electrical Requirements

The PDP-11/70 operates from a nominal 3-phase 115 V, 50/60 Hz or 3-phase 230 V, 50/60 Hz, ac
power source. The primary ac operational voltages should be maintained within the tolerances defined
in Chapters 2 and 4.

For certain options that use synchronous motors, line voltage tolerance should be maintained within
+ 15 percent of the nominal values, and the 50/60 Hz line frequency should not vary more than +2 Hz.
Primary power to the system should be provided on a line separate from lighting, air-conditioning,
etc., so that computer operation will not be affected by voltage transients. The wiring should conform
to the following general guidelines:

All electrical wiring must conform with the National Electric Code (NEC).

The ground terminal on the receptacle is normally a green screw; the neutral terminals are

white or silver; and the “hot” terminals are brass-colored.

3-3

Under the NEC (in the U.S. only), the color coding for the neutral wire is either white or
gray, and the ground wire is solid green, green with one or more yellow stripes, or bare.
There are no specified colors for the ““hot” wires.

The PDP-11/70 cabinet grounding point should be connected to the building power transformer
ground or the building ground point. Direct any questions regarding power requirements and installation wiring to the local DIGITAL Sales Engineer and/or Field Service.

Chapter 4 contains a detailed description of the Power System and includes a list of connectors and
plugs used.
3.2.5 Related Documents
The following documents contain information that may be of value during site preparation and planning operations:
1.

Plant Engineering Handbook, by William Staniar (McGraw Hill)

National Electrical Code (NFPA 70)*

Protection of Electronic Computer/Data Processing Equipment (NFPA 75)*
Installation of Air-Conditioning and Ventilation Systems (non-residential) (NFPA 90A)*
Recommended Good Practice for the Maintenance and Use of Portable Fire Extinguishers
(NFPA 10A)*

Installation of Portable Fire Extinguishers (NFPA 10)*
Lightning Protection Code (NFPA 78)*
ASHRAE Handbook, (American Society of Heating, Refrigeration, and Air-Conditioning
Engineers)

Computer Talk, Vol. 1, No. 1, 3M Company
10.

Computer Decisions, Vol. 2, No. 10

11.

ANSI Standard X3.11 (1969)

12.

ISO Recommendation R1681 (1970)

13.

U.L. Handbook No. 478, Underwriters Laboratories, Inc.

14.

NBFU No 70, National Board of Fire Underwriters

15.

EIA Standard RS-232C, Electronics Industries Association

16.

Digital Supplies Catalog, Digital Equipment Corporation

17.

IEEE Standard 142-1972.

*NFPA Standards and publications are available from the National Fire Protection Association, 60 Batterymarch Street, Boston, Massachusetts 02110.

3-4

3.3 INSTALLATION
The installation procedure for a PDP-11/70 is essentially the same as that for all other PDP-11s. This
installation procedure is described in the PDP-11 Family Field Installation and Acceptance Procedure.
EK-FS003-IN, which should be followed and initiated as shown as the various steps are performed.
This paragraph summarizes the PDP-11 Faily Field Installation and Acceptance Procedure; procedures and details that pertain especially to the PDP-11/70 are inserted.

The PDP-11 Family Field Installation and Acceptance Procedure should be used in conjunction with
the Installation Checklist, a computer printout in three parts:
1.
2.
3.

3.3.1

Stand alone diagnostics to be run
DEC/XI11
System Software Exerciser (under development)

Chapter 2 of the PDP-11 Family Field Installation and Acceptance Procedure
WARNING
Do not unskid the equipment until the procedures
outlined in this paragraph (3.3.1) have been
completed.

Do not plug in the ac power until told to do so in
Paragraph 3.3.3.3.

Check the shipment for damage and inventory as described in EK-FS003-IN.
Figures 3-1 through 3-4 show the shipping retainers used in the PDP-11/70 processor and memory
cabinets:
1.

Figure 3-1 shows the tie wrap that secures the front door of the memory cabinet.

Figure 3-2 is a front view of the memory cabinet and shows the shipping bracket that secures
each memory frame during shipment.

Figure 3-3 shows the rear of the processor cabinet and the shipping bracket that must be
removed before pulling out the CPU drawer.

The tie wrap mentioned in step 1 and the two brackets shown in Figures 3-2 and 3-3 are the only items
that are added to the basic PDP-11/70 for shipping. Figure 3-4 shows the lower portion of the memory
cabinet as it is shipped.
Document any damage and call it to the attention of the customer. If the damage is extensive, report it
to the Branch Service Manager or Supervisor immediately. DIGITAL is not responsible for shipping
damage on systems that are F.O.B. from the manufacturing facility.

3-5

TOP OF MEMORY CABINET "
P

v ¥ ‘,,/\f‘”

TIE-WRAP HOLDS FRONT
DOOR OF MEMORY

CABINET CLOSED

7554-8BW-0165

Figure 3-1

View of Inside Top of Memory Cabinet as Shipped

3-6

7554 1BW-A-0163

Figure 3-2

Front View of Memory Cabinet as Shipped

3-7

LAEED

0P O
4

TORE

UPPER POWER SUPPLY
H7428
RED SHIPPING BRACKET
HOLDS KBA1-B PROCESSOR

DRAWER DURING
SHIPMENT

| LOWER POWER SUPPLY
LY

POWER CABLE FROM ——=—="7"""
861 POWER CONTROL

Figure 3-3

Rear View of Processor Cabinet as Shipped

MEMORY BUS CABLE FROM CPU

‘Q\\\\Q\\
NEPA Teop

/ |

OWER.GABLE FROM
MEMORY FRAME TO

861 POWER CONTROL

POWER CABLE FROM

. 861 POWER CONTROL,

7554-6-BW-A0164

Figure 3-4

Rear View of Memory Cabinet as Shipped

3-9

Chapter 3 of the PDP-11 Family Field Installation and Acceptance Procedure

3.3.2

Move the equipment to the installation site and remove the cabinets from the skids. Insert filler strips
and bolt the cabinets together.

Lower the leveling feet so the cabinets are not resting on the roll-around casters. Ensure that all
leveling feet are planted firmly on the floor and the system is kept level.
WARNING

System cabinets with heavy drawers fully extended
are unstable when feet are not lowered.

Memory frames (drawers) must not be pulled out until the memory cabinet(s) are bolted to another cabinet.

Connect all ground straps; ensure that all ground connections are metal to metal, i.e., scrape off all
paint at ground connection points. Lay out the I/O cables, but do not connect at this time. Check the
physical layout with the configuration sheet.

Chapter 4 of the PDP-11 Family Field Installation and Acceptance Procedure

3.3.3

3.3.3.1

Grounding - Connect the system to the independent earth ground provided by the customer.

3.3.3.2 AC Power Supply Checks - Check the customer’s ac power for proper voltage and phasing.
Check that the power receptacles are wired correctly, and that ac ground is connected to all ground
pins in all power receptacles for this system.

WARNING

It is very important that safety ground be maintained
throughout the system to minimize the possibility of
injury to personnel and damage to equipment.

Check the Customer’s ac power as follows:

Refer to Figure 3-5, which shows the ac power receptacle required for the PDP-11/70.
Measure the voltage between each of the three phases and neutral at the receptacle. The
voltage should be between the limits defined in Chapter 2.

Approximately the same voltage should be read between each phase and the earth ground
terminal.

EARTH

GROUND

<7
NEUTRAL

)

$2
+3
11-3466

Figure 3-5

NEMA L21-30R Receptacle

In order to balance the three phases in the PDP-11/70, the phase rotation must be identical in all
connectors used for the processor and memory cabinets (Figure 3-6).

Check the voltage between Phase 1 on one connector and the corresponding Phase 1 on
another connector. Voltage reading should be 0 V.

Repeat step 1 for Phases 2 and 3.

If the voltage reading is not 0 V, one of the connectors is miswired. The customer must have
the wiring corrected before plugging in the PDP-1 1/70.

OA/’\

¥ \\\\\\‘

O
EARTH
GROUND

—_—

300 ACV

EARTH
GROUND

¢1

NEUTRAL

-— 2
—

NEUTRAL

$2
$3

11 -3467

Figure 3-6

3.3.3.3

AC Phase Rotation

Equipment Power Checks

NOTE
The PDP-11/70 power system is described in Chapter 4 of this Manual.
Check all ac, dc, and signal cables.

Visually inspect all modules for any hardware that may be lodged between them. Vibrate all the
modules to help dislodge any loose hardware or solder splashes.

Disconnect all Unibus cables that interconnect the system cabinets.
TURN OFF all the circuit breakers on all 861 power controls. Ensure that all fixed head disk motors
are switched off at the unit (i.e., RS03, RS04) (Figure 3-7).

3-11

MEMORY

TU16

MEMORY

// //////
-7

RPO4

RS03/04

CPU

RKO5

100
Y,

W
-t
REAR

MEMORY

CPU

RS©3/04

RK®5

MEMORY

TUl6

i, ///)
i
A

WY,
g
i
L

KX X
X K | 861
X X | 861
X 4 | 861
gel

861&[2

FRONT

[X] DENOTES CIRCUIT BREAKERS
11 - 3333

Figure 3-7

PDP-11/70 Circuit Breaker Location

Plug all the system 861 ac line cords into the customer receptacles. Put the LOCAL/REMOTE switch
on all 861s to the LOCAL position.

NOTE

861-E power controls are shipped without a power
cord.

3.3.3.4 System Cabinet Checks - Starting with the CPU cabinet, do the following for each cabinet in
the system:

Turn ON the main ac circuit breaker on the 861 power control. Also turn on the console key

Check for correct ac voltage output from all the 861 ac outlets: the meter reading between
points P and N on Figure 3-8 should be 95 to 132 Vac on a 120 V system, and 180-264 Vac
on a 240 Vac system; the reading between terminals P and G should be the same as those

in the case of the CPU cabinet.

between P and N.

Check all fans.

Check all dc voltage levels and ripple with the proper test equipment and adjust to specification. Table 3-1 lists the voltage test points for the CPU and Table 3-2 lists those for the
MJ11. Table 3-3 lists the voltage test points for the MK11. Test points for peripheral equipment are listed in their respective manuals.
3-12

125v - 15A

()

125V-20A

861-A,C,F

861-D

250V~ 15A
861-E
11-3468

Figure 3-8

Table 3-1

Output

Slots

Supplied

861 Power Control Outlets

H7420 Voltage Measurements*

Measure at CPU

Backplane pin

Max Ripple

Peak-to-Peak V

Voltage

H744 +5V

2-5

F02A2

+5V

0.2 Vdc

H744 +5V

1, 6-9

F09A2

+5V

0.2 Vdc

H744 +5V

10-15

F15A2

+5V

0.2 Vdc

H744 +5V

36-44

F44A2

+5V

0.2 Vdc

H744 +5V

20-22

F22A2

+5V

0.2 Vdc

H744 +5V

16-18

F18A2

+5V

0.2 Vdc

H744 +5V

24-28

F28A2

+15V

0.2 Vdc

H744 +5V

29-35

F35A2

+5V

0.2 Vdc

Upper H7420

BO1Bl1

+8 V61.2Vdc

0.24 Vdc

Upper H7420

40-44

E13A1

+15V 61.5 Vdc

0.45 Vdc

Lower H7420

2,17,

E13B2

-15V £1.5Vdc

0.45Vdc

Regulator A

Regulator B
Regulator C

Regulator D
Regulator H
Regulator J

Regulator K

Regulator L

5411086
5411086

5411086

25-27
29-31
33-35
37-44

*Use a digital voltmeter, Data Technology Model 31, or Weston-Slumberger Model 4443, or equivalent.
3-13

Table 3-2

Regulator Test Points (MJ11)

M8149

Test Point*

Regulator

Backplane

Voltage

Pins

Connector Pins

744 No. 4
744 No. 2
754 No. 3
754 No. 1
754 No. 3

+5 Vdc
+5Vdc
+20 Vdc
+20 Vdc
-5 Vdc

J16-2,5
J14-2,5
J15-5
J13-5
J15-3

J21-5,6,7,8
J18-1,2,3,4
J21-3,4
J18-5,6
J21-1,2

754 No. |

-5 Vdc
TP Ground

J13-3

J18-7.,8

Regulator

TP1
TP2
TP3
TP4
TP5
TP6
TP7

*These test points are located approximately 1.5 inches from the edge of the M8149 that faces the front of the
cabinet. TP1 is the top test point. Refer to Figure 4-43.

Table 3-3

Regulator Voltage Measurements (MK11)
Regulator

Backplane

Regulator

Voltage

Pins

Connector Pins

Slots Supplied

H7441

+5 Vdc

J14-1,2,5

J18-1,2
J21-7

10-17

7014251 ‘A’

+5Vdc
+12 Vdc
-12 Vdc

J13-4
J13-1
J13-6

J18-4
J18-5
J18-7

6-13
6-13
6-13

7014251 ‘B’

+5Vdc
+12 Vdc
-12 Vdc

J15-4
J15-1
J15-6

J21-5
J21-4
J21-2

15-21
15-21
15-21

7014251 ‘C

+5Vdc
+12 Vdc
-12 Vdc

J16-4
J16-1
J16-6

J21-6
J21-3
J21-1

2-5,22-25
2-5,22-25
2-5,22-25

Turn all ac power breakers to the OFF position.

Set all LOCAL/REMOTE switches to the REMOTE position, and verify that the remote
sensing cables are installed.

Check all free-standing peripherals.

Install all the Unibus, Massbus, and peripheral cables. Install Unibus terminator at the end
of the Unibus.

Put the ac breakers on the power control(s) and supplies to the ON position.

3-14

Preliminary System Check - Load all disk and magtape units with Scratch packs and tapes.

3.3.3.5

Since the PDP-11/70 bootstrap module (M9301-YC) contains a diagnostic, all the preliminary CPU
checks listed in Chapter 4 of the PDP-11 Family Field Installation and Acceptance Procedure need not
be performed.

Turn on the CPU key and ensure that the power comes up. Check ac/dc low on the Unibus for proper
levels (>4.0 Vdc).

Figure 4-37, ACLO and DCLO CIRCUITS, shows all points where ACLO and DCLO may be

checked.

3.4

SYSTEM CHECKOUT (Chapter 5 of PDP-11 Family Field Installation and Acceptance Pro-

cedure)

The system checkout is intended to prove the integrity of the PDP-11/70.
It consists of the following operations (refer to Figure 3-9):
1.

Checking the console functions

Booting the XXDP diagnostic monitor via the M9301-YC

Running the CPU and applicable peripheral diagnostics, and

Running the system software exerciser, if available.

When these have been run successfully and the customer has accepted the system, the installation is
complete.

If the system fails, refer to Chapter 5 (Maintenance) for troubleshooting procedures. No failures are

permitted during the CPU, cache, main memory, memory management, Unibus map or (optional)

floating point processor diagnostics. The error criteria for peripheral equipment are specified in the
PDP-11 Family Field Installation and Acceptance Procedure.

Refer to Figure 3-9, which is a detailed installation checkout procedure. The several steps in this
flowchart are explained in the paragraphs that follow.
3.4.1

Console Functions

Refer to Section III, Chapter 1 of the KB11-B Processor Manual or to the PD-11/70 Processor Hand-

book for a detailed description of the console and its operation.
3.4.2

Bootstrap Modules

The M9301-YC, -YH, and M9312 modules contain ROM programs located on the peripheral page, as
shown on the memory map in Figure 3-10; note that the programs take up part of the user addresses
(17 765 000 - 17 765 776) and all the bootstrap addresses (17 773 000 - 17 773 776). Paragraph 5.4.11
lists the programs and a brief explanation of their operation.

The ROM programs check the CPU first, then main memory, and the cache. Then it boots the XXDP
monitor from the device selected. Note that early versions of XXDP load only from drive unit number
|

zZero.

Figure 3-9 summarizes instructions for using the M9301 and M9312. If the low order byte of the
Switch register contains 0, a default device and drive are selected by switches on the M9301.

3-15

LOAD ADDRESS

( INSTALLATION )

DEPOSIT & DEPOSIT/STEP
EXAMINE & EXAMINE/STEP

FROM GENERAL REGISTERS (ADDRESSES 17 777 700- 17)

{FROM MEMORY (ANY OTHER EXISTING ADDRESS)

START
CONTINUE
|

CHECK

CONSOLE
FUNCTIONS

BOOTSTRAP
M9301-YC

DIAGNOSTIC

BOOT

l——
_— ___

F———————

r——

—_LOAD ADDRESS 17 765 000
LOAD DEVICE CODE (OCTAL) INTO SWITCH REGISTER <06:03>
(ALL DEVICES HAVE XXDP AVAILABLE AT THIS TIME)
TM11/TU10
MAGNETIC TAPE, TM11
TC11/TUb6
DECtape, TC11-G
DECpack DIS CARTRIDGE, RK11-D
RK11/RK05
RP11/RP0O3
DISK PACK, RP11-C
RK611/RK06 DISK*
RH70/TU16
MAGNETIC TAPE SYSTEM, TWU16
RH70/RP0O4
DISK PACK, RWP04
10)
RH70/RS34
FIXED HEAD DISK, RWS04 (OR RSWO03)
11)
RX11/RX01
DISKETTE
(*NOT AVAILABLE ON EARLY VERSIONS OF M9301-YC)
LOAD DRIVE NUMBER 000 INTO SWITCH REGISTER
<02:00> DRIVE 0 IS REQUIRED, SINCE XXDP
AT PRESENT LOADS ITS MONITOR FROM DRIVE 0.
LOAD THE PHYSICAL MEMORY BLOCK DESIRED (OCTAL) INTO
SWITCH REGISTER <15:12>.

0)
1)

PHYSICAL MEMORY
PHYSICAL MEMORY

2)
3)

PHYSICAL MEMORY
PHYSICAL MEMORY

PHYSICAL MEMORY

5)
6)
7)
10)
12)

PHYSICAL MEMORY
PHYSICAL MEMORY
PHYSICAL MEMORY
PHYSICAL MEMORY
PHYSICAL MEMORY
PHYSICAL MEMORY

13)

PHYSICAL MEMORY

14)

PHYSICAL MEMORY

16)

PHYSICAL MEMORY

11)

00 000 000 - 00 077 776
00 100 000 - 00177 776
00 200 000 - 00277776
00 300 000 - 00 377 776
00 400 000 - 00477776
00 500 000 - 00577 776
00 600 000 - 00677 776
00 700 000 - 00777776
01 000 000 - 01077 776
01 100 000 - 01177776
01 200 000 - 01277776
01 300 000 -01 377776

16)

PHYSICAL MEMORY

01 400 000 - 01477776
01 500 000 - 01577776
01 600 000 - 01677776

17)

PHYSICAL MEMORY

01 700 000 - 01777776

40)

PHYSICAL MEMORY

17 700 000 - 17777 776

START

XXDP

IS
LOADED

MESSAGE TYPED ON LA36. REFER TO “XXDP USER
MANUAL,” MAINDEC-11-DZQXA FOR DETAILED
EXPLANATION.

TO SHEET 4,

FIG. 39

Figure 3-9

System Checkout (Sheet 1 of 4)

3-16

( INSTALLATION )

SELECT FUNCTIONS VIA MICROSWITCHES (S1)
- $1-10
S1-9

S1-8

TURN

OFF

DIAGNOSTIC ON/OFF SWITCH
OFF, DEVICE CODE FROM SWITCHES
ON, DEVICE CODE FROM CONSOLE
DEVICE CODE

POWER

OFF, RUN MEMORY-MODIFYING TESTS

ON, NO MEMORY-MODIFYING TESTS
POWER UP REBOOT ENABLE

LOW ROM ENABLE

SWITCH
S1-2 ON

YES

LOAD
ADDRESS

17773000
v

LOAD DEVICE
CODE AND

—

DEVICE CODES SW REG<06:03>

?
2

3
3

DRIVE NUMBER

SWITCH REGISTER

‘

INTO

PRESS

READ MICROSWITCHES
MAGNETIC TAPE
TTMM11/TU10
DECTAPE
TC11/TU56
DISK
RK11/RKO05
DISK
RP11/RP0O3
DISK
RK611/RK06
MAGNETIC TAPE
RH11-RH70/TU16
DISK
RH11-RH70/RP0O4
RH11-RH70/RS04
FIXED HEAD DISK
RX11/RX01
FLOPPY DISK
PC11
PAPER TAPE READER

DRIVE NUMBER SW REG<02:00>

START

M9301-YH

DIAGNOSTIC

BOOT

BOOTSTRAP

MESSAGE TYPED ON LA36 REFER TO
“XXDP USER MANUAL"” MAINDEC-11-DZQOXA
FOR DETAILED EXPLANATION.

XXDP
IS

LOADED

TO SHEET
4
FIG. 39
TK-1467

Figure 3-9

System Checkout (Sheet 2 of 4)

FROM SHEET 1,2,0R 3
FIGURE 3-9

RUN DIAGNOSTICS IN THE FOLLOWING
ORDER: DEKBA THROUGH DEKBG, DEQKC,

RUN SYSTEM
DIAGNOSTICS

DEMJA, DZKWA, DZDLA FOR BASIC PDP-11/70;

DERHA FOR RH70; RH70 MASSBUS DEVICE
L DIAGNOSTICS; ALL OTHER OPTION DIAGNOSTICS.

REFER TO “DEC/X11 USERS DOCUMENTATION

RUN DEC/X11

AND REFERENCE GUIDE,"”
MAINDEC-11-DXQBA.

EXERCISER

IF APPLICABLE: DOES NOT EXIST FOR ALL
OPERATING SYSTEMS AT THIS TIME. REFER

RUN SYSTEM
SOFTWARE
EXERCISER

TO APPROPRIATE MANUAL.

END OF

SYSTEM TEST

Figure 3-9

TK-1470

System Checkout (Sheet 4 of 4)

3-19

pheds”
rlotel . ‘aludel ‘cholud dhotute” « tadudu’"

773776
773 700

}

M9301-YC

MAINTENANCE LOADER

> CACHE

DIAGNOSTIC

773 676
773 606

773&)4_-___—_—_—__*—_—_—*“{

M9301-YH

. AND

773 400

M9312

BOOTSTRAPS

773 376
773 300
773276

BM792-YC CARD

M9301-YC/YH

773 200

773 176

BOOTSTRAPS

:
MR11-DB

BM792-YB DISK/DECtape

773 100

773 076
773 000

5767 774 |

- INPUT BUFFER

:OUTPUT BUFFER:

767 772

NOT USED BY

4 7~ M9301-YC/YH

USER ADDRESSES{|

OR M9312

M9301-YC
CPU, MEMORY MGMT.
& MAIN MEMORY DIAG.

765 776

765 000

M9301 DIAGNOSTIC

M9301-YH

CPU, MEMORY

& CACHE TEST

“ M9312 DIAGNOSTIC

FLOATING 1
ADDRESSES 3

TK-14€6

Figure 3-10

Location of M9301-YC, YH and M9312 in Peripheral Page

(Refer to PDP-11 Peripherals Handbook)

3-20

The diagnostic portion of the programs test the basic CPU, including the branches, the registers, all
addressing modes, and most of the instructions in the PDP-11 repertoire. Then it sets the stack pointer
to Kernel D-space PAR 7, checks and turns on, if requested, memory management and the Unibus
map, and checks memory from virtual address 1000 to 157776. After main memory has been verified,
with the cache off, the cache memory is tested to verify that hits occur properly. Then main memory is
scanned again to ensure that the cache is working properly throughout the 28K of memory to be used
in the boot operation.

If one of the cache memory tests fails, the operator can attempt to boot the system anyway by pressing
CONTINUE. This causes the program to force MISSES in both groups of the cache before going to
the bootstrap section of the program.

The bootstrap portion of the programs look at the lower byte of the Switch register to determine which
device will attempt the boot for load-address start sequences. (Note that XXDP loads only from drive
0). With the M9301, switches (02:00) select the drive number (0-7 octal), and switches (06:03) select the
device code (1-11 octal). If the lower byte of the Switch register is zero, the program reads the set of
switches on the M9301 to determine the device and drive number. These switches can be set to select a
default boot device. With the M9312, switch register switches (11:0) select the starting address of one
of the ROM Boot Programs installed on the module. Each device has its own boot ROM, the address
in the switch register selects one of the four ROMs on the module

Automatic boot on power-up is available with both the M9301-YH and the M9312. When enabled, the
module will boot the device selected by switches on the module when the processor power is turned on.
If the bootstrap operation fails as a result of a hardware error in the peripheral device, the program
will perform a RESET instruction and jump back to the test that sets up and turns on memory management and tests memory. Then the program attempts to boot again.
Starting Procedure, M9301-YC

3.4.2.1

Switch Settings — The lower byte of the Switch register should be set to have the drive number (0-7
octal) in switches (02:00), and the device code (1-11) in switches (06:03). Drive 0 is required for XXDP,
since the XXDP monitor uses drive 0.

The upper byte of the Switch register (15:12) should be set to (0-17 octal) to have the bank number of
the 32K block of memory which will be used for the bootstrap operation.

—_ O ~NON N

AW N

The device codes are as follows:

TM11/TU10 Magnetic Tape, TM11
TC11/TUS56 DECtape, TC11-G

RK11/RKO05 DECpack Disk Cartridge, RK11-D
RP11/RPO3 Disk Pack, RP11-C
RK611/RK06 Disk Pack
RH70/TU16 Magnetic Tape System, TWU16
RH70/RP04 Disk Pack, RWP04

RH70/RS04 Fixed Head Disk, RWS04 (or RWS03)
RX11/RXO01 Diskette (Floppy Disk)

3-21

The memory blocks are as follows:
Physical Memory 00 000 000 - 00 077 776
Physical Memory 00 100 000 - 00 177 776
Physical Memory 00 200 000 - 00 277 776
Physical Memory 00 300 000 - 00 377 776
Physical Memory 00 400 000 - 00 477 776
Physical Memory 00 500 000 - 00 577 776
Physical Memory 00 600 000 - 00 677 776
Physical Memory 00 700 000 - 00 777 776
Physical Memory 01 000 000 - 01 077 776
Physical Memory 01 100 000 - 01 177 776
Physical Memory 01 200 000 - 01 277 776
Physical Memory 01 300 000 - 01 377 776
Physical Memory
01 400 000 - 01 477 776
Physical Memory 01 500 000 - 01 577 776
Physical Memory
01 600 000 - 01 677 776
Physical Memory 01 700 000 - 01 777 776

Physical Memory 17 700 000 - 17 777 776

Starting Addresses, M9301-YC - The normal starting address for DEKBH is 17 765 000.

If the diagnostic portion of this program fails and the operator wants to attempt to boot anyway, he
must follow these steps:
1.

Set up memory management if booting into other than the lower 28K of memory.

If device is on Massbus, set stack pointer to a valid address and load that address with the
memory bank number the operator would put into switches (15:12).
If device is on Unibus, set up Unibus Map registers 0 through 6 to map to same memory as
memory management,

Deposit address 173000 into the PC.
Set the device code and drive number in the lower byte of the Switch register.
Press CONTINUE.

Examples:
a.

RPO04:

Setstack pointer to 40000
Load 000000 into address 40000
Load 173000 into the PC (17 777 707)

Set 000070 into switches (RP04 Drive 0)
Press CONTINUE

RKO5:

Load 173000 into the PC (17 777 707)
Set 000030 into switches (RK 0S5 Drive 0)
Press CONTINUE

3-22

Operator Action - If the diagnostic portion of the ROM fails, record the PC of the HALT instruction
and refer to the listing (or to Chapter 5) to find out which portion of the machine failed.
3.4.2.2

Errors, M9301-YC - List of error halts indexed by the address displayed.

Address Displayed

Test Number and Subsystem Under Test

17765004
17765020
17765036
17765052
17765066
17765076
17765134
17765146
17765166
17765204
17765214

Test 1 Branch Test
Test 2 Branch Test
Test 3 Branch Test
Test 4 Branch Test
Test 5 Branch Test
Test 6 Branch Test
Test 7 Register Data Path Test
Test 10 Branch Test
Test 11 CPU Instruction Test
Test 12 CPU Instruction Test
Test 13 CPU Instruction Test

17765474
17765510
17765520
17765530
17765542
17765550

Test 22 Kernel PDR Test
Test 23 JSR Test
Test 23 JSR Test
Test 23 RTS Test
Test 23 RTI Test
Test 23 JMP Test

17765222
17765236
17765260
17765270
17765312
17765346
17765360
17765374
17765450

17765760
17766000

Test 14 “COM?” Instruction Test
Test 14 CPU Instruction Test
Test 15 CPU Instruction Test
Test 16 Branch Test
Test 16 CPU Instruction Test
Test 17 CPU Instruction Test
Test 20 CPU Instruction Test
Test 20 CPU Instruction Test
Test 21 Kernel PAR Test

Test 25 Main Memory Data Compare Error
Test 25 Main Memory Parity Error
(No recovery possible from this error)

17773644
17773654

Test 26 Cache Memory Data Compare Error
Test 26 Cache Memory No Hit

17773736
17773746

Test 27 Cache Memory Data Compare Error
Test 27 Cache Memory No Hit

17773764

Test 25 or 26 Cache Memory Parity Error

Pressing CONTINUE here will cause
boot attempt forcing misses

Error Recovery - Most of the preceding error halts are hard failures, which means that there is no
recovery from them. The two main memory halts are not recoverable; attempt to boot into another
32K bank of memory if it appears to be a main memory failure.

3-23

If the processor halts in one of the two cache tests, the error is recoverable. By pressing CONTINUE,
the program will either attempt to finish the test (if at either 17 773 644 or 17 773 736), or force
MISSES in both groups of the cache and attempt to boot the system monitor with the cache fully
disabled (if at either 17 773 654, 17 773 746, or 17 773 764).
3.4.2.3

Execution Time - The run time for this program is approximately three seconds.

3.4.2.4

MI301-YC Switches — Refer to schematic D-CS-M9301-0-1, revisions E and F.

Two different revisions of the M9301 are in the field: E and F. They are easily recognized by the
number of Fastab connectors on the modules: Rev. E has two Fastabs while Rev. F has three (Figure
3-11).

F
ETCH REV.

(_v'"vw"iflI
@]

i501
coz

FHEd

e
T

JDF: ]
T3

©®

FASTABS

DE‘ s ]
—
3

JL E11 JDE

|
o — —EZ? {D“O
|
e
T

1 e le08 8
0 Je

03l e

£5 1

El=s
Y

el 0
1

—_—

11-4095

Figure 3-11

M09301-YC Etch Revisions

There is a 10-pole DIP switch, S1, on both versions of the M9301.
1.

S1-1 must be always ON in the PDP-11/70. It allows reading locations 17 765 000 — 17 765
776.

S1-2 must be ON, for remote booting on power up. M9301 remote booting is available by
installing M9301 ECO 5, M8138 ECO 5, M8136 ECO 4, M8130 ECOs 1-3, and >010329
ECO 8.

3-24

S1-3 through S1-10 determine the device and drive that are to be used if Switch register bits
(07:00) are all Os. Figure 3-12 shows the correspondence between S1-3 through S1-10 on
both revisions of the M9301-YC. The switches must be OFF to generate a 1: refer to sheet 4
of the schematic and to Paragraph 5.4.12, Default Device and Drive.
NOTE

As of this writing, XXDP only loads to physical
address 0 from drive 0. XXDP will be modified in the
near future to load into any of the sixteen blocks of
memory that can be specified by Switch register bits
15:12 (refer to Figure 3-9).

PDP-11/70
4

16 15

SWITCH REGISTER

08 07

MEMORY BANK

/NéT U/SE/D////

DEVICE
)

9|8

0302

DRIVENO

7168

ON/OFF

alzla]|t

—

M9301-YC SWITCH S1-

a. ETCHREV E(SEE NOTE)
PDP-11/70 SWITCH REGISTER

16 15

‘21

/) //fiéfi;%}%

MEMORY BANK

08 07

DEVICE

03 02

00"

R E

ON/OFF

ALWAYS ON k
M93301-YC SWITCH St-

b.ETCH
Note:

REV F (SEE NOTE)

When S1-3 through §1-10 are OFF,

they correspond to a 1 in the Switch
Register.

1-3471

Figure 3-12

3.4.2.5

Use of S1-1 through S1-10 on M9301-YC

Starting Procedure M9301-YH - The operation of the M9301-YH is similar to that of the

M9301-YC. The M9301-YH provides the additional feature of booting automatically on power-up, or
by a load-address start sequence.

3-25

M9301-YH Microswitch settings — Prior to installation, set the microswitches on the M9301 (S1) to
select the desired functions and default device. The default device set by the switches will be booted
during a power-up boot or a load-address start sequence if no device is specified by the console switch
register. Note that jumpers W1-W5 on the M9301 must be inserted for PDP-11/70’s and also that for
the automatic power-up boot, ECO 5 must be installed (with jumper W-6 in).
Configure the microswitches as indicated below:
S1-1

Low ROM enable; normally ON, enables diagnostics

S1-2

Power-up boot enable; boots on power-up when ON

S1-3

Memory modifying test disable; when OFF, all diagnostic tests run, when ON, disables
tests 21-24

S1-4.7

Default device code (81-4 is the MSB)

S1-8

Device code source; OFF, device code read from microswitches
ON, device code read from console switch register

S1-9

Diagnostic ON/OFF disables all diagnostics

S1-10

OFF for all PDP-11/70’s

The device codes (S1-4:7) are as follows:

TTMM11/TU10

Magnetic Tape

2
3
4

TC11/TUS6
RK11/RKO0S
RP11/RPO3

DECtape
Disk

5
6

RK611/RKO06
RH11-RH70/TU16

RHI11-RH70/RP04

RHI11-RH70/RS04

11
12

PCl11

RX11/RX01

Disk
Disk
Magnetic Tape
Disk
Fixed Head Disk

Floppy Disk
Paper Tape Reader

The default device is always drive unit number zero.
Power-Up Boot — With microswitch S1-2 in the ON position an automatic boot on power-up will occur

from the default device specified in the microswitches or optionally from the device specified by the
console switch register. If switch S1-8 is OFF, the M9301 will always boot the default device specified
by the microswitches. If switch S1-8 is ON, the device may be selected by loading a device code into the
switch register prior to power-up. The M9301-YH will boot the default device with S1-8 ON if no
device is specified by the switch register; that is, if the switch register low byte is equal to zero.
With switch S1-8 OFF, select the device with the switch register as follows:

3-26

SW REG(6:3)
Device Code

0
1
2
3
4
5
6
7
10
11
12

Use the device specified in microswitches (S1-7:S1-4)
TMI11/TUI10
Magnetic Tape
TC11/TUS6
DECtape
RK11/RKO05
Disk
RK11/RP03
Disk
RK611/RKO06
Disk
RH11/RH70/TU16
Magnetic Tape
RH11/RH70/RP04
Disk
RH11/RH70/RS04
Fixed Head Disk
RX11/RX01
Floppy Disk
PCl11
Paper Tape Reader

SW REG (2:0) Drive Unit Number

Load Address Start Sequence - This mode allows the user to boot from any device and any unit number
available for load address starts. Microswitch S1-2 must be OFF and microswitch S1-8 must be ON.

The boot procedure is as follows:

3.4.2.6

Turn power ON.
Load address 17773000.

Load switch register (6:3) with device code and (2:0) with drive number.
Start.

Errors, M9301-YH - The following is a list of error halt addresses and the corresponding test.

Address
Displayed

Test Number and Subsystem Under Test

17765004
17765020
17765036
17765052
17765066
17765076
17765126
17765136
17765154
17765172
17765202
17765210
17765224
17765246

Test 1, Branch Test

17765256

Test 16, Branch Test
Test 16, CPU Instruction Test
Test 17, CPU Instruction Test
Test 20, CPU Instruction Test

17765300

17765334
17765352

Test 2, CLR and Conditional Branch Test
Test 3, DEC and Conditional Branch Test
Test 4, ROR and Conditional Branch Test
Test 5, Conditional Branch Test
Test 6, Conditional Branch Test
Test 7, Register Data Path Test
Test 10, Conditional Branch Test
Test 11, CPU Instruction Test
Test 12, CPU Instruction Test
Test 13, CPU Instruction Test
Test 14, CPU Instruction Test
Test 14, CPU Instruction Test
Test 15, CPU Instruction Test

3-27

17765376

17765520

Test 21, JSR Test
Test 21, JSR Test
Test 21, RTS Test
Test 21, RTI Test
Test 21, JMP Test
Test 22, Main Memory Data Compare Error

17765540

Test 22, Main Memory Data Compare Error, no recovery possible from this error

17765604
17765614

Test 23, Cache Memory Data Compare Error
Test 23, Cache Memory No Hit
(pressing continue here will cause boot attempt, forcing cache misses)
Test 24, Cache Memory Data Compare Error
Test 24, Cache Memory No Hit
(pressing continue here will cause boot attempt, forcing misses in the cache)
Test 22, 23, or 24, Cache Memory or Main Memory Parity Error. (Examine memory error register 777744 to find out more.) If cache parity error, pressing continue
here will cause boot attempt forcing misses in cache:

17765406
17765416
17765430
17765436

17765720
17765732

17765752

Most of the errors listed are hard failures, and there may be no recovery from them.

[f the processor halts in one of the two cache tests, error recovery is possible. When continue is pressed,
the program will either attempt to finish the test (1776504 or 17765720) or force misses in both groups
of the cache and attempt to boot with the cache fully disabled (1776514, 17765732, or 17765752).
[f the program fails in an uncontrolled manner, it might be due to an unexpected trap to location 4 or
10. If this is suspected, then load the following.
Location

Contents

6
10

0
10

The preceding steps will cause all traps to vectors 4 and 10 to halt the processor at addresses 6 and 12,
respectively (with addresses 10 and 14 in the display); the operator can examine the CPU error register
at 17777766 to get more error information. Bits in CPU error register are defined as follows:

Bit 02 = Red Zone Stack Limit
Bit 03 = Yellow Zone Stack Limit
Bit 04 = Unibus Timeout
Bit 05 = Nonexistent Memory
Bit 06 = Odd Address Error
Bit 07 = Illegal Halt

3.4.2.7 Starting Procedure M9312 - The M9312 bootstrap module executes its diagnostic and boot
routines initiated either automatically on power-up or by a load address start procedure. The bootstrap programs are stored in ROMs that plug into sockets on the M9312. Each device is booted only
by its own ROM; up to four ROMs can be installed on the M9312. Devices for power-up booting are
selected by specifying a starting address of one of the ROM boot routines. These functions are selected
with microswitches (S1) on the module prior to installation. The location of S1 is shown in Figure 3-13.

3-28

FASTON TABS

—— Ij

BOOT ROM

£S5 U[“_— [L___

BooT RoM _ | || §E34J[:| "

jUfz
\}ess
Boojzflowl
T~
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JUDS .
—

lLrl.

m |:/E

-J

(E37)

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JDF \

E[j]

ADDRESS OFFSET

" SWITCH BANK $1

1]
— =//_.
_WQ
T3

CXT3

TP1

(,|000CszZ00n

6 €2 ][]B

W12 —

TP2

TP3

l’fh E] E‘] E’

D[]E_l_'

BOOLFOM\

LO ROM ENA H
JUMPER W—8

TP4

]

) D : JL

ATOR
~~ CONSOLE EMULROM
& DIAGNOSTIC

‘Jj\\v\fl

W
TK-1469

Figure 3-13

M9312 Bootstrap/Terminator Module

3-29

Power-Up Boot - The module performs a power-up boot when switch S1-2 is in the ON position. The
device used will depend on the ROMs installed and the starting address selected by switches S1-3:9. Set
the switches as follows:
S1-1
St-2
S1-3:9

OFF
ON for power-up boot
Offset address of ROM program

S1-10

ON for diagnostics

The following lists the available ROMs by part number, the device or devices they boot, and the
address to set in microswitches to select the device for booting.
Part

Number

S1 Switch Settings

Device

23-751A9

RLO1

OFF

23-752A9

RX06/07

OFF

23-753A9
23-754A9

RXO01
RXO02

OFF
OFF

ON
ON

23-755A9

RP02/03

OFF

23-756A9

RP04/516, RM02/3
RK03/05/05J (Unit 0)
RK03/05/05J (Unit 20

OFF
OFF
ON

ON
OFF
ON

OFF
OFF
ON

ON
OFF
OFF

OFF
ON
ON

TUS5/56
TUL6/E16 (TM02/03)
TUI10/TE10, TSO3
RS03/04

OFF
OFF

ON
OFF
OFF
OFF

ON
OFF

ON
ON

OFF

OFF
OFF
OFF
OFF

OFF

23-760A9

PCO05
DL11A/W

OFF
OFF

OFF
ON

ON
ON

23-761A9
23-762A9

TU60
RS11

OFF
OFF

ON
ON

23-763A9

RS64
CR11

OFF
OFF

ON
OFF

OFF
OFF

ON
OFF

OFF
ON

23-757A9
23-758A9
23-759A9

OFF

The setting of switches S1-3 and S1-4 depends on the ROM location in which the boot ROM is

located.
ROM Slot

S1-3

S1-4

OFF

3
4

ON
ON

OFF
ON

Load Address Start Sequence — When microswitch S1-2 is placed in the OFF position, the device is
specified by the console switch register. The address loaded in the switch register depends on which
ROMs are installed and in which ROM locations they are located.

3-30

il
s

The load address start sequence is as follows.
Turn power ON.
Load address 765744.

‘

Load switch register (8:0) with starting address and (11:9) with drive unit number.
Press START.

Switch register bits (11:9) are loaded with an octal number that is the drive number of the device used
for booting.

in which the ROM is located. Set
Switch register bits (8:6) correspond to the ROM socket number
switches (8:6) on the console as follows:
ROM Socket

Number

SW Reg (8:6)

|
2
3
4

0
2
4
6

Switch register bits (5:0) point to the starting address of the ROM boot program in the ROM selected
by switch register bits (8:6). The following lists the available ROMs by part number and their devices,
along with the address to load in switch register bits (5:0).

Part Number

Device

SW REG (5:0)

23-751A9
23-752A9
23-753A9
23-754A9
23-755A9

RLO1
RK06/07
RXO01
RX02
RP02/03

12
12
12
12
12

23-756A9

RKO03/05/05])

RP04/516, RM02/03

TUS5/56

DLI11A/W

RS64

23-757A9
23-758A9
23-759A9
23-760A9

TU16/E16 (TMO02/03)
TU10/TE10, TS03
RS03/04
PCO05

23-761A9
23-762A9

TU60
RS11

23-763A9

CR11

12
12
12
12

12
12
12

3.4.2.8 Errors - M9312 - The following is a list of diagnostic error halt addresses and the corresponding failing test. Most of the errors are hard failures and there will be no recovery from them. If one of
the cache memory tests fails (test 23 at location 165564 or test 24 at location 165704), attempt to boot
the system by pressing continue. This will cause the program to force misses in both groups of cache
before going to the bootstrap portion of the program.

3-31

Address
Displayed

Test
Number

165050
165064

Unconditional Branch Test

CLR, BMI, BVS, BHI, BLOS Test

165102

DEC, BPL, BEQ, BGE, BGT, BLE Test

165116

165132
165142
165160
165176
165206
165214
165230
165250
165260
165302
165320
165332

5
6
11
12
13
14
14
15
16
16
20
21

ROR, BVC, THIS, BIT, BNE Test
SEZ, BHI, BLT, BLOS Test
CLZ, BLE, BGT Test
ADD, INC, COM, BCS, BLE, Test
ROR, BIS, ADD, BLO, BGE Test
DEC, BLOS, BLT Test
COM, BLOS Test
BIC, BGT, BGE, BLE Test
ADC, CMP, BIT, BNE, BGT, BEQ Test
MOVB, BPL Test
SOB, CLR, TST, BNE Test
ASH, SWAB Test
JSR Test

165342

165352
165364

21
21

165372
165470
165510
165724
165554
165564
165672
165704
165724

21
22
22
22
23
23
24
24
24

Failing
Test

JSR Test

RTS Test
RTI Test
JMP Test
Main Memory Data Compare Test
Main Memory Complement Data Test
Main Memory Parity Error
Cache Data Compare Test
Cache Miss (Press continue to boot)
Cache Data Compare Test
Cache Miss (Press continue to boot)
Cache/Main Memory Parity Error

3.4.2.9

M9312 Boot ROM Identification - Every boot ROM contains an identification code stored in
the ROM program. To identify the type of ROM installed, examine the contents of the ROM’s ID
location at the console switch register and then find the part number from the list included below.

To identify the ROM in ROM socket number one, examine address 773000. To identify the ROM in
ROM location two, examine address 773200. To identify the ROM in ROM location three, examine

address 773400; and for the ROM in ROM socket number four, examine address 773600.
Contents of ROM
ID Address

ROM Part
Number

Used with Device

042114
042115
042130
042131
042120

23-751A9
23-752A9
23-753A9
23-754A9
23-755A9

RLO1
RK06/07
RXO01
RX02
RP02/03, RP04/516, RMO02/03

042113
046515

23-756A9
23-757A9

RKO03/05/05J, TU55/56
TUI6/E16, TM02/03

046524
042123

23-758A9
23-759A9

TUI10/TE10, TS03
RS03/04

3-32

050122

23-760A9

PCO5, DL11A/W

041524
042106
041522

23-761A9
23-762A9
23-763A9

TU60
RS11, RS64
CRI11

3.4.3

Diagnostics

Locate the installation checklist, K-SP-7668010 (a computer print-out). Compare the configuration
key, or transfer sheet to the installation checklist and check under “Run’ the diagnostic tests for all
options listed as being present in this system.

Load and run the diagnostics listed in the installation checklist which are applicable to the system for

the time or number of passes specified.

The diagnostics should be run in the order specified on Figure 3-9. Abstracts of the CPU diagnostics
are reproduced in Chapter 5. Operating procedures and listings for all diagnostics are contained in the
MAINDEC
s for each program.

Operating procedures for the XXDP monitor are described in the XXDP User Manual, MAINDEC11-DZOXA.

3.44

DEC/X11 System Exerciser

DEC/X11 is a system exerciser, i.e., it is an operating system that runs all devices in a system, using

random data. Any errors are reported.

DEC/X11 must be configured for each individual system. The DEC/X11 User's Documentation and
Reference Guide, MAINDEC-11-DXQBA contains all information required to configure and run
DEC/X11 and to interpret the results of the tests performed. The XXDP DEC/X11 Programming
Card, MAINDEC-11-DZZPA contains a summary of DEC/X11 features.

Turn to the system exerciser section of installation checklist and prepare to load DEC/X11. The
system exerciser checklist numbering sequence begins with IBXXXX. To start the DEC/X11 package,
see the notes at the beginning of the system exerciser section of the installation checklist.
3.4.5

System Software Exerciser (Under Development)

The system software exerciser will be similar to DEC/X11, except that it will use the system software
operating system. Because of this, it will be a better test of the integrity of a system than DEC/X11. A
printout will be available for each version of the software exerciser.
3.4.6

Summary and Final Acceptance

Go through each chapter of the PDP-11 Family Field Installation and Acceptance Procedure and
ensure that all areas requiring an initial are so marked. If an initial is missing, investigate that section
and complete if necessary.

Ensure that all paperwork is complete. The Field Service and/or installation reports should reflect any
problems/repairs encountered during the installation. After completion, the reports and checklists
should be returned to the office.

The installation is now complete. Have the customer sign the Field Service Report reflecting installation activity.

3-33

OUTER BOX (TOP)

TOP PROTECTOR (FOAM)

INNER BOX (TOP)

SIDE

PROTECTOR

(CARD BOARD)

MEMORY FRAME

FRONT

REAR PROTECTOR

PROTECTOR

INNER

BOX

(BOTTOM)

OTTOM PROTECTOR

(FOAM)

QUTER BOX

FOAM PROTECTOR

OUTER BOX
(8OTTOM)

1E- 3161

Figure 3-14

Memory Frame Packaging

3.5 MJ11 MEMORY EXPANSION
An MJ11 memory frame is shipped in a protective box (Figure 3-14). Remove the memory frame from
the box and inspect for damage. Save the shipping cartons and packaging materials in case it becomes
necessary to return the memory frame for service. The slide mounts are attached to the memory frame,
but the mounting screws are packed in a bag placed in the shipping container.

3-34

Slide Mounting - The fixed slides must be mounted equidistant from and parallel to the floor at the
proper cabinet frame hole number (Figure 3-15). The front of the fixed slide has an integral bracket
and is mounted in the cabinet with four screws that are secured with captive (Tinnerman) nuts. The
rear of the fixed slide is attached to a separate L-shaped bracket with two screws and nuts. The bracket
is attached to the cabinet with two screws that are secured with captive nuts.

Lift the memory frame and slide it carefully into the fixed guides until the slide release engages. Unlock
the slide release and push the memory frame fully into the cabinet. Extend the memory frame enough
to allow access to the front mounting screws. Slightly loosen the front and rear slide mounting screws
and slide the memory frame back and forth. This allows the slides to assume a position that results in
minimum binding. Retighten the mounting screws.

Cable Retractor - The cable retractor rod (DEC Part No. 12-12173-00) prevents the main memory bus
cables from tangling when memory frames are extended from the cabinet. Install the cable retractor
rod at the holes indicated in Figure 3-15.

AC Power Connection - Plug the memory frame power cord into one of the switched outlets of the
cabinet power controller.

NOTE

The load at the power controller outlets must be dis
tributed among the three phases. No other device
should be plugged into a power controller phase circuit loaded by two memory frames. Refer to Drawing E-AR-11/70-0-1 and Figure 3-16.

MJ11 Memory Configuration

3.5.1

Whenever memory capacity is expanded, the following guidelines must be adhered to:

1.
2.

Before installing memory controller modules (M8147/M8148, and M8149), ensure that the

switches on the M8147/M8148 module are properly configured.

Lower addresses must be implemented in memory frames electrically closest to the bus
master.

All interleaved memory frames must be closer to the bus master than non-interleaved mem-

ory frames.

When memory frames are interleaved, they must be physically and electrically adjacent, with

the memory frame containing ‘“‘even” addresses closer to the bus master.

Care should be taken that modules are installed in their designated slots, as indicated in the

When memory capacity is increased within a2 memory frame, stack module set pairs are
installed at the left and right-hand side of the backplane, working toward the center. Thus
the stack three (high and low word) modules are the last module sets added to a memory

module utilization sticker (Figure 3-17).

frame.

Record the serial number of the module group just installed in the appropriate slot on the

module utilization sticker.

3-35

004e

—

SLIDE MOUNT | CABLE RETRACTOR
HOLE WHICH

HOLE LOCATION

COINCIDES WITH |

(AT SIDE OF

LOWEST HOLE

CABINET)

FIXED SLIDE

MOUNT

HOLE
78

HOLE

L +

HOLE

57
HOLE
53

HOLE
36

HOLE

—

HOLE

1-3162

Figure 3-15

MJ11 Memory Frame and Cable Retractor Mounting

PROCESSOR

1ST MEMORY

2ND MEMORY

CABINET

L »

[

CABINET /
FANS
: @1

UNSWITCHED

(MJ11)

(NOTE 2)

(o]

73
(NOTE 2)

(MJ11)

g;figg

Z1 (MJ11)

@3 (MJ11)

@1 (MK11)

@2 (MK11)

LOWER

@3 (MJ11)

(NOTE1)

H7420

B3 (MKI)

oIt1({MJ11)

3Kt

ullin

nlin

NOTES:
1.Minimum memory:

K bytes.
128
2.Refer to chapter 1
for allowable peripherals.
MA-1485

Figure 3-16

Phasing of Memory Frames

Starting Address Switch Configuration — Switches S1-1 through S1-7, S2-1, and S2-2 on the
M8147/M8148 module (drawing MCTB and MCTIJ) must be configured to represent the starting
address of the memory controller. This is done by setting the switches to the binary number which
represents the total number of 16K blocks of 36-bit double words controlled by memory controllers

having lower starting addresses.

’

A closed switch (set to ON) represents a logic 0. Switch S1-1 represents the LSB and switch S2-2 the
MSB.

The steps required to determine the starting address switch settings are shown in Figure 3-18 in flowchart form. For example:
In an MJ11 Memory System, any two adjacent memory frames containing equal amounts of memory
can be interleaved. If interleaving is desired, switch S2-3 on the M8147/M8148 modules (drawing

MCTB) in both memory frames must be open (OFF). By convention, the memory controller located
closer (electrically) to the bus master is required to respond to “even” addresses. Switch S2-4 in this
controller must be closed (ON); switch S2-4 in the memory controller, which is farther from the bus
master, should be open (OFF).

Switch Configuration Example - In a memory system consisting of three memory frames, assume that
the first two frames (0 and 1) contain 128K of 18-bit words (i.e., 64K 36-bit blocks each, and that
memory frame contains 32K 18-bit words (i.e., 16K 36-bit blocks). If memory frames 0 and 1 are
interleaved, the memory frames are configured as follows:
Memory Frame 0 - Since no words precede this frame, 0 divided by 16K = 0 is set into switches SI-

1:52-2 (i.e., all nine switches are set to ON). Switch S2-3 is set for interleaved operation (OFF) and
switch S2-4 is set for even addresses (ON).

3-37

mji1 memory sysctem
CONTROLLER STARTING ADDRESS (OCTAL) .
INTERLEAVED

CIYES

CINO

CJEVEN

MEMORY SYSTEM SERIAL NO.

00000
[10ODD

DATE INSTALLED
-

SLOT|

MODULE TYPE

MODULE GROUP

SER. NO.

G11d

H217C

03 |

G235

Giid

SIN

H217C

STK

G235

DRV

G114

SIN

H217C_

G235

HIGH WORD
STACK 2

HIGH WORD

SIN

H217C _ STK

G235

M8148

M8149

UEVEN

MEMORY SYSTEM SERIAL NO.
MODULE TYPE

STACK 3

G116

SIN

H224C

STK

G236

DRV

G116

IN
:TK

04 |

H224C

G236

DRV

G116

SIN

H224C

STK

G236

DRV

G116

SIN

CJODD
DATE INSTALLED

MODULE GROUP

MODULE (GROUP) FUNCTION

STACK 0

HIGH/ODD WORD

STACK 1
HIGH/ODD WORD

STACK 2

HIGH/ODD WORD
STACK 3

H224C

STK

MCT

MEMORY CONTROL & TIMING

G236

DRV

MXR

MEMORY TRANSCEIVER

M8147

MCT

MEMORY CONTROL & TIMING

M8149

MXR

MEMORY TRANSCEIVER

SIN

G114

SIN

H217C

STK

STACK 3

DRV

G114

SIN

H217C

STK

G235

[NO

HIGH WORD

G235

CJYES

DRV

STACK 1

DRV

HIGH WORD

STK

INTERLEAVED

SER. NO.

STACK 0

DRV

CONTROLLER STARTINGADDRESS{OCTAL) ___
00000

| MODULE (GROUP) FUNCTION

SIN

_ STK

mJjt memory system

LOW WORD

STACK 2

DRV

G114

H217C

_ STK

G235

DRV

G114

SIN

H217C

STK

G235

DRV

LOW WORD

SIN

STACK 1

LOW WORD
STACK 0

LOW WORD
MJ11-A

G116

H224C

G236

DRV

SIN

H 224C
2?1

HIGH/ODD WORD

STACK 3
LOW/EVEN WORD

_ STK

STK

G236

G116

SIN

H224C

STK

STACK
LOW/EV2EN WORD

DRV

G236

DRV

G116

SIN

H224C

STK

G236

DRV

STACK 1

LOW/EVEN WORD
STACK 0

LOW/EVEN WORD

MJ11-B
11-3287

Figure 3-17

Module Utilization Labels

3-38

EVEN

NUMBERED

FRAMES

FRAME

0,2,4,6

YES

DETERMINE
NUMBER OF

36-BIT DOUBLE
WORDS PRE-

CEDING THE

SET SAME NUMBER

IN SWITCHES AS

FRAME

IN PREVIOUS

FRAME

DIVIDE
BY 16K
SET SWITCH S2-3

OFF (ENABLE

INTERLEAVE)

SET NUMBER

IN SWITCHES

(81-1: §2-2

SET EVEN/ODD
SWITCH S24

TO OFF (ODD)
IS

FRAME

YES

INTERLEAVED
?

SET SWITCH

$2-3 TO ON

$2-3 OFF

(DISABLE

(ENABLE

INTERLEAVE)

SET EVEN/ODD
SWITCH S24

(

DONE

(EVEN)

)
11-3164

Figure 3-18

Procedure for Configuring M8147 (or M8148) Switches

3-39

Memory Frame | - Since this frame is interleaved, the starting address switches are configured as in
memory frame 0. Switch S2-3 is set for interleaved operation (OFF) and switch S2-4 is set for odd
addresses (OFF).
Memory Frame 2 - Since frames 0 and 1 contain a total of 128K 36-bit blocks, 128K divided by 16K =
8(10) = 10(8) = 000001000(2) is set into switches S1-2:S2-2 (i.e., S1-4 is set to OFF while the remaining

switches are set ON). Switch S2-3 is set to ON to disable interleaving. With interleaving disabled, the
state of switch S2-4 is irrelevant.
3.5.2

Main Memory Bus Cabling

Remove the M8147/M8148 and M8149 module comprising the last memory controller on
the main memory bus.

Remove the H873 bus terminator from J2 and J4 on each module.

Install address cable assembly 7010824-1 in connectors J2 and J4 of the M8147/M¥§148
module.

Install the data cable assembly 7010824-0 in connectors J2 and J4 of the M8149 module.

Replace the modules in their proper backplane slots.

Route the main memory bus cables as shown in Figures 3-19 and 3-20. Ensure that the
cables do not obstruct the air vents at the rear of the memory frame. Connect the cables to
J1 and J3 on the M8147/M8148 and M8149 modules of the memory frame being installed.

Insert the main memory bus terminators in connectors J2 and J4 of the M8147/M8148 and
M8149 modules, which are last on the main memory bus.

3.5.3

Install the modules in their proper backplane slots.

Secure the bus cables by tightening the cable clamps.
Voltage Checks

After installation has been completed, check regulator voltage outputs in all the memory frames (Table
3-2). Perform voltage adjustments (Paragraph 4.5.2.2) if necessary.
3.5.4

Memory Expansion in the PDP-11/70

Prior to installation verification, the PDP-11/70 System Size register must be reconfigured to represent
the new memory size. Refer to drawing D-CS-M8140-0-1, sheet SCCN in the PDP-11/70 Engineering
Drawings and to Figure 3-21.
3.5.5

Checkout
Run diagnostics as listed in Figure 3-9.

3.6

MK11 MEMORY EXPANSION
The MK 11 memory frame is similar to the MJ11 memory frame. They are shipped in the same type of
protective box (Figure 3-14) and have the same type of slide rail mounting brackets (Paragraph 3.5). Both memory frames are mounted in the memory cabinet in the same manner. In addition to installing
the memory frame, the box controller and the three battery backup units must also be installed in the
cabinet and cabled to the memory frame.
'

3-40

—\ (—

A-

Figure 3-19

Typical MJ11 C able Routing

3-41

RIBBED SIDE DOWN
__TO NEXT MEMORY
FRAME

— FROM PREVIOUS
MEMORY FRAME

TOP

RIBBED SIDE UP

MJ11

a.Incabinets where the bus is
routed from bottom to top

—— TO NEXT MEMORY FRAME
FROM PREVIOUS MEMORY FRAME

TOP OF

\J\

MJ11

MB147

MB8149

M8148

______ e

b.In cabinets where

the bus is

routed from top to bottom

NOTE:

1. The cables shown above do not overlap exactly due to iliustrative
purposes only.

2. Dotted lines indicate red stripe on smooth side of cable.
11-4309

Figure 3-20

MJ11 Main Memory Bus Cable Routing

3-42

BIT

H-3470

X = ON
- = OFF

Memory Size

Last Address

32K

00177776

64K
96K

128K
160K
192K
224K
256K

288K

320K
352K
384K

416K
448K
480K
512K
544K

576K
608K
640K
672K
704K
736K
768K
800K
832K
864K
896K
928K
960K
992K
1024K

00377776
00577776

00777776
01177776
01377776
01577776
01777776
02177776

02377776

02577776
02777776

WI3

Wi4

—
X
X
—
—

X
X
X
X
X

X
—_

—
—

X
X

03177776
03377776
03577776
03777776

X
X
—
—_

X
X
X
X

04377776
04577776
04777776
05177776
05377776
05577776
05777776
06177776
06377776
06577776
06777776
07177776
07377776
07577776
07777776

X
—_
—_
X
X
—
—
X
X
—
—
X
X
—
—

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

04177776

Switch Settings
W10 WIi6 W15

Wil

—

—_

X
X
X
X
X

—_
X
—_
X
—

X
—
—_
—_
—

X
X
X
X
X

—_
—_
—
—_
—_

—_

—

—_

X
X
X
X

X
—
X

—_
—
—
—

—_
—

X
X
X
X
X
X
X
—
—
—
—
—_
—_
—
—

—
—
—_
—
—_—
—_
—
—_
—_
—_
—_
—
—
—_
—

X
X

—

—
—
—
—_
—_
—_
—_
—_
—
—_
—
—_
—

_
X

X
—

—
X

—_—
X
—_
X
—
X
—_
X
—_
X
—
X
—_—
X
—

X
X

—

X
X

—
—

—_
—
—_
—
X

X
X
X
—
—_
—_
—_
X
X
X
X
—
—_—
—_

Figure 3-21
System Size Register Switches (Sheet 1 of 2)
(refer to D-CS-M8148-0-1, Sheet 1, for Location of Switch Assembly)

3-43

W12

—
—

—

—
—

—
—
—

—_
—_
—
—_
—

—

—
—

—
—
—
—
—

—
—
—_
—
—_—
—
—
—
—_
—_
—_
—
—
—
—

X = ON
- = OFF

Switch Settings
W10 W16 WIS

Memory Size

Last Address

WI3

W14

1032K
1064K
1096K
1128K

10177776
10377776
10577776
10777776

X
X
—_
—_

—_
—
—
—_

X
X
X
X

X
—
X
—_

1192K
1224K
1256K

11377776
11577776
11777776

X
—
—

—
—
—

X
X
X

12377776

1160K

1288K

1320K
1352K

1384K

11177776

12177776

12577776

—

13177776
13377776
13577776

X
X
—

—

—
—_
—
—_

X
X
X
X

—
—_
—
—

—_
X
—_

—
—_
—

—
—
—_

X
X
X

—
—
—

—

—_

—
X

—
—_

—
X

X
X

—

13777776
14177776

—
X

—
—_

X
—

—_
X

1640K
1672K
1704K

14777776
15177776
15377776

—
X
X

—_
—
—_

—
—
—

—
X
—

X
_
—

—_
—_
—

1832K
1864K
1896K
1928K
1960K
1992K
2048K

16377776
16577776
16777776
17177776
17377776
17577776
17777776

X
—_
—
X
X
—
—

—_—
—
—
—
—_
—
—

—
—
—_
—
—
—_
—

—_
X
—
X
—
X
—_

X
X
X
—_
—
—_
—_

—
—
—_
—
—_
—
—

1512K
1544K

1576K
1608K

1736K
1768K
1800K

14377776
14577776

15577776
15777776
16177776

Figure 3-21

X
—

—
—
X

—
—

—
—
—

X
X
X

—
—

—
—
—

X
—
X

—
—
—

—
X

X
X

X
—
X

—
—
X

—
—
—

—
—

—
—
—

System Size Register Switches (Sheet 2 of 2)

(Refer to D-CS-M8148-0-1, Sheet 1, for Location of Switch Assembly)

3-44

—

—_

—
—
—

Wil

X
X
X
X

—

1416K
1448K
1480K

12777776

—

Wi12

—

—
—

—

—
—
—

—_
—

X
X

—
—

X
X
X

—
—_
—

—_
—_
—
—
—
—
—_

—
—
—_—
—
—_
—

X
X
—

—
—
—

Cable placement is critical in the memory cabinet. The cables will be damaged if the following procedure is not followed carefully. The following steps refer specifically to adding memory box no. 1 to
the first memory cabinet. The procedure for installing expansion box no. 3 to the second memory
cabinet is similar and can be generalized from the steps given in this section if the following guidelines
are observed.

¢ Cable from lower numbered memory box to higher numbered box. Take up excess cable slack
inside of higher numbered memory box.

e Keep smooth side up on incoming ribbon cables. Keep ribbed side up on outgoing ribbon
cables.

e Memory boxes no. 0 and no. 2 have their incoming cables on the left-hand side of box. Memory boxes no. 1 and no. 3 have their incoming cables on the right.
Prior to installation, check contents of shipment against packing list, unpack containers, and inspect
for obvious shipping damage. Remove the memory cabinet’s front and rear doors.
Configure the power fail jumpers on the address buffer module (M8158) as shown in Table 3-4. This
will allow any memory to be switched off-line and powered down without affecting the other memories
or the processor.

The CSR address select switches must select the address corresponding to the memory’s unit number.
Consult Table 3-5 for the proper CSR address and set the switches on the address interface module.
Apply unit number decal to memory box.

Extend memory box no. 0 from the cabinet. Remove the top cover and remove the strain
relief bar. Remove address interface and data buffer modules (slots 13 and 15). Remove
screws and unplug memory bus terminators from J2 and J4; see Figure 3-22 for their loca
tion. Configure power fail jumpers as in Table 3-4. Plug in address and data bus cables,
keeping ribbed side up and red stripe to left on component side of board. Replace address
and data buffer modules.

Fold outgoing bus cables. Lay cables, ribbed side up, on right-hand side of memory box.
Replace the strain relief bracket keeping cables between retaining screws. Flatten outgoing
cables and pull them toward rear of box to take up any slack inside the box. Tighten strain

-relief bracket. Tie wrap outgoing cables to power supply assembly.

Tilt memory box no. 0 to the 90 degree service position. Align cables so they extend straight
back into the cabinet, parallel to the slide rails. Tie wrap cables to front cable retractor bar

as shown in Figure 3-28, taking up slack in cables between memory box and retractor. Route
bus cables over cable retractor and into cabinet. Use tape to tie wrap the four cables together
between memory box and front cable retractor. Place floating restraint under cables midway between memory box and cable retractor and tie wrap to cables.

Tilt memory box no. 0 to its level position and replace top cover. Slide box no. 0 into

Mount memory box no. 1 in cabinet, position slide rails at height indicated in Figure 3-23.

cabinet, guiding cables by hand if necessary.

3-45

| el

()
BOX CONTROLLER-

INCOMING DATA CABLES

RIBBON CABLE

I
J4
M8159 DATA BUFFER

OUTGOING DATA CABLES

COMPONENT SIDE

OR
TERMINATORS

e
M8158 ADDRESS

INTERFACE

COMPONENT SIDE

INCOMING ADDRESS AND

CSR

S1| ADDRESS

SWITCHES

CONTROL CABLES
J’"

J2
OUTGOING ADDRESS AND

J4
W3

]
W4

CONTROL CABLES

TERMINATORS

POWER

FAIL

JUMPERS
MA-1412

Figure 3-22

Address and Data Buffer Plug Locator

3-46

BATTERY BACK-UP
UNIT 1-C
96 —»|+

BOX

CONTROLLERS

& CONTROL
PANEL

+la

BATTERY BACK-UP
UNIT 1-B

84 —»+

BATTERY BACK-UP

BATTERY BACK-UP
UNIT 1-A

72 ——w{4-

+e— 72

UNIT O0-C

BATTERY BACK-UP

BATTERY BACK-UP
UNIT O-A

60 —»14+

+jea—— 60

UNIT O-B

64 CABLE

——p

-}e——57 CABLE TROUGH 57 —p1-

RETRACTOR

(2)

BA11 BOX #1
r-

e 41
-y¢—— 33 CABLE
RETRACTOR

(2)

BA11 BOX #0
-

it+He—20

REAR VIEW

FRONT VIEW

MA-1413

Figure 3-23

MKI11 Memory Cabinet Configuration

3-47

Route power cables (Figure 3-24). Tilt box no. 1 to the 90 degree service position. Plug in

battery backup and box controller power cables and tie wrap to power supply chassis. Overlap the two power cables on left side of box and tie wrap them to the front cable retractor,
taking up any slack and keeping the cables parallel to the slide rails. Route cables straight
back through the cabinet, under and around the rear cable retractor bar. Tie wrap power

cables to cable retractor. On right side of box, route and tie wrap power and controller
cables in the same fashion. Tie wrap cable bundles every six inches. Use tape to tie wrap
cables between memory box and front cable retractor.
Install battery backup units 1B and 1C in the rear of the cabinet at the heights shown in
Figure 3-23. Plug power cables into battery backup units. Take up slack in cables by tie
wrapping loops into the cables as shown in Figure 3-25
Remove blank control panel cover. Pull controller power cable through cutout on top of
control panel and out through front of panel. Plug cable into box controller and mount
controller in control panel. Install battery backup unit 1A in cabinet and plug in power
cable. Tie wrap loops into cables to take up slack as shown in Figure 3-26.
Return memory box no. 1 to level position. Remove top cover and strain relief bar. Lay the
four incoming bus cables, from box no. 0, on the right-hand side of box, keeping smooth
side of cables up. Replace strain relief bar (do not tighten) and position cables just to the left

of the retaining screw. Pull bus cables forward under strain relief taking up enough slack in
cables to allow service loop (Figures 3-27 and 3-28). Cables should be tight when memory
box is pushed back into cabinet. If box is pushed into cabinet to check length of service loop,
push box carefully and guide cables by hand to avoid damage to cables.
10.

Remove data buffer and address buffer modules. Configure power fail jumpers and CSR
address switches as two indicated in Tables 3-4 and 3-5. Plug terminators and secure with
two screws and connect bus cables into modules as in Figure 3-22. Keep red stripe to left on

component side of modules. Replace address and data buffer modules. Fold incoming bus
cables to take up slack inside of memory box. Tie wrap incoming bus cables every six inches.
11.

Plug box controller ribbon cable into data buffer board, fold, and lay on top of incoming

bus cables, keeping smooth side up. Lift strain relief bar and slide cable under bar, position
cable on top of bus cables (do not alter position of incoming bus cables). Flatten controller
cable to remove slack and tighten strain relief bar. Replace top cover and tilt box to the 90
degree service position.
12.

Route controller ribbon cable over front cable retractor bar then under and around rear
cable retractor (Figure 3-26). Take up slack in cable and tie wrap to cable retractors as
shown. Keep cable path parallel to slide rails. Bring cable across to front of cabinet and plug
into box controller as in Figure 3-27. Plug cable in with smooth side of cable up on bracket
behind controller. Take up slack in cable with folds and tie wrap to bottom of control panel.
Install strain relief bracket behind controller panel. Tie wrap floating strain relief to cables
mid-way between memory box and front retractor bar.

13.

Return memory box to level position. Tie wrap power cord to rear cable retractor. Plug
power cord into receptacle. Attach memory unit number decal corresponding to CSR ad-

dress to memory box. Push memory box into cabinet, guiding cables by hand if necessary.

3-48

BBU1-C

BOX

CONTROLLER

BBU1-B

TIE WRAPS
EVERY 6 IN.

FRONT CABLE

RETRACTOR BAR

REAR CABLE
RETRACTOR BAR

TAPE

P31

(BOX CONTROLLER)

J28 (BBU1-A)

J29 (BBU1-B)
J30 (BBU1-C)

MA-1414

Figure 3-24

Box Controller and Battery Backup Power Cables

3-49

BBU

1-C

CONTROLLERS

TIE WRAP GOES AROUND

CABLES IN TWO PLACES
AS SHOWN

=
=
="

USE TAPE

90°

SERVICE

POSITION

FRONT

Figure 3-25

Battery Backup Power Cable Routing, First Memory Cabinet

3-50

MA-1415

1-C

BBU

1-B

CONTROLLERS

/
BBU
1-A

BBU
0-C

BBU
0-A

BBU
0-B

TIE WRAP AROUND CABLES
IN TWO PLACES AS SHOWN

________;.l

HERE

|
|

90°

SERVICE
POSITION

USE TAPE

/
Wik

0,/
17

L‘——_—

D
s

FRONT

Figure 3-26

Box Controller and Battery Backup Cable Routing

3-51

MA-1416

BOX
&

CONTROLLERS

BOX CONTROLLER

RIBBON CABLE

REAR CABLE

FRONT CABLE

ia L = 1d < Q|O c M < o ]

RETRACTOR BARS

|
|

TAPE

MAIN MEMORY

BUS CABLE

I
WRAPS

MA-1417

Figure 3-27

Main Memory Bus and Box Controller Cables

3-52

1-C

TIE WRAP GOES AROUND
CABLES IN TWO PLACES

AS SHOWN

BBU

CONTROLLERS

1-B

BBU

1-A

0-C

BBU
0-A

BBU
0-B

FRONT

REAR CABLE

CABLE
RETRACTOR

RETRACTOR
BARS

BAR

<«——CABLE TROUGH

USE TAPE

HERE

| 90° SERVICE |~
7

MEMORY

|Eee—=""

TO MEMORY #2 54—

| POSITION

a—

FRONT

CABLE

RETRACTOR
BAR
-

e
‘

FRONT

MEMORY
#0

]

FROM PROCESSOR

MAIN MEMORY
BUS CABLES
MA-1418

Figure 3-28

Main Memory Bus Cable Routing, First Memory Cabinet
3-53

Table 3-4

Power Fail

Jumpers

Memory

Last Memory
Box on Bus

Out

All Other

Memory Boxes | In

Table 3-5§

CSR Address Selection
Switch Position

Unit Number

CSR Address

S1-3

0
1
2
3

X772100
X772104
X772110
X772114

Closed | Closed
Closed | Closed
Closed | Open
Closed | Open

X
X

3.6.1

S1-2

S1-1

Closed
Open

106 for direct addressing mode.
17 for indirect addressing mode.

Memory Expansion Cabinet

Expansion memory cabinets are shipped with the memory box, battery backup units, and the box
controller installed and cabled. The second memory cabinet is installed immediately to the right of the
first memory cabinet. At most sites, this requires repositioning the tape or disk drive cabinet since
these cabinets are positioned to the right of the memory cabinet(s).

Prior to installation, check contents of shipment against packing list and inspect for obvious shipping
damage.

Remove shipping container and polyethylene covers from cabinet. Remove tape, plastic
shipping pins and securing bolts from cabinet. Remove side panel from right side of first
memory cabinet.

Raise leveling feet so that cabinet rests on its casters. Roll cabinet onto floor using suitable
ramp. Push cabinet into position along side the first memory cabinet.

Install filler strips between memory cabinets. Lower leveling feet to align height of second
memory cabinet to first memory cabinet. Tighten bolts securing cabinets together. Install
ground strapping between cabinets. Remove shipping bracket from memory box.

Install memory bus cable trough at height indicated in Figure 3-23.

3-54

Extend memory box no. 1 to service position. Remove top cover. Remove strain relief
bracket. Remove address buffer and data buffer modules. Note cable positions, do not alter
folds in- ribbon cables. Configure power fail jumpers per Table 3-4. Remove screws and
unplug memory bus terminators. Connect main memory bus cables to modules keeping
ribbed side up and red stripe to left on component side of board. Replace address interface
and data buffer modules.

Fold outgoing bus cables, keeping ribbed side up and lay them on left side of memory box
just to the right of strain relief bracket retaining screw. Return incoming cables to original
position. Replace strain relief bracket, do not tighten. Pull outgoing cables backward to take
slack out of memory box. Tighten strain relief bracket.
Replace top cover. Tilt memory box no. 1 to 90 degree service position. Tie wrap outgoing
bus cables to front cable retractor bar as shown, taking up slack between memory box and
cable retractor. Keep path of cables parallel to slide rails. Wrap cables together with tape.
Tilt memory box no. 1 back to level position and push memory box back into cabinet.
Extend memory box no. 2 to service position. Remove top cover. Remove strain relief
bracket. Note position of controller ribbon cable.
Fold and route memory bus cables through cable trough into second memory cabinet as
shown in Figure 3-29. Exit cables with smooth side up through front of second memory
cabinet on top of front cable retractor bar. Lay cables on left side of memory box just to the
right of retaining screw. Straighten cables and tie wrap to front cable retractor bar.
10.

Remove address buffer and data buffer modules. Configure power fail jumpers and CSR
address select switches per Tables 3-4 and 3-5. Connect memory bus terminators and incoming bus cables. Replace address interface and data buffer modules. Replace strain relief
bracket; do not tighten.

11.

12.

Tilt memory box no. 2 to the 90 degree service position. Pull upward on incoming bus cables
to take up slack between front cable retractor and memory box. Ensure controller ribbon
cable is returned to former position. Tighten strain relief bracket. Tape incoming cables
together between cable retractor and memory box. Tie wrap cables to floating restraint.
Return memory box no. 2 to level position. Fold incoming cables to take up slack inside of
memory box. Replace top cover.

13.

3.6.2

Place unit number decal on memory box (Figure 3-30) to indicate CSR address as in Table
3-5. Plug in power cord. Verify cabling with diagrams.

MK11 Memory Configuration

Thumbwheel switches on the MK11 box controller select the starting address and the type of interleaving for the memory frame. The thumbwheel switches are eight position switches, labeled from zero
through seven. The octal number displayed by the starting address switches represents the starting
address of the memory frame in 32K word blocks (decimal). The interleave number selects the external
interleaving between two or four memory frames. The control panel decal, Figure 3-31, summarizes
the interleave switch settings and correlates the starting address switch settings to the starting address
of the memory.

3-55

TIE WRAP GOES
AROUND CABLES IN
TWO PLACES AS SHOWN

CABLE TROUGH
,

FRONT CABLE
R/ETRACTOR BAR

l
-

|
|

I
|

MA-1419

Figure 3-29

Main Memory Bus Cable Routing, Second Memory Cabinet

3-56

mkll memory system
BOX STARTING ADDRESS (OCTAL)

CONTROL & STATUS REGISTER STARTING ADDRESS E] 1 ? g ; Z, g : —

INTERLEAVED (] EXT 2WAY (0 EXT 4 WAY
MEMORY SYSTEM SERIAL NO.

sLoT | MopuLE TYPE

I RESPONDS TO :2;;
DATE INSTALLED

Mooé‘éllf fig_oup

MODULE FUNCTION

NOT USED

M7984 —

12 STORAGE ARRAY

M7984 -

710 STORAGE ARRAY

M7984 —

8 STORAGE ARRAY

M7984 —

6 STORAGE ARRAY

M7984 —

4 STORAGE ARRAY

M7984 —

2 STORAGE ARRAY

M7984 —

-0 STORAGE ARRAY

M8161

0 CONTROL B (DATA & ECC)

M8160

0 CONTROL A (TIMING & CONT.)

NOT USED

14 STORAGE ARRAY

M8158

NOT USED

M8159

M8160

T CONTROL A (TIMING & CONT,)

MB161

1 CONTROL B (DATA & ECC)

M7984 —

1 STORAGE ARRAY

M7984 —

=3 STORAGE ARRAY

M7984 -

-5 STORAGE ARRAY

M7984 —

=7 STORAGE ARRAY

M7984 —

0 STORAGE ARRAY

M7984 -

11 STORAGE ARRAY

M7984 —

13 STORAGE ARRAY

M7984 -

NOT USED

ADDRESS BUFFER

|
DATA BUFFER

Figure 3-30

15 STORAGE ARRAY

Memory Box Decal

3-57

BATTERY STATUS

LED'S

FUNCTION

1. SLOW FLASH

FAST CHARGE
SLOW CHARGE
DISCHARGE
BATTERY OFF

|
2. ON

3. FAST FLASH
4. OFF

INTERLEAVE

O EXT INTERL
OT USED
WAY EXT NTERL BOX 0
WAY EXT NTERL BOX 1
WAY EXT NTERL BOX 0
WAY EXT NTERL BOX 1
WAY EXT NTERL BOX 2
WAY EXT NTERL BOX 3

STARTING ADDRESS
K

SET/WORDS|

PANE

SET

-t NOTRNOMNMOOMNMOONOM

OrANMTLONO~NMITDON

Y
=YX -X=)
e X=1=1= =1X=1=1=X=X=X=

Figure 3-31

Control Panel Decal

3-58

PANE

0 RDS|

SET

ORDS

DNOQOWOONNNODOOOOOONO

PANEL

OO OWWOWWOWNPNNNNNSS

O0O00O0OO0OOOOO0OO0O000O

7z RDS|

PANE
SET

Interleaving — Internal interleaving, between the right and left sides of the memory frame, is a function
of the number and types of storage arrays installed in the memory. If both sides of the memory contain
the same number of MS11-KE, MS11-KD, and MS11-KC arrays, then, at power up, the memory will
be internally interleaved. If the memory frame is unbalanced, that is a different capacity or number of
array modules on one side than the other, then the memory will not be internally interleaved. There is
no way to force an unbalanced memory to be internally interleaved. Internal interleaving in a balanced
memory, however, may be defeated. Consult the technical manual for the MK 11 memory for defeating
the internal interleaving.

External interleaving, between two memory frames or among four memory frames, is determined by
the interleave switches on the box controllers. To interleave two memory frames (external two way),
set the interleave switch on one box controller to 2, and the interleave switch on the second box
controller to 3. The memory frame with its box controller interleave switch set to 2 responds to addresses with address bit A02 equal to zero. The memory frame with its box controller interleave switch
set to 3 responds to addresses with address bit A02 equal to one.
Two memory frames may be two-way externally interleaved only if their capacities are equal. Also,
both memory frames must have the same starting address.
Four memory frames may be four-way externally interleaved by using the interleave switch positions
labeled 4, 5, 6, and 7. The switch settings and the addresses that the memory responds to are listed
below.

Box 0
Box 1
Box 2
Box 3

Interleave
Switch Number

Responds to Address Bits
A03
A02

4
5
6
7

0
0
1
1

0
1
0
1

In order to externally interleave the four memory frames, they must all have the same memory capacity. The same starting address must be selected for all four memory frames.

Interleave switch position 0 corresponds to no external interleaving. Use switch position 0 if there is
only one MK11 memory frame in the system or if external interleaving among the boxes is not desired.

Interleave switch position 1 is not used.
Starting Address — Refer to the control panel decal shown in Figure 3-31. The decal correlates the octal
starting address switch settings to the decimal starting addresses in 32K word blocks. The first memory
frame in the system, box 0, will have its starting address switches set to 000. The starting address switch
settings of the second memory frame, Box 1, are determined by the capacity of Box 0 (only if the two
memories are not externally interleaved).
For example, if Box 0 contains 256K words of memory, the starting address switches for Box 1 are set
to 010. The starting address for a third memory frame, Box 2, will be the total of the capacities of Box 0
and Box 1. For a fourth memory frame, total the capacities of Boxes 0, 1, and 2. If, in this case, all four
memory frames contained 256K words, then the starting address of Box 2 would be 512K words. The
starting address switches for Box 2 will be set to 020, from the decal. Box 3 will have a starting address
of 256K + 256K + 256K or 768K and its starting address switches will be set to 030.

3-59

If any of the memory frames are externally interleaved, their box controllers must display the same
starting address. Any memory interleaved with Box 0 will have a starting address of zero. To two-way
interleave Boxes 0 and 1 of the preceding example, set the starting address switches of box controller 1
to 000 and set the interleave switches of Box 0 to 2 and Box 1 to 3. Similarily, Box 2 and Box 3 may be
two-way interleaved by setting the starting address switches of Box 3 to 020, the starting address of
Box 2. The interleave switches of Box 2 and Box 3 will then be changed from 0 to 2 and 3, respectively.

Set the starting address switches to 000 on all the box controllers for four-way external interleaving.
The interleave switch settings will be 4, 5, 6, and 7. Remember that the memory capacity of the four
frames must be equal for four-way external interleaving.

11 memory system, enter the starting address, interleaving information, and
After configuring the MK
the CSR address on the memory box decal. A sample memory box decal is shown in Figure 3-30.
3.6.3

Voltage Checks

3.6.4

PDP-11/70 System Size Register

After completing the installation and configuration procedures, verify the regulated voltage outputs of
the memory frames (Table 3-3). Perform any necessary adjustments as described in Paragraph 4.5.2.2.
The system size register in the PDP-11/70 must be reconfigured to represent the new memory size.
Refer to drawing D-CS-M8140-0-1, sheet SCCN in the PDP-11/70 engineering drawings and to Figure
3-21.

3.6.5

Checkout

Run diagnostics as listed in Figure 3-9.

3.7 NON-MEMORY ADD-ON INSTALLATION
Non-memory add-on installation may be:
1.
2.
3.

System Unit (SU) options
Rack-mounted options
Cabinet options.

The options available to the PDP-11/70 are listed in Appendix F.
Installation in an existing system consists of:

Determination of the optimum electrical and physical position of the option on the Unibus
or on the Massbus guidelines are supplied in Paragraphs 3.7.2 and 3.7.3 to aid in this determination.

2.
3.7.1

Mechanical installation of the option.
Mechanical Installation

SUs are mounted in BA11-K boxes. All required information is supplied in the BAI1-K
Mounting Box Manual, EK-BA11K-MM.

Up to five SPCs may be mounted in the processor cabinet, élots 40-44, Refer to appropriate

manual. Slot 40 is reserved for the DL11-A that controls the system terminal. Any additional SPCs must be mounted in BA11-K boxes.

Instructions for installation of rack-mounted and cabinet options are contained in their,
respective manuals.

3-60

3.7.2

System Configuration (Massbus)

The optimum configuration of the Massbus (RH70) is determined by the same rules used for Unibus
NPR devices (Paragraph 3.7.3). The prepared order of priorities for RH70 devices is as follows:
1.
2.
3.
4,
5.

CPU
RWS(4
RWP0O4
RWSO03
TWUIS6.

The DWR70 is a customer interface; the speed of this interface should determine the position of the
DWR70 on the Massbus.
3.7.3

System Configuration (Unibus)
NOTE

System configuration is a function not only of the
variables mentioned below, but also of size, available
space, and power distribution. These factors are not discussed here, but must be taken into consideration
when a system is reconfigured.

System configuration as defined here is a function of two variables:
1.

The tolerance of each device for delays in service (maximum tolerable latency), and

The data transfer demand placed by each device on the system.

As the demand of device X increases, it increases the time that device Y must wait for service.
The order in which devices are serviced depends upon:

Their assigned priority, in descending order: NPA\R, BR7, BR6, BR5, BR4.

Within each priority, the order in which they are placed on the Unibus (electrical position).

The definitions that follow are taken from the glossary of the Unibus specification:
Latency is the delay between the time that a device initiates a transaction and the time that it
receives a response.

Thus, if a device requests the use of the data section of the bus, is granted the use of the bus,
and then receives the negation of BBSY (signifying that the previous master has released the
data section of the bus), then latency is the delay between the assertion of the request and the
receipt of the negation of BBSY by the requesting device.

Maximum Tolerable NPR Data Transfer Latency is the longest time that a device may be
refused bus mastership before it loses data. It affects only devices that transfer data in a
constant stream, e.g., a disk.

Maximum Tolerable BR Interrupt Latency is the longest time the computer may take to
service an interrupt before the requesting device loses its data. The service time includes the
execution of all higher priority interrupts and programs that may be pending, plus the time
spent in the interrupt subroutine of the device in question,
3-61

From the preceding, general rules for configuration may be stated as follows (‘‘behind’’ means farther
from the processor):
1.

In general, BR devices should be placed physically behind NPR devices; thus, the propagation delay of fast NPR devices is reduced and transfers are faster. For convenience, however,
some BR devices are sometimes placed before NPR devices, e.g., DL11-A/LLA36 is first on
the Unibus in the PDP-11/70 (slot 40 of the processor backplane.)

Buffered devices (Category 2: see Figure 3-33 for definition) should be placed physically
behind unbuffered devices (Category 1: see Figure 3-33).

Ineither category, devices with higher transfer speed rates should be placed ahead of devices
with lower transfer speed rates.

Less used devices may be placed behind devices that are accessed more often, if required.

Figure 3-32 shows the optimum placement of Massbus and NPR Unibus devices in a PDP-11/70
system.

The flowchart (Figure 3-33) provides an algorithm by which these variables can be combined to produce an optimum Unibus system configuration of both NPR or BR devices. BR devices are placed

behind NPR devices with the same data transfer rates, and before NPR devices with slower data
transfer rates. The same algorithm is used. This flowchart is intended only as a guideline.
NOTE
The algorithm given in Figure 3-33 suggests the opti-

mum positioning of contending devices on the
Unibus. This positioning is not mandatory. If the
configuration resulting from the use of this algorithm
is not satisfactory, alternative placement of devices
should be tried.

3-62

PDP-11/70 PROCESSOR

MASSBUS (RH70)

UNIBUS DEVICES (NPR)

DEVICE PRIORITY

)

RWS04

XFER RATE > 90 KC/S (11 us/XFER)

RK11C/RK05 (90 KC/S, 11 us/XFER)
RK11D/RK05

RWPO4

RWS03

TWU16

90 KC/S < XFER RATE < 36 KC/S (28 us/XFER)

TM11/TU10 (36 KC/S, 28 us/XFER)

36 KC/S < XFER RATE <5 KC/S (200 us/XFER)

TC11/TU56 (5 KC/S, 200 us/XFER)

5 KC/S < XFER RATE < 1.7 KC/S (600 us/XFER)

RP11C/RPO3 (TL = 463 us)

RF11/RS11 (TL = 100 ms)

XFER RATE < 1.7 KC/S (600 us/XFER)

END OF UNIBUS

11-3480

Figure 3-32

PDP-11/70 Configuration

3-63

Unibus Loading Rules:

GIVEN A DEVICE OR SEVERAL
DEVICES TO BE ADDED TO AN

A) Maximum loading before the first bus repeater is 19DC
bus loads; between two adjacent bus repeaters is 18DC

EXISTING PDP-11/70 SYSTEM

bus loads.

B) Maximum unibus cable length between the first bus
repeater and the cpu or between the adjacent bus
repeaters is 50 ft,

ADD DEVICE

DOES THE

TO SYSTEM

THIS CONFIGURATION

CONFIGURATION

IS THE OPTIMUM

VIOLATE THE

FOR THE SYSTEM.

UNIBUS LOADING
RULES

DATA

XFER RATE OF

MAXIMUM DATA

DEVICE FIXED

YES

DATA

YES

USE
::?::;lfis

XFER RATE

DEVICE

| TRANSFER RATE

CD-11E

1000 cards/min

"
1200 ©
CD11-A
<«—] DA11-B/ | 500K words/see
DR11-B

DETERMINED,

DH11

OF DEVICE

16 x 9600 Baud

DQ11-DA | 10K Baud
DQ11-EA | 1MegaBaud
9.6K Baud
DV11
20 us/point
GT40

YES

MAXIMUM

NPR RATE
ADD A BUS

1.3 KC/S

REPEATER

16 ~
500

AT END OF

VERIFY

BUS IF

SYSTEM

154

NECESSARY

(FIG. 3-9)

125 ~
125 ~
57.6 "
'
50

MOVE THE LAST OR
THE LEAST

FREQUENTLY USED
UNBUFFERED

DEVICE BEFORE

C oone

CATEGORY 2:

‘(1)

BUFFERED devices that have more

DEVICE A

than 6 words of data buffer, e.g.:
RP11C/RPO3. {2) RF11/RS11 is also

BELONGS TO
CATEGORY 1

DEVICE

1S
YES

YE#

FIG. 3-20

NPR RATE

< 1.7 KBC/S

LISTED IN

Category 2 device Unibus sequence is
determined by comparing Tl of the devices:

words to/from device

COMPUTE

Tbblup = Typical data bubble-up

time of controller

1. if sector size of device > dbs,
Tdbs = dbs x instantaneous data xfer

TC11/TU56. The
exception is the

RF11/RS11, which

PLACE DEVICE

NPR RATE
= WORD/SEC
or

CATEGORY 1

DECREASING

AFTER

BEFORE

BEFORE ANY
DEVICES

RATES ARE

< 1.7 KBC/S

2. If sector size of device < dbs,
Tdbs = (dbs x instantaneous data xfer
rate) + {sector gap in ps) + xfer

DQ11,DR11, GT40,
RK11/RK05. TM11/TU16,

IN ORDER OF
INCREASING
T, VALUES

WHOSE NPR

rate of device

Devices whose controllers have < 6

belongs to Categ. 2

1
PLACE DEVICE

T = Tdbs - Tbblupx2

where dbs = device data buffer size
Tdbs = time required to xfer dbs

CATEGORY 1:
94—

words of data buffer,
e.g.: CD11, DA11, DH11,

DEVICE

T,
= Maximum Tolerable NPR or BR Latency.

AFTERIT.

DEVICE

CATEGORY 2

a Category 2 device.

THE BUS REPEATER
TO IMMEDIATELY

)

IN ORDER OF

NPR RATES

CATEGORY 2

DEVICES

IN ORDER OF

NPR RATES

CATEGORY 2

DEVICES

= CARDS/MIN X 1.33
=BAUD RATE
n

where 7 = bits/char

(typically 7-10)

rate x number of words required

from second sector

THIS
LAST DEVICE
ADDED

Figure 3-33

Flowchart

3-64

11-3484

CHAPTER 4
POWER SYSTEM

4.1
SCOPE
This chapter describes ac and dc power in the PDP-11/70. Both the processor cabinet and the memory
cabinet power systems are discussed. Included are descriptions of the power supplies, their location
within the cabinets, how they function, voltage adjustments, and component removal procedures.

4.2 OVERALL SYSTEM DESCRIPTION
Figure 4-1 shows the physical location of the PDP-11/70 power system. The basic components are two
861-D/E power controls (one in the processor cabinet and one in the first memory cabinet), two H7420
power supplies (both located in the processor cabinet) and one power supply (per frame of memory),
located in the memory cabinet. Additional power controls would be required if the basic system is
expanded.
MINIMUM

ll_ _______ 4

[7
I
|
I

:
I

l
h

|
|

(EXPANSION

CABINET)

[

CONFIGURATION
e

|
(1ST)

PROCESSOR

MEMORY

CABINET

Jl _________ d

(2nD)

MEMORY

CABINET

SUPPLY

LOWER

MEMORY

SUPPLY

II‘ —————— —l

SUPPLY

||
!

‘

H7420

POWER

CABINET

h
|I|

TU16

|I
UPPER

B A Al
II:
1

|
|

] R1l

II'

;

l— —————— AFbr———————-—- —!|

i
se1-c
861 D/E
861D/E
|
8eto/E
il
861-C
,
|' POWER CONTROL | | POWER CONTROL | | |POWER CONTROL || POWER CONTROL!|| POWER CONTROL!
——————— ~
b=
——= 2y

Figure 4-1

=il

— = == —
S
H oo
e ——e

bre

11-337

PDP-11/70 Power System, Physical Location

Figure 4-2 is a block diagram of the power system for a typical PDP-11/70. The processor and memory
cabinets derive their ac and dc power from separate sources. In the processor cabinet, the basic devices
are an 861-D power control (120 Vac line voltage) or an 861-E power contro! (240/415 Vac line
voltage), and two H7420 power supplies. The memory cabinet contains a separate 861-D or E power

control and a memory frame power supply. (Up to seven additional MJ11 memory frames or three
additional MK11 memory frames can be installed. Each would require a separate memory frame
power supply. Refer to Paragraph 4.3.2.).
4-1

PROCESSOR CABINET- —
—— ———
861—-D/E POWER CONTROL

o —

SWITCHED
AC

)

CIRCUIT BREAKERS
& CONTROL

|NOTE 2

UNSWITCHED

CUT-OFF

SENeY

)

ETE

THERMAL

5411086

REGULATOR &

O . oo O

E———————SEE T

eL e

REGUL

20-30VAC

INPUT

ATORS

|
|

HT44

HT744

H744

‘

+5V

TERMINAL

45V

+5V

UPPER & LOWER
LOGIC FANS

1S VAC

NOTE 2

TRANSFORMER
REGULATOR FANS

-~
POWER

OUTLETS

LINE FILTER,

___'__

CIRCUIT BREAKERS

3 PHASE

8 CONTROL

AT
POWER

OUTLETS

[

¢ EIOTE
é2
.1

THERMAL

|
|

AC INPUT
BOX

ASSEMBLY

(NOTE 3)

20- 30vAC

HT754

HT44

(2)

+20/-5V

AG
POWER

]

HT54

HT44

(3)

(4).

+20/-5V

]

+5V

|
|

MEMOR Y
DISTRIBUTION

4
¢NOTE
|

PROTECTION
PROCESSOR &

| NOTE 3 , BaCKPLANE DC |
o

CONTROL
I_O
ON
SHORTED
l POWER
(NOTE 3}

i
i

+5V

THERMAL SWITCH
CONTROL

)

e —)

1S VAC

——————

———————

REGULATORS

15/230VAC | TRANSFORMER | 20-30VAC

UNSWITCHED

‘_

115/230VAC ¢3

SWITCHED

DC DISTRIBUTION

PPLY
MJ11 POWER SUPP
|

PROCESSOR

MON ITOR

EANS

POVER
MonNE
(5411086-YA)

ACLO, DCLO SIGNALS

MEMORY

POWER CONTROL

NOTES:

1. Included with floating point processor {optional)

2. Part of power distributlion cable harness 7011051
3, Part of power cable harness 70O10580.
4.

AC/DC low wire harness

To optional memory frames.

Figure 4-2

7010581 and main memory

bus cabie.

Typical PDP-11/70 Power System

4-2

POWER LINE

e o

—15V, ACLO, DCLO SIGNALS

—15V

REGULATOR &

N
.
)
'861 - D/E POWER CONTROL

5411086

ce e

POV&ERO
CONTROL

|
115 VAC

—& PROCESSOR

| > BACKPLANE

+5v

20 - 3OVAC

& TRANSFORMER

115/230VAC

CONSOLE LOGIC

> AND POWER

—

LOWER H7420 POWER SUPPLY

FANS

PMONITOR

‘

NOTE 2

SWITCH

PROCESSOR CABINET

CABINET

— L e

REMOTE CONTROL
(7010695)

+5V

+8Y, +15v, ACLO, DCLO, LINE CLOCK SIGNALS

+8, +15V

REGULATOR FANS

HT44

+5v

TRANSFORMER
A

eLapseo
MT!_?AER |I

20-30VAC

15 VAC

$1
—_—

1157230 VAC ¢!

‘
i

OUTLETS

switer < NOTET 2
THERMAL

5 VA

H744

NOTE
1

|
1"

H744
+5V

45V

TERMINAL

8 TRANSFORMER

POWER

INPUT

!
|

H744

20-30VAC

115/230 VAC ¢2

UTLETS

cONSOLE

1
!

C—— — S S ———————— — —
REGULATORS

-——
'—___.
| UPPER H7420 POWER SUPPLY

115/230 VAC #1

OPG‘#ER

LINE FILTER,

1157230 VAG
|
3 phase

DEVICES IN
PROCESSOR

TO PERIPHERAL

- 4084

4.2.1

Processor Cabinet

The processor cabinet 861 power control is connected to the building mains (120 or 240 Vac 3 phase
wye) which must be capable of supplying 24A (861-D) or 15A (861-E) per pole. Two types of outlets
are provided on the 861: switched and unswitched (Figure 4-2). The switched group of outlets, which
can be controlled either locally or remotely, consist of phase one, two, and three outlets. The un-

switched outlets, however, are controlled solely by the 861 front panel circuit breakers; they are all
phase one. The processor cabinet 861 switched outlets are controlled remotely by a switch on the
processor console and a thermal cut-off switch in the processor mounting box. A second thermal
switch is flush mounted on the side of the 861 box. These switched outlets are de-energized if either
sensor detects an over temperature or the console switch is turned to the OFF position. The memory
cabinet 861 switched outlets are also de-energized at the same time since the 861s are connected by a
remote control cable.

Two H7420 power supplies, designated the upper H7420 and the lower H7420 according to their
cabinet mounting location, are connected to phase one and phase two switched outlets, respectively,
on the 861 rear panel. Each H7420 power supply contains four H744 +5 V regulators (three in the
upper H7420 if the floating point option is not included in the system). These regulators furnish +5
Vdc to the processor backplane and the processor console. Their applications are listed in Table 4-1. A
circuit description of the H7420 is provided in Paragraph 4.4.4.

In addition to the H744 regulators, each H7420 contains a 5411086 regulator. The 5411086 regulator in
the upper H7420 provides a +8 V and +15 V to the processor backplane and functions as the power
line monitor for the upper supply. This upper 5411086 also produces the line clock output that is used
to drive the KW11-L line frequency and KW11-P real-time clock option. The 5411086 in the lower
H7420 furnishes -15 V to the processor and monitors the lower supply for a low voltage condition. AC
LO and DC LO signals are asserted in the event of a low voltage input to either 5411086 regulator
(Paragraph 4.4.6.1 and Figure 4-34).

Completing each H7420 power supply are the input terminal block and the transformer assembly. The
input terminal block in the upper H7420 provides 115 Vac to the elapsed time meter (which is mounted
at the rear of the processor cabinet) to the power supply fans (one for the transformer and three for the
regulators), and to the transformer primary. The lower H7420 input terminal block provides similar
connections. However, in place of the output to an elapsed time meter, the lower input terminal block
supplies 115 Vac to the processor mounting box fans (five upper and four lower). The terminal block in
an H7420 used in a 230 Vac environment (861-E power control) provides the same voltage outputs.This is accomplished through the use of a different jumper configuration on the terminal block
itself (drawing D-CS-H7420-0-1 and Figure 4-28). The transformer produces 20-30 Vac at the secondary (the actual voltage is subject to input voltage fluctuations). Outputs are provided to the H744 and
5411086 regulators.

A single power distribution cable harness (7011051) distributes the power and signal outputs from
both H7420s. In addition to delivering dc voltages to the processor console and the processor backplane, the cable routes the AC LO and DC LO signals to the memory protection logic and to the
processor power control logic. The line clock signals go to the line time clock. Also contained in the
cable harness are connecting wires from the processor console switch and the thermal cut-off sensor to
the 861-D/E power control. Figure 4-3 illustrates how the power distribution cable connects the 861
and the H7420s with the processor backplane.

A more detailed description of the processor cabinet and the H7420 power supply is provided in

Paragraph 4.4.4.

4-3

Table 4-1

Processor Power Supply Voltage Regulators

Type

Name

Quantity

H744

+5 V Regulator

8 (Note 2)

Location

Application

+5 V to processor module slots
2-5. Included
only with the
FP11 option.

(Note 1)

(Figure 4-20)

+5 V to proces-

sor module slots
1, 6-9.

+5 V to processor module slots
10-15.
+5 V to proces-

sor module slots
36-44.
H

+5 V to processor module slots
20-22.

+5 V to processor module slots
16-18 and to the
console.

+5 V to processor module slots
24-28.

+5 V to processor module slots
29-35.

5411086

+8, +15 V Regulator

Upper H7420 |

+8 and +15 V to

5411086

-15 V Regulator

Lower H7420 | -15 V to processor backplane;
AC LO and DC
LO sensing for

processor backplane; AC LO
and DC LO sensing for the upper
H7420.

the lower H7420
Notes:

Location within the H7420s.

Seven if the FP11 option is not included.
4-4

PROCESSOR

P34,P35

P8 (TO THERMAL SWITCH & $2

ELAPSED
TIME METER

CABINET FANS

POWER FOR LOGIC FANS)

7011051 HARNESS

UPPER

H7420

$1 UNSWITCHED

)

Aaa

420

BACKZU
s

$1 SWITCHED

'DEV'EVOIR

LOWER

H7420
86
POWER CONTROL

\__

J10 (H7420-42)

$2 SWITCHED

J14 (HT420-43)
_

J15(H7420-J4)

D|C|B\A

J6 JT

f&—&—;—\g—\g =]

o Lpl opl

g oq

Ji3

Jt2

J21(HT7420-43)

427"

CcPU

BACKPLANE

J22 (H7420-44)

J26

PIN SIDE VIEW

J16(H7420-42)
11-4086

Figure 4-3

Processor Cabinet Power Connections

4.2.2

Memory Cabinet

As previously mentioned, the memory cabinet has its own power system (Figure 4-2). This system
consists of an 861-D/E power control and a memory power supply. The 861s in the processor and
memory cabinets are connected via a remote control cable (7010695). This cable connection allows the
switched outlets on both power controls to be de-energized in the event either power control is shut
down due to over temperature or if the console switch is turned to the OFF position (MJ11 only). The
memory cabinet 861-D/E is connected to the building mains (120 or 240 Vac 3-phase wye). This source

must be capable of supplying 24 A (861-D) or 15 A (861-E) per pole. Switched and unswitched outlets
are provided on the 861; the switched outlets are the power source for the one or more memory frames
included in the system. Switched phase 3 power is used if the minimum memory configuration of one
frame is installed.

The MJ11 power supply (120 Vac: 7010694-00; 240 Vac: 7010694-01) consists of an ac input box with
an associated power control circuit, a transformer assembly, a power line monitor circuit, four voltage
regulators and two 1211714 fans.

The MK 11 power supply (120 Vac: 7014227-00 240 Vac: 7014227-01) consists of an ac input box with
an associated power control circuit, a transformer assembly, a power line monitor circuit, four voltage
regulators, two 1211714 fans, and three H775 battery backup units.

The ac input box, under the direction of the ac power control circuit, routes the ac input power to the

transformer assembly. Two types of boxes are used: one (7009811-1) for a 120 Vac input from an 861D power control, and one (7009811-2) for a 240 Vac input from an 861-E power control. Only one ac
input box is installed in each memory power supply. The ac power control circuit (5410993) controls
the 120/240 Vac input to the transformer. A shorting wire in the MJ11 maintains the circuit in an ON
condition, i.e., power is routed to the transformer. However, an input from a thermal switch attached
to the transformer can open this circuit if an over-temperature condition is sensed. In the MK11, the
power switch on the box controller switches ac power to the transformer via connector J4 on the ac
input box.

In the 7010014 (MJ11) or 7011486 (MK 11) transformer assembly, two terminal blocks, with power
inputs from the ac input box, have outputs to two fans that cool the transformer. Other terminal block
outputs are to the transformer, which steps down the line voltage (120/240 Vac) to the required 20/30
Vac input for the regulators and the power line monitor circuit.
The power line monitor circuit and 15 V regulator are part of the 5411086; the regulator portion of the
card is not used in the MJ11 or MK11 application — 5411086-Y
A. If a low voltage condition occurs at
the 20-30 Vac input from the transformer assembly, the 5411086-YA asserts AC LO and DC LO
signals. These power fail signals are carried to the memory protection logic and to the processor power
control logic via a wire harness (7010581) and the main memory bus cable.

There are four voltage regulators used in the MJ11 power supply, two H744 and two H754. The H744
regulators generate +5 V and the H754 regulators generate both -5 V and +20 V. These dc voltages
are routed to the memory backplane through the power cable harness (7010580). This cable also
carries the 20--30 Vac input to the regulators from the transformer.
There are four voltage regulators used in the MK 11 power supply, one H7441 and three 7014251. The
H7441 regulator generates +5 V and the 7014251 regulators generate +5 V, +12 V, and -12 V. Cable
harness 7014228 routes the stepped down ac voltage to the regulators and also routes the regulated
voltages from the regulators to the memory backplane.

Figure 4-4 shows the power and signal connections between the 861 power control, the MJ11 power
supply and the memory backplane. Figure 4-5 shows the power and signal connections for the MK11
memory.

4-6

861 POWER
CONTROL

MJtt

POWER SUPPLY

(SEE NOTE)

$3 SWITCHED

7010680

8 7010584

HARNESS

NOTE:

Fans (2) not shown

J16

REGULATOR 4

H744

REGULATOR 3

NOWER

H754

AC INPUT BOX

VIEW

J2=

REGULATOR 2
.
H744

REGULATOR 1
H754

~121\‘D

supPLY VI~| TRANSFORMER St

BOTTOM

P17/t

P2/J2

J20~_|

J1o__|

MEMORY

BACKPLANE

(PIN SIDE VIEW)

~~J14

‘

J,e/’fl
1-4085

Figure 4-4

MJ11 Memory Cabinet Power Connections

4-7

H775

BATTERY BACKUP

UNIT B

H775

BATTERY BACKUP
UNIT C

861 POWER
CONTROL

POWER

SUPPLY

(SEE NOTE)

$3 SWITCHED
P31

7014312

HARNESS

7014228

& 70105814

HARNESS

H775

UNIT C

BATTERY BACKUP

]

;

Fans (2) not shown

b
2

&
*Q/aatAY)

J16__P26

REGULATOR C

30~ 7014251

REGULATOR B

"P‘guER
BOTTOM
VIEW

129—ag 7014251

AC INPUT BOX

,fi/

+5 REGULATOR
fomt

REGULATOR A
7014251

P25

P1/Jt

p2/J2

Sr— 3

=
H7444

Jee—q

Pa7

JI15__p24g

JZO\

‘U

yio—J]

MEMORY
(PIN SIDE VIEW)

~~~J14

| —%— psp

.—U‘F p23

.{,\

Jai-_|

J18-"]

=l
MA-1487

Figure 4-5

MKI11 Memory Cabinet Power Connections

4-8

The contents of the power system are housed in a welded steel chassis. The chassis is rectangular and
measures approximately 7-3/4 inches long by 10-1/2 inches high by 17 inches wide. The top power
system cover is held in place by six screws. The main structural member contains cutouts and drill
holes which enable screws to be inserted for securing the regulators, ac input box, transformer assembly, and fans. Cutouts for the regulators allow the regulator ON indicators to be monitored and the
regulator output voltages to be adjusted.
A more detailed description of the memory cabinet and the power supply is provided in Paragraph
4.4.6 for the MJ11 and Paragraph 4.4.7 for the MK11.
4.3 PRIMARY AC POWER, 861 POWER CONTROL
Power from the building mains is applied to the system components in the processor, memory, and
expansion cabinets through 861-D/E power control units. In a minimum configuration system consisting of a processor cabinet and a memory cabinet, power is controlled by two 861-D/E power
controls, one in each cabinet. The controls are located at the bottom front of the cabinets (Figure 4-1).

The 861-D is used with 120 Vac, 3-phase lines; the 861-E is used with 240 Vac (415 Vac phase to phase),
3-phase lines. Both versions are contained on panels intended for mounting in racks or cabinets that
accept standard 19-inch panels. Each power controller requires 5-3/16 inches of vertical mounting
space and extends 11 inches into the mounting rack or cabinet.
Figure 4-6 is a simplified block diagram of the 861-D Power Controller. Four basic functions are
performed:
1.

Control of large amounts of power by control signals of small power content.

Convenient distribution of primary power to controlled devices.

Filtering of primary power to controlled devices.

Automatic removal of primary power from controlled devices in case of overload or overtemperature conditions.
-

Circuit descriptions of the 861-D and 861-E are given in Paragraph 4.3.5; ac power and remote power
control connections are described in Paragraphs 4.3.2, 4.3.3, and 4.3.4.

.
AC

INPUT [~

LINE

| FILTER|

PILOT

CIRCUIT

UN=-

BREAKERS

DUTCHED

CON-

SPIKE

CIRCUIT

| LAMPS [ |BREAKER[ ]

pyp—

OFF
LOCAL
SWITCH

| TacTOR [| SURPRESSION '——
CIRCUIT

CIRCUIT

ggeakers [

SWITCHED
ouTLeTs

l
POWER REQUEST
PILOT
CONTROL#— EMERGENCY SHUTDOWN
CIRCUIT
[«— COMMON

THERMAL
SWITCH
ii-3029

Figure 4-6

861 Power Controller Simplified Block Diagram

4.3.1
Power Control Specifications
Power control specifications are listed in Table 4-2. Reference should be made to the 861-4, B, C, D, E,
F Power Controller Maintenance Manual for additional information.
4-9

Table 4-2

Mechanical and Environmental
Dimensions

Power Controller Specifications

12.7cmh, 48.57 cm w, 27.94cmd (5in h X 19-1/8

inwx 11 ind)

Weight

12.24 kg. (approx) (27 1b)

Cooling Method

Convection

Mounting

Rack (standard 19 in)

Ambient Temperature (recommended temperature)
Operating

0° to +70° C

Storage

-40° to 71° C

Relative Humidity

95% max

Altitude (max)

2438 m (8,000 ft)

Shock, Non-operating

40 G (duration 30 ms)

Vibration, Non-operating

1.89 G rms average, 8 G peak; varying from 10 to
50 Hz, 8 dB/octave roll-off, 50-200 Hz; each of six

(no condensation)

directions

Electrical
Input Power

Voltage-phase to neutral
of 3-phase wye

861-D: 90 Vac - 132 Vac
861-E: 180 Vac - 264 Vac

-phase to phase

861-D: 156 Vac - 229 Vac
861-E: 312 Vac - 458 Vac

Phase

3-phase (120 degree displacement) wye connection

Frequency

47-63 Hz

Current

861-E: 24 A per phase
861-E: 15 A per phase

Power Requirements
Full load

861-D: 8640 VA
861-E: 10800 VA

No load

10 VA maximum

Inrush Current Capability

600 A peak, 1/2 cycle per phase

Input Overvoltage Transient
(power controller alone)

180/260 V, 1 second
360/720 V, 360 ms

4-10

Table 4-2

Power Controller Specifications (Cont)

High Voltage Transients

Magnitude
Duration
Frequency
Average Power

1 kV
<0.1us
<10 us once every 10 s
<0.5W

Leakage Current

861-D: 1.75 mA max
861-E: 3.5 mA max

Activate Time

20 ms (from switch closing to power out)

Deactivate Time

10 ms (from switch opening to power out)

Input Breaker

Delayed action, manual reset, magnetic; 861-D: 30
A; 861-E: 15 A

Thermoswitch

Opens at 71.1° C (160° F), automatically resets at
49° C (120° F), (exposed to ambient air external to
controller)

Input Power Connection

861-D: NEMA L21-30P
(Table 4-3)
861-E: None provided

Remote Power Control
Remote Switching Control Connectors

Three: Female, AP 1-480304-0 (DEC-12-09350-03)
with Amp 61117-4 (DEC-12-09379) pins or equivalent. These mate with AMP 1-480305-0 (DEC-1209351) connectors with AMP 61118-4 (DEC-1209378) pins or equivalent.)

Remote Control Cable

DEC 7010695

Input Signal Current Levels
(for worst case line voltage)

0.5 mA min, 40 mA max Power Request
0.5 mA min, 80 mA max Emergency Shutdown

Input Signal Voltage Levels
(for worst case line voltage)

+3.0 V max = low; +35 V min = high

Bus Signal Line Overload Capability

125 Vac rms, 60 Hz, 13K ohms impedance in relation to pin 3 for two seconds with no damage

Power Control Impedance

Inductive (diode suppressed)

Power Control Capacitance

200 pF (max)

Output

Outlets (power)

14 (10 switched, 4 unswitched)

Outlet Current Ratings

861-D: 15 A /outlet, 24 A /phase
861-E: 12 A/outlet, 15 A/phase

4.3.2

Power and Power Control Connections

The H7420 processor cabinet power supplies and the memory cabinet power supply are connected to

the switched outlets of the two power controls. All power supplies within these cabinets are single
phase. The upper H7420 is plugged into a phase 1, circuit 2 outlet while the lower H7420 is plugged

into a phase 2, circuit 1 outlet on the processor cabinet 861 power control (Figure 4-7). If the system
contains a single memory frame, the memory power supply is connected to a switched phase 3 outlet
on the memory cabinet 861 power control. Additional memory frames use switched phase 1, 2, or 3
outlets on the 861, as shown in Figure 4-8.

TO CONSOLE
KEY SWITCH (P1)
(NOTE 1)

f'é""“%"

1-CIACUIT

UNSWITCHED

{

]

QFF

| &P
CIRCHT 2

cimeunT ¢

®ll®

£
PHASE

Z4A/NIABE

3 WIRE

REMCTE ] LOCAL

CIRCUIT ¢

POWER [CONTROL 061

=\ INPUT f20V 3060 HZ

@
®

(NOTE 1)

P23 % P24 }{

J1/P1

ON MEMORY
CABINET 861
POWER CONTROL

TO LOGIC
THERMAL
SWITCH

cutT

]

@® 15 amps ar 120 vouTs
CIRCVIT

HAXIMUM

PER CIRCUIT

CABINET
FANS

FRONT

PANEL

ow—
1

(RED) ——7»
() «—— POWER REQUEST

2 (BLACK) —1»
() <1— EMERGENCY SHUTDOWN
3 (GREEN)

— 7o () <—— SIGNAL RETURN
Lr

S—

FRONT PANEL REMOTE

CABLE
CONNECTORS J1,423,J24

TO UPPER

TO LOWER

PowER

l [

@ EE)| -

5 | Pl

H7420

*-'@@d

N CIRSUIT 2

REAR

CIRCUIT | e CIRCUIT 2 —Am CIRCUIT1

PANEL

NOTES:
1. Part of harness 7011051,
1-3315

Figure 4-7

Procéssor Cabinet Power and Remote Control Connections

4-12

PROCESSOR

1ST MEMORY

2ND MEMORY

CABINET

CABINET /
FANS : @1

UNSWITCHED

(MJ11)

(NOTE 2)

a3
(NOTE 2)

(MJ11)
g2

(MJt1)
ge

UPPER
H7420

@1 (MJ11)

@3 (MJ11)

Z1 (MK11)

@2 (MK11)

LOWER

@3 (MJ11)

H7420 .
g2

1({MJN

@3 (MK11)

oIt

(NOTE 1)

B3(MK1t)

EJ0E

1
3

NOTES:
1.Minimum memory:

K bytes.
128

2.Refer to chapter |
for allowable peripherals.
MA-1485

Figure 4-8

PDP-11/70 Power (Phase) Assignments

The 861-D/ E power controls in adjacent cabinets are interconnected to allow power in all cabinets of
the system to be controlled from the processor console (power ON/OFF) or from emergency shutdown devices, i.e., thermal sensors. The remote power control cables used to interconnect the system
cabinets contain three conductors and connect to three pin Mate-N-Lok connectors that are plugged
into the 861 front panel (Figure 4-7). The following signals are routed to the pins:
Pin 1

POWER REQUEST - A ground on this line activates the power control circuits and
energizes the device.

Pin 2

EMERGENCY SHUTDOWN - A ground on this line de-energizes the device.

Pin 3

GROUND RETURN - This is the ground return for the preceding two signals.

The three remote power control connectors on the power controller are connected in parallel. When
power is turned on at the processor console, a ground is routed via the power request line to all the
power controllers in the system, causing their switched outlets to be energized.
A more detailed description of remote power control is contained in Paragraph 4.3.4.

4-13

4.3.3

Primary AC Power Connections

Of the two 861 power control versions supplied with the PDP-11/70, only the 861-D is equipped with
an input power cable and connector. This cable is 15 feet long and consists of insulated stranded
conductors. The input power cable connector and receptacle part numbers are listed in Table 4-3. The
primary power outlet (receptacle) at the installation site must be compatible with the input power cable
connector on the 861-E, Figure 4-9 shows the 861-D connector and receptacle outlines in addition to
.

wire color coding information.

NOTE
In MK11 memory cabinets, the 861
LOCAL/OFF/REMOTE switch must be in the
LOCAL position. Power to the memory is controlled
by the box controller power switch.

Table 4-3

861-D Input Power Connector

Description

Poles

Wires

120 Vac, 30,
30 A, 5-prong

5
No.10 AWG

twist

Plug

Receptacle

NEMA

DEC No.

Hubbell No. | NEMA

DEC No.

Hubbell No.

L21-30P

12-12314

2811

12-12315

2810

L21-30R

RECEPTACLE

PLUG

Gggs;g

BLACK

NEUTRAL

RED

— GREEN

$3
NEMA L21-30R

ORANGE

NEMA L21-30P
"
1-3165%

Figure 4-9

861-D Power Control Connector Outline

4-14

Power Control Connections

Remote
controls are
Each cabinet in a PDP-11/70 system has one 861-D or 861-E power control. All the power
signal
turn-off
y
emergenc
an
1),
(line
signal
turn-on
connected by a 3-wire bus that carries a remote
the
of
ly
respective
3,
and
2,
1,
pins
on
appear
signals
(line 2), and a control ground (line 3). These

4.3.4

power control’s J1, J23 and J24 connectors. Operation occurs as follows:

Connection between line 1 and line 3 energizes the power control relay and applies power to
the components under control. When the LOCAL/OFF/REMOTE switch on the power
control is in LOCAL, line 1 and line 3 are connected.

Connection between line 2 and line 3 overrides all other conditions to disconnect input

power to the components under control.

If no connection exists between either lines 1 or 2 and line 3, the components will remain in

the power off state unless the LOCAL/OFF/REMOTE switch is in LOCAL.

Table 4-4 summarizes these connectors.

Table 4-4

Power Control Operation
Switch Position

Connections
Between Control
Lines

Local
Switched
Power is:

Off
Switched
Power is:

None
1-3
2-3
1-3,2-3

ON
ON
OFF
OFF

OFF
OFF
OFF
OFF

Remote
Switched
Power is:

OFF
ON
OFF
OFF

Three identical parallel-wired Mate-N-Lok connectors are provided on each power control. A 3-foot
cable, DEC part number 7010695, is supplied with each cabinet to connect the power control of that
cabinet to the power control in the next cabinet (Figure 4-10). Because each power control must be
capable of connecting to the power controls in the preceding and following cabinets, two Mate-N-Lok
connectors are reserved for the intercabinet cables; a third connector is provided for connection to
thermal switches and other shut-off devices within the cabinet.
Power Controls 861-D and 861-E

4.3.5

Two versions of the power control are available for use in the PDP-11/70 (Figure 4-11):
1.

861-D 90-132 Vac, 47-63 Hz, 3-phase, 24 A /phase (30A circuit breaker)

861-E 180-264 Vac, 47-63 Hz, 3-phase, 15 A/phase (15 A circuit breaker)

Circuit schematics of the 861-D and 861-E power controls are included in the engineering drawing set

(D-CS-861-D-1 and D-CS-861-E-1).

Both versions of the 861 are similar. However, they are discussed separately in Paragraphs 4.3.6 and
4.3.7 for clarification purposes. The pilot control boards in the 861-D and 861-E are identical; they are
described together in Paragraph 4.3.8.

EXPANSION

CABINET

PROCESSOR

[12 3] [12 3]

UPPER

MJi1

H74 20

POWER SUPPLY

P/J

{12 3]

OUTLETS

SWITCHED AC OUTLETS

861-D/E POWER

P24

7010695

Lfi 2 3]

L1 2 3]

Lj 23|

CABLE

Lj 2 3!

Lj ZAfJ

[12 3]

91-v

CONTROL

LOWER

861-D/E POWER CONTROL

MEMORY CABINET

H7420

SWITCHED AC

861-D/E POWER CONTROL |

CABINET

PO P8
N\

P/O POWER

HARNESS 7011051

;E&;;fL
SWITCH

(N.O.)
I

| P/O

: CONSOLE
:

J
OFF

LOCK
POWER

)

U
— |

1~3319

Figure 4-10

Example of Remote Power Control

POWER CONTROL ae| D

r~ swncm—:oj

CIRCUIT ¢
®
®

=1 veuT 120v 50,60

[0 S P HASE S WiRE 24a/PHASE

LOCAL
REMOTE|
s, ON
ON

PHASE 2

[¢)o

UNSWITCHED

@
@

SWITCHED
=

CIRCUIT

® 15 AMPS AT 120 VOLTS
MAXIMUM

PER CIRCUIT

®]

—

PHASE !j_ PHASE

PHASE 3

() Cat) () ®l®)

()
()

Ca) (')

LCIRCUIT 2 —A—CIRCUIT

GIRCUIT 2 —4 CIRCUIT1 ——— CIRCUIT 2 mmed

£
@

PHASE 1-CIRCUIT{

MAIN POWER

PHASE 1

f——— swiTCHED

e
@

=] POWER

CONTROL 861-E

=1
=1

[ =]
[o]

REMOTE

—_—

PHASE 1 - GIRGUIT 1
UNSWITCHED

OFF
| LOCAL

INPUT 240 50/60 HZ
3 PHASE 5 WIRE 15A/PHASE

MAIN POWER

ALL OUTLETS

MAXIMUM CURRENT AT 240 VOLTS

ARE

12 AMPS/QUTLET- 15 AMPS/PHASE

SWITCHED

<:>

~— PHASE { r'— PHASE

{@GJ

£,

£
®

PHASE 3

)
L_cmcun 2 =

SIS (&S]

A— CIRCUIT1

CIRCUIT 2 —-—‘

CIRCUIT1

CIRCUIT 2 —

CP-1730

Figure 4-11

861-D/E Power Control Panels

4-17

4.3.6

Type 861-D Circuit Description
Figure 4-12 is an 861-D simplified circuit schematic. The 861-D is a 90-132 Vac, 47-63 Hz, 3-phase
power controller.

UNSWITCHED
OUTLETS

AC INPUT

CK1

CcK 2

77‘7

cB2

NEMA

a1
CK2

TWE LR
T 0

ng\_.l_fvvv\
2

M
Y'Y

Y YL

ce7

conTacToR!

EE-A

|K1

[

”l'_ I

(

cB4

cB5

(C20a(C

(20a(C

(Cz0a

|
1:
L

ERESE:

-y

—/—I_
— L L1l
GND/—L—‘""——T—‘I:EFLJ I
N

(20a

N
—

cB6

[

: |
coiL I

L——__
= J

T gszcgfg
|5

]

Llcm | |ces3

(" (208(" (Co0m

L_—_
cky
PILOT

CONTROL

2 I

—

=
Ty

LOCAL

AL—_———
.

ON}

REMOTE

OFF

§ON

]

_~L>

Lole

)—p

<:t?._ _J 2 :>

N
7/

> 1

BOARD

Co2-1732

Figure 4-12

861-D Simplified Circuit Schematic

Power is applied to the terminal block mounted on the power line filter via a 15-foot line cord. This

filter contains 0.03 uF capacitors which connect between neutral and each of the 3-phase lines, and
between neutral and ground. Also contained in the filter are nine chokes, connected in series with each
of the four lines and ground. The capacitors provide low impedance paths to ground for high frequency line components. The chokes present a high impedance to these components. If 90-132 Vac
exists between phase 1 and neutral, I1 lights. If 90-132 Vac is present between phase 2 and neutral, 12
lights. Similarly, if 90-132 Vac is present between phase 3 and neutral, I3 lights.

4-18

All three lines are connected to 30 A elements in circuit breaker CB7. All loads connected to the power
controller (both switched and unswitched) are controlled by individual 20 A circuit breakers, CB1
through CB6.

If the current through any of the lines exceeds 20 A, the respective circuit breaker trips, removing
power from the loads. Phase 1, circuit 1 outlets connect across the main circuit breaker output. These
outlets are energized (90-132 Vac) whenever the circuit breaker is closed. All outlet lines from CB7 are
connected to a normally open contact on contactor K 1. The field coil associated with K1 is energized
by 156-229 Vac from the output of CB7 if a relay (K1*) on the pilot control board is closed (see
Paragraph 4.3.8 for a description of the pilot control board).

When K1 is closed, 90-132 Vac is applied across phase 1, circuit 2, phase 2, circuits 1 and 2, and phase
3, circuits 1 and 2. The three 0.1 uF capacitors (Cl and C2), connected across the lines at the relay,
reduce the amplitude of voltage spikes at the output of the controller when switching inductive loads,
thereby preventing interference to nearby electronic data processing equipment.
4.3.7

Type 861-E Circuit Description

Figure 4-12 is a simplified circuit schematic of the 861-E, the 180-264 Vac (312-457 Vac phase to
phase), 47-63 Hz, 3-phase version of the power controller.

Power is applied to the terminal block mounted on the power line filter. This filter contains 0.03 uF
capacitors which connect between neutral and each of the 3-phase 180-264 Vac lines, and between
neutral and ground. Also contained in the filter are nine chokes, connected in series with each of the
four lines and ground. The capacitors provide low impedance paths to ground for high frequency line
components. The chokes present a high impedance to these components. If 180-264 Vac is present
across each line at the output of the line filter, I1, I2, and I3 light. Each side of the line connectsto a 15
A element of circuit breaker CB1. All loads connected to the power controller (both switched and
unswitched) are controlled by CB1. If the current through either line exceeds 15 A, CBI trips, removing power from the load. Phase 1, circuit 1 connects across the output of CB1. These outlets are
energized (180-264 Vac) whenever the circuit breaker is closed. Each output line from CB1 connects to

a normally-open contact on contactor K1. The field coil associated with K1 is energized byis180-264
Vac from the output of CBI if a relay (K1*) on the pilot control board (Paragraph 4.3.8) closed.
When K1 is closed, 180-264 Vac is applied across outlets phase 1, circuit 2, phase 2, circuits 1 and 2,
and phase 3, circuit 1 and 2. The 0.1 uF capacitors (C1 and C2), connected across the lines at the relay,
reduce the amplitude of voltage spikes at the output of the control when switching inductive loads,
thereby preventing interference to nearby electronic data processing equipment.
4.3.8

Pilot Control Board Circuit Description

Figures 4-12 and 4-13 show the pilot control board simplified circuit schematic. The pilot control
board contains the circuitry which allows remote turn-on and emergency turn-off of the switched
power outlets in both 861 power controller versions. These functions are accomplished by controlling
the voltage applied to the field coil of relay K1 in the 861 power controller.

Basically, the circuit consists of a full-wave rectifier loaded by the center-tapped field coil of a relay.
Three control lines connect to the board. Pin 3 connects to the center-tapped secondary of the fullwave rectifier transformer. (The center tap is returned to chassis ground through a plug connection.)
Pin 2 is the disable (emergency shutdown) line from the signal bus, pin 1 is the enable (power request)
line from the signal bus. Two additional lines (from the thermal switch) are connected to the lines
associated with pins 3 and 2.

4-19

UNSWITCHED

OUTLETS
21

cK2

CK 1

CK 2

D!
|
o | g2
23

GND

FONeE FiLter
. — -‘|

|
l

SAMA

___T_m

_._I__m
_L JS

|~~~
T

¢8 1

fCONTACTORY

——j—

[l
S I

—

< &

I
!

T/fi B

'h—l

‘Il
fi{:l’_

L. _____ _j

77@77

coiL

'
I

:LC2

OUTLETS

IT T
I

— e

3
cK1

PILOT CONTROL BOARD

b}
P

03
cK2

| | —';

K{ % L

1sc\>/«|'r(:mzt>

J_C1_]_

p—

__._<3

)'L+

LOCAL

REMOTE |

Figure 4-13

¥03

)

CP-1733

861-E Simplified Circuit Schematic

When the LOCAL/OFF/REMOTE switch is in the REMOTE position
and pins 3 and 1 are connected, current flows through the lower portion of the center-tapped
relay field coil to the full-wave
rectifier transformer. This action closes the relay on the pilot control
board and causes an energizing
potential to be applied across the field coil associated with
contactor K1 in the power controller,
thereby energizing the controlled outlets. When pins 3 and 2 are connecte
d (emergency shutdown is
true), current flows through the lower and upper halves of the center-ta
pped field coil in different
directions before returning to the power supply transformer. The resultant
current through the field

coil is less than that required for holding the relay closed. Therefore, energizin
at contactor K1 and power is removed from controlled outlets.

g potential is not present

Diode D2 provides a current path in the lower section of the coil
to prevent closing the relay in
instances where pins 3 and 2 are connected, but no connection exists
between pins 1 and 3.

4-20

Closing T1 (the thermal switch) performs the same function as emergency shutdown (connects pins 2
and 3 together). This switch is exposed to the ambient air surrounding the power controller. Temperatures above 71° C (160° F) close the switch (disabling the switched outlets). The switch resets automatically when the temperature drops below 49° C (120° F).

Placing the LOCAL/OFF/REMOTE switch in the LOCAL position provides a connection between
pin 3 and the lower portion of the coil to energize relay K1, regardless of the state of the power request
line on the signal bus. With MJ11 memories, this switch position is normally used for maintenance
purposes; operations on the pilot control board are exactly the same for situations where a connection
is provided between pins 3 and 1 of the signal bus connector due to closing of a circuit in an external
device. MK 11 memories require that this switch be in the LOCAL position. A connection between
pins 2 and 3 disables the switched outlets, regardless of the position of the LOCAL/OFF/REMOTE
switch.

4.3.9 AC Power Distribution
AC power distribution for both the processor and memory cabinets is depicted in Figure 4-2. In the

processor cabinet the upper H7420 power supply is connected to a phase 1, circuit 2 outlet on the 861D/E power controller (Figure 4-14). The lower H7420 uses a phase 2, circuit 1 outlet; those peripheral
devices installed in the processor cabinet use phase 3 power. (These are all switched outlets.) The two
processor cabinet fans (located at the top of the cabinet) obtain their power from an unswitched outlet
on the 861 front panel. The ac power cord for the fans is routed through a terminal block that is
attached to the inside surface of the top left part of the cabinet frame. The electrical hook-up at the
terminal block is the same for both 115 and 230 Vac systems (Figure 4-14).

Several other devices in the processor cabinet use ac power from the 861-D/E power control. They are
the transformer and regulator fans in both H7420s, the elapsed time meter (located at the rear of the
cabinet), and the upper and lower processor box logic fans (Figure 4-2). The source of 115 Vac power
for these devices is two terminal blocks (TB1) located in the upper and lower H7420s. The electrical
jumper configuration at these terminal blocks is determined by the input voltage to the H7420: 115 Vac
from an 861-D or 230 Vac from an 861-E (see note on Figure 4-14).
In the memory cabinet, the memory power supply obtains its power from a phase 3 switched outlet on
the 861-D/E. Additional memory frames use phase 1 and phase 2 switched power from the 861 (Figure
4-8). Several connections in the memory (at two terminal blocks in the transformer assembly) provide
115 Vac to internal cooling fans (drawing E-AD-7010694-0-0).
The distribution of the 20-30 Vac output of the H7420 and MJ11 transformer secondaries is described
in Paragraphs 4.4.4 (for the H7420), and 4.4.7 (for the MJ11) and 4.4.7 (for the MK11).
44

DC POWER, H7420, MJ11, and MK11 POWER SUPPLIES
Switched ac power from the 861-D/E power controls in the processor and memory cabinets is routed
to the H7420 and memory power supplies that generate the required dc voltage for the system (Figure
4-2, 4-3, 4-4, and 4-5).
4.4.1
DC Power Distribution
The outputs from the H7420 and MJ11 power supplies are channeled through three wire harnesses to
the processor console and the processor and memory backplanes. AC power to the logic fans, to the

elapsed time meter, and to the MJ11 voltage regulators is also sent through two of these harnesses
(Figure 4-2).

4-21

BLK

RED
ORN

D-CS-H7420-0+1

REFER TO CIRCUIT

861-E: NOT SUPPLIED

SCHEMATIC

WHT

D-CS-861-D-1

D-CS-861-E-1

GRN/YEL

i CONNECT TO SWITGHED
PHASE1

CIRCUIT2

ON 861
POWER CONTROL

SWITCHED AND
UNSWITCHED AC
OUTLETS ARE

47-63Hz
3 PHASE
120° DISPLACED

| 701105

POWER

L RS T I S 4
P/0
P8

[7]

CIRCUIT 1

THERM 2

3|3

VERSION | VOLTAGE | INSERT TBY JUMPERS | CB!

90-132VAC | 2 =6 , 4§ =——e8

204

180-264VAC|

4 «— 6

15 A

90-132VAC|

20
A

180-264VAC|

4 =— 6

=+ 6 ,4<+—>
8

15 A

FANS

REFER TO D-CS-H7420-0-1

§D1

CONNECT TO SW!TCHED
PHASE

CIRCUIT 1

POWER

CONTROL

ON 861
N

I
H7420 VERSIONS

—Dpss

LOWER H7420 POWER SUPPLY (See note)!

|
NOTE:

METER

POWER CONTROL

717

861

Pio

5|5 ——A I—l

— ) TIME

TO Jt ON MEMORY CABINET

ELAPSED

.;’g.-

REGULATOR

GROUNDED
THERM 1

SHOWN

|
|

6|6

230V

WINDINGS

DRAWING D-1C-11/70-0-2

J24

KEY
2 (GND)

Lock |

OFF

CAE{'NET

UNSWITCHED

120° DISPLACED

KEY 1 (ENABLE)

FAN HOOK UP 115V

CONNECT TO
PHASE1

N I

SWITCH

423

SECONDARY
ON

CABINET

861-E:180-264 VAC
47-63 Hz
3 PHASE

|
fl

KEY

rer———---

1 P/ 0 I PART OF POWERI
r{f‘
HARNESS

]

P/0
CONSOLE

¥ 02

|
N
—

r—————j 0w ~N O [ R T ¥ B V] -

*864-D: 50-132 VAC

INDICATED BY PANEL
MARKINGS

|||_. — e e e ————

REFER TO

—5F

LINE PLUG
861-D:NEMA L21-30P

UPPER H7420 POWER SUPPLY (SEE NOTE)

861 POWER
CONTROL

SECONDARY

WINDINGS

SHOWN

DRAWING D-I1C-11/70-0-2

P/0

Jea P16

515

6 |6

313

717
[

c—

! ? LOGIC
2 j FANS
TO

]

REGULATOR

FANS
1-3321

Figure 4-14

AC Power Connections (Processor Cabinet)

4-22

Power Distribution Cable Harnesses

4.4.2

Three power distribution harnesses are used in the PDP-11/70: one in the processor cabinet, 7011051
(Figure 4-15) and two in the memory cabinet, 5010580 and 5010581 (Figure 4-16). In general, the
power harness connectors are assigned a number with a “P” prefix; e.g., P1, P2, etc., whereas the
connectors attached to the hardware (regulators, backplanes, etc.) have a “J” prefix. Several exceptions to this can be noted on Figure 4-15. These harnesses contain several different types of Mate-NLok connections (both male and female). They are shown in detail on drawings D-1A-7010580-0-0, D1A-7010581-0-0 and D-IA-7011051-0-0. Figures 4-17, 4-18, and 4-19 are photographs of the processor
and memory cabinets that show the harnesses in relation to the power supplies.

The 7010580 power distribution harness interconnects the transformer assembly, regulators, and the
memory backplane. The harness routes 30 Vac to the regulators and regulated dc voltage to the memory backplane.

The 7010581 harness interconnects the transformer assembly, the 5411086-YA power line monitor
board, and the memory backplane. The harness routes 30 Vac to the power line monitor board, and
power fail signals (AC LO and DC LO) to the memory backplane.
MJ11 Backplane Power Distribution

4.4.3

Processor cabinet power is applied to the processor backplane via the power harness to ten connectors

(Figure 4-15). Six are voltage inputs (P2 through P7) and four are ground connections (P25 through
P28). Ground is established through three connectors (from P25, P27, and P28) fastened to the backplane with the wire harness cable clamps. A separate plug (P1) on te harness (Figure 4-20) is the
power and signal connection to the processor console (J4). An additional plug (P8) provides a connection for power to the five upper and four lower processor mounting box fans. P8 also connects the
thermal switch in the mounting box to the 861 power control. The processor backplane row and slot
assignments are shown in Figure 4-20; backplane connectors and pins are shown in Figure 4-21. Table
4-5 lists all the processor cabinet power and signal connections. These connections are also shown on
drawing D-1C-11/70-0-2.

CONNECTED
TO UPPER H7420
REGULATORS

TO LOGIC FANS AND

THERMAL SWITCH

(KEY SWITCH
8 +5V)

P
TO CONSOLE

| &1

&\
e

".'I'I-.-r li( \“

. P28

per

p26

‘

BULK SUPPLY

CONNECTED TO

REGULATORS

LOWER H7426

P14

£ P16

)
e

PROCESSOR BACKPLANE

FROM

THERMAL SWITCH

Ped

GROUND
BACKPLANE
INPUTS

P13

‘% >

CONNECTED TO

UPPER H7420

GROUND CONNECTIONS TO
=

P12

Jfi

’

/./"-'/A
S

n\\‘\\“
!

BACKPLANE
VOLTAGE INPUTS

—

'E,,- P11

TO 861

POWER CONTROL

p24 (] i

‘\Q

Pe2y
-

23
FROM CONSOLE
KEY SWITCH

——Z

P21%

-’I;'?MELMAE'?EEg
—

034
P35

CONNECTED TO
LOWER H7420
BULK

SUPPLY

1-3314

Figure 4-15

Power Distribution Cable Harness

(Processor Cabinet) 7011051

4-23

20-30
CONNECTED TO
H754 REGULATOR

JUMPERCONNECTED

VAC

INPUTS FROM
TRANSFORMER
SECONDARIES

TO AC
POWER CONTROL
(5410993)

CONNECTED TO
H744 REGULATOR 2

CONNECTED
TO H744 —
REGULATOR 4

P16

P13

CONNECTED

f——

TO H754
REGULATOR
1

+5V,-5Vv &
+20V TO
MEMORY
BACKPLANE

MEMORY
BACKPLANE
GROUND

BACKPLANE

+5v,-5V

GROUND
DISTRIBUTION

+20V TO
MEMOR
Y

BACKPLANE
11-331

Power Harness Assembly 5010580

VAC

FROM

SECONDARY

CONNECTED

TO POWER
==
LINE MONITOR \_E'j
(5411086-YA)

INPUT

~ TRANSFORMER

=
P6

20-30

P19

CONNECTED
TO

MEMORY

BACKPLANE

H-33t12

AC LO DC LO Wire Harness Assembly 5010581

Figure 4-16

Power Distribution Cable Harnesses

(Memory Cabinet)

4-24

UPPER
H7420
POWER

DISTRIBUTION

CABLE HARNESS
7011051

ELAPSED

TIME
METER

LOWER

H7420

7456-19

Figure 4-17

Processor Cabinet (Processor Mounting
Box Extended)

4-25

POWER DISTRIBUTION
> CABLE HARNESS
7011051

UPPER
H7420

PROCESSOR
BACKPLANE

LOWER

H7420

861
-

POWER
CONTROL

7545-11

Figure 4-18

Processor Mounting Box

4-26

MEMORY

BACKPLANE

GROUND

CONNECTION

TO P20

AO1A1

POWER DISTRIBUTION (7010580}

& AC/DC LOW (7010581) CABLE

HARNESSES

M1
POWER

SUPPLY

7545-3

Figure 4-19

Memory Cabinet Power Supply (Bottom View)

4-27

SMALL
MISC

MEMORY

CACHE

PROCESSOR

MGT.

MEMORY

PIN ASSIGNMENTS

PERIPHERAL
CONTROLLERS

MAP

(@]

~O J8

TIGIBN 1§D I|E

RS IBW WY

£06SW VSEW

SHISWN WAV
2- 9cI8W 28N

CENTRAL

]

oTM~

SLOTS

41 42 43 44
30 31 32 33 3435 36 37 383940
27 28 29 6
1 2345 67 8 9 101112 1314151617 18 19 2021222324 252

MATE-N-LOCK CONNECTORS J25-J28

11-338

REGULATORS

NOTES:

1 Slot 44 A,B could be UNIBUS out

if there are other UNIBUS devices.
2.FP-11B contains the foilowing modules:

3. Modules shown are used in KB#1-C.
KB1f{-B uses M8133 instead of mM8123
and M8138 instead of MB138-YA.

FRH M8114
FRL MB8115

FRM M8112
M8113

FXP

Figure 4-20 KB11-B,C Processor Backplane Slot
and Row Assignments (Pin Side View)
4-28

CONSOLE

Pila|7|e]s]a]3]2]1]

GND

{SLOT D)

SLOT

SLOT A
Note 1

SLOT C

H744

HT44

H744

+5VDC

+5vDC

REGULATOR | | REGULATOR

SLOT

Sfiéa
P

CONSOLE +5V

ENABLE | OTEaL

SLOT H

HT44

SLOT

+5VDC
+5VDC
REGULATOR | | REGULATOR

REGULATOR

SLOT D

HT44

H744

+5vDC
REGULATOR

+5VDC
REGULATOR

+5VDC

H744

SLOT

REGULATOR

ACLO
1

LINE ‘CLK

+8v MAlNT:\\

DCLO
1

P2l817[6

+15v

DCLO

+15v2

‘

N\
N

ACLO

FOIF1 A18E1

DBIR1,

> LAB1BY
~

A,O1A1—\

MAIN
DCLO

BUS

\~
LTC ;

+8V

\
\
\

+1 5V

E13A1\

K ——

)

-5V
A25B2

(FP OPTION)

ININTNZNZN

2N/,
OO

Do R

®ecccoee

SLOT C

NN\

NINT O«

NN
7oQi)
O

(XOTO

Bus/

BUS
ACLO.B44F1

DCLO

B44F2

MAIN

DCLO.~
A1BE1

-7

v
-

ral

;z/floof’

/////////

000000060

fio eooe

0.0.0.0,
0000200

O)
OO

P26

"G
)¢

PINSIDE VIEW
5411337

N/N\ZNY,

)
-

o 3o X

PN
e
\,

4—’4——6—9 —+——10—15——+-16—18——|
SLOT 8
REGULATOR (Notfe 7

’

6.% [ X}

Note SLOT A REGULATOR

COXOKOKOXOKS

DCLO 2

!
[}

BUS
DCLO

FO1F2

I’

ACLO

DCLO Y

] relrTsTsTe 5[] Prlelv]els[4]s]2]1]
[sTaTs[e] P3[}£]77‘ 65[a3]2] f] P4[%1;7]6| ; [a]3]2]1]psGITeeETel
N\

SLOT __ | CAYNN
TM S
o_s
:
NU MBERS

SLOT J
REGULATOR

2428
SLOT K

SLOT L

O OTMUN OO
000
(¥ -.o

s‘

5411339

NOTES:

%)
3.

Used only if FP11 option is

-15 Vv, DCLO 2, and DCLO X

installed.

are from lower H7420.

Electrical Connection.

+8V, +15 V, ACLO 1, DCLO Y,

P25 through P28 are ground
connections. (Refer to D-1C-11/70-0-2)

Shaded etch connections are

on connector side.

ACLO 4, LINE CLOCK, and

DCLO 1 are from upper H7420.
Slot B regulator provides power
to slots 1, 6-9.
11-3201

Figure 4-21i

Processor Backplane

Connectors and Pins

4-29

Table 4-5

Processor Cabinet Voltage/Signal Connections
(Refer to Figures 4-19 and 4-20)

Voltage /

H744

Regulator

Plug-Pin-

Regulator

Backplane

Plug-Pin

Modules

+35V

Siot A
Slot B
Siot C
Slot D
Slot H
Slot J

P9-2, 5
P11-2, 5
Pi2-Z, 5
P13-2, 5
P17-2, 5
P18-2, 5

P2-5, 0
P2-1, 2
P3-5, 06
P7-6, 8
P4-1, 2
P44, 5

Siots 2-5
Slots 1, 6-9
Siots 10-i5
Slots 36-44
Slots 20-22
Siots 16-18

Signal

Ground

Slot K
Slot L

P19-2, 5
P20-2, 5

Slot A

P9-3, 4

Slot B

Slot C

P11-3, 4
P12-3, 4

P5-1, 2
P6-5, 6

P28-1, 2

All ground

P28-5, 6

are common

Backplane

Processor/

P1-7; P27-4
P25-1, 2
P27-1, 2
P25-3, 4
P25-5, 6

H7420

Power Supply
Plug-Pin

Plug-Pin

Upper
Lower

P15-5
P22-2, 3

P28-8
P26-5

Logic Ground

Upper
Lower

P15-7
P22-7

P26-1
P26-2

+15V

Upper

P15-3

P3-2, 3

-15V

Lower

P22-4

P5-5,6

Power Supply

Slots 24-28
Slots 29-35

connections

P13-3, 4
P17-3, 4
P18-3, 4
P19-3, 4
P20-3, 4

Signal

Also to processor
console (P1-8) via
P4-6

P28-3, 4

Slot D
Slot H
Slot J
Slot K
Slot L

Voltage/

Processor/

Modules

Slots 40-44

Slots 2, 17, 25-27,

29-31, 33-35, 3744

+3V

Upper

P15-1

P2-8

Siot

Line Clock (LTC)|

Upper

P15-11

P2-7

Slot 1 (KW11)

Bus ACLOL

Upper

P15-8

P3-7

Refer to

Lower

P22-10

4-30

P3-7

(CP

Maintenance
card)

Figure 4-37

for complete AC
LO, DC LO
Circuit

Table 4-5

Processor Cabinet Voltge/Signal Connections (Cont)

Voltage/

H7420

Power Supply

Backplane

Processor/

Signal

Power Supply

Plug-Pin

Modules

BUSACLOL

Upper

P15-10

P7-7

(Cont)

Lower

P22-8

P7-7

Bus DCLOL

Upper
Lower

P15-9
P22-12

P6-1
P4-3

Main DCLOL

Upper
Lower

P22-9

Voltage/

H7420

P15-12

Power Supply

P3-8

P7-4

Regulator

Signal

Power Supply

Plug-Pin

Remarks

20-30 Vac

Upper

P10-1, 2

P14-1, 2
P14-7, 8
P10-8, 10

P9-6, 7
P11-6, 7
P12-6, 7
P13-6, 7

Regulator A
Regulator B
Regulator C
Regulator D

P21-1, 2
P16-8, 10
P16-1, 2

P18-6, 7
P19-6, 7
P20-6, 7

Regulator J
Regulator K
Regulator L

Lower

P21-7, 8

P17-6, 7

Regulator H

Voltage/
Signal

H7420
Power Supply

Power Supply
Plug-Pin

H7420 Fan
Connections

Remarks

115 Vac

Upper

P10-3, 7

J10, J11

Upper

J8, J9
J6, J7

Lower

P16-3, 7

J10, J11

J8, J9

J6, J7

Voltage/
Signal

Fan 2
Upper
Fan 3
Upper
Fan 4
Lower

Fan 2
Lower
Fan 3
Lower
Fan 4

H7420,

H7420,
H7420,

H7420,

H7420
Power Supply

Power Supply
Plug-Pin

Processor
Cabinet Plug

Upper

P10-5, 6

P34, P35

Elapsed
Meter

Lower

P16-5, 6

P8-1, 2

9Processor

Remarks
Time

mounting box
logic fans

4-31

Two plugs on the processor power harness, Pv3 and P24, connect the console ON /OFF switch (via P1)
and the thermal switch (via P8) to the 861 power control (Figure 4-14).

Fourteen of the harness connectors are attached to the upper and lower H7420s. Seven (P9 through
P15) go to the upper H7420 and seven (P16 through P22) go to the lower H7420. Figure 4-3 shows how

the processor power harness plugs connect the backplane to the H7420s. The two remaining conaectors on this harness, P34 and P35, are used to apply ac power to the elapsed time meter (Figure

4-17).

Memory cabinet power is distributed to the memory backplane via the power harness. The harness
contains nine connectors (Figure 4-16). Two connectors (P18 and P21) apply dc voltage to the backplane (Table 4-6). A third connector (P20) is for ground distribution that originates at a chassis ground
connection on the backplane (Figure 4-19). At the MJ11 power supply, four connectors (P13 through
P16) are attached to the voltage regulators and one connector (J1) routes the ac input from the transformer secondary to the four regulators. The last connector on the harness is P3, which is functionally
separate from the others. P3 is attached to the ac power control board in the MJ11 and contains a
single shorting loop. This loop maintains the MJi1 in the ON mode during normal operation (Figure
4-2 and drawing E-AD-7010694-0-0).

Table 4-6

MJ11 Memory Cabinet Voltage/Signal Connections

Voltage/Signal

Wire Color

+5V

Red

+20V

(Refer to Figure 4-21)

Regulator

Backplane

Plug Pin

H744 (No. 2)

P14-2,5

P16-2,5

P21-5,6,7,8

Orange

H754 (No. 3)

P15-5

P21-3,4

-5V

Brown

H754 (No. 3)

P15-3

Ground

Black

H754 (No. 1)

DC LO
ACLO

H744 (No. 4)

H754 (No. 1)

P13-5

P18-1,2,3,4
P18-5,6

P21-1,2

P13-3

P18-7,8

H744 (No. 2)
H754 (No. 3)
H744 (No. 4)
5411086-YA

P14-3,4
P15-2
P16-3,4
P6-4,11

P13-2

(Note) P20-3

Violet

5411086-YA

P6-1,2

P19-6,7

Yellow

5411086-YA

P6-3, 8

P19-8

H754 (No. 1)

P20-4,5
P20-7
P20-6,8
P19-4,5

NOTE: Ground connections on J20 and J19 (layer 3) are common to each other. P20-2 is connected to
chassis ground on the backplane (Figure 4-19).

4-32

A second wire harness is routed adjacent to the memory power harness in the MJ11. This is the ac/dc
low wire harness (Figure 4-16). It is used to convey AC LO and DC LO power fail signals from the
5411086-Y
A low voltage detection circuit to the memory backplane, and ac power from the transformer to the 5411086-Y
A. Three connectors, P6, J2, and P12, are used for these functions.
Figure 4-22 depicts the MJ11 power supply and memory backplane connections made with the two
wire harnesses (7010850 and 7010851) just described. In the drawing the four backplane layers are

separated to show where each signal/voltage is applied. Layer four is the one observed when the
backplane is viewed from the bottom (pin side). Some jack pins are common to each other due to an
electrical connection on the associated backplane layer. Consequently, a voltage or signal may be
present at more than one jack pin even though it is sent to just one plug pin. For example, -5 V is sent
to P21-1 from regulator 3. However, -5 V is present at both J21-1 and J21-2 because of an etch
connection on layer one between these two pins. Figure 4-23 is a cross-sectional view of this part of the
backplane. Table 4-6 lists the backplane pins that are common to a particular voltage or signal. Pin
AOlA1, identified on each layer (Figure 4-22) to illustrate exactly how the four layers are overlayed, is
in the lower right corner of the backplane when the memory drawer is in the raised (maintenance)
position (Figure 4-19).
Drawing E-UA-MJ11-0-0 is a more comprehensive view of the backplane wire connections.
4.4.4 Processor Cabinet DC Power Supply (H7420)
The upper and lower H7420 power supplies in the processor cabinet provide the processor with the
required dc voltage and low voltage signals. Each H7420 consists of a multiple output transformer, a
power line monitor, 15 V regulator, and cooling for up to five H744 +5 V power supply modules.
Figure 4-24 is a simplified schematic drawing of the two H7420s in the processor cabinet (only the
unique parts of the lower H7420 are shown) and their connections to the processor cabinet, processor
console, and processor backplane.

Figure 4-25 is a photograph of an H7420 with four regulators installed. In Figure 4-26, all the regulators have been removed and the top cover and the PC mounting board bracket have been detached to
show the interior of the H7420. A front view of the power supply is shown in Figure 4-27.

Four versions of the H7420 are made: A, B, E, and F. The major differences are listed in Table 4-7.
The 115/230 Vac power input to the H7420 is through a circuit breaker (CB1) and a terminal block
(TBI1). (Refer to this part of the power supply on Figure 4-14). In the A and E versions, CB1is a 20 A
circuit breaker; the B and F versions use a 15 A circuit breaker. TB1 contains eight double terminals;
adjacent terminal pairs are common as shown in Figure 4-28. In addition, jumpers are installed (Table
4-7) to provide 115 Vac outputs with either a 115 Vac or a 230 Vac input. Simplified circuit drawings of
the two jumper-transformer configurations are shown on Figure 4-24. Also connected to TB1 are two
capacitor-varistor assemblies (C1 and D1, C2 and D2) that function as input surge limiters.

The 115 Vac outputs from TB1 are connected to the two transformer primary windings, the regulator,
and processor logic cooling fans, the elapsed time meter and the power indicator light (Figures 4-17,
4-26, and 4-27). The externally used outputs and the 115 Vac for the regulator fans are routed through
J2 on the H7420 box (Figure 4-25).

The transformer secondary windings are connected to J2 (15-pin Mate-N-Lok) and J3 (9-pin Mate-NLok) on the H7420 box, and J5 (2-pin Mate-N-Lok). The output to J5 is the only one that is fused.
These transformer outputs are 20-30 Vac (26 Vac is the nominal voltage). The two wires from P5 (J5)
are routed to J1 (15 pin Molex right angle edge connector) on the 5411086 board (Figure 4-26).

4-33

VAC

P16
—

(4)

(P16)

|15V

—
6 e

[
1

]

P/J15
T,

4
5

GND (P20)

CHASSIS GND(S—=— 2
(P14-4)

«=——

(P14-3) «——

(2)

L-AC LO

(P16-4) «—H 8

{P15-2) =

SggstE-YRA 2 1« GND (P19)
[F7]

GND(P19)

o,
o

75| 30VAC

7 JSRD

]

Note 3

1
2|

3|« GND_(P20)

(P&-4)

GND (P20)

|_t5

& le

[°
6

G +5V

> 1 30vac (p1)
__7___‘_J

(3)

_GND

GND

—1

DC LO

s
8

AC LO

e
{2}

—

P/J18

(2)

|15V

—(1)

P/I13
KN

5 leGND (P20)

—g—-‘

{3)

REGULATOR [ 5

GND

P/J19

P/Ji4
2

L(3)

l——“(3)
L (3)
(3)
l'_m

CONTROL | g

-5V

—

+20V

]

| 4

+20V

6 |
8

‘-—> (2

—

(P16-3)e—— 6

Note1
(1)

—1_GND

|_AC LO

[5|
>

—|_GND

| ]

GND

(P13-2)
—] [—13 _GND
[«SND
;

Note 4

1
"
oc Lo

+20/-5V

[
)

REGULATOR
(1

LAYER

P/420

| 6 |
.

HT754

+20V

8 |2V

5 fi:}sow&c (P1)

(2}

LAYER 2

-5V

7
Sy
|
|

4
—1 +20vV

| 7]

HT44

LAYER 3

' 6 |

3
=3V
—

REGULATOR | 5

CARD

LAYER 4 (Note 2)

(3}

(P13)

Pry21

}3OVAC (P1)

H754

(P14)

(P20}

I
—

|7 e

+20/-5V

(P15)

1q-GND_(P20)

2 e SN0

REGULATOR [ g

Note 3

+5V

0!,..,....

H744

P/J’FBI?IGISPMZI']

]
7

pry =

}3ovac P1)

—

ra—J

PINSIDE

NOTES:

1.
2.

Numbers denote backplane layer

Power transformer secendary.

connected.

Harness 7010581 connects P6

Layer 4 is the pinside layer.

with P2 and P18.

All other

wires are contained in harness

7010580.

Figure 4-22

Memory Backplane Connectors and Pins

4-34

TK-1791

PINS

BACKPANEL

—_
>\

INSULATING
LAYERS

%\\LAYER 2
(+5V)

LAYER 2
(+20V)

J21-2

LAYER 3

(PLATED THROUGH

{GROUND)

TO LAYER 1)

LAYER 1 (-5V)
| J21-1

(PLATED THROUGH TO LAYER 1)
11-3293

Figure 4-23

Memory Backplane Cross Section

Table 4-7

Version
A
B
E
F

Version

A
B
E
F

H7420 Versions
TB1 Jumper

Apparent input

Voltage

CB1

Connections

Power (kV
A max)

90-132 Vac
180-264 Vac
90-132 Vac
180-264 Vac

20A
15A
20A
15A

2-6,4-8
4-6
2-6,4-8
4-6

1.44
1.68
1.44
1.44

Transformer
Assy - DEC No.

Max Transformer
Output Load*

Max No.
Regulators

7011211
7011211
7010814
7010814

1220 VA
1220 VA
1020 VA
1020 VA

5
5
4
4

4-35

115 VAC

SURGE

TRANSFORMER

]

PRIMARIES

CcB1

TRANSFORMER| 20-30

SECONDARIES | vac

3,4 1,2

1157230 VAC

{NOTE 2)

JzePa

H744

REG[;‘,;NTOR

P13 H

20-30 VAC

H744

o—

|
]1

édg

—

P3j

P26

+5VTO P2

TO P28
GND

P11 H

H744

7011051
HARNESS

VAC

| !5 VAC

+5V TO P7
GND TO P P27
;' ~ '

l_ — e o—p ——

20-30

REGULATOR

PS5

+5V TO P3

P27
_

GND TO P8,P28

5411086

P12

REGULATOR
&

Ll_
v

power

}(NOTE 5)

REGULATOR

€1

+5v

INDICATOR

P35

REEL?LVATOR

ter

\AAAAAAAAAANS

LIMITER

IF?‘LPUUGT

POWER

H744

MONITOR

REGULATOR

LINE

—

METER

J10

ELTIMSEED

115 VAC

T81

—

VAC

+5V_TO P2 GND TO P28

——,

115 VAC
20-30 VAC

——

P10

| CONSOLE

——

20-30

R
o

MProcESsOR ~ |

115 VAC

IPROCESSOR CABINET

H7420

UPPER

+5V
c

J4 P15

TB1-T1 SIMPLIFIED CIRCUITS
_

[COWER H7420 REGULATORS & FANS

115 VAC

% E

J2rm

P16

20- 30 VAC

115 VAC

5V TO P5 GND TO P25

(NOTE 3)

P19

3 %

TB1

230 vAC

20-30 VAC

15 VAC

20-30 VAC

H744
+5V

REGULATOR

FAN

on[l—“]

+5V 7O P6

H744

REGULATOR
L

l
l

+5y

20-30 VAC

GND TO P25

+5V TO P4
GND TO P25

»>-

115 VAC

P17

H744

L ATOR
REGU

H744

identical except for those unigue

parts shown (plugs, jacks,

regulators and wiring).

5V TO P4
GND TO P27

REGULATOR
J

The upper H7420 is shown in its
entirety. The lower H7420 is

Switched ¢1 to upper H7420,
switched ¢2 to lower H7420
!.AI

NOTES

+8 V, LINE CLOCK to P2; +15V
AC LO,DC LOtoP3; GND o
P28, P26; AC LO 10 P22, P7;
DC LO to P6.

GND to P10; -15V to P5; AC LO
to P16;DC LO to P4, P7.

»—

(NOTE &)

Included only with the floating

point processor (optional).
11-3320

Figure 4-24

H7420 Power Supply

4-36

H7420

~UPPER H7420 REGULATORS

—-LOWER H7420 REGULATORS
7301-2

Figure 4-25

H7420 Power Supply with Regulators

4-37

i
17
.

o
u

T
1
-1
-1

7A SLO BLO

FUSE F1

TRANSFORMER
T

R24

VOLTAGE
ADJUST

(+15V,-15v}
5411086
REGULATOR/
POWER LINE

5A PICO

MONITOR

FUSE F1

D20 ACOK LED

D21 DCOK LED

7301-3

Figure 4-26

H7420 Power Supply (PC Mounting Board Bracket
with Top Cover Removed)

4-38

FAN 1

cB1

POWER

INDICATOR

POWER CORD

& CONNECTOR ——
~—

7301-1

Figure 4-27

H7420 Power Supply, Front View

4-39

J2 and J3 are mated with P10 and P14 respectively, in the upper H7420 and P16 and P21 in the lower
H7420. The 20-30 Vac wires from these plugs are connected to the seven (or eight if the floating point
option is installed) H744 regulators in the H7420.
The 5411086 regulator and line monitor boards — one in each H7420 - furnish +8 V, -15V, and +15V
along with AC LO and DC LO power fail signals to the processor backplane (notes 1 and 2 on Figure
4-23). These outputs are through two 12-pin Mate-N-Lok connectors on the H7420 boxes: J4 /P15 on
the upper H7420, and J4 /P22 on the lower H7420. The 5411086, including the AC LO and DC LO
circuits, is described in Paragraph 4.4.6.1.
Four 4-inch, sleeve bearing fans provide air flow to cool each H7420. One is mounted above the
transformer assembly and three are mounted above the H744 regulators (Figures 4-24, 4-25, and 4-27).
The regulator fans receive 115 Vac power through six connectors, J6 through J11. Additional fan
specifications follow.
A minimum of seven H744, +5 V regulators are included in the processor cabinet power system: three
in the upper H7420 and four in the lower H7420. The upper H7420 regulators occupy slots B, C, and
D; the lower H7420 regulators use slots H, J, K, and L (Figures 4-24 and 4-25). An additional H744 is
installed in slot A of the upper H7420 if the optional floating point processor is included in the PDIP11/70. An 8-pin Mate-N-Lok connector on each regulator is used for both the 20-30 Vac input, and
the +5 V output to the processor backplane. The connectors for the upper H7420 regulators are P9
and P11 through P13. For the lower regulators, they are P17 through P20 (Table 4-5). These connectors, as well as the connectors on the backplane, and the associated wires, are contained in the
7011051 power harness (Figures 4-15, 4-17, and 4-24). The H744 regulator is described in Paragraph
4.4.6.2.
To convert a 240 Vac version H7420 to a 120 Vac version, or a 120 Vac version to a 240 Vac version, it

-th:—-

is necessary to change the following components:
Circuit breaker CBlI
The jumper configuration on TBI
The line cord and connector
The decal

Refer to Table 4-7 and Figures 4-28 and 4-65 for component sizes and locations. Illustrated Parts
Breakdown (IPB) EK-H7420-1P-001 lists the appropriate part numbers.
NOTE
The H7420 A and B versions can be converted to E
and F versions, but not vice versa. This is because the
E and F versions can supply 20-30 Vac to a maximum of four regulators; the A and B versions may
be equipped with up to five regulators.

4.4.5

H7420 Power Supply Specifications
Specifications for the H7420 are listed in Table 4-8. Reference should be made to engineering specification A-SP-H7420-0-2 for additional information.

4-40

115/230 VAC"
cz2z

[SHS IDHS) | |+

SHEOHD)
ADJACENT

TERMINALS

ARE COMMON

—®
{1

Rt il

r—J ’

J2 /P16

=2
)

(

LOGIC FANS
(LOWER H7420)

F2,F3
& ' Fa

~.l-—

T1
J2 /P10

ELAPSED TIME METER
{UPPER H7420 )

*For 115 VAC input jumper terminais
2-6 and 4—8. for

230 VAC inputs

jumper terminals 4-6.
11-3340

Figure 4-28

Terminal Block TBI

4-41

Table 4-8

H7420 Power Supply Specifications

Mechanical and Environmental
Dimensions

254 cmh X 5842 cm w X 20.32 cmd (10 in. h X
23 inw X 8 in d)

Weight

17.23 kg (38 Ib), approximately without regulators.
Regulators are 1.18 kg (4 1b), approximately

Cooling

4-inch sleeve bearing fans, DEC Part No. 1209403-01 (IMC No. WS2107F-110-01, ROTRON
No. CT 3 A2)
Temp Rating -28.9° C to +54.4° C (-20° F to
+130° F)
Power Requirements: 115 Vac 0.24 A
Air delivery: 18.87 1/s (40 ft3/min)

Ambient Temperature:

Operating: 0° to 60°C (32° to 140° F)
Storage: -40° to 70° C (-40° to 158° F)

Relative Humidity

10% to 90% (without condensation)

Altitude

3,048 meters (10,000 feet) max approximately

Electrical
Input Power
Voltage

Frequency
Current

90-132 Vac (H7420A, H7420E)
180-264 Vac (H7420B, H7420F)
47-63 Hz
12 A rms max at 120 Vac (A,E)

7 A rms max at 240 Vac (B)

6 A rms max at 240 Vac (F)

Inrush Current

260 A peak for 1/2 cycle at 120 Vac (A,E)
150 A peak for 1/2 cycle at 240 Vac (B,F)

Power (Apparent)

1.44 kVA max (A,E,F)
1.68 kVA max (B)

Conducted Noise
(Noise on ac line)
Transients

Single transient, without system degradation: 300

Vat02Ws

Single transient, survival: 1000 V at 2.5 W s max.
Average transient power survival: 0.5 W max.
CW Noise

10 KHz 3 MHz: 3 Vrms
3 MHz 50 MHz: 1 Vrms
500 MHz 1000 MHz: 0.5 Vrms

4-42

Table 4-8

H7420 Power Supply Specifications (Cont)

Conducted Noise (cont)

RF Field
Susceptibility

10 kHz-1000 MHz: 1 V/m

Ride-through Power

Upon power outage the voltage outputs are maintained within specified limits for 220 ms. Control
outputs are maintained within specified limits for
=5 ms. (Refer to Figure 4-36).

Output Power

General

Output is through three Mate-N-Lok connectors,
J2, J3, and J4, described in Paragraph 4.4.4 (Refer
to Table 4-7)

Pins
1,2,

Voltage
19-30 Vac

Max Load
375 VA

3,7
5,6
4
9,12
11,13
14, 15

90-132 Vac
90-132 Vac
0
19-30 Vac
Not used
Not used

N/A
4A
Chassis Gnd
375 VA except E, F

Pins
1-8

Voltage
19-30 Vac

Max Load
:
375 VA except Pins 3-6
for E, F (no connection)
Pins 1-2, 3-4 and 5-6, 7-8
are in parallel. Use only one
set at one time.

Not used

Pins
1
2,3
4-6

Voltage/Remarks
+8 V or -7 V if regulator used for -15 output
+15Vor-15V
Ground

8
9
10

if +15 V regulator; to pin 2 and 3
if =15 V regulator
ACLO1
DCLO1
ACLO?2
LTCL except when pins 2, 3, and 7 tied
together (-15 V regulator)

DCLO2

8, 10

AC LO/DC LO Grounds Connected to Pins 4, 5, and 6

5411086 Regulator - Refer to Paragraph 4.4.6.1

AC LO, DC LO Circuits - Refer to Paragraph 4.4.6.1

4-43

4.4.6 Memory Cabinet DC Power Supply (MJ11)
The MJ11 memory frame (Figure 4-29) is a 19 inch rack mountable expander box containing a 26-slot
backplane and a power system which provides the regulated voltages and power fail signals required
by the memory. There are two basic types of memory frame: the MJ11-AA, AC, BA, BC for 115 Vac,
and the MJ11-AB, AD, BB, BD for 230 Vac. The MJ11-AA, AC, BA, BC (115 Vac) memory frame
contains a 7009811-1 ac input box. The MJ11-AB, AD, BB, BD (230 Vac) contains a 7009811-2 ac
input box. Aside from the ac input box, the two types of memory frames are physically identical. The
memory frame can be converted from 115 Vac to 230 Vac operation or vice versa by installing the
proper ac input box.

FRONT OF

MEMORY FRAME\
TRANSFORMER
ASSEMBLY

REGULATOR

# 3

H754

REGULATOR # 4

H 744

MEMORY

BACKPLANE

REGULATOR # 2 /

H7 44

AC INPUT BOX

REGULATOR
# 1 / AIR VENTS
H754

Jz2

5410993 AC POWER CONTROL BOARD
AND 5411086 YA POWER MONITOR

INPUT BOX.

BOARD ARE INTERNAL TO THE AC

I-3028

Figure 4-29

MIJ11 Memory Frame Physical Layout

Table 4-9 lists the mechanical specifications of the memory frame.
The power supply is self-contained in its own chassis. It is secured to the main chassis with
six screws.
Two are special-purpose screws which function as hinges, enabling the power supply to be
swung away

from the main chassis during maintenance. The power supply contains four regulators, two fans, an ac
input box, a transformer assembly, a power control card, and two power harnesses. The regulators
are
self-contained DIGITAL standard modular types. Table 4-10 lists the physical characteristi
cs of the
power supply. Tables 4-11 and 4-12 list the input power electrical specifications for the MJ11-AA, AC,
BA, BC and MJ11-AB, AD, BB, BD memory frames.

4-44

Table 4-9

MJ11 Memory Frame Physical Characteristics

Dimensions

26.51 cmh X 4348 cmw X 63.5cm d
(1044 inh X 17.12inw X 25ind

Weight

40.82kg (90 1b)

Module Slots

Slide Extension
(Three-section slide)

68.58 cm (27 in) maximum

Slide Weight Capacity

68.04 kg (150 Ib) (frame fully extended)

Three-section slide
pivotal positions

Horizontal, 45 degrees and 90 degrees
(front panel facing up)

Fan air movement direction

Horizontally toward rear of memory frame

Cooling efficiency for both
fans at 90 Vac, 50 Hz

Temperature rise no greater than 10° C (18° F)
from inlet air temperature to exhaust air

Table 4-10

Power Supply Physical Characteristics

Item

Description

Power Supply Components

H744 Regulators (two)
H754 Regulators (two)

5411086-Y
A Power Line Monitor Board
7010014 Transformer Assembly
7009811-1 or -2 AC Input Box with
5410993 Power Control Board
7010580 Power Distribution Harness
7010581 Harness
1211714 Box Fans (two)
Fan Size

15.2 cm (6 in) Diam., 3.8 cm (1-1/2 in) blade depth

Fan Type

Ball bearing, DEC No. 1211714

Fan Capacity at 115 V, 50 Hz

122.7 1/s (260 ft3/min) at O static pressure

Fan efficiency at 90 Vac, 50 Hz

60%

7010014 Transformer
Assembly Weight

11.34 kg (25 Ib)

4-45

Table 4-11

MJ11-AA, AC, BA, BC Memory Frame Input Power
Electrical Specifications

Parameter

Specification

[nput Power

MIJI11-AA, BA 90-132 Vac,
47-63 Hz, single phase

115

Vac nominal,

MJ11-AC, BC

180-264 Vac (phase to neutral)
(312-456 Vac phase to phase)
3-phase wye at 30 A/phase
Inrush Current

175 A peak for 10 ms max. at 115 V line voltage

Input Power

1200 W maximum at 115 V nominal line voltage

Input Current

12 A max at 115 Vac

Circuit Breaker rating

20 A at 115 Vac

Power Factor

The ratio of input power to apparent power will be
greater than 0.85

Conducted Noise
(Noise on ac Line)
Transients

Single transient without loss of data: 300 V at 0.2
W /s max.

Single transient, survival: 1000 V at 2.5 W s max.
Average transient power survival: 0.5 W max.
CW Noise

10 KHz - 3 MHz: 3 Vrms
3 MHz - 500 MHz: 1 Vrms

500 MHz - 1000 MHz: 0.5 Vrms
RF Field Susceptibility

10 KHz - 1000 MHz: 1 V/m

Power Fail

The power supply is capable of withstanding power
interruptions of any magnitude and duration without damage. Storage time of power supply at low
line and full load shall be 20 ms minimum. Storage
time is measured from the time the power outage
occurs until the time the regulator voltages listed in
Table 4-16 drop below their specified regulation
limits.

4-46

Table 4-12 MJ11-AB, AD, BB, BD Memory Frame
Input Power Electrical Specifications
Parameter
Input Power

Specification
180-264 Vac,

230 Vac nominal,
47-63 Hz, single phase

Inrush Current

80 A peak for 10 ms max at 230 Vac line voltage

Input Power

1200 W maximum at 230 Vac nominal line voltage

Input Current

6 A max at 230 Vac

Circuit Breaker Rating

10 A at 230 Vac

Power Factor

The ratio of input power to apparent power shall
be greater than 0.85

Conducted Noise
(Noise on ac Line)
Transients

Single transient, without loss of data: 300 V at 0.2
W/s
Single transient, survival: 1000 V at 2.5 W/s max
Average transient power survival: 0.5 W max

CW Noise

10 KHz-3 MHz: 3 Vrms
3 MHz-50 MHz: 1 Vrms
500 MHz-1000 MHz: 0.5 Vrms

RF Field Susceptibility

10 KHz-1000 MHz: 1 V/m

Power Fail

The power supply is capable of withstanding power
interruptions of any magnitude and duration without damage. Storage time of power supply at low
line and full load shall be 20 ms minimum. Storage
time is measured from the time the regulator voltages (listed in Table 4-16) drop below their specified regulation limits.

A functional block diagram of the power supply is shown in Figure 4-30. If the line cord is plugged into
an energized outlet, line voltage is applied to the ac input box. The ac input box contains a circuit
breaker, an ac power control board, and a power line monitor board. The circuit breaker is used as an
ON/OFF switch, as well as an overcurrent protection device. The ac power control board and its
associated relay (K2) allow remote control of ac power to the transformer assembly primaries by the
thermal switch mounted on the transformer assembly. The memory frame cooling fans connect
directly to the transformer primaries.

4-47

OWER SUPPLY
FAN

|
|

P T P8
L

ACINPUT

[700981T(-1 OR-2)

I D'
l

INPUT BOX

ij131’5

Jalpa

)

Agofig\ggfi

J3IP3

5410993

gy-v

| P6

SECONDARI

SwiTcH

z:wxc

BOARD

J2 P2

+5V TO P21

GND TO P20

j QXQKPLANE
7010497
I

P21jy21

H744

p15'__.l

gzov;gv T200P21

P20| 420

P15 ———

CONNECTOR)

J
P1sj

5411086 -YA POWER | | [(carD EDGE

LINE MONITOR

] |

28 VAC

THERMAL

S0ARD *——L—[]:

P [M

EsS

RARNESS

DISTRIBUTION

TRANSFORMER|
|||TRANSFORMER
PRIMARIES
SECONDARIES

7010580 POWER

7010014 TRANSFORMER

Pj‘ P‘IO]’0
)

ASSEMBLY

e!l "
RELAY

FAN

[m]

REGULATOR

7010581

HARNESS

P14[___.|_\

TO P18

GND TO P20

i N

P14

H744
REGULATOR
#2

+20V,-5V TOPI8
GND TO P20

J13r__|_\

p1I3——

H754
REGULATOR
$#1

I
P19

|u19

AC LOW ,DC LOW

PINS1 AND 3 JUMPERED BY
P3.P3 IS PART OF 7010580

POWER DISTRIBUTION

HARNESS.

- ]

11-3024

Figure 4-30

MJ11 Power Supply Functional Block Diagram

The 7010014 transformer assembly steps down the voltage from the ac input box to approximately 28
A power line
Vac and routes it to the two H744 regulators, the two H754 regulators, and the 5411086-Y
monitor board in the ac input box. The H744 and H754 regulators produce the +5 V, +20 V, and -5
Vdc voltage required in the memory frame.

The 5411086-YA power line monitor generates the AC LO and DC LO power fail signals. It is
mounted within the ac input box and is secured in place when the ac input box is installed in the power
supply chassis. A card edge connector provides an electrical connection to a transformer secondary
and to the memory backplane. Note that although the 5411086-YA is physically mounted in the ac
A, which is referred to as the power
input box, it is considered a separate assembly. The 5411086-Y
4.4.6.1.
Paragraph
in
further
described
is
control card in some documentation,
The H744 (also used in the H7420) and H754 regulators are described in Paragraph 4.4.6.2. Drawings
E-UA-MJ11-0-0 sheet 4 and E-AD-7010694 sheet 2 illustrate these circuits and their interrelation.

The following paragraphs describe, in detail, the ac input box, the transformer assembly, and the box
fans.

The ac input box is mounted in the center of the power supply chassis with three Phillips head screws.
The center rear of the power supply chassis is cut out, exposing the rear of the ac input box. This
enables easy access to the ac line cord, circuit breaker, and remote power control Mate-N-Lok. The
5410993 ac power control board and the 5411086-YA power line monitor board are physically
mounted in the ac control box.

The 115 V (7009811-1) and 230 V (7009811-2) ac input boxes are functionally identical. They differ
physically in their components and in the way they are connected to the transformer assembly. Figure
4-31 is a simplified schematic of the 115 Vac power configuration. In this configuration, the power
transformer windings are connected in parallel. In the 230 Vac power configuration (Figure 4-32), the
power transformer windings are connected in series.

TRANSFORMER ASSEMBLY

115V 7009811-1
AC

15V A

INPUT BOX

cB1

.| BLACK

GRN

47-63HZ | |WHITE =

NOMINAL{

J5|PS

111

!o_1 2|2

3|3

4]4

TB1

[1]2,34 1 T

5678 2

TB2

[1]224

5,6,7,8 42

NOTE:

Transformer windings are connected in parallel to the input power.

Figure 4-31

115 Vac Power Configuration

4-49

11- 2546

TRANSFORMER

230V 7009811-2
AC INPUT BOX
_|PHASE

—

GRN

]

PHASE { WHITE) A
NOTE:

Transformer

[

[1]71]

I
230V
fiNOMINAL
47-63HZ

Oo—¢

windings

T81

J5|PS

CBI

(BLACK)
v

|
K2

are

[1,]2,3.4

2|2

5,/6.7.8 '3

ASSEMBLY

3|3

TB2
234 3

“T°]

414

5,/6,7,8 4%

connected in series to the input power.
11-2545

Figure 4-32

230 Vac Power Configuration

Utilizing the 115 Vac input box (7009811-1), the input line voltage is applied via a 20 A circuit breaker
to relay K2 and transformer T1 on the power control board. Transformer T1 steps down the voltage to
24 Vac. The 24 Vac is rectified and applied to relay K1 (Figure 4-33). Energizing K1 completes the
path to K2, switching the 115 Vac to the transformer assembly. The normally open thermal switch
(TS1) (located in the transformer assembly) closes when an over-temperature condition is sensed.
Closing TS1 applies 24 Vdc to half the K1 relay coil. This creates two opposing fields, causing K1 to
de-energize. De-energizing K1 interrupts the ac power to the transformer assembly. The varistor (D}6
or D7) across the coil of K2 suppresses voltage spikes in excess of 150 Vac for ac input box 7009811-1
and 275 Vac for ac input box 7009811-2.

54 -10993 AC POWER

CONTROL BOARD

FAST-ON TABS

TO 230VAC OR 115 VAC
RELAY

COIL K2

REFERENCE

—F;_J

-1

|
|

=== .|

——"
e

——i¢—
|

THERMAL (N.O.)

230 VAC

g E

T
.

3 EN VI

24VDC

SWITCH

—T

)

L ————— J

2.7k

JUMPERED AT J3 OF
AC INPUT

BOX BY
P3 OF POWER DISTRIBUTION
HARNESS

NOTE:
THERMAL SWITCH IS NOT PART OF
AC POWER CONTROL BOARD.

Figure 4-33

24VDC

11-3026

Power Control Board Simplified Diagram

4-50

The 7010014 transformer assembly is located in the center of the power supply chassis. Two capacitors,
two varistors, and two terminal boards are mounted directly on the transformer. The transformer base
plate is used to bolt the transformer to the chassis. The area around the transformer is open, enabling
ample air flow from the two fans across the transformer. A thermistor is mounted directly to the
transformer frame, enabling over-temperature monitoring. Output leads from the transformer, which
go to other modules, are terminated in Mate-N-Lok connectors. A cable clamp is used to secure these
leads to the chassis.
The primary function of the transformer assembly is to step down the 115 Vac or 230 Vac input voltage

to 28 Vac. There are five separate secondary transformer windings, one for each regulator and one for
the power line monitor board. In addition, the transformer assembly routes 115 Vac from TB1 and
TB2 to box fans 1 and 2, respectively.
The two capacitors (C1, C2) connected across the primary of T1 function as input line filters. Two

varistors (D1, D2), also connected across the T1 primary, suppress voltage spikes in excess of 150 Vac.
Two, 6-inch ball bearing box fans (1211714) are used in the power supply. They are mounted on the
chassis between the module boards and regulators. Each fan is secured to the chassis with two screws.
4.4.6.1

5411086-YA Power Line Monitor - The 5411086 power line monitor (Figure 4-34)isa 15V
switching regulator that also produces real time clock (LTCL) and power fail (AC LO and DC LO)

signals. A +8 V terminal is also provided. LTCL is a square wave, logic level, signal at line frequency.
AC LO L indicates that the line voltage is below a prescribed minimum. DC LO L indicates that the
line voltage is below the minimum operating tolerance and that the +15 V regulator circuit cannot be
expected to produce an output within specified normal operating limits.
The 15 V output can be connected to provide either a ~15 V or a +15 V source. If connected asa-15V
source, the LTCL and +8 V terminals should not be used. This is the case in the processor cabinet
power system. The 5411086 in the upper H7420 power supply produces +15 V, +8 V, LTCL, and the

AC LO-DC LO signals while the 5411086 in the lower H7420 produces only -15 V and the AC
LO-DC LO signals.

NOTE
The MJ11 power supply is equipped with the -YA
version of the 5411086 board. The 5411086-YA contains the line clock and power fail circuits just
described, but not the regulator circuit.
The specifications for the 5411086 are listed in Table 4-13. Drawing D-CS-5411086-0-1 is a circuit
schematic of the 5411086.
In the regulator circuit, the 20-30 Vac input is full-wave rectified by bridge D11 to provide dc voltage

(25 to 45 Vdc, depending on line voltage and load on +15 V) across filter capacitor C1 and bleeder
resistor R15. Operation centers on voltage regulator E1, which is configured as a positive switching
regulator. A simplified schematic of E1 is shown in Figure 4-34. El is a monolithic integrated circuit
that is used as a voltage regulator. It consists of a temperature-compensated reference amplifier, an
error amplifier series pass power transistor, and the output circuit required to drive the external transistors. In addition to El, the regulator circuit includes pass transistor Q7, predriver Q4, and level
shifter Q6. Zener diode D17 is used with R11 to provide +15 V for El.

The output circuit is standard for most switching regulators and consists of free-wheeling diode D12,
choke coil L1, and output capacitor C3. These components make up the regulator output filter. Freewheeling diode D12 is used to-clamp the emitter of Q7 to ground when Q7 shuts off, providing a

discharge path for L1.

4-51

I SENSI—NG_CIF\’—CUIT_

DCOK

DC LOW

—*

SENSING

Q13,Q16

D21

ACLO,DC LO DRIVER

AC LO, DC LO SENSING

—l—fl

p20

AC LOV(J;

\_/

ACOK

(10,014,Q17

FET NEGITIVE

Q15,018,019

Q3,05,T1

FUSE

FULL WAVE

RECTIF IER

S\ p

D11

L(3.9V)

D19

‘

l
|

ZENER

D17

REGULATOR

R4,R5,R6,01,02,02

OVERVOLTAGE
CROWBAR

CIRCUIT

»+13VDC

|
I

REFERENCE

OVER CURRENT

SWITCHING

(PASS TRANSISTOR)
Q4,7

15 VOLT

(ZENER

— L0

REGULATOR

LINE

1.2

I
LINE CLOCK

o AC LO

REGULATOR CIRCUIT
ACINPUT

L D NS D AR o E— —— L] — E—— SE— — —— E———— R S L
20-30 VAC

DRIVERS

GENERATOR

DC LO

—> .5

L| aciow

BIAS VOLTAGE

DRIVERS

SENSIN
an Q12

—»|

DC LOW

VOLTAGE REGULATOR I.C.

REFERENCE

ZENER

v[?Lr[l)AEeg
i

NYCOMPARATOR
SRe4

VOLTAGE
ADJUST

!
!

]

t10%

+8VDC

- GND
1-4301

Figure 4-34

5411086 Block Diagram

Table 4-13

5411086 Specifications (+15 V)

Parameter

Specification

Input Voltage,

20-33 Vacrms,

47-63 Hz

Frequency

Input Power

120 W (at nominal line, full load)

Output Voltage

+15 Vde +£5%
+8 Vdc £10%

Output Load

+15V:0-40A
+8V:0-10A

The total of +15 V and +8 V loads must not
exceed 4 A

Adjustment

15V £1.5 V (R 24)

+8 V output is 6.8 V £5% below 15 V output

Ripple

0.45 V peak-to-peak maximum

Backup Fuse

50A

Over Voltage

SCR crowbar trips at 16.5 Vto 19.5V

Protection

Output Signals

LTCL, AC LO (2), DCLO (2)

Indicators

2 LEDs (ACOK, DCOK)

In operation, Q7 is turned on and off, generating a square wave of voltage that is applied across D12 at
the input of the LC filter (L1 and C10). Basically, this filter is an averaging device, and the square wave
of voltage appears as an average voltage at the output terminal. By varying the period of conduction of
Q7, the output (average) voltage may be varied or controlled, thus supplying regulation (Figure 4-36).
The output voltage is sensed and fed back to El, where it is compared with a fixed reference voltage.
El turns pass transistor Q7 on and off, according to whether the output voltage level approaches its
upper and lower limits (approximately +15.15 V and +14.85 V respectively).

During one full cycle of operation, the regulator operates as follows: Q7 is turned on and a high
voltage (approximately + 30 V) is applied across L1. If the output is already at a +15 V level, then a
constant + 15 V would be present across L1. This constant dc voltage causes a linear ramp of current to
build up through L1. At the same time, output capacitor C10 absorbs this changing current, causing
the output level (+15 V at this point) to increase. When the output, which is monitored by E1, reaches
approximately +15.15 V, E1 shuts off, turning Q7 off; the emitter of Q7 is then clamped to ground. L1
reverses polarity and discharges through D12 into capacitor C10, and the load. Predriver Q4 is used to
increase the effective gain of Q7, thus ensuring that Q7 can be turned on and off in a relatively short
period of time.

Conversely, once Q7 is turned off and the output voltage begins to decrease, a predetermined value of
approximately +14.85 V will be reached, causing El to turn on; El in turn, causes Q7 to conduct,
beginning another cycle of operation.

4-53

FREQUENCY

COMPENSATION

INVERTING

INPUT O
VREF ©

—O V¢

SERIES PASS
TRANSISTOR

GL——————O vVOouT
x
—0 VZ

NONINVERTING

INPUT ©

V..

A -Voltage Reference Amplifier

B-Error Amplifier

ipe
i
C-Current
Limiter

CURRENT
LIMIT

CURRENT
SENSE

Simplified Schematic

NC |:_111

14| nC

curr uim [ 2
T
CURR SENSE [ 3

13| FREQ comP
12| v+

INV OUTPUT [4

(11] ve

NON-INV ouTPUT [ 5

10| vout

Vref [:6]:

n vz

1
v- [z

| 8 | ne

Pin Designations
11-1895

Figure 4-35

Voltage Regulator El, Simplified Diagram

Thus, a ripple voltage is superimposed on the output and is detected as predetermined maximum
(+15.15 V) and minimum (+14.85 V) values by E1. When +15.15 V is reached, El turns Q7 off; when
+14.85 V is reached, E1 turns Q7 on. This type of circuit action is called a ripple regulator.

The overcurrent regulator circuit functions as a current regulator when the current, monitored at D11,
exceeds 5 A. The current regulator consists of R4, R5, R6, Q1, Q2, and D2. During normal operation,

Q1 and Q2 are not conducting. Q2 starts conducting when the voltage drop across RS and R6 (sensed
by D2) exceeds approximately 0.6 V. When Q2 conducts, D1 becomes forward biased and El is shut
off, turning off the pass transistor Q7 and predriver Q4. The conduction of Q2 will also turn on Q1
providing a constant current source (1 mA) to the base of Q2. Q1 will hold Q2 on until the current
across R5 and R6 drop below approximately 4 A.

4-54

Q7 OFF

__________
:

— _REGULATED
OUTPUT

14.95V (TYPICAL)

11-2709

Figure 4-36

5411086 Regulator Waveforms

With Q1 and zener D2 tied to the +15 V zener reference for E1, the conduction of Q1 will hold E1 off.
When Q1 and Q2 stop conducting, E1 will turn on, enabling the current to exceed the regulator limits.
With a continuous overcurrent condition, Q1 and Q2 will be turning on and off, causing the circuit to
become a constant current regulator.

The +15 V overvoltage crowbar circuit consists of the following components: zener diode D18, silicon
controlled rectifier (SCR) Q8, Q9, R38, R40, C13, and Q9. Under normal output voltage conditions,
the trigger input to SCR D7 is at ground because the voltage across zener diode D3 is less than 18 V. If
the output voltage becomes dangerously high (above 18.0 V), diode D18 conducts turning Q9 on, and
the voltage drop across R40 draws gate current and triggers the SCR. The SCR fires, short circuits the
+15 V output to ground, and turns off E1 by shorting out the +15 V reference at D17.

The line clock output (LTCL) is derived from one leg of full-wave rectifier bridge D11, by voltage
divider R22 and zener diode D19. The clock output is a 0 to +3.9 V square wave at the line frequency
of the power source (47 to 63 Hz). The clock output is used to drive the KW11 clock options.

The AC LO and DC LO sensing circuit has a 20-30 Vac input from a secondary winding of transformer T 1. The sensing circuits are shown on drawing D-CS-5411086-0-1; a simplified version is shown
in Figure 4-34. The ac input is rectified by diodes D15 and D16, and filtered by capacitors C20 and
C24. A common reference voltage is derived by zener diodes D13 and D14. Both sensing circuits
operate similarly; each contains a differential amplifier and associated circuits. The major difference is
that the base of Q12 in the AC LO circuit differential amplifier is at a slightly lower value than that of
Q16 in the DC LO differential amplifier. The operation of both sensing circuits depends on the voltage
across capacitor C8. For AC LO and DC LO timing during power up and power down, refer to Figure
4-37. Table 4-14 lists some of the characteristics of the AC LO and DC LO circuits.
The AC LO and DC LO driver circuit produces the power fail signals that are sent to the memory

backplane. When an ac low condition is sensed, the output of differential amplifier Q12 turns off Q9.
Q19 in turn gates on FETs Q15 and Q18, generating AC LO 1 and AC LO 2 signals.

Approximately 7 ms after ac low is sensed, the dc low sensing circuit will generate DC LO. The dc low
sensed output from differential amplifier Q16, turns off Q10. Q10 in turn gates on FETs Q14 and Q17,
generating DC LO 1 and DC LO 2 signals.

4-55

AC POWER

(132V rms AC)

]

|
|

REGULATOR
I

OuTPUTS ¥

20ms
Maximum

LOW L

5ms.

—! [ Maximum
|

AC LOW L

—»

le—2ms Nominal

(5.5ms. Maximum)

AC POWER UP

--95V rms AC

AC POWER

OV--==--- ]

DOWN

GENERATED WHEN

FETS Q15 AND Q18

OF THE CONTROL

BOARD ARE

TURNED ON

Sms

REGULATTgR

OUTPU

7
|

minimum

-10%

;
|

AC LOW L

|+—‘>

minimum TM"

GENERATED WHEN

FETS Q14 AND Q17
OF THE CONTROL BOARD

}'T
-—’! j#—1 ms Minimum

]

AC POWER DOWN
11-3027

¥ The 5411086-YA version does not supply
regulated outputvoltoge.

Figure 4-37

Table 4-14

Parameter
Static Performance at Full Load
Input Voltage Increasing

5411086 Power Up and Power Down

AC LO and DC LO Circuit Specifications

Specifications

DC LO goes high at 75-80 Vac

AC LO goes high at 85-90 Vac
Input Voltage Decreasing

AC LO goes low (asserted) at 83-88 Vac

DC LO goes low (asserted) at 73-78 Vac

Hysteresis
Output Characteristics
Load
Rise/Fall Times

2-4 Vac (approximately)

J FETs can sink 100 mA (max)

1 us (max)

4-56

The +25 Vdc to +45 Vac from rectifier D11 is applied to T1, Q3, and Q5, Q3 and QS5, due to their
switching action, create a pulsating dc which is applied to the primary of transformer T1. The output
from the secondary of T1 (approximately 15 V) is rectified by D6, D7, D8, and D9, producing -10 Vdc
to —15 Vdc. The -10 Vdc to -15 Vdc is a negative bias used to gate OFF J FETs Q15, Q18, Q14, and
Q17 via Q19 and Q10. Unlike most transistors, the negative bias is used to turn off the J FETs. The J
FETs are turned on when there is zero volts between gate (G) and source (S) terminals.

Light emitting diodes D20 (ACOK) and D21 (DCOK) are normally lit. When AC LO L and/or DC
LO L are asserted, the light emitting diodes go off, indicating that this regulator is the source of AC
LO L or DC LO L on the Unibus. (The location of D20 and D21 on the H7420 5411086 is shown in
Figure 4-26.)
The following paragraphs describe AC LO and DC LO interconnections in the processor and memory
cabinets. Figure 4-38 shows the routing of these signals through the system.
Each main memory drawer power supply and both processor cabinet power supplies contain a

5411086 power line monitor board (memory power supply contains a -YA version). The ac power
monitor circuits (AC LO and DC LO) are on this board. AC LO and DC LO both have two independent open collector output drivers on each 5411086. Refer to the Engineering Print Set for a schematic
of this circuit.
Table 4-15 lists the processor cabinet and main memory cabinet AC LO and DC LO signals.

The AC LOssignals from all main memory power supplies are wire-ORed and transmitted to the cache
(ADML) on the main memory bus cable. The signal is buffered, renamed ADML AC LO H and is one
of two inputs to the processor power-up/power-down circuits on UBCE.
The processor power supply AC LO 1, AC LO 2, ACLO 3 and AC LO 4 signals are connected to the
Unibus AC LO line (BUS AC LO L) at the backplane. This signal is the other input to the processor
power-up/power-down circuits on UBCE, when it is ORed with ADML AC LO.

The output of the OR, UBCE AC LO L, is also input to the cache power-up circuits (ADM]J).
There are two separate DC LO lines in the PDP-11/70: BUS DC LO (Unibus) and MAIN DC LO

(main memory). Two signal lines are required because:
I.

The signal level on the Unibus (0 V to 5 V) is different from that on the main memory bus
(OV to 3.5 V), and

Theimpedance of the Unibus (120 @) is different from that of the main memory bus (75 Q).

BUS DC LO L is the wire-OR of DC LO Y (upper processor H7420 power supply), DC LO X (lower
processor H7420) and the DC LO signals from all devices on the Unibus. It is one of two inputs to the

processor power-up/power-down circuits on UBCE.

MAIN DC LO is the wire-OR of DC LO 1 (upper processor H7420), DC LO 2 (lower processor
H7420), and both DC LO outputs from all main memory drawers (via the main memory bus cable).
MAIN DC LO is buffered in the cache, renamed ADML MAIN DC LO H, and is the second input to

the processor power-up/power-down circuits.

BUS DC LO and MAIN DC LO are ORed (UBCE) and input to both the cache power-up and to the
processor power-up/power-down circuits. MAIN DC LO, however, is the only input to the main
memory protection circuitry (MCTH). This circuitry inhibits the memory write operations on power-

down 3 us after receipt of DC LO.

4-57

MAIN
MEMORY

MEMORY CONTROL

HARNESS
7010581

P6 ¢ Low

MJ11 MEMORY ;1 DC LOW
POWER SUPPLY 1 AC LOW
(UP TO 8)

OR MKN POWER SUPPLY

(UP TO 4)

(POWER CONTROL
5411086YA

| | ac Low

MJi1 BACKPLANE

P/J19

TM
1 A1381
X A1382

I MCTA M8148

LT
RR
o

PROCESSOR

HARNESS 7011051

T AC LO1

POWER SUPPLY m

(5411086 iN B
[
m

DC LOI
DC LO Y

AC LO 4
pe2

POWER SUPPLY

|9]

(5411086 IN

—

LOWER 7420)

MolACLO3

5 10¢ LO X

ACLO @

,__41___|

MCTH M8148
'

| PROTECTION |

— -

CIRCUITS

l—m—r —
1

A18E1

5 LMAIN DCLO L

0 A18C1

A1BLZT

DCLO H

ACLO H

0 C12F2

SE12L!

LMH

BUS ACLO L

MAIN DCLO L

BUS ACLO L

}

NOTES:

BUS DCLO L

|
|

1, Processor Power-down/ power-up circuit. Refer

4-58

‘

BUS DCLO L

AC LO and DC LO Circuit

I I

=
L Fize2

3 BUS DCLO L

l l
l
I
B |ahbete
mhowan
NOTE | B
NOTE 1 T B
| I
1
1
—
§

BUS
ACLO L

I_TMC
M8i35

>0 I

UNIBUS

Figure 4-38

D12S2

0BI2K2 0 DI2L1

! +-

Ba4F2
—°

UBCE ACLO L

UBCE

Q C18R1

M8136

F@iF1

1 BUS DCLO L
!

= ]

|ADML MAIN UBCE DCLO

ADML MAIN

MAIN DCLO L

H |

I
i

i UP CIRCUIT 1

l' CACHE POWER !|

ol
-] BUS ACLO L

DC LO 2

MEMORY

M8143

| J2

PROCESSOR BACKPLANE

UPPER 7420)

PROCESSOR

T
RR

| MAIN DC LOW L
|RrR
] MAIN AC LOW L IA

P15

i
[

ADMJ

ADML

I M8143

NOTE
2

BUS CABLE

Processor Manua! Section I, Chapter. 6.

2. Connecior J4 connecis Main Memory

KB11-B

Bus cabie io J3 on

MB8148 of next memory frame.

1ra

Table 4-15

AC LO and DC LO Driver Qutputs

Signal Name

Unit

Connector Pin

ACLOI1
ACLO?2
ACLO3
ACLO4

Upper processor H7420
Lower processor H7420
Lower processor H7420
Upper processor H7420

P/J15-8
P/J22-8
P/J22-10
P/J15-10

DCLO1I
DCLO2
DCLOX
DCLOY
DCLO
DCLO

Upper processor H7420
Lower processor H7420
Lower processor H7420
Upper processor H7420
Main Memory P/S
Main Memory P/S

P/J15-12
P/J22-9
P/J22-12
P/J15-9
P/J6-1
P/J6-2

ACLO
ACLO

P/J6-3
P/J6-8

Main Memory P/S
Madin Memory P/S

In the PDP-11/70, these interconnections are such that a power failure from any device (Unibus

device, processor or main memory):

Causes the processor to trap to location 24 and to perform the power-down subroutine, and

Causes the cache to prevent all access to main memory when DC LO is asserted at the end of
the 2 ms power-down subroutine time allotment.

In addition, when the power failure is a processor or a main memory failure, the main memory pro-

tection circuits are activated when MAIN DC LO is asserted by either the processor or the main

memory power supplies.

4.4.6.2 H744 and H754 Regulators - There are seven (eight if the FP option is included) H744 regu-

lators in the processor cabinet power system (Figure 4-3). In the MJ11 memory cabinet power supply,
there are two H744 and two H754 regulators (Figure 4-4).

These regulators are secured to the power supply chassis with three screws and are installed with the
heat sink upward. The mounting screws pass through the chassis holes and screw into the regulator. A
plastic (Lexon) cover is installed on the component side of each regulator. This permits visual
inspection of the regulator components when the regulator is removed from the chassis. The fuse,
which is located on the component side, is accessed by removing the plastic cover. Table 4-16 lists the
output power characteristics of the H744 and H754 regulators.

Circuit schematics for the H744 and H754 regulators are shown in drawings D-CS-H744-0-1 and DCS-H754-0-1, respectively.

The following paragraphs describe the regulator circuit, overcurrent sensing circuit, and the overvoltage crowbar circuit for each regulator.

4-59

Table 4-16

Output Power Characteristics

Output Current

Maximum

Ripple

Regulator

Voltage and Tolerance

(maximum per
regulator)

Peak-to-Peak

H744

+5 Vdc

250 mV

25 A

200 mV

H754

+20 Vdc

8 A

5%*

-5 Vdc

250 mV

1A-8A**

5%*

*At backplane, typical ripple +3 percent.

**Maximum -5 V current is dependent upon +20 V current. It is equal to 1 A plus the current of the +20 V
supply, up to a total of 8 A.

In the H744 regulator circuit, the 20-30 Vac input is full-wave rectified by bridge D1 to provide dc¢
voltage (24 to 40 Vdc, depending on line voltage) across filter capacitor C1 and bleeder resistor R1.
Operation centers on voltage regulator El, which is configured as a positive switching regulator. A
simplified schematic of El is shown in Figure 4-34. E1 is a monolithic integrated circuit that is used as
a voltage regulator. It consists of a temperature-compensated reference amplifier, an error amplifier
series pass power transistor, and the output circuit required to drive the external transistors. In addition to El, the regulator circuit includes pass transistor Q2, predrivers Q3 and Q4, and level shifter Q5.
Zener diode D2 is used with Q5 and R2 to provide +15 V for E1. Q5 is used as a level shifter; most of
the input voltage is absorbed across the collector-emitter of Q5. This is necessary because the raw input
voltage is well above that required for E1 operation. While this +15 V input is supplied, D2, Q5, and
R2 retain the ability to switch pass transistor Q2 on or off by drawing current down through the
emitter of QS.

The output circuit is standard for most switching regulators and consists of free-wheeling diode D5,
choke coil L1, and output capacitors C8 and C9. These components make up the regulator output
filter. Free-wheeling diode D5 is used to clamp the emitter of Q2 to ground when Q2 shuts off, providing a discharge path for L1.

In operation, Q2 is turned on and off, generating a square wave of voltage that is applied across D5 at
the input of the LC filter (L1, C8, and C9). Basically, this filter is an averaging device, and the square
wave of voltage appears as an average voltage at the output terminal. By varying the period of conduction of Q2, the output (average) voltage may be varied or controlled, supplying regulation (Figure
4-38). The output voltage is sensed and fed back to El, where it is compared with a fixed reference
voltage. El turns pass transistor Q2 on and off, according to whether the output voltage level increases
or decreases. Defined upper and lower limits for the output are approximately +5.05 V and +4.95 V.
During one full cycle of operation, the regulator operates as follows: Q2 is turned on and a high
voltage (approximately +30 V) is applied across L1. If the output is already at a +5 V level, then a
constant +25 V would be present across L1. This constant dc voltage causes a linear ramp of current to
build up through L1. At the same time, output capacitors C8 and C9 absorb this changing current,
causing the output level (+5 V at this point) to increase. When the output, which is monitored by El1,
reaches approximately +5.05 V, El shuts off, turning Q2 off; the emitter of Q2 is then clamped to
ground. L1 discharges into capacitors C8, C9, and the load. Predrivers Q3 and Q4 are used to increase
the effective gain of Q2, ensuring that Q2 can be turned on and off in a relatively short period of time.

4-60

r—\————— Q2 ON

Q2 OFF
/5.05V (TYPICAL)

— _REGULATED
OQUTPUT

TM~ 4.95V (TYPICAL)

t1-0098

Figure 4-39

H744 Regulator Waveforms

Conversely, once Q2 is turned off and the output voltage begins to decrease, a predetermined value of
approximately +4.95 V will be reached, causing El to turn on; El in turn, causes Q2 to conduct,
beginning another cycle of operation.

Thus, a ripple voltage is superimposed on the output and is detected as predetermined maximum
(+5.05 V) and minimum (+4.95 V) values by E1. When +5.05 V is reached, E1 turns Q2 off; when
+4.95 V is reached, El turns Q2 on. This type of circuit action is called a ripple regulator.

The H744 +5 V overcurrent sensing circuit consists of Q1, R3 through R6, R25, R26, programmable
unijunction Q7, and C4. Transistor Q1 is normally not conducting; however, if the output exceeds 30
A, the forward voltage across R4 is sufficient to turn Q1 on, causing C4 to begin charging. When C4
reaches a value equal to the voltage on the gate of Q7, Q7 turns on and E1 will be biased off, turning
the pass transistor off. Thus, the output voltage is decreased as required to ensure that the output
current is maintained below 35 A (approximately) and that the regulator is short circuit protected. The
regulator continues to oscillate in this new mode until the overload condition is removed. C4 then
discharges until El is allowed to turn on again and the cycle repeats.

The H744 +5 V overvoltage crowbar circuit contains the following components: zener diode D3,
silicon-controlled rectifier (SCR) D7, D8, R22, R23, C7, and Q6. Under normal output voltage conditions, the trigger input to SCR D7 is at ground because the voltage across zener diode D3 is less than
5.1 V. If the output voltage becomes dangerously high (above 6.0 V), diode D3 conducts, and the
voltage drop across R23 draws gate current and triggers the SCR. The SCR fires and short circuits the
+5 V output to ground.

‘

The regulator circuit in the H754 has a voltage doubler input, but the output consists of two shunt
regulator circuits - one for the +20 V, the other for the -5 V. The +20 V shunt regulator consists of
transistors Q4, Q10, and Q11; the -5 V shunt regulator consists of Q6 and Q9. Q10 and Q9 are the pass
transistors.

4-61

The output of the basic regulator is 25 V (-5 to +20 V). The shunt regulators are connected across this
output, with a tap to ground between pass transistors Q9 and Q10. The voltage at the bases of Q6 and
Q4 will vary with respect to ground, depending on the relative amount of current drawn from the +20
V and -5 V outputs of the regulator. If the +20 V current increases while the -5 V current remains
constant, the output voltage at the +20 V output will tend to go more negative with respect to ground;
this will also cause the -5 V output to go more negative, since the output of the basic regulator is a
fixed 25 V. This change is sensed at the bases of Q6 and Q4; Q6 will conduct, causing Q9 to conduct
also, increasing the current between -5 V and ground until the balance between the +20 V and the -5V
is restored. At this time, neither Q6 nor Q4 will be conducting. If the -5 V current increases, Q4 and
Q10 will conduct to balance the outputs.
The H754 has two crowbar circuits: Q7 and its associated components for the +20 V and the Q12 and
is circuitry for the -5 V. Either one will trigger SCR D9.
The H754 overcurrent circuit comprises Q1, Q8, Q13, Q14, and associated circuitry. The total peak
current is sampled through R4. When the peak current reaches approximately 14 A, QI turns on
sufficiently to establish a voltage across R7 and R38, firing Q8. This pulls the voltage on pin 4 of the
723 up above the reference voltage on pin 5, shutting off Q2. D6 now conducts, and the current
through R37 turns on Q14, which turns on Q13. This keeps Q8 on for a time which is determined by
the output voltage and L1. This action, in turn, allows the off-time to increase as the overload current
increases, thereby changing the duty cycle in proportion to the load. The output current is thus limited
to approximately 10 A.

4.4.7 MKI11 DC Power Supply
The MK11 power supply consists of an ac input box (7014420-1, 2), a transformer assembly (7011486),
a +5 V regulator (H7441), three £12 V and +5 V regulators (7014251), and three battery backup units
(H755-D). A chassis, mounted at the back of the memory box, houses the ac input box, transformer
assembly, the four voltage regulators, and two cooling fans. The three battery backup units and their
battery packs are each housed in their own boxes, separate from the other power supply assemblies.
Figure 4-40 identifies the major assemblies of the memory’s power supply.

4.4.7.1

MKI11 Power Supply Cables

External Power Cables
The external power cables interconnect the memory box and the box controller and battery backup
units within the memory cabinet. Figure 4-41 is a simplified block diagram of these cables. For the
actual cable routing, see Paragraph 3.6.
Box Controller Power Cable (7014311) - This cable harness connects the on/off power switch on the

box controller to the memory’s power supply for controlling power to the memory. This harness also
carries signals to the battery status indicators, which show the operating mode of the three battery
backup units.

Battery Backup Power Cable (7014520-08) — These three cables connect the battery backup units to

their regulators. Power to charge the batteries or power from the batteries to run the memory is carried
by these cables, along with control and battery status signals.
Internal Power Harnesses
The internal power harnesses connect the power supply assemblies to the memory backplane. These
harnesses are shown in Figure 4-42.

4-62

TRANSFORMER
ASSEMBLY

7014251-0-0
REGULATOR ‘B’

7014251-0-0
REGULATOR 'C’

FRONT

\
MEMORY
BACKPLANE
|
REGULATOR

T
\

+5V REGULATOR

MOUNTING

H7441

SCREW

7014251-0-0

———J30
'
J29
'

REGULATOR ‘A’

°8
J28

REGULATOR

MOUNTING

AC INPUT BOX

SCREWS

J1(TO

J28,J29, OR J30)

H775

BATTERY BACKUP UNIT (ONE OF THREE)
MA-1632

Figure 4-40

MKI11 Power Supply Major Assemblies

4-63

(OIT]| BOX CONTROLLER
7014274 -0-0

7014311-9F

BCOBR-10

MEMORY BOX

P31

7014520-08

J_ZST

J29

~~7014520-08

H775-D

BATTERY BACKUP A

SWITCHED AC OUTLET

7014520-08

‘Eso

H775-D

BATTERY BACKUP B

BATTERY BACKUP C

|AC LINE CORD
| TM |

861 - D,E
POWER CONTROLLER

Figure 4-41

MA-1633

MKI11 Power Supply External Cabling

4-64

HARNESS

7010581

‘

+12VB
&
+5

ADJUSTMENT

J13

7014251

128

]

——
J14

J18[P1s

7441

GND

Ja N
\

T T T T T T

Si5Ters

INPUT

BOX

P1|P1

—
J20| P20

Ifi

o
&= FRONT

o
BACK PLANE (PIN SIDE)

HARNESS

| P26

POWER

CORD

5Py

P24
__ P24 P15;
=
P25

fi&
92 <

+5V ADJUSTMENT

]

P25

Jis

7014251

_____________>i12VB&+5VB

—{TJJ16

__p26]r16

3\].129

ADJUSTMENT

7014251
o

]J30

7014228

MK11 POWER SUPPLY
#7014227-00-0 (120 V)
HARNESS

#7014227-01-0 (240 V)

7014312

WIRING DIAGRAM
BACK PLANE TO MK11

POWER SUPPLY
MA-1634

Figure 4-42

MKI11 Power Supply Internal Cabling

4-65

four regulator
Power Distribution Harness (7014228) — This harness carries low voltage ac power to the
boot enable
and
fail
Power
e.
backplan
the
to
voltages
output
regulated
the
modules and connects
signals from the backplane are also sent by the 7014251 regulators via this harness.

Power Monitor Harness (7010581) — This harness carries the power fail signals to the memory backplane from the ac input box.

cable (7014311) to
Box Controller Harness (7014312) - This harness connects the box controller power
on and battery status
the power supply. It carries the power on signal to the ac input box, and power
signals between the three 7014251 regulators and P31.
4.4.7.2

Power Supply Major Assemblies

AC Input Box (7009811-1, 2)

head screws.
The ac input box is mounted in the center of the power supply chassis with three Phillips
from the
visible
box
input
ac
the
making
out
A portion of the rear of the power supply chassis is cut
primary
The
cutout.
the
through
extend
breaker
back of the memory. The ac power cord and a circuit

assembly
function of the ac input box is to switch power to the transformer’s primary windings. This
a power
and
,
(5410993)
board
control
power
ac
an
consists of a circuit breaker, a power control relay,
line monitor board (5411086-YA).

to the transThe ac power control board operates the power relay that switches primary ac power
controller
box
the
from
supply
power
the
for
control
power
former assembly. This allows remote
power switch.

Sensing
The power line monitor board receives a low voltage ac output from the transformer assembly.
is
power
if
memory
the
for
signals
low
dc
and
low
ac
the
generate
and
circuits monitor the ac voltage
memory
lost. Two LEDs indicate the generation of the power fail signals by turning off, flagging the
low not
dc
and
low
(ac
ns
conditio
normal
Under
signals.
low
dc
and
low
ac
that is the source of the
asserted) these LEDs are lit.

Transformer Assembly (7011486)

capacitors, two
The transformer assembly is located in the center of the power supply chassis. Twophase
115 Vac or
Single
varistors, and two terminal boards are mounted directly on the transformer.
secondseparate
five
are
230 Vac is stepped down by the transformer to approximately 30 Vac. There
cooling
The
board.
monitor
ary windings, one for each regulator module and one for the power line
and the
voltage
line
input
the
fans receive 115 Vac from the primary windings. The two capacitors filter
varistors suppress voltage spikes that occur on the ac input voltage.
+5 Vdc Regulator (H7441)

(as
The H7441 module mounts in the power supply chassis to the right of the transformer assembly
the
to
input
The
screws.
head
Phillips
viewed from the front.) It is secured in the chassis by three
regulator is 30 Vac from one of the transformer’s secondary windings; its output is a regulated +5 Vdc
at up to 32 A.

. An
The H7441 is a switching regulator and provides both overcurrent and overvoltage protection
folda
is
overload
current
The
loads.
shorted
from
overcurrent sensing circuit protects the regulator
to
regulator
switching
the
of
cycle
duty
the
limiting
by
back type; the output voltage is decreased
that
circuit
crowbar
age
overvolt
an
by
provided
is
n
protectio
age
decrease the output current. Overvolt
shunts the output current to ground through an SCR when the output voltage exceeds 6 V.
An LED, visible from the bottom of the regulator (near the voltage adjustment potentiometer), lights
whenever +5 V is present at the output of the regulator.

4-66

+12 VB and +5 VB Battery Backup Regulators (7014251) and Battery Backup Units (H755D)
The three 7014251 modules mount in the power supply chassis in the locations shown in Figure 4-40.
Each regulator is secured in the chassis by three Phillips head screws. The regulators are cabled to their
battery backup units through cutouts at the rear of the power supply chassis. The battery backup units
are housed in their own enclosures that mount in the memory cabinet. Figure 4-43 is a block diagram
of one of the regulator/backup unit pairs.

The £12 VB and +5 VB regulator consists of a regulator board (5413075), an input rectifier board
(5412411), and a controller board (5413073). The rectifier board rectifies the low voltage output from
the transformers secondary windings, supplying the raw dc voltage to the rectifier. Raw dc from the
rectifier also goes to the battery backup unit to supply the charging current for the batteries. In the
regulator, the raw dc is modulated by a switching circuit. Energy in the switched dc waveform is
transformer coupled to rectifiers that produce the +12, -12, and +5 V outputs. Regulation is accomplished by changing the duty cycle of the switched raw dc to keep +5 VB at 5 V. The regulator is
overcurrent protected by a foldback current limiter and overvoltage protected by a crowbar circuit.
The controller monitors the power fail and charge mode signals to control the operation of the batteries and indicate the battery status with the lights in the box controller. Operation of the regulator is
enabled by the power switch on the box controller via the signal DC ON. A normally closed thermal
switch in the DC ON path opens and shuts off the regulator if an over temperature condition exists.

The battery backup unit contains a battery charger printed circuit board (5411625) and two 12 V
batteries (1212499). The battery charger consists of a regulator that supplies the charging current,
charge status circuitry, and a relay that connects the batteries to the charger. When the memory is
powered up, the controller in the 7014251 regulator connects the batteries to the charging regulator
through the relay. The regulator supplies the charging current from the raw dc input, supplying a full
charging current until the battery voltage reaches approximately 22 V. After this level is reached, the
regulator supplies a trickle charge to maintain the charge on the batteries. The rate of charging is
sensed by the charge status indicator circuitry that sends the charge mode signals to the 7014251
regulator.
Loss of ac input power causes the loss of the rectified raw dc from the 7014251 regulator. When this
happens, the batteries supply the dc voltage to the regulator in the 7014251 instead of the rectifier
board. The regulator will continue to produce +12, -12, and +5 V until the batteries discharge past 18
V. An 18 V reference is used by the relay to disconnect the batteries from the regulator to prevent the
batteries from discharging completely.
.
4.4.7.3 Power Distribution — Figure 4-44 shows the interconnection of all the power supply assemblies
identified in the previous paragraphs. Distribution of the power can be traced from the ac line input to
the memory backplane with this diagram; specific pin numbers and color coding of wires are found in
the field maintenance print set. Locations of the regulated inputs to the backplane are called out in
Figure 4-45 which shows the backplane as viewed from the bottom (wire-wrap pin side).
Single-phase ac line voltage is present at the ac input box from the 861-D,E power controller. Turning
the power switch on the box controller activates the power relay through the ac power control board.
The power relay switches 115 Vac or 230 Vac to the primary windings of the transformer and to the
two cooling fans. From the transformer secondary windings the stepped down 30 Vac is routed to the
four regulator modules via harness 7014228. The power switch on the box controller also switches on
the three 7014251 regulators and the battery backup units.

4-67

P/J13, 156, OR 16

PART OF HARNESS

P/J28, 29, OR 30

RATTERY

CHARGER

5411625
~45

5 VDC REGULATOR

GE
CHAR
STATUS

18 V REF

o—»{ RELAY

INDICATOR

RDC IN

fa—GND

H775

l_i_J
=

BACK-UP
UNIT

BATTERY

BAT IN

MODE
4e | CHG
le_t5VE
6

l
TTER
=
BATTERIES
¥

1
3

7014228

. |+12ve T

MON (KEY) EN 6

]

REGULATOR

CONTROLLER

L 4 A

, |GND
3

RAW

6 -12 VB )

AC IN"—1 rrom
7 [*=——

e [

THERMAL

kTO

ol 4A |1VB8_ [BACKPLANE

7014251

CABLE #

+5VB & +12 VB
REGULATOR

7014520-08

— P/J23, 25, OR 27

7O BOX CONTROLER (P31)

1 |«2CON__y
,

PART OF HARNESS

|BAT MON_
s

ADAND

ITVI%0 <

—
S

AC LOW

TO BACKPLANE
DC LOW
2 j&—————— ) PART OF HARNESS
BOOT EN L| 7014228
l————

P/J22, 24, OR 26

Figure 4-43

Battery Backup Regulator Block Diagram

4-68

MA-1635

F
AC INPUT BOX
ok

AC INPUT
FROM

861-D.E

BREAKER

p7] pg
POWER

UNIT A

Tpg P10

H775

TRANSFORMER|
ASSEMBLY
|

J4|Pa
s

WER LINE

[

MONITOR

P1[T]J1

AC POWER | [T
CONTROL ||

MAIN BOOT ENL

BATTERY BACKUP

Y 7019510

Js|rs

RELAY

[

FAN

’g

30 VAC

L_',
—Ip13

A
7014251

DC LOW,

|
i

BAT MON

” BACKPLANE

SLOT NUMBERS
, o

___Eaj:g;

0 BOOT ENL

+5V

P88 | 1o ve
-12VB

—

+5V, GND

P19|J19
AC L

+12 VB, -12 VB,
P20l J20

s2gfp2s

—"
T

o FJ:

_E—o.

DC ON

SWITCH

BAT MON

AC LOW

‘B’
7014251

| |

OFF t

J3o|pzo

STATUS

DC ON

HARNESS

—

7014520-08

> +5V FROM H7441

18-

- +12 VB AND +5 VB

19—

FROM 7014251 ‘B’

20—

+12 VB, - 12VB,
+5 VB GND
AC LOW

L—Jdpr16

DC LOW

23-

+12 VB AND +5 VB

P21fy21 L7

24 -

FROM 7014251 ‘C’

—

25~

+5V

+5 VB

1 BOOT ENL

26 -

BACKPLANE

P26[J26

J27

12 VB

PART OF

HARNESS

7014228

_HARNESS
7014520-08

BATTERY BACKUP|
UNIT B

H775

15=)

292
=

BAT MON

BOX CONTROLLER

12-

21—_/

P24]J24

J16

P27r——

GND

2 BOOT ENL

[ 7014251 |1 |

BATIERY

2 BOOT ENL

stL.I__l

gg% 7010581

DC LOW

L—Ip1s

P25

SOWER

—

J15

+12 VB AND +5 VB

9-[ FROM 7014251 ‘A’
o=

17—
J

//HARNESS
7014311

16—

+5 VB GND
81

s:fl

0 BOOT ENL ._

— P14
H7441

7014321

AC LOW

DC LOW

—I‘L‘[IJM

+12 VB AND +5 VB

4- ( FROM 7014251 C

+5 VB

323

__~ HARNESS
P31

AC LOW,

P23 P22[J22

DC ON

y
7

J13

J2g|p28

928

7014520-08 412 vB, _12 VB, +5 VB, GND
|

m';Lgst

T~ HARNESS

RAW DC IN

|BATTERY BACKUP
UNIT C
H775

GND

BAT IN
CHARGER STATUS
+5V
KEY ENABLE
MA-163€

Figure 4-44

MKI11 Power Distribution and Control

4-69

-12vB (A) P13-6

+12VB (A) P13-1

+5VB (A) P13-4
1

+5V P14-2
+5V P14-5
J19

GND
GND
GND
GND
GND

®
J20

GND (+5V) P14-8
GND (B) P15-2
GND (C) P16-2
GND (+5V) P14-3
GND (+5V) P14-4
GND (A) P13-2
GND

®
|

-t

+5V P14-1

+5VB (C) P16-4

+5VB (B) P15-4

+12VB (B) P15-1
+12VvB (C) P16-1

—12VB (B) P15-6

—12VvB (C) P16-6

MA-1637

Figure 4-45

MKI11 Backplane Power Connections

Thirty volts ac from one of the transformer’s secondary windings is rectified and regulated by the four
regulator modules. The H7441 +5 V regulated output is carried by harness 7014228 from J14 on the
regulator module to backplane connectors J18 and J21 (ground return to J20.) From these connectors,
the +5 V are routed to all backplane slots. The +5 V powers all the devices on the address buffer, data
buffer, and the four control modules not flagged with asterisks in the schematic diagrams. A LED, on
the bottom of the regulator near the adjustment potentiometer, illuminates while the H7441 is producing +5 V.

Three more secondary windings supply 30 Vac to the three 7014251 modules via harness 7014228.
Regulator A produces +12, -12, and +5 Vdc (£12 VB, +5 VB) which are carried through harness
7014228 (J13) to the memory backplane connector J18 (ground returns to J20.) From J18, regulator
A’s voltages go to backplane slots 6 through 13. The A regulator provides power to all the devices
indicated with asterisks on the address interface module, the control 0 pair of control A and B modules, and to the array modules in backplane slots 6, 7, 8, and 9.
Regulator B produces +12, -12, and +5 Vdc, which enter the memory backplane via harness 7014228
to connector J21 (ground returns to J20.) The B regulator powers backplane slots 14 through 21, which
contain the data buffer module, the control 1 pair of control A and B modules and the arrays in slots
18, 19, 20, and 21. Only the devices indicated with asterisks on the schematic diagrams are powered by
the B regulator.

‘

Regulator C sends its £12 VB and +5 VB voltages to the backplane via harness 7014228 to connector
J21 (ground returns to J20.) Its regulated outputs power the array modules in backplane slots 2
through 5 and 22 through 25. Figure 4-45 locates the backplane connector pins that carry the regulated
voltages and the source connectors and pin numbers.

A fifth secondary winding on the transformer supplies low voltage ac to the power line monitor located
in the ac input box. When power is switched on, the power line monitor switches the dc low signal to a
high level and then the ac low signal to a high level. Harness 7010581 carries these dc low-and ac low
signals to the memory backplane connector J19. The memory monitors the power fail signals from its
own power line monitor and power fail signals from the main memory bus. From the backplane, dc
low and ac low signals go to the 7014251 regulators (J22, J24, and J26) via harness 7014228, These

same cables carry the boot enable signals to the 7014251 regulators. The source of the boot enable
signal is cable 7019510, which plugs into connectors J100 and J101 on on memory box no. 0. Other
memories in the system obtain the boot enable signal from the main memory bus.

Raw dc, rectified from the 30 Vac, is sent to the battery backup units by the 7014251 regulators via
harness 7014520-08. This voltage powers the battery charger and supplies the charging current for the
battery pack. The regulated output, +5 VB, also goes to the battery charger. The battery backup units
send charger status information to the regulators, which send coded status signals to the box controller
via harness 7014312 (P31). These battery monitor signals operate the battery status indicator LEDs in
the box controller. The coding is as follows:

OFF, Battery off
SLOW FLASH, Battery receiving full charge
FAST FLASH, Battery supplying power to memory
ON, Battery receiving trickle charge

In the event of a power failure, the batteries in the backup units supply current to the 7014251 regulators which continue to produce their regulated output voltages. Power is then supplied only to the
array modules and the devices flagged with asterisks on the schematic diagrams of the address buffer,
data buffer, and control A and B modules. Battery power is used by the memory for refresh cycles
only, no other memory cycles are allowed to run.

4-71

4.5

MAINTENANCE

Maintenance of the PDP-11/70 power system is discussed in the following paragraphs. Included are
the preventive and corrective maintenance procedures for the 861-D, -E power control, the H7420
power supply, and the memory power supply. H7420 and memory subassembly removal procedures
are also described.

The most important point in maintenance philosophy is that the user understand the normal operation
of the PDP-11/70 power system as previously described in this chapter. A thorough comprehension of
this information, plus the maintenance procedures described, are the best tools the user has to isolate
and correct malfunctions.
4.5.1
861-D, -E Power Control
The 861 power controllers are constructed of high quality components (Figures 4-46 and 4-47) and can

therefore be expected to provide trouble-free performance for extensive periods. No adjustment or
alignment procedures exist. No special tools or equipment are required and no fuses are utilized. A
5000 ©/V multimeter is adequate for accomplishing all voltage and resistance measurements.
Preventive maintenance procedures for the power controllers consist of periodic cleaning and
inspection to detect any mechanical damage to wiring and components or evidence of overheating, etc.
The operation of the thermal switch can be checked by holding a flame close to the sensing element
while the controller is operating and observing that the switched outlets become disabled. Emergency
shutdown response to devices on the signal bus can also be checked as a preventive maintenance
procedure by connecting pins 3 and 2 of the remote switching control bus. Should a failure occur,
proceed as described in the following paragraphs.
WARNING
Dangerous potentials exist within the power controller. Perform all measurements with properly
insulated meter leads. Remove the main power plug
before attaching or removing test leads.

Failures within the power controller occur in one of three failure modes:
1.
2.
3.

No output (circuit breaker trips)
No output (circuit breaker not tripped)
No control (including emergency shutdown and overtemperature)

The flowcharts in Figures 4-48 and 4-49 present a logical troubleshooting sequence for the three failure
modes.

4.5.1.1 No Output (Circuit Breaker Tripped) - If correct power is available from the mains, a tripped
circuit breaker can be caused only by: a faulty circuit breaker, a low resistance load, or a low resistance
within the power controller caused by component failure.
4.5.1.2 No Output (Circuit Breaker Not Tripped) — Failures within this mode are caused by: bad cable
connections, open components in the line filter, improper relay operation, or a faulty circuit breaker.

4.5.1.3 No Control - Control failures are associated only with the switched outlets; the input circuits,
line filter, and main circuit breaker are therefore not involved. These failures are caused by bad cable
connections, secondary circuit breakers, relays, and diodes. A faulty thermal switch, T1, can cause loss
of control. Control problems can be isolated to either the internal or external circuit by use of the
LOCAL/OFF/REMOTE switch. With the switch in the LOCAL position, if T1 is operating properly,
the switched outlets should be enabled. If not, the problem is within the controller circuitry. If operation is normal when in LOCAL, check the control signals from the external device.
4-72

SWITCHED

Cavaf:

OUTLETS

STRAIN
RELIEF

BRACKET

CONTACTOR K1

THERMOSTAT

(THERMAL SWITCH)

Y 0 ovn nee sl )

487034

T8N £ 2w B8R

i gpvgiH

VARISTOR

ONE RD0E0Y

LINE

FILTER

-C2

CB1,

CB3-CB6
. INDICATOR LAMPS

PILOT CONTROL

CIRCUIT BREAKER

UNSWITCHED

BOARD

CB7

OUTLETS 91
7570 - 2

Figure 4-46

861-D Power Control Component Identification

REPLACE

PHASE 1

CIRCUIT 1CB

FIND & REPAIR

SHORT
PHASE 1

CIRCUIT 1

TURN ON C8

IN LOAD

YES

TRIPS

CB ON

REPLACE CB

LOAD NOT SHORTED

TURN ON CB
INPUT

RIS

POWER

FIND &

REPAIR

LOAD

SHORT IN

)

CHECK POWER
AT MAINS

4
IF LOAD NOT

POWER

CHECK

i2& 13

TO SWITCHED

RESPECTIVE

OUTLETS

CBON

OPEN CB.

REPLACE CB

CHECK FW

T1 CLOSED

PHASE 1

POWER

BROKEN WIRES OR

SHORTED

RE PLACE CB

FHECK K1 CONTACTS J

CIRCUIT 1

MAIN CB ON

CHECK FOR’

LINE FILTER

LIGHTED

OR PINS 3-2

RECTIFIER

CONNECTED,

ON PILOT BOARD

{F BAD

SL¥

CLEAR OVERTEMP
CONDITION.

REPLACEK1*

REPLACE

PILOT BOARD

REPLACE

T1, OR CLEAR EMERG
SHUTDOWN FROM
SIGNAL BUS
MAIN

ce
TRIPS?
POWER

VOLTAGE

SIGNAL

AT K1 FIELD

BUS PINS 1-3

COiL

CONNECTED

REDISTRIBUTE

POWER CONTROL

QUTLETS?

OR REDUCE

OVERLOADED

TO SWITCHED

CHECK K1*
CONTACTS

LOAD

PUT SWITCH IN LOCAL

REPLACE
K1

OR CONNECT PINS 1-3
WITH SWITCH IN
REMOVE ALL

REMOTE

EMERGENCY

1OADS FROM

SHUTDOWN

QUTLETS

1S OPERATING
PROPERLY

YES

REMOVE OUTPUT

LEADS FROM

DOES

FIND AND REPAIR

SHORT CIRCUIT
IN POWER CONTROL

CIRCUT BREAKER

CHECK F.W. RECTIFIER
ON PILOT BOARD

CLOSING
T1 DISABLE

IF BAD
REPLACE

THERMAL SWITCH
1S OPERATING

YES

FIND AND

REPAIR SHORT

«CIRCUIT IN LOAD

REPLACE

Note:

CIRCUIT
BREAKER

K1 is the contactor for the
switched outlets. K1* is

the relay in the pilot control.

PILOT BOARD

PROPERLY

cP-1736

Figure 4-48

Troubleshooting Flow Diagram - 861-D

START

CHECK FOR

PHASE 1

CIRCUIT 1
NPUT

POWER
)

CHECK POWER
AT MAINS

OWER:

REPLACE BROKEN

BROKEN WIRES

WIRE OR

OR LOOSE

TIGHTEN

CONNECTIONS

CONNECTION

POWER

TO SWITCHED
OUTLETS??

CHECK

12813
LIGHTED

LINE FILTER

MAIN CB

SIGNAL

8US PINS 1-2

K1* CLOSED

OR PINS 3-2

CONNECTED

»?

CONNECTED,

T1 CLOSED

CHECK Fw

RECTIFIER

ON N Pl PILOT BOARD

L TURN MAIN CB ON

]

PUT SWITCH IN LOCAL

CLEAR OVERTEMP

OR CONNECT PINS 1-3

WITH SWITCH IN

CONDITION.

REMOTE

SHUTDOWN FROM

REPLACEK1*

REPLACE

l——

IF BAD

REPLACE
PILOT BOARD

T1, OR CLEAR EMERG

9L-v

SIGNAL BUS

ARE

VOLTAGE

P3, P4, PS, P6
ENERGIZED

AT K1 FIELD

colL

?
YES
POWER

CONTROD

REDISTRIBUTE

OVERLOADED

R REDUCE

CHECK K1

LOAD

CONTACTS

REPLACE
K1

EMERGENCY

REMOVE ALL

SHUTDOWN

LOADS FROM

DOES

CONNECTING
PIN 2 TO 3

OUTLETS

IS OPERATING

PROPERLY

DIsaBL
NO

vES

DOES

REMOVE QUTPUT

LEADS FROM

CIRCUIT BREAKER

FIND AND REPAIK

CHECK F.W. RECTIFIER

SHORT CIRCUIT

ON PILOT BOARD

CLOSING

T1 DISABLE

IN POWER CONTROL
YES

FIND AND

REPLACE

IF BAD

REPAIR SHORT

CiRCUIT

REPLACE

THERMAL SWITCH

IS OPERATING

CIRCUIT IN LOAD

BREAKER

PILOT BOARD

PROPERLY

NOTE:

K1 15 the contactor for

the switched outlets.
1% 15 the relay in the
priot control.

CP-1737

Figure 4-49 ~ Troubleshooting Flow Diagram - 861-E

A digital voltmeter (Weston Schlumberger DVM Model 4443 or Data Technology Model 21) should
be used for making the regulator voltage measurements. A calibrated oscilloscope may be used if a
DVM is not available. An oscilloscope is necessary for measuring ripple voltage. A VOM is useful for
making continuity and resistance checks within the power supply.
Visual Inspection

CAUTION
Make sure all power is off before performing the fol-

lowing steps.

Check all fans to ensure that they are not obstructed in any way. Clean air filters mounted

Visually inspect the modules and backplane for broken wires, connectors, or other obvious

Inspect all wiring and cables for cuts, breaks, frays, deterioration, kinks, strain, and
mechanical security. Repair or replace any defective wiring or cable covering.

Inspect the following for mechanical security; power supply regulators, fans, capacitors, etc.

on the inside of the cabinet door if required.
defects.

Tighten or replace as required.

Inspect power supply capacitors for leaks, bulges, or discoloration. Replace as required.

Voltage Measurements (MJ11) - Turn on power and open the memory cabinet door. Witha DVM, or
a calibrated oscilloscope, measure the dc voltages at the M8149 regulator test points (Figure 4-50 and

drawing D-CS-M8149-0-1, sheet 1). The procedure is described in Appendix G. Using an oscilloscope,

measure the peak-to-peak content of all dc outputs. Table 4-7 lists the test points, the associated
voltages and regulators, and the regulator and backplane connections. (Regulator specifications are
listed in Table 4-19; regulator adjustments are described in Paragraph 4.5.2.2).

Voltage Measurement (MK11) - Turn on power and measure the +12 VB, -12 VB, +5 VB,and +5V
voltages at J18 and J21 of the memory backplane with a DVM (Figure 4-45). All voltages must be
within £5 percent tolerance as listed in Tables 4-18 and 4-19. If a voltage is found to be out of
tolerance, perform the required voltage adjustment.

4.5.2.2 Memory Power Supply Corrective Maintenance — Before any adjustment procedure is undertaken, the MJ11 power supply should be inspected to ensure that the equipment is energized:
1.

2.
3.

Check that the memory cabinet 861 power control indicators light.

Check that all fans are energized.
Check that all regulator indicators light.

Voltage Regulator Adjustments

NOTE

Read the entire procedure before making any adjustment.

The voltage regulator outputs (Table 4-17) must be adjusted to the tolerances indicated in Table 4-19.
When performing the adjustments, ensure that the maximum voltages at the regulator are not exceeded. These voltages represent the maximum regulator voltage prior to crowbar. Figure 4-51 shows
the location of the voltage regulator adjustment protentiometers.

4-77

mM8149

VOLTAGE
TEST POINTS

TP1-TP7

7644-5

Figure 4-50

MJI11 Voitage Test Points

4-78

Table 4-17 Regulator Test Points (MJ11)
M8149
Test Point

Regulator

Voltage
(Vdc)

Regulator
Pins

Backplane
Connector Pins

TPI
TP2
TP3
TP4
TPS
TP6

744 No. 4
744 No. 2
754 No. 3
754 No. 1
754 No. 3
754 No. 1

+5
+5
+20
+20
-5
-5

J16-2,5
J14-2,5
J15-5
J13-5
J15-3
J13-3

J21-5,6,7,8
J18-1,2,3,4
J21-34
J18-5,6
J21-1,2
J18-7,8

TP7

TP Ground

Table 4-18

Regulator

Voltage

H7441

+5 Vdc

Regulator Voltage Measurements (MK11)
Regulator

Backplane

Connector Pins

Slots Supplied

J14-1,2,5

J18-1,2

10-17

Pins

Backplane

J21-7

7014251 ‘A’

+5 Vdc
+12 Vdc
-12 Vdc

J13-4
J13-1
J13-6

J18-4
J18-5
J18-7

6-13
-13
6-13

7014251 ‘B’

+5 Vdc
+12 Vdc
-12 Vdc

J15-4
J15-1
J15-6

J21-5
J21-4
J21-2

15-21
15-21
15-21

+5 Vdc
+12 Vdc
-12 Vdc

J16-4
J16-1
J16-6

J21-6
J21-3
J21-1

2-5,22-25
2-5,22-25
2-5,22-25

\
7014251 ‘C

4-79

Table 4-19

Regulator Specifications

Regulator

Voltage and Tolerance
at Backplane

Maximum Voltage
at Regulator
(Note 1)

Maximum Qutput
Current
Capability

H744

+5 Vde £250 mV

5.5Vdc

25 A

H754 (Note 3)

+20Vdc 1V
-5Vdc £250 mV

21.5Vdc

8 A

-5.5Vdc

1-8 A (Note 2)

H7441

+5 Vdc £250 mV

5.5Vdc

32A

7014251

+5 Vde £250 mV

6.0 Vdc

4 A

+12 Vdc £600 mV

13 Vdc

Regulator

Output Current Under
Maximum Load
(Per Regulator)

Maximum
Peak-to-Peak
Ripple

H744

17 A

0.2 Vdc

H754 (Note 3)

7.5A

1.0 Vdc

1.75A

1.0 Vdc

H7441

27 A

0.2 Vdc

7014251

35A

1.0 Vdc

1.3A

1.0 Vdc
.

NOTES:

Do not adjust the regulator to these voltages. They represent the maximum regulator voltage prior to
crowbar.

Maximum -5 V current is dependent upon +20 V current. It is equal to 1 A plus the current of the
+20 V supply up to a total of 8 A.

When adjusting the output of H754, adjust +20 Vdc first, then -5 Vdc. Refer to the H754 voltage
regulator adjustment procedure.

4-80

BACKPLANE CONNECTORS

P21

ADJUSTMENT
REGULATOR #4

P20

P19

P18

+5V

-5V

ADJUSTMENT
(REGULATOR #2)

+20V
ADJUSTMENT

(REGULATOR #3)

+20V
ADJUSTMENT

{REGULATOR #1)
7501-10

Figure 4-51

Regulator Adjustments

4-81

Correct power system voltages at the backplane are critical to a properly operating system. If a voltage
regulator cannot be adjusted to meet the required tolerance, check for a faulty regulator or harness.
The regulator replacement procedure is described in Paragraph 4.5.2.3.
H'754 Voltage Regulator Adjustment (+20 V, -5 V)
L.

Power down the equipment.

Fully extend the memory frame from the rack, ensuring that the cables do not bind.
Refer to Figure 4-53. Pull the chassis slide operating handle to release the slide latch. Carefully rotate the memory frame 90 degrees to the upright position.
Power up the equipment.

Connect a digital voltmeter across the +20 V and -5 V test points (M 8149) of the H754, i.e.,
TP3 and 5 or TP4 and 6.

Adjust the +20 V potentiometer (Figure 4-51) for a +25 V reading.
Connect the digital voltmeter between the -5 V and ground test points on the M8149, i.e.,
TPS5 and 7 or TP6 and 7.
Adjust the -5 V potentiometer for -5 V. This procedure is necessary because the 4-20 V
potentiometer (R17) actually sets the overall output of the regulator (25 V from +20 V to -5
V), while the -5 V adjustment (R21) controls the -5 V to ground output. (See Drawing DCS-H754-0-1.)
9.

Recheck the voltages at the M8149 test points, and if necessary, readjust the outputs.

10.

Power down the equipment.

11.

Return the memory frame to its original horizontal position (steps 2 and 3 above in reverse)
or perform the +5 V adjustment described below (steps 3, 4, 5, and 6).

H'744 Voltage Regulator Adjustment (+5 V)
1.

Perform the procedure described above in steps 1, 2, and 3 of the H754 voltage regulator
adjustment.
Power up the equipment.

Using a digital voltmeter, measure the +5 Vdc output voltages under normal load conditions at the M8149 test points (Table 4-17).

Adjust voltages (Figure 4-51) at the backplane to the tolerances specified in Table 4-18 as
required.
Power down the equipment.

4-82

Pull the chassis slide operating handle to release the slide latch. Carefully rotate the memory
frame down to the horizontal position.

Carefully push the memory frame back into the cabinet, observing that the cables do not
bind.
H7441 Voltage Regulator Adjustment, +5 V

Using a digital voltmeter, measure the voltage at J18 pin 1 or J21 pin 7 under normal load

conditions.

Adjust the voltage to +5 V; see Figure 4-52 for location of adjustment potentiometer.

If the voltage cannot be adjusted to +5 V, check for faulty regulator or harness.
7014251 Voltage Regulator Adjustment, =12 VB and +5 VB

Using a digital voltmeter, measure the voltage of +5 VB (A) at the backplane under normal

load conditions. Figure 4-45 shows the backplane pin connections.

Adjust the voltage to +5 V; see Figure 4-52 for the location of the adjustment potentiometer.

Measure the voltage of +12 VB (A) and -12 VB (A).

Repeat Steps 1-3 for the +5 VB (B), £12 VB (B) and +5 VB (C), £12 VB (C) voltages.

If the +5 VB voltages cannot be adjusted to +5 V or if the £12 VB voltages are out of tolerance, check
for faulty regulators or harness.

4.5.2.3 Memory Power Supply Fault Isolation - The memory frame power supply consists of field
replaceable modules. Once a power system failure is discovered, the following steps and associated
flowchart (Figure 4-46) can be utilized to isolate to a faulty module:
1.

Ensure that the power supply is plugged in and getting primary ac power (115 Vac/230 Vac).

Check CBI1 on the ac input box.
Check the fans for proper operation.

Check the two LEDs on the 5411086-Y
A power line monitor. Both can be seen through the
vent slots on the ac input box (Figure 4-29). They should be ON during normal operation,
i.e., AC LO and DC LO not asserted (Paragraph 4.4.6.1).

Utilizing the flowchart (Figure 4-54) and power system schematic (drawing 7010694-0-0),
isolate the faulty module.

‘

Replace the module as described in Paragraph 4.5.2.4.

When a fault is isolated to a voltage regulator, refer to Paragraph 4.5.2.2 for voltage regulator checks and adjustments.

4-83

BACKPLANE

(21920019, 1g.

SCREW HINGE

REGULATOR
MOUNTING

SCREWS

(DO NOT REMOVE)

REGULATOR

MOUNTING
SCREWS

+5VB & + 12 VB

ADJUSTMENTS

AC INPUT BOX
MOUNTING SCREWS

+5 VB & £12 VB ADJUSTMENT
+6 VB ADJUSTMENT
MA-1638

Figure 4-52

MKI11 Power Supply in Maintenance Position

4-84

SCREW
HINGE

(DO NOT

TF&PM%‘:I‘;E;‘

REMOVE)

POWER

SYSTEM
SCREWS

CHASSIS SLIDE
OPERATING
HANDLE

7501-6

Figure 4-53

Power Supply Access (Main Memory Bus

Cables Not Shown)

4-85

CHECK REGULATOR

FAILURE MOST

LIGHTS*
ALL

REGULATOR
OUTPUTS

MEASURE REGULATO
VOLTAGES AT BACKPLANE PER TABLES

BAD

4-17 AND 4-18

AT AC INPUT BOX
BOX SET CB1TO
ALL

LIKELY IN REGULATOR, TRANSFORMER ASSEMBLY,

POWER HARNESS,
OR LOAD. ISOLATE
BY CHECKING REGULATOR INPUT AND
OUTPUT.

OFF

REGULATOR
VOLTAGES

CORRECT

AT AC INPUT BOX
DISCONNECT P5

YES

FROM J5

CHECK FOR

FAULTY WIRING

TO BACKPLANE

SET CB1 TO ON

!
MEASURE LINE

VOLTAGE 1156 VAC
OR 230 VAC AT J5

CHECK THE FOLLOWING
LINE
VOLTAGE

* REGULATOR LIGHTS ARE LIT DURING
NORMAL OPERATION. THE 7014251

PRESENT

REGULATORS DO NOT HAVE INDICATOR
LIGHTS.

FOR A FAULT:
1. AC INPUT BOX

NO 2. THERMAL SWITCH ON

TRANSFORMER
ASSEMBLY
PINS 1 & 3 OF J3ON AC
INPUT BOX JUMPERED.

CHECK FOR FAULTY
TRANSFORMER

ASSEMBLY
TK-1790

Figure 4-54

Memory Frame Power Supply Fault
Isolation Flowchart
4-86

Voltage Regulator Troubleshooting - The voltage regulators are designed to be replaced when a failure
is detected. However, there are unique situations when a regulator must be repaired in the field. Table
4-20 lists the primary fault indications, the most probable cause, and corrective action required. This
table should be used in conjunction with the regulator’s theory of operation (Paragraph 4.4.6.2) and
the print set.
Once the repairs have been accomplished or a new regulator is installed (Paragraph 4.5.2.4), refer to
Paragraph 4.5.2.2 for voltage regulator checks and adjustments.

Table 4-20

H744, H754 Voltage Regulator Troubleshooting Chart

Fault Indication

Most Probable Cause

Corrective Action

No output voltage

1. Q2, Q3, Q4 and Q5

Replace regulator or transistor.

2. D5

Replace regulator or diode.

3. D1 (bottom of D1
will appear burnt)

Replace regulator or D1.

4. Faulty crowbar

Replace regulator or transistor.

Q6 and Q7

5. E1 (DEC 723, IC
voltage regulator)

Replace regulator or El.

6. Misadjusted output
voltage

Shut power off and turn voltage
adjust fully ccw (below crowbar

voltage). Turn power on and
slowly increase voltage (Table 418) until correct value is
obtained.
Blown fuse

1. Q2 (pass transistor)

Replace voltage regulator or pass

transistor

and

associated

components

2. Excessive loading of
voltage regulator

Replace fuse and check loads

Regulator Bench Test Procedures (H744 and H754) - The following paragraphs suggest procedures to
troubleshoot and test the H744 +5 V regulator and H754 +20 V, -5 V regulator modules. The procedures are intended to aid in locating a fault, provided the fault has not destroyed the etched circuits.
When replacing a faulty voltage regulator, the new voltage regulator may need adjustment to com-

pensate for the load. If the new regulator is initially adjusted too high, it may activate the crowbar

circuit and provide no output when initially installed. If this happens, turn power off and rotate the
adjustment potentiometer counterclockwise. Then reapply power (regulator should not crowbar) and
adjust the regulator output.

4-87

Initial Tests - When a power system fault has been isolated to a voltage regulator (H744 or H754),
examine internal fuse F1 (Figure 4-45). A blown fuse usually indicates that the main pass transistor Q2
and/or one of its drivers Q3 or Q4, has short-circuited.
1.

Check for constantly tripped crowbar SCR. (V out = +1 to +1.5 Vdc and regulator *“sings”
too loud.)

Check for damage to base-emitter bleeder resistors and a scorched etched board in the area
of Q3 (and Q4 if applicable).

If the pass transistor and drivers check OK on a VOM, the fault may be caused by continuous base drive to the first driver, Q4 (Q3 in H754). Check level shifter Q5 for a short circuit.
Check DS for a short. A shorted D5 will usually destroy Q2, Q3, and Q4. Consequently, if
the latter are bad, check D5 before powering up.

Check the resistance to ground at the input to precision voltage regulator integrated circuit
E1l (pins 4 and 5) to determine if an external short circuit is affecting the 1C.

Use the VOM to check for a short circuit between fuse terminals and ground. Possible short
circuits involving mounting TO-3 components to the heat sink may be located by connecting
VOM leads between TO-3 cases and a regulator bracket mounting screw on the end of the
heat sink.

Output Short Circuit Tests - A voltage regulator that provides no output or low output without causing fuse F1 to blow, is probably working into a short-circuited output.
NOTE

An activated crowbar or a short-circuited output in
an otherwise properly operating voltage regulator
will not cause K1 to blow.

If fuse F1 is not blown and the area of etched circuit around the ac input to the bridge circuit
is not damaged, it is safe to apply an ac input to the voltage regulator to determine if the
regulator is overloaded by a short circuit across the output.

Connect the voltage regulator to a test bench source (Figure 4-56) and advance the Variac to
about 90 V (20 Vac at voltage regulator input). If the output is near 0 V, turn the voltage
adjustment fully counterclockwise and repeat the test.

If the regulator appears overloaded, check for a short circuit across the output and for a
component failure in the crowbar circuit.

Testing a “Dead” Regulator - Use the following procedure to test a faulty regulator that does not
exhibit the symptoms just described.
1.

Apply 115 Vac to the test bench source (25 Vac at the voltage regulator input), with no load
on the regulator output.

Check for 30 Vdc across filter capacitor C1 (and C2 if applicable).

Check for +15 Vdc at pin 12 of precision voltage regulator E1. No voltage at this point
could mean zener diode D2 (H744) or D3 (H754) has failed.

4-88

Check for 6.8 — 7.5 Vdc at pin 6 of El with respect to ground, pin 7.

If all voltage measurements steps 2, 3, and 4 are OK and there is no output voltage, pin 5 of
E1 should be positive with respect to pin 4.

El, pin 2, should be +0.6 V with respect to pin 3. If it is not, connect the emitter and base of Q5. If a
0.6 V indication is obtained, precision voltage regulator E1 is OK and the fault is probably caused by

Q5 or Q4 (Q3 in H754).

7644-4

Figure 4-55

H744 Regulator Fuse Location

4-89

|
VARIAC

= 90 VAC

& 20 VAC

BENCH

TRANSFORMER

REGULATOR
UNDER

TEST

(NOTE 1)

|
|
|

NOTE1:

H742,H7420,0r H765

power supply can be used.
1-3431

Figure 4-56

H744, H754 Bench Check

Testing a Voltage Regulator After Repairs - Before returning a repaired voltage regulator to service, it
should be checked as follows:
1.

Connect the repaired voltage regulator to the appropriate source connector.

Set the voltage adjustment fully counterclockwise and set the load to zero.
Close the input circuit breaker and advance the Variac until output voltage is indicated (at
approximately 60-80 Vac input). No audible noise should be heard under no-load
conditions.
Be sure Q2 is connected and soldered before loading the regulator.

Advance the Variac to 130 Vac and return to 115 Vac.

Apply a 30-50 percent load. The output voltage should remain nearly constant. A clean
whistle may be heard. A buzz or harsh hissing sound indicates possible instability. Check
waveforms as indicated in Figure 4-57.
Apply 100 percent load and set the voltage adjustment for nominal output as listed:
H744

+5.10 Vdc

H754

+25 Vdc between +20

and -5 outputs
Apply 200 percent load and clock for a decrease in the frequency and the output voltage.

CAUTION
If the output voltage does not decrease noticeably
(approximately 1 V on H744, or 1 to 5 V on the
H754), do not attempt the following short circuit
test.

4-90

9.
10.

Short circuit the output. The regulator should continue to operate at a low frequency with a

clean, smooth whistle and stable waveforms.

Increase the voltage adjustment and observe the output voltage when the crowbar circuit
fires. The output voltage should be within the following ranges:
H744

6.00-6.65V

H754

25.0-30.0 Vand
-6.00to -7.00 V

@—\

+:’>OV——-€Q2 5———1&———""““’\

/—NOTE 1

us
50-200

Vout

QUTPUT NOISE
NOTE 2
__{____

i+
TN

30 volt

level

FULL LOAD

ll Vout —
'

e
NOTE

| mm——

30V

—r —————————

shifts with AC input voltage,

Small 120Hz jitter is normal.

NOTE 2:

Peak noise=1% max.
Measure noise with a short 1008 terminated piece of foil
coax. Normal 10.1 scope probe will not give an accurate

noise

measurement.

Figure 4-57

1-1075

Typical Voltage Regulator Output Waveforms

4.5.2.4 Memory Power Supply Subassembly Removal Procedure - The power supply access procedure
enables the supply to be accessed for adjustments and subassembly removal. The removal procedures
include:

Power supply access procedure

H744, H754, H7441, and 7014251 regulator removal

"AC power input box and 5411086-YA power line monitor board removal

Fan removal

Transformer assembly removal.

4-91

Power Supply Access Procedure
1.

Power down the equipment.

Remove the ac power connection by disconnecting the line cord on the power supply from
the 861 power control.
Fully extend the memory frame from the rack, ensuring that the cables do not bind (Figure

4-53).

Remove the memory frame’s top cover by removing six screws.
Remove the cable clamps by removing four screws.
To remove the top cover of the power supply, loosen the top three screws and remove the
back four screws.

Regulator Removal (Figure 4-58)
1.

Perform the power supply access procedure just described.
CAUTION
Do not remove the power supply hinge screws when
performing the next step.
Remove the two power screws on each side of the power supply (Figure 4-53).

Carefully rotate the memory frame 90 degrees and tilt the power supply (Figure 4-59).
Remove the bottom cover of the memory frame.
WARNING
Power must be removed prior to removing regulators.

Disconnect the Mate-N-Lok from the regulator to be removed.

Remove three screws, two on the top and one on the bottom of the regulator (Figures 4-58
and 4-60).
Rotate the memory frame 90 degrees to the horizontal position.
To remove the regulator, slide it out.
Install a new regulator as described in Paragraph 4.5.2.5.

CAUTION
Use correct length screws when installing a new
regulator.

4-92

£6-v

7501-22

REGULATOR

MOUNTING

(TO BE

SCREWS

REMOVED)

TRANSFORMER

REGULATOR

ASSEMBLY

MATE-N-LOK

GROUND LUG

Figure 4-58

Regulator Removal

R
irge

—— BACKPLANE

POWER

_~ HARNESSES

MJ11

— MEMORY
FRAME
POWER

SUPPLY

7601-16

Figure 4-59

Power Supply in Maintenance Position

4-94

AC Input Box and 5411086-YA Power Line Monitor Board Removal

Perform the power supply access procedure just described.
CAUTION
Do not remove the power supply hinge screws when
performing the next step.

Remove the two power system screws on each side of the power supply (Figure 4-53).

Carefully rotate the memory frame 90 degrees and tilt the power supply (Figure 4-59).
WARNING

Be sure that ac power is removed prior to removing
the ac input box or 5411086-YA power line monitor
board.

Disconnect all the Mate-N-Loks connected to the ac input box.

Disconnect the card edge connector from the 5411086-Y
A power line monitor board.
CAUTION

Hold the ac input box in place while performing the
next step.

Remove three screws and slide out the ac input box (Figure 4-60).

Remove 5411086-YA power line monitor board from the ac input box.

Fan Removal

Perform the power supply access procedure just described.
NOTE

The memory frame should be in a horizontal position
when removing fans.
WARNING
Ensure ac power is removed.

Remove all modules.

On the module side of the fan, remove the two screws holding the fan.

Slide the fan up and out of the power supply chassis and disconnect the jack (Figure 4-61)
from the fan.
CAUTION
When installing the fan, do not tighten the screws
beyond 10 in/Ib. Tightening screws beyond 10 in/1b
may cause the fan to bind.

4-95

AC INPUT BOX
MOUNTING SCREWS

AC INPUT

CIRCUIT BREAKER

BOX

A inndwin A

L
REGULATOR

REGULATOR

MOUNTING

AC LINE

MOUNTING

SCREWS

CORD

SCREWS

Figure 4-60

7111-41

Memory Frame Power Supply

Transformer Assembly Removal
WARNING
Remove ac power before performing this procedure.
1.

Remove all four regulators per previous directions.

Remove the ac input box. Refer to previous directions.

Remove both fans. Refer to previous directions.

Disconnect the transformer assembly’s Mate-N-Loks.

Remove both screws from the transformer assembly’s cable clamp (Figure 4-62, sheet 1).

Rotate the memory frame to the horizontal position.

Remove the transformer assembly’s four mounting screws and nuts (Figure 4-62, sheet 2)
and lift out the transformer assembly.

4-96

PR
eR

BOX FAN

ee e B

S
R R

FAN JACK

TRANSFORMER

et
E Rty
S
A s

ARSI
g

BOX FAN

7501-30

Figure 4-61

Fan Removal

4-97

TRANSFORMER

ASSEMBLY

7501-35

CABLE CLAMP
MOUNTING SCREWS

Figure 4-62

Transformer Assembly Removal (Sheet 1 of 2)

4-98

'AC INPUT BOX OPENING

TRANSFORMER

(AC INPUT BOX REMOVED)

(LOCATED INSIDE BOX)

7111-11

TRANSFORMER ASSEMBLY
MOUNTING SCREWS

Figure 4-62

Transformer Assembly Removal (Sheet 2 of 2)

4-99

4.5.2.5

Regulator Installation Procedure — The following steps describe the procedure for installing

the regulators.

Verify that power to the power supply is off.

Install the regulator. (Refer to Figures 4-58 and 4-60 for mounting screw locations.)
CAUTION
Use correct length screws when installing a new
regulator.

Connect the regulator Mate-N-Lok to the installed regulator.

Turn on power to the regulator.
NOTE
If the regulator crowbars, turn power off and rotate
the regulator voltage adjustment potentiometer fully
counterclockwise (below crowbar voltage). Turn on
power.

Using a DVM, measure the voltage(s) at the M8149 test point(s) (Paragraph 4.5.2) or at the
backplane to ensure that the voltage(s) is(are) within limits specified in Table 4-19. Adjust
voltage(s) if necessary (Paragraph 4.5.2.2).

Recheck the regulator voltage(s) at the backplane per Tables 4-17, 4-18, and 4-19. Adjust
voltage(s) if necessary.

Turn off power and attach the bottom cover of the memory frame. Carefully rotate the
memory frame to the horizontal position.

Install the two power system screws (Figure 4-53) and attach the top cover. Carefully push
the frame back into the cabinet; be careful that the cables do not bind.

4.5.3 H7420 Power Supply
The following paragraphs describe the preventive and corrective maintenance procedures for the
H7420 processor power supply.

4.5.3.1 Preventive Maintenance — The preventive maintenance philosophy for the MJ11 power supply, stated in Paragraph 4.5.2.1, is also applicable to the H7420, preventive maintenance (PM) of the
H7420, consisting of periodic visual inspections and voltage measurements, help anticipate future
equipment failures. The PDP-11/70 PM procedures, including those for the power system, are included in Appendix G; the listed PM schedule should be adhered to.
Monthly Field Service PM procedures (Appendix G) include visual inspection of the logic and power
supply fans, cleaning the air filters, and replacing burned out indicators.

Quarterly PM procedures, also listed in Appendix G, include inspections and checks of the PDP-11/70
that are more comprehensive than the monthly procedures: a check of the wiring and etch conditions,
cleaning the air vents and fan housings with a vacuum cleaner, and voltage checks of the regulators
(Table 4-21).

Figure 4-63 is a reproduction of the decals that are attached to the back of the processor box. The
decals indicate where the +5 Vac from each regulator in the two H7420s is applied.

4-100

Table 4-21

Slots
Output

Supplied

H744 +5V
Regulator A

H7420 Voltage Measurements

Measure at CPU

Max Ripple

Backplane Pin

Voltage

Peak-to-Peak

2-5

F02A2

+5V

0.2Vdc

H744 +5V

1,6-9

F09A2

+5V

0.2 Vde

H744 +5V
Regulator C

10-15

F15A2

+5V

0.2 Vdc

H744 +5V
Regulator D

36-44

F44A2

+5V

0.2 Vdc

H744 +5V

20-22

F22A2

+5V

0.2Vdc

H744 +5V
Regulator J

16-18 and
the console

F18A2

+5V

0.2 Vdc

H744 +5V
Regulator K

24-28

F28A2

+5V

0.2 Vdc

H744 +5V

29-35

F35A2

+5V

0.2 Vdc

Upper H7420
5411086

BO1B1

+8V +1.2Vdc

0.24 Vdc

Upper H7420
5411086

40-44

El13Al

+15V+1.5Vdec|

045Vdc

Lower H7420
5411086

2,17,

E13B2

-15V+1.5Vdc

0.45 Vdc

Regulator B

Regulator H

Regulator L

25, 27,
29-31,
33-35
37-44

Measure and adjust (if necessary) the regulator voltages according to the instructions listed in Appendix G. (Refer to Paragraph 4.5.3.2 for adjustment procedures). Figure 4-64 shows the locations of the
H744 voltage adjustment screws; the 5411086 voltage adjustment is identified in Figure 4-26. If a
regulator cannot be adjusted to meet specifications, remove and replace the regulator (Paragraph
4.5.3.4 and 4.5.3.5).

A digital voltmeter (Weston Schlumberger DVM Model 4443 or Data Technology Model 21) should
be used for making the regulator voltage measurements. A calibrated oscilloscope may be used if a
DVM is not available. A VOM is useful for making continuity and resistance checks within the power
supply. An oscilloscope is necessary for measuring ripple. (Ripple tolerances are listed in Table 4-21).

4-101

H7420
BULK

7420
REGULATOR
E

REGULATOR
D

REGULATOR
C

REGULATOR
B

REGULATOR
A

+5V

+5V
CENTRAL
PROCESSOR

FLOATING
POINT

RH70 &
SPC

& MEMORY
MANAGEMENT

+5V

+15V TO

CENTRAL
PROCESSOR.
CACHE.
RH70.
& SPC

NOT

+8V TO

USED

MAINT SLOT

AC LOW

+5V TO
+5V 1O
ROWS
ROWS
36.37.38.39.40. | 10.11.12.13.14.15

+5V TO
ROWS
16789

+5v TO
ROWS
2345

41424344

DC LOW

50/60 HZ
SIGNAL TO
CLOCK

11-3285

H7420
BULK

7420
REGULATOR
L

REGULATOR
K

REGULATOR
J

REGULATOR
H

+5V
RH70

+5V
CACHE
CONSOLE

+5V
CACHE

REGULATOR
F

-15V TO
CENTRAL
PROCESSOR.
CACHE.
RH70.
& SPC

NOT
USED
AC LOW

+5V TO
ROWS
29.30.31.32.
333435

+5V TO
ROWS
2425262728

+5V TO
ROWS
16.17.18

+5V TO
ROWS
20.2122

DC LOW

11-3286

Figure 4-63

H7420 Decals

4-102

,: i/
.

hrak
g4 258

7301-2

Figure 4-64

H744 Regulator Voltage Adjustment

Visual Inspection

CAUTION
Make sure all power is off before performing the following steps.

Check all fans to ensure that they are not obstructed in any way. Clean air filters mounted
on the inside of t he cabinet door if required.

Visually inspect the modules and backplane for broken wires, connectors, or other obvious
defects.

Inspect all wiring and cables for cuts, breaks, frays, deterioration, kinks, strain, and
mechanical security. Repair or replace any defective wiring or cable covering.

Inspect the following for mechanical security: power supply regulators, fans, capacitors, etc.
Tighten or replace as required.

Inspect power supply capacitors for leaks, bulges, or discoloration. Replace as required.

4-103

4.5.3.2

H7420 Corrective Maintenance — Prior to making any adjustment, the H7420 power supply

should be inspected to ensure that the equipment is energized.

Check that the processor cabinet 861 power control indicators light (Figure 4-46 and 4-47).

Check that all fans are energized.

Check that all regulator indicators light. The indicators are directly below the voltage ad-

justment screws (Figure 4-63) and are on during normal operation.

Voltage Regulator Adjustments — The H744 voltage regulator outputs (Table 4-17) must be adjusted to
the tolerances indicated in Table 4-19. When performing the adjustments, ensure that the maximum

voltages at the regulator are not exceeded. These voltages represent the maximum regulator voltage
prior to crowbar. Figure 4-64 shows the location of the voltage regulator adjustment potentiometers.

Correct power system voltages at the backplane are critical to a properly operating system. If a voltage
regulator cannot be adjusted to meet the required tolerance, check for a faulty regulator or harness.
The regulator replacement procedure is described in Paragraphs 4.5.3.4 and 4.5.3.5.
H744 Voltage Regulator Adjustment (+5 V)

Power down the equipment.

Fully extend the processor frame from the rack, ensuring that the cables do not bind.

Power up the equipment.

Using a digital voltmeter, or a calibrated oscilloscope, measure the +5 V outputs at the
processor backplane (Table 4-21). Adjust these voltages to +5 Vac £ 250 mV. The adjustment screws are identified in Figure 4-64.

Power down the equipment.

Carefully push the processor frame back into the cabinet, observing that the cables do not

bind.

4.5.3.3 H7420 Power Supply Fault Isolation - If a power system fault is suspected, visually inspect the
system components for obvious fault indications. For example, each of the voltage regulator modules
is provided with an output indicator lamp that lights when the output voltage is within range. If a
single indicator lamp within the group (A-D or H-L) is not lit, the fault is probably within that voltage
regulator module. This can be verified by swapping H744 modules. Once the fault has been isclated to
a voltage regulator module, refer to the voltage regulator checkout procedure described in Paragraph
4.5.2.3. A decal (Figure 4-63) is placed on the rear of the processor rack chassis to indicate the location
and function of each voltage regulator.

If none of the voltage regulator output indicator lamps in the group are lit, the fault is probably in the
associated H7420 power supply or 861 power control. Visually inspect the power indicator lamps and
circuit breakers provided with these devices to determine whether the fault can be isolated to either the
H7420 or the power control. Figures 4-12, 4-24, 4-27, and 4-47 show where these indicator lamps and
circuit breakers are located in each device. Figures 4-26 and 4-65 show the internal components of the
H7420. A description of the 861 power control is given in Paragraph 4.3.5.

4-104

!
|

POWER

CORD

|
|

|
POWER
I
INDICATOR
!
!

!
TRANSFORMER T1

TERMINAL

T81

7A SLO BLO FUSE F1
(TO 5411086)

2
FAN

BLOCK

\\\

J)T~

PC MOUNTING

BOARD BRACKET

5411086
REGULATOR
8

LINE MONITOR

FAN POWER

CABLE

Figure 4 65

ASSY

11-3309

H7420 Power Supply Component Identification

4-105

The following steps can be used to aid in locating the cause of a power system failure:
1.

Ensure that the H7420 is plugged in and getting primary power (115/230 Vac) from the 861
power control.

Check the power indicator and circuit breaker CB1 on the H7420 (Figure 4-27).

Check the individual regulator lights. (Regulator lights are lit during normal operation.)

Check the two LEDs on the 5411086 power line monitor (Figure 4-26). They should be on

during normal operation, i.e., AC LO and DC LO are not asserted (Paragraph 4.4.6.1). The
first two steps of the 5411086 removal procedure (Paragraph 4.5.3.4) must be performed in
order to view the two indicators.
5.

Measure regulator voltages at the processor backplane (Paragraph 4.5.3 and Table 4-21).

If all regulator outputs are within specifications, check the backplane for faulty wiring.

If one or more regulator outputs are incorrect, check the regulator fuse(s) (Figure 4-55), the
transformer assembly, the power harness connections and the load.

Ifthe +8 V, =15V, or +15 V outputs are incorrect, check the 5411086 power line monitor.
(Fuse locations are shown in Figure 4-26).

If the fault is isolated to a voltage regulator, refer to Paragraphs 4.5.2.3 and 4.5.3.2 for
regulator troubleshooting and adjustment procedures. Table 4-20 lists several possible problem causes and their solution.

H744 regulator bench test procedures are described in Paragraph 4.5.2.3.
4.5.3.4 H7420 Power Supply Subassembly Removal Procedure - The power supply access procedure
enables the supply to be accessed for adjustments and subassembly removal. The procedures listed
below are described in the following paragraphs:
1.

Power supply access procedure

H744 Regulator removal

5411086 15 V regulator/power line monitor board removal

Power Supply Access Procedure
1.

Power down the equipment.

Fully extend the processor frame from the rack, ensuring that the cables do not bind (Figure
4-17 and 4-18).
3.

Remove the ac power connection by disconnecting the H7420 power cord (Figure 4-27)
from the 861 power control.
CAUTION
Since both H7420s are connected to the same 861
(Figure 4-7), make certain that the correct H7420

power cord is disconnected.

4-106

H744 Regulator Removal

Perform the power supply access procedure just described.
WARNING

Power must be removed prior to removing regulators.

Disconnect the Mate-N-Lok connector from the regulator to be removed.

Remove the two screws and lockwashers that fasten the top of the regulator to the H7420
(Figure 4-66, sheet 1 of 2). Loosen, but do not remove, the knurled screw that fastens the
bottom of the regulator to the H7420.

Slide the regulator out of the H7420 (Figure 4-66, sheet 2 of 2).

Install a new regulator as described in Paragraph 4.5.3.5.

5411086 15 V Regulator/Power Line Monitor Board Removal

Perform the power supply access procedures just described.
WARNING

Power must be removed prior to removing the
5410086 board.

Remove the two screws at the top of the PC mounting board bracket (Figure 4-67, sheet 1 of
3). The bracket then swings down from the top and remains suspended from the bottom

edge.

3.
4.

Remove the two hex nuts from the end of the 5411086 board (Figure 4-67, sheet 2 of 3). Do

not lose the attached hardware (screws, washers, and spacers).

Remove the 5411086 board from the PC mounting board bracket. This is accomplished by
carefully pulling the board to separate the edge connector on the board from J1 (Figure 467, sheet 3 of 3).

5.
4.5.3.5

Install a new 5411086 board as described in Paragraph 4.5.3.5.
H?7420 Power Supply Subassembly Installation Procedure

H744 Regulator Installation —-The following steps describe the procedure for installing H744 regulators
in the H7420.

Perform the power supply access procedure (Paragraph 4.5.3.4).
WARNING

Power

must be removed prior

regulators.

4-107

to installing

Place the H744 regulator in the correct position in the H7420. Tighten the knurled screw on
the bottom of the H7420.

Fasten the top of the H744 to the H7420 with two screws and lock washers.

Connect the Mate-N-Lok connector (in the power harness) for this regulator position to the
connector on the top of the regulator.

Turn on power and measure the regulator voltage at the processor backplane (Paragraph
4.5.3.1). Adjust the voltage (Paragraph 4.5.3.2) if the measured voltage is not within the
tolerances listed in Table 4-19.

5411086 15 V Regulator/Power Line Monitor Board

Perform the power supply access and 5411086 removal procedures (Paragraph 4.5.3.4).
WARNING

Power

must be
5411086 board.

removed

prior

installing

the

Connect the edge connector on the 5411086 to J1 (Figure 4-67).

Fasten the opposite end of the board to the PC mounting board bracket with the necessary
hardware (screws, washers, spacers, and hex nuts).

Attach the top of the PC mounting board to the H7420 chassis with two screws and washers.

Turn on power and check the backplane voltages (upper H7420: +15 V and +8 V: lower
H7420: -15 V). Refer to Paragraphs 4.5.3.1 and 4.5.3.2 for 5411086 voltage check and
adjustment procedures.

Power down the equipment.

Carefully push the processor frame into the cabinet, observing that the cables do not bind.

4-108

7644-8

Figure 4-66

H7420 Regulator Removal (Sheet 1 of 2)

4-109

7644-2

Figure 4-66

H7420 Regulator Removal (Sheet 2 of 2)

4-110

REMOVE

7545-22

Figure 4-67

5411086 Removal (H7420) (Sheet 1 of 3)

4-111

REMOVE

Figure 4-67

5411086 Removal (H7420) (Sheet 2 of 3)

4-112

7545-25

Figure 4-67

5411086 Removal (H7420) (Sheet 3 of 3)

4-113

CHAPTER 3§
MAINTENANCE

By use of on-line diagnostics, DEC/X11 or the PDP-11/70 subsystem diagnostic, system faults can be
isolated to the appropriate subsystem; i.e., CPU, cache, memory management, Unibus map, Unibus

device, main memory, Massbus controller or Massbus device.
Once the failing subsystem has been identified, the individual stand-alone diagnostic is used to locate
the failing module. Once the bad module has been identified, it should be replaced and returned to the
Maynard or European Depots for repair. Due to the complexity of the modules and the size (cost) of
the PDP-11/70 systems in general, on-site component level repair of modules is discouraged. Component level repair should only be used as a back-up strategy or whenever the fault is obvious and can
be repaired quickly.
Cold start maintenance (being unable to load diagnostics) is made easier by a hardware diagnostic
routine included in the system bootstrap loader (standard on all machines). This loader, the M9301YC, YH or M9312, contains 512 words, of which 256 words are used for diagnostic routines. The
listing of the program stored in the M9301-YC (DEKBH), M9301-YH and M9312 are supplied at the
end of this chapter (Paragraph 5.4.11); they contain detailed documentation to aid in troubleshooting
a defective machine.
Basically the routines check the instructions used by the loader for loading programs and the first 28K
of memory (basic address test). It also does a basic check of memory management and a basic check of
the Unibus map. There are no routines in the diagnostic boot for checking the loading device. A paper
tape diagnostic is supplied for this purpose. In addition to the bootstrap diagnostic, cold start maintenance is aided by the ability to eliminate the cache partially by forcing misses in half or all of the cache
as well as forcing selection (upon word replacement) to a specific group.

System maintenance on the PDP-11/70 is enhanced by various registers and indicators (Paragraphs
5.3.1 and 5.3.2) within the CPU (Paragraph 5.3.1.1) and Massbus controllers as well as a ““maintenance
mode” of operation within each Massbus controller to allow complete checking of the RH70 data
buffer. System problems are also aided by various bits within the parity registers (outline following)
which enable one to find out easily where parity errors actually occurred, i.e., Unibus operations, CPU
abort, memory bus timeouts, etc.

Memory system maintainability is improved because of the extensive use of parity throughout the
memory system. Memory system failures are easily isolated because of six error registers which retain
information on where the error occurred in addition to providing means of verifying the parity checkers and margining main memory.

5-1

The error registers are as follows:
1.

Lo Error Address Register - Provides lower 16 bits of the 22-bit address where the parity
error occurred.

Hi Error Address Register - Provides upper 6 bits of the 22-bit address as well as the cycle
type which was being done, i.e., DATI, DATO, etc.
Error Register — Tells where the error actually occurred, i.e., lower word main memory,
main memory bus, etc.

Control Register - Allows for the disabling of parity traps, forcing of cycles to bypass the
cache or go to a specific group within the cache, etc.

Maintenance Register - Allows for margining of main memory currents and strobe, as well
as forcing wrong parity checks.

Hit/Miss Register — This register tracks each processor cycle whether it was a hit (word
present in cache memory) or a miss (word had to be obtained from slow memory).
Error indicators are easily checked by opening the memory cabinet front door. Indicators are present
for incorrectly configured memory systems, memory address parity errors, and hung memory
controllers.

The basic tools required for maintenance and repair of the PDP-11/70 system are listed in Table 5-1.
This chapter describes the maintenance aids available to Field Service personnel for diagnosis and
repair of a defective system:
1.

Guidelines for PDP-11/70 troubleshooting (Paragraph 5.1)

Basic checkout of a dead machine (Paragraph 5.2).

Troubleshooting aids (Paragraph 5.3), which include the system registers, indicators switches, and the maintenance module
A description of the PDP-11/70 diagnostic (Paragraph 5.4).

5-2

Table 5-1

Maintenance Equipment Required

Model, Type or

Equipment or Tool

Manufacturer

Part No.

Oscilloscope -

Tektronix

453

Digital Voltmeter (DVM)

Weston (or the like)

6000

Volt/Ohmmeter (VOM)

Triplett

Unwrapping Tool

Gardner-Denver

DEC Part No

29-13510
505 244-475

29-18387

A-20557-29

29-18301

29-13460

(DEC Catalog #H812A)
Hand Wrap Tool

Gardner-Denver

(DEC Catalog #H811A)
Diagonal Cutters

Utica

47-4

Diagonal Cutters

Utica

466-4 (modified) | 29-19551

Miniature Needle Nose Pliers

Utica

23-4-1/2

29-13462

Wire Strippers

Millers

101S

29-13467

Solder Extractor

Solder Pullit

Standard

29-13451

Soldering Iron (30W)

Paragon

615

29-13452

Soldering Iron Tip

Paragon

605

29-19333

16-Pin IC Clip

AP Incorporated

AP923700

29-10246

24-Pin IC Clip

AP Incorporated

AP923714

29-19556

Maintenance Cards

DEC

W131,W133**

Maintenance Card Overlay

DEC

5509974-0-1

Module Extender Boards (3)

DEC

W900

* Tektronix type 453 oscilloscope is adequate for most test procedures: type 454, or equivalent, may be required

for some measurements.

** W133 is a dual version of W130. It provides the drivers for two W131 maintenance cards.

5.1

SYSTEM TROUBLESHOOTING

This paragraph describes typical procedures used when attempting to isolate a failure in a PDP-11/70
system. It is not intended as a method to be used for all types of failures, but rather as a guideline.
Refer to Figure 5-1: This flowchart points to the available maintenance aids, and thus may be used as a

guide for troubleshooting a defective PDP-11/70.
5.1.1

Dead Machine

5.1.2

System Repair

This is cold start troubleshooting. Refer to Paragraph 5.2.

If the console functions work, attempt to bootstrap the XXDP monitor. If the bootstrap is successful,
run the subsystem diagnostic. This program analyzes errors and points to the area of the system that is
causing the primary trouble. Run the appropriate PDP-11/70 diagnostic, repair, and run the subsystem diagnostic again. If no errors are indicated, run DEC/X11 configured for the whole system,
then the appropriate software exerciser. If no errors (within the limits set in the PDP-11 Family Installation and Acceptance Procedure) occur, the system should be good. If errors occur at any point in this
series of tests, repair before proceeding.

If the bootstrap does not work (no message from XXDP), one of several conditions may occur:
1.

The bootstrap halts at a location within its diagnostic. Refer to the diagnostic listing (Paragraph 5.12) to locate the defective instruction and repair. Use of the maintenance module
and the KB11-B flowcharts may be indicated at this time.

The machine goes into a loop. Press the HALT switch and examine the PC. Also examine
the PC if an unscheduled halt occurs and no parity error is indicated. If the PC contains a
meaningless address, load all vector addresses with their own address plus 2, and the vector
plus 2 with 0. Bootstrap again. The halt will then occur in the vector area, at address vector
plus 4. Examination of the appropriate registers should then enable the field service engineer
to start troubleshooting the appropriate area of the system. Examination of the various
troubleshooting aids (indicators and test points) may save time at this point. The vectors
that may be loaded are the following plus the vectors used by the Unibus devices installed on
the system:
004

CPU errors

010

Illegal and reserved instructions

014
020
024
030
034
240
244

BPT, breakpoint trap
IOT, input/output trap
Power Fail
EMT, emulator trap
TRAP instruction
PIRQ, Program Interrupt Request
Floating Point Error

250

Memory Management

Refer to Paragraph 5.3 for a description of the PDP-11/70 registers, and troubleshooting
aids.

FROM

FIG. 5-2

:l‘:
r

START

)

|
|

REPAIR
LB

]

___
J 1

(WounT xxoP MEDTOM

(

GRS

BOOT M9301/M9312

GAED

LONDRIVED.

LoapADDRESs

| SET CONS. sw. REG. |

| DEPREsssTART

CHECK ADRS. WITH

CXDP

MEDIUM
ON DRIVE
0

vES

HALT

WITHIN
DIAGNOSTIC

‘

“CONS PHY"' SW

VES

17 765 000-

| 17 765 776
OR
17 773 600-

(1|ZA7FZ357Z61 )

MACHINE

REFER TO
FIGURE 39

HALT
XXDP

CPARAGRAPH 52

MESSAGE

)

ON LA36

YES

LOOP

REFER TO XXDP

MANUAL

Y
2

CONSOLE

BOOTSTRAP
IS

LITE

SUCCESSFUL

FIG. 5-2

VES

PARITY

+»|

CHECK MEMORY
REGISTERS

(PAR. 5.3.1.4)

I no

RUN SUB-SYSTEM
DIAGNOSTIC

REPAIR

(DXSSA?)

(PAR.5.4.8)

]

EXAMINE

SYSTEM

RUN 11/70
STAND ALONE

DIAGNOSTIC(S)

AS REQUIRED

| NO

CHECK

INDICATORS

CPU REGS.

LOAD VECTORS

TEST POINTS

WITH V +2, AND

(PAR.5.3.1.1)

& REGISTERS
(PAR.5.3.1

(PAR.5.4.3

V +2 WITH 0.

& 5.3.2)

THRU 5.4.6

REFER TO

DEC/X11

MANUAL

RUN

DEC/X11

REFER TO
PO
ROPRIATE

SOFTWARE

EXERCISER

MANUAL

EXERCISES

(IF AVAILABLE)

!
o

TRY LOADING

DIAGNOSTICS

USE TOGGLE

BOOTSTRAP

(PAR. 5.1.3)

LOAD DEV

W/TOGGLE

TAPE DIAG.

(XXDP CARD)

W/PAPER

ROUTINES

YES

YES
TK-1464

Figure 5-1

Guidelines for PDP-11/70 Troubleshooting

5-5

The machine halts with the Parity Console Indicator ON. Examine the Cache Error register

If the memory system is not working at all, the toggle-in routines, which use the PARS

It is of course possible that the ROM in the M9301 or M9312 is defective. This may be
checked by examining the suspected locations from the conscle, if no spare MQ10! or
M9312 is available. Listings of the ROM programs on the M9301-YC (DEKBH) M930iYH and M9312 are reproduced in Paragraph 5.4.11. Operating procedures for the M930!

and the other Cache registers (Paragraph 5.3.1.4).

instead of memory, may help (Paragraph 5.1.3).

and M9312 are given in Paragraph 3.4.2.

The XXDP-DEC/X11 program card lists toggle-in loaders for all XXDP media; this

If a defective load medium device is suspected, and it is not convenient to change devices (it
must be drive 0), a paper tape diagnostic is supplied to check this device. If no paper tape

method of booting diagnostics may also be tried.

device is available at the site, a PMKO1 should be used.
5.1.3

Toggle-in Routines

A few ideas that should aid in debugging failures in the cache memory of the PDP-11/70 are presented
here. Many failures in this unit prohibit the normal troubleshooting technique of using standard diagnostics to isolate problems. This is because the cache in the PDP-11/70 is very much a part of the
system hard core. Even a minor failure in this area could mean that the diagnostics could not be run
because main memory may not be accessible from the processor. For these situations, the use of an
alternate storage for short toggle-in routines is suggested: the memory management PARs.

The troubleshooter of course should attempt to run the standard PDP-11/70 diagnostics before
attempting to use the methods that are outlined here. If these will not load or run properly, then the
user should try to load and run them with the cache disabled, that is: forcing misses to both cache
groups by depositing 14 (8) in the Cache Control register, 17 777 746.
NOTE

The Cache Control register is cleared by a console
START as well as by a power-up. Therefore, it is
necessary to use the CONTINUE switch instead of
the START switch when using this procedure.

In this way two of the four modules in the cache memory unit can be turned off effectively. These are
the cache address memory board, M8143, and the cache data memory board, M8144. There is no way
to disable the logic on the other two boards, the cache control board (M8142), or the cache data paths
board (M8145).

The memory management PARs are 16-bit registers which can, with a little programming skill, be used
easily to store short routines to check much of the logic anywhere in the PDP-11/70 system. Suggestions will be given here for toggling in cache tests.

5-6

Before toggling in a routine, the troubleshooter should try to isolate the problem first to either the
address paths and control or the data paths and control. This can usually be done using the console.
For example, a good way to check out most of the address paths is to examine the Cache Error
Address register (17 777 740 and 17 777 742). This register is toggled every time a cycle is executed. It
thus contains the address being referenced anytime a reference is made: When the register itself is
examined twice, it should contain its own address on the second EXAMINE. This is an easy way to
ensure that the address multiplexer on the ADM (M8143) board can pass ones and that the address
paths themselves can go to one. Another good way to isolate a problem to a subcomponent is to use
the Cache Error register, which should indicate the source of any parity error. If the Error register
indicates an address memory error, an address test should be run, etc.

If the troublshooter cannot isolate the failure from the console, he/she can pick routines that he/she
thinks most general (or use one that was written by oneself).
As a simple example, consider the case in which it has been discovered that writing and reading data
from a particular cache group (say group zero) will result in a parity error. Toggling the following
routine into the KIPARs should be a great help in isolating the problem with or without the use of an
oscilloscope:

Address

Data

Mnemonic

17772340
17772342
17772344
17772346
17772350
17772352
17772354
17772356
17772360
17772362
17772364
17772366
17772370
17772372
17772374

012737
172350
000114
005003
012706
000500
005203
010337
177570
013701
177570
010110
021001
001366
000772

MOV

#18,@#114

CLR
MOV

R3
#500,SP

INC
MOV

R3
R3,@#SWR

MOV

@#SWR,R1

MOV

R1,(RO)
CMP (RO),R1
1$
2%

18$:

28$:

BNE
BR

This routine will move the value constantly in the low order 16 Console Switch register switches to the
address in RO. It will then compare what is in that location with what was written. If either this
comparison fails or a parity error occurs, the contents of R3, which is displayed in the data lights of the
display register, will be incremented. In this way the user can monitor the failure rate of a particular
pattern, or try different patterns by changing the switches without stopping the program. Note that the
parity traps (if any occur) will be dealt with properly.
As a more general approach which may be useful, the following program is provided. It has no parity
check which eliminates machine halt on a parity error and thus may aid in troubleshooting. This
program will write any pattern throughout memory from 0 to the system size register. It executes from
the supervisor I and D space address registers. Deposit the pattern that you wish to use in R5. If you
wish to clear memory, deposit 0 in RS5.

5-7

17772300
17772316
17772340
17772356
17777700
17777701
17777702
17777703
17777704
17777705
17772240
17772242
17772244
17772246
17772250
17772252
17772254
17772256
17772260
17772262
17772264
17772266
17772270
17772272
17772274

077406
077406
000000
177600
000000
172340
177572
177760
172516
(PATTERN)

012714

MOV #20,(R4)

000020
005212

010520 18:

INC (R2)

MOV RS5,(RO)+

020027
017776
003774
062711
000200
021311

CMP RO,#17776

BLE 1$
ADD #200,(R 1)

005000
000766
005312
000000

CLR RO
BR 1$
DEC (R2)
HALT

CMP (R3),(R1)

003402

BLE 2§

28:

These were only examples. The routines presented are by no means general enough to catch any
failure.
If the troubleshooter has determined the address paths to be the source of a problem which results in a
parity error (or perhaps some addresses cannot be made hits) the following routine could be used:
17772340
17772342
17772344
17772346
17772350
17772352
17772354
17772356
17772360
17772362
17772364
17772366
17772370
17772372
17772374
17772376

012737
172350
000114
005003
012706
000500
005203
010337
177570
013700
177570
021010
006037
177752
103365
000771

28:

MOV

41$,@4114

CLR
MOV

R3
4#500,SP

INC
MOV

R3
R3,@#SWR

MOV

@#SWR,RO

CMP
ROR

(RO),(RO)
@#HITMISREG

BCC
BR

1$
2%

In this test, whatever address is in the Switch register (bits 15 through 0) is referenced and a check is
made to see if that address can be made a hit. If that address was not a hit when it should have been, or
if a parity error occurred, then the contents or R3 will be incremented and shown in the Display
Register Data Indicators.

5-8

Note that this and the preceding routine continually loop and use the contents of the Switch register to
make the test. The Switch register can be changed at any time while the program is running and any
errors are displayed by incrementing the Display register. In spite of the fact that both routines are too
specific to be used in finding a general or completely unknown problem, they are good examples of
what is desirable in a usable toggle in routine.
If the troubleshooter has discovered how to aggravate a particular failure, he should not be afraid to
write and toggle in a short simple routine to help isolate it. Sometimes a simple:
1$:

TST
BR

(RO)
1§

will be of considerable aid when used in conjunction with an oscilloscope, if it is put in the PARs.

Some very general more sophisticated toggle in routines follow. These may be helpful when the source
of a failure is not clear.
Test 1

Data Memory Count Pattern Test

This test runs a count pattern through each cache memory data word. If one of the patterns is not
stored correctly, a parity error will occur and the halt at 116 will be executed. When HALT is executed,
the contents of RO, the address, will be displayed in the Data Paths Display lights. R1 will contain the
last data pattern read from that location. If the routine is unable to make the address a hit, then the
halt at 17 772 364 will be executed. If a parity error occurs, then the troubleshooter should examine the
contents of the Cache Error registers. Note that this routine should be run twice, once for each group.
It should be run first in group zero by forcing misses to group one and forcing selection of group zero
(put 30 in the Cache Control register, 17 777 746), then in group one by forcing misses to group zero
and selection of group one (by putting 44 in the Cache Control register, 17 777 746).

NOTE
The Cache Control register is cleared by a console
START as well as by a power-up. Therefore, it is
necessary to use the CONTINUE switch instead of
the START switch when using this procedure.

The test will run continuously if no errors occur. It can be made to run just one pass by replacing the
last instruction with a halt (000000 at 17 772 376).
SP
00000114
00000116
17772340
17772342
17772344
17772346
17772350
17772352
17772354
17772356
17772360
17772362
17772364
17772366

000500
000116
00000
012700
004000
012702
001000
044010
005310
011001
006037
177752
103401
000000
005110

17772370
17772372
17772374
17772376

005110
001367
077212
000760

1$:

28:
38:

48:

MOV

44000.R0

MOV

4#1000,R2

BIC
DEC
MOV

~(RO),(RO)
(RO)
(RO),R
1

ROR

@#HITMISREG

BCS
HALT
COM

COM
BNE
SOB
BR

(RO)
3$
R2,2$
1$

5-9

(RO)

Test 2

Address Memory Count Pattern Test (Bits A10 Through A15 Test)

This test tries to make every address in the first 28K (addresses 0 through 00 157 776) a hit. It should be
run twice (once in each group) as was outlined in Test 1. If a parity error occurs, the HALT at 116 is
executed and the user should look at the Cache Error registers to see what happened. When the routine
fails to make a particular address a hit, the halt at location 17 772 360 will be executed. If either of
these halts is executed, RO (the address being tested) will be displayed in the Display Register
Indicators.
SP

00000114
00000116
17772340
17772342
17772344
17772346
17772350
17772352
17772354
17772356
17772360
17772362
17772364
Test 3

000500

000116
000000
005000
012701
070000
005710
005720
006037
177752
103401
000000
077107
000765

CRL
MOV

2§:

TST
TST
- ROR
BCS

RO
#70000,R
1

(RO)
(RO)+
@#HITMISREG
3%

HALT
3§:

SOB
BR

R1,2%
1%

Main Memory Dual Addressing Test 0 to 28K

This test runs a dual addressing test through the first 28K of main memory. It writes the address of
each location into each location. Then it returns to check that each location contains its own address.
If the halt at location 17 772 370 is executed, then the test has failed. The address that contained the
bad data is in RO (which is displayed in the data lights of the Display register). The user should then
examine that location to see what the bad data is. This test should be run while forcing misses to both
groups by first depositing 14 into the Cache Control register at 17 777 746.

000500

00000116

000000

17772340

012700

17772342
17772344
17772346

000500
012701
067540

17772350
17772352
17772354
17772356
17772360
17772362
17772364
17772366
17772370
17772372
17772374
17772376

010020
077102
012700
000500
012701
067540
020010
001401
000000
005120
077105
000760

00000114

000116

HALT
18:

28%:

3%:

4%:

MOV

#500,R0

MOV

#67540,R1

MOV
SOB
MOV

RO,(RO)+
R1,2%

MOV

#67540,R
1

CMP
BEQ
HALT
COM
SOB
BR

RO,(RO)
43

5-10

#500,R0

(RO)+
R1,3%
1$

Test 4

Data Memory Dual Addressing Test

This routine performs a dual addressing test on the cache data memory. Each of the locations 2000
through 3776 is made a hit and the address of each location is written into itself. Then the routine goes
back and makes sure each of those locations still contains its own address. If the halt at 17 772 362 is
executed, then there is a dual addressing problem. If the halt at 17 772 370 is executed, then the address
being tested should have been a hit but was not. This test should be run twice; once for each group as
just outlined.
R3
R4
RS
SP

002000
001000
177752
000500

00000114
00000116
17772340
17772342
17772344
17772346
17772350
17772352
17772354
17772356
17772360
17772362
17772364
17772366
17772370
17772372
17772374
17772376

000116
000000
010300
010401
005710
010020
077103
010300
010401
020010
001401
000000
006015
103401
000000
005120
077110
000760

Test 5

18:
28$:

3%:

483:

5%:

HALT
MOV
MOV
TST
MOV
SOB
MOV
MOV
CMP
BEQ
HALT
ROR
BCS
HALT
COM
SOB
BR

R3,R0
R4,R1
(RO)
RO,(RO)+
R1,2%
R3,R0
R4,R1
RO,(RO)
4%
(RS)
53
(RO)+
R1,3%
1$

Main Memory Data Patterns Test

This routine puts data patterns that the user designates in the Switch register in the lower 28K of
memory. Since the program loops, the specified data pattern can be changed as the program runs. The
test should be run while forcing misses to both cache groups (deposit 14 in the Cache Control register
at 17 777 746). If the HALT at 116 is executed, then a parity error occurred with the designated data
pattern at the address in RO. If the HALT at 17 772 366 is executed, then the data read from the
location does not match the data written into it. If either HALT is executed, the address (RO) will be
displayed on the console. A suggested data pattern to put in the Switch register is 125252 or 052525;
000000 and 177777 might also be tried.

5-11

00000114
00000116
17772340
17772342
17772344
17772346
17772350

000500
000116
000000
012700
000500
012701
067540
013703

17772352
17772354
17772356
17772360
17772362
17772364

177570
010310
005110
005110
022003
000401

17772370
17772372

077111
000762

17772366

Test 6

000000

HALT

1$:

28:

38:

MOV

#500,R0

MOV

#067540,R1

MOV

@#SWR,R3

MOV
COM
COM
CMP
BEQ

R3,(R0)
(RO)
(RO)
(RO,+,R3
3§

SOB
BR

R1,2$
1$

HALT

Address Memory Dual Addressing Test

~J O\

OWW
e

N hWhN—ODO

This routine performs a dual addressing test on the cache address memory. This sequence of tags (bits
A10 through A21) is written into the address memory:

This is done by generating the sequence of addresses:
00002000

00002002
00004004
00004006
00006010
00006012
00010014
00010016

5-12

and making each a hit in one group. Then the routine goes back and re-references that same series of
addresses to ensure that they all are still hits. Note how the addresses are made hits: The instruction at
17772 350 (CMP (R0),(R0O)+) is used, but when the routine goes back to check if the addresses are still
hits, that instruction is changed to (CMP R0,(R0)+) by the XOR instruction. Then that instruction is
changed back to (CMP (RO0),(R0)+) by the XOR. This is done so when the addresses are originally
made hits they are referenced twice; but when the routine goes back to see if they are still hits, only one
reference is needed. If the HALT at 17 772 356 is executed, then an address which should have been a
hit was not; the troubleshooter should examine location 17 772 350 to see if the routine was making the
addresses hits for the first time, or if it was going back to ensure that they were all still hits. If the latter
case is true, then three is a dual addressing problem in the address memory. This test should be run
twice, once in each group as outlined in Test 1.
R2
R3

100000
002000

000400

R5
SP
00000114
00000116
17772340
17772342
17772344
17772346
17772350
17772352
17772354
17772356
17772360
17772362
17772364
17772366
17772370
17772372
17772374

177752
001000

Test 7

000116
000000
005000
010401
060300

1$:
28:

040200
021020

3$:

006015

103401
000000
005720

48:
58:

HALT
CLR
MOV
ADD

R3,R0

BIC

R2,R0

RO
R4,R1

CMP

(RO),(R0)+

ROR

(R5)

BCS
HALT
TST

58
(RO)+

006015

ROR

(R5)

103374
077112

BCC
SOB

4%
R1,28

074737
172350
000761

XOR

SP,@#3$

Main Memory Data Pattern Test

This routine can be used to run a data pattern test on any 4K bank of memory. The user specifies
which bank by setting the switches in the Switch register to any 100 (8) word block of memory. For
example: To test addresses 2000 through 22000, put 20 in the Switch register. The routine loops continually so that the Switch register can be changed dynamically to test another memory bank without
restarting the program. The test is run with the data pattern in R4. That pattern is written into every
tested word and complemented twice. Suggested patterns are 125252 or 052525. Note that memory
management is turned on while running this test from the PARs themselves. The user should force
misses to both cache groups to run this test; put 14 in the Cache Control register at 17 777 746. If the
HALT at 116 is executed, then a parity error occurred at the address contained in RO, that is displayed
when the HALT is executed. If the HALT at 17 772 340 is executed, then the data that was read out of
the location being tested did not match the data that was written; the address in RO will be displayed.
Note that this test does not have 17 772 340 as its starting address as do all the other routines. Its
starting address is 17 772 342. Also note that the user should be careful not to specify a test of nonexistent memory that will cause a trap to 4. Any memory up to 2 million words can be checked.

5-13

R2
R4

00000114
00000116
17777572
17772516
17772300
17772306
17772316
17772340
17772342
17772344
17772346
17772350
17772352
17772354
17772356
17772360
17772362
17772364
17772366
17772370
17772372
17772374
17772376

Test 8

010000
125252
000500
000116
000000
000001
000020
077406
077406
077406
000000
013727
177570
000000
012700
060000
000401
177600
010201
010410
005110
005110
020420
001362
077106
000761

THE DATA PATTERN
HALT

1%:
2%:

3%:

HALT
MOV

@#SWR,#000000

MOV

R0
4060000,

.WORD
MOV
MOV
COM
COM
CMP
BNE
SOB
BR

177600
R2,R1
R4,(RO)
(RO)
(RO)
R4,(RO)+
1$
R1,3$
28

Address Memory Hits Test

This routine will check that any address in memory can be made a hit. It checks 4K at a time. The user
specifies which 4K bank is to be tested using the Switch register. The user must specify the 100 (8) word
block number of the starting address of the 4K bank he/she wishes to have tested. For example, if the
user puts 1007 in the switches, addresses 00 100 700 through 00 120 700 will be tested. The routine
loops continually so that the user can dynamically change the specified bank to another. If a parity
error occurs, then the HALT at 116 will be executed. If the halt at 17 772 340 is executed, then the
routine was unable to make the address in RO a hit. The routine should be run twice, once for each
group as outlined in Test 1.

5-14

SP
00000114
00000116
17777572
17772516
17772300
17772306
17772316
17772340
17772342
17772344
17772346
17772350
17772352
17772354
17772356
17772360
17772362
17772364
17772366
17772370
17772372
17772374
17772376

000500
000116
000000
000001
000020
077406
077406
077406
000000

HALT

18:

HALT

2$:

MOV

@#SWR,#000000

MOV

#060000,R0

000401
177600

BR
.WORD

41
177600

012701
010000

MOV

#010000,R
1

CP
ROR

(RO),(RO)+
@#HITMISREG

103362
077105

BCC
SOB

1$
R1,3$

000761

013727
177570

000000

012700
060000

021020
006037
177752

38:

5.2

COLD START TROUBLESHOOTING
,
When a system is inoperative, the first things that should be checked and repaired if necessary include:

AC and dc power and cabling (Chapter 4)

Signal cabling (Paragraph 5.2.2 and Appendix A)

Console functions (Paragraph 5.2.3).

When the console is functioning properly, the diagnostics should be bootstrapped and the system
verified. Refer to Figure 5-1.
The flowchart shown on Figure 5-2 suggests some steps that could be taken to bring a dead machine to
the point at which the M9301-YC will operate. Console functions are described in detail in Section III
of the KBI1-B Processor Manual (PDP-11/70).

(DEAD MACHINE)
2

CHECK POWER

(CH. 4) AND CABLES
(PAR.5.2.2; APP. A)

| FIG.51

SOME

Sgtfig'fil\'

vesY

| N A SYSTEM DEVICE.

LADRS = 200 PROBABLY

MEANS LOSS OF POWER

LOAD ADRS

;

"IF LOAD ADRS DOES NOT

17 777 776

WORK AND:

ALL 0S

RUN, MASTER & ALL DATA

uLADRS =200 (ZAP)

INDICATORS ARE ON

LTHEN MEMORY HAS LOST POWER

CHECK INDICATORS}{
W/LAMP TEST SW

ADRS
INDICATORS
=SW REG.

THESE STEPS SHOULD BE
EXECUTED ONCE FOR
1S, THEN REPEATED FOR

KALL 0S

CHECK:
CONS. CABLES

YES

| (APPENDIX A)

DATA PATHS USE *
MAINTENANCE

MODULE (PAR. 5.3.3)

_ADDR

“RR LITE
ON
NO

DEPOSIT
ALL 1S
ALL 0S

YES
-

EXAMINE

ADOR

ALL 1S

ERR LITE

ALL 0S

MODULE &
REPAIR (PAR. 5.3.3)

START &

v :
— CONTINUE

RUN SMALL LOOP

PAR

ERR LITE
ON

YES

CHECK:

.
C
MORY
ZC)ABLES
‘ '(‘gEARc’:z
AR 622),

YES

STEP THRU

o| W/MAINTEN.

BOOT
M9301

|FeuRre
5-1

*DATA PATHS ARE
DESCRIBED IN
SECT.Il,CH.2 OF
KB11-B MANUAL
11-3481

Figure 5-2

Troubleshooting Dead Machine

5-16

5.2.1

AC and DC Power

5.2.2

Cabling

AC and dc power maintenance and troubleshooting are explained in Chapter 4 of this manual.
This paragraph describes the cable routing for the memory, Massbus and Unibus, and console. Power
(ac and dc) cabling is described in Chapter 4.

When looking at the top of the CPU box, the memory, Massbus, and Unibus cables are all routed to
the rear of the cabinet. All these cables are ROUGH side up, RED STRIPE towards the backplane
side of the modules. The console cables, on the other hand, are routed to the front of the box and have
the SMOOTH side up, RED STRIPE toward the handle side of the modules (refer to Paragraph
5.2.2.4 for the console cables).

The SPC (small peripheral controller) cables are also routed toward the rear of the box.
SPC, MJ11, Massbus and Unibus cables are held in place at the rear of the CPU box by a clamp
(Figure 5-3).

ROUND

FLAT

CABLES

MN-3469

Figure 5-3

CPU Cable Holding Clamp

Some PDP-11/70 systems use wire cable troughs in which the cables are routed. Refer to Appendix H

for details on this system.

5.2.2.1

MKI11 Cabling -

All cables are marked at each end.

There are two address bus cables:
From H8143 (ADML) J1 to M8158 (ABB) J1.
From M8143 (ADML) J2 to M8158 (ABB) J3.

There are two data bus cables:
From M8145 (CDPC) J1 to M8159 (DBB) J1.
From M8145 (CDPC) J2 to M8159 (DBB) J3.
5-17

At the CPU end, the SMOOTH side of the bus cables face the module into which it is
plugged. The red stripe is on the left (handle side of module).
At the MKI11, the red stripe is on the left side as seen from the component side of the
module. Incoming cables, from the CPU, have the SMOOTH side up; outgoing cables, to
next memory frame, have the RIBBED side up.

There are two box controller cables:
From box controller J1 to memory frame J31.
From box controller J2 (SMOOTH side up) to M8159 (DBB) J5.
(SMOOTH side up, red stripe to left on component side of board).
There are three battery backup power cables:
From memory frame J28 to H775 unit A, J1.
From memory frame J29 to H775 unit B, JI.
From memory frame J30 to H775 unit C, J1.
5.2.2.2

MJ11 Cabling

All cables are marked at each end.
There are two address cables:
From M8143 (ADML) J1 to M8147/M 8148 (MCTA) J1.
From M8143 (ADML) J2 to M8147/M8148 (MCTA) J3.

There are two data cables:
From M8145 (CDPC) J1 to M8149 (MXRA) J1.
From M8145 (CDPD) J2 to M8149 (MXRB) J3.

At the CPU end, the SMOOTH side of the cables faces the module into which it is plugged.
The red stripe is on the left (handle side of the module).

At the MJ11 end, the ROUGH side of the cable faces the module into which it is plugged.
The red stripe is on the side of the cable closer to the front of the drawer (Figure 5-4).
5.2.2.3 - Massbus Cabling

There are three Massbus cables per controller.
These cables plug into J1 of the three M5904 modules, SMOOTH side facing the module
into which it is plugged.
The red stripe is on the left (handle side of module).
Refer to the several Massbus device maintenance manuals for the cable connections at the
device.

5-18

7456-34

Figure 5-4

MJ11 Frame Cabling

5.2.2.4 PDP-11/70 Unibus Cabling - The BC11-A cable is the I/O bus that connects all Unibus
system components external to the CPU cabinet. To connect the Unibus between the CPU cabinet and
an expansion cabinet, insert the BC11-A cable in slot A44 of the CPU mounting box cabinet. The cable
runs through a cable clamp in the upper left corner at the rear of the CPU mounting box and passes
under the power supply mounting rails into the next cabinet. In the expansion cabinet, the cable passes
through a similar cable clamp and is inserted in the appropriate slot of the first system unit of the
BA11-K mounting box. Adjacent system units in a mounting box are connected by an M9202 Unibus
connector module. The Unibus must be terminated at the CPU end (slots EOl and F01) by an M9301YC.

If the Unibus interconnects more than 20 bus loads, or is longer than 50 feet, a DB11-A bus repeater

must be used. Refer to Paragraph 3.6 for Unibus loading and configuration rules. A section of bus
delimited by bus repeater(s) is called a bus segment, and must be terminated at both ends with an
M930 bus terminator. The last terminator on the Unibus must be an M9302.

5.2.2.5

Console Cabling

Power Connector

Power is supplied to the console by processor harness plug P1. Insert this plug into console PC board

connector J4.

Signal Connectors

Three flat signal cables connect the console to the processor modules.
1.

J1 connects to J1 on M8134 (PDR, slot 10).

J2 connects to J1 on M8140 (SCC, slot 16): J3 connects to J2 on the same module. J1 on the
M 8140 is the connector closer to the edge of the module.

Installation of Signal Cables

The three signal cables are installed with the rough side facing the console PC board. The red stripe is
on the side of the flat cables that is closer to the power harness connector J4. The smooth side of the
cable faces the M 8134 and M8140 modules.
Console Operations

5.2.3

The console operations, as listed below, can only be executed when the processor is in the HALT state
(microprogram address = 170) and the console key is in the ON position.
Console operations are the following:
1.

LOAD ADDRESS

DEPOSIT and DEPOSIT/STEP

Memory (00 000 000 - SYSTEM SIZE REGISTER)
Peripheral Page (17 777 776 - 17 760 000)
General Register (17 777 717 - 17 777 700)

5-20

EXAMINE and EXAMINE/STEP

Memory (00 000 000 - SYSTEM SIZE REGISTER)
Peripheral Page (17 777 776 - 17 760 000)
General Register (17 777 717 - 17-777 700)

START

CONTINUE

Section III of the KB11-B Processor Manual contains a description of these functions
as well as those
of the console indicators (Chapter 1), and a detailed description of the console logic
(Chapter 2).

NOTE
It is important to use the correct setting of the ad-

dress select switch:

VIRTUAL - Six positions: KERNEL, SUPER and
USER I space and KERNEL, SUPER and USER D
space. The address displayed is a 16-bit virtual address; bits 21 - 16 are always off.
CONS PHY - (Console Physical). The 22-bit address entered by a LOAD ADRS is the physical address of the console operation.
PROG PHY - (Program Physical). Displays the 22bit physical address generated by memory management for the current Unibus or memory cycle.

5.3

TROUBLESHOOTING AIDS

5.3.1
PDP-11/70 Unibus Registers and Addresses
The peripheral page addresses of particular concern to the PDP-11 /70 are listed
below in numerical
order.

5-21

There are references to brief descriptions in this paragraph and to the appropriate manaul.
References

Address

17777 776

Processor Status Word (PS)

17777 772
17 777 770

Program Interrupt Request (PIR)
Microprogram Break

17777 774

Stack Limit (SL)

17 777 766

CPU Error

17 777 756

Reserved for future use

17 777 764
17 777 762
17 777 760

System I/D
Upper Size
Lower Size

17 777 754

17777716
17777 715
17 777 714
17777 713
17777 712
17777 711
17777710

Supervisor SP
General Registers,
Set 1

R6
RS
R4
R3
R2
R1
RO

17 777 707
17 777 706
17 777 705
17 777 704
17 777 703
17 777 702
17 777 701
17 777 700

Program Counter
Kernel SP
General Registers,
Set 0

R7 (PC)
R6
RS
R4
R3
R2
R1
RO

17777 676

User Data PAR, Reg 0-7

MM Registers (5.3.1.2)

17 777 656

User Instruction PAR, Reg 0-7

through
17 777 660

through
17 777 640

17 777 636

User Data PDR, Reg 0-7

through
17 777 620

17777 616

User Instruction PDR, Reg 0-7

through
17 777 600

17 777 576
17777 574
17777 572

Memory Mgmt Regs: (MMR2)
Memory Mgmt Regs: (MMR1)
Memory Mgmt Regs: (MMRO)

5-22

Address

References

17 777 570

Console Switch and
Display Register

Refer to Chapter 3, Section II of
KB11-B, C Processor Manual.

17 777 566
17 777 564
17 777 562
17 777 560

LA36 DECwriter Printer Data
L A36 DECwriter Printer Status
LA36 DECwriter Keyboard Data
LA36 DECwriter Keyboard Status

17 777 556

PC11/PR11, punch data

17772 376

Kernel Data PAR, Reg 0-7

through

Refer to LA36 Manual. These
- locations are reserved for KBO,
the system console.

17 772 360
17772 356
through
17 772 340

Kernel Instruction PAR, Reg 0-7

17 772 336

Kernel Data PDR, Reg 0-7

through
17 772 320

17772 316

Kernel Instruction PDR, Reg 0-7

17772276
through
17 772 260

Supervisor Data PAR, Reg 0-7

17772 256

Supervisor Instruction PAR, Reg 0-7

through
17 772 300

through
17 772 240
17772 236
through
17 772 220

Supervisor Data PDR, Reg 0-7

17772 216
through
17 772 200

Supervisor Instruction PDR, Reg 0-7

17 770 366
through
17 770 200

Unibus Map

Refer to Paragraph 5.3.1.3

17 765 776
through
17 765 000

Part of PDP-11/70 diagnostic
bootstrap

Refer to Paragraphs 3.4.2
and 5.4

5-23

5.3.1.1

CPU Registers - The CPU registers are briefly explained here. For complete details, refer to
'

Section II, Chapter 3, of the KBI1-B Processor Manual.
17 777 776

Processor Status Word

CURRENT MODE "——-—f

PREVIOUS MODE *———
GENERAL REGISTER
SET(0,1)

‘T

11-3098

——

* MODE: 00 =KERNEL

01 =SUPERVISOR
=USER

Current Mode

15-14:

Specifies the current processor mode as follows:

When PS(15:14) = 0, the processor is in Kernel mode: all operations are legal.

When PS(15:14) = 01, the processor is in Supervisor mode; HALT, RESET, and SPL
instructions either trap to location 4 (HALT) or are treated as NOP (RESET and SPL);
SUPER address space is used if memory management is enabled.

PS(15:14) = 10 is an illegal mode; if memory management is enabled, a memory management abort occurs (refer to Section IV of the KBI1-B Processor Manual).

When PS(15:14) = 11, the processor is in User modc; HALT, RESET, and SPL instructions

either trap to location 4 (HALT) or are treated as NOP (RESET and SPL) USER address

space is used if memory management is enabled.
13-12:

Previous Mode

Specifies the processor mode prior to the last trap, interrupt, or loading of the PS.
11:

Specifies which general register set is used; if PS11 = 0, register set 0 is selected; if PS11 = 1, register set
1 is used.

10-08:

Unused

07-05:

Priority

Sets the processor priority; this priority determines which levels of programmed and external device

interrupt requests are honored.
04:

Trace

When PS04 = 1, the processor traps to the trace trap vector address (14 octal) after each instruction
fetch; this facility is used to debug programs.
03:

N Condition Code

02:

Z Condition Code

This bit is set when the result of the last data manipulation is negative.
This bit is set when the result of the last data manipulation is 0.

5-24

01:
V Condition Code
This bit is set when the result of the last data manipulation causes an arithmetic overflow.

00: C Condition Code
This bit is set when a carry occurs during data manipulation.
Stack Limit Register 17 777 774
The stack limit allows program control of the lower limit for permissible stack addresses. This limit
may be varied in increments of 400 (8) bytes or 200 (8) words, up to a maximum address of 177 400
(almost the top of a 32K memory).
The normal boundary for stack addresses is 400. The stack limit option allows this lower limit to be
raised, providing more address space for interrupt vectors or other data that should not be destroyed
by the program.
=
The Stack Limit register has the following format:

W
1-3099

The Stack Limit register can be addressed as a word at location 17 777 774, or as a byte at location 17
777 775. The register is accessible to the processor and console, but not to any bus device.

The 8 bits, 15 through 8, contain the stack limit information. These bits are cleared by INIT. The lower
8 bits are not used. Bit 8 corresponds to a value of 400 (8) or 256 (10).

Program Interrupt Request Register (PIR) 17 777 772
A request is booked by setting one of the bits 15 through 9 (for PIR 7 - PIR 1) in the Program
Interrupt register at location 17 777 772. The hardware sets bits 7-5 and 3-1 to the encoded value of the
highest PIR bit set. This Program Interrupt Active (PIA) should be used to set the processor level and
also index through a table of interrupt vectors for the seven software priority levels. The following
figure shows the layout of the PIR register.

PIR 7

PlR]F/,/jP
"//

A%P

Ayfi
11~3097

When the PIR is granted, the processor will trap to location 240 and pick up PC in 240 and the PSW in
242. Tt is the interrupt service routine’s responsibility to queue requests within a priority level and to
clear the PIR bit before the interrupt is dismissed.
Microprogram Break Register 17 777 770
This register is used for maintenance purposes only. It is used with maintenance equipment to provide

timing synchronization and testing facilities. The microaddress in this register generates a sync pulse at
T1 at pin F13K2 each time the cycle corresponding to the address is executed (TIGB PB SYNCH H); a
pulse whose width is the same as that of the cycle is also generated at A10E1 (PDRC PB CMP H).

5-25

Refer to the KB11-B or KB11-C Processor Manual Section 1I, Paragraphs 3.6 and 4.9.2,
CPU Error Register

17 777 766

ILLEGAL HALT

Y ////%11%1%%2%///2
T

ODD ADDRESS ERROR
NON-EXISTENT MEMORY (CACHE)
UNIBUS TIME-OUT
YELLOW ZONE STACK LIMIT

RED

ZONE STACK LIMIT
11-3100

This register identifies the source of the abort or trap that used the vector at location 4.
7.

Illegal Halt

Set when trying to execute a HALT instruction when the CPU is in User or Supervisor mode (not
Kernel).

Odd Address Error

Non-existent Memory

Unibus Timeout

Sét when a program attempts to do a word reference to an odd address.

Set when the CPU attempts to read a word from a location higher than indicated by the System Size
register. This does not include Unibus addresses.

Set when there is no response on the Unibus within approximately 10 us.

3: Yellow Zone Stack Limit
Set when a yellow zone trap occurs.
2:
Red Zone Stack Limit
Set when a red zone abort occurs.
System I/D Register 17 777 764
This read only register contains information uniquely identifying each system. As of this writing, the
bits are undefined.

Upper Size Register 17 777 762
This register is an extension of the lower size register, which is reserved for future use. It is read only
and its contents are always read as zero.
Lower Size Register 17 777 760
This read only register specifies the memory size of the system. It is defined to indicate the last addressable block of 32 words in memory (bit O is equivalent to bit 6 of the Physical Address).

Refer to Paragraph 3.5.4 and to the KBI1-B Processor Manual, Section 1V, Chapter 5.
CPU General Registers
17 777 717 - 17 777 700
The general registers can be used as accumulators, index registers, auto-increment registers, autodecrement registers, or as stack pointers for temporary storage of data. Arithmetic operations can be
from one general register to another, from one memory or device register to another, or between
memory or device register and a general register.
5-26

R7 is used as the machine’s program counter (PC) and contains the address
of the next instruction to
be executed. It is a general register normally used only for addressin
g purposes and not as an accumulator for arithmetic operations.
The R6 register is normally used as the processor stack pointer indicatin
g the last entry in the appropriate stack (Kernel stack, Supervisor stack, and User stack). When the
central processor is operating
in Kernel mode it uses the Kernel stack, in Supervisor mode, the Superviso
r stack, and in User mode,
the User stack. When an interrupt or trap occurs, the PDP-11 /70 automatic
ally saves its current status
on the Processor stack selected by the service routine.

The remaining 12 registers are divided into two sets of unrestricted registers,
RO-RS. The current
register set in operation is determined by the processor status word bit 11.
Refer to the KBI1-B Processor Manual, Section II, Paragraphs 2.1.3 and 2.1.4.
3.3.1.2 Memory Management Registers - A brief descript
ion of the Memory Management registers
follows. For a detailed description of their operation, refer
to Section IV of the KBI11-B Processor
Manual.

Memory Management Register 0 (MMRO)
MMRO contains error flags, the page number whose referenc
e caused the abort, and various other
status flags. The register is organized as follows:

SSRD

SSRC

SSRD
SSRC

SSRE

HEEN
]
$

LENGTH ERROR

TTLITITIT]

ABORT-READ ONLY
ACCESS VIOLATION
TRAP-MEMORY MANAGEMENT

NOT USED

NOT USED
ENABLE MEMORY MANAGEMENT TRAP
MAINTENANCE MODE

INSTRUCTION COMPLETED
PAGE MODE
PAGE ADDRESS SPACE

I/D

PAGE NUMBER

ENABLE RELOCATION
11- 4046

Setting bit 0 of this register enables address relocation and error detection. This means that the bits in
MMRO become meaningful.

Bits 15-12 are the error flags. They may be considered to be in a “priority queue” in that “flags
to the
right” are less significant and should be ignored. That is, a “nonresident” fault-service routine
would
ignore length, access control, and memory management flags. A “page length’ service routine
would
ignore access control and memory management faults, etc.
Bits 15-13, when set (error conditions), cause memory management to freeze the contents of bits 1-7
and Memory Management registers 1 and 2. This has been done to facilitate error recovery.

5-27

These bits may also be written under program control. No abort will occur, but the contents of the
Memory Management registers will be locked up as in an abort.

Abort-Nonresident

15:

Bit 15 is the abort-nonresident bit. It is set by attempting to access a page with an Access Control Field
(ACF) key equal to 0, 3, or 7. It is also set by attempting to use memory relocation with a processor
mode of 2.

Abort-Page Length

14:

Bit 14 is the abort-page length bit. It is set by attempting to access a location in a page with a block
number (virtual address bits, 12-6) that is outside the area authorized by the Page Length Field (PLF)
of the Page Descriptor Register (PDR) for that page. Bits 14 and 15 may be set simultaneously by the
same access attempt. Bit 14 is also set by attempting to use memory relocation with a processor mode
of 2.

13:

Abort-Read Only

Bit 13 is the abort-read only bit. It is set by attempting to write in a read-only page. Read only pages
have access keys of 1 or 2.
12:

Trap-Memory Management

Bit 12 is the trap-memory management bit. It is set whenever a memory management trap condition
occurs; that is, a read operation which references a page with an Access Control Field (ACF) of lor4,
or a write operation to a page with an ACF key of 4 or 5.
11 and 10 - Spares

Bits 11 and 10 are spare and are always read as 0; they should never be written. They are unused and

reserved for possible future expansion.
9:

Enable Memory Management Traps

Bit 9 is the enable memory management traps bit. It is set or cleared by doing a direct write into
MMRO. If bit 9 is 0, no memory management traps will occur. The A and W bits will, however,

continue to log memory management trap conditions. When bit 9 is set to 1, the next memory management trap condition will cause a trap, vectored through Kernel virtual address 250.

Note that if an instruction which sets bit 9 to 0 (disable memory management trap) causes a memory

management trap condition in any of its memory references prior to and including the one actually

changing MMRO, then the trap will occur at the end of the instruction anyway.
8:

Maintenance/Destination Mode

Bit 8 specifies that only destination mode references will be relocated using memory management. This

bit may be used only for maintenance purposes.

Instruction Completed

Bit 7 indicates that the current instruction has been completed. It will be set to 1 during T bit, parity,
odd address, and time out traps and interrupts. This provides error handling routines with an aid to
determine whether the last instruction will have to be repeated in the course of an error recovery

attempt. Bit 7 is read only (it cannot be written). It is initialized to a 1. Note that EMT, TRAP, BPT,
and IOT do not set bit 7. Refer to Section 1V, Paragraph 9.1.4 of the KBl 1-B Processor Manual.
5 and 6:

Processor Mode

Bits 5 and 6 indicate the CPU Mode (Kernel/Supervisor/User) associated with the page causing the
abort (Kernel = 00, Supervisor = 01, User = 11, Illegal mode = 10). If an Illegal mode is specified, bits
15 and 14 will be set.

5-28

Page Address Space

Bit 4 indicates the type of address space (I or D) the Unit was in when a fault occurred (0 = I Space, |
= D Space). It is used in conjunction with bits 3-1, Page Number.

3to1l:

Page Number

Bits 3-1 contain the page number of a reference causing a memory management fault. Note that pages,
like blocks, are numbered from 0 upward.
0:
Enable Relocation
Bit 0 is the enable relocation bit. When it is set to 1, all addresses are relocated by the unit. When bit 0
is set to 0, the memory management unit is inoperative and addresses are not relocated or protected.

Memory Management Register 1 (MMR1) 17 777 574
MMRI1 records any autoincrement/decrement of the general purpose registers, including explicit ref-

erences through the PC. MMRI1 is cleared at the beginning of each instruction fetch., Whenever a
general purpose register is either autoincremented or autodecremented, the register number and the
amount (in 2s complement notation) by which the register was modified, is written into MMR.

AMOUNT CHANGED

(2S5 COMPLEMENT)

NUMBER

~ AMOUNT CHANGED

{2'S COMPLEMENT)

NUMBER

11-4042

Memory Management Register 2 (MMR2)

17 777 576

MMR?2 is loaded with the 16-bit virtual address (VA) at the beginning of each instruction fetch, or
with the address trap vector at the beginning of an interrupt, T bit trap, parity, odd address, and
timeout aborts and parity trap. Note that MMR2 does not get the trap vector on EMT, TRAP, BPT
and IOT instructions. MMR?2 is read only; it cannot be written. MMR2 is the Virtual Address Program Counter.

11-4041

Memory Management Register 3 (MMR3)

17 772 516

Memory Management Register 3 (MMR3) enables or disables the use of the D space PARs and PDRs
and 22-bit mapping and Unibus mapping. When D space is disabled, 11 references use the I space
registers; when D space is enabled, both the I space and D space registers are used. Bit 0 refers to the
User’s registers, bit 1 to the Supervisors, and bit 2 to the Kernels. When the appropriate bits are set, D
space is enabled; when clear, it is disabled. Bit 03 is read as zero and never written. It is reserved for
future use. Bit 04 enables 22-bit mapping. If memory management is not enabled, bit 04 is ignored and
16-bit mapping is used.
If bit 4 is clear and memory management is enabled (bit 0 of MMRO is set), the computer uses 18-bit
mapping. If bit 4 is set and memory management is enabled, the computer uses 22-bit mapping. Bit 5 is
set to enable relocation in the Unibus map; the bit is cleared to disable reloaction. Bits 6 to 15 are
unused. On initialization, this register is set to 0 and only I space is in use.

5-29

/7 7 %
v//l///,{u// It’////
F/CL
N

’

‘MODE l

ENABLE UNIBUS MAP

ENABLE 22-BIT MAPPING

MMR3
17772516

KERNEL

—
SUPERVISOR
USER
11-4040

Bit
5

2
1
0

State
0

Operation
Unibus map relocation disabled

Unibus map relocation enabled

Enable 18-bit mapping

Enable 22-bit mapping

1
1
1

Enable Kernel D Space
Enable Supervisor D Space
Enable User D Space

if bit 0
of MMRO
is set

Page Address Registers (PAR)
The Page Address Register (PAR) contains the Page Address Field (PAF), 16-bit field, which specifies
the starting address of the page as a block number in physical memory. -

The addresses of these registers are listed in Table 5-2.
The Page Address Register may be alternatively thought of as a Relocation register containing a
relocation constant, or as a Base register containing a base address. Either interpretation indicates the
basic importance of the Page Address Register (PAR) as a relocation tool.

There are six sets of eight PARs, one set for Kernel Data Space, one for Kernel Instruction Space, one
for Supervisor Data Space, one for Supervisor Instruction Space, one for User Data Space, and one
for User Intruction Space.
Page Descriptor Registers (PDR)
.
The Page Descriptor Register (PDP) contains information relative to page expansion, page length, and
access control.

There are six sets of eight PDRs which are allocated in the same manner as the PARs. The addresses of
these registers are listed in Table 5-2.

A BIT (TRAP)
PAGE

WRITTEN

INTO (TRAP)

EXPANSION DlRECTlON\
(0=UP, 1= DOWN)f
ACCESS

CONTROL

FIELD
11-4033

5-30

Table 5-2

PAR/PDR Unibus Addresses
Kernel

D Space

I Space

No.

PAR

PDR

No.

PAR

PDR

0
1
2
3
4
5
6
7

17 772 340
17 772 342
17 772 344
17 772 346
17 772 350
17 772 352
17 772 354
17 772 356

17 772 300
17 772 302
17 772 304
17 772 306
17 772 310
17 772 312
17 772 314
17772 316

0
|
2
3
4
5
6
7

17 772 360
17 772 362
17 772 364
17 772 366
17 772 370
17 772 372
17 772 374
17 772 376

17 772 320
17 772 322
17 772 324
17 772 326
17 772 330
17 772 332
17 772 334
17 772 336

Supervisor

D Space

I Space

No.

PAR

PDR

No.

PAR

PDR

17 772 240

17 772 200

17 772 260

17 772 220

1
2
3
4
5
6
7

17 772 242
17 772 244
17 772 246
17 772 250
17 772 252
17 772 254
17 772 256

1
2
3
4
5
6
7

17 772 202
17 772 204
17 772 206
17 772 210
17 772 212
17 772 214
17772 216

17 772 262
17 772 264
17 772 266
17 772 270
17 772 272
17 772 274
17 772 276

17 772 222
17 772 224
17 772 226
17 772 230
17 772 232
17 772 234
17 772 236

User

D Space

I Space

No.

PAR

PDR

No.

PAR

PDR

0
1
2
3
4
5
6
7

17 777 640
17 777 642
17 777 644
17 777 646
17 777 650
17 777 652
17 777 654
17 777 656

17 777 600
17 777 602
17 777 604
17 777 606
17 777 610
17 777 612
17 777 614
17777616

0
1
2
3
4
5
6
7

17 777 660
17 777 662
17 777 664
17 777 666
17 777 670
17 777 672
17 777 674
17777 676

17 777 620
17 777 622
17 777 624
17 777 626
17 777 630
17 777 632
17 777 634
17 777 636

5-31

2to 0:
Access Control Field (ACF)
This three-bit field, occupying bits 2-0 of the Page Descriptor Register (PDR) contains the access
rights to this particular page. The access codes or “keys” specify the manner in which a page may be
accessed and whether or not a given access should result in a trap or an abort of the current operation.
A memory reference which causes an abort is not completed while a reference causing a trap is completed. In fact, when a memory reference causes a trap to occur, the trap does not occur until the entire
instruction has been completed. Aborts are used to catch a “missing page fault,” prevent illegal access,

etc.; traps are used as an aid to gather memory management information.

In the context of access control, the term “write” is used to indicate the action of any instruction that
modifies the contents of any addressable word.

The modes of access control are as follows:

000 Nonresident Abort all accesses
001 Read only

Abort on write attempt, memory management trap on read

010

Readonly

Abort on write attempt

011

Unused

Abort all accesses - reserved for future use

100

Read/write Memory management trap upon completion of a read or write

101

Read/write Memory management trap upon completion of a write

110

Read/write No system trap/abort action

111

Unused

Abort all accesses - reserved for future use

It should be noted that the use of I Space provides the user with a further form of protection, execute
only.
7.
A Bit
This bit is used by software to determine whether any accesses to this page met the trap
condition

specified by the Access Control Field (AFC) (A = 1 is affirmative). The A Bit is used in the process
of
gathering memory management statistics.
6:
W Bit
This bit indicates whether this page has been modified (i.e., written into) since either the PAR
or

PDR
was loaded. (W = 1 is affirmative). The W Bit is useful in applications that involve disk swapping and
memory overlays. It is used to determine which pages have been modified and hence must be saved

their new form, and which pages have not been modified and can be simply overlaid.

Note that A and W bits are “‘reset” to ‘0’ whenever either PAR or PDR is modified (written

5-32

into).

Expansion Direction (ED)

Bit 03 of the Page Description Register (PDR) specifies in which direction the page expands. If ED = 0
the page expands upwards from Block Number 0 to include blocks with higher addresses; if ED = 1,
the page expands downwards from Block Number 127 to include blocks with lower addresses. Upward
expansion is usually used for program space while downward expansion is used for stack space.
14 to 08:

Page Length Field (PLF)

This 7-bit field specifies the block number, which defines the boundary of that page.
The block number of the virtual address is compared against the page length field to detect length
errors. An error occurs when expanding upwards if the block number is greater than the page length
field, and when expanding downwards if the block number is less than the page length field.
15, 5, and 4:

Reserved Bits

Bits 15, 5, and 4 are spare, are always read as 0, and should never be written. They are unused and
reserved for possible future expansion.

5.3.1.3 Unibus Map Registers 17 770 336 - 17 770 200 - There are a total of 31 mapping registers for
address relocation. Each register is composed of a double 16-bit PDP-11 word (in consecutive locations) that holds the 22-bit base address.

If Unibus Map relocation is enabled, the five high order bits of the Unibus address are used to select
one of the 31 mapping registers. The low order 13 bits of the incoming address are used as an offset
from the base address contained in the 22-bit mapping register. To form the physical address, the 13
low order bits of the Unibus address are added to 22 bits of the selected mapping register to produce
the 22-bit physical address. The lowest order bit of all mapping registers is always a zero, since relocation is always on word boundaries.

Table 5-3 shows the correspondence between the Unibus address when reading or writing the Unibus
Map registers and the peripheral page addresses that will use these same registers for mapping.
For a detailed description of Unibus Map operation, refer to Section V, Chapters 1 and 3 of the KBI /B Processor Manual.

5.3.1.4 Cache Registers - The PDP-11/70 utilizes byte parity throughout the memory system. Parity
is checked on each byte of a word (the sum of the bits, 8 data plus one parity should always be odd).

When a parity error occurs under normal operation, it causes a trap through location 114. Exception is
made when parity traps are disabled.

In general, two types of action can be taken as the result of a parity error. One is an abort of the
memory reference, where the cycle detecting the parity error is suspended and the CPU is immediately
trapped through location 114, The other type of action is a trap. This occurs at the completion of the
instruction being executed and also traps the CPU through vector 114. Since the PDP-11/70 fetches
two 16-bit words from main memory into the cache on misses, it is possible for parity errors to occur
on either of the words being fetched. One of the two words fetched is not used immediately.

Aborts, in general, are the result of parity errors occurring on the data word requested by the memory
reference, while traps occur if the data word not needed by the reference is the cause of the parity error.

5-33

Table 5-3

Access to Unibus Map Registers

Unibus Address
Read or Write

Unibus Address for
Memory Reference

When Mapping

Low O1der

High Order

Bits

0
1
2
3

17 770 200
17 770 204
17770210
17 770 214

02
06
12
16

17 000 000
- 17 017 777
17 020 000 - 17 037 777
17 040
000 - 17 057 777
17 060000
- 17 077 777

4
5
6
7

17 770220
17 770224
17 770230
17 770 234

22
26
32
36

17100000
- 17 117 777
17120000-17 137 777
17 140000
- 17 157 777
17 160 000 - 17 177 777

17 770 240
17 770 244

17 200 000 - 17 217 777

12
13

17770250
17 770 254

46
52

17 220000 - 17 237 777
17240 000
- 17 257 777
17 260 000 - 17 277 777

17 770260

17 770 264

16
17

17 770270
17 770 274

17 300 000
- 17 317 777
17 320000 - 17 337 777

72
76

17 340 000 - 17 357 777
17 360 000 - 17 377 777

20
21
22
23

17 770 300
17 770 304
17770310
17 770 314

17400000
- 17 417 777

06
12
16

17420000 - 17 437 777
17 440 000 - 17 457 777
17 460000
- 17 477 777

24
25
26
27

17 770 320
17 770 324
17 770 330
17 770 334

22
26
32
36

17 500 000 - 17 517 777
17 520 000 - 17 537 777
17 540 000 - 17 557 777
17 560000 - 17 577 777

30
31
32
33

17 770 340
17 770 344
17 770 350
17 770 354

42
46

17 600000-17 617 777
17 620000~ 17 637 777

52
56

17 640 000
- 17 657 777
17 660 000 - 17 677 777

34
35
36
*37

17 770 360
17 770 364
17 770 370
17 770 374

62
66
72
76

17700 000
- 17 717 777
17 720000 - 17 737 777
17 740 000 - 17 757 777
17760000 - 17 777 777

*Note: Can be read or written into, but not used for mapping.

5-34

In the case where the memory word that is not required causes the parity error, a trap is set up for
execution at the end of the instruction. If this word then becomes a desired location prior to the
completion of the instruction, the instruction is also aborted immediately during the reference when it
is the desired word.
Memory System Troubleshooting Aids
The PDP-11/70 contains numerous memory system troubleshooting aids. The most significant of
which are the Error registers, which store information at the time of error for future reference.

These registers are listed in this paragraph along with a short description of each.
In addition to these registers, the console panel provides a parity error indicator and two byte parity
bits adjacent to the Data register.
The parity error indicator operates dynamically: it follows the parity error lines from the memory
system, Thus, when running a program, this indicator will be ON when an error occurs, and is cleared
once it has been acknowledged by the trap sequence in the microprogram. For console operations this
light remains on (after a parity error resulting from an EXAMINE) until another console function is
executed.
The two parity bits adjacent to the Data register are loaded along with the 16 data bits when examining
a location from the console. They are cleared on DEPOSIT. These bits can be used to determine
whether the correct parity exists for a word in cases where the parity checkers/generators are suspected
as being bad. Note that when a location causes a parity error, neither the data nor the parity bits are
loaded. Instead, the parity error indicator is lit and all information concerning the error is saved in the
Error registers.
An important feature of the memory system Error registers is that in the case of multiple errors,

The Error registers preserve the information pertaining to the first error that occurred, and

In addition, they also flag the fact that a multiple error condition exists and that the memory
system no longer can track the failures. These bits are explained in detail in the Memory
System Error register bit description.

When a memory system error is detected, the processor traps to location 114. If location 114 is used as
a trap catcher, the operator can examine the Memory System Error register to determine the type of
error that has occurred. The Low Error Address registers can then be examined to determine where in
the program, and during what type of cycle, the error occurred. If statistics on the hit ratio are desired,
the Hit/Miss register can be read. The Control register can be read to determine what the control
conditions were at the time the error occurred.

If location 114 is not used as a trap catcher, the previous tasks must be performed by the trap service
routine.

The following points should be noted when troubleshooting the memory system:

The data patterns being written and read can affect detection of parity errors. For example,
if a bit in the address memory or main memory is stuck high, a parity error will be detected
only after writing a 0 into that bit position.

5-35

The replacement scheme within the cache is random. Thus:

Whenever a miss occurs and a block of data within the cache must be overwritten, or

Whenever a block of data is written immediately after power up,

the group into which the word goes is selected at random.

Because of the replacement strategy, a parity error may be detected if data is read from a
malfunctioning group, yet the same data will not generate a parity error when read from the
non-malfunctioning group (or if fetched directly from main memory).

A parity check is made each time the address memory and fast data memory are accessed. A
parity error can be detected even if the location being accessed is not stored in the cache (i.e.,
a miss). If the operation is a read, the data fetched from main memory will overwrite the
location causing the parity error (i.e., random replacement is overridden). The next time the
same location is read, no parity error may be detected.

[n some cases, therefore, a solid error may appear to be intermittent, while an intermittent error may
appear to be more intermittent than it really is.
Another factor to consider when working on the PDP-11/70 is that some of the older device diagnostics have not been rewritten to incorporate parity error handlers. This means that whenever a parity
error occurs, the program will halt with 120 in the address lights. (Trap through 114). This condition
should be treated in the same manner as any other memory parity error.
The Cache registers and their use are summarized in the following paragraphs. A complete description
of these registers and of their operation may be found in Section VI of the KB11-B Processor Manual.
Hit/Miss Register

17 777 752

]
11-2853

This register indicates whether the six most recent references by the CPU were hits or misses. A 1
indicates a read hit; a O indicates a read miss or a write. The lower numbered bits are for the more
recent cycles.
All the bits are read only. The bits are undetermined after a power-up. They are not affected by a
Console Start or a RESET instruction.

5-36

Maintenance Register

17 777 750

MAIN MEMORY PARITY-—'—j

FAST ADDRESS PARITY
FAST DATA PARITY
MEMORY MARGINS

]

The Maintenance register is used mainly to check the parity checkers and generators in the PDP-11 /70
memory system. Refer to the cache diagnostics for examples of the use of this register.
15-12:
Main Memory Parity
.
’
Setting these bits causes the four parity bits to be 1s. This only causes an error if the byte(s) for which
these bits are set to 1 contain an odd number of bits. There is 1 bit per byte; there are 4 bytes in the data
block.

Bit Set

Byte

Odd word, high byte

14
13
12

Odd word, low byte
Even word, high byte
Even word, low byte

11-8:
Fast Address Parity
Setting these bits causes the four parity bits for fast address memory to be wrong. This causes an error
to be flagged immediately. Bits 11 and 10 affect group 1; bits 9 and 8 affect group 0.
7-4:
Fast Data Parity
Setting these bits causes the four parity bits to be 1s. This only causes an error if the byte(s) for which
these bits are set to 1 contain an odd number of bits.

Bit Set

Byte

7
6
5
4

Group 1, high byte
Group 1, low byte
Group 0, high byte
Group 0, low byte

3-1:
Memory Margins
These bits are encoded to perform maintenance checks on main memory.

0O
0
0
0
1
1
1
1

Bit 3

Bit 2

Bit 1

O
O
1
1
0
0
1
1

Normal operation
Forces wrong address parity
Early strobe margin

1
0
1
0
1
0
1

Late strobe margin
Low current margin
High current margin
Reserved
Reserved

All main memory is margined simultaneously.

5-37

17 777 746

Control Register

]

iiiiiiivzzRERRER
1

‘J

GROUP1O
FORCE REPLACEMENT
REPLACEMENT GROUP
FORCE

FORCE MISS GROUP 1
FORCE MISS GROUWP O
DISABLE UNIBUS TRAP
DISABLE TRAPS

The PDP-11/70 has the capability of running in a degraded mode if problems are detected in the cache.
If group 0 of the cache is malfunctioning, it is possible to force all operations through group 1. If bits 2
and 5 of the Control register are set, and bits 3 and 4 are clear, the CPU will not be able to read data
from group 0, and all main memory data replacements will occur within group 1. In this manner, half
the cache will be operating, but system throughout will not decrease by 50 percent, since the statistics
of read hit probability will still provide reasonably fast operation.

If group 1 is malfunctioning, bits 3 and 4 should be set, and bits 2 and 5 cleared so that only group 0 is
operating. If all of the cache is malfunctioning, bits 2 and 3 should be set. The cache will be bypassed,
‘

and all references will be made directly to main memory.

Bits 1 and 0 can be set to disable trapping; more memory cycles will be performed, but overall system

operation will produce correct results.
5-4:

Force Replacement

Setting these bits forces data replacement within a group in the cache by main memory dataon a read
miss. Bit 5 selects group 1 for replacement; bit 4 selects group 0.
3-2:

Force Miss

Setting these bits forces misses on reads to the cache. Bit 3 forces misses on group 1; bit 2 forces misses
on group 0. Setting both bits forces all cycles to main memory and disables the cache.
1:

Disable Unibus Trap

Disable Traps

Set to disable traps to vector 114 when the parity error signal (PB=1, PA=0) is placed on the Unibus.
Set to disable trap from non-fatal errors.

Bits 5 through 0 are read/write. The bits are cleared on Power-up or by Console Start.
17 777 744

Memory System Error Register

CPU ABORT

[ TT T T[]

CPU ABORT AFTER ERROR

UNIBUS PARITY ERROR
—

UNIBUS MULTIPLE PARITY ERROR
CPU ERROR
UNIBUS ERROR
CPU UNIBUS ABORT
ERROR IN MAINTENANCE
DATA MEMORY GROUP 1

DATA MEMORY GROUP 0
1
ADDRESS MEMORY GROUP
O
ADDRESS MEMORY GROUP

MAIN MEMORY QDD WORD
MAIN MEMORY EVEN WORD

MAIN MEMORY ADDRESS PARITY ERROR

MAIN MEMORY TIMEQUT

5-38

[}

[

[}

[

| ]]

15:
CPU Abort
Set if an error occurs that caused the cache to abort a processor cycle.

14:
CPU Abort After Error
Set if an abort occurs with the Error Address register locked by a previous error.

If bit 14 (CPU abort after error) or bit 12 (Unibus multiple parity error) of the Memory System Error
register is set, the address stored in the Low Error Address and High Error Address registers is the

address of the first error and not the address at which the most recent error occurred. The address at
which the most recent error occurred must be reconstructed from the contents of the SP (which points
to the virtual address incremented by 2) and the appropriate memory management PAR.

The contents of the Memory System Error register and the High and Low Error Address registers
indicates the failing section of the memory system.
13:
Unibus Parity Error
Set if an error occurs that resulted in the Unibus Map asserting the parity error signal on the Unibus.

12:
Unibus Multiple Parity Error
Set if an error occurs that caused the parity error to be asserted on the Unibus with the Error Address
register locked by a previous error.
11:
CPU Error
Set if any memory error occurs during a cache CPU cycle.

10:
Unibus Error
Set if any memory errors occur during a cache cycle from the Unibus.

9:
CPU Unibus Abort
Set if the processor traps to vector 114 because of Unibus parity error on a DATI or DATIP memory
cycle.
8:
Error in Maintenance
Set if an error occurs when any bit in the Maintenance register is set. The Maintenance register will
then be cleared.

7-6:
Data Memory
These bits are set if a parity error is detected in the fast data memory in the cache. Bit 7 is set if there is
an error in group 1; bit 6 for group 0.
5-4:
Address Memory
These bits are set if a parity error is detected in the address memory in the cache. Bit 5 is set if there is
an error in group 1; bit 4 for group 0.

3-2:
Main Memory
These bits are set if a parity error is detected on data from main memory. Bit 3 is set if there is an error
in either byte of the odd word; bit 2 for the even word. (Main memory always transfers two words at a
time.) An abort occurs if the error is in the word needed by a CPU reference. A trap occurs if the error
is in the other word, or if it is a Unibus reference.

5-39

For example, if type MJ11-A (16K, core) memory is used in the system, and a main memory parity
error bit is set in the Error register, all the information required to determine the failing 16K section of
memory is present. The Low and High Error Address registers indicate the 32K section of memiory in
which the error occurred. The Error register indicates whether the error occurred on the odd or even
addressed word. If, for instance, the error occurred in the odd addressed word, the 16K section cotitaining odd addressed words should be replaced.
1:

Main Memory Address Parity Error

Set if there is a parity error detected on the address and control lines on the main memory bus. If the
main memory address parity bit is set, there may be a problem in the parity generator (Drawing
ADMYJ) or in a memory controller parity checker. A failure in the main memory bus address and
control lines is the most likely cause for this error.
0:

Main Memory Timeout

Set if there is no response from main memory. For CPU cycles, this error causes an abort. When a
Unibus device requests a non-existent location, this bit will set, cause a time-out on the Unibus, and
to vector 114. If the main memory time-out bit is set, the most probable
then cause the CPU to trap
cause is a memory controller failure. Another possible cause is a miscontiguration of the System Size
register in the processor. (Refer to Paragraph 3.5.4.)

The bits are cleared on Power-up or by Console Start. They are unaffected by a RESET instruction.

When writing to the Memory System Error register, a bit is unchanged if a 0 is written to that bit, and
it is cleared if a 1 is written to that bit. Thus, the register is cleared by writing the same data back to the
register. This guarantees that if additional error bits were set between the read and the write, they will
not be inadvertently cleared.

High Error Address Register 17 777 742
4

rCYCLE E//
1

Eava

{

/ /A

s
s

HIGH ADDRESS
i

i
1

15-14:

Cycle Type

These bits are used to encode the type of memory cycle that was being requested when the parity error
occurred.

5-0:

Bit 15

Bit 14

0
1
1

1
0
1

Cycle Type
-

Data In Pause
Data Out
Data Out Byte

Address

These bits contain the higher six of the 22-bit address of the first error. The most significant bit is bit 5.
All the bits are read only. The bits are undetermined after a power-up. They are not affected by a
Console Start or RESET instruction.

5-40

Low Error Address Register
15

17 777 740
.

LOW ADDRESS (16 BITS)
L

This register contains the lower 16 bits of the 22-bit address of the first error. The least significant bit is
bit 0. The high order bits are contained in the High Error Address register.

All the bits are read only. The bits are undetermined after a Power-up. They are not affected by a
Console Start or RESET instruction.
5.3.2

Indicators, Switches, Jumpers and Test Points

This paragraph describes the maintenance aids and the switches provided in the PDP-11/70.
5.3.2.1 SACK Timeout Indicator (UBCD) - If no response (SACK) is received from the Unibus 10
microseconds after a Unibus grant (NPG or BG) is issued, a SACK timeout is said to have occurred.
This sets a flip-flop on UBCD, which turns on a LED indicator. The indicator stays on until the flipflop is reset by INIT. Figure 5-5 in this maintenance manual shows the location of the LED. Refer to
Section II, Paragraph 6.4, of the KB11-B or KBI1-C Processor Manual (PDP-11/70).

SACK
TIMEOUT
LED

(D10, UBCD)

a1
=

B 5=

1 o
— =

=3l e =]
':___][][]i0

;

[

£—n

L___l[][]g::

—0

e 10

&30

&£

| | — | >\|JD

0
0
&g
—

Figure 5-5

—

1-3488

M8136 SACK Timeout LED

5-41

5.3.2.2 Start Vector (M8130-DAPE) - Jumpers W1 through W6, shown on DAPE, determine the
start vector on power-up. The jumpers may be cut to provide a start vector between 00 000 000 and 00
000 174 (W6 OUT), or between 17 173 200 and 17 173 374 (W6 IN). Refer to Section II, Paragraph
2.1.9.4 of the KBI1-B or KBI1-C Processor Manual (PDP-11/70).
Bits 00 and 01 of the start vector are always 0. Bits 02:06 of the start vector are Os if their respective
jumpers (W 1:WS5) are OUT, and 1s if they are IN.
5.3.2.3
System Size Register (M8140-SCCN) - Refer to Paragraph 3.5.4, Figure 3-20, and Table 3-4
of this manual.
5.3.2.4

Massbus Controller Indicators and Jumpers

5.3.2.4.1 Indicators — The following light-emitting diodes are incorporated in the RH70 Massbus
Controller logic BCT module (Figure 5-6) on the M8153.
SSYN (Slave Sync)
TRA (Transfer)
BG IN (Bus Grant In) |
SACK (Selection Acknowledge)
BBSY (Bus Busy)

D-CS-M8153-0-1, Sheet 3 of 6
D-CS-M8153-0-1, Sheet 3 of 6
D-CS-M8153-0-1, Sheet 4 of
6
D-CS-M8153-0-1, Sheet
4 of 6
D-CS-M8153-0-1, Sheet 4 of 6

These LEDs are provided to aid maintenance personnel to isolate system faults as described below:
1.

Unibus on PDP-11/70is in “hung” condition (no operations can be performed on Unibus):
a.
b.
c.

Stuck SACK,
Stuck BBSY, or
Stuck SSYN

The associated LED will be continuously illuminated. LEDs may flicker intermittently during normal operation.

The Unibus device interrupt sequence is not functioning properly (processor continuously
loops in service routine and fails to execute instructions).
This condition may be caused by discontinuity of the bus grant signal on the Unibus from
the processor to the interrupting device and may be caused by missing grant continuity cards
or effective circuitry which normally passes grant signals from device to device. This will
cause the BG IN light-emitting diode to illuminate. If this LED is brightly illuminated, this
indicates that the Unibus BG IN signal coming to that device is stuck high.

The processor attempts to read or write a Remote register in the RWS04 or RWS03 subsystem and receives an address error indication on the console (CPU traps to location 4).
This condition may be caused by a stuck TRA signal on the Massbus which prevents the
SSYN resonse frm the RH70.
Determination of this condition may be made if local registers in the RH70 can be successfully accessed. If no register responds, the address jumpers may be improperly selected.

5-42

RH70 Jumpers
Address
Selection
Jumper
(BCTA)

Address
Bit

W14

Device

RWS04
(14 REG)

RWP04
(22 REG)
OuT

TWUI16
(16 REG)

W10
W9
W38

11
10
9

ouT

IN
ouT
IN

OuUT
OouT
IN

IN
OouT
IN

W1l
W13

8
7

IN
IN

ouT
ouT

OouT
IN

W15

OouT

W12

ouT

—
—_
—
—

IN
IN
OouT
OuUT

OouT
OuT
IN
IN

IN
IN
ouT
ouT

ouT

Slot E41
Jumper
(BCTA)

OouT

Binary
Weight

(ADRS. Bit 5)

1-16
2-25
3-14
4-13

(No. of Regs.)
5-12
6-11
7-10

OouT

OuUT

OuT

OuUT

W4
W1

V8
V7

ouT
IN

ouT

ouT
IN

OouT

ouT
IN

ouT

W3
W7

V3
V2

ouT
IN

IN
IN

OouT
IN

8-9

Vector
Jumper
(BCTC)

OouT
out

Vector
Bit

Figure 5-6

ouT

OouT

M28153 (BCT) Module (Sheet 1 of 2)

5-43

OuT

BCTB

—_—

BCTC

SACK

BBSY

SSYN

8CTB

et
TRA

BG IN

[s}

o] t

(o}

-\7

(]

O
i

L E E

w9
ws

wii"

w15

/3 —
. — =

]

) |

L D
o

—

wi2

=—]

I; =
— | m—]
]

B 5
=2~—
=
TM

i —"

ADDRESS

BITS

THE SUM OF THE

WEIGHTED

VALUES OF

JUMPERS REMOVED
PLUS 2 IS NO. OF
REGISTERS

SELECTED

eT =

—

PRIOR ITRY

“?é ll\lGAHRTYS

{NORMALLY BRS5)

OF JUMPERS

JUMPE

W5
w2

wé
w3

w7
11-3487

Figure 5-6

M8153 (BCT) Module (Sheet 2 of 2)

5.3.2.4.2 Jumper Configurations - The following paragraphs describe the various jumper configurations on the BCT (M8153), MDP (M8150), and CDP (M8145) modules.
BCT Module

M8153

The BCT module contains jumpers for register selection, BR level interrupt, and vector address. Refer
to Figure 5-6, which shows both jumper location and configurations.

Register Selection - The RH70 is capable of responding to 32 possible Unibus addresses. The number
of addresses, however, is dependent on the Massbus device. Jumpers W8 through W15 select the block
of Unibus addresses that the subsystem responds to. The standard addressing blocks assigned are as
follows:

RWS04: 772 040 through 772 072
RWPO04: 776 700 through 776 752
TWUI16: 772 440 through 772 476

BR Level Interrupt - The priority jumper plug for the RH70 is normally set for the BR5 level. This plug
is located in E022 (refer to D-CS-M8153-0-1, sheet 4 of 6).

Vector Address Jumpers — The interrupt vector transferred to the processor is jumper selectable via
jumpers W1 through W7, representing vector bits 2 through 8. Vector assignments for the RH70
devices are the following:
RWSO04: 204
RWP04: 254
TWUI16: 224

MDP Module

M8150

CDP Module

M8145

The MDP module contains jumpers that allow troubleshooting of the write-check error circuitry (Figure 5-7). These jumpers allow maintenance personnel to disconnect wired-OR connections from
the exclusive-OR network used to detect write-check errors. These jumpers are designated W1 through
W4 and are shown on MDPE. The jumpers provide maintenance personnel with a method of isolating
a faulty output (stuck low) of the wired-OR bus to one of four integrated circuit (IC) chips which
perform the exclusive-OR function during write-check operations. Fox example, if the output of E21
and E23 open-collector line is stuck low when scoping of the inputs indicate that it should be high, the
faulty IC (E21 or E23) can be ascertained by removing jumpers W2 and W1. If, after removing the
jumpers, the outputs of the exclusive-OR gates in E23 are still low, it indicates that the E23 chip is
defective. If E23 outputs are high, then the E21 chip is defective (outputs stuck low).

Jumpers W1, W2, and W3 determine the priority arbitration of the RH70 Massbus controllers. A
complete description of the arbitration process is given in Section VI, Paragraph 4.6 of the KB/I-B
Processor Manual (PDP-11/70). The most common configuration is that which allocates priority to
the controllers in the following order:
1.
2.
3.
4.

A
B
C
D

(slots 24-27)
(slots 28-31)
(slots 32-35)
(slots 36-39)

In this case, jumpers W1, W2, and W3 are all IN.

5-45

[

'3 0 ot (im dle=

] D§:| D::l IIDDD

—

0
0e=a

W4 w3

w1 lwe

el
0=

1€[(mmm)
==0
0
g

e 1

20—

i N1 [

0—1

(D0

0e—a0—

[0 0=—1 0—f
00—

010

c—

—

Figure 5-7

MDP Module - M8150

5.3.2.5 Main Memory (MK11) Maintenance Aids - Maintenance aids provided in the MK11 MOS
memory include: control and status register (CSR), fault indicator lights on the memory frame modules, and indicator lights on the box controller. The format of the two word CSR is shown in Figure
5-8. The address of the CSR is indicated in the memory box decal (refer to Chapter 3, Figure 3-29). The
CSR can be written to and read from the processor console, or through a terminal while running the
memory system diagnostic program, CEMKAA.
The CSR can be accessed from the processor console in the following manner:
1.

Halt all NPR activity in system.

Turn off cache 17777746 ~ 14.

Set up map 0 17770200 « 170000

17770202 « 77.
4.

Turn on Unibus map 17772516 « 40.

Turn display switch to CONSOLE PHYSICAL.

[Examine and/or deposit SCRs as addresses 17002100 through 17002136 (address is indicated on the memory box decal).

5-46

CSR FIRST WORD

“

olsie

CHECK BITS/SYNDROME BITS/

DOUBL

)

ARRAY NUMBER

BOX CAPACITY

BIT ERROR

CSR

SINGLE BIT |DIAGNOSTIC|
ERROR

CHECK

ENABLE

|PARITY TRAP

PROTECTION

ECC

POINTER

DISABLE

SECOND WORD

DOUBLE

BIT ERROR

INTERLEAVING

—~
EXTERNAL

STARTING

STARTING ADDRESS

ADDRESS
SELECT

INTERNAL
CONTROLLER
INTERLEAVING
NUMBER
MA.1483

Figure 5-8

MKI11 Control and Status Register

While running the memory system diagnostic program, the CSR can be accessed by entering the field
service mode (control F) and typing command 1 to read the CSR or typing command 2 to load data
into the CSR. Refer to the MKI11 MOS Memory Technical Manual for a description of running the
memory diagnostic.
CSR Bits - First Word
Bit 15 - Double Bit Error - When set to one, this bit indicates a double bit (uncorrectable) error was
found in a 32-bit double word fetched from an array. The array number and controller number indicating the location of the error will be loaded into the CSR.

Bits (14:8) - Check Bits — In a diagnostic mode [bits (3:1) = 010] check bits can be written to and read

from the check bit storage field on the array modules.

Bits (14:8) - Syndrome Bits — Bits 14 through 8 store the ECC syndrome bits when the ECC circuitry
encounters a single bit error.
Bits (14:8) - Box Capacity - By writing a 100 into bits (3:1), the box capacity in 32K word blocks can
then be read from bits (14:8).

Bits (7:5) - Array Number - These bits indicate the array that contained the single bit or double bit
error flagged by bit 4 or bit 15.

Bit 4 - Single Bit Error - When set to one, this bit indicates that a single bit (correctable) error was
found in a 32 bit double word fetched from an array. The array number, controller number, and
syndrome bits will be loaded into the CSR.

Bit 3 - Protection Pointer ~ For diagnostic purposes, this bit selects which 32K word bank of memory

is protected memory space. When zero, this bit indicates that the first 32K bank of each controller is
protected. When one, this bit indicates that the second 32K bank of each controller is protected.

5-47

Bit 2 - Diagnostic Check - When set to one, this bit allows the reading and writing of check bits via
SCR bits 14 through 8.
Bit 1 - ECC Disable - When set to one, this bit disables single bit error correction in all unprotected
memory space.

Bit 0 - Enable Parity Trap - When one, enables parity traps. Memory will force bad parity on Main
Memory Bus if ECC circuitry encounters an uncorrectable error.
CSR Bits - Second Word
Bit 15 - Double Bit Error - Same as CSR first word bit 15.
Bits (14:12) - External Interleaving - These bits indicate the number of ways the memory is externally
interleaved. The interleave number from the box controller interleave switch is loaded into bits (14:12)
at power up. See bit 10.
Bit 11 - Internal Interleaving - When one, this bit indicates that the memory is internally interleaved.
Bit is set to one at power up if memory arrays in frame are balanced. When zero, this bit indicates that
there is no internal interleaving. See bit 10.
Bit 10 - Starting Address Select - When zero, this bit selects the switches on the box controller as the
source of the starting address and number of ways externally interleaved. When set to one, the bit
allows writing SCR bits 14:12, 11, and 8:0 to select the external interleaving, internal interleaving, and
starting address. To write these bits, the Address/Interleave switch on the box controller must be in the
ALLOW PROG CONTROL position.

Bit 9 - Controller Number - This bit, along with first word bits (7:5), indicate the array that contained
the single bit or double bit error flagged by first word bit 4 or bit 15. A zero is for controller pair zero
(right side of frame); a one is for controller pair one (left side).

Bits (8:0) - Starting Address — These bits indicate the starting address of the memory frame in 32K
word banks. The starting address from the box controller thumbwheel switches is loaded into bits (8:0)
at power up. See bit 10.
Memory Frame Indicator Lights - Fault indicator lights (LEDs) in the memory frame are shown in
Figure 5-9. These lights are mounted near the edge of address interface (M8158), data buffer (M8159),
and control B (M8160) modules; they are visible through the opening at the front of the memory
frame.

Address Parity Error Indicator - Lights when the memory receives incorrect address parity on the
main memory bus. Indicator stays lit until the memory is powered down.
Configuration Error Indicator - Lights if MOS array modules are improperly installed in memory
frame.
Double Bit Error Indicator — Lights when the error detection circuitry encounters an uncorrectable
(double bit) error in the data during a read operation.
Memory Busy Indicator - Lights while memory controller is executing a memory cycle (read, write,
refresh). Brightness of light indicates the rate at which the memory is accessed. Light glows dimly while
controller is refreshing memory only. When off, light indicates that the controller is not functioning.

5-48

Appress
PARITY
ERROR

DOUBLE BIT
ERROR

‘

CONFIGURATION

ERROR

\\19

MEMORY BUSY

II(CONTROLAO)

M7984

M8161

M8158

M8160

M8159

M8160

M7984

{CONTROL A1)

M8161

MEMORY BUSY

08 {\

MA-1484

Figure 5-9

MKI11 Memory Frame Error Indicators

Box Controller Indicator Lights — The box controller, shown in Figure 5-10, mounts in a controller
panel near the top of the memory cabinet. It contains the following indicator lights.

Panel Selected — When lit, light indicates that the Address/Interleave switch is in the FORCE
PANEL position and that the thumbwheel switches determine the starting address and interleaving. CSR second word bit 10 is held at zero.

Uncor Error - When lit, light indicates that a double bit error was detected in memory. See CSR
bit 15.

Battery Status — These lights indicate the operating status of the three battery backup units.
ON
Fast Flash
Slow Flash
OFF

- Battery receiving trickle charge
- Battery delivering power to memory
- Battery receiving full rate charge.
- Battery off or disconnected

MEM PWR Ready - When lit, light indicates that the power supply voltages are within tolerance.
When off, light indicates that either main dc low or box dc low are asserted.

5.3.2.6 Main Memory (MJ11) Maintenance Aids - Refer to Figure 5-8, which shows the module
layout (Rev C) of the M8148 module. This module contains all the logic indicators, test points and
switches for an MJ11 frame. Seven power test points are provided on the M8149 module. Refer to
Paragraph 4.5.2 of this manual.

5-49

INTER j

[ I—- STARTING
@

LEAVE

ADDRESS —l

Bs ]

ADDRESS/INTERLEAVE
ALLOW PROG

PANEL

SELECTED

ALLOW
EN

CONTROL

UNCOR

FORCE PANEL

MEMONLIN]

ERROR

ECC

FORCE

ON__

DIS

BOX

D ©©® © V.

MEMOFF
| garreRy sTATUS
LINE

MEM
PWR

AC/

READY

MA-1420

Figure 5-10

Box Controller

The use of switches S1 and S2 is described in Paragraph 3.5.1 of this manual.

The following paragraphs describe the use of the indicators and test points. For additional maintenance information, refer to the MJI11 Memory System Maintenance Manual, EK-MJ11-MM.
Address and Control Parity Error Indicator and TP2 - MCTA WRONG PARITY is assertec when a
memory controller detects bad parity on the A and C lines, at the time that it receives START. In this
case, the controller does not respond to START and a memory bus time-out occurs. This in turn
causes the memory cycle to be aborted. The Parity Error flip-flop is set, asserting MCTA PAR ERR
(1) L. This asserts MAIN PAR ERR L on the main memory bus.

MCTA PAR ERR (1) L sets a flip-flop that lights the Parity Error LED indicator, which is visible
from the front of the memory mounting box (Figure 5-11). The flip-flop is cleared on Power-up
(MCTH RESET L asserted), or by grounding test point TP2 on the M8147/M8148 module.
TP1 - When grounded, TPI causes the memory controller to cycle continuously. A console LOAD
ADRS followed by a DEPOSIT or an EXAMINE would cause the read/write operation to be repeated until the ground is removed from TP1.

CAUTION

Do not power up memory system with TP1
grounded. To do so may cause failure of stack charge
circuitry on H217C stacks controlled by this controller. Refer to the MJ11 Maintenance Manual for
diagnostic procedures and proper use of TP1.

5-50

Mismatch Error Indicators - The MJ11 Memory Controller is designed to operate with different types
of stack module sets (16K—-MJ11-A, 32K—MJ11-B). The different types of stack modules have different control and timing requirements. The circuitry at the top center of Drawing MCTC determines
whether the 16K block being addressed resides in a 16K or 32K stack. If a 16K stack is being addressed, the 16K flip-flop is clocked set when MCTF IACK H is asserted (i.e., when the memory
controller initiates the memory cycle), thereby asserting MCTC 16K (B) H.

Stacks that operate in parallel must be of the same type. The eight Exclusive-OR gates on Drawing
MCTC check that the stack module set pairs are properly matched. If a mismatch is detected, MCTC
MISER L is asserted; this asserts MTB GO DISABLE H, which inhibits initiation of memory cycleby the memory controller, MCTC MISER L asserted also lights the Mismatch Error LED, which is
visible from the front of the memory frame (Figure 5-11).

~r
0

MISMATCH ERROR (MCTC)

PARITY ERROR (MCTA)\ i

MTCD BUSY

I Dx

81, 52

B JI

—]

TP2 RESETS MCTA PARITY

ERROR INDICATOR WHEN GROUNDED/‘

o —

1+ —@
TP1 CAUSES MEMORY TO CYCLE

CONTINUOUSLY WHEN GROUNDED (MCTD)

||—

11-3486

Figure 5-11

M8148 (MCT) Module

Configuration Error Indicator (Upper Limit Comparison) - Signals MCTB 16K BLK ADDR 2:0 H,
which represent the effective 16K block address, are applied to the A inputs of the Upper Limit

Compare ALU. The B inputs of the ALU are provided by the Memory Top Look-Up ROM. This
ROM decodes the ID signals from the stack module sets installed in the memory frame and generates

outputs that indicate the number of 16K blocks available to the memory controller. The Upper Limit
Compare ALU output MCTB ABOVE TOP L is asserted if the effective 16K block address being
accessed is greater than the number of 16K blocks available to the memory controller. If MCTB
ABOVE TOP is asserted, MCTB GO DISABLE H is asserted, thereby inhibiting initiation of a memory cycle.

The Memory Top Look-Up ROM also checks for correct configuration of the stack module sets. A
configuration error asserts MCTB CONER L, which asserts MCTB GO DISABLE, inhibiting all
memory cycles by the memory controller. MCTB CONER L lights the LED which is visible from the
front of the memory frame (Figure 5-11).
Busy Indicator - MCTD DELAY L starts the read timing sequence by turning on transistor Q1. This
shunts the +5 V at the collector of Q1 to the input of a delay line, sending a positive pulse down the
line. Taps along the delay line are located at 25 ns intervals and are labeled accordingly. The leading
edge of the pulse asserts MCTD RDLY 0 H through MCTD RDLY 350 H as it travels down the delay
line. MCTD RDLY 350 H is fed back and turns transistor Q1 off, thereby terminating the positive
pulse. The width of the pulse traveling down the delay line is thus fixed at 350 ns. This means that the
outputs at all the delay line taps are also 350 ns pulses. The signals output from the delay line are
buffered by type 74S04 inverters to provide clean TTL-compatible signals with sufficient drive. The
buffered outputs of the delay line are MCTD RT 0 through MCTD RT 350. MCTD RD 0 L direct sets
the Busy flip-flop, which inhibits the memory controller from initiating memory cycles while the present cycle is in progress. The BUSY LED indicator (Figure 5-11) is set by the Busy flip-flop.

5.3.2.7

Unibus Map Response Switches (M8141-MAPF) - Jumpers W1 and W3-W6 (MAPF HIXX
JUMPER H) determine the upper limit of responding Mapping registers to be compared with the
Unibus address.

Jumpers W2 and W7-W10 (MAPF LOXX JUMPER H), are the lower limit of responding Mapping
registers to be compared with the Unibus address.
In standard configurations, the HIXX jumpers are all 1s, and W1, W3-W6 are OUT; the LOXX
jumpers are all Os, and W2, W7-W10 are IN. This allows the Unibus Map to accept Unibus addresses
000 000 through 757 7717.

Table 5-4 shows the limits that can be obtained by the jumper configurations. Note that if the HI
jumpers are all Os (IN), or if the LO jumpers are all 1s (OUT), no response can be obtained from the
Unibus Map.

5.3.2.8 AC LO and DC LO Indicator - The Power Line Monitor/15 V Regulator Module (D-CS5411086) contains two LED indicators which are ON when AC LO or DC LO are not asserted
(=power OK).

In the MJ11, they may be observed through the ventilation slots in the AC input box. In the CPU
cabinet, the H7420 power supply must be opened to observe these indicators. Refer to Paragraphs
4.5.2 (MJ11) and 4.5.3 (H7420) of this manual.
WARNING
Power must be shut off by turning the console key to

OFF

before assembling or disassembling the H7420.

Figure 5-12 shows the location of these indicators on the 5411086 module.

5-52

Table S-4

MAPF
HI(17:13)
JUMPER H

(OCTAL)

Unibus Map Limit Jumpers (MAPF)

MAPF
LO (17:13)
JUMPER H

Highest
Possible Unibus

Address

(OCTAL)

Lowest
Possible Unibus

Address

37
36
35
34
33
32
31
30

757 777
737777
717777
677 777
657777
637777
617777
577777

37
36
35
34
33
32
31
30

None
740 000
720 000
700 000
660 000
640 000
620 000
600 000

27
26
25
24
23
22
21
20

557777
537777
517777
477777
457 777
437777
417 777

377777

27
26
25
24
23
22
21
20

560 000
540 000
520 000
500 000
460 000
440 000
420 000
400 000

17
16
15
14
13
12
11
10

357777
337777
317777
277777
257777
2377717
217777
177777

17
16
15
14
13
12
11
10

360 000
340 000
320 000
300 000
260 000
240 000
220 000
200 000

07
06
05
04
03
02
01
00

157 777
137777
117777
077 777
057 777
037 777
017 777
None

07
06
05
04
03
02
01
00

160 000
140 000
120 000
100 000
060 000
040 000
020 000
000 000

5-53

DCLO

O 5

Yea god

ACLO\\%LS\,EJQ ©
S08

.....

ool

.....

CONNECTOR "’"—”]D[Ll

J\]fl

NOTE:

11-3489

5411086-YA indicators are
similarly located.

Figure 5-12

5411086 AC LO and DC LO Indicators

5.3.2.9 Sync Points - The microaddress in the Microprogram Break register (17 777 770) generates a
sync pulse (TIGB PB SYNCH H) at T1 at pin F13K2 each time the cycle corresponding to the address
is executed. PDRC PB CMP H generates a pulse whose width is the same as that of the microstate (pin
A10E1).

5.3.3 How to Use Maintenance Cards
The maintenance card that is used to perform maintenance tests and troubleshooting procedures on
the PDP-11/70 system is shown in Figure 5-13. The maintenance card is constructed from a W131
Maintenance module. The W131 is used with a W133 Driver module. Figure 5-11 shows the overlay
that is used to designate switches and indicators for KB11-B, C and FP11-B test functions.

NOTE
The maintenance card is not used with the FP11-C,
since it operates synchronously with the processor
and has no RC clock.

5-54

The indicator lamp functions and the sources of the inputs from the KB11-B, C and FP1 1-B follow:

Indicator

Source
KB11-B,C

TPH

TIGA TPH MAT H

Signal Description
FP11-B

FRHJ MSTEP
CLOCK (0) H

KBI111-B,C:
Basic processor timing pulse,
whether crystal clock,
RC clock, or MAINT
STPR is selected.

FP11-B:
Indicates
MAINT STPR clock
pulse.
T1 through TS5

TIGA (T1:T5) MAT H

FRHH (T1S:T4S) H

Indicate major time
states for KB11-B,C and
FP11-B. TS5 is not used
for FP11-B.

BUST

UBCE BUST MAT H

KB11-B,C bust cycle.
Not asserted by FP11-B.

MEM

TIGA MEM SYNC H

TIGA MEM SNC H

Indicates the completion
of a memory cycle.
Asserted by CCBC
MEM SYNC H.

AF2/BF2
AH2/BH2

No connection
No connection

Spare indicators. Inputs
at pins F2 or H2.

SLOW CYCLE

CCBD SLOW
CYCLE MAT H

ry cycle referenced main

Indicates that the memomemory.

BBSY

UBCA BBSY MAT H

5-55

Indicates Unibus is busy.

7545-6

Figure 5-13

Maintenance Cards: for FP11-B (Top) and
for KB11-B,C (Bottom)

5-56

|BUST

TS5

TPH |_F T

AST
mem | ACT

sync| Req

|ATTN | wArT | BF2

| acrr
P | FP | FP | FP | AF2 || AH2
BH2

TLENFZ

[FY

PAR

|Eerr[SERF

IFC

xTaL
54

Eang

CLK

RrRC

MAINT

STPR =»

PB
iU
4%

]o]1

roM

|1 1o

cveL
1

SING

7413772-01

11-3288

Maintenance Card Overlay

Figure 5-14

Signal Description

Source

Indicator

FP11-B

KB11-B,C

MSYN

MAPB MSYN B
MAT H

MAPB MSYN B
H
MAT

Indicates Unibus Master
Sync is asserted.

SSYN

UBCB SSYN MAT H

Indicates Unibus
Sync is asserted.

CNTL OK

TMCE CONTROL
OK H

TMCE CONTROL

Asserted by processor to
allow memory cycle to be
completed.

FP SYNC

UBCD FP SYNC H

UBCD FP SYNCH

Indicates that the FP11-B
is ready to send or receive
data. Asserted by FRMJ

OK H

Slave

FP SYNC L.

FP REQ

RACK FP REQ H

Used with FP SYNC to
indicate to CPU that
more data words are
required. If FP SYNC is
returned to CPU without
FP REQ, the memory
cycles are terminated.

FP ATTN

UBCD FP ATTN H

Decoded from CPU
ROM states where MSC
= 5, indicating floatingpoint instruction has
been decoded.

FP WAIT

FRHH WAITS H

Represents the Wait state
of the FP11-B.

5-57

Indicator

Source

Signal Description

KB11-B,C

FP11-B

AC1/BCl

No connection

AERF

TMCC AERF MAT H TMCC AERF MAT H

Indicates state of KB11B,C Address Error Flag.

SERF

TMCC SERF MAT H

Indicates state of KB11B,C Stack Error Flag.

PAR ERR

UBCB PARITY

ERR MAT H

Indicates

TMCB PS04 MAT H

Indicates processor status word trace bit is set.

IRCH MAT N H

FRL
FN (1)
P
H

KB11-B,C: N (negative)
bit of the CPU Processor
Status Word condition
code.

No connection

Spare indicator, input at
pin Cl.

Unibus or
memory has detected a
parity error.

FP11-B: N bit of the FPP
Program Status register.

IRCH MAT Z H

FRL
FZ (1)
P
H

KBI11-B,C: Z (zero) bit of
the CPU Processor Status Word condition code.
FP11-B: Z bit of the FPP
Program Status register.

IRCH MAT VH

FRLP
FV (1) H

KB11-B,C: V (overflow)
bit of the CPU Processor
Status Word condition
code.
FP11-B: V bit of the FPP
Program Status register.

IRCH MAT CH

FRLP FC (1) H

KBI11-B,C: C (carry) bit
of the CPU Processor
Status Word condition
code.
FP11-B: C bit of the FPP
Program Status register.

5.3.3.1
Clock Selection - CLK switch S3 is used to select the crystal clock (XTAL), the RC maintenance clock (RC), or the MAINT STPR switch as the timing source for the CPU or FP11-B.
CPU
timing and FP11-B timing are independent; thus, the switches on each maintenance card need not be
set for the same selection when two cards are used.

5-58

When set to XTAL, the 33.3 MHz crystal clock is selected for the CPU timing source and the 18 MHz
crystal clock is selected for the FP11-B. When the CLK switch is set to RC, the variable frequency RC
maintenance clock is selected as the timing source. By adjusting the potentiometer, the useful range of
the period of the RC maintenance clock pulse can be adjusted as follows:
KB11-B,C RC Clock: 28 to 50 ns
FP11-B RC Clock: 50 to 290 ns
NOTE

When using both CPU and FP11-B RC clocks, half
of the FP11-B clock period must be shorter than two

CPU ROM cycles. The FP11-C does not have a vari-

able RC clock.

5.3.3.2 Maintenance Mode Control — Maintenance card switches S2 and S1 are used to select the
Maintenance mode, as indicated below:

Mode

Operation

NRM OP

No effect on KB11-B,C or FP11-B operation.

uPB STOP

The KB11-B,C or FP11-B will execute instructions until the micro-

program ROM address matches the contents of the Program Break
(PB) register. It halts at T2 of that ROM state.

ROM CYCL The KB11-B,C or FP11-B will execute a single ROM state each time the

SING TP

MAINT STPR is pressed.

The basic clock changes state each time the MAINT STPR is pressed.
Pressing MAINT STPR twice provides a single time pulse.

Single ROM Cycle - When Switches S1 and S2 are set for single ROM Cycle mode, the processor
executes a single ROM cycle each time the console CONT switch is pressed. For convenience, MAINT
STPR switch S4 on the maintenance card can also be used to initiate the single ROM cycle. In this
mode of maintenance operation, the processor stops in T2 of each microstate.

MPB STOP - If CONT is pressed when switches S1 and S2 are set for PB (microprogram break) Stop
mode, the KB11-B,C or FP11-B execute program instructions until the ROM Address register contents match the CPU Program Break (PB) register contents. When both microstate addresses are
equal, the processor stops in T2 of the selected microstate. At that point, S1 and S2 can be set for
SII}IG TP mode as described in Paragraph 5.3.3.3. Load the PB with the desired microprogram address
as follows:

Press HALT switch. Processor halts at microprogram CON.00 (CPU uADRS 170).

Set PB register address 17 777 770 into console Switch register.

Press LOAD ADRS. ADDRESS: Display will be 17 777 770.

Set desired microprogram break address into the low byte of the Switch register. For
example, to stop at IRD.00, set 343(8) into the Switch register.

5-59

Press DEP. The DATA display will display this input in the low order byte with the Data

Display Select switch set to DATA PATHS.

Set Maintenance module switches for PB STOP (S1=1, S2=0).

Press CONT. The processor executes program instructions until the RAR equals the PB,
then stops.

Single Step — When switches S1 and S2 are set for SING TP mode, gating logic shown on drawing
TIGB inhibits the source synchronizer from selecting either the crystal clock or the RC maintenance
clock. Under these conditions, each time MAINT STPR switch S4 is pressed, TP H changes levels.

NOTE
MAINT STPR must be pressed twice to complete
each time pulse. This feature allows events that occur

on the leading edge or trailing edge of the same time
pulse to be examined separately.

5.3.3.3
Using the Maintenance Card with KB11-B,C - Section II, Chapter 1 of the KB11-C and KBl |B Processor Manuals explains how to use the processor flow diagrams; an instruction example is also

provided to familiarize the reader with the sequence of machine states used to execute a typical instruction. The same compare instruction example is used to demonstrate how to use the maintenance card
for test purposes. Section II, Chapter 4 of the KB11-C and KB11-B Processor Manuals describes the
maintenance board control logic on the M8139 module (TIG). Section III of the same manual explains
the console logic in detail.

Deposit Test Intruction — Set the Address Display Select switch to CONS PHY, load address 1000, and
deposit the following:
Address

Data

Comments

1000

022767

1002

Compare instruction

000015

1004

000100

Destination operand indexed

1106

000000

Word =0

Source operand immediate

Set up the PB for a PB STOP at IRD.00 (CPU ADRS 343).
Load address 1000(8).

uPB Stop Mode

Set maintenance card switches $1 and S2 for PB STOP mode. (S1=1, S2=0)
Set ENABLE/HALT to ENABL and press START.

5-60

The processor stops at Ird.00 (343), in T2. The table below shows normal console indications as a
result of these events.

Contents (octal)

Console Display
ADDRESS:

DATA.:

CONPHYS

1002

DATA PATHS

1002

BUS REGISTER
wADRS FPP/CPU

022767
343*

PAUSE

Maintenance card indicator T2 lights.

*In Low order.byte.
Single ROM Cycle Mode - This setup causes the processor to execute one ROM cycle of the test
instruction and stop in timestate 2 each time MAINT STPR switch S4 is toggled.
1.

Set Maintenance Card switches S1 and S2 for single ROM Cycle mode. (S1=0, S2=1).

Press Maintenance Card MAINT STPR switch S4 or CONT switch on the console.

The table below lists normal ADDRESS and DATA displays resulting from each ROM cycle execution, starting with IRD.00, T2 of the example test intruction.
ROM pustate

IRD.00

Bus Register

343

1002

022767

251
122

1106
15

100
100

S13.00
S13.10
D67.80
D67.00

021
027
117
006

D10.60

177

D67.10
D10.30

TST.10

Console Display

Data Path

uwADDRS CPU|

033

022767
022767
15
15

1004
1004
15
1006

177762

Address CON PHYS

1002

1002 (BUST)**
1002 (CNTL OK)**.
1004 (BUST)**
1004 (CNTL OK)**
1004
1106 (BUST)**
1106 (CNTL OK)**
1006

*1’s complement of 15(8).
**Maintenance Module Indicators

SING TP MODE - This procedure allows the maintenance card user to step through microstates of
N

the test instructions example in the SING TP mode.
Set S1 and S2 to.

Set ENABL/HALT to HALT and press START.
Load the example instruction address 1000.

Set Maintenance Card switches S1 and S2 to uPB STOP mode. (S1=1, S2=1).
Set ENABL/HALT to ENABL and press START.

5-61

When the processor stops at T2 of FET.10 (CPU pADRS 260), set S1 and S2 to select SING TP mode.
Then press MAINT STPR switch S4 twice to step through each time state.
NOTE
The T1 through T5 indicators on the Maintenance
module are driven by the T1-TS flip-flops on TIGA.

Thus, a time pulse is only asserted when both its
associated indicator and the TP H indicator are on.

5.4
PDP-11/70 DIAGNOSTICS
The principal PDP-11/70 diagnostic programs are briefly described in this paragraph.
NOTE
1.

During an installation, the stand alone diagnos-

tics described in Paragraphs 5.4.2-5.4.5 and 5.4.8
and 5.4.9 should all be run immediately after loading

XXDP (Figure 3-9).

2.
During a service call in which the failure is not
obvious, the Subsystem Diagnostic (Paragraph
5.4.7) should be run; this program will then point to
the stand-alone diagnostic(s) related to the area of
the system that is failing (Figure 5-1).

54.1
PDP-11/70 XXDP
XXDP is a catch-all name for a group of binary packages available for loading devices

3-9.

All XXDP packages require a console device (teletype, LA36, VTO05), and
age media.

listed in Figure

one of the diagnostic pack-

The above requirements are for loading and running diagnostic programs already

stored in one of the
diagnostic package media. They are also sufficient for implementing permanent patches
on programs
when required.

The XXDP monitor is loaded via the M9301-YC bootstrap module.

Complete documentation is contained in the XXDP user manual, MAINDEC-1 1-DZQXA.
A programming card, MAINDEC-11-DZZPA is also available.
Disclaimers — The XXDP packages have been designed for diagnostic purposes
only. The software
used is not intended to be compatible with any other PDP-11 family software, any non-diagnost
ic uses
of the software, or uses of the software in other than the manner described in the XXDP user
manual
are not supported.

The XXDP packages are binary packages only. They provide the PDP-11 family diagnostic
programs
in the various media described. Documentation for each of the programs stored in
a XXDP package
must be obtained separately. However, said documentation must be obtained at the
same time as the
package, in order to ensure that the documents and the programs match.

5-62

Contents of an XXDP Package - The basic parts of an XXDP package are:
1.

A control program referred to as the monitor. The monitor provides the means to load
programs under keyboard control, to obtain a directory of contents of the XXDP medium
(DECtape, Magtape, etc.), to duplicate the medium, and to make up Chains of programs to
be run sequentialy under Chain mode.

XXDP Update Program 1. This 4K program provides the means for modifying and updating the programs in the XXDP package. It is intended for use in 8K systems.

XXDP Update Program 2. A 6K program that provides a more comprehensive set of commands that provide more convenience and ease of updating the XXDP package.
The PDP-11 Family Diagnostic programs themselves, including DEC/X11 exerciser (Paragraph 5.4.6).

PDP-11/70 Stand Alone CPU Diagnostics

5.4.2

5.4.2.1 DEKBA and DEKBB (CPU Diagnostics parts 1 and 2) - DEKBA /B are programs designed to
detect and report logic faults in the PDP-11/70 Central Processing Unit. They consists of 210(8)
individual tests carefully designed and sequenced to detect and attempt to identify logic faults at a
minimum hardware/software level. These tests are partitioned into two stand alone programs as described below.

Basic Instruction Test

DEKBA consists of a logially sequenced set of instruction tests designed to verify the integrity of those intructions and logic operations used by the utility routines that provide error
reporting and scope looping facilities for DEKBB.

Any fault detected in this program causes the program to HALT with the console address
lights indicating the error program counter and the console data lights showing the test
number (for tests 24 and above). Additional fault identification information is available in
the program annotation for the failing test.

If the program halts at location 6 or 12 (address lights of 10 or 14), the program annotation
for the indicated test number should give a clue to the problem. To loop on the error, the
halt must be replaced by the octal code shown in the comment field of the HALT and the

program restarted at 200, or the start address of that particular test.
Advanced Instruction and Miscellaneous Logic Test

DEK BB consists of a logically sequenced set of instruction tests followed by a set of miscellaneous logic tests. The instruction tests complete the test of the PDP-11/70 instruction
repertoire. The logic tests verify such things as:

R0
Qe o

The internal registers
Register set 1
Internal interrupts
Bus request levels 4, 5, and 6
Internal traps and aborts
Other mode selection
External traps and aborts

5-63

Each test in this program calls a SCOPE LOOP utility that makes user control of test
selection and execution via the console Switch register easier.
Upon detection of a logic fault, each test in this section calls an ERROR SERVICE that

reports it as hard copy on the console terminal device. The error service routine also facilitates user control of the program sequence via console Switch register options. A fter reporting the error, the program continues on its normal sequence unless modified by the user
activating the HALT ON ERROR switch option.
3.

Important Note
The program annotation in DEKBA and the typed error reports in DEKBB are based upon
the knowledge that all previous tests were faultless and that there is only one single point
failure in the processor. This means that if either program, or the programs themselves, are
not run in sequence, the error message may not be valid.

Although each error annotation and typed message conclusion has been proven by physical
fault insertion (one signal stuck low), it is humanly impossible to guarantee that error report
is 100% correct. The sole function of the error report is to direct the user to the most probable area of failure.
5.4.2.2

DEKBC and DEKBD (Cache diagnostic parts 1 and 2) - The programs, DEKBC and
DEKBD, are intended to be used as aids for the repair and maintenance of the cache memory system

in the PDP-11/70 computing system. The aim is to detect and report failing components of the cache

unit. The failures are typically identified with a failing circuit when the report is made, but the overall
diagnostic philosophy has been to locate the failing module (hex board) of which there are four in the
cache unit. Note that when a failure is reported and the associated circuit identified, that circuit should
not be taken in blind faith as the defective component; the identified component should rather be
taken as the probable cause of the falure. There are four modules (hex boards) in the cache unit:

CCB
CDP
ADM
DTM

Cache Control Board
Cache Data Paths Board
Cache Address Memory Board
Cache Data Memory Board

The program DEKBC is designed to test the first two of these boards; the program DEKBD
is
designed to test the last two boards. Note that though the testing has been divided into two stand
alone

programs, each associated with two modules, it should not be assumed that a particular
module is

working after having run only one of the programs. Both programs should be run. For example,

just
running DEKBC without error does not rule out a faulty component on the CCB (Cache
Control)
board. To put it more simple, the testing has been divided into programs only because of the
restrictions of core size, and not to provide a means of testing two of the boards with one program
and the
other two boards with a second program.

NOTE
DEKBD is designed to run after DEKBC. If this
hierarchy is not heeded, that is, if DEKBD is run
before DEKBC, then the error reporting from
DEKBD cannot be strictly interpreted.

5-64

5.4.2.3 DEKBE (Memory Management Diagnostic) -This program will test all of the memory management logic and enable the field service represenative to isolate the detected failures to a replaceable
module. It is'assumed that both the CPU and the cache have been tested, or are known to be functioning correctly, and that the program is started from address 200. This will provide the earliest detection
of memory management related errors and enable looping on the error involving minimum logic. This
program may also expose faults that are on the interface between Memory Management and other
sections of the computer.

This program has been segmened in the following way: All data tables, error mssages, and subroutines
reside in low core (virtual pages 0 and 1 i.e., addresses 001100 through 037776). Right now the end of
the subroutines is around 025000, so there is some room for future expansion. The test code starts at
virtual page 2 (address 040000) and expands toward page 4 (address 100000). The end of the program
is now around address 074000, so modifications can be made without resegmenting the program.
This program has been segmened in the following way: All data tables, error mssages, and subroutines
reside in low core (virtual pages 0 and 1 i.e., addresses 001100 through 037776). Right now the end of
the subroutines is around 025000, so there is some room for future expansion. The test code starts at
virtual page 2 (address 040000) and expands toward page 4 (address 100000). The end of the program
is now around address 074000, so modifications can be made without resegmenting the program.
The reason for this segmentation is two-fold. Fist it enables the operator to tell from the address lights
exactly where the program has halted or hung-up. That is, did it halt in the error routine or in a trap
routine because of a condition impossible to recover from (on page 0 or 1), or did it get hung-up in the
test code on page 2 or 3. The other reason is that certain memory management functions lock up the
virtual PC of the instruction and the program, and in order to operate properly, one must know where
it is at all times. It seems much simpler for the code to start at a predetermined boundary so that if the
messages change or a new subroutine is added, the page that the code is on will remain the same.
Each test will set the loop on error pointer (SLPERR) to the minimum necessary setup code, if any, for
the function under test. A synchronization instruction (NOP) is provided before the intruction(s) that
test(s) each new function. This will enable the field service representative to utilize the Micro Break
register to generate an External Sync pulse on the backplane for better pulse resolution.
It should be noted that this program does not check out the console or the console cables that plug into
the memory management boards. The program assumes that those components have been tested or are
known to be good.

5.4.2.4 DEKBF (Unibus Map Diagnostic) — This program is designed to be run on a PDP-11/70 on
which the CPU, cache, and memory management diagnostic programs have been run. The program
will detect all errors that originate with the Unibus Map and provide looping capabilities so that the
field service engineer can verify the failures. There may be some cases, such as the Cache register data
path, and cache memory data path, where interaction between modules prohibits close isolation, but
the failing function will be called out so the field service engineer can complete the isolation process.

If the program catches an error in an early test and is allowed to continue running through the later
tests, the error indications from those later tests may be invalid. This is due to the structure of the
program, which assumes that all areas tested prior to the current test are functioning properly.

The error type-outs will be in table format, with a message indicating the class of error, a header
identifying each column, and a report of all pertinent data. When the test can produce more than one
error condition, a summary of errors will be given at the end of that test consisting of: The logical
AND and OR of the data previously reported, and the number of errors in this test.

5-65

The program loads 044 into the Micro Break register (17 777 770) so that a sync pulse is generated on
pin A10El and F13K2 every time a NOP is executed. This should help to isolate the exact timing of
bad or missing signals. Refer to Paragraph 5.3.2.8.
5.4.2.5

DEKBG (Power-Fail Test) -This program is made up of 16 subtests to check out the power
fail on the PDP-11/70. The 2 ms power down and power up time is checked on each power fail.
Initially, power fails are tried in all processor modes, then error conditions like Red Zone, Yellow

Zone, Timeout, and Odd Address are tried in all the processor modes. Finally, a power fail is done
with memory management aborts occurring and a memory volatility test is run on all available memory.

5.4.2.6

DEQKC (11/70 Instruction Exerciser) - This Diagnostic Program is designed to be a comprehensive check of the PDP-11/70 processor. The program executes each instruction in all address
modes and includes tests for traps and the Teletype® interrupt sequence. The program relocates the test
code throughout memory 0-512K. If selected, the program may be relocated by any of the available
disks.

5.4.2.7 DEMJA (PDP-11/70 Memory Test) - Program DEMJA tests contiguous memory address
from 000000 to 17757776. It verifies that each address is unique (an address test) and that each merory
location can be read/written reliably (worst case noise tests). This program may be used to adjust/margin memory.

5.4.2.8

CEMKAA (PDP-11/70 Memory Diagnostic) - This program tests both MK
11 memory systems and mixed memory systems containing both MJ11 (core) memory
and MK11 (MOS) memory

frames. Configuration maps and error printouts isolate memory faults to the
board level. A field
service mode allows test operations to be run directly from a terminal.
5.4.3

RWP04 Diagnostics
DERHA

DERPK
DERPL
DERPM
DERPN

DERPS
DERPT
DERPU

DERPV

RH70 Controller Diagnostic
Read/Write and Mechanical
Formatter program
Head Alignment Verification
Multidrive Exerciser
Diskless Controller Test (Part 1), Static 1

Diskless Controller Test (Part 2), Statis 1
Functional Controller Test (Part 1), Static 2

Functional Controller Test (Part 2), Static 2

Refer to appropriate MAINDEC documentation.

®Teletype is a registered trademark of Teletype Corporation, Skokie, Illinois.

5-66

5.44

RWS03 or RWS04 Diagnostics

DERHA
DERSA
DERSB
DERSC
DERSD

RH70 Controller Diagnostic
Basic Function Test
Data Reliability
Diskless (RS03)
Diskless (RS04)

Refer to appropriate MAINDEC documenation.
5.4.5

TUI16 Diagnostics

DERHA
DZTUA
DZTUB
DZTUC
DZTUD
DZTUE

RH70 Controller Dignostic
Data Reliability
Basic Function Diagnostic
TMO02/TU16 Control Logic Test
TMO2 Drive Function Timer
TU 16 Utility Driver

Refer to appropriate MAINDEC documentation.
5.4.6 PDP-11/70 DEC/X11
DEC/X11 is a comprehensive, easy to use software system that provides the user with the means to
generate, run, control, and update interactive hardware system exerciser programs for PDP-11/70
systems.

Because of the dependency of the DEC/X11 software on the XXDP diagnostic package software, the
user is urged to become thoroughly familiar with the uses of the XXDP packages. Refer to XXDP User
Manual, MAINDEC-11-DZQXA.
DEC/X11 is documented in the DEC/X11 User's Documentation and Reference Guide, MAINDEC11-DXQBA. A programming card, MAINDEC-11-DZZPA is also available.
5.4.7 PDP-11/70 Subsystem Diagnostic
The objectives of the PDP-11/70 subsystem diagnostics are:

To check the complete CPU cluster of the PDP-11/70 system. This cluster includes: CPU,
cache, memory management, Unibus Map, and all of main memory, and will also ensure
that the Unibus and Massbus are capable of performing data transfers.

To find subsystem problems within the CPU cluster and, through error analysis, attempt to
isolate these problems to the failing subsystem.

To allow quick verification of a questionable system or to ensure the integrity of a newlyrepaired system.

This program is intended:

To allow the Field Service Engineer to logically attack a problem on a system’s level.

To allow rapid isolation of a problem in order to minimize MTTR (Mean Time To Repair).

To allow quick verification of a questionable system or to ensure the integrity of a newly
repaired system.

5-67

The operator selects elements that are run under the PDP-11/70 system diagnostic, which in turn is a
module run under the DEC/X11 monitor. Errors ocurring in the CPU cluster are analyzed. The results
of this analysis, if errors are relatively concrete, will be isolation to some subsystem. Unibus and
Massbus device transfers are attempted and any errors are reported. Errors are also logged and
analyzed in an attempt to provide further isolation through the use of the stand alone diagnostics.
This program assumes that the diagnostic boot ROM (M9301-YC) has run successfully and that a
successful load has occurred via the XXDP device.

The subsystem diagnostic programs are fully documented in MAINDEC-11-DTUMA..
5.4.8 DZKWA (Line Clock Test)
This program tests the KW11L line frequency clock. It validates proper operation under both Interrupt and Non-interrupt modes. It requires the operator to monitor its operation with a clock capable
of measuring time in seconds.
5.4.9 DZKLA (TTY or DECwriter Test)
This MAINDEC consists of a package of test programs designed to test an ASR33, KSR33, ASR35,
or KSR35 teletype when attached to a PDP-11 system through a KL11 or DL11A teletype control. All
tests are included in a single object tape.
NOTE
The following programming format is illegal and is
not used in this program: message, filler, filler, reset,
and another message immediately.
The available test programs are listed here in numerical order:
PRG0O0

Combined Input-Output Logic Tests

PRG1

Reader Test

PRG2
PRG3
PRG4
PRG5
PRG6
PRG7
PRG10
PRGI11
PRG12
PRG13
PRG14

Printer Test
Punch Test
Keyboard Test
Combined Reader-Punch-Printer Test
Reader Exerciser-Special Binary Count Pattern
Printer Exerciser
Special Binary Count Pattern Tape Generator
Punch Clock Adjustment Routine
Reader Clock Adjustment Routine
Maintenance Mode Single Character Data Test
Maintenance Mode Special Binary Count Pattern Test

Programs PRGO through PRG35 are the actual teletype tests.

Programs PRG6 through PRG14 are utility and maintenance routines.

5.4.10 Maintenance Program Generator (MPG)
MPG (MAINDEC-11-DTUMA) is a compiler that uses english language statements. It provides hardware oriented technical personnel with the ability to easily generate and execute programs on the PDDP11 series of computers. While these programs may be written to perform any type of task, the major
applications expected are programs that aid in the maintenance and repair of peripheral devices.

The XXDP Update Program 2 (UPD2 - MAINDEC - 11-ZQUB) is used for certain MPG media
maintenance and creation functions. In addition, MPG uses the XXDP media and therefore is preceded by execution of the applicable XXDP Monitor.

5-68

Related Documents — For details concerning the operation of the XXDP monitor and the UPD2
program, refer to the XXDP User’s Manual (MAINDEC-11-DZQXA).
A catalog of selected MPG User programs will be provided in the MPG User Program Manual
(MAINDEC-11-DTUPA). These will be programs developed by MPG factory and field users.
5.4.11
M9301-YC and DEKBH
This paragraph contains both a listing of DEKBH, the ROM program contained on the M9301-YC,
and a brief description of the interaction between DEKBH and the logic on the M9301.
The operation of the bootstrap module is described in Paragraph 3.4.2.
M9301/DEKBH Interaction - Refer to schematic D-CS-M9301-0-1 and to the DEKBH listing, which
is reproduced at the end of Chapter 5.

The M9301 is a Unibus device which responds to addresses 17 765000 - 17 765 776 and 17 773 000 - 17
773 776. The starting address is loaded (17 765 000) and, when START is pressed on the K11-B
console, this address is decoded by the logic on sheet 3 of the schematic. When MSYN is received,
ENAB DATA and 765XXX L are asserted, and the first ROM word is read by the processor; this is
the first instruction of DEKBH.
Instructions are read from the ROM and executed in the following order (refer to DEKBH listing in
Chapter 5):
1.
2.

17765000 - 17 765 776 (diagnostic)
17773 606 - 17 773 776 (diagnostic)

17773 000 - 17 773 604 (bootstrap)

Location 17 765 772 contains a JMP to 17 773 606 at which time 773XX L is asserted. Location 17 773
774 contains a JMP to 17 773 000. 773XXX L also asserts ENAB DATA and allows the bootstrap
portion of DEKBH to be executed.
If the diagnostic portion of the program finds an error, the program halts. Refer to Chapter 5 for an
explanation of the use of the diagnostic.
Default Device and Drive - Refer to line numbers 716-724 of the DEKBH listing and to the lower right
of sheet 4 of the schematic.

Line 715 moves the low order byte of the Switch register
to RO. If RO is not equal to 0, the
program branches to 18 (line 724), where RO is moved to R4 and then decoded into device
and drive parameters.

If RO is equal to 0, the program does not branch (line 717), but moves the contents of the
updated PC (17 773 024) to RO, then increments the PC and executes the next instruction,
ASR RO, (line 723), which shifts the contents of location 17 773 024 right one bit. This
location reflects the setting of S1-3 through S1-10 on the M9301-YC.

ENAB JUMP L is asserted when bits (08:01) of the Unibus address lines equal 024 octal, and the high
order Unibus address is not 765 octal. If the program calls for 17 773 024 (step 2 above), 773XXX L is

~asserted, as is ENAB DATA L; the ROM data word [ROM D(15:01) L] at location 17 773 024 is 0.
The 7402s on sheet 4 of the schematic are all asserted (outputs high); they enable the 8881 Unibus
drivers for BUS D(08:01).

5-69

If any of the switches S1-3 through S1-10 are OPEN (off), the Unibus driver to which it is

the input, is then asserted (low=1).

If any of the switches S1-3 through S1-10 are CLOSED (on), the Unibus driver to which it
is the input, is not asserted (high=0) since ENAB JUMP L is asserted (low) and disables the
Unibus driver.

The data from the switches is output on BUS D(08:01) L. This is the reason for the ASR on
line 723 of DEKBH.

NOTE
The preceding logic description corresponds to Rev F
of the M9301. Rev E logic is slightly different, but
overall operation is identical. Note also that the
DEKBH program is the same in both revisions, but
the ROMs are different. Check the revision before
ordering spares.

5.4.12
M9301-YH and 60BOOT
The ROM program contained on the M9301-YH is called 60BOOT. For the M9301-YH, consult the

bootstrap and diagnostic listing, 60BOOT LST. A current listing of 60BOOT is included in the documentation package supplied with the processor.
5.4.13
M9312 and DIAROM
The M9312 Bootstrap and Terminator Module contains the diagnostic ROM program DIARCM. For

the M9312, consult Section II of the listing, DIAROM LST. A current listing of this diagnostic program is supplied with the documentation package shipped with the processor. Program listings for the
bootstrap ROMs are supplied with the individual ROMs

5-70

ECEECEEEEEREREE
EEEEEEEEEEEEEEE
EEEEEEEEEELEEEE

popoNoooONAnD
nDoODDDDDNNOD
npoponpopNILD

EEE
EEE
EEE
EEE
EEE
EEE

DDD
non
non

noo

nop
noo
N0

noo
000

non
nan

200

nan

noo

nnn
nan

EEEEEELEEEEE
EEEFEEEEEEEE
ECEEEEEERELE

nan

aJali]
nn

Varsion

#START#®

Jser

6(344)

2L1R0FpGER

will

MENAMEQG

KKK

WHMH

HHH

HHM

AAAAAAAAA

AAA

AAA
AAA

KKK

838

AHH

HHM

AAA

KKK

guy

838

wHH

HH
M

KKK

- 1e1-)

834

WHH

HHH

NHHHHHHHHHEHHHA

AAA
AAA
AAA

AHHHHHHBMHHHHRHHH

AAA

RN
HAHHHHHHHHMH

AAA

HEBHBBBREE3H3
BHYHBEBBEBEIBI
gHEHERBRE3IBA

WHH

HHH

WHH

AAARAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAA
AAA

KKK

+1-1. ]

838

KKX

KKK

HHE

#38

WHH

gy
gHB
1.1,

H3g

WHH

4HH

838
838

WHH

KKK

KK¥

KKK

ARA
AAALAAAAAAAAAAA

HHBHERBBEAY3
gHEHERBREILT
HHBBHRBRESYA

HHH

AAA
AAA

WHH

AAA

dHH

HHH

AAA

HHH

AAA

WHH

AAA

SSS

SSESSSSSS
SSSS58S5845S
SS$SSSSSS
$5S
8§58
S8S

S9S
$8S
S8$S
SSSS5S8595488S

]
L

>t
e

Gk Gt Gt Bt

S—d bt
i
r—t
g
G

et Gt Pt Bt Gt

KKK

L1
1.1

HHH

$SSSESSSSSSsR

et Bt

Gt Demf oed
d

KKK

NHH

SSSSSSSSE8SsS

Gt Dot Gl Bt Gt

KKK

g3
g3s
838

P
Gt Bt

et St Bt

gB8

AAAAAAAAA
AAAAAAAAA

SSS
SS$
§SS

Ot
Qe

HHBHBHBBBRER

WHHH
HHM

SSS

L
I ad

bty

Rynning

[4U4%,3193]

("5/>

KKW

KKK

HHM

WHH
dHH

S5555535888S

SSSSSSSSSSSS
SSSS$SSSESSSS

(P10
T
Jyob

DEKBHA

Hequest created; 18=Jyn=75
17100110
Fljet JMLIVINEKE
1A LIST444,35143] Created:
2UEUE Swltches:
JPRINTARRJW /F ILESASCL]
Flle

KKK

WM H

SSS

Gt W
Bt Pt

Gt Bt

Bt B
Ot Pt

Pt Gt Bt Pt B

LPTSPL

D=t

CLLLLLLLLLLLLLL
LLLLLLLLLLLLLLL

——
>

Gt Part

Bt B

Lt
LLL
Lt
LLL
LLb
LLL
LLL
LLLLLLLLLLLLLELL

Pt
e
o

LLb
LLb
LLL
Lk
Ll
SR8
Ll
LLbL
LLL
LLL
LLL

IL-§

po2DODDDNIAND

BHEHEBBRABAYI
HHHHHHYBBARES

KKKKKKKKK
KKK
KKK

EEECEEECEELEEER
EEEEFEEEEEEEEEE

pLoonpnpNloD

KK¥

KLKKKKKKX

ECECEEEEEEREEEE

noo

phoDNDDONULY

QoD

Bt Pt

oo
a]8]s]

KKK

KKKKKKKKX

EEE
EEE
EEE
EEE
EEE
EFE

Ot
s ot

0Do

—

pno
noa
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ndo
npo

KKK

protect|on

Saq,

17«June’5

2671

jate

10104100

L¥eyyn=75
<197>

17102141

Printedi

Monltor

18w Jyn=75

/COPIEN145 /SPACING:1 /LIMIT14966 /FORMSIJMLY

C$2=518

24129190

HDP759B8

10479

T/M

S31AnTs

pOP~11/7¢ DIAGNQSTIC/BOOTSTRAP

(MPIFL-YC)

PATTERY

MACY1l 27(457)

17eyyne?9

19104

pAGE

NO® IR
R WN

DEKBHA,PLL

+TITLE

mOpe1i/70 DlAQNUSTlC/.UOT’YHAP

(MP3DL=YC)

1o COPYRIGHY (C)
JUNE 21,3
I® DIGITAL EQUIPMENY QONPOIATION
18 MAYNARD, MASS, #1744

MATTERN

1o pROGRAMMER DALE A,

RQEDGER

X )

FVVYVVVVVVVVVVVVYVVVVVVVVVVVVVYV
VYV
VVVVVVVVVVVVVYV
VYV VYV UV VYV VYV Y VY VY
FVVVVVVVVYVVVVVVVYVVVYVVVVVY
VY VVIVVVV VY VYV YV VYVVVVVVVVV
VY VYV VYV VY Y VY VY

INITIATE

THE DIAGNQSTIC/H50TSTRAF PROGRAM

THE OPERATOR MUST: LOAD ADONESS 17769900,

IN THE

M93@i~Y(

SELECT THE DESIRED

ODEVICE CODE, DRIVE NUMPER, AND MEMORY BLOGK VIA THE SWITCH
REGISTER, AND THEN PRESS "START®,
AFTER TNE PROGRAM MHAS
VERIFIED THE C.P.U,, CACHE, AND THE 20K BLOCK OF MEMORY

SELECTED 10 BE USED (APPROXIMATELY 3 SECONDS) THE PERIPHERAL
DEVICE WILL "BOOTTM THE SY$TEM MON]TOR,

THE

DRIVE

NUMYER

SWITCHES <@2

THE CQOE FoR

[NE

DESIRED

@8>,

DESIRED DEVICC

REGISTEK, SWITCHES <@7 : 23>
THE
L
2)

MUSY

IN THE

11)

MYST BE

SWITCH REGIGTER,

THE

SWITCH

DEVICE COOES AND DEVICE NAMES ARE AS FQLLONWSH
TM11/
MAGNETIC TAPE, TM1y
Tcxx/ruso
DECTAPE, TC1i<C

RK11/AXES

4)
5)

RPL1/HPES
RESERVED

DECPACK DISK CARTRIDGE, RKLieD

DISK

PACK,

RP11-C

RH78/ U216

RH72/8PB4

MAGNETIC TAPE SYSTEM, TWUls

1)
11)

RH72/HSE4
RX11/RX&1

FIXED WEAD DISK,
DISKETTE

THE

DISK

32K HEHQRY BLOCK NUMBER

PACK,

RWPB4

(8 = 17)

RWS@4

(DR RWSE3)

IN WHICHM Tg "8poT"

THE

SYSTEM MUST BE [N THE SWITCH REGISTEN, SH1TCHES s 1 12>,
MEMORY

BLOCK

UORNESPONOS

MEMORY BLOCK 3, CORRESPONDS
MEMORY BLOCK 2 CORRESPONDS

PHYSICAL

10
TO

PHYSICAL 32K
PHYSICAL 64K

28K,

o@K,
92K,

MEMQRY BLQCK 16 CQRRESPQNDS To PHYSICAL 448K = 476K,

MEMORY

BLOCK

DlAGNo?TIC

THE

TO TRY

SELECT

MUST

70 BOOT

THE

SET

CORRESPONDS

ANYWAY,

URIVE

PORTIQN
NUMBER

MEMORY

PHYSICAL

THE

482K

PROBRAM FAILS

1)
THE

IF THE DEVICE
STACK POINTER

MUST

CONTAIN

AND

DEVICt

MANAGEMENT

CODE

YOU

WISH

WIBKR TGO BOOT

IR AR

AN AR

AR AR R

5-72

SET YP

AL R

BLOCK

INTYO,

THE DEVICE

YOU MUST

1§ gN THE MASS BUSI
(Rg) MUST BE SETUP AND

THE

NYMBER

I35 gN THE

THE
R

AND

YOoU

WANT

TWEN YOU MUST LOAD ADDRESS 1777388¢,
BEFORE,

"g0OT"

OTHER THAN THE LOWER 28K QF MEMURY, AND FOLLOW
LIBTED(ELOW #OR YQUR PERIPHERAL DEVICE,

5pak.

UNIBUS
R

THE

THE
32K

yNIByg!

MAP

AUDJTION
Y

WORD

THAT

TO MEMORY
Y

INTO

YQU

TME PROCEDURES

BOUNDARY

NOW

YRR N

THAT

PUINTS
YUU

MANAGEMENT,
NN R

TYVYVVVVVVVVVVYVVVVVVVYVVVVVVVVVVVVVVVYVYVVVVVVVYVVVVVVVVVVVVVVVVVVVVVVY
IVVVVVVVYVVVVVVVVVVVVVVVVVVYVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV
VYV VY
| K

IF THIS PROGRAM FAILS

[N AN UNCONTROLLED MANNER

BE DUE YO AN UNEXPECTED TRAP TO LOCATION poQeWe,

1]
je

SUSPECTED THEN LOAD A "20OQPR6"
"QQ0000" [NTO LOCATION @ogoRe,

LOCATION

pPRgoEd

LOCATION

47777766,

HALY

WITH

1T MIGHY

THWIS

INTO ADORESS 280204 AND A
THIS WILL CAUSE ALL TRAPS TU

92000018

THE

ADORESS

LIGHTS

THAT THE OPERATUR CAN EXAMINE THE CPU ERROR REGISTER AY

3o
je

i e

je
te
Ie
te
pe
1o

"THE BITS IN THE CpU ERRQR REGISYCR ARE DEFINED AS FpLLoWSt
BITE2
= RED BUNE STACK LIM
= YELLOW ZONE STACK LIM!Y
BITE3
» UNIGUS TIME-OYT
BITP4
BITE5
= NON~EXISTANT MEMOHY (CACHE)
= QDD AUDRESS ERRQR
BITES
HALT

ILLESAL

BITE?

JETRLRRELRELTAITRIITRIRPRLIRIRRIRIPLIRIPERPLIOPRRRIERIOIRRRRELIRORR ERPRPPYCRERORCLOIERRYRIRRPRROCRRYRCRTYTY
JErELILPILRILIERLOIRTRIOIRTRRRIRERTYRRICECRIRLIRARRROIROCEROCRRRERRRRORRCRREOERRCRRRYRRERCORRRRIORORIRERYCOTRY

FYVVVVVVVVVVVVVVVVYVVVVVVVVYVVVVVVVVVVYVVVVVVVVYVVVVVVVYVVVVVYVYVVVVVVVY
FVVVVYVVVVVVVVVVVVVVVVVVVVVVVVVVYVVVVVVVVVVVVVVVVVVVYVVVVVVVVVVVVVVVVVVY
e

’e

NQTE:

IN THE CoMMENT

FIELY oF THE

BRANCHES THAT

ARE BEING

TESTEQY, JUST PRECEEDING THE ROM ADDRESS INVOLVED,

A SYMBOL USED TO
OR

FALL

THROUGN

TWE

THE BRANCH

UNDER

I
’e

A V" INDIGATES THAT TWE BRANCH SMOULD NOT BE
AND THE NEXT INSTRUCTION SHOULD BE EXECUTED,

TEST

INDICATE WHETHER TO TAKE

INSTRUCTION,

TAKEN,
A "e®

INDICATES THAT THE BRANCHM SHOULD BE EXECUTED, UNLESS

AN ERHOR CONDITION OCCURS,

1K)

JET

P It PP IR I PRI IIRPRILIITRIRIRRIERERRIRRIRRIRIROIOIRLOIRPRERRRTIERREYRRIOIRRICRRIRYRRRPROROICRYIOCRORTY

e
sterotr
strsteterestererseorere
treterer
e eesteesatrreersertreret
Frteeeet

1639200

BASEY

'l...QQ.;Q.Q.Q..IQ.I.0......00..........Q....Q.......0....0........0....
;e
ie

THIS TEST VERIFIES YME UNCQNDITIQNAL BRANCH

TESTL

,8BTTL

THE REGISTERS AND CQNDlTl?N CODES ANE ALL UNDEFINED WHEN
THIS TESTY IS ENTERED AND
THEY SHOULD REMAIN THAT WaY UPON

THE

COMPLETION UF

THIS

TEST,

169000
165000

165902

Y L

YSTL:

u00401

peeeoe
Y Y Y

T I

T§re

HALY
R

XYY YT

«SBTTL

TEST2

PR Y LTy

Y Y Y Y

Y Y

Y Y Y

Y Y YYYYYY

Y XYY ]

& 326 BRANCH ALWAYS

Yy Yy Yy

Y Yy

“syB"TM,

MODE

"9",

AND

"8Ml%,"BVS","BHI","BLDS"

NOITIQN

CQDES

ARE

ALL

UNDEFINED

TEST

Y Yy Y

Y Y

Yy Yy

Ty Yy YY Y Y}

1 e

THE

REGISTERS

(Ré)

SHOULD

AND

THIS TEST IS ENTERED,
BE

WHEN

UPON COMPLETION OF THIS TEST

!ERO

AND

ONLY

THE

FLIPFLOP

THE 3P~

WILL

IREI XX XTI XYL AR AL

16%g04
165004

1659906
169018
165912

169914

169016

Y Y

Y R

Y Y

SET,
Y Y Y YY)

T§T2!

109006

oLt

s»

iNgD

194004

sve
Wl
8,08
HALT

19
i3
HE

; V 324 DRANCH
PV 3gy WRANCH
i w 325 BRANGH

120403
122402

121401

oza%a0

it
R

Y Y Y Y YT Yy y Yy Y

JSBTTL

2n2iven

Ced, 5P e0ReO0g

3V 324 BRANBW IF

TESYY

Yy Y Yy

TEST

“QECTM,

IF V'l
IF B AND C_ARE

(2 XOR C)ay

Yy Yy Yy Yy Y Y Yy

MODE

“@%,

AND

80TH

Y Y Y Y Y I Y

)

"BpL","BEG","BGE","BGVm,~BLE"

upoN ENTtRlNG YHIS TEST

YH: REGISTERS ARE: RP o 9, R1 M Y R2 « ?

THE CQNDITIQN CoDES ARE:!

AND C

PROOOQ

UPON COMPLETION OF THWIS TEST THE CONOITION CODES WILL B3
Ne i,
End, VP, ANOCaj
THE REGISTERS AFFECTED BY THE TEST ARE:
8P » 177777

X
X
1o
e
}o

1 1900000000000 0000

165020
165020
169922
165924
164026
165030

800000000 00RRRRSRRRRNRRRIRARRRRRORRRABRERNRRORGRERNE
RS

TST3I

¢ 15306

DEC
arL

120004
J214¢3
sepue

165932

oT3¢L
203441

165034

.degue

-19]

8GT

b8 )

V 322 BRANCH

(N XOR v)a=p

TIT4

326 BRANCH

(2 OR

Yy Yy

iV 324 BRANCH IF 1'1

oLE
HALT
L

lN.I;!"'V'U Cl0,3pl177777
3V 321 BRANCH IF

8GE
181

sp
18

«88TTL

iV 322 BRANCH 1F 2 AND (N XOR V) ARE B80TH @

Y Y YTy Yy

TEST4

Yy Y

TEYT "RQRTM,

Yy Y Y Yy

MQODE 2",

(N XOR Vv))s1

Y Y Y

Y Y Y Y YT

Y I

AND “BVC","BHIS"TM,"BMI","BNEL"

je
te

UPaAN ENTERING THIS TESY YNE CgNDlTIoN CODES ARE:
Ne1l, £ 0g, V=g, AND

i
P

R = 2 Ré = ? RS =
UPON COHPLETION or

THE REGISTERS ARE: Rp » 7.

je
12

THE REGISTERS AfFEQTED ay
P = !7/777

"8,V

Ky & ? R2 = 7

7 8P » 177777
TH[! Y;ar THE CONDJITION CODES WILL BE!

AND
C

YHE

TEST

ARE!

llOQQ.Q!Q.QCl.00..00...0000..0.0.QOQ..OOQ!O!QQ!QQQOOQ..QIQ....Q.QQ.O.IOI

165036
165036

2060206

TST4:

ROR

5-73

iN"0,2e0;,y8),Cxi,5pPaB77777

1635940

165942
145044
163046
163950

102003

103042

1010¢1
g21004

ove
LLRE

15
18

iV 321 BRANCH
; V 321 BRANCH

17 V=D
1F Cs2

INE
HALT

IF #ep

JToRVY

YTy Yy Y

«SOTTL

TESTS

Y Yy

321

BRANCH

® 320 DRANCH

vy Yy

TET "OHITM,

AND

Yy Y Yy

mBLT",

ARE

Yy Y

BOTH

YT Yy YTy YY)

AND "8BLoS"

je
i®
je
je

UpgN ENTERING
Nes @, £9» 8,
THE REGISTERS
R} = ? R4 = ?

THIS TEST THE CgNUITIgN CQDES
Vi, ANDC= {,
ARE: Rp = ?, HL = ? R2 = 7
RS = 7 SP = /2777

UPUN COMPLETIUN

OF THIS TEST
Vw3, ANDC

THE

CONDITION

ARE!

CODES

WILL

BE?S

TNE REGISTERS ARE ALL UNAFF&CTED 8Y THE TEST,

165952

169952
165954
163956

163960

169962

165964

Jl0usasncaadoonaatediniasnslidadasiiaRansstBicutatiaaciRanerpaeneassssese
TSTH

F1 ]

¥no264
121983
oeg2ze
s02401
101404
200002

BH!
SEN

BLY
8,08
HALT

18!

INTR,Z®1jv®l,Cul

;i V 321 BRANEH IF g AND € ARE BOTW ¢
iNel, Zeljyei,Csl
; V 324 BRANCH IF (N XOR v)=sg
; & 325 BRANCH IF (2 OR C)=1
;3TOP WERE IF A GRANCH FAILED

19
T§Te

Jl00na00sentssntatanatonssltatapiostntanistosinaadassdRonesalelaeasasases

«S8TTL

TESTE

TEST

"BLE®TM AND "BGT"

K]
ie

UpgN ENTERING TNIS TEST THE coNDlTlQN
Nwsi1, 283,
1, AND C =

je
je
1A
1A

Ry = 2 R4 = 2 RS = 7 §P a 77777
UPON COMPLETIOUN OF THIS TEST THE CONDITION CODES WILL
Nsl, 2ag, Vs, ANDC =1

CoDES

ARE}

THE REGISTERS ANE! Rp » 7, "1 . tR2 a7

BE!?

THE REGISTERS AME ALL UNAFFECTED @Y THE TYEST,

1658606

169966

169p79

169872
163974

I 1080000000000 00R0RRRRNERRRORCRERRRORBRRROINRNG
QR aRREREttRORERIGORARES
TST6!:

100244
203491
eP3vaL

CLE

BLE

IRE T

HALT
Y Y T

Y Y

XYY Y

PRANCH

(N XOR

V)Js1

;STOP WERE IF A BRANCH FAILED

Yy Y

«SBTTL

324

® 328 BRANCH 1F B AND (N XOR V) AWE B801M

;

817

BGT

18!

coavee

IN"L,2%05Ve1,08

Y LYY Yy

TEST7?

Yy Yy Yy

Yy Yy Yy Yy

Yy Yy

Yy Yy YYY

TEST REGISTER DAYA pATH AND MQUES "2%,

"3%",

YY)

"6"

1x]

WHEN THIS TEST

Nwoil,

299,

IS :NTERED

THE CQNDITXUN CODES ARE!

Ve,

THE REGISTERS ARE: Ru . 7. a1 . 1, R =« 7

;e
;e

Ry =
UPON

.
;e

Nwg, ¢sl,
THE REGISTERS

;e
e

RO
R4

2, R4 = 7,
COMPLETIUN

»
=

125232,
1252392,

RS
OF

= 2?2,
THIS

8P =
TEST

@§77777,
TWE CONOITION

CODES

ARE?

V@, ANDC = g,
ARE LEFT AS FULLOWS:

Nl
HB

=
2

Q008PP,
1252%2,

1252%2,

125252,

R3 = 129282
AND MAP B2 =

125292

]

}l.l......l'....'.......i...........0...II...QI....Q.D...'......0......0

165976
165876

165122
165104
165106

T§Y7:

012726
108692

163112
165120
168122

418537
170200
1677¢4

165114
165116

16%126

165132
165132

A13405

B124u1
w1401
W20002

177772

MOV

#129292,8p

MOV
MOV
MOV
MOV
MOV

ng,Hy
Ry, R2
R2,R3
R3, R4
R4, RS

,WORD

MAPLD

BLT

MOV

n108901

2101¢2
010203
210304

165110

12%252

INOMAP:

MOV

iNWl,Ze@,VeR,Cx), ROx125252
iNey, 880, v2g,Ca1,R1=125252
iN=]1 ,2s0,vEp,Cx),R2212%9252
iNEl,Z=p,Vap,Cn1,RI=12%252
iNxl, 2=p,vmp,Ce1,R42125252
iNwy,ZeQ,vsp,C=1 ,RO125252
;N'I.E'E.V'B.C'l

R%,0(PC)+

sue

IMAP
L P=1252%2

@ INUMAPR ,R1

BED
HALT

198

iN®l,2%0,v®0,C=1,8pu
39252

SP, RO

iNwg,Z=1,vep,Cagg,

AND R1sgppoge

Zwg

T9T10

324

BRANCH

® 326 BRANCH

XOR

Vv)sy

11 00c0cadRsdasinstatRniitondatadlsnasiuvldtoanasadeadnianlialanaecsnesene

+SBTTL

TESTLM

TEYT

“RQL".

®"BCCMTM,

“BLT",

AND MQODE

"e"

1K]

]e
e

WHEN THIS TEST IS ENTEIED
Nsg, & a3, V=d, AND

1K}

R = 125242,

' e

UPON COMPLETIUN OF

)

THE

REGISTERS

ARE:

THE CoNDIYIQN
= 9,

125452.

N4 = 1252%2,

MAPLBE

12%2%2

Nwg@,

gsp,

RD =

THIS TEST

Ve,

ANDC

2OU@PB,

1252%2,

THE

CQDES

ARE!
N2

125252

SP = 119252,

CONDITION CODES ARE$

THE REGISTERS ARE LEFT UNGHANGED EXCEPT FOR

MAPLPE

WH]CH JHOULD

NOW

EQUAL

P%2%24,

163134
169134
169140
16%142

169144

XY T

Y r Y

INSD,2%0,y%1,C21,
7V 321 BRANCH IF

Y Y

AND
C=p

MApLDO

yyryyy

TST18!¢

276167
123004

gr24a1
200809

283040

RoL
8cc

MAPLD
i¥

BLY

1%t

TST11

326

BRANCH

XOR

252524

V)=}

HALT

11000000000 R0RCARANRRBRRRRRRIRRREIRRNIRNRBANRIOARRRBINAERRNENBOROROBONERS

,SBTTL

TESTL1

TEST "aADOTM,

"INC",

“EoM",

AND "BCS",

WHEN THIS TEST IS ENTERED THE CONDITIQN
Nsg, 8=y, Ve, ANDC = 1,

X
ie
e
ie
e
ie

R3 = 125292, Hé4 = 125252, R = 1252%2, sSP w 179252,
MAPLOP = 232544,
UPON COMPLETIUN OF THIS TEST TWE CONDITION CODES ARE1
Nag, g2, Vs, ANDC =g,
THE REGISTERS ARE LEFT UNCHWANGED EXCEPT FOR
R3 WHICH NOW EQUALS 0900020, AND R1 WKICH |8 ALSO PDoeger

THE

REGISTERS

ARE:

125232,

CODES

"8LE

.
X

poooee,

ARE:
R2

12%2%2

]

163146

N a00RasRRlat et R

T8TLLE

5-74

dasaR

s taRBlaRRlEIR

R IRs

IRl ERelNeERORRRINSERRIBRGRS

165146
16%152
165154
169156
165160

169162

165164

266703
w23233
383403
0603281
103421
503401
w020

18!

J(MAPLBE ® 952524) ¢ (R3 = 125252)

,
MAPLERS

ADD
INC
COM
ADD
:14]
8LE
HALT

213026

iNsl,EZn@,yep,C=20,

iN=1l,Z=Q,VeQ,Cn0,

iNmp,Zny,VeQ,Cel,

AND R3I=177776
AND R3=177777
AND R3 = pppRop
ANDO

iNeg,2s1,veg,Cag,
5V 324 BRANCH IF

Cal

326

BRANCH

oeppen

XOR V)Jsi

00NN NRRIBIRRIREDRREBONINBRRBAGRIBRUBENSNIBBRAIINGERQINRNRIUBONORIRENDES

+SOTTL

TEST

TEsTiZ

HHEN THls TEST

1Kd

"Bl§",

"RQR",

“ADO",

AND "BLp",

"BGE“

1S ENTERED THE CoNODIv!IQN CoDES ARE:

THE Rccxsrtaé ARE! Rg s 125252, Ri * p@ge@s, R2 = 125252
g,

Now

K]
K]

popauad,

AND

= 125252, Ry

= 125233,

s 125232,

UPON COMPLETIUN OF THIS TEST THE CONDITION CODES ARE1

Nnm2p,

AND

g3,V

THE REGISTERS ARE LEFT UNCHANGED EXCEPT FOR

R3 WHICH SHOULD BE MODIFIED
R4

WHICH SHOULD

NOW

RACK

TO 892222,

EQUAL 952525

AND

,|..Q'..U...Q.I"...l...’..l'...l...QQ...Q..0..‘0..'.l.......’.l..lll.'.

165166
163166

TST12¢

165179
165172

036004
250403
n60503

B?!

1652e0
165202

103401
¢r200L
338000

8GE

165174
165176

ADD
INC
BLO

¥a%203

iN®@, %%B,v*1,Cm0,

ROR

R4,RY
RY,R3
RJ

iNsg,2mp,Vep,Cnp,
;N'l.!lB.V'D.ClE,
iNspg,2uy,V=p,Ce0,

TST13

BRANCH

324

320 BRANCH

AND R4 = 232929
AND R3 = 952525
AND R3I = 177777
AND

ppooge

|1 31

(N XOR V)ap

HALT

18!

,'..DQQ...Q...O..Q....OIQQ..Q.Q.......Q..Q...IO..'Q...QQ..I...l........'
TEST "DEC® AND “BLos". “aLT"
+SBTTL
TESTLY
1K)

WHEN THIS TEST lS ENTEIED THE CoNDITIgN CpRES ARE!
2,
AND €
N=p, 283,V
THE REGISTERS ARE: Rn L 125£SZo Ry = pgopes, R2 s 125252

IR)
e
je

R3 = P9 ggpe ,

352525

UPON COMPLETXUN OF THIS

1K)

AND

Ewyg,V

125252,

125232,

te ST THE CONDITION CODES ARE!
C

THE REGISTERS ARE LEFT UNCHANGED EXCEPT FOR

R1 WHICH SHOULD NOW EQUAL 177777

165204
169204
16%206
165210

168212

225301

;'...........Q....G...'QI....O...'..'I........i...QQ.Q....'...........'.
TSTL3

iN®1,2%Q,v8,Ca0,RAn177777

3V
i ®

121401

L2491

JJ00ce

324
326

BRANCH
BRANCH

1F
1F

XOR

C)s}

vzl

18!

s s N e NN atat Nl eRoRloRatB Il aNINcRsloRnItaaEacRedsIReIsssRORRaERSS

«§8TTL

TEST “GCp4",

TEST14

"BICY,

AND "BGT",

“BSE",

"BLE"

I1XJ
IR

1R]

e
}e

134
je

HLJ

WHEN THIS TEST IS ENTEIID THE CONDITION CODES ARg!
N = 1, ga2g, VR, AND

THE REGISTERS ARE: Rp » 129(!2. Ry = 177777, R2 = 129282

R = POWOSE,

K4 = §52325,

AY » 135252,

SP = 128292,

UPQON COMPLETION OF Tuizofgir THE GCONDITION COODES ARED
N

g=a,V LI ¥
=4,
REGISTERS ARE LEFT UNGHANGED EXCEPT

=@,

THME

FOR

AP WHICH QHGULD NOW EQUAL 992525, AND

Ry WHICH PJHOULD NOW EQUAL ©€52%524

IL]

169214
169214

169216

J0%3120
101401

169222

V40001

169220

163224
165226
169232
163232
169234

000000

1103000000000 00000000R0RRR0RRRRRRRERNRRRRGORRRRRNNORRNRRNERBORRRNRRRENNS
T8T141
IN.' !.'Qv.'.c.1' AND RE = @5292%

260101

v23401
220040

188

Ry,RL

INs1,2ep,V%0,Ca1, AND Ry = 12’!52
sNep ,Z0p,vy"},Csy, AND Ri = 9352524
RANCH 1F 2 AND (N XOR V) AKE

9718

;

iV o822 8

13
3

pa3ge2

zg203L

OR C)=3
i @ 325 QRANGCH IF (&
;$TOP MERE IF BRANGH FAILED

g, Ry

29!

BLE
HALT

BRANCH

® 326 BRANCH

322

(N XOR v)=p
[2 OR (N XOR V)Jmy

BOTH #

110000000 RRBRRERRRRARRANINRIGIRRARIRENRNIRIROLARERNIBRINRIEIRNONORRORNIE
TESTLY
TEST "ADCTM, »CMpn, “BIT", AND “ONE","RCGT","BEQ"
198TTL
e

K]
K]

HHEN THIS TSSTVIS ENTE:SOCTH!CONDITIQN CODES ARE!}
.

THE REGISTERS AKE!

R = 052525a

R1 = 252324,

R2 » 125252

R3 » PPUOER, N4 = 0523023, RY = 125258, SP s 12%2%2,
UPON COMPLETIUN OF THIS TEST TWE CONDITION CODES ARE}
=g, £ 93, Ve g, AND C =
THE REGISTERS ARE NOW!

RE = 392528, Ry » ppoPEBR, RE = 125232, RIS

952925,

= §52%23,

SP = 123232,

]l......Q..Q.......QQOQ..........l.Q.......Q...C...Q....................

165236

165240
165242
164244
165246
165250
169242

165294

16%256

TETLS!

ADC
cMP
8NE

0999591

320401
ae1093
30103
v33003

¢>58405
160501
621401
v30009

18!

AND m1

IN®U,290,veD,Cep,

i ¥V 322 BRANCH IF 2eQ
;R = @32%52%
RS = 125252
N, 2al;vep,Ca@

252825

iNSQ,2ul,ysQ,Csp

R4, R1

BIT
BGT
COM
sua
8EQ
HALT

; V 322 BRANCH 1F X AND (N XOR V) ARE BOTH ®

;N.’.!".V'E.C'I,
iNsg,Es),Ve8,080,
; ® 326 DRANDH LF

AND RS = 523523
AND R1 = popEge
gny

}'.‘.....0...............Q.Q..QO....II........lQ.QIQ..I.................
wENE®
TEST “MovB", "Sol". "CLr", WTIST" AND ®BpL",
TEST1§
S§BTTL

WHEN THIS TEST IS ENTERED THE CoNDITIQN CODES ARE!
N

=@,

Vs,

THE REGISTERS AHE:

5-75

AND

R » 052’254

Ry = POPORY,

RZ = 125252

399

o8
401

i
3]

ap2
:03

i
e

(L)

"5
4p6

1465260

427

163262

408

= ODEOUE,

nl
M1

18 QECREMENTED OY A 308 INSTRUCTION T0 epsene
1S CLEARED AND THEN [NCRLMENTED AROUND TO gwedee

852523,

952323,

129292,

upoN COMPLETIQN oF THIS TEST THE CONBITIgN CQOES ARE1L
#, 2% 31, Ve @8, ANDC s,

ll0...0..l........l......'........00....00.0..0..QCQ...QQOOQ..O.....O...

165264

TSv16!
112700

170001

409

16%266

pogeoe

411
412
413
414
41%

165272
169274
169276
1633D3
163302

o0%pol
085201
077802
2%7¢p
po2ife2

418

163272

177401

277802

416

1653p4

po%7p1

418

163318

220000

Mov8

417 165306 poleey

177401, R0

L 11N
1814

48:

NSO, 88,VeH,Ce0,

WALY

;

ANO

& 320 BRANCH [F Nsg

FT0P

IF #BPLTM FAlLED

Q0881

soe

RD, 13

cLr
INC
08
187
ONE

L}
a‘
Re, 38
1]
48

iNwg, Esy, Veg, Cs8, AND R1 = g3p990¢0
s INGREMENT 04K TIMES (2 oo 38)
;LO0P BACK TO "INC" 64K TIMES
iNsg,Zag,vep,Cs@, AND RO s QEpEds
i ¥ 322 BRANCH IF =9

T8?

]

iNwg,Eul,vep,Cn@,

11}

;00

vtr;v

HALT

NOY

LDOP

SINCE

(R#

: & 326 BRANCH (F Z»g

AND

popEOE

419

‘2'

ll0....0.0..0.D..000.000000000.0.0.0.00Q....0.l..GQ.OQOOQ.!OOOOO0.000...

:g;

423

42%

427
428
429
43p
431
432

je
1R
je
e
10
ie

426

433

‘34

169312

436
437
438
439

163312
163316
163320
169324

,127g¢
02%201
912742
306208

441
442

169330
165332

443
444
445

163334

446

169336

60001

448

169342

203001

447
449

453

163326

165333
165344

TESTL/

TEST "AgR", “ASL"
IS ENTERED THE CONDITIQN CODES ARES

THE REGISTERS ARE:

Rp s 125232,

R3 o gogegs, Rd o 952923,

R1 = BOPEOE,

R = 392528,

R2 » 125292

SP » 125292,

UPON COMPLETION or THIS rtsf THE CONOITION CODES ARE}
Nwop,
Eng, Vo, AND C = 8,
THE REGISTERS ARE LEFT UNCNANGED EXCEPT FOR
RS WHICH S NOW EQUAL YO 9B9geS,
Ry
WHICH |8 NOW 098901, AND
RR
WHICH [S NOW oposed,

llfl..l..........‘......O000000..00000.00.0000000000.0000.0...0000000000.

435

44¢

+OBTTL

WHEN THIS TEST

TTLT

100900
]
230020

MoV
1N
MOV
ASR

4300008, RE
ng
#eDL6, R2

226301
229591

ASL
ADC

R}
Ry

sLEFT SHMIFT My (16 TIMES)
;ADD CARRY (8 UNTIL LAST TINE)

;ADO CARRY

(36 YIMES)
(g UNTIL LAST TIKE)

77205

300

R2.18

;L00P

181

0p%%0p

023421

Ry
ry

ADC

ADD

Ry, R

acT

TET20

oLk

22000

28!

,nl-:IOIIl
iR1egg
% [ couurtn TO 16 DECIMAL
sRIGHT SWIFT RO, SIGN EXTEND

;AT
;RS

WALT

BACK

DECIMAL

THE END OF THE
s FOESEG
AND

TIMES

LOOP
Ri

ppeen)

INsg,Reg,vepQ,Cu0

Ricgeoenl,

RE=890308

iV 324 BRANGH IF £Z OR (N XOR v)Jea
@ 328

BRANCH

AND

(N XOR V)

AKE

BOTH p

451

l|UQOQQ.0.0.I...l....0.0..l...........000..0.000.000”00000...0.60..00.00

432

«SOTTL

453
454
485
456
457

I
je
e
I

WHEN THIS TEST |S ENTERED Tut CONDITION COQESY ARE!
NsB, &%, Ved, ANDCOPR
THE REGISTEHS ARE:! AP » llllll. Ry = gOO@P1, R2 = SoERPE
RY & SE040, WA = §52525, Ry = 32329, SP » 129292,

458

UPON COMPLETIUN OF THIS TEST TME CONDITION CODES ARE:

468

)

THE

461

Ry WHICH JHOULD NOW EQUAL Spaces

::g

459

464

169346

169348

72127

467

163352

179781

479
471

169356
169362

200000
LPR30L

473

169362

372127

475
476
477

163366
169377
165372

(3%2¢1
271401
000020

468

adcep7

T8T281

469 163354 130401

472

474

€931,

REGISTERS

TEST

Vag@,

ARE

ASH,

AND SwAB

ANOC

LEFT

=},

UNCHANGED

EXCEPT

FOR

j]10000300000000 3300030000000 000000000000008000300000000480000000800000000

465

466

Nesg@g

TEST2¢

AgH

#7.R1

T8T0

HALT
SWAS

| L1t
18!
177761

SGEEY SHIFTY 01Te InTg BIT?
iNug,Zeg,veg,C=0,

AND

pEp28s

i ONER BYTE lHOULD OE NEGATIVE

,N-;,lll veg,

;o8 328 ‘RANCHIF u-;

iWASHY MUST MAVE FalLE
;SHITCH BYTES OF Ry, Rz . 190000

iNsy,EnB,Vep,Cnp

ASH

#utD1Y,RY

INC
BEQ
WHALT

Ri
T§T21

SRIGHT SHIFT Ry 13 PLAGES SIGN EXTEND
;Ns1,Zsp;VeQ,Cx@,

iNwg,Zal,yep,Crl, Ry = eoafll!
i 8 326 BRANGH [F @sy
;EITHER nSWaB® OR “ASHTM FAILED

4;3

)IlQ......O....l..Q.QC...!I.........Q.IOQOl..O.G.O..OOQQ..QOCQ..........

481
482

1o
;e

au:u

484

ru:

482

+SOTTL

483

TEST2]

THIS

Nw@,

TEST 16 KERNEL P,AR,’S

TESI

:ernzo

#=1,Vsp,

REGISTERS

AKE:

AN
=

THE

CoNDlTloN

slssze.

CODES

govesd,

ARE:
R2

2goeRR

485
486

i
1.

RI = PEUGGA, R4 = §5252%, R> = §92529, SP = 129252,
UPON CDHPLETXUN OF THIS TEST THE CONDITION CUDES ARES

487
488
489
49
491

ie
i
e
I
T

N
s 1, Vs @, ANDC s g,
TH: R:elsfeas NOW EQUALI
RP = 172400, KL * QUOEOS, "2 * PWOEP3,
R4 = PB5252%, MY = {23282, §P = 125252,
ALL XERNEL P.A.R.'S = 128282,

:3§

12700

497
498

14%424
165490

208145
210429

500

165414

521

165408

@60002¢

169410

02046¢

177776

163416

105149

165422

21011

169420

Sz4

169424

505
536

172340

12701

532

583

CEEE20

] 1004008000000 00300000R000000000008000300000000B 00030 RBACBRRRRRRNENS

169374
$69374

499

494
495

496

16%426
16%430

JTi014

120512

120440
[ 1007
12%112

Tgr21¢

MoV

#KIPARD, RO

iFIRST

coM
MOV

RY
R4, (RY)+

iRS=125282
iPARSD32525

MAv

cMP

BNE

comMB

WeD16,R1

CKECKED

;010 1Y LOAD PROPERLY?

»(RY)

;COMPLEMENT MiGH BYTE

RY, (R¥)

cMPB

R4, ~(RO)

BNE
coMB

"paAR"

KIPARD THRU KOPAR7

R4,=~2(RY¥)

cHre

BNE

;00

r]]

23
(R3)

5-76

;

V BRANCH

;CMECK

THE

IF NJ-

R % PAR + 2

HIGH BYTE

i V BRANGH 1F BAD

PAR=125125

RE w PAR + 3

;CMECK THE LOW BYTE OIDN*T CHANGE
; V BRANGH IF IT CHANGED
;COMPLEMENT THE LOW BYTE

Ry s PAR
PARE1292%2

169432

165434

169436

165440
165442
169444

165446

CMPB

120520
021804

RS, (RY)+

6?7147
o7penL
2200800

281

; V BRANGH )F IT FAILED RO ® PAR ¢ 2
;LOOP UNTIL KDPAR7 HAS BEEN TESTED

23
R}.1S

BNE
308

371002

7CHECK THME LOW BYTE

; V BRANCH IF BAD RO ® pAR ¢ 1
;CHECK THE MIGH BYTE

28
RS, (R +

BNE
CMPB

120520

; & BRANCH Y5 NEXT TESY

Ter22

HALT

;A P,A,R, FAILED TO WOLD THE RIGHT DATA

;GHECK R@ FOR THE ADDRESS

[ 100eneRIest i atad sslobasINEIaRti i alEslstRItsieRensloncatassasenensnsd
1EJ

«8BTTL

TEXT AND LOAD KIPDR'S

TEST2Z

WHEN THIS TES{ 1S ENTERED THE CONDITIoN CoOES ARL!

ie
ie

THE REGISTERS ARE! Rp s {72400, Ry * poORED, RZ = PREERD
R3 » geU@dD, N4 = p32525, RS x 125254, SP = 129252,

N=g, £e3, Vs P, ANDC:=0,

Ie
jo

New@,

@2, Ve, ANDCo» @,

UPON COMPLETIUN OF THIS TEST THE CONDITION CODES AREY
THE REGISTERS THAT ARE MODIFIED ARE:

RP = 172380, HY = 04000Q, RZ = P774p6
ALL KERNEL l«SPACE P,0,R,’S (172300 » 172336) ® 077486

IR]

"..I..Q..Q...'....0....0.........0.......'...000...0...................
169450

165459

165454

163462

165464
163466
163470

165472

165474

212700
212721
012702

172329
200014
n77408

110240

V21002

T§T22!1

291401

MoV
MOV
MOV
MOV

#X1POR7+2, R0
#108,KRy
#P77496,R2

R2,=(RD)

thART WITH LASY "POR*"
;00 K{POR7 TWRU KIPOR®
sPATTERN TO TEST ®PDR‘8%
;LOAD "POR"TM UNDER TEST

BEQ

;BRANCH IF TME DATA MATCHES

300

Ry, 18

HALT

2900090

25!

a7710%

;8EE IF THWE DATA LOADED 1S CORRECY

(Ra),R2

CHe

;A "PDRTM HAS FAILED
;RE WAS THE ADORESS OF TWE BAD “PDR*®
;R2 WMAS THE EXPECTED DATA

;WOQP UNTIL ALL EIGMT »PDR’§» WAVE BEEN
;TESTED

"....0...0'..........'..Q..I.Q..Q..........l..O..OI..........Q'........
LSBTTL TEST2Y TEST “JIRT", YRTEM, “RTITM, & “JMp"
je

1
te
1o
e

1658816

165522
163524
163524
165530,
165532
185536
1658540

165542
165546

ALL WORK PROPERLY.

oN ENTRY T THIS TEST THE STACK PGINTER "Sp® 1§ INITIALIZED
TO 172376 AND IS LEFT THAT WAY ON EXIT,
.

I IS Rsatesasensneatasalensssnedotniticnecnalantssalssedianossionesassnsed

169476

165476
165502
165536
165517
1695.4

THIS TESY FImyT SETS THE $TACK pquTEa Yp "KOpAR7TM (172376),
AND THEN VERIFIES THAT wySAw, wRTS®, ®RT]w, AND wJwP*®

T§T23!
J12736

I 4767

Q70000
J22716

Jrl40L

J20008
d12716
Ja0207
200900

172879
yagge

165906
165330

025046
J12746
230002

165542

eageue
200137
p2gd0a

165950

#C,18

JSA

HALT

CMP

4108, (9P)

238

HAL

3%, (yM)

CLR

'} 3]
581

165550

#KOPANTY, SP

MOV

1081

MOV

;WAS THEL CORRECT ADDRESS PUSHED?

;BRANCH IF YCS

;WRONG -THING PUSHED ON STACK

;CHANGE THE ADORESS ON THE BTACK

RYS
HALT

MOV

#4s,-(8P)

;TRY TO RETURN Y0 38
;010 NOY RETURN PROPERLY

JMP

1111 ]

e({SP}

LAS
HALT

HALT

;TRY TD JSR Y0 1§

JTHE "JSR®TM MUST MAVE FAILED

IEOT

:§£1 UP THE §TACK POINTER

;PUSH A RERU ON THE STaCK

;PUSH THE RETURN ADORESS ON STACK

;SEE IF AN "RTI" WORKS
;THE "RTI» FALILED

iTRY TO W NpPw

stee "gMpe FaAlLED

; ADDRESS TO "yMP® TQ

110088083000 00000000000000033000000000000000RR0RERRNANRRLRRRRNRRRRRRRY

§8TTL

TEST2¢

LpAD AND TYRN gN MEMQRY MANAGEMENT ANO TYHE yN1Byg Map

je
1Y)

THIS TEST 18
gNLY EXECUTED LF THE UppER 4 OITS <15112> of
THE SWITCH REQGISTER ARE NON-EERO,
TNE TEST WILL LOAD MEMORY

e
1o
je
1o

1T WILL ALSO $ET UP THE UNIWUS MAP REGISTERS B THRU & TO
ISLOCATL THE YUNIBUS ADDRESSES CORREGTLY. (1E, JF BITS <i%112>
: :g;:vrggock :u¢ufln 3, THEN YOU WANY TO BOOT INTO
LR
)
0 128K,
THE KIPAR‘S WILL BE LOADED AS FOLLOWS}

je
je

KIRAR4 = gO70p@, KIPARYS » PpY20¢,
KIPAR? WILL ALWAYS EQUAL 177628,

MAPLD = PPPRAY, MAPHE s @3, MAPLY * J20¢@P, MAPH = @3,

e
I

e
1o
I

MANAGEMENT

T8 RELOCATE YO

THE

32X PLOCK NUMBER SPECIFILD,

K?PARG = JOOPKME, KIPARL = 6220, KIPARZ = gpésgs, KIPARS = paeény
THE

UNJBUS

MAP

REGISTERS

MAPL2 = Q48POE,
MARLA = LOSB0U,
MAPLG = 140834,

WILL

MAPH2 = §3,
MAPHA x 03,
MAPHS = 33,

THEN

KIPARS & §o7483,)
WE

SET

MAPLY = 360098,
MAPLY = (20080,

FOLLONS)

MAPHI = 83,
MAPHS s 23,

IRd

1180800000300 00000RRUGIBRRBIIDNIGRRIGRIRVRIBRARINBRERINRORBANIORNOIROS

165550

T§T2M)

vi¥7@2

177579

164856
165362
168566

J137e2

173924

£42792

141777

165572

201433

169550
169554

¥oL002

072227

177778

)

MoV

#NSWR,R2

iREAD THE SWITCH REGISTER

MOV

P#173024,R2

;READ

1081

ASH

#e2,R2

iRIGHT SHIFT BITS <15112> 2 PLAGES

T§T25.

;GO TO NEXT TESY [P R2 18 ZERQ NOW

aNE

alc

108

#1Ca39090, N2

;§XIP YHE NEXT
THE

INSTRUCYTION IF NOT ZLRO

SWITCHES

THE

;LEAVE ONLY 8178 <13:i8>

THIS NEXY poRIIQN of CoDE wWiLL OE RUN oNLY

MY3@1

IN R2

IF You ARE

BOOTING

INTO MEMORY OTHER THAN PWYS]CAL 8 TQ 28K,

M8V
MOV

#KIPAND, RO
#eD7,Re

s ADDRESS of FIRST "pARTM Tg LoAD
iLOAD KIPARE THRY K]PARG

ADD
800
MOV

#200,82
R1,18

;MAKE R2 POINY TO NEXT 4K BLOCK
;LOOP UNTIL KiPARG HAS BEEN LOADED
iMAP KIPAR? Y0 1,0 PAGE

ie
i

Ngu LOAD THE YNIBUWS MAP YO HEFERENCE THE SAME MEMQRY
AS
MEMORY MANAGEMENT DOES,

169374
1656022
1650604

1659626
169642
169614

¢i27a¢2
12791

172344
60207

ze2702

020204

210220

B77104
g12710

177609

18t

MOV

RZ, (RP)*

#377688, (RH)

5-77

;LOAD THE KERNEL

1=8PACE P,A,R,.’'S

165622
167624
165626

16%632
165636
165640
165642
162646
162650

162656

72227
L2%0903
912790
212701
210320
vig22e
62793
¥77105
12737
395237

177766,

ASH

170200
oaeas?

nov
NOV
MOV

22000¢

200860
177972

172916

Bue0ly,N2

iRIGHT

BNAPLE, HE
#07,R
Ry, (Rd)*

;ADORESS OF
;PREPARE TO
iLOAD LOWER

SHIFT

PLACES

OLA

MOV
ADD
200

Ry, 28

R2,(RY)+
$23000,R3

;LOAD UPPER ¢ BITS OF
;POINT TO THE NEXT 4X

MOV

#40,90MMRI

JENABLE 22B1T MAPRING AND UNIBUS MAP

INC

START WITH R3 =« gpadee

FIRST MAP REGISTER
LOAD SEVEN MAP REGISTERS
406 BTS OF THE MAP REGISTER

YTHE MAP REGJSTER
BLOCK

;L00P UNYIL SEVEN MAP REGS ARE LOADED

[ TLLLY]

;TURN ON FULL RELOCATION

} l000000'0..0!0000.!00000ooo..ooo.ooooooio0oooooooooooooo-noo.o.o.o..oooo
}e

12 ]
I
je

+SOTTL
THIg

TEST2Y

TEGT MAIN MEMQRY FROM VIRTUAL 1980 YR 20K

TEST WILL

TEST MAIN Hzflgnv WITH THE CACWE D13ABLED,

THE

& § ON

THE

BTACK

WHICH

THE

KERNEL

FRgM

VIRTUAL ADDRE¥I POLEAP TO 137776,
1P THE DATA DOES NOT COMPARE
PROPERLY THE
TEST WILL WALT AT EITHER 1065742 OR 148786, 1F &
PARITY ERROR
OCCURS THE TEST WILL HALT AT ADDRESS 1063776, WITH
IN THI®

TEST

THE REGISTERS

JELEER,

DATA

DE7488,

177746

ARE

READ,

INITIALIZED
=

(CONTROL

267402,

REG,)

DeSPACE P,A.K,'S,

AS FoLLONWS!

pli0pé

17237¢

1K)

169662
169662

163664
163672
165676
169702
169726

169712

165716

169720
1658722

1658724

165726
1639732
1659732
169734

11 0000000000000 2000008080080 G0000000R0RK0RRRINRNNEORRNBRIRERORRRE0RERRE

Ta4T2MN

e19216

812703

J1271%
012792
212703

vig224
218300
019029

165776
000116

MOV

290114

177748
geepLe
267400

277402

216204

310380

281t

381

1659746

14008

agt

169750

16%742
169744

169752

165754

163756
163769

169762
165770
165772
169776

v200v1
J71401
v02009

977206
212737

005946
300137

ase8o00

APAEH T, 02114

i§ET

UP BARITY VECTQR

o116

;SET

#177744,RS
SH1§S, (KS)
947430 ,R2

;CAGHE CONTROL REGISYER ADDRESS
iFORCE MISS 80TH GROUPS
;COYUNT STORABE

PROCESSOR

nOv

173762

opP114

1736006

PAEHLTt

!.nl

RY, (R@)+

300
MOV
MOV

18
R3, R4
Ry, Ro

cHP

;g.flt

MOV

HALTY
coM

308

(RQ), 11

(RE)+

LITY 1]

NDV

s(RE).R1

coM
CHp

Ry
RD,RY

BEQ

A2, 48

HALT

381

83888, RS

MoV

BEQ

977406

iSAVE A2 FQR THE UmpER S1x BITS
;QF THE MASS BUS DEVICE’S BUS ADDRESS
; IN ADDRESS 17772376 (KDPAR?)

MOV
nov
MOV

HOV

191!

RZ. (SP)

cLR

MOV

29100¢

211801
220033
001421
eooeRe
ca%122

169736
169742

MoV

#CONT, Pp114

CLR

«{SP)

JHP
MALT

[TRg 2F]]

STATUS

WORD

;FIRST

ADDRESS STORAGE

SETUP

FIRST

EERO

;$EIUP COUNTER

ADORESS

;LOAD EACH ADURESS WITH 1TS

;OWN ADDRESS

+Q0OP UNYIL DONE
;QETUP COUNTER AND FIRST ADDRESS
;SET STARTING ADDRESS IN Re

;GET THE DATA

;18 1V CORRECT?

iBRANCH

YES

;ROSADDRESS, R1=DATA

iCOMPLEMENT

DATA AND

iLOUP UNTIL DONE
+READ THE DATA
COMPLEMENT OF

(IT
THE

INCREMENT ADORLSS

SHOULD NOW BE
ADURESS!?

THE

s GONPLEMENT BEFORE CNECKING
i18 THg OATA CORRgCT?

iBRANCH IF vES

;ROWADDRESS

iL00P

UNTIL

Riz<DATA
DONE

;BET PARITY VECYOR TO CODE THAY

iWILL TRY TO CONTINUE
+JF THE GCACHE FAILS,

AND BOOTY

;SET THE CYCLE FLAG TO ZERO

iJUMP TO SECOND WALF OF THE ROM

iMALTING HERE

MEANS A PARITY ERROR
]

5-78

681

,SBTTL

BOOTSTRAP ENTHY POINT 1§ AT 17773209

VYV YV VYV VYV VY VYV VY
VVVVVVVVVVVVVV
VYV VYV VVVVV
FVVVVYVVVVVVVVVVVYVVVVVVYVVV

683

VYV VYV VYV VYV Y
VVVVV
VYV VY VY VYV VYV VYV YV VYV VUV
VYV VVVYVVYVYVV
FVYVVVV

684
685

686

687

]

688

689
699

THE REGISTER YSAGE DURING THE BpoTSTRAP 1S GENERALLY AS FpLioWs?
RP = THE DRIVE NUMBER RIGHT JUSTIFIED (B < 7)

je
je

Ry = TWE ADURESS OF THE MAIN CONTROL AND STATUS REGISTER
R2 = THE DRIVE NUMBER POSITIONED FOR LOADING INTO DEVICE

R4 & INDEX NUMBER TO GET TKRU THE TADLES FOR THE CORRECT INFORMATION

691

692
693
694

R3 = POINTER TO THE FUNCTION TABLE

134

696
697
698

e
1.

699
798

AFTER A SUCCEYSFUL BpoY THE REGISTERS ARE AS FolLOQWS!

RO » THE DR!VE NUMBER RIGHY JUSTIFIED (8 »

Ry o THE ADDRESS OF THE MAIN COMMAND ANO STATUS REGISTER

} e

X0""'900"'"""'Q?"'Q'O"""Q'0"0"'"'000"'900""'0'0"""00'

l""00"'00"0""'0"'9'0'0"'0'0""'0"000"0"""00"0""0"00"'

701

722

793

798

173000

173000
V9495

736

739

173902
173010
173012

y32761
J1774
320430

pedBadL

173014

113720
V31083

177%97¢

173028

177778

B BASE2

(SBTTL

COOE To WAIT FOR TULR YO COME oN INE

WALTS

BIT

BEQ
]

GNSHR, Ry

(PC)+,RY

BNE

+WORD

173p36
173042
173044

173950
173p52
173954
173060

173064

116493
JE0L74

173970
173872
173874

nio21L
a00743
552311

173976

125711

173108

173102
173110

173142
173114
173116

173128
173122

173324

173126

173130
173432
173134

1731492

173142
173144

173146
173152
173156

180376
312764
112314
198711
108376

410264
ned40

210211

173162

173172
173174
173176
173200

173202

;RIGHT SNIFY R@ ONE PLACE

LLTY ]
MOV

n2
CYRPTH(RA) , Ry

;PUT UNLIT NUMBER IN UPPER BYTE OF R2
:LOAD MAIN CSR ADDRESS INTO R}

JMP

SADDRY (R4)

;JUMP TU START OF PARTICULAR goOT

Rié,R2

CMOPTH(R4) ,R]

;COPY UNLIT NUMBER INTO R2

i GOAD POINTER TU FUNCTION TABLE

Tyig2:

MOV
R
8!8

18!

1878

JCOMMAND REGISTER ADORESS 1% 172%22

R2,(RY)
WALT
({R3)+, (R1)

‘tOAD UNIT NUmBER INTO C,S.R
D WAJT FOR SELEGTED DRlVE TD COME ONLINE
;'OR REWIND COMMAND INTO C,S,R,

(R1)

;SEE IF THE REWIND 1S COMPLETE

pel, 2(RL)

;SET RECORD BOUNTER 710 SKIP ONE RECORD

aplL

MOVE
1878

(R3) &, (HL)
{R1)

MOV

oaere2

uPL

aMl
BR

AGAIN
CMNSGO

(1)

;THIS COMMAND ALSO SETS 809 BPI 9 CHAN,

;WAJY FOR BlY @7 OF C.8,R, 10 BE SET

:L0AD SPACE PORWARD COMMAND INTO C,5.R,
;SEE IF THE SPACE 18§ COMPLETE
;MALT FOR BIY @7 OF C.S,m, T0 OE SET

;CHECK THME ERROR FLAG FOR THE TM13/TU1e

;RE=TRY BOOT |F THERE WAS AN ERROR
;BRANCM YO COMMON READ CODE IF NO EHRORS

,8BTT_

THIS IS THE START OF TWE TC11/7TUS6 B0OT STRAP (DECTAPE, TC11-6)
JCOMMAND REGI§TER ADDRESS 1B 177342

TUS6!

MOV
LIL)
ST

177776

148

R2.(R})
(R3)+, (R1)

(Rl)

T&Y

-Z(Rli

MOV

RZ,(RY)

8PL

B8R

AGAIN

CMNS60

:LOAD gN!T NUMBER INTO C,S$.R,
;"OR¢ REWIND COMMAND INTO c.S,

.SEi IF ERROR BIT 1§ SET
iWALT UNTIL 01T 35 OF C,S,R, 18 SET
;18 THE ERROR

'END ZONE'

;BRANCH IF NOT *END ZONE'

;RE=L0AD DRIVE NUMBER AND CLEAR REVERSE BIlY
;BRANCH TOD COMMON READ CODE-

JSBTTL

THIS I8 THE START QF THE Rx11/RKES BOOY STRAP (DECPACK D1§K CARTRIQGE, KxileD)

RKSS:

ASH

JCOMMAND REGI§TER ADDRESS 1§ 1774p4

MOV

¥9,H2

SLEFY SHIFT UNIT NUMBER % PLACES

EHNSBQ

;@RANCH TQ COMMON READ CODE

R2,6(HL)

;LOAD UNIT NUMBER INTO DEVICE

L88TTL

THIS IS THE START QF THE RP1I1/RPES HOOT STRAP (DISK PACk, RP11+C)
JCOMMAND REGIJTER ADDRESS 1§ 176714

RPE3:

MOV

,$BTYL

THIS 1S THE S{AKT OF THE COMMON REAU CODE

CMNSGO?t MOV
181

MOVD

T§TE

aPL

TSY
8Pl

100012

;TW1S WORD WILL BE ASSEMBLED AT 773024

TULE:

18t

177020

s THEN READ SWITCHES ON THE M9381

;TO DETERMINE DEVICE TYPE AND NO,

87
8lc

87T

aeees
000906

i1F SWITCH REGISTER 1S ZERO

THIS I8 THE STAHT OF THE TWii/TULR BOOT STRAP (MAGNETIC TAPE, THMil)

200406

J72227

1BRANCH TO DECODE IF THE LOWER

;BYTE 1S NOY ZERO

LSBTYL

100563
JOgaL7

052311
003711
100376
w3761
100153
J1021d

;READ SWITCH REGISTER INTO RE

;COPY DEVICE AND UNIT NUMBER
iLEAVE DEVICE NUMBER IN R4
uSHlfT R4 RIGHT 2 PLACES 10 BE 2 o 76
;ADJUST R4 TO INDEX THRU TABLE (B =~ 74)
;LEAVE UNIT NUMBER IN Mg

MOV

281

J108211

RE, R4
#eCRONIVR, R4
#a2,R4
=(R4)
#1C7, K0

MOV
eic

MOV

173%2¢
173942
173564

177777

ASR

ASH

17777¢

208711

173162

173176

#i00¢2

Jea3ve
v16401

TO BC SEY BY ORIVE
.nnancu Yo conrxnu: BOOTING FROM TUiE

THIS I8 THE CyDE TO READ THE SWITCH REGISTER AND DECODE IV

QooRve

177427
177776

EETED onxv: ON LINE
.xs ruz£ TERES

MQVD

173¢24
173p2¢8
1738392

V42724
72427
pe5744
42702

WALT
TU12

.8BTTL

p12709

326200

#TUR, =2(R1)

START:

MOV

0100p4

;ORANCH TO START OF BOOT STHAP

B8R

173022

1730932

START

BOOT:

CHP

R2. (RY)

#e812.42(RY)
(R3),(R1)

(R1)

(R1)
23

#12,R¢

5-79

i, OAD THE UNIT NUMBER INTO THE COMMAND REG,

i 0AD WORD CQUNT OF 312 WORDS

;LOAD READ FUNCTION INTO C.S.R,

;SEL IF FUNCTION IS COMPLETE
;MALT UNTIL BIT @7 OF C,S.R,

1S SET

;WERE THERE ANY ERRQRS ON THE YRANSFER
;1F NO ERRORS BRANGH TO SEC, 800Y

;1S THIS THE RW72/Ty16?

173206
173219
173216
173223
173222
173224

173226

0eLL3e
222764
021124

a201pee

ONE

sEpNLY

205011

ONE
CLR

#FCE,16(R1)
AGAIN

09497

CLR

163e00

17323¢

173236
173242

1732%0

173252

173254
173268

173262

173264
173279

173272

175328

173382

173306
173319

173314

vieee2

2327g2
¢10261
232761
881774
112311
125763

120379
11231
165761

12983735
212764
112314
179761
100379
w1166}

THIS

IBeL2

STANT

181

;GOPY

i*OR’

(=3)+.(u1)

28!

132(Ry)

020012

38!

12(R1)
38
fey,8(RY)
(R3)e, (K1)
13RS
4y
($P), $4(RY)

o
(N3)

177777
431

nEeale

n00419

THIS

TME

e, (AY)

173336

118064

] LUL

posNLY

110844
11661

vose1eY
0180630

1733%2
173356

216164

JAPULG

173360
173364

173366

17337¢
173374

173376

173420

173404

173426
1734102

173416

173422
173424
173426

173439

173434
173436

173442
173444

173446

173452

173452
173454
173456

173462

173464
173466

173479
173472

242790
go1402

225203
132714
01778

111314
012702
165711
108376
112761
277296
<32711
a21775%
100420
112711
103711
1208376
116122
128792
100372
ge%007

oeReas

va0Yey

STARY

RY,10(RL)

(R3)e, (RY)

iWALY UNTIL 91T 27

RO, 10CRY)
(3P)
3B (1)
,

.'.TTL

THIS

CMNSRH1

nsv

THIS

RXOY:

Bic
BEQ
INC
alre
8EQ
MOVE

33!

5A0402

1:("1):16(!1)

8877y,

seove2

IS THE START OF

CRNSGD

WITH SLAVE NUMBER

IS BET

;HAF

THE

SWALT

DRIVE FINISHED THE
UNTIL BIT g7 IS SEY

SPACE?

;L0AD UPPER ¢ BITS OF HUS ADDRESS

THE

JOIN COMMON RM?72 CODE

RH7§/RPE4

1§ 176788

;SELECT

BOOT

STRAP

(DISK

PACK,

RWPPA)

UNIY NUMBER TQ BooT FRoM

JSSUE READ«IN PRESET COMMAND

;QET FMT22 & ECC INWIBIT 81718
;LOAD UPPECR ¢ BITS OF BUS ADORESS
;G0 JOIN THE COMMON RH7® GOOE

(FIXED WEAD DISK,

RWEI4)

IL0AD THE DRIVE NUMBER TO B0OT ann
iLOAD UPPER
¢ BITS OF BUS ADDRES
THE CeMmON RMe78 CQDE
sTURN OFF ANY ACTIVE ATYENTION F AGS
sBRANCH Y0 COMMON READ CODE

I8 THE STANT OF THE RX11/RXZ1 HOOT STRAP (FLOPPY DISK)
JCOMMANY REGIJTER ADDRESS 1y 177470
#0, R0
1%
R3
49, (NL)
18
(H3), (R

JMAKE SURE UNIT NUMBER 1S ZERD OR ONE

;SKIP

BPL
MOV
309
BlY
BEQ
BMI

[ ]
#801,2(R1)
RZ,2%
#108048, (R1)
38
AGAIN

aPL
Move

49
2(R1),(R2)+

BPL
CLR

s¢8s, (R1)

(R1)

«8BYT

THIS

FUTDEY!

HALY

LT]

1§

THE

START

INST

RESERVED

Fom

FUTYRE

+WORD

pPeQBY

{RESERVED

TST24

iG0
SETUP MEMORY
JMAIN MEMORY AND

RESET
JHP

5-80

NUMBER

Z&RQ

SEY

DEVICE

s THERE 13 NO BoQT YEY

L)
opeecy
pEsooR
o02¢0¢
pgoopoY

UNIT

;1S YHE "TR" BlT SET?
;WALT UNTIL BIT 27 OF RXCS 1S SET
;L0AD SLCTOR NUMBER OK TRACK ADDRESS
+LO0UP BACK TO (OAD SECTOR NUMBER
;CHECK FOR “ERAORTM QR “DONETM
PWALT UNTIL BIT 15 OR BIT 25 OF RXCS IS SEY
;BRANGW YO TRY AGAIN 1F ERROR
iLOAD "EMPTY QUFFER"TM COMMAND INTO RXCS
;18 ‘TR’ BIT SET?
sHALT UNTIL BIT a7 OF RXCS IS SET
;STORE DATA (R2 STARTS AT @ & GOE.T0 177)
i1% BIT 87 OF MEMORY ADDRESS SET?
;BRANCH IF NOT 128 BYTES YET
;START SECONDARY BQOT AT VIRTUAL ZERD

+WORD
+HORD
+WORD
+WORD
+WORD

;18 THE "DONETM BIT SET?
;WALY UNTIL YHE DONE BIT
;LOAD THE READ COMMAND
;LOAD LOOP COUNT INTO R2

#2,R2
(R1)

MOVE
1378

JPOINT TO UNIT ONE’'S READ COMMAND

MOV
1878

7878

ABAING

TAPE SYSTEw,

Y0 { RECORD

Hove

14eeas

165950

INTO

2 FORMAT,

LI LR

23!

120040

NUMBER

THIS 18 THE SCANT oF THE RM/P/RS84 BOOT STRAP
JCOMMAND REGIYTER ADDRESS 1§ 172348

k-] J-F

170001

UNIT

899 BP]

o..TTk

(MAGNETIC

; ISSUE SPACE FORWARD COMMAND

;G0

li‘lll.&?(li)
( P).S9(RL)
CMNSRH

NOV

nagude

2710000
cagoco
yIoBve
J30002
olX124]
GPAve
L 30000

30437

MOVE

MOV
HOV
MOV

[1]

173349
173344

2878

RPB4:

J14000
30085¢

THE START OF w9381 BOOTSTRAP
STATUS TO ASSUME AT BOOY TIME

SSET SKIP COUNT

FCOMMAND REGIYYER ADDRESS
173316

WILL StoP

STATUS REG
; ISSUE REWIND COMMAND
;18 QRIYE READY BIT SEY YET?
;WALY FOR DRIVE READY BIT
; ISSUE DRIVE CLEAR COMMAND
;18 DRIVE READY 81T SET?

CMNSRN

JJ0TT

AGAIN
COUNT ERROR?

;L0AD UNIT NUMBER
i 13 THE MEDIUM ON [ INE
sMALY FOR BT 12 OF DRIVE

#MOL,12¢RY)
1

aNd912

9912

TRY

RH78/7yL6 BOOT STRAP

THE

RE,R2
s88L300,R2
RZ,32(RY)

naee32

viedee

FRAME

JCOMMAND REGIJTER ADDRESS 1§ 172448

TULé!

J8130¢

THE

IF
ERROR

iVEGTOR Y
$PROCESSD

08834y
13

NOT

iWAy

iTHE DECTAPE MOTJON IF DEVIGCE WAS Tuse
;$TART SECONDARY 800" AT VIRTUAL ZERD

14500y

+HORD

;ORANCH

;BRANCH JF NOT TO TRY AGAIN
sCLEAR COMMAND REGISTER THIS

(R1)

+WORD

«3034p

% 12440

173232

a;axn

Cup

;RESERVED FOR FUTURE

iRESERVED
:REJERVED
;RESERVED
:RESERVED

;Cbclfl

THE

FUTURE
FUTURE
FUTURE
CUTURE

FUTYRE

WQRLD

AFTER

EXPANSION

EXPANSION
EXPANSION
EXPANSTION
EXPANS]ON
EXPANSION

ERROR

MANAGEMENT AND TEST
THE CACHE AGAIN,

TWY16)

.SBTTL

FUNCTION GODEY FOR THE ALL OF THE DEVICES

iREWIND SEbEOTED DRIVE AND SET 808 BPl
;SPACE FORWARD COMMAND FOR 1ULS

+HORD
BYTE

06081/
et

JHORD

004209

iSEARGCH FoR 8LOCK o, REVERSE DIRECYION

LBYTE

o83

;READ COMMAND FOR TUS6, RK2%, RPOJ

+BYYE
JBYTE
+BYTE
BYTE

y?
P11
931
p71

REWIND SELECTED DmivE
;QRIVE GCLEAR COMMAND
;SPACE FORWARD
;READ FORWARD

281

;READIN PREBET

297

;READ SECTDR ComMAND FOR DRIVE ZERQ

]
-]

;SPAGE FOR FUTURE DEVICE COMMAND
;SPACE FOR MORE COMMANDS

173476
173800

peos17

173%p2
1735p4
173504

Je4003
945

RKOSS!
RPB3S!

173505

2?7

TyLes:

173536

173507
173510

Ril
231
871

173914

021

074

RSD4s)

JBYTE

1733513
173514

ea7
827

RXO1S!

BYTE

837

173513
173816

2090
eaaeae

FUTDES:

JBYTE
+WORD

JI8TTL

COMMAND AND STATUS REGISTER ADORESS TABLE

172522

CSRPTRS

+WORO

17292¢

JHORD

+WORD
JHORD
+WORD

176704
172044
17747

173901

173512

173320
173522

173%24
173526

173530
173932

173534

473536
173549

173542
173544

173546
173852
173852

173554

173556
173962

1738562

Tyiest

Q11
203

{BYTE

TyBées!

RPA4S:

177342
177404

176714
¢29002

173972
173974
173876

173600

173602

173604

+HORO
«WORD
+HORD

JHORD

172442

176700

172042

177172

173474

;READ COMMAND FOR AP@4 & RSQ4

g71

JREAD SEEGTOR COMMAND FOR DRIVE ONE

;THIS 1S THE C.S,R, ADDRESS FOR TUis

177342
177404
17671¢

;THIS IS THE C,5,R,
iTHIS 1S THE C,S,R,
;THIS 18 THE C,5,R,

;THIS 1S THE C,.%,R,

ADORESS FOR THE TUS6
ADDRESS FOR THE RKES
ADORESS FOR THE RPPS

ADORESS OF A FUTURE OEVICE

iTHIS IS THE C,S,R, ADDRLSS FOR THE RW78/Ty2d

172449

3THIS IS THE C,S,R, ADDRESS FOR THE RH7D/RPga
sTHIS 18 THE C,5,R, ADORESS FOR THE RH7B/REp4
;THIS 1S THE C,.5,R, ADDRESS FOR RX11/RX§1

S8TTL

FUNCTION POINTER TABLE

+HQRD

+WORD

TYLP8

TUSes

iPOINTER TO FUNCTIQN

+HORD
MORO

JHORD
+WORD

RKpSS
RPE3S

FYTDES
TYLeS

SPOINTER YO PUNGTION TABLE FOR THE RK®S
;POINTER TO FUNCTION TABLE FOR THE HPQ3

;POINTER TO FUNCTION TABLE FOR A FUTURE DEVICE
;POINTER TO PUNGYION TABLE FOR THE RM78/TYLo

«WORD

RXp1S

sPOINTER TO FUNCTION TABLE FOR THE RX@1

173902
173504
173504

173518
173503
173511

+WORD
HORD

173512
173%13

ADORS?

173870
173424
173146
173160
173452
173238
173316
173349
173362

;READ COMMAND FOR Tyi¥

CMOPTRS

JB8TTL

1738564
173366
173579

+BYTE

203

sPOINTER TO FUNCTION TABLE FOR THE RH7p/RPB4
;POINTER TO FUNCTIQN TABLE FOR THE RH78/RSN4

RPQ4S
R§B4s

STARTING ADLRESS TABLE

+HORD

TYi2

JWORD
JWORD
+WORD
LNORD
+HWORD
+NGRD

RKEY
RPQY
FYTOEV
TV1a
RP24
R§04

+NORD

JWORD

+387TL

TABLE FOR TWE TULD

3POINTER YO 'UNCTIO” TABLE FOR TKE TU;G

ADDRESS FOR THE Twil/Tyil

JSTARTING
7211178:6
Pgfl THE
ADORESS FOR
;S?ART!NG AUDRESS
THE RK11/RK§5

Wil

i $TARTING
iSTARTING
;8TARTING
;STARTING
;STARTING
JYTARTING

RX21

ADQRESS
AUQRESS
AOUDRESS
ADDRESS
ADDRESS

FOR
FOR
FQR
FOR
POR

THE RPLL/RPES
A FUTURE DEVICE
THE RH78/TUL6
THE RM78/RPp4
THE RH7B/RS§4

;STARTING ADORESS FOR THE RX11/RXEL

CACHE MEMORY PI1AGNOSTIC TESTS

VVVVVV
3VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV
VVVVVVVVVVVVVVVV
iVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV

THE rgLLouxuc TWo TESTS ARE CACME MEMgRY TESTS, IF EITHER gof

THEM

FAILS TO RUN SUCCESSFULLY THEY WiLL COME TO A HALY

IN THE M93@3 RGM, 1F YOU DESIRE TO TRY TO BOOT YOUR SYSTEM, OR
DIAGNOSTIC AMYWAY, YOU CAN PRESS "CONTINUETM AND THE PROGRAM

WILL FORCE MIYSES [N 80TM GROUPS OF THE CACHE AND GO 70 THME
POOT STHAP THAT HAS BEEN SELECTED,

,'"0"0'00!""9"'0!0"100"""0’0"000'09'00"0!0"0'0'0""0"00"'
0
]"9""'9'90"'00""0'0'0"'0"0"""0"9000'0'"0'00"""'0'0"0'0
+

173606

" BAgE2 + 6W6

ll.....U..I...........O..l........I)...0.0......I..'....O.......Q...O...
e
IA]

X}
je

e
13
je
IR]

13
}e

je
e
}e

173606
173612

173616
173620

173622
173626

212704

012748
010302
ni0200
“12703
2n8LR4

129252

200030

1§¢
pacage

7TEST28

TEYT CACHE DATA MEMoRY

AN ADDRESS COMPLEMENTS
§ AND THEN GRUYP 3, 1T LOADS 952525 INTO
THAT
IT TWICE AND THEN READS THE DATA, THEN 1T CHECKS TO ONINSURE
THE SAME
REPEATED
1S
SEQUENCE
THE
THE DATA WAS A HIT, THEN
ADORESS WITH 425252 AS.THE OATA, ALL CACHE MEMORY DATA LOCATIONS
ARE TESTED IN THIS WAY,

iF EITHER GROYP FAILS AND THE OPERATOR PRESSES CONTINUE THE
PROGRAM WILL [RY TO B0OT WITW THE CACHE DISABLED,
THE REGISTERS ARE INITIALIZED AS FolioWS FoR THIS TEST!
Rg » 10 (ADURESS) R1L s 2 (COUNT), R2 = 1890 (COUNT)

R3 & 4998 (COUNT), R4 = 125282 (PATTERN) R3 s 177746 (CONTROL REG)
3P = 172874 (FLAG OF ZERD PYSWED ON STACK)

'l..!..QO.......Q...Q....Ql.l..........Q.Q...'0..........Q..I.........
TgT26!
;8ET YP R4 FoR THIS TEST
#4129292,R4
MgV
e

173606

.8BTTL

THIS TESY WILL CHECK THE DATA MEMgRY IN THE GACHE. FIRSY GrgUp

28!
3%

Hgv

nov

MOV

Hov

CoM

SGRPE, (HS)

R3,RP

;FORCE REPLAME GROUP @ AND FORCE.M18S GROUP 3

;SET COUNT TO CONTENTS OF Ry

R2,R0

;SET STARTING AUDRESS INTO RE

;COMPLEMENT DATA IN R4

#2,R1

;YBE 2 PATTERNS IN DATA MEMORY

173630

173632

173634

173636
173642

173642

vif4lp

029110
223110
“21P04
<1401
“39800

173644

6037

173654
173636

200002
CJ0444
~77115

173650
173652

173660

173662

173664

1736792

173672

103402

315720
177221
wi271%
275116
331351

MOV

R4, (RY)

coM
cHP

(HE)
(R@), N4

CoM

177752

ast

TEST

PATTERN

.14}

;BRANCH IF OATA MATCMES

ROR

MmL77/982

acs
HALT

BOOTM(SS

;ADORY RESTY OfF

(RO)+

iMOVE

(1]

iMAKE SURE DATA
COMPARE DATA &
iOATA

TST

;GO

IN TME
BIY 8

BACK

ONE

WIT

TEST

TIME

CACH
IN n:w;nxss

REG,

ADORESS

;FORCE REPLACE

(3P)
13

ADORESS

“CONTINUE® PRESSED

TRY

COMPLEMENT

DATA

ADDRESS

;ORANCH ér NOT OQNE

SGRPL, (RS)

coM
BNE

MATCH

BRANCH IF YES
;CAGHE FAILED TO

RZ2,2%

MoV

DIDN’T

SET

;WAS THE LASY MLMORY REFERENCE A WiT?

R1, 38

308

CoPv4es

THE

;OOYBLE COMPLEMENT DATA AND

HALT

sgt

JMRITE

(He)

bROUP

AND FORCE

MISS

;COMPLEMENT YHE CYGLE FLAG
.LOOP 1F NOT DONE

GROYP @

1g08

H I.Q.l...Q.OQ...Q0.0...000.0.0.0...0..000..OlIli.......m....Q...QQI.....

1009
1810

2011

1212
1013
i014
1215
1916

1017
l1e18
1919
igep
1021
ig22

+8BTTL

TH1S

TEST2/

TEST

TEST VIRTYAL 28K WITW CACHE gN

CHEGKS

VIRTUAL

MEMpRY

FROM

§21998

MEMORY,

FINALLY

;e
i
je

THE THREE PASYES FAIL THE TEST WILL WALT AT wCONT & 2",
If THE OPERATUR PRESSES nCONTINUETM, THE PROGRAM WILL TRY
BOOT WITH THE CACHE DISABLED.

[T STARTS WITH GROUP 1 ENABLED,

CHECKE

MEMORY

WITH WOTH

GROUPS

ENABLED,

UPgN

ENTRY

THE

ncsxsrcas

RP = gP1OJS (ADUREW

R = 1000

025

173674

173674
173702
173722
173704

1935
1236
1837

17372@
173722

1238
1939

173724
173726

1049

173732

1@41
1942

173732

.043
1044

173736

1945

173742

1346

173734

173744

1947

173746

1048

173752

1349
1050

173752

19251

173754

1362

173756

1953
1854
L1855

173760

1056

173762

Las?

173764
173766

1258

1859
1260

UpgN

1062

177746

WiLL

SET

R4 » §7400

(GONTROL REG,),

coan:rxsn oF

J127a2
210302
£10204
V10020
077442

267400

212716
2127¢L

4100348

18!

20803

210302
210204
0e%112
~25110
220028
221401
uo000R
236037

123402
20000
co0407
077413
J11615

TS§T271

THEN
YO

FolLows?

(M:nonv COUNTER),

THIS

TEST

172374

MAIN

(POINTING TO cooc FOR

MEMgRY

FRQM

r{ 3

LT T

STQRAGE

(20K

ADORESS

COUNTER

;FILL

MEMORY

MOV

SGRPR, (SP)

iL0AD

CODE

MOV

R§, RO

;FIHST ADDRESS

BEY

MOV

MOV
COM
QoM
cMP

HALT

ROR

HALT

uese16
v77120
00404

VIRTUAL

CONTROL

ADORESS

CONT!

173766
173772

212715
283726

caggLe

173774

£o0137

173800

#3,RL

R2,R4
{R3)
(RQ)
RE, (R

0ogsuL

L7782
43

WITH

;L00P UNTIL DONE

1292

BYTES)

OCTAL

ADDRESSES

TO FORCE GROUP

;SET PASS COUNT TO THREE

ONTO STaCK

; GOYNTER
;00UBLE COMPLEMENT DATA AND
iMAKE SURE [T IS IN THE CACHE,
;COMPARE DATA, AND SET BIT @ IN WIT/MISS REG
;ALS0 POINT YO NEXT ADORESS
;BRANCH

;DATA

DATA

MATCHES

DIDON'T MATCH R®

ADDRFSS + 2

;WAS THE LASY MEMORY REFERENCE A H117?
;BRANCH

YES

BOOTM{SS

iMIT

FAILED

808

R4, 3S

;L00P

UNTIL

CLR
s08

(§P)
Ri, 28

;ENABLE CACHE ON PASS THREE,
;GET READY T9 FULLY ENABLE CACHE
;RUN THREE PASSES THRU THIS TES

cMP

(SP)+, (5P)+

i8TUP WERE |F
;ADJUSY STACK

MOV

#M1S8, (HS)
(§P)+

JMP

*4B00T

MOV

(3P), (RY)

JUMP

HALT

BOOTMISS!t
JUMP:

R¢,18

1288

| L]

20009
222626

;COYNT
;FIRST

;SETUP

acs

ag:

#67430,H2
RS, RO

R2, R4
RB, (R¥)+

308

1777%2

MoV
MOV

MOV
MOV

1064

.65

AND

221982 THRU 197776 WILL CONTAIN ITS OWN vxa?uau ADORESS,

1261
1063

ANY

31 000.....IQIIQO.QQ.Q...OOOQ.Q...Q..l'...ll.0..0.!.....0QOIQCOOOIDOIQQIO

173726
173710
17374

1g34

Ry o 3 (PASS COUNT 82s 6748@ (MEMORY COUNIER),

(FINST ADDRESS)p

1231
1832
1833

THEN TESTS GROUP B,

iB24

1826
1027
1p28
1929
1838

THRY 157776

TO INSURE THA! YOU CAN GET u?rs ALL THE WAY UP THROUGH MAIN

+END

5-82

;ABORT REST OF

OCCUR

TEST

ADDRESS

"CONTINUETM

+ 2

PRESSED

OONE

;FONCE MISS QGRPL ON PASS 2, FULLY
ON

PASS

;G0 TO B0OT STRAP CODL

THERE [S A CACWE ERROW
POINTER AFYER ABORT

iFORCE MISSES IN BOTH GROUPS OF CACHE
;POINT TO UPPER SIX BITS OF BUS ADORESS
;THAT DATA 18 IN ADDRESS 1772376 (KUPAR7)
;GO YO BOOT BTRAP ENTRY PDINT

REG)

173472

16%0230
1739020
173900

7¢2

789

116
744
1062

964

1047

173766
173542

17335¢
173762
178520

CSAPTR

01SPLA s

177572

s
FCE
FUTOEV

391900

,PP030

10569

173772

K]PAR? »

172376
172342
172356

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MOL
N

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RKDS5S

495

172329

258
851

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177572
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820e

629

118
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380
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4360

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49%»

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1590
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[1.1"]

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173230

422
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173529
1733124

148

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368

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441w

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173476
173074

289
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251

743

169966
169976
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147

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173513

1460
212
278

173512
173360

517

JA2s.
424

134
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929

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338

4200

134
290
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191
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173160
173524
173316
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618e
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109#
257

323
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358
249
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RS04

119

A798

163776

RSQ45

271

10939

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173146

RX21

129w

8gs

331

172316

179200

=X:00007

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RPO3S
RPO4
RPO4S

124

957

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T
PAEH_

618

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292

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172360

K]PDR@ x
K1PDR? s
MAPL2 =
M18S
MMRQ

842

8419

= 30pg44
INOMAP
1693120

KOPARQ s
KDPAR7 5
KIPARG »

782¢

883

942

173513

JUMP

L1311

V14w

173452

FUTDES

791

10584
772

173162

CONT

GRPPQ
GRP1L

V384

173864

ADDRS

AGALH
BASE: «
BASE2 x
goorT
BOOTM]
CMOPTR
CMNSGO
CMNSRH

5-83

3160

362

1957

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1738822

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173002
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163
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287
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293
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242
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8518

1031

427

436
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M4

246

547
651

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841

1836
8gs

883
271

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182
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204
282

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447

418

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342

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558

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183

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642

297

338
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750
415

295

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387

209

227

203

316
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851

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323

313
516

108

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256

148

142
186
161

mQVve

594

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149

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22¢

573

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165
319
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L I'T

APPENDIX A

MODULE AND CONSOLE ASSEMBLY,
REMOVAL, AND REPLACEMENT

No special procedures are required to disassemble and reassemble most of the components and assemblies in the H960-C cabinet or the processor mounting box. This paragraph outlines the procedures for
removing and replacing modules and the steps required to disassemble the console.

A.1

MODULE REMOAL AND REPLACEMENT

The multilayer modules used in the PDP-11/70 are equipped with lock/release type handles, and each
slot in the backplane has card edge and center guides that allow the modules to be installed easily. The
card guides ensure that the modules are not removed or inserted at an angle so great that module or
connector slots are damaged. Even though these features are provided, always install and remove the
modules carefully.

A.2

CONSOLE DISASSEMBLY

Refer to Figure A-1. The following steps are required to disassemble the console:

\ q
(Z’\ \
¢

IPE ;

dsé J}/" Hfln

Ty
11-3427

Figure A-1

Console Assembly
A-1

Turn power OFF at the circuit breakers.

Remove the four screws (A) that secure the bezel; remove the bezel.

Pull off the two switch knobs (B).

Remove the five nylon screws (C) and the console panel.

Unplug the harness power plug P1 from J4 and the signal cables from J1, J2 and

J3.

Remove the three spacers (D) and the three screws (F) that hold the console PC board to i.fihe

processor mounting box. Retain the six adhesive spacers (E) for reassembly.

A.3 CONSOLE REASSEMBLY
The console is reassembled by executing the steps in Paragraph A.2 in reverse
A.4

order.

CONSOLE CABLES

A.4.1
Power Connector
Power is supplied to the console by processor harness plug P1. Insert this plug into

connector J4.

console PC board

A.4.2
Signal Connectors
Three flat signal cables connect the console to the processor modules.
1.

JI connects to J1 on M8134 (PDR, slot 10).

J2 connects to J1 on M8140 (SCC, slot 16); J3 connects to J2 on the same module. J1
on the
M8140 is the connector closer to the edge of the module.

A.4.3 Installation of Signal Cables
The three signal cables are installed with the rough side facing the console PC board.
The red stripe is
on the side of the flat cable that is closer to the power harness connector J4. The
smooth side of the
cable faces the M8134 and M8140 modules.

APPENDIX B

REMOVAL AND REPLACEMENT OF ICs

The PDP-11/70 modules are multilayer etched circuit boards. The four layers consist of two (power
and ground) internal planes, and two etched circuit external layers (Figure B-1). The inner power and
ground planes form a decoupling capacitor between the power and ground planes, providing shielding
between the etched circuit layers and reducing the possibility of noise and/or cross-talk. One advantage in using this type of module construction is that the need to route power and ground signals to
each individual component and IC via etching on the two outer etched boards is eliminated, allowing a
much greater component density on each board.

No. 1

v 4

A
A
Pt
A

A
A
AT
Pai%d
—A
Paitd
Pai%d
A

Palitd

ISNN NSNS NN N NN NN N s e

Paird
A

Zad

ETCH LAYER SIDE

POWER (+5V) LAYER

ETCH LAYER SIDE No. 2
41-0959

Figure B-1

B.1

Cross Section of Multilayer Board

LOCATION OF ICs

On the handle end of the board, the physical location of the last IC in each row is E-numbered to aid in
locating ICs during maintenance and troubleshooting.

The first sheet of each module circuit schematic is a physical layout showing the location of the ICs
and discrete components on that module.

When possible, some IC locations on most boards are not used; these spare locations, provided on a
space available basis, ensure that if future ECOs (engineering change orders) involving additions are
required, they can be implemented more easily.

B-1

When spare locations are provided on the module, each spare location has a number just like one
of
the ICs. The spare locations must also be counted when locating ICs on the board. Thus, when an IC
is
added to a board (e.g., because of an ECO), the IC assumes the preassigned number of the location
into which it is installed. Thus, the numbered IC locations at the handle end of the board, as well
as all
other IC locations, always remain the same.
B.2
IC CONNECTIONS
IC and component connections to the power and/or ground inner layers are normally made as
shown
in Figure B-2A. The ICs and components are connected to the inner layers in this manner to allow the
IC or component to be more easily replaced.
When a component is tied directly to an inner layer, as shown in Figure B-2B, instead of connecting
through an etch as shown in Figure B-2A, it is difficult to remove the component because
most of the
heat from the soldering iron is absorbed by the inner layer, preventing the solder around the
leads of
the component or IC from melting. To minimize this difficulty, direct connections to
the inner layer

are made by a vein-type connection as shown in Figure B-3. This type of connection
reduces the
connected area between the plated-through hole and the inner layer. This reduces
the amount of heat

transfer to the inner layer when heat is applied to the plated-through hole when melting solder
and
removing component leads, or removing excess solder once the lead has been removed.

ETCH

CONNECTION—

GROUND LAYER__\_\
X:\ i ANANAN

MADE TO

CONNECTION

NO CONNECTION
TO INNER PLANES

N A\
\

NORMAL

CONNECTION

COMPONENT

TO___

INNER GROUND LAYER

CONNECTION

cAP

\
-.(—

N
¢

aT\NN

INNER

LAYER

CONNECTION

INNER

MADE TO

GROUND

LAYER

TIA\ NN NSy
NN

NN\

)

NO CONNECTION TO
INNER

POWER

LAYER

NN
PLATED THROUGH HOLES

LAYER

CONNECTED

CONNECTION MADE TO ___
INNER POWER
B. COMPONENT

PLATED THROUGH HOLES

DIRECTLY

INNER

LAYERS
11- 096

Figure B-2

Component Connections to Inner Layers

COMPONENT LEAD

INSULATING
LAYERS

PLATED THROUGH HOLE

INNER GROUND PLANE

CLEARANCE HOLE THROUGH
THE INNER PLANE

L VEIN CONNECTION BETWEEN INNER PLANE
AND PLATED THROUGH HOLE

11-2300

Figure B-3

Top View of Component Connection

Made Directly to Inner Layer

B.3

IC AND COMPONENT REMOVAL AND REPLACEMENT

Because the etch and plated-through hole eyelets are so small, extra care should be taken during the
maintenance and repair of the multilayer modules, especially when soldering and unsoldering components. Certain tools (or their equivalent) are recommended for use during removal and replacement
of ICs on the multilayer modules. The manufacturer and type of part number of each tool is indicated
in the list below:

Small diagonal cutters, Utica No. 47-4
Soldering iron, Paragon No. 615
Pliers, Utica No. 23-4

B.4

REMOVAL AND REPLACEMENT OF PLASTIC CASE ICs

To remove and replace a plastic case IC and to preclude damage to the multilayer board, the procedure
described by Figures B-4 through B-10 should be strictly adhered to.

B-3

Figure B-4

Removing a Defective IC From the Module

Defective IC leads are clipped, using small diagonal cutters (Utica, Part No.
47-4). Cut the leads as
close to the body of the IC as possible to allow the remaining leads to be removed
more easily.

B-4

Figure B-5

Defective IC Removed

IC location after the IC has been removed - with the IC leads still in the board. Locate the leads of the
IC just removed on the soldered (back) side of the board and cut all leads to avoid difficulty during

their removal.

%
s

®
%

R
%7

:,“‘ w W *,‘r‘ ,*,.-'w M

@ 8 ET

Figu're B-6

Removing IC Leads

IC leads being removed from side 1 of the board. Apply heat to the lead until the lead becomes loose.
Then remove the lead by pinching with the soldering iron (Paragon, Part No. 615) and pliers (Utica,
Part No. 23-4).
CAUTION
Leads that are connected to an inner layer require
more heat because much of the heat is absorbed by
the inner layer. It is helpful to add solder to the lead
first causing more heat to be conducted to the solder
in the eyelet around the lead.

B-6

Figure B-7

IC Lead Removed

Lead directly after removal from the eyelet using the soldering iron and pliers.

B-7

6201-6

Figure B-8

Applying Solder to Refill Eyelet

After all of the IC leads have been removed, remove the excess solder remaining in the eyelets prior to
inserting the new IC. This figure shows solder being applied to the eyelets after all the leads have been
removed. The extra solder absorbs excess heat and keeps it from being applied directly to the etch of
the plated-through holes.

6201-9

Figure B-9

Removing Excess Solder From Eyelet

Once the eyelets have been refilled with solder, as described in Figure B-8, remove the solder using the
soldering iron and solder extractor as shown above. In this figure, the eyelet has no connection to the
board inner layers; thus, the solder can be extracted from the same side of the module to which the heat
is applied. However, in cases where direct connections to the inner layer are made, heat must be
applied to one side of the module and the solder must be extracted from the opposite side due to the
heat sinking properties of the inner layers. In this case, the module should be in a vertical position to
allow access to both sides of the module simultaneously.

'EEAERER

&Nwwn@mfi@

5201-8

Figure B-10

IC Location Ready for Insertion of New IC

IC lo¢ati-on after all the eyelets have been cleared of solder.
Inspect the eyelets to ensure that no excess solder remains. If all the solder is not removed,
refill the hole as described in Figure B-8 and remove the solder again as described in Figure
B-9. Continue this procedure as required, until all of the eyelets are cleared of excess solder.
Use a cleaning solvent and brush to clean the IC location of any excess solder flux.
Thoroughly inspect the IC location and surrounding area for solder splash and damage to
etch lines and plated-through holes.
Ensure that none of the leads is bent, and insert the replacement IC in the holes. When
inserting the replacement IC into place, avoid ending the leads on the opposite side of the
module; this makes future removal of the IC easier, should it be necessary.
CAUTION
If the leads must be bent to hold the IC in position for
soldering, avoid bending the leads more than 45
degrees, using only one lead at each end and on opposite sides of the IC.

Solder in the new IC from the opposite side of the module. Use enough solder to fill the
holes and make a good connection. Avoid using an excess of solder to prevent overflow on
the top side of the board, which could cause a short under the body of the IC.

Once all the solder connections are made, clean and inspect the area for any damage. Cut off
IC leads close to the board. Take necessary corrective action for any defects that are found.
CAUTION
After installing the ECO or replacing a faulty IC on
a module, ensure that no short circuit exists between
the power and ground planes of the module. Do this
before replacing the module in the equipment.

B-10

APPENDIX C

EQUIPMENT CONFIGURATION AND REVISION STATUS

LABELS AND SHIPPING FORMS

The following paragraphs describe the MUL sticker, the ECO status sticker, and module revision

status. The MUL sticker lists the equipment complement system serial number, etc.; the ECO status
sticker provides information about the current ECO status of wire-wrap devices; module revision
status shows the current ECO status of the module.
C.1
MECHANICAL STATUS STICKER
See Figure C-1. This sticker is located on the rear of the mounting box. Box type is PDP-11/70, H960X. A letter designates the revision level at manufacturing. Field installed ECOs should be entered as
performed.

MECHANICAL STATUS

BOX TYPE

REVISION LEVEL AT MFG.

FIELD INSTALLED MECHANICAL ECOS
ECO NUMBER

Figure C-1

C.2

Mechanical Status Sticker

ECO STATUS STICKER
The ECO status sticker, Figure C-2, is located on the inside of the module door in the CPU or BA11FB mounting box. This sticker is filled out for installation of ECOs to wire-wrap devices such as the
KB11-B, C or the various system units. Table C-1 describes how the various columns are to be filled
out and the department responsible for filling out these items.

& Eco STATUS %
Q.

Ser. No._(2)

Device

NO. DATE INIT|

COMMENT

]

12-(7 76)-

1097-N172
11-1498

Figure C-2

Table C-1
Item No.

Responsibility

Production

ECO Sticker

Completing the ECO Status Sticker
Description

Option

designation code for applicable

device.

Production

Device serial number.

Production

Original wire wrap revision
letter (e.g., ORIGINAL REV. B.)

Production/Field Service*

Numerical portion of ECO/FCO number

Production/Field Service*

Installation date of ECO/FCO.

Production/Field Service*

Initials of person installing ECO/FCO.

Production/Field Service*

Necessary comments about ECO/FCO

or its installation, (e.g., only
part 2 installed).

*If an option is installed in the factory, production has responsibility for filling out an ECO sticker. If the option
is an add-on in the field, field service will fill out items 4 through 7.

NOTE: ECO Status Sticker is located on the inside of the module door of the mounting boxes.
C-2

C.3

MODULE ECOs

C.4

MODULE UTILIZATION LIST (MUL) STICKER

Each module is stamped with the alphabet (except for G, I, and O) to record various circuit schematic
revisions to a module. When a module is shipped from the factory, the actual revision letter from
production is stamped on the handle. When ECOs that revise modules are installed in the field, scratch
off the appropriate letters from the module. For example, if an ECO corresponding to revision F of the
module was installed and an ECO corresponding to revision E of the module was not installed, the
letter F would be scratched out and the letter E would remain intact.
This sticker, Figure C-3, located on the top panel of the A11-FA mounting box (left-hand side),
provides a quick, convenient tabulation of the various equipments located in a particular system.
Additional information such as serial number, comments, technical tips, and installation of partial
ECOs is also shown on the sticker. Table C-2 describes the manner in which the sticker is to be filled
out and indicates the department (production/field service) responsible for filling out the various items.
Table C-2

Completing MUL Sticker

Item No.

Responsibility

Description

Production

System Serial Number, Unit Serial Number

Field Service

Acceptance Date of installation at customer site

None

Not Used

Field Service

Comment area. Note ECO/FCOs
installed, partial ECO/FCOs,
miscellaneous information about
module or slot.

None

Not Used

Production/Field Service*

Enter device type as installed.

*To be filled out by production if option or device is factory installed. If option or device is an add-on in the field,
field service will complete these items.

NOTE: The MUL Sticker is located on the top of the KB11-B, C cover over the modules.

C-3

kb1ib

Il INDICATES NON STANDARD VOLTAGE PRES

INDICATES OPTION

SYSTEM SERIAL NUMBER

CACHE MEMORY
MAP
B*] RH70 CONTROLLER A*
SMALL PERIPHERAL CONT. |[RH70 CONTROLLER D*JRH70 CONTROLLER C* RH70 CONTROLLER
, \ 43
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M5904 | M5304 JJrssoafmseoamsooaf
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hUSED

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gct || Ma1s2

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st
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\\\

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FLOATING POINTTM \ MISCyrow

FPT A
\ me136 | M8135 | Ma13a | Me133 | ma132]| ma131 | mer3o | menia | meniz | meuis fmenid) |
I | msi37 \\
| maraoP | ma13s
41 ] Me1as] me1a \\ ms143 || me142
cce | scc | ssr | sap NN uec § TMMc | por | rac | rc | ora | pap | Fxp | FRM | FRL | FRH

M9302
UBUS

CENTRAL PROCESSOR

MEMORY MGT.

FOATELSTALLED

-~ | UNIT SERIAL NUMBER
NUMBI N\ \

BB BBERERE

DTM iNOT\ aom

MAINT

NOT I
USED

M8139
TG

\
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4 m

P B

USEDY

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M787

kw1 ID
CLOCK
M9301

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7l Tl sl L4

01
11-3284

| UNIT SERIAL NUMBER N\ \

LSYSTEM SERIAL NUMBER 4 DATE INSTALLED
[
FLOATING POINT* \ MISCJ]row
CENTRAL PROCESSOR
MEMORY MGT. ’

. INDICATES OPTION
INDICATES NON STANDARD VOLTAGE PRESENT
C
kb11
.
MAP
A*
SMALL PERIPHERAL CONT. |RH70 CONTROLLER D*| RH70 CONTROLLER C*]RH70 CONTROLLER B* RH70 CONTROLLER
\“
| M504 | M5904

CACHE MEMORY
rer A
% m8143 | ms142 | Ms140 |mai3s.§ M8137 N ma136 | me135 | me132 | ms123 | ms132 | me131 | me1so | M129 me128| me127f mer2e]\T X
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UBUS
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OR
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| M8153 | Me152 | M8151
mM7800
oLt | Ber | awr | cst

| M8 152 | M8151
me153
BT | awr | csT

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8153
BCT | awr | csT

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rg\

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NOT Yo
M787

USED

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01
11-3463

Figure C-3

MUL Stickers

C-4

APPENDIX D
IC DESCRIPTIONS

The following ICs are described in this appendix. The S or H version of an IC listed below merely
indicates its a high-speed version.
3101
7474
7485
8598
74112
74151
74153
74154
74155
74157
74158
74161
74174
74175
74181
74182
74187
74191
74193
74194

Random Access Memory

D-Type Edge-Triggered Flip-Flops

4-Bit Comparator

Read-Only Memory

Dual J-K Edge Triggered Flip-Flops

8-Line to 1-Line Multiplexer

Dual 4-Line to 1-Line Data Selectors/Multiplexers

4-Line to 16-Line Demultiplexer
3-Line to 8-Line Decoder
Quadruple 2-Line to 1-Line Multiplexer
Quadruple 2-Line to 1-Line Multiplexer
4-Bit Binary Couner
HEX D-Type Flip-Flops

Quad D-Type Flip-Flops

4-Bit Arithmetic Unit with Full Look-Ahead
Look-Ahead Carry Generator
1023-Bit Read-Only Memory
4-Bit Binary Counter
4-Bit Binary Counter

Parallel Access Shift Register with Mode Control

3101 16-WORD X4-BIT MEMORY
Easy memory expansion is provided by an active LOW chip select (ENB) input and open collector OR
tieable outputs.
An active LOW Write line WR controls the writing/reading operation of the memory. When the chipselect and write lines are LOW the information on the four data inputs Dy to Dy is written into the
addressed memory word.
Reading is performed with the chip select line LOW and the write line HIGH. The information stored
in the addressed word is read out on the four inverting outputs M0 to M3.

0O—— w1

During the writing operation or when the chip select line is HIGH the four outputs of the memory go
to an inactive high impedance state.

)

[WR

ENB]

NON-OVERLAPPING

16 X

ROM DECODER

MATRIX

OF STORAGE CELLS

M3 (1)fo—

0 Inz

M2 (1)jo—2
3101

& 1o

M1 (hp—L

4 oo
A3

Mo (1)jo—>
A2

Al_AD

‘VCC=PIN 16
GND=PIN 28

LU
N\

Jer

|13 14 |15 1

IC- 3101

D-2

7474

DUAL FLIP-FLOP

STANDARD CONFIGURATION
PRESET

TRUTH TABLE FOR

02 & 05
04

7474 STANDARD CONFIGURATION

(EACH FLIP-FLOP)

Preset
Pin 4(10)
High
High
High
Low
Low

Clear
Pin 1(13)
High

D fnput
Pin 2(12)
Low

High
Low
High
Low

High
X
X
X

1 Side
Pinb
Low
High
Low
High
High

—C

0 Side
Pin 6
High
Low
High
Low
High

05
—

0106

Jo1

1[0

'Q-C
3

o5
o[ 22
Joa

CLEAR

PRESET

12[ . 09

12 4 08

7474

1|08

—o

X = irrelevant

CLEAR
Veer PIN 14
GND:PIN 07

D-3

CLEAR

tn = bit time before clock pulse.
tnt1 = bit time after clock pulse.

PRESET

7474

th+1

1|08

REDIFINED CONFIGURATION

1}09

L Fo

OFo9

T10

CLEAR
1C-7474

7485 4-BIT COMPARATOR
The 7485 performs magnitude comparison of straight binary or straight BCD codes. Three fully
decoded decisions (A > B, A < B, A = B) about two 4-bit words (A,B) are made and externally
available at three outputs.

7485

— 15 A3
—

131,

a-gl2&

__.._L‘_ BA1

A<B __OL___

—

©O91gp
1

®lne
INc<

IN=

IN>

|Q4 |03 |®2
VCC = PIN
OND:= PIN

16
@8

TRUTH TABLE

COMPARING

CASCADING

INPUTS

A3,B3

INPUTS

A2, B2

A1,B1

A0, BO

A3> B3

A3 <B3

A3=B3

A2>82

A3=B3

IN >

IN <

A2 < B2

A2 =82

Al1>B1

A3=B3 | A2%B2 | A1<B1 | X
A3=8B3
A2 =82
A1l=81
A0 > B0

OUTPUTS
IN=]

A>B

A<B

A=B

X
X

L
H

H
L

L
L
L

A3=B3

A2 =82

Al1=81

A0 < BO

A3 =B3

A2=B2

Al1=81

A0=B0

A3=8B3

A2=8B2

At =B1

A0=80

A3=B3

A2=B2

A1l1=B1

A0=80

NOTE:

H = high level, L = low level, X = irrelevant
1C-7485

D-4

8598 READ-ONLY MEMORY

The 8598 is a 256-bit, read-only memory organized as 32 words of eight bits each. Addressing is
accomplished in straight 5-bit binary with full decoding. An overriding memory enable input is provided which, when taken high, will inhibit the 32 address gates and cause all eight outputs to remain high.

10
A0 o..(._.)_.
{11)

A1 O—
(12)

BINARY fi A2 O——|

SELECT

1 0F 32

32-WORD BY 8 BIT

DECODE

MEMORY CELL

(13)

A3 O—
LA4 o (14)

MEMORY°(15) ’
ENABLE

(7)

(6)

{5)

(4)

{3)

(2)

OUTPUTS

8598

M7 (1)

’

14 TM

M6 (1)

M5 (1)

12
1"

M4 (1)

M3 (1)

M2 (1)

3
2

M1 (1)

Mo (1)

p———

ENB

+5 V PIN 16

GND PIN 8
1C-8598

D-5

(9)
M7
)

74112 DUAL J-K FLIP-FLOP

PRESET

¢L4

CLOCK —Q
2

73112
|

ol®

T15
CLEAR

PRESET

‘LiO
1
1

cLock 3Bd

9
W

74112
7

—<1k

o—

74112 Truth Table

th
J

theq
K

Pin5or 9

Complement

No change

t,, = Bit time before clock pulse.
th+1 = Bit time after clock pulse.
IC-74112

D-6

74151 8 TO 1 MULTIPLEXER

74151 TRUTH TABLE
Outputs

Inputs

80 | STB

When used to indicate an input, X = irrelevant.

STB

74151

6
fop—

|10

|11
IC-74151

74153 DUAL 4 TO 1 MULTIPLEXER

ADDRESS

INPUTS

DATA INPUTS

STROBE

OUTPUT

STB

Address inputs 50 and S1 are common to both sections.
H = high lavel, . = low level, X = irrelevant.

-—-—-——03 DO

———13 DI

04
—co

fO
05

— ¢

74153

74153
B1

—— AQ
S1

[02

|14

STBO

TO1

0 Al
S1

"VCC= PIN16
GND:= PINOS8

IOZ

|14

ST B1

T15
IC-74153

74154 4-LINE TO 16-LINE DECODER

AsAAAsaan T:: Ima s

The 74154 4-Line to 16-Line Decoder decodes four binary-coded inputs into one of 16 mutuallyexclusive outputs when both strobe inputs (G1 and G2) are low. The decoding function is performed
by using the four input lines to address the output line, passing data from one of the strobe inputs with
the other strobe input low. When either strobe input is high, all outputs are high.

fiq

f13

f12

74154

—

BCD

INPUT

|—— D2
22

FOR DECODING | — D1

16 OUTPUTS
1 OF 16 MUTUALLY
EXCLUSIVE OUTPUTS
DECODED FROM BCD INPUT
WHEN BOTH STB1 AND
STBO ARE LOW

—1 DO

)

f10

STBO

T19

T18
Notes For Demultiplexing:

+5V
= PIN 24
GND:=PIN 12

Inputs used to address output line.
Data passed from one strobe input

with other strobe held low. Either
strobe high gives all high outputs.
1C-74154

D-9

STROBE
16

(2)

DATA (1) |>
1€

(7) ouTpPUT

1y
I

¥%% ¥¥>¢

74155 3-LINE TO 8-LINE DECODER

1YQ

(6) OUTPUT
1Yd

{5) ouTPUT

SELECT (3) |>
B

{(4) ouTPUT
1Y3

(9} ourPuT

SELECT

——4 :x>—~—-—44 >>———-—
(13)

2Y0

1 O} ouTPUT
2Y1

DATA
2¢

(15)

srggae 14)

{1 1) ouTPUT

—'O-j

r-fi___,/

2Y2

,12) oyTPUT
2v3

1C- 7455

74157 QUAD 2 TO 1 MULTIPLEXER

INPUTS

OUTPUT

S0 | A

STB!

H = high level, L = low level, X = irrelevant,

06 _1g

74157

far—

A2
STB

11107

S T8

told

VCC:=PIN 16

GND:=PIN 08

01
I1C-74157

D-11

74158 QUAD 2 TO 1 MULTIPLEXER

INPUTS

'STB | S0 | A

OUTPUT

L
H

H = high level, L = low level, X = irrelevant

—

1% a3

132

74158

19 182

09
f2jo—

AT
PN

STB

T15

STB

’01

e Te

T15

‘01

VCC=PIN 16
GND=PINOSB

IC-74158

D-12

SYNCHRONOUS 4-BIT COUNTER
3

14
RO(1)—

2 1o

INPUTS) 8 12

rat 2

DATA

OUTPUTS

1
R3(1)p—

1
CLEAR ———0ICLR

74161

9
LOAD ——O LD

cLock —2J cLk
ENABLE P

—

CNT EN

ENABLET
15
col3.
CARRY

CRY EN

OUTPUT

GND = PIN 8

+5V=PIN 16

typical clear, preset, count, and inhibit sequences

for 74161

IHlustrated below is the foflowing sequence:

1. Ciear outputs to zero.
2. Preset to BCD seven.

3. Count to eight, nine, zero, one, two, and three.
4.

Inhibit

CLEAR

PINO1

{ASYNCHRONOUS)

ENABLE
P

PINO7

CLEAR

—

A
=]

|2}

[EPIGSE

CARRY
PiIN15

—

R3(1)
LPING

PINIZ

R2(1)
—TM —

PING3

R (1)
OUTPUTS

e B

RO(1)
PIN14

PR,

PIN1O

1]N

ENABLE
T

PINO2

CLOCK

D3
PINO6

NENENNN

PINOS

INPUTS

D1
PINO4

DATA

DO
PINO3

[

LOAD

____J._Jl_JE

L L L

74161

INHIBIT

PRESET
IC-74181

D-13

74174 HEX D FLIP-FLOP REGISTER

po o)
TRUTH TABLET
INPUT
'n

————Cf CLOCK
CLEAR

[QUTPU

fn01

R(1)

@sro(1)

D1 o—

——-—0(5) R1 (1)

th = Bit time before

clock pulse,

-QJCLOCK

th+1=Bit time after
clock pulse.

CLEAR

0——-5
p2 o8

LTy ra(1)
-QICLOCK
CLEAR

—1D5

— D4
11
6

-—D2
4

—~—

R3(1)
74174

(1)

[

(10)

—oR3(1)

D3 o-

R4 (1)

~——D3

q}______f?

RS5(1V)

R2(V ) fp—
R (V) p——

3
— DO

2
RO(Y)}—

CLEAR

o——j

—Qf CLOCK

D4 <:(13)

{12) R4 (1)

—QJCLOCK

CLR

CLK

CLEAR

(14)

(15

D5 o—
cLock ot
|’:‘7

CLEAR 0)

-—0) RS (1)
CLOCK

CLEAR

>———T

Pin (16)= V¢, Pin (8)= GND
IC-74174

D-14

74175

QUAD STORAGE REGISTER

TRUTH TABLE

|OUTPUTS

INPUT
'n

'n'1

|R(1IR(O)

L
H

H
L

th2Bit time before
clock puise.
th+i=Bit time ofter
clock pulse.

Blos

r3m i}
14

R3(0) }—

DATA

‘NPUTSfi

R2(\WY—

l D2

74175

|—{po

R2(0) F

rRoOL (2)
[»]0] (1 )—--O

(4)

, gourpurs

R1(1) —
R1(0) -2~
2

RO(|—

0108
o

RO(O) 2 |

CLR

CLK

ril (M

)

——o0

R1]

(6)

CLK (o)f—>°

CLEAR

.
¢

D2 o2

(10)

bz FaF—o
rR2|

(1)

—QICLK (oj}—o

CLEAR

LT
(9
cLoc K H

r-fl__/

(15)

3 412

03 F31EL

(14)
-QICLK R3]
(0)—°
CLEAR

M
_j
CLEAR r»—(i>0—-l——‘——<L——Pin{16)= V¢, Pin (8)=GND

IC-74175

D-15

74181 4-BIT ARITHMETIC LOGIC UNIT, ACTIVE HIGH DATA
The 74181 performs up to 16 arithmetic and 16 logic functions. Arithmetic operations are selected by
four function-select lines (SO, S1, S2, and S3) with a low-level voltage at the mode control input (M),
and a low-level carry input. Logical operations are selected by the same four function-select lines
except that the mode control input (M) must be high to disable the carry input.

74181

TABLE OF LOGIC FUNCTIONS
Function Select

COMPARATOR

CARRY

Ss2

Negative Logic

Positive Logic

f =A

f=A

L
L

H
H

f=A+B

f = Logical 1

f = Logical 0

f=B

L
L

L | f=AB
H|
{=A®B

L
L

f =AB

H
H

GE%I:ERRRAYTE

Output Function

OUTPUTS
~

L | ¢t=A+8B
L

f =AB

f=A+B

L
H

f = Logical 0

f =AB

f=A

f=A+B
f =A®B
f=8

WORD

f=AB

INPUTS

f = Logical 1

f=AB

f=A®B
f =AB

f=A+B

COuUT

PROPAGATE

(—— B3

f=B

L | f=B

lus

A=B

f =AB

f =A®B
f=A+B

CARRY

£3 —)

29 Ig
21

— A2
2

74181

L Y
23

f=A+8B

—

f=A

f0H—

_L— AO

For positive logic: logical 1 = high voltage

OUTFPUTS

f1 —

=80
02

With mode control (M) high: C;, irrelevant

> FUNCTION

logical O = low voltage

For negative logic:

logical 1 = low voltage

O = high voltage
logical

|04

|05

CIN

SO
|06

|08

|07

MODEARRY
INPUT

——

VCC=PIN 24

GND =PIN 12

FUNCTION

SELECT
INPUTS
IC- 74181

74181,
TABLE OF ARITHMETIC OPERATIONS
Function Select

Output Function

f= A minus 1

f=A

f = AB minus 1

f=A+B

Low Levels Active

High Levels Active

f = AB minus 1

f = minus 1 (2's complement)

f=
A plus [A + B]

f = A plus AB

= [A +B] plus AB

f = AB plus (A + B]

f = A minus B minus 1

f = AB minus 1

f=A+B

f = A plus [A
+ B}

f = A plus AB

f=AplusB

f=A plusB

f = AB plus [A + B]

t = [A + B] plus AB

f=A+B

f = AB minus 1

f=A plus At

f=AB plus A

f=[A+8B] plusA

f=AB plus A

f=[A+8B] plus
A

f=A

f=A minus 1

With mode control (M) and C;, low
1 Each bit is shifted to the next more significant position.
”~

D-16

74182 LOOK-AHEAD CARRY GENERATOR

The 74182 Look-Ahead Carry Generator, when used with the 74181 ALU, provides carry look-ahead
capability for up to n-bit words. Each 74182 generates the look-ahead (anticipated carry) across a
group of four ALUs and, in addition, other carry look-ahead circuits may be employed to anticipate
carry across sections of four look-ahead packages up to n-bits.

Carry inputs and outputs of the 74181 ALU are in their true form, and the carry propagate (POUT)
and carry generate (GOUT) are in negated form.

PIN DESIGNATIONS

Pin No.

Function

G0, G1,G2,G3
PO, P1,P2,P3

3,1,14,5
4,2,15,6

ACTIVE-LOW CARRY GENERATE INPUTS
ACTIVE-LOW CARRY PROPAGATE INPUTS

GOUT
POUT

10
7

GND

Designation

CIN
COUTX, COUTY,COUTZ
Vee

13
12,11,9

CARRY INPUT
CARRY QUTPUTS

SUPPLY VOLTAGE

ACTIVE-LOW CARRY GENERATE OUTPUT
ACTIVE-LOW CARRY PROPAGATE OUTPUT
GROUND

lo7

Loe

GOULT

POUT

COouTZ

74182

COUTX

couTY

G1
o1
VCC=
GND=

74182

—OQ CIN

74182

GO
03

PO
04

PIN 16
PIN O8
IC~-74182

74187 1023-BIT READ-ONLY MEMORY

1024

BIT MEMORY CELL

(A7—————>
(15)

A6 —p
()
1

A5 —————9{
(2)

DECODER

MEMORY

MATRIX

A4 ———p
(3)
BINARY

SELECT

A3—4———u
{4)

(17

Al
(6)
AO

DECODER

—»

DECODER

L—q

;
MEMORY

ENB1 )

a®

ENABLE

ENB2

a__/

(13)

DECODER

(5)

i
-

. 8
OF

1
DE

CODER

(9)

(10)

11)

-V

(12)

OUTPUTS

15 14
01

74187

—
0

M3(1) b—22—

M2 (1) jo———o
a4

.
M1(1)

—92 140

p—1———

Mo(1) jo—2&—

ENBI

ENBO

VCC =PIN

16
GND
= PIN 08
IC-74187

74191

4-BIT UP/DOWN COUNTER

The 74191 is a 4-bit binary counter that counts in BCD or binary and can operate as an up or down
counter. The counter can be preset by the load control and uses a rippled clock output for cascading.

DOWN/UP

ENABLE

LOAD

MODE

Parallel Load

No Change

Count Up

Count Down

H= high level

L =low level

X=irrelevant

NOTE 1
12

NOTE 2
I

RCLK

MAX/MIN

(29 1ps

DATA

12 1o

INPUTS |

r3 (12 )

74191

r2 (12
02

LA 0

R1 (WP

(EREN P

rRo (23

DN/UP CLK

$ OUTPUTS

ENB

Trn 'os 114 Tem

VCC= PIN 16
GND= PIN 08
NOTES

1. MAX/ MIN produces a high level output pulse
when the counter overflows or underflows.

2.Ripple clock produces a low level output pulse

when an overflow or underflow condition exists.
1IC-74i91A

D-19

74193

4-BIT UP/DOWN COUNTER
The 74193 binary counter has an individual asynchronous preset to each flip-flop, a fully independent
clear input, internal cascading circuitry, and provides synchronous counting operations.

typical cleor, load,and count sequences for

74193

lllustrated below is the following sequence

1. Clear outputs to zero.

Load (preset) to BCD thirteen.

3. Count up to fourteen, fifteen, carry, zero, one, and two.
4.

Count down to one, zero, borrow, fifteen, fourteen, and thirteen.

SEE
NOTE

|13

CRY

BRW

l l
09

DATA

—

INPUTS Y 4

R3(1} |—

74193

R1(1) p—

RO ) o~

[

PIN 01

PIN Q5

CouNT

SEE SEE ‘“—~—'
5

PING4

UOUNT

(oin o3

SEE

NOTE

PINOZ

1. Clear overrides load, data, and count inputs.
2.

ROt

CLR input high forces all cutputs low.

||__________________________._

—_— e = — e — — — e — e — — — ——— =

[

: !

: :

Select DN or UP clock while other is held high.

|LML

'
|

! B!

R3 (1)

s Y

[

l
l

—

|
|

HORROA

Preset to any state by applying input data with
independent of count pulses.

PIN 13

PINOE R2 (1) —_ j___l_____I
PINO7

PIN 12 CARRY

load input low. Output changes to agree with inputs

[

CLR

overrides toad, data and DN/UP inputs.

Underflow (BORROW)

Overflow (CARRY}
4.

[

_I_——_—‘__——___—__——-—___—_"

RI (1)

Produce pulses equal to width of count pulses
during:

DowN

When counting up, count down input must be high;

when counting down, count-up input must be high.
3.

[

“OUY

OUTPUTS

NOTES:

LD CUP CDN

NOTE NOTE

[

PINO9

lm Tn los loa

PIN1i 1L0AD
PIN IS

[

—{ oo

PIN 10

o2 ) OUTPUTS

- 0t

CLR

DATA

R2(1) —

{

r
07

-—1D3

PIN 14 CLEAR

SEQUENCE
{LLUSTRATED

=
CLEAR

CCUNT uP

COUNT DOWN —

PRESET

D-20

7419}

74194 4-BIT SHIFT REGISTER

The 74194 is a parallel load, parallel output, shift register with left shift and right shift capability.
Clocking is accomplished by positive-edge triggering. In addition, the IC contains an inhibit function
and direct overriding clear input.

MODE

CONTROL

SHIFT RIGHT

SERIAL INPUT

—N
I1O

S1
~

INPUTS

)

S®

‘02

DSR

RO (1)

2% 1o,

PARALLEL

\09

74194

15 )

R1(1p—12

R2 (1)

lps

R3 (1)

vCC=PIN 16

GND
= PIN

CLK

OUTPUTS

|—12

CLR

\ PARALLEL

DSL

To i o

SHIFT LEFT

SERIAL

INPUT

MODE CONTROL
S1

PARALLEL LOAD

SHIFT RIGHT (IN THE DIRECTION RO TOWARD R3)

SHIFT LEFT (IN THE DIRECTION R3 TOWARD RO}

INHIBIT CLOCK (DO NOTHING)

L
IC-74194

D-21

APPENDIX E

PREVENTIVE MAINTENANCE SCHEDULE

Device
CR11/CR04

DL11-A
FP11-B

Period* | Time®* | Weekly
40 hr

15 min

—

Semi-

Monthly | Quarterly | Annually

—

1 hr

2 hr

1.5 hr

15 min

—

15 min

2.5 hr

Annually
—

—

20 min

—

3hr

—

KB11-B,C

—

KW11-L

—

20 min

25 min

30 min

LA36

—

3 hr, 10 min
—

MJ11

LPO5

LP11 (ALL)
LPS11

—

LV11/LVO0l

—

PCO5

—

RH70

RKO5
RP04
RP11C/RPO3
RS03/04

TU10

TU16

TUS6

—

—
—
—
—

8 hr
—

—

30 min

—

1.5 hr

4 hr

3hr

—

1 hr

—

2 hr

—

15 min

—

1 hr

3hr

—

35 min

1.75 hr

—

1.75 hr
1.5 hr
1.5 hr

2.75 hr
3 hr
3 hr

3.75 hr
3.5hr
3 hr, 10 min

1.5 hr

2.5 hr

—

1 hr

2 hr

—

—
—
—
—

15 min
—

—

5 min
—

—
—
—

10 min
—
10 min

—

15 min

1.5hr

20 min

1 hr

30 min

—

30 min

—

2.75 hr

4 hr

2 hr

3.5hr

—

* NOTE: These two columns show the maintenance required at odd intervals, e.g., 15 min of PM every 8 hrs on the TU10.

E-1

APPENDIX F
SUMMARY OF EQUIPMENT SPECIFICATIONS

This table provides mechanical, environmental, and pro-

Cabinet

gramming information for the PDP-11/70 optional equip-

magnetic

ment. The equipment is arranged in alphanumeric order

cations.

and

peripheral

tape)

are

equipment

included

(such

the

specifi-

by Model Number.
3.

Relative humidity specifications mean without

condensation.
NOTES
4.

Mounting Codes

CAB

C(Cabinet

Equipment that can supply current is indicated

by parentheses ( ) around the number of amps

in the POWER section.
mounted.

cabinet

included with the option, it is indicated by an

Non-Processor Request Devices are indicated by
an X in the “NPR” column.

X in the “Cab InclTM column.

FS = Free standing unit. Height X Width X

MIJ11 Memory specifications are stated in
Chapter 2 of this manual.

Depth dimensions are shown in inches.

TT = Table top unit.
PAN = Panel mounted. Front panel height is

CONVERSION FACTORS

shown in inches. An included cabinet is indi-

cated when applicable.

(inches)

X 2.54

(cm)

(Ibs)

X 0454

(kg

X 341

(Btu/hr)

(Watts)

SU = System Unit. SU mounting assembly is

[(CC)X3] +32

included with the option.
SPC = Small Peripheral Controller. Option is a
module that mounts in a quad module, SPC -

slot.

MOD = Module. Height is single, double, or

quad.

( ) = Option mounts in the same space as the
equipment shown within the parentheses.
Some options include 2 separate physical parts
and are indicated by use of a plus (+} sign.

F-1

)

= (°F)

MECHANICAL

Model
Number
AAl11-D
ADO1-D
AFCl11
AR11-K

BAiI-K

Description
D/A Subsystem

A/D Subsystem
A/D Subsystem
A/D Subsystem

Mounting Box

Mounting
Code
Su

PAN
CAB
SPC + PAN

PAN

Size
HXx WXx D
(inches)

Cab
Incl

S5V

ENVIRONMENTAL

Weight
(Ibs)
15

10%

POWER

Power Harness
BA11-K | H960-D

Oper
Rel
Temp | Humid

Cur needed/ (supplied)
115 Vac / other
{+5V

(%)

7009562 7009562

10-50

§{20-95

0-55 § 10-95
iG--55 § i6-85

(amps)

100

0.5

PROGRAMMING

Power
Dis

Int
Vector

BR
Level

17 776 756

140,144

4,5

NPR

Bus
Loads

Model
Number

0.5
is

60
1746

12a115V

1380

10A @ -15V

UNIBUS

1st Reg
Address

17776 770
17772576

130
i34

4-7
4

AAl1l-D

1
H

ADO1-D
AFCE!
AR11-K

BA11-K

I1A@-5V

50A @+5V

8A @ +20V
4A @ +15V

BA614
BB!!
BB11-A

D/A Converter
Blank Mntg Panel
Blank Mounting

(AA11-D)
SU
SuU

BA614
BB11
BB11-A

2SU

BB11-B

Panel (non-slotted
blocks)

BBI11-B

Blank double
Mounting Panel,

BC11-A
BM792-Y

99X 6

Unibus Cable
Bootstrap Loader

SPC

CB11

Telephone Switching | Cab

CD11-A/B
CDII-E

Card Reader
Card Reader

SU+TT
SU+TT

CR11

Card Reader

SPC+TT

CM11-F

CTS-11

DALll-B
DAIlIL-F
DBil-A

DCI11-A
DDI11-B
DECKkit 01-A

DECkit 11-F

Interface

Card Reader
Card Reader/Punch
Unibus Link
Unibus Window
Bus Repeater

SPC+TT
SU +FS

SU
SU
Su

Asynch Line Inter
SU
Periph Mntg Panel
SuU
Remote Analog Data | PAN

Concentrator: §
Channels, Serial

I/O Interface: 3

X
14 X 24 X 18
38 X 24 x 38

11 x 19%x 14
11X 19%x 14

38 X 48X 27

5% X 19x 13

10-50 | 10-90

300
85
200

60
60

300

7010117 7009562
7010117 7009562

7009562 |7009562

7009562 7009562
7010117 7009563
7009562 7009562

7010117 7009562
7010117 [7009563

10-50 |} 10-90
10-50 | 10-90

10-50 | 10-90
10-50 | 10-90

5-43

8-90

10-50 | 10-90
5-506 § 16-95

0.3

BCl1-A
BM792-Y

1,2

CB1l

1
1

CDI11-A
CDl11-E

CR11

5.6

650

17 764 000

float

4-17

|2.5
|2.5

4
6

450
700

17 772 460
17 772 460

230
230

4
4

|[1.5

400

17 777 160

230

17 772 410
17 764 000

124
float

5
7

17 774 000

float

DC11-A
DDI11-A
DECKit 01-A

|1.5

(4.0

400

4
IS5
;3.2

10-50 | 20-90

sce Product Bull.
1.5@ 115 Vac

0-50 | 10-95

17 777 160
17 777 160

230

X
X

CMI11-F
CTS-11

1
DA1l-B
1
DAI1l-F
1+1 | DRIl

175

0.75 @ 230 Vac

7009562

0-70 | 10-95

|1.84

User

DECkit 11-F

7009562

0-70 | 10-95

|3.91

User

5-6

DECKit 11-H

SuU

7009562

0-70 | 10-95

{1.97

User

DECKkit 11-K

7009562

0-70 | 10-95

|1.75

User

DECKkit 11-M

Words In/]1 Word

Qut

DECkit 11-H

[/O Interface: 4

Words In/4 Words

DECkit 11-K

Out

I/O Interface:
8 Words In

DECkit 11-M

I/O Interface:

DFO01-A

Acoustic Coupler

DHIl

Asynch Line MX

2SU

DFi1

DH11-AD

User

Instrumentation

Interface

Line Sig Cond

Asynch 6 Line MX

F-2

DF slot

2SU

6X 7% 12

7010118 7009561
7010118

5—-45 | 10—-95

10-40

DFO01-A

0.3

0-60

|8.4

10.8

see Product Bull.

0.24A@-15V

04A@+15V

065A@-15V

float

DF11

DHI11

DH11-AD

MECHANICAL

Model
Number

Size

Cab

Weight

Code

HXWXD

Incl

(Ibs)

Description

(inches)
DH11-AE

Asynch 6 Line MX

ENVIRONMENTAL

Mounting

Power Harness
BA11-K

|H960-D

Oper

Rel

Temp

|Humid

2SU

7010118

POWER

Cur needed/ (supplied)
[+5V

|®

10-40

115 Vac / other

(amps)
8.6

PROGRAMMING

Power | 1st Reg
Dis

Address

0.IA@+]1S5V

UNIBUS

Int

Vector

Level

float

Bus

Model

NPR

Loads

Number

DH11-AE

0.34A@-15V

DJ11-A

Asynch Line MX

SuU

DLI11-A

Terminal Control

SPC

DLI11 (others) | Asynch Line Inter
DM11-BB

Modem Ctr. MUX

DN11-A

Auto Calling Unit

7009562 | 7009562

7010117

(7009563

see Product Bull.

float

DI11

DL11-A

17 776 500

float

DL11 (others)

17 775 000

float

0.15A@-15V

SPC

17 777 560

1.8

0.15A@-15V

(DHI11)

2.8
0-40 | 20-90

060,064

1.8

|14

0.10A@+15V

17 775 200

float

DM11-BB

DN11

DP11

Synch Line Inter

7009562

|7009562

0-40 | 20-90

|25

0.100A@ +15V

DQI11

DMA Sync Line

17 774 400

float

DP11

7010117 | 7009563

10-50 | 10-90

{5.7

0.04A@+]15V

float

DQ11

DRI11-B

DMA Interface

7009562 [ 7009562

10-50 | 20-90 | 3.3

DR11-C

General Interface

17772 410

SPC

124

DR11-B

10-50 | 20--90 | 1.5

17 767 770

float

DR11C

Iser

User

DR11-L

Interface

0.07TA@-15V

DR11-K

General Interface

DR11-L

Unibus 2-Word In

SPC

5-50 | 10-95

1.5

User

DR11-M

Unibus 2-Word Qut

SPC

5-50 | 10-95

|[1.5

DTO3-F

Unibus Switch

User

PAN

DU11

Sync Line Inter

SPC

DR11-K

2
10-50 | 20-95

|2.2

07A@+15V

User

DR11-M

User

1+1

DTO3-F

float

DU11

float

DVI11l+

4-7

DX11-B

GT40

0.17A@-15V
DV11+

Sync MUX

2SU

7010835

10-40 | 10-90

|15

05A@+]15V

2DVI1I1-BA
DX11

IBM Chan. Interface

| CAB

GT40

Graphics Terminal

H312-A

Null Modem

H720-E

Power Supply

H722

Transformer

(PC11-A)

Power Supply

(H960-D)

H744

+5 V Regulator

(H742)

H745

-15V Regulatbr

(H742)

H754

+20, -5 V Regulator | (H742)

Mounting Panel

18 X 20x 24

2DV11-BA

180

10-55 | 10-90

2.5

300

| 17 776 200

float

150

15-35 | 20-80

1500

float

0-50 | 20-95

6 (100A)@-15V

700

H312-A

(BA11)

H742

H933-C

1.0OA@-15V

|(22)

H720

1.5A @230 Vac

H722

B(1A)@+15V

H742

(100A)@ -15V

H745

(8A) @ +20V

H754

(25)

H744

(l1A)y@ -5V

H933C

(H803 blocks)

H933-CB

Mounting Panel

SuU

H933-CB

(slotted blocks)

H933-D

Mounting Panel

H933-D

(H808 blocks)

H934-CB

Double Mounting

2SU

H934-CB

Panel (slotted

blocks)

H960-C

Cabinet

72X 21 x 30

120

H960-D

Cab (1 drawer)

72 x 21 x 30

300

7009566

(75)

8(20A)@-15V

900

H960-C

H960-D

H960-E

Cab (2 drawers)

72 x 21X 30

470

7009566

(150)

16 (40A) @-15V | 1800

H960-E

H961-A

Cab w/o side pan

72X 21X 30

120

KG11-A

Comm Arith Unit

SPC

KW11-L

Line Clock

MOD

KWI11-P

Programmable Clock | SPC

1.5
single ht

17770 700

H961-A
KGI11-A

0.8

17 777 546

100

KWI11-L

17 772 540

104

KWI11-P

F-3

MECHANICAL

Cab | Weight
Incl (Ibs)

Power Harness
BA11-K | H960-D

ENVIRONMENTAL

Oper
Temp

Rel
|[Humid

POWER

Cur needed / (supplied)
115 Vac[ other
[+5V

[Power
Dis

300

PROGRAMMING

Ist Reg
Address

Int
Vector

BR
Level

17 777 560
17 777 514
17 777 514
17 777 514

060,064
200
200
200

4
4
4
4

17777 514

200

UNIBUS

Bus
Loads

Model
Number

Description

Mounting
Code

Size
HXxWxD

LA36
LCI1-A
IP1L.F
LP11-J
LP11-R
LPS11
LS11
LT33
LVI11
M10S
M783
M784
M785
M792
M795
M796
M920
M9302
M1501
M1502
Ml1621

DECwriter
LA30 Control
Printer (80 col)
Printer (132 col)
Ptr (Heavy duty)
Lab Periph System
Line Printer
Teletype
Electrostatic Ptr
Adrs Select Module
Bus Transmitter
Bus Receiver
Bus Transceiver
Diode ROM
Word Count
Bus Control
Bus Jumper
Bus Terminator
Bus Input Interface
Bus Output Inter
DVM Data Input

FS
SPC
SPC + FS
SPC + FS
SPC + FS
PAN
SPC+TT
FS
SPC + FS
MOD
MOD
MOD
MOD
SPC
MOD
MOD
MOD
MOD
MOD
MOD
MOD

33.5x 27.5% 24

102

10-40 | 10-90

46 X 24 x 22
46 X 48 x 25
48 x 49 x 36
5%
12x 28x 20
34 x 22x 19

200
575
800
80
155
60

10-43 | 15-80
10-43 | 15-80
10-43 | 15-80
5-43 | 20-80
5-90
5-38
15-35 | 20-80

single ht
double ht
double ht
single ht
double ht
quad ht

0-70 | 10-95
0-70 | 10-95
0-70 | 10-95

1.25
|03
10.75
|0.78

LA36
LC11-A
LP11-F
LPii-J
LP11-R
LPS11S
LS11
LT33
Lv1l
M105
M783
M784
M785
M792
M795
M796
M920
M9302
M1501
M1502
M1621

M1623

Instrument Remote

MOD

quad ht

0-70 | 10-95

|[1.6

M1623

MOD &

quad ht

0-70 { 10-95

{0.79

16-Bit Relay Qutput | MOD

quad ht

0-70 | 10-95

|[1.46

MOD

single ht

M1710

M1801
M7821

Interface

Control Interface

Unibus Interface
Foundation
Interface

Interrupt Control

SPC

(inches)

PCiI
PDM70

Paper Tape
Programmable Data

SPC + PAN
TT

10%2
5% X 19X 23

PRI11
RC11-A
RF11-A

Paper Tape (rdr)
Disk & Control
Disk & Control

SPC + PAN
PAN
PAN + PAN

102
10v
16 + 16

RKOS

RK11-D
RP0O3
RP11C
RSI11
RS64
RTO1

Mover

Disk Drive

PAN

SU + PAN
Disk & Control
FS
Disk Drive
CAB + FS
Disk & Control
PAN
Disk Drive
PAN
Disk
Numeric Data Entry | TT

Terminal

RWPO4

Alphanumeric Data
Entry Terminal
Disk Drive and

RWS03

Disk Drive &

PAN

RTO2

Massbus Control

- 10%

10%
40 X 30 x 24

16
10%
6.5 12.5% 15

6.3x 144X 16
40X 31 x 32
16

10-43 | 20-80

160

38x 19x 18
single ht
single ht
single ht
single ht
quad ht
double ht

O |»

1.5
|1.5
|1.5
|1.5
|1.5
|{1.5
0.34
0.2
0.2
0.3
0.23
0.6
0.13

0.55

118

50
55

13 38 0 20.95
0-40 | 10-95
13-38 | 20-95
17-50 | 20-80
17-33 | 20-55

|1.5

50
115
500

15-43 | 20-80
15-33 | 10-80
15-33 | 10-80
17-33 | 20--55
17-50 | 20-80
0-40 | 10-90

{7.5

110

250
415
740
100
65
12

600
110

70101151 7009562

15-43 | 20-80

(amps)

2
4
17

250
500
2000

3
2
5

300
200
600

300

fioat

17777514

floai
200

NPR

opt

1
1
i
1

2
1
1

17 773 000

M1710

opt

M1801

PCl11
PDM70

X
X

1
1
1

PR11
RC11-A
RF11-A

RK11-D
RPO3
RP11<C
RS11
RS64
RTO1

17 777 550

070,074

350
250
750

17 777 550
17 777 440
17 777 460

070
210
204

4
5
5

200
6 A @ 230Vac | 1300
7 6A@230Vac | 2100
200
2
250
2.2
0.25 @115 Vac 30

17 777 400

220

17776 710

254

3
2.2
6.5

115 Vac

230 Vac

160

2
2

0.12@ 220 Vac

110 Vac

0-40 | 10-90
15-32 | 20-80

220 Vac

250

RKO05

RTO02

50
50

M7821

350
250

3 phase Y or.A | 2100

17 776 000

254

(MB)

RWP04

700

17 772 040

204

(MB)

RWS03

MECHANICAL
Model
Number

Mounting

Size

Code

HXWXD

Description

ENVIRONMENTAL

Cab | Weight
Ind

(bs)

(inches)
RWS04

Disk Drive &

PAN

Power Harness
BA11-K | H960-D

Oper

POWER

Rel

Temp | Humid

Cur needed / (supplied)
[+5V

120 -

UNIBUS

1st Reg

Int

Bus

Model

115 Vac / other

Dis

Address

Vector

Level

NPR

Loads

Number

(amps)

w)
(MB)

RWS04

RX11

- CO | @B

PROGRAMMING
| Power

700

17 772 040

204

400

17 177 170

264

Massbus Control
RX11

Floppy Disk &

SPC + PAN

104X 19X 17

15-32

| 20-80

(1.5

|1.5

Control

TAll

Cassette

SPC + PAN

S5V

10-40

|20-80

120

17 777 500

260

TA1ll

TC11-G

DECtape & Control

PAN + PAN

10%2 + 10%

250

15-32

]20-80

870

17 777 340

214

TC11G

TU10 & Control

PAN + PAN

26 + 10%

500

15-32

| 20-80

1000

17 772 520

224

TMA-11

TMA-11-M

TS03 & Control

PAN + PAN

10% + 10%

100

15-32

| 20-80

200

17 772 520

224

TS03

Magtape Transport

PAN

102

15-32 | 20-80

100

TS03

TUIO0

Magtape Transport

PAN

450

15-32 | 20-80

1000

TU10

TU16

Magtape Transport

PAN

450

15-32

| 20-80

1000

TU16

TU45

Magtape Transport

PAN

450

15-32

120-80

TUS6

DECtape Transport

PAN

10%2

15-32

|20-80

350

TU70

Magtape Transport

PAN

500

15-32

[20-80

06A@-15V | 1000

PAN

450

15-32 [ 20-80

] TMA-11

TWU16

Magtape Transport

TMA-11-M

TU45

TUS6

17 772 440

224

(MB)

TWU16

& Massbus Control

TWU45

Magtape Transport

TWU4S

& Massbus Control

TWU70

Magtape Transport

TWU70

& Massbus Control

UDC11

I/O Subsystem

CAB

VRO!

Display

PAN

5-50

|]10-90

1700

10-50

[10-90

120

VRO1

VR14

Display

PAN

VTO1

Display

10%

10-50 [ 10-90

400

VR14

12x 12x 23

0-50

}10-80

2.2

250

VTOS

Alphanum Terminal

| TT

12X 19X 30

VTO1

10-43

8-90

130

VT20

Alphanum Terminal | TT

VTO0S

VTS50

Alphanum Terminal | TT

14 x 21 x 28

10-40

]10-90

110

VT52

Alphanum Terminal | TT

14 X 21 X 28

VTS0

10-40

|10-90

110

VTS52

10%

17771 774

234

4,6

VT20

VT55

XYl11

UDC11

VT5S

Plotter Control for

SPC

1.4

0.1A@-15V

17 772 554

120

XY11

17 772 554

120

XY311

Calcomp 563 &
565 Houston DP1
& DP10
XY311

3 Pen Plotter

SPC + FS

44 X 50 x 24

{Calcomp 936)

F-5

APPENDIX G

WIRE TROUGH SYSTEM

This appendix is included in this manual to acquai
nt service personnel with the wire trough cable
routing system. Some PDP-11/70s are alread
y cabled this way, and eventually, all will be.
The illustrations show part numbers as well as

cable folding procedures.

G.1
GENERAL
The trough system (Wire Cable Basket System

) provides an organized cable system that improv

the
appearance of the cabling and helps reduce
cable damage. With this system, cables
are routed in

channel baskets (troughs) along the edge of a

bay, thus eliminating the tangled clumps of cables

were previously inevitable (Figure G-1). This

system protects cables from inadvertent snaggi

that

servicing a box.

ng when

Figure G-6 illustrates a trough section and its
associated hardware. The trough iself is merely
a wire
basket. Trough sections come in three lengths:
1-bay, which is used for horizontal and vertical
applications,

and 2- and 3-bay, which are used strictly for
vertical applications extending up to the entire
height of a bay.

Figure G-2 illustrates a typical system applica

tion.

G.2
CALCULATION OF REQUIREMENTS (CABL
ES AND TROUGHS)
There are two cases in which troughs are used.
First, they are used in the initial factory assemb

ly of a

system. (Refer to Paragraphs G.2.1 and
G.2.2 for a design procedure and exampl

e.) Secondly wire

troughs are field-retrofitted in existing system
s for system enhancement. (Refer to Paragr
aph G.2.2 for
a general procedure for the location and install
ation of troughs.)

The following are basic rules for planning the

installation and placement of troughs. These
rules are
not intended to be absolute, but merely a guide
for planning.
1.

Always install troughs at the rear of the bays.
This makes it possible to install equipment in
box space and prevents zig-zag trough pattern
s.

For an unwired system, always plan to channel cables

system. This provides accessibility and causes

down to the bottom, back edge of the

minimum interference with boxes.

Allow enough extra cable in all boxes to remove

A horizontal trough section must be available for

cable connectors from modules.
each slide-mounted box.

7819 19

Figure G-1

Installed Wire Trough System

WIRE BASKET CLAMP

(7413983-0-0)

€D

T/SCREW,PHL,TRUSSHD#10—32 x .62

(9006074-3) NUT,SPD.
# 10-32
, (9007786
)

TROUGH, CABLE
SINGLE BAY *

(7011223-2)

*NOTE!

TROUGH, 2 BAY (7011223-1) AND TROUGH,
3 BAY (7011223-0) ARE USED ONLY FOR
VERTICAL CABLE SUPPORT.

UNIBUS

CABLE

CLIP 9009760

REF

11-4092

Figure G-2

PDP-11/70 with Cable Troughs

Determining Correct Cable Lengths

G.2.1

Thus, the accuracy of our calcuMost Unibus and I1/O cables come in lengths of 1 foot increments.
lations need not exceed £0.5 feet. Cable should be conserved to cut costs, but should not be conserved
at the expense of proper operation and safety.

cable length exceeds the limit, cable
The maximum Unibus cable length is approximately 50 feet. If the
rerouting should be considered. If this does not reduce it sufficiently, a bus repeater must be added.
Cable lengths can be determined as follows:

of box in its respective location
Set up a block diagram of the system and specify each type G-3a.)

List the desired cable connections (box-to-box; example: CU to BA11-F).

as seen from the back of the system. (See example, Figure

(slide-mounted), or an
In the upper-left corner of the box, place an r, signifying Removablebox,
signifying HorizonF, signifying Fixed. If Removable, also place an H or V within the d from
the side or from
tally or Vertically removable modules (i.e., modules that are remove
(step 5).
use
the top or bottom). This will assist in identifying the type of box for formula

run. (Bottom of
Draw a U-type line connecting the box bases to represent the desired cable
a color code of
Use
bays.)
of
U rests on bottom of bays or top of box occupying bottom
red: Unibus;
(i.e.,
system
your
in
your choice to define the different types of cables present
blue: round cables (line printer terminal); green: flat BCO8 type).

length by
For each cable connection (refer to the list made in step 2), calculate the proper
the systo
refer
right),
or
(left
n
directio
ion
using the formula shown below. Using destinat
(feet)
lengths
cable
the
lists
G-1
Table
values.
B
tem block diagram (Figure G-3a) for A and
box
the
imate
(approx
base
bay
the
at
exit
an
to
box
necessary to span from the rear of the
or
(right
exit
The
ation).
approxim
level
to
g
accordin
level and adjust L (total cable length)
do
values
These
G-4).
Figure
see
,
example
(for
n
directio
ion
left will depend on the destinat
not include service loop considerations.

NOTES

Total cable length, L, will be altered upon com-

pletion of trough planning.

2. Do not discard system block diagram as it will
be used for calculations of trough sections and locations.

f301 6.

, Figure G-3,
Examine the system block diagram for obvious cable routes. (In the exampleand
TMO02, or

cable need not run to the bottom of the cabinet in a connection of TU16 .
RKO5 and BA11-F.) Note this type of connection for future trough planning

. This has generated usage of
Certain options are usually connected and located in the same positionsTU16
to TMO2 require 6-foot
standard cable lengths. Cable connections from TU10 to TM11 and
lengths.

G-4

BLOCK DIAGRAM

N
2

TUl6

RKOS

R’/-/i/

TMO2

BAt1-F

7
MJ11

J
TU16é

TTMMO2

TM02

BAN-F

MJ11

BAM-F

L=5+6+0+25+25+0+0.5+0.5 =17 ft.

RKOS5

BAM11-F

BLOCK

DIAGRAM

L = 6t ( STANDARD LENGTH) (2 SERVICE LOOPS)
L=6+6+2+25+25+0.5+0.5+05 =20.5ft.

10+5+0+25+25+0+0.5+0.5 =21 ft.

TUlé

TROUGH

LOCATED

BETWEEN

RKO5

——p

TUi6 AND TMO2

TTMMO2

BAY1-F
7

CABLE LENGTH ALTERATIONS
TUl6

TMO2

L= 6ft.

TMO02

BAM-F

L= 20.5ft.

MJ11

BAM-F

L =17+2=19t.

RKO5

BA11-F

L =21 ft,
11-3651

Figure G-3

Example Problem

G-5

Table G-1

Option to Bay Base Cable Length
Cable Length from Rear of Box to Bay Exit
at Base

Level

Destination-Left

Destination-Right

21 in. High

1,2,&3

8.0

7.0

2.0ft

4,5,&6

4.0

BA11-K
MJ11
10.5 in. High
Max. Box Depth

2
3
4
5

7.0
6.0
50
4.0

7.0
6.0
5.0
4.0

BAl11-D,B
BA11-ES
10.5 in. High
Max. Box Depth

2
3
4
5

7.0
6.0
50
4.0

6.0
5.0
4.0
3.0

BAll-L
(PDP-11/04)
5.25 in. High
Max. Box Depth

2
3
4
5

7.0
6.0
50
4.0

6.0
5.0
4.0
3.0

PDP-11/05
5.25 in. High
Max. Box Depth
2.0 ft

2
3
4
5

7.0
6.0
5.0
4.0

6.0
50
4.0
3.0

BAl11I-M
(PDP-11/03)
3.50 in. High
Max. Box Depth

2
3
4
5

8.0
7.0
6.0
5.0

7.0
6.0
50
4.0

TC11
DECtape
Control

1
2
3

10.0
9.0
8.0

8.0
7.0
6.0

RF-11
Fixed Head

1&2
2&3

9.0
8.0

7.0
6.0

Option
BA11-F

Max. Box Depth

2.0 ft

15in.or 1.25 ft

Disk Control

Table G-1

Option to Bay Base Cable Length (Cont)
Cable Length from Rear of Box to Bay Exit
at Base

Option

Level

Destination-Left

Destination-Right

2&3

8.0

6.0

4
5

7.0
6.0

6.0
5.0

4
5

7.0
6.0

6.0
5.0

10.0

9.0

3
4
5

9.0
8.0
7.0

8.0
7.0
6.0

2&3
3&4
4&5

6.0
50
4.0

6.0
5.0
4.0

2
3
4
5

7.0
6.0
5.0
4.0

6.0

RP11

Disk Pack
Control
TTMI11

(TU10)
Max. Box Depth
1.5 ft
TTMO02

(TU16)
Max. Box Depth
1.5 ft

RK11
RKO05
10.5 in. High
Max. Box Depth
2.0 ft
RJS04

RS04
15.75 in. High
Max. Box Depth
2.0 ft
TAll

TU60
5.25 in. High
Max. Box Depth
1.5 ft

G-7

5.0
4.0
3.0

CABINET

BOX

BOX EXIT

CABLE LENGTH (A OR B)

/CABINET

EXIT

11-3660

Figure G-4

Destination Direction — Right

The formula for calculating cable length is as follows:
L

A+B+nC+
DA+ DB+ EA + EB
NOTE
0.5 is added to the total to prevent taut cables.

where L

= Total cable length (feet or meters)

= Cable length within starting unit bay (Table G-1)

= Cable length within the destination unit bay (Table G-1)

= Number of bays between cable termination bays

= 2 feet (bay width)

DA,DB

= 2.5 feet if box is slide-mounted or removable (R) for service loop

EA,EB

= Estimated value for length of cable needed to reach connecting module inside the
box

from the back of the box (see Table G-1 for the maximum box depth); add 0.5

feet if the box is slide-mounted and modules are horizontally removable (H).

G-8

In calculating the cable length needed to reach a peripheral device located outside the system bays, the

total, L, becomes LX (L exterior).

where P

A+DA+EA+P

= Length of cable needed from exit of bay to peripheral device.
NOTES

0.5 is added to the total to prevent taut cables.

2. Total cable length may change once trough location is determined. This is due to possible additional
cable needed to access a trough.

G.2.2

Determining Correct Trough Sections and Locations

To determine the correct trough sections and locations for a prewired system, follow the procedure
below.
1.

Examine the system from the rear and draw a sketch of the box locations including the cable
system layout.

Plan trough locations referring to basic rules (Paragraph G.2).
NOTE

It may be necessary to plan various new cable routes
and lengths.

Remove back doors to system wherever possible.

Examine the system and observe trough locations making plan alterations for obvious cable
conservation.
5.

Install troughs (Paragraph G.3.1).

Route cables in troughs individually using Unclamp-Reclamp method (Paragraph G.3.2).

If the system is an initial factory assembly, the cables are installed after the installation of all troughs is
completed.

As a general rule, cables should be run across the back bottom edge of the bays (unless occupied by a

box). One-bay horizontal trough sections are used to cross through a bay to another bay. A horizontal

trough section is also used when a service loop is required for a slide-mounted box. The trough provides fixed anchorage for the one end of the service loop. The trough for service loop anchorage is
usually planned for positioning on a level adjacent to the box.

Necessary trough sections and locations can be determined as follows:
1.

Draw a second system block diagram (Figure G-1b) and label the appropriate boxes with

the option designations.

G-9

Examine the first system block diagram (Figure G-1a) for required horizontal trough sections. Do not use 2- or 3-bay lengths when crossing the bays consecutively. This is physically

difficult to install. Indicate the necessary horizontal trough sections on the second system
block diagram.
3.

Examine the first block diagram for vertical trough section locations. Observe adjacent bays
to determine where vertical sections are required. Remember a vertical section need not

extend fully to a slide-mounted box. Draw the required vertical trough sections on the sec-

ond system block diagram. Leave as many box positions empty as possible in order to
provide for possible future box additions.
4.

G.3

Upon completion of trough planning, an alteration of cable lengths may be necessary. This
is because positioning the vertical troughs for maximum cable access may have caused a
more indirect cable route. Examine both diagrams and check each cable route for added
cabling to access a trough. If the cable must be routed in the opposite direction from its
destination, recalculate the corresponding A or B value for the opposite direction and add 2
feet. (This is done to allow for cabinet width.) Otherwise the total, L, remains unchanged.
The same holds for Lx.

INSTALLATION

Before beginning installation of troughs and/or cables, examine the physical system to confirm cor-

rectness of planning approximations. When the necessary corrections are satisfactorily done, continue
with the installation procedures.
NOTE
Care must be taken in trough positioning, to allow

clearance for the fans on the top and/or bottom of
the cabinet.

G.3.1

Installation of Troughs
Examine Figure G-6. Note the required parts and fastening hardware. Part numbers are included. The
only required tools are pliers and a Phillips screwdriver (offset if available).
G.3.1.1
Basket Bar Assembly (Retaining Bracket) - Once a trough location is selected, fasten the
retaining bracket to the bay frame. This retaining bracket may be connected on the inner or outer

edges of the cabinet. Note that these brackets are always installed horizontally from back to front and

act as a support for a horizontal and/or vertical trough. The connection to the cabinet is made at each
end of the bracket by means of a Phillips truss-head machine screw and self-retaining speed nut (Figure

G-6). If space restricts use of speed nuts, kep nuts can be used as replacements. Note the contact
surface of the bracket in Figure G-5.

A retaining bracket is installed to support each end of the trough. When connecting a vertical trough
section to a horizontal section, the adjoining bracket can act as a support for both,
(.3.1.2
Horizontal Troughs — After retaining brackets have been installed at each end of the desired
trough location, slide hooked ends of trough through bars of bracket. Both ends are positioned at the

same time (Figure G-7). Once the trough is in position, place clips on hooked ends (Figure G-2) with
pliers. This will secure the trough.

INCORRECT

CORRECT

11-3652

Retaining Bracket Contact Surface

/AN

Figure G-5

NOTE!

Troughs
1

can be obtained in three lengths|

bay

- 18.88in.

2 bay

-39.68in.

11-3653

3 bay -60.25in.

Figure G-6

Trough Assembly

G-11

TOP VIEW
STEP 1

STEP

2
H-3654

Figure G-7

Positioning Horizontal Trough Section

G.3.1.3
Vertical Troughs - A vertical trough is installed so that it correctly joins with
the horizontal
troughs and necessary retaining brackets. The second retaining bracket
for a vertical trough is positioned by temporarily holding the trough in its location. Once both brackets are
installed, the trough is
again positioned and fastened to the retaining bracket. This is done by
a nut and screw assembly
through the hooked ends of the trough and bars of the retaining bracket (Figure
G.3.2). The screw
heads should appear on the inside of the bay to allow removal of the trough
if necessary.
G.3.2

Installation of Cables
Examine Figure G-8. Note the way in which a cable enters and exits
a trough.

Each cable will be installed completely before installation of the next
cable. Begin at one cable end and
make the proper cable connections to the box. Observe all length considerat
ions before branching the
cable onto the first trough. (Refer to Paragraphs G.2.1.) Folding will be necessary
to keep cables flat
and obtain desired polarity at the destination. (Refer to Paragraph
G.3.2.1.) Apply clamps as the cable
is routed down a trough at approximately 6-inch intervals. For successiv
e cable routing through the
same trough, one end of each clamp is unclamped and then reclamped as
the cable is set in the trough.
This is repeated down the entire cable path for each cable addition and
is referred to as the UnclampReclamp method. Cable ties are also used to bundle cables in troughs.
Foam padding is required
between adjacent Unibus cables to prevent cross talk.

G.3.2.1
Folding - In order to branch on or off a trough with a flat cable, a bend,
fold, or number of
folds are necessary (Figure G-8). Figures G-9 and G-10 provide various folding
sequences to assist in
cable manipulation.
Excess cable due to miscalculation is folded in an overlapping sequence
and wrapped with a cable tie.
If possible, this folding is stored inside the box to preserve the appearan
ce of the system and may be
utilized as an internal service loop for removing modules. Excess
cable is necessary to provide an
internal service loop for horizontally removable modules (Figure G-11).
G.3.2.2
Service Loops - A service loop consists of an excess unbound bundle
of cables which allows a
slide-mounted box to be extended from the cabinet without detaching cables
(Figure G-12).
When a service loop is required, a horizontal trough is accessed within

one level of the box position.

This allows a fixed feedpoint for the cable. If a horizontal trough does
not exist in this proximity,
installation of one is required. Although it is usually located below the
box, it may be positioned above
the box. A service loop requires branching through (not over) the edge
of a trough (Figure G-8).

G-12

./& AN

NOTE CABLES BRANC I
THROUGH

TRO 2 G I

SIDES,NOT O > ER

BRANCHING

Figure G-8

Horizontal and Vertical Troughs with Cables

G-13

POLARITY

INDICATOR

LINE

e
~

K‘X* FAR SIDE
- o

CABLE

* —&

FOLD

A. Straight cable

B. Polarity on bottom

C. Polarity on top

11- 3656

Figure G-9

Cable Fold

POLARITY

[NDICATOR

LINE

SI-D

11-3657

Figure G-10

TU16 Cables: Cables Inverted and Red Stripe on Same Side

OVERLAPPING SEQUENCE

SIDE VIEW

Figure G-11

L FOLDING STORED

INTERNAL

11-3658

Excess Cable Folding

SIDE

VIEW

SERVICE LOOP (2.5ft.)

BOX EXTENDED
11-3659

Figure G-12

Service Loop

APPENDIX H
PDP-11/70 BLOCK DIAGRAM ADDRESS AND DATA PATHS

H-1

PROCESSOR DATA PATHS

xall

3R oR

TERIEL

CACHE

'1F1F]

BR]

UL L

[BR

)

fl'

MEMORY MGMT

]

]

PDRs

\}v

o[ tTo]t]o]]o
ToTiol
]

UNIBUS MAP

:
0l

)

DATA FROM FPP

PARS

DATA

UB MAP REGS

BIT MUX

SCCH

\; AV

37:0

100

CACHE

CONTROL

DATA

REG DATA

MAPH

Lia)

le]

‘;

s
o

z
A

PAR

MUX

PDR

[L)

» 2 P

N
n
[4]

'3
o
u

DRIVERS

SCCH

SSRJ

N
%]
[7)

%)
;

UNIBUS

DgrvTéRs
PDRE

UNIBUS

DATA
p
MAPA

MAP

‘<A\>

MUX

UB DATA
MAPJ

INTERNAL DATA BUS

PDP-11/70 Address Paths
H-2

REG

MAPJ

UNIBUS

MAPH

ORIVERS

SCCM,N

DATA

)

MUX 8 DRIVERS

Figure H-1

CACHE

LATCH

RECEIVERS

A\l——_——

[&)

J<L

REG MUX & DRIVERS

PDRJ

sapm | |2

DATA
RECEIVERS

o
0

UNIBUS

N
0

o
x

MAPC, D

CACHE

MAIN Mt

/RY DATA BUS <35:00>

3
(@]

:
‘.‘:’

[12]

MAIN MEMORY DRIVERS

MEMORY RECEIVERS USED

AS MBC DRIVERS

32 BITS (CDPC,D)

32 BITS + 4 BYTE

BYTE PARITY (CDPF)

GENERATE
(CDPF)

[e]

[@]

35:00

DRIVERS

CDPC.D

32 BITS + BYTE PARITY

CDPA

MUX DEPOSIT

HIGH WORD

CCBH

LOW WORD

MBC BUS

DRIVERS

32 BIT MUX
|

le__ _ _/

<31:116>
MDPH

PARITY
ON

INVERT

DTMP

GROUP 0
HI WORD

15:00 + 2P [15:00+2P |15:00
+ 2P |15:00
+ 2P
DTMB

CS3L

DTMB

DTMJ,H,K, L

FDOM
PARITY

CHECK
OB

DTMH DTMJ [DTMK DTML|DTMC DTMD|DTME DTMF
csaL

CS@L

DTMB

MBC BUS

MDPB

<15:00>
MDPH

MIXER

DRIVERS

A
<

]

LO WORD | HI WORD | LO WORD |

MDPB

MBC BUS

WRITE

GROUP 1

RC REG

MDPD

cHECkED

CDPF

GENERATE
MDPC

RD/RC ENB

{;

CHECK &

GENERATE
MDPC
RD REG

CACHE REG

MDPB

PARITY

CHECK &

MDPD

PARITY

RA REG

RB/RA ENB

MDPC

PARITY BUS

ODD WORD | EVEN WORD

MDPB

%8 REG

MAIN MEMORY

BD REGISTER

A MUX

MDPC

MEMORY DATA BUFFER

CDPE

15:00

DATA AND

WRITE MUX

[o]

15:00
B MUX

|
[

»---—-—o

PARITY
A

PARITY

MBC BUS

]

+ 2P
15:00

]

{

CcSIL-

DTMB

MDPE

INVERT

DTMP

MASSBUS

RE REG

RECEIVERS

MDPF

MBSA. B.C

SARITY
HECK
&
GCENERATE

DTMC,D,E,F

RF REG

MASSBUS

CHECK

(DTMN)

OUT BUF

MDPF

RF REG
MDPF

MASSBUS
DRIVERS

MBSA,B,C

CACHE DATA MUX
DTMM

UB DATA
DRIVERS
BCTC,D

UNIBUS

UB DATA
RECEIVERS

I MUX

MDPH

BCTD

Sz
Figure H-2

PDP-11/70 Data Paths

H-3

PDP-11/70 MAINTENANCE

Reader’s

eader’'s

AND INSTALLATION MANUAL

Lomments

EK-11070-MM-002

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