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EK-11045-MM-007

October 1976

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Document:	PDP-11/45, 11/50, and 11/55 System Maintenance Manual
Order Number:	EK-11045-MM
Revision:	007
Pages:	223
Original Filename:

OCR Text

EK-11045-MM-007

" PDP-11/45, 11/50,

and 11/55 system
maintenance manual

digital equipment corporation « maynard, massachusetts

Ist Edition, October 1972
2nd Printing, December 1972
3rd Printing, February 1973
4th Printing (Rev), April 1973
5th Printing, July 1973
2nd Edition, March 1974
7th Printing (Rev), October 1974
8th Printing (Rev), September 1976

Copyright © 1972, 1973, 1974, 1976 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no respon-

sibility for any errors which may appear in this
manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

PDP
RSTS

DECsystem-10

DIGITAL

DECSYSTEM-20

MASSBUS

TYPESET-8
TYPESET-11
UNIBUS

9/76-14

CONTENTS
Page

CHAPTER 1

GENERAL DESCRIPTION

1.1

BASIC SYSTEM DESCRIPTION

1.1.1

1-1

Physical Characteristics

1-1

. . . . . ... .. .. . .. .. ....
. . . . . .. ... .. ... ... ... ....
General Power Requirements and Electrlcal Specifications
. . . .. ..
Internal Option Power Requirements
. . . . .. ... ... ...

1.1.2
1.1.2.1

1.1.2.2

Determining Option Power and Line Current Requirements

. . .

1-1
1-7

1-10

1.1.3

H7420 Power Supply Characteristics

1.1.4

. . . . . . . .. . ... .....

1-11

H742 Power Supply Characteristics

1.1.5

. . . . . .. ... .. ... ....

1-11

Voltage Regulator Characteristics

. . . . . . . .. .. .. .. ..... 1-12
. . . . . . . ... ... ... ... ... .. 1-12
Environmental Specifications
. . . . . ... ... ... ........ 1-12
SYSTEM CONFIGURATIONS AND OPTIONS . . . ... ... ... .... 1-12
EXPANSION CABINETOPTION . . . . ... . . ... .
.
... 1-12
REFERENCE DOCUMENTS
. . . . . . . . . s 1-18
ENGINEERING DRAWINGS
. . . .. . . ... . . . .
.
... 1-18

1.1.6

Interface Specifications

1.1.7
1.2
1.3
1.4

1.5
1.6

DRAWING CONVENTIONS

CHAPTER 2

SYSTEM INSTALLATION

2.2

SITE PREPARATION

2.2.1

. . ... ... ... ...... e

e e e

1-23

. ettt
. . . . . . . . . . . . .. ...

2-1

. . . . . . . . .

Physical Dimensions

2-1

2.2.2

Fire and Safety Precautions

. . . . .. ... ... ....... Cee .

2.2.3

Environmental Requirements

. . . . . . ... ... .. .. ......

2-3

2.2.3.1

Humidity and Temperature

2.2.3.2

Air Conditioning

2233

Acoustical Damping

2.2.34

Lighting

2.2.3.5

Special Mounting Conditions

2.2.3.6

2.3.1

2.3.2

2-3

. . . . . ... ... ... .....

2-3

. . . . . . . . ... .. ..

2-3

Inspection
'

2-3

. s

. . . . . . . . .. . . .. . ... .. .....
INSTALLATION AND INSPECTION . . . . . .. . .. .. ... .....
Unpacking . . . . . . . . . . .
e
. . . . . ...

Cabinet Installation

245

2-6

. . . . . . . ... .. ... ... . .....
. . . . . .. ... ... .. ... ......

2-6

2.3.5

Intercabinet Connections
Unibus Connections

2.3.5.2

Remote Power Connections

2.3.5.3

Ground Strapping

2.3.5.4

Wire Trough Cabling

2-6

. . . . ... .. ... .. ..........

2-7

INITIALPOWER TURN-ON

2.5

SYSTEM CONFIGURATION TEST PROCEDURES

2.5.2

Preliminary Checks

2-6

. . . . . ... ... ... ......
. . . . . . . ...

2.4

Special Test Equipment

2-5

. . . . . . . .. .. ... . ... ...

ACPower Connections

2.5.1

24
2-4

. . . . . ... ... ... ........ ...

2.3.4
2.3.5.1

. . .. ... L
.

2-3
2-3

Flectrical Requirements

2.3

2.3.3

. . .

. . . . . . . . .

Static Electricity

2.2.4

. . . . . .. ... ... .. .....

. . . . . . . ...

. . . . . . . . . . .

. . . . . . . . ...
. . .

. .

2-6

2-7

. . ... ... .....
... ... .. ......

2-8
2-8

. . . . . . . .. ...

2-9

CONTENTS (Cont)

253

Detailed Procedure

. . . . . . . . .

e e e

o o e

e e e e

e e

2.5.33

RC Maintenance and Crystal Clock Test . . . . . . .. ... ...
. . . . . . . . .. .. ... ...
Microprogram ROM Cycle Test
.. ...
Single Time Start Test . . . . . . . . . . ..

2.534

Single Time Step Test

2.5.3.1
2.5.3.2

2.5.3.5

Switch Register and Display Test

2.5.3.6

Internal Data Transfer Test

2538

I/O Data Transfer Test

2.5.39

Unibus Test

2.5.3.10

Fastbus Test

2.5.3.12
2.5.3.13

2.5.3.14

o oo

. . . . . . . ... ... ....

. . . . . . . . .. ...

2.5.3.7

2.5.3.11

. . . . . . . . . .«

. . . . . .. .. ... ... ...

. . . . . . . .«

. . . & o o v v

... ...

v v v i

e e e e e e e e e e e e

e e e e

e
e
e
. . . . . . . o v v v e e e e e e e e e
v
v
v
oo
v
o
.
.
.
.
.
. . . . . .
ALU Arithmetic Test
Unconditional Branch Test . . . . . . . . . .. ... .....
Register-to-Register Data Move Test . . . . . . . ... . ... ..

. . . . . . . .. ... ... ..
Move-Immediate-to-Register Test
. . . & o i i i e e e e e e e e e e e e e e

2.6

CUSTOMER ACCEPTANCE

CHAPTER 3

POWER SYSTEM

3.1
3.3

OVERALL SYSTEM DESCRIPTION . . . . . . .« i i it e i e e e e
e s e
i i i e e
. . . . . . .« o
115 Vac AND 230 Vac MODELS
...
...
.
.
.
.
.
.
.
.
.
.
VERSIONS
SYSTEM
POWER
DIFFERENT

CHAPTER 4

AC POWER DISTRIBUTION

4.1

oo e
. . . . . .« . o« v i it v v i
PRIMARY ACPOWER OUTLETS
Primary AC Power Outlets, 861 Power Control . . . . . .. ... ...
. . . . ... ... ..
Primary AC Power Outlets, 860 Power Controls

3.2

4.1.1
4.1.2
4.2
42.1

4.2.2
42.2.1

e e et
e
ACPOWER CONTROL . . . o o o
Remote Power Connections . . . . . . . .
. . . . .« v v v i i e e
Power Controllers
. . . . . . . .
861 Power Controls

e
e e e e e e e e e e
e
. ¢« v o v v o v
e e e e e e e e e e e e e e
i

e e e e e e e e e

42.2.3

. . . . . . . v v v v e e e e e e e e e
...
. . . . . . . . . . . . ...
Control
Switched 860 Power

4224

Unswitched 860 Power Control

4222

860 Power Controls

. . . . . . . . . . ...

. ...

. . ..

4.3

BACK-UP AC POWER SOURCE FOR SEMICONDUCTOR MEMORY

4.4

ACPOWER DISTRIBUTION

CHAPTER 5

DC POWER DISTRIBUTION

5.1

e e e e e e e e e e e e e e
. . . . . o o i
DC POWER DISTRIBUTION
...
Power Distribution Cable Harnesses . . . . . . . . . . . .«
Backplane Power Distribution . . . . . . . . ... ... ...
e e e e e e e e e e e e e
. . . . .
DC POWER SUPPLIES
. . . . . . . . . . e
ACInput/Output
oo e
. . . . . . . . . . .« . . o
Power Control Boards

5.1.1
5.1.2

5.2

5.2.1
5.2.2

. . . . . o o

e e e e e e e e e e e e e e e

CONTENTS (Cont)
Page

5.2.2.1

5411086 Power ControlBoard

5.2.2.2

5409730 Power Control Board

5.2.3

H744 +5 V Regulator

5.2.4

H745-15 V Regulator

5.2.5

H746 MOS Regulator

5.2.6

H754 +20,~5 VRegulator

CHAPTER 6

. . . .. ... ... ....... 5-18
. . . .. ... .. ... ..... 5-22

. . . . . ... ... ... .. ... 5-25
. . . . .. .. ... ... ... . . .. ..., 5-27
. : . . . . . . . . . . . .. i 5-27
. . . . . . .. .. ... ... .. ..... 5-28

MAINTENANCE

6.1

MAINTENANCE EQUIPMENT REQUIRED

6.2

PREVENTIVE MAINTENANCE

6-1
6-2

6.2.2

Electrical Checks and Adjustments

6.2.2.1

Regulator Voltage Checks

6.2.2.2

Power Control

6.2.4

6.3

6-3
6-3

. . . . ... ... .......
. . . . . . . . ...

6-3

General Diagnostic Testing

6-4

. . . ... ... . ... ... ......

6-5

. . . . . . . . . . e

6-5

Visual Aids to Troubleshooting

6.3.3

Voltage Regulator Test Procedures

. . . . ... ... ... ........

6.3.3.1

Initial Tests

6.3.3.2

Output Short-Circuit Tests

6.34.1
6.3.4.2
6.3.4.3

6.3.4.4
6.3.4.5
6.4
6.4.1
6.5

. .

...

6-6

Testing a “Dead” Regulator . . . . . .. .. ... ... .....
Testing a Voltage Regulator After Repairs
. . . . ... ... ..
H7420 Power Supply Subassembly Removal and Installation Procedures

6-7

Power Supply Access Procedure

H744 Regulator Removal

. . . . . . . .. ... ... ...

6-7

6-9
6-9

. . . ... .. .. .. .........

6-9
. . . . . ... ... ... ...... 6-12
5411086 15 V Regulator/Power Line Monitor Board Removal
. . 6-12
5411086 15 V Regulator/Power Line Monitor Board Installation . 6-14
CPUMAINTENANCE . . . . . . .
s
e et 6-15
KB11-A,D CPU Diagnostics . . . . . . v v v v v v v v oo oo 6-16

H744 Regulator Installation

HOW TO USE MAINTENANCECARDS
Maintenance Mode Control

. . .. .. ... .. ... ..... 6-20

. . . . . . . . . . . .

6.5.2.1

Single ROM Cycle

6.5.2.2

uPBSTOP

6.5.3.2

. .

6-6

6.5.2

6.5.3

. . .

6-5

6-6

......

Clock Selection

6.5.3.1

. . . . .. .. ... ........

. . . . . . . . . . . . .. .

6.5.1

6.5.2.3

6-3

. . . . . . . . . . .. .. ... ......

POWER SYSTEM MAINTENANCE
Circuit Tracing

6.34

6-3

.. .. ... . ...,

. . . . .. ... .. ...

6.3.2

6.3.3.4

... ......

6.3.1

6.3.3.3

. . . . . ... ... ... .....

. . . . . . . ...

AC Power Connector Receptacles
Timing Margins

6-1

. . . . . . . . . .. ... . .

Physical Checks

6.2.2.3

6.2.1

6.2.3

. . . . ... . ... ... ...

. . . . . . . . . .. ..

. . .

6-20
. . . . . . . . . .. .. ... .. ..... 6-23

. . .. ... ... .. .. .. ... ...... 6-23
. ..

6-24
. . . . . ... 6-24
Using the Maintenance Card with KB11-A,D
. . . . . ... ... ... 6-24

Single Step

Deposit Test Instruction

MPBSTOPMODE

. . . . . ... ... ... .. ...... 6-25
. .. ... . ... ... .. 6-25

6.5.3.3

Single ROM Cycle Mode

6.5.3.4

SINGTPMode

. . . . .. . ... ... ... ...... 6-25

. ... . ... .. .

.. 6-26

CONTENTS (Cont)
Page

6.6
6.7
6.7.1

. . . . .. .. ... .. 6-27
HOW TO USE THE W900 MODULE EXTENDERS
. .. 6-27
. ..
MODULE AND ASSEMBLY REMOVAL AND REPLACEMENT
. . . . . . . . ... ... ... .. 6-27
Module Removal and Replacement

CHAPTER 7

PLUG-IN CARD OPTIONS

7.1
7.1.1
7.2
7.2.1
7.2.2
7.2.3
7.2.3.1
7.2.4
7.2.4.1
7.2.4.2
7.2.4.3
7.2.4.4

FP11-B, C FLOATING POINT PROCESSOR . . . . . . . . . ... ... ..
e e e e e e e e e e e e
. . . . . . . . .
Installation
e e e e e e e e e e e e e e e
e
.
.
.
.
.
.
FP11 DIAGNOSTICS
e e e e e
v v v v b i
v
v
. . . . . .
FP11-B Diagnostics
e e
. . . . . . . . .« « v v v i i
FP11-C Diagnostics
. . ... .. ... ..
Using the Maintenance Card with the FP11-B,C
FPP Test Timing . . . . . .« ¢ o v v v o i e i i e e e e e e
FP11-B, C Floating-Point Processor Procedures . . . . . . . .. .. ..
. . . . . ... ... . ... ...
Time Margining of the FP11-B
. . . . . .. .. ... ... ...
Time Margining of the FP11-C
. . . . . . . ..
Special Maintenance Instructions of the FP11-B
Special Maintenance Instructions of the FP11-C
. . . . . . . ..

6.7.2
6.8
6.8.1
6.8.2
6.8.3
6.8.3.1
6.8.3.2
6.8.4
6.9
6.10
6.10.1
6.10.2
6.10.3
6.10.4

7.2.4.5
7.2.4.6
7.3
7.3.1
7.3.2
7.4
7.4.1
7.4.1.1
7.4.1.2
7.4.1.3
7.4.1.4
7.4.2
7.4.3
7.5

. . . . . . . . . . .. oo e 6-27
Console Disassembly
REMOVAL AND REPLACEMENTOFICs . . . . . ... ... ... .... 6-28
e e 6-28
e e e
e e
Locationof ICs . . . . . . . o v i i e
e e e e 6-29
e
e
e
e
e
e
e
e
e
e
e
. . v v v v v v e e e e
IC ConnectionS
IC and Component Removal and Replacement . . . . . ... ... .. 6-29
Removal and Replacement of PlasticCase ICs . . . . . . .. . .. 6-29
. . . . . . ... ... 6-39
Removal and Replacement of CeramicICs
e 6-40
oo
.
Solder Mask Removal . . . . . . . . . .
... .. 6-40
...
...
.
..
.
.
.
PROCEDURES
SPECIAL MOS HANDLING
.. .. 6-41
...
.
STATUS
EQUIPMENT CONFIGURATION AND REVISION
o0 6-41
Mechanical Status Sticker . . . . . . . . . ..o
e e e e e 6-41
. . . . . . . . o e e e e e e
ECO Status Sticker
e 6-43
. . . . v v i e e e e e e e e e e e e e e e e
Module ECOS
. . . . . . . . ... ... ... 6-43
Module Utilization List (MUL) Sticker

7-1
7-1
7-2
7-2
7-3
7-3
7-4
7-4
7-4
7-4
7-4
7-6

Maintenance Instruction Programming Example
. . . . . . . .. 7-7
Console Display Features
. . . . .. . ... ... ... ..... 7-8
KT11-C,CD MEMORY MANAGEMENT UNIT . . ... ... ... ... .. 7-10
Installation
. . . . . . .
e
e e e e e e e e e
e e 7-10
Diagnostics
. . . . . . . . e e e
e
e e e e
e
e
e e 7-11
MS11 SEMICONDUCTOR MEMORY . . . . . . . ... ... ... 7-12
Installation
. . . . . . . .
e
e e e e
e
e e 7-12
Semiconductor Memory Jumper Connections . . . . . . . . . .. 7-12
Installation of Bipolar Memory
. . . . . . . . . . ... ... .. 7-16
Installation of MOS Memory (MS11-B)
. . . . . .. .. .. ... 7-19
Installation of Both MOS and Bipolar Memory
. . . . . . .. .. 7-19
Semiconductor Memory Calibration . . . . . . . .. ... ... ... 7-20
Diagnostics
. . . . . . e e e e
e
e e e e e e
e e e e e e e e e
. . . . .
KWII-LLINE CLOCK

e e
e
7-20
e 7-21
e e e e

CONTENTS (Cont)

CHAPTER 8

SYSTEM UNIT OPTIONS

8.1

SYSTEM UNITS

8.2

EXPANSION CABINETS

8.3

DC POWER DISTRIBUTION

8.3.1
8.3.2
8.4

CPUCabinet

. . . . .

. . .

Expansion Cabinets

MF11 CORE MEMORY

e e e e e e

. . . . . .

e e e e e s e

e e

e e e

. . . . . . . . .. . .

. . . . . . .
. . . .

. . .

e e

e e e

i
e

e e e

. . . . . . . . e

. . . . . . .

e e e

e e e e

8.5
APPENDIX A

IC DESCRIPTIONS

APPENDIX B

PERIPHERAL PREVENTIVE MAINTENANCE SCHEDULE

APPENDIX C

SUMMARY OF EQUIPMENT SPECIFICATIONS

ILLUSTRATIONS
Figure No.
1-1

Title
Location of Major Components and Assemblies Showing New Models

Using 861 Power Control

. . . . . . . . . . . . .

v i v

Location of Major Components and Assemblies Showing 860 Power

Controls Used on Early Models
Unibus A and BConnectors

. . . . . . . .. .. . ... . ... .....

. . . . . . . . . . .

0 i i i i
PDP-11/45,11/50, 11/55 Drawing Convention Examples . . . . .. ...
.

Typical PDP-11/45,11/50, 11/55:Power System

. . . . . . . .. ... ...

Newer Versions (3rd and 4th) of Power System; CPU Cabinet
Serial Numbers 2000 and Higher

. . . . . . . . .. .. ... ... .....

Early Versions (1st and 2nd) of Power System; CPU Cabinet
Serial Numbers Less Than2000
Power Connectors

. . .

. . . . . . . 0 v i

. .

i i e

. . . .. ... .. .. .....
e e e e e e e e e e e e

Two-Phase Outlet Connections for Use with 861-A Power Control
Example of Remote Power Control

861 Power Controller Schematic =

. . . .

. .

e e

. . . . . .

... ... ..

.....

. . .. ... .. .. .. ......

Power System Configuration with: Back-Up AC Power Source

. .

AC Power Interconnections (H7420and 861)
AC Power Interconnections (H742 and 861)

. . . . . . . ... ... ....
. . .. .. .. .. ... ....

AC Power Interconnections (H742and 860)

. . . . . . . . .. .. .. ...

Power Distribution Cable Harness 7009540, CPU Cabinet Serial Numbers
Greater Than 2000

. . . . . . .

. 0 .

e e

e e e

Power Distribution Cable Harness 7008784, Revisions A Through C
CPU Cabinet Serial Numbers Less Than2000

. .

.. .. ... ... ...

CPU Backplane Slot and Row Assignments

. . .

. .

.. ... ...

vii

.....

ILLUSTRATIONS (Cont)
Figure No.

5-4
5-5
5-6
5-7

5-8
5-9
5-10

5-11

5-12
5-13
6-1

6-2
6-3

Title

Page

Backplane Connectorsand Pins
. . . . . ... ... .. ... .. ...,
H7420 Power Supply
. . . . . . .
e
e e e e e e e e e e e
H742 Power SUpply . . . . o o o
e
e e e e e e e e e e e e e
Regulator Slot Assignments, CPU Cabinet . . . . . ... ... . ... .. ..
5411086 Block Diagram . . . . . . . . . . . .
e e
e
H744 Regulator Waveforms
. . . . . . . . . .
. v v v i i
H7420 Power-Up and Power-Down Sequences
. . . . . . .. .. ... ...
5409730 Block Diagram . . . . . . . . . . ..
e
e
e
e e
H742 Power-Up and Power-Down Sequences
. . . . . . . . . ... ... ..
Voltage Regulator El, Simplified Diagram
. . . . . ... ... ... ....
Typical Voltage Regulator Output Waveforms
. . . . . .. ... ... ...
H7420 Regulator Removal
. . . . . . . . . .. ... ...,
5411086 Removal (H7420)
. .. .. e
e e e e e e e e e e e e e e e e

6-4

Maintenance Card Installed for Test Purposes

6-5

Maintenance Card Control and Indicator Overlay for KB11-A,D and FP11-B,C
Test Procedures
. . . . . . . o i i
e e e e e e e e e e e e e e e e
Console Assembly . . . . . . . . L.
e
e
e e
e e e e e
Cross Section of Multilayer Board . . . . . . . . . . .. .. ...
Component Connections to Inner Layers
. . . . . . .. .. ... ... ...
Top View of Component Connection Made Directly to Inner Layer
. . . ..
Module to be Repaired and Tools Required . . . . . .. ... ... ... ..
Removing a Defective IC fromthe Module
. . . . .. .. .. ... .....
Defective IC Removed . . . . . . . . . . . . o
e
e e
e
Removing ICLeads
. . . . . . . . . . @ & i i i i i
i et it i e e e
ICLead Removed
. . . . . . . . . i i i e
e e e e e e e e e e e e
Applying Solder to Refill Eyelet
. . . . . ... ... ... ... ......
Removing Excess Solder from Eyelet
. . . .. ... .. .. ... ......
IC Location Ready for Insertionof New IC . . . . . . . . ... ... .. ..
Special Tool and Method Used to Clip Ceramic ICLeads
. . . . . .. .. ..
Mechanical Status Sticker
. . . . . . . . . . .. .
.o
e
ECO Sticker . . . . . o v o e i
e
e e e e e e e e e e e e e e e e e e e
MUL Stickers
. . . . . . . o
e
e e
e e e e e e e e e e e e e e e
Fastbus Multiplexing <14:11> Required E67 Jumper Configuration . . . . .
Unibus Multiplexing <14:11> Required E78 Jumper Configuration
. . . . .
CPU Backplane Memory Slots . . . . . . . . . . . . . ... ...
DC Power Distribution; Simplified Block Diagram
. . . . . .. ... . ...
Installation of System Units, Later Systems, CPU Cabinet Serial Numbers
2000 and Higher . . . . . . . . . o
e
e e e e e e e e e e e e
Installation of System Units, Early Systems, CPU Cabinet Serial Numbers
Less than 2000
. . . . . . . . . . ..
e
e e
e e

6-6
6-7

6-8
6-9
6-10
6-11
6-12

6-13

6-14
6-15
6-16
6-17

6-18
6-19

6-20

6-21

7-1

7-2
7-3
8-1

8-2
8-3

8-4

8-5
8-6

5-8
5-14
5-15
5-16
5-19
5-20
5-22
5-23
5-25
5-26
6-8
6-10
6-13

. . . . . . . . . . . .. . ... 6-20
6-23

6-28
6-29
6-30
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-42
6-42
6-44
7-14
7-15
7-16
8-2
8-3
84

Expansion Cabinet Power Distribution Cabmet Serial Numbers

7000 and Higher . . . . . . . . . . . o
e e
e
e e
8-6
Expansion Cabinet Power D1str1but10n Cabinet Serial Numbers
Less than 6999
. . . . . . . ..
e
e e e e e e e e e e e e
8-7
Installation of MF11-U/UP and FM-11 Kit In Early Systems, Expansion Cabinet
Serial Numbers Lessthan 6999
. . . . . . . . . . ... ... ... ...,
8-9
viii

TABLES
Table No.

Title

Page

1-1

Basic PDP-11/45 Configuration

Basic PDP-11/50 Configuration

. . . .. ... .. ... ... ... ...
. ... ... ... ... ... ......

1-5

1-3

Basic PDP-11/55 Configuration

. . ... ... ... ... ........

1-6

Input Specifications

. . . . .. C e e

e e e

1-5

Option Power Requirements (Maximum)

1-6

PDP-11/45 System Options

e e e

e e e e

e e

. .. ... ... ... .....

. . . . . . . . . . . . v v v v i i
..
. . . ... .. ... ... ... .........

1-14

1-7

Related Documentation

Title

Document Number

PDP-11/45 Manuals*
KB11-A, D Central Processor Unit Maintenance Manual

EK-KB11A-MM-004

MS11-A, B, C Memory Systems Maintenance Manual

EK-MS11A-MM-005

FP11-B Floating Point Processor Maintenance Manual

EK-FP11-MM-003

FP11-C Floating Point Processor Maintenance Manual

EK-FP11C-MM-PRE

KT11-C, CD Memory Management Unit Maintenance Manual

EK-KT11C-MM-005

MF11-U/UP Core Memory System Maintenance Manual

EK-MF11U-MM-003

MM11-S, MF11-L, and MF11-LP Core Memory Systems

EK-MM11S-TM-004

Reference Manuals

PDP-11/04, 05, 10, 35, 40, 45 Processor Handbook, 1975, 76

EB 05138 75 070/20-9 50

PDP-11 Peripherals Handbook, 1975

EB 05117 060/20-90 50

*A set of engineering drawings is provided with each of the components and options in the PDP-11/45, 11/50,

11/55 systems.

DEC drawing numbers are interpreted as indicated in the following example:

E-CS-M8109-0-1

Original drawing size —?

Pt Series
Manufacturing variation

Drawing type

CS:

Circuit Schematic

BS:

Block Schematic

DD:

Drawing Directory

MU:

Module Utilization

AD:

Assembly Drawing

UA:

Unit Assembly

WL:

Wire List

PL.:

Parts List

Module type, equipment type,

or a 7-digit DEC part number

IA:

Inseparable Assembly

ML:

Master List (replaced by DD in new drawing sets)

IC:

Interconnecting Cabling

1-19

Table 1-8
Drawing Number

Reference Drawing Summary

Title

PDP-11/45 System Engineering Drawings
B-DD-11/45-0-0

Drawing Directory

D-CS-5409684-0-1

Circuit Schematic — Console Board
11/45 Back Panel PC Board

D-IC-11/45-0-2

KB11-A Central Processor Unit
B-DD-KB11-A-0

Drawing Directory

E-MU-KB11-A-1

Module Utilization

D-BD-KB11-A-2

Block Diagram

D-FD-KB11-A-3

Flow Diagram

E-CS-M8100-0-1

M8100 DAP Module Schematic

E-CS-M8101-0-1

M8101 GRA Module Schematic

E-CS-M8102-0-1

M8102 IRC Module Schematic

E-CS-M8103-0-1

M8103 RAC Module Schematic

E-CS-M8104-0-1

M8104 PDR Module Schematic

E-CS-M8105-0-1

M8105 TMC Module Schematic

E-CS-M8106-0-1

M8106 UBC Module Schematic

E-CS-M8116-0-1

M8116 SIB Module Schematic

E-CS-M8109-0-1
D-IC-KB11-A-BG

M8109 TIG Module Schematic
Bus Cables and Grant Chain

C-CS-M930-0-1

Circuit Schematic — Bus Terminator

C-CS-M920-0-1

Circuit Schematic — Internal Bus Connector

E-CS-5409910-0-1

Circuit Schematic

E-CS-5409912-0-1

Circuit Schematic

KB11-D Central Processor Unit
B-DD-KB11-D

Drawing Directory

E-MU-KB11-D-1

Module Utilization

D-IC-KB11-A-BG

Bus Cables and Grant Chain

D-BD-KB11-D-2

Block Diagram

D-FD-KB11-C-1

KB11-C Flow Diagrams

E-CS-M8100-0-1

M8100 DAP Module Schematic

E-CS-M8101-0-1

M8101 GRA Module Schematic

E-CS-M8132-0-1

M8132 IRC Module Schematic

E-CS-M8123-0-1

M8123 RAC Module Schematic

D-CS-M8104-0-1

M38104 PDR Module Schematic

E-CS-M8105-0-1
E-CS-M8119-0-1

M8105 TMC Module Schematic
M8119 UBC Module Schematic

E-CS-M8109-0-1

Timing Generator

D-CS-M8116-0-1

System Jumper Board

C-CS-M930-0-1

Circuit Schematic

C-CS-M920-0-1

Circuit Schematic

E-CS-5409910-0-1

Circuit Schematic

E-CS-5409912-0-1

Circuit Schematic

1-20

Table 1-8
Drawing Number

Reference Drawing Summary (Cont)
Title

FP11-B Floating-Point Processor
B-DD-FP11-B-0

Drawing Directory

E-CS-M8112-0-1

M8112 FRM Module Schematic

E-CS-M8113-0-1

M8113 FXP Module Schematic

E-CS-M8114-0-1

M8114 FRH Module Schematic

E-CS-M8115-0-1

M8115 FRL Module Schematic

D-FD-FP11-B

FP Data Paths and Flow Diagrams

FP11-C Floating-Point Processor
B-DD-FP11-C-0

Drawing Directory

D-FD-FP11-C-

Flow Diagrams

D-CS-M8126-0-1

M8126 FRH Module Schematic

D-CS-M8127-0-1

M8127 FRL Module Schematic

D-CS-M8128-0-1

M8128 FRM Module Schematic

D-CS-M8129-0-1

M8129 FXP Module Schematic
1-C, CD Memory Management Unit

B-DD-KT11-C-0

Drawing Directory

D-BD-KT11-C-1

Block Diagrams

E-CS-M8107-0-1

M8107 SAP Module Schematic

E-CS-M8108-0-1

M8108 and M8108-YA SSR Module Schematic

MS11-AP Bipolar Memory

B-DD-MS11-A

Drawing Directory

D-CS-M8121-YA-1

Bipolar Memory Matrix

A-SP-MS11-A-1

MS11-A, C Bipolar Installation Procedure

MS11-B MOS Memory
B-DD-MS11-B-0

Drawing Directory

D-BD-MS11-0-1

Block Diagram

E-CS-M8110-0-1
E-CS-G401-0-1

M8110 SMC Module Schematic
G401 MOS Memory Matrix Schematic

E-CS-G401-YA-1

G401YA MOS Memory Matrix Schematic with parity
MS11-C Bipolar Memory

B-DD-MS11-C-0

Drawing Directory

D-BD-MS11-0-1

Block Diagram

E-CS-M8110-0-1

M8110 SMC Module Schematic

E-CS-M8111-0-1

M8111 Bipolar Memory Matrix Schematic

E-CS-M8111-YA-1

M8111YA Bipolar Memory Matrix Schematic with parity

1-21

Table 1-8
Drawing Number

Reference Drawing Summary (Cont)

Title
MF11-U 16K Core Memory

B-DD-MF11-U

Drawing Directory

D-CS-G114-0-1

16K Sense Memory

D-CS-G235-0-1

16K X—Y Drive

D-CS-M8293-0-1

16K Unibus Timing

D-CS-H217-0-1

Memory Stack (16K X 16)

D-MU-MF11-U-MU

Module Utilization

D-TD-MF11-U-1

Timing Diagram

D-CS-5410345-0-1

Backplane
MF11-LP 8K Core Memory

B-DD-MM11-F-0

Drawing Directory

D-MU-MM11-F-0

Module Utilization

D-CS-G109-0-1

G109 Module Schematic

D-CS-G231-0-1

G231 Module Schematic

D-CS-H215-0-1

H215 8K Memory Matrix Schematic

D-CS-M7259-0-1

M7259 Parity Module Schematic

KW11-L Line Frequency Clock
A-ML-KW11-L-0

KW11-L Master List
Power Systems

D-IC-11/45-0-1

Interconnection Diagram

B-DD-H7420-0

H7420 Drawing Directory

D-CS-H7420-0-0

Wiring Diagram

D-CS-5411086-0-1

Power Line Monitor (Regulator)

E-UA-H7420-0-0

H7420 Power Supply

A-P1-H7420-0-0

H7420 Power Supply

B-DD-H742-0

H742 Drawing Directory

D-CS-H742-0-1

H742 Circuit Schematic

C-CS-5409730-0-1

H742 Power Control Board Circuit Schematic

B-DD-H744-0

H744 Drawing Directory

D-CS-H744-0-1

H744 Circuit Schematic

B-DD-H745-0

H745 Drawing Directory

D-CS-H745-0-1

H745 Circuit Schematic

B-DD-H746-0

H746 Drawing Directory

D-CS-H746-0-1

H746 Circuit Schematic

D-CS-H754-0-1

H754 Circuit Schematic

B-DD-860-0

860 Drawing Directory

C-CS-860-0-1

860 Circuit Schematic

C-CS-5409770-0-1

860 Power Control Board

D-CS-861-A-1

861-A Power Control

D-CS-861-B-1

861-B Power Control

1-22

Table 1-8
Drawing Number

Reference Drawing Summary (Cont)
Title

DL11-A Asynchronous Line Interface
B-DD-DL11-0

Drawing Directory

C-UA-DL11-0-1

Asynchronous Line Interface

A-PL-DL11-0-0

Asynchronous Line Interface

E-CS-M7800-YA-11

Asynchronous Line Interface

D-IA-7008360-0-0

Cable, Modem BCO5C

A-SL-DL11-0-4

Cable Assembly (KL8/E)

A-AL-DL11-0-5

Modem Test Connector

A-SP-DL11-0-2

Installation Procedure

1.6
DRAWING CONVENTIONS
,
Figure 1-4 illustrates some of the drawing conventions used on the circuit schematics. Example A

defines the meaning of each part of a typical signal mnemonic. Example B provides the following
information:
1.

CLR SL YEL L, originating on sheet D of the TMC drawing (on which this gate is shown),
is asserted when low (0 V).

UBCE INIT H is input to TMC module on pin CJ1, as indicated by the arrow. (This pin
mates with backplane connector pin C11J1.)

The NOR gate is provided by pins 1, 2, and 3 of a type 8885 integrated circuit located at
position E24 on the TMC module.

TMCCSERF (1) H is the high (+3 V) output of the SERF flip-flop, when the flip-flop is set.

Example C shows the arrows indicating signals that leave the module. TMCE BUST OUT L is output
on pin DLI1 of the TMC module.

Examples D and E show the flip-flop conventions. Note in D that IRCA IRO0S5 (1) H is the same pin as
IRCA TRO05 (0) L, and that IRCA IRO0S5 (1) L is the same pin as IRCA IR05 (0) H.
The same type of flip-flop has been re-defined in example E - the D input is inverted; the 1 and 0
outputs are interchanged as are the Set and Reset inputs.

1-23

ORIGIN

IRCB

vOMD{Y

—

IRC MODLLE —J

l—— ASSERTION LEVEL

SSSFJTBsg

- SIGNAL MNEMONIC
Example A

CJi
UBCE
TMCC

INIT H

SERF (1)

» | 884

)O—- TMCD CLR SL YEL L

Example B
9

TMCE BUST H

7453'5‘0

TMCE BUST OUT L

TMCC TS3

CLK
A H

Example C
ém
12

éw
9

T]-—— 1RrCA
ras7af®
0>

y
—

IRCA

IROS

(1) M

IROS

(1)L
(1

E1S a2 IRcA IROS (0)L
0

IRCA

IRO5

(0)
H

Tia

—£9

1ReH v (0 H

sas7aP—— IRCH V (1)L

|
—

E72 158 treHv (0)L
0]

IRCH V

(0)
H

Tio
Example D

Example E
11-1135

Figure 1-4

PDP-11/45, 11/50, 11/55 Drawing Convention Examples

1-24

CHAPTER 2
SYSTEM INSTALLATION

2.1
GENERAL
This chapter contains installation information and recommendations to ensure a successful PDP11/45 installation. Installation of new options is an existing PDP11/45, 11/50, 11/55 system is
described in Chapters 7 and 8 for PC board and system units options.

Customer assistance is provided during site planning, preparation, and installation; the final layout
plan should be approved by both the customer and DEC prior to delivery of the equipment.
Planning considerations should include:
¢
e

e
e

Shipping and access routes; e.g., door, hall, passageway, elevator restrictions, etc.
Floor plan layout for equipment
Electrical and environmental considerations
Fire and safety precautions
Storage facilities for accessories and supplies

Site preparation is dictated by the customer’s requirements and can range from providing the required
source power to complete construction or remodeling of the selected installation site. Therefore it is
recommended that any and all requirements and restrictions be considered and effected prior to shipment and installation of the equipment.
2.2

SITE PREPARATION
Adequate site planning and preparation simplifies the installation process. DEC Sales and Field Service Engineers are available for consultation and planning with customer representatives regarding
objectives, course of action, and progress of the installation. The information in this paragraph is
provided primarily to permit review of the site planning; use the PDP-11/45 Site Configuration Worksheet to perform the initial site planning.
2.2.1

Physical Dimensions
The overall dimensions and total weight of a particular system - the dimensions, weight of any optional cabinets, cable lengths, and the number of free-standing peripherals - should be known prior to
shipment.
The route the equippment is to travel from the customer receiving area to the installation site should be

studied; measurements of doors, passageways, etc., should be taken to facilitate delivery of the equipment. All measurements and floor plans should be submitted to the DEC Sales Engineer and Field
Service to ensure that the equipment is packed to suit the installation site facilities. Any restrictions
(such as bends or obstructions in hallways, etc.) should be reported to DEC.

2-1

If an elevator is to be used for transferring the PDP-11/45, 11/50, or 11/55 and its related equipments
to the installation site, DEC should be notified of the size and gross weight limitations of the elevator
so that the equipment can be shipped accordingly.

The site space requirements are determined by the specific system configuration to be installed and,
when applicable, provision for future expansion. To determine the exact area required for a specific
configuration, a machine-room floor plan layout is helpful. When applicable, space should be provided in the machine room for storing tape reels, printer forms, card files, etc. The integration of the work
area with the storage area should be considered in relation to the work flow requirements between
areas.

In large installations where test equipment is maintained, DEC recommends that the test equipment
storage area be within or adjacent to the machine room.

Operational requirements determine the specific location of the various options and free-standing
peripherals of the system. Dimensions, weights, and cable lengths of freestanding peripheral equipment must be known prior to installation - preferably during site preparation and planning. The
computer peripherals must not be located at distances where connecting cables exceed maximum limits. The following points should be considered when planning the system layout:
1.

Ease of visual observation of input/output devices by operating personnel.

Adequate work area for installing tapes, access to console, etc.

Space availability for contemplated future expansion.

Proximity of the cabinets and peripherals to any humidity-controlling or air-conditioning
equipment.

Adequate access to equipment (e.g., rear door, etc.) for service personnel.

The final layout will be reviewed by the DEC Sales Engineer, Field Service, and in-house engineering
personnel to ensure that cable limitations have not been exceeded and that proper clearances have been
maintained.
2.2.2

Fire and Safety Precautions

The following fire and safety precautions are presented to aid the customer in maintaining an installation that affords adequate operational safeguards for personnel and system components.

If an overhead sprinkler system is used, a dry pipe system is recommended. Upon detection
of a fire, this system removes source power to the room and then opens a master valve to fill
the room’s overhead sprinklers.

If the fire detection system is the type that shuts off the power to the installation, a batteryoperated emergency light source should be provided.

Ifan automatic carbon dioxide fire protection system is used, an alarm should sound prior
to release of the CO, to warn personnel within the installation.

If power connections are made beneath the floor of a raised-floor installation, waterproof
electrical receptacles and connections should be used.

An adequate earth ground connection should be provided to protect operating personnel.

2-2

2.2.3
Environmental Requirements
An ideal computer room environment has an air distribution system that provides cool, well-filtered,
humidified air. The room air pressure should be kept higher than that of adjacent areas to prevent dust
infiltration.
2.2.3.1
Humidity and Temperature - The PDP-11/45, 11/50, and 11/55 electronics are designed to
operate in a temperature range of from 50° F (10° C) to 110° F (40° C) at a relative humidity of 10 to
90 percent with no condensation. However, system configurations that use input/output devices such
as magnetic tape units, card readers, etc., may require closer control of the environment. See Appendix
C for detailed specifications. Nominal operating conditions for a typical system configuration are a
temperature of 70° F (20° C) and a relative humidity of 45 percent with no condensation. (For operation above sea level, see Paragraph 1.1.7)
2.2.3.2 Air Conditioning - When used, computer room air-conditioning equipment should conform
to the requirements of the *““Standard for the Installation of Air Conditioning and Ventilating Systems
(non-residential),” N.F.P.A. No. 90A, as well as the requirements of the Standard for Electronic Computer Systems, N.F.P.A. No. 75. Remember, air flow in a PDP-11 is from top to bottom of cabinets.
2.2.3.3

Acoustical Damping - Some peripheral devices (such as line printers and magnetic tape transports) are quite noisy. In installations that use a group of high noise-level devices, an acoustically
damped ceiling will reduce the noise.

2.2.3.4 Lighting - If CRT peripheral devices are part of the system, the illumination surrounding
these peripherals should be reduced to enable the operator to conveniently observe the display.

2.2.3.5 Special Mounting Conditions - If the system will be subjected to rolling, pitching, or vibration
of the mounting surface (e.g., aboard ship), the cabinetry should be securely anchored to the installation floor by mounting bolts. Since such installations require modifications to the cabinets, DEC must
be notified when the order is placed so that the necessary modifications can be made.
2.2.3.6 Static Electricity — Static electricity can be an annoyance to operating personnel and can (in
‘extreme cases) affect the operational characteristics of the PDP-11/45, 11/50, 11/55 and related peripheral equipments. If carpeting is installed on the computer floor, it should be of a type designed to
minimize the effects of static electricity. Flooring consisting of metal panels, or flooring with metal
edges, should be adequately grounded.
2.2.4

Electrical Requirements
The PDP-11/45, 11/50, 11/55 operates from a nominal 115 V, 50/60 Hz or 230 V, 50/60 Hz, ac power
source. The primary ac operational voltages should be maintained within the tolerances defined in
Paragraph 1.1.2 and in Chapter 4.
For certain options that use synchronous motors, line voltage tolerance should be maintained within

+ 15 percent of the nominal values, and the 50/60 Hz line frequency should not vary more than +2 Hz.

Primary power to the system should be provided on a line separate from lighting, air-conditioning,
etc., so that computer operation will not be affected by voltage transients. The wiring should conform
to the following general guidelines:
1.

All electrical wiring must conform with the National Electric Code (NEC).

The ground terminal on the receptacle will normally have a green colored screw; the neutral
terminal will be white or silver colored; and the ‘“hot” terminals will be brass colored.

Under the NEC (in the U.S. only), the color coding for the neutral wire is either white or
gray, and the ground wire is solid green, green with one or more yellow stripes, or bare.
There are no specified colors for the “hot’ wires.
2-3

The PDP-11/45, 11/50, 11/55 cabinet grounding point should be connected to the building power
transformer ground or the building ground point. Direct any questions regarding power requirements
and installation wiring to the local DEC Field Service Engineer.
Chapter 4 contains a detailed description of the ac power system and includes a list of connectors and
plugs used.

2.3

INSTALLATION AND INSPECTION
CAUTION
Do not attempt to install the system until DEC has
been notified and a DEC Field Service Representative is present.

The procedures in Paragraphs 2.3.1 through 2.3.5 are provided to assist in receipt, unpacking,
inspection, and installation of the PDP-11/45, 11/50, 11/55, and associated peripherals and equipments. Paragraphs 2.4 and 2.5 describe the procedures recommended for bringing the system up.
2.3.1

Unpacking

Before unpacking the equipment, check the shipment against the packing list provided. Check that the
correct number of packages has been delivered and that each package contains all the items listed on
.the accompanying packing slip. Also, check that all items on the accessories list in the Customer
Acceptance Procedures have been included in the shipment. Unpack the cabinets as follows:
1.

Remove outer shipping container.

Remove the polyethylene cover from the cabinets.

Remove the tape or plastic shipping pins from the cabinet(s) rear access door(s).

Unbolt cabinet(s) from the shipping skid as follows: to remove shipping bolt from right side
of cabinet.

Remove the shipping bracket. Pull CPU mounting box out to locked position and
remove side panels from cabinet.

Remove nut and washer from the underside of the shipping skid.

There are three 10-32 screws attaching the lower power supply to the front upright of
the cabinet; loosen these three screws (no more than three turns).

At the rear of the lower power supply are three additional screws. Remove these completely and swing the power supply toward the middle of the cabinet 1 to 1-1/2 in.
Holding the power supply, remove the shipping bolt by pulling straight up.

Swing the power supply back to the original position, replace the rear screws and
tighten the front screws.

Raise the leveling feet so that they are above the level of the roll-around casters.

Use wood blocks and planks to form a ramp from the skid to the floor and carefully roll the
cabinet onto the floor.

Roll the system to the proper location for installation.

If necessary, repeat steps 1 through 7 for the expansion cabinets. When the cabinets are
properly oriented, follow the procedure of Paragraph 2.3.3 to install the cabinets(s).
2.3.2

Inspection

After removing the equipment packing material, inspect the equipment and report any damage to the
local DEC sales office. Inspect as follows:
1.

Inspect external surface of the cabinets and related equipments for surface, bezel, switch,
light damage, etc.

Open the rear door of the cabinet, and internally inspect the cabinet for console, processor,
and interconnecting cable damage; loose mounting rails; loose or broken modules; blower
or fan damage; any loose nuts, bolts, screws, etc.
Inspect the wiring side of the logic panels for bent pins, broken wires, loose external components, and foreign material.
Inspect the power supply for proper seating of fuses and power connections.

Inspect all peripheral equipment - including magnetic tape and DECtape transport heads,
motors, paper-tape sprockets, etc. — for internal and external damage.
CAUTION
Do not operate any peripheral device that employs
motors, tape heads, sprockets, etc., if these items
appear to be damaged.
2.3.3

Cabinet Installation

The cabinets are provided with roll-around casters and adjustable leveling feet so it is not necessary to
bolt the cabinet to the mounting floor unless conditions indicate otherwise (e.g., shipboard installation). In multiple cabinet installations, receiving restrictions may require that cabinets be shipped
individually or in pairs. In such cases, the cabine¢ts are connected at the installation site. Cabinet
installation procedures are as follows:
L.

With the cabinets positioned in the room, install H952-GA filler strips between cabinet
groups (filler strips are shipped attached
to the end of a cabinet group). Remove four bolts
each from the front and rear filler strips. Butt the cabinet groups together while holding the
filler strips in place and rebolt through both cabinets and the filler strips (drawing C-UAH952-G-0). Do not tighten the bolts securely at this time.
Lower the leveling feet so that the cabinets are not resting on the roll-around casters but are
supported on the leveling feet.

Tighten the bolts that secure the cabinet groups together. Ensure that all leveling feet are
planted firmly on the floor.

Electrical connections, including intercabinet ground strapping, are described in Paragraphs
2.3.4 and 2.3.5.

2.3.4

AC Power Connections

Paragraph 2.2.4 and Chapter 4 define the electrical requirements and the ac power outlets required at
the site. Early systems include two 860 power controls as shown in Figure 1-2. Current versions are
equipped with a single 861 power control as shown in Figure 1-1. Most of the additional cabinets in a
system include a power control and ac connector that are similar to that supplied in the basic CPU
cabinet. All ac power is distributed from the power control to the appropriate power supplies within
the cabinet.

The power controls in all cabinets are connected to provide central control of power turn-on and turnoff from the CPU console POWER switch. Before connecting any power cables to the site source
power, check all building wiring. Ensure that power receptacles of the appropriate types have been
provided for each cabinet and that the receptacles are positioned close enough to the cabinet positions
to allow the cables to be connected without stretching or crossing the cables. In particular, check that
the phase and neutral wires have been connected to the same pins in each receptacle.
2.3.5 Intercabinet Connections
When a multi-cabinet system is assembled, three types of electrical connections must be made between
cabinets (refer to Paragraph 2.3.3 for mechanical connections). These connections are:

Unibus connections - A BC11-A cable must connect the last system unit in a cabinet to the
first system unit in the next cabinet.

Remote power connections — All cabinet power controls are connected to a control bus that
provides for system turn-on and turn-off.

Ground strapping - The frame ground of the system is distributed through the cabinets by
direct electrical connections between the cabinet frames.

2.3.5.1 Unibus Connections - The BC11-A Unibus cable is the I/O bus that connects all system
components. To connect the Unibus between the CPU cabinet and an expansion cabinet, insert the
BC11-A cable in the rear system unit slot of the mounting box of the CPU cabinet. The cable runs
through a cable clamp in the upper left corner at the rear of the CPU mounting box and passes under
the power supply mounting rails into the next cabinet. In the expansion cabinet, the cable passes
through a similar cable clamp and is inserted in the appropriate slot of the first system unit of the
mounting box.
2.3.5.2 Remote Power Connections - The power controls in all cabinets must be interconnected to
ensure common power turn-on and turn-off. Detailed cabling instructions are provided in Paragraph
4.2 of this manual.
2.3.5.3 Ground Strapping - Electrical safety is provided by connecting all the cabinet frames to the
ground level of the site power system. This is accomplished by connecting a wire in each power cable
between the frame and the power system ground; this is not a load-carrying wire - it is intended only as
an emergency ground path. The green wire in each power cable is the frame ground, while the white
wire is the neutral, or return wire, that carries the load current.
To improve the level of safety provided by the frame ground connections, all cabinet frames are
connected by braided copper straps or No. 4 AWG solid wire with crimp-on lugs which are fastened to
copper studs that are welded to the frames (this also prevents the generation of ground loops between
cabinets that are connected by signal-carrying cables). The studs are welded to the bottom side rails of
the cabinet frame, facing inward; the stud on the left side of the cabinet is slightly forward of center
while the stud on the right side is slightly to the rear.

2-6

The ground strap supplied with each cabinet is fastened to one stud, passed over the side rail of that
cabinet and the side rail of the adjacent cabinet, and fastened to the stud in that cabinet. The copper
studs are threaded and nuts are supplied on the studs.
Similar strap/stud grounding is used to ground the H7420 power supplies to the cabinet frame.
2.3.5.4 Wire Trough Cabling - An optional wire trough system can be installed which provides cable
organization that improves the appearance of the system’s cabling and helps reduce cable damage.
Device location in the CPU cabinet and expansion cabinet determines required cable lengths and
trough configuration. For planning and installation procedures, refer to the Wire Trough Installation
Manual (EK-WIRET-IN-001).

2.4

INITIAL POWER TURN-ON
CAUTION
The following checks and those in Paragraph 2.5
should be performed as part of the initial system
installation checkout procedures.

Inspect the CPU backplane assembly for bent connector pins, loose wires, imperfections in the dc
power distribution board etch, or any other physical defects that can be observed. Correct any problems discovered.

With the power off, check the power distribution system to determine if any short-circuits to ground
exist. Refer to power supply dc distribution charts in Chapter 5 of this manual for circuit and connector information.
Check the dc power system as described below. Figures 5-1A, B, and C show the power distribution
harness for newer systems (CPU cabinet serial numbers 2000 and higher, H960D cabinets and higher)
while Figure 5-2 shows the same for older systems. Paragraph 3.3 defines old and new systems.

Unplug the ac power cables. Disconnect the following Mate-N-Lok plugs:
New Harness

Old Harness

P2-P13
P17-P21
P25-P31
P36, P37, P40

P2-P13
P17-P21
P25-P31

P1, P14-P16, P22-P24 and P32-P35 remain connected in all cabinets.

Turn off the circuit breakers on all the 860 or 861 power controls. The console switch must
be on or the LOCAL/REMOTE switch on the power control must be set to LOCAL to
check the ac voltages on the upper supply.

Plugin the ac power cable(s), turn on the circuit breaker(s), and check the 20-30 Vac generated by the H7420 power supplies. These voltages can be checked at the pins of plugs P17
through P21, P25 through P31 (also P40 in newer systems). Table 5-2 provides specific pin
numbers.

Turn off the circuit breakers and connect plugs P17 through P21, P25 through P31 (and P40
if applicable).

Turn the circuit breakers on and check the dc voltages generated by the regulators. Note
that not all regulators need be present. The voltages should be checked on the following
connectors (P8 through P11 are ground returns for these voltages):
New Harness

Old Harness

P2-P7
P12

P2-P7
P12 & P13

P36 & P37

P36

Table 5-2 provides specific pin numbers.
If a regulator shows no output, turn off the circuit breakers, lower the voltage adjustment
for this regulator, then reapply power and check again (the regulator may have crowbarred
due to overvoltage).
Turn the circuit breakers off and plug in the remaining connectors.
Turn the power on and check the voltages at the points listed in Table 6-2. Adjust if
necessary.

Verify correct operation of the console power switch. Refer to Table 6-1 of the KB11-4, D
Central Processor Unit Maintenance Manual.
9.

Check the operation of all fans.

1 0.

Refer to Paragraph 2.5 for an initial test procedure of the KB11-A, D, which should be
performed after this initial power turn-on procedure.

2.5
SYSTEM CONFIGURATION TEST PROCEDURES
The test procedures require the following basic PDP-11/45, 11/50, 11/55 system components:
1.

KBI11-A or KB11-D Central Processor Unit, with console and power supplies, installed in
cabinet.
Magnetic core memory with Unibus connection to KB11-A, D or MS11 Semiconductor
Memory System installed in the CPU backplane assembly.
MS8116 SJIB module or KT11-C, CD option (M8107 SAP module and the SSR module M8108 in the KT11-C, M8108-YA in the KT11-CD).

2.5.1
Special Test Equipment
The following special test equipment is required:
1.

Maintenance card with W130 or W133 driver module. Use of the maintenance card is
described in Paragraph 6.5.

Tektronix model 454 oscilloscope, or equivalent, is preferred; however, Tektronix model
453, or equivalent, is adequate for most tests.

2.5.2 Preliminary Checks
The following procedures are recommended as preliminary precautions when installing a PDP-11/45,
11/50, 11/55.
1.

Check the power supplies as detailed in Paragraph 2.4.

Turn the power supplies off. Refer to the module location drawing to either install, or check
for proper installation of all required modules. These include:

The KB11-A or KB11-D module complement and console connectors.

The M8116 SJB module or the KT11-C, CD modules (M8107 and M8108 in the KT11C, or M8107 and M8108-YA in the KT11-CD).

The Unibus A cable connector to the magnetic core memory or the MS11 modules.

If a problem is detected, install the maintenance and driver cards. Install the W130 driver
module in slot 1, row F, on the CPU backplane. If dual driver module W133 is used, install
it in slot 1, rows E and F. The maintenance card plugs into the driver module connector
associated with row F for KB11-A, D test purposes.

2.5.3
Detailed Procedure
The following test proceudre is used to verify the correct operation of sufficient logic elements in the
KBI11-A, D to enable the initial KB11-A, D diagnostic programs to be executed. The sequence of these
tests leads to the ultimate execution of an unconditional branch instruction, which is the first instruction tested by the diagnostic programs.

The logic elements are checked in small groups. Each step uses only previously tested logic elements to
perform tests on additional logic elements. Test results only verify that the logic under test is operating;
they do not test speed or quality of performance.
NOTE
Use the KB11-A, D block diagrams shown in the

KBI11-A, D Central Processor Unit Maintenance
Manual, Chapter 4, Figure 4-1 and 4-4, as an aid to
visualize which groups of logic elements are being
verified by each test.
2.5.3.1

1.
2.

RC Maintenance and Crystal Clock Test

Install the maintenance card and set CLK switch S3 to RC.
Turn the power supplies on and use the console key switch to apply power to the KB11-A,
D.

Connect oscilloscope to observe TIGA TPH MAT H clock output at pin FU1 of slot 15.

Adjust potentiometer R 104 on the TIG module (RC clock adjustment) to produce a 60 ns
period for each complete TIGA TPH MAT H clock pulse. This ensures a 300 ns machine
state made up of five 60 ns time states.

Set maintenance card CLK switch S3 to XTAL and observe that the crystal clock is operating properly.

2-9

2.5.3.2

Microprogram ROM Cycle Test

Turn power off.
Set console ENABL/HALT switch to HALT.
Turn power on.

Set DATA display select switch to uADRS FPP/CPU. Verify that the CPU ROM address is
170s. This is displayed in the low-order byte of the DATA display.

When the correct DATA display is observed, proper operation of the following processor logic elements is verified:

The ROM microaddress (UADR) logic

One microprogram branch (console)

The microprogram ROM and buffer (drawing RACA through RACD)

Part of the display multiplexer (low byte drawing PDRF)

Part of the console DATA indicator lamps (drawing KNLA)

2.5.3.3

1.
2.

Single Time Start Test

Set maintenance card switches S1 and S2 to 2 to select SING TP operation.
Press console START switch. The DATA display should display microprogram ROM
address 2005 in the low byte indicators.

This test provides additional checks of the ROM microaddress (UADR) logic, the display multiplexer,
and the DATA display indicator lamps.
2.5.3.4

Single Time Step Test

Press maintenance card MAINT STPR switch to produce time pulses.

Note that each time the MAINT STPR switch is pressed, the TPH indicator changes state.

Verify that the uADRS changes at T3, and the processor sequences through several machine
states. Maintenance card indicators T1 through T5 will light in sequence, progressing from
T1 through TS each time TPH goes off.

Verify that after several machine states, the uADRS becomes 170s. After arriving at 170s,
the processor continues to cycle through that machine state.

When correct results are observed for this test, the microprogram branch and microprogram address
logic is further verified.

2-10

2.5.3.5
1.

Switch Register and Display Test
Reset the maintenance card switches S1 and S2 to 0 and advance the MAINT STPR switch
to allow normal timing cycles.
Set the DATA display select switch to BUS REGISTER.

Set the console switch register for various switch inputs to test all switches and DATA
display indicators.
When this test is successfully completed, all parts of the console DATA display, the display multiplexer, and data inputs from the switch register are verified for proper operation. When correct test
results are obtained for all tests up to this point, the following logic elements are operating properly:
1.

Console switch register

Basic microprogram control and address logic

Processor timing circuits

Part of the bus register multiplexer (BRMX), bus register (BRA), and part of the display
multiplexer, all located on M8104 PDR module

2.5.3.6

Internal Data Transfer Test - The following test is the initial data path test; it involves transferring data from the switch register to one of the general registers.
1.

Set maintenance card switch S1 to 0 and S2 to 1 to select ROM CYCL operation.

Set the console ADDRESS display select switch to CONS PHY.

Set up various address selections on the console switches and press LOAD ADRS for each
selection.

Observe that the ADDRESS display corresponds to the address selected.

When correct test results are observed, proper operation of the following parts of the processor is
verified:
1.

The A multiplexer (AMX) (passing the BR input without error)

The ALU (passing the A input without error)

The shifter (SHFR) (passing the data without error)

The source register (SR)
The bus address multiplexer (BAMX) (passing the BR input)
The console ADDRESS display indicator lights

2-11

2.5.3.7

KBI1-4 Test:

Set the console ADDRESS display select switch to CONS PHY and set the DATA display
select switch to DATA PATHS.
Set switches to all Os.
Press LOAD ADRS.
Press REG DEP.

Increment the switch register by 1, by setting the switches accordingly.

Repeat steps 3, 4, and 5 for successive values from Os through 17s. (Register 0 contains 0,

Load address 0 and press REG EXAM. Observe that the DATA display indicates the contents of Register O are Os.

Increment switch register contents by 1 and press LOAD ADRS.
Press REG EXAM.
1 0.

Continue to examine the contents of each register by repeating steps 8 and 9 to determine if
the correct data was deposited during steps 2 through 6.
NOTE

If a register has the number of some other register in
it, the address logic is probably at fault. If the numbers in the register have any bits other than the four
least-significant bits set, the register storage elements are probably the cause of the trouble.
1 1.

As a further test, deposit other switch register data into the general register to ensure that all
bits are stored and displayed correctly.

KBl 1-D Test:
1.

Set the console ADDRESS display select switch to CONS PHY and set the DATA display

select switch to DATA PATHS.

Set switches to all Os.
Press LOAD ADRS.
Press REG DEP.

Increment the switch register by 1, by setting the switches accordingly.

2-12

Repeat steps 3, 4, and 5 for successive values from Og through 175, (Register 0 contains 0,
register 1 contains 1, etc.)
Load address 0 and press REG EXAM. Observe that the DATA display indicates the contents of Register 0 are Os.
_
Continue to examine the contents of each register by consecutively pressing REG EXAM to
determine if the correct data was deposited during steps 2 through 6. (Each consecutive
REG EXAM automatically steps the address.)
NOTE
If a register has the number of some other register in
it, the address logic is probably at fault. If the numbers in the register have any bits other than the four
least-significant bits set, the register storage elements are probably the cause of the trouble.

As a further test, deposit other switch register data into the general registers to ensure that
all bits are stored and displayed correctly.

When the test results are correct, the following parts of the KB11-A,D processor have been verified for
proper operation:

The general destination (GD) register (drawings GRAD through GRAH)

The destination register multiplexer (DRMX) (drawings GRAD through GRAH)

The destination register (DR) (drawings GRAD through GRAH)

The program counter registers (PCA and PCB) (drawings DAPF and DAPH) if register 07
is deposited and examined

2.5.3.8 I/0 Data Transfer Test - The tests performed up to this point have verified that the processor
can transfer data to an external location.
1.

Set the console switches to an address within the range assigned to the available memory
(either Unibus memory or MS11 Semiconductor Memory System).
Press LOAD ADRS.

Set ENABL/HALT switch to HALT.
Set various data into the switch register and perform alternate DEP and EXAM functions.
With the DATA display select switch set to DATA PATHS, the DATA displayed by the
deposit should match the DATA displayed by the EXAM for each test.

After checking the DATA display for each test switch the DATA display select to uADRS
FPP/CPU and observe that the processor returns to ROM state CON.00 (ROM address
170s) after each DEP and EXAM is performed.

2-13

When the correct test results are observed, the following parts of the processor are verified to be
operating properly:

The Unibus (or semiconductor memory) control logic on the UBC module (M8106 in the

The data multiplexer (DMX), passing the BR inputs without error (drawing PDRE).

The BRMX Unibus inputs (drawing PDRA) and the BAMX PCB inputs (drawings DAPB,

KBI11-A, M8119 in the KB11-D).

DAPC, and DAPD).

Additional timing pulse logic on the M8109 TIG module.

If the deposit and examine tests are unsuccessful, the problem is probably in the external data t.ransfgar
operation. To further isolate the cause of malfunction, perform either the Unibus test outlined in
Paragraph 2.5.3.9 or the Fastbus test outlined in Paragraph 2.5.3.10.
2.5.3.9

Unibus Test

Set maintenance card switches S1 and S2 to 1 to select SING TP operation. Center CLK
switch S3 for single time pulse operation.

Repeat Step 4 of the I/O data transfer test (Paragraph 2.5.3.8).

Press the MAINT STPR switch to perform the deposit and examine functions in single time
steps.

Look for the following normal indications:

Step through time states until the maintenance card BBSY indicator lights.

Several more time states should elapse before the MSYN indicator lights. If not, ground
MSYN SET H at pin E12 Ul on the UBC module and repeat step to see if MSYN ever
lights.

The SSYN indicator should appear to light simultaneously with MSYN.

There should be several clock ticks before the MSYN and SSYN indicators go off.

There should be several more clock ticks before the BBSY indicator goes off.
NOTE
Data transferred into the processor during the examine function should appear in the BR at the end of
ROM cycle at uADRS 1535. Set DATA display
select switch to BUS REGISTER. The input data
should be located in the DR at the end of ROM cycle
at uADRS 137;. Set DATA display select switch to
DATA PATHS.

2-14

2.5.3.10 Fastbus Test — Use the same test procedure as described for the Unibus test (Paragraph
2.5.3 .9). Look for the following normal Fastbus indications:
1.

The BBSY indicator lights.

Several more time states should elapse before the MEM indicator lights.

The CNTL OK and T3 indicators should appear to light simultaneously.
ALU Arithmetic Test

Select an address and deposit data into that location.

Press DEP again several times to deposit the data into several successive word locations.

Load the original address and press EXAM several times to determine that the data was

stored in the several successive locations.

When correct test results are observed, the following parts of the processor are verified to be operating

properly:
1.

The constant multiplexer KOMX (drawing DAPD).

The B multiplexer (BMX) (drawing DAPB, DAPC, and DAPD).

The ALU arithmetic function A plus B (drawing DAPF and DAPH).
Unconditional Branch Test

Deposit a branch instruction (000777s) in a memory location.
Load the address of the instruction.

Set maintenance card switches S1 and S2 to select ROM CYCL operation.

‘Set ENABL/HALT switch to ENABL.
Press START.

Use the MAINT STPR to step the processor through single machine states as indicated by

the tyADRS FPP/CPU DATA display. Look for the following events:

The processor should enter the RES.00 machine state at wADRS 015 after executing

The processor should cycle throug' “e RES.20 state at uADRS 374 at least twice. If

machine states 200, 154, 170, and 176.

this does not occur, the micropre_ .m branch has failed and the processor cannot
execute instructions at full speed.

The processor should enter the IRD.00 state at wADRS 343 with the correct data in the
BR.

Set DATA display select switch to BUS REGISTER to check for the correct data (0007775).

Press the MAINT STPR. The next uADRS indication should be 326, which is the BXX.02
machine state.
NOTE
When the correct test results are observed, the processor fork A logic is operating properly. Once this
test has been successfully completed, reset maintenance card switches S1 and S2 for normal operation
and repeat the test, allowing the processor to loop
through the branch instruction. If it does, the offset is
being computed properly.

While the processor continues to loop through the BR instruction, press the HALT switch.
The processor should halt in the CON.00 state at uADRS 170. If it does not, check the
processor in single ROM cycle mode to determine that the BRQ branch during instruction
fetch works and that the trap sequence ends in the console state.
2.5.3.13

Deposit a MOV R2, R3 instruction (0102035) into a memory location, followed by BR
.4
instruction (000776g).

Load the address of the MOV instruction.
Set maintenance card switches S1 and S2 for ROM CYCL operation.
Press START and then step through the MOV instruction that moves data from R2 to R3.

Upon completion of the instruction, press HALT and check the contents of general register
R3 for correct data (000002s).
When the correct test results are observed, this test verifies that the fork A and BRQ branch logic are
operating properly.
2.5.3.14
1.

Move-Immediate-to-Register Test

Deposit a move-immediate-to-RO instruction in memory, followed by a HALT instruction,
as follows:
Address

Contents

Symbolic

012700

MOV # 77, RO

X+2
X+4

000077
000000

HLT

Set DATA display select switch to DATA PATHS.

Execute the sequence deposited in Step 1. The immediate data, 775, should be displayed.

2-16

When the correct result is observed, the processor fork C logic has been verified to be operating
properly.
NOTE
The preceding tests check all the KB11-A, D logic
required to load and execute the initial diagnostic
program. When the correct test results have been
observed, load the diagnostic programs as described
in Chapter 6 of the KBI11-A, D Central Processor
Unit Maintenance Manual. These programs provide
a complete check of all KB11-A, D operations and
are listed in Chapter 6 of this manual. Run each
diagnostic as described in the related MAINDEC
program description.

2.6 CUSTOMER ACCEPTANCE
Verify correct system operation by performing the Customer Acceptance Procedures. The Customer
Acceptance Procedure document is shipped with the system, and lists all the tools, programs, and tests
required to certify correct operation.
A properly running system must be able to execute the system diagnostic program successfully without
error. These programs are loaded and run according to procedures described in the related Customer
Acceptance Procedure.

2-17

CHAPTER 3

POWER SYSTEM

This chapter describes the several versions of power distribution, both ac and dc, in the CPU cabinet.
The ac power system is described in Chapter 4, the dc power system in Chapter 5, and expansion
cabinet power in Chapter 8.
3.1
OVERALL SYSTEM DESCRIPTION
Figure 3-1 is a block diagram of the CPU cabinet power system. The basic components are two H7420

power supplies and their associated power control(s). AC power from the building mains is fed to the
power control unit(s), which provides two sets of ac outlets: one switched, the other unswitched. Two
H7420 power supplies are provided in the CPU cabinet; one is plugged into the switched power control
outlet, the other is plugged into the unswitched power control outlet. These H7420 power supplies are
designated upper and lower according to their mounting location in the cabinet (refer to Figures 1-1
and 1-2). Each H7420 contains a complement of voltage regulators, which depend upon the system
configuration.

The power system block diagram shows a typical complement of voltage regulators installed in the
appropriate slots of the upper and lower H7420 power supplies (Figure 3-1). Some voltage regulators
are supplied with the basic system and others are supplied as part of system options. The voltage
regulator complement for the basic system and options is summarized in Tables 3-1 and 3-2. Circuit
descriptions of each voltage regulator type are provided in Paragraph 5.2

The primary purpose of the switched supply is to provide dc power to the KB11-A, D and to the
options, other than semiconductor memory, that are installed in the CPU mounting box. The lower
H7420 subsystem (except for the H745 -15 Vdc regulator in slot F) is unswitched because it must
remain on at all times during normal operation to provide dc power to the optional MS11 Semiconductor Memory System, plus ac power to the logic fans and cabinet fans. The power supplied to
these components must not be inadvertently switched off because

3.2

If the power is switched off, the semiconductor memory contents are lost.

Other Unibus devices, or another processor, may be accessing the MOS or bipolar memories. Core memory is shut off (-15 V) via +15 V from the upper supply.

Fan voltage is required for cooling semiconductor memories.

115 Vac AND 230 Vac MODELS

The PDP-11/45, 11/50, 11/55 power system operates with 115 Vac or 230 Vac primary source power

inputs. The 861-A (CPU cabinet) or -C (expansion cabinet) or the 860-A power controls are used with
115 Vac source power and the 861-B or 860-B power controls are used with 230 Vac source power. The
differences between the power controls are described in Chapter 4. The H742-A or H7420-A power
supply is used with the 115 Vac source and the H742-B or H7420-B power supply is used with the 230
Vac source. Appropriate jumper connections are made at its primary input for operation on 115 or 230
Vac input power, as shown on drawing No. D-CS-H742-0-1, sheet 1, or D-CS-H7420-0-1, sheet 1.
3-1

fe——UPPER H7420 (OR H742) POWER SUPPLY SWITCHED ——»

fe—— BASIC SYSTEM—>]
15/

H745

230

20-30 VAC | H744 | H744 | H744 | HT744 |~ I8V or

SULK

POWER

OU?LETS

+5V | 45V | 45V | +5v |MTS2
A

SUPPLY

CONSOLE
LOGIC AND
POWER CONTRCL
CPU DC DISTRIBUTION
BACKPLANE

861
115/230 —
TWOPHASE | POWER CONTROL
f

)

| 1 1]

SWITCHED

POWER

ELAPSED BULK SUPPLY
TIME
AND REGULA
METER
FANS

115/230
Ineimenen
1157230

DISTRIBUTION

CABLE HARNESS

REMOTE

SYSTEM UNIT POWER

CONTROL

CONSOLE
SWITCH

DISTRIBUTION BOARD

THERMAL
CUT OFF
SENSORS

fe—— LOWER
LOW
a
w
H7420
(OR H742) POWER
SUPPLY UNSWITCH
UNSWITCHED—#}
115/

230

POWER

BULK

OUTLETS

ARLY MODELS EQUIPPED
WITH TWO 860POWER

CONTROLS

THERMAL

CUT-0FF

CONSOLE

SENSORS

SWITCH

CONTROL

860

|BIPOLAR|

H746

H744 |H744 MOS or
i85y | 45y {H744

[

UPPER AND LOWER

LOGIC FANS

[BIPOLAR

OPTIONAL

CONNECTORS

CABINET
FANS

BULK SUPPLY

AND

REGULATOR

FANS

ll 115/230 VAC —* bowER860
SWITCHED 115/ 230 I >
CONTROL

1157230 VAC =" oowER CONTROL

H745 MOS or
-15v |H744

SUPPLY

REMOTE

20-30 vAC

H746

NOTE:

Early models are equipped with two 860

power controls instead of one 861 power

control.

UNSWITCHED 115/230 I

11-4300

Figure 3-1

Typical PDP-11/45, 11/50, 11/55 Power System

Table 3-1

Type

Voltage Regulator Configuration Data CPU Cabinet Serial Numbers 2000 and Higher

Name

Quantity

Location

Comments

Basic System

H744

+5 V Regulator

+5 V to CPU modules slots 6—9.

+5 V to CPU and KT11-C, CD modules, slots
10-15.

+5 V to internal options, slots 26—28, systems

units 1, 2, and 3, and Console.
H745

-15 V Regulator

-15V to CPU and internal option modules and
to system until 1, 2, and 3, if slot E regulator is

a H754. This supply is switched, even though in
the lower H742, because it is fed by +15 Vdc from
the upper H742.
FP11-B, C Floating-Point Processor

H744

+5 V Regulator

+5 V to FP11 modules, slots 2—5.

MS11-A, C Bipolar Memory
H744

+5 V Regulator

+5 V to control and first two matrix modules

(slots 16—18).
J

+5 V to third and fourth matrix modules

(slots 19-20).
2

+5 V to control and first two matrix modules

(slots 21-23).
L

+5 V to third and fourth matrix modules

(slots 24—25).
MS11-B MOS Memory
H744

+5 V Regulator

+5 V to control and matrix modules, slots 16—-25.

H746

MOS Regulator

H,L

+19.7V,+23.2V, and -5V to MOS matrix
modules; H slots 17—20; L slots 22-25.

MM11 Core Memories and Controls

H745

-15 V Regulator

-15 V to Systems Units 13 (if MF11-UP is not
installed).

H754

+20,-5V

+20 and -5 Vdc to MF11-U/UP.

Regulator

3-3

Table 3-2
Type

Voltage Regulator Configuration Data CPU Cabinet Serial Numbers Less Than 2000
Name

Quantity

Location

Comments

Basic System
H744

+5 V Regulator

+5V

CPU

modules,

slots

6-9.

+5 V to CPU and KT11-C, CD
modules, slots 10—15.

+5V to internal options, slots

26—28, system units 1, 2, and 3,
and Console.
H745

-15 V Regulator

-15V

CPU

and

internal

option modules and system units
I and 2.

FP11-B, C Floating-Point Processor
H744

+5 V Regulator

+5V

FP11

modules,

control

slots

2-5.

MS11-A, C Bipolar Memory
H744

+5 V Regulator

H,J

+5V

and

matrix

modules if no MOS memory is

installed,

or only 4K is used.

H: slots 16—18;
J: slots 19—20.

K,L

If MOS memory is also installed,
or if more than 4K of bipolar is
used. K: slots 2123, L: slots
24-25.

MS11-B MOS Memory
H744

+5 V Regulator

+5V

control

and

matrix

modules, slots 16—25.

H746

MOS Regulator

H,L

+19.7V, 4+23.2V, and -5V to
MOS

matrix modules; H slots

17-20; L slots 22-25.
MM11 Core Memories and Controls
H745

-15 V Regulator

-15V to System Unit 3. H745
provided in basic system supplies
System

Units

and

This

supply is switched even though

in the lower H7420, because it is

fed by +15 Vdc from the upper
H7420.

3.3
DIFFERENT POWER SYSTEM VERSIONS
The CPU Cabinet Power Distribution System exists in four versions. The types of power control,
harness, and supply used in the CPU cabinet determine the version of power system. Table 3-3 lists
each version. The first version includes two 860 power controls, a 7008784 power harness and a H742
power supply. The two 860 power controls were then replaced by one 861 power control to generate
the second version. A different power harness was then utilized, when CPU cabinet serial number 2000
was produced, to generate the third version. The latest version contains the previous revisions and a
different power supply - the H7420 instead of the H742. Figure 3-2 shows a pictorial representation of
the second and third versions. Figure 3-3 shows a pictorial representation of the first and second
versions.

Each 11/45 or 11/50 uses one ofthe four versions of the power systems. The 11/55 uses only the most
current power system version (4th).

Table 3-3

Power System Versions

Power System Version

Power Control
Power Harness*
Power Supply

Ist

2nd

3rd

4th (Current)

(2) 860
7008784
H742

861
7008784
H742

861
7009540
H742

861
7009540
H7420

Below CPU cabinet

Above CPU cabinet

serial numer 2000

serial number 2000

*Power harness of the CPU cabinet. Note the entire power system uses a number of power harnesses.

3-5

7009540
HARNESS

UPPER*
H7420

5410590
POWER DISTRIBUTOR

(TO SYSTEM UNITS)

)

P13(TO FANS &
THERMAL

H7420%
861 POWER

9-¢

CONTROL

UNSWITCHED

~I_
/‘ ~

SYSTEM

UNITS
J2

Jgg

d:u\lb\b\tn\r_‘::l\

/:,—_,

J8 f K g
i

J21

CcPU

BACKPLANE

TM10

J19

J20

J17

E\ b N B\

\D\’EI

J16

J14

\\u\\

UPPER
H7420
TOP VIEW

PIN SIDE VIEW

J29
OR
J30

J27

J25

J74

Ly T aNe

\fl

*Early power system versions {1st,2nd, and 3rd)

J22

| Lower Hrazo
NN

TOP VIEW

uses H742 power supplies.

J28

J26
OR
J31

J23

Figure 3-2 Newer Versions (3rd and 4th) of Power System;
CPU Cabinet Serial Numbers 2000 and Higher

11-4350

i 860 POWER CONTROLS

7008784
HARNESS

ffi¢}c;>

RN
36

POWER UNSWITCHED
861
CONTROL

'{/’
unnm
F

LOWER

H742

549903

L -

DISTRIBUTION
POWER

~I_ !

(TOSU, FANS &

THERMAL SWITCH)

/'\\

UNITS

43 J4 J5 U6 J7

J29

J8
49|

J1
CPU

BACKPLANE

PIN SIDE VIEW

J19

J20

J10

J16

J18 \ J15

D\ c

/ J14

B\\:

UPPER H742

\fl\J\\n\‘flN
J29

J27

425

TOP VIEW

J2a

J22

% |

Lower H742

L ! kYJ
\fl
\\{1 |H ‘KLE

J28

J26
OR
J31

TOP VIEW

J23

Figure 3-3
Early Versions (1st and 2nd) of Power System;
CPU Cabinet Serial Numbers Less Than 2000

11-2292

CHAPTER 4
AC POWER DISTRIBUTION

This chapter contains information relative to ac power control and distribution in the PDP-11/45,
11/50, 11/55 CPU cabinet. Input specifications for ac power are discussed in Paragraphs 1.1.2 and
2.2.4, Appendix C lists ac power requirements for the various components of the PDP-11 system.
4.1

PRIMARY AC POWER OUTLETS

4.1.1
Primary AC Power Outlets, 861 Power Control
The type of input power cable provided depends on which version of the 861 power control is being

installed (see Table 4-1). Cables supplied with all versions are 15 feet long and composed of insulated
stranded conductors. The power cable connector types provided also differ depending upon which 861
version is being installed. Table 4-2 lists the plug and receptacle types with NEM A, Hubbell, and DEC
designations. Figure 4-1 illustrates the power connector outlines and provides color coding
information.

Table 4-1

Input Power Cables

Control

Conductors

Size

Coding

861-A

#12 AWG

Green, black, white, red

861-B

#14 AWG

Green, black, white

861-C*

#12 AWG

Green, black, white

*Used on peripheral cabinets.

Input Power Cable Connections

Table 4-2
Model

No.

NEMA
Configuration

Description

861A

L14-20*

120V, 29,20
A

Poles | Wires

PLUG
DEC # | HUBBELL #

RECEPTACLE
DEC # | HUBBELL #

12-11045

2411

12-11046

2410

120V, Split

phase, 20 A
861-B

860-B

861-C

S60-A

L6-20*

240V,1¢9,20A

12-11192

2321

12-11191

2320

L5-30*

120V, 1¢,30A|

1211193 |

2611

12-11194 |

2610

* Add Suffix “P” for plug, “R” for receptacle

RECEPTACLE

PLUG

PHASE 1

RED
X

WHITE
EARTH

_..‘
w

GREEN
G

GROUND
Y

PHASE 2

NEMA L14 - 20R

BLACK

NEMA L14-20P

Used with the 861-A Power Control

PHASE

OR
NEUTRAL

(NEUTRAL

PREFERRED)

WHITE

PHASE OR

BLACK

y
GREEN

EARTH

GROUND

NEUTRAL

NEMA L6-20R

EARTH

GROUND

(E L
\

WHITE

BLACK

PHASE

NEMA L6-20P

Power Control

WHITE

NEUTRAL

NEMA L5-30R

Used with the 861-C Power Control

Figure 4-1

Used with the 861-B

GREEN G

GREEN

NEMA L5-30P
11-2293

Power Connectors

An 861-A must be supplied with two power phases that are displaced by either 180° (120/240 V split
phase) or 120° (two phases of a 120/208 V 3-phase Y). The same phase must not be connected to both
X and Y terminals because this would cause current in excess of 20 A to flow through the neutral wire,
causing the circuit breaker to trip. Figure 4-2 shows the proper connections for an 861-A power
control.
861-B and 861-C power controls use the plugs and receptacles shown in Table 4-2; these are wired as
shown in Figure 4-1.
4.1.2
Primary AC Power Outlets, 860 Power Controls
Primary power outlets at the installation site must be compatible with the primary power input con-

nectors. The PDP-11/45, 11/50, 11/55 requires two recepticles — one for the 860 power control associated with the switched H742 power supply, and one for the 860 power control associated with the
unswitched H742 power supply. Table 4-2 describes the plugs and receptacles used with the 860-A and
860-B power control units. Figure 4-1 shows the outline of the plugs and receptacles and the connections to them. (Plugs and receptacles of the 861 are the same for the 860.)
4.2

AC POWER CONTROL
Power from the building mains is applied to the system components in each cabinet through power
control unit(s). These units are interconnected to allow power in all the cabinets of a system to be
controlled from the console (power ON/OFF) or from emergency shut-down devices (OFF only).
Interconnections are explained
in Paragraph 4.2.1, and the power control units in Paragraph 4.2.2.
4-2

I POWER LINE

TRANSFORMER

| POWER LINE

TRANSFORMER

ul
|2

WATE

120V

[

ZL = | 120V
Y

G
L

|
I

|
!

X GREY
G

I 120V

| \L

°
W

GREEN
SAFETY GROUND

{a) 120/240V Split-Phase { Two Phase)

Figure 4-2

WHITE

208V

OR GRAY

—

11-2294

Two-Phase Outlet Connections for Use with 861-A Power Control

4.2.1

Remote Power Connections
Each cabinet in a PDP-11/45, 11/50, 11/55 system has one 861 or two 860 power controls. All the
power controls are connected by a 3-wire bus that carries a remote turn-on signal (line 1), an emergency turn-off signal (line 2) and a control ground (line 3). These signals appear on pins 1, 2, and 3,
respectively of the power control’s J1, J2, and J3 connectors. Operation occurs as follows:
.

Connection between line 1 and line 3 energizes the power control relay and applies power to
the components under control. When the LOCAL/OFF/REMOTE switch on the power
control is in LOCAL, line 1 and line 3 are connected.

Connection between line 2 and line 3 overrides all other conditions to disconnect input
power to the components under control.

If no connection exists between either lines 1 or 2 and line 3, the components will remain in
the power off state unless the LOCAL/OFF/REMOTE switch is in LOCAL.

Refer to Figure 4-3. Three identical paralled-wired Mate-N-Lok connectors are provided on each
power control. A cable, DEC part number 7008288, is supplied with each cabinet to connect the power

control of that cabinet to the power control in the next cabinet. Because each power control must be

capable of connecting to the power controls in the preceding and following cabinets, two Mate-N-Lok
connectors are reserved for the intercabinet cables; a third connector is provided for connection to

thermal switches and other shut-off devices within the cabinet.

The 3-wire power control cable, DEC part number 7008288, can also be used to interconnect H720
power supplies. A special power control cable, DEC part number 7008964, is used to connect an 860 or
861 power control to an H720 power supply. This cable is available for use with special multiprocessor

systems that include both a PDP-11/45, 11/50, 11/55 and a PDP-11/15 or a PDP-11/20.

4.2.2

Power Controllers
Circuit schematics of the 861-A, 861-B and 861-C power controls are included in the engineering
drawing set (D-CS-861-A-1, D-C8-861-B-1, and D-CS-861-C-1). (Figure 4-8 shows circuit details of
the 860 power control used in early systems.) Two identical 860 power controls are used in each
cabinet, one for the switched, and one for the unswitched power supplies.

Table 4-3 summarizes the operation of the power controls.

A detailed description of the 861 and of the 860 circuitry is given in the following paragraphs.
4-3

SWITCHED

UNSWITCHED

POWER

CONTROL

f123]

P32/ P33/
HARNES S &

123]

7008784

X—AC OUTLETS—*

860/861

11
860/861

L - e— q
THERMAL

r——-|

SWITCH

- — =1

,
|

SENSOR

OFF9"

CONTROL

“549903 POWER
DISTRIBUTION

1
860/861

|\123l

7008288

TT\CABLE
J1|2

| 3|

| |(OPTIONAL)
H720E,F KR
|
Jal2 }:

POWER

CONTROL

\123]

t123|

{12
3]

]

1
2

|Jd2

H720E ,F E E

]

{OPTIONAL) | 3

BOARD

(CONSOLE

(N.O)

CABINET
# 2

——————— J

sat1-Fa

ADDITIONAL

|
|

P/0!

li 2 3]

AC INPUT —-———:‘j

]

5
3

L123|

]

M\W

POWER

|
|

[123]

| 111

P13

P/O P

;

|
|
|

H742(0)
LOWER
SUPPLY

CABINET
# 1

e e

H742(0)
UPPER
SUPPLY

ADDITIONAL

CABINET

INPUT

———e

PROCESSOR

|ock

|
|

POWER

$11-22956

Figure 4-3

Example of Remote Power Control

Table 43

Power Control Operation
SWITCH POSITION

CONNECTIONS

LOCAL

OFF

REMOTE

BETWEEN CONTROL

SWITCHED

LINES

POWER IS

POWER IS
OFF

NONE

OFF

1-3

OFF

2-3

OFF

1-3, 2-3

OFF

4-4

4.2.2.1

861 Power Controls — There are three versions of the 861 power control:

e 861-A, 90-135 Vac, 2 phase, 32 A (20 A circuit breaker)
e 861-B, 180-270 Vac, 1 phase, 16 A (20 A circuit breaker)
e 861-C, 90-135 Vac, 1 phase, 24 A (30 A circuit breaker)
The following paragraphs describe the operation of the 861 power controls in general terms; Figures 44A, B, and C are simplified schematics of the three 861 models.
861 Operation - Refer to Figure 4-4. Power is applied to the terminal block mounted on the power line
filter, which is an L-type L-C filter with series RF chokes and shunt capacitors to ground. If the rated
voltage is present at the indicator terminals, I1 and/or 12 light. All ac lines are connected to elements at
the circuit breaker CB1. All loads connected to the power controller (both switched and unswitched)
are controlled by CBI.

Yl"—_""fi""——'l

rcer |

——————I—I

AC INPUT

L14-20P

|
I
|

| C)
|

D |

| |L lfi |

208

o
'
|

1
1
re_——-J]
|

__; =

T WF 7Rk TRARF |

e
e e = e o

r—=

1
r
I 208 1
L—__d

|
1
|

G| R

20n

colL

\—< 2¢

)

|
|

50uF

(3¢

,
a¢ y

=
Pt
D4

|
|

]

I
I

¥y03

REMOTEl
LOCAL
i
ON OFF

afv

Figure 4-4

wefv2

I R

ROL
|__< _ IPiLoT CoNTBOARD

wsfr2 3]

B861-A

861 Power Controller Schematic (Sheet 1 of 2)

|°13|oeI2T251=-RS

2¢To<L2N-EeesW1oc3NEse--NeSeWRe—I “|<Lo~-EsJllItlil©l—'Ir.
-

a28 ‘- 5 _ ——e-e—

K1
IL
1T

6—O

__T__

3 5

]mw“||]1|J%a=O—|“s®,¢mnb1IR|!3

I
11

—~

AC INPUT
L6-20P

®-

LFa)—

T YT i

lHH!E

J2L1

|
s3]

E—

PHASE

17T

ACINPU

LJE ;%

(3)

IFH!F

()

4| g 8 I,

L5-30P

| I\

sft

Figure 4-4

vz1 23]

J3| 1

861-C
C.
861 Power Controller Schematic (Sheet 2 of 2)
4-6

CP-0357

If the current through any of the ac lines exceeds the rating of CB1, CBI trips, removing power from
the loads. Power outlets P1 and P2 connect across the circuit breaker output. These outlets are energized whenever the circuit breaker is closed. Each outlet line from CBI is connected to a normally open
contact on relay K1. The field coil associated with K1 is energized by the output of CBI if a relay on
the pilot control board is closed (see below for a description of the pilot control board).
When K1 is closed, ac power is applied across outlets P3, P4, P5, and P6. The two 0.1 uF capacitors

(CI) connected across the lines at the relay reduce the amplitude of voltage spikes at the output of the
controller when switching inductive loads, thereby preventing interference to nearby electronic data
processing equipment.

Pilot Control Board Circuit Description — Figures 4-4A, B, and C illustrate the pilot control board

simplified circuit schematic. The pilot control board contains the circuitry that allows remote turn-on
and emergency turn-off of the switched power outlets (P3, P4, P5, and P6) in all 861 power controller
versions. These functions are accomplished by controlling the voltage applied to the field coil of relay
K1 in the 861 power controller.
The circuit consists basically of a full-wave rectifier loaded by the center-tapped field coil of a relay.
Three control lines connect to the board. Pin 3 connects to the center-tapped secondary of the full
wave rectifier transformer. Pin 2 is the disable (emergency shutdown) line from the signal bus; pin 1 is
the enable (power request) line from the signal bus. Two additional lines (from the thermal switch) are
connected to the lines associated with pins 3 and 2.

When the LOCAL/OFF/REMOTE switch is in the REMOTE position and pins 3 and 1 are connected, current flows through the lower portion of the center-tapped relay field coil to the full-wave
rectifier transformer. This action closes the relay on the pilot control board and causes an energizing
potential to be applied across the field coil associated with K1 in the power controller energizing the
controlled outlets P3, P4, P5, and P6. When pins 3 and 2 are connected (emergency shutdown is true),
current flows through the lower and upper halves of the centertapped field coil in opposite directions
before returning to the power supply transformer. The resultant current through the field coil is less
than that required for holding the relay closed. Energizing potential, therefore, is not present at relay
K1 and power is removed from controlled outlets P3, P4, PS5, and P6.

Diode D2 provides a current path in the lower section of the coil to prevent closing the relay in
instances where pins 3 and 2 are connected but pins 1 and 3 are not.
Closing T1 (the thermal switch) performs the same function as emergency shutdown (connects pins 2

and 3 together). This switch is exposed to the ambient air surrounding the power controller. Temperatures above 160° F close the switch (disabling P3, P4, P5, and P6). The switch resets automatically
when the temperature drops below 120° F.

Placing the LOCAL/OFF/REMOTE switch in the LOCAL position provides a connection between
pin 3 and the lower portion of the coil to energize K1, regardless of the state of the power request line
on the signal bus. This switch position is normally used for maintenance purposes; operations on the
pilot control board are exactly the same for situations where a connection is provided between pins 3
and 1 of the signal bus connector due to closing of a circuit in an external device. A connection
between pins 2 and 3 disables the switched outlets regardless of the position of the
LOCAL/OFF/REMOTE switch.
The power supply that provides the potential for closing the relay need not be returned to ground. It

can be operated in a floating configuration where a connection between pins 3 and 2 (as by the thermal
switch or emergency shutdown) disables the switched outlets and a connection between pins 1 and 3
(power request) enables the switched outlets.

4-7

4.2.2.2 860 Power Controls — Figure 4-8 shows circuit details of the 860 power control for the switched power supply. Either an 860-A or 860-B power control is supplied, depending on the power source
voltage. The 860-A operates with 115 Vac input power, and the 860-B operates with 230 Vac power.
The basic differences between these 860 types are that:

CBIl is a 30 A circuit breaker in the 860-A and a 15 A circuit breaker in the 860-B.

TI primary is connected for 115 Vac in the 860-A and 230 Vac in the 860-B.

The 860 power controls for both switched and unswitched power supplies are identical.

The T1 secondary voltage is half-wave rectified to provide +24 V, which is used to provide Vcc to
control transistors Q1 and Q2, and to energize relay K1. The +24 V output of each 860 is used to
energize the K1 relay in the opposite 860 power control. The purpose of this interlock circuit is to shut
down either power supply if input power to the opposite subsystem fails.

4.2.2.3 Switched 860 Power Control — In the switched 860 power control REMOTE/OFF /LOCAL
switch S1 is normally set to REMOTE. When the console POWER switch is turned to ON, it completes a ground circuit that causes Q1 to cut off. When Q1 cuts off, Q2 conducts and causes relay K1 to
be energized, which closes the switched output circuit. Other connectors are provided on the 860 power
control so that power in other system cabinets can be controlled from the console.

Thermal switch 52 provides protection against fire or excessive heat. It is normally open but closes if
the ambient temperature exceeds 130° F (54° C). If it closes, Q2 cuts off, relay K1 de-energizes, and ac
output is switched off. Pin 2 on J1, J2, and J3 allows additional thermal switches in the cabinet and the
extension mounting box to be connected in parallel with S2 to perform the same function.
4.2.2.4 Unswitched 860 Power Control - The unswitched 860 power control is identical to the switched power control except that the REMOTE/OFF/LOCAL switch Sl is always set to LOCAL. Thus,
Q1 is always cut off, Q2 always conducts, and K1 remains energized under normal operating
conditions.

Note that only excessive temperature or an input power failure to the switched 860 power control will
cause unswitched power control relay K1 to de-energize.

BACK-UP AC POWER SOURCE FOR SEMICONDUCTOR MEMORY

The semiconductor memory (MOS or bipolar) offered on the PDP-11/45, 11/50, and 11/55 is volatile
(i.e., stored data is not retained when power is removed from the memory). For those applications that
require data to be retained in the event of ac power failure, it is necessary to provide a back-up source
of power. In the event of power line outage, brown-outs, etc., this back-up source will supply minimum
power to only the memory sections, cabinet fans, and CPU fans until power can be restored. This
guarantees that data stored in this memory will not be lost; however, system power must be restored
before the data can be accessed.

Figure 4-5 is a simplified diagram of the power system in the CPU cabinet of the PDP-11/45, 11/50,
11/55 with a back-up ac power source. Note the power source must be installed to suply ac to the CPU
fans and cabinet fans and dc supply for the semiconductor memory in the event of a power line failure.

Although a back-up ac source is not available through DEC, the back-up source employed for this
application must meet or exceed the ac line specifications listed in Table 4-4.

4-8

fe——BASIC SYSTEM——|
nsS/

_ .

H745

VA | H74
20-30
O-30VAC
4 | H744 | H744 | H744 -I15Vor
W7

230

+5V | +5V

BULK

POWER
OUTLETS

SUPPLY

+5V

+20-5V
;

—»

DC TOCPU LOGIC

DCTOCPU LOGIC &

SEMICONDUCTOR

YY)

SWITCHED

115/230
861
TWOPHASE| POWER CONTROL

115/230
b

ELAPSED BULK SUPPLY
. TIME = AND REGULATOR
FANS
vcocien

UNSWIICHED

1157230

REMOTE
CONTROL
CONSOLE
THERMAL
SWITCH
CUT OFF

SENSORS

fe———LOWER H7420 (OR H742) POWER SUPPLY UNSWITCHED—|

6-v

—>

POWER
OUTLETS

115/
230

20-30 VAC

BULK
SUPPLY

H745

H746
MOS or

|H744

|HT44

H746
MOS or

|BIPOLAR|

|BIPOLAR

-15v

|H744

|45y | t5v | H744

MEMORY.

NOTE:

Back-up ac power source supplies power
to semiconductor memory and corresponding

[ Y 1)
BACK-UP

BULK SUPPLY

AC POWER

AND

SOURCE

fans during power-fail.

REGULATOR

FANS

CABINET FANS
11-4364

Figure 4-5

Power System Configuration with Back-Up AC Power Source

Table 4-4

Back-Up Source Specifications Requirements

105-130 Vac

Output Voltage

210-260 Vac
Output Frequency

47-63 Hz

Output Power

2000 VA (minimum)

Output Voltage Dynamic Variation

Maximum: +£10% of nominal voltage (duration <O0.1
second occurring less than once every 10 seconds)

Output Harmonic Distortion
Total

<5% maximum of fundamental

Single Harmonic

< 3% maximum of fundamental

Output Transients
Peak Voltage

<#£300 V (differential and common mode)

Energy

<0.2 watt-second

Average Power

<0.5 watt

Single Transients
Peak Voltage

<+600 V (differential and common mode)

Energy

<2.5 watt-second

(non-repetitive)
Output Current

20 Arms (minimum)

Load Inrush Current

Peak Current

+300 A (duration < ms, steady state >50 ms)
NOTE
If the input current of the back-up supply exceeds the 861
power control limit, provisions must be made for a separate ac source for the back-up supply.

4-10

Table 44

Back-Up Source Specifications Requirements (Cont)
861-A

861-B

861-C

Voltage

105-130 Vac

210-260 Vac

105-130 Vac

Phase

Two (120° or

Single

47-63 Hz

Per Outlet

12
A

12A

Per Branch Circuit

16
A

Total

32A

861 Power Control Output Limits

180° dis-

placed)
Frequency

Outlet Current

16
A
16
A

24
A

Outlet Inrush Current
(peak, 1 cycle)

Per Branch Circuit

A
240

Total

430 A

240 A
240 A

360 A

AC POWER DISTRIBUTION

Figures 4-6, 4-7, and 4-8 show the ac connections for various power controls, power supplies, and fans.

Figure 4-8 shows the connections of two 860 power controls and two H742 power supplies. Figure 4-7 |
shows an 861 power control and two H742 power supplies. The most current power system is shown in
Figure 4-6 which consists of an 861 power control and two H7420 power supplies. In all three varia-

tions, any options that require an ac input are also plugged into the power control ac outlets.
Refer to Figures 3-2 and 3-3 for a pictorial view of the power connections.

4-11

—_—————————————————q

POWER
*861
CONTROL

UPPER H7420 POWER SUPPLY

REFER TO D-CS-H7420-0-1

l
N\

[
o
w1

LINE

PLUG

861-A:NEMA L14-20P

CONNECTOR

REFER TO CIRCUIT
SCHEMATIC
D-CS-861-A-1
D-CS-861-B-1 OR

861-C . NEMA L5-30P CONNECTOR

ON 861

OUTLETS ARE INDICATED BY PANEL
MARKINGS.

POWER CONTROL

|
|

| OFF

L POWER

wek[

|
|

— - — -]

_____

UNSWITCHED

PHASE1 CIRCUIT1

- —

P13-6
P13-5

(N.O)

2
.

ON DRAWING D-I1C-11/45-0-1

CABINET
_—

NI
!
!

PART OF

POWER DISTRIBUTION
HARNESS

TIME

p34

METER

5|5

2 ‘; 3

FRONT

V\“/\

FAN

L L] E

2|7

G T CEIEEED IS S J

Fa
FANS

REAR

GROUNDED

| |

AT TB

TERM 2

ELAPSED

0/0

FAN

KEY 2

TERM |

SECONDARY WINDINGS SHOWN

]

REGULATOR

KEY
1

2
P33[J3

CABLE

3 § .:

SWITCH

THERMAL

CABINET FAN HOOK UP 115V & 230V

CONNECT TO

S
; I

—'

P32]J2

—— -

PHASE

Pi-3
-

LOGIC

‘l_

63Hz SINGLE

861-B:230V/47-63Hz
SINGLE PHASE
861-C.: 90-135v/47-

SWITCH

63Hz 2PHASE (120°
OR 180° DISPLACED)

| KEY

TO SWITCHED
|CONNECT
PHASE1 CIRCUIT2

%x861-A:90-135Vv/47-

MconsoLe

D -CS-861-C-1

SWITCHED AND
UNSWITCHED AC

861-B: NEMA L6-20P CONNECTOR

=! c1

' 1

T81

cB1

LOWER H7420 POWER SUPPLY

REFER TO D-CS-H7420-0-1

cB1

TO SWITCHED
| CONNECT
PHASE2 CIRCUIT1
|

ON 861
POWER CONTROL

e e e

1
=

.|
!

e —— e — —

“go2

3
4

c2=
I
4/,\“2

T1 |

! c1a= §M
|T

!
|

' 1

l
'

TB1

i
I

) +

——————

P/0

J2 Ple

51°%

2| | Fans

616

S SHOWN
RY WINDING
| ONSECONDA
ey
o
0-1
DRAWING D-1C-11/45-

3|3

TOLosic

7|7

REGULATOR

FANS
11-4304

Figure 4-6

AC Power Interconnections

(H7420 and 861)

4-12

lupPER
PPER H742
H742 POWER
POWER supPLY
SUPPLY
|

REFER TO

*861

POWER

CONTROL

BLK

/
LINE

GRN

PLUG

SCHEMATIC

D-CS-861-A-{

D-CS-861-B-1 OR
D-CS-861-C-1

CONNECTOR

SWITCHED

452

ONSWITCRED AC

L5-30P CONNECTOR

a<.

é: ; "\ | CONNECT TO THE SAME
o

UNSWITCHED LINE (LINE 1

POweR

»TO?

THERMAL
SWITCH

et S
2

1 ;{(5)

6|6

on 861) AS THE

TIME

METER

LOWER

H742 (FOR 230Vac

IN SERIES)

]

MLOWER H742 POWER SUPPLY

(See note)

|
|

REGULATOR FANS

3. | |

[ ¢y

~ouF

—————

LOGIC

|
|

OPERATION CONNECT FANS

63Hz SINGLE

Pi1-3
3|KEY2
/—psz —

i
Fi

861-C: 90-135V/47-

11
=

)

>(T:gchl)r\éGCFAAB'\:EJET

)

&/?mr

861-8: 230V AT E3Hz

I
OFF
|

CONNECTED

| || TO REGULATOR

IN-

gmggm“'s‘

PHASE

WINDINGS

PHASE (120°

1 key|

3+ ||

L—— — et —————————'

%861-A:90-135Vv/47-

S Rl

ZI\—4'3

I
I

2 | || SECONDARY

| CONNECTOR

DICATED BY PANEL

IKEY
SWITCH

T~ 0.4uF

—

AND

OUTLETS ARE

—————

O.1uF

_L_—:_m

. T T

T1
1,|

REFER TO cIiRcuIT | | SA‘g'gg;*,Eg

861-C : NEMA

(See note)
—

50 Anv

861-B:NEMA L6-20P CONNECTOR
-

CONNECT

WHT
861-A:NEMA L14-20P

T81

CB1
31

{

D-CS-H742-0-1

SECONDARY

CONNECTED

WINDINGS

TO REGULATOR

P13-6

—— el ==
1

|2|TERM1

—_———
e

P13-5

—

(N.O}

P33]J3

4 _l_

TERM
2

‘

'(LINE 1ON 861)

( SEE NOTE ON 7OP OF CABINET FANS)

1
PART OF

POWER DISTRIBUTION
CABLE HARNESS

b e e e e e e

NOTE:

FOR 115Vac OPERATION

JUMPER TB1-182,TB1-384 (H742-A)
FOR 230Vac OPERATION

JUMPER TB{-283 (H742-B)

Li
O+

.—P/O———-—-l

J2 P23

s]s]y

6le

3|3

L_ S

TO LOGIC FANS

F31

REGULATOR

FANS
11-1699

Figure 4-7

AC Power Interconnections

(H742 and 861)

4-13

—

DASHED LINE ENCLOSES 860 POWER CONTROLS AND COMPONENTS

| USED ON EARLY PDP-1i/45 SYSTEMS
I

860 POWER CONTROL UPPER POWER SUPPLY

860B: 230Vac/ 50Hz

AC POWER

860A: 115Vac/60Hz

BLK

115/230Vac

GRN

— ] ReD

WHT

WHT [

(SWITCHED)

CB1

_
|

3 T~

RED

WHT

35 !o8

°e
1

8604 .: 30A

<—RED

BRN —~

ORN

LA‘L)&

° 11 °
|
1

8608: 154

CONNECTORS

TBI

BLK

WHT

)

YEL

M——

P/0 POWER

_____

FeonsoLe
ISWITCH
I

OFF

| POWER

Losic

SWITCH

THERMAL

—

—_

Stocx |

_____

! l‘ TM Pi-a_ KEYY (o1
|
| —e
:(3I—¢
PI-3 KEY2
—

KEY

DISTRIBUTION

CABLE HARNESS

D10 Q2
t+w

- —
——

P13-5 TERM 2

SWITCH

47-63 Hz

l
|

—

Ot
e

UNSWITCHED AC POWER CONNECTOR.

115Vac

j’—\\

< |
@ I

°[°

He o0

sle

3|3

METER

FANS
COOLING
TOP OF CABINET
230Vac

()
\_/

|
|

COOLING FAN

TOP OF CABINET

el — — — J

P/0
£El5

REGULATOR FANS

—_—— —

——1

il—e

[

q‘; |

3 6

I
1

JJ4

Il LOWER H742 POWER SUPPLY

)

]

LI lva

[
[
TO
PC-9 PC-10

AC POWER

|
K1

CONNECTORS
P1-P9
B

+24v TO

(UNSWITCHED)

BLk

GRN

wnr_|

GRN 1,

SAME TYPE AS ABOVE (860A OR 860B)
S11S ALWAYS SET TO LOCAL
REFER TO C—CS-860-0-1 FOR
COMPLETE CIRCUIT SCHEMATIC

”

{See—note)

1.T

25 ||

e
4
4]

—0 | O

2
TO ANY
UNSWITCHED

CONNECT

!
4532

otaF

YT o
2

]
:
I

]

I
| NOTE :

1
Ly

"‘O“"

seconpary

|| To REGULATOR |
L=
|
!

2 o — —J
" E/Z%
L reTe]

—s|s

313

FOR 115Vac OPERATION

5. || Connecren

IICONNECTOR

Il_- — e ——— — ——— _.'

AC POWER

TB1

cBi
3T

!
M1

BLK
WHT

3.1 ! || CONNECTED
TO REGULATOR

OPEN

SI|NGLEPHASE

NORMALLY

860 POWER CONTROL LOWER POWER SUPPLY

115/230Vac

2 %I

THERMAL

CONNECT COOLING FAN TO ANY

|
|

| 4

TO ANY

[

i E—

iyT

P33 )uz
PI3-6 TERM 1

Ras

9
T

40/'—\02

l CONNECTOR

!
!|
||

AC POWER

D3 <[s
g

(See :note)

CONNECT

TBY

CBi

35T

SWITCHED

& b %5

REFER
TO D-CS-HT742-0-1

)

]

|'["UPPER H742 POWER SUPPLY

P1-P9

70 LOGIC FANS

717

JUMPER TB1-182,TB1-384 (H742-A)
FOR 230Vac OPERATION

REGULATOR

JUMPER TBi-283 (H742-B)

FANS

11- 0985

Figure 4-8

AC Power Interconnections
sw

wam

4-14

CHAPTER 5

DC POWER DISTRIBUTION

This chapter explains the distribution of dc power through the power harness and the configuration,
and theory of the regulators.
5.1
DC POWER DISTRIBUTION
The outputs from the switched and unswitched power supplies and the voltage regulators are applied

through the power distribution cable harness to the CPU backplane, the system unit power distribution board, and the console. The ac power is also supplied through the power distribution cable
harness to CPU mounting box logic cooling fans; this ac power distribution is schematically shown in
Figures 4-6, 4-7, and 4-8.
5.1.1

Power Distribution Cable Harnesses

Figures 5-1A, B, and C illustrate the revisions to the 7009540 power harness for CPU cabinets with
serial numbers 2000 and higher. Figure 5-2 illustrates the earlier version of the harness (7008784) for
CPU cabinets with serial numbers below 2000. Table 5-1 relates the various revisions of the harness to
ECOs and specific hardware modifications.
The power distribution cable harnesses consist of three distinct connector groups that connect to the
upper power supplies, the lower power supplies, and the CPU backplane and console, as shown in
Figures 5-1 and 5-2. In these figures, the power harness connectors are designated with a “P”’ prefix;
e.g., P1, P2, etc., whereas the connectors that are mounted on the bulk supplies, regulators, back panel,
etc., are assigned a “‘J” prefix. The power harness used the male (P) half of the Mate-N-Lok connector(s), and the bulk supplies, regulators, etc., use the female (J) half of the connector(s). When a
connector reference appears in the text, a ‘““‘P” designation (P1, P10, etc.) refers to the power harness,
and a ““J”’ designation refers to one of the female connectors mounted on the bulk supplies, regulators,
back panel, etc.
S5.1.2

Backplane Power Distribution

The bulk power supply and individual regulators supply dc power, and apply it via the power harness
to the ten connectors (J2 through J11) on the backplane, to the connectors on the system unit power
distribution board, and to the console. The harnesses that distribute this power are shown schematically in the engineering drawings.

5-1

VOLTAGE

=15V JUMPER
CONNECTOR

INPUTS
=~

aicioin

——

TO FANS AND
THERMAL

|P45|J45|

TO BACK
PLANE &+
CONSOLE

)
T0

CONSOLE

[ = B
GROUND

P12
)
v

INPUTS

TO SYSTEM
UNIT POWER
DISTRIBUTION
BOARD

CONNECTED
BULK

SUPPLY

—

P14

P15

UPPER

SWITCHED
]

POWER
ASSEMBLY

)

T AP
:

S
CONNECTED TO

TO BA11-FA
THERMAL
SWITCH

REGULATORS
CONNECTED TO
BULK
SUPPLY

LOWER
UNSWITCHED
|
POWER
ASSEMBLY

EEE
CONNECTED TO

ELAPSED

REGULATORS

TIME METER
11— 2575

Revision F and H

Figure 5-1
Power Distribution Cable Harness 7009540,
CPU Cabinet Serial Numbers Greater Than 2000 (See Table 5-1) (Sheet 1 of 3)

FROM
861
POWER
CONTROL

~15V JUMPER
VOLTAGE

CONNECTOR

INPUTS

]
TO

BACK

PLANE afi

ee|

CONSOLE

r—_/;_\

[o7]

|P45 [J45]

TO FANS AND
THERMAL

CONSOLE

] [0 B9 [

GROUND

INPUTS

—
TO SYSTEM
UNIT POWER
DISTRIBUTION
BOARD

CONNECTED TO
BULK SUPPLY

UPPER

SWITCHED |

POWER
ASSEMBLY

B b

TO CONSOLE

FROM

861

POWER

CONNECTED TO

BA11-FA | CONTROL
. TO
10 2

REGULATORS

SWITCH

CONNECTED TO
BULK
SUPPLY

P22

P23

P24

LOWER

UNSWITCHED
|
POWER
ASSEMBLY

P31

P29

P26

P27

P28

P25

CONNECTED TO

P34

P35

ELAPSED

REGULATORS

TIME METER
11—-2443

Figure 5-1

Revision
E

Power Distribution Cable Harness 7009540,

CPU Cabinet Serial Numbers Greater Than 2000 (See Table 5-1) (Sheet 2 of 3)

TO FANS AND

INPUTS

THERMAL

VOLTAGE

TO BACK
PLANE &
CONSOLE
TO

CONSOLE

] [

GROUND

INPUTS

TO SYSTEM
UNIT POWER
DISTRIBUTION

BOARD
CONNECTED TO
BULK SUPPLY

P14

P15

P16

UPPER
SWITCHED
POWER
ASSEMBLY

P40

P21

P20

P19

P18

P17

——'PEIKEY SWITCH
170

CONSOLE

POWER

CONNECTED TO
REGULATORS

TO BA11-FA
THERMAL

.SWITCH

CONNECTED TO
BULK
SUPPLY

P22

P23

LOWER
UNSWITCHED
|
POWER
ASSEMBLY

FROM

861

CONNECTED TO

ELAPSED
TIME METER

REGULATORS

11-2296

Revision D

Figure 5-1
Power Distribution Cable Harness 7009540,
CPU Cabinet Serial Numbers Greater Than 200 (See Table 5-1) (Sheet 3 of 3)

5-4

CONTROL

|
TO BACK
PLANE &4

VOLTAGE

INPUTS

[

CONSOLE

\
TO
CONSOLE

]

[ B

| S—

GROUND

INPUTS

TO SYSTEM
UNIT POWER
DISTRIBUTION
BOARD

CONNECTED TO
BULK SUPPLY

UPPER

SWITCHED |

)

POWER

ASSEMBLY

TO CONSOLE

CONNECTED TO

REGULATORS

LOWER

ASSEMBLY

BAl1-FA | CONTROL
THERMAL
SWITCH

NOT
USED

SS%E%R 861

CONNECTED TO
BULK
SUPPLY

UNSWITCHED|

FROM

)

CONNECTED TO
REGULATORS

w’

ELAPSED
TIME METER
11-0966

Figure 5-2 Power Distribution Cable Harness 7008784, Revisions A Through C
CPU Cabinet Serial Numbers Less Than 2000 (See Table 5-1)

Table 5-1

Major ECO Summary for the Power System

From

ECO No.

Rev.

Rev,

11/45-00031

Description

Replaced 860 Power Control with 861 Power Control. Drawing
D-IC-11/45-0-1, Revision A, documents machines with the 860
Power Control.

11/45-00054

Power

distribution

redesigned

accommodate

H754

Regulator (+20V and -5V) for 16K memory. Power harness
changed from Part No. 7008784 to Part No. 7009540. System
unit power distribution harness moved from back of CPU box to

top rear of CPU box. System unit connectors changed from flat
8-pin connector to 15-pin and 6-pin pair of rectangular connectors.

11/45-00057

7009540 harness modified for distribution of =15V to system
units when H754 Regulator is installed for 16K memory.

11/45-00060

+5 V from slot D H744 rewired to lower voltage drops to system
units.

11/45-00061

CPU harness modified to accommodate second H746 MOS
Regulator. Add P30 to 7009540 harness near P29 machine

with S/N 2= 2000). If S/N < 2000 P30 of the 7008784 harness

is rewired to distribute MOS voltage from an H746 in slot L of
the lower H742. KB11-A ECO (KB11A-S0023) must be installed

at the same time.

The ten connector (J2 through J11) power distribution board on the CPU backplane is etched to carry
dc voltages, AC LO, DC LO, and clock signals on the outer side of the board, while the various
grounds connect to the inner side to form a common ground. The CPU backplane row and slot
assignments are shown in Figure 5-3. Backplane connectors and pins are shown in Figure 5-4.
Table 5-2 shows the distribution of dc power from its source at the regulator to its destination on the
backplane. Connectors, slots, rows, and pins are listed.
5.2 DC POWER SUPPLIES
The theory of dc power supplies and voltage regulators are discussed in this section. Table 5-3 lists the
regulator specifications.

5-6

ROW

- L IBW J0°L0H 9 ‘YA - 1218 XHINW

MATE-N-LOCKS

ROW B

ROW C

80¥SI8W

9160ISW ee Ne e SO

pHIYSJW E1dIXBdWN

ROW D

[} =z

w [&] - (= Z

ROW E

ROW F

SLOTS

91011 12 1314 15 16 17 18 19 20212223 242526 27 28

VIEWED

FROM

PIN SIDE

OF BACKPLANE (KB11-A)

HdXyxd4m921r8wWz%QuwM~0HO_ww_.l

= 378v2 € IN

Wi8ZI8N

VXAH-1LZI8WN 10W¥ZI18WD

SLOTS

456
78

10 11

VIE WED

2 301A30Q

£2OiVHSA

§|©o0m|g

XYWVA-1ZI8W

U s

WQemQO

|ov|8 & 0|

12 13 14 15 16 17 18 19 20212223 242526 27 28
FROM

SIDE

BACKPLANE (KB!1-D)

NOTE

For single unibus systems, an M9200 jumper module is used to connect Unibus A and Unibus B

(A,B26 and A,B27) together.

The unibus is then continued from slot A,B28 (M930 terminator removed).
11-4297

Figure 5-3 CPU Backplane Slot and Row Aséignments

5-7

TO SYSTEM
HARNESS

UNITS

7008784

(S/N <2000)

ALL UNITS
NOTES:

1. Used only if FP11 option is installed.
2. Used only if semiconductor memory is installed.

P/O L |COINSIOLE
87165 |

3. Slot H contains H746 if MOS memory is installed. It contains
H744 if no MOS memory but more than 2K bipolar memory
is installed.

Pl2 [I

7.-15V from lower H742(0)

F and higher.

Revision F and

p3é

higher

:;g

413121

;gRSJES;‘gM7(l)JON;15-iO

SLOT J

P/0

(S/N 2 2000)

Pisq6ls]4|3]2]1]

NoTE|
H744
2
RE; 3:’330"
Frm=——y

SLOT A

SLOT B

SLOT C

H744

{S/N 22000)

paeme-

H746

—5VH

MOS
ATOR!

+5VvDC

IREGULATOR

TOP6-4

REGUL

HT44

+5vDC
|REGULATOR

8-S

+5VvDC
[REGULATOR]|

—
]

TO SYSTEM UNITS
HARNESS 7009540

SLOT L

SLOT H

NOTE
+5vVDC
1
REGULATOR|

| I
I [ I
615141312 |1

REGULATOR

* %% 8. -15V from H745 in slot E (newer units) or slot F (early units)

Tt 9.

P /0

6. Dotted lines on etch are on connector side.

Revision

tt P/O

:;7 464(:

t 5. P8 through P11 are ground connections.

SLOT D

% 4. Wire wrap connection.
%%

SLOT K

NOTE
3

H746

H744

JUMPERS

11t

1
MOS
—
1REGULATOR I
H744

+5vDC

+5VDC

|REGULATOR

REGULATOR

o Jd
& &

o L

Q¥

*
*ol N

A %

*
o
AN
o
*

Vv o
X
*

Pl e WY AR M cutn B

HARNESS

X
o)

*hd \

A
%)
N

)" ¢

A
So}
g A
© mo O

N
A
o

S——

pe[a[7]e[5]a|3]2|1|p3[s]7]e]5[a[3]2] ]pa[s[7]6]5 [43]2]1]Ps[s]7]e|5]a]3]2] 1 ]re|s]7 le|s]a]3|2]1]p7|8]7 [s]5]a]3]2]1
\\

’r

’,

’

\‘

X/ v Y v ~

ORI

SLOTS;

—-l-f

26 2le27- 28 —f
o

L4
,

5009909D - PINSIDE

)

€

LJ
R

VIEW

11-2299

Figure 5-4

Backplane Connectors and Pins

Table 5-2

VOLTAGE | REGULATOR
Slot

Plug

Voltage Distribution, PDP-11/45, 11/50, 11/55

HARNESS
Plug

BACKPLANE
Slot

Row

+5 Vde

MODULES
Pins

KB11-A, D — NO OPTIONS

P18-2,5

J2-1,2

1,69

A—F

P18-2,5

J1-1,2

A-F

Slot 1: KW11-L, W131, W133

P19-2.5

J3-5,6

10-15

A-F | A2Vl

P20-2

J1-8

—

Console

P20-5

J12-1.4

—

System Units

P20-5

J12-54

—

System Units

P20-5

J7-8

A,B

Unibus A, Peripheral Controller

P20-5

J7-8

26-28

C-F

Peripheral Controllers

Slots 6—9: DAP, GRA, IRC, RAC

PDR, TMC, UBC, SSR, SAP or SBJ, TIG & PHK

FLOATING POINT OPTION

P17-2,5

12-5.6

2-5

A-F | A2, VI

FRH, FRL, FXP, FRM

6-S

MOS ONLY MEMORY

P27-2,5

J4-1245
J5-14,78

16-25
-

A-F | A2, V1

Slots 16 & 218: M8110 Controllers
Slots 17—20 & 22—25: G401 Matrix Modules®

37-5,6

27-28

A,B

Unibus B

BIPOLAR ONLY MEMORY

P27-2,5

J445

16-18

A-F | A2,V

Slot 16: M81203; Slots 17—18: Two M8111! or M8121-YA$

37-5,6

27-28

A,B

Unibus B

19,20

A-F | A2, V1

24-25

A-F | A2, VI

P31-2,5

J4-1.2

| By

P29-2.5

J6-5,6

P28-2.5

J5-1,2

21-23

A-F | A2, VI

Two M81112 or M8121-YA?

Slot 21: M81203, Slots 22—23: Two M81118 or M8121-YA®
Two M81112 or M8121-YA®

BIPOLAR AND MOS MEMORIES

KS
L?

P27-2,5

P28-2,5
P29-2.5

J44.5

16—20

A-F | A2, V1

Slot 16: M8110%; Slots 17—20: G401 (-YA)®

3756

27-28

A,B

Unibus B

P5-1,2
P6-5,6

21-23
24,25

A-F | A2, VI
A-F | A2, V1

Slot 21: M81203; Slots 22—23: M8111% or M8121-YA®
Two M81118 or M8121-YA®

* Newer systems only (S/N > 2000)

3 Bipolar Controller (early versions use an M8110)

7 3rd and 4th 4K of Bipolar

+ Early systems only (S/N < 2000)
! 1st and 2nd 1K of Bipolar Memory

4 MOS Controller

8 Asrequired

2 3rd and 4th 1K of Bipolar Memory

5 Up to 16K of MOS
¢ 1st and 2nd 4K of Bipolar

Table 5-2

VOLTAGE

REGULATOR
Slot

Voltage Distribution, PDP-11/45, 11/50, 11/55 (Cont)

HARNESS

BACKPLANE

MODULES

Plug

Slot

Row

Pins

Upper | Pl14-1

P2-8

E,F

w131

t | H742) | P14-2

P21-5

—

-15 V Regulator Slot E

T
*

P25-5
P254

—
—

-15 V Regulator Slot F
-15 V Regulator Slot F

P214

—

-15 V Regulator Slot E

P36-8,7

—

System Units

+8 Vdc

H7420

(or
+15V

P14-2

*
T

P14-3

P3-2,3

01-¢

P14-3

'
ACLO1

ACLO2

CLOCK

DCLO1

P14-8

P14-10

P14-11

P14-12

* Newer systemsonly (S/N > 2000)
+ Early systems only (S/N < 2000)

TIG

26—28

Peripheral Controllers

P1-1

—

Console

P12-2

—

System Units

P36-2

—

System Units

P3.7

UBC

P22-10

—

Lower H7420 (or H742)

P22-8

—

Lower H7420 (or H742)

P7-7

Unibus B

P36-6,5

—

System Units

P2-7

KW11-L

P3-8

UBC

Table 5-2

VOLTAGE

REGULATOR
Slot

ACLO2

Voltage Distribution, PDP-11/45, 11/50, 11/55 {Cont)

HARNESS

BACKPLANE
Slot

Row

MODULES

Plug

Pins

Lower | P22-8

P14-10

—

Upper H7420 (or H742)

H7420

P7-7

Unibus B

(or

ACLO1

H742) | P22-10

—

Upper H7420 (or H742)

UBC

DCLO 2

P22-9

P7-4

Unibus B

DCLO X

P22-12

P4-3

16, 21

SMC

P22-4

PP5-6,5

Second M8110

P3-1

First M8110

-15 Vdc
unswitched

[1-g

P14-8
P3-7

-15 Vdc

P12-7,2

—

System Units No. 1 & 2

switched

P21-1

P7-1,2,3

2628

C—F

Peripheral Controllers

P3-4

PHK

2,3

FRH, FRL

P21-1

P1-5
P36-13

—
—

—_
—

—
—

Console
System Units — Only if no +20, -5 V Options

P25-1

P13-7

—

System Unit No. 3

2628

C-F

Peripheral Controllers

PHK

2,3

FRH, FRL

—

Console

T
*
T

Y
F

P25-1

P7-1,2,3
P3-4

*
*

i
* Newer systems only

1 Early systems only

P25-1

P1-5

P45-3/J45-3

to P12-13

System Units - Only if Slot E Regulator is a

H754 (+20.-5 V)

Table 5-2

VOLTAGE

-5 Vdc MOS

REGULATOR
Slot

Plug

P26-3

+19.7 Vdc MOS

HARNESS
Plug

P64

BACKPLANE

MODULES

Slot

Row

Pins

17-20

Cl1

22-25

Cl1

P26-4

P4-6

17-20 | ACE | U2

P314

P6-2

22-25

P26-5

P4-8

17-20

| ACE

P31-5

P6-3

22-25

| ACE | V2

-5 Vdc

P40-3

P12-14

—

+20 Vdc

P40-5

P12-3

—

Tt
+23.2 Vdc MOS

cl-s

Voltage Distribution, PDP-11/45. 11/50, 11/55 (Cont)

+1 Revision F and higher.

G401 (-YA) MOS Matrix

| ACE | U2
| V2

Y
MM11-U/UP

Table 5-3

Regulator

Regulator Specifications

Voltage and Tolerance

Output

Peak-to-Peak

Current (max)

Ripple (max)

H744

+5 Vdc * 5%

25 A

200 mV

H745

-15Vdc = 5%

10 A

450 mV

H746

H754

H742

+23.2 Vdc +3, -5%

1.6 A

+19.7 Vdc

33A

-5 Vde

1.6 A

+20 Vdc £ 5%

8 A

-5 Vdc * 5%

700 mV
)

150 mV

1A-8A (4)

+15Vdc +10%

+8 Vdc + 15%

20--30 Vac (5 outputs)

700 mV

)

300 W ea output,

s% [ G
-

—

———

1 Kw max.

total output.

Notes:

Refer to drawing D-CS-H746-0-1. Since the 19.7 V output is obtained by
regulating down from the +23.2 volt level, any combination of loads on the
two outputs is acceptable as long as the sum does not exceed 5 A.

Negative 5 V level is obtained by inserting a 5.1 V Zener diode in series with
the +23.2 and +19.7 loads, and using the Zener cathode as GND. Therefore,
maximum =35 V load current is equal to the greater of 1.6 A or the sum of the

two positive load currents (+23 and +19).

Total not to exceed 3 A continuously.

At backplane. Typical ripple ~+3%.
Maximum -5 V current is dependent upon +20 V current. It is equal to 1 A +
I +20) Uptoa total of 8 A. (I +20) is the amount of +20 V current.)

Each H7420 and H742 power supply provides 5 slots for regulator positioning. (See Figures 5-5 and 56.) The types of regulators used in these slots are dependent on the dc power requirements of the
particular PDP-11/45, 11/50, or 11/55 system.
Figure 5-7A shows the voltage regulator slot assignments for the various configurations in a system

with the new power harness (CPU cabinet serial numbers greater than 2000). Figure 5-7B shows the

same for a system with the old harness (serial numbers 1999 or lower). Note these figures are decals
that are located on the back of their related power supplies.

5-13

CIRCUIT
BREAKER

xaO m

TERMINAL

4)
( FAN
(Fa)

x [a)

5 SLOTS FOR
REGULATORS

5411086
REGUEATOR

LINE MONITOR

(POWER CONTROL BOARD)

11-4299

Figure 5-5

H7420 Power Supply

5-14

w®

TERMINAL
BLOCK
TB82

FAN1
(F1)

5-15

3oy
0—

1
4

5 SLOTS FOR

REGULATORS

NOTE:

A and B version of the H742 is shown here.

11-4306

Figure 5-6

H742 Power Supply

upper pouJer supply

'SWITCHED REGULATORS

e J o | _c |
115V TO

+5V

SYSTEMUNITS]

INTERNAL

12.3

| A

+5V

CENTRAL

FLOATING

+5V

OPTIONS

CENTRAL

PROCESSOR

‘

| PROCESSOR

SUPPLY

POINT

+15V

+5V TO

REGS E.F.

ROWS

ROW

26.2728

13& CONSOLE

20V -5V

ACLO.DCLO

ALTERNATE

+8V TO

TOUSNYgTSEM

1 FOR MAINT

INITS

5V TO

ROW

MODULES

SYSTEM
UNITS

123

50/60 HZ SIG
(0 TO +5V)
TO

r5V TO

+5V TO

+5v TO

10-15

16.7.8.9

2345

ROWS

ROW

| FOR CLOCK
MODULE

Engineering Drawing No. A-DC-5310709

lower power supply

UNSWITCHED REGULATORS

+5V

BIPOLAR
MEMORY

+5V

BIPOLAR

MEMORY

+5V

IF BIPOLAR

MEMORY IS
INSTALLED

+5V

IF BIPOLAR
MEMORY IS
INSTALLED

+15V

CENTRAL

PROCESSOR
-15vV TO
ROWS

1.2.15
+5v TO

+5V TO

ROWS

ROWS
16.17.18

1920

+5V
+19V +23V -5V
IF MOS MEMORY[IF MOS MEMORY
IS INSTALLED | IS INSTALLED

BuLK

SUPPLY

15V TO

CENTRAL

PROCESSOR

INTERNAL
OPTIONS
15V TO
ROWS
26.27.28
CONSOLE

+5v TO

+5vV TO

MOS VOLTAGES

2425

212223

16-25

ROWS

TO ROWS

ACLO

DCLO

Engineering Drawing No. A-DC-5310709

Figure 5-7

Serial Numbers 2000 and Higher

Regulator Slot Assignments, CPU Cabinet (Sheet 1 of 2)

5-16

power supply

h742a
REGULATORS

o | c |

+15V

+5V

CENTRAL

PROCESSOR
—15V TO

+5V

INTERNAL

+5V

CENTRAL

OPTIONS

PROCESSOR

CENTRAL

PROCESSOR

+5V

FLOATING
POINT

BULK
SUPPLY A
REGULATORS

AB.CDE

SWITCHED

ROWS
1.2.15
+15V TO

INTERNAL

26.27.28

+15V TO ROW

ROWS

OPTIONS

—-15V TO

REGS

+5v TO
13

ROWS

CONSOLE

+8V TO ROW

26.27.28
CONSOLE

SYSTEM

SYSTEM
UNITS
_
15V TO

UNITS
+5v 70
SYSTEM
UNITS

1. FOR MAINT
MODULES

SYS

50/60 HZ

H1 H2 H3

UNITS

+5V TO

10.11.12.13.14.15

16789

2345

ROWS

Hi#H2

ROWS

SIG

(0
10 TO+5V)
ROW 1

FO% cOLOCK
MOBULE

Engineering Drawing No. A-DC-5309993

power supply

h742 a

+5v
BIPOLAR
MEMORY

+5V
BIPOLAR
MEMORY

+5V
BIPOLAR

MEMORY

INSTALLED

+5v
BIPOLAR

MEMORY

INSTALLED

—15V
SYSTEM
UNITS

BULK
SUPPLY

REGULATORS

FHJKL

NOT
SWITCHED
+5V TO

+5V TO

ROWS

1920

16.17.18

+5V
+19V +23V =5V
IF MOS MEMORY}IF MOS MEMORY
IS INSTALLED | IS INSTALLED

*REG H
+5vV TO
ROWS

+5V TO
ROWS

2425

212223

+5V TO
ROWS
16.17.1819.20.
2122232425

MOS VOLTAGES
TO ROWS
| 16.17.18.19.20.
| 2122232425

—15V TO
SYS UNIT

WILL BE
EITHER A
| +5vV OR MOS
VOLTAGE

REG

Engineering Drawing No. A-DC-5309994

B.
Figure 5-7

Serial Numbers Less Than 2000

Regulator Slot Assignments, CPU Cabinet (Sheet 2 of 2)

5.2.1

AC Input/Output

The input circuits of the upper and lower power supplies are shown in Figures 4-6, 4-7, and 4-8. Refer
to Figures 5-5 and 5-6. Jumper connections for 115 or 230 Vac operation are provided by TB1 at the
primary of T1. Each power supply contains a bulk supply cooling fan F1 and three voltage regulator
cooling fans F2, F3, and F4. An elapsed time meter receives 115 Vac from the upper supply to indicate
total time power is applied to the CPU. On the lower supply, the corresponding output is applied to
the nine cooling fans in the CPU mounting box to provide unswitched cooling for the logic modules
installed in the CPU backplane.
5.2.2

Power Control Boards

Each H7420 power supply contains a 5411086 power control board (Figure 5-5). Each H742 power
supply contains a 5409730 power control board (Figure 5-6). Both types of power control boards
provide dual functions as regulators and line monitors. As regulators, they provide +15 V,-15 V, and
+8 V sources. As line monitors, they provide AC LO and DC LO power fail signals. They also provide
an LTC signal to drive the KW11 clock options. Thus, the power control board may be referenced as a
regulator or a line monitor.

AC LO L indicates that the line voltage is below a perscribed minimum. DC LO L indicates that the
line voltage is below the minimum operating tolerance and that the +15 V regulator circuit cannot be
expected to produce an output within specified normal operating limits. These signals are not affected
by the outputs of the individual voltage regulators.

5.2.2.1

5411086 Power Control Board - Figure 5-8 shows a simplified diagram of the 5411086 control

board.
+15 V and +8 V Supply

In the regulator circuit the 20-30 Vac input is full-wave rectified by bridge D11 to provide dc voltage
(25 to 45 Vdc, depending on line voltage and load on +15 V) across filter capacitor Cl and bleeder
resistor R15. Operation centers on voltage regulator E1, which is configured as a positive switching
regulator. A simplified diagram of El is shown in Figure 5-8. El is a monolithic integrated circuit that
is used as a voltage regulator. It consists of a temperature-compensated reference amplifier, an error
amplifier series pass power transistor, and the output circuit required to drive the external transistors.
In addition to El, the regulator circuit includes pass transistor Q7, predriver Q4, and level shifter Q6.
Zener diode D17 is used with R11 to provide +15 V for El.
The output circuit is standard for most switching regulators and consists of free-wheeling diode D12,
choke coil L1, and output capacitor C3. These components make up the regulator output filter. Freewheeling diode D12 is used to clamp the emitter of Q7 to ground when Q7 shuts off, thus providing
discharge path for L1. This output circuit and waveforms are shown in Figure 5-9.
In operation, Q7 is turned on and off, generating a square wave of voltage that is applied across D12 at
the input of the LC filter (L1 and C10). Basically, this filter is an averaging device, and the square wave
of voltage appears as an average voltage at the output terminal. By varying the period of conduction of
Q7, the output (average) voltage may be varied or controlled, thus supplying regulation. The output
voltage is sensed and fed back to E1, where it is compared with a fixed reference voltage. El turns pass
transistor Q7 on and off, according to whether the output voltage level approaches its upper and lower
limits (approximately +15.15 V and +14.85 V respectively).

5-18

| SENSING CIRCUIT
I

AC LO, DC LO SENSING

ACLO,DCLO DRIVER

]

DCOK

I
|

D21

—*

DC LOW

SENSING

Q13,016

— DRIVERS

—*

D20

AC LOW

SENSING

Q11,Q12

ACOK

FET NEGITIVE

DC LOW

BIAS VOLTAGE
GENERATOR

61-G

I
I

FULL

WAVE

» RECTIFIERD11

|
_ AC

DRIVERS

1,2

»LO

FUSE

SWITCHING

-\ 2

LINE CLOCK
(ZENER
CLOCK <——] RUZENER

REGULATOR

Q4,Q7

ZENER

R4,R5,R6,01,02,D2

DI7

OVERVOLTAGE
CROWBAR

CIRCUIT

€

8,Q9,D11

VOLTAGE REGULATOR I.C.

REFERENCE

»*H5VDC

REFERENCE

GND

(PASS TRANSISTOR)

15VOLT

OVER CURRENT
REGULATOR

LINE

’

REGULATOR CIRCUIT
20-30
VAC
ACINPUT

AcLow

215,018,019

Q3,Q5,T1

010,014,017

DC LO

ZENER

VOLTAGE

DIVIDER

NYCOMPARATOR

$R24

I
VOLTAGE
ADJUST

+8VDC

" +10%

I
]

* GND

1-4301

Figure 5-8

5411086 Block Diagram

+30V

/— NOTE

30V

seszaay

Q7 OFF

&D12

A
C10

NOTE

30 volt

level

50-200us

Vout

Q
(

OUTPUT NOISE

FULL

LOAD

NOTE 2

shifts with AC input voltage.

Small 120Hz jitter is normal.

NOTE

Peak noise=1% max.

Measure noise with a short 100§ terminated piece of foil
coax. Normal 10:1 scope probe will not give an accurate

noise

NOTE 3.

measurement.

Noise and ripple amplitudes are exaggerated in this

figure for iltustrative purposes.

Figure 5-9

11-4302

H744 Regulator Waveforms

During one full cycle of operation, the regulator operates as follows: Q7 is turned on and a high
voltage (approximately +30 V) is applied across L1. If the output is already at a +15 V level, then a
constant +15 V would be present across L1. This constant dc voltage causes a linear ramp of current to
build up through L1. At the same time, output capacitor C10 absorbs this changing current, causing
the output level (+ 15 V at this point) to increase. When the output, which is monitored by E1, reaches
approximately +15.15 V, E1 shuts off, turning Q7 off; the emitter of Q7 is then clamped to ground. L1
reverses polarity and discharges through D12 into capacitor C10, and the load. Predriver Q4 is used to
increase the effective gain of Q7, thus ensuring that Q7 can be turned and off in a relatively short
period of time.
Conversely, once Q7 is turned off and the output voltage begins to decrease, a predetermined value of
approximately +14.85 V will be reached, causing El to turn on; El in turn, causes Q7 to conduct,
beginning another cycle of operation.

Thus, a ripple voltage is superimposed on the output and is detected as predetermined maximum
(+15.15 V) and minimum (+14.85 V) values by E1. When +15.15 V is reached, E1 turns Q7 off; when
+14.85 V is reached, El turns Q7 on. This type of circuit action is called a ripple regulator.

5-20

The overcurrent regulator circuit functions as a current regulator when the current, monitored at D11,

exceeds 5 A. The current regulator consists of R4, RS, R6, Q1, Q2, and D2. During normal operation
QI and Q2 are not conducting. Q2 starts conducting when the voltage drop across R5 and R6 (sensed
by D2) exceeds approximately 0.6 V. When Q2 conducts, D1 becomes forward biased and El is shut

off, turning off the pass transistor Q7 and predriver Q4. The conduction of Q2 will also turn on QI

providing a constant current source (1 mA) to the base of Q2. Q1 will hold Q2 on until the current
across R5 and R6 drop below approximately 4 A.
With Q1 and Zener D2 tied to the +15 V Zener reference for E1, the conduction of Q1 will hold E1 off.
When Q1 and Q2 stop conducting E1 will turn on, enabling the current to exceed the regulator limits.
With a continuous overcurrent condition Q1 and Q2 will be turning and off, causing the circuit to

become a constant current regulator.
The +15 V overvoltage crowbar consists of the following components: Zener diode D18, and siliconcontrolled rectifier (SCR) Q8, Q9, R38, R40, C13, and Q9. Under normal output voltage conditions,
the trigger input to SCR D7 is at ground because the voltage across Zener diode D3 is less than 18 V. If
the output voltage becomes dangerously high (above 18.0 V), diode D18 conducts, turning Q9 on, and
the voltage drop across R40 draws gate current and triggers the SCR. The SCR fires, short circuits the
+15 V output to ground, and turns off E1 by shorting out the +15 V reference at D17.
Line Clock Output

The line clock output (LTCL) is derived from one leg of full-wave rectifier bridge D11, by voltage
divider R22 and Zener diode D19. The clock output is a 0 to +3.9 V square wave, at the line frequency
of the power source (47 to 63 Hz). The clock output is used to drive the KW11 clock options.
AC LO and DC LO Circuits

The AC LO and DC LO sensing circuit has a 20-30 Vac input from a secondary winding of transformer T 1. The sensing circuits are shown on drawing D-CS-5411086-0-1; a simplified version is shown
in Figure 5-8. The ac input is rectified by diodes D15 and D16, and filtered by capacitors C20 and C24.
A common reference voltage is derived by Zener diodes D13 and D 14. Both sensing circuits operate
similarly; each contains a differential amplifier and associated circuits. The major difference is that the
base of Q12 in the AC LO circuit differential amplifier is at a slightly lower value than that of Q16 in
the DC L O differential amplifier. The operation of both sensing circuits depends on the voltage across
capacitor C8.
The AC LO and DC LO driver circuit produces the power fail signals. When an ac low condition is
sensed the output of differential amplifier Q12 turns off Q9. Q19 in turn gates on FETS Q15 and Q18,
generating AC LO 1 and AC LO 2 signals.
Approximately 7 ms after AC LO is sensed the DC LO sensing circuit will generate DC LO. The DC
LO sensed output from differential amplifier Q16, turns off Q10. Q10 in turn gates on FETs Q14 and
Q17, generating DC LO 1 and DC LO 2 signals.
The +25 Vdc to +45 Vac from rectifier D11 is applied to T1, Q3, and Q5. Q3 and QS5, due to their

switching action, create a pulsating dc which is applied to the primary of transformer T1. The output
from the secondary of T1 (approximately 15 V) is rectified by D6, D7, D8, and D9, producting -10
Vdc to -15 Vdc. The -10 Vdc to -15 Vdc is a negative bias used to gate OFF J FETs Q15, Q18, Q14,
and Q17 via Q19 and QI10. Unlike most transistors, the negative bias is used to turn off the J FETs.
The J FETs are turned on when there is zero volts between gate (G) and source (S) terminals.

5-21

Light-emitting diodes D20, (ACOK) and D21 (DCOK) are normally lit. When AC LO L and/or DC

LO L are asserted, the light-emitting diodes go off, indicating that this regulator is the source of AC
LO L or DC LO L on the Unibus.
Figure 5-10 shows the H7420 power-up and power-down sequences.

AC POWER
ON

(132V rms AC)

—_J
|

REGULATOR

;

OUTPUTS

20ms

Maximum

DC LOW L

|
—

Sms.

—! [*— Maximum
|J

—»|

le—-2ms Nominal

LOW

(5.5ms. Maximum
)

POWER UP

'——'[-QSV rms AC

AC POWER

DOWN

-10%

‘Q

GENERATED WHEN
FETS Q15 AND Q18

OF THE CONTROL
BOARD ARE

TURNED ON

S5ms

minimum ~

[

REGULATOR

QUTPUTS

LOW

Low L

=|r
|

GENERATED WHEN
FETS Q14 AND Q17
OF THE CONTROL BOARD
ARE TURNED ON.

—-’: f#—1 ms Minimum
AC POWER DOWN
11-3027

Figure 5-10

H7420 Power-Up and Power-Down Sequences

5.2.2.2 5409730 Power Control Board - Figure 5-11 shows a simplified diagram of the 5409730 control board.
+15 V and +8 V Supply - The power control board of each H742 power supply contains a +15/+8
Vdc supply (drawing C-CS-5409730-0-1). The dc supply receives 20 to 30 Vac from the secondary of

transformer T1. The ac input is full-wave rectified by diode bridge D1. The resultant dc is applied to
Darlington voltage regulator Q1 through fuse F1. The bias on Q1 is controlled to provide +15 Vdc at
output pins 2 and 3, with respect to output pins 4, 5, and 6. Zener diode D7 provides approximately +8
Vdc at output pin 1. The combined output of this supply (+15 V and +8 V) is rated at 3 A.
The power control board outputs of the upper H742 are used as positive (+15 V, +8V) voltages with
respect to ground. On the lower H742 power control board, the positive output pins are at ground and
the negatlve output pins are used to provide a ~15 Vdc output with respect to ground. This =15 V
output is used by the M8110 SMC modules.
When DC LO 1 (or DC LO 2) is grounded at pin 9, Q2 conducts hard and cuts off Q1 completely, thus
removing the +15 V and +8 V outputs.

5-22

SENSING CIRCIT

"oc Loorive|

|
|

- DC LO

AC LODRIVE | |

. AC LO

DC LO DRIVE

——

REFERENCE
VOLTAGE

—4

o SENSING
DC LO

D12, R18, C3

Q4,Q5

AC LO

FULL WAVE

—

SENSING

RECTIFIER

D8,09,D10,011

06,q27,Q15

AC LO DRIVE II

. AC LO

» LO GND

Q14,015

-l

I REGULATOR CIRCUIT
|

'
l

LEQE&%CK

VOLTAGE

DARLINGTON
PAIR)

VOLT
15ZENER

REFERENCE

. 15VDC

REGULATOR

FUSE

I
I

REGULATOR
DISABLE
ZENER

VOLTAGE

DIVIDER

|
I
|

|
|

+8VDC

—* (+0.8 VDC)
—» GND

ke
5%

CIRCUIT

Q203,04,05,06]

|
|

REFERENCE)

|
|

4—

LINE

crocx

RECTIFIER
D1

AC INPUT

FULL WAVE

15-24 VAC

» DC LO

| | Q16,Q17

!
I

, Q11

__les,09,012

20-30 VAC
AC INPUT

11-4293

Figure 5-11

5409730 Block Diagram

Line Clock Output - The clock output (LTC L) is derived from one leg of full-wave rectifier bridge D1,

by voltage divider R10 and R11, and Zener diode D2 (drawing C-CS-5409730-0-1). The clock output is
a 0 to +5 V square wave, at the frequency of the power source (47 to 63 Hz). The clock output is used
to drive the KW11-L line frequency and KW11-P real-time clock options.
AC LO and DC LO Circuits - A 20-30 Vac input from the secondary of transformer T1 is applied to

the AC LO and DC LO sensing circuits on each of the H742 power control boards. The sensing circuits
are shown on drawing C-CS-5409730-0-1. The ac input is rectified by diodes D8 through D11, and
filtered by capacitor C3. A common reference voltage is derived by resistor R18 and Zener diode D12.
Both sensing circuits operate similarly; each contains a differential amplifier, a transistor switch, and
associated circuits. The major difference is that the base of Q6 in the AC LO circuit differential
amplifier is at a slightly lower value than that of Q9 in the DC LO differential amplifier. The operation
of both sensing circuits depends on the voltage across capacitor C3.
For AC LO sensing, the 20-30 Vac input is rectified and stored in capacitor C3, which will charge and
discharge at a known rate whenever the ac power is switched on or off. Thus, the voltage applied to the
emitters of differential amplifier Q6/Q7 through R17 is a rising or falling waveform of known value.
For example, when power fails or is shut down, the dc voltage decays at a known rate, as determined
by the RC time constant. If the voltage decreases to the point where the base of Q6 becomes negative
with respect to the base of Q7, the increased forward bias on Q6 causes it to conduct more, and the
resultant decrease in Q7 causes it to cut off. This removal of voltage across R16 causes Q5 and Q4 to
conduct. The AC LO line at pin 8 is grounded. An extra AC LO line (AC LO X on pin 10) is also
grounded by the similar switching of transistors Q15 and Q14.

AC LO 1 is applied through the cable harness and CPU backplane to the power fail initialize logic
shown on drawing UBCE. The mnemonic assigned to the input is BUSA AC LO L. AC LO 2 is

applied through the cable harness to the Unibus B terminator as BUSB AC LO L. The AC LO outputs
from the upper and lower H742 power supplies are interconnected for use in multiprocessor systems.
A regulator disable circuit is also provided that disables the regulator outputs when a DC LO is
detected. (AC LO may also trigger a disable since it eventually generates a DC LO.) The regulator
disable circuit consists of Q2, Q3, and associated circuitry. When a DC LO is generated, Q3 is biased
on which turns on Q2. This disables the regulator by turning off Q1 and clamping the output to ground
through D4 and RS5.

The DC LO sensing circuit operates in a manner similar to that described for AC LO. The difference
between these circuits is the voltage level at which they trip. For example, if the ac input starts to
decrease, as a result of a power failure or shutdown, the AC LO lines are grounded before the DC LO
lines. As power is restored, the ground is removed from the DC LO lines before it is removed from the

AC LO lines. A description of how the AC LO and DC LO control signals are used in the KB11-A, D
is provided in the KB11-4, D Central Processor Unit Maintenance Manual.

DC LO 1, generated by the switched H742 power control board, is applied to the power fail initialize
logic shown on drawing UBCE as input BUSA DC LO L. DC LO 2, generated by the unswitched
H742 power control board, is applied to the Unibus B terminator module as BUSB DC LOL. A DC
LO X output from the lower H742 power supply is applied to the M8110 SMC modules.

AC LO and DC LO indicate the status of the associated H742 bulk supply, as described in the preced-

ing paragraphs. These signals are not affected by the outputs of the individual voltage regulators.

Figure 5-12 shows the H742 power-up and power-down sequences.

5-24

—l__— 95

132 VAC

» POWER

—

- DC LO

+3.5V

o-|

f—

MOS (H746)

—

‘

> AC LO

)

NOTE:

—t

"""’

Processor operation
LO is removed.

-15V (H745)

: i

—>:
(M |<—

ARE IN

0-+--—

—

oi’———l
007

(H724)

(H748)

DC LO (H742)

t—

AC LO (H742)

l__

*5V

-15V

(H745)

HIsY

+15V (H742)

.001

1 +,003 |+ I MIN

|‘“'3%c>)<."| l : o

TIMES SHOWN

45y

0——\w

HSV

[
I
|[l——|—+15v,+8v
(H742)

H<— 002

is internally inhibited

OFF

---5V

for 70ms after AC

' : |

.025
= "max" |

—» POWER

+oV

VAC

0 -

+5V (H744) &

=~
'

l.002 MIN., .007 TYP,

NOM.

SECONDS

AC POWER-UP

AC POWER DOWN
11-2334

Figure 5-12

H742 Power-Up and Power-Down Sequences

5.2.3 H744 +5 V Regulator
From three to eight H744 +5 V regulators are used in the PDP-11/45, 11/50, 11/55 power system,
depending on the system configuration (drawing D-CS-H744-0-1).
Regulator Circuit — The 20-30 Vac input is full-wave rectified by bridge D1 to provide a dc voltage (24
to 40 Vdc, depending on line voltage) across filter capacitor C1 and bleeder resistor R1. Operation
centers on voltage regulator E1, which is configured as a positive switching regulator. A simplified
schematic of E1 is shown in Figure 5-13. E1 is a monolithic integrated circuit that is used as a voltage
regulator. It consists of a temperature-compensated reference amplifier, error amplifier series pass
power transistor, and the output circuit required to drive the external transistors. In addition to E1, the
regulator circuit includes pass transistor Q2, predrivers Q3 and Q4, and level shifter Q5. Zener diode
D2 is used with Q5 and R2 to provide +15 V for E1. QS5 is used as a level shifter; most of the input
voltage is absorbed across the collector-emitter of Q5. This is necessary because the raw input voltage
is well above that required for E1 operation. This +15 V input is supplied while still retaining the
ability to switch pass transistor Q2 on or off by drawing current down through the emitter of Q5.
The output circuit is standard for most switching regulators and consists of free-wheeling diode D5,
choke coil L1, and output capacitors C8 and C9. These components make up the regulator output

filter. Free-wheelmg diode D5is used to clamp the emitter of Q2 to ground when Q2 shuts off, thus
providing a discharge path for L1. (Circuit and waveforms are similar to those of Figure 5-9.)
In operation, Q2 is turned on and off, generating a square wave of voltage that is applied across D5 at
the input of the LC FILTER (L1, C8, and C9). Basically, this filter is an averaging device, and the
square wave of voltage appears as an average voltage at the output terminal. By varying the period of
conduction of Q2, the output (average) voltage may be varied or controlled, thus supplying regulation.
The output voltage is sensed and fed back to E1 where it is compared with a fixed reference voltage. E1
turns pass transistor Q2 on and off, according to whether the output voltage level decreases or increases. Defined upper and lower limits for the output are approximately +5.05 V and +4.95 V.

5-25

FREQUENCY

COMPENSATION

INVERTING
INPUT

VREF ©

SERIES PASS
TRANSISTOR

0 VOUT
¢ ————

QE___Q
vZ

NONINVERTING
INPUT

CURRENT CURRENT

V-

LIMIT

SENSE

11-0965

Figure 5-13

Voltage Regulator El, Simplified Diagram

During one full cycle of operation, the regulator operates as follows: Q2 is turned on and a high
voltage (approximately +30 V) is applied across L1. If the output is already at a +5 V level, then a
constant +25 V would be present across L1. This constant dc voltage causes a linear ramp of current to
build up through L1. At the same time, output capacitors C8 and C9 absorb this changing current,
causing the output level (+5 V at this point) to increase. When the output, which is monitored by E1,
reaches approximately +5.05 V, El shuts off turning Q2 off; the emitter of Q2 is then clamped to
ground. L1 discharges into capacitors C8, C9, and the load. Predrivers Q3 and Q4 are used to increase
the effective gain of Q2, thus ensuring that Q2 can be turned on and off in a relatively short period of
time.

Conversely, once Q2 is turned off and the output voltage begins to decrease, a predetermined value of
approximately +4.95 V will be reached, causing E1 to turn on; El, in turn, causes Q2 to conduct,
beginning another cycle of operation.

Thus, a ripple voltage is superimposed on the output and is detected as predetermined maximum
(+5.05 V) and minimum (+4.95 V) values by E1. When +5.05 V is reached, E1 turns Q2 off; when
+4.95 V is reached, E1 turns Q2 on. This type of circuit action is called a ripple regulator.

45 V Overcurrent Sensing Circuit — The overcurrent sensing circuit consists of: Q1, R3 through R6,
R25, R26, programmable unijunction Q7, and C4. Transistor Q1 is normally not conducting; however,
if the output exceeds 30 A, the forward voltage across R4 is sufficient to turn Q1 on, causing C4 to
begin charging. When C4 reaches a value equal to the voltage on the gate of Q7, Q7 turns on and El
will be biased off, turning the pass transistor off. Thus, the output voltage is decreased as required to
ensure that the output current is maintained below 35 A (approximately) and that the regulator is short
circuit protected. The regulator continues to oscillate in this new mode until the overload condition is
removed. C4 then discharges until El is again allowed to turn on and the cycle repeats.

5-26

+5 V Overvoltage Crowbar Circuit — The following components comprise the overvoltage crowbar
circuit; Zener diode D3, silicon-controlled rectifier (SCR) D7, D8, R22, R23, C7, and Q6. Under
normal output voltage conditions, the trigger input to SCR D7 is at ground because the voltage across
Zener diode D3 is less than 5.1 V. If the output voltage becomes dangerously high (above 6.0 V), diode
D3 conducts, and the voltage drop across R23 draws gate current and triggers the SCR. The SCR fires
and short circuits the +5 V output to ground.
5.2.4

H745 -15 V Regulator

According to the power requirements of the particular PDP-11/45, 11/50, 11/55 system configuration,
one or two H745 -15 V regulators may be included in the power system. Operation of the H745 is
basically the same as that of the -+5 V regulator (drawing C-CS-H745-0-1). Input power (20 to 30 Vac)
is taken from the transformer secondary and input to full-wave bridge D1, whose output is a variable
24 to 40 Vdc input across capacitor C1 and resistor R1.

-15 V Regulator Circuit - Regulator operation is almost identical to that of the +5 V regulator;
however, the +15 V input that is required for E1 operation is derived externally and is input across
capacitor C2 to El, and the inverting and noninverting inputs to E1l are reversed. In addition, the
polarities of the various components are reversed, For example, Q5, which is used as a *“‘level shifter,”
is an NPN transistor on the +5 V regulator; whereas a PNP is required on the -15 V regulator, thus
allowing the regulator to operate below ground (at -15 V).

Under normal operating conditions, regulator operation centers around linear regulator E1 and pass
transistor Q2, which is controlled by El. Predetermined output voltage limits are -14.85 V minimum
and -15.15 V maximum. When the output reache¢s ~15.15 V, E1 will shut off, turning Q2 off, and L1
discharges into C8 and C9. When the output reaches -14.85 V, E1 will conduct, causing Q2 to turn on,
thus increasing the output voltage.

~15 V Overcurrent Sensing Circuit — The —15 V regulator overcurrent sensing circuit is basically made
up to the same components used in the +5 V regulator, except QI is an NPN transistor in the =15V
regulator. Q1 is normally not conducting; however, once the output exceeds 15 A, Q1 will turn on and
C3 will charge. When C3 reaches the same value
as the gate of Q7, E1 will be biased off, which turns
Q2 off, thereby stopping current flow and turning the —-15 V regulator off. Thus, the regulator is short
circuit protected.

~15 V Overvoltage Crowbar Circuit - When SCR D5 is fired, the 'S V output is pulled up to ground and
latched to ground until input power or the +15 V input is removed. A negative slope on the +15V line
can be used to trip the crowbar for power-down sequencing, if desired.
5.2.5

H746 MOS Regulator

If the particular PDP-11/45, 11/50 system configuration contains MOS memory, the MOS regulator
must be included in the PDP-11/45, 11/50 power system. The MOS regulator supplies regulated out-

puts of -5, +19.7, and +23.2 Vdc. Basic MOS regulator operation and circuitry is similar to that of the

+5 V regulator; however, major differences do exist between the input and output circuitry of the two
(+5 V and MOS) regulators, because a higher input voltage is required in the MOS regulator, and
multiple outputs of -5V, +19.7 V, and +23.2 V are supplied by the regulator (drawing C-CS-H746-01).

Regulator Circuit — As in the +5 V and -15 V regulators, operation of the MOS regulator centers
around El, pass transistor Q2, predriver Q3 and level shifter Q5. The input uses a voltage doubler as

opposed to the full-wave diode bridge used in the +5 V and -15 V regulator. This is necessary because
the +23 V output requires a much higher input voltage (48 to 80 Vdc) to ensure the circuit operates
efficiently. The remaining regulator components are identical to those of the +5 V regulator except
that the individual components are selected to operate at the higher voltage levels.

5-27

The output circuitry contains additional components to yield the required multiple outputs of -5,
+19.7 and +23.2 Vdc. Transistor Q6 is a Darlington power amplifier that is employed as a linear pass
transistor to drop the +23.2 Vdc down to +19.7 Vdc. This is necessary because a constant 3 to4 V
difference in the two voltages is required in MOS memory operation. All of the current drawn by the
+23.2 and +19.7 V outputs is fed back to the rectifier source via the ground line, through Zener diode
D10, to yield the -5 Vdc output from the anode of D10.
Overcurrent Sensing Circuit — The overcurrent sensing circuit, consisting of Q1, R4 through R7, Q8,
R29, and C3, operates in exactly the same manner as in the +5 V regulator.
Overvoltage Crowbar Circuit - The overvoltage circuit consists of D7 through D9, Q7, and associated
circuitry, and operates in exactly the same manner as the +5 V regulator crowbar circuit.
5.2.6

H754 +20, -5 V Regulator

If the system contains an option requiring +20 and -5 V, such as the MF11-U/UP, H754 regulator(s)
must be added. They are mounted into slot E of the PDP-11/45, 11/50, 11/55 cabinet or into slots D
and/or E of an expanded cabinet.
Regulator Circuit — The circuit (schematic D-CS-H754-0-1) is similar to that of the other regulators:
like the H746, it has a voltage doubler input, but the output consists of two shunt regulator circuits,
one for the +20 V, the other for the -5 V. The +20 V shunt regulator consists of transistors Q4, Q10,
and Q11; the -5 V shunt regulator, of Q6 and Q9. Q10 and Q9 are the pass transistors.
The output of the basic regulator is 25 V (-5 to +20 V). The shunt regulators are connected across this
output, with a tap to ground between the pass transistors Q9 and Q10. The voltage at the bases of Q6
and Q4 will vary with respect to ground, depending on the relative amount of current drawn from the
+20 V and -5 V outputs of the regulator. If the +20 V current increases while the -5 V current remains
constant, the output voltage at the +20 V output will tend to go more negative with respect to ground;
this will cause the -5 V output to go more negative also, since the output of the basic regulator is a
fixed 25 V. This change is sensed at the bases of Q6 and Q4: Q6 will conduct, causing Q9 to conduct
also, thus increasing the current between -5 V and ground until the balance between the +20 V and the
-5 V is restored. At this time, neither Q6 nor Q4 will be conducting. If the -5 V current increases, Q4
and Q10 will conduct to balance the outputs.
Overvoltage Crowbar Circuits — There are two crowbar circuits in the H754: Q7 and its associated
circuitry for the +20 V, and Q12 and its circuitry for the -5 V. Either one will trigger SCR D?9.
Overcurrent Sensing Circuit - The overcurrent circuit is comprised of Q1, Q8, Q13, Q14, and associated
circuitry. the total peak current is sampled through R4. When the peak current reaches approximately
14 A, Q1 turns on sufficiently to establish a voltage across R7 and R38, thus firing Q8. This pulls the
voltage on pin 4 of the 723 up above the reference voltage on pin 5, thereby shutting off Q2. D6 now
conducts, and the current through R37 turns on Q14, which turns on Q13. This keeps Q8 on for a time
which is determined by the output voltage and L1. This action, in turn, allows the off-time of Q2 to be
greater than the on-time; the off-time increases as the overload current increases, thereby changing the
duty cycle in proportion to the load. The output current is thus limited to approximately 10 A.
Voltage Adjustment - The +20 V adjustment is located on the side of the H754; and the -5 V potentiometer is on the top, next to the connector. To set the output voltages: power down, disconnect the
load, power up, adjust for a 25 V reading between the +20 and -5 V outputs with the 20 V potentiometer. Then set the -5 V between its output and ground. Power down, reconnect the load, power up and
then check and adjust the outputs again. This procedure is necessary because the +20 V potentiometer
(R17) actually sets the overall output of the regulator (25 V from +20 to -5 V), while the -5 V
adjustment (R21) controls the -5 V to ground output. (See schematic drawing D-CS-H754-0-1)

5-28

CHAPTER 6
MAINTENANCE

PDP-11/45, 11/50, 11/55 maintenance procedures are divided into two categories: preventive maintenance and corrective maintenance. Corrective maintenance should be performed to isolate a fault or
malfunction and to make necessary adjustments and/or replacements. Using diagnostic programs that
test the functional units of the system and special calibration and test procedures aid in performing
corrective maintenance.

This chapter contains the following sections:

6.1

Maintenance Equipment Required

6.2

Preventive Maintenance - General

6.3

Power Systems Maintenance

6.4

CPU Maintenance - Diagnostic Programs

6.5

How to Use Maintenance Cards

6.6

How to Use the W900 Module Extenders

6.7

Module and Assembly Removal and Replacement

6.8

Removal and Replacement of ICs

6.9

Special MOS Handling Procedures

6.10

Equipment Configuration, Revision Status, and Mechanical Status Stickers.

MAINTENANCE EQUIPMENT REQUIRED

Maintenance procedures for the PDP-11/45, 11/50, 11/55 require the standard equipment (or equiva-

lent) listed in Table 6-1.

Generally the voltage regulators are not field repairable. However, guidelines are given in Paragraph
6.3.3 for depot or factory repairs.

6.2

PREVENTIVE MAINTENANCE

Preventive maintenance consists of specific tasks performed periodically to prevent failures caused by
minor damage or progressive deterioration due to aging. A preventive maintenance log book should be
established and necessary entries made according to a regular schedule. This data, compiled over an
extended period of time, can be very useful in anticipating possible component failure resulting in
module replacement on a projected module or component reliability basis.
6-1

Table 6-1

Equipment or Tool

Maintenance Equipment Required

Manufacturer

Model, Type or Part No.

Oscilloscope

Tektronix

453*

Digital Voltmeter (DVM)

Weston (or the like)

6000

Volt/Ohmeter (VOM)

Triplett

Unwrapping Tool

DEC Part No.

29-13510

Gardner-Denver

505 244-475

29-18387

A-20557-29

29-18301

(DEC Catalog #H812A)

Hand Wrap Tool

Gardner-Denver
(DEC Catalog #H811A)

Diagonal Cutters

Utica

474

29-13460

Diagonal Cutters

Utica

466-4 (modified)

29-19551

Miniature Needle Nose Pliers

Utica

23-4-1/2

29-13462

Wire Strippers

Millers

101S

29-13467

Solder Extractor

Solder Pullit

Standard

29-13451

Soldering Iron (30W)

Paragon

615

29-13452

Soldering Iron Tip

Paragon

605

29-19333

16-Pin IC Clip

AP Incorporated

AP923700

29-10246

24-Pin IC Clip

AP Incorporated

AP923714

29-19556

Maintenance Cards

DEC

W131, W133*#*

Maintenance Card Overlay

DEC

5509974-0-1

Module Extender Boards (3)

DEC

w900

* Tektronix Type 453 Oscilloscope is adequate for most test procedures; Type 454, or equivalent, may be required for some
measurements.

** W133 is a dual version of W130. It provides the drivers for two W131 maintenance cards.

Preventive maintenance tasks consist of mechanical and electrical checks. All maintenance schedules
should be established according to environmental conditions at the particular installation site.
Mechanical checks should be performed as often as required to enable fans and air filters to function
efficiently. All other preventive maintenance tasks should be performed on a regular schedule determined by reliability requirements. A recommended schedule is every 1000 operation hours or every
three months, whichever occurs first. Appendix B is a suggested preventive maintenance schedule for
peripheral equipment.

6.2.1
Physical Checks
Th/e following is a list of the steps required for mechanical checks and physical care of the PDP-11 /45,
11/50, 11/55:
1.

Check all fans to ensure that they are not obstructed in any way. Vacuum-clean the air vents

of the upper and lower logic fan housings, and upper and lower regulator fan housings.
Remove and wash the filters in the cabinet fan, located in the top of the cabinet.

6-2

6.2.2

Inspect all wiring and cables for cuts, breaks, frays, deterioration, kinks, strain, and
mechanical security. Repair or replace any defective wiring or cable covering.

Inspect the following for mechanical security: lamp assemblies, jacks, connectors, switches,
power supply regulators, fans, capacitors, etc. Tighten or replace as required.

Inspect all module mounting panels to ensure that each module is securely seated in its

connector and the locking-releasing mechanism is working properly.

Inspect power supply capacitors for leaks, bulges, or discoloration, and replace as required.

Inspect module guides for wear, damage, and secure fastening.
Electrical Checks and Adjustments

6.2.2.1 Regulator Voltage Checks - Perform the power system checks listed in Table 6-2. Use a
volt/chmeter (VOM) to check the output voltages under normal load conditions. Use an oscilloscope

to measure the peak-to-peak ripple content on all dc outputs. Each voltage regulator has an adjustment, potentiometer located just below the output indicator lamp (indicator lamp not present on

earliest versions). If the regulator output is not within the specified tolerance, adjust as required to

obtain an acceptable output. If a voltage regulator cannot be adjusted to meet specifications, remove
and replace the regulator. (See Paragraph 6.3.3.)

6.2.2.2 Power Control - Operate the REMOTE/OFF/LOCAL switch S1 on each power control to
ensure that power is turned on in the LOCAL position and disconnected in the OFF position. Return
S1 to its original position after performing this test. On early systems equipped with two 860 power
controls, the upper 860 S1 should be set to REMOTE, the lower 860 S1 to LOCAL. Figure 1-2 shows
which 860 power control is associated with each H742 power supply.

6.2.2.3 AC Power Connector Receptacles - Test the output voltage at each plug to ensure that 115 or
230 Vac is available.

6.2.3

Timing Margins

A preventive maintenance timing margin chart is provided at the back of this manual. The timing
margin chart can be used to maintain a record of margin test results. Such a record of timing variations
over a period of time will serve to point out any deterioration in system timing margins and indicate
when corrective maintenance may be required to prevent a system failure.

Paragraph 6.5 describes how to use the maintenance cards to vary the CPU and FPP RC clocks to
perform timing margin tests on the CPU and FPP. As each diagnostic program listed on the preventive
maintenance timing margin chart is run, vary the appropriate RC clocck to determine the minimum
and maximum clock speed at which the program fails. Nominal margins are 28-50 ns for the KB11-A,
27-450 ns for the KBI11-D, and 50-290 ns for the FP11-B at 70° F. Refer to the note in Paragraph
6.5.1. Record these speeds on the chart for each test. In the space provided above each entry, record
the date of the preventive maintenance procedure.

NOTE

Appendix B provides a table of peripheral preventive
maintenance schedules.

Table 6-2 CPU DC Outpuf Voltage Checks
Measure at

Max. Ripple

Output

CPU Backplane Pin

Voltage

Peak-to-Peak V

H744 +5V Regulator

A02A2

+5.0

0.15

AO6A2

+5.0

0.15

A10A2

+5.0

0.15

A26A2

+5.0

0.15

+5.0

0.15

(slot A)
H744 +5V Regulator

(slot B)
H744 +5V Regulator

(slot C)
H744 +5V Regulator

(slot D)
H744 +5V Regulator

A19A2

(slot H)

(Bipolar)

H744 +5V Regulator

A16A2

+5.0

0.15

A21A2

+5.0

0.15

A24A2

+5.0

0.15

E02B2

-15.0

0.45

A17V2

+23.2

0.70

+19.7

0.60

(slot J)
H744 +5V Regulator

(slot K)
H744 +5V Regulator

(slot L)
H745 -15V Regulator

(slot E)
H746 MOS Regulator

(slot H)

*(slot L)

A22V?2

H746 MOS Regulator

A17U2

(slot H)
*(slot L)
H746 MOS Regulator

(3—4V less
A2202

than +23.2)

F17C1

-5.0

0.15

+15.0

0.45

(slot H)
Switched H7420 P.S.

E15A1

(13.5-16.5)
Switched H7420 P.S.

EO1B1

+8.0

0.24

(6.8-9.2)
*Revision F and higher.

6.2.4

General Diagnostic Testing
Run all applicable diagnostic programs listed in Paragraph 6.4 for a minimum of one complete pass, or
three minutes, whichever is longer, to ensure that no machine problems exist that were not detected in
the timing margin tests.

6-4

6.3

POWER SYSTEM MAINTENANCE

WARNING
Dangerous voltages (115 or 230 Vac) are present in
the power system! Be careful when servicing these

circuits.
6.3.1

Circuit Tracing
A thorough knowledge of the location and operation of the various components of the PDP-11/45,
11/50, 11/55 power system is essential for troubleshooting this system. The drawmgs and text of
Chapters 3 (Power System), 4 (AC Power) and 5 (DC Power) of this manual, in conjunction with the
schematics listed below should provide all the necessary information in this respect.

H7420 Power Supply

D-CS-H7420-0-1

H742 Power Supply

D-CS-H742-0-1

H7420 Power Control Board
H742 Power Control Board
H744 +5 V Regulator
H745 -15V Regulator
H746 MOS Regulator
H754 +20, -5 V Regulator

C-CS-5411086-0-1
C-CS-5409730-0-1
D-CS-H744-0-1
D-CS-H745-0-1
D-CS-H746-0-1
D-CS-H754-0-1

PDP-11/45 Console Board
861 Power Control
860 Power Control

D-CS-5409684-0-1 (drawing KNLC)
D-CS-861-A-1, -B-1, or-C-1
D-CS-860-0-1, -A-1

6.3.2 Visual Aids to Troubleshooting
If a power system fault is suspected, visually inspect the system components for obvious fault
indications. For example, each of the voltage regulator modules is provided with an output indicator
lamp that lights when the output voltage is within range. If a single indicator lamp within the group
(A-E or H-L) is not lit, the fault is probably within that voltage regulator module. In the case of the
H744 +5 V regulator, this can be verified by swapping H744 modules. (See Paragraph 6.3.3.) Once the
fault has been isolated to a voltage regulator module, refer to the voltage regulator checkout procedure
described in Paragraph 6.3.3. A decal is placed on the rear of the BA11-FA chassis to indicate the
location and function of each voltage regulator. (See Figure 5-7.)

If none of the voltage regulator output indicator lamps in the group are lit, the fault is probably in the
associated power supply or power control. Visually inspect the power indicator lamps and circuit
breakers provided with these components to determine whether the fault can be isolated to either the
H7420 or the power control. Figures 4-6, 4-7, andi4-8 show where these indicator lamps and circuit

breakers are located (electrically) in each component. A description of the power controls is given in
Paragraph 4.2.

The following steps can be used to aid in locating the cause of a power system failure in a system using
an H7420 power supply and an 861 power supply control. Similar steps can be used for earlier power
system versions.
1.

Ensure that the H7420 is plugged in and getting primary power (115/230 Vac) from the 861
power control.

Check the power indicator and circuit breaker CB1 on the H7420.

Check the individual regulator lights. (Regulator lights are lit during normal operation.)

Check the two LEDs on the 5411086 power line monitor. They should be on during normal
operation. The first two steps of the 5411086 removal procedure (Paragraph 6.3.4.4) must be
performed in order to view the two indicators.

Measure regulator voltages at the processor backplane (Paragraph 6.2.2.1 and Table 6-2).

If all regulator outputs are within specifications, check the backplane for faulty wiring.

If one or more regulator outputs are incorrect, check the regulator fuse(s), the transformer
assembly, the power harness connections, and the load.

Ifthe +8 V,-15V, or +15 V outputs are incorrect, check the 5411086 power line monitor.

If the fault is isolated to a voltage regulator, refer to Paragraphs 6.3.3 and 6.2.2.1 for regulator troubleshooting and adjustment procedures.

6.3.3

Voltage Regulator Test Procedures

This paragraph suggests procedures to troubleshoot and test the H744 +5 V regulator, H745 -5 V
regulator, H746 MOS regulator, and H754 +20 -5 regulator modules. The procedures are intended to
aid in locating a fault, provided the fault has not destroyed the etched circuits.
When replacing a faulty voltage regulator, the new voltage regulator may need adjustment to compensate for the load. In some instances, if the new regulator is initially adjusted too high, it may
activiate the crowbar circuit and therefore provide no output when initially installed. If this happens,
turn power off and rotate the adjustment potentiometer counterclockwise. Then reapply power (regulator should not crowbar) and adjust the regulator output.
6.3.3.1
Initial Tests - When a power system fault has been isolated to a voltage regulator, examine
internal fuse F1. A blown fuse usually indicates that the main pass transistor Q2 and/or one of its
drivers Q3 and Q4 has short-circuited.
1.

Check for damage to base-emitter bleeder resistors and scorched etched board in the area of
Q3 (and Q4 if applicable).

If the pass transistor and drivers check OK on a VOM, the fault may be caused by continuous base drive to the first driver Q4 (Q3 in H754). Check level shifter QS for a short-circuit.

Check the resistance to ground at the input to the precision voltage regulator integrated
circuit E1 (pins 4 and 5) to determine if an external short-circuit is holding the IC in
conduction.

Use the VOM to check for short-circuit between fuse terminals and ground. Possible shortcircuit involving mounting TO-3 conponents to the heat sink may be located by connecting
VOM leads between TO-3 cases and a regulator bracket mounting screw on the end of the
heat sink.

6.3.3.2 Output Short-Circuit Tests — A voltage regulator that provides no output, or low output,
without causing fuse F1 to blow is probably working into a short-circuited output.
NOTE
An activated crowbar or a short-circuited output in
an otherwise properly operating voltage regulator
will not cause F1 to blow.

6-6

If fuse F1 is not blown, and the area of etched circuit around the ac input to the bridge
circuit is not damaged, it is safe to apply an ac input to the voltage regulator to determine if
the regulator is overloaded by a short-circuit across the output.
Connect the voltage regulator to a test bench source and advance the Variac to about 90 V.
If the output is near 0 V, turn the voltage adjustment fully counterclockwise and repeat the
test.

If the regulator appears overloaded, check for short-circuit across the output and for a
component failure in the crowbar circuit.
6.3.3.3

Testing a “Dead” Regulator - Use the following procedure to test a faulty voltage regulator
that does not exhibit the symptoms described above.

Apply 115 Vac to the test bench source (25 Vac at the voltage regulator input), with no load
on the regulator output.
Check for f30 Vdc across filter capacitor C1 (and C2 if applicable).
Check for +15 Vdc at pin 12 of precision voltage regulator E1. No voltage at this point
could mean Zener diode D2 (H744) or D3 (H746 or H754) has failed.
Check for 6.8-7.5 Vdc at pin 6 of E1 with respect to ground, pin 7.
If all voltage measurements in Steps 2, 3, and 4 are OK and there is no output voltage, pin 5
of E1 should be positive with respect to pin 4.
El, pin 2 should be +0.6 V with respect to pin 3. If it is not, connect emitter and base of Q5
together. If 0.6 V indication is obtained, precision voltage regulator E1 is OK and the fault
probably is caused by Q5 or Q4 (Q3 in H754).

6.3.3.4 Testing a Voltage Regulator After Repairs - Before returning a repaired voltage regulator to
service, it should be checked as follows:
1.

Connect the repaired voltage regulator to the appropriate source connector.

Set the voltage adjustment fully counterclockwise and set the load to zero.

Close the input circuit breaker and advance the Variac until output voltage is indicated (at
approximately 60-80 Vac input). No audible noise should be heard under no-load
conditions.
Be sure Q2 is connected and soldered before loading the regulator.
Advance the Variac to 130 Vac and return to 115 Vac.
Apply a 30-50 percent load. The output voltage should remain nearly constant. A clean
whistle may be heard. A buzz or a harsh hissing sound indicates possible instability. Check
waveforms as indicated in Figure 6-1.

juusnamenmmass

/— NOTE

30V

—

us
50-200

Vout
OUTPUT NOISE
NOTE 2

FULL LOAD

pe
NOTE

30 volt

level

—D‘

+30V

shifts with AC input voltage.

Small 120Hz jitter is normal.

NOTE 2:

Peak noise=1% max.
Measure noise with a short 100Q terminated piece of foil
coax. Normal 101 scope probe will not give an accurate

1-1075

noise measurement.

Figure 6-1 Typical Voltage Regulator Output Waveforms
(Maximum Output Ripple Is Specified in Table 5-3)

Apply 100 percent load and set the voltage adjustment for nominal output, as listed in the
following chart:

H744

+5.10 Vdc

H745

-15.10 Vdc

H754

+25 Vdc between +20 and -5 V outputs.

H746

+23.2 Vdc. After this adjustment, the regulator should be slid out to allow

access for the 19.7 Vdc adjustment.

Apply 200 percent load and check for a decrease in the frequency and the output voltage.
CAUTION

If the output voltage does not decrease noticeably
(approximately 1 V on H744, or 1 to 5 V on the
H745, H754, and H746), do not attempt the following short-circuit test.

Short circuit the output. The regulator should continue to operate at a low frequency with a

clean, smooth whistle and stable waveforms.

6-8

10.

Increase the voltage adjustment and observe the output voltage when the crowbar circuit
fires. The output voltage should be within the following ranges:

H744
H745
H746
H754

6.3.4

6.00--6.65 V
16.8-20.5 V
26.0-30.0 V
25.0--30.0 V and -6.00 through -7.00 V

H7420 Power Supply Subassembly Removal and Installation Procedures

The power supply access procedure enables the supply to be accessed for adjustments and subassembly

removal. The procedures listed below are described in the following paragraphs:
1.

Power supply access procedure.

é.

H744 regulator removal and installation.

5411086 15 V regulator/power line monitor board removal and installation.

Removal and installation procedures are similar for the H742 power supply.

6.3.4.1

Power Supply Access Procedure

Power down the equipment.

Fully extend the processor frame from the rack, ensuring that the cables do not bind.

Remove the ac power connection by disconnecting the H7420 power cord from the 861
power control.

CAUTION
Since both H7420s are connected to the same 861,

make certain that the correct H7420 power cord is
disconnected.

6.3.4.2

H744 Regulator Removal

Perform the power supply access procedure described above.
WARNING
Power must be removed prior to removing regulators.

Disconnect the Mate-N-L
ok connector from the regulator to be removed.

Remove the two screws and lockwashers that fasten the top of the regulator to the H7420
(Figure 6-2, Sheet 1 of 2). Loosen, but do not remove, the knurled screw that fastens the
bottom of the regulator to the H7420.

Slide the regulator out of the H7420 (Figure 6-2, Sheet 2 of 2).

6-9

7644-8

F igure 6 2

H7420 Regulator Removal (Sheet 1 of 2)

6-10

7644-2

Figure 6-2

H7420 Regulator Removal (Sheet 2 of 2)

6.3.4.3 H744 Regulator Installation — The following steps describe the procedure for installing H744
regulators in the H7420.
1.

Perform the power supply access procedure (Paragraph 6.3.4.2).

Power must
regulators.

2.
3.

WARNING
removed prior

installing

Place the H744 regulator in the correct position in the H7420. Tighten the knurled screw on

the bottom of the H7420.

Fasten the top of the H744 to the H7420 with two screws and lockwashers.

Connect the Mate-N-Lok connector (in the power harness) for this regulator position to the
connector on the top of the regulator.

6.3.4.4
1.

Turn on power and measure the regulator voltage at the processor backplane (Paragraph
6.2.2.1). Adjust the voltage (Paragraph 6.2.2.1) if the measured voltage is not within the
tolerances listed in Table 6-2.
5411086 15 V Regulator/Power Line Monitor Board Removal
Perform the power supply access procedures described in Paragraph 6.3.2.

Power must be
5410086 board.

WARNING
removed prior

removing

the

Remove the two screws at the top of the PC mounting board bracket (Figure 6-3, Sheet 1 of
3). The bracket then swings down from the top and remains suspended from the bottom
edge.

Remove the two hex nuts from the end of the 5411086 board (Figure 6-3, Sheet 2 of 3). Do
not lose the attached hardware (screws, washers, and spacers).

Remove the 5411086 board from the PC mounting board bracket. This is accomplished by
carefully pulling the board to separate the edge connector on the board from J1 (Figure 6-3,
Sheet 3 of 3).

6-12

7545-22

Figure 6-3

5411086 Removal (H7420) (Sheet 1 of 3)

6-13

REMOVE

Figure 6-3

6.3.4.5
1.

5411086 Removal (H7420) (Sheet 2 of 3)

5411086 15 V Regulator/Power Line Monitor Board Installation
Perform the power supply access procedure in Paragraph 6.3.4.2.
WARNING

Power must be removed prior to installing the
5411086.

Connect the edge connector on the 5411086 to J1. (Refer to Figure 6-15.)

Fasten the opposite end of the board to the PC mounting board bracket with the necessary

Attach the top of the PC mounting board to the H7420 chassis with two screws and washers.

hardware (screws, washers, spacers, and hex nuts).

6-14

|uppeg POWER suppyy
H742g

7545-25

Figure 6-3
5.

5411086 Removal (H7420) (Sheet 3 of 3)

Turn on power and check the backplane voltages (upper H7420: +15 V and +8 V; lower
H7420: =15 V). Refer to Paragraph 6.2.2.1 for 5411086 voltage check and adjustment
procedures.

6.4

Power down the equipment.

Carefully push the processor frame into the cabinet, observing that the cables do not bind.

CPU MAINTENANCE

Maintenance of the PDP-11/45, 11/50, 11/55 CPU consists mainly of running diagnostic tests and

making the adjustments, if any, that may be required.

The following groups of diagnostic programs are applicable for the basic PDP-11/45, 11/50, 11/55
DB W=

system and options:

KB11-A, D Central Processor Unit Diagnostics
|
Memory System Diagnostics

FP11-B, C Floating-Point Processor Diagnostics
KT11-C, CD Memory Management Unit Diagnostics
KL11 Teletype Unit Diagnostics
KW11-L Line Clock Diagnostics

6-15

Diagnostic programs for all MF11 memory systems are listed in Paragraph 8.4; those for the MMSI11,
FP11, and KT11 options are described in Chapter 7.
Diagnostic programs for peripherals and I/O devices in the system are listed and described in their
associated maintenance manuals. Detailed descriptions and specific operating procedures for each
diagnostic program are provided in related diagnostic program description (MAINDEC) documentation. A Libkit lists all the diagnostics that are supplied with a particular piece of equipment.
The following program naming convention is now in use for MAINDECs.
Program Naming Convention 1 is a test written for the PDP-11/45 to test the FP11 option and is test

number K version A.

CFPKA-X
T

L MCN level

X = no MCN ever issued
0 = initial MCN announcing latest program version
1-9

A thru Z

latest MCN rev level

revision designation

A thru Z = program designation
0 thru 9 = overlay designation

2 digits = option designation

QO MTmMDY
Ow

11/34 processor

11/04 processor

11/05, 15, 20 processors

all processors

“

A =

11/40 processor

11/45 processor

11/05 only

11/70 processor

= DEC/X11 exerciser software

D indicates a Diagnostic Program, and is not used
in naming a program.

Program Naming Convention 1

6.4.1
KB11-A, D CPU Diagnostics
In general, all diagnostic programs are loaded into the lowest 4K words of physical memory. All
diagnostic programs start at address 200. The programs run in Kernel mode. If the KT11-C, CD
option is implemented in the system it is disabled by clearing SRO bit 0.

6-16

Any trap or interrupt vectors not used by the test in progress are set up as ‘““‘trap catchers;” the new PC,
stored in the first word of the vector, points to the second word of the vector, which contains a 0. When
the 0 is fetched as an instruction, the processor interprets it as a HALT instruction. The instruction
being executed when the trap occurred can be identified as follows:
1.

Do a REG EXAM operation to determine the contents of register 6.

Set the number found in R6 in the switch register and do a LOAD ADRS operation.
Do an EXAM operation to determine the contents of the top word in the stack. This is the
PC at the time that the false trap/interrupt occurred.

Set the same number minus two, four or six, depending upon addressing mode, into the
switch register and perform a LOAD ADRS operation.

Perform a second EXAM operation to determine the instruction. This procedure will fail if
the last instruction before the trap altered the PC.

Whenever an error is identified by a diagnostic program the program executes a HALT instruction.
The location of the HALT identifies the type of error identified. To loop continuously through a
particular test, replace the instruction following the HALT with a branch instruction to a location
preceding the test — if possible, to a SCOPE instruction (if the test is failing consistently, the branch can
replace the HALT instruction). The SCOPE instruction is a MOV PC, R1 (octal code 010701) in the
DCKB tests. The later type of SCOPE provides a tag that identifies the last successfully completed
subtest.

The diagnostic programs are listed in Table 6-3 in the order in which they are normally run.
Table 6-3

KB11-A, D Central Processor Unit Diagnostic Programs

Number

Tests

MAINDEC-11-DCKBA-

Sign extend instruction

MAINDEC-11-DCKBB-

Subtract one and branch instruction

MAINDEC-11-DCKBC-

Exclusive-OR instruction

MAINDEC-11-DCKBD-

Mark instruction test

MAINDEC-11-DCKBE-

Trap and interrupt return

MAINDEC-11-DCKBF-

Stack limit test

MAINDEC-11-DCKBG-

Set priority level instruction

MAINDEC-11-DCKBH-

MAINDEC-11-DCKBI-

Arithmetic shift instruction

MAINDEC-11-DCKBIJ-

Arithmetic shift combined instruction

MAINDEC-11-DCKBK-

Multiply instruction

MAINDEC-11-DCKBL-

Divide instruction

MAINDEC-11-DCKBM-

Trap instructions and error traps

MAINDEC-11-DCKBN-

Program interrupt request test

MAINDEC-11-DCKBO-

Processor states test

MAINDEC-11-DCKBP-

Power fail test

MAINDEC-11-DCKBQ-

Console test

MAINDEC-11-DCKBR-*

CPU Parity test

MAINDEC-11-DCQKC-

Instruction exerciser

*Used only with systems containing Parity Memory.

DCKBA SXT Instruction - This is a test of the SXT instruction that ensures correct results and
condition code operation. The SXT instruction is tested in all address modes in a general register and
the PC.

DCKBB SOB Instruction - This is a test of the SOB instruction that ensures correct branching and
condition code operation.
DCKBC XOR Instruction - This is a test of the XOR instruction that ensures correct results and
condition code operation. The XOR instruction is executed using various operands; all address modes
are executed using a general register and the PC.
DCKBD MARK Instruction - This is a test of the MARK instruction. The test executes the MARK
instruction using all values of “N” and checks the results. Correct condition code operation is also
tested.

DCKBE RTT Instruction - This is a test of the RTT and RTI instructions and uses *“T"’ bit traps in the
test. Proper stack operation and proper status changes are tested.
DCKBEF Stack Limit Test — This is a test of the stack limit register and ensures correct YELLOW zone
and RED zone boundaries, and overflow traps for all values of the stack limit register (dependent on
available memory).

DCKBG SPL Instruction — This is a test of the SPL instruction. The test checks that only the priority
level bits in the PSW (PS7-5) are affected by the SPL instruction,
DCKBH 11/45, 11/50, 11/55 Registers - This is a test of all the PDP-11/45, 11/50, 11/55 hardware
registers (R10-R15), supervisor stack pointer (R16), user stack pointer (R17), and the microbreak
register. This test ensures that all bits in each of the registers can be set and cleared, and are selected
properly.
DCKBI ASH Instruction — This is a test of the ASH instruction. It tests ASH with different shift
counts and in all the registers.

DCKBJ ASHC Instruction - This is a test of the ASHC instruction. It tests ASHC with different shift
counts and in all the registers, including odd registers (test of circular shift).
DCKBK MUL Instruction - This is a test of the MUL instruction. It tests MUL with different
number patterns in all registers, including single precision (odd registers).
DCKBL DIV Instruction - This is a test of the DIV instruction. It tests DIV with different number
patterns in all even registers. Error conditions are also checked.
DCKBM Traps Test - This program tests all trap instructions and error traps (time out, odd address,
and overflow). Interrupt logic is also tested, using the Teletype.
DCKBN PIRQ Interrupt — This is a test of the program interrupt request (PIRQ) logic.
DCKBO 11/45, 11/50, 11/55 Processor States — This program tests that PDP-11/45 instructions are
executed properly in the three 11/45 modes (Kernel, Supervisor, and User). Also, the MIPD/I and
MFPD/I instructions are tested.

6-18

DCKBP 11/45, 11/50, 11/55 Power Fail Test — This test checks out the power fail system.
DCKBQ - This test checks out the console.

DCKBR - This program will test parity aborts during CPU execution of read/restore (DATI) and
read /pause (DATIP) memory operations. Normal parity is generated when writing to Memory
(DATO) and checked for “other” parity when reading from memory (DATI or DATIP). Parity aborts
are forced by setting a Parity Control Register for “other” parity (not normal) before execution of
DATI or DATIP instructions.

This program does not test memory; it tests the processor and assumes memory to be functioning
properly. MAINDEC-11-DCMFA will test memory and should be run in conjunction with this program to provide a through test of parity.

DCQKC - This diagnostic program is designed to be a comprehensive check of the PDP-11/45, 11/50,
11/55 processors. The program executes each instruction in all address modes and includes tests for
traps and the Teletype interrupt sequence. The program relocates the test code throughout memory, 0124K.

Table 6-4 lists the 13 general PDP-11 processor diagnostic programs. Each program thoroughly exercises a given instruction group. These programs are available as an additional CPU troubleshooting
aid. They are the original PDP-11 CPU diagnostics; however, they now can only be obtained under the
new MAINDEC numbers.

Table 6-4

General PDP-11 Processor Diagnostic Programs

MAINDEC No. *

Instructions Tested

Old

New

DOAA

DZKAA-A

Branch

DZKAB-A

Condition Branch

DODA
DOEA
DOFA

DZKAD-A
DZKAE-A
DZKAF-A

Unary and Binary
Rotate/Shift
Compare Non-Equality

DOHA

DZKAH-A

DOBA

DOCA

DOGA

DZKAC-A

Unary

DZKAG-A

Compare Equality

DOIA

DZKAI-A

DOKA

DZKAK-A

DOJA

DOLA

DOMA

Move

BIS, BIC, BIT

DZKAJ-A

Add

DZKAL-A

JMP

DZKAM-A

Subtract

JSR, RTS, RTI

* All numbers are preceded by MAINDEC-11-.

6-19

6.5
HOW TO USE MAINTENANCE CARDS
The maintenance card that is used to perform maintenance tests and troubleshooting procedures on
the PDP-11/45, 11/50, 11/55 system is shown in Figure 6-4. The maintenance card is constructed from
a WI131 maintenance module. The W131 is used with a W133 driver module. Figure 6-5 shows the
special overlay that is used to designate switches and indicators for the KB11-A, D and FP11-B, C test
functions. Table 6-5 lists the indicator lamp functions and the sources of the inputs from the KB11-A,
D and FP11-B, C.

NOTE
The KB11-A uses one maintenance card. With an
FP11-B also installed, another card is required for
maintenance procedures. The KB11-D and FP11-C,
however,

together

only

require one

maintenance

card.
Clock Selection
CLK switch S3 is used to select the crystal clock (XTAL), the RC maintenance clock (RC), or the
MAINT STPR switch as the timing source for the CPU or FPP. The KB11-A timing and FP11-B
timing are independent; thus the switches on each maintenance card need not be set for the same
selection. The FP11-C clock is syncronized to the KB11-D clock; thus settings on the one maintenance
card effect the speed and maintenance mode of both the KB11-D and FP11-C.

#RW
BB AR

6.5.1

»*
2

A223-4

Figure 6-4

Maintenance Card Installed for Test Purposes

6-20

Table 6-5

Indicator

TPH

Maintenance Card Indicators

Source

KB11-A and KB11-D/FP11-C
TIGA TPHMATH

Signal Description

FP11-B

FRHJ MSTEP CLOCK (0) H

KB11-A, D:

Basic processor

timing pulse, whether crystal

clock, RC clock, or MAINT
STPR is selected.
FP11-B, C:

Indicates MAINT

STPR clock pulse.
T1 through TS

TIGA(T1:T5) MAT H

FRHH (T1S:T4S) H

Indicates major time states for
KBI11-A, D and FP11-B, C. TS

is not used for FP11-B.
BUST

UBCB BUST MAT H

KB11-A, D Bust Cycle. Not
asserted by FP11-B, C.

MEM

TMCF MEM H

MS11 Semicondutor Memory System response to Fastbus memory

address. From SMC Module

(MOS-M8110, Bipolar-M8120).
REF REQ 1

REF REQ 2

SMCA RREQ IN PROG H

Indicates

semiconductor

(1st SMC)

memory

SMCA RREQ IN PROG H

gress.

(2nd SMC)

SMC module that is control-

recycle

Asserted

only

pro-

by an

ling Memory Matrix
Modules.
EN T3 DLY

TIGB ENABLE T3 DLY H

Asserts

TIGA

STOP T3

when KT11-C, CD option is
installed and enabled.

BBSY

UBCA BBSY MATH

MSYN

UBCB MSYN B MAT H

Indicates Unibus A is busy.
Indicates

Unibus

Master

Slave

Sync is asserted.
SSYN

UBCC SSYN MATH

Indicates

Unibus

Sync is asserted.
CNTL OK

UBCA CONTROL OK MATH

UBCA CONTROL OK MAT H

Asserted by processor to allow Fastbus memory cycle to

be completed by MS11.
FP SYNC

UBCE FP SYNCH

UBCE FP SYNC H

Indicates that the FP11-B, C
is ready to send or receive

data. Asserted by

FRMJ FP

SYNC L.
FP REQ

RACK FP REQH

RACHFP REQH

Used with FP SYNC to in-

dicate to CPU that more data
words

are

SYNC

required.
returned

If FP
CPU

without FP REQ, the memory cycles are terminated.

6-21

Table 6-5
Indicator

FP ATTN

Maintenance Card Indicator (Cont)
Source

KB11-A and KB11-D/FP11-C
UBCD FP ATTN H

Signal Description

FP11-B

UBCD FP ATTN H

Decoded

from

CPU

ROM

states where MSC = 5, indicating floating-point instruc-

tion has been decoded.
FP WAIT

FRHH WAITS H

Represents the Wait state of
the FP11-B.

CPFC1/FPEC1

No connection

Spare indicator.

For future

use, wire to row E, pin Cl
(FPP)

row

CI1

(CPU).
AERF

TMCC AERRF MAT H

TMCC AERF MAT H

Indicates state of KB11-A, D
Address Error Flag.

SERF

TMCC SERF MAT H

Indicates state of KB11-A, D
Stack Error Flag.

PAR ERR

UBCB PARITY ERR MAT H

Indicates Unibus A or Fast-

bus memory has detected a
parity error.

TMCB PS04 MAT H

Indicates

processor

status

word trace bit is set.
IRCHMAT N H

FRLP FN (1) H

KB11-A, D: N (negative) bit of
the CPU processor status
word condition code.
FP11-B, C: N bit of the FPP
program status register.

IRCHMAT Z H

FRLP FZ (1) H

KB11-A, D:

Z (zero) bit of the

CPU processor

status word

condition code.
FP11-B, C:

Z bit of the FPP

program status register.

IRCHMAT VH

FRLP FV (1) H

KB11-A, D: V (overflow) bit of
the

CPU

processor

status

word condition code.

FP11-B, C:

V bit of the FPP

program status register.

IRCHMATCH

FRLP FC (1) H

KB11-A, D:
CPU

C (carry) bit of the

processor

status word

condition code.
FP11-B, C:

C bit of the FPP

program status register.

6-22

aeH |T

|T2

|T3

|Ta

cPFCI|EN T3

|BUST|

Req | ATTN | WA

|REQ;

NORM FF!
orm

|REQ>

1 PB

|cerr|SERF

|FY |- €

CLK

CNTL

P | FP_ | FP | FP_TREF [ REF [acrel

syNC|

MAINT

roM

[110

cveL

TM | 1]

STPR =»

P/N 5509974-0-0

n-1077

Figure 6-5 Maintenance Card Control and Indicator Overlay
for KB11-A,D and FP11-B,C Test Procedures

When S3 is set to XTAL, the 33.3 MHz crystal clock is selected for the CPU timing source and the 18
MHz crystal clock is selected for the FPP. When the CLK switch is set to RC, the variable frequency
RC maintenance clock is selected as the timing source. By setting the potentiometer (Table 6-6), the
useful range of the period of the RC maintenance clock pulse can be adjusted. Note that this potentiometer (on both the TIG and FRH boards) is mounted on the front edge of the module and thus does
not require W900 Extender modules to be adjusted.
NOTE
When using both KB11-A and FP11-B RC clocks,
half of the FP11-B clock period must be shorter than
two KB11-A ROM cycles. This ratio must be main-__

tained when using the RC clock or single-stepping f
the FP11-B, otherwise the two processors will not
remain syncronized.
Table 6-6

RC Maintenance Clock Pulse Adjustment

Potentiometer

Module

Module Location

Range (ns)

Device Affected

R162

M8109 (TIG)

KBI11-A

28—-50*% _

KB11-A

R32

M8114 (FRH)

FP11-B

50-290*

FP11-B

R162

M8109 (TIG)

KB11-D_

27—-450 _

KB11-D, FP11-C

*See note above on RC clocks

6.5.2

Maintenance Mode Control

Maintenance card switches S2 and

S1 are used to select the maintenance mode, as indicated in Table 6-

6.5.2.1

Single ROM Cycle - When switches S1 and S2 are set for single ROM cycle mode, the

processor will proceed through a single ROM cycle each time the console CONT switch is pressed. For
convenience, MAINT STPR switch S4 on the maintenance card can also be used to initiate the single
ROM cycle. In this mode of maintenance operation, TIGA STOP T3 L is asserted at time state T1,
causing the processor to stop at time state T2 of each microstate.

6-23

Table 6-7
S2

Mode

NORM OP

uPB STOP

Maintenance Mode Selection
Operation

No effect on KB11-A, D or FP11-B, C operation.

The KB11-A, D or FP11-B, C will execute instructions until the
microprogram ROM address matches the contents of the Program

Break (PB) register. It halts at T2 of that ROM state.
1

ROM CYCL

The KB11-A, D or FP11-B, C will execute a single ROM state each time the

MAINT STPR is pressed.

SING TP

The basic clock changes state each time the MAINT STPR is pressed. Thus,
pressing MAINT STPR twice provides a single time pulse.

6.5.2.2

uPB STOP - When switches S1 and S2 are set for uPB (microprogram break) STOP mode,
the KB11-A, D or FP11-B, C will continue to execute program instructions each time CONT is
pressed, until the ROM address register contents match the Program Break (PB) Register contents.
When both microstate addresses are equal, the processor stops at time state T2 of the selected microstate. At that point, S1 and S2 can be set for SING TP mode as described in Paragraph 6.5.2.3. Load
the PB with the desired microprogram address as follows:

Press HALT switch. Processor halts at microprogram CON.00 (CPU uADRS 170).

Set PB register address 777770 into console switch register.

Press LOAD ADRS. ADDRESS display will be 777770.

Set desired microprogram break address into the low byte of the switch register. For
example, to stop at FET.00, set 2175 into the switch register.

Press DEP. The DATA display will display this input in the low order byte with the Data
Display Select switch set to DATA PATHS.

Press CONT. The processor will execute program instructions until the RAR equals the PB,
then stop.

6.5.2.3 Single Step - When switches S1 and S2 are set for SING TP mode, gating logic shown on
drawing TIGB inhibits the source synchronizer from selecting either the crystal clock or the RC
maintenance clock. Under these conditions, each time MAINT STPR switch S4 is pressed, TP H
changes levels.
NOTE
MAINT STPR must be pressed twice to complete
each time pulse.

This feature allows events that occur on the leading edge or trailing edge of the same time pulse to be
examined separately.
6.5.3 Using the Maintenance Card with KB11-A, D
Chapter 7 of the KB11-A, D Central Processor Unit Maintenance Manual explains how to use the
processor flow diagrams. The same compare instruction example is used to demonstrate how to use the
maintenance card for test purposes.

6-24

6.5.3.1

Deposit Test Instruction — Set the Address Display Select switch to CONS PHY, load address

1000, and deposit the Test Instruction 6-1.
Address

Data

(octal)

Comments

1000
1002
1004

022767
000015
000100

Compare instruction,
Source operand immediate
Destination operand indexed

1106

000000

Word =0

Test Instruction 6-1
uPB STOP MODE - This setup loads the test instruction address into PCA; then into PCB.
The processor performs the RES.00 microprogram sequence (flows 3) and then fetches the test
instruction.
L=

6.5.3.2

Set up the PB for a uPB STOP at FET.10 (CPU uADRS 260).
Load address 1000s.
Set maintenance card switches S1 and S2 for uPB STOP mode.
Set ENAB/HALT to ENABL and press START.

The processor will stop at FET.10 microstate 260 in T2. Refer to Paragraph 6.4 in the KB11-A, D
manual to review the processor events. Table 6-8 indicates normal console indications as a result of
these events.

Table 6-8

Console Indications

Console Display

Contents (octal)

ADDRESS:

CON PHYS

1000

DATA:

DATA PATHS

1002

BUST REGISTER

1000

tADRS FPP/CPU

260

PAUSE
Maintenance card indicator T2

lights.

6.5.3.3 Single ROM Cycle Mode - This setup causes the processor to execute one ROM cycle of the
test instruction and stop each time MAINT STPR switch S4 is pressed.

1.
2.

Set maintenance card switches S1 and S2 for single ROM cycle mode.
Press maintenance card MAINT STPR switch S4 or CONT switch on the console.

Refer to the test instruction description in the K11-A, D manual, Paragraph 6.4. Table 6-9 lists
normal ADDRESS and DATA displays resulting from each ROM cycle execution, starting with
FET.10, T2 of the example test instruction.

6-25

Table 6-9 Normal Display Indications for Single ROM Cycle Example
After Executing

The Console Displays will be:

ROM Microstate: | \ppSCPU | DATA PATH
FET.10

343

1002

$13.10
D67.80
D67.00
D67.10
D10.30
D10.60

117
006
251
122
177
~FAST 032

5
1006
1106
5
15
_16%*

TST.00

217

TST.01

260

IRD.00
$13.00

BUS REGISTER

022
027

FAST 033

1004
1004

ADDRESS CON PHYS

022767

1002

15
15
100
100
15
0

1004*
1004
1004
1106
1106
1006

022767
022767

1002
1002

Indicates BUST

** 1’s complement of 15

—

Determined by next instruction; not included in this example.

6.5.3.4 SING TP Mode - This procedure allows the maintenance card user to step through microstates of the test instructions example in the SING TP mode.
1.
2.
3.
4,

Set ENABL/HALT to HALT and press START.
Load the example instruction address 1000.
Set maintenance card switches S1 and S2 to uPB STOP mode.
Set ENABL/HALT to ENABL and press START.

When the processor stops at T2 of FET.10 (CPU wADRS 260), set S1 and S2 to select SING TP mode.
Then press MAINT STPR switch S4 twice to step through each time state.
NOTE
A time state is only valid when the associated time

state indicator and the TP H indicator are both lit.

Table 6-9 lists the normal DATA and ADDRESS displays for each time state of the example, starting
with T2 of FET.10 (CPU uADRS 260).

NOTE
The example assumes the test instruction is deposited in a semiconductor memory location.

If the test instruction is deposited in a core memory location, Unibus control signals MSYN and
SSYN will be displayed on the maintenance card indicators. Also, if the KT11-C, CD option is implemented, the EN T3 DLY indicator lights. While EN T3 is lit, the processor will remain in T2 until the
delay counter is stepped through three complete time periods.

6-26

6.6

HOW TO USE THE W900 MODULE EXTENDERS

The W900 module extender is a double-height, multilayer etch board that provides one-to-one connections between module connectors and corresponding CPU backplane connector slots. Thus, three

W900 module extenders can be used to extend a PDP-11/45 hex-size module from the CPU backplane
to provide access to ICs and discrete components for test purposes under active operating conditions.
Alternatively the W904 hex height multilayer extender can be used.
NOTE

Do not attempt to extend more than one module at a
time while performing test procedures.

6.7

MODULE AND ASSEMBLY REMOVAL AND REPLACEMENT

No special procedures are required to disassemble and reassemble most of the components and assemblies in the H960-C cabinet or the BA11-FA mounting box. This paragraph outlines the procedures for
removing and replacing modules and the steps required to disassemble the console.
6.7.1

Module Removal and Replacement

The multilayer modules used in the PDP-11/45, 11/50, 11/55 are equipped with lock/release type
handles, and each slot in the backplane has card edge and center guides that allow the modules to be
installed easily. The card guides ensure that the modules are not removed or inserted at an angle so
great that module or connector slots are damaged.

CAUTION

Even though these features are provided, always
install and remove the modules carefully.

Console Disassembly

6.7.2

Refer to Figure 6-6. The following steps are required to disassemble the console. (Note that very-earlymanufactured 11/45 systems have a slightly different console mounting bracket, but disassembly is
similar.)

Turn power OFF at the circuit breakers.

Remove the four screws (A) and washers that secure the bezel (B); remove the bezel.

Remove the five screws (C) and washers that secure the console panel (D); remove the

console panel.

Unplug the harness power plug P1 from J3 and the signal cables from J1 and J2.

Remove the three screws (E) and washérs that hold the bottom of the console PC board to

the processor mounting box. Also remove the three screws (F), washers, and spacers (G)
that hold the top of the console PC board to the processor mounting box. This will free the
PC board (H).

Reassembly requires reversal of the previous steps.

6-27

e
i

41-4305

Figure 6-6

Console Assembly

To replace a faulty indicator bulb on the console, follow the above steps 1 through 5 and replace the
faulty indicators. This requires soldering. When indicator replacement has been completed, test all
indicators. Reassemble the console partially for indicator testing by reversing steps 5 and 4. Test all
indicators by turning power ON at the circuit breakers and lifting the indicator test switch. This is an
unlabeled white switch located between switch register bit 0 and the LOAD ADRS switch. All

indicator bulbs should light. Turn power OFF at circuit breakers before reassembing the console.
6.8

REMOVAL AND REPLACEMENT OF ICs
The PDP-11/45, 11/50, 11/55 modules are multilayer etched circuit boards. The four layers consist of

two power and ground internal planes, and two etched circuit external layers (Figure 6-7). The inner
power and ground planes form a decoupling capacitor between the power and ground planes providing shielding between the etched circuit layers and reducing the possibility of noise and crosstalk. One
advantage in using this type of module construction is that the need to route power and ground signals
to each individual component and IC via etching on the two outer etched boards is eliminated, allowing a much greater component density on each board.
6.8.1

Location of ICs
On the handle end of the board, the physical location of the last IC in each row is E-numbered to aid in
locating ICs during maintenance and troubleshooting.

The first sheet of each module circuit schematic is a physical layout showing the location of the ICs
and discrete components on that module.

6-28

ETCH

LAYER

SIDE

No. 1

COMPONENT SlDE_l

sroond taven ot
N N NN N NN NN NN NN

J¢— POWER

NANANANAN N

LETCH LAYER SIDE No. 2
Figure 6-7

N ousss evony
(+5V)

LAYER

——

11-0959

Cross Section of Multilayer Board

When possible, some IC locations on most boards are not used; these spare locations, provided on a
space available basis, ensure that if future ECOs (engineering change orders) involving additions are
required, they can be more easily implemented.
When spare locations are provided on the module, each spare location has a number just like one of
the ICs. The spare locations must also be counted when locating ICs on the board.
When an IC is added to a board (e.g., because of an ECO), the IC assumes the preassigned number of
the location into which it is installed. Thus the numbered IC locations at the handle end of the board,
as well as all other IC locations, always remain the same.
6.8.2

IC Connections
IC and component connections to the power and/or ground inner layers are normally made as shown

in Figure 6-8A. The ICs and components are connected to the inner layers in this manner to allow the
IC or component to be more easily replaced.

When a component is tied directly to an inner layer as shown in Figure 6-8B, instead of connecting
through an etch as shown in Figure 6-8A, it is difficult to remove the component because most of the
heat from the soldering iron is absorbed by the inner layer, preventing the solder around the leads of
the component or IC from melting. To minimize this difficulty, direct connections to the inner layer
are made by a vein-type connection as shown in Figure 6-9. This type of connection reduces the

connected area between the plated-through hole and the inner layer. This reduces the amount of heat
transfer to the inner layer when heat is applied to the plated-through hole when melting solder and
removing component leads, or removing excess solder once the lead has been removed.
6.8.3 IC and Component Removal and Replacement
|
Because the etch and plated-through hole eyelets are so small, extra care shold be taken during the
maintenance and repair of the multilayer modules, especially when soldering and unsoldering components. Certain tools (or their equivalent) are recommended for use duing removal and replacement

of ICs on the multilayer modules; they are listed in Table 6-1. The manufacturer and type of part
number of each tool is indicated in parentheses at its first occurrence in the procedure.
6.8.3.1
Removal and Replacement of Plastic Case ICs - To remove and replace a plastic case IC and to
preclude damage to the multilayer board, the procedure described by Figures 6-10 through 6-17 should
be strictly adhered to. Removal and replacement of ceramic ICs are covered in Paragraph 6.8.3.2.

6-29

ETCH

CONNECTION

CONNECTION MADE TO
GROUND

LAYER

'
x

N A\ \
AN
E %

COMPONENT CONNECTION

CAP

SANANY/

CONNECTION
MADE TO___/
INNER POWER LAYER
B. COMPONENT

CONNECTED

HOLES

LAYER

CONNECTION

MADE TO

)

// e

& \

THROUGH

/_INNER GROUND LAYER
1

NO CONNECTION TO

INNER GROUND LAYER

TO INNER

AN N NS
NN

NORMAL

TO INNER PLANES

'\
PLATED

NO CONNECTION

;;

NO CONNECTION TO
INNER POWER LAYER

\———-—X——PLATED THROUGH HOLES
DIRECTLY

INNER

LAYERS
14~ 0961

Figure 6-8

Component Connections to Inner Layers

COMPONENT LEAD

INSUL ATING
LAYERS

PLATED THROUGH HOLE

INNER GROUND PLANE

CLEARANCE HOLE THROUGH
THE INNER PLANE

L VEIN CONNECTION BETWEEN INNER PLANE
AND PLATED THROUGH HOLE
11-2300

Figure 6-9

Top View of Component Connection Made Directly to Inner Layer

6-30

6201-1

This sample module is a G401 MOS Memory Matrix Module which has com-

ponents that are connected directly to the inner layers using the vein method
described in Figures 6-8 and 6-9.

Figure 6-10

Module to be Repaired and Tools Required

6-31

AN
6201-2

Defective IC leads are clipped, using small diagonal cutters (Utica, Part No. 47-4).

Cut the leads as close to the body of the IC as possible to allow the remaining
leads to be more easily removed.

Figure 6-11

Removing a Defective IC from the Module

6-32

IC location after the IC has been removed — with the IC leads still in the board.
Locate the leads of the IC just removed on the soldered (back) side of the board
and cut all leads to avoid difficulty during their removal

Figure 6-12

Defective IC Removed

6-33

6201-4

IC leads being removed from side 1 of the board. Apply heat to the lead until the
lead becomes loose. Then remove the lead by pinching with the soldering iron

(Paragon, Part No. 615) and pliers (Utica, Part No. 23-4).
CAUTION

Leads that are connected to an inner layer require
more heat because much of the heat is absorbed by
the inner layer. It is helpful to add solder to the lead

first causing more heat to be conducted to the solder in the eyelet around the lead.

Figure 6-13

Removing IC Leads

6-34

6201-6

Lead directly after removal from the eyelet using the soldering iron and pliers.

Figure 6-14

IC Lead Removed

6-35

After all of the IC leads have been removed, remove the excess solder remaining in
the eyelets prior to inserting the new IC. This figure shows solder being applied to

the eyelets after all the leads have been removed. The extra solder absorbs excess
heat and keeps it from being applied directly to the etch of the plated-through
holes

Figure 6-15

Applying Solder to Refill Eyelet

6-36

6201-9

Once the eyelets have been refilled with solder, as described in Figure 6-10,
remove the solder using the soldering iron and solder extractor as shown above. In

this figure, the eyelet has no connection to the board inner layers; thus, the solder
can be extracted from the same side of the module to which the heat is applied.

However, in cases where direct connegtions to the inner layer are made, heat must
be applied to one side of the

module and the solder must be extracted from the

opposite side due to the heat sinking properties of the inner layers. In this case, the

module should be in a vertical position to allow access to both sides of the module
simultaneously.

Figure 6-16

Removing Excess Solder from Eyelet
6-37

6201-8

IC location after all the eyelets have been cleared of solder.
Inspect the eyelets to ensure that no excess solder remains. If all the solder is
not removed, refill the hole as described in Figure 6-15 and remove the solder
again as described in Figure 6-16. Continue this procedure as required, until all
of the eyelets are cleared of excess solder.

Use a cleaning solvent and brush to clean the IC location of any excess solder
flux.

Thoroughly inspect the IC location and surrounding area for solder splash and
damage to etch lines and plated-through holes.
Ensure that none of the leads are bent, and insert the replacement IC in the

holes. When inserting the replacement IC into place, avoid bending the leads
on the opposite side of the module: this makes future removal of the IC easier,
should it be necessary.

CAUTION

If the leads must be bent to hold the IC in position

for soldering, avoid bending leads more than 45°,

using only one lead at each end and on opposite

sides of the IC.

Solder in the new IC from the opposite side of the module. Use enough solder
to fill the holes and make a good connection. Avoid using an excess of solder
to prevent overflow on the top side of the board, which could cause a short
under the body of the IC.

Once all the solder connections are made, clean and inspect the area for any
damage. Cut off IC leads close to the board. Take necessary corrective action
for any defects that are found.
CAUTION

After installing the ECO or replacing a faulty IC on a
module, ensure that no short circuit exists between

the power and ground planes of the module. Do this
before replacing the module in the equipment.

Figure 6-17

IC Location Ready for Insertion of New IC
6-38

6.8.3.2 Removal and Replacement of Ceramic ICs - Ceramic ICs require a different removal/replacement procedure than the plastic ICs because of their different construction. Leads of the
plastic ICs extend out and down from the case of the IC, whereas the leads on the ceramic ICs extend
straight down from the case of the IC, and are harder and thicker than those found on plastic ICs.
Thus, certain steps of the removal/replacement procedure for the plastic ICs do not apply to removal
and replacement of ceramic ICs. To remove a ceramic IC, use the following procedure:

Special diagonal cutters (DEC Part No. 29-12551) are required to remove ceramic ICs. (See
Figure 6-18) Cut all the IC leads and remove the IC from the module.

6201-7

Figure 6-18

Special Tool and Method Used to Clip Ceramic IC Leads

6-39

Inspect the component side of the module for any burrs that may be present from cutting the
IC lead. If any burrs are present, carefully remove them using the special diagonal cutters.

Perform procedure listed in Paragraph 6.8.3.1 starting with Figure 6-12.
NOTE
Because the leads will be cut flush with the board
surface, it is not possible to pinch leads between
pliers and soldering iron. Use the following procedure to remove leads.

Cut the leads on side 2 of the board to allow easy removal.

On side 1, heat the plate-through hole and extract lead and solder with solder extractor. If

lead cannot be extracted from side 1, try to extract it from side 2.
NOTE
Do not attempt to remove melted solder or lead by
banging the module on the bench.
6.8.4

Solder Mask Removal
Side 2 of PDP-11/45, 11/50, 11/55 module (the side opposite the component side) is coated with a
solder mask to prevent short circuits between adjacent electrical connection points. To repair side 2 of

these modules, scrape off the solder mask chemical. Use a knife or X-acto tool to remove the solder
mask.
6.9

SPECIAL MOS HANDLING PROCEDURES
Because of the high input impedance of MOS (metal oxide semiconductor) devices, they are susceptible to damage from static discharge. These devices, such as the Intel 1103-1, are employed extensively
on the G401 and G401YA MOS memory matrix modules.

Many manufacturers of MOS devices use various types of internal protection against damage from
static discharge. These types of protection range from Zener diodes to limiting resistors. However, the
effectiveness of these protection schemes is questionable and many manufacturers suggest that additional precautions be taken to ensure safe handling of these devices.
This paragraph outlines some basic rules for handling MOS devices in the field. The precautions taken
at the factory are more extensive than those that are practical for field implementation. Therefore, the
following rules represent only the basic requirements for safely handling MOS devices in the field.
These rules are intended to keep the MOS device at the same electrical potential as the work area,
tools, and personnel. Do not handle MOS devices in areas of high static susceptibility such as carpeted
areas or areas of extremely low humidity.
1.

Choose a work area that exhibits minimal potential for the generation of static electricity.

Use a power receptacle that has a connection to earth ground.

Only use a soldering iron that offers a 3-wire ground such as the new DEC-supplied soldering iron (DEC Part No. 29-13452). Do not use a transformer-type soldering iron.

Removal of defective MOS devices from a module requires no special handling procedures.
MOS devices, once soldered on the board, offer no danger of damage from static discharge.

6-40

If you are sitting in a chair while working with MOS devices, it is suggested that the chair be
electrically connected to the frame of the work table. If this is not possible, use care to
prevent the chair from touching the work table, thus preventing a static discharge from the
chair to the work table.

If you are standing while handling MOS devices, avoid rubbing your clothing against the
work table or nearby furniture, thereby preventing the build-up of static electricity.

7. MOS devices (as supplied by DEC) are phckaged in a conductive plastic bag. Before opening
the bag, touch the work table or metal connected to it to discharge any static build-up.

Empty the contents of the bag onto the work area without touching the MOS devices.

Prior to touching the MOS device, always discharge yourself by touching the work area or

attached metal.

10.

Insert the MOS device into the module using care to ensure minimal handling of the device
leads. Try to grasp the chip by the body of the device and not by its leads.

11.

Using the soldering techniques described in Paragraph 6.8.3.1, Figure 6-14, solder the MOS
device using the 3-wire grounded soldering iron. If a grounded iron is not available, always
attach a wire from the iron tip to ground (or the work area) to prevent any potential difference between the device and the soldering iron.
'

12.

Replace the unused spare MOS devices in the conductive plastic bag by grasping the body of
the IC, after previously discharging yourself against the work table. Reseal the bag using
tape or a stapler.

All of the above are precautions to reduce the possibility of a potential difference between the MOS
device being handled and the surrounding environment. Again, common sense is essential when choosing a good work area and method of handling these devices.

6.10

EQUIPMENT CONFIGURATION AND REVISION STATUS

The following paragraphs describe the MUL sticker, the ECO status sticker, and module revision
status. The MUL sticker lists the equipment complement system serial number, etc.; the ECO status
sticker provides information about the current ECO status of wire-wrap devices; module revision
status shows the current ECO status of the module.

6.10.1

Mechanical Status Sticker

See Figure 6-19. This sticker is located on the rear of the Mounting Box. Box Type is 11/45, 11/50,
11/55, H960-D or H960-E. A letter designates the Revision Level at Manufacturing. Field installed
ECOs should be entered as performed.

6.10.2

ECO Status Sticker

The ECO status sticker (Figure 6-20) is located on the inside of the module door in the CPU or BA11FB mounting box. This sticker is filled out for installation of ECOs to wire-wrap devices such as the
KBI11-A, D or the various system units. Table 6-10 describes how the various columns are to be filled
out and the department responsible for filling out these items. Later versions have an additional MUL
sticker for BA11-FB mounting boxes, used in expansion cabinets. It consists of nine system unit sections similar to those shown for system units 1, 2, and 3. It is used for the same purpose.

6-41

MECHANICAL STATUS
BOX TYPE

REVISION LEVEL AT MFG.

FIELD INSTALLED MECHANICAL ECOS
ECO NUMBER

Figure 6-19

Mechanical Status Sticker

%c STATUS
Device

Ser. No._@>_

NOJDATE[INIT| COMMENT

———0

DECI12
- (7176)-11097- N172
11-1498

Figure 6-20

ECO Sticker

6-42

Table 6-10 Completing the ECO Status Sticker
Description

Responsibility

Item No.

Production

Option designation code for applicable device (e.g.,
KB11-A, D, MM11-S, etc.).

Production

Device serial number.

Production

Original wire wrap revision letter (e.g., ORIGINAL REV.

Production/Field Service*

Numerical portion of ECO number (e.g., for ECO

Production/Field Service*

Installation date of ECO.

Production/Field Service*

Initials of person installing ECO.

Production/Field Service®

Necessary comments about ECO or its installation, (e.g.,

B).

KB11-0002 write only 02 in this column).

only part 2 installed).

* If option is installed in factory, production has responsibility for filling out ECO sticker. If the option is an add-on in the

field, field service will fill out items 4 through 7.
£2.19

cmertme wem 11

211

Zhnamnn

ae o

Note: ECO STATUS STICKER is located on the inside of the module door for BA11-FA and BA11-FB Mounting Boxes.

6.10.3

Module ECOs

Each module is stamped with the alphabet (except for G, I, and O) to record various circuit schematic
revisions to a module. When a module is shipped from the factory, the actual revision letter from
production is stamped on the handle. When ECOs that revise modules are installed in the field, scratch
off the appropriate letters from the module. For example, if an ECO corresponding to revision F of the
module were installed and an ECO corresponding to revision E of the module were not installed, the
letter F would be scratched out and the letter E would remain intact.

6.10.4

Module Utilization List (MUL) Sticker

This sticker (Figure 6-21), located on the top panel of the BA11-FA mounting box (left-hand side),
provides a quick convenient tabulation of the various equipments located in a particular processor
box. Additional information such as serial numbers, comments, technical tips, and installation of
partial ECOs is also shown on the sticker. Table 6-11 describes the manner in which the sticker is to be
filled out and indicates the department (production/field service) responsible for filling out the various
items.

06 - B 1473.N272

SYSTEM SERIAL N

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LATE INSTALLED .

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SYSTEM UNIT =1

SYSTEM UNIT =2

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erch | eten

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I UNIT SERIAL NO. (KB11)-

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Rev

rev.

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TIG

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f— )

_ POWER IS APPLIED 70 SemicoNbucTor | =ev

—

MEMORIES WITH CONSOLE SWITCH OFF

DATE INSTALLED-

CENTRAL PROCESSOR

FLOATING POINT

Tusico

weize uerzs [me127 f wa 26

mem \

fETCH

]

SYSTEM SERIAL NO.-

| BACKPLANE W.L. REV.—

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CONTLRY

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Rev

ercH | ETcH

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Rev | Rev | rev | orev | rev | rev | orev | Rev § Rev § Rev | REv | Rev | REV

rev

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rev

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C. KBI11-D Sticker (7415804-0-1)

Figure 6-21

—_

[vatr]matrix|matrixImatrix] mem

SERIAL NO.-

[ rev f R N —

— | ——|—
|

@«

New KBI1-A Sticker (7415804-0-0)

SERIAL NO-

rev

FLOATING POINT

—_ ] e | e |

SERIAL NO.SERIAL NO-

H1a-

e| e

SERIAL NO-

4.
1755

#13.

rev

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SERIAL NO.

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]

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frev

e Tee e T

CP |MEM.MGT.

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—_

rev

REv | Rev.

73—

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MEMORIES WITH CONSOLE SWITCH OFF

SERIAL NO.—

SU.

rev

S.P. CONTLS. |} SEMICONDUCTOR MEMORY | SEMICONDUCTOR ME\MQRY

— POWER IS APPLIED TO SEMICONDUCTOR

—

SU.#

U.72-

[

810,

SYSTEM SERIAL NO.—

DATE INSTALLED—

CENTRAL PROCESSOR
06 | M8

N\ evcH [ EvcH

{ even

VOLTAGE APPLIED

SYSTEM UNIT AND S.P.C. DEVICES
[

feren

Jes ) ces]ces

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. I
S.U.#1 -

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| rev | rev. | rev | orev | Rev.

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(-

evcH | even | eten | even

| BACKPLANE W.L. REV.—

CP | MEM.MGT.
N

— | — ] — ) rev. ] rev | rev | Rev. | orev.

| UNIT SERIAL NO. (KB11)-

=== === [
RN
[mavrimatrix matrix |[MaTRiX] MEM I matrix| matrix | mariy fratrc | MEm \
CONTL k
2
CONTL.

1775

VOLTAGE APPLIED

MUL Stickers
6-44

11-4307

Table 6-11
Item No.

Completing MUL Sticker

Responsibility

Description

Production

System Serial Number

Field Service

Acceptance Date of installation at customer site.

None

Unused

Field Service

Comment area. Note tech tips installed, partial ECOs, miscel-

laneous information about module or slot.
5

None

Production/Field Service*

For in-house use.

Enter memory type as installed (G401, G401YQ, M8111 ,

M8111-YA, M8121-YA). Comments should list address of
memory.

List option designation as installed (e.g., KL11, PC11, etc.).
Enter module type for control module (e.g., M780 for KL11,

etc.).

Production/Field Service*

Enter option serial number.
List system unit device type (e.g., MM11-S, DD11-A, MM11-F,
etc.).

Production/Field Service*

List system unit serial number.

Production/Field Service*

List option designation code devices within DD11-A, B, D if
applicable

(e.g.,

LP11,

CRI11,

etc.).

Also

include

small

peripheral serial numbers.
* To be filled out by production if option or device is factory installed, If option or device is an add-on in the field, field
service will complete these items.
Note: The MUL STICKER is located on the top of the KB11-A, D cover over the modules.

6-45

CHAPTER 7
PLUG-IN CARD OPTIONS

This chapter provides the information needed to install PC board options in an existing PDP-11 /45,
11/50, 11/55 system. Options included are:
FP11-B Floating Point Processor (for the KB11-A)
FP11-C FLoating Point Processor (for the KB11-D)
KT11-C Memory Management Unit (for the KB11-A)
KT11-CD Memory Management Unit (for the KB11-D)

MSI11 Semiconductor Memory Systems
KW11 Line Clock
Additional SPC Space

The DD11 system interfacing unit provides additional SPC slot positions for plug-in card options
other than those provided by the standard backplanes and system units. It is usually mounted in the
processor cabinet or expansion cabinet. The DD11-A and DD11-B each provide four SPC slots and
are described in the PDP-11 Peripherals Handbook. The DD11-D provides nine SPC slots and a modified Unibus connection. (A description of the DD11-D is provided in the PDP-11/34 System User
Guide - EK-11034-OP.)

7.1

FP11-B, C FLOATING POINT PROCESSOR

7.1.1
Installation
The following steps outline the procedure necessary to install the FP11-B, C Floating-Point Processor.
1.

Turn power off at the console by shutting off both circuit breakers on the power supplies.

Install the H744 +5 V regulator in slot A of the upper H742 power supply as indicated on
the power supply decal located at the rear of the CPU mounting box.
Install FRH module (M8114 for the FP11-B or M8126 for the FP11-C) in slot 2 of the CPU
backplane assembly (Figure 5-12).

Install FRL module (M8115 for the FP11-B or M8127 for the FP11-C) in slot 3 of the CPU
backplane assembly.
Install FRM module (M8112 for the FP11-B or M 8128 for the FP11-C) in slot 4 of the CPU
backplane assembly.
Install FXP module (M8113 for the FP11-B
or M8129 for the FP11-C) in slot 5 of the CPU
backplane assembly.

7-1

Turn circuit breakers on and recheck the +5 Vdc and -15 Vdc regulator outputs for proper
voltages. Readjust as required in accordance with Paragraph 6.2.2. Refer to Table 6-2 for
test points.

Set the Data Display switch on the console to uADRS FPP/CPU and press the HALT
switch. The FP11-B, C microaddress should display 076. Connect an oscilloscope probe to
A2A1 to determine that the oscillator is running. Press the START switch and check that
the FP11-B, C cycles back to address 076.

Run the diagnostic programs listed below.

7.2

FP11 DIAGNOSTICS

7.2.1

FP11-B Diagnostics

Table 7-1 lists the diagnostic programs for the FP11-B Floating-Point Processor. These programs test
the FP11-B in all modes with fixed number patterns. Additional test procedures for the FP11-B are
provided in Paragraph 7.1.5.

Table 7-1

FP11-B Floating-Point Processor Diagnostic Programs

Number

Tests

MAINDEC-11-DCFPA-

CFCC, LDFPS, STFPS, SETI, SETL, SETF, and SETD Diagnostic

MAINDEC-11-DCFPB-

STST Diagnostic

MAINDEC-11-DCFPC-

LDF and STF, LDD and STD Diagnostic

MAINDEC-11-DCFPD-

ADDF and SUBF, ADDD and SUBD Diagnostic

MAINDEC-11-DCFPE-

CMPF, CMPD Diagnostic

MAINDEC-11-DCFPF-

MULF, MULD Diagnostic

MAINDEC-11-DCFPG-

DIVF, DIVD Diagnostic

MAINDEC-11-DCFPH-

CLRF, NEGF, ABSF, and TSTF Diagnostic

MAINDEC-11-DCFPI-

LDCDF, LDCFD, STCFD, and STCDF Diagnostic

MAINDEC-11-DCFPJ-

LDCIF, LDCID, LDCLF, LDCLD, STCFI, STCFL, STCKI, and STCDL Diagnostic

MAINDEC-11-DCFPK-

LDEXP and STEXP Diagnostic

MAINDEC-11-DCFPL-

MODF and MODD Diagnostic

MAINDEC-11-DCFPM-

LDUB, LDSC, STAO, MRS, and STQO Maintenance Instructions

MAINDEC-11-DCFPO-

Exercises all instructions

MAINDEC-11-DCFPR-

LDD and STD Exerciser

MAINDEC-11-DCFPS-

ADDF, ADDD, SUBF, and SUBD Exerciser

MAINDEC-11-DCFPT-

MULF and MULD Exerciser

MAINDEC-11-DCFPU-

DIVF and DIVD Exerciser

MAINDEC-11-DCQOA

OVERLAY

DCFPA through DCFPL Diagnostic - These programs test the FP11-B in all modes with fixed number patterns. The programs should be run in order for at least two passes with all switches down.
DCFPM Maintenance Instruction Test — This program tests the maintenance instructions and
microtraps.
DCFPO Basic Instruction Exerciser - This program is a general test of all instructions.

7-2

DCFPR LDD/STD Exerciser — This program tests the load and store instructions, using random

numbers.
DCFPS Add and Subtract Exerciser — This program tests the add and subtract instructions, using

random numbers, and compares the results of these instructions with FORTRAN software.
DCFPT Multiply Exerciser — This program tests the multiply instruction, using random numbers, and
compares the results of this instruction with FORTRAN software.

DCFPU Divide Exerciser — This program tests the divide instruction, using random numbers, and
compares the results of this instruction with FORTRAN software.
DCQOA - Overlay diagnostic.
7.2.2
FP11-C Diagnostics
The diagnostic programs for the FP11-C Floating Point Point Processor are listed below. These programs consist of 237(8) individual tests designed and sequenced to detect and identify logic faults at a
minimum hardware/software level. These tests are partitioned into two stand-alone programs as
described below.
DEFPA Basic Instruction Tests — This program is a logically sequenced set of instruction tests
designed to verify the logic operations and data paths used by the more complex instructions such as
multiply and divide.

DEFPB Multiply and Divide ROM Tests - This program is a logically sequenced set of tests for the
multiply, modulo, and divide instructions and the memory management ROM. Also included is a test

of all the locations of the A-branch, No-mem branch, and ADX ROMs that have not previously been
tested. This last test is also used to verify the ‘““Disable Interrupt’ bit in the control store of the FPP.
The error reports in these programs assume there are no previous errors and that there is only one
failure in the FPP. This means that if the programs are not run in sequence, the error message may be
invalid.
7.2.3
Using the Maintenance Card with the FP11-B, C
FP11-B, C operation in the maintenance modes selected by maintenance card switches S1 and S2 is
similar to those operations described for the KB11-A, D. See Paragraph 6.5.
uPB STOP Mode - The FP11-B, C microbreak register is loaded with the required microprogram
ROM address, using the FP11-B, C maintenance instruction LDUB (Load Microbreak Register),
170003, as described in the FP11-B or FP11-C manual. Basically, this procedure requires that the
ROM address be deposited into the low-order byte of CPU general register R3. The LDUB instruction

transfers this address to the FP11-B, C microbreak register. When the CONT switch is pressed, program execution will proceed until the contents of the FP11-B, C control ROM address register matches
the contents of the microbreak register. When a match occurs, the FP11-B, C stops in time state TS2 of
the ROM state.

ROM CYCL Mode - FP11-B operation in the ROM CYCL maintenance mode is identical to KB11A, D operation in that mode (Paragraph 6.5.2.1). The FP11-B, C stops at time state TS2 of each
successive ROM cycle.
SING TP Mode - Same operation as described for KB11-A, D (Paragraph 6.5.2.3).

7-3

7.2.3.1

FPP Test Timing - When FP11-B maintenance is required, the FP11-B module is extended

with M900 module extenders and the FP11-B RC maintenance clock is used as a source of FPP timing.
When FP11-C maintenance is required, the FP11-C module is extended with M900 module extenders

and the KB11-D RC maintenance clock is used as a source of FPP timing. This is because the FP11-C
is synchronized to the KB11-D.

Clock selection is described in Paragraph 6.5.1.

Connect an oscilloscope to measure FRHJ CLOCK A H (pin A02B2) for the FP11-B or
T1GC TF H (pin D15M2) for the FP11-C at the CPU backplane.

For the FP11-B, adjust the potentiometer on the FRH module to provide a 50 ns FRHJ
CLOCK A H repetition rate. (Note that this does not affect CPU timing.) For the FP11-C,
adjust the potentiometer R162 on the T1G module (in the KB11-D) to provide a 30 ns
T1GC TF H repetition rate. (Note that this affects CPU timing.)

7.2.4

FP11-B, C Floating-Point Processor Procedures

This paragraph describes maintenance techniques available for the FP11-B, C Floating-Point Processor. The procedures involve the use of the maintenance card (W131) and driver module (W130 or
W133), mounted in slot El of the KB11-A, D CPU backplane. The use of the maintenance card is
described in Paragraphs 6.5 and 7.1.3.

7.2.4.1 Time Margining of the FP11-B - The timing of the FP11-B RC clock can be varied by using
the maintenance card with switch S3 in the RC position. Timing is adjusted by potentiometer R32 on
the M8114 FRH module. The nominal limits are from 50 ns to 290 ns. Refer to the note in Paragraph
6.5.1.

7.2.4.2 Time Margining of the FP11-C - The timing of the FP11-C RC clock can be varied using the
maintenance module with S4 in the RC position, by adjusting potentiometer R162 on the M8139 T1G
module. (Note that this also adjusts the KB11-D maintenance timing.) The limits are from 27 ns
minimum to 450 ns maximum. The time margins should be checked periodically to locate any potential problems due to increase in propagation delays of flip-flop switching times due to IC degradation.
7.2.4.3 Special Maintenance Instructions of the FP11-B - A set of five maintenance instructions is
available to assist maintenance personnel. These instructions are described in the following
paragraphs.

LDUB - Load Microbreak Register (170003) - This instruction causes the lower eight bits of general
register 3 in the CPU to be loaded into the microbreak register LDUB can be used for the functions
described in the following paragraphs, depending on the FMM bit (bit 4) in the program status word
(FPS).

NOTE
The FMM bit in the status word is used to enable
special maintenance logic. To set this bit, the CPU
must be in Kernel mode.

7-4

With the
FMM bit set, the microprogram will be aborted through the trap routine ROM address to
the ready state after the state specified by the address (next sequential ROM state) in the microbreak
register is detected. If the Interrupt Enable bit (bit 14) of the floating-point processor status word is set,
the CPU will trap to location 244. An exception code of 16 will be stored in the FEC (floating exception code) register. The contents of the FEC register can be transferred to the CPU by the STST (store
status) instruction. A second function, available as a result of the LDUB instruction, allows maintenance personnel to use the address match as a scope sync independent of the FMM bit. When the
ROM address matches the contents of the microbreak register, the UMATCH flip-flop is set at the
leading edge of TS1. The set output of this flip-flop (pin DK1 of slot 4 in the FXP module) is used as a
scope sync to allow visual observation of events that occur duing a particular ROM state. UMATCH
is cleared at the trailing edge of TS4, providing maintenance personnel with a sync signal that occurs at
the beginning of a specified ROM state and ends at the beginning of the next ROM state.
LDSC - Load Step Counter (170004) - This maintenance instruction loads the 1’s complement of the
least significant six bits of general register 4 into the step counter. LDSC sets the SC LOADED flipflop, provided FMM (bit 4) of the processor status word is set (CPU must be in Kernel mode to set
FMM), which inhibits the ROM from loading the step counter. When the step counter is incremented

to all 1s, the SC LOADED flip-flop is cleared. As a result of this instruction, maintenance personnel
can set up the step counter to perform a specified number of steps in a multiply or divide routine and
can stop where desired to examine the contents of the registers.
STAO - Store AR in ACO (170005) - This instruction transfers the contents of the AR to ACO, as

described below:
AR (57:35) - ACO (57:35) if FD = 0
AR (57:3) - ACO (57:3) if FD = 1
STQO - Store QR in ACO (170007) - This instruction transfers the contents of the QR to ACO, as
described below:

QR (57:35) —» ACO (57:35) if FD = 0 QR
QR (57:3) - ACO (57:3) if FD = 1

NOTE
The STAO and STQO instructions are used to store
the contents of the AR and QR (internal registers) in
an AC. Since the contents of the AC can be transferred to memory, maintenance personnel are able to
check the contents of the AR and QR registers.
MRS - Maintenance Right Shift (170006) - The Maintenance Right Shift instruction shifts the AR or
QR one bit position to the right. This instruction is used with the STAO instruction to allow AR59 and
ARS8 to be examined. Two MRS instructions are necessary to transfer AR59 to AR57 and AR58 to
ARS56. The MRS instruction
is also used with the STQO instruction to allow bits QR59 and QR S8 to be
examined. Two MRS instructions are necessary to shift QR59 to QR57 and QR58 to QR56. AR59 and
ARS8 as well as QR59 and QRS58 represent the sign bit and hidden bit, respectively. These bits are not
transferred between the CPU and the FP11-B but are used in data calculations by the floating-point
processor. Therefore, to examine the state of these two bits, the use of the MRS instruction is required.

7-5

7.2.4.4 Special Maintenance Instructions of the FP11-C - A set of four maintenance instructions is
available to assist maintenance personnel. These instructions are described in the following

paragraphs.

LDUB - Load Microbreak Register (170003) - This instruction causes the lower eight bits of general
register 3 in the CPU to be loaded into the microbreak register. LDUB can be used for the functions
described in the following paragraphs, depending on the FMM bit (bit 4) in the program status word
(FPS).

NOTE

The FMM bit in the status word is used to enable
special maintenance logic. To set this bit, the CPU
must be in Kernel mode.

With the FMM bit set, the microprogram will be aborted through the trap routine ROM address to

the ready state after the state specified by the address (next sequential ROM state) in the microbreak
register is detected. If the Interrupt Enable bit (bit 14) of the floating-point processor status word is set,
the CPU will trap to location 244. An exception code of 16 will be stored in the FEC (floating exception code) register. The contents of the FEC register can be transferred to the CPU by the STST (store
status) instruction. A second function, available as a result of the LDUB instruction, allows maintenance personnel to use the address match as a scope sync independent of the FMM bit. When the
ROM address matches the contents of the microbreak register, the UMATCH signal is present. This
output is pin DBI (slot 5 in the FXP module) and is used as a scope sync to allow visual observation of
events that occur during a particular ROM state. Note that match occurs at T2 of the previous state
and is negated at T2 of the selected state.

STAO - Store AR in ACO (170005) - This instruction transfers the contents of the AR to ACO, as
described below:

AR (57:35) - ACO (57:35) if FD = 0
AR (57:3) = ACO (57:3) if FD = 1

STQO - Store QR in ACO (170007) - This instruction transfers the contents of the QR to ACO, as
described below:

QR (57:35) - ACO (57:35) if FD = 0 QR
QR (57:3) - ACO (57:3) if FD = 1
NOTE
The STAO and STQO instructions are used to store
the contents of the AR and QR (internal registers) in
the AC. Since the contents of the AC can be transferred to memory, maintenance personnel are able to
check the contents of the AR and QR registers.

MSN - Maintenance Shift by N (170004) - This instruction transfers the contents of register R4 to the
shift control logic and causes the contents of the AR and QR to be right or left shifted by N. A negative
number in R4 causes a right shift by that number and a positive number in R4 causes a left shift by that
number.

7-6

7.2.4.5 Maintenance Instruction Programming Example — Program Example 7-1 demonstrates the use
of the FP11-B maintenance instructions. A similar program can be written for the FP11-C. The program is a multiplication example, whereby the contents of the AR and QR are typed out with each
incrementation of the step courter from 1 through 71. Note that the MRS instruction is used to get AR
and QR bits 59 and 58 into general register R5 for the typeout in each pass through the loop.
Program Example 7-1

001000

012706

001002

000600

001004

170127

001006

040220

001010

172667

001012

000204

001014

012703

001016

000230

START:

MOV

#600,%6

;SET UP STACK POINTER AT 600

LDFPS

#40220

;DISABLE INTERRUPTS; SET DOUBLE AND MAINT. MODE

LDD

MLYR,AC2

;LOAD MULTIPLIER IN AC2

MOV

#230,%3

;SET REG. 3 to 230

001020

170003

Lbus

001022

005004

CLR

;CLEAR COUNTER

001024

005204

INC

JINCREMENT COUNTER

001026

170004

001030

012705

001032

001166

NXTMUL:

;SET MBR TO 230

LDSC
LSTMUL:

;LOAD 1'SCOMPLEMENT OF R4 INTO SC

MOV

#QR+10,%5

;SET UP REG. 5 TO STORAGE TABLE

LDD

MCND,AC1

;LOAD MULTIPLICAND INTO AC1

AC2AC1

;DO PARTIAL MULTIPLY

001034

172567

001036

000150

001040

171102

MULD

001042

170007

STQO

001044

174045

STD

ACO,-(5)

;STORE QR IN TABLE

001046

042715

BIC

#177600,@5

;CLEAR SIGN AND EXPONENT

001050

177600

001052

170005

STAO

001054

174045

STD

ACO,-(5)

;SSTORE AR IN TABLE

001056

042715

BIC

#177600,@5

;CLEAR SIGN AND EXPONENT

;TRANSFERQR TO ACO

;STORE AR IN ACO

001060

177600

001062

170006

MRS

;SSHIFT AR AND QR RIGHT ONE PLACE

001064

170006

MRS

;SHIFT AR AND QR RIGHT ONE PLACE

001066

170007

STQO

001070

174067

STD

ACO,TEMP

;MOVE ACOTO TEMP

001072

000134

MOV

TEMP,%3

;MOVE MOST SIGNIFICANT 7 BITS OF QR TO R3

BIC

#177600,%3

;CLEAR SIGN AND EXPONENT

001074

016703

001076

000130

001100

042703

001102

177600

;TRANSFER QR TO ACO

001104

006303

ASL

;SHIFT MSB OF QR ONE PLACE LEFT

001106

006303

ASL

;SSHIFT MSB OF QR ONE PLACE LEFT

001110

050365

BIS

%3,10(5)

;SET QR59 AND QR58 IN TABLE

001112

000010

001114

170005

STAO

001116

174067

STD

ACO,TEMP

;MOVE ACOTO TEMP

001120

000106

001122

016703

MoV

TEMP,%3

;MOVE MOST SIGNIFICANT 7 BITS OF AR TO R3

001124

000102

001126

042703

BIC

#177600,%3

;CLEAR SIGN AND EXPONENT

;STORE AR IN ACO

7-7

Program Example 7-1 (Cont.)
001130

177600

001132

006303

ASL

001134

006303

ASL

SHIFT MSB OF AR ONE PLACE LEFT

001136

050315

BIS

%3,@5

;SET AR59 AND AR58 IN TABLE

JSR

%5,PRI NT

;PRINT AR AND QR

001140

004567

001142

000234

001144

000410

001146

000000

001150

000000

001152

000000

001154

000000

001156

000000

001160

000000

001162

000000

001164

000000

001166

020427

001170

000071

;SHIFT MSB OF AR ONE PLACE LEFT

422

;BRANC
OVER ARGUMENTS
H

AR:

FLT4

;AR STORED IN

QR:

FLT4

THESE FOUR LOCATIONS

JOR STORED IN THESE FOUR LOCATIONS

CmP

%4471

;HAVE 71 PASSES BEEN DONE

001172

100714

BMlI

NXTMUL

;/NO—-DO NEXT PASS

001174

001402

BEQ

LSTPAS

;'YES—DO LAST PASS

001176

000167

JMP

START

;THIS MULTIPLY COMPLETE—-DO NEXT ONE

001200

177576

001202

005204

001204

000167

001206

177620

LSTPAS:

INC

JINDICATE 72ND PASS

JMP

LSTMU L

;DO LAST PASSWITHOUT LOADING SC.

001210

040052

WORD

040052

001212

125252

WORD

125252

001214

125252

WORD

125252

001216

125252

.WORD

125252

001220

040000

WORD

040000

MCND:

MY LAR:

001222

000000

WORD

000000

001224

000000

WORD

000000

001226

000000

WORD

000000

001230

000000

FLT4

001232

000000

001234

000000

001236

000000
000001

TEMP:

.END

The fractional part of the multiplicand (1/2 or 0.1) is stored in the BR and fractional part of the
multiplier (consisting of alternating 1s and 0s) is stored in the QR.
The multiplier has an exponent of 200 and the multiplicand has a exponent of 204. The sign bitisa 0
and the hidden bit is a 1. The result of each step of the multiplication is stored in the AR. The typeout
of the listing after each step of the multiplication is shown in Table 7-2.

The contents of the AR and QR are typed out 57 times. On the 58th typeout, the step counter is not set
and this last typeout represents the final product.
7.2.4.6 Console Display Features — The console can be used to display the floating-point ROM
address and, under certain conditions, can display the contents of the EALU.

Table 7-2
Step

1
2
3
4

Typéout of QR and AR

Step

0000000000000000000
0000000000000000000
1000000060000000000
0400000000000000000

12525252562525252525
05252525252525252562
0252525252525252525
0125252525252526252

1252525252000000000

0000000000525252525

0525252525000000000

0000000000252525252

31
32
33
34

1252525252400000000
0525252525200000000
1252525252500000000
0525252525240000000

0000000000125252525
0000000000052525252
0000000000025252525
0000000000012525252

1200000000000000000

0062525252525252525

1252525252520000000

0000000000005252525

0500000000000000000

0025252525252525252

0525252525250000000

0000000000002525252

1240000000000000000

0012525252525252525

1252525252524000000

0000000000001252525

0520000000000000000

0005252525252525252

0525252525252000000

0000000000000525252

1250000000000000000

0002525252525252525

1252525252525000000

0000000000000252525

0524000000000000000

0001252525252525252

0525252525252400000

0000000000000125252

1252000000000000000

0000525252525252525

1252525252525200000

0000000000000052525

0525000000000000000

0000252525252525252

0525252525252500000

0000000000000025252

1252400000000000000

0000125252525252525

1252525252525240000

0000000000000012525

0525200000000000000

0000052525252625252

0525252525252520000

0000000000000005252

1252500000000000000

0000025252525252525

12525252526525250000

0000000000000002525

0525240000000000000

0000012525252525252

05252525256252524000

0000000000000001252

1252520000000000000

0000005252525252525

1252525252525252000

0000000000000000525

0525250000000000000

0000002525252525252

0525252525252525000

0000000000000000252

1252524000000000000

0000001252525252525

1252525252525252400

0000000000000000125

20
21

0525252000000000000
1252525000000000000

0000000525252525252
00000002525252525256

0000000125252525252

50
51

0525252525252525200
1252525252525252500

0000000000000000052
0000000000000000025

1252525200000000000

0525252500000000000

0000000052525252525

0000000025252525252

1252525252525252520

05252525252652525250

0000000000000000005

1252525240000000000

0000000012525252525

1252525252525252524

0000000000000000001

0525252520000000000

0000000005252525252

0525252525252525252

0000000000000000000

1252525250000000000

0000000002525252525

1252525252525252525

0000000000000000000

0525252524000000000

0000000001252525252

1252525252525252525

0000000000000000000

1252525252525252525

0000000000000000000

0525252400000000000

05256252525252525240

0000000000000000012

0000000000000000002

Display of ROM Address - The 16 DATA indicators on the console can be used to display the 8-bit
FPP ROM address and the 8-bit CPU ROM address. The FPP ROM address is diplayed on the high
order byte DATA indicators (bits 15-08) and the CPU ROM address is displayed on the low order

byte indicators (bits 07-00). The four-position data selector switch on the console must be set to the
rADDR FPP/CPU position to display the ROM address.
NOTE
If the maintenance card is set up to perform single
ROM cycles or micromat¢h, the FPP ROM address
displayed is the next ROM address, i.e., the address
of the next ROM state to be cycled, because the
ROM address changes at the end of time state 2 and
a pause or wait state occurs between time state 2 and
time state 3. If the maintenance card is set up to perform single clock cycles during time states 1 and 2,
the ROM address displayed is the current address;
for single clock cycles during time states 3 and 4, the
ROM address displayed is the next address.

7-9

Display of EALU Contents - In certain ROM states of the CPU, the contents of the EALU may be
displayed on the lower 16 ADDRESS indicators (bits 15-00) on the console. These CPU ROM states

are unique to F class instructions and are listed in Table 7-3.

Table 7-3 Class F CPU ROM States
Octal Address

ROM State
FOP.30

173

FOP.50

211

FOP.60

362

FOP.70

316

FOP.80

376

FOP.90

375

FOP.40

FSV.20

225

NOTE

The contents of the EALU at any of these ROM
states is dependent on the FP ROM state occurring
at that time. Both the FPP and the CPU should be
set up for single step operation, using both the CPU
and FPP maintenance cards to see meaningful data
in these ROM states.

The 8-position address selector switch on the console must be set to CONS.PHYS or PROG.PHYS.
7.3

KT11-C, CD MEMORY MANAGEMENT UNIT

7.3.1

Installation

Use the following procedure to install the KT11-C, CD Memory Management Unit.
1.

Turn switched power off at the console by shutting off both circuit breakers on the power
supplies.

2.
3.

Install SSR module (M8108 for the KT11-C or M8108-YA for the KT11-CD) in slot 13 of

the CPU backplane assembly.

Install SAP module M8107 in slot 14 of the CPU backplane assembly.
NOTE
SAP Module M8107 replaces the SJB Module
M8116, which is located in slot 14 when the KT11-C,
CD is not installed.

Turn circuit breakers on.

7-10

Measure the voltage at pin A13A2, which receives +5 Vdc from the H744 +5 V regulator
located in slot C of the H7420 power supply. If voltage is not correct, adjust voltage as
required (Paragraph 6.2.2).

7.3.2

Run the KT11-C, CD Memory Management Unit diagnostic programs listed below to veri-

fy that the KT11-C, CD is operating properly.
Diagnostics

Table 7-4 lists the diagnostic programs for the KT11-C, CD Memory Management Unit option. If a
fault is suspected in the KT11-C, CD prior to running the diagnostics, the internal registers (status,
page address, and page description) should be checked at the console for proper operation. The
addresses of the status registers are:
SRO - 777572
SR1 - 777574
SR2 - 777576
SR3 - 772516

Table 7-4

KT11-C, CD Memory Management Unit Diagnostic Programs

Number
MAINDEC-11-DCKTA-A

Tests
Basic Logic Test, Part 1

MAINDEC-11-DCKTB-A

Basic Logic Test, Part 2

MAINDEC-11-DCKTC-A

Access Keys Test

MAINDEC-11-DCKTD-A

Move to Previous I/D Space Test

MAINDEC-11-DCKTE-A

Move from Previous I/D Space Test

MAINDEC-11-DCKTF-A

Abort Tests

MAINDEC-11-DCKTG-A

Memory Management Exerciser

The addresses of the page address and page description registers are given in Table 2-1 of the KT11-C,
CD manual. Bits 12 through 15 of the Page Address Registers are not used, and bits 4, 5 and 15 of the
Page Description Registers are not used. Press the DEP and EXAM switches for each of the registers.
DCKTA and DCKTB Basic Logic Tests One and Two - Tests the basic logic, including write into
PAR and PDR, and all status registers.
DCKTC Access Keys Tests — Performs a test of all access control field (ACF) keys to verify that each
key provides the required results for valid and invalid access attempts.
DCKTD MTPD/I with Memory Management - Tests the MTPD and MTPI instructions with the
KT11-C, CD enabled. The instructions are executed in all combinations of current and previous mode
conditions.
DCKTE MFPD/I with Memory Management - Tests the MFPD and MFPI instructions with the
KT11-C, CD enabled. The instructions are executed in all combinations of current and previous mode
conditions.

7-11

DCKTF Memory Management Abort Tests — Tests the memory management abort errors. This diagnostic causes an abort of each BUST of the KB11-A, D. Following the abort, the diagnostic checks for
correct information in the status registers and on the stack. The sequence of tests begins with Page 1 of
the microflows and proceeds from left to right.
DCKTG KT11-C, CD Exerciser — Exercises basic KT11-C, CD Memory Management Unit functions.

In addition, this diagnostic uses all available memory and will run many I/O devices simultaneously
with KT11-C, CD tests.
7.4

MS11 SEMICONDUCTOR MEMORY

7.4.1
Installation
Table 1-2 and 1-3 indicates the wide range of MOS and bipolar memory configurations that can be
implemented in a PDP-11/45, 11/50, 11/55 system. Table 7-5 provides a summary of the semiconductor memory available. Before installing a semiconductor memory system, the user should be
completely familiar with the MS11-B MOS and MS11-A, C bipolar memory options, described in the
MS11-A, B, C Memory Systems Maintenance Manual. The MS11 manual presents comprehensive
coverage of all optional jumper connections.

Table 7-5

Matrix

MS11 Memory Configurations

MS11-AP*

MS11-BR, BT

MS11-CM, CP

Matrix Size

4K Bipolar

4K MOS

1K Bipolar

Matrix Module

M8121-YA

G401

M8111

MS11-CC

Controller

MS11-C

MS11-B

Controller Capacity

4K Bipolar

4K MOS

1K Bipolar

Controller Module

M8120

M8110

M8120¢t

*QOnly the parity version (MS11-AP, M8121-YA) is available.
tEarly versions use the M8110.

7.4.1.1

Semiconductor Memory Jumper Connections - When MOS or bipolar memory is installed,
certain jumpers are to be cut or installed, depending on the range of memory addresses desired. The
following paragraphs describe the jumper connections for the MOS and bipolar memory matrix
boards, followed by a description of the jumpers for the memory controller.
NOTE
To fully utilize MOS or bipolar memory speed, the
MOS memory address should be cut for the /ower

portion of memory (0-XK). However, if power fail
recovery is a critical requirement, it may be more

desirable to locate core memory in the 0-4K portion
of the total memory range.
In either case, the DEC Field Service Representative should contact the customer so that optimum use
can be made of the memory system. We suggest that MS11-CM or -CP bipolar memory be addressed
as the last segment of memory because it is expandable in 1K increments; however, when configuring a
total memory system, the customer should always be advised of the variables to determine the optimum configuration for each installation.

7-12

MOS - Table 7-6 contains the required jumper configuration for the assignment of the 4K block of
MOS memory addresses. If, for example, a G401 MOS memory matrix has jumpers C and B installed,
then that matrix contains memory locations XX4096 through XX8191. The Xs preceding the number
denote that the memory addresses can be selected anywhere in the range from 0 to 128K. Any address
from 4096 to 8191 is recognized and responded to by the matrix.

Table 7-6

G401 MOS Memory Matrix Selected Address Configuration (4 of 16K)

MAD

Required Jumpers

MOS Matrix Memory

(MAD 14)

(MAD 13)

Address Assignment

0 — 4095

4096 — 8191

8192 — 12,287

12,288 — 16,383

MAD 02 and MAD 01 (not jumper selected) further define a particular 1K block of addresses within
the specified 4K block (Table 7-7).

Table 7-7

G401 MOS Memory Matrix Control Level Generation
and Selected Memory Address Block (1 of 4K)

MAD

Memory Address Block Selected

1024 — 2047

2048 — 3071

3072 — 4095

0—1023

Bipolar - The M8111 and M8121-Y
A bipolar memory matrix decodes Unibus or Fastbus address bits
(14:11). The selective jumpering of these bits on an M8111 1K memory module, or the selective switching of these bits on an M8121-Y
A 4K memory module, can designate that memory module as having a
unique set of consecutive addresses within the total set of 16K addresses. Table 7-8 lists the jumper
connections and the corresponding address set selected by each jumper configuration on the M8111
module. Table 7-8 also lists the switch positions and the corresponding address set selected by each
switch configuration on the M8121-YA module. The M8111 jumpers are wire-wrapped in place. As in
the MOS matrix, addresses can be selected on both types of bipolar matricies from 0 to 128K when
used with an M8120 or M8110 control module.
M8110 and M8120 SMC Module - The jumper connections on the M8110 and M8120 SMC module
are designated by E numbers. Jumpers are located on E67, E75, E78 and E87 (described in the following paragraphs). All jumpers are prewired on the controller module; for a specific address con-

figuration, jumper wires must be cut. If the configuration is changed it is necessary to reinstall some
jumpers previously cut. Refer to the MS11-4, B, C Memory Systems Maintenance Manual and related
engineering drawing set for detailed information pertaining to the various jumper connections.

7-13

Table 7-8 M8111 and M8121-YA Bipolar Matrix Selected Address Configuration
,

Unibus/Fastbus

MS8111

“dlulnln

Required Jumpers

MAD
14

M8121-YA

SI Switches Closed

Memory Address

(Denoted by X)

Assignment

MAD 14 | MAD 13

1|0

[1]o0

A | B

{13 | 11|

10 | (MAD 14)| MAD 13)| (MAD 11)| MAD 10)|

X | 0to1023

1024 to 2047

2048 to 3071

5120 to 6143

0
0

1
1

0
1

D
D

E
E

J
J

B
A

X
X

|1 X
|X

6144 to 7167
7168 to 8191

| X

3072 to 4095
4096 to 5119

110

X | 9216to 10,239

10,240 to 11,263

| 11,264 to 12,287

12,288 to 13,311

13,312 to 14,335

111

14,336 to 15,359

15,360 to 16,383

8192 to 9215

E67 - Figure 7-1 shows the jumper connections at E67 that interface the Fastbus to the controller for
MOS and bipolar memory. Note that bits 13 and 14 are designated for MOS and 4K bipolar, and bits
11 and 12 for 1K bipolar. Note also that SMCF DECODE 14 and SMCF DECODE 13 are connected
only for MOS memory and 4K bipolar.

4K BIPOLAR
4K MOS

1K BIPOLAR

1
.

DECODE 14 H .|
TM
SAPJ PAI3 H

SAPJ PA{2 H
SAPJ PA14 H

SMCF

SMCF
DECODE

2l ———

MUX 14712 H

SAPJ PA12 H

sMmcF FB

SAPJ PA14

SMCF FB

sMCF FB

4| —— ,3|

13 H

8| ——° l
EGT

SMCF FB

MUX DEC 14 H

SMCF

MUX 14 /12 H

_'il

SMCF FB

DECODE 14 H

SMCF FB

SAPJ PA{3 H

SMCF
DECODE 13 H

'_51

SMCF

MUX DEC 13 H

MUX DEC 14 H

SMCF

MUX DEC 13 H

E67
t1-1327

Figure 7-1

Fastbus Multiplexing (14:11) Required E67 Jumper Configuration

7-14

E78 - Figure 7-2 shows the jumper connections at E78 that interface the Unibus to the controller for
MOS and bipolar memory. Note that bits 13 and 14 are associated with MOS and 4K bipolar, and bits
11 and 12 are associated with 1K bipolar. Also note that SMCF DECODE 14 and SMCF DECODE
13 are not connected for 1K bipolar.
4K BIPOLAR

SMCH UBAD
12 H
SMCH UBAD 14 H

SMCF

DECODE 14 H
SMCH UBAD

SMCH UBAD 13

SMCF

DECODE 13 H

1K BIPOLAR

4K MOS
12/_\15’—MUX
| 16
SMCF {4712
UB
4

—

4L '3
‘

smcF uB

SMCF UB

DECODE 14 H

SMCF

DEC 14 H

12
”‘[_MUX13/11

SMCH UBAD 12
H
SMCH UBAD 14 H

MUX

SMCF UB

E78

| 3 —4

SMCH

UBADHH———T

SMCH

UBAD 13
H

?[_ MUX DEC
13 H

—
8L %

L E—MUX
S
SMCF14712
UB H
)

SMCF

'__3_|——

DEC

14 H

e E——MUX
SMCF 13/11
UB

|7 e ALY

DECODE 13 H

SMCF UB

MUX

E78

SMCF UB

MUX DEC
13 H

11-1329

Figure 7-2

Unibus Multiplexing (14:11) Required E78 Jumper Configuration

E75 - The jumpers at E75 permit Fastbus and Unibus address selection. Four of these jumpers correspond to Fastbus addresses and four correspond to Unibus addresses. Each jumper allows the M8110
or M8120 control to respond to a 4K group of addresses; thus, each M8110 or M8120 can control up
to 16K words. The corresponding jumper is removed if memory is present for the associated address
group.

Table 7-9 illustrates the required jumper connections for both MOS and bipolar memory. Assume that
MOS memory is connected to a controller and jumper J is cut. In this case, memory addresses from 0
to 4K are assigned to memory, and the controller will recognize and respond to this group of addresses
from the Fastbus. If jumper N is cut, the controller will recognize and respond to these addresses from
the Unibus. Table 7-10 shows the jumper configuration as additional memory matrices are added to a
memory controller. For example, if MOS memory is connected to the controller, and it is desired to
have the controller respond to addresses from 0 to 12K from the Unibus jumpers N, P, and R must be
cut. If, at some future date, it is desired to reconfigure the memory from 4K to 12K, for example,
jumper N must be reinstalled.

Table 7-9
4K MOS or 4K Bipolar

Address
Bit

14 | 13
0
0
1
1

Memo.ry Address

MOS/Bipolar Module Addressing

Fastbus

Unibus

Remove Jumper

Assignment

0—4095
4096—8191
8192—-12,287

J
K
L

12,288—16,383

Memo.ry Address
Assignment

0
1
0

1K Bipolar

N
P
R
S

7-15

Address
Bit

12 | 11

0-—-1023
1024-2047
2048—3071

0
0
1

0
1
0

3072-4095

Table 7-10 MOS/Bipolar Memory Addressing (More Than One Matrix)
Remove Jumpers
No. of Memory

Memory Capacity

Modules in

4K MOS or

Memory

4K Bipolar

1K Bipolar

Fastbus

Unibus

Address

Select

JKL

NPR

JKIM

NPRS

12K

16K

*Connected to one M8110/M8120 Control.

E87 — Jumpers C, D, E, F, and H are used to assign a block of MOS or bipolar addresses to a
controller from the total available address area from 0 to 12K (Table 7-11). For example, to have the
controller respond to bipolar memory addresses from 120K to 124K, jumpers C, D, E, and F must be
cut. Jumpers C, D, and E allow assignment of 16K words within the total address space; jumpers F
and H allow assignment of 4K words within the assigned 16K.
For MOS memory, jumper A is cut. If this jumper is not cut, the controller is configured for bipolar
memory and refresh is inhibited. If the parity option is installed, jumper B is cut to enable the Parity

Control Register. If jumper T, is cut, Parity Register address bit 1 will be a 1; if jumper T is not cut, this
bit will be a 0. See Drawing D-CS-M8110-0-1, sheet SMCF or the equivalent M8120 drawing.
7.4.1.2 Installation of Bipolar Memory - The CPU backplane of the PDP-11/45, 11/50, 11/55, provides slots for eight memory matricies and two memory controllers. Refer to Figure 7-3. Note the CPU
backplane section and dedicated slots. The controller of slot 16 addresses the matricies of slots 17

through 20. The controller of slot 21 addresses the matricies of slots 23 through 25. Each M8120
controller is jumpered to provide either 4K or 1K matrix operation; thus only that type of matrix can
be placed in the corresponding matrix slots. For example, if the M8120 controller is jumpered for 1K
operation, one, two, three or four M8111 modules of bipolar memory may be placed in its corresponding slots to provide 1K, 2K, 3K, or 4K of memory.

MEMORY CONTROL

MATRIX

MATR X

MATR
X

MATRIX

MEMORY CONTROL

MAT RIX

MATRIX

MAT RIX

— CONTROLS

:——CONTROLS

B
]

NOTE:

Slots 17-20 can contain either 1K BIPOLAR, 4K BIPOLAR, or 4K MOS modules according to the jumpar configuration on the corresponding memory control.

Likewise for slots 22-25;

however, MOS can be used in slots 22-25

ONLY if slots 17-20 contain MOS. (For MOS/BIPOLAR combination, MOS
MUST be in slots 17-20.

11-4292

Figure 7-3

CPU Backplane Memory Slots
7-16

Table 7-11

Fastbus/Unibus Memory Address (Assign and Decode)

Fastbus/Unibus

Memory Address

M8120 or M8110 Jumpers (E87)

Address Decoder Bits

Assignment

(NOTE 1, NOTE 2)

(16 | 15

4K MOS or

|14

113

1K Bipolar | 4K Bipolar

| 04K

0-16K

0 0 0

0 8—12K

20-24K

|24-28K

28—-32K

|32-36K

32—48K

36—-40K

| 40—44K

|48-52K

48—-64K

52-56K

0
1
1

1
0
0

0 56—-60K

60—-64K
|64-68K
68—-72K

1
1
1

0
0
0

0
1
1

1
0
1

0 | 72-76K
1

76—-80K
80—84K
84—-88K

0 | 838-92K

0110

|44-48K

X
X

64—-80K

X
X

96—112K

92—-96K

| 96-100K

100—104K

0 104-—-108K
1

108—112K

112—-116K|

112—128K

116—120K

120—-124K

NOTES:

124—128K

80—96K .

16—32K

16—20K

12—-16K

4—-8K

X
_

1. “X” denotes jumper to be cut.
2. Jumpers F and 11 are left intact for all 4K memory assignments, i.e., when assigning address to

G401 and M8121 modules.

Note that a combination of 1K and 4K modules may be utilized on the same backplane provided the

respective controller is jumpered for such operation. Thus, a maximum of two types of memory may
be used in one backplane (two controllers). The following steps outline the procedures for installation
of the bipolar memory.
1.

Turn off H7420 (or H742) power supply circuit breakers.

Install H744 regulators and M8120 SMC control modules, and cut power harness jumpers
per Table 7-12, depending on amount of Bipolar memory. "
7-17

Table 7-12

Bipolar Memory Configurations

M8121

< 8K

< 16K

< 24K

> 24K

MS8111

<2K

<4K

< 6K

> 6K

Slot J

Slots J, H

Slots J, H, K

Slots J, H, K, L

no jumpers cut

cut P5-7, 8

cut P5-7,8

cut P5-7, 8

cut P5-3, 4

cut P5-3,4
cut P6-7, 8

M8120 in CPU Slot 16
Note:

M8120 in CPU Slot 21

Early Bipolar versions used an M8110 control.

Install the M8121(4K) or M8111(1K) memory matrix modules (-Y
A versions signify memo-

> ry with parity).
4.

Note that:

Each M8120 can control up to four M8111s or up to four M8121s.

Each H744 +5 V regulator can supply enough current for only one M8120, plus two
MS8111s or M8121s. The H744 is rated at 25A.

Installation of bipolar memory must start at slot 16.

Refer to Figure 5-3 for +5 V regulator configurations.

Turn on the power supply circuit breakers.

Measure +5 V at each of the points indicated in Table 7-13.

Adjust voltages if required as described in Paragraph 6.2.2.

Refer to the MSI11-A, B, C Memory Systems Maintenance Manual and the MS11 engineering print set for appropriate timing adjustments.
Table 7-13

Bipolar Memory Voltage Checks

Regulator

Point of

Slot

Voltage

Measurement

SlotH

[|+5Vdc

Between A19A2
and ground

Slot J

+5 Vdc

Between A16A2
and ground

Slot K

+5 Vdc

Between A21A2

and ground
Slot L

]+5Vdc

Between A24A2
and ground

7.4.1.3 Installation of MOS Memory (MS11-B) - From 4K to 32K of MOS memory in increments of
4K, can be installed in the PDP-11/45, 11/50 system. The MS11-BC memory option controls 16K of
MOS memory (Table 1-2). If more than 16K of MOS memory capacity is desired, an additional MS11BD memory control is required. The procedure for installing MOS memory is described below.
Turn off circuit breakers on both the H7420 power supplies. Install the H744 +5 V regulator
(part of the MS11-BC) in slot J of the lower H7420 power supply.

Install the H746 MOS regulator in slot H of the lower H7420 power supply.

Install the M8110 SMC module in slot 16 of the CPU backplane assembly and install the
G401 MOS memory matrix modules in the CPU backplane assembly in slots 17-20 (maximum of four G401 modules per M8110).

NOTE

If MS11-BP (memory parity) option is selected, the
MOS memory matrix modules are designated
G401YA.

If more than 16K of memory is required, install the second M8110 SMC module that comprises the MS11-BD memory control inslot 21 of the CPU backplane assembly. Install the
additional G401 MOS memory matrix modules starting at slot 22 of the CPU backplane
assembly. Install additional H746 regulator in slot L of the lower H7420. Modification of
the backplane is required if the power system revision letter is E or lower. See Table 5-1.
Turn on circuit breakers and measure the voltage from A16A2 of the CPU backplane to
ground for +5 Vdc.

Measure the following voltages at the points indicated below:
-

Voltage

+23.2 Vdc
+19.7 Vdc
—5Vdc

CPU Backplane
Point of Measurement

Pin A17V2 and ground (Rev F and up A22V2 and ground)
Pin A17U2 and ground (Rev F and up A22U2 and ground)

Pin F17C1 and ground

Readjust as required in accordance with Paragraph 6.2.2.
NOTE

Do not cut any jumpers on the power harness when
installing MOS memory.

Refer to the MSI11-A, B, C Memory Systems Maintenance Manual and the MS11 engineering

print set for appropriate timing adjustments.

7.4.1.4 Installation of both MOS and Bipolar Memory - The installation for combined MOS and
bipolar memory is described below.

Turn off H7420 (or H742) power supply circuit breakers.
2.

Cut the jumper between P5-3 and -4 on the power harness.

7-19

[Install the H746 MOS regulator in slot H of the lower H7420 power supply.

Install one H744 +5 V regulator in slot J of the lower H7420 power supply.

[Install second H744 +5 V regulator in slot K of the lower H7420 power supply.

If more than 2K of M8111 or more than 8K of M8121 bipolar memory is installed, install
third H744 +5 V regulator in slot L of the lower H7420 power supply. Cut the jumper

between P6-7 and -8 on the power distribution cable harness.
7.

Install the M8110 SMC module supplied as part of the MS11-BC MOS memory control

option in slot 16 of the CPU backplane assembly.
8.

Install the G401 MOS memory matrices (G401Y
A if memory parity is selected), starting at
slot 17 of the CPU backplane assembly. Up to four modules can be installed.

Install the M8120 SMC module supplied as part of the MS11-CC (or -AP) bipolar memory
control in slot 21 of the CPU backplane assembly.

10.

Install the M8111 or M8121 bipolar memory matrix modules in the CPU backplane assembly (-YA with memory parity) starting at slot 22 of the CPU backplane assembly.

11.

Turn on power supply circuit breakers.

12.

Measure the following voltages between the points indicated.

13.

Voltage

CPU Backplane

+ 5.0Vdc
+23.2 Vdc
+19.7 Vdc

Between A16A2 and ground
Between A 17V2 and ground
Between A17U2 and ground

— 5.0Vdc
+ 5.0Vdc
+ 5.0 Vdc

Between F17C1 and ground
Between A21A2 and ground
Between A24A2 and ground

Adjust voltages if required as described in Paragraph 6.2.2.
NOTE
All M8110 and M8120 module adjustments have
been made at the factory. If further adjustment is
required, use the latest SMC module circuit schematic for the proper adjustment procedure.

7.4.2

Semiconductor Memory Calibration
Semiconductor memories must be calibrated before use. The procedures for this are set forth in the
MSI11 print set and Chapter 4 of the MSI1-A, B, C Memory Systems Maintenance Manual.

7.4.3 Diagnostics
The diagnostic programs used with the MS11 Semiconductor Memory System are briefly described in
the following paragraphs. Specific calibration and maintenance procedures are provided in Paragraph
7.3.2 of this manual, as well as the MS11-A, B, C Memory Systems Maintenance Manual. Table 7-14
lists the diagnostic programs used with the MS11.

7-20

Table 7-14

MS11 Semiconductor Memory System
Diagnostic Programs

Number

Tests

‘

MAINDEC-11-DZMSA- (1) | Logic
MAINDEC-11-DZQMA- (2) | Mem Ex > 28K
MAINDEC-11-DZQMB-

0-124K Memory Exerciser

MAINDEC-11-DCMFA- (3) { Parity Check
(1) MOS Memories only
(2) Requires NPR device input
(3) Parity memories only

DZMSA Memory Parity Test — The Memory Parity Test reads the semiconductor control parity
register addressed and prints out on the 33 ASR whether or not the register exists. If the addressed
register does exist, the function of each register bit is tested. This diagnostic will also load the
addressed register and initiate parity write/read tests in the memory section designated, and permit
error interrupts as specified by the state of the pertinent parity register bit.
DZQMA - This test checks memory up to 124K, using NPR devices.

DZQMB - This test checks 0-124K. of memory for unique addressing and worst-case noise patterns.
DCMFA - This program locates the Parity Memory Registers for both the core and MOS parity
memories and performs a check of the bits in each. It then creates a map showing the memory controlled by each Parity Register. The Parity Registers and the memory are then tested using the information in the map.
7.5

KWI1I1-L LINE CLOCK

Shut power off.

Cut the jumper between COIR2 and C01V2 on the CPU backpanel.

Install the KW11-L module in slot 1, row C of CPU.

The following programs may be used to check the operation of the KW11-L:
a.

INTERRUPT MODE
The following program is an example of one way the KW11-L can be used in the
interrupt mode. This program is intended to enter the routine TIME after every N
interrupts. The mnemonic LKS represents the permanent memory address of the
KWI11-L, 777546; LKV represents the vector address, 100. When the main program is
interrupted, it is directed to LKV, and then to LKV +2, which is 102. The word in
location 100 is the address of the first instruction in the interrupt service routine; this
address is transferred into the program counter of the processor. The word in location
102 is the new status word, which is transferred into the status register of the processor.
The new status word contains the number 300, which indicates a priority level of 6,
with all five condition codes, T, Z, N, V, and C equal to 0.

7-21

LKS = 777546
LKV =100

MAIN:

MOV #N, CNTR
MOV #100, LKS

LKV:

;ENB INTR

LKSERV
300

LKSERYV:

MOV #100, LKS

;Clear bit 7. This instruction is optional

DEC CNTR
BEQ TIME

;If counter is zero, go to time.

;If counter is not
;Zero, continue.

RTI
TIME:

MOV #N, CNTR

;Reset counter

RTI
Program Example 7-2

NONINTERRUPT MODE
The following program is an example of one way the KW11-L can be used in the
noninterrupt mode. In this example, it is assumed that an INIT or a previous DATO
with D06 = 0 has placed the KW11-L in the noninterrupt mode. This program alternates between two program routines - each lasting for approximately the time period
between line clock changes, which is either 16.67 ms or 20 ms. Each routine contains a
program loop that lasts for a considerably shorter time than the period between line
clock changes. The mnemonic LKS represents the permanent memory address of the
KWI11-L, 777546.

LKS = 777546

START:

SYNC:

CLRB

ILKS

;Reset bit 7

TSTB

1KS

BPL

SYNC

;Then reset it

CLRB

LKS

;Clear bit

;Do first routine

TSTB

LKS

;EBach time through loop test bit 7

BPL

;When bit is set

CLRB

LKS

;Clear bit

;Do second routine

TSTB

LKS

;Test bit 7

BPL

OFF

;1f not set, do loop again

CLRB

IKS

;If set, clear bit

JMP

;Do first program again

ON:

OFF:

;Wait until bit 7 is set,

Program Example 7-3

7-22

CHAPTER 8

SYSTEM UNIT OPTIONS

8.1

SYSTEM UNITS

Many of the options available for the PDP-11/45, 11/50, 11/55 systems consist either in whole or in
part of system units. Appendix C lists these as SU in the Mounting Code column. A system unit

consists of:

The backplane, which can be be either single (four card slots) or double (nine card slots),

PC module(s) that plug into the backplane.

A power harness (option harness) that brings power from the cabinet power distribution
system to the option backplane. Harness numbers are listed in Appendix C.

and either wire-wrapped or printed circuit etch connected.

If the system unit is a peripheral device controller, the cable to the peripheral device plugs into a
connector on one of the modules. System units may be installed, within the limits set by the applicable
configuration rules, in either the CPU or in an expansion cabinet. Three single system units can be
installed in the PDP-11/45, 11/50, 11/55 CPU cabinet and nine in an H960-D expansion cabinet; a
double SU takes up the space of two single units.

8.2

EXPANSION CABINETS

The H960-D cabinet contains one BA11-FB mounting box containing up to nine system units and an
associated H7420 (or H742) power supply. The H960-C Version of the expansion cabinet is merely the
empty cabinet frame and panels. The ac power distribution for the cabinet is shown in engineering
drawing D-1C-H960-0.

The ac power control system is the same as that for the CPU cabinet, which is explained in Chapter 4
of this manual, with the exception that only one (switched) H7420 (or H742) is provided per BA11-FB
mounting box.

The voltage regulator complement varies with the system unit configuration. DC power distribution is
explained in Paragraph 8.3.

8.3

DC POWER DISTRIBUTION

Refer to the block diagram of Figure 8-1. Chapter 3 of this manual refers to the power harness in the
lower half of the figure connecting the power supplies with the CPU backplane, console, and distribution board. A second power harness is needed to connect a third power supply and the distribution
boards of the expansion cabinet. The power distribution boards provide a link between the power
harnesses and option harnesses(SUpower harnesses). Each power distribution board can handle three
system units; therefore, the CPU cabinet contains one distribution board and the expansion cabinet
contains three distribution boards.

8-1

POWER

CONTROL

POWER

CONTROL

SUPPLY

DISTRIBUTION

BOARD

s|s|s

OPTION

Uuiulu

HARNESSES

DISTRIBUTION

BOARD

OPTION HARNESSES

DISTRIBUTION
POWER HARNESS

BOARD

DISTRIBUTION

POWER
SUPPLIES

BOARD

(2)

sS|{s|s
ujul|u

s|s|s

vuju|u

OPTION HARNESSES

> S|S|S

OPTION HARNESSES

CPU

BACKPLANE

CPU

CONSOLE

11-4294

Figure 8-1

DC Power Distribution; Simplified Block Diagram

Paragraph 3.3 of this manual defines four versions of the dc power distribution system in terms of
control, harness, and supply. When CPU cabinet serial number 2000 was produced, its power distribu-

tion board was also changed with the power harness. When expansion cabinet serial number 7000 was

produced, its power distribution boards and power harness were also changed. These changes are
tabulated in Table 8-1.

Distribution board location is described in the following paragraphs.
Table 8-1

Part
Harness

Power Distribution Components

Version

Cabinet
CPU

H960-D

Older

7008784

7008754

Newer

7009540

7009566

Distribution

Older

5409903

5409944

Board

Newer

5410590

8-2

8.3.1
CPU Cabinet
The connectors of the distribution board for the SU power harnesses (option harnesses) are at the rear
of the CPU mounting box in the older versions (Figures 8-3 and 1-1) and at the top of the CPU box in
the newer versions (Figures 8-2 and 1-1). See engineering drawings D-UA-11/45-0-1 for more detail on
both versions. (Equivalent 11/50 or 11/55 drawings present detail on newer versions only.)

POWER

DISTRIBUTION
PANEL

5410590
SYS UNIT PWR
DISTRIBUTION BOARD
MOUNTED ON TOP
OF CPU BOX.

POWER HARNESS
7009540

TYPICAL
———— OPTION
HARNESS

TO BOTH
H7420's

(or H742's)

)

\
\

7L
.

g 5T

0Y<E

0yst

2S
>

TYPICAL OPTION

BACKPLANES

11-2301

Figure 8-2
Installation of System Units, Later Systems,
CPU Cabinet Serial Numbers 2000 and Higher

8-3

REKD GND
+

BBLK Gs\’

GLUE

MATE-N-LOCK

CONNECTORS

{ 'RAY 15
NESNJ5

< RK

5409903

SYSTEMUNIT

glgzgloeunon

MOUNTED ON REAR

OF CPU BOX

1
MATE-N-.OCK
CONNECTORS

7008784

POWER HARNESS

FASTAB CABLE

le— (SEE OPTION
LISTING)

\P\

(uj4

®~|o g 0>

[a)
|

‘5’ ||
a|alal

8
o
3

z
&

! S ol

N, T

Cry X
By ‘A

|Z
|&

708855
CABLE

NSOR

NOTE:

In some systemunits, such
as MM11-S,G772A plugs
into slot CO4; on other
options, A0 3 is used.

Power distributionto these
siots is shown below:

+5V
-15v

GND

5TEM1

SEE NOTE

gYNIT

+5V

-15V —

LINE
CLOCK

+15V

GND —
L

pinside of system
unit power slot)
| ...,

Figure 8-3 Installation of System Units, Early Systems,
CPU Cabinet Serial Numbers Less than 2000

8-4

8.3.2

Expansion Cabinets

In the older versions the power distribution boards are mounted vertically and are shown in Figure 85: the newer ones are mounted horizontally and shown in Figure 8-4. Drawings D-UA-H960-D-0 show
the complete assembly of both old and new expansion cabinets. The newer harness is installed in
cabinets bearing serial numbers 7000 and higher.

8.4

MF11 CORE MEMORY

A system unit option for the PDP-11/45, 11/50, and 11/55 is the MF11 Core Memory System. Refer
to the MF11-U/UP Core Memory System Maintenance Manual (EK-MF11U-MM-003) for installa-

tion and maintenance procedures. The diagnostic programs used with the MF11 Memory Systems are
described briefly below. Table 8-2 lists the diagnostic programs used with the MF11.
Table 8-2

MF11 Core Memory System Diagnostic Programs

Number

Tests

* MAINDEC-11-DZMMJ

Mem 0—-24K

MAINDEC-11-DZQMA (1)

Mem I/O Exerciser

MAINDEC-11-DZQMB

0—124K Memory Exerciser

MAINDEC-11-DCMFA (2)

Mem Parity Control Logic Check

(1) Requires NPR device input
(2) Parity memories only

DZMMIJ - This program is a combination of eight test patterns that can be used to test 0-24K of
memory. This program may find problems not found by DZQMB.
DZQMA - This test checks memory up to 124K, using NPR devices.

DZQMB - This test checks 0-124K of memory for unique addressing and worst-case noise patterns.
DCMFA - This program locates the Parity Memory Registers for the memory and performs a check
of the bits in each. It then creates a map showing the Memory controlled by each parity register. The
‘Parity Registers and the memory are then tested using the information in the map.
8.5

INSTALLATION OF SYSTEM UNIT
The installation of a system unit requires the items listed in Table 8-3.

Table 8-3

SU Installation Requirements

Qty

Item

Backplane

Power Hamess | See Appendix C

M920 Unibus

Remarks

Except when the

Jumper Module | SU is the first

installed in a
BA11-FB expan-

sion box.

SuU

———P1B

SYS UNIT PWR

POWER DISTR | BUTION
PANEL

DISTRIBUTORS
5410590

BOARDS

oeR

0000 000D

Oaui]

P4 P5P6

Pi8

TYPICAL OPTION

HARNESS
7009573

g0‘

r”s0 A
Yy

NOTE:

A jumper harness will have fo be
removed when installing DB11
Unibus repeaters.

WIRING SIDE
3

0 ol6

3loo000

Eoof

[ooooo

ilooia

I fTo0
O 0O

POWER
HARNESS
7009566

OPTION POWER CONNECTORS
PIN ASSIGNMENTS

—BLK

1.+5V—RED

9.GND — BLK

2. LINE CLOCK —BRN

2.+15V—GRY

10.

—VI0
—~YEL

3.+20V-0ORN

11.GND —BLK

4,+5V —RED

5.GND — BLK

13-15v —BLU

14,.-5v —BRN

7. GND —BLK

15.

1. GND

3.0C LO
4. AGC LO

8.GND —BLK

TO SWITCHED
OUTLET
POWER CONTROL
TYPICALOPTION
BACKPLANES

*Early versions use an H742
power

suppy.
11-4298

Figure 8-4 Expansion Cabinet Power Distribution
Cabinet Serial Numbers /000 and Higher

8-6

SYS UNIT PWR
DISTRIBUTION BOARD

5410590

POWER HARNESS
7008754
FAN AC POWER

DISTRIBUTION
BOARD
7009511

N
P7

"’

TO SWITCHED

OUTLET

POWER CONTROL

TYPICAL OPTION
BACKPLANES

11-2304

Figure 8-5

Expansion Cabinet Power Distribution

Cabinet Serial Numbers Less than 6999

8-7

The following steps outline the procedure to be used when installing a system unit option. The rear of
the CPU mounting box, which is housed in the H960-CA or H960-DB (Table 1-1) processor cabinet,
can accommodate three system units. An additional nine system units can be installed in an expansion
cabinet mounting box, which is housed in the H960-D cabinet.
1.

Install the required number of system units in the H960 cabinets and secure them to the

mounting boxes, using the thumbscrews provided.

Plug in the system unit power cables. Two types are used: one connects to the SU backplane
by means of a G772A power connector card (see Figure 8-3 for wiring details); the other uses
Fastab connectors. The G772As are standard, while the Fastab harnesses vary with the
option. The other end of this cable has one (older systems) or two (newer versions) Mate-NLok connectors which plug into the power distributor panels. Installation is shown in detail
as indicated in Table 8-4.

Table 84

SU Power Cable Installation
Cabinet

Version
CPU

H960-D

older

Figure 8-3

Figure 8-5

newer

Figure 8-2

Figure 8-4

Plug in an M920 Unibus jumper module for each system unit that is installed. This module
jumpers the Unibus from one system unit to slots A01, BO1 of the next system unit.
When system units are to be installed in an H960-D expansion cabinet, a Unibus cable is
connected from the last system unit in the processor cabinet to the first system unit in the
expansion cabinet.

A special case is that of an MF11-U/UP 16K memory installed in an old style H960-D
cabinet (it cannot be used in an old version CPU cabinet). In this case (Figure 8-6) a 7009569
conversion harness must be used between the H754 +20, -5 Vdc regulator and the backplane, in addition to the 7009568 harness to the power distributor. One 7009569 can power
two MF11-U/UP backplanes. If only one is used, the jumpers between backplanes should
be cut. One 7009568 is required per backplane.
A field modification kit (FM11-U) is available for these installations. The FM11-U permits
installation of one or two MF11-U/UP backplanes. Refer to the field modification kit print
set for installation procedures (DD-FM11-U).

8-8

POWER HARNESS
7008754

SEE NOTE 1

nia

riiv

CONVERSION HARNESS

7009568 (1 PER MF11-U/UP
BACKPLANE)

NOTE 1:

IN EXPANDER BOX,
PLUG MF11-U/UPs IN
SLOTS:
SU2 & SU3, or

6-8

SU5 & SUB, or

SU8 & SU9

IN 11/40 CPU BOX,
PLUG MF11-U/UPs IN
SLOTS:

REGULATOR
HARNESS
7009569

SUS5 & SU§, or
SU8 & SU9

(1FOR1OR 2
MF11-U/UP

NOTE 2: a. WHEN REMOVING

SLOT E H745 TO

BACKPLANES)

iNSTALL H754 AND

CONVERSION HARNESS,
THE BLUE —15 V WIRE
{FROM P15) MUST BE
REMOVED FROM P1-1
AND A JUMPER WIRE
ADDED FROM P1-1 TO
P3-2, TO PERMIT THE

SLOT D H745 TO PROVIDE
-15V TO THE ENTIRE
BOX.

. THE RED AND WHITE

TO SWITCHED

AC WIRES MUST BE
REMOVED FROM P15

QUTLET
POWER CONTRC.

PINS 6 AND 8 AND

PLUGGED INTO PINS 7
AND 8 OF REGULATOR
HARNESS 7009569.

NOTE 3:

SEE NOTE 3

iF ONLY ONE MF11-U/UP
1S USED, CUT THE UNUSED
JUMPER WIRES AT THE
BACKPLATE TO PREVENT

POSSIBLE SHORT CIRCUITS.

11-2306

Figure 8-6

Installation of MF11-U/UP and FM-11 Kit In Early Systems,
Expansion Cabinet Serial Numbers Less than 6999

APPENDIX A
IC DESCRIPTIONS

The following ICs are described in this appendix. The S or H version of an IC listed below merely
indicates high speed.
1103-1
3101
3404
7474
7485

82S10*
8251
8598
74112
74123
74151
74153
74154
74155
74157
74158
74161
74174
74175
74181
74182
74187
74191
74193

74194
75107

1024-Bit MOS RAM
Random Access Memory
Latch

D-Type Edge-Triggered Flip-Flops

4-Bit Comparator
1024-Bit Bipolar RAM

BCD to Decimal Decoders
Read-Only Memory
Dual J-K Edge-Triggered Flip-Flops
One-Shot
8-Line to 1-Line Multiplexer
Dual 4-Line to 1-Line Data Selector/Multiplexers
4-Line to 16-Line Demultiplexer
3-Line to 8-Line Decoder
Quad 2-Line to 1-Line Multiplexer
Quad 2-Line to 1-Line Multiplexer
4-Bit Binary Counter
Hex D-Type Flip-Flops
Quad D-Type Flip-Flops
4-Bit Arithmetic Unit with Full Look-Ahead
Look-Ahead Carry Generator
1024-Bit Read-Only Memory
4-Bit Binary Counter
4-Bit Binary Counter

Parallel-Access Shift Register with Mode Control
Sense Amplifier (Dual-In-Line)

* 82510 is not the high-speed version of the 8210. (The 8210 is an 8-channel digital switch and not a product of
the 82S10 vendor.)

A-1

1103-1

1024-BIT MOS RAM

A3 ——]

—— READ/WRITE

Ap —

—— Vss

Ag —

18 chip ENABLE

———15 Ag

PRECHARGE
Ag

1103 -1

14
—
—— DATA OUT

—8

12 baTA IN

Ag ——
A5 _8_.

Ll._ VDD

A7 ——

—— Vgg

LOGIC 2 = high voltage level
LOGIC

1 =low

voltage level

TRUTH TABLE

INPUTS

OUTPUT

MODE

not selected

CE | RW

Doyt

Dour

O
R

Read

Write

Read/Write

H=high voltage level

L=low voltage level

X=irrelevant

NOTES:
1. A chip enable is provided for memory array expansion.

2. Before any read/write, or read/writa cycle, a precharge pulse is required to
refresh the addressed memory bit. For a read cycle the data is read from the
addressed location when the chip is selected during the end of a precharge
pulse and read/write is held high. For a write or read/write cycle the read

cycle is executed, however before any enable is unasserted, read/write is held
low. This writes the new data (DATA IN) into the addressed location.
IC-1103-1A

A-2

1103-1

1024-BIT MOS RAM (CONT)

WRITE CYCLE

READ/WRITE CYCLE

ADDRESSVlH
ViL
.

<F®
@

ADDRESS ¥

CAN CHANGE
~

. ——>lat
)
AC
OVH "l—

‘e —

CENABLEV

ViL

tca

- 'PW —_—

PATAIN,

CHANGE

wp—TM

- 'F’O——b

DATA OUT

CLOAD=50pF

R oap= 1002 =

VoL

VREF=80mV

tacce
READ CYCLE

ViH

"®

Vin

ADDRESSVIL @i@

CENABLE

ViL

'ac

ViL

DATA OUT

—

tovL

ViH

OUT te—

VALID

ADDRESS
CAN
CHANGE 7~
—

“lovHTM,—

fl
\L
=
TM

tpov

CLoap =9500pf

=== === N

VREF=80mV

'acct

'acce

T
DATA OUT

VALID

Ay o

Ag 4 ©

1 OF 32
ROW

SELECTOR

32
+

READY

WRITE

AMPLIFIERS

MEMORY MATRIX:

ROWS

32 COLUMS

(1024 BITS}

Vggo—»

Vss
Vppo——*

PRECHARGE

~o—»

READ/WRITE

o—

ENABLE

—

-~ ce tp——

RLoaD= 1000 |\
-

DATA

et PO
o ———

VoL

Apg

VOH

NOT VALID

ADDRESS STABLE

1PC —

READ/WRITE
ViL

Tt
OUT \ '~
DATA AT

fACCI

PRECHARGE

to (NOTE 4)

STABLE

—_—

/ 7 ////% DATA TIME

DATA CAN

'CW

tow (NOTE 3)
VIH

I 'ovL

[

e —

ViH

READ/WRITE

ADDRESS‘ STABLE

le——t,

Vig

PRECHARGE

fwc OR Trwe

o—»

REFRESH AMPLIFIERS
READ/WRITE COLUMN
GATING

DATA IN
DATA OUT

r3z

NOTES:

@ oD

Vpp= 2V

® vgg=2v

10F 32

}t, Is defined as the transitions between these two points,

COLUMN SELECTOR

Ag Ag A7 Ag Ag

3. wa Is referenced to point @ of the rising edge of chip enable or read/write, which ever occurs first,
4. tpy !s referenced to point @ of the rising edge of chip enable or read/write, which ever occurs first,

IC-1103-1

RANDOM ACCESS MEMORY

NON~OVERLAPPING
ROM

16 X 4

DECODER

MATRIX

OF STORAGE CELLS

ENB]

M3 (1)jo—

9 Ipp

M2 (1)jo—2
3101

L 09
4

[WR

< Ip3

M1 (1jo—-

oo
A3

Mo (1)jo—2
A2

JUOU

l13 ‘14 ‘15 |1
VCC=PIN
16
GND=PIN 08

—x

3101

M3
IC~ 310t

A-4

3404

LATCH (DUAL-IN-LINE)

- 3404 p2

4L 3404 P12
q

213404 p*

T"S

~31 3404 &

i
12
—]

101 3404 b2

3404

11
p—

+5V = PIN16

GND = PIN8
IC-3404

A-5

7474 DUAL FLIP-FLOP

TRUTH TABLE FOR

7474 STANDARD CONFIGURATION

(EACH FLIP-FLOP)

tnh

th+1

Preset

Clear

D {nput

1 Side

0 Side

Pin 4(10)

Pin 1{(13)

Pin 2{12)

Pin 5

Pin 6

| High

High

Low

High

Low

High

Low

High

Low

High

Low

High

tn = bit time before clock pulse.

tnt1 = bit time after clock pulse.
X = irrelevant

STANDARD CONFIGURATION

REDIFINED CONFIGURATION

PRESET

Loa o5
02

—-D

1},06

401
02

7474

o-—

P 06

oPos

Yo1

Jo4
CLEAR

PRESET

1}08

7474

O3lc

CLEAR

&10

1},05

7474
05

2, 08

509

7474

OE‘l—B_

Mlc

Onog

T13

T10

CLEAR

Vee: PIN 14

GND=RIN O7

o6
|
—=

IC-7474

7485 4-BIT COMPARATOR

codes. Three fully
The 7485 performs magnitude comparison of straight binary or straight BCDmade
and externally
are
(A,B)
words
4-bit
two
about
B)
=
A
decoded decisions (A > B, A < B,
available at three outputs.

7485

————B3

— 151,32

14 B2

A>B—2§———

a-pp2&

—
—

A<B_EZ.__

“31

121,
— 9914

—

DAQ

IN>

IN=

IN<

04 ‘ws |®2

= PIN
VCC
OND= PIN

16
@8

TRUTH TABLE

CASCADING

COMPARING

A3,B3 | A2,B2 | A1,B1

A0,BO | IN> | IN< | IN=|

A>B|

X
X
X
X
X
X
X
X
L

H
L
H
L

X
X
X
X
X
A3=B3 | A2=B2 | A1>B1 | X
X
A3=B3 | A2=B2 | A1<B1 | X
A3=B3 | A2=B2 | A1=B1 | AO>BO | X
A3=B3 | A2=B2 | A1=B1 | AD<BO | X
A3=B3 | A2=B2 | A1=B1 | A0O=BO | H

X
A3>B3 | X
X
A3<B3 | X
A3=B3 | A2>B2 | X
A3=83 | A2<B2 | X

OUTPUTS

INPUTS

X
X
X
X

A3=B3 | A2=B2 | A1=B1 | A0=BO0 | L
A3=B3 | A2=B2 | A1=B1 | A0=BO | L

X
X
X
X
X
X
X
X
L

H
L

L
H

H
L
H
L
H
L
L

A<B | A=B
L
H
L
H

L
H
L
H
L
H
L

L
L
L
L

L
L
L
L
L
L
H

NOTE: H = high tevel, L = low level, X = irrelevant
1C-7485

82S10 1024-BIT BIPOLAR RAM

[a4

Vee =16

1541

82310

14o wEL

]10

po}’—
A8

GND-=8

CSL =CS=Chip select
WEL = WE=Write enable

|12

[13

TRUTH TABLE

INPUTS

QUTPUT

—

OPEN

Cs | WE | Din

MODE

[COLLECTOR

NOT SELECTED

WRITE O

WRITE 1

Dour

READ

H=HIGH VOLTAGE LEVEL
L=1LOW VOLTAGE LEVEL

X=IRREVELANT
NOTES:
1. A chip select {CS) input provides for memory array expansion.

2. Data is written into the addressed location when WE is held low and the
chip is selected.

3. Data is read from the addressed location when WE is held high and the
chip is selected.
IC-82510

A-8

8251 4 TO 10 DECODER
8751 TRUTH TABLE
f OUTPUT

INPUT
DO

1= High
0 = Low

07«

t8 28
722

fep2

(224 p3

|
14 o2~
f5jo 23

01
BCD
INPUTS

8251
14

DECIMAL

OUTPUT

§3jo+
f2 o

D1
—]

f1 Oig~
15

. — 00

vCC
GND

13
7

PIN 16
PINOS
IC-8251

A-9

8598

READ-ONLY MEMORY

The 8598 is a 256-bit, read-only memory organized as 32 words of 8-bits each. Addressing is accomplished in straight 5-bit binary with full decoding. An overriding memory enable input is provided
which, when taken high, will inhibit the 32 address gates and cause all 8 outputs to remain high.

8598
F——

M7 (1)

_14

——]

—

(10)

M6(1)—7—

—

(AG O—

—

2040

Mal)

10,4
_10]

M2)

5
4
3

BINARY | ap ol12)|

SELECT

A3
a

13)

1 OF 32

DECODE

(14)
14

—

MEMORY CELL

|}—
——

]

M1 (0|2

—

M@ (1)}

—
—

ENB

T15

32 WORD BY 8 BIT

[

MEMORY _ (15) l
ENABLE

M
M@

Pin (16)=Vvcc,pin (8)= GND

(20
M1

[(3)
M2

[
M3

|(B)
M4

|(6)
M5

(T)
M6

{9
M7

OUTPUTS
IC-8598

A-10

74112 DUAL J-K FLIP-FLOP
PRESET

CLOCK—Qg
2

74112
|,

ole

CLEAR

PRESET

CLOCK

13
|
2o

74112

T14
CLEAR

74112 Truth Table

th+1

th
K

Pin5o0r9

No change

Complement

t,, = Bit time before clock pulse.
t,+1 = Bit time after clock pulse.
IC-74112

74123

RETRIGGERABLE MONOSTABLE

MULTIVIBRATOR

The 74123 Monostable Multivibrator provides d-c
triggering from gated low-level active (A) and high-

level active (B) inputs. Overriding direct clear inputs
and complementary outputs are also provided.
By triggering the input before the output pulse is ter-

minated, the output pulse may be extended. The
overriding clear capability permits any output pulse

to be terminated at a predetermined time, independently of the external timing components.

At —O

s s
1

Bt —=

‘

74123

4
13

G EE—

TRUTH

INPUTS

9
—O

|7 5

B2 —

74123

012__
5

NOTE:.

OUTPUTS

B T

I
A2

TABLE

H=high level (steady state), L= low level (steady state),

t = transition from low to high-level, #=transition from

high to low level, _IL= one high-level pulse,
low-leve!

pulse,

X= irrelevant

(any

LI= one

input, including

transitions).

o e

Tn
+5V=PIN 16
GND =PIN 8
IC-74123A

1C-741238

74151 8 TO 1 MULTIPLEXER

74151 TRUTH TABLE
Inputs

§2

S0 | STB

When used to indicate an input, X

Outputs

irrelevant.

STB

74151

6
fop—

I1O

IH
IC-7415

A-13

74153 DUAL 4 TO 1 MULTIPLEXER

ADDRESS

OUTPUT

STROBE

DATA INPUTS

INPUTS

sSTB

L
L

L
H

X
X

L
L

L
H

L
L

L
H

Address inputs SO and S1 are common to both sections.
H = high level, L = low level, X = irrelevant.

23 1p

12
— C1

co
fo

£1
1"

74153

—B1

AOQ

10
—
A1

]

STBO

VCC=

PIN16

.99

74153

SO0

STBi

GND= PINOB
IC-74153

A-14

74154 4-LINE TO 16-LINE DECODER

20 | __
T D3

BCD | — D2

INPUT

FOR DECODING | ——| D1

£y

231 po

STB1

STBO

T19

+5Vv =PIN 24
GND=PIN 12

16 OUTPUTS
1 OF 16 MUTUALLY

74154

[ folsJofols o o]

_.,

f13

f1s

f14

a B & Is E

The 74154 4-Line to 16-Line Decoder decodes four binary-coded inputs into one of 16 mutuallyexclusive outputs when both strobe inputs (G1 and G2) are low. The decoding function is performed
by using the four input lines to address the output line, passing data from one of the strobe inputs with
the other strobe input low. When either strobe input is high, all outputs are high.

Notes For Demultiplexing:

Inputs used to address output line.
Data passed from one strobe input

with other strobe held low.

Either

strobe high gives all high outputs.
1C-74154

(2)

(7) outpuT

DATA (1) |>

STROBE

¥ ¥ Sy

74155 3-LINE TO 8-LINE DECODER

1Y@

(6) ouTPUT
1Y1

() ouTPUT

SELECT (3) l >
B

(4) ouTPUT
1Y3

_fi

DOE)OUTPUT

SELECT (13)

‘I >°——“" >—‘

2Y0

(10) outPUT

]

DATA 15)

—

2Y1

)O (1)1 ouTeuT

—

2Y3

iIC~74155

FUNCTION TABLE
3-LINE-TO-8-LINE DECODER

OR 1-LINE-TO-8-LINE DEMULTIPLEXER
INPUTS

OUTPUTS

STROBE
OR DATA

SELECT

0
(0)

(1)

(2)

3
(3)

(4)

(5)

(6)

7
(7)

2Y3

1Y0

1Y1

1Y2

2Y0

2Y1

2Y2

L
H

H
H

TC = inputs 1C and 2C connected together
}G = inputs 1G and 2G connected together
H = high level, L = low level, X = irrelevant

74155

3-LINE TO 8-LINE DECODER (CONT)

FUNCTION TABLES
2-LINE-TO-4-LINE DECODER
OR 1-LINE-TO-4-LINE DEMULTIPLEXER

INPUTS
SELECT

STROBE

OUTPUTS
DATA

1Y0

1Y1

1Y2

1Y3

INPUTS
SELECT

OUTPUTS

STROBE

DATA

2Y0

2Y1

2Y2

2Y3

74157 QUAD 2 TO 1 MULTIPLEXER

INPUTS

STB | SO

OUTPUT

f
L

H = high level, L = low level, X = irrelevant.

05 1

f2—

_9.3_ BO

£1197

74157

fofi_

L2 1o

STB

T15

STB

‘01

VCC:=PIN 16

GND:=PIN 08

IC-74157

A-18

74158 QUAD 2 TO 1 MULTIPLEXER
OuUTPUT

INPUTS

STB | SO

H = high level, L = low level, X = irrelavant.

1% 1as

3 jo—=
12

22>

74158
09

19 lg2
STB

T15

Al
74158

A PO

STB

T15

l01

‘01

e T

12 g3

16
VCC=PIN
GND=PINOS8

I1C-74158

A-19

74161 SYNCHRONOUS 4-BIT COUNTER
3

{po

14
RO(1)}—

DATA — 21

INPUTS

12_(

N D2

R2(1)}—

1
R3(1)}—

ip3

1
CLEAR ——O|CLR

OUTPUTS

74161

LOAD ——0|LD
2

CLOCK ———{ CLK
i
ENABLE P

CNT EN

ENABLET
15

CRY EN

cop— CARRY

OUTPUT

GND = PIN 8
+5V:=PIN16

typical clear, preset, count, and inhibit sequences

for 74161

Hlustrated below is the following sequence:
1. Clear outputs to zero.

2. Preset to BCD seven.
3. Count
to eight, nine, zero, one, two, and three.
4.

Inhibit

CLEAR

PINOI

[ASYNCHRONOUS)

DO
PINO3

Dt
PINO4

DATA

INPUTS

PINOS

L L L

LOAD

hPINOG

—

CLOCK

PINO2

ENABLE P

PINO7

ENABLE T

PIN10O
RO(1)
PIN14

t
t

R1 (1)
PINI3

OUTPUTS

]

PINI2

R2(1)y —

f
|

PINT)

CARRY
PINtS

—o

|
|

R3(1) . —

|
|

[}

CLEAR

PRESET

|
1

]
1

I 8

COUNT

—=~

INHIBIT ———rer—m—
IC-74161

A-20

74174 HEX D FLIP-FLOP REGISTER

L@)5R0(1)

po o)
— olCLOCK
CLEAR

TRUTH TABLE

LINPUT
fn

fn*'

R(1)

[OUTPUT
@)

D1 o

———0(5) R1(1)

tp = Bit time before

~Q|CLOCK

clock pulse.

CLEAR

tnt1=Bit time after

»—J

clock pulse.

02 &8

LT R2(1)
OICLOCK
CLEAR

o——j

—D5

R5(1)|——

—1D4

R4 (1) b—

(10) R3(1)

DBc( 1

Q| CLOCK

—D3

R3(1) |——

CLEAR

74174
6
R2(1) }——
~— D2

R1 (1) —

3
— DO

2
RO(1)——

CLR

(12) R4 (1)

D4 C(13)

—1 D1

CLOCK

CLK

CLEAR

(15)
—o R5(1)

(14)
D5 ©

cLock o2
r—‘

ocLock

CLEAR

| T
1
CLEAROLCDO—l—-‘
Pin (16)= V¢ ¢, Pin (8)= GND

IC-74174

A-21

74175 QUAD STORAGE REGISTER

TRUTH

DOO——————-() DO FP)P""Q(
4

TABLE

INPUT | OUTPUTS
th

th+i

R(1)R(O)

H
L

RO|

(3)
CLK (oc;—o
CLEAR

L
H

th =Bit time before

clock pulse.

Dlsfi

th+1=Bit time after

(R11)—O(7)

clock pulse.

QICLK (o)-——O(G)
CLEAR

.1
ch(lz,)

[Bos

(10}

R3(0) |—

R2
CLK (g)

(1)

L] L

CLEAR

B
1

R2(0) P

DATA
INPUTS

74175

> 1oy

R1(1)
R1(0) Fo-

OUTPUTS

p3 o)
(13

(9)

CLOCK o—
4

:.'\:2)

ran}>

Rro(n

—

RO(0) -2
CLEAR
CLR

CLK

D3 <R13)-“)°
(15

CLEAR

Pin (16)= Voc, Pin (8)2GND
IC-74175

A-22

74181 4-BIT ARITHMETIC LOGIC UNIT, ACTIVE HIGH DATA

The 74181 performs up to 16 arithmetic and 16 logic functions. Arithmetic operations are selected by
four function-select lines (SO, S1, $2, and S3) with ia low-level voltage at the mode control input (M),
and a low-level carry input. Logical operations are selected by the same four function-select lines
except that the mode control input (M) must be high to disable the carry input.
74181
TABLE OF LOGIC FUNCTIONS

Function Select

Negative Logic

Positive Logic

f =A

f=A

I
L

H
L

t=A+B

f =AB

f=A+8B

f = Logical 1

f = Logical O

H
H

L
L

H
H

L
H|

—

f = AB
f=B

f=A+8B

L | f=

f = Logical O

=AB

”\YVP%F}%

f = Logical 1

f =AB

f=A+B

f =A

f=A

For negative logic:

logical 1 = low voltage
logical O = high voltage

fea —

g FUNCT ION

74181

OUTPUTS

—1 A1
O fgo

With mode control (M) high: C;, irrelevant

logical 1 = high voltage

—1B1

f=A+B

For positive logic:

CcouT

B3
19 | a3

f =AB

f=AB

PROPAGATE

20 {45

f=8

f=A+B

f=A®B

f =A®B

lus

A=B

f=A+B

L | f=AB

CARRY

=A®B

=AB

f=A+B
=8B

CARRY
GENERATE

CARRY

Output Function

L
L

COMPARATOR

OUTPUTS

_——1 AO

logical 0 = low voltage

|04

|05

CIN

SO
|06

|08

(07

MODE

CARRY
INPUT

vCC=PIN 24
GND =PIN 12

FUNCTION
SELECT

INPUTS
IC-7418)

74181
TABLE OF ARITHMETIC OPERATIONS
Function Select

Output Function

Low Levels Active

High Levels Active

f=A minus 1

f = AB minus 1

f=AtB

f = AB minus 1

f=A+B
f = minus 1 (2’s complement)

f=A

f = minus 1 (2's complement)

f = A plus [A + B]

f=A plus AB

f = AB plus [A + B]

f = [A + B]) plus AB

f = A minus B minus 1

f=A plus [A
+ B}

f = A plus
AB

f=AplusB

f = AB plus [A
+ B]

f = [A + B] plus AB

f=A+8B

f = AB minus
1

f=A plus A¥

f=Aplus At

H
H

L
H

H
L

f=AB plus
A
f = AB plus
A

f=[A+B] plus
A
f=[A +B] plus
A

f=A

f=A minus 1

f=A+8B

With mode control (M) and Cin low
t Each bit is shifted to the next more significant position.

A-23

f = AB minus1

74182 LOOK-AHEAD CARRY GENERATOR
The 74182 Look-Ahead Carry Generator, when used with the 74181 ALU, provides carry look-ahead

capability for up to n-bit words. Each 74182 generates the look-ahead (anticipated carry) across a
group of four ALUs and, in addition, other carry look-ahead circuits may be employed to anticipate

carry across sections of four look-ahead packages up to n-bits.

Carry inputs and outputs of the 74181 ALU are in their true form, and the carry propagate (POUT)
and carry generate (GOUT) are in negated form.

PIN DESIGNATIONS

Designation

Pin No.

Function

GO0,G1,G2,G3

3,1,14,5

PO, P1,P2,P3

4,2,15,6

ACTIVE-LOW CARRY PROPAGATE INPUTS

CIN

CARRY INPUT

ACTIVE-LOW CARRY GENERATE INPUTS

COUTX, COUTY, COUTZ

12, 11,9

CARRY OUTPUTS

GOUT

ACTIVE-LOW CARRY GENERATE OUTPUT

POUT

ACTIVE-LOW CARRY PROPAGATE OUTPUT

Vee

SUPPLY VOLTAGE

GND

GROUND

|1o

| 07

Loe

GOUT

POUT

couTz

74182

COuTY

COouTX

13
—OICIN

74182

VCC=
GND=

74182

PO
04

PIN 16
PIN O8
1C-74182

A-24

74187 1024-BIT READ-ONLY MEMORY

1024

BIT MEMORY CELL

(A7 —
(15)

A6 ——P
i)

91
A5 —

*(2)

DECODER

MEMORY MATRIX

A4 —
(3)

BINARY
SELECT

A3 (4)

v or s

A2—=
Al
AO (6)

DEC ODER

of s

TM
|>
5

DECODER

TM v ofF 8 [ 1 oF 8
—*1 DECODE R >
> DECODER

(5)

MEMORY

ENB 1

ENABLE

ENB2

(14)

(13)

(11

(10)

(9)

\/~

(12)

OUTPUTS

—_—
03

74187

10
M2(1) o—7m

———]

M3 (1)

N
M1(1)
(1)

ENB1

ENBO

T14

T13

VCC =PIN

o————

GND
= PIN 08
IC-74187

A-25

74191

4 BIT UP/DOWN COUNTER

The 74191 is a 4-bit binary counter that counts in

BCD or binary and can operate as an up or down
counter. The counter can be preset by the load control and uses a ripple clock output for cascading.

DOWN/UP

ENABLE

LOAD

MODE

Parallel Load

No Change

Count

Count Down

L =low level

X=irrelevant

H = high level

NOTE

NOTE
2

112

MAX/MIN

(29 o3
12 1r,

DATA {
INPUTS

{4,

RCLK

74191

R3 (12
r2 (1)} 28
02

RY (1)}

rRo( 2>

DN/UP CLK

» OUTPUTS

ENB

To Jos ha oo
VCC= PIN 16
GND= PIN @8

NOTES
1. MAX/ MIN produces a high level output pulse
when the counter overflows or underflows.

2.Ripple clock produces a low level output pulse
when an overflow or underflow condition exists.
IC-74191A

A-26

typical load, count, and inhibit sequence:

Illustrated below is the following sequence.

Load (preset) to binary thirteen.

Count up to fourteen, fifteen (maximum), zero, one and two.
Inhibit

Count ddwn to one, zero (minimum), fifteen, fourteen, and thirteen.

I
|

(" PIN 15 DO

]

10 D2

:
{

—

————

—

c—

—

—_—

—

r—_

—

—_

—_-

—

Epe
pEREREE.
N e
EpEp
NpEp
:.
|
P

]

[E——

PIN3 RO(1) __|
-_——

PIN2 RI(1) __ 1

[

1]
]

[

PIN7 R3(1)
_ _ | !}

|
b

]

PIN 42 =7~
MAX/MIN = = =

— —7

{

|
:

b
—

]

2,2
1

| b——count up——}- inmieiT=)

RIPPLE CLOCK — — 3],
& 14 15L o
PIN 13

[

ll ,

-———

[

- —

6 R2 (1

—

DOWN/ UP

SR
CLOCK
ENABLE

—
OBe
!

nj,__

PIN 1 D1

DATAfi
INPUTS

11 LOAD
PIN

Ll
0
15

—— count oown

LOAD
IC-74191B

A-27

74193

4-BIT UP/DOWN COUNTER

The 74193 Binary Counter has a individual asynchronous preset to each flip-flop, a fully independent clear

input, internal cascading circuitry, and provides syn-

chronous counting operations.

typical clear,load,and count sequences for 74193

{llustrated below 15 the following sequence:
1. Clear outputs to zero.

2. Load (preset} to BCD thirteen.

3. Count up to fourteen, fifteen, carry, zero, one, and two.
4. Count down to one, zero, borrow, fifteen, fourteen, and thirteen.

SEE
NOTE

PIN 14

l(Z lfl
PIN11

CRY

1LOAD

BRW
PIN 15

DATA
INPUTS

RN 06

ra1es

19102
01

— Dt

RI(1) —

15
—100

RO(1) [—

(OUTPUTS

PIN Q1

R3() -

DATA

°IN 10
PINO9

PINO5 0VOUN!
CLR

CUP

CDN
PINO4 UOUNT

]14 Tn ‘05 ‘04

DOWN

SEE SEE

“—~—

NOTE

INO3 RO(1)

NOTE NOTE SEE
4

PINO2

RI1 (1)

PINO6

R2 (1}

PINO7

R3(1)

Clear overrides load, data, and count inputs.

When counting up, count down input must be high;

when counting down, count-up input must be high.

NOTES:

Produce pulses equal to width of count pulses
during:

Underflow (BORROW)
PIN 12 CARRY

Overflow (CARRY)

—

OUTPUTS

CLR input high forces all outputs low.

CLR

overrides load, data and DN/UP inputs.

PIN 13 HORROW

[

Preset to any state by applying input data with
load input low.

Output changes to agree with inputs

independent of count pulses.

Select DN or UP clock while other is held high.

ll:il

SEQUENCE
ILLUSTRATED

CLEAR

oo
PRESET

)

CCUNT uUP

— COUNT DOWN

A-28

/4193

74194 PARALLEL-ACCESS SHIFT REGISTER WITH MODE CONTROL

MODE
CONTROL

SHIFT

RIGHT

SERIAL
‘10

|09

f 03
04

S®

INPUTS

DSR

RO (1)

R1{1)

PARALLEL

INPUT

‘02

74194
05

\ PARALLEL

R2 (1)

t LA D3

R3 (1)

OUTPUTS

12
-~

CLR

VCC=PIN 16

CLK

Tm In

DSL

l;\

GND
= PIN @8

SHIFT LEFT
SERIAL INPUT

MODE CONTROL

PARALLEL LOAD

SHIFT RIGHT (IN THE DIRECTION RO TOWARD R3)

SHIFT LEFT (IN THE DIRECTION R3 TOWARD RO)

INHIBIT CLOCK (DO NOTHING)

L
IC-74194

A-29

75107

SENSE AMPLIFIER (DUAL-IN-LINE)

TRUTH TABLE

675107

S ————

DIFFERENTIAL
INPUTS

Vip

-25mV

6
S

—_—

75107

STROBES

A-B

< V5 <25 mV

LorHlLor

Vip
€ -25mV

LorH

fLorH

H
Y

OUTPUT

H | INDETERMINATE

LorHj

fLorH

GND=7
-VCC=13
+VCC=14
IC-75107

A-30

APPENDIX B

PERIPHERAL PREVENTIVE
MAINTENANCE SCHEDULE

Man-Hours

(approximate)

Peripheral
Monthly

0.25

LA30 DECwriter
TU56 DECtape Transport

0.25
1.0

weekly
monthly

0.5

RKO5 Disk Drive
TU10 DECmagtape Transport

0.5
1.25

weekly
monthly

0.25

CR11-A Card Reader
(300 cpm M200)

0.25

CD11 Card Readers
(M1000, M1200)
Quarterly

LA30 DECwriter

0.75

RKO05 Disk Drive

1.0

RP11-C/RPO3 Disk Pack System

0.75

PCO5 Paper Tape Reader/Punch

0.75

TU10 DECmagtape Transport

1.75

LP11-F, H Line Printer

1.0

LP11-J, K Line Printer

1.0

LP11-M, Q Line Printer

2.0

B-1

Quarterly (Cont)
LP11-R, S Line Printer

2.0

CR11-A Card Reader (M200)

0.75

CD11 Card Readers

0.5

(M1000, M1200)
LPS11 Laboratory Peripheral System

3.0

*KB11-A Central Processor

3.0

*MS11 Semiconductor Memory System

0.5

*KT11-C Memory Management Unit

0.5

*FP11-B Floating Point Processor

0.75

*MM11-S Core Memory

0.5

*Run all diagnostics on system
Semi-Annual

RKOS5 Disk Drive

1.0

LP11-M, Q Line Printer

3.5

LP11-R, S Line Printer

3.5

LV11 Printer/Plotter

3.0

RKO3 Disk Drive

1.0

RP11-C/RP03 Disk Pack System

2.75

NOTES:
1.

For any devices not listed, run their associated

diagnostics programs quarterly.
2.

Analog devices are not included in this list
because of the numerous options and variations

that are available.
3.

All man-hour requirements are approximations.

PDP-11/45 Timing Margins Preventive Maintenance Chart
Margin

Clock

KB11-A,D

Test Program

+ns

- ns

+ns

-ns.|

-ns

+ns

-ns

+ns

—ns

+ns

DCKBO

States Test

DZQGA

General Test Program

DCKTG

If KT11-C is
implemented
DZFPO
If FP11-B is

implemented
DIGB

Use MS11 if
implemented
DEFPA

If FP11-C is
implemented

DEFPB

If FP11-Cis
implemented

FP11-B

DZFPO
FP Exerciser

DZFPP
General Test Program
with FP Overlay

Note:

Refer to Paragraph 6.2.1 (Clock Selection) for timing adjustment procedures.

B-3

—ns

+ns

-ns

APPENDIX C

SUMMARY OF
EQUIPMENT SPECIFICATIONS

This table provides mechanical, environmental, and programming information for PDP-11 optional

equipment. The equipment is arranged in alphanumeric order by model number.
NOTES
l.

Mounting Codes

CAB = Cabinet mounted. If a cabinet is included with the option, it is indicated by an X in
the “Cab Incl” column.

FS = Free standing unit. Height X Width X Depth dimensions are shown in inches.
TT = Table top unit.

PAN = Panel mounted. Front panel height is shown in inches. An included cabinet is
indicated when applicable.

SU = System Unit. SU mounting assembly is included with the option.

SPC = Small Peripheral Controller. Option is a module that mounts in a quad module, SPC

slot.

MOD = Module. Height is single, double, or quad.

() = Option mounts in the same space as the equipment shown within the parentheses.
Some options include 2 separate physical parts and are indicated by use of a plus (+) sign.

Cabinet and peripheral equipment (such as magnetic tape) are included in the specifications.
Relative humidity specifications mean without condensation.

Equipment that can supply current is indicated by parentheses ( ) around the number of
amps in the POWER section. MEMORY POWER: MF11- and MM11- require the same
amount of power. In this table, MF11- power figures show the power required when the
memory is active, while MM11- figures reflect that required by an inactive unit.
Non-Processor Request devices are indicated by an X in the “NPR” column.
7008855 in 11/45, 11/50, 11/55 CPU; 7008909 in H960-D and 11/40.

C-1

77009174. If first MF11-L in 1140, use 7009103.

7009560. If first MF11-L in 11/40, use 7009565.

H960-C, D only (not CPU Cabinet): one 7009568 per backplane (9 pin conversion) and one
7009569 for two backplanes (regulator harness).

10.

7009162 in 11/45, 11/50, 11/55 CPU; 7009099 in H960-D and 11/40.

CONVERSION FACTORS

(inches)
(1bs)
(Watts)

[(°C)X9/5]+32

X
X
X

2.54
0454
341

=
=
=

(cm)
(kg)
(Btu/hr)

(°F)

C-2

Model

MECHANICAL

Description

Number

Mounting

Size

Code

Cab

HXWXD

Weight

Incl

(Ibs)

ENVIRONMENTAL

Power Harness

Early

New

(inches)

AA11-D

D/A Subsystem

SuU

ADO1-D

A/D Subsystem

PAN

AFC11

A/D Subsystem

CAB

BA11-ES

Mounting Box

PAN

BA614

D/A Converter

(AA11-D)

BBI11

Blank Mntg Panel

BB11-A

Blank Mounting

Note 6

5%
10%

7009562

POWER

PROGRAMMING

Oper

Rel

Temp

Humid

(°C)

(%)

10-50

20-95

0.5

0-55

10-95

0.5

10-55

10-95

1700

772570

Cur needed/(supplied)

#5V |

115 Vac / Other
(amps)

100

UNIBUS

Power

Ist Reg

Dis

Int

Address

Vector

Bus

Level

Model

Loads

Number

776 756

140,144

4,5

776 770

AAl1-D

130

ADO1-D

134

AFCt1

NPR

(W)

BA11-ES
BA614
BB11
BBi1-A

Panel (non-slotted

blocks)

BC11A

UNIBUS Cable

BM792-Y

Bootstrap Loader

SPC

CB11

Telephone Switching

Cab

BC11A

0.3

300

10-50

Interface

10-90

5.6

650

764 000

float

4-7

BM792-Y

1,2

CB11

CDI1-A

Card Reader

SU+TT

CD11-E

14X 24X 18

Card Reader

SU+TT

Note 6

7009562

10-50

10-90

Note 6

10--90

230

2.5

700

CD11-A

400

CD11-E

1.5

230

CR11

SuU

UNIBUS Window

7009562

777 160

DA1I-F

Note 6

400

CM11-F

SuU

10-90

230

UNIBUS Link

10-50

777 160

DAI11-B

11 X 19X 14

1.5

SPC + TT

10-90

230

Card Reader

10-50

772 460

CR11

11X 19X 14

10-50

772 460

SPC + TT

7009562

450

Card Reader

200

2.5

CM11-F

38 X 24 X 38

124

DA11-B

Bus Repeater

7009563

772410

DB11

7009099

DA11-F

DCI1I-A

Asynch Linc Inter

Note 6

float

1+1

DB11

DD11-A

Periph Mntg Panel

DD11-B

Periph Mntg Panel

DD11-D
DECkit 01-A

Periph Mntg Panel

7009562

5-50

10-95

Note 6

7009562

10-50

20-90

Note 6

7009562

Note 10

7009563

28U

Remote Analog Data

PAN

5 X 19X 13

see Product Bull

I/O Interface: 3

DD11-B
10-95

1.5@115 Vac

175

DECkit 01-A

0-70

10-95

1.84

User

DECkit 11-F

Note 6

0-70

10-95

3.91

User

5-6

DECkit 11-H

Note 6

0-70

10-95

1.97

User

DECkit 11-K

SuU

Note 6

0-70

10-95

1.75

User

DECkit 11-M

1/O Interface: 4
Words In/4 Words

QOut
I/O Interface:

8 Words In
DECkit 11-M

DC11-A

Note 6

Out

DECkit 11-K

0.75 @ 230 Vac

Words In/4 Words

DECkit 11-H

float

TMD11-D

Channels, Serial

DECkit 11-F

774 000

DD11-A

0-50

Concentrator: 8

3.2

I/0 Interface:
Instrumentation

User

Interface
DFO1-A

Acoustic Coupler

DF11

Line Sig Cond

DF slot

DHI11

Asynch Line MX

28U

DI11

7009466

Asynch Line MX

7009561

7009099

DL11-A

7009563

Terminal Control

SPC

DLI11 (others)

Asynch Line Inter

SPC

DL11-W

Asynchronous

6XTX12

0—-60

0.3

5-45

10-95

8.4
5

SPC

Quad Ht

float

see Product Bull.
0.1SA@-15V

1.8

0.15A@-15V

0.05A@+15V

Modem Ctr. MUX

(DH11)

Microprocessor and

2 SPC

2.8

2 Hex Ht

float

DH11

float

DJt1

777 560

060,064

DLI11-A

DL11 (others)

DL11-W

776 500

float

A.Int.-SS | A.Int.4

(SS)

CLK-104

775 000

float

Selectable { Line

Line

]

| CLK-6
5

float

4.5

Line Unit

Switch

0.15A@-15V

Line Clock
DMC-11

DF11

024A@-15V

1.8

Interface and

DM11-BB

DFO1-A

see Product Bull.

_
X

DM11-BB

DMC-11

]

DNI11

Auto Calling Unit

DP11

Note 6

7009562

Synch Line Inter

0—40

20-90

1.4

0.10A@+ 15V

775 200

float

0-40

DN11

DMA Sync Line

7009562

DQI1

Note 6

20-90

7009099

0.i10A@+15V

7009563

10-50

10-90

774 400

5.7

float

004

float

DP11

DQ11

DR11-B

Interface

A@+15V

007 A@-15V

DR11-B

DMA Interface

DR11-C

General Interface

SPC

[

DTO3-F

UNIBLS Switch

PAN

DX11

IBM Chan. Interface

CAB

’

GT40

Graphics Terminal

}

Note 6

7009562

10--50

10-50

S
X
18 X 20X 24

20-90

772410

124

20-90

1.5

767 770

float

DKIT-L

user

1+1

DTO3-F

4-7

180

1055

10-90

2.5

300

776 200

150

float

15-35

20—80

1500

float

C-3

]

DX11-B

GT40

Model
Number
H312-A
H720-E
H722
H742
H7420
H744

H745
H746

H754
H933-C
H933-D

H960-C
H960-D
H960-E

HI961-A
KEI1-A
KG11-A
KW11-L
KW11-P
LA30
LC11-A
LP11-F
LP11-]
LP11-R

LPS11
LS11
LT33
LV1l
M105
M783
M784
M785
M792
M795
M796
M920
M930
M1501
M1502

M1621
M1623
M1710
M1801

Description
Null Modem
Power Supply
Transformer
Power Supply
Power >upply
+5 V Regulator

-15 V Regulator
MOS Regulator

+20, -5 V Regulator
Mounting Panel

(H803 blocks)

Mounting Panel

(H808 blocks)

Cabinet
Cab (1 drawer)
Cab (2 drawers)

Cab w/o side pan
Ext. Arith. Elem.
Comm Arith Unit
Line Clock
Programmable Clock
DECwriter
LA30 Control
Printer (80 col)
Printer (132 col)
Ptr (heavy duty)

Lab Periph System
Line Printer
Teletype
Electrostatic Ptr
Adrs Select Module
Bus Transmitter
Bus Receiver
Bus Transceiver
Diode ROM
Word Count
Bus Control
Bus Jumper
Bus Terminator
Bus Input Interface
Bus Output Interface
DVM Data Input
Instrument Remote
Control Interface
Unibus Interface
Foundation
16-Bit Relay Output

Interface

Mounting
Code

Size
(HX WX D)
(inches)

MECHANICAL

Cab
Incl

Weight
(Ibs)

Power Harness
New
Early

Oper
Temp
°C)

0-50

(BA1l)
(PC11-A)
(H960-D) _
(H960-D)
(H7420 or H742)
(H7420 or H742)

ENVIRONMENTAL

POWER

Rel
Humid

Cur needed/(supplied)
+5V I 115 Vac / Other

2095

(22)

(%)

(amps)

(25)
(25)

6
18

(H7420 or H7420

FS
FS
FS

FS
SU
SPC
MOD
SPC
FS
SPC
SPC + FS
SPC + FS
SPC + FS

PAN
SPC + TT
FS
SPC + FS
MOD
MOD
MOD
MOD
SPC
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD &
SPC
MOD

(W)

PROGRAMMING

Ist Reg
Address

Int
Vector

BR
Level

UNIBUS

NPR

Bus
Loads

Model
Number
H312-A
H720
H722
H742
H7420
H744

700

(10A)@-15V
(1.6 A)@232V

H745
H746

(J6A)@-5V

H754
H933-C

(33A)@19.7V

(8A)@+20V

(H742)
SU
SuU

(10A)@-15V
1.5 A@230 Vac
(1A @+15V

Power
Dis

(1A)@-5V

H933-D

72X 21 X 30
72 X 21 X 30
72X 21X 30

72X 21X 30

single ht
31 X21X 24
46 X 24 X 22
46 X 48 X 25
48 X 49 X 36

5%
12X 28X 20
34 X 22X 19
38X 19X 18
single ht
single ht
single ht
single ht
double ht
single ht
double ht
quad ht
quad ht
quad ht
quad ht

X
X
X

120
300
470
120

110
200
575
800

80
155
60
160

7008754
7008754
Note 6

7009566
7009566
‘
7009562
15-35
10—43
10-43
10-43

20-80
15-80
15-80
15-80

5-43 | 20-80
5-38 5-90
15-35 20-80
10—43 20-80

0-70
0-70
0-70
0-70
0-70
0-70

10-95
10-95
10-95
10-95
10-95
10-95

(75) 8
(150) |16
4
1.5
0.8
1
3
1.5
1.5 2
1.5 4
1.5 17

1.5
1.5
0.34
0.2
0.2
0.3
0.23

3
3
2
5

(20A)@-15V
40A@-15V

900
1800

300
250
500
2000

300
300
200
600

H960-C
H960-D
H960-E

777 300
770 700
777 546
772 540
777 560
777514
777514
777 514

float
777514
777514

100
104
060,064
200
200
200

float
200
200

6
6
4
4
4
4

4-6
4
4

opt

C-4

2
1
1
1

773 000

1.25
0.3
0.75
0.78
1.6
0.79
1.46

1
1
1
|
1
1
1
1

H961-A
KE11-A
KGI11-A
KWI11-L
KWii-P
LA30
LC11-A
LP11-F
LP11-]
LP11-R

LPS11-S
LS11
LT33
LVi11
M105
M783
M784
M785
M792
M795
M796
M920
M930
M1501
M1502
M1621
M1623
M1710
M1801

MECHANICAL

Model

Description

Size

Cab

Weight

Code

HXWXD)

Incl

(Ibs)

Number

(inches)
M7820

Interrupt Centrol

MOD

single ht

M7821

Interrupt Control

M9301(-YA),

MOD

Bootstrap Terminator

single ht

Unibus Slot

Double Ht

Core Memory (8K)

PAN

(YB), (YD)

MEII-L

ENVIRONMENTAL

Mounting

Power Harness
Early

New

Oper

Rel

Temp

Humid

(%)

POWER

Cur needed/(supplied)
+5V I

(amps)

0-50 | 10-90

MF11-LP

Parity Memory (8K)

Note 7

Note 8

0-50

2SU

10—90

3.4

MF11-U

Core Memory (16K)

Note 7

Note 8

2SU

0-50

10—=90

4.9

Note 9

7009535

0-50

0—90

4.5

MM11-L
MM11-LP
MM11-U

MM11-UP

Parity Memory (16K)

Note 9

7009535

0-50

0-90

0-50 | 10-90
0-50 | 10-90

Parity Memory (16K) | (MF11-UP)

0-50

MS11

Semiconductor Mem

(11/45)

PCl11

Paper Tape

SPC + PAN

10%

PDM70

Programmable Data

5% X 19X 23

0-90

0-50

10—80

13-38

20-95

0-40

10-95

Level

NPR

Bus

Model

Loads

Number

(W)

6A@-15V

125
125

SPC + PAN

10%

RC11-A

Disk & Control

PAN

13-38

10%

20-95

RF11-A

Disk & Control

115

RKO05

PAN + PAN

Disk Drive

16+ 16

17-50

PAN

500

10%

RK11-D

Disk & Control

110

SU + PAN

10%

40X 30X 24

X
X

RP11-C

Disk & Control

CAB+FS

RS11

Disk Drive

PAN

RS64

Disk

PAN

10%

RTO1

Numeric Data Entry

6.5X 125X 15

63X 144X 16

X
16

Entry Terminal

250

415

7008992

M7821

M9301(-YA),

ME11-L

(-YB), (-YD)

MF11-L

6A@-15V

125

35A@20V

MF11-LP

120

MF11-U

120

MFT1-UP

125
125

1
1

MM11-L
MM11-LP

34A@20V

05A@-5V

1.7
1.7

0.5A@-15V
05A@-15V
05A@20V

4.5

0.5

MM11-U

A@20V

1.5

MM11-UP

350
115 Vac
230 Vac

Paper Tape (rdr)

Alphanumeric Data

Vector

05SA@-5V

PR11

Terminal

Address

0.6

Mover

Disk Drive

Dis

05A@-5V

2 SPC

RTO02

4.5

Bootstrap

RPO3

05A@=-5V

(MF11-L)
(MF11-LP)

MR11-DB

2SU

Core Memory (8K)
Parity Memory (8K)

Int

Core Memory (8K)

MF11-UP

UNIBUS

Ist Reg

M7820

MF11-L

2SU

115 Vac'/ Other

PROGRAMMING

Power

7009562

1.5

772 100

114

777 550

070,074

MR11-DB

MS11

250

PC11
PDM70

250

350

777 550

070

20-80

2.2

PR11

250

17-33

20-55

777 440

210

6.5

20—80

777 460

RC11-A

15-43

750

204

160

15-43

20—-80

15-33

10-80

7.5

740

15-33

10-80

100

17-33

2055

17-50

20—-80

2.2

0-40

10-90

0-40

10-90

200

6 A @230 Vac

1300

6 A @230 Vac

2100

777 400

220

RK11-D

RP03
776 710

254

200

RP11-C
RS11

250

RS64

RTO1

110 Vac

220 Vac

RTO2

0.25 @115 Vac

0.12
.

RF11-A

RKO05

@220 Vac

TA11

Cassette

SPC + PAN

TC11-G

DECtape & Control

20-80

260

214

1000

TC11-G

772 520

224

TM11

10%

15-27

1000

PAN

9
9

DECtape Transport

40-60
40-60

777 340

TUS56

15-27
15-27

870

PAN

500
450

X
X

40-60

777 500

26+ 10%
26

15-27

120

PAN + PAN

250

Magtape & Control
Magtape Transport

10% + 10%

10-40

TM11
TUI10

PAN + PAN

40—-60

350

1.5

UDC11

1/0 Subsystem

VRO1

CAB

Display

PAN

10%

5-50

10-90

Display

PAN

10-50

120

Display

VT01

10%

10-90

1700

VR14

10-90

12X 19X 30

0-50

400

Alphanum Terminal

12X 12X 23

10-50

VTO05

10-80

2.2

10-43

8-90

250

130

TAll

TU10

771 774

234

TUS6

4,6

UDC11
VRO1
VR14

VTO1

VTO5

Reader’s Comments

PDP-11/45, 11/50, 11/55 System
Maintenaance Manual
EK-11045-MM-007

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