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Document:	PDP-11/40, -11/35 (21 Inch Chassis) System Manual
Order Number:	EK-11040-TM
Revision:	2
Pages:	152
Original Filename:

OCR Text

PDP-11/40,-11/35

(21 inch chassis)
system manual

dlilgliltiall

EK-11040-TM-002

lillhar PD P,; 11/40,-11/35
LPA(21 mch chassss)

| system manual

digital equipment corporation - maynard. massachusetts

4th Printing, January 1975

The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no respon~

sibility for any errors which may appear in this
manual.

Printed in U.S.A.

" The following are trademarks of Digital Equipmeht
Corporation, Maynard, Massachusetts:

DEC
FLIP CHIP

DIGITAL

UNIBUS

PDP
-~

FOCAL

COMPUTER LAB

First Edition, June 1973

2nd Printing (Rev), February 1974
3rd Printing, July 1974

CONTENTS
Page

CHAPTER 1
1.1

1.2

1.3

1.3.1
1.3.2

1.3.3
1.3.4

1.3.5
1.3.5.1

- 1.3.5.2
1.3.5.3

1.3.6
1.3.7

1.3.8
1.4

e e e e e e e e e i e e e e e 1-1
SCOPE . ... ... . ..., e
e e e e e e e e e e e e 1-1
SYSTEM COMPONENTS .. ... ......... e
e e e e e e e e e e e e e e e - 1-1
e
e
e
e
o
.
.
.
.
.
FUNCTIONAL DESCRIPTION
e e 1-4
e e e ee
e
e
ee
e
e
e
e
e
e
Unibus . . . . o o e e
)
R
e
e
e
e
e
e
e
e
e
e
e
...
...
..
.
KD11-AProcessor . .
1-6
e
e
e
e
e
e
e
..
..
...
...
.
.
.
Console
KY11-D Programmer’s

MF11-L Core MEMOTY . . v« « v o v v v v e et e e e e e e U ...

. ... .. ........e e e U

BB|

. PR e e . 1-7
Optional Memory Systems . . . . . . ...
e 1-7
et e e e e e e e e e e e
e
o
o
¢
«
«
=
«
«
.
MEMOTIES
PDP-11/40
18
....
e
e
e
e
e
e
[
.
.
.
.
.
Memories
PDP-11/20
1-9
e
e
e
e
e
e
e
e
e
e
v
e
e
e
i
v
v
v
v
.
«
.
MEMOTY
U/UP
Core
MF1119
.
e
e
e
e
e
e
e
e
e
e
e
e
e
e
...
...
...
.
.
LA30 DECwriter
1-10
oo
o
.
.
.
.
.
.
.
.
.
.
Interface
Line
DL11 Asynchronous
e e ... 1-10
Power System . . . . . . . ... ... ... e e e e e e e e

APPLICABLE DOCUMENTATION

1.5

ENGINEERINGDRAWINGS

CHAPTER 2

INSTALLATION

2.1

2.2
2.2.1
2.2.2

2.2.3

2.2.3.1

2.2.3.2
2.2.3.3
2.2.3.4

2.2.3.5

2.2.3.6

2.2.4
2.3

2.3.1
2.3.2
2.3.3

2.3.4
2.3.5

2.3.5.1

2.3.5.2
2.3.5.3

2.3.6
2.3.7

2.3.8
2.4
25

INTRODUCTION

. . ... ... ... . ... ... e

e e A . 1-13

e e e eA
e e e
i e
it
SCOPE . .. ... . . @
2-1
e
e e e e
e
e
e
e
e
e
e
..
...
...
...
..
.
N
SITE PREPARATIO
272
e
e
e
e
e
e
e
..
.
...
.
.
.
Dimensions
Physical
A 2-2
Fire and Safety Precautions . . . . . ... ... .. I
23
e
e
e
e
e
e
e
e
e
..
...
...
.
.
.
.
.
Requirements
Environmental
23
e
e
e
e
.o
..
.
.
.
.
.
.
.
.
Temperature
and
Humidity
2-3
e
e
e
o
.
.
.
.
.
.
.
Conditioning
Air
~ Acoustical Damping . . . . ... ... e e e e e e e e e e 2-3
Lighting . ... ... ... e e e e e e e e e e [ 2-3
Special Mounting Conditions . . . . . e e e e e e . 2-3
e e e e e e 2-3
Static Electricity . . . . . . . .. e e e e e e e e
e e 23
o ee
Electrical Requirements . . . . . . . . .« . oo
INSTALLATIONPROCEDURES . . . .. ... ... .. ... ... S 2-4
e e e e e e . L. 24
Unpacking . . . ... ... .. e
e e e 2-5
e e e e ee
Inspection . . . . . . ... ... e
Cabinet InStallation . . « « « v o e e e e e e e e e e e e e e e e e e e e 2-5
AC Power Connections . . . « v v v v v v b e e e e e e e e e e e e e e e e e 2-6
e e 2-6
Intercabinet Connections . . . . . . e e e e e e e e e e e
Unibus Connections . . . . « v v v o v v v v v v v v e e e PR 26

Remote Power CONNECHONS

- + « v v v v v v e e e e e e e e e e

e 2-6

Ground Strapping . . . . . . ..o e e e e 2-6
Remote Peripheral Interconnection- . . . . . e e e e e e e e e e - 24
Installation Verification . . . . . O . 27
Initial Power Turn-on . . . . . . . . ... . .. e e e e e .. 212
INITIAL OPERATION AND PROGRAMMING . . .. ... . .. ... .. 2-13

CUSTOMER ACCEPTANCE . . . . . . ..

e ... 2-13
e

~ CONTENTS (Con

t)
Page

CHAPTER 3

SYSTEM OPERATION

3.1

SCOPE

3.2

KY11-D PROGRAMMER’S CONSOLE

3.3

DECwriter

e e

TELETYPE

BASIC OPERATION

3.5.1

PowerOn

3.5.2

Basic Console Control

. . . .. ........ e P 3-20
. . .. .........................320

ENABLE/HALT Switch

3.5.2.2

Loading Data Manually

. . ... ...... [P e

Manual Program Loading (Bootstrap Loader) T

3.5.4

Automatic Program Loading

3.5.4.1

. . . . . .e

Loading Absolute Loader

3.5.4.2

e e .. 325

.. ... ....... e
e 3-26
NG 101
. . ... .. e e
ee G
1501

BASIC PROGRAMMING

CHAPTER 4

PROCESSOR INSTRUCTIONS AND OPTIONS

4.1

SCOPE

4.3

... 321

. . . .

3.5.5

4.2.3

Running Programs

. .. .. ....... p

3-29

. ... ............ . Y

INSTRUCTI
SET
ON . . . . .. . . .

e s

43
4-5

Extended InstructionSet
PROCESSOR OPTIONS

e e

e e e e

. . ... ... .......................417

. . . . . . ..

ittt

4.3.2

KE11-F Floating Instruction Set (FIS) Option

KJ11-A Stack Limit Register Option ... . ....

4.3.4

KT11-D Memory Management Option . . . . . . v v oo

4.3.5

KW11-L Line Time Clock Option

SmallPerlpheralController

SCOPE

5.2

PERIPHERALS AND OPTIONS

CHAPTER 6

EQUIPMENT MOUNTING AND POWER

6.1

SCOPE

6.2

SYSTEM MOUNTING BOX

e e 4-24

... .......... L0425
v v i 4-26

T .

J
|

e e e e e

. . . . . Pe e e

Processor Module Allocations

. e

6.2.2

Memory Module Allocatio'n‘s

e e e

Programmer’s Console Mounting

T 5-1

.. ........... e e

e e e e e e e

e e e - 6-1

e e

e e e
e

e e-

6-1

6-3

e e e e e

... . . ... .......... e

... ...

e Ce
P e
e e e
e e e e

6-3

CABINET AND SYSTEM MOUNTING
SystemCabmet

. ............ B

621

6.3.1

SYSTEM PERIPHERALS AND OPTIONS

6.3.2

. . . . ........ e

. . . . .. .. ... ... ........ e 4-27
KM11-A Maintenance Console Option . .......... ... ... . ..... . 4-29

CHAPTER 5

6.2.3

e, 4-22

. . .................. 4-23

4.3.3

6.3

o |
4-1

AddressModes . . . . ..... ... ..., ... T ...

KE11-E Extended Instruction Set (EIS) Option

4.3.7

Basic Instruction Set . A e

4.3.1

4.3.6

... . 320

LoadlngMamtenanceLoader

3.6

4.2.1

e, I

. .. .. e
e e e e e
e e e e 3-19
... .. . e e, 3-20

3.5.3

4.2.2

N |
. . ........S 3-15
. ... .. ... ... ........ e
e e e e
ee
e e e 3-15

3.4

4.2

. ................ e e e L.

3.5

3.5.2.1

6-5

" CONTENTS (Cont)
Page

6.4

POWERSYSTEM

861 Power Controller

6.4.2

H742Power Supply

. . . .

. o o

e e e

6.4.2.1

H742+15V Output

. . . . ... ... ... ... ... e

H742 Clock Output

& . . . i vt

6.4.2.3

ACLO and DC LO Circuits
H744 +5V Regulator

v o e e

e e

6-7
6-9
6-9

e e 6-10

6-10

. . . ...
..SV e 6-10

. . . . . e

H744 Regulator Circuit

6.4.3.1

e, 6-10

. . . . . . .. ..

... ... .. .... e 6-11

6.4.3.2

H744 Overcurrent Seénsing Circuit

. . . . . . . . . ...
... e e ... 6-12

6.4.3.3

H744 QOvervoltage Crowbar C1rcu1t

........................ 6-12

6.4.4

H745-15V Regulator

.. . . . . i i i

e e

6-12

6.4.4.1

H745 Regulator Circuit

6.4.4.2

H745 Overcurrent Sensing Circuit

. . . . . . . . o v v v v v ie e .. 6-12

6.4.4.3

H745 Overvoltage Crowbar Circuit

. . . . . .. . . . ... ... .. ...... 6-13

6.4.4a
6.4.5

. . . . . . . . . .

H754 +20,-5V Regulator
-

e 6-12

. . . . . . . . . . . ... .. e 6-13

861 Power Controller Interconnection

. . . . .. .. e e

e e

e e e 1 6-13

6.4.6

Power System Cable Harnesses . . . . . ...
.. ... e 6-15

6.4.7

DC Power Distribution

. . . . . e
e e e

6.4.7.1

Early Power Distribution Systems

6.4.7.2

Newer Power Distribution Systems

e e e ee

. . . ..

e e e e e e e e e 6-15

.. e e e

e e e e e 6-16

. . . . . .. e e e e e e

e e e e 6-18

CHAPTER 7

GENERAL MAINTENANCE

7.1

SCOPE . ... ... ... ... ... .... e e e i e e e e e e e 7-1
OVERALL MAINTENANCE TECHNIQUES . . . . . . . . . . it 7-1
Knowledge of Proper Hardware Operatlon . P A|

7.2
7.2.1

7.2.2

Detection and Isolation of Error Conditions

7.2.3

Means of Repamng Error Cond1t1ons

e e e e e e

e e e e

Digital
Field Service

i i

' 7.2.4

. . . . . . . o

7.3

MAINTENANCE EQUIPMENT REQUIRED

7.4

PREVENTIVE MAINTENANCE

. . . . ... e e

7.4.2

Electrical Checks and Adjustments . . . . . e

7.4.2.3

861 Power Controller

7.4.2.4

7.4.3

7.4.3.1
7.4.3.2

7-2

7-2
7-2

. . ... ....... e

Voltage Regulator Checks

e e e

7-3

e e e e e

. . .. .......... F

~ Processor Clock Ad]ustment Check

e e

Physical Checks

74.2.2

e e e e e e

e e e

e e e e e e e e e e ee

7.4.1
7.4.2.1

e e e e,

. . . .. e e P

6.4.2.2
6.4.3

. . . ... ... ... ........ e

6.4.1

7-3

. ....... e e e

e e

. . . . .P

. . .. ......... e e

7-5
7-5
7-5

AC Power Connector Receptacles
e e
e 7-5
ASR33Teletype . . . . .o P e 7-5
Preventive Maintenance Checks
. . . . ..
. e e .15
Lubrication
. . ... ... ...
........ e

7.4.4

LA30 DECwriter Preventive Maintenance

7.4.5

PCO5 High-Speed Paper-Tape Read/Punch Option

7.4.5.1

Mechanical Checks

7.4.5.2

Electrical Checks

e e

. . . . ... ... ... .. B

7-6
A

. .. ... ... .. ... .....

7-6

. . . .. . . . .. . Lo

7-6

. . . . . . .. ... .. .. e e e e e e e e e I

b |

CONTENTS (Cont)
Page

Diagnostic Program Utilization

. .. ..., . ... e

7.6

USE OF

1.7

PDP-11/40 POWER SYSTEM MAINTENANCE e

MODULE EXTENDERS

. ..., ..... e

7.7.1

Visual Inspection

71.7.2

Power System Checks . . . . . v v

e e e

e b e e e e e e e

e e e

e e e e

e e e

e e

e e e e e e 7-12

e e e

v vt e

e e 7-12

e e e e e

7-12

SUMMARY OF EQUIPMENT SPECIFICATIONS

Figure No.

Title

Page

1-1

PDP-11/40 Basic System Block Diagram

3-1a

PDP-11/40 Programmer’s Console

3-1b

. . . . .T e e e e

PDP-11/35 Programmer’sConsole

3-2

. . . . . ... ......... e

LA30-SKeyboard

. . . . .. ...

... ... ... .........

1-4

3-2

3-3

LA30Power Controls

Teletype Controls

. . . . . . . . . ..

3-5
4-1

Double and Single Operand Addressmg

4-2

Instruction Formats

. . . . ...
.. e

e e
e

e e e e
e e

e P
e

6-1

PDP-11/40 System Cabinet

6-2

PDP-11/40 Mounting Box (BA11-FC) . ... ... ...... et
Module Allocation
— KD11-A Processor, Basic and Optrons e

6-5

PDP-11/40 Power, System Block Diagram

Precision Voltage Regulator E1, Simplified Dragram

6-8

Power Control Interconnection

6-9

Regulated DC Power Distribution

4-4

6-2
e e e

. . . . . .. .. . .. ..o

e e e

6-3

6-8

A T 6-11

. . . . .. ... ... ... ... .. ... ... .. ... 6-14
. . .. ... ... .. PRI e - 6-16

6-10

Power Distribution— Early Units with System Senal No 5999 and Lower

6-11

Power Distribution Schematic — Early Systems

6-14

e e e e

e
e, 64
Module Allocation — MF11-L Memory, Basic and Optional MMll Ls .
oo
6-4
Typical Multiple Cabinet System Configuration
. . .. ... .. .. ... ... ......6-6

6-7

6-13

4-4
i

. ....... S

6-6

6-12

e 3-16

e e . 3-17

e e e e e e e e ... 323
e

3-2
3-16

v v e e e e e e e e e

. . ... ...... e e e e e e e
Flowchart of Procedure for Loadrng and Running Programs

6-4

e e e e e e

. .......... R

3-4

6-3

7-9

e 7-12

......... 6-17

(System Serial No. 5999 andlower)
. . . . . .. ... .o i it 6-19
MF11-U/UP Installation — Early Systems
. . . . . o o oo v v oo 6-20
Power Distribution — Newer Unit with System Serral No. 6000 and Hrgher
......... 6-21
Power Distribution Schematic— Newer Systems
R

(System Serial No. 6000 and Higher)

. . .. ..... e e e e e e

e e .. 6222

TABLES
Table No.

Title

I-1

Possible PDP-11/40 Variations

1-2

Applicable Documents

1-3

Drawing Set/Sheet Code Prefixes

Page

. . . . ..., ... ......... [

. . . . . .

... .

e e

. . . . . . . . . .

1-2
1-11

v v i 1-14

ya '

APPENDIX A

. . . . .e

7-7
747

7.5.2

DIAGNOSTICPROGRAMS . .. ... ............. S
©
General Description
. . . . ... u o
e

7.5
7.5.1

TABLES (Cont)

Title

Table No.
2-1

2-2

Page

Option Installation Verification
. .. ...
. ... P
L., 28
Memory Verification or Installation . .. ... ........... PR R 2-10

3-1

PDP-11/40 Console Indicators

3-2

PDP-11/40 Console Controls

. . . . . ... ... ... ...... e

e e ee

e e .

3-3

. . . ... ... .. e e e e e e e e P

3-3

LA30 Controls and Indicators

3-4

Teletype Controls

3-5

Program Identification Codes

. . . . . . e e e e e e

e e. e e e

e oow . 315

. . . . .. .. ... ......... I e e e e e e e e 3-17
. . . . . ... e

e ee

3.6

Bootstrap Loader (DEC-11-LIPA-LA)

3.7

Binary Tape Load Selection (using Absolute Loader)

3.8

Relocation of Memory Contents

3-9

PDP-11 Programming Comparison

e e

322

. .. ... .. .. ... G 15027

. ... ................327

. . . . ... ... ...... e e
. . . . . . . . . . . .

. ... ... ... .... e

e e

e e 3-28

i v vt vt v v

.. c. ... 330

4-1

ISP Symbology

e e e e s e e e e e e e e e ..

4-2
4-3

AddressModes . . . . . ... ....... e e
e[
Double Operand Instructions
. . ... ... ... ....... e
i ie ..

B |
46

4-4

- Single Operand Instructions

4-5

. . . . .. ... ... ......... e e

e ee e

4-6

4.7

Miscellaneous Instructions

. . . . . . . . .. ... ... .... T 4-15

4-8

Condition Code Operators

. . . . . . .. . . v

4-9

Extended Instruction Set (EIS)

4-10

Floating Instruction Set (FIS)

4-11

Memory Management Instruction Set

v . PR ... 416

. . ... .. e e

e e e e e

. . .. ... ... ... .. e e

e e e e e

e e 4-18

e e e e e e e e

420

. . . . . . . ee e.. 422

4-12

Location of Processor Options

4-13

KE11-E
(EIS) Specifications . . . .. .. ... ... R

4-14

KE11-F (FIS) Specifications

. . . . ... ... e e e

. . . . . .. . ...«
... e

-9

... 426

4-15

KJ11-A Specifications

. . . . .. ... ...

KT11-D Specifications

. . . . . . ... ..., e e e

4-17

KW11-L Specifications . . . ...
.e e
e
e ... 4-28
PDP-11/40 Peripherals and Options . . . . . ... ..... R 5-1
Timing Characteristics of PDP-11 NPR Devices I
e e e e e .. 65
Priority of Devices Affected by BR Latency . . . ... ... ........ e .. 6T
Maintenance Equipment Required . .. .. ... ...
.. e . Y
&

5-1

6-2
71

ee e e 4-23

4-16

6-1
\____‘//

oo I
. 428

7-2

DC Output Voltages

PDP-11/40 Diagnostic Programs . . . . . ... ... ... PO
.
PDP-11/40 Processor Preliminary Diagnostic Program Error Analysis . . e
e 7-10

- 7-5

. . .. ... .........e e e e e e e e e e e e e e e

Power System TroubleshootingGuide

. . . . ... .. ... ... ... .

Vii

7-5

. ... ... . 7-13

FOREWORD

_ThisManual describes all PDP-11/40s and those PDP-11 /35s that are mounted in a 21-inch, (as opposed to a 10-1/2 inch) box.

Text 're.fe’renc‘es that specify “PDP-11/40" also apply to the PDP-11/35. |

1
CHAPTER
INTRODUCTION

1.1 SCOPE

This manual provides a general introduction to the PDP- 11 /40 System and includes sections on installation,

operation, the instruction set, options, peripherals, equipment mounting, power, and maintenance. This overview is
‘\-—-/"!

supplemented with references to other manualsin the PDP-11/40 series for detailed explanations.

The PDP-11/40 series manuals provide the user with the theory of operation necessary to understand, operate, and

maintain the PDP-11/40 System. These manuals and the associated engineering drawings are discussedin Paragraph
1.4. Please note that the associated drawmgs are separate volumes documented by their Drawing Directory number.

“

The manuals and drawings combine to form a complete documentation package.

The level of discussion in each manual assumes that the reader is familiar with basic digital computer theory. The
maintenance philosophy presents information about normal system operation and enables the user to recognize
trouble symptoms and take necessary corrective action. Each individual manual contains theory of operation,
diagrams, and maintenance techniques. Logic drawings for the spemflc components covered are containedin separate
~

volumes

This chapter describes the basic system components (Paragraph 1.2) and provides a functional description of the'.,

overall PDP-11/40 System and each of its major components (Paragraph 1.3). The remainder of the chapter covers

applicable documents and engineering drawings (Paragraphs 1.4 and 1.5).
1.2

SYSTEM COMPONENTS

The PDP-11/40 System consists of six basic components: processor, programmer’s console, core memory,
DECwriter with associated control, power system, and mounting box. Possible variations to this basic system are
listed in Table 1-1.

Options and peripherals added to the basic PDP-11/40 System are covered in separate manuals delivered W1th the.

system. Manuals are included only for those options specifically ordered with an mdmdual system.
1.3

FUNCTIONAL DESCRIPTION

The PDP-11/40 is a 16-bit, general purpose, parallel logic, microprogrammed computer using single and double
operand instructions and 2’s complement arithmetic. The system contains a multiple word instruction processor,

which directly addresses up to 28K words of core memory. All communication among system components

(including processor, core memory, and peripherals)is performed on a single high-speed bus, the Unibus. Because of
the bus concept, all peripherals are compatible, and device-to-device transfers can be accomplished at the rate of 2.5

million words per second. All system components and peripherals are linked by the Unibus and power connectors,
and all peripherals are in the basic system address space. Therefore, all instructions applied to data in memory can

also be applied to data in peripheral device registers, enabling peripheral device registers to be manipulated by the

processor as flexibly as memory.

Subsequent paragraphs present a brief functional description of basic PDP-11/40 System components (Figure 1-1). A
functional description of all processor options is presented in Chapter 4.

1-1

Revision 1
January 1974

- Table 1-1

Possible PDP-11/40 Variations
Possible Variations

Major Component

*KD11-A Processor

No variations in basic processor. However, any of the following internal

processor options can be included:
KE11-E Extended Instruction Set (EIS)

KE11-F Floating Instruction Set (FIS)
KJ11-A Stack Limit Register
KM11-A Maintenance Console

KT11-D Memory Management

KW11-L Line Time Clock
*KY11-D Programmer’s Console

None

Core Memory

MM11-L — 8K word core memory, 900 ns cycle time, 350 ns internal
access time

- *MF11-L

— MMll -L memory plus double

system unit backplane

(space exists for two additional MM11-Ls)
MF11-LP

— Same as MF11-L with the addition of two panty bits

making it an 18-bit word memory

MEll L MMll L memory plus backplane, mountmg box, and power
supply (complete memory system)
|
‘

MM11-S

— MM11-L memory, plus backplane (may be used for'

expansion of memory above 24K)

NOTE

Memory systems compatible with the PDP-11/20 may also
be used in the PDP-11/40. However, these memories must
~

be housed in their own mounting boxes and powered by
their own power supplies. The memories are:
MM11-E

4K by 16 bit

MM11-F

4K by 16 bit

- MM11-FP

4K by 18 bit, with parity

MM11-H

1K by 16 bit

MM11-J

2K by 16 bit

'MM11-U — 16K word core memory

MF11-U - MM11-U plus double backplane (can accept one additional
MM11-U)
DECwriter

MM11-UP, MF11-UP—Same as MMI11-U and MF11-U but with
addition
of parity.

| DEwaiter

**LA30 — Standard

97-character keyboard.

keyboard available. (LA30-S

Optional

128-character

is a serial DECwriter and is controlled by a

DL11 control; LA30-P is a parallel DECwriter and is controlled by an

LC11 control )

Revision 1

January 1974

1-2

| Table 1-1 (Cont)

Possible PDP-11/40 Variations

Possible Variations

Major Cbmpo-nent

#%33 ASR

Teletype Unit

Each unit is available in 120V or 240V models.

35ASR

35 KSR

Input Terminal Control

DL11-A — Teletype, display, or LA30-S control.
DL11-B - EIA terminal control.

DL11-C — Teletype, display or LA30-S control. The DL11-C is simply a

more flexible version of the DL11-A. The DL11-C features a variable
- character code plus crystal and switch selectable baud rates.

"DL11-D — EIA terminal control. The DL11-D is simply a more flexible

version of the DL11-B. The DL11-D features a variable character code

‘plus crystal and switch selectable baud rates.

DL11-E — Datase't control.

KL1i-A )

Units differ primarily
cor
or KSR- Teletype
ASR
Leletype control.
.
in baud rates as described in KL11 manual.

LB
KL11-C \¥
KL11-E

KL11-F

LC11 — LA30-P DEeriter‘ckontrol.
Power System

*H742 PoWer Supply (may be jlumpered for either 120V or 230V,
50/60 Hz).

*H744 +5V regulator, 25A (three supplied with basic system)

*H745 - 15V regulator, 10A (one or two») |
H754 +20, - 5V regulator, used with MF11-U/UP

*861 Power Contrbller — mounted in bottom rear of cabinet. Two
- . yersions available:

861B — requires 240 Vac input

861C — requires 120 Vac input

Mounting' Box

*BA11-FC Mounting Box

*An asterisk indicates that this is the normal configuration shipped with the basic machine, unless otherwise specified by the
customer.

**Either the LA30 DECwriter or the Teletype unit may be used as the basic PDP-11/ 40‘ System input/output device.
Revision 1

1-3

January 1974

’

KD11-A

ASYNCHRONOUS

CENTRAL

LINE INTERFACE

PROCESSOR

MF11-L
CORE

MEMORY

- (8K)

DECWriter

KDN-D

PROGRAMMER'S

TELETYPE

CONSOLE

POWER SYSTEM
861 POWER ‘CONTROLLER
e

caman

c—

PRIMARY
POWER

——

'
e

——on

——

—

E———

H742
T

TGS

H745

POWER

G——

—

———

—

——

SUPPLY
——

—

-—>
Sm—

—

———

—

w—

REGULATOR (2)
11-1719

Figure 1-1

1.3.1

PDP-11/40 Basic System Block Diagram

Unibus

The Unibus provides high-speed communication between system components. With bidirectional data, address, and
control lines, the Unibus allows data transfers to occur between all units on the bus, with control of the bus an

important factor in these transfers. The fixed repertoire of bus operations is flexible enough for speed and design
economy, yet provides a fixed specification for interfaces. The asynchronous nature of these operations also eases

design and operation. The repert01re of bus operations is:
DATI, DATIP, DATO, DATOB — data operations
INTR, BR, NPR — control operations

Full 16-bit words or 8-bit bytes of information can be transferred on the bus between the master and slave. The
-

DATI, DATIP operations transfer data into the master; DATO, DATOB operations transfer data out of the master.
When a device is capable of becoming bus master and requests use of the bus, it is for one of two purposes: to make

a Direct Memory Access (DMA) transfer of data directly to or from another device or memory without processor

intervention, or to INTeRrupt (INTR) program execution and force the processor to branch to a specific address
where an interrupt service routine is located.
Bus control is obtained under a Non-Processor Request (NPR) for the DMA or under a Bus Request (BR) for an
INTR. A device can perform a DMA after acqumng bus control via a BR.

Requests for the bus can be made at any time on the BR and NPR lines. Transfer of bus control from one device to

another is made by the processor priority arbitration logic which grants control of the bus to the device having the
highest priority. NPRs are accorded higher priority than BRs. The NPRs are serviced before and immediately after

Unibus data cycles, in addition to specific times during WAIT or TRAP sequences. The BRs are serviced upon
completion of the current instruction if the requesting priority exceeds that of the processor.
Revision 1

January 1974

1-4

The PDP-11/40 proCessor has a special role in bus control operations as it performs the priority arbitration to select

the next bus master. The processor assumes bus control when no other device has control.

The Unibus originates in the processor with the Internal Unibus and Terminator module (M981), which carries the
Unibus from the processor to the next system unit. All 56 Unibus signals and 17 grounds are carried in this one
module. In addition, a 120-conductor Mylar cable may be used to connect system units in different mounting boxes
or to connect a peripheral device removed from the mounting box.

A complete description of the Unibus, including specifications, is presented in the PDP-11 Peripherals Handbook.
1.3.2

KD11-A Processor

The KD11-A Processor decodes instructions; accepts, modifies, and outputs data; performs arithmetic operations;
and controls allocation of the Unibus among external devices. The processor contains sixteen hardware registers,
eight of which are programmable. Two of the eight programmable registers are specifically used for processor
operation: a program counter (PC) and a stack pointer (SP); the remaining six serve as arithmetic accumulators,
index register, and autoincrement and autodecrement registers.

The eight non-programmable registers are used for 'storage of a variety of functions'including: intermediate address,

source and destination data, a copy of the instruction register, the last interrupt vector address, console operation
data and stack pointer for the KT11-D Memory Management Option.

Because of the flexibility of hardware reglsters, address modes, 1nstruct10n set, and DMA, PDP- 11/40 programs are

written in directly relocatable codes. The processor also includes a full complement of instructions that mampulate
byte operands and provisions for byte swapping. Either words or bytes may be displayed on the programmer’s
console.

Any of the eight programmable internal registers can be used to build last-in, first-out stacks. One register serves as a

processor (or system) stack pointer for automatic stacking. This stack-handling capability permits save and restore of

’

the program counter and status word in conjunction with subroutine calls and interrupts. This feature allows true
reentrant codes and automatic nesting of subroutines.

The Unibus serves the processor and all peripheral devices; therefore, there must be a priority structure to determine
which device becomes bus master. Generally, a device requests use of the bus for one of two reasons: to make a
non-processor transfer of data directly to or from memory, or to interrupt program execution and force the
processor to branch to an interrupt service routine. An NPR is granted by the processor at the end of bus cycles and
allows device-to-device data transfers without processor intervention. A BR is granted by the processor at the end of
an instruction and allows the device to interrupt the current processor task.

The processor recognizes four levels of hardware BRs, with each major level containing sublevels. Many devices can

be attached on each major level, with the device thatis electrically closest to the processor given priority over other
devices on the same priority level. The priority level of the processor itselfis programmable within the hardware
levels; therefore, a running program can select the priority level of permissible interrupts.

- Additional speed and power are added to the interrupt structure through the use of the PDP-11/40 fully vectored
interrupt scheme. With vectored interrupts, the device identifies itself, and a unique interrupt service routine is
automatically selected by the processor. This eliminates device polling and permits nesting of device service routines.

The device interrupt priority and service routine priority are independent to allow dynamic ad]ustment of system

behaviorin response to real-time conditions.

The Un1bus addresses generated by the KD11-A Processor are 18-bit direct byte addresses, even though the
PDP-11/40 word length and operational logic is all 16-bit word length. Thus, while the PDP-11/40 word can only
contain address references up to 32K words (64K bytes), the KD11-A Processor can reference addresses up to 128K
words (256K bytes).
1-5

In addition to the word length constraint on basic addressing space, the uppermost 4K words of address space are
reserved for peripheral control, status, and data registers. In the basic PDP-11/40 configuration (without memory
management), all address references to the uppermost 4K words of 16-bit address space (160000—177777) are
converted to full 18-bit references with bits 16 and 17 always set to 1. Thus, a 16-bit reference to address 1732244
is automatically converted to a full 18-bit I/O device register address of 7732245. Consequently, the basic

PDP-11/40 configuration can address up to 28K words of core memory and 4K words of I/O device registers. If core

memory is increased beyond 28K words, the KT11-D Memory Management Option must be installed. A brief
description of the KT11-D Memory Management Optlonis providedin Chapter 4

A detailed description of the KD11-A Processor is contained in the KDII -A’ Processor Mamz‘enance Manual,
EK-KD11A-MM-001.

1.3.3

KY11-D Programmer’s Console

The KY11-D Programmer’s Console provides the programmer with a direct system interface. The console allows the
user to start, stop, load, modify, examine, step, or continue a program. Console dlsplays indicate processor operation

and the contents of the address and data registers. The console is mounted as the front panel of the BA11- FC
Mounting Box andis connected to the processor by two cables.

The programmer’s console interacts with the processor through a microprogram control located
in the processor.

The console contains only indicators (light emitting diodes), switches, and the contact bounce filtering circuits for
the control switches. Console operation does require certain Unibus operations through the ’processor DATO for
DEP and DATI for EXAM. For single-step operation, the processor responds to a Console Bus Request (CBR) whose
priority supersedes all other BR priorities. Note that use of the KMi1 Mamtenance Console opt10n prov1des a
further display of machme states, and allows single mlcroword stepplng |
"

Console operation, including descriptions of all controls and indicators, is _presented in Chapter 3. Detailed descriptions of console logic circuits are contained in the KD11-A Processor Maintenance Manual, EK-KD11A-MM-001.

1.3.4 MF11-L Core Memory
The PDP-11/40 contains an MF11-L Core Memory. The MF11-L consists of a three-module, 8K, '16-bit word,
MM11-L memory mounted on a double system unit backplane. The backplane has nine slots of mounting space,
hence two additional MM11-L memories may be mounted on the backplane as options. With two additional MM11-L

memories installed, the memory size is increased to a total of 24K. A detailed description of the memory is
contained in the MM11-S, MF11-L, and MF11-LP Core

Memory System, EK-MM11S-TM-003.

NOTE

PDP-11/40

memory

non-overlapped

powered

situations.

for

non-interleaved

Successive

and

continuous

operations to alternate 8K memory segments is considéred-_afl

prohibited overlapped situation. Interleaving is not allowed

within the MF11-L or MM11-S powered by the basic box.

)

The core memory uses the Unibus for data transfers to and from the processor and other devices. The core memory,
however, is never bus master; therefore, DATO or DATOB indicates information transferred out of the master into
the memory. Because of the Unibus strueture, the memory can be directly addressed by the processor or any other
master device. Because of double operand instructions, every location in core can functlon as a true arlthmetlc

accumulator,

The memory does not enter the priority structure because it is always a slave device. The master device, however,
can request use of the Unibus and thus the memory through either a BR or a NPR Because the memory is

completely independent of the processor, any master device can perform dnect data transfers W1th memory without
processor intervention.

1-6

NOTE

The instruction timing specified for the PDP- 11/40 applies
only

for

the memories

mounted within the

computer

mounting box. These memories employ a special MSYN A

signal between the processor and the memory.

1.3.5

Optional Memory Systems

Memories with different ranges of speeds and various physical and electrical charactenstlcs can be freely mixed and
interchanged in a single PDP-11/40 System. The basic system mounting box can house up to 80K of memory in
addition to the processor and processor options. Additional memory units may be added by using separate mounting
boxes and power supplies up to a total of 124K. Note that the KT11-D Memory Management Optionis requ1red if
core memory is increased beyond 28K,

Generally, memory systems compatible with the PDP-11/40 fall into two categories: memories designed for use
with the PDP-11/40 and memories designed for use with the PDP-11/20. The PDP-11/40 memories are: MM11-L,
MF11-L, MF11-LP, ME11- L, and MM11-S. The PDP-11/20 memories are: MM11-E, MM11-F, MM11-FP, MM11-H,
and MM11-J.

1.3.5.1 PDP-11/40 Memories — The following paragraphs provide brief descriptions of the MM11-L, MF11-LP,
ME11-L, and MM11-S memories (the MF11-L memory was described in Paragraph 1.3.4). For detailed descriptions
of the MM11-L, MF11-LP, and MM11-S memories, refer to the MM11-S, MF11-L, and MFI1I1-LP Core Memory
System, EK-MM11S-TM-003. For a detailed description of the ME11-L memory, refer to the ME'11-L Core Memory

System Manual, DEC-11-HMELA-B-D.

1.3.5.1.1 MMI11-L Core Memory— The MM11-L Core Memory is a read/write, random access, coincident current,
magnetic core type memory with a cycle time of 900 ns and Unibus access time of 400 ns. The memory is organized
in a 3D, 3-wire planar configuration. It provides 8192 (8K) 16-bit words that are both word and byte addressable.
The memory is orgamzed into 16-bit words, each word containing two 8-bit bytes. The bytes are identified as the

low-order byte (bits 07—00) and the high-order byte (bits 15—08). Each byte is addressable and has its own address
location. Low bytes are always even numbered and high bytes are odd numbered. Full words are addressed at
even-numbered locations only. When a full word is addressed, the high byte is automatically included. For example,
the 8K memory has 8,192 words or 16,384 bytes; therefore, 16,384 locations are assigned. Address 000000 is the

first low byte, address 000001 is the first high byte, 000002 is the second low byte, 000003 is the second high byte,

etc.

The MM11-L consists of three modules: a2 G110 Hex module containing the memory control logic and data
channels; awex module containing the memory driver logic; and an H214 Quad module containing the
memory core stack.

The memory control logic acknowledges the request of the master device, determines which of the four basic
operations (DATI, DATIP, DATO, or DATOB) is to be performed, and sets up appropriate timing and control
circuits to perform the desired read or write operation. It also contains the inhibit drivers and sense amplifiers as well
as device selector logic to determine if the memory bank has been addressed from the Unibus. The control logic
includes a 16-bit flip-flop storage register. During DATI operations, this register stores the contents of the memory

location being read (destructive read) so that the data can be written back into memory (restored). The register is
also used during DATO and DATOB cycles to store incoming data from the Unibus lines so that it can be written

into core memory.

The memory driver logic includes: address selection logic that decodes the incoming address to determine the core
specifically addressed; the switches and drivers that direct current flow through the magnetic cores to ensure the

proper polarity for the desired function; and the X and Y current generators that provide the necessary current to
change the state of the magnetic cores.
1-7

The ferrite core memory stack consists of 16 memory mats arranged in a planar configuration. Each mat contains
8192 ferrite cores arranged in a 128 X 64 matrix. Each mat represents a single bit position of a word. Each ferrite
core can assume a stable magnetic state corresponding to either a binary 1 or binary 0. Even if power is removed
from the core, the core retains its state until changed by appropriate control signals.

1.35.1.2 MFI1I-LP Core Memory — The MF11-LP is an 8K, 18-bit word memory consisting of four modules
mounted on a double system unit backplane. Three modules perform identical functions as those in the MM11-L
memory while the fourth module contains parity control circuitry. The two additional bits (bits 16 and 17) provide
parity bits for the low and high bytes of the data word respectively. The MF11-LP may be expanded to 24K

capacity by installing two additional 8K segments (three modules each) on the double system unit backplane.

Note that while the 8K MF11-LP memory contains four modules, the 24K unit only requires 9 module slots (one
double system unit). This is possible because only one parity controller module is needed for 24K. The parity
controller module is a dual-height module and is installed in the two normally vacant slot/sections next to the

1.3.5.1.3 MEII-L Core Memory
— The ME11-L is a complete memory system con31st1ng of an MM11-L Core
Memory and associated backplane housed in its own mounting box which contains an integral power supply. This

power supply and mounting box can accommodate up to three MM11-L Core Memories. In effect, the ME11-L can
be expanded up to 24K in 8K increments. These memories should not be mterleaved due to power supply
limitations.

The system mounting box is 5-1/4 in. high, 19 in. wide, and 20 in. deep and is designed for mounting in a standard
19-in. cabinet. Rack-mountable slides are included but the box can be used as a stand-alone unit, if desired. In

addition to holding the core memory, backplane, and power supply, the box contains all cables necessary for
providing power and for interfacing the units of the ME11-L. It also provides for connection to the Unibus. The rear

of the box contains cable clamps, a line cord for input power, a cooling fan for the memory modules and power
supply, and a power control circuit breaker.
The memory system power supply converts single-phase 115 or 230 Vac line voltage to the two regulated dc voltages

required by the memory system: +5V for the logic and -15V for the core memory. Both outputs are overvoltage

and overcurrent protected. The power supply also provides line power to the mounting box cooling fan and the BUS
AC LO and BUSDC LO signals which are sent to the Unibus in the event of a power failure.

The power supply consists of a power control, a power chassis assembly, and a dc regulator along with associated ac
and dc cables. The power control contains a thermal circuit breaker which protects against input and overload andis
reset by depressing a button on the rear of the mounting box. A thermostat in the regulator opens one side of the

primary circuit and deenergizes the power supply if the temperature rises above 100° C. It is automatically reset
when the temperature reaches 63° C.

1.3.5.1.4 MMII-S Core Memory— The MM11-S Core Memory is an MM11-L. memory on a single system unit
backplane. The prime physical difference between the MM11-S and the MF11-L is that the MM11-S is an 8K single
system unit while the MF11-L is a 24K capacity double system unit. The MM11-S should not be interleavedin the
PDP-11/40.

1.3.5.2 PDP-11 /20 Memories — Brief descriptions of the PDP-11/20 memories are provided below. These memories
may be used with the PDP-11/40 System provided they are powered by H720 Power Supplies and are mounted in a
BA11-ES Mounting Box. The MMI11-E and MM11-F memories are expandable to 28K with interleaving of 4K
segments permitted.
MMI11-E — 4K by 16 bit, 1.2 us access time

‘

MM11-F
— 4K by 16 bit, 950 ns access time
MM11-FP — an MM11-F with parity option included

MM11-H — 1K by 16 bit, 950 ns access time
MM11-J — 2K by 16 bit, 950 ns access time

1-8

~—_

memory stack module.

1.3.5.3 MFI11-U/UP Core Memory The MFll U/UP Memory is a read/wrlte random access comcrdent current

magnetic core type with a maximum cycle time of 980 ns and a maximum access time of 425 ns. ltis organizedin a
3D, 3-wire planar configuratlon Word lengthis 16 bits and the memory consists of 16 384 (16K) words

The MF11- U provrdes 16 384 (16K) 16-bit words the MF 11 UP provrdes the same number of words but mcludes |
S

parity.

The memory can be interleaved in 32K increments for faster operatron Interleavmg causes consecutlve bus addresses
-

to be located within alternate 16K memory blocks

The chart below shows the variousoption desc,ription's 'a,sso.Ciated with the 16K memory.
M8293 16K Unibus Timing Module
G114 Sense Inhibit Module
G235 X-Y Driver .

I
|

- MF11-U
-

'H217D Stack Module (16 blts)
7009295 Backplane Assembly

Includes all modules hsted in MFll U but does not include backplanef

MM11-U Module Set
|

MF11-UP

assembly

M8293 16K Unibus Timing Module

‘G114 Sense Inhibit Module
G235 X-Y Driver Module

“H217C Stack Module (18 bits 1nclud1ng panty)
7009295 Backplane Assembly
M7259 Parlty Control Module

MM1 I'UP Module Set '_
|

| Includes all modules hsted in MFll UP except M7259 Parlty Control' . o
|

| Module and does not 1nc1ude backplane assembly

If a user has a 16K memory system and wishes to add another 16K, he merely specrfies the approprlate module set
.

since the ex1st1ng backplane assembly can hold 32K of memory

The MFI 1-U/UP Core Memory is explamed in detallin the MF1 I U/ Up Core Memory System Mamtenance Manual-

DEC-11-HMFMA-CD.

- 1.3.6 LA3O DECwriter

The LABO DECwriter is a dot matrix 1mpact pnnter and keyboard for use as a hard copy I/O termmal Itis capable.
of printing a set of 64 ASCII characters at speeds up to 30 characters per second on asprocket'fed 9 7/8 in.
|
contmuous form. Data entry is from a keyboard capable of generating either 97 or 128 characters

The LA30 is avarlable in two versions: parallel (LA30-P) and serial (LA3O S). The serial version is normally used

with the PDP-11/40 System in that it is interfaced to the Umbus via the DL11 Asynchronous Line Interface The
DL11 is basrc to the PDP- 11/40 System

The LA30 DECwriter is covered in Chapter 3 and a detarled descnptlon is contamed in the LA30 DEerzter

Mamtenance Manual, DEC-00- LA30-DD .

1.3.7

DLI11 Asynchronous Line Interface

The DL11 Asynchronous Line Interface prov1cles an 1nterface between a communrcatrons devree such as a serral

LA30 DECwriter or Teletype, and the PDP-11/40 Unibus. Serial information read or written by the device is

assembled or disassembled by the control for parallel transfer to or from the Unibus. The control also formats the
data from the Unibus so that it is in the format required by the device. The interface provides the flags that initiate

these data transfers and cause a priority interrupt to indicate the availability of the device.

The DLll ‘transfers data via processor DATI ‘and DATOB bus cycles. Although a DATO can be used, normal

operation consists of a DATOB transfer because the device and the interface handle byte rather than word data. The

interface can acquire bus control through a BR and is normally set at the BR4 prrorrty level. Because the DL11

interface operates through an interrupt, no NPR hardware exists.

Five available DL11 interface options (DL11-A through DLI1 l-E) provide the flexibility needed to handle a variety

of terminals. For example, the user can select an option for interfacing a Tele'type or display keyboard, for handling
EIA data, or for handling dataset devices. In addition, dependrng on the optron used the user has a choice of line
speeds, character size, stop-code length, and parrty

The DL11 consists of a single quad module, which is normally installed in the processor Small Peripheral Controller
(SPC) slot. This module contains address selection logic for decoding the incoming bus address, an interrupt control
for generating the interrupt, and receiver/transmitter logic that performs the“conversion and formatting functions.

A detailed description of the DL11 1nterface is presented in the DL] ] Asynchronous Line Interface Manual,
EK-DL11-TM-002.

1.3.8 Power System
NOTE

Two different power distribution systems are used in the
PDP-11/40; both are described in detail in Chapter 6 This
manual refers to these systems as early or older and recent or

newer models. This note applres to both CPU and expansion boxes and cabinets.

The new power distribution is mcorporated 1n PDP11/40’ "
systems with serial number 6000 and greater

The PDP-11/40 power system consists of an 861 Power Controller an H742 Power Supply, three H744 +5V
Regulators, two H745
- 15V Regulators, and interconnection and power d1str1but1on cabllng One H754 +20,-5 Vdc
regulator may replace an H745 if the MFllU/UP Memoryis rnstalled

The 861 Power Controller controls all ac power 1nput to the system cabrnet The controller is equlpped with a

circuit breaker for overload protection and a thermostat for excessive heat protection. ‘Thepower controller provides
switched ac outputs (controlled) and unswitched ac outputs (uncontrolled) whrch prov1de power for the entrre
system cabinet and related peripherals.

The H742 Power Supply takes ac input power from the 861 Power Controller generates and distributes dc power
and control signals to the system, and provides ac power to the logic cooling fan and H744 and H745 regulators.

There are three control signals generated: a clock signal, a DC LO logie signal, and an AC LO logic signal. The clock
signal drives the processor real-time clock option (KW11-L or KW11-P) if it is installed. The AC LO and DC LO
signals warn the processor of imminent power failure, allowing the processor time to perform a power-fail sequence.

The H744 and H745 regulators generate +5V and - 15V outputs, respectively, which are distributed to the KD11-A

Processor and MF11-L Memory backplanes and the KY'1 l-D console.

Expansion cabinets are 31mllar to the PDP-11/40 cabinet, but can accept two H754 +20,-5V regulatorsin place of
the two H745- 15V regulators, if required by the MF11 -U complement.

1.4 APPLICABLE DOCUMENTATION

PDP-11 documents related to the PDP-11/40 System are listed in Table 1-2 in two main categories: general

handbooks and PDP-11/40 hardware manuals. Hardware manuals cover equipment specifically related to the
PDP-11/40 and have associated engineering drawings. General handbooks cover overall PDP-11 system descriptions,
instruction set, addressing modes, basic logic modules, Unibus description, and interfacing information. Also covered
is general software documentation for basic programs necessary to develop, load, and run programs. Both the
PDP-11/40 hardware manuals and the general PDP-11 handbooks must be used together for a complete
understanding of PDP-11/40 Systems.

‘Table 1-2

Applicable Documents

Title

Associated

Description

Drawing Set

PDP-11/40 Processor
Handbook DEC, 1972

N/A

’

A general PDP-11/40 System handbook covering
system architecture, addressing modes, the instruction set, programming techniques, memory man-

agement, internal processor options, console operation, and system specifications.

A general peripheral interface handbook. The first

N/A

PDP-11 Peripherals

part is devoted to a discussion of the various

Handbook

peripherals used with PDP-11 Systems. The second
part provides detailed theory, flow, and logic
descriptions of the Unibus and external device
logic; methods of interface construction; and
~ examples of typical interfaces.

Logic Handbook
|
DEC, 1972
|

o
"

produced by DEC but not used with the PDP-11).

N/A

PDP-11 Paper-Tape

Software Programming
|
Handbook,
XPTSA-A-D

Presents functions and specifications of the MSeries logic modules and accessories used in
PDP-11 interfacing (includes other types of logic

N/A

Detailed discussion of the PDP-11 software system

.
|

used to load, dump, edit, assemble, and debug
PDP-11 programs; input/output programming; and
the floating point and math package.

Table 1-2 (Cont)
N

Applicable Documents
Description

Associated

Title

Drawing Set

PDP-11/40,-11/35

PDP-11/40 System

A general introduction to the basic PDP-11/40

(21 inch Chassis)

System including sections on installation, oper-

System Manual

ation,

EK-11040-TM-002

detailed information, including maintenance, of

and

the

instruction

set.

Also provides

the system power supply.

KD11-A Processot

PDP-11/40 System

Block diagram discussion, flow diagram discussion,

Maintenance Manual,

~theory

EK-KD11A-MM-001

"KD11-A
Console,

of operation,

and maintenance

Processor,
KJ11

KYI11-D

Stack

Limit

for the

Programmer’s"

Option,

KW11-L Line Frequency Clock Option, and KM11

Maintenance Module Option.

PDP-11/40 System

MM11-S, MF11-L, MF11-LP

General

description,

Core Memory System,

maintenance

the

EK-MM11S-TM-003

MM11-S memories.

detailed

description,

and

MF11-L,

MF11-LP,

and

(Note

that MF11-L is the

memory system; MMII-L the basic core memory.)
The MF11-L consists of a MM11-L Core Memory

Contains a detailed description and maintenance

MF11-U/UP

MF11-U/UP Core Memory

System Maintenance Man-

information for the MF11-U and -UP Memory

ual, DEC-11-HMFMA-C-D

Systems. MF11-UP is a parity memory.

KE11-E and KE11-F Instruc-

KE11-E Extended

Algorithms,

tion Set Option Manual,

Instruction Set

operation, and maintenance for the KE11-E Ex-

EK-KE11E-TM-002
-

data

programming,

theory =

(EIS) Option and

tended

KE11-F Floating

KE11-F Floating Instruction Set (FIS) Option.

Instruction

Set

(EIS)

Option and

of
the

Instruction Set

(FIS) Option

KT11-D Memory Managé-’

KT11-D Memory

‘ment Option Manual,

Management

Operation, programming, and detailed theory of

EK-KT11D-TM-002
DLI11 Asynchronous Line

operation for the KT11-D Memory Management

Option.

PDP-11/40 System

Interface Manual,

installation

configuration,

programming,

and

theory of operation of the DL11 interface. Covers

EK-DL11-TM-002

DL11-A through DL11-E. The DL11-A or C is

normally used as a control for the Teletype or the
LA30-S DECwriter but the DL11 can be used for a
variety of communications devices. The DL11-C is

simply a more flexible version of the DL11-A in
that the DL11-C features a variable character code

plus crystal and switch selectable baud rates.
861-A, B, C Power Controller Maintenance Manual,

- DEC-00-H861A-A-D

| N/A

Installation, theory of operation, and maintenance

of the 861-A, B and C Power Controllers.

a\\..'//, '

on a double system unit backplane.

‘Table 1-2 (Cont)
Applicable Documents

Title

»LA3O DECwriter Manual,
DEC-00-LA30-DD

Associated

Description

DEC-00-LA30-DA

Presents a detailed discussion of the DECwriter

Drawing Set

including installation, operation, principles of
operation, maintenance, troubleshooting, and engineering drawings.

~ Provides general and detailed descriptions, programming, and operation for the LC11 DECwriter

DEC-11-HLCB-D

LC11 DECwriter System
Manual, DEC-11-HLCB-D

interface. The LC11 is used when an LA30-P
(parallel) DECwriter is used as a system input/
output device.

DEC-11-HR4C-D

KL11 Teletype Control

Manual, DEC-11-HR4C-D
-

Automatic Send-Receive
Sets, Manual
-

Model 33 Page
Printer Set, Parts
|

Provides general and detailed descriptions, programming, adjustments, and maintenance for the

KL11 Teletype Control that may be used instead
of the DL11 control.

Bulletin 273B,
two volumes,
Teletype Corp.

Bulletin 1184B,
Teletype Corp.
|

Describes operation and maintenance of the Model
33 ASR Teletype unit that can be used as an
input/output device with the PDP-11/40 System.

Comparable manuals available for other Teletype
|
~models.

Contains an illustrated parts breakdown to serve as
a guide for disassembly, reassembly, and parts
ordering for the Model 33 ASR Teletype unit.

Comparable manuals available for other Teletype

models.

1.5

ENGINEERING DRAWINGS

A complete set of engineering drawings and module circuit schematics is provided with each PDP-11/40 System.
These print sets are listed in Table 1-2 either under a Drawing Directory reference or as a second volume to the
maintenance manual. The engineering drawings support manual discussions and are often directly described therein.
The Drawing Director Index (DDI) provides a list of prints included in the set and includes drawing number, title,
and revision. An X in the column labeled CUSTOMER PRINT SET indicates each drawing that is provided for the
customer. The 1972 DEC Logic Handbook contains general logic symbols used on DEC drawings. A more detailed

discussion of drawing set conventions is contained in the KDI 1-A Processor Maintenance Manual,

EK-KD11A-MM-001 with this convention directly applicable to the PDP-11/40 processor and processor options.
All DEC drawings are identified with a drawing identification code shown below:

Original print size —
Drawing type

CS-M7233-0-1

Series
| l L— Manufacturing
variation

Module type, equipment type, or a
7-digit DEC part number.

Drawing Type Designations

CS:
BS:

BD:

Circuit schematic

AD:

Block schematic

UA:

Unit assembly

Block diagram

WL:

Wire list

FD:

Flow diagram

PL:

DD:

Drawing directory

AL:

MU:

Module utilization

Assembly drawing

Parts list

Accessory list

In addition to the basic drawing identification code, a drawing set/sheet code
is also used to identify logic drawings.
This code is written in the title block and consists of three characters: two letters identify the equipment drawing

set; and a number identifies the sheet in that drawing set. For example, KT-3 indicates sheet 3 of the KT11-D

Memory Management Option drawing set.

Because of its multiple module configuration, the processor drawing set/sheet code is a little different. Only one
letter, the letter K, is used in the processor code along with two numbers. The first number indicates the module,

and the second number indicates the sheet. For example, K2-4 indicates sheet 4 of the processor UWORD Module
Drawing set. See Table 1-3 for a complete listing of drawmg set/sheet code prefixes.

‘Table 1-3

Drawing Set/Sheet Code Prefixes:

Drawing Set

KD11-A Processor Modules:

DATA PATHS

Code Prefixes

M721t

M7232

UWORD
IRDECODE

Module Number

|
=

M7234

STATUS

M7235

KM11-A Maintenance Board

KY11-D Console

WI30,W131

xvp

M7800

KT11-D Memory Management

- M7236

KE11-E Expanded Instruction Set

- M7238
|

M7239

114

- K5

M7237

DLll Asynchronous Line Interface

KE11-F Floating Instruction Set

K2
K3

M7233

TIMING

KJ11-A Stack Limit Register

KE
KF

CHAPTER
2
INSTALLATION

2.1

SCOPE

This chapter provides information on PDP-11/40 System site preparation, equ1pment installation, operation and
programming, and customer acceptance. Only installation of the basic PDP- 11/40 System and processor options is
included in this chapter. A section on installation of peripheralsis not provided because of the modular and Unibus
concepts of the system. To install a peripheral, for example, it is usually only necessary to insert the interface
module(s) into the basic system mounting box and connect appropriate cabling between the interface and the
peripheral, Installation and maintenance of the peripheral itself is covered in associated manuals.

2.2

SITE PREPARATION

It is recommended that sufficient time be given to site planning and preparation with particular attention given to

the user’s specific system configuration especially if a large number of peripherals are part of the system.

Two DEC documents will aid in proper site plannrng the PDP-11/10, 40 Confrgura’uon Worksheet and the PDP-11
Site Preparation Worksheet.

The Configuration,Worksheet permits the user to lay out the system prior to ordering so that he is aware of drawer

~ layout, cabinet layout, and Unibus interconnection. This ensures that the proper number of drawers and cabinets are
used and that Unibus length and loading is proper for the system.

The Site Preparation Worksheet permits the user to determine the power requirements, environmental preparations,

and physical arrangement of his system. The worksheet provides data on operating environment, power

~ requirements, service and access requirements, and physical specifications for the basic system and available
peripherals.

A final layout plan should be approved jointly by the user and DEC prior to delivery of equipment It is

recommended that any modifications to the mstallatron site be effected prior to shrpment and installation of the
system.

DEC Sales Engrneers and Field Service Engineers are available for consultation and planning regarding objectives,

course of action, and progress of the installation. Itis recommended that a qualified DEC representative either install
the system, or at least be present during installation.

Adequate site planning and preparation can greatly simplify the installation process, resulting in a more efficient and

reliable installation. Information in the following paragraphs is provided primarily to permit review of the site
planning,.

2-1

2.2.1

Physical Dimensions

The overall dimensions and total weight of the particular PDP-11/40 as well as dimensions, weights, and cable

lengths of any optional cabinets and free-standing peripherals should be known prior to shipment of the equipment.

The route the equipment is to travel from the customer receiving area to the installation site should be studied.
Measurements of doors, passageways, etc., should be taken and submitted along with floor plans to the DEC Sales

Engineers and Field Service to ensure that the equipment is packed to suit the installation site facilities. Any
restrictions (such as bends or obstructions in hallways, etc.) should be reported to DEC.

Secondly, elevator limitations should be determined. If an elevator is to be used for transferring the PDP-11/40 and
its related equipment to the installation site, DEC should be notified of the size and gross weight limitations so that

the equipment can be packed accordingly.
Thirdly, system operational requirements should be considered. Operational requirements determine the specific
location of the various options and free-standing peripherals of the system. Dimensions, weights, and cable lengths of

free-standing perrpheral equipment must be determined prior to installation, preferably during site preparation and
planning. Note that peripheral cables must not exceed maximum specified lengths. Operational requirements that
should be considered are listed below:
a.

Ease of observation of input/output devices by operating personnel.

Adequate work area for installing tapes, access to console, etc.

Space availability for contemplated future expansion.

Proximity of the cabinets to peripherals.

Proximity of cabinets and peripherals to any humidity controlling or air conditioning equipment.

Finally, site space requirements should be determined by the specific system configuration to be installed and, when

applicable, provision for future expansion. To determine the exact area required for a specific configuration, a
machine-room floor plan layout can be helpful. When applicable, space should be providedin the machine room for

storage of tape reels, printer forms, card files, etc. The integration of the work area with storage area can be
considered in relation to the work flow requirements between areas. In large installations where test equipment is

maintained, DEC recommends that the test equipment storage area be within or adjacent to the machine room.
2.2.2

Fire and Safety Precautions

The following fire and safety precautions are presented as an aid to providing an installation that affords adequate

operational safeguards for pe‘rsonnel and system components.

If an overhead sprinkler system is used, ‘a “dry pipe” system is recommended. This type of system, upon

detection of a fire, removes source power to the room and then opens a master valve to fill the room’s

overhead sprinklers.

If the fire detection system is the type that shuts off the power to the 1nsta11at10n a battery-operated

~
c.

emergency light source should be provided.
If an automatic carbon dioxide fire protection system is used an alarm should sound prror to release of
the CO, to warn personnel within the installation.

If power connections are made beneath the floor of a raised-floor installation, waterproof electrical
receptacles and connections should be used.

An adequate earth ground connection should be provided for the protection of operating personnel.

2-2

2.2.3

Environmental Requirements

has an air distribution system that provides cool, well-filtered, humidified air.
An ideal computer room environment
The room air pressure should be Kept higher than that of adjacent areas to prevent dust infiltration.

2.2.3.1 Humidity and Temperature — The PDP-11/40 electronics are designed to operate in a temperature range of

from 50°F (10°C) to 122°F (50°C) at a relative humidity of 20 to 95 percent without condensation. However,
typical system configurations that use I/O devices such as magnetrc tape units, card readers, etc., require an

operational temperature range of from 60°F (15°C) to 80°F (27°C) with 40 to 60 percent relative humidity.

Nominal operating conditions for a typrcal system configuration are a temperature of 70°F (20 C) and a relative

humidity of 45 percent.

2.2.3.2 Air Conditioning— When used, computer room air-conditioning equipment ‘should' conform to the

requirements of the “Standard for the Installation of Air Conditioning and Ventilating Systems (non-residential)”,
N.F.P.A Number 90A; as well as the requirements of the “Standard for Electronic Computer Systems”’, N.F.P. A.
Number 75.

2.2.3.3 Acoustical Damping— Some peripheral devices (such as line printers and magnetic tape transports) are

quite noisy. In installations that use a group of high noise level devices, an acoustrcally damped ceiling reduces the
noise. Operator comfort and efficiencyis a major concern here.

— If cathode-ray tube (CRT) peripheral devices are part of the system, the illumination
2.2.3.4 Lighting
surrounding these peripherals should be reduced to increase the visibility of the display.

2.2.3.5 Special Mounting Conditions — If the PDP-11/40 is to be subjected to rolling, pitching, or vibration of the
mounting surface (e.g., aboard a ship), the cabinets should be securely anchored to the installation floor by
mounting bolts. Since such installations require modifications to the system cabmets DEC must be notified upon
placement of the order so that necessary modifications can be made.

2.2.3.6 Static Electricity — Static electricity can be an annoyance to personnel and can, in extreme cases, affect the

operational characteristics of the PDP-11/40 System and related peripherals. If carpeting is installed on the

installation room floor, it should be of a type designed to minimize static electricity. Flooring consisting of metal
panels, or flooring with metal edges, should be adequately grounded..
2.2.4

Electrical Requirements

The PDP-11/40 can be operated from a nominal 115 or 230 Vac, 50/60 Hz power source. Line voltage should be
maintained within 10 percent of the nominal value and the 50/60 Hz line frequency should not vary more than 3
Hz. A PDP-11/40 System with 16K of memory and standard perrpherals requires approxrmately 690W of mput
power (6A @ 115 Vac, 3A @ 230 Vac).

Primary power to the system should be provided on a line separate from lighting, air-condrtlonmg, etc., sO that
computer operation is not affected by voltage surges or fluctuations.

The PDP-11/40 cabinet grounding point should be connected to the building power transformer ground or to the

building ground point. Any questions regarding power requirements and installation wiring should be directed to the
DEC Sales Engineer or Field Service Engineer.

Primary power outlets at the installation site must be compatible with the PDP-11/40 primary input connectors. The
input connectors provide power directly to the cabinet-mounted 861 Power Controller (one per cabinet) and each
model of the power controller uses a specific type of connector. Power controller models 861-B and 861-C are used
in the PDP-11/40 System cabinets. Refer to Figure 2-1 in the 861-A4, B, C Power Controller Maintenance Manual,
DEC-00-H861-A-A-D for complete connector information.

2-3

2.3

INSTALLATION PROCEDURES

The procedures presented in the following paragraphs are prov1ded to assist in unpacklng, 1nspect1ng and rnstalhng
the PDP-11/40 System and assocrated processor options.
|

CAUTI()N

Do not attempt to install the system until DEC has been
notified and a DEC Field Service Representativeis present.

2.3.1

Unpacking

Before unpackrng the equrpment check the shrpment against the packrng list.. Ensure that the correct number of
packages has been delivered and that each package contains all the items listed on the accompanying packing slip.
Also, make certain that all items on the accessories list in the Customer Acceptance Procedures have been included
in the shipment. Unpack the cabinets as describedin the followrng procedure

Remove outer shipping container. |

NOTE

The container may be either heavy corrugated cardboard or
plywood. In either case, remove all metal straps first, then
remove any fasteners and cleats securing the container to the

skid. If applicable, remove wood frammg and supports from
around the cabinet perimeter.

Remove the polyethylene cover from the cabinets.

Remove the tape or plastic shipping pins, as applicable from the cabinet(s) rear access door(s).

Unbolt cabinet(s) from the shrppmg skid. The bolts are located on the lower supportrng siderails, and are
exposed by openrng the access door(s) Remove the bolts.

5. Raise the leveling fe"et above the level of -the roll-around casters.'
6.

Use wood blocks and planks to form a ramp from the skid to the floor and carefully roll the cabinet

onto the floor.

Roll the system to the proper location forlnstallation.‘ o

If applicable repeat steps 1. through 7. fo‘r theexpansion cabinets.

| When the cabinets are orrented properly, follow the procedures in Paragraphs 2.3.2 and 2.3.3 to install
the cab1net(s)

2.3.2

Inspection

After removing the equrpment packrng material, 1nspect the equrpment and report any damage to the local DEC

sales office Inspect as follows:
1.

Inspect external surfaces of the cabmets and related equipments for surface bezel, swrtch and light
damage etc.

Remove the sh1pp1ng bolts from the rear door then open the rear door of the cabinet. Internally inspect
the cabinet for console, processor, and mterconnectmg cable damage; also inspect for loose mountmg

rails, loose or broken modules, blower or fan damage, any loose nuts, bolts, SCIEews, etc.

Inspect the wiring side of the logrc panels for bent pins, broken wrres loose external components and
| forergn materral

Inspect the power supply for properseating'of fuses and power conneCtions.

Inspect all peripheral equipment for internal and external damage. This 1ncludes mspectron of magnetic |
tape and DECtape transport heads, motors, paper-tape sprockets etc.
CAUTION

Do not operate any perlpheral device which employs motors

tape heads, sprockets, etc., if they appear to have been
damaged
in shipment.

2.3.3 vCabmet Installation
The PDP-11/40 cabinets are provided wrth roll-around casters and ad]ustable leveling feet. It is not necessary to bolt
the cabinet to the mounting floor unless condltrons indicate otherwise (e. g shrpboard installation). Cabinet
installation procedures follow.

|
-

NOTE

In multiple cabinet installation, receiving restrictions may
necessitate shipping cabinets individually or in pairs. In such
cases, the cabinets are connected at the installation site.

With the cabinets positioned in the room, install H952-GA Filler Strips between cabinet groups (filler
strips are shipped attached to the end of a cabinet group) Remove 4 bolts each from the front and rear
filler strips. Butt the cabinet groups together while holding the filler strips in place and rebolt through
both cabmets and the filler strrps Do not tighten the bolts securely at thrs time.

‘Lower the leveling feet $0 that the cabrnet(s) are not restmg on the roll around casters but are supported
on the leveling feet.

Use a sprrrt level to level all cabmets and ensure that all levelrng feet are firm agamst the floor.

Tighten the bolts that secure the cabinet groups together and then recheck the cabinet levehng Again
ensure thatall levelmg feet are planted firmly on the floor.

Remove the sh1pp1ng bracket that secures the extendable BA11-FC Mountmg Boxin the cabinet.

2-5

2.3.4

AC Power Connections

‘A 3-wire cable is used to connect the site source power to the power controllerin ‘the H960-C cabinet. The cable is

connected at the factory for either 230V, 50 Hz or 115V, 60 Hz operation. All cabinets in a PDP-11/40 System

include a power controller and a smgle ac power cable; power is distributed within the cabinet from the power
|

controller.

Proper connection of power is basic to system operation and personnel safety. Power cables must be connected to a
site power system that provides ac power plus ground. The cabinets should be grounded to an earth ground, with
| ground straps connecting all the cabinets to each other. In addition, the frame ground wire in each power cable
connects the cabinet ground system to the site power system ground.

Before connecting any power cables to the site source power, check all site wiring. Ensure that power receptacles of
the appropriate types have been provided for each cabinet, and that the receptacles are positioned close enough to
the cabinet positions to allow connecting the cables without stretching or crossing the cables. In particular, check
that the proper voltage levels are present and that the phase wires have been connected to the same pins in each
receptacle so that all cabinet power controllers receive the same voltage phase.

2.3.5 Intercabinet Connections

When a multi-cabinet system is assembled, three types of electrical connections must be made between cabinets (see

Paragraph 2.3.3 for mechanrcal connectrons) These connectrons are:

Unibus connections —a BC11-A cable must connect the last system unit in a cabinet to the first system
unit in the next cabinet. The shortest possible length should be used to reduce loading.

Remote power connectrons — all cabinet power controllers are interconnected by a 3-wire control bus
|
that provides for system turn-on and turn-off and emergency shut-off.

~C.

.Ground strappmg the frame ground of the system is drstrrbuted through the cabinets by drrect
electrical connections between the cabinet frames.

2.3.5.1 Unibus Connections — To connect the Unibus between the H960-C Cabinet and an H960-D Expansion

Cabinet, insert the BC11-A cable in the rear system unit slot of the BA11-FC Mountrng Box of the H960-C Cabinet.

The cable then runs through a cable clamp in the upper left corner at the rear of the BA11-FC Mounting Box andis

passed under the power supply mounting rails into the next cabinet. In the H960-D Cabinet, the cable passes
through a similar cable clamp and is inserted in the appropriate slot of the first system unit of the mounting box.
The BA11-FC is noted above as an example, other mounting boxes mrght be the last box.

2 3. 52 Remote Power Connectrons — Each cabinetin the system has one 861 Power Controller. All controllers are

connected by a 3-wire bus that enables a remote turn-on and turn-off, and an emergency shut-off. There are three
Mate-N-Lok connectors on each power controller for the 3-wire bus. A cable is supplied with each cabinet to
connect the power control of that cabinet to the next cabinet. Because each 861 Power Controller must be capable
- of connecting to the 861 Power Controllersin the preceding and following cabinets, two Mate-N- Lok connectors are

reserved for the intercabinet cables. The third connector is provided for connection to a remote on/off switch and a
|

thermal switch, or other emergency shut-off devices within the cabmet

2.3.5.3 Ground Strappmg Electrrcal safetyis provided by connectrng all the cabmet frames to the ground level of
is done by connecting a wire in each power cable between the frame and the power
the site power system. This
system ground; this is not a load carrying wire, and is intended only as an emergency ground path. The green wire in
each power cable is the frame ground while the white wire is the neutral, or return wire, that carries the load
~

current. -

2-6

To improve the level of safety provided by the frame ground connections, all cabinet frames

are connected' by

braided copper straps of 4 AWG solid wire with crimp-on lugs, which are fastened to copper studs that are welded to
the frames (this also prevents the generation of ground loops between cabinets that are connected by signal-carrying
cables). The studs are welded to the bottom srde rails of the cabinet frame, facrng inward; the stud on ‘the left side of

the cabinetis slrghtly forward of center while the stud on the right side is slightly to the rear.

~ The ground strap supplied with each cabinet is fastened to one stud, passed over the side rail of that cabmet and the

side rail of the adjacent cabinet, and fastened to the stud in that cabinet. The copper studs are threaded, and nuts are
supphed on the studs.

Remote Perrpheral Interconnectlon

2.3.6

Installation instructions for remote peripherals, such as line printers, card readers, and magnetic tape units, are

covered in the appropriate peripheral maintenance manual. Normally, the peripheral itselfis a free-standing unit and
- the peripheral controller is mounted in one of the system drawers. The controller and -peripheral must be
mterconnected and the peripheral must also be connected to an ac power source.

Ina basrc PDP 11/40 System there is a small peripheral controller mountrng slot that houses the controller for the
system 1nput/output device (LA3O DEerrter or Teletype unrt) This device is characterrstrc of remote perrpherals
-

mstallatron

When 1nstalhng the system it is necessary to 1nterconnect the system and the mput/output devrce (DEerrter or
Teletype) as describedin the following steps

1. Place the free-standing LA3ODEeriter or Teletype‘in the desired position neXt to the system cabinet.
or Teletype»unit through the back of the system cabinet and
Run the control cable from the DECwriter

~ through the cable clamp at the rear of the mounting box. Note that because of the size of the control
‘cable connector one side of the cable clamp must f1rst be loosened and moved aside before the
~connector can be brought into the box.

Bring the cable connector into the mounting box and connect it to the receptacle on the input terminal

control (DLI11, KLll or LC1 1) mountedin the small perrpheral controller slot of the processor

Place the cable clamp movedin step 2. above over the cable and trghten

Verify that the 1nput termmal control module is plugged securely into the small perrpheral controller
-

slot.

Connect the power cable from the DEerrter or Teletype unit into one of the 861 Power Controller

_power receptacles

2 3.7 Installatlon Verlflcatlon

"'PI‘IOI' to turnmg power on, proper mstallatron of all processor internal optrons and memory should be verrfred
Although memory and processor options are mstalled in the system at the factory, 1nstallat10n should be verified at
the site.

Installatron verification procedures for the available processor options are given in Table 2-1. Verification procedures

for core memory, as well as procedures for installing additional memory, are grven in Table 2-2. A dragram of the
memory system unit is shownin Chapter 6 (Figure 6- 4).

2.7

Table 2-1 |

N B . | Q:p-t‘ion I.nstallation Verification .

| Optnon .

Procedure

‘,Venfy that KE11-E module M7238 is installed in slot 02

KE11l-E Extended Instructron

- Set (EIS) Optlon .

N (sectlons A——F) of processor backplane

. Ensure that ]umper W1 on print K3-8 of KD11-A prOCessor

module M7233 (located in slot 05, sections A F) has been
,_removed

3. Ensu,re
~

the three ‘over-the-back cables have been

that

connected
to

the 40-pin

Berg

connectors

the M7238

KE11-E module and the M7232 processor module (slot 03,

.section AD) These cables provide a required logic inter-

connecton between the processor and the KEll E option.

KEH F Floatrng Instructmn:' ‘V 1 .} . Verlfy that the KEll E optron has been 1nstalled The KEll E |

isa prereqursrte for the KE11-F.

Set (FIS) Optron R

Verlfy that KEll -F module M7239 is 1nstalled 1n slot ()1 o

o (sectlons A— D) of processor backplane

3. Ensure that the three ]umpers on the KEll E M7238 module )
B

have been removed. These jumpers must be removed to allow -

B T ,:'the KE11-F option to execute floatrng pomt instructions. Thev
S

;-,..J

umpers

are

follo

ws
SR

Jumper

Printf " Module

KBS

w1 :_“.,KE'Q" W3

- KT11-D

Memory Management - |

- Option (requires
the KT11:A
|
~ installation procedure also)

‘_ - AKE9

M7238

-.'Verrfy that KTll D module M7236 is. mstalled 1n slot 08 |

"l‘(sectrons AF) of processor backplane

; ;-.‘Ver1fy that processor jumper changes have been made as
- indicated below (these changes are detafled in the installation
L sectron of the KTllD optron manual)

- Verrfy that the followmg]umpers have been removed

- ,Jumper_
W9
W6
W5

P:_rm».,t:': o | Module |

M7231
K18
K18 M7231
K18
M7231

w1 K17

w2
K17
‘w3
K17
K17
w4
‘W7
K19

K19 =

M7231
M7231

M7231
M7231
M7231

M7231

Table 2-1 (Cont)

Option Installation Verification
Procedure

Option

Verify that

the following jumpers have been moved in

accordance with notes on prints:

W10

K16

M7231

K44

M7234

Verify that the following components have been added:
C113

K4-4

M7234

Cl14

K44

M7234

1. Verify that KJ11-A module M7237 is installed in slot EO3 of

‘ ~—_

KJ11-A Stack Limit Register

the processor backplane.

2. Verify that the following processor jumpers have been moved
~

inaccordance with notes on prints:

Jumper
W2*

w1
W1

Module

K1-7

M7231

K4-4
K54

M7234
M7235

*Note that if the KT11-D option is

present, jumper W2 of M7231 is
removed completely.

KW11-L Line Time Clock

Verify that

KW11-L module M787 is installed in slot FO3 of the

processor backplane. Verify that the backpanel wire between pin
- FO3R2 and FO3V2 for BG6 H has been removed
KM11-A Maintenance Console

This option consists of a double-length module (W130/W 131)'
that is plugged into slot FO1 when used to monitor KD11-A
~ operation, and slot EO1 when used to monitor KT11 -D, KE11-E,
“or KE11-F operation.

- Note that this option is not installed in the system during normal
use.

Revision 1
2.9

January 1974

Table 2-2
Memory Verification or Installation

Mem Ory
'MF11-L Core Memory
|

Verify proper address selection on jumpersAon G110 Control &

(basic to PDP-11/40)

Data Loops module.
2.

Verify that modules are installed for basic 8K memory as follows:

Module

Slot/Sections

H214 Memory Stack

01/C—F

G231 Memory Drivers
G110 Control & Data Loops

02/A-F
03/A—F

Verify Unibus interconnection to the KD11-A processor (M981)
and interconnection or termination to rest of system (M920 or
M930).

- 4a.

Ifolder type system:

Verify that system unit ‘power cable (D-1A-7009103-0-0) is
connected from the system unit to Mate-N-Lok receptacles of the
power distribution panel located on the BA11-FC Mounting Box

(see Figure 6-10). Connector P1 goes to 3; connector P2 goes to
.

)

,,“

If newer type system:

~ Verify tha't system unit power cable (D-1A- 7009565) is connected
from the

system

unit

to the power distributors: the -15V

connector (15 pin, 2 wire: blue and black) and the 6 pin signal
connector, to the first power distributor; the +5V connector (15

pin) to the second power dlstnbutor

~ MM11-L Core Memories

Select proper address se]ection on jumpers on G110 Control &

(additional memories

added to MF11-L

| memorles)

- 2.

Data Loops module.
|

For 16K memory, insert modules as follows in addition to the 8K
- configuration described above:

Module
G231 Memory Drivers

Slot/Sections

04/A—F

G110 Control & Data Loops

05/A—F

H214 Memory Stack

06/C—F

For 24K memory, insert modules as follows in addition
to the
16K configuration described above:

Module

07/A-F

G110 Control & Data Loops

08/A—F

H214 Memory Stack

09/C—F

Revision 1
January 1974

Slot/Sections |

G231 Memory Drivers

2-10

4b.

Procedure

Table 2-2 (Cont)
Memory Verification or Installation
Memory

Procedure

MF11-L Core Memory

Insert the MF11-L system unit into the BA11- FC Mountmo Box

~ (expansion units added

using thumb screws provided.
[\

~ to basic PDP-11/40)

Rearrange Unibu's connections and termination using the M920

‘and M930, respectively. If memory is last unit in the mounting
box, use BC11-A cable for interconnection to a next box.
LI

Verify proper address seleetlons on jumpers on G110 Control &

Data Loops modules.

Insert modules according to locations noted for MF11-L Core
Memory (basic) and MM11-L Core Memories (additional).

'Sa.

If older type unit:

A system unit power'cable'(D-IA-70091 74-0-0) is used to connect
the backpanel of the additional MF11-L to the power distributor

panel’s Mate-N-Lok receptacles. See Paragraph 6.4.7 for power
loading restrictions.

If newer type unit:
Same as Sa, except that the power cable is D-IA-7009560.
NOTE

If PDP-11/20 Memory Systems are mstalled they must
be housedin their own mountmg boxes and powered by
their own power supplies.

MFI 1-U/UP

. Install the MF11-U/UP backplane mto the mounting box, using
the screws provided.

Rearrange or install Unibus connections, as requi‘red.
Verify that address and interleaving jumpers are correct. Refer to
Chapter 2 of the MF11-U/UP Core Memory System Maintenance
Manual, DEC-1 1-HMFMA-C-D, for details.

Insert modules as shown in Chapter 1 of the MF11- U/UP Core
| Memory System Maintenance Manual.
Sa.

If early type unit:

Install as explained in Paragraph 6.4.7 of this manual.

5b. If later type unit:
Install power harness 7009535 between the MF11-U/UP and the
Power

Distribution

Panel.

If this

memory

the

PDP-11/40 CPU, the hamess should be plugged into the second
power distributor (not the same one as the CPU).
2-11

| Table 2-2 (Cont)
Memory

MF11-U/UP

(Cont)

Memory Verification or Installation

Procedure

Make sure that an H754 +20 -5V regulator is mstalled in the
H742 Power Supply

A complete checkout procedure is included in the MF11-U/UP
Core Memory System Maintenance Manual, Chapter 5.

2.3.8 Initial Power Turn-on
NOTE

Power distribution system differences are describedin Chapter
6. Refer to Fiigures 6-10 and 6-13 for plug locations.

Before turning power on, check the PDP-1 1/,40 System as described in the following.. steps:
1.

,Ensurethat all installation Veri“ficatio'n procedures (Paragraph 2.3.7) have been performed.
Before plugging in the system ac po\Ver cord disconnect. the following Mate-N-Lok connectors in the
basic H742 Power Supply wiring harness: Pl through P7 (and P18 if a newer system). Note that
connectors P8 through P15 remain connected.

Turn off the circuit breaker on the 861 Power Controller. (If more th"an one cabinet exists, turn off all
861 Power Controllers ) Check all cable connections for proper seating.
\-

CAUTION

Before connecting the 861 Power Controller to local power, be

certain that line frequency and voltage are compatible with
power controller requirements.

Line frequency should be

50—60 Hz (+3) and line voltage should be 180—270V for the
861-B Power Controller and 90—135V for the 861-C Power
N

Controllér.

~ Plug in the ac power cord, turn on the circuit breaker and check the dc voltages generated by the

regulators. These voltages can be checked
at pins of connectors P1 through P6 (and P18 if a newer
system). See Figures 6-11 and 6-14 for specific pin numbers. Check fan ac power on connector P7. If
any voltages are found to be incorrect, refer to power system mamtenance in Chapter 7 and take

- corrective action before continuing to the next step of thls procedure
Turn off the circuit breaker and reconnect all connectors.

Turn on crrcurt breaker and perform voltage regulator checksin accordance w1th Paragraph 74.2. 2.

Verify correct operation of the 861 Power Controller’s REMOTE/OFF/LOCAL switch in accordance"
w1th Paragraph 7.4.2.3.

Revision1

January 1974

2-12

2.4

INITIAL OPERATION AND PROGRAMMING

Once the system has been installed and power applied, preliminary operating and programming procedures should be
followed prior to using the system. Console operation, as well as the basic operating procedures noted in Chapter 3,

should be performed first. If the user is already familiar with console operation, then the basic operating procedures
given in Paragraph 3.6 may be performed immediately. These procedures are necessary to, but independent from,
the customer acceptance procedure noted in Paragraph 2.5.

After initial operation, the above procedures use a common set of system, peripheral, and individual instruction
diagnostics. These programs, listed in Table 7-3, define initial acceptance and operation. They also provide for a

continuing check on proper operation and permit analysis of system failures.
2.5

CUSTOMER ACCEPTANCE

Verify correct system operation by performing the Customer Acceptance Procedures. The Customer Acceptance

Procedures document is shipped with the PDP-11/40 System and lists all the tools, programs, and tests required to
certify system operation.

2-13

CHAPTER 3

SYSTEM OPERATION

3.1

SCOPE

This chapter provides the information necessary to operate and program the PDP-11/40 System and associated

input/output terminal, (LA30 DECwriter or ASR 33 Teletype). The description is divided into five major
parts: programmer’s console, DECwriter, Teletype, basic system operation, and basic system programming.
The description of controls and indicators for the consoles is in tabular form and provides the user with the type and

function of each operating switch and indicator. Operating controls for peripheral devices that are not part of the

basic machine are contained in the appropriate peripheral manual. Operation of the programmer’s console, LA30
DECwriter, and ASR 33 Teletype is covered in Paragraphs 3.2, 3.3, and 3.4, respectively.
Basic step-by-step procedures for both manual and program operation are given in Paragraph 3.5. More specifically,

procedures for loading the bootstrap loader, absolute loader, and the maintenance loader are provided in Paragraphs
3.5.3, 3.5.4.1, and 3.5.4.2, respectively. Basic system programming is covered in Paragraph 3.6.

3.2

KYll -D PROGRAMMER’S CONSOLE

The KY11-D Programmer’s Console (Figure 3-1) prowdes the PDP 11/40 System with a necessary and useful
programmer’s interface. Manual operation of the system is controlled by switches mounted on this console whichis
the front panel of the basic mounting box. Visual displays indicate processor operation and the contents of the

address and data registers.

All register displays and switches, whether marked on the console panel or not, are numbered from right to left. The

numbers correspond to the power of two: 215 ... ... .... 22,21, 2% Therefore, the most significant bit (MSB) is
at the left of each specific register or display, the least significant bit (LSB) is at the right. Whenever an indicator is
on, it denotes the presence of a binary 1 in the particular bit position. The alternate color codmg on the console

identifies the different functlons or segments of the binary wordin octal format.

In addition to the alternate segment color coding, the DATA register contains an index mark that divides the

low-order byte (bits 7—0) from the high-order byte (bits 15—8). The high-order byte is divided into octal format by
two more index marks. No marks are required for the low-order byte because octal coding for this byteis identical
to the alternate segment color coding.

Figure 3-1 shows the location of all PDP-11/40 console controls and indicators. Each indicator and associated
function is listed in Table 3-1. Each control and related function is listed
in Table 3-2.

3-1

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3-14

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3.3 DECwriter
The LA30 DECwriter is an input/output device that can be used with the PDP-11/40 System. Data can be entered
into the processor via the keyboard or data from the processor can be printed out by the DECwriter under program
control. Controls and indicators for the serial version LA30 DECwriter are shown in Figures 3-2 and 3-3 and listed in

Table 3-3. The serial version of the LA30, the LA30-S, would normally be used with the PDP-11/40 in that it is
compatible with the DL11 input terminal control and the DL11 is part of the PDP-11/40 basic configuration. The
LC11 is compatible with the parallel version of the LA30, the LA30-P. Further detailed operating information is

contained in the LA30 DECwnter Manual (DEC-00-LA30-DD) and in the LC11 DECwriter System Manual

(DEC-11-HLCB-D).

Table3-3

~ LA30 Controls and Indicators

Index
)

Cohtr.ol/lhdieator'

READY
|

Function

Lamp — Indicates power up on printer electronics

and

that

Indicates

the

DECwriter is

READY

for use.

an interrupt is enabled by keyboard

electronics, if INT bit is set by software.
2

LOCAL LINE FEED

Switch — When depressed, causes a local line feed

to be applied to the printer without a code being
sent out to the computer. This control will also

disrupt printing, but no characters will be lost.

MODELOCALLINE

BAUD RATE 110,150,300

2-Position Switch — Selects either local or on-line
|

operation.

3-Position Switch — Selects the baud rate clock
frequencies for 110, 150, and 300 baud.

MOTOR POWER
-

)

6
1

Breaker (CB2) — Applies power to printer stepping

ACPOWER
|

3.4

motor electronics.

Breaker (CB1)— Applies ac power to the unit
power supply.

TELETYPE

The ASR 33 Teletype unit is an 1nput/output device that can be used W1th the PDP- 11/40 System. Data can be
entered into the processor via the keyboard or through a paper-tape reader. The Teletype can also be operated

off-line to punch paper tapes. Controls for the ASR 33 Teletype are shown in Figure 3-4 and listed in Table 3-4.
Further detailed operatmg information is contamed in the Teletype Corporation manuals listedin Table 1-2 of this

manual.

3-15

Figure 3-2

LA30-S Keyboard

ALt AGRACEOTRASIO N R

Figure 3-3

LA30 Power Controls

3-16

DRI

ARY 2 B0

Figure 3-4

Teletype Controls

Table 3-4
Teletype Controls
Control

Remarks

Function

Type

Punch:

REL. pushbutton

Momentary

switch,

Disengages the paper tape from the
punch to allow loading or removal of

depress to activate

tape.

B. SP. pushbutton

Momentary switch, de-

Backspaces the paper tape by one
space

press to activate

each time

the

pushbutton is

depressed to allow manual correction
or rubout of character just punched.
ON pushbutton

2-position switch, con-

When depressed, turns on the paper-

nected

push-

tape punch and releases OFF switch.

2-position switch, con-

When depressed, turns off the paper-

nected

tape punch and releases ON switch.

OFF

button

OFF pushbutton

push-

button

3-17

Table 3-4 (Cont)
Teletype Controls

Control

Type

Function

Remarks

Controls operation of the tape reader.

Used on-line

Reader:

START/STOP/

3-position switch

FREE switch

- START position — engages tape reader
which begins operation under program

control.

STOP position — engages reader mech-

‘anism but does not energize it. In
~effect, tape is locked in the reader but

reading operation does not begin until

the switch is moved to START.
FREE position — disengages reader to

permit loading and unloading of tape.

LINE/OFF/

3-position

LOCAL switch

rotary switch

Serves two functions: applies primary
-power to Teletype and connects com-

puter to Teletype.
LINE

position — energizes

Teletype

and connects it to the computer as an

input/output

device.

Signals

from

either the Teletype reader or keyboard

can be used as an input while the
computer output can be used to con-

trol the keyboard or punch.

OFF position — deenergizes the Teletype by removing primary power.

LOCAL

position — disconnects

the

Teletype

from

The

the

computer.

Teletype can be used for punching or

‘reading tapes but all control is localized at the keyboard.
Keyboard

45 printing

Uses

characters

print characters on paper, punch tape,

6 non-printing

puter.

typewriter-like

keyboard

or input information into the com-

characters

Off-Line Operation (LOCAL) — When
Typewriter-like

tape reader and punch are off, prints

layout

characters on paper.

3-18

Table 3-4 (Cont)

Teletype Controls

Function

Type

Control
Keyboard (cont)

Remarks

When punch is on, simultaneously

prints characters on paper and punches

~ equivalent code into paper tape.

'When reader is on, reads code from
punched paper tape and prints equivalent characters on paper.

On-Line

Operation

(LINE) — When

tape reader and punch are off, prints
characters on paper and sends equivato the computer.
lent signals

When tape reader is on, reads code
from punched paper tape and sends
equivalent signals to computer. No
characters are printed.

When receiving signals from computer,
prints equivalent characters on paper
and punches tape if punch is on.

Cover Guard

~ Latch, push to ',
release

Used to hold paper tape in posmon

when using tape reader.

3.5 BASIC OPERATION

Many methods exist for stormg, mod1fymg, and retnevmg information from the PDP- 11/40 Systern These methods
depend on the form of the information, time limitations, and the peripheral equipment connected to the processor.
The following procedures are basic to the use of the PDP-11/40 System. Although they may be used less frequently
as the programming and use of the system become more sophisticated, they are valuable in preparing the initial
programs and in learning the function of system input and output transfers. For an understanding of the various
operational controls and 1nd1cators refer to Paragraphs 3.2 through 3.4. Basic programming techniques are given in

Paragraph 3.6.

Moo

| Operating procedures are separated into the following categories:

Powér .dn — Paragraph 3.5.1

Basic console cbntrol — Pa'ragraph'.3i,5 2

Manuai program loading — Pa‘ragraph 3.5.3

Automatic program loading — Paragraph 3.5.4

Running programs — Paragraph 3.5.5

3-19

3.5.1

Power On

When the programmer’s console

OFF/POWER/LOCK switch is turned from OFF to POWER, the system is

initialized (zeroed). A time delay allows sufficient time for voltages to logic units (especwlly memory elements) to

stabilize.

The power-up initialization logic directly sets the microprogram control to a sequence of controlled events

determined by the setting of the ENABLE/HALT switch. If the console ENABLE/HALT switch is set to ENABLE
when power is turned on, the processor executes a power-up microprogram sequence with the power-up vector
address determined by jumpers on the Status module (M7235) of the KD11-A Processor. A new Processor Status

(PS) word and Program Counter (PC) are unstacked from the vector address, and vector address plus two,
~

respectively.

Program operation begins with an entrance to the

FETCH portion of the microflow with the new PC used to obtain

the first instruction. Note that the processor status module jumpers are initially set at octal location 24. This
location can be changed to accommodate system requirements.
I the console ENABLE/HALT switch is set to HALT when power is turned on, the processor microflow is directly
set to the console microloop. The machine awaits the activation of a console control switch.

The LOCK position of the programmer’s console OFF /POWER/LOCK switch provides for program operation with
the console control switches disabled. However, the console Switch register may still be accessed.
3.5.2

Basic Console Control

Two major areas of control exist: control influenced by the ENABLE/HALT switch, which selects either program
or console control; and control by the switches and sequences used for loading data manually into the processor.

3.5.2.1

ENABLE/HALT Switch — When the processor has control (ENABLE/HALT in ENABLE), either the

START or CONT switch causes the program to run. The START switch initializes the system with a clear signal and
begins operation at a specific address determined by the last console operation (usually LOAD ADRS). The CONT

switch merely releases console control, and the program continues at the existing Program Counter (PC)
When the ENABLE/HALT switch is set to HALT, the console obtains control. The LOAD ADRS, EXAM, and DEP
switches can be used. The CONT switch can now cause the processor to step through the program a s1ngle
instruction at a time.

3.5.2.2

Loading Data Manually
— Whenever data is manually loaded into a computer, it is desirable to have the

address increment automatically upon each deposit. Thus, the user can set a starting address and continue to store

data in sequential memory locations providing only new data for each location. The programmer’s consolelogic also
-

permits the user to immediately examine the data just deposited without re-addressing, to re-deposit if necessary,

and to continue with automatic incrementation. These sequences are associated W1th the functioning of the DEP and
EXAM switches.

The address in the ADDRESS register, and R(ADRSC), does not increment the first time EXAM or DEP is used after
a HALT or LOAD ADRS. It does not increment if DEP is used immediately after EXAM or if EXAM is used

immediately after DEP. It does increment if a DEP is used immediately after a DEP,
or if an EXAM is used
immediately after an EXAM. This increment is a word increment as the console is word oriented. Thus, the user can

look at a location, change it, deposit the changed data, and then reexamine it without having to load an address each
time.

Incrementation is on even boundaries for all addresses except the addresses specifically designated for the processor
internal registers, which are incremented by 1.

3-20

For exatvn‘ple, to alter several successive locations, the following steps are performed:

LOAD ADRS (starting location)

EXAM (no increment — looks at starting location)

DEP .(no increment — loads starting location)

4. EXAM (no increment — checks previous deposit)
5.

EXAM (increment — looks at next location)

DEP (no increment — loads second locétion)

EXAM (no increment — checks previous depositj

EXAM (inorement — looks at third.loca’.cion) |

If the user desires to take advantage of automatic address incrementation for examining or loading data, the
following steps can be used to load data into sequential locations:

LOAD ADRS (starfing location)

DEP (no increment — loads starting location)

DEP (incfement — loads second location)

DEP (increment — loads third looatjon

DEP (increment — loads fourth location)
etc.

The same procedure can be used for exam’ining data in sequent-ial memory locations.
3.5.3 Manual Program Loadmg (Bootstrap Loader)

A primary manual use of the programmer’s console is to store the bootstrap loader in the core memory. (Programs
and data can be stored or modified by manual use of the programmer’s console.) The bootstrap loader
(DEC-11-L1PA-LA) is a minimal instruction program that can automatically load programs into core memory from a
paper tape punched in a special bootstrap format. One of these programs, after being stored, can in turn load any
binary format tape into the computer. (An explanation of the number de31gnat1ons used for DEC programs is given
in Table 3-5.)

The sequencé for loading the computer is shown in Figure 3-5, with programs noted as follows:
a.
b.

Bootstrap loader (DEC-11-L1PA-LA) — manually loaded by console switches; provides for automatic

loading of programs punched in a special format.

Absolute loader — punched in special format;loaded by bootstrap loader; provides for automatic loading
- of programs punched in binary format.

Selected program — punched in binary format;loaded automatically by absolute loader.

|
3.21

Revision 1
-

January 1974

Table35
Program Identification Codes

COMPUTER
- PRODUCT,_
\

Format:

DEC-11'L1PA-LA

IDENTIFICATION
,DISTRIBUTION

Notes:

Product Code

4544

2 3456 78

MAINDEC = maintenance library products

DEC =

programming library products

2 .

Computer Series

= PDP-11 Computer Systems

Major Category

= Loader

Minor Category

= firstin a series of programs

(sequential numbers)

= second in series, etc.

Option Category

(hardware required

P
~H

to use software)
|

° Revision Caté'gdry

= Teletype keyboard only

magtape

= basic program

(sequential letters)

= first revision

Distribution Method

~
|

= paper tape system
= high-speed reader and/or punch

7
o

| Exa’mplc:-

Distribution Mode
I

DEC-11-L2PB-PO K

second revision, etc.

= listing

‘P

A
B

= binary (absolute)

= other (bootstrap binary)

paper tape

= ASCII
|

Indicates a PDP-11 .pr_’ogravmming library product,
second in a series
of loaders, requiring a paper tape

‘system to use, the first revision to the program, supplied as a paper tape in bootstrap binary format.

322

/"/
N

PROGRAM
LOAD

718 N\

~ABSOLUTE
LOADER
~LOADED

USE ABSOLUTE
LOADER TO
LOAD PROGRAM

USE
| MAINTENANCE
" LOADER TO
LOAD PROGRAM

USE BOOTSTRAP
TO LOAD
ABSOLUTE OR
MAINTENANCE

_~~
DO
YOU HAVE
BOOTSTRAP
A

PROGRAM

- ROM

RUN

Y NO

LOAD BOOT

LOAD ADDRESS

AND START

LOADER
PROGRAM

i1-1023

Figure 3-5 Flowchart of Procedure for Loading and Running Programs

To eliminate the necessity of more than one bootstrap loader, the bootstrap loader instructions contain two

variables (x and y) to provide compatibility with various memory configurations and reading devices. These variables
are listed in Table 3-6. A complete explanation of the bootstrap loader program is given in Chapter 5 of the PDP-11
Paper Tape Software Programming Handbook (DEC-11-XPTSA-A-D); further information may be found in the
program listing, DEC-11-L1PA-LA.

3-23

Table 3-6
Bootstrap Loader

(DEC-11-L1PA-LA)

Bootstrap loader should be toggled into highest core memory bank.

Address

Instruction

xx7744

016701

xx7746

000026

xx7750

012702

005211

xx7756

105711

xx7760

100376

xx7762

- 116162

xx7764

000002

xx7766

xx7400

xx7770

005267

xx7772

177756

xx7774

000765

Xx7776

Yyyyyy

xx represents highest available memory bank. First location of the loader is one of the following, depending
on memory size;
xx in all subsequent locations is the same as the first.

Address

Memory Bank

037744

077744

137744

157744

Memory Size

8K
16K

7 4
28K

Contents of address xx7776 (yyyyyy) should contain device status register address of paper-tape reader to be
-

used when loading the bootstrap formatted tape. Addresses are:
Teletype Paper-Tape Reader

177560

High-Speed Paper-Tape Reader

177550

3-24

xx7754

v”

000352

o’

xx7752

The following procedure is used to manually load the BOOT bootstrap loader program (DEC-1 1-L1PA-LA):
Bt

Set ENABLE/HALT switch to HALT to give bus control to the console when powering up.

Turn OFF[POWER/LOCK switch to POWER position. This Venergizes the programmer’s console.

. Enter starting address of bootstrap loader (Table 3-6) into Switch register. Make certain that the correct
xx value is used (037744 for 8K memory, 077744 for 16K memory, 137744 for 24K memory, etc.).

Depress LOAD ADRS switch. The address set in the Switch register is shown on the ADDRESS display.
. Enter starting address contents (016701) into Switch register.

Lift DEP switch. The contents just entered in the Switch register is displayed in the DATA display. |
//,

Enter contents of next address into Switch register.
NOTE

"It is not necessary to load addresses after the starting address
has been loaded because the address is automatically
incremented by two each time DEP is used consecutively.

Lift DEP switch.

‘Repeat steps 7 and 8 above for each location of the bootstrap loader. When loading the contents of
address xx7766, make certain that the correct x value is used. When loading the contents of the last
address, make certain that the correct y value is used.

10.

11.

The bootstrap loader program is now loaded in memory locations xx7744 through xx7776 and can be

used to automatically load other programs into memory.

Correct program entry can be verified by examining the addresses between xx7744 and xx7776. This is
accomplished by setting the starting address into the Switch register, depressing the LOAD ADRS switch
and depressing the EXAM switch. The contents of the starting address are shown in the DATA display.
Each time the EXAM is again depressed, the address is automatically incremented by two and the
corresponding contents displayed.

12.

Step 11 alone (verification) may be sufficient if the bootstrap loader program has already been loaded

~ into the system. The program is stored in the last portion of available memory so that it tends to survive
and is available for reloading programs. If the program is not in tact, load according
program operation
to the above procedure, beginning with step 1.

3.5.4

Automatic Program Loading

Information can be stored or modified in the computer automatically only if a program capable of performing these
functions has previously been stored in the core memory. For example, having the bootstrap loader stored in the
computer enables the user to operate any program that has been punched in the special tape format required by the
bootstrap loader. Typical programs of this type include the absolute loader, the absolute dump, and the teleprinter
dump.

3-25

The bootstrap loader is limited because of the special
tape format; another loader is used to load any binary format

tape into the computer. This is the absolute loader (DEC-11-L2PC-PO), which is loaded into the computer by the

bootstrap loader. Once the absolute loader is in memory, any binary tape program (such as PAL III assembler,
symbolic editor, input/output service routines, diagnostics, mathematical routines, etc.) may be automatically
loaded.

The following paragraphs give procedures for loading the absolute 10adef, and for using the absolute loader to store
other programs. A complete description of the absolute loader program is given in Chapter 5 of the PDP-11 Paper
Tape Software Programming Handbook, DEC-11-XPTSA-A-D; refer also to the program listing, DEC-11-L2PC-LA.

3.5.4.1

Loading Absolute Loader — The following procedure is used for automatlcally loading the absolute loader

program (DEC-11-L2PC-PO):

Set ENABLE/HALT switch to HALT.

Make certain that the bootstrap loader has been stored in core memory (Paragraph 3.5.3, step 11).

Enter starting address of bootstrap loader into Switch register. The starting address is xx7744 (037744
for 8K memory, 077744 for 16K memory, 137744 for 24K memory, etc.).

Depress LOAD ADRS switch. The address set in the Switch reg1ster is dlsplayed in ADDRESS register
|

indicators.

Place the input/output device (LA30 DECwriter or Teletype unit) on-line (connected to the computer).
NOTE

If some other reading device (such as the high-speed paper-tape
reader) is used, ensure that the y value in bootstrap loader.
address xx7776 corresponds to the devnce as descnbed in
Table 3-6.

Place the absolute loader tape in the reader. Make certain that the special leader (a sequence of 351
punches) is under the reader station. Blank leader does not work.

Set ENABLE/HALT to ENABLE.

Depress START switch. The tape is now read into the computer which halts when the entire program is
loaded.

When the tape is completely loaded, the DATA display lights may be in any conflgurauon The main
reason for thisis that no checksum capability exists in the bootstrap loader.

Any PDP-11 program punched in binary format may be loaded automatic'ally by using’ the absolute loader. The
absolute loader can be set up to select either an absolute or relocatable code. If a relocatable code is selected, the

user may specify that the relocatable code start at a specific address or that the code start loading at the point the

previous load stopped. The absolute loader also provides a checksum test to ensure accurate loading. Although the
computer normally stops when the binary tape is loaded, instructions on the tape itself may cause the computer to

begin execution of the program immediately after loading is finished. This action is beyond the control of the user
because it is a part of the program on certain binary tapes.

3-26

The fol__lowing procedure is used for automatic loading of binary tapes into the computer using the absolute loader:
1.

Make certam that the absolute loader program is stored in core memory (Paragraph 3.5.4.1).

Set ENABLE/HALT switch to HALT.
Enter starting address of absolute loader into Switch register. The starting addressis xx7500 (037500 for

8K memory, 077500 for 16K memory, 137500 for 24K memory, etc.).

De'press’ LOAD ADRS switch. The starting address of the absolute loader is now displayed in ADDRESS
register indicators.

Select the type of load desired by setting the Switch register as specified in Table 3-7.
Make certain that input/output device (Teletype unit or LA30 DECwriter) is on-line.
|

NOTE

The reading device may be changed at any time
by the user

without reloading the absolute loader. If a reader is to be
changed, simply replace the contents of address xx7776 with

the appropriate device status address (y value in Table 3-6).

Load desired binary tape into reader by placing leader under the reader station.

Set ENABLE/HALT switch to ENABLE.
. Depress START switch. This begins the binary tape load.
10.

If the binary tape contains a transfer address instruction, the computer begins execution of the program
as soon as loading is complete.

11.

The computer stops when either loading is complete or there is a checksum error.

Loading complete — the low-order (right-hand) byte displayed in the DATA indicators is zero.
Additional binary tapes may be loaded by repeatmg steps 5 through 7 above and depressing the
CONT switch.

Checksum error — the low-order byte displayed in the DATA indicators is not zero, thereby
indicating a checksum error has occurred in the previous block of data. In this case, reposition the
tape in front of the error-producing block and depress the CONT switch.

Table 3-7

Binary Tape Load Selection

(using Absolute Loader)

Type of Load

Switch Register Settings
Bits 1501

Normal (absolute)

Bit 00

Not applicable

Relocatable (continue where left off)

Relocatable (load at specified address)

Offset from tape origin

3-27

3.5.4.2 Loading Maintenance Loader — The maintenance loader program, MAINDEC-11-D9EA, provides an
alternate method of loading diagnostic programs that can be used if the absolute loader fails to function because of a
hardware failure. This loader should only be used to load diagnostic programs if the absolute loader malfunctions.

Use the following procedure io automaticaily load the maintenance loader:
1.

Set ENABLE/HALT switch to HALT and depress START to clear the system.

Make certain that the bootstrap loader has been stored in memory, starting at address 037744.
NOTE

The maintenance loader operates in the lowest 8K of memory.
If some other memory area must be used, several program
locations must be changed as listed in Table 3-8 after the

maintenance program is loaded.

Set Switch register to 037744 and depress LOAD ADRS.

Place the input/output (LA30 DECwriter or Teletype unit) on-line.

Place the maintenance loader tape in paper-tape reader.

Set ENABLE/HALT switch to ENABLE and depress START. The tape is read into memory and the
processor halts when the entire program has been loaded.
NOTE

If the maintenance loader was not loaded into the lowest 8K

of memory, make location changes at this time (Table 3-8).

Table 3-8
Relocation of Memory Contents

Move Contents of

XX7502_

xx7470

xx7510

xx7474

xx7542

xx7475

xx7566

xx7475

xx7624

xx7776

xx7674

xx7474

Where xx equals:

03 for 8K memory

07 for 16K memory
13 for 24K memory

3-28

3.5.5

Running Programs

When running any program, the program must first be loaded into the core memory either manually
or via the
automatic loading programs (bootstrap loader or absolute loader). Once the program is in storage, it can be run at

any time by loading the starting address of the program (refer to appropriate program documentation) into the
Switch register, depressing the LOAD ADRS switch, and then depressing the START switch. The user also must

make certain that the ENABLE/HALT switch is in ENABLE and that the appropriate external devices are on-line

(connected to the computer).
The program can be manually stopped at any time by setting the ENABLE/HALT switch to HALT. It can be

restarted from that point by returning the ENABLE/HALT switch to ENABLE and depressing the

CONT switch. It

can be started anew by reloading the starting address and depressing the START switch.
A program can be altered during operation, or new data introduced, through the Switch register. This console

register has a bus address that the processor can reference in its instruction sequence. The information transferred
may be treated as data or used to alter program flow.

Because of the speed of the computer, console indicators are of limited value while the computer is running. Console
indicators are used primarily during manual operation, single instruction operation, or during the maintenance mode.
‘During manual operation, the console indicators reflect the console operations of LOAD ADRS, EXAM, and DEP.
During maintenance operations, the console indicators display various data functions of the processor
as the
maintenance module is used to step through the program a microword at a time. Use of the maintenance module is

~describedin the KD11-A Processor Maintenance Manual, EK-KD11A-MM-001.

3.6

BASIC PROGRAMMING

To produce programs that fully utilize the pOwer and flexibility of the PDP-11/40, it is necessary for the user to first
become familiar with various programming techniques that are part of the basic design philosophy of the PDP-11/40
System. These techniques (such as use of stacks, subroutine linkage, interrupt nesting, reentrant and recursive

programming, etc.) are covered in the PDP-11/40 Processor Handbook, which also provides a detailed discussion of
the instruction set.

In addition to the general programming information given in the PDP-11/40 Processor Handbook, the user should be
familiar with console operation (Paragraph 3.2) and with the basic and extended PDP-11/40 instruction sets

~.. s -

described in Chapter 4.
For those users already familiar with PDP-11/20 system programming, the primary programming differences

between the PDP-11/20 and PDP-11/40 Systems are listed in Table 3-9. With this table, the experienced user can
immediately begin to program the PDP-11/40 System.
Basically, the PDP-11/40 offers increased flexibility and speed. The basic system (without options) has five more

programming instructions than the PDP-11/20. These instructions are: eXclusive OR (XOR), Subtract One and

Branch (SOB), ReTurn from inTerrupt (RTT), Sign eXTend (SXT), and MARK (MARK). System flexibility is
increased even more if the KT11-D Memory Management Option and the KE11 Extended Instruction Set (EIS) and

Floating Instruction Set (FIS) Options are installed.

3-29

Table 3-9

PDP-11 Programming Comparison

~ PDP-11/20

PDP-11/40

- JMP/ISR (R)+ uses (REG) before autoincre-

JMP/ISR (R)+ uses (REG)+2 as address

- ment as address. All autoincrements are now
post autoincrements.

All REG 6 (SP) autodecrement references can

Address modes 1, 2,4, and 6, JSR and traps are

and traps are tested.

ences to stack data are always allowed.

No red zone on stack overflow.

“Red zone trap occurs if stack is 16 words below

tested except that nonaltering (DATIs) refer-

cause overflow. Address modes 4 and 5, JSR-

This trap saves PC+2 and PS on new
boundary.

“stack at locations 2 and 0.

SWAB instruction does not affect V.

SWAB instruction clears V.

Program HALT dlsplays PC of HALT mstruc
tion in ADDRESS display.

Program HALT displays PC+2 of HALT instruction in ADDRESS display.

Byte operations to the odd byte of the PS cause

Byte operations to the odd byte of the PS do

odd address traps.

not trap. No_t all bits may exist.

If RTT sets the T bit, the T bit trap occurs after

No RTT instruction.

the instruction followmg RTT.

.If RTI sets T bit, T bit trap acknowledged after

If RTI sets T bit, T bit trap acknowledged

immediately following RTI.

instruction following RTI.

Explicit reference to PS can IYOad T bit. Console

can load T bit, ’_initialize can clear it.

Only implicit references (RTI, RTT, traps, and

can load T bit. Console cannot load
interrupts)

T bit but initialize can clear it.

The BUS INIT of the RESET instruction occurs

The BUS INIT of the 'RESET instruction occurs

- asynchronously with other Unibus operations.

when the processor has control of the bus. No
bus cycles are interrupted.

CAUTION

Because PDP 11/20 and PDP-11/40 RESET instruction tlmmg

‘precludes the POWER FAIL routine, use of the RESET
instruction should be severely limited.

Odd address or nonexistent r,e_ferences using the

SP cause a HALT. This is a case of double bus
error with a second error occurring in the trap |

Odd address or nonexistent references using the

SP cause a fatal trap. On bus error in trap

service, a new stack is created at locations 0 and

service of the first error.

3.30

Table 3-9 (Cont)
PDP-11 Programming Comparison
PDP-11/20

PDP-11/40

Stack limit boundary fixed at octal 400 with

Optional variable stack limit boundary (KJ11-A
option). Use of red and yellow zones on either
basic (octal 400) or optionally variable bound-

violations serviced by an OVFL trap.

ary.

The first instruction in an interrupt routine is

First instruction in an interrupt service routine
‘is guaranteed to be executed.

not executed if another interrupt occurs at a

higher priority level than was assumed by the
first interrupt.

Power up vector is initially at 24; can alter

Power up vector at 24 when power returns.

jumpers to other addresses.

The formerly unnamed instruction for IR code

A trap instruction to vector location 14 exists
for the IR code 3. No name is given this

3 is now called BPT.

instruction.

Condition codes for a MOV instruction are not
altered for present data if a bus error occurs on
the last destination address. The error trap

Condition codes for a MOV instruction are
altered for present data if a bus error occurs on

sequence of that address.

address.

the last destination address. The error trap

occurs on the singular DATO sequence to that

occurs on the DATIP of the DATIP, DATO

NOTE

The following is the priority sequence of service for internal
processor traps, external interrupts, and HALT and WAIT.

BUS ERROR TRAP — odd address, fatal stack

BUS ERROR TRAP — odd address, data time

overflow (red); if KT11-D option is used,

out.

memory management violations; parity error
|

trap response.

Same. (Refer to KT11-D, if installed, for other

HALT instruction for console operation.

changes.)

TRAP instructions — illegal or reserved instructions, TRT, 10T, EMT, TRAP.

TRAP instructions — illegal or reserved instructions, BPT, IOT, EMT, TRAP.

TRACE TRAP — T bit of processor status.

Same

OVFL trap — stack overflow.

OVFL — warning (yellow) stack overflow.

PWR FAIL trap — power down.

Same

3-31

Table 3-9 (Cont)
PDP-11 Programming Comparison

PDP—11/20

PDP-11/40

CONSOLE BUS REQUEST
— console oper-

Same

UNIBUS BUS REQUEST — peripheral request,

Same

ation after HALT switch.

compared with processor priority, usually an
interrupt occurs.

WAIT LOOP —loop on a WAIT instruction in

Same

the IR until an interrupt allows exit. A CONSOLE BUS REQUEST returns to this loop after

being honored.

3-32

CHAPTER
4

PROCESSOR INSTRUCTIONS AND OPTIONS

4.1

SCOPE

This chapter presents a brief introduction of the PDP-11 instruction set and the processor options lavail'able for the
PDP-11/40 System.

’Paragraph 4.2 dlseusses the basic PDP-11 instruction set and also covers the additional instructions that are available
if certain processor options (KEI11-E, KEl 1- F and KT11-D) are installed in the basic system.
Paragraph
4.3 describes each of the options that can be mounted in the basic KD11-A Processor and references

appropriate documents containing detailed information on the specific option. These options are: KE11-E, KE11-F,
KJ11-A, KT11-D, KW11 L KM11-A, and a Small Peripheral Controller. Specifications are contained in Tables 4-12
through 4-16.

INSTRUCTION SET

'Thls section summarizes the PDP 11/40 address modes and instruction set. Its purpose is to define the operation of
the KD11-A Processor and provide qu1ck-reference tabular 1nformat1on A complete description of PDP-11/40

address modes and 1nstructlons with addltlonal details and examples is provided in the PDP-11/40 Processor
Handbook

The Instruction Set Processor (ISP) notation is used to define the processor operations for each address mode and

instruction. Table 4-1 defines the modified ISP symbology used in this chapter. A more detailed description of ISP
notation is provided in Appendix A of the PDP—] 1/40 Processor Handbook. Modified ISP notation is used in the
KD11-A Processor Manual in the block dlagram and flow dlagram description of instruction 1mplementatlon The
modifications are as follows

(( )

or () around an expression indicates logical AND

minus

. is used for( ) Or.[ ]

plus

indicates logical OR

indicates logical negation
indicates addition

indicates subtraction

The following paragraphs cover address modes (Paragraph 4.2.1), the basic instruction set (Paragraph 4.2.2), and the
extended instruction set (Paragraph 4.2. 3)

4-1

Table 4-1

ISP Symbology

Symbol
(

)

[ ]

Definition

)

Defines the limits of an expression, such as word length (15:0).

Defines the limits of a memory declaration: Mw [SP] specifies the address of the
stack pointer in memory.

The expression to the left of this symbol1s replaced by the expressmn to the nght
of this symbol,.
Z < 1 indicates the Z bitis set,

PC < PC + 2 indicates the program counter register (PC) is incremented by 2.
cat

Indicates concatenation; registers to the left and right of this expressmn are consid-

ered to be one register.
equiv

Designates that expressions to the left and right are equivalent.

Logical AND

Logical inclusive-OR

Negate

XOR
’

|
>

Logical exclusive-OR
Indicates that a reference to the expression with which this symbol is used may
cause side effects, e.g., registers may be changed as a result of the operation.

:
next

Used as a delimiter

A sequential delimiter, the operatlon to the left must occur before the operation to

the right.

)

Designates an address mode; address mod_e ] is indicated by m = 1;

General register 7 (program counter)

Auto-increment; by 2 for word instructions, and by 1 for byte inst’ruction‘s

Indicates a result; used many tlmes with limit symbols as an 1ntermedlate register

(r {15:0)).

Addition; expressmn to the left is added to expression to the rlght

Subtraction; expression to the r1ghtis subtracted from expresolon to the left

Multiply; expression to the leftis multlphed by expression to the right.

Divide; expression to the left is divided by the expression to the right.

sign-extend

)

The sign bit of a byte, bit 7, is extended through bits 8 to 15.

Memory word declaration; the address in brackets pointS'to the memory location.

nw’

Indicates next word, as pointed to by the PC with side effects (’). The word is at
the next sequential PC address, or the word pointed to by the next word (deferred
addressing).

R [dr]

Indicates that a reg1ster (R) address as a memory declaratlonis that of a dev1ce |
register.

Destination

Byte destination

Source

Byte source

|
|

4.2

)

4.2.1

Address Modes

The instruction set of the PDP-11/40 System flexibly interacts with the general-purpose registers through the address
modes. Table 4-2 lists all of the address modes, including the Program Counter (PC) register address modes. These

address modes, along with the general-purpose register designation, determine the instructions’ operands (source

and/or destination) and form part of the 16-bit instruction format (Figure 4-1).

Table 4-2
Address Modes

Mode

Designation

Sy mbolic

ISP

Description

General Purpose Register Addressing

if (m=0) then Rr{w1:0);

|@R or (R) | if (m=1) then M[Rr];

Defer to operand through register

deferred
2

(R, Rr) as address.

auto-increment | (R)+
-

autb-increment

@(R)+

deferred

The register (R, Rr) is the operand.

auto-decrement | -(R)

if (m=2) and (rg#7) then

Defer to operand through register

(M [Rr]; next

(R, Rr) as address, then increment.

Rr < Rr + ai);

if (m=3) and (rg#7) then

Defer to operand through (R), Mw

(M [Mw [Rr] ]; next

[Rr] as address, then increment

Rr < Rr+ 2;

if (m=4) then (Rr < Rr - ai); | Decrement register (R, Rr), then defer
next

M[Rr];

to operand through register (R, Rr) as

address.

auto-decrement | @-(R)

if (m=5) then (Rr <~ Rr - ai; | Defer to operand through (R), Mw

deferred

indexed

+X (R)

M[Mw [Rr]]);

Rr after decrement of register (R, Rr).

if (m=6) and (rg#7) then

Index via register = (R, Rr) by the

M[nw’ + Rr];

amount specified in next PC word (X).

indexed

@*=X(R) or|

if (m=7) and (rg#7) then

Defer to operand through index of

deferred

@(R)

M[Mw[nw’ + Rr]];

PC Register Addressing
2

immediate

if (m=2) and (rg=7) then
nw’ (wl:0)

(next word); next word is immediate

absolute

relative

@#HA

relative

operand.

if (m=3) and (rg=7) then

Defer via next word (PC address) as

M[nw’]

address to operand; absolute address-

ing.

- if (m=6) and (rg=7) then
M[nw’ + PC];

deferred

Defer to operand through PC value

if (m=7) and (rg=7) then
M[Mw[nw’ + PC]];

Relative to PC; uses next word as deferred address of operand.

Defer relative to PC; uses next wbrd as
address of deferred address of the operand.

NOTE: The following symbols are used in this table:
R

= Register

X, n, A = next program counter (PC) word (constant)

4.3

[ |
15

]

]
:

l
v

mopE 5@[

]

DESTINATION

OP CODE
%= SPECIFIES DIRECT OR

* % %

* %

SINGLE OPERAND

ADDRESS FIELD
INDIRECT ADDRESS.

#%= SPECIFIES HOW REGISTER WILL BE USED.

x%%=SPECIFIES ONE OF EIGHT GENERAL PURPOSE REGISTERS.

{

OP CODE
|

MODE | @
12

MODE | @

|
3
4
5

*% %

Kx¥%

DOUBLE OPERAND xx

—J

|
v

]
0

DESTINATION
ADDRESS FIELD

SOURCE
ADDRESS FIELD

*=DIRECT/DEFERRED BIT FOR SOURCE AND-DESTINATION ADDRESS.
%% = SPECIFIES HOW SELECTED REGISTERS ARE TO BE USED.

%% = SPECIFIES A GENERAL REGISTER.

|
t1-1068

Double and Single Operand Addressing

Figure 4-1

DOUBLE OPERAND

{

OP CODE
|

[

REG l

]

SOURCE OR DESTINATION

dst

Src

~SINGLE OPERAND

OP CODE

NS AN W

15
MISCELLANEOUS

{

T2
|

REG

]

BRANCH (PROGRAM CONTROL)

N T

OP CODE
R
SN A

OFFSET
TR SN

15
CONDITION

AN T

CODE OPERATORS

1°0 . °

0t 14l'TlNIVZJVICl

Figure 4-2

Instruction Formats

4-4

4.2.2

Basic Instruction Set

The KD11-A basic instruction set is divided into six gmups of instructions. The format of each group is shown in
Figure 4-2. The six groups of instructions are:

Double Operand _ Operations which imply two operands (such as ADD, SUBtract, MOVe, and

CoMPare) are handled by instructions that specify two addresses. The first operand
is called the source
operand; the second is called the destination operand. Bit assignments in the source and destination
address fields may specify different address modes and different registers.

Double-operand instructions
are listed in Table 4-3.

Single Operand — Operations which require only one operand (such as CLeaR, INCrement, TeST) are
handled by instructions that specify only a destination address (operand). The operation code, address
~mode, and destination address are specified by the instruction.

- Single-operand instructions are listed in Table 4-4.
Register Source or Destination — Instructions in this group make use of the general processor registers as

simple accumulators and the resultant is stored in the selected register. Information can be used as either
a source or destination operand. For example, the eXclusive OR of the selected register and the

destination operand can be stored in the destination address.

Branch (Program Control) — These instructions permit control of the program by branching to new

locations
in the program dependent on conditions tested by the program. The instructions cause the

program to branch to a location specified by the sum of an offset value (multiplied by 2) and the current
contents of the Program Counter (PC), provided the branch is either unconditional or is conditional and

the coh_dit_ions are met after testing the Processor Status (PS) word.
Branch instructions are listed in Table 4-6.

Miscellaneous — These instructions include 'HALT, WAIT, and RESET as well as interrupt and trap

handling instructions such as RTI, RTT, EMT, and TRAP.

MisCellane_ous instructions are listed in Table 4-7.

Condition Code Operators — These instructions are u‘se‘d, to set or clear individual condition codes in the
Processor Status (PS) word. Selected combinations of these bits may be set or cleared together.

Condition code operators are listed in Table 4-8.

Table 4-3

Double Operand Instructlons

Mnemonic

Instruction

ISP Notation

and Op Code

MOV

r < S’; next

Move

N+ (5

01SSDD

V<0,

(SrctoDst) | if (x<15:0)

Move source to intermediate register, 1.

' Set N if negative.

= 0) then (Z < 1 else Z < 0)

SetZif0.
Clear V.

D’ <r
MOVB

| Tfans’mit result to destination.

1 < Sb’; next

Move source to mtermedlate reglster I.

Move Byte
N« 1(7);
(Src to Dst) | if (r (7:0)= 0) then (z <1 else Z < 0)

Set N if negatwe |
Set
Z if O.
|

11SSDD

V <+ 0;

Clear V.

CMP
Compare

1(16:0)« S’ - D’ next o

Source and de_stinatiori-operands are compared, but unaffected.
Only condition codes are affected, as follows:

Db’ <r

Transmit result to destination.

(Src to Dst) | N« r(15);
02SSDD

if (r<15:0)

CMPB

Compare Byte|

“Set N if r is negative.

= O) then (Z <1 else Z < 0);

Set Z if ris 0.

if (S(15)=~DK15) & (S (15) XOR r (lS)) then | Set V if operands have opposite signs and the sign of the source

(V< lelse V< O)
|

|
- Description

C<r(16)

is the same as the result, r.

r (8:0) < Sb’ - Db’; next N<r (7

Clear
C if 17th bit is carry.

Same as CMP, exeept'ope.rands are bytes.

o L

if (1 (7:0)= 0) then (Z < 1 else Z < 0);
if (Sb{(7)=~Db (& (Sb (7) XOR I (7>) then
(V*—lelseV*-O)

C<+r1(8

BIT

r< D’ & S’; next

N «1{15);
)
o
if (r (15:00 = 0) then (Z < 1 else Z< 0); V<0
I

Set N if negative.
Set Z if.0..
No overflow.

BITB
Bit Test,

1< Db’ & Sb’;next
N« (7;
S

Same as BIT, except byte :
Lo

Byte

if (r (7:0)=0) then
(Z < 1 elseZ< 0);

13SSDD

V<0

BIC
Bit Clear

r<D&~S’; ne-xt o
N<rdsy;
=

04SSDD

if (r {15:0)

Bit Test
03SSDD

Logical AND of source and destination operands.

o
AND déstination o‘per‘andeith complemented source operand.
Set N if negative.
S

=0) then (Z <1 else Z<+ O)

Set Zif 0.

V< 0;

C_leélr V and putresult
in

D<«r

destination address.

BICB

r< Db &~ Sb” n'.ex't_‘

- Same as BIC, except byte.

Bit Clear,.

N <1 (7

Byte

if (r {7: 0= 0) then (Z « 1 else Z “ O)

14SSDD

V <0;

Db «r

4-6

Table 4-3 (Cont)

Double Operand Instructions
Mnemonic

Instruction

ISP Notation

Description

and Op Code

BIS

r < D’ OR §’; next

Inclusive OR of source operand and destination operand.

Bit Set

N« 1(15);

Set N if negative.

05SSDD

if (r {15:0)=0) then (Z < 1 else Z < 0);

Set Z if 0.

V<0,

Clear V.

D<r

Put result in destination.

r < Db’ OR Sb’; next

Same as BIS, except byte.

BISB

Bit Set, Byte

| N < r(7);

15SSDD

if (r(7:0)=0) then (Z < 1 else Z+ 0);

V< 0;
Db<«r

ADD

1 {16:0) < S’ + D’; next

Add

N <1 (15);

Add source and destination to provide 17-bit sum.

06SSDD

if (r {15:00 =0) then (Z < 1 else Z < 0);

Set Z if 0.

if (S (15) equiv D (15)) & (S (15) XOR r(15))

Set V if both operands were same sign and the result is of

then (V « 1 else V < 0);

~ opposite sign.

Set N if negative result.

C<+rl6);

Set
C if carry.

D <1 (15:0

Put result in destination.

SUB

1{16:0) < D’ - §’; next

Subtract source operand from destination operand.

Subtract

N <1 {15;

Set N if negative results.

16SSDD

if (r (15:0) = 0) then (Z < 1 else Z < 0);
|

if (D <15) XOR S(15)) & (D {15) XOR 1 (15))

Set Z if 0.
~Set V if operands had different signs and result is opposite

then (V < 1 else V < 0);

sign from destination.

C < r(16);

Clear C if a carry.

D« r{15:0)

Put result in destination.

4-1

Table 4-4

Single Operand Instructions
Mnemonic

Instruction

ISP Notation

Description

and Op Code

CLR

| D’ <o0;

Clear dst

0050DD

Clear destination, N, V, and C; set Z.

N < 0;

Z<1;
V < 0;

C<0

CLRB

Db’ < 0;

Clear destination byte.

Clear Byte dst | N < O;

'1050DD

Z<1;
V < 0;

C<0

COM

r <~ D’ next

Complement

dst

0051DD

COMB

Complement destination.

| N < r(15);

Set N if negative.

if (r {15:0>=0) then Z < 1 else Z < 0);

Set Z if 0.

V < 0;

Clear V.

C<«1;

Set C.

D<r

Put result in destination.

r < ~Db’;next

Same as COM, except byte.

Complement | N < r(7);
Byte dst

if (r (7:0)=0) then (Z < 1 else Z < 0);

1051DD

V<« 0;

C<1;

Db <1

INC

r< D’ +1;next

Increment dst | N < r(15);

0052DD

Result is sum of D plus 1.
-

Set N if negative.

if (r {15:0) = 0) then (Z < 1 else Z < 0);

Set Z if 0.

if (r <15:0) = 100000g) then (V « 1 else V< 0); | Set V if result equals 100000, (dst was 077777g).
D<r

Put result in destination.

INCB

r< Db’ + 1;next

Increment

Same as INC, except byte.

Byte dst

if (r {7:0> = 0) then (Z < 1 else Z < 0);

1052DD

if (r (7:00= 200g) then (V < 1 else V « 0);

Set V if result equals 2004 (dst byte was 1774).

Db «r

DEC

r <D’ ~1; next

Decrement

N < r(15);

~Result is destination operand minus 1.
Set N if negative.

dst

if (r (15:0> = 0) then (Z < 1 else Z < 0);

Set Z if 0.

0053DD

if (r <15:00="777774) then (V < L else V< 0); | Set Vif result equals 77777, (dst was 100000g).
D<r

Put result in destination.

DECB

r < Db’ -1;next

Same as DEC, except byte.

Decrement

N <1 (7;

Byte dst

if (r {7:0)=0) then (Z < 1 else Z < 0);

1053DD

if (r (7:0)= 1774) then (V < 1 else V< 0);
Db <«r

Set V if result is 177, (dst byte was 000,).

4-8

Table 4-4 (Cont)
Single Operand Instructions
[eoney

Mnemonic
Instruction

ISP Notation

Description

and Op Code

NEG

r <-D’; next

Negate dst

N <«r{15);

if (r (15:0)= 100000 ) then (V < 1 else V < 0); | Set V if result is 100000,.

0054DD

Negate D by 2’s complement.

‘

Set N if negative result.

if (r <15: 0 = 0) then (Z “lelseZ< O)

Set Z if 0.

if (r (15:0) = 0) then (C, < Qelse C < 1);

D<r
NEGB

Put resultin destination.

r<-Db’; next

Negate Byte
1054DD

Clear C if resultis 0, otherwme set C.

|
|

Same as NEG, except byte.

| N« r(7);
|

‘

if (r {7:0)=0) then (Z «< 1 else Z < 0);

if (r (7:00 = 200) then (V < 1 else V < 0);
if (r (7:0)=0) then (C < Qelse C « 1);

Db<«r |
ADC
Add Carry

- 0055DD

1< D’ +C;next
|

Add the C bit to the destmatlon

N« r(15);

Set N if negative.

if (r (15:0)= 0) then (z “1else Z< 0);

Set Z if 0.

|
| Set V if destination was 0777774 and C was 1.

| if (r <15:0>= 100000 ) & (C=1) then (V*— 1
else V < 0); next

if (r<15:00)=0)& (C=1) then (C <1 else

Set
C if destination was 177777¢ and C was 1.

C < 0);
D<r

ADCB

I < Db’ + C next

Add Carry

N < r(7;

Byte

if (r (7:0)
= 0) then (Z < 1 else Z < 0);

1055DD

Same as ADC, except byte.
|

if (r (7:0)
= 200g) & (C
= 1) then (V « 1 else

V < 0); next
if (r(7:00=0) & (C= 1) then (C+1 else C*—O)
Db<«r

SBC

<D ~C; next

Subtract

N < 1(15);

Carry

if (r (15:0)=0) then (Z < 1 else Z < O)

0056DD

Subtract
C bit from contents of destination.
Set N if negative.
|

Set Z if 0.

if (r {15:0)
= 1000004
) then (V « 1 else V « 0); | Set V if result is 100000,

if (r (15:0) =0) & (C=1) then (C < O else

‘Clear Cif result is 0 and C
=1.

C < 1)

D<«r

Put result. in destination.

SBCB

r < Db’ -C; next

‘Same as SBC, except byte.

Subtract

N« (D;

Carry Byte

if (r (7:0) = 0) then (Z < 1 else Z < 0);

1056DD

if (r ¢7:0) = 2004
) then (V « 1 else V < 0);

(r{7:00=0)& (C=1)then(C <0 else C « 1);

- Db<r

4-9

‘

‘ATable’4-4 (Cont)
Single Operand Instructions
Mnemonic

Instruction

ISP Notation

Description

and Op Code

TST

1 <D’ -0; next

Sets N and Z condition codes according to contents of

Test
0057DD

destination address.
N <1 (15);
if (1 (15:0) = 0) then (Z < 1 else Z < 0);
V <« Q;

C<0

TSTB

r < Db’ -0; next

Test Byte

N «r(7);

Same as TST, except byte.

1057DD

if (r (7:0)=0) then (Z < 1 else Z < 0);
V < 0;

C <0

ROR

1 €16:0) < D’ {0} cat C cat D’ (15:1); next

17-bit intermediate result is C and contents of destination

Rotate Right
0060DD

rotated right one plaee.
N <1 (15);

Set N if high order bit is set.

if (r {15:0)=0) then (Z < 1 else Z <« O)

Set Z if result is O.

C cat D(15:0) < r {16:0); next

Put 17-bit result into C bit and destination.

if (N XOR C) then (V < 1 else V< 0),

Load V with exclusive-OR of N and C (after rotation is
complete).

RORB

r (8:0) <~ Db’ (0 cat C cat Db’ (7:1); next

Same as ROR, except byte.

Rotate Right | N <« r(7);
Byte
1060DD

if (r (7:00=0) then (Z < 1 else Z « O)
C cat Db < r (8:0); next

if (N XOR C) then(V < 1 else V< 0)

ROL

r16:0) < D’ (15:0) cat C; next

Rotate Left
0061DD

17-bit result
is C and contents of destination rotated left one

bit.

N «<r(15);

Set N if result is negative.

if (r 15:0>=0) then (Z < 1 else Z < 0);

Set Z if resultis 0.

C cat D < 1 (16:0); next

Put result into C and D. Bit 15 into C b1t and prev1ous C bit
into bit 0.

if (N XOR C) then (V< 1 else V< 0)

Load V. W1th exclusive-OR of N and C after rotation is
complete.

ROLB

r (8:0) < Db’ (7:0) cat C; next

Rotate Left

N <1 (7

Byte

if (r (7:0) = 0) then (Z <«

1061DD

C cat Db < 1 (8:0); next

Same as ROL, except byte.

1 else Z < 0);

if (N XOR C) then (V < 1 else V < 0)
ASR

r < D’/2; next

Contents of destination shifted right one place (= 2).

Arithmetic
Shift Right

C <D0,
N < r{15);

Least-significarit bit loaded into C.
Set N if result negative.

if (r {15:0) = 0 then (Z < 1 else Z < 0); next

Set Z if result 0.

0062DD

Load V with exclusive-OR of N and C after shift is chplete;

- if (N XOR C) then (V < 1 else V< 0);
D<r

Put result into destination.

4-10

Table 4-4 (Cont)

Single Operand Instructions
Mnemonic

Instruction

ISP Notation

Description

and Op Code

ASRB

r< Db’/2; next

Arithmetic

C < Db (0,

Same as ASR except byte.

Shift Right

N <1 (7);

Byte

if (r (7:0) = 0) then (Z < 1 else Z < 0); next

1062DD

if (N XOR C) then (V < 1 else V < 0);

Db <1
ASL

1< D’ (15) cat D’ 13:0) cat O; next

Arithmetic

Shifts contents of destination left one place, but sign bit -

remains in most significant place.

Shift Left

C < D {14); next

'Bit 14 loaded into C.

0063DD

N <

Set N if result negative.
Set Z if result 0.

{15);

if (r (15:0)=0) then (Z < 1 else Z < 0); next
if (N XOR C) then (V < 1 else V < 0);

D<«r

Put result in destination.

ASLB

r < Db’ (7) cat Db’ (5:0) cat O; next

Same as ASL, except byte.

Arithmetic

C < Db (6); next

Shift Left

N <1 (7);

Byte

if (r (7:0)=0) then (Z < 1 else Z < 0); next

1063DD

Load
V with exclusive-OR of N and C after shift completed.

if (N XOR C) then (V < 1 else V < 0);
Db <1

MARK

SP < SP + (2 X df (5:0); next

Adjusts stack pointer by the number of words indicated in the

PC < R[5]; next

Puts old PC (RY) into PC.

R[S5] < Mw [SP];

Contents of old R5 popped into RS.

Mark

0064nn

low 6 bits of the instruction (2 X nn locations).

SP <SP + 2

SXT

if (N=1) then (r <15:0) < -1 else r ¢{15:0)« 0); | If the N bit is set, then - 1 is placed in the destination operand.

Sign Extend

Otherwise, 0 is placed in the destination operand.

destination

if (r {15:0>=0) then (Z < l-else Z < 0);

Set Z if result is O.

0067DD

D <r

JMP

PC < D address

D address is computed in a fashion similar to D.

Result is byte swapped of D negative?

Jump

0001DD

SWAB

r< D’ (7:0) 0 D’ 15:8); next

Swab Bytes

N <

Destination

(r<7:00=0)>(Z <« 1 else Z=0);

Zero?

0003DD

V< 0;

Clear V, C

C<0;
D<r

Transmit result to D.

Table 4-5

- Instruction

ISP Notation

Description

and Op Code

XOR

r < R[sr] XOR D’; next

The exclusive-OR of the register and the destination operand

Exclusive-OR

074RDD

is stored in ti.¢ destination address.

if (r = 0) then (Z < 1 else Z < 0);
N < r(15);

V «0;

Set Z if result is O.
Set N if result is negative.

Clear V; no overflow possible.

Rfsr] «<r

)

SOB

r < Rfsr] -1;next

Subtract

R{sr] «r;

One and

if (r # 0) then (PC < PC -2 X df {(5:0))

Branch

077R offset

Decrement register by 1. If result is not equal to G, branch.

|
-

Subtract 2 X 6-bit offset from PC to get new PC.

Table 4-6
|
Mnemonic

Branch Instructons

ISP Notation

lnstruction

Description

and Op Code

| Always branch.

PC
< PC + sign-extend (instr (7:00 X 2)

Branch

Unconditional

Eight least-significant bits of instruction are multiplied times 2

0004 loc

and added to PC with sign extended.

if (Z = 0) then (PC « PC + sign-extend |

Branch if Z is 0.

BEQ

if (Z = 1) then (PC < PC +.sign-extend

Branchif Zis 1.

Branch on

(instr (7:0) X 2))

BNE

PC changed as follows:

(instr {7:0) X 2))

Branch
Not Equal

00101oc

Equal

0014 loc

if (N equiv V) then (PC < PC + sign-extend

BGE

| (instr <7:0) X 2))

Branch if

Branch if N is equivalent to V.

Greater than

or Equal (zero)
0020 loc
BLT

if (N XOR V) then (PC < PC + sign-extend

Branch on

(instr (7:0) X 2))

Branch if exclusive-OR of N and V equal 1.

Less Than
0024 loc

BGT

if (~Z & (N equiv V)) then (PC < PC + sign-

Branch on

extend (instr (7:0) X 2))

Branch if Z equals 0 and N equals V.

Greater Than
0030 loc
BLE

if (Z OR (N XOR V)) then (PC <« PC + sign-

Branch on

extend (instr {7:0) X 2))

‘Branch if Z equals 1 or if exclusive-OR of N and V equals 1.

Less Than
or Equal (zero)

0034 loc
BPL

if (N = 0) then (PC < PC + sign-extend

Branch on

(instr (7:0) X 2))

Branch if N is 0.

Plus
1000 loc

BMI

Branch on

Branch if Nis 1.

if (N =1) then (PC < PC + sign-extend
(instr (7:0) X 2))

Minus

1004 loc
BHI

if ~(C OR Z) then (PC « PC + sign-extend

Branch on

(instr (7:0) X 2))

‘Branch if C and Z are 0.

Higher
1010 loc

4-13

Table 4-6 (Cont)
‘Branch Instructions
Mnemonic

Instruction

ISP Notation

Description

~and Op Code

BLOS

if (C OR Z) then (PC < PC + sign-extend

Branch on

(instr (7:0) X 2))

Branch if C or Z is 1.
|

Lower or
Same
1014 loc

BVC

if (V =0) then (PC < PC + sign-extend

Branch on

(instr (7:0) X 2))

Branchif Vis 0.

Overtlow
Clear

BVS

if (V = 1) then (PC < PC +sign-extend

Branch on

(instr (7: X 2))

{

Branchif Vis 1.

Overflow Set
1024 loc

BHIS

if (C = 0) then (PC < PC + sign-extend

Branch on

(instr 7:0) X 2))

Branch if C is O.

Higher or
Same

BLO

if (C=1) then (PC < PC +sign-extend

Branch on

(instr 7:0) X 2))

Lower

Branchif Cis 1.

1034 loc
JSR

SP <~ SP - 2; next

Jump to

Mw [SP] < R[sr];

Subroutine

R[sr] < PC

004RDD

PC < D address

RTS
Return from

Subroutine

Push contents of R onto stack.

|
|

|
-

;

PC < R[dr];

|
Store current PC in R.

Load subroutine address into PC.
Load contents
of R into PC. |

| R[dr] < Mw |[SP];

Pop stack pointer into R.

| SP <SP + 2

00020R

4-14

\W‘

1030 loc

Table 4-7

Miscellaneous Instructions
Mnemonic

Description

ISP Notation

Instruction
and Op Code

HALT

Halt

Processor halts with console in control. No activities or

Off < true

instructions can be executed until a console actions restarts
the processor.

000000

Wait < true

Processor relinquishes bus and waits for an external interrupt :

10T

SP < SP -2; next

Push PS onto Stack.

I/O Trap

Mw [SP] < PS;

WAIT
Wait

000001

000004

Push PC onto stack.

SP < SP -2; next
Mw [SP] < PC;

Get new PC from location 20.

PC < Mw [20];
RESET
Reset

PS <~ Mw [22]

Get new PS from location 22.

Init < 1;
Delay (20 milliseconds); next

Send INIT on Unibus for 20 ms.
|

External Bus | Init< 0
000005

BPT

Break Point
Trap
000003

RTI

SP < SP -2; next

Place

MW [SP] < PC;

PC on stack

< MW [164]
PS

fromM [14],M [16]

PC < Mw [SP];

Pop PC off stack.

PS and

MW ['SP] < PS;
SP « SP - 2; next

take new PC and PS

PC < MW [144];

Return from

SP < SP + 2; next

Interrupt

PS <~ Mw [SP};

000002

SP <SP + 2

(RTI permits trace trap.)

RTT

PC < Mw [SP];

Pop PC off stack.

Interrupt

PS < Mw [SP];

Pop PS off stack.

Return from |} SP <« SP + 2; next
000006

SP < SP + 2

(RTT inhibits trace trap.)

EMT

SP < SP -2; next

Push PS onto stack.
|

Emulator Trap] Mw [SP] < PS;

Push PC onto stack.

104 Code

SP < SP -2; next

(104000 —

Mw [SP] <« PC;

PC < Mw [30];
PS < Mw [32]

Get new PC and PS from locations 30 and 32.
|
|

TRAP

SP < SP -2; next

Push PS onto stack.

Trap

Mw [SP] < PS

104 Code

SP < SP -2; next

(104400 —

Mw [SP] « PC;

104377)

104777)

Push PC onto stack.

Get new PC and PS from locations 34 and 36.

PC < Mw [34];
PS < Mw [36]

4-15

Table 4-8
Condition Code Operators
Mnemonic

Instruction

ISP Notation

Description

and Op Code

CLC

Clear C

if (instr 4) =0 & instr{0) = 1) then C < 0
~

When bit 4 of the instruction is O bits 3, 2, 1, and O clear

corresponding bits in PS.

000241

CLV

if (instr (4) = 0 & instr (1) = 1) then V < 0

Clear V

000242

CLZ

if (instr (4> =0 & instr (2> =1) then Z < 0

Clear Z
000244

CLN

if (instr 4)=0& instr (3)=1) then

N« 0

Clear N
000250

Z <0;

000257

N < 0)

SEC

if (instr (4> = 1 & instr (0) = 1) then C < 1 |

When bit 4 of the instruction is 1, bits 3, 2, 1, and O set corre-

Set C

sponding bits in PS.

000261
SEV

|
if (instr 4)=1 & instr {I>)=1) then V< 1

Set V
000262

SEZ

if (instr (4) = 1 & instr () = 1) then Z < 1

Set Z
000264

SEN

if (instr 4) =1 & instr (3> =1) then N < 1

Set N

000270

SCC

if (instr (4:0) = 37) then

Set all

(C<1;

Condition

V<1,

Codes

Z <1;

000277

N+« 1)

4-16

/,v

V < 0;

Codes

\’:‘“—/’

(C<0;

Condition

if (instr 4) = 0 & instr {3:0) = 17) then

Clear all

- CCC

4.2.3 Extended Instruction Set

Additional instructions are available if certain processor options are added to the basic system. These instructions

-are:

KE11-E Extended Instruction Set (EIS) — These instructions have the same format as double-operand

instructions and provide an increased arithmetic capability to the basic instruction set. These
instructions are: MULtiply (MUL), DIVide (DIV), Arithmetic SHift (ASH), and Arithmetic SHift
|
|
Combined (ASHC).
The EIS instructions are listed in Table 4-9.

KE11-F Floating Instruction Set (FIS)— These instructions permit arithmetic operations in
floating-point notation. The instructions are: FADD, FSUB, FMUL, and FDIV (Floating point
ADDition, SUBtraction, MULtiplication, and DIVision).

- The FIS instructions are listed in Table 4-10.

KT11-D Memory Management — This option provides expanded address capability for the PDP-11/40. It
allows the PDP-11/40 to treat sections of memory differently (user mode and kernel mode). Two

instructions are also provided: Move From Previous Instruction (MFPI) and Move To Previous

Instruction (MTPI). The MFPI instruction is provided to allow interaddress space communication when

the PDP-11/40 is using the memory management option. The MTPI instruction determines the address

of the destination operand in the current address space.

Note that in the table, the move from previous instruction (MFPI) and the move to previous instruction

(MTPI) are listed as MFPI/D and MTPI/D. This is because in the PDP-11/40,” MFPI and MFPD

instructions are executed identically and the same applies to the MTPI and MTPD instructions.
The KT11-D instructions are listed in Table 4-1 1.

4-17

Table 4-9
Extended Instruction Set (EIS)
Mnemonic

Instruction

ISP Notation

Description

and
Op Code

MUL

1(31:0) < D’ X R[sr] ;next

Multiply contents of source register and destination to form

Multiply

070RSS

32-bit product.

if (r (31:0) = 0) then (Z < 1 else Z < 0);

Set Z if product is 0.

N <r{31D;

Set N if product is negative.

if 1 31:00 < —215) OR (r (31:0) = A )then

| Set Cif product is more than 16-bit result

(C« 1else C<0);

V <« 0;

No overflow possible; clear V.

R[sr] <15:0) <1 (31:16); next

Store the high-order result in R.

R[sr OR 1] (15:0) <1 (15:0);

Store the low-order resultin succeeding register if Ris even
number. Otherwise, store in R.

DIV

r1 (31:0) < Rsr] cat R[sr OR 1]/D’; next

Divide

071RSS

The 32-bit dividend, R, R OR 1, is divided by source operand

D. R must be even number.

12¢15:0) < R[sr] cat R[sr OR 1] -(r1 X D);

next N < r1(15);

Determine the remainder.

Set N if quotient is negative.

if (r1 (31:0) = 0) then (Z < 1 else Z <« 0);

Set Z if quotient is 0.

if ‘(D = Q) then (C < 1 else C < 0);

Set C if divide by 0 attempted.

if (r1 {15 =0) & (r1 31:16) # 0)

Set V if divisor
is 0, or if the result is too large to be stored

as a 16-bit number.

if (r1 (15)=1)
& (r1 (31:16)
# -1)

if (D

ASH
Arithmetic

=0) then (V<1 else V < 0);

Risr] < r1<15:0)

Store quotient in R.

Rfsr OR 1] <12

Store remainder inR OR 1.

1(79:0) < sign-extend (R[sr] <15:00 X 2 %

Contents of R are shifted NN places right or left, where NN

(D’ (5:0) + 32) mod 64); next

Shift

072RDD

equals the six low-order blts of DD.
NN =-32to +31.

Risr] {15:0) < 1 47:32); next

Store resultin R.

if (R[sr] =0) then (Z < 1 else Z < 0);

Set Z if result is 0.

if (R[sr] (15 = 0) & (r (79:48)% 0) OR

Set V if sign of register changed during shift.

(R[sr] {15)=1) & (r (79:48) # - 1)) then
(V< 1else V< 0);
N < R[sr] (15

Set N if result is negative.

if (D(5)=1) then C < r{31)

Load C from last bit shifted out of register.

if (D (5)=0) & (D (5:0) # 0) then
C<r148);

if (D{:00=0)thenC <0

4-18

Table 4-9 (Cont)

Extended Instruction Set (EIS)
Mnemonic

Instruction

ISP Notation

and Op Code

Description
-

ASHC

r ¢95:0) < sign-extend (R[sr] cat R[sr OR 1] X | Contents of R, and R ORed with 1, form a 32-bit word (R =

Arithmetic

2 1(D’(5:0) + 32) mod 64); next

31:16, ROR 1 = 15:0) that is shifted right or left NN places,

Shift

specified by six low-order bits of destination operand, DD.

Combined

R[sr] < r{63:48); next

073RDD

R[sr OR 1] <1 (47:32); next

Store results in R and

if (R[sr] cat R[sr OR 1] =0) then (Z « 1 else

ROR 1.

Set Z if result is O.

Z<0);
N < R[sr] (15);

Set N if result is negative.

if (r (63)=0) & (r(95:64) # 0) OR

Set V if sign bit changes during the shift.

if (r (63)# 0) & (1 (95:64) # - 1) then

(V< 1else V<« 0);
if (DS)=1)thenC <« r{31);

Load C with high order if left shift.

if (D (5)=0) & (D (5:0) # 0) then

Load C with low order if right shift.

C <164,
if (D{G:0)=0)thenC<«0

XOR

r < R[sr] XOR D’; next

Exclusive-OR

074RDD

Otherwise, clear C.

The exclusive-OR of the register and the destination operand
»

is stored in the destination address.

if (r =0) then (Z < 1 else Z < 0);

Set Z if result is 0.

N <1 (15);

Set N if result is negative.

V <« 0;

Clear V; no overflow possible.

R[sr] <r
SOB

r < R[sr] - 1; next

Subtract

R[sr] < r;

One and

if (r # 0) then (PC < PC -2 X df (5:0)

Decrement register by 1. If result is not equal to 0, branch.

|
Subtract 2 X 6-bit offset from PC to get new PC.

Branch

077R offset

4-19

Table 4-10
-Floating Instruction Set (FIS)
The following abbreviations are used in this table:

FSP = Floating Stack Pointer
FAC =(31:00)=FSP + 4 <15:00) (J FSP + 6 (15:00»

FAS’ (31:00) = FSP(15:00) 0 FSP + 2 (15:00)

Mnemonic
Instruction

ISP Notation

FADD

Description

and Op Code

FR < FAC + FPS’; next

~ Move sum of accumulator and source to temporary register.

Floating ADD

07500R

(FR<XUL) V (FR > XLL))~

(FAC < FR

Store result if no underflow or overflow, NO OP otherwise.

else NO OP); next

(FAC<0) V(FAC<XLL))~

Negative?, underflow?

(N < 1 else N« 0);

(FAC=0)=>(Z
<« 1lelse Z<0);

Zero?

((FAC> XUL) V (FAC > XLL)) »

Overflow?, underflow?

(V < 1else V< 0);

C<0
FSUB

FR < FAC - FPS’; next

Floating

Subtract

07501R

Clear Carry
Move difference of accumulator and source to temporary

(FR<XUL)
V (FR > XLL)) -

Store result if no underflow or overflow, NO OP otherwise.

(FAC < FR else NO OP); next

(FAC<0)

V(FAC<XLL))~

“

Negative?, underflow?

(N < 1 else N« 0);

(FAC=0)—>(Z < lelse

Z<+0);

Zero?

(FAC > XUL) V(FAC > XLL)) ~»

Overflow?, underflow?

(V< 1else V< 0);
C<0

Clear Carry

4-20

Table 4-10 (Cont)
Floating Instruction Set (FIS)
‘Mnemonic
Instruction

ISP Notation

Description

and Op Code
FMUL

Move product of accumulator and source to temporary

FR
< FAC * FPS’: next

Floating

Multiply

07502R

' Store result if NO overflow or underflow, NO OP otherwise.

((FR < XUL) V (FR > XLL)) -

(FAC < FR else NO OP); next

((FAC <0V (FAC < XLL))~

Negative?, underflow?

(N < 1 else N < 0);
(FAC=0)—>(Z
<« | else Z<+0);

Zero?

((FAC > XUL) V (FAC > XLL)) >

Overflow?, underflow?

(V< 1else V<0);

C+0

FDIV

Clear Carry

(FPS=0)=C <« |

Floating

Divide

(FPS # 0) - FR < FAC / FPS’: next

Move result of division to temporary register.

07503R

((FR < XUL) V (FR > XLL)) -

Store result if NO overflow or underflow, NO OP otherwise,

(FAC < FR else NO OP);

((FAC<0)V(FAC>XLL)) ~

Negative?, underflow?

(N < 1 else N« 0);

(FAC=0)~
(Z < 1 else Z < 0);

Zero?

((FAC>XUL) V (FAC > XLL)) ~

(V< 1else V<0):

Overflow?, underflow?

(FES=0)~>
(C < 1 else C < 0)

Divide by Zero?

4-21

Table 4-11

Memory Management Instruction Set
Mnemonic

Instruction

ISP Notation

Description

and Op Code

4.3

MFPI/D

r < D’; next

Get destination operand from previbus I'space.

Move From

SP < SP-2;

Push stack.

N <1 (15);

Instruction

if (r{15:0)=0) then (Z < 1 else Z < 0);

Space

V<0,

Clear V.

0065DD

Mw [SP] «

Put operand into current address space.

MTPI/D

r < Mw [SP];

Get data from current stack.

Move To

SP <SP + 2;next

Pop stack.

N <1 ({15);

Instruction

if (r {15:0)=0) then (Z < 1 else Z < 0);

Set N if negative.
Set Z if 0.

Set N if negative.

Set Z if 0.

Space

V<« 0;

Clear V.

0066DD

D’ <r

Move to previous I space destination.

PROCESSOR GPTIONS

The basic KD11-A Processor contains space for installing six processor options. In addition, there is a Small
Peripheral Controller (SPC) slot that is usually used for an input terminal control (such as the DECwriter or Teletype

interface) but that also can be used for a variety of options dependent on the user’s individual requirements. The
specific slot, or slots, allocated for each option is listed in Table 4-12 and shown in Figure 6-3.
The available processor options are:

KE11-F Floating Instruction Set (FIS)

KJI11-A Stack Limit Register

KTI11-D .Memory Management

. e.

a. | KE11-E Extended Instruction Set (EIS)

KW11-L Line Tirr.le.Clock

KM11-A Maintenance Console

Small Peripheral Controller (variable option)

The above options can be used in any combination as they function independently with two exceptions. The

KE11-F (FIS) option physically requires the KE11-E (EIS) option, and software for the KT11-D option requires the
KJ11-A option. Each option is discussed separately in subsequent paragraphs which include a general descnptlon
specifications, and a reference to more detailed documents.
(

4-22

Table 4-12
Location of Processor Options

Option

| Section(s)

Slot

KEI 1-E Extended Instruction Set (EIS)

A—F

KE11-F Floating Instruction Set (FIS)

A-D

KJ11-A Sfack Limit Register

A—F

KT11-D Memory Management

KW11-L Line Time Clock
KM11-A Maintenance Console
e

For maintenance of the basic

processor

For maintenance of the KT11-D

and/or EIS and FIS options
Small Peripheral Controller

4.3.1

C—F

KE11-E Extended Instruction Set (EIS) Option

The KE11-E Extended Instruction Set Option is a processor option that expands the basic PDP-11/40 instruction set
to include: MULtiply (MUL), DIVide (DIV), Arithmetic SHift (ASH), and Arithmetic SHift Combined (ASHC).
The option permits multiplication and division of signed 16-bit numbers and arithmetic shifting of signed 16-bit or
32-bit numbers. Condition codes are set on the result of each instruction.

The KE11-E (EIS) option is a single hex (six section) module (M7238) that plugs directly into slot A02-FO02 of the
processor backplane. The option functions as an extension of the basic KD11-A data paths, microbranch control,

and control ROM. The basic processor timing is not degraded when this option is used. The NPR latency is not

\“‘-n')'/

affected when the instructions are being executed. Interrupts are serviced at the end of each instruction in the

standard manner.
There are no addressable registers in the KE11-E option. All operands are fetched from either core memory or from

the general processor registers and the result of each operation is stored in the general registers.
The MUL instruction uses the contents of the effective addresses specified by the destination register and the source
register as 2’s complement integers which are multiplied. The result is stored in the source register and, if even, the

low-order result in the succeeding register. If the source register address is odd, only the low-order product is stored.
The MUL instruction multiplies full 16-bit numbers for a 32-bit product.

The DIV instruction permits a 32-bit 2’s complement dividend in the destination registers (R and R+1) to be divided

by a 16-bit divisor in the source register.

A 16-bit quotient is left in R and the 16-bit remainder is left in R+1. The

sign of the remainder is always the same as the sign of the dividend unless the remainder is zero. Overflow is

indicated if more than 16 bits are required to express the quotient. In this case, the instruction is aborted, the

overflow condition code is set, the expansion processor status (EPS) word is loaded into the processor PS register,
and the program branches to a service routine. If the source register is zero, indicating divide by 0, an overflow is

indicated.

4-23

When the ASH instruction is used, the contents of the selected register is shifted right or left the number of places

specified by a count. This shift count is a 6-bit, 2’s complement number which is the least significant 6 bits of the
destination operand. If the count is positive, the number is shifted left; if it is negative, the number is shifted right.
This allows for shifts from 31 positions left to 32 positions right (+31 to -32). A count of zero causes no change in
the number.
When the ASHC instruction is used, the contents of a register (R) and the contents of another register (R+1) are
treated as a single 32-bit word. Register R+1 represents bits 0—15, register R represents bits 16—31. This 32-bit word
is shifted right or left the number of places specified by a count. This shift count is the same as that described for

the ASH instruction and permits shifts from +31 to-32. If the selected register (R) is an odd number, then R and
R+1

are the same. In this case, a shift becomes a rotate and the 16-bit word is rotated the number of counts

specified by the shift count (up to 16 shifts).
Specifications for the KE11-E option are listed in Table 4-13. A detailed description of this option is given in the
KE11-E and KE11-F Instruction Set Option Manual, EK-KE11E-TM-002.

Table 4-13

KE11-E (EIS) Specifications
Function

Instructions

Description

MULtiply (MUL)

DIVide (DIV)

Arithmetic SHift (ASH)
Arithmetic SHift Combined (ASHC)

Operations

Multiplication and division
of signed 16-bit numbers.
'Arithmétic shifting of signed 16-bit or 32-bit numbers.

Registers

None in option. Operands fetched from core or general
processor registers.

Timing (approximate)

MUL =9.5 us
DIV =10.5 us
ASH
= 3.4 ps plus address calculation time plus 300 ns
times absolute value of shift count.
- ASHC = 3.8 us plus address calculation time plus 300 ns

times absolute value of shift count.

Size

4.3.2

Single hex module (M7238)

KE11-F Floating Instruction Set (FIS) Option

'Ihe KE11-F Floating Instruction Set Option enables the KD11-A Processor to perform arithmetic operations usmg
floating point arithmetic. The prime advantage of this option is increased speed without the necessity of writing
complex floating point software routines. The KE11-F performs single-precision operations. The KE11-F option
cannot be used unless the KE11-E (EIS) option has been installedin the system.

4.24

The KE11-F (FIS) option is a single quad module (M7239) that plugs directly into slot A01-D0O1 of the processor
backplane. If a BR is issued before the instruction is within approximately 8 us of completion, the floating point

instruction is aborted. In this event, the Program Counter (PC) points to the aborted floating point instruction,
making the instruction the next instruction to be performed by the program. The NPR latency is not affected when

floating point instructions are being executed. Interrupts are serviced at the end of each instruction in the standard
manner.

The FIS option provides four sp»ecial instructions: Floating point ADDition (FADD), Floating point SUBtraction
(FSUB), Floating point MULtiplication (FMUL), and Floating point DIVision (FDIV).

Floating point representation of a binary number consists of three parts: an exponent, a mantissa, and the sign of
the mantissa. The mantissa is a fraction in magnitude format with the binary point positioned between the sign bit
and the most significant bit. If the mantissa is normalized, all leading Os are eliminated from the binary
representation; the most significant bit is thus a 1. Leading Os are removed by shifting the mantissa left; however,
each left shift to the mantissa must be followed by a decrement of the exponent value to maintain the true value of
the number. The exponent value represents the power of 2 by which the mantissa is multiplied to obtain the value to
be used.

For FADD or FSUB operations, the exponents must be aligned (or equal). If they are not, the mantissa with the
smaller exponent is shifted right until they are. Each right shift is accompanied by incrementation of the exponent

value. Once the exponents are aligned (equal), the mantissa is added or subtracted. The exponent value indicates the

number of places the binary point is to be moved
in order to obtain the actual representation of the number.
For FMUL instructions, the mantissas are multiplied and the exponents are added. For FDIV instructions, the
mantissas are divided and the exponents are subtracted.

The KE11-F option stores the exponent in excess 2003 notation. Therefore, values from -128 to +127 are

represented by the binary equivalent of 0 to 255 (octal 0—377). Mantissas are represented in sign magnitude form.

The binary radix point is to the left. The result of the floating-point operatlons is always rounded away from zero,
increasing the absolute value of the number.

If the exponent is equal to 0, the number is assumed to be O regardless of the sign bit or fraction value. The
hardware generates a clean 0 (32-bit word all zeros) in this instance.
Specifications for the KE11-F option are listed in Table 4-14. A detailed description of this option is given in the

KE1I-E and KE 11-F Instruction Set Option Manual, EK-KE11E-TM-002.

4.3.3 KJ11-A Stack Limit Register Option
The KJ11-A option enables variation of the limits of the stack area. In the basic PDP-11/40 System, the first 4004
memory locations (0 through 377g5) are reserved for storage of trap and interrupt vectors. This area of memory
should be accessed only when an interrupt subroutine is to be executed or a trap error occurs such as a power

failure. Normally, memory is arranged such that the system stack area is above this vector area. However, to prevent
inadvertent entrance of the stack into the vector area, protection is provided. In the basic KD11-A Processor, this

protection is provided by a fixed boundary (400g), detection circuit. The KJ11-A Stack Limit Register Option
provides a programmable boundary detection circuit. Note that the processor response for a yellow or red zone
boundary violation is unchanged; only the location of the boundary is variable.

Specifications for the KJ11-A option are listed in Table 4-15. A detailed description of this option is presented in
the KD11-A Processor Maintenance Manual, EK-KD11A-MM-001.

4-25

Table 4-14

KE11-F (FIS) Specifications
Function

Description

Pferequisite

KE11-E Extended Instruction Set Option

Instructions

Floating point ADDition (FADD)
Floating point SUBtraction (FSUB)
Floating point MULtiply (FMUL)
Floating point DIVide (FDIV)

Operations

Single precision, floating point addition, subtraction, multiplication, and
division of 24-bit numbers.

Registers

None in option. Operands fetched from core.

Timing

Time = Basic Time Plus Binary Point Alignment Time Plus Normalization

INSTR

Time

Basic Time#*
(us)

‘Binary Point
Alignment Time

Normalization Time
Per Shift

(us)
FADD

18.78

(us)

0.30

0.34

FSUB

19.08

0.30

FMUL

29.00

—

0.34

FDIV

46.27

———

0.34

‘Size

0.34

Single quad module (M7239)

*Basic instruction times for FADD and FSUB assume exponents are equal or differ by one.

4.3.4

KT11-D Memory Management Option

The KT11-D Memory Management Option provides the capability to expand
the 32K word addressing of the
KD11-A Processor to 128K words and to enhance the use of multi-user, multi-program systems. A timesharing
environment is created by providing two operating modes: kernel and user. These modes can operate with or

without relocation and protection. Mode selection is made by using an expanded KD11-A processor status word.
The KT11-D option basically performs four functions:
a.

Expands the basic 32K word address capability to 128K words.

Provides address space with memory relocation and protection for multi-user timesharing systems.

Implements the separate address spaces for the kernel and user modes of operation.

Provides memory management information
for use of memory in multi-user, multi-program systems.

Specifications for the KT11-D Memory Management Option are listed in Table 4-16. A detailed description of this
option is given in the KT11-D Memory Management Option Manual, DEC-11-HKTDA-B-D.

4-26

- Table 4-15
KJ11-A Specifications

Function
Register

Description
8-bit

stack limit

(bits

15—08) addressable by console

processor, but not by any bus device.

777774 (word addressing)

777775 (byte addressing)
Stack Limit

Programmable; if register is all Os, then:
000—337 = red zone
340—-377 = yellow zone

Yellow Zone Violation

Occurs if the stack operation’s address is equal to or less than the stack
limit address by 16 words or less. The operation is completed and then
a TRAPis executed.

Red Zone Violation

Occurs if the stack operation’s address is less than the stack limit

address by more than 16 words. The operation is aborted (fatal stack
error), a stack vector exists at address 4, and a bus error TRAP occurs.
The old PS and PC are pushed into locations 2 and 0; the new PC and
PS are taken from locations 4 and 6.
Initialized Stack Limit

The initialized state of the KJ11-A option is 377; this is equivalent to

the fixed stack limit of a PDP-11/40 System without the KJ11-A
option.

One Single-height module.

Size

4.3.5

KWI1I-L Line Time Clock Option

The KW11-L Line Time Clock option provides a method of referencing real intervals. This option generates a
repetitive interrupt request to the processor. The rate of interrupt is derived from the ac line frequency, either 50 Hz

or 60 Hz. The accuracy of the clock period, therefore, is dependent on the accuracy of this frequency source.
The KW11-L option can be operated in either an interrupt or noninterrupt mode. When in the interrupt mode, the

clock option interrupts the processor each time it receives a pulse from the line frequency source. In the
noninterrupt mode, the clock option functions as a program switch that the processor can examine or ignore. Mode

selectionis made by the program.

Specnfica‘uons for the KW11-L Line Time Clock Option are listedin Table 4-17. A detailed description of this option
is given in the

KW11-L Line Time Clock Manual, EK-KW11L-TM-002.

4-27

Table 4-16

KT11-D Specifications

Description

Function

Memory Expansion

Expands PDP-11/40 memory address capability up to 124K words.

Interface

Address line outputs compatible with PDP-11 Unibus.

Timing

Timing derived from KD11-A Processor.

Delay |

Adds 150 ns to every memory reference when installed.

Operating Modes

Ker;lel and user.

Available Pages

Provides eight 4K word pages for each mode.

Page Length

A page can vary in length from one 32-word block up to 128 32-word

blocks. Maximum page lengthis 4096 words.
Program Capacity

Fight 4096-word pages accommodate 32K word programs.

Size

Single hex module (M7236).

Table 4-17

KW11-L Specifications

Function

| Register
-

Description

2-bit status register
bit 06 — interrupt enable
bit 07 — interrupt monitor

777546

Vector Address

100

Mode Control

bit 06 set — interrupt mode

bit 06 clear — non-interrupt mode
Monitor Function

Bit 07 can be used to serve as a partial check on the origin of the interrupt
vector.

Interrupt

Same as line frequency; 50 or 60 Hz.

Priority Level

BR6

Size

Single-height module (M787) that mounts in KD11-A Processor slot F03.

4-28

4.3.6

KM11-A Maintenance Console Option

The KM11-A Maintenance Console (also referred to as the maintenance module) is a 2-module set contalmng 28
indicator lights and 4 switches used to monitor and control functions during maintenance tests.

The functions monitored by the option depend on which processor slot the module is installed in. Different overlays

are provided to indicate the function being tested. The module is installed in processor backplane slot FO1 when
testing the KD11-A Processor and is installed in slot EO1 when testing the KT11-D or KE11-E, F options.

A detailed description of the maintenance console is provided'in the KD11-A Process_or Maintehanée Manual,
EK-KD11A-MM-001.

4.3.7 Small Peripheral Controller

Processor backplane slot 09, sections C—F, permit installation of any Small Peripheral Controller option. This slot is
normally used to install the controller for the PDP-11 /40 System input/output dev1ce but may be used for any
Small Peripheral Controller, if desired.

The standard controllers for system I/O devices are:

DL11 Asynchronous Line Interface — the standard PDP-11/40 controller used for elther the LA30-S
DECwriter or for the ASR 33 Teletype unit.

LC11 DECwriter Control — a controller used when the LA30-P DECwnter is used as the system I/O
device.

KLI11 Teletype Control — an earlier version of the Teletype control whichis used only with the ASR 33
Teletype unit.

A brief description of the DL11 is given in Paragraph 1.3.7. Detailed descriptions of all -th’r_e,e controlleré are included
<

in related maintenance manuals listed in Table 1-2.

4-29

CHAPTER 5

SYSTEM PERIPHERALS AND OPTIONS

5.1

SCOPE

This chapter lists the periphérals and options that may be used with the PDP-11/40. Functional and detailed

~ descriptions of these units are contained in other documents, listed in Paragraph 5.2.
5.2 PERIPHERALS AND OPTIONS

Table 5-1 lists the PDP-11/40 peripherals and options. The PDP-1l Peripherals Handbook contains functional
descriptions of these units. Detailed descriptions are provided in associated equipment maintenance manuals. The
handbook is provided with each system and each peripheral and option delivered is accompanied by its own
maintenance manual.

Table 5-1

PDP-11/40 Peripherals and Options

~ Function
Input/Output

Equipment
Teletype

PC11 High-Speed Reader/Punch
LP11 High-Speed Line Printer

CM11/CR11 Card Reader
LA30 DECwriter

Magnetic Tape Storage
-

Display

TC11/TUS56 DECtape |
TM11/TU10 Magtape

‘

VTO1A Storage Display
VRO1A Oscilloscope

VR 14 Point Plot Display

VTO5 Alphanumeric Terminal
RTO1 DEClink Terminal

Disk Storage
|

RC11/RS64 DECdisk Memory
RF11/RS11 Disk and Control
RK11-C/RK02, RK03, RK05 DEC Pack
Disk Cartridge System

5-1

Table 5-1 (Cont)

PDP-11/40 Peripherals and Options
Function

Equipment

Bus Extension

DB11 Bus Repeater
DT11-A, DT11-B Bus Switches

Communications

DC11 Asynchronous Line Interface
DN11 Automatic Calling Unit Interface
DP11 Synchronous Interface

DM11 Asynchronous 16-Line Single Speed Multiplexer
DL11 Full Duplex 8-bit Asynchronous Line Interface

DATA Acquisition and Control

AFC11 Low Level Analog Input Subsystem

ADO1D Analog to Digital Conversion Subsystem
AA11D Digital to Analog Conversion Subsystem

5-2

CHAPTER 6

EQUIPMENT MOUNTING AND POWER

6.1

SCOPE

This chapter provides detailed information on the PDP-11/40 equipment mounting and power system.
The BA11-FC Mounting Box is basic to PDP-11/40 equipment mounting and is discussed in Paragraph 6.2. System
unit allocations as well as processor and basic memory slot allocations are noted for the basic box. This information

covers mounting space within the basic system cabinet and in adjacent cabinets (Paragraph 6.3).

The power system is duscussed in Paragraph 6.4 and consists of the 861 Power Controller (Paragraph 6.4.1), the

H742 Power Supply (Paragraph 6.4.2), two H744 +5V Regulators (Paragraph 6.4.3), two H745 -15V Regulators
(Paragraph 6.4.4), a power distribution panel, and interconnection and distribution cabling. Power controller
interconnection, power system cable harnesses, and dc power distribution are discussed in Paragraphs 6.4.5, 6.4.6,

and 6.4.7, respectively.

6.2 SYSTEM MOUNTING BOX

The major components of the PDP-11/40 System, with the exception of the power system and console I/O device
are mounted in a single BA11-FC Mounting Box Space for additional memory and/or peripheral interfaces is also
provided within this mounting box.

The BA11-FC Mounting Box is mounted in a standard DEC H960-C Cabinet, shown in Figure 6-1. The box is
mounted on chassis slides that enable it to be pulled out for maintenance and/or installation of logic modules; the

power supply, however, remains within the cabinet. Cooling fans are mounted on top of the box to provide proper
cooling of the logic elements within the box. The KY11-D Programmer’s Console is located on the front of this box.

The mounting box is capable of holding nine system units or equivalents. Each system»unit casting contains four
slots for mounting logic modules. An alternate double system unit contains nine slots because it has no center
casting. This double system unit is used for the KD11-A Processor and MF11-L Memory.

Allocation of logic within the box is shown in Figure 6-2. A double system unit (with nine slots) is used for the
processor and processor options. Another double system unit is used for the MF11-L Core Memory, which includes
three modules to provide a basic 8K memory. This leaves space for five additional system units (or equivalents) for

additional memory and/or peripheral interfaces. Note that core memory should always be placed as close to the
processor as possible. The basic mounting box provides mounting space and cooling for these additional (expansion)
units. Module allocations for the processor, and memory, are covered in Paragraphs 6.2.1 and 6.2.2, respectively.

Programmer’s console mounting is coveredin Paragraph 6.2.3.

Revision 1

6-1

January 1974

/i 7

7] |\ AN

z w= ao = w @
DISTRIBUTION

PANEL

(1) CABINET
FAN

HOUSING
s

=
s
7

72)

72
T 7L L
(777T

7L L
77T
i
77

S77777
2L
V4

2055555

BA11-FC MOUNTING
BOX-NEW STYLE

e«

H960 -C

CABINET

CA :115Vac

CB: 230 Vac

CABLE SUPPORT
AND

CABLE

STRAP

HARNESS

H742
POWER SUPPLY
WITH REGULATORS
BA11-FC
MOUNTING

OLD

BOX

STYLE

UPPER LOGIC FANS
KY11-D

CONSOLE

FAN POWER
DISTRIBUTION
BOARD (OLDER

MODEL
861 POWER
CONTROLLER
861-C:115VAC
861~ B:230VAC

ONLY)

MOUNTING SPACE
FOR ADDITIONAL
SYSTEM UNITS

MF11

L 8K MEMORY KD11-A

PROCESSOR
11-2308

Figure 6-1

PDP-11/40 System Cabinet

Revision 1

January 1974

6-2

MFi1-L 8K
CORE MEMORY
DOUBLE SYSTEM
UNIT, 9 SLOTS
I

|
|

SECTIONS ——

|
|

KY11-D

PROGRAMMER'S

—
C

f——'&_‘fi

a CONSOLE

|
|

|
|
P
b

—_—
E

SPACE

FOR

M—,—_—.—J

KD11—A PROCESSOR

ADDITIONAL MEMORY
OR PERIPHERAL
INTERFACES
5 SINGLE SYSTEM
UNITS OR EQUIVALENT

DOUBLE SYSTEM
UNITS, 9 SLOTS

LEFT SIDE VIEW

(MODULE VIEW)
11-1570

Figure 6-2

6.2.1

PDP-11/40 Mounting Box (BA11-FC)

Processor Module Allocations

Figure 6-3 shows the module allocation for the basic KD11-A Processor and processor options. The modules noted
with an asterisk are the standard basic modules and must always be present. Other modules are optional with the
specific option designation noted on the figure. The KT11-D Memory Management Option requires the KJ11-A
M7237 module in addition to the M7236 module. The KM11-A Maintenance Console Option may be plugged into

either slot FOI1 or EO1, depending on whether the user is monitoring the basic KD11-A Processor or one of three

processor

options

(KT11-D Memory

Management,

KE11-E Extended

Instruction

Set,

or KE11-F Floating

Instruction Set). Note that the maintenance console option is not installed during normal system operation.

6.2.2

Memory Module Allocations

Figure 6-4 shows the module allocation for the MF11-L Memory system. The basic MF11-L Memory consists of a
single MM11-L 8K memory segment mounted on a double system unit backplane. The modules comprising the basic
MF11-L Memory are indicated by an asterisk. If two additional MM11-L 8K segments are installed in slots four

through nine as shown, the memory is expanded to 24K.
6.2.3

Programmer’s Console Mounting

The KY11-D Programmer’s Console is mounted on the front of the BA11-FC Mounting Box, shown in Figure 6-1.
Mounting is integral with the bezel and panel mounting. The console interfaces directly with the processor. It
provides control signals and Switch register information to the processor and receivers status and data information

and operating power from the processor.
6.3

CABINET AND SYSTEM MOUNTING

Because of the modularity of the PDP-11/40 System, a variety of peripherals may be added to the basic system.
Depending on the type and number of peripherals selected, the unused space in the basic system cabinet may be
sufficient. If necessary, additional cabinets may be added to the system. The basic system cabinet is discussed in

Paragraph 6.3.1; multiple-cabinet systems are discussed in Paragraph 6.3.2

6-3

107S

(USUALLY DL11)

KT11-D

MEMORY MANAGEMENT OPTION (M7236)

TIMING

M7234

STATUS M7235

- *

DECODE M7233 ¥

DATA
KW 11-L
OP TION

(M787)
2

PATH

M7231

KJift
-A
OPTION ‘/

EIS

KMI1-A | KM11-A

OPTION

M7232 %

M7238

KEi1-F FIS OPTION M7239

(FOR KD11)|(FOR KT,KE)

TOP —=

U WORD

(M7237)

KE{1-E

REAR

UNIBUS(M981‘)-X-

SMALL PERIPHERAL CONTROLLER

LEFT SIDE VIEW

* BASIC SYSTEM COMPONENTS
1-138%

Figure 6-3 Module Allocation — KD11-A Processor, Basic and Options :

SECTION

H214 MEMORY

STACK

UNIBUS

G110 CONTROL AND DATA LOOPS

G231 MEMORY DRIVER
H214 MEMORY STACK

G110 CONTROL AND DATA LOOPS

6231 MEMORY DRIVER

*¥G110 CONTROL AND DATA LOOPS

*G231 MEMORY DRIVER

REAR *H214 MEMORY STACK

L UNIBUS

TOP —

* BASIC MF1i-L MEMORY SYSTEM MODULES
NOTE:
Memory in PD P-11/40

Systemis powered for non-interleaved and non-o\rerlopped

situations. Successive and continuous operations to alternate 8K memory segments
is considered a prohibited overlapped situation. Interieaving is not allowed
within the MF11-L or MM11-S powered by the basic box.

11-1571

Figure 6-4 Module Allocation — MF11-L Memory, Basic and Optiohal MM11-Ls

6-4

6.3.1

System Cabinet

The cabinet housing the basic PDP-11/40 is divided into six levels (Figure 6-5). The bottom level (level six) is
reserved for cable entry, however, power supplies and the ADO1-D option may be installed there. Levels four and
five contain the BA11-FC Mounting Box which houses the basic system. Levels one through three provide space for

mounting up to three peripherals, each having a front panel height of 10-1/2 inches.

If a high-speed paper-tape

reader is added to the basic system, it is always installed directly above the BA11-FC Mounting Box. There are

certain restrictions to mounting peripherals in cabinets (Paragraph 6.3.2). With the basic system cabinet, any

free-standing peripheral (system I/O device, card reader, etc.) can be no further from the cabinet than the maximum
length of the interconnecting cable between the interface in the cabinet and the device itself.
6.3.2

System Configuration

In many cases, the number and types of peripherals added to a basic system necessitate additional mounting
cabinets. The standard cabinet layout for PDP-11

systems starts at the right and evolves to the left. Another standard

practice is to define the equipment in the processor cabinet first, then move to the next cabinet not defined for a
specific device. It is always necessary to keep in mind the overall Unibus chain to keep Unibus length to a minimum.

Cooling, cabling, and logic interaction are all system considerations that must be accommodated.

| Generally, configuring multiple cabinet systems requires that no full-depth device or combination of devices should
be placed at the top position (Ievel one) or bottom position (level six) of a cabinet. This restriction is necessary to
ensure unrestricted cable entry at the bottom and proper air flow at the top. Devices can be placed in the unused

cabinet space of another device provided the installation does not interfere with the operation of that dev1ce Disk
cabinets are normally used only for mounting a specific disk system and its options.

- In any cabinet, the top position (level one) should be used only for rigidly fixed equipment. Levels two through five
may be used for either rigidly fixed equipment or slide-mounted equipment. In any cabinet, levels two through five
may be used for a peripheral device or for mounting an extension mounting box which is then used to house various
device interfaces at the discretion of the user. Flgure 6-5 illustrates typical mounting information for a multiple
cabmet system.

A major logic interaction consideration in multiple cabinet systems is latency. Latency is defined as the longest time
a device can be left unserviced before data is lost. Latency is usually a problem only in extremely large systems but

should be considered for optimum system performance. A recommended priority scheme has been established to
determine which peripherals should be mounted electrically closer to the processor to compensate for timing

characteristics of the NPR devices and latency requirements
for BR devices. These priorities are listed in Tables 6-1

and 6-2, respectively. The typical mounting information of Figure 6-5 accommodates these priorities. Additional
information on system configuration is contained in PDP-11 Configuration Worksheet and the PDP-11/10,40 Site
Preparation Worksheet.

Table 6-1
Timing Characteristics of PDP-11 NPR Devices

~ NPR Priority

Device

1
2

Worst Case Latency (us)

RK11/RKO03

8.5

RPI11

14.8%
16

RC11

RF11

RK11/RK02

TM11

TC11

DM11

CD11

DR11-B

Time Between Data Available (us)

11.1

222
32 (at 800 bpi)

200

100
|

119 (at 1200 baud)

800

Dependent on customer use

*The RP11 transfers two words each 14.8 microseconds.

6-5

_., 1490140
LIWL |

NG YV- b4y
anM o'

1409

43av3y

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Table 6-2
Priority of Devices Affected by BR Latency

BR Level Priority

~
BR7

BR Levels

BR6

BRS

BR4

ADO1*

KWI11-L

DP11 @ 9600 baud or higher

KL11

DT11-B

TC11

DC11 @ 1800 baud

UDC117

CR11

- CM11

DP11 @4800 baud

AFC11**

DC11
@ 1200 baud

KWI11-P

DP11 @ 2400 baud

UDCI11¥

DC11 @ 600 baud

DC11 @ 2000 baud

DC11 @ 300 baud

DM11

DR11-A**

DR11-B

*For ADO1 sampling at high rates. Can be assigned to a lower level for slow input applications.
**Priority positions depend on customer application.
TUDC immediate = BR6; UDC deferred = BR4.

6.4

POWER SYSTEM

The PDP-11/40 power system converts a single phase, 115 or 230V, 47—63 Hz line voltage to dc voltages required
by the system. In addition, the power system distributes ac power to drive cooling fans and generates power fail

early warning signals and a clock signal.
The basic power system (Figure 6-6) consists of an 861 Power Controller, an H742 Power Supply, three H744 +5V
Regulators, two H745 -15V Regulators, cooling fans, a power distribution panel, and interconnection and power
distribution cabling. One H754 +20, -5V regulator may be substituted for an H745 if the MF11-U/UP is installed in

an 11/40 mounting box. Two H754s may replace two H745s in an expansion box. One H754 can power two

MF11-U/UP backplanes (up to 64K).

The power system block diagram (Figure
distribution within the power system.

6-6) illustrates component interconnection and power and signal

All power system input power flows through the 861 Power Controller. The power controller output is switched on

and off by the programmer’s console OFF/POWER/LOCK switch. The H742 Power Supply and the cabinet fan
obtain 115 or 230 Vac power from the power controller output connectors. Jumper wires are used to adapt the

H742 to 115 or 230V input power. The H742 distributes 115 Vac to the logic fans, power supply fan and regulator

fans, and 20—30 Vac to each of the regulators. The H742 also generates a +15V output, power fail early warning

- signals, and clock control signals which are distributed along with the regulator dc outputs to the power distribution
panel. The power distribution panel provides a central distribution point for all dc voltages and control signals. Three

power distribution expander boxes, mounted on the panel, provide input and output connectors that route power to
the processor and memory power distribution harnesses.

The following paragraphs are detailed descriptions of power system components as well as dc power distribution.
Prints referenced in the following discussions are contained in the PDP-11/40 System Engineering Drawings.

Revision 1

6-7

January 1974

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6-8

6.4.1

861 Power Controller

The 861 Power Controller centralizes control
of all system power. All power for one or several equipment cabinets is
controlled by a single master switch. The ac input power cord (one per cabinet) is connected to the 861 Power

Controller; the controller also provides two sets of ac power output connectors. One set of connectors can be
switched on and off locally (via the power controller LOCAL/OFF/REMOTE switch) or remotely (via the
programmer’s console OFF/POWER LOCK switch) and is referred to as the switched ac output. The other set of
connectors provides a continuous (uncontrolled) ac output power and is referred to as the unswitched ac output. All
system units and peripherals are normally connected to the switched ac output. The unswitched ac output is
provided for peripherals that require continuous power

The power controller also provides protection against circuit overloading and excessive heat or fire in the equipment
cabinet. If excessive current is drawn (30A @ 115V, 20A @ 230V) the input circuit breaker trips and all input

power is removed. If there is excessive heat in the cabinet (160° F) the thermal switch closes and removes power
from the power controller switched ac output.

For a complete description of the 861 Power Controller, refer to the 861-4, B, C Power Controller Maintenance
Manual, DEC-00-H861A-A-D. Note that the PDP-11/40 uses model 861-B. for 230V operation and model 861-C for
115V operation.

For information on interconnecting 861 power controllers installed in separate equipment cabinets plus information

on connecting the H720 Power Supply to 861 Power Controller, refer to Paragraph 6.4.5.

6.4.2 H742 Power Supply

‘The H742 Power Supply is functionally divided into two major parts:

Power Supply (drawing D-CS-H742-0- 1) — used to provide the various ac mput voltages requ1red by th«
fans, regulators, and power control board.

Power Control Board (drawing C-CD- 5409730 0-1) — used to provide +15V, line clock, and AC LO arr
DC LO signals for system use.

The PDP-11/40 power system operates with 115 or 230 Vac primary power inputs. Although different models of the

861 Power Controller are used, only one power supply (H742)
is necessary. Jumpers are used on the H742 terminal

strip (TB1) to adapt it to a 115 or 230 Vac primary power. If 115 Vac primary power is used, jumpers are placed
between pins 1 and 2, and between pins 3 and 4 of TBI1. If 230 Vac prlmary power is used, a jumper is connected
between pins 2 and 3.

Line power is applied through TB1 to the primary of transformer T1. The transformer secondaries provide 20—30

Vac and 15—24 Vac input power for the power control board and 20—30 Vac for the regulators. Power to cooling

fans is taken from transformer primary. 115 Vac is provided for fan operatlon with either 115 or 230 Vac prime
power input.

The power control board portion of the power supply (drawing C-CS-5409730-0-1) provides a +15V output to
power the Small Peripheral Controller, a clock output used to drive the KW11-L or KW11-P clock option, and the
AC LO and DC LO control signals used to warn the processor of imminent power failure. The power control board
circuits, which generate these outputs, are discussed in Paragraphs 6.4.2.1 through 6.4.2.3.

6-9

6.4.2.1

H742 +15V Output — The power control board of the H742 Power Supply contains a +15V/+8V dc supply

and is shown on print C-CS-5409730-0-1. This dc supply receives 15—24 Vac from the secondary of transformer T1.
This ac input is full-wave rectified by diode bridge D1. The resultant dc is applied to Darlington power amplifier Q1,

through fuse F1. The bias on Q1 is controlled to provide +15 Vdc at output pins 2 and 3 with respect to output pins

4, 5, and 6 (ground). If the Q1 collector voltage starts to increase, the bias at the base of Q2 increases, and Q2
conducts slightly more current to maintain a constant output voltage. Zener diode D7 provides approximately +8

- Vdc at output pin 1. The +8V output is not usedin the PDP-11/40 System. When DC LO is grounded at output pin
9, Q2 conducts hard to cut off Q1 completely, thus removing the +15V output.
6.4.2.2

H742 Clock Output — The CLOCK output is derived off one leg of full-wave rectifier bridge D1 by voltage

divider R10 and R11, and Zener diode D2. The CLOCK output isa O to 5V square wave at the line frequency of the

input power source (47 to 63 Hz). The CLOCK output is used to drive the KW11-L Line Time Clock Option, which
mounts in siot FO3 of the processor backplane or the KW11-P option, which can be mounted in the Small Peripheral

Controller slot.

Operation

of the

KWI11-L

option

described in the KWII-L Line Time Clock Manual,

EK-KWI11L-TM-002; operation of the KWII -P option is described in the

KW1I11-P Programmable Real- sze Clock

6.4.2.3

AC LO and DC LO Circuits — The AC LO and DC LO control signals are used to warn the processor that a

power failure is imminent, allowing the processor time to perform a power-fail sequence. If there is an ac power

failure (line power or power supply failure), AC LO is asserted on the bus followed by DC LO. Sufficient time exists
between these signals to allow storage of volatile data and the conditioning of peripherals. Note that the DC LO
control signal is also used by the MF11-L Memory to inhibit memory operation.

The 20—30 Vac input from the secondary of transformer T1 is applied to the AC LO and DC LO sensing circuits on
the power control board. The ac input is rectified and filtered by diodes D8 through D11 and capacitor C3. A
common reference voltage is derived by resistor R18 and Zener diode D12. Both sensing circuits operate in a similar

manner, and each contains a differential amplifier, a transistor switch, and associated circuits. The major difference
is that the base of Q6 in the AC LO circuit differential amplifier is at a slightly lower value than that of Q9 in the DC

LO differential amplifier. The operation of both sensing circuits depends upon the voltage across capacitor C3.

When AC LO is being sensed, the 20—30 Vac input is rectified and stored in capacitor C3 which charges and
discharges at a known rate whenever the ac power is switched on or off. Thus, the voltage that is applied to the

emitters of differential amplifier Q6/Q7 through R17 is a rising or falling waveform of known value. For example,
when power fails or is shut down, the dc voltage decays at a known rate as determined by the RC time constant. If

the voltage decreases to approximately 20V, the base of Q6 becomes negative with respect to the base of Q7. The
increased forward bias on Q6 causes it to conduct more and the resultant decrease in Q7 causes
it to cut off. This

removal of voltage across R16 causes Q5 and Q4 to conduct, grounding the AC LO line at pin 8. The AC LO signal is
applied through the cable hamess and processor backplane to the processor power-fail initialize logic so that the
power-fail sequence can be started.
The DC LO sensing circuit operates in a similar manner to the AC LO sensing circuit. The prime difference being the

voltage level at which they “trip.” For example, if the ac input starts to decrease, as a result of a power failure or
shutdown, the AC LO lines are grounded before the DC LO lines. As power is restored, the ground is removed from
the DC LO lines before it is removed from the AC LO lines. The DC LO signal is also apphed to the power-fail
initialize logic.

A description of how the AC LO and DC LO control signals are used in the KD11-A Processor
is provided in the
KD11-A Processor Maintenance Manual. For a description of how the DC LO control signal is used by the MF11-L
Memory, refer to the MM 11-S, MF'1I-F, and MF11-LP Core Memory System Manual.
6.4.3

H744 +5V Regulator

Two H744 +5V Regulators are used in the basic PDP-11/40 power system. The H744 circuit schematic is shown in
drawing D-CS-H744-0-1. The following paragraphs describe the regulator circuit, overcurrent sensing circuit, and

overvoltage crowbar circuit.
6-10

Manual, EK-KW11P-MM-002.

6.4.3.1 H744 Regulator Circuit — The 20—30 Vac input is a full wave whichis rectified by bridge D1 to provide a

dc voltage (24 to 40V, depending on line voltage) across filter capacitor C1 and bleeder resistor R1. Operation
centers on precision voltage regulator E1 which is configured as a positive switching regulator. A simplified
schematic of E1 is shown in Figure 6-7. Regulator E1 is a monolithic integrated circuit that is used as a precision

voltage regulator. It consists of a temperature-compensated reference amplifier, error amplifier, series-pass power
transistor, and the output circuit required to drive the external transistors. In addition to E1, the regulator circuit

includes pass transistor Q2, pre-drivers Q3 and Q4, and level shifter Q5. Zener diode D2 is used with Q5 and R2 to
provide +15V for E1. Q5 is used as a level shifter; most of the input voltage is absorbed across the collector-emitter
of Q5. This is necessary since the raw input voltageis well above that required for E1 operation. This +15V input is
Asupphed while still retammg the ability to switch pass tran31stor Q2 on or off by drawmg current down through the
emitter of Q5.

INVERTING
INPUT

FREQUENCY

COMPENSATION

VREF o—

—

—O V¢

SERIES PASS
TRANSISTOR
—o0 VOUT

—Oo VZ

NONINVERTING o~
-~

INPUT

V-

CURRENT

CLIMIT

CURRENT

SENSE

Figure 67 P.recision Voltage Regulator E1, Simplified Diagram

11-0965

The output circuit is standard for most switching regulators and consists of “free-wheeling” diode D5, choke coil L1,

and output capacitors C8 and C9. These components make up the regulator output filter. Free-wheeling diode D5 is

used to clamp the emitter of Q2 to ground when Q2 shuts off, thus providing a discharge path for L1.

In operation, Q2 is turned on and off generatinga square wave of voltage which is applied across D5 at the input of
the LC filter (L1, C8 and C9). This type circuit is basically only an averaging device, and the square wave of voltage

appears as an average voltage
at the output terminal. By varying the period of conduction of Q2, the output
(average) voltage may be varied or controlled, thus supplying regulation. The output voltage is sensed and fed back
to E1 where it is compared with a fixed reference voltage. E1 turns pass transistor Q2 on and off according to
whether the output voltage level decreases or 1ncreases Defined upper and lower limits for the output are
approx1mately +5 05V and +4 95V.

During one full cycle of operat1on the regulator operates as follows Q2 is turned on and a high voltage
(approximately +30V) is applied across L1. If the output is already at a +5V level, then a constant +25V would be
present across L1. This constant dc voltage causes a linear ramp of current to build up through L1. At the same time,

6-11

output capacitors C8 and C9 absorb this changing current and voltage, causing the output level (+5V at this point) to

increase. When the output which is monitored by E1 reaches approximately +5.05V, E1 shuts off turning Q2 off,

and the emitter of Q2 is clamped to ground. L1 discharges into capacitors C8, C9, and the load. Pre-drivers Q3 and

Q4 are used to increase the effective gain of Q2 to ensure that Q2 can be turned on and off in a relatively short
period of time.

Conversely, once Q2 is turned off and the output voltage begins to decrease, a predetermined value of approximately
+4.95V will be reached causing E1 to turn on which in turn causes Q2 to conduct, beginning another cycle of
operation. Thus, a ripple voltage is superimposed on the output and is detected as predetermined maximum

(+5.05V) and minimum (+4.95V) values by E1. When +5.05V is reached, E1 turns Q2 off and when +4.95V is
reached, E1 turns Q2 on. This type of circuit action is also referred to as a “ripple regulator.”
6.4.3.2

H744 Overcurrent Sensing Circuit — The overcurrent sensing circuit consists of:

Q1, R3 through R6, R25,

R26, Q7, and C4. Transistor Q1 is normally not conducting; however, if the output exceeds 30A, the forward
voltage across R4 is sufficient to turn Q1 on, causing C4 to begin charging. When C4 reaches a value equal to the
voltage on the anode gate of Q7, Q7 turns on and E1 is biased off, turning the pass transistor off. Thus, the output

voltage is decreased as required to ensure that the output current is maintained below 35A (approximately) and the

regulator is “short-circuit” protected. The regulator continues to oscillate in this new mode until the overload
condition is removed.

6.4.3.3 H744
components:

Overvoltage

Crowbar

Circuit — The overvoltage crowbar circuit consists of the

following

Zener diode D3, silicon-controlled rectifier (SCR) D7, D8, R22, R23, C7, and Q6.

Under normal conditions, the trigger input to the SCR (D7) s at ground because the voltage across Zener diode D3
is too small to cause it to conduct. As the +5V line approaches
6V, Zener diode D3 conducts and the voltage drop
across resistor R23, draws gate current, and triggers the SCR. The SCR shorts the +5V line to ground through

resistor R21, which is a current-limiting resistor. The SCR remains on until the capacitors discharge.
6.4.4

H745-15V Regulator

Two H745 -15V Regulators are included in the PDP-11/40 power system Operation of the H745 is basically the

same as that of the +5V regulator. The H745 schematicis shown
in drawing C-CS-H745-0-1. Input power (20 to 30

Vac) is taken from the secondary of transformer T1 and applied to the full-wave bridge rectifier (d1). The output of
D1 is a variable 24 to 40 Vdc and is applied across capacitor C1 and resistor R1. The followmg paragraphs discuss
the regulator circuit, overcurrent sensing circuit, and the overvoltage crowbar circuit,
6.4.4.1

H745 Regulator Circuit — Regulator operation is almost identical to that of the +5V regulator; however,

the +15V input that is required for operation of E1 is derived externally and is applied across capacitor C2 to E1 and

the inverting and noninverting inputs to E1 are reversed. In addition, the polarities of the various components are
reversed. For example, Q5, which is used as a level shifter, is an NPN transistor on the +5V regulator but a PNP is

required on the -15V regulator to allow the regulator to operate below ground (at -15V).

Under normal operating conditions, regulator operation centers around linear regulator E1 and pass transistor Q2,
which is controlled by E1. Predetermined output voltage limits are-14.85V (minimum) and -15.15V (maximum).
When the output reaches ~15.15V, E1 shuts off, turning Q2 off, and L1 discharges into C8 and C9. When the output
reaches -14.85V, E1 conducts, causing Q2 to turn on, 1ncreasmg the output voltage
6.4.4.2

H745 Overcurrent Sensmg Circuit — The - 1 5V regulator overcurrent sensing circuit is basically made up of

the same components as the +5V regulator except Q1 is an NPN transistor in the -15V regulator. Transistor Q1 is
normally not conducting; however, once the output exceeds 15A, Q1 turns on and C3 charges. When C3 reaches the
same value as the anode gate of Q7, E1 is biased off, which turns Q2 off, thereby stopping current flow and turning

the -15V regulator off. Thus, the regulatoris short-circuit protected.

612

6.4.4.3

H745 Overvoltage Crowbar Circuit — When SCR D5 is fired, the ~15V output is pulled up to ground and

latched at ground until input power, or the +15V input is removed. A negative slope on the +15V line can be used to
trip the crowbar for power-down sequencing, if desired.
6.4.4a

H754 +20,-5V Regulator

If the system contains an option requiring +20 and -5V, such as the MF11-U/UP, H754 regulator(s) must be added.
They are mounted into slot E of the PDP-11/40 cabinet or into slots D and/or E of an expander cabinet. Note that
the installation of an H754 reduces the amount of available -15V power, because an H745 must be removed.
al

Regulator Circuit — The circuit (refer to schematic D-CS-H754-0-1) is very similar to that of the other
regulators: like the H746, it has a voltage doubler input, but the output consists of two shunt regulator

circuits, one for the +20V, the other for the -5V. The +20V shunt regulator consists of transistors Q4,
Q10 and Q11; the =5V shunt regulator, of Q6 and Q9. Q10 and Q9 are the pass transistors.

The output of the basic regulator is 25V (-5 to +20V). The shunt regulators are connected across this
output, with a tap to ground between pass transistors Q9 and Q10. The voltage at the bases of Q6 and

Q4 will vary with respect to ground, depending on the relative amount of current drawn from the +20V

and -5V outputs of the regulator. If the +20V current increases, while the -5V current remains
constant, the output voltage at the +20V output will tend to go more negative with respect to ground;

this will cause the -5V output to go more negative also, since the output of the basic regulator is a fixed
25V. This change is sensed at the bases of Q6 and Q4; Q6 will conduct, causing Q9 to conduct also, thus
increasing the current between
-5V and ground until the balance between the +20V and the -5V is
restored. At this time, neither Q6 nor Q4 will be conducting. If the -5V current increases, Q4 and Q10

W111 conduct to balance the outputs.
- Overvoltage Crowbar Circuits — There_ are two crowbar circuits in the H754: Q7 and its associated
circuitry for the +20V, and Q12 and its circuitry for the -5V. Either one will trigger SCR D9.

Overcurrent Sensing Circuit — The overcurrent circuit is comprised of Q1, Q8, Q13, Q14, and associated
circuitry. The total peak current is sampled through R4. When the peak current reaches approximately

14A, Q1 turns on sufficiently to establish a voltage across R7 and R38, thus firing Q8. This pulls the
voltage on pin 4 of the 723 up above the reference voltage on pin 5, thereby shutting off Q2. D6 now
conducts, and the current through R37 turns on Q14, which turns on Q13. This keeps Q8 on for a time
which is determined by the output voltage and L1. This action, in turn, allows the off-time of Q2 to be
greater than the on-time; the off-time increases as the overload current increases, thereby changing the

duty cycle in proportion to the load. The output current is thus limited to approx1mately 10A.

Voltage Ad]ustment — The +20V adjustment is located on the side of the H754; and the -5V
potentiometer is on the top, next to the connector. To set the output voltages:

power down, disconnect

the load, power up, adjust for a 25V reading between the +20 and -5V outputs with the 20V
potentiometer, then set the -5V between its output and ground. Power down, reconnect the load, power

up, and then check and adjust the outputs again. This procedure is necessary because the +20V

potentiometer (R17) actually sets the overall output of the regulator (25V from +20 to -5V), while the
-5V adjustment (R21) controls the =5V to ground output. Refer to schematic drawing D-CS-H754-0-1.

6.4.5

861 Power Controller Interconnection

The 3-pin Mate-N-Lok connectors on the 861 Power Controller serve a multiple purpose. They are used along with

the power controller bus cabling to (Figure 6-8):

connect the programmer’s console OFF/POWER/LOCK swflch to the 861 Power Controller, thus

enabling remote control.

|
6-13

Revision 1
|

January 1974

interconnect 861 Power Controllers in adjacent équipment cabinets when more than one cabinet is used
in a system, thus enabling all power controllers to be controlled by the programmer’s console switch.

connect H720 Power Supplies to the 861 Power Controller (H72O Power Supplies must be used
whenever PDP-11/20 memories are usedin the PDP- 11/40 System).

connect optional cabinet- mounted thermal switches (cabinet-m()unted thermal switches must be
connected to pin 2 of any available connector, normally the same connector used for the programmer’s

console switch).

JUMPERPLUGS
E

_~7007006-1

7007006-2

EDNED
i

LOCAL
H720 E/F

(OPTIONAL)

AC PRIMARY

POWER

861

POWER

CONTROLLER

CABLE &

—

|
|

8_
PDP -11/40
CONSOLE

(KYI1-D)

—

o
i

THERMAL SWITCH

(OPTIONAL)

861

POWER CONTROLLER

(ADDITIONAL CABINET)

23) (1

'\ 7008288

7008964

CABLE
]

CABLE

NOTES:

supply may be connected
in either of the twe
configurations shown.

CONNECTOR

(1 23) (12

1. The optional H720 E/F power

o341

<——SWITCHED AC

POWER CONTROLLER

CABINET MOUNTED
.

[(ADDITIONAL CABINET)|

—

(123) (123

7009053

(PROCESSOR CABINET)

—
S

‘

H720

E/F

(OPTIONAL)

REMOTE

a‘fl

2. No terminators are needed
on the unused pins of the
MATE-N-LOK connectors

1
2

|
AC PRIMARY>

H720
E/F

(OPTIONAL)

)

REMOTE

POWER

>
7007006-1
LAST H720 IN LINE

MUST BE JUMPERED

Figure 6-8
Revision 1

January 1974

Power Control Interconnection

- 6-14

11718

6.4.6

Power System Cable Harnesses

The overall layout of the PDP-11/40 power system is shown in Figures 6-10 for the early systems, and 6-13 for the
newer ones. Four cable harnesses are shown on these drawings, which interconnect all power system units and
provide power to the logic fans and the KD11-A Processor and MF11-L Memory backplanes. These harnesses and
their functions are listed below:

H742 to 11/40 Power Harness — interconnects the H742 Power Supply, the H744 and H745 regulators,
the logic fans and the power distribution panel (refer to F1gures 6-11 and 6-14 for detailed wiring
information on these harnesses).

Harness Numbers:

OLD: 7008754: NEW: 7009566

Console to Power Controller Harness — connects programmer’s console OFF/POWER/LOCK switch to a

3-pin Mate-N-Lok connector on the 861 Power Controller (enables system power to be turned on and
off by the programmer’s console switch).
Harness Numbers:

OLD: 7009053; NEW.: 7009053

PDP-11/40 Processor Power Harness — routes dc power and control signals from the power distribution
|
panel to the KD11-A Processor backplane.

Harness Numbers:

OLD: 7009046; NEW: 7009564

First Memory (11/40) Power Hamess — routes dc power and control signals from the power distribution
panel to the basic MF11-L Memory backplane.Harness Numbers:

OLD: 7009103'NE W: 7009565

A fifth cable harness, not shown on Figures 6-10 and 6-13, is used to connect any additional MF11-L Memories that
may be installed in the basic BA11-FC Mounting Box to the power distribution panel. This harness is referred to as
the MF11-L Power Hamess (BA11-FC) and its cable numberis 7009174 (OLD) or 7009560 (NEW).
If any DD11 type system units requiring the G772 module are installed in the basic BAll FC Mounting Box, they
are connected to the power distribution panel by cable harness 7009177 (OLD) or 7009562 (NEW).

For additional information on the DD11 system unit and its installation, refer to Chapter 2 of the PDP-11
Peripherals Handbook.,
|

Appendix A lists all system unit power hérnesses.
6.4.7

DC Power Distribution

Two different power distribution systems may be found in the PDP-11/40 and H960-D, -E Expansion Cabinets. The
newer systems (serial number 6000 and higher) are easily distinguished from the older ones by observing the
BA11-FC Mounting Box (see Figure 6-1): the newer machines have a horizontal power distribution panel, while the

are given in Appendix A.
early ones have a vertical one. Harness numbers for the various system unit options
The early systems are explained in Paragraph 6.4.7.1; the newer ones in Paragraph 6.4.7.2.

6-15

6.4.7.1 Early Power Distribution Systems (Refer to Figures 6-9 and 6-10) — DC power and control signals
generated by the H742 Power Supply and the H744 and H745 regulators are distributed to three power distribution
expander boxes that are mounted on the power distribution panel (Figure 6-9). Each expander box contains two

input: connectors and three output connectors. The three output connectors are wired in parallel, and all signals
applied to the input connectors are applied to each of the output connectors.

Expander boxes. E1 and E2 distribute power to the KD11-A Processor and the MF11-L. Memory backplanes.

Connector J1 receives dc power from the +5V regulator
in slot A and the -15V regulator in slot E. This power is
distributed through output connectors 1 and 3 and is totally committed to the KD11-A Processor and MF11-L
Memory. Connector J3 receives dc power from the +5V regulator in slot B and the -15V regulator in slot D. Output
connector 4 distributes +5V to the MF11-L Memory. Note that a 24K MF11-L Memory only requires 6.4A of +5V
- power, leaving 13.6A for distribution to expansion units.

Expander box E3 distributes power for expansion units. Connector J5 receives power from the +5V regulator in slot

C and the -15V regulator in slot D. Care must be taken when connecting expansion units to avoid overloading the

Note that the H742 +15V and control signal outputs are not shown on Figure 6-9. The +15V output is applied to
input connectors J1, J3, and J5. The control signal outputs are applied to input connectors J2, J4, and J6. Refer to
Figure 6-11 for detailed information on the power distribution (harness 7008754).

In the ca.se of an 11/40 CPU cabinet only (not in an H960-D or -E expansion cabinet), the Console to Power Control
harness 7009053 is tied in with the main power harness.

+5V, 20A
REGULATOR

~15V,10A
REGULATOR

POWER
PANEL

+5V,20A
REGULATOR

AT
| |

‘

+5V,20A
RESGLL(’)'-TATCOR
O0NGL)

SLQT D

iy S

-15v *

-15V,10A
REGULATOR

SLOT B

DISTRIBUTION
——— —-— A
£1
|

o E G
ISR U

SLOT E

SLOT A

—— = f———
E3
|
¥

(]

[

lt._.__.._.._________.!

+5V

v
KD11-A

MF11-L

(SEE BELOW)
MF1i-L POWER REQUIREMENTS(NON-INTERLEAVED)

# There are only two wires

on this cable one biack,
lue.
one blue

BASIC

MEMORY

OPTIONAL MEMORY

16K

24K

+5V u 3.4A

+5V « 4.9A

+5V « 6.4A

~15V « 6.0A

~15V« 6.5A

~15V «

7.0A
"1-1717

Figure 6-9

Regulated DC Power Distribution

Revision 1
January 1974

6-16

~ 15V regulator which is also connected to J3 on expander box E2.

dX3 X08 ¥4MdbP¥660+S1Siq 08

\iflu,if/:

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¥S2800L

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¥00LMd9¢061SIQ S INYVYH HMd 1510 S IANYVH

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6-17

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sog2-ti

Y6"WP[IaBO3IUH6MSNImO5BAST

Installation of MF11-U/UP in Early Units (See Figure 6-12) — A 7009569 conversion harness must be used between

the H754 +20, -5 Vdc regulator and the backplane, in addition to a 7009568 harness between the backplane and the

Power Distribution panel. One 7009569 can power two MF11-U/UP backplanes. If only one backplane is used, the
jumpers to the second backplane should be cut. One 7009568 harness is required per backplane.

The H754 Regulator should be installed in slot E; the blue ~15V wire between P1-1 and P15-1 should be removed; a
jumper wire should be installed between P1-1 and P3-2. This will allow the H745 in slot D to supply ~15 Vdc to the
entire box

The FM11-U field modification kit permits installation of up to two MF11-U/UP backplanes
of 16K memory.

Refer to the field modification kit print set for installation procedures (DD-FM11-U).
6.4.7.2 Newer Power Distribution Systems (Refer to Figure 6-13)— Three 5410590 Power Distributors transmit
the power generated by the H742 and its voltage regulators to the system units. Each distributor has five 15-pin
power and five 6-pin signal connectors. Two of thepower connectors on each distributor are used by the harness
plugs, thus leaving three for connection to system units. The 6-pin signal connector is used only on the 5410590
Power Distributor closest to the CPU. A jumper harness connects the 6-pin plugs on the other distributors to this
|

one (harness number 7009573).

The two power distributors closest to the front of the mountlng box handle power for the KD11-A Processor and to
the first MF11-L Memory. The CPU gets its +5 Vdc from the H744in slot A and its - 15 Vdc from the H745 in slot
E. The MF11-L, as in the early power distribution system, gets its +5 Vdc from the H744in slot B and its =15 Vdc

from the H745 in slot E. The KD11-A uses harness number 7009564, and the first MF11-L number 7009565, to

connect to the power distribution panel. The first MF11-L is connected as follows: the -15V connector (15 pin, 2
wire: blue and black) and the 6 pin signal connector plug into the first power distributor (the same one as the
KD11-A); the +5V connector (the other 15 pin) plugs into the second power distributor. Any additional MF11-Ls

require harness 7009560 and obtain power from a smgle power dlstnbutlon connector, as would any other system
|

umts m the mountlng box.

Figure 6-14 shows details of the new power distribution system (harriess 7009566)5 Note that in the case of an

11/40 CPU cabinet only (not in an H960-D or -E expansion cabinet) there is a Console to Power Control harness
|

7009053 which is tied in with the main power harness.

6-18

P8-

P11

P-;

Ps-2 | _

py Mk

362

H744

45V

REGULATOR

SLOT A

4518

H742

BULK SUPPLY

g Ml

Pi1-7

P14-6

7 P14-8

o1z
—

P10-11¢
-

P10-2 |

/V\

—

HT44

+5V REGULATOR
SLOT B

, | P5-1i

3[B12-5

P14 -1

o2
1 P3-7

23|-£3-8
p3-8
3

]
_————

N
J

G|enD
-

GND

[ -H3=2
7

_P13-3
12221

P13-41

P9-

Ps-s

P10-8

>|[Pe-6
g [ PE-12
12| P6-7

~
~
~

P6 -2

[

P10-10 | -

P10

3| £5-8
4}-F£2-3
51 PS5-10

J
N
J

2 P7-2

g |£13-6

P15-6

SIFs=7

P8 -8

12} £15-8

P14

J
TM

|GND

|onD

po-11

-5V REGULATOR

P10-9

d
e

P10-12

P15
[

| +1sv

P12-21

P12-3
_—12>1

Plz-4

p6-3|

JocLo

pa-7| °

|bcLo

_——— 10

P9-71
6 |eND
8

P1-3|
1221

| 6ND

|enD

P2-21

[
P4-12)
4y L acLo
P9-81 12 |acLo

2 | LcLK

{iLcLk

_———1

|G6ND

P6-101

|ocLo

|pbcLo

P6-51
6 |6nD
-

|
-

p2-7|

_———— 10

4
5

|enD

|45V A REG
|enD

|GND

P3-12

———

| +15V

|-15v E REG

P15 40 | +5v A REG

| +i5v

p2-6|

/—%1-% s

P9-121

PU-21

11 | +15V
12

t
2

P21 5 | ono
|—

|GND

——

———1
N

P5-1

|icLk

pa-g| °5

-EL5-14

7 | +5v B REG

P33 6

P'z': 10 | +5v B REG

GND

P73 ¢ | enD

P42l 3

g-——%%-‘;
2

P15 -1

[EEE [ acko
et 2 | acLo

pa-3|

L——"2] 2!

|LcLk '

P4-51
6 |GnD
-

P4-101

|ocLo

I
LB 2 [ aclo

P15

|
H745

15V REGULATOR
SLOT

)

NakA

P14-4

2
3}

|-B1-3
P9-5

A
~

:g_z

~-P10-6|

| +15V

P
ill BPE

I Mk-

745

P14

SLoT D

‘\\w:-‘;/ ‘

/——:——

7 | +sv ¢ rEG

4 | -15v D REG
2

P>-41 3 | eND
| ———

|enD

|
y
|

° P7-1

H7 44
+5V REGULATOR

SLOT C

[ Rk
P12-7

PS5-2

2721
|

Pw'i— 10 | +5v C REG |

TM
.|

|15V D RS
|-15V D REG

P14-31 3
L ————
P3-3

P96} ¢

4Ip15-3

1
2

e B

5{P3-10

‘

, |

115V AC TO

fLoGIC FANS

11-2305

Figure 6-11 Power Distribution Schematic — Early Systems
(System Serial No. 5999 and lower)

6-19

|
Revision 1
January 1974

—_
ety

S
"“‘"’“"‘:qq,‘
RIS

iy,

Eit

9 PIN

’

CONVERSION HARNESS

7009568 (1 PER MF11-U/UP
BACKPLANE)

‘

C——

;

A
.

kO
S

m”'flxhhq

i
i,

“fh,“_nq'

IN EXPANDER BOX,

NOTE 1:

PLUG MF11-U/UPs IN
SLOTS:
SU2 & 5V3, or

SUS5 & SU6, or
SuU8 & SU¢

IN 11/40 CPU BOX,

PLUG MF11-U/UPs IN
SLOTS:

" REGULATOR
HARNESS
7009569

(1FOR1OR 2
MF11-U/UP
BACKPL ANES)

SUS & SUG, or
SuU8 & SuU9 NOTE 2: a. WHEN REMOVING

SLOT E H745T0
INSTALL H754 AND

CONVERSION HARNESS,
15V WIRE
THE BLUE
{FROM P15} MUST BE
REMOVED FROM P1-1

AND A JUMPER WIRE
ADDED FROM P1-1 7O

P3.2, TO PERMIT THE
SLOT D H745 TO PROVIDE
15V TO THE ENTIRE
BOX.

b. THE RED AND WHITE
AC WIRES MUST BE
REMOVED FROM P15

PINS 6 AND 8 AND

PLUGGED INTO PINS 7
AND 8 OF REGULATOR
HARNESS 7009559.

)

I.
iy

IF ONLY ONE MF11.U/UP

IS USED, CUT THE UNUSED
JUMPER WIRES AT THE
CONNECTOR TO PREVENT
POSSIBLE SHORT CIRCUITS.

NOTE 3:

Figure 6-12

Revision 1
January 1974

MF11-U/UP Installation — Early SyStems

6-20

CONSOLE TO 861 POWER CONTROL
HARNESS # 7009053

POWER DISTRIBUTION
PANEL

SONRSED SN
'

P4 P5P6

SYS UNITPWR

DISTRIBUTORS

P16 NOT USED

IN 11/40 CPU BOX

5410590

T06TR EEEY BRAD
P18

MEMORY HARNESS
MF11-L/LP: 7009565
MF11-U/UP: 7009535

o
P6
T

PLUG INTO 15T
POWER
DISTRIBUTOR

JUMPER

* 1f the first memory is an MF11 L/LP, the --15 V plug

]

HARNESS
7009573

,‘

>
N

TR hl

To mN
YAg
.

(blue and black wires only) goes to the SU-3 socket;

the other 15-pin plug connects to SU-4 jack. -- If the

POWER

WIRING SID S
E

first memory is an MF11-U/UP, the 15-pin plug

connects to SU-4 jack.

3looo0o0 o |15

3l o 0|6

000 0O

@ 00 ;]

oo oo o

HARNESS

7009566

|13

OPTION POWER CONNECTORS
PIN ASSIGNMENTS

1. GND

—BLK

4.+5V—RED

2 LINE CLOCK —BRN | 2.+15V—GRY

3. DC LO

4, AC LO

6.
.

— BLK
9.GND

10.

—Vv10 | 3-+20V-ORN

11.GND —BLK

D
— BLK
5.GN

13-15v —BLU

7. GND —BLK

15.

—YEL | 4.+5V —RED
6.

14.-5V —BRN

8.GND —BLK

TO SWITCHED
OQUTLET
POWER CONTROL

11-2310

{

Figure 6-13 Power Distribution — Newer Unit
with System Serial No. 6000 and Higher

6-21

Revision 1

January 1974

\
~
BULK
SUPPLY
|

REF ONLY

182

SECONDARY -H742

|
€]

15
161

4. BLK. N .
|4 | P14-2

GND3|

|6}—

|7[PI&-lSHLD

VAC

DCLOZ|

O
¥
-

DC LOI|

[I12)}—=2=2

t5vB2| 51

P4-1

RED

’

acepi2-7

/°

ol ac7

_H+_75£\L/4

PI3
»
+svell o) 8- RED

acs

GND
CI| 3f P27 BLK

GNDC2| 4|

P87 BLK

+svcel 5|

P6-! RED

J2'PIO

Wit - O\

_ Rep ,pe-7(

5 .
-

IRy
N
| lAc5 PlI-6
N A
A

RED -

RP8-8
/\WHT
|

\WHT P

__GRYPI5-4]

vAS

aca

|ACO

20-30

‘

115 VAC

N
-13
BLY

| svohl

. GNDDI|3

Pa-2

|, 5y5

GRY

/<>BRN P3-14

QORN P3-3

)

P5-11BLK

oy,

51 50y,

Qorn PI-3

4
|5]

+20v2

5 VAC

RED |
LINE
-

BLK

P2-9

BLK

BLU

P4-13

YBRN
/

P4-14

TWP
i

P4-1|

SLOT E

. 11

15 VAC 10 HT_4 2 FANS

"SHLD

BLK_Pi2-4

lal

onp s

—

CABLE

RED

|!
|

GND 6

It}

GND7

SPARE*3

;"p

SPARE
"]

BLK

+5V Al

15V
4

GND

GND Al

Twp | BLK
P3-8
lg|4 GND 8
BLK
P3-9
GND

() BLK PIT-2 |y GND 11
O
12 SPARETM3

BLU___P3-13
BERY__FoTlo
| 13 -15VJ
1
BRN
PI7-3

-5v2

SPARETM3

=
[ 1l,5v B2

/RED

PLI-5

ORN

P5-3

P6-ll

P6-13

| — =

4 l+5v

—

= — =

5 GND

sPARE’]

onD

GND

| GND 7

10} sPARETM2
2]

SPARETM3
*;

|z]. 15V 2

BLK
/‘BLK

BLK

TM|
6 SPARE

P-4

P6-8

P6-9 |

BLK

PI5-2

BLU

PI5-|
,

GND A2

GND
5

6
GND

GND

~ SPARE %2
12

d BRN_ P5714

13 15V
1.4

15|

[

sPaRETM3

SPARETM3

lial-sv3

-5VJ3

SPARETM3

Pi8

|HOUSING

LINE]

t20VJ2

4 +5V

|5 GND4

|71 6nD B2

+5V A2

> +|5V

P9-11

(HSVAC)

CABLE

DEC 9107574

IBGA\

BLK

Po-12

RED

P9-8

po-7

SHLD

LINE CLOCK
|
DC LO
AC LO!

LO GND

5
8

:
LA

»
WO P22

NOTES:
1.

All wires are 14 AWG unless otherwise specified

|f options requiring
+20 V and -5 V are instailed

in box replace H745 and P15 in slot E with H7j4

REGULATORS

P17 pins 7 & 8. If additional +20, -5 is required,
_replace H745 and P14 in slot D with H754 and
P16, transfer AC wires as above.
(

H745 1 H745 | out
H745 | H754 | in
H754 | H754
--

and P17, transfer
AC wires from P15 pin 6 & 8fto

‘

JUMPERS

slot
D | slotE | -16VJ1 | +20VJ2 | -5VJ3

-—
-~
in__ | in
out
out

WARNING — To prevent damage to regulators

remove/add jumpers according to table:

Figure 6-14 Power Distributibn Schematic — Newer Syst'e_.ms'
(System Serial No. 6000 and Higher) :

Revision 1

January 1974

6-22

TWP

10 SPARE*2

i) aNp 10
12| SPARETM3

14}5v) .

_PII-3

|FEMALE

WHT I N3

)

BLK

d
ERN_P6-1%

PIO-6 18GA| | | | \gp \TOFANS
WHT

BLK _P6-5

BLU

sPareTM3

—

RED

6ND c2

13§- 15V2
14]- 5V3

~PIO-5

SEE NOTES*2&3

17}

SPARETM

ACIO

A
o

12l

;

—

PI9 gk

e=m— 5

P6-2 [2lisvs

0| SPARE2

PIG & PIT.5

'E: ATTER

D.E

ACO

CABEE
_
'
A | DEC "9107786]
'
'
S

P2-8

DEC 910776

[

UNEZ
pP7-2
WHT \

PI3"4

PI2-5

15) onp4 .

15|

ACIO

\__GRY Pl4-4 | 4| y5v3

ORN__P6-3 |3 l20v3

4|+5v

WHT o —-S

/BL,K

-5v2

BLK

‘

fi\/<>BRN Pl-14

|1, 50v3

[2 BEE P

ACE

ORN_P4-3

— Osik pi-11

,
PI5 P23
BLU

o
H745

PIS-6
~
A

_____ )

P3-2

"GRY

/’38_""_0_*3E'C_"_aT 7} ACT

Pi5 B

(JRED PIO-I2 | 8|

3 F———— "% _

GRY

15§ SPARE "3

15} 6nplo

Rz 71

o lAclOPIS-8 [\ A
WHT
D
-

BLU _PI-13

| W BLK P3-1l

KBk P95 | 3| enp2

RED.

10| SPARE2

e
T
13§-15vye¢
/-BRN
PI6-3

/RED

RED

VAC

|s8jeND8
|9|gnDo

I3f-I5V DI

i
|
1 l+sv c2

cnp;

S avanm

lolAcs PI3-7 [\ A

7 | GND BI

Fox
CQBLKPIE=2

SPARE”3

[
|

(QORNPI7-5 | 4
2
20V
¢

1] enD DI
12| SPARE*3

PI3-5

WHT

/RED

PIO-12

'
RED

P2-14

CB"K
PI-8
BLK PI-9

PI6
]

glacr P36 ~ A

20-30

10| SPARE2

15|

)

GNDCI

_PlI-2

6 | SPARE
|

PI2-3

RED

em2-K 5| 6ND A
BLK

AT 14{ -5y 43

—

P20 _

GND3

SPARE#

. 98

4|, vy

WHT

“

BLU Pl4-|

€0

' H-745
H-745.

¢|
6| AC3

N_"7BLK P94 5|

BRN

/EB_-B__(_)_R_PI_Q-_I%&

>\
‘
o
]

PIAB(PI7-8
8Pl )

l2|usva

|4tV

, BLK_P14-3

“:E?l;? ) =N

PI-2

QO ORN PI6-5 | 3 k20vI
&S

e=p—2tK| 8]sl GND
anp

SLOT C

Pla-6

(GRY

poce

—

[ lisy g

AC-3

;
PI12-2

SLOT B

20-30

RED

|ol,.isvi

P3
P

P9-2

PI3-3
% BLK 55T

'RED

_ RED
+5va|| 2| =>-L
GNDBI| 3] P37 BLK

GRY

GNDB2|4 | P4-7 BLK

VAC.

VAC

)

—~

A\Y

CORN_P2-3_ 13l,.0v00
a

T)ACI PI2-6
~ A

P5
—~

RED_PI3-2

BLK

1.|
o

GND Al 3 |FI-T

CLR- \UJ Y

J31P8

Pl-l| RED

GNDA2|4 | P27 BLK
+5VA2|5 | P21 RED

>§WHT pg-2| T| AC®

:
P
10 PI'B-Z‘BL'K

20-30

)
ReD P8-11]6l|ACS
pa v
\RED
VY
'

11J LINE CLOCK| |I1 a3

7/ AC2
8|

ACLO?2

S1ACI

+5VAI [ 2

pig-4ReD()
s

H-744
ALy

SLOT A

|5|P18-3BLk
Y
|Ps-5 BLK Y

LoGND|

)

GNDIl

, AC LOI
»

|3[P14-56RY

onpz|

20-30

|2fP5-2GRY

asve|

:
Pl

o
PliO-i

QWHT Pl0-2}
|

3oLl | BOARPwisvi|
|

S
\RED

)
J4|P9

“jconTROL+V [

vae

5409730
5|
POWER

"
|

N’

" H742 |

H=-2307

CHAPTER
7

GENERAL MAINTENANCE

7.1

SCOPE

This chapter provides general maintenance information for the PDP-11/40 System and includes: preventive
maintenance of mechanical assemblies, diagnostic programs, system power checks, and power supply maintenance.

Maintenance information related to the processor and memory components of the basic PDP-11/40 System is
presented in the associated maintenance manuals. Maintenance of Unibus peripherals requires not only the
associated maintenance manual, but also an understanding of Unibus operation.

In addition to the maintenance information contained in the processor, memory, and peripherals manuals of the
PDP-11/40, significant maintenance information is available in the diagnostic programs documentation. The
diagnostic programs are a major tool for detecting and isolating machine faults, and preventive maintenance should

include their regular use. Diagnostic programs are discussed in Paragraph 7.5.
7.2

OVERALL MAINTENANCE TECHNIQUES

Maintenance of the PDP-11/40 System requires:
®

knowledge of proper hardware operation,

ability to detect and isolate an error condition, and

means to repair the error condition.

The above conditions are true for all but the preventive maintenance procedures for mechanical assemblies and for

the relatively simple power check-out procedures. This section outlines techniques for performing maintenance on
the PDP-11/40. Note, however, that the essential starting point is to have knowledgeable and capable service

personnel.
7.2.1

Knowledge of Proper Hardware Operation

Training courses and machine documentation provide information on hardware operation and are available at the
|
programming, systems, and individual device levels.
The training courses available for the PDP-11/40 System include:
PDP-11/40 Hardware Familiarization (10 days)
KD11-A Maintenance (3 days)

PDP-11/40 Options Maintenance (5 days)
Interfacing the PDP-11 (5 days)

Other courses are available on Paper Tape Software, Disk Operating System Software, and Resource Timesharing

System Software. Information on these and other PDP-11 courses is available from either the Digital Account
|
|
Representative or from the Digital Education Centers.

7-1

Documentation pertinent to the PDP-11/40 System includes documents produced specifically for the PDP-11/40,
and common PDP-11 documents on programming and Unibus interfacing. All of the relevant documents are listed in
Table 1-2.

A special effort has been expanded in production of documents relating to the PDP-11/40 processor (KD11-A) and

processor options (KE11-E, KE11-F, KJ11-A, KW11-L, KM11-A, and KT11-D). Innovations include: print set
formats, tables and notes on the prints, and wire list print notations. These are provided to facilitate initial learning
but, more importantly, to provide instant reminders of specific details during maintenance. Information describing
the print sets appears in the processor and options maintenance manuals.
7.2.2

Detection and Isolation of Error Conditions

Malfunctioning hardware is normally indicated by either software failure or peripheral malfunctions. Failures can
occur with customer’s system software or during the periodic operation of various MAINDEC diagnostic programs.
If the failure occurs with system software, verification by MAINDEC diagnostic programs is suggested.

The PDP-11/40 maintenance philosophy requires that service personnel be well trained on the PDP-11/40 System

and experienced in computer maintenance. While MAINDEC diagnostic progrvams are provided to isolate faults to a
specific program operation or device, service personnel must fully understand hardware and software operation and
system documentation to use the diagnostics effectively. This understanding can only come through training and
experience.

Once the fault has been isolated to a device, the level of repair determines the difficulty and/or expense involved in

making the repair. In the power system for example, regulator units such as the H744 or H745 are replaced if their
output voltages are in error; the circuit board of the H742 unit is replaced if the AC LO or DC LO control signals are
in error. Replacement of KD11-A Processor modules is suggested for situations requiring minimum downtime. While
module replacement is usually the most expeditious method of repair, experienced service personnel may find

integrated circuit (IC) replacement a practical alternative to the cost or transportation of modules.
7.2.3

Means of Repairing Error Conditions

The method of repairing an error condition is directly related to the levels of fault isolation mentioned in the

previous paragraph. If, for example, fault isolation and repair is to be at the IC level, then the parts identified in the
machine documentation must be available and suitable repair and rework techniques must be followed to avoid

equipment damage. If module or subassembly level of fault isolation and repair is to be used, these modules and

subassemblies must be available. Spare part kits are available for the PDP-11/40 (SP11-KF for processor and
SP11-PD for the power supply) and the various Unibus devices. Repair is normally at the module or subassembly

level when downtime is critical or when a large number of machines are involved.

NOTE
|
Memory module replacement may require readjustment of the

strobe delay. Refer to MM11-S, MF11-L, and MF11-LP Core
Memory

cedure,

System,

EK-MM11S-TM-003

for

adjustment pro-

Verification of repair at any level is made by running the appropriate MAINDEC diagnostic programs.
7.2.4

Digital Field Service

The present state-of-the-art in complex computer systems requires qualified service personnel. Installation and 90-day
warranty service are provided by such personnel from Digital Field Service. These people are trained both in basic

PDP-11/40 components (processor, console, and memory) and in peripherals that may be placed on the Unibus.
Material support exists both at the IC level (directly equivalent parts) and at the module and subassembly level.

7-2

Digital Field Service support may be continued beyond the warranty period with a Digital Service Agreement. Total
equipment maintenance programs are available. Details of this service may be obtained from the Digital Account

Representatwe at the local Field Service Office.

7.3

MAINTENANCE EQUIPMENT REQUIRED

Maintenance procedures for the PDP-11/40 require the standard equipment (or equivalent) listed in Table 7-1.
Especially important in analyzing operation of the processor, or processor options, is the KM11 option consisting of

the W131 Module and the W130 or W133 module and associated overlays. Use of the KM11 maintenance displays
and switches is covered in the processor and processor options maintenance manuals. The module extender board

(W900) is also an important diagnostic tool and is discussed in Paragraph 7.6.
7.4

PREVENTIVE MAINTENANCE

Preventive maintenance consists of specific tasks performed periodically; its major purpose is to prevent future

failures caused by minor damage or progressive deterioration due to aging. Any equipment defects or deterioration
detected during preventive maintenance checks should be documentedin a maintenance log book. This maintenance
log, compiled over an extended period of time, can be very useful in anticipating possible component failures,
resultingin module replacement on a projected module or component reliability basis.

Preventive maintenance tasks consist of mechanical and electrical checks. All maintenance schedules should be
established according to conditions at the particular installation site such as environmental conditions, usage, etc.
Mechanical checks should be performed as often as required to allow the fans and air filters to function efficiently.
All

other preventive maintenance tasks should be performed on a regular schedule determined by reliability

requirements. A recommended schedule is every 1000 operation hours or every three months, whichever occurs first.

7.4.1

Physical Checks

The following procedure contains the necessary steps required for mechanical checks and phys1ca1 care of the
PDP- 11/40
1.

Clean the exterior and interior of the cabinet with a vacuum cleaner or a clean cloth moistened with

nonflammable, noncorrosive solvent.
2.

Ensure that the fans are not obstructed in any way. Vacuum clean the air vents of the upper and lower

logic fan housings, and upper and lower regulator fan housings. Remove and wash the filters in the

cabinet fan, located in the top of the cabinet.

3. ' Inspect all wiring and cables for cuts, 'br'eaks, fraying, déterioration, kinks, strain, and mechanical
security. Repair or replace any defective wiring or cable covering.
4.

Inspect the following for mechanical security: LED or lamp assemblies, jacks, connectors, switches,

power supply regulators, fans, capacitors, etc. Tighten or replace as required.

7.4.2

Inspect all module mountmg panels; ensure that each module is securely seatedin 1ts connector and the

locking--releasing mechanismis functioning properly.

Inspect power supply capacitors for leaks, bulges, or discoloration and replace as required.

Inspect module guides for wear, damage, and secure fastening.

Electrical Checks and Adjustments

Make the followmg checks when the system is first installed and whenever a new component is installed in the

system (such as an additional regulator, processor option module, interface module, etc.).

Table 7-1

Mamtenance Equlpment Requlred |
Equipment or Tool

- Oscilloscope

Volt/Ohmmeter (VOM)

Manufacturer

Model, Type,

or Part No.

- Tektronix

DEC Part No. .

- 453%

Triplett

Unwrapping Tool

29-13510

Gardner-Denver

505 244-475

29-18387

(Cat. H812A)

Hand Wrap Tool
__

(Cat. H811A)

29-18301
|

Diagonal Cutters

- Utica

47-4

29-13460

Diagonal Cutters

Utica

466-4 (modified) |

29-19551

Utica

23-4-1/2

29-13462

| 101S

- Miniature Needle Nose Pliers

Wire Strippers
Solder Extractor

Solder Pullit

Standard

Soldering Iron

Paragon

615

(30 watts)

Soldering Iron Tip

29-13452

Paragon

29-13467
(IC type head)

| 605

16-pin IC Clip

AP Inc,

- AP923700

29-10246

24-pin IC Clip

AP Inc.

AP923714

129-19556

KM11 Option Main-

" DEC

KM11-A

“W131 and W130 or 133

tenance Console Modules

Maintenance Card

DEC

Overlay (KD11-A)

Maintenance Card Over-

DEC

lay (KE11-E, F, KT11-D)

Module Extender Board

DEC

* Regulator Extender Cable

559081-0-12

5509081-0-13
|
w900

" DEC

70-08850-0-1

*Tektronix Type 453 Oscflloscope is adequate for most test procedures Type 454 (or equlvalent) may be requlred for some
measurements.

*¥*W133 is a dual version of W130 It provides the drivers for two W131 malntenance cards. The W130 may still be used, but
two units would be required for simultaneous momtorlng of the basic processor and options. Two W131s are required for

simultaneous monitoring in any case.

7.4.2.1 Processor Clock Adjustment Check — Perform the processor clock adjustment according to the clock
adjustment procedure on the KD11-A timing module (M7234) print K4-2
7.4.2.2

Voltage Regulator Checks — Perform the power system checks listed in Table 7-2. Use a VOM to check the

output voltages under normal load conditions at logic backplanes. Use an oscilloscope to measure the peak-to-peak
ripple content of all dc outputs. Each voltage regulator has an adjustment potentiometer located just below the
output indicator lamp. If the regulator output is not within the specified tolerance, adjust as required to obtain an
acceptable output (use a nonconducting adjustment tool). If a voltage regulator cannot be adjusted to meet
specifications, remove and replace the regulator.

Table 7-2

DC Output Voltages

Regulator

Slots

Voltage and Tolerance |

Output Current (max) | ~

Ripple

H744

AB,C

+5 Vdc = 5%

25A

200 mV

H745

| -15Vdet5%

D.E

H754

|
H742

10A

+20Vdc £ 5%

450 mV

-5Vdc £ 5%
——

+15Vdc +10%

1A
Ay

+8 Vdc £ 15%

20—30 Vac (5 outputs)

300W ea output, 1 kW

max. total output

Note 1: Total not to exceed 3A Continuou‘sly-.

7.4.2.3 861 Power Controller — Operate, the REMOTE/OFF/LOCAL switch on the 861 Power Controller to verify
that power is turned on in the LOCAL position and disconnected in the OFF position. Return the switch to the

REMOTE position after performing this test. Paragraph 6.4 references a detailed description of the 861 Power
Controller.

7.4.2.4 AC Power Connector Receptacles — Test the output voltage at each plug and ensure that 115 or 230 Vac

power is available.

ASR 33 Teletype

7.4.3

7.4.3.1

Preventive Maintenance

Checks — Check

the

following "ASR 33

items during system preventive

maintenance:

Check distfibutor plates for deposits.

Check platen and typewheel for deposits.

Check wires around distributor area for secure‘mechanical and electrical connections.

Check the'print hammer and replace if worn.

Rotate the mamshlft manually and check that movement is free. If movement is restr1cted check clutch
assemblies,

Check typewheel pinion racks, and gears for dirt.
Revision 1

7-5

January 1974

7.4.3.2

Lubrication — Use a 50-50 mixture of 20 weight, non-detergent oil and STP oil additive for viscosity

improvement to perform the following lubrication, except where otherwise noted:

QOil all clu‘tch assemblies.

b. . Oil all felts until saturated.
C.

Lightly oil all pivot points.

Oil drive motor at both lubrication points provided.

Oil print carriage bearings.

Oil main shaft bearings.

Qi bearing on function shaft.

Oil the eye ends of all springs.

Oil the typewheel pinion and gear.

Oil repeat mechanism in keyboard assembly.

Clean the dashpot assembly and lubricate it with graphite dust.
NOTE

Do not put oil in the dashpot.

L.
7.4.4

Grease the teeth on spacing ratchet.
LA30 DECwriter Preventive Maintenance

A maintenance manual is provided with the LA30 DECwriter. Refer to Chapter 5 of that manual for detailed
preventlve maintenance procedures.

7.4.5

PCOS High-Speed Paper-Tape Reader/Punch Option

The PCOS High-Speed Paper-Tape Reader/Punch includes a Roytron 500 Series Reader/Punch mechanism. Complete
lubrication and preventive maintenance instructions for this mechanism are containedin the Preventive Maintenance
Section of the Roytron Maintenance Manual, which is supplied with the PCO5. In addition to the preventive
maintenance procedures listed in that manual, perform the following mechanical and electrical checks as part of the
system preventive maintenance procedure.

7.4.5.1

Mechanical Checks — Inspect the PCO5 as follows:

1.
2.

Visually inspect the general condition of the tape reader.
Clean the PCOS5, inside and out, using a vacuum cleaner or a clean cloth moistened with a nonflammable
solvent.

Lubricate the chassis slide mechanism with
a light machine oil. Wipe off excess oil.

Revision 1

January 1974

7-6

Inspect all wiring and replace any defective wiri'ng or defective cables.

.Check that the READER FEED switch, READER ON/OFF LINE switch light condenser,
phototransistor assembly, depressor arm, hold-down bracket, all connectors and circuit modules, tape
feed motor, front cover, and resistor assembly are mechanically secure.

7.4.5.2 Electrical Checks — Perform power supply output tests listed in the following chart:

Output

Pin Number

Tolerance

Ripple (peak-to-peak V)

+5V

A1A2

+0.25V

-15V

A1B2

+1.0V

0.1V

-18V

B8vV2

+2.0V

1.0V

-36V

A8V?2

+4.0V

0.1V

1.0V

Use a VOM to measure output voltage and an oscilloscope to check ripple voltage The +5 and 15V outputs are
adjustable; the —18 and =36V outputs are not adjustable.

7.5

7.5.1

‘

DIAGNOSTIC PROGRAMS

General Description

The following groups of diagnostic programs are apphcable to the basic PDP- 11/40 System and options
a.

PDP-11/40 System Diagnostics

KD11-A Processor Diagnostics

Core Memory Diagnostics

KE11-E Extended Instruction Set Diagnostics
KE11-F Floating Instruction Set Diagnostics
KT11-D Memory Management Diagnostics
g.

KJ11-A Stack Limit Register Diagnostic
KWI11-L Lrne Frequency Clock Diagnostics

Diagnostic programs for peripherals and I/O devices in the system are listed and described in their associated

maintenance manuals. Detailed descriptions and specific operating procedures for each dragnostrc program are

providedin related diagnostic program description (MAINDEC) documentation

Generally, all diagnostic programs are loaded into the lowest 4K words of physrcal memory All diagnostic programs
|

start at address 2005 and run in kernel mode.

Revision 1
7-7

January 1974

Any trap or mterrupt vectors not used by the test. in progress are set up as “‘trap catchers”; the new Program Counter

(PC), stored in the first word of the vector, points to the second word of the vector, which contains

is fetched as an instruction, the processor interprets it as a HALT instruction. The mstructron being
the trap occurred can be 1dentrfied as follows:

executed when

Examine R6 (777‘706).

Set the number foundin R6in the SW1tch regrster and do a LOAD ADRS operatron

) 3.

a 0. When the O

Do an EXAM operatron to determme the contents of the top word in the stack. This is the PC at the

time the false trap/mterrupt occurred

Generally, the PC is pomtmg at the mstructlon following the mstructron that
caused the trap or

interrupt. Use this value and the program hstmg to determme the mstructron
trap or mterrupt occurred

being executed when the

o '-The available dragnost-ic programs.a‘re listed in Table 7-3.

Table 7-3
PDP-11/40 Diagnostic Programs -

Title

Code

System Exercnsers

Commumcatrons Test Program (CTPT
‘General Test Program (GTP)

- MAINDEC-11-DZQCA.
'MAINDEC-11-DZQGA-

System Sizer

Processor Test 17 System Exercrser

MAINDEC-11-DZSSA-

MAINDEC-11-DZQXB-

| Processor Tests

Processor Test 14 Traps

— PDP-11/40, ]]/45 Instruction Exerclser
'.Processor Power Fail Test

MAINDEC-11-DZKAQ-A-

PDP-11/40 Basrc CP Test SXT

'MAINDEC-11-DCKBA-

PDP-11/40 Basic CP Test SOB

MAINDEC-11-DCKBB-

PDP-1 1/40Basrc CP Test XOR

- MAINDEC-11-DCKBC-

. PDP 1 1/40 Basrc CP Test RTT

'MAINDEC-11-DCKBE-

~ PDP- 11/40 Basrc CP Test MARK

MAINDEC-11-DCKBD-

Memory Tests o

" MAINDEC-11-DZQMB-

- -0-124 Memory Exercrser
- CPU Parrty Test* |

MAINDEC-11-DBKBR-

KEI1-E (EIS) Optron Tests |
PDP-11/40 Basic CP Test ASH

MAINDEC-11-DCKBI-

- PDP-11/40 Basic CP Test ASHC

MAINDEC-11-DCKBJ-

PDP-11/40 Basic CP Test MUL

MAINDEC-11-DCKBK-

"PDP-11/40 Ba_Sic CP Test DIV

MAINDEC-11-DCKBL- MAINDEC-11-DCQKA-

- MUL-DIV Random Exerciser

*U_se._only with parity memory systems.

Revision]

January 1974

MAINDEC-11-DBKDMMAINDEC-11-DCQKC-

e
|

7-8

Table 7-3 (Cont)

PDP-11/40 Diagnostic Programs
Title

Code

KE11-F (FIS) Option Tests
KE11F Instruction Tests

MAINDEC-11-DBKEA-

KE11F Exerciser

MAINDEC-11-DBKEB-

KE11F Systems Exerciser (GTP) Overlay

- MAINDEC-11-DBKEO-

KT11-D Memory Management Option Tests
KT11D Basic Logic Test

MAINDEC-11-DBKTA-

KT11D Access Keys Test

MAINDEC-11-DBKTB-

MTPI/MFPI with Memory Management Test

MAINDEC-11-DBKTC-

KT11D Processor States Test

MAINDEC-11-DBKTD-

Memory Management Abort Tests

MAINDEC-11-DBKTF-

KT11D Exerciser

MAINDEC-11-DBKTG-

KJ11-A Stack Limit Register Option Test
PDP-11/40 Basic CP Test Stack Limit

MAINDEC-11-DCKBF-

KW11-L Line Frequency Clock Test

MAINDEC-11-DZKWA-

LA30 Serial — 300 baud

MAINDEC-11-DZLAB-

KL11/DL11A Teletype Tests

MAINDEC-11-DZKLA-

MAINDEC-00-D2G2-PT

1s and Os Test Tape

7.5.2

Special Binary Count Pattern Tape

MAINDEC-00-D2G4-PT

Maintenance Loader

MAINDEC-11-D9EA-

Diagnostic Program Utilization

Diagnostic programs are designed to facilitate maintenance of the PDP-11/40 System and its options. Their specific
purpose is to aid in the definition and isolation of error conditions; this is accomplished in greater detail than is

possible with system operational software.
There is a definite order in which diagnostics should be run. When problems occur or are suspected, a system type

exerciser (GTP or CTP) should be run to isolate the failure to a specific Unibus device. Once the fault is isolated to a

specific Unibus device, the programs designed to checkout that device should be run. This naturally assumes that
programs can be loaded and run.

Relative to the PDP-11/40 processor, an effort has been made to correlate a specific diagnostic program error with a
particular module failure. Table 74 correlates the processor and processor option diagnostic programs to the
modules most likely to be at fault in the event an error is detected. The diagnostics are listed in the order they

should be run (top to bottom), and the modules are listed in the order of failure probability (left to right). The
percentage of failure probability is also noted. Be advised that Table 74 presents the initial effort to correlate

L%)

diagnostic programs to specific module failures and should not be considered an absolute error indicator.

Revision 1

7-9

January 1974

Revision 1

January 1974

7-10

1UOIS}ON9IS,U]

u1os9n]i,dp
7-11

Revision 1
January 1974

7.6 USE OF MODULE EXTENDERS

The W900 Module Extenderisa double-herght multi-layer etch board that provides
one-to-one connections between
module connectors and corresponding processor backplane connector slots. Thus,
three W900 Module Extenders can
be used to extend a PDP-11/40 hex-size module from the processor backplane to
provide access to ICs and discrete

components for test purposes under actrve operatrng condrtrons
-

CAUTION

Do not attempt to extend more than one module at a trme

| while performing tests. Note that the processor clock may

~ have to be adjusted to allow operation with the modules
extended. See processor timing module (M7234) print K4-2
for clock ad]ustment procedure

’7 7

PDP 11/ 40 POWER SYSTEM MAINTENANCE
TP

WARNING

Dangerous voltages ( 115/230 Vac) are present in the power
-system, All electrical safety precautions must be observed.

For the most part marntenance of the power system in the field consists of
replacrng defectrve modules, such

Vvoltage regulators. Paragraph 6.4 provrdes the theory operation of the power system. When a failure occurs,

recommended troubleshootrng approach is to visually inspect the power
system and then, if necessary, check

' _voltages at specrfic pornts in thepower system to 1solate the fault to a particular

module.

771 Vrsual Inspectmn
|

the

If a power system fault is suspected vrsually mspect the system components
for obvrous fault indications. For
'example each of the Voltage regulator modulesis provided with an output indicator lamp
thatis on when the output

o voltage is withinrange. If a single indicator lamp within the group is off, the fault is probably
_regulator module In the case-of the H744 +5V Regulator thrs can be verrfred

within that voltage

by swapprng H744 regulators.

”""Becausethere are two +5V and two -15V regulators in the

~ PDP-11 /40 System, a common troubleshootmg technique
~
would be to swap an operating regulator with a faulty
- regulator If thisis done, first check regulator input voltages to

prevent damage to the second regulatorin the event the fault

'lresin the H742 Power Supply.

If none of the voltageregulator output mdrcator lamps in the group are on, the fault is probably in the associated

H742 Power Supply or 861 Power Controller. Visually inspect the power
indicator lamps and circuit breakers
provided with these components to determrne Whether the fault can be isolated to either
the H742 or the 861.

7. 7. 2 Power System Checks |

- Table 7-5 provrdes a procedure that can be used as a gurde to locatrng defective modules.

January 1974

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\_/

"APPENDIX A

SUMMARY OF EQUIPMENT SPECIFICATIONS

This table gives mechanical, environmental, and programming information for PDP-11 optional equlpment The
equipment is arranged in alphanumeric order by Model Number.

NOTES

Mounting Codes

CAB
= Cabinet mounted. If a cabinet is included with the optlon it is indicated by an X in the “Cab
Incl” column.

FS = Free standing unit. Height X Width X Depth dimensions are shown in inches.
TT = Table top unit.

PAN
= Panel mounted. Front panel height is shown in inches. An included cabinet is indicated when
applicable.

SU = System Unit. SU mounting assembly is included with the option.

SPC = Small Peripheral Controller. Option is a module that mounts in a quad module, SPC slot.
MOD = Module. Height is single, double, or quad.

() = Option mounts in the same space as the equipment shown within the parentheses.

Some options include 2 separate physical parts and are indicated by use of a plus (+) sign.
Cabinet and peripheral equipment (such as magnetic tape) are included in the specifications.
Relative humidity specifications mean without condensation.
Equipment that can supply current is indicated by parentheses ( ) around the number of amps in the |
POWER section. MEMORY POWER: MF11- and MM11- require the same amount of power. In this
table, MF11- power figures show the power requned when the memory is active, while MM11- figures

reflect that required by an inactive unit.

Non-Processor Request devices are indicated by an X in the “NPR” column.
7008855 in 11/45-11/50 CPU; 7008909 in H960-D and 11/40.
7009174. If first MF11-L in 11/40, use 7009103.

A-1

Revision
1

January 1974

8.
9.

7009560. If first MF11-L in 11/40, use 7009565.
H960-C, D only (not CPU Cabmet) one 7009568 per backplane (9 pin convers1on) and one 7009569

for two backplanes (regulator harness).

CONVERSION FACTORS
(inches)

X 2.54

= (cm)

(1bs)

X 0454

= (kg

(Watts)

X 3.41

= (Btu/hr)

[(°C) X }
= + 32

= (°F)

Revision |-

January 1974

‘Model
Number

Description

Mounting
Code

AAll1-D -

D/A Subsystem

ADO1-D

AFC11
BAII-ES
BA614
BB11
BB11-A
|

CAB
PAN
(AA11-D)
SU
SU

CDI11-A
CDI1-E

~ Card Reader
~Card Reader

SU+TT
SU+TT

CR11

Card Reader

SPC + TT

Card Reader

SPC+TT

DAII-B

UNIBUS Link

SuU

DB11

Bus Repeater

Periph Mntg Panel
Remote Analog Data

SU PAN

DA11-F

UNIBUS Window

DCI1-A

Concentrator: 8

Channels, Serial

DECKit 11-F
|

DECkit 11-H o

I/O Interface: 4

Words In/4 Words

1/0 Interface:

DECkit 11-M

I/O Interface:

DFOI1-A
DF11
DHI11
DJ11
‘DL11-A

DLI11 (others)
DM11-BB

DNI11
DP11

8 Words In

Instrumentation
Interface
|

‘Acoustic Coupler
Line Sig Cond
Asynch Line MX
Asynch Line: MX
Terminal Control

Asynch Line Inter
Modem Ctr. MUX
Auto Calling Unit
Synch Line Inter

14 X 24X 18
38 X 24X 38

85
200

11X19X 14

(%)

10-50

20-95

10-55
-

10—-95

(amps)

10—95

'PROGRAMMING
Ist Reg
- Int
Address
Vector

BR
Level

776 756

- 140,144

4,5

AA11-D

1700

772 570
,

134

AFCl11
BAI1-ES
BA614
BB11
BB11-A

Power
Dis
(W)

0.5

7009562
7009562

10—-50
10-50

10—90
10-90

10-50

10-90

7009562

Note 6

7009562

Note 6

- 7009099

10-50

7009563

7009562 |
7009563
|

Note 6 -

776 770

10—-90

650

2.5
2.5

4
6

1.5

130

UNIBUS

NPR

Bus
" Loads

4-7

Model
Number

10—95

3.2

|
0--50

.
10—95

10-50 | 20-90

float

450
700

772 460
772 460

230
230

4
4

400

777 160

230

400

0-70 | 10-95
|

175

0.75 @ 230 Vac

777 160

ADO1-D

772 410
:

float

774 000

float

|
;

1.84

User

Note 6

0-70

10—-95

3.91

User

Note 6

0-70 | 10-95

1.97

User

Note 6

0-70

1.75

User

TT
.
- DF slot
2 SU
SU
SPC

6X7X12
-

0-60
7009466
7009561
7009099 | 7009563

SPC
(DH11)

- SU
SU

Note 6
Note 6

General Interface
UNIBUS Switch

SPC
PAN

GT40

Graphics Terminal

18X 20X 24

IBM Chan. Interface | CAB

X | 180

150

7009562
7009562

- 7009562
|

10-95
'

10—95

7009099 | 7009563
Note 6

5-45

0—40
0-40

10-50
|

10—-50

10-50

20—-90
20—-90

10-90

20-90

10-55 | 10-90

15—35

20—80

8.4
5
1.8
1.4
2.5

0.100A@% 15V
0.10A@+% 15V

1.8
2.8

0.15A@-15V

5.7

0.04
0.07

3.3
1.5

User

- User

2.5

4
5

772 410

767770
o

|
|

float
124

float
user

300 | 776200 | float

1500

fl.pat

~ float

1+1

- CM11-F

CR11

DA11-B
DAI11-F

‘DBI11

DCI11-A

DDI11-A
DECkit O1-A

DECKkit 11-F
DECkit 11-H

DECkit 11-K

‘DECkit 11-M

2
1
|

DFO1-A
DF11
DH11
DIl
" DLI11-A

1
1

DNI11
DP11

1
1

5
7

float |
float

float
|

775 200
774 400

float
float

5-6

5
5
4

CD11-A
CDII-E

float
float
060,064

1
1

CBl11

|
float
float
777 560

776500 |
775 000

A@+15V
A@-15V

User

0.3
see Product Bull.
0.24 A@-15V
see Product Bull.
0.15A@-15V

]

X
X

1,2
|

124

BC11A
BM792-Y

4-7

230

see Product Bull.
1.5@ 115 Vac

|
764 000

5-50

‘

5.6

10-90

.
0.3

DR11-C
DTO3-F

DMA Interface

'
15

S% X 19X 13

DMA Sync Line
Interface

DX11

(°C)

10-50

Note 6

7009099

DQ11
1

DRI11-B

X 19X 14

Note 6
Note 6

Out

DECKit 11-K

POWER

- Cur needed/(supplied)
+5V | 115 Vac / Other

- SuU

Words In/4 Words
I

Rel
Humid

0-55

300

/O Interface: 3

Asynch Line Inter

DDI11
DECkit 01-A

Cab

Interface .

- CMI11-F

7009562

100
|

SPC

Telephone Switching

10%

Oper
Temp

UNIBUS Cable
Bootstrap Loader

CBIl

‘Note 6

ENVIRONMENTAL -

Power Harness
Early
New

Panel (non-slotted

blocks)

BCI1A
BM792-Y

PAN

-~ A/D Subsystem
Mounting Box
D/A Converter
Blank Mntg Panel
Blank Mounting

(inches)

A/D Subsystem

" MECHANICAL
Cab | Weight
Incl
(Ibs)

Size
HXWXD

-7 | X

[
|

A-3

DQI11

DR11-B

1
1+1

‘DR11C
DTO03-F

GT40

DL11 (others)
DM11-BB

DX11-B

Model

Number

Description

‘Mounting

Code

Size

(HX WX D)

(inches)

MECHANICAL
Cab

Weight

Incl

(lbs)

Power Harness

Early

New

ENVIRONMENTAL

Oper

Temp

Humid

0-50

| 20-95

POWER

Rel

Cur needed/(supplied)

+5V l 115 Vac / Other

(%)

(amps)

Power

Dis

(W)

PROGRAMMING

1st Reg

Int

Addfess

Vector

Level

UNIBUS
NPR

Bus

Loads

Model

Number

H312-A

Null Modem

H720-E

Power Supply

(BA11)

‘H312-A

H722

Transformer

(PC11-A)

H742

Power Supply

(H960-D)

H744

+5 V Regulator

(H742)

H745

-15 V Regulator

(H742)

(100A)@-15V

H745

H746

MOS Regulator

(H742)

(1.6 A)@23.2V

H746

(22)

(10A)@-15V

700

H720

1.5 A @230 Vac

H722

(1A @+15V

H742

(25)

- H744

33A)@19.7V

H754
H933-C

+20, -5 V Regulator
Mounting Panel

(H742)

(1.6 A)@-5V
BA)@+20V

:
|

(1A)@-5V

H933-C

(H803 blocks)
H933-D

* Mounting Panel

|
SU

H933-D

(H808 blocks)

H960-C

Cabinet

72 X 21 X 30

120

Cab (1 drawer)

72 X 21 X 30

300

7008754

7009566

(75)

20A)@-15V

900

H960-E

Cab (2 drawers)

72 X 21 X 30

470

7008754

7009566

(150)

|16

(40A)@-15V

| 1800

KE11-A

~ Ext. Arith. Elem.

Note 6

7009562

777 300

KG11-A

Comm Arith Unit

SPC

1.5

770700

KWI1-L

-“_.//

H960-D

H961-A

H754

Cab w/o side pan

72 X 21 X 30

120

KWI11-P

Line Clock

Programmable Clock

MOD

single ht

LA30

DECwriter

31 X 21X 24

LCI1-A

LA30 Control

SPC

LP11-F

Printer (80 col)

SPC + FS

46 X 24 X 22

LP11-]

Printer (132 col)

SPC + FS

SPC

‘

H960-C

0.8

|
15-35

3
1.5

10—43

15—-80

1.5

46 X 48 X 25

575

10—43

15-80

1.5
1.5

LP11-R

Ptr (heavy duty)

SPC + FS

48 X 49 X 36

800

10—43

15—-80

Lab Periph System

PAN

5—43

20-80

LS11

Line Printer

SPC + TT

12X 28 X 20

155

5-38

5-90

LT33

Teletype

34 X 22X 19

15-35

20—-80

160

10—43

20—-80

300

H961-A
100

|
1.5

1.5

104

|
|

060,064

KE11-A
KG11-A

- KWII-L

777560

200

LPS11

H960-E

}

772 540

20-80
-

H960-D
é

777 546

1
110

KW11-P

LA30
LC11-A

250

777514

200

LP11-F

500

777514

200

LP11-J

2000

777514

200

LP11-R

300

float

-4—6

LPS11-S

300

777514

200

600

777514

opt

200

LS11
LT33

LV11

Electrostatic Ptr

SPC + FS

38X 19X 18

M105

Adrs Select Module

MOD

single ht

0.34

M105

LV1l

M783

Bus Transmitter

MOD

single ht

0.2

- -M783

M784

Bus Receiver

MOD

single ht

0.2

M784

M785

Bus Transceiver

MOD

single ht

0.3

M792

Diode ROM

SPC

0.23

773000

M795

Word Count

MOD

M796

Bus Control

MOD

M796

M920

Bus Jumper

MOD

- M920

M930

Bus Terminator

MOD

double ht

M1501

Bus Input Interface

MGOD

single ht

0-70

10-95

0.3

M1502

Bus Output Interface

MOD

double ht

0—70

10—-95

0.75

M1502

M1621

DVM Data Input -

MOD

quad ht

0-70

10-95

0.78

M1621

‘

Interface

- M1623

Instrument Remote

M785
1

M792
M795

1.25

M930

M1501

MOD

quad ht

0-70

| 10-95

1.6

Unibus Interface

MOD &

quad ht

0-70

| 10-95.

0.79

Foundation

SPC

16-Bit Relay Output

MOD

M1623

- Control Interface

M1710
M1801

Interface

quad ht

0-70

10-95

1.46

opt

M1710

M1801

A-5

- Model

Description

MECHANICAL

Mounting

Size

Code

(HXWXD)

Number

Cab |

Weight

Incl

- (Ibs)

ENVIRONMENTAL

Power Harness

Early

New

(inches)

Rel

Temp
(°C)

Humid
(%)

POWER

Cur needed/(supplied)

+5V !

Power

115 Vac / Other
(amps)

Dis
(W)

M7820

Interrupt Control

MOD

single ht

M7821

Interrupt Control

MOD

single ht

ME11-L

Core Memory (8K)

PAN

MF11-L

Core Memory (8K)

2 SU

MF11-LP

Parity Memory (8K)

Note 7

Note 8

2 SU

0—50

10—90

3.4

6A@-15V

Note 7

125

MF11-U

Note 8

Core Memory (16K)

0—50

10-—-90

2SU

4.9

6A@-15V

125

‘Note 9

7009535

0-50

0-90

4.5

120

MM11-L
MM11-LP

Parity Memory (16K)

Core Memory (8K)

MM11-U

MM11-UP

Parity Memory (16K)

0—-50

\
~
b

/'(

Note 9

10-90

7009535

0—50

0—90

(MF11-L)

0-50 | 10-90

(MF11-LP)

0-50

0—50

MSI11

Semiconductor Mem

(11/45)

Paper Tape

SPC + PAN

10%

5% X 19 X 23

Mover

A@20V

Level

NPR

Bus

34A@20V

0.5A@-5V
0.5A@-15V

125

05A@-15V

125

10-90

1.7

0—90

4.5

M7820
M7821

MF11-L
MF11-LP

120

0-50

10-80

13-38

20-95

05A@-5V

0.5 A @20V

0—40

10—95

|
MM11-L

MM11-UP

0.5A@-5V

350

115 Vac

250

230 Vac

250

772 100

114

777 550

070,074

MS11

10%

13-38

20-95

10%

115

350

777 550

070

Disk & Control

20-80

RF11-A

17-50

PAN + PAN

16+ 16

2.2

250

500

777 440

210

Disk Drive

20--55

RKOS

17-33

PAN

6.5

10%

750

777 460

204

160

RK11-D

Disk & Control

SU + PAN

102

RP0O3

Disk Drive

40X 30X 24

RP11-C

Disk & Control

CAB + FS

Disk Drive

RTO1

Numeric Data Entry

Terminal
RTO02

Alphanumeric Data

TAll

Cassette

PAN

10%

6.5 X 12.5X 15

250

7008992

|
X

DECtape & Control

SPC + PAN

7009562

15-43

| 20-80

10-80

100

17-33

20-55

200

17-50

20-80

2.2

250

0—40

RS64

10-90

RTO1

‘RTO2

0—40

450

15-27

10%

15-27

PAN

10%

PAN

10%

TUS6

DECtape Transport

PAN

UDC11

I/O Subsystem

CAB

VRO1

Display

VR14

Display

VTOl1

Display

12X 12X 23

12X 19 X 30

15-27

200

6 A @230 Vac

1300

6 A @230 Vac

2100

0.25 @ 115 Vac

40—60

777 400

220

RK11-D

RP11-C

776 710

254

RPO3

X
|

RS11

0.12
@ 220 Vac
110 Vac

220 Vac
20-80

40-60

PAN

|
10—-40

15-27

Magtape Transport

7.5

10-90

500

TU10

- RKOS

15-33

740

250

26+ 10%

RF11-A
N

10—-80

PAN + PAN

RCI11-A

20—-80

Magtape & Control

Alphanum Terminal

10% + 10%

PRI11

15—-43

PAN + PAN

- 15-33

|
|

- TM11

VTO5

63X 144X 16

415

PAN

Entry Terminal
TC11-G

110

PDM70

‘

SPC + PAN

PCI11

PAN

MR11-DB

1
4

Disk & Control

1.5

MMI11-LP
MM11-U

1.5

MF11-UP

;“

05A@20V

0.6

RC11-A

Disk

MF11-U

Paper Tape (1dr)

RSi1

‘ME11-L

PR11

RS64

Model

Loads
Number
N

|
1.7

PCl11

Programmable Data

Vector
|

125

(MF11-UP)

2 SPC

Addr&}éss
)

UNIBUS

05A@-5V

Bootstrap

PDM70

MRI11-DB

Int

PROGRAMMING

IstReg

2 SU

- Parity Memory (8K)

- MF11-UP

//\\

Oper

1.5

1
9

120

777 500

260

870

777 340

214

1000

40—60

-9

1000

| 40-60

- 5-50

10-90

350

10-50

1700

10-90

771 774

120

10-50

10—-90

0-50

10—80

- 10—43

8—90

2.2

772 5;20

224

o
X

‘TA1l

"TC11-G

TTM11

TUIO0

234

TUS6

4,6

UDCl11
|

400

VRO1
VR14

250

VTO1.

130

VTOS

A-7

PDP-11/40, -11/35 SYSTEM MANUAL

EK-11040-TM-002

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