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Document:	PDP-11/34 System User's Manual
Order Number:	EK-11034-UG
Revision:	1
Pages:	142
Original Filename:

OCR Text

PDP-11/34
system user’'s manual

dlifgliltiall

" EK-11034-UG-001

PDP-11/34
system user’'s manual

digital equipment corporation - maynard, massachusetts

1st Edition, July 1977

The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

PDP
RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

TYPESET-11
UNIBUS

7/80-14

CONTENTS

SCOPE

. . . . . e
e
e I

SYSTEM DESCRIPTION
Unibus

. . . . . . . . . .

1-2

. . . . . . L
e e e e
e e

1-3

W
D

M9301 Bootstrap/Terminator
M9302 Terminator
Memory

Operator’sConsole

KDI11-E (EA) Central Processor

. . . . . . . . .

. .

...

1-3

1-4

1-6

e e e e e e e e e e e e e

1-7

Mounting Box, Backplane, and Power Supply
RELATED LITERATURE

1-5

. . . . . . . . . . . .

. . . . . . . . . . . . . ... ... ...

. . . . L

Optional Equipment

. .

. . . . . . e

CHAPTER 2

OPERATION

2.1

OPERATOR’S CONSOLE (KY11-LA)

. .
.

. .

1-9

...

. .

. . .. ...

1-11

1-14

. . . . . .. ... ... ....

2-1
2-1

. .

...

2-3

. . . . . . . ... oo

2-3

Console Switches

. . .

2.1.2

Console Indicators

2.1.3

Console Emulator

. . .

.
.

. . . . . . . . .

2.1.1

. . . .

2.1.3.1

Entry Into the Console Emulator

2.1.3.2

2.1.3.3

Console Emulator Functions

. 2.1.3.4

dQN

—

W B R R RN NN

e
Y
e
T
T
N

[WY

INTRODUCTION

CHAPTER 1
[

Page

. .

.. .

... .. ...

. . . . . . . . . . ...
.

. .

L. ..

2-4

...

.. ....

2-5

2-6

...

2-7

. . . . . . . . . . .. ... e

2-8

Examples of Console Emulator Operation

2.1.3.5

Booting from Peripheral Devices

2.1.3.6

Possible Operator Errors

2.2

PROGRAMMER’S CONSOLE (KYI11-LB)

. .

...

. .. . . . .. ... ....... 2-10

2.2.1

KY11-LB Controls and Indicators

2.2.2

Notes on Operation

. . . . . . . . . . o

v i i 2-12

2.2.3

Examples of Programmer’s Console Operation

. . . . . . .. ... ... 2-13

. .

. . . . . . . .. ..

e
e

Boot-Initialize Function

Power-Up Reboot Enable Feature

. .

Sack Turnaround Feature

. . ... ...

GENERAL

Halt-Continue Function

3.2.1

... .... 2-10

FUNCTIONAL SYSTEM DESCRIPTION

PO et e
—
N
fo

CHAPTER 3

. .

. . .

. .

. . . .

3-1

. . . . . .. ... ...,

3-5

... ... ....

3-5

.. .........

3-5

KY11-LA DETAILED DESCRIPTION
. . . . . . . ... ... ... ....
HALT/CONT Switch . . . . . . . . . . . ..
.
.
...

3-5
3-6

. . . .

. ...

3-1

... ......

. .

... .

3.2.2

BOOT/INIT Switch

. . . . . . . . . . oo,

3-8

3.2.3

DC Power Switch

. . . . . . . .. o

3-9

3.2.4

Indicators
. . . . . . L L

i1i

e e

3-9

CONTENTS (CONT)
Page

3.3

M9301 BOOTSTRAP/ROM FIRMWARE

3.3.1

Basic CPU Diagnostics

3.3.2

3.3.3

Memory-Modifying Diagnostics

3.3.4

Bootstrap Programs

CHAPTER 4

CONFIGURATION

4.1

GENERAL

4.2

BACKPLANE

. . . . . . . . . . . ... ... ... 3-12

. . . . . e
e e e e e e e

. . . . .

Physical Description

4.2.2

Electrical Connections

4-1
4-1

. . . . . . .

4.2.2.2

Backplane Signal Connections

4.2.3

Module Placement

SWITCHES AND JUMPERS

4.3.3
434

4.3.4.1
4.3.4.2

4.34.3
4.3.4.4

4.3.4.5
4.3.4.6

4.3.5
4.3.6

4.3.7
4.3.8

e e e e e e e

. . . . . . . . .« v v i i

Power

4.3

e e

e e e e e e e

e e e e e e e e

. . . . . . . . . . . ..

..o

. . . . . . . . . . .

e 4-15

KD11-E Processor
. . . .. ... ... ... e
e e e e e e e e e 4-15
KDI11-EA Processor
. . . . . . .. e e e e e e e 4-15

M9301 Bootstrap/Terminator
. . . . . . . . . . . . . . .. ... .. 4-15
DL11-W Serial Line Interface and Real-Time Clock
. . . . . . . . . .. 4-19
Device Address
. . . . . . . . ..
e e
e e e 4-20

Vector Address
. . . . . . . . .
e e e
Baud Rate
. . . . . . . . . ..o
20-mA Current LoopMode . . . . . . . . ..o oL
Data Format
. . . . . . . . . .
e
e
e e
e
DL11-W Compatibility Switches
. . . . . . . .. ... ... ...

4-21
4-21
4-22
4-22
4-23

MS11-EP, MS11-FP, and MS11-JP MOS Memory
. . .. . . ... ...
MMI11-CP Core MEmMOTY
. . . . v . v v v i e e e e e e e e e e e
e
MM11-DP Core MEMOTIY . . . . . .« v v it e e i e e e e e e e e
M7850 Parity Controller . . . . . . . . . . . . .
oo

4-24
4-26
4-26
4-27

5.1

GENERAL
. . . . .
e e e e e e e e
e e
SITE CONSIDERATIONS
. . . . . . . o
e e s s e
e e
... ...
. . . . . . . . . . . .. ...
Humidity and Temperature
Air-Conditioning . . . . . . . . . . L oL
L oo
. . . . . . . .. Lo
Acoustical Damping
Lighting
. . . . . . . . . .«
e
e e
e e e
Special Mounting Conditions . . . . . . . . . ... ... oo
Static Electricity . . . . . . . . . . . ..o oo
ELECTRICAL REQUIREMENTS . . . . . . . . . . . ..
System Grounding . . . . . . . . .. . Lo oo
Specifications Summary
. . . . . . . . .. oL o o000
e e

5.2.1
5.2.3

5.2.4
5.2.5
5.2.6
5.3

5.3.1
5.3.2

5.4
5.5

4-6

e 4-10

INSTALLATION

5.2.2

4-1

. . . . . . . . ... ... .. ...

CHAPTER 5

5.2

4-1

. . . . . . . . . . .. .. . oo

4.2.2.1

4.3.2

e e e e e 3-10

. . . . . . . . . . . .. ... ......... 3-12

. . . . . . . . .. .. Lo 3-14

4.2.1

4.3.1

. . . . .. . . ... ... ..... 3-10

. . . . . . . . . . .

e e e e e e e e e e e e e e e e
e
e
UNPACKING . . .
MODULE UTILIZATION IN TYPICAL SYSTEMS . . . . ... . ... ...

5-1
5-1
5-1
5-2
5-2
5-2
5-2
5-2
5-2
5-4
5-5

5-6
59

CONTENTS (CONT)
Page
5.6

INITIAL INSPECTION

5.7

TYPICAL SWITCH SETTINGS OF MODULES

. . . . . . . . .

e e

5.8

FIRST-TIME START-UPPROCEDURE

5.8.1

Check of Standby Operation

e it e 5-10

. ... ... ... e 5-13

. ... .. ... ... .. ..... 5-21

. . . . . . . . . . . . ... ... ..... 5-23

CHAPTER 6

TROUBLESHOOTING

6.1

PDP-11/34 CHARACTERISTICS SUMMARY

.. ... .. ... .. ....
. .«

6-1

6.1.1

Operation (KY11-LA)

. . . . . . . .

6-1

6.1.2

Operation (KY11-LB)

. . . . . . . . . . ...

6-1

6.1.3

Installation

. . . . . . . . . .. ..

6.2

TROUBLESHOOTING PROCEDURES

. . . . . .. ... ...

6.2.1

Quick Verification Routine

6.2.2

Troubleshooting Flowcharts and Explanations

6-2

... ...

6-2

. . . . . .. . ... ...

6-6

. . . . . . . . . . . ..

APPENDIX A

KY11-LB MAINTENANCE MODE OPERATION

APPENDIX B

EXTENDED ADDRESSING

APPENDIX C

SUMMARY OF EQUIPMENT SPECIFICATIONS

6-2

.......

FIGURES

. . . . . . . . .. . ... ..... e .

1-1

. . . . . . . . . . ... ...

1-2

KD11-E Central Processor Unit (M7265 Module)

. . . . . . . . . . . .. ..

1-3

KD11-E Central Processor Unit (M7266 Module)

. . . . . . . ... ... ..

1-4

Operator’s Console

. . . . . . . . . o i

1-5

. . . . . . . . ... .. ... .....

1-6

. . . . . . . . . . . ... oo

1-7

M9301 Bootstrap/Terminator Module
M9302 Terminator Module

MS11-JP MOS Memory Module

. . . . . . . . . . ... ... ... . ...,

. . . . . . . . .. ...

MMI11-DP Core Memory Module

. . . . . . . .

M7850 Parity Controller

MMI11-CP Core Memory Module

DL11-W Serial Line Interface and Real-Time Clock

e
e
ek
kel

LR
]

ped
e
paed

System Block Diagram

]

PDP-11/34 Computer System

Page

]

Title

KY11-LB Console and Interface Module

. .. ... ... .....
... ......

1-9
1-10
1-11

3-3

. . ...
. ..

PDP-11/34 Programmer’sConsole

\®)

. .. .. . ..

PDP-11/34 System Interconnections (BA11-K Mounting Box)

PDP-11/34 System Interconnections (BA11-L Mounting Box)

PDP-11/34 Operator’sConsole

;—;M.._;;—d — o

. . . . . . . . . . . . ..o

1-8

D 00 3 A O S W
-

Figure No.

. . . .

. . ... ...

1-12

. . . .. ... ... ....

1-13

. . . . . . . . . . . . o v v

v i v i v

2-1

. . . . . . . . . . . .« . ...
... 2-10

FIGURES (CONT)
Figure No.

Title

Page

3-3

M9302 Sack Turnaround Logic

. . . . . . . . . .. .. ... ... .....

3-6

34
3-5

HALT/CONT Switch Logic
. . . . . . . . . . . .« .
i
v i v
.
BOOT/INIT Switch Logic
. . . . . . . . . . . . . .. .. ... . .....

3-7
3-8

3-6

DC Power Switch

. . . . . . . . . .

3-7

DC ON Indicator

. .

3-8

BATT Indicator

4-1

PDP-11/34 Backplanes

Mate-N-Lok Connector Pin Locations (Viewed from Wire Side)

4-3

3M Connector Pin Locations (Viewed from PinSide)

4-4

Standard and Modified Unibus Pin Designations

. . .

. .

. . . . . . . . . .

4-5

SPC Pin Designations

4-6

NPG Signal Path

BG Signal Path (BG4 Line)

5-1
5-2
5-3

5-4
5-5

5-6
5-7

5-8

5-9
6-1
6-2
6-3

6-4
6-5
6-6

6-7

e e

3-9

e e e e e e e e e e e

3-9

4-2

. . . . . . . .

4-3

. . . . .. . . ... ..

4-6

. . . . . . . . . . ... ..

4-8

. . . . . . . . . . . ...

Module Placement . . . . . . . . .
DL11-W (M7856) Switch Locations
DL11-W Device Address Selection .
DL11-W Vector Address Selection

4-11

o e

4-9

. . . . . . . . . . . ..o 4-10

4-8

4-9

e e

. . . . . . . . . . . .

4-7

4-10

. .

. . . . . . . . . . . . ... oL 4-11

..
e e
. . . . . . . . . . .
. . . . . ... ...
. . . . . . . . . ..

e
e
e e e e e
. . . .. .. ....
... e
e e e e
... ... .....

Connector Specifications for BA11-L and BA11-K Boxes . . . . . .
Connector Specifications for 861-B and 861-C Power Controllers . .
Packaging of PDP-11/34 [26.3 cm (10-1/2inch Box)]
. . . . . ..
Packaging of PDP-11/34 [13.3 cm (5-1/4inch Box)]
. . . . . ...
PDP-11/34 Module Utilization
. . . . . . . . . . . . . . .

4-13
4-19
4-20
4-21

.. ...
. . . . .
... ..
... .....

5-3
5-4
5-7
5-8
59

Computer Subassemblies of BA11-L MountingBox . . . . . . . .. ... ..
Computer Subassemblies of BA11-K MountingBox . . . . . .. ... .. ..
Backplane Connectors . . . . . . . . . . . ..
o
e
Typical Jumper Placement and Switch Settings of Modules . . . . . . . . ..
Action 1 . . . . . L
e e e e e e e e e
e e e
e
ACtiOn 2 . . . .
e e
e e e e e e e e e e e e e e e e e e

5-10
5-11
5-12
5-13
6-9
6-11

Action 3
Action 4
ACtiOn 5
ACLION 6
ACtiON 7

.
.
.
.
.

.
.
.
.
o

L
e
.
e
.
e
.
e e e e e
o e e e e e e e e e e e e

e e e
e e e
e e
e e e
e e e

e
e
e
e
e

e e e e
e e e e
e e e e
e e e
e e e e

e
e
e
e
e

e e e
6-12
e e e e 6-13
e e e e e
6-13
e e e e 6-14
e 6-14
e

TABLES
Title

Table No.

2-1

Page

Bootstrap Routine Codes for M9301-YA and M9301-YB

. . . . . ...
...

2-7

2-2

Bootstrap Routine Codes for M9301-YF

. . . . . . . . . . .. ... ....

2-8

2-3

Load, Examine, Deposit, and Start Errors

. . . . . . . . . . . . ... ....

2-9

3-1

Priority Service Order

4-1

Power Connector Signal Assignments for DD11-PK and DD11-DK

4-2

Power Connector Signal Assignments for DD11-CK

. . .

. . . . . .

oo
.

. .

. . . . . .

.. .. .. ...

3-1

4-3

4-5

. . . . . . . . . ... .. .. ...

4-7

4-3

10-Pin 3M Connector Signal Designations

4-4

M9301-YA ROM Starting Address Selection

. . . . . . . . . ... .. ... 4-16

4-5

M9301-YB ROM Starting Address Selection

. . . . . . . .. ... .. ... 4-17

4-6

M9301-YF ROM Starting Address Selection

. . . . . . . ... . ... ... 4-17

4-7

DL11-W Switch Functions

. . . . . . . . . . . . . .. ...

. 4-23

4-8

Switch Settings for MS11 Address Assignments

MM11-CP Memory Address Selection

. . . . . . . . .. ... ... ..... 4-26

4-10

MMI11-DP Memory Address Selection

. . . . . . . . . . . ... .. ... .. 4-26

5-1

PDP-11/34 Diagnostics

. . . . . .. . ... .. ... 4-25

. . . . . . . . . . . . e 5-24

vii

CHAPTER 1
INTRODUCTION

1.1 SCOPE
This manual is intended to provide an introduction to the PDP-11/34 computer system and present the
information required by the user for configuration, installation, operation, familiarization with system
components, and limited troubleshooting procedures.

The basic PDP-11/34 (Figure 1-1) includes a simple operator’s console which does not contain a
switch register and light display. Communication between the user and computer is implemented via
the system terminal. A special bootstrap /terminator module allows the terminal to simulate the function of a traditional programmer’s console.

8141-21

Figure 1-1

PDP-11/34 Computer System

A version of the 11/34, designated 11/34A, was developed to accommodate a floating point option
(FP11-A). Functionally, the 11 /34 and 11/34A are the same. The physical differences are as follows.

The 11/34 system includes the KD 11-E central processor (M7265 and M 7266 modules) and an M8264

Sack Timeout module.

1-1

The 11/34A system uses the KD11-EA central processor, consisting of the M8265 and M8266 mod-

ules. The new module set is a functional equivalent of the KD11-E version with modifications to
include the sack timeout circuitry and the required connections for the floating point option. The
capabilities of the power supplies have been increased to accommodate the floating point unit.
Unless specified otherwise, all references to 11/34 in this manual apply to both variations.
1.2 SYSTEM DESCRIPTION
The PDP-11/34 computer system comprises modular units that can be configured to suit the customer’s application. The basic PDP-11/34 consists of the following equipment.

Central processor (KD11-E or KD11-EA)
Operator’s console (KY11-LA)
Bootstrap/terminator (M9301-YA, YB, YF)
Unibus
Unibus terminator (M 9302)
Core (MM11-CP, DP) or MOS (MS11-EP, FP, JP) memory
Mounting box (BA11-L or BA11-K)
Backplane (DD11-PK)
M8264 Sack Timeout module (11/34 only)
Parity controller (M 7850)

Optional equipment available for the system includes:
Programmer’s console (KY11-LB)
Serial line unit/real-time clock (DL11-W)
Battery backup unit for MOS memory (H775)
Standard PDP-11 peripherals
Expander backplane (DD11-CK, DK).

Figure 1-2 illustrates a block diagram of the PDP-11/34.

CENTRAL
PROCESSOR

TERMINATOR

UNIBUS

(M9302)

KD11-E (EA)

OPERATOR'S
CONSOLE
(KY11-LA)

»{

BOOTSTRAP/
TERMINATOR
(M9301)

MEMORY

CORE (MM11)
OR

INTERFACES
TO PERIPHERAL

MOS (MS11)

DEVICES

11-5450

Figure 1-2

System Block Diagram

1-2

1.2.1

Unibus

All components of the PDP-11/34 computer system, including peripheral devices, are connected to
and communicate with each other on a single high-speed bus known as the Unibus (Figure 1-1).
All devices on the Unibus communicate in the same manner. Addresses, data, and control information
are sent along the 56 lines of the bus. Each Unibus device, including Processor registers, Peripheral
Device registers, and memory locations, is assigned an address on the bus. Therefore, the central
processor can access and manipulate Peripheral Device registers as easily as memory. (A detailed

description of the Unibus can be found in the Unibus Interface Manual or the PDP-11/34 Processor

Handbook.)

The PDP-11/34 computer system contains both standard and modified Unibus connections. The modified Unibus is similar to the standard Unibus except that certain pins have been redesignated to allow
installation of memory modules in particular backplane slots (Paragraph 4.2.2.2).
1.2.2

KDI11-E (EA) Central Processor

The KD11-E Central Processor Unit (CPU), designed for the PDP-11/34 computer series, is contained
on two multilayer, hex-height modules, M7265 (Figure 1-3) and M7266 (Figure 1-4).

Figure 1-3

KDI1I1-E Central Processor Unit (M7265 Module)

1-3

8107-1

Figure 1-4

KD11-E Central Processor Unit (M7266 Module)

The KD11-EA CPU, designed for the 11/34A, is contained on two multilayer, hex-height modules,
M8265 and M8266.
The KD11-E (EA) connects to the computer system via the Unibus. The processor controls the time
allocation of the Unibus for peripherals, and performs arithmetic operations, logic operations, and
instruction decoding.

The Extended Instruction Set (EIS) is a standard feature of the KD 11-E which provides the capability
of performing hardware fixed-point arithmetic and allows direct implementation of multiply, divide,
and multiple shifting. This feature allows double-precision 32-bit words to be processed.
The KD11-E also contains memory management logic which provides memory extension, relocation
and protection. This allows the user to:

Extend memory space from 28K to 124K.

Allow efficient memory segmentation for multi-user environments.

Provide effective protection of memory segments in multi-user environments.

1.2.3 Operator’s Console
The operator’s console provides a front panel communication link between the user and computer.
Unlike the traditional programmer’s console, a minimum number of switches and lights are contained
on the operator’s console (Figure 1-9).

8107-25

Figure 1-5

Operator’s Console

The three switches on the console are as follows.

Power

3-position rotary switch
DC OFF, DC ON, STNDBY

HALT/CONT

2-position toggle switch

HALT and CONTINUE

BOOT/INIT

Spring-action momentary switch that is normally in the BOOT position
BOOT and INITIALIZE

The three indicators on the console are as follows.

1.2.4

BATT

Monitors conditions of battery

DC ON

Indicates presence of dc logic power

RUN

Indicates, when lighted, that the processor is in the RUN state or, when light
is off, that the processor has halted.

M9301 Bootstrap/Terminator

The PDP-11/34 contains a special terminator module (M9301) that contains the required Unibus
terminator resistors and 512 words of read-only memory (ROM). The M9301 is a double-height,
extended module (Figure 1-6) that is available in three versions: M9301-Y
A, suited to the OEM user,
M9301-YB, suited to the end user, and M9301-YF, suited to the OEM or end user.

The ROM in the M9301 contains diagnostic routines for verifying computer operation, several bootstrap loader programs for starting up the system, and the console emulator routine for issuing commands from the console terminal. The M9301 provides the PDP-11/34 with the capability of using a
console terminal to replace the functions normally controlled through the programmer’s console. A
serial I/O terminal such as an LA36 DECwriter, VT50 Video Terminal, or an LT33 Teletype® and
associated controller, when used in conjunction with the M9301, can be added to the system to provide
most programmer’s console functions.
Refer to the M9301 Bootstrap/ Terminator Maintenance Manual for a complete description of the
M9301.
®Teletype is a registered trademark of Teletype Corporation.

1-5

8107-17

Figure 1-6

M9301 Bootstrap/Terminator Module

1.2.5 M9302 Terminator
The M9302 terminator is a double-height module (Figure 1-7) and must be installed at the end of the
Unibus (furthest from the processor) in all PDP-11/34 systems. This module contains terminating
resistors and additional logic which generate a BUS SACK signal if a processor GRANT signal ever
reaches the end of the Unibus.

1-6

8107-7

Figure 1-7

M9302 Terminator Module

1.2.6 Memory
The PDP-11/34 computer system is designed to operate with both MOS memory and core memory.

The MOS memory is available in 4K, 8K, or 16K (MS11-EP, MS11-FP, or MS11-JP) increments and
each memory module consists of a single hex-height board (Figure 1-8). The MOS module contains an
interface to the Unibus, timing and control logic, refresh circuitry, and an MOS storage array. (Refer
to the MS11-E-J
MOS Memory Maintenance Manual for a detailed description.) MOS memory is
volatile and data is lost when power is removed. An optional battery backup unit (H775) is available
that can supply the power required to preserve data in memory when system power is lost. When the
system is operating in the battery backup mode, power is used for MOS memory refresh only.

1-7

R m

8107-12

Figure 1-8

MS11-JP MOS Memory Module

Core memory is available in 8K or 16K (MM11-CP or MM11-DP) increments. The MM11-CP (Figure 1-9) consists of a hex-height, multilayer motherboard (G651) and a quad-height, bilayer
daughterboard (H221). The MM11-DP (Figure 1-10) consists of a hex-height, multilayer motherboard
(G652) and a hex-height, bilayer daughterboard (H222). The motherboard is inserted into the Unibus
backplane and contains the Unibus interface logic, timing and control logic, X-Y drivers, and inhibit
and sense circuitry. The daughterboard is attached to the motherboard and contains the core plane,
stack diodes, and stack charge circuit. Core memory is not volatile and data will not be lost when

system power is removed. (Refer to the associated memory manual for detailed information.)

1-8

1.2.7 Mounting Box, Backplane, and Power Supply
The PDP-11/34 system utilizes either the BA11-L [13.3 cm (5-1/4 inch) chassis] or BA11-K [26.6 cm
(10-1/2 inch) chassis] mounting box. The BA11 houses the DD11 backplane and the power supply.
The mounting box is divided into two sections, one containing all logic modules and the other containing the power supply. The operator’s console assembly (KY11-LA) mounts on the front of the BA11
frame.

The DD11-PK backplane, implemented in the PDP-11/34, provides the electrical connections between
the modules in the system. The DD11-PK consists of nine hex-height slots for module placement.
The H777 power supply is used with the BA11-L mounting box and the H765 power supply is used
with the BA11-K mounting box. For cabinet-mounted PDP-11/34 systems, the 861 AC Power Con-

troller is implemented. The 861 is used to control and distribute ac voltage to the power supplies, fans,
and other electrical devices (within each cabinet) that require ac inputs within the system.

8107-11

Figure 1-9

MMI11-CP Core Memory Module

1-9

Figure 1-10

MM11-DP Core Memory Module

M7850 Parity Controller (Figure 1-11) - The M7850 Parity Controller is a double-height module that
generates and checks parity on stored data in memory. This module also contains a 16-bit Control and
Status register for diagnostic purposes.

8107-20

Figure 1-11

M7850 Parity Controller

1.2.8 Optional Equipment
The following options can be incorporated to expand system capabilities and meet specific requirements of the user.

DL11-W Serial Line Interface and Real-Time Clock (Figure 1-12) - The DL11-W provides an asynchronous serial line interface to an ASCII terminal (e.g., LA36, VT50, or LT33) and a line frequency

clock. The serial line interface can handle data rates from 110 to 9600 baud and provides serial-toparallel (and vice versa) data conversion for information transfer to or from the Unibus. The line clock
senses the 50- or 60-Hz line frequency for internal timing and is program compatible with the standard
line clock option (KW 11-L) used with other PDP-11 computers.

Figure 1-12

DL11-W Serial Line Interface and Real-Time Clock

1-12

KY11-LB Programmer’s Console (Figure 1-13) - The PDP-11/34 programmer’s console contains a
7-segment LED display and a keypad for entering and verifying data as well as controlling basic
computer operations. The programmer’s console can also be used in a maintenance mode which provides several hardware maintenance features (Appendix A). The console interfaces to the Unibus via a

TR
G

quad-height module (M 7859).

2
»

»
)
23

8141-15

Figure 1-13

KY11-LB Console and Interface Module

1-13

H77S Battery Backup Unit - If system power is interrupted, the battery backup unit provides auxiliary

power to preserve the contents of up to 32K words of MOS memory for about two hours. This
auxiliary power unit is a battery that is charged by the main ac power when the computer system is
operating normally. The battery backup unit is physically mounted outside the processor box to facilitate battery maintenance. The battery backup option is not available in PDP-11/34 systems using the
BA11-K mounting box.
Expander Backplane - The DD11-CK (4-slot) and DD11-DK (9-slot) backplanes can be implemented
by the user to expand the basic system. These expander backplanes allow greater flexibility for system
configuration.

Standard PDP-11 Peripherals - The 1/O capabilities of the PDP-11/34 system can be expanded
through the implementation of such standard PDP-11 peripheral devices as card readers, alphanumeric display terminals, line printers, teletypewriters, or high-speed paper tape readers. Available
storage devices include magnetic tapes and disk memories.
1.3 RELATED LITERATURE
For detailed information concerning each of the system components, refer to the following documents.

Manual

Document Number

BA11-K Mounting Box Manual
BA 11-L Mounting Box Manual
DL11-W Maintenance Manual
KD11-E Processor Manual (PDP-11/34)
M9301 Bootstrap Terminator Maintenance Manual
MMI11-C/CP Core Memory Manual
MM11-D/DP Core Memory Manual
MS11-E-J MOS Memory Maintenance Manual
PDP-11 Peripherals Handbook
PDP-11/34 Processor Handbook .
KDI11-EA Processor Manual (PDP-11/34A)

EK-BA11K-MM
EK-BAI11L-MM
EK-DL11W-MM
EK-KDI11E-TM
EK-M9301-MM
EK-MM11B-TM
EK-MM11D-TM
EK-MSI11E-MM
EP-PDP11-HB
EP-11034-HB
EK-KDIEA-MM

1-14

CHAPTER 2

OPERATION

2.1
OPERATOR’S CONSOLE (KY11-LA)
In the PDP-11/34 system, communication between the user and computer is provided by the operator’s console. The M9301 bootstrap/terminator allows the operator’s console, in conjunction with an
ASCII terminal, to provide programmer’s console functions to the user.

8107-25

Figure 2-1

2.1.1

PDP-11/34 Operator’s Console

Console Switches

The operator’s console contains three switches: power, HALT/CONT, and BOOT/INIT. The function of each switch and its effect on system operation is explained as follows.
Power (3-position rotary switch)

DC OFF

DC power is removed from the system; contents of MOS memory are 10st
and fans are off.

DC ON

Power is applied to the computer system.

STNDBY

Standby; dc power to the computer is off, but dc power is applied to MOS
memory (to avoid data loss).

NOTE
STNDBY position is not functional in the BA11-K
box.
WARNING
The DC OFF position does not remove ac power
from the system. AC power is removed only by dis-

connecting the line cord.

HALT/CONT (2-position toggle switch)

HALT

The program is stopped. The system (including console emulator functions)

CONT

The program is allowed to continue.

cannot be run in this position.

NOTE
If the program causes the system to halt, the switch
must first be placed in the HALT position and then
moved to the CONT position to resume operation.

BOOT/INIT (Spring-action momentary switch that is normally in the BOOT position)
INIT

When this switch is pressed to INITialize and then released (returned to

BOOT position), an operation will be performed depending on the setting of
the HALT/CONT switch and the M9301 switch settings (Paragraph 4.3.2).
If the HALT/CONT switch is in the HALT position when BOOT/INIT is
pressed and released, only the processor will be initialized and Peripheral
Device registers will not be cleared.
[f the HALT/CONT switch is in the CONT position when BOOT/INIT is
pressed and released; the processor will be initialized, Peripheral Device registers will be cleared, and the M9301 program will be executed.
NOTE
The BOOT operation is only initiated if the
BOOT/INIT switch is pressed and released. Holding the switch in the INIT position will cause a con-

tinuous initialize.
- CAUTION
Pressing the BOOT/INIT switch to the INIT position while running a program will abort the program
in progress and may destroy general register and
memory contents.

2.1.2

Console Indicators

The three indicators (BATT, DC ON, and RUN) on the operatdr’s console provide the following
information to the user.

BATT

Off

Battery voltage is below the minimum
level required to maintain the contents
of MOS memory, or the battery is not
present in the system.

Slow flash
(1 flash/2 seconds)

Battery is charging and the voltage is
above the minimum level required to
maintain contents of MOS memory if
power is removed. The amount of
time that memory will be retained will
depend on the degree of discharge of
the battery. The flash rate is fixed and
does not vary with the charge rate of
the battery.

Fast flash
(10 flashes/second)

Indicates that primary power has been
lost and the battery is discharging
while maintaining MOS memory con-

tents. The flash rate is fixed and does
not indicate the charge level remaining on the battery.

DC ON

RUN

Continuous on

Battery is present and fully charged.

Indicates that dc power is applied to
the logic but does not imply that the
power is within the required levels.

Off

DC power is off.

Indicates either:
1. Processor is executing, or

2. Processor is attempting to run but
is disabled due to a system failure.
Off
2.1.3

Processor has halted.

Console Emulator

The M9301 module contains a console emulator routine in ROM memory. This routine allows the
operator to use a console terminal to generate functions similar to those provided on the traditional
programmer’s console. The console emulator allows the user to perform LOAD, EXAMINE, DEPOSIT, START, and BOOT functions by typing in the appropriate code on the keyboard. The M9301
also contains non-destructive CPU diagnostic tests which are performed prior to entering the console
emulator and additional CPU and memory diagnostics executed prior to entering a boot routine.

The following is a summary of the console emulator functions.

LOAD

Loads the address to be manipulated into the system.

EXAMINE

Allows the operator to examine the contents of the address that was loaded.

DEPOSIT

Allows the operator to write into the address that was loaded and/or
examined.

START

Initializes the system and starts execution of the program at the address
loaded.

BOOT

Allows the booting of a specified device by typing in a 2-character code and
unit number (if required). If a number is not typed, the default number will
be zero.

2.1.3.1 Entry Into the Console Emulator - In order to enter the console emulator, the M9301 bootstrap/terminator switches must be properly set. (Refer to Paragraph 4.3.2 to determine the correct
switch settings.)
The console emulator can be entered in the following ways depending on the setting of the M9301
switches.
1.
2.
3.
4.

Move the power switch to the DC ON position.
Press and release the BOOT/INIT switch.
Automatic entry on return from a power failure.
Load address and start (via programmer’s console).

2.1.3.2 Register Printout - Once the console emulator routine has started, a series of numbers representing the contents of RO, R4, SP, and “OLD PC” respectively, will be printed by the terminal. This
sequence will be followed by a $ on the next line. The following is an example of the printout. (X
signifies an octal number, 0-7.)

XXXXXX

$
RO

R6
STACK POINTER
(SP)

“OLD PC”
PROGRAM
COUNTER

PROMPT CHARACTER
on next line
NOTE
Whenever there is a power-up microroutine, or the
BOOT/INIT switch is released from the INIT position, the current PC will be stored in RS. The contents of RS are printed out as shown above (noted as
“OLD PC”).

2-4

When the BOOT/INIT switch is pressed and released, the system will print out RO, R4, SP, and “OLD
PC” followed by a prompt character, as previously described. This feature is especially valuable when
the system has halted unexpectedly. The operator can determine where the system has halted by examining the “OLD PC” and subtracting two.

CAUTION
Pressing the BOOT/INIT switch may alter the con-

tents of the General Purpose registers and make it
impossible to continue the program.

2.1.3.3 Console Emulator Functions - As previously mentioned, the console emulator can be used to
perform LOAD, EXAMINE, DEPOSIT, START, and BOOT functions. Once the system has been
powered up or initialized via the BOOT/INIT switch and RO, R4, SP, “OLD PC” and $§ have been
printed, the console emulator is entered.
The following symbols are used in the discussion of the keyboard input format:
Space bar: (SB)
Carriage return key: (CR)
Any number 0-7 (octal number) key: (X)

The capital letters L, E, D, and S on the keyboard are used to perform the functions LOAD, EXAMINE, DEPOSIT, and START, respectively. The keyboard input format required to perform each of
the functions is as follows.
Function

Format

Load Address

(SB)(X)(X) (X)(X)(X)(X)(CR)

Examine address loaded

(SB)

Deposit contents into address loaded

(SB) (X)(X) (X)(X) (X)(X)(CR)

(CR)

and/or examined
Start program

The first octal number that is typed (X) will be the most significant digit and conversely the last
number typed will be the least significant digit. The console emulator routine can accept up to six octal
numbers in the range of 0-32K (word locations). The lower 28K of memory and the 4K 1/0 page can
be directly manipulated by the console emulator. If all six octal numbers are input, the most significant
number must be a zero or a one. When an address or data word contains leading zeros, the leading
zeros can be omitted when loading the address or depositing the data. Refer to Appendix B for the
‘procedure required to examine and deposit in locations above 28K.
NOTE
1.

The console emulator will accept octal numbers
only (i.e., typing 8 or 9 within the address will

cause the entire address to be ignored).

The console emulator will accept even addresses
only (i.e., the least significant digit must be a 0,

2,4, or6).
3.

The General Purpose registers (GPR) cannot
be addressed from the console emulator.

2-5

2.1.3.4 Examples of Console Emulator Operation - The following example implements the LOAD,
EXAMINE, DEPOSIT, and START functions.

AN
h W —

If the operator wishes to:
Turn on power

Load address 700
Examine location 700
Deposit 777 into location 700
Examine location 700
Start at location 700

The operator performs the following:

1.
2.
3.
4.
5.
6.

Operator

Terminal Display

Turns on power
L(SB)700(CR)
E(SB)
D (SB)777 (CR)
E(SB)
S(CR)

XXXXXX XXXXXX XXXXXX XXXXXX
$ L 700
$ E 000700 XXXXXX
$ D777
$ E 000700 000777
$S

Successive examine operations are permitted using the console emulator. Successive examine commands issued by the operator will cause the address to increment by two and will display consecutive
addresses and the contents of each.
The following example examines addresses 500 through 506.

Operator

Terminal Display

L (SB) 500 (CR)
E (SB)
E (SB)
E (SB)
E (SB)

$ LS00
$ E 000500 XX XXXX
$ E 000502 XXXXXX
$ E 000504 XXXXXX
$ E 000506 XXXXXX

Successive deposit operations are also permitted using the console emulator and the address will also
increment by two with each deposit command.

The following example deposits 60 into location 500, 2 into location 502, and 4 into location 504.
Operator
L (SB) 500 (CR)

D (SB) 60 (CR)

D (SB)2 (CR)
D (SB) 4 (CR)

Terminal Display
$ LS00

$ D60
$D2
$D4

Alternate deposit-examine operations are permitted but the address will not increment after each
command is typed. The address will contain the last data that was deposited.

The following example loads address 500, deposits 1000, 2000, and 5420 in that address, and then
examines location 500 after each deposit:

Operator

Terminal Display

L (SB) 500 (CR)
D (SB) 1000 (CR)
E (SB)
D (SB) 2000 (CR)
E (SB)
D (SB) 5420 (CR)
E (SB)

$ L 500
$ D 1000
$ E 000500 001000
$ D 2000
$ E 000500 002000
$ D 5420
$ E 000500 005420

2.1.3.5 Booting from Peripheral Devices - The console emulator can be used to input bootstrap routines from peripheral devices. Once the prompt character (§) has been displayed on the terminal (as a
result of power-up or activating BOOT /INIT switch), the system is ready to load a bootstrap routine
from the selected device. The following procedure is implemented to boot from the keyboard:
1.

Locate the 2-character code that corresponds to the peripheral to be booted (Tables 2-1 and
2-2).

Table 2-1

Bootstrap Routine Codes for M9301-YA and M9301-YB

Device

Description

Boot Command

RK11
RP11
TCI1
TTM 11
TA1l
RX11

Disk cartridge
RPO02/03 disk pack
DECtape
800 bits/inch magtape
Magnetic cassette
Diskette

DK
DP
DT
MT
CT
DX

DLI11

Terminal reader

PCl11

Paper tape reader

RJS03/04*
RJP0O4*
TJU16*

Massbus fixed-head disk
Massbus disk pack
Massbus tape drive

DS
DB
MM

RJS03/04,

Mixed combination of

RJPO4, or TJU 16*

Massbus devices

*Devices supported by M9301-YB (end-user version) only.

2-7

Table 2-2

Bootstrap Routine Codes for M9301-YF

Device

Description

Boot Command

RK11
RPI11
TCl11
TMI11
RX11
DL11
PCl11
RJS03/04
RJP04/05/06
TJU16
RK611

RKO03/05 disk cartridge control
RP02/03 disk pack control
TUS56 DECtape control
TU10 magtape control
RXO01 diskette control
Terminal reader control
Paper tape reader control
Massbus fixed-head disk
Massbus disk pack
Massbus tape drive
RKO06 disk drive control

DK
DP
DT
MT
DX
TT
PR
DS
DB
MM
DM

NOTE
The user can boot from a peripheral directly upon

power up (M9301-YA or M9301-YF versions only)
provided the switches on the M9301 module are set
properly (Paragraph 4.3.2).

Load medium (paper tape, magtape, disk, etc.) into the peripheral, if required.
Verify that the peripheral indicators signify that the peripheral is ready (if applicable).

Type the 2-character code obtained from Table 2-1.

If more than one unit of a given peripheral exists, type the unit number to be booted (0-7). If
a number is not typed, the default number will be 0.
6.

Type (CR); this initiates the boot.

The following points should be remembered before attempting to boot from a peripheral device.
.

The medium (paper tape, disk, magtape, etc.) must be placed in the peripheral prior to
booting.

The machine will not be under control of the console emulator after booting.
The program that is booted must be:
a.

Self-starting, or

Restartable after the console emulator is recalled.

Actuating the BOOT/INIT switch will always abort the program being run. The contents of
the General Purpose registers (R0-R7) may be altéred.

2.1.3.6 Possible Operator Errors - This paragraph discusses the effect of erroneously pressing the
BOOT/INIT switch and solutions to incorrect entries of information to the console emulator routine.

As previously mentioned, pressing the BOOT /INIT switch while a program is running will cause that
program to be aborted. All devices that respond to system INIT will be cleared and the contents of all
General Purpose registers may be modified. The console emulator will be activated (possible on
M9301-YA, YB, or YF versions) or a peripheral routine will be booted (possible on M9301-YA or YF
versions only). Critical data in the user’s system will probably be lost and the possibility of retrieving
that data will depend on the user’s program.

Table 2-3 lists possible operator errors that may be encountered when implementing the LOAD,
EXAMINE, DEPOSIT, or START functions.

NOTE

If an entry has not been completed and the user realizes that an incorrect character has been entered, the
user can press the rubout or delete key and delete the
entire entry.

Table 2-3

Load, Examine, Deposit, and Start Errors

Error

Result

L, E, S, or D was followed by a key other than
space bar (SB).

Terminal display will return a prompt character ($)
to signify an unknown code.

An illegal number (8 or 9) or incorrect alpha
key (Y) is typed after the correct load

Upon receipt of the illegal number or alpha key,
the entire address will be ignored and $ will be

sequence.

returned.

The most significant octal number in a 6-bit

The address will be loaded but the most significant
digit will be interpreted as follows:
Number typed (number accepted)
7(1), 6(0), 5(1), 4(0), 3(1), 2(0).

address i1s greater than 1.

An extra (seventh) octal number is typed.

Any size word will be accepted but only the last six
digits typed will be remembered.

A memory location is loaded whose address is

No errors will result unless a deposit, examine, or
start is attempted.

nonexistent.

Examine, start, or deposit is attempted at an

The system will halt when (SB) is executed.

odd memory location or at a nonexistent
memory location.
Examine is performed without loading an
address prior to the first examine.

Examination of an unknown address will be performed and possibly the system could try to access
a nonexistent address.
NOTE
If a legal address is examined, the address
and data will be typed out. If address is
illegal, the computer will halt.

Table 2-3

Load, Examine, Deposit, and Start Errors (Cont)

Error

Result

Start is performed without loading an address
prior to starting.

Start at an unkown location will occur.

Deposit is performed without previously
loading an address or without knowing what
address had been previously loaded.

Data will be written over and lost or machine will
halt.

2.2 PROGRAMMER’S CONSOLE (KY11-LB)
The optional PDP-11/34 programmer’s console (KY11-LB) provides all the standard functions
required for entering and verifying data as well as controlling basic computer operations. The programmer’s console can also be used in a maintenance mode that provides several hardware maintenance features. (Refer to Appendix A for a discussion of the KY11-LB operation in the maintenance
mode.) The KY11-LB contains a 20-pushbutton keypad for operator/programmer control, 6 indicator
LEDs for monitoring system status, a 6-digit display for address or data, and a dc power switch. The
programmer’s console interfaces to the Unibus via a quad-height module (M7859) which must be
installed in the processor backplane. Refer to the Programmer’s Console (KY11-LB) Maintenance
Manual for a detailed discussion.

aUN

S8 DISP

BUS ERR

MAINT

8107-3

Figure 2-2

PDP-11/34 Programmer’s Console

2.2.1

KY11-LB Controls and Indicators
The following provides a brief functional description of the 6-digit display, indicators, and the pushbutton keyboard provided on the programmer’s console. The.dc power switch and the BATT, DC ON,
and RUN indicators function in the same manner as described for the operator’s console (Paragraphs
2.1.1 and 2.1.2).

Display

The 7-segment display represents the current address or the con-

tents of the current address. Each segment of the display will
contain an octal digit (0-7). Six-digit numbers are generated as
octal digits and are entered from the right and left-shifted.

2-10

Indicators

SR DISP

Switch Register Display - Indicates, when on, that the contents
of the Switch register (address 777570) are being displayed.

MAINT

Maintenance - Indicates, when on, that the console is operating
in maintenance mode.

BUS ERR

Bus Error - Indicates, when on, that an examine or deposit
resulted in a SSYN timeout, or that HALT GRANT was not
received after a HALT REQUEST was issued.
NOTE
This indicator reflects a bus error by the console
only. The indicator does not reflect bus errors due
to other devices such as the processor.

Pushbutton Keys

0,1,23,4,5,6,7

Allow the operator to enter data (octal digits) into the display.

LSR

Load Switch Register - A copy of the contents of the display are
placed in Unibus address 777570.

LAD

Load Address - The contents of the display become the current
address. The display is cleared when LAD is pressed.

DIS AD

Display Address - The current address is displayed. The next
examine or deposit will occur at the address displayed.

CLR

Clear - The display is cleared in preparation for entry of new
data via the number keys.

EXAM

Examine - A copy of the data contained in the location specified by the current address is placed in the display. This key is
operative only if the processor is halted.

DEP

Deposit - A copy of the data being displayed is transferred to
the location specified by the current address. This key is operative only if the processor is halted.

CNTRL

Control - The control key is used in conjunction with other keys
to provide certain functions. The requirement of having both
CNTRL and the second key pressed at the same time prevents
accidental use of these functions.

The following pushbutton keys must be used in conjunction with the CNTRL key to provide the
function described. In each case, the CNTRL key must be pressed first and held down while the second
key is pressed.

INIT (with CNTRL)

Initialize - Causes BUS INIT L to be generated for 150 ms. Key
is operative only if processor is halted.

2-11

HALT/SS (with CNTRL)

Halt/Single Step - Halts the processor if the processor is running. To single instruction step the processor, halt the processor, then press the HALT/SS key without pressing the CNTRL
key. After a halt, the display will contain the contents of R7
(program counter).

CONT (with CNTRL)

Continue - Allows the processor to continue from a halted state
using its current program counter. The contents of the Switch
register are displayed.

START (with CNTRL)

This key is operative only if the processor is halted. The function causes the program counter (R7) to be loaded with the current address. BUS INIT L is then generated and the processor is
allowed to run. Switch register contents are then displayed.

BOOT (with CNTRL)

Causes the M9301 bootstrap/terminator to be activated if present in the system. Console will boot only if processor is halted.

No. 7 (with CNTRL)

When the No. 7 key and CNTRL key are both pressed, the

current address plus the value presently being displayed plus 2
are added together. The result is then displayed. This function
allows the console to calculate the correct offset address when
mode 6 or 7, register 7 instructions are encountered. The
required index must be in the display so that when the keys are
pressed, the index will be added to the PC+2. The offset address
is then displayed.
No. 6 (with CNTRL)

When the No. 6 key and CNTRL key are both pressed, the
contents of the Switch register are added to the value presently
being displayed. The result is then displayed. This function
allows the console to calculate the correct offset address when
mode 6 or 7 instructions that do not use register 7 are encountered. To implement this function, it is easiest to put the index in
the Switch register, then examine the general register that contains the base address, thereby placing the base address in the
display. Then, when the No. 6 key and CNTRL key are both
pressed, the index and base address will be added and the correct offset address will be displayed.

No. 1 (with CNTRL)

Maintenance Mode - This key combination puts the console in
maintenance mode. When the console is in maintenance mode,
normal console mode keypad functions are not available (Refer
to Appendix A for a description of the maintenance mode keypad functions.) The CLR key causes the console to exit from
maintenance mode and enter console mode via a processor halt.

2.2.2 Notes on Operation
The input format required to perform each of the functions previously described is shown as follows.
(X denotes an octal number, 0-7.)
XXXXXX
XXXXXX
XXXXXX

LSR
LAD
DEP

2-12

Note that, unlike the operator’s console, the data must be entered before the function key is pressed.
Prior to entering a new 6-digit number, if the display is non-zero, the clear key (CLR) should be
pressed to initially zero the display. If the display is not cleared, the new data will be left-shifted into
the existing data and may result in an erroneous number in the display.
An erroneous display will also result if, while the processor is running and the Switch register is being
displayed, a numeric key (0-7) is pressed. Although the SR DISP indicator will be on, the display will
no longer reflect the actual contents of the Switch register. If any time while the processor is running
the operator wishes to examine the contents of the Switch register, the CNTRL and CONT keys
should be pressed simultaneously. This action will not affect processor operation.
The console requires an 18-bit address. This is especially important to remember when accessing
Device registers (i.e., 777560 must be input rather than 177560 to address a Device register). If the 18bit address i1s not used, access to memory or to a nonexistent address will occur.

In order to single instruction step the processor from a given starting address, the program counter
(R7, Unibus address 777707) must be loaded with the starting address. For example, to single instruction step the processor from the beginning of a program starting at location 1000, the following
sequence is required:
777707

LAD

1000

DEP

INIT (With CNTRL pressed)
HALT/SS
HALT/SS
etc.

The above procedure is required only if the program counter does not already contain the desired

address.
2.2.3
Examples of Programmer’s Console Operation
The following example implements the load address, load switch register, deposit, examine, display

address, start, halt, continue, and single instruction step functions. To demonstrate these functions, the
following program is loaded into memory.
PROGRAM

1000

12737

1006
1010
1021

00240
00240
00137

177777

01000

1016

START:

MOV #177777,@#1016

:LOAD LOCATION 1016

NOP
NOP
JMPSTART

;DO NOTHING
;DO NOTHING
;LOOP

The program is loaded into memory by depositing the following data into each associated memory
address.
Address

Data (instruction)

1000

012737

1002
1004
1006
1010
1012
1014
1016

177777
001016
000240
000240
000137
001000
000000

The data is loaded by first loading address 1000, and then making successive deposits. Note that the
processor must first be halted if the RUN indicator is on (EXAM and DEP keys are operative only if
the processor is halted).
Operator Input

Display

HALT/SS (with CNTRL pressed)
(if processor is running)
CLR
1000 LAD
12737 DEP and then CLR
177777 DEP and then CLR
1016 DEP and then CLR
. 240 DEP and then CLR
240 DEP and then CLR
137 DEP and then CLR
1000 DEP and then CLR
DEP
DIS AD

000000
000000
012737 and then 000000
177777 and then 000000

001016 and then 000000
000240 and then 000000
000240 and then 000000
000137 and then 000000
001000 and then 000000
000000
001016

Successive deposit operations cause the address to be incremented by 2. Note that the display must be
cleared (if it is non-zero) before entering new data. Successive examine operations can also be performed. Again, the address is incremented by two after each successive examine.
NOTE

If the address is in the range 777710-777717 (address of general registers), successive examine will
increment the address by one.

2-14

To verify that the above data has been deposited correctly, load address 1000 and perform successive
examines as follows:
Operator Input

Display

CLR
1000 LAD
EXAM
EXAM
EXAM

000000
000000
012737
177777
001016

Once the program has been loaded and verified, the program can be started, continued, halted and
single instruction stepped. To demonstrate these functions, first load the Switch register with 125252
and then load the program starting address (1000).
Operator Input
125252 LSR
CLR
1000 LAD

Display

START (with CNTRL pressed)

125252
000000
000000

125252

CLR

000000

HALT/SS
HALT/SS
HALT/SS
HALT/SS
HALT/SS
HALT/SS
CLR
001016 LAD
EXAM

001012
001000
001006
001010
001012
000000
000000
177777

CONT (with CNTRL pressed)
HALT/SS (with CNTRL pressed)

125252
001006
001010

Display shows contents of Switch register.

Display shows contents of Switch register.
*See NOTE

Result of instruction at address 1000.

NOTE

When the processor is halted via the HALT/SS
(with CNTRL) key, the display will shown the current program counter (PC). The display contents will
therefore depend on which instruction is currently
being executed.

When

the single instruction step function
(HALT/SS key) is used, the display will show the
current program counter and the program will be
single instruction stepped from that location.

Refer to the KY/I-LB Maintenance Manual for a more detailed discussion of the programmer’s console operation.

2-15

CHAPTER 3

FUNCTIONAL SYSTEM DESCRIPTION

3.1

GENERAL

This paragraph provides a description of the interaction between PDP-11/34 system components.

Figures 3-1 and 3-2 are block diagrams of the system showing interconnecting signals for the BA11-L

and BA11-K mounting boxes, respectively.
3.1.1

Halt-Continue Function

The operator’s console can be used to halt the processor via the HALT/CONT switch. When the
HALT/CONT switch is moved to the HALT position, the console asserts the signal HALT RQST L
which is recognized by the processor like a BUS request. The HALT request is therefore serviced

according to its priority. The order of priority for all BUS requests and other traps is listed in Table 3I. The processor responds to HALT RQST L by inhibiting the processor clock and returning the signal
HALT GRANT H to the console. HALT GRANT H causes the console to assert BUS SACK L,
thereby gaining control of the Unibus. BUS SACK L, in turn, causes the processor to drop HALT
GRANT H. The user can keep the processor in the halted state indefinitely. In the halt state, BUS
SACK L and HALT RQST L are asserted. When the HALT/CONT switch is returned to the CONT
position, the console releases BUS SACK L and HALT RQST L and the processor continues
operation.

Table 3-1

Priority Service Order

Priority

Service Order

Highest

Halt (Instruction)
Odd Address
Memory Management Error
Timeout
Parity Error
Instruction Traps
Trace Traps
Stack Overflow
Power Fail
Halt Switch (on console)
BR7
BR6
BRS

BR4

Lowest

Next Instruction Fetch

3-1

———m

om ]|

]—

===

—

w
--

-—

—

o |

— ]

- |

—.

—

S54

alo

21m

3|
(00]

(o30]

—————

181

82|
Wp
\

S
——

R DR
e

— — -

o 2
S

(8]

BOOT SWITCH

POWER UP

| ReBoOT ENABLE

1p, MO0

PERIPHERAL

INTERFACES

[

B
CABLE

C
— CABLE

o)
g

C B}— No. 7011414
CABLE

MEMORY

v
\~ o

CABLE
A — No. 7011411

= E

|
|
L

2
w

________1_,1

c I

VARV,
]

}— CABLE A

TERMINATOR

PROCESSOR

M9302

UNIBUS

CENTRAL

KD11-E (EA)

CABLE B — No. 7011413

H777 POWER SUPPLY

11-5451

Figure 3-1

PDP-11/34 System Interconnections

(BA11-L Mounting Box)
3-3

KD11-E (EA)

CENTRAL

PROCESSOR

TERMINATOR

\__ CABLE A

M9302

UNIBUS

| S—

prs—

a——

o—

pra—"

——

—

——

<Zt

IT)

KY11-LA
-

TB4

TP1

TB5

TB6

TB3

a—

emmm

)

-l

——

p——

TP2

)

| | BooTswiTcH
T
|

| POWER UP
~|/

==~

1
CABLE D —,

)\
- mnl

+5V

-———

GND

1 782

M9301

\/
MEMORY

PERIPHERAL

INTERFACES

> TB1

REBOOT ENABLE

CABLEB

_j—CABLEC
"‘fli—

-—

—

CABLE A — No. 7011411

H765 POWER SUPPLY

CABLE B — No. 7011413

CABLE C — BLUE/BLACK TWISTED PAIR
CABLE D — RED/BLACK TWISTED PAIR
11-5452

Figure 3-2

PDP-11/34 System Interconnections (BA11-K Mounting Box)

3-4

3.1.2 Boot-Initialize Function
The operator’s console activates the M9301 bootstrap/terminator via the BOOT/INIT switch.
BOOT/INIT is a spring-action momentary switch that is normally in the BOOT position. When the
BOOT /INIT switch is pressed to the INIT position, the two signals BUS AC LO L and BOOT SW L
are generated. BOOT SW L is the enabling signal for the M9301. When the switch is released from the
INIT position to the BOOT position, the two signals BUS AC LO L and BOOT SW L allow the
processor to start a power-up sequence. The processor then attempts to read a new processor status
word (PSW) from memory location 26s. Address 263 is logically ORed with the address asserted by the
M9301 (address lines enabled by BOOT SW L) to generate 773026;s. This location is in the M9301
ROM address space and contains the starting address of an optionally selected routine. Once a new
PSW is obtained from location 7730265, the processor attempts to read a new program counter (PC)
from memory location 245. Address 245 is also logically ORed with the address assertd by the M9301
to generate 7730243, also located in the ROM address space. The specific routine initiated by the above
sequence depends on the setting of switches located on the M9301.
NOTE
The PSW obtained from the M9301 (7730265) sets
the priority level of the CPU to 7.

3.1.3 Power-Up Reboot Enable Feature
The Power-Up Reboot Enable switch (S1-2) located on the M9301 provides the user with the option of
automatically rebooting (activating the M9301) whenever the processor is powered up. If the switch is
closed (ON position) and the processor begins a power-up routine, circuitry on the M9301 will be
activated. The power-up sequence that follows will then be the same as that described for the BOOTINIT function (i.e., the PSW and PC will be obtained from the M9301 ROM address space).
If the Power-Up Reboot Enable switch is open, (OFF position) the M9301 will be activated (during a

power-up) only if the signal BOOT ENB is asserted low. BOOT ENB L is generated by the power
supply and is transferred to the M9301 via the operator’s console. Here, the operator’s console functions only as a connector. BOOT ENB L is asserted if the +15 and -15 voltages are lost during battery
backup operation. The voltage loss means that the contents of MOS memory are lost. BOOT ENB L
will remain asserted until the signal BUS AC LO goes high. When BUS AC LO and BOOT ENB are
both asserted low, the circuitry on the M9301 is enabled. When BUS AC LO goes high, the processor
will begin a power-up routine. With the M9301 enabled, the processor will read the program counter
and processor status word from the M9301 ROM address space (Paragraph 3.1.2). This feature allows
the operator to automatically reboot on power up only if MOS memory contents are lost. If MOS
memory has been retained during a power fail (by the battery backup unit) the processor will perform
its normal power-up routine.
NOTE
In systems containing core memory, the black wire
that connects to TP1 on the M9301 must be disconnected and taped. This will disable the power-up
reboot enable feature.

3.1.4 Sack Turnaround Feature
The M9302 terminator provides circuitry that generates a BUS SACK signal if a GRANT signal ever
reaches the end of the Unibus. The bus grant lines (BG4:BG7, and NPG) are ORed on the M9302 to
produce BUS SACK L which is returned to the processor (Figure 3-3). BUS SACK L will cause the
processor to drop the asserted grant line which will in turn cause BUS SACK L to be dropped.

3.2 KY11-LA DETAILED DESCRIPTION
The KY11-LA operator’s console provides the means for controlling dc power (dc power switch),
indicating systems status (BATT, DC ON, and RUN indicators), halting the processor
(HALT/CONT switch) and activating the M9301 (BOOT/INIT switch).

3-5

BUS BG7 H

AU1

A V1

7
BUS BG6 H

9 ) 8837

BA1

_D
E3

8837
BUS BGS5 H

BE2

) 8837

BUS BG4 H BB1

Jses37
HDIWIAINAIN
| =

BUS NPG H

7430

miB
8981
| 3]

! ARZ gussackL

—

8837

il
11-4639

Figure 3-3

M9302 Sack Turnaround Logic

3.2.1
HALT/CONT Switch
This paragraph describes the logic associated with the HALT/CONT switch located on the operator’s
console (Figure 3-4).
The HALT/CONT switch allows the operator to halt the processor and keep it in the halted state as

described in Paragraph 3.1.1. As shown in Figure 3-4, when the HALT/CONT switch is placed in the

HALT position, the HALT RQST flip-flop is direct cleared. This position enables one input of the
open-collector NAND gate that drives the HALT REQUEST L line.

The other input of the NAND gate is enabled if both BUS DC LO L and BUS INIT L are unasserted.
HALT RQST L 1s transmitted to the processor and causes the processor to return HALT GRANT H
to the console (Paragraph 3.1.1). HALT GRANT H direct sets the SACK flip-flop, thereby causing
the operator’s console to assert BUS SACK L. The processor is now halted and the operator’s console

has control of the Unibus. The processor will remain halted as long as BUS SACK L is asserted by the
console. The SACK flip-flop can be cleared (and BUS SACK L dropped) by any of the following
actions:
1.
2.
3.

Bus INITialize
Pressing and releasing the BOOT/INIT switch
Moving the HALT/CONT switch to the CONT position.

When the HALT /CONT switch is moved to the CONT position, the HALT RQST flip-flop is direct

set and HALT RQST L is dropped. The transition of the HALT RQST flip-flop output from clear to
set causes the SACK flip-flop to be clocked. Since the data input is low, the SACK flip-flop clears on
the low-to-high clock transition. When the SACK flip-flop is cleared, the RUN indicator turns on. The
RUN indicator reflects the state of the SACK flip-flop. When the SACK flip-flop is set, the RUN
indicator is off.

3-6

HALT GRANT H 13

o°

BUS SACK L

SACK

r__D

From BOOT/INIT

Switch Logic

L__)—

BUS INIT L

RUN

]

BUSDC LOL

11-4640

Figure 3-4

HALT/CONT Switch Logic

A A

3.2.2 BOOT/INIT Switch
This paragraph provides a description of the logic associated with the BOOT /INIT switch located on
the operator’s console (Figure 3-5).

_AAA

+5V

Cc7

INIT

Birect Clears

SACK FF

—Q

BOOT

['T
|

BUSACLOL

BOOTSW L

11-4635

Figure 3-5

BOOT/INIT Switch Logic

The BOOT/INIT switch allows the operator to activate the M9301 bootstrap/terminator and the
processor (via a simulated power fail) as described in Paragraph 3.1.2. The M9301 is activated by the
signal BOOT SW L, generated by the operator’s console. A power fail is simulated when the operator’s

console asserts BUS AC LO L on the Unibus. This boot sequence also requires that the SACK flip-

flop be cleared. BOOT/INIT is a spring-action momentary switch that is normally in the BOOT
position. Pressing the switch to the INIT position causes the two NAND gates to assert the signals
BUS AC LO L and BOOT SW L (Figure 3-5). The INIT position also causes the capacitor (C7) to be
discharged. When the switch is released to the BOOT position, BUS AC LO L and BOOT SW L are
dropped, thereby allowing the processor to start a power-up sequence. Since the capacitor (C7) charges
through a resistor (R1), a momentary low is maintained across the capacitor. This momentary low
enables the signal that will direct clear the SACK flip-flop.

3-8

3.2.3

DC Power Switch

The dc power switch is a 3-position (DC OFF, DC ON, STNDBY) rotary switch that is always driving
one of three signals to ground. These signals, when not grounded by the switch, are normally pulled
high by the H777 power supply (Figure 3-6). When this switch is used with the H765 power supply,
only the DC ON position is operational. The function of each position is described in Paragraph 2.1.1.

To H765 Power Supply

DCONL

STNBY L

To H777 Power Supply

DC OFF L

11 4636

Figure 3-6

DC Power Switch

3.2.4 Indicators
The operator’s console provides three indicators that monitor system status. The RUN indicator is
discussed in Paragraph 3.2.1. The function of each of the console indicators is described in Paragraph
2.1.2.

The DC ON indicator is a light-emitting diode (LED) with a series current-limiting resistor connected
between +5 Vdc and ground (Figure 3-7).

DC ON

i
+5V

—__L

11-4637

Figure 3-7

DC ON Indicator

The BATT (battery monitor) indicator is a LED driven by the +5 Vdc regulator board in the battery
backup portion of the power supply (Figure 3-8). This indicator is not functional in a system without
battery backup.
BATT

Regulator

\l/‘/

-:15

of H777 Power

Supply
11-4638

Figure 3-8

BATT Indicator

3-9

3.3

M9301 BOOTSTRAP/ROM FIRMWARE

The M9301 bootstrap/terminator contains a 512-word ROM (Read Only Memory). The memory is
composed of four 512 X 4 bit tri-state ROMs organized in a 512 X 16 bit configuration. All four units
share the same address lines and produce 16-bit PDP-11 instructions to be executed by the processor.
The three versions of the M9301 (M9301-YA, M9301-YB, and M9301-YF) that are used in the PDP11/04 system contain basic CPU and memory Go/No-Go diagnostics along with specific sets of bootstrap programs. The following list gives the function and order of each diagnostic test in the ROMs.
Test 1

All single operand instructions

Test 2

All double operand instructions

Test 3

Jump tests (modes 1, 2, and 3)

Test 4

Single operand, non-modifying, byte test

Test 5

Double operand, non-modifying test (source modes 1 and 4, destination
modes 2 and 4)

Double operand, modifying, byte test

Test 7

JSR test

Test 8

Memory test

Bootstrap programs

3.3.1
Basic CPU Diagnostics
The following is a description of Tests 1-5.
Test 1 - Single Operand Test

This test executes all single operand instructions using destination mode 0. The basic objective is to
verify that all single operand instructions function properly. It also provides a cursory check on the
operation of each instruction, while ensuring that the CPU decodes each instruction in the correct
manner.

Test | brings the Test Destination register through its three possible states: zero, negative, and positive.
Each instruction operates on the register contents in one of four ways:

Data will be changed via a direct operation (i.e., increment, clear, decrement, etc.).

Data will be changed via an indirect operation (i.e., arithmetic shifts, add carry, and subtract
carry).

3.
4.

Data will be unchanged, but will be operated upon via a direct operation (i.e., clear a register

already containing zeroes).

Data will be unchanged via a non-modifying instruction (TST).

3-10

Note that when operating upon data in an indirect manner, the data is modified by the state of the
appropriate condition code. Arithmetic shift will move the C bit into or out of the destination. This

operation, when performed correctly, implies that the C bit was set correctly by the previous
instruction.

There are no checks on the data integrity prior to the end of the test. However, a check is made on the
result. A correct result implies that all instructions manipulated (or did not manipulate) the data in the

correct way. If the data is incorrect, the program will fall into a branch-self.

Test 2 - Double Operand, All Source Modes, Destination Mode 0
This test verifies all double operand general and logical instructions - each in one of the seven modes
(excludes mode 0). Thus, two operations are checked; the correct decoding of each double operand
instruction, and the correct operation of each addressing mode for the source operand.
Each instruction in the test must operate correctly in order for the next instruction to operate. This
interdependence is carried through to the last instruction (bit test) where, only through correct execution of all previous instructions, a data field is examined for a specific bit configuration. Thus, each
instruction prior to the last serves to set up the pointer to test data.
Two checks on instruction operation are made in Test 2. One check, a branch-on condition, is made
following the compare instruction, while the second is made as the last instruction in the test sequence.

Since the Go/No-Go test resides in a ROM memory, all data manipulation (modification) must be
performed in destination mode O (register contains data). The data addressing constants used by Test 2
are contained in a literal pool within the ROM.

It is important to note that two different types of operations must execute correctly in order for this
test to operate:

Those instructions that participate in computing the final address of the data mask for the
final bit test instruction.

Those instructions that manipulate the test data within the register to generate the expected
bit pattern.

Detection of an error within this test results in a branch-self.
Test 3 — Jump Test Modes 1, 2, and 3

The purpose of this test is to ensure correct operation of the Jump instruction. This test is constructed
such that only a Jump to the expected instruction will provide the correct pointer for the next
instruction.

There are two possible failure modes that can occur in this test:

The Jump addressing circuitry will malfunction causing a transfer of execution to an illogical instruction sequence or nonexistent memory.

The Jump addressing circuitry will malfunction in such a way as to cause the CPU to loop.

The latter case is a logical error indicator. The former, however, may manifest itself as an after-the-fact
error. For example, if the Jump causes control to be given to other routines within the M9301, the
interdependent instruction sequences would probably eventually cause a failure. In any case, the failing of the Jump instruction will eventually cause an out-of-sequence or illogical event to occur. This is
a meaningful indicator of a malfunctioning CPU.

3-11

Test 4 — Single Operand, Non-Modifying, Byte Test

This test focuses on the one unique single operand instruction, the TST.TST, which is a special case in
the CPU execution flow since it is a non-modifying operation. Test 4 also tests the byte operation of
this instruction. The TSTB instruction will be executed in mode 1 (register deferred) and mode 2
(register deferred, auto-increment).
The TSTB is programmed to operate on data that has a negative value most significant byte and a zero
(not negative) least significant byte.

In order for this test to operate properly, the TSTB on the LSB must first be able to access the evenaddressed LSB, then set the proper condition codes. The TSTB is then reexecuted with the autoincrement facility. After the auto-increment, the addressing register should be pointing to the MSB of
the test data. Another TSTB is executed on what should be the MSB. The N bit of the condition codes
should be set by this operation.

Correct execution of the last TSTB implies that the auto-increment recognized that a byte operation
was requested, thereby only incrementing the addressing by one, rather than two. If the correct condition code was not set by the associated TSTB instruction, the program will fall into a branch-self.
Test 5 — Double-Operand, Non-Modifying Test
There are two non-modifying double operand instructions - the compare (CMP) and bit test (BIT).
These two instructions operate on test data in source modes 1 and 4, and destination modes 2 and 4.

The BIT and CMP instructions will operate on data consisting of all ones (177777). Two separate fields
of ones are used in order to utilize the compare instructions, and to provide a field large enough to
handle the auto-incrementing of the addressing register. Since the compare instruction (CMP) is executed on two fields containing the same data, the expected result is a true Z bit, indicating equality.
The BIT instruction will use a mask argument of all ones against another field of all ones. The expected
result is a non-zero condition (Z bit cleared). Failures will result in a branch-self.
3.3.2 Register Display Routine
The register display routine prints the octal contents of Processor registers R0, R4, SP, and “OLD PC”
on the console terminal. This sequence of numbers is followed by a prompt character (§) on the next
line (Paragraph 2.1.3.2). The console emulator is entered before any memory-modifying diagnostics

have been executed. Once the prompt character (§) has been received, the operator can execute the
remainder of the diagnostics by typing a boot command for a non-existent device.

The console emulator is entered before any memory-modifying diagnostics have been executed.
3.3.3

Memory-Modifying Diagnostics

Prior to execution of device boots, the following memory-modifying diagnostics will be executed (if the
diagnostics have been enabled on the M9301). The following is a description of Tests 6-8.

Test 6 — Double Operand, Modifying, Byte Test

The objective of this test is to verify that the double operand, modifying instructions will operate in the
byte mode. Test 6 contains three subtests:

.
2.
3.

Test source mode 2, destination mode 1, odd and even bytes
Test source mode 3, destination mode 2
Test source mode 0, destination mode 3, even byte.

The move byte (MOVB), bit clear byte (BICB), and bit set byte (BISB) are used within Test 6 to verify
the operation of the modifying, double operand functions.
3-12

Since modifying instructions are under test, memory must be used as a destination for the test data.
Test 6 uses location 5003 as a destination address. Later, in Tests 7 and 8, location 500s is used as the
first available storage for the stack.
Note that, since Test 6 is a byte test, location 500z implies that both 5005 and 5015 are used for the byte
test (even and odd, respectively). Thus, in the word of data 5005, both odd and even bytes are caused to
be all zeroes and all ones throughout the test. Each byte is modified independently of the other. Errors
detected in this test will result in a halt.

Test 7 — JSR Test
The JSR is the first test in the Go/No-Go sequence that utilized the stack. The Jump subroutine

command (JSR) is executed in modes 1 and 6. After the JSR is executed, the subroutine that was given
control, will examine the stack to ensure that the correct data was deposited in the correct stack
location (500s).

The routine will also ensure that the Link Back register points to the correct address. Errors detected in
this test will result in a halt.

Test 8 - Memory Test
Although this test is intended to test both core and MOS memories, the data patterns used are
designed to exhibit the most taxing operations for MOS. Before the details of the test are described, it
would be appropriate to discuss the assumptions placed upon the failure modes of the MOS

technology.
The test is intended to check for two types of problems that may arise in the memory:

1.
2.

Solid element or sense amplifier failures
Addressing malfunctions external to the chip.

The simplest failure to detect is a solid read or write problem. If a cell fails to hold the appropriate
data, it is expected that the Memory Test will easily detect this problem. In addition, the program
attempts to saturate a chip in such a way as to cause marginal sense amplifier operation to manifest
itself as a loss or pick-up of unexpected data. The 4K X 1 bit chip used in the memory consists of a 64
X 64 matrix of MOS elements. Each 64-bit section is tied to a common sense amplifier. The objective
of the program is to saturate the section with, at first, all zeroes and one 1 bit. This 1-bit is then floated
down through the section. At the end, the data is complemented, and the test repeated.

For external addressing failures it is assumed that if two or more locations are selected at the same
time, and a write occurs, it is likely that both locations will assume the correct state. Thus, prior to
writing any test data, the background data is checked to ensure that there was no crosstalk between
any two locations. Failures will result in a program halt as do failures in Tests 6 and 7. After the halt, it is
expected that the operator will press the BOOT switch causing RO (expected data), R4 (received data),
SP (failing address), and “OLD PC” (PC indicating memory failure) to be displayed. Refer to Paragraph 6.2.2 (Action 3).

NOTES
The M9301-YF Memory Test performs both a
dual-addressing and data check of all available
memory on the system.

3.3.4

If the expected and received data are the same,
it is highly probable that an intermittent failure
has been detected (i.e., timing or margin problem). The reason the expected and received data
can be identical is that the test program rereads
the failing address after the initial non-compare
is detected. Thus, a failure at CPU speed is
detected, and indicated by the reading of the
failing address on a single reference (not at
speed) operation.

Bootstrap Programs

This paragraph provides a list of the peripheral bootstraps supported by the M9301-YA, M9301-YB,
and M9301-YF modules. Which bootstrap program is run depends on the switch settings of the
M9301. On systems utilizing the M9301-YA or M9301-YF, the bootstraps can be entered directly
without running the CPU diagnostics (Paragraph 4.3.2).
Device

Device
Code

Unibus
Address

Peripheral Bootstraps Supported
by M9301-YA

777560

Terminal paper tape reader

777404

RK 11 moving-head disk cartridge

777342

TCI11 DECtape

772522

TM11 magnetic tape drive. Tape must be 7- or 9-track, 800

776714

RP11 moving-head disk pack for RP04/03

777500

TAI1Il cassette

777550

PC11 high-speed paper tape reader. Tape must be in a special

777170

bits/inch, odd parity, and dump mode.

bootstrap format (such as ABSLDR).

RX11 diskette

3-14

Device

Unibus

Code

Address

Peripheral Bootstraps Supported
by M9301-YB

777560

Terminal paper tape reader

772040

RJS03/04 Massbus fixed-head disk

772440

TJU16 Massbus tape drive.
bits/inch, and odd parity.

776300

Mixed combination of Massbus devices. The actual device is
determined by the specified unit number. The device can be a
TJU16, RJP04, or RJS03/04.

776700

RJP04/05/06 disk pack. Format 22, ECC inhibit.

777404

RK11 moving head disk cartridge

777342

TC11 DECtape

772522

TM11 magnetic tape drive. Tape must be 7- or 9-track, 800

Tape

must

9-track,

800

bits/inch, odd parity, and dump mode.
DP

776714

RPI11 moving-head disk pack for RP02/03

777500

TA1l cassette

777550

PC11 high-speed paper tape reader. Tape must be in a special
bootstrap format (such as ABSLDR).

777170

RX11 diskette

3-15

Device

Code

Unibus
Address

Peripheral Bootstraps Supported
by M9301-YF

777560

DL11 control for terminal paper tape reader

772040

RJS03/04 Massbus fixed-head disk

772440

TJU 16 Massbus tape drive

776700

RJP04/05/06 Massbus disk pack

777404

RK11 moving head disk cartridge control for RK03/05

777342

TC11 control for TU56 DECtape

7172522

TMI11 control for TU10 magtape

776714

RP11 moving-head disk pack control for RP02/03

777550

PC11 high-speed paper tape reader

777170

RXI11 control for RXO01 diskette

777440

RK611 control for RK06

Device

3-16

CHAPTER 4
CONFIGURATION

4.1
GENERAL
The PDP-11/34 computer system is contained in either the BA11-L [13.3 cm (5-1/4 inch) chassis] or
BA11-K [26.6 cm (10-1/2 inch) chassis] mounting box. The BA11 mounting box houses the backplane
and power supply. For a detailed discussion of the BA11-L mounting box (and H777 power supply) or
BA11-K mounting box (and H765 power supply), refer to the associated maintenance manual.

4.2 BACKPLANE
Three types of backplane can be used with the PDP-11/34: processor backplane, expander backplane,
or special purpose backplane.

The DD11-PK is used as the basic PDP-11/34 processor backplane. The DD11-CK or DD11-DK can
be used for expanding the system. Special purpose backplanes are wired to accommodate particular
options and are supplied with systems containing such options.
4.2.1 Physical Description
The DD11-PK is a 9-slot backplane and the DD11-CK is a 4-slot backplane (Figure 4-1). Each backplane is prewired (via wire-wrap connections on pin side) to accommodate certain types of modules in
each slot location. Details of signal connections and module placement are discussed in Paragraphs
4.2.2.2 and 4.2.3, respectively. Figure 4-1 shows the module connection side of each of the two backplanes.

Each system module plugs into one of the slots that is properly wired to provide all necessary power
and signal-connections for that particular module.
The DD11-DK (9-slot expander backplane) is the same as the DD11-PK processor backplane except
for slot 1 and slot 2, which have special interconnections for the KD11-E and KD11-EA processor
modules. Slots 1 and 2 of the DD11-DK are not dedicated to processor modules and therefore the
DDI11-DK can be used as an expander backplane.
4.2.2

Electrical Connections

This paragraph describes the power connections to the backplane and the signal connections of the
backplane itself.
4.2.2.1
Power - Power is supplied to the backplane via a wire harness that connects to the dc distribution board of the power supply. The wires exit from the backplane to a set of Mate-N-Lok connectors
that plug directly into the distribution board.

DD11-PK BACKPLANE

DD11-DK BACKPLANE

ROW
B

ROW
D

W
H
(8)]

SLOT NO.

/
/A

/1/
A/
VAV,

~
oc

N
w
»
O
o

TANANANN
DD11-CK BACKPLANE
ROW

‘

AV,

SLOT NO.

0
©

SLOT NO.

/X /

N\
2| /

(o))

MRV

STANDARD UNIBUS

MODIFIED UNIBUS

SPECIAL PURPOSE SLOTS FOR KD11-E

QUAD SMALL PERIPHERAL

SLOTS

SLOTS FOR MODIFIED

AND KD11-EA PROCESSOR MANUALS

CONTROLLER (SPC) SLOTS

IS)

UNIBUS DEVICES (MUD)

AN
HEX SMALL PERIPHERAL CONTROLLER (SPC) SLOTS

11-54563

Figure 4-1

PDP-11/34 Backplanes

4-2

The power harness from the DD11-PK and DD11-DK backplanes contains two large connectors (15pin Mate-N-Lok) and one small connector (6-pin Mate-N-Lok).
The DD11-CK backplane has only one 15-pin connector and one 6-pin connector. The connector pin
locations are shown in Figure 4-2 and the signal assignments for each pin are shown in Table 4-1
(DD11-PK and DD11-DK) and Table 4-2 (DD11-CK).

PIN 3

PIN 1

_\ A

Locating Lug

E ®

PIN 4

PIN 3 _/

\PINS

6-Pin Mate-N Lok

PIN 13

PIN 15

Locating Lug

15-Pin Mate-N-Lok

11-4632

Figure 4-2

Mate-N-Lok Connector Pin Locations
(Viewed from Wire Side)

Table 4-1

Power Connector Signal Assignments
for DD11-PK and DD11-DK

15-Pin Mate-N-Lok Connector 1

Signal

Wire

Color

+5V

No. 14

Red

2
3
4
5
6
7

+15V
+20V
+5V
Spare (not connected)
Spare (not connected)
Spare (not connected)

No. 18
No. 14
No. 14
~

Gray
Orange
Red
~
-

8
9

Ground
Ground

No. 14
No. 14

Black
Black
-

- Spare (not connected)

Spare (not connected)

+5 Bat

No. 14

Red

Spare (not connected)

-5V

No. 18

Spare (not connected)

Brown
-

Table 4-1
Power Connector Signal Assignments
for DD11-PK and DD11-DK (Cont)

15-Pin Mate-N-Lok Connector 2

Signal

Wire

Color

1
2
3
4
5

+5V
Spare (not connected
+20V
+5V
Spare (not connected)

No. 14
No. 14
No. 14
-

Red
Orange
Red
-

Spare (not connected)

+15 Bat

No. 18

White

8
9

Ground
Ground

No. 14
No. 14

10
11
12

Spare (not connected)
Spare (not connected)
Spare (not connected)

14
15

Spare (not connected)
-15 Bat
|

No. 18

Green

-15V

No. 18

Black
Black

Blue

6-Pin Mate-N-Lok Connector

Signal

Wire

Color

1
2
3
4
5
6

LOGND
LTC (line clock)
DCLO
ACLO
Spare (not connected)
Spare (not connected)

No. 14
No. 18
No. 18
No. 18
-

Black
Brown
Violet
Yellow
-

Table 4-2

Power Connector Signal Assignments for DD11-CK
15-Pin Mate-N-Lok Connector

Signal

Wire

Color

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

+5V
+15V
+20V
+5V
Spare (not connected)
+15 Bat
Ground
Ground
Spare (not connected)
Spare (not connected)
Spare (not connected)
+5 Bat
-15V
-5V
-15 Bat

No. 14
No. 18
No. 18
No. 14
No. 18
No. 14
No. 14
No. 14
No. 18
No. 18
No. 18

Red
Gray
Orange
Red
Green
Black
Black
Red
Blue
Brown
White

Signal

Wire

Color

l
2

LOGND
LTC (line clock)

No. 14
No. 18

Black
Brown

3
4

DCLO
ACLO

No. 18
No. 18

Violet
Yellow

5
6

Spare (not connected)

6-Pin Mate-N-Lok
Pin

4.2.2.2 Backplane Signal Connections - In the following discussion, particular areas of the backplane
will be referred to according to slot number (1-9) and section (A-F). Refer to Figure 4-1.

Signal connections between the backplane and operator’s console are made via a single cable which
terminates in a 10-pin 3M connector and plugs into connector J1 on the operator’s console. Figure 4-3
shows the 3M connector pin locations and Table 4-3 lists the signal designation of each pin.
NOTE
The 3M connector is installed only if the operator’s
console is present.

PIN9

\;%)

AN\ N\
Y

PIN 10

PIN 1

11-4633

Figure 4-3
3M Connector Pin Locations
(Viewed from Pin Side)

Table 4-3

pe—t

OVvooNAWn
B W —

10-Pin 3M Connector Signal
Designations

Signal
Ground
DCLO
Ground
ACLO
Ground
HALT REQUEST
HALT GRANT
SACK
Ground
INIT

Standard Unibus Slots - Slot 1 (sections A and B) of the DD11-PK, DD11-CK, and DD11-DK is the
Unibus IN slot. Slots 1 and 2 of the DD11-PK backplane are dedicated to the processor modules.
However, slot 1 (sections A and B) of the expander backplane (DD11-CK and DD11-DK) can accept
any dual module that can plug into standard Unibus slots (i.e., BC11-A Unibus cable or M9202
Unibus jumper cable). Slot 9 (sections A and B) is the Unibus OUT slot of the DD11-PK and
DDI11-DK backplanes and slot 4 (sections A and B) is the Unibus OUT slot of the DD11-CK backplane. These sections must contain either a Unibus terminator (M9302) or a Unibus output cable
(BC11-A or M9202). Figure 4-4 shows the pin designations of the standard and modified Unibus
connectors.

Modified Unibus Device (MUD) Slots - Slots 2 through 8 (sections A and B) are the modified Unibus of
the DD11-PK and DD11-DK backplanes. Slots 2 and 3 (sections A and B) are the modified Unibus of
the DD11-CK backplane.

The modified Unibus differs from the standard Unibus in that certain pins have been redesignated
(Figure 4-4). Some ground connections, BUS GRANT signals, and the NPG signal have been remov-

ed from the standard Unibus and have been redesignated with core memory voltage pins, battery
backup voltage pins for MOS memory, parity signal pins, several reserved pins, and test point pins.

Small Peripheral Controller (SPC) Slots - The sections that accommodate small peripheral controller
modules are slots 3 through 9 (sections C-F) of the DD11-PK backplane, slots 1 through 4 (sections
C-F) of the DD11-CK backplane, and slots 1 through 9 (sections C-F) of the DD11-DK backplane.
These sections provide the signal connections required by hex-height or quad-height modules (SPC
modules) containing control logic for peripheral devices (i.e., serial line controller, programmer’s console interface). Figure 4-5 shows the pin designations for the SPC connectors.

Non-Processor Grant (NPG) Line - The NPG line is the Unibus grant line for devices that perform data
transfers without processor intervention. The NPG line grant continuity is provided by wire-wrap
jumpers on the backplane. When an NPG module is placed in a slot, the corresponding jumper wire
from pin CA1 to pin CBI of that slot must be removed. The routing of the NPG signal through the
backplane is shown in Figure 4-6. Grant priority decreases from slot 1 to slot 9 (i.e., slot 1 has highest
priority and slot 9 lowest).

NOTE

If an NPG module is removed from a slot, the jumper
wire from CA1 to CB1 must be reconnected.

Standard Unibus

Modified Unibus

Pin Designations

Column

ide

|+5V

|BG6

INTR|{GND

|BG5

INIT

D00

|DO1

D04

|D0O3

|BR5

IGND

BG4

[AC

L
|DO5

LO L

D08

|D07

|AO01

A00

|D0O9

|AO3

A02

D12

|D11

|AO05

A04

D14

|D13

}AO7

A06

|D15

|AO9

A08

|A11

A10

GND

|BBSY]|

A13

A12

GND

|SACK]

A15

A14

GND

|[NPR | A17

GND

|BR7

|GND

P
R

S
T

|SSYN

BG7

|GND

LOL
A00

D09 | A03

A02

D12

D11

| A05

| AO04

D15

L
P1

D13 | A07

L
d

L
SACK|

BAT I

A08

L
L
| A10

+15

NPR

AO6

A09

A11

BBSY|

BAT

L
|

A13 |

L
A12

A15 ]|

A14

A17 | A16

GND

BR7
L

GND|

€1
L

+20

BR6

|SSYN | co

[J(CORE)

J(CORE)|/CORE)

|[MSYN | GND

LOL|

D07 | AO1

PAR

L
PAR

|[SSYN ] DET

PAR

|BR6

L SO g

D14

A16

NPG

BR4

DO5 | AC

D10

|PB

GND

DO3 | INT

D08

)

D04

D06

DO1

L | BAT

GND

GND | BRS

€

D10

| RESV|

D02

D00

BR4

|RESV | +5V

|GND

| +6V

INTR|

GND

D06

INIT

|GND

D02

€

GND

2
+5V

Column

Side

Column

+20

|MSYN|

(CORE)‘

| S—

11-4631

NOTE: D indicates a redesignated pin.
Figure 4-4

Standard and Modified Unibus Pin Designations

Column

ide
Pin

NPG

+5V

GND

+5V

ABG

+5V

. | -15V

-15VvV

ASSYN | -15V

ABG

(IN)
NPG

GND

D15

BBSY

FO1

D02

A IN

BR4

A01

A00

D07

A INT

SSYN

NPR

GND

ENBB
TP

| DO8

A13

D08

A INT

INIT

BG?7

A11

D03

FO1

ENBA

AINT | BG6
A

FO1

D04

A OUT | AO08

BG5

A10

A07

ABR

FO1

ouT

BG5S

A09

ASEL

FO1

ouT

BG4

ASEL

FO1

GND

BG4

GND

ASEL

GND

SACK

ouT
TP

D06 | ASSYN

L
N1

L
LO

HIGH
L

L
+15/+8 | D02

L2
FO1

LOW

D03

L
AOUT | INTR

ouT

ENB B

GND

A14

AIN

D00

ouT

BG6

HALT | DO

ouT

HALT | D05

D06

D05

AINT

D04

GRT

- V2

L
C1

D07

REQ

L
A02

A OUT | BG?7

L
A INT

A SEL | ABR

L
D09

A SEL | BR5

MSYN | A16

FO1

)

A15

D12.

A SEL | BR6

A17

D11

GND

D13

SSYN

A INT | D10

GND

A OUT | BR?

LOW

A12

D14

| GND

-15V

€

A SEL

LTC

ouT

IN H

(OUT)
PA

IN H

ABG

2
A06

A04

L
AINT | ABR

ABG

A05

A03

A INT | FO1

ouT

ENBA | FO1
11-4630

Figure 4-5

SPC Pin Designations

REMOVABLE WIRE WRAP

AUl @

4,’
CB1

CA1

AU1

VN VN\:wAN

/-\

11-4628

Figure 4-6

NPG Signal Path

Bus Grant (BG) Lines - The bus grant lines (BG4:BG?7) for devices requiring processor intervention
during data transfers are routed through each small peripheral controller section in connector D. Each
of the four GRANT signals is routed on a separate line. Figure 4-7 shows the routing of one of the
grant lines. The other three lines follow a similar path. Grant priority for each level decreases from slot

1 to slot 9.
NOTE
A bus grant jumper card (G727) must be placed in
connector D of any unoccupied SPC section. If an
SPC section is left open, bus grant continuity will be
lost and the system will hang.

4.2.3 Module Placement
The PDP-11/34 backplanes are wired to accommodate particular types of modules in each section.
Figure 4-8 illustrates which modules can be placed in each backplane slot.

4-10

- o+0 10 010 10 010 010

BE2

114629

Figure 4-7

BG Signal Path (BG4 Line)

4-11

DD11-DK Backplane

Row

\\ AN

S N

NOTE 1

|NOTE 2

Siot No.

\\?w

DD 11-PK Backplane

NY
Y [ Y

NOTE 1|

NOTE 2

I
DD11-CK Backplane

m
Standard Unibus — ACCOMMODATES DUAL-HEIGHT MODULES WHICH ARE STANDARD UNIBUS COMPATIBLE:
M9202 (NOTE 4), BC11A CABLE, M9302 SACK/TERM (NOTE 5)
EXAMPLE:
(Stots 2 through 8) DD11.PK
or

Row

(Slots 1 and 4) DD11-CK

s 2f / // /
2

/ /

@ 3

4 \\

(Slots 24 through 8) DD11-PK

NOTE 1 NOTE 2

' ‘

[7/ 7T/ /] Modified Unibus — ACCOMMODATES DUAL-HEIGHT MODULES WHICH ARE MODIFIED UNIBUS COMPATIBLE:

{

[

J — ACCOMMODATES SMALL PERIPHERAL CONTROLLER (SPC).
EXAMPLE:

(Slots 3 thro&;grh 9)D D11-PK

NOTES:
.

Remove CA1 to CB1 wire-wrap jumper from the appropriate slot to install an
NPR option in that SPC slot.

2. A G727 card is required in any unused SPC slot to provide bus grant continuity.
.

M9301 BOOT/TERM, M9306 TERM, M7850 PARITY CONTROLLER.

(Slots 2 and 3) DD11-CK

[

EXAMPLE:

3. Grant direction is slot 1 to slot 9 (or slot 4).

4. Use M9202 to interconnect system units instead of M920. M9202 is a 2-ft. Unibus

PROGRAMMER’'S CONSOLE INTERFACE (M7859), DL11-W (M7856)

(Slots 1 through 4) DD11-CK
A

W/]//A
(Slots 2 through 8) DD11-PK
or

(Slots 2 and 3) DD11-CK

[

J — ACCOMMODATES HEX-HEIGHT MODULESWITH
MODIFIED UNIBUS SIGNALS.

EXAMPLE.

MS11 MOS MEMORY MODULES

MM11 CORE MEMORY

Y MODULES
M

jumper cable used to distribute Unibus loading.

5. The M9302 sack/terminator must never be installed in any slot other than slot 9

(sections A and B) in the DD11-PK and slot 4 (sections A and B) in the DD11-CK.

\\ \

(Slots 1 and 2) DD11-PK Only

- ;’;ig'fiA::gg::ssoencaggt5€ZORs SLOT 1 IS DEDICATED TO THE M7266 OR
SLOT 2 IS DEDIGATED TO THE M7265 OR M8265
PROCESSOR MODULE.

CAUTION
Power supply voltages will be shorted out if
this terminator is mounted in the modified

Unibus slots. Also, Unibus cables (i.e.,

BC11A) must never be plugged into a modified Unibus slot.

11-5454

Figure 4-8

Module Placement

4-13

4.3

SWITCHES AND JUMPERS

This paragraph provides a definition of all switch settings and jumper locations associated with the
PDP-11/34 system components.
4.3.1

KDI11-E Processor

4.3.2

KD11-EA Processor

There are only two jumpers (W1 and W2) on each of the two processor modules. No switches are
associated with the modules. Jumper W1 is OUT and W2 is IN on the M7266 module and both W1
and W2 are IN on the M7265 module.

The M8266 module has only one jumper (W1) which is IN. The M8265 module has two jumpers (W1
and W2) which are both IN.
4.3.3

M9301 Bootstrap/Terminator

The M9301 module has only one switch pack (S1) which contains 10 switches (S1 through S10). The
five jumpers (W1, W2, W3, W4, and W5) should always be removed when the M9301 is installed in the
PDP-11/34 system.

The function of each switch in the module switchpack is as follows:

Low ROM Enable switch. When this switchis placedin the OFF position,
the lower 256 words of the M9301 ROM (Unibus addresses 765000 through
765776) are disabled. Placing S1in the OFF position resultsin the following:
M9301-Y
A: The cassette boots, floppy boots, and diagnostics are unavailable and the paper tape boot will default to the lower
4K.

M9301-YB: Switch is not used.

M9301-YF: The paper tape boot and console emulator are unavailable.
S2

Power-Up Reboot Enable switch. When this switch is in the ON position, the
M9301 will be activated automatically when the system returns from a power

fail. With this switch in the OFF position, the processor will perform a normal power-up routine through locations 24 and 26. If the BOOT/INIT
switch on the console is pressed and released, the M9301 will be activated
regardless of the position of switch S2.
NOTE

This switch should be in the ON position in systems
using MOS memory without the battery backup
option. Systems using MOS memory and containing
the battery backup option or systems with core memory should have this switch in the OFF position.
Refer to Paragraph 3.1.3.

S3-S10

ROM Address Switches. The setting of switches S3 through S10 determines
the ROM starting address that will be used as the new PC by the processor
during a power-up routine (providing the M9301 has been enabled). The
M9301-YA, YB, and YF allow the operator to select (via switches S3-S10)
the function performed upon activation of the bootstrap /terminator.

Tables 4-4, 4-5, and 4-6 show the correspondence between switch settmgs and the function selected for
the M930l YA, M9301-YB, and M9301-YF respectively.

4-15

Table 4-4

M9301-YA ROM Starting Address Selection

M9301-Y
A Switch Settings
Function

CPU diagnostics - Consoleemulator|

| ON

ON | ON

CPU diagnostics —» Vector
through location 24

|ON

ON | ON

OFF

Console emulator
(without diagnostics)

ON | ON

OFF

OFFf

CPU diagnostics - Boot RK11

OFF

|OFF

ON | ON

Boot RK 11 (without diagnostics)

OFF

|OFF

ON | ON

OFF

CPU diagnostics- Boot RP11

OFF

ON | OFF

OFF

ON | OFF

OFF

Boot RP11 (without diagnostics)

OFF

ON | OFF

OFF

OFF{

CPU diagnostics» Boot TC11

OFF

OFF|ON

ON | OFF

OFF

Boot TC11 (without diagnostics)

OFF

OFF|

CPU diagnostics- Boot TM 11

OFF

OFF|

OFF

ON | OFF

Boot TM 11 (without diagnostics)

OFF

OFF|

OFF

ON | OFF

OFF

CPU diagnostics - Boot TA 11

OFF

ON | ON

OFF

ON | OFF

Boot TA 1 (without diagnostics)

"OFF

OFF

ON | ON

OFF

ON | OFF

OFF

CPU diagnostics - Boot RX11

OFF

ON | ON

OFF

OFF|

OFF

Boot RX11 (without diagnostics)

OFF

ON | OFF

ON | ON

CPU diagnostics- Boot DL11

OFF

ON | OFF

OFF|,

Boot DL11 (without diagnostics)

OFF

ON | OFF

ON-

OFF|

OFF

CPU diagnostics
—» Boot PC11

OFF

ON | OFF

OFF

ON | ON

Boot PC11 (without diagnostics)

OFF

ON | OFF

OFF

ON | ON

OFF

Note: ON = logic 0; OFF = logic |

4-16

S10

Table 4-5

M9301-YB ROM Starting Address Selection

M9301-YB Switch Settings

Function

S5 [ S6

CPU diagnostics - Console Emulator|

ON | ON

CPU diagnostic - Vector
through location 24

ON ] ON

ON | ON

OFF

Console emulator

OFF

ON | ON

OFF

ON | OFF

OFF

|S9

SI0

Note: ON = logic 0, OFF = logic 1

Table 4-6

M9301-YF ROM Starting Address Selection
M9301-YF Switch Settings

Function

| ON

ON | ON

OFF

CPU diagnostics » Vector
through location 24

OFF

ON | OFF

Vector through location 24
(without diagnostics)

OFF

ON | OFF

OFF

CPU diagnostics » Boot RP11

| OFF

ON | ON

Boot RPI11
(without diagnostics)

ON | OFF

ON | ON

OFF

CPU diagnostics - Boot RJP04/05/06f

OFF

ON | ON

OFF

ON | OFF

Boot RJP04/05/06
(without diagnostics)

OFF

ON | ON

OFF

ON | OFF

OFF

CPU diagnostics —» Boot RJS03/04

OFF

| OFF

ON | ON

Boot RJS03/04 (without diagnostics)

| OFF

ON | OFF

ON | ON

OFF

CPU diagnostics - Boot RK 11

OFF|

OFF

ON | OFF

Boot RK 11 (without diagnostics)

OFF|

OFF

ON | OFF

OFF

CPU diagnostics- Boot RK611

OFF

ON | OFF

OFF

ON | ON

OFF

Boot RK611 (without diagnostics)

OFF

ON | OFF

OFF

ON | OFF

CPU diagnostics » Consoleemulator

Console emulator

S10

(without diagnostics)

Note: ON = logic 0; OFF = logic 1.

4-17

Table 4-6

M9301-YF ROM Starting Address Selection (Cont)
M9301-YF Switch Settings

Function

CPU diagnostics - Boot RX11

OFF

OFF|

OFF

ON | OFF

Boot RX11 (without diagnostics)

OFF

OFF | OFF

ON | OFF

OFF

CPU diagnostics- Boot TCl11

OFF | OFF

OFF

OFF|

OFF

Boot TC11 (without diagnostics)

OFF | OFF

OFF

OFF|

OFF

CPU diagnostics- Boot TM 11

OFF

ON | OFF

OFF

OFF|

OFF

Boot TM 11 (without diagnostics)

OFF

ON | OFF

OFF

OFF|

OFF

CPU diagnostics - Boot TJU 16

ON | OFF

OFF|

OFF

Boot TJU 16 (without diagnostics)

ON | OFF

OFF|

OFF

CPU diagnostics- Boot DL11

OFF

OFF|

OFF

ON | OFF

Boot DL11 (without diagnostics)

OFF

OFF|

OFF

ON | OFF

OFF

CPU diagnostics- Boot PC11

OFF

OFF|

OFF

Boot PC11 (without diagnostics)

OFF

OFF|

ON | OFF

OFF

Note: ON = logic 0; OFF = logic 1.

4-18

S10

4.3.4 DL11-W Serial Line Interface and Real-Time Clock
The DL11-W (M7856) contains 5 switch packs labeled S1 through S5. Each switch pack contains
either 8 or 10 individual slide or toggle switches. The switch packs are labeled with each switch numbered 1 through 8 or 10. Each pack is also labeled showing the on and off positions (Figure 4-9).

8107-26

Figure 4-9

DL11-W (M7856) Switch Locations

4-19

Switch selections on the DL11-W allow the interface to directly replace a DL11-A, B, C, or D in most
applications. Through proper setting of the switches, the user can select the desired baud rate, character size, stop-code length, parity, error detection, and 20-mA current loop modes. Table 4-7 lists the
function of each of the switches. The switches are used separately or in conjunction with other switches
to select the parameters discussed in the following paragraphs.
NOTE
In boxes other than BA11-L, there is not sufficient
drive capability on the LTC L signal to drive multiple
loads. Since each DL11-W constitutes a load (even if
the line clock is disabled by the switch), multiple
DL11-Ws in a box will overload the LTC L signal
causing line clock failures. To alleviate the loading
effect of the additional DL11-Ws, remove resistor
R63 from all DL11-W modules except the one being
used as a line clock. If multiple DL11-Ws are used
on the same system, the line clock must be enabled
(via switches) only on the DL11-W being used as a
line clock.
In the following description, the switch will be indicated by its switch pack and switch number (e.g.,
S4-5 indicates switch pack 4, switch 5).
4.3.4.1
Device Address - The standard Unibus address assignment for the console device is 777560.
However, the address of the DL11-W may be selected by the following switches:
Address Bit

Corresponding Switch

10
09
08
07
06
05
04
03

S5-3
SS5-2
SS5-1
S5-4
S5-5
S5-6
S5-8
S5-7

Note: Switch ON = logical 0; OFF = logical 1.

Figure 4-10 shows the bit values for the standard address and the correspondence between the address
bits and switches.

OCTAL ADDRESS

ADDRESSBIT

pATA

SWITCH NO. (PACK 5)

11|

o]l

—~——

‘

11l

11o0o]lo]l

SN~

NOT SWITCH

SELECTABLE

SWITCH ON = Logical 0, OFF = Logical 1
11-4625

Figure 4-10

DLI11-W Device Address Selection
4-20

The switches may be set so that the DL11-W responds to any address within the range of 774000 to

1777717,

4.3.4.2
Vector Address - The standard vector address assignment for the console device is 060. The
vector address may be selected by the following switches:
Vector

Address Bit

Corresponding Switch

08
07
06
05
04
03

S2-8
S2-7
S2-5
S2-3
S2-6
S2-4

Note: Switch ON = logical 1; OFF = logical 0.

Figure 4-11 shows the bit values for the standard vector address and the correspondence between
address bits and switches.

OCTAL ADDRESS

ADDRESS BIT

DATA

| ol

SWITCH
NO. (PACK 2) “\__

——

NOT SWITCH SELECTABLE

NOT SWITCH
SELECTABLE

SWITCH ON = Logical 1, OFF = Logical 0
11-4626

Figure 4-11

4.3.4.3

DL11-W Vector Address Selection

Baud Rate - Switches provided on the DL11-W allow the user to select independent receiver

and transmitter baud rates. The following shows the correspondence between switch positions and
baud rates.
Switch Positions

Transmit

Receive

Baud Rate

S4-10

S3-1

S3-4

S3-2

S3-3

S3-5

110
150
300
600
1200
2400
4800
9600

ON
OFF
ON
ON
ON
OFF
OFF
OFF

ON
ON
OFF
OFF
ON
OFF
OFF
ON

ON
ON
OFF
ON
OFF
OFF
ON
OFF

OFF
ON
OFF
OFF
OFF
ON
ON
ON

OFF
OFF
ON
ON
OFF
ON
ON
OFF

OFF
OFF
ON
OFF
ON
ON
OFF
ON

4-21

4.3.4.4

20-mA Current Loop Mode - The DL11-W provides two modes of operation (active and
passive) for use with 20-mA current loop devices. In the active mode, the DL11-W is the source of the
20-mA current (all standard DEC terminals). In the passive mode, the external device must provide the
required current (LA36, LA30, and VT52 options). The following shows the switch settings for the
active and passive modes for the transmitter, receiver, and paper tape reader enable.
Switch Positions
Transmitter

S1-1

S1-2

S1-3

S1-6

S1-7

Active
Passive

ON
OFF

OFF
ON

ON
OFF

Receiver

S3-6

S3-7

S3-8

S3-9

S3-10

Active
Passive

ON
OFF

OFF
ON

ON
OFF

OFF
ON

ON
OFF

Paper Tape Reader Enable

S1-4

S1-5

S1-8

S1-9

S1-10

Active
Passive

ON
OFF

OFF
ON

ON
OFF

OFF
ON

ON
OFF

4.3.4.5 Data Format - The data format consists of a start bit, 5 to 8 data bits, a parity bit (or no parity
bit), and 1, 1-1/2, or 2 stop bits. The following shows the switch selections for the desired format.
S4-4

oo~
O\ W»n

Switch Positions
S4-3

No. of Data
Bits/Character

ON
ON
OFF
OFF

No. of Stop
Bits/Character

S4-5

1
2

Parity

S4-6

Enable
Disable

ON
OFF

ON
OFF
ON
OFF

OFF (1.5 stop bits with
5 data bits)

S4-2

ON
OFF

Odd
Even

4-22

4.3.4.6 DL11-W Compatibility Switches - The DL11-W can replace a DL11-A, B, C, or D in most
applications if the foliowing switches are set properly.
Function

Switch

Description

Break Bit

S4-1

The break bit is enabled if S4-1 is in the ON position.
S4-1.should be OFF if replacing a DL11-A or DL11-B
and ON if replacing a DL11-C or DL11-D.

Error Bits

S4-7

Error bit reporting is enabled if S4-7 is in the ON position. S4-7 should be OFF if replacing a DLI11-A or
DL11-B and ON if replacing a DL11-C or DL11-D.

Real-Time Clock

S5-9 and

The real-time clock is enabled if S5-9 is in the OFF position and S5-10 is in the ON position. To disable the real-

S5-10

time clock, S5-9 must be ON and S5-10 must be OFF.
The real-time clock must be disabled if the DL11-W is
not used as the console terminal control. If both S5-9
and S5-10 are ON, the DL11-W is used as a line clock
only and the serial line unit section does not respond to
any address. If the DL11-W is used as a line clock only,
the address selection switches must be set for 77754X.

Table 4-7 lists each of the switch packs and the associated function of each switch.
Table 4-7
Switch Pack
|

DL11-W Switch Functions

Switch No.

Function

2
3

4
5

Transmitter (Active/Passive mode of 20-mA loop)
Reader Enable (Active/Passive mode of 20-mA loop)

Transmitter (Active/Passive mode of 20-mA loop)

Reader Enable (Active-Passive mode of 20-mA loop)

Not Functional

2
3
4

5
6

Vector Address
‘

7
8

4-23

Table 4-7
Switch Pack

DL11-W Switch Functions (Cont)

Switch No.

Function

1
2
3
4
5
6
7
8
9
10

Transmitter baud rate
Receiver baud rate

Break enable

2
3

Parity select (odd or even)
No of Data bits

Transmitter baud rate
Receiver baud rate

Receiver (Active/Passive mode of 20-mA loop)

5
6
7
8
9
10
5

No. of Stop bits
Parity enable
Error bit enable
Not functional
Transmitter baud select

1
2
3

4
5
6
7
8

Device Address

Real-Time Clock Enable

4.3.5

MS11-EP, MS11-FP, and MS11-JP MOS Memory

The MS11 MOS memory module (M7847) has one switch pack containing eight individual switches.
The switches are identified by etched letters A-J on the printed circuit board. Switches A through E are
used to select the memory starting addresses and switches F through H are normally in the OFF
position for PDP-11/34 systems (switch H is ON if MS11-JP memory is used). Table 4-8 shows the

correspondence between the switch settings and the address banks assigned to the memory module.
Jumpers on the module allow more than one 4K address bank to be assigned. For example, the
MS11-JP (16K memory) would require all four address banks. When switch H is ON, bank D is
enabled. The following lists the memories by size and indicates the jumpers installed (and setting of
switch H) for normal use.

4-24

Eyelet Pairs Connected by Jumpers
Memory

Memory

Designation

Size

Switch

W3-W4 | WI-W2 | W5-W6

MSI11-EP

OuT

OUT

OFF

MSI11-JP

16K

MSI11-FP

Table 4-8

OouT

OFF

Switch Settings for MS11 Address Assignments

Switch Selection

Bank A

Bank B

Bank C

Bank D

OFF OFF
OFF OFF
OFF OFF
OFF OFF
OFF OFF
OFF ON
OFF ON
OFF ON
OFF ON
OFF ON
OFF ON
OFF ON
OFF ON
ON OFF
ON OFF

OFF ON
ON OFF
ON OFF
ON ON
ON ON
OFF OFF
OFF OFF
OFF ON
OFF ON
ON OFF
ON OFF
ON ON
ON ON
OFF OFF
OFF OFF

ON
0-4K
OFF|
4-8K
ON
8-12K
OFF]| 12-16K
ON | 16-20K
OFF| 20-24K
ON | 24-28K
OFF]| 28-32K
ON | 32-36K
OFF| 36-40K
ON | 40-44K
OFF| 44-48K
ON | 48-52K
OFF| 52-56K
ON | 56-60K

4-8K
8-12K
12-16K
16-20K
20-24K
24-28K
28-32K
32-36K
36-40K
40-44K
44-48K
48-52K
52-56K
56-60K
60-64K

8-12K
12-16K
16-20K
20-24K
24-28K
28-32K
32-36K
36-40K
40-44K
44-48K
48-52K
52-56K
56-60K
60-64K
64-68K

12-16K
16-20K
20-24K
24-28K
28-32K
32-36K
36-40K
40-44K
44-48K
48-52K
52-56K
56-60K
60-64K
64-68K
68-72K

ON
ON
ON
ON
ON
ON
ON
ON
ON

OFF ON
OFF ON
ON OFF
ON OFF
ON ON
ON ON
OFF OFF
OFF OFF
OFF ON

OFF| 60-64K
ON | 64-68K
OFF| 68-72K
ON | 72-76K
OFF| 76-80K
ON | 80-84K
OFF| 84-88K
ON | 88-92K
OFF| 92-96K

64-68K
68-72K
72-76K
76-80K
80-84K
84-88K
88-92K
92-96K
96-100K

68-72K
72-76K
76-80K
80-84K
84-88K
88-92K
92-96K
96-100K
100-104K

72-76K
76-80K
80-84K
84-88K
88-92K
92-96K
96-100K
100-104K
104-108K

112-116K
116-120K
120-124K
124-128K
0-4K
4-8K
8-16K

OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON

ON ON
ON ON
ON ON
ON ON
OFF OFF
OFF OFF
OFF OFF

OFF ON
ON
ON
ON
ON
OFF
OFF
OFF

ON | 96-100K

100-104K

104-108K

104-108K
108-112K
112-116K
116-120K
120-124K
124-128K
0-4K

108-112K
112-116K
116-120K
120-124K
124-128K
0-4K
4-8K

108-112K

To enable bank | To enable bank | To enable bank | To enable bank
A, jumper
W3-W4isIN.

B, jumper
|WI-W2isIN.

4-25

C, jumper
D, switch H
| W5-W6isIN. | is ON.

4.3.6 MM11-CP Core Memory
The MM11-CP core memory module has one switch pack (E39) which contains eight switches
(SW1-SW8). These switches are used to select the Unibus addresses that the 8K memory will occupy.
Table 4-9 lists the memory bank, Unibus address range, and corresponding switch positions.
Table 4-9

MM11-CP Memory Address Selection

Memory

Unibus Address

Switch Settings

Bank

Range

SW1, 2

SW3, 4

SWS, 6

SW7,8

OK-8K
8K-16K

000000-037776
040000-077776

ON
OFF

ON
ON

16K-24K

100000-137776

OFF

24K -32K
32K-40K
40K -48K
48K-56K
56K-64K
64K-72K
72K-80K
80K-88K
88K-96K

140000-177776
200000-237776
240000-277776
300000-337776
340000-377776
400000-437776
440000-477776
500000-537776
540000-577776

OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF

OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF

ON
OFF
OFF
OFF
OFF
ON
ON
ON
ON

ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF

96K-104K
104K-112K
112K-120K
120K-128K

600000-637776
640000-677776
700000-737776
740000-777776

ON
OFF
ON
OFF

ON
ON
OFF
OFF

OFF
OFF
OFF
OFF

4.3.7 MM11-DP Core Memory
The MM11-DP core memory module contains four jumpers (W1, W2, W3, W4) that are installed (or
removed) to select the Unibus addresses that the 16K memory will occupy. Table 4-10 lists the memory
bank, Unibus range, and corresponding jumper assignment.
Table 4-10

MM11-DP Memory Address Selection

Memory

Unibus Address

Jumper Assignment

Bank

Range

0K-16K
8K-24K
16K~-32K
24K -40K
32K-48K
40K-56K
48K -64K
56K-72K
64K -80K
72K-88K
80K-96K
88K-104K
96K-112K
104K-120K
112K-128K

000000-077776
040000-137776
100000-177776
140000-237776
200000-277776
240000-337776
300000-377776
340000-437776
400000-477776
440000-537776
500000-577776
540000-637776
600000-677776
640000-737776
700000-777776

OouUT
OUT
OUT
OouT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN

OuUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OuUT
OuUT
IN
IN
IN
IN

OUT
IN
IN
OuUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN

IN
ouT
IN

4-26

ouT
IN
OuUT
IN
OUT
IN
OouT
IN
OuT
IN
OuUT
IN

4.3.8

M7850 Parity Controller

The M7850 Parity Control module contains four jumpers which are used to determine the Unibus
address of the Control and Status register (CSR). The following shows the correspondence between the
CSR address and jumper arrangement:

Jumper Arrangement

CSR Address

772100
772102

IN
IN

IN
OUT

772106
772110
772112
772114
772116
772120
772122
772124
772126

IN
IN
IN
IN
IN
OUT
OuT
OUT
OUT

IN
ouT
OouUT
OUT
OUT
IN
IN
IN
IN

ouT
IN
IN
OUT
ouT
IN
IN
ouT
OuUT

OuUT
IN
OUT
IN
OuUT
IN
OuUT
IN
OUT

OuT
OUT
OuT

OuT
OuUT
OUT

IN
IN
ouT

IN
OouUT
IN
OUT

772104

772130
772132
772134

772136

OUT

OuUT

OouT

OouUT

NOTE
There is no correlation between the CSR address of
the M7850 and the memory block(s) it controls.
Only one M7850 is required in each backplane containing parity memory.

4-27

CHAPTER 5

INSTALLATION

5.1

GENERAL

This chapter provides the information necessary for site preparation, unpacking, inspection, and firsttime start-up of the basic PDP-11/34 system.

5.2 SITE CONSIDERATIONS
The computer room environment should have an air distribution system that provides cool, well-

filtered, humidified air. The room air pressure should be kept higher than that of adjacent areas to
prevent dust infiltration.

Computer area environment can have a substantial effect upon the overall reliability of the system.
Temperature cycling and thermal gradients induce temporary or permanent microscopic changes in
materials that can affect performance or endurance. High temperatures tend to increase the rate of
deterioration for nearly every material. High absolute humidity (dew point) causes moisture absorption that can result in dimensional and handling changes in paper and plastic media (line printer paper,
cards, paper tape, magnetic tape, etc.)

Low humidity allows static electricity to build up, while lack of air cleanliness results in dust that
reduces tape life and leads to excessive head wear and early data errors in all moving magnetic storage
media (drums and disks). This combination of static electricity and airborne dust is especially detrimental to magnetic tapes.
Vibration can also cause slow degradation of mechanical parts and, when severe, may cause errors on
disks and drums.

Hardware errors can also be caused by electromagnetic interference (EMI). EMI sources that have
been known to cause failures include: radar installation, lightning strikes, power transmission lines,
vehicle ignition systems, broadcast transmitters, arc welders, etc.
5.2.1

Humidity and Temperature

PDP-11/34 systems are designed to operate in a temperature range of 5° C (41° F) to 50° C (122° F) at
a relative humidity of 10 to 95 percent, without condensation. However, system configurations that use
I/0 devices such as magnetic tape units, card readers, disks, etc., require an operational temperature
range from 15° C (60° F) to 27° C (80° F) at a relative humidity of 40 to 60 percent, without condensation. Nominal operating conditions for a system configuration are a temperature of 20° C (70°
F) and a relative humidity of 45 percent.

5.2.2

Air-Conditioning

When used, computer room air-conditioning equipment should conform to the requirements of the
Standard for the Installation of Air-Conditioning and Ventilating Systems ( Non-Residential) N.F.P.A.
No. 90A, as well as the requirements of the Standard for Electronic Computer Systems, N.F.P.A. No.
73.
5.2.3

Acoustical Damping

Some peripheral devices (such as line printers and magnetic tape transports) are quite noisy. In installations that use a group of high noise level devices, an acoustically damped ceiling will reduce the
noise.

5.2.4

Lighting

5.2.5

Special Mounting Conditions

If CRT peripheral devices are part of the system, the illumination surrounding these peripherals
should be reduced to enable the operator to conveniently observe the display.

If the system will be subjected to rolling, pitching, or vibration of the mounting surface (e.g., aboard
ship), the cabinetry should be securely anchored to the installation floor by mounting bolts. Since such
installations require modifications to the cabinets, DEC must be notified when the order is placed so
that the necessary modifications can be made.
5.2.6

Static Electricity

Static electricity can be an annoyance to operating personnel and can (in extreme cases) affect the
operational characteristics of the PDP-11/34 system and related peripheral equipment. If carpeting is
installed on the computer floor, it should be of a type designed to minimize the effects of static electricity. Flooring consisting of metal panels, or flooring with metal edges, should be adequately
grounded.

5.3

ELECTRICAL REQUIREMENTS

The PDP-11/34 system can be operated from a 115/230 Vac + 10%, 47- to 63-Hz power source. The
primary ac operational voltages should be within the defined tolerances. The primary power outlets at
the installation site must be compatible with the PDP-11/34 primary power input connectors, or
compatible with the primary power input connectors of the 861 Power Controller if the system is
cabinet mounted. Refer to the related mounting box manual for details concerning power requirements.

Two types of connectors are used with the PDP-11/34, depending on whether the system is configured
for 115 Vac or 230 Vac operation. Figure 5-1 shows the plug portion of each connector and a table
provides specifications for both plugs and receptacles.

If the system is cabinet mounted, the 861 Power Controller is used. The power controller requires
different connectors from those used with the BA11-L or BA11-K mounting box. The 861-C Power
Controller is used for 115 Vac operation and the 861-B is used for 230 Vac operation. Figure 5-2
illustrates these connectors and the associated table provides connector specifications.

5-2

230 V
MALE PLUG

15 v
MALE
PLUG

(SINGLE

(S INGLE PHASE)

PHASE)

GROUND

NEUTRAL

RETURN
X

PHASE

CONNEETOR

DESCRIPTION

ADD P
ADD

NEMA

CONFIGURATION

SPECIFICATIONS

POLES |WIRES

PLUG

RECEPTACLE

DEC PART NO.

115V, 15 AMP

5-15

90 -08938

12-05351

230V,
15 AMP

6-15

90-08853

12- 11204

SUFFIX

FOR

PLUG

R SUFFIX

FOR

RECEPTACLE

Figure 5-1

I-2872

Connector Specifications for BAI1-L and BA11-K Boxes

5-3

PHASE OR
NEUTRAL

GREEN

(NEUTRAL

PREFERRED)

GROUND

WHITE

X -

(”

GREEN

NEUTRAL

\ NEMA L6-20R

\ NEMA L6 -20P

230V used with the 861-8B

GREEN G [

EARTH

G’

QA)

WHITE

NEUTRAL

PHASE

BLACK

, G

\ NEMA L5-30R

GREEN

NEMA L5-30P

115V used with the 861-C
11-4813

CONNECTOR SPECIFICATIONS

MODEL

PLUG

NUMBER

861-C

RECEPTACLE (SUPPLIEDBY CUSTOMER)

POWER

RATING

NEMA CODE

DEC PART NO.

115V

30A

L5-30P

L5-30R

12-11191

20 A

L6-20P

L6-20R

12-11194

SINGLE PHASE
861-B

230V
SINGLE PHASE

Figure 5-2

Connector Specifications for 861-B and 861-C Power Controllers

5.3.1
System Grounding
|
The PDP-11/34 3-prong power connector, when inserted into a properly wired receptacle, should
ground the computer chassis. It is unsafe to operate the computer unless the case is grounded because
normal current leakage from the power supply flows to the metal parts of the chassis. If the integrity of
the ground circuit is questionable, the user is advised to measure with a voltmeter the potential between the computer case and a known ground, or to notify the Field Service representative.

5-4

Computer systems are often sensitive to the interferance present on some ac power lines. If the computer is to be installed in an electrically noisy environment, it is necessary to provide primary power to
the computer on a separate power line from lighting, air-conditioning, etc., so that computer operation
is not affected by voltage surges of fluctuations.
Any questions regarding power requirements and installation wiring should be directed to the DIGITAL Sales representative or Field Service engineer.
5.3.2

Specifications Summary

Physical

Dimensions

13.3-cm (5-1/4-inch) chassis

13-1/2cmh X 64 cmw X 48 cm
|

(5-1/4inh X 25inw X 19 in |)
26.3-cm (10-1/2-inch) chassis

26cmh
X 64cmw X 48 cm |
(10-1/2inh X 25inw
X 19in)

Weight

13.3-cm (5-1/4-in) chassis
26.3-cm (10-1/2-in) chassis

20 kg (45 Ib)
50 kg (110 Ib)

Expansion Space
13.3-cm (5-1/4-in) chassis
26.3-cm (10-1/2-1n) chassis

7 slots
7 slots plus space for 3 system units

Electrical
System Power

13.3-cm (5-1/4-1n) chassis
26.3-cm (10-1/2-in) chassis

115/230 Vac + 10%, 47-63 Hz

350 W
800 W

Logic Power
PDP-11/34

BA11-L [13.3 cm (5-1/4 in) chassis]

25 A available for processor backplane

BA11-K [26.3 cm (10-1/2 in) chassis]

25 A available for processor backplane and 25 A
available for expander backplanes

PDP-11/34A
BAI11-L [13.3 cm (5-1/4 in) chassis]
BA11-K [26.3 cm (10-1/2 in) chassis]

32 A available for processor backplane
32 A available for processor backplane and 32 A
available for expander backplanes

The following is a list of typical PDP-11/34 components and the current required for each. Appendix
B provides current requirements and other pertinent information for PDP-11 optional equipment.

Current Required At:
Typical System Components

+5 Vdc

KD11-E (M7265 and M7266)
|10.5 A
KD11-EA (M 8265 and M8266) | 11.5 A
M9301
20A
M9302
1.2 A
MMI11-CP (Active)
30A
MMI11-DP (Active)
4.0 A
MS11-EP (Active)
20A
MS11-FP (Active)
20A
MS11-JP (Active)
20A
Parity Controller (M78350)
1.0A
KY11-LB Interface (M7859) |3.0A
DL11-W (M7856)
20A

+15Vde | -15Vdc

+20 Vdc | -5 Vdc

|
35A
4.0 A
0.8 A
0.85 A
0.95 A

0.1 A
0.1 A
0.1 A

0.05 A

0.15A

0.2A
0.5A

Functional
Word Length

16 bits

Memory Access Time

MOS with parity
MM11-DP core memory with parity

700 ns
570 ns

DMA Rate

MOS memory
Core memory

1.4 M words/second
1.0 M words/second

Unibus Rate

2.5 M words/second

Addressing Space

128K words (124K memory and 4K 1/0O page)

Environmental

Temperature
Relative Humidity
5.4

5°C(41° F) to 50° C (122° F)
10% to 95% (non-condensing)

UNPACKING

The basic PDP-11/34 system is shipped in the package shown in Figure 5-3 [26.3 cm (10-1/2 inch)
mounting box] or Figure 5-4 [13.3 cm (5-1/4 inch) mounting box]. Please study these figures before
unpacking the computer.

5-6

LAMINATED

9905323

SADDLE

REAR PAD
9905644

P
PDP-11/704

BEZEL
PROTECTOR

9905889

POLY BAG

9905129-7

REGULAR
9905650

SLOTTED

CARTON

11-4587

Figure 5-3

Packaging of PDP-11/34 [26.3 cm (10-1/2 inch Box)]

LAMINATED

(9905755)

SADDLE

POLY BAG

(9905129-7)

PDP

BEZEL

11/04

PROTECTOR—

(9905754)

REGULAR

(9905418)

SLOTTED

CARTON

11-4586

Figure 5-4

Packaging of PDP-11/34 [13.3 cm (5-1/4 inch Box)]

5-8

5.5 MODULE UTILIZATION IN TYPICAL SYSTEMS
Figure 5-5 shows the module placement in typical PDP-11/34 (11/34A) systems. Refer to Paragraph
4.2.3 for a detailed discussion of the backplane module utilization.

PDP-11/34 (11/34A) WITH 16K MOS MEMORY

PDP-11/34 (11/34A) WITH 16K CORE MEMORY

M7266 (M8266) CPU CONTROL

M7265 (M8265) CPU DATA PATH

M9301

M7265 (M8265) CPU DATA PATH

DL11-W OR QUAD SPC SLOT

M9301

] DL11-W OR QUAD SPC SLOT

MS11-JP 16K MOS MEMORY

M7850

MM11-DP 16K CORE MEMORY

QUAD SPC SLOT

M7850

HEX OR QUAD SPC SLOT

M9302 * 1

QUAD SPC SLOT

HEX OR QUAD SPC SLOT

QUAD SPC SLOT

M9302 *

QUAD SPC SLOT

PDP-11/34 (11/34A) WITH 32K MOS MEMORY

PDP-11/34 (11/34A) WITH 32K CORE MEMORY

M7266 (M8266) CPU CONTROL

M7265 (M8265) CPU DATA PATH

M9301

[

DL11-W OR QUAD SPC SLOT

M9301

r DL11-W OR QUAD SPC SLOT

MS11-JP 16K MOS MEMORY

MS11-DP 16K CORE MEMORY
MS11-JP 16K MOS MEMORY

M7850

QUAD SPC SLOT
MM11-DP 16K CORE MEMORY

HEX OR QUAD SPC SLOT
HEX OR QUAD SPC SLOT

M9302 *

[

QUAD SPCSLOT

M7850

QUAD SPC SLOT

M9302 *

QUAD SPC SLOT

* M9302 or Unibus “OUT’’ Connector

NOTE:
The M7850 Parity Controller can
be installed in any available modified

Unibus slot (slots 2 through 8, A and B)
11-5455

Figure 5-5

PDP-11/34 Module Utilization

5.6 INITIAL INSPECTION
After unpacking the computer, extend the wire frame assembly containing the logic and power
subassemblies. Refer to Figure 5-6 for the 13.3 cm (5-1/4 inch) box and Figure 5-7 for the 26.3 cm (101/2 inch) box. Examine the following areas:

Check the overall appearance for scratches, dents, chipped paint, dust, etc.

Check for loose or missing hardware (screws, nuts, etc.).

Toggle front panel switches to make certain each switch operates freely and unrestricted.

Examine backplane for bent pins.

Check power and console harness for proper connection to the power supply and front
console. Refer to Figure 5-8 for connector placement and Paragraph 4.2.2.1 for connector
pin locations and signal assignments.

Remove the shipping brackets from both the BA11-L and BA11-K boxes.

MODULE

BACKPLANE

WIRE FRAME

POWER SUPPLY

8141-3

Figure 5-6

Computer Subassemblies of BA11-L Mounting Box

5-10

POWER

SUPPLY

MODULES

OPERATOR
'S CONSOLE
ilH-4814

Figure 5-7

Computer Subassemblies of BA11-K Mounting Box

5-11

SLOT 1

15PIN

6 PIN

prma—

10 PIN
3M

.
)

CONNECTOR*
TO CONSOLE

15 PIN

SLOT 9

MATE-N-LOK CONNECTORS

TO POWER SUPPLY

*3M Connector installed on DD11-PK only

DD11-DK and DD11-PK NINE-SLOT BACKPLANES (module side)
A

15 PIN

SLOT 1

SLOT 4

6 PIN

MATE-N-LOK

CONNECTORS

TO POWER SUPPLY

DD11-CK FOUR SLOT BACKPLANE (module side)

NOTE

The 3M connector is installed only if the operator’s console is present.

Figure 5-8

115456

Backplane Connectors

5-12

5.7

TYPICAL SWITCH SETTINGS OF MODULES

Figure 5-9 shows the typical switch settings of each of the modules in the system. The specific settings

for a particular user’s system will depend upon the configuration. Refer to Paragraph 4.3 for a detailed
discussion of the switch functions on each module.

Py
M7850 Parity Controller
CSR Address = 772100

Jumper IN = Logic O

Jumper OUT = Logic 1
11-4617

Figure 5-9

Typical

Jumper Placement and Switch Settings of Modules
(Sheet 1 of 9)

Ci\\\-l=f——'

4!%55—

y 1 -

M7265

KD11-E Data Path Module

~—"
M7266

]
|

trol Module

Wi
& @
o .,\.

KD11-E Contro

]

[
11-5457

Figure 5-9

Typical

Jumper Placement and Switch Settings of Modules
(Sheet 2 of 9)

N——

)

—

)g -

M8265

KD11-EA Data Path Module

o SN

KD11-EA Control Module

rtore

€
dw

g
11-5458

Figure 5-9

Typical

Jumper Placement and Switch Settings of Modules

(Sheet 3 of 9)

5-15

———

Jumper not installed

M9301 Bootstrap/Terminator Setup for:
ROM Starting Address = 773000
MOS memory without battery backup.

2
-

= -

Switch setting for normal power
.

fai

ail operation in core memory

systems or MOS memory

systems with battery backup.

Jumpers

Not

0
N = ON = Logic
1
F = OFF = Logic
11-4618

Figure 5-9

Typical Jumper Placement and Switch Settings of Modules
(Sheet 4 of 9)

5-16

MS11-EP
4K MOS Memory
0 — 4K Memory Address
Unibus Addresses:
w2

wa &

e w3

we @

ews

000000 — 017777

INn

|»

|o»

L))

N =ON = Logic 0

F = OFF = Logic 1

Jos~_—

)

MS11-FP

8K MOS Memory
0 — 8K Memory Address

Unibus Addresses:

w2 e

000000 — 037777

e wi

ZZTTT

MMM

® ws

we @

9SG vECTI

wad
e ws

N =ON = Logic
0
F = OFF = Logic
1
11-4620

Figure 5-9

Typical

Jumper Placement and Switch Settings of Modules

(Sheet5 of 9)

5-17

MS11-JP

16 K MOS Memory
0 — 16K Memory Address
Unibus Address :

000000 — 077776

w2 @

e Wi

wWa @

e W3

wee

ews

O S ——

o [

|o»

|®

32K MOS Memory
Using two MS11-JP’s

This is the setup of the second MS11-JP.

w2e

16K — 32K Memory Address

¢wew3s

e@
we @W5

A | F

| &

Unibus Addresses:

100000 — 177776

E |n

$)]

F’L

0
N = ON = Logic

[

]

1
F = OFF = Logic
11-5459

Figure 5-9

Typical

Jumper Placement and Switch Settings of Modules

(Sheet 6 of 9)

5-18

;

)

—11

MM11-CP

8K Core Memory
0 — 8K Memory Address
Unibus Addresses:
000000 — 037776

ENNNNNNN'
8

1ot

N = ON = Logic 0
F = OFF = Logic 1
11-4622

Figure 5-9

Typical

Jumper Placement and Switch Settings of Modules
(Sheet 7 of 9)

5-19

0\4——4}L

MM11-DP 16K Core Memory

y | —4p

—!

0 — 16K Memory Address
Unibus Addresses: 000000 — 077776

WWWWWWWWwW

0 N—"

Dy 3 1TM

|
— [

000090

g
mi

—

32K CORE Memory Using two MM11-DP’s
This is the setup of the second MM11-DP,

16K — 32K Memory Address
Unibus Addresses:

100000 — 177776

WWWWWWWW

’

765

000

[
11-5460

Figure 5-9

Typical

Jumper Placement and Switch Settings of Modules

(Sheet 8 of 9)

5-20

S22

_ 2

S 2

DL11-W (Console Device Only)

F———
e
—— — —

Typical Switch settings for standard

300 ;123456789 N
10,
BAUD'F F N F NNFN

)

DEC terminals.

110

BAUD|

FNFNFNFN

10S3

R63*

1 _2_3_4 —5—6—7 —8 —9 _1-0_‘|

RTC
Disbled
|F

N F FNENEF

s1/1 2
N

ERLCd1234567891085
nabled | .

FEENFE

3456 7 89

NFNTFTFNNTFN

= = = = — — ——

300‘12345678910:
BAUD N N FFNNF—N

110

[T 2

BAUD|F

10|,

FNF

—N

—

8{S2

FNFF

N = ON

F = OFF
- = UNUSED

11-4619

Figure 5-9

5.8

Typical

Jumper Placement and Switch Settings of Modules
(Sheet 9 of 9)

FIRST-TIME START-UP PROCEDURE

The following start-up procedure should be performed in sequence and no steps should be omitted.
The procedure requires the following.

e Serial Line Controller (DL11-W or equivalent) is installed.
e Console terminal is ON-LINE.

e Operator’s console (KY11-LA) or programmer’s console (KY11-LB) is installed.

o All M9301 switches are ON.

WARNING

Placing the power switch in the OFF position does
not prevent ac power from being applied to some
areas of the computer when the line cord is plugged
into the ac receptacle.

Lo
-

Step 1

Place the power switch in the OFF position.
Plug the line cord into the ac receptacle.
Place the HALT/CONT switch in the CONT position.
Place the OFF/ON/STNDBY switch in the ON position.

5-21

Step 2

Check for the following indications:
I.

Fan rotation

DC power indicator ON

BATT status indicator on or blinking (BATT indicator is off
if battery backup option is not
present).

Console terminal printed register printout and prompt character ($).
NOTE
If switch 2 of the M9301 is OFF, the BOOT/INIT

switch must be pressed and released to get the register printout and prompt character.

RUN indicator on.

Step 3
Perform the following quick verification routine. (Refer to Paragraph 6.2 if any of the tests yield
incorrect results.)

Action
1. Load address
that location.

Correct Result

173024

and

examine

2. Type a boot command for a non-exist-

ent device.

1. The contents will be 173000.

2. Register printout will be typed on console termi-

nal and RUN light will be on.
NOTE

If the M9301-YF is implemented, this action will
result in a halt, (i.e., register printout is not typed

and RUN light is off).

3. Load address 0. Examine location O.
Deposit 777 into location 0 and exam-

3. The keyboard will no longer respond and the
RUN light will be on.

ine. Start.

4. HALT the processor.

4. The RUN light will be off.

5. CONTinue the processor from the

5. The RUN light will be on.

halted state.

6. HALT the processor. Initiate the
BOOT function. Move the

6. Register printout will be typed on console terminal. The “OLD PC” will be 0.

HALT/CONT switch back to CONT
(KY11-LA only).
NOTE

Return all switches to their proper positions.

5-22

Step 4
Run the PDP-11/34 diagnostic as follows:

Bootstrap load a diagnostic from a peripheral device as described in Paragraph 2.1.3.5.

After booting, refer to the diagnostic writeup for instructions. Let the diagnostic run for two
passes.

Table 5-1 lists the diagnostics associated with the PDP-11/34 system.

Check of Standby Operation

5.8.1

After proper operation of the computer has been verified by the diagnostics, a check of standby

operation (BA11-L only) can be made as follows.

NOTE

MOS memory must be installed in the system to
make this check.

HALT the processor (via the console).

Place the OFF/ON/STNDBY switch in the STNDBY position and check the following
indications:

DC ON indicator will go off.

BATT indicator will be on blinking. (BATT indicator will be off if battery backup is
not present.)

c.
3.

Remain in the STANDBY mode for approximately 1 minute.

Continue processor operation from the halted state and place the OFF/ON/STNDBY
switch in the ON position.
DFKAA).

Rerun

the PDP-11/34 CPU diagnostic (MAINDEC-11-

5-23

Table 5-1

PDP-11/34 Diagnostics

Title

Number

PDP-11/34 CPU Test

MAINDEC-11-DFKAA

PDP-11/34 Trap Test

MAINDEC-11-DFKAB

PDP-11/34 Memory Management Exerciser
PDP-11/34 EIS Instruction Tests

MAINDEC-11-DFKTG
MAINDEC-11-DFKAC

MOS/CORE Memory Exercisers

MAINDEC-11-DZKMA
MAINDEC-11-DZQMC (Rev. C or later)

Combined Parity Memory Test

MAINDEC-11-DCMFA (Rev. C or later)

PDP-11 Power Fail
(if system contains core memory or MOS
memory with battery backup)

MANDEC-11-DZKAQ (Rev. E or later)

DL11-W Serial Line Unit/Real-Time Clock
Diagnostic

MAINDEC-11-DZDLD

NOTE
The DL11-W diagnostic is preferred; however, if it is
unavailable, the following diagnostics may be implemented.

KL11/DL11-A Teletype Test
(if system contains console serial line unit)

MAINDEC-11-DZKLA (Rev. E or later)

Line Frequency Clock Test
(if the line frequency clock is enabled)

MAINDEC-11-DZKWA (Rev. E or later)

5-24

CHAPTER 6

TROUBLESHOOTING

6.1
PDP-11/34 CHARACTERISTICS SUMMARY
This paragraph provides a listing of operation and installation notes peculiar to the PDP-11/34.
Operation (KY11-LA)

6.1.1

Pressing the BOOT/INIT switch while a program is running will cause that program to be
aborted.
The console emulator will accept octal numbers only.
The console emulator will accept even addresses only (i.e., least significant digit must be a 0,
2,4, or 6).

First octal number typed is the most significant digit.
The console emulator can accept up to six octal digits. If all six numbers are input, the most

significant number must be a zero or a one.
[f the program causes the system to halt, the HALT/CONT switch must first be placed in
the HALT position and then moved to CONT to resume operation.

6.1.2

Operation (KY11-LB)
I

Examine and deposit functions are operative only if processor is halted.

The control key (CNTRL) must be pressed to enable the initialize, halt/single step, continue, start, and boot functions.

The display must be cleared before entering any new data.
The programmer’s console requires an 18-bit address.
In order to single instruction step the processor from a given starting address, the program
counter (R7, Unibus address 777707) must be loaded with the starting address.

The BUS ERR indicator reflects a bus error by the console only. The indicator does not
reflect bus errors due to the processor.

6-1

6.1.3

Installation
1,

The KDI11-E (KDI11-EA) processor modules must be installed in the first two backplane
slots of the system.

The M9302 terminator module must be installed in the last backplane slot of the system. The

M9302 must not be installed in a modified Unibus slot. The modified Unibus slots are:
DDI11-CK - Slots 2 and 3 (sections A and B)
DDI11-DK - Slots 2 through 8 (sections A and B)
DD11-PK - Slots 2 through 8 (sections A and B)

6.2

The DC OFF position of the power switch does not remove ac power from the system. AC
power is removed only by disconnecting the line cord.

The DC ON light indicates that dc power is applied to the logic but does not imply that the
power is within required levels.

A bus grant jumper card (G727) must be placed in connector D of any unoccupied SPC
section or grant continuity will be lost.

Unibus cables (i.e., BC11-A) must never be plugged into a modified Unibus slot.

In boxes other than BA11-L, there is not sufficient drive capability on the LTC L signal to
drive multiple loads. Since each DL11-W constitutes a load (even if the line clock is disabled
by the switch), multiple DL11-Ws in a box will overload the LTC L signal causing line clock
failures. To alleviate the loading effect of the additional DL11-Ws, remove resistor R63
from all DL11-W modules except the one being used as a line clock. If multiple DL11-Ws
are used on the same system, the line clock must be enabled (via switched) only on the
DL11-W being used as a line clock.

TROUBLESHOOTING PROCEDURES

This paragraph provides the user with a quick method for isolating major problem areas of the system.
The quick verification routine consists of seven tests that should be performed in sequence. The associated flowchart for each test lists the possible problem areas that may have caused incorrect test results.
Each flowchart is accompanied by a detailed explanation containing additional tests to help further
isolate the problem. These troubleshooting procedures assume that the system has been installed and
configured according to Chapters 4 and 5 and that the M9301 switches are set as in Figure 5-8.
6.2.1

Quick Verification Routine

The quick verification tests should be performed in sequence. If an incorrect result is obtained, refer to
the flowchart and explanation associated with that test. These procedures are applicable for both the
KY11-LA and optional KY 11-LB consoles.

6-2

Correct Result

Action

. Register printout will be typed on console termi-

. Turn power on.

nal and RUN light will be on.

. Load address
that location.

173024

and

examine

. Type a boot command for a non-existent device.

. The contents will be 173000.

. Register printout will be typed on console terminal and RUN light will be on.
NOTE

If the M9301-YF is implemented, this action will
result in a halt (i.e., register printout is not typed
and RUN light is off).
. Load address 0. Examine location O.
Deposit 777 into location 0 and exam-

. The keyboard will no longer respond and the
RUN light will be on.

ine. Start.

. The RUN light will be off.

. Halt the processor.

. CONTinue the processor from
halted state.

the

. Halt the processor. Initiate the BOOT
function. Move the HALT/CONT
switch back to CONT (KYII-LA
only).

. The RUN light will be on.

. Register printout will be typed on console terminal. The “OLD PC” will be 0.

NOTE
Return all switches to their proper positions.

The following is a brief explanation of each of the quick verification tests:
Correct Result

Action 1
Turn power on.

When the system is powered up, the first five processor diagnostics of the M9301 are executed. The

diagnostic tests performed are:
l.

All single operand instructions tests (Test 1)

All double operand instructions tests (Test 2)

Jump test (modes 1, 2, and 3) (Test 3)

Single operand, non-modifying, byte test (Test 4)
Double operand, non-modifying test (source modes 1 and 4, destination modes 2 and 4)
(Test 5).
Paragraph 3.3 contains a description of each of the above diagnostic tests.

Once the fifth diagnostic test has been performed, the M9301 will enter the register display routine.
The console teletype will print out the contents of RO, R4, R6, and RS (Paragraph 2.1.3.2). R5 contains the “OLD PC”’ since the microcode moves the contents R7 into RS before entering the power-up
routine. The sequence of register contents is followed on the next line by a prompt character ($) which
indicates that the console emulator is waiting for a command. If the prompt character is received, it

can be assumed that a portion of the processor, M9301, console interface, console terminal, and
Unibus are functioning properly.
If the terminal does not type out the register sequence and prompt character, refer to Figure 6-1.
Action 2

Load address 173024 and examine that
location.

Correct Result

The contents will be 173000.

This test checks a portion of the console emulator routine and the switch settings of the M9301. If the
contents of location 173024 are not 173000, the switch settings of the
M9301 are incorrect. It is possible
to receive the register display and prompt character in Action 1 without performing any diagnostics.
All M9301 switches should be on. If they are not on, set them correctly and repeat Action 1. Refer to
Figure 6-2 if incorrect results are obtained.
Action 3

Correct Result

Type a boot command for a non-existent
device.

If the M9301-YF is implemented, this action will
result in a halt (i.e., register printout is not typed and
RUN light is off).

This test allows the user to execute the remainder of the M9301 diagnostics without actually booting
from a peripheral device. The remaining diagnostic tests performed are:
1.
2.
3.

Double operand, modifying byte test (Test 6)
JSR test (modes 1 and 6) (Test 7)
Memory test.

The bootstrap routine will try to boot from the non-existent peripheral. After failing to boot, the
console terminal will type the register printout and the prompt character (§). After successful completion of the remaining diagnostic tests, the user can assume that a large portion of the processor,
M9301, console interface, and terminal are functioning and that memory (up to 28K) contains no
major errors. Refer to Figure 6-3 if the register printout and prompt character are not received.
Action 4

Correct Result

Load address 0. Examine location O.

The keyboard will no longer respond and the RUN

Deposit 777 into location 0 and examine.

light will be on.

Start

This test checks the remainder of the console functions, specifically DEPOSIT and START. Refer to
Figure 6-4 if an incorrect response is obtained.

Action §

Halt the processor.

Correct Result

The RUN light will be off.

This test checks the logic on the console and processor that is associated with the HALT function.
Refer to Figure 6-5 if the RUN light remains on.
Action 6

CONTinue processor operation from the
halted state.

Correct Result

The RUN light will be on.

This test checks the logic on the console and processor that is associated with the CONT function.

Refer to Figure 6-6 if the RUN light does not come on.
Action 7

Correct Result

Halt the processor. Initiate the BOOT
function. Move the HALT/CONT

switch back to CONT (KY11-LA only).
This test checks the BOOT switch on the console, the cable connecting the console and M9301 and the

portion of the M9301 associated with the BOOT function. Refer to Figure 6-7 if the register printout
and prompt character are not received or if the “OLD PC” is wrong.

6-5

6.2.2 Troubleshooting Flowcharts and Explanations
This paragraph provides a chart and explanation for each of the quick verification tests.
Action 1

Turn power on.

Correct Result

and RUN light will be on.

Action | has failed if the register printout and prompt character were not received on power up. The
following symptoms will help the user locate the problem area (Figure 6-1).
1.

RUN light flashes once but does not stay on.

There are several possible problem areas that may cause this symptom.
a.

The HALT/CONT switch could be in the HALT position. Place the switch in the
CONT position and repeat Action 1.

Switch number 2 on the M9301 may be in the off position. Press and release the
BOOT/INIT switch. If the register printout and prompt character are then received,
the only problem is that switch 2 is in the off position.
There may be a problem with the console terminal interface (i.e., interface not present
in system or not set to correct address).

The HALT GRANT or HALT REQUEST signals may be causing the Unibus to hang.
Check the BUS SACK signal line on the processor module. If this line is low, trace the
error back through the console HALT GRANT and HALT REQUEST signals. If
BUS SACK is not low, there may be an internal problem with the console.

A problem may exist with the processor modules and one of the first five diagnostic
tests could have failed.
f.

The M9301 module may be functioning incorrectly.

RUN light is off but DC ON light is on.

The DC ON light does not necessarily indicate that dc power is within the required levels.
However, when it is off, it does indicate that +5 V is not present. BUS INIT will turn the
RUN light ON if +5 V is present. BUS INIT can be generated by pressing the BOOT /INIT
switch with the HALT/CONT switch in the CONT position (KY11-LA) or by pressing
INIT and CNTRL simultaneously (KY11-LB). If the RUN light still does not turn on, a
problem may exist with the console.

6-6

RUN light is on.
If the RUN light is on but the register printout and prompt character are not received, a
further test may be performed to isolate the problem area. The RUN light, when on,
indicates that the processor is not halted. Therefore, if there are no other errors in the
system, the RUN light being off indicates that a HALT was executed by the processor or the
console. The user can determine if the Unibus is hung or if there is a grant problem by
halting and then continuing processor operation. This action will issue a halt command and
if the Unibus is functioning the RUN light will go off and then back on.
d.

(1)

If the RUN light does not obey the HALT function and remains on:

Check the Grant cards. If any of the cards are missing or installed with the etch
facing away from the processor module, all the Grant lines will go high (except
NPG). Assertion of a Grant line will cause the M9302 to issue BUS SACK L and
the processor will turn off its clock. If the Unibus is lightly loaded, remove the
M9302. If Unibusis heavily loaded, replace the M9302 with an M930 terminator.
If the register printout is then recelved there is a Grant problem and the user
should proceed to step (2).

(2)

Check the BUS SACK signal line on the processor module. If BUS SACK is
asserted low, then check the Grant lines on the M9302 module. The NPG signal
line is continued by backplane jumpers and not with grant continuity cards.
If BUS SACK is not asserted, check the MSYN and SSYN lines to see if either

signal 1s asserted.

If the RUN light obeys the HALT function and goes off and then back on:

(1)

A console teletype error may be causing the program to loop on the READY bit.
This condition can be checked by removing the interface, inserting a grant continuity card, and repeating Action 1. If the RUN light goes out after performing
Action 1, the console interface or terminal is causing the error.

(2)

The processor may be executing a program loop in memory (this is unlikely with
MOS memory and no battery backup).

(3)

One of the first five M9301 diagnostic tests may have failed, causing the processor
to execute a branch self instruction.

Any symptom not described above:

Cursory checks should be made by the user if other symptoms are encountered.
Checking areas such as power connections, module placement, and switch and jumper
settings will help to solve most simple problems.

SYMPTOM ]
—gp»

Printout occurs

h’OSSIBLE PROBLEM AREA l
———® Switch 2 on M9301 in OFF position

F—-—’ HALT/CONT switch in HALT position (KY11-LA only)

LSYMPTOM ]

l FURTHER TESTT

RUN light flashes

r————’

once but will not

—_—e

Press and release

BOOT/INIT switch

(——& Console interface problem
—_—r

Printout

not received

—t—p»> HALT GRANT or HALT REQUEST problem

stay ON
———8 M9301 DIP-switch problem

I SYMPTOM
>

IJ’OSSIBLE PROBLEM AREA

RUN light is OFF

- BUS INIT

DC ON light is ON

ACTION 1

.
.
Register Printout and

Faulty M9301 or M7263

LSYMPTOM ]

@ KY11-LAor KY11-LB
—

Prompt Character not
received.

[ SYMPTOM ]

[ FURTHER TEST ]

l SYMPTOM ]

RUN light is ON

Halt and then continue

—

remains ON

—®

Power down,
Remove M9302,

Pnntf)ut

Bus Grant

Received

l FURTHER TEST ]

RUN light
e >

[POSSIBLE PROBLEM AREA|

Problem

Power UP

Printout

————r——4#

Unibus hung

not Received

9 KY11-LAor KY11-LB
Power down,

L SYMPTOM ]
—®

[LOSSIBLE PROBLEM AREA]

RUN light
goes OFF and
then ON

Any symptom not

describedabove @~
T Power

———— Configuration (module placement, switch settings, etc.)

Remove

—_——

f:onsole
interface,

Power Up

—_——

RUN light

_—

Console terminal

goes OFF

or interface

RUN light

Branch-Setf

® (M9301 Diag.)

remains ON
,

Program looping
in memory
11-56071

Figure 6-1

6-9

Action 1

Action 2

Correct Result

Load address 173024 and examine that
location.

The contents will be 173000.

Location 173024 is the address of the M9301 dip-switch pack. If location 173024 is examined and the
contents are not 173000, the switches on the M9301 may be set incorrectly. For these tests, all switches
on the M9301 should be on. If the switches are set correctly and location 173024 does not contain
173000, there may be an M9301 hardware failure. If some other symptom results, an error in the input
format may have been made or the console emulator may have failed. Refer to Figure 6-2.

I SYMPTOM I
—

LPOSSIBLE PROBLEM ARE;]

Contents of

Incorrect M9301 switch settings

location 173024

are not 173000
M9301 Hardware failure
ACTION 2

LSYMPTOfl

L—D

D’OSSIBLE PROBLEM ARE;]

Any other symptom

Input format error —E Operator

[ Console emulator failure

Lower case KYBD
11-5075

Figure 6-2

Action 2

Action 3

Type a boot command for a non-existent

device.

Correct Result

and RUN light will be on.

NOTE
If the M9301-YF is implemented, this action will
result in a halt, (i.e., register printout is not typed
and RUN light is off).

If the M9301 (YA, YB, and YF versions) diagnostic tests 6, 7, or memory test fails, the result is a halt.
If the M9301-YF diagnostic tests 6, 7, and memory test are all successful, the result is also a halt.
Therefore, if the RUN light goes off after booting from a non-existent device, it can be assumed that
one of the diagnostics has failed (M9301-YA, YB, and YF versions) or that the diagnostics were
successful (M9301-YF only). Proceed as follows:
1.

Halt the processor and initiate the BOOT function.

Return the HALT/CONT switch to CONT (KY11-LA only).

6-11

The register printout will be typed and the value of the “OLD PC” will indicate which test
has failed.
“OLD PC”
(M9301-YA)

“OLD PC”
(M9301-YB)

“OLD PC”
(M9301-YF)

Failed Test 6

165320

173452

Failed Test 7
Failed Test 7
Failed Memory Test

165350
165372
165536

173472
173514
173764

165650
165664
165700
166000

All Tests Successful

000002

It is possible to fail at location 165250 (M9302-YA), 173402 (M9301-YB), or 165600 (M9301-YF) if
address 500 does not return SLAVE SYNC. If the memory test fails, additional information can be
evaluated.

The register printout also includes:
M9301-YA and YB

M9301-YF

RO=Expected data
R4=Received data
R6=Failing address

RO=Failing address
R4=Received data
R6=Expected data

If the expected data and received data are the same, it is highly probable that an intermittent failure has
been detected (i.e., timing or margin problem). Other failures such as double bus errors could cause the
RUN light to go off.
If the register printout is not received after the nonexistent boot, and the RUN light remains on,
reboot the system via the BOOT switch. This action will reboot the system and cause the register
printout to be typed. The user can then determine where the processor is running by examining the
“Old PC.”

[ POSSIBLE PROBLEM AREfl

{ SYMPTOMJ
%

RUN light goes OFF —1'———’ Diagnostic test 6 or 7 failed
pb———»

Memory test failed

————®

M9301-YF tests successful

L’ Other

ACTION 3 ——

[

LSYMPTONLI

FURTHER TEST

L——-’ RUN light remains ON ———————# Reboot system to get PC
11-5076

Figure 6-3

Action 3

6-12

Action 4

Correct Result

Load address 0. Examine location O.

The keyboard will no longer respond and the RUN

Deposit 777 into location 0 and examine.
Start.

light will be on.

If an incorrect response results from Action 4 (i.e., keyboard continues to respond, RUN light is off,
etc.), two possible problems may exist. The input format on the terminal may have been erroneous or
there may be a fault in the M9301 firmware.

rSYMPTOMJ
ACTION 4

[ POSSIBLE PROBLEM AREA ]

Incorrect response

—4@»

—— @

Input format error

M9301 firmware fault

11-4645

Figure 6-4

Action 4

Action 5

Correct Result

The RUN light will be off.

Halt the processor.

If the HALT function is initiated and the RUN light remains on, a problem may exist with the HALT
REQUEST or HALT GRANT signals or the console may be malfunctioning.

[ SYMPTOMJ
ACTIONS

[ POSSIBLE PROBLEM AREA l

RUN light remains ON

———@

Halt Request problem

Halt Grant problem

l——. KY11-LA or KY11-LB malfunction
11 4646

Figure 6-5

Action 5

6-13

Action 6

Correct Result

CONTinue processor operation from the
halted state.

The RUN light will be on.

If the CONTinue function is implemented and the RUN light does not come on, the console is

malfunctioning.

EYMPTOM‘]
ACTION 6

[jOSSIBLE PROBLEM ARE;]

RUN light remains OFF

¥ KY11-LA or KY11-LB malfunction

114647

Figure 6-6

Action 6

Action 7

Correct Result

Halt the processor. Initiate the BOOT
function. Move the HALT/CONT
switch back to CONT (KY11-LA only).

If the register printout does not result from Action 7, the boot cable (from the console to the M9301)

may be faulty or connected improperly.

If the register printout occurs but the wrong “OLD PC” is received, the BOOT /INIT switch may have
been pressed twice (KY11-LA only) or there may be noise on the boot cable.

fpossneus PROBLEM AREA]

fvaPTOM J

——»

ACTION 7—T—® Register Printout s not received

Boot cable fault

FPOSSIBLE PROBLEM AREA]

SYMPTONL]

- Noise on boot cable

L——-’ Wrong “OLD PC’’ received

L——. BOOT/INIT switch pressed twice (KYII-LA only)
11-4648

Figure 6-7

Action 7

6-14

APPENDIX A
KY11-LB MAINTENANCE MODE OPERATION

A.1
INTRODUCTION
This chapter covers the keypad facilities of the programmer’s console available for hardware maintenance of the processor.
A.2 MAINTENANCE MODE KEY OPERATIONS
The following definitions apply to a subset of the same keys used in console mode; however, the
functions and operations differ from those in console mode. In general, console mode functions are
not available while in maintenance mode, and many keys have no function in maintenance mode.
NOTE
Maintenance mode operation is indicated by the
MAINT indicator being on.

In order to use the hardware maintenance features available in maintenance mode, the maintenance
cables must be connected between the KY11-LB interface board (M 7859) and the processor board
(M7266) (Figure A-1). An exception to this is the No. 5 (maintenance mode) operation which is used to
allow the console to examine or deposit into memory or device registers without the processor being
either present or functional.
NOTE
The maintenance mode is entered by pressing the No.
1 key and the CNTRL key at the same time.

DIS AD (Maintenance Mode) - Used to display Unibus address lines.
1.

Press and release the DIS AD key.

Unibus address lines will be sampled (read once) and displayed, i.e., display will not be
updated as address lines change.

EXAM (Maintenance Mode) - Used to display Unibus Data lines.
I.

Press and release the EXAM key

Unibus data lines will be sampled and displayed.

A-1

RRS R
AEE

w»fi&*t#
-

8141-14

Figure A- 1

KY11-LB Main tenance Cable Connection

A-2

HLT/SS (Maintenance Mode) - Asserts MANUAL CLOCK ENABLE and displays MPC (microprogram counter).

Press and release HLT/SS key.

MANUAL CLOCK ENABLE will be asserted.

MPC will be sampled and displayed.

CONT (Maintenance Mode) - Single micro-steps the processor through one micro-state and displays
the MPC.

Press and release the CONT key.

MANUAL CLOCK will be pulsed.

New MPC will be sampled and displayed.

BOOT (Maintenance Mode) - Boots the M9301. If MANUAL CLOCK ENABLE is asserted, the
M9301 routine will not be entered but because the M9301 simulates a power fail the processor will
power up through location 24.
1.

Press and release BOOT key.

The display is not affected. If MANUAL CLOCK ENABLE is asserted, the MPC is now at
the beginning of the power-up sequence. To see the new MPC, use HLT/SS key.

START (Maintenance Mode) - Drops MANUAL CLOCK ENABLE.
1.

Press and release START key.

MANUAL CLOCK ENABLE is released.

Samples and displays MPC.

CLR (Maintenance MODE) - Returns console to console mode operation.
1.

Press and release CLR key.

MAINT indicator is off.

Processor should halt.

Program counter should be displayed.

No. 5 (Maintenance Mode) - Allows the console to take control of the Unibus if a processor is not in
the system.
.

Press and release the No. 5 key.

The MAINT indicator will be off (console mode operation now).

Console attempts to read the program counter which is not present and therefore the BUS
ERR indicator will be on.
A-3

A.3 NOTES ON OPERATION
If the single micro-step feature in maintenance mode is to be used, it is preferable that the processor be
halted prior to entering maintenance mode. The assertion of MANUAL CLOCK ENABLE, which
turns the processor clock off if it is running, cannot be synchronized with the processor clock. There-

fore, if the processor is not halted, the clock may be running and the assertion of MANUAL CLOCK
ENABLE may cause an erroneous condition to occur.
In order to single micro-step the processor from the beginning of the power-up sequence, the following

steps may be used.
1.

Halt the processor if possible.

Use CNTRL No. 1 to enter maintenance mode.
Use HLT/SS to assert MANUAL CLOCK ENABLE (RUN indicator should come on).

Use BOOT to generate a simulated power-fail (will work only if M9301 is present in the
system).

Use HTL/SS to display the MPC (microprogram counter) for the first micro-step in the
power-up routine.

Use CONT to single micro-step the processor through the power-up routine. (The new MPC
will be displayed at each step.)

Unibus address lines and Unibus Data (see the note below) lines may be examined at any
micro-step by using DIS AD and EXAM keys respectively. Use of these keys does not
advance the microprogram. To redisplay the current MPC without advancing the microprogram, use the HLT/SS key.
To return from maintenance mode to console mode, use the CLR key.

To single micro-step through a program, the program counter (R7) must first be loaded with
the starting address of the program as in signal instruction stepping the processor, prior to
entering maintenance mode.

APPENDIX B

EXTENDED ADDRESSING

B.1 INTRODUCTION
This appendix applies to use of the M9301-YA, -YB, and -YF in PDP-11/34 systems which do not
have a programmer’s console. When the memory of a PDP-11 system is extended beyond 28K, the
processor is able to access upper memory through the memory management system. However, the

console emulator normally allows the user to access only the lower 28K of memory. This appendix
explains how the user can gain access to upper memory in order to read or modify the contents of any
location. The reader should be familiar with the concepts of memory management in the KD11-E
processor.
|
B.2 VIRTUAL AND PHYSICAL ADDRESSES
Addresses generated in the processor are called virtual addresses and are 16 bits in length. Physical
addresses refer to actual locations in memory. They are asserted on the Unibus and are 18 bits in
length.
B.3 ADDRESS MAPPING WITHOUT MEMORY MANAGEMENT
With memory management disabled (as is the case following depression of the boot switch), a simple
hardware mapping scheme converts virtual addresses to physical addresses. Vitual addresses in the 0 to
28K range are mapped directly into physical addresses in the range from 0 to 28K. Virtual addresses of
the I/0O page, in the range from 28K to 32K (160000-177776), are mapped into physical addresses in
the range from 124K to 128K.
B.4 ADDRESS MAPPING WITH MEMORY MANAGEMENT
With memory management enabled, a different mapping scheme is used. In this scheme, a relocation
constant is added to the virtual address to create a physical or “relocated’’ address.
Virtual address space consists of eight 4K banks, where each bank can be relocated by the relocation

constant associated with that bank. The procedure specified in this section allows the user to:
1.

Create a virtual address to type into the Load Address command.

Determine the relocation constant required to relocate the calculated virtual address into the
desired physical address.

Enable or disable the memory management hardware.

B.S CREATION OF A VIRTUAL ADDRESS
The easiest way to create a virtual address is to divide the 18-bit physical address into two separate
fields - a virtual address and a physical bank number. The virtual address is represented by the lower
13 bits, the physical bank by the upper 5 bits. The lower 3 bits of the physical bank number (bits 13, 14,
15) represent the virtual bank number. Thus, if bits 13, 14, and 15 are all zeros, the virtual bank
selected is zero. The user should calculate the relocation constant according to Table B-2; then, deposit
this constant in the relocation register associated with virtual bank 0 (Table B-1).

B-1

One relocation l:egister exists for each of the eight virtual banks. In addition to the relocation registers,
each bank has its own descriptor register which provides information regarding the types of access
allowed (read only, read or write, or no access).

The memory management logic also provides various forms of protection against unauthorized access.
The corresponding descriptor register must be set up along with the relocation register to allow access
anywhere within the 4K bank.
B.6

AN EXAMPLE

For example, assume a user wishes to access location 533720. The normal access capability of the
console is 0 to 28K. This address (533720) is between the 28K limit and the I/O page (760000-777776)
and consequently must be accessed as relocated virtual address with memory management enabled.
The virtual address is 13720 in physical bank 25 and is derived as follows.
All locations in bank 25 may be accessed through virtual addresses 000000-017776. The relocation and
descriptor registers in the KD11-E are still accessible since their addresses are within the I/O page.
Note that access to the I/O page is not automatically relocated with memory management, while
access to the I/0 page is automatically relocated when memory management is not used.

The relocation constant for physical bank 25 is 005200. This constant is added in the relocation unit to
the virtual address, as shown, yielding 533720.
013720
520000

Virtual Address
Relocated Constant (Table B-2)

533720

Physical Address

The Unibus addresses of the relocation registers and the descriptor registers are given in Table B-1.
The relocation constant to be loaded into the relocation register for each 4K bank is provided in Table
B-2. The data to be loaded in the descriptor register to provide read/write access to the full 4K is
always 077406.

The Unibus address of the control register to enable memory management is 177572. This register is
loaded with the value 000001 to enable memory management; it is loaded with O to disable it.

To complete the example previously described (accessing location 533720), the console routine would
be as follows:

SL
$D
SL
$D
SL
$D
S$L
$D
$L
$D

$L
$E

172340
5200
172356
7600
172300
77406
172316
77406
177572

/Access relocation register for virtual bank 0
/Deposit code for physical bank 25
/Access relocation register for virtual bank 7
/Deposit code for the I/O page
/Access descriptor register, virtual bank 0
/Deposit code for read/write access to 4K
/Access descriptor register virtual bank 7
/Deposit code for read/write access to 4K
/Access control register

13720

/1 Load virtual address of location desired
/Examine the data in location 533720

/Enable memory management
/Data will be displayed

B-2

Table B-1

Unibus Address Assignments

Virtual

Relocation

Descriptor

Virtual Address

Bank

160000-177776
140000-157776
120000-137776
100000-117776

7
6
5
4

172356
172354
172352
172350

172316
172314
172312
172310

040000-057776
020000-037776

2
1

172344
172342

172304
172302

000000-017776

172340

172300

060000-077776

Table B-2

172346

172306

Relocation Constants

Physical

Relocation

Physical

Relocation

Bank Number

Constant

Bank Number

Constant

37
36
35
34
33
32
31
30
27
26
25
24

007600
007400
007200
007000
006600
006400
006200
006000
005600
005400
005200
005000

17
16
15
14
13
12
11
10
7
6
5
4

003600
003400
003200
003000
002600
002400
002200
002000
001600
001400
001200
001000

004600

004400

3
2

000600

22
21
20

004200
004000

|
0

000200
000000

000400

Loading a new relocation constant into the relocation register for virtual bank 0 will cause virtual
addresses 000000-017776 to access the new physical bank. A second bank can be made accessible by
loading the relocation constant and descriptor data into the relocation and descriptor registers for
virtual bank 1 and accessing the location through virtual address 020000-037776. Seven banks are
accessible in this manner, by loading the proper constants, setting up the descriptor data, and selecting
the proper virtual address. Bank 7 (I/O page) must remain relocated to physical bank 37 as it is
accessed by the CPU to execute the console emulator routine.
Memory management is disabled by clearing (loading with 0s) the control register 177572. It should
always be disabled prior to typing a ‘““boot” command.

The start command automatically disables memory management and the CPU begins executing at the
physical address corresponding to the address specified by the previous Load Address command.
Depressing the boot switch automatically disables memory management. The contents of the relocation registers are not modified.
The HALT/CONTINUE switch has no effect on memory management.

B-3

APPENDIX C
SUMMARY OF

EQUIPMENT SPECIFICATIONS

This table provides mechanical, environmental, and programming information for PDP-11 optional
equipment. The equipment is arranged in alphanumeric order by model number.

NOTES
.

Mounting Codes

CAB = Cabinet mounted. If a cabinet is included with the option, it is indicated by an X in
the “Cab Incl” column.
FS = Free standing unit. Height X Width X Depth dimensions are shown in inches.

TT = Table top unit.
PAN = Panel mounted. Front panel height is shown in inches. An included cabinet is
indicated when applicable.

SU = System Unit. SU mounting assembly is included with the option.
SPC = Small Peripheral Controller. Option is a module that mounts in a quad module, SPC
slot.
MOD = Module. Height is single, double, or quad.

() = Option mounts in the same space as the equipment shown within the parentheses.

Some options include 2 separate physical parts and are indicated by use of
a plus (+) sign.
Cabinet and peripheral equipment (such as magnetic tape) are included in the specifications.
Relative humidity specifications mean without condensation.
Equipment that can supply current is indicated by parentheses () around the number of
amps in the “POWER” columns. MEMORY POWER: MF11- and MMI11- require the
same amount of power. In this table, MF11- power figures show the power required when
the memory is active, while MM 11- figures reflect that required by an inactive unit.
5.

Non-Processor Request devices are indicated by an X in the “NPR” column.

CONVERSION FACTORS
(inches)

2.54

(cm)

(Ibs)
(Watts)
[(°C)X9/5] + 32

X
X

0454
3.41

=
=
=

(kg)
(Btu/hr)
(°F)
C-1

Description

Model

Number
AA11-D
ADO1-D
AFCI11
BA11-ES
BA614
BB11
BB11-A

BCI1A
BM792-Y
CB11
CDI1-A
CDI11-E
CMII-F
CRI11
DA11-B
DAII-F
DBI11
DC11-A
DD11-A
DD11-B
DD11-D
DECkit O1-A

DECkit 1 1-F

DECkit 11-H

DECkit 11-K

DECkit 11-M
DFOI1-A
DF11
DHI11
DJ11
DLI1-A
DLI11 (others)

DL11-W

DM11-BB

DMC-11

DNI11
DP11
DQIl11
DR11-B
DR11-C
DTO3-F
DX11

D/A Subsystem
A/D Subsystem
A/D Subsystem
Mounting Box
D/A Converter
Blank Mntg Panel
Blank Mournting

Mounting
Code

SU
PAN
CAB
PAN
(AA11-D)
SU.
SU

Size

Cab
Incl

HXWXD
(inches)

Weight | Oper

Rel

Cur needed/(supplied)

Power

(amps)

(W)

(Ibs) | Temp

Humid

5V I 115 Vac / Other

10-50
0-55
10-55

20-95
10-95
10—-95

(°C)

100

10%2

POWER

ENVIRONMENTAL

MECHANICAL

(%)

0.5
0.5
15

PROGRAMMING

Ist Reg

Int

‘BR

Dis

Address

Vector

Level

60
60
1700

776 756
776 770
772 570

140,144
130
134

4,5
4-7
4

Panel (non-slotted

SPC
Cab

650

764 000

float

4-7

4
6
4
4

450
700
400
400

772 460
772 460
777 160
777 160
772 410

230
230
230
230
124
float

4
4
6
6
5
7

/74 000

float

1.84

User

10-95

391

User

0 70

10-95

1.97

User

0-70

10--95

1.75

User

10-50

10-90

85
200
60
60

10-50
10-50
10-50
10-50

10-90
10-90
10-90
10-90

510—-50

10--95
20-90

0-50

10 -95

SuU

0-70

10- 95

0- 70

1/0 Interface:

SuU

/O Interface:

SuU

Card Reader
Card Reader
Card Reader
Card Reader
UNIBUS Link
UNIBUS Window
Bus Repeater
Asynch Line Inter
Periph Mntg Panel
Periph Mntg Panel
Periph Mntg Panel
Remote Analog Data
Concentrator: 8

Channels, Senal

[/O Interface: 3

SU+TT
SU+TT
SPC + TT
SPC+TT
SU
SU
SU
SU
SU
SU
2SU
PAN

X
14 X 24 X 18
38 X 24 X 38
[1 X 19X 14
11X 19X 14

0.3

5.6

300

Interface

“NPR

Bus

2.5
2.5
1.5
1.5
4
5
3.2

see Product Bull

Number

1
1
1

AAll-D
ADO1-D
AFCl11

1
1,2

BCI1A
BM792-Y
CBl11

1.5@ 115 Vac

0.75 @ 230 Vac

BAI11-ES
BA614
BB11
BB11-A

1
1
1
1
1
1
1+ 1
1

CDI1-A
CDI11-E
CMI11-F
CRI11
DA11-B
DAI1I-F
DB11
DC11-A
DD11-A
DD11-B
DD11-D
DECkit 01-A

User

DECkit 11-F

User

5-6

DECkit 11-H

DECkit 11-K

DECkit 11-M

2
1
1
|

DFOI-A
DF11
DHI1
DJ11
DLI1-A
DLI11 (others)

X
X
X
X

‘

5% X 19 X 13

Model

Loads

blocks)

UNIBUS Cable
Bootstrap Loader
Telephone Switching

UNIBUS

175

Words In/4 Words
Out

/O Interface: 4

Words In/4 Words

Out

8 Words In

User

Instrumentation

Interface

Acoustic Coupler
Line Sig Cond
Asynch Line MX
Asynch Line MX
Terminal Control
Asynch Line Inter

Asynchronous

Interface and
Line Clock
Modem Ctr. MUX

Microprocessor and

Line Unit

TT
DF slot
2 SU
SuU
SPC
SPC

SPC

(DH11)

2 SPC

6X 7X 12

0-60
5-45
|

10--95

Quad Ht

2 Hex Ht

4.5

Auto Calling Unit
Synch Line Inter
DMA Sync Line

0-40
0-40
10- 50

20-90
20-90
10 90

DMA Interface
General Interface
UNIBUS Switch
IBM Chan. Interface

SuU
SPC
PAN
CAB

10-50
10-50

20-90
20-90

10--55

10-90

FP11-A

Fl(/)ating Point for

GT40

Graphics Terminal

11/34A

SPC

Hex Ht

18 X 20 X 24

005SA@+15V

0.15SA@-15V

2.8

SU
SU
SU

Interface

8.4
S
1.8
1.8

0.3
see Product Bull.
024 A@-15V
see Product Bull.
0.15SA@«@-15V
0.ISAE-15V

180
150

10-50

20-90

15-35

20-80

0.I0A@* 15V
0.1I0A@* 15V
004 Al +15V

1.4
2.5
5.7

7.0

Switch

float
float
060,064
float

5
5
4
4

007A@-15V

A. Int.-SS | A. Int.4

Line
Selectable | Line
CLK-104 | CLK-6
(SS)
float
775 000

3.3
1.5

float
float
777 560
176 500

775 200
774 400
float

float
float
float

4
5
5

172 410
167 770

5
5
7
4-7

2
2.5

300

776 200

124
float
user
float

1500

float

X
X

DL11-W

1
1
l

DN11
DP11
DQI1

1
T
1 +1
1

DRI1-B
DRTIL
DTO3-F
DX11-B

FP11-A

GT40

Model

Number
H312-A
H720-E
H722
H742

Description

Null Modem
Power Supply
Transformer
Power Supply

Mounting

Code

Power Supply
+5 V Regulator
-15 V Regulator
MOS Regulator

(H960-D)
(H7420 or H742)
(H7420 or H742)
(H7420 or H7420

H754

+20, -5 V Regulator

(H742)

Mounting Panel

H933-D
H960-C
H960-D
H960-E
H961-A
KE11-A
KG11-A
KWI11-L
KWI11-P
LA30
LC11-A

LPI1I-F
LP11-J
LP11-R

LPS11

LS11
LT33
LVI11
M105

M783
M784
M785
M792
M795
M796
M920
M930
M1501
M1502
M1621
M1623
M1710

M1801

(H803 blocks)

Mounting Panel

(H808 blocks)

Cabinet
Cab (1 drawer)
Cab (2 drawers)
Cab w/o side pan
Ext. Arith. Elem.
Comm Arith Unit
Line Clock
Programmable Clock
DECwriter
LA30 Control

(HX WX D)
(inches)

Cab

Incl

Weight | Oper

Rel

Cur needed/(supplied)

Power

(amps)

(W)

700

(Ibs)

Temp

Humid

+5V l 115 Vac / Other

0-50

20-95

(22)

(°C)

(%)

(295)
(29)

1 8

(10A)@-15V
1.5 A @230 Vac
(JA)@+]5V

Dis

PROGRAMMING

Ist Reg

Address

Int

Vector

Level

UNIBUS

NPR

Bus

Loads

H312-A
H720

H722
H742

H7420
H744
H745
H746

(I10A)@-1SV
(1.6 A)@23.2V
Jo6A)@-3V

H754

(8A)@+20V
(lA)@-5V

H933-C
H933-D

SU
FS
FS
FS
FS
SU
SPC
MOD
SPC
FS
SPC

72X 21 X 30
72X 21 X 30
72X 21 X 30
72X 21 X 30

X
X
X
X

120
300
470
120

8
(75)
(150) |16

single ht

110

15-35

20-80

Printer (80 col)
Printer (132 col)
Ptr (heavy duty)

SPC + FS
SPC + FS
SPC + FS

46 X 24 X 22
46 X 48 X 25
48 X 49 X 36

200
575
800

1043
10--43
1043

15-80
15-80
15-80

Line Printer
Teletype
Electrostatic Ptr
Adrs Select Module

SPC + TT
FS
SPC + FS
MOD

12 X 28 X 20
34 X 22X 19
38X 19 X 18
single ht

155
60
160

5-38
15-35
10-43

PAN

Model

Number

(3.3A)@19.7V

31 X 21 X 24

Lab Periph System

POWER

ENVIRONMENTAL

MECHANICAL

(BAl11)
(PC11-A)
(H960-D)

H7420
H744
H745
H746

H933-C

Size

5—-43

single ht
single ht
single ht

20—80

5-90
20-80
20-80
:

4
1.5
0.8
l

1.5
1.5
1.5
1.5

1.5

1.5
0.34
0.2
0.2
0.3
0.23

(20 A)@-15V
(40 A)@-15V

900
1800

300

2
4
17

250
500
2000

3
2
5

300
200
600

300

777 300
770 700
777 546
772 540

100
104

6
6

1
1
1
1

777 560
777514
777514
777514

060,064
200
200
200

4
4
4
4

1
1
1
1

777514

200

777514

200

float

4—6

opt

2
1

H960-C
H960-D
H960-E
H961-A
KE11-A
KG11-A
KWI11-L
KWI11-P
LA30
LCI1-A

LP11-F
LP11-J
LP11-R

LPS11-S

LS11
LT33
LV1I
M105
M783
M784
M785

MOD
MOD
MOD
SPC
MOD
MOD
MOD
MOD
MOD
MOD
MOD

double ht
single ht
double ht
quad ht

0-70
0-70
0—70

10-95
10-95
10-95

1.25
0.3
0.75
0.78

M792
M795
M796
M920
M930
M1501
M1502
M1621

Instrument Reinote

MOD

quad ht

0-70

10-95

1.6

M1623

Unibus Interface

MOD &

quad ht

0-70

10-95

0.79

Foundation

SPC

quad ht

0-70

10—-95

1.46

Bus Transmitter
Bus Receiver
Bus Transceiver
Diode ROM
Word Count
Bus Control
Bus Jumper
Bus Terminator
Bus Input Interface
Bus Output Interface
DVM Data Input
Interface

Control Interface

16-Bit Relay Output

MOD

773 000

opt

M1710

M1801

Interface

C-5

Model

Description

Mounting

Size

Code

(HX WX D)

Number

MECHANICAL

Weight

Oper

Rel

Incl

(Ibs)

Temp

Humid

(°C)

(%)

(inches)
M7820

Interrupt Control

MOD

single ht

M7821

Interrupt Control

MOD

single ht

M9301(-YA),

Bootstrap Terminator

Unibus Slot

Double Ht

MEIl1-L

Core Memory (8K)

PAN

5Y%

MFI11-L

Core Memory (8K)

MF11-LP
MF11-U

Parity Memory (8K)
Core Memory (16K)

MF11-UP

Parity Memory (16K) | 2SU

ENVIRONMENTAL

Cab

+SV I

(amps)

0-50

10—-90

2 SU
2 SU

3.4

0--50 | 10-90
0-50
0-90

4.9
4.5

0—50

MMI1-LP

Parity Memory (8K)

(ME11-LP)

Address

Vector

Level

NPR

Bus

Model

Loads

Number

(W)

M9301(-YA),

0-90

125

6A@-15V

125

6A@-15V
35A@20V

125
120

MFI11-L

2
1

MF11-LP
MF11-U

120

MF11-UP

MEI11-L

05A@=-5V

34A@20V
0SA@-5V

0-50

10-90

0-50 | 10-90

1.7

0OSA@-15V

1.7

0.5A@=-15V

4.5

125

MMI11-L

MM11-LP

05A@20V

MMI11-U

05SA@=5V

Parity Memory (16K) | (MF11-UP)

0--50

0-90

4.5

0.5 A @20V

MM11-UP

0SA@=5V

MRI11-DB

Bootstrap

2 SPC

MS11

Semiconductor Mem

(11/45)

PC11

Paper Tape

SPC + PAN

10%

Programmable Data

5% X 19X 23

PDM70

Dis

UNIBUS

‘

MM11-UP

(-YB). (-YD)

2SU

(MF11-L)

Int

M7821

10—90

Core Memory (8K)

Ist Reg

2
0-50

MMI11-L

115 Vac / Other

PROGRAMMING

Power

M7820

(-YB), (-YD)

MMI1-U

POWER

Cur needed/(supplied)

0.6

0-50

10-80

13-38

20-95

0-40

10-95

Mover

1.5

2
3

350

115 Vac

250

230 Vac

250

772 100

114

777 550

070,074

MR11-DB

MS11

PCl1i

PDM70

PRI11

Paper Tape (rdr)

SPC + PAN

10%

13-38

RCI11-A

20-95

Disk & Control

PAN

350

10%

777 550

070

115

2080

PR11

RF11-A

17-50

Disk & Control

2.2

PAN + PAN

250

16+ 16

777 440

210

500

17-33

RC11-A

RKOS

20-55

Disk Drive

6.5

PAN

750

10%

777 460

204

110

15-43

RK11-D

20—80

Disk & Control

SU + PAN

160

10%

250

RPO3

15-43

Disk Drive

20-80

40 X 30X 24

415

15-33

10--80

X
X

1.5

7.5

200

6 A @230 Vac

1300

6 A @230 Vac

2100

RF11-A
RK0S

777 400

220

RK11-D

RPO3

RP11-C

Disk & Control

CAB + FS

740

15-33

10-80

RS11

Disk Drive

PAN

100

RS64

17-33

2055

Disk

PAN

10%

200

17-50

20--80

RS11

Numeric Data Entry

6.5X 125X 15

0—40

10--90

2.2

250

RS64

RTO!

Terminal
RTO2

Alphanumeric Data

0.25 @ 115 Vac

63X 144X 16

0—-40

10-90

"10-40 | 20-80

1.5

254

RP11-C

RTO1

110 Vac

RTO2

220 Vac

0.12

Entry Terminal

776 710

@ 220 Vac

TAIll

Cassette

SPC + PAN

TC11-G

DECtape & Control

PAN + PAN

10%2 + 10%

250

15--27

40-60

120

777 500

260

TTMMI11

Magtape & Control

870

PAN + PAN

26 + 10%

500

15-27

40-60

TU10

Magtape Transport

1000

777 340

214

TC11-G

772 520

224

TM11

PAN

450

15-27

40-60

TUS6

DECtape Transport

1000

PAN

10%

- 15-27

TUI10

UDCI11

1/O Subsystem

40—-60

CAB

350

VROl

5-50

Display

10-90

PAN

TUS6

10%

1700

10-50

10-90

VR14

Display

120

PAN

10%

10-50

VROl

VTOl

Display

10--90

12X 12X 23

400

VTO05

0-50

Alphanum Terminal

10—80

2.2

VR14

12X 19X 30

250

10-43

8—90

VTOl

130

VTO5

771 774

234

4,6

C-7

TAll

UDCI11

PDP-11/34 SYSTEM USER’S MANUAL

Reader’s

EK-11034-UG-001

Comments

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