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February 1975

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Document:	PDP-11/05,11/10 Computer Manual
Order Number:	EK-11005-TM
Revision:	003
Pages:	248
Original Filename:

OCR Text

PDP-11/05,11/10

computer manual

EK-11005-TM-003

PDP-11/05,11/10

computer manual

digital equipment corporation - maynard. massachusetts

1st Edition, February 1973
2nd Printing, September 1973

3rd Printing, July 1974
4th Printing, September 1974

2nd Edition, April 1975

The material in this manual is for informational
purposes and is subject to change without notice.

Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

CONTENTS
Page

PART 1 — COMPUTER DESCRIPTION
CHAPTER 1
1.1

INTRODUCTION

1-1

1.2

COMPUTER COMPONENTS

. . . . . . . . . ... it

1-1

1.2.1

KDII-BProcessor

122

Core Memory

. . . . . .

e s e e e e

. . . . . o o v v v v vttt

. . . . . . .

. . . . . . . .. ...

1.2.2.2

Memory Specification

. . . . .. ..

124

Backplane

e e

1-1
1-1

Memory Organization
Power Supply

1.2.2.1

1.2.3

prerey

COMPUTER COMPONENTS

Lo o

1-2

oL oo

1-2

. . . . . . ..

1-2

. . . . . ...

. . . . . . .. . ... ... .

ME11-L CORE MEMORY SYSTEM

...

1-5

1.4

EXTENSION MOUNTING BOX

. . . . . . . . . e

1-5

CHAPTER 2

UNIBUS

2.1

INTRODUCTION

2.2

UNIBUS STRUCTURE

. . . . . e
e
. . . . . . . ... et

2-1
2-1

2.2.1

Bidirectional Lines

. . . . . . . . .. L.

2-1

22.2

Master/Slave Relationship

2.2.3

Interlocked Communication

. . . . . . . .. ..

1-2

1.3

.. ... ..

2-1

L Lo

2-2

. . . . . . .. ...

2.3

PERIPHERAL DEVICE ORGANIZATION ANDCONTROL

. . .. ... ... ......

2.4

UNIBUS CONTROL ARBITRATION
. . . . .. .. ... ... ... .. ... ......
Priority Transfer Requests
. . . . . .. .. . . ... ... .. ...

2-2
2-2

24.1
242

Processor Interrupts

243

Data Transfers

CHAPTER 3

. . . . . . . . ... e

2-3

. . . . . . . . . . . L L

2-3

UNPACKING AND INSTALLATION

3.1

INTRODUCTION

UNPACKING
. . . .
MECHANICAL DESCRIPTION
. . . . . . . . . . .

34.1

. . . . . o e
e
e
. e

3-1
3-1

INSTALLATION
. . . . .
e e
e
Mounting Computer on Installed Slides
. . . . ... ... .. .. ... .......

36
3-6

34.2

Securing Computer to Cabinet Rack

3.4.3

Installation of [fJOCables

3.5
3.6

3.7
3.7.1
3.7.2

3-1

. . . . . .. .. ... ..............

3-6

. . . . . . . . . . . e

3-6

INTERCHANGEABLE PERIPHERAL SLOTS
. . . . . .. .. ... .. .........
SIDE AND TOP COVER INSTALLATION
. . . . . ... .. . .. .. .. .. .....

3-7

ACPOWER SUPPLY CONNECTION
. . . . ... ... ... ... ... . ........
Connecting to Voltages Other than 115V
. . . . . . ... ... .. ... ... ...

3-7
3.7

Quality of ACPowerSource

. . . . . . ...

. ... Lo

CABINETPOWER CONTROL

3.7

3.9

INSTALLATION CERTIFICATION . . . . . ... ... ... ... ... .. .. .....
WARRANTY SERVICE (DOMESTICONLY) . . . .. ... ... ... ... ... ....

3-8
39

iii

3.8
3.10

. . . . . . . . .

CONTENTS (Cont)

CHAPTER 4

COMPUTER OPERATION

4.1

INTRODUCTION

4.2

POWER SWITCH OPERATION

4.3

FUNCTION SWITCHES

4.4

ADDRESS/DATA SWITCHES

4.5

CONSOLE INDICATORS

4.6

CONSOLE OPERATION

4.6.1

Load Address Switch

4.6.2

Examine Switch

4.6.3

Deposit Switch

. . .

4.6.4

ENABLE/HALT Switch

4.6.5

START Switch

4.6.6

. ..

. ...

. ..

Continue Switch

4.7

UNCONDITIONAL COMPUTER AND UNIBUS INITIALIZATION

4.8

LOADING PROGRAMS FROM PAPER TAPE

4.8.1

The Bootstrap Loader

4.8.1.1

Loading the Loader Into Memory

48.1.2

Loading Bootstrap Tapes

48.13
482
4.8.2.1
4822
4.8.3

Bootstrap Loader Operation
The Absolute Loader
Loading the Loader Into Memory
Loading Absolute Tapes
Memory Dumps

4.8.3.1

Operating Procedures

4.83.2

Output Formats

4833

Storage Maps

PART 2 - KD!1-B PROCESSOR
CHAPTER 5

PROCESSOR GENERAL DESCRIPTION

5.1

KD11-B DEFINITION

5.2

KD11-B AND THE UNIBUS

KD11-B AS AN INSTRUCTION INTERPRETER

MEDIUM AND LARGE SCALE INTEGRATED CIRCUIT REPRESENTATIONS

54.1

Microprogram Documentation

542

Read-Only Memory (ROM) Maps

CHAPTER 6

. .

. . . . . .

... .

INSTRUCTION SET

6.1

INTRODUCTION

6.2

ADDRESSING MODES

6.2.1

Introduction

6.2.2

Instruction Timing

6.3

PDP-11/05 INSTRUCTIONS

6.4

INSTRUCTION SET DIFFERENCES

CHAPTER 7

CONSOLE DESCRIPTION (Sece the KD11-B Processor Maintenance Manual)

CHAPTER 8

KD11-B DETAILED DESCRIPTION (Sce the KD11-B Processor Maintenance Manual)

. . .

. .

. . .

. .. ..

CONTENTS (Cont)
e

Page

CHAPTER 9

MICROPROGRAM CONTROL (See the KD11-B Processor Maintenance Manual)

CHAPTER 10

KD11-B AND CONSOLE MAINTENANCE (See the KD11-B Processor Maintenance Manual)

PART 3 — MM11-K AND MM11-L MEMORIES
CHAPTER 11

MMI11-K AND L GENERAL DESCRIPTION

11.1

INTRODUCTION

11.2

GENERAL DESCRIPTION

. . . . ..

11-1

. . . . . . .. . .

11-1

. . . . . . . ... L

11-1

. . . . . ...

11-1

11.2.1

Physical Description

11.222

Specifications

11.2.3

Functional Description

. . . . . . . .. ...

Lo L

11-4

11.2.3.1

G110 ControtModule

. . . . .. .. ... L

11-4

11.23.2

G231 DriverModule

. . . . .. Lo

11-6

11.2.3.3

H213 orH214 Stack Module

11.24

Basic Memory Operations

. . . . . . ... ... .. ..

... ...

11-6

. . . . . . ... .. Lo

11-7

. . . . . . . . . .. .

11-7

11.24.1

nata In(DATD Cycle

11.2.4.2

Data In, Pause (DATIP)Cycle

11.2.4.3

Data Out (DATO)Cycle

11244

Data Out, Byte (DATOB)Cycle

CHAPTER 12

...

. . . . . ... ... .. ... .. .. ......

. . . . . . . . ..

. .

11-7
11-7

. . . . . .. ... ... ... ... . .....

11-7

MM11-K AND L DETAILED DESCRIPTION

12.1

INTRODUCTION

12.2

CORE ARRAY

12.3

MEMORY OPERATION

12.4

DEVICE AND WORD SELECTION

12-1

. . . . e

. . . . . .

e e e

12-1

. . . . . . . . . . .
. . . . .. ..

12-1

...

.. ....

12-4

. . . . . .. . ... ... ... ..

12-6

12.4.1

Memory Organization and Addressing Conventions

12.4.2

Device Selector

. . . . . . ..

12.4.3

Word Selection

. . . . .

.. . ... ...

L L

.. L

12-8
12-11

124.3.1

Word Address Register and Gating Logic

12432

X-and Y-Line Decoding

12433

Drivers and Switches

12434

Word Address Decoding and Selection Sequence

. . . . ... ... ... ...

12-17

READ/WRITE CURRENT GENERATION AND SENSING

. . . . . ... ... .....

12-19

. . . . . . . . . ... ... ...

12-19

12.5
12.5.1

Read/Write Operations

12.5.2

X-and Y-Current Generators

1253

Inhibit Driver

. . . . . .. .. .. ... ......

12-12

. . . . . .. .. ... Lo

12-13

. . . . . . .. ...

Lo oo

12-15

. . . . . . . . . . .. ..o

12-21

. .

12-22

. . . . ...

12-23

. .

. . .

1254

Sense Amplifier

12.5.5

Memory Data Register

12.6

STACK DISCHARGE CIRCUIT

12.7

DCLOCIRCUIT

12.8

OPERATING MODE SELECTION LOGIC

12.9

CONTROL LOGIC

. .

. . . . . .

. . .

. . .. .

. . . . . . ..

. . e

12-24

12-26

. . . . . .. .. ... ... ... ......

12-26

. . . . . . .
e e e

12-27

129.1

Timing Circuit

129.2

Slave Synchronization (SSYN) Circuit

1293

Pause/Write Restart Circuit

1294

Strobe Generating Circuit

. . . . . . . ...

1295

Data In (DATI) Operation

. . . . . . . . .. . ..

. . .

. . . . . ... Lo

. . . . . . . .. . ... ... ...

. . . . . . . . . . .. . .. ..
L. oL

. o

12-28

12-33
12-34
12-36

12-38

CONTENTS (Cont)
Page

12.9.6

Data In Pause (DATIP) Operation

129.7

Data Qut (DATO) Operation

12.9.8

Data Out Byte (DATOB) Operation

CHAPTER 13

. . . . . . . . .. ...

. . . . . . . . . . ..

INTRODUCTION

13.2

PREVENTIVE MAINTENANCE

. . . . . . . . .. ... ...

. . . . .

. . . . . . .. . . .

13.2.1

Initial Procedures

13.2.2

Checking Output of Current Generators

13.3.1
133.2
13.4

13.4.1

. oo
i i it

1240

... ....

12-40

MEMORY MAINTENANCE

13.1

13.3

. . .

. . . .

CORRECTIVE MAINTENANCE

L oL e
.

. . . . . . ... ... ... ......

13-1
132
13-2

Strobe Delay Check and Adjustment

. . . .

13-2

Corrective Maintenance Aids

oL Lo

13-2

. .

. . . . .

. .

13-1
13-1

. . . . . e

PROGRAMMING TESTS

e e

. .

. . . .. . ...

. .

. o o

..o

o e

Address Test Up (MAINDEC-11-DIAA)Y

. .

. . . ... ..

13-6

...

13-6

. . . . . .. . ... . ... ........

13-6

134.2

Address Test Down (MAINDEC-11-DIBA)

1343

No Dual Address Test (MAINDEC-11-DICA)

1344

Basic Memory Patterns Test (MAINDEC-11-DIDA)

1345

Worst-Case Noise Test (MAINDEC-11-DIGA)

. . . . . . .. .. .. ... ... ...
. . . ...

13-6

. ... ... . .... 13-6

. . . . . . . . ... ... ... ....

13-7

PART 4 — POWER SUPPLY
CHAPTER 14

POWER SUPPLY GENERAL DESCRIPTION

14.1

INTRODUCTION

14.2

PHYSICAL DESCRIPTION

. . . .

. . . . . . . .

14.2.1

Power Control Unit

14.2.2

Power Chassis Assembly

. . . . .

14-1
14-1

14-2

14.2.5

ACCable

. . . .

14.3

SPECIFICATIONS

CHAPTER 15

POWER SUPPLY DETAILED DESCRIPTION

15.1

INTRODUCTION

15.2

ACINPUT CIRCUIT

153

DC REGULATOR MODULE OPERATION

e e

. . . . . . . ..o

14-3

14-5

. . e

14-5

14-6

. .

.
.

e
. . . . . . . .

15.3.1

Generationof * Raw DC

. . .

LTCL Circuit

1533

BUSACLOLand BUSDC LO LCircuits

15.3.4

+15 V Regulator Circuit

1535

+5 V Regulator Circuit

15.3.6

-15 V Regulator Circuit

. . . e
e
e 15-1

. . . . . . o

1532

. .

15-1

... ...

15-1

. . . . . . .

15-5

15-7

. . . oL

15-7

. . . . . . . ..o

159

. . .

INTRODUCTION

16.2

ADJUSTMENTS

. .

. . . . .. . ...
.

. . . . .

15-6
15-6

16.1

16-1

e
e 16-1

16.3

CIRCUIT WAVEFORMS

. .

16.4

TROUBLESHOOTING

. . . . .

Troubleshooting Rules

POWER SUPPLY MAINTENANCE

. . .

... ...

...

o e

CHAPTER 16

16.4.1

14-1

. . .

. .

. . .

DCCable

c e
e

. e

DC Regulator Module

. .

. ..

1423

. .

14.2.4

. .

. . . . . .

. .. .0

16-1

16-4

e e

CONTENTS (Cont)

16.4.2
16.4.3

16.5

Troubleshooting Hints
Troubleshooting Chart

PARTS IDENTIFICATION

PART 5 — 10-1/2 INCH MOUNTING BOX AND POWER SYSTEM
CHAPTER 17

MOUNTING BOX

17.1

INTRODUCTION

17.2

OVERALL MECHANICAL DESCRIPTION
BACKPLANE

POWER SYSTEM

CHAPTER 18

10-1/2 INCH MOUNTING BOX UNPACKING AND INSTALLATION

18.1

INTRODUCTION

18.2

UNPACKING

18.3

INSTALLATIONIN ACABINET

184

INSTALLATION OF OPTIONS AND CABLES

. . . . . . . . . .

Installing Options on Site

184.2

Connecting the Serial Communications Device to the Processor

18.4.3

Console Cable

18.4.4

Unibus Cable/Jumper

18.6

. . . . . . . . . . . .

Quality of AC Power Source

Introduction

18.7

INSTALLATION CERTIFICATION

18.8

WARRANTY SERVICE (DOMESTIC ONLY)

CHAPTER 19

POWER SYSTEM

19.1

INTRODUCTION

19.2

MECHANICAL DESCRIPTION

19.2.1.2
19.2.3

Power Supply
DC Regulator
+5 V Regulator
Line Set
Wiring Harnesses

19.3

SYSTEM FUNCTIONAL DESCRIPTION

19.4

SYSTEM CIRCUIT DESCRIPTION

194.1

CABINET POWER CONTROL

Typical Multi-Cabinet Installation

19.2.2

Connecting to Voltages Other than 115V

18.6.2

19.2.1

e e

AC POWER SUPPLY CONNECTION

18.6.1

19.2.1.1

i ie

184.1

18.5.2

17.3

18.5.1

174

185

arr—.

. . . . ..

Introduction

1942

Line Set

19.4.3

Power Distribution Board

. . . . . .

194.4

DC Regulator (PS1)

19.44.1

Functional Operation

19442

Generation of Raw DC Voltages

19.4.4.3

LTC L Circuit

19444

BUS AC LO L and BUS DC LO L Circuits

vii

e e

CONTENTS (Cont)
Page

19.4.4.5

+15 V Regulator Circuit

19446

+5 V Regulator Circuit

. .

19447

-15 V Regulator Circuit

19.4.5

+5V Regulator (PS2)

. . . . . ..

19-24

19-25

... .. ...

19-26

. . . . . ...

19-26

. . . . . ... ...

19.4.5.1

Functional Operation

19.4.5.2

Generationof RawDC Voltage

19.4.5.3

Regulator Circuit

19454

19.45.5
19.5

...

. . .. .. ... ... ...

. . . . .. ... ... ... .. ............

. . . . . .

. . . . ... ... ... ...........

19-29

Overcurrent Protection Circuit

. . . . . .. . ... ... ... ... .....

19-31

Overvoltage Crowbar Circuit

. . . . . . ... ... ... ... ........

19-31

POWER SUPPLY MAINTENANCE

19.5.1

Introduction

. . . ... ...

19-26

. . . . .. ... ... ... ... ... .. .. ...

19-31

. . . . .. L

19-31

19.5.2

Checking and Adjusting Voltages

19.5.3

Power Supply Removal

19.54

Troubleshooting Procedures

. . . . . ... ... ... ... .........

. . . . . . ... ... ... ...

19.37

. .. ... L

19-37

19.54.1

Introduction

Troubleshooting Hints

19.54.3

Troubleshooting the 5409728 Regulator

19.54.4

Troubleshooting the H744 Regulator

19-33

. . . . . . . . .. ... ... ... ...

19.5.4.2

. .

19-31

. . . . ... ... ... .. .. ... ... .. ...

APPENDIX A

INTEGRATED CIRCUIT DESCRIPTIONS

APPENDIX B

COMPUTER CONNECTORS

19-37

. . . . . . . .. ... ... .....

19-37

. . . . . . . . . ... . ... ... ..

19-39

ILLUSTRATIONS

Figure No.

Title

Page

I-1

Module Utilization Diagram for Configuration 1 (16K)

... ... . ... ..

1-3

1-2

Module Utilization Diagram for Configuration 2(8K)

. . . . .. ... .. ... .. ... ..

1-3

Computer Backplane Connector and Pin Designations

. . . . . ... ... ... ......

Module Contact Designations

. . . . ... ...,

1-5

Computer Packaging

3-2

Computer Mounting Box

. . . . . .

. . . .

. ..

. . . . . . . ... ..
. . .

. . . . ...

3.3

Computer Box With Top Cover Removed

Computer Box With Top and Side Covers Removed

Computer Chassis

3-6

Mounting Box Without Modules

. . . .

. . . . . .. ... .. ... ... ........
. . . . . . .. ... ... .......

. . . . . . L
. .

. . . . ..

. ... ...

34
34
35

... .. ... ... ... .......

3-5

Rear of Computer With Cable Strain Reliefs

3-8

Typical Cabinet Power Control System Wiring Diagram

4-1

Console Itlustrating Switch Movements

. . .

3-3

.. ... .. ...

3-7

32
3-3

. . . . . . ... . ... ... ...

3-8

. . . . . . . .. ... ... ... .........

4-1

4-2

Loading and Verifying the Bootstrap Loader

4.3

Loading Bootstrap Tapes IntoMemory

4-4

Absolute Format

. . . . . . . ... ... ... .......

. . . . . .. ... ..

... .. ... ... ..

4-8
49

. . . . . . . ... L 4-13

Bootstrap Format

5-1

KD11-B With Interconnections to Memory and Peripherals

. . . .

. .. ... L. ... 414
. . . . ... ... ... . ...
52

5-2

KD11-B Processor Block Diagram

5.3

Instruction Interpreter Block Diagram

ALU, MSI Circuit Type 74181 Representation

. . . . . . ... ... ... ... ... .........
. . . . . . . .. ... ... ... ..........

viii

. .

. . .

. ..

...

.. .. ...

.....

52
5-3
5-3

ILLUSTRATIONS (Cont)

Title

Figure No.

5-5

EO68 ROMMapExample

6-1

Addressing Mode Instruction Formats

6-2

PDP-11 Instruction Formats

Page

. . ... . ... ... ... ... ... ...,
. . . . . . .. ..

...

54
6-2

. . . . . . . . . . . .. .. .. ... ... ... . ... 6-18

11-1

Component Side of G110 Control Module

. . . . . ... ...

11-2

Component Side of G231 DriverModule

. . . . .. ... . ... .. ...

11-3

Component Side of 8K H214 Stack Module

114

MM11-K,

LMemory Block Diagram

...

... ..., 11-2

. . . . . . . ... ... ...

o000, 11-2

... .....

. . . . . . ... ... ... .. .. ...

12-1

Three-Wire Memory Configuration

12-2

Hysteresis LoopforCore

123

Three-Wire 3D Memory, Four Mats Shown for a 16-Word 4-Bit Memory

124

Device and Word Address Selection Logic, Block Diagram

12-5

Memory Organization for8K Words

12-6

Address Assignments For Three Banks of 8K Words Each

12-7

Jumper Configuration For A Specific Memory Address

12-8

Device DecodingGuide

129

Type 8251 Decoder, Pin Designationand Truth Table

. . . . ... ... . ... ... ..

12-13

12-10

Decoding of Read/Write Switches and Drivers Y4-Y7

. . . . . . . ... ... ... ...

12-14

12-11

Switch or Driver Base Drive Circuit

12-12

Y-Line Selection Stack Diode Matrix

12-13

Typical Y-Line Read;Write Switchesand Drivers

12-14

Interconnection of Unibus, Data Register, Sense Amplifier,
and Inhibit Driver

. . . . .. ... ... ... ...

11-3

..., 11-5

. . . . . . . .. .. ...

12-3
. . . . ... ... 12-5

. . . . . ... ... ... .... 12-6

. . . . . . . . . .. ...

. . . . . . . . . .

... .. ...... 12-2

. . . . . ... ... ... ....

12-7
12-8

. . . . ... ... ........

12-10

. e

12-10

. . . . . . .. . .. ... ... ...

...

12-15

... .. ...

12-16

. . . . . . . .. .. .. ... ... ..

12-17

. . ... ... ... ...

. . . . . . . . . .

...

12-20

. . . . . . ... .. ... ... ..

12-21

12-15

Y-Current Generator and Reference Voltage Supply

12-16

Sense Amplifier and Inhibit Driver

12-17

Type 7528 Dual Sense Amplifiers With Preamplifier Test Points

12-18

Stack Discharge Circuit

12-19

DC LO Circuit, Schematic Diagram

12-20

Basic Timing and Control Signal Functions

12-21

TWID

12-22

Generationof MSELRESET L

12-23

Slave Sync (SSYN) Circuit

12-24

Pause/Write Restart Circuit

12-25

Strobe Generating Circuit and Timing Diagram for STROBEH

12-26

Flow Chart For Memory Operation

13-1

Strobe Pulse Waveform

. . . . . . . . . ... L

13-2

Troubleshooting Chart

. . . . . . . ... . ... ... 133

13-3

MM11-K Sense/Inhibit Waveforms . . . . . . . . . . .. ..
Drive Waveforms . . . . . . . . . . .
e
e
e
e
e
Power Chassis Assembly (with DC RegulatorModule) . . . . . ... ... ... ......
Power Supply Assembly (with DC Regulator Module Removed) . . . .. ... ... .. ..

134

14-1

14-2

. . . . . . . ... ... ...

12-23

. . . . . . . .. ... ..

1224

. . . . . . . . . . . . . L

12-25

Hand TNARH Control Logic

. . . . . . .. ... ... ... ... ... .....

12-26

. . . . . .. .. ... ... .........

12-29

. . . . . ... .. ... ... ... . .......

12-31

. . . . . . . .

. .

. i

12-32

. . . . . . . . . . . . e

12-35

. . . . . . . . . . . . .«

12-36

. . . . ... ... .. ..

12-37

. . . . . . .. . .. ... ... ... ........

12-39

e 13-2

134
13-5
14-2
14-3

14-3

DC Regulator Module (Top View)

14-4

DC Regulator Module (Bottom View In MountingBox) . . . ... ... ... ... .... 144
Detailed AC Interconnection Diagram . . . . . . . ... ... ... .. ..
.. 15-2

15-1

. . . . .. .. .. .. .. .. ... .. ..., 14-4

15-2

115 V Connections — Simplified Schematic Diagram

15-3

230 V Connection Diagram

154

Regulator Module Block Diagram

15-5

Rectifierand LTC L Circuits . . . . . . . . . . 0 .t it i it it
et
e
e e 15-5
BUSACLOand BUSDC LOCircuits
. . . . . . . . . .. ..o
oL 15-6
+15 V Regulator Circuit
. . . . . . .e
e e e e e
e e 15-7

15-6
15-7

. . . . . ... ... .. ... . ... 15-3

. . . . . . . . . ...

e
e
e e e
e 15-3
. . . . . .. ... ... ... ... .. ..., 15-4

ILLUSTRATIONS (Cont)

Title

Figure No.

15-8

+5 V Regulator Circuit

159

=15V Regulator Circuit

16-1

+5 V Regulator Circuit Waveforms

16-2

- 15 V Regulator Circuit Waveforms

17-1

PDP-11/05 NC Computer Mounted InCabinet

17-2

PDP-11/05 NC Computer Extended and Locked In Front

Down 90° POSItion

Page
oL

. . . . . . .. ..
.

L e

. . . . . . . . .. ... . L

16-3

. . . . .. ... ... . ... ........

. . . . . . . . .

e e

PDP-11/05 NC Computer Extended and Locked in Front

17-4

PDP-11/05 NC Computer, Rear View

17-5

Connector Side of Backplane
Pin Side of Backplane

e e e

177

Computer Backplane Connector and Pin Designations

17-8

Module Contact Designations

179

Module Utilization Diagram

18-1

Computer Packaging

. . . . . ... ...

18-2

SCL Cable 70-08360

. . . . . . . . . . .

18-3

Connector Specifications for Line Set

18-4

Typical Cabinet Power Control System Wiring Diagram

. . . . . . . . . ...

. . . . . .. ...

17-2

e e e 17-3

e e

174

. . . . . . . . . .. .. ... ...

17-6

... 17-5

L oL

17-6
17-6

. . . . . . .. ... ... ... ...

17-7

. . . . . . . . . ... Lo

17-8

. . . . . . . . . ...

...

L e

. . . . . . . . ... .. ... ..

Interconnection of Power Controllers in Multi Cabinet Installation

19-1

Power Supply Side View

19-2

Power Supply Frontand Rear Views

19-3

DC Regulator, Top View

. . .

. . . . ... ... ..

. .. .

.
...

18-9
18-10

18-11

19-3
19-4

19-4

DC Regulator, Bottom View

19-5

+5 V Regulator, Side View

19-6

+5 V Regulator, 3/4 Bottom View

. . . . . . . .

.. e

19-13

19-7

BCOST Line Set, Cover Removed

. . . . . . . ..

... ... ... ...

19-14

. . . . . . .

18-5

19-2

. . . ... .. .. ... ... ... ... ...,

. . . . . . . . ..
.

. . . . . ... ... ... ... 0oL

. . . . . .. ..o

179
18-2

18-5

159
16-2

i e

15-8

17-3

Up90° POSIION .« . . . o o v e

... oL oL

19-8

BCOST Line Set, Rear View

199

Power System Functional Block Diagram

19-10

Power System Interconnection Diagram

19-11

Power Applications Using 115V LineSet

. . . . . ... . ... ... ... ...

19-12

Power Application Using 230 V Line Set

. . . . . . ... ... ...

19-13

Power Distribution Board Circuit Schematic

19-14

DC Regulator Block Diagram

19-15

Rectifierand LTC Circuits

19-16

BUSACLO and BUSDC LO Circuits

19-17

+15 V Regulator Circuit

19-18

+5 V Regulator Circuit

19-19

=15V Regulator Circuit

. . . . . .

. .

. . . . . .

. . ..

. .

. . . ..

19-14

0L,

19-16

.. ... ..o L.

. . . . . ..

19-18

oL,

19-18

.. ... ... ... ... ...

19-19

0 Lo

19-21

o e

19-23

. . . . . . . o

19-24
19-25

. . . . . . . ..

19-17

...

. ... .. ...

. . . . . ..

. . .

. . . . . . . ... .. ...

. . . . . . .. ...
.

19-5
19-12

19-25

19-27

19-20

+5 V Regulator (PS2) Functional Block Diagram

. . . . . . ... .. ... .. .....

19-27

19-21

+5 V Regulator (PS2) Circuit Schematic

. . ..

19-28

. .

. . .

...

... ... ........

19-22

Voltage Regulator (E1) Equivalent Circuit and Package Configuration

19-23

Simplified 5 V Switching Regulator Schematic and Waveforms

19-24

Power Supply Adjustments

19-25

Disconnecting Line Set From PowerSupply

19-26

Removing Power Supply Mounting Screws

19-27

Removing Power Distribution Harness Connectors H2-P2 and H2P3

. . . . . . .

19-28

Lifting Power Supply From MountingBox

...

19-29

Disconnecting DC Regulator Output Connector

. . . . ...

. ..

19-29

. . . . . . . ... .. ..

19-30

19-32

. . . . ... ... ..
. . .

. . . . . . ...

. . . . . ..

.. ... ... ..

... ... ... ..

. . . . . .. .. ...

. . ..

19-34
19-35
19-35

.. ...,

19-36

. . . . . . . . . . ... ... ......

19-36

ILLUSTRATIONS (Cont)
Figure No.
19-30
19-31

Title

+5 V Regulator Circuit Waveforms . . . . . . .. .. ... .. 0oL
. . . . . .. . ... . ... oL
-15 V Regulator Circuit Waveform

Page

1940
1941

TABLES

Table No.
4-1

4-2
4-3

6-1

6-2
6-3
6-4
6-5

6-6
6-7

6-8
11-1

12-1

12-2
12-3
124
12-5
14-1

14-2
14-3
16-1

18-1
18-2
183
19-1

19-2
19-3
194

Title

Page

. . . . . . ... ... .. ......... 4.3
Significance of ADDRESS/DATA Indicators
oo oo 4-6
Bootstrap Loader Instructions . . . . . . ... ...
. . . . . . .. ..o e 4-6
Memory Bank Assignments
. . . . ... 6-3
AddressingModes
e e 6-4
. . . . . . . .. Lol
Addressing Times
Single Operand Instructions . . . . . . . . ... ... .. 6-5
. . . . . ... ... ... 69
Double Operand Instructions
. . . . . . . . ... ..o o 6-12
Program Control Instructions
. . . . . . . .. .. .o L L L 6-17
Operate Group Instructions
Condition Code Operators . . . . . . . . . oo i it 6-18
6-19
e
e e e e e e e e e
. . .« v v v v v v i e e e
PDP-11 Differences
11-3
...
..
..
.
.
.
.
.
.
.
MM11K and L Memory Specifications
12-4
o
. . . . . . . ..
Addressing Functions
12-12
.......
.
...
..
...
...
.
.
.
.
.
.
Enabling Signais for Word Register Gating
. . . . . . . . ..o 12-18
Word Address Decoding Signals
. . . . . .« o o Lo 12-27
.
.
Selection of Bus Transactions
. . . . . . . ... ... .. ... 12-28
Signals
Generation of Memory Operating
. .. ... Lo 14-6
...
.
.
.
.
Power Supply Input Specifications
... ... ... 14-7
..
.
.
.
.
.
.
Power Supply Output Specifications
oL 14-10
. . . . .. .. .. ..o
.
.
.
Specifications
Mechanical and Environmental

Troubleshooting Chart . . . . . . . . .. ... 16-5
SCL Interface Pin and Signal Designations . . . . . . . . . .. ... ... 18-6
BCO8R-03 Console Cable Pin and Signal Designations . . . . . . . . .. . ... ... ... 18-7
. . . . . .. ... .. .. 18-8
Unibus BC11A Cable/M920 Jumper Pin and Signal Designations
. 19-6
..
..
..
.
.
.
.
.
.
.
.
Specifications
5409728
Regulator
DC
19-19
.
..
...
..
.
.
.
.
.
Signals
Board
Distribution
Power
Option Power Harnesses . . . . . . . . .. ..ot 19-20
. . . . . . ... ... ............ 19-38
5409728 Regulator Troubleshooting Chart

This manual describes the PDP-11/0S and PDP-11/10 Computers. The PDP-11/05 and PDP-11/10 are electrically
identical. The PDP-11/05 is specified for the Original Equipment Manufacturer (OEM) market and the PDP-11/10 is
specified for the end user market.

The PDP-11/05 is available in two versions: one provides a maximum of 8K words of core memory and the other
provides a maximum of 16K words of core memory. The PDP-11/10 is available only with a maximum of 8K words
of core memory.

This manual is divided into four parts.

—

Part 1

Computer Description

Part 2

KD1 1-B Processor

Part 3

MMI11-K, MM11-L Memories

Part 4

Power Supply

Chapter outlines of each part are shown below.
Part 1

Part 2

COMPUTER DESCRIPTION

Chapter 1

Computer Components

Chapter 2

Unibus

Chapter 3

Unpacking and Installation

Chapter 4

Operation

KD11-B PROCESSOR

Chapter 5

Part 3

Processor General Description

Chapter 6

Instruction Set

Chapter 7*

Console Description

Chapter 8*

KD11-B Detailed Description

Chapter 9*

Microprogram Control

Chapter 10*

KD11-B and Console Maintenance

MMI11K and MM11-L MEMORIES

Chapter 11

MM11K and L General Description

Chapter 12

MM11-K and L Detailed Description

Chapter 13

Memory Maintenance

—

*Chapters 7, 8, 9, and 10 have been deleted. Current information is available in the KD11-B Processor Maintenance Manual.

Part4

POWER SUPPLY
Chapter 14

Part 5

Power Supply General Description

Chapter 15

Power Supply Detailed Description

Chapter 16

Power Supply Maintenance

10-1/2 INCH MOUNTING BOX AND POWER SUPPLY
Chapter 17

Mounting Box

Chapter 18

Unpacking and Installation

Chapter 19

Power System

A bound volume of engineering drawings is supplied with each computer.
The following related documents are valuable as references.

PDP-11/05, 11/10 Processor Handbook
PDP-11 Peripherals Handbook

PDP-11 Paper-Tape Software Programming Handbook

(Document No. DEC-11-GGPB-D)

PART 1

COMPUTER DESCRIPTION

Part 1 provides a general physical description of the PDP-11/05 and PDP-11/10
computers.

Unibus

operation is discussed prior to the discussions of computer

installation and operation. The chapters of Part 1 are:
Chapter 1 — Computer Components
Chapter 2 — Unibus

Chapter 3 — Unpacking and Installation
Chapter 4 — Operation

CHAPTER 1

COMPUTER COMPONENTS

1.1

INTRODUCTION

This chapter briefly describes the major components of the PDP-11/05, 11/10 Computer. It includes module
utilization diagrams for both computer configurations and a backplane connector and pin designation diagram.
1.2

COMPUTER COMPONENTS

The computer consists of a mounting box, console, processor, core memory, prewired backplane, power supply,
fans, and interconnecting cables. The processor is contained on two modules, and each 4K or 8K memory is
contained on three modules.

1.2.1

KDI11-B Processor

The processor comprises the M7260 Data Path Module and the M7261 Control Logic and Microprogram Module.

They are hex height modules which measure 8-1/2 inches long by 15 inches high. A hex height module contains six
edge connectors (A-F).
All

the

processor

functional components are contained on these modules. The M7260 Data Path Module

contains: data path logic, processor status word logic, auxiliary arithmetic logic unit control, instruction register and

decoding logic, and serial communications line interface. The M7261 Control Logic and Microprogram Module
contains: internal address detecting logic, stack control logic, Unibus control logic, priority arbitration logic, Unibus
drivers and receivers, microbranch logic, microprogram counter, control store logic, power fail logic, line clock, and
processor clock.

The serial communications line (SCL) interface is directly connected to the desired serial communications device. It
can operate at speeds of 110—300 baud and is program compatible with the KL11 Teletype Control Interface

option. The SCL is compatible with the LA30 DECwriter at 30 characters per second, the VTOS Alphanumeric CRT
Display Terminal at 30 characters per second, and the Teletype Model 33 ASR at 10 characters per second.

The line time clock (LTC) allows the program to measure time by sensing the 50 Hz or 60 Hz ac line frequency. This
clock is program compatible with the KW11-L Line Time Clock option.

The line time clock and the serial communications line interface are not connected to the Unibus; they use an
internal bus and can be addressed only by the processor and the console.
1.2.2

Core Memory

The PDP-11/05 is available in two versions: one provides a maximum of 8K words of core memory and the other

provides a maximum of 16K words. The PDP-11/10 is available only with a maximum of 8K words of core memory.
A separate add-on core memory system (ME11-L) is available to provide an additional 8K, 16K, or 24K words of

core memory. A PDP-11/05 or PDP-11/10 processor provides program control for a maximum of 32K words of
memory; therefore, the self-contained memory plus the ME11-L must not be greater than 32K words.

1-1

1.2.2.1

Memory Organization — The memory is organized in 16-bit words consisting of two 8-bit bytes. The bytes

are identified as low and high. The memory contains 8192 words or 16,384 bytes; therefore, 16,384 locations are
assigned. The address locations are specified as 6-digit octal numbers. The 16,384 locations for the 8K memory are
designated 000000 through 037777.

Each byte is addressable and has its own address location; low bytes are even numbered and high bytes are odd
numbered. Words are addressed at even numbered locations only, and the high (odd) byte is automatically included.
Consecutive words are therefore found in even numbered addresses.

The PDP-11 address word contains 18 bits [A (17:00)], which provides the capability of addressing 262,144 (256K)

locations (bytes) or 131,072 (128K) words. The basic processor provides

16 bits

[A (15:00)]

of address

information, which handles 65,536 (64K) bytes or 32,768 (32K) words. During an addressing operation, if bits A

(15:13) are all 1s, bits A (17:16) are forced to ls, which relocates the last 8K bytes (4K words) to become the
highest locations accessed by the bus. These top 4,096 word locations are reserved for peripheral and register
addresses, and the user therefore has 28,672 (28K) words of memory to program.

1.2.2.2

Memory Specification — The core memory is a read/write, random access, coincident current type with a

cycle time of 900 ns and an access time of 400 ns. It is organized in a 3-dimensional, 3-wire planar configuration
with a word length of 16 bits. The memory is offered in two word capacities:

the MM11-K Core Memory contains

4096 words and the MM11-L Core Memory contains 8192 words. Each memory is contained on three modules
designated the stack, control, and driver modules. For the MM11-K memory, the stack module is H213; H214 is the
stack module for the MM!1-L memory. The G110 Control Module and the G231 Driver Module are the same for
both memories.

1.2.3

Power Supply

The power supply consists of a dc regulator module, transformer, and fan, mounted in a chassis. It is installed in the
computer mounting box. The power supply converts 115V or 230V, 47-63 Hz line voltage to three regulated dc
voltages that are used by the processor, memory, and optional modules. The regulated voltages are: +5V at 17A,
-15V at 6A, and +15V at 1A.

An associated component, the power control, provides the ac line voltage to the power supply and cooling fans. The
power control is installed in the rear panel of the computer mounting box. It consists of a line cord, circuit breaker,

and output connector. A model is available for each of the two line voltages (115V or 230V), as shown below.
Power Control
Part Number

Rating

BCOSH

7A at 115V/47-63 Hz

BCOS5J

4A at 230V/47-63 Hz

The power supply provides three additional outputs. Signal LTC L is the Line Time Clock signal that drives the line

time clock. The BUS AC LO L and BUS DC LO L signals actuate the processor power-fail auto-restart circuitry.
1.2.4

Backplane

The backplane is the connector assembly into which the computer modules are plugged. It provides interconnections
between the Unibus, processor, memory, and optional modules. The interconnections are made via a printed circuit

board and wirewrapped pins that are part of the backplane assembly.
The backplane is wired differently for the 8K and 16K memory versions of the computer. As a result, the modules
must be installed in specific locations as shown in Figure 1-1 for the 16K version and Figure 1-2 for the 8K version.
These illustrations show the backplane as viewed from the module side. The slots are numbered 1 through 9 from
top to bottom, and the connectors are lettered A through F from left to right.

SLOT,

2 | RN

HATOR MaS

MEMORY STACK H213 (4K) OR (8K)

MEMORY DRIVER 6231

MEMORY CONTROL GHO

UNIBUS TERMINATOR M930

MEMORY STACK H213 (4K) OR

MEMORY

(8K)

DRIVER G231

MEMORY CONTROL G110

KD11-B PROCESSOR M7261

KD11-8

PROCESSOR M7260

CONNECTOR

Figure 1-1

free

Module Utilization Diagram for Configuration 1 (16K)

SLOT

DF11

COMMUNICATIONS
LINE

PERIPHERAL

ADAPTER

CONTROLLER

OR GRANT CONTINUITY

KM11

MAINT

CARD G727

(SLOT

PERIPHERAL CONTROLLER
OR GRANT CONTINUITY CARD G727 (SLOT D2)

UNIBUS TERMINATOR M930 OR
EXTERNAL UNIBUS CABLE

BLANK

PERIPHERAL CONTROLLER
OR GRANT CONTINUITY CARD G727

PERIPHERAL

(SLOT

D3)

(SLOT

04)

CONTROLLER

OR GRANT CONTINUITY CARD G727

UNIBUS TERMINATOR M930

MEMORY

STACK H213 (4K) OR H214 (8K)

MEMORY DRIVER 6213

MEMORY CONTROL G110

KD1-B

KD11-B PROCESSOR M7260

PROCESSOR M7261

CONNECTOR

Figure 1-2

DI}

Module Utilization Diagram For Configuration 2 (8K)

1-3

n-t222

Configuration 1 is the 16K version (Figure 1-1). Unibus M930 Terminator Modules are installed in slots A2-B2 and
AS5-BS. If other peripherals are to be connected to the computer, the terminator module in slot A2-B2 must be
replaced with a BC11A Unibus cable, and a terminator module must be installed in the last device in the system. Slot
C1-F1 provides the only space for a small peripheral controller. If this slot is not used, A G727 Grant Continuity
Module must be installed in slot D1. If a small peripheral controller is to be instalied, the G727 module must be

removed first. Slots Al and Bl are wired for the KM11 Maintenance Module. The core memories (3 modules each)
are physically interchangeable as systems.

Configuration 2 is the 8K version (Figure 1-2). Unibus M930 Terminator Modules are installed in slots A3-B3 and
A5-BS5. If required, a BC11A Unibus cable can be installed in place of the terminator in slot A3-B3. Slots C1-F1,
C2-F2, C3-F3, and C4-F4 can be used for small peripheral controllers. Slot Al-Bl is wired for a DF11
Communications Line Adapter that provides signal conditioning for communications devices using signals that are
not TTL compatible. Slots A2 and B2 are wired for the KM11 Maintenance Module.

Figure 1-3 shows the backplane connector block configuration as viewed from the wirewrap pin side. The pin

arrangement for each connector block is identical. It represents the total pins (36) available on the double-sided edge
connector of a single height module. Connector Al is shown in detail. Module contact designations are shown in
Figure 14.

LAYOUT

PER BLOCK

VeT*R*N®L*yJ®*F°*D®8"*
.

o.‘.o...o.o.o...o.
F

9
VIEW FROM WIRE

WRAP PIN SIDE
1-1220

Figure 1-3

Computer Backplane Connector and Pin Designations

18 CONTACTS

ON EACH SIDE

:
E

SIDE 1

CONTAINS

COMPONENTS

M
L

NOTES:

1. Side 1 is component side.

J
H

2. Each side contains

18 contacts that are designated

A-V {omitting G,I,0,Q.W,X,Y,2)

3. A complete designation contains

a connector letter prefix,

contact latter,and side suffix number.
for example: AD2

A
ey
t1-1568

Figure 1-4

1.3

Module Contact Designations

ME11-L CORE MEMORY SYSTEM

Additional core memory is available for the computer in the self-contained add-on ME11-L Core Memory System.
The basic ME11-L consists of an 8K MMI11-L memory and power supply installed in a mounting box. It is

expandable to 16K words or 24K words maximum by adding one or two more MM11-L memories. The ME11-L uses

the same backplane construction as the computer. Nine slots are provided and they are wired to accommodate three
MM11-L memories. These core memories (3 modules each) are physically interchangeable as systems and as
individual modules within a system for troubleshooting purposes. If only one memory is used, the modules must be

installed in the three bottom slots (7, 8, and 9).

1.4

EXTENSION MOUNTING BOX

Additional interface logic for the computer is installed in an extension mounting box identical to those used for the

rest of the PDP-11 family. A rack-mounted box (BA11-ES) or a tabletop box (BA11-EC) can be used. The mounting
box contains cooling fans, filter, and power cord. Space is provided to install six system units and an H720 Power

Supply. Details of the extension mounting box, system units, and H720 Power Supply are included in the PDP-11
Peripherals Handbook.

1-5

CHAPTER 2

UNIBUS

2.1

INTRODUCTION

This chapter describes in general the operation of the Unibus.

The following documents, in conjunction with this manual, will aid the reader in understanding interface techniques
and the overall PDP-11 system.

PDP-11/05, 11/10 Processor Handbook

PDP-11 Peripherals Handbook

Digital Logic Handbook

All communication between PDP-11 system components is through the high-speed Unibus. The Unibus operational
concepts are vital to the understanding of the hardware and software implications of the Unibus.
2.2

UNIBUS STRUCTURE

The Unibus is a single common path that connects the processor, memory, and all peripherals. Addresses, data, and
control information are transmitted along the 56 lines of the bus.

Every device on the Unibus employs the same form of communication; thus, the processor uses the same set of
signals to communicate with memory and with peripheral devices. Peripheral devices also communicate with the
processor, memory, or other peripheral devices via the same set of signals.

All instructions applied to data in memory can be applied equally well to data in peripheral device registers, enabling
peripheral device registers to be manipulated by the processor with the same flexibility as memory. This feature is
especially powerful, considering the capability of PDP-11 instructions to process data in any memory location as
though it were an accumulator.

2.2.1

Bidirectional Lines

Most Unibus lines are bidirectional, allowing input lines to also be driven as output lines. This is significant in that a
peripheral device register can be either read or used for transfer operations. Thus, the same register can be used for
both input and output functions.

2.2.2

Master/Slave Relationship

Communication between two devices on the bus is based on a master/slave relationship. During any bus operation,
one device, referred to as the bus master, has control of the bus when communicating with another device, the slave.

A typical example of this relationship is the processor (master) transferring data to memory (slave). Master/slave
relationships are dynamic. The processor, for example, passes bus control to a disk; the disk, as master, then
communicates with a slave memory.

2-1

The Unibus is used by the processor and all 1/O devices; thus, a priority structure determines which device gains
control of the bus. Consequently, every device on the Unibus capable of becoming bus master has an assigned
priority. When two devices capable of becoming bus master have identical priority values and simultaneously request

use of the bus, the device that is electrically closest to the bus receives control.
2.2.3

Interlocked Communication

Communication on the Unibus is interlocked between devices. Each control signal issued by the master device must
be acknowledged by a response from the slave to complete the transfer. Consequently, communication is
independent of the physical bus length and the response time of the master and slave devices. The maximum transfer
rate on the Unibus, with optimum device design, is one 16-bit word every 400 ns or 2.5 million 16-bit words per
second.

2.3

PERIPHERAL DEVICE ORGANIZATION AND CONTROL

Peripheral device registers are assigned addresses similar to memory; thus, all PDP-11 instructions that address
memory locations can become I/O instructions, enabling data registers in peripheral devices to take advantage of all
the arithmetic power of the processor.

The PDP-11 controls devices differently than most computer systems. Control functions are assigned to a register
address, and then the individual bits within that register can cause control operations to occur. For example, the
command to make the paper-tape reader read a frame of tape is provided by setting a bit (the reader enable bit) in
the control register of the device. Instructions such as MOV and BIS may be used for this purpose. Status conditions
are also handled by the assignment of bits within this register, and the status is checked with TST, BIT, and CMP
instructions.

2.4

UNIBUS CONTROL ARBITRATION

The Unibus is capable of performing two basic and parallel tasks in order to allow transfers by multiple peripherals
at maximum speed. The first is the actual transfer of data between the current bus master and its addressed slave.

The second is the selection of the next bus master, the peripheral which will be allowed to assert control as soon as
the bus becomes free. It is important to note that the granting of future mastership is in no way influenced by either

the current master or its method of obtaining the bus. It is this fact which allows these functions to be performed in
parallel and allows transfers on the bus at a maximum rate.

2.4.1

Priority Transfer Requests

To gain mastership of the Unibus, a peripheral must first make a request to the processor for the bus and then wait

for its selection. The processor contains the logic necessary to arbitrate these requests because normally there are

several requests pending at any given time.

There are two classes of requests: bus requests and non-processor requests. A bus request (BR) is simply a request
by a peripheral to obtain control of the Unibus with the understanding by the processor that the peripheral may end
its use of the bus with a processor interrupt. An interrupt is a command to the processor to begin executing a new
routine pointed to by a location selected by a device. A non-processor request (NPR) is similarily a request for the

bus, but with the exception that it may not interrupt the processor. Since the granting of an NPR cannot affect the

execution of the processor, it can occur during or between instructions. BRs however, by possibly causing execution
to be diverted to a totally new routine, can only be granted between instructions. In this way, NPRs are assigned

priority over any BR.

Between bus requests, there are four levels of priority created by four separate request lines. They are assigned
priority levels 4 through 7; BR4 is the lowest and BR7 is the highest. These levels are associated with the program
controlled priority level of the processor controlled by bits 7, 6, and 5 of the processor status register. Only BRs on
a priority level higher than the level of the processor are eligible for receiving a bus grant. Thus, during high priority

program tasks, all or selected Unibus requests (hence interrupts) can be inhibited by raising the level of the processor
priority.

Another form of priority arbitration occurs through the system configuration. When the processor grants a request,
the grant travels along the bus until it reaches the first requesting device which terminates the grant. Therefore, along
the same grant line, the device electrically nearest the processor has the highest priority. Also note that in the

KD11-B, the internal line clock is logically the last device on BR6, and the serial communication line interface is
logically the last device on BR4.

After a requesting device receives a bus grant it asserts its selection as next bus master until the bus is free, thus
inhibiting other requests from being granted. When the bus becomes free, the selected device asserts control of the
bus and relinquishes its selection as next bus master so that the priority arbitration among pending requests may
continue.

2.4.2

Processor Interrupts

After gaining control of the bus through a BR, a device can perform one or more transfers on the bus and/or request
a processor interrupt. This is typically requested after a device has completed a given task; e.g., typing a character or
completing a block data transfer through NPRs. If a peripheral wishes to interrupt the processor, it must assert the
interrupt after gaining control of the bus but before relinquishing its selection as next bus master. Thus the processor

knows that it may not fetch the next instruction, but must wait for the interrupt to be completed. Along with
asserting the interrupt, the device asserts the unique memory address, known as the interrupt vector address,
containing the starting address of the device service routine. Address vector +2 contains the new processor status
word (PSW) to be used by the processor when beginning the service routine. After recognizing the interrupt, the

processor reads the vector address and saves it in an internal register. It then pushes the current PSW and program

counter onto the stack and loads the new program counter (PC) and PSW from the vector address specified. The
service routine is then executed.
NOTE

These operations are performed automatically and no
device polling is required to determine which routine to
execute.

The device service routine can cause the processor to resume the interrupted process by executing the return from
interrupt (RTI) instruction which pops the top two words from the processor stack and transfers them back to the
PC and PS registers.

2.4.3

Data Transfers

After asserting control of the Unibus, the device does not release control until it has completed either one or more

data transfers or an interrupt. Typically, only one transfer is completed each time the device gains control of the bus
because few single devices can give or receive information at the maximum Unibus rate. Holding the bus for multiple
transfers inhibits other devices from using the bus.

A transfer is initiated by the master device asserting a slave address and control signals on the bus and a master or
address validity signal. The appropriate slave recognizes the valid address, reads or writes the data, and responds with
a transfer complete signal. The master recognizes the transfer complete, sends or accepts data, and drops the address
validating signal. [t can then assert a new address and repeat the process or release control of the bus completely.
The importance of this type of structure is that it enables direct device-to-device transfers without any interaction
from the central processor. An NPR device, such as a high speed CRT display, can gain fast access to the bus and
transfer data at high rates while refreshing itself from memory without slowing down the processor.

CHAPTER 3

UNPACKING AND

3.1

INSTALLATION

INTRODUCTION

The computer is shipped ready to operate in either a protective box or a 19-inch cabinet. Unless required by
peripherals, there are no special shipping mounts internal to the computer. Prior to final electrical testing, each
computer is thermal cycled, vibrated, and subjected to mechanical shock with all modules in place.
Basic computers are shipped in the package illustrated in Figure 3-1. Sufficient hardware is included in the shipping
carton to rack mount the computer.

3.2

s—.

UNPACKING

Remove the computer from the box and remove the protective plastic cover from the console. Slide mounts are
attached to the computer, but mounting screws are packed in a bag located in the same box. Also included is one
83600 Serial Communication Line (SCL) cable and two keys for the console lock. The 83600 SCL cable has a Berg
127009-0, 40-pin connector on one end that matches the SCL output connector on the computer. The other end of
the 83600 SCL cable terminates in a Mate-N-Lok 1209340 which matches that used on the VT0S, LA30, and Model

33 ASR Teletype®.

If the computer was ordered as a system with options requiring small peripheral controllers, the controllers may be

inside the computer box. Small peripheral controllers are used to interface options such as a line printer or

paper-tape reader/punch, as well as to implement a device such as a programmable clock.

After removing the computer from its package, it should be inspected for damage. It is advisable to save the packing

carton in case it is necessary to return the unit for service.

A computer shipped in a 19-inch cabinet is locked in place by a metal lock attached to the rear of each slide
assembly. Each lock is J-shaped and is attached by an 8-32 screw that passes through the slot in the chassis section of
the slide and is threaded into the longer leg of the lock. The shorter leg is hooked around the end of the cabinet
section of the slide to prevent extension of the slide. Both locks must be removed in order to slide the computer out
of the cabinet. Retain the locks and screws for re-use if the equipment is to be shipped or moved any distance.
3.3

MECHANICAL DESCRIPTION

Figure 3-2 illustrates the 5-1/4 by 19 by 20 inch computer mounting box, including rack-mountable slide and
console. The removable top cover of the mounting box is fastened by four Cam-Lock screws. The removable side

panel is fastened by four Phillips-head screws.

Figure 3-3 shows the mounting box with the top cover removed. The backplane unit divides the power supply from
the module side of the mounting box. The internal SCL cable runs from the backplane under the power supply unit
to the rear of the mounting box.

®Teletype is a registered trademark of the Teletype Corporation.
3-1

<_FOLDED

CORRUGATED

LAMINATED

CEE

PDP-11/05

BEZEL

PROTECTOR

QUTER

CARTON

INTERIOR

WITH

PIECES

11-1223

Figure 3-1

Computer Packaging

REMOVABLE

SLIDE

REMOVABLE

SIDE PANEL

TOP COVER

GUIDE
CONSOLE

DECORATIVE

PANEL

Figure 3-2

6307-2

Computer Mounting Box

BACKPLANE UNIT

MODULE SIDE

COMPUTER
FAN

FRONT

POWER
CONTROL
CHASSIS

POWER SUPPLY FAN

POWER SUPPLY

Figure 3-3

INTERNAL SCL CABLE

Computer Box With Top Cover Removed

63075

Figure 3-4 shows the mounting box with top cover and side panel off, and the processor and memory modules
plugged in. In this case, the computer is a Configuration 2 machine, using an MM11-L, 8K memory unit. Three small
peripheral controllers are shown with the external cables attached. A G727 Grant Continuity Card is in the top

peripheral slot and an M930 Unibus Terminator Card is in slot A3, B3. In Figure 3-5, the Unibus cable is in place,
replacing the Unibus terminator card.

Figure 3-6 shows the mounting box without modules. The path of the console cable is under the M7260 Processor
Module, then up and over to plug into the top of the M7260. The module guides aid in inserting the modules into
proper slots.

Figure 3-7 is a rear view of the mounting box with attached rack-mountable slides. If the computer contains
peripheral controllers outside the mounting box, the Unibus is extended from under the top cover. The power
control circuit breaker protects the power supply from overload. It is rated at 7A for 110V units or 4A on 230V.

The SCL connector and ac remote power control connectors are also shown.

UNIBUS

TERMINATOR

G727

GRANT CONTINUITY

CARD

FRONT

SLIDE RELEASE

PERIPHERAL CABLE

Figure 3-4

UNIBUS

CABLE

AND

UNIBUS

CONSOLE CABLE

SMALL PERIPHERAL

Computer Box with Top and Side Covers Removed

CABLE

CONTROLLER

63133

CLAMP

63134

Figure 3-5

Computer Chassis (showing peripheral cables and the Unibus)

A
SLOT

SLOT B

CENTER

CONSOLE CABLE CLAMP
CONSOLE

SLOT

GUIDE

SLOT C

CONSOLE

CABLE

SLOT

MODULE

GUIDES

CABLE CONNECTOR
6307-1

Figure 3-6

Mounting Box Without Modules

UNIBUS

CABLE

POWER CONTROL,LINE CORD AND
CIRCUIT BREAKER ASSEMBLY

BEZEL HOLE ——
I/0 CABLE

CABINET POWER
CONTROL CONTACTS

UNIVERSAL I/0
CABLE

CLAMP

SCL CABLE

(LETTER ON CONNECTOR
FACE

UP)

Figure 3-7

Rear of Computer With Cable Strain Reliefs
3-5

3.4

INSTALLATION

The computer mounts in a standard 19-inch wide by 25-inch deep equipment bay. The computer is mounted on
slides for easy service. To mount the unit, first attach the fixed portion of the slides to the cabinet; the fixed portion
of the slides can be removed from the computer by actuating the slide release shown in Figure 34. Be sure to mount
the slides so that the fixed guides are parallel and level with the ground.

3.4.1

Mounting Computer on Installed Slides

Once the slide guides have been securely fastened in the cabinet using all eight screws, lift the computer and slide it

carefully onto the slide guides until the slide release locks. Lift the slide release and push the computer fully into the
rack, being careful not to tear any existing cabling.

Slightly loosen all eight cabinet slide mounting screws. Slide the computer back and forth several times to allow the
slides to assume an optimum position. Push the computer into the cabinet as far as possible, leaving access to the

The computer should then be fully extended until the slide release locks. As shown in Figure 34, the panel on the
module side of the computer should be removed to permit installation of /O cables and the Unibus if required. The
panel is removed by loosening and removing four Phillips-head screws.

3.42

Securing Computer to Cabinet Rack

If the rack-mounted computer is used in a moving environment, it must be secured to the cabinet rack to prevent the

machine from moving on its slides. This option, if desired, is implemented as follows:
1.

Remove the console bezel from the computer by removing the four screws at the rear of the bezel, being

careful not to tear the cable that connects the console and processor.

2.
3.

Drill the partial 7/32-inch holes at each top inside corner of the bezel through from the rear of the bezel.
Counter-bore the 7/32-inch holes at the front of the console bezel 1/2 inch in diameter to a depth to
accommodate the full head of a 10-32 machine screw.

Replace the console bezel.

Use two 10-32 by 2-inch Phillips-head screws and two Tinnerman nuts (PN 9007786) to secure the
computer to the cabinet rack through the bezel holes at the desired rack position.

To make the 10-32 by 2-inch Phillips-head screws captive, machine a 1/8-inch deep by 1/8-inch wide
groove, in each 10-32 by 2-inch Phillips-head screw just above the threads toward the head and insert a

1/8 LD. O-ring in each groove.

3.4.3

Installation of 1/O Cables

Flat and round 1/O cables should be fed through the universal I/O cable clamp shown in Figure 3-6 for strain relief.
They should then be connected to the appropriate small peripheral controllers. Note that the strain relief clamp
prevents tension on the cables from damaging the connector block inside the computer. The wide Unibus cable, if

required, should be folded as shown in Figure 3-5 and routed over and through a clamp attached to the top of the
fan as shown in Figure 3-7. Note that there is a guide extending from the fan that prevents the Unibus cable from
blocking air flow to the computer.

front mounting screws. Tighten all eight cabinet slide mounting screws. Slide the computer back and forth and check
for binding of the slides. If there is binding, repeat the above procedure until it is eliminated.

As shown in Figure 3-4, systems in which the Unibus is terminated in the computer box must have an M930
Terminator Card in slot A3-B3 as well as in slot A5-BS.

3.5

INTERCHANGEABLE PERIPHERAL SLOTS

The four peripheral slots in Configuration 2 are identical; therefore, it is possible to arrange the small peripheral
controllers for the best mechanical convenience. For example, to diagnose a failure in a small peripheral controller, it

may be convenient to place the selected option in the top slot where its components will be exposed.

3.6

SIDE AND TOP COVER INSTALLATION

Figures 34 and 3-5 show the computer ready for installation of the side cover. Note that the console cable is folded
into a flat loop in order to clear the side cover. Attached to the side cover is the continuation of the left-hand slide.

All four 8-32 screws that hold the cover in place should be inserted and tightened securely. The top cover can now
be installed using the four Cam-Lock screws.

3.7

ACPOWER SUPPLY CONNECTION

Computers designed for use on 115-Vac circuits are equipped with a 3-prong connector, which, when inserted into a
properly wired 115-Vac outlet, grounds the case of the computer. It is unsafe to operate the computer unless the

case is grounded since normal leakage current from the power supply flows into metal parts of the chassis.

If the integrity of the ground circuit is questionable, the user is advised to measure the potential between the
computer case and a known ground with an ac voltmeter.

3.7.1

Connecting to Voltages Other than 115V

The computer will operate at voltages ranging from 95V to 135V and from 190V to 270V (47 Hz — 63 Hz),
providing the proper power control is attached to the computer. The computer is ordered for nominal voltages of

115V or 230V. The standard 3-prong connector for 115V is identical to that found on most household appliances. A
standard 3-prong connector is also used for 230V.

On installations outside of the United States or where the National Electrical Code does not govern building wiring,
the user is advised to proceed with caution.

3.7.2

Quality of AC Power Source

Computer systems consisting of CPU, memory, and peripherals are often sensitive to the interference present on
some ac power lines. If a computer system is to be installed in an electrically “noisy” environment, it may be
necessary to condition the ac power line. DEC Field Service Engineers can assist customers in determining if their ac
line is satisfactory.

3.8

CABINET POWER CONTROL

Provisions have been made for the computer switch to operate a cabinet power control. This feature permits the
computer key lock switch to control the power supply for peripherals attached to the computer (Part 4). The power
control contacts are closed when the key lock switch is in the POWER or PANEL LOCK positions. The wiring

diagram for a typical cabinet power control system is shown in Figure 3-8. The power control contacts of the
computer may be used to switch a maximum of 230V at 4A.

3-7

I'__""'"'_fl

UNSWITCHED AC

==
o____‘i—'_k_r_fib_l_l
1
=
=
=
LINE CORD

10 MOTOR

Ly CONTROL
power |¢St
SONTROLLER

l — 1

' ME

]

1
!

L_____otfi
________ =
t?
?
!
L

ri=s|——==-—=-= 1
|

coNTRoL [ SSNTROLL

1 =

2 2

| —
!

l
o Tt
e
DISK SYSTEM
@
L_.___..__.7 —to i o—4—

N
[

POWER = t3yrroLl€R

CIRCUIT | S0Pely

______I_ L

1 R
B

31 Y R

b
@
POWER

controOL

3.9

D EXSRE] DS L |

T
]
PROCESSOR
L__....___.J

BUS

]

N.O.
i

Figure 3-8

CABLE

I —1

POWER CONTROL BUS SWITCH

CABINET THERMOSTAT @

=
=

CABINET

SWITCHED AC

|—~o0Rary

@POWER
CONTROL

(

CIRCUIT

POwER
CIRCUIT

r tg) ————— 7
|

(TO BLDG

AC POWER)

e_Ll7

POWER

H-1225

Typical Cabinet Power Control System Wiring Diagram

INSTALLATION CERTIFICATION

Once the computer has been installed, it is strongly recommended that a system diagnostic be run to ensure that the
equipment operates correctly and that installation has been properly performed. Because system configurations
widely vary, no one diagnostic will completely exercise all the attached devices.
The MAINDEC User’s Manual that comes with the diagnostic package should be consulted for the appropriate

diagnostic to be run, depending upon the attached devices. The MAINDEC User’s Manual lists the devices that each
diagnostic

will

exercise.

The

three

system

exercisers

presently

available

are

TI17

System

Exerciser

(MAINDEC-11-DZKAP) for relatively small systems, General Test Program (MAINDEC-11-DZQGA) for medium to
large systems, and Communications Test Program (MAINDEC-11-DZQCA) for communications-oriented systems. At
least one of the above diagnostics and, if appropriate, the other two, should be used to verify system operation.
Once

the diagnostic is selected, the respective diagnostic write-up should be consulted for specific operating

instructions. If the user is not familiar with console operation and/or procedures for loading paper tapes, he should
read Chapter 4 of this manual.

3-8

3.10

WARRANTY SERVICE (Domestic Only)

If the machine is still covered under the 30 day return-to-factory warranty, and it is desired to return it for factory
service, the following procedure should be used. If the machine is no longer on warranty, the local DEC Field Service

office should be contacted.

1.
2.

Call the Maynard, Massachusetts Repair Depot, Telephone 617-897-5111, X4079 or X2135.
The caller will receive an RA (Return Authorization) number, which must appear on the shipping label

of the package being returned.
3.

Package the machine in an equivalent shipping container, similar to the one the computer arrived in. If

possible, use the original computer shipping container.

Send the machine to the following address:
Digital Equipment Corporation
146 Main Street
Maynard, Massachusetts 01754
Att:

Depot Repair, Bldg, 214

RA # XXXX

3-9

CHAPTER 4
COMPUTER OPERATION

4.1

INTRODUCTION

This chapter assumes that the computer is installed and connected to the ac power line. It is also assumed that the
reader has access to the appropriate diagnostic materials, and a copy of the absolute loader paper tape. It is further
assumed that the user is using paper tapes to load software and diagnostics. For systems that have mass storage
services, i.e., disks or DECtape, the user should refer to the appropriate software manuals for mass storage operating
systems.

4.2

POWER SWITCH OPERATION

The key lock power switch shown in Figure 4-1 has three positions:
OFF — Fully counterclockwise

POWER — 90° clockwise from OFF

PANEL LOCK — 180° clockwise from OFF
In the OFF position, ac power is removed from the primary of the computer power supply, and the cabinet power
control contacts are open-circuited. In the other two positions, the ac power is applied to the computer power

supply and the cabinet power control contacts are short-circuited. In the POWER position, the console function
switches (the right six switches in Figure 4-1) are fully operative. In the PANEL LOCK position, the console
function switches have no effect on the computer’s operation. PANEL LOCK is used to secure a running computer

from mischievous tampering.

ADDRESS/DATA

SWITCHES

(16)

FUNCTION

SWITCHES (6)

KEY

LOCK

63131

Figure 4-1

Console Illustrating Switch Movements

4-1

4.3

FUNCTION SWITCHES

The right six switches in Figure 4-1 are called function switches. They are listed below in order of their appearance

A Ul

from left to right.

LOAD ADRS (load address)
EXAM (examine)
CONT (continue)

ENABLE/HALT
START

DEP (deposit)

Function switches 1 through § are actuated by being depressed as is the ENABLE/HALT switch in Figure 4-1. The

DEP switch must be lifted for actuation. All of the function switches, with the exception of ENABLE/HALT, are
spring loaded and return to their rest state when released.
4.4

ADDRESS/DATA SWITCHES

The 16 ADDRESS/DATA switches are to the left of the function switches (Figure 4-1). These 2-position switches
represent a manually set flip-flop register with the up position representing a logical 1 and the down position a
logical 0. The ADDRESS/DATA switches may be used in conjunction with the function switches or in conjunction

with a program stored in the computer’s memory. The ADDRESS/DATA switches are often referred to as the
Switch Register in DEC documentation. In Figure 4-1, the contents of the Switch Register is equal to 2004 because
bit 7 is set to a 1 and all others are set to a 0.
4.5

CONSOLE INDICATORS

There are 17 indicators on the computer console. The contents of the 16 ADDRESS/DATA lights cither represent a
16-bit Unibus address or the contents ofa 16-bit Unibus address. Note that the state of the ADDRESS/DATA lights
is defined only when the computer RUN light is not illuminated.
4.6

CONSOLE OPERATION

The following paragraphs describe the operation of the function switches. Table 4-1 indicates the meaning of the
ADDRESS/DATA lights for all cases where the contents of these lights are defined.
4.6.1

Load Address Switch

Depressing the LOAD ADRS switch when the computer is halted causes the contents of the Switch Register to be

stored in a temporary register within the computer. This data is also displayed in the ADDRESS/DATA lights for
verification. The load address operation performs the following functions:
a.

4.6.2

Selects a Unibus address for a subsequent examine operation.

Selects a Unibus Address for a subsequent deposit operation.

Selects the starting address of a program.

Examine Switch

The EXAM switch permits the display of the contents of a selected Unibus address in the ADDRESS/DATA lights.
Select the appropriate address in the Switch Register and depress the LOAD ADRS switch. Then depress and release
the EXAM switch. The contents of the selected address will then be displayed in the ADDRESS/DATA lights.
Several features are built into the examine function to aid in programming the computer.

While the EXAM switch is depressed, the address to be examined is displayed. The data itself is displayed
when the switch is released.

If the EXAM switch is repeatedly depressed, the Unibus address is incremented by two on each
depression*. This permits the examination of a list of addresses without repeated load address
operations.

The Unibus address is incremented by one when examining general registers.
4-2

Table 4-1
Significance of ADDRESS/DATA Indicators

Action

Qualification

Information Displayed In
ADDRESS/DATA Indicators

Power On

1. ENABLE/HALT switch in

1. Contents of location (24)g

HALT position

2. ENABLE/HALT switch in
ENABLE position

2. Undefined — depends on
contents of memory

Load Address

LOAD ADRS switch depressed

Contents of Switch Register

Examine

1. EXAM switch depressed

1. Unibus address that is to

be examined
2. EXAM switch released

2. Contents of Unibus address
that was examined

Deposit

1. DEP switch raised

1. Unibus address that is to
be deposited

2. DEP switch released

2. Contents of Switch Register
which is the data deposited

Undefined

RUN Light On
Program Halt

1. ENABLE/HALT switch

I. Address of instruction to
be executed when CONT

in HALT position

switch is actuated
2. Same as 1

2. HALT instruction
executed

3. Double bus error which

3. Contents of program

is two successive attempts

counter (R7) at time

to access non-existent

double bus error occurred

memory or improper odd

byte address.
Program
Execution

1. START switch depressed

1. Address of last load address

2. CONT switch depressed

2. Address of instruction to be
executed

If an attempt is made to examine non-existent memory, it is necessary to perform the initialize
operation explained in Paragraph 4.7.

Only full words are displayed in the ADDRESS/DATA lights; thus, bit O, the byte address bit, is ignored
when using the EXAM switch with the following exception. Note that the general registers are located
on byte addresses. Therefore, when examining the general registers, address bit O is recognized and the
increment feature is modified such that sequential registers may be examined by repeated use of the
EXAM switch.

4-3

Note that the EXAM switch has no effect while the computer is in the RUN state or when the key operated power
switch is in the PANEL LOCK position.
4.6.3

Deposit Switch

The physical operation of the DEP switch requires that it be lifted for actuation. The DEP switch permits the
contents of the Switch Register to be deposited in a Unibus address, which is typically specified by a previous load

address operation. To deposit the instruction BRANCH SELF (777;) in location 200g, first set the Switch Register
to 200z as shown in Figure 4-1 and actuate the LOAD ADRS switch. Set the Switch Register to 7775 then lift and
release the DEP switch.
Several additional features are built into the deposit function:

While

the

DEP

switch

actuated,

the

Unibus

address

effected

displayed

the

ADDRESS/DATA lights. When the switch is released, the data deposited is displayed for verification.
b.

If the DEP switch is repeatedly depressed,

the Unibus address is incremented by two on each

depression*. This permits the depositing of an entire program with only one load address operation.
c.

If an attempt is made to deposit into non-existent memory, it is necessary to perform the initialize
operation explained in Paragraph 4.1.

All deposit operations affect full 16-bit words. Bit O of the address is used only when depositing into
general registers, otherwise, bit O of the address is ignored.

4.6.4

ENABLE/HALT Switch

Place the ENABLE/HALT switch in the HALT position (Figure 4-1); the computer will halt at the end of the
current instruction, providing the key switch is not in the PANEL LOCK position. All interrupts and traps will be

executed prior to halting. This switch may be used in conjunction with the CONT switch to step through programs

(Paragraph 4.6.6). With the ENABLE/HALT switch in the ENABLE position, programs may be executed once
started by: actuating the START switch, actuating the CONT switch, and the auto-restart power-up sequence.
4.6.5

START Switch

The sequence for starting a program from the console is as follows:
Set the starting address of the program in the Switch Register.
Depress the LOAD ADRS switch.

Position the ENABLE/HALT switch in the ENABLE position.
Depress and release the START switch.

While the START switch is depressed, the following actions occur:

Aninitialize signal is generated on the Unibus. This initialize signal serves to reset all peripherals.

The program status word is reset to zero.

The program counter, R7, is loaded with the last address loaded with the LOAD ADRS switch.

When the START switch is released, program execution begins with the instruction contained in the location
specified by R7 and the RUN light is turned on. If the ENABLE/HALT switch is in the HALT position, the
computer remains in the HALT state following the release of the START switch.

*The Unibus address is incremented by one when depositing into general registers.
4-4

A—

Observe the following precautions when using the START switch:
a.

If the keylock is not in the PANEL LOCK position, depressing the START switch while a program is
running initializes the computer system and restarts the program.

c¢.

Itis good practice to precede every program start with a load address operation.

A program should not be started at an odd address or the first fetch operation will be aborted and an
odd address trap will be attempted. If the stack pointer, R6, is not properly set up, the program in
memory may be destroyed.

4.6.6

Continue Switch

The CONT switch is used to continue a program without altering the program counter, R7, or the machine state. To
continue a halted program, depress and release the CONT switch. The program is resumed when the CONT switch is
released.

The CONT switch is used with the ENABLE/HALT switch to step through programs one instruction at a time. If the
CONT switch is actuated while the ENABLE/HALT switch is in the HALT position (Figure 4-1), a single instruction
will be executed. Note that interrupts are serviced in single instruction mode. In single step mode, the address of the
next instruction to be executed is displayed in the lights.

4.7

UNCONDITIONAL COMPUTER AND UNIBUS INITIALIZATION

Unconditional initialization of the computer system usually occurs because of an attempt to examine from, or
deposit into, non-existent memory from the console. However, a peripheral or processor error may occur that can

only be overcome by initializing the system from the console. The procedure is simply to depress the START switch
with the ENABLE/HALT switch in the HALT position.
4.8

LOADING PROGRAMS FROM PAPER TAPE

When the computer is first received, the content of its memory is not defined (it knows absolutely nothing, not even
how to receive paper-tape input). However, the computer can accept data when toggled directly into core using the
console switches. The Bootstrap Loader program is the first program to be loaded, and therefore must be toggled
into core. The loaders described in this section facilitate the loading of programs from either the low or high speed
paper-tape reader. The low speed reader is part of the Model 33 ASR Teletype and is operated via the SCL. The high
speed reader is DEC part number PC-11.

The Bootstrap Loader program instructs the computer to accept and store in core data that is punched on paper
tape in bootstrap format. The Bootstrap Loader is used to load very short paper-tape programs of 1625 16-bit words
or less (primarily the Absolute Loader and Memory Dump programs). Programs longer than 162g 16-bit words must

be assembled into absolute binary format using the PAL-11A Assembler and loaded into memory using the Absolute
Loader.

The Absolute Loader (Paragraph 4.8.2) is a system program that enables data punched on paper-tape in absolute
binary format to be loaded into any available memory bank. It is used primarily to load the paper-tape system
software (excluding certain subprograms) and object programs assembled with PAL-11A.

The loader programs are loaded into the upper most area of available memory so that they will be available for use
with system and user programs. When writing programs, the locations used by the loaders should not be used
without restoring their contents; otherwise, the loaders will have to be reloaded because the object program will have
altered them.

Memory Dump programs are used to print or punch the contents of specified areas of memory. For example, when
developing or debugging user programs, it is often necessary to get a copy of the program or portions of memory.
4-5

There are two dump programs supplied in the paper-tape software system: DUMPIT, which prints or punches the

octal representation of all or specified portions of memory; and DUMPAB, which punches all or specified portion of
memory in absolute binary format suitable for loading with the Absolute Loader.
4.8.1

The Bootstrap Loader

The Bootstrap Loader should be loaded (toggled) into the highest memory bank. The locations and corresponding
instructions of the Bootstrap Loader are listed in Table 4-2 and explained below.

Table 4-2

Bootstrap Loader Instructions

Location

Instruction

XX7744

016701

XX7746

000026

XX7750

012702

XX7752

000352

XX7754

005211

XX7756

105711

XX7760

100376

XX7762

116162

XX7764

000002

XX7766

XX7400

XX7770

005267

XX7772

177756

XX7774

000765

XX7776

YYYYY

In Table 4-2, XX represents the highest available memory bank. For example, the first location of the loader would
be as indicated in Table 4-3, depending on memory size, and XX in all subsequent locations would be the same as
the first.
Note in Table 4-3 that the contents of location XX7766 should reflect the appropriate memory bank in the same
manner as the preceding locations.

Table 4-3
Memory Bank Assignments

Location

Memory Bank

Memory Size

017744

037744

057744

12K

077744

16K

117744

20K

137744

24K

157744

28K

The contents of location XX7776 (YYYYYY in the instruction column of Table 4-2) should contain the device
status register address of the paper-tape reader to be used when loading the bootstrap formatted tapes. Either
paper-tape reader may be used, and the associated address is specified as follows:
Teletype Paper-Tape Reader — 177560

High Speed Paper-Tape Reader — 177550

4.8.1.1

Loading the Loader Into Memory — With the computer initialized for use as described in Paragraph 4.7,

toggle in the Bootstrap Loader as explained below.
1.

Set XX7744 in the Switch Register (SR) and press LOAD ADRS switch (XX7744 will be displayed).

Set the first instruction, 016701, in the SR and lift DEP switch (016701 will be displayed).
NOTE

When depositing data into consecutive words, the DEP switch
automatically increments the address to the next word.
Set the next instruction, 000026, in the SR and lift DEP switch. Continue to deposit subsequent
instructions.

Deposit the desired device status register address in location XX7776, the last location of the Bootstrap
Loader.
NOTE

It is a good programming practice to verify that all instructions
are stored correctly. Proceed to Step 6.
Set XX7744 in the SR and press LOAD ADRS switch.

Press and release EXAM switch (the octal instruction in location XX7744 will be displayed so that it can
be compared to the correct instruction, 016701). If the instruction is correct, proceed to Step 38,
otherwise go to Step 10.

Press EXAM switch. The instruction of the location displayed in the ADDRESS/DATA indicators with
the switch depressed will be displayed when the switch is released. Compare the indicator contents to
the instruction at the proper location.

Repeat Step 8 until all instructions have been verified or go to Step 10 if the correct instruction is not
displayed.
NOTE

Whenever an incorrect instruction is displayed, it can be
corrected by performing Steps 10 and 11.
10.

With the incorrect instruction displayed in the ADDRESS/DATA register, set the correct instruction in
the SR and lift DEP switch. The contents of the SR will be deposited in the location displayed with the
key lifted.

Press EXAM switch to ensure that the instruction was correctly stored.

The Bootstrap Loader is now in core. The procedures above are illustrated in the flow chart of Figure 4-2.

4-7

Set SR
xx7744

Press
LOAD ADDR

Load

Load
or Verity

Verify

Instr.

Set SR
to

016701

Press EXAM

Set SR
to

Instruction

Set SR to
Correct
Instruction

Lift DEP

l
F

Lift DEP

l
At

All

Instr.

Instr.
Deposited

Verified

H-1219

Figure 4-2

Loading and Verifying the Bootstrap Loader

4.8.1.2

Loading Bootstrap Tapes — Any paper tape punched in bootstrap format is referred to as a bootstrap tape
and is loaded into memory using the Bootstrap Loader. Bootstrap tapes begin with about two feet of special
bootstrap leader code (ASCII code 351, not blank leader tape as is required by the Absolute Loader).

With the Bootstrap Loader in memory, it will load the bootstrap tape into memory starting anywhere between

location XX7400 and location XX7743; i.e., 1623 words. The paper-tape input device used is specified in location
XX7776. Bootstrap tapes are loaded into memory as explained below:
1.

Set the ENABLE/HALT switch to HALT.

Place the bootstrap tape in the specified reader with the special bootstrap leader code over the reader

sensors (under the reader station).

Set the SR to XX7744 (the starting address of the Bootstrap Loader) and press LOAD ADRS switch.

Set the ENABLE/HALT switch to ENABLE.
Press START switch. The bootstrap tape will pass through the reader as data is being loaded into
memory.

4-8

The bootstrap tape stops after the last frame of data (Figure 4-5) has been read into memory. The
program on the bootstrap is now in memory.

The procedures above are illustrated in the flowchart of Figure 4-3.

With Bootstrap

See Figure 4-2

Loader in Core

Set ENABLE/HALT
to HALT

;

Code 351 must be

Ptace Booistrap Tape
in Specified Reader

over Reader sensors

;

[

set SR 1o xx 7744

Press LOAD ADDR

;

Set ENABLE/HALT
to ENABLE

Press START

Tape Reads inand

Stops ot End of Data

Dota is 1n Core

Figure 4-3

N-1218

Loading Bootstrap Tapes Into Memory

If the bootstrap tape does not read in immediately after depressing the START switch, it is due to one of the

following reasons:

Bootstrap Loader not correctly loaded
Using the wrong input device

Code 351 not directly over the reader sensors

Bootstrap tape not properly positioned in reader

4.8.1.3 Bootstrap Loader Operation — The Bootstrap Loader source program is shown below. The starting address
in the example denotes that the program is to be loaded into memory bank zero (a 4K system).
The Bootstrap Loader source program is a brief but fairly complex example of the PAL-11A Assembly Language.

Explanations of the program and PAL-11A are found in the PDP-11 Paper-Tape Software Programming Handbook,
DEC-11-GGPB-D.

4-9

000001

R1=%1

;USED FOR THE DEVICE
;ADDRESS

000002

R2 %2

;USED FOR THE LOAD AD-

017400

LOAD=17400

;DATA MAY BE LOADED NO

017744

—17744

;START ADDRESS OF THE

;DRESS DISPLACEMENT

;LOWER THAN THIS
;BOOTSTRAP LOADER

017744

016701

START:

MOV DEVICE, R1

;PICK UP DEVICE ADDRESS,

LOOP:

MOV # .—LOAD+2, R2

;PICK UP ADDRESS

000026
017750

012702

PLACE IN R1

000352

;DISPLACEMENT

017754

005211

ENABLE:

INC @RI

;ENABLE THE PAPER TAPE

017756

105711

WAIT:

TSTD @ R1

;READER
;WAIT UNTIL FRAME

017760

100376

BPL WAIT

;IS AVAILABLE

017762

116162

MOVB 2(R1), LOAD (R2)

STORE FRAME READ

000002

;FROM TAPE IN MEMORY

017400

017770

005267

INC LOOP+2

177756

INCREMENT LOAD ADDRESS
;DISPLACEMENT

017774

000765

BRNCH:

BR LOOP

;GO BACK AND READ MORE

017776

000000

DEVICE:

;:DATA
;ADDRESS OF INPUT DEVICE

4.8.2

The Absolute Loader

The Absolute Loader is a system program that enables data punched on paper tape in absolute binary format to be

loaded into any memory bank. It is used primarily to load the paper-tape system software (excluding certain
subprograms) and object programs assembled with PAL-11A. The major features of the Absolute Loader include:
a.

Testing of the checksum on the input tape to ensure complete, accurate loads

Starting the loaded program upon completion of loading without additional user action, as specified by
the .END in the program just loaded

¢.

Specifying the load address of position independent programs at load time rather than at assembly time,

by using the desired loader Switch Register option.

4.8.2.1

Loading the Loader Into Memory — The Absolute Loader is supplied on punched paper-tape in bootstrap
format, therefore, the Bootstrap Loader is used to load the Absolute Loader into memory. It occupies locations

XX7474 through XX7743, and its starting address is XX7500. The Absolute Loader program is 7254 words long,
and is loaded adjacent to the Bootstrap Loader.
4.8.2.2

Loading Absolute Tapes — Any paper-tape punched in absolute format is referred to as an absolute tape,
and is loaded into memory using the Absolute Loader. When using the Absolute Loader, there are two methods of
loading available: normal and relocated.

A normal load occurs when the data is loaded and placed in memory according to the load addresses on the object
tape. It is specified by setting bit 0 of the Switch Register to 0 immediately before starting the load.

4-10

There are two types of relocated loads:
a.

Loading to continue from where the loader left off after the previous load. This type is used, when the
object program being loaded is contained on more than one tape. It is specified by setting the Switch
Register to 000001 immediately before starting the load.

Loading into a specific area of memory. This is normally used when loading position independent
programs. A position independent program is one that can be loaded and run anywhere in available
memory. The program is written using the position independent instruction format. The type of load is
specified by setting the Switch Register to the load address and adding 1 to it (i.e., setting bit O to 1).
Optional Switch Register settings for the three types of loads are listed below.
Switch Register

Type of Load

Bits 1-14

Bit 0

(ignored)

Relocated - load in

nnnnn

specified area of memory

(specified

Normal
Relocated - continue

loading where left off

address)

The absolute tape may be loaded using either paper-tape reader. The desired reader is specified in the last word of
available memory (XX7776). The input device status word may be changed at any time prior to loading the absolute
tape. With the Absolute Loader in memory, absolute tapes are loaded as explained below:
1.

Set the ENABLE/HALT switch to HALT. To use an input device other than that used for loading the

Absolute Loader, change the address of the device status word (in location XX7776) to reflect the
desired device; i.e., 177560 for the Teletype reader or 177550 for the high-speed reader.

Set the SR to XX7500 and press LOAD ADRS switch.

Set the SR to reflect the desired type of load.

Place the absolute tape in the proper reader with blank leader tape directly over the reader sensors.
Set ENABLE/HALT switch to ENABLE.

Press START switch. The absolute tape will begin passing through the reader station as data is being
loaded into memory.

If the absolute tape does not begin passing through the reader station, the Absolute Loader is not in memory

correctly. Reload the loader and start over at Step 1. If it halts in the middle of the tape, a checksum error occurred
in the last block of data read in.

Normally, the absolute tape will stop passing through the reader station when it encounters the transfer address as
generated by the statement .END, denoting the end of a program. If the system halts after loading, check that the
low byte of RO is O*. If so, the tape is correctly loaded. If not 0, a checksum error has occurred in the block of data
just loaded, indicating that some data was incorrectly loaded. The tape should be reloaded starting at Step 1.

*To read RO, load address 177700 and press EXAM switch.
4-11

4.8.3

Memory Dumps

A Memory Dump program is a system program that enables the contents of all or any specified portion of memory

to be dumped (print or punch) onto the teletype printer and/or punch, line printer, or high speed punch. There are
two dump programs available in the paper-tape software system:
a.

DUMPIT, which dumps the octal representation of the contents of specified portions of memory onto
the teleprinter, low speed punch, high speed punch, or line printer.

DUMPAB, which dumps the absolute binary code of the contents of specified portions of memory onto
the low speed or high speed punch.

Both dump programs are supplied on punched paper tape in bootstrap and absolute binary formats. Paragraph
4.8.1.3 explains how the Absolute Loader is Joaded over the bootstrap tapes. The absolute binary tapes are position

independent and may be loaded and run anywhere in memory as explained in Paragraph 4.8.2.2. DUMPIT and
DUMPAB are very similar in function; they differ primarily in the type of output they produce.

4.8.3.1

Operating Procedures — Neither dump program will punch leader or trailer tape, but DUMPAB will always

punch ten blank frames of tape at the start of each block of data dumped.

The operating procedures for both dump programs follow:
1.

Select the dump program desired and place it in the reader specified by location XX7776 (Paragraph
4.38.1).

If a bootstrap tape is selected, load it using the Bootstrap Loader (Paragraph 4.8.1.2). When the
computer halts, go to Step 4.

If an absolute binary tape is selected, load it using the Absolute Loader (Paragraph 4.8.2.2), relocating as
desired.
Place the proper start address in the Switch Register, press LOAD ADRS and START switches. (The
start addresses are shown in Paragraph 4.8.3.3.)

When the computer halts, enter the address of the desired output device status register in the Switch
Register and press CONT switch (low speed punch and teleprinter = 177564; high speed punch =

177554; line printer = 177514).
5.

When the computer halts, enter in the Switch Register the address of the first byte to be dumped and
press CONT switch. This address must be even when using DUMPIT.

When the computer halts again, enter in the Switch Register the address of the last byte to be dumped
and press CONT switch. When using the low speed punch, set the punch to ON before pressing CONT

switch.
7.

Dumping will now proceed on the selected output device.

When dumping is complete, the computer will halt.

If further dumping is desired, proceed to Step 5. It is not necessary to respecify the output device address except
when changing to another output device. In such a case, proceed to the second paragraph of Step 3 to restart.
If DUMPAB is being used, a transfer block must be generated as described below. If a tape read by the Absolute
Loader does not have a transfer block, the loader will wait in an input loop. In such a case, the program may be

4-12

manually initiated, however, this practice is not recommended because there is no guarantee that load errors will not

occur when the end of the tape is read.
The transfer block is generated by performing Step 5 with the transfer address in the Switch Register, and Step 6
with the transfer address minus 1 in the Switch Register. If the tape is not to be self-starting, an odd-numbered

address must be specified in Step 5 (e.g., 000001).
The dump programs use all eight general registers and do not restore their original contents. Therefore, after a dump,
the general registers should be loaded as necessary prior to their use by subsequent programs.

4.8.3.2

Output Formats — The octal output from DUMPIT is in the following format:

XXXXCCYYYYYY

YYYYYY

Where XXXXXX is the address of the first location printed or punched, and YYYYYY are words of data, the first of
which starts at location XXXXXX. This is the format for every line of output. There are only eight words of data
per line, but there can be as many lines as needed to complete the dump.

The output from DUMPARB is in absolute binary.

4.8.3.3

Storage Maps — The DUMPIT program is 87 words long. When used in absolute format, the storage map is

as shown in Figure 4-4.

XX7776
Bootstrap Loader
XX7744

Absolute Loader

XX7500

XX7474

Loader Stack Space

XXXXXX+256

DUMPIT
XXXXXX

Two-word Stack Space

XXXXXX= desired load address = start address
Figure 4-4

Absolute Format

When used in bootstrap format, the storage map is as shown in Figure 4-5.

XX7776
Bootstrap Loader

XX7744

DUMPIT
start

address = XX7440
XX7473

Two-word Stack Space

Figure 4-5

Bootstrap Format

4-14

PART 2
KD11-B PROCESSOR

Part 2 has been revised to reflect hardware changes to the KD11-B Processor. Chapter
5 has been revised but Chapter 6 remains as it was in the earlier edition. Chapters 7, 8,
9, and 10 have been deleted from this manual. Current versions of Chapters 7, 8, 9,

and

are

available

the

KDI1-B

Processor

Maintenance

DEC-11-HKDBB-A-D. The former chapter structure of Part 2 was:

Chapter 5 — Processor General Description
Chapter 6 — Instruction Set
Chapter 7 — Console Description
Chapter 8 — KD11-B Detailed Description

Chapter 9 —~ Microprogram Control
Chapter 10 — KD11-B and Console Maintenance

Manual,

CHAPTER 5

PROCESSOR GENERAL DESCRIPTION

5.1

KD11-B DEFINITION

Physically the KD11-B consists of two 8-1/2 by 15 inch modules, the M7260 and M7261. Each module contains
approximately 100 dual in-line integrated circuits of the 14-, 16-, and 24-pin variety. There is one MOS-LSI 40-pin

integrated circuit used on the M7260. This MOS circuit is the serial communication line (SCL) receiver and
transmitter. All other integrated circuits used on the KD11-B are bipolar. The connections between the two modules
are made through the backplane.

The KD11-B programmer’s console interfaces to the processor via a 40-conductor cable that is attached to the
M7260

module.

The

console

described

detail

the

KDI11-B

Processor

Maintenance

Manual,

DEC-11-HKDBB-A-D.

5.2

KDI11-B AND THE UNIBUS

The processor is interfaced with memory and most peripherals by the Unibus as shown in Figure 5-1. The KD11-B is
capable of arbitrating bus requests (BR) and non-processor requests (NPR) as they are asserted onto the Unibus by
the connected peripherals.

The line clock and the serial communications line (SCL) do not interface with the processor via the Unibus in the
traditional PDP-11 sense; both connect to the KD11-B through an internal bus. For most programs, these peripherals
are indistinguishable from their appearance on other PDP-11 implementations. In other words, the program may
access the line clock and the serial communications line by using instructions that move data to and from the Unibus

address specified for these peripheral options in the PDP-11 Peripherals Handbook. These Unibus addresses are as

opo
s

follows:

Line Clock Status Register Address = 177546
SCL Receiver Status Register Address = 177560
SCL Receiver Buffer Register Address = 177562
SCL Transmitter Status Register Address = 177564

SCL Transmitter Buffer Register Address = 177566

It is not possible for the line clock and SCL to be addressed by any devices attached to the Unibus other than the
KD11-B processor. For example, it is not possible to perform NPRs to the SCL from another peripheral such as the
DECtape unit.

The SCL input/output is available for connection to such devices as the LA30 DECwriter, the VT05 CRT Terminal,
or the Model 33 ASR Teletype. These SCL input/output signals interface at the fingers of the processor’s M7260
module via a Berg connector located on the rear of the computer chassis as shown in Chapter 3.

5-1

(

CONSOLE )

scL

LINE
cLoCK

Ei““"" KD11-B
PR

INTERNAL

BUS

MEMORY

PERIPHERAL

(ANALOG/

DIGITAL
CONVERTER)

B
3

I
!
]

I
|

PERIPHERAL

(DISK)

|\ /

Figure 5-1
5.3

[E R ETY

KD11-B With Interconnections to Memory and Peripherals

KDI11-B AS AN INSTRUCTION INTERPRETER

Figure 5-2 illustrates the division of the KD11-B into Unibus control and instruction interpreter. This division is
significant

because

the

KDI11-B the Unibus control is implemented as a block of logic that is relatively

independent of the rest of the processor.

INSTRUCTION

UNIBUS

INTERPRETER

CONTROL

UNIBUS

VAN

4
11-1213

Figure 5-2

KD11-B Processor Block Diagram

In Figure 5-3, the instruction interpreter is further divided into a data path (DP), a data path control (DPC), and a

control store (CS). Whenever power is applied to the computer, the DPC continually executes a program that is
stored in the CS. All instructions, interrupt sequences, and console functions are performed by the DPC when
executing a microprogram contained in the CS. The Unibus control and the DP are facilities used by the DPC in the

course of performing its tasks. The program contained in the CS is referred to as the microprogram.

5-2

CONTROL
STORE
(cs)

(——

DATA

PATH

CONTROL
(DPC)

(——

DATA
PATH

(DP)

i-12t4

Figure 5-3

Instruction Interpreter Block Diagram

5.4 MEDIUM AND LARGE SCALE INTEGRATED CIRCUIT REPRESENTATIONS

MSI and LSI integrated circuits (Figure 5-4) are represented in the KD11-B print set as rectangles with inputs on the
left and outputs on the right. Control lines often enter the IC from the bottom. The functional descriptions of the
KD11-B MSI and LSI ICs are contained in Appendix A.

CONTROL OUTPUTS

—A-

A=8

COUT

(18d 83

t3 p13)

194 a3

20d B2

INPUTS <

21q A2

74181

22d 81

EO27

D11

> OUTPUTS

ALU

23d a1

o1d 8o

P10

fo P 09

L02d A0

Cin

BENEE

v—

CONTROL

INPUTS
11- 1197

Figure 5-4

5.4.1

ALU, MSI Circuit Type 74181 Representation

Microprogram Documentation

The microprogram is documented at three levels in the print set. The first level is the microprogram flow listing
(K-MP-KDN-B-1), at this level, the microprogram is described in terms of register transfers. The microprogram
symbolic listing (K-MP-KD11-B-2) shows how the microprogram accomplishes each step. (References in the
microprogram listing are symbolic; e.g., scratch pad address = R7.) The binary equivalent is shown in the
microprogram binary listing (K-MP-KD11-B-3), which actually shows the binary contents of each word of the

microprogram. The microprogram cross reference listing lists the microprogram by address (K-MP-KD1 1-B4). The
microprogram is discussed in detail in the KD11-B Processor Maintenance Manual, DEC-11-HKDBB-A-D.

5-3

5.4.2

Read-Only Memory (ROM) Maps

Figure 5-5 is a typical ROM map listing. ROM map listings for the ROMs used in the KD11-B processor are provided

in the Engineering Drawing Manual (K-RL-M7260-8 and K-RL-M7261-8).

/¢
t/(

zv8

(PIN

8Y7

*t/(

(PIN

=Y6

tte/l

ttere/(

treeer/(
OCTAL

DECIMAL

ADDRESS

200

221

EpCBA
2p20Y

ggs

Aga19

SGZI;

ees

226
enz
212

np119
"g111
fq1200

212

21201

P13

21919

211

2417

22¢
21

(AR R RRE

DATA

LCLK ,TRANOUT
[CLK .TRANOUT,B4R
GR<RB:R17> ,TRANOUY

277
177

11111111

111

21111111

10020
12201

1212111
11211111

377

177

11114111

$77

127
337

SWR

TKS
TKS

,TRANOUT BA177560
,TRANOUT,BAR
,TRANOUT BAz177564

21100111

147

TPS

224
@25
@26

1100
1p121
ig11¥
1g111

357

TPS
TKB

20
21
22
23

1i1p1111

234

1311111
11211111
l1p1111
111g1111

12111114

11219

238

11110

g37

11111

137
$37

TKB

157
357

TPB
TPB

$77

11171111

$77

11111111
1111111
11111111

377
377
377

11111111

s TRANOUT ,BAR
.TRANOUT BA2177562
.TRANOUT ,BAR

,TRANOUT BAs177566
,TRANOUT,BAR

377

11111118
11111111

377

$77

tetr?

tert/(
rer/0

*o/{
/0

/¢

A(PIN
BIPIN

C(PIN
D(PIN

ECPIN

#1Q)
#11)

#12)
#13)

#14)

CONA

BA=1777XX

SWR .T::ng}.SAR177S7z

10719

11211
111009
11101

377

12211

377

27
28
29

,TRAN

GRSRO:R17> s TRANOUT ,BAR
00D BYTE (LCLK/YK/TP)

232

PSW ,TRAN 08;.S:R177776

g22

232
034
35

PSW

173
$77
275

3110;

PSW

377

11111111

11200

LOAD

377

19111111
Q11111131

11001

WRITE

PSW

176

CONG

PSW

CLK

377

2302

21111110

111111114

16
17

LOAD

MODEM

377

01111011
11111111
29111121

21111

LOAD

11111111

21109

TRANSMIT

377

11191111

21211

#1)

OCTAL

(PIN

11111114

2g101

RECEIVE

CONG

trrsetee

11111112

719

)
7
8

SY1

CONA

#2)

SYNC

ADDR

CONA

#3)

(PIN

11111111

Gpo01

222

e14
giz

aY2

TRAN

REG

CONA

#4)

(PIN

INT

CONA

#5)

(PIN

vY3

trrrrrr/t

CONA

#6)

(PIN

av4

CONA

#7)

(PIN

=y5

tree/(

#9)

Y2
Y1

QF
OF

TRAN
FO25

Fp2o
FO25

FR25

Figure 5-5 EO68 ROM Map Example

OUT

CHAPTER 6
INSTRUCTION SET

6.1

INTRODUCTION

The KD11-B is defined by its instruction set. The sequences of processor operations are selected according to the
instruction decoding. This chapter contains tables that describe the PDP-11 instructions and instruction set
addressing modes. Instruction set differences between the PDP-1 1/05, 11/10 and PDP-11/20 are listed in Table 6-8.
6.2
6.2.1

ADDRESSING MODES
Introduction

Data stored in memory must be accessed and manipulated. Data handling is specified by a PDP-11 instruction MoV,

ADD, etc.) which usually indicates:

The function (operation code).

A general purpose register for locating the source operand and/or a general purpose register for locating

¢.

Anaddressing mode [to specify how the selected register(s) is to be used].

the destination operand.

A large portion of the data handled by a computer is usually structured in character strings, arrays, lists, etc. Thus,
the PDP-11 is designed to handle structured data efficiently and flexibly. The general registers may be used with an
instruction in any of the following ways:

As accumulators. The data to be manipulated resides within the register.

As pointers. The contents of the register are the address of the operand, rather than the operand itself.

¢.

As pointers that automatically step through core locations. Automatically stepping forward through
consecutive core locations is termed autoincrement addressing; automatically stepping backwards is
termed autodecrement addressing. These modes are particularly useful for processing tabular data.

As index registers. In this instance, the contents of the register and the word following the instruction
are summed to produce the address of the operand. This allows easy access to variable entries in a list.

PDP-11s also have instruction addressing mode combinations that facilitate temporary data storage structures for
convenient handling of data that must be frequently accessed. This is known as the “stack”.

6-1

In the PDP-11 any register can be used as a stack pointer under program control; however, certain instructions
associated with subroutine linkage and interrupt service automatically use register 6 as a hardware stack
pointer. For
this reason, R6 is frequently referred to as the SP.

Two types of instructions utilize the addressing modes: single operand and double operand. Figure 6-1 shows
the
formats of these two types of instructions. The addressing modes are listed in Table 6-1.
6.2.2

Instruction Timing

The PDP-11 is an asynchronous processor in which, in many cases, memory and processor operations are overlapped.
The execution time for an instruction is the sum of a basic instruction time and the time to determine and
fetch the
source and/or destination operands. Table 6-2 shows the addressing times required for the various modes
of
addressing source and destination operands. All times stated are subject to +10% variation.

k.2
T

MODE
1

OP CODE

k.2
2

DESTINATION

ADDRESS FIELD

* =SPECIFIES DIRECT OR INDIRECT ADDRESS
HOW REGISTER WILL BE USED

#% =SPECIFIES

#ux = SPECIFIES ONE OF 8 GENERAL

PURPOSE REGISTERS

(a)

OP CODE
1

MODE

)

—

2.1

Rn
8

MODE

ki1

2
Y

SOURCE ADDRESS FIELD

Rn
0

DESTINATION ADDRESS FIELD

% =DIRECT/DEFERRED BIT FOR SOURCE AND DESTINATION ADDRESS
#»= SPECIFIES HOW SELECTED REGISTERS ARE TO BE USED

#x% = SPECIFIES

GENERAL

(b)
1-1227

Figure 6-1

6.3

Addressing Mode Instruction Formats

PDP-11/05 INSTRUCTIONS

instructions can be divided into five groupings:
Single Operand Instructions (shifts, multiple precision instructions, rotates)

The PDP-11

Program Control Instructions (branches, subroutines, traps)

Double Operand Instructions (arithmetic and logical instructions)

Operate Group Instructions (processor control operations)
Condition Codes Operators (processor status word bit instructions)

Tables 6-3 through 6-7 list each instruction, including byte instructions for the respective instruction groups. Figure
6-2 shows the six different instruction formats of the instruction set, and the individual instructions in
each format.

6.4

INSTRUCTION SET DIFFERENCES

Table 6-8 lists the differences between the PDP-11/20 and PDP-11/05 instruction sets.

Table 6-1

Addressing Modes

Binary

Name

Code

Assembler

Function

Syntax

DIRECT MODES

000

010

Autoincrement

(Rn) +

100

Autodecrement

-(Rn)

110

Index

X(Rn)

mented after reference.

contains address of operand.

Value X (stored in a word following the instruction) is added
to (Rn) to produce address of operand. Neither X nor (Rn)
are modified.

DEFERRED MODES

001

@Rn

011

Autoincrement

@Rn) +

101

Deferred

Autodecrement

or (Rn)

address of the operand, then incremented (always by two;
even for byte instructions).

@ -(Rn)

structions) and then used as a pointer to a word containing
the address of the operand.

111

Index Deferred

Value X (stored in a word following the instruction) and (Rn)

@X(Rn)

are added and the sum is used as a pointer to a word contain-

ing the address of the operand. Neither X nor (Rn) are
modified.

PC ADDRESSING

010

Immediate

Operand follows instruction.

011

Absolute

@#HA

Absolute address follows instruction.

110

Relative

Address of A, relative to the instruction, follows the instruction.

111

Relative Deferred

Address of location containing address of A, relative to the

Rn = Register

X, n, A = next program counter (PC) word (constant)

instruction, follows the instruction.

Table 6-2
Addressing Times

Addressing Format

Mode

Description

Time (us)

Symbolic

Source*

Destination**

@R or (R)

Autoincrement

(R) +

0.9

Autoincrement

@R) +

Autodecrement

- (R)

0.9

Autodecrement

@- (R)

2.4

Deferred
4

Deferred

Indexed

+ X (R)

Index Deferred

@+ X (R)

4.7

or @ (R)
* For Source time, add 1.3 us for odd byte addressing.
** For destination time, modify as follows:
a. Add 1.3 us for odd byte addressing with a non-modifying
instruction.

b. Add 2.4 us for odd byte addressing with a modifying
instruction.

“~

c. Subtract 1.2 us for a non-modifying instruction.

)

Table 6-3

Single Operand Instructions

Mnemonic/

Instruction Time

OP Code

CLR

0050DD*

CLRB

1050DD

Operation

(dst)Jr <0

34 us

N: cleared
Z: set

Contents of specified destination are replaced with zeroes.

V: cleared

34us

COM
COMB

Description

Condition Codes

C: cleared

0051DD
1051DD

(dst) < n (dst)

N: set if most significant
bit of result is 0

Z: setif resultisO

Replaces the contents of the destination address by their
logical complement (each bit equal to 0 set and each bit equal
to 1 cleared).

V: cleared
C: set

INC

INCB
34 pus

DEC

DECB
34us

NEG
NEGB
3.4 us

0052DD

1052DD

(dst) < (dst) + 1

N: set if result is less than O
Z: setifresultisO
V: set if (dst) was 077777

Add 1 to the contents of the destination.

C: not effected

0053DD

1053DD

(dst) < (dst) -1

N: set if result is less than O

Z:. setif resultis O

Subtract 1 from the contents of the destination.

V. set if (dst) was 100000
C: not effected

0054DD
1054DD

(dst) < - (dst)

N: set if result is less than O
Z: setifresultisO

Replaces the contents of the destination address by its 2’s complement. Note that 100000 is replaced by itself.

V: set if result is 100000
C: cleared if result is 0

ADC
ADCB
34 pus

0055DD
1055DD

(dst) « (dst) + C

Adds the contents of the C-bit into the destination. This permits
N: set if result is less than 0
carry from the addition of the Jow order words/bytes to be
the
Z: setifresultisO
into the high order resuit.
carried
|
and
V: setif (dst) is 077777
Cisl

C: set if (dst) is 177777 and
Cisl

Table 6-3 (Cont)
Single Operand Instructions

Mnemonic/

Instruction Time

OP Code

Operation

Condition Codes

Description

SBC

0056DD

(dst) < (dst) C

N: set if result is less than O

Subtracts the contents of the C-bit from the destination. This

SBCB

1056DD

Z: sctifresultisO

permits the carry from the subtraction of the low order words/

bytes to be subtracted from the high order part of the result.

34 pus

set if (dst) was 100000

C: cleared if (dst)is 0 and C
is 1

TST

0057DD

TSTB

1057DD

(dst) < (dst)

34us

N: set if result is less than 0

Sets the condition codes N and Z according to the contents of

Z: setifresultis O

the destination address.

cleared

C: cleared

ROR

0060DD

(dst) < (dst)

N: set if high order bit of

Rotates all bits of the destination right one place. The low

RORB

rotate right

the result is set

order bit is loaded into the C-bit and the previous contents of

34 us

one place.

Z: set if all bits of result

the C-bit are loaded into the high order bit of the destination.

are 0

V: loaded with the exclusive-

OR of the N-bit and the

C-bit as set by ROR
ROL

0061DD

(dst) < (dst)

ROLB

1061DD

rotate left

the result word is set

order bit is loaded into the C-bit of the status word and the

one place.

(result < 0); cleared

previous contents of the C-bit are loaded into the low order

otherwise

bit of the destination.

34 us

N: set if the high order bit of } Rotate all bits of the destination left one place. The high

Z: set if all bits of the
result word = Q; cleared

otherwise
V: loaded with the exclusive-

OR of the N-bit and C-bit

(as set by the completion
of the rotate operation)
C: loaded with the high order

bit of the destination

)

Table 6-3 (Cont)

Single Operand Instructions

Mnemonic/

Instruction Time

OP Code

ASR

0062DD

ASRB
34 us

1062DD

Operation

(dst) < (dst)

shifted one
place to the
right.

Condition Codes

. set if the high order bit

of the result is set
(result < 0); cleared
otherwise

Description

Shifts all bits of the destination right one place. The high

order bit is replicated. The C-bit is loaded from the low order
bit of the destination. ASR performs signed division of the
destination by two.

. set if the result = 0;
cleared otherwise
: loaded from the exclusive-

OR of the N-bit and C-bit
(as set by the completion
of the shift operation).
L9

. loaded from low order bit
of the destination

ASL
ASLB
34 us

0063DD
1063DD

(dst) « (dst)
shifted one
place to the left.

. set if high order bit of the | Shifts all bits of the destination left one place. The low order
(result < 0); cleared
bit is loaded with a 0. The C-bit of the status word is loaded
otherwise
from the high order bit of the destination. ASL performs a

. set if the result = 0; cleared | signed multiplication of the destination by 2 with overflow
indication.
otherwise
. loaded with the exclusive-

OR of the N-bit and C-bit
and C-bit (as set by the
completion of the shift
operation)
. loaded with the high order
bit of the destination

Table 6-3 (Cont)

Single Operand Instructions

Mnemonic/
Instruction Time

OP Code

JMP

0001DD

Operation

PC « (dst)

Condition Codes
Not effected.

1.0 us

Description

JMP provides more flexible program branching than provided
with the branch instruction. Control may be transferred to any

location in memory (no range limitation) and can be accomplished with the ful] flexibility of the addressing modes. with
the exception of register mode 0. Execution of a jump with
mode 0 will cause an illegal instruction condition. (Program
control cannot be transferred to a register.) Register deferred

mode is legal and will cause program control to be transferred
to the address held in the specified register. Note that instructions are word data and must therefore be fetched from
an even numbered address. A boundary error trap condition
will result when the processor attempts to fetch an instruction

from an odd address.

SWAB

0003DD

4.3 us

Byte 1/Byte O

N: set if high order bit of

Byte 0/Byte 1

low order byte (bit 7)

of result is set, cleared
otherwise

Z: setif low order byte

of result = 0, cleared
otherwise
V: cleared

C. cleared

* DD = destination (address mode and register)
t (dst) = destination contents

Exchanges high order byte and low order byte of the destination
word (destination must be a word address).

{

Table 6-4

Double Operand Instructions

Mnemonic/

Instruction Time

OP Code

Operation

MOV

01SSDD*

(dst) < (src) ¥

MOVB
3.7 us

11SSDD

Condition Codes

Description

. set if (src) < 0; cleared

Word: Moves the source operand to the destination location.

. set if (sr¢) = 0; cleared

operand is not effected.

otherwise

3.1 us mode O

. cleared

. not effected

CMP
CMPB
3.7 us

02SSDD
12SSDD

(src) ~ (dst)
[in detail,
(src) +~
(dst) + 1]

The previous contents of the destination are lost. The source

Byte: Same as MOV. The MOVB to a resistor (unique among
byte instructions) extends the most significant bit of the low
order byte (sign extension). Otherwise. MOVB operates on

bytes exactly as MOV operates on words.

. set if result <0, cleared
otherwise
. set if result = 0; cleared

Compares the source and destination operands and sets the
condition codes. which may then be used for arithmetic and
logical conditional branches. Both operands are uneffected.

. set if there was arithmetic
overflow, i.e., operands

customarily followed by a conditional branch instruction. Note
that unlike the subtract instruction the order of operation is

were of opposite signs

(src) - (dst), not (dst) - (src).

otherwise

and the sign of the destination was the same

as the sign of the result;
cleared otherwise
. cleared if there was a

carry from the most sig-

nificant bit of the result;
set otherwise

The only action is to set the condition codes. The compare is

Table 64 (Cont)
Double Operand Instructions

Mnemonic/

Instruction Time

OP Code

BIT

03SSDD

BITB

13SSDD

Operation

Condition Codes

(src) A\ (dst)

: set if high order bit of
result set: cleared other-

3.7 us

wise

. set if result = 0; cleared

otherwise

BIC

04SSDD

(dst) < ~ (src)

BICB

14SSDD

A\ (dst)

cleared

not effected

. set if high order bit of

3.7 us

Description
Performs logical AND comparison of the source and destination
operands and modifies condition codes accordingly. Neither
the source nor destination operands are effected. The BIT in-

struction may be used to test whether any of the corresponding

bits that are set in the destination are clear in the source.

Clears each bit in the destination that corresponds to a set bit

result sct, cleared other-

in the source. The original contents of the destination are lost.

wise

The contents of the source are uncffected.

. set if result = 0, cleared

01-9

otherwise
: cleared
.

BIS

05SSDD

(dst) « (src)

BISB

158SDD

A\ (dst)

not effected

: set if high order bit of

3.7 us

Performs inclusive-OR operation between the source and des-

result set: cleared other-

tination operands and leaves the result at the destination

wise

address; i.e., corresponding bits set in the destination. The

o set if result = 0; cleared

contents of the destination are lost.

otherwise
: cleared

ADD

06SSDD

(dst) < (sr¢)
+ (dst)

not effected

. set if result O; cleared
otherwise
. set if result = Q; cleared

otherwise

Adds the source operand to the destination operand and stores
the result at the destination address. The original contents of
the destination are lost. The contents of the source are not

effected. Two's complement addition is performed.

Table 6-4 (Cont)

Double Operand Instructions
Mnemonic/
Instruction Time

Operation

OP Code

Description

Condition Codes

. set if there was arithmetic

ADD (Cont)

overflow as a result of the
operation; that is both

operands were of the same
sign and the result was of
the opposite sign; cleared
otherwise

. set if there was a carry from

the most significant bit of
the result cleared other-

11-9

wisc

SUB

16SSDD

3.7 us

(dst) < (dst) -

(sr¢) in detail,

(dst) + ~ (src)
+ 1 (dst)

. set if result < 0; cleared
otherwise

. set if result = 0; cleared
otherwise
. set if there was arithmetic

overflow as a result of
the operation. i.e., if
operands were of opposite signs and the sign

of the source was the

same as the sign of the
result, cleared otherwise
: cleared if there was a
carry from the most

significant bit of the
result; set otherwise

* 8§ = source (address mode and register)
1 (src) = source contents

Subtracts the source operand from the destination operand and

leaves the result at the destination address. The original contents
of the destination are lost. The contents of the source are not
effected. In double precision arithmetic, the C-bit, when set,
indicates a borrow.

Table 6-5
Program Control Instructions

Mnemonic/
Instruction Time

OP Code

Operation

000400

PC«PC+

2.5 us

xxxt

(2 X offset)

Condition Codes
Uneffected

Description
Provides a way of transferring program control within a range

of- 128 to +127 words with a one word instruction. It is an
unconditional branch.

BNE

001000

PC«PC+

1.9 us no branch

XXX

(2 X offset)

2.5 ps branch

Uneffected

Tests the state of the Z-bit and causes a branch if the Z-bit is

is clear. BNE is the complementary operation to BEQ. It is

ifZ=0

used to test inequality following a CMP, to test that some bits

set in the destination were also in the source, following a BIT,

and generally, to test that the result of the previous operation
(A%

was not 0.

BEQ

001400

PC «<PC +

1.9 us no branch

XXX

(2 X offset) if

2.5 us branch

Uneffected

Z=1

Tests the state of the Z-bit and causes a branch if Z is set. As
an example, it is used to test equality following a CMP operation, to test that no bits set in the destination were also set in
the source following a BIT operation, and generally, to test

that the result of the previous operation was 0.

BGE

002000

PC «~PC+

1.9 us no branch

XXX

(2 X offset) if

2.5 us branch

NvV=0

Uneffected

Causes a branch if N and V are either both clear or both set.

BGE is the complementary operation to BLT. Thus. BGE
always causes a branch when it follows an operation that

caused addition to two positive numbers. BGE also causes a

branch on a 0 result.

‘

Table 6-5 (Cont)
Program Control Instructions

Mnemonic/

Instruction Time

OP Code

Operation

BLT

002400

PC+«PC+

1.9 us no branch
2.5 us branch

XXX

(2 X offset) if
NV=1l

Condition Codes

Uneffected

Description

Causes a branch if the exclusive-OR of the N- and V-bits are 1.
Thus, BLT always branches following an operation that added
two negative numbers, even if overflow occurred. In particular,
BLT always causes a branch if it follows a CMP instruction
operating on a negative source and a positive destination (even
if overflow occurred). Further, BLT never causes a branch when

it follows a CMP instruction operating on a positive source and
negative destination. BLT does not cause a branch if the result

£1-9

of the previous operation was 0 (without overflow).

BGT

003000

PC<PC+

1.9 us no branch
2.5 us branch

XXX

(2 X offset)
ifZv(N&

Uneffected

Operation of BGT is similar to BGE, except BGT does not
cause a branch on a 0 result.

V)=0

BLE
1.9 us no branch

003400
XXX

2.5 us branch

PC<PC+
(2 X offset) if

Uneffected

Operation is similar to BLT but in addition will cause a branch
if the result of the previous operation was 0.

Uneffected

Tests the state of the N-bit and causes a branch if N is clear.
BPL is the complementary operation of BML

Uneffected

Tests the state of the N-bit and causes a branch if N is set. It is

Zv (N¥V)
=1

BPL
1.9 us no branch

100000
XXX

2.5 us branch

PC<PC+
(2 X offset) if
N=0

BMI

100400

PC < PC +

1.9 us no branch

XXX

(2 X offset) if

used to test the sign (most significant bit) of the result of the

N=1

previous operation.

2.5 us branch

Table 6-5 (Cont)
Program Control Instructions

Mnemonic/
Instruction Time

OP Code

Operation

BHI

101000

PC<PC+

1.9 us no branch

XXX

(2 X offset) if

2.5 us branch

Condition Codes

Uneffected

Description

Causes a branch if the previous operation causes neither a carry
nor a 0 result. This will happen in comparison (CMP) operations
as long as the source has a higher unsigned value than the

C=0

destination.

BLOS

101400

PC<PC +

1.9 us no branch

XXX

(2 X offset) if

2.5 us branch

Uneffected

Causes a branch if the previous operation caused either a carry

or a 0 result. BLOS is the complementary operation to BHI.

CvZ=1

The branch occurs in comparison operations as long as the
source is equal to or has a Jower unsigned value than the

destination. Comparison of unsigned values with the CMP
instruction to be tested for “higher or sameTM and “higher” by

v1-9

a simple test of the C-bit.

BVC

102000

PC«PC +

1.9 us no branch

XXX

(2 X offsct) if

2.5 us branch

Uneffected

Tests the state of the V-bit and causes a branch if the V-bit is
clear. BVC is complementary operation to BVS.

V=0

BVS

102400

PC«<PC+

1.9 us no branch

XXX

(2 X offset) if

2.5 us branch

Uneffected

V-bit is set. BVS is used to detect arithmetic overflow in the

V=1

BCC

103000

PC «PC +

BHIS

XXX

(2 X offset) if

1.9 us no branch

Tests the state of V-bit (overflow) and causes a branch if the

previous operation.

Uneffected

Tests the state of the C-bit and causes a branch if C is clear.
BCC is the complementary operation to BCS.

C=0

2.5 us branch

BCS

103400

PC<PC+

BLO

XXX

(2 X offset) if

1.9 us no branch

Uneffected

Tests the state of the C-bit and causes a branch if C is set. It is

used to test for a carry in the result of a previous operation.

C=1

2.5 us branch

L §

)

Table 6-5 (Cont)
Program Control Instruction

Mnemonic/

Instruction Time

OP Code

Operation

JRS
3.8 us

004RDD

(tmp) < (dst)
(tmp is an inter-

Condition Codes

Uneffected

In execution of the JSR, the old contents of the specified
register (the linkage pointer) are automatically pushed onto

the processor stack and new linkage information placed in
the register. Thus, subroutines nested within subroutines to any
depth may all be called with the same linkage register. There

nal processor
register)
{ (SP) < reg

(push reg contents onto processor stack)
reg < PC PC
holds location following JSR; this
address PC «
(tmp), now put in
(reg)

S1-9

Description

is no need either to plan the maximum depth at which any
particular subroutine will be called or to include instructions
in each routine to save and restore the linkage pointer. Further,
since all linkages are saved in a re-entrant manner on the processor stack. execution of a subroutine may be interrupted,
and the same subroutine re-entered and executed by an interrupt service routine. Execution of the initial subroutine can
then be resumed when other requests are satisfied. This process (called nesting) can proceed to any level.
JSR PC, dst is a special case of the PDP-11 subroutine call
suitable for subroutine calls that transmit parameters.

RTS
3.8 us

00020R

PC < (reg)
(reg) <« SP t

Uneffected

Loads contents of register into PC and pops the top element
of the processor stack into the specified register.
Return from a non-re-entrant subroutine is typically made
through the same register that was used in its call. Thus. a
subroutine called with a JSR PC, dst exits with an RTS PC,
and a subroutine called with a JSR RS, dst may pick up

parameters with addressing modes (R5) +, X (RS), or @X (RS)
and finally exit, with an RTS R5.

Table 6-5 (Cont)

Program Control Instructions

Mnemonic/
Instruction Time

OP Code

(No mnemonic)

000003

8.2 us

10T

000004

8.2 us

Operation

Condition Codes

Description

1 (SP) < PS

N: loaded from trap vector

{ (SP) « PC

Performs a trap sequence with a trap vector address of 14. Used

Z: loaded from trap vector

PC « (14)

to call debugging aids. The user is cautioned against employing

V: loaded from trap vector

PS < (16)

code 000003 in programs run under these debugging aids.

C. loaded from trap vector

{ (SP) < PS

N: loaded from trap vector

1 (SP) < PC

Z: loaded from trap vector

PC « (20)

to call the 1/0 executive routine I0X in the paper-tape software

C: loaded from trap vector

system, and for error reporting in the disk operating system.

PS < (22)

EMT

104000

91-9

8.2 us

Performs a trap sequence with a trap vector address of 20. Used

| (SP) < PS

N: loaded from trap vector

All operation codes from 104000 to 104377 are EMT instruc-

1 (SP)«<PC

Z: loaded from trap vector

tions and may be used to transmit information to the emulating

PC < (30)

V: loaded from trap vector

routine (e.g., function to be performed). The trap vector for

PS < (32)

C: loaded from trap vector

EMT is at address 30; the new central processor status (PS) is

taken from the word at address 32.
CAUTION

EMT is used frequently by DEC system software and
is therefore not recommended for general use.

TRAP

104400 to

| (SP) « PS

N: loaded from trap vector

82 us

104777

I (SP) <« PC

Z: loaded from trap vector

PC « (34)

V: loaded from trap vector

PS < (36)

C: loaded from trap vector

Operation codes from 104400 to 104777 are TRAP instructions
TRAPs and EMTs are identical in operation, except that the
trap vector for TRAP is at address 34.
NOTE

Since DEC software makes frequent use of EMT, the

TRAP instruction is recommended for general use.
NOTE: Condition Codes are uneffected by these instructions

txxx = offset, 8 bits (0-7) of instruction format
R = register (linkage pointer)

)

Table 6-6

Operate Group Instructions

Mnemonic/

Instruction Time

OP Code

HALT
1.8 us

000000

WAIT
1.8 us

000001

RTI
4.4 us

000002

Operation

Condition Codes

Not effected

Description

Causes the processor operation to cease. The console is given
control of the processor. The console data lights display the

address of the HALT instruction plus two. Transfers on the
Unibus are terminated immediately. The PC points to the next
instruction to be executed. Pressing the CON key on the console
causes processor operation to resume. No INIT signal is given.

Not effected

Provides a way for the processor to relinquish use of the bus
while it waits for an external interrupt. Having been given a

L1-9

WAIT command, the processor will not compete for bus by
fetching instructions or operands from memory. This permits
higher transfer rates between device and memory, since no
processor induced latencies will be encountered by bus requests from the device. In WAIT, as in all instructions, the PC
points to the next instruction following the WAIT operation.
Thus, when an interrupt causes the PC and PS to be pushed onto
the stack, the address of the next instruction following the
WAIT is saved. The exit from the interrupt routine (i.e., execution of an RTI instruction) will cause resumption of the interrupted process at the instruction following the WAIT.

PC (SP)
PSW (SP)

N: loaded from processor stack
Z: loaded from processor stack

Used to exit from an interrupt or trap service routine. The PC
and PSW are restored (popped) from the processor stack. If a

trace trap is pending, the first instruction after the RTI will be

executed prior to the next T trap.

V: loaded from processor stack

C: loaded from pro-

cessor stack

RESET
20 ms

000005

PC (SP)

PSW (SP)

Not effected

Sends INIT on the Unibus for 20 ms. All devices on the Unibus

are reset to their state at power-up.

Table 6-7
Condition Code Operators

Mnemonic/
Instruction Time

OP Code

Description

CLC

000241

Set and clear condition code bits. Selectable combination of

CLZ

000242

these bits may be cleared or set together. Condition code bits

CLN

000244

corresponding to bits in the condition code operator (bits 0—3)

CLV

000250

are modified according to the sense of bit 4, the set/clear bit

Set all CCs

000261

of the operator;i.e., set the bit specified by bit 0, 1,2, or 3 if

Clear all CCs

000262

bit 4 is a 1. Clear corresponding bits if bit 4 = 0.

Vand C

000264

No operation

Clear

000270

No operation

000277

25 pus

000243

000257
000240
000260

1. Single Operand Group (CLR,CLRB,COM,COMB,INC,INCB, DEC,DECB,NEG,NEGB, ADC,ADCB, SBC,SBCB,TST,TSTB,ROR,RORB,
ROL ,ROLB,ASR, ASRB,
ASL, ASLB, JMP, SWAB)

]

)

Code

Dst

]

|
6

]

2.Double Operand Group(BIT,BITB,BIC,BICB,BIS,BISB,ADD,SUB)

Code

]
12

Src

]

)
6

dst

]

}

3.Program Control Group

a.Branch(all branch instructions)

]

OP Code

]

|
8

offset

]

b.Jump To Subroutine (JSR)

]

Src/dst

reg

]

¢.Subroutine Return (RTS)

o]
|

reg

]

d.Traps {break point, IOT,EMT, TRAP)

0P CODE

]

4.Operate Groupe (HALT,WAIT,RTI, RESET)

]

CODE

5.Condition Code Operators(a!l condition code instructions)

0
1

Figurc 6-2 PDP-11 Instruction Formats

6-18

1-1226

Table 6-8

PDP-11 Differences

PDP-11/15,PDP-11/20

PDP-11/05, PDP-11/10

OPR %R, (R) +/-(R), source operand is %R after autoincrement/autodec-

OPR %R, (R) +/-R source operand is %R before autoincrement/autodec-

rement of DEST register only when source and destination registers are
the same.

same or not.

Example:

12700 MOV # 100, R0 100
10020 MOV RO, (R0) + 0 HALT
After Execution:
RO =102

LOC100 =102

61-9

rement of DEST register whether source or destination registers are the

12700 MOV #100, R0 100

10020 MOV RO, (R0) + 0 HALT
After Execution:
RO =102

LOC100 =100

(Note that LOC100 is now 100)

OPR %R, @-(R) /@ (R) + uses R after autodecrement/autoincrement

OPR %R, @-(R) /@ (R) + uses R before autodecrement/autoincrement as

as source operand.

source operand.

MOV PC, LOC stores PC of INST +4 in LOC.

MOV PC, LOC stores PC of INST +2 in LOC.

SWAB does not change V.

Swab clears V.

Program halt displays PC of halt instruction in ADDRESS lights. DATA

Displays next PC.

Byte ops to the odd byte of the PS cause odd address trap.

Byte ops to odd byte of PS do not trap. Not all bits may exist.

The RESET instruction clears the RUN light such that program loops
that make frequent use of RESET may not appear to be running.

RESET does not clear the RUN light.

Power fail during RESET instruction is not recognized until after the
instruction is finished (70 ms). Too late, so don’t use RESET. RESET
instruction consists of 70 ms pause with INIT occurring during first

Power fail immediately ends the RESET instructions and traps if an INIT
is in progress (22 ms). A minimum INIT of 300 ns occurs if the instruction
aborted. Power fail during RESET fetch is fatal: no power-down sequence.

lights display (RO).

20 ms.

Table 6-8 (Cont)
PDP-11 Differences

PDP-11/15, PDP-11/20
The first instruction in an interrupt service routine is guaranteed to bé
executed.

PDP-11/05, PDP-11/10
The first instruction in an interrupt routine will not be executed if another

interrupt occurs at a higher priority level than was assumed by the first

interrupt.

Sequence of internal processor traps, external interrupts, HALT and

WAIT:

BUS ERROR Trap

Odd Address
Data Time Out

0z-9

HALT Instruction for Console Operation

TRAP Instructions: lllegal or Reserved Instructions,
TRTT, IOT, EMT, TRAP

TRACE TRAP: T-bit of processor status

OVFL Trap: Stack overflow
PWR FAIL Trap: Power down
CONSOLE BUS REQUEST: Console operation after HALT switch

UNIBUS BUS REQUEST: Peripheral Request, compared with Processor

Priority - usually an interrupt occurs.

WAIT LOOP: Loop on a WAIT instruction in IR until an interrupt allows
exit.

A CONSOLE BUS REQUEST returns to this loop after being

honored.

Sequences:

BUS ERROR Traps

HALT Instruction
TRAP Instructions

OVFL

Trap

PWR Fail Trap
UNIBUS BUS REQUESTS

CONSOLE STOP

(HALT switch)
WAIT LOOP

PART 3
—

MM11-K AND MM11-.

MEMORIES

Part 3 provides both general and detailed descriptions of the MM11-K and MM11-L

core

memories

that are used in the PDP-11/05 and PDP-11/10. Maintenance

information is also included. The chapters of Part 3 are:

Chapter 11 — MMI11-K and L General Description
Chapter 12 — MM11-K and L Detailed Description
Chapter 13 — Memory Maintenance

CHAPTER 11
MM11-K AND L GENERAL DESCRIPTION

11.1

INTRODUCTION

This chapter provides the user with the theory of operation and logic diagrams necessary to understand and maintain
the MM11-K and MM11-L Read/Write Core Memories. The level of discussion assumes that the reader is familiar
with basic digital computer theory. Both general and detailed descriptions of the core memories are included.

Although memory control signals and data pass through the Unibus, it is beyond the scope of this discussion to
describe the operation of the Unibus. A detailed description of the Unibus is presented in the PDP-11 Peripherals
Handbook.

A complete set of engineering logic drawings is shipped with each core memory. These drawings are bound in a
separate volume entitled MM11-K and L Core Memories, Engineering Drawings. The drawings reflect the latest print
revisions and correspond to the specific memory shipped to the user.
11.2

GENERAL DESCRIPTION

This paragraph provides a physical description and specifications for the memory. The major functional units of each
memory are briefly described, and the basic memory operations are discussed.
11.2.1

Physical Description

The MM11-K provides 4096 (4K) 16-bit words: the MM11-L provides 8192 (8K) 16-bit words. Both configurations
require three standard 8-1/2 inch wide modules: two are hex-height and one is quad-height.
The quad-height module contains the memory stack: module H213 for 4K; and module H214 for 8K. One
hex-height module (G110) contains the control logic, inhibit drivers, sense amplifiers, and 16-bit data register; the
other hex-height module (G231) contains the address selection logic, current generator, and switches and drivers.

Pin-to-pin compatibility exists between the C, D, E, and F connectors of both these modules are also compatible
with the standard Unibus pin assignments.

It is recommended that the G231 Driver Module be installed between the G110 Control Module and the H213 or
H214 Stack Module. Photographs of the component sides of the modules are shown in Figures 11-1, 11-2, and 11-3.
11.2.2

Specifications

The general memory specifications are listed in Table 11-1.

HANDLE(2)

STROBE ADJUSTMENT

PRI

R120

62702

Figure 11-1

Component Side of G110 Control Module

Figure 11-2

Component Side of G231 Driver Module

VHANDLE(Z)

62706

11-2

HANDLE (4)

wrrrsiv

8192 X 16 BIT CORE ARRAY
WITH PROTECTIVE COVER

6270-10

Figure 11-3

Component Side of 8K H214 Stack Module

Table 11-1
MM11-K and L Memory Specifications
Type:

Magnetic core, read/write, coincident current, random access.
Organization:

Planar, 3D, 3-wire
Capacity:

4096 (4K) words for MM11-K
8192 (8K) words for MM11-L
Access Time and Cycle Time:
Bus Mode

Cycle Time

Access Time

DATI

900 ns

400 ns

DATIP

450 ns

400 ns

DATO DATOB

900 ns

200 ns

450 ns

200 ns

(PAUSE L)

DATO-DATOB

(PAUSE H)

Table 11-1 (Cont)

MM11-K and L Memory Specifications
X-Y Current Margins:

6% @ 0° C, +7% @ 25° C, +6% @ 50° C
Strobe Pulse Margins:

+30 s @ 0° C, 40 ns @ 25° C, +30 ns @ 50° C

Voltage Requirements:

+5V 5% with less than 0.05V ripple
-15V +5% with less than 0.05V ripple
Average Current Requirements:
Stand by
+5V:

1.7A

-15V: 0.5A
+5V:

Memory Active
34A

-15V: 6.0A

Power Dissipation (worst case):
Control Module (G110): = 60W
Drive Module (G231): =40W
Stack Module (H213 or H214): = 20W
Total at maximum repetition rate: 120W
Environment:

Ambient temperature: 0° C to 50° C (32° Fto 122° F)
Relative Humidity: 0—90% (non-condensing)

11.2.3

Functional Description

The memory is a read/write, random access, coincident current, magnetic core type with a cycle time of 900 ns and
an access time of 400 ns. It is organized in a 3D, 3-wire planar configuration. Word length is 16 bits, and the memory

is offered in two word capacities: the MM11-K contains 4096 (4K) words, and MM11-L contains 8192 (8K) words.
The major functional units of the memory (Figure 11-4) are briefly described in the following paragraphs.
11.2.3.1

G110 Control Module — The G110 Control Module contains the memory control circuits, inhibit drivers,

sense amplifiers, data register, threshold circuit, - 5V supply, and device selector.

Memory Control Circuits — Control circuits are provided to acknowledge the request of the master

device, determine which of the four basic operations (DATI, DATIP, DATO or DATOB) is to be
performed, and set up the appropriate timing and control logic to perform the desired read or write
operation. If a byte operation has been selected, address line AOO L determines the byte to be selected.
The actual read or write operation is selected by control lines (C00 and CO1). The memory control logic
also transfers data to and from the Unibus.

Inhibit Driver — Each bit mat contains a single inhibit/sense line that passes through all cores on the mat.

To write a 0 into a selected bit, an inhibit current is passed through the inhibit/sense line that cancels the
write current in the Y-line. The core does not switch, so it remains in the O state. With no inhibit
current, the currents in the X- and Y-lines switch the core to the 1 state.

114

STROBE 0 & 1H —

BUS CO L,CH
BUS MSYN
BUS SSYN

8US A1 L,A4

BUS

Ai5L,16 L,17

BUS DRIVER

4096
CORES FOR
8K } PER BIT
FOR 4K
8192 CORES

MODE CONTROLS T'NHT: e T
BUS RECEIVERS

Ole‘T o

SELECTOR

DATA H —]

—————— ——

X -Y DIODE MATRICES
X DRIVE LINES

Y DRIVE LINES

PRD O

S-I1

I Osed

—

FIRST LEVEL DECODE

apoRESS —l
TDR —JAZ.S
res

| I0H

| READ-WRITE

>,y

L 7777

YPRD 0-7} YOR O-7

YNWD 0-7

cireuir - lapgq XPRD 0-7 1| XOR O
893

ynwD 0-7

oc Lo |——————la0.1

xss0-15

X8Y

CURRENT

2 13 0-7 FOR 4K
—

GENERATgR

TRAN -

.
n

s 2
553

W
e

_"_},71796/_
¢

O-7

.
1«

XSS 0-15

2177

7777
L

_________________

SERIES |__.(X_I_ET_I_)._.__.._—-—-SISTOR)

PRD 1

NWD {

¥SS 0-7

XDR

DISCHARGE
READ=GND
WRITE
= -15V

1777

«17777

—"aas6 vss0-7

STACK

(-15v

ss 1

'A%q*}fisss: CKTS

ADDRESS LATCHES

BUS DCLO L — —

eV,

i< 7777

BUS RECEIVERS

cKT

ss 0

olJlZz|®|w
Hlojl+-lx

/77

NWD 0

| Z|zlalg

BUS A2,3,4,5,6,7,]
8,9,10,41,12,13

CIRCUITS

A—AAAAAAA

_'{|

INTERLEAVE CONTROL

BIT

LA A A0 A AN 2 4% AN 4

L Wp

TIMING CHAIN

DEVICE

DATA FF REG
INHIBIT DRIVER

Loap omih —s

BUS DCLO

BUS DATA (0-15)

RESET 0aiL —»|

—

BUS INIT

et
alt

AO L —

16 DATA LOOPS

BYTE MASKING

BUS

H213,214 MEMORY STACK 4 OR 8K X

G110 CONTROL AND DATA LOOPS MODULE

UNIBUS

VOLT REF CIRCUIT

CURRENT CONTROL &

TEMPERATURE COMPENSATION

THERMISTER
RT1

RESISTOR

6234 DRIVER MODULE
11-1148

Figure 11-4

MM11-K, L. Memory Block Diagram

Sense Amplifiers — During a read operation, the sense amplifier picks up a voltage induced in the
sense/inhibit winding when a core is switched from a 1 to a 0. This signal is detected and amplified by

the sense amplifier whose output sets a data register flip-flop to store a 1. In effect, a 1 is read but the
core is switched to the O state. Cores which were previously set to O are not effected.

Data Register — The data register is a 16-bit flip-flop register used to store the contents of a word after it
is destructively read out of the memory; the same word can then be written back into memory

(restored) when in the DATI mode. The register is also used to accept data from the Unibus lines to

accommodate the loading of incoming data into the core memory during the DATO or DATOB cycles.

Device Selector — The device address is decoded in the device selector to determine if the memory bank

has been addressed.

Threshold Circuit and -5V Supply — The threshold circuit provides a reference threshold voltage to the
sense amplifiers. During a read operation, if the threshold voltage (20 mV) is exceeded, the sense

amplifier produces an output. The -5V supply provides a negative voltage for the sense amplifiers.

11.2.3.2

G231 Driver Module — The G231 Driver Module contains the address selection logic, switches and drivers,

current generator, stack discharge circuit, and DC LO protection circuit.
a.

Address Selection Logic — The core memory receives an 18-bit address from the master device. The

address is latched and decoded to determine if the memory is the selected device and to determine the
core location specifically addressed. If the operation is a byte operation, bus line AOO L indicates the
byte to be used. The X- and Y-portion of the address is decoded through selection switches and a diode

matrix to enable passage of read/write current through the selected X- and Y-drive lines of the memory.
The coincidence of these currents selects the specific 16-bit core memory location desired.

Switches and Drivers — The switches and drivers direct the flow of current through the magnetic cores to
ensure the proper polarity for the desired function. This action is necessary because a single read/write
line is used, and the current for a write operation is opposite in polarity to the current required
for a
read operation. There are separate switches and drivers for the read and write circuits in the selection
matrix.

Current Generators — X- and Y-current generators provides the current necessary to change the state of
the magnetic cores. The linear rise time and amplitude of the output-current waveform have been

selected to provide optimum switching of the core states and maximum signal-to-noise ratio for a wide
range of temperatures.

Stack Discharge Circuit — The stack discharge circuit maintains the proper stack charge voltage during
operation:

approximately

during

read

operation

and

approximately -14V during a

write

operation.

DC LO Protection Circuit — If any dc voltage is out of tolerance, DC LO is asserted on the Unibus.

sensed by the DC LO protection circuit, which inhibits the memory operation by opening the -15V
to the current source. This prevents spurious memory operation.

11.2.3.3

It is
line

H213 or H214 Stack Module — The stack module contains the ferrite core array and the
X-Y diode

matrices. For the 4K memory (H213), 16 core mats are used, each wired in a 64 X 64 matrix; 16
core mats, each
wired in a 128 X 64 matrix are used for the 8K memory (H214). The stack also contains the resistor/thermis
tor

combination to control the X-Y current generator temperature compensation.

11-6

11.2.4

Basic Memory Operations

The core memory has four basic modes of operation. The main function of the memory is simply to read and write
data. Additional modes are provided, however, to allow for byte operation and to eliminate the restore cycle when it
is not needed, thereby increasing overall system efficiency. The four basic memory operations are:
a.

Read/restore (DATI)

Read pause (DATIP)

Write (DATO)

Write byte (DATOB).

These four modes are discussed briefly in the following paragraphs.
NOTE

In the following discussions, all operations refer to the master

(controlling)

device.

For example, the term “data out”

indicates data flowing out of the master and into the memory.
11.2.4.1

Data In (DATI) Cycle
- The DATI cycle is a read/restore memory cycle. During this operation, the

memory reads the information from the selected core location, transfers it to the Unibus, and then writes the

information back into the memory location. This last step is necessary because the core memory is a destructive
readout device. During the first part of the cycle, the memory loads the data into a register; at the same time, the

memory applies the data to the Unibus. Then, during the second part of the cycle, the memory takes the data from
the register and writes it back into the addressed memory location.
11.2.4.2

Data In, Pause (DATIP) Cycle — Normally in reading from memory, the information is destroyed in the

particular location accessed, and the data must be restored. However, sometimes it is not actually necessary to

restore the information after reading, because the location is to have new data written into it. In this instance,
eliminating the restore operation decreases the memory cycle time by approximately 50 percent. The DATIP

operation is used for this purpose. The data is read from memory and the restore cycle is inhibited. Because no
restore cycle is used, a DATIP must always be followed by a write cycle (either DATO or DATOB) on the same
address or data in both addresses will be destroyed. If a DATIP is not followed by a DATO or DATOB, the memory

controller will be unable to control the bus, and other devices will be unable to access the bus (this is known as
hanging the bus).

11.2.4.3

Data Out (DATO) Cycle — The DATO cycle is a write memory cycle used by the master device to transfer

data into core memory. To ensure that proper data is stored, the memory unit must first be cleared by reading the
cores (thereby setting them all to 0) before writing in the new data. During a normal DATO, the memory first
performs the read operation to clear the cores and then performs a write cycle to transfer data from the bus into the
selected core location. If a DATO follows a DATIP (rather than a DATI), the sequence is not the same. The DATIP
clears core and generates a pause flag; the DATO skips the read cycle and immediately begins the write cycle. This
process reduces DATO cycle time by approximately 50 percent.

11.2.4.4 Data Out, Byte (DATOB) Cycle — The DATOB cycle is similar in function to the DATO cycle, except
that during DATOB data is transferred into the core memory from the bus in byte form rather than as a full word.
During the read cycle, the non-selected byte is saved by reading it into the data register while the selected byte is
transferred into the register from the bus. During the write cycle, only the selected byte portion of the word is
loaded into the memory location from the bus. At the same time, the non-selected byte is restored from the data
register into the memory location. In effect, the memory is first cleared and then simultaneously performs a restore
cycle for the non-selected byte and a write cycle for the selected byte. This mode can follow a DATIP as described
above.

CHAPTER 12

MM11-K AND L DETAILED DESCRIPTION

12.1

INTRODUCTION

This chapter provides a detailed description of the MM11-K and L memories. The discussion is related to the 8K
memory (MM11-L). The description of the 4K memory (MMI11-K) is basically the same; only the differences are
discussed.

The detailed description covers the core array, device and word selection, switches and drivers, current generation,
stack discharge circuit, DC LO circuit, sense/inhibit circuitry, control and timing logic, and memory operating
cycles.
12.2

CORE ARRAY

The ferrite-core array for the 8K memory consists of 16 mats arranged in a planar configuration. Each mat contains
8192 ferrite cores arranged in a 128 X 64 array. Each mat represents a single bit position of a word. This planar

configuration provides a total of 8192 16-bit word locations. The 4K memory core array consists of 16 mats each
arranged in a 64 X 64 planar configuration to provide a total of 4096 16-bit word locations. Each ferrite core can
assume a stable magnetic state corresponding to either a binary 1 or a binary 0. Even if power is removed from the

core, the core retains its state until changed by appropriate control signals. The outside diameter of each core is 18
mil; the inside diameter is approximately 11 mil. Each core is 4.5 mil thick.

Selection and switching of the cores is provided by three wires traversing each core in a special selection technique.
An X-axis read/write winding passes through all cores in each horizontal row for all 16 mats. A Y-axis read/write
winding passes through all cores in each vertical row for all 16 mats. Through the use of selection circuits which
control the current applied to specific X-Y windings, any one of the 8192 or 4096 word locations can be addressed
for writing data into memory or reading data out of memory. A third line passes through each core on a mat to
provide the sense/inhibit functions. There is one sense/inhibit line per mat. This single sense/inhibit line, as well as
the selection circuits, are discussed in subsequent paragraphs.
12.3

MEMORY OPERATION

Figure 12-1 illustrates a typical portion of the core memory. An X- and Y-winding pass through each core in the
mat. The current passing through any one winding is such that no single winding produces a magnetic field strong
enough to cause a core to change its magnetic state. Only the reinforcing magnetic field caused by the coincident
current of both an X- and Y-winding can cause the core located at the point of intersection to change states. It is this
principle that allows the relatively simple winding arrangement to select one and only one memory core out of the
total contained on each mat. The current passing through either an X- or Y-winding is referred to as the half-select
current.
]

A half-select current passing through the X3 winding (Figure 12-1) from left to right produces a magnetic field that
tends to change all cores in that horizontal row from the O to 1 state. The flux produced by the current is, however,

insufficient to complete the state transition in any core. Simultaneously passing a half-select current through the Y2
winding from top to bottom produces the same effect on all cores in that particular vertical row. Note, however,
that both currents pass through only one core which is located at the intersection of the X3 and Y2 windings. This is

12-1

INHIBIT
CURRENT DRIVER

\kg/

‘j /

AN\

\\w

)

/f_\

FERRITE

/\/com-:s

—

SELECTED

/\/CORE

\(\

B
1

SENSE/INHIBIT

LINES

TO SENSE AMPLIFIER
TERMINATION

Figure 12-1

Ims2
11-0079

Three-Wire Memory Configuration

the sclected core and the combined current values are sufficient to change the state

of the core. The arrows in Figure
12-1 show current direction for the write cycle. All X- and Y-windings are arranged
in such a manner that whenever
a half-select current is passed through ecach, the resultant magnetic fields combine
in the core at the point of
intersection. This combined, full-select current ensures that the selected core
is left in the binary 1 state. The
currents used to select the core are referred to as write currents. A typical hystersis
loop for a core is shown in
Figure 12-2.

12-2

(«

/§

\\Lt
=14

Im/o X3 =

HYSTERESIS LOOP FOR CORE
———

INHIBIT OR

FLUX STORED OR SWITCHED

READ HALF SELECT

q
t

TUNDISTURBED

—~ “"DISTURBED

|
|

|
|
WRITE
FULL
SELECT

FLUX

CHANGE

I WRITE
Y

FOR 1 AT<

READ

DRIVE CURRENT

TIME

|
|

READ
FULL

SELECT

|
{

:
|

-- ¢
"0" DISTURBED

|
MALF SELECT WRITE

“0" UNDISTURBED==
{

FLUX CHANGE AT READ
TIME FOR A"0"

NOTE NO SWITCHING

TAKES PLACE.

"1" QUTPUT SWITCHES AT THE
CORE TIME CONSTANT AND IS

0" OUTPUT COMES DURING I RISE TIME
AND IS A FUNCTION OF IT AND CURRENT
AMPLITUDE.
1

PRIMARILY DEPENDENT ON

CURRENT AMPLITUDE. IT WILL
SWITCH FASTER AND GROW AS
RISE TIME IS DECREASED.

"0" QUTPUT & A §— OR O g7
_____ L

—

DOTTED LINES SHOW HOW
OUTPUTS WOULD BEHAVE
WITH DIFFERENT CURRENTS

11-00888

Figure 12-2

Hysteresis Loop for Core

In the MM11-K and L Core Memories, the X3 windings in all 16 mats are connected in series as are the Y2 windings.
Therefore, whenever a full-select current flows through a selected core on one mat, it also flows through an identical
core on the other 15 mats. The X3-Y?2 cores on all mats switch to a binary 1, causing each of the 16 cores to become
one bit of a 16-bit storage cell.

——

12-3

Because of the serial nature of the X-Y windings, a method is used that allows cores to remain in the O state during a
write operation; otherwise, every 16-bit word selected would be all 1s. The method used in the MM11-K and L Core

Memories is to first clear all cores to the O state by reading and then, by using an inhibit winding during the write

operation, to inhibit cores on particular mats. The inhibited cores remain Os even when identical cores on other mats

are set to 1.

The halfselect current for the inhibit lines is applied from an inhibit current driver, which is a switch and a resistor

between the inhibit line and -15V. The current in the inhibit line flows in the opposite direction from the write
current in all Y-lines and cancels out the write current in any Y-line. There is a separate inhibit driver for each
memory mat, and each mat represents one bit position of a word; thus, selected bits can be inhibited to produce any

combination of binary 1s and Os desired in the 16-bit word. It must be remembered that the inhibit function is

active only during write time.

The sense/inhibit lines are also used to read out information in a selected 16-bit memory cell. The specific core is
selected at read time in the same manner as during the write cycle with one notable exception: the X- and
Y-currents are in the opposite direction. These opposite half-select currents cause all cores previously set to 1 to
change to 0; cores previously set to O are not effected. Whenever the core changes from 1 to 0, the flux change

induces a current in the sense winding of that mat. This current is detected and amplified by a sense amplifier. The

amplifier output is strobed into the data register for eventual transfer to the Unibus. Figure 12-3 shows a 16-word by
4-bit planar memory. The MM11-L Core Memory (8K) functions in the same manner, except that it has 128 X-lines,
64 Y-ines, and 16 core mats. The core stringing is identical, and the sense windings are strung through all 8192 cores
with the interchange between X63 and X64 instead of between X1 and X2. For the 4K memory, the interchange is

between X31 and X32 and it has 64 X-lines and 64 Y-lines.

12.4

DEVICE AND WORD SELECTION

When the processor or a peripheral device attempts to perform a transaction with the memory, the processor asserts

an 18-bit address on Unibus address lines A (17:00). Six of these 18 bits [AO1 and A (17:13)] indicate the address
of the memory as a device. Depending on the memory configuration, only four or five bit combinations of these bits

are used as shown in Table 12-1. Eleven of the 12 remaining bits [A (12:02)] plus AO1 and A13 indicate the address
of a specific word within the memory. Address bit A0O is used to select the byte (8 bits) transaction when in

DATOB mode.

Table 12-1
Addressing Functions

Bus Address

Function

4K Mode

8K Mode

A00

Controls byte mode

A0l

Becomes AOIH to G231

A02, A03, AQIH*

Decode Y-Drivers

A04, A0S, AO6

Decode Y-Switches

A07, A0S, A09

Decode X-Drivers

Al0, All, A2

Decode X-Switches

Controls byte mode

Al3

Goes to device selector

Decode X-Switches

Al4

Goes to device selector

AlS, Al6,Al17

Goes to device selector

*AOIH is not a Unibus signal.

124

ARROWS SHOW CURRENT
DURING WRITE TIME

TOP VIEW OF CORE MATS

XSW

W————

W————
R ————

____“_._Y

—
R P

w ————fl—‘1

W ————
—
R T

)
TN

M
‘S'

XDR

vel

Y',

INH

I~ INTERCHANGE
IS FOR NOISE
CANCELLATION

THERE IS 1 SENSE INHIBIT

WINDING PER MAT

vsw

Ysw

fl fl

)-.\

WR
WR
YDR

CORE

SENSE-INH LINE

)

X
Y

BONDING MEDIUM —={
{

Oxume

LINE

)

GROUND PLANE

BOARD

DETAILS OF CORE STRINGING

Figure 12-3 Three-Wire 3D Memory, Four Mats Shown for a 16-Word 4-Bit Memory

12-5

11-00884A

The memory address is decoded by the device selection circuit on the G110 Control

stored in a register on the G231 Driver Module whose output is decoded to activate the

Module. The word address is

X-Y line switches and drivers
which select the addressed word. These circuits contain jumpers which are included or excluded to establish a
specific device address and select 4K- or 8K-word capacity. Jumpers are provided to select interleaved or
non-interleaved operation for the 8K model; however, the memory is to be operated in the non-interleaved mode

only.

Table 12-1 lists the function of each address bit. Figure 12-4 is a simplified block diagram of the device and word

[

address selection circuits,

‘/\F

'CONTROL MODULE G110
DCLOL

A<|7:I4>l

DEVICE

A13

CONTROL

201 H

A13 !

AOQ3H & L
AO9H

GaTEs

TDR H

A<12:02>

WORD

AO1H,AO2H,AQ4H,AO5H, AO7H, AOBH, A1OH, AlTH

ADDRESS

nanp

]

TO DECODERS

| FOR X=Y

A13 (1) B(0)

(A12H-AT3H)
L

A06(1) 8(0)
ADDRESS

GATING

IssH ]

Lo
\/
I

SWITCHES

AND DRIVERS

AOB(1)L,A06 (0L

A12 (1) &(0)

(AM12L-A13H) L

[

(A12L-A130)L

)

(A12H-A13L)L

l
Figure 12-4

12.4.1

LOGIC

DRIVER
MODULE G231

DSEL H

SELECTOR

AQQ,A01 I

H-1090

Device and Word Address Selection Logic, Block Diagram

Memory Organization and Addressing Conventions

Prior to a detailed discussion of the address selection logic, it is important to understand

addressing conventions.

The memory is organized in 16-bit words each consisting of two 8-bit bytes. The
as shown below.

HIGH

15
Ms8

BYTE
L

DATA

]

o8
07
BITS D<I5:00>

LOW

BYTE

bytes are identified as low and high

00
LSB
H-t17a

12-6

memory organization and

Each byte is addressable and has its own address location: low bytes are even numbered and high bytes are odd
numbered. Words are addressed at even numbered locations only; the high (odd) byte is automatically included.

For example, an 8K word memory has 8192 words or 16,384 bytes; therefore, 16,384 locations are assigned. The
address locations are specified as 6-digit octal numbers. The 16,384 locations for the 8K memory are designated
000000 through 037777. Figure 12-5 shows the organization for an 8K memory.

8|7

|
+——16 B!T WORD——»

HIGH BYTE

LOW BYTE

000001

000000

000003

000002

000005

000004

N———
\/Q\_

037773

037772

037775

037774

Q37777

037776
11-1091

Figure 12-5

Memory Organization for 8K Words

The address selection logic responds to the binary equivalent of the octal address. The binary equivalent of 017772
is shown in the following example.

ADDRESS BITS A<17:00>

1716|151l

141131211

cojotolojo
o)

]10]|09|08|07]|06]05]|04]03]|02]01

1
7

00|

BIT POSITION

O | BINARY

OCTAL
o173

Each memory bank (4K or 8K words) requires its own unique device address. For example, assume that a system

contains three 8K memory banks (Figure 12-6). The device selector for the 8K non-interleaved memory decodes

four address lines [A (17:14)}. Examination of the binary states of these bits for the three memory banks shows
that the changes in the states of bits A14 and Al15 allow the selection of a unique combination for each bank. The
combination, which is the device address, is hardware-selected by jumpers in the device selector.

12-7

000000

037777

BANK
1
8K WORDS

040000
BANK
2

077777

8K WORDS

“>

100000

BANK
3

[H)

137777

BK WORDS

1st

ADDRESS

{
BANK

BIT

]sinary

ol o]ofo]f:
LAST ADDRESS

BANK
2

ADDRESS

tst

ADDRESS

LAST

ADDRESS

[

]

)

1
7

BANK
3

]

)

0
LAST

OCTAL

ojo]o]
tst ADDRESS

POSITION

|
)

ool

)

[

3
1-1092

Figure 12-6

Address Assignments For Three Banks of 8K Words Each

During system operation, the processor generates the binary equivalent of the octal address on Unibus address lines
A (17:00). The processor uses positive logic and the Unibus uses negative logic. With this in mind, the following is

included to remind the reader of the negative logic convention of the Unibus.
Processor (Positive Logic)
Signal Asserted: High = Logical 1 =+3V

Signal at Rest: Low = Logical 0 =0V

Unibus (Negative Logic)
Signal Asserted: Low = Logical 1 =0V
Signal at Rest: High = Logical 0 = +3V

12.4.2

Device Selector

The device selector located on the G110 Control Module (drawing G110-0-1, sheet 2) shows a logic diagram
device selector in the 4K configuration.

12-8

of the

Address bits A0l and A (17:13) are decoded in the device selector to provide the device selection signal D SEL H
that is used in the control logic. Two combinations of these bits are decoded, depending on the memory
configuration as shown below.

Memory Configuration

Address Bits

4K Words

A(17:13)

8K Words

A(17:14)

Obviously, the memory capacity is determined by the stack module: H213 for 4K words and H214 for 8K words.
The same control module is used for both 4K and 8K memories; therefore, two jumpers (W9 and W10) are provided
to include or exclude address bit A13 commensurate with the memory word size. Two jumpers (J3 and J4) on the
G231 Driver Module (drawing G231-0-1, sheet 2) are provided for A13 inclusion or exclusion in the word addressing
logic. The same driver module is used for both memory capacities. In the 4K word size, the components associated

with the additional X-line read and write switches needed for 8K words may be removed. Two jumpers (W7 and W8)
in the device selection logic on the control module are used to select interleaved or non-interleaved operation of the
8K memory. They are configured to provide non-interleaved operation only.

Each memory bank (4K or 8K) must have its own unique device address. Five jumpers (W2-W6) in the device
selector provide this capability. On drawing G110-0-1, sheet 2, all the jumpers are shown in place and the device
selector responds only when high signals appear on the Unibus address lines A (17:13). Some jumpers can be
removed to allow the device selector to respond to a particular combination of high and low signals on these address
lines.

All highs at the inputs of the 7380 Unibus receivers (E12 and E23) give lows at their outputs. Each receiver output
goes to one input of a type 8242 Exclusive-NOR gate. Because of jumpers W7 and W8, bit A14 is decoded for 4K

and 8K configurations. An additional receiver is used to sense BUS DC LO L, and its output (E23 pin 14) is sent to
an 8242 gate (E24 pin 5). BUS DC LO L is asserted only when the dc voltages from the power supply drop below
specified limits.

The other input of the 8242 gates associated with bits Al4, A13, A1S5, A16 and Al7 can be connected to +5V or
ground, depending on whether or not jumpers W2-W6 are installed. The input is low (ground) with the jumper in;
with the jumper removed, the input is high (+5V). Each 8242 gate is used as a digital comparator; its output is high

only when both inputs are identical. The 8242 gates have open collectors and they are connected in common;

therefore, the comparator output D SEL H is high only when all gates detect matched inputs (both lows or both
highs).

An installed jumper requires a low signal at the output of the 7380 Unibus receiver. The 7380 is connected as an
inverter so this signal is reflected as a high on the Unibus (logical or asserted state for the Unibus). To configure the
jumpers for a specific device address, find the binary equivalent of the assigned octal address and insert a jumper in
each bit position that contains a 0. A specific jumper configuration is shown in Figure 12-7.
The previous discussion dealt with the 4K memory configuration of the device selector as shown in drawing

G110-0-1, sheet 2. Address bits A (17:13) are decoded and the output of bit AO1 Unibus receiver (E23 pin 2) is sent

via jumper W8 to the word address register as AOL H.

In the 8K memory configuration, jumper W9 is removed and W10 is installed. This removes bit A13 from the input
of Unibus receiver E12 on G110 and replaces it with +5V via resistor R107. This receiver output (pin 14) always
remains low so that jumper W5 must remain installed to ensure a match on pins 12 and 13 of gate E13. The jumper
configurations for memory systems up to 128K words are shown in Figure 12-8.
12-9

PROCESSOR STATE (POSITIVE LOGIC)

BUS STATE (NEGATIVE LOGIC)

ASSERTED: H=1=+3V

ASSERTED: L=1=0V

REST: L:0:0V

R108

REST: H=0=+3V

BUS A14 L ——(Q)
s

—

wé

+5v

R122

oL EeTOR

E23

RESISTOR

—C_J

ASSERTED
ONLY

R109
'

LOSELH
| IF ALL
p—>

GATE

OUTPUTS

w4
7

BUS A15 L —+—(

ARE HIGH

\
E'2

ONLY

TRUTH TABLE

=
A14 AND

A <17TH46>HAVE

A15

AlB|C

SHOWN.

JUMPERS

ALSO.

'
8242 EXCLUSIVE NOR ELEMENT

ASSIGNED

ADDRESS

)

=
A

]

1901

USED ASAD
AS
DIGITAL

JUSER

00TPUT

IS HIGH

ONLY WHEN BOTH

INPUTS MATCH.

tlrg

040004

17 (16151
(13|12 {1144
{10
9 | 8|7

|61 5432|410

BIT POSITION
000100000000000100BINARYOCTAL

BITS A <17:14> ARE DECODED FOR DEVICE

OCTAL

SELECTION

116 | 15 | 14

olo]|o]

t t t

INSTALL JUMPERS IN THESE BIT POSITIONS
11-1093

Figure 12-7

Jumper Configuration For A Specific Memory Address

CONTROL MODULE G110
COMPONENT

o W

SHOWING PHYSICAL
SIDE

LOCATION OF

JUMPERS

o
w7
o

o wio o

o“wWsTMo

o
ws
o

o
wa
o

w
o 2
o

o
we
o

o
ws
o

o wi o

o
wi
o
>

NOTES:

/
CONNECTOR

EDGE

1. Jumper W1 is for test purposes only.
It must be installed for normol operation.
2. Jumper W11 should be removed for normal operotion.When installed the memory

[$ I

)

responds to DATI onty,regardless of state of control lines COO and CO1.
. Jumpers W7 and W8 must remain in the factory installed positions.

. When used as an 8k bank, jumpers WS and W10 must be instalied and jumper
WS must be removed.

. When used as o 4k bank, jumper WO must be removed and jumper
W9 must be
installed. Jumper W5 defermines the location of the bank on the bus.

Figure 12-8

Device Decoding Guide

12-10

H-tta9

Device Address Jumpers

Memory
Bank (Words)

Machine
Address (Words)

W5
Al3

Wé
Al4 or AOL

w4
AlS

W3
Alé6

w2
Al17L

0—4K
4-8K
8-12K
12-16K
16—-20K
20--24K
24-28K
28—-32K
32-36K
36—-40K
40-44K

000000-017776
020000037776
040000057776
060000-077776
100000117776
120000137776
140000157776
160000177776
200000217776
220000237776
240000-257776

IN
ouT
IN
ouT
IN
OouT
IN
ouT
IN
ouT
IN

IN
IN
ouT
ouT
IN
IN
ouT
ouT
IN
IN
ouT

IN
IN
IN
IN
ouT
ouT
OUT
ouT
IN
IN
IN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

OouT

IN
IN
IN
IN
IN
IN
IN
IN
ouT
ouT
OUT

48-52K
52-56K

300000317776
320000-337776

IN
ouT

IN
IN

ouT
ouT

IN
IN

60—-64K
64—-68K
68-72K
72-76K
76—80K

360000-377776
400000—-417776
420000—437776
440000457776
460000477776

OouT
IN
ouT
IN
ouT

OouT
IN
IN
ouT
ouT

ouT
IN
IN
IN
IN

IN
ouT
ouT
OUT
ouT

88—92K
92-96K

540000557776
560000577776

IN
OouT

ouT
ouT

IN
IN

ouT
OouT

100-104K
104—108K
108—-112K

620000637776
640000657776
660000—677776

ouT
IN
ouT

IN
OuT
ouT
IN

IN
IN
IN

ouT
ouT
ouT

ouT
ouT
OouT

44-48K

56—-60K

80-84K
84—-88K

96—100K

112-116K
116—120K
120-124K
124—128K

260000277776

340000-357776

500000517776
520000537776

600000617776

700000717776
720000737776
740000757776
760000777776

OouT

IN
ouT

IN
ouT
IN
ouT

IN
IN

IN
ouT
OouT

OuUT

ouUT
OouT

OouT
ouT
OuUT
OouT

OouUT

OuUT

IN
IN

OouUT

ouT
OouUT
ouT
ouT

ouT
ouT

ouT

OouT
ouT
ouT
OouT

Figure 12-8 Device Decoding Guide (Cont)

12.4.3

Word Selection

Word selection requires two levels of decoding. The word address bits are placed in the 13-bit word address
register: 12 bits are used for a 4K memory, and 13 bits are used for an 8K memory. Some bits from the register
output are combined in a gating network. The outputs from the gating network and some outputs directly from the
register are used as inputs to a group of decoders (Figure 124). The outputs of the decoders select the proper X- and
Y-read/write switches and drivers.

12-11

12.4.3.1 Word Address Register and Gating Logic — The word address register and gating
logic are contained on the
G231 Driver Module. The circuit schematic is shown in drawing G231-0-1, sheet 2.
The register is composed of 13
74H74 dual D-type edge-triggered flip-flops. They ave identified as E11, E12, E13,
Ei14, E18, E19, and E20. The
output (pin 3) of gate E9 provides a high signal on the preset input (pin 4 or pin 10)
of each flip-flop, which
prevents direct presetting of the flip-flop. Direct clearing of each flip-flop is prevented
by a high signal on the clear
input (pin 1 or pin 13) via the output (pin 2) of gate E9. The register cannot be directly
cleared or preset; its output

responds only to the signal at its data (D) input.

Address bits A (13:02) are picked off the Unibus via type 7380 receivers (E15, E16, and

are

E17). The receiver outputs

sent to the corresponding flip-flop D-inputs. The input to the receiver associated
with bit A13 has two
sources: Unibus signal BUS A13 L via jumper J4, or +5V via jumper J3. These
jumpers are associated with the
memory word size. A 4K memory requires J3 in and J4 out; an 8K memory requires
J4 in and J3 out. Because BUS
Al3 L is used on the G110 module as part of the device selector, this arrangement
prevents loading BUS A13 L
twice per memory bank.

The EI1 flip-flop associated with bit AO1 receives its input from the device selector
(drawing G110-0-1, sheet 2).
The input signal is AO1 H, which is obtained from bit AO1 Unibus receiver for both 4K
and 8K memories.
The register flip-flops are clocked synchronously by CLK 1 H from the control logic
(drawing G110-0-1, sheet 2).
Clocking occurs on the positive-going edge of CLK 1 H. The generation and timing of
this clock signal is discussed in
Paragraph 12.9.1. When the register is clocked, the outputs of flip-flops AO1, A02,
AO4, A0S, AO7, AO8, A10 and
All are sent to the type 8251 X-Y decoders on the G221 Driver Module (drawing G231-0-1,
sheets 3 and 4). The
outputs of flip-flops A06, A12, and Al3 are combined in a group of six type 74H10
NAND gates (three E22s, and
three E25s), which are enabled by signal TSS H. Table 12-2 lists the states of flip-flops
A06, A12, and A13 that are

required to enable these gates. The outputs of flip-flops A03 and A09 are gated
with TDR H in high-speed 2-input
NAND gates and then applied to the decoders for the drivers only. The six signals listed
in Table 12-2 are sent only
to the X-Y line read/write switch decoders on the driver module.

Table 12-2
Enabling Signals for Word Register Gating

Output Signals

Gate

Asserted Signal

Enabling Signals

FF A06

FF A12

FF A13

E22 pin 12

(AO6H) L

Set

E22 pin 8

AO6L

Reset

E22 pin 6

(A12H - AI3H) L

Set

E25 pin 12

(A12L - AI3H) L

Reset

Set

25 pin 8

(AI2H - AI3L)L

Set

Reset

E25 pin 6

(A12L - AI3L)L

Reset

Signal ISS H is generated at the output (pin 3) of negative input OR gate E4 during a read

a read operation, the enabling signal is produced at NAND gate E4, pin 8

or write operation. During

by ANDing READ H and TNAR H. During

a write operation, the enabling signal is produced at NAND gate E4,
pin 6 by ANDing WRITE H and TWID H.

Signals READ, TNAR and TWID are generated by the control logic on the
G110 Control Module. WRITE is the
complement of READ (produced by inverter E6). Signal READ H comes from

the 1 output of R/W flip-flop E13

(drawing G110-0-1, sheet 2); the READ H signal is produced when the flip-flop is set. When
the R/W flip-flop is
cleared, READ H is low and is inverted by E6 to produce WRITE H.

12.4.3.2 X-and Y- Line Decoding — The basic decoding unit is a Type 8251 BCD-to-Decimal Decoder that converts
a 4-bit BCD input code to a one-of-ten output; however, only eight outputs are used. Figure 12-9 shows an 8251 and
associated truth table. The inputs are DO, D1, D2, and D3; they are weighted 1, 2, 4, and 8 with DO being the least
significant bit. The outputs are 0—7 and are mutually exclusive. The selected output is low and all others are high.

7 b2>—
s b2 | TO WRITE

14
12
—
BCD INPUT

SWITCHES/
3
5 o2~ | ORIVERS

)

—
2

4 Pp—
0

8251

3pl9

2 b | 10 READ

SWITCHES/

DRIVERS

p—

—

+5Vv

o p2—o

TRUTH

TABLE

OUTPUTS

INPUTS

p3]oe[o]oo o[1]2]s]a]s]e]7
ololoJolol
ololotr

ololr|olv
otlolr1ial

[alsr

1ol
1ol

olrfolr

ol1l1jol

X | X

]1]ols]n

1l1it]1]oly

it
X

ba]r]]

1]olla]a]n

oltlololr

][]

1]t

i l 1

fifitalo
1 11
1
1

X:1IRREVELANT
151095

Figure 129 Type 8251 Decoder, Pin Designation and Truth Table

For the 8K memory, ten decoders are used: six for the X-axis and four for the Y-axis. Each decoder controls four
read/write switch pairs. Each pair is associated with a specific switch or driver. This switch matrix is combined with
the stack X-Y diode matrix to allow selection of any location out of the total 8192 locations (stack drawing
DCS-H214-0-1 for interconnections).

For the 4K memory, cight decoders are used, four for each axis. The stack X-diode matrix is halved to allow
selection of any location out of the total 4096 locations (stack drawing DCS-H213-0-1 for interconnections). A
discussion of the configuration and operation of the switches and diode matrices is given in Paragraph 12.4.3.3.

The X- and Ydine switches are first differentiated as switches and drivers. The drivers are those switches that are
connected to the diode end of the stack. Drivers and switches are further differentiated by function: either read or
write. Another differentiation is made by polarity: negative or positive, depending on the physical connection. Read
drivers and write switches are connected to the current generator outputs and are considered positive; write drivers
and read switches are connected to ~15V and are considered negative.

Figure 12-10 shows the decoders associated with Y-line read and write switches 4-7 and Y-line read and write
drivers 4—7. {Refer also to the truth table in Figure 12-9.) In both decoders (E28 for switches and E8 for drivers),
the signal to input D3 selects the block of switch pairs. This signal must be low for any output to be selected. The
signal to input D2, which is READ L for all decoders, controls the selection of read or write switches/drivers. When

12-13

READ L is low, outputs 03 are selected: these are read switches and read drivers. When READ L is high,
outputs
4--7 are selected: these are write switches and write drivers. The four combinations of the states of inputs DO and

D1 select the particular switch/driver.

5
70—

AO6

30—

— D2

A0S H

WRITE SW

YS7 READ Sw

a
6

READ

YS7

p—
11

Pp————1

YS6

WRITE SwW

YS6

READ

£28

——
] D!

02—-

YSS5

WRITE

YS5

READ

{

10—

AO4

DO
9

YS4 WRITE
13

OpP——

DECODER

FOR READ AND

WRITE

—

AO3

)

D3
READ

20—

60—

£E8

—— Dt

5————

YP READ

DRé6

WRITE

DR6

READ

DRS

WRITE

DRS

13
oOp———/
9

40—

DECODER

DR7

12
{P——94

AO{ H {5
-1

DR7

WRITE

- D2

AO2

YS4-YS7

YP READ
YN

)

READ SW

SWITCHES

10
3P——
TDR

YS4

FOR READ AND

WRITE

YP READ
YN

WRITE

DR4
DR4

DRIVERS Y4-Y7
11-1096

Figure 12-10

Decoding of Read/Write Switches and Drivers Y4-Y7

The four driver decoders (E3, E8, E43, and E46 on drawing G231-0-1, sheets 3 and 4) have a NAND gate connected

to input D3. Signal TDR H is an input to each gate; therefore, the driver decoders cannot be enabled unless TDR
H
is high. This signal is generated on the G231 Driver Module (drawing G231-0-1, sheet 2, coordinates A-8) by ANDing

TWID H and READ H or TNAR H and WRITE H.

Each switch/driver is connected to the decoder output through a transformer-coupled base drive circuit. When the
decoder output is at ground (low), the switch/driver is turned on; it is turned off when the decoder output
is at
+3.5V (high). The base drive circuit for writc switch YS7 shown in Figure 12-11 is typical.
In this example, the decoder inputs have selected output 7, which is at ground. Current i; flows into this decoder

output circuit from the +5V supply via resistor Ri1 and the primary winding (terminals 4 and 3) of transformer T8.

The value

of i,

is determined by the value of RI1

and the voltage reflected into the transformer primary

(approximately 1V). An equal current i, is induced in the base-emitter circuit of write switch E29, which is

12-14

connected to the transformer secondary winding (terminals 13 and 14). This current turns on E29. All the base
current for E29 is provided by this circuit: i3 is the collector current. When the decoder is turned off, its output
pull-up transistor tries to drive the turn-off current is in the opposite direction. This reverse current removes the
forward bias from the base of E29 and turns it off. Capacitor C30 allows the decoder to pump reverse current is into
the transformer primary; it also speeds up turn-on current i;. Diode D1 prevents reverse breakdown of the
base-emitter junction of E29; it also protects the decoder output.

+5V

8251
DECODER
E28
b

+5V

€30 2 R

FROM

CURRENT

GENERATOR

7hs

i
)

WRITE
SWITCH

‘3

STACK

—>

PORTION OF
OUTPUT 7

gt
~

.
11-109

Figure 12-11

Switch or Driver Base Drive Circuit

12.4.3.3 Drivers and Switches — Drivers and switches direct the current through the X- and Y-lines in the proper
direction as selected by the read and write operations.

For an 8K memory, 16 pairs of read/write switches and 8 pairs of read/write drivers are provided in the X-axis; 8
pairs of read/write switches and 8 pairs of read/write drivers are provided in the Y-axis. In conjunction with the

stack diode matrix (drawing H214-0-1, sheet 2), one driver and any one of 16 switches select 16 lines in the X-axis;
one driver and any one of eight switches select eight lines in the Y-axis. This allows selection of 128 lines in the
X-axis and 64 lines in the Y-axis. This provides a 128 X 64 matrix that selects any location out of 8192 locations.

For a 4K memory, eight pairs of read/write switches and eight pairs of read/write drivers are provided for each axis
(X and Y). One driver and any one of eight switches select eight lines in both axes, which allows selection of 64 lines
in each axis and provides a 64 X 64 matrix that selects any location out of 4096 locations. The size of the X-diode
matrix for the 4K memory is one half the size of the corresponding matrix for the 8K memory (drawing H213-0-1,
sheet 2). In both memories, the diodes prevent sneak currents in the stack and steer all switched current into the
selected stack line.

Figure 12-12 is one fourth of a Y-selection matrix showing the interconnection of the diodes and the lines from the
switches and drivers. It also shows how four pairs of switches and drivers are connected to select 16 locations. Refer
to drawing H213-0-1, sheet 2 for an extension of this method that uses eight pairs of switches and drivers to select
64 locations.

Figure 12-12 shows four pairs of drivers and four pairs of switches for the Y-axis only; polarities are shown for
convenience. The diodes are identified to assist in associating them with the drivers and switches. Each line from a
twin diode interconnection to a read/write switch pair passes through 64 cores and represents one line on each bit
12-15

mat. Assume that a write operation is to be performed and the word address decoders have selected write switch
WYS00 and write driver YNWD1. The Y-current generator sends current through write switch WYS00 (conventional

flow), which puts a positive voltage on the anodes.of diodes 03W, 02W, 01W and 00W. The non-selected write
drivers (YNWD3, YNWD2, and YNWDO) provide a positive voltage on the cathodes of their associated diodes (03w,

02W and OGW, respectively), which reverse biases them and prevents conduction. Write driver YNWD1, which has

been selected, turns on and makes the cathode of diode 01W negative with respect to the anode that forward biases
it. The diode conducts and allows current to flow to write driver YNWDI1. A half-select current now flows through

this line that links 64 cores per bit mat (1024 total for 16 mats).

SWITCHES
-1RYS0O

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-

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XK 23w

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SECTION

(16

OOW

il i

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LOCATIONS)

11-1098

Figure 12-12

Y-Line Selection Stack Diode Matrix

Figure 12-13 is a simplified schematic of two pairs of switches and drivers interconnected with the core
stack and

current generator. Read/write switches YSO7 and read/write drivers YD7 are used as examples.
These switches and

drivers are chosen for convenience. For a read or write operation, there are 64 switch/driver combinations
available
on the Y-axis and 128 on the X-axis. For a read operation, decoder ES selects positive read driver
E7 via transformer
T3; and decoder E28 selects negative read switch E26 via transformer T7. Both E7 and E26
are turned on when they
are selected. E7 conducts and removes the reverse bias on diode D67, which allows
current from the Y-current

generator to flow through D67, E7, the associated matrix diode, and the cores on
the selected line. After passing

through the cores, the current flows through E26 and R27 to the -15V line. For a write
operation, decoder

E28
via transformer T8; and decoder E8 sclects negative write drivers E10 via
transformer T4. Both E29 and E10 are turned on. E29 conducts and removes the reverse
bias on diode D17, which

selects

positive write switch

E29

allows current from the Y-current to flow through D17, E29, and the cores in the opposite

direction. After passing
through the cores, the current flows through the associated matrix diode, E10, and R140
to the -15V line. Read
current flow is shown as a solid line; a broken line shows write current flow.

12-16

+5V

READ
CURRENT

WRITE
CURRENT
Y -CURRENT
GENERATOR

% D60

D67 ¥

—-15V

R141

i D61

|
|

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TO DECODER

T3
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8 piopE

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E£10

TO DECODER

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CIRCUIT
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——————J

NEG READ SWITCH

£26

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TO DECODER

R140

E28

(64/MAT)

YNWD?

YSO7

i
|

+ S5V AN—9

NEG WRITE ORIVER

£8

PAIRS

POS WRITE SWITCH

TO DECODER

Q1024@CORES@ X|

A~ +5V

E29

RS9

—

>E7

YPRD7

¥ D17

£28

R27
-15v

.15V

1-1089

Figure 12-13 Typical Y-Line Read/Write Switches and Drivers

12.4.3.4 Word Address Decoding and Selection Sequence — This paragraph takes a specific word address through
the decoding and X- and Yline selection sequence.

The word address is 017772, and it is assumed that a specific memory bank has been selected. The binary equivalent
of the address is shown below. A read operation is to be performed.

ADDRESS BITS A<17:00>

171161514

|13

o|lo]jo]joOo|O
j¢]

1211

|10

|09{08{07[06]05]04]03]02{01

1
7

[0O]BIT POSITION

O | BINARY

OCTAL

Bits A (13:01) are used to decode the word address. Bit AO1 is sent to the device selector (drawing G110-0-1, sheet
2) and appears at word address flip-flop E11, pin 2 as AO1 H (drawing G231-0-1, sheet 2). Bits A (12:02) are sent to

the Unibus receivers, which are inputs to the associated word address flip-flops. Bit A13 is not used. The input to the
Unibus receiver associated with this bit is connected directly to +5V through jumper J3 (for a 4K memory, J3 is in
and J4 is out). Table 12-3 shows the state of bits A (13:01) and the decoding signals generated by the word address
flip-flops after they are clocked.

12-17

Table 12-3
Word Address Decoding Signals

Address

Bit

Unibus
Receiver

Receiver
Output

Flip-Flop
State

Flip-Flop
Output Signals
te

Input
A0l

set

AOIH=H

A02

reset

AO2H=L

A03

set

A04

AO3H=H, AO3L=L

set

AO4H =H

A0S

set

AOSH=H

A06

set

AO6H =H, AO6L =L

A07

set

AO7H=H

A08

set

AOSH=H

A09

set

AO9H =H, AO9L=L

AlO

set

Al10H=H

All

set

AllH=H

Al2

set

A12H=H,
A12L =L

Al3

reset

Ai3H=L,Al13L=H

The output signals from flip-flops A06, A12, and A13 are not used directly from the flip-flops; they are sent to
gating logic (E22 and E25) and are ANDed with signal TSS H. In this case, only two out of a possible six signals are
generated:

AO6H is low from E22, pin 12 and (A12H . A13L) L is low from E25, pin 8. These signals and the

outputs from the other word address flip-flops are sent to the inputs of the type 8251 decoders to select the
appropriate switches and drivers. READ L is an input to each 8251 decoder. A read operation is to be performed;

therefore, READ L is low.
The decoders, switches, and drivers are shown in drawing G231-0-1, sheets 3 and 4. Using the decoding signals in
Table 12-3 and the operating characteristics of the decoders, it is possible to determine which decoders have been

selected for word address 017772. A decoder is selected only when its D3 input is low. In this case, the selected

decoders are E34 and E46 for the X-line (drawing G231-0-1, sheet 3), and E23 and E8 for the Y-line (drawing
G231-0-1, sheet 4). READ L is low and is sent to input D2 of each decoder; it selects read drivers and switches in
this case. To verify this point, refer to the truth table and diagram in Figure 12-9. Decoder inputs DO and D1 select

the particular switch or driver as shown below.
a.

Decoder E34
D1 is high, DO is high: selects output 3 (pin 10), which is read switch XS07.

Decoder E46
D1 is high, DO is high: selects output 3 (pin 10), which is read driver XPRD7.

¢.

Decoder E23

D1 is high, DO is high: selects output 3 (pin 10), which is read switch YS03.

Decoder E8
D1 is low, DO is high: selects output 1 (pin 12), which is read driver XPRDS.

The last step is to follow the outputs of the drivers and switches to the stack diode matrix (drawing H213-0-1, sheet

2). For the Xdine, the circuit is from driver XPRD7 to diode junction E7-11, across termination 35 to switch XS07.

12-18

For the Y-line, the circuit is from driver YPRDS to diode junction E4-9, across termination 15 to switch YS03. The
termination indicates the point on the stack printed circuit board where the X- or Yine is soldered. Physically, the
wire that is connected across the termination is strung through 64 cores per bit mat (total of 1024 cores in series for
16-bit memory).

12.5 READ/WRITE CURRENT GENERATION AND SENSING

In addition to the addressing and control logic, four functional units are involved in generating current to switch the
cores and detect their state. The X- and Y-line current generators supply the drive current (via switches and drivers);
the inhibit drivers allow Os to be written during a write operation; the sense amplifiers detect 1s during a read
operation; and the memory data register (MDR) temporarily stores data to be written or data that has been read
from the memory. The following paragraphs describe each functional unit and their interrelationship.
12.5.1

Read/Write Operations

The read/write operations are discussed in terms of the interrelation of the current generator, inhibit drivers, sense
amplifiers, and memory data register. Details of operation of each functional unit are discussed in subsequent
paragraphs. Several control signals are mentioned; however, details of their generation and timing are described in
Paragraph 12.8.

For clarity, one data bit (DO7) of the selected word is discussed and the text is referenced to Figure 12-14, which is
a simplified block diagram. Detailed logic for the memory data register (MDR), Unibus receivers and drivers, sense

amplifiers, and inhibit drivers for all 16 data bits is shown on drawing G110-0-1, sheets 3 and 4.

During a read operation, half-select currents flow in the X- and Y-lines for the selected word in each bit mat. These
currents flow opposite to the write currents; therefore, cores in the 1 state are switched to the O state, and cores in
the O state are unchanged. Switching the core from the 1 state to the 0 state induces a voltage pulse in the sense
winding. This pulse is detected by sense amplifier E52 as a differential voltage on input pins 6 and 7 that exceeds the
threshold reference voltage. This pulse is amplified and when STROBE O H is generated at pin 11, the output of
sense amplifier ES2 goes high. Just prior to the strobe signal, the control logic generates RESET O L, which clears
(resets) flip-flop E54. The sense amplifier output is inverted by E56 and sent to the preset input (pin 10) of MDR
flip-flop ES4. A low on the preset input sets the flip-flop: its 1-output (pin 9) is a high and its O-output (pin8)isa
low. The high from pin 9 of the flip-flop is sent to input pin 1 of the Unibus driver E21. The other input to thisOgate
for
is the data out signal. When the control logic generates DATA OUT H, the output of E21 is low (logical
via
device
requesting
the
to
sent
is
and
D07
bit
of
memory logic and logical 1 for Unibus logic). This is the readout
the Unibus. Timing diagrams for the sense operation are also shown in Figure 12-14.

must be
The read operation is destructive: all cores at the specified location are now 0. The data that was read set
state;
the
in
still
is
E54
Flip-flop
operation.
read
the
follows
restored by a write operation, which immediately
generates
logic
control
The
E53.
gate
NAND
of
9
pin
input
to
therefore, its O-output (pin 8), which is low, is sent
(pin 8 is
the inhibit driver control signal TINHO H, which is the other input to gate E53. The gate is not assertedhalf-select
the
oppose
to
line
inhibit
the
in
current
inhibit
no
With
high), and the inhibit driver is not turned on.
Y-line current, a 1 is written back into the appropriate cores.

of sense
In this example, if bit DO7 is a O in core, it does not switch during the read operation and the output O-output
its
amplifier ES2 does not go high. Flip-flop E54 remains cleared (reset): its 1-output (pin 9) is low isandhigh
(logical 1
E21
driver
Unibus
of
output
the
H,
OUT
DATA
generates
logic
control
(pin 8) is high. When the
gate
NAND
to
sent
is
for memory logic and logical 0 for Unibus logic). The O-output of flip-flop E54, which is high,
8 to
pin
E53,
at
signal
output
E53. During the subsequent write operation, TINHO H is generated, producing a low
from
1
a
prevents
and
activate the inhibit driver which in turn produces a current that opposes the Y-line current
being written into this bit of the selected word.

12-19

INHIBIT

SENSE
AMP

DRIVER

INPUT

[’:3

STROBE G H

T INH O H

NETWORK

INVERTER

Jeio

6 o REC

2] PRE

1
~n

E21

DRIVER

E54
BIT DO7

LOAD O H

! CcL

CLR

DO7

———J
8

DATA OUT H

DO7

RESET O L

UNIBUS DATA LINES D<I5:00>

THRESHOLD
VOLTAGE

SENSE

_ SENSE

AMP

FROM

STACK

INPUT

LINE

OUTPUT ES2 (6-7)

RESET O L

]

STROBE H

| L

SENSE AMP

I o) |

OuUTPUT

E56

OQUTPUT

‘I

ES54
OUTPUTS

DATA OUT H
E21

ouTPU7T

TO UNIBUS

I
—————

l‘

/- -~
— -

I
n-1100

Figure 12-14

Interconnection of Unibus, Data Register, Sense Amplifier, and Inhibit Driver

The read/write operation that has been discussed is a read/restore operation
(DATI). The requesting device wants to
read a word from memory, and as an internal requirement, the
memory must restore the word by writing it back
into core. In this case, the MDR flip-flops are preset by the sense
amplifier outputs when 1s are read from the core.
The MDR flip-flop outputs are used in the subsequent write (restore)
operation to control the inhibit drivers. If the
requesting device wants to write a word into memory (DATO),
it must load the data into the MDR flip-flops. The

12-20

requesting device then asserts the data on the Unibus, from which it is picked off via Unibus receivers. In this
example, bit D07 is sent to pin 7 of Unibus receiver E10. Bit D07 is inverted by the receiver and sent to the D-input
(pin 12) of flip-flop E54. At the start of the DATO operation, the control logic generates LOAD O H, which clocks
the flip-flop. If the D-input is high, E54 is set and its O-output is low. Control gate E53 is not asserted by TINHO H,
and the inhibit driver is not turned on. A 1 is written into the selected core. If the D-input is low, E54 is reset and its

O-output is high. Control gate E53 is asserted by TINHO H, and the inhibit driver is turned on. A 0 is written into
the selected core. Because RESET and STROBE are inactive in this mode, the read operation is used only to
magnetically clear all the cores to the O state.
12.5.2

X- and Y-Current Generators

Two identical current generators are provided: one each for the X- and Y-drive lines. They generate the current
pulses that are used during read and write operations to switch the cores. The current generators and associated
reference voltage supply are shown in drawing G231-0-1, sheet 2. Figure 12-15 shows the Y-current generator and
reference voltage supply.

+5v

!2R83

b oS

dee>?

MOUNTED ON STACK

-1

TWID H

RC52

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cst

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TO X CURRENT

GENERATOR

—15Y

11-1104

Figure 12-15 Y-Current Generator and Reference Voltage Supply

Optimum core switching requires repeatable current pulses of constant amplitude with a linear rise time. The current
generator and reference voltage circuit provide current pulses that meet these requirements. The amplitude of the
output current pulse is determined by the reference voltage circuit; the rise time is determined by an RC circuit in
the current generator; and pulse duration is determined by the length of the triggering pulse TWID H.

12-21

During the quiescent state of the current generator, input transistor
connected to the cathode of diode D62, which reverse biases

Q8 is on; its collector voltage is 4.7V, and it is

it. The anode of D62 is connected to the emitter of

transistor Q4, which is the output of the reference voltage
circuit. In this state, D62 blocks the output from the
reference voltage circuit to the current generator. With Q8
on, both output transistors Q9 and Q10 are turned off,
and the current generator is off.

Operation of the current generator is triggered by a high
TWID H signal from the control logic. TWID H is double
inverted by two E6 inverters and sent to the base of Q8,
which turns it off. When Q8 is cut off, capacitor C52 starts
charging, which provides base drive to output transistors
Q9 and Q10 and they begin to conduct. With Q8 off, its
collector goes negative until it reaches the forward bias
level of D62, which is the value of the reference voltage
minus the voltage drop across D62. The rise time of the
current pulse is determined by the time constant of C52,

R87, and R88. The amplitude of the pulse is determined
by the value of the reference voltage. When TWID H goes
low again, the current generator is turned off and the output
pulse is terminated.
A resistor network in the base circuit of Q4 (in the reference
supply) is used to

set the amplitude of the current

generator to approximately 410 mA. The total
resistance of parallel network R90, R91, and R92
is changed

by the

configuration of jumpers J1 and J2. The amplitude of the
current generator output pulse is factory set as close as
possible to 410 mA at 25°C. It should not be changed in the field.
The base circuit of Q4 is temperature compensated by a resistor
ensures that

the

and thermistor that are mounted on the stack. This

amplitude of the current generator output pulse
remains within specified tolerances over a

temperature range of 0°C to 50°C. This temperature compensation
12.5.3

is approximately ~0.8 mA/°C.

Inhibit Driver

A detailed schematic of the inhibit driver for bit DO7 is shown in Figure

(drawing G110-0-1, sheets 3 and 4).

12-16; it is typical of all 16 inhibit drivers

When the inhibit driver is off, none of the currents shown in the schematic are

flowing. Transistor Q7 is held off by
the negative voltage on its base. The output of NAND gate ES3 goes low (ground)
when this inhibit driver is
selected. Current i, flows into the output circuit of E53 from the +5V supply via
resistor R87 and the primary
winding (terminals 15 and 16) of transformer T8. An equal current is induced
in the base-emitter circuit of Q7,
which is connected to the transformer secondary winding (terminals 1 and
2). This base current overcomes the
reverse bias voltage and turns on Q7. Current i, and therefore induced-current
iy are determined by resistor R87 and
the reflected base-emitter voltage Vpe of Q7. When Q7 is turned on, current
flows from ground through Balun
transformer T7, isolation diodes DI3 and D14, and the sense/inhibit winding
to the common inhibit terminal

(07IN). The Balun transformer balances the two inhibit half-currents. At terminal
O7IN, the full inhibit current
flows through resistor R72 and Q7 to - 15V. The value for the inhibit current is calculated
as follows:

i,inh =ISV-V, sat Q7 “Vhe diodes

R72+R core mat

=15-0.8-12 = =3 =740mA
Each leg of the sense/inhibit winding sees half the inhibit current:

the rise time of the current.

approximately 370 mA. Capacitor C55 decreases

The inhibit driver is turned off when the output (pin 8) of gate E53 goes
from low to high. At turn-off time, the
back emf caused by the stack inductive reactance tries to drive the collector
of Q7 highly positive; however, diode
D43 clamps this voltage to ground. When the output of ES3 goes high
(approximately +3.2V), its output pull-up
transistor (an integral part of the gate circuit) tries to drive the turn-off
current ia in the opposite direction through
the transformer primary winding. An equal current induced in the secondary
winding removes the forward bias from

12-22

the base of Q7 and turns it off. With Q7 off, all dynamic current flow ceases in the circuit and the negative voltage
on the base of Q7 keeps the circuit turned off until the output of gate E53 goes low again.

Capacitor C74 allows the gate to pump reverse current i into the transformer primary; it also helps to decrease the
turn-on time of Q7. Diode D59 prevents reverse breakdown of the emitter junction of Q7.

(
X3

X1
‘o

/*’_Nm

b
4

+5V

STROBE O H

IRd
07SB

TH = 22mV

:: R58

g Ri14

)

RS7 3

16
+5V

T0 E54

MDR DO7

SENSE AMP

ouTPuT

-5V

TINHO H —]
9
DO7 (0) H ——

i
8 -'_‘_
—_—

T8
18

'4 Yopse

RB7 1; ;J]:cm
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Figure 12-16

12.5.4

Sense Amplifier and Inhibit Driver

Sense Amplifier

A detailed schematic of the sense amplifier circuit for bit DO7 is shown in Figure 12-16; this circuit is typical of all
16 sense amplifier circuits (drawing G110-0-1, sheets 3 and 4). The circuit consists of the sense amplifier,

terminating network for the sense/inhibit winding, and threshold voltage network.

The sense amplifier input (E52, pin 6 and 7) is across the sense/inhibit winding (points 07SB and 07SA). Resistors
R13 and R14 are matched to terminate the sense/inhibit line in the desired impedance. Practically speaking, during
the sense operation, the inhibit driver connection is an open circuit through the driver transistor Q7. The effect of
the inhibit driver circuit, Balun transformer T7, and isolation diodes D13 and D14 can be ignored during the sense
operation, because the diodes are reverse biased.

Sense amplifier E52 is one half of a dual IC package (type 7528). A simplified block diagram of the package is
shown in Figure 12-17. The two identical circuits are marked 1 and 2. Each one consists of a preamplifier and sense

12-23

amplifier. The output of the preamplifier is available as a test point to observe the amplified core signal and to

facilitate accurate strobe timing. Both circuits share a reference voltage (or threshold voltage) amplifier (pins 4 and

5). In this application, pin 4 is grounded and a positive threshold voltage of approximately 20 mV is supplied to pin
5. This voltage is obtained from the +5V supply through resistor voltage divider R57 and R58; C40 is a bypass
capacitor. Operation of the sense amplifier is discussed in Paragraph 12.5.1.

VeeTM

Vect

[a]

[re]

CIRCUIT 1

15]

SA1
INPUT

1
N

SB1

—

l—_-

DIFF—INPUT | +V
THRESHOLD

TEST POINT

T——Iw OUTPUT 1

STROBE

VOLTAGE

—f

SA2

INPUT 2

:i E

}12 OUTPUT 2

SB2

CeExT

(2]
z

TEST POINT

10]
CIRCUIT

11-1103

Figure 12-17

12.5.5

Type 7528 Dual Sense Amplifiers With Preamplifier Test Points

Memory Data Register

The memory data register (MDR) is a 16-bit flip-flop register that is used to store a word after it is read out
of the

memory; or to store a word from the Unibus prior to its being written into the memory. The MDR
is composed of

eight 74H74 dual high-speed D-type flip-flops: bits DOO-DO7 are shown in drawing G110-0-1, sheet
3 and are
identified as E54, E57, E60, and E63; bits D08-D15 are shown in drawing G110-0-1, sheet 4 and are identified
as
E42, E4S, E48, and E51.
At the start of a memory operation, the MDR is cleared directly via the clear input (pin 1 or pin
13) of each
flip-flop: the clear signal is RESET O L for bits D00-D07 and RESET 1 L for bits DO8-D15.

The operation of the MDR during a read/restore operation (DATI) and a write operation (DATO) is discussed
in
Paragraph 12.5.1.

12.6

STACK DISCHARGE CIRCUIT

The stack discharge circuit assists the stack capacitance in recovering and shortens the rise time of the stack
It also reduces unwanted currents in the seven unselected lines associated with the selected driver.

current.

Figure 12-18 shows the stack discharge circuit. Its output is taken from the emitter of transistor Q2 and goes
to the
junction of each X- and Y-read/write switch pair via a resistor. This common interconnection is labeled
Vo. It is
desired that Vo = OV (ground) during a read operation; and VO = -15V during a write operation. The effective

capacitance associated with each line is shown as Cstack:

12-24

stack

+5V

R773

3R79

R783%

WRITE SWITCH

READ H

5
R80S

¥ D54

ps3 v

055

W= -

READ SWITCH

¥ D56

<
C STACK

D57

RE1%
s

I
=

-15V

TO ALL OTHER READ/WRITE
SWITCH PAIRS IN X AND
Y AXES
t1-104

Figure 12-18

Stack Discharge Circuit

During a write operation, READ H is low; it is inverted and ANDed with TWID H at NAND gate E4. The low output
(pin 11) of E4 is inverted by E6 and sent to the cathode of diode D51, which reverse biases it. The emitter of Q1
becomes more positive, overcomes the constant positive base bias, and turns on transistor Q1. When Q1 conducts, it

provides base drive for Q3, which also turns on. When Q3 conducts, it reduces the base drive on Q2 and it tumns off.

The emitter voltage of Q2 goes to approximately - 14V, which is Vo on the switch node for the stack. Diode D57
prevents hard saturation of Q3; diode D55 holds Q2 off. During a write operation, Vo = -14V and the stack
discharge circuit is considered to be turned on (input transistor Q1 is on).
During a read operation, READ H is high: it is inverted and ANDed with TWID H at NAND gate E4. The gate is not
asserted and its output (pin 11) is high. This signal is inverted by E6 and sent to the cathode of diode D51, which
forward biases it. The voitage on the emitter of Q1 produced by the current through R77 and D51 is not enough to
overcome the constant positive bias and Q1 is turned off. With Q1 off, Q3 looses its base drive and turns off. Now,
D55 cannot hold Q2 off. As long as the stack capacitance is charged negatively, base current exists for Q2 and it
remains on. The stack capacitance now charges in the positive direction until it reaches ground potential. During a

read operation, Vo = OV and the stack discharge circuit is considered to be off (input transistor Q1 is off).

Figure 12-13 shows how the stack discharge circuit reduces unwanted currents on the seven unselected lines
associated with the selected driver.

During a read operation, the stack discharge circuit is off and Vo = OV. The current generator drives the read driver
node of the stack towards ground; the current generator output is clamped to ground by diode D61. The anodes of
the eight read diodes are at ground. The stack discharge circuit is on and the cathodes of the seven unselected diodes
are also at ground, which back biases them off. The read switch pulls the cathode of the selected line towards - 14V,
which forward biases it and allows conduction through the diode. Current flows only through the selected line.
Reverse biasing of the diodes in the unselected lines prevents current from flowing between the unselected nodes and
the selected read driver. The stack discharge circuit performs the same task during the write operation by back
biasing the anodes of the diodes in the unselected lines with -14V.

12-25

12.7

DCLO CIRCUIT

A circuit on the G231 Driver Module (drawing G231-0-1, sheet 2) opens the -15V supply line to the current
generators when power is interrupted to the power supply. When power is interrupted, the +5V supply is lost and

the operation of all logic is indeterminate. In this state, it is necessary to cut off the -15V supply to the X- and
Y-line current generators to prevent them from destroying stored data. The circuit that performs the - 15V cutoff is

called the DC LO circuit (Figure 12-19).

+5vV

BUS DC

LO L

FROM UNIBUS

-15V

TO CURRENT GENERATORS

-15V

FROM

SUPPLY

n-105%

Figure 12-19

DC LO Circuit, Schematic Diagram

The -15V supply for the X- and Y-line current generators passes through transistor Q7 in the DC LO circuit. Q7
must be turned on for the ~15V to reach the current generators. The circuit monitors BUS DC LO L from the power

supply via the Unibus. This signal is sent to the base of transistor Q5. When power is on, BUS DC LO L is high (not

asserted).

The voltage across R96 forward biases Q5 and it turns on, which turns on Q6. The conduction through Q5 and Q6
forward biases Q7 which turns it on. The -15V flows through Q7 to the X- and Y-line current generators.
When power is interrupted, BUS DC LO L goes low (asserted). QS5 is now reverse biased and it turns off, which turns
off Q6. With Q5 and Q6 off, Q7 is also turned off, which opens the —15V line to the current generators. This circuit

still functions when BUS DC LO L is asserted even if the +5V supply drops to zero.
12.8

OPERATING MODE SELECTION LOGIC

When the memory is addressed by the master device, one of four bus transactions is selected. The transaction (or

operation) selected is determined by the states of control bits CO1 and C0OO and address bit AOO as placed on the
Unibus by the master device. Table 12-4 shows the states of these bits for each transaction.
The logic that decodes the mode and byte control bits is shown in drawing G110-0-1, sheet 2; it appears at the
bottom of the sheet and is identified as the byte masking logic. Bits BUS CO1, BUS C00, and BUS AOO are taken

from the Unibus to three E29 receivers. One input of each gate associated with CO1 and COO is connected to the
output of the PROTECT LOW gate (E29 pin 3). Both inputs to this gate are tied to +5V so that its output is always
low. For troubleshooting purposes, a jumper (W11) can be installed that makes the gate output high, which allows
only DATI operations to be performed regardless of the states of bits CO!1 and CO0O. This jumper hardwires the
memory as a read-only device.

12-26

Table 12-4

Selection of Bus Transactions

Mode Control
Transaction

Mnemonic

Data In

DATI

C(01:00)
00

Byte

Control

Octal

A00

Function

Data from memory to master. Memory

performs operations.

Data In,
Pause

DATIP

Data from memory to master. Restore
operation is inhibited. Must be
followed by DATO or DATOB: Read
operation is inhibited.

Data Out

DATO

Data from master to memory (words).

Data Out,
High Byte

DATOB

Data from master to memory. High
byte on data lines D (15:08).

Data Out,

DATOB

Data from master to memory. Low

Low Byte

byte on data lines D (07:00).

Lamoe,

The outputs of the three E29 receivers (C01, C00, and A0O) are sent to the byte masking logic to generate LOAD 0
H and LOAD 1 H and to qualify a group of gates, which are enabled by control signals to generate RESET 0 L,
RESET 1 L, STROBE 0 H, STROBE 1 H, and DATA OUT H. The logic also conditions the D-input of the PAUSE
flip-flop (E4, pin 12) to allow it to be set or reset. It also applies conditioning signals to the wired-AND that provides

the clocking signal to the slave synchronization (SSYN) flip-flop. The PAUSE flip-flop and the SSYN flip-flop are
part of the control logic.

The signals generated for each bus transaction are shown in Table 12-5. The memory operational sequences are
discussed in subsequent paragraphs. To avoid confusion in interpreting the transactions listed in Table 12-5, the
purpose of the PAUSE flip-flop is discussed briefly. During DATIP, the PAUSE flip-flop is set during the read
operation, which inhibits the restore (write) operation. The DATIP must be followed by a DATO or DATOB on the
same address. The DATO or DATOB that follows a DATIP is shorter than a standard DATO or DATOB because the
initial read operation is eliminated. In Table 12-5, the suffix PAUSE L identifies the standard transactions; the suffix
PAUSE H identifies the DATO and DATOB transactions that must follow a DATIP.
12.9

CONTROL LOGIC

The control logic generates the precisely timed signals that initiate and stop the memory operations that are
requested as a result of the decoding of the bus transaction. The heart of the control logic is the delay line timing
circuit. For better understanding, the timing circuit, slave sync circuit, pause/write restart circuit, and strobe
generating circuit are described separately. Each bus transaction is also discussed in detail. The discussion is to the
detailed logic level but the signals are not traced through each component. The text is referenced to logic drawing
G110-0-1, sheet 2 and the timing diagrams in drawing MM11-L-3.

12-27

Table 12-5

Generation of Memory Operating Signals

Mode

Byte

Mode

Control

PAUSE

C01

Flip-Flop

A00

State of

CO00;

Signals Generated

Operation Sequence

Xl [e=]
—

—

l3l51g|a

—

Z1E|2|2|2|2]5
172}
(%] ‘é
K&j
~
d
[
DATI

0 | Reset

Read-Restore.

DATIP

Read-Pause. Restore inhibited by PAUSE flip-flop.

| Reset-

Set

DATO

0 ] Reset

Clear-Write.

DATO

0 | Set

Write. Must follow DATIP.

DATOB

PAUSE L

| Reset

Clear-Write selected byte

PAUSE L

0. Clear-Restore nonselected byte 1.

DATOB

I | Set

Write selected byte 0. Re-

PAUSE H

store non-selected byte 1.
Must follow DATIP.

DATOB

1 | Reset

PAUSE L

Clear-Write selected byte
1. Clear-restore nonselected byte 0.

DATOB

PAUSE H

1 { Set

Write selected byte 1. Restore non-selected byte 0.

Must follow DATIP.

12.9.1

Timing Circuit

The heart of the memory control logic is the timing circuit. When activated, it generates a series of precisely timed

signals that control memory operation. The major component of the timing circuit is a delay line (DL1) with
multiple 25-ns taps (drawing C110-0-1, sheet 2). The delay line outputs are gated to produce the control signals.

Figure 12-20 shows the timing of the delay line outputs and the timing of the control signals obtained by gating
these outputs. A brief statement of the function of each control signal is included. Absolute timing is obtained from

the engineering timing diagram (drawing MM11-L-3). The discussion is referenced to Figure 12-20 and the control

logic drawing G110-0-1.

When the system is turned on, the processor asserts BUS INIT L on the Unibus. This initializing signal is sent to pins

6 and 7 of bus receiver E7. It is inverted by E7 to produce a high, which is sent to pins 9 and 10 of the memory
select reset (MSEL RESET) gate E16. The output (pin 8) of E16 is low and is used to clear (reset) MSEL flip-flop E2
via the 100-ns delay DL3. The output of E7 is also inverted by E18 to provide a low that clears read/write (R/W)

flip-flop E3. The output of E7 is also inverted by E15 to provide a low that clears PAUSE flip-flop E4. The low

BUS MSYN L]

450ns

400

{lNiTIATES MEMORY CYCLE, RESETS SSYN FF E4

)
I

s— |
DL1 DELAY
TAPS

LINE

(TM
2

350

300

250

200

150

100

|
|

{sters DELAY FF £28 BOTH IN READ AND WRITE

DEL FF RES L
(6L:8H) E27-P6
H

(2L-4H-READ H) E7-P3

RESETS DATA £F's {BITS 0-15) AND STARTS STROBE DELAY.

{USED ONLY DURING READ.

]

RESET

ATED TOGETHER AS SHOWN BELOW

{CONTROLS SWITCH TIMING DURING READ AND DRIVER TIMING DURING WRITE.

TNAR H

(L+sL) E1A- P

CONTROLS TORH DURING READ AND TSSH DURING WRITE. CONTROLS

TWID

{WRIYE CYCLE

CURRENT GENERATOR AND STACK DISCHARGE TIMING USED AS TINH DURING

(1L+7L) EX4-P8

RESETS MSEL {MEMORY SELECTED) FF E2 AT END OF READ CYCLE IN DATIP

MSEL RESET H

MODE; AT END OF WRITE CYCLE IN ALL OTHER MODES.

(6H - 8L) E26-P13

R/W

RESET H

(8H-9L) E26-P10

{RESETS R/W (READ/WRITE} FF £3 AT END OF READ CYCLE

{
b

{ADJUSTED TO GIVE PROPER DELAY FROM READ CURRENT TO STROBE

!
|

STROBE DEL L E36-P4

sTroBE H E17-P3

I A

STROBE 0s £28-P3

GENERATES NARROW WIDTH 135 ns] STROBE PULSE FROM TRAILING EDGE OF
STROBE DELAY.

{sers AT START OF CYCLE UNLESS PAUSE FF E4PIISSET. AS 1T RESETS, IT

READ H _.rE?S -P9

GENERATES WRITE RESTART UNLESS IN DATIP MODE

WRITE

RESTART L £25-P3

CLOCKS DELAY FF E28 TO START WRITE TIMING CHAIN

LI_ {DOES NOT OCCUR IN DATIP

CLOCKS (R/W. AD, €0, CI FF: ON G110, (AT-A13 FF) ON G231 IN ALL MODES.

IN DATO AND DATOB MODES, T BECOMES LOADO, 1H

E14-PE

CLK{ H

GATES SENSE AMPS TO DATA LATCHES DURING READ CYCLE
TRAILING EDGE SETS SSYN FF E4 DURING DATi - DATIP MODES.

CLOCKS MSEL FF E2 IN ALL MODES

CLOCKS SSYN FF E4 1N DATO AND DATOB MODES

'A\

cLkz W EI5-P4

{smoaes DATA FROM BUS TO DATA FF 0 15IN DATO AND DATOB MODES

E34-P11

LOAD t

{SETSSSVN FF E4 AS SHOWN

DATI, DATIP

CLK SSYN H E4—P3/ uDATO. DATO B

DATA OUT H STROBES DATA FROM DATA FF 0 15 YO UNIBUS IN DATI AND DATIP
MODES.

SSYN H BECOMES BUS SSYN L WHICH KEEPS MSEL FF FROM SETTING

DATAOUT H E6-P3

SSYN H ES-P2
w

~
N

TIMING CHAIN READ OR WRITE

11-1108

Figure 12-20 Basic Timing and Contro! Signal Functions

12-29

master asserts BUS MSYN L to bus receiver E23, pin 12 of E1 is high
also. The output of E1 (pin 8) goes low and is
sent to pin 13 of ES, pins 4 and 5 of E14, and pin 1 of delay line DL2.
E14 inverts the low from El to start the

positive CLK 1 H pulse. DL2 provides a 30-ns delay for the low signal from
E1, which is inverted
positive CLK 2 H pulse. The output (pin 3) of DL2 is also sent to the preset

by E15

to start the

input (pin 4) of MSEL flip-flop E2, and

pin 6 goes low which in turn is fed back to pin 10 of E1 to disable it.
The output (pin 8) of E1 is now high, and this
signal terminates both clock pulses (CLK 1 H and CLK 2 H) via gates E14
and E15. These pulses are approximately
50-ns wide.

Gate ES also inverts the low from E1 because pin 12 (WRITE RESTART L) of

ES is high. The positive transition at
the output (pin 11) of ES clocks delay (DEL) flip-flop E28 which sets it.
Pin 5 of E28 is high and is connected to
pins 1 and 2 of DLI driver gate E34. The low from the E34 output (pin
3) is the input to delay line DL1. This signal

remains low for approximately 225 ns until DEL flip-flop E28 is cleared
by DELAY FF RESET L. This provides

negative pulse that propagates through the delay line and can be picked off

at 25-ns intervals.

DL1 taps 2,4,5,6,7, 8, and 9 are used to generate control signals. Figure
12-20 depicts each control signal and
relates it to logic drawing G110-0-1, sheet 2.
DELAY FF RESET

Tap 6L is inverted by E15 and sent to pins 3 and 5 of 3-input NAND gate E27;

the third input (pin 4) is tap 8H. The
output (pin 6) of E27 clears the DEL flip-flop E28; however, it is ORed with INIT
L in gate E28 (pins 9 and 10) and

inverted by E38, pin 11 so that either (6L . 8H) or BUS INIT L can produce
DELAY FF RESET L, which clears

E28 via its clear input (pin 1). This signal is generated in both read and write operations.
RESET H

Tap 2L, tap 4H, and signal READ H are gated to generate RESET H, which
triggers the strobe delay circuit and

generates RESET O L and RESET 1 L during the read operation only.
Tap 4H and READ H (high during read
operation) are ANDed at pins 10 and 9 of E17. The low output of E17 is
ANDed with tap 2L in gate E7. The high

output (pin 3) is RESET H.

TWID H and TNAR H
The 0-output of DEL flip-flop E28 is ORed with tap 5L and

tap 7L in separate gates (E14) to produce signals TWID
H and TNAR H. Tap 5L is sent to pin 13 of E14; the other input
to this gate (pin 12) is from the O-output of DEL
flip-flop E28. Tap 7L is sent to pin 10 of another E14 gate;
pin 9 of this gate is also connected to the O-output of
DEL flip-flop E28. These gates are 2-input NAND gates (type
7437); however, they are shown as logically equivalent
negative-input OR gates, because it is desired to have them
asserted high (logical

asserted.

At the start of a read or write cycle, just before E28 is set,

1) when TWID H or TNAR H is

TNAR and TWID are low because both inputs to each

gate are high. E28 is set and pins 12 and 9 of E14 go
low; TNAR and TWID are both high,

TNAR and TWID pulses simultaneously. When taps 5 and 7 go
At the end of the read or write cycle, E28 is cleared (taps

which starts the positive

low (E28 is still set), TNAR and TWID remain high.

S and 7 are still low) and TNAR and TWID still remain

high. When tap 5 is high again, TNAR goes low because
both inputs (pins 12 and 13) of E14 are high. This

terminates the positive TNAR pulse. Approximately 50-ns
later, tap 7 is high again and TWID goes low, terminating
the positive TWID pulse. In summary, TNAR H and TWID
H are started together by setting DEL flip-flop E28
before taps 5 and 7 are low; TNAR H and TWID H are not effected
when taps 5 and 7 go low. Signals TNAR H and
TWID H are terminated when taps 5 and 7 return high. The
intervening clearing of E28 does not affect TNAR H or
TWID H.

output of E15 is double inverted by two E38 gates to clear the DEL
flip-flop E28. The master places the address,
mode control state, and data (if required) on the Unibus. The device
address is decoded and DSEL H is generated
and sent to pin 13 of El, which is one of four input signals (pins 10, 11, 12, and
13). Pin 11 is high via the O-output
of MSEL flip-flop E2. SSYN flip-flop E4 is preset, making pin 10 of
E1 high via its 1-output (pin 5). When the

Signals TNAR H and TWID H provide various control functions related to the operation of the switches, drivers,
current generators, inhibit drivers, and stack discharge circuit. At this point, the discussion digresses to follow TNAR
H and TWID H through some additional logic in order to understand their functions. The logic is spread throughout
several engineering drawings. To simplify the discussion, all the logic is shown in Figure 12-21.

READ H

TWID H

—4

READ H]

WRITE H

€6

READ L

7O ALL SWITCH AND

TO X-AND Y CURRENT
GENERATORS

1 £e 2

DRIVER DECODERS

DISCHARGE CIRCUIT
TO STACK

1—=ON

I—

O—eOFF

4
o

G6110-0-1SH2
—_

e—

]

3 __ FOR SWITCH DECODERS
TO

DECODING

LOGIC

TSS H ONLY

R/WFF
E3
PIN 8
O—+READ

1—=WRITF

G231-0-1SH3 8 4
11

Figure 12-21

Axx—l—} ¢
EX

C
10} £25 P 8 B,B

]

TOR H

JTINHOH

TINH 1 H

TO DRIVER
DECODERS ONL'

TO INHIBIT DRIVERS

FOR
BITS D<O7:00>
TO INHIBIT DRIVERS

| FOR BITS D<15:08>

TWID H and TNAR H Control Logic

Signal TWID H is ANDed with the 0-output (pin 8) of R/W flip-flop E3 at pins 9 and 10 of gate E25. With TWID H
high, E25 is asserted only when E3, pin 8 is high; this occurs only during a write operation. The output (pin 8) of
E25 is inverted by El4 to procure TINH O H and TINH 1 H. The output of E14 is physically divided into two
paths: TINH O H activates the inhibit drivers for bits D (07:00), and TINH 1 H activates the inhibit drivers for bits
D (15:08). These signals do not leave the control module because the inhibit drivers are also on this module.

Signals TWID H and TNAR H leave the control module (G110) and are sent to the drive module (G231). TWID H is
sent to pin-4 of E2R, and TNAR H is sent to pin 2 of E2W. Gates E2 and E4 are marked W and R in Figure 12-21 to

show their association with write or read operations. READ H is sent from the 1-output (pin 9) of R/W flip-flop E3
on the control module to pin 9 of inverter E6 on the driver module. READ H is high during a read operation and

low during a write operation. Assume that a read operation is selected. READ H is high at pin 9 of E6 and is sent to

pin 5 of E2R to be ANDed with TWID H. This gate is asserted and its low output is sent to pin 12 of negative-input
NOR gate E2, which inverts it to produce TDR H. This signal is a decoding input for the memory read/write drivers
only. Gate E2W is not asserted because WRITE H, which is the inversion of READ H, is low. Therefore, TWID H
controls decoding signal TDR H during a read operation. During a write operation, READ H is low and WRITE H is

high. Signal TDR H is asserted via the output of gate E2W, using the ANDing of WRITE H and TNAR H. Decoding
signal TDR H is controlled by TNAR H during a write operation.

12-31

A similar logic network is used to control signal TSS H, which enables six decoding signals that are in turn used to

control memory read/write switches only. When gates E4W, E4R, and E4 are used, TSS H is generated at the output
(pin 3) of E4. During a read operation, TNAR H controls enabling signal TSS H; signal TWID H controls TSS H

TWID H controls the operation of the X-and Y-current generators. During read and write operations, when
TWID H
is high, the signal is double inverted by two E6 inverters to turn both current generators on.
The TWID H

signal also controls the operation of the stack discharge circuit. It is ANDed with WRITE H at pins 13
and 12 of NAND gate E4. The output (pin 11) of E4 is inverted by E6 to control the stack discharge circuit.
This
circuit is considered to be turned on when the output (pin 2) of E6 is high. This occurs during a write
operation

when TWID H and WRITE H are both high.

Although not part of the timing circuit, Figure 12-21 shows READ H inverted by two E6 inverters to become

READ
L, which is a decoding input to all 8251 decoders for the memory switches and drivers. During a read operation,

READ H is high and READ L is low, which selects only read switches and drivers; conversely, during a write

operation, READ L is high, which selects only write switches and drivers (Paragraph 12.4.3.2).

MSEL RESET

The memory select (MSEL) flip-flop E2 is cleared (reset) at the end of
a read operation in DATIP mode and

at the
end of a write operation in all other modes (DATI, DATO, and DATOB) by signal MSEL RESET L. The
MSEL
RESET L signal is generated at the output (pin 8) of gate E16 (a type 74H53 2-2-2-3 input AND-OR-invert
gate).
Three of its four AND inputs are used to facilitate the various methods used in generating MSEL RESET
L (Figure
12-22).
When the system is turned on, the processor asserts BUS INIT L on the Unibus. The output of bus receiver

E7 is
high; this high output is sent to pins 9 and 10 of E16 to generate MSEL RESET L at its output (pin 8). The MSEL

RESET L signal is passed through a 100-ns delay line (DL3) to the clear input (pin 1) of MSEL flip-flop
E2, which
directly clears (resets) it. All memory operations start with E2 cleared; however, this flip-flop is set approximately
75 ns after the processor asserts BUS MSYN L. It remains set until it is cleared by one of the following
operations.

R/W

E26

PIN 4

DATIP

o%!

12
—

FF E3 PIN 9

1-0UTPUT

1
3

TAP 8

oL1 TAP 6

BUS

INIT

———

10 12

—————4——Q
,

R/W

€26

2
€7

‘

[y
S ¥

DL!

0-0UTPUT
PAUSE

E4 PIN

O-0UTPUT

Figure 12-22

Generation of MSEL RESET L

12-32

MSEL RESET L
TO CLEAR INPUT

OF MSEL FF E2

‘A

during a write operation.

In the DATIP mode, pin 12 of AND gate E6 is high; in all other modes, it is low, disqualifying E6. A read operation

is performed in DATIP, and R/W flip-flop E3 is set. The 1-output of E3 is sent to pin 13 of E6. At this time, pin 13
is high and a high is generated at the output (pin 11) of E6. This AND input is qualified when pin 1 is also high,
which occurs when DLI tap 6 is high and DL1 tap 8 is low. Tap 6H is inverted by E35 and sent to pin 12 of E26.
Tap 8L is sent directly to the other input (pin 11) and the gate is asserted; this gate sends a high to pin 1 of E16,

which generates MSEL RESET L at the output (pin 8) of E16. This low signal clears MSEL flip-flop E2 at the end of
the read operation (timed by 6H and 8L).
In all other modes (DATI, DATO, and DATOB), signal MSEL RESET L is generated at the end of the write
operation (except DATO or DATOB following a DATIP). The R/W flip-flop is set, making its O-output (pin 8) low,
which disqualifies the 3-input (pin 4, 5, and 6) AND gate in E16.
Taps 6H and 8L cannot qualify this AND input or the other AND input (pins 1 and 13) because the memory is not
in the DATIP mode. Therefore, the read operation is completed and MSEL RESET L is not generated. The write

operation is now started and the R/W flip-flop is cleared, which puts a high on input 5 of E16. Input 6 is high

because the PAUSE flip-flop is reset (pin 8 is a 1). Now, when tap 6 is high and tap 8 is low, input 4 of E16 is high.
This generates signal MSEL RESET L to clear MSEL flip-flop E2 at the end of the write operation. This circuit
performs the function of a memory bus flip-flop.

R/W RESET

The timing for the generation of the signal to clear (reset) R/W flip-flop E3 is obtained from taps 8 and 9 of DL1.
Tap 9 is sent directly to pin 8 of E26. Tap 8 is inverted by E35 and sent to pin 9 of E26. When tap 9 is low and tap
8 is high, E26 is asserted (output pin 10 is high). This signal is sometimes called R/W RESET H. It is ANDed with
READ H at pins 2 and 1 of NAND gate E18 to generate R/W RESET L. When this signal is a low, it directly resets
R/W flip-flop E3 via its clear input (pin 13). READ H is high when the R/W flip-flop is set because it comes from the
l-output (pin 9). The remainder of the control signals shown in Figure 12-20 are discussed in the circuit descriptions

contained in Paragraph 12.9.2, Slave Synchronization Circuit; Paragraph 12.9.3, Pause/Write Restart Circuit; and
Paragraph 12.9.4, Strobe Generating Circuit.

12.9.2

Slave Synchronization (SSYN) Circuit

Slave synchronization (SSYN) is the response of the slave device to the master, usually a response to master

synchronization (MSYN). The master places address information, mode control information, and data (if a DATO or
DATOB is selected) on the Unibus. It then asserts BUS MSYN L but only if BUS SSYN L from the slave is cleared,
which indicates that the slave can participate in a bus transaction. The slave asserts BUS SSYN L when it has data to
send (DATI or DATIP) or when it has received data (DATO or DATOB). The master receives BUS SSYN L in both
cases and clears BUS MSYN L. When the slave receives the cleared BUS MSYN L, it clears BUS SSYN L which frees
the bus. This brief statement of the SSYN/MSYN interaction is necessary to understand the operation of the
memory SSYN circuit. Details of the SSYN/MSYN interaction during all bus transactions can be found in the
PDP-11 Peripherals Handbook. The SSYN circuit is shown in drawing G110-0-1, sheet 2; however, for clarity,

only the SSYN circuit is shown in Figure 12-23 along with the appropriate timing diagram.
During a DATI or DATIP transaction, signal BUS SSYN L is asserted by the memory when the data is placed on the
Unibus by the MDR. During a DATO or DATOB transaction, BUS SSYN L is asserted by the memory when it
receives data from the Unibus.

At the start of each transaction, the master first places the memory address (device and word) and mode control
information on the Unibus. (Data is included if the transaction is DATO or DATOB.) For a DATI or DATIP
transaction, BUS CO1 L is high at pin 10 of bus receiver E29. The output (pin 14) of E29 is low and is sent to the
D-input (pin 6) of CO1 latch E30 and to pin 5 of the E5 WRITE gate. Signal BUS MSYN L has not yet been asserted;
thus, the output (pin 13) of bus receiver E23 is low. This signal is sent to pin 2 of NOR gate E26: the other input
(pin 3) of this gate is always low because MSYN A L is normally not connected. The output (pin 1) of E26 is
inverted by E15 to produce SSYN RESET L; this signal sets SSYN flip-flop E4 via its preset input (pin 4). The low
O-output (pin 6) is sent to both inputs of bus driver ES. The output of this gate is the slave synchronization signal
(BUS SSYN L) and, at this point, it is not asserted.

12-33

As long as BUS MSYN L is not asserted, the SSYN flip-flop is preset. The master now asserts BUS MSYN L, which in

turn disables the preset signal to the SSYN flip-flop (SSYN RESET L is high). Clock signal CLK 1 H is generated and
clocks CO1 latch E30. Latch E30 is reset and its high O-output (pin 11) is sent to pin 10 of the E5 READ gate in the
wired-AND. The wired-AND output CLK SSYN is high, and it remains high as long as both ES NAND gate outputs
are high; this occurs when at least one input of each gate is low. The output of E5 WRITE remains high because
input pin 5 is held low by the output of CO1 receiver E29. The output of this gate is not changed when the CLK 2 H
pulse appears at pin 4. The output of ES READ remains high until STROBE H goes low again; the wired-AND

output is high again. This positive transition clocks the SSYN flip-flop, which now resets because its D-input is tied

to ground (low). The high O-output (pin 6) of the SSYN flip-flop asserts BUS SSYN L at the output (pin 3) of bus
driver E5. The master receives the asserted BUS SSYN L signal and clears BUS MSYN L. The memory receives the
cleared BUS MSYN L from the master at bus receiver E23 and generates signal SSYN RESET L via gates E26 and
Ei5 to set the SSYN flip-flop. The memory is now ready for the next transaction.
For a DATO or DATOB, the sequence is the same except that BUS CO1 L is low at pin 10 of bus receiver E29. This

conditions the wired-AND so that the output of E5 READ remains high. In this case, the CLK 2 H pulse generates
the CLK SSYN pulse that clocks the SSYN flip-flop via ES WRITE.

12.9.3

Pause/Write Restart Circuit

The PAUSE flip-flop is used to inhibit the restore (write) operation during a DATIP transaction. This transaction is
useful when there is no need to restore data after reading because the location is to have new data written into it. By
eliminating the restore operation, memory cycle time is decreased by approximately 50 percent.

A DATIP must

always be followed by a DATO or DATOB. In this case, the DATO or DATOB is shortened by eliminating the clear

(read) operation that is normally performed prior to the restore (write) operation. The location has been cleared
previously by the DATIP; consequently, the DATO or DATOB need only perform the restore (write) operation. The

pause/write restart circuit is shown in drawing G110-0-1, sheet 2; however, for clarity, only the pause/write restart
circuit is shown in Figure 12-24.

At the start of all bus transactions, the PAUSE flip-flop is reset; it remains reset throughout the bus transactions

except during a DATIP, in which case it is set during the read operation. The PAUSE flip-flop is clocked by the reset

0O-output (pin 6) of the SSYN flip-flop. The state (set or reset) of the PAUSE flip-flop is determined by its D-input
(pin 12): the D-input is high to set and low to reset. The state of the D-input is controlled by Unibus mode control
bits CO1 and C0O. (Only the mode control representing a DATIP provides a high to the D-input of the PAUSE

flip-flop.) During a DATIP, CC1 is high and COO is low at bus receivers E29, pin 10 and E29, pin 7. These signals are
inverted by the bus receivers and applied to the D-input of the CO1 and COO latches: COO latch E30, pin 3 is high,
and CO1 latch E30, pin 6 is low. When the latches are clocked by the CLK 1 H signal, latch CO1 is reset and C00 is
set. This action puts a low on each input of negative input AND gate E26, which generates a high output. This high
output is the D-input to the PAUSE flip-flop. The PAUSE flip-flop is now conditioned to set when it is clocked.
Returning to the start of the DATIP operation, the PAUSE flip-flop is reset. Its D-input is conditioned (D is high)
but the PAUSE flip-flop has not been clocked; thus, its 0-output (pin 8) is high. This high output goes to the D-input

of the Read/Write flip-flop (R/W E3); this flip-flop is clocked early in the sequence by CLK 1 H. The R/W flip-flop is
then set which permits a read operation. The low 0-output (pin 8) of the R/W flip-flop is sent to pin 4 of E17. The

other input (pin 5) of E17 comes from the 0-output (pin 8) of the PAUSE flip-flop, and it is a high at this time. The
output of E17 is a high and is inverted by E15, which puts a low on the clear input of the Write Restart flip-flop

(WRRS E2). The output of E15 also goes to input 2 of E25. The WRRS flip-flop is cleared (reset) and its high
O-output (pin 8) is sent to the other input (pin 1) of E25. The output of E25 is the WRITE RESTART L signal. This
signal is produced to trigger the timing circuit and to initiate a write operation. Signal WRITE RESTART L is now
high, its proper state when a read operation is being performed.
At the end of the read operation, the SSYN flip-flop is clocked which resets it. The positive transition at its 0-output

(pin 6) clocks the PAUSE flip-flop, which sets the SSYN flip-flop and puts a low on pin 5 of E17. The timing circuit

clears (resets) the R/W flip-flop, which in turn puts a high on pin 4 of E17. The output of E17 remains high,
inhibiting the WRITE RESTART L signal and preventing the initiation of a write operation.

12-34

BUS MSYN L

CLK1 H E14 PIN 6

CO1{ LATCH
0-OUTPUT E30 PIN 11

STROBE

E17

PIN 3

CLOCK SSYN ES

BUS MSYN L1—20

PINS 6/8 WIRED-AND

SSYN FF

0-QUTPUT E4 PING

—l

BUS SSYN L E5 PIN 3

—

Buscort

PRE

° sEin ' 6

o
10

+5v

RESET

11-1440

Timing Diagram for SSYN Circuit During DATI and DATIP

SSYN

E29

b
e

14 ]

1'1_0_

£30

LATCH

STROBE H—

CLR

CLK

WIRED - AND

+ 3V

10
531CLOCK
géN 1cr)wu'r
| FF
OF PAUSE

2
1|

BUS

SSYN L

+5v
11-1139

BUS MSYN L

]

CO1 RECEIVER
€29 PIN 14

CLK2 H E15 PIN

CLOCK SSYN ES
PINS 6/8 WIRED-AND

0-0OUTPUT

SSYN FF

E4 PIN 6

BUS SSYN L

E5 PIN 3

I
t1-1141

Timing Diagram for SSYN Circuit During DATO and DATOB

Figure 12-23

Slave Sync (SSYN) Circuit

12-35

WRITE RESTART L

BUS COO L

6} E29

LATCH

6126 Yo

Bus corL

ALWAYS O

10
-4

9'4 Sip

£30

SSYN RESET L

CLK

a] £17

pe—dEs>E

Mek o

READ=SET:0

CLR

WRITE= RESET=1

T13

PRE

SSYN

+3v

INIT L

PRE

1
8
ca.|::3 'Ps
CLKI H —

—14

1°

1—:-

E4a

co1

PRE

PAUSE

LATCH

)’10

o3cik ofiLd

CLK1 H

+3V

2eik o

R/W

CLR

R/W RESET L

+3V

11-1144

Figure 12-24

Pause/Write Restart Circuit

For any transaction other than DATIP (DATI, DATO, or DATOB), the PAUSE flip-flop is not set when it is clocked
because its D-input is low. It remains reset which keeps a high on pin 5 of E17.

When the R/W flip-flop is cleared, it puts a high on pin 4 of E17. The low output of E17 is now inverted by E15 and
sent to pin 2 of E25. The WRRS flip-flop is reset so that pin 1 of E2S is also high. The output (pin 3) of E25 goes
low, which generates WRITE RESTART L. This starts the formation of a low WRITE RESTART L pulse. This
output is inverted by E25, pin 6 which clocks the WRRS flip-flop and sets it, because its D-input is connected to
+3V. Pin 8 of the WRRS flip-flop now goes low, which is in turn fed to pin 1 of E25. Thus, the output of E25
becomes high again, which terminates the low WRITE RESTART L pulse. This pulse triggers the timing circuit and
initiates a write operation.

For a DATO or DATOB following a DATIP, the PAUSE flip-flop is reset by the SSYN flip-flop, because the DATO
or DATOB transaction started with the PAUSE flip-flop set previously by the DATIP.
12.9.4

Strobe Generating Circuit

The strobe generating circuit produces a narrow positive pulse (STROBE H) during the read operation to enable the
STROBE 0 H and STROBE 1 H signals for the sense amplifiers. The strobe generating circuit is shown in drawing
G110-0-1, sheet 2; however, for clarity, only the strobe generating circuit is shown in Figure 12-25 along with an
appropriate timing diagram.

During the read operation, the timing circuit generates a positive RESET H pulse. The RESET H pulse is sent to pin
5 of the strobe delay one-shot (ST DEL E36); this 74121 one-shot provides complementary outputs but only the Q
(negative pulse) output (pin 1) is used. Pins 3 and 4 of the ST DEL one-shot are connected to ground so that it can
be triggered by a positive-going edge at pin 5. Prior to receiving the triggering signal (RESET H), the strobe
generating circuit is in the quiescent state. The STROBE 08 flip-flop E28 is in the reset state. (When the memory is

12-36

powered up, E28 is driven to the reset state by E36 if it did not come up reset randomly.) The low 1-output (pin 9)

of E28 is sent to pin 13 of E17. The ST DEL one-shot is inhibited so that its Q output (pin 1) is high, which is sent

to pin 12 of E17. The output (pin 11) of E17 is high and is inverted by the next E17 gate (pin 3). This is the
STROBE H signal, and it is low at this time.

The timing circuit generates a positive RESET H pulse that is sent to pin 5 of E36. The positive edge of RESET H
triggers E36, and its Q output (pin 1) goes to low. This is the start of a single negative pulse whose duration is
determined by an external RC circuit connected to pins 10 and 11 of E36. The output of E36 directly sets STROBE
E 0S flip-flop E28 via its preset input (pin 10). The 1-output (pin 9) of E28 goes high and is sent to pin 13 of E17.
The other input to this gate (pin 12) is now low. E17, pin 11 is high and is inverted so that E17, pin 3 is stiil low (no
strobe pulse yet). When E36 times out, its output (pin 1) goes high again. Pins 12 and 13 of E17 are now both high,

and the output (pin 11) of E17 is low. This signal is inverted and E17, pin 3 is high. This is the beginning of the
STROBE H pulse. The positive transition of E17, pin 3 also clocks flip-flop E28. E28 is reset because its D-input is
connected to ground (low); pin 9 of E28 is now low. It is fed back to pin 13 of E17, which makes E17, pin 3 low

again. This terminates the positive STROBE H pulse. The circuit is back to its quiescent state where it remains untii
another RESET H puise comes along to trigger ST DEL one-shot E36.

—“‘—110
A

E28
&
nl

“CLR

Tis

+3v

STROBE H

RESET H

€36

ST DEL

NEGATIVE PULSE
WHEN TRIGGERED

TRIGGERS ONLY
ON POSITIVE

TRANSITION

-4z

RESET H

E36 PIN

5
__—TIMES OUT

STROBE _DELAY
ONE -SHOT
€36 PIN 1

STROBE H
E17 PIN 3

STROBE
OS FF
€28 PIN 9

PRESET

CLOCKED TO RESET

STATE

1-1:43%

Figure 12-25

Strobe Generating Circuit and Timing Diagram for STROBE H

12-37

12.9.5

Data In (DATI) Operation

In the discussion of the DATI operation (as well as the DATIP, DATO, and DATOB operations) signals are not
traced through circuit components; rather, various events are integrated to describe a complete memory operating
engineering logic drawings G110-0-1, sheets 2, 3, and 4; G231-0-1, sheets 2, 3, and 4; MM11-L-3 (timing diagram);

and Figure 12-26, which is a flow chart for memory operation.
In a DATI operation, the master requests that a selected memory location be read and the information transferred to
the master via the Unibus. The readout is destructive because the read operation forces all cores in the selected
location to 0. However, during readout, the information is temporarily stored in the MDR and is automaticaily
restored to the selected location by a write operation that immediately follows the read operation.

At the start of the DATI, MSEL flip-flop is reset, DEL flip-flop is reset, R/W flip-flop is reset, PAUSE flip-flop is
reset, and SSYN flip-flop is set. The address lines and mode control lines (CO1 and C00) are decoded. The master
asserts the BUS MSYN L signal and the cycle begins. Signal CLK 1 H is generated, the DEL flip-flop is set, and the

R/W flip-flop is set. Setting the DEL flip-flop initiates the timing chain via delay line DL1. The timing chain

generates TWID H and TNAR H. At the same time, CLK 2 H is generated and it presets the MSEL flip-flop, which
prevents the start of another cycle until it is reset. Signal READ H from the R/W flip-flop and signals TNAR H and
TWID H go to the driver module to select the appropriate read drivers and switches, turn on the X- and Y-current
generators, and control the stack discharge circuit. As a result of these signals, the X- and Y-half currents are directed

to the selected memory location, and all 16 cores (one per bit plane) are set to 0. Just prior to this event, the timing
chain generates RESET O L and RESET 1 L; these signals clear the MDR. The timing chain then generates STROBE
H, which asserts STROBE 0 H and STROBE 1 H; these signals are sent to the sense amplifiers. The strobe pulses are

timed to arrive at the same time as the pulses induced in the sense/inhibit line. If a selected core is a 1, a pulse is
induced in the sense/inhibit line that exceeds the sense amplifier threshold and produces an amplified positive pulse.

This output is inverted and presets its associated MDR flip-flop and a 1 is stored in the flip-flop. Signal STROBE H
also clocks the SSYN flip-flop which resets. The SSYN flip-flop output asserts DATA OUT H and BUS SSYN L.

Signal DATA OUT H gates the output of the MDR to the Unibus. BUS SSYN L is a Unibus signal that informs the

master that the memory has read the selected location and placed the data on the Unibus. The master takes the data
and clears BUS MSYN L,which in turn generates SSYN RESET L to set the SSYN flip-flop. BUS SSYN L is cleared

to indicate that the Unibus is free; however, another bus transaction cannot be initiated even if the master asserts
BUS MSYN L because the lockout feature of the MSEL flip-flop is still set. Prior to the assertion of BUS SSYN L,
the timing chain generates DELAY FF RESET L, which resets the DEL flip-flop and allows the TNAR H and TWID
H pulses to terminate as a function of taps 5 and 7 of the delay line. The timing chain also generates R/W RESET L,

which resets the R/W flip-flop.

The memory now enters the write (or restore) cycle. With the R/W flip-flop and PAUSE flip-flop both reset, the
pause/write restart circuit generates the WRITE RESTART L signal, which initiates another timing cycle by setting
the DEL flip-flop.
The timing chain generates TWID H and TNAR H. These signals, plus a low READ H signal from the R/W flip-flop,
go to the driver module to select the appropriate write drivers and switches; turn on the X- and Y-current generators;
and control the stack discharge circuit. In addition, TWID H and an output from the R/W flip-flop are ANDed to
generate TINH O H and TINH 1 H. These signals control the operation of the inhibit drivers. Signals TINH 0 H and

TINH 1 H are ANDed with the outputs of the MDR flip-flops. If a 1 is stored in the MDR flip-flop, the associated
inhibit driver is not turned on and a 1 is written into this bit of the selected memory location. Ifa 0 is stored in the

MDR flip-flop, the associated inhibit driver is turned on and produces a current that opposes the Y-line current and
prevents a 1 from being written into this bit. The timing chain generates DELAY FF RESET L, which resets the
DEL flip-flop and allows TNAR H, TWID H, and the inhibit pulses (TINH O H and TINH 1 H) to terminate. The
timing chain also generates MSEL RESET L, which resets the MSEL flip-flop.

12-38

‘3

cycle. All the circuits involved have been discussed in detail in the preceding paragraphs of this chapter. Refer to

BUS

MSYN L

DATI OR DATIP

WAIT UNTIL
MEMORY IS NOT

ASSERT BUS

BUSY

SSYN L AT END

OF STROBE
ASSERT DATOUT H

S
MEMORY BUSY

IN
DATIP MODE

CLOCK IN CONTROL
AND ADDRESS
FROM

ég%sRJAQFUELK 2

BUS

[seT PausE FF AT

[ssyn L Time

RESET R/W FF,
RESTART DEL FF

CLOCK IN DATA
FROM

RESET MSEL FF
AT END OF READ

BUS

AND START WRITE

CYCLE

}

[(]

RESET

PAUSE FLIP-FLOP
SET

SET R/W FF,DEL FF
AND START READ
CYCLE

YES

BUS

SSYN L WITH

SET DEL FF_AND

BUS MSYN H

START WRITE
CYCLE

MEMORY READY
FOR DATO
CYCLE (%450ns)

ASSERT BUS

SSYN L AT CLK 2
TIME

RESET

BUS
RESET
SSYN L WITH

MSEL FF

AT END OF

WRITE CYCLE

BUS MSYN H

|
MEMORY READY
FOR NEXT

CYCLE (8900ns)

RESET MSEL FF

RESET BUS

WRITE CYCLE

BUS MSYN H

SSYN L WITH

AT END OF

MEMORY READY
FOR NEXT

CYCLE (x 450ns)
ty

Figure 12-26

Flow Chart For Memory Operation

nars

12.9.6

Data In Pause (DATIP) Operation

In a DATIP operation, the master requests that a selected memory location be read and the information transferred
to the master via the Unibus. However, unlike the DATI, this information is not to be restored after reading; this

location is to have new information written into it. The DATIP performs only a read operation; the write operation
is inhibited. A DATIP must always be followed by a write operation (either DATO or DATOB).

The read operation of a DATIP is identical to that of a DATI (Paragraph 12.9.5) until the time the SSYN flip-flop is
reset (clocked by STROBE H). At this time, the SSYN flip-flop output clocks the PAUSE flip-flop, which sets it

because its D-input is a 1 (only during DATIP due to the state of mode control bits CO1 and C00). The timing chain
generates R/W RESET L which resets the R/W flip-flop. The outputs of the PAUSE flip-flop and R/W flip-flop
prevent the pause/write restart circuit from generating WRITE RESTART L. With this signal inhibited, the write
operation is not produced. The timing chain generates DELAY FF RESET L, which resets the DEL flip-flop and

terminates TNAR H and TWID H. The timing chain also generates MSEL RESET L, which resets the MSEL flip-flop.

The memory is now ready to accept another request from the master. The next operation must be a DATO or
DATOB. Normally, a DATO or DATOB starts with a read operation to set all selected cores to zero (clear) before
writing new information into them. A DATO or DATOB following a DATIP has this initial clear operation
eliminated because the cores have been cleared by the previous DATIP operation.

The DATO or DATOB following a DATIP starts when the master asserts BUS MSYN L. Pulse CLK 1 is generated
but it does not set the R/W flip-flop because the PAUSE flip-flop is set. The master places the information to be
written on the Unibus where it is picked off by bus receivers and sent to the D-input of the MDR flip-flops.
Decoding the mode control bits (CO1 and C00) for a DATO or DATOB generates LOAD 0 H and LOAD 1 H, which
clock the MDR flip-flops. The outputs of the MDR flip-flops are gated with TINH 0 H and TINH 1 H to control the
associated inhibit drivers to write 1s or Os into the selected memory location. As in the write operation ofa DATI,

the timing chain generates TWID H and TNAR H which select the appropriate write drivers and switches; turn on the

X- and Y-current generators; and control the stack discharge circuit. They also generate inhibit driver control signals
TINH O H and TINH 1 H. Signal CLK 2 H clocks the SSYN flip-flop (resets it), which asserts BUS SSYN L to tell the
master that the data has been taken from the Unibus. When the master clears BUS MSYN L, the SSYN flip-flop is
reset, which in turn resets the PAUSE flip-flop. At the end of the write operation, the timing chain generates
DELAY FF RESET L and MSEL RESET L to restore the control signals to their original states.

12.9.7

Data Out (DATO) Operation

In a DATO operation, the master sends a 16-bit word to be written into the selected memory location. The
transaction starts with a read (clear) operation to set the selected cores to 0 before writing new data into them. The
standard DATO consists of a read operation followed by a write operation. (As described in Paragraph 12.9.6, a
DATO following a DATIP does not perform the read operation.)
The read operation of a DATO is similar to a read operation of a DATI except that no RESET 0 L, RESET 1 L,

STROBE 0 H, and STROBE 1 H pulses are generated. The MDR is not cleared and the sense amplifiers are not
strobed. This read operation is required only to clear the memory location by setting all the selected cores to O it is
not necessary to readout and store the information in the MDR. The information on the Unibus data lines is
sent to

H, which clock the MDR flip-flops. The MDR outputs (16 bits) are gated with TINH 0 H and TINH 1 H to control
the associated inhibit drivers. The timing chain generates the other control signals that provide the selection of the

appropriate write drivers and switches and a write operation is initiated. This write operation
is the same as that

described in Paragraph 12.9.6 for a DATO following a DATIP.
12.9.8

Data Out Byte (DATOB) Operation

In a DATOB operation, the master sends a byte (8 bits) to be written into the selected memory location. A high
byte [bits D (15:08)] or a low byte [bits D (07:00)] can be selected. Byte selection is made by the state of address
bit A00. A DATOB is the same as a DATO except that the sclected and non-selected bits are handled differently.

1240

the inputs of the MDR flip-flops. Decoding the mode control bits (CO1 and C00) generates LOAD 0 H and LOAD 1

Assume that the low byte [bits D (07:00)] is selected (A0O = 0). Neither RESET O L or STROBE 0 H are generated
for the selected byte because new data is to be written into bits D (07:00) (low byte). The LOAD 0 H signal is
generated so that the data on Unibus bits D (07:00) can be written into the selected byte location.

The nonselected byte [bits D (15:08)] is to be restored so that RESET 1 L and STROBE 1 H are generated. These
signals strobe the byte into the MDR for restoration during the write operation. Restoration is necessary because this
byte does not receive new data. The LOAD 1 H signal is not generated; therefore, any data on Unibus bits D (15:08)
has no effect on the non-selected byte.

When the DATOB is complete, the selected byte contains new data and the non-selected byte remains unchanged. A
DATOB operation following a DATIP is the same, except that the read portion is eliminated.

1241

CHAPTER

MEMORY MAINTENANCE

13.1

INTRODUCTION

This chapter provides the preventive and corrective maintenance procedures for the MM11-K and L memories. The
user should have a thorough understanding of the normal operation of the memory (Chapter 12). This knowledge
plus the maintenance information will aid the user in isolating and correcting maifunctions.
13.2

PREVENTIVE MAINTENANCE

Preventive maintenance consists of specific tasks performed at intervals to detect conditions that could lead to
subsequent performance deterioration or malfunction. The following tasks are considered preventive maintenance
items.

a.
b.
c.

Visual inspection of modules for broken wired, connectors, or other obvious defects.
45V and -15V checks: both must be within +3%.
X-and Y-current generator check (Paragraph 13.2.2).

Two pieces of test equipment are recommended for checking and troubleshooting the memory: Tektronix 453 Dual
Trace Oscilloscope or equivalent, and Honeywell 33R Digital Voltmeter or equivalent with 0.5 percent accuracy.
Initial Procedures

13.2.1

Before attempting to check, adjust, or troubleshoot the memory, perform the following steps.
NOTE

All tests and adjustments must be performed in an ambient

temperature range of 20°C to 30°C (68°F to 86°F).

Verify that all modules are properly and securely installed.
CAUTION

Ensure that all power is off before installing or removing
modules.
2.

Visually check modules and backplane for broken wires, connectors, or other obvious defects.

Verify that power buses are not shorted together.

Turn on primary power and check that both the -15V and +5V power are present and within tolerances
(£3%).

13-1

Start the system. The memory should operate without errors. If not, check the output of the current

generator (Paragraph 13.2.2). If the memory still does not operate properly, a malfunction has occurred.
Proceed with corrective maintenance (Paragraph 13.3).

13.2.2

Checking Output of Current Generators

The amplitude of the current pulse from each current generator (X and Y) is factory set at 4105 mA. It is not

adjustable in the field.
The X- and Y-current generators are located on the G231 Driver Module. Each output has a current loop on its
output line for attaching a test probe. Loop J5 is for the Y-generator and loop J6 is for the X-generator (drawing

G2310-1, sheet 2). The amplitude of each READ current pulse should be 41045 mA. At the time of measurement,
=15V and +5V power must be within the specified tolerance of +3 percent.

13.3

CORRECTIVE MAINTENANCE

This paragraph describes the method of interchanging the positions of the memory modules to gain access to test
points. It also describes the strobe delay adjustment, which is a specific corrective maintenance procedure. Further,

three aids are included for performing corrective maintenance: a troubleshooting chart and waveforms for the drive

and sense/inhibit circuits.
13.3.1

Strobe Delay Check and Adjustment
CAUTION

Strobe delay is factory adjusted and should be adjusted only
when one of the three modules is replaced. It is a critical
adjustment and must be done carefully.

The strobe must be set while cycling worst-case noise test patterns (MAINDEC-11-DIGA). The proper setting is

midway between the two end points where the memory starts to error as strobe time is moved from earliest to latest.
As the strobe time is varied, allow adequate time to cycle completely through the worst-case noise test at each strobe
position. Figure 13-1 shows the strobe pulse waveform and the READ pulse waveform and the points at which they

are picked off for display. Strobe-adjusting potentiometer R120 is on the G110 module next to the large delay line

(DL1) and is accessible without putting the module on the extender.

READ

G110 OR G231
PIN

CU2

I
|[e——— T

STROBE ——+

STROBE H
G110 TEST POINT 1

INPUT

TO E5 PIN

Figure 13-1

13.3.2

Strobe Pulse Waveform

Corrective Maintenance Aids

Figure 13-2 is a troubleshooting chart arranged as a two-axis grid that identifies faults versus cause location. Figure

13-3 illustrates the sense/inhibit waveforms, and Figure 134 illustrates the drive waveforms. Both figures include
schematics to indicate the points in the circuit where the waveforms occur. In addition to nominal waveforms,
dotted lines are used to indicate waveforms that appear if specific components are faulty.

Loc.

)

Possible

Circuit

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Memory Does Not

Respond to MSYNL

Memory Hangs Bus

DATO Fails
]

DATIP Fails

Picks Bits

Drops Bits

Byte Failures

FA2
X

2 Bits Fail

1 Bit Fails

Hi{

| Lo | Lo

4 Bits Fail

Fails All Addresses

CO1
oo

Many Bits Fail

Coo

Al-A3 Common

Ad4—-A6 Common

A7- A9 Common

Al0—-A13 Common

| X

READ Waveforms
Wrong
WRITE Waveforms

Wrong

No Inhibit

Location

C =G110 Sense Control

]
X

| x

[ X

| x|

X = Indicates Circuit Not Operable

S = Stack

Lo = Measured Parameter Too Low or Early

D= G231 Driver

Hi = Measured Parameter Too High or Late

Figure 13-2

Troubleshooting Chart

]

READ
A

WRITE
_A

]

|I
LM
__

BN
©

0
1

o}
-15v

|G214 MODULE

MODULE

MEMORY

+5V

4096 CORES

[

| 6110 MODULE
| sa
'

[

SENSE /INH

FROM MDR

FLIP-FLOP

TINH H (&) —

WINDING

7437

CORE MAT

® __

AMP

-12v f

—
-

4096 CORES

SENSE

-1.5v

Lind

+50mvV

dvaso

DATA
(N

[PRE

BAS E DRIVER

0
TO 7437

INHIBIT

{

MDR FLIP-FLOP

A
—
—c . ot
Loap

74HON

——————————

BASE DRIVER
7474

INH 181T

| s8

-2v

I o

OPEN INH. OR SENSE

p—o0

TERMINATION

G110

-50mv

@ ___| ORIVER
DATOUT

-15v

INHIBIT DRIVER

® ____K\
1

RESET L
v

UNIBUS
11-1151

STROBE

I DATA ON BUS FROM OTHER UNITS WilLL ALSO APPEAR HERE

11-1152

Figure 13-3

MMI11-K Sense/Inhibit Waveforms

13-4

+5V

TWID

216.9Q

READ

WRITE

47V

450mA

EF}E_F_—}

GND

OPEN LINE

OR RPDR |

—————— .

-15v

CURRENT GENERATOR

o @)

Y SHORTED LINE
—15v

-20v

/©

+5v

GND

“1BV 1~

- = — —

OPEN LINE

-5y

-25v

e o

INOP WPS

o
+5V

+5v

INOP RNS

URRENT LOOP

_ _ OPEN LINE

INOP

TO DECODER

< E}—-TO DECODER

RPDR
INOP WNDR

-15v

~15V

OPEN LINE
MEMORY

CORES

U+5v©

----Dotted line show possibie
failure woveforms.

+1.5V

i-1154

¥TDR H—]

8251

DECODER

11 VB

+5V

NEG

READ

DISCHARGE
STACK

CIRCUIT

DECODER

SWITCH

DRIVER

15y

ONLY
READ L — (ONE

AX —1 OUTPUT
AX — SHOWN)

5.10

5.1Q

‘l’Indwuies module conn pin.
*TDR M ond NAND
gate are used on
driver

decoders

only.

(VB—— Vp) fotiows waveform

—15v

below

shown

+1V

(VB-VA)
-1V
11-1153

Figure 134 Drive Waveforms

13-5

13.4

PROGRAMMING TESTS

Certain DEC programs may be used to test various memory operations as an aid to troubleshooting. The purpose of

each of these memory-related test programs, as well as the program abstract, is given in the following paragraphs.
Each program contains instructions for use.
13.4.1

Address Test Up (MAINDEC-11-DIAA)

The purpose of the Address Test Up program is to demonstrate that the selected memory area is capable of basic
read and write operations when address propagation is upward through memory. This test program writes the

address of each memory location (within the test limits) into itself and then increments through memory until the
address corresponding to the high limit is reached. After this location has been written, the memory enters the read
cycle. The read cycle starts with the high limit location and reads and compares each word location, decrementing
down to the low limit location. The program halts on an error.

The program ensures that all addresses are selectable and can also be used to isolate bad switches, wiring errors, or

address selection errors. It will also find double selection errors when two bus addresses sclect the same core address.
13.4.2

Address Test Down (MAINDEC-11-DIBA)

The purpose of the Address Test Down program is to demonstrate that the selected memory area is capable of basic
read and write operations when address propagation is downward through memory. It is a companion test to the
Address Test Up program (Paragraph 13.4.1).
This test program writes the address of each location into itself, downward through memory. After writing down,
the program reads and checks back up through the memory test area. The program halts on an error.

The Address Test Down program resides in the high portion of core memory. It does not check memory below
address 100, as these locations are reserved for trap and vector locations. The program verifies that all modules can
perform their basic functions, checks that all addresses are selectable, and can also be used to isolate faulty switches,
wiring errors, or address selection errors.

13.4.3

No Dual Address Test (MAINDEC-11-DICA)

The purpose of the No Dual Address Test program is to check the unique selection of each memory address tested.
This test is divided into two parts. The first portion of the test fills the test field with 1s and writes Os into the first
test location. This is followed by a read check from this location. The program then checks each field location to

ensure there are no variations from the Is configuration. Upon completion of this test, the test location pointer is
incremented. The next location is then write/read exercised with Os, and the test field rechecked for any change in

content. When the selected test field has been tested in this mode, the program sets a flag and the second portion of
the test is begun. The program fills the test ficld with Os and the field is then tested with a write/read exercised with
Is.

This program checks for faulty switches or wiring errors, checks the complete address selection scheme, and checks
all 16 bits in the data field for 1s and Os operation.

13.4.4

Basic Memory Patterns Test (MAINDEC-11-DIDA)

The Basic Memory Patterns Test program has two main purposes:

Verify that the selected memory test field is capable of writing and reading fixed data patterns.

Verify that the memory plane is properly strung.

13-6

This test program writes a specific pattern throughout a given memory zone, then reads the pattern back and
compares it with the original for correctness. If the pattern read fails to compare correctly with the original, the
program initiates a call to the error subroutine. After completely checking the pattern, the program continues on to
the next pattern test.

13.4.5

Worst-Case Noise Test (MAINDEC-11-DIGA)

The purpose of the Worst-Case Noise Test program is to generate the maximum possible amount of plane noise
during execution of memory reference instructions to check system operation under worst-case conditions.
This test program is designed to produce the greatest amount of plane noise possible during memory read and write
cycles. The noise parameters are affected by a number of factors. The noise generated is distributed across the core
plane algebraically and adds to the normal dynamic noise present on the sense lines. This can cause misreading of
data (within the plane) that is in the low (1) or high (0) category. The sense windings of most memories are such
that worst-case patterns can be caused by alternately writing -1 and 0 data configurations throughout memory. Under
these conditions, worst-case noise is generated by performing a read, write, complement operation at each location.
The test is repeated after complementing all of the pattern data stored in the memory test zone; thus, all cores are
tested for worst-case as both 1s and Os. The pattern or its complement is written into the memory test zone as
determined by the exclusive-OR between address bits 3 and 9.

The Worst-Case Noise Test program is divided into two parts. Part 1 is run first and, during this part of the program,
a -1 configuration is written into all locations having an address with an exclusive-OR state between bits 3 and 9. All
other locations are loaded with the O configuration. After the test zone has been loaded, the memory is rescanned.

This time, each location is read, complemented, read, and complemented (RCRC). Any location detected as being
disturbed by a previous RCRC operation is flagged as an error. Upon conclusion of the read scan loop, the program
automatically switches to Part 2.
pn——

During Part 2 of the program, the data patterns stored in memory are complemented. In other words, O patterns are
stored in locations having addresses with an exclusive-OR between bits 3 and 9. All other locations are loaded with
the -1 configuration.

The exclusive-OR pattern distribution for Parts 1 and 2 is summarized for reference as follows:
Part 1

Exclusive-OR (3 and 9) = 1 pattern

No Exclusive-OR (3 and 9) = 0 pattern
Part 2

Exclusive-OR (3 and 9) = 0 pattern
No Exclusive-OR (3 and 9) =~1 pattern

After memory is loaded, it is scanned again with a read, complement, read, complement (RCRC) loop as previously
described. Any location detected as being disturbed by a previous RCRC operation is flagged as an error.

Before writing or reading any location (in either part of the program), the program issues a call to subroutine
XORCK (exclusive-OR check) that tests bits 3 and 9 and sets the XORFLG if the exclusive-OR condition is present.
Subroutine ERRORA is called for any location disturbed from the -1 configuration; subroutine ERRORB is called
for any location disturbed from the O configuration.

The program prints out errors and repeats when complete without interruption. Upon completion, the program rings
the teletype bell and then halts if switch 12 is present. A continue from the halt initiates another pass.
A,

If the program indicates an error, use the troubleshooting chart as a guide to locate the fault.

13-7

PART 4

POWER

SUPPLY

Part 4 provides specifications and a general physical description of the power supply.

A detailed circuit description and maintenance information are also included. The
chapters of Part 4 are:

Chapter 14 — Power Supply General Description

Chapter 15 — Power Supply Detailed Description
Chapter 16 — Power Supply Maintenance

CHAPTER 14

POWER SUPPLY GENERAL DESCRIPTION

14.1

INTRODUCTION

The power supply is a forced air-cooled unit that converts single-phase 115V or 230V nominal, 47-63 Hz line voltage
to the three regulated output voltages required by the computer. The output voltages and their principal uses and
characteristics are:

Voltage

Use

Characteristics

+15V

Communication Circuits

Series regulated and overcurrent protected.

+5V

IC Logic

Switching regulated and overvoltage and overcurrent protected.

-15vV

Core Memory

Switching regulated and overvoltage and overcurrent protected.

The power supply is used in conjunction with the BCOSHXX (115V) or BCOSJXX (230V) Power Control
Assemblies, which contain a line cord, circuit breaker, and RF1 capacitors. Line cord length is specified in the part

number; e.g., 115V, 6 feet is designated BCOSHO6.
The power circuitry also generates BUS AC LO L and DC LO L power fail early warning signals, and the LTC L

real-time clock synchronizing signal.
A thermal control mounted on the heat sink will interrupt the ac input should the heat sink temperature become
excessive due to fan failure or other cause.

14.2

PHYSICAL DESCRIPTION

The power supply comprises three major subassemblies and two cables:

the power control unit, power chassis

assembly, dc regulator module, dc cable, and ac cable.

14.2.1

Power Control Unit

The power control unit (drawing H400-0-0) is mounted to the rear of the computer by two screws. It contains line
cord, circuit breaker, RFI capacitors, 115V or 230V connections for the power supply transformer, and an output
6-socket Mate-N-Lok connector. Physically, it consists of a sheet metal bracket and a slide-on cover that is locked in
place by one screw. A single pole thermal breaker and a line cord strain-relief grommet are mounted on the flange of
the bracket, making the line cord and breaker reset button accessible on the rear of the computer.

14-1

A small printed circuit card is mounted directly to the breaker terminals. This card interconnects and mounts the

RFI dual-disc ceramic capacitor, the output Mate-N-Lok connector and three fast-tabs for ac input and ground
connections. A dual fast-tab is connected directly to the bracket. The black and white line cord wires are connected
via fast-tab to the PC card; the green (ground) line cord wire is connected to the dual fast-tab, which in turn is

connected to the third fast-tab on the PC card.
The 115V and 230V models differ in only two respects: breaker current rating and (printed circuit) jumpers for

parallel or series connection of the power supply transformer primaries. Power control part numbers are: BCOSHXX
- 115V, 7A; and BCOSJXX - 230V, 4A; where XX denotes line cord length; e.g., BCOSHO6 has a 6 foot line cord.
14.2.2

Power Chassis Assembly

The 700 8731

Power Chassis Assembly (Figures

14-1

and

14-2) consists of a long, inverted U-shaped chassis,

700-8726 power transformer, and a S-inch fan. It is secured to the bottom of the computer by four 8-32 by 3/8 inch
Phillips pan-head bolts.

u“““l

Figure 14-1

Power Chassis Assembly (with DC Regulator Module)

6211-2

62111

Figure 14-2

Power Supply Assembly (with DC Regulator Module Removed)

The chassis is mounted to the right of the connector blocks, when viewed from the front, and airflow is from front
to rear. The fan is held to one end of the chassis by two screws; the transformer is held to the other end by four

mounting studs. The transformer may be removed by loosening four nuts, which are accessible through large holes
on the bottom of the power chassis.

The dc regulator module is mounted to the chassis assembly by six screws and must be removed for cable access. The
dc cable enters a slot on the connector block side of the chassis; the ac cable enters a slot on the other side.
Connections to the fan are made by small fast-tabs; connections to the transformer are made via Mate-N-Lok
connectors: 6-pin for primary, 3-socket for secondary.

14.2.3

DC Regulator Module

The 5409728 DC Regulator Module (Figures 14-3 and 144) is a printed circuit assembly, mounted to the power

chassis assembly by four 6-32 by 9/16 inch and two 6-32 by 1/4 inch Phillips pan-head screws.

14-3

POWER SUPPLY FAN

DC REGULATOR MODULE

THERMOSTAT
MATE-N-LOK CONNECTOR

T TABS

CHASSIS

3PIN
MATE-N-LOK

CONNECTORS
POWER CONTROL
MATE-N-LOK

CONNECTOR

Figure 14-3

DC Regulator Module (Top View)

6270-3

DC REGULATOR MODULE

DC CABLE

CHASSIS

( \\.X

FAST TABS
6270-9

Figure 14-4

DC Regulator Module (Bottom View In Mounting Box)
144

)

TRANSFORMER

Computers that were shipped during the first three or four months of production use a dc regulator module
designated 5409728-YA-0; later shipments use a module designated 5409728-0-0, E revision. There are differences in
component values on the two modules. The discussion of the dc regulator module circuits in this manual is directed
to the later module, designated 5409728-0-0. Engineering drawings applicable to the module used are shipped with
the equipment. These drawings provide schematics and component values of the dc regulator module.

This module contains all the circuitry between the transformer secondary winding and the power supply output
cable. The transformer secondary 3-socket Mate-N-Lok connector is plugged into a mating connector that is soldered
directly to the printed circuit board and is accessible underneath it. The 9-pin Mate-N-Lok connector on the dc
output cable to the computer is similarly mated to a connector undemeath the other end of the board.
The dc regulator module may be probed for troubleshooting purposes from the top; all points on the circuit are
available. It may also be removed from the top for cable access and for parts replacement by removing the six
mounting SCrews.

The printed circuit is approximately 5 by 10 inches, with about half of the top surface devoted to the heat sink. The
power transistors and power rectifiers are bolted to two shelves on the sides of the heat sink and make contact with
the circuit board directly underneath via solder and screw connections. The heat sink is hard anodized for electrical
insulation.

The other half of the top surface is devoted to interconnecting and mounting the balance of the circuit. Three small
output voltage adjustment potentiometers are accessible on this top portion of the board.

Two small pico fuses are mounted on the top of the PC board on the fan end. These fast-acting fuses will typically
only blow when some component is defective or when the +5V or -15V is too high. The two input filter capacitors
are held to the underside of the board by a bracket and are connected to the circuit via jumper tabs on the fan end.
The +5V and - 15V output filter capacitors and inductors are also mounted under the board, the former by screws
and the latter by nuts.

Care must be taken to ensure that all electrical and mechanical connections are secure. In manufacturing, the
hardware is tightened with a torquing device set to 12 inch-pounds.
14.2.4

DC Cable

This is a simple cable connecting the computer module to the dc power module via a 9-pin Mate-N-Lok. The latter is
made accessible by loosening the six mounting screws and lifting out the dc module. Cable access is through a slot on
the computer module side of the power chassis.
14.2.5

AC Cable

This cable interconnects all ac portions of the computer chassis (Figures 14-1 through 14-4). The ac portions of the

computer chassis are as follows:

Power Supply Fan — two fast-tabs

Power Supply Thermostat — one 2-pin Mate-N-Lok
Memory Section Fan — two fast-tabs

Transformer Primary — one 6-socket Mate-N-Lok
Power Control — one 6-pin Mate-N-Lok

PDP-11 System AC Power Control — two 3-pin Mate-N-Lok connectors on rear of computer.

The ac cable is located on the right-hand side and rear of the computer and is inherently shielded by the power
supply chassis and the computer chassis.

14-5

SPECIFICATIONS

Tables 14-1, 14-2, and 14-3 list all the power supply specifications according
to input, output,
environmental specifications.

and mechanical and

Table 14-1

Power Supply Input Specifications

Parameters

Specifications

*Input Voltage (1 phase, 2 wires and ground)

95-135/190-270V

Input Frequency

47—-63 Hz

Input Current

5/2.5A RMS

Input Power

325W at full load

Inrush

80/40A peak, 1 cycle

Rise Time of Output Voltages

30 ms max. at full load, low line

Input Overvoltage Transient

180/360V, 1 sec

360/720V, 1 ms
Storage After Line Failure

25 ms min., starting at low line, full load

Input Breaker (part of BCO5 Power Control)

TA/4A single-pole, manually reset, thermal

Thermostat Mounted on Heat Sink (opens

277V 7.2A contacts

transformer and fan power)

Opens 98—105°C

Automatically resets 56—69°C
Input Connections

Line cord on BCOS5 Power Control, length

and plug type specified with BCO5

(Paragraph 2.2.1.1)

Turn-On/Turn-Off

Application or removal of power

Hipot (input to chassis and output)

2.1 kV/dc, 60 sec

*Input voltage selection, 115V or 230V, is made by specifying the appropriate

All specifications are with respect to the BCOS input,

14-6

AC Input Box, DEC Model BCOS5.

'
“

14.3

Table 14-2

Power Supply Output Specifications
Specification

Parameter

+15V
Load Range
Static
Dynamic

Max. Bypass Capacitance in load for 30 ms turn-on

500 mF

Overvoltage protection

None

Current limit at 25°C

1.3Ato 1.7A (-6.2 mA/°C)

Backup Fuse

15A (also used for +5V)

Adjustment

+5% min.

Regulation (All causes including line, load,

+5%

ripple, noise, drift, ambient temperature)

+5V

Load Range

Static

0-15A

Dynamic #2

No load ~ full load

Dynamic #1

Max. Bypass Capacitance in load for 30-ms

+5A (within 0—17A load range)
2000 uF

turn-on

Overvoltage Crowbar (blows fuse)

5.7—6.8V actuate (7V abs. max. output)

Current Limit at 25°C

24-29.4A (-0.1A/°C)

Backup Fuse (series with raw dc)

15A

Adjustment Range

+5% min.

Regulation
Line

Dynamic Load #1
Dynamic Load #2

+10%

Ripple and Noise
1000 Hour Drift

Temperature (0—60°)
—-—_

+0.5%

Static Load

+2%

4% peak-to-peak
+0.25%
1%

Table 14-2 (Cont)
Power Supply Output Specifications
Parameter

Specification
-15v

Load Range
Static

0-7A

Dynamic #1

Al'=5A (0.5A/ps)

Dynamic #2

No load — full load (0.5A/us)

Max. Bypass Capacitance in load for 30-ms

1000 uF

turn-on

Overvoltage Crowbar (blows fuse)

17.4-20.5V (22V abs. max. output)

Current Limit at 25°C

10-13.3A (-0.03A/°C)

Backup Fuse (series with raw dc)

Adjustment Range

*5% min.

Regulation
Line and Static Load

Dynamic Load #1

+2.5%

Dynamic Load #2

Ripple and Noise

3% peak-to-peak

1000 Hour Drift

+0.25%

Temperature (0—60°C)

BUSDCLOL and BUSACLOL
Static Performance at Full Load
(for 230V connection, double below voltages)
BUS DC LO L goes to high

74—80 Vac line voltage

BUS AC LO L goes to high

8—11V higher

BUS AC LO L drops to low

80—86 Vac line voltage

BUS DC LO L drops to low

710V lower

Hysteresis (contained in above specifications)

3—4 Vac

Output voltages still good

70 Vac line voltage

14-8

Table 14-2 (Cont)

Power Supply Output Specifications

Specification

Parameter
BUS DC LO L and BUS AC LO L (Cont)
Dynamic Performance

POWER ON

line
line,
high
s high
is
-up
Worst ca case on power-up
full load.
§

)

SLOWEST OUTPUT
COMES UP

[

30ms

]

BUS DC LOL

k= max :
]
I

2ms_!

BUS AC LO L

FM'N":
|

3
]
ms

NOMINAL

Worst case on power-down is low line,

11094

———

full load.

POWER DOWN
)

25ms

;

MIN

_,:

)

]

FASTEST OUTPUT
GOES DOWN

i g

BUS AC LO L

]

le— 1ms MIN-—-——”:

:"Mm

BUS DC LO L

N-1099

Output Characteristics

50 mA sinking capability

Open Collector

+0.4V max. offset

5V nominal, 180£2 impedance

Pull-Up Voltage on Unibus

1 pus max.

Rise and Fall Times

Outputs shall remain in O state

subsequent to power failure until power
is restored despite Unibus pulling
voltages remaining.

14-9

Table 14-3
Mechanical and Environmental Specifications

Parameter

Specification

Weight

DC Regulator

7 1b approx.

Power Chassis Assembly including AC

18 1b approx.

Regulator Module

Dimensions

16.50 in. length
5.19 in. width

3.25 in. height

Cooling Means

Integral 5 in. fan

Minimum Cooling Requirements

375 CFM through heat sink
250 CFM over caps, chokes, and transformer

Rated Heat Sink Temperature

95°C max.

Shock, Non-Operating

40G (duration 30 ms) 1/2 sine in each of
six orientations

Vibration, Non-Operating

1.89G RMS average, 8G peak; varying from

10 to 50 Hz, 8 dB/octave roll-off 50—200 Hz;
each of six directions

Ambient Temperature

0 to +60°C operating
-40 to +71°C storage

Relative Humidity

95% max. (without condensation)

Altitude

10K ft

Output parameters are specified at the pins of the 9-pin Mate-N-Lok connector (Figure 14-5) which plugs
into the

output connector on the 5409728 module. All output voltages are given with respect to the
common ground pin on

this connector. IR drops in the distribution wiring are minimized to achieve good regulation at the load.
Pin1 BUSACLOL

Pin 9 -15V output

NOTES:

_L@ ® ©

Pin 8 Not used

Pin6 BUSDCLOL
Pin 7 Not used

J@ ® O

Pin 4 LTCL (Clock Signal)

Pin 5 +15V output

Pin 2 Common
Pin 3 +5V output

The circuit connected to pins 7 and 8 is not used in the PDP-11.

Pin 2 is not connected to chassis within the power supply. Chassis ground is made at the
backplane.
Figure 14-5

Output Connector, 5409728 Regulator Module

14-10

CHAPTER 15

POWER SUPPLY DETAILED DESCRIPTION

15.1

INTRODUCTION

The power supply is divided into two sections: the ac input circuit and the dc regulator module. A detailed
description to the circuit level is provided for each section. The ac input circuit description discusses the power
supply interconnections, power control, power switch, transformer, power control circuit breaker, and the power
supply thermostat. The dc regulator module operation description discusses the generation at the circuit level of
each of the five power supply outputs.
15.2

ACINPUT CIRCUIT

A detailed ac interconnection diagram is shown in Figure 15-1. Figures 15-2 and 15-3 give this information in
schematic form.

The line cord, single pole breaker, RFI capacitors, and connections for transformer 115V or 230V wiring are
contained in the power control unit. To select 115V input or 230V input, use the BCO5H or BCO5J power control
unit, respectively.

A 3section managed keyswitch is employed and mounted on the console. One section interrupts the power to the
transformer primary. A second section is wired to two 3-pin Mate-N-Loks; if the PDP-11 cabinet power control bus
is plugged into one of these connectors, the keyswitch will turn on the whole cabinet as well as the computer. The
other three-pin Mate-N-Lok is provided for daisy-chaining in the cabinet power control system. The third section of
the keyswitch is for Panel Lock and is described in Chapter 4.

The transformer is rated for 47-63 Hz and is equipped with two windings that are connected by the power control in
parallel for 115V operation and in series for 230V. The fans are connected across half of the primary so that they
are always provided with 115V nominal. There is an electrostatic shield between primary and secondary of the
transformer.

The power control circuit breaker contains a single-pole thermal circuit breaker that protects against input overload

and is reset by pressing a button on the rear of the computer.

The thermostat is mounted on the power supply heat sink. If the heat sink temperature rises to about 100°C, the
thermostat will open one side of the primary circuit and de-energize the power supply. It will automatically reset at

about 64°C.
15.3

DC REGULATOR MODULE OPERATION

The discussion of the DC Regulator Module circuits in this manual is directed to the module designated
5409728-0-0, rather than the earlier module designated 5409728-YA-0. A block diagram of this module is shown in
Figure 15-4. The center tapped output of the power transformer is applied to positive and negative rectifier and
filter circuits. The rectifier circuits produce +28V and - 28V nominal raw dc voltages which are unregulated but well
filtered by the input storage capacitors.

15-1

C\;
210

BACK | 3]

PANEL TO |

CABINET{

o9
M

POWER |
CONTROL
|, | o

U
COMPUTER

+ ON /OFF
SWITCH

415_'

FAN

J10

IEI

Jit

{

Jur2

¢Sl

PWR

[

SUPPLY

FAN

P3
2

‘
—

1
THERMAL

INPUT

{

—

—J

°
v

p 1

]

P—

12-10601

H400A

i
1

ACLOL

GROUND

+5v

REGULATOR 4 | o
MODULE

5409728

¢|o

°f3

LTC
L
+{5V

e Lo L

78o

}noT used

-5V

S
—

Jzl

H4008

r=-n

—

o| 2

[— o

-y

—

o| 1

CuTOUT

o| 4

No S
B =oleER
| g |
INPUT

BCOSHXX (115V)

)

(\r

r-—-A

o4+

]

[] 1

o|2

ofa

| jI Bl
R
B oo | 6
cS—— I
INPUT

BCOSJXX (230V)
11-1045

Figure 15-1

Detailed AC Interconnection Diagram

\7
J7

KEYSWITCH
REMOTE TURN-ON

[

|
]

]

|
I

PANEL |_oc»<‘);’°
KEYSWITCH

]

¢~

KEYSWITCH |

AC ON-OFF
|

BREAKER

MOUNTED ON
HEAT SINK

POWER

SUPPLY

RFL
AP

FAN

CAP

DCREQULATOR O
MODULE

15v

LINE

{e—1—0°

PLUG

RFI

o—t—

——

CAP.

COMPUTER

FAN

11-1136

Figure 15-2

‘e

115V Connections — Simplified Schematic Diagram

KEYSWITCH
AC ON-OFF

BREAKER

RFJ

CAP.

230V

|
|

{

LINE
PLUG

|§——o REGULATOR
|
MODULE

<
11-1137

Figure 15-3

230V Connection Diagram

15-3

SERIES

REGULATOR
VOLTAGE

OVER

DETECTION
_leosimive

FILTER

RrecTIFiER

AND

FUSE[

+15V OUTPUT

CURRENT

DETECTION

+) RAW

T]DC

OVER CURRENT

DETECTION

VOLTAGE

DETECTION

SWITCHING

+15V

OUTPUT

OVER VOLTAGE
CROW BAR

v-Sl

CENTER TAPPED
AC FROM

TRANSFORMER

SECONDARY

SCALING

POSITIVE
LIMITING

RESISTORS [

AUXILLIARY

TIMING

RESISTORS

ACLO

—| DETECTION

OPEN

[

COLLECTOR

CURRENT sink

RECTIFIER

REFERENCE

DIODE

DCLO

DETECTION [

TM|

OPEN COLLECTOR | o ac

CURRENT SINK

RESISTOR-ZENER

RECTIFIER, FILTER
AND FUSE

(=) RAW DCf

[ TM

CLIPPER

NEGATIVE

|[~*0C LO L

'Ac/bC Lo [ AND FILTER

S wiTCHING REGULATOR

LT L

> ~15V OUTPUT

VOLTAGE
DETECTION

OVER VOLTAGE]
CROW BAR

OVER CURRENT]
DETECTION
i

Figure 15-4

Regulator Module Block Diagram

iG4b

The +28V dc is used by an efficient switching regulator circuit to produce the +5V dc output. Provisions for
overcurrent detection are incorporated in the regulator circuit so that excess current is limited when there is a
malfunction in the load. The +5V output is also protected against overvoltage by a crowbar circuit which limits the
output to under 7V; before the output gets to this value the crowbar circuit blows the fuse in the output circuit of
the rectifier.

The -28V dc is used by the -15V circuit, which is similar in operation to the +5V regulator circuit. The -15V
crowbar circuit limits the output to 22V.
The LTC L Real-Time Clock synchronizing signal is generated by a simple Zener clipper that is fed from the
transformer secondary.

The BUS AC LO L and BUS DC LO L signals are used to warn the Unibus of imminent power failure. Circuits on the
regulator module detect the transformer secondary voltage and generate two timed TTL-compatible open-collector
signals that are used for power fail functions by devices on the Unibus.
15.3.1

Generation of tRaw DC

As stated in the previous paragraph, the centertapped transformer secondary voltage is rectified and filtered prior to
being fed to the three dc regulators.

The circuitry involved is shown in Figure 15-5. The bridge rectifier D14 is mounted on the heat sink and the input
capacitors C1 and C2 are mounted on the bottom of the regulator module. These capacitors filter the input dc and

are large enough to provide at least 25-ms storage when the input power is shut off or fails.

R45

4.7

J1-3

28VAC

47-63Hz|

FROM(

TRANSFORMER

SECONDARY

NSS-351

1/2W

—

ANA-

_J1-1

>—

[

F1,15A

N\ _o——8——p TO+5V

REGULATOR CIRCUIT

J1-2

24K pF

50V

24KpF_1

50V-T~

3\ }_______fi
Jl+

=+
T

TO AC LO

R44.7k

F2,10A

TO-15V REGULATOR
CIRCUIT

Figure 15-5

Rectifier and LTC L Circuits

A fuse is used on each output to protect the regulator and load during faults. The fuses will not normally blow when
a regulator output is shorted because the three outputs are electronically overcurrent protected. However, the

appropriate fuse will blow in case of +5V or - 15V overvoltage crowbar or in case of failure in one of the overcurrent
circuits.

15-5

The resistor across each fuse provides a slow (100 - 150 seconds) discharge of C1 or C2 after the power is turned off
in case a fuse blows. The capacitors are placed ahead of the fuse to limit the energy in any fault and thus better
protect the outputs.

15.3.2

LTC L Circuit

The LTC L Real-Time Clock synchronizing signal (Figure 15-3) is generated by a Zener clipper circuit. The output
waveform is a square {clipped sine) wave at line frequency. For one polarity of output sine wave, D13 clips at about
+3.9V and in the other polarity D13 clips at its forward voltage of -0.7V.

15.3.3

BUS ACLO L and BUS DC LO L Circuits

The circuitry shown in Figure 15-6 is employed to generate the timed Unibus power status signals specified in Tabie
14-2. These are used for power fail functions. The transformer secondary voltage is rectified by DIl and D2 and

filtered by C9 and R1, R14.

IN4OO4

5”’°
.

28VAC, 47-63Hz FROM

TRANSFORMER SECONDARY

OUTPUT

20uF

AC LO L

10K 1%

S$R6E

S10K 1%

(2!

RIO

10K

Q15

XA55

54V

$10K 1%

SRrit
=

75K

Q14
2N1309

2N1308

Q13

2N1308

Ri3

470

im 1%

Figure 15-6

11-1176

BUS AC LO and BUS DC LO Circuits

Circuit parameters are chosen so that the voltage across C9 will rise slower than the three regulated output voltages
on power-up, and will decay faster than the three regulated output voltages on power-down.
Two differential amplifier circuits are used to detect power status:

C17, Q18 is used to generate BUS DC LO L; and

Q15, Q16 is used to generate BUS AC LO L. The differential amplifiers share a common reference Zener diode D3,
which is fed approximately 1 mA by R3.
As C9 charges subsequent to power-up, first Q17, Q18, and then Q15, Q16 change state; the reverse is true during
power-down. When C9 starts to charge, Q17 and Q16 are on and Q15 and Q18 are not conducting. As C9 charges
further, Q18 starts to conduct into R7 and raises the voltage on cathode D3. This acts as positive feedback and snaps

Q17 off and Q18 on more solidly. A few milliseconds later, the voltage across C9 has risen sufficiently for the same
process to take place in differential amplifier Q15, Q16. The status of each differential amplifier is followed by the
germanium transistor open-collector output stages Q19, Q20 for BUS DC LO L, and Q13, Q14 for BUS AC LO L.

These stages clamp the Unibus at about +0.4V until the differential amplifier circuits sequentially signal them across
R11 and R12 that power is up. The outputs then rise to about +5V as dictated by the Unibus loading and pull-up
termination resistors.

15-6

The sequence is as follows:

power-up —>

then BUSDC LOL=0-then BUSACLOL=0

power-down—>

BUSACLOL=1-BUSDCLOL=1

0 = High (+3V)
1 =low (+0.4V)

Any time that BUS DC LO L or BUS AC LO L go low, there is sufficient storage in capacitors Cl and C2 to
maintain output voltage long enough to permit the power fail circuit to operate. The open collector stages are
designed to clamp the Unibus to 0.4V maximum, even when there is no ac input to the regulator. They are
inherently biased on by R11 and R12 until the differential amplifiers signal that power is OK.
15.3.4

+15V Regulator Circuit

The +15V regulator shown in Figure 15-7 is a simple series regulator. The pass transistor Q1 is a high-gain power
Darlington and is mounted on the heat sink. Base drive current is supplied to Q1 via R38. Q3 acts to limit the value
of this current to the required value by shunting it away from the Q1 base. Q4, the voltage detector amplifier, biases
on Q3 and thus limits current in Q1. The +15V output voltage is sampled on the viewing chain R34, 35, 36 and

compared to the voltage across reference Zener D8, which is fed by R37. If the output should try to increase from
the regulated value, the emitter of Q4 is made more negative (relatively) than its base and conduction through Q4
increases. This increases the conduction through Q3 and causes QI to shut down sufficiently to restore the output
voltage to the regulated value. Ambient temperature compensation of the voltage detector is essentially flat since D8

has a +2 mV/°C temperature coefficient and the base emitter junction of Q4 has a -2 mV/°C temperature
coefficient.

TO PWR OK CiRCUIT
(NOT USED IN POP-11/05)
R33

0.39

+28V FROM RECTIFIER

R32
66

M900

08
K tN753A

R34
383

| 62y

R35

R37

t—%‘f’c

+45V,1A OUTPUT

R36

100

464

11-0968

Figure 15-7

+15V Regulator Circuit

R35 acts as the +15V voltage adjustment potentiometer. C18 is a high frequency stabilization capacitor. Q2 is the
overload detector; when the output current reaches 1.5A nominal, the voltage across R33 is sufficient to cause Q2 to
conduct. This removes base drive from Q1 and causes the regulator to current limit.
15.3.5

+5V Regulator Circuit

The +5V regulator is similar to the +15V regulator in that the sampled output voltage is compared to the voltage
across a reference Zener by a voltage detector transistor, which in turn controls the drivers for the main pass
transistor. The +5V regulator circuit is shown in Figure 15-8. An over-current circuit is likewise employed.
15-7

100uH

Jz-3

010,204
FAST

+5V, 154

OuTPU

6000

RECOVERY

I#F 10V
D11

¥ Nse24
D2

& INTS24,
5.6V

gRse

+28V FROM __

RECTIFIER

Qt1

i€

0.033,F

XA55

c3
I'#F

[

c32ax13s

3
LR46

$47K

R43
c5
6.8uf

10K

Sesk

12w

53¢
1003

35V

RA9
$ 147

SR47

A
¥

C8
T .Otuf

1OV.10% g2 av
Rs

[ AZS

330

Q10

e
I

XAQOS5

4 ce

ci7

6.8uF
=
35VI
=

R51

SR44
330

tuF

3% PT0 S
o

=
-

Figure 15-8

1175

+5V Regulator Circuit

The viewing chain consists of R49, 50, 51 and the reference Zener is D9, which is fed
by R44. Q10 is the detector
amplifier. The pass transistor Q6 and first stage driver Q7 are mounted on the heat
sink. The predriver Q8 is turned
on by R46. The current is diverted from the base of Q8 by off-driver Q9, which is controlled
by Q10. The +15V and
+5V regulators are similar in operation; i.e., a tendency for the output voltage to
rise results in more conduction
through Q10 and resultant limiting of conduction through Q6.
Here the similarity ends. The +5V circuit is a regulator that operates in the switching
mode for increased efficiency.
To get the regulator to switch, positive feedback is applied to the voltage detector
input via R47. Thus the whole
regulator acts as a power Schmitt trigger and is either completely turned on
or turned off, depending on whether the
output voltage is too high or too low. When Q6 is on, it supplies current
through filter choke L1 to the output

smoothing capacitor C7 and the load. When Q6 is off, the L1 current decays through
commutating diode D10,
which becomes forward biased by the back emf of L1. The waveform across
D10 is a 30V nominal rectangular pulse
train. The filtered output across C7 is thus +5 Vdc with about a 200-mV
peak-to-peak 10-kHz nominal sawtooth of

super-imposed ripple. At the crest of the ripple, Q6 turns off and
at the valley Q6 turns on. This switching mode of

operation limits the dissipation in the circuit to the saturated forward
losses of Q6 and D10 and the switching

losses

of Q6. The resultant high efficiency allows the heat sink to be small and the
number 8 power semiconductors to be
few.
R50 is the voltage adjustment potentiometer. R51 is a positive temperature
coefficient wire-wound resistor that
compensates for the fact that the Q10 base-emitter junction and the reference
diode D9 both have negative voltage
temperature coefficients. Q5 current, limited by R39, 40, detects the overcurrent
signal generated across resistor
R41, which is in series with the Q6 collector.

15-8

Output fault current is limited to a safe value because conduction of Q5 makes the reference voltage across D9
decrease to zero. This causes Q10 to conduct and shuts down the regulator. C5 is an averaging capacitor, which is
necessary in the circuit because the current through R41 is pulsating.

High frequency bypass capacitors are used on input and output of the regulator, C3 and C6, respectively. C4 is used
to slow down the turn-on of Q6 to allow D10 to recover from the on state without a large reverse current spike.
In the event a malfunction causes the output voltage to increase beyond about 6.8V nominal, Zener diode D2 will
conduct and fire silicon-controlled rectifier Q11. This will crowbar the output voltage to a low value through D11
and will blow fuse F1 in the rectifier circuit through R52.
15.3.6

-15V Regulator Circuit

The ~ 15V regulator circuit is shown in Figure 15-9. It is essentially the complement of the +5V regulator circuit and
differs only in minor detail.

FROM

RECTIFIER

g3t
L
=

R28
A

R29

115

R31

J2-2,GROUND

R27
Rel

OUTPUT

0.01uF

100

c19

026

Re2uf
35V

r—1' ‘)?028
1/2W

—n—e
R58
330

=013

68K

IN753A

25V

DS, 20A

<E§§g

X FAST
RECOVERY

oK
—N—e Q25

A So00uF

1pF

R24

XAO5

3
Q27 WA

MaCt1-3
T2

%60

100V

0.033uF
1L

1A%

o]
2.2uF
35V

AL
¥

1€

*_l\
R22

gfi

D7,

18V

‘& IN52488

021
XAO5
06

T
In5824
R20

R19

0.06
5W

2N5302

200uH

OUTPUT

J2-9, -15V, 7A

11-0970

Figure 15-9

-15V Regulator Circuit

The crowbar device is a Triac Q27 instead of an SCR. No temperature compensating resistor is required because Q26
and D4 track each other, as in the +15V regulator (Paragraph 15.3.4). The detailed interconnection of the drivers
and the circuit values are different. The - 15V output voltage is adjusted by potentiometer R26.

159

CHAPTER 16
POWER

16.1

SUPPLY MAINTENANCE

INTRODUCTION

Information is provided in this chapter to maintain the power supply. This consists of adjustments, circuit
waveforms, troubleshooting, and parts identification. The adjustments consist of three output potentiometers. The
circuit waveforms provide a guide to proper operation at various places in the circuit. The troubleshooting section
provides rules, hints, and a troubleshooting chart as a maintenance aid in isolating power supply malfunctions.
Finally, the parts identification section provides a directive to obtaining parts information for the entire power
supply unit through a parts location directory to the mechanical engineering drawings in the Engineering Drawing
Manual.

16.2

ADJUSTMENTS

Three adjustments to the power supply adjust the three dc output voltages: +15V, +5V, and -15V. A small
screwdriver is all that is required. Clockwise adjustment of any of the potentiometers increases voltage, and the
potentiometers are located on the top side of the dc regulator module. The potentiometer designations are:
a.

R35-—+15V

RS0-+5V

R26--15V

In performing any of these adjustments note the following:
CAUTION

Do not adjust voltages beyond their 105 percent rating
and adjust slowly in order to avoid overvoltage crowbar,
which will blow dc output fuses.

Do use a calibrated voltmeter; preferably a digital
voltmeter. Voltages should be adjusted to their center
values: +15.0, +5.0, and -15.0, all under load at the dc
cable termination on the system unit,

16.3

CIRCUIT WAVEFORMS

The two basic regulator circuits used on the dc regulator module generate +5V and -15V. Figure 16-1 shows six
waveforms of the +5V regulator circuit taken at two points (A and B) in the circuit (Figure 14-6). Waveformsa, b,
and ¢ are taken at point A, which is the +5V circuit, Q6 transistor output. Waveforms d, e, and f are taken at point
B, which is +5V power supply output (J2-3). Figure 16-1 also indicates the Joad conditions and time scales for each
waveform. Figure 16-2 shows six waveforms of the -15V regulator circuit taken at two points (C and D) in the
circuit (Figure 14-7). Waveforms a, b, and ¢ are taken at point C, which is the - 15V power supply output (J2-9). The
load conditions and time scales of the respective waveforms are indicated in Figure 16-2. These waveforms were
taken on a Tektronix Model 453 Oscilloscope. All waveforms are with respect te J2-2, power common.

16-1

a) Point A, No load,

d) Point B, No load,

2 ms /div, and

2 ms/div, and

b) Point A, No load,

e) Point B, No load,
20 us/div, and

10V/div.

50 mV/div.

20 ps/div, and

10V/div.

50 mV/div.

Point A, 20A load,

20 ps/div, and

Point B, 20A load,

us/div, and

10V/div.

50 mV/div.

Figure 16-1

+5V Regulator Circuit Waveforms

16-2

Point C, No load,

Point D, No load,

5 ms/div, and

b) Point C, No load,

e) Point D, No load,

f) Point D, 5A load,

10V/div.

50 mV/div.

50 ps/div, and
50 mV/div.

50 ps/div, and
10V/div.

Point C, 5A load,
50 ps/div, and

50 ps/div, and

10V/div.

50 mV/div.

Figure 162 -15V Regulator Circuit Waveforms

16-3

164

TROUBLESHOOTING

Troubleshooting information for the power supply consists of troubleshooting rules, hints, and a troubleshooting
chart,

This

information

provides

maintenance

aid

isolating

power

supply

malfunctions

(drawing

D-CS-5409728-0-1).
16.4.1

Troubleshooting Rules

Troubleshooting rules for the power supply are as follows:
a.

Make certain that power is turned off and unplugged before servicing the power supply.

Ensure that input capacitors C1 and C2 are discharged before servicing the power supply. A 10 to 10082,
10W resistor can be used to hasten the discharge of the capacitors. (Be sure power is off.)

The dc regulator module is not internally grounded to the chassis; therefore, shorts to ground can be

located after disconnecting the dc output cable to the system unit.
d.

The dc output fuses F1 and F2 can be replaced without removing the dc regulator module. Before
unsoldering fuses, observe cautions described in Steps a and b.

For proper operation, all hardware must be secured tightly to about 12 inch-pounds (i.e., capacitors,
chokes, semiconductors). All hardware should be replaced with identical hardware replacement parts.

The dc regulator module may be removed from the top of the power chassis assembly while the latter is
still bolted to the computer chassis. The dc regulator module is held in place by six screws.

When replacing power semiconductor components that are secured to the heat sink, apply a thin coat of

Wakefield #128 compound or Dow Silicon Grease to the heat sink contact side (bottom) of the
semiconductor. Insulating wafers are not required.
16.4.2

Troubleshooting Hints
CAUTION

Unplug computer before servicing.

The most likely source of power supply malfunction is the dc regulator module. A quick remedy for a malfunction
may be to replace this entire module. The problem, however, could be a short in the system unit or possibly a

defective component or other problem in the ac input circuit.
The +5V and - 15V regulators contain overvoltage detection circuitry. If R50 or R26 are adjusted too far clockwise,
the corresponding crowbar circuit will trip and blow fuses. To correct this condition: adjust the potentiometer fully

counterclockwise, replace the blown fuse, and re-adjust per Paragraph 16.2.
Make a visual examination of the circuitry. Check for burnt resistors, cracked transistors, burnt printed circuit board
etch, oil leaking from capacitors, and loose connections. A visual check can be a quick method of locating the cause

of a malfunction.

16.4.3

Troubleshooting Chart

In checking the various arcas of the power supply, the rules listed in Paragiaph 16.4.1 should be followed. The
waveforms referenced in Paragraph 16.3 provide a comparison for the troubleshooting readings. Tabie 16-1 provides
the dc regulator troubleshooting chart.

l6-4

Table 16-1

Troubleshooting Chart
Cause

Problem

No +5V and +] 5V output

F1 opened*®

+5V Qutput Too Low

Qs, D9, Q10,Q9,Q11, D12, or D10

D14 or transformer cpened*®
+5V adjusted too high*
Shorted C5 or C7 shorted

R49, R50, R46, or R44 opened
Q6, Q7,Q8, or D11 shorted
A9, Q10, or D9 opened*
R51, or R50 opened

+15V Output Too High

Q1 shorted

E8 opened

R35 or R36 opened

No - 15V Output

-15V Output Too Low

F2 opened

D14 or transformer opened
-15V adjusted too high*

Q25, D4, Q26,Q21, Q27,D7 or DS shorted
C14 or C12 shorted

R22, R26, R25, or R29 opened

Q22, Q23, Q24, or D6 shorted
Q25, Q26, or D4 opened

BUS AC LO L Will Not Go High

Q13, Ql14, or Q15 shorted

Q16 or D3 opened

R7, R3, R6, or R8 opened
C9 shorted

BUS AC LO L Will Not Go Low

Q13, Q14, or Q16 opened

and/or acts erratically on
power-on/power-off

Q15 or D3 shorted

BUS DC LO L Will Not Go High

Q19, Q20, or Q18 shorted

R12, R13, R7, or R10 opened
Q17 or D3 opened

R7, R2, or R6 opened
C9 shorted

BUS DC LO L Will Not Go Low

Q19, Q20, of Q17 opened
Q17 or D3 opened
R7, R3, or R6 opened
C9 shorted

*These causes make the crowbar fire, which in turn, blows the appropriate fuse.

Table 16-1 (Cont)
Troubleshooting Chart
Problem

Cause

BUS DC LO L Will Not Go Low

Q19, Q20, or Q17 opened

and/or acts erratically on

Q18 or D3 shorted

power-on/power-off

R9, R10, R11, or R8 opened

No LTC L Signal

RS5 opened
D13 shorted

LTC L Going Too High

16.5

D13 opened

PARTS IDENTIFICATION

Parts identification for the power supply is provided in the Enginceri
drawings with associated parts lists, which list the respective

ng Drawing Manual. This includes the assembly
unit parts, their part designation, and their DEC part

numbers. These drawings and the respective drawing numbers are
a.

Power Supply Chassis: E-1A-5309816-0-0

Power Control Board 115V: C-1A-5409824-0-0

as follows:

230V: C-1A-5409825-0-0
DC Regulator Module:

E-1A-5409728-0-0

D-CS-5409728-0-1 (schematic)
Power Supply Assembly and Fan: D-AD-7003731-0-0

AC Input Box Assembly: D-UA-H400-0-0
Line Set 115 Vac 7A: C-UA-BCO5H-0-0

230 Vac 5A: C-UA-BC05J-0-0

16-6

PART 5

10-% INCH MOUNTING BOX
AND POWER SYSTEM
Part 5 discusses the following PDP-11/05 and PDP-11/10 Computer models:
Model NC-115 V, 47-63 Hz
Model ND-230 V,47—-63 Hz

These models are packaged in a 10-1/2 in. high mounting box. The prewired backplane
can accommodate 16K of core memory and the computers are normally supplied with
8K of core memory installed. Part 5 describes only the 10-1/2 in. mounting box and
power system. These items are different from the corresponding items that are used in
the 5-1/4 in. high models.
Chapters of Part 5 include:
Chapter 17 Mounting Box

Chapter 18 Unpacking and Installation
Chapter 19 Power System

CHAPTER 17
MOUNTING BOX

17.1

INTRODUCTION

This chapter contains a detailed description of the mounting box (or chassis assembly) used for the PDP-11/05,

11/10 Models NC and ND. The same mounting box is used for both models except for the ac power line set which is
wired for

17.2

115V, 47—63 Hz for model NC and 230 V, 47—63 Hz for model ND.

OVERALL MECHANICAL DESCRIPTION

Figure 17-1 shows the PDP-11/05-NC Computer mounted in a cabinet. The console and top decorative panel (bezel)
are attached to the mounting box with four screws each that are inserted from the rear side of the console and panel.

The lower filler strip is similarly installed with two screws. The mounting screws are located along the vertical sides
and are accessible when the computer is extended from the cabinet.

Figure 17-2 shows the computer fully extended from the rack and locked in the front down 90° position. The top
and bottom mounting box covers have been removed. The power supply cover has been removed also. The top and
bottom mounting box covers are each held in place with four Phillips pan-head screws (#6-32 X 0.37 in. long) and

four #6 lock washers. The power supply cover is held in place with four Phillips pan-head screws (#10-32 X 0.31 in.
long) and four #10 lock washers.
The interior of the mounting box is divided into three compartments. The smallest one extends partially across the
front and contains the power distribution board and two fans for cooling the modules.
The power distribution board is secured to a mounting plate with two Phillips pan-head screws (#6-32 X 0.81 in.

long) and two #6-32 nuts with integral lock washers. The mounting plate contains cutouts to accept the connectors
on the power distribution board. The two logic fans have protective screens on the intake side. Each fan is mounted

on the compartment partition with four Phillips pan-head screws (#6-32 X 0.62 in. long) and four #6 lock washers.
The screws are secured by captive nuts on the fan. Intake air enters the compartment through slots on the left side,
is forced over the modules, and exits through slots in the rear of the mounting box.

The next largest compartment extends from front to rear along the right side. This section contains the power
supply that is installed as an assembly and is held in place by six Phillips pan-head screws (#10-32 X 0.31 in. long)

and six #10 lock washers inserted through holes in the right side of the mounting box into nuts that are integral with
the power supply chassis.
The largest compartment contains the pre-wired backplane, modules, and module guides. The basic computer
contains a standard pre-wired 9-slot backplane installed pin side down next to the power supply. It is secured to

both the front and rear mounting brackets by two Phillips pan-head screws (#10-32 X 1 in. long) and two #10 lock

washers each that are inserted from the bottom through holes in the backplane frame (Figure 17-3). There is enough
space to install one additional 9-slot backplane and one 4-slot backplane or three 4-slot backplanes.

17-1

Two rows of module guides are installed on mounting box brackets at the front and rear of the backplane
compartment. The bottom row is slotted to guide the module into the slot for installation. The top row

is slotted for

the same reason but it also contains a steel rod that is circular in cross section. This rod engages the slotted arm of

the pivoted handles on the hex-width module to provide the mechanical advantage required to properly
seat and
unseat the module.

The

line

set

attached to the rear of the mounting box (Figure

17-4) with two Phillips pan-head screws

(#6-32 X 0.19 in. long). Space is available in the rear of the mounting box for cable access. Three cable retainers
mounted on a bracket on the rear of the mounting box.

6601-2

Figure 17-1

PDP-11/05 NC Computer Mounted In Cabinet

are

UNIBUS
CABLE CLAMP

POWER
SUPPLY

CONSOLE
CABLE

MODULES

BACKPLANE

POWER SUPPLY

FAN

LOGIC FANS
6699-6

Figure 17-2 PDP-11/05 NC Computer Extended and Locked In Front Down 90° Position

17-3

POWER DISTRIBUTION
BOARD CONNECTORS (5)

COMPUTER POWER

LTC TOPIN FV2

PIN SIDE OF
BACKPLANE

+5V(2) ADJUSTMENT ON
H744 REGULATOR

6699-4

Figure 17-3

PDP-11/05 NC Computer Extended and Locked In Front Up 90° Position

17-4

UNIBUS CABLE

UNIBUS

CLAMP

CABLE

! g power control
i v 0w

46 A

LINE SET

CABINET POWER

SCL CABLE

CONTROLLER CONNECTORS

Figure 17-4

17.3

6699-9

PDP-11/05 NC Computer, Rear View

BACKPLANE

The backplane is the connector assembly into which the modules are plugged. It consists of
a group of molded

connectors attached to a metal frame (Figure 17-5). One side provides slots with finger type contacts into which the
modules are inserted. These contacts terminate in wire wrap pins on the other side of the backplane. The pins are
inserted through and soldered to a printed circuit board that is part of the backplane. This board provides most

backplane interconnections and the remaining interconnections are made by wire wrapping the pins (Figure 17-6).
The printed circuit board also contains eight Faston tabs that mate with Faston connectors on the processor power
distribution cable. This cable provides power, ground, and sensing signals from the power supply to the backplane.

The cable also contains a slip-on connector that sends the line time clock (LTC) signal from the power supply to
backplane pin FO3V2.

17-5

6699-12

Figure 17-5

DCLO

Connector Side of Backplane

ACLO

GROUND

+5V

=15V

+15V

GROUND

+5V

6699-3

Figure 17-6

Pin Side of Backplane

17-6

Figure 17-7 shows the backplane pin layout and method of identification. The slots are numbered 1 through 9 and
the rows are lettered A through F. Each row is pinned to accommodate a single-height double-sided module
edge-connector. The backplane accepts single, double, quad, and hex modules. A backplane pin is identified as
follows:

Row

Slot
Pin

Side

FRONT

PIN
SLOT
LAYOUT

0
4
5

sio7T

2
1
{
oV oV |)
ve

eTeOT
ses
e
®

P ®
Fe@

® N eN

M @
MO
oL

Ke
K @
e,

H @
HO
®F eoF

O
E@E

peop

cece

B @8

A®
A O
1
2

ROW A

VIEW FROM WIRE WRAP PIN SIDE,
COMPUTER IN MAINTENANCE POSITION
11-2964

Figure 17-7 Computer Backplane Connector and Pin Designations

17-7

Each module connector contains finger contacts on each side. Module contact designations are shown in Figure

17-8.

The backplane is pre-wired for the configuration shown in Figure 17-9. If an additional backplane is installed to
accommodate additional memory or options, the M930 Unibus Terminator in slot A9-B9 must be removed and
installed in the appropriate slot of the added backplane. In place of the M930 removed from slot A9-B9, an M920

Unibus Jumper module is installed to connect the Unibus signals to the added backplane. The M9970 Cable
Connector module in slot C1-D1 contains a 40-pin Berg connector that accepts the connector on the serial

communications line cable, which is used for the ASR-33, VT0S5, and serial model of the LA30. Slot A1-B1 is wired

for a DF11 Communications Line Adapter that provides signal conditioning for communications devices using
signals that are not TTL compatible. The DF11 works with the serial communications line interface so that when it

is installed, the M9970 module is not used. Slots E1 and F1 are wired for the KM11 Maintenance modules that are
used during troubleshooting operations. The core memory modules must be installed in the designated slots (Figure

17-9), but they are interchangeable.

PODOOMMICcXTrTZ0I30AACCK

18 CONTACTS
ON EACH SIDE

Fr‘

SIDE 1
CONTAINS
COMPONENTS

—

11-1568

NOTES
:
t.

Side

1 is component side
.

2. Each side contains
18 contacts that are designated

A-V (omitting 6,I1,0,Q,W,X,Y,2)
3. Acomplete designation contains
o connector letter prefix,

contact letter,and side suffix number.

for example:

AD2

Figure 17-8

Module Contact Designations

17-8

282
32s

i
22
3

22
O

7
=+

-3
a

]

[=]

—

a
[

IRE

=
w

s
»

S
=

-3

=
w

]

«
a

)

il I

AR
hat
<
~

= |

lL
ltell8=]l|a]!
ell=s]
Sllall
O
IS
o
w
=

|
—
B

AREINHRE
o~

HEPRE:
ol

[

J-

]

l
28
Ef
oz

Dea

°gl

¢
—

o3
m8

—
]
-1

—

1E|
=<9

[| L L_ AN I N T O AN Iy N S B
FRONT

View of module side
of backplane

11-1872

Figure 17-9

17.4

Module Utilization Diagram

POWER SYSTEM

The power system consists of the H750 power supply, BCOST/U line set, power supply wiring harness, power
distribution wiring harness and board, and processor power harness.

The H750 Power Supply converts 115 V or 230 V, 47—63 Hz line voltage to regulated +5 V,+15 Vand -15V for
the computer. The power supply also generates BUS AC LO L and BUS DC LO L, which are the power fail early

warning signals and LTC L which is the real-time clock synchronizing signal.

The line set provides ac line power to the processor: BCOST is used for 115 V and BCO5U is used for 230 V.

The power harnesses and distribution board interconnect the power supply, line set, cooling fans, and backplane.
A detailed discussion of the power system is given in Chapter 19.
179

CHAPTER 18
3

UNPACKING AND INSTALLATION

18.1

INTRODUCTION

This chapter provides information on the unpacking and installation of the computer. Information on installation
certification and warranty service is also included.
18.2

UNPACKING

The computer is shipped ready to operate in a protective box (Figure 18-1) or mounted in a 19-in. cabinet. Remove
the computer from the box and visually inspect for damage. Save the shipping carton and packaging materials in case

it is necessary to return the computer for service. The slide mounts are attached to the computer, but the mounting
screws are packed in a bag placed in the shipping container. Two console keys and a serial communications line
(SCL) cable are also included. The keys are attached to the line cord at the rear of the computer. The standard SCL
cable (70-08360) has a 40-pin Berg connector on one end that mates with the M9970 Cable Connector module. The

other end has a Mate-N-Lok connector that mates to the one used on the LA30 DECwriter (serial model), DEC

VTOS Alphanumeric CRT Display Terminal, and Teletype® Model 33 ASR. If the DF11 Communications Line
Adapter is used instead of the M9970 module, the appropriate cable is included.

A computer shipped in a cabinet is locked in place to prevent movement during shipment. A shipping bracket is
mounted on the back of the cabinet. The heads of two T-bolts are inserted in the cooling slots in the rear of the

computer mounting box, and the heads are turned 90° so that they cannot be withdrawn. The bolt bodies protrude

through holes in the shipping bracket and are secured to it by two nuts. Remove and retain the T-bolts and nuts for
re-use if the cabinet is to be shipped or moved any distance.

18.3

INSTALLATION IN A CABINET

The slide assembly is installed on the computer. Unlock the slide release and remove the outer slide from each side
of the computer. These are the fixed portions of the slide assembly and are mounted in the cabinets as follows.

The front of the fixed slide has an integral bracket and is mounted in the cabinet with two screws that are secured
with captive nuts (Tinnerman nuts). The rear of the fixed slide is attached to a separate L-shaped bracket with two
screws and nuts. The bracket is attached to the cabinet with two screws that are secured with captive nuts. Mount
the fixed slides equidistant from and parallel to the floor.

Lift the computer and slide it carefully into the fixed guides until the slide release engages. Unlock the slide release
and push the computer fully into the cabinet. Extend the computer enough to allow access to the front mounting
screws. Slightly loosen the front and rear slide mounting screws and slide the computer back and forth. This allows
the slides to assume a position that causes minimum binding. Retighten mounting screws.

® Teletype is a registered trademark of Teletype Corporation.

18-1

TOP FOAM

PIECE

SIDE

PROTECTOR

BEZEL

REAR

PROTECTOR

{

SHIPPING
CARTON

1-2139

Figure 18-1

18.4

Computer Packaging

INSTALLATION OF OPTIONS AND CABLES

The basic computer is shipped with a 9-slot backplane that accommodates the processor and 8K or 16K of core
memory. Enough room remains to install three 4-slot backplanes or one 9-slot and one 4-slot backplane.
If options are purchased with the computer, they are installed in the mounting box, space permitting. Adjacent

backplanes are interconnected with an M920 Unibus Jumper module.

18.4.1

Installing Options on Site

Remove the mounting box top and bottom covers. From the top, place the backplanes next to one another with
connector row A at the rear of the box. From the bottom, secure the backplane to the mounting flange at the front

and rear using four screws for the 9-slot version and two screws for the 4-slot version.

18-2

For each option, a power hamess is used to connect the backplane to the power distribution board. All cables use
identical Mate-N-Lok connectors to connect to the power distribution board. The other end of the cable terminates
in Faston connectors or in a cable card, depending on the type of backplane. Faston connectors are used for a
backplane that has its power connections brought out to Faston tabs on the pin side. Refer to the power harness
drawing to identify the Faston connectors on the cable and slip them over the tabs on the backplane which are
identified on the etched surface of the backplane.

If the backplane does not use Faston tabs, the other end of the power harness terminates in a cable card. Refer to
the module utilization drawing for the option and insert the cable card in the designated slot in the connector side of
9

the backplane.

The five connectors on the power distribution board are J1-J5, with J1 next to the power supply. Normally, the
processor backplane is connected to J1, and J2 is not used. If this mounting box is used as an expansion box, J2 can
be used because it is possible to install five 4-slot backplanes in an extension box.

If an MF11-L Memory is to be added, place it next to the processor backplane. Connect the MF11-L power hamess
(70-09206) to J3 on the power distribution board. If another 4-slot backplane is to be added, the box would be
filled and the power hamess for this backplane should be connected to JS. Connector J4 is not used because the
MF11-L backplane takes the space of two 4-slot backplanes.

If three 4-slot backplanes are to be added, connect them to J3, J4, and JS. See Table 3-2 for option power hamess
part numbers.

CAUTION

1. Memory interleaving is not allowed in the PDP-11/05.
2. MM11-E and F Memories must not be installed in the
PDP-11/05 mounting box. Neither the H750 Power Supply
in the PDP-11/05 nor the MM1 1-E and F Memories contain
the DC LO circuit that cuts off ~15V to the memory
during a power interruption to avoid destruction of store
data. These memories must be installed in a box that is
powered by an H720 Power Supply containing the DC LO
circuit.

The MM11-K and L Memories that are installed in the
PDP-11/05 mounting box contain the DC LO circuit.

After the options are installed, use M920 Unibus Jumper modules to distribute the Unibus signals to all backplanes.
Insert an M930 Unibus Terminator module in slots A4-B4 of the last backplane, if it is the last device connected to
the processor.

A BC11-A Unibus cable is used to connect devices in another box to the processor. If the box contains only the
processor backplane, install the Unibus cable rather than the M930 Terminator in slots A9-B9. If other options have
been added, install the Unibus cable rather than the M930 Terminator in slots A4-B4 of the last backplane. Secure
the Unibus cable in the strain relief clamp on the top rear surface of the mounting box (Figure 17-4). Remove the two
screws that hold the Unibus cable clamp to the box. Place the cable between the box and the clamp, install the
screws, and tighten loosely. Plug the cable into the backplane, leaving some slack, and tighten the screws.
Three strain relief clamps are provided on the top rear surface of the mounting box for 1/O device cables.

18-3

18.4.2

Connecting the Serial Communications Device to the Processor

The 70-08360 SCL cable contains an 8-pin Mate-N-Lok connector on one end that mates with the cable on the serial
communications device (Figure 18-2). The other end contains a 40-pin Berg female connector that mates with a

40-pin Berg male connector on the M9970 Cable Card that is inserted in slots C1-D1 in the computer backplane. The

signals are wired, via the pin side of the backplane, to the M7260 Data Paths module. Table 18-1 contains pin and

signal designations at these points and a description of each signal. Figure 18-2 shows the 70-08360 cable and Berg
connector on the M9970. Connect the serial communications device (ASR 33, VTO5, etc.) to the processor as

follows:
1.

Remove the M9970 Connector module from backplane slots C1-D1.

Plug the Berg connector on the 70-08360 SCL cable (supplied with the computer) into the Berg
connector on the M9970.

Insert the M9970 into backplane slots C1-D1.

Connect the Mate-N-Lok connector on the SCL cable to the Mate-N-Lok connector on the cable that is
attached to the serial communications device.

18.4.3

Place the SCL cable in one of the strain relief clamps.

Console Cable

Console cable BCO8R-03 is a 3-ft flat cable with 40-pin female Berg connectors on each end. Table 18-2 lists the pin

and signal designations for the console cable.

18.4.4

Unibus Cable/Jumper

Table 18-3 lists the pin and signal designations for the Unibus BC11A Cable and Unibus M920 Jumper.

18.5

AC POWER SUPPLY CONNECTION

Computers designed for use on 115-Vac circuits are equipped with a 3-prong connector, which, when inserted into a

properly wired 115-Vac outlet, grounds the case of the computer. It is unsafe to operate the computer unless the
case is grounded since normal leakage current from the power supply flows into metal parts of the chassis.

If the integrity of the ground circuit is questionable, the user is advised to measure the potential between the

computer case and a known ground with an ac voltmeter.

18.5.1

Connecting to Voltages Other than 115V

The computer operates at voltages ranging from 95 V to 135 V and from 190V to 270V (47 Hz — 63 Hz),
providing the proper line set is attached to the computer. The plug is part of the line set. The plug configuration and
specifications are shown in Figure 18-3.

On installation outside of the United States or where the National Electrical Code does not govern building
wiring,
the user is advised to proceed with caution.

18.5.2

Quality of AC Power Source

Computer systems consisting of the processor, memory, and peripherals are often sensitive to the interference

present on some ac power lines. If a computer system is to be installed in an electrically noisy environment,
it may

be necessary to condition the ac power line. DEC Field Service Engineers can assist customers in determining

ac line is satisfactory.

18-4

if their

MALE BERG CONNECTOR
ON M9970 MODULE

FEMALE BERG CONNECTOR
ON 70-08360

CABLE

MATE-N-LOCK
ON

CONNECTOR

70-08360 CABLE

11-2076

Figure 18-2

SCL Cable 70-08360

18-5

Table 18-1
SCL Interface Pin and Signal Designations

70-08360 CABLE

SIGNAL NAME

MATE-N-LOK PIN

BERG PIN

SIGNAL NAME

ON 70-08360

ON 7008360

ON M9970

ON M7260

CABLE

CABLE CARD

MODULE

M7260

SIGNAL

DESCRIPTION

SER 0 + (20 mA)

DPHSEROL

FE2

+20 mA SERIAL OUT (from computer)

SER 0 - (20 mA)

DPH SER 0-15L

FJ2

-20 mA SERIAL OUT

SER IN +(20 mA)

DPH SER IN H

FN1

+20 mA SERIAL IN (to computer)

SER IN - (20 mA)

DPH SI-15 L

FP1

-20 mA SERIAL IN

READER RUN + (20 mA)

DPH RDR ENAB L

FK2

+20 mA TTY READER ENABLE

READER RUN - (20 mA)

DPHRE -15 L

FRI

-20 mA TTY READER ENABLE

SER 0 (TTL)

DPH SER 0 H

DF1

SERIAL DATA OUT (from computer)

NOTE 1

SER IN (TTL)

FSSERINH

FM1

SERIAL DATA IN (to computer)

NOTE 1

CLK IN (TTL)

ccC

FSCLK L

FH1

EXTERNAL CLOCK INPUT FOR SCL

NOTE 1,2

CLK DISAB (TTL)

FS CLK DISAB L

FH2

DISABLE LINE FOR INTERNAL SCL

NOTE 1,3

CLOCK

20 mA INTERLOCK

H,E

NOT USED ON THIS INTERFACE

+5V

+5 V POWER AVAILABLE EXTERNALLY

+15V

+15 V POWER AVAILABLE EXTERNALLY

GROUND

AB,UUVV

LOGIC GROUND

NOTE 1: These signals are TTL compatible.
NOTE 2: Externally supplied SCL CLOCK must be 16 times desired buad rate

(max. baud rate is 10,000 baud).
NOTE 3: This signal must be asserted low to disable internal clock if the external TTL CLOCK is to be used.

18-6

Table 18-2

BCO8R-03 Console Cable Pin
and Signal Designations
Designations

Signals

H
DAK

SW 15 (1) H
H
SW 14 (1)
SW 13 (1)H

mfizwmmnggégfit\:x<—1x2r‘~:}];%;

SW12(1)H
SW11(1)H

SW10(1)H

SWO09 (1)H
SWO08 (1)H
SWO07 (1)H

H
SW06 (1)
H
SWO05 (1)
SW 04 (1)H
SWO03(1)H
SW02(1)H

SWO01(1)H

H
SWO0o (1)

L
SCAN ADRS 01 (1)
SCAN ADRS 02 (1) L
SCAN ADRS 03 (1) L
SCAN ADRS 04 (1) L
PUP
L
RUNL

KEY LOAD ADRS (1) L
KEY EXAM (1)L
KEY CONT (1) L
KEY HLT ENB (1) L
KEY START (1)L
KEY DEP (1) L

18-7

Table 18-3
Unibus BC11A Cable/M920 Jumper
Pin and Signal Designations

Designation

Signals

AAl
AA2
ABI1

INITL
POWER (+5 V)
INTRL

BA1
BA2
BB1

BG 6 H
POWER (+5 V)
BGSH

AB2

GROUND

BB2

GROUND

AC1

DOOL

BC1

BRSL

AC2

GROUND

BC2

GROUND

AD1

DO2L

BD1

GROUND

AD2
AE1

D01 L
D04 L

BD2
BE1

BR4L
GROUND

AE2

DO3 L

BE2

BG4H

AF1

D06 L

BF1

ACLOL

AF2

DOS L

BF2

DCLOL

AH1

D08 L

BH1

AO1L

AH2

DO7L

BH2

AOOL

All

DIOL

BJ1

AO3 L

AJ2

D09 L

BJ2

AO2 L

AK1

DI2L

BK1

AOS L

AK?2

DI1L

BK?2

AO4 L

ALl

D14 L

BL1

AO7L

AL2

DI3L

BL2

AQ6 L

AMI1
AM?2

PAL
DISL

BM1
BM?2

A09 L
AO8 L

AN1

GROUND

BN1

AllL

AN2

PBL

BN2

AIOL

AP1
AP2
AR1

GROUND
BBSY L
GROUND

BP1
BP2
BR1

Al3L
Al2L
AlSL

AR2

SACKL

BR2

Al4L

AS1

GROUND

BS1

Al7L

AS2

NPR L

BS2

Al6 L

ATI

GROUND

BT1

GROUND

AT2

BR7L

BT2

ClL

AUl

NPG H

BU1

SSYNL

AU2

BR6L

BU2

COL

AV1

BG 7H

BV1

MSYN L

AV2

GROUND

BV2

GROUND

18-8

B8CO5U
MALE PLUG

BCOST
MALE PLUG

(SINGLE PHASE)

WJI

PHASE

CONNECTOR

NEMA
MODEL
NUMBER | CONFIGURATION

GROUND

g
NEUTRAL
OR RETURN

DESCRIPTION

SPECIFICATIONS

|POLES|WIRES

RECEPTACLE

PLUG

DEC

HUBBEL

PART NO.

DEC

| nusBEL

PART NO.

|12-05351 | 5262

BCOST

5-15

115V, 15AMP

|90-08938|

5266-C

BCOSU

6-15

230V, 15 AMP

|90-o08853|

sees-c | 12-1204 | 5662

*ADD P SUFFIX FOR PLUG

1-1761

ADD R SUFFIX FOR RECEPTACLE

Figure 18-3

Connector Specifications for Line Set

18.6 CABINET POWER CONTROL
18.6.1

Introduction

The PDP-11/05 and PDP-11/10 Computers have provisions to allow the console switch to control the operation of
the cabinet mounted 860 or 861 Power Controller.

The computer is connected to the power controller via Mate-N-Lok connector J3 or J4, each of which is part of the
power supply harness (H1). These connectors are mounted on the power supply chassis and are accessible at the rear
of the computer(Figure 17-4). Two connectors are provided so that other devices in the cabinet can be connected in
a daisy-chain manner to the power controller. A typical cabinet power control system wiring diagram using a
PDP-11/05 and one power controller is shown in Figure 18-4.

When the PDP-11/05 console switch is in the POWER or PANEL LOCK positions, the power controller is activated
and power is supplied to all devices in the cabinet. In multi-cabinet systems, appropriately wired power controllers in
the additional cabinets are activated when the PDP-11/05 console switch is in the POWER or PANEL LOCK
positions.

The power controller provides eight switched power outlets and four unswitched outlets. The 860 controller outputs
are available at two connector strips installed in the cabinet. The 861 controller outputs are installed in the
controller front panel.

Functionally, both the 860 and 861 operate in the same way. A 3-wire cable is used to interconnect power

controllers, computer, and other peripherals in a system. Line 1 is a POWER REQUEST, Line 2 is EMERGENCY
SHUTDOWN, and Line 3 is SIGNAL RETURN (ground). Line 2 is connected to Line 3 through a thermostat,
mounted on the controller. The controlier LOCAL/OFF/REMOTE switch is placed in the REMOTE position for this
application. Placing the PDP-11/05 console in the POWER or PANEL LOCK position, connects lines 1 and 3 which
energizes the power controller and supplies ac power to the system. If an overtemperature occurs in a cabinet, the
thermostat closes, connecting lines 2 and 3, and disables the switched outlets of all controllers in the system. The
unswitched outlets are not affected. Refer to the 861-A,B,C Power Controller Maintenance Manual
DEC-00-H861A-A-D, for additional information.

18-9

860 OR 861 CABINET

UNSWITCHED AC(4 OUTLETS)

= o—o—q"—"’""“'?_:""

TO UNSWITCHED AC
i

10 MOTOR

OREET

]

l ME
ME

1 | SROY

AC POWER)

2
3

2
i
2
AMBMNMNE

l
fe
T
L_owssrs

-O-

—

18.6.2

2
3

ETE
o]
— |

Figure 18-4

—

TO SWITCHED AC

f=——=-—-=-= A

1 l

| 1
1
!

_é_________o_&_—_odz

J—:_!——o =

r \_:f ————— M

ng gf_’ggq?

UNSWITCHED AC (8 OUTLETS)

P%YE(”)‘L

um—-l

POWER CONTROLLER

l —
'
|

2
3

controL

7008288

2
3

e
CIRCUIT

CONSOLE
SWITCH
s LA

RSE Sg
o13d o

2],
3l

|
|

|
]

BUS

CABLE

°
N.O.
CABINET

THERMOSTAT

rees

Typical Cabinet Power Control System Wiring Diagram

Typical Multi-Cabinet Installation

Figure 18-5 shows a typical multi-cabinet installation. Specifically, it shows the interconnection of the
PDP-11/05

Computer, three power controllers, and three model H720 E/F Power Supplies in a three-cabinet system. The

interconnection is identical for model 860 or 861 Power Controllers.

The 3-wire cable (7008288) that is used to interconnect the power controllers and computer allows

the controllers

to be operated in the local or remote mode and permits switched power to be shut off
if any power controller

overtemperature switch is activated.

In this example, each power controller should have its LOCAL/OFF/REMOTE switch in the
REMOTE position in
order to respond to the computer key switch. Placing the computer key switch in the POWER
or PANEL LOCK
position, with the power controller switch in the REMOTE position, energizes
the controller and supplies ac power
to the switched outputs. If the power controller switch is placed in the LOCAL position, ac power
is supplied to the
switched outputs and the computer key switch does not affect controller operation.
Individual cabinets can be
turned on and off using the LOCAL switch position, which is convenient during
system troubleshooting. Power is
supplied to the unswitched outputs in the LOCAL or REMOTE switch positions
as long as the controller circuit
breaker is on.

Figure 18-5 shows two methods of supplying power to options that use H720 E/F type power supplies.
The first, or local method, relates to the H720 E/F that is connected to the power controller in

additional cabinet 1.
The power controller interconnection cable is not used: jumper plugs 7007006-1 and 7007006-2
are installed in the
two unused connectors. The ac line cord for the H720 E/F is plugged into the
power controller switched ac outlet.

18-10

JUMPER

7007006-2

7007006-1

PLUG

123

]

LOCAL

PRIMARY

AC POWER

H720 E/F

UNSWITCHED

UNSWITCHED SWITCHED

| -

AC OUT

[123]
l i

7008288
CABLE

|
1

L23

L‘23

AC OUT

POWER CONTROLLER

(ADDITIONAL CABINET 2)

(ADDITIONAL CABINET 1)

(PROCESSOR CABINET)

SWITCHED

UNSWITCHED

SWITCHED

AC OUT

POWER CONTROLLER

[123]

PRIMARY

AC POWER

(OPTIONAL)

AC OUT

LINE CORD

PRIMARY

7008288
CABLE

23]

{123

7008964
CABLE

123

CRIMARY

2
¢

} |, JUMPER BUS
-1
[17007006
¢

(CONSOLE KEY SWITCH
CONTROLS POWER)

AC POWER

PDP-11/05 COMPUTER

PRIMARY

HT20E/F

AC POWER

REMOTE
(OPTIONAL)

HT20E/F

REMOTE

{OPTIONAL

7008288 CABLE

I
1-2135

Figure 18-5 Interconnection of Power Controllers in Multi Cabinet Installation

The H720 E/F REMOTE/LOCAL switch is placed in the LOCAL position. This power supply is turned on when the

computer key switch is placed in the POWER or PANEL LOCK position.

The second, or remote method, relates to the two H720 E/F Power Supplies associated with the power controller in
additional cabinet 2. Both supplies are daisy-chained to the controller using the interconnecting cable. The first

H720 E/F is connected to the controller with 2-wire cable 7008964. In turn, it is connected to the second H720 E/F
with 3-wire cable 7008288. This power supply has jumper 7007006-1 installed in the unused connector. Both H720

E/F REMOTE/LOCAL switches are placed in the REMOTE position, and both ac power cords are plugged into wall
outlets. These supplies are turned on when the computer key switch is placed in the POWER or PANEL LOCK
position. Each H720 E/F can be tumed on individually with the computer key switch OFF by placing the power
supply switch in the LOCAL position.

18.7 INSTALLATION CERTIFICATION

The MAINDEC User’s Manual that comes with the diagnostic package should be consulted for the appropriate
diagnostic to be run, depending upon the attached devices. The MAINDEC User’s Manual lists the devices that each
diagnostic will exercise. The three system exercisers presently available are TI17 System Exerciser

1811

(MAINDEC-11-DZQKB) for relatively small systems, General Test Program (MAINDEC-11-DZQGA) for medium to

large systems, and Communications Test Program (MAINDEC-11-DZQCA) for communications-oriented systems. At
least one of the above diagnostics and, if appropriate, the other two, should be used to verify system operation.

Once the diagnostic is selected, the respective diagnostic write-up should be consulted for specific operating
instructions. If the user is not familiar with console operation and/or procedures for loading paper tapes, he should

read Chapter 4.

18.8

WARRANTY SERVICE (DOMESTIC ONLY)

The PDP-11/05 Computer is sold with the 30 day, return-to-tactory warranty. If the computer warranty period has

expired or it is covered by on-site warranty, the local DEC field service office should be contacted. If the computer
is still covered by the 30 day, return-to-factory warranty, and factory service is required, the following procedure

should be used.

Call the Maynard, Massachusetts Repair Depot, Telephone 617-897-5111, X4079 or X2135.

The caller will receive a retum authorization (RA) number that must appear on the shipping label of the
returned package. Do not return equipment for repair unless it has an assigned RA number.

Package the computer in a shipping container equivalent to the one that it arrived in. Use the original
shipping container, if possible.

Send the computer to the following address:

Digital Equipment Corporation
146 Main Street
Maynard, Massachusetts 01754
Attn:

Depot Repair, Bldg. 8-2

RA #XXXX

The PDP-11/10 Computer is sold with the 90 day, on-site warranty. Call the local DEC field service office if service
is desired.

18-12

CHAPTER 19
POWER SYSTEM

19.1

INTRODUCTION

This chapter provides a mechanical description of the power system that consists of the H750 Power Supply,
BCOST/U line set, and three wiring harnesses. A system functional description and detailed electrical interconnection
diagram is included.

The regulator circuits are discussed in detail. Regulator maintenance and troubleshooting information is included
also.

19.2

MECHANICAL DESCRIPTION

19.2.1 Power Supply

The power supply consists of three transformers (T1, T2, T3), dc regulator (PS1), +5 V regulator (PS2), relay (K1),
diode board (PS3), terminal board (TB1), and fan mounted in a sheet metal chassis (Figures 19-1 and 19-2).
The chassis is rectangular in shape and measures approximately 22 in. long by 9-1/2 in. high by 5 in. wide. The top
and left side are open and all the components are mounted on the solid bottom and right side. The main structual

member is the mounting plate that is a single piece of sheet metal bent to form the right side and bottom of the
chassis, Two end pieces are welded to the mounting plate. Component mounting is facilitated by threaded inserts
that are installed in integral brackets and by holes in the right side and bottom of the chassis. The front cover has a

cutout for the fan and holes for the fan mounting screws. The rear cover has cutouts for the line set and two
Mate-N-Lok connectors. Several holes in this cover allow air to be drawn in by the fan to cool the power supply.
The power supply components are mounted as follows.

The dc regulator (PS1) is attached to six integral brackets on the side of the chassis with six Phillips pan-head screws

(#6-32 X 1/2 in. long) and #6 lock washers. The regulator is installed with the heat sink facing inward. The screws
pass through holes in the board and are threaded into inserts in the brackets.

The additional +5V regulator (PS2) is attached to the side of the chassis with four Phillips pan-head screws

(#440 X 5/16 in. long) and four #4 lock washers. The screws pass through holes in the chassis and are threaded into
four standoffs (#440 X 3/4 in. long) that are attached to the +5 V regulator mounting bracket.

The diode board (PS3) is attached to the side of the chassis with two Phillips truss-head screws (#6-32 X 3/8 in.
long) and two #6 lock washers. The screws pass through holes in the chassis and are threaded into two standoffs

(#6-32 X 3/4 in. long) that are attached to the diode board.

19-1

+5V REGULATOR

DIODE BOARD PS3

TRANSFORMER T3

PS2

DC REGULATOR PS1

Lerom

g2t 93

RELAY K1

TRANSFORMER T2

TRANSFORMER T1
6699-8

Figure 19-1

Power Supply Side View

Relay K1 is attached to the side of the chassis with four Phillips truss-head screws (#8-32 X 5/8 in. long) and four
#8-32 Kep nuts that have integral lock washers.
Transformers T1 and T2 are attached identically to the side and bottom of the chassis. Each transformer is attached

to the bottom of the chassis by four Phillips flat-head screws (#8-32 X 1/4 in. long). The screws pass through
dimpled holes in the chassis and are threaded into #8-32 standoffs that are attached to the transformer. Each
transformer is attached to the side of the chassis at its top and bottom. At the top, the attachment is made with two

Phillips truss-head screws (#10-32 X 7/16 in. long) that pass through holes in the chassis and transformer bracket
and are secured by two #10-32 Kep nuts. These nuts are accessible inside the chassis. At the bottom, the attachment
is made by two identical screws; however, they are threaded into two #10-32 U-shaped, self-retaining speed nuts

(Tinnerman nuts) attached to the transformer bracket. Tinnerman nuts are used because these attaching points are
not accessible from inside the chassis.

Transformer T3 is attached with two Phillips truss-head screws (#8-32 X 3/8 in. long) that pass through holes in the
chassis and transformer bracket and are secured by two #8-32 Kep nuts.
Terminal block TBI is attached to the side of the chassis with two each Phillips pan-head screws (#6-32 X 5/8 in.
long), #6 lock washers, and #6-32 Kep nuts.

The fan is attached to the front end of the chassis with four Phillips pan-head screws (#6-32 X 5/8 in. long) and four
#6 lock washers. The screws pass through holes in the chassis and are secured by self-retaining nuts on the fan.

19-2

POWER

SUPPLY FAN

CONNECTORS
H1-J3 AND

CONNECTOR H1-P1

H1-J4 (TOP)

TO LINE SET

TO CABINET
POWER
CONTROLLER

FRONT

6699-2

6699-5

Figure 19-2

Power Supply, Front and Rear Views

19-3

19.2.1.1

DC Regulator — The 5049728 dc regulator (Figures 19-3 and 19-4) consists of a printed circuit board,

heat sink, discrete electronic components, thermostat with cable connector, ac input and dc output connectors, and
attaching hardware. Table 19-1 lists the specifications for the 5409728 dc regulator.

+15V

ADJUSTMENT

POTENTIOMETER
,

+5V

ADJUSTMENT

POTENTIOMETER

)

-15V

ADJUSTMENT
POTENTIOMETER

HEAT SINK

THERMOSTAT

MATE-N-LOK
CONNECTOR

-15V PICO

FUSE

+5V PICO FUSE

6211-2

Figure 19-3

DC Regulator, Top View

19-4

Current shipments use regulator 5409728-0-0, J revision that is discussed in this manual. Earlier revisions differ in
component values and current ratings. Engineering drawings applicable to the module used are shipped with the
equipment. These drawings include a schematic of the dc regulator module that shows component values and part
numbers.

FILTER CAPACITORS

DC OUTPUT
MATE-N-LOK

CONNECTOR

AC INPUT
MATE-N-LOK

CONNECTOR

6211-1

Figure 19-4

DC Regulator, Bottom View

19-5

The printed circuit board measures approximately 10 in. long by 5 in. wide with about half of the top surface
devoted to the heat sink. The power transistors and power rectifiers are bolted to two shelves on the sides of the
heat sink and make contact with the circuit board directly underneath via solder and screw connections. The heat
sink is hard anodized for electrical insulation.

The other half of the top surface is devoted to interconnecting and mounting the balance of the circuit components.
Three output voltage adjustment potentiometers (+5 V, +15 V and -15 V) are accessible on the top surface of the
board.

Table 19-1

DC Regulator 5409728 Specifications
Input Specifications

Specification

Parameter

Input Voltage (1 phase, 2 wires and ground)*

95-135/190-270 V

Input Frequency

47—-63 Hz

Input Current

5/2.5 A rms

Input Power

325 W at full load

Inrush

80/40 A peak, 1 cycle

Rise Time of Output Voltages

30 ms max. at full load, low line

180/360 V, 1 second

Input Overvoltage Transient

360/720V, 1 ms
Storage After Line Failure

25 ms min., starting at low line, full load

Input Breaker (part of BCOS line set)

10 A/5 A single-pole, manually reset, thermal

Thermostat Mounted on heat sink (opens

277V, 7.2 A contacts

Opens 98°~105° C
Automatically resets 56°—69° C

transformer and fan power)

Line cord on BCOS line set, length and plug

Input Connections

type specified with BCOS
Turn-On/Turn-Off

Application or removal of power

Hipot (input to chassis and output)

2.1 kV/dc, 60 seconds

*Input voltage selection, 115 or 230 V, is made by specifying the appropriate line set, DEC Model BCOST or
BCO5U. All specifications are with respect to the BCOS input.

Continued

19-6

Table 19-1 (Cont)

DC Regulator 5409728 Specifications
Output Specifications

Parameter

Specification
+15V

Load Range
Static

Dynamic

—

Max. Bypass Capacitance in load for 30 ms turn-on

500 mF

Overvoltage protection

None

Current limit at 25° C

1.3At01.7A(-6.2mA/° C)

Backup Fuse

15 A (also used for +5 V)

Adjustment

+5% min.

Regulation (All causes including line, load, ripple,

*5%

noise, drift, ambient temperature)
5V

Load Range

Static

0—15 A

Dynamic #1

+5 A (within 0—17 A load range)

Dynamic #2

No load — full load

Max. Bypass Capacitance in load for 30-ms turn-on

2000 uF

Overvoltage Crowbar (blows fuse)

5.7—6.8 V actuate (7 V abs. max. output)

Current Limit at 25° C

24-294 A(-0.1 A/° C)

Backup Fuse (series with raw dc)

15A

Adjustment Range

+5% min.

Regulation
+0.5%

Line

Static Load

Dynamic Load #1

Dynamic Load #2

+10%

Ripple and Noise

4% peak-to-peak

1000 Hour Drift

+0.25%

Temperature (0—60°)

19-7

Table 19-1 (Cont)

DC Regulator 5409728 Specifications
Output Specifications

Parameter

Specification
-15V

Load Range
Static

0-7A

Dynamic #1

Al=5 A (0.5 Alus)

Dynamic #2

No load — full load (0.5 A/us)

Max. Bypass Capacitance in load for 30-ms turn-on

1000 uF

Overvoltage Crowbar (blows fuse)

17.4—20.5 V (22 V abs. max. output)

Current Limit at 25° C

10-13.3 A(-0.03 A/°C)

Backup Fuse (series with raw dc)

Adjustment Range

+5% min.

Regulation

Line and Static Load

Dynamic Load #1

+2.5%

Dynamic Load #2

*3%

Ripple and Noise

3% peak-to-peak

1000 Hour Drift

10.25%

Temperature (0—60° C)

*1%
BUSDCLOL and BUSACLOL
Static Performance at Full Load

(for 230 V connection, double voltages below)
BUS DC LO L goes to high

74—80 Vac line voltage

BUS AC LO L goes to high

8—11 V higher

BUS AC LO L drops to low

80—86 Vac line voltage

BUS DC LO L drops to low

7~-10 V lower

Hysteresis (contained in above specifications)

3—-4 Vac

Output voltages still good

70 Vac line voltage

19-8

Table 19-1 (Cont)

DC Regulator 5409728 Specifications
Output Specifications

Parameter

Specification
BUSDCLOL and BUS ACLO L (Cont)
Dynamic Performance

Worst case on power-up is high line, full load.

POWER ON

SLOWEST QUTPUT

]
I

COMES UP

1
]

30ms

= max :

BUS DC LO L

]
!

2ms_

"M'N":

BUS AC LO L

i
]

IEM

NOMINAL

"- 1094

Worst case on power-down is low line, full load.

POWER DOWN
]

25ms

MIN

!
|

FASTEST OUTPUT
GOES DOWN

1
1

: Sms

M MIN]

‘

]

Sms

BUS AC LO L

|
!

:‘—MIN"— 1ms MIN——-——Ds

BUS DC LO L
n-1099

Output Characteristics

50 mA sinking capability

Open Collector

+0.4 V max. offset

5 V nominal, 180 § impedance

Puli-Up Voltage on Unibus

1 ps max.

Rise and Fall Times

Outputs shall remain in O state subsequent
to power failure until power is restored
despite Unibus pulling voltages remaining.

19-9

Table 19-1 (Cont)
DC Regulator 5409728 Specifications
Mechanical and Environmental Specifications

Parameter

Specification

Weight

7 Ib approx.
18 Ib approx.

Dimensions

10.50 in. length
5.19 in. width
3.25 in. height

Minimum Cooling Requirements

375 ft3/min through heat sink
250 ft3 /min over caps, chokes, and transformer

Rated Heat Sink Temperature

95° C max.

Shock, Non-Operating

40 G (duration 30 ms) 1/2 sine in each of six
orientations

Vibration, Non-Operating

1.89 G rms average, 8 G peak; varying from
10 to 50 Hz, 8 dB/octave roll-off 50—200 Hz;
each of six directions

Ambient Temperature

0 to +60° C operating
-40 to +71° C storage

Relative Humidity

95% max. (without condensation)

Altitude

10K ft

19-10

Two small Pico @ fuses are soldered to split lug terminals on the fan end of the PC board. These fast-acting
fuses blow only when some component is defective or when the +5V or -V is too high. The two input filter

capacitors are held to the underside of the board by a bracket and are connected to the circuit via jumper tabs on
the fan end.

The +5V and ~15 V output filter capacitors and inductors are mounted on the bottom surface of the board. The
capacitors (C7 and C14) are attached with screws that are threaded into the capacitor terminals. The inductors (L1
and L2) are attached with integral terminal studs that pass through the board and are secured by Kep nuts.

19.2.1.2 +5 V Regulator — The H744 +5 V Regulator (Figures 19-5 and 19-6) consists of a printed circuit board, heat
sink, discrete electronic components, input/output connector, and attaching hardware mounted on a sheet metal
bracket.

The main structural member is a U-shaped sheet metal bracket that measures approximately 8 in. high X 5-1/4 in.
wide X 2-3/4 in. deep. The heat sink is mounted in the open top of the bracket with its cooling fins facing outward
and component mounting surface facing inward. It is held by two screws on each side that pass through holes in the
bracket and are threaded into holes in the heat sink.

The printed circuit board is mounted with its component side facing inward on the rear of the bracket. It is mounted
on two corner lugs on the lower edge of the bracket by two screws that pass through the board and are threaded into
inserts in the lugs. The top of the board is attached to the rear side of the heat sink by the same hardware that is
used to attach the transistor (Q2) and diodes (D4 and D5) to the top side of the heat sink. The large input filter
capacitor (C1) is retained in an L-shaped holder that is attached to the bottom and left side of the bracket with two
screws. The capacitor is electrically connected by two straps that are secured to the capacitor terminals with screws
and are soldered to the printed circuit board. Output capacitors (C8 and C9) are mechanically and electrically
connected to the printed circuit board with screws. The output inductor (L1) is mechanically and electrically
connected to the printed circuit board with integral terminal studs that pass through the board and are secured by
Kep nuts.

The input/output Mate-N-Lok connector is attached to the bottom right side of the board and is accessible through a
hole in the side of the bracket.

A small notch in the bottom of the bracket provides access to the voltage adjustment potentiometer.

A clear plastic cover is mounted on four mounting lugs on the front of the bracket. It is held by four standoffs that
have male threads on one end to attach the cover and female threads on the other end by which the regulator is
mounted to the power supply chassis.
19.2.2

Line Set

The line set consists of a BCOST (115 V) or BCO5U (230 V) ac power cord installed in and wired to an ac input box
(drawing C-UA-BCO5T-0-0 or C-UA-BCO5U-0-0). The box is a U-shaped sheet metal bracket with a slide-on cover
that is locked in place with one screw (Figures 19-7 and 19-8). The box contains a circuit breaker, printed circuit

board, RF1 dual-disc ceramic capacitor, and a 6-socket Mate-N-Lok connector. The circuit breaker is mounted on
one end of the box so that the reset button is accessible when the line set is installed in the computer. The printed
circuit board is mounted on the circuit breaker terminals with two screws to provide the electrical interconnection
for the circuit breaker. The board is used to mount and interconnect the RFI capacitor, Mate-N-Lok connector, and
Faston tab connectors for the ac power cord. The phase (black) and neutral (white) wires of the ac power cord are

connected directly to the Faston tabs on the printed circuit board. The ground (green) wire of the ac power cord is
connected to a dual Faston tab on the bracket and then to the Faston tab on the printed circuit board.

The 115 V and 230 V models differ in two respects: breaker current rating (10 A for 115 V and 5 A for 230 V) and
the layout of the printed circuit jumpers for connection to the transformers.

@Pico is a trademark of Littlefuse Electrical Supply.
19-11

INPUT
FILTER

FUSE

PASS TRANSISTOR Q2

16-10550

MMC-4347
7804

OUTPUT FILTER
CAPACITORS

INPUT
RECTIFIER

OUTPUT
FILTER

INDUCTOR

CROWBAR
SCR D7

COMMUTATING
DIODE D5

6699-10

Figure 19-5

+5 V Regulator, Side View

19-12

INPUT/OUTPUT
CONNECTOR J1

HEAT SINK

PC BOARD
6699-7

Figure 19-6

+5 V Regulator, 3/4 Bottom View

19-13

CIRCUIT BREAKER

PC BOARD

RFI CAPACITOR

st 'y
©

__—

MATE-N-LOK
CONNECTOR

6712-13

Figure 19-7

BCOST Line Set, Cover Removed

gy power control
3 bcost 4762wz
115V NOM

68 AMP

AC LINE

CORD

RESET BUTTON

6712-9

Figure 19-8

BCOST Line Set, Rear View

19-14

19.2.3

Wiring Harnesses

Two mechanical features concemning the wiring hamnesses are worth mentioning. One is that terminal block TB1 is
considered part of the power supply hamess (drawing E-IA-7009207-0-0). It is a Cinch #8-540 and contains eight
pairs of screw type terminals.

The other feature is that the power distribution board is part of the power to distribution board hamess (drawing
E-IA-7009208.0-0). It is a printed circuit board and the harness wires are soldered to eyelets on the board. The
signals on these wires are connected to five identical 9-pin Mate-N-Lok connectors on the board via the etched
circuit.

19.3 SYSTEM FUNCTIONAL DESCRIPTION

A functional block diagram of the power system is shown in Figure 19-9. Assume that the line cord is plugged in and

the console switch is OFF. Line voltage is applied to the primary of transformer T3 and produces 28 Vac in the
secondary of T3, which is connected to the diode board (PS3). The diode board rectifies the secondary output of T3
to energize the coil of relay K1. The +28 V from PS3 must pass through relay coil K1, PS1 regulator, thermostat,
and the console switch to ground to complete the circuit. If the console switch is OFF or the thermostat is open
(overtemperature condition), relay K1 cannot be energized. This prevents ac line voltage from being applied to
transformers T1 and T2 and all three fans.

When the console switch is placed in the POWER position, the relay coil circuit is completed and the relay is
energized. Two sets of normally opened relay contacts now close and ac line voltage is applied to all three fans and
the primaries of transformers T1 and T2. The 28 Vac secondary voltage from T1 is applied to the rectifier circuit in
the PS1 regulator and the 28 Vac secondary voltage from T2 is applied to the rectifier circuit in the PS2 regulator.
The outputs of the regulators are sent to the power distribution board and on to the backplane.
The power supply hamess contains two Mate-N-Lok connectors that allow connection to the optional cabinet
mounted power control unit. This device allows all units in a single or multi-cabinet system to be turned on using the
computer console switch. The power control unit automatically removes ac line power if an overload or
overtemperature condition occurs in a cabinet.

A detailed power system interconnection diagram is shown in Figure 19-10. All connector and component pins are
identified to allow detailed circuit tracing.

19.4 SYSTEM CIRCUIT DESCRIPTION
19.4.1

Introduction

This paragraph provides circuit descriptions of the 115 V and 230 V line sets, power distribution board, dc regulator,
and +5 V regulator.
19.4.2

Line Set

The 115 V and 230 V line sets differ only in the circuit breaker current rating and printed circuit board jumper
configuration. For 115 Vac power, the jumpers connect both primaries of transformers T1, T2, and T3 to 115 Vac

in parallel (Figure 19-11). For 230 Vac power, the jumpers connect both primaries of each transformer (T1, T2, and
T3) to 230 Vac in series (Figure 19-12).

19.4.3

Power Distribution Board

The circuit schematic for the power distribution board is shown in Figure 19-13. The outputs of the dc regulator
(PS1) and +5 V regulator (PS2) are sent via the power distribution hamess to the board. The harness wires are
soldered to eyelets on the board. The signals on these wires are distributed via the etch to the five 9-pin Mate-N-Lok
connectors (J1—J5) on the board as shown in Table 19-2.

19-15

115V/10A

Phase

|Neutrat

TRANS
T3

230V/ 54

LOGIC

FAN

REGULATOR

POWER

+5V+15V,-15V

DISTRIBUTION

TRANS

Ps1

- L1c
——1

DIODE

BOARD

AC LO

—4 DC LO

Ps3

THERMOSTAT

a——T

———

+15V

|
—

-15v

—1

9I-61

—TRANS

+5v

REGULATOR

| J2
I“_——-”—

5V(1)

—— GND (1)

o o

| N

—— +5v (2)

GND (2)

[o4]
| 45

BACKPLANE I

LINE SET

LOGIC

RELAY

K1
15v
OR
230V
47-63Hz
POWER

FAN

Ground

—

et ——

a—r—

O PANEL LOCK

;ro an;ec"ors

Power
or

{abine

Controller

-—e

{‘_[

POWER

I“

CONSOLE POWER SWITCH

OFF

11-1893

Figure 19-9

Power System Functional Block Diagram

U5V LINE SET

PHASE

0" o i

GROUND

NEUTRAL

Js |H1-P1

ol o
1]

10A

A
I

[

;

Tea o

PS1

;

313

oo GND (D

92 |

oloe

2 %

-~1-e

212

- 0CLO

2 2

BOARD

1]-

POWER DISTRIBUTION

(89097280, lhae

Pl
_—_}—{’

——

BACK PLANE

e
e —

;

2
H1-91|

4
oLTC

313

* -

L >
518

*1—»

- .2

212

(

L »-

O +15V

“T*
1|7

0 +5V (1)

6|8

THERMOSTAT | ¢ | ®

0 AC LO

olo

—15v

ols]

[]

T8t

1
230V LINESET

5T~

6 ]

d
—

(5409498)

)

‘ %

T2-P1|

.
!

* |

GND (2)

+5V(2)

+5v

&—1-® | GND

(H744 +5V)

3f3

PS2

s
L

oo | GN

TO CONSOLE

ouTPUT

POWER DISTRIBUTION BOARD WIRING

5§15

1o | +5v
POWER

SUPPLY
FAN

HI- U6

J5l

HI1-J5

J4 |

T2-41 H2-P2

H1-42

H2-P3

3103

*~{—o

313

HI-J4
1

H2-Ps

b
H2P5 —

ugflc
N

NOTES:

3
— | To RACK MOUNTED

Hi-43 | POWER CONTROLLER

616

o—}-o

pAciNeUT

M\
7

9 _J' |
3

SIGNAL
I

DC LO

LTC

+15v

———]z r—lg |—2
.

-15v

+5v{1)
+5v(2)

GND(
1}

L/
J1-us

GND (2)

LpOWU®D sl-m[

CONN
J-J5
Ji-J5
Ji-d5

Ji-Js
J1-J5
Jiadge
J3-J5

J1-J5

H1 indicates power

supply harness (E-1A-7009207-0-0}

H2 indicates power distribution board

H2-

P6)

harness (E -1A-7009208-0-0)

H2 -P7 [:

‘2
LOGIC
FAN

TO CONSOLE
SWITCH

11-2021

Figure 19-10

Power System

Interconnection Diagram

19-17

o—————

115V Line Set

115V
47-63Hz
Power

1 T3 5
g

l Neutral

;I-\
-

Llz]

l Phusej(% _ 1 |
! Ground

AAA

[ XN
[B

.._'

_E_g

)
4

— I
J5

2
Note:
For simplicity,intermediate connections involving TB% and K1 are not

shown
.
rogaen

Figure 19-11

Power Applications Using 115 V Line Set

1 %

—

47-63Hz

Power |

| prasesa. (1] |
I

T3 8

Ground

L
X | 15
2

| Neutrat
I

=< | 31
T
la

|
1

211

*®

Llsl

230V Line Set

230v

_E_g

L — —

Note:

Figure 19-12

TB1 and

K1 are not

shown.

Power Application Using 230 V Line Set

19-18

For simplicity,intermediate connections involving

GND(2)

+5v(2)

-i5Vv

+5v(1)

6ND(2)
[

ACLO
B

”

frws

'wa

‘W3

—

+15V

DCLO

GND(1)

fW2

InREnlin

LTC

)

|-o

\_/

/
J5

11-1889

Figure 19-13

Power Distribtuion Board Circuit Schematic

Table 19-2
Power Distribution Board Signals

Source

Signal

Destination

H744

5V Q)

J3,J4, and J5 pin 9

5 V Regulator

GND (2)

J1-J5 pin 4**

DC LO

J1--J5 pin
1*

5409728

J1-J5
pin 2

LTC

J1-J5 pin 7

+15V

J1-J5 pin 8

< 5V (1)

dc Regulator
»

Notes:

ACLO

31 and J2 pin 9

-15V

J1-J5 pin 3

GND (1)

J1-J5 pin 4**

*Connected to each Mate-N-Lok via a jumper.

**Electrically connected on the board. Pins 5 and 6 on J1-JS5 are spares.

CAUTION
Output +5 V (1) is generated by the 5409728 regulator and is
available

oo,

generated

connectors

the

H744

and J2.

Output

+5V (2) is

Regulator and is available

connectors J3—J5. These supplies are separate and should not
be connected together.
19-19

The current ratings for the power supply outputs are shown below. The ratings listed are maximum; that is, for a
particular output, the sum of the loads on the connectors used must not exceed the specified value.
5409728 dc regulator
1S

+5 V (1) on connectors ¥1 and J2 is 20 A total
+15V on connectors J1-J5is 1 A total

-15 V on connectors J1-J5 is 8 A total
H744 Regulator

+5 V (2) on connectors J3, J4, and J5 is 20 A total

Parallel connections of +5 V (2) and GND (2), using Faston tabs on the power distribution board, are provided to
connect these outputs to the computer console printed circuit board.

The power distribution board contains a DC LO jumper for each connector (J1-J5). Only one DC LO connection is
required per mounting box. In the basic computer, jumper W1 is installed to bring the DC LO signal to the
backplane because the processor power harness connects the backplane to the power distribution board at connector
J1.

A jumper for each connector is provided because it is possible to mount a backplane in any position and connect it
to any power distribution board connector.

The requirement for only one installed DC LO jumper per box is emphasized in the following special case.
Assume that a PDP-11/05 mounting box is to be used as an expander box with a DB11-A Bus Repeater installed
along with other options. Unlike previous expansion boxes, the PDP-11/05 box allows the DB11-A to be installed in
any position. When connected to the appropriate distribution board connector, the associated DC LO jumper is
installed. All other DC LO jumpers must be open to prevent latching up of the DC LO circuit by looping through the
power harness if more than one jumper is installed.

Options for the basic computer include a pre-wired backplane and specific power harness to connect the backplane
to the power distribution board (Table 19-3).

Table 19-3

Option Power Harnesses

Option

Power Harness

MF11-L

70-09206

DDI11-B

70-09099

DDi1-A

70-09205*

*Not shipped with computer.
Harness must be ordered

separately to install customer’s
DDI11-A.

19-20

—e

SERIES
SERIES

. +15V

VOLTAGE
DETECTION
POSITIVE
RECTIFIER|
FILTER
AND
FUSE

__l(+) RAW
e

OUTPUT

OVER CURRENT
DETECTION

OVER CURRENT

DETECTION

VOLTAGE

[*—

DETECTION

SWITCHING
SwiTCHING

+5V OUTPUT

1261

OVER VOLTAGE
CROW BAR

CENTER TAPPED
AC FROM
TRANSFORMER
SECONDARY

POSITIVE

SCALING

ResisTors [ "] ac/oc Lo [N FIER
LIMITING

AUXILLIARY

IMING

RECTIFIER

RESISTORS
REFERENCE

DIODE

ACLO

OPEN

COLLECTOR

DCLO

OPEN COLLECTOR | o ac 10 o

_| DETECTION ] "CURRENT sink

DETECTION

CURRENT SINK

RESISTOR-ZENER

NEGATIVE

AND FUSE

CLIPPER

RECTIFIER, FILTER

|[=DPC LO L

(=) RAW DC ] swITCHING REGULATOR

> -15V OUTPUT

VOLTAGE
DETECTION

OVER VOLTAGE]
CROW BAR
OVER CURRENT]
DETECTION
1-1046

Figure 19-14

DC Regulator Block Diagram

The DD11-A and DD11-B are pre-wired backplanes used to mount up to four small peripheral interfaces (equivalent

to four quad boards). The DD11-B is a later version of the DD11-A that uses Faston tabs on the wire-wrap pin side
to connect with the power hamess. The DD11-A uses a power hamess that contains a cable connector module which
plugs into the connector side of the backplane. The DD11-A is not shipped with the computer; rather, the later
DD11-B version is used. If the customer has a DD11-A and wants to install it in the computer, he must order power
hamess 70-09205.

The KD11-B Processor requires 8,0 A at +5V and 1 A at -15 V. The power requirements for the MF11-L Memory
are listed below.

MF11-L
Capacity

19.4.4

Current
at+s5 v

Current
at-15v

34A

6.0 A

16K

49 A

65A

24K

64 A

70 A

DC Regulator (PS1)

19.4.4.1

Functional Operation — A block diagram of the dc regulator is shown in Figure 19-14. The center tapped

output of the power transformer is applied to positive and negative rectifier and filter circuits. The rectifier circuits
produce +39 V and -29 V nominal raw dc voltages, which are unregulated but well filtered by the input storage
capacitors.

The +39 V is used by an efficient switching regulator circuit to produce the +5 V output. Provisions for overcurrent
detection are incorporated in the regulator circuit so that excess current is limited when there is a malfunction in the
load. The +5 V output is also protected against overvoltage by a crowbar circuit which limits the output to an

absolute maximum of 7 V; at approximately 6 V, the crowbar circuit blows fuse F1 in the output circuit of the
rectifier.

The +15 V output is produced by a series regulator circuit. It has no overvoltage protection circuit. Fuse F1 is used
for protection in case of
a malfunction in the +15 V regulator.
The -39 V is used by the - 15 V circuit, which is similar in operation to the +5V regulator circuit. The -15V

crowbar circuit limits the output to an absolute maximum of -22 V. At approximately -19 V, the crowbar circuit
blows fuse F2 in the output circuit of the rectifier.

The real-time clock synchronizing signal (LTC L) is generated by a simple Zener clipper that is fed from the
transformer secondary.

The BUS AC LO L and BUS DC LO L signals are used to warn the Unibus of imminent power failure. Circuits detect
the transformer secondary voltage and generate two timed TTL-compatible open-collector signals that are used for
power fail functions by devices on the Unibus.
19.4.4.2

Generation of Raw DC Voltages — As stated in the previous paragraph, the centertapped transformer

secondary voltage is rectified and filtered prior to being fed to the three dc regulators.
The circuitry is shown in Figure 19-15. Bridge rectifier D14 is mounted on the heat sink and input capacitors C1 and

C2 are mounted on the bottom of the regulator module. These capacitors filter the input dc and are large enough to
provide power storage for at least 25 ms when the input power is shut off or fails.

19-22

R45

J1-3

—
28VAC
47-63Hz|

FROM

_J1-1

TRANSFORMER

SECONDARY

4.7K

NSS-351

172w

F1,15A

D14

o TO+5V

REGULATOR CIRCUIT

J1-2

c2
24K pF

50V

c1
24KpF_1
50V~

TO AC LO

AAR&GiTs®

R4 4.7K

Fz.104

TO-15V REGULATOR
CIRCUIT

-7
7

Figure 19-15

Rectifier and LTC Circuits

Two fuses are used to protect the regulator and load during faults. A 15 A fuse protects both the +5 Vand +15V
outputs and a 5 A fuse protects the -15 V output. Normally, the fuses do not blow when a regulator output is
shorted because the three outputs are electrically overcurrent protected. However, the appropriate fuse does blow in
case of +5 V or -15 V overvoltage crowbar or in case of failure in one of the overcurrent circuits.

The resistor across each fuse provides a slow (100 — 150 seconds) discharge of C1 or C2 when the power is turned
off after a fuse has blown. The capacitors are placed ahead of the fuse to limit the energy in any fault and thus
better protect the outputs.

19.4.43

LTC L Circuit — The LTC L real-time clock synchronizing signal (Figure 19-15) is generated by a Zener

clipper circuit. The output waveform is a clipped sine wave at line frequency. For the positive half of the output sine
wave, D13 clips at about +3.9 V and for the negative half D13 clips at its forward voltage of -0.7 V.
19.4.4.4

BUS AC LO L and BUS DC LO L Circuits — The circuitry shown in Figure 19-16 is used to generate the

timed Unibus power status signals that are used for power fail function.

The transformer secondary voltage is rectified by D1 and D2 and filtered by C9 and R1, R14. Circuit parameters are
chosen so that the voltage across C9 rises slower than the three regulated output voltages on powerup and decays
faster than the three regulated output voltages on powerdown.
Two differential amplifier circuits are used to detect power status: Q17, Q18 generates BUS DC LO L; and Q15,
Q16 generates BUS AC LO L. Both differential amplifiers share a common reference Zener diode D3, which is fed
approximately 1 mA by R3.
As C9 charges subsequent to powerup, first Q17, Q18, and then Q15, Q16 change state; the reverse is true during
powerdown. When C9 starts to charge, Q17 and Q16 are on and Q15 and Q18 are not conducting. As C9 charges
further, Q18 starts to conduct into R7 and raises the voltage on the cathode of D3. This acts as positive feedback

and snaps Q17 off and Q18 on more solidly. A few milliseconds later, the voltage across C9 has risen sufficiently for
the same process to take place in differential amplifier Q15, Q16. The status of each differential amplifier is
followed by the germanium transistor open-collector output stages Q19, Q20 for BUS DC LO L, and Q13, Q14 for
BUS AC LO L. These stages clamp the Unibus at about +0.4 V until the differential amplifier circuits sequentially

signal them across R11 and R12 that power is up. The outputs then rise to about +5 V as dictated by the Unibus
loading and pull-up termination resistors.
19-23

The sequence is as follows:

powerup ~>then BUSDCLOL=0—>then BUSACLOL=0
0 =high (+3 V)
powerdown =>then BUSACLOL=1—>then BUSDCLOL =1
1 =low (+0.4 V)

During a power-down sequence, after BUS AC LO L goes low, there is sufficient storage in capacitors C1 and C2 to
maintain output voltage long enough to permit the power fail circuit to operate. The open collector stages are

designed to clamp the Unibus to 0.4 V maximum, even when there is no ac input to the regulator. They are
inherently biased on by R11 and R12 until the differential amplifiers signal that power is OK.

IN4004
-

bl
28VAC,

’

47-63Hz

FROM

TRANSFORMER SECONDARY

20pF

R14

INGOO4

SR2
b

* 10K 1%

SR3
3

210K 1%

BUS

> 10K 1%

114V
.

BUS

!
Qi7

XA55

V2!

XAS5

J2°6 pcloL

[

OUTPUT

3RS
1§

YRy

SRIO

$10K

SR6
3

)
+10vV

OUTPUT

> 10K 1%

—_—

Ac LO L

SRS
b3

S 75K

Q13

2N1309

Q14

2N1309

N?308

LEbd

—AAA

Q13

2N1308

Figure 19-16

"n-0176

BUS AC LO and BUS DC LO Circuits

19.4.4.5 +15 V Regulator Circuit — The +15 V regulator shown in Figure 19-17 is a simple series regulator. The pass
transistor Q1 is a high-gain power Darlington type and is mounted on the heat sink. Base drive current is supplied to
Q1 via R38. Q3 limits the value of this current to the required value by shunting it away from the Q1 base. Voltage
detector amplifier Q4 biases on Q3 and thus limits current in Q1. The +15V output voltage is sampled on the

viewing chain R34, R35, R36 and compared to the voltage across reference Zener D8, which is fed by R37. If the
output tries to increase from the regulated value, the emitter of Q4 is made more negative (relatively) than its base
and conduction through Q4 increases. This increases the conduction through Q3 and causes Q1 to shut down
sufficiently to restore the output voltage to the regulated value. Ambient temperature compensation of the voltage

detector is essentially flat since D8 has a +2 mV/° C temperature coefficient and the base emitter junction of Q4 has
a-2mV/°C temperature coefficient.
R35 is the +15 V voltage adjustment potentiometer and C18 is a high frequency stabilization capacitor. Q2 is the

overload detector; when the output current reaches 1.5 A nominal, the voltage across R33 is sufficient to cause Q2
to conduct which removes base drive from Q1 and causes the regulator to current limit.

19-24

—

TO PWR OK CIRCUIT
{NOT USED IN PDP-11/05}
R33

0.29

+39V FROM RECTIFIER

/’\MJZSOO

R32
66

J2-5

R34
3383
1%

+15V, OUTPUT

o8
&K IN7S3A

+ %s'

6.2V

R37 1K

R35
100

R36

"1 cw

464

SR3B
.

10K

c18
680pF

AT
bl

L——“P

X A0S
$1-0968

Figure 19-17

+15 V Regulator Circuit

Lt~

19.4.4.6

+5 V Regulator Circuit — The +5 V regulator is similar to the +15 V regulator in that the sampled output

voltage is compared to the voltage across a reference Zener by a voltage detector transistor, which, in turn, controls
the drivers for the main pass transistor. An overcurrent circuit is used also. The +5 V regulator circuit is shown in
Figure 19-18.

R41

0.025

—

Soh

354

]

D10,20A

OUTPUT

6000
IFF.IOV

FAST
RECOVERY

R39 |
51
7

J2-3 L.y

100uH

2N5302

W, 3%

xas5

y DUl

IN5624

D12

& INTS2A,
5.6V

RS2

gRS4

—

+39V FROM

RECTIFIER

l c3

011] A

0.033,F

xass_go

I 1uF

Lras

6.8uF

Ra3

10K

c3zax3s¥k

gRrav

$hy

jesx

o 0%,
1,09
10V,10%

330

6.8 uF 1<

35v

Rs3s
1008

Rie | A%

cw t

a®0
XAO5

$RS0

]
|

2RA4

T (oF

3% PT.C. |

2330

]

Figure 19-18

Lcs

0.22uF

50V

35V

+5 V Regulator Circuit

19-25

The viewing chain consists of R49, R50, and R51. The reference Zener is D9, which is fed by R44. Q10 is the
detector amplifier. The pass transistor Q6 and first stage driver Q7 are mounted on the heat sink. The predriver Q8 is
turned on by R46. The current is diverted from the base of Q8 by off-driver Q9, which is controlled by Q10. The
+15 V and the +5 V regulators are similar in operation; i.e., a tendency for the output voltage to rise results in more
Ki

conduction through Q10 and resultant limiting of conduction through Q6.
Here the similarity ends. The +5 V regulator operates in the switching mode for increased efficiency. To get the
regulator to switch, positive feedback is applied to the voltage detector input via R47. Thus, the whole regulator acts
as a power Schmitt trigger and is either completely turned on or turned off, depending on whether the cutput
voltage is too high or too low. When Q6 is on, it supplies current through filter choke L1 to the output smoothing
capacitor C7 and the load. When Q6 is off, the L1 current decays through commutating diode D10, which becomes

forward biased by the back emf of L1. The waveform across D10 is a 30 V nominal rectangular pulse train. The
filtered output across C7 is thus +5 Vdc with

about

a 200 mV peak-to-peak

10 kHz nominal sawtooth of

superimposed ripple. At the crest of the ripple, Q6 turns off and at the valley Q6 turns on. This switching mode of

operation limits the dissipation in the circuit to the saturated forward losses of Q6 and D10 and the switching losses
of Q6. The resultant high efficiency allows the use of a small heat sink and relatively few power transistors.
R50 is the voltage adjustment potentiometer. RS1 is a positive temperature coefficient wire-wound resistor that
compensates for the fact that the Q10 base-emitter junction and the reference diode D9 both have negative voltage
temperature coefficients. Q5 current, limited by R39 and R40, detects the overcurrent signal generated across
resistor R41, which is in series with the Q6 collector.
Output fault current is limited to a safe value because conduction of Q5 makes the reference voltage across D9
decrease to zero. This causes Q10 to conduct and shuts down the regulator. C5 is an averaging capacitor, which is
necessary in the circuit because the current through R41 is pulsating.
High frequency bypass capacitors are used on the input and output of the regulator (C3 and C6, respectively) and C4
is used to slow down the turn-on of Q6 to allow D10 to recover from the on state without a large reverse current
spike.

If a malfunction causes the output voltage to increase beyond about 6 V, Zener diode D2 conducts and fires
silicon-controlled rectifier Q11. This crowbars the output voltage to a low value through D11 and blows fuse Fi in
the rectifier circuit through R52.

19.44.7

-15 V Regulator Circuit — The -15 V regulator circuit is shown in Figure 19-19. It is essentially the

complement of the +5 V regulator circuit and differs only in the following minor details.

The crowbar device is a Triac (Q27) instead of an SCR. No temperature compensating resistor is required
because Q26 and D4 track each other, as in the +15 V regulator.

The detailed interconnection of the drivers and the circuit values are different.

The-15 V output voltage is adjusted by potentiometer R26.

19.4.5.1

+5 V Regulator (PS2)

Functional Operation — A functional block diagram of the +5 V regulator is shown in Figure 19-20. The

28 Vac from the secondary of transformer T2 is full wave rectified and filtered. This raw dc voltage (approximately

39 V) is used by a switching regulator circuit to produce the +5 V output. An overcurrent detection circuit is
incorporated in the regulator circuit to limit excess current when there is a fault in the load. The +5 V output is also
protected against overvoltage by a crowbar circuit that limits the voltage to +7 V. Before the output reaches +7 V,
the crowbar circuit blows the fuse in the rectifier output. A circuit schematic of the +5 V regulator is shown in

Figure 19-21 and is referenced in the subsequent paragraphs.

19-26

19.4.5

FROM—e3t

R29

RECTIFIER

ir2s

R27

1/2W

)

lcie

Q26

T22uf

35V
.

XA55

RS8

TSI

OUTPUT

0.22uF
50V

ci” R26

e300,

68K

3%%5

J2-2 , GROUND
Lcts

100

Tasv TM

T we

sR24

Loy
IN753A

”

2’

D5, 20A

523

& FAST

RECOVERY

»—Q fi———o
G3uF
100V

Q27 yif 3

MAcn-:s!iz

R30

JL
LAY

c12

2.2uF
35V

R22

D7, 18V

‘K \N52488

Q21

XAQ5

ins62a¥

R20.

7 a0

~qe2

0,06

2N5302

100uH

10A

3% WW

oUTPUT

J2-9 , —15v

11-0970

Figure 19-19 -15 V Regulator Circuit

INPUT

RECTIFIER

SWITCHING

AND FUSE

TRANSISTOR

SoTPUT

g?l?é‘;

PASS

FILTER

—

OVER
CURRENT
SENSING

PRECISION
VOLTAGE

REGULATOR

OVER
VOLTAGE
SENSING

DRIVERS

|e—

OVER

VOLTAGE
CROWBAR

11-1892

Figure 19-20 +5 V Regulator (PS2) Functional Block Diagram

19-27

154

.02,5W

2N5302

2,5,

{45V

fo |7 [ 1
|
T

7—t
]

Rmer $RI30K
sov.

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5v

| R2

[

R123

1W,10 %

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R21
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MPSAOS5

p
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1N474473

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R25 ¢

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l12

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56PF TN

R26
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ADAZR649P2
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s

1/8W,1%

2N6028

318

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1.5K
=

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£05

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15V

R22¢

5.1

SKuF | 6Kuf
10V

10V

F-I
0664

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R17

750

1/8W, 1%

2R14

9200

Ve
Et

R18

DECT23

$511

11/8W,1%

R19
|

7.5k
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I8W,
1%
1/8W,1

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cCoMP
cs

56PF TS

::RIS

210K

=
-

SENSE

11-1894

Figure 19-21

+5 V Regulator (PS2) Circuit Schematic

19.4.5.2

Generation of Raw DC Voltage — The 28 Vac from transformer T2 is applied to full wave rectifier D1 via

pins 6 and 7 of connector J1. The rectifier output is approximately +39 V and is filtered by capacitor C1. Resistor
R1 is a bleeder resistor and dissipates the charge on C1 during shutdown. The 15 A fuse (F1) protects the regulator
and load during faults. Normally, the fuse does not blow when the regulator output is shorted because the output is
protected against overcurrent operation. The fuse does blow if the crowbar circuit fires or in case of failure in the
overcurrent protection circuit.

19.4.5.3

Regulator Circuit — The regulated +5 V is sampled by resistors R19 and R7. The magnitude of this voltage

is compared to a precision 5 V reference voltage produced by voltage regulator E1 and voltage divider R17, R14, and
R18. This regulator responds to #0.05 V differences between the sensed output and the reference.

El is an integrated circuit in a 14-pin dual in-line package. A simplified equivalent circuit and package configuration
are shown in Figure 19-22.

FREQUENCY

COMPENSATION

]

INVERTING

INPUT
VREF O

SERIES PASS
TRANSISTOR

v ouT

NONINVERTING

}/c

INPUT

A - Voltage Reference Amplifier
B-Error Amplifier

CURRENT CURRENT

C -Current Limiter

LIMIT

Simplified

SENSE

Schematic

[ 13 ] FREQ cOMP

CURR LIM | 2

CURR SENSE | 3

[12] v+

INV OUTPUT | 4

(11] ve
Vout

NON-INV OUTPUT | 5

vret | 6

[9| vz

| 8 ] ne

7
Pin Designations

1-1895

Figure 19-22 Voltage Regulator (E1) Equivalent Circuit and Package Configuration

19-29

The +5 V output passes through transistor Q2 to the output filter (C8, C9, and L1) and to the load. Q2 is called the
pass transistor and is mounted on the heat sink. Transistor Q2 is operated in the switched mode; therefore, it is

either on or off. It is controlled by drivers Q5, Q4, and Q3 that are controlled by voltage regulator E1. A simplified
+5 V regulator circuit and associated waveforms are shown in Figure 19-23 to illustrate the operation of a switching

regulator.

Q2
o]
———————

POWER
ON

43V~ p————

——

—

== Q2 ON

11-0098

+39Vv

4.95v-5.05Vv

DRIVERS

1 €9 3LOAD

o—|—o

%05

11-0097

Figure 19-23

Simplified 5 V Switching Regulator Schematic and Waveforms

When power is applied, the drivers tum on Q2 and the output voltage starts to rise toward +39 V. Because of

inductor L1 in the circuit, the voltage rise is relatively slow. When the output voltage reaches 5.05 V, E1 signals the
drivers to cut off Q2. As the field associated with L1 starts to collapse, L1 current flows through the load to ground
and retumns to the other side of L1 through commutating diode DS, which is forward biased by the L1 back emf.

The output voltage decays, and when it reaches 4.95 V, El signals the drivers to turn on Q2 and current is supplied
through L1 to C8 and C9 and the load. The output voltage rises and when it reaches 5.05 V, E1 again signals the

19-30

drivers to cut off Q2. The circuit oscillates in this manner and generates a 39 V p-p rectangular pulse train across
diode DS. The regulator circuit acts like a power Schmitt trigger and is either on or off depending on whether the
output voltage is too low or too high. The filtered output across C8 and C9 is thus +5 V with about a 100 mV p-p
10 kHz nominal sawtooth of superimposed ripple. The output filter is an averaging device so the rectangular pulse
£

train appears as an average voltage (+5 V nominal) at the output terminal.

If the load increases, the output voltage decays faster and Q2 turns on sooner so that the waveform frequency (duty
cycle) increases. Conversely, if the load decreases, the waveform frequency (duty cycle) decreases.
The driving chain for Q2 consists of first stage driver Q3, predriver Q4, and off driver QS, which is controlled by E1.
Off driver Q5 diverts current from the base of Q4 and thus controls it. QS, R2, and Zener diode D2 are used to
generate +15 V for the operation of E1 from the +39 V raw input.

19.4.5.4 Overcurrent Protection Circuit — The regulator is protected from damage by high current due to a fault
(short circuit) in the load. The current is limited to about 30 A by the overcurrent protection circuit that consists of
Qt, R3 through R6, R25, R27, Q7, and C4.

The current drawn by the load through pass transistor Q2 is sensed by monitoring the voltage drop across 0.02 £
resistor R4 that is in series with the +39 V raw voltage. If the current exceeds 30 A, the drop across R4 increases and
forward biases Q1 and it turns on. Capacitor C4 charges and overcomes the bias on Q7 which turns it on. This action
turns on E! which, in turmn, cuts off pass transistor Q2. The forward bias on QI is reduced and it turns off. Capacitor
C4 discharges and holds El off for a period of time during which the current drops nearly to zero. When C4
discharges, E1 tums on to re-establish the output voltage. If the fault still exists, the overcurrent circuit tums off Q2
again. As long as the fault exists, the regulator oscillates in this mode and limits output current to approximately
30 A.

19.4.5.5

Overvoltage Crowbar Circuit — The +5 V is used to power digital logic devices that must be protected

against voltage in excess of 7.0 V. This protection is provided by the overvoltage crowbar circuit that consists of
silicon controlled rectifier D7, Zener diode D3, diode D8, Q6, R22, R23, and C7.

During normal operation, the trigger input to SCR D7 is at ground potential because the voltage across Zener diode
is less than the 5.1 V required to cause it to conduct. If a malfunction occurs that increases the output voltage above
6.0V, Zener D3 turns on which forward biases Q6. When Q6 conducts, resistor R23 in the SCR gate circuit draws
current and tumns on D7. The +5 V output is short circuited to ground. Capacitor C7 bypasses R23 to ground so that
line transients of short duration that might cause D3 and D4 to conduct do not fire the crowbar.
19.5

POWER SUPPLY MAINTENANCE

19.5.1

Introduction

Power supply maintenance information includes the following items:
a.

Checking and adjusting voltages

Removing power supply

¢.

Troubleshooting procedures

19.5.2

Checking and Adjusting Voltages

The power supply has four adjustable output voltages. Three voltages [+5 V (1), +15V, and =15 V] are associated
with the 5409728 DC Regulator and one {+5 V (2)] is associated with the H744 +5 V Regulator.

19-31

The computer must be extended more than half way out of the cabinet to provide access to all four adjustments.
The three dc regulator adjustments are located in a vertical line midway on the right side of the computer; from top
to bottom they are +15V, +5V and -15 V. The H744 Regulator adjustment is located on the bottom of the
computer approximately 15 in. from the front and 1-1/2 in. from the right side. In each case, access is provided
through holes in the computer mounting box and power supply chassis (Figure 19-24).

ADJUSTING TOOL

+15V ADJUSTMENT

+5V ADJUSTMENT

-15V ADJUSTMENT

6712-2

Figure 19-24

Power Supply Adjustments

All adjustments are controlled by potentiometers with slotted-head shafts that are conveniently rotated using a small
blade type screw-driver. Clockwise rotation increases the voltage in each case. The output voltages should be checked
and adjusted as close to nominal as possible. The nominal values and allowable tolerances are shown below.
5409728 Regulator Output Voltages

Nominal Value and Tolerance
5.0V+5%

Equivalent Range
475Vto525V

150 V+5%

1425V to 15.75V

~15.0Vixi5%

1425V to-15.75V

H744 Regulator Output Voltage

Nominal Value and Tolerance
50Vt5%

Equivalent Range
475V t05.25V

When adjusting the voltages, use a digital voltmeter and measure the output under load at the connectors (Faston
tabs) on the pin side of the computer backplanes. These connectors are reached conveniently by extending the

computer from the cabinet, locking it in the 90° front up position and removing the bottom cover.
Observe the following cautions when adjusting the output voltages.
1.

Do not adjust the voltages beyond the 105% rating to avoid activating the overvoltage protection
(crowbar) circuit. In the case of the H744 Regulator, the +5 V output is drastically reduced when the
crowbar fires but the fuse does not blow. In the case of the 5409728 Regulator, fuse F1 (15 A) blows if
the +5 V output is adjusted too high; and fuse F2 (10 A) blows if the -15 V output is adjusted too high.
These crowbar circuits are designed to blow the fuses when activated. The +15V output has no
overvoltage protection circuit but it uses fuse F1 for protection in case of a malfunction in the +15V
supply.

The two +5 V outputs, +5 V(1) from the 5409728 Regulator and +5 V(2) from the H744 Regulator,
must not be shorted together. Qutput +5 V(1) is available on power distribution board connectors J1
and J2; and output +5 V(2) is available on connectors J3, J4, and J5 of this board.
19.5.3

Power Supply Removal

The following procedure must be used to prevent damage to the power supply during removal from the mounting
box:

Turm off power.

Remove the two screws that hold the line set to the rear of the mounting box, withdraw the line set

slowly,and disconnect line set connector J5 from power supply harness connector H1-P1 (Figure 19-25).

Remove the six screws on the right side of the mounting box that hold the power supply chassis to the
mounting box (Figure 19-26). Disconnect the console cable connector from the Berg connector on the

M7260 module and move the cable away from the power supply cover. Remove the four screws that
secure the cover and remove it from the power supply.

Disconnect the following connectors that are accessible at the rear of the power supply (Figure 19-27).
a.

Power Supply harness connector H1-J2 from power distribution harness connector H2-P3.

Power distribution harness connector H2-P2 from transformer connector T2-J1 (2 red and 2 black
wires).
CAUTION

The dc regulator output connector PS1-J2 is still connected
but it is not accessible.

19-33

Lift the P power supply
in the mounting box
pply chassis slowly y upward until it is free of the compartment
P
(Figure 19-28). Rest the bottom of the power supply chassis on the top of the mounting box and remove

power distribution harness connector H2-P1 from dc regulator output connector PS1-J2 (Figure 19-29).
6.

Place the power supply on a bench. Be careful when lifting and carrying the power supply because its
center ofgravity is near the front end.

POWER SUPPLY

HARNESS

CONNECTOR H1-P1

LINE SET CONNECTOR J5

67121

Figure 19-25

Disconnecting Line Set From Power Supply

19-34

POWER SUPPLY

CONSOLE

POWER SUPPLY

MOUNTING SCREWS(6)

CABLE

COVER

6712-5

POWER DISTRIBUTION
HARNESS

CONNECTOR H2-P3

Figure 19-26

POWER SUPPLY HARNESS
CONNECTOR H1-J2

POWER DISTRIBUTION

g TRANSFORMER

CONNECTOR H2-P2

(2 RED AND 2 BLACK

HARNESS

CONNECTOR T2-J1
WIRES)

Removing Power Supply Mounting Screws

67126

Figure 19-27

Removing Power Distribution Harness

Connectors H2—P2 and H2—-P3

19-35

DC REGULATOR OUTPUT

POWER DISTRIBUTION

CONNECTOR PS1-J2

HARNESS CONNECTOR H2-P1

6712-7

Figure 19-28

Lifting Power Supply

From Mounting Box

6712-8

Figure 19-29

Disconnecting DC

Regulator Output Connector

19-36

19.5.4
19.5.4.1

Troubleshooting Procedures
Introduction — Most of the troubleshooting information presented relates to the components 5409728

s ]

Regulator and H744 Regulator.

Troubleshooting the other power system components such as the line set, relay, transformers, connectors, etc., can
be accomplished by performing an electrical continuity check using the power system interconnection diagram

(Figure 19-10).

19.5.4.2

Troubleshooting Hints
WARNING

Dangerous voltages (115 or 230 Vac) are present in the power

system. Be careful when servicing these circuits.

Because of the physical configuration of the power supply, very little troubleshooting can be performed with the
power supply installed. Voltages can be checked under load on the pin side of the computer backplane. For some
malfunctions, the problem can be isolated to the load or power supply by disconnecting the backplane cable and
checking the power supply outputs at the power distribution board connectors. Refer to the power distribution
board circuit schematic (Figure 19-13) and list of signals (Table 19.2).
The most likely source of a power supply malfunction is the 5409728 Regulator or the H744 Regulator. A quick
remedy for a malfunction in either of these regulators is to replace the complete unit. The replacement regulator
may need adjustment to compensate for the load. If the new regulator is initially adjusted too high, it may activate
the crowbar circuit. In the case of the H744 Regulator, no output is generated. In the case of the 5409728

Regulator, no output is generated and the +5 V fuse or -15 V fuse blows. If this should happen, remove power and
rotate the appropriate voltage adjustment fully counterclockwise. Replace the fuse, if required, and apply power.
Adjust the output to the recommended value per Paragraph 3.5.2.
NOTE
When replacing or swapping the 5409728 DC Regulator (PS1),
etch revision D or later must be used. Earlier etch revisions,
such as revision C which is used in the 5-1/4 in. PDP-11/05,

11/10 Computer, must not be installed because of insufficient
current capacity.

19.5.4.3 Troubleshooting the 5409728 Regulator — Table 194 is a troubleshooting chart for the 5409728 Regulator.
It should be used with Figures 19-15 through 19-19 or regulator schematic drawing D-CS-5409728-0-1 in the print set.
A visual check is a valuable aid in locating the cause of a malfunction. Check for loose connections, burned resistors,
burned printed circuit board etch, cracked transistors or leaky capacitors.

As an additional aid to troubleshooting the 5409728 Regulator, waveform photos are provided for the +5 V and
=15V outputs. These waveforms were taken on a Tektronix Model 453 Oscilloscope. All waveforms are with respect

to power common (J2 pin 2).

19-37

Table 19-4

5409728 Regulator Troubleshooting Chart

No +5 V and +15 V output

+5 V Output Too Low

F1 open

[

Cause

Problem

D14 or transformer T1 open
+5 V adjusted too high*

Q5, D9, Q10, Q9, Q11, D12, or D10 shorted
CS or C7 shorted
R49, R50, R46, or R44 open

Q6, Q7, Q8, or D11 shorted

Q9, Q10, or D9 open*
RS1 or R50 open

+15 V Output Too High

Q1 shorted
D8 open

R35 or R36 open

No - 15 V Output

=15 V Output Too Low

F2 open
D14 or transformer T1 open

-15 V adjusted too high*

Q25, D4, Q26, Q21, Q27, D7, or DS shorted

C14 or C12 shorted

R22, R26, R25, or R29 open

Q22, Q23, Q24, or D6 shorted
Q25, Q26, or D4 open

BUS AC LO L Will Not Go High

Q13, Q14, or Q15 shorted
Q16 or D3 open

R7, R3, R6, or R8 open
C9 shorted

BUS AC LO L Will Not Go Low
and/or acts erratically on
poweron/poweroff

Q13,Qi4, or Q16 open
Q15 or D3 shorted
R12, R13, R7, or R10 open

BUS DC LO L Will Not Go High

Q19, Q20, or Q18 shorted
Q17 or D3 open

-»

R7, R2, or R6 open

C9 shorted

BUS DC LO L Will Not Go Low

Q19, Q20, or Q17 open

Q18 or D3 open
R7, R3, or R6 open
C9 shorted

19-38

Table 19-4 (Cont)
5409728 Regulator Troubleshooting Chart

Problem

Cause

BUS DC LO L Will Not Go Low

Q19, Q20, or Q17 open

and/or acts erratically on

Q18 or D3 shorted

poweron/poweroff

R9Y, R10, R11, or R8 open

No LTC L Signal

RS55 open
D13 shorted

LTC L Going Too High

D13 open

*These causes make the crowbar fire, which, in turn, blows the appropriate fuse.

Figure 19-30 shows six waveforms for the +5 V output taken at points A and B in the circuit (Figure 19-18). Point A
is the output of pass transistor Q6 and point B is the +5 V output (J2 pin 3). Waveforms a, b, and ¢ are taken at

point A and waveforms d, e, and f are taken at point B. Figure 19-31 shows six waveforms for the -15 V output
taken at points C and D in the circuit (Figure 19-19). Point C is the output of pass transistor Q22 and point D is the

-15 V output (J2 pin 9). Waveforms a, b, and c are taken at point C and waveforms d, e and f are taken at point D.
19.5.4.4

Troubleshooting the H744 Regulator — The design of the +5 V H744 Regulator is similar to the +5 V

portion of the 5409728 Regulator. In general, the same troubleshooting procedures and fault isolation techniques
apply to both regulators.
Some specific troubleshooting procedures are listed for the H744. Refer to Figure 19-21 which is the H744 circuit
schematic.

A regulator that provides no output, or low output, without causing fuse F1 to blow is probably
working into a short-circuited output. Check for a short circuit in the load or a component failure in the

crowbar circuit.
b.

A regulator that provides no output and has fuse F1 blown usually indicates a fault in the pass transistor
or its driver network. Proceed as follows:
1.

Check for scorching of the etched board in the area of Q3 and Q4. Check the associated
base-emitter bleeder resistors for damage.
Check pass transistor Q2, drive transistors Q3 and Q4, and level shifter Q5 with an ohmmeter. The
fault could be caused by continuous base drive to Q4.

The fault could be caused by an external short-circuit that holds precision voltage regulator El in
conduction. E1 pin 4 to ground should measure approximately 20K 2. E1 pin 5 to ground should
measure approximately 1.5K §2.

Check for shorts to ground at the fuse terminals and components mounted on the heat sink.

19-39

a) Point A, No load,

d) Point B, No load,

b) Point A, No load,
20 ps/div, and

e) Point B, No load,
20 ps/div, and

c) Point A, 20A load,
20 ps/div, and

f) Point B, 20A load,
ps/div, and

2 ms/div, and
50 mV/div.

2 ms /div, and
10V/div.

10V/div.

50 mV/div.

10V/div.

Figure 19-30

+5 V Regulator Circuit Waveforms

19-40

Point C, No load,

Point D, No load,

5 ms/div, and

b) Point C, No load,

e) Point D, No load,

50 ps/div, and

10V/div.

50 mV/div.

10V/div.

PointC, 5A load,

50 ps/div, and

10V/div.

Point D, 5A load,
50 us/div, and

50 mV/div.

Figure 19-31

-15 V Regulator Circuit Waveforms

19-41

APPENDIX A

INTEGRATED CIRCUIT DESCRIPTIONS

A.1

INTRODUCTION

The MSI and LSI integrated circuits (ICs) which are shown in the engineering drawings are discussed in the following

paragraphs. The descriptions include a pin location diagram, simplified logic diagram, and truth table. These
descriptions are intended as maintenance aids for troubleshooting to the IC level. Table A-1 lists the ICs by part
number, nane, and respective paragraph number.

Table A-1
Integrated Circuits

Manufacturer

DEC

Part Number

8266

19-09934

Name

2-Input, 4-Bit Digital

Para.

Multiplexer

7413

19-09989

Dual NAND Schmitt Triggers

7473

19-05587

Dual J-K Master-Slave

Flip-Flops

7474

19-05547

Dual D-Type, Edge-Triggered

A.S

Flip-Flops

7475

19-09050

4-Bit Bistable Latch

A.6

7489

19-10396

64-Bit Read/Write Memory

74121

19-10230

Monostable Multivibrator

74150

19-10153

Data Selector Multiplexer

74153

19-09927

Dual 4-Line-to-1-Line Data
Selectors/Multiplexers

A.10

74154

19-09701

4-Line-to-16-Line Decoders/

A.ll

Demultiplexers

A-l

‘Table A-1 (Cont)

Integrated Circuits

Manufacturer

DEC

Part Number

74157/74S158

74174/74175

74181

Name

19-10655/

Quadruple 2-Line-to-1-Line

19-10656

Multiplexer

19-10652/

D-Type Flip-Flops, Hex/Quad

19-10651

with Clear

19-09982

Arithmetic Logic Unit/Function

Para

A12

A.13

A.14

Generator (ALU)

74182

19-10019

74193

19-10018

Look-Ahead Carry Generator

Al5

Synchronous 4-Bit Up/Down

A.16

Counter (Dual Clock with Clear)

74194

19-10623

4-Bit Bidirectional Universal

Shift Registers

7528

19-10687

Dual Sense Amplifiers with

A.l18

Preamplifier Test Points

9602

19-09374

Dual Retriggerable Monostable
Multivibrator with Clear

A.19

A.2

8266 2-INPUT, 4-BIT DIGITAL MULTIPLEXER
Truth Table

Output
t 0,1,2,3)

Select Lines
S,
So
0

]%u

1
SELECT

INPUT

INPUTS

OUTPUTS

Vee

INPUTS

12 {11104

243

INPUTS

v——" “——~—

INPUTS

OUTPUTS

r——-—--—-——--—

LK ]

_]’

SELECT GND

INPUT

-——

H-108

NS e CEES

]

T :>°
O
Sy

t3
11-0632

7413 DUAL NAND SCHMITT TRIGGERS

A.3

Vee

sldep

fbls

1 1
1A

21 3H a

SL_G""'T”'—J

POSITIVE

GND

LOGIC: Y= ABCD

11-1114

A.4 7473 DUAL J-K MASTER-SLAVE FLIP-FLOPS

T@®@9@6
Q

GND

} —
Q
CLEAR

K CLOCK J 7
il

OOOOOOO

CLOCK CLEAR

Vce

CLOCK CLEAR

TRUTH TABLE

(EACH FLIP-FLOP)
tn+1

tn
J

[¢]
1
1

1
o]

0
1
Qn

tn = Bit time before clock pulse.
tn+1= Bit time after clock pulse.

———

sot—a(_ |

[

1_3

—a

AU
H
1n-1128

A-S

7474 DUAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

Vee

CLEAR

CLOCK

PRESET

A.5

CLEAR

PRESET

—{cLock @

CLOCK

[}

Q-

PRESET

CLEAR

—
1

1
CLEAR

1
CLOCK

1
PRESET

GND

POSITIVE

LOGIC:

LOW

INPUT TO PRESET

LOW

INPUT TO

PRESET

CLEAR

SETS
SETS

Q TO

LOGICAL

Q TO LOGICAL O

AND CLEAR ARE INDEPENDENT OF CLOCK
11-0766

Truth Table (Each Flip-Flop)

tn+l

tn
Output

Output

Input

Notes:

1. t_=bit time before clock pulse.
2. t,,, = bit time after clock pulse.

A-6

7475 4-BIT BISTABLE LATCH

Truth Table

(Each Latch)

th+l

NOTES:

)

o -y

1. t = bit time before clock
negative-going transition.
2. t+1 = bit time after clock
negative-going transition.

CLOCK

1-2

GND

CLOCK

Vee

3-4

Q
o

CLOCK
L4

cLock] | feLock

—

——0

CLOCK

p—C

—Q

11-0894

A-7

7489 64-BIT READ/WRITE MEMORY

Function Table

Operation

Condition of Outputs

Write

Read

Complement of Selected Word

Inhibit Storage

Complement of Data Inputs

Do Nothing

High

SELECT INPUTS

Vee
_Jwe

Complement of Data Inputs

st jap

DATA

SENSE

DATA

SENSE

|NPUT QUTPUT INPUT OUTPUT

diol ]l

sS4

D3
S3

_“1—2*3r‘4"‘5"s—7"‘8—
SELECT
INPUT
A

MEM WRITE
ENABLES

DATA SENSE DATA SENSE
INPUT OUTPUT INPUT OUTPUT
1
1
2
2

GND

T-1117

A.7

A-8

——

A8 74121 MONOSTABLE MULTIVIBRATOR

Vee

TIMING PINS

—Jiaf i3]

NC
9

B
[‘B_/

GND

11-11419

TRUTH TABLE

4+ XOXXOXO0O—-

O+ =XxX=>2XO0OO0XOXxX-=

00~-00—-=2=2200
-

"Vm(1)’

OX =

[tq,q INPUT

00--=-00C~+--000—+0|@

15 INPUT

-+ XOXO=>=+>0O0X
=X~

Hz2MH3MH

e OXOX==>XOXO-IB

0=Vin(0) £0.8V

OUTPUT
INHIBIT

INHIBIT
INHIBIT
ONE SHOT

ONE SHOT
ONE SHOT

ONE SHOT
INHIBIT
INHIBIT

INHIBIT
INHIBIT
INHIBIT

INHIBIT

74150 DATA SELECTOR MULTIPLEXER

DUAL-IN-LINE PACKAGE

(TOP VIEW)

DATA INPUTS

Yee

2at23fqez}4

Eg
[

DATA SELECT

214201918}

H17

Eio

Eig

{15

|14 -—F;

Es5

Ey
Eg

1
7
“

c
Eg

3
6

rHsesl{

{01112

STROBE

W
D
GND
OUT DATA
PUT SELECT

1
v

O
J

DATA INPUTS

POSTIVE LOGIC

W=SI(ABCDE
+ ABCDE + ABCDE» + ABCDE3 + ABCDE
4 + ABCDE 5 + ABCDE
g + ABCDE7

+ABCDEg + ABCDE g + ABCDE+ABCDEY; + ABCDE
2+ ABCDE
3 +ABCDE 4 + ABCDE1 5)
12-0324

TRUTH TABLE
Output

Inputs

A | Strobe

E)[E3 |Eq

[Es [Eg {E7 | Eg [Eg [Eqo | Eyy

Ep |E13 | Ea | Eys

When used to indicate an input condition, x

togical 1 or logical 0.

A-11

74153 DUAL 4-LINE-TO-1-LINE DATA SELECTORS/MULTIPLEXERS

STROBE
~

*>—

*—

DATA

INPUTS

CONTROL
INPUTS

28
DATA

INPUTS

Bols/eipev/cle

A.10

r OUTPUTS

*—

STROBE

LOGIC DIAGRAM

CONTROL
E

INPUT [ STROBE | OUTPUT
F

LOW

HIGH

LOW

HIGH

LOwW

HIGH

LOW

HIGH

LOW

DON'T CARE

Vee

(EACH HALF)

I
1

TRUTH TABLE

C1r1r-i1ir-

O
PIN

1f
2B

I
4

1
2

I
3

i1+

1
2Y

O
6

)

GND

I
7

|
8

LOCATOR

(TOP VIEW
OF IC)
BE-0138

A-12

A.11

74154 4-LINE-TO-16-LINE DECODERS/DEMULTIPLEXERS

DUAL -IN-LINE PACKAGE

Vee
24

23122

(TOP VIEW)

INPUTS

QUTPUTS

212019

17H{16

1514

GND

OUTPUTS

H-0636

TRUTH TABLE

Inputs

Outputs

H
H

H = high, L =low, X

irrelevant

A-13

74157/745158 QUADRUPLE 2-LINE-TO-1-LINE MULTIPLEXER
EENABLE

SELECT (—17'

(6)

(5)

(3)

(2)

(10)

(11)

Pin 16 = Ve e

Pin 8:=GND

(9)

(7)

(4)

745158 DIAGRAM
-

TRUTH TABLE

INPUTS

OUTPUT Y|OUTPUT

ENABLE | SELECT | A B |

74157 | 745158

X X

H X

X L

H
L

L
H

X H

H=High level, L=Low leve!,X=Irrelevant

74157

LOGIC

DIAGRAM

1a -2
@

18 02
*—]

24 O (5)

o 2y

28 08
6

"
3A C(‘H)

3 ol2)
1

an o

14)

13
ap o2

w2)

‘

-1

SELECT

.-Do—
Pin 162 V¢, Pin8= GND

ENABLE 0“5’)—_4>___

n-13

A.12

A.13 74174 HEX/74175 QUAD D-TYPE FLIP-FLOPS WITH CLEAR

(3)

TRUTH TABLE
INPUT

tn
D

H
L
tn

A F—————0a

(2)

Qa[—°0Qa

TRUTH TABLE

JOUTPUTS

INPUT | OUTPUTS

th+?
Q

—
—QJCLOCK

'I‘I

CLEAR

H
L

L
H

—

= Bit time before

" clock pulse.

tat1=Bit time ofter

8 c(fi)

'n"1

tn =Bit time before
clock pulse.

Qg --ELQB

tht1=Bit time after

clock pulse.

clock puise.

OICLOCK

CLEAR

‘}__J
c o8

4
(4)

(2)

CLK Qpf—o

OICLOCK

CLEAR |

CLEAR

T
D C(Ln

(10

Dp Qp ‘—‘O) Qp

|°s Qg |(7}
QCcLK Qgl—

Ol CLOCK

CLEAR

9
E é13)
p—

(12)

De Qg '“—2)0 Qg

CLEAR

CLOCK 0——~(9)

)

_dcLock

]

CLEAR

(14)

(}(1 3)

(15}

Qff—>oQf

(9)
cLocko—

—

CLEAR

CLEAR ):

Pin (16)
= Vcc,Pin (8)=GND

Qcp—o

QICLK Q¢ f—o

gjcLock

F o~

(10)

CLEAR ©

(15)

-gcLk Qpl—o

CLEAR

Pin (16)= Ve, Pin (8)=GND

V-3

74175 Diagram

74174 Diagram

A-15

A.14

74181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR (ALU)

Active-Low Data
M=H

Selection

M = L; Arithmetic Operations

Logic

c,=0

c, =1
Cn =]1=H

Functions

Cn =0=

L
L
L

L
L
H

L
H
L

F=A
F=AB
F=A+B

F = AMINUS 1
F = ABMINUS I
F=ABMINUS 1

F=1

F = MINUS 1 (2's COMP)

F = ZERO

L
L

H
H

L
L

L
H

F=A+B
F=B

F=APLUS(A+B)
F=ABPLUS (A +B)

F=APLUS
(A +B)PLUS |
F = ABPLUS
(A + B) PLUS 1

F=A+B

H
L

L
L

F=A®B
F=AB

F = A MINUS B MINUS 1

F=A
F=AB
F=AB

F=AMINUSB

F=(A+B)PLUS1

F=APLUS(A+B)

F=APLUS
(A + B)PLUS |

F=A®B

F=APLUSB

F=APLUSBPLUS
1

F=B

F= ABPLUS (A +B)

F = AB PLUS (A + B) PLUS 1

F=A+B

F=(A+B)PLUS
1

F=0_

F=APLUS A

F=APLUSAPLUS
1

F=AB

F = ABPLUS
A

F = ABPLUS
A PLUS 1

F=AB

F=ABPLUS A

F = AB PLUS A PLUS 1

F=A

F=APLUS
1

A-16

PIN DESIGNATIONS

Designation

Pin No.

Function

A3,A2,A1,A0

19,21,23,2

WORD
A INPUTS

B3,B2,B1,B0

18,20,22,1

WORD B INPUTS

S3,82,51,S0

3,4,5,6

FUNCTION-SELECT INPUTS

CARRY INPUT

MODE CONTROL INPUT

F3,F2,F1,F0

13,11, 10,9

FUNCTION OUTPUTS

A=B

COMPARATOR OUTPUT

CARRY PROPAGATE OUTPUT

Coia

CARRY OUTPUT

CARRY GENERATE OUTPUT

SUPPLY VOLTAGE

GND

GROUND

INPAUTS

—

OUTTUTS

Vo A1 Bl

A B2 A3 B3

T Cpg P

A8 F3

14 —-|_|-3-

Cpn+g

’

)

4 [5V

GND

INPLTS

l OUTvPUTSJ

tz-o321

A-17

A-18

A.15

74182 LOOK-AHEAD CARRY GENERATOR

INPUTS

Equations:

OUTPUTS

Cn+x = G0 + POCn

Vee

Cnx Cn+y
12

ntz

Coty =Gy + PGy + P1PoCy

Chz = G2 + PyGy +PyP Gy + PoP PoCyy
]

(}==(}3 + P3(;1 + P3])2(;1 + P3I>2P1(;0

Cp+x Cney

Cn+z

P=P;P,PP,

1 ] 2]3]q
i

INPUTS

[5]6]T

GND

QUTPUT
12-0326

PIN DESIGNATIONS

Designation

Pin No.

Function

G0,G1,G2,G3

3,1,14,5

ACTIVE-LOW CARRY GENERATE INPUTS

P0,P1,P2,P3

4,2,15,6

ACTIVE-LOW CARRY PROPAGATE INPUTS

CARRY INPUT

Cptx Crrtys Ctz

12,11,9

CARRY OUTPUTS

ACTIVE-LOW CARRY GENERATE OUTPUT

ACTIVE-LOW CARRY PROPAGATE OUTPUT

Vee

SUPPLY VOLTAGE

GND

GROUND

A-19

D__

s
]
-

H%j:[}

Cn+y

Ch+x

12-0323

—

A.16

74193 SYNCHRONOUS 4-BIT UP/DOWN COUNTER (DUAL CLOCK WITH CLEAR)

J OR N DUAL-IN-LINE PACKAGE (TOP VIEW)
INPUTS

INPUTS

OUTPUTS

DATA
A

CLEAR ,——A—— LOAD
BORROW CARRY

COUNTCOUNT

Qp DOWN

CLEAR
CARRY
BORROW
LOAD

DATA
INPUT

——

OUTPUTS

COUNT COUNT

DowN

Q¢

DATA

1 o]

GND

uwp , °©

INPUTS

DATA

OUTPUTS

LOGIC: LOW INPUT TO LOAD SETS Qa=A,Qg=B,Qc=C,AND Qp=D

i1-0640

A-21

o BORROW
QUTPUT

o CARRY
OQUTPUT

DATA

INPUT

>
==

DOWN
COUNT

COUNT

DATA

INPUT B ©

—o OUTPUT Qg

DATA

INPUT ¢ ©

PRESET

Q¢

CLEAR o

DATA
INPUT D

- OQUTPUT Qp

LOAD °—<{>
1n-064:

A.17

74194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS

16 415

Ve¢

-3 = T3 == KT == R T0)

Q¢

cLock

CLEAR
A

[

tHH2H3

CLEAR SHIFT

RIGHT SERIAL
INPUT

PARALLEL
INPUTS

SHIFT GND

/ LEFT
SERIAL
INPUT

H-hazi

A-23

A.18

7528 DUAL SENSE AMPLIFIERS WITH PREAMPLIFIER TEST POINTS

TRUTH TABLE
INPUTS

DEFINITION

OUTPUT

INPUT

OF LOGIC LEVEL

ViD>VT max|ViD<VT min|IRRELEVANT

VIZ2VIH

'A is a differential voltage (V|p) between Al and A2.For

which terminal is positive with respect to the other.

MIN

{VI<ViL MAX|IRRELEVANT

these circuits V|p
is considered positive regardless of

n-1122

OUTPUTS

CcC

STROBE ¢

TtH2H 3
Cext

1Al

1A2

N STROBE

1312

GND
9

al4sHHefd
7H s
-VRer

-VREF

2A1

POSITIVE LOGIC: W=AS

A-24

2A2

V¢¢

A.19

9602 DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH CLEAR

Vee
16

INPUTS

[5)
CLEAR

\ -

CLEAR
0

[
1

INPUTS

CLEAR ~

OUTPUTS

l
2

v
INPUTS

CLEAR*

~
INPUTS

TRUTH TABLE

M= HIGH. LEVEL

L=LOW LEVEL

$ = LOW TO HIGH TRANSITION

§ =HIGH TO LOW TRANSITION
1-1130

A-25

v
OUTPUTS

GNOD

APPENDIX B

COMPUTER CONNECTORS

Table B-1 lists the computer connectors, the connector type, part number, pin and signal designations, and the
associated connector cable. This includes the connectors for the SCL cable that interfaces the computer (Berg)
connector to an LA30 or Model 33 ASR Teletype equivalent (Mate-N-Lok) connector. The power supply connectors
are described in Part 4 of this manual.

Table B-1
Connectors

Connector

Type

SCL
Connector

40-pin Berg

Part Number

549949
(Female)

1270090-0
(Male)

Designations

Cable

Signals

BB
\Y

-15V
SER 0+ (20 mA)

70-8820

R
N
L

READER RUN — (20 mA)
CLK DISAB (TTL)
SER 0 — (20 mA)

+5V

T
DD

D
F
RR

NN
LL

Teletype

6-pin

1209340

Mate-N-Lok
or LA30
Connector | (Female)

Console

40-pin

Berg
Connector

549949

(Female)
1270090-0

3
4

CLK IN(TTL)
SER IN — (20 mA)

SER 0 (TTL)
READER RUN + (20 mA)
SER IN (TTL)

20 mA INTERLOCK
SERIAL IN + (20 mA)

SER O -

-15V
-15V

SERO +

6
7

READER RUN
SER IN

DAK H

BB
DD
FF
1)
LL

B-1

SWI15(1)H
SWI14(1)H

SWI13(1)H
SWI12(1)H
SWI11(1)H

70-8360

BCO8R-03

Table B-1 (Cont)
Connectors

Connector

Type

Part Number

Designations
Pin

Console
(cont)

Unibus

NN
RR
TT

Signals

SWI10(DH
SWO09 (1) H
SWO08(1)H

SWo07(1)H

SWO06(1)H

SWOS(1)H

SW04(1)H

SWO03 (1)H

SWO02(1)H

SWOl1(1)H

SWO00(1)H

SCAN ADRS 01 (1) L

SCAN ADRS02(1)L

SCAN ADRS03(1) L

SCAN ADRS04 (1) L

CcC

PUPL

RUNL

KEY LOAD ADRS (1) L

KEY EXAM (1) L

KEY CONT (1) L

KEY HLTENB(1)
L

KEY START (1) L

KEY DEP(1) L

M920 or

AAl

INIT L

M930

AA2

POWER (+5V)

AB!

INTRL

AB2

GROUND

ACl

DOOL

AC2

GROUND

ADI

D02 L

AD2

D01 L

AE1

D04 L

AE2

DO3 L

AF1

D06 L

AF2

DOSL

AHI1

D08 L

AH2

DO7 L

AJl

DIOL

AJ2

D09 L

AK1

D12 L

AK?2

DIl L

ALl

D14 L

AL2

DI3L

AMI

PAL

AM2

DI5SL

ANI1

GROUND

B-2

Cable

Table B-1 (Cont)
Connectors

Connector

Type

Part Number

Designation
Pin

Signals

Unibus

AN2

PBL

(cont)

AP1

GROUND

AP2

BBSY L

ARI
AR2
AS1

GROUND
SACK L

AS2

NPR L

AT1
AT2

AUl

GROUND
BR7L
NPG H

AU2

BR6L

GROUND

AVl

BG7H

AV2

GROUND

BAl

BG6H

BA2

POWER (+5V)

BB1

BB2
BC1

BGSH
GROUND
BRSL

BC2
BD1

GROUND

BD2

BR4L

BE1

GROUND

BE2

BG4 H

BF1

ACLOL

BF2

DCIOL

BH1

AOl1L

BH2

AOOL

BJ1

AO3L

BJ2

AO2L

BK1

AOSL

BK?2

AQ4L

BLI

AO7L

BL2

AQ6L

BM1

AQ9L

BM2

AO8L

BN1

AllL

BN2

Al10L

BP1

AlI3L

BP2

Al12L

BRI

AlSL

BR2

Al4L

BS1

Al7L

BS2

Al6L

BT1

GROUND

BT2

ClL

BU1

SSYNL

B-3

Cable

Table B-1 (Cont)
Connectors

Connector

Type

Part Number

Designation

A
Sionals

Unibus

BU2

COL

(cont)

BV1

MSYNL

BV2

GROUND

1
2

Power Request
Emergency shutdown
Ground

AC Remote | Two 3-pin
Power
Mate-N-Loks
Turn-On

(J6 and 17)

Power
Supply
AC Cable

DEC 12-09351)

Connector

Line Cord

DEC
2-09350-03
(Plug is

Cable

AC Line

(110V)

Connector | Plug

BCOSH
(230V)
BCOSJ

Reader’s Comments
e

COMPUTER MANUAL
PDP-11/05, 11/10

EK-11005-TM-003

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