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EK-OKL10-MG-003

May 1985

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Document:	-003 KL10 Maintenance Guide Volume 1 Rev 3 Apr85
Order Number:	EK-OKL10-MG
Revision:	003
Pages:	409
Original Filename:	EK-OKL10-MG-003_KL10_Maintenance_Guide_Volume_1_Rev_3_Apr85.pdf

OCR Text

KRLE10
Maintenance
Guide

Company

Confidential

Volumel

dlilgliltlall

EK-OKL10-MG-003

RKRL10
,
Maintenance Guide
Volumel

| Prepared by Educational Services
|

| Digital Equipment Corporation
Marlborough, MA

FOR INTERNAL USE ONLY

1st Edition, February 1979

2nd Edition, December 1983
3rd Edition, April 1985

1979, 1983, 1985 by Digital Equipment Corporation
All Rights Reserved

The material in this guide is for informational purposes and is

subject to change without notice.

Digital Equipment Corporation assumes no responsibility for

any errors that may appear in this guide.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation.

flflflflflfln

DEC
DECsystem-10
DECSYSTEM-20
DECUS
DIBOL

EDUSYSTEM

IASMASSBUS
OMNIBUS
0S/8
PDP

RSTS

- RSX
UNIBUS
VAX
VMS
VT

-iii-

ORDERING

KL10/KS10

Maintenance

Guides

order

one

the

both

distribution

Publishing
Order

PROCEDURES

these

list),

guides

(if

you

have

your

order

TWX

guide

per

name)

send

Circulation

never

been

memo

to:

Services

Processing

NRO-2/W3
TWX

Specify

RCS

the

Code

NR12

following:

Name

Badge
Cost

Number
Center

Location
Quantity:

(only

one

EK-OKL10-MG

(KL10

Maintenance

Guide)

EK-OKS10-MG

(KS10

Maintenance

Guide)

KS10/KL10

you

Maintenance

have

Volume

not

receive

Volume

June

1980,

for

that

then

guide.

Publishing

your

To
&

copy

Guide

volume

the

KS10

(Software
name

order

may

Volume

Maintenance

and

not

Circulation

each

II,

Guide,

Diagnostics),

send

the

but

TWX

did

distributed

distribution

memo

list

to:

Services

Order Processing
NRO-2/W3
TWX

RCS

Specify

the

Code

NR12

following:

PLEASE

ADD

NAME

THE

DISTRIBUTION

LIST

Name

Badge
Cost

Number
Center

Location

EK-OKS10-MG

Deletions
To

and

only):

Transfers

deleted

subscription

(Volume

from

the

someone

distribution

list

else,

TWX

Publishing & Circulation
List Maintenance

send

transfer

memo

stop

your

to:

Services

NRO-3/M1
TWX

Specify

RCS

the

Remove:

Code

NR12

following:
Name

Badge
Cost

Number
Center

Location
Add:

New

Name

Badge
Cost

Number
Center

Location
State

which

Maintenance

Guide

you

want

receiving

transfer:
EK-OKL10-MG.

(KL10

Maintenance

Guide)

(KS10

Maintenance

Guide)

EK-OKS10-MG

-iv-—

the

Reader:

IMPORTANT

and

Refer

This

guide

intended
to

company

the

for

policy

contains

use

Field

pertaining

information

DIGITAL

Service

Field

Methods

internal

for

internal

Service

and

use

engineers

Procedures

only

only.

Manual

for

information.

OBJECTIVE - The objective of this guide is to organize and present
the maintenance
information necessary to resolve 80% of all KL1O
hardware
To

malfunctions.

properly

revisions,

maintain

and
feedback

need

improve
this
gquide
in
subsequent
concerning accuracy and clarity. This

communication
is
very
helpful
to
your
forward
any
corrections,
suggestions,
improve

this

guide

fellow engineers.
Please
comments
that
would

and

to:
Customer

Services,

Systems

RE: KL10 Maintenance
MR01-1/S35

ORGANIZATION - Volume
pertaining

with

separate

contains

KL10.

tables

The

general

volume

contents

(CSSE)

maintenance

divided

into

information

tabbed

sections

follows.

GENERAL INFORMATION consists of miscellaneous maintenance
information

the
2.

the

Engineering

Guide

other

that

cannot

hardware

SWITCHES

AND

hardware

switch

classifed

and

filed

any

of.

pertaining

sections.

JUMPERS

contains

positions

and

information

jumper

connections.

TABLES AND MAPS describes the process tables and bit maps
associated
with
the
KL10
mainframe
and
peripheral

equipment.

CHECKS

AND

ADJUSTMENTS

procedures
performed
maintenance.
5.

DIAGRAMS

AND

layouts,

and

KL10-based
5.

MULTI-CPU

specific
7.

MULS

consists
during

check

and

adjustment

and

corrective

contains

module

preventive

block

diagrams,

utilization

1lists

power

associated

supply

with

systems.
contains

maintenance

multiprocessor

DECnet-10/20

contains

and

diagnostic

information

systems.

system

hardware

and

software

information.,
The

information

unit

and

in
subsystem

each

hardware section is
(i.e., CPU, memory, disk,

arranged

tape,

and

according

I/0).

—v—

Volume
related

with

contains

the

separate
l.

additional

KL10.

tables

COMPUTER

cage,

The

hardware

volume

contents

INTERCONNECT

module

contains

1locations,

diagnostics,

and

NETWORK

INTERCONNECT

provides

module

formats,
HSC

SUBSYSTEM

and

consists

intoc

information

tabbed

descriptions

label

locations,

diagnostics,

software

switch

formats,

cage,

and

divided

sections

follows.

descriptions

switch

label

settings,

the

card

bit/error

information.
of

setting,

the

card

bit/error

information.

RA81,

RA60,

and

HSC50

Error

for

fault

Codes.
CLUSTER

TROUBLESHOOTING

isolation

presents

error

BUS

contains

ARM-10LS

provides

isolation

SOFTWARE

KLDCP,

programs.

SYSTEM

SOFTWARE

presents

TOPS-20
and

NOTES

FSC,

jumper,

installation,

operation,

message

and

information

MEMCON,

information

TRACON,

and

memory

DIAMON,

typical

programs

stop/error

information

PIP

contains

provides

RP20

DDT,

operating

formats.

addition

supplies

error

and

information.

description,

consists

includes

PARSER,

and

other

KLDCPU,

command

RSX-20F

TOPS-10

registers

and

installation,

the

D20MON

and

procedures

information.

MAINTENANCE

DIACON,

includes

level.

general

information.

GALAXY-10,

13.

RP0O7

stops,

operation

systems

12,

cluster

routines,

fault

11.

the

RPO7/RP20

S/X

10.

SYSLIB-20F

and

codes.

TOPS-10,

DECnet-10,

programs.

system

program,

command

summary/format,

information.

blank

pages

for

note

taking.

GEN.

INFO.

-1-

TABLE

Support
KLINIK

Phone
Phone

Bootstrap

CONTENTS

Numbers‘...........‘.‘......-........'..... 000000003
Numbers..‘.........Q.....Q.................

ROMS..........QO...l..........................

Vector

and

Address

Unibus

AssignmentsS...cceeeeeecscesossssoonsenscnsns

General

Power

KL10-Based

Supply

System

Module
Module

KL10(PA)
KL10(PV)

Drawing
Drawing

~—

KL10 (PA
KL10 (PV)

CRAM

Front-End

Options....

SpecificationS...eeececeeeceaas

and

Processor

DesignationS........

IndeXeeeeseeeecscecoaoss
IndeX.eeeeeeosoooeeccooeas

Bit
Bit

KLDCP

Basic

Instruction

Device

for

Compatibility.eeeeeescesoscos
Compatibility.eeeseescceccnss

CRAM

LOCAtiONS.
s eeevcesceconcsooansonsea
Map........‘......... ......... * &
and

Codes

~Machine

Assignments

Command

and

Language
Half

Data

Format......

FormatS...... csesssenns
MNnemoniCS..ceeeeeeeeoees
Instructions

Full

and

Word

Byte

ManipulationS.eeeeeeseesccsscocces

Transfers...eececess

BOOlEAN. . eeeeseoesossssssssscccnsssssss

Logical

Testingesseeeeeeesssnccaaanas .

Arithmetic

Testinge.eeeeeeeoess cesresaee

Shift

and

Rotate...eeeeesescocsas ceonese

Fixed

and

Floating

Point

Arithmetic....

StACK . e eeeeseeeeescaceacacocscnassssnsnss
Program

Control...eeesscseesoscsnsnscanne

Extended

InstructionNS..eceessecscccscass

CaAChe .. veeeeesncesosesssssassssonsnssoca

INPUL/OUEPUL
. ettt eeoerestoscnnassscanes
Algebraic Representation CodesS...ve.eess
Seven

Steps

Gathering

Systematic

KL10

System

Fault

Error

Analysis.

Information..

Disabling

Auto-Reload

(TOPS-10).eeeeecoon

Disabling

Auto-Reload

(TOPS-20)..ceeecesn

Gathering

System

Error

KL10 Error Checking
Field Service Probe
KL10

Page

KL10

Hardware

KL10

Page Fail Traps Fault Isolation Table

KL10

Hardware

Memory

Falil

StatuUS...c.ceescoeecaes

Logic Diagrame...oeoeos.
LogiCiiieeeeeeeecnnas

Traps
Fault
Fault

Address

Fault

Isolation

Isolation
Isolation

Table
Table

Table
(Int.
(Ext.

.......47
e

000000050
I..ll..sl

(Int.
Mem.).

(Ext.
.....0054
Mem.). ceesceasan ceseesadb

MapP..seeseess cteseectessenannne .

MA20

1-,

and

4-Way

Interleaving

Diagram.....

MB20

1-,

and

4-Way

Interleaving

Diagram....

Magnetic Tape FOrmatS..eeeesseeccsccssassssnssess
TX0X/TU7x Sense ByteS..ieeeess seessicsensseassas

ceeeeaedb
N

00-000062

KL10(PA and PV) Diagnostic Execute Functions...
KL10(PA and PV) Diagnostic Write Functions..
KL10(PA) Diagnostic Read Functions (Numeric)...
KL10(PA)

Diagnostic

Read

Functions

KL10(PV)

Diagnostic

Read

Functions

(Numeric)........

KL10(PV)

Diagnostic

Read

Functions

(Alphabetic)...

KL10

Data

RP20

Inline

Path

RP20
RP20

Fault
Sense

Parity

(Alphabetic)

NetworkS..eseesoesos

RoOULINES..ieeeeeecoens e tesessssesacene . e
Symptom CodeS....eveecescsascss
Byt S.u...eeeeeeoseasssonosossosossssessosssassossccccaseos 136

GEN.

IMPORTANT

Digital
NORAM

TELEPHONE

Diagnostic

Colorado

303-599-4000

8-522

ext.

NUMBERS

Center

Springs,

This

number

and VAX)

should

used

All
field
engineers
to
request
link or technical assist.
is

This

customers

the

DIGITAL

DDC.

This

should

number

switchboard

by:

extension

LCG

11/70,

Canadian

NORAM

303-599-4111

(10/20/

Colorado

This

INFO.

log

Telephone
number

used

should

request

Network
plus

for

(DTN)

the

KLINIK

code

for

appropriate

contact DDC

used

service.

either

personnel.

contact

the

DDC

operator.

Resources

Digital
U.S.

Diagnostic

Area

Customer

Center

Field

Support

Center

Systems

Support

Center

Digital Equipment Corporation
4405 North Chestnut Street
Colorado

Springs,

Telephone:
DIGITAL

DIAGNOSES

The

DDC

80907-3812

CENTER

staffed

(DDC)

and

provides

the

following

support:

0000000000

Initial System Diagnoses
Technical Support for Field
Remote

Support

Limited

Dump,

Engineer
Referral/Screening
Analysis/Screening

Acceptance

Testing
Verification

Klinik

Inclusion in Action Plans
System Monitoring and Repair
Preventive

Maintenance

Pro-Active

Remote

Special

LCG

Remote

The

LCG

Support
for

Colorado

1-800-525-6570

Certification
-

Diagnostics

(PARD)

Requests

SUPPORT

Remote

Support

Engineers

all

(PM)

Diagnoses

other

Group

hours.

(0600

currently

Future

1800

call

staffed

MT),

1loads

with

may

with

coverage,

provides
options,

First Level Telephone
and limited support on

options.

Line

that
by

Remote

expertise

are

across

the

LCG

the

" limited
LCG

CRASH

Crash
o

AREA

product

Remote

Support

the

KS,

and

(Disk,

Group,

depending

Tapes,

etc.)

Cross

the

option

may

the

KS,

KA,

and

specific

and

options.

options,

and

ANALYSIS

Analysis
Crash

THIRD

Group
is

Analysis
LEVEL

Product

and

available.

Support

support

KA,

lines

Support

Group,

engineer

Technical

The

Support

supported

level

coverage

a
’

LCG Remote Support
KL and KL specific

Options

T7S

standby

dictate

staffed

RSX20F,

TOPS20,

(0800
and

SUPPORT

Provides third level support on KL systems,

1800

TOPS10

MT)

"GEN. INFO.
TELEPHONE

The

TSC

all

other

SUPPORT

Support
with the
The

TSC

Library
is

Service

with

invoke

Center

(0800

1800

MT)

with

standby

coverage

1is
provided
TSC.
software

customers

having

software

analysis

Operating

Systems

and

Products,

staffed

any

you

M-

Technical
HOW

(TSC)

LIBRARY

AREA

The

does

Layered

hours.

Software
contracts
o

CENTER

staffed

YOU

resource

dial

(0600

1800

MT).

They

provide

Field

Documentation.
ACCESS

THE

Colorado

the

1-800~-525-6570

ABOVE

and

ask

RESOURCES?
Springs

for

Customer
Support
specific group you

the

desire.
DIGITAL
If

the

DIAGNOSES
DDC

contacted
be

the

contacted

will

begin

the

will

inform

Once

the

affect
DDC

one

(DDC)
by

the

customer,
them

hour

call.
with

Engineer

DDC.

Support

the

inform

approximately

working

Branch

Technical

DDC

within

approximately
If

CENTER

contacted

The

type

The

the

needs

the

fifteen

Branch

then

immediately

customer

will

notified

results or

will

The
and

status

assistance

DDC

Branch

call.
minutes

the
the

working

change

the

will

engineer

within

call.

the

call

type

call.

call

four

hours

fix,

will

then

old,

and

the

DDC

has

turned

over

Remote

not

been

able

Support

the

Engineer.

LCG

REMOTE

the

SUPPORT

Remote

Service

Support
Group
is
Engineer, Product Support

help

the

resolution

Service

Product

contacted
by
either
the
Field
Engineer, or the DDC Engineer to

problem,

Support

they

Engineer

will

work

(on-site)

with

the

Field

to resolve

the

problem.

When

has

Remote

worked

After

Support

the

Remote

call

requested,

and

been

Support

has

unable

worked

assumed

affect

call

for

that

engineer

fix.
three

hours,

the

District Product Support Manager/Engineer will be notified of the
problem and
the call
turned
over
to
them.
If
they
request,
the
Remote Support Group may assist the District in the established
Action Plan
(set
up by
the
Branch
and District)
with
telephone
support
LCG

(depending

CRASH

All

initial

the

DDC.

contact

the

groups

requests

for

crash

Once
with

specific

call

load

and

available

staff).

ANALYSIS

the
the

engineer
Branch

problem

may

analysis

performing

Engineer,
be

referred

will

the

then

crash

all

screened
analysis

dumps

directly

through
has

relating

the

made

'LCG

that
Crash

Analysis Group.
Requests
basis,

for

and

crash

also

analysis
the

are

handled

availability

analysis. However, support
of a routine nature.

level

requests

first-in

engineer

have

first-out

perform

priority

over

the

those

When calling for Crash Analysis it is assumed that an engineer has
a system with a recurring problem that he/she has been unable to
diagnose
wusing
other
methods
of
troubleshooting.
It
1is
also
assumed that correct telephone numbers, account and passwords are
provided,

the

and

required

that

files.

sufficient

privileges

are

avallable

access

GEN.

THIRD

US AREA

This

level

Unit

Manager.

LEVEL

SUPPORT

support

TELEPHONE SUPPORT CENTER

support

Software
number

Support

Service,
US

and

AREA

the

Product

Regional

Support

(TSC)

contact

provided

and Remote

invoked

provided

specific

also

DDC,

INFO.

customers

valid

access

Specialist,

Field

having

person.

Field

Software

Support Engineers.

LIBRARY

Documentation support is provided to all Field Service Engineers.
EUROPEAN

Telephone

LCG

SUPPORT

Numbers

(33)

(93)

74 72 50

(33)

(93)

LCG Area Manager

(33)

(93)

Backup Support Manager

(33)

(93)

Hotline

Cupid

45 05

*NdD

OPERATOR NUMBER
SITE CONTACT

*OdNI

KLINIK NUMBER

_9_

SITE

MR-2329

GEN.

INFO.

-7

BOOTSTRAP

ROMS

BM873YH

First Used

On - DECsystem-10XX console

- Current

Usability

DECSYSTEM-20XX console
Summary

front

DECsystem-10XX

front

end.

front

end,

Used if DECtape bootstrap
in configuration.

(unit

end.

—console

‘

Features

Switch

disk bootstrap
floppy disk bootstrap
DECtape bootstrap

RP04/05/06
W

RX11l

SO UL

TCll
Error

parameters

Parameter

entry

Button
o WN

retry

Bootstrap

Addresses

773000

Switch

773030
773020

Disk
Floppy/DECtape

773554

DTE20

Other

Entry

Locations

773300
TCll DECtape bootstrap.
0) desired and RX1ll floppy exists
BM873YJ

First

Used

DECSYSTEM-20XX

communications

front

end.

Current
Usability
DECsystem-10XX
console
front
“end,
DECSYSTEM-20XX console
front end,
DECsystem-10XX communications
front

end,

OO~
u b WN -

DECSYSTEM-20XX communications

Summary

front

end.

Features

Switch register
RP04/05/06 disk bootstrap
RX11 floppy disk bootstrap
TC1l1l DECtape bootstrap
DTE20 bootstrap and dump
DL11 asynchronous line bootstrap
retry

Error

Bootstrap

parameters

Parameter

entry

PDP11/34

support

Addresses

773220

Switch

(halts)

773000

Switch
Disk

(does

773030

B W

Button

773020
773230

Floppy/DECtape/DL11
DTE20

not

halt)

Other Entry Locations
773214
TC1ll DECtape bootstrap.
Used 1if DECtape bootstrap
0) desired and RX1l floppy disk exists in configuration.

773530

DL11

desired

and

asynchronous
either

configuration.
To

make

any

RX1l1

line

bootstrap.. Used

floppy

disk

TCll

the

first

DH11

DL11l

DECtape

(unit

bootstrap
exists

1in

'
terminal

act

‘as

the

console

. terminal, select the line number using the switches on the 11/40.
Bits 14-11 are the line numbers. The line numbers start at line 0.
Bits

300 baud

1200

14-11

XXX277 (address in the switéhes)

XXX317

2400

XXX337

4800

XXX347

9600

XXX357

GEN.

INFO.
-8~

VECTOR

AND

ADDRESS

ASSIGNMENTS

|DQll

|DM11BB|DH1l

FOR

FRONT

END

OPTIONS

|LP20

|CcD20

Unit

cTY

No.

|DN11

|775200{760230|770500]760020|774400|775400!777160]
660

350

540

360

370

550

400

410
(760120

700

430

774

754

230

770

750

560

420

764
774540
760

|775250]760300[770550|760140

570

440

450

|775260(760310|770560|760160
710
600
460
470

|775270(760320]|770570 (760200

714

610

|775300{760330

|775310(760340

|775320|760350

720

724

730
12

340

|775240{760270|770540

704
07

530

|775230|760260|770530|760100]
674

330

|775220(760250|770520{760060|774500
670

320

|775210(760240{770510]760040|774440|775420

664

520

|DTE20

500

510

620

630

640

{775330]760360

734
13

|775340
740

|775350

650

744
15

|775360
750

[775370
754

DL11-E

fel

RH11

175630

RH11

176700

RX11

177170

740
fe2

175640

fe3

175650

730

720

254

264

|DL1l1-C|DL11-E

777560|775610
60
300

GEN

INFO.

_9_

UNIBUS

(BY

ASSIGNMENTS

NUMBERS)

UNIBUS

ASSIGNMENTS

(BY

SIGNAL NAME)

AOO

AAl

INIT

AA2

POWER

AO1

BH1

AB1
AB2

INTR L
GROUND

AO2
AO3

L
L

BJ2
BJ1

AC1
AC2

DOO L
GROUND

AO4
AO5

L
L

BK2
BK1

AD1

DO2

AQO6

BL2

(+5

BH2

AD2

DOl

AO7

BL1

AE1

DO4

AQO8

BM2

AE2

DO3

AO9

BM1

AF1l

DO6

Al0

BN
2

AF2

DO5

All

BN1

AH1
AH?2

DO8
DO7

L
L

Al2
Al3

L
L

BP2
BP1

aJl

D10

Ald4

BR2

AJ2

DO9

Al5

BR1

AKl1

D12

Al6e

BS2

AK2

D11

Al7

ALl

D14

ACLO

AL2

D13

AM1
AM?2

PA L (Dl6
D15 L

AN1

GROUND

BS1

BBSY

(D17

BF1

BG4
BG5S

H
H

BG6

AP2

BE2
BB1
BAl

AN2

BG7

AV]

APl

GROUND

BR4

BD2

AP2

BBSY

BR5

BC1

AR1

GROUND

BR6

AU2

AR2

SACK

BR7

AS1

GROUND

AS2

NPR

AT1

GROUND

L
L

DOO

AT?2

BU2
BT2

aACl

AT2

DO1

AD2

AUl

NPG

DO2

AD1

AU2

DO3

AE?2

AV1

D04

AE1l

AV?2
BAl

GROUND
BG6 H

DO5 L
DO6 L

AF1

BA2

POWER

BR1

BB2

BC1

BC2

BD1

AH?2

DO8

AH1

GROUND

DO9

AJ2

D10

-.GROUND

D11

AK?2

GROUND

D12

AK1

BD2

D13

AL2

BE1

GROUND

D14

ALl

BE2

D15

AM?2

GROUND

BF1

4
4

ACLO

AF?2

DO7

(+5

AJ1

AB2

BF 2

DCLO

GROUND

AC2

BH1

AOl

GROUND

AN1

BH2

AOO

GROUND

APl

BJ1

AO3

GROUND

AR1

BJ2

AO2

GROUND

Asl

BK1

BK?2

AOS5

GROUND

AT1

AO4

GROUND

BL1

AQO7

GROUND

AV?2
BB2

BL2

AO6

GROUND

BC2

BM1
BM2

AOS9

GROUND

BD1

AO8

BN1

All

BE1
BT1

GROUND
GROUND

BN2

Al0

GROUND

BP1

Al3

INIT

BV2
aal

BP2

Al2

Al5

INTR
MSYN

L
L

AB1
BV1

BR1
BR2

Al4d

NPG

BS1
BS2

Al7
Al

NPR

BT1

GROUND

L
L

BT 2

+5
+5

V*
V*

BU1

SSYN

BU2

BV1
BV2

AUl

AS2

(Dlée
(D17

L)
L)

AM1
aANZ2

AAZ2
BA2

SACK

AR2

DCLO

BF?2

GROUND

SSYN

BU1

MSYN

NOTES

supply
only.

wired

power

these

the

bus

pins

terminator

+5 V should never be conneéted via
the

Unibus

between

system

units.

GEN.

INFO.
-10-

GENERAL

POWER

The
following
voltage
backplane of the option.
POWER

SUPPLY

TYPE

SUPPLY

SPECIFICATIONS

measurements

are

TOLERANCE

MAXIMUM

OUTPUT

MAXIMUM

+10
+1.8

+11.0
+1.,9

+9.4
+1,7

300
N/A

-3.0

-3.15

-2.85

N/A

+10

+11.0

+9.4

300

-15

-16.5

-14.5

700

706

+50

+54.0

+49.0

1500

723

+9.5

+7.8

600

725

-15

-18.0

~14.7

900

728

+10
-15

+11.0
-16.0

+9.5
-14.5

700
700

+53

+55

+52

250

+65

+63

250

+25 V

+30

+20

-15

-16.5

-13.5

N/A

+3.5

+2,5

"N/A

744/7440

+5.05

+4.95

150

745

-15

-15.05

-14.95

450

754

+20

+20.2

+19.8

450

-5

-5.05

-4.95

150

702

703

705

VARIABLE

732
739

742/7420

761

MINIMUM

VARIABLE

-2

RIPPLE

MILLIVOLTS

600

N/A

NONE

-5.2

made

NONE

770

+15

+15.05

+14.95

450

778

-15

-16.5

-14.5

700

7131/7131A

+5.07

+4.93

+12

+12.18

+11.82

100

-2

-2.03

-1.97

-5.2

-5.28

-5.12

from

the

GEN.

KL10-BASED
The

SYSTEM

following

AND

tables

PROCESSOR
summarize

INFO.

DESIGNATIONS
the

differences

KL10-based
DECsystem-10,
DECSYSTEM-20,
Consult
the
Option/Module
List
for
a

between

and
KL10
complete

the

various

processors.
1list
of
the

differences.

KL10

System Designations

Designation | Description
1080

KL10-A(PA)

1088

Dual processor (1080) systeé

1090

running

TOPS-10

RKL10-B(PA) or KL10-D(PV) running TOPS-10

1090T

KL10~BC(PA)

running

1091

KL10-E/R(PV)

with

cache

running

1095

KL10-E/R(PW)

with

MCA25

and

1099

SMP multiprocessor

2040

KL10-C(PA)

KL1O0-E(PV)

2050

KL10-C(PA)

KL10-E/R(PV)

2060

KL10-E/R(PV)

2065

KL10-E/R{PW)

PV/]

(1090)

with

MOS

with

MCA25

system

only)

TOPS—lO

MG20

system
running

with

TOPS-20

cache

running

TOPS-20

memory

and

INT

MG20

MAX NO.

CACHE

CHAN | DTEs;

RH20s|

DIA | DMA

NO | 10

YES

YES | YES

KL10-B

YES

YES | YES

KL10-BC

YES

YES | YES

KL10-C

OPTIONAL | YES

KL10-D

YES|

YES

YES | YES

KL10-E

YES|

OPTiONAL

YES

OPT | OPT

KL10-R

YES | 20

OPTIONAL | YES

OPT | OPT

with

slots

KL10-A

TYPE|

(ARPANET

Processor Designations

KL10

Designation | PW

TOPS-20

'NOTES

KL10-PA

(Model A)

basic

KL10-PW

(Model

faster

either

CI20

for

cache

and

Unofficially, this processor is

the Model

A machinef

clock.

Unofficially,

this

processor

referred to as the Model B machine.

A KL10-PV which has been modified to enable support
MCA25.

number of RH20s

*Maximum

A KL10-PA which has been modified to include
extended addressing, more extensive microcode, and
variation

processor

internal channels.

referred

KL10-PV
2.
(Model B)

ECL

will

NIA20.

decrease

with

installation

GEN.

INFO.
-12-

KL10A,

VRS
MODULE

CPU-PA

TYPE

M8510

MODEL A(PA)

MODULE

REVISION

SYSTEM

REVISION

COMPATIBILITY

10B

12-12D

M8511

B,C

M8512

A,B,C

A,B,C,

M8513

D1,F

M8516
M8517

D1,F

D,E

D,E
B

D,E

M8518

M8519

A,B,C

a,B,C

M8520

A,B,C

M8522

D
A

M8523

B,C

M8524

D,E

M8525

E,F,H

E,F,H
F<H

M8526

F<H

M8527

F<H

M8528

M8529

c,Cc1,D

c,C1,D

c,Cl1,D

E
B

c,C1,D

M8530

M8531
M8532
M8537

B,C

D,E
c,D

B,C

D,E
c,D

M8538

D1,F
c,D

c,D

M8539

c,D

MODULE

CACHE

MODULE

REVISION

COMPATIBILITY

TYPE

10A

12-12D

M8514

M8515

M8521

MODULE

CACHE

SUBSTITUTE

MODULE

TYPE

REVISION

10A

10B

12-12D

| A

M8549YF

| A

M8549YH

| B

M8549YE

MODULE

CHANNEL

MODULE

TYPE

M8533

REVISION

COMPATIBILITY

10A

10B

o
c,D

C
c,D

12-12D

M8534

c,D

o
c,D

M8535

c,D

M8536

c,D

D,E

c,D

D,E

c,D

D,E

MODULE

CHANNEL

TYPE

SUBSTITUTE

MODULE

REVISION

10A

10B

12-12D

| A

M8549YC

| A

M8549YD

| B

M8549YA

MODULE

RH20/DTE

MODULE

REVISION

COMPATIBILITY

TYPE

10A

108

12-128B

M8552

E,F

M8553

H,J,K,L

M8554

D,F

M8555

c,D,E

C,D,E

M8556
M8557

c,D,E

C,D<E<F

D,E

D<E<F

M8559

C,D<KE<F |
o

D1,E

MODULE

DMADIA

TYPE

10A

10B

12-12a

M8550

B,C

M8551

| H,J,K,

| C,D<E<

MODULE

H,J,K,L

REVISION

| H,J,K,L

F
D,E

COMPATIBILITY

M8558

B,C,D

M8560

B,C,D

B,C

B,C,D

B,C

B,C,D

B, C

M8563

B,C

D,D1

B,C

D,D1

D, D1

E,F

GEN.
-13-

KD10D,

MODEL

MODULE

CPU-PV

MODULE

B(PV)

REVISION

TYPE

SYSTEM

B,C

B,C
B

D,E

M8513YA

M8514

M8515
M8516

D,E

M8517

M8518YA

M8519

).\

M8520YA

M8521

M8522

M8524
M8525

D,E

M8526YA

M8529YA

D,E

D1,F

M8531YA

M8532

D,E

M8532YA
M8533

A
a

M8534

c,D

M8535

c,D

M8536

M8537

M8538

c,D

M8540

c,D

M8541

c,D

).\

M8542

M8543

M8544

).\

M8545

M8548

MODULE

CACHE

TYPE

10A

10B

4-4D

M8549YA

M8549YC

M8549YD

M8549YE

M8549YF

M8549YH

MODULE

MCA25

SUBSTITUTION

MODULE

B
LARGER

REVISION

B
CACHE/PAGER

TYPE

M852

M853
M854
M855
M856
M857
MODULE

RH20/DTE

MODULE

REVISION

Al,A2

COMPATIBILITY

TYPE

10A

10B

M8552

E,F

M8553

E,F

J,K,L

E,F

J,K,L

M8554

J,K,L

J1,M

M8555

c,D,E

12A-12B

D,E

M8556

C<D<E<H

C,D<E<F

M8557

D<E<F

E,H

M8559

D1,E

MODULE

DMADIA

MODULE

REVISION

TYPE

10A

10B

12-A

M8550

B,C

M8551

M8558

c,D

C
c,D

M8560

C
c,D

c
c¢,D

M8563

D1,F

Dl,F

COMPATIBILITY

B,C

NOTE

Refer

level

changes.

VRS

COMPATIBILITY

M8512

REVISION

COMPATIBILITY

REV

(purple

For

microfiche)

KL10-R,

see

KL10~-R

for future
RM.

revision

INFO.

GEN.

INFO.
-14-

KL10-PA DRAWING

INDEX

Module Type | Index Name | Module Description

M8563

ATl

ADAPTER INTERFACE

DM20 BOARD 2

AIZ2

ADDRESS BUFFERS

DM20

AIS

TIMING LOGIC

DM20 BOARD 2

M8539

APR1-6
APR7

M8559

CDS3

M8514

APR BOARD
APR POWER,

CHAl

0, 1 BITS 14-25

CHA3

CACHE DIRECTORY

BIT

CHAS
CHAG6

CACHE DIRECTORY
CACHE DIRECTORY

CHD1

CACHE DATA

BITS

[N]

POWER, GND, CAPS
TERMINATORS

CHD2
CHD3

CACHE DATA
CACHE DATA

BITS
BITS

[N+03]
[N+06]

CHD7
CHX1

TERMINATORS
CACHE DATA
CSH ADR COMPARITORS AND VAL BIT MIXERS

CACHE

M8525

M8528

M8513

M8527
M8550
M8552

M8512

CLl-3
CL4
CLK1

M8554

BITS

CACHE

DIRECTORY

CACHE DATA
CACHE DATA
CACHE DATA

CHX4

M8526

3 BITS

CACHE DIRECTORY

CHA?Z

CHX3

M8551

CAPS

GND,

CACHE DIRECTORY

CHD4
CHD5
CHD®6

M8515

I/0 BOX CLOCK DISTRIBUTION

CHA4

M8521

BOARD

DM20
DM20 BOARD 3

BUSS SELECTION
REQUEST LOGIC

AI3
AT4

&
&
&
&

BRX REGISTERS

GND,

CAPS

INTERRUPT CONTROL

CARRY
CARRY
CARRY
CARRY

IR, DRAM & CARRY
BUS

BR,

FM,

POWER,

IR REG, DRAM BUFF
"DRAM
DIAG REG & MISC
ADD - CARRY NETOWKR

ADAPTER

POWER, GND, CAPS

GEN.

INFO.

-]15~

KL10-PA
Module

M8561
M8562
M8517

M8531

DRAWING
Type

INDEX

Index

M8537

M8530
M8519

M8538

MA20
MA20

MB1-5

MEMORY

MBC1-5

MBOX

M8518

MBC

MBX1-6

MBOX
'MBX

M8516

CAPS

POWER,

GND,

CAPS

LOGIC

CONTROL

MCL1-6

MEMORY

MCL7

MCL

MBZ

CONTROL

POWER,

GND,

INTERNAL MEMORY

CAPS

BUS

TRANSLATOR

MTR1

METER

MTR2

MTR4

ACCOUNTING ENABLES AND
INTERVAL TIMER
PERFORMANCE ANALYSIS

MTR6

METERS

PAG1

PAGE

PAG2
PAG3

PAGE TABLE
PAGE TABLE

PAG4

DATA PT 16-PT-26
DIRECTORY

PAGE

TABLE

CONTROL

PAG5

PAGE

TABLE

PARITY

LOGIC

POWER,

GND,

COUNTERS

MHZ

CLOCKS

EBUS MIXERS AND BUFFERS
POWER,

GND,

TABLE

DATA

CAPS
PT

ACCESS-PT-17

LOGIC

PAG6

PAGING

PIl

PRIORITY

INTERRUPT

PI2

REGISTERS

PRIORITY

INTERRUPT

DEVICE

BOARD

CAPS
SELECTION

PI3

PRIORITY

INTERRUPT

PI4

PRIORITY

CHANNELS

INTERRUPT

EBUS

INTERRUPT

CONTROL

PI5

PRIORITY

PI6

PMAl

PI POWER, GND, CAPS
PHYSICAL MEM ADR

PMA 2

PHYSICAL

MEM

PMA3

ADR

PHYSICAL

MEM

ADR

PHYSICAL

MEM

EBR,

UBP,

UEBR

CACHE

CLR

ADR

INTERFACE

ERA,

32-35

PHYSICAL

MEM

ADR

PMA6

SELECTION

PHYSICAL

MEM

ADR

POWER,

GND,

SCADA,

SCAD,

FLAGS

SCADD,

SCAD,

FLAGS

SC,

SCM,

SCAD,

FLAGS

ARM

DIAG

MIXER

SCAD,
SHIFT

PC FLAGS
MATRIX

PC FLAGS
CONTROL

SH2

SHIFT

MATRIX

SH3

SHIFT

16,

MATRIX

SHIFT

MATRIX

SH5

SHIFT

MATRIX

SH6
SICl

SHIFT

SBUS

INTERFACE

POWER,
TERMINATORS

CONTROL

SIC2

ERROR

AND

CLOCK

LOGIC

SIC4
TRM2-5

TIMING LOGIC DMA20 BOARD
E AND C BUS TRANSLATOR

VMA 1l
VMA3

VMA 4

VMAS5
VMAG6

DMA20

VIRTUAL MEM ADR

DMA

BOARD

CAPS

BOARD

ADDER & CONTROL

MEM

ADR

VIRTUAL

MEM

ADR

VIRTUAL

MEM

ADR

VMA

MEM

ADR

POWER,

VIRTUAL

SCADB

GND

VIRTUAL

VIRTUAL MEM ADR

PMA

BOARD

SIC3

DIAGNOSTIC

CAPS

SCD1

VMA

LOGIC

SCD2

SCD4,
SH1

14-31

PMAS

VMA2

M8523

GND,

CONTROL

MBOX

MEM1-6

GND,

TERMINATORS

MBOX

SH4

M8560

POWER,

MBZ1-6

SCD3

M8510

BUFFER

CONTROL

MBZ7

PMA4

M8524

BOARD

MBX7

MTRS5

M8532

Description

CONTROL BOARD
TIMING BOARD

MB6

- MTR3

M8520

Module

MAC1-6
MAT1-2

MBC6

M8529

(Cont)

Name

VMA

ADR

BRK

HELD

DIAGNOSTICS
GND,

REG

INFO.

GEN.

~16-

CRAM BIT LOCATIONS

CRAM BITS SORTED BY LOCATION

PHYSICAL

LOCATION | FUNCTION

BIT

LOCATION |

FUNCTION

BIT

A4OR2
A40V2
B40OF1
B40OP2
C40F2
C4042

FM ADR SEL 1
COND 05
#08
COND 02
TIME 01
#07

58
59
39
19
78
38

D44R2
D44V2
E44D2
E44P2
E44S2
F44K2

ARXM SEL 2
Joa
403
#00
ADB SEL 2
MEM 01

68
09
08
29
28
a9

E40P2
E40S2

#06
ARMX SEL 4

37
36

E45M2
E4552

DiSPO3
DISPO4

84
85

SH-ARMM SEL 2

FM ADR SEL 4

A50V2

SH-ARMM SEL 1

#05

C40K2
D40R2
D40V2
E40D2
E40K2

E40P2

Ad42P1
A42V2

842F1

B42P2

COND 01
TIME 00
COND 00
MQ SEL

FM ADR SEL 2

BRX LOAD
COND 04

18
76
17
16
57

54
55

J10

Fa4p2
D45M2
D45T2
E45F1

A50R2

BS0A1
BS0P2

C50F2

C5042

MEM 00
DISP0O
DISPO1
DISP02

48
81
82
83

ARM SEL 1

27
p
66

ADA SEL 1
102

ADA SEL 2

301

ca2K2

J09

#04

34
14

DSOV2

100

D42R2

VMA SEL 1

£50D2

FE LOAD

Da2v2

J 08

E50L1

ADA DISABLE

#03

E50K2

Fa2K2
Fa2pP1

COND 03
BR LOAD

53
52

A52R2

A44R2
A44V2
B44F1

MEM 02
MEM 03
#02

50
51
31

B52F1
B52P2
C52F2

Caar2

ARMX SEL1

C52K2

SCAD 2

E52D2
E52P2

SCADA EN L
AD SEL 4

00
21

E52S1
F52K2
F52P2

AD SEL 8
SCADA SEL 1
SCADA SEL 2

20
a1

Ca2F2

ca2.2

E420D2
E42p2

E42S2

B44pP2

caaj2
Caak2

AD CRY

J07

ADB SEL 1

J 06

#01
405

30
10

C50K2

D50R2
E50S1

EEOP2

A52V2

c5242

D52R2
D52V2

ARM SEL 2
AD BOOLE

ARM SEL 4

64
24
45

VMA SEL 2

SCADB SEL 2

AD SEL 1
SCAD 1
SCM SEL 2

23
03
62

MARK BIT

AD SEL 2

SCADB SEL
SCAD4 -

60
01

CRAM BITS SORTED BY FUNCTION

PHYSICAL

FUNCTION

BIT

LOCATION

FUNCTION

BIT

LOCATION

AD SEL 1

B52F1

AD SEL 2

c522

AD CRY

ARM SEL 1
ARM SEL 4
ARXM SEL 2

66
a5
68

AD SEL 4

ADA SEL 1
ADA DISABLE

27
25

AD BOOLE

E52P2

AD SEL 8

B50A1
ESOL1

ADA SEL 2
ADB SEL 1

E50S1

ADB SEL 2
ARM SEL 2
ARXM SEL 1

28
64
70

E44S2
D50R2
Ca4F2

BRX LOAD

ARXM SEL 4

E40S2

BR LOAD

20
26
32

E5281

cazF2

c5002
E4252

C50F2
F50K2
D44R2
Fa2p1

D4OV2

BA4OP2

A42P1

COND 00

CALL

COND 02

COND 03

F42K2

FE LOAD

DISPOO

J 00

D50V2

Joa

D44v2

310
MEM 01

15
a9

#00

#04
#05
#08

34
37
39

ca4J2

SCADA SEL 2

B42F1

SH-ARMM SEL .2

AB50R2

B52P2
D52V2

VMA SEL 1
MARK BIT

72
43

D42R2
A52V2

COND 01

COND 05

DISPO1

Ca0K2

A40V2

D45T2

DISPO2

FM ADR SEL 1
FM ADR SEL 4

58
56

J03

DISPO3
DISP04

J01

J 05

84
85

E45M2
E45S2
C50K2

E44D2

Ca4K2

50
16

A44R2
E40D2

12
14
a8

#01

#03

E45F1

A40R2
F40P2

307
409
MEM 00
MEM 02
MQ SEL

D45M2

405

SCAD 1
SCAD 4

03
o1

E42D2
ca2K2
Fa4p2
E42P2

ca0J2

SCADA SEL 1
SCADS SEL 1
SH-ARMM SEL 1

a1
60
a7

VMA SEL 2

F52K2
D52R2
A50V2
C52F2
C40F2

%07

SCM SEL 2
TIME 01

62
78

COND 04

FM ADR SEL 2

402

J 06
J 08

MEM 03

#02

SCAD 2
SCADA EN L-

SCADB SEL 2

TIME 00

55
57

A42V2
ESOD2

F40K2

BSOP2

L
13

B44P2
D42v2

A44V2

02
00

B42P2
Fa4K2

E44P2

B44F1

C42J2
E40P2
BA40OF1

C52K2
E52D2
F52P2

AB52R2

D40R2

F50P2

MR-2214

GEN.
-17~

CRAM SORTED BY BITS

PHYSICAL

PHYSICAL
BIT

FUNCTION

LOCATION

BIT

FUNCTION

LOCATION

00
01
02
03

SCADAEN L
SCAD 4
SCAD 2
SCAD 1

35
36
37
38

J 00
Jo

D50V2
C50K2

#05
ARMX SEL 4
#06
#07
#08

B42F1
E40S2
E40P2
C4042

05
06

E52D2
D52Vv2
C52K2
B52P2
E50D2

J 02

B50P2

SCADB SEL 2

A52R2

ARM SEL 4
SH ARMM SEL 2

F50K2
AS50R2

FE LOAD

08
09
10
11

J 03
Jo4
J 05
J 06

J 08

16
17

MQ SEL
COND 00

14
15

19
20
21
22

24
25
26
27
28
29
30
31

J 07

43
44
45
46

MARK BIT
VMA SEL 2

D42V2

MEM 00

E40D2
D40V?2

51
52

E44D2

E42D2

C42K2
B42P2

COND 01

C40K2

COND 02
ADSEL 8
AD SEL 4
AD SEL 2

B40P2
E52S1
E52P2
Cc52J2

AD BOOLE
ADA DISABLE
ADA SEL 2
ADA SEL 1
ADB SEL 2
# 00
#01
#02

E50S1
ESOL1
Cc5002
BS0A1
E44S2
E44D2
ca4)2
DA4A4F1

ADB SEL 1
#03

#04

SCADA SEL 2
SCADA SEL 1

D44v2
Ca4K2
B44P2

J 09
J10

AD SEL 1

40
41

B52F1

E42S2
E42P2

ca2J2

49
50

SH ARMM SEL 1

MEM 01
MEM 02

MEM 03
BR LOAD
COND 03

F52P2
F52K2

A52V2
F50P2

AS0V2

F44P2

F44K2
A44R2

Ad4av2
Fa2P1
F42K2

54
55
56
57

BRX LOAD
COND 04
FM ADR SEL 4
FM ADR SEL 2

A42P1
A42V2
F40P2
F40K2

59
60
62
64
66
68
70
72

COND 05
SCADB SEL 1
SCM SEL 2
ARM SEL 2
ARM SEL 1
ARXM SEL 2
ARXM SEL 1
VMA SEL 1

A40V2
D52R2
C52F2
D50R2
C50F2
D44R2
CA44F2
D42R2

TIME 00

FM ADR SEL 1

AD CRY

TIME 01

A40R2

C42F2

D40R2

CAO0F2

‘80

CALL

DISPOO

DA5M2

DISPO1

D45T2
EA5F1

84
85

DISPO2

DISP0O3
DISPO4

*CALL BIT IS USED IN KL10{PV) ONLY, THERE IS NO LOGIC FOR IT IN THE MODEL
PA. THE CALL BIT IS NOT ACCESSIBLE ON THE BACKPLANE , IT MUST BE READ
VIA A DIAGNOSTIC READ FUNCTION 141 BIT 00.

B40F1

E45M2
E45S2

INFO.

*NAD
SCADA

DIS

02
SCAD

]

32
ADB

SEL1

00
:

AD SELECT

36
ARXM

SEL4

07
]

J FIELD

- 25
ADA

BOOLE | DIS

40f’

SCADA SEL

" 02
:

11
06

13
08

27'

AD A SEL

10
i

28
ADB

SEL2

29
00

30
#

SCADB 'MARK

44
VMA

SEL2

45
ARM

SEL4

31
1

01
]

SEL2

’

38
T

04
1

04
|

LOAD

CONDITIONS

.33

SEL

47
T

- SH/ARMM
SEL2

SEL1

BITS

SLOT

<00:03>

<04:07>

<08:11>

<12:15>

<16:19>
-

<20:23>

<24:27>

<28:31>

<32:35>

<36:39>

<40:43>

<44:47>

<48:51>

<52:55>

*OdNI

<56:59>

<60,62>

<64,66>

<68,70>

<7274>

<76,78>

<80:85>

45
MR-2212

..8'[_

C RAM BIT MAP

00
.

ARM

SEL2

03 | LoAD | 03

CALL 1 4o

FM ADR

62
:

= ARXM piiininiinl ARXM

VMA

il TIME

TIME

CRY

SEL1

[

SEL2 [

DISP/SPEC

SEL1

scm

|
COND | SCADB

o SEL1

| SEL2

LOAD | 04

82
|

COND | BRX | conD

SEL1

MEMORY

]

04
MR-2213

*NdD

*OdNI

*NdD

(
J

3777/3777

3777

MaQ

SCAD

VMA

MEM

COND

SPEC

377

777

*OdNI

ADR/

KLDCP EC AND DC COMMAND DATA FORMAT

SEE NOTE

ARITH

"ARITH

00—07

10—17

A+C

ORCB+C
A-B-1+C

A#2+C

NOTE:

A+B+C

BOOLE

COND

00-07

10-17

00-07

10-17

20-27

30-37

40-47

50--57

AR/ARX

SETCA

ANDCA

FM WRITE

DIAG FUNC

VMA—#

CACHE

ORC

XOR

LD ARO-8

PCF—#

EBOX STATE

VMA—#+TRP

ORCA

LD AR9-17

FE SHRT

EBUS CTL

VMA-#+MODE BRO

AD FLAGS

MBOX CTL

EBUS/MQ
-1+C

05
06

AR/ARX
- 00-07

SC,LT,36
EVEN PAR

SCADO

SCAD#0

LD ARR

VMA—-#+AR

ARXO0

ADXO0

ANDC

AR CLR

LOAD IR

VMA-#+Pi*2

AR18

AD CRYO

AD*2

SETCB

ANDCB

ARXCLR

SPEC INSTR

VMA DEC

ARO

ADO

AND

ARL IND

SR—-#

VMA INC

REG CTL

SEL VMA

LD VMA HLD

AND-7+C

ADX

EQV

A-1+C

AD*,25

ORCB

AC#0

AD#0

SCO

AD#0

AR FIELD INCLUDES
AR AND ARX
AD FIELD INCLUDES ADA AND ADB
SCAN FIELD INCLUDES SCADA AND SCADB.
MR-2210

COND

FMADR

MEM

SCAD

SPEC

60—67

70-77

00—07

00-07

10-17

00-07

10-17

20-27

30-37

FETCH

INTRPT

A INDRCT

DIAG

SEC HOLD

MUL

SPEC

KERNEL

-START

BYTE INDRCT

A-B-1

DRAM J

CALL

DIV

USER

RUN

MB WAIT

LOAD AR

A+B

A READ

MQ SHIFT

ARL IND

SIGNS

PUBLIC

10 LEGAL

SECO

LOAD ARX

A-1

RETURN

SCM ALT

MTR CTL

DRAM B

RPW CYCLE

PIS XCT

A READ

AD FUNC

A+1

PF DISP

CLR FPD

FLG CTL

‘BYTE

PI CYCLE

B WRITE

BYTE READ

A-B

LOAD PC

SV FLGS

NORM

iNH CRY18

-EBUS GRNT

AC REF

FETCH

WRITE

NICOND

XCRY ARO

SP MEM

EAMOD

-EBUS XFER

-MTR REQ

REG FUNC

RPW

AND

SH 0-3

GEN CRY18

AD LONG

EA TYPE

ARMM

VMA

N=
O

ADB

SHIFT

ARX

BR*2

AR SIGN

ARX

EXP

PC+1

ADA

AR SWAP

POS

AR*4

VMA

MR-2211

*NUD

ARL IND

*OdNI

COND

*NdD

BASIC INSTRUCTION (KA10, KI10 AND KL10)
00

08 09
1

I
I
I
I
|
INSTRUCTION CODE

12
T

13 14

17 18
T

* QNI

(INCLUDING MODE)
1

‘MR-39563

IN-OUT INSTRUCTION (KA10, KI10 and KL10)
09 10

01 02 03
T

17 18

12 13 14
1

.—Z Z_

INSTRUC-

1
1

DEVICE CODE
1

TION CODE

1
MR-3954

INSTRUCTIONS EXECUTED UNDER EXTEND (KL14O-ONLY)
12 13 14

08 09

00
T

INSTRUCTION CODE

MR-3955

LOCAL INDEX REGISTER (KL10 ONLY)
00

18
I

|
¥
1
1
i
I
|
I
IN NONZERO SECTION MUST BE

]

<0 BITS 6-17=0
|

]

LOCAL INDEX
1

MR-3956

GLOBAL INDEX REGISTER (KL10 ONLY)
05 06
0
1

0
1

0
]

]

GLOBAL INDEX WITH NONZERO SECTION NUMBER

MR-3957

LOCAL INDIRECT WORD (KL10 ONLY)
00 01
1

13 14
I

]

{

]

RESERVED
]

17 18
T

]

X
1

Y
]

MR-3958

GLOBAL INDIRECT WORD (KL10 ONLY)
00 01 02

05 06
I

35
T

]

MR-3959

*NHID

*OdNI

—EZ—

12 13
T

FLAGS
]

17 18
T

[

0
|

35
{

]

)

IN-SECTION PC
1

1
MR-3960

PC DOUBLEWORD (KL10 ONLY)
00

12 13

—————
Y

]

'FLAGS

—
1

0
'

’

+—t+—t

{

INSTRUCTION—DEPENDENT INFORMATION

|
:

|
1

MR-3961

*OJdNI

00
—

*NdD

PC WORD (KA10, Ki10 AND KL10)

SAVED FLAGS
00

OVER -

-09

USER |

FLOW

IN-QUT

~ PREVIOUS

CARRY

CONTEXT*

PUBLIC

FIRST

* ADDRESS

DONE

USER

INHIBIT

PART

FLOATING

OVERFLOW

USER

TRAP

FAILURE

* PUBLIC

DIVIDE

TRAP

FLOATING

UNDERFLOW

—SZ_

CARRY

CONTEXT

*KL10 ONLY

PC WORD

]

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

]

SECTION

FLAGS
1

)

[

IN-SECTION PC
4

*NdD

*OdNI

00 01 02 03 04 05 06 07 08 09 10 11

)

]

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
|

FLAGS

[

1
0

1
o

T
O

)

]

PROCESSOR-DEPENDENT INFORMATION

)

WYT

LOCAL STACK POINTER

CONTROL COUNT

(IN NONZERO SECTION < 0 OR BITS 617 =0)
1

)

]

25/

]

|—

]

IN-SECTION OF LAST ITEM

)

*NdD

00 01 02 03
04 05 06 07 08 09 10 11

*OdNI

FLAG-PC DOUBLE WORD

GLOBAL STACK POINTER

)

]

10
|

11
¥

12
l

13
i

14
I

)

[

ADDRESS OF LAST ITEM (NONZERO SECTION)

)

25
1

26
|}

27
1

28
I

]

29
L

ADDRESS OF LAST ITEM (NONZERO SECTION)
i

]

LOCAL BYTE POINTER (KA10, K110 AND KL10)
00

05 06
1

POSITION P
1

]

'
i

13 14

SIZE S
i

rrrrrTr—Tr
1t 1 1 r 1 1 1 11
—Tr
T 1T 717

o1l

X
|

Y
1

]

*OdNI

*NdD

MR-6482

*NIdO

BYTE STORAGE
~
i

]

35.P.S-1
1

]

SRS N

35.P 35-P+1

BYTE

I T

NEXT BYTE

e—SBITS—fe——P
BITS—
]

: |

MR-3966

GLOBAL BYTE POINTER (KL10 ONLY)
00

01
]

02
¥

POSITIONP

——
o|

‘

05 06

11
1

-7

‘

SIZE S

;

17 18
1

|
1

[

]

}

AVAILABLE TO USER

+—
|

RESERVED

12 13

RN TN A

NS SN SN RRN BN

—8Z_

*0dNI

SECTION POINTER — No Access (TOPS-20 Only)

". ...... l

POINTER TYPE

00000800t

BO0ESO000M

000800008 l.'. DROOCOOt

002080000 [ BOOODORE N ID000OBO00 ) O00DDO0E BOOODDBOCON OOO000000 | 300000O000

IDOOOODNNE

DOOOOOICC

MR-3832

SECTION POINTER — Immediate (TOPS-20 Only)

POINTER TYPE

)

0 =PRIVATE

‘

09
T

0=WRITEPROTECTED
1 =WRITABLE

{

}

@ 27

15
1

16
|

17
I

STORAGE MEDIUM
I

PAGE NUMBER OF PAGE MAP.

[

0=CACHE-LOOK BUT DO NOT LOAD

<12:17>

NON-ZERO INDICATES PAGE MAP IS NOT IN MEMORY

1=PUBLIC

10
I

AVAILABLE TO SOFTWARE

AVAILABLE 1;0 SOFTWARE

08
T

PUB | WRITE |:

07
g

1=CACHEABLE
MR-3833

*NdD

*OdNI

*NdD

SECTION POINTER — Shared (TOPS-20 Only)
1

POINTER TYPE

pus

| wrITE

06
[iF

AVAILABLE TO SOFTWARE

"
[

cACHE

]

35 |

INDEX TO SPT LOCATION CONTAINING PAGE ADDRESS OF PAGE MAP

]

REFER TO IMMEDIATE POINTER FOR BIT DEFINITIONS.

MR-3835
—OE_

NOTE:

]

*OdNT

SECTION POINTER — Indirect (TOPS-20 Only)
-

00
I

PUB

| WRITE

POINTER TYPE

R
] CACHE | .

[

R |

}

]

SECTION TABLE INDEX

AVAIL TO
SOETWARE

LIS

)

30
!

I |

]

INDEX TO SPT LOCATION CONTAINING PAGE ADDRESS OF ANOTHER SECTION TABLE
|

NOTE:

)

]

REFER TO IMMEDIATE POINTER FOR BIT DEFINITIONS.

{

]

MR-3834

BYTE STORAGE
00

)

]

35-P-S-1
T

35-P 35-P+1

BYTE

]

NEXT BYTE

]

le——s BITS—=}e

]

P BITS

—]

MR-3967

BLT POINTER (XWD) (KA10, KI10 AND KL10)
17 18
T

]

SOURCE ADDRESS
1

]

‘

]

|
‘

MR-3968
35

NUMBER OF WORDS IN BLOCK

ACH1

LOCATION OF SOURC!E BLOCK

AC+2

LOCATION OF DESTINATION BLOCK

*NdD

05 06

DESTINATION ADDRESS

XBLT POINTER (KL10 ONLY)

=TE
-

MR-3969

*OdNI

S o4

'G1

;

BINARY NUMBER (TWOS COMPLEMENT)

*OdNI

00 . 01

*NdD

FIXED POINT OPERANDS (SINGLE PRECISION OR HIGH ORDER WORD (KA10 KI10 AND KL10)

LOWER ORDER WORDS
IN DOUBVLE LENGTH FIXED POINT OPERANDS
00 01

k%
sc

35
1

CHRNY N

WA WA SN TN

LOWER ORDER PART OF BINARY NUMBER (TWOS COMPLEMENT)

SO NAN S

SN S

{

SR T

SH SHEE S

U
_Zg..

MR-3970

FLOATING POINT OPERANDS (SINGLE PRECISION OR HIGH ORDER WORD) (K110 AND KL10 ONLY)

00 01
S

08 09
T

,
T

p—

,
‘
(ONES COMPLEMENT)

EXCESS 128 EXPONENT

]

35
T

]

[

LOWER ORDER WORDS IN DOUBLE LENGTH FLOATING POINT OPERANDS

00 01

(

)

‘

FRACTION (TWOS COMPLEMENT)

LOWER ORDER EXTENSION OF FRACTION (TWOS COMPLEMENT) \‘

]

"
MR-3971

SECOND AND

DEVICE CODE AND MNEMONICS

THIRD OCTAL

APR

PAG

INTERRUPT

PAGING

CPA

CENTRAL

PROCESSOR

]

KIo

PTP

PTR

CcDP

PAPER

ARD

PUNCH

READER

DTE20

DTEO
10/11

APE

DTE20

DTE1
10/11

CACHE

cP10

PAPER

TAPE

PRIORITY

14
MCA20
CCA

DTE2
10/11

PDC4

MAGNETIC
TAPE

TIM

MTR

KL10 ACCOUNTING
LOGIC

TTY
CON

TEL:TOYLPE
DTE20

DTES3
10/11

INTERFACE | INTERFACE | INTERFACE | INTERFACE

DX10

626

F?UNCH
DTE20

DX10

30
AD10
ADC2

LPT

VP10

DIS

VP10

DIS2

XY10

PLT

XY10

PLT2

CR10

CR2

CARD

DX10

LP10

DC10

PDC2

LPT2

TAPE

PRINTER | SCANNER | SCANNER | - SYSTEM

DTS

DLS

DLS2

RP10

PDC

TD10

64
|

DL10

DLC

PDP-11 DATA LINK

TAPE

MAGNETIC | MAGNETIC

DTC

DLB

ANALOG| maAGNETIC
DIGITAL
CONVERTER

LP10

34
DX10

PDC3

DPC

RP10

DL10

DLB2

DLC2

PDP-11 DATA LINK
‘

RP10

DTC2

DECTAPE

DTS2

DECTAPE

TTMMI0

TTMMC

TMS

MAGNETIC TAPE

TMC2

CLOCK

REAL
TIME
RC10

DSK

REAL
TIME

RC10

DSK2

DISK/DRUM| DISK/DRUM
RH10

DPC4

SYSTEM

SYSTEM' | CONTROL | CONTROL

TM10

TMS2

MAGNETIC TAPE

RH10

RMC3

RH10

RMC4

RMC

RH10

DPC3

DATA

RH10

RMC5

RMC2
DATA

RH10

RMC6

DATA
DATA
DATA
DATA
conTroL | contrOL | controL | conTRoL
DS10

DSS

DSI

DS10

DSS2

DSI2

SINGLE SYNCHRONOUS | SINGLE SYNCHRONOUS
INE U
LINE UNIT

RH20

74
DK10

CLK2

DPC2

TD10

70
DK10

CLK

MBCO
CODES IN THIS SECTION RESERVED FOR USER SPECIAL DEVICES

RH20

MBC1

RH20

MBC2

RH20

MBC3

RH20

MBC4

RH20

MBC5

RH20

MBC6

MBC7

KI10 UNRESTRICTED CODES

RESERVED FOR USERS

KI10 UNRESTRICTED CODE
RESERVED FOR DEC

MR-2300

"NdD

"OdNI

DIGITS

FIRST
OCTAL
DIGIT

GEN.

INFO.
-34-

MACHINE LANGUAGE INSTRUCTION SET

Full and Half Word Transmission

E
¢ Negative

MoV e Magnitude

to AC

e Swapped

Immediate to AC

no effect
Right| | Ones

to zl:mm)’
to Self

Half word Left } 1\ Left Zeros
Right

Extend sign

Double MOV Ee Negative

{ to~ Memory

eXtended MOVE Immediate
eXtended Half word Left to Left Immediate
BL ock Transfer

eXtended BLock Transfer
EXCHange Ac and memory

Full Word Daté Transmission
EXCH

(AC) < (E)

MOVE

(E) = (AC)

MOVS

204

MOVEI

0,E - (AC)

MOVSI

205

E,0- (AC)

MOVEM

(AC) = (E)

MOVSM

206

(AC)s~— (E)

MOVES

If AC # 0: (E) = (AC)

MOVSS

207

(E)s— (AC)

(E)s— (E)
If AC # 0:

(E) = (AQ)

MOVN

210

- (E)~> (AO)

MOVM

214

(E)| ~ (AC)

MOVNI

211

- [0,E] = (AC)

MOVMI

215

0.E -~ (AC)

MOVNM

212

- (AC) = (E)

MOVMM

216

[(AO)|
= (E)

MOVNS

213

= (E)~>(E)

MOVMS

217

If AC#0: (E) > (AO)

(BE)I—=(E)
If AC # 0:

(E) = (AQ)

If not local AC reference: E - (AQ)

XMOVEI

415

DMOVE

120

(EEE+1)
= (ACAAC+]D)

DMOVEM

124

(AC.AC+1)—~ (EE+1)

DMOVN

121

—(E.E+1
—> (ACAC+1)
)

DMOVNM

125

—(AC.AC+1)~ (EE+1)

BLT

251

Move ER = (A(‘)R + 1 words starting with ((A(’)L )~ ((A(‘)R )

XBLT

020

Move (AC) words

If local AC reference: 1,E = (AC)

If (AC) > 0: start with (AC+1)) = ((AC+2)) and go up
If (AC) < 0: start with ((AC+HD) - 1)Y= ((AC+2) - D and go down

Half Word Data Transmission
HLL

500

(E). = (AC),

HLLZ

510

HLLI

501

HLLZI

511

HLLM

502

(AC), ~ (E)

HLLZM

512

HLLS

503

IfAC#0: (E)>(AC)

HLLZS

513

(AC),

(Ex,0-> (AC)

0~ (AC)
(AC)y 0~ (E)

0~ (E)
If AC # 0:

(E) > (AC)

HLLO

520

(E).,777777 -~ (AC)

HLLE

530

HLLOI

521

0,777777 - (AC)

HLLEI

531

0 - (AC)

"HLLOM

522

(AC).,777777 - (E)

HLLEM

532

(AC).,[(AC)y X 777777} = (E)

HLLOS

523

777777 - (E)

HLLES

533

If AC # 0:

(E) = (AC)

(Ex. ~ (AC)

HLRZ

HLRI

545

0~ (AC)x

HLRM

546

(AC), = (E)g

HLRS

547

(Ex. ~ (E)g
IfAC#0:

(E) = (AC)

(E)o X 777777 - (E)x
If AC #0:

544

HLR

(E),[(E)y X 777777] = (AC)

(E)~ (AC)

554

0,(E).
— (AC)

HLRZI

555

0 - (AC)

HLRZM

556

0,(AC),
~ (E)

HLRZS

557

0.(E),~ (E)
IfAC# 0.

(E)—~>(AC)

GEN.

INFO.

-35«

HLRO

564

HLROI

565

HLROM

777777 (E). = (AC)
777777,0 ~ (AC)
777777 (AC), ~ (E)
777777 (E)y. = (E)
If AC#0: (E)~ (AC)

HLRE
HLREI
HLREM
HLRES

574 [(E) X 7777771
(E). ~ (AC)
575 0-(AC)
576 [(AC), X 777777}
(AC).~ (E)
577 [(E)} X 777777]
(E)}. ~ (E)
If AC # 0: (E)— (AC)

HLROS

567

HRR

540

(E) = (AC)

HRRZ

550

0(E)s
= (AC)

HRRI

541

E - (AC)

HRRZI

551

0,E-(AC)

HRRM

542

(AC) = (E)n

HRRZM

552

0(AC)g
~ (E)

HRRS

543

If AC #0: (E)~ (AC)

HRRZS

553

0-(E)

HRRO

560

777777 (E)g = (AC)

HRRE

570

[(E)g X 7777771 (E)x = (AC)

HRROI

561

777777,E > (AC)

HRREI

571

[E;s X 7777771 E - (AC)

HRROM

562

777777,(AC)g ~ (E)

HRREM

572

[(AC),s X 777777] (AC)g = (E)

HRROS

563

777777 - (E)

HRRES

573

(E) X 777777 = (E).

HRL

504

(E)g — (AC),

HRLZ

514

HRLI

505

E > (AC)

HRLZI

515

E,0-(AC)

HRLM

506

(AC)p = (E),

HRLZM

516

(AC),0~ (E)

HRLS

507

(E)g = (E)

HRLZS

517

If AC#0:
(E)~ (AC)

If AC #0: (E)~ (AC)

If AC#0:

If AC # 0: (E) -~ (AC)
(E)x,0~ (AC)

(E),0~
(E)

(E)—~ (AC)

IfFAC#0: (E)—~> (ACO)

HRLO

524

(E),777777 = (AC)

HRLE

534

HRLOI

525

E,777777 - (AC)

HRLEI

535

EJ[E;§ X 777777] - (AC)

HRLOM

526

(AC)\,777777 > (E)

HRLEM

536

(ACR,[(AC)3 X 777777)
=~ (E)

HRLOS

527

(BE)g,777777 — (E)

HRLES

537

If AC#0:

XHLLI

501

(Eg,[(E)s X 777777] = (AC)

(ER,[(E)g X 777777] = (E)

If AC#0:

(E) = (AC)

(E)—~(AO)

E, > (AC),

Byte Manipulation
7
{

use present poimer} and

LoaD Byte into ac

Increment pointer

DePosit Byte in memory

Increment
ADJust

IBP

133

AC=0

} Byte Pointer

Linear operations on pointer in E or E.E+1

P~S>20:P-S—~>P

IfP-S<0:

ADIJBP

133

Y+1->Y

36-S~>P

Array operations on pointer in

AC#0

Let

E or EJE+1

36-P
A = REMAINDER — ¢

I[fS>36-A:
IfS=0:

1| >

NODIVIDE

(E)~> (AO) or (E,E+1) > (ACAC+1)

If 0<S <36 -A: make copy Cof (E)or (EE+1)

Compute (AC) +[

36-P

]= QX BYTESWORD +R

1<
R < BYTES/WORD =l“""§"‘] + [f]
36-P

v{c}+ Q-v{c}

36 - RXS - 4 > P{C}
C—-> (AQ)or (AC,AC+1)
LDB

135

BYTE IN ((E)) = (ACQ)

DPB

137

BYTEIN

ILDB

134

IBPand LDB

IDPB

136

IBPand

(AC)—
DPB

ByTEIN

((E))

GEN.

INFO.
-36~

Boolean

Zeros

Ones

SET 10 mmow
Complement of Ac
Complement of Memory

AND

| .. ] acImmediate

with Complement of Ac

inclusive OR} with Complement of Memory [ |
Complements of Both

Memory

Both

Inclusive OR
eXclusive OR
EQuiValence

SETZ

400

0-(AC)

SETO

474

737777777777 = (AC)

SETZI

401

0-(AO)

SETOI

475 =

777797777777 = (AC)

SETZM

402

0->(E)

SETOM

476

777777777777 = (E)

0->(AC) (E)

SETOB

477

7777777771777 = (AC) (E)

SETZB
SETA

424

(AC) = (AC) [no-op]

SETCA

450

~(AC) > (AO)

SETAI

425

(AC) — (AC) [no-op]

SETCAI

451

~(AC) > (AQ)

SETAM

426

(AC) ~ (E)

SETCAM

452

~ (AC) — (E)

SETAB

427

(AC) > (E)

SETCAB

453

~ (AC) = (AC) (E)

SETM

414

(E)—> (AC)

SETCM

460

~(E)—> (AC)

- SETMI

415

0.E - (AC)

SETCMI

461

~ {0,E] = (AC)

SETMM

416

(E) = (E) [no-op]

SETCMM

462

~(E)—>(E)

SETMB

417

(E) = (AC) (E)

SETCMB - 463

~(E) > (AC) (E)

AND

404

(AC) A (E) = (AC)

ANDCA

410

~(AC) A (E) = (AC)

ANDI

405

(AC) A 0E = (AQ)

ANDCAI

411

~(AC) A O,E— (AC)

ANDM

406

(AC) A (E)
> (E)

ANDCAM

412

~(AC) AN (E)=(E)

ANDB

407

(AC) A (E) > (AC) (E)

ANDCAB -

413

~(AC) A (E) = (AC) (E)

ANDCM

420

(ACYA ~ (E) > (AC)

ANDCB

440

~(AC) A ~(E) = (AC)

ANDCMI

421

(ACO)A ~[0,E] » (AO)

ANDCBI

441

~ (AC) A ~ {0,E] = (AC)

ANDCMM

422

(AC) A ~(E)—= (E)

ANDCBM

442

~(AC) A ~(E)—~ (E)

ANDCMB

423

(AC)A ~(E)=>(AC) (E)

ANDCBB = 443

~(AC) A ~(E) = (AC) (E)

IOR

434

(AC) v (E) =~ (AC)

ORCA

454

~(AC) Vv (E) > (AC)

IORI

435

(AC) v O?E - (AC)

ORCAI

455

~(AC) vV 0,.E = (AQ)

IORM

436

(AC)v (E)~> (E)

ORCAM

456

~(AC) v (E)= (E)

IORB

437

(AC) v (E)
> (AC) (E)

ORCAB

457

~(AC) Vv (E)
= (AC) (E)

ORCM

464

(AC)v ~(E)—= (AO)

ORCB

470

~(AC)v ~(E) > (AO)

ORCMI

465

(AC)v ~ [0,E] = (AC)

ORCBI

471

~(AC).v ~ [0,E] = (AC)

ORCMM

466

(AC)v ~(E)— (E)

ORCBM

472

~(AC)v ~(E)—>(E)

ORCMB

467

(AC) v ~ (E) > (AC) (E)

ORCBB

473

~(AC) v ~(E)~> (AC) (E)

XOR

430

(AC) ¥ (E) > (AC)

EQV

444

~ [(AC) ¥ (E)] — (AQ)

XORI

431

(AO) v 0,.E » (AC)

EQVI

445

~ [(AC)v¥ 0,E] = (AO)

XORM

432

(AC) % (E)=(E)

EQVM

446

~ [(AC) ¥ (E)] = (E)

XORB

433

(AC) ¥ (E) > (AC) (E)

EQVB

447

~ [(AC) ¥ (E)] = (AC) (E)

GEN.

INFO.

-37-

Logical Testing and Modification

Test ac

with Direct mask

No modification

with Swapped mask

set masked bits to Zeros

Right with £

set masked bits to Ones

Left with £

Complement masked bits

never

if all masked bits Equal 0

and skip if Not all masked bits equal 0
Always

No-op

TLN

601

No-op

TRN

600

TLNE

603

If (ACyANE=0: skip

TRNE

602

TLNA

605

Skip

TRNA

604

TLNN

607

If (AC). A E#0: skip

TRNN

606

TRZ

620

(AC)kx A~ E-=(AC)R

TRZE

622

If(AC)x

TLZ

621

(AC)

TLZE

623

If (AC). AE =0: skip

(ACy,

A~E—(AC)y,

625

(AC), A~ E—>(AC),

TLZN

627

If (AC). A E#0: skip

TLC

641

(AC) ¥ E—~ (AC),

TLCE

643

If (AC),ANE = 0: skip
VE = (AC)y,
(AC).

TLCA

645

(AC). v E~> (AC)

TLCN

647

If (AC),

(AC)

624

(AC)RA~E->(AQ)R

TRZN

626

If(AC)x

TRC

640

(AC)R vV E - (AOR

TRCE

642

If (AC)x

TRCA

644

TRCN

646

TRO

660

661

663

If (AC)y. AN E =0: skip
(AC)L,VE—=> (AC)y

(AC)R V E— (AC)

TROE

662

If (A

TLOA

665

(AC), VE - (AC)

TLON

667

If (AC), A E #0: skip

TDN

610

TDNE
TDNA

AE =0: skip

(ACx ¥ E = (AO)
skip

(AC)r ¥ E - (AC)
~If (AC)R

skip

AEF0: skip

(AC)r ¥ E = (AQO)

(AC), ¥ E—~ (AC),

TLOE

skip

ANEF0: skip

(AC)r A~ E = (AC)

AE #0: skip

TLO

AE=0: skip

A~ E > (ACKk

skip TRZA

A~ E - (AC)y

(AC),VE—- (AC)y

If(ACR AE #0: skip

(ACRr

A~ E— (AC)

TLZA

If(AC)R AE =0: skip

- Skip

AE =01 skip

(AC) V E = (AC)y
ship

TROA

664

(AC)R VE = (AC)K

TRON

666

If (AC)x

No-op

TSN

611

No-op

612

If (ACO)A (E) = 0: skip

TSNE

613

If(AC)A (E)s=0: skip

614

Skip

TSNA

615

Skip

TDNN

616

If (AC) A (E) # 0: skip

TSNN

617

0: skip
If (ACYAN(E)g#

TDZ

630

(AC)A ~ (E) = (AO)

TSZ

631

(AC)A ~ (E)s~> (AC)

TDZE

632

If (AC) A(E) = 0: skip

TSZE

633

If(AC)N(E)s=0: skip

TDZA

634

(AC) A~ (E) ~ (AC)

TSZA

635

(AOA~(E)s— (AC)

TDZN

636

If (AC)A(E) #0: skip

TSZN

637

If(AC)A (E)s #0: skip

TDC

650

(AC) ¥ (E) ~ (AC)

TSC

651

(ACYw (E)g— (AC)

TDCE

652

If (AC)A(E) = 0: skip

TSCE

653

If(AC)A(E)s=0: skip

TDCA

654

(AC)¥ (E) > (AC)

TSCA

655

(AC)¥ (E)g — (AC)

TDCN

656

If (AC) A (E) # 0: skip

TSCN

657

If (ACOYN (E)s#0: skip

TDO

670

(AQ)V (E)—~ (AC)

TSO

671

= (AC)
(AC)V (E)s

TDOE

672

If (AC)A (E) = 0: skip

TSOE

673

(E)g =0: skip
If(ACYA

TDOA

674

(AQ) Vv (E) > (AC)

TSOA

675

(AC)V (E)g—> (AC)

TDON

676

If (ACOYA(E) #0: skip

TSON

677

skip

(AC)R V E »> (AC)

(AC). VE > (AC)y

> (AC)
(AC)A ~ (E)s

(AC) A~ (E) = (AC)
skip

skip

> (AC)
(ACYA ~ (E)s

(AC) A ~(E) = (AC)

= (AC)
(AC)¥ (E)s

(AC) ¥ (E) = (AC)

skip

(AC) ¥ (E)g—~ (AO)

(AC) ¥ (E) > (AC)

(AO)V (E)g~ (AC)

(AC)v (E) » (AO)

(AQ)V (E) > (AC)

AE#F0: skip

skip

- If (AC)AN (E)g #.0: skip
(AC)V (E)s = (AC)

GEN.

INFO.
-38~

Arithmetic Testing

never

SKIP it memory}
JUMP if ac

Less

Equal

Add One to

l memory and Skip

Subtract One from § { ac and Jump

) Less or Equal

) Always

Immediate
Compare A( with
Memory} and skip
if a¢

Greater

Greater or Equal
Not equal

Add One 10 Both halves of ac and Jump it POSI(IYC

Negative

AOBJP

252

AOBIJN

253

(AQ)+1,1 > (AC)

(AG+1,1 > (AC)

If (AC)=>0: E— (PC)

If(AC)<0: E~ (PO)

CAl

300

No-op

CAM

310

CAIL

301

If (AC)<E: skip

CAML

311

If (AC) <(E): skip

CAIE

302

If(AC) = E: skip

CAME

312

If(AC) = (E): skip
If (AC) < (E): skip

No-op

CAILE

303

If(AC)<E: skip

CAMLE

313

CAIA

304

Skip

CAMA =

314

Skip

CAIGE

305

If(AC)=E: skip

"CAMGE

315

If (AC) = (E): skip
If (AC) #(E): skip

CAIN

306

If(AC)#+E: skip

CAMN

316

CAIG

307

'lf(AC) > E: skip

CAMG

317 If (AC) > (E): skip

JUMP

320

No-op

SKIP

330

JUMPL

321

If(AC)<0: E~ (PC)

SKIPL

331

IfAC#0: (E)~ (AC)

JUMPE

322

If(AC)=0:

SKIPE

332

IfAC#0: (E)- (AO

JUMPLE

323

If(AC)<O0: E- (PC)

SKIPLE

333

JUMPA

324

E~->(PC)

SKIPA

JUMPGE

325

If(AC)=0: E -~ (PO)

SKIPGE

335

JUMPN

326

If(AC)#0: E— (PO

SKIPN

336

IfAC#0: (E)- (AQ)

JUMPG

327

If(AC)>0: E- (PO)

SKIPG

337

IfAC#0: (E)= (AOQ)

AOJ

340

(AO)+1->(AO)

SOJ

360

AOJL

341

IfAC+#0: (E)—>(AO)
If (E)<O0:

E—~>(PO)

skip

If (E) = 0: skip

IfAC#0: (E)=>(AO)
If(E)<0: skip

334

IfAC#0:

(E)- (AQ)

Skip

IfAC+#0: (E)~ (AQ)
If (Ey=0: skip

If (E)#0: skip

If(E)> 0:

(AC) + 1 - (AC)
If (AC) <0:

AOJE

342

AOJLE

If (AC) = 0:

343

SOJL

361

SOJE -

362

SOJLE

363

SOJA

364

E- (PO)

(AC) + 1 - (AO

344

(AC)+ 1-(AQ)

345

(AO) + 1 - (AO)

SOJGE

365

E = (PO)

AOJN

346

AOIJG

347

(AC) + 1 » (AQ)

AOS

350

(BE)+1->(E)

AOSL

351

(AO)+ 1-(AO)

366

SOJG

367

(AC) - 1= (AO)

SOS

370

(E)—-1~>(E)

SOSL

371

If (AC)>0:

If AC#0:

E -~ (PO

E~ (PO

(E)— (AO)

(EYy - 1 =>(E)

IfAC#0: (E)
= (AO)

If AC#0:

If (E) <0: skip

If (EYy<O0: skip

(E)+1~(E)
If AC#0:

SOSE

372

(E)
> (AQ)

(E)+1-(E)
If AC#0:

(E)— (AC)

If (E) < 0: skip

(E)—> (AO)

(E)—-1 »(E)
If AC#0:

If(EY=0: skip

353

. (AC) -~ 1-(AQO)
If (AC) #0:

If (ACY#
0: (E)~ (AO)

AOSLE

E - (PO)

SOJN

If (AC)
> 0: E = (PO)

B+ 1->(E)

(AC) - 1 = (AO)

If (AC)=0:

If (AC)#
0: E -~ (PO)

352

(AC)-1-(AQ)

E - (PC)

If (AC)=0:

AOSE

E > (PC)

(AC) - 1 - (AO)
If(AC)<
0: E— (PO)

E- (PC)

AOJGE

E - (PO)

(AO)-1-(AO
If (AC) = 0:

If (AC)
K 0: E-~ (PO)
AOJA

(AC) - 1 » (AO)
If (AC)<0:

E - (PC)

(AC) + 1 - (AQ)

skip

(AO) - 1-(AO

(E)—>(AO)

If(E) =0: skip

SOSLE

373

{(E) — 1 = (E)
If AC+0:

(E)—»> (A

I (EY<<0: skip

GEN.

INFO.

-39~

AOSA

AOSGE

AOSN

354

355

356

(E) - 1—>(E)

374

SOSA

(E)+1—>(E)

If AC#0: (E)— (AC)

If
AC #0:

Skip

SOSGE

(E) +1-(E)

(EY — 1 > (E)

375

If AC#0: (E)~ (AO)

If AC #0: (E)—~ (AC)

If (E) = 0: skip

I[f(E) =2 0: skip

(E) — 1 = (E)

376

SOSN

(E) + 1> (E)

IfAC#0:

If AC #0: (E) = (AO)

(E) > (AC)

If (E) #0:

If (E) # 0: skip

AOSG

357

(E)—~> (AC)

skip

(E) — 1 = (E)

377

SOSG

(E)+ 1-(E)

If AC#0: (E)—> (AC)

If AC #0: (E) > (AQ)

If (E) > 0: skip

If(E) > 0: skip

Shift and Rotate

Arithmetic SHift | (

{ Combined

:'{Oog,l;::esmfl

ASH

240

(AC) X 22> (AC)

ASHC

244

(AC,AC+1) X 22> (AC,AC+1)

ROT

241

Rotate (AC) E places

ROTC

245

Rotate (AC,AC+1) E places

LSH

242

Shift (AC) E places

LSHC

246

Shift (AC,AC+1) E places

FIXED AND FLOATING POINT ARITHMETIC
ADD

SUBtract
MUL:tiply

Integer MULtiply

Integer DIVide

‘

DIVide

Floating AdD

l to Memory
Immediate

and Roundd 1 1° Both
~

Long

Floating SuBtract
Floating MultiPly
Floating DiVide

to Memory
to Both

Floating SCale

Double Floating Negate
Unnormalized Floating Add
FIX

FIX and Round
FLoaT and Round

Double ADD
Double SUB tract
Double MU Ltiply

Double D1Vide
Double Floating AdD
Double Floating SuBtract
Double Floating MultiPly
Double Floating DiVide

Fixed Point Arithmetic

(AC) — (E)— (AO)

ADD

270

(AC) + (E) > (AC)

SUB

274

ADDI

271

(AC) + 0,E ~ (AC)

SUBI

275

(AC) - 0,E - (AC)

ADDM

272

SUBM

276

(AC) — (E) = (E)

ADDB

273

(AC) + (E) ~ (E)
(AC) + (E) = (AQ) (B)

SUBB

277

(AC) — (E) = (AC) (E)

IMUL

220

(AC) X (E) =~ (AC)*

MUL

224

(AC) X (E) = (AC,AC+1)

IMULI

221

(AC) X 0,E = (AO)*

MULI

225

(AC) X 0,E = (AC,AC+1)

IMULM

222

(AC) X (E) > (E)*

MULM

226

(AC) X (E)—= (E)t

IMULB

223

(AC) X (E) = (AC) (E)*

MULB

227

(AC) X (E) = (AC,AC+1) (E)

IDIV

230

(AC) + (E) > (AC)
REMAINDER —> (AC+1)

DIV

234

(AC,AC+1) + (E) ~> (AC)
REMAINDER = (AC+1)

IDIVI

231

(AC) ~ 0,E = (AC)

DIVI

235

(AC,AC+1) ¥ 0,E = (AC)

IDIVM

232

(AC) + (E) > (E)

DIVM

236

(AC,AC+1) ~ (E)— (E)

IDIVB

233

(AC) + (E) > (AC) (E)

DIVB

237

REMAINDER —~ (AC+1)

REMAINDER —> (AC+1)

REMAINDER = (AC+1)

(AC,AC+1) *+ (E} = (AC) (E)
- REMAINDEE —* { AC+11}

GEN.

INFO.
DADD

=40~

114

(AC,AC+1) + (E,E+1) > (AC,AC+1)

DSUB

(ACACHD) - (E,E+1) > (AC,ACH])

DMUL

116

(AC,AC+1) X (E,E+1) > (AC-AC+3)

117

(AC-AC+3) + (E,E+1) > (AC,AC+])

DDIV

REMAINDER = (AC+2,AC+3)

*The high order word of the product is discarded.

1The low order word of the product is discarded.

Floating Point Arithmetic
FAD

140

(AC) + (E) = (AQ)

‘FADR

144

(AC) + (E) = (AO)

FADL

141

(AQ) + (E) » (AC,AC+1)

FADRI

145

FADM

(AQ)+ E.,O = (AC)

142

(AO)+(E)~»(E)

FADRM

146

(AC)+ (E)— (E)

FADB

143

(AC) + (E) = (AC) (B)

FADRB

147

(AC)+ (E)— (AC) (E)

FSB

150

(AC) — (E)~> (AO)

FSBR

154

(AC) —(E) - (AC)

FSBL

151

(AC) - (E) > (AC,AC+1)

FSBRI

155

(AC)-E, 0~ (AO)

FSBM

152

(AC) - (E)~> (E)

FSBRM

156

(AC) - (E)—~>(E)

FSBB

153

(AC) - (E) > (AC) (B)

FSBRB

157

FMP

160

(AC) X (E)— (AQ)

FMPR

164

FMPL

161

(AC) X (E)—> (AC,AC+D)

FMPRI

165

(AQC) X E,O — (AC)

FMPM

162

(AC) X (E)—= (E)

FMPRM

166

(AC) X (E)~ (E)

FMPB

163

(AC) X (E) -~ (AC) (E)

FMPRB

167

(AC) X (E) ~ (AC) (E)

FDV

170

(AC) ~ (E) » (AQ)

FDVR

174

(AC) ~ (E) = (AO)

171

(AC) ~ (E) > (AO)

FDVRI

175

(AC) ~ E,0 —» (AO)

FDVL
\

(AC) = (E) = (AC) (E)

-~ (AC) X (E) = (AC)

REMAINDER > (AC+1)

FDVM

172

(AC) ~(E)=>(E)

FDVRM

176

(AC) ~ (E) = (E)

FDVB

173

(AC) ~ (E) > (AC)(E)

FDVRB

177

(AC) ~ (E) = (AC) (E)

FI1X

122

UFA

130

(AOC) + (E) > (ACH+1) without normalization

DFN

131

- (AC,E)—>(ACE)

FSC

132

(AC) X 22> (AQ)

FLTR

127

(E) floated, rounded — (AC)

(E) fixed = (AC)
DFAD

110

FIXR

126

(E) fixed, rounded — (AC)

(ACLAC+1)
(EEE+1) = (ACAC+1)
+

DFSB

111

(ACAC+1) —(EEE+D)
~ (AC.AC+1)

DFMP

112

(AC.AAC+1) X (EEE+1) = (AC.AC+1)

DFDV

113

(AC,AC+1
+ (E.E+1) = (AC.AC+1)
)

STACK
PUSH} ‘ ~

POP

and Jump

ADJust Stack Pointer

PUSH

261

POP

262

PUSHJ

260

IfPCL =0 or (AC)o,m.7 <0:

(AO)+ l‘,l - (AC)

IfPCL #0and (AC)
15 ~v:

(AQ)+1-(AC)

(E) ->_((AC)R )

(E)~ ((AC))

IfPC =0 or (AQ),
., <O

((AQ)) »(E)

(AC)-1,1~ (AC)

IfPC

((AC)) — (E)

(AC) - 1 - (AC)

#0 and (AC),
., >0:

If PCL =90:

(AC) + 1,1 = (AC)

FLAGS, PC+] — ((AC,)R)

IFPC #0and (AC) 6,7 <0: (AC)+1,1>(AC)
IfPC, #0and

POPJ

ADIJSP

263

105

(AC),,

. >0:

0,617

(AQ)+1-(AC)

PCH = ((AC),)
PC+l > ((AC)

E~ (PO)

IfPC,_=0:

((AC)), = (PO)

IfPC, #0and

(AC),,,,

IfPC, #0and

(AC) 0,6-17'> 0:

IfPC =0 or

(AQ),
;, <O: (AQ)+[#] Ep, E, = (AC)

<0:

(AQ)- 1,1 > (AC)
((AQ)
)=(PC)
((AQ))

= (PO

IfPC, # 0and (AC) 0,6-17 >0: (AC)+ [£] E; > (AQ)

(AC)-1,1-(AC)

AO -1- (AO

GEN.

INFO.

-4]1-

Program Control

(1o SubRoutine
and Save Pc
and Save Ac
and Restore Ac
if Find First One
on Flag and CLear it
on OVerflow (JECL 10,)
Jump
on CaRrY 0 (JFCL 4
on CaRrY 1 (JECL 2)
on CaRrY (JFECL 6)

on Floating OVerflow . (JFCL 1)
and ReSTore
and ReSTore Flags (JRST. )
and ENable pt level (JRST 12))

(JRST 4,

HALT

PORTAL

(JRST 1))

e Xtended Jump and ReSTore Flags (JRST 5.)

eXtended Jump and ENable r1 level (JRST 6,)
e Xtended PC Word (JRST 7))
(JRST 14,)

Save Flags in Memory
e XeCuTe

MAP

XCT

256

Execute (E)

JFFO

243

If(AC)=0: 0> (AC+ 1)

If (AC) # 0: E = (PC) (see page 2-63)
255

If AC A FLAGs + 0

JRST

25400

E - (PC)

PORTAL

25404

0" puBLIC

25420

E - (PC)

JFCL

JRSTF
HALT

E—~(PC)

E- (PC)

25410 (X),, or (Y), — FLAGS
stop

XJRSTF

25424 (E)L_, rFLacs . (E+1) > (PC)

XJEN

25430 Dismiss »1 (E)L - rLags

XPCW

25434

JEN

~ AC A FLAGS = FLAGS

E = (PC)

= (PC)
(E+1)

E— (PC)

(X)L or (Y)L —> FLAGS

0= (E)

SFM

rFLaGs,

JSR

264

If PC, =0:

FLags, PC, +1>(E)

If PC, #0:

PC+1 = (E)

E - (PC)
PC+1 - (AQ)
E+1 = (PC)
Ep,PCp+1 = (AC)

If PCL =0:

~ E+1—> (PO)

E+1 = (PC)

FLacs, PCy +1 = (AC)

JSP

265

JSA

266

IfPC, #0:
(AC) = (E)

JRA

267

((AC);) = (AC)

MAP

257

PHYSICAL MAP DATA = (AC)

(E+43) = (PC)

(E+2), - FLAGS

PC+1 = (E+1) =

FLAGs, 0~ (E)

25450 Dismiss p1

E - (PC)

Extended Instructions
Left Justified

Right Justified
MOVe String Offset
Translated
Less
Equal

CoMPare Strings and skip if (lfise:);Equal
Greater or Equal
Not equal

ConVert

Decimal to Binary }
Binary to Decimal

Offset
Translated

EDIT string

CMPSL - 001
002
CMPSE
CMPSLE 003
004
EDIT
CMPSGE 005
CMPSN 006

CVTDBO
CVTDBT CVTDBO
CVTDBT
MOVSO
MOVST

010
011
012
013
014
015

MOVSRJ

017

MOVSLJ

CMPSG - 007

NOTE

016

~ Refer to the DECsystem-10/DECSYSTEM-20
Hardware Reference Manual, Volume I, for a
description of the Extended Instructions.

GEN.

INFO.
-4 2=

Cache

CCA 014

All sweeps initially set Sweep Busy, and at termination they clear Sweep Busy and set Sweep Done.
SWPIA

70144

Invalidate all pages

* SWPIO

70164

SWPVA

70150

Validate all pages

* SWPVO

70170

Validate page E

SWPUA

70154

Unload all pages

* SWPUO

70174

Unload page E

‘

Invalidate page E

In-out

DATA }
BLocK

‘In

CONditions

Out

in and Skip ’flall masked bits Zero
some masked bit One

CONO

70020

E - coMMaND

CONI

70024

status = (E)

DATAO

70014

(E) @ pata

BLKO

70010

(E)+ 1,1 > (E)

((E)g)~> parta

‘BLKI

70000

(E)+1,1>(E)

pata

CONSZ

70030

Ifstatusg A E = 0: skip

CONSO

70034

Ifstatusg A

DATAI

70004

pata— (E)

E#0: skip

If(E), # 0: skip

> ((E),) If(E), #0: skip

ALGEBRAIC REPRESENTATION

The accumulator address in bits 9-12 of the instruction word

AC+N

The address ¥ greater than AC, except that accumulator addresses wrap around
17, e.g., AC+3is 1 if AC is 16.

from

The result of the effective address calculation. When E is an address it has
the number
of bits appropriate to such use - depending on the type of processor, whether local
or
global, etc. E is elghteen bits unsigned when used as a half word operand, mask or output conditions; nine bits signed when used as a scale factor or shift number;
and

eighteen bits signed when used as an offset. For any signed quantity, the sign is always

bit 18.

The in-section part of E (the right eighteen bits).

The section-number part of E (those bits, if any, at the left of bit 18).

E+N

The address N greater than E, with a wraparound, where appropriate, from an insection value of 777777 without changing the section number.

The 30-bit or 18-bit program counter; the symbol also represents the contents of PC
when used as the source of an address.

PC+1

The address produced by adding 1 to thein-section part of PC with a wraparound from
777777 (the section number does not change).

X))

The word contained in register X.

(XN

The left half of (X).

(Ngr

The right half of (X).

(X)s

The word contained in X with its left and right halves swapped.

The value of bit n of the quantity A4

A 36-bit word with the 18-bit quaniity A in its left half and the 18-bit quantity B in its

(X.Y)

The contents of registers X and Y concatenated into a double word operand.

(X-Y)

The contents of registers X to Y concatenated into a multiword operand.

(X))

The word contained in the register addressed by (X), i.e., addressed by the word in regis-

right half (either

4 or B may be 0).

ter X.

*With

MCA25

SWPTO,
pages

installed

SWPVO,
will

and

cache

SWPUO

swept

when

data

will
these

sweep

two

for

one

pages

instructions

are

page

(both

instruction,

even

executed).

and

odd

GEN.

INFO.

-43-

A- B

The quantity A replaces the quantity B (4 and B may be half words, full words or
double words). For example,

(AC) + (E) - (AC)

means the word in accumulator AC plus the word in memory location E replaces the
word in AC.

(AC) (E)

The word in AC and the word in E.

AV ¥~

The Boolean operators AND, inclusive OR, exclusive OR, and complement (logical

+—X=+||

or subtraction, multiplication, division,
The arithmetic operators for addition, negation

negation).

and absolute value (magnitude).

Square brackets are used occasionally for grouping, but when they enclose an arithmetic computation they represent the ‘‘largest integer contained in” the enclosed quantity. With respect to the
values of their terms, the equations for a given instruction are in chronological order: e.g.. in the pair
of equations

(AC) + 1 - (AC)
If (AC) = 0: E - (PC)

the quantity tested in the second equation is the word in AC after it has been incremented by one.

"NID

PROCESS

OuUTPUT

SEVEN STEPS OF FAULT ANALYSIS
THREE METHODS OF

FIVE METHODS OF

INFORMATION GATHERING

STATE THE PROBLEM.

OBSERVATION

OPERATION —

NOoO O~ WN

QUERY —

(SYMPTOMS AND CONDITIONS)

WHAT IS HAPPENING THAT SHOULDN'T?

WHAT ISN'T HAPPENING THAT SHOULD?

UNDER WHAT CONDITIONS?

RESTORATION

— REPLACE FRU

HYPOTHESIZE MOST PROBABLE CAUSE.
DESIGN AN EXPERIMENT OR TEST.
PREDICT THE RESULTS

CONDUCT THE EXPERIMENT.
EVALUATE THE RESULTS.

CORRECT THE FAULT OR

—— ADJUST OR ALIGN FRU
>

REPAIR FRU

—— CORRECT ENVIRONMENT
—— INSTALL FCO

REPEAT STEPS 1 THROUGH 7.
FEEDBACK

TWO METHODS OF CONFIRMATION

RE-INSERT FAULT OR
ESTABLISH TIME-WINDOW

MR-2502

*OJdNI

INPUT

GEN.
-45-

NOTES

INFO.

GEN. INFO.

GATHERING

KL10

Prior

gathering

feature

must

Procedure

TOPS-20

SYSTEM

lists

auto-reload

for

Procedure

system

the

steps

error

information,

all

1lists

necessary

(release

1lists

error

INFORMATION

system

the

auto-reload

disabled.

and TOPS-10

Procedure

ERROR

KL10

603

disable

auto-reload

additional

TOPS-10
the

steps
necessary
operating systems.

steps

for

1later).

necessary

gather

disable

essential

KL10

information.

Procedure

Disabling

TOPS-10/603
Step

|Command

PAR>SET

Auto-Reload
and Later)

Response

and

Comments

Enter
CONSOLE

(TOPS-20

PROGRAMERKCR>

PARSER

Request

command mode

PROGRAMMER

mode

privileges

CONSOLE

MODE:

PAR>SET

RELOAD

PROGRAMMER

RELOADKCR>

ENABLE:

OFF

PAR>QUIT<CR>

response

PARSER

Disable

auto-reload
response

PARSER

Exit

PARSER.

command

Procedure 2
Step | Command

Disabling Auto-Reload

Response

.R WHEEL<KCR>
Setting Wheel

Capability

used.

the

CTY

(TOPS-10 Only)

Control

command

mode.

Request
This step

.R FILDDT<CR>

Run FILDDT

FILE:

Load

the

symbol

FILE:/M/P<CR>

Enter

TOPS-20

1,2
privileges,
is not necessary

Comments

SYSTEM/S<CR>

Return

mode.

operating

system's

table.

Enable,

examining

patching

the

and

operating

system.

*SH<CR>

Set

DDT

printout

mode

must

half-word.

*DEBUGFE /XYXXXX, ,XXXXXX

Bit

set

disable

That
1is,
digit
(Y)
4,
5,
6,
type

this

word

auto-reload.

the
second
octal
must be either
a
or
7.
If
it is,

carriage

not,

changing

return.

retype

the

second

line
octal

digit.
From

3
For

7
example,

127413,,371520

would become;
167413, ,371520<CR>

Control-Zz

Exit

return

TOPS-10

mode.

FILDDT

and

command

INFO.

GEN.
-47~-

Procedure

Gathering

Step | PARSER Command

TN\

SET CON MAINT<KCR>

System

Error

Status

Comments

Enter PARSER,

Mode

Maintenance

Request

privileges.

EXAMINE DTE-20<CR>

Get

MCR BOO<KCR>

Load BOO.TSK file.

current DTE20 status.

DBOOTLCR>

Direct

start

and

load

BOO

KLDCP.

Step | KLDCP Command

Comments

EE 174434<CR>

Examine DTE STATUS register.

EE 174430<CR>

Examine DTE DIAG 1 register.

DE 174432:100<CR>

Reset the DTE,

FX O0<KCR>

Turn off the clock.

ALL<CR>

Print all CRAM and registers

FR 110<CR>

Read APR.

'FR 100,177<CR>

Read all diagnostic functions.

FX 1,FX 10,PC<KCR>

Start

FX 12,PC,FX 12,PCLKCR>

Continue

get

PC.

(momentarily)

and

get

this

Perform

again.

several

and get PC,

(momentarily)

continue

clock,

the

stop

clock,

the

step

times.

Examine the current CRAM location.

EC<KCR>

the

1is

location

the

Determine

halt loop location for the version
of microcode

by the

system.

procedure

cannot

in use

If
I1f it is, proceed to step 19.
The KL10 is hung
it is not, stop.
the
and
state
unknown
an
in
the

remainder
be

executed.

Turn on the clock.

FX 1<CR>

EM 16,17<CR>

Examine
examine

hung

Jumper

4F20E1

ground.

KLDCP

reset

and

hold

700400

Remove

17,

with

BLKI APR(APRID)

24,

procedure.

and print.

EX 700240
EX 701240

17,EM 17<CR>

CONI

701040

17,EM 17<CR>

DATAI

17,EM 17<CR>

17<CR>

and

steps

720240

machine

jumper.

the

PAG and print.
PAG and

print.

BLKI PI (RDERA) and print.
CONI

DTE

1is

ERA valid.

CONI APR and print.

17,EM 17<CR>

Then

KL10

steps.

EX 700000 17,EM 17<CR>

EX 700400 17,EM 17<CR>

21.

state.

the

following

step

fails,

the

continue

proceed

unknown

the

17.

and

ACs

works,

If the examine

(STATUS)

and print.

then

GEN.

INFO.
-48—

Procedure

Step

|KLDCP

Gathering

Command

System

(Cont)

AC BLK 7<CR>

(Cont)

XXXxxx500

PAGE

FAIL

xxxxx501

PAGE

FAIL

XXxxx502

PAGE

FAIL

BLK

WORD

and

FLAGS

Select microcode AC block 7.

0, 2<CR>

Examine
ACO0

Status

(Cont)

xxXxxx500,xxxxx502<CR> | Examine PAGE FAIL location.
Where
XXXXX
equals
bits
<23:35>
of
the
DATAI PAG
(UBR)
refer to step 13.

Error

Comments

the

block.

data

for

PAGE

ACl

= ARX

data

for

AC2

I/0

PAGE

FAIL

block

O0<CR>

Select

FAIL

PAGE

FAIL

word

INTERNAL MEMORY STATUS
28

16:0<CR>

700500

16:1<CR>

700500

Set
up
for
controller 0)

16,EM

17<CR>

Execute

16,EM

17<CR>

MEMORY

(DMA)

DM 16:100000

Execute

SBDIAGl
steps

700500

754240

controller

E+1.
24

the

BLKO

deposited

word

(SBDIAGI,

E+l.

through

bits

Set

17<CR>

(RH20)

17,EM

and

(SBDIAG

for

system

<00:04>

the

16.

STATUS

O<CR>

16,EM

CONTROLLER

and

incrementing

BLKO

controller

MASSBUS

BLKO

Repeat
each

SBDIAGO

Set
up
for
controller 0)

EXTERNAL

BLKO

Execute

17<CR>

CONI

Repeat
the

600:540001

701200

20000<CR>

200740

1000,EM

EBR

and

E+1.

print
28
by

select

RH20
on
the
1I/0

CONI

754640

755240

3
4

755640
756240

756640

7572490

for
each
changing

code.

system

RH20

STATUS
IF

SBDIAG

step

device

CHANNEL

(SBDIAG

STATUS

INTERNAL

4).

757640
EQUAL

540000<CR> | Set

Turn

17<CR> | Move

page

table

paging

CHAN

(INIT

(ERROR

CMD)

ACl7

and

ACl7

and

for

‘print.
40

200740

1001,EM

17<CR> | Move

200740

1002,EM

and

CHAN
print.

17<CR> | Move

CHAN
print.

Repeat

each
-

STATUS)

steps

channel

(STATUS)

:
32

through

the

CHAN

(1010-1012)

CHAN
CHAN

(1014-1016)

(1020-1022)

(1004-1006)

CHAN

(1024-1026)

CHAN

(1030-1032)

CHAN

(1034-1036)

system.

GEN.

INFO.

-49-

Gathering

STATUS

System Error

EBR

xxxxx000,xxxxx037

GREATER THAN

XXXXX

equals

(EBR)

PAG

step

the

<23:35>

refer

20.

CMD

= CHAN

INIT

CHAN

ERROR

CHAN

STATUS

xxxxx004

through

xXxxxXxx006

xxxxx010

through

xxxxx014
xxxxx020

through
through

xXxxx012 CHAN
xxxxx016 CHAN
xxXxx022 CHAN

xxxxx024

through
through
through

xxxxx026
xXxxxx032
xxxXxx036

xxxxx034

STATUS

)

CHAN

CHAN
CHAN
CHAN

STATUS

16:000400

O<KCR>

EX" 754140

754040

16:010400

754140

16<CR>

17,EM

Set

select

DATAO

reg

for

(DRCR)
.

16<CR>

17,EM

17<CR>

O<KCR>

DATAO RH

select

DATAI

Set

DATAO RH select

17<CR>

DATAI

754040

16:020400

754140

754040 17,EM 17<CR>

DATAI

16:140400 O<CR>

Set

754140

16<CR>
17,EM

O<CR>

754040

16:150400

754140

16<CR>

754040

17,EM

17<CR>

O0<KCR>

select

Set

reg

RH print

select

DATAO

reg

(DRERL)
.

reg

DATAO RH select

16<CR>

DATAO

reg
reg

(DRSR)
.

Where

locations.

bits

XXXxx000
xxxxx001
xxXxx002

XxXxx030

DEVICE

(Cont)

channel

Examine
CONI

RH20

Status

(Cont)

Comments

(Cont)

W N

INTERNAL CHANNEL
43

KLDCP Command

IO U

‘Procedure
Step

RH print

reg

DATAO

RH to

select

(DRER2)
.

DATAO

select

DATAI

Set

14.

reg

DATAO

1l4.

reg

select

(DRER3)

DATAO RH select reg 15.
17<CR>

DATAI

RH print

reg

15.

Repeat

steps

through

each

device

the controller

incrementing bits <15:17> of the
DATAO RH word deposited in AC 16.
for
52
through
37
steps
Repeat
each controller on the system by
changing the I/0 device select
code.

RH20
1

DATAQO
754540

DATAL
754440

755540
756140
756540
757140

755440
756040
756440
757040

3.
4
5
6
7

755140

757540

755040

757440

MEM

[

MH 10

PC/PG

EXT
MF20

ME§8

MEM
PG

SBUS ERR

DMA 20

CAUSES
APR INT

TTL
S/XBUS 0
CEERNRER

] .

PC | PG

ERROR

MICRO

CAUSES

.CONTROL

PLINT

CBUS

)

XLATOR

————

(CR 03)

TTL

ECL
SBUS

(DP3)

RH20

TTL
S/XBUS 1
L)

HALTS CLOCK (CLK 3}

MASSBUS
PC

*OdNI

INT

EE}(;--I
X

DEVICE

CRAM

PC
MA20

*NdD

(R
KBUS

(IR 3)

]

HALTS CLOCK (CLK 3)

DRAM

Y
1

CHANNEL

(MBO1, PAG 5)

MB PAR
APR INT

;

PAGE

TABLE
PC

STATUS

HALTS
CLOCK

(ccLs,

(CLK 3)

CCw4)

PG-PARITY GENERATOR

CAUSES
APR INT

PAGING

PAGE FAIL

CODE: 25

[

(FOR CONO, DATAO)

ADDER

FROM AR

ON KL

conTRoL | TRAP

PC
"

CHX 4}

CACHE
DIRECT

EBOX
DATA

PATHS

{PMA 4)

il,
AR

(SH1)

{7
ARX

I(sun

PAGE
FAIL

X I
L

| TRAP

CODE

36(AR),

(sHi) 37(ARX)

ECL EBUS

TTL

EBUS

A I

Lo
]

NOTES:

(EDP 4,
APR
3)

(PAG 5)
MEM

()

FAST
MEM

PC-PARITY CHECKER

—_——

- — —

]
MR-2418

F/S PROBE

CLK3 ERROR L

CLK3 FSERROR L

CLK3 ERROR H

CLK1 ODDBH

0 40176

E45

]10

10176

CLK3 ERROR
L
HOLDB

HOLD A H

C
EM1> CLK3 FS EN A H\ #400\

VvV

AAA

LAANA

HOLD B H

E45

CLK3 ERROR

10176

[14

|13

013

ELT) CLK3 FS EN B H\ #400\
C
{
EL2) CLK3 FS EN C H\ #400\

EK1> CLK3 FS EN D H\ #400\
{

CLK3 ERROR HOLD B H

| CLK3 ERROR HOLD B L

CLK5 FS CHECK L

NOTE

THIS LOGIC IS CHECKED ON EVERY MBOX CLOCK. |F THE ERROR STEP LOGIC
IS USED ON EBOX SIGNALS THEN CLK EBOX SYNC SHOULD BE JUMPERED IN.

USE EBOX SYNC AS AN FSINPUT WHEN LOOKING AT EBOX SIGNALS.
'

3 WHEN USING NAND GATE FOR QUALIFIERS GROUND PIN EM1.

MR-2301

" NUD

EK2» CLK3 FS EN G L\ #400\
{

*OdNI

LA
4

‘b

EJ1) CLK3 FS EN E L\ #400\
C
EJ2> CLK3 FSEN F L\ #400\
{

AAA

*OdNI

*NHID

KL10 PAGE FAIL TRAPS (INT. MEM.)

WHERE

S G

—

0]0

READ

—

OR RPW

OFF

READ

oz,

FAILINGDATAPATH

sS=<KE

ORCOMPONENT

x[x]

Tx]

MEMORY

DETECTED

IERE

PAGE
MEMORY

?3:
.

0(0

111

MB TO PT OR THE PT
X

MEMORY

MEMORY TO MB

MB TO AR/ARX

010

CACHE TO AR, THE CACHE OR MB TO AR/ARX

»
o1

MR-2421

KL10 HARDWARE FAULTS (INT. MEM.)

TM~

T
x ¥

2
O

wi
o

a
w

c
Z

»
<

m
—

O
=
=
<
o

=
Z
w

o
c

iZ
g

W
%)

DETECTED

>
i

x
[os
<

b oo

=S<&

N TM
W
o
o

FAILING DATA PATH

ORCOMPONENT

~-{-]0

PAGE

—-1-10

oo}

REFILL | vEmMORY

111

X|X

~|-10

010

READ

OR RPW

11]1

X | X|x

MEMORY

0|1

MEMORY
TO MB

0|1

MEMORY
TO MB

MB OR AR TO CACHE TO MB
MASSBUS DEVICE TO RH TO CACHE
TO MB

-{-10 o]0
~1-10

010

oj{1]o

ofo

of{1]1

1]o0

READ

CHAN DATA

of1]o

o{1]0

=11

WRITE

RPW

1|0

=11

WRITEBACK

1101

1|1

SWEEP

MEMORY
TO MB

MEMORY
MEMORY
TO MB

0|1

CHAN STATUS

011

CHAN
TO MB

|EBOXSTORE

0|1

AR TO MB

CACHE TO MB OR THE CACHE

*NdD

[1 [ N

llCACHE

| on

WHERE

MB TO MEMORY

MR-2422

*OdNI

’

~ §

B |4_ |’ ‘JCACHE,

_
o

o«
I

£z

ojol}

SacE

0|0

REFILL

- —|-

*OdNI

*NdD

KL10 PAGE FAIL TRAPS (EXT. MEM.)

0]-

oo|=]
0~

cén

v
MEMORY
READ

...~
READ

OR RPW

.,
<

DETECTED

0f1

WHERE
&

w
o

X
<«

B =<k

X|X

MEMORY
TO DMA

FAILING DATA PATH

ORCOMPONENT

DMA TO MB

MB TO PT OR THE PT

1]1

X | X|x

MEMORY
TO DMA

0|1

X | Xx

DMA TO TO MBMB

OFF

o|o

MB TO AR/ARX

0|0

CACHE TO AR,

‘

THE CACHE OR MB TO AR/ARX
MR-2419

KL10 HARDWARE FAULTS (EXT. MEM.)

w -Z
v <

<
£

o
m

-1-1o0

PAGE

0olo

REFILL

—{-10

o T

=
=

wn g
> o

—1-1o oo

W =

S s

[os

DETECTED

<«
<
.3

o
o

O
O

8 = < &

FAILING DATA PATH

= A

OR COMPONENT

DMA
TO MB

ol1

‘
MEMORY

111

X | X

READ

X | x| x

MEMORY
TO DMA

X |X

DMA
TO MB

OR RPW

~{-10

olo

READ

o|1{0

oo}

111

X |X

ol1]lo ool

of1

WHERE

CHAN DATA

;

MEMORY
TO DMA

TO MB
DMA

of1]1

ol1lo

ol1]0

of1

=11

ol1

—-]=

RPW

110

=11

111

WRITEBACK

CACHE TO MB OR THE CACHE

1ol

111

0|1

CACHE TO MB OR THE CACHE

CHAN STATUS
WRITE

SWEEP

| EBOX STORE

ol1

MEMORY
TO |DMA

DMA
TO MB

AR OR MB TO CACHE TO MB

0|1

'MASSBUS DEVICE TO RH TO CHAN
TO MB

CHAN TO MB

0}1

AR
TO MB

MB TO DMA

MR-2420

"NHD

*OdNI

_(59_

GEN.

INFO.
-56—

MEMORY

ADDRESS

Double
Triple

spaced
spaced

FROM

MAP

at
at

START

16K
64K
STOP

07777

4K
8K

10000
20000

12K
16K

12K

30000

17777
27777
37777

16K

40000

47777

20K

50000

57777

24K

60000

28K
32K

28K

70000

67777
77777

32K
36K

100000
110000

107777
117777

40K

120000

127777

44K

48K

36K

44K

130000

137777

48K

140000

147777

52K
56K

52K

150000
160000

60K

170000

157777
167777
177777

56K
60K
64K

64K

200000

207777

68K

68K
72K

210000
220000

217777
227777

72K

76K

230000

237777

80K

240000
250000

247777

257777

88K

92K

260000
270000

267777
277777

92K

96K

96K
100K

300000
310000

307777
317777

100K
104K

84K
88K

76K

84K

104K

320000

327777

108K

330000

337777

112K

340000

347777

116K

116K
120K

350000
360000

120K

124K

370000

357777
367777
377777

128K
132K

136K

400000
410000

420000

124K
128K

407777

132K

417777

136K

427777

140K

430000

437777

144K

440000

447777

148K

450000

457777

152K

152K
156K

460000
470000

467777
4777717

156K
160K

507777
517777.

164K
168K

160K

500000

164K
168K

510000
520000

172K

530000

527777

172K

537777

176K

540000

180K
184K

550000

547777
557777

180K

560000

567777

188K

570000

577777

192K

184K

GEN.
-57
=

192K

600000

196K
200K

610000
620000
630000

607777
617777
627777
637777

196K
200K
204K
208K

640000
650000
660000
670000

647777
657777
667777
677777

212K
216K

707777
717777

228K
232K

727777

236K

700000
710000
720000
730000

7377717

240K

740000

747777

244K
248K

750000
760000

252K

770000

757777
767777
777777

244K
248K
252K
256K

204K
208K
212K

216K
220K
224K
228K
232K

220K
224K

INFO.

SiNGLE

QUAD-WORD

DISTRIBUTION

FOR

(DEPENDS ON VALUE OF ADR

CONTROLLER

19 & 20

SHOWN)

PAIR

SHOWN)

QUAD-WORD

DISTRIBUTION

SM1

SMO

WORD

WORDS

0-3

L1
0DbD
CONT

CONT

SM1

Iii;iil
0-3

CONT

ODD

CONT

)

sm2

|Ii'i||
WORDS

19:=0,ADR

CONT

SM3

IIiIiII
WORDS

I
CONT
20:1,ADR 21:='1

SMO

SM 1

SMO

WORD

EVEN
CONT

19:0
SM3

‘
sM2

ODD

CONT

EVEN

CONT

ADR 19=1

SM2

WORDS
OA2

I
ODD

CONT

20:=1

‘

CONT

]

ADR

ADR 20:=1,ADR 21:0

ADR

EVEN

ADR

SMm2

SM2

PAIR

ADR
SM3

CONTROLLER

WORD

oDD

2 0lElp 7k

ADR 20=0,ADR 21= 1

OF ADR 19 AS SHOWN)

CONT
ADR 19:0,ADR 20:=0

ADR 20:0 ADR 21:=0

FOR

(DEPENDS ON VALUE

19:=1, ADR

EVEN

CONT

20:=0

BEEEIELEE:
ODD

CONT

EVEN CONT

ADR

19=1, ADR

20:1

MR-2069

*OdNI

QUAD-WORD
FOR

(DEPENDS ON VALUE OF ADR 20 8 21

"NID

MA20 1, 2 AND 4-WAY INTERLEAVING

1, 2 AND 4WAY INTERLEAVING
MB20

QUAD-WORD.

QUAD-WORD

DISTRIBUTION

OR A SINGLE

DISTRIBUTION

FOR-A

CONTROLLER

(DEPENDS ON VALUE OF ADR 18. 8 19

CONTROLLER

(DEPENDS ON VALUE OF ADR 12 8 20 AS

QUAD-WORD

PAIR

SHOWN)

DISTRIBUTION

FOR

(DEPENDS ON VALUE

CONTROLLER

PAIR

OF ADR 18 AS SHOWN)

SHOWN)

SMO

‘

SMO

|Iiii||

SMH

)

WORD

WORDS

0-3

00D

‘

CONT

EVEN

SM 1

SMO

WORD

obo

EVEN

CONT

ADR {8 =0

ADR18:=0,ADR 19:0

ADR 19 =0 ADR 20:0

SMO

SM3

SMi

SM2

ODD

WORDS

ADR 18 =1

OO
]

|
CONT

ADR

19:=1,ADR2D= !

LI%

CONT

EVEN

CONT

)

IoNT

Swi

SM3

110]

0-3

fLEn

00D CONT

I
ODD

ADR 18 =1

Elo7 o3

CONT

- ADR 19 :1,ADR20:0

TINT

ADR 18 =0, ADR 19 : -

SM2

SM3

eves

CONT

ADR'13 =0,ADR 20=1

"NHUD

CONT

]

O
.

—

f.2% CONT

QDD CONT
)

ADR 18:1.
7% ">

MR-2070

"OdNI

|iiiii|
0-~3

~-69—-

SM1

GEN.

INFO.
-60-

MAGTAPE FORMATS

7 TRACK

TRACK 7

TRACK 6

TRACK §

TRACK 4

-2

TRACK 3

.27

TRACK 2

TRACK 1

REFERENCE EDGE

9 TRACK (INDUSTRY COMPATIBILITY MODE)
TRACK 9

TRACK 8

TRACK 7

TRACK 6

TRACK 5

TRACK 4

TRACK 3

TRACK 2

TRACK 1

REFERENCE EDGE

9 TRACK (CORE DUMP MODE)
TRACK 9

TRACK 8

TRACK 7

TRACK 6

TRACK 5

TRACK 4

TRACK 3

TRACK 2

TRACK 1

REFERENCE EDGE

RELATIONSHIP BETWEEN TRACK NO. AND CRC REGISTER BIT POSITIONS:
TRACK NO
CRC REG, BIT

5
4

MR-2209

GEN.
-1~

NOTES

INFO.

*N3D
BYTE

)

(8)

(4)

(2)

3
:

COMMAND

INTERVENTION|

BUS OUT

EQUIPMENT

DATA

REJECT

REQUIRED

CHECK

N OISE

STATUS A

TU.

STATUS B

TRK

R/W VRC

5
6

;

9
10

NEW

WTM

'SUBSYSTEM

7-TRK

¥* *

|coLumn

=*#|LEFT. coL.

REJECT TU

gXFLRENT

TOP OR BTM
IBG

FAIL

*%% | VELOCITY

CORRECTION | CHANGE
CMND STAT

'REJECT

DUAL

CcK

¥* % ¥

RIGHT COL.

RESET

*%%|

PROTECTED

CHECK

SELECTED & | FILE

NOT
| CAPABLE

ERROR
1600 BPI
SET IN TU

\s/n;iw

PARTIAL

READ CHECK | RECORD

BAC KWARD

C/P COMP.

RPQ

CHECK

*% | POSTAMBLE
**

ERROR
'

1600

*%% | KEY

TAPE UNIT MODEL IDENTIFICATION
DSE

ERASE HD *#*

FAILUR

FAILURE

6
LOAD

FAILURE

wenl
8

CHANNEL

BUFFER CK

CRC I
RECORD NOT

#*»

DETECTED

TX01 ONLY

NOT

* ¥

(1)

WORD COUNT | 2800
ot

| 2 sTAT

ENV CK/

START

7
DATA

LWR

**|

ZERO

VRC

*% | |D BURST

OVERRUN

WRITE TRG

DENSITY TU

*x%% | FAIL

(4)

* %

| DETECTED
6250

WRITE

END DATA CK
ICRC

CHECK

* *

SKEW
ERROR

MTE/LRC

(8)

LOAD POINT

TRACK

6250

*¥

TCU

RESERVED

TACH START

FAIL

VELOCITY

CHECK

2
**[

#% TX02 ONLY

%% TU72 ONLY

MR-2309

*OJdNI

TXO0x/TU7x SENSE BYTES

13
14

;

4096
1]

;

128

512

256

]

|
1§

SWITCH FEATURES
v

FEATURE

13
14

256

SAME

I.D.

TUF

TUE

]

E.C.

TU 7

REFLECTS TCU DIAGNOSTIC RELEASE LEVEL
:
L
.

LEVEL

18
]

BUSY STATUS, LO—ORDER TAPE UNITS

TUS

TUD

BUSY STATUS, HI—ORDER TAPE UNITS
TuC
TUB

TU 4

TAPE UNIT UNIQUE IDENTIFICATION (LO—ORDER PART S/N)

2 CHSW

‘46

1024

TAPE UNIT UNIQUE IDENTIFICATION (HI—ORDER PART S/N)

8192

CONTROL UNIT UNIQUE IDENTIFICATION (LO~ORDER PART S/N)

TU 3

TU 2

TU1

TUO

U A

TU9

TUS

21
'

22
23

“REFER TO MICROPROGRAM PAGE QA025"

{

MOD 1V

“REFER TO MICROPROGRAM PAGE AQ025"

BYTE

T
*

BYTE

0
TX01ONLY

TX02ONLY

(4)

2
*%%

(2)

(8)

(4)

(2)

*NID

2048

128

;

CONTROL UNIT UNIQUE IDENTIFICATION (HI-ORDER PART S/N)

‘

CU FEATURES

TU72 ONLY

MR-2310

*Od4dNT

-89_

GEN.

INFO.
-64-

DIAGNOSTIC

FUNCTIONS

KL10(PA and PV)
Function
CLOCK

Diagnostic Execute

(Control)

Functions

Mnemonic

Operation

STPCLK

STOP THE KL10 CLOCK
START THE KL10 CLOCK
SINGLE STEP THE MBOX CLOCK
SINGLE STEP THE EBOX CLOCK.

CONTROL

STRCLK
SSCLK

" SECLK

EBOX

CLOCK

CAUSES

FALSE

(2,3)

AND

EBOX

MBOX CLOCKS

LEAVES

SYNC

THE

TRUE.

DEPENDING ON

EBOX CLOCK INITIALLY (FALSE,TRUE}. DOES
NOT DEPEND ON 'T' FIELD OR MB WAIT.
04

CECLK

BRCLK

CONDITIONALLY ISSUE AN MBOX CLOCK IF
THE EBOX CLOCK IS TRUE. MAKES EBOX
CLOCK FALSE.
-IF ISSUED IN THE MASTER
RESET STATE,LEAVES EBOX SYNC TRUE.

ISSUE A BURST OF CLOCKS.
THE NUMBER OF

MBOX CLOCKS DESIRED (1-255) HAS BEEN
LOADED PREVIOUSLY BY FUNCTIONS 42,43.
06
07

CLRMR
SETMR

CLEAR MASTER RESET STATE.
SET MASTER RESET STATE. RUNNING

CLOCK WHILE

IN THIS STATE

KL10.

EBOX

CLRRUN

SETRUN

SET

CONBUT

SET THE CONTINUE FLOP (MOMENTARY).
ALLOW THE MICROCODE TO LEAVE THE

IRLTCH

UNLATCH

THE

DRLTCH

UNLATCH

THE

DRAM

CLEAR

THE

RUN

THE

FLOP.

and

PV)

'LOAD'

RUN

FLOP.

ALLOW

THE

EXECUTION.

.
AND

HALT

‘
LOAD

IT FROM

TO LOAD FROM THE RAMS.

Diagnostic Write

MICRO-CODE

REPEATED

THE

AND ALLOW

AD.

Functions

FUNCTIONS.

LDBRR

LDBRL

LOAD THE RIGHTHAND 4 BITS OF THE 8-BIT
BURST

COUNTER

LOAD

THE

FROM

LEFTHAND

CTR.

MAKE

"HALT LOOP".

GO TO THE

LOOP.

CLOCK

THE

CONTROL

INSTRUCTION

KL10 (PA

THE

'CLEARS'

LDSEL

EBUS
4

BITS

32-35

BITS

AND

RATE

THE

BURST

LOAD

THE

CLOCK

SOURCE

SELECT

LDDIS

LDCHK1

SOURCE

NORM XTAL

RATE

NORMAL

FAST XTAL

DIVIDE

1
1

0
1

EXTERN

DIVIDE

FAST

DIVIDE

LOAD

THE

EBOX

CLOCK

XTAL

33
34

DISABLE
DISABLE

DISABLE CONTROL
THE

CONTROL RAM CLOCK
-DATA PATHS CLOCK

THESE

STOP

AND

SHOULD

WITH

BIT

LOGIC

CONDITION-CHECKING

THE

DISTRIBUTION.

BIT

LOAD

CONTROLS

ALL

ENABLE

USED

FUNCTION

CLOCK

ENABLE

THE

CLOCK -TO

IN CONJUNCTION

47.

FUNCTION

CHECK

FM PARITY
CRAM PARITY

CHECK

DRAM

CHECK

FIELD

PARITY

SERVICE

'PROBE'

GEN.

INFO.

-65-~

LOAD THE

LDCHK?2

ENABLE/DISABLE

FUNCTION

32
33

DISABLE

EBOX

SIMULATE

CHECK

CAUSE A
IF

TO MBOX
FOR EACH

RESP

AND

ARX

'PAGE

PARITY

FAIL'

AND

UCODE TRAP

ERROR.

MUST
:

REQUESTS
MB

WAIT.

SET

ACTION

STOPS

ALL

PERFORM

FUNCTION

CLOCKS

DESIRED
(ABOVE).

ERROR

BITS

ABOVE

DETECTED.

CONTROL

RAM

LOAD

FUNCTIONS

LCRDAR

00-05.

CRAM

52
53

LCRDAL

01-05
00-05

CRAM DIAG ADR 00-04
EA CALL & DISP 00-04

LCRAM4

LCRAMS

DIAG

ADR

05-10

BITS
EBUS

CRAM

08
10
14

60
62
64
66

ODD

NUMBERED

68
70

ARE

NONEXISTENT.

LCRAM3

LCRAM2

NOTE

74
76

LCRAM1

LOAD

DRAM

FUNCTIONS
BITS

LDRAM]1

12-14
15-17

DRAM A00-02,
DRAM B00-02,

EVEN
EVEN

LDRAM2

12-14

DRAM

ODD

ADDRESSES

15-17
14-17

DRAM B00-02, ODD
COMMON J01-04

ADDRESSES

15-17
12

J08-10, EVEN ADDRESSES
PARITY BIT, EVEN ADDRESSES

LDRAM3-

LDRJEV

LDRJOD

COMMON J07

15-17
12

J08-10, ODD
PARITY BIT,

IR,

DRAM

CONTROL

A(00-02,

NOT

ADDRESSES
ADDRESSES

(NOTE:

J05 AND JO6

EXIST.)

ADDRESSES
ODD ADDRESSES

FUNCTIONS

DISIOJ

DISACF

DISABLE

ENIOJA

ENABLE KL10 STYLE DECODING
OP CODES AND AC'S.

DISABLE

SPECIAL
IR

FUNCTION

THIS

CERTAIN
NEEDED
PROPER

CONDITIONS
FOR

FUNCTION
EBUS

OUTPUTS

CHANNEL CONTROIL FUNCTIONS
70

DECODE

254, 7XX.

CODES

SHOULD NOT

TIMING

BIT

USED

WITHIN

DEVICELESS

ESTABLISH

THE

TESTING.

CHANNEL
THIS

USED WITHOUT

SYNCHRONIZATION.

OPERATION

SIMULATE

CBUS

RESET

SIMULATE

CBUS

START

SIMULATE

CBUS

DONE

10
11

SIMULATE
SIMULATE

CBUS
CBUS

CTOM
STORE

SET DIAG

SLOW

REQ

SET

FAST

REQ

12
13

DIAG

GEN.

INFO.
-66~

MBOX

CONTROL

FUNCTIONS

CONTROL
OF THE MEMORY TO CACHE SELECTOR

LDMBXA

(MEM

FUNCTION
BITS

SEL
A

NOT

1,2)IS

LDMBXA
LOAD

THEREFORE

NORMAL

USE

BITS

GIVEN THROUGH .THE

(071)
CONTROL

USING SIX EBUS
REGISTER, THIS
BY MR RESET

INITIALIZED

MUST

THE

KL10.

LOADED

BEFORE

FUNCTION

CONTROL

0
0

0
1

UNDEFINED
FORCE MIXER

MEM

ALLOW

CACHE

MIXER

ENABLE

1
'

UNDEFINED

SELECT

SEL 1
INCLUSIVE

THE

AND

SEL

AND

BITS

AND

RESPECTIVELY.

NORMAL

30, 31.
ALLOW ONLY

THE

WHAT

SOURCE

WITH

NORMAL

INPUTS.

THE

CONSOLE

BITS

SHOULD

SUPPLY FOR NORMAL OPERATION.
FORCE SEL 2 AND SEL 1 FALSE.

SELECT

(INVERTED)
SEL

INPUTS

TO SEL

SELECT

MB
MEM

TO CHANGE THE KW20 CLOCK FREQUENCY,

CONSOLE

REPLACE

THIS

THE

SOURCE

WITH THE NORMAL SOURCE OF SEL
"

NOTE

OPERATION..

STATE

ENABLE

NORMAL

RESET

FOLLOWING

MASTER

RESET

EXECUTE

FUNCTION

BITS

FUNCTION

MOS

CLOCK

EXT

CLK

0
1

1
0

31
25

MHZ
MHZ

FUNCTION

(76)

WRITE

72.

CONTROL

MHZ
MUST

INITIALIZED

THE

SOFTWARE.

SBUS

CONTROLLER

24=]1

WILL

SET

24=0 WILL

RESET

THE

MEM

CLEAR THE

RESET

FLIP-FLOP

MEM RESET

FLIP-FLOP

TO CLEAR ALL MEMORY CONTROLLERS, SET
THE MEM

THEN

RESET

FLIP-FLOP,

CLEAR THE

MEM

REST

RUN

THE

CLOK,

FLIP-FLOP.

.CHANNEIL CLOCK .CONTROL
25=1 INHIBIT
THE

25=0

THE

MBOX

CHANNEL

ENABLE

CLOCK

DISTRIBUTION

LOGIC.

MBOX

CLOCK DISTRIBUTION

CHANNEL

LOGIC

EBUS REGISTER LOAD ENABLE
26=1

"
26=0

ENABLE

EBUS

DISABLE

EVERY

EBUS

EXTENDED

ADDRESSING

(KL10 (PV)ONLY)

CAUSES

THE

EFFECTIVE

ADDRESS

CALCULATIONS

VMA,

SECTIONS

NONZERO

PCS

ANY

OCCUR

UNTIL

FUNCTION

27=0

EXPECTED.

LOAD

THE

WRITE

LDAR

0-35

FROM

THE

WERE

SECTION.

TRUE

WITH

AR LOAD FUNCTION
77

CLOCK TICK

FORCE
27=1

EVERY CLOCK TICK

EBUS 0-35.

BIT

GEN.

INFO.

-67-

FUNCTION

CODES

SORTED

DRAWING

BOARD

NAME

AND

PIC1

M8532

PICl

PTH1

100

PIC1

M8532

PIC1

100
100

PIC1

M8532

PIH2
PIH3

PIC1

M8532

PIC1
PIC1

100
100

PIC1
PIC1

' M8532

PIC1
PICl

M8532

PIH4
PIHS5

PIH6

PIC1

M8532

PICl1

PIH7Y

PIC1

100
100

PICl
PIC1

PIC1
PIC1

ACTIV
ON

PIC1

100
100

PIC1

100
100

PIC1

M8532
M8532
M8532
M8532
M8532
M8532

100
100

PICl
MCL3

100
100

MCL3
MCL3

100

MCL3

100
100

MCL3
MCL3

PIC1

M8532
M8532
M8530

PIC1

PICl1

PIC1

ON
HELD

VMA

HELD

OR
OR

VMA

HELD

VMA

HELD
HELD

OR
OR

VMA

M8530
M8530
M8530
M8530
M8530

SOy
U s
N

100

PIC1

NUMERICALLY

TRUTH

VMA

100

CTL1

M8527

CTL

SPEC/SCM ALT

100
100

CTL1
CTL2
CTL2

M8527
M8527

CTL
CTL

SPEC/SAVE
ARL SEL 2

M8527

CTL

ARR

LOAD

CTL?2
CLK1

M8527
M8526

CTL

00-08

100

CLK

EBUS

CLK

100

CLK1

M8526

CLK

SBUS

CLK

100
100

CLK5
CLK5

M8526
M8526

CLK

BURST
BURST

CNT=0
128 H

100

CLK5

M8526

BURST

M8532
M8532
MBS 32

Prei
Prei

GEN

PICL

GEN

PICl
PIC1

GEN
GEN
GEN

4
5

H
H

100

101

PIC1

101

PIC1

101

PIC1l

101
101
101

PIC1
PIC1l
PIC1

101
101
101

MCL3
MCL3

101
101

MCL3

M8532
M8532
M8532
M8532
M8530
M8530
M8530

MCL3

101

PIC1

CLK

PIC1

PIC1
VMA

GEN
HELD

FLAGS
H
A

LOAD

7 H
OR PC

HELD OR

VMA

HELD

M8530

VMA

HELD

MCL3

M8530

VMA

HELD

101

MCL3

M8530

VMA

HELD OR

101

CTL1

CTL

CTL1

M8527

CTL

SPEC

CTL2

M8527
M8527

CTL

ARL

SEL

CTL

ARR

LOAD

09-17

101

MTR

CTL2

M8527

CTL

CLK5

M8526
- M8526

CLK
CLK

BURST
BURST

101

CLK5

M8526

CLK

BURST

101

" CLK5

CLK

BURST

101

' CLK5

M8526
M8526

32
16
08
04

CLK

CLK5

M8526

BURST
BURST

02
01

Cs05
Cs06

E
E

101
101

101
102
102

102
102.
102
102

CLK5

PIC4
PIC4
PIC2.
PIC4

CLK

M8532

EBUS

M8532

EBUS

M8532

EBUS ‘DEMAND

M8532
M8532

EBUS Cs00

PIC4

M8532

EBUS

SPEC/CLR FPD

101
101
101

CTL2

E
E
E

Cs01
Cs02

Cs03 E
READ

H
B

L OAD

H
H
H
H

H
H
jusfiia slie o lin ol s Je s Jhaw)

CTL

VMA

M8527

josjiiasBiusiiaoiin
i

READ

ommm Imom

100

BIT

DIAGNOSTIC

asfiosiiiasiiasiinslia
sl +lca RiusJiasiiaciie riiasiicsiiias]

KL10 (PA)

102

PIC4

M8532

102

MCL2

M8530

MCL

VMA

102

MCL1

M8530

MCL

MEM/ARL

102
102

MCL2
MCL4
4
MCL

M8530
M8530
M8530

MCL

PAGE TEST PRIVATE
XR PREVIOUS H
VMA GETS AD H

‘MCL5
CTL1
CTL1

‘M8530
M8527

M8527

CTL

COND/AR GETS

CTL2

‘M8527

CTL

ARR SEL

M8527

CTL

MQM

‘M8527
M8526
M8526

CTL

102
102
102
102

102
102

102

CTL2
CTL2

102
102
102

CLK1
CLK2
CLK4

102
102

CLK3
CLK4

M8526

102

CLK4

M8526

M8526
M8526

EBUS

MCL

~MCL

ARMM
CTL

IND H

SPEC/GEN CRY 18 H

SEL

LOAD

ARX

EXP

2
H

CLK

ERROR STOP H

CLK
CLK

EBOX

SYNC
CLK PAGE.
CLK

- CLK

FORCE

REQ

FAIL

1777

INFO.

GEN.

-68-

KL10 (PA)

* %

DIAGNOSTIC READ FUNCTION CODES SORTED NUMERICALLY
DF

DRAWING

BOARD

NAME

AND

103

PIC2
PIC5
PIC2

M8532
M8532
M8532

PIC2
PIC5
PIC2

TIMER

103
103

PIC4
PIC2

M8532
M8532

EBUS

Cs04

103
103

PIC2

READY

PIC5

EBUS

REQ

103
103

MCL2
MCL1

M8532
M8532
'M8530
M8530

VMA

PAUSE

MCL

REQ

103
103

M8530
M8530

MCL
MCL

VMA UPT H
PREV COND

103

MCL3
MCL4
MCL4

M8530

MCL

VMA

103
103

MCL5
CTL1

M8530

MCL

SPEC/SECTION

CTL1

M8527
M8527

CTL

103

CTL

DISP

103
103

CTL2

M8527
M8527

CTL

ARR
MQM
ARL

PIC5

103

CTL2
CTL2

103

CLK3

103
103

CLK2
CLK4

M8527
M8526
M8526
M8526

103
103

CLK4
CLK4

103

CLK4

104

MCL2

104
104

104
104
104
104

PIC2

MCL

CTL

EBUS

DONE

STATE

HONOR

INC
SEC

RET

SEL
SEL

1
1

SEL

PAR

CLK

M8526
M8526

CLK

EBOX

CLK

INSTR 1777

CLK

1777

MCL

VMA

WRITE

MCL2
MCL3

M8526
M8530
M8530
M8530

MCL

VMA

USER

MCL

PAGE

UEBR

MCL4
MCL4
MCL6

M8530
M8530
M8530

MCL

VMAX

MCL

LOAD VMA

MCL

EBOX

CTL1
CTL1
CTL2

M8527
M8527
M8527

CTL

SPEC/FLAG CTL H
LOAD

CTL

ARXL

SEL

CTL2
CTL2

M8527

CTL
CTL

CLK3
CLK2
CLK5

M8526
M8526
M8526

CLK

CRAM

PAR

CLK

EBOX

ERR

CLK

MBOX

105

MCL2
MCL2

M8530
M8530
M8530
M8530

MCL

LOAD AR H

MCL

VMA

M8530
M8530
M8527
M8527
M8527
M8527

MCL

EBOX

105
105

CTL1
CTL2
CTL2

H
ERR
L

EBOX

MCL6
CTL1

CLR

SOURCE

105

SEL

SOURCE

H
H

CHECK

CYCLE

DIS

PUBLIC

MCL

PAGE

ADDRESS

MCL

VMAX

SEL

MCL

MAY

COND

H
PAGED

SPEC/SP MEM CYCLE
ADX CRY 36 H
ARXL SEL 1 H
CTL MQ SEL 1 H
CTL AR 12-17 CLR H

CTL

CTL
CTL

M8527
M8526
M8526

SH AR PAR ODD H

CLK5
CLK5
CLK5

M8526
M8526
M8526

CLK

SOURCE

CLK

EBOX

CRM

DIS

CLK

CRAM

PAR

CHECK
L

CLK5
MCL2
MCL2
MCL3
MCL4

M8526
M8530

CLK

MBOX

RESP

MCL

LOAD

ARX

- M8530

MCL4

M8530

106
106

MCL6

106

CTL1

106
106

CTL2
CTL2
CTL2

106
106

CLK3
SHD1

106

CLK5

106
106
106

CLK5
CLK5
CLK5

107
107

105

105
105
105

105
106

CLK

PAR

ERR

SEL

SIM
H

M8530

~ MCL VMA PREVIOUS L

M8530

. MCL

PAGE

ILL

ENTRY

MCL

VMAX

SEL

MCL

M8530
M8527

MCL

REG

M8527
M8527
M8527
M8527

CTL

M8526
M8526
M8526
M8526
M8526
M8526

CLK

MCL2
MCL2

107
107

106
106
106
106

106

CTL1

CTL2
CLK3
SHD1

105
105

00-11

BIT

CLK

105

REF

CONTEXT

CLK

MCL3
MCL4

CLK

MCL4

CACHE

PAR

XFER

M8526
M8526

105
105

DRAM

M8527

H
H

BURST

SEL

HOLD

CLK

M8526

105

ARMM

CLK

CTL

CLK3

105

INTERNAL

CLK5
CLK5

105

GRANT

HOLD

104
104

(Cont)

TRUTH

BIT

FUNC

CTL AD LONG H
ADX CRY 36

CTL

ARXR

CTL

MOM

SEL
EN H

CTL

ARR

CLR

SH
CLK

EDP
PAR

CLK
CLK

AR/ARX

M8530

MCL

STORE

M8530

MCL,

VMA

MCL4

M8530

MCL

‘MCL4

M8530

MCL

EA TYPE
EA TYPE

A H
H

FS ERROR H
ARX PAR ODD
RATE SEL 2

EBOX
DRAM

CLK

H
H

CHECK

PAR
AR

H
H

DIS

EXTENDED

10
09

CHECK

H
H

GEN.

INFO.

-69~

DIAGNOSTIC READ FUNCTION CODES SORTED NUMERICALLY
DF

DRAWING

BOARD

NAME

AND

107

MCL5

M8530

MCL

MBOX

REQ

107

MCL6

M8530

MCL

EBOX MAP

107
107

CTL1
CTL3
CTL2
CTL3
CTL2
CLK3
CLK4
CLK5

M8527
M8527

CTL

INH CRY

107
107
107

107

107
107
107
107

CLK5
CLK5

DIAG

CTL

M8527
M8527
M8527
M8526

M8526

CYC

MEM

RESET

ARXR SEL

DIAG

LOAD

CTL

SPEC

CLK

ERROR

L
FAIL

CLK

PAGE

M8526

CLK

RATE

SEL

M8526

CLK

EBOX

CTL

DIS

M8526

CLK

CHECK

STOP

H
H

107
110

CLK5
APR2

M8526
M8539

CLK
APR

SWEEP

110
110

APR1

M8539
M8539

APR SBUS ERR IN H
APR NXM ERR IN H

110

APR1
APR1
APR2

110

110
110

APR2

APR
APR

PIC3
PIC3
PIC3

M8539

110
111

M8538
M8539
M8539
M8539
M8539
M8539
M8539
M8539

111

MTR1
APR5
APRS
APR5
APRS
APR5
APRS
APR3
APR3
APR3
APR3
APR3

111
111

APR3
MTR1

M8539

112

112
112
112

APR1
APR1
APR1
APR1

M8539
M8539
M8539
M8539

112
112

APR2
-APR2

M8539
M8539

112

113

APR2
APR2
MTR1
APR3

113
113

APR3
APR3

113

APR3

M8539
M8539
M8538
M8539
M8539
M8539
M8539

113
114

MTR1

APR5

M8538
M8539

114

APRS

M8539

114

APRD

114

APRS
APR4

M8539
M8539
M8539

114
114

APR4
APR4
APR4

M8539
M8539
M8539

114
114

APR4
APR3

M8539
M8539

114

115
115

APR3
MTR1
APRS
APRS

115
115

APR3
APR3

115

APR2
APR6
APR6
APRO

111
111

111

112

114
114

114

115

115
115

115

APR6
APR6
APR6
MTR3
MTR3
MTR3

115

MTR3

115
115
115

115
115

M8539
M8539
M8539
M8539
M8539

110
110
110

111
111

APR

APR2

111
111

ERR

APR MB PAR ERR IN H
APR C DIR P ERR IN H
APR S ADR P ERR IN H

110

111

M8539
M8539
M8539

APR2

111

BUSY

M8539

110
110

APR2

I/0

EBUS
CALL

ERR

APR1

(Cont)

TRUTH

X oo
e

KL10 (PA)

M8539

M8539
M8539

M8539

M8538

M8539
M8538

.M8539
M8539

M8539
M8539
M8539
M8539
M8539
M8539
M8539
M8539
M8539
M8538
M8538
M8538
M8538

APR
PI3
PI3
PI3

PWR FAIL IN H
SWEEP DONE IN
APR INTERRUPT
APR PIA 04 H
APR PIA 02 H
APR PIA 01 H

MTR TIME 02-17 H
APR CURRENT BLOCK

APR CURRENT BLOCK

4
2

APR CURRENT BLOCK 1
APR PREV BLOCK 4 1
APR PREV BLOCK 2 1
APR PREV BLOCK 1 H
APR

APR
APR
APR
APR
APR
MTR
APR

CWSX

PREV SEC
PREV SEC

PREV SEC

H
H
il

13 H
14 H

15 H
16 H

PREV SEC 17 H
PERF COUNT 02-17 H

SBUS ERR EN IN H
APR NXM ERR EN IN H

APR I/O PF ERR EN IN H
APR MB PAR ERR EN

APR C DIR P ERR EN IN H
APR S ADR P ERR EN IN H
APR PWR FAIL EN IN H
APR SWEEP DONE EN IN H

MTR EBOX COUNT 02-17 H
APR FETCH COMP H
APR READ COMP H
APR WRITE COMP H
APR USER COMP H

MTR CACHE COUNT 02-17 H
APR MBOX CTL 03 H

APR FM BLOCK 4 H
APR FM BLOCK 2 H
APR FM BLOCK 1 H
APR FM ADR 10 H
APR FM ADR 4 H

APR FM ADR 2 H
APR
APR
APR
APR
MTR

FM ADR 1 H
F02 EN H
FM 36 H
FM ODD PARITY H
INTERVAL 06-17 H

APR MBOX CTL 06 H

APR SET PAGE FAIL L
APR EBUS RETURN H
APR EBOX DISABLE CS H
APR WR BAD ADR PAR L

APR EBOX CCA H

APR

EBOX

ERA

APR EBOX SBUS DIAG H
MCL MEM/REG FUNC L
APR EBOX LOAD REG L

" APR EBOX READ REG L
MTR3

INTERVAL

MTR3 INTERVAL DONE H
MTR3 INTERVAL OVRFLO H
- MTR PERIOD 06-17 H

GEN.

INFO.
-70-

KL10 (PA)

DIAGNOSTIC
DF

APRS5
APRS

APR WR PT SEL
APR PT DIR WR

“APR2

M8539
M8539
M8539
M8539

FLG

116
116

12
13

APR6
APR6

M8539
M8539

APR EBOX UBR H
APR EN REFILL RAM WR

116

.21

MTR2

M8538

MTR2 PI ACCT EN

116

MTR2

M8538

MTR2

116

PIC3

M8538

PI3 MTR PIA

APR5S

M8539

APR PT WR L

APR3

MTR?2

09
10
11

APR

M8539

FOl1

EBOX

ACCT ON

APR EBUS DEMAND H
APR EBOX SEND FO02 H
CON FM WRITE PAR L

APR6

M8539

APR EBOX EBR H

20
21

MTR5
MTR5

M8538
M8538

MTR5 VECTOR REQ
MTR5 INCR SEL 2

117
117

22
25

MTR5
MTR3

M8538
M8538

MTRS5 INCR SEL
MTR CONO MTR,

EDP1

M8512

120

APR6

M8539

APR EBOX SPARE H

EDP AR

120

EDP1

M8512

EDP

120

EDP1

M8512

EDP AR 02 H

120

EDP1

M8512

EDP AR (04

* %
* %
*
* %
*%

120
120
120
120
120

05
06
07
08
09

EDP1
EDP1
EDP1
EDP1
EDP1

M8512
M8512
M8512
~M8512
M8512

EDP AR
EDP AR
EDP AR
EDP AR
EDP AR

05
06
07
08
09

H
H
H
H
H

* %
* %

120
120 . -

10
11

EDP1
EDP1

M8512
M8512

EDP
EDP

10
11

H
H

120

12-35

EDP1

M8512

AR 12 TO 35

*
*

121
122

0-35
0-35

EDP4
EDP2

M8512
M8512

BR
MQ

TO
TO

35
35

H
H

123

0-35

EDP4

M8512

FM
0 TO

*
*
*

124
125
126

-0-35
0-35
0-35

EDP4
EDP2
EDP3

M8512
M8512
M8512

BRX
ARX
ADX

127

120

EDP3

04
05
06

130

* %
* %

130
130

* %

130

* %

130

* %

’

'SCD4

130
130
130
:

130

EDP1

0-35

130

09
10

;

M8512

M8524

SCD4
SCD4
SCD4

M8524
M8524
M8524

AR
AR

0
0

0
0
0
0

TO
TO
TO
TO

35
35
35
35

H
H
H

SCD

TRAP

CYC

SCD TRAP CYC
SCD TRAP REQ
'SCD FPD
H

1
1

H
H

M8524

M8524
M8524

SC 07 H
sC 08 H

SCD2

M8524

IRD3

M8522

NORM 08

IRD3

M8522

IR NORM

DR ADR 00 A H

IRD1

M8522

M8522
M8525
M8525

DR ADR

DR ADR 02 A H
CON WR EVEN PAR ADR H
CON3 WR EVEN PAR DATA H

SCD2

M8524

'SCD?2
SCD2

IRD3

SC 06 H

M8522

IRD1

IR NORM 09 H
10

17
18
19

IRD1
CON3
. CON3

130

CON3

M8525

CON3

131

SCDh4

M8524

SCD CRYO H

EDP3
SCD4
'sCD2

M8524
M8524
M8524

AD CRY 01 L
SCD DIV CHK
SC 00 H
SC

sC
SC
SC

02
03
04

H
H
H

M8522

ADR

M8522

DR ADR

M8522 .

DR ADR

SCD4

* %

131
131
131

05
06
07

* %

131

SCD2

M8524

* %
* %
* *

131
131
131

09
10
11

SCD2
SCD2
SCD2

M8524
M8524
M8524

* *

131

IRD1

* *

131

IRD1

* %

¥*

131

IRD1

* %

131

IRD1

131

SCD4

M8524

131

"
'~

H
H

1 H
L

SCD TRAP REQ 2 H

M8524

SCD2

‘

EDP AR

M8512

SCDh4

130
130
130

131

PI3 MTR PIA 02 H
PI3 MTR PIA 01 H
APR WR PT SEL 1 H

117.
117

* %

117

ERR

MTR2 TIME ON H

M8539
M8539

CON5

ANY

0
L

REQ

MTR2 EXEC ACCT EN H

M8538
M8538
M8539

APR3
APR3

EBUS

APR EBUS

M8538

PIC3
PIC3
APRS

APR

M8538

MTR?2

34
35
07

117
117
117

APR3

117
117

M8539

(Cont)

AND TRUTH

08
09
10
11

116
116

NAME

116

* %
* %

SORTED NUMERICALLY

DRAWING BOARD

116
116
116
116

116

READ FUNCTION CODES

BIT .

IRDI1 .
IRD1

CON3

M8524

SCD OV H

EVEN

PAR DIR

SCD CRY1l H

M8522 © ‘DR ADR 05 A H
M8522

M8522

M8525

DR ADR 07 A H

~ CON3 CACHE LOOK EN H

GEN.

INFO.

-71-

DIAGNOSTIC

* %

* %k

FUNCTION

CODES

SORTED

NUMERICALLY

BIT

DRAWING BOARD

131

19
21

CON3

131

M8525

CON

CON3

M8525

CON

KI10

PAGING

131
132

22
02

CON3
SCD4

M8525
M8524

CON

TRAP

VMA

HELD

132

* %

READ

NAME

AND

CACHE

LOAD

SCDh4

132

M8524

SCD

SCDh4

132
132

-EDP3

M8524
M8524
M8524

OVERFLOW

132
132

CRY

SCD2
SCD2

M8524

132

FE
FE

05
06

SCD2

M8 524

132

SCD2
SCD2

M8524
M8524

FE
FE

08
09

132

IRD4

M8524

FOV

SCD

(Cont)

TRUTH

MODE

FXU

-02

132

IRD3

M8522

132
132

I/0,

IRD3

M8522

IRD1

M8522

132

IRD1

M8522

132
132

IRD1

M8522
M8522

IRD1

132

CON1

M8525

132
132

CON

CON1
CON1

M8525
M8525

CON

132

CON2
CON4

00-07 L
COND/SEL VMA L
COND/MBOX CTL L

M8525
M8525
M8525

CON

LOAD

CON4
CON5

AR
PI
PCP

132
132

CONS5

COND

SCD4

M8524

SCD

M8524
M8524

133

SCD LOAD
SCAD=0 L

CON2

M8524

133

CON

SCD4
SCD2
SCD2
SCD2
SCD2
SCD2

M8524
M8524

SCD

133
133

133

FLAGS

M8524

FE
FE
FE

02
03
04

H
H
H

133

IRD1
IRD1

M8522
M8522

DRAM
DRAM

133

A
A

00
01

IRD1

M8522

DRAM

133
133

IRD1
IRD1

M8522

DRAM
DRAM

B
B

M8522

PRIVATE

NICOND

CLR

M8524
M8524

SCD5
scpnl

LOADED H
CYCLE H

133

JRST

133
133

133

INSTR

H
H
H

133

IRD1

M8522

DRAM

133

CON1
CON1

M8525
M8525

CON

SKIP

40-47

CON

COND/VMA

GETS

133

CON3

M8525

CON

EBUS

REL

133
133

CON4
CON2

M8525

133

CON4

PC+1
COND

INH

M8525

CON
CON

M8525

CON

ARX

LOADED

133

CON5
SCD5
- SCD5

M8525

CON5

CYCLE

INSTR

M8524
M8524

SCD
SCD

LEAVE

CON

SCD

USER

SCD5

M8524
M8524
M8524

SCD

PUBLIC

SCD2
IRD3

M8524
M8522

134
134

CON5

134

* %

H
EN

MEM

SCD5

USER

ABORT

H
L

L
PAGE

SATISFIED

IRD3

M8522

IRD1

DRAM J
DRAM J
DRAM J

01
02
03

H
H

JRST

0,
L

* %

IRD1

M8522
M8522
M8522

* %

IRD1

M8522

DRAM

CON1
CON1
CON3

CON2

M8525
M8525
'M8525
M8525

'CON SKIP EN 50-57
CON COND/LOAD VMA
'
CON SR 00 H
TRAP

EN
.H

CON2

M8525

CON

LOAD ACCESS

COND

CON4

M8525

CON

UCODE

CON5
SCD5

M8525
M8524

CON

SCD

PUBLIC
EN

SCD5
SCD5

M8524

SCD

PUBLIC

M8524

SCD

KERNEL

MODE

IRD1

* %

NICOND

STATE

WRITE

PAR

L
HELD H

H
H

SCD5

M8524

SCD

PRIVATE

INSTR

M8524

SCD

PRIVATE

INSTR
EN

IRD1

M8522

DRAM

IRD3

M8522

DRAM ODD PARITY H

"IRDL"

M8522
M8522

DRAM J

DRAM

‘DRAM J

09 H.

IRD1

M8522
M8522

DRAM

CON3

M8525

- CON

IRD1

SIGN

PAR

J
J

DELAY

~ SCD5
- SCD2

IRD1

135

CON

I,
USER

CYCLE

SIGN

TEST

133

134
134

zofiusiiaciiucias

KL10 (PA)

H
REQ

INFO.

GEN.

-72~

DIAGNOSTIC READ FUNCTION CODES SORTED NUMERICALLY
DF

DRAWING BOARD

135
135

CON1
CON3

135

CON2
CON2
CON4
CON5

M8525
M8525
M8525
M8525
M8525
M8525

SCD5
SCD3

M8524
M8524

SCD3
SCD5

M8524

SCD TRAP MIX 33

M8524
M8524
M8524

SCD USER
SCD USER

136

136
136
136
136
136
136
136

M8522
M8522
M8522

M8525
M8525
M8525
M8525
M8525

CON NICOND

136
137

CON5

CON
SCD

137

SCD3
SCD3
SCD5
SCD5

M8525
M8524
M8524
M8524
M8524

137

IRD4

137

IRD4
IRD4

IRD4

ADX CRY 24 H
CON ARX 36 H
CON VMA SEL 1
CON SR 03 H

CON3
CON2
CON2

137
137

CON4
CON5

M8525
M8525

140

CRA3
CRA3
CRA3
CRA3

M8511

M8511
M8511

M8525

M8525
M8525
M8525
M8525

M8511
M8511
M8511

*k
*x
k%

141
141
141

141

CRA3

. M8511

*k
*

141
141

CRA3
CRA3

M8511
M8511

142
142
142

CRA4
CRA4
CRA4

M8511
M8511
M8511

142

CRA4

- M8511

142

CRA4
CRA4
CRA4

M8511
M8511
M8511

143

CRA4
CRA4

M8511

143

'M8511
M8511
M8511

M8511

* ok

143

CRA4

M8511

143

144

*
**
**
**
**

144
144
144

CRA4
CRA2
CRA2
CRA2
CRA2
CRA2
CRA2
CRM5

M8511
M8511
M8511
M8511
M8511
M8511
M8511
M8528

*x
**
**
**

144

CRM5

M8528

144

CRM5
CRM5
CRMS

M8528
M8528

CRM5
CRM5

M8528
M8528

* ok

144

144
144

144

* %

144

BREAK

M8522

137

142

ADR

M8528

CRY

H
PREVENT
L

CON NICOND 09 H
CON COND ADR 10
CON UCODE STATE
CON

DISP

DISMISS

H
07
L

00-07

DISP EN
DISP 02
DISP 03
DISP 04

30-37
A H
A H
A H

DISP EN 00-03 L

CRA

DISP

PARITY

CRA
CRA
SBR
SBR
SBR
SBR
SBR
SBR

DISP 03
DISP 04
RET 05
RET 06
RET 07
RET 08

H
H

SBR

RET

RET
RET

09
10
00

SBR RET 01
SBR RET 02
SBR RET 03
SBR. RET 04
CR ADR 05
CR ADR 06
CR ADR 07
CR ADR 08
CR ADR 09
CR ADR 10
CRAM 60 H

H
H

CRA DISP 00
CRA DISP 01
CRA DISP

CYC

AD CRY 24 H
AD CRY 36 H
ADX CRY 12 H

CRA3
CRA3
CRA3
CRA3
CRA3

BRK

M8522
‘M8522
M8522

137
137.

140
140

ADR

34 H
35 H

SCD TRAP MIX
SCD TRAP MIX
SCD

SCD

CON1

140

L
INH

FM XFER
ADR BRK

SCD TRAP CLEAR
AD CRY 12 H

137

140

M8524

IRD4
IRD4
CON4

140

STATE

M8524
M8522
M8522

137
137

DRAM

CON UCODE

SCD4

LOAD

CON

By L B

137
137

M8525

CTL SPEC/GEN CRY
GEN CRY 36 H
AD CRY -02 A H
CON AR 36 H
CON VMA SEL 2 L
CON SR 02 H

137

137
137

SCD5

M8522
M8522

CRY

CON4
CON1
CON3
CON2
CON2
CON4

M8522

IOT

LEGAL H

136
136

137

* ok

INH

IR I/0

IRD4

137

*x
%
*x

AD=0
.CTL

136

CTL1
IRD4

A H
EN L

IOT
IOT

.GE.

SsC

CTL1

136
136
136

**x

SCD2
IRD3
IRD1

MBOX WAIT L
SCD KERNEL OR USER
SCD TRAP MIX 32 H
CON

136
136
136

136

SCD5

CON SR 01 H
CON NICOND 07 H
CON2 INSTR GO L
CON UCODE STATE

o> B

* %
**

INSTR L

LOAD SPEC

CON

(Cont)

AND TRUTH

juefilesiiaoliasiiiasiiosfieciiariicciicnfias

135

135
135

NAME

jaelie slsfinsiasiia]

KL10 (PA)

CRAM PAR 1ST 00
CRAM 62 H
CRAM PAR 00 H
CRAM 64 H
CRAM PAR 1ST 04
CRAM 66 H

GEN.

INFO.

-73-

KL10 (PA) DIAGNOSTIC READ FUNCTION CODES SORTED NUMERICALLY

*
*
*

BIT

DRAWING

BOARD

NAME

144
144
144

17
20
21

CRM5
CRM5
CRM5

M8528
M8528
M8528

CRAM PAR 04 H
CRAM 68 H
CRAM PAR 1ST 08

144

CRM5

M8528

CRAM

*
*

144
144

23
26

CRM5
CRM5

M8528

CRAM

PAR

M8528

CRAM

144

CRM5

M8528

CRAM

144

CRM5

M8528

144
144

CRM5
CRM5

M8528

*
*

144
144

CRM5
CRM5

M8528
M8528

*
*
*
*

144
145
145
145

CRM5
CRAl
CRAl
CRAl

M8528
M8511
M8511
M8511

*
*

145
145

CRAl
CRAl

M8511
M8511

CRAM 74 H
CRAM PAR 12 H
CRAM 76 H
CRAM PAR 1ST 16
CRAM 78 H
CRAM PAR 1 6
CR ADR 00 F
CR ADR 01 F
CR ADR 02 F
CR ADR 03 F
CR ADR 04 F

145

CRM5

M8528

CRAM

145
145

CRM5
CRM5

M8528
M8528

CRAM 44-47
CRAM 48-51
CRAM 52-55
CRAM 56-59
CRA LOC 05
CRA LOC 06
CRA LOC 07
CRA LOC 08
CRA LOC 09
CRA LOC 10
CRAM 20-23
CRAM 24-27

146
146

CRA3
CRM5
CRM5
CRM5
CRM5
CRM5
CRA3
CRA3
CRA3

146

146
146
146
*

147

M8511
M8511

M8528
M8528
M8528
M8528
MB528
M8511
M8511
M8511
M8511
M8511
M8528
M8528

CRAM

28-131

312-15

CRAM

CRAM 36-39
CRA LOC 00
CRA LOC 01
CRA LOC 02

147

*
*

147
147
147

CRA3
CRA3

147
147

CRM5
CRM5

147

CRM5

M8528

CRA LOC 03
CRA LOC 04
CRAM 00-03
CRAM 04-07
CRAM 08-11
CRAM 12-15

147

CRM5

M8528

CRAM

CRM5

M8528

ool cierfifcfiariiuvifasiiariiisofia
s fiurfias)

146

*
*

M8511
M8511

M8511

CRA3
CRA3
CRA3

16-19

CRA3

146
146

146

*
*

M8528
M8511

—

M8528

CRM5
CRA3

CRM5

146

40-43

jasiosiasiiesiiasiiociiariiaciie

145
145

jasjitaciiesiifasiiaciias)

*
*
*

M8528

(Cont)

TRUTH

AND

NOTE ABOUT READING VMA BOARD REGISTERS
THESE FORMULAS TERSELY DESCRIBE THE DIAGNOSTIC FUNCTION (150-157)
(13-35, ODD) CORRESPONDING TO A REGISTER
AND EBUS BIT NUMBER
BIT

'B'.

[]

MEANS

"THE

INTEGER PART OF THE QUOTIENT"

() MEANS "THE
REM

REMAIN DER OF"

FORMULA
REGISTER
ADR

BRK

FUNC

153-REM (B/4)

DITTO

157-REM (B/4)

VMA
VMA

DIAG

HELD

THE

BIT

4% [B/4]+3
4*[B/4]+1
4% [B/4]+3
4*%[B/4]+1

PRINTS!

18-31=0

M8523

VMA

157

VMAL
VMA3

M8523
M8523

VMA AC REF H
VMA MATCH 13-35

15X

VMA3

15X

VMA4
VMA2

M8523
M8523
M8523

ADR BRK 13-35 H **NOTE
VMA HELD 13-35 H **NOTE
VMA 13-35 H **NOTE

VMA3
MBZ1
4
MBZ

M8523

M8537
M8537

CORE
CHAN

160

SHD1

M8537

160
160
160

MBZ5
MBZ1
MBZ1

M8537
M8537

MB PAR
CSH EN

M8537

160
160

MBZ3
MBZ1

M8537

NXM ACKN

M8537

MBZ1

160

MBZ3

M8537

NXM

160

MBZ4

M8537

MBZ4

160

MBZ3
PAG5S

M8537

CHAN NXM

160

M8537

PAG MB

160

MBC5

M8531

VMAL

157

15X

153

YET--SEE

EBUS

BETTER

DITTO

FOR:

15X
160
160

**NOTE

13-35

BUSY H
PAR ERR L

PAR ODD A

IN H
DATA

BIT
CSH

SEL

BUSY H

CHAN CORE
L

ANY

NXM T6,7
ERR

18-35

PAR H

FORCE VALID MATCH

GEN.

INFO.
-74-

KL10 (PA)

DIAGNOSTIC

READ

FUNCTION

BIT

DRAWING

CODES

BOARD

SORTED
NAME

NUMERICALLY

AND

160

MBC5

M8531

FORCE

VALID

MATCH

160

MBC5

M8531

FORCE

VALID

MATCH

160
160
160

30
31
32

MBC5
MBC1
MBC2

M8531
M8531
M8531

FORCE VALID MATCH
.3 H
WRITE OK H
MBC2 CSH ADR WR PULSE

160

MBC2

'M8531

CSH

161

MBZ5

M8537

CBUS

161
161

MEM5
MBZ6

M8537

MEM

M8537

MBZ6

PAR IN H
CSH PAR
TO

161

MBZ4

M8537

MBOX

DATA CLR DONE IN
ADR

PAR

ERR L

PAR

LEFT

DIAG
2

H
H

161

MBZ1

M8537

MEM

20
21

MBZ1

M8537

MBZ1

M8537

MBZ1

161

MBZ3

M8537

MBOX

RD-PSE-WR
NXM ERR L

161

MBZ3

M8537

MBZ3

CHAN

SEL

TE
BIT

161
161

MEM

REF

161

MBZ 4

M8537

MBOX

MBZ3

M8537

NXM

DATA

26
27

MBZ6
MBC2

MBC?2

M8537
M8531

M8531

CSH
CSH

PAR BIT A H
DATA CLR Tl

161

MBC2

M8531

CSH

DATA

161

MBC2

M8531

CSH

SEL

161
161

32
33

MBC2

M8531

162

MBZ 4

M8537

CHAN

ADR

PAR RIGHT

161

MBC?2

M8531

ERR
VAL

L
L

CSH DATA CLR T2
CLR

LRU

T3
H

MBC2 CSH VAL WR PULSE H

MBC2

CSH

WR WR

HOLD

PULSE

ERR
L

162

MBZ5

M8537

CBUS

17
18

MBZ5
MBZ3

M8537

CSH PAR BIT IN H
MBZ3 SEQUENTIAL RQ

162

MBZ1

M8537

MBZ1

M8537

CHAN

READ

SEL

162

MBZ1

M8537

MEM

162

22
23
24

MBZ3
MBZ4

M8537
M8537

MBZ3
MBZ4

HOLD ERA
NXM T2 H

MBZ4

M8537

MBOX

162
162

25
26

162

H
H

162
162

BUSY

PAR

ERR

PAG5

M8537

PAG

00-17

MBZ6

M8537

CSH

PAR

27 .

BIT

MBC2

M8531

MBC2

CACHE

MBC2

M8531

MBC2

CACHE

MBC2

162

MBC2

162
162

31
32

MBC2
MBC3

162

MBC3

M8531

MBC2

SBUS ADR
A CHANGE

M8531

PAR
H
B

MBC2 CACHE WR 18

M8531
M8531

CACHE

HOLD H
COMING

A H

A
A

H
L

MBC3

163

ANY SBUS

MBC3

M8531

163

MBC3

MBC5

COMING

163

~M8531

CORE

BUSY

MBC3

M8531

CSH

CHANGE

VAL

ALL

DATA
H
ALL H

30
31

MBC3
MBC3

M8531
M8531

CSH
CSH

VAL

163

SEL

MBC3

M8531

CSH

163

WR WR

MBC3

M8531

164

MBC3

M8531

DATA VALID
DATA VALID

DATA

164

MBC3

M8531

MBC

INH

164

MBC3

.M8531

MBC3

MEM

M8531

PHASE

164

MBC4

M8531

ACKN

PULSE

164

MBC4

M8531
M8531

CORE
CORE

ADR
ADR

OUT H
OUT

CHANGE

MBC1

M8531

CAM

28
29

MBC1
MBC4

M8531
M8531

CAM SEL 2 H
CORE DATA VALID

165
165

30
31

MBC4

M8531

MBC4

165

MBC4
MBC4

M8531
M8531

CORE DATA
MBC4 CORE

166

27
.28

166

166
166

30
31

CORE

MBC#4

M8531

MEM

ADR

MBC4
MBC4

M8531
‘M8531

MEM

RD
RQ

MEM

MBC4

M8531

MEM

MBC4
MBC4

M8531
‘M8531

MEM
MEM

RQ
RQ

2
3

H
H

-1

VALID

VALID
RD IN

PROG

PAR

166

MBC4

M8531

MEM

166
167

START
L

MBC4

M8531

MEM

00-08

MBZ2

M8537

EBUS

167

REG

14-26

00-08

MBZ2

M8537

EBUS

REG

14-26

MBC1

REG
REG

27-33
34,35

H
H

167.

27-33

167

34,35

MBZ2

M8531
M8537

170

EBUS
EBUS

CRC6

M8535

CRC

170
170

01
02

CRC4
CRC4

M8535
M8535

170

CRC4 RESET IN
CRC MEM STORE

CRC4

M8535

CRC4

BUF

DONE

ADR

L ENA
L

-2

L-

0 H

DATA

H
H

165

COMING

34
35

REQ

164

SEL

1ST
C

165
165

MBC4

SEL

163
163

PAR

162
162

M8537

REF
L

161
161

SBUS

161

(Cont)

TRUTH

GEN.

INFO.

-75=

KL10 (PA)

DIAGNOSTIC
DF

SORTED

NUMERICALLY

(Cont)

BOARD

NAME

AND

CCwW4

M8534

M8535

CRC4

STORE

170

CCW6

M8534

CCW

170
170

07
08

CCW6
CCW5

M8534
M8534

CCW MEM
CCW ACT

STORE ENA H
FLAG REQ ENA

170

CCW3

M8534

CCW ALU

OUT

170

CCW3

M8534

CCW

OUT

170
170

11
12

CHC1
CHCS

M8533
M8533

CH T0 H
CBUS SEL

170
170

13
14

CHC1
CHC2

M8533
M8533

CHX RESET H
CH RESET INTR

170

CCL5

M8536

CCL

ODD

PAR

170

CCL5

M8536

CCL5

GE4

170

CCL5

‘M8536

CCL WC=0

170

20
21

CHX2

170

CHX3

M8515
M8515

CSH 0 ANY VAL L
CSH USE IN 0 H.

170
170

23
24

CSH6
CSH6

M8513
M8513

CACHE WR IN H
MBOX PT DIR WR

170

CSH2

M8513

CSH2

170

CSH3

M8513

ANY

VAL

170
170

27
28

CSH4
CSH4

M8513
M8513

CSH
CSH

DATA CLR DONE
REFILL RAM WR

170

CSH4

M8513

CSH

EBOX

170

170
170

33
34

170
171

CRC4

CSH5

TRUTH

M8513

CCWF

REQ

ALU

CSH5

PAGE

M8529

CACHE
CCA

REQ

M8529

CSH

WR WD

MBX5
MBX5

~ M8529
M8529

35
00

MBX5
CRC6

M8529
M8535

RQ 1 IN H
CRC CH BUF

COMP

HOLD

M8529

L
L

BIT H
L
2

MB REQ IN H
MBX MEM TO C

ADR

ERR IN

171

CRC4

M8535

CRC

RH20

CRC4

M8535

CRC

OVN

171

M8535

CRC SHORT WC ERR H

ERR

CRC4

171

CRC4

M8535

CRC

LONG

171
171
171
171

05
06
07
08

CCw4
CCw4
CCw4
CCw4

M8534
M8534
‘M8534
M8534

CCW
CCW
CCW
CCW

WDO
WDl
WD2
WD3

REQ H
REQ 1
REQ H
REQ #

171
171

09
10

Cccwl
CCW6

M8534
M8534

171

CHC1

M8533

171

CHC1

M8533

CHX

171

CCL3

M8536

CCL3 MB RIP

171

CHC5

M8533

CHC?2

CCL3

M8536

171
171
171
171
171
171
171
171
171
171

19
20
21
22
23
24
25
26
27
28

CCL4
CHX2
CHX3
CSH5
~ CSH6
.
CSH4
CSH6
CSH7
CSH5
CSH3

M8536
M8515
M8515
M8513
M8513
M8513
M8513
M8513
M8513
M8513

CSH4

"M8513

171

START

CH START INTR H
CCL

ALU

A H

MINUS

CCL CH TEST MB PAR L
CSH 1 ANY VAL L
CSH USE IN 1 H
CHAN RD T5 L
CSH6 WR DATA RDY L
PAGE FAIL T2 L
CSH EBOX LOAD REG H
CSH FILL CACHE RD L
CSH5 CHAN WR T5 L
MB WR RQ CLR NXT L

CSH4 EBOX Tl

30
31
32
33

171

MBX3

M8529

MEM

DIAG

171
172

35
00

MBX5
CRC6

M8529
M8535

RQ 2 IN H
CRC CH BUF

172

CRC3

M8535

CRC

READY

172
172

02
03

CRC3
CRC3

M8535
M8535

CRC LAST WORD
CRC ERR IN H

172
172

05
06

CCW3
CCW3

M8534
M8534

CCW ACT CTR 0 EN H
CCW ACT CTR 1 EN H

CRC3

172

CCW3

172

CCwWl

11
12
13
14

CHC1
CHC5
CHC1
CHC2

172

172
172
172
172
172

172

M8529
M8529
M8529
M8529

M8535

M8534

EN H

ADR
IN

2 H

IN H

CCW ACT CTR 2 EN H
CCW BUF ADR

M8534

CCW BUF ADR

2 L

M8533
M8533
M8533
M8533

CH T2 H
CBUS SEL 2 E H
CHX DONE H
CH DONE INTR H

M8534

CCwl

CRC REVERSE

‘M8534

CCWl

CCL3

CACHE TO MB
CCA SEL 1 H
CSH WR WD 3
MB SEL
1 H

171
171
171
171

172

. MBX2
MBX1
MBX4
MBX2

ERR

CBUS SEL 1 E H

M8533

171

H
H

CCW MEM ADR=( I
CCW CCWF WAITING

CH Tl

M8536

WR TEST

MBX4

REFILL

MBX1

ENA

MBX1
~

CCW WD READY H

171

* %

DRAWING

CODES

170

BIT

FUNCTION

170

READ

CCw BUF ADR 1 L

CCL3 CCWF T2 H

GEN.

INFO.
~-76DIAGNOSTIC
DF

* %
* %

SORTED

NUMERICALLY

NAME

AND

CCL3

M8536

CCL3

M8536
M8515

CCL4 REVERSE H
CSH 2 ANY VAL L

M8515
M8513
M8513
M8513

CSH

USE

CHAN

CACHE

CCA

CYC

DONE
L

CHAN

CHX2

172

CHX3

172

CSH6
CSH6
CSH5-

REQ

CHX3
CSH1

M8513
M8513

CSH LRU 2 H
CSH1 READY TO

172

CSH6

M8513

CSH

USE

HOLD

172

M8513
M8513

CSH

CCA

CYC

172
172

CSH1
CSH2
MBX2

M8529

CACHE

172
172

MBX1
MBX1

M8529
M8529

CCA

172

MBX2

M8529

SEL

172

MBX5

M8529

MEM

172
173

MBX5
CRC6

M8529
M8535

RQ 3 IN H
CRC CH BUF

173
173

CRC2
CRC2

M8535
M8535

CRC2
CRC2

ACT
ACT

CTR
CTR

173

CRC2
CRC2
CCw2
CCw2

M8535

CRC2

ACT

CTR

M8535
M8534
M8534

M8534

CRC2 RAM CYC
CCwW CHA 30
CCW CHA 31
CCW CHA 32
CCW CHA 33
CCW CHA 34

173
173
173
173

EBOX

TO
NO

MATCH
IN

M8534
M8533
M8533

CCW CHA 35
CH T3 H
CBUS SEL 3

173
173

CHC1
CHC2

M8533
M8533

CHX STORE H
CH STORE H.

173

CCL4

173

CCL4
CCL3
CHX2

M8536
M8536
M8536
M8515

CHX3
CSH2
CSH2
CSH2
CHX3

M8515
M8513
M8513
M8513
M8513

CSH5
CSH4
CsH7

M8513

173
173
173

173
173
173
173

173
173

M8513

CSH

CSH4

173
173
173

173
174
174

173

SEL

CCA

A
L

M8529

MBX4

M8529

CHAN

CYC

M8529

MEM

DATA

MBX2
MBX3

M8529
M8529

MB SEL
MEM TO

MBX?2

M8529

SBUS

CRC6

M8535
M8535

CRC CH BUF ADR 4 H
CRC1 ACT FLAG ENA H

CRC1

CACHE

MEM

M8535

CRC

M8535
M8535

CRC3
CRC3

174

CCw2

CCW CHA

174

CHC1
CHC5S
CHC1

M8534
M8533
M8533

READY

CBUS

SEL

M8533

CHX

CTOM

M8533
M8536

CH
CCL

CHAN

REQ

M8536

CCL

CHAN

EPT

M8536
M8515

CCL

CHAN

CSH DIR 0

MEM

174
174

CHC3
CCL3
CCL3
CCL4
CHX4
CHX3

M8515

CSH

USE

174
174

CsSH2
CSH6

CSH2

CORE

PAGE

FAIL

174

-174

174

174
174

CSH1
CSH1

M8513
M8513
M8513
M8513
M8513
M8513
M8513
M8513

174

MBX4

M8529

CACHE

174

MBX1

174

00
01

24-29

CTOM

CSH5
CHA3
CSH5
CSH3

174

OP CODE
OP CODE

CBUS

H
H

PAR ODD H
H

HOLD

ADR

CSH1
CSH1

PMA

CCA

INVAL

MBX3

M8529
M8529

CSH

174

DATA

CODE

MBX6

M8529

MBO

HOLD

174
174

MBX3
MBX?2

M8529

MEM

SBUS

ADR

L
L
L

CSH

SEL

T9,12

EBOX CYC B
CACHE IDLE

174

M8529

H
H-

CSH5 PAGE REFILL
CSH 3 ANY WR L
CSH TO L
CSH

CRC5

RAM

DONE
H

‘CRC3
CRC3

HOLD H
C SEL 1

ADR

174
174

WRITEBACK

EBOX T2

174

174
174

H
H

CSH5 T1 L
CSH4 WRITEBACK

M8513

173

OR
1R

CCL CH MB SEL 1 H
CCL AF T2 L
CSH 3 ANY VAL L
CSH USE IN 3 H
CSH2 ONE WORD RD A L
CSH2 MBOX RESP L
CSH2 RD PSE 2ND REQ EN
CSH LRU 1 H

CSH4
MBX4
MBX?2
-MBX3

173

ADR

173
173

CCL

M8534
M8534

173

CCw2
CCW2
CCW2
CCwW2
CHC1
CHCS5

173

GO A H
H

REQ EN
MB 35 H

SEL

FORCE

172
172

CSH2

(Cont)

TRUTH

CCL4

173

* %

CODES

BOARD

172
172

173
* %

FUNCTION

‘DRAWING

172

172
172

* *

READ

feriiualieriieriie
e

KL10 (PA)

GEN.

INFO.

-77-

KL10(PA)

* %

DIAGNOSTIC

READ

FUNCTION

CODES

SORTED NUMERICALLY

DRAWING

BOARD

NAME

175

CRC6

BUF

175
175

CRC6
CRC6
CRC6

M8535
M8535
M8535
M8535

CRC

175

CRC
CRC

SEL
SEL

1D
2D

L
L

CRC

SEL

175

CRC1

175

M8535
M8534

CRC1

REQ

CCw2

175

CHC1

M8533

CBUS

LAST WORD

SEL

AND

ADR

ENA

CCW CHA 18-23

H
E

175

CHC5

M8533

CBUS

175
175

CHC5
CHC2

M8533
M8533

SEL

175
175

M8536
M8536
M8536

CCL

175

CCL2
CCL2
CCL2

CCL2
CCL

MEM

175
175
175

STORE

REQ

CHX4
CHX3
CSH2

M8515

CSH

DIR

M8515

USE

ODD
H

CSH

1 PAR
ADR 2

M8513

CSH

175
175

CSH6
CSH3

M8513

CSH

USE

M8513

TEST

PAR

175

CHA3
CSH5
CSH3
CSH1

M8513

CSH

175
175
175

M8513
M8513
M8513

CSH5

ANY WR L
T3 L

MBOX

GATE

175
175

CSH4.
MBX4

M8513

CONTR

REQ

CCWF

REQ

ACT

FLAG

EBOX

CSH

REQ

RETRY

VMA

CYC

27-33

M8529

175

MBX1

M8529

CSH

MBX3

175
175

MBX6
MBX5

M8529
M8529

MB1

HOLD

M8529

MEM

175

MBX3
CRC6

M8529
M8535

SBUS DIAG 3 L
CRC CH BUF ADR

M8535

CRC1

MEM

PTRO

M8535
M8535

176

CRC1
CRC1
CRC1
CRC1

CRC1l
CRC1
CRC1

MEM
MEM
MEM

PTR!
PTR2
PrRrR}

H
H
H

176
176

CCw3
CcCw4

M8534

CCL
CCL

WC=3 H
CCW REG

176

M8534

CCW

CHA

176

CcCw2
CHC1

CBUS

ERROR

176

CHC5

M8533
M8533

CBUS

SEL

176

CHC1

M8533

176
176

CHC1
CCL4

M8533
M8536

REVERSE

176

M8536
M8536
M8515

CCL

BUF

CCL

176

CCL2
CCL4
CHX4

START
DIR 2

176

CHX3

M8515

CSH USE ADR 3 H

176
176

CSHo
CSH5

CCA INVAL T4 L
PAGE REFILL T8

176

CSH4

176

CHA3
CSH5
CSH2

M8513
M8513
M8513
M8513
M8513
M8513

CSH7
CSH5

M8513
M8513

CSH

176

MBX4

M8529

176

MBX4
MBX3
MBX6

M8529
M8529
M8529

CACHE TO MB T4
CSH WR WD 0 EN

A
H

M8529
M8529

176
176
176
176

176

176
176
176

176
176

M8535

176

MBX3

176

MBX3

177
177

CRC1
CRC6

M8535

177

CRC6

177

CRC6

177
177

CRC6
CCWo6
CCWob
CCwWé6
CCwW3
CCW3

177

177
177
177

VAL

CORE

DATA CODE

CCL4

CSH

LOAD

INH

STORE

CCW

ADR

H
H

MEM

L
ODD

PAR

EBOX TO L
CSH 2 ANY WR L
CSH T2
L
E

CACHE

PAGE

CYC

REFILL

PAR

MB2

WRITEBACK

HOLD

REFILL

HOLD

DIAG

M8535
M8535

CRC1
CRC6
CRC6
CRC6

M8535
M8534
M8534

PTR DIF=0
CH ADR 0C
CH ADR 1C
CH ADR 2C
CH ADR 3C

H
L
L
L
L

CCW RAM ADR

M8534
M8534

CRC6

SBUS

‘M8534

CCW RAM ADR 4

CCW RAM

ADR

CCL WC=1
CCL WC=2

H
H

ADR
REQ

PAR
H

177
177

CCw4
CHC1

M8534
M8533

CCW ODD
CH CBUS

177

CHC5

M8533

CBUS

177

CHC2
CHCZ2

CONTR

START

177

CCL1

M8533
M8533
M8536

177

CCLl

ERR

REQ

177
177

CCLb6
CCL3

M8536
M8536

CCL6
CCL3

CSH
MEM

CHAN CYC
PTR EN H

177

CHX4
CHX3

M8515
M8515

CSH

DIR

CSH

USE

ADR 4

177

CSH4

MBX3

M8535

14-17
6

REQ

CYC

SEL

175

REQ

ONE WORD WR TO L
MBX4 CACHE TO MB
CCA

(Cont)

TRUTH

PAR

ODD

L
H

GEN.

INFO.

'KL10 (PA) DIAGNOSTIC READ FUNCTION CODES SORTED NUMERICALLY (Cont)

M8513
M8513
‘M8513

NAME AND TRUTH
PAGE REFILL ERROR L
CSH6 DATA DLY 1 L
CSH4 PAGE FAIL DLY H
CSH 0 ANY WR L
CSH5 PAGE REFILL T10 L
RD PAUSE 2ND HALF L.
CSH4 EBOX WR T4 L

M8529

WRITEBACK T2 L

BIT

DRAWING BOARD

177
177

CSH6

M8513

177
177

24
25

CsHA4
CHA3

- M8513
M8513

177
177
177
177
177
177
177
177

177

CSH6

©~
.

CSH5

CSH2
CSH4

30
31
32
33
34

MBX4

and

programs

the

CCA ALL PAGES CYC H
CSH WR WD 1 EN H
MB REQ HOLD H
MB3 HOLD IN H
RQ 0 IN H

M8529
M8529
M8529
M8529
M8529

MBX1
MBX4
MBX2
MBX6.
MBX5

TRACON

M8513

NOTE

1ll-based

interpret

all

diagnostic

read

functions which are not preceded with
either a single or double asterisk [(*)
or (**)] as single bits; as such, they
are printed out by bit position and/or
read functions
Diagnostic
name.
preceded by a single ‘asterisk (*) are
interpreted as registers and are printed
Diagnostic read functions
out as such.
which are preceded by a double asterisk
(**) may be interpreted and printed as
as a register
single bits or
either
the
depending on' the program doing
interpretation.

GEN.

INFO.

-79-

KL10 (PA)

DIAGNOSTIC

READ

FUNCTION

CODES

SORTED ALPHABETICALLY

DRAWING

BOARD

NAME

162

MBC3

M8531

164
127

MBC4
EDP3

M8531

ACKN

PULSE

M8512

132
137

IRD4

TRUTH

COMING

M8522

CRY

-02

EDP3

M8524

AD
AD

CRY
CRY

-02

IRD4

‘M8522

'AD

CRY

IRD4

M8522

137
137

‘IRD4

M8522

AD
AD

CRY
CRY

18
24

137

IRD4

M8522

CRY

132

EDP3
IRD3

M8524

OVERFLOW

136

M8522

AD=0

15X

VMA3

M8523

ADR

BRK

126
137

EDP3
IRD4

M8512
M8522

ADX

CRY

13-35

mmom
e

136
131

AND

CHANGE

**NOTE

FLG

137

IRD4

M8522

ADX

CRY

170

CSH3
APR2

M8513
M8539

ANY

VAL

116

HOLD

APR

ANY

EBOX

ERR

110

APR2

M8539

APR

INTERRUPT

112
110

APR2
APR2

M8539
M8539

APR

DIR

APR

DIR

111

APR5

M8539

APR

CURRENT

111
111

APRS

APR5S

M8539

APR
APR

CURRENT

BLOCK

CURRENT

BLOCK

111

APR3

M8539

APR

CWSX

ERR

115
115

"APR6
APR3

M8539
M8539

APR
APR

EBOX
EBOX

CCA

APR6

M8539

APR

EBOX

EBR

115

APR6

M8539
M8539

APR

EBOX

ERA

115

APR6

APR

H
DISABLE

APRG6

M8539

EBOX

LOAD

115

REG

APR

EBOX

READ

REG

115
117

APRG
APR3

M8539
M8539

APR

EBOX

SBUS

DIAG

APR

EBOX

SEND

F02

117

APRG

M8539

APR

EBOX

SPARE

116

APR6

M8539

APR

EBOX

UBR

117

APR3

M8539

APR

EBUS

DEMAND

116

APR3

M8539

APR

EBUS

FOl

116
115

APR3
APR3

M8539
M8539

APR
APR

EBUS
EBUS

REQ

116
114
113

APR6
APR4
APR3

M8539

APR

M8539
.
M8539

APR

F02

APR

FETCH

COMP

APR

M8539

APR
APR

FM
FM

ADR
ADR

1 H
10 H

APR

ADR

2
4

APR4

M8539

APR

FM ADR

114

APRS

M8539

APR

BLOCK

114

APRS

M8539

APR

BLOCK

omom

M8539

APR4

114
114

APRS
APR3

M8539
M8539

APR

BLOCK

APR

ODD

PARITY

APRI1

M8539

APR

I/O

ERR

APR1

M8539

APR

I/O

112

ERR

APR1
APR1

M8539

APR

PAR

ERR

PAR

ERR

APR

APR5S

M8539

APR

MBOX

CTL

APR5

M8539

APR

112

MBOX

CTL

APR1

M8539

110

APR

NXM

ERR

APR1
APRS

M8539
M8539

APR

NXM

ERR

APR

BLOCK

111

APR5

M8539

APR

BLOCK

APR5

M8539
M8539

APR

BLOCK

APR

SEC

APR3

jusiin=jiac
e siien)

111
111
111

usfusiian

M8539

114
115

111

APR3

M8539

APR

SEC

111
111

APR3
APR3

M8539
M8539

APR

SEC

APR

SEC

111

APR3

M8539

APR

SEC

116
117

APR5
APR5

M8539
M8539

APR

DIR

APR

112

APR2

M8539

APR

PWR

FAIL

110

APR2

M8539

APR

PWR

FAIL

113
112

APR3
APR2

M8539
M8539

110
112

APR2
APR1

M8539
M8539

110

APR1

M8539

APR READ

COMP

APR

ADR

APR

ADR

APR

SBUS

ERR

SBUS

ERR

APR>

M8539

APR

SET

110
112

PAGE

APR2

M8539

APR

SWEEP

BUSY

APR2

M8539

APR

SWEEP

DONE

APR

IN'H

-115

H
H

jac]

112

110
110

APR3

114

RAM

APR4

M8539

RETURN

114

APRA4

114
114
114

REFILL

BLOCK

117

ERR

FAIL

GEN.

INFO.
- -80-

KL10 (PA) DIAGNOSTIC READ FUNCTION CODES
SORTED ALPHABETICALLY (Cont)
DF

DRAWING

BOARD

NAME AND TRUTH

110
113

APR2
APR3

M8539
M8539

APR SWEEP

116

APR2
APRS

M8539

117

APR5S

113

APR3

120

EDP1

M8512
M8530

125

EDP2
EDP4
EDP4

-M8512
M8512

ARX 0 TO 35 H
BR 0 TO 35 H
BRX 0 TO 35 H

170

MBX1

M8529

CACHE

BI T

171
172

MBX?2
MBX2
MBX4

M8529
M8529
M8529

CACHE

MB
MB

CACHE

35
T2

MBX4

M8529
M8513

CACHE

M8531

CAM

SEL

M8531
M8533
M8533
M8537
M8537

CAM SEL

M8533

174
176
170
165"

CSH6
MBC1

165
176

MBC1
CHC1

175

CHC1

161

MBZ5
MBZ5
CHC1

162
174

ARMM 12

M8512

CBUS

ERROR

CBUS

LAST WORD

CBUS

PAR

LEFT

CBUS

PAR

RIGHT

CBUS

REA DY

0
l1
2

EH
EH
EH

PAGES CYC
DONE L

M8533
M8533
M8533

CBUS

SEL

CBUS

SEL

3
4

EH
EH

175

CHCS
CHC5
CHC5

CBUS

SEL

176
177

CHC5
CHC5

M8533
M8533

CBUS

SEL

6
7

E
E

CBUS

177

M8529
M8513
M8513

CCA ALL
CCA CYC

176

MBX1
CSH6
CSH6

CCA

INVAL T4

170

MBX1

M8529

CCA

REQ

171

MBX1
MBX1

M8529
M8529

CCA SEL
CCA SEL

CCL3
CCL3
CCL2
CcCcw4
CCL?2
CCL4
CCL4
CCL4
CCL3
CCL3
CCL4
CCL2

M8536

174

172

2172

173
171

176
176
175
173

173
171

174
174
174
175

CBUS
CBUS
CBUS

173

M8533
M8533
M8533

172

E
TE

CHCS
CHC5
CHC5

170
171

SEL
SEL
SEL

2 H
CCL AF T2 L

. M8536

MINUS

CCL

ALU

CCL

CCW REG LOAD
CCWF REQ H

M8536
M8534

CCL BUF ADR 3

M8536
M8536
M8536

CCL

M8536
M8536
M8536

CCL CH TEST

H
H

1 H
2 H

CCL CH MB SEL
CCL CH MB SEL

CCL CHAN EPT H

PAR L

CCL CHAN REQ H
CCL CHAN TO MEM H
CCL MEM STORE REQ H

M8536
M8536

CCL ODD WC PAR H
CCL START MEM L

M8536

170
177

CCL5
CCL4
CCL5
CCW3

177
-176

CCW3
CCW3

M8534

CCL
CCL
CCL
CCL

177

CCL1
CCL2
CCL3
CCL3

M8536
M8536
M8536
M8536

CCLl ERR REQ H
CCL?2 ACT FLAG REQ
CCL3 CCwW F T2 H
CCL3 MB REQ T2 H

CCL3
CCL3
CCL4
CCL4
CCL5
CCL6
CCW3
CCW3
CCW3
CCW5

M8536
M8536

170
176

175
172
172
171
177

172
176

170
177

172
172
172
170
170
170

172
172
172
170

171

*
*

MCL5

o ]

APR WRITE COMP H

AR 12 TO

102

M8539
M8539
M8539

115

DONE IN H
USER COMP H
APR WR BAD ADR PAR L
APR WR PT SEL 0 H
APR WR PT SEL 1 H
APR

176
175

CCW3
CCW3

CCwWl
CCwWl
CCW1
CCW6
CCW6
CCW2
CCW2

M8536
M8536
M8534

M8536
M8536
M8536
M8536
M8534
M8534
M8534
M8534
- M8534
M8534
M8534
M8534
M8534

WC=0
WC=1
WC=2
WC=3

CCL3
CCL3
CCL4
CCL4
CCL5
CCL6

MEM

L
H
H

RIP A H
PTR EN

WwC

GE4

REV ERSE

STO RE

CCW

CHAN
CTR 0
CTR 1
CCwW A CT CTR 2
CSH

CCW A CT
CCW ACT

CYC

EN H
EN H
EN H

FLAG REQ E
C2 OUT H
C8 OUT H
CCW B 8)3) ADR 0 L
CCW B UFr ADR 1 L
CCW B UrF ADR 2 L

CCW

ACT

CCw

A LU

CCw

ALU

M8534

M8534
M8534

CCW CCWF REQ ENA
CCW CCWF WAITING
CCW CHA 14-17 H

M8534

CCw CHA

18-23

GEN.

INFO.

-81-~

KL10 (PA)

DIAGNOSTIC

SORTED
DF

FUNCTION

CODES

(Cont)

DRAWING

BOARD

NAME

174

CCW2

M8534

CCW CHA

24-29

173

M8534
M8534
M8534
M8534

CCwW

CHA

CCW CHA
CCW CHA

31
32

173

CCW2
CCW2
CCW2
CCW2

CCW2

M8534

CCW CHA

173
173

CCW

CHA

CCW2

M8534

CCW

CHA

MEM

ADR=0

173

171
170
177
177

AND

TRUTH

CCwWl

M8534

CCW

CCwW4

M8534

CCW

MEM

STORE

CCW

ODD

ADR

PAR

CCW RAM

ADR

1
2
4

CCW6
CCW6

M8534
M8534

177
177

CCW6
CCW6

M8534
M8534

CCW RAM
CCW RAM

ADR
ADR

170

M8534
M8534
M8534
M8534

CCW WD

READY

171
171

CCw4
CCw4
CCw4
CCw4

CCW WD0
CCW WDl

REQ
REQ

H
H

WD2 REQ

171
177

CCw4
CHC1

M8534
M8533

CCW WD3
CH CBUS

177

CHC2

M8533

175

CHCZ2

M8533

CONTR

174
172

CHC3

M8533

CTOM

CHC?2

M8533

DONE

176
170

CHC1

M8533

RESET

176

M8533
M8533
M8533
M8533

REVERSE

171

CHC1
CHCS
CHC2
CHC2

173
170

CHC2
CHC1

M8533
M8533

171

162

CHC1
CHC1
CHC1
MBZ4

M8533
M8533
M8533
M8537

160
160

MBZ3
MBZ4

M8537
M8537

171

CSH5
MBZ1
CSH5

M8513
M8537
M8513

171

175
177

172
173

172
172
173
174

172

170
171
173

o mom
oI o

173

BIT-

READ

ALPHABETICALLY

CHC?2

M8533

CCW

H
H
H
H

REQ H
REQ H

CONTR

CYC

REQ

INTR

REQ

INH

INTR

SEL

START

INTR

STORE

H
H
H
H

CH TO
CH T1
CH T2
CH T3

H
ENA
H

CHAN

ADR

PAR

ERR

CHAN

NXM

ERR

CHAN

PAR

ERR

CHAN

READ

CHAN

CACHE

CSH6

M8513

CHAN

MBX2
CHC1
CHC1

M8529
M8533
M8533

CHAN WR CYC
CHX CTOM H

CHX

DONE

CHC1
CHC1
CHC1

M8533
M8533
M8533

CHX
CHX

RESET
H
START H

CHX

STORE

103
106

CLK4

M8526

CLK5

M8526

CLK 1777 EN H
CLK AR/ARX PAR CHECK

101

CLK5

M8526

CLK

BURST

101

CLK5

M8526

CLK

BURST

101

CLK5

M8526

CLK

BURST

101

CLK5

M8526

CLK

BURST

100
101

CLK5
CLK5

M8526
M8526

CLK BURST

128

101

CLK5

M8526

CLK BURST
CLK BURST
CLK BURST

16
32

H
H

100

CLK5

100
103

CLK5

CLK2

‘M8526

M8526

CLK
CLK

BURST CNT=0
BURST L

105~
104

CLK5
CLK3
CLK5
CLK3
CLK4
CLK5

M8526
M8526
M8526

CLK

CRAM

PAR

CLK

CRAM

PAR

ERR

CLK DRAM

PAR

CHECK

106
103

M8526

CHECK

107
106

CLK5

M8526
M8526
M8526
M8526

CLK

EBOX

EDP

DIS

102

CLK4

M8526

CLK

EBOX

REQ

104

CLK3

‘M8526

CLK

EBOX

SOURCE

104

CLK?2

M8526

CLK

103
105

CLK5S

M8526

CLK

DRAM

PAR

ERR

CLK

EBOX

CLK

EBOX

CRM

DIS

CLK

EBOX

CTL

DIS

CLK1

M8526

CLK

EBUS

CLK

CLK5
CLK3
CLK1

M8526
M8526
M8526

CLK

ERR

STOP

CLK

ERROR

CLK5
CLK3
CLK4

M8526
M8526
M8526

CLK

PAR

105
102

CLK

PAR

CLK

FORCE

107
106

CLK5
CLK3

M8526
M8526

CLK
CLK

FS
FS

102

104

CLK ERROR

EBOX

100

107
107

STOP

CHECK
ERR

1777

CHECK
ERROR

L
H

INFO.
-80~

KLlO(PA)

DIAGNOSTIC

READ

FUNCTION

SORTED ALPHABETICALLY

CODES

(Cont)

DRAWING

BOARD

NAME

102

CLK2
CLK4

M8526

CLK

M8526
M8526

CLK

INSTR 1777

CLK MB

CLK5
CLK5

M8526

CLK

MBOX

CYCLE

M8526

CLK

MBOX

RESP

SIM

CLK4

M8526

CLK

PAGE

FAIL

CLK4
CLK5
CLK5
CLK1

M8526
.
M8526
M8526
M8526

.CLK

PAGE

FAIL

CLK
CLK

RATE
RATE

SEL
SEL

1
2

CLK

SBUS

CLK

M8526
M8526

CLK

SOURCE
SOURCE

M8526

CLK

SYNC

M8525
M8525

CON

137
133

CLK5
CLK5
CLK3
CON4
CON4
CON4

AR 36 H
ARX 36 H

. M8525

CON

ARX

131
133

CON3
CON2

M8525
M8524

CON

CACHE

CON

CLR

137
132

CON2
CON1
CON2

M8525
M8525
M8525
M8525

CON

M8525
M8525

133
117

CON1
CON1
CON1
CON3
CON3
CON5

134
136

CON5
CON5

131

CON3
CON2

103

CLK4

103
104
105
102
107
107

106
100
105
104

102
136

133
134

CON1

132
132
133

135

134

M8525
M8525
M8525
M8539

CON

AND

TRUTH

L
XFER

DIS

H
H

LOADED

LOAD

PRIVATE

CON

DELAY

CON

EBUS

CON

WRITE

REQ

PAR

M8525

CON

WRITE

PAR

M8525

CON FM XFER L

M8525

CON KI10

PAGING

MODE

COND

CON

LOAD

ACCESS

LOAD

DRAM

CON2

135
135

CON1
CON5

M8525

135

CON2

136
137

CON2
CON2Z

134

CON2
CON4
CONS

L
L

M8525

CON

LOAD

M8525

CON

LOAD

SPEC

CON

MBOX WAIT

M8525
M8525
M8525
M8525

CON

NICOND

CON

NICOND

CON NICOND

08
09

H
H

CON

NICOND

TRAP

M8525
M8524

CON

PC+1

INH

CON

CYCLE

M8525
M8525

CON

DISMISS

INSTR

CON

SKIP EN

40~-47
L

CON

SKIP

50-57

137

CON1
CON1
CON3
CON3
CON3
CON3

131

CON3

- M8525

CON

135

CON4
CON4

- M8525

CON

CON4
CON4

M8525

CoN1

M8525

" CON1
CON3
CON2

M8525
M8525
M8525

CON

CON3
CON3

M8525

CON3 CACHE LOOK EN H

CON3
CON4

M8525

132

133

" CONS5

132

CON5

164
164

MBC4
MBC4

- M8531

163

MBC5

134

136

137.

137
136
130
135

131
130

.
130

M8525

CON

M8525
M8525
M8525

CON
CON
CON

SR
SR
SR

01
02
03

H
H
H

CON

TRAP

M8525

UCODE STATE
UCODE STATE
CON UCODE STATE
CON UCODE STATE
CON VMA SEL 1 L

CON VMA SEL
WR

CON2

EVEN

INSTR

01
03
05
07

PAR ADR
H

CON3

EVEN

PAR

CON3

EVEN

PAR DIR

M8525

CON4

LOADED

M8525
M8525

CONS5

MEM

CYCLE

CONS5

PI CYCLE

M8531

CORE
CORE

ADR
ADR

M8531

CORE

BUSY

CORE

BUSY

34
35

DATA

L
H

H
H

B
H

160

MBZ1

M8537

165

MBC4

M8531

CORE DATA VALID -1

MBC4

M8531

CORE

CRrAl
CRAl

M8511
M8511

CR
CR

A DR
ADR

145

CRAL

M8511

A DR

145

"CRAl

M8511

145

CRA1l

M8511
M8511

ADR
A DR

03
04

CR ADR

M8511
M8511

A DR

06
07

M8511

A DR

145

144

CRA2

144

CRA2
CRA2

144

"CRA2

00
01

VALID
Be s By Bheo Les Bes B

145

DATA

s itsviaviia
viius e s lius it sifasi

165

[usfis il

135
136

M8525

REL

CON

134

COND/LOAD VMA HELD
COND/MBOX CTL L
CON COND/SEL VMA L
CON COND/VMA GETS # H
CON

M8525

134

-CON

M8525

CONS5

INSTR

COND ADR 10 H
CON COND EN 00-07 L
CON COND INSTR ABORT

CON2

137
133

H
H

1
2

SEL
SEL

136
132

133
134

H
L

o> B> B

GEN.

H
H

GEN.

INFO.

-83-~

DIAGNOSTIC

SORTED

READ

FUNCTION

ALPHABETICALLY

CODES

(Cont)

DRAWING

BOARD

NAME

144
144

CRA2
CRA2

ADR

141

M8511
M8511

CR ADR

CRA3

M8511

CRA

141

CRA3

M8511

AND

TRUTH

DISP

CRA

DISP

141

CRA3

M8511

CRA

DISP

141

CRA3

M8511

CRA

DISP

141

CRA3

M8511

CRA DISP

141
147

CRA3
CRA3

CRA

DISP

CRA

LOC

147
147

CRA

LOC

CRA
CRA

LOC
LOC

02
03

146
146

CRA3
CRA3
CRA3
CRA3
CRA3
CRA3

M8511
M8511
M8511
M8511
M8511
M8511
M8511
M8511

CRA
CRA

LOC
LOoC

O4
05

CRA

LOC

146
146

CRA3
CRA3

M8511
M8511

CRA

LOC

CRA

LOC

O7
08

146

CRA3

- M8511

CRA

LOC

146

CRA3

M8511

CRA

LOC

147

CRM5

M8528

CRAM

00-0 3

147

CRM5

M8528

CRAM

04-0 7

147
147

CRM5
CRM5
CRM5

M8528
M8528
M8528

CRAM

08-1 1

CRAM

146
146
146

12-1 5
l6-1 9

CRM5
CRM5

M8528
M8528
M8528

. CRAM

CRM5

CRAM

28-3 1

146
146

CRM5
CRM5

M8528
M8528

CRAM
CRAM

145

CRM5

M8528

CRAM

32-3 5
36-3 9
40-4 3

145
145

CRM5

M8528
M8528

CRAM

145

CRM5

M8528

CRAM

CRM5
CRM5

M8528
M8528

CRAM

52-5 5
56-5 9
60 H

144

CRM5

M8528

144

CRM5
CRM5

CRAM
CRAM
CRAM
CRAM

62
64
66
68

H
H
H
H

147

145
144

CRAM

20-2 3
24-2 7

44-4 7
48-5 1

H
H

CRM5

144
144

CRM5
CRM5

M8528
M8528

CRAM
CRAM

70
72

144

CRM5

M8528

CRAM

144

CRM5
CRM5

CRAM 78 H

CRAM

144

CRM5

M8528
M8528
M8528

144
144

CRM5
- CRM5

M8528
M8528

144

CRAM

PAR

CRAM

PAR

jusfijanjiungiasiges)

144

M8528
M8528
M8528

144

jorfiariincipuniusiineiasiitasiiariiasiiveiiasfiuviieolusiic
s linsiiasiiar]

147
147

PARITY

CRAM PAR

144

CRM5

M8528

CRAM

PAR

144

CRM5
CRM5

M8528
M8528

CRAM

PAR

144

CRAM

144

CRM5

M8528

CRAM

PAR

144

CRM5
CRM5

M8528
M8528

CRAM

PAR

CRAM

PAR

144

CRM5

M8528

CRAM

170

M8535
M8535
M8535

CRC

BUF

CRC

‘BU F

172

CRC6
CRC6
CRC6

CRC

BU F

173
174

CRC6
CRC6

M8535

CRC

BU F

M8535

- CRC

BU F

175

CRC6

M8535

CRC

171

josfiiaiaciiuciian)

144

PAR

176

BU F

CRC6

M8535

CRC

BU F

172
172

CRC3
CRC3

M8535
M8535

CRC

ERR

171

CRC4

170

CRC

LAST

CRC4

M8535

CRC

LONG

M8535

CRC MEM

STORE

M8535
M8535
M8535
M8535
M8535
M8535

CRC

OVN

ERR

CRC

READY

171

CRC4

172

CRC3
CRC3

172

171

CRC4

175
175

CRCO6
CRC6

175

CRC6

M8535

171

174
174

CRC4
CRC5
CRC1

M8535
M8535
M8535

175
176

CRC1
CRC1

176

CRC1

176

CRC1

WORD

CRC

REVERSE

CRC

RH20
SEL
SEL

CRC

SEL
WR

4D
RAM

IN .H:

IN H

L
L

L
ERR"H

CRC1

ACT

M8535
M8535

CRC1
CRC1

MEM

PTRO

M8535
M8535

CRC1

MEM

PTR1

CRC1

MEM

PTR2

FLAG
REQ

H-

CRC SHORT WC

CRC

ENA

ERR
1D
2D

ERR

-IN

CRC

-CRC

L Iommmnm

KL10 (PA)

ENA

GEN.

INFO.
-84-

DIAGNOSTIC

READ

FUNCTION

CODES

SORTED ALPHABETICALLY .(Cont)

BIT

DRAWING

BOARD

NAME

AND

TRUTH

176

04
00

CRC1

M8535

PTR3

M8535

CRC1
CRC1

MEM

CRC1

PTR

DIF=0

173
173

CRC?2

M8535

ACT

CRC2

M8535

ACT

CTR
CTR

173

CRC2

M8535

CRC2
CRC2
CRC2

ACT

CTR

173

CRC2
CRC3

M8535
M8535

CRC2

RAM

CYC

CRC3

177

174
174

OR
1R

CRC3

M8535

CRC3

OP CODE
Op CODE

CRC4
CRC4

M8535
M8535

CRC4
CRC4

DONE IN H
RESET IN L

170

CRC4

STORE

177

CRC6
CRC6

M8535
M8535
M8535

CRC4

177

CH
CH

177

CRC6

M8535

177
170

CRC6

- M8535

CRC6
CRC6
CRC6

171
175
172

CHX2

M8515

CSH

CHA3
CHX2

M8513
M8515.

CsH

CHA3
CSH3

M8513
M8513

CsH

177

176
173
174
174

M8515
M8513
M8515
M8513

CRC6
CSH

CHX2
CHA3
CHX2
CHA3

CSH
CSH

CsH

CSH

00
01

0C
1C

CH ADR
CH ADR

2C
3C

ANY

VAL

ANY

H
H

ADR
ADR

WwhoNNHE-=OO

170
170

juafiaciiun

KL10 (PA)

L
L

L
L
L

ANY

VAL

ANY

VAL

ANY

VAL

ANY

WR L

L
L

172

CSH1

- M8513

CSH
CsH

CCA

CYC

174

MBX1

M8529

CSH

CCA

INVAL

175
173

MBX1

M8529

CSH

CSH7

M8513

CsH

CCA VAL CORE H
CCA WRITEBACK L
DATA

ADR

PMA

CSH

160

MBC?2

M8531

CsH

CLR

DONE

170

CSH4
MBC2
MBC2

M8513
M8531
M8531

CSH

DATA

CLR

DONE

CSH

DATA

CLR Tl

CSH

DATA CLR T2

174

MBC2
CHX4

M8531
M8515

CSH
CSH

DATA CLR T3 L
DIR O PAR ODD

175

CHX4

M8515

CcsH

DIR

PAR ODD

176

CHX4
CHX4
CSH7

M8515
M8515
M8513

CSH
CSH

DIR
DIR

2
3

PAR ODD
PAR ODD

CSH

M8513
M8513
M8513
M8537
M8513
M8513

CSH

LOAD

CsH

RETRY

160
171
173

CSH6
CSH2
CSH4
MBZ1
CSH7
CHX3

172
175

CHX3
CSH1

M8513
M8513

CSH
CsH

161

MBZ6
MBZ6
MBZ5
CSH4

M8537

CSH

MBC2
CSH5
CSH5

M8531
M8513
M8513

CHX3
CHX3
CHX3

M8515
M8515
M8515

172
173

CSH6
CHX3
CHX3
CHX3
CHX3

174

175
163

161
161

161

177
176
171
175
170

WRITEBACK

EBOX
EBOX
CsH. EBOX

REG
REQ

CSH
CSH

EN CSH DATA L
FILL CACHE RD

CSH

LRU
LRU

CYC

L
A

M8537

CSH ‘PAR

BIT

M8537
M8513

CSH

PAR

BIT

CcshH

REFILL

RAM

CSH

SEL

CSH

CsH

USE

CSH

M8513
M8515
M8515
M8515
M8515

csH

CHX3

M8515

CSH6
MBC3
MBC3

"M8513
M8531
M8531

CSH
CsH

VAL

SEL

ALL

163

CSH

VAL

DATA

163

MBC3

M8531

CSH

SEL

ALL

176

MBX4
MBX4

M8529

CsH

WR WD.0

M8529

CSH

1 EN
WR WD

M8529
M8529

CsH

163

MBX4
MBX4
MBC3

M8531

CSH

174
174

CSH1
CSH1

M8513
M8513

CSH1
CSH1

CACHE IDLE
EBOX CYC B

172

CSH1

M8513

~ CSH1

READY
- TO GO

174
172

CSH2
.CSH2

M8513
M8513

CSH2
CSH2

E CORE RD RQ A
EBOX REQ EN L

173
173
173

CSH2
CSH2
CSH2

M8513
M8513
M8513

CSH2
CSH2
CSH2

MBOX

176

175
176
177
172
170

171

177
170
171

LRU

ADR

"CSH USE ADR

2
3

USE

ADR

USE

HOLD

CsH

USE

CSH

USE

IN 1

CSH

CsH

USE
USE

CSH

USE

H
H
H

WR WD
2 EN
CSH WR WD 3 EN
WR

WR DATA

ONE

RESP
WORD

PSE

jasfiiusiasiiaviiaciias

161
174

m m o

170

BIT

162
162

PAR

L
L

H
L

L
RD

2ND

REQ

GEN.

INFO.

-85~

KL10 (PA)

DIAGNOSTIC

SORTED

READ

FUNCTION

ALPHABETICALLY

CODES

(Cont)

DRAWING

BOARD

NAME

AND

170

CSH2

M8513-

CSH 2

WR TEST

176
171

CSH4
CSH4
CSH4
CSH4
csH4
CSH4

M8513
M8513

CSH 4

EBOX
EBOX

L
L

M8513
M8513
M8513
M8513

CsH 4

EBOX

CsH 4

EBOX WR T4 L
PAGE FAIL DLY H
WRITEBACK Tl A H

173
177
173

CSH 4

TRUTH

171
170

CSH5
CSH5

CSH 5

- CSH 5

CHAN

M8513

PAGE

WR T5 L
REFILL COMP

177

CSH5

M8513

CsH 5

PAGE

REFILL

T10

174

CSH5

M8513

CSH 5

173
175

REFILL

M8513
M8513.

T9,12

CSH5
CSH5

CSH 5

PAGE
Tl L

CSH 5

M8513

177
171

CSH6
CSH6

M8513
M8513

CSH 6

CTL1

M8527

CTL

LONG

CTL1
CTL1

M8527

CTL

ADX
ADX

CRY

105

DATA
WR

DLY

DATA

RDY

CTL2

M8527
M8527

CTL

100

CTL

00-08

LOAD

104
101

CTL2
CTL2

M8527
M8527

CTL
CTL

AR
AR

00-11
09-17

CLR H
LOAD L

CTL2
CTL2

M8527

CTL

12-17

101

M8527

CTL

ARL

SEL

100

- CTL2

M8527

CTL

ARL

SEL

105

CLR

103

CTL2

M8527

CTL

ARL

SEL

106
100

CTL2

CTL

ARR

CLR

CTL

ARR

LOAD

101

CTL?2

M8527
M8527
M8527

CTL

ARR

LOAD

103

CTL2

M8527

CTL

ARR

SEI

102

CTL2

CTL

ARR

SEI.

CTL

ARX

LOAD

CTL

ARXL
ARXL
ARXR

SEL
SEL
SEL

1
2
1

CTL?2

102

CTL2
CTL2
CTL2
CTL2

M8527
M8527
M8527

CTL2
CTL1

M8527
M8527

CTL

ARXR SEL 2 H
COND/AR GET S

CTL1

M8527

CTL

DISP

107
136

CTL1
CTL1

M8527

CTL

M8522

CTL

INH
INH

104

CTL1
CTL2
CTL2

M8527

.CTL

M8527
M8527
M8527

CTL

106
102

103

105

104
106
103
102

CTL2

CTL
CTL

RET

CRY
CRY

LOAD

H
H
H

EXP

L
L

CTL

MQ
MQ

SEL
SEL

1
2

CTL

MOM EN

H
H

101
101

CTL2
CTL2
CTL?2
CTL1
CTL1

104

. CTL1

M8527
M8527
M8527
M8527

102
136

CTL1
CTL1

M8527
M8522

CTL

100

CTL1

M8527

CTL

100

M8527

CTL

M8527
M8527

CTL

105

CTL1
CTL1
CTL1

163
164

MBC3
MBC3

- DAT A VALID
A OUT H
M8531
M8531
DATA VALID B OUT H
M8527
DIA G LOAD EBUS REG

CTL3

107

130
130

CTL3
CRA3
CRA3
CRA3
CRA3
CRA3
CRA3
IRD1
IRD1

130
131

IRD1
IRD1

140
140
140

140

131

IRD1

CTL

MQM
MQOM
SPEC

CALL

CTL

SPEC

MTR

CTL

SPEC/CLR FPD H
SPEC/FLAG CTL H
SPEC/GEN CRY 18 H
SPEC/GEN CRY 18 H
SPEC/SAVE FLAGS L
SPEC/SCM ALT H
SPEC/SECTION HOLD
SPEC/SP MEM CYCLE

M8527
M8511

CTL

SEL
SEL

DIAG MEM
DIS P

M8511

DIS P

04
EN

A H
00-03

M8511

DIS P

M8511
M8522
M8522
M8522
M8522
M8522

EN 00-07
EN 30-37
DR ADR 00
DR

ADR

ADR 02
ADR 03
DR ADR 04
DR

IRD1

M8522

IRD1

ADR
ADR

05
06

IRD1

ADR

131
133

IRD1

M8522
M8522
M8522
M85272
M8522
M8522
M8522
M8522

131

ADR 08
A 00

133

IRD1

133

IRD1
IRD1

133

IRD1

- M8511
M8511

131

133

H
H

RESET
A

131

IRD1

1
2

DRA M

.DRA M

DRA M

jusfiiasiiasiiasiinsiiosiiesiiaslion

107
140
140

CTL

mm P PP

103

M8527
M8527

Tmm

107

18
18

105
104

107

H
A

M8527
M8527

CTL

106
106

CsH 6

H
H

GEN.

INFO.
-86-

DIAGNOSTIC READ FUNCTION CODES
SORTED ALPHABETICALLY (Cont)

KL10 (PA)

* %
*%

* %
*
*%
*

*
*

*
**
*
*
*
*
Ll
**
*
*%

DRAWING BOARD
M8522
IRD1

135
135
135
135

14
15

IRD1
IRD1
IRD1
IRD1

176

CSH?2

PIC4

14
15

102

DRAM J 07 H
DRAM J 08 H

DRAM J 09 H
DRAM J 10 H

M8522
M8522

DRAM ODD PARITY H

M8522

IRD1

M8522

DRAM PAR H

PIC4
PIC4

M8532
M8532

EBUS CS00 E H
EBUS CS0l E H

M8513

E CACHE WR CYC H

EBUS CS02 E H

167

00-08

MBZ2

M8537

EBUS REG 00-08 H

167
120
120
120
120
120
120
120
120
120

34,35
00
01

MBZ2
EDPl1
EDP1
EDP1
EDP1
EDP1
EDP1
EDP1
EDP1
EDP1

M8537
M8512
M8512

EBUS REG 34,35 H
EDP AR 00 H
EDP AR 01 H
EDP AR 02 H
EDP AR 03 H
EDP AR 04 H
EDP AR 05 H
EDP AR 06 H
EDP AR 07 H
EDP AR 08 H

02
03
04
05
06
07
08

EBUS

M8512
M8512
M8512
M8512
M8512
M8512
M8512

EDP1

M8512

DEMAND E H

EBUS REG 14-26 H
EBUS REG 27-33 H

M8537
M8531

MBZ2
MBC1

14-26
27-33

167
167

EBUS CS04 E H
EBUS CS05 E H
EBUS CS06 E H

M8532

PIC2

102

133
133

*%
*%
*%
*%

H
H
H
H

= EBUS CS03 E H

01
02
03
04

M8532
M8532
M8532
M8532

J
J
J
J

M8532

120
133
133

* %

DRAM
DRAM
= DRAM
DRAM

PIC4
PIC4
PIC4
PIC4

103
102
102

*%
* %
*%

NAME AND TRUTH
H
DRAM B 02

14
11
12

102

120

102
102

M8522
M8522

IRD3

135

* &

16
17

135

M8522
M8522
M8522
M8522

IRD1
IRD1
IRD1
IRD1

14
15
16
17

~
= EDP AR 09 H

EDP AR 10 H

EDP1

M8512

EDP1
SCD2
SCD2

'M8512
M8524
M8524

SCD2
SCD2

M8524
M8524

132

SCD2

M8524

FE 06 H

05 H

132

SCD2

M8524

FE
FE

09 H
SIGN H

120

11
07

132
132

SCD2

11
07

SCD2
SCD2

M8524
M8524

172
160
160
160
160

32
27
28
29
30

MBX1
MBC5
MBC5S
MBC5
MBC5

M8529
M8531
M8531
M8531
M8531

IRD4
IRD1
IRD1
IRD1
IRD1"

M8522
‘M8522
M8522
M8522
M8522

136
132
132
132
132

16
14
15
16
17

13
12
13

132
132
136

134
130
130
130
174
175
160
161
162

160

IRD3
IRD3
IRD1

IRD3
IRD3
IRD3
IRD3

13
12
13
14
32
32
20
20
20
32

177
170

32
33

173
175
171

33
24
28

33
33

M8522
M8522

FORCE NO MATCH H
FORCE VALID MATCH
FORCE VALID MATCH
=

FORCE VALID MATCH
FORCE VALID MATCH

GEN CRY 36 H
IR AC 09 H
IR AC 10 H
IR AC 11 H
IR AC 12 H

IR EN AC H
IR EN I/0, JRST H

IR I/0 LEGAL H
IR JRST 0, L
IR NORM 08 H

NORM 09 H
NORM 10 H
DATA CODE 1 H
DATA CODE 2 H
IN SEL 1 H

IR
IR
MB
MB
MB

M8537

IN SEL

MBX3

M8529

PAR H

MBX2
MBX5

M8529
M8529

MB REQ HOLD H
MB REQ IN H

MBX2
CSH3
CSH3

M8529
M8513
M8513

'MB SEL HOLD H
MB TEST PAR A IN L
MB WR RQ CLR NXT L

MBZ1
MBZ1

MBZ5
.

FM 0 TO 35 H

M8512°

M8522
M8522
M8522

FE 08 H

‘M8522
M8522
M8529
M8529
M8537

MBX3
MBX3
MBZ1

176

171
172

EDP4

0-35

123

03 H
FE 04 H

.M8524

132
135

FE 02 H

M8524

SCD2

133

EDP AR 11
FE 00 H
01 H

*k
*%

BIT
17

134
134
134
134

MBX2
MBX2

M8537

M8529
M8529

MB IN SEL 2 H
4

MB PAR BIT IN H

MB SEL 1 H
MB SEL 2 H

asfiaisiinafian]

DF
133

* %
*%
*%
*k
*%
*%
* %
*%
*%

GEN.

INFO.

-87~

DIAGNOSTIC

SORTED

READ

FUNCTION

ALPHABETICALLY

CODES

(Cont)

DRAWING

BOARD

NAME

AND

174

MBX6

M8529

MBO

HOLD

175

MBX6

M8529

MB1

HOLD

176
177

MBX6
MBX6

M8529
M8529

HOLD

164

MB2
MB3

MBC3

M8531

MBC

INH

1ST

162
162

MBC2
MBC2

M8531
M8531

MBC2

CACHE

MBC2

CACHE

162

MBC2

M8531

MBC2

CACHE

162

MBC2
MBC?2
MBC2

M8531

MBC2

CACHE

M8531
M8531

MBC2
MBC2

CSH

ADR

CSH

VAL

M8531

MBC2
MBC3

CSH WR WR
ANY

160
161

161

162

MBC2
MBC3

M8531

163

TRUTH

SBUS

REQ

A
A

fussfifesiia
s fiariias]

KL10 (PA)

PULSE

PULSE
PULSE

H
H

MBC3

M8531

MBC3

165

MBC4

CORE

DATA

VALID

-2

MBC4
MB7Z4

M8531
M8531

MBC4

165
161

MBC4

CORE

PROG

M8537

MBOX

ADR

PAR

ERR

175
162

CSH3
MBZ4
MBZ3

170
161

CSH6
~ MBz4

M8513
M8537
M8537
M8513
M8537

MBOX

161

170

MBX5

M8529

MBX

176
173

MBX3
MBX4

M8529
M8529

MBX3

SBUS

DIAG

MBX4

CACHE

DONE

175

MBX4

M8529

MBX4

CACHE

160
16l
161l

MBZ1

MBZ1
MBZ1

CHAN

CORE

MBZ3

M8537
M8537
M8537

MBZ3

CHAN

MEM

REF

162
162

MBZ3
MBZ3

M8537
M8537

MBZ3
MBZ3

HOLD

FRA

162

MBZ4
MBZ4
MBZ6
MCL4
MCL4
MCL4
MCL4

M8537
M8537
M8537
M8530

MBZ
4
MBZ4
MBZ6

NXM

NXM
CSH

TG6,7 L
PAR BIT

MCL

BIT

M8530
M8530

MCL

BIT

MCL

TYPE

M8530

MCL

EA TYPE

104
107
105

“MCL6

M8530

MCL

EBOX

CACHE

MCL6
MCL6

M8530
M8530

MCL

EBOX

MAP

MCL

EBOX

MAY

105
106

MCL2

M8530
M8530

MCL
MCL

LOAD
LOAD

ARX

MCL

LOAD

VMA

MCL

MBOX CYC

160
106
105
107
107

MBZ1

MCL2

104

MCL4

107
102

. MCL1

MCL5

M8530
M8530
M8530

CHANGE

GATE

MBOX

NXM

MBOX
MBOX

COMING

VMA

PAR

27-33

ERR

DIR

SBUS
MEM

L
WR

ERR

L
CYC

RD-PSE-WR

SEQUENT
AL

PAGED

CONTEXT

IND H
FUNC L

115

APRG

M8539

105
106

MCL3
MCL3

M8530
M8530

MCL
MCL

PAGE

ILL

102

MCL?2

M8530

MCL

PAGE

TEST

PRIVATE

ENTRY

MCL3

M8530

MCL

PAGE

UEBR

REF

103

MCL4

M8530

MCL

COND

103

MCL5

M8530

MCL

SEC

106
103

MCL6
MCL1

M8530
M8530

MCL

REG
REQ

FUNC
EN L

107

MCL2

M8530

MCL

107

MCL2
MCL4

M8530
M8530

" MCL

VMA

EXTENDED

MCL

VMA

GETS

MCL4

M8530

MCL

VMA

INC

VMA

STORE

MCL2
MCL2

M8530
M8530

MCL
MCL

VMA

105

MCL2

MCL

VMA

PUBLIC

102

MCL2

MCL

VMA

READ

MCL

VMA

103
104

MCL3
MCL2

M8530
M8530
M8530
M8530

MCL

VMA

USER

104
104

MCL2
MCL4

M8530
M8530

MCL

VMA

WRITE

MCL

VMAX

106

MCL4

M8530

MCL

VMAX

SEL

UPT

105

.
MCL4

M8530

MCL

VMAX

102

MCL4
MBC4

M8530

MCL

M8531

MEM

ADR

PAR

162
173

MB71

MBX3

MEM

BUSY

MEM

DATA

171

MBX3

M8537
M8529
M8529
M8537
M8531

MEM

DIAG
L

MEM5
MBC4

MEM

PAR

165

161
166

MEM

H
H

TO.

MEM
H

172

MBX5

M8529

MEM

166
166

MBC4
MBC4

M8531
M8531

MEM

RQ
RQ

0 H
1 H

MEM

103
106

H
H

PAUSE

ARMM

COND

ADDRESS

104

102
103

REQ

MEM/ARL
MCL MEM/REG

MCL

PAGE

BUSY H
REF L

GEN.

INFO.
-88-

KL10 (PA) DIAGNOSTIC READ FUNCTION CODES

SORTED ALPHABETICALLY

166
166
166
161

164
173

(Cont)

BOARD

NAME

MBC4

M8531

MEM

MBC4
MBC4
MBZ1

M8531
M8531

MEM

START

M8537

MEM

DIAG

MBC3
MBX3

M8531
M8529

MEM

174

MBX3

M8529

MEM

175

MBX5

166

MBC4
EDP2

M8529
M8531
M8512

-MEM

MTR1

M8538

MEM

TO
TO

C SEL
C.SEL

WR RQ L
TO 35 H
CONO

112

M8538
M8538

MTR

114

111

MTR1

M8538

MTR

115

MTR3
MTR1
MTR2

M8538

MTR

M8538
M8538

MTR

- MTR2

ACCT

MTR2

M8538

MTR2

EXEC

ACCT

M8538
M8538
M8538

MTR2
MTR2
MTR3

116
115

MTR2
MTR2
MTR3

115
115

MTR3
MTR3

-+ MTR3
MTR3

117
117
117
160

MTR5
MTR5
MTR5
MBZ3

160
161

MBZ3
MBZ3

M8538
M8538
MB8538
M8538
M8538
.M8537
MB8537
M8537

NXM

ONE

116

PERF COUNT 02-17
PERIOD 06-17 H
TIME 02-17 H
H

ACCT

TIME

INTERVAL DONE H

INTERVAL
INTERVAL

ANY

NXM

DATA VAL L

WORD WR TO L
PAG MB 00-17 PAR H
PAG MB 18-35 PAR H

CsSH4

162

160

PAG5
PAG5S

M8537
M8537

174

CSH6

M8513

PAGE

FAIL

HOLD

171

CSH4
CSH6

M8513
M8513

PAGE

FAIL

PAGE

REFILL

CSH5
CSH5
VMA3
MBC3

M8513

PAGE

REFILL T4

M8513
M8523

PAGE

M8531

PHAS E

PIC3

M8539
M8539
M8539

PI3

- 101
101

PIC1
PIC1
PIC1

MTR PIA
MTR PIA
MTR PIA

M8532
M8532
- M8532
M8532
M8532
M8532
M8532

PIC1
PICL
PIC1

GEN

PICl
PICl

GEN

PICL

GEN

M8532

' M8532
M8532
M8532

PIC1

PIC1
PIC1

PIC1

100

PICl

100
100

PIC1
PIC1

M8532
-

. PIC1

100

PIC1
PIC1
PICl PICL
PIC1

M8532
M8532
M8532
M8532
M8532

PIC1

100

M8532

~PIC1

M8532
M8532
M8532

PIC1

100
100
100
100

100
100

PICL
PICl
PICl
PIC1
PIC1

103

PIC2

103

PIC2

103
103

177
176

PIC2

- pIC2
PIC5
PICS5

CSH2
- MBX3

M8532

- M8532
M8532

PIC1
PIC1
PIC1

INTERNAL

READY

PIC2
PIC2
PIC5

177
170

‘MBX5
MBX5

M8529

171

MBX5

M8529

;

PIH7
HONOR

PIC?2

M8532
M8532

M8529

PIC1
PIC2

M8532
- M8532

M8513

GEN

" PIC1 GEN
PIC1 GEN

100

ACTIVE
GEN

fuvfaciiscjiociiavignegen

101
101
101

PI3

oYU
W N

PIC1
~PIC1
PIC1
|
PIC1
PIC1

PI3

COMING L
01
02
04
01
02
04

a nfias e ofifu s JRacfia s Rt

100
101
101

PIC3

P13

M8538
M8538
M8538

PIC3
PIC3

116
116
116

CHANGE

APR PIA
APR PIA
APR PIA

PI3

ofo s liiu ofifn sfie o

110

PIC3
PIC3

faujia B

110
110

Lan]

164

L
ERROR

REFILL T8 L
1 3-35 H **NOTE

176
15X

OVRFLO H
INCR SEL 1 H
MTR5 INCR SEL 2 H
MTR5 VECTOR REQ H.
NXM ACKN H

MTRS5

175

176

M8513

177

m ommom

116

EBOX COUNT 02-17 H
INTERVAL 06-17 H

MTR

110

02-17

MTR,

(

CACHE COUNT

MTR

M8538

116

H
H

1
2

MTR3
MTR1
MTR1

113
117

122

AND TRUTH

DRAWING

STATE HOLD
TIMER DONE

EBUS PI GRANT H

PICS EBUS
RD

P AUSE

- REFI LL

RQ
RO
RQ

O
1
2

H
H

REQ

2ND HALF

HOLD
H

GEN.

INFO.

-89-

KL10 (PA) DIAGNOSTIC READ FUNCTION CODES
SORTED ALPHABETICALLY (Cont)
DRAWING

BOARD

NAME

AND

172

MBX5

HOLD

143

MBC?2
CRA4
CRA4
CRA4

M8529
M8531
M8511

161

143

CRA4

143
142

CRA4
CRA4
CRA4

142
142
142
142

SBR

RET

M8511
M8511

SBR

RET-

SBR

RET

M8511
M8511
- M8511
M8511

SBR

RET

CRA4
CRA4

CRA4

173

CRA4
MBX2

M8511
-+ M8529

SBUS

ADR

174

MBX2

M8529

SBUS

ADR

162

MBC2

SBUS

ADR

HOLD

SBUS

DIAG

142

SBR

RET

SBR

RET

SBR

RET

M8511
M8511

SBR

RET

SBR

RET

M8511

SBR

RET

SBR

RET

175

MBX3

M8531
M8529

136

SCD2-

M8524

131

SCD2
SCD2

M8524
M8524

sSC

131
131

.GE.

143

SCD2

M8524

131
131

'SCD2

M8524

SCD2

130

SCD2

M8524
M8524

130
130

SCD2
SCD?2

M8524
M8524

130

SCD2

M8524

130
134

SCD2
SCD2

M8524
M8524

133

SCD1

M8524

SCAD=0

137

SCD5

ADR

BREAK

SCD5

SCD

ADR

BRK

CYC

137

SCD5

M8524
M8524
M8524

SCD

137

SCD

ADR

BRK

INH

131
131

SCD4
SCDh4

M8524
M8524

SCD

CRYO
CRY1

131

SCD4

SCD

DIV

CHK

132
130

SCh4
SCDh4

M8524
M8524
M8524

MmO

(02

[e»]

SC
SC

L
PREVENT

SCD

FOV

SCD

FPD

H
H

132

SCD4

M8524

SCD

FXU

135
136

SCD5
SCD5

M8524
M8524

SCD
SCD

KERNEL
KERNEL

134

M8524

SCD

LEAVE

USER

133

SCD5
SCD5

M8524

SCD

LOAD

FLAGS

MODE H
OR USER

133
131

'SCD4
SCDh4

M8524
M8524

SCD

NICOND

SCD

133
135

SCDh4
SCD5

M8524
M8524

SCD

PCP

SCD

PRIVATE

135

SCD5

SCD

PRIVATE

135

SCD5
SCD5

SCD

PUBLIC

H
H

INSTR

PUBLIC

134

SCD5

SCD

PUBLIC

PAGE

137
130

SCD4
SCDh4

M8524
M8524

SCD

TRAP

CLEAR

SCD

TRAP

CYC

130

SCD4

M8524

SCD

TRAP

CYC

136

SCD3
SCD3

M8524
M8524

SCD

TRAP

MIX

136

SCD TRAP

MIX

32
33

H
H

* %

137

SCD3

M8524

SCD

TRAP

MIX

* %

137
130

SCD3
SCD4

SCD

TRAP

MIX

SCD

TRAP

REQ

35 H
1 H

130

SCD4

M8524
M8524
M8524

SCD

TRAP

REQ

134

SCD5
SCD5

M8524
M8524

SCD

USER

SCD

USER

* %

134

SCD

L
H
L

136

SCD5

M8524

SCD

SCD5
SHD1

M8524
M8537

SCD

AR PAR ODD A H

105

SHD1

ARX

TEST

USER

10T

USER

I0T

134

SHD1
IRD3

M8526
M8526
M8522

15X

VMA2

M8523

VMA

153
157

VMA1
VMALl
4
VMA

M8523
M8523

VMA
VMA

M8523

VMA

HELD

SCD4
MCL3
MCL3

M8524

VMA

HELD

100
100

M8530
M8530

VMA

HELD

OR. PC

100
100

MCL3
MCL3

100
100

MCL3
MCL3

M8530
M8530
M8530
M8530

15X
132

PAR ODD
PAR

ODD

SATISFIED

13-35

**NOTE

18-31=0
R EF

136
160
106

IOT

M8524
M8524
M8524
M8524

135

H
H

13- 35
PC

H
00
01
02

VMA

HELD

VMA

HELD

VMA

HELD

vMA

HELD

PC
PC

VMA

HELD

PC 06

03
04
05

**NOTE
jasjiiaciissiiaciiurifariias

143

TRUTH

H
e jiasiiusRasiiasiiasiiasiiasiiusiiosiiaviias]

INFO.
-90-

>KL10(PA)»DIAGNOSTIC READ FUNCTION CODES
- BIT -

"DRAWING BOARD

NAME AND TRUTH

MCL3
MCL3
MCL3
MCL3
MCL3

M8530
M8530
M8530
M8530
M8530

VMA
VMA
VMA
VMA
VMA

HELD
HELD
HELD
HELD
HELD

OR
OR
OR
OR
OR

PC
PC
PC
PC
PC

07
08
09
10
11

VMA

HELD OR

13-35

101

18
19
20
21
22

101

MCL3

M8530

157
160

VMA3

M8523

VMA MATCH

MBC1

M8531

WRITE

177

MBX4

M8529

WRITEBACK

101
101
101
101

H
T2

NOTE

TRACON

and

programs

the

1ll-based

are

preceded

with

single or double asterisk
as single bits; as such,

[ (¥*)
they

interpret

functions
either a
or
(**)]

which

all

diagnostic

not

read

are printed out by bit position and/or
name.
Diagnostic
read
functions

preceded by a single asterisk
(*)
are
interpreted as registers and are printed
out as such.
Diagnostic read functions
which are preceded
by a double asterisk
(**) may be interpreted and printed as

either

single

bits

depending
on
the
interpretation.

as a

program

doing

the

s Jtw
ool
iia N

(Cont)

_ SORTED ALPHABETICALLY

o s}

GEN.

INFO.
~9]-

READ

FUNCTION

DRAWING

BOARD

CODES
NAME

SORTED
AND

100

PIC1

M8532

PIC1

PIH1

100

PIC1

PIH2

PIC1

M8532
M8532
M8532

PIC1

100

PIC1

PIH3

PIC1

PIH4

PIC1

PIHS
PIHG6

100

PIC1
PIC1

100

PIC1

M8532
M8532

PIC1

100

PIC1

M8532

PIC1

PIH7

100

PIC1

ACTIV

PIC1

M8532
M8532

PIC1

100

PIC1

100

PIC1

M8532

PIC1

100

PIC1

~SNoyun
W N

100

NUMERICALLY

TRUTH

100

PIC1

M8532
M8532
M8532

PIC1

100
100

PIC1
PIC1

M8532
M8532

PIC1
PIC1

VMA

HELD

VMA

HELD

VMA

HELD

OR PC

VMA

HELD OR. PC
HELD OR PC

05
06

100
100

MCL3
MCL3

M8544
4
M854

100

MCL3

100

MCL3

M8544
M8544

100
100

MCL3
MCL3

100

CTL1

M8544
M8544
M8543

100

CTL1
CTL2

M8543
M8543

100

VMA

CTL

HELD

SPEC/SCM ALT

SPEC/SAVE

FLAGS

ARL

SEL

100

CTL2

M8543

CTL

ARR

LOAD

CTL2
CLK1

M8543
M8526YA

CTL
CLK

00-08

EBUS

CLK

100

CLK1

M8526YA

CLK

SBUS

CLK

100
100

CLK4
CLK5

M8526YA CLK INSTR 1777 H
M8526YA CLK5 BURST CNT=0

100

CLK5

M8526YA

CLK5

100
101

CLK5
PIC1

M8526YA
M8532

CLK5
PICI

BURST

GEN

101

PIC1

M8532

PIC1

GEN

101
101
101

PIC1
PIC1

M8532
M8532
M8532

PICl1
PIC1

GEN
GEN

3
4

H
H

PIC1

GEN 5
5

101
101

PIC1
PIC1

M8532

PIC1

GEN 6
6

M8532

PIC1

GEN

101

MCL3

101
101
101

MCL3
MCL3
MCL3

M8544
M8544
M8544
M8544

101
101

MCL3
MCL3

M8544
M8544

101

CTL1

101

CTL1
CTL2
CTL2

101

CTL2

101

CLK5

101

CLK5

101

CLK5
CLK5
CLK5

101
102

CLK5
PIC4

102

PIC4

101

102

PIC2

102
102

PIC4
PIC4

BURST

128

VMA

HELD

HELD
HELD

OR
OR

PC
PC

08
09

VMA

HELD

VMA

HELD OR
HELD OR

PC
PC

11
12

M8543

CTL

SPEC/CLR FPD

M8543

CTL

SPEC

M8543
M8543

CTL

ARL

SEL

CTL

ARR

LOAD

MTR

CTL

M8526YA

CLK5

BURST

M8526YA CLK5 BURST 04
M8526YA CLK5 BURST 02
M8526YA CLK5 BURST 01
M8532
EBUS Cs05 E H
EBUS CS06 E H
M8532
M8532
M8532
M8532

EBUS

DEMAND

EBUS

E
E
E
E

READ

M8532

EBUS

MCL?2

VMA

MCL1

MEM/ARL

102
102

MCL3
MCL4

PAGE

102
102

MCL4
MCL4

MCL4

VMA GETS
XR SHORT

102

CTL1
CTL1
CTL2
CTL2

M8544
M8544
M8544
M8544
M8543
M8543
M8543
M8543

102
102

CTL2

102

CLK2
CLK4
CLK3
CLK4

102
102
102

CLK1

M8543
CTL AR 09-17 LOAD
M8526YA CLK5 BURST 32
M8526YA CLK5 BURST 16

M8544
M8544

102
102

H
B

PIC4
PIC4

102

VMA

MCL2
MCL1

VMA

102
102

102

CS00
Cs0l1
Cs02
Cs03

102

LOAD

EBUS
EBUS

MCL4

jmofiesjanfiasiaclian

101
101

CTL
CTL

100
100

PIC1

I DI @IDmm

BIT

jsejusiiafiacijuciias]

DIAGNOSTIC

ZTIOIIDIIDINIIMDI
DS Do D@

KL10 (PV/PW)

H
H
H

IND

PRIVATE

TEST

CTL

SPEC/GEN CRY 18 H
COND/AR GETS EXP H

CTL

ARR

CTL

SEL

CTL

MQM

SEL

M8543
M8526YA

CTL

ARX

LOAD

CLK

ERROR

M8526YA

CLK2

H
H

STOP

M8526YA CLK EBOX REQ H
M8526YA CLK3 SYNC H
M8526YA CLK4 PAGE FAIL

GEN.

INFO.
-92

KL10

(PV/PW)

DIAGNOSTIC

‘

* %

READ

FUNCTION

(Cont)

35
11

- CLK4
PIC2

M8526YA CLK FORCE 1777 H
MB8532
IC2 TIMER DONE H

103

"PICS

M8532

PIC2

103
103
103
103
103
103
103

PIC2

MCL2
MCL1
MCL6
. MCL5

" M8532
M8532
M8532
M8544
M8544
M8544
M8544

103
103

22
23

MCL4
MCL4

M8544
M8544

103

CTL1

M8543

103

CTL1

M8543

PIC2
PIC5

103
103
103

28
30

103
103

32
33

103

CLK4

103

CTL2

103

TRUTH

GRANT H

STATE

HOLD H

PIC2

HONOR

INTERNAL H

PIC2
PIC5

READY H
EBUS REQ H

EBUS CS04 E H

MCL2 VMA
MCL1 REQ
MCL6 VMA
MCL5 VMA
MCL4
MCL4

PAUSE H
EN L
UPT H
ADR

ERR H

VMA INC H
SHORT STACK

CTL SPEC/STACK
CTL

M8543

CTL2
-

PIC2

M8532

15
16
17
18
19
20
21

AND

PICS EBUS PI

M8532

PICA4

103

NAME

NUMERICALLY

102
103
103

BOARD

SORTED

BIT

103

‘DRAWING

CODES

DISP

RET

UPDATE

CTL ARR SEL 1 H

M8543

CTL MQM SEL

1 H

CTL2
CLK3
CLK2

M8543
CTL ARL SEL 4 H
M8526YA CLK3 DRAM PAR ERR H
M8526YA CLK2 BURST L

CLK4
CLK4

‘M8526YA CLK MB XFER H
M8526YA CLK4 EBOX CLK L
M8526YA

CLK

PAGE

M8526Ya CLK4

ERROR H

104

CLK4

MCL2

M8544

MCL2

104

MCL2

M8544

MCL

104

MCL6

M8544

MCL6

PAGE

104
104

21
22

MCL5
MCL4

M8544
M8544

MCL5
MCL4

VMAX EN L
LOAD VMA CONTEXT

104
104

23
24

MCL6
" CTL1

M8544
M8543

104

1777

VMA USER

VMA

WRITE

UEBR

REF

MCL6 EBOX CACHE L
.CTL SPEC/FLAG CTL

CTL1

M8543

CTL

LOAD

104

CTL2

M8543

CTL

ARXL

SEL

CTL2

M8543

CTL

SEL

104

CTL2

M8543

CTL

00-11

104

CLK3

M8526YA CLK3

CRAM PAR ERR H

104

CLK2

M8526YA

CLK2

EBOX

104

CLK5

M8526YA

CLK5

SOURCE

104

CLK3

M8526YA

CLK3

EBOX

104

CLK5

M8526YA

CLK5

MBOX CYCLE

CLR

L
SEL

SOURCE

PAR

H
H

CHECK

L-

104

CLK5

M8526YA

CLK5

105
105

18
19

MCL2
MCL2

M8544
M8544

MCL LOAD
MCL2 VMA

DIS

105

MCL3

M8544

MCL3

PAGE

ADDRESS COND

105

MCL4

M8544

MCL4

VMAX

SEL

105
105

22
23

MCL5
MCL6

M8544
M8544

MCL5
MCL6

23 BIT EA H
EBOX MAY BE

105
105

24
25

CTL1
CTL1

M8543
M8543

CTL
CTL

105

CTL2

M8543

AR H
PUBLIC

SPEC/SP
ADX CRY

PAGED

MEM CYCLE
36 H

CTL

ARXL

105

CTL2

M8543

CTL

28
30

CTL2
CLK3

M8543
M8526YA

CTL AR 12-17 CLR H
CLK3 FM PAR ERR H

105
105

31
32

SHD1
CLK5"

M8526YA
M8526YA

SH AR PAR ODD H
CLK5 SOURCE SEL

105

- CLK5

105

CLK5

M8526YA

105

CLK5

M8526YA CLK5 MBOX RESP

106

MCL2

M8544

MCL

106
106

19
20

MCL2
MCL3

- M8544
M8544

MCL2
MCL3

VMA PREVIOUS L.
PAGE ILL ENTRY H

106

-MCL4

M8544

MCL4

VMAX

106
106

22
23

MCL5
MCL6

M8544
M8544

MCL5
MCL6

18 BIT EA H
REG FUNC H

106
106

24
25

CTL1.
CTL1
--

M8543
M8543

CTL AD LONG H
CTL ADX CRY 36 A H

106

M8543

106

106
106

28
30

SHD1

CLK5

106

‘107

107

CLK5

CLK5
-

LOAD

CTL

ARXR

PAR
ARX

SEL

CTL MQM EN
H
ARX

PAR

M8526YA

CLK5

RATE

SEL

ODD

M8526YA

CLK5

DRAM

PAR

CHECK

~ M8526YA CLK5 EBOX EDP DIS H
M8526YA

CLK5

M8544

MCL

STORE

M8544

MCL6

VMA

FETCH

M8526YA

CLK5

MCL6

SIM

MCL2

CHECK
H

M8543
CTL ARR CLR H
M8526YA CLK3 FS ERROR

CRAM

M8543

106

CLK5

CTL2
CLK3

106

CTL?2

106

M8526YA CLK5 EBOX CRM DIS
H

CTL2

SEL

105
105

SEL

104

M8544

AR/ARX

PAR

CHECK

MCL2 VMA EXTENDED
L
H

GEN.

INFO.

-93-

KL10(PV/PW)

DIAGNOSTIC

READ

FUNCTION

CODES

SORTED

NUMERICALLY

(Cont)

NAME AND TRUTH

MCL6

M8544

MCL6

107

MCL5

M8544

MCL

107

MCL6

M8544

MCL6

107
107

24
25

CTL1
CTL3

M8543
M8543

CTL INH CRY 18
DIAG MEM RESET

107
107

26
27

CTL2
CTL3

M8543
M8543

CTL ARXR SEL 1
DIAG LOAD EBUS

107

CTL2

M8543

CTL

107
107

30
31

CLK3
CLK4

M8526YA
M8526YA

CLK3
CLK4

PAGED

MBOX

FETCH

CYC

SPEC

REQ

EBOX MAP

CALL

L
H
H
REG

ERROR L
PAGE FAIL

SEL

107

CLK5

M8526YA CLKS5 RATE

33
34

CLK5
CLK5

M8526YA
M8526YA

CLK5
CLK5

EBOX CTL
FS CHECK

DIS
L

107

CLK5

M8526YA

CLK5

ERR

STOP

110

APR1

M8545

APR]1

APRI1

M8545

APR1

SBUS

110

APR1

M8545

APR]1

NXM

110
110

08
09

APR1
APR1

M8545
M8545

APR]1
APR1

I/0 PF
MB PAR

110

APR2

M8545

APR2

DIR

ERR

110

APR2

M8545

APR2

ADR

ERR

110
110

12
13

APR2
APR2

M8545
M8545

APR2
APR2

PWR FAIL IN H
SWEEP DONE IN

110
110

14
15

APR2
PIC3

M8545
M8545

APR2 APR INTERRUPT
H
PI3 APR PIA 04 H

110

PIC3

M8545

PI3

110

M8538

PI3 APR PIA 01
MTR TIME 02-17

20-35

PIC3
MTR1

M8545

110
111

APRS

M8545

APR5

CURRENT

BLOCK

111
111

07
08

APRS
APRS

M8545
M8545

APR5
APR5

CURRENT
CURRENT

BLOCK
BLOCK

2
|

H
#l

111
111
111

09
10
11

APR5
APRS
APR5

M8545
M8545
M8545

APR5
APR5
APR5

PREV BLOCK
PREV BLOCK
PREV BLOCK

111

SHM1

M8540

SHM1

EXTENDED

111
111

13
14

APR3
APR4

M8545
M8545

APR3
APR4

FM EXTENDED
AC+# 09 H

111

APR4

M8545

~ APR4

AC+#

16
17

APR4
APR4

M8545

APR4

AC+#

111

M8545

111

20-35

MTR1

M8538

APR4 AC+# 12 H
MTR PERF COUNT

02-17

112
112

06
07 .

APR1
APR1

M8545
M8545

APR1
APR1

SBUS ERR EN IN H
NXM ERR EN IN H

112
112

08
09

APR1

M8545
M8545

APR1
APR1

I/0O

APR1

PAR

APR?2

M8545

APR

BUSY

H
L

110

SWEEP

107
107

112

DRAWING BOARD

107

111

BIT

ERR

PIA

ERR
ERR

IN
IN

H
H

4
2
1

Hi
H
H

ERR EN
ERR EN

IN
IN

112

APR2

M8545

APR2

112
112

12
13

APR2
APR2

M8545
M8545

APR2
APR2

PWR FAIL EN IN H
SWEEP DONE EN IN

112

20-35

~ MTR1

M8538

MTR EBOX

113
113
113

09
10
11

APR3
APR3
APR3

M8545
M8545
M8545

APR3
APR3
APR3

FETCH COMP H
READ COMP H
WRITE COMP H

M8545

APR3

USER COMP

M8545
M8545
M8545
M8545

APR MBOX CTL
APR FM BLOCK
APR FM BLOCK
APR FM BLOCK

ADR

ERR

COUNT

02-17

APR3

* %

114
114
114
114

07
08
09
10

APRS
APRS
APRS
APRS

* %

114

M8545

APR FM ADR 10 H
APR

ADR

114

12
13

APR4

M8545

APR

ADR

4
2

* %

114

APR4

M8545

APR

ADR

114
114

15
16

APR4
APR3

M8545
M8545

APR4 F02 EN
APR FM 36 H

114
114
115

17
24-35
07

APR3
MTR1
APR5S

‘M8545
M8538
M8545

APR3 FM ODD PARITY H
MTR INTERVAL 06-17 H
APR MBOX CTL 06 H

115
115

08.
09

APR5
APR3

M8545
M8545

APR5 SET PAGE FAIL
APR EBUS RETURN H

115

APR3

M8545

APR

115
115

11
12

APR2
APR6

M8545
M8545

APR2
WR BAD ADR
APR6 EBOX CCA H

115
115

13
14

APR6
APR6

M8545
M8545

APR EBOX ERA H
APR6 EBOX SBUS

115

MCL1

M8545

MCL1

DIAG H
MEM/REG FUNC L

115
115

16
17

APR6
APR6

M8545
M8545

APR6
APR6

EBOX LOAD REG
EBOX READ REG

* %

* k

* %

113

114

115
115

20-35

21
22

MTR1

APR4

MTR3
MTR3

M8538

M8545

. M8538
M8538

MTR CACHE

MTR3
MTR3

EBOX

COUNT

02-17

03 H
4 H
2 H1 H
H
H
H

DISABLE

PAR

L
L

INTERVAL ON H
INTERVAL DONE H

H
H

113

H
H

APR2 C DIR P ERR EN IN H

INFO.

GEN.

-94-

KL10 (PV/PW)

DIAGNOSTIC

READ

FUNCTION
(Cont)

BIT

115

116
116
116
116
116
116
116
116
116
116
116

07
08
09
10
11
12
13
21
22
23
25

115

*%
*%
*%

116
116
116
117

117
117

*x
*
*
*
*
*
*
*
*

*%
Kk
* %
*%
*%

*%
*%
*%

APRS
APRS
APR3
APR3
APR2
APR6
APR6
MTR2
MTR2
MTR2
MTR2

M8545
M8545
M8545
M8545
M8545
M8545
M8545
M8538
M8538
M8538
M8538

PIC3
PIC3
PIC3

MTR3 INTERVAL OVRFLO H

MTR PERIOD 06-17 H

M8538
M8538
M8538

PI3 MTR PIA 04 H
PI3 MTR PIA 02 H
PI3 MTR PIA 01 H

APR5 WR PT SEL 0 H
APR5 PT DIR WR L
APR EBUS REQ L
APR EBUS FOl1 E H
APR ANY EBOX ERR FLG H
APR6 EBOX UBR H
APR EN REFILL RAM WR H
MTR2 PI ACCT EN H
MTR2 EXEC ACCT EN H
MTR2 ACCT ON H
MTR2 TIME ON H

APR5 WR PT SEL 1 H

APR5
APR3

M8545
M8545

APR5 PT WR L
APR3 EBUS DEMAND H

12
13
20
21

APR6
APR6
MTR5
MTR5

M8545
M8545
M8538
M8538

APR6
APR6
MTR5
MTR5

M8545
M8545

APR3
CONS5

M8538

MTR5

M8538

MTR3

APR3 EBOX SEND F02 H
CON FM WRITE PAR L
EBOX EBR H
EBOX SPARE H
VECTOR REQ H
INCR SEL 2 H

MTR5 INCR SEL 1 H
L

MTR CONO MTR,

AR 00 H
AR 01 H
H
AR 02
AR 03 H
AR 04 H
AR 05 H
AR 06 H

00
01
02
03
04
05
06

EDP1
EDP1
EDP1
EDP1
EDP1
EDP1
EDP1

M8512
M8512
M8512
M8512
M8512
M8512
M8512

120

EDP1

M8512

EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP

M8512
M8512
M8512
M8512
M8512
M8512
M8512

AR 12 TO 35 H
BR 0 TO 35 H
MO 0 TO 35 H
FM 0 TO 35 H
BRX 0 TO 35 H
ARX 0 TO 35 H
ADX 0 TO 35 H

120
120
120

120

120
121
122
123
124
125
126

127
130
130
130
130
130

130
130
130
130
130
130
130
130
130

130

130
130
130

131
131
131
131

131
131
131
131
131
131
131
131

NUMERICALLY

M8538

M8545

APRS

SORTED

120
120
120
120
120
120
120

131

*%
* %
*%

117

131

* %
*%
*%
*%
*%
* %

M8538

CODES

NAME AND TRUTH

08
09

10
11

117

MTR3

33
34
35

117
117

117
117
117
117

*%
*%
*k
*%
*&
*X
Ll
*%
*%
*%
LA

24-35

DRAWING BOARD

EDP1
EDP4
EDP2
EDP4
EDP4
EDP2
EDP3

12-35
0-35
0-35
0-35
0-35
0-35
0-35

07
08
09
10
11
12
13
14
15

16
17

18
19
20

04
05
06
07

08
09
10
11
12
13
14
15

M8512

EDP1

0-35
02
03
04
05

M8512
M8512
M8512

EDP1
EDP1
EDP1

07
08
09

M8512
M8524
M8524
M8524
M8524

EDP3
SCD4
SCD4
SCD4
SCD4

M8524

SCD4

'SCD4
"EDP3
sCp4
SCD2

SCD2
SCD2
SCD2
SCD2
IRD1
IRD1
- IRD1
IRD1

EDP AR 11 H

AD 0 TO 35 H
SCD TRAP REQ
SCD TRAP CYC
SCD TRAP CYC
SCD TRAP REQ
SCD FPD H

2
2
1
1

M8522

DR ADR 02 A H

M8524
M8524
M8522

M8522

IRD1

H
H
H

M8522
M8522
M8522

M8524

IRD1

CON3
CON3
CON3

07
08
09
10

sc 05 H
SC 06 H
sC 07 H
sCc 08 H
SC 09 H
IR NORM 08 H
IR NORM 09 H
IR NORM 10 H
DR ADR 00 A H

M8524
M8524

SCD2
SCD2
SCD2
SCD2
SCD2
IRD3
IRD3
IRD3
IRD1

AR
AR
AR
AR

H
H
H
H

DR ADR 01 A H

M8525 CON WR EVEN PAR ADR H
CON3 WR EVEN PAR DATA H
M8525
M8525 CON3 WR EVEN PAR DIR H
M8524

SCDb OV 'H

M8524

SCD CRYO H

M8524
M8524
M8524
- M8524
M8522
M8522
M8522
M8522

SC
scC
sC
SsC
DR
DR
DR
DR

M8524
M8524
M8524
M8524

SCD CRYLl H
AD CRY 01 L
SCD DIV CHK H
SC 00 H

01 H
02 H
03 H
04 H
ADR 03
ADR 04
ADR 05
ADR 06

A
A
A
A

H
H
H
H

GEN.

INFO.

-905~

KL10 (PV/PW)

DIAGNOSTIC

READ

FUNCTION

CODES

SORTED

NUMERICALLY

(Cont)
DF

DRAWING

BOARD

NAME

* k

131

IRD1

M8522

* %k

131
131

IRD1

CON3

M8522
M8525

CON3

131

CON3

131

CON3
CON3
SCDh4

131
132

132
132

CACHE

H
H

LOOK

CON

CACHE

LOAD

CON

KI1l0

PAGING

CON
VMA

TRAP
HELD

EN
OR

SCD

FOV

132
132

SCD2
SCD2

M8524

132

SCDh2

M8524

132

IRD3
IRD3

M8522
M8522

I/0,

132

IRD1

M8522

132
132

IRD1

10
11

IRD1

M8522
M8522
M8522

IR AC
IR AC

132

132
132

M8525
M8525

CON
CON

132

CON1
CON1
CON1

M8525

CON

COND/MBOX

132
132

CON2
CON2

M8525
M8525

CON
CON

LONG
LOAD

132

CON4

132

CON5
SCD4

IRD1

06
07
08
09

FE
FE
FE

-02

COND EN 00-07 L
COND/SEL VMA L
EN
IR

133

SCD5

133
133

SCD1
CON2

M8524
M8524

SCAD=0

133

SCD4

133
133

SCD2
SCD2

M8524
M8524
M8524

SCD NTICOND
FE 00 H
FE 01 H
FE 02 H

CTL

LOADED

CYCLE

SCD

PCP

SCD

H
H

LOAD

CON

FLAGS

CLR

PRIVATE

133

SCD2

M8524

SCD2
SCD2

M8524
M8524

FE
FE

133

IRDI1
IRD1
IRD1

M8522
M8522

M8522

DRAM
DRAM
DRAM

A
A
A

00
01
02

H
H
H

B
B
B

00
01
02

H
H
H

INSTR

H
H

03
04

IRD1

M8522

DRAM

133
133

IRD1
IRD1

M8522
M8522

DRAM
DRAM

133

CON1
CON1
CON3

M8525
M8525
M8525

CON SKIP EN 40-47
CON COND/VMA GETS

133

CON

EBUS

REL

133

CON4

M8525

CON

PC+1

INH

133
133

CON2
CON4
CON5

M8525
M8525
M8525

CON

133
134

SCD5

M8524

SCD

USER

SCD5

LEAVE

CON>5

M8524
M8524

SCD

134

CON

134
134

SCD5
SCD5

M8524
M8524

SCD

USER

SCD

PUBLIC

134

SCD2

M8524

134

IRD3

M8522

TEST

134
134

IRD3
IRD1

M8522
M8522

134
134

IRDI1
IRD1

M8522
M8522

IR JRST 0, L
DRAM J 01 H
DRAM J 02 H
DRAM J 03 H
DRAM
-J 04 H

- M8522

134

IRD1

134

CON1
CON1

134

CON3

134
134

CON2
CON2

M8525

134

CON4
CON5

134

M8525
M8525
M8525

L
#

COND INSTR ABORT
L
CON ARX LOADED
CON5 MEM CYCLE L

134

L
USER

CYCLE
EN'L

PAGE

SATISFIED

SKIP

50-57

CON COND/LOAD VMA HELD
CON SR 00 H
NICOND TRAP
LOAD ACCESS

M8525

CON
CON

M8525

CON

UCODE

STATE

M8525

CON

WRITE

COND

PAR

134

XCDh1

CLK

SEL

XCD1

M8572

CLK

SEL

SCD5
SCD5

M8524

SCD

M8524

SCD

PUBLIC

135

SCD5
SCD5

M8524

SCD

KERNEL

MODE

M8524

SCD

PRIVATE

INSTR

135

SCD5

SCD

PRIVATE

INSTR

135
135

SCD2
IRD1

M8524
M8524
M8522

DRAM

135

IRD3

ODD

IRD1

M8522
M8522

DRAM

135

DRAM

135

PUBLIC

SIGN

L
H

PAR .H

PARITY

134
135
135

M8572

SIGN

CON

133

L
L

CON5

133
133

133

JRST

M8525
M8525
M8524
M8524

133

jsejiuviiacfiacias]

M8524

CRY

FE
FE

H
H

MODE

SCD FXU H
AD OVERFLOW
AD

EN
EN

H
PC

M8524
M8524
M8524
M8524
M8524
M8524

133

* %

M8524

ADR

DR ADR

SCD4
SCD4
EDP3
IRD4
SCD2
SCD2

132
132

* %

M8525
M8525
M8525

AND TRUTH

GEN.

INFO.
-96—

KL10(PV/PW)

i
* %
* %

DIAGNOSTIC

135
135
135

15
16
17

IRD1
IRD1I
IRD1

DRAM J 08 H
DRAM J 09 H
DRAM J 10 H

18.
°

M8525
M8524

CON MBOX WAIT L
SCD KERNEL OR USER IOT

SCD3
SCD3

M8524
M8524

SCD TRAP MIX 32 H
SCD TRAP MIX 33 H

05
06

SCD5
SCD5

M8524
M8524

SCD USER IOT A H
SCD USER IOT EN L

136

IRD3

M8522

AD=0

136
136

13
14

IRD1
CTL1

M8522
M8522

IR I/0 LEGAL H
CTL INH CRY 18 L

136
136
136
136

16
17
18
19

IRD4
IRD4
CON4
CON1

M8522
. M8522
M8525
~ M8525

CON2

M8525

CON2

CON5

135
136

24
02

- CON5
SCD5

136
136

03
04

136
136

136

137

137
137
137

03
04
05

137

137
137
137

137
137
137
137
137
137
137
137

16
17
18
19
20
21
22
23

137

140

* %
*%

141
141

* %

* %
* %
**

* %

141
141
141

142

02
03
04

CON

LOAD DRAM

CON

FM XFER L

SCD ADR BRK

SCD5

M8524 ~

'M8524

M8522

IRD4
IRD4
IRD4

M8522
M8522

SCD ADR BRK CYC
H

SCD ADR BREAK PREVENT H
SCD TRAP CLEAR L

AD CRY 12 H
AD CRY 18 H
AD CRY 24 H

M8522

M8522
M8522
M8525
M8525
M8525
M8525
M8525
M8525
M8525

ADX
ADX
CON
CON
CON
CON
CON
CON

AD CRY

CRY 12 H
CRY 24 H
ARX 36 H
VMA SEL 1 L
SR 03 H
NICOND 09 H
COND ADR 10 H
UCODE STATE 07 H

36 H

CON

DISMISS

M8541

CRA DISP EN 00-07

CRA4
CRA4
CRA4

M8541
M8541
M8541

CRA STACK ADR 10 H
CRA STACK ADR 04 H
CRA STACK ADR 02 H

M8541
M8541

CRA CALL, RESET H
CRA DISP 00 H

CRA4

M8541

CRA3

M8541

03
04
05

CRA3
CRA3
CRA3

CRA DISP

M8541
M8541
M8541

CRA DISP 02 H
CRA DISP 03 H
CRA DISP 04 H

CRA4

M8541

CRA SBR RET 06 H

CRA SBR RET

05 H

142
142
142

03
04
05

CRA4

_CRA4
CRA4
CRA4

M8541

M8541
M8541
M8541

CRA SBR RET

CRA SBR RET 08 H
CRA SBR RET 09 H

07 H

143

CRA4

M8541

CRA SBR RET 00 H

M8541

CRA SBR RET 02 H

M8541

CRA SBR RET 04 H

143

CRA4

CRA STACK ADR 01 H

142

M8541

"CRA3

CRA4

" CRA4

CRA1

M8541

CRA -SBR RET 10 HCRA DISP EN

30-37

CRA SBR RET

01
H

CRA SBR RET 03 H

* *

144

CRA1

M8541-

CR ADR 06 F H

* %

144

CRA2

M8541

CR ADR

144

144
144
144
144
144

03
04
05
08
09

CRA4

CRA2
CRA2
CRA2
CRM5
CRM5

CRA DISP EN 00-03 L

* %
* %
* %
* %
* %

CRA3

143

05 H

INH
H

SCD TRAP MIX 34
H
H
SCD TRAP MIX 35

M8524

SCD4

- CRA4
CRA3

CON NICOND 08

M8524

00
01

.02

-~ CON SR 02
H

SCD5

CRA3

GEN CRY 36 H
AD CRY -02 A H
CON AR 36
H
CON VMA SEL 2 L

M8525

CON5

CON UCODE STATE

M8524
M8524

M8525

IRD4

.GE.

CON4

IRD4
IRD4 .
CON4
CON1
- CON3
"CON2
CON2
CON4

140

141

INSTR

CTL SPEC/GEN CRY 18 H

M8525

SCD5

12
13
14

137

140
140
140

M8525

SCD3
SCD3 ~

M8522

CON3

SPEC

CON UCODE STATE 03 H

M8524

CTL1

M8525

SCD2

136

LE
* %
*%

CON4

136

CON SR 01 H
CON NICOND 07 H
CON2 INSTR GO L

LOAD

REQ

CON

M8525
M8525
M8525

136

CON DELAY

NUMERICALLY

M8525

"CON3
CON2
CON2

136

M8525

CON1

20
21
22

136

LE
* %
* %

M8522
~ M8522
M8522

CON3
.

135
135
135

136

* *

SORTED

NAME AND TRUTH

135

* ok

CODES

DRAWING BOARD

135

*%
*%

FUNCTION
(Cont)

BIT

135

* %
*x

READ

M8541

CR ADR

M8541
CR ADR 08 F H
M8541
CR ADR 09 F H
< CR ADR 10 F H
'M8541
M8548
CRAM 60 H
-~ M8548 = CRAM PAR 1ST 00
.

GEN.

INFO.

-97<

KL10 (PV/PW)

DIAGNOSTIC

READ

BIT

DRAWING

FUNCTION

CODES

©SORTED

NUMERICALLY

(Cont
BOARD

NAME

AND

TRUTH

144

CRM5

M8548

* %
**

144
144

11
14

CRM5
CRM5

M8548
M8548

CRAM
CRAM
CRAM

62 H
PAR 00
64 H

**
**

144
144

15
16

CRM5

MB8548

CRAM

PAR

CRM5

M8548

CRAM

**
**%

144
144

CRM5

M8548

CRAM

PAR

CRM5

M8548

CRAM

**
**

144
144

CRM5

M8548

CRM5

CRAM

PAR

M85438

CRAM

* %
*%

144
144

23
26

CRM5

**
*%
* %
* %

144
144
144
144

CRM5

M8548

**
*%

144
144

33
34

CRM5
CRM5

M8548
M8548

CRAM
CRAM

PAR 1ST
78 H

* %

144

CRM5

M8548

CRAM

PAR

CRA

DISP

CRM5

CRAM

CRM5

M8548

CRAM

PAR

CRM5

M8548

CRM5

M8548

CRAM
CRAM

145

* %

145

CRA3
"

PARITY

1ST

CRAM PAR 08 H

04
H

M8548
M8548

* %

1ST

74 H
PAR 12
CRAM 76 H

M8541

CrRAl

M8541

CR ADR

CRAl

M8541

ADR

145

03
04

CRAl

M8541
M8541

CR ADR
CR ADR

02
03

F
F

H
H

145

CRAl

M8541

CR ADR

CRAM
CRAM

40-43
44-47

145

20-23

CRM5

M85438

CRAM

48-51

*
*

145
145

26—29
32-35

CRM5
<CRM5

M8548
M8548

CRAM
CRAM

l46

CRA3

M8541

*
**

146

CRA3

146

M8541
M8541

146

CRA3
CRA3

52-55
56-59
LOC 05
LOC 06
LOC 07

02
03

CRA
CRA
CRA

M8541

CRA

LOC

* %

146

CRA3

MB8541

* %

146

CRA3

M8541

CRA
CRA

LOC
LOC

09
10

146

08-11

CRM5

M8548

CRAM

20-23

146

14-17

CRAM
CRAM
CRAM

32-35

146

20-23

CRM5
CRM5

M8548
M8548

146

26-29

CRM5

M8548

24-27
28-31

146
147

32-35
01

CRM5

CRA3

M8541

147

CRA3

M8541

CRA

LOC

*%
* %
* %

147
147
147

03
04

CRA3
CRA3

M8541
M8541

CRA3

M8541

CRA
CRA
CRA

LOC
LOC
LOC

*
*

147
147

08-11

CRM5

M8548

14-17

CRM5

M8548

147

20-23

CRM5

M8548

CRAM
CRAM
CRAM

01
02
03
04
00-03
04-07
08-11

147

26-29

147

32-35

CRM5
CRM5

M8548
M8548

CRAM
CRAM

12-15
16-19

NOTE

ABOUT

READING

VMA

BOARD

CRAM 36-39
CRA LOC 00

M8548
M8548

CRMS5
CRM5

08-11
14-17

145
145

—

*
*

jaciiaciicciiariiaciiaciicsiivoiiosfiariiosiiasiinsiiasiic
siie

CRA1

ofiasiiosiiasiiasiius

* %

REGISTERS

THESE FORMULAS TERSELY DESCRIBE THE DIAGNOSTIC FUNCTION
AND-

EBUS

BIT

'B'.

[]

BIT

NUMBER

(13-35,

ODD)’CORRESPONDING

(150-157)

MEANS "THE INTEGER PART OF THE QUOTIENT"

REM
() MEANS "THE REMAINDER OF"

"FORMULA FOR:
REGISTER

DIAG

ADR

153-REM(B/4)

BRK

EBUS

DITTO

157-REM(B/4)

VMA
VMA-

FUNC

HELD

DITTO

BIT

4*[B/4]1+3
4*[B/4]1+1

4*[B/4]1+3
4*[B/41+1

BETTER YET--SEE THE PRINTS!

* %

150

VMAL

M8542

151
152

VMA3
VMA4

M8542
M8542

VMA4

PCS

VMA

SECTION

153

VMA
4

153

M8542

vMaAl

M8542

153

VMA
L

- M8542

154

VMA4

VMAl
VMAl

"M8542

VMA

SEC

VMA
4

VMA
VMA

PREV SEC
PREV SEC

15
14

H
H

VMA1 VMA SECTION 0 L

‘VMA3 PC SECTION O L-

SEC

156

VMA4

M8542
M8542

157

VMA4

M8542

VMA

157
157

13
15

VMAl

M8542
M8542

VMAl

VMA3

MATCH

VMA3

MISC=0 L
LOCAL AC

SEC
REF

ADDRESS

13-35

GEN. INFO.
-98-

KL10

(PV/PW)

DIAGNOSTIC

READ

FUNCTION

CODES

SORTED

NUMERICALLY

(Cont)
*

BOARD

15X

13-35

VMA3

M8542

DRAWING

15X

13-35

VMA4

M8542

BIT

15X

13-35

VMA?2

15X

13-35

M8542
M8542

TRUTH

ADR BRK 13-35 H **NOTE
VMA HELD 13-35 H **NOTE
" VMA 13-35 H **NOTE
PC 13-35 H **NOTE

MBZ1
MBZ4

M8537

CORE

M8537

CHAN

160
160

SHD1

M8537

MBZ5

M8537

PAR

160

MBZ1

M8537

CSH

MBZ1

M8537

160

MBZ3

M8537

NXM

160

MBZ1

BUSY H
PAR ERR

PAR

BIT

CSH

DATA

ACKN

M8537

MBZ1

160

MBZ3

M8537

NXM

160

MBZ4

M8537

MBZ4

CHAN

160

MBZ3

M8537

CHAN

160
160
160

PAG5S

M8537

PAG

MBC5

M8531YA

FORCE

VALID

MATCH

MBC5

M8531YA

FORCE

VALID

MATCH

VALID MATCH
VALID MATCH

1
2

H
H

ANY

CORE

T6,7

NXM

ERR

MBCS5

M8531YA

160
160

MBC1

WRITE

MBC2

M8531YA
M8531YA

MBC1

NOTE

MBC2

CSH

ADR

NOTE

160

MBC?2

M8531YA

MBC2

CSH

DATA

H
WR

PULSE

CLR

DONE

161

MBZ4

161
161
161

MEM5
MBZ6

M8537

MBZ5

M8537

CBUS

M8537

MEM

M8537

MBZ6

PAR
PAR

LEFT
IN

CSH
C

DIAG
2

M8537

MEM

MBZ1

M8537

161

MBZ1

M8537

MBZ1

RD-PSE-WR

161
161

MBZ3

M8537

MBOX

NXM

MBZ3

M8537

MBZ3

CHAN

SEL

BIT

MBZ1

TE H

PAR

161
161

ERR

MEM REF

SBUS

REF

ERR

MBZ4

. M8537

MBOX

161

MBZ3

DATA

~“MBZ$§

. M8537
M8537

NXM

161

CSH

PAR

161

MBC2

M8531YA

MBC2 CSH DATA CLR

161
161

MBC?2

M8531YA

MBC2

CSH

DATA

CLR

MBC2

M8531YA

MBC2

CSH

DATA

CLR

NOTE

161

MBC?2

M8531YA

CSH

161

MBC2

M8531YA

MBC2

CSH

NOTE

161

MBC2

M8531YA

MBC2

CSH

NOTE

161

MBC2

M8531YA

SEL

LRU

PULSE

162

MBZ4

M8537

CHAN

162

MBZ5

M8537

CBUS

MBZ5

M8537

CSH

162

MBZ3

M8537

MBZ3

SEQUENTIAL

162

MBZ1

M8537

CHAN

READ

162

MBZ1

M8537

SEL

162
162

MBZ1

M8537

MBZ3

M8537

MBZ3

HOLD

162

MBZ4

M8537

MBZ4

NXM

162

MBZ4

M8537

MBOX

PAR

162

PAGS

M8537

PAG

00-17

162

MBZ6

M8537

CSH

PAR

BIT

NOTE

162

MBC2

M8531YA

MBC2

NOTE

162

MEM

PAR

ERR L
TE H

BIT

H
RQ

BUSY
H

ERA

H
ERR

PAR

CACHE

MBC2

M8531YA

MBC2

CACHE

NOTE

162

MBC2

M8531YA

MBC2

CACHE

NOTE

162

MBC2

M8531YA

MBC2

CACHE

NOTE

162

MBC?2

M8531YA

SBUS

ADR

NOTE

162

MBC3

M8531YA

MBC3

NOTE

162
163

MBC3

M8531YA
M8531YA

MBC3

ANY

NOTE

MBC3

NOTE

163

MBCS5

M8531YA

MBC5

NOTE

163
163

MBC3
MBC3

M8531YA
M8531YA

CSH VAL SEL ALL H

NOTE

CSH

VAL

NOTE

163

MBC3

M8531YA

MBC3

RIGHT

PAR
PAR

PULSE

162

ADR

VAL

HOLD

VAL
BIT

NOTE

HOLD

SBUS

BUSY

DATA

CSH

SEL

ALL

NOTE

163

MBC3

M8531YA

CSH

DATA

163

MBC3

M8531YA

DATA

VALID

H
OUT

164
164

MBC3

M8531YA

DATA

VALID

OUT

MBC3

M8531YA MBC3

REQ

NOTE

164

MBC3

M8531YA

MEM

NOTE

164

MBC3

M8531YA

PHASE

COMING

NOTE

164

MBC4

M8531YA

ACKN

PULSE

NOTE

164

MBC4

M8531YA

MBC4

CORE

ADR

NOTE

164
165

MBC4

M8531YA

MBC4

CORE

ADR

MBC1

M8531YA

CAM

SEL

NOTE

NOTE
NOTE

165

MBC1

M8531YA

CAM

NOTE

165

MBC4

M8531YA

NOTE

165

MBC4

M8531YA

MBC4
MBC4

1ST

INH
TO

COMING

CHANGE

CORE

COMING

CHANGE

NOTE
NOTE

MBOX ADR PAR ERR L

o BT
=l 7

NOTE

161

NOTE

PAR

FORCE
FORCE

NOTE

18-35

M8531YA

NOTE

BUSY

NXM

MBC5

NOTE

160
160

NOTE

SEL

ODD

jeafiissiiusgia]

NOTE-

AND

160
160

160

NOTE

VMA3

NAME

CHANGE

CORE DATA VAL -1 L
CORE DATA VALID -2

GEN.

INFO.

-990-

DF
NOTE
NOTE

165
165

NOTE

165

NOTE

166

DIAGNOSTIC

READ

FUNCTION

CODES

SORTED

DRAWING

BOARD

NAME

AND

MBCA4
MBC4

M8531YA

MBC4

33
27

MBC4

M8531YA

MEM

ADR

MBC4

M8531YA

MEM

M8531YA MBC4

TRUTH

CORE
CORE

DATA VALID
RD IN PROG

PAR
RQ

166
166

MBC4

M8531YA

NOTE

MBC4

M8531YA

MEM

166

MBC4

M8531YA

MEM

NOTE

166

MBC4

M8531YA

MEM

NOTE

166

MBC4

M8531YA

MBC4

NOTE

166

MBCA4

MEM

M8531YA

167

00-08

MBZ2

M8537

EBUS

MEM
WR

START

REG

167

EBUS

167

REG

27-33

14-26

MBC1

M8531YA

EBUS

REG

27-33

167
170

34,35

MBZ2

M8537

EBUS

REG

CRC6

34,35

M8535

CRC

170

CRC4

M8535

CRC4

170

CRCA4

170
170

M8535

CRC

CRC4

M8535

CRC4

M8535

CRC4
CRC4

* *

NOTE
NOTE

* %k

MBZ?2

M8537

BUF

ADR

RESET
MEM

00-08

NOTE

14-26

ENA

170

CCW4

M8534

CCW

CCW6

M8534

CCW

CCWF

REQ

CCW6

M8534

CCW

170

MEM

STORE

CCW5

M8534

CCW

ACT

FLAG

170

CCW3

M8534

CCW

170

ALU

OUT

CCW3

M8534

CCW

ALU

OUT

READY

170

CHC1

M8533

170

CHC5

M8533

CBUS

170

SEL

CHC1

M8533

CHX

RESET

170

CHC2

M8533

RESET

H
ENA

H
H

CCL5

M8536

CCL

ODD

PAR

CCL5

M8536

CCL5

GE4

170

CCL5

M8536

CCL

WC=0

CSH

170

CHX3

M8515

CSH

USE

170

CSH5

M8513YA

CSH5

PAGE

170
170

CSH6

M8513YA
M8513YA

CSH6
CSH6

CACHE WR IN
MBOX PT DIR

ANY

VAL

170

CSH2

M8513YA

CSH2

TEST

CSH3

M8513YA

CSH3

ANY

VAL

170

CSHA4

M8513YA

CSH4

DATA

170

CSH4

M8513YA

CSH

REFILL

170
170

29
30

'CSH4
MBX1

M8513YA
M8529YA

CSH4
MBX1

170
170

MBX1

M8529YA

MBX1

MBX 4"

M8529YA

CSH

170

33
34
35
00

171

MBX5
:

M8529YA

CCA

MBX5

M8529YA

MBX5

MEM

M8529YA

MBXS5

CRC5%

M8535

CRC

BUF

ADR

M8535

CRC

RH20

CRC4

M8535

CRC

OVN

CRC4

M8535

CRC

SHORT

CRC4

M8535

CRC

LONG

171

CCwW4

- M8534

CCW

WD0O

REQ

171
171

CCW4

M8534

CCW

WDl

REQ

CCW

WD2

REQ

171

CCw4

M8534

CCW

WD3

REQ

171

CCW1

M8534

CCW

MEM

ADR=0

M8534

171

CCW6

M8534

CCW

171

CHC1

M8533

171

CHCS5

M8533

CBUS

171

13
14

CHC1
CHC2

M8533
M8533

CHX

CCL3

M8536

CCL3

171

CCL3

M8536

CCL

ALU

NOTE

171
171

19
20

CCL4
CHX2

M8536
M8515

CCL

CSH

NOTE

171

CHX3

M8515

CSH

USE

H
H

ERR
ERR

H
H

WAITING

SEL

171

IN
IN

171

ERR
ERR

CCWF
T1

H
H

L
L

REQ

171
171

CCwW4

171
171

DONE

RAM

START
H
START

INTR

RIP

MINUS

TEST
ANY

VAL

PAR

TS5

CSH5

M8513YA

CSH5

CHAN

171

CSH6

M8513YA

171

CSH6

CSHA4

M8513YA

CSH4

WR DATA RDY L
PAGE FAIL T2 L

171

CSH6

M8513YA

CSH6

EBOX

LOAD

REG

171

CSH7

M8513YA

CSH7

FILL

CACHE

171

CSH5

M8513YA

CSH5

CHAN

171

"CSH3

M8513YA

CSH3

171

CSH4

M8513YA

CSH4

EBOX

171

MBX2

CACHE

CSH

SEL

171
171

MBX 4

M8529YA
M8529YA
M8529YA

171

MBX?2

M8529YA

MBX1

REQ

COMP

H
WR

HOLD

CLR

EBOX T3 L
CACHE BIT

MBX5
CRC4

L
H

REFILL

170

H
INTR

170

ENA

170

M8515

ENA

REQ

170

CHX2

DONE IN H
STORE IN H

170

STORE

170

L
A

NOTE

NUMERICALLY

(Cont)

BIT

oI
n T I

KL10 (PV/PW)

MBX1

CCA

RQ
Tl

CLR

L
NXT

SEL

INFO.

GEN.

-100-

KL10 (PV/PW)

* %k

NOTE

DIAGNOSTIC

READ

CODES

SORTED

{Cont)
DRAWING BOARD

NAME

AND

171

MEM

DIAG

MBX3

M8529YA

171

MBX5

M8529YA MBX5

CRC6

M8535

CRC

172
172

CRC3
CRC3"

M8535
M8535

CRC

READY

CRC

LAST

WORD

M8535
M8535

CRC

ERR

CRC

REVERSE

CRC3
CRC3

172
172

CCW3 . .

M8534

CCW ACT

M8534

CCW

ACT

172

CCW3

M8534

CCW

ACT

CCW

H
H

CTR

BUF

ADR

BUF
BUF

ADR
ADR

1
2

L
L

172
172

CCWl

M8534

CCW
CCW

172

CHC1

M8533

172

CHC5

M8533

CBUS

SEL

172

CHC1

DONE

CHC2

M8533
M8533

CHX

172

172
172

CCL3
CCL3

M8536
"M8536

CCL3
CCL3

172

CCL4
CHX2

M8536
M8515

CCL4

172

INTR

DONE

CCWF T2 H
MB REQ T2

REVERSE

CSH

ANY

USE

172

CHX3

M8515

CSH

172

CSH6

M8513YA

CSH6

CHAN

172

CSH6

M8513YA

172

CSH5

M8513YA

CSH6
CSH5

CCA CYC
CHAN T4

172

CHX3

M8513YA

CSH

172

CSH1
CSH6
CSH1

M8513YA
M8513YA
M8513YA

CSH1

LRU

USE

CSH1

CSH2

M8513YA

CSH2

EBOX

MBX2

M8529YA

MBX2

CACHE

MBX1

M8529YA

MBX1

CCA

172

MBX1

M8529YA

FORCE

M8529YA

MBX5

M8529YA

MBX5

MEM

MBX5

' M8529YA

MBX5

SEL

173

CRC6

M8535

CRC

REQ

SEL

MATCH

BUF

CRC2

M8535

CRC2

ACT

CTR

M8535

CRC2

ACT

CTR

173
173

CRC2

M8535

CRC2

ACT

CTR

CRC2

M8535

CRC2

RAM

CYC

173

CCW2

M8534

CCW CHA

173

CCW2

M8534

CCW

CHA

173

CCW2

M8534

CCW CHA

173

CCW2

' 'M8534

CHA

173

CCW2

M8534

173

CCW2

M8534

CCW CHA
CCW CHA

34
35

H
H

173

CHC1

173

CHCS

M8533

173

CHC1

'M8533

CHX

173

CHC2

M8533

STORE

CH T3 H
CBUS SEL

STORE

CCL4

M8536

CCL4

M8536

CCL
CCL

CH
CH

MB
MB

SEL
SEL

CCL3

M8536

CCL

NOTE

173
173

ANY

173

M8515
M8515

CSH

NOTE

CHX2
CHX3

CSH

USE

173

CSH2

M8513YA

CSH2

ONE

173

CSH2

M8513YA

CSH2

MBOX

173

CSH2

M8513YA

CSH2

173

CHX3

‘M8513YA

CSH

LRU

173

CSH5

M8513YA

CSH5

CSH4

VAL

CSH4

WRITEBACK

M8513YA

CSH7

CCA

M8513YA

CSH4
MBX4

MBX4

M8529YA

MBX2

M8529YA

MBX2

173

MBX3

M8529YA

MEM

173

MBX 2

M8529YA

173

MBX3

M8529YA

MEM TO C SEL

173

MBX 2

M8529YA

SBUS

174

CACHE
CHAN
DATA

SEL

TO
WR

HOLD

ADR

L
H

H
ADR

CRC

CRC1

M8535

CRC1

CRC5

‘M8535

CRC

CRC3

M8535

CRC3

CODE

BUF

ACT
WR

CRC3,

M8535

CRC3

174

CCW2

M8534

CCW CHA

174

CHC1

CBUS

174

CHCS5S

M8533

174

CHC1

M8533

CHX

174

CHC3

M8533

CBUS

DONE

CYC
MEM

M8535

M8533

WRITEBACK
L
;
EBOX T2 L

173

174

REQ

M8513YA

174
174

2ND

CSH7

"CRC6

RESP

PSE

~CSH4

174

WORD

173

173
-

173

ADR

CRC2

173

H
RD

173

M8533

173

CCW

MB
2

GO
H

172

MBX2

CYC

172

DONE
L

172

H
CACHE

HOLD

CCA

172

READY

CSH

VAL

173

* %

CCW1l

172

ADR

172

CCwWl

BUF

172

CCW3
.

172

NUMERICALLY

TRUTH

172

* %k

FUNCTION

FLAG

RAM

24-29

READY
E

SEL
4 E

CTOM
CTOM

H,
H

ENA

GEN.

INFO.

-101-

KL10 (PV/PW)

DIAGNOSTIC

BIT

174

16
18
19

174
NOTE

174
174

NOTE

174
174
174

* %

READ

FUNCTION

CODES

SORTED

NAME

CCL3

M8536
M8536
M8536

CCL

CHAN

REQ

CCL
CCL

CHAN
CHAN

EPT H
TO MEM

CCL3
CCL4
CHX4

AND

TRUTH

M8515
M8515

CSH

DIR

PAR

CHX3

CSH

USE

22
23

CSH2
CSH6

M8513YA
M8513YA

CSH2

CORE

PAGE

FAIL HOLD L

CSH5

PAGE

REFILL

CSHS5

M8513YA

CSH6

24
25

CHA3

M8513YA

CSH

174
174

26
27

CSH5
CSH3

M8513YA
M8513YA

CSHS5
CSH3

174

CSH1

174

CSH1

174
174

30
31

174

ANY

ODD

H
RD

TO L
PMA EN

CYC

CSH1

EBOX

CSH1

CACHE

IDLE

MBX 4
MBX1

M8529YA
M8529YA

MBX4

CACHE

MBX1

CSH

MBX 3

M8529YA

MBX6

M8529YA

MBO
MEM

DATA

CCA

ADR

SEL

174

MBX3

M8529YA

MBX 2

M8529YA

SBUS

175
175

00
01

CRC6
CRC6

M8535
M8535

CRC

SEL

175
175

02
03

CRC6
CRC6

M8535
M8535

CRC

SEL

CRC

SEL

175

CRC1

M8535

CRC1

REQ

175

05-10
11
12

CCW2
CHC1
CHC5

M8534
M8533
M8533

CCW

CHA

CHC5
CHC2

M8533
M8533

SEL

175

13
14

BUF

LAST

CBUS

SEL

CONTR

REQ

175

CCL2

M8536

CCL

CCWF

REQ

175

CCL2

M8536

CCL2

ACT

FLAG

REQ

CCL2

M8536

CCL

MEM

STORE

REQ

NOTE

175
175

CHX 4

M8515

CSH

DIR

ODD

NOTE

175

CHX3

M8515

CSH

USE

ADR

175

CSH2

M8513YA

CSH2

175

CSH6

M8513YA

CSH

USE

175

CSH3

M8513YA

TEST

PAR

CSH

CSH5

M8513YA
M8513YA

CSH3

GATE

CSH1

CSH4

M8513YA

CSH4

ONE

30
31
32

MBX 4
MBX1
MBX3

M8529YA
M8529YA
'M8529YA

MBX4

CACHE

MBX1

CSH

33
34
35
00
01
02
03
04
05

MBX6
MBX5
MBX3
CRC6.

M8529YA MB1 HOLD IN H
M8529YA MBX5 MEM WR RQ
M8529YA MBX3 SBUS DIAG
CRC CH BUF ADR
M8535

CRC1
CRC1

M8535
M8535

CRC1

MEM

PTRO

CRC1

MEM

PTR1

CRC1

M8535

CRC1

MEM

PTR2

CRC1
CCW3

M8535
M8534

CRC1

MEM

PTR3

CCL

WC=3

CCL

CCW

CHA

175

176
176
176
176
176
176

176
176

07-10
11

176
176

CCcw4

M8534

ANY

REQ

M8513YA

175

176

RETRY

M8513YA

27
28

175
* %

CSH3
CSH1

175

EBOX

CSH5

175

PAR

~_CHA3

175

VMA

27-33%

TO MB

CYC

DATA

WORD
CCA

VAL

CODE

CORE

REG LOAD
14-17 H

M8534

CCW

M8533
M8533

CBUS
CBUS

CHC1

M8533

CHC1

M8533

REVERSE

ERROR
SEL 6

REQ

INH

CCLA4

M8536

CCL4 STORE CCW H

176

CCL2

M8536

CCL

BUF

176

CCL4

M8536

CCL

START

MEM

NOTE

176

CHX4

M8515

CSH

DIR

PAR

NOTE

176

CHX3

M8515

CSH

USE ADR

176

CSH6

M8513YA

176

CSH5

M8513YA

CSH6
CSH5

CCA INVAL T4 L
PAGE REFILL T8

176

CSH4

M8513YA

CSH4

EBOX

176

CHA3

M8513YA

CSH
2 ANY

ADR
2

H
L

ODD

176

CSHS

M8513YA

CSHS

T2 L

CSH2

M8513YA

CSH2

CACHE

176

CSH7

M8513YA

CSH7

WRITEBACK

176

CSH5

M8513YA

CSH5

PAGE

MBX 4

M8529YA

MBX4

MBX 4

M8529YA

CSH

176

32
33

MBX 3
MBX6

M8529YA
M8529YA

PAR

176

MBX3

M8529YA

MBX3

REFILL

176

35
00

MBX3
CRC1

M8529YA
- M8535

MBX3

SBUS

DIAG

CRC1

PTR

DIF=0

176

177

MB2

CACHE

HOLD

TO
0

CYC

REFILL

176

CCW2

CHC1
CHCS

176

ENA

WORD

L
CSH

18-23

CBUS

174

ADR

INVAL

CODE

HOLD

CSH
ADR

M8513YA

T9,12

M8513YA

174

175

20
21

174
174

175
175

NUMERICALLY

(Cont)
DRAWING BOARD

HOLD

CYC
H

INFO.
-102-

DIAGNOSTIC

READ

BIT

DRAWING

177

CRC6

177

CRC6

177

CRC6

KL10 (PV/PW)

FUNCTION

CODES

SORTED

NUMERICALLY

(Cont)DF

BOARD

NAME

AND

M8535

CRC6

ADR

M8535

CRC6

ADR

M8535

CRC6

ADR

TRUTH

177

CRC6

M8535

CRC6

ADR

177

CCW6

M8534

CCW RAM

ADR

177
177

CCW6

M8534

CCW

RAM

ADR

CCW6

M8534

CCW

RAM

ADR

177

CCW3

M8534

CCL

WC=1

177

CCW3

M8534

CCL

WC=2

177

CCW4

M8534

CCW

ODD

ADR

PAR

177

CHC1

M8533

CBUS

REQ

177
177

12
13

CHCS
CHC2

M8533
M8533

CBUS SEL
CH CONTR

7 E
CYC

H
H

177

14
16

CHC2
ccLl

M8533
M8536

CH START
CCL1 ERR

H
REQ

177

CCL6

M8536

CCL6

CSH

CHAN

177

CCL3

M8536

CCL3

MEM

PTR

NOTE

177

CHX4

M8515

CSH

DIR

NOTE

177

CHX3

M8515

CSH

USE

ADR

177
177

22
23

CSH6

M8513YA
M8513YA

CSH6
CSH6

177
177

24
25

CSH4
CHA3

M8513YA
M8513YA

CSH4 PAGE FAIL
CSH 0 ANY WR L

CYC

PAR

PAGE
DATA

ODD

REFILL ERROR
DLY 1 L

DLY

177

CSHS5

M8513YA

CSHS5

PAGE

177

CSH1

M8513YA

CSH1

CYC

TYPE

HOLD

177

CSH2

M8513YA

CSH2

PAUSE

2ND

HALF

177

CSH4

M8513YA

CSH4

EBOX

177

MBX1

M8529YA

MBX1

CCA

ALL

CYC

177

MBX 4

M8529YA

CSH

177
177
177

MBX2
MBX6
MBX5

M8529YA

33
34

M8529YA
M8529YA

MB REQ HOLD H
MB3 HOLD IN H
MBXS5 RQ 0 IN H

177

MBX 4

M8529YA

MBX4

REFILL

T4
EN

WRITEBACK

and
the
1 l-based
10
diagnostic
interpret
all
diagnostic
read
functions
which
are
not
preceded
with
either a single or double asterisk [ (*)
or
(**)]
as single bits;
as such,
they
TRACON

programs

are

printed

out

interpreted

out

which
(**)

bit

Diagnostic

preceded

such.

are
may

either

single

registers
Diagnostic

preceded
be

position
read

interpreted

single

bits

depending
on
the
interpretation.

and

and/or

functions

asterisk

(*)

are

read

double

asterisk

and

printed

program

are

printed

functions
as

doing
'

the

PAGES

NOTE

name,

T10

GEN.

INFO.

-103KL10(PV/PW)
DF

DIAGNOSTIC

READ

FUNCTION

DRAWING

BIT

CODES

BOARD

SORTED

NAM E

AND

ALPHABETICALLY

TRUTH

NOTE

164

MBC4

M8531YA

ACK N

127

EDP3

M8512

136
132

IRD4
IRD4

M8522

CRY

-02

M8524

CRY

-02

131
137

EDP3

M8524

CRY

IRD4

M8522

CRY

PULSE

137

IRD4

M8522

.CRY

137

IRD4

M8522

CRY

137
132

IRD4

M8522

CRY

EDP3

M8524

OVERFLOW

136

IRD3

M8522

AD= 0L

15X

VMA3

M8542

ADR

126

EDP3

M8512

ADX

137

IRD4

M8522

ADX

CRY

IRD4

BRK

13-35

**NOTE

ERR

FLG

H
H

CRY

APR

ANY

EBOX

APR3

M8545

APR

EBOX

DISABLE

115

APRG6

M8545

APR

EBOX

ERA

116
116

APR3

" M8545
M8545

APR

EBUS

FO01

APR3

APR

EBUS

REQ

115

APR3

M8545

APR

EBUS

RETURN

116

APRG6

M8545

APR

REFILL

114
114

APR3
APR4

M8545

APR

M8545

APR

ADR

114

APR4

M8545

APR

ADR

114

APR4

M8545

APR

ADR

114

APR4

APR

114

APRS5

M8545
M8545

FM
FM

ADR 4
BLOCK

H
1

114

APRS5

M8545

APR

BLOCK

M8522
M8545

ADX

APR2

115

114

APRS

M8545

APR

BLOCK

137
116

114

APR5S

M8545

APR

MBOX

CTL

115

APRS5

M8545

APR

MBOX

CTL

112

APR1

M8545

APR 1

APRI1

M8545

APR 1

PF
PF

ERR
ERR

EN
IN

IN
H

110

I/0
1I/0

112

APR1

M8545

APR 1

PAR

ERR

PAR

ERR

RAM

H
H

110

APR]1

APR 1

112

APR1

M8545

APR 1

NXM

ERR

110

APR1

M8545

“APR 1

NXM

ERR

112

APR1

'M8545

APR 1

110

APRI1

M8545

110

APR1

M8545

APR

SBUS

ERR

APR 1

SBUS

ERR

APR 1

SWEEP

BUSY

H
EN

H
H

INTERRUPT

APR2

M8545

APR 2

APR

APR2

M8545

APR 2

APR2

M8545

APR 2

C
C

P
P

ERR
ERR

EN
IN

IN
H

112

APR?2

M8545

APR 2

PWR

FAIL

110
112

APR2

M8545

APR 2

PWR

FAIL

APR2

M8545

APR 2

ADR

ERR

110

APR2

M8545

APR 2

ADR

ERR

112

APR2

M8545

APR 2

SWEEP

110
115

APR2
APR2

M8545
M8545

APR 2
APR 2

DONE
SWEEP DONE
WR BAD ADR

117

APR3

M8545

110

112
110

DIR
DIR

EN IN
IN H
PAR L

APR 3

EBOX

SEND

117

APR3

M8545

“APR 3

EBUS

DEMAND

113

APR3

M8545

APR 3

FETCH

COMP

F02

APR3

M8545

APR 3

APR3

M8545

APR 3

FM
FM

113
113

APR3
APR3

M8545

APR 3

READ

EXTENDED H
ODD PARITY

COMP

M8545

APR 3

USER

COMP

113

APR3

M8545

WRITE

APR4

M8545

APR 4

AC+#

111

APR4

M8545

APR 4

AC+#

111

APR 4

AC+#

COMP

APR 3

111

APR4

M8545

111

APR4

M8545

APR 4

AC+4$#

114

APR4

M8545

APR 4

FO2

111

APRS

M8545

APR 5

CURRENT

BLOCK

111

APR5

M8545

111

APR5S

BLOCK
BLOCK

2
4

H
H

APR5

APR 5
APR 5
APR 5

CURRENT
CURRENT

111

M8545
M8545

BLOCK

111

APR5

M8545

APR 5

111

APRS

M8545

APR 5

PREV
PREV

BLOCK
BLOCK

APR 5

DIR

116

APR5

M8545

117

‘APR5S

M8545

APR 5

115

APR5S

M8545

APR 5

SET

116

APRS

117

"M8545
M8545

APR 5

APR5

WR
WR

APR 5

12
EN

H
H

WR
L

PAGE

PT
PT

1
2

FAIL

O H
1 H

SEL
SEL

APR6

M8545

APR 6

EBOX

cCCA

117

APR6

. M8545

APR 6

EBOX

EBR

115

APRS

M8545

APR 6

EBOX

LOAD

REG

115

APR6

M8545

APR 6

EBOX

READ

REG

115

111
114

GEN.

INFO.
-104-

KL10 (PV/PW) DIAGNOSTIC READ FUNCTION CODES
SORTED ALPHABETICALLY

DRAWING BOARD

NAME AND TRUTH

115

APR6

M8545

APR6

EBOX

SBUS

117

APR6

M8545

APR6

EBOX

SPARE

APR6
EDP1

M8545
M8512

APR6 EBOX UBR
AR 12 TO 35 H

M8512

ARX

M8512
M8512

BR 0 TO 35 H
BRX 0 TO 35 H

116
120

12
12-35

125

0-35

EDP2

*
*

121
124

0-35
0-35

EDP4
EDP4

(Cont)

BIT

NOTE

165

MBC1

M8531YA

CAM

SEL

165

MBC1

M8531YA

CAM

SEL

176

CHC1

M8533

CBUS

ERROR

175

CHC1

M8533

CBUS

LAST

WORD

161

‘MBZ5

M8537

CBUS

PAR

LEFT

162

MBZ5

M8537

CBUS

PAR

RIGHT

174

CHC1

M8533

CBUS

READY

170

CHC5

M8533

CBUS

SEL

171

H
H

CHC5

M8533

CBUS

SEL

172

CHCS

M8533

CBUS

SEL

173

12 -

CHCS

M8533

CBUS

SEL

174

CHC5

M8533

CBUS

SEL
4 E

175

CHC5

M8533

CBUS

SEL

176

CHC5

M8533

CBUS

SEL

177
0173

12
19

CHC5
CCL3

M8533
M8536

CBUS SEL 7 E
CCL AF T2 L

CCL3

M8536

CCW4
CCL2

M8534
M8536

CCL CCW REG LOAD
CCL CCWF REQ H

173

CCL4

M8536

CCL

173

TEST

M8536

MINUS

CCL BUF ADR 3 H

SEL

CCL4

M8536

CCL

171

.CCL4

M8536

CCL

174

CCL3

M8536

CCL

CHAN

EPT

174
174

16
19

CCL3
CCL4

M8536
M8536

CCL
CCL

CHAN
CHAN

REQ H
TO MEM

175

CCL2

M8536

CCL

MEM

170

CCL5

M8536

CCL

ODD WC

CCL4

M8536

CCL

START

176

170

PAR

REQ

PAR
MEM

CCL5S
CCW3

M8534

CCL

WC=1

CCW3

M8534

CCL

WC=2

176
177

05
16

CCW3
ccLl

M8534
M8536

CCL WC=3
CCL1 ERR

175
172

18
16

CCL2
CCL3

M8536
M8536

CCL2 ACT FLAG REQ
CCL3 .CCWF T2 H

172

CCL3

M8536

CCL3

REQ

171

CCL3

M8536

CCL3

RIP

177

CCL3

M8536

CCL3

MEM

172

CCL4

M8536

CCL4

REVERSE

176

CCL4

M8536

CCL4

STORE

CCL5

H
H

H
REQ

PTR

H
EN

CCW

CCL5

M8536

177

CCL6

'M8536

CCL6

CCW3

M8534

CCW

ACT

CTR

172

CCW3

M8534

CCW

ACT

CTR

CCW3

M8534

CCW

ACT

CTR

08
10

CCW5
CCW3

M8534
M8534

170

CCW3

M8534

172

170
170

Cccwl

GE4

172

CSH

CCW ACT
CCW ALU

CHAN

CYC

FLAG REQ
C2 OUT H

CCW ALU C8

M8534

ENA

OUT H

CCW

BUF

ADR

CCW

BUF

ADR

CCW

BUF ADR

M8534

CCW

CCWF

CCW6

M8534

CCW CCWF WAITING
H

07-10
05-10

CCW2
CCW2

M8534
M8534

‘CCW
CCW

05-10
05
06

CCW2
CCW2
"CCW2

M8534
‘M8534
M8534

CCW CHA 24-29 H
CCW CHA 30 H
CCW CHA 31 H

M8534

CCW

CHA

M8534

CCW

CHA

172

CCWl1

172

CCW1

M8534

170

CCW6

171

*
*

176
175

*
**
*ko

174
173
173

* %

M8534

CHA
CHA

REQ

L
L

L
ENA

14-17
18-23

H
H

173

* k.

173

* *
*%

173
173
171

09
10
09

CCW2
‘CCW2
CCW1

M8534
M8534
M8534

170

CCW6

M8534

CCW MEM STORE ENA H

177

CCW4

M8534

CCW

177
177

05
06

CCW6
CCW6

CCW6

M8534
M8534

M85.34

170

‘CCW4

M8534

CCW

READY

171
171

05
06

CCW4
CCW4

M8534
M8534

CCW
CCW

WDO
WDl

REQ

177

‘CCW2

STORE

CCL WC=0 L

08
09

170

M8536

SEL

H
H

177

06 16

CcCcL2

ALU

171

CCL

176
175

176

CCW2

NOTE

DIAG

CCW CHA 34 °H
CCW CHA 35 H
CCW MEM ADR=0
ODD

ADR

PAR

CCW RAM ADR
~ CCW RAM ADR

1 H
2 H

CCW RAM ADR 4 H'
REQ

H
H

INFO.

GEN.
-105-

KL10(PV/PW)

DIAGNOSTIC

SORTED

READ

ALPHABETICALLY

FUNCTION

CODES

(Cont)

BIT

DRAWING

BOARD

NAME

AND

TRUTH

171

CCW4

CCW

WD2

REQ

171

cCcw4

M8534

CCW

WD3

REQ

177

CHC1

M8533

CBUS

REQ

177

CHC2

M8533

175
174

CHC2
CHC3

M8533

CONTR

M8533

CTOM

172
176

CHC2
CHC1

M8533
M8533

DONE

170

CHC2

M8533

RESET

REVERSE

CONTR

CYC

REQ

INTR

REQ

INH

INTR

176

CHC1

M8533

175

CHC5

SEL

177

" CHC?2

M8533

START

171

CHC2

M8533

START

INTR

173

CHC2

M8533

STORE

170

CHC1

M8533

171

M8533

H
H
H

CHC1
CHC1

M8533
M8533

172

173

CHC1

M8533

162

MBZ4

M8537

CHAN

ADR

PAR

ERR

160

MBZ3

M8537

CHAN

NXM

ERR

160

MBZ4

M8537

CHAN

PAR

ERR

162

MBZ1

M8537

CHAN

174

CHC1

M8533

CHX

CTOM

172

CHC1

M8533

CHX

DONE

READ

170

CHC1

M8533

CHX

RESET

171

CHC1

M8533

CHX

START

173

CHC1

M8533

CHX

STORE

102

CLK4

M8526YA

CLK

EBOX

REQ

100
102

CLK1
CLK1

M8526YA
M8526YA

CLK
CLK

EBUS CLK H
ERROR STOP

102
100

CLK4
CLK4

M8526YA CLK
M852AYA CLK

103

CLK4

M8526YA

CLK

103

CLK4

M8526YA

CLK

PAGE

100

CLK1

M8526YA CLK SBUS CLK H

103

CLK2

M8526YA

CLK2

BURST

104

CLK2
CLK2

M8526YA
M8526YA

CLK2
CLK2

EBOX
GO L

102

104

CLK3

M8526YA

CLK3

CRAM PAR

ERR

103

CLK3

M8526YA

CLK3

DRAM

ERR

104
107

CLK3
. CLK3

M8526YA
M8526YA

CLK3

EBOX SOURCE
ERROR L

M8526YA

FORCE
INSTR

CLK3

FM
FS

CLK3

SYNC

CLK4

M8526YA

CLK4

M8526YA

CLK3

103
103
102

CLKA4

107
106
101

CLK4
CLK5
CLK5

101

CLK5

101

fast

H
H

H
jas]

ERROR

M8526YA" CLK3

CLK3
‘CLK3

102

1777
1777

XFER

M8526YA

105
106

PAR

PAR ERR
ERROR H

1777

M8526YA

CLK4

EBOX

CLK

CLK4

PAGE

FAIL

- M8526YA
M8526YA
M8526YA

CLK4

PAGE

FAIL

CLK5

AR/ARX

CLK5

BURST

M8526YA

CLKS5

BURST

PAR

CLK5
CLKS

M8526YA

CLK5

BURST

H°

M8526YA

CLKS

BURST

CLKS

CLK5

BURST

128

101

CLK5

BURST

101

CLKS
CLK5=~

M8526YA
M8526YA

100

CLK5

M8526YA
M8526YA

CLK5
CLKS

BURST
BURST

32
64

H
H

105

CLK5

106

CLK5

105

CLK5

107

CLK5

106

CLKS

107
104

CLK5
CLK5

107

CLKS

104

CLKS5

.
H

M8526YA
M8526YA
‘M8526YA

CLK5

CRAM

PAR

CHECK

CLK5

DRAM

PAR

CHECK

CLK5

EBOX

CRM

DIS

M8526YA
M8526YA

CLK5

EBOX

CTL

DIS

CLK5

EBOX

EDP

DIS

ERR

STQP

M8526YA

CLK5

PAR

CHECK

MBOX

CLK5

M8526YA

105

~ ~“M8526YA CLK5 MBOX

107

CLK5

M8526YA CLKS5

106

CLKS

105

CLK5

M8526YA

104
136

CLK5
CON4

M8526YA
M8525

137

M8525

133

CON4
CON4

131
133

CON3
~CON2

137

CON2

RATE
RATE

H
L

CYCLE DIS H
RESP SIM L
SEL

SEL

CLK5 SOURCE SEL
CON AR 36 H
H
CON ARX 36

M8526YA "CLK5

CLK5

L
L

CHECK

SOURCE

CON

ARX

M8524

CON
CON

CACHE LOAD EN H
CLR PRIVATE INSTR

M8525

CON

COND ADR

M8525
M8525

M8526YA CLK5 BURST CNT=0

M8526YA CLK5
M8526YA CLKS

CHECK

101

CLKS5

H
EN

100

LOADED

GEN.

INFO.
-106~

KL10 (PV/PW) DIAGNOSTIC READ FUNCTION
SORTED ALPHABETICALLY (Cont)

BIT

DRAWING BOARD

NAME AND TRUTH

132
133

18
22

CON1
CON2

M8525
M8525

CON COND EN 00-07 L
CON COND INSTR ABORT H

132
133

19
19

CON1
CON1

134
132

M8525
M8525

CON COND/SEL VMA L
CON COND/VMA GETS #

M8525
M8525
M8545

CON
CON
CON

134
136
131
134
136
132
135
132

24
24
21
22
22
22
19
21

CONS
CON5 CON3
CON2
CON2
CON2
CON1
CON2

M8525
M8525
M8525
M8525
M8525
M8525
M8525
M8525

L
CON FM WRITE PAR L
CON FM XFER L
CON KI10 PAGING MODE
CON LOAD ACCESS COND
CON LOAD DRAM H
CON LOAD IR L
CON LOAD SPEC INSTR
CON LONG EN L

CON5

M8525

CON

21
21
21

CON2
CON2
CON2

M8525
M8525
M8525

CON NICOND 07 H
CON NICOND 08 H
CON NICOND 09 H

134
133

21
21

CON2
CON4

M8525
M8525

CON NICOND TRAP
CON PC+1 INH L

133
134

18
18
20
20

CON1
CON1

CON3
CON3

‘M8525
M8525
M8525
M8525

CON
CON

134
135

134
135
136

23
23
23

23
19

CON4
CON4
CON4
CON4
CON1

M8525
M8525
M8525
M8525
M8525

130
135
131
130
130

18
22
18
19
20

CON3
CON2
CON3
CON3
'CON3

M8525
M8525
M8525
M8525

M8525

2 L
CON WR EVEN PAR ADR
CON2 INSTR GO L
CON3 CACHE LOOK EN H
CON3 WR EVEN PAR DATA H
CON3 WR EVEN PAR DIR H

133

CONS5

M8525

L
CONS5 MEM CYCLE

01
02
03

. CRA1
CRAL
CRAl

CRA1l

04
24

20
20
22

132
160

24
15

145
145

04
05

145
145
145

144

CONS5
CONS5

CON3
CON3
CON3

CON1

M8524
M8525

M8525
M8525
M8525

M8525

CON4

M8525

CONS
MBZ1

M8525
M8537

CRA1
CRAL

CRALl

M8541
M8541
M8541

M8541
M8541

M8541

* %

144

CRA2

M8541

* %k
*%
*%
*%
* %
*%
*%

144
141
141
141
141
141
141

05
00
01
02
03
04
05

CRA2
CRA4
CRA3
CRA3
CRA3
CRA3
CRA3

M8541
M8541
M8541
M8541
M8541
M8541
M8541

*%
*%
*%
*%
*%
*%
*%
*%
*%
* %
*%
*%

144
144

140

140
143
145 147
147
147
147
147
146
146
146
146

146
146

03
04

00
00
00
01
02
03
04
05
00
01
02
03

04
05

CRA2
CRA2

CRA3

CRA3
CRA3
CRA3
CRA3
CRA3
CRA3
CRA3
CRA3
CRA3
CRA3
CRA3
CRA3.

CRA3
CRA3

M8541
M8541

"M8541

M8541
M8541
M8541
M8541
M8541
M8541
M8541
M8541
M8541
- M8541
‘M8541
M8541

M8541
M8541

MBOX

WAIT

L
H

135

132

*%
*%

DELAY REQ H
EBUS REL H
FM WRITE PAR

135
136
137

136

CON COND/LOAD VMA HELD H
M8525
M8525. CON COND/MBOX CTL L

CON3
CON3
CON5

137
137

*%
*%

CON1
CON1

18
20
11

136
137
131

19
20

135
133
117

134
137

*%
*%
*%

CODES

CON PI CYCLE A L
CON PI DISMISS L
CON

SKIP EN
SKIP EN
SR 00 H

CON

SR 01

40-47
50-57

L
L

CON SR 02 H
CON SR 03 H
CON TRAP EN H

CON UCODE STATE 01 H
CON UCODE STATE 03 H
CON UCODE STATE 05 H

CON UCODE STATE 07 H
CON VMA SEL 1 L
CON VMA SEL

CON4 AR LOADED H

CONS
CORE

PI CYCLE H
BUSY H

CR ADR 00 F H
CR ADR 01 F H
CR ADR 02 F H

CR ADR 03 F H
CR ADR 04 F H

CR ADR 05 F H

CR ADR 06 F H
CR ADR 07 F H

CR ADR 08 F H
CR ADR 09 F H

CR ADR 10 F H
CRA CALL, RESET H
CRA DISP 00 H
CRA DISP 01 H
CRA DISP 02 H
CRA DISP 03 H
CRA DISP 04 H

CRA DISP EN 00-03 L
CRA
CRA
CRA
CRA
CRA
CRA
CRA
CRA
CRA
CRA
CRA
CRA

DISP EN 00-07 L
DISP EN 30-37 L
DISP PARITY H
LOC 00 H
LOC 01 H
LOC 02 H
LOC 03 H
LOC 04 H
LOC 05 H
LOC 06 H
LOC 07 H
LOC 08 H

CRA LOC 09 H
CRA LOC 10 H

GE N.

INFO.

~107-

DIAGNOSTIC

SORTED

READ

FUNCTION CODES

ALPHABETICALLY

(Cont)

DRAWING

BOARD

NAME

143

CRA4

M8541

CRA

SBR

RET

61V

143

CRA4

M8541

CRA

SBR

RET

143

CRA4

M8541

CRA

SBR

RET

143

CRA4
CRA4

M8541
M8541

CRA
CRA

SBR
SBR

RET

142

CRA4

M8541

CRA

SBR

RET

142

CRA4

M8541

CRA

SBR

RET

142

CRA4

M8541

CRA

SBR

142
142

CRA4

M8541

CRA

SBR

RET

CRA4

M8541

CRA

SBR

RET

142
140

CRA4
CRA4

M8541
M8541

CRA

SBR

RET

CRA

STACK

ADR

140
140

CRA4

M8541

CRA

STACK

ADR

CRA4

M8541

CRA

STACK

ADR

140
147

CRA4
CRM5

M8541
M8548

CRA

STACK

ADR

CRAM

00 -03

147

CRM5

M8548

CRAM

04 -07

147

CRAM

08 -11

TRUTH

CRM5

M8548

CRM5

M8548

CRAM

CRM5

M8548

CRAM

16 -19

146
145

CRM5

M8548

CRAM

20 -23

12 -15

24 =27

CRAM

CRM5

M8548

CRAM

28 -31

CRM5

M8548

CRAM

32 -35

146

CRM5
CRM5

M8548
M8548

CRAM

36 -39

145

CRAM

40 -43

145
145

CRM5
CRM5

M8548
M8548

CRAM

44 -47

CRAM

48 -51

145

CRM5

M8548

CRAM

52 ~55

145

CRM5

M8548

CRAM

56 -59

144

CRM5

M8548

CRAM

144

CRM5

M8548

CRAM

CRM5

M8548

CRAM

M8548

CRAM

CRM5

M8548

CRAM

144

CRM5

M8548

CRAM

144

CRM5

M8548

CRAM

144

CRM5

M8548

CRAM

144

CRM5

M8548

CRAM

144

CRM5
CRM5

M8548
M8548

CRAM

PAR

144

CRAM

PA R

144

CRM5

M8548

CRAM

PAR

144

CRM5

M8548

CRAM

PAR

144
144

CRM5

M8548

CRAM

PAR

CRM5

M8548

CRAM

PAR

1S T

jasiiasfiavifasiias

M8548

CRM5

144
144

M8548

CRAM

PAR

1S T

M8548

CRAM

PAR

1S T

144
144

CRM5

M8548

CRAM

PAR

18 T

CRM5

M8548

CRAM

PAR

1S T

170

CRC6

M8535

"CRC

BUF

ADR

CRC6

M8535

CRC

BUF

ADR

171

172

CRC6

M8535

CRC

BUF

ADR

173

CRC6

M8535

CRC

BUF

ADR

174

CRC6

M8535

CRC

BUF

ADR

175

CRC6

M8535

CRC

BUF

ADR

176
172

CRC6

M8535

CRC

BUF

ADR

ERR

CRC3

M8535

CRC

CRC3

M8535

CRC

LAST

WORD

171

CRC4

M8535

CRC

LONG

170

CRC4

M8535

CRC

MEM

STORE

171

CRC4

M8535

CRC

OVN

ERR

172

CRC3

M8535

CRC

READY

172

CRC3

M8535

CRC

REVERSE

171
175

CRC4

M8535

CRC

RH20

CRC6

M8535

CRC

SEL

175

- CRC6

M8535

CRC

SEL

CRC6

M8535

171

CRC4

M8535

CRC

SHORT

CRC5

M8535

CRC

174

-~ CRC1

175

M8535

CRC1

176

CRC1

176
176

CRC1

M8535

CRC1

M8535

176

CRC1

M8535

177

CRC1

M8535

173

CRC2

173

CRC2

CRC

SEL

ERR

ENA

ERR

175

172

174

jusfiasiiasiiangasiiasiias

CRM5
CRM5

NV
W N
O

144
144

jasfijaciiasiiasiien)

CRMS5

jusfisiiaviasilesiiasiiaofieofiasfian

M8548

146
146

144

[aajis s iasiia siiasiia
viinsfiasiiaciariiiacjiis
o iias e o

RET

147

144

RET

147

CRM5

usiiariiasiiasiiariiasfiizefianiiasiicoiias

AND

asfiasiiasiian]

KL10 (PV/PW)

L
WC

RAM

ERR

CRC1

ACT

M8535

CRC1

M8535

CRC1

ME M

PT RO

CRC1

MEM

PT R1

CRC1

ME M

PT R2

“CRC1

ME M

PT R3

CRC1

PT R

DI F=0

M8535

CRC2

AC T

CTR

~M8535

CRC2

AC T CTR

FLAG
REQ

ENA

H
H

GEN.

INFO.
-108-

KL10 (PV/PW)

DIAGNOSTIC

SORTED
DF

BIT

DRAWING

BOARD

NAME

AND

TRUTH

CRC2

M8535

~ CRC2

ACT

CTR

173
174

04
03

CRC2
CRC3

M8535
M8535

~ CRC2
CRC3

RAM CYC
OP CODE

H
00

174

CRC3

M8535

CRC3

NOTE

CRCA4

M8535

CRCA4

M8535

CRC4 STORE IN H

CRC4

RESET

177
177

01
02

CRC6
CRC6

M8535
M8535

CRC6
CRC6

CH
CH

ADR
ADR

0C
1C

177

CRC6

~ M8535

CRC6

ADR

177

CRC6

M8535

CRC6

ADR

170

CHX2

M8515

CSH

ANY

VAL

177

CHA3

M8513YA

CSH

ANY

171

CHX2

M8515

CSH

ANY

VAL

175

CHA3

M8513YA

CSH

ANY

172

CHX2

M8515

CSH

ANY

VAL

'CHA3

M8513YA

CSH

ANY

CHX2

M8515

CSH

ANY

VAL

ANY

173

CRC4

CODE

174

NOTE

174

NOTE

175

CHX4

NOTE

176

CHX4

NOTE

177

160
173

19
25

172

161
162
162

CRC4 DONE IN H

170

176
NOTE

170

NOTE

CODES

(Cont)

173

170

NOTE

READ FUNCTION

ALPHABETICALLY

M8535

L
L
L
L
L

L
L
L
L

L
L

CHA3

M8513YA

CSH

CHX4

MB8515

CSH

DIR

PAR

ODD

M8515

CSH

DIR

PAR

ODD

M8515

CSH

DIR

PAR

ODD

CHX4

M8515

- CSH

DIR

PAR

ODD

MBZ1
CHX3

M8537
M8513YA

CHX3

M8513YA

CSH

LRU

MBZ6

M8537

CSH

PAR

BIT

26
17

MBZ6
MBZ5

M8537
M8537

CSH
CSH

PAR
PAR

BIT
BIT

B H
IN H

.
~

CSH
CSH

EN CSH DATA
LRU 1 H

H
H

170

CSH4

M8513YA

CSH

REFILL

NOTE

161

MBC2

M8531YA

CSH

SEL

LRU

NOTE

175

CHX3

M8515

CSH

USE

ADR

NOTE

CHX3
CHX3
CSH6
CHX3

M8515

ADR

M8515
M8513YA
M8515 -~

CSH
CSH
CSH
CSH

USE

NOTE

176
177
172
170

USE
USE
USE

ADR 4 H
HOLD H
IN O H

NOTE
NOTE
NOTE
NOTE

171
172
173
174

21
21
21
21

CHX3
CHX3
CHX3
CHX3

M8515
M8515
M8515
M8515

CSH USE
CSH USE
CSH USE
CSH USE

163
176
177

31
31
31

MBC3
MBX 4
MBX 4

M8531YA CSH WR SEL ALL
M8529YA CSH WR WD 0 EN
M8529YA CSH WR WD 1 EN

32
32
29

MBX 4
MBC3
CSH1

'M8529YA CSH WR WD 3 EN H
M8531YA CSH WR WR DATA H
L
M8513YA CSH1 CACHE IDLE

NOTE

NOTE
NOTE

NOTE

175
163
163

170

NOTE

21
27
21

171
163
174

23
29
30

172

CSH6
MBC3
MBC3

M8513YA
M8531YA
M8531YA

MBX 4

CSH
CSH
CSH

RAM

IN
IN
IN
IN

1 H
2 H
3 H
4 H

USE WR EN H
VAL SEL ALL
VAL WR DATA

H
H

H
H
H

M8529YA CSH WR WD 2 EN H

CSH1

M8513YA

CSH1

CCA

CYC

177

CSH1

~ M8513YA

CSH1

CYC

TYPE

174

CSH1

M8513YA

CSH1

EBOX

CYC

175

CSH1

M8513YA

CSH1

172

CSH1

M8513YA

CSH1

READY

176
174

27
22

CSH2
CSH2

M8513YA CSH2
M8513YA CSH2

E
E

172

'CSH2

M8513YA

CSH2

EBOX

175

CSH2

M8513YA

CSH2

EBOX

173

CSH2

M8513YA CSH2

MBOX

173

CSH2

M8513YA

CSH2

ONE

WORD

177

CSH2

M8513YA

CSH2

PAUSE

170
174

25
27

CSH2
CSH3

M8513YA
M8513YA

CSH2
CSH3

WR TEST
ADR PMA

L
EN

CSH3

M8513YA ‘CSH3

ANY

HOLD

27
28
27
24
29

' CSH3
CSH3
CSH4
CSH4
CSH4

173

170

175
171
170
176
171

CSH2

173

170

CSH4

177

'~ CSH4

175

CSH4

177

CSH4

'CSHA4

173

171

CYC

M8513YA CSH3
M8513YA CSH3
M8513YA CSH4
M8513YA CSH4
‘M8513YA CSH4

CSH4

~
-

HOLD

L
TO

CACHE WR CYC
CORE RD RQ A
REQ

RETRY

RESP

M8513YA CSH2 RD PSE

H
L

L
REQ

L
RD

2ND

HALF

2ND REQ

VAL

M8513YA

CSH4

EBOX

CSH4

EBOX

M8513YA'
CSH4 EBOX WR T4
M8513YA

CSH4

ONE

M8513YA

CSH4

PAGE

WORD

FAIL

DLY

M8513YA CSH4 PAGE FAIL T2

CSH4

M8513YA

CSH4

WRITEBACK

CSH5

M8513YA

CSH5

CHAN

GATE VMA 27-33 H
MB WR RQ CLR NXT
DATA CLR DONE L
EBOX TO L
EBOX T1 L.

‘M8513YA

L
H

GEN.

INFO.

~-109-

KL10 (PV/PW)

DIAGNOSTIC

SORTED

READ

FUNCTION

ALPHABETICALLY

CODES

(Cont)

BIT

DRAWING

BOARD

NAME

AND

172

CSH5

CHAN

171

CSH5

M8513YA
M8513YA

CSH5

CHAN

174

CSH5

M8513YA

CSH5

CSH

170

CSH5

M8513YA

CSH5

PAGE

177

CSH5

M8513YA

CSH5

PAGE

REFILL

T10

CSHS

M8513YA

CSH5

PAGE

REFILL

176

TRUTH

TS5

REFILL

COMP

176
174

M8513YA

CSH5

PAGE

REFILL

CSH5

M8513YA

CSH5

PAGE

REFILL

T9,12

173

CSH5

M8513YA

CSH5

176

CSH5

M8513YA

CSH5

175

CSH5

M8513YA

CSH5

170

CSH6

M8513YA

CSH6

CACHE

172

CSH6

M8513YA

CSH6

CCA

CYC

176

CSH6

M8513YA

CSH6

CCA

INVAL

172

CSH6

M8513YA

CSH6

CHAN

177
171

CSH6

M8513YA

CSH6

DATA

DLY

CSH6

M8513YA

CSH6

EBOX

LOAD

DONE

CACHE

REG

170

CSH6

M8513YA

CSH6

MBOX

CSH6
CSH6

M8513YA

CSH6

PAGE

FAIL

M8513YA

CSH6

PAGE

REFILL

171

CSH6

CSH7

M8513YA
M8513YA

CSH6

173

CSH7

CCA WRITEBACK

DIR

DATA

L
L

ERROR

RDY

CSH7

M8513YA

CSH7

M8513YA

CSH7

106

CTL1

M8543

CTL

LONG

106

CTL1

M8543

CTL

ADX

CRY

105

CTL1
CTL2

M85473

CTL

ADX

CRY

100

M8543

CTL

00-08

LOAD

104

CTL2

M8543

CTL

00-11

CLR

101

CTL2

M8543

CTL

09-17

LOAD

12-17

WRITEBACK

FILL CACHE

105

CTL2

M8543

CTL AR

CTL2

M8543

CTL

ARL

SEL

100

CTL2

M8543

CTL

ARL

103

CTL2

M8543

CTL

ARL

SEL

106

CTL2

M8543

CTL

ARR

CLR

100

"CTL2

M8543

CTL

ARR

LOAD

101

CTL2

M8543

CTL

ARR

LOAD

103

CTL2

M8543

. CTL

ARR

SEL

102

CTL2

M8543

CTL

ARR

SEL

102

CTL2

M8543

CTL

ARX

LOAD

105

CTL2

M8543

CTL

ARXL

SEL

104

CTL2

M8543

CTL

ARXL

SEL

107

CTL2

M8543

CTL

ARXR

SEL

106

CTL2

M8543

-CTL

ARXR

SEL

102

CTL1

M8543

CTL

COND/AR

103

CTL1

M8543

CTL

DISP

107

CTL1

M8543

CTL

INH

CRY

136

CTL1

M8522

CTL

104

-~ CTL1

M8543

CTL

LOAD

M8543

CTL

SEL

105

‘CTL2

L
H

GETS

CRY

RET

=N
D

SEL

CLR

EXP

L
18

104

CTL2

M8543

CTL

SEL

106

CTL?2

. M8543

CTL

MQOM

103

CTL2

M8543

CTL

MOM

SEL

102

CTL2

M8543

CTL

MOM

SEL

107

CTL2

M8543

CTL

SPEC

CALL

101

CTL1

M8543

CTL

SPEC

MTR

CTL

101
104

CTL1

M8543

CTL

SPEC/CLR FPD H
SPEC/FLAG CTL H

H
H

H
L

CTL1

M8543

102

CTL1

M8543

CTL

SPEC/GEN

CRY 18

136

CTL1

M8522

CTL

SPEC/GEN

CRY

100

CTL1

M8543

CTL

SPEC/SAVE

100

CTL1

M8543

CTL

SPEC/SCM

105

CTL1

M8543

CTL

SPEC/SP

SPEC/STACK

CTL

18
FLAGS

ALT

MEM CYCLE

103

CTL1

M8543

CTL

163

MBC3

M8531YA

DATA

VALID

OUT

NOTE

164

MBC3

M8531YA

DATA

VALID

OUT

M8543

DIAG

LOAD

EBUS

M8543

DIAG

MEM

RESET

IRD1

M8522

ADR

IRDI1

M8522

130

IRD1

M8522

ADR

131

IRD1

M8522

ADR

131

IRDI

M8522

ADR

131

IRD1

130

M8522

ADR

M8522

ADR

IRD1

M8522

ADR.

133

IRD1I

M8522

DRAM

133

IRD1

M8522

DRAM

131

IRD1

131

IRD1

131

ADR

jasijesiieviasifasiiuciiesiasiiian]

CTL3
CTL3

130

fuofiuciii-die-dih
i v v 5 B I

107
107

NOTE

ADR

171

101

HOLD

176

174
177

UPDATE

REG
H

H
H

GEN.

INFO.
-110-

READ.FUNCTION

IRD1

M8522

IRD1

M8522

DRAM

IRD1

M8522

DRAM

M8522

DRAM

IRD1

M8522

DRAM

134
134

IRD1

M8522

DRAM

IRD1

M8522

DRAM

134

135

DRAM

W T

R e B o=

134

DRAM

M8522

DRAM

M8522

IRD1

135

IRD1

M8522

DRAM

135
135

IRD1

M8522

DRAM

IRD3

M8522

DRAM

ODD

PARITY

135

IRD1

M8522

DRAM

PAR

102

PIC4

M8532

EBUS

CS00

102

PIC4

EBUS

cso01

102

PIC4

M8532

EBUS

CS02

102

PIC4

M8532

EBUS

CS03

103

PIC4

M8532

EBUS

CS04

102

PIC4

M8532

EBUS

CSs05

102

PIC4

M8532

EBUS

CS06

102

PIC2

M8532

EBUS

DEMAND E

167

MBZ2

M8537

EBUS

REG

00-08

167

MBZ2

M8537

EBUS

REG

14-26

167

MBC1

M8531YA

EBUS

REG

27-33

167

MBZ2

REG

34,35

M8537

EBUS

120

EDP1

M8512

EDP

120

EDP1

M8512

EDP

120

EDP1

M8512

EDP

120

EDP1

M8512

EDP

120

EDP1

M8512

EDP

120

EDP1

M8512

EDP

120

'EDP1

M8512

EDP

120

EDP1

M8512

EDP

120

M8512

EDP

EDP1

M8512

EDP

EDP1

M8512

EDP

AR
AR

09
10

120

EDP1

M8512

EDP

133

SCD2

M8524

133

ScD2

M8524

133

scp2

ofiia s fia via n}

TonIITonoD@onIoDITom

EDP1

120

mEmoEoEEmE
o

120

[z Ja ofifa siie o

M8532

jusfiia=giusiicsiiesiiasiiasiiiasiiusiife
s siies]

M8522

IRD1

135

IRD1

D T

133
133

133

CODES

(Cont)

oMM T I E

SORTED ALPHABETICALLY
133

DIAGNOSTIC

. KL10(PV/PW)

M8524

133

SCD2

M8524

133

SCD2

M8524

132

SCD2

M8524

132

scp2

M8524

132

SCD2

M8524

132

SCD2

M8524

132
135

SCD2

H
35

SCD2

M8524
M8524

09
SIGN

123

EDP4

M8512

172

MBX1

M8529YA

FORCE

NOTE

160

MBC5

M8531YA

FORCE

VALID

MATCH

NOTE

160

MBC5

M8531YA

FORCE

VALID

MATCH

NOTE

160

MBC5

VALID

160

MBC5

M8531YA
M8531YA

FORCE

NOTE

FORCE

VALID

136
132

IRD4

M8522

GEN

IRD1

M8522

132
132

IRD1

M8522

IRD1

M8522

132

IRD1

M8522

132

IRD3

M8522

I/0,

-,k

* *

* %

MATCH
MATCH

CRY

132

TRD3

M8522

136

IRD1

I/0

134

IRD3

M8522
M8522

JRST

130

IRD3

M8522

NORM 08

130
130

IRD3

M8522

NORM

IRD3

M8522

NORM

JRST
LEGAL H
0,

174

MBX3

M8529YA

DATA

CODE

MBX3

M8529YA

DATA

CODE

160

MBZ1

M8537

‘MB

SEL

M8537

SEL

161

MBZ1

162
160

"MBZ1

M8537

MBZ5

M8537

MB-

PAR

BIT

MBX3

M8529YA

PAR

HOLD

MBX2

M8529YA

REQ

171

MBX?2

M8529YA

SEL

172

MBX2

M8529YA

SEL

173

33
24

MBX?2

M8529YA

SEL

HOLD

CSH3

M8513YA

TEST

PAR

175

H
IN

177

175

176

H
H
IN

GEN.

INFO.

-111-

KL10 (PV/PW)

DIAGNOSTIC READ FUNCTION CODES

SORTED ALPHABETICALLY

(Cont)

BIT

DRAWING BOARD

NAME AND TRUTH

174
175

33
33

MBX6
MBX6

M8529YA
M8529YA

MB(O
MB1

HOLD
HOLD

IN
IN

176

MBX6

M8529YA

MB2

HOLD

H
H
H

177

MBX6

M8529YA

MB3

NOTE

160

MBC1

M8531YA

MBCl1

WRITE

NOTE

162

MBC2

M8531YA

MBC2

CACHE

NOTE
NOTE

162
162

28
29

MBC2
MBC2

M8531YA
M8531YA

MBC2
MBC2

CACHE
CACHE

WR
WR

09
18

A
A

H
H

NOTE
NOTE

162
160

30
32

MBC2
MBC2

M8531YA
M8531YA

MBC2
MBC2

CACHE WR 27 A H
CSH ADR WR PULSE

NOTE
NOTE

160
161
161
161

33
27

MBC2
MBC2

M8531YA MBC2
M8531YA MBC2
M8531YA

MBC2

CSH DATA CLR DONE
CSH DATA CLR Tl L
CSH

DATA

MBC2
MBC2

CSH
CSH

DATA CLR T3 L
VAL WR PULSE H

NOTE

NOTE
NOTE

NOTE

MBC2

CLR

H
IN

161

29
31

MBC2
MBC2

M8531YA
M8531YA

161

MBC2

M8531YA MBC2

CSH WR WR

PULSE

COMING A

NOTE

162

MBC3

M8531YA MBC3

A CHANGE

NOTE
NOTE
NOTE
NOTE
NOTE
NOTE
NOTE
NOTE
NOTE
NOTE

163
164
164
164
165
165
165
165
166
163

27
28
32
33
29
30
31
32
32
28

MBC3
MBC3
MBC4
MBC4
MBC4
MBC4
MBC4
MBC4
MBC4
MBC5.

M8531YA
M8531YA
M8531YA
M8531YA
M8531YA
M8531YA
M8531YA
M8531YA
M8531YA
M8531YA

MBC3
MBC3
MBC4
MBC4
MBC4
MBC4
MBC4
MBC4
MBC4
MBC5

B CHANGE COMING L
INH 1ST MB REQ H
CORE ADR 34 H
CORE ADR 35 H
CORE DATA VAL -1 L
CORE DATA VALID -2 L
CORE DATA VALID L
CORE RD IN PROG A H
MEM START L
CORE BUSY B H

161

M8531YA MBC3 ANY SBUS RQ

162

MBZ4

M8537

MBOX

ADR

161
161

22
24

MBZ3
MBZ4

M8537
M8537

MBOX
MBOX

NXM ERR L
SBUS ERR L

‘170

MBX1

M8529YA

MBX1

CACHE

177
170
171

30
31
31

MBX1
MBX1
MBX1

M8529YA MBX1
M8529YA MBX1
M8529YA MBX1

CCA ALL
CCA REQ
CCA SEL

PAGES
L
1 H
2

M8537

MBOX MB

PAR

ERR

ERR
L

BIT

CYC

172

MBX1

M8529YA

MBX1

CCA

174
175
171

31
31
30

MBX1
MBX1
MBX2

M8529YA
"M8529YA
M8529YA

MBX1
MBX1
MBX2

CSH CCA INVAL CSH H
CSH.-CCA VAL CORE H
CACHE TO MB 34 H

172

MBX2

M8529YA

MBX2

CACHE

176
175

34
35

MBX3
MBX3

M8529YA
M8529YA

MBX3
MBX3

REFILL HOLD
SBUS DIAG 3

176

MBX3

M8529YA

MBX3

SBUS

DIAG

173

MBX 4

M8529YA

MBX4

CACHE

174
175
176
177
170

30
30
30
35
33

MBX4
MBX4
MBX4
MBX4
MBX5

M8529YA MBX4
M8529YA MBX4
M8529YA MBX4
M8529YA MBX4
M8529YAa MBX5

173

172

MBX?2

M8529YA MBX2

SEL

TO MB

CHAN WR

CYC

MBX5

M8529YA

MBX5

M8529YA

MBX5

M8529YA MBX5

MEM WR

MEM

MBX5
MBX5

M8529YA

MBX5

M8529YA

MBX5

RQ
RQ

IN
IN

171
172

35
35

MBX5
MBX5

M8529YA MBX5
M8529YA MBX5

RQ
RQ

2
3

IN
IN

H
H

160
161

22
21

MBZ1
MBZ1

M8537
M8537

MBZ1
MBZ1

CHAN CORE
RD-PSE-WR

161
162

23
22

MBZ3
MBZ3

M8537
M8537

MBZ3
MBZ3

CHAN
HOLD

162
162

18
23

MBZ3
MBZ4

M8537
M8537

MBZ3
MBZ4

SEQUENTIAL
NXM T2 H

160
161
105

24
18
18

MBZ4
MBZ56
MCL2

M8537
M8537
M8544

MBZ4 NXM T6,7 L
MBZ6 CSH PAR BIT
MCL LOAD AR H

102
115

19
15

106
105

19
19

103
107
103

19
19

MCL1
MCL1

MCL1
MCL2
MCL2

MCL2
MCL?2

M8544
M8544
M8544
. MB8544

MCL
MCL
MCL
MCL

MEM
ERA

H
L

177

MCL2
MCL5
MCL2
MCL2

IN
EN

170

18
22
18
19

DONE

170

106
107
107
104

BUSY H
REF L
REF
L

LOAD ARX H
MBOX CYC REQ H
STORE AR L
.
VMA USER H

‘M8545

MCL1 MEM/ARL IND H
MCL1 MEM/REG FUNC L

M8544
M854 4

MCL2 VMA PREVIOUS L
MCL2 VMA PUBLIC H

M8544

M8544
M8544
M8544

H
L

CACHE TO MB T2 L
CACHE TO MB T3 L
CACHE TO MB T4 A
WRITEBACK T2 L
MB REQ IN H

175

CYC

MCL1 REQ EN
MCL2 VMA EXTENDED
MCL2 VMA PAUSE H

GEN.

INFO.
-112-

KL10(PV/PW) DIAGNOSTIC READ FUNCTION
'SORTED ALPHABETICALLY (Cont)
DF

BIT

DRAWING

BOARD

NAME

102

18
18

MCL2

M8544

MCL2 VMA READ H
MCL2

VMA WRITE

105

MCL3

M8544

MCL3

PAGE

106
102
104
103
102
103

20
20
22
23
22
22

MCL3
MCL3
MCL4
MCL4
MCL4
MCL4

‘M8544
M8544
M8544
M8544
M8544
M8544

. MCL3
MCL3
MCL4
MCL4
MCL4
MCL4

104

NOTE

MCL4

VMAX SEL

M8544

MCL4

23
22
22
21

MCL4
MCL5
MCL5
MCL5

M8544
M8544
M8544
M8544

MCL4
MCL5
MCLS5
MCL5

XR SHORT H
18 BIT EA H
23 BIT EA H
VMA ADR ERR

MCL5
MCL6

MCL5
. MCL6

MCL®6

M8544
M8544
-M8544

MCL6

VMAX EN L
EBOX CACHE
EBOX MAP L

MCL6
MCL6
MCL®
MCL6
MCL6

M8544
M8544
M8544
'M8544
M8544

MCL6
MCL6
MCL6
MCL6
MCL6

EBOX MAY BE PAGED
PAGE UEBR REF H
PAGED FETCH L
REG FUNC H
VMA FETCH H

107

.105
104
107
106
107

23
20
21 .
23
20

103

MCL6

M8544 -~ MCL6

33
21
32
34
17

MBC4
MBZ1
MBX3
MBX 3
MEM5

‘M8531YA
M8537
M8529YA
M8529YA
M8537 -~

MEM ADR PAR H
MEM BUSY H
MEM DATA TO MEM
MEM DIAG L
MEM PAR IN H
MEM

VMA

166

MBC4

M8531YA

28
29
30
31
19
29

MBC4
MBC4
MBC4

‘M8531YA MEM RQ
M8531YA MEM RQ
M8531YA MEM RQ

NOTE

166
166
166
166
161
164

NOTE
*
*

166
122
113

*
*

112
114

173

174

117

111

115
110

MBC4
'EDP2
MTR1

M8531YA MEM RQ 3
MEM TO C
M8537

H
DIAG

M8531YA MEM

TO C

- M8529YA MEM TO C SEL

MBX3

0 H
1 H
2 H

M8529YA MEM TO C SEL

MBX3

2 H

M8531YA MEM WR RQ L
MQ O TO 35 H
M8512
MTR CACHE COUNT 02-17
M8538

MTR3

M8538

MTR

CONO

M8538
M8538

MTR
MTR

EBOX COUNT 02-17 H
INTERVAL 06-17 H

160

13-35
30

110
110

16 15~

116
116
116~

100
101

*%
* %
*
*%
*%

101
101
101
101
101

13
14
15
16
17

M8538

MTR2 ACCT ON H

M8538

MTR2

EXEC

MTR2
MTR2

M8538
M8538 -

MTR2
MTR2

PI ACCT
TIME ON

.~ MTR3

INTERVAL

M8538

“ PAGS

M8537- PAG MB

PICl

NXM

DATA VAL

PAG MB 00-17 PAR H
18-35

PAR H

M8542

PC 13-35 H **NOTE

M8545

PI3 APR PIA 01
H

M8545
M8545

PI3 APR PIA 02
PI3 APR PIA 04

M8531YA PHASE CHANGE COMING

PIC3
PIC3.

PIC1
PIC1
.PIC1
PIC1
PIC1

MTR3 INTERVAL OVRFLO H
~MTR5 INCR SEL 1 H
~ MTR5 INCR SEL 2 H
MTR5 VECTOR REQ H
NXM ACKN H
.
NXM ANY L

M8537

PIC3

PIC1
PIC1

EN
H

M8537-

VMA3
MBC3

ACCT

INTERVAL DONE

M8538
M8538
M8538
M8538
M8537
M8537

PIC3
PIC3
PIC3

12~.

MTR3

MTR3
MTR5
MTRS
MTR5
- MBz3
MBZ3
MBZ3-.

PAG5

110

MTR PERIOD 06-17 H
MTR TIME 02-17 H

M8538
~M8538

'MTR2

MTR3

MTR2

MTR3

21
- 23
22
21
20
21
23
25

MTR,

MTR PERF COUNT 02-17 H

M8538

MTR1
20-35
MTR3
24-35
20-35 = MTR1

MTR1
MTR1

115
115
117
117
117
160
160
161

101

RD RQ

H
L

35
34
33
10
11

*ro

UPT

20-35
24-35

21
25 -

15X
164

.23

162 .

*
*
*

33
0-35
'20-35

116
116

115

MBC4
MBZ1
MBC3

116
116

NOTE

165
162
173
171
161

NOTE

*
*
*

2 H

M8544

1 H

MCL4 VMAX SEL

MCL4

21
23

COND

PAGE ILL ENTRY H
PAGE TEST PRIVATE H
LOAD VMA CONTEXT L
SHORT STACK H
VMA GETS AD H
VMA INC H

NOTE
NOTE
NOTE
NOTE

ADDRESS

MCL4

102
106
105
103
104
104

TRUTH

105

102

M8544

MCL4

106

M8544

AND

CODES

H
H

M8538
PI3 MTR PIA Ol H
M8538- PI3 MTR PIA 02 H M8538
PI3 MTR PIA 04 H
=~M8532
PICl ACTIVE H
M8532
PICl GEN
1 H

M8532

PICl GEN 2 H

M8532
'M8532 .
M8532
M8532
M8532

PICl
PICl
PICl
PICl
PICl

GEN 3
GEN
4
GEN S5
GEN
6
GEN 7

H
H
H
H
H

GEN.

INFO.

-113-

FUNCTION CODES
(Cont)

BOARD

NAME

AND

100

PIC1

M8532

PICl

100

PIC1

M8532

PIC1

100

PIC1

100

PIC1

M8532

100

PIC1

M8532

PIC1

100

PIC1

M8532

PIC1

M8532

PICL

M8532

PICL

TRUTH
~NOY
U
W N

DRAWING

100
100

PIC1

M8532

PIC1

100

PIC1

M8532

PIC1

PIH2

100

PIC1

M8532

PIC1

100

PIH3

PIHI

PIC1l

M8532

100

PIC1

100

‘M8532

PIC1

PIH5

PIC1

M8532

PIC1

100

PIH6

PIC1

M8532

PIC1l

PIH7

PIC1

PIH4

103

PIC?2

M8532

PIC2

103

HONOR

PIC2

M8532

PIC2

READY

103
103

PIC2

M8532
M8532

PIC2

STATE

HOLD

DONE

PIC2

INTERNAL

TIMER

103

PICS

M8532

PIC5

103

EBUS

PICS

M8532

161

PIC5

EBUS

REQ

MBC2

M8531YA

HOLD

GRANT

173

MBX
2

M8529YA

SBUS

ADR

MBX
2

162
136

MBC2

M8529YA

SBUS

ADR

M8531YA

SBUS

ADR

HOLD

SCD2

M8524

131

.GE.

SCD2

M8524

SC
SC

j=ufitar e sl as e ofite sfianlia o flle o

131

SCD2

M8524

131
131

SCD2
SCD2

M8524
M8524

SCD2

130

M8524

SCD2

M8524

130

SCD2

M8524

130

SCD2

M8524

130

SCD2

130

M8524

SCD2

M8524

SIGN

134

SCD2

133

M8524

SCD1

M8524

137

SCAD=0

SCD5

M8524

SCD

H
H
H

ADR

BREAK

PREVENT

SCD5

M8524

137

SCD

ADR

BRK

CYC

SCD5

M8524

SCD

ADR

BRK

INH

SCD4

M8524

131

SCD4

131

M8524

SCD4

SCD

CRY1

M8524

SCD

DIV

CHK

SCD

CRYO

132

SCD4

M8524

SCD

FOV

SCDh4

M8524

SCD

FPD

H
H

132

SCD4

M8524

135

SCD

FXU

SCD5

M8524

136
134

SCD

KERNEL

SCD5

M8524

SCD

KERNEL

USER

SCD5

M8524

133

~SCD

LEAVE.

USER

SCD5

M8524

133

131

SCD4

. M8524

SCD4

M8524

SCD4

M8524

135

SCD5

M8524

135

SCD5

135

SCD5

MODE

SCD

OV
H

PCP

M8524

SCD

PRIVATE

SCD

PRIVATE

M8524

SCD

PUBLIC

INSTR

SCD5

M8524

134

PUBLIC

SCD5

M8524

137

SCD

PUBLIC

SCD4

PAGE

M8524

130

SCD

TRAP

CLEAR

SCD4

M8524

SCD

TRAP

CYC

H
H

SCD

130

SCD4

M8524

SCD

TRAP

SCD3

CYC

136

M8524

SCD

TRAP

MIX

SCD3

M8524

SCD

TRAP

137

MIX

SCD3

M8524

137

SCD

TRAP

MIX

SCD3

M8524

SCD

TRAP

MIX

SCD4

M8524

130

SCD

TRAP

REQ

SCD4

M8524

134

SCD

TRAP

REQ

scps

M8524

SCD

USER

134

SCD5

M8524

SCD

USER

IOT

136

SCDS

M8524

136
160

SCD

SCD5
SHD1

M8524
M8537

SCD USER IOT EN
SH AR PAR ODD A

105

SHD1

M8526YA

ARX

106

SHD1

111

SHM1

134
15X

IRD3
VMA2

15X

VMA4

PAR

ODD

PAR

ODD

M8540

SHM1

M8522

TEST

SATISFIED

mM8542

VMA

L
H

H
H

EXTENDED

13-35

136

130

IOT

SCD LOAD FLAGS A H
SCD NICOND 10 H

A H
EN L

135

130

133

137

131

174

131

* %

READ

ALPHABETICALLY

DIAGNOSTIC

SORTED

DD mmID D T T T T

KL10 (PV/PW)

**NOTE

HELD

13-35

SCD4

M8542
M8524

VMA

132

VMA

HELD

100

MCL3

M8544

VMA

HELD

**NOTE

GEN. INFO.
-114-

KL10 (PV/PW) DIAGNOSTIC READ FUNCTION
SORTED ALPHABETICALLY (Cont)
DF

BIT

DRAWING

BOARD

NAME

100

MCL3

M8544

VMA HELD OR PC 02 H

*x
**

100
100

20
21

MCL3
MCL3

M8544
M8544

VMA HELD OR
VMA HELD OR

PC
PC

03
04

* %

100

MCL3

VMA

HELD

VMA

HELD

MCL3

"‘M8544

AND

CODES

TRUTH

H
H

VMA HELD OR PC 05 H
PC

101

MCL3

M8544

101

MCL3

M8544

VMA HELD OR

* %

*x
**
**
**
**
**

20
21

MCL3
MCL3

M8544
M8544

VMA HELD OR
VMA HELD OR

PC
PC

09
10

H
H

MCL3

M8544

VMA

23
11
11
11

MCL3
VMA4
VMA4
VMA4

M8544
M8542
M8542
M8542

VMA HELD OR PC 12
H
VMA PREV SEC 13
H
VMA PREV SEC 14 H
VMA PREV SEC 15 H

VMA1l
VMA1l

M8542
M8542

VMAl AC REF A L
VMAl LOCAL AC ADDRESS L

* %

100

101
101
101
101
157
156
155

* %

154

153

11
11

VMA4
VMA4

13
15

157
153
153

150
157
151
152

M8544

13
11
15

VMA1
VMAl
VMA3

VMA3

M8542
M8542

KL10

M8542
M8542

PV/PW CROSS

DIAGNOSTIC

VMA
VMA

M8542
M8542
M8542

VMA4

VMA3

VMA4

FUNCTION

PCS

CHA

M853

CHX
PMA

M8520YA
M8521

M855
M856

PAG
CHD

M8531YA

M857

MBC

functions

either

(**)]

which

single

SECTION

CHART

M854

NOTE

SECTION

CODES

M8518YA

the

VMA SECTION O
MATCH 13-35H

diagnostic

1ll-based

are

not

preceded

with

bits;

as such,

they

interpret

all

diagnostic

or double

single

asterisk

read
[(¥*)

are printed out by bit position and/or
name.,
Diagnostic
read
functions
preceded by a single asterisk
(*)
are
‘interpreted as registers and are printed
out as such.
Diagnostic read functions

which are preceded by a double asterisk
(**) may be interpreted and printed as
either
single
bits
or
as
a
register
depending
on
the
program
doing
the
-

interpretation.

H
H

MISC=0

M852

and

16
17

VMAl

programs

SEC
SEC

VMAl
VMA3

REFERENCE

READ

PREV
PREV

M8514
M8515

TRACON

HELD

PC 08

GEN.

INFO.

=115~

KL10

DATA

PATH

PARITY

NETWORKS

There are very' few places

in the KL10 system that generate parity.

Generally,

once parity is generated,
it is passed from component
to component and checked for errors in the process.
This reduces
the chance of having
undetected
errors.
The KL10 system has two
parity
generation
(PG)
networks:
one
is
at
the
output
of
the
arithmetic
register
(AR);
the
other
1is
at
the
output
of
the
channel status words. Proper parity is generated when data leaves
memory,

the

memory buffer.,
This parity remains with
memory, the EBus, and the memory buffer,

the

cache,

fast

the

data

EBus,

cache,

the

fast

There are
instances
where
the
data
paths
must
decrease
from
36
bits to 18 bits,
or
increase
from 18 bits
to 36 bits.
In these
cases, parity folding generation occurs. As an example, when data

passes

from

the

memory

buffer

the

input

there is a conversion from 36 bits to
is generated
to
check each
18 bits).

side

the

page

table,

18 bits
(and proper
Conversely,
as data

parity
passes

from the RH20 to the channel, there is a
to 36 bits
(because the RH20 deals with
channel deals with 36-bit entities).

conversion from
18-bit entities

18 bits
and the

networks,

are

addition

parity
These

the

checking
parity

two

parity

networks

checking

the memory
as
it is

generation

the

side

data

and

networks
of

the

data

path

there
of

the

six

system.

follows.

the DMA20 from memory

received

leaves

major

are

DMA20

and

Parity
is
enters

checked on
the DMA20,

and

goes

through

the

KBus

registers

memory.

the

output

the

memory

buffer

(MB)

Parity
1is checked when data
leaves
a memory buffer
for
any of
the
following:
memory,
the hardware page
table,
channel,
cache,
AR,
or the arithmetic register extender

(ARX)
.

the

output

data

comes

the

device

data

travels

the

RH20.

and

Oon

the

of
of

side

the

Parity

are

the

coming
CRAM

APR

checks

Massbus

‘

STATUS

checked

mass

checked

device

storage

data

leaves

the

arriving

the

RH20

mass

storage

the

AR from

checks

other
DRAM.

stored

two

are

For

both

the

microword

and

CONI

parity

the

controls

and

output

these,

use

data

the

parity

it.

(CONO

APR

24-31,

flags

bits

clearing

for

the

cache

(bits

the

Bit
is

which

and

APR

ADDRESS

flags

sweeper

system

allow

enabling,

MBox.

This

memory

system.

also

of operation

(read,

conditions,

33-35

Bits

are

busy.

conditions.

nonexistent

6-13

the

enabled.
When

are

indicate

are

the

When

CONO

used

that

one

priority

bit

for

the

interrupt

CONI

word

CONI

bit

set

all

indicate

ERA

error

SBus,

reset.

The error address

are

error

set

Bits

device.

selected

the

eight

24-31)

eight

true.

operations)

These
memory,
fail, MB parity, cache directory, address parity, power
and cache sweep done. Four bits
(20-23)
in the CONO word
whether
to
enable,
disable,
clear,
or
set
the
selected
flags).

ERROR

The
the

before

conditions

(Bits

I/0

data

setting,

error

selected

the

Parity

the
to

the

memory.

word

selected

fast

memory.

devices

I1/0 page
failure,
indicate

level

output

each

disabling,

flags.

Parity
table.

‘

fast

the

ERROR

eight

RH20

from

checked

the

output

from

Internal

the

also

page

On
the ARX It
checks
data
arriving
at
the
ARX
from
three other parity checklng networks in the system.
One

and

checked

table
-

Massbus

page

hardware

memory.
0
There

the
the

put

device,

side
out

or ERA,

contains

the

contains

write,

is an

internal

flags

that

last

the

etc.)

has

address

been

requested

indicate

requested.

the

what

type

Until

error occurs, the ERA register is changing with every address that
is
being
sent
by
the MBox
to
the
memory
system
for
reading
or
writing.

When

error

occurs,

the

ERA

latches

the

GEN.

INFO.
~116-

last

address

sent

the

MBox

the

memory

‘system,

The

ERA

remains latched until the software is able to correct the error
address and until
the
error address
1is
recorded
in
the
system
error log for field service.
As

mentioned

previously,

there

are

eight

error status register. Three
software
(upon an
interrupt

of
to

error

ERA register

error

bits

the

APR

these error bits indicate to the
the APR)
that the ERA register

contains error
information.. These three error bits are: bit 25
(Nonexistent Memory Error), bit 27 (MB Parity Error), and bit 29
(SBus Address Parity Error). The software reads the contents of
the ERA register, using the appropriate internal device code (BLKI
PI), and clears the three error bits in the APR register. When the
bits

are

subsequent
Layout

When
at a

the

again

ready

for

the

ERA

the MBox makes a reference to memory, it requests four words
time: the word that the EBox needs is requested first and the

other

of
in

cleared,

error.

three

in quick

the four words
physical,
not

reference

equals

memory.

when

succession.

Bits

0-1

indicate

in which

Cache

Reference

bit.

the error occurred (note that word numbers
<chronological
order).
Bits
2-6
identify

the

Bit

memory

the

error

Clear

occurred

while

the cache

are
the

was

sweeping. Bit 3 jis the Channel Reference bit, It equals 1 if the
error occurred when the channel was making a refernce to memory.
Bits 4 and 5 comprise a data source code that indicates where, in
the MB, the data originated. Data may come from: memory on a read
or a read-pause-write, the channel
on a storing status (writing
into memory), the AR on an EBox write, cache on a page refill or
channel read operation, cache on a write operation to memory. The
data source field is not valid on an address parity error. Bit 6
is
the
write
reference
bit.
It
equals
1
if
a
memory
write
operation

Bits

was

14-35

from
that

group

progress

the

when

the

physical

error

occurred.

address

that

the

EBox

requests

the MBox. If the reference requires only a single transfer,
address is the error address. If the reference triggers a

transfer,

then

DIAGNOSTIC

CYCLE

reference

SBUS

contain

bits

chronologically

14-35

are

the

the group.

address

‘the

first

The SBus diagnostic cycle is used to communicate between the MBox
and the internal memory controllers. Because there are no switches
associated with the internal memory controllers, functions such as

address
boundaries,
interleave
mode,
controlled using the diagnostic cycle. The

diagnostic

cycle

when

gives

the

margining,
etc.,
are
processor initiates the

instruction

send

function

word to a particular controller and to receive an error word and
diagnostic
information back
from
it.
The MBox
executes the
diagnostic
cycle
and
uses 36
SBus
data
lines
to
transfer

information. A macroinstruction, BLKO PI, (700500) takes a 36-bit
input argument and returns a 36-bit output argument. The microcode
for this instruction puts the 36-bit input argument in the AR and
tells

the

MBox

execute

turns on its response
the cache data lines
the

output

Layout of

SBus

diagnostic

argument,

the

cycle.

When

the

MBox

signal, the microcode clocks the contents
into the AR and returns the information

SBus Diagnostic

of
as

Cycle

There are two halves to the SBus dlagnostlc cycle- the first is
"to memory" (700500) and the second is "from memory" (E+1l). Also,
‘for each controller (DMA20, MA20, MB20), there are two function
codes:

and

01l.

‘

GEN.

INFO.

-117-

SBus

Diagnostic

Bit(s)

Name

0-4

Controller

Cycle,

"To

Memory",

Function

specify

with

Description
Address

Bits

0-4

controller

the

communicating.

the

internal

MB20.

Clear

Error

true

for

and

function

01.

bit

set

Bus

Mode

"from

are

cleared.

function

then

flags

memory"

the

DMA20.

both

MA20

specifies

0-4,

specify

controller:

error-reporting

6-7

0-3

controllers:

Bit

external

This

which

MBo X

Bits

the

(bits

function

00)

(DMA20)

Interleave

Mode

(MA20/MB20)
8-11

SBus

Load

6-7

Load

6-11

31-35

Function

Bit (s)

Name

Request
(MA20/MB20)

Enables

The
SBus
Request
Enables
bits
assign
odd
or
even
status
to
the
controller
for
interleave
modes.

(DMA20)

(MA20/MB20)

Code

SBus Diagnostic Cycle,

Function 01

Description

0-4

Controller

Loopback

14-17

SBus

18-21

Low ‘Address

Address

Address
(MA20/MB20)
Boundary

(MA20/MB20)
22-25

"To Memory",

High

Bits

18-25

with

the

14-17)
Address

Boundary

act

upper

Load

14-25

(MA20/MB20)

Bit

address

bits

27-30

enables

14-25,

the
bit

reads

bits

set

(bits

lower

and

limits

loading
26

set

14-25.
loads and

If
it
reads

back.

Select

Margins

(MA20/MB20)

Bits

27-30

control

of
current,
threshold.
When
not

set,

the

set,

all

bit

29
1is

either

threshold,
If

bit

margin

Function Code

cleared.

the

current

set,

margin

bit

code

eguals

not

set,

Set,
01,

strobe

margin

low.

With

bit

current,
is

margin

the

30
is

1is

strobe

threshold

operational.,

are

bit
are

set,

the

operational.

for

and

control

operational.

set,

the

amount

bits

margin

margins

margin

the

strobe,

nonoperational.

31-35

conjunction

address

specify

(MA20/MB20)
26

memory

set

high.
the

the

function

INFO.

GEN.

-118—

SBus Diagnostic Cycle,

Bit(s)

Function 00

"From Memory",

Description

Name
expansion)

0-1

(for

Incomplete Cycle

Read Parity Error

Write

Address Parity Error

(NXM on DMAZ20)

(DMA20)

Bits 2-5 are error-reporting
If

bit

cycle,

half

memory"

the "to

memory

the

flags

controllers.

these

then

set

flags

are

cleared.

bits

6-7

reporting

the

error

Parity Error

(DMA20)

Bus Mode

6-7

(Interleave Mode on

MA20/MB20)

(DMA20)

8-11

Last Request

12-13

Last Type (DMA20)

14-35

Address or First Address
of

Error

Setting

off-line mode.
did

the

Bit 12 is
bit

what

ask:

8-11

Bits

word

occur?

failure

the

1in

00,

indicates

controller,

either

quad

request and

read

request.

the write

(DMA20)

SBus Diagnostic Cycle, "From Memory", Function 01

Bit(s)

Name

Description

0-17

Storage Modules
Installed (DMA20)

These bits indicate the number
of storage modules connected to

4-7

" Storage Modules

particular

8-11

Controller Type

Loopback

14-17

Installed

SBus Address

22-25

controller,

bit

Setting

indicates

the

presence of a storage module.

Bits

8-11

the

identify

memory

type.

(MA20/MB20)

Low Address Boundary

18-21
»

(MA20/MB20)

Bits 18-25 indicate the address

boundaries

the

"to

that

the

located

memory" half of function 1.

High Address Boundary

(MA20/MB20

Margin On (MA20/MB20)

Bit

current,

margin

indicates

strobe,

control

threshold

on.

‘Requests Enabled

32-35

(MA20/MB20)

DESCRIPTION OF

SBUS

ERRORS

MA20/MB20

Incomplete Cycle - Occurs on a

the processor

read-pause-write

(RPW)

cycle when

fails to send valid data to the memory to initiate

of the RPW cycle. It also occurs on any cycle
the write portion
that the memory fails to complete before the 8.0 us timeout. The
MA20/MB20 signals the occurrence of this error by sending an SBus

"error

the

processor.

Address Parity Error - Can occur at the start of any memory cycle.
The MA20/MB20 signals the occurrence of this error by sending the
SBus address parity error to the processor. Thus, the processor is
notified of the occurrence of the error within 125 us. The address
that the processor was attempting to reference when the error

occurred becomes latched in the ERA register. An address parity
error flag is set in the MA20/MB20 to indicate the occurrence of
‘
this error.

GEN.

INFO.

-119-

DMA20

Data

Parity Error - Both
during the three types of
sets

appropriate

logic

stores

the

after

not

until

last

Address

error)

may

signals

the

error

bit

DMA20

error

detection

the

MBox.

the

processor

read

until

the

cycle,

250

occurrence

the
parity

error

cleared.

sent

processor

DMA20

first

The

arrive

the

The

error

not

arrives.

error

status

the

word

Parity

the

associated

(SBus

arrive
SBus

the

read and write are checked
memory cycles. Each type of

address

signal

the

arrives.
an

the

signal

error

flags

the

cumulative

write

after

this

cycle,

until

error

address

the

error

500

signal

may

last

word

sending

processor.

Error

Can occur at the start of any memory cycle.
of this error by sending the SBus
to
the
processor.
Thus,
the
processor
is
notified of the occurrence of the error within 125 us. The address
that
the
processor
was
attempting
to
reference
when
the
error
occurred
becomes
latched
in
the
ERA
register.
An
address
parity
error flag is set in the DMA20 to indicate the occurrence of this
error.
The
address
that
the
DMA20
receives
at
the
time
of
the
error is latched in the DMA20 error address registers.
The

DMA20

address

signals

parity

the

occurrence

error

NOTE

The address parity
is only checked
for
SBus addresses and does not include KBus
addresses.
NXM

Error

storage

acknowledge

module,

and

any

The

DMA20

error

address

us.

The

the

DMA20

address

data

sends

error.

notified

SBus

received

reference

from

the

cycle

first

does

not

storage module did not
respond),
then a
flag
is set
in the DMA status register,
register becomes frozen in the same way as

parity

processor

(ACK)

subsequent

receive an ACK
(i.e.,
a
nanexistent memory
(NXM)

The

timeout

immediately

for

this

after

error

the

timeout

error.

when

MBOX
SBus

Error

When

the

MBox

DMA20,
it sets the
information is held in

the

sees

SBus

the

error

ERA

SBus

APR

error

flag

from

the

this

occurrence

MA20/MB20

EBox.

valid

error.

SBus Address
parity error

Parity Error - When the MBox sees the SBus address
from the MA20/MB20 or DMA20,
the MBox sets the SBus
address
parity
error
flag
in
the
APR
status
register.
The
ERA
register
in
the MBox
is
latched
when
the
error
is
detected.
It
does
not
unlatch
until
the
software
clears
the
APR
flag
after

having

Data

copied

Parity

the

data

Error

out

The

the

ERA.

parity

all
data leaving
the MBs
is
If the parity is
incorrect,
the address of the location
referenced:
an 8-bit code
indicating
the source of the data,

checked.

is
and

two

the
in

bits

ERA.
the

Page

Table

25).

The

error

indicating

the MB that held
information
is held until

This

EBox

(APR

Parity

error

status

page

word)

Error

the

Forces

result

refill,

of
a

the

bad

the

page

either
fatal

fail

memory,

error

the

If there is a fatal error on the hardware
solid failure, then the hardware page table

Cache
the

Directory

cache

Parity

directory,

are

held in
error flag

Error

When

flag

set

parity
the

trap

cache

table.

word

parity

cleared.
1is

parity
page

page

error

APR

(code

data

hardware

table and
unusable.

detected

The

cache

is
effectively
turned
off
at
the
end
of
the
current
memory
reference and remains "off"TM until the cache directory parity error
flag
in
the
APR
status
register
1is
<cleared.
This
error
is

nonrecoverable
scan

the

cache

before

NXM

Error

nonexistent
memory,

bad

the

parity.

the

monitor
An

The

memory,

the

latched

data

KL10

error

EBox
in

(if

flag

MBs

this

PDP-11
off

the

parity
error

able

the affected

reproducable).
APR

zeros

discarded.

the

turn

addressed.

words

data
is

type

but

and

error

set

1is

four

gets

the

mode

the

location

supplies

when

software,

diagnostic

reload

memory
MBox

MBox

cache

During

EBox

trap.
The

occurs.

the

During
ERA

when

read

write

from

that
in

has

to
the

INFO.

GEN.

-120-

EBOX

AR/ARX Parity Error - Parity is checked on all data that
the AR/ARX for use by the EBox. If a failure is detected,
fail trap which has a code of 36/37 occurs.

enters
a page

EBus Parity Error - All words that enter the AR/ARX from the EBus
if the parity was generated by the
are checked for parity
transmitting device. If an error is detected, an I/O page fail.
interrupt occurs, and the monitor is able to determine that the
bad

data was

received

from the

Fast

Memory

Parity

Error

EBus.

stored

word

Each

fast

memory

generates odd parity as it leaves the AR. If the fast memory word
(ADB) mixer, parity is checked. If

is read out through the Adder B

an error is detected, and if fast memory parity checking is
enabled by the console processor, then the EBox clock is halted.
CRAM

and

DRAM

EBox

clock

Parity

Errors

0d4dd

parity

generated by

the

microcode assembly program for each word stored into the CRAM and
DRAM. This is done each time these RAMs are loaded. When a word in
If an error
either RAM is referenced, odd parity 1is checked.
occurs and the halt on the error diagnostic function is enabled,
the

halted.

RH20

Data Parity Error - Occurs when the RH20 detects bad parity on a

data transfer from the device. If disable transfer error stop is
set, the transfer will continue after a status flag is set. If the
disable transfer error stop is not set, the EXC is set and an
is

interrupt

sent to

the

EBox.

SUMMARY OF PARITY ERRORS

There are two ways in which the software recognizes parity errors.

The

Trap

Method

trap

instruction sequence of the

CPU

an- interruption
caused

an attempt

the

execute that instruction. Control passes to a trap
routine that attempts to solve the problem. When a trap
occurs, the software retries and if the error does not
repeat, then there is a successful recovery. There are

two types of page fail traps: page table parity error
(code 25), and AR/ARX data parity error (code 36/37).

An Interrupt on the APR - Interrupts differ from traps in

that they are usually caused by an external activity. In
many cases, the software is unable to recover by retrying. In other cases, such as channel errors, the software

is able to recover by retrying the I/0O operation. In all
cases, core memory is reviewed by the sweep instruction
in the search for and the recording of more errors.
‘

Address Parity Errors

Address parity errors are detected by the MA20/MB20 or the DMA20

on a read, write, or read-pause-write. Address parity is a way of
checking the bus and drivers that exist between the MBox and the
MA20/MB20 or
MA20/MB20

the DMA20.

Response

When, during a read, the MA20/MB20 detects an address parity error
on the address lines coming from the MBox, the MA20/MB20 returns
four words of zeros with bad parity to the MBox. The bad parity is

detected throughout the system by the parity network. Thus, parity
is never regenerated, but is simply checked along the way, at each
level. During a write from the MBox to the MA20/MB20, the
controller throws away the data. The MA20/MB20 does not write the
data into memory because it is not clear into which address it
should be written, since there is a parity error in the address.

DMA20 Response

The DMA20 does not respond to the MBox

if an address parity error

occurs during a read and a write. Instead, the MBox does a timeout

and gives a normal nonexistent memory interrupt to the CPU on the

APR. The DMA20 does not attempt to read or write memory, but it
whether the
always checks all addresses on the memory bus,
for the MA20/MB20 or the DMA20. Therefore,
addresses are intended

the DMA20 may send an address parity error condition to the CPU
via SBus address parity error, even if the address is intended for
the MA20/MB20.

GEN.

INFO.

-121-

Nonexistent Memory (NXM)
The ERA register is valid

and

MBox

APR

nonexistent

memory

caused.

response

from

interrupt

because

there

when

NXM

error
the

after 64 us. The software determines which
and the source of the request.
If address
set, the error is an address parity error,
is,

the

error
64

DMA20

does

the

Consequently,

failure

not

respond

Because

the

address.

period,

the

when

MBox

both

NXM

where

software

the

1is

parity

reads
four

write

Thus,

memory,

However,

everything

data

parity

the

exist.

error

parity

Another

form

NXM

logs

and

the

ERA

error

parity

are

the

NXM.

the

real

indicated
memory
zeros,

so that the EBox gets a data parity
The
software
checks
to
see
if
the
in
bounds,
i.e.,
does
the
address

software

the

DMA20

after

from the
words
of

the

NXM,

error

the

occurs

the

does,

This

routine

data

occurred.

trap

because the EBox detects a parity error on the NXM
that
an APR
interrupt
also
occurs with
the
ERA

error word.
routine.

is
is

what

errors

If the MBox
will
supply

expects

programmed

there

aware

address

occurs

the

response,

should

and

software

retries

there

with bad parity, to the EBox
trap when
it
uses
the
data.
address
being
referenced
is
exist

lack

that

in the APR error status word.
when
the NXM occurs,
the MBox

procedure

address

word received the NXM
parity error
is also
not a NXM error. That

concludes

software

error

detected

MA20/MB20

the

retry
occurs

condition. Note
latched
to
the

the

and

APR

the

interrupt

MBs

lost.

valid.
if

the

first word requested by the MBox is acknowledged. However, if
the
subsequent
three
words
does
not
send
back
acknowledgement within 28 us, a NXM condition is indicated to

DMA20.

occurs

one
an
the

software

via

NXM

error

the

specific

SBus

interrupt

error
on

word

interrupt

the

that

APR.

The

received

the

APR,

remembers

NXM

condition.

reads
this
address
from
the DMA20 by
using
function. In this case, the ERA is not valid.
CRAM

and

0dd

parity

DRAM

stored

RAMs

are

PDP-11

generated

into

loaded.

parity
1is
diagnostic

of
the
information is
in a condensed

the

CRAM

When

detect

state

the

checked.
function

must

microcode

and

DRAM.

word

If
1is

an
error
enabled,

this

and

save

the

overlay

the

associated

the

RAM.

compared

Memory

0dd

parity

the

AR,

the

detected

copy

with

Parity

the

diaqnostic

ADB

and

program

done

RAM

1is

for

each

time

the

referenced,

odd

entire

internal

hardware

each

word

the

checked

mixer.

front-end
"good"

contents

processor

contents

the

validates

(from

disk

RAM.

Error

generated

Parity

through

gsoftware

machine
by
using
diagnostic
functions.
This
included in the system error file, and presented,
form, on the operator's console.

error-recording

Fast

occurs
and
the
halt
on
error
the
EBox
clock
1is
halted.
The

the

via

address

The

SBus

assembly

This

either

The

file)

the

Parity Errors

word

instead

DMA20

the

The

halt

EBox

stored

fast

memory

fast

memory

word

clock

halts

function

1is

is
an

enabled

for

DATAO

leaves

read

out

error

the

console

processor.

EBus Parity Error
The AR parity tree

generates

odd

parity

all

and

CONO

words that are destined to be output on the EBus. All devices may
check this parity.
The DTE20 checks parity on DATAO operations,
but not on CONO. All devices may not generate odd parity for all
words

that

are

transmitted

appropriate

EBus

that

has

parity

entering
If

AR/ARX
is

the

EBox

generated

over

the

EBus.

device

The

indicate

generated.

generated

the

error

signal

been

from

the

detected,

transmitting

EBus

I/0

are

page

device,

checked

fail

for

interrupt

then

all

correct

words

parity.

occurs

and

the

monitor determines
that the bad data was received from the EBus.
The information collected for error reporting should be the same
as for other occurrences of the same APR interrupt.

Note
This

that a PDP-11 deposit to KL10 memory causes parity interrupt.
has nothing to do with the KL10 instruction being executed.

This

interrupt

monitor.
PDP-11

the

log

should

Continue

that

the

file.

all

deposit

treated

parity

traps.

failed,

and

The
the

interrupt

KL10
KL10

monitor

logs

the

KL10

tells

the

failure

GEN.

INFO.
-122-

NOTES

GEN.

INFO.

~-123-

RP20

INLINE

Refer

ROUTINES

STC

8350/8650

Disk

Inlines

Reference

Manual

(ER-91392-RM)
.
The

various

~Linked
Cl

types

RP20

inline

routines

are

listed

below.

Series

Control

Module

Tests

Interface Tests

Drive

C3
C4
C5

Basic Servo Tests
Index and Sector Tests
Gap Counter Tests

Cé6
Cc7

Basic Read/Write Tests
Padding Tests

C8
C9

ECC

Tests

Logic

Reorient

Counter,

TR Counter

Tests

Servo

Complex

CB
CC*
CD
CE
CF

Read/Write Reliability
Read/Write Margin
AM Detection Tests
Overwrite Test
Reformat FE Tracks

Servo Utilities
D8

Servo Adjustment
Incremental Seek Test
Cylinder Seek Test
Random Seek Test

D9
DA
DB
DC
DD

Pumped Resonance
Crash Stop Test

Track

Servo

Test

General Utilities
EQ
El
E2
E6

Sync Utility
Read Test
Display HA Utility
Display Memory

Memory

E8
E9
EA
EB

FE Panel Test
HDA State Analysis
Display Sense Data
TAG Utility

EC
EE

String
Manual

Scan

Switch/Dual Path
Intervention Test

Skip Handling Routines
F2*

RP20

Track

Analysis Utility

Inline Operating

Instructions

Refer to STC 8350/8650 Disk Inlines Reference Manual - Chapter 1
Enter

Parameters

Refer

to STC

Select

’

8350/8650 Disk Inlines Reference Manual

- Chapter

Run Options

Refer to STC 8350/8650 Disk»Inlines Reference Manual - Chapter 1

Displaying Errors/Messages

Refer to STC 8350/8650 Disk Inlines Reference Manual - Chapter 1
Display Message

Bytes

Refer to STC 8350/8650 Disk Inlines Reference Manual - Chapter 1

RP20

Microdiagnostic

Microdiagnostics)

Refer

STC

Procedures

- Hardcore Routines

(ER-80002-RM), Entry

(Control

8000-2 Maintenance Reference Manual
S000

*Not supported on Digital-formatted packs..

Unit
(MRM)

GEN.

INFO.
=124~
Table

Inline

Display

Summary*

PROGRAM
CONTROL

DATA
DISPLAY

DISPLAY
‘(Hex)

Description

The

The Inline (routine series,
test) is running.

routine

specified

the

switches is now loading.

Dynamic

Error

Display.

displayed as they occur,

ENTRY

routine,

Errors

Routine

Number

Routine
Number

are

Error

Number

but execution

is not stopped because of
error display run option.

Cco

DATA

the

dynamic

An invalid routine number was set in
the DATA ENTRY switches, or an incorrect

Routine
Number

The routine execution was interrupted by

a system or
Inline.
The

installed.

floppy

Inline

elective

Inline monitor

reset.

has

Restart

accepted

the

5X or

4X entry from the data entry switches

Inline

ready for

execution.

Routine

Number

Routine stopped because manual inter-

Routine

vention
message

Number

is required or the error
display 1is complete.

Normal end of routine or end of series

Routine

Normal

linked

fault

routines.

end

control

symptom

code

option

30,

generator

Number

and

overlay

complete.

Parameter

parameter

Error

required.

byte

Message

Stop.

PROGRAM

CONTROL

that

shown

option

bytes,

CONTROL

displayed
indicators.

error

was

The

proper

TIf

disk

through

Routine

indicate

Number

Error
Number

DISPLAY

used to

message

indicators.|

Message

display

Byte

7 of the
the byte

DATA

the

DCU.

Verify:

floppy

disk

the

disk

DISPLAY

not

installed,

and

through
show E1,

error

the

Inline

not properly

correct

detected

installed.

DATA

bits

DISPLAY

first

bits 4 through
DISPLAY indicate

numbers

the

control

additional
PROGRAM

needed.

the

Bits

PROGRAM CONTROL DISPLAY

indicates

byte
If

the

entry

7
a

reissue

correct

reinstall

the

N/A

the

command.

Floppy

disk

closed.
"correct
error

reader door is securely
Refer to the 8000-2 MRM if the
is installed and an FXXX

disk

occurs.

NOTES

Routine

has

display.

to
instructions
for
the Routine Listings

Refer

running
D8
in Chapter 4

in
of

the 8000-2 MRM.
2.

Routines
to

both

Refer

these
Listings

and

sets

generate
FE

routines
in

Chapter

for
the

displays

indicators.

1instructions

running
Routine

the

8000-2

MRM.

*Original

Technology

Corporation

1979

GEN.

INFO.

-125Table

Option

Control

Options*

Description

Start/Stop
Starts

Stops

(or

resumes)

execution

message

Parameter

Start

Reset

diagnostic

Control

execution
if
the
routine
the
routine
is
running or

display

entry

control

advance

error

option

stopped.
if error

progress.

message

display

control

must

selected

with

microprogram

the

functional

disk
installed
before
returning
the
subsystem to the customer.
The purpose is to reload the
fault symptom code generator into the diagnostic overlay

area.

control

option

indicate

to
no

disk

command.

the

correct
refer

the

Table

the

FXXX

error

occurs.

the

reader

and

installed

8000-2

Run

display

Technology
3

then

disk

Storage

should

completion.

installed,

DISPLAY

reload

insert

the

occurs,

DATA

selected:

CF30

recover,

*Original

CONTROL/DATA

With

PROGRAM

and

reissue

FXXX

crror

MRM.

Corporation

1979

Options*

ENTRY

Switches

(Hex)

Description

Dynamic

error

error.

Can

display.

used

Loop routine.
All
routine also run.

Dynamic

Inhibit

routine

selected.

error

Inhibit

routine
Repeats

Loop

single

Loop

single

dynamic
08

*Original

Storage

loop

—

1linking,
routine

)

the

error

error.

linking).

(inhibit

linking)

display.

only

dynamic

after

(inhibit

routine

and

(allows linking, no looping,
as
1if
no
run
options
were

Technology

to looped

routine.

Runs

Corporation

1979

BIT SIGNIFICANCE OF RUN OPTION PARAMETER:

after

Reset run options
and
error
stops
selected)
.
copyright

and

test

test.

linked
i

1linking.

routine

error

Repeat
looping

routines

display

display.

when

NOT USED

RESET RUN

LOOP

OPTIONS

ROUTINE

INHIBIT

LINKING
DYNAMIC ERROR

DISPLAY

(REPEAT TEST
AFTER ERROR)
MR-6082

GEN.

INFO.
-126-

RP20 Fault Symptom Codess

Fault
Symptom
Code
(Hex)

1000

Drive
Error Description

False Device Interface
:

Check

8650
MRM Map

FRUs
(Cards)

Control
Modules

Entry
or Par.

AQ7*

co8

IvV-3

co7

V-7

AQT*

Cc03

Iv=-20

J10

co7

Jo3

cos8

Jo4

J09
J10

1001

1002

Device Interface Check
- TAG BUS PAR CHK

Device Interface Check
- BO PAR CHK

AOT7*
Jo3

Jl0

JO3

c06

co8

1003

Device Interface Check

- TAG BUS and BO PAR CHK

AO8
Jo3

J04

co7

c08

V-2

c09/10

J09
J10

11FF

HDA Mode Parity Check

A0B+4

no format mode was

AQT7*

either multiple or

detected.

11XX

HDA Sequence Check -

(READY), or a run

status

Jo9

Iv-10

BQ2**

A0B+
AQLl**
AQ7*
)
AQ4

Iv-1

A0S

problem was

detected while
state

AQ1**

Jo4

AO4
A0S

This indicates
an initial status
problem was detected
during the seqguence
from state 0 to state

1200

AQ2**

This indicates that

Timeout Check
During Recalibrate
State 0 - Move Out

AO6
AQLl**
AQ2**

bPar.
6.84

AO4
A0S

208+

1201

Timeout Check

During Recalibrate
State 1 - Reset

DO2**

208+
AOG6

Par.

6.84

A04

A0S
AQ1**

1206

Timeout. Check

‘AQLl**

State 6 — Rezero

AQ6

During Rezero
Linear Mode

AQ2**

Par.

6.84

AQ4

A0S

A08+
PA Card**

1208

Timeout Check
During Seek

State 8 - Decelerate

AQ2**

“AQL**
AO4

Par.

6.54

A0S

206
PA Card**

*When replacing, check address module.
*x*pfter replacing, adjust servo velocity gain.

+Before replacing, check K631 (K641) for shorted coils.
#0riginal copyright © Storage Technology Corporation 1980

GEN.

INFO.

-127-

RP20

Fault

Symptom

Codes

(Cont)

Fault

8650

Symptom
Code
(Hex)

Error

120A

Timeout

Drive

FRUs
(Cards)

Description

During
State

Check

AQ2*x*
AQLl*x*

Seek
A

MRM

Control
Modules

Accelerate

Map
Entry
or Par.

Par.
6.84

AQO4

A0S
A06
PA

120C

Timeout
During
State

Check
Seek

Linear

Seek

Card**

AQ2*%*

Par.

6.84

Card**

AQLl**

Mode

AQ4
A0S
AQ6

AQo6

120E

Invalid

Timeout

During

Check

AQ6
AQ1**

Seek

State

Track

Par.
6.84

AQ2**
AQ4
AQ5
A08+

1210

Timeout

Check

During

Rezero

State

Move

Out

AQ1**

Par.

Al4
AQS

6.84

AQ6

AQ2%*

A08+4

AQT*
PA

1212

Timeout

Check

During

Rezero

State

Turn

Around

Card**

AQO6

Par.

AQ2%%*
AQl**

6.84

AQ4

A0S
A08+
PA

1216

Timeout

Check

During

Rezero

State

Move

Card*~*

AQ1l**

Par.

AQ8+

6.84

AQ6
AQ2%*

A0S
AQ7*
PA

12XX

Timeout
an

Check

Invalid

During

Control

State

Card**

AQ6

Par.

AQ7*

6.84

A08+
A0S

1301

Sector

Non Comp

(Sector
compare

within
(one

of
1310

AQ1**

JO04

This

AQ®6

J09

sector

AQ7

not

received

A08+

1index

marks

Compare)

indicates

that

was

two

IX-14

complete revolution

the

False

disk) .
Drive

Check

AQl**

Cco7

This indicates that
drive check occurred

AO4

co8

AQ5

c09/10

without
compare

AQ6
Al1G*

cli
(Cl1l2)

a sector
Or access

check.

AQ8+

IX-14

Jo7
Jo03

1400

False

Read/Write Check

AO4

Sense

Bytes

A0S

(EA
8

Message

and

Bytes

15)

*When replacing, check address
**After replacing, adjust servo

+Before

VIII-1/2

AQ7*

replacing, check K631

module.

velocity gain.
(K641) for shorted

coils.

GEN.

INFO.
-128-

RP20

Fault

Symptom

Codes

(Cont)

.8650

Fault
Symptom

Drive

Code
(Hex)

Error Description

FRUs
(Cards)

1401

Write

AQ4

I Check

MRM Map

Entry

Control
Modules

or Par.
VIII-1/2

A0S
AQ7*

1402

VIII-1/2

co1

AQ4

Transitions Check

co6

A0S

AQ07*

C05
C03
co4

1404

Control Check

1408

Delta I/W Check

AQ4

co8

A0S
DOT*

co6
Cl1

AQ4

Cco6

VIII-1l/2

(C12)

VIII-1/2

A0S

AQ7*

1410

Index Check Select

1420

Write Overrun Latch

VIII-1/2

AQ4
AQ05
AQ7*

’

AQ4

C05

AQS
AQ7*

Cc05
Cc08
Cl1
(C12)

14490

VIII-1/2

AQ4

Capable Enable Check

A0S

AQT*

1480

Multichip Check

AQ4

VIII-1/2

AQ5

AOT*

14F4

14F8

VIII-1/2

AQ4

Pad Gate Error 5
‘

AQ5

AQ7*

VIiII-1/2

AO4

Head Short Latch

AOS

’

AQ7*

14XX

Multiple Read/Write

AQ4

Checks

AQS

VIII-1/2

AQ7*

1500

Overcshoot Check
During

Rezero -

AO6

G3#

Par.

AQ2**

G5%

6.84

AQ1**

Go6+

A04

1506

Recalibrate - Track
Overshoot

1508

Check

Overshoot Check

During Seek
State 8 —~ Decelerate

G3%

Par.

AQ8+

A0S

G5%

6.84

G6#

Card**

AQL1l**

G3%

AQ4
A0S

Par.

G5#%
Go#

6.84

G3#

Par.

G5%

6.84

206
AQ2**
AQ7*

150a

Card**

Overshoot Check

AQ2**

During

AQ6

Seek

State A - Accelerate

AQS5

AQ1**

G6+

Card*«*

*When replacing, check address module.
**After replacing, adjust servo velocity gain.
+Before replacing, check K631 (K641) for shorted
See Table 6.3A in STC 8650 MRM.
*¥Cable Groups.

coils.

’

GEN.

INFO.

-129-

RP20

Fault

Symptom

Codes

(Cont)

Fault

8650

Symptom

Drive

Code

(Hex)

150cC

Error

Map

FRUs

Description

Control

(Cards)

Entry.

Modules

Overshoot Check
During
State

MRM

Seek
C

Linear

Mode

Par.

AQ6

G3¥

Par.

A04

G5#

6.84

A0S

G6¥

AQ2**

AQLl**

AQ7*
PA

150E

Overshoot
Lost

Check

Servo

Track

Following

Card**

AQ6

G3%

Par.

AQ2**

G5%

6.84

AOQ1

Go6¥

AQ4

AQS5
PA

1510

Overshoot
During

Check

Rezero

Card**

A06

G3F

Par.

AQ2**

G5%

6.84

AQL1**

Go#

AQ4
AQ5
PA

1512

Overshoot

During

Check

Rezéro

Card**

A06

G3%

Par.

AQ2*~*
AQ1**

G5%
G6#

6.84

AQ4
AO5S
PA

1516

Overshoot

During

Check

Rezero

Card**

AQ6

G3#

Par.

AQ2**

G5%

6.84

AQ1**

G6#

AQ4
AQ>5
PA

15XX

Overshoot
an

Check

Invalid

During

State

Card**

AQ6

G3%

Par.

AQ2#*%*

G5%#

6.84

AQ1**

Gé6%

AQ4

AQS
PA

160E

Servo

Off

During

Track

Error

State

AQ2*x*
AQLl**
PA

16XX

Servo

Off

during

control

Track

invalid

state

read/write
during

Error

set

active

access

motion

Card**

A06

Carg*+*

ADG6

co7

Par.

AQ7*

cusg

6.84

AO4

Cll

A0S
AC8+

(Cl12)
c09/10

AQ2*%*

G3
G5
G6

1910

Error

Alert

CJoe6,CJos

Cl1l

CJ05,CJ07

(C12)

J110,J111

Cco7

J112,J113

cos8
c09/10

J114,3115

ITI-8

J116,J117
1911

Transmit

Target

Error

AQ1*x*
AQ6

IX-17

AQ7*
A08+4

AQ4
AQ5

*When
**After

replacing,
replacing,

check

address

adjust

servo

module.
velocity

gain.

+Before replacing, check K631
(K641l)
for shorted
*Cable Groups.
See Table 6.3A in STC 8650 MRM.

coils.

GEN.

INFO.
-130-

RP20 Fault Symptom Codes

Fault

Drive

Symptom

Code

(Cont)

(Hex)

Error Description

1912

_Microprogram
Detected

FRUs

(Cards)

8650

Control

Modules

1913

or Par.

18)

Difference Counter or
HAR (head address

AQ05
A0b6

co7
c08

IV-14/16

Sync Out Timing Check

G9#

co3

V-36

1914

Entry
Par.
5.22

Error (detailed
information is in
sense byte

MRM Map

AQT7*
A08+
GO0,Gl#

Cc09/10
Cll
(C12)
Co4
C06
CcOo7
Cco8

C09/10
Cl1l
(C12)

1915

Unexpected File Status
at Initial Selection

AO7(BO7)*

AQ6

AQL1**
AQ4
A05

c07

Par.

co8

6.14

GO+

IV-10

Cl1l
(C12)
c09/10

A084
AQ2**

1916

1917

Transmit CAR (cylinder

Error

address register)

A05

bp07*

A0S

Transmit HAR Error

AQT*

Gl#

G7#
G8#
G9#

GO#*
Gl#

V-14

G7#

G8+%
G+

1918

Transmit Difference

Counter Error

A0S
A06

AQ7*

GO*

Gl#

IV-16

G7#%

G8+#

G9#

1919
191A

G3#%

Unexpected File Status

G5%

During Read IPL

G6%

AQ2**

Seek Verification

Check

cos8

AG4

Cll

AQ6

A0S
AQT*
PA Card**

1918

co7

DO1**

C06

6.136

Go6#*

;

Timeout Check i1f byte
16, bit 0 is -on (EA
message byte 9, bit 1)
Overshoot Check 1f byte
16 bit 1 is on (EA

message byte 9, bit 0)

*When replacing, check address module.

**pAfter replacing, adjust servo velocity gain.
+Before replacing, check K631 (K641) for shorted colls.
*Cable Groups.

Par.

G5%

if byte 9, bit 1 1is
on (EA message byte 5,
1)

6.5

(C12)
G3#

Sector Compare Check
bit

Par

See Table 6.3A in STC 8650 MRM.

Pari
6.9

GEN.

INFO.

-131RP20

Fault

Symptom

Codes

(Cont)

Fault

8650

Symptom

Drive

Code
(Hex)

191C

Error

Description

Interrupt

From

Drive

(Missing Device
Attention)

MRM

Map

FRUs

Control

Entry

(Cards)

Modules

AQ2*%*

Par.

IV-19

AQ6

191D

Defective Skipping
Reorientation Error

191E

Unable

Device

Format

V-47

Determine
Mode

AQ7*
A0S

co8
C04

AQ8+

Cl1

IV=-23

(C12)
C09/10

191F

Retry

Orientation

Check

GO#
Gl#

col

4940

ECC

Data

Field

Check

V-54

co7

G8#*

co4

AQ03(B03)

C05

Par.

AQ4

Cco3

6.149

AQ5

co07

AQ7*

co1

AQ6

4941

ECC

Data

Count

4942

4943

Field

ECC

Data

Key

Field

ECC

Data

4944

Check

Sync

Field

Co1

Par.

AG4

Cco03

6.149

A05
AQ7*

Co4

AQ06

Co06

See

co5

FSC

Par.

4941

Check

See

Field

A03 (B03)

6.149

FSC

Par.

4941

Byte

Found

6.149

AQ3

Cc03

Par.

A04

co4

6.148

A05

Ccol1

A06

co7

AQ7*

Co05

AQ8

4945

Sync

Count

4946

Found

Byte

Found

AQ03

Cc03

Par.

co4

6.148

AQ6

Cco1

AQ7*
AQ8+

Cco6
Co5
FSC

During

When

AQ3

reorienting

AQ4

‘Par.

C04

6.150"

failing

record

A05

opera-

tion,

mark

AQ6
AQ7¥*

c05
C0b

AQ7*

co6

G7#

Cco3
Cco4

not

Missing

retry

address

Cc01

detected.

Tag

Valid

Operation

206

G8%
GA#
Gl#
*When

6.148

co3

Read/Write

**After

Par.

4946

Found

the

Par.
6.148

AQ5

See

Field

FSC

during
was

9001

See
4944

Byte

Sync

Retry

Field

Data

4949

Found

Field

Sync

Key

4947

Byte

replacing,

check

address

adjust

servo

Cco01

module.

velocity -gain.

+Before replacing, check K631
(K641l) for shorted
$Cable Groups.
See Table 6.3A in STC 8650 MRM.

coils.

IT1-12

6;131146

INFO.
-~132~

RP20 Fault Symptom Codes {(Cont)

Fault

Drive

Symptom

Code

(Hex)

9002

FRUs

Error Description

Normal or Check End
Read/Write or ECC

MRM Map

Entry

(Cards)

‘Modules

or Par.

G7,G8%,

C06

III-25

GA,Gl#

Missing Following

8650

Control

co5

Cco3

Cco4

Operation

Co1
co7
Cc08
c09/10
Cll1
(C12)

9003

AQ7*

No Response from

G7,GB%

Control Module on a

GA,Gl#

Control Operation

Cco6

Cco03

IV-2u

Co07

Cc08
€09/10
Cll

(C12)

9004

204 (BO4)

Timeout Waiting
For Index

co6

AQS

Cco08

GO,G7%
G8,Gl#
GC,G9+

co3
C04

AOS5

c06

AQ7*
AQLl**

IX-12

Cll(Cl2)
C05

co02

Cco7

9005

ECC Hardware Check

AQ6

AQT*
AQ8+
GO,G7%

V=22

Cco4

Cc07
co8
C05

G8,Gl#*
GC,G9+#

9006

GO0,G7#

Multiple Controllers

G8,G9+

Selected

cos

Ccll

I11-2

(C12)

C07
C09/10
C04

9007

GO,G7#

Preselected Check

G8%

co4

I11-2

C07
Cco8
C09/10
Cll
(C12)
cO05

C06
C02
C03

9008 -

G0,G7%

Repetitive Command

G8+#

Overruns on Gl

Cperations

-CO06
C04

v-32

c05

C07

c08
Cl1
(C12)

9009
900A

Repetitive Command

AQT*

Physical Address Check -

AQT*

Overruns on G2 or
G3 Operations

incorrect physical

a drive

**After

#Cable

Cco7

Iv=-2

co8

selection
check

replacing,
replacing,

Groups.

V-38

Cl1l
(C12)

C09/10

address returned after

*When

Cco8

address module.

adjust servo
Table 6.3A

See

velocity gain.
1n STC 8650 MRM.

GEN.

RP20

Fault

Symptom

Codes

(Cont)

Fault

8650

Symptom
Code

Drive

MRM

(Hex)

Error

Description

FRUs
(Cards)

900B

Busy

Missing

AQ6

Seek

Start

After

Issued

Device

Interface

Failure

‘

Map

Control
Modules

Entry
or Par.

co8
Cll

VII-18

AQ7*
AQ4

(Cl2)

AOS

900E

INFO.

GO#

AQ2**

G3#

AQl**

G5%
G6#

AQS

C03

AQG

C04

AQ7*

IvV-9

co8

G0,G1l+#
G8%
900F

Attention

Check

AQ6

CO07

device

attention

AQS

co8

failed

AQ7*

c09/10

AO8+

Cll

reset

GO0,G1l+#

IV-22

(Cl1l2)

G8+#

9101

Reorient

Counter

Check

G1,G8+%

CO07

GO#

CO05

V-49

cos8
c1l1
(C12)

C04

9102

Track Counter

Gl,G8%

Check

GO#

c02,Cc07

V-56

€c05,C08

C06,C03
c04,Cl1

(C12)
9104

Write

Fail

AQ4

C06

AQS

C05

AQ7*

co8

G1,G8+%

Cll

GO#

V=20

(Cl12)
Co04

9018

Controller

Check

AQT7*
G1l,G8+%

C04
cos8

GO+

Cll

IT1I-13

(C12)
C03
Cco7

c09/10
co2

9110

Device

Check

AQ7*

co3

G1,G8+%

co8

Iv-15

GO#

9118

Device BI

P Check

Controller

and

P Check

AQT*

c03

IV-15

Gl,G8+#
GO+

co8
C07
c09/10

c1l1

(C12)

9120

Check
The

numwber

selected

9140

AQT7*
drives

less

greater

than

Parity

Check

c09/10

Iv-2

Cl1

ITI-11

Gl,G8+%

than

GO%

one.

GA,GC#

(C12)
C07
C08

c09/10
C04

*When
**After

#Cable

replacing,

check

replacing,

Groups.

address
adjust servo

See Table

6.3A

module.
velocity

STC

gain.

8650 MRM.

GEN.

INFO.
-134-

RP20

Fault

Symptom Codes

(Cont)
8650

Fault
Symptom

Drive

Code
(Hex)

FRUs"

Error

9180

Tag

Description

Bus

Parity Check

MRM

Map

(Cards)

Control
Modules

GA,GC#*

Cll

ITI-11

Entry

Par.

(Cl2)
Cco7
cos

C09/10
co4
91FF

Control
Bus

GA,GC#

Interface

Cc05

IT1I-15

C06
co4

Assembly

Failure

cos8
Cll

(Cl2)

co7

91XX

GA,GC#

Some Failures Cause
Multiple Fault
Symptom Codes

Refer

to RP20
Inline
Section

9200

False

Co4

Controller

co7

Check

co8
Cll
(Cl12)
Cco2
C05

coé

9201

ECC
This

indicates

the

not

normal completion of a
read or write operation.
9202

ECC

Hardware

1is

This

Compare

error

co3

Check

Co4

co05
Co6
coz2
Co1

9204

Status

Monitor

Cco05

Check

co7
co8

co3
co6
co4

co2
9208

Write

Data

Parity

co2
Cco3

Error

Ccou4

co7

co8
C09/10
Cll
(C12)

co05

+Cable Groups.

See Table 6.3A

in STC

8650 MRM.

IT1-17

GEN.

INFO.

-135~

RP20 Fault Symptom Codes

8650

Fault

MRM

Drive

Symptom

Code

(Cont)

FRUs

Description

(Hex)

Error

9210

GAP Counter

Check

(Cards)

Control
Modules
C05

Co3
co4
CO7

cos
c09/10
Cl1

(C12)
9220

Shift

Error

Cco3
Co4
. €01
Cco05

Ccos
C1l1l
(Cl12)
9240

Missing

Servo

Data

co1
COe6
co2
Co03

Cco5
co7

9280

VFO

Phase

Error

Co6
col
03
co4
c1l

(C12)
92XX

93XX

Some Failures Cause

Multiple Fault
Symptom Codes

Invalid

Fault

Symptom

Code

Refer

RP20

Inline

Section
co7co8
cll
(Cl1l2)

Map

" Entry

Par.

*OdNI *NID

INFORMATION COMMON TO ALL FORMATS
BIT

0
COMMAND
REJECT

PERMANENT
ERROR

INTERVENTION

BUS OUT

EQUIPMENT

REQUIRED

PARITY

RVALID

FORMAT

NOT

4
DATA

CHECK

NOT

RECORD

CYGLE

USED

NOT

ENVIRONMENTAL

P OUND

OVERRUN

FILE

NOT

USED

WRITE

OPERATION

PROTECT

INHIBIT

INCOMPLETE

NOT

-9¢T1~

By TE

BYTE 8-23

RESTART COMMAND
BYTE 1 BIT 7=0 - LAST CHANNEL COMMAND IN THE CCW
BYTE 1 BIT 7=1- OPERATION IN PROGRESS WHEN OBR WAS GENERATED
PHYSICAL DRIVE IDENTIFICATION
DRIVE

DRIVE

8 OR 0

90R1

DRIVE

-DRIVE

DRIVE

AOR2

B OR

COR 4

DOR

EOR6

FOR7

DRIVE

LOGICAL CYLINDER ADDRESS LOW
128

CYL ADD
HIGH NAT/-11

CYL ADD
HIGH NAT/-I1

CYLRER

512

256

LOGICAL TRACK

MR-6083

FORMAT 0 MESSAGE ONLY

SENSE BYTE 7 FORMAT/MESSAGE

SENSE BYTES 8-23 NOT USED

NO MESSAGE

INVALID
COMMAND

INVALID
SEQUENCE

CCWLOW
COUNT

ARGUMENT
IGUMED

ByINHIBITED
EUBITED

CHANNEL

ABORTED
BORTE

INCORRECT

MPL
rfiLE

- PERMANENT
MPL FILE

DATA

DEFECTIVE
,

ALTERNATE

SEEKCNECK

_MPL
FILE
PERMANENT

READ CMECK

COMMAND
OVERRUN

OVERRUN

TRACK

NOT

USED

MR-6084

*NID

NOT BEAby

Pttt

CHANNEL

*OdNI

k
MESSAGE
|
,

DIAG /W

~LET-

A
MESSAGE

DATA

*NJD

*0dNI

FORMAT1 DRIVE EQUIPMENT CHECK SENSE BYTE 7 FORMAT/MESSAGE

|
|

0
B

"
TRANSMIT

ERROR -

|
=

ETECTED

TRANSMIT

SYNC OUT

HIGH ERR

ERROR

5
UNEXPECTED

6
TRANSMIT

AT INITIAL

GIST
E

|
'
TRANSMIT
f

DRIVE STAT

SEEK VER

SEEK

DEFECT

| MESSAGE | OIFFERENCE |
e

2
MICRO-

NOT AS

CHECK ON

DURING RD 1PL

ADDRESS

gxpecTeD

PHYSICAL

INCOMPLETE

| OR SECTOR

| COMPARE CHECK

INTR

FROM

DRIVE

SKIPPING OR

REORIENTATION
CHECK

NOT

USED

|
TRANSMIT'

ERROR
F

| RETRY
.

REORIEN TRTION
MR-6085

-8€T1~

MESSAGE | wessace
|

;

USED

UStD

CheCK

S REG

| SEISSGEVE‘B\\%DES
CTL INTF

13-15

¥ NoT UsED.

I
MR-6086

ORMAT 3

‘MESSAGE

SENSE BYTE 7 FORMAT/MESSAGE

FORMAT 3

SENSE BYTE 7/MESSAGE NOT USED
'SELECTIVE RESET

MR-6087

*NEO

SENSE BYTE 7 FORMAT/MESSAGE

*OdNI

|’ |

DCU ERROR

-6E£1~

FORMAT 2

*NdD
5y

MESSAGE

MESSAGE
|

HA ECC

COUNT

CHECK

DATA CHECK

NoT

"M PAILURE

DATA

USED

FIELD

SENSE BYTE 7 FORMAT/MESSAGE

"KEY

DATA

HA FIELD

FIELD

DATA CHECK

FIELD
DATA CHECK

ON RETRY

NO SYNC
BYTE FOUND

A-F

COUNT FIELD

'KEY FIELD

DATA FIELD

BYTE FOUND

NO SYNC

*OdNI

DATA CHECKS UNCORRECTABLE

NO SYNC

BYTE

FOUND

| NOT USED
MR-6088

FORMAT S5

I
»
;
I MESSAGE

DATA CHECKS CORRECTABLE

FORMAT/MESSAGE

NOT
USED

DATA FIELD
CORRECTABLE

MESSAGES 4 - F NOT USED

|
MR-6089

-0v1-

FORMAT 4

FORMAT 6 - MESSAGE 0-F ARE NOT USED

*NID

MR—609O

*OdNI

|MESSAGE

USAGE AND OVE RRUN ERROR STATISTICS
-1v1-

FORMAT 6

DRIVE STATUS

BYTE19BITO0=0|

TAG BUS OR

PAD IN PROGRESS|

CNRITE

FIXED.

DE005

MOTOR AT

DHO60

LTH

DHO10

10
HDA/SEQ
CONTROL

FMT
LTH
FMT ERR/
ERROR

HDA SEQUENCE STATE L LATCH
)

11
L OAD-EW

DRIVE
START

GUARD BAND
LTH

DHO10

NON

ENABLE

DEO10

DEO010

DEO15

*N3D

PAD CMPT

DF040

DEO15

DH005

3330-1.... 10

B350 ... 01%

3330-11.... 11*
DHO005

HDA
SEQUENCE
CHECK

INHIBIT
i
RECYCLE

GEMINI*
HDA

100
oDD
STAT 7

TRACK
CROSSING

UNS%T

AlIR
SWITCH

GEMINI*
HDA

MOTOR
AT

DHO85

DENSITY

DHO010

CHECK

INDEX

DELTA /W

DAO0OS

DE025

CHECK

OVERRUN

DH005

WRITE

E 3K

“heck- | Moheck | 1CHeck
DEO010

DEO35

BUS OUT AT TIME OF ERROR WHEN SENSE BYTE

18=01,03,05, OR 06

MES%‘ESDCCODE

LOGICAL CYL ADDRESS LOW PRIOR TO SENSE BYTE 5

MESSALE CobE
|

DHG10

OHO10

TARGET
VELOGITY
"

AIR SWITCH

SPEED

~
CAPABLE

" eHEGK

3330 MODES

DF030

DP050 |

SECTOR

INDEX MARK

ATTN

OovontE

COMPARE

STATUS

7
K CMPT SK SCT

NONGOWRARE | (REF BYTE 12819)

STATUS

6
BUSY

WRITE 1

DEO30

GHECK

RD/WR

BUS OUT PAR | ACCESS CHECK

CONTROLLER

BYTe 17820
REF CC170
——
BYTE 19 BIT 0= 1

5
ACCESS HDA

BIT

BYTE

128

*8650 ONLY **¥8350 ONLY

*OdNI

SENSE BYTES 8-13

MR-6091

A AL

FORMAT 1

FORMAT 1
BIT

BYTE

SENSE BYTES 13-18

MESSAGE CODE

EXPECTED DRIVE STATUS/DATA

1.3,56.7.8,89

MESSAGE OTHER

CONTROL INTERFACE BUS IN AT TIME OF FAILURE

IF BIT 081 =11

MESSAGE
CODE A&B

LOGICAL CYL ADDR HIGH PRIOR TO

FIXED HEAD

512

D )00

LOGICAL TRACK PRIOR TO SENSE BYTE 6
256

17
|

TRACK
= HEAD

CONTROL INTERFACE TAG BUS AT THE TIME OF THE DETECTED ERROR

TME

OVER SHOOT

Heet

DF030

CHECK

VFO PHASE CK

01=MISSING SERVQ DATA
10= VFO PHASE ERR
11= MISSING READ DATA

SERVO

REZERO

SERVO

LINE AR

CONTROL

DF010

BE0S0

DFO10

DF010

OFF-TRACK
SHIET REG

CC140

NOT USED

ERR
coio

LATCH
GAP

CNTR
CHECK
CF120

LATCH

WRT DATA

PARITY
ERROR
CC140

L AT

STATUS

MONITOR
CHECK
CJ160

LATCH
ECC

HARDWARE
CHECK
CD100

CODED ERROR CONDITION

(BITS 4-7 HEX) LISTED BELOW

WAIT

LATCH
DF040
ECC

0
COMPARE
CD100

‘NI

*OdNI

R AR

THAN A&B

"NdD
*OdNI

BYTE 18, BITS 4-7

NOT USED

NO TAG

NO NORMAL

NO RESPONSE

TIME OUT

OR CHECK END '

VALID ON
RIW

OPERATION

9
REPETITIVE

BRS80S

FROM CNT
MODON

GVERRUNS
ON |CMNDN OVERRUNS|
,
G2
G1 OPERATIONS |

ONR/WOR

ECC OPERATION | CNT OPERATION

B
BUSY MISSING

PG
QR | AFTER SEEK

| DECODE ERROR

ISSUED

WAITING FOR | ECC HARDWARE
INDEX

CHECK

CTYPE.
ERROR

NO CNT
MOD

SELECTED

D
|

MULTIPLE OR

E
|

7
PRESELECTION
CHECKS

PRESELECTION

CSELECT | DISK
CONTROL | UNRESETABLE
INTERFACE
INTERRUPT
ERROR

NOTE:

! SENSE BYTES 13.14.15 ARE VALID FOR THESE MESSAGES
MR-6092

-ph1-

SENSE BYTES 19-23

BIT

BYTE
19

opéélfiéfi 85

NOT

PARITY

NOT

USED

TAG BUS

CH120

NOT

SHORT

CHECK
1 OF 8

PARITY CHECK

LATCHED

150

LATCHED

CHECK

CH120

HEAD

USED

DEVICE BUS IN

PAD

1,2 MB

GATE

LATCH

ERROR &

CONTROLLER

CURRENT (1)

DEO15

CJ150

BUS IN PARITY
CHK LATCHED

D180

DE110

)

FILE *
SELECTED

ALWAYS
ON

WRITE
CHECK

TRACK
COUNTER
CHECK GTD

REORIENT

CC170

COUNTER
QNI

LOGICAL CYLINDER ADDRESS LOW

MESSAGE A AND

BYTE O BIT 3=1

BUS OUT

PARITY

CHECK

USED

;

128

-Sh1-

FORMAT 1

BITSO& 1=11

FIXED HEAD

512

LOGICAL CYLINDER
ADDRESS HIGH

NOT
USED

22-23
*8650 ONLY

NOT
USED

LOGICAL TRACK (HEAD)
256

NOT
USED

BUS OUT

TAG

PARITY

(BO PAR)

'BUS

PARITY

FAULT SYMPTOM CODE
**8350 ONLY

MR-6093

*NED

BYTEO BIT 3«1

*OdNI

MESSAGE A AND

BYTE

’

*NJD

DCUCHECK

SENSE BYTES8-23
4

CUFFER
PARITY

ANNEL

CHECK

NSERFACE
LOGIC

REC?ASEEERS

COMPARE
ASSIST

/D
OR
MULTI-

NOT USED

8-10

CONTROL

CHECK

Nt
CHANNEL
A OR C

Nk
CHANNEL
B OR D

DATA

TRANSFER
CHECK

CHECK

LOAD 5
K

CHECK

SET TO 0

CONTROL INTERFACE (CONTENTS OF TA REGISTERS, VALID ONLY IF SENSE BYTE 7 IS 24)

CONTROL INTERFACE BUS-IN (CONTENTS OF MA REGISTER. VALID ONLY IF SENSE BYTE 7 1S 24))

CONTROL INTERFACE BUS-IN (CONTENTS OF MD REGISTER, VALID ONLY IF SENSE BYTE 7 IS 24)

CONNECT

NOT USED. SET TO 0

16-19
;

*OdNI

BIT

‘

=9p1-

FORMAT 2

CONTROL

MODULE
EeK

CONTROL

MODULE
ACTIVE
CHECK

CONTROL

BUFFER PARITY |

UNEXPECTED

TAG BUS

BUS-OUT

TRANSFER

MODULE
CHECK

MODULE

END CHECK

MODULE
CHECK

NOT USED. SET TO 0.

22-23

FAULT SYMPTOM CODE

MODULE
CHECK

NOT

USED

MR-6094

BIT 0=0

LATE ERROR

STORE
ADDRESS
BUS 0-7

BITO=0

CHECK

CLOCK

STORE

MULTIPLE
READ ERROR

STORE
ADDRESS
BUS 813

CHECK

SPECIAL
OP ERROR

A REG

8 REG

CHECK

ALU

CHECK

MPL READ

eS80

MPL
MPL

ERROR

CHECK

STORE

ECC LOGIC
ERROR

STORE
WRITE

BUS

2/3 CHECK

.
|

STORE
WRITE

(
ERROR

BUS

SYNDROME REGISTER

TC REGISTER (THIS REGISTER IS RESET IF SELECTIVE RESET OCCURRED IN RESPONSE TO DISCONNECT IN )

TG REGISTER (THIS REGISTER IS RESET IF SELECTIVE RESET OCCURRED IN RESPONSE TO DISCONNECT IN)
NOT USED.

CHECK

READY

0/1 CHECK

15-23

FAILING ADDRESS (BACK-UP ADDRESS REGISTER BUS 8-13)
BIT Om
1
EARLY ERROR

SENSE BYTE 10
BIT 0 =1

SENSE BYTE 10

FAILING ADDRESS (BACK-UP ADDRESS REGISTER BUS 0-7)

*NdD

BYTE

SENSE BYTES 8-23

SETTO 0

MR-6095

*OdNI

BIT

~-L¥1-

FORMAT 3

*NID

FORMAT 4 DATA CHECKS NOT PROVIDING DISPLACEMENT INFORMATION SENSE BYTES 8-23
7
6
5
4
3
2
1
0
BYTE
CYLINDER ADDRESS OF THE RECORD IN ERROR

8
0

128

22-23

HEAD ADDRESS OF THE RECORD IN ERROR

)

512

256

‘

RECORD NUMBER (UNRELIABLE MESSAGE 0 OR 4, ERROR HA)

(UNRELIABLE MESSAGE 1 OR 5, ERROR COUNT FIELD)

SECTOR NUMBER OF THE RECORD IN ERROR

o
-

14 21

HEAD ADDRESS OF THE RECORD IN ERROR

CYLINDER ADDRESS OF THE RECORD IN ERROR

' 4 0‘

'NOTE

*0dNI

BIT

BYTE 15=RETRY COUNT
'

NOT T USED
FAULT SYMPTOM CODE
MR-6096

~8v1-

’

BYTE

8 IT

DATA CHECKS PROVIDING DISPLACEMENT INFORMATION

CYLINDER ADDRESS OF THE RECORD IN ERROR

512

256

128

HEAD ADDRESS OF THE RECORD IN ERROR

SENSE BYTES 8-23

-6V1-

FORMATS5

" RECORD NUMBER SET TO 0 IF ERROR OCCURRED IN HA
|

*OdNI

*NID

*NJD
*OdNI

SECTOR NUMBER OF THE RECORD IN ERROR

]

NOT USED

15,16,17

IDENTIFIES THE NUMBER OF BYTES PROCESSED BY THE DCU FROM THE INITIATION OF DATA TRANSFER AND THE END OF THE DATA FIELD

18-19

ERROR DISPLACEMENT. SPECIFIES THE FIRST BYTE IN ERROR WITHIN THE DATA FIELD WITH RELATIONSHIP TO THE END OF THAT DATA FIELD

20-21

ERROR CORRECTION PATTERN (EACH BIT IN ERROR WILL BE INDICATED BY A 1)

ALWAYS 0

NOT USED
MR-6097

~0ST-

8-11

NUMBER OF BYTES READ OR SEARCHED (KEY AND DATA FIELD O’NLY)

12-13

NOT USED

14.15

SET TO ZERO

NUMBER OF DATA CHECKS SUCCESSFULLY RETRIED

16-17
18

SENSE BYTES 8-23

NUMBER OF ACCESS MOTIONS
CHANNEL

SELECT

FOR

SENSE

BYTES

20-23.

BIT 0=0

INFORMATION

APPLIES TO INTERFACES

IF BIT O=1 INFORMATION APPLIES TO INTERFACES C & D.

AND

TOTAL SEEK ERRORS RETRIED

COMMAND OVERRUNS A (C)

DATA OVERRUNS A (C)

COMMAND OVERRUNS B (D)

DATA OVERRUNS B (D)

*NJD

BITS 1-7 NOT USED

MR-6098

*OdNI

USAGE AND OVERRUN ERROR STATISTICS

=161~

FORMAT 6

SW./JMPS.
-]1=

Table
LP20

Switches

KL10(PA
MA20

and

PV/PW)

L oL o

MG10/MH10
MF20/MG20

and

J UM P

Contents

St e eeenonsosensoceooncessssssecosocnenses

Option

JUMPE LS. ettt

eseesssoesoencoesonsansaeel
R

DL S ot et eeooeeeeesesssocosnessseesnsecneeenn
nnnnesdd
(see CHECKS ADJUSTMENTS, pg. 9)

DC20F

(H3007)

DNZ2OF

(H3001)

WIS .ttt tiiii ittt eneneeeesnsenseeeennnnnn
eesod
SWitCheS.uueeeeeeeenoeeeooanoonnennnennnnn, ceeresneasd

SW./JMPS.

LP20 SWITCHES AND JUMPERS
Switches

M8586 (Rev. E) uses a switch pack in place of jumpers.
775400 (address unit 0) set switches 5, 6, 8, 9, and 10 OFF.
754

(vector unit 0)

set switch 3 OFF

775420 (address unit 1) set switches 1, 5, 6, 8, 9, and 10 OFF,

750 (vector, unit 1) set switches 1 and 3 OFF.

Jumpers

I indicates that the jumper should be installed.

R indicates that the jumper should be removed.
M8586 Control Loc:

ABCDEFO02

W1-W9 corresponds to base address 775400
(for

Jumper
Wl
W2

Adr List

775400

775420

4
5

I
I

R
I
I

7
8

W4
W5

W6
W7
w8

9
10
11

R
I,
R

R
I
R

Jumper

Vec bit

754

750

W10

Wll
W12
W13

3
4
5

I
R
I

Wl4d
W15
W16

6
7
8

I
I
I

(for unit 0) or 775420

1).

unit

W10-W16 corresponds to vector 754 (for unit 0) or 750 (for unit 1)

M8587 Data Paths

Jumper

Function

W1l

Install to enable parity

Install

for DAVFU

SW./JMPS.

KL10

MODEL(PA

OPTION
CACHE

PV)

OPTION

JUMPERS

AVAILABLE

CHANNELS

and

BITS-~SOURCE

AVAILABLE

HRZ-

MCA25

AVAILABLE

KL10-PV/PW-CPU
SERIAL

4D43D 2

NUMBER

BITS--SOURCE--4D42E1

2048--4E41M2
1024--4E41A1
512---4E41E1

256---4D41D2
128~--4p41E1

64----4E41F2
SERIAL

NUMBER

BITS--SOURCE--4D40E1l

32----4E39M2

16----4E39A1
08----4E39E1
04----4D39D2
02----4D39E1

01--~--4E39F2

MA20

JUMPERS

CONT

JUMPER

PINS(S)

EE1 AND

EF2

EE1

GROUND

EF2

NONE

NOTE:

Jumpers

MG10/MH10

are

external

ROW)

DAS33

AS*

DF10

Cc7

From

AS5*

Cc7

DL10O

DTO5

AS5*

Cc7

DX10

AS**

KAlQ

Cc7

KI10

A5*

T7
T7

c7
Al

KL10

AS5*

MX10

MX10C
.

AS5*

Use

use

backplane.

ADRACK

ROW)

From

DF10C

the

JUMPERS
REQCYC

DEV

BS5,

**Never

use

if
pin

MG1l0
B5

(RQ

the
Cyc

fastest
Slow).

memo ry

that bus;

otherwise,

SW./JUMPS.
-4~

DC20F

H3007 DISTRIBUTION PANEL

o —0 10

o—m lorr

o—0

om—
~C_® |—OFF
|—OFF
oW

o —0 2

~E— |-ON

9
o—0
08
o
o—"0 76

F
»>[—W [—OF
l-oN

07T 1

Oz0wi

DESCRIPTON:

282C,D

1000 BAUD % DUP

EIA

RS232-C (SEE BELOW)

300 BAUD FULL DUP
183A
183E, G, H| 300 BAUD FULL DUP
300 BAUD FULL DUP
183F
UD ORIGINATE ONLY
300 BAUD
113 A

w[_M |—OFF
<WH—1 —ON
= Eon

o—0 5
o—T 4
3

MODEM
iy

DONT CARE

SWITCH SETTINGS

CASES

WHEN SHIPPED

SIGNAL

MODEM

| REQ TO SEND
| SEC TRANS DATA|

BEL

S AATION |PIN NO

SWITCH

|SEC TRANSDATA|

| SEC REC'D DATA

25 | BUSY

—

|sec RecD DATA | 202

17 | RESTRAINT

SWITCH SETTINGS H3007 DISTRIBUTION PANEL
1.

LOW SPEED TWX

0118

—ON

011B

103E.G.H

’

R PIN
SHOULD BE PUT ON WHATEVE
SIGNAL FROM THE MODEMWITH
IN SPECIAL CASES, ANY GIVEN
SWITCHES 1-7. CHECK MODEM
THE H3007 DIST. PANEL
REPRESENTS THAT SIGNALEONIT WITH
THIS FIGURE.
SCHEMATIC AND COMPAR
, H7807, AND H7147 (OR M7808)
THE MODEM CONTROL MODULES
BUS INITIALIZATION OFREMOVIN
BACKPANEL WIRE FO2B2 TO GROUND.
DH11
G
BY
D
CAN BE INHIBITE
SECRX, OR CLEARTOSEND
MAY BE INHIBITED FOR CARRIER RING,
INTERRUPTS FORALL LINES LISTED
'
BELOW.
BY REMOVING THE WIRES
STATUS

DH11 WIRE REMOVED

CARRIER
RING
SEC RX

E02A1 TO DO2B1
E02C1 TO DO2F2
E02B1 TO DO2A1

CLEAR TO SEND

E02D1 TO DO2C1

SW./JUMPS.

-5-

H3001 DISTRIBUTION PANEL

+ |80
)

]

1112131415

e—

8910

= [AARR]%
SW-

|
]| [L—0

QQQT OFF(OPEN)

fi 95|
|| [E

SW-

ON (CLOSED)

|
]
O

12345

SRR

W-—

MALE

———a

~==3

<
<

N——

IO&L

/7325

an
]

62<?08

&,
L
20,
94

{<0

573
S1

CONNECTOR

S3
S4
S5

S6
S7
S8
S9
S10

S11
S12
S13

S14
St5
NOTE:

SWITCHES ARE OFF UNLESS OTHERWISE INDICATED.

*ON IF NEW SYNC CONFIGURED ON M7867
201", 208", 209" ARE TRADEMARKS OF WESTERN ELECTRIC.
MR-14266

TABLES/MAPS
-1-

Table

Contents

LP2O Bit Maps.....oooooo‘.ooooooooooooooooco-oo0000000000000000004
DTE20 Bit MapS..........................-..........--oo..........8
TOPS-10
Process

TablesS..ieeeiieeeeneeseosssscssnsscscsossncnnsnes cemens eeees20

Page

FOIMAtSeeeeesonoosescscscccosscsasansccssscsscscncsssocsnssll

MAP

Page

Map

Instruction

(AC

FOrmatsS) eeeecoeessssccssssossossscanssccocseell

Fail Word FOIMAtS.eeeesesoscescsssesasossscsssnsanscseseald

TOPS-20

Process Tables (Single SectioN) .eicecessecccesssssocscnsscnceelbd
Process Tables (Extended) ceseeessssescscecascscssssossenasasncscssll
Core Status Table.i.iiiieeeosoessssssosososcosasssoccsosssscsoccnsessll
Page Map FOrmMatSeeeeseseeeococesosceecscssoscsosassscccossoascsesesldl
Page Map Pointer FOIrMatS.sceseeeoccecsssosssencscsssesoscsscsssssell
"Section Map Pointer FOIrMAtS.eeessesssonacsasssssassssassessseseldd
MAP Instruction (AC FOrmatS) seescesconcscscecnasass O
1
Page Fail Word FOIMALS.eeeoesaccoceeoonssssssssssssasonssassssl8
PC

@and

FlagS. ceeeeoseesssssssssosssssssssassasascsssscsassascccesssidl

VM e e eeeoeeososossesssossosasseoscsassssssasnsassessassssscsscsnnsassccsasdl
APR Bit MABPSeeesssasccsacesnossssassssnsesncsacssssssssssscansssasssidl
MTR (Meter) Bit MapPSeeeteeececessssassacsasosssssasscssssncsssssesidh
PAG Bit MapPSeeseeesssesoscssns Y
<
PI Function Word FOIMAt.eeeeeososooesssascsssssossssasocssasssssncseadl

Bit
SBus

MAPSeeeooesosscosossosssssassasasossassasssssansssssesencsscseedl
Diagnostic Functions (DMA20)....ce.. cesessesesnsascsvessend

SBus
SBus

Diagnostic
Diagnostic

Functions
Functions

(MA20/MB20) ceeeevessascccasanness «eshB
(MF20).eesseecccssccaassscsassansassl?

RDERA WOrd. eveeeeeoeeosscssessenscnscns L
L
TIM (Timer) Bit MApPSeeeeeoessoeosssesascsccscossass P
. 1)

Channel Command COeS..euieeessseeesessossesossssossaccsoasacsscoses88
Channel Control Word FOIrmMAtS..eeeeeeesessesescescsscascscscsosnsasd8
RH Disk and Tape Function COdeS..eeesesccccsscsssccscsscssssssssdl
RH1I0 I/0 Bit MAPS:eseesocsscsascsacrsssssnsssssessessosnsoassonsessldd
RH11 I/0 Bit MAGPSeeceeececccosoososccscssassosssassccnsssscsossesslld
RH20 I/0 Bit MapSeeeassoes P
B 1
RHXX ~ RP04/06 Bit MApPS.eseeocessossosseososssasscsasssancessesll8B
RHXx — TM02/03 Bit MapPSessscessoccses crseesenons cessssssesassaasdl28
DXlO/DX2O

Bit

TX0x/TU7X

Sense Byte

Maps............0........ ....... 0.......‘.-...-..134

DX20 Bit MAGPSeeteeoesossssescocsesoosososncscass S
e1

FOrMatS..ieeeesessecsscssssncsoscscessssesl’b

TABLES/MAPS

NOTES

]

11
NOTE:

}

(775406)

00
I

(BYTE COUNT — TWOs COMPLEMENT
OF NUMBER OF BYTE TO XFER)

]

06
B

)

ALL BITS READ/WRITE.
MR-2015

LPBSAD — DMA Bus Address Register

14
I

13
I

12
I

11
I

10
]

09
I

(775404)

13
{

NOTE:

12
|

11
1

10
|

09
1

06
I

(ADDRESS OF NEXT BYTE

08
|

05
L

04
i

03
]

00
T

IN BUFFER)

07
)

06
{

05
4

03
1

01
L

ALL BITS READ/WRITE

MR-2014

LPCCTR — Column Count Register (High Byte)

LPCBUF — Character Buffer Register (Low Byte)
15

14
T

(775414)

06
L

NOTE:

13
T

05
N

12
T

]

09
J

(CHARACTER COLUMN)
{

01
1

06
T

00
|

05
!

06
]

05
]

04
T

03
T

]

(CHARACTER BUFFER)
|-

00
!

00
|

BITS <15:08> READ/WRITE

MR-2018

0¢d1

LPBCTR — DMA Byte Count Register

LPCKSM — Checksum Register
LPTDAT — Printer Data Register

(775416)

NOTE:

i
\

CHECKSUM

11 |

12 |

10 -

1
ol

T
1

04
DATA

1
|

1
]

1
[

i
1

ALL BITS READ ONLY
MR-2013

(775400)

PAGE | ILL

VFU

INIT

RESET

DEL

13
12

11
10
09
08

R/W

(EXT ADR)

R/W

LOGICAL “OR’ OF ALL ERRORS

INTERRUPT ENABLE

ILLEGAL CHARACTER
DAVFU READY (SET IF OPTICAL VFU)

<03:02>

MODE BITS
00 = NORMAL

<05:04>

PAGE COUNTER INCREMENTED TO ZERO
PRINTER READY AND ON LINE
DELIMITER CHAR HELD
INITIALIZE - RESET FLAGS SET DONE
RESET ERROR, SET DONE, RESET GO

PAR

R/W

(MODE)

enag | ©©
R/W

EXTENDED UNIBUS ADDRESS BITS 17 AND 16

01 = TEST MODE (INHIBIT PRINTING)
10= VFU LOAD (DMA TO VFU)
11 = RAM LOAD (DMA MODE ONLY)
PARITY ENABLE (RAM AND MEMORY)
MR-2012

0Cd'l

LPCSRA — Control and Status Register “A”

(775402)

R/W

DATA PARITY BIT (AS SENT TO PRINTER)
OPTICAL VFU (ZERO IF DAVFU)

OFF
|VFU
|PAR
|MEM
|RAM | sync | DEM
LINE | ERROR| ERROR| ERROR| ERROR| TO
TO

R/W

<10:08>

|Go
|ERROR

R/W

FORCE ERROR CONDITIONS
02
0

MEMORY PARITY ERROR

DEMAND TIME OUT

GO SET AND “ERROR" OR “DEMAND

01
0

RAM PARITY ERROR DURING DMA XFER
MASTER SYNC TIME OUT (NO SSYNC)

RMW

'PARITY ERROR AT PRINTER

NOT READY (OTHER THAN TAPE FAULT)

08
1

SET IF LA180 TYPE PRINTER

(TEST)
01

09
I

00
0

NORMAL

DEMAND TIME OUT

MSYNCTIME OUT

MEMPARITY ERROR

RAMPARITY ERROR

LPTDATAPAR ERROR

DECREMENTPAGE
COUNT
NOTUSED
MR-2016

LPPCTR — Page Count Register

’

(PAGE COUNT)

(775410)

10
j|

09
1

08
L

07
i

06
I

05
1

04
1

NOTE: - - ALL USED BITS READ/WRITE

MR-2017

0¢dl

LPCSRB — Control and Status Register “B"’

LPRAMD — RAM Data Register

)

(775412)

12
RAM

PAR

RAM

INIT

DELIM

TRAN | PAPER

07
07

06
06
——

05
05

({RAM DATA)

]

03
03

02
02

{

[

01
o1

00
1

ALL USED BITS EXCEPT 12 READ/WRITE

RAM PARITY BIT

INTERRUPT BIT — GEN ABR

DELIMITER — TAKE DATA FROM RAM

<07:00>

TRANSLATION BIT — RDAT TO PRINTER
PAPER INSTRUCTION RDAT TO DAVFU
RAM DATA — ADDRESS IS IN LPCBUF
MR-2019

0c¢d1

NOTE:

0cddLd

CONI DTE

(7xx240)

POWER

REQ

INT

FAIL

ERROR

_T011

[

RESTRICTED MODE

10 REQUESTING 11

11 REQUESTING 10

TO10

DONE | DONE

‘.

PIO

|ERROR|

ENAB |

PIA

[

INTERRUPT TO11 ERROR

P10 ENABLE

TO10

]

,
.

MR-2100

CONO DTE

34
1

(7%x200)

INT

| CREL | SREL

CLR11

INT

CLEAR | LOAD |

PIO

TO10

ENAB

TO REQUESTING 11 INTERRUPT

CLEAR TO 11 DONE AND TO 11 ERROR

CLEAR RELOAD 11

CLEAR TO 10 DONE AND TO 11 ERROR

SET RELOAD 11

LOAD Pl CHAN NUMBER INTO BITS «<33:35>

CLEAR 11 REQUESTING 10 INTERRUPT

PIO ENABLE

35
)|

oI
]

MR-2099

DATAO DTE

(7xx140)

NEGATIVE BYTE COUNT

{

0 =INTERRUPT KL10 (ONLY) AT END OF TRANSFER
1 =INTERRUPT BOTH 10 AND 11 AT END OF TRANSFER
MR-2106

0Z 4Ld

174xxx

(RD/WR)

NOTE:

KL10 DATA BITS

0Zd1Ld

DEXWD1 — Deposit or Examine Word 1

03
Il

xxx = (406 — DTE NO. 0) (446 — DTE NO. 1) (506 — DTE NO. 2) (546 — DTE NO. 3)
MR-2107

DEXWD2 — Deposit or Examine Word 2
T

]

(RD/WR)

05
L

NOTE:

08
)

KL10 DATA BITS

{

00
19

xxx=(404 — DTE NO. 0) (444 — DTE NO. 1) (504 — DTE NO. 2) (544 — DTE NO. 3)
MR-2108

DEXWD3 — Deposit or Examine Word 3
15

14
T

(RD/WR)

20
NOTE:

13
I

174xxx

12
I

]

11
T

]

10
i

09
1

08
I

07
I

06
1

03
I

02
i

01
|

00
L]

KL10 DATA BITS
I

]

xxx={402 - DTE NO. 0) (442 — DTE NO. 1) (502 — DTE NO. 2) (542 — DTE
NO. 3)
MR-2109

_0‘[_

15
17 4xxx

DIAG1 — Diagnostic Word 1

174xxx

(READ)

ERROR|

KL10

HALT

DEP

TO10

TO11

| RUN

DIAG

LOOP

XFER

10/11

z|sTop

NOTE:

03
}

| plaG

VEC INT ADR

=] cMDST

02
L

xxx =(430 — DTE NO. 0) (470 — DTE NO. 1) (530 — DTE NO. 2) (570 — DTE NO.
3)

CRAM, DRAM, FM PARERR OR FS PROBE COND

RUN

MICROCODE IN HALT LOOP

FLOP SET, CONTROLLED BY 11

<04:02>

DEPOSIT OR EXAMINE

TO10 TRANSFER

TO11 TRANSFER
DIAGNOSE 10/11 INTERFACE

VECTOR INTERRUPT ADDRESS

DIAGNOSTIC COMMAND START

MR-2118

e
[

DIAG1 — Diagnostic Word 1

14
T

13
T

174xxx

12
T

11
T

10
T

01
L

NOTE:

02
1

03
1

04
|

DIAG

DIAG | SING

KL10

| DSEND f:::

FUNC

10/11 | PULSE | DIAG | DREC

05
1

08
B

‘

00
o

DIAG

-} cMDsST

xxx=(430 — DTE NO. 0} (470 — DTE NO. 1) (530
— DTE NO. 2) (570 — DTE NO. 3)

REMOVE STATUS FROM DS LINES

DIAGNOSE 10/11 INTERFACE

SINGLE CLOCK CYCLE

03
\

KL10 DIAGNOSTIC TRANSFER MODE

SEND/RECEIVE DURING DIAGNOSTIC BUS TRANSFER

DIAG COMMAND START (DCOMST)
MR-2102

0Z4dLd

(WRITE)

DIAGNOSTIC SELECTION CODE

0Z4d1d

DIAG2 — Diagnostic Word 2

(READ)

RAM FILE MIXER

NOTE:
<15:12>

15
17 4xxx

03
]

xxx=(432—~ DTE NO.0) (472 — DTE NO. 1) (632 — DTE NO. 2) (572 DTE NO. 3)
RAM FILE MIXER ADDRESS

-Cl-

MR-2119

DIAG2 — Diagnostic Word 2
06

14
174xxx

(WRITE)

EBUS

DONE

DTE

RESET

[

NOTE: xxx = (432 — DTE NO. 0) (472 — DTE NO. 1) (532 — DTE NO. 2) (572 — DTE NO. 3) MR-2103

DIAG3 — Diagnostic Word 3

. 14

17 4xxx

SWSEL | PAR

(READ)

LEFT

15
14

| FLOP

UBUS | WRITE | UBUS

|NPR

DPE
|

NOTE:

UNIBUS PARITY INEO
|

03
EP

[

ERROR | ERROR |

)

xxx = (436 — DTE NO. 0) {476 — DTE NO. 1) (536 — DTE NO. 2) (576 — DTE NO. 3)

<13:09>

SWAP SELECT LEFT
DPS4 (N) PARITY FLOP
UNIBUS PARITY ERROR CAPTURED DATA

DATO UNIBUS PARITY ERROR

03
02
01

EVEN PARITY WRITE SET
UNIBUS RECEIVER ERROR

UNIBUS (NPR — BYTE) PARITY ERROR

_€'[_

MR-2120

DIAG3 — Diagnostic Word 3

174xxx

CLEAR|

WRITE |

PERE | EP

{(WRITE)

I NPRE | BYTE

xxx = (436 — DTE NO. 0) (476 — DTE NO. 1) (536 — DTE NO. 2) (676 — DTE NO. 3)

SHIFT CAPTURED DATA

CLEAR NPR PARITY ERROR

CLEAR UNIBUS PARITY AND RECEIVE ERROR

TO10 BYTE MODE

WRITE EVEN PARITY

|
MR-2104

0Z d1a

NOTE:

=] cLEAR | TO10

174xxx

(RD/WR)

16
|

NOTE:

12
1

1
|

{

MSD

07
]

06
1

{

0Z4ddd

DLYCNT DELAY COUNT

00
1

DELAY COUNT
|

)

LSD

XXX = (400,—, DTE NO. 0) (440 — DTE NO. 1) (500 — DTE NO. 2) (540 — DTE NO. 3)
DELAY COUNT 37777 = NO DELAY

<15:14>

UNIBUS ‘ADDRESS BITS 16 AND 17
MR-2101

STATUS

.
-9

:;g:";)

Tot0

ETi

DONE

NOTE:

~ 7| BELL | wp1 | PE

INT

BELL |

DONE | SEL

NPR UNIBUS OR — 11 MEM PE OR UNIBUS TIMEQUT
-

7011 | DEX | 11MEM|

TO10 BYTE COUNT
= 0 OR PDP-11 SET TO10 DONE

ram-ol

STOP | PE

MODE | comp

| ERROR|

xxx=1(434 — DTE NO. 0) (474 — DTE NO. 1) (534 — DTE NO. 2) {574 — DTE NO. 3)

_DURING TO10 BYTE XFER

RAMDATA =0

11 DOORBELL INT REQ BY 10

TO11 BYTE COUNT =0, XFER STOP ON MU11 CHAR OR PDP-11
SET TO11 DONE

04
03

E BUFFER SELECT

EBUS PARITY ERROR DURING TO11 BYTE OR EXAM XFER
1 = RESTRICTED MODE, 0 = PRIVILEGED MODE

DIAGNOSTIC USE ONLY

PDP-11 MEM PARITY ERROR

TO11 BYTE XFER ERROR

LAST DEP/EXAM COMPLETED

10 DOORBELL INT REQ BY 11

INTERRUPT ON
MR-2105

STATUS

174xxx

TO10

|CLEAR

(WRITE)

TERM | TERM

|TO10

12
|CLEAR|

SET11 | cLR11|

| ERROR | TO10E | BELL

CLR11 | SET10 | SET11

| BELL | PE

BELL

| CLR11 | 11INT

| pone | ponE

| REQ

04
|CcEBUS|
| PE

INT

| SET

SET

OFF

| EBPE | TO11E | TON1E

| CLEAR

xxx = (434 — DTE NO. 0) (474 — DTE NO. 1) (534 — DTE NO. 2) (574 — DTE NO. 3)

TO10 NORMAL TERMINATION

SET TO11 DONE

CLEAR TO10 NORMAL TERMINATION

SET TO10 ERROR

CLEAR TO11 DONE

CLEAR TO10 ERROR

CLEAR EBUS PARITY ERROR

SET TO11 DOORBELL

DISABLE DTE FROM GENERATING BR REQ

CLEAR TO11 DOOR BELL

SET EBUS PARITY ERROR

SET T10DB

CLEAR TO11 ERROR

13
10

CLEAR PDP-11 MEMORY PARITY ERROR

GEN PDP-11 BR REQ

SET TO11 ERROR

MR-2121

0c 4Ld

NOTE:

(RD/WR)

;

ADDRESS SPACE
Cg

NOTE:

EX
DEP

PROT

]

KL10 ADDRESS
15
16
17

15
17 4xxx

18
{

19
3

xxx={410— DTE NO. 0) (450 — DTE NO. 1) (510 — DTE NO. 2) (550 — DTE NO. 3)

<15:13>

0=EPT, 1= EXEC VIRTUAL,

2-—-3 = RES, 4 =PHYS, 5-7 = RES

0= EXAMINE 1 = DEPOSIT

1=PROTECTION AND RELOCATION
IS OFF FOR PRIVILEGED FRONT END.

0 =PROTECTION AND RELOCATION

IS ON FOR PRIVILEGED FRONT END.
MR-2110

TENAD2 — Ten Address 2
15

14
¥

13
1

12
i

11
T

10
I

09
T

08
|

174xxx

(RD/WR)

07
i

06
L

05
I

04
1

03
!

02
1

01
i

00
I

KL10 ADDRESS

21
{

NOTE:

22
I

23
]

24
]

25
1

26
1

27
|

28
]

29
L

30
]

31
1

32
i

33
1

34
-

35
1

xxx=(412—- DTE NO. 0) (452 — DTE NO. 1) {512 — DTE NO. 2) (552 — DTE NO. 3)
MR-2111

0cdlLd

TENAD1 — Ten Address 1

TO10AD — TO10 Address

)

174xxx

09
T

08
T

07
T

06
T

05.
)

BYTE ADDRESS OF SOURCE STRING (PDP-11)
L

NOTE:

xxx=(420— DTE NO. 0) (460 — DTE NO. 1) (520 — DTE NO. 2) (560 — DTE NO.
3)
MR-2115

TO10BC — TO10 Byte Count

15
INT
ERROR
NOTE:

06
I

05
I

04
1

]

NEGATIVE BYTE COUNT
;

]

_LT_

174xxx

10
1

xxx={414 — DTE NO. 0) (454 — DTE NO. 1) (514 — DTE NO. 2) (554 — DTE NO. 3)
MR-2117

TO10DT — TO10 Data

]

WORD MODE: KL10BITS <20:27>
i

NOTE:

BYTE MODE: <15:08> =0

.
1

BYTE MODE: KL10 BITS <28:35>

WORD MODE: KL10BITS <28:35>
\

]

xxx = (424 — DTE NO. 0) (464 — DTE NO. 1) (524 — DTE NO. 2) (564 — DTE NO. 3)
MR-2113

0Z dLd

%5
17 4xxx

0CdLd

TO11AD — TO11 Address

]

174xxx

10
I

09
LB

08
1

07
I

06
I

05
1

04
|

BYTE ADDRESS IN PDP-11 MEMORY — FOR STORAGE OF NEXT BYTE

NOTE:

]

xxx=(422 — DTE NO. 0) (462
— DTE NO. 1) (522 — DTE NO. 2) (562 — DTE NO. 3)

_.8'[_

MR-2114

| TO11BC — TO11 Byte Count

15
174

Xxx

NOTE:

NULL | TO1

:
-STOP ' | MODE |-

NEGATIVE BYTE COUNT
|

{

xxx=1(416— DTE NO. 0) (456 — DTE NO. 2) (516 — DTE NO. 2) (556 — DTE NO. 3}

INT BIT:

0=INT 11 NORM TERM,

:1T=INT 10 AND 11

STOP ON NULL CHAR FROM EBOX

0 =WORD MODE IN DTE
1=BYTE MODE IN DTE
MR-2116

TO11DT
— TO11 Data
1

14
I

13
L

12
T

10
1

09
i

08
1

06
1

BYTE MODE: KL10 BITS <20:27> OR <28:35>

WORD MODE: KL10 BITS <20:27>
|I

NOTE:

]

03
1

02
1

01
|

00
|

WORD MODE: KL10 BITS <28:35>
1

[

]

xxx = (426 — DTE NO. 0) (466 — DTE NO. 1) ( 526 — DTE NO. 2) (566
— DTE NO. 3)

MR-2112

0ZdLd

174xxx

05 |
I

BYTE MODE: KL10BITS <20:27> OR <28:35>

_6'[_.

TOPS-10

PROC.

TABLE
-20-

EXECUTIVE PROCESS TABLE

(ADDRESSED FROM EBR)

o]
|
I

EIGHT CHANNEL LOGOUT AREAS

EACH:

|
!

INITIAL

1
2

GETS CHANNEL
STATUS WORD
GETS LAST UPDATED COMMAND

CHANNEL COMMAND

RESERVED

37
40

RESERVED

57 |

STANDARD PRIORITY INTERRUPT INSTRUCTIONS

60 |

! FOUR CHANNEL BLOCK FILL WORDS

64 |
I

RESERVED

137
140 |

FOUR DTE20 CONTROL BLOCKS

EACH:

|
j

0 TO11BYTE POINTER

TO10BYTE POINTER

DTE INTERRUPT INSTRUCTION

RESERVED

EXAMINE PROTECT

DEPOSIT PROTECT

DEPOSIT RELOCATION

5 EXAMINE RELOCATION

'
!
|

177 |

200 | EXECUTIVE PAGE 400

: EXECUTIVE PAGE 401

[

377 [ EXECUTIVE PAGE 776

400 lr

|
I

! EXECUTIVE PAGE 777

| RESERVED

420!
421 | EXECUTIVE ARITHMETIC OVERFLOW TRAP INSTRUCTION

422 | EXECUTIVE STACK OVERFLOW TRAP INSTRUCTION

423 | EXECUTIVE TRAP 3 TRAP INSTRUCTION
424
RESERVED

507

510

TIME BASE

511
512

PERFORMANCE ANALYSIS COUNT

513

514 { INTERVAL COUNTER INTERRUPT INSTRUCTION
516

EXECUTIVE PAGE 1

‘

757 LEXECUTIVE PAGE 336

EXECUTIVE PAGE 337

760 |

' RESERVED

777 I

d—

——

RESERVED

one——b—

577 I
600 | EXECUTIVE PAGE 0

NOTE: APPLICABLE ONLY FOR MONITORS UP TO 7.01A

TOPS - 10 PROCESS TABLE
CONFIGURATION
MR-3699

TOPS-10

PROC.

-21~-

USER PROCESS TABLE

USER PAGE 1

USER PAGE 0O

en e

——

Gme

. wen

[

CEE

s Gn

ewe

(ADDRESSED FROM UBR)

400

EXECUTIVE PAGE 340

USER PAGE 777

| user Pace 776

|
377

EXECUTIVE PAGE 341

EXECUTIVE PAGE 376

420

RESERVED

USER ARITHMETIC OVERFLOW TRAP INSTRUCTION

422

USER STACK OVERFLOW TRAP INSTRUCTION

pree

417

EXECUTIVE PAGE 377

423

USER TRAP 3 TRAP INSTRUCTION

424

MUUO STORED HERE

425

MUUO OLD PCWORD

426

MUUO PROCESS CONTEXT WORD

427

RESERVED

430

KERNEL NO TRAP MUUO NEW PC WORD

431

KERNEL TRAP MUUO NEW PC WORD

432

SUPERVISOR NO TRAP MUUO NEW PC WORD =

433

SUPERVISOR TRAP MUUO NEW PC WORD *

434

CONCEALED NO TRAP MUUO NEW PC WORD

435

CONCEALED TRAP MUUOC NEW PC WORD

436

PUBLIC NO TRAP MUUO NEW PC WORD

437

PUBLIC TRAP MUUO NEW PC WORD

440

RESERVED
477

500

PAGE FAIL WORD

501

PAGE FAIL OLD PCWORD

502

PAGE FAIL NEW PC WORD

503

RESERVED

504
505

506

507
510

USER-PROCESS EXECUTION TIME

USER MEMORY REFERENCE COUNT
NOT USED

RESERVED

*NOT USED.

NOTE: APPLICABLE ONLY FOR MONITORS UP TO 7.01A

TOPS - 10 PROCESS TABLE
CONFIGURATION
MR-3698

TABLE

ACC | PUB | WRITE | SOFT

|CACHE|

ace | pus

| waite | sort | cace

00& 18

0=NO ACCESS ALLOWED

01&19

0=PRIVATE

1= ACCESS ALLOWED

[

]

1=PUBLIC

02820

28
1

___ |

* PHYSICAL PAGE NUMBER (EVEN VIRTUAL PAGE)

1
)
1
1
¥
PHYSICAL PAGE NUMBER (ODD VIRTUAL PAGE)

]

)

0=WRITE-PROTECTED

- 1=WRITABLE

- 03&21

SOFTWARE (NOT INTERPERTED BY HARDWARE)

04822

0=CACHE-LOOK BUT DO NOT LOAD
1=CACHEABLE

MR-2194

Map (TOPS-10 Only)

00
MODE |

AcC

|WRITE | SOFT |

PUB

[cAcHE|

keep [ o

18
NOTE:

]

)

]

{

I
|
]
PHYSICAL ADDRESS
1

o
L

11
g

o
L

]

12
o

[

0 = EXEC MODE

0 =NO ACCESS ALLOWED

1 =USER MODE

1 =PUBLIC

{

SOFTWARE (NOT INTERPERTED BY HARDWARE)
0 =PRIVATE

PHYSICAL ADDRESS

THIS REPRESENTS THE CONTENTS OF AC IF NO ERRORS OCCURRED.

257000

17
17

0T-SdOd4

d¥W

Page Map Entry (TOPS-10 Only)

THIS REPRESENTS THE CONTEN’TS OF AC IF NO ERRORS OCCURRED.

NOTE:
00

0 = EXEC MODE
1 = USER MODE

0=NO ACCESS ALLOWED

0 =WRITE-PROTECTED

04
06

SOFTWARE (NOT INTERPERTED BY HARDWARE)

0 =CACHE LOOK BUT DO NOT LOAD

0 =PRIVATE

1=PUBLIC

1= ACCESS ALLOWED

1=CACHEABLE

1 =WRITABLE

Map (TOPS-10 Only)

257000

MODE

)

18 |

18
NOTE:

<01:05>

]

19
)

L
1

‘

04
‘

FAILURE TYPE
:

1
I

puUB |CACHE | KEEP

1
1

]
[

]

23 ] 24

1
1

LIRS

PHYSICAL ADDRESS

28
‘

T
[

0
R

29 ] 30

1
1

B
1

PHYSICAL ADDRESS 17
L

‘l
1

A|
1

1
]

THIS REPRESENTS THE CONTENTS OF AC IF A MAP ERROR IS DETECTED.
:
REFER TO OTHER MAP WORD FOR BIT DEFINITIONS.
FAILURE TYPE

21 =PROPRIETARY ERROR
25 = PAGE TABLE PARITY ERROR

MR-3825

0T-5dO0L

)

dVYW

.—{Z_

MR-3824

MODE

18
'

19
I

ACC

03
|

‘

REF

WRT | SOFT

.
1

20
1

23
‘

21
L

27
|

25
i

26
I

0 = WRITE PROTECTED

28
T

29
J

30
L)

31
I

32
L

2
i

29
1

30
)

31
1

33
L

32
[

0= READ-ONLY REFERENCE

0 =PRIVATE

0= CACHE LOOK BUT DO NOT LOAD

34
1

’

35
’

33
| S

1 = REFERENCE INVOLVED A WRITE

1=PUBLIC

1=WRITABLE

SOFTWARE (NOT INTEfiPERTED BY HARDWARE)

;

1 = USER MODE

0= NO ACCESS ALLOWED
1 = ACCESS ALLOWED

VIRTUAL ADDRESS

24
1

KEEP

‘

| CACHE|

RE
»

PUB

0 = EXEC MODE
,

1
:

1 = CACHEABLE

A 1INDICATES A VIRTUAL ADDRESS
WAS GIVEN FOR THE REFERENCE
MR-2193

—Vz_

TIVd HOVd 0T-SdOL

Page Fail Word (TOPS-10 Only)

18
NOTE:

|
|

19
19

]

1
1

20
20

KEEP

]

VIRTUAL ADDRESS

)

]

28
28

I
1

29
29

1
]

30
30

!
1

31
31

|}
1

32
32

1
1

33
33

1
1

34
34

I
{

35
35

REFER TO OTHER PAGE FAIL WORD FOR BIT DEFINITIONS.

0 = EXEC MODE
1 = USER MODE

<01:05>

PAGE FAIL CODES

22
23

~ PROPRIETARY VIOLATION
REFILL ERROR

ADDRESS FAILURE

PAGE TABLE PARITY ERROR

ARX DATA PARITY ERROR

AR DATA PARITY ERROR

MR-3823

0T-SdOL

dD¥d

PAGE FAIL CODE

MODE

TIVd

_.gz._

TOPS-20 PROC.

TABLE
-26-

EXECUTIVE PROCESS TABLE

(ADDRESSED FROM EBR)

O | gigHT CHANNEL LOGOUT AREAS.
{

1 GETS CHANNEL STATUS WORD

2 GETS LAST UPDATED COMMAND

EACH: 0 INITIAL CHANNEL COMMAND

RESERVED

STANDARD PRIORITY INTERRUPT INSTRUCTIONS

7 |

60 |

! FOUR CHANNEL BLOCK FILL WORDS

63 |
64 |
|

|
|

RESERVED

137 |

140!
|

FOUR DTE20 CONTROL BLOCKS

EACH:

]

TO11BYTE POINTER

[

TO10BYTE POINTER

[

RESERVED

EXAMINE PROTECT

2 DTE INTERRUPT INSTRUCTION

)
|

EXAMINE RELOCATION

DEPOSIT PROTECT

DEPOSIT RELOCATION

177 |

200 |

RESERVED

{

420

421 | EXECUTIVE ARITHMETIC OVERFLOW TRAP INSTRUCTION
422 | EXECUTIVE STACK OVERFLOW TRAP INSTRUCTION

423 | EXECUTIVE TRAP 3 TRAP INSTRUCTION
424

I
|

RESERVED

|
:

507
510
TIME BASE

511
512
PERFORMANCE ANALYSIS COUNT

513

514 | INTERVAL COUNTER INTERRUPT INSTRUCTION
515 |

| RESERVED

537 |

540 : EXECUTIVE SECTIONQ

577 |
EXECUTIVE SECTION 37

600 |

RESERVED

777 |

‘

]
'

SINGLE—-SECTION TOPS-20 PROCESS

TABLE CONFIGURATION
MR-3702

TOPS-20

PROC. TABLE

-27-

USER PROCESS TABLE

———

(ADDRESSED FROM UBR)

NOTE:

ASTERISKS INDICATE
USE DIFFERS FROM

EXTENDED PROCESS
TABLE LISTED ON

LOCATIONS WHOSE

THOSE IN THE

RESERVED

GES

THE PRECEDING

mmn

PAGE.

USER ARITHMETIC OVERFLOW TRAP INSTRUCTION

422

USER STACK OVERFLOW TRAP INSTRUCTION

423

RESERVED

425

MUUO STORED HERE

426

MUUO OLD PCWORD

USER TRAP 3. TRAP INSTRUCTION

424

427

MUUO PROCESS CONTEXT WORD

430

KERNEL NO TRAP MUUQ NEW PC WORD

431

KERNEL TRAP MUUO NEW PC WORD

432

SUPERVISOR NO TRAP MUUO NEW PC WORD

433

SUPERVISOR TRAP MUUO NEW PC WORD

434

CONCEALED NO TRAP MUUO NEW PC WORD

435 |

CONCEALED TRAP MUUO NEW PC WORD

436

PUBLIC NO TRAP MUUO NEW PC WORD

437

PUBLIC TRAP MUUO NEW PC WORD
.

440

i
477

RESERVED

]

500 |

PAGE FAIL WORD

501

PAGE FAIL FLAGS

502 |

PAGE FAIL OLD PC WORD

503

PAGE FAIL NEW PC WORD

504

USER PROCESS EXECUTION TIME
505

506 | USER MEMORY REFERENCE COUNT
507
510 |

RESERVED

537 l

540 F USER SECTION 0

577 {

oo I

USER SECTION 37

RESERVED

777 4

B
:

SINGLE-SECTION TOPS-20 PROCESS

TABLE CONFIGURATION
MR-3703

TOPS-20 PROC.

TABLE
-28-

EXECUTIVE PROCESS TABLE
(ADDRESSED FROM EBR)

40
a4

INITIAL CHANNEL COMMAND

EACH:

GETS CHANNEL STATUS WORD

GETS LAST UPDATED COMMAND

RESERVED

——

I EIGHT CHANNEL LOGOUT AREAS

RESERVED

42
STANDARD PRIORITY INTERRUPT INSTRUCTIONS

60
FOUR CHANNEL BLOCK FiLL WORDS

RESERVED

WN-=O

TO11 BYTE POINTER

FOUR DTE20 CONTROL
BLOCKS
EACH:

EXAMINE PROTECT

TO10BYTE POINTER
DTE INTERRUPT INSTRUCTION

RESERVED

EXAMINE RELOCATION

DEPOSIT PROTECT
DEPOSIT RELOCATION

RESERVED

EXECUTIVE ARITHMETIC OVERFLOW TRAP INSTRUCTION

EXECUTIVE STACK OVERFLOW TRAP INSTRUCTION
EXECUTIVE TRAP 3 TRAP INSTRUCTION

RESERVED

507

510
TIME BASE

511

512
PERFORMANCE ANALYSIS COUNT

513
514

INTERVAL COUNTER INTERRUPT INSTRUCTION

515

! RESERVED
537
540

I EXECUTIVE SECTION O

577

'l EXECUTIVE SECTION 37

SR
IR

600

| RESERVED
777

EXTENDED TOPS - 20 PROCESS TABLE
CONEIGURATION

MR-3700

TOPS-20

PROC

TABLE

-29-

USER PROCESS TABLE

emwe

wee

(ADDRESSED FROM UBR)

NOTE:

LOCATIONS WHOSE

USE DIFFERS FROM
THOSE IN THE

emEn

Semms

wmmm

ASTERISKS INDICATE

RESERVED

SINGLE-SECTION

PROCESS TABLE

cume

LISTED ON THE

—

NEXT PAGE.

417
ADDRESS OF LUUO BLOCK

421

USER ARITHMETIC OVERFLOW TRAP INSTRUCTION

422

USER STACK OVERFLOW TRAP INSTRUCTION

423

USER TRAP 3 TRAP INSTRUCTION

MUUO FLAGS
MUUO OLD PC

426

E OF MUUO

| MuUO OP CODE, A

427

MUUO PROCESS CONTEXT WORD

430

KERNEL
NO TRAP MUUO NEW PC

432

SUPERVISOR NO TRAP MUUO NEW PC

424
425

433

KERNEL TRAP MUUO NEW PC

*
X

CONCEALED NO TRAP MUUO NEW PC
CONCEALED TRAP MUUO NEW PC

SUPERVISOR TRAP MUUO NEW PC

434
435

437

PUBLIC NO TRAP MUUO NEW PC

436

PUBLIC TRAP MUUO NEW PC

440

RESERVED

500

PAGE FAIL

501

PAGE FAIL FLAGS

502

PAGE FAIL OLD PC

503

PAGE FAIL NEW PC

* *

WORD

504
USER PROCESS EXECUTION TIME

505
506

USER MEMORY REFERENCE COUNT

RESERVED

USER SECTION 0

577 I

USER SECTION 37

600 !
|
777 |

RESERVED

540

537

———
—

510

EXTENDED
TOPS - 20 PROCESS TABLE
CONFIGURATION (CONT)
MR-3701

~LSY 0¢-5404L
_OE_

CST ENTRY

05
B

PAGE AGE
|

|§

]

12
T

AVAILABLE TO SOFTWARE

—

]

24
R

}

]

AVAILABLE TO SOFTWARE
|

NOTE:

]

)

]

AGE TRAP OCCURS IF BITS <00:05> EQUAL ZERO.
MR-21562

Page Map Entry (TOPS-20 Only)

;

|cacHEe

acc | puB | mop | wrt
|

acc |

pus | mop

| weT

00:18
01&19

22
|cacHe

)

14B 18

1
i

i
1

07
16

0 = REFILL REQUIRED TO DETERMINE PAGE ACCESSIBILITY
1=ACCESSIBLE
0=PRIVATE
1=PUBLIC

—

I
|

I
L

12
‘

PHYSICAL PAGE ADDRESS BITS
22
21
20
19
18

27
18

02820

1
i
A
1
PHYSICAL PAGE ADDRESS BITS
|

]

32
23

|
| -

1
i

33
24

1
1

i
)

3
25

1
.

¥
1

35
26

0=PAGE NOT MODIFIED

03& 21

1=PAGE MODIFIED
0=WRITEPROTECTED
1=WRITABLE

04& 22

0=CACHE-LOOK BUT DO NOT LOAD

1=CACHEABLE

NOTE: KEEPBITO= PAGE’WILL BE INVALIDATED ON DATAO PAGE

1 = PAGE WILL NOT BE INVALIDATED ON DATAO PAGE
MR-3828

d¥W 0Z-SdOL

KEEP

._'[g.._

KEEP

0¢-SdOd

MAP POINTER — No Access (TOPS-20 Only)
04

dVN

- POINTER TYPE

MR-3831

01
I

)§

PUB | WRITE | KEEP | CACHE

‘

0=PRIVATE

0 = WRITE PROTECTED

1= PUBLIC

1= WRITABLE

14
1

24
R

25
i

15
1

09
¥

10
1

AVAILABLE TO SOFTWARE

AVAILABLE TO SOFTWARE
{

0 PO'NT"(E)R TYPE .
|

_ZE..

MAP POINTER — Immediate (TOPS-20 Only)

26
1

16
1

27
1

28
T

17
1

18
1

06
‘

29
|

PAGE NUMBER FOR MAPPING
i

<12:177>

STORAGE MEDIUM

32
1

33
||

23
1

)

24
[

25
1

26
1

0=CACHE-LOOK BUT DO NOT LOAD
1 = CACHEABLE

NONZERO INDICATES PAGE NOT IN MEMORY
|
MR-2149

MAP POINTER — Indirect (TOPS-20 Only)
02

PAGE MAP INDEX

’

]

INDEX TO SPT LOCATION CONTAINING PAGE ADDRESS OF ANOTHER PAGE MAP
1

__1

]

}

REFER TO IMMEDIATE POINTER FOR BIT DEFINITIONS.

MR-2151
_€E_

NOTE:

SOFTWARE

AVAIL TO

KEEP | CACHE

WRITE|

PUB

MAP POINTER — Shared (TOPS-20 Only)

"O'NTfiR TYPE 0

puB

| WRITE|

00
0

|
NOTE:

KEEP | CACHE

REFER TO IMMEDIATE POINTER FOR BIT DEFINITIONS.

‘

]

{

R |

INDEX TO SPT LOCATION CONTAINING PAGE ADDRESS FOR MAPPING
4

AVAILABLE TO SOFTWARE

]

1
MR-2150

0¢-SdOL

‘POINTER TYPE

dVW

.POINTER TYPE

MR-3832

SECTION POINTER — Immediate (TOPS-20 Only)

00
0

POINTER TYPE:

PUB | WRITE | KEEP | CACHE

0 = PRIVATE

0 =WRITE-PROTECTED

1=PUBLIC

1=WRITABLE

¥
1
I
AVAILABLE TO SOFTWARE

|
’

)

23
14

)

‘

24
15

AVAILABLE TO SOFTWARE

25
16

26
.

[

06
<12:17>

‘

]

¥
.
¥
T
I
PAGE NUMBER OF PAGE MAP

STORAGE MEDIUM
1

{

]

0 = CACHE-LOOK BUT DO NOT LOAD
1 =CACHEABLE

NONZERO INDICATES PAGE MAP IS NOT IN MEMORY
MR-15041

dV¥W 0¢-Sd0dL

SECTION POINTER — No Access (TOPS-20 Only)

SECTION POINTER — Indirect (TOPS-20 Only)
00
0

POINTER TYPE

]

g
{

PUB

WRITE | KEEP

CACHE

—T1

__t

25
)

13
I

SOFTWARE

17
1

SECTION TABLE INDEX

{

10
1

AVAIL TO

{

" INDEX TO SPT LOCATION CONTAINING PAGE ADDRESS
OF ANOTHER SECTION TABLE

)

REFER TO IMMEDIATE POINTER FOR BIT DEFINITIONS,

MRA15042

_SE_

NOTE:

)

‘ 00

-0

. PO'NTE1R TYPE .

PUB | WRITE | KEEP | CACHE

AVAILABLE TO SOFTWARE

' .

)

INDEX TO SPT LOCATION CONTAINING PAGE ADDRESS OF PAGE MAP
|

NOTE:

REFER TO IMMEDIATE POINTER FOR BIT DEFINITIONS.

]

MR-15043

d¥W

0Z¢-SdOl

SECTION POINTER — Shared (TOPS-20 Only)

0Z-SdOd
dVIN
Map (TOPS-20 Only)

257000

MODE

mMop

| 04

e |

10
¥

| WRT

keep

0
|

20
¥

31
|

33
1

32
1

17
]

31
1

PHYSICAL ADDRESS

30
]

15
|

]

)

PHYSICAL ADDRESS

11
¥

34
1]

35
1

33
L

34
1

%
1

NOTE: THIS REPRESENTS
THE CONTENTS OF AC IF NO ERRORS OCCURRED.

0 = EXEC MODE
1 = USER MODE

1 = PUBLIC

0 = PAGE NOT MODIFIED

0 = CACHE-LOOK BUT DO NOT LOAD

1 = PAGE MODIFIED

1 = CACHEABLE

0= WRITEPROTECTED
1=WRITABLE

0=PRIVATE

MR-3829

...9{..

00
.

Map (TOPS-20 Only)

UNDEFINED

FAILURE TYPE

MODE

12
0

)

13
0

UNDEFINED

{

UNDEFINED

__l

{

]

{

THIS REPRESENTS THE CONTENTS OF AC IF A MAP ERROR IS DETECTED.

. 0=EXEC MODE

<01:05>

FAILURE TYPE

1 =USER MODE

<01:05>

CONT

27 = ILLEGAL ADDRESS - SECTION > 37

_LE_

36 = AR DATA PARITY ERROR

00 = AGE, NO ACCESS OR NOT-IN-MEMORY IN A REFILL

- 21 =PROPRIETARY VIOLATION
MR-3830

0Z-Sd0L

25 = PAGE TABLE PARITY ERROR

d¥W

NOTE:

0C¢-SdOd
dDVYd
00

MODE

ACC
,

MOD

;

REF

WRT

PUB

TYPE

|CACHE |

]

-19

KEEP
14

24
T

25
1

26
1

19
:

20
:

’

‘

23
:

24
|

25
1

26
1

0= EXEC MODE

0=REFILL REQUIRED TO DETERMINE PAGE ACCESSIBILITY

1 = USER MODE
‘
03

04
’

27
T

28
1

30
T

31
LK

VIRTUAL ADDRESS (PHYSICAL FOR MAP)

1 = ACCESSIBLE

1 = PAGE MODIFIED

0 = WRITE-PROTECTED
1 =WRITABLE

27
L

28
1

. 32
¥

30
0|

33
1

29
I

15
L

=
1

‘

31
1

32
|

0 =READ-ONLY REFERENCE

0 =PRIVATE

‘0 =CACHE-LOOK BUT DO NOT LOAD

33
| N

34
1

35
-

1 = REFERENCE INVOLVED A WRITE

0 = PAGE NOT MODIFIED

SECTION
i

_8€_

1 = PUBLIC

1 =CACHEABLE

A 1 INDICATES A VIRTUAL ADDRESS WAS GIVEN
FOR THE REFERENCE

MR-3826

TIVd

Page Fail Word (TOPS-20 Only)

‘Page Fail Word (TOPS-20 Only)
00

- 02

MODE

PAGE FAIL CODE
1

19
I

]

20
I

21
i

KEEP
]

22
1

23
1

26
L

27
L

28
i

30
T

31
T

32
|

33
I

34
|

35
1

VIRTUAL ADDRESS (PHYSICAL FOR MAP)

{

]

}

33
:

PAGE FAIL CODES

<01:06>

CONT

PAGE TABLE PARITY ERROR

PROPRIETARY VIOLATION

ILLEGAL ADDRESS - SECTION > 37

ADDRESS FAILURE

AR DATA PARITY ERROR

ILLEGAL INDIRECT

ARX DATA PARITY ERROR
MR-3827

dDO¥d

_6€_

1 =USER MODE

<01:05>

0¢-SdO0L

REFER TO OTHER PAGE FAIL WORD FOR BIT DEFINITIONS.

0= EXEC MODE

TIVA

NOTE:

{

24
L

od
_0 v_

PC — Progrém Counter
00
i

OVER

FLOW |

CARRY
f

FLOAT

|ovFLo|

USER

FPP | USER | o7
.

10
T

ADDR

TRAP

PUB 1| INn

|FLOAT |

|UNFLO|

14
T

DIV

CURRENT SECTION

]

19
T

20
T

21
T

19
1

22
T

23
T

20
1

21
L

FIRST PART DONE

24
T

25
T

22
{

27
T

28
T

29
T

32
T

24
1

25
1

26
1

27
L

35
T

28
|

PROGRAM COUNTER

23
1

26
T

29
1

30
3

31
1

32
1

33
1L

34
_

35
1

ADDRESS FAILURE INHIBIT
MR-2192

T
LOAD

‘AR

19
1

| USER

PUB

EXT

FETCH

PAUSE | WRITE

ARX

‘

10
|

MAP

NOT

'CACHE | CACHE

20
T

21
i

22
1

23
1

24
T

25
|

26
¥

27
I

28
1

29
1]

30
1

0
1
SECTION

31
T

32
||

33
I

34
1

._'[v...

VMA — FORMAT |

VIRTUAL ADDRESS

NOTE:

]

[

FR 105 BIT 18(1)

FR 106 BIT 19(0)

FR 104 BIT 18(1)

FR 107 BIT 23(0)

05
06

)

THISIS THE INTERMEDIATE WORD STORED BY THE MICROCODE AT LOCATION SV. VMA DURING A PAGE TABLE REFILL.
THE STATUS BITS MAY BE READ VIA DIAGNOSTIC FUNCTIONS.

02
03

FR 106 BIT 18(1)
FR 103 BIT 18(1)

FR 104
BIT 19(1)

FR 105 BIT 19(1)

08
09
11

FR 107 BIT 19(0)
FR 107 BIT 20(1) KL10 PV ONLY
FR 104 BIT 23(1)
FR 105 BIT 23(1)

MR-2196

VYRA

ddV
BLKI APR,

EXT

NON

(700000)

PAGE | ADR | STD
18

| CACHE | CHAN [ MODEL|

|PV

MSTR

14
1

CRO CODE VERSION
' NUMBER '

29
T

13
1

30
|

‘

31
T

PROCESSOR SERIAL NUMBER

osc: | MCA25

NOTE:

12
i

INST

11
T

KL10

SOHZ 1 \\sT

10
1

EXT

_Zv_

00
APRID

BITS <00:08> ARE MICROCODE OPTIONS
BITS <18:23> ARE HARDWARE OPTIONS

MICROCODE IS FOR TOPS-20 PAGING

MICROCODE VERSION SUPPORTS TRACKING

MICROCODE HANDLES EXTENDED ADDRESSES

CACHE INSTALLED

NON-STANDARD MICROCODE

CPU IS AN EXTENDED KL10

CHANNELS INSTALLED

MODEL PV TYPE PROCESSOR

MASTER OSCILLATOR (KW20 OPTION)

OPTION BIT FOR MCA25
MR-2067

CONI APR,

{700240)

SBUS

NXM

1/0

CACHE

ADR

| POWER|

SWEEP

PGF

DIR

FAIL

DONE

NXM

1/0

CACHE|]

ADR

PGF

DIR

FAIL

REQ

ERROR

|POWER ] SWEEP]

INT

SBUS

=JERROR

06
-

INTERRUPT ON:
:

SBUS ERROR
NONEXISTENT MEMORY

1/0 PAGE FAIL

MB PARITY ERROR

CACHE DIR PARITY ERROR

CACHE DIRECTORY PARITY ERROR

ADDRESS PARITY ERROR

POWER FAILURE

CACHE SWEEP DONE

INTERRUPT REQUEST

12
13

CACHE SWEEP IN PROGRESS

35
1

Pl LEVEL

SBUS ERROR
NONEXISTENT MEMORY

DONE

34
I

25
‘

1/0 PAGE FAILURE

MR-2064

dd
v

‘APR

ddv

DATALI APR,

1 1

09
1

APR

REFERENCE TYPE

]

(700040)

FETCH

WRITE
Il

MR:-2068

BLKO APR, (WRFIL)

APR

(700100)

CACHE REFILL

REFILL RAM ADDRESS

RAM DATA
1

MR-2066

_vv.—

NOTE: REFER TO DATAO APR FOR BIT DEFINITIONS’

CONO APR,
19

JOEM

APR

(700200)

1/0

|POWER

|SwEep

DIS

reser | asLe | asLe

|CUEAR|

SBUS

SET

lepror|

WTM | perF

|CACHE | ADR

PE | DIR

SELECT FLAG:

|FAIL | DONE

ENABLE

SELECTED
FLAGS <24:31>-

SELECTED FLAGS <24:31>

CLEAR

SELECTED
FLAGS <24:31>

I/O PAGE FAIL

SET

SELECTED FLAGS <24:31>

MB PARITY ERROR

DISABLE

1/0

PIA

SBUS ERROR

NON-EX-MEMORY

CACHE DIR PARITY ERROR

ADDRESS PARITY ERROR

POWER FAIL
CACHE SWEEP DONE
MR-2063

DATAO APR,

10
¥

APR

(700140)

FETCH

READ
\

)

15
¥

USER

BREAK

WRITE | SPACE
|

14
¥

REFERENCE TYPE

ADDRESS

<09:12>

’

)

ADDRESS BREAK ENABLES
MR.2065

ddv

BLKI MTR,

READ MBOX ACCOUNT DOUBLEWORD

?7[());"4?)((:);'-

MR-2091

CONI MTR,

702640

ACCOUNTING
\

NOPI

]

2 I -T
on

)

[

Pl LEVEL
[

TIME BASE ON
MR-2089

DATAI MTR;

" READ EBOX ACCOUNT DOUBLEWORD

RDEACT
(702440)

_LV..

!MR-ZOQO 7

18
702600

LOAD [

ACCT

21
PI

ACCOUNTING
)

NOPI

OFF
:

TIME BASE
i

1 CLEAR |
.

PI LEVEL
.
MR-2088

d LW

CONO MTR,

‘

PAG

(701240)

LOOK

CACHE

LOAD

KL10

PAGE | ENAB

25
T

26
T

15
|

16
i

27
T

| TRAP

24
T

17
i

0 = TOPS-10 PAGING

28
|

)

1 = TOPS-20 PAGING

29
T

30
T

31
T

32
T

EXECUTIVE BASE ADDRESS (PAGE NUMBER)

}

33
T

23
1

34
T

24
L

35
1

25
1

26
1

ENABLE PAGER AND PAGE TRAPS
MR-2145

DATAI PAG,

01
I

PAG
(701040)

02
L]

LLLn

07
I

CURRENT AC BLK
04 | 02 | 01

24
LB

25
L]

10
I

27
]

28
1

14
J

PREVIOUS AC BLK
o
.

26
i

11
J

16
1

17
|

PREVIOUS CONTEXT SECTION
13 |
415
16 L

29
¥

15
I

30
1

31
I

32
1

33
1

34
]

35
]

USER BASE ADDRESS (PAGE NUMBER)
14

15
1

16
1

17
1

18
L

19
1

20
§

21
§

22
1

23
i

24
%

25
1

26
1

MR-2147

ovd

CONI PAG,

CONO PAG,

18
(701200)
~

-1

CACH

LOOK

NOTE:

923

1 KtL10 | TRAP

LOAD f:

1 pace | enaB | 14

’

|
1

25
16

T
1

26
17

EXECUTIVE BASE ADDRESS (PAGE NUMBER)
L

T
i

T
1

35
26

REFER TO CONI PAG FOR BIT DEFINITIONS.

...67._

MR-2144

BLKO PAG, (CLRPT)

.14

PAG

(701100)

VIRTUAL ADDRESS TO CLEAR IN HARDWARE PAGE TABLE

E—

31
1

]

35
1

35
MR-2148

oYd

ovd
00

SeEL | SEL

PAG

(701 140)

pcs | upa | PAGE

TABLE

‘

Loap | CLEAR

[
-

24
T

USER

ACCT

15
|

16
1

27
'

32
T

17
'

31
T

PREVIOUS CONTEXT SECTION
1

{

USER BASE ADDRESS (PAGE NUMBER)

17
1

)

11
T

PREVIOUS AC BLK

10
T

CURRENT AC BLK

33
T

23
1

34
T

24
L

35
T

25
1

26
1

NOTE:

BIT3=0INVALIDA
ALL PAGE TABLE ENTRIES
TE
BIT3 =1 INVAL
NONKEEP
IDATE
ENTRIES ONLY
,

SELECT AC BLOCKS <06:08>

SELECT PREVIOUS CONTEXT SECTION <09:11>

CLEAR PAGE TABLE

LOAD USER BASE ADDRESS

1= DO NOT UPDATE USER ACCOUNTS

MR-2146

._0 S-..

DATAO PAG

1I0P FUNCTION WORD
01
I

<00:02>

20
1

0=EPT

}

]

24
BED

]

25
i

08
1

26
I

29
I

)

15
1

30
1

31
I

32
1

16
T

SECTION
1

ADDRESS

)

34
1

35
1

[

5 = DATAI (DEPOSIT) [QUAL = > PROTECTED]

6 =BYTE [QUAL => TO -10]

0=STANDARD (40
+ 2N) INTERRUPT

7 = STANDARD (40
+ 2n) INTERRUPT

1=STANDARD INTERRUPT (40
+ 2N)
2 = VECTOR INTERRUPT [XCT (13-35)]

PHYSICAL DEVICE NUMBER

1=EXECUTE VIRTUAL

4 =PHYSICAL

<03:05>

21
i

QUAL

)

[

05
L

FUNCTION

04
1

ADDRESS SPACE

n =DTE NUMBER
<07:10> .

0-7 = RH20

3= INCREMENT [QUAL = > DECREMENT]

10-13 = DTE20

4= DATAO (EXAMINE) [QUAL = > PROTECTED]

17 = DIA 20
MR-2195

(API WORD)

Id
BLKI PI,
01

NUMBER

:;?32%

03
T

WORD

04
T

05
T

SWEEP CHAN DATA
L

}

]

25
1

PHYSICAL

SRC WRITE |
23

15
T

REFERENCE IDENTIFICATION

00
P

26
'

27
I

28
I

29
1

]

)

]

REF MADE FOR CACHE SWEEP

SOURCE

REF MADE FOR CHANNEL XFER

WRITE

DATA

_ZS_

ADDRESS OF FIRST WORD OF TRANSFER
|N

BIT <04:06> COMBINATIONS

04
0

06 (WRITE =0)

06 (WRITE = 1)

MEMORY (RD OR RPW)

CHAN STORE STATUS

CHAN STORE DATA
EBOX STORE FROM AR
READ FROM CACHE

CACHE WRITEBACK

(PAGE REFILL OR CHAN READ)

MR-2162

CONI PI,

{700640)

18 T 19 T 20
WR EVEN PAR

ADR | DATA 1 :DIR

Pl IN PROGRESS

|
|

PROGRAM REQUEST LEVELS
05

02
30
02

T
1

PI CHANNELS ON

]

..Eg..

MR-2155

DATAI PI,

(700440)

PHYSICAL ADDRESS OF LAST PC STORED IN BUFFER

NOTE:

]

TRACKS ONLY
MR-2157

Id
BLKO PI, (SBus Diagnostic Function Code 00) DMA
00

01
{

SBDIAG 00

02
I

(700500)

CONTROLLE

03
)

ESS.

CLEAR

ERROR

BUS

" MODE

LOAD

32
¥

33
I

34
i

35
I

FUNCTION CODE

0
1

NOTE:

0
]

THIS BIT MAP APPLIES TO DMA20S ONLY.

<00:04>

0
|

CONTROLLER ADDRESS

04=DMA20

CLEAR ERROR-CLEARS CONTROLLER’S ERROR
FLAGS NXM, RD PE, WR PE AND ADR PE

<06:07>

BUS MODE

0 = OFF LINE
1 =1 BUS MODE

- 2=2BUS MODE
,
12

3 =4 BUS MODE
LOAD ENABLE- ENABLES LOADING OF BITS 6—7.

0= READ ONLY

1= LOAD AND READ BACK
MR-3814

02
SBDIAGO0

‘NXM

(E+1)

18
NOTE:

<06:07>
‘

T
1

19
19

T
i

T
T
PARITY ERRORS

READ

20
20

T
L

21
21

WRITE

T
1

22
22

ADR

T
1

23
23

T
BUS

MODE

RQO

T
1

—1

T
T
LAST REQUEST

RQ1

RQ2

29
29

WRITE|

T
<LAST TYPE>

RQ3 | READ

ADDRESS OR FIRST ADDRESS OF ERROR

]

33
33

15
T

[

34
34

{

}

35
35

E+11S THE WORD RETURNED FROM MEMORY AS A RESULT OF BLKO PI, (FUNCT 00). THIS BIT MAP APPLIES TO DMA20S ONLY.

BUS MODE

0 = OFF LINE

1=1BUS MODE

2 = 2 BUS MODE

3= 4 BUS MODE
MR-3815

_gg_

Id
BLKO PI, (SBus Diagnostic Function Code 01) DMA

CONTROLLER ADDRESS

(700500)

12
_99_

00
SBDIAGO1

BACK

FUNCTION CODE

0
{

NOTE:

<00:04>

0
L

0
1

1
}

THIS BIT MAP APPLIES TO DMA20S ONLY.

REFER TO SBDIAG FUNCTION 00

SET LOOP-AROUND MODE-INHIBITS READ/WRITE
CURRENTS IN STORAGE MODULES. A DIAGNOSTIC

FEATURE FOR CHECKING DATA PATH INDEPENDENT
OF CORE ACTIVITY
MR-3816

02
Bl

(E+1)

NOTE:

]

{

03
I

STORAGE MODULES INSTALLED
02

06
06

LOOP

CONTROLLER TYPE
.

BACK

E+11S THE WORD RETURNED FROM MEMORY AS A RESULT OF BLKO PI (FUNCT 01). THIS BIT MAP APPLIES TO DMA20S ONLY.

<00:07>

DMA ALWAYS RETURNS 0.

<08:11>

MEMORY ID-THESE HARDWIRED BITS IDENTIFY

MEMORY TYPE.

LOOP-AROUND MODE — INDICATES CONTROLLER IN

LOOP-AROUND MODE.

00 = CUSTOMER UNIT

01 = MA20
02 = DMA20

03
= MB20
05 = MF20 MOS

MR-3817

00
SBDIAGO1

BLKO PI, (SBus Diagnostic Function Code 00) MA/MB
00

SBDIAG 00

03
I

]

07
I

CLEAR
ERROR

CONTROLLER ADDRESS

(700500)

]

10
|

INTERLEAVE
[

RQ3

LOAD
6—11

SBUS REQ ENABLES
ROO
RQ2
1

32
1

33
1

34
I

35
i

FUNCTION CODE

<00:04>

THISBIT MAP APPLIESTO MAZO AND MB20 MEMORIES ONLY.
CONTROLLER ADDRESS-EACH MA20 CONTROLLER HAS

<08:11>

A HARDWIRED ADDRESS 0-3. MCO AND MC1 CONNECT

STATUS
00 = CONTROLLER OFF-LINE

00 = MCO

FIRST 128K (MA20) OR

05 =CONTROLLER ODD (2 WAY AND 4 WAY INTERLEAVE

01 =MC1

FIRST 256K (MB20)

03 =MC3

MODES)

12 = CONTROLLER EVEN (2 AND 4WAY INTERLEAVE

SECOND 256K (MB20)

MODES)

04 = DMA20 (NOT AN MA20 OR MB20 ADDRESS)

17 = CONTROLLER ODD AND EVEN ( NO INTERLEAVE
MODES)

CLEAR ERROR-CLEARS CONTROLLER'S INTERNAL

ERROR FLAGS INCOMPLETE REQUEST AND ADR PAR
ERR.

<06:07>

SET REQUEST ENABLES-ASSIGNS CONTROLLER ODD-EVEN

TO SBUS 0; MC2 AND MC3 TO SBUS 1

02 =MC2 SECOND 128K (MA20) OR

INTERLEAVE

_8g_.

NOTE:

12
:

LOAD ENABLE-ENABLES LOADING OF BITS 6—11.
0= READ ONLY

1=LOAD AND READ BACK

0 = OFF-LINE FOR DMA20 (NOT AN MA20 OR MB20
OPERATING MODE)

‘

1=NO INTERLEAVE

2 = TWO WAY INTERLEAVING

3= FOUR WAY INTERLEAVING
MR-2158

07
i

SBDIAGOO

INC

ADR

INTER

(E+1)

{

cycLe

LEAVE
1

E+11S THE WORD RETURNED FROM MEMORY AS A RESULT OF BLKO P1, (FUNCT 00). THIS BIT MAP APPLIES TO MA20 AND MB20 MEMORIES ONLY.

ADDRESS PARITY ERROR-INDICATES BAD PARITY

FOR 10.2 MICROSECONDS: HUNG CONTROLLER.

<06:07>

INTERLEAVE MODE-INDICATES INTERLEAVE MODE
LOADED IN FIRST HALF OF FUNCTION 0.

DETECTED FOR INFORMATION ON SBUS ADR, R Qn,
RD RQ, AND WR RQ LINES.

MR-2159

lNCOMPLETE_ REQUEST-INDICATES CONTROLLE R ACTIVE

_6g_

NOTE:
02

BLKO PI, (SBus Diagnostic Function Code 01) MA/MB

SBDIAGO1

CONTROLLER ADDRE

(700500)

LOOP

HIGH ADR BOUNDRY
|

26
LOAD

14-25

27
,

)

SELECT MARGINS
L

FUNCTION CODE
L

{

17
17

)

T
T
SBUS ADDRESS
.
16
15

BACK

REFER TO SBDIAG FUNCTION 00

[

LOAD ENABLE — ENABLE LOADING BITS <14:25>

0=READ ONLY

SET LOOP-AROUND MODE-INHIBITS READ/WRITE

<22:25>

THIS BIT MAP APPLIES TO MA20 AND MB20 MEMORIES ONLY.

NOTE:

<18:21>

LOW ADR BOUNDRY

<00:04>

<14:17>

CURRENTS IN STORAGE MODULES. A DIAGNOSTIC

FEATURE FOR CHECKING DATA PATH INDEPENDENT
OF CORE ACTIVITY
SET MEMORY ADDRESS-CORRESPOND TO SBUS ADR
14—17. MUST MATCH THE SBUS ADDRESS LINES IF A
CONTROLLER IS TO RESPOND TO A MEMORY

<27:35>

1=LOAD AND READ BACK

SET MARGIN CONTROL-TURN ON MARGIN CONTROL AS
SPECIFIED BELOW. ONLY ONE MARGIN SHOULD BE
TURNED ON AT ANY ONE TIME
‘
27 28 29 30

REFERENCE

SBUS ADR 18-21. ACT IN CONJUNCTION WITH
MEMORY ADDRESS (BITS 14—17) TO SPECIFY LOWER
ADDRESS LIMIT
SET UPPER ADDRESS BOUNDARY-CORRESPOND TO

o
o

SET LOWER ADDRESS BOUNDARY-CORRESPOND TO

SBUS ADR 18—21. ACT IN CONJUNCTION WITH
MEMORY ADDRESS (BITS 14—17) TO SPECIFY UPPER

1
0

X
X

NO OP

CLEAR ALL MARGINS
CURRENT MARGIN
STROBEMARGIN
THRESHOLD MARGIN
X =0~ LOW MARGIN

X =1 —- HIGH MARGIN

ADDRESS LIMIT
MR-2160

05
I

SBDIAGO1

06
T

(E+1)

NOTE:

<04:07>

20
]

19
1

20
{

BACK

16
i

{

17
T

SBUS ADDRESS

MARG

15
¥

LOOP

17
L

34
|

35
T

REQUESTS ENABLED

RQ0

]

RQ1
L

RQ2
1

RQ3
1

E+11S THE WORD RETURNED FROM MEMORY AS A RESULT OF BLKO Pl (FUNCT 01). THIS BIT MAP APPLIES TO MA20 AND MB20 MEMORIES
ONLY.

STORAGE MODULES CONNECTED — THESE HARDWIRED
BITS INDICATE THE NUMBER OF STORAGE MODULES

CONNECTED TO A CONTROLLER.

LOOP-AROUND MODE — INDICATES CONTROLLER IN

<14:25>

ADDRESS BOUNDARIES — INDICATES ADDRESS BOUNDARIES

LOOP-AROUND MODE.

1=SM CONNECTED

0 = SM NOT CONNECTED
<08:11>

)

HIGH ADR BOUNDRY

| —

11
I

CONTROLLER TYPE

10
i

MEMORY ID — THESE HARDWIRED BITS IDENTIFY
MEMORY TYPE,

LOCATED IN FIRST HALF OF FUNCTION 1.

MARGINS SELECTED — INDICATES THAT CURRENT,
STROBE, OR THRESHOLD MARGIN CONTROL IS ON.

00 = CUSTOMER UNIT
01 = MA20

02 = DMA20
03 =MB20

MR-2161

LOW ADR BOUNDRY

09
1

STORAGE MODULES INSTALLED

(700500)

'
CONTROLLER NUMBER

MF/MG20

CLEAR [
ERROR

FUNCTION CODE

0
1

0
i

0
Il

_89—

SBDIAGO0O

BLKO Pl (SBus Diagnostic Function Code 00)

CLEAR ERRORS
— REFER TO FUNCT O

(E+1) BITS <00:05>
MR-2163

INC

ERROR|

18
’L

20
|

PARITY ERROR

CYCLE | READ

19
I

21
LI

WRITE

22
1

ADR

LEAVE

24
T

25
1

RQ1

RQ2

19
]

NOTE:
00

20
]

21
|

22
|

23
i

24
|

25
|

28
T

30
i

WRITE

31
I

15
I

32
I

16
1

XBUS
1

33
|

17
¥

34
1

’L

35
i

;

28
1

READ

29
T

13
I

RQ3

ADDRESS AT ERROR TIME

LAST WORD REQUEST

RQO

23
I

{

INTER

29
|

30
]

31
f

32
1

33
|

34
]

35
|

E+1 1S THE WORD RETURNED FROM MEMORY AS A RESULT OF BLKO PI, (FUNCT 00). THIS BIT MAP APPLIES TO MF20/MG20 MEMORIES ONLY

CONTROLLER ERROR —'REFER TO FUNCT 2 (E+1)
BITS <28:30>

CORRECTABLE READ PARITY ERROR

iNCOMPLETE MEMORY CYCLE
MR-2164

(E+1)

CONT: | CORR

-£9-

SBDIAGO0O

Id
BLKO Pl (SBus Diagnostic Function Code 01)
00

01
I

SBDIAG
(700500)

02
i

03
1

MF/MG20

13
T

CONTROLLER NUMBEP

)

LOOPBACK
ENAB

GN2

GN1

ABLE
NOTE:

SF2

SF1

LD EN

25-27

FUNCTION CODE
1

)

_vg_

25
DIS

THIS BIT MAP APPLIES TO MF20/MG20 MEMORIES ONLY. BITS <26:27> ARE SOFTWARE FLAGS. THEY DO NOT AFFECT
THE HARDWARE, NOR DOES THE HARDWARE AFFECT THEM.

ENABLE LOOPBACK

<26:27>

00 = MF20/MG20 JUST POWER UP

<13:14>

GROUP NUMBER TO LOOPBACK

01 = ALL RAMS EXCEPT ADDRESS RESPONSE RAM LOADED

DISABLE MF20/MG20 (PLACE OFF-LINE)

10 = ALL RAMS LOADED

11 = ALL RAMS LOADED AND TGHA HAS BEEN RUN
MR-2165

(E+1)

1
L

25
DIS
|

ABLE

0
|

SF2

SF1

"GNO

13
I

14
T

GN1
1

GN2
1

THIS BIT MAP APPLIES TO MF20/MG20 MEMORIES ONLY. E+1 IS THE WORD RETURNED FROM
MEMORY AS A RESULT OF
BLKO PI, (FUNCT 01).

<08:11>

CONTROLLER TYPE (5 = MF/MG20)

<12:14>

LOOPBACK GROUP SELECTED

<25:27>

REFER TO FUNCT 01 (E) BITS <25:27>
MR-2166

10
I

CONTROLLER TYPE

_99_

09
|

SBDIAGO1

Id
BLKO Pl (SBus Diagnostic Function Code 02) MF/MG20
00

SBDIAGO02

GN1
)

26
T

FLD2
1

FLD1

FUNCTION CODE
L

32
T

DIAG MIXER INPUT SELECT
|

PROM SELECT

CONTROLLER NUMBER

(700500)

11
I

<23:27>

WHEN ALL ZEROS, THIS FIELD INDICATES THAT THE

CONTENTS OF BITS <07:14> DURING THE SECOND HALF
~ OF THE DIAGNOSTIC CYCLE WILL BE PROM DATA.

)

<23:27>

WHEN NOT ALL ZEROS, THE BITS ARE USED TO SELECT

WHICH MF20 CONTROL SIGNALS WILL APPEAR IN

<07:14> DURING THE SECOND HALF OF THE DIAGNOSTIC
CYCLE (DIAGNOSTIC DATA).
MR-2167

(E+1)

08
B

D00

]

DO1
1

D02

D03

01
L

NOTE:

02
1

03
1

04
1

13
T

D04

D05

D06

[

14
|

DO7
1

" (RAM ERROR TYPE)

05
1

12
I

MOS ADDRESS (SINGLE STEP ONLY)

11
T

SELECTED DIAG DATA OR PROM DATA

06
1

TIME

SuB
]

ADR
]

THIS BIT MAP APPLIES TO MFZO/MGZO MEMORIES ONLY. E+1 1S THE WORD RETURNED FROM MEMORY AS A RESULT OF
BLKO PI, (FUNCT 02).

<05:06>
<07:14>

SPECIFY WHICH WORD IN QUAD WORD GROUP

CAUSED ERROR

REFER TO FUNCT 02 (E) BITS <23:27>

RAM TIMING ERROR

RAM SUBSTITUTION BIT ERROR
-

RAM ADDRESS RESPONSE ERROR
MR-2168

06
LB

1 ERR WORD NO

_Lg_

05
.

SBDIAGO02

Id
BLKO PI (SBus Diagnostic Function Code 03) MF/MG20
01
I

02 .
1

[

BUS

)

ACKN
27

24
LB

11
|

- CONTROLLER NUMBER

(700500)

08
FAST

D VAL

]

LD EN

RDA34 RDA35| 10
1

01
1

NOTE:

02
I

03
1

04
q

05
1

FIXED VALUE LOGIC RAM LOAD ADDRESS

11-13

FUNCTION CODE

THE FAST-BUS (BIT 08) IS DISCONNECTED INTERNALLY. IT IS LEFT IN ONLY FOR DIAGNOSTIC COMPATABILITY.
THE ACKN RAM (BIT 10} USES ADDRESS BITS <21:27> ONLY.

P ACKN EN BIT

<10:13>

LOAD OR ACCESS FIXED VALUE RAMS

SET DATA VALID BIT

<12:13>

P RD ADR 3435 BITS
MR-2169

..89_

00
SBDIAGO3

(E+1)

BUS

] ACKN

DVAL

RDA34

RDA3S |:
:

E+1 1S THE WORD RETURNED FROM MEMORY AS A RESULT OF BLKO PI, (FUNCT 03). REFER TO FUNCT 03 (E)
FOR BIT DEFINITIONS.

MR-2170

NOTE:

FIXED VALUE RAMS

_69_

FAST

08
SBDIAGO3

I1d
BLKO PI, (SBus Diagnostic Function Code 04) MF/MG20

(700500)

02
T

19
|

20
1

C.ONTROLLER NUMBER

,-L

03
T

09
00

i
22
24—-30

10
T

ACOM
26

BCOM

03
1

15
Y

DVAL

)

29
Li

05
1

’L

[

- SINGLE STEP CLOCK CONTROL

i
1
REFRESH INTERVAL
1

NOTE:

LPBK

ENAB | LD EN

R NOW | REF

06
5

PORT

|
31

06
1

32
i

07
|

SSCLK SSMOD

0
i

I
I
FUNCTION CODE

35
¥

IF5 =1 THE CONTROLLER WILL ONLY ECHO INFORMATION SENT OUT BY AN SBUS DIAG AS LONG AS THE PROPER CONTROLLER
NUMBER IS GIVEN. ONLY A SBUS RESET CAN CLEAR THIS CONDITION.

PORT LOOPBACK
_

SIM A PHASE COMING

REFRESH NOW

SIM B PHASE COMING

ENABLE REFRESH

PDATAVALIDIN

MR-2171

-0L-

01
1

00
SBDIAGO4

12
T

SBDIAGO4

13
1

]

SINGLE STEP CLOCK CONTROL ECHO

(E+1)

ACOM

BCOM
]

{

]

REFRESH INTERVAL COUNTER

- 06

E+1 1S THE WORD RETURNED FROM MEMORY AS A RESULT OF A BLKO Pi, (FUNCT 04), REFER TO FUNCT 4 (E)

FOR BIT DEFINITIONS.

‘
MR-2172

NOTE:

Id
BLKO PI, (SBus Diagnostic Function Code 05) MF/MG20
0’5

01
I

BDIAG

(700500)
'

02
T

CONTROLLER NUMBER
1

08
I

21
14

09
1

STA

STB

[

RQO

[

26
|

RQ1

15
L

DIAGNOSTIC START A

DIAGNOSTIC STARTB

RQ2

RQ3

)

LD EN

RDRQ WRRQ[:

]

20
1

SINGLE STEP REQ SIMULATED ADDRESS BITS
:

10
|

SINGLE STEP SIMULATED REQUEST BITS

21
L

<29:30>

35
|

33
i

SS QUADWORD

FUNCTION CODE

1
L

SELECTS QUADWORD FOR DIAGNOSTIC SINGLE
STEP OPERATION
MR-2173

_Z L_

00
s

SBDIAGO05

(E+1)

SS MOS RAS
01

_EL_.

E+11S THE WORD RETURNED FROM MEMORY AS A RESULT OF BLKO PI, (FUNCT 05).
ROW ADDRESS STROBE (RAS) BITS

MR-2174

NOTE:
<24:27>

BLKO PI, (SBus Diagnostic Function Code 06) MF/MG20
00

SBDIAGO6

03
T

CONTROLLER NUMBER

(700500)
1

32
\

08
1

16
|

09
|

10
1

1
e

12
T

13
T

{

MISC

LD EN

DIAGNOSTIC DATA TO SY OR WP BOARD

MIsC | 07-14
1

ECC DIAG SUBFCN
04

02
1

<07:14>

AN 8-BIT FIELD USED TO SET UP THE DIAGNOSTIC DATA

USED TO CONTROL SYN2M TO CHK ECC 32,16, 8, 4,2, 1,

PAR TO BE USED AS SPECIFIED BY THE DIAGNOSTIC

FUNCTION CODE

0
1

<25:27>
=3

1
L

1
|

0
n

CONT

NOT USED

SUBFUNCTION SPECIFIED IN <25:27>

<25:27>

SPECIFIES ONE OF EIGHT SUBFUNCTIONS PERFORMED BY A
DIAGNOSTIC FUNCTION CODE 6.
o

READ IT BACK.
=5

READ THE ECC REGISTER ON WRP7.

WRITE THE ECC COMPLEMENT REGISTER, THEN ENABLE IT

TO BE SENT TO MEMORY IN PLACE OF <36:42> ON THE NEXT
"WRITE CYCLE.

- READ THE SYNDROME BUFFER REGISTER ON THE SYN

WRITE THE ECC COMPLEMENT REGISTER IF 156 =1, THEN

BOARD.

READ THE OUTPUT OF THE <36:42> MIXER.

SELECT DIAGNOSTIC BITS <07:13> IN PLACE OF MOS BITS

ENABLE LATCHING OF <36:42> MIXER AFTER NEXT WRITE.

<36:42>, FORCE 0S ON <00:35>, RUN A CORRECTION PASS,
AND RETURN <00:35>,
MR-2175

SBDIAGO06

10
|

11
T

12
I

13
T

14
1

DIAGNOSTIC DATA FROM SY OR WP BOARD

(E+1)

16
1

25
1

08
L

26
1

04
1

02
1

o1
|

MisC
1

SS MOS CAS

01
i

<07:14>

03
|

E+11S THE WORD RETURNED FROM MEMORY AS A RESULT OF BLKO PI, (FUNCT 08).

REFER TO FUNCT 06 E <07:14>

<24:27>

‘A 4-BIT FIELD THAT DISPLAYS THE STATE OF THE COLUMN

ADDRESS STROBE (CAS) SIGNALS ADT5 MOS CAS 0-3.
MR-2176

NOTE:

02
1

Id
BLKO Pl (SBus Diagnostic Function Code 07) MF/MG20

00
SBDIAGO7

(700500)

CONTROLLER NUMBER

00000

)

21
o

GN2

|
i

08
16

BIT SUBSTITUTION RAM LOAD ADDRESS

GN1

BN2

)

BN1

BIT SUBSTITUTION RAM DATA (BIT NUMBERS)

L
T

ICE

LD EN

PAR | 07-14

FUNCTION CODE
\

{

1
1

NOTE: “ICE” MEANS IGNORE CORRECTABLE ERROR (I.E., DON'T-SET CORR ERR FLAG).
'

' MR-2177

ICE

PAR

SBDIAGO7

BIT SUBSTITUTION RAM DATA ECHO

(E+1)

08
L.

25
T

26
T

04
1

02
[

SS MOS WRITE ENABLE

E+1 IS THE WORD RETURNED FROM MEMORY AS A RESULT OF BLKO PI, (FUNCT 07).
“ICE” MEANS IGNORE CORRECTABLE ERROR

(1.E., DON'T SET CORR ERR FLAG).

MR-2178

NOTE:

_LL_

Id
BLKO PI, (SBus Diagnostic Function Code 10) MF/MG20

SBDIAG10

CONTROLLER NUMBER

{(700500)

06
o
:

+12v

VOLTAGE MARGINS
|

45V

]

-2V

5.2V

+12V

MARGIN ENABLES

—l

+BV

-2V

]

LD EN |

5.2v|

07-14 |

|CLEAR [

ECC

|DCBAD

FUNCTION CODE

[

NOTE:
07
08

]

32
INH

MORE THAN ONE VOLTAGE MARGIN MAY BE SET CONCURRENTLY.
0=11.40,1=12.60
0=475,1=56.25

09
10

0=-1.90,1=2.10

0=-494,1-5.46
MR-2179

_8L.—

09
1

10
I

(E+1)

+12V

+5V
]

-2v
}

NOTE:

<07:10>

13
1

[ +12v

+5V
o

12
T

ACTIVE MARGIN ENABLES

INH | DC
ECC

-52V

-2V
]

52V
]

ERROR{::

E+1 1S THE WORD RETURNED FROM MEMORY AS A RESULT OF BLKO PI, (FUNCT 10).

REFER TO FUNCT 10 (E) FOR MARGINS
MR-2180

08
|

ACTIVE VOLTAGE MARGINS

_6L_

07
SBDIAG10

Id
BLKO PI (SBus Diagnostic Function Code 11) MF/MG20
00

SBDIAG11

CON

(700500)

]

v-'L»
I

ONTROLL

]

)}

ER NUMBER

| LDEN
21-27

RAS

24
1

CAS

25
T

TIMING RAM DATA

RAMP

WREN

2NDA

26
I

27
1

DRDY

BCLR

[

ROW ADDRESS STROBE

ADDRESS 2ND HALF

COLUMN ADDRESS STROBE

DATA READY

RAM PARITY

RAM BUSY CLEAR

WRITE ENABLE

32
1

TIMING RAM ADDRESS

FUNCTION CODE
L

,-l.,

04 T
35

)

MR-2181

SBDIAG11

(E+1)

22
1

] RAS

23
i

CAS

RAMP WREN

2NDA

]

NOTE:

TIMING RAM DATA ECHO

DRDY
|

B CLR

DESEL

ENAB | CYCEN [

E+1 1S THE WORD RETURNED FROM MEMORY AS A RESULT OF BLKO PI, (FUNCT 11).
REFER TO FUNCT 11 (E) BITS <21:27>

SPECIFY MOS CHIP SIZE

DESELECT CYCLE ENABLE

‘
MR-2182

<21:27>

Id
BLKO PI, (SBus Diagnostic Function Code 12)

00
SBDIAG12
(700500)

CONfROILLER NUMBER
20
14

]

ADDRESS RESPONSE RAM LOAD ADDRESS

)

ADDRESS RESPONSE RAM DATA

PAR

TYPE

)

GN2

GN1

)

BN2

13
BN1

LDEN [

DESEL | 08—14 [

ROt

FUNCTION CODE
I

31
0

{

1=BOX DESELECTEDON A 1
MR-2183

&
N

13
T

ADDRESS RESPONSE RAM ECHO

SBDIAG12

PAR

(E+1)

TYPE

GN2

GN1
|

)

BN2

BN1

DESEL

—€8_

E+1 1S THE WORD RETURNED FROM MEMORY AS A RESULT OF BLKO PI, (FUNCT 12).
MR-2184

NOTE:

CONO PI,
18

19
1

- {700600)

ADR

WR EVEN PAR

DATA

DIR

DROP INTERRUPT

CLEAR Pl SYSTEM

DROP | CLEAR |

REQ

INT

SYS

Pl CHAN

Pl SYSTEM

OFF

30
1

32
k]

]

356
I

SELECT CHANNELS

31
T

)

REQUEST INTERRUPT

MR-2154

00
’

-0

TRACK

(700540)

ENAB

)

]

24
L

NOTE:

]

28
i

16
1

15
1

1§

TWO’'S COMPLEMENT OF LENGTH OF BUFFER IN WORDS

)

29
1

31
T

18
L

32
7

PHYSICAL PAGE NUMBER OF BUFFER

:
1

33
I

23
1

34
1

24
L

35
1

25
1

26
1

TRACKS ONLY
ENABLE MICROCODE TRACKING
MR-2156

_.v 8_

DATAOPI,

" BLKIPI,
00

WORD
1

NUMBER

(RDERA)
.

SWEEP

CHAN
J

DATA
1

.21

SRC
H

]

)

]

’

»L

I :

[

]

REF MADE FOR CACHE SWEEP

SOURCE

REF MADE FOR CHANNEL XFER

WRITE

DATA

28
1

ADDRESS OF FIRST WORD OF TRANSFER

PHYSICAL

WRITE |:

]

[

‘

_g 8...

REFERENCE IDENTIFICATION

BIT <04:06> COMBINATIONS -

06 (WRITE =0)

06 (WRITE=1)

MEMORY (RD OR RPW)

CHAN STORE STATUS

0
1
1

1
0
1

‘
READ FROM CACHE
(PAGE REFILL OR CHAN READ)

CHAN STORE DATA
EBOX STORE FROM AR

CACHE WRITEBACK

MR-2162

vaday

(700400)

RDPERF

NIL

BLKI TIM,
'

(702000)

READ PERFORMANCE ANALYSIS DOUBLEWORD

MR-2086

CONI TIM (TOPS-10 TAG: TIMSTS)

01
:

06
.

]

09
1

10
]

|
i

25
]

TIMER

DONE

]

26
i

[

15
I

]

PERIOD

’

)

OVELO

]

12
T

INTERVAL TIMER
]

27
I

11
|

31
I

]

)

/ MR-2084

DATAI TIM,

RDTIM

(702040)

|
READ TIME

BASE

DOUBLEWOBD

MR-2085

_98_

|
702240

BLKO TIM,

WRPAE

(702100)

CHANNEL PERFORMANCE ANALYSIS ENABLES
I

‘21

{

}

PI PERFORMANCE ANALYSIS ENABLES
02

10 -

UCODE

IGNOR | IGNOR | LOW

NOPI

p—

PC MODE

| USER

PROBE

|IGNOR

CACHE PERFORMANCE ENABLES

IGNOR|

REF

FILL

WRITE

{

EVENT | CLEAR [

|MODE

|PA

SWEEP IGNOR |:

| 35

MR-2087

CONO TiIMm
%

CLEAR I
TIMER

ol
e

=] TIMER | CLEAR |

DONE

PERIOD REGISTER

DONE

{

)

MR-2083

WIL

702200

COMMAND

CODES

Code

Operation

Code

000

HALT

100

NVYHO

CHANNEL

Operation
.

FORWARD

DATA

TRANSFER

(DO

NOT

HALT)

001
010

101

REVERSE

DATA

TRANSFER

(DO

NOT

HALT)

110

FORWARD

DATA

TRANSFER

(HALT)

011

111

REVERSE

DATA

TRANSFER

(HALT)

CCW JUMP

0
‘L

OPfiODE

I
)

‘Ij

| |

20
.

15
L

T
‘

]

23
s

CHANNEL

]

CONTROL WORD

ADDRESS

’

[

]

4:]‘

[

‘T”

MRQ2186'

CCW DATA TRANSFER

HALT
REV
XFER | XFER

04
.

POSITIVE WORD COUNT
1

DATA

-88~-

I‘]
NOTE:

]

;

)

BUFFER STARTING ADDRESS (0 FOR SKIP OPERATION)

]

WORD COUNT FIELD
= POSITIVE WORD COUNT STORED IN CHAN AND DECREMENTED, IF BIT 1 =1 HALT WHEN WC =0.

ADDRESS 22 BITPHYSICAL ADDRESS:
IF
= 0; SKIP
IF DEVICE READ; DON'T MOVE DATA TO MEMORY
- {F DEVICE WRITE; CHANNEL SUPPLIES FILL DATA FROM EXEC PROCESS TABLE LOCATIONS 60—-63 TO WRITE REMAINDER OF DRIVES DATA BLOCK.

HALT AFTER LAST TRANSFER

‘

REVERSE DATA TRANSFER

_68_

MR-2187

CCW HALT
00

01
oP

CODE

‘24

LSS

]

[

{

MR-2185

NYHO

CHANNEL COMMAND LIST POINTER
|

NYHDO

WORD 0 JUMP
JUMP TO CHANNEL COMMAND LIST

NOTE:

EXECUTED AS A RESULT OF RH20 ASSERTING CBUS RESET.
MR-2188

WORD 1 STATUS

‘

8
RUN

ERROR | WC

=
=0

]

{

)

LIST POINTER (ADDRESS OF CURRENT CCW + 1)

‘1

{

MEMORY PARITY ERROR

" 'NOT ADDRESS PARITY ERROR

CHAN WORD COUNT DID NOT = 0 WHEN CHAN DID STORE

CHAN REF NON EXIST MEM

ERROR DETECTED AFTER RH20 TERM XFER, CHAN ABORTS

)

RH20 TRIED TO START CHAN WHEN CHAN WAS NOT READY

CHAN XFERRED DATA SPEC BY CCW, BUT RH20 STILL HAS DATA
IF DEV READ, RH20 SENT DATA BUT CHAN BUFF WERE FULL

RH20 COMP XFER, BUT WORD COUNT IN CCW NOT REACHED

IF DEV WRITE, RH20 REQ DATA BUT CHAN BUFF WERE EMPTY

NEXT XFER
MR-2189

...06..

WORD 2 STATUS
T

OP CODE

1
’.L

<00:01>

]
20

]
22

1
23

]

)

1
24

CURRENT WORD COUNT

1
I

1
28

DATA BUFFER ADDRESS

)
29

)

[]
30

1
31

CURRENT

1
1

CURRENT FUNCTION CODE IN CCwW

<03:13>

NORMALLY 0 AT END OF TRANSFER

00 =HALT

<14:35>

ADDRESS OF LAST DATA TRANSFERRED TO/FROM MEMORY

,_L,

J
35

1
_‘[6_

01 = NOT IMPLEMENTED '
02 = JUMP

03 = NOT IMPLEMENTED
04 = FWD DATA XFER
05 = REV DATA XFER

06 = FWD DATA XFER (HALT LAST XFER)
07 = REV DATA XFER (HALT LAST XFER)
MR-2190

NOTE:

WORD 3 OF THE CHANNEL LOGOUT AREA IS NOT CURRENTLY USED BUT THE PROGRAM MAY USE IT AS THE VECTOR INTERRUPT ADDRESS FOR THE
ASSOCIATED CHANNEL.
MR-2191

NVHO

WORD 3 STATUS

Data Transfer

Codes

Function Codes

Nondata Transfer

Codes

Data Transfer

Codes

Code | Fixed Head

Moving Head

Code | Fixed Head | Moving Head

Code | Magnetic Tape

01
03
05
07
11
13

NO-OP

NO-OP
UNLOAD
SEEK
RECAL
DRIVE CLEAR
RELEASE

51%*
53=*
61
63
71
73

01
03
07
11
21
25

NO-OP
REWIND - OFF LINE
REWIND
DRIVE CLEAR
RD-IN PRESET
ERASE

51*
57%
61
71
77

RD-IN PRESET|

BACKSPACE

23
31

15
17

DRIVE CLEAR

OFFSET
RET TO C.L.

‘

RD-IN PRESET
PACK ACK
SEARCH

*Implemented in RH1l controllers only.

WR CK DATA | WR
WR
WR DATA
WR
WR
RD DATA
RD
RD

CK DATA
CK HDR/DATA
DATA
HRD/DATA
DATA
HDR/DATA

27
31

SHAOO * LONNA

RH/TAPE

Function Codes

Nondata Transfer

Codes

WR CHECK FORWARD
WR CHECK REVERSE
WR. FORWARD
RD FORWARD
RD REVERSE

WR FILE MARK
SPACE FORWARD

*Implemented

RH1l1l

controllers

only.
_Z6_

RH/DISK

-93-

NOTES

O/I OTHY

CONI RHn

00
AR

(7XX240)

FULL | FuLL

INH

04
| ACT

| PLS

09
ILL

SELDR

FUNCT | ADR E

|DRRE |

ILL

rae

|ERROR|

cMD

ERROR | ERROR | WRITE | RUN

W | wxm

OVER

DBUS | DREXC | CHAN | cw
PE

| CHAN | CHAN | .,

| atrn | Busy | pone

PIA
|

ASSEMBLY REGISTER FULL

DATA BUS PARITY ERROR

CHANNEL BUFFER FULL

EXCEPTION ERROR

CHANNEL CONTROL INHIBIT

CHANNEL ERROR

04
05

CHANNEL CONTROL CHANNEL ACTIVE
CHANNEL CONTROL CHANNEL PULSE

21
22

CONTROL WORD WRITTEN
DATA CHANNEL OVERRUN

CHANNEL IS IN 22 BIT ADDRESS MODE

DRIVE RESPONSE ERROR

SELECTED DRIVE REGISTER ADDRESS ERROR

CONTROL BUS OVERRUN

CHANNEL DATA PARITY ERROR

CONTROL WORD PARITY ERROR

ATTENTION

NONEXISTENT MEMORY

ILLEGAL FUNCTION CODE

ILLEGAL COMMAND

MR-2198

RH10

Reg Adr
40

Addresses

R/W

Name

R W

Interrupt

R W

Data

R W

Reé Adr

R/W

Name

Control

Address

Buffer
Access Error

03
I

(7XX040)

CBUS

PAR

BIT

NOTE:

cBUS

DATA

T0DR | ToO

22
I

01
[

07
CBUS

CMD

24
L

25
|

27
I

DEVICE SEL CODE

28
I

29
J

30
I

DRIVE REGISTER DATA.

03
]

04
}

05
1

06
1

07
[

31
I

09
1

33
|

34
I

35
1

10
q

32
1

08
[l

17
1

{

16
H

ILL

LATE

]

21
1

06
CONT

11
1

12
1

13
L

14
1

15
1

REFER TO DATAO DIB FOR A DEFINITION OF BITS <00:05>, 06, <15:17> AND 18.

CONTROL BUS TIME OUT

CONTROL BUS PARITY ERROR

ILLEGAL COMMAND

MR-2200

O/1 OTHY

00
DATAI RHn

._(56._

DIB — Drive Interface Buffer

O/I OTHY

CR — Control Register
02

(7XX040)

0
:

NOTE:

05 -

]

1
Il

DBUS
TO

] MAINT |-

28
34

29
MEM |

DEVICE SEL CODE

-:{ MODE

30
00

V-

FUNCTION CODE

]

1
1

34
.

GO
_96.—

01
DATAI RHn

REFER TO DATAOCR FOR A DEFINITION OF BITS <00:05>, 15, 18, 19, AND 29.
Refer to the function code tables which precede the RH10 1/0 bit maps.

DATA BUS TIME OUT

CONTROL BUS TIME OUT

IA — Interrupt Address

00
DATAI RHn
(7XX040)

{

]

05
0

MR-2202

K110

KA10

INT

30
1

31
T

32
Li

33
¥

]

INTERRUPT VECTOR ADDRESS

NOTE:

}

REFER, TO DATAO CR FOR A DEFINITION OF BITS <00:05>.

KITOINTERRUPT BIT

KA10 INTERRUPT BIT

MR-2204

DB — Data Buffer

01
T

04
T

poe

11 |

{7 XX040)

21
T

NOTE:
14

(]

02
1

03
|

25
I

DBUS

EVEN

0OobDD

PAR

opD P

BYTE

BIT

27
T

28
T

29
T

30
T

31
T

32
|

33
|

34
T

\I\o’

35
!

DATA BUFFER BITS

05
]

04
I

T
|

01
i

)

22
T

06
}

07
|

08
]

09
i

]

1
{

12
]

13
1

14
1

15
[

16
i

17
1

REFER TO DATAO CR FOR A DEFINITION OF BITS <00:05>.
DATA BUS ODD PARITY

MR-2206

O/1 OTHY

00
DATAI RHn

O/I OTHY

AE — Access‘Error
00
DATAI RHn
(7XX040)

0
.

1 -

0
i

MR-2208

CONO RHn

18
(7XX200)

DBPE | DREXC | CHN
CLEAR|

WRITE |OVRUN|

CLEAR | CLEAR | cw

23
DRE

25
]

|ILLCM | CONT

RAE

CLEAR | CLEAR | CLEAR | RESET [

30
ATTN

ENAB | ENAB

31
STOP

DONE

DATA BUS PARITY ERROR CLEAR
CLEAR DRIVE EXCEPTION ERROR
CHANNEL ERROR CLEAR
WRITE CONTROL WORD
OVERRUN CLEAR

DRIVE RESPONSE ERROR CLEAR

[

24
- 25
28
29
30

PIA

CLEAR

...

18
19
20
21
22

[

ILLEGAL COMMAND CLEAR
CONTROLLER RESET
CONTROL BUS OVERRUN CLEAR
REGISTER ACCESS ERROR ENABLE
ATTENTION ENABLE

MR-2197

_86—

NOTE: - REFER TO DATAO CR FOR A DEFINITION OF BITS <00:05>.

DIB — Drive Interface Buffer

02
]

03
I

04
I

(7XX140)
]

-l

15
.

16
I

17
I

DEVICE SEL CODE

)

24. 25
L

02
1

03
1

04
]

05
i

06
]

SELECTS ONE OF 32 DRIVE REGISTERS FOR |NP_UT OR OUTPUT

07
L

09
1

10
i

11
1

12
i

13
i

14
1

<15:17>

DEVICE SELECT CODE SPECIFIES WHICH DEVICE (0-7)

CONTROL BUS EVEN PARITY

DEPENDING ON BIT 6,

DRIVE REGISTER DATA
00
L

<00:05>

10
.

CBUS
EP

LOAD
REG

15
]

IS TO BE USED IN THE OPERATION.

IF =0 DATA (FROM THE DRIVE REGISTER AND DRIVE

SPECIFIED BY BITS <00:05> AND <15:17>) WILL BE
TRANSFERRED TO THE RH.

IF =1 DATA WILL BE

TRANSFERRED TO THE DRIVE AND REGISTER SPECIFIED
MR-2199

O/I O0THY

_66_

00
DATAO RHn

O/1 OTHY

CR — Control Register
01

’

02
I

03
T

{7XX140)

0
i

0
1

0
L

REG

NOTE:

<00:05>

16
T

[

]

MEM
31

| -

17
|

DEVICE SEL CODE

MODE

[

FUNCTION CODE
00

35
GO

Refer to the function code tables which precede the RH10 1/0 bit maps.

<15:17>

I'S; TO BE LOADED IF BIT 06 IS SET. THIS APPLIES TO REGISTER

MAINT -

SEL

INAD

DBUS
EP

12
!

)

-00T~-

00
DATAO RHn

DEVICE SELECT CODE — SPECIFIES WHICH DEVICE
{(0—~7) IS TO BE USED IN THE OPERATION

ADDRESS 40—-77 ONLY. REFER TO DIB REGISTER FOR

DATA BUS EVEN PARITY

ADDRESS 00-37

DISABLE TRANSFER ERROR STOP

WRITE EVEN MEMORY PARITY

LOAD REGISTER — IF =0 LOAD CONTROL REGISTER.

’

IF =1 LOAD THE REGISTER SPECIFIED BY BIT <00:05>

MR-22C1

IA — Interrupt Address

01
1

09
K110

DATAO RHn

INT

(7XX140)

29
!

30
!

31
1

32
I

33
I

)

REFER TO DATAO CR FOR A DEFINITION OF BITS <00:05> AND 06.
KIT0 INTERRUPT ENABLE
MR-2203

O/1 OTHY

NOTE:

-TI0T-

INTERRUPT VECTOR ADDRESS

O/I OTHY

DB — Data Buffer

01
|

(7XX140)

0
|

19
I

]

LOAD | DIAG
]

22
1

REG

23
I

24
1

DIAG

]

27
1

04
1

05
]

06
|

)

07
1

REFER TO DATAO CR FOR A DEFINITION
OF BITS <00:05> AND

DIAGNOSTIC SYNC CLOCK
DIAGNOSTIC END OF BLOCK

08
|

33
i

pBuUS

PAR

34
{

35
|

BITS

09
L

DATA BUFFER

03
L

17
|

scLK | Eos

;

02
1

1
,

01
1

05
1

{
_

NOTE:

04
I

1
1

14
)

15
L

16
1

17
1

06.

DATA BUS PARITY
:

MR-2205

-201-

00
DATAO RHn

AE — Access Error

0
DATAO RHn
1

05
0

06
LOAD
REG

29
l

30
I

31
)

32
I

33
I

34
1

35
i

CLEAR REGISTER ACCESS ERROR FLAGS
04
1

03
1

02
L

01
|

)

REFER TO DATAO CR FOR A DEFINITION OF BITS <00:05> AND 06.
MR-2207

OTHY

NOTE:

05
]

O/1

06
|

-€0T-

(7XX140)

O/1 T1HY

RH11 — RPBA — Bus Address Register

07
1

04
L

03
L

02
§

01
L]

00
¥

BUS ADDRESS

(776704)

NOTE:

ALL BITS READ/WRITE

RH11 — RPCS2 — Control and Status Register 2
15

PROG

MISS

ERROR|

XFER | DPE

CONT | PAR

BAI

CLEAR|

INH

(776710}

DATA | WRCK |

UBUS | NON-X

LATE | ERROR|

DRIVE |

XM
-

MBUS | ouT

| READY|READY|

TEST

R/W

o1
1

R/W

DATA LATE

WRITE CHECK

UNIBUS PARITY ERROR

INPUT READY

12
11

NON-EXISTENT DRIVE
NON-EXISTENT MEMORY

05
04

CONTROLLER CLEAR
PARITY TEST

PROGRAM ERROR — RH BUSY

BUS ADDRESS INCREMENT INHIBIT

MISSED TRANSFER

<02:00>

UNIT SELECT

00
1

UNIT SEL

)

01
1

00
4

R/W

MASSBUS DATA PARITY ERROR
OUTPUT READY

MR-2216

-¥01-

MR-2215

RH11 — RPDB — Data Buffer Register

14
¥

(776722)

08
I

07
]

DATA BUFFER

14
i

NOTE:

]

08
L

]

ALL BITS READ/WRITE
:

-G0T~

MR-2217

RH11 — RPWC — Word Count Register

14
I

12
i

‘

08
1

07
|

WORD COUNT REGISTER

14
L

NOTE:

13
-

12
i

ALL BITS READ/WRITE‘V

1
'

08
L

07
i

06
1

05
]

MR-2218

O/I TTHY

(776702)

13
1

O/I 0zZHY

CONI RHn

(7XX 240)

MBUS |

PRI

CMD

AlE

CFL

DONE

EXC

34
I

WCE

ERROR | ERROR|

ERROR|

RDY

RUN

ENAB | ATTN

CFL

‘

35
1

PIA
|
{

}

,C_;

NOTE:

[e))

BITS 24, 28 AND 32 WILL CAUSE AN INTERRUPT.

DATA BUS PARITY ERROR

DRIVE EXCEPTION ERROR

MASSBUS ENABLE

LONG WORD COUNT ERROR

SECONDARY COMMAND FILE LOADED

SHORT WORD COUNT ERROR

MASSBUS ATTENTION INTERRUPT ENABLED

CHANNEL ERROR

PRIMARY COMMAND FILE LOADED

DRIVE RESPONSE ERROR

COMMAND DONE

<33:35>

PRIORITY INTERRUPT CHANNEL

CHANNEL READY TO BEGIN TRANSFER

DATA OVERRUN ERROR

MASSBUS ATTENTION

MR-2046

Reg

Adr

R/W

'Name

PREP

Preparation

(not

addressed

directly)

R--

PTCR

Primary

R'W

IVIR

Intetiupt

Transfer

R W

SBAR - Secondéry Block Address Register

R -

- Read Register

R W

STCR -

Secondary Transfer

)

- W

- Write

PBAR

Primary

DCR

Block

Control ‘Register

Address

Control

Vector

(Diagnostic Use)

Reg{ster

Diagnostic

Index

(Diagnostic Use)

Control

(Diagnostic

Use)

01
i

(7XX040)

02
]

03
|

04
I

21
|

CBUS | DIS

REG

RAEI

]

22
T

13-

C15

C14

C13

ci12
]

16
I

| TRAN

DEVICE SEL CODE

REC

c11
1

C10
|

29
1

. C09
1

Cco8
1

17
1

]

15
.

30
|}

31
I

32
|

co7

CO06
1

Co05
]

co4
[}

33
1

EXTERNAL REGISTER DATA — CORRESPONDS TO MASSBUS BITS <C15:C00>
L

NOTE:

RIS

LOAD

CBUS
PBIT

34
I

35
{

:
Cco3

Cc02
1

Co1
1

coo0
}

REFERTO PREP REG FOR DEFINITION OF BITS <00:05>, 6, AND <15:17>.
CONTROL BUS PARITY ERROR

DISABLE REG ACCESS ERROR, INTERRUPTS AND

SUBSEQUENT REG WRITES

TRANSFER RECEIVED (DEVICE RESPONDED)

CONTROL BUSPARITY BIT

MR-2050

O/1 0ZHY

00
DATAI RHn

-L0T-

EXT — External Registers (00—37)

00
DATAI RHn

(7xx 040)

I |

.02

14”.

DIS

'0/1 0ozHY

PREP — Preparation Register (Not Addressed Directly)

DEVICE SEL CODE

RAEI

cBus [
EP

REFER TO DATAO PREP REG FOR DEFINITIONS OF BITS.
=80T~

NOTE:

SBAR — Secondary Block Address Register (70)
DATAI RHn
{7XX040)

02 -

. 21

RRG

oot

DEVICE SEL CODE

0
]

{

BLOCK ADDRESS (DISKS) OR FRAME COUNT (TAPES)
L

NOTE:

]

[

)

[

REFER TO PREP REG FOR DEFINITIONS OF <00:05>, 06 AND <15:17>.
MR-2052

STCR — Secondary Transfer Control Register (71)
01
I

02
T

15
R

23
T

16
1

24
RS

25
i |

26
I

28
|}

]

17
I

DEVICE SEL CODE
1

NEGATIVE BLOCK COUNT (TWO's COMP)

XFER

13
]

::2:E F

DiS

22
R

21
T

32
L

33
i

34
¥

35
1

MASSBUS FUNCTION CODEFE
1

REFER TO PREP REG FOR DEFINITIONS OF BITS <00:05>, 06, AND <15:17>.

RESET COMMAND LIST POINTER

STORE CHANNEL STATUS CONTROL BIT

DISABLE TRANSFER ERROR STOP BIT

MR-2054

O/1 0ZHY

NOTE:

RfGISTER 18ELECT ((:)ODE (71)o

-601-

00
gl;(';m)Hn

DATAI RHn
(7XX040)

DEVICE SEL CODE
0

-1

-01T~-

BLOCK ADDRESS (DISK) OR FRAME COUNT (TAPE)
i

NOTE:

{

REFER TO PREP REG FOR DEFINITIONS OF BITS <00:05>, 06, AND <15:17>.
REFER TO SBAR REG FOR DEFINITIONS OF BITS <20:35>.
~

MR-2055

PTCR — Primary Transfer Control Register, (73)
00
DATAI RHn

(7XX040)

]

{

O/1 0zHY

PBAR — Primary Block Address Register (72)

10
]

STAT

14 o

)

DEVICE SEL CODE
'

21
-

DIS

TERM

23
|}

\
!

NOTE:

22
LIS

24
B

25
1

26
I

27
]

31
¥

NEGATIVE BLOCK COUNT {(TWO’s COMP)

]

32
|

33
{

34
|

35
|

MASSBUS FUNCTION CODE

)

REFER TO PREP REG FOR DEFINITIONS OF BITS <00:05>, 06, AND <15:17>.

REFER TO STCR REG FOR DEFINITION OF BITS 07, 10, AND 19.
MR-2056

IVIR — Interrupt Vector Index Register (74)

01
1

03
1

04
1

VECTOR (EPT) INTERRUPT ADDRESS
|

NOTE:

REFER TO PREP REG FOR DEFINITIONS OF BITS <00:05> AND 06.
MR-2058

O/1 0ZHY

(7XX040)

02
1

-TTT-

00
DATAI RHn

O/1 0ZHY

RR — Read Register (75) Diagnostic Use

(7XX040)

NOTE:
17
<18:35>

}

D15

100

000

25
]

26
]

27
|

28
1

29
|

30
1

17
=]

PAR

BIT

D04

DO3

D02

DO1

D00

]

DIAGNOSTIC WRITE DATA — CORRESPONDS TO MASSBUS BITS <D17:D00>

D14

]

22
L

‘

D16
i

- D17

03
1

D13
n

D12

D11

D10

D09

D08

D07

D06

DO5

=211~

00
DATAI RHn

REFER TO PREP REG FOR DEFINITIONS OF BITS <00:05> AND 06.
PARITY BIT

WRITE DATA AND PARITY (17) LOOPED BACK VIA MASSBUS

' XCVRS DURING DIAG WRITE

MR-2059

CONO RHn

(7XX 200)

I RAE

|mBCc | XFER | ENAB | cLP

peL | ATTN

CLEAR

sck | enas | STOP | pone

34
P

CLEAR REGISTER ACCESS ERROR

CLEAR MASSBUS CONTROLLER, ZERO IVIR REGISTER

ATTENTION INTERRUPT ENABLE

CLEAR TRANSFER ERRORS

'STOP TRANSFER (STATUS BITS NOT CLEARED)

DELETE SECONDARY CONTROL REGISTER

MASSBUS ENABLE

<33:35>

PRIORITY INTERRUPT CHANNEL

RESET COMMAND LIST POINTER
MR-2045

EXT — External Registers (00—37)
02
|

73X140)

05
|

'CBUS
EP

;
c15

NOTE:
- 09

c14

RAEI

24
1

)

c12

25
{

26
|

|DEVICE SEL CODE

27
|

28
i

29
¥

30
T

31
¥

32
]

(EXTERNAL REGISTER DATA — CORRESPONDS TO MASSBUS BITS <C15:C00>)
c11
c10
co9
cos
co7
co06
co5
co4
co3
1

| I

17
]

c13

16
||

DIS

REG

,
L

LOAD |

_37
REGISTER SELECT CODE (00-37)

{

]

33
1

34
1

co2

35
1

co1

c00

REFER TO PREP REG FOR DEFINITIONS OF BITS <00:05>, 06, AND <15:18>.
DISABLE REG ACCESS ERROR, INTERRUPTS AND

SUBSEQUENT REG WRITES.
MR-2049

O/1 0ZHY

st A

DATAO RHn

O0/1 0ZHY

PREP — Preparation Register (Not Addressed Directly)
00

03.
1

DATAO RHn

(7XX 140)

LOAD

DIS
RAEI

REG

15
i

DEVICE SEL CODE

CBUS

NOTE:

BITS <00:05>, 06 AND <15:17> HAVE A COMMON DEFINITION FOR MANY RH REGISTERS, TO ELIMINATE REDUNDENCY THEY ARE DESCRIBED ONCE
HERE.

1 <00:05>

”

TO BE LOADED IF BIT 06 IS SET.

" LOAD REGISTER. IF 0 LOAD PREP REG. IF 1 LOAD

<15:17>

DEVICE SELECT CODE. SPECIFIES WHICH DEVICE (0-7) IS TO BE

CONTROL BUS EVEN PARITY

USED IN THE OPERATION.

REG SPECIFIED BY BITS <00:05>

DISABLE REG ACCESS ERROR INTERRUPTS AND
SUBSEQUENT REG WRITES
MR-2047

SBAR — Secondary Block Address Register (70)

DATAO RHn

(7xx140)

01
:

BRE

4
|

LOAD
REG

1617
1

DEVICE SEL CODE
]

-pT1-

26
|

27
]

28
1

29
i

30
|}

]

BLOCK ADDRESS (DISK) OR FRAME COUNT (TAPE)

NOTE:

)

REFER TOPREP REG FOR DEFINITIONS OF BITS <00:05>, 06, <15:17>.

<20:35>

TAPE — FRAME COUNT 20 = MSD 35 = LSD

<23:27>

DISK — TRACK ADDRESS

<31:35>

DISK — SECTOR ADDRESS

MR-2051

STCR — Secondary Transfer Control Register (71)
02
|

(7XX140)

03
I

1
i

LOAD | RESET

STORE

REG

STAT

|cLp

DEVICE
SEL

25
{

26
1

27
I

]

NEGATIVE BLOCK COUNT (TWO's COMP)

TERM
1

17
|

CODE

22
1

16
T

0o
L

{

NOTE:

33
¥

34
1

35
1

FUNCTION CODE
| .

REFER TO PREP REG FOR DEFINITIONS OF BITS <00:05>, 06, AND <15:17>.

Refer to the function code tables which precede the RH10 1/O bit maps.
07

RESET COMMAND LIST POINTER

STORE CHANNEL STATUS CONTROL BIT

DISABLE TERMINATION OF TRANSFERS DUE TO DATA BUS

PARITY ERRORS OR DRIVE EXCEPTION ERRORS.
MR-20563

O/1 0ZHY

-ST1-

00
DATAO RHn

Oo/1I 0zZHY

IVIR — Interrupt Vector Index Register (74)

DATAO RHn

(7XX140)

LOAD [
[
REG

17
:

__
NOTE:

=91T1-

VECTOR (EPT) INTERRUPT ADDRESS

REFER TO PREP REG FOR DEFINITIONS OF BITS <00:05> AND 06.
MR-2057

WR — Write Register (76) Diagnostic Use
00
1

DATAO RHn

(7XX140)

03
]

)

000

LOAD

REG

[}

comp
1 pBIT

]

26
J

27
1

28
1

]

{

]

DIAGNOSTIC READ DATA

NOTE:

REFER TOPREP REG FOR DEFINITIONS OF BITS <00:05> AND 06.

COMPUTED PARITY BIT (BY PROG) FOR DIAG READ DATA
MR-2060

DCR — Diagnostic Control Register (77) Diagnostic Use
01
T

02
1

03
i

1
[

1
1

1
L

LOAD
REG

NOTE:
26

XFER | DATA
SIG
LOOP

TEST
EVEN | READ | SIM
SBAR | PCK
WRITE | D EXC

SIMm
EOB

SIM
SiMm
ATTN | SCLK

REFER TO PREP REG FOR DEFINITIONS OF BITS <00:05> AND 06.
31

SIMULATES DRIVE EXCEPTION

DATA LOOPBACK (VIA MASSBUS XCVRS)

SIMULATES END OF BLOCK

28
29

TRANSFER SIGNAL (SIMULATED)

TEST SBAR
EVEN PARITY CHECK

34
35

SIMULATES ATTENTION
SIMULATES SYNC CLOCK SIGNAL

"READ/WRITE-SET ON DIAG READ

(LOOPS RD DATA VIA MASSBUS XCVRS)
MR-2061

O/1 0zHY

(7XX140)

-LTT-

00
DATAO RHn

0dd-HY

RH11 — RPCS1 — Control and Status Register 1
RH20— DRCR
— Control Register

(776700)

SPEC | XFER

MBUS

DRIVE | PORT

ADDRESS

(MB-00)

conD | ERROR]|

cPE

AVAIL | SEL

R/W

NOTE:

R/W

rReapy | 'NIT

R/W

FUNCTION

ENAB |

R/W

RMW

90/

Go
01

R/W

SHARED REGISTER BITS <15:13> AND <10:06> ARE IN RH.
REFER TO DCL PRINT RG3 AND RG6.

SPECIAL CONDITION

~8T1-

Refer to the function code tables which precede the RH10 I/O bit maps.

PORT SELECT

TRANSFER ERROR

<09:08>

UNIBUS ADDRESS EXTENSION BITS 17 AND 16

MASSBUS CONTROL PARITY ERROR.

INTERRUPT ENABLE

DRIVE AVAILABLE
.

MR-2219

RH11 — RPDS — Drive Status
RH20 — DRSR — Status Register.

15
(776712)
(MB-01)

ATTN |

AcT | ERROR|

NOTE:

13
o1p

12
|

write|

REFER TO DCL PRINT RG6.

MOL | 1ock | sect | ABLE | PRES

ALL BITS READ ONLY.

07
| READY|

voL

P=! | D>64 | GOREV|

DIGB | DF20 | DFOS

RERERERN: SUSESHORS, SRns

i B

15 -

ATTENTION ACTIVE

~ POSITIONING IN PROGRESS

122

RP04 — DIFFERENCE EQUALS ONE

RP04 — DIFFERENCE LESS THAN 64

RP04 — GO REVERSE

RP04 — DRIVE TO INNER GUARD BAND

RP04 — DRIVE FORWARD 20 INCH/SEC

MEDIUM ON LINE

LAST SECTOR TRANSFERRED

09 .

PROGRAMMABLE

08
06

DRIVE PRESENT
VALID VOLUME

00
<06:00>

’

RP04 — DRIVE FORWARD 5 INCH/SEC
RP06 UNUSED

MR-2220

15
(MB-02)

| DATA | UN

CHECK|

NOTE:

OPER

|DRT

SAFE | INC

|WRLK

|IADR

|AOV

|[HCRC

|HCOM

| ERROR|ERROR|

ERROR|

ERROR | ERROR|

06
|ECC

ERROR|

WR CK | FMT

| PAR

FAIL | ERROR|

ERROR

rvmr |

tLL

| AL

REG | FUNC

ALL BITS READ/WRITE.
REFER TO DCL PRINT RGO.

13
12
1

OPERATION INCOMPLETE
DRIVE TIMING ERROR
WRITE LOCK ERROR

06
05
04

ECC HARD ERROR
WRITE CLOCK FAIL
FORMAT ERROR

INVALID ADDRESS ERROR

PARITY ERROR

ADDRESS OVERFLOW ERROR

HEADER CRC ERROR

ILLEGAL REGISTER

HEADER COMPARE ERROR

ILLEGAL FUNCTION
MR-2221

90/%0dd-HY

(776714)

=611~

RH11 — RPER1 — Error Register 1
RH20 — DRER1 — Error Register 1

(776724)

HICT | SBYTE | ZERO | DATA | ECC

(MB-03)

DET

| wRITE|

NOTE:

| DET

DET

ENV

90/¥0dd-HY

RH11 — RPMR — Maintenance Register
RH20 — DRMR - Maintenance Register

READ | SCLK | INDEX | cLock|

MODE

ALL BITS READ/WRITE.
REFER TO DCL PRINT EC1 AND RG3.

HIGH COUNT DETECT

SYNC BYTE DETECTED
ZERO DETECT

'DATA ENVELOPE

ECC ENVELOPE

03
00

MAINTENANCE SECTOR CLOCK
DIAGNOSTIC MODE
MR.2222

-0CT1~-

09
08

RH11 — RPAS — Attention Summary
RH20 — DRAS — Attention Summary

06
T

(776716)
(MB-04)

{

NOTE:

05
1

)

04
LJ

03
I

02
I

DRIVE ATTENTION SUMMARY
05

01
I

[

00
|

[

ALL BITS READ/WRITE.
REFER TO DCL PRINT DP.
MR-2223

RH11 — RPDA — Desired Track/Sector Address
RH20 —- DRDA — Desired Track/SectorvAddress‘
15

11
T

(776706)
(MB-05)

16
NOTE:

]

10
I

03
1

TRACK ADDRESS
|

02
1

01
1

SECTOR ADDRESS

[

00
¥

]

ALL BITS READ/WRITE.
REFER TO DCL PRINT SS3 AND SS6.

-1¢I-

MR-2224

RH11 — RPDT — Drive Type
RH20 — DRTR — Type Register
14

NO BLK|

TAPE

MOVE

(MB-06)

ADR

DRIVE | HEAD R

NOTE:

ALL BITS READ ONLY.

[

02
T

01
T

00
T

DRIVE TYPE

04 |

REFER TO DCL PRINT ECS.

15
14

NOT BLOCK ADDRESSED

MOVING HEAD

TAPE DRIVE

DRIVE REQUEST REQUIRED

MR-2225

90/%0dd-HY

15
(776726)

90/%0d9-HY

RH11 — RPLA — Look Ahead
RH20 — DRLP

|§

(776720)

(MB-07)

NOTE:

SECTOR COUNT

EXT FIELD

[

ALL BITS READ ONLY.

REFER TO DCL PRINT DP6.

EXTENSION FIELD
05 04

HEAD LOCATION

0=<20% (IN FIRST 20% OF SECTOR)

1=20-40%

0=40—80%

1=>80% (IN LAST 20% OF SECTOR)
MR-2226

RH11 — RPSN — Serial Number
RH20 — DRSN — Serial Number

15
(776730)

(MB-10)

14
|

13
|

NOTE:

HIGH ORDER DECADE

28
.

09
T

24
B

22
1

21
L

14
{

04
1

12
;

)

1
[

02
LB

08
)

01
I

00
1

LOW ORDER DECADE

ALL BITS READ ONLY.
_

REFER TO DCL PRINT ECS.
MR-2227

e AA

<05:04>

RH11 — DPOF — Offset
RH20 — DROF — Offset

(776732)
(MB-11)

SIGN
CNG

14
NS

FMT

Ecc | Hcom fi

INH | INH

06
i

06
1

NOTE:

05
L

04
¥

05
)

]

OFFSET

04
1

ALL BITS READ/WRITE.
REFER TO DCL PRINT RG1.

SIGN CHANGE

FORMAT 22 SECTORS

ECC INHIBIT

HEADER COMPARE INHIBIT

-€21-

MR-2228

RH11 — RPDC — Desired Cylinder
RH20 — DRDC — Desired Cylinder

8 B,

NOTE:

08
pco9

07
|

pcos

06
| pco7

05
| pcoe

| pcos

| pcoa

02
|

pcoz

01
| pcoz

00
|

Deo1

ALL BITS READ WRITE.
REFER TO DCL PRINT SS1.
MR-2229

90/ 0dd-HY

(776734)
(MB-12)

90/
% 0dd-HY

RH11 — RPCC — Current Cylinder Address

RH20 — DRCC — Current Cylinder Address
08

05
i

(776736)

(MB-13)

NOTE:

04
1

03
]

CURRENT CYLINDER REGISTER

ALL BITS READ ONLY.
REFER TO DCL PRINT SS1.

RP04 — UNUSED
RP06 — CURRENT CYLINDER BIT 10

e 2A

MR-2230

RH11 — RPER2 — Error Register 2
RH20 — DRER2 — Error Register 2

15
(776740)
(MB-14)

ACUN [oiintl
R

NOTE:

pro

30VU

UNSF

[T ERROR|

ALL BITS READ/WRITE
REFER TO DCL PRINT ECS.

|ynpeEX | NO

HSEL | HSEL

| UNSF

[ apsy

| UNSF

| DETF

[ppaec|

UNSE

| UNSF

| UNSF | unsr

RP04 — AC UNSAFE

RP0O4 — FAILSAFE ENABLED

PHASE LOCKED OSCILLATOR UNSAFE

TRANSITION UNSAFE

RP0O4 — 30 VOLTS UNSAFE

TRANSITION DETECTOR FAILURE

RP0O6 — UNUSED

RP04 — MOTOR SEQUENCE ERRCR

NO HEAD SELECT

CURRENT SWITCH UNSAFE

MULTIPLE HEAD SELECT

WRITE SELECT UNSAFE

WRITE READY UNSAFE

CURRENT SINK FAILURE

WRITE CURRENT UNSAFE

RP0O6 — UNUSED

RP06 — ABNORMAL STOP

INDEX ERROR

RP06 — READ AND WRITE

MR-2231

15
(776742)

(MB-15)

OFF | SEEK

] VEUS | PSUN

cyL

Ltow

Low

NOTE:

| INc

=GCT-

RH11 — RPER3 — Error Register 3
RH20 — DRER3 — Error Register 3

wr os | oc un

ALL BITS READ/WRITE.

- 15

OFF CYLINDER

.14

SEEK INCOMPLETE

RP0O4 — UNUSED

AC VOLTAGE UNSAFE

RP04 — VELOCITY UNSAFE

RP06 — OPERATOR PLUG ERROR
DC VOLTAGE UNSAFE
04

RP04 — ANY UNSAFE EXCEPT READ/WRITE
RP06 — UNUSED

RP06 — WRITE AND OFFSET
00

RP04 — PACK SPEED UNSAFE

RP06 — DC VOLTAGE UNSAFE

RP0O4 — UNUSED

RP06 — 35 VOLTS UNSAFE
MR-2232

90/%0dd-HY

REFER TO DCL PRINT EC7.

90/%0dd-HY

RH11 — RPEC1 — ECC Position Register
RH20 — DREC1 — ECC Position Register

12
(776744)

4096

(MB-16)

2048

10
1024

09
512

08
256

|§

)\ |

ECC ERROR LOCATION

128

32
.

NOTE: ALL BITS READ ONLY.

REFER TO DCL PRINT EC2.

<12:00>

BURST LOCATION CODE FOR ECC
.

-9C1-

MR-2233

RH11 — RPEC2 — ECC Pattern
RH20 — DREC2 — ECC Pattern
SENSOOO00

ERERRR

ooooooos

IOSORONE

(776746)
(MB-17)

Sl SSN F OBSSENES g

NOTE:

ECC MASK BITS

06
1

05
05

]

)

03
i

ALL BITS READ ONLY.
REFER TO DCL PRINT ECA1.

<10:00>

ERROR BURST AT COMPLETION OF ECC
MR-2234

TABLES/MAPS
-127-

NOTES

€0/Z0WL-HY

CS1 — Control Register 1

03
1§

(MB-00)

DRIVE |

2| avaiL [

NOTE:

R/W

02
I

R/W

FUNCTION CODE

]

R/W

Refer to the function code tables which precede the RH10 1/O bit maps.

DRIVE AVAILABLE (HARDWIRED)

DS — Status Register

15
ATTN

(MB-01)

Aact

NOTE:

|ERROR|

PIP

11
WRITE

MOL | Lock

EOT

08
‘]

DRIVE | DRIVE | SLAVE |

| PRES | RDY
5

|STAT

05
PE

SET

IDB

TAPE

STAT | DOWN | DECT | MARK

01
BOT

00
SLAVE

ATTN

ALL BITS READ ONLY.

ATTENTION ACTIVE

COMPOSITE ERROR

PHASE ENCODED STATUS

POSITIONING IN PROGRESS

SETTLE DOWN

SLAVE STATUS CHANGE

MEDIUM ON LINE

IDENTIFICATION BURST DETECTED

END OF TAPE

TAPE MARK DETECTED

DRIVE PRESENT

BEGINNING OF TAPE

DRIVE READY

SLAVE ATTENTION

MR-2073

-82T-

MR-2}072

ER — Error Register

15
CRC

NOTE:

SAFE

OPER

|DRT

'NXF

| INC

|ERROR]|

ITTM

ERR

08
NSTD |
| GAP

PFE

NDE

| DBUS

|FMT

CBUS |

REG

ILL

LRC

VPE

| PE

ERROR|

MOD

REG

| FUNC

ALL BITS READ ONLY
PE
SP LITBITS
I
—=—!

PE — CORRECTABLE DATA ERROR NRZ! — CRC DOES NOT

PE — FORMAT ERROR

PE — NONCORRECTABLE DATA ERROR

MATCH COMPUTED CRCC
14

UNSAFE

OPERATION INCOMPLETE

NRZI — CHECK CHAR ERROR
NRZI — VERTICAL PARITY ERROR

DRIVE TIMING ERROR

NONEXECUTABLE FUNCTION

FORMAT ERROR

PE CORRECTABLE SKEW

CONTROL BUS PARITY

DATA BUS PARITY ERROR

NRZ! — ILLEGAL TAPE MARK

FRAME COUNT ERROR

ILLEGAL REGISTER

NONSTANDARD GAP TAPE CHAR

ILLEGAL FUNCTION

MR-2074

€0/Z0WL-HY

-62T1-

(MB-02)

CORR | UN

€0/Z0WL-HY

MR — Maintenance Register

15
08
NOTE:

<15:7>
'
'
06

14
07

{

MAINTENANCE DATA FIELD
05

]

SEL

MANT

]

MANT

MODE

SCLK | CLK

MAIN OP CODE
L

ALL BITS READ/WRITE

MAINT DATA FIELD: BUFFER DATA ON WRAP OP, LRC AT
END OF NRZI TRANSFERS
SELECTED SLAVE CLOCK: WRT CLOCK SIG GEN BY SEL

<4:1>

MAINTENANCE CLOCK
MAINT OPERATION CODE
MAINT MODE

SLAVE

MR-2075

AS — Attention Summary

(MB-04)

ATTENTION SUMMARY

'
1

00
L

NOTE: . ALL BITS READ/WRITE
MR-2076

-0€T~

(MB-03)

FC — Frame Count

14
I

( MB-05 )

13
Ll

NOTE:

12
I

11
T

10
)

09
I

08
LR

05
I

04
L]

03
1

]

00
1

FRAME COUNT

ALL BITS: READ/WRITE

DT — Drive Type

(MB-06)

NOBLK | TAPE

MOVE |

ADR

HEAD

DRIVE |

07
]

]

| DRIVE | SLAVE

REQ

05
¥

04
I

ALL BITS

02
I

01
]

00
¥

DRIVE TYPE {011 = TU16) (012 = TU45)

PRES

04
1

NOTE:

03
]

03
|

‘

]

READ ONLY

BITS <08:00> HARDWIRED
15

NOT BLOCK ADDRESSED

TAPE DRIVE

MOVING HEAD UNIT

<08:00>
;

'
.

DRIVE TYPE
X5X = TM03
X1X = TM02

7 CHANNEL UNIT-NEGATED ON 9 CH DRIVE OR

XX1 =45 IPS SLAVE

POWER LOSS

XX2 =75 IPS

DRIVE REQUEST REQUIRED

XX4 =125 IPS

SLAVE PRESENT
MR-2077

€0/ZO0WI-HY

~TET-

MR-2082

€0/Z0WL-HY

CK — Check Character

14 -

(MB-07)

NOTE:

=
]

4PAR

|
]
T
DEAD TRACK (PE MODE)
09
03
05

{

ALL BITS READ ONLY

USE THIS BIT MAP FOR PHASE ENCODED DRIVES

MR-2078

CK — Check Character

CRC BITS FOR LAST XFER (NRZI MODE)

(MB-07)

PAR

NOTE:

_ 00

{

)

ALL BITS READ ONLY

USE THIS BIT MAP FOR NRZi DRIVES
MR-2079

SN — Serial Number

14
T

(MB-10)

NOTE:

13
1

]

05
T

06
|

05
]

01
|

00
|

01
{

00
{

ALL BITS READ ONLY

-EE€T1-

MR-2080

TC — Tape Control

09
T

AccL | FRAME | TAPE
STAT
WRITE|

NOTE:

EAO
DTE
i

DENSITY
01

[

05
1

]

EVEN
PAR

SLAVE SEL
01

FORMAT SELECT
02
01

00
1

ALL BITS READ/WRITE

ACCELERATION

FRAME COUNT STATUS

ENABLE ABORT ON DATA TRANS ERROR

TAPE CONTROL WRITE

<02:00>

EVEN PARITY
SLAVE SELECT BITS

MR-2081

€0/Z0WIL-HY

15
(MB-11)

TYPE

PRG

05*

06*

SEL | SEQ

E:;’

LEN

:.(2:1

iLL | DsR

error |ERROR | (PAR |erroR|

STAT

09*

04*

03*

02
1

02/0TXA

CHANNEL STATUS REGISTER

SR | OPER

LEN | cmD | FLAG | ERROR|

INC

5 DEVICE PAR ERROR
0 PROGRAM STATUS
6 LENGTH ERROR
00 = INITIAL SELECTOR STATUS
TYPE
12

7 IGNORE LENGTH ERROR

01 = ENDING STATUS

8 ILLEGAL COMMAND
9 DEVICE STATUS REGISTER FLAG

10 = TXOX INITIATED STATUS
11 = IDLE STATUS

10 SENSE BYTE READ ERROR

3 SELECTION ERROR

11 OPERATION INCOMPLETE

4 SEQUENCE ERROR

“THIS REGISTER CONTAINS USEFUL ERROR INFORMATION
WHEN CSR FLAG IN DX10 CONI IS SET.

MR-11411

DEVICE STATUS REGISTER

00*

ATTEN|

01
STAT |

03*

06*

07*

CHAN | DEV | UNIT | UNIT

cuU

“iop | enp | BYSY | enp | eEnD | cHECK| EXCEP

0 ATTENTION
1 STATUS MODIFIER
2 CONTROL UNITEND
3 BUSY

4
5
6
7

CHANNEL END
DEVICE END
UNIT CHECK
UNIT EXCEPTION

*SET DSR FLAG IN CHANNEL STATUS REGISTER.

THIS REGISTER CONTAINS USEFUL ERROR INFORMATION WHEN SET.
MR-11412

itA3

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DEFINITIONSREGISTERINTERFACE MASSBUSDX20

(72}

DX20

dpraeorsbnTiatgenfmrnhsteansetors

-135-

05
atere]

04
L

03
T

02
1

01
1

NOTE:

00
'

FUNCTION CODE

0ZXa

CONTROL REGISTER — Address 00 (M8604-MC02 E91, 110)

ALL BITS ARE READ/WRITE.

15—06k NOT USED

05-01"

FUNCTION CODE

GO
MB-6611

STATUS REGISTER — Address 01 (M8604-MC10 E8)

15
ATA

' NOTE:
15

ERR

LINK

PRES

RUN

ALL BITS ARE READ ONLY.
ATTENTION
ERROR

LINK PRESENT

MICROPROCESSOR RUN
MR-6612

DX20
-137-

CONTROL

Address

Bits

15-06

Not

Bits

05-01

Function

performed.

Valid

(M8604-MC02

E91,

110)

used.
Code

The

operations

function

code

put

is the function
bits 05-01 are

into

to
as

follows.

Code

Disk

Functions

Tape

Operation

Functions

Operation

Rewind Unload

Seek

07
11

Recalibrate
Drive Clear

Sense

Release

Erase

Gap

Write

Tape Mark

Backward

35
37

Forward

Test

I/0

Data

Security

Rewind

Drive

Clear

Forward

Space

Backward

Record

Space

Record
File

Space

File

Erase

Sense

Write

Data

Write

Format

Write
Write

Write

Special

Loop

Diagnostic
Write to Read

Read

Data

Read

Data

Read

Format

75
77

Read

Special
-

Read
Read

Reverse

Bit 00 - GO
available
to
the

DX20

Sense

Bit - The GO
it and
start

when

the

function

another

command.

Réverse

Data

Extended

bit
the

causes

complete

the

Status

DX20

operation.
and

study

The

bit

cleared

the

DX20

then

the

bit

being

(l:l‘ A

rt‘fl(]y

NOTE

The GO bit cannot be set if error is
in the Status Register (address 01).

STATUS

Bit

indicates

that

this

the

bit,

the

attention

Bit

condition

host.
also

field
Bit
when

DX20

has
bit

Link
DX20

error

bit

error

Present
is

Bit

the

microprocessor

status

E8)

The

ready

(address

E78)

the

bit

E97)

DX20,

cleared

(M8604-MC03

04)

This
but

set,

attention

for

corresponding

(M8604-MC03

the

(M8604-MCl0

detected

the

(M8604-MC02

summary

The

07-00

Address

attention

Error

When
set.

Attention

set

the
the

must

bit

has

not

host.

Massbus

cleared.

set

been

set

clear

device

cleared

error
by

the

attention

bit

(bit

15)

clearing

any

bits

bit

always

set

(address
E76)

02).
This

bit

This

bit

operation.

Microprocessor
is

Run

(M8604-MC10

running.

E8)
‘

set if

0Z2Xd

ERRIOR suB
ve- (;LASS CO'DES,
L

T SS CODE‘ s

ERROR CLASS

[

NOTE:

ALL BITS ARE READ/WRITE.

15—-12

MICROPROCESSOR DETECTED ERROR SUB-CLASS CODE
MICROPROCESSOR DETECTED ERROR CLASS CODE

11-08
07

MICROPROCESSOR ERROR
MICROPROCESSOR STOPPED
MICROBUS PARITY ERROR

ERR

¢8 | RMR | IR
DB | PAR
g | PAR
mp
stop | PAR
trr | Mmp

00
ILE
-8¢T-

ERROR REGISTER — Address 02

DATA BUS PARITY ERROR
CONTROL BUSPARITY ERROR
REGISTER MODIFICATION REFUSED
ILLEGAL REGISTER
ILLEGAL FUNCTION
MR-6613

DX20
-139-

ERROR

Address

Bits 15-12 - Microprocessor Detected Error Class
Code which class error the microprocessor has detected.
Each
a

type

Bits

11-08

Indicates
subclass
report

The

logging

a
is

Error

Class

error

error
to

Detected

within

used

and

Subclass

Error

error

SYSERR

Subclass

Error

Subclass

Codes

are

Unusual

Device

not

Status

necessarily

device

returns

check

(error)

condition)

This
a

set.

Condition

byte

with

unit

Refer

sense

RP20

sense

(tape)

for

Status

from

the

final

Status

from

the

initial

Disk

Only:

data

transfer

is
2

always

Tape

was

Only:

Disk

Only:

Device

that

the

Only:
Only:
may

Data

Ending

Address

path

' drive

drive

the

not

bad

read,

not

Error

not

read.

Indicatesn

present

(1,e,,

Error

Indicates

parity

error.

Address

match

the

Error

returned

correct

Address

returned

parity.

Initial statfis byte parity error.

Data path detected microbus‘parity error.
Channel

parity
7

Channel

Device

Run

)

handshake

not

Only:

Select
not

present.

Disk

Only:

command

needs

interface

detected

the

microbus

error.

asserted

was

Tape

bus

the

address.

4
6

the

error.

byte

Parity

has

last

This

operation.

Mismatch

Address

the

length.

drive

record

parity

does

Selection

Recoverable

status

correct

disks.

IN).

Long

retry

bytes

detailed

sequence.

Indicates

record

addressed

Disk

the

error.

SELECT

Tape

selection
-

the

with

Short
an

CPU

not

code

sequence.

Length

error

necessarily

received

Record

This

set

bytes

1
2

either a unit
exception
(unusual

error

detailed

follows.

error.

status

(disk)
or TX02
information.

Code

class.
providing

has

Description

for

failures.

Class

Indicates
class

recovery.

Microprocessor

specific
designed

the

and

help

timeout.

disconnect

in.

received

from

Device

Select

Addressed
'

Error

TX02

- Received

address

that

Command

retry

from

RH20.

the

Retry

Request

sequence
host,

with

The

the

DX20

drive

and

DX20
-140-

Class

Subclass

Description
motion.

tape

during

error

Recoverable

Only:

Tape

Data path parity error on IBM channel bus.

Parity error in final status byte from TX02.

channel bus
known number

which cannot be’ recovered after a

‘of

(microcode).

retries

if a

Issued

Disk Only: Nonrecoverable Error parity error is detected on the

Parity error receiving the drive address during
the sequence initiated by the control unit. The

microcode previously retried the operation five
times.

Parity error receiving the drive status during
the sequence initiated by the control unit. The
microcode previously retried the operation five

times.

Recoverable

Only:

Tape

error

before

because

tape

motion.

Address

Bus

returned

correct

the

match

status

Run not

received

from RH20.

Disk Only: Retry log information available.

Tape

Only:

tape

position

Data

path

parity

was

not

microbus

detected

error.

detected microbus

(M8607)

Channel bus interface
error.

parity

IBM channel bus handshake timeout with TXO02.

TX02 asserted disconnect in.

Disk

Only:

without

Fatal

repairing

microcode.

Drive

match

type

Error

microprocessor

the

known.

M8606)

(M8605,

because

error

Nonrecoverable

bus

channel

IBM

not

while

bus

IBM channel

error

byte.

initial

did

from TX02.

address

parity

error

parity

receiving

TX02

address.

cannot
or

occurs

corrected

reloading

along

with

the

halting.

expected

hardware

Error

hardware

microcode

the

does

not

type.

drive

Unknown
control

Control Unit - Microcode detects a
unit other than the RP20 disk control

Massbus

controller

Microprocessot

unit.

fail

(DCU).

(RH20)

power

failed

(power

1line).

{nothing

interrupted

interrupt

0).

from
:

interface

DX20
-141-

Class

Subclass

Description

Tape

0
'

Only:

drive

error

sequence

type

does

the

drive

Parity

initiated

has

error

the
sequence
‘Microcode has

(nothing

Diagnostic

drive

the

status

power

interrupted

times.

byte

during

failed

from

Microprocessor

locations
halts
by

Either

set.

way,

the

Extended

includes

loops

the code is
(address
02)
and

status

Bit

DX20

halts,

error

status

the

Microprocessor
which

Microbus

Data

Bus
from

includes

Control

receives

Bit

the

host

being

00)

Bus

written

set.

Parity

Illegal

access

Illegal

for

Set

the

new

the

error

Set

E86)

Set

the
set,.

DX20
the
bit

the

DX20

data

path

the

host.

(M8604-MC02
the

are

bad

that

the

E95)

(control

the

parity.

Set

when

prevented

from

(address
only

Set

address

03)

and

the

registers

that

can

set.

(M8604-MC02
be

E95)
with

(M8604-MC02

bit

host

the

stopped

When

(M8604-MC02

when

the

from

31)

bit

function

E86)

Set

failure.

undefined

Function

illegal

E80)

parity

the

bad

Refused

into

because

(address

transmitted

Error

asked

reqgister

bit

include

hardware

(M8604-MC02

with

information

write

when

the

parity

Modification

into

detected

(M8604-MC02

Error

host
bad

into

E80)

08-15

microcode
the
i{dle

set,.

microprocessor

microbus.

diagnostic

tries

01l)

sets

maintenance

Bit

and

number.

error

internal

The

written

bits

the

attention

(M8604-MC0O2

Error

its

the

control

which

Parity

data
DX20

DX20

the

(M8604-MC02

Stopped

Parity

receives
the

placed

(address

that

caused

from

Bit

code

error

detects
an
error
on
microprocessor
halts,
(bit 06).

Error

1indicate

information.

Microprocessor

microprocessor

Bit

Disk/Only: Interrupt on Full Initial Start-up loop,

Bit

3 or 4. Otherwise
a
stack
pointer

Confirms that the host knows that the
has
been
started.
Before
entering

Bit

(power

Interface

Error

SYSERR]

the

unit.

five

0).

are

during

control

interrupt

error.

flag

[E0O(26)

hardware

if started at
microprocessor

underflow

repair

by
the
control
unit.
operation five times.

the

(RH20)

error

address

operation

initiated
retried

controller
line).
.

the

match

the

Microprocessor

halted.

not

retried

Massbus

fail

microcode

type.

Parity

Reload

Microcode

Microcode
2

microprocessor

drive

Fatal

hardware;

E10l1)

E101)
-

Set

performed.

Set

the

host

has

NOTE:

15-05

04
03
02

STR

RST

0ZXd

MAINTENANCE REGISTER — Address 03

ALL BITS ARE READ/WRITE.

NOT USED

MICROPROCESSOR SINGLE CYCLE
WRITE EVEN PARITY
MICROPROCESSOR START

DXZORESET

‘NOT USED

AAS

MR-6614

ATTENTION SUMMARY REGISTER — Address 04
15

1110

04
i

ATTENTION BITS
1

NOTE:

15—08
07-00

ALL BITS ARE READ/WRITE.
NOT USED

ATTENTION BITS
MR-6615

DX20
-143MAINTENANCE

Address

Bits

15-05

Bit

Micrdprocessor

the

diagnostics

Not

microprocessor
Only

Bit

the
Bit

even

bit,

Bit

the

all

Bit

Parity

results

this

Reset

the

per

set,
of

set,

Start

current

the

When

When
PC

end

the

DX20

any

ALU

set

the

microprocessor

host,

the

current

host,

07-00

the

host

Only

DX20

clears

instruction.

the

DX20

halts

and

used.

SUMMARY

15-08

DX20
start.

operation.

the

location.

the

microprocessor

bit.

its

halts

Cycle
once

registers.

Not

ATTENTION

Bits

bit.

DX20

resets

clock

this

Microprocessor

execution

the

its

use

Even
use

Single

cycle

parity

diagnostics

starts

Bits

will

Write

generates

used.

Not

Attention

for

each

Massbus

set,

bit

the

status

the

Massbus

device.

Address

This

used.
Bits

device.

this

the

is set.
(address 01),

has

attention
To

clear

the

one

attention

bit

for

the

attention

bit

that

device

bit
3

bit in
identifies

]

NOTE:

)

01
.

RECORD NUMBER

HEAD NUMBER

)

0ZXd

HEAD/RECORD REGISTER — Address 05 [Disks Only]
— Address 05 [Tapes Only]
BYTE COUNT REGISTER
10
11
12
13
14
15

]

ALLBITS ARE READ/WRITE.

-yvi-

MR-6616

DRIVE TYPE REGISTER — Address 06

DRIVE TYPE

NOTE:

ALL BITS ARE READ/WRITE.

15—00

DRIVE TYPE REGISTER

MR-6617

CONO BIT ASSIGNMENTS
18

19
T

20
T

21
T

22
T

23
T

ICPC
|

18—24
25

mpP

ICPC
I

]

ERROR

PAR

NXM

STAT

AVAIL

1 =INHIBIT ICPC LOAD

STATUS AVAILABLE

0=LOAD ICPC

STATUS REQUEST

CLEAR

35
|

REQ

CLR

ERROR

INITIAL CHANNEL PROGRAM COUNTER

MEM

CONT

PIA
\

MICROPROCESSOR ERROR

CONTINUE

MEMORY PARITY ERROR

33—-35

NONEXISTENT MEMORY

PRIORITY INTERRUPT ASSIGNMENT

MR-11409

CONI BIT ASSIGNMENTS

RUN
BIT

BITS

18-24 AND 26—35
17

25
* %

19
T

20
T

21
|

22
1

ICPC

‘

23
T

26**

26*

CSR

FLAG

| ERROR

27*

28*

29*

STAT

PAR

ERROR

AVAIL

REQ

35
1

MEM

NXM

CLEAR|

CONT

PIA

SEE CONO BIT ASSIGNMENTS.
MICROPROCESSOR RUN BIT

CSR FLAG

CAUSES AN INTERRUPT TO THE CPO.
AFTER SETTING THE CSR FLAG;
THE PDP-BA SETS STATUS AVAILABLE,

MR-11410

02/01Xd

{

NOTE:

RECORD NUMBER

HEAD NUMBER

0ZXd

HEAD/RECORD REGISTER — Address 05 [Disks Only]
BYTE COUNT REGISTER
— Address 05 [Tapes Only]

}

ALL BITS ARE READ/WRITE.

A AN

MR-6616

DRIVE TYPE REGISTER — Address 06

DRIVE TYPE

]

NOTE:

ALL BITS ARE READ/WRITE.

15—00

DRIVE TYPE REGISTER

‘

MR-6617

DX20
-147-

HEAD/RECORD
BYTE

COUNT

Address

[Disks

Only]

Address

[Tapes

Only]

This
register
is
used
interchangeably
with
address
25.
access
the
same
register.
Refer
to
address
25
description of the contents of this register.

addresses

DRIVE

TYPE

Bits

15-00

hardware
devices

Address

Type

type

code

drive
on

Drive

the

Massbus.

The

and

legal

halt

bits

drive

are

types

This
register
includes
the
differentiates the DX20 from other

that
The

also

are

microcode

set

checks the contents of the
not
correct,
an
error
code
is
(address
02).
Microprocessor
the

error

subsystem.

follows.

050060

DX20-V100

interfaces

with

TX02

tape

010061

DX20-V200

interfaces

with

RP20

disk

010052

DX20-v400

interfaces

directly

peripheral

Both
for

the

IBM

selector

subsysten.
IBM

360/370

channel

bus.

acting

15 I 14 1 13 1 12 i 11 ¥ 10 ¥ 09 I 08

NOTE:

STS

STATUS INDEX

1
[

REQ

ALL BITS ARE READ/WRITE.

15—08

ENDING STATUS

06—00

STATUSINDEX

ENDING STATUS

07
EXT

0ZXd

ENDING STATUS/STATUS INDEX REGISTER — Address 20

EXTENDED STATUS REQUEST
MR-6618

GENERAL PURPOSE REGISTER 01

— Address 21 (M8604-MC06) [Tape Only]

DRIVE STATUS

Disk Only

I
NOTE:

{

ALL BITS ARE READ/WRITE.

DISK ONLY: 15—08 DRIVE STATUS

07—-00 DRIVE NUMBER

DRIVE NUMBER

TX02 ADDRESS
L

DRIVE NUMBER
1

CODE + DENSITY

DATA MODE

Tape Only

07/

]

TAPE ONLY: 15-12 DATA MODE

11—08 CODE + DENSITY
07—-04 TX02 ADDRESS
03—-00 DRIVE NUMBER
MR-6619

-gv1-

ASYNCHRONOUS ADDRESS REGISTER — Address 21 (M8604-MCO06) [Disk Only]

DX20
-149ENDING

STATUS/STATUS

Bits 15-08
bytes.
Bit

request

Ending

Extended

the

DX20

bits

Status
27)
if

These

Request

microcode

(addresses 26 and
set
by
the
DX20
completion,

INDEX

Status

Address

change

The
the

host

indicating

update

extended

microcode

way,

status

updates

Bits

06-00

bits

Status

status

Index

table,.

DX20

this

status

the

Either

the

sets

DX20

progress.

allows

device

extended

the

extended

the

according to the status index.
a
sense
operation
is
performed

after

extended

include

the

These

The

select

setting

status

are
o6f

used

bits

information

status

registers

this

index

00-07

bit

registers

This bit is
at
command

clears
completed.

are

status

bit

into
the

specified

the
host

the

status

index
and
load
it
into
the
extended
status
registers
(addresses
26
and
27).
When the updates to the extended status
registers are completed,
the DX20 microcode
clears
the
extended
status request bit (bit 07).

Status

information

operation
status
may

not

sense

(bytes)

because

byte

the

correspond

operation

the

DX20

and

set

the

status

size

the

check

sense

the

setting

command
If

status
update

may

not

agree

being

set

Status

the

Sense
request

the

force

reset

bit

status

sense

the

ending
also

bit

performed

the

while

index

with

the

information

operations,

completion,

status

registers.

bit

bytes.

performed.

extended
field
and

this

unit

read

extended

due

being

microcode

the

DX20

status
updating

larger

the

than

table, the DX20 microcode will
the
extended
status
registers

index
the

clear
using

index
index 0.
After completing the extended status register updates,
DX20
sets
the
extended
status
request
bit,
which
indicates
completion of the updates.
the

NOTE

The

host

request

ASYNCHRONOUS

GENERAL

STATUS

PURPOSE

should

not

write

while

the

extended

bit

(bit

07)

into

Address

Status

Drive

(M8604-MCO06)

(M8604-MC06)

Disk Only:
Bits

Bits

Drive

07-00

status,

which

usually

the

Drive

Number

Only:

Bits

15-12

Data

Mode

Bits

11-08

Code

and

Density

The

number

drives

the

mode

data

Codes

and

Density

Indicates

follows.

Density

Mode

7-Track

508

7-Track
7-Track
7-Track

1412 bits/cm (556 bits/in)
2032 bits/cm (800 bits/in)
508 bits/cm (200 bits/in)

bits/cm

(200

bits/in)

0dd

7-Track

1412

bits/cm

(556

bits/in)

7-Track

2032

bits/cm

(800

bits/in)

9~Track

2032

bits/cm

(800

bits/in)

9-Track

4064

bits/cm

(1600

9-Track

15875

bits/cm

(6025

bits/in)

Drive
status.

Number

The

Parity

0dd Parity
0dd Parity
Even Parity
~

Even

Parity

'Even

Parity

NRZI
-

bits/in)

- TX02 Address - This address

asynchronous

drives

‘

used.

the

Mode
Set

02
03
05

03-00

being

for
,

Code

Bits 07-04

showing

status.,

Tape

Bits

Only]

end.

asynchronous

are

([Disk

[Tape

15-08

device

this

status

set.

GCR

is usually

number of

the

zero.
drive

showing

— Address 22 (M8604-MC06) [Disk Only]

_
H

DlSk Only'

IGN

MDE

DIA

coMm

SEN

DIS

. SEN

FOR

WHL

LEN

RET

Tape Only:

TRK

]

}

T
1

ARGUMENT
1

T
1

EXTENDED STATUS TABLE (NUMBER OF BYTES)

L
NOTE:

)

]

ALL BITS ARE READ/WRITE.

DISK ONLY:

SPARE BIT .

DISABLE SENSE

FORCE SENSE

DIAGNOSTIC MODE

WHOLE TRACK

COMMAND RETRY

07—-00

ARGUMENT

NOT USED

IGNORE LENGTH

MR-6620

0ZXd

FLAGS/ARGUMENT REGISTER

GENERAL PURPOSE REGISTER 02 — Address 22 (M8604-MC06) [Tape Only]

DX20
-151~

FLAGS/ARGUMENT
GENERAL

Disk

PURPOSE

(M8604-MC06)

Address

Spare

Bit

Ignore

bytes

for

into

with

584

bytes

the

- When set, record Lengths other than 576
bytes for TOPS-20) may be read or written
ignoring
length
records.
Records other
than

(2304

DX20

1long

(total)

and

verified

the

word

and

for

with

count

set.

TOPS-10

this

bit

the

(2312

set.

channel

Mode

Set

when

read

is
host

command

determined

that command
sets
this
bit.

never

retry

when

bit

set.

Bit

Not

Bit

Disable

unit

the

Sense

condition

this

bit.

Force

completion of
of unit check

Whole

Track
is

only

head/record

address,

the

this

bit

special

when

operate

command

reloaded

detected.
bit

sense

set

when

beginning
the

format,
formatted.

with

retry

the

This

entire
bit

-is

format

home

and

performed

used

the

issued,

with

25)

mode,
these
512-byte block

09)

the

record

read.

1including

for diagnostic

setting

the
bit
in

set

the

home
purposes

‘

07-00 - Argument
- For sense and no operation commands,
include
operations to be performed.
For read special

diagnostic
identifying the

when

(bit

purposes.

address.

starts

track,

bit

1is

dependent

read

the

operation

sense

diagnostic

operation

that

(addresses

the

sense

force
for

not

track

the

The

present

‘

Tape

Set

only.
Bits
bits

suppress

read
part

write
is

Sense

track

during

write

DX20

this command, which is
in the final status.

cleared,

the

can

count
when

The host clears this bit
asistance
is not needed.
DX20
microcode
continues

retry
The

Command

This

complete
is

met

used.

check

overrides

Bit

TOPS-20)

block

and

Bit
12
-~
Command
Retry
Set
by
the
assistance is asked for from the host.

The

for

This

must

Bit 13 - Diagnostic
in diagnostic mode.

Bit

Only]

Length

TOPS-10

formatted

Only]

[Tape

bit.

RH20

[Disk

(M8604-MC06)

Only:

Bit

- Address

these
macro

bits
contain the
control
byte
of microcode to be transferred.

Only:

Bit
15
table.

1Includes

the

number

bytes

the

extended

status

0ZXd
DRIVE NUMBER REGISTER.
GENERAL PURPOSE REGISTER 03

— Address 23 (M8604-MCO06) [Disk Only]
— Address 23 (M8604-MC06) [Tape Only]

09-

Disk Only:

02
1

DRIVE NUMBER
g

04
T

-¢ST-

TRACK IN ERROR
_

NOTE:

[

RTY

FES

Tape Only:

09
.

ALL BITS ARE READ/WRITE.

DISK ONLY:

15-08
07—-00

FUTURE USE
DRIVE NUMBER

TAPE ONLY:

15—-11
10

09
08

07-00

_
NOT USED
SUPPRESS EXTENDED STATUS

FORCE EXTENDED STATUS
RETRY

TRACK IN ERROR
MR-6621

DX20
-153-

DRIVE

NUMBER

GENERAL

Disk

Only:

Bits

15-08

Bits

07-00

address)

control

Tape

Only:

Bit

15-11
10

Address

Future
-

for

the

Bits

PURPOSE

(M8604-MC06)

Address

[Disk

Only]

(M8604-MC06)

[Tape

Number

operation

Not

Includes

defined

the

drive

number

function

code

extended

status
status

Bit

Extended

Force

status

from the
byte.
Status

When

TX02

When

set,

even

set,

causes

with

the

DX20

the

unit

gets

status
from
the TX02 on completion of
the operation.
normally gets Extended Status only if
the TX02
returns

Bit
the

bit

the

status

07-00

from

the

Track

TX02.

DX20

not

check

bit

extended

The
the

DX20
unit

automatically
:

retry

the

error

byte.

08 - Retry - When set, causes the
operation if there is an error.

Bits

(device
field

used.

Supress

extended
the TX02

check

Only]

to get
set in
09

use.

Drive
the

Error

The

DX20

writes

track

0ZXa
CYLINDER REGISTER

— Address 24 (M8604-MC06) [Disk Only]

GENERAL PURPOSE REGISTER 04 — Address 24 (M8604-MCO06) [Tape Only].
15

Disk Only: |

‘

]

INTERRUPT DRIVE STATUS

Tape On|y:
A

NOTE:

DESIRED CYLINDER NUMBER
L

]

INTERRUPT DRIVE NUMBER
1

]

-vSs1i-

;

ALL BITS ARE READ/WRITE.

DISK ONLY:
TAPE ONLY:

BITS 15—00 CONTAIN THE DESIRED CYLINDER NUMBER FOR THE CURRENT OPERATION.
15-08

[INTERRUPT DRIVE STATUS

07—-00

INTERRUPT DRIVE NUMBER
MR-6622

DX20
-155-

CYLINDER

GENERAL

Disk

PURPOSE

Address

(M8604-MC06)

Address

Only]

[Tape

number

the

Only]

Only:

Bits

15-00

have

the

needed

cylinder

operation.
Tape

Only:

Bits

15-08

the

Interrupt

Drive

drive

that

interrupted.

drive

coming

number

rewind

completed

Bits

([Disk

(M8604-MC06)

07-00

status

byte

Interrupt
that

goes

Drive

with

Status

These
bits
The interrupt

current

include
the
is caused by

on-line.

Number

the

for

These

interrupt.

bits

include
:

the

TX02

0ZXd

Disk Only:

]

HEAD NUMBER

]

RECORD NUMBER

00
-9G1-

— Address 25 (M8604-MC06) [Disk Only] *
HEAD/RECORD REGISTER
GENERAL PURPOSE REGISTER 05 — Address 25 (M8604-MC06) [Tape Only] *

BYTE COUNT

Tape Only:

)

{

*THIS REGISTER IS THE SAME AS THE HEAD/RECORD REGISTER (ADDRESS 05).
NOTE:

ALL BITS READ/WRITE.

DISK ONLY:

15-08

07-00

HEAD NUMBER

RECORD NUMBER

TAPE ONLY:

15-00

BYTE COUNT REGISTER
MR-6623

DX20
-157-~

HEAD/RECORD
GENERAL

Disk

Only:

Bits

15-08

number

for

Bits

07-00

head

for

Tape

Only:

15-00

These

operation.

These

the

expected

record

the

completion

record

operation,

Count

the

(M8604-MC06)

times

[Disk

Only]

(M8604-MC06)

[Tape

bits

include

the

correct

bits

include

the

Only]

head

operation.

Number

is
set

This

must
the

correct

set

2's

start

the

read

operation,

returned

the

this

2's

start

positive

complement

nondata
of

the

the operation is to be repeated.
At termination
includes 2's complement of the number of repeats not
(This register is the same as the head/record register

address

Address

Record

performed.
-

Number

current

Byte

transfer

this

Head

the

operation.

number

the

complement

length

PURPOSE

05.)

10
I

09
T

UPPER BYTE

LOWER BYTE

NOTE:

02
T

]

03
|

0ZXd

EXTENDED STATUS REGISTER — Address 26

ALL BITS ARE READ/WRITE.

EXTENDED STATUS REGISTER 01 — Address-27
15

]

-8

MR-6624

06
|

05
T

NOTE:

UPPER BYTE

LOWER BYTE
I

04
T

d—

]

ALL BITS ARE READ/WRITE.
MR-6625

DX20
-159-

EXTENDED STATUS REGISTER 0 - Address 26
This
the

status

table

returns

spare

information
to
the host
from
information from
the
extended

table.

The

depends

this

ending

status/status
index
information are returned to
byte being bits 15-08.
Index

status

status
in

the

index

(address
20).
reglster, with the

this

placed

the

Two bytes of
lower numbered

Contents

Sense

Bytes

and

Sense

Bytes

and

Sense

Bytes

and

Sense

Bytes

and

Sense

Bytes

and

Sense

Bytes

and

Microcode

MBI

Version

Registers

21
Number

and

MBI

Registers

and

MBI

Registers

and

MBI

Registers

and

MBI

Registers

and

MBI

Registers

and

CBI

Registers

and

CBI

Registers

Data

04 and 05
Registers 00 and

Path

Data

Path

Registers

and

21~

Data

Path

Registers

and

Registers

and

Data

Path

Last

Command

Diagnostic

Bytes

and

Diagnostic

Bytes

and

Diagnostic

Bytes

and

Diagnostic

Bytes

and

Sent;

Last

Device

Address

EXTENDEDiSTATUS REGISTER 01 - Address 27
This

host

from

the

extended

status

table

extended

placed

the

used

ending

Index

Contents

Sense

return

status

placed

spare

this

status/status

1ndex

Bytes

and

Sense

Bytes

and

Sense

Bytes

and

Sense

Bytes

and

Sense

Bytes

and

06
07

Sense Bytes 22 and 22
Microprocessor Status Register;
MBI Registers 02 and 03

MBI

Registers

and

MBI

Registers

and

MBI

Registers

and

MBI

Registers

and

Registers

and

Registers
Registers

02 and

CBI

Data

Path

Registers

02.and

03.

Data

Path

Registers

and

Data

Path

Registers

and
and

13
17

and

Data

Path

Last

Asynchronous

Diagnostic

Bytes

and

Diagnostic

Bytes

and

Diagnostic

Bytes

and

Diagnostic

Bytes

and

Address

the
-the

(address

index

20).

I/0

Bank

Select

DIAGNOSTIC

from
the

MBI

CBI

12
14

information

The

status

table.

Status;

Last

Asynchronous

Device

Bits
15-00
Instruction Register
- This
is a 16-bit
read/write
microcontroller register accessible from the Massbus control bus.

It
includes
instructions to be performed by the microcontroller:
Reading or writing operations depend on the contents of diagnostic
register
reset.

(bits

15,

and

12).

The

is cleared

)

0¢Xd

— Address 30

DIAGNOSTIC REGISTER O

MICROCONTROLLER INSTRUCTIONS

NOTE:

___J

)

ALL BITS ARE READ/WRITE.
MR-6626

DIAGNOSTIC REGISTER 01 — Address 31

IRE

gfm

Efim

]

PROGRAM COUNTER
{

-09T-

ALL BITS ARE READ/WRITE.

INSTRUCTION REGISTER ENABLE

MICROSTORE ENABLE

PROGRAM COUNTER ENABLE
PROGRAM COUNTER AUTOINCREMENT

13
12

11-00 -

PROGRAM COUNTER

MR-6627

)

DIAGNOSTIC REGISTER 02 — Address 32

1
NOTE:

]

NOTE:

ALL BITS ARE READ ONLY.

15—-08

B INPUTS
ALU

07-00

ALU A INPUTS

ALU B INPUTS
i

)

MR-6628

DX20
-161DIAGNOSTIC

Bit

allow

Instruction
the

Address

microcontroller

microstore.

With

instruction

this

Enable
to

bit

This

execute

set,

reading

bit
run

is
a

set

the

program

host

stored

writing

into

the

30)
from
the Massbus
control
bus,
register
being
loaded
from
the

results
in
microstore location
11-00) .
With this

being pointed to by the program counter
(bits
bit cleared,
reading the instruction register
from the control bus does not change the current contents of the
instruction register.
Writing into the instruction register loads

data
into
the
instruction
lines.
This bit is cleared

the

Bit

This

bit

cleared

writing

into

the

microstore.

Microstore

operation

set

and

Enable

prevents

and

instruction register
microstore
location
pointed

the

enable

from
the
Massbus
control
data
Register multiplexer
(address
30)

the

instruction

set

(and

this

bit

(bit

to by
the
bus
1lines

Program

program

counter

control

data

counter

(PC).

Counter

1lines

This

loaded,

the

write

host

bit.

1is

control bus write
cleared will

Program

When
are

control

1is

has

set

this

Counter

automatic

incrementing

microstore

enable

bit

cleared,

1location
This bit

set,

the

from

the

Massbus

the

program

typical

microprogram

before
starting
the
the microprocessor is

This

bit

must

cleared

Auto-Increment

this

instruction

This bit
the PC.

the

both

bit

write

during

effect.

the

bit,
or
the
to
set
this

operation.
not change

typical

When

microstore
register.

loaded

bus

host
loads
the
PC
not clear it.
Once

modify

enable
possible

when

Bit

the

can

microstore

11-00)

bit

execution,
because
the
microprocessor and does
before

Enable

(bits

during

during
15)

data

current
PC
is
loaded
via
the
Instruction

instruction
register
loads
ones
into
the
pointed to by the PC and 1nto the instruction
is cleared by DX reset.

Bit

bus

during
a
control
bus write
to
the instruction register enable is
a
control
bus
write
into
the

When
set),

bit

control

This

PC.

set,

cleared

bit

With

and

the

this

reset

set

bit

enable

allow

and

instruction

and

the

bit reset, control bus write operations of the instruction
register,
will
load
consecutive
locations
of
the
microstore
via
the Instruction Register without having to load the PC each time.
The PC
is
incremented
following a
read or
write
of
the
current

microstore
allowed

location.
When bit is cleared, the microcontroller
repeat the execution of an instruction.
This bit

cleared

Bits

11-00

Program

microcontroller
{CRAM) .

counter
cleared,

is
is

reset.

Counter

program

can

This

counter

written

enable
(bit
13)
This register
is

12-bit

used

into

from

address

the

1is
set
and
cleared by DX

includes.
the

the

Massbus

microstore

when

microprocessor

program

start

reset,

DIAGNOSTIC REGISTER 02 - Address 32
Bits 15-08 "A"
side
of
accumulator

being

read,

decoded

Bits

"B"

instruction
a

direct

07-00
side of

source
are

ALU
B Inputs =~
the ALU
which
registers.

ALU

octal

These

from

outputs,

instruction

multiplexer

bits

15-08

(address

and

buffer

(SROM

SROM

which

bits

inputs to the
of
the
elght

06-04

(address

30)

must

to
of

the
the

Inputs -~ These bits include the inputs
ALU which
are
received
from the output

input

determine

bits

the
one

accumulator

code.

07-00

decoding

which

the

multiplexer.

available

These bits include
are
received
from

determine

35)

outputs
and

these

.06,

bits

SROM

are

bits

the

15-00

source

(address

ROM,
30),

(address
36),
memory
register
bits
register bits 07-00
(address 36). To

being

address

selected

33)

read,
must

source
be

ROM

bits

decoded.

follows.

05
The

and

source

Source

Input

Multiplexer

Memory

Instruction

Buffer

SOURCE ROM OUTPUTS

NOTE:

ALL BITS ARE READ ONLY.

15-08
07—00

SOURCE ROM OUTPUTS
DESTINATION ROM OUTPUTS

_
T

DESTINATION ROM OUTPUTS

[

]

)

0ZXd

DIAGNOSTIC REGISTER 03 — Address 33

DIAGNOSTIC REGISTER 04 — Address 34

FUNCTION ROM OUTPU
TPUTS
i

NOTE:
15—08

07
06
05
04
03-00

IR P

PGO

BALU

PAR

ACC

PAR

SMX

INTERRUPT BITS
A

ALL BITS ARE READ ONLY.
FUNCTION ROM OUTPUTS

INSTRUCTION REGISTER PARITY
BALU PARITY GENERATOR OUTPUT
ACCUMULATOR PARITY
SOURCE MUX PARITY
INTERRUPT BITS 0300

‘MR-6630

-C¢91-

MR-6629

DX20
-163~
DIAGNOSTIC

Address

Bits

ROM

Outputs

15-08

(SROM)

Source

outputs

being

read

The

location

determined

of
by

the

source

the

following

ROM

instruction register bits:
IR15, IR14, IR13, IR09, and IR08.
eight outputs are determined as follows for a logical 01.
SROM7

-MA

EXT

SROM6

SMUX

SROMS5

SMUX

SROM4

BITS

-MOV

SROM3

MOV

INST

SROM2

SEC

SEL

SROM1

ALU

PAR

CHK

SROMO

IBUS

The

INST

Bits
07-00
Destination
ROM
Outputs destination
ROM
(DROM)
outputs
being
read
following
instruction register bits:
IR09,

The
location
of
is
determined
by
IR08,
IR12,
IRll,

IR10.

follows

The

eight

outputs

are

determined
:

01.

DROM7

WRITE

MEM

DROM6

WRITE

DROM5

MAR

INC

-MAR

DROM4
=

DROM3

= WRITE

DROM2

for

the

the
and

logical

OUT

PUSH/POP

DROM1

DROMO

DIAGNOSTIC REGISTER 04 - Address 34
Bits

15-08

Function

the
32
locations
determined by the
IR02,

IRO1l,

and

names

for

logical

FROM7

FROM6

CLK

ROM

Outputs

These

bits

indicate

which

of
the
function ROM
(FROM)
are
being
read,
as
following instruction register bits: IR14, IRO03,

IR00.

The

eight

outputs

use

the

following

logical

’

FROM5

FORCE

FROM4

-ALU

FROM3

-ALU

FROM2

-ALU

FROM1

-ALU

FROMO

ALU
M

Bit 07 - Instruction Register
instruction
register
parity

Parity - This bit indicates that the
was
read
from
the
microstore
or
depending on when
it was
read.
This

received
from the Massbus,
bit is cleared by DX reset.

Bit

BALU

Parity

parity

logic

and

outputs

ALU.

Bit

the

eight

the

ALU

diagnostic
for

ALU
04

input
Source

multiplexer.

the same
the

Parity

1input

A
-

bits

correct

was

clocked
reset.

for

Interrupt

interrupt
at

the

This

bit

being

the

(address
bits

this

feeds

the

generated

32,

bits

This

BALU

by the

for

one

07-00).
same

echos

parity

bit

bits
is

the

of
If

when

correct

parlty

for

source

07-00).

the

ALU

parity
32,

06-04)

bit

02 was

input

03-00

microbus

This

instruction

07-00).

Bits

diagnostic

parity

30,

read,

(address

the

bits

(address

MUX Parity

as when

Output

the

Accumulator

instruction

Bit

Generator

indicates

bit

(address

read,

bits

30)

the

bits

are

32,

bits

this bit

(address

shows

These

bits

1lines

(UBUS

INT

microprocessor

time

include

the

03-00).

state

T60

and

status
of
the
This
register
1is
is

cleared

NOTE:

ALL BITS ARE READ ONLY.

15—08
07-00

MEMORY LOCATIONS 0700

15—08

07—-00

Y
1

BUFFER REGISTER
1

[

ALLBITSARE READ ONLY.

INPUT MULTIPLEXER (07-—-00)

BUFFER REGISTER (07-00)

ALU
APE

ALU
BPE

’

ALU
ZBIiT

IRP
ERR

STK
OUF

NOTE:

ALL BITS ARE READ ONLY.

15
14

ALU CARRY BIT
ALU Z BIT

STACK OVER/UNDER FLOW

{

]

DIAGNOSTIC REGISTER 07 — Address 37
11
12
13
14
15
ALU
CRY

T
T
T
MEMORY LOCATIONS

e 63

INPUT MULTIPLEXER
L
NOTE:

T
]

BUFFERED ALU OUTPUT 07-00

DIAGNOSTIC REGISTER 06 — Address 36
5

T
T
T
BUFFERED ALU OUTPUT

-oT1-

0Z2Xd

DIAGNOSTIC REGISTER 05 — Address 35

‘

INSTRUCTION REGISTER PARITY ERROR

T
L

.
T

‘
T

MEMORY ADDRESS
g

)

1
10

ALU A PARITY ERROR
ALU B PARITY ERROR

09-00

MEMORY ADDRESS 09-00

MR-6632
00

MR-6633

DX20

DIAGNOSTIC

Bits

15-08

the

output

state.

Bits

This

07-00

output

the

working

the

Memory
of

memory

1024

(07-00)

the

cleared

Locations

(07-00)

working

from

BALU.

Input

Address

This

microprocessor

includes

T180

time

reset.

This

memory

(address

the

last

comes

Output

the

15-08

ADDRESS

ALU,

address

DIAGNOSTIC

Bits

ALU

one

memory

Buffered

locations

37).

The

includes

pointed

data

the

stored

1in

Multiplexer

.(07-00)
The
outputs
of
this
the source multiplexer
(SMUX).
The outputs
input multiplexer are the Ubus data register,
the
I/0 bank
register,
and
the
status
register.
The
Ubus
data
register includes the data strobed from the microbus data lines
on
the
last
DATI
instruction.
The
I/0
bank
register
is
used
for
selecting
different
microbus
interfaces
for
I/0
operations.
The
status
register
inputs
are
available
from
bits
15
and
14
in
diagnostic
register
7
-~
address
37,
and
from
bits
03-00
in

are

available

fed

from

diagnostic

into

the

address

reset,

34.

These

bits

are

cleared

Bits

07-00
Buffer
Register
(07-00) The
outputs - of
this
register
is
fed
into
the -source multiplexer
(SMUX).
The buffer
register is loaded from the BALU at microprocessor time state T30.
This register can be used for a "rotate right" operation under the
control

0l.

This

DROM
(diagnostic register 03 - address
register is cleared by DX reset.

33)

bits

and

DIAGNOSTIC REGISTER 07 - Address 37
Bit

ALU

from

last

Carry Bit - When set this bit indicates a carry takes
the most significant bit of the ALU as
a result of the
instruction with an arithmetic ALU function.
This bit
cleared by DX reset.

place

Bit

move

14
-

from

ALU

move

Bit

This

instruction

comparison

ALU

complement

the

and

Bit

the

1's
B

the

inputs

Instruction

Bit

stack

Stack

This

(too

bit

within

[bits

15-08])

Bit

ALU

the

side

the

I/0

made.

Parity
ALU

when

all

bit

Parity

ALU.

has

Set

even

side

ALU
of

Parity

the

ALU

used

ALU
in
the

comparison

reset.

the

parity.

input

This

bit

Flow

- Set when the hardware detects a
or
a
stack
underflow
(too many
reset or SP reset.
SP reset
is a
register (diagnostic register 06 - address

the

microprocessor

Error
have

This

bit
even.parity.

Error
have

This

bit

even parity.

reset.

sets.

set

This

when

bit

This

loaded

the

inputs

cleared
‘

set

This

)

Bits 09-00 - Memory Address address
for
selecting
one
of
locations.
This
is cleared
by DX

the

placing

when

the

bit
By

pushes)

reset.

Bit

magnitude

cleared

Error

30)

output

The

the

1s.

mode,

(address

many

reset

bank

set
to

inputs

This

which

the

subtract

Over/Under

overflow

equal

and

the instruction register
is cleared by DX reset.

pops).

bit

the

when

bit

the

inputs

cleared

to
DX

10-bit
register
includes
the
(1024 decimal)
working
memory
in

two

bytes

from
:

the

BALU
'

and

(4)

(8)

EQUIPMENT

INTERVENTION| BUS OUT

COMMAND
REJECT
.

1 | NOISE

REQUIRED

CHECK

STATUS A

STATUS B

OVERRUN

SELECTED &

CHECK

7-TRK

LOAD POINT | \wi sTAT

IN
CK

END DATA .
JCRC

ENV CK/

NEW
SUBSYSTEM

WTM
CHECK

*% | IDBURST
CK

*| PARTIAL
**| START
READ CHECK | RECORD

)
DUAL

* % ¥

* ¥

6
7
8

9
10

*% I WRITE

7-TRK

CURRENT

* %

WRITE TRG

VRC

DENSITY TU

NOT

1600

FAIL

IBG

6250

*%%{ VELOCITY

| DETECTED

CORRECTION | CHANGE

CMND STAT
#=*
|REJECT

CHANNEL **

BUFFER CK

CRcll

RECORD NOT
DETECTED

| C/P COMP.

6250 _
L

!
2
3

RPQ

4
5

6
wxxl
LOAD
FAILURE
TCU

TACH START
*%
FAIL

BYTE
[
T

** RPQ
*%| POSTAMBLE
ERROR

ERASE HD *%#|
FAILURE

TAPE UNIT MODEL IDENTIFICATION

*%%| DSE
FAILURE

RESET
RIGHT COL.
COLUMN #*#*#*| LEFT.COL.
*x%x | KEY
*%% | FAIL
FAIL
TOP OR BTM

NOT

TU
CHECK

FILE

LWR

REJECT TU

\S/|I<R%W

GHECK

BACKWARD

ERROR

(1)

PROTECTED | CAPABLE
ERROR

BPI

SKEW

R/W VRC

ZERO

1600
IN TU
SET

MTE/LRC

(2)

WORD COUNT gg;een-r

DATA

CHECK

TRACK

(4)

(8)

(1)

(2)

RESERVED

VELOCITY *¥|
CHECK

XLOL/X0XL

[
T

°
‘

11
MR-2309

991~

;

BYTE

CONTROL UNIT UNIQUE IDENTIFICATION (HI-ORDER PART S/N)
4096
:
.
1024
12
|

128

4096

128

SAME

TUG

TUF

TUE

512

256

I.D.

[

TU
|§

TUS

TU 4

TU 3

]

TU 2

TUC

LEVEL

1
17

|
]

TU1

BUSY STATUS, HI-ORDER TAPE UNITS

TUD

E.C.

BUSY STATUS, LO—ORDER TAPE UNITS

TUO

TUB

TUA

TU9

TUS

22
23

)

.
1

[

]

MOD IV

TCU

“REFER TO MICROPROGRAM PAGE QA025"
1

“REFER TO MICROPROGRAM PAGE AQ025"

}

BYTE

T
*

REFLECTS TCU DIAGNOSTIC RELEASE LEVEL
'
|
:

TU7?

|
T

SWITCH FEATURES

1024

256

TAPE UNIT UNIQUE IDENTIFICATION (LO—ORDER PART S/N)

FEATURE

(8
,

TXO01 ONLY

TX02 ONLY

(4)

(2)

(1)

BYTE

(8)

(4)

(2)

(1)

i
T

*%%

TU72 ONLY

MR-2310

XLOL/X0XL

TAPE UNIT UNIQUE IDENTIFICATION (HI-ORDER PART S/N)

8192

2 CH SW

CONTROL UNIT UNIQUE IDENTIFICATION (LO—ORDER PART S/N)

-L9T-

CU FEATURES

CHECKS/ADJ

Table

Contents

Title
RH20

Mass

When

DMA20

Fail

Adjustment

Page
o.0..oolo...

.0'.‘0.oo...

DeSkeW...............o-.

ooc.o.t.coc.

.....-....-.....-.......

Clock

Deskew

Data

Warning

Procedure...............
.............
Adjustment..............
.............
Adjustments.............
.................
MF20/MG20 Deskew Proced
ure.....................
.........
Troubleshooting.........
........................
........
DMA20

TU7x

..loz

.......-.2

Pneumatic

ceeesall

CHECKS/ADJ
-2

RH20 MASS FAIL ADJ

Attach channel 1 probe to appropriate pin for RH20

being

adjusted.

RH20 #

PIN #

0
1
2
3
4
5
6
7

2F34T2
2F31T2
2F28T2
2F25T2
2F22T2
2F19T2
2F16T2
2F13T2

r on appropriate M8555 one
FAIL potentiomete
Adjust MASS the
point at which it goes low.

turn beyond

ments of fault correction of power supplies
when doing theadjust
lelowing modules, check the appropriate deskews.

WHEN TO DESKEW

to
related

MODULE

LOGIC

ASSY.
CcPU

Bay

REPLACED

DESKEW

M8526 - CLK CPU Clock Module

DMA20,

M8519 - MEM (Slot 07) SBus

DMA20, All MA20s,

All MAZ20s,

All MB20s, All RH20s
All

MB20s

M8516 - TRN (Slot 06) E & C

All

RH20s

M8562 - MA20 Timing Module

MA20

M8561 - MA20 Control Module

MA20

Translator

Bus Translator

MA20

SBus Cable
DMA20

M8563 - DMC Adapter Interface

DMA20

DMA20 Board Two

M8560 - DTR DMA Timing and

DMA20

g Bus Transceivers
MB20

gBus Cable
MB20

M8565

MB20 Timing Module

MB20

M8568

MB20 Control

MB20

Module

MB20

SBus Cable
1/0

BAY

M8559 - CDS I/0 Bay Clock

All

Distribution Module

M8556-DP

RH20 Data Path

RH20

RH20s

CHECKS/ADJ.

RH20

DESKEW

EQUIPMENT

PROCEDURE

REQUIRED

Tektronics

475

identical

probes

ALL

are

equivalent

and

short

ground

(100

MHz)

scope

clips.

with

OBJECTIVE
RH20s

deskewed

channel

time

zero,

Recheck

skew

whenever

the

CHTO.

MBox

clock

cable

that

produces

NOTES

replaced.

The

adjustments

potentiometer

is
ADJUSTMENT

for

RH20

are

#1,

the

CBus

made

for

RH20

the

#0,

etc.

M8559

the

M8556

module.

second

module

The

top

potentiometer

PROCEDURE

Attach

probe

(either

ext,

4B0O9K1.

Sync

positve

Attach

sync

channel

CHTO

external.

channel

probe

MTR

MBOX

CLK

4D33p1.

Push

TRIGGER
VIEW
and
verify
that
the
MBOX
CLK
occurs just prior to
CHTO can be seen on the
scope.
diagram below.

CHTO

(EXT.SYNC.)

that
See

MTR MBOX CLK H

(CHANNEL 1)
DP4 CLK H

(CHANNEL 2)

—_J—_]_I—l__

_JL
MR-2266

Attach

channel

being

deskewed.

NOAYUT
R W N
O

RH20

‘Align

this

probe

See

appropriate

chart

clock

for

RH20

MBox

clock

that

before

CHTO.

below.

2A36D2
2A33D2

2A30D2
2A27D2

2224D2
2A21D2
2A18D2
2A15D2

clock

occurs

pulse

approximately

for

all

RH20s

channel
10

that

with

the

nanoseconds

are

installed.

CHECKS/ADJ.

MA20/MB20 DESKEW PROCEDURE

lent (100 MHz) scope with
Tektronics 475 or equivaground
clips.

EQUIPMENT REQUIRED

identical probes and short

OBJECTIVE

and
To assure proper clock alignment between KL10

MA20/MB20 controller.
NOTES

Type a MR and then a FX1 to

gSelect CRO on the KLI1O.
turn on the clock.

1is
arranged so that A clock
The M8562 delay lines rare and
B clock 1is the bottom
the top potentiomete
potentiometer.

l sync or channel 3) to A
Attach a probe (either externa
trigger
CHANGE COMING L, 4E22F2. Set scope for external

ADJUSTMENT PROCEDURE

and negative edge.

MBOX CLK C, 4D33Pl. Use
Attach channel 1 probe to MTR
that the ground reference is

such
0.5 V/CM and set scope ine.
1.3 V above the centerl

of
Press TRIGGER VIEW and observe that the relationship to
MTR MBOX CLK C to A CHANGE COMING L corresponds
diagram below.
CLK FREE

CTL2ACLKDLY L

A CHANGE COMING L
{CPU E22F2)

CTL2 APHSCOM FREE L
{(MF20 D0O5D1)

CTL2BCLKDLY L

MR-2005

of the first A phase clock
Set the leading edge
the scope screen.

on the

first division on

to be
Attach channel 2 probe to pin 5D26Al in memory
aligned.
or M8565 in
iometer on the M8562
Adjust the top potentso
leading edge 50% point
slot 1 of the memoryg edgethat503thepoint
A phase
MBox
of
crosses the leadin
,
clock.
memory to
Connect channel 2 probe to pin 5D26K1 in the
be aligned.
or M8565 in
iometer on the M8562
Adjust the bottom potent
leading edge 50% point
slot 1 of the memoryg SOedgethat50%thepoint
B phase
MBox
of
crosses the leadin
clock.

Connect channel 2 probe'to pin 5D29Al in the

memory to

be aligned.

alignment described above. slotAdjust
Perform the A phase
54.
the top potentiometer of the M8562 or M8565 in
mamory to
Connect channel 2 probe to pin 5D29K1 in the
be

aligned.

Adjust
alignment describedor =2bove.
Perform the B phase
M8565 in slot
iometer of the M8562
the bottom potent
MB20
or
MA20
one
focr
54. This completes the adjustments
unit.

cal.

For additional memory boxes the orocedure is identi

CHECKS/ADJ

DMA20

CLOCK

EQUIPMENT

DESKEW

PROCEDURE

REQUIRED

Tektronics

identical

475

probes

equivalent

and

short

ground

MHz)
clips,

performing

clock

FX1

deskew

procedure

(100

scope

with

OBJECTIVE
assure

then

type

under

turn

running

the

clock.

type

not

and

check

deskew

pProcedure

type

check

deskew

program.

NOTES

Before

performing

then

type

under

ADJUSTMENT

FX1

clock

turn

running

deskew

the

clock.

program

not

and

PROCEDURE

Attach

a probe
(either external sync or
channel 3)
to
COMINL,
G
4E22F2.
Set sync for negative edge,.

CHANGE
Attach

channel

0.5

V/CM

1.3

Attach
Use

and

V/CM

positive
clock

clock

phase

clock

tick.
tick

Adjust

DL2

from

the

top)

channel

until

which

crosses

the

edge

M8560

centerline

phase

MBox

MTR MBOX CLK
A CHANGE

COMING L

1AQ2R2.

the

ground

occurs

phase

after

clock.

clock

tick

The

the

1AF03
(it
is
the
4th
leading edge of the clock
by

the

same

channel

this

time

|B|

adjustment

the

leading

DIAGRAM OF CLOCK “A” AND. "B PHASES
MR-2254

Adjust

DL3

delay)

until

the
the

affected

the

this

same

time

channel

Connect

leading

slot

edge

adjustment

1AF03

(it

the

clock

crosses

the
B

the

leading

edge

DTR3

125

the
which

centerline

phase

MBox

top
is
at

clock

’

channel

Adjust

M8560

CLK

1DO3Fl.

DLl

on the M8560 in slot 1AF03
(it is the bottom
delay)
until the leading edge of the
clock on channel 2
which is
affected
by
this
adjustment
crosses
the
centerline

phase

Connect

Adjust

DL4

delay

from

the

clock

time

DL5

the

top)

completes

the

leading

CLK

affected

same

time

channel

the

leading

edge

1D0O3L2.

M8560
until

slot

the

1AF03

leading

(it

edge

is
of

this

delay

crosses

the

leading

edge

the

phase

MBox

adjustment

from

Adjust

the

DTR3

channel

delay
at

time

channel

on
the M8560
in slot
1AF03
(it
is
the
2nd
the top)
until the leading edge of the clock
affected by this delay crosses
the centerline

same

which
clock

This

the

clock

channel
2

which
at

MBox

slot’

the

affected

POINT,

that

which

the

clock

IAI
—'l

the

DESKEW
such

Use

reference

The
second
clock
tick
after
the
another A phase clock tick,
etc.

the

CLK

4D33P1.

ground

centerline.

pulse

low

after

CLOCK,

the

Scope

the

clock

goes

tick

MBOX

that

DMC2

below

delay
on

MTR

adjust

MBox

COMING

second

probe

and

1.5

CHANGE

phase

probe

scope such
centerline.

the

channel

0.5

reference

The

set

above

DMA20

clock.

the
the

3rd
clock

centerline
phase

MBox

CHECKS/ADJ

DMA20 DATA WARNING ADJ

lent (100 MHz) scope with
Tektronics 475 or equivaground
clips.

EQUIPMENT REQUIRED

identical probes and short

OBJECTIVE

for
The KL10 use DATA WARN as well as READ RESTART ent
memory reads. This procedure assures correct alignm
of

NOTES

these pulses.

assuming
be done in 4-Bus Mode,
This procedure should les
of 4 memories. This general
the system has multipr, work
in any bus mode.
procedure will, howeve

G SLOW
up to return DATA WARNIN
The memory must be setonly.
No other combination 1is
and ADDRESS ACK (NT) ‘
legal!

small loop which
4-Bus Mode doing abus,
Set up the DMA20 in memory
such as:
on a given

ADJUSTMENT PROCEDURE

reads from only one

10/ MOVE 0, 100
11/ MOVE 0, 101
12/ MOVE 0, 102
13/ MOVE 0, 103
14/ JRST 10

(200000 100)
(200000 101)
(200000 102)
(200000 103)
(254000 10)

‘put channel 1 probe on KBus n DATA WARNING.
KBus
KBus
KBus
KBus

1C05D1
1C07D1
1C09D1
1C11D1

0
1
2
3

put channel 2 probe on KBus n RD RS.
KBus 0
KBus 1

1C05J1°
1C07J1

KBus 3

1c11J1

1c09J1

KBus 2

sync on channel1 going negative.

l 1)
that DATA WARNING (on channe
Adjust each memory suchMHI10s
to
295 +5) nanoseconds prior
occurs (MGlo0s 260 $5)
1in the
adjustment is done
RD RS (on channel to2). theThis
delay
for
set
print
memory
Refer
memory.
being
locations for the specific type of memory
adjusted.

to be adjusted,
controllers are select
I1f more than four memoryJjust
the next
adjusted and
deselect the memories Rerun
and adjust the
m
progra
the
boxes as low core.
next memories.

delay
Adjust the appropriate M8591 for the port - top

potentiometer.

MG10/MH10
Port

-0

1
2
3
4
5
6
7

Loc

KL39

KL32
KL38
KL31
KL37
KL30
KL36
KL29

CHECKS/ADJ.
-7-

PNEUMATIC ADJUSTMENTS

THREAD MODE
ALL MODELS

ITEM

TUBE

COLOR

RED

RESTRAINT

BLUE

RT THD CHAN

YELLOW

LOWER

RESTRAINT
UPPER

”

107 -12

V' | purpPLE

LT THD CHAN

YELLOW

REEL

15°"

20"

30’

6
BLUE

VACUUM

5" "6’
-6

[

JET

THD CHAN

AIR

EASY

LOAD

Rep

19"

’

- 17
-

oare

- 21

RUN MODE TU70

ITEM

TUBE
COLOR

v/P

Tu70

PURPLE
RT UPPER AIR

BEARING

RT GU IDE

LT GUIDE

RT LOWER AIR

BEARING

LT LOWER AIR

BEARING
'

48"

10
GREEN

44"

|10

40" - 60"

BROWN

CLEAR

”

- 48

174

”

43" -53

GREEN

-53

-6

BLOCK

. ”

PINK

;

TAPE CLEANER

347 - 35

40" - 42

5 -8 — ADJUST SO

THAT TAPE SEALS TO

BLACK

CLEANER BLOCK WITH

MINIMUM VACUUM.

RUN MODE TU72

| TEM

COLUMNS
:

RT UPPER

VP |

TUBE
coLor

PURPLE

33" . 35"

PINK

48" - 53

AIR BRNG
RT LOWER

AIR BRNG

CLEAR

GREEN

LT GUIDE

REGWN

AIR BRNG
CAPSTAN

CLEANER
BLOCK

48 ;53
607

-70

GREEN

-42

—

TAPE

r”r "

RT GUIDE

LT LOWER

TU72

|10
|
BLACK

”

.19

5” . 6" — ADJUST

FOR TAPE SEAL AT
MINIMUM VACUUM .
MR-2314

CHECKS/ADJ.

MF20/MG20 CLOCK DESKEW PROCEDURE

The following equipment is required.
1.
2.

Oscilloscope - Tektronix 475 or equivalent

W9025, 12-inch extender module
,

Alignment tool

Clock Check Procedure
NOTE

‘

This is not a deskew procedure. If the
requirements of this check are not
_ satisfied, the deskew must be performed
as described in the Clock Deskew

Procedure below.

‘channel 1 and channel
Set oscilloscope to 1lv/div for both
Load the KL1O microcode.
2. Set sweep rate to 20 ns/div.
the
gelect full clock rate and source the clock from (CRO,
master oscillator at 30 MHz. Sstart the microcode
FW72/3,

CS2,

SM).

in the CPU bay (signal A
pPlace probe 1 on pin E22F2 the
clip on a ground pin.
CHANGE COMING L) and place
MF20/MG20 (signal CTL2 A PHS
place probe 2 on pin D5D1 in clip
on a ground pin. Sync
the
place
and
coM FREE L)
l.
internal on channel 1. These signals must be identica
C5M2
pin
at
Move probe 1 from CPU bay to MF20/MG20 the clip on
a
(signal CTL2 B PHS COM FREE L) andto place
with
1
add channel
ground pin. Set the oscilloscope d must
ly
perfect
be
observe
m
2. The wavefor
channel
'
time.
symmetrical with respect to ON/OFF

Clock Deskew Procedure
l.

the M8576 on the
power down the MF20/MG20 and place
all the way clockwise.
extender. Rotate the two switchesmicrocod
e, master reset
Restore power and load the KL10 clock rate
(CRO), and
the machine (MR), select full
MHz.
source the clock from the master oscillator at 30
Now start the microcode (SM).

e external sync on pin
Place the probe for the viewabl
A CHANGE COMING L) and place the
E22F2 in CPU bay (signal pin.
ground clip on a ground

external

sYnc

trigger

Select negativ
’
oscilloscope.
probe 2 on
place
and
M8576
the
put the dip clip on EB86 of
clip on pin

E86 pin 5 (CT A CLK DLY L). pPlace the ground
l.

place probe 1 on E86 pin 9 of the M8576 (CLK FREE) and

ground clip on pin 16,

of CLK FREE
Vview external sync and locate A phase tick
-going pulse after the
(probe 1). It is the first positivelow.
L goes
CPU signal A CHANGE COMING

define the
Having 1located the A tick of CLK FREE,
X tick. Define the
positive .pulse before A tick to be tick.
Y
positive pulse before X tick to be

-going edge
Rotate the bottom switch to align the negative-going
edge

the negative
of CT A CLK DLY L (probe 2) with optimal
setting is not
of Y tick (probe 1l). If this
of CT A CLK DLY L must
edge
-going
possible, the negative
ng range: after the
be aligned within the followi
positive-going edge of Y tick and before the
positive-going edge of X tick.

E86 pin 6. Rotate the
Move probe 2 from E86 pin 5 to -going
edge of CT B CLK
upper switch to align the negative ve-goi
ng of A tick
edge
DLY L (probe 2) with the negati
possible, the
not
1s
setting
(probe 1). If this optimal B CLK DLY L must
be aligned
negative-going edge of CT after the positive-going
edge
within the following range:
of A tick and before the positive-going edge of the pulse
following A tick.

CHECKS/ADJ.
-9-

10.

11.

Semi-Final

check

place

and

should

Final

Check

CHANGE

- Remove probe 1 from pin 9 of E86
and
5.
The waveforms observed on channels 1
logically opposite to each other.

the

scope,

from

the

EXT

Now

remove

dip

probe

COMING

internal
the

on
clip

channel
and

E61

place

the

move

dip

(signal

MF20/MG20) and place the ground
signals should
be identical.

MF20/MG20

No.

JUMPERS

Pin to Ground Connections
A4L1
A4M1
A4N1
NC

GND

the

SYNC

clip
A

probe
to

the
on

PHS

clip

monitoring

CHANNEL

probes

E6l.

Put

COM

FREE

16.

E61

Sync

attached
channel
[

to
2
in

These

TROUBLESHOOTING
-11-~

KL10

TROUBLESHOOTING

FLOWCHARTS

INTRODUCTION

These

flowcharts

were

engineer.

KL10-based

system

order

causing

shows

isolate

produced

the

that

steps
is

the

that

help

guide

should

experiencing

failing

Field

the

Field

performed

intermittent
Replaceable

intermittent

Service

debug

crashes.

Unit

‘

(FRU)

which

error,
two basic steps must be taken.
They
are
data
collection,
and
decoding
of
this
data.
These
flowcharts
describe
a
logical
sequence
of
steps
that
can
be
followed to collect and decode data.
Data

Collection

Data

collection

about

Due

data
the

portions

gathering

the

from

number

information

In this portion
This
symbol
is

experienced.

zZero.

that

closed
and

which

data

previously

call

the

old

hard-down

Decoding

use

her

information"

that

how

the

error.

to
to

collect
collect

KL10

assumed

that

may

and

not

into

DEC

the

Service,

particular

This

confused

the

readily
that

occur

available

Maintenance

that

solved.)

ensures

with

data

errors.

1logged

data

expertise
(the

been

problem

involved

©perceive

has

unrelated

the

tools

Site

Management

available

engincer

will

during

data

such

anyone
nolve

collection,

diagnost fos

Guide).

the flow uses the "tables",
sections
of
this
manual.

from

crashes

done

where

interpreted

will be times when escalation
reflected in NOTE 1 of the flow.
as

now

and

"maps",
and
"general
Data
that
has
been
acted

possible.

There

escalation

with

about

Data

portion

selection

deal

possible

everyone

call

new

should

it.

situation

manual

collected

the

for

any

This

means

for

his

sedquence.

customer

collected

needs

this

collected

who

using

flowcharts

errors,
it
is
best
crashes.
It is important

logical

initiated

All
data
collected
Guide.
This ensures

and

the

information

intermittent

the flow you will find many references to
(N).
equal
to
the
number
of
crashes
the
system
has
Whenever
a
call
has
been
closed,
(N)
is
reset
to

management,

problem

much

nature

defined

upon.

FRU

a problem is needed.
This
This note pertains to support

the Action

Outage

policy.

TROUBLESHOOTING
-13-

HAVE
YOU SET

NO RELOAD,

YOU HAVE

THE SYSTEM

CHECK FAULT
INDICATOR ON

FRONT OF
FE CAB

SET

RELOAD

SAVECTY
PRINTOUT
IN

UNDER PARSER
2.

LOG
TAKE/SAVE

SYSERR
3.

RECORD TIM¢

RECORD
HUMIDITY

INVESTIGATE

AND RECORD
ANY POWER OR

LOOK AT 863
FAULT INDICATORS
AND FIX PROBLEM

KLAD PACK
IS DRIVE
READY