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EK-TWU16-MM-001

December 1975

208 pages

Original

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Document:	TWU16 Magnetic Tape Subsystem Maintenance Manual
Order Number:	EK-TWU16-MM
Revision:	001
Pages:	208
Original Filename:	EK-TWU16-MM-001_TWU16_Magnetic_Tape_Subsystem_Maintenance_Manual_Dec75.pdf

OCR Text

EK-TWU16-MM -001

TWU16
magnetic tape subsystem
maintenance manual

digital equipment corporation • maynard. massachusetts

1st Edition, December 1975

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no
responsibility for any errors which may appear in
this manual.
Printed in U.S.A.

This document was set on DIGITAL's DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL
UNIBUS
DEC US

PDP
FOCAL
COMPUTER LAB
MASSBUS

CONTENTS
Page
CHAPTER 1

SYSTEM AND PHYSICAL DESCRIPTION

1.1
1.1.1
1.1.2
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.2.6
1.2.6.1
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.4
1.4.1
1.4.2
1.4.3
1.5
1.6
1.6.1
1.6.1.1
1.6.1.2
1.6.2
1.6.2.1
1.6.2.2
1.7
1.7.1
1.7.2
1.7.3

GENERAL . . . . . . . . . .
Scope
........ .
Related Documentation
BUS INTERFACES
Unibus .
Massbus
Slave Bus
RH70 to Cache Interface
Main Memory Bus
Unibus to Cache Interface ..
CPU to Cache Interface
PDP-ll/70 CENTRAL PROCESSOR SYSTEM
PDP-II Central Processor
Cache Memory, Main Memory . . . . . .
Unibus Map
....... . .... .
RH70 Massbus Controller . . . . .
TUI6/TM02 Tape System . . . . . . .
RH70 FUNCTIONAL OPERATION
Register Access Control Path
DMADataPath
...... .
. . . . .
Data Transfer Rates . . . . .
MAGNETIC TAPE FUNDAMENTALS
..... .
TUI6/TM02 RECORDING TECHNIQUES
.... .
NRZI (N on-Return to Zero - Change on a 1) . .
Definition
..... .
Format . . . .
Phase Encoding (PE)
Definition
Format . . . .
TWU16 SPECIFICATIONS
Data Format . . . .
TUI6/TM02 SpeCifications
RH70 Massbus Controller SpeCifications

CHAPTER 2

MASSBUSINTERFACE

2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.5
2.6

GENERAL . . .
DATA BUS
CONTROL BUS
COMMAND INITIATION
Non-Data Transfer Commands
Data Transfer Commands
READING/WRITING DRIVE REGISTERS
MASSBUS PHYSICAL DESCRIPTION

CHAPTER 3

OPERATION AND PROGRAMMING

3.1
3.2

GENERAL ..
DEFINITIONS . . . . . . . . . . . .

1-1
1-1
1-2
1-2
1-2
1-2
1-3
1-3
1-3
1-3
1-3
1-4
· . . .. 1-4
1-4
. . . . .. 1-4
· . . .. 1-5
. . . . .. 1-5
1-5
1-7
1-7
1-7
1-7
1-10
1-10
1-10
1-10
1-10
1-10

1-11
1-11
1-11
. 1-11
1-12

2-1
2-1
2-1
2-4
2-4

· . . ..

2-4
2-4
2-5

3-1
3-1

iii

CONTENTS (Cont)
Page
3..3
3.4
3.5
3.5.1
3.5.2
3 ..5.2.1
3 ..5.2.2
3 ..5.2.3
3.5.2.4
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
3.6.8
3.6.8.1
3.6.8.2
3.6.9
3.6.9.1
3.6.9.2
3.6.10
3.6.11
3.6.12
3.6.13
3.6.14
3.6.15
3.6.16
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.8

3-4
INTERRUPT CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TERMINATION OF DATA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . .. 3-4
TWU16 COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3-6
Non-Data Transfer Commands . . . . . . . . . . . . . .
3-6
Data Transfer Commands
...........................
3-7
Write Data Transfer
...........................
3-8
Read Data Transfer
Write-Check Data Transfer . . . . . . . . . . . . . . . . . . . . . . . .
3-9
3-9
Data Transfer Rates . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
REGISTER DESCRIPTIONS
Control and Status 1 (MTCS1) Register (772440) . . . . . . . . . . . . . . . . . . . 3-9
Word Count (MTWC) Register (772442) . . . . . . . . . . . . . . . . . . . . . . .. 3-9
Bus Address (MTBA) Register (772444) . . . . . . . . . . . . . . . . . . . . . . . . 3-9
. . . . . . . . . . . . . . . . . . . . . . . 3-13
Frame Count (MTFC) Register (772446)
Control and Status 2 (MTCS2) Register (772450) . . . . . . . . . . . . . . . . . . . 3-14
Drive Status (MTDS) Register (772452) . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Error (MTER) Register (772454) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Attention Summary (MTAS) Register (772456) . . . . . . . . . . . . . . . . . . . . 3-25
Setting the Attention Active (AT A) Bit . . . . . . . . . . . . . . . . . . . . . 3-26
Clearing the Attention Active (AT A) Bit . . . . . . . . . . . . . . . . . . . . . 3-26
Character Check (MTCC) Register (772460) . . . . . . . . . . . . . . . . . . . . . . 3-27
CRC Character Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
Dead Track . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
Data Buffer (MTDB) Register (772462) . . . . . . . . . . . . . . . . . . . . . . . . 3-28
. . . . . . . . . . . . . . . . . . . . . . . 3-29
Maintenance (MTMR) Register (772464)
. . . . . . . . . . . . . . . . . . . . . . . 3-34
Drive Type (MTDT) Register (772466)
. 3-34
Serial Number (MTSN) Register (772470) . • . . . . . . . . . . . . . . . . .
. 3-34
Tape Control (MTTC) Register (772472) . . . . . . . . . . . . . . . . . . .
. 3-34
Bus Address External (MTBAE) Register (772474) . . . . . . . . . . . . . .
Control and Status 3 (MTCS3) Register (772476) . . . . . . . . . . . . . . .
. 3-34
PROGRAMMING EXAMPLES
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
Write Data Transfer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
Read Data Transfer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
Space Operation .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
Tape Mark Operation
SUGGESTED ERROR RECOVERY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43

CHAPTER 4

TWU16 COMMAND REPERTOIRE

4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.]0

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
REWIND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
ERASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
PE DATA READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
NRZ DATA READ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-6
PE DATA WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
NRZ DATA WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4-9
WRITE TAPE MARK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ERRORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

CONTENTS (Cont)
Page
CHAPTER 5

THEORY OF OPERATION

5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.3.1
5.3.1.1
5.3.1.2
5.3.1.3
5.3.2
5.3.2.1
5.3.2.2
5.3.3
5.3.3.1
5.3.3.2
5.3.4
5.4
5.4.1
5.4.2
5.5
5.5.1
5.5.2
5.6
5.6.1
5.6.2
5.7

GENERAL . . . . . . . . . . . . . . . .
REGISTER ACCESS CONTROL PATH
Writing a Local Register
Reading a Local Register .
Writing a Remote Register
Reading a Remote Register
DMADATAPATH
..... .
Data Buffer Maintenance Operation
Writing the Data Buffer During Maintenance Operation
Reading the Data Buffer During Maintenance Operation
Parity Generation/Checking During Maintenance Operation
Write Commands (Data Buffer Operation)
Incremented Memory Addresses .
Decremented Memory Addresses . .
Read Command (Data Buffer Operation)
Incremented Memory Addresses DUring Read Operation
Decremented Memory Addresses During Read Operation
Write Check Command (Data Buffer Operation) . . .
RH70/CACHE INTERFACE . . . . . . . . . . . . . . . . .
Write or Write-Check Operation (Read from Memory)
Read Operation (Write Into Memory) . . . . . .
WRITE COMMAND FLOW DIAGRAM DESCRIPTION
RH70/Cache Interface Flow . . . . . . . . . . .
................. .
Massbus Flow
READ COMMAND FLOW DIAGRAM DESCRIPTION
Massbus Flow
................. .
RH70/Cache Interface Flow . . . . . . . . . . .
WRITE-CHECK COMMAND FLOW DIAGRAM DESCRIPTION

CHAPTER 6

DETAILED LOGIC DESCRIPTION

6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6

GENERAL . . . . . . . . . . . . . .
BCTA LOGIC DIAGRAM . . . . .
Local/Remote Register Selection
RSEL Signals . .
Decoder Inputs . . . . .
Decoder Outputs . . . .
Word or Byte Addressing
Control Lines
.....
ODD BYTE L Signal ..
Device Select (DEV SEL) Logic
Control Out (CNTL OUT) Signal
LOGIC DIAGRAM BCTB
Loading Local Registers
Deskew of DEMAND Signal
Register Strobe (REG STR)
Writing a Remote Register
SSYN Logic . . . . . . . .

6.2.7
6.2.8

6.2.9
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5

5-1
5-1
5-3
5-3
5-3
5-5
5-5
5-5
5-8
5-9
5-9
· 5-10
· 5-10
· 5-12
· 5-13
· 5-13
· 5-15
· 5-15
· 5-17
· 5-17
5-19
· 5-21
· 5-21
· 5-23
.. 5-24
· 5-24
· 5-26
· 5-27

6-1

.. 6-9
· 6-11
· 6-11
.. 6-11

· 6-11
· 6-12
· 6-12
· 6-12
· 6-12
· 6-12
· 6-12
· 6-12
· 6-12
· 6-13
· 6-13
· 6-13

CONTENTS (Cont)

Page
6.3.6
6.3.7

6.3.8
6.4
6.4.1
6.4.2
6.4.3
6.5

6.6
6.6.1

6.6.2
6.6.3
6.6.4
6.6.5
6.7

6.7.1
6.7.2

6.7.3
6.8
6.8.1
6.8.2
6.8.3
6.9
6.9.1
6.9.2
6.9.3
6.1l0
6.10.1
6.10.2

6.1.1
6.11.1
6.11.2
6.12
6.12.1
6.12.2
6.12.2.1
6.12.2.2
6.12.2.3
6.12.3
6.12.4
6.12.5
6.12.6
6.13
6.13.1
6.13.2
6.13.3
6.13.4
6.13.5
6.14

One·Shot Multivibrator
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·14
Data Buffer Out Clock (DB OCLK H) . . . . .
. . . . . . . . . . ..
. . . . 6·14
SSYN and TRA Light Emitting Diodes (LEDs)
. . . . . . . . . . . . . . . 6·15
LOGIC DIAGRAM BCTC . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 6·15
Interrupt Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·15
Interrupt Done . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·15
BG IN, SACK and BBSY Light·Emitting Diodes (LEDs) . . . . . . . . . . . . . . . . 6·16
LOGIC DIAGRAM BCTD . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 6·16
LOGIC DIAGRAM AWRA . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 6·16
DBL Flip·Flop . . . . . . . . . . . . . .
. . 6·16
CNT DWN Flip·Flop . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 6·17
BA01 Flip·Flop
.................
. . . . . . . . . . . . . . . 6·17
. . . . . . . . . . . . . . . . . . . . . . . 6·17
BA02, BA03 Bus Address Bits .
BA04 - BAll Bus Address Bits . . . . .
. . . . . . . . . . . . . . . . . . . . 6·18
LOGIC DIAGRAM AWRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·18
BA12 - BA15 Bus Address Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·18
Bus Address Extension Register (Bits BA16 - BA21)
. . . . .. . . . . . . . . 6·18
Asynchronous Massbus Parity (CPA OUT) . . . .
. . . . . . . . . . . . . . . . 6·19
LOGIC DIAGRAM AWRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·19
BA and BAE Multiplexers . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·19
Address Drivers
..........
. . . . . . . . . .
. . . . . . 6·19
Control Signals CX and C 1 ..
. 6·19
. . 6·20
LOGIC DIAGRAM AWRD . . . . . .
Drive Word Count Register . .
. . . . .
. . 16·20
Word Count Register . . . . . . . . . . . .
. . . . . .
. . 6·20
Detection of Maximum Word Count ..
. . . . . . . . .
. . 6·21
LOGIC DIAGRAM AWRE . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 6·21
Drive Word Count Overflow . . . . . . . . . . . .
. . . . . . 6-21
Word Count Overflow
.... .
. . 6-21
LOGIC DIAGRAM AWRF . . . . . . . .
· 6-21
BUSI Multiplexers . . . . . . . . . . . . . . .
. . . . . . .. . . . . . . . 6-21
. . . . . . . 6·21
Parity Checker, MCPE Flip·Flop . . . . . . . .
LOGIC DIAGRAM MDPA . . . . . . . .
. . . . . 6·22
RA FULL and RB FULL Flip.Flops . . . . . . . . . . . . . .
. . . . . . . 6·22
MDP A CLK RA H, MDPA CLK RBH . . . . . . . . . . . . .
. . . . . . . 6·22
Assertion of CLK RA, CLK RB During Read Command . . . . . . . . . . . . . 6·22
Assertion of CLK RA or CLK RB During Maintenance Operation . . . . . . . . 6·23
Assertion of CLK RA or CLK RB During Write or Write·Check Command
.. 6·23
RC FULL and RD FULL Flip.Flops ..
. . . . 6·23
MDPACLKRCH,MDPACLKRDH
... ...
. . . . . . 6·24
Parity Check Enable . . . . . . . . . .
. . . . .
. . . . . . 6·25
START MEM Enable . . . . . .
. . . . . .
. 6·25
LOGIC DIAGRAM MDPB . . . . . . . . . . .
... . . . . . . . . . . . . . .
. 6·25
AMX Multiplexer
· 6·25
Parity Bits (AMX)
· 6·25
RA, RC Registers
· 6·25
MXR . . . . . . .
· 6·25
Parity Bits (MXR)
· 6·25
LOGIC DIAGRAM MDPC . . . . . . . .
. . . . 6·26

CONTENTS (Cont)
Page
6.14.1
6.14.2
6.14.3
6.15
6.15.1
6.1 5.2
6.15.3
6.15.4
6.15.5
6.15.6
6.15.7
6.15.8
6.15.9
6.15.10
6.15.11
6.15.12
6.16
6.16.1
6.16.1.1
6.16.1.2
6.16.1.3
6.16.2
6.16.3
6.16.4
6.16.5
6.16.6
6.16.7
6.16.8
6.16.9
6.17
6.18
6.19
6.19.1
6.19.2
6.19.3
6.19.4
6.19.5
6.19.6
6.19.7
6.19.8
6.19.9
6.20
6.20.1
6.20.1.1
6.20.1.2
6.20.1.3
6.20.1.4
6.20.1.5
6.20.2

Pari ty Bits (BMX) . . . . . . . . .
RB and RD Registers . . . . . . . .
Parity Generator/Checker Circuits .
LOGIC DIAGRAM MDPD . . . . . . . .
Clocking the RF Register, RF FULL Flip-Flop
Clearing the RE FULL Flip-Flop . . . . . . .
Clocking the RG Register, RG FULL Flip-Flop
Clearing RF FULL Flip-Flop . . . . . . .
RG RDY Flip-Flop . . . . . . . . . . . .
Clocking OBUF, OBUF FULL Flip-Flop .
Clearing the RG FULL Flip-Flop
Clearing OBUP FULL Flip-Flop . . . . .
MDPD DB EMPTY L, MDPD LAST WORD H .
Mixer Select (MDPD MXR SEL) ..
RD ENA Pointer . . . .
. .....
RB ENA Pointer . . . . . . .
LOGIC DIAGRAM MDPE . . . .
MDPE CLK MXR WORD H
Write Operation
Data Buffer Maintenance Operation
Write Check Operation ..
MDPE CLK RE L Signal .
Inhibiting Delay Line E011
RE FULL Flip-Flop
MDPE REG FULL H Signal
Exclusive-OR Network . . .
Odd Word and Even Word Write-Check Error
Pari ty Checkers
.............. .
RE Register Chip . . . . . . . . . . . . . . .
LOGIC DIAGRAM MDPF . . . . . . .
LOGIC DIAGRAM MDPH . . . . . . .
LOGIC DIAGRAM CSTA . . . . . . . .
Command Code Decoding Logic .
GO Bit, GO CLRPulse . . . . . . .
Function Load Flip-Flop
Ready State (RDY)
BUSY Flip-Flop . . . . . . .
Invert Parity Check (IPCK)
Unit Select Bits and Program Clear (PG CLR) .
PAT Bit
................... .
Bus Address Increment Inhibit Flip-Flop
..... .
LOGIC DIAGRAM CSTB
Massbus Control Logic . . . . . . . . . . . .
RUN Flip-Flop . . . . . . . . . . . . .
End of Segment (EOS) Flip-Flop
Disable Sync Clock (DIS SCLK) Flip-Flop .
...... .
DRIVE CLK Signal
Zero Filling the Sector or Record
Non-Existent Drive (NED) Flip-Flop . .

vii

· 6-26
· 6-26
· 6-26
· 6-26
· 6-26
· 6-27
· 6-27
· 6-27
· 6-27
· 6-27
· 6-28
· 6-29
· 6-29
· 6-30
· 6-30
· 6-31
· 6-31
. . . . 6-31
· . . . . 6-31
· . . . . 6-32
. .. 6-32
· . 6-32
· . 6-32
· . 6-32
· . 6-32
· . 6-32
· . 6-33
· 6-33
· 6-33
· 6-34
· 6-34
· 6-35
· 6-35
· 6-35
· 6-35
· 6-36
· 6-36
· 6-36
· 6-36
· 6-36
· 6-37
· 6-37
. . . . . . . . . 6-37
· . 6-37
· . 6-38
· . . . . 6-38
· . . . . 6-38
· 6-39
. . . . . . 6-39

CONTENTS (Cont)
Pagt~

6.20.3
6.20.4
6.20.5
6.20.6
6.20.7
6.20.8
6.20.9
6.20.10
6.21
6.21.1
6.21.1.1
6.21.1.2
6.21.1.3
6.21.2
6.21.3
6.22
6.22.1
6.22.2
6.23
6.23.1
6.23.2
6.24
6.25
6.25.1
6.25.2
6.26

Program Error (PGE) Flip-Flop
· 6-39
Missed Transfer (MXF) Latch
· 6-39
Data Late (DLT SYNC) Flip-Flop .
· 6-401
Exception Save (EXC SAVE) Flip-Flop
'. 6-40
Read Exception Circuitry . . . . .
· 6-41
Transfer Error (TRE) Flip-Flop
· 6-41
Special Conditions (CSTB SC H) ..
· 6-41
Interrupt Logic . . . . . . . . . .
· 6-41
LOGIC DIAGRAM CSTC . . . . . . .
· 6-42
Memory Cycle Control Logic
· 6-42
SMC Flip-Flop
· 6-42
REQ Flip-Flop . . . . . . .
'. 6-42
CIP Flip-Flop
.........
. . . . . .
· 6-43
Data Parity Error . . . . . . . . . . .
. .....
· 6-43
Address Parity Error (APE), Non-Existent Memory (NEM) Flip-Flops . . .
· 6-44
LOGIC DIAGRAM CSTD . . . . . . . . . . . . . .
· 6-44
BUSI Multiplexers (CS1, CS2) . . . . . . . . . .
. . . . . . . . . . . . . 6-44
INIT and Program Clear (PG CLR) Logic . . .
· . . . . . . . . . . . 6-45
LOGIC DIAGRAM CSTE
· 6-45
BUSI Multiplexers (DB, CS3) . . . . . . . .
" 6-45
Four Counter . . . . . . . . . . . . . . . .
· 6-45
M5904 MASSBUS TRANSCENER MBSA, MBSB, MBSC .
· 6-45
M5904 MASSBUS TRANSCENER MODULE
" 6-46
75113 Dual Differential Driver Chip . . . . . .
'. 6-47
75107B Dual Differential Line Receiver Chips .
. " 6-48
H870 TERMINATOR . . . . . . . . . . . . . . . .
. ' 6-48

CHAPTER 7

INSTALLATION AND MAINTENANCE

7.1

INTRODUCTION
INST ALLATION
Mechanical .
Electrical . . . .
Module Locations
Massbus Cables .
Jumper Configurations
BCT Module (M8153)
..... .
MDP Module (M8150).
. . . . . .
Light-Emitting Diodes (LEDs) . . . . . . . . . .
VISUAL INSPECTION AND ELECTRICAL CHECK
TM02/TU16 INSTALLATION . . . . . . . . . . .
RH70/TM02 Massbus Cable Installation
TM02/TU16 Slave Bus Cable Installation . . . . . .
Markup of Massbus and Slave Bus Cables
..... .
MAINTENANCE TOGGLE PROGRAM . . . . . . . . .
Maintenance Program to Exercise the Data Buffer .
DIAGNOSTIC MAINTENANCE . . . . . . . . .
RH70 Controller Test Diagnostic (DZRHA)
Data Reliability Diagnostic (DZTUA)

7.2
7.2.1
7.2.2

7.2.3
7.2.4

7.2.5
7.2.5.1
7.2.5.2
7.2.6

7.3
7.4
7.4.1

7.4.2
7.4.3
7.5
7.5.1
7.6
7.6.1

7.6.2

viii

7-1
7-1
7-1
7-1
7-1
7-1
7-1
7-1
7-4
7-4
7-5
7-6
7-7
7-8
· . . . .
. 7-11
· . . . .
" 7-11
· . . . . . . . .. . 7-13
· . . . . . . . . . . " 7-14
· 7-14
· . . . . . . . . . . . 7-14

CONTENTS (Cont)
Page
7.6.3
7.6.4
7.6.5
7.6.6
7.6.7

TM02/TUI6 Basic Function Diagnostic (DZTUB) . . . . . . . . . . . . . . . . . . . 7-14
TM02/TUI6 Control Logic Test (DZTUC)
. . . . . . . . . . . . . . . . . . . 7-15
TM02 Drive Function Timer (DZTUD) . . . . . . . . . . . . . . . . . . . . . . . . 7-15
TU16 Utility Driver (DZTUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
Data Tape Create (DZTUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

APPENDIX A

INTEGRATED CIRCUIT DESCRIPTIONS

A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
A.I0
A.l1
A.12
A.13
A.14
A.15
A.16
A.17
A.18
A.19
A.20
A.21

INTRODUCTION . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-I
7442 4-LINE-TO-I0-LINE DECODERS (l-of-l0) . . . . . . . . . . . . . . . . . . . . . . A-2
74H74 D-TYPE EDGE-TRIGGERED FLIP-FLOPS . . . . . . . . . . . . . . . . . . . . . A-4
74S74 D-TYPE EDGE-TRIGGERED FLIP-FLOPS . . . . . . . . . . . . . . . . . . . . . A-4
7485 4-BIT MAGNITUDE COMPARATORS . . . . . . . . . . . . . . . . . . . . . . . . A-5
74HI06 DUAL J-K EDGE-TRIGGERED FLIP-FLOPS . . . . . . . . . . . . . . . . . . . A-6
74123 RETRIGGERABLE MONOSTABLE MULTIVIBRATOR . . . . . . . . . . . . . . A-7
74157 QUADRUPLE 2-LINE TO I-LINE MULTIPLEXER . . . . . . . . . . . . . . . . . A-9
74S157 QUADRUPLE 2-LINE TO I-LINE MULTIPLEXER . . . . . . . . . . . . . . . . A-9
74174 HEX D-TYPE FLIP-FLOPS . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-I0
74S174 HEX D-TYPE FLIP-FLOPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-I0
74175 QUAD D-TYPE FLIP-FLOPS . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-11
74180 PARITY CONTROL GENERATOR/CHECKER . . . . . . . . . . . . . . . . . . A-12
74191 4-BIT BINARY COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-13
74193 4-BIT BINARY COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-15
74298 QUADRUPLE 2-INPUT MULTIPLEXER . . . . . . . . . . . . . . . . . . . . . A-17
75107 DUAL DIFFERENTIAL LINE RECEIVER . . . . . . . . . . . . . . . . . . . . A-18
75113 DUAL DIFFERENTIAL DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . A-18
8223 256-BIT BIPOLAR FIELD-PROGRAMMABLE ROM (32 X 8 PROM) . . . . . . . A-18
8234 2-INPUT 4-BIT DIGITAL MULTIPLEXER . . . . . . . . . . . . . . . . . . . . . A-19
82S62 PARITY GENERATOR AND CHECKER . . . . . . . . . . . . . . . . . . . . . A-20

ILLUSTRATIONS
Figure No.
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
2-1
3-1
3-2
3-3

Title

Page

TWU16 Simplified System Diagram
. . . . . . . . . . . . . . . . . . . . . . . . .. 1-1
RH70 Simplified Data Path Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-6
Read Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Write Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
RH70 Error Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9
Reference Edge of Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Track-Bit Weight Relationship for Nine-Channel Transport . . . . . . . . . . . . .
1-10
NRZ Format (Nine-Channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
PE Recording Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Data Formats
Massbus Interface Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Device Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ., 3-2
RH70/TM02 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Control and Status Register I-Bit Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

ILLUSTRATIONS (Cont)

Figure No.
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
4-1
4-2
4-3

44
4-5
4-6
4-7
4-8
5-1
5-2
5-3

54
5-5
5-6

5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
6-1
6-2
6-3

64
6-5
6-6
6-7
6-8
6-9
6-10
6-11

Title
Word Count Register Bit Usage
Bus Address Register Bit Usage
Frame Counter Bit Usage
Control and Status Register 2-Bit Usage
Drive Status Register Bit Usage
Error Register Bit Usage . . . . . . . .
Attention Summary Register Bit Usage
Check Character Register Format
Data Buffer Bit Usage
Maintenance Register Bit Usage
Drive Type Register Format
Serial Number Register Bit Usage
Tape Control Register Bit Usage
Bus Address Extension Register Format
Control and Status 3 Register Format
Rewind Operation Flowchart
Space Operation Flowchart
Erase Operation Flowchart .
PE Data Read Operation Flowchart
NRZ Data Read Operation Flowchart
PE Data Write Operation Flowchart
NRZ Data Write Operation Flowchart
Write Tape Mark Operation Flowchart
Register Control Path
..... .
Writing Remote Register Interface .
Reading Remote Register Interface
Data Buffer Maintenance Operation
Write Command Data Path
Data Word Boundaries . . . . . .
Read Command Data Path . . . .
Write-Check Command Data Path
Memory Interface Write or Write-Check Operation (Read from Memory)
Write or Write-Check Command Memory Bus Timing (Read from Memory)
Memory Interface - Read Operation (Write into Memory)
Read Command Memory Bus Timing (Write into Memory)
Write Command Flow Diagram
Read Command Flow Diagram . . . . . . . .
Write-Check Command Flow Diagram
Read or Write-Check Massbus Timing Diagram
Write Command Massbus Timing Diagram
Data Buffer Maintenance Operation Timing Diagram
Data Buffer Write Command Timing Diagram
Data Buffer Read Command Timing Diagram
Data Buffer Write-Check Command Timing Diagram
Mapping Massbus/Unibus Addresses
Massbus Data Transfer Sequence .. . . . . . .
Memory Cycle Simplified Timing Diagram . . . .
Typical Differential Driver/Receiver Connection
Driver Termination . . . . . . . . . . . . . . .

Page
· 3-1l3
3-:l3
· 3-114
· 3-1l4
· 3-1t7
· 3-20
· 3-26
· 3-28
· 3-29
· 3-30
· 3-34
3-36
3-36
3-39
3-39
4·2
4·3

44
4·5
4·7
4·8
· 4-] 0
.. 4-11
5··2
5·4
5··6

5-7
· 5-] 1
· 5-12
5-14
5-] 6
· 5-18
5-19
· 5-20
· 5-20
· 5-22
5-25
5-28
6-3
6-4
6·5

6..6
6 ..7
6 ..8
6-10
6-2.8
6-42
6-46
6-47

ILLUSTRATIONS (Cont)

Figure No.
6-12
6-13
6-14
6-15
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9

Title
Driver Chip Simplified Schematic
Dual Differential Driver Pin Connection Diagram
Simplified Line Receiver Logic Diagram . . . .
75107B Differential Receiver Pin Connection Diagram
Module Utilization Chart . . . . . .
Massbus Cable System Configuration
LED Physical Locations . . . . . .
Jumper Summary
.......... .
RH70/TM02 Massbus Cabling Diagram
TM02/TU16 Slave Bus Cabling Diagram
......... .
Massbus Cable Stamp
Marked-Up Massbus Cable . . . . . . .
Maintenance Program to Exercise Data Buffer

Page
· . 6-47
· 6-48
· 6-48
· .. 6-48
7-2
7-3
7-5
7-8
7-9
· .. 7-10
· 7-11
· .. 7-11
· 7-12

TABLES

Table No.
1-1
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
6-1
7-1
7-2
7-3

Title
Related Documentation . . . . .
Massbus Signal Cable Designations
RH70 and TM02/TU16 Device Registers
Results of Program-Controlled Clearing
Command Function Codes . . . . . . .
1WU16 Commands and Required Parameters
Control and Status 1 Register Bit Assignments
Word Count Register Bit Assignments
Bus Address Register Bit Assignments . . . . .
Frame Counter Bit Assignments
Control and Status Register 2 Bit Assignments .
Drive Status Register Bit Assignments
. . . . . .
Error Register Bit Assignments . . . . . . .. . .
Error Conditions . . . . . . . . . . . . . . .
Attention Summary Register Bit Assignments .
Check Character Register Bit Assignments . . . . .
Data Buffer Bit Assignments . . . . . .
.. . . .
Maintenance Register Bit Assignments .
Drive Type Register Bit ASSignments . . .
Serial Number Register Bit Assignments
Tape Control Register Bit Assignments
Bus Address Extension Register Bit AsSignments
Control and Status 3 Register Bit Assignments
Error Recovery Procedures . . . . .
Listing of RH70 Logic Diagrams ..
TU16 Backplane, Regulated Voltages
P4 Connector, Unregulated Voltages
TM02 Voltage Check . . . . . . . . .

Page
1-2
2-5
3-1
3-3
3-5
3-8
· 3-11
. . . . 3-13
· . 3-13
· 3-14
· 3-15
· 3-18
· 3-21
· .. 3-25
· 3-27
· .. 3-29
· 3-29
· . 3-30
· 3-35
· . 3-36
· 3-37
· .. 3-39
· . 3-40
· .. 3-45
6-2
7-6
7-7
7-7

CHAPTER 1
SYSTEM AND PHYSICAL DESCRIPTION

1.1 GENERAL
This manual describes the TWU16 Magnetic Tape
System manufactured by Digital Equipment Corporation. The basic items in the system are:

1.1.1 Scope
This manual is designed to provide Digital Field
Service and customer maintenance personnel with
sufficient installation, operation, and servicing information to install and maintain the RH70. Because
the RH70 is used with the TM02 Tape Controller
and TU16 Tape Transport, brief descriptions of
these items are included in this manual. Detailed information on these items may be found in the
TU16/TM02 Tape Drive System Maintenance
Manual.

RH70 Massbus Controller(s)
TM02 Magnetic Tape Controller(s)
TU 16 Tape Transport(s) (Figure 1-1).
The TWU16 is employed with the PDP-ll/70 Central Processor which can accommodate up to four
RH70 Massbus Controllers.

UNIBUS

CENTRAL
PROCESSOR

I
I

MEMORY
MANAGEMENT

I
I

UNIBUSI
CACHE
INTERFACE
CACHEI
MEMORY
INTERFACE

RH70
MASSBUS
CONTROLLER

I
I RH70/CACHE

I INTERFACE

CACHE

~--------~MEMORY~--~I~------~

L_____ _

SLAVE
BUS

MAIN
MEMORY
BUS

MAIN
MEMORY

TU16
TAPE
TRANSPORT
(1 TO 8)

11- 3071

Figure 1-1

TWU16 Simplified System Diagram
I-I

the Unibus is not overloaded, resulting in less contention at the Unibus. Peripheral devices connected
to the Unibus access main memory via the Cache.

1.1.2 Related Documentation
Table 1-1 lists related documentation that suppleml!nts the information in this manual.

1.2.2 Massbus
The Massbus provides a parallel data path between
the RH70 and the TM02 Tape Controller; it has a
minimum cable length of 120 ft, allowing 15 ft b~~
tween TM02 Controllers if the "daisy-chain" configuration (with a maximum of 8 controllers) is
employed. The Massbus comprises two sections: an
asynchronous control bus and a synchronous data
bus for high-speed data transmission.

1.2 BUS INTERFACES
This paragraph briefly describes the following interfaces which are incorporated into the system.
Unibus - provides interface between PD P-ll /70
Central Processor and RH70 Massbus Controller.
M assbus - provides interface between RH70 Massbus Controller and TM02 Tape Controller.

The asynchronous control bus:

Slave Bus - provides interface between TM02 Tape
Controller and TU 16 Tape Transports.

Transmits commands and information
from the controller to the drive to read
or write drive registers.

RH70/ Cache Interface - provides interface between
RH70Massbus Controller and Cache memory.

Notifies the controller when an unusual
(attention) condition exists in one or
more drives.

Transmits status information from the
drive to the controller

Provides a master reset to all drive:s
from the controller.

Main Memory Bus - provides interface between
cache memory and main memory.
Unibus / Cache Interface - provides interface between Unibus Map and Cache memory.
CPU / Cache Interface - provides interface between
PDP-l1/70 Central Processor and Cache memory.

The synchronous data bus transmits blocks of data
at high speed between the RH70 Controller and the
TM02 Controller and controls the initiation and termination of block transmissions. Because the data
and control buses operate independently, the Mas8bus Controller can monitor drive status on the control bus while a data transfer operation on the data
bus is being performed. Additional details on the
Massbus can be found in Chapter 2.

1.2.1 Unibus
The Unibus provides the interface between the
PDP-l1/70 Processor, Cache, the RH70 Massbus
Controller and general-purpose peripherals. Unibus
devices contain the highest priority for main memory accesses. Since a dedicated separate data path is
available for memory and high-speed peripherals,

Table I-I
Related Documentation
Title

Document Number

PDP-II Peripherals Handbook

2002.20175.4526

TU16/TM02 Tape Drive System Maintenance Manual
PDP-11/70 Processor Handbook
KB11-B Processor System (PDP-I 1/70 Manual)
PDP-11/70 Maintenance and Installation Manual

EK-TUI6-MM-00I
EB 04588/750100
EK-KB11B-TM-001
EK-1170-MM-001

1-2

the Map box, or the CPU. It then sends back an acknowledge signal to the device of highest priority.
If an RH70 is selected for the next memory cycle,
the Cache asserts signals which gate that controller's bus address, bus address extension (memory address), and control information (CO, C1, and
CX) onto the RH70 to Cache Interface. Additionalselect signals allow the specified controller to gate
data onto the interface (read) or to clock data off
the interface (write or write-check).

1.2.3 Slave Bus
All TU 16s controlled by a TM02 are "daisychained" on the Slave Bus (Figure 1-1). Essentially,
this means that the TU16s are configured parallel
to each other. The Slave Bus consists of slave select
lines, write data lines, read data lines, transport control lines and various TU 16 status lines. The various signals on the Slave B us are tabulated in the
TU16/TM02 Tape Drive System Maintenance
Manual.
1.2.4 RH70 to Cache Interface
The RH70-to-Cache Interface is an integral interface with an open-collector bus to which each
RH70 connects. This interface routes 22 bits of address, 36 bits of data (32 data bits, plus 4 parity
bits), and three control signals (CO, C1 and CX) to
or from Cache. CO specifies a Data Out Byte (DATaB) or Data In Pause (DATIP); however, the
RH70 does not implement these operations and this
bit is always unasserted, (see chart below).

0
0

1
1
1

0
0

0
0
0

1
0

1.2.5 Main Memory Bus
The Main Memory Bus is a bus structure which
originates at the Cache and daisy-chains through all
the control modules of the memory. Physically, it
consists of 4 cables containing 22 bits of address, 1
bit of address and control parity, 36 bits of data
(32 bits of data, plus 4 parity bits), four byte mask
signals, which determine the byte(s) to be written
on write cycles, and various handshake signals associated with controlling the interface sequence.
1.2.6 Unibus to Cache Interface
During Unibus memory cycles, the Unibus-toCache interface controls the mapping of 18-bit
Unibus addresses to the 22-bit address field of the
Main Memory Bus. The interface contains 22 address bits, a 16-bit wide data path, a Request signal
that requests use of the Cache, a parity error signal,
and two control signals (CO, C1) to determine the
direction of data transfer. The interface is integral
with the 11/70 and contains no external bus
structure.

*DATI always double words
DATIP
*DATO single word
*DATO double word
DATOB

C I specifies a DATI (read from memory) or a
DATa (write into memory) transfer; and CX specifies a double-word transfer, if asserted, or a singleword transfer, if negated.
For transfers between the RH70 and memory, the
Cache merely serves as an interface and is not updated as in Unibus/memory transfers or
CPU /memory transfers. If the memory location
being modified during a read (drive to RH70) is
also in Cache, the data in Cache is invalidated. As
a result, the CPU and Unibus memory cycles must
access main memory to obtain correct data.

1.2.6.1 CPU to Cache Interface - The CPU to
Cache Interface is an integral interface (with no external buses) between the 11/70 processor and
Cache memory. It contains a 22-bit wide address,
16-bit wide data path and associated error signals
such as parity abort. The CPU/Cache Interface
also contains CO and CI control signals which specify the type and direction of data transfer between
Cache and the 11/70.

The RH70 initiates a data transfer by issuing a
request to Cache. Cache arbitrates the request
along with requests from other RH70 Controllers.

The Memory Management and Relocation unit in
the processor converts the I6-bit virtual address
from the processor into the 22-bit address which
specifies a location in main memory.

* RH70 functions - DATIP and DA TOB
operations are not implemented by the
RH70.

1-3

1.3 PDP-II/70 CENTRAL PROCESSOR
SYSTEM
The PDP-II/70 Central Processor System consists
of the following components.
PDP-ll/70 Central Processor
Cache Memory, Main Memory
Unibus Map
RH70 Massbus Controller
TM02 Tape Controller and TU16 Tape
Transport
Each component is briefly described below.

Process parity and perform error dt~tec
tion to maintain system integrity.

Arbitrate cycles to determine which device will have access to memory. The
Unibus Map box has the highest pJriority, followed by the RH70 I/O Controllers (Controller A, B, C and D, in
that order) with the CPU having the lowest priority.

When the Cache is interfacing between the CPU
and memory or between the Unibus Map and memory, it is continually being updated by the' current
data with which the CPU or Unibus Map is working. During a CPU-to-memory or Unibus-to-memory transfer, if a word to be written into memory is
also in Cache, the word in Cache is updated and at
the same time is transferred to main memory. If the
word to be written into memory is not in Cache,
the CPU -to-memory or Map-to-memory cycle occurs with no Cache update.

1.3.1 PDP-II Central Processor
The 11/70 Central Processor is an advanced processor of the PDP-II family, available with an optional floating point unit. Several additional
features are contained in this processor. The large
memory capacity allows up to 2 million words of
core memory. The entire 2 million words of core
memory is made to appear as fast memory to the
11/70. This is accomplished via a fast 1K or 1024word Cache memory. Core memory cycle time is approximately 1 /-LS and the Cache memory cycle time
is approximately 300 ns. Statistically, it has been determined that 80 to 95 percent of the words referenced by the 11/70 may be in Cache, which creates
an effective memory time of less than 450 ns.

During a memory-to-CPU or memory-to-U nibus
transfer, if a word to be read from main memory is
also in Cache, the word in Cache is directly transferred to the CPU or Unibus Map and no slow
memory cycle is performed. If the word to be read
from memory is not in Cache, a slow memory cycle
is performed and the two words of that block are
sent to Cache. The word requested is then sent to
the CPU or Unibus Map.

1.3.2 Cache Memory, Main Memory
The: 11/70 Central Processor contains a 1024-word
bipolar memory system, designated Cache Memory.
The Cache Memory system simulates a system having a large amount of moderately fast memory by
relying on a small amount of very fast bipolar memory, a large amount of slow core memory and the
statistical behavior of operating programs. The concept is to have most of the data that the processor
needs in the fast Cache Memory, to allow the program to operate quickly, while having to slow
down only occasionally for slow core memory cycles. This is accomplished by constantly updating
the data in Cache to provide a high probability that
the data most likely needed by the processor will be
in fast memory.

In the case of data transfers from the RH70 to
memory or from memory to the RH70, the Cache
merely serves as an interface and there is no updating of Cache.

1.3.3 Unibus Map
The Unibus Map is a standard hex board which allows Unibus devices in the 11/70 system to address
up to 2 million words of core memory through the
use of 31 read/write registers. These registers are
each 22 bits long and require two Unibus register
addresses. A block of 62 Unibus addresses is consequently reserved for the Unibus Map-31 registers
with two addresses per register.

The primary functions of the Cache Memory are
to:
1.
Act as a high speed buffer and interface
between memory and the requesting device (e.g. CPU, Unibus or Massbus
Controls).

Bits 13 - 17 of the Unibus address dynamically select one of 31 mapping registers during Unibus
memory cycles.

1-4

NOTE
A 32nd Map register is dynamically selected when
Unibus address bits 13 - 17 are all Is. In the PDP11 architecture, this address field is defined as I/O
register space; therefore, the 32nd register is not used
to map address to memory.

1.3.5 TUI6/TM02 Tape System
The TU 16/TM02 is a Massbus-compatible, versatile tape drive system, consisting of a TM02 Tape
Controller and TU16 Tape Transport(s). The
TUI6/TM02 records and reads digital data in industry-standard PE or NRZ mode at a maximum
data transfer rate of 72,000 tape characters per second. Tape density and tape character format are
program-selectable. Forward/reverse tape speed is
45 in/sec, while rewind is performed at 150 in/sec.
The TUI6/TM02 Tape Drive System also has forward and reverse read/space capability.

When an Initialize is received or when power is
first turned on, the system is set for one-to-one
mapping, which means that a specific Unibus address specifies the corresponding main memory address with no relocation. In other words, Unibus
address 5000 specifies main memory location 5000.
This process is valid up to 124K of memory. Beyond that point, memory relocation (mapping) is required. In order to implement this, the programmer
loads the Map registers and sets a bit in a Control
register, located in the processor Memory Management Unit. When the Unibus address selects a particular mapping register via bits 13 - 17, bits 0 - 21
of the Unibus address are added to bits 1 - 21 of
the mapping register. The sum of these bits result
in a relocated address in core memory. Consequently, this mapping scheme allows any of core
memory to be accessed.

The TU 16 /TM02 Tape System performs the following functions:

1.3.4 RH70 Massbus Controller
The RH70 Controller, in conjunction with the
TM02/TUI6, provides an extremely fast and reliable mass storage system that can be employed in
timesharing or real-time data storage applications.
The following major functions are performed by
the RH70:
1.

Communicates with the main memory
via Cache in order to fetch and store
data.

Communicates with the central processor via the Unibus in order to receive
commands, provide error and status information, and generate interrupts.

Interfaces with from one to eight drives
via the Massbus.

Records and plays back data.

Generates tape marks to separate files.

Provides clock signals to synchronize
data transmission between drive and
controllers.

Maintains error and status indicators
and generates an Attention signal when
exceptional conditions occur.

Locates data records by the spacing
function.

Provides mechanisms for convenience
and diagnostic testing.

Performs error detection on the data and
provides error correction in PE (PhaseEncoded) mode only.

The major assemblies of the TUI6/TM02 Tape System include the TU16 Tape Transport, the TM02
Tape Controller, the H740D Power Supply for the
TM02, and the 861 Power Controller, which controls power in the TU 16/TM02 cabinet.
1.4 RH70 FUNCTIONAL OPERATION
The RH70 is divided into two major functional
groups: the register access control path, and the
DMA (Direct Memory Access) data path (Figure 12). The register access control path allows the program to read from or write into any register contained in the RH70 or in the selected tape drive.

The RH70 can accommodate up to eight TM02
Tape Controllers. Each TM02 Tape Controller, in
turn, can accommodate up to eight TU 16 Tape
Transports.

1-5

RH70 1/0 CONTROLLER

I
U
N
I
B
U

PROGRAM
CONTROLLED

TRANSFERS

I
I

LOCAL
REGISTERS

I
I
7

.I.

'- -

I
I
I
I

M
E
M

0
R
Y

CACHE
MEMORY

I
I
I

MASSBUS
CONTROL
BUS
LOGIC

f--

MASSBUS
CONTROL BUS

M
A
S
S
B
U
S

- - -- - - - -- - - -- - ..J

PATH (DiRECTMEMORYACCESS-)- -

DATA TO

- - -- l

DATA TO MASS BUS

MEMORY

- - - - - --

I
J OBUF
FULL 1
-I

8 WORD
DATA
BUFFER

FLAG

1-------

I
L - - - -

I
I

ORDY (OUTPUT READY FLAG)

IRDY( INPUT READY FLAG)

I
I
I

roM;-OATA

I--

MTCS1 CONTROL AND STATUS 1
(SHARED WITH THE DRIVE)
MTCS2 CONTROL AND STATUS 2
MTDB DATA BUFFER
MTWC WORD COUNT
MTBA BUS ADDRESS
MTBAE BUS ADDRESS
EXTENSION
MTCS3 CONTROL AND STATUS 3
REMOTE REGISTERS

I
~

I
I

RH70 DEVICE REGISTERS

DATA
BUFFER
CONTROL
LOGIC

MASS BUS
DATA BUS

I
I

DATA FROM
MEMORY

I
-- - - - - - -- - -- - J
DATA FROM MASSBUS

Figure 1-2

r;EG7ST~ Am:S~O~O;:-;AT-;;- -- -- -- -- -- -- -- l

There are a total of six registers in the RH70, nine
registers in each TM02, and one shared register
which is contained partially in the RH70 and partially in the selected TM 02.

When the RH70 receives TRA, it gates the Control
lines onto the Unibus. After a deskew delay, the
RH70 asserts SSYN to the processor. When the
processor receives the control data and SSYN, it
clears MSYN, which in turn negates SSYN and DEMAND. The negation of DEMAND negates TRA
and completes the operation.

The DMA data path functionally consists of an 8
word X 16 bit first-in, first-out memory and associated control logic. The major function of this memory is to buffer data in order to compensate for
fluctuations in cycle arbitration time of the Cache.

Accesses to a TM02 register via the control bus portion of the Massbus do not interfere with data
transfer operations occurring over the data bus portion of the Massbus.

1.4.1 Register Access Control Path
When a PDP-II instruction addresses the RH70 to
read or write any device register in the RH70 or in
the drive, a Unibus cycle is initiated and this data
is routed to or from the RH70. (Refer to Chapter 3
for a detailed description of the registers.) If the register to be addressed is local (contained within the
RH70), the register control logic immediately gates
the data to or from the appropriate register.

1.4.2 DMA Data Path
The D MA data path is used for the actual transfer
of blocks of data and functionally consists of the
synchronous (data) portion of the Massbus, a data
buffer, and the memory bus. The data buffer compensates for cycle arbitration time of the Cache by
buffering data between the RH70 to Cache Interface and the Massbus data bus during data
transfers.

If the register to be accessed is remote (contained in
the TM02 Controllers), the register access control
logic initiates a Massbus control bus cycle. TM02
registers are loaded in the following manner:

The controller places the drive select
code of the desired TM02 on the Drive
Select lines.

The controller places a register select
code on the Register Select lines.

The controller asserts CTOD (Controller-to-Drive ).

The controller places data on the Controllines.

The controller then asserts DEM.

1.4.3 Data Transfer Rates
The data transfer rate from the drive is determined
by a clock in the drive. The basic data transfer rate
for the TWU16 is approximately 28 J.Lsjword. The
memory transfer rate depends on cycle arbitration
time in the Cache and memory cycle time. Figure
1-3 shows the data transfer sequence for a read operation; Figure 1-4 shows the sequence for a write
operation. For lengthy data transfers, the average
memory transfer rate is half the average disk data
transfer since double words are transferred. Statistical fluctu~tions in cycle arbitration times are absorbed by the buffering in the data buffer.
1.5 MAGNETIC TAPE FUNDAMENTALS

The selected TM02 responds to DEM and CTOD
asserted by loading the selected register with the
data on the Control lines; then it asserts TRA. The
controller responds by negating DEM, which
causes the TM02 to negate TRA; the write operation is thereby terminated.

Referenced Edge - The edge of the tape as defined
by Figure 1-5. For tape loaded on a TUI6, the reference edge is toward the observer.
BOT (Beginning of Tape) Marker - A reflective
strip placed on the non-oxide side of the tape,
against the reference edge, 15 ft (± 1 ft) from the beginning of the tape.

A TM02 register is read in a similar manner except
that CTOD is negated (step 3) and step 4 is eliminated. The selected TM02 responds to DEM as~
serted and CTOD negated by gating out the
contents of the selected register onto the Control
lines. The TM02 then asserts TRA to the
controller.

EOT (End of Tape) Marker -A reflective strip
placed on the non-oxide side of the tape, against
the non-reference edge, 25 to 30 ft from the trailing
'
edge of the tape.
1-7

Nine-Channel Recording - Eight tracks of data plus
one track of vertical parity. Figure 1-6 shows the
relationship between track and bit weight for a
nine-channel transport.

Tape Speed - The speed at which tape moves past
the read/write heads; normally stated in inches per
second.
Tape Density - The density of sequential characters
on the tape. It is normally specified in bytes per
inch (bpi), since 800 bpi means that there are 800
tape characters per inch of tape.

Tape Character - A bit recorded in each of the nine
channels.
Record - A series of consecutive tape characters.

Write Enable Ring - A rubber ring which must be
inserted on the supply reel to allow the transport tlO
write on the particular tape. This safety feature
helps to prevent accidental destruction of pre:viously-recorded data.

File - An undefined number of records (minimum
= zero, no maximum).
[merrecord Gap (IRG) - A length of erased tape
used to separate records (0.5 in. minimum for ninetrack; maximum IRG is 25 ft).

Tape Mark (TM) - A record written on the tape to
designate the end of a file; sometimes referred to as
a File Mark (FMK). In the TUI6/TM02, the TM
is always preceded by an extended IRG.

Extended [RG - A length of erased tape (3 in. minimum) optionally used to separate records. It must
be used between BOT and the first record.

WORD

WOFID

WORD

DATAr-----r-----t-~---+_~--+_~--4_~~~

~
.

MEMORY
DATA
NOTE:

Data transfer rate forthe TU16 is
28 J.lsec/word. Average memory
data rate is 56 J.lsec/double word.

Figure 1-3

WORD
1,2

WORD
3,4

CYCLE

ARBITRATION

WORD
56
'

11-3073

Read Data Transfer Sequence

WORD
7

NOTE:

Data transfer rate for the TU16 is 28 J.lsec/word.
Average memory data rate is 56 }Jsec/double word.

SECTOR
FOUND
11-3076

Figure 1-4 Write Data Transfer Sequence

1-8

CPU

TM02

RH70

lOAD FUNCTION
CODE &GO

lOAD FUNCTION
CODE - CLEAR
ROY IF DATA
TRANSFER
FUNCTION

OZ
Z~
ctl-

:E~

:EI0U~

EXC (IF DATA TRANSFER COMMAND)

ATTN, EBl

I
I

TERMINATE
OPERATION
CLEAR GO

SET TRE
IF IE BIT SET

I
I

I
I
Z
00
Zctl:E:::J

:E~
OX
uW

I
I

EXC (IF DATA TRANSFER COMMAND)
ATTN,EBl

SET TRE

I
I

SET ROY,
INTERRUPT
CPU IF IE
I
T

ATTN (IF CLASS A ERROR), EBl

TERMINATE
OPERATION

11-3070

Figure 1-5

RH70 Error Termination

1-9

Cyclic Redundancy Check Character (CRCC) - A
check character that is written four character spaces
after the last character of an NRZ record (ninechannel only). CRCC is derived by a complex
mathematical formula applied to the characters written in the record. The result of this manipulation
(CRCC) can be used to recover a lost bit in a record read from tape. CRCC error recovery hardware is not available in the TUI6/TM02, but
CRCC is written for purposes of compatibility.

TAPE
LEADER

.~~---

Longitudinal Parity Check Character (LPCC) - A
check character written four character spaces after
CRCC (nine-channel). LPCC consists of one bit of
even parity for each track of data. F or example, if
track 1 had an odd number of Is written in a record, then a 1 must be written in the LPCC bit associated with track 1.

SUPPLY
REEL
10-1265

Figure 1-6

Reference Edge of Tape

Tape Mark - A nine-channel NRZ tape mark consists of one tape character (23 8), followed by seven
blank spaces, and then LRCC (23 8). (CRCC is not
written.) Figure 1-8 illustrates nine-channel NRZ
tape format.

1.6, TUI6/TM02 RECORDING TECHNIQUES
1.6.1

NRZI (Non-Return to Zero - Change on a 1)

1.6.1.1 Definition - NRZI is a recording technique
which requires a change of state (flux change) to
write a 1, and no change of state (no flux change)
to write a O.

1.6.2 Phase Encoding (PE)
1.6.2.1 Definition - Phase encoding is a recordinr'
technique in which a flux reversal occurs for eac1~
bit of information written onto the tape. A 1 can
be defined as a positive level followed by a m~gativle
transition; a 0 can be defined as a negative lev,el, followed by a positive transition.

1.6.1.2 Format - A record is a mInImUm of 12
characters. A CRCC character occurs four character spaces after the record. An LPCC character occurs four character spaces after the CRCC (Figure
1-7).

Sequential flux transitions on the tape are eit.her at
the data rate or at twice the data rate. Sequential Is
or sequential Os will cause flux reversals to occur at
twice the data rate:

BIT WT TRACK
22 .-1-

RD 0

2°-2-

RD 1

24 . - 3 -

RD 2

P '-4-

RD :3

25_5-

FW 4

26_6-

RD 5

LJlSL.fULJl
I
I
I
I
I
I

27 - 7 -

RD 6

10-1271

21 -8-

RD 7

23_9-

RD P

ILJlJLIl.JLJ
I
I
I
I
I
I
I 0 101 0 I 0 101

Alternate Is and Os cause flux reversals to occur at
the data rate:

READ AMPS
READ HEAD
10-1264

HI~IHI

I Lf-1 I Lf-1 I ~

Figure 1-7 Track-Bit Weight Relationship
for Nine-Channel Transport

10-1269

1-10

OXIDE SURFACE

TAPE MARK
1

IL. _ _ _ _ ..JI

REFERENCE
EDGE
BOT MARKER

EXTENDED
IRG

EOT MARKER
TAPE MARK

ON OTHER)
SIDE OF
(
TAPE

(

CHARACTER

ON OTHER)
SIDE OF
TAPE
10-1263

Figure 1-8

NRZ Format (Nine-Channel)
Identification Burst (IDB) - The IDB identifies the
tape as a PE tape. It consists of alternating 1sand
Os in the parity track (track 4) with all other tracks
erased. The IDB is located at BOT and has a minimum length of 1.7 in. Figure 1-9 illustrates PE
tape format.

1.6.2.2 Format - To ensure proper extraction of
PE data from the serial stream of transitions coming off the tape, PE data must be recorded in a precise format. A PE record consists of preamble,
data, and postamble.
Preamble - Forty characters of Os in all nine tracks,
followed by a character of Is in all nine tracks.

1.7 TWU16 SPECIFICATIONS
This paragraph defines the parameters in the
TWU16 Magnetic Tape Subsystem.

Data - The data consists of flux reversals for each
bit of information. Negative flux reversals designate
1s; positive flux reversals designate Os.

1.7.1 Data Format
Data Format is selected by the format select bits
(FMT 0-3) in the tape control register as follows:

Postamble - One character of Is in all nine tracks,
followed by 40 characters of Os in all nine tracks.

The PE read electronics uses a data window to isolate data transitions. For example,

FMT (0 - 3)
Mode

Bit
3

1
1
1

0
0
1

0
1
0

DATA

WINDOW
DATA TRANSITION __

__L-__

Normal Mode
Core Dump
15 Mode

Figure 1-10 shows the three modes in the TWU16
system: normal mode, core dump mode and 15
mode. In 15 mode, bit 15 in memory corresponds
to Massbus data bit DO; bit 0 in memory corresponds to Massbus data bit D 17.

10-1270

Zeros in the preamble are used to set the window
in position when reading in a forward direction; Os
in the postamble perform this function when reading in the reverse direction. The all-l s character in
the preamble and postamble is used to mark the beginning of data.

1.7.2 TUI6/TM02 Specifications
Packing Density
200, 556, 800, and 1600 bpi; programselectable.

Tape Mark - A PE tape mark consists of forty Os
in tracks 2, 5, and 8 (bit positions 0, 5, and 1) with
tracks 3, 6, and 9 (bit positions 4, 6, and 3) erased.

1-11

Tape Speed
Forward/Reverse: 45 in/sec (1.14 m/sec)

Power Dissipation
TUI6: 1000 W max
TM02: 300 W max

Rewind: 150 in/sec (3.8 m/sec)
TU16 Transport (without cabinet)
Depth: 25 in. (0.64 m)
Width: 19 in. (0.48 m)
Height: 7 in. (0.17 m)
Weight: 150 lb (70 kg)

Maximum Transfer Rate
72,000 characters/sec
Tape Motion Times
Start: Normal operating speed is reached
within 9 ms after initiation of forward or reverse command.

TM02 Tape Controller
Depth: 23 in. (0.58 m)
Width: 19 in. (0.48 m)
Height: 7 in. (0.17 m)
Weight: 45 lb. (21 kg)

Stop: Motion stops in less than 8 ms after removal of forward or reverse command.
lElectrical Skew
Write deskew only. Read skew mechanically
aligned.

TM02 Power Supply (H740D)
Depth: 8 in. (0.18 m)
Width: 19 in. (0.48 m)
Height: 5 in. (0.13 m)
Weight: 24 lb. (11.2 kg)

Recording Method
NRZI or PE recording; industry-compatible.

861 Power Controller
Depth: 8 in. (0.20 m)
Width: 19 in. (0.48 m)
Height: 5 in. (0.13 m)
Weight: 10 Ib (4.54 kg)

Transport Mechanism
Single capstan; vacuum columns
Read/Write Heads
Dual gap, read after write.

Environmental Limits
Temperature*: 60° to 95° F (15° to 35° C)
Relative Humidity: 20% to 80% (no
condensation)

BOT, EOT Detection
Photoelectric sensing of reflective strip
Interrecord Gap
0.5 in. minimum, 0.65 in. nominal

1.7.3 RH70
Specifications

Tape
Width: 0.5 in.
Thickness: 1.5 mil

Massbus

Controller

Mechanical
RH70 Logic
3 quad-height modules
1 hex-height module
3 double-height modules
CPU Backplane
4 module slots

Take-up Reel
Diameter: 10-1/2 in. (For 1600 bpi mode, the
tape should be certified at 3200 flux changes
per inch).
Capacity: 2400 ft

Power Requirements (RH70)
+5.0±.25 Vdc at 8.5 A max
-15± 1.5 Vdc at 0.5 A max

Power Control
861 Power Controller
Voltage Requirement
TUI6: 115/230 Vac + 10% at 50/60 Hz + 2%

* Magnetic tape operation is more reliable if the temper-

TM02: 90-135 Vac; 180-270 Vac at 47-63 Hz

ature is limited to 65° to 75° F (18° to 24° C) and the relative humidity to 40% to 60%.

1-12

Logic Voltage
High=0.3 V; Low=O V

Vibration Shock
1.89 g rms, 10-300 Hz
20 g, half sine, 30 ms duration, any plane

Environmental
Data Transfers Memory/Controller
Data is normally transferred as double data
words (32 data bits, plus 4 parity bits) via the
RH70/Cache Interface, and then to or/from
memory via the memory bus.

Temperature
32° - 122° F (0° - 50° C) Class C
Relative Humidity
8% to 90%, no condensation

~TENDED IRG

1.7" MIN.

IRG
3.0'MIN.~-+lI+-------RECORD --------100/4----0.6" NOMINAL-----+)

PREAMBLE: 41 CHAR.

~---- DATA -----.)~i

j . - - POSTAMBLE: 41 CHAR.

)1111111111111 illl
\11111111111111111

27 7 II I I II I I I I 1111 I I

~ 11111111111111111

2 6 6 I I I I I I I I I I II I I I I

I I I I I I I I I I I I I I I II

1111111

2 5 5 I I I II I I I I I II I I I I

11111111111111111

1111111I

41111111111111111

1111111·1111111111

1111111

IDENTIFICATION BURST
I

31111111111111111

~1I111111111111111

i BOT TAB :

21111111111111111

'11111111111111111

11111111111111111

(111111111 I 111111 I

1111111111111111111111

r-------l
L

______ -'

1111111

....---MOST SIGNIFICANT

IIIIII~

11111111

...---:::LEAST SIGNIFICANT

I II I II I

1111111

TRACK NUMBER
NOTE

II II II I

91111111111111111
81111111111111111

REFERENCE EDGE

1. TAPE IS SHOWN WITH OXIDE SIDE UP.
10-1280

Figure 1-9

PE Recording Format

1-13

PDP-tt
CORE WORD
LSB

MASSBUS
DATA WORD

BIT WEIGHT
20

_D"j
1 ", CHARACTER
WRITTEN

DB]
1 2'· CHARACTER
WRITTEN

MSB

R15

215

---'015
DIS
017
a. Normal Mode

PDP-t1
CORE WORD
LSB

MASSBUS
DATA WORD

BIT WEIGHT

--DoJ}
+
D4+}
DB}
+
D12}

Rflj

2°

st CHARACTER
WRITTEN

2nd CHARACTER
WRITTEN

3rd CHARACTER
WRITTEN

011
~

MSB

b. Core

2 15

Dump Mode

PDP-15
CORE WORD
LSB

4th CHARACTER
WRITTEN

--.015
016
017

Rt5

MASSBUS
DATA WORD

- - + D{'

N17

}-2-

BIT WEIGHT

nd-C-HA-R-A-CT-E-R-WRITTEN

2°

} 1st CHARACTER
WRITTEN
N2 --------+ 015 - - - - - - - - - 2 15
MSB

018

Nt
----016
N 9 j - - - - - - - - + 017

Mode
10-1326

Figure 1-10

Data Formats

1-14

CHAPTER 2
MASSBUSINTERFACE

2.1 GENERAL
The Massbus provides the interface between the
RH70 Controller and the TUI6/TM02 Tape System. The Massbus can be up to 120 ft in length and
up to eight drives may be connected in a daisychain configuration. The Massbus consists of two
sections: a Data Bus section and a Control Bus section. These buses are described in the following
paragraphs.

End-of Block (EBL) - This signal is asserted by the
drive at the end of each record (after the last SCLK
pulse). For certain error conditions, where it is necessary to terminate operations immediately, EBL is
asserted prior to the normal time for the last
SCLK. The data transfer is terminated prior to the
end of the record in this case.
Exception (EXC) - This signal is asserted when an
abnormal condition occurs in the drive. The drive
asserts this signal to indicate an error during a data
transfer command (Read, Write, or Write-check).
Exception is asserted at, or prior to, assertion of
EBL and is negated at the negation of EBL.

2.2 DATA BUS
The Data Bus section of the Massbus consists of a
19-bit (18 data bits, plus parity bit) parallel data
path and six control lines (Figure 2-1).

Sync CLK (SCLK), Write CLK (WCLK) - These
signals are the timing signals used to strobe the
data in the controller and/or in the drive. During a
read operation, the RH70 strobes the data lines on
the negation of SCLK and the drive changes the
data on the assertion of SCLK. During a write operation, the controller receives SCLK and echoes it
back to the drive as WCLK. an the assertion of
WCLK, the drive strobes the data lines and on the
negation of WCLK, the controller changes the data
on the data lines.

Parallel Data Path - The parallel data path consists
of an 18-bit data path, designated DOO - D 17, and
an associated parity bit (DPA). The data path is
bidirectional and employs odd parity. Data is transmitted synchronously, using a clock generated in
the drive.

R UN - After a data transfer command has been
written into the control register of a drive, the drive
connects to the data bus. The controller then asserts the RUN line to initiate the function.

2.3 CONTROL BUS
The Control Bus section of the Massbus consists of
a 17-bit (16 bits, plus parity) parallel control and
status data path, and 14 control lines (Figure 2-1).

Occupied (OCC) - This signal is generated by the
drive to indicate "data bus busy." As soon as a
valid data transfer command is written into a drive,
and the command is accepted, the drive asserts
acc. Various errors may cause a drive to be
unable to execute a command. The controller will
time out in these cases, due to no assertion of acc
or SCLK, and the MXF (Missed Transfer Error)
will be set in the controller. acc is negated at the
trailing edge of the last EBL pulse of a transfer.

Parallel Control and Status Path - The parallel control and status path consists of a 16-bit parallel
data path, designated COO - C 15, and an associated
parity bit (CPA). The control and status lines are
bidirectional and employ odd parity.

2-1

0 ATA AND PARITY

[0 (17 : 00) 8 DPA ]

....

)

..".

RUN
OCCUPIED (OCC)
DATA
BUS

END-OF-BlOCK (EBl)
EXCEPTION (EXC)
SYNC ClK (SClK)
WRITE ClK (WClK)
\,.

V
MASSBUS
CONTROllER

CONTROL. STATUS 8 PARITY [C (15:00) 8 CPA]

....

)

v
DR I VE SELECT (DS02 - DSOO)

DRIVE

....

,)
CONTROL TO DRIVE (CTOD)
REGISTER SELECT (RS04: RSOO)
CONTROL
BUS

DEMAND (OEM)
TRANSFER (TRA)
ATTENTION (ATTN)

INIT IALIZE (IN IT)
FAil

Figure 2-1

Massbus Interface Lines

Drive Select, DS (2:0) - These three lines transmit a
3-bit binary code from the controller to select a particular drive. The drive is linked to the Control Bus
when the (unit) select number in the drive corresponds to the transmitted binary code.

Register Select, RS (4:0) - These five lines transmilt
a 5-bit binary code from the controller to the se:lected drive. The binary code selects one of the
drive registers.

NOTE
Ten registers (including the MTCSI register) are prE:sent in the TM02 Tape Controller, designated by
codes 00 - 11. If a register code higher than 1:1 is SE:lected, an Illegal Register (ILR) Error occurs.

Controller-to-Drive (CTOD) - This signal is generatc!d by the controller and indicates the direction in
which control and status information is to be transferred. For a controller-to-drive transfer, the controller asserts CTOD. For a drive-to-controller
transfer, the controller negates this signal.

2-2

Corresponds To:
Massbus
Address

00
01
02
03
04
05
06
07
10

Control & Status 1 Register*
Drive Status
Error
Maintenance
Attention Summary
Frame Count
Drive Type
Check Character
Serial Number
Tape Control

Unibus
Address
(Octal)

MTCSI
MTDS
MTER
MTMR
MTAS
MTFC
MTDT
MTCK
MTSN
MTTC

772440
772452
772454
772464
772456
772446
772466
772460
772470
772472

* This register is shared by the RH70 and the TM02 controller.
The RH70 Massbus Controller Registers are:

Unibus
Address
(Octal)

Control & Status 1
Word Count
Bus Address
Control and Status 2
Data Buffer
Bus Address Extension
Control and Status 3

MTCSI
MTWC
MTBA
MTCS2
MTDB
MTBAE
MTCS3

772440
772442
772444
772450
772462
772474
772476

Demand (DEM) - This signal is asserted by the controller to indicate that a transfer is to take place on
the Control Bus. For a controller-to-drive transfer,
OEM is asserted by the controller when data is present and settled on the Control Bus. For a drive-tocontroller transfer, OEM is asserted by the controller to request data and is negated when the data
has been strobed off the Control Bus. In both
cases, the RS, OS, and CTOO lines are generated
and allowed to settle before assertion of OEM.

Attention (A TTN) - This line is shared by all eight
drives attached to a controller; it may be asserted
by any drive as a result of an abnormal condition
or status change in the drive. An AT A status bit in
each drive is set whenever that drive is asserting the
ATTN line. ATTN may be asserted due to any of
the following conditions:

Transfer (TRA) - This signal is asserted by the
drive in response to OEM. For a controller-to-drive
transfer, TRA is asserted when the data is strobed
and is negated when DEM is negated. For a driveto-controller transfer, TRA is asserted after the
data is asserted on the bus and negated when the
negation of DEM is received.

2-3

An error while no data transfer is taking
place (asserted immediately).

Completion of a data transfer command
if an error occurred during a data transfer (asserted at the end of the transfer).

Completion of a non-data transfer command (such as a space).

The AT A bit in a drive may be cleared by the following actions:
1.

Asserting INIT on the Massbus (affects
all eight drives).

Writing a I into the Attention Summary
register (in the bit position for this
drive). This clears the ATA bit; however,
it does not clear the error.

Commands are of two types: non-data transfer com··
mands (such as Drive Clear, space) and data trans ..
fer commands (such as Read, Write, and 'Write..
check). The command function code bits (05 - 00"
including GO in MTCS1) are OIs - 478 for non ..
data transfer commands and 518 - 778 for data
transfer commands.
2.4.1 Non-Data Transfer Commands
Non-data transfer commands have effect only on
the state of the drive. The controller merely writes
the command word (with GO bit set) into tht~
drive's Control register. At the completion of the
command execution, the drive typically asserts tht:
A TTN line to signal its completion.

Writing a valid command into the Control register (with the GO bit set). Note
that clearing the ATA bit of one drive
does not always cause the ATTN line to
be negated because other drives may
also be asserting the line.

If the non-data transfer command code written into
the drive is not recognized by the drive as a valid
command, the drive will immediately signal an er'·
ror by asserting the ATTN line. The Illegal Func··
tion Error (ILF) is set.

NOTE
There are three cases in which ATA is not reset when
a command is written into the Control register (with
th,~ GO bit set): 1) if there is a Control Bus parity error on the write, 2) if an error was previously set, or
3) if an illegal function code (ILF) is written.

2.4.2 Data Transfer Commands
When any data transfer command code (wi1th the
GO bit set) is written into the drive's Control regis··
ter, the controller expects data transfer on the: Data
Bus to begin thereafter. The controller res~!ts its
RDY (Controller Ready) bit as soon as tht~ data
transfer command code is written into a drive!. The
drive normally responds by asserting the oce line.
The controller asserts RUN and then data is trans··
ferred to or from the specified drive.

Initialize (IN IT) - This signal is asserted by the controller to perform a system reset of all drives. It is
asserted when a 1 is written into the CLR bit (bit
05 of MTCS2) or when Unibus INIT is asserted on
the Unibus. When a drive receives the INIT, pulse,
it immediately aborts the execution of any current
command and performs all actions described for
the Drive Clear command.

Fail - When asserted, this signal indicates that a
power-fail condition has occurred in the controller.
In particular, the drive inhibits reception of the
INIT and DEM signals at the drive.

If an error occurs in a drive during a data transfer
command, the drive asserts the EXC line. This linc~
remains asserted until the trailing edge of the last
EBL pulse. The RH70 Controller always negatei~
the RUN line when it detects EXC asserted, so that
data transfer is terminated at the end of the record
in which the error was signaled.

2.4 COMMAND INITIATION
To initiate a command in a drive via the Massbus,
the controller (or the central processor via the controller) writes a word in the MTCSI register which
causes a word to be written into the drive's Control
register (00). The word contains a command function code in bits 05 - 01 and a GO bit in bit 00.
The GO bit is set when initiating a command. If
the command specified is valid, the drive which has
been addressed by the program executes the
command.

2.5 READING/WRITING DRIVE REGIST1ERS
The process of reading/writing drive registers is ac'·
complished via the asynchronous (Control Bus) portion of the Massbus (Figure 2-1). The RH70
initiates the action by selecting a drive (DS2-·DSO),
selecting a register (RS4-RSO) in that drive, select·
ing a direction of transfer (CTOD), and either reading-writing the register via the 17 bidirectional
control lines [C (15:00) and CPA]. After a deskew
delay to allow the control lines to stabilize, th~!
RH70 asserts DEM. Upon receiving the DEM assertion, the drive checks the CTOD line to ascertain whether a read or write is to occur.

2-4

If a register read operation is specified, the drive
will gate the contents of the specified register onto
the Control B us and issue TRA. When the RH70
receives TRA, it will gate the control lines onto the
Unibus. After a deskew delay, the RH70 asserts
SSYN to the processor. When the processor receives the control data and SSYN, it clears MSYN.
The clearing of MSYN negates SSYN and DEM.
The negation of DEM causes TRA to be negated
and completes the operation.

NOTE
Massbus cables are to be installed per markings on
the cables.

If a register write operation is specified, the RH70
gates the control data onto the Control Bus when it
issues DEM. The drive will transfer the data from
the Control Bus into the specified drive register and
assert TRA, which causes the assertion of SSYN in
the RH70. SSYN is transferred to the processor
and causes MSYN to be cleared. The clearing of
MSYN causes SSYN and DEM to be negated. The
negation of DEM causes TRA to be negated to
complete the operation.

Massbus
Cable A

Table 2-1
Massbus Signal Cable Designations
Cable

The Massbus structure allows a register read operation (asynchronous Control Bus) to occur while a
data transfer (synchronous Data Bus) is taking
place. Any attempt by the RH70 to write a register
in a drive performing a data transfer operation (except for the Maintenance and Attention Summary
registers) will cause the RP04 Drive to set the Register Modification Refused (RMR) error bit (Chapter
4).
2.6 MASSBUS PHYSICAL D.ESCRIPTION
The Massbus consists of 56 signals including data,
control, status, and parity. These signals are routed
between the RH70 and the drives by three 40-conductor flat cables. Since Massbus signal transmission (with exception of the FAIL ~ignal) is
accomplished by differen tial transmitter/receiver
pairs, each cable can accommodate 20 differential
signals.
On the drive end, the cables are plugged into
M5903 Massbus Drive Transceiver modules (slots
AB, -4, -5, -6 in the TM02). The last drive has
M5903 modules with H870 miniterminators which
terminate the bus. On the controller end, each cable
plugs into an M5904 Massbus Controller Transceiver module (described in subsequent paragraphs). Each M5904 module in turn plugs into a
slot (see Figure 7-1) in the 11/70 backplane to complete the signal path.
Table 2-1 shows the Massbus signals and their associated pin assignments.

Pin*

Polarity

Designation

1
2
3
C
D
4
E
5
F 6
H 7
J
8
K
9
L
10
M
11
N
12
P
13
R
14
15
S
T
16
U 17
V
18
W
19
X
20
y
21
Z
22
AA 23
BB 24
CC 25
DD 26
EE 27
FF 28
HH 29
30
11
KK 31
LL 32
MM 33
NN 34
pp
35
RR 36
37
SS
TT 38
UU 39
VV 40

MASSDOO

+
+

MASS DOl

MASSD02

+
+

MASSD03

MASSD04

+
+

MASS DOS

MASS COO

+
+

MASS COl

MASS C02

+
+

MASS C03

MASSC04

+
+

MASS COS

MASS SCLK

+
+

MASS RS3

*Alternate pin designation schemes

2-5

MASS ATTN

MASS RS4

MASSCTOD

+
+

MASSWCLK

MASS RUN

SPARE
GND

Table 2-1 (Cont)
Massbus Signal Cable Designations

Table 2-1 (Cont)
Massbus Signal Cable Designations
Cable
Massbus
Cab!eB

Pin*

A
B

D
E
F
H
J

K
L
M

N
P
R
S
T
U
V
W
X

Y
Z
AA
BB

DD
EE
FF
HH
11

KK
LL
MM

NN
PP
RR
SS
TT
UU
W

Polarity

Design ation

Cable

Pin *

MASS D06

Massbus
Cable C

1
2
3
4
5
6
7
8
9
10
11

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

+
+

MASS D07

MASS D08

D
E

MASS D09

F
H

+
+

MASS D10

+
+

MASS Dll

L
M

MASS C06

+
+

MASS C07

MASS C08

N
P
R
S
T

U
V

+
+

MASS C09

W
X

MASS CI0

Y
Z

+
+

MASS Cll

MASS EXC

MASS RSO

DD
EE

MASS EBL

FF
HH
11

MASS RS1

MASS RS2

LL
MM

+
+

NN
PP
RR
SS
TT

MASS I NIT

MASS SPI

SPARE

GND

Polarity

Design:dion

MASS D12

+
+
_.

MASS 013

MASS 014

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

*Alternate pin designation schemes

2-6

+
+

MASS 015

MASS 016

+
+

MASS 017

MASS DPA

+
+
..

MASS C12

MASS C13

+
+

MASS C14

MASS CIS

+
+

MASS CPA

..
+
+

MASS acc

MASS TRA

MASS OSI

MASS DS2

+
+

MASS DEM

MASS DSO

MASS SP2

MASS FAIL

GND

CHAPTER 3
OPERATION AND PROGRAMMING

3.1 GENERAL
Sixteen 16-bit registers are employed to interface the RH70
Massbus Controller to the TM02/TUI6 tape system. These
registers are loaded and read under program control via the
Unibus. The tape system is monitored by status and error
indicators in these registers. Figure 3-1 shows the various
device registers and their locations. Six of the sixteen
registers are located entirely in the RH70 and nine are
located entirely in the TM02. The sixteenth register
(MTCSI control and status register) is shared by both the
RH70 and the TM02. Bits 15 through 13 and bits 10
through 6 of this register are stored in the RH70 while bits
12, 11, and 5 through 0 are generated by the TM02. Table
3-1 shows the various subsystem registers and their
respective addresses. The following paragraphs describe the
registers and their bit usage in detail.

Table 3-1
RH70 and TM02/TUI6 Device Registers

Mnemonic

MTCSI *

Control and Status 1
(shared by RH70 and TM02)
Word Count
Bus Address
Frame Count
Control and Status 2
Drive Status
Error
Attention Summary
Check Character
Data Buffer
Maintenance
Drive Type
Serial Number
Tape Control
Bus Address Extension
Control and Status 3

MTWC*
MTBA*
MTFC
MTCS2*
MTDS
MTER
MTAS
MTCK
MTDB*
MTMR
MTDT
MTSN
MTTC
MTBAE
MTCS3

3.2 DEFINITIONS
This paragraph describes one of the Massbus Signals that are
used to operate status information.

Attention Active (ATA) - The AT A bit is a TM02 bit that
indicates that the TM02/TUI6 requires servicing 1) because
it has become ready after completion of a non-data transfer
operation, 2) because of an error condition, or 3) because
of an important internal status change (Paragraph 3.7.8).

Unibus
Address
772440
772442
772444
772446
772450
772452
772454
772456
772460
772462
772464
772466
772470
772472
772474
772476

*RH70 Registers

Transfer Error (TRE) - The TRE bit is located in the
RH70 and indicates that an RH70 error or a TM02 error
has occurred while a data transfer is in progress. Writing a 1
into TRE does not affect the ERR bit in any drive.
Similarly, a Drive Clear command does not affect TRE in
the RH70.

Ready, Drive Ready (RDY, DRY) - RDY is the "ready"
indicator for the RH70 controller. When RDY is asserted,
the RH70 is ready to accept a data transfer command. DRY
is the "ready" indicator for each drive. To successfully
initiate a data transfer command, both of these bits must be
asserted. However, a non-data transfer command (e.g.,
Search, Drive Clear) may be issued to a drive any time DRY
is asserted, regardless of the state of the RDY bit.

Special Conditions (SC) - The SC bit indicates that a TRE
has occurred or that ATA has set on one of the drives.

3-1

----------------------------------------------~

RH70 CONTROLLER
15

MTCSI

131211 10

6 5

c=:=J::= ""l~-----rl - ::= =: ::= ::= J

MTwcl
MT8A

~I======================:

C =: =: =: =: ::= =: ::= :: :: ::= =: :: :: :: =: ~

MTFC
MTCS2 .....

C____________--'

====

=::

15
MTCS1 [:

=:: = :: = = = : = ==J

=: =: =: =: =: := := := := =: =: =: :: ::= := J
MTDT :::: ::= =: := := =: =: =: :: ::= := =: := =: :: =: J
MTSN [ := := := := =: := := := := =: =: := := : := J
MTTC :::: ::= ::= ::= ::= ::= ::= =: ::= =-= ::= ::= =: =::= J
MTMR ::::

:= :: := := := =: =: =: := := := := =: =: =: J

MTCS2 [

MTER
MTAS

MTI)B 1....._ _ _ _ _ _ _ _ _ _ _ _---1

6 5

MTFC r='--_ _ _ _ _ _ _ _ _ _ _ _ _~

MTDS

MreK::::::==::=::==::==::===::=::=::==::=J

TM02 #1

1312 1110

:= =: CJ:= :: :: =: """11----.....,1
MTWC [ ::= ::= ::= ::= ::= ::= := ::= =: := := ::= ::= ::= ::=]
MTBA :::: ::= ::= ::= ::= := ::= := :: ::= ::= ::= ::= :: ::= ::= J

MTDS :::: ::= ::= = =
= :: ::
= =
MTfR rL -_ -_ -_ _
- _
- _
- _
- _
- _
- _
- _
- _
- _
- _
- _
- 1J
MTM :::::: :: :: ::

TM02 #0

================~

C==================~
C
IAT4
MTCK L
1
MTDB [ ::= ::= ::= ::= :: ::= ::= ::= :: ::= :: ::= ::= ::= := J
MTMR
MTDT

L==================:::::::
L,______________--'

MTSN
MTTC

c:::====================~
L
__________---'

MTBAEc==________________~

MTBAE [~~ = ~ ~ -_ -=- -_- _-_- ~ ~ ~ ~ ~ :_

MTCS3 1....._______ ,_ _ _ _ _ _ _ _- - '

MTCS3 ~

NOTES'
1. MTCSI shared between RH70 and TM02
bits 15-13
10-6 are stored In RH70
bits 12, 11, a 5-0 are generated by TM02

2. Each drive Is assigned an attention summary
bit in the bit location corresponding to it's
unit no.
3. Location of registers denoted by solid lines;
dotted lines ore for reference only

=~ ::= ::= -=- -=- ~ ~ __ -=- =~ _-_-_- ~

1312 1110

6 5

CJ ::= ::= ::= :: r===::=J
MTWC [ := =~ ::= ::= =: =: ::= =: := ::= :~ := := ~= := 1
MTCSI [

::= ::=

MTBA [

::= =~ ::= ::= ::= ::= ::= ::=

=: ::= :~ :: ::= :~ ::= J

MTDS

r==
===::::J
:= =: := ::= =: =: ::= ~~ ::= ::= := =: J
r==
__:=J

MTER

===::=J

MTAS

=::::::EL]

MTFC

MTCS2 [

MTCK

::=

r===============::::::::l

= =: = : :: :: :: ::= :: ::= :: := :: ~~ = J
L:==
==:=J
MTDT L:== ______ ==:=J
MTDB [
MTMR

r==

===:J
C===============:J
MTBAE[==~-~ = = ~ _-_~~ ~ =~~

MTSN

MTTC

MTCS3 ~ ~ -=-.~

MTCS1,MTCS2,MTCS3 - Control and
MTWC - Word Count
MTBA - unibus Address
MTFC - Frame Count
MTDS - Drive Status
MTER - Error
MTAS - Attention Summary
MTCK - Check Character
MTDB - Data Buffer
MTMR- Maintenance
MTDT - Drive Type
MTSN - Serial Number
MTTC - Tape Control
MTBAE - Bus Address Elttension

-_-_-~ _- ~ ~ ~: =~- ~:: ~ ~~

Statu~;

11-2976

Figure 3·1 Device Registers

3-2

When a data transfer command is successfully initiated,
both RDY and DRY become negated. When a non-data
transfer command (such as Search) is successfully initiated,
only the DRY bit becomes negated. Some non-data transfer
commands (such as Drive Clear) take so little time to
execute, that the program will never see the negation of the
DRY bit.
The assertion of RDY after the execution of a data transfer
command will not occur until the DRY bit is set and the
controller (RH70) is done.
If any command other than Drive Clear is issued to a drive
which has ERR (a summary error bit located in each drive)
asserted, the command is ignored by the drive. If a data
transfer command is issued to a drive that has ERR
asserted, the drive does not execute the command, and the
missed transfer errox (MXF, bit 9 in the MTCS2 register)
occurs in the RH70.

Data buffer

MTBA Bus Address register and MTBAE Bus
Address Extension register.

Unit select U(02:00), IE, BAI, PAT, IPCK 0-3,
and DBL.

Errors, function code, and MTDA register in all
drives connected to the RH70 (by assertion of
the Massbus INIT signal).

RH70 Error Clear - RH70 error clear is the action of
writing a 1 into the TRE bit (bit 14 of MTCS1). This causes
all controller errors to be cleared (MTCS2 - bits 15
through 8, MTCSI bits 14 and 13, and MTCS3 - bits 15
through 11).

Clearing Methods
Controller Clear - Controller clear is the action of writing a
1 into the CLR control bit (bit 5 of MTCS2). This causes
the following to be cleared:

Drive Clear - Drive Clear is a command code (11s) that
causes errors and the function code to be cleared in the
drive selected by U(02:00).

All controller errors (MTCSI - bits 15 through
13, MTCS2 - bits 15 through 8, MTCS3 - bits
15 through 11).

Table 3-2 shows the various methods used to clear the
magnetic tape system.

Table 3-2
Results of Program-Controlled Clearing
RESULTS
Clear All
RH70 Errors

Clear
Data
Buffer

Clear BA, BAE,
U(02:00), IE, PAT,
BAI, IPCK, DBL

Assert Massbus
INIT

Unibus INlT
(Reset instruction
execu tion or
console reset)

Controller Clear
(Bit 5 in MTCS2+-1)

Issue a Data
Transfer command
(with GO==l)

RH70 Error Clear
(Bit 14 in MTCSl+-l)

Action

Clear GO, ATA, ERR,
and errors in the drive
X

(all 8 drives)

Clear SSC
X

(all 8 transports)

Drive Clear
(Function code with
GO = 11 8 )

(selected
drive only)

3-3

(selected
transport
only)

Controller Error - An error is asserted in the MTC~
register as indicated below:

3.3 INTERRUPT CONDITIONS
The RH70 generates an interrupt in the PDP-II CPU due to
the following conditions:
a.

Upon termination of a data transfer (if interrupt enable is set when the RH70 becomes
"ready").

15
14
13
12
11
10
9
8

Interrupt=(RDY+-I) o(IE)
b.

Error
Clas:s

Bit

Upon assertion of attention or occurrence of a
controller error (while the controller is not
busy and interrupt enable is set).

DLT (Data Late)
WCE (Write Check Error)
PE (Parity Error)
NED (Nonexistent Drive)
NEM (Nonexistent Memory)
PG E (program Error)
MXF (Missed Transfer Error)
MDPE (Massbus Data Parity Error)

A
A
A
A
A
A
B
A

Interrupt=(SC+-I)o(RDY)o(IE)
c.

Any of these errors sets TRE. The RH70 terminates th
data transfer immediately, but waits for DRY which OCCU]
at the inter-record gap before becoming Ready.

When the program writes Is into IE and RDY
in MTCS 1 at the same time.

Drive Error - An error occurs in the drive. The drive se1
ERR in the MTDS register and at least one bit in the MTEl
register. The ERR bit causes TRE, SC, RDY, DRY, and th
AT A bit to be asserted.

lnterrupt=(IE+-I) (RD Y+-1)
0

CAUTION
Read-Modify-Write instruction (BIS, BIC,
etc.) to MTCS 1 with IE bit set will cause
an immediate interrupt.

Program-caused Abort - By performing a controller de~
or a reset instruction, the program can cause Ma:;sbus ][NI'
to be asserted by the RH70, which aborts all operations 0
all drives attached to the controller. (A program-cause
abort can also be caused by Drive Clear.) Status and errc
information is lost when any of the above conditions OCCUl
The RH70 and TM02/TU16 become Ready immediately.

Read-Modify-Write instruction (BIS, BIC,
etc.) to MTCS3 with the IE bit set will
not cause an immediate interrupt. In
these cases, the interrupt will occur upon
normal completion of the operation.

3.5 TWU16 COMMANDS
TWU16 commands are classified as data transfer or non
data transfer commands. Table 3-3 lists all the command
with a brief description of each. Before a command i
initiated, certain parameters are specified by the progran
for each command. These parameters are listed in Tabl(
3-4. For example, in an Erase operation, it is only necessar)
to specify the TM02 and the TUI6.

3.4 TERMINATION OF DATA TRANSFERS
A data transfer that has been successfully started may
terminate in the following ways:

Assertion of RDY - This is the normal termination and is
caused by detection of the inter record gap.

3-4

Table 3-3
Command Function Codes
Function Code F(O-S)
(octal)

Operation

Description

NoOp

Performs no operation. Clears GO bit in Control register.

Rewind Off-line*

Initiates a rewind on selected transport and places
it off-line.

Clears GO bit.

Sets the following bits in the Status register:
Drive Ready (DRY)
Slave Status Change (SSC)
Attention Active (ATA)
Rewind off-line causes one interrupt only
indicating rewind underway and transport off-line.

Rewind

Initiates a rewind to BOT marker on selected
transport and clears the GO bit.

Sets DRY, PIP, and ATA bits in the Status register
during rewind.

When BOT is sensed, sets SSC and clears PIP.
Rewind causes two interrupts:
a.

Rewind underway

SSC when BOT is sensed (rewind 'job
done').

Drive Clear

Similar to Initialize. Resets all TM02 and selected
transport logic only. Does not affect unselected transports.

Erase

Erases approximately 3 in. of tape. Clears GO bit and
sets AT A on termination.

Write Tape Mark

Writes a special tape record on the selected transport.
Clears GO bit and sets AT A bit on termination (paragraph 1.6.1.2).

Space Forward

Moves tape forward (toward EOT) on the selected
transport over the number of records specified by the
Frame Count register. Aborts space operation if TM or
EOT is detected prior to specified frame count. Clears
GO bit and sets ATA on termination.

*Requires manual intervention to return transport on-line.

3-5

Table 3-3 (Cont)
Command Function Codes
Function Code F(O-S)
(octal)

Descrip tion

Operation

Space Reverse

Moves tape in reverse (toward BOT) on the selected
transport over the number of records specified by the
Frame Count register. Aborts space operation if TM or
BOT is detected prior to specified frame count. Clears
GO bit and sets AT A on termination.

Write Check Forward

Does a word-by-word comparison of specified memory
locations with the tape record read from tape in the
forward direction.

Write Check Reverse

Same as write-check forward except for reverse tape
motion.

Write Forward

Writes forward one tape record on the selected
transport. Record length is determined by Frame Count
register. Clears GO bit on command termination.

Read Forward

Reads forward one tape record on the selected transport.
Qears GO bit on command termination.

Read Reverse

Reads reverse one tape record on the selected transport.
Clears GO bit on command termination.
NOTE
Do not use this mode unless whole
PDP-II data words were written in the
record.

command, will cause an interrupt if IE is set. If a data
transfer and a non-data transfer command are in progress
(on different drives), an interrupt will occur only on the
assertion of RDY even though the Attention bit (asserted
on completion of the non-data transfer command) may be
asserted before the RDY bit. Data transfer commands are
read, write, and write check and cause the transfer of dlata
over the data bus (synchronous) portion of the Massbus.
The parameters specified by the program during the
issuance of these commands are described as follows:

3.5.1 Non-Data Transfer Commands
Non-data transfer commands do not cause the RH70 to
become busy (RDY asserted). Therefore, other commands
can be issued to other drives while a non-data transfer
command is in progress. A non-data transfer command is
terminated when the Attention bit for the specified drive is
asserted. The assertion of the Attention bit, upon completion of a non-data transfer command, will cause an
interrupt if the IE bit is set and RDY is asserted.
3.5.2 Data Transfer Commands
Data transfer commands cause the RH70 to become busy
(RDY negated). No other commands can be issued while a
data transfer command is in progress. Termination of a data
transfer command is indicated by the re-assertion of RDY.
Assertion of RDY, upon completion of a data transfer

Bus Address - The bus address represents the star1tin~
memory location that the data will be read from (for (l
write) or written into (for a read). The address occupies the
16 bits of the MTBA bus address register and six bits of the
MTBAE bus address extension register.

3-6

through 2 of this register are slave select bits which select
the appropriate tape transport (designated slave). Bits 4
through 7 of this register are the format select bits which
specify Massbus-to-tape character formatting during a write
(or tape character-to-Massbus formatting during a read
operation). Bits 8 through 10 of this register specify the
tape density (phase-encoded or one of four possible non
return-to-zero formats).

Selected TM02 Tape Controller - The TM02 is selected by
writing the MTCS2 register in the RH70. Bits 0 through 2
of the register are the unit select bits that spe~ify the
desired TM02.
Word Count - The word count is a count of the number of
words to be transferred to or from the tape drive. The
MTWC word count register is loaded with the two's
complement of the number of words to be transferred and
is incremented toward zero for each word transferred to or
from memory. Overflow to zero terminates the Unibus
transfer.

3.5.2.1 Write Data Transfer - After the above parameters
are specified, the data transfer is initiated by loading a write
command function code in the MTCS 1 register in the RH70
and setting the GO bit. This process logically connects the
data portion (synchronous) of the TM02 to the RH70 as
this is the path that the data will be transferred over.

Frame Count - The MTFC frame count register specifies
the number of frames (bytes) to be written on tape" Each
sixteen-bit PDP-II word is divided into two frames.
Consequently, the frame count register is loaded with twice
the number in the MTWC register for normal or 15 mode or
four times the number in the MTWC register for core dump
mode. The frame count register is loaded with the two's
complement of the number of frames to be written.
Overflow to zero terminates transfers on the slave bus.
Since the frame count register is located in the TM02 tape
controller, writing this register requires the RH70 to
perform a Massbus cycle. If the frame count register
overflows before word count, the transfer may be terminated by FCE (see below). If word count overflows before
frame count, the rest of the record is zero-fIlled.

Memory cycles are initiated by the RH70 and the data
words from memory are transferred to the input of the data
buffer (Figure 1-5).
For each data word transferred, the word count is
incremented by 1 and the bus address is incremented by 2.
If double words are transferred, the bus address is incremented by 4. The data words are clocked into and
"bubble" through the data buffer. When the first data word
reaches the top, it is automatically clocked into the output
buffer (OBUF). When the data buffer is filled and a word is
in OBUF, the RH70 asserts the RUN signal which signals
the TM02 to begin assembling characters and writing on
tape.

Normally, the frame count register is set to twice the word
count in normal and 15 mode. In core dump mode, the
frame count is set to four times the word count. If less than
two frames of the last word are desired in normal or 15
mode, the frame count register may be loaded with an odd
number. If less than four frames of the last word are desired
in core dump mode, the frame count register may be loaded
to 1, 2, or 3 less than four times the word count. For
example, if 21 frames were to be transferred in normal
mode, the frame count register is set to the two's
complement of 21 and the word count register is set to the
two's complement of 11. Frame count would overflow
before word count and the last byte would be transferred as
Os. No FCE occurs in this case. Frame count need not be
specified in a read operation or a write-check operation and
is automatically reset in these cases. At the end of a read or
write-check operation, the frame count is equal to the
number of frames read from tape.

The TM02 accepts the first data word, converts it into two
tape characters, and outputs it to the TU16 tape transport.
It then sends a sync clock (SCLK) signal to the RH70
requesting another data word. The RH70 receives SCLK
and echoes it back as write clock (WCLK) along with the
next data word. The TM02 assembles this into two tape
characters, transfers it to the TUI6, and issues another
SCLK. The process continues until frame count overflow is
detected indicating that the desired number of characters
have been transferred.
NOTE
If the word count register is set to less than
twice the frame count, word count overflow
will occur first. This causes the un line to be
negated and will cause Os to be written in the
rest of the record. If the word count register is
set to more than twice the word count, frame
count overflow will occur first and may cause a
frame count error (FeE).

Selected Tape Transport, Format Character Packing and
Tape Density - These parameters are specified by the
program by writing the MITC tape control register. Bits 0

3-7

Table 3-4
TWU16 Commands and Required Parameters
Word
Count

Slave
Select

Read,
Read Reverse

write

write-check,
write Check Reverse

Command

Frame
Count

Bus Address/Ext.

Unit
Select

Density

Format

function Code

space

Erase

R.ewind,
Rewind Off-line

write Tapemark

X
X

NOP
Drive near

Notes:

(1)

Frame count for a space operation is
loaded with 2's complement of number
of records to be spaced.

(2)

GO bit must be loaded last.
The order of specifying the other
parameters is immaterial.

(3)

3.5.2.2 Read Data Transfer - In a read operation, the data
words are transferred from the tape drive to memory via
the TM02 and RH70 and cache. The data path functionally
consists of the TM02/TU16, RH70 data buffer, cache
memory and main memory (Figure 1-5).

X indicates that the item must be specified,
e.g., word count specified for read, write,
and write check.

main memory via cache. When memory is ready, it w
accept the data.
The TM02 waits for the next two characters and, on tl
negation of SCLK, transfers the second word to the RH7
The process continues until the inter-record gap is detecte
At this point, the TM02 sends EBL to the RH70
terminate the data transfer.

The data transfer is initiated by loading a Read command
function code in the MTCSI register in the RH70 and
setting the GO bit. This process logically connects the data
portion (synchronous) of the TM02 to the RH70 as this is
the path that the data will be transferred over.

NOTE
If the Word Count register overflows before the
inter-record gap, only the number of words
designated in the Word Count register will be
transferred. In this case, the RH70 will ignore
the remaining words and wait for EBL illl the
drive to terminate the data transfer. If EBL
occurs before word count overflow, a frame
count error (FCE) is flagged.

The Run line is asserted by the RH70 and when the tape is
up to speed, the TM02 receives two tape characters from
the TU16 tape transport, assembles them into a 16-bit
word, and sends it to the RH70 data buffer accompanied
by SCLK. When the data word sequences through the data
buffer to OBUF, the RH70 initiates a memory request to

3-8

3.5.2.3 Write-Check Data Transfer - The third type of
data transfer is a write-check and is initiated when a
write-check function is specified in the MTCS 1 register and
the GO bit is set. In this operation, a record which has
previously been written onto the tape is read from the tape.
This data is compared to the data in memory originally
used to write on the tape. The comparison is accomplished
by Exclusive OR gates, and if any of the bits fail to
compare, a write-check error occurs. This method allows
automatic verification that the data on tape agrees with the
contents of memory.

become busy (RDY negated) until the completion of tll
operation. When the controller is busy, no further da1
transfer commands may be issued (see PGE bit 10 j
MTCS2). Non-data transfer commands, however, may t
issued at any time and to any drive which is not busy.
While a data transfer is in progress, unit select bits U(02:0(
in the MTCS2 register may be changed by the program t
issue a non-data transfer command to another drive. Th
will not affect the data transfer.
When a non-data transfer command code is written int
MTCS 1 while a data transfer is taking place, only the eve
(low) byte of MTCSI should be written. This will prever
the program from unintentionally changing MTCSI statl
bits (AI6, A17) if the transfer is completed just before tl
register is written. (While the RDY bit is negated, the RH7
prevents program modification of these control bits eve
when the write is done into the odd byte.)

3.5.2.4 Data Transfer Rates - The data transfer rate from
the drive is determined by the frequency of the data on
tape. The basic data transfer rates are listed below:
PE
NRZ

1600 BPI - 14 Ms/character
800 BPI - 28 MS/ character
556 BPI - 40 Ms/character
200 BPI - 112 MS/ character

Figure 3-3 shows the MTCSI bit format and Table 3provides a description of each bit.

3.6 REGISTER DESCRIPTIONS
The following paragraphs provide a description of each bit
in the RH70 and TM02 registers. Figure 3-2 shows each
register and the associated bits in each register.

3.6.2 Word Count (MTWC) Register (772442)
This register is loaded by the program with the 2
complement of the number of words to be transferre,
During a data transfer, it is incremented by 1 each time
word is transmitted to or from memory.

3.6.1 Control and Status 1 (MTCS1) Register (772440)
This register is utilized by both the controller and the mass
storage device to store the device commands and hold
operational status. Register bits 0 through 5, 11, and 12 are
dedicated for use by the drive and are physically located in
each drive attached to the controller. When reading or
writing this register, the selected drive (indicated by bits 2
through 0 in the MTCS2 register) will respond in those bit
positions.

Figure 3-4 shows the MTWC bit format, and Table 3
provides a description of each bit.
3.6.3 Bus Address (MTBA) Register (772444)
This device register is used by the RH70 to address tl
memory location in which a transfer is to take place. TI
MTBA register forms the lower 16 bits of address whi(
combine with MTBAE bits 05 through 00 to create tl
22-bit memory address. This register should be loaded t
the program with the starting memory address. Durir
forward operations, this register is loaded with the lowe
value memory address, while in reverse operations, tb
register is loaded with the highest value memory addres
Each time a data transfer is made, the register is incr
mented by 2. If a double data word is transferred, tl
register is incremented by 4. For read reverse operation
the register is decremented by two for a single word da
transfer or four for a double word transfer. If the BAI (Bl
Address Increment Inhibit) bit (bit 03 of MTCS2) is set, tl
incrementing of the MTBA register is inhibited and ::
transfers take place to or from the starting memory addres
Figure 3-5 shows the MTBA bit usage, and Table 3
provides a description of each bit.

When the program reads, writes a word, or writes the low
byte of this register, a register cycle will be initiated to the
selected drive over the Massbus. If the unit selected does
not exist or respond, a NED (non-existing drive) error will
result. The program may, however, write the upper byte of
this register without regard to the unit selected and without
affecting any drive.
Register bits 0 through 5 indicate the command to be
performed and are actually stored in the selected drive. The
controller will always interrogate the command code being
passed to the drive by the program and will prepare for the
appropriate memory cycle required by data transfer operations. Data transfer command codes are deSignated by 518
through 778 (always odd since the GO bit must be asserted
to execute the function) and will cause the controller to

3-9

MTCS' ;:':::~5)! SC !TR+, 0IOVAI 0IA'++OVI IE I F41 F31 F21 F m
772442
MTWC
(Table 3-6) 1...---L_-L-_...I...-.--J__-.l.._-1-_l...---L_-L-_...I...---..JL.....--.l.._-1-_l...MTBA

772444
(Table 3-7) '-----'-_....I-_..L-...--I__--1.._-L-_"-----'-_--'-_..L-...--I'----1.._-'-_"--,
772446

MTFC

(Table 3-8) 1...---L_. ..J...._...I...---..J~_-.l.._-1-_l...---L_-L-_...I...---..JL.....--.l.._...1-_l...---L_....I

MTCS2 ~:'::~~9) OLT! weE! PE !NED! NE+G+X+DPl OR I IR ICL+AT IBAI IU21 U~

MTER

772454

MTAS

MTCK

MTDB

772460
(Table 3-14)
772462
(Table 3-15)

772466
MTDT
(Table 3-17)
772470
MTSN

(Table 3-18)
772472

MTTC

MTCS3 772476
(Table 3-21)
11-2769

Figure 3-2 RH70/TM02 Register Summary

3-10

LOCATED IN
CONTROLLER

LOCATED IN
DRIVE

LOCATED IN
CONTROLLER

LOCATED IN
DRIVE
11- 2975

Figure 3-3 Control and Status Register I-Bit Usage
Table 3-5
Control and Status 1 Register Bit Assignments
Bit

Set By/Cleared By

Remarks

SC
Special condition
Read only

Set by TRE, ATTN, or Massbus control parity error. Cleared by Unibus
INIT, controller clear, or by removing
the ATTN condition.

SC=TRE+ATTN+MCPE

TRE
Transfer error
Read/write

Set by DLT, WCE, PE,NED, NEM,
PGE, MXF, MDPE, or a drive error
during a data transfer. Cleared by
Unibus INIT, controller clear, RH70
error clear, or by loading a data
transfer command with GO set.

TRE=DLT+WCE+PE+NED+NEM
+PGE+MXF+MDPE+(EXCp· EBL)

MCPE
Massbus control
bus parity error
Read only

Set by parity error on Massbus control
bus while reading a remote register
(located in the drive). Cleared by
Unibus INIT, con troller clear, RH70
error clear, or loading a data transfer
command with the GO bit set.

Parity errors that occur on the
Massbus control bus while writing a
drive register are detected by the drive
and cause the PAR error (MTER register, bit 03) to set. Parity checking
occurs at the completion of the register cycle (an MCPE, when reading the
MTCS1 register, would not be indicated on the same cycle).

Not used

Always read as a O.

DVA
Drive available
Read only

Always a 1 in the TM02 when read
from an existing drive. Unit number in
MTCS2 is an existing drive.

Not used

Always read as a O.

09
08

A17
A16
Unibus address
Read/write

Upper extension bits of the MTBA
register. Cleared by Unibus INIT, controller clear or by writing Os in these
bit positions.

3-11

Used in dual port drive applications.

These bits cannot be modified while
the RH70 is performing a data transfer
(ROY negated). Incremented by a
carry from the MTBA register during
data transfers to/from memory. These
bits can also be set/cleared through the
MTBAE register.

Table 3·5 (Cont)
Control and Status 1 Register Bit Assignments
Bit

Set By/Cleared By

Remarks

RDY
Ready
Read only

RDY normally=l. During data transfers, RDY=O. The assertion of RDY
(transfer complete or TRE) will cause
an interrupt if IE=:1.

Indicates controller status. When set,
the controller will accept any command. When cleared, the controller is
performing a data transfer command
and will allow only non-data transfer
commands to be executed.

IE
Interrupt enable
Read/write

IE is a control bit which can be set
only under program control. When
IE=I, an interrupt may occur due to
RDY or A TIN being asserted (Paragraph 3.4). Cleared by Unibus INIT,
controller clear, or automatically
cleared when an interrupt is recognized by the CPU. When a 0 is written
into IE by the program, any pending
interrupts are cancelled.

A program-controlled interrupt may
occur by writing Is into IE and RDY
at the same time. This bit can be
set/ cleared through the MTCS3 regis ..
ter.

F4-FO are function (command) code
control bits that determine the action
to be performed by the RH70 and
TM02/TU16 as shown below.

The function code bits are stored in
the selected drive. Data transfer com··
mands, defined as F4 (F3+F2), always
cause the RH70 to become busy.
(RDY negated.) All other commands
are ignored by the RH70 Controller.

05-00
F4-FO
and GO bit
Read/write

03
07
II

25
27
31

33
51
57
61
71
77

F4 F3 F2 FIFO GO
0 0 0 0 0
0 0 0 0 I
0 0 0 .I I I
0 0 I 0 0 I
0 I 0 1 0 I
0 I 0 1 I
0 I I 0 0
0 I
0 I I
I 0
0 0 I
0 I 1 I I
I 0 0 0
I I I 0 0
I I I 1 I I

Function
No operation
Rewind off-line
Rewind
Drive clear
Erase
Write tape mark
Space forward
Space reverse
Write check forward
Write check reverse
Write forward
Read forward
Read reverse

The GO bit (MTCS 1, bit 0) must be
set to cause the controller or drive to
respond to a command. The GO bit is
reset by the drive at the end of the
operation.
Cleared by Unibus INIT or controller
clear (will abort command execution
in all drives).

3-12

CP-1326

Figure 3-4 Word Count Register Bit Usage

Table 3-6
Word Count Register Bit Assignments
Bit

Set By/Cleared By

Remarks

IS-00
WC
Word count
Read/write

Set by the program to specify the
number of words to be transferred (2's
complement form). This register is
cleared only by writing Os into it.

Incremented for each word transferred
to or from memory.

CP-1327

Figure 3-5 Bus Address Register Bit Usage

Table 3-7
Bus Address Register Bit Assignments
Bit

Set By/Cleared By

Remarks

15- BA 15-01
01
Bus address
Read/write

Loaded by the program to specify the
starting memory address of a transfer.
Cleared by Unibus INIT or by controller clear.

The MTBA register is incremented or
decremented by 4 for each double
data word transferred to or from
memory. For Single-word operation,
the register is incremented or decremented by 2.

Not used.

Always read as a o.

during a space operation, this register is incremented each
time a record is detected. The register output may be read
by the controller at any time; but the controller can only
write into this register when the transport is not performing
a space or data transfer (GO negated).

3.6.4 Frame Count (MTFC) Register (772446)
The frame count register is a 16-bit, read/write register that
counts tape events. During a data transfer operation
(read/write), this register is incremented each time a tape
character is transferred to or from the tape. However,

3-13

For a write operation, the frame count register is loaded,
prior to write initiation, with the 2's complement of the
numbe~r of tape characters to be written. In NRZ mode, the
minimum number of characters that can be written is 13.
During the writing process, the frame count register is
incremented each time a tape character is recorded. Normal
write data transfer termination is accomplished when the
frame count register overflows to zero. For a space
operation, the frame count register functions similarly to a
write, except it is loaded with the 2's complement of the
number of records to be spaced and is then incremented
each time a record is detected. Space termination is
accomplished when the register overflows to zero. For a
read or write check operation, this register is automatically
reset prior to read initiation. The register is then incremented each time a tape character is read. The register is
not incremented for check characters (LRCC, CRCC).
Thus, at the end of the read operation, the frame count
register contains a count of the number of characters read.

Figure 3-6 shows the frame count register bit usage anc
Table 3-8 provides a description of each hit.
3.6.5 Control and Status 2 (MTCS2) Register (772450]1
This register indicates the status of the controller anc
contains the drive unit number U(02:00). The un:lt numbel
specified in bits 02 through 00 of this register indicate!
which drive is responding when registers are addressed ltha1
are located in a drive.
These are:
MTCS 1 (bits 5 through 0, 12 and 11)
MTDS
MTDT
MTCK
MTER
MTMR
MTTC
MTFC
MTSN
Figure 3-7 shows the MTCS2 bit usage, and Table 3-S
provides a deSCription of each bit.

FC
00
CP-1328

Figure 3-6 Frame Counter Bit Usage

Table 3-8
Frame Counter Bit Assignments
Set By/Cleared By

Remarks

Cleared by writing Os in the bit locations

Designates in 2's complement form the
number of records to be spaced over,
characters to be written, or characters
that have been read. Initiating a write
or space command when the frame
count register is loaded with zeros
implies a count of 21 6.

Bit
15-00
FC 15-00
Frame count
Read/write

I DLT I weE

NED

I NEM I PGE I MXF IMDPE I OR

CLR

PAT

I SAl

U0
11-297'1

Figure 3-7 Control and Status Register 2-Bit Usage

3-14

Table 3-9
Control and Status Register 2 Bit Assignments
Bit

Set By/Cleared By

Remarks

DLT
Data late
Read only

Set when the controller is unable to
supply a data word during a write
operation or accept a data word during
a read or write··check operation at the
time the drive demands a transfer.
Cleared by Unibus INIT, controller
clear, RH70 error clear, or loading a
data transfer command with GO set.

DLT causes TRE. Buffering is 8 10
words deep in the controller, and a
DLT error indicates a severely overloaded system.

WCE
Write check error
Read only

Set when the controller is performing
a write-check operation and a word on
the tape does not match the corresponding word in memory. Cleared by
Unibus INIT, controller clear, RH70
error clear, or loading a data transfer
command with GO set.

WCE causes TRE. If a mismatch is
detected during a write-check command execution, the transfer terminates and the WCE bit is set. The
misma tched data word from the tape
drive is displayed in the data buffer
(MTDB).

PE
Parity error
Read/write

Set if a data parity error from memory
is detected while the controller is
performing a write or write-check
command. Cleared by Unibus INIT
con troller clear, RH70 error clear, or
loading a data transfer command with
GO set.

PE=APE+DPEOW+DPEEW
APE - address parity error
DPEOW - data parity error odd word
DPEEW - data parity error even word

NED
Non-existent drive
Read only

Set when the program reads or writes a
drive register (CSl, DS, ER, MR, FC,
DT, CK, TC, or SN) in a drive
[selected by U(02:00)] which does
not exist or is powered down. (The
drive fails to assert TRA within 1.5 p,s
after assertion of DEM.) Cleared by
Unibus INIT, controller clear, RH70
error clear, or loading a data transfer
command with GO set.

NED causes TRE.

NEM
Non-existent
memory
Read only

Set when the controller is performing
a data transfer and the memory address specified in MTBA and MTBAE
is non-existent (does not respond to
MSYN within 10 p,s). Cleared by
Unibus INIT, controller clear, RH70
error clear, or loading a data transfer
command with GO set.

NEM causes TRE to set.

3-15

Table 3-9 (Cont)
Control and Status Register 2 Bit Assignments
Bit

Set By /Oeared By

Remarks

PGE
Program error
Read only

Set when the program attempts to
initiate a data transfer operation while
the RH70 is currently performing one.
Cleared by Unibus INIT, controller
clear, RH70 error clear, or loading a
data transfer command with GO set.

PGE causes TRE to set. The data
transfer command code is inhibited
from being written into the drive.

MXF
Missed transfer
Read/write

Set if the drive does not respond to a
data transfer command within 650 MS.
Cleared by Unibus INIT, controller
clear, RH70 error clear, or loading a
data transfer command with GO set.

MXF causes TRE to set. This bit can
be set or cleared by the program for
diagnostic purposes. This error oceurs
if a data transfer command is loaded
in to a drive which has ERR set, or if
the drive fails to initiate the command
for any reason (such as a parity error).

MDPE
Massbus data bus
parity error
Read only

Set when a parity error occurs on the
Massbus data bus while doing a read or
write-check operation. During maintenance operation, MDPE may occur
when writing or reading the MTDB
register if bad parity is detected as the
word is propagated through the data
buffer. Cleared by Unibus INIT, controller clear, RH70 error clear, or
loading a data transfer command with
GO set.

MDPE causes TRE to set. Parity errors
on the Massbus data bus during write
operations are detected by the d.rive
and cause the PAR error (MTER register, bit 03).

OR
Output ready
Read only

Set when a word is present in the
MTDB register and can be read by the
program. Cleared by Unibus INIT,
controller clear, or by reading DB
(Paragraph 3.6.10).

Serves as a status indicator for diagnostic check of the data buffer.

IR
Input ready
Read only

Set when a word is written in the
MTDB register by the program.
Cleared when the data buffer (MTDB)
is full (contains eight words).

Serves as a status indicator for diagnostic check of the data buffer.

CLR
Controller clear
Write only

When a 1 is written into this bit, the
RH70 and all drives are initialized
(Paragraph 3.2).

Unibus INIT also causes controller
clear to occur.

3-16

Table 3-9 (Cont)
Control and Status Register 2 Bit Assignments
Bit

Set By/Cleared By

Remarks

PAT
Parity test
Read/write

While PAT is set, the RH70 generates
even parity on both the control bus
and data bus of the Massbus. When
clear, odd parity is generated. Cleared
by Unibus INIT or controller clear.

While PAT is set, the RH70 checks for
even parity received on the data bus
but not on the control bus. If PAT bit
is set (IPCK bits are all Os) during
maintenance operations of the data
buffer, the data word loaded in the
data buffer will sequence through the
buffer with parity being calculated by
the hardware (controlled by IPCK
bits). When the data word reaches the
OBUF register, the parity checker
(controlled by PAT) will detect inverse
parity as an MDPE error.

BAI
Unibus address
increment inhibit
Read/write

When BAI is set, the RH70 will not
increment the BA register during a
data transfer. This bit cannot be
modified while the RH70 is doing a
data transfer (RDY negated). Cleared
by Unibus INIT or controller clear.

When set during a data transfer, all
data words are read from or written
into the same memory location.

These bits are written by the program
to select a drive. Cleared by Unibus
INIT or controller clear.

The unit select bits can be changed by
the program during data transfer
operations without interfering with
the transfer. The CSl, DS, ER, MR,
FC, DT, CK, TC, and SN registers
contain bits that come from the
selected drive.

02- U 02-00
00 Unit select
Read/write

3.6.6 Drive Status (MTDS) Register (772452)
This register contains the various status indicators for the
selected drive. The status indicators displayed are those of
the tape drive which is specified by the unit select bits
(02:00) of the MTCS2 register. The register is a read-only

register. Figure 3-8 shows the MTDS bit usage, and Table
3-10 provides a description of each bit. Writing into this
register will not cause an error and will not modify any of
the status bits.

CP-1330

Figure 3-8 Drive Status Register Bit Usage

3-17

Table 3-10
Drive Status Register Bit Assignments
Bit

ATA
Attention active
Read only

Set By/Cleared By

Remarks

Set by the drive when there is an
attention condition in that drive.
Cleared by Unibus INIT, controller
clear, drive clear, loading a command
with the GO bit set, or loading a 1 in
the MTAS register in the bit position
corresponding to the drive's unit
number. (The last two methods of
clearing the AT A bit will not clear the
error indicators in the drive.)

An attention condition indicates one
of the following:

The TM02 and the selected!
transport require servicing due
to SSC (see bit 6 in this Table) .

The TM02 and the selected!
transport have become ready
after a non-data transfer opera..
tion.

At the completion of any opera..
tion with EOT asserted.

This bit is the logical OR of all the bits
in the MTER register. This bit is not
cleared by loading a command other
than drive clear. While ERR i~:
asserted, commands other than drive:
clear are not accepted by the drive.

ERR
Error summary
Read only

Set when one or more of the error bits
is set in the MTER register of the
selected drive. Cleared by Unibus
INIT, controller clear, or by drive
clear.

PIP
Positioning in
progress
Read only

Set by the drive while the space or
rewind command is under way.
Cleared at the completion of the
operation.

MOL
Medium on-line
Read only

Set when the selected slave is loaded
and the on-line switch activated. This
condition is necessary for response to
any commands - if GO=I and
MOL=O, the command is aborted and
UNS and AT A are asserted. This bit is
not affected by drive clear or INIT.

Indicates selected slave is ready for
immediate use. Any change in status
of MOL will set ATA.

WRL
Write locked
Read only

Set whenever a reel of tape without a
write enable ring is loaded on the
selected slave. This bit is not affected
by drive clear or INIT.

Indicates that the selected slave trans·
port is write protected.

EOT
End of tape
Read only

Set when the EOT marker is recognized during forward tape motion.
Cleared when the EOT marker is
passed over during reverse tape
motion. This bit is not affected by
drive clear or INIT, however, execution of a rewind command causes EOT
to be cleared.

3-18

Table 3·10 (Cont)
Drive Status Register Bit Assignments

Bit

Set By/Cleared By

Remarks

Not used

DPR
Drive present
Read only

Always set in the TU16/TM02 system.

This bit is a hardwired 1.

DRY
Drive ready
Read only

Set by IN IT or at the completion of a
command. Cleared whenever a valid
command (with the GO bit asserted) is
loaded into MTCS 1.

Indicates that the drive is on-line and
prepared to accept a command. It does
not necessarily indicate that the slave
is ready to accept a command (see
SPR, MOL, PIP).

SSC
Slave status change
Read only

Set when any slave transport requires
attention due to one of the following
conditions:

Setting SSC causes ATA to be asserted
as soon as DRY becomes asserted.
ATA is asserted immediately if DRY is
asserted. More than one slave can be
asserting SSC simultaneously. Each
drive must be polled (for changes in
SPR, MOL, PIP), in turn, and after
servicing, a drive clear should be used
to clear the SSC on that slave. All
drives must be polled when SSC is
serviced since an interrupt will only
occur on SSC transitioning to a 1.

a)
b)
c)
d)

Completion of a rewind
Power failure
Coming on-line
Going off-line

Cleared by INIT. Drive clear will clear
this bit if the sse condition was raised
by the selected slave and no other
slaves are posting SSC.
05

PES
Phase encoded
status
Read only

Set when the selected slave is in PE
mode. Cleared when the selected slave
is in NRZI mode. This bit is not
affected by drive clear or INIT.

Reflects the format mode in which the
formatter is operating.

SDWN
Slowing down
Read only

Set during the period when tape
motion is stopping. This bit is not
affected by drive clear or INIT.

DRY is asserted on the leading edge of
SDWN.

IDB
Identification burst
Read only

Set in PE mode on recognition of the
PE identification burst. Cleared when
another command is issued, or cleared
by drive clear or INIT.

In the forward direction, the bit
remains set through the reading,
writing, or spacing operation. On a PE
tape, IDB should be asserted after any
tape motion operation which began
from BOT.

3-19

Table 3·10 (Cont)
Drive Status Register Bit Assignments
Bit

Set By!Cleared By

Remarks
Indicates detection of tape mark. The
phase encoded tape mark writte:n by
the TUl6 consists of 40 characters
with zeros in physical tracks I, 2, 4,5,
and 8 with tracks 3, 6, 7, 9 dc erased.
The NRZI fIlemark written by the
TUI6 consists of a single character
record followed by the LRCC fOJr that
record. CRCC is held 0 for 9·track
recording of tape mark. The single
character contains octal 023. TM
should be asserted after the completion of a write tape mark command.

TM
Tape mark
Read only

Set when a tape mark is detected and
remains set until the next tape motion
operation is initiated. Cleared by INIT
or drive clear.

BOT
Beginning of tape
Read only

Set when the selected slave detects the
BOT marker. This bit is not affected
by drive clear or INIT. Cleared by
passing BOT (Ber)nning of Tape) in
the forward direction.

SLA
Slave attention
Read only

Set by a selected slave which requires
attention due to coming on-line.
Cleared by drive clear or INIT.

forming a rewind (i.e., the GO bit is clear), the controlll~r i:
immediately notified of an error condition by the assertior
of ATTN H on the Massbus.

3.6.7 Error (MTER) Register (772454)
There are 16 different error conditions that can be detected
in the TM02!TU16 tape drive system. The error register is a
16-bit, read-only register which stores all of the tape system
error indications.

Figure 3-9 illustrates the error register bit usage and Table
3-11 provides a description of each bit. Table 3-12 lists the
various operations and the associated error condition
which can occur during normal operation of the system
Mter performing one of the operations listed at the left 0
the table, only errors indicated by an X may be present it
the MTER register. Presence of any other errors indicate :
hardware malfunction.

TM02!TUI6 errors are categorized as class A and class B.
Class B errors will terminate an in-progress data transfer; a
class A error will not. However, the Massbus controller is
notified of any error during a data transfer by the
immediate assertion of EXC H on the Massbus. If the
TM02!TU16 is not performing any operation, or is per-

CP-1331

Figure 3-9 Error Register Bit Usage

3-20

Table 3-11
Error Register Bit Assignments
Bit

Set By/Cleared By

Remarks

COR/CRC
Correctable data
error /CRC error
Read only

PE mode - set on a tape character.
Therefore, PE error correction logic
was able to correct the data on-the~fly
and good data was transferred to
memory.
NRZ mode - set when the CRC
character generated from read back
data does not agree with the CRC read
from tape. Cleared by drive clear or
INIT.

In the PE case, when the single dead
track is accompanied by a parity error,
the data bit in the dead track is
inverted. COR/CRC is a class A error.

UNS
Unsafe
Read only

Set if the GO bit in the MTCSI
register is set, the MOL bit in the
MTDS register is reset, and a command
code other than drive clear is issued.
Also set if the TM02 detects an imminent power fail condition (AC LO
asserted, DC LO not asserted).

UNS is a class B error.

If UNS is caused by GO= 1 while
MOL=O, it is cleared by RH70 CLR or
DRIVE CLEAR. If UNS is caused by a
transient voltage-low condition, it can
be cleared by INIT or drive clear when
voltage returns to an acceptable level.
If UNS is caused by a permanent
voltage - low condition, it cannot be
cleared.
13

OPI
Operation
incomplete
Read only

A read or space operation indicates
that a tape record has not been
detected within 7 sec from command
initiation. A write operation indicates
that a read-after~write tape record has
not been detected within 0.7 sec from
command initiation. Can also indicate
that NSG > 0.08 inches. Cleared by
INIT or drive clear.

3-21

OPI is a class B error. Also, OPI can be
set when a rewind command is issued
at BOT.

Table 3-11 (Cont)
Error Register Bit Assignments
Bit

Set By/Cleared By

Remarks

DTE
Drive timing error
Read only

Set (1) during a write operation if
WCLK was not received from the
RH70 in time to provide a valid tape
character, or (2) when a data transfer
is attempted when the bus of the
Massbus is already occupied (OCC= 1).
Cleared by INIT or drive clear.

When DTE is asserted, the drive also
asserts EBL and EXC and aborts the
command.
Case 1 can be distinguished from case
2 by monitoring the MTFC frame
count register. In case 1, this register is
incremented at least once since it was
loaded. In case 2, this register will
contain the same number with which
it was loaded prior to the issuance of
the data transfer command. During a
read operation, DTE can occur only
due to case 2. DTE is a class B error.

III

NEF
Non-executable
function
Read only

Set when:

NEF is a class B error.

A write operation is attempted
on a write-protect transport.

A space reverse, read reverse, or
write check reverse is attempted
when the tape is at BOT.

The DEN 2 bit in the tape
control register does not agree
with the PES status bit (Le.,
selected drive not capable of
selected density).

A space or write operation is
attempted when FCS=O in the
tape control register.

A read or write operation is
attempted with DEN2=O in the
tape control register and the 2's
complement of a number less
than 13 is in the frame count
register.

Cleared by drive clear or INIT.

3-22

Table 3-11 (Cont)
Error Register Bit Assignments
Bit
10

CS/ITM
Correctable skew/
illegal tape mark
Read only

Set By/Cleared By
In PE mode, this bit is set when
excessive but correctable skew is
detected in data read back from tape.
It is a warning only, and does not
indicate that bad data was read from
tape.
In NRZ mode, this bit is set when a bit
pattern is detected on tape which has
the general characteristics of an NRZ
fllemark (specifically, two single
characters separated by seven blank
character spaces) but which does not
contain the exact data expected in an
NRZ fllemark. Cleared by drive clear
or INIT.

Remarks

When such a bit pattern is detected in
NRZ mode, both tape marks in the DS
register and CS/IFM in the ER register
will become asserted.

FCE
Frame count error
Read only

Set when a space operation has terminated and the frame counter is not
cleared. Also set when the RH70 fails
to negate RUN when the TM02 asserts
EBL. Cleared by drive clear or INIT.

FCE is a class A error.

NSG
Non standard gap
Read only

Set after a data transfer operation
whenever any tape characters are read
while the read head is scanning the
first half of the interrecord gap.
Cleared by drive clear or INIT.

NSG is a class A error.

PEF/LRC
PE format
error/LRC
Read only

Set in PE mode when an invalid
preamble or postamble is detected. Set
in NRZ mode when the LRC character
generated from readback data does not
match the LRC character read from
tape. Cleared by drive clear or INIT.

PEF /LRC is a class A error.

INC/vpE
Incorrectable datal
vertical parity error
Read only

A PE read operation indicates that one
of the following has occurred:

INC /VPE is a class A error.

1.
2.
3.

Multiple dead tracks
Parity errors without dead tracks
Skew overflow

During an NRZ read operation,
indicates that a vertical parity error
has occurred or that data has occurred
after the skew delay is over. Cleared
by drive clear or INIT.

3-23

Table 3-11 (Cont)
Error Register Bit Assignments
Bit

Set By/Cleared By

Remarks

DPAR
Data bus parity
error
Read only

Set when a parity error is detected on
the Massbus data lines during a write
operation. Cleared by drive clear or
INIT.

DP AR is a class A error. Can be forced
set by the PAT bit (bit 04 of MTCS2).

FMT
Format error
Read only

Set when a data transfer is attempted
with an incorrect format code (Le., the
tape format code loaded in the MTTC
register is not implemented on that
TM(2). Cleared by drive clear or INIT.

Tape motion is inhibited; EXC and
EBL are asserted. DRY and ATA are
asserted on the negation of EBL. FMT
is a class B error.

CPAR
Control bus parity
error
Read only

Set when a parity error is detected on
the Massbus control lines during a
control bus write operation. Cleared
by drive clear or INIT.

Detection of CP AR does not interfere'
with the register write sequence except:
during a write to the MTCS 1 rl~gistel'
which suppresses setting of the GO bit..
CPAR is a class A error. Can be forced.
set by the PAT bit (bit 04 of MTCS2)"

RMR
Register modification
refused
Read only

Set when the controller attempts to
write into any implemented TU16
register except the maintenance
register or the attention summary
register while the GO bit is asserted. If
RMR occurs, the addressed register is
not modified. Cleared by drive clear or
INIT.

RMR is a class A error.

ILR
Illegal register
Read only

Set when a read or write from a
non-existent register is attempted.
Cleared by drive clear or INIT.

No register modification should occur,
On a control bus read, all zeros are
gated onto the control lines. ILR is a
class A error.

ILF
Dlegal function
Read only

Set when the GO bit is asserted and a
function code not implemented by the
TM02/TUI6 is attempted. Cleared by
drive clear or IN IT .

ILF is a class B error.

3-24

Table 3-12
Error Conditions
OPERATIONS

ERRORS

- -r:x: -r:x: -E-<

- r:x:
tJ...

r:x:

WRITE TO ANY REGISTER*

READ FROM ANY REGISTER

~
tJ...

-r:x: ~w r:x:

il;
w
.....:I

u
~

ii:

E-<

Q:I

W
U
tJ...

==
til
U

....

tJ...

E-<

r:x:

r:x:
0

LOAD NO-OPWITH GO=}

LOAD REWIND OFF LINE WITH GO= }

LOAD REWIND ON LINE WITH GO=}

LOAD DRIVE CLEAR WITH GO=}

LOAD WRITE FMK WITH GO=}

LOAD ERASE WITH GO=}

LOAD SPACE FWD WITH GO= 1

LOAD SPACE REV WITH GO=}

LOAD WRITE CHECK FWD WITH GO= 1

LOAD WRITE CHECK REV WITH GO= 1

LOAD WRITE FWD WITH GO=}

X
X

LOAD READ FWD WITH GO= 1

LOAD READ REV WITH GO = }

X
X

MASS BUS INIT
WRITE TO AS OR MT REG

"'Except MTAS or MTMR registers
TM02 operations with errors that could be detected during those operations and remain asserted after the operation is complete:
1
2

Most likely a programmer-caused error.
Possible operator errors (WRL, off-line).

3.6.8 Attention Summary (MTAS) Register (772456)
The attention summary register is a read/write "pseudoregister," which consists of from one to eight bits depending on the number of TM02s in the system. The term
"pseudo-register" refers to the fac~ that only one register
bit position is physically contained in each TM02. This bit

position reflects the state of the AT A status bit for tha
TM02. Hence, bit position 0 of the attention summar:
register is generated by the AT A bit of TM02 0, bit positiol
1 is generated by the AT A bit of TM02 1, and so on to bi
7. Bits 8 through 15 are not used.

3-25

Unlike the other drive registers, the attention summary
register is directly selected by the RH70 controller without
first addressing a particular TM02. Thus, for a single
attention summary register read operation, every TM02 in
the system responds by placing the state of its ATA bit in
the appropriate bit position on the control bus and
disabling its remaining 15 control bus transmitters. This
control bus configuration appears as a single register output
which collectively informs the controller of all TM02s that
require attention (Le., ATA=l). The programmer can then
selectively examine the error or status registers of each of
the affected TM02s to determine the cause of the individual
attention conditions.

3.6.8.1 Setting the Attention Active (ATA) Bit - The
AT A bit is displayed in bit 15 of the MTDS register, and
indicates that the TM02/TU16 requires servic:ing (I)
because it has become ready after completion of a non-data
transfer operation (2) because of an error condition, or (3)
because of an important internal status change. AT A is
asserted only if the DRY (drive ready) bit is asserted. The
setting of the AT A bit does not in itself prevent execution
of commands. If the ERR (bit 14-MTDS) or the SSC (bit
06-MTDS) transitions from the negated to asserted state
while the DRY bit is set, the AT A bit will become a.sserted.
The ATA bit will also be asserted if the DRY bit transitions
from the negated to the asserted state at the time one of
the following conditions is met:

The programmer can also write into the attention summary
register; however, the significance of the bits being written
is unusual. Writing a 1 into a bit position resets the AT A bit
in the TM02 assigned to that bit position; however, writing
a 0 has no effect. This unique writing scheme allows the
controller to reset, after inspection, all summary bits that
were set, without accidentally resetting those bits that may
have become set in the meantime. The following table
illustrates the effects of writing into an attention summary
bit position.
ATA Bit
Before

Summary Bit
Written

ATA Bit
After

0
0

0
0
0

Figure 3-10 shows the bit usage of the attention summary
register and Table 3-13 provides a description of each bit.

ERR is asserted

SSC is asserted

The function code in the MTCS 1 register
denotes a space, erase, write tape mark, rewind
or read-in preset command.

EOT is asserted.

3.6.8.2 Clearing the Attention Active (ATA) Bit - The
ATA bit may be cleared by writing a 1 into its po:;ition in
the attention summary register. Parity is checked during the
control bus transfer which controls the writing of the AT A
bits, and if a parity error is detected, the AT A bit will be
set at the completion of this transfer. The AT A bit will a1:so
be cleared by issuing a valid drive clear command, by
asserting the INIT line, or by loading a GO bit into the
MTCS 1 register while the ERR bit is negated.

~~----------------~yr------------~
NOT USED
CP-1332

Figure 3-10 Attention Summary Register Bit Usage

3-26

Table 3-13
Attention Summary Register Bit Assignments
Bit

Remarks

Set By/Cleared By

15-08

Not used.

07-00
ATA 07-00
Read/write

Each bit sets when the corresponding
drive asserts its ATA bit. All bits are
cleared by Unibus INIT, drive clear,
or controller clear. Individual bits are
cleared by loading a function code
with the GO bit in the corresponding
drive or by writing a 1 in the ATA bit
positions of this register. Writing a 0
has no effect.

The description below applies only to clearing the AT A bit
by writing a 1 into it.
•

Clearing the AT A bit while ERR is asserted will
result in negation of ATA but will not affect
the status of the error register. No commands
except drive clear can be executed until the
error register is cleared.

•

Clearing the AT A bit when the attention
condition is caused by normal completion of a
space, rewind, read-in preset or write tape mark
operation will result in negation of ATA and
will result in no other drive status changes.

•

Clearing the AT A bit when the attention
condition is caused by assertion of SSC will
result in negation of ATA. SSC will remain set,
and unless it is cleared by drive clear or INIT,
completion of the next command will cause
AT A to become set.
Note that SSC can be generated by up to eight
slaves in the TM02/TU 16 tape system and that
its assertion may indicate status changes in
several slaves including the selected slave. Thus,
while a drive clear command will clear SSC and
SLA in a selected slave, unselected slaves could
continue to assert SSC. Moreover, if an unselected slave caused SSC to be asserted because

of a power failure, issuance of drive clear may
(and INIT will) succeed in clearing SSC while
leaving a broken slave on the master-slave bus
waiting to abort the next command issued it.
BECAUSE OF THIS, SSC SHOULD NEVER
BE CLEARED BEFORE A DECISION IS
MADE TO POLL ALL AVAILABLE SLA VES
TO DETERMINE THEIR STA TUS.
•

Clearing the ATA bit when the attention
condition is caused by assertion of DRY while
EaT is asserted will result in negation of AT A
and will leave the drive ready to accept another
command. Note that detection of EaT during
tape motion will not generate an AT A and will
not cause an abort. The EaT flag is a warning
only, and it is the programmer's responsibility
to go no more than 10 feet beyond the EaT
marker.

3.6.9 Character Check (MTCC) Register (772460)
The check character register is a nine-bit, read-only register
that permits the programmer to check the validity of a data
transfer. At the end of an NRZ read operation, this register
contains the CRC character for that operation. Hence, the
programmer can determine if the CRCC generator logic is
functioning properly. At the end of a PE read operation,
however, this register contains a dead track indication
(DT= 1) of any track which may have dropped one or more
bits during the operation.

3-27

Figure 3-11 illustrates the check character register bit usage
for both NRZ and PE modes :and Table 3-14 provide!s a
description of each bit.

3.6.9.1 CRC Character Storage - At the end of an NRZ
Read or Write operation, the CRC character read from tape
will be stored in bits 0 through 8 of the MTCC register. The
least significant bit will be stored in bit 0, and the most
significant bit in bit 7 of this register.

3.6.1 0 Data Buffer (MTDB) Register (772462)
This register provides a maintenance tool to check the dlata
buffer in the RH70. A total of eight words is accepted
before the data buffer becomes full. Successive reads from
data buffer will read out words in the same order in which
they were entered into the data buffer.

NOTE
The check character register will contain the
(~heck character described above at the end of n
read or write operation when DRY transitions
from a 0 to a I. Bits 00 through 08 are
i~aranteed true only as long as DRY is equal to
l.

The IR (input ready) and OR (output ready) status
indicators in the MTCS2 register are provided so that the
programmer can determine when words can be read from OJ
written into the MTDB. IR should be asserted before
attempting a write into DB; OR should be asserted before
attempting a read from DB.

3.6.9.2 Dead Track - The dead track register is normally
used for maintenance to determine which tracks are
dropping data bits. The dropped data bits (read data) are
orienh;:d with the following binary weights.
Dead Track

Binary Weight

DTO
DT1
DT2
DT3
DT4
DT5
DT6
DT7
DTP

2°
21

22
23
24
25
26
27
P

15
r-.1RZ
FORMAT

The MTDB register can be read and written only as an
entire word. Any attempt to write a byte will cause an
entire word to be written. Reading the DB register is a
"destructive read-out" operation: the top data word in the
data buffer is removed by the action of reading DB, and a
new data word (if present) replaces it a short time later.
Conversely, the action of writing the DB register does not
destroy the "contents" of DB; it merely causes one more
data word to be inserted into the data buffer (if it was not
full). Figure 3-12 shows the MTDB bit usage, and Table
3-15 provides a description of each bit.

ICRCP I c~C I C:C I C:C

CRC
4

CRe
3

---.J

PE
FORMAT

I
\.

I C:C I C~C I

c;:]
--.-J

CRC
CHARACTER

IOTP

DT7

IOTa IOT5

DT4

---.J

NOT USED

Ion IOT2

DT1

NOT USED

lo:J
..---J

DEAD TRACK
Cp·-1333

Figure 3-11 Check Character Register Format

3-28

Table 3-14
Check Character Register Bit Assignments
Bit

Remarks

Set By/Cleared By

15-09

Not used.

08-00
CCD
Check character /
dead track
Read only

Contains the CRC character and parity
bit in NRZ mode or the dead track
register in PE mode.

CP-1334

Figure 3·12 Data Buffer Bit Usage

Table 3-15
Data Buffer Bit Assignments
Bit

Set By/Cleared By

Remarks

15-00
DB 15-00
Data buffer
Read/write

When read, the contents of OBUF
(internal RH70 register) are delivered.
Upon completion of the read, the next
sequential word in the data buffer will
be clocked into OBUF. When written,
data is loaded into IBUF (internal
RH70 register) and allowed to
sequence into the data buffer if space
is available.

Used by the program for diagnostic
purposes. When the register is written
into, IR is cleared until the DB is
ready to accept a new word. When the
register is read, it will cause OR to be
cleared until a new word is ready.
During a write-check error condition,
the data word read from tape which
did not compare with the corresponding word in memory is frozen in
MTDB for examination by the
program.

3.6.11 Maintenance (MTMR) Register (772464)
The maintenance register is a 16-bit read/write register
which performs the following functions:
1.

Provides data wraparound paths for checking
the data formatting logic in the TM02.

Provides a means for testing error detection
circuitry within the TM02.

Acts as a storage buffer for the longitudinal
parity check (LRC) character when operating in
NRZ mode and performing a forward read or
forward write operation.

Figure 3-13 shows the maintenance register bit format and
Table 3·16 provides a description of each bit.

3-29

'~------------------~y~-------

~--------~y~----------

MAINTENANCE
OPCODE

MAINTENANCE
DATA FIELD

CP-133~

Figure 3-13 Maintenance Register Bit Usage
Table 3-16
Maintenance Register Bit Assignments
Bit

Set By/Cleared By

These bits buffer the data gem~rated
during wraparound operations. At the
end of normal NRZ transfers (except
read reverse), these bits contain the
LRC of the last record. MDF 0 contains the parity bit for the maintenance data character. MDF 1 contains
the LSB of the maintenance data
character and the remain bits are
contained in order in MDF 2 th rough
MDF8.

15-7
MDF 8-0
Maintenance
data field
Read/write

Remarks

BPICLK
Two-hundred
BPI clock
Read only

Displays a clock signal derived from
the crystal oscillator in the selected
slave. The clock frequency is dependent on the read/write speed of the
selected slave and is equal to the
frequency at which a contill1uous
succession of characters is written on
tape when operating at 200 characters
per inch density.
BPICLK is displayed to aid in monitoring of drive functions during maintenance mode operations.

MC
Maintenance clock
Read/write

Cleared by drive clear or INIT.

3-30

This bit controls the sequencing of
data through the TM02 data paths
when operating in maintenance mode.
If the GO bit is asserted and a maintenance op code of 4 8 , 58, or 6 8 is
contained in MOP bits 0 through 3,
the MC bit changes state each time a
control bus write to the maintenance
register is executed. If the GO bit is
asserted and an op code of 3 8 is
contained in MOP bits 0 through 3,
the MC bit changes state after each
read strobe occurs. The maintenance
op code is described under bits 4
through 1 in this table.

Table 3-16 (Cont)
Maintenance Register Bit Assignments
Bit

Remarks

Set By/Cleared By

4-1

These bits control the maintenance
function which will occur when the
MM bit is set to 1 and the TM02 is
loaded with the appropriate command.
The following op codes will be implemented:

MOP3-MOPO
Maintenance
op code 03 -00
Read/write

a.
b.

3-31

0000 - Null code
0001 - Interchange read
In NRZ mode, this op code
causes a more stringent skew
check to be made on data during
read or write-check operations.
In PE mode, this op code suppresses on-the-fly correction of
data errors resulting from a
single dead track.
0010 - Even parity
Causes an even parity bit to be
associated with data sent from
the TM02 to the controller on
either the data or control bus
lines, thereby causing the controller to detect parity errors.
0011 - Data Wraparound,
Global
Causes execution of a write forward command to be executed
as follows:
Data is brought in on the data
lines, divided into bytes using
the algorithm defined by the
format code in the tape control register, formatter as
either NRZ or PE write data,
multiplexed into the read circuitry and deposited in the
maintenance register data
field.
In PE mode, every other character generates a read strobe
to allow the programmer sufficient time to write and
monitor a loop.

Table 3-1() (Cont)
Maintenance Register Bit Assignments
Bit

Remarks

Set By /<:leared By

4--1 (Cont)

3-32

0100 - Data Wraparound,
Partial
Causes execution of a wrih~ forward command to be exel:uted
as follows:
Data is brought in on th{~ data
lines, divided into bytes using
the algorithm defined by the
format code in the tape: control register, formatted as
either NRZ or PE write data,
and deposited in the main tenance register data field.
0101 - Data Wraparound,
Formatter Write
Causes execution of a write forward command to be executed
as follows:
Data is brought in on the data
lines, divided into bytes. using
the format code in the tape
control register, and de·
posited in the mainte:nance
register data field.
0110 - Data Wraparound"
Formatter Read
Causes execution of a read com ..
mand to be executed as follows::
Data is taken from the main·
tenance register data field,
multiplexed into the fmmat·
ting logic byte-by-byte,
formed into data bus word::;
using the algorithm defined
by the format code in the
tape control register, and
transmitted to the RH70 controller.
In addition, this op cod.e suppresses reception of the Massbus
WCLK signal. Thus, an attempt
to perform a write op1eratiolll
with this op code in the maintf:nance register will result in df:tection of a drive timing error
(DTE).

Table 3-16 (Cont)
Maintenance Register Bit Assignments
Bit

Set By /Oeared By

4-1 (Cont)

Remarks
h.

MM
Maintenance mode
Read/write

Must be set to a 1 when any maintenance mode function is desired.
Setting the MM bit to 1 does not
initiate any action on the part of the
drive but alters the manner in which
the drive executes various commands.
The manner in which the command
execution is altered depends on the
maintenance op code in bits 4 through
1 of this register.

3-33

0111 - Cripple Reception of
OCC
An attempt to perform any data
transfer operation with this op
code in the maintenance register
will result in detection of DTE.
1000 - In NRZ mode, this op
code suppresses initialization of
the CRC checking logiC, resulting in CRC errors.
In PE mode, this op code suppresses detection of data in
logical track 1.
1001 - This op code causes bit
5 of tape data bytes to remain in
the asserted state.
In PE mode, this op code suppresses detection of data in
logical tracks 1 and 2.
1010 - Maintenance Mode End
of Record
This op code is used to signal the
end of a maintenance mode
operation causing the GO bit to
become negated.
1011 - Causes logical bit 1 of a
PE preamble and postamble to
be inverted during a write forward command, resulting in
generation of invalid preambles
and postambles.

with the MTBA register to specify the starting mem
address of a data transfer operation. The six bit riel<
incremented (decremented for specific function code~;) e;
time a carry (borrow) occurs from the MTBA regi~
during memory transfers.

3.6..12 Drive Type (MTDT) Register (772466)
The drive type register is a 16-bit read-only register, the
content of which identifies the particular type of storage
device (transport) being used. Bits 0 through 8 (DT 0-8) of
the drive type register identify the type and status of the
selected transport. If a nonexistent transport is selected or
if the selected transport is not powered up, DT 0-8 will
contain 01 Os. If the selected transport is powered up, but is
not a TV16, DT 0-8 will contain 012s to 017 s , depending
on the type of transport. If the selected transport is a TV 16
and is powered up, these bit positions will contain OIls.

Address bits A16 and A17 can also be set or clea
through the MTCS 1 register. If an address extension fiel~
written into MTBAE, the program should ensure that A
and Al 7 are not altered when a command is loaded il
MTCSI. This can be accomplished by either loading
command with a write low byte instruction to MTCSI
by ensuring the proper value appears in the A16 and A
bit positions of MTCSI.

Figure 3-14 shows the drive type register bit usage and
Table 3-17 provides a description of each bit.

Figure 3-17 shows the MTBAE register bit usage and Ta
3-20 provides a description of each bit.

3.6.13 Serial Number (MTSN) Register (772470)
The serial number register is a 16-bit, read-only register
which contains a BCD representation of the four least
Significant digits of the transport serial number.

3.6.16 Control and Status 3 (MTCS3) Register (7724~
The MTCS3 register contains parity error in for mati
associated with the memory bus. Bit position 13 of 1
MTCS2, (PE) indicates that a parity error occurred duri
the memory transfer. Bits 15 through 13 of MTCS3 fmtl
localize the error for diagnostic maintenance. [n additi<
bits 3 through 0 provide the diagnostic program the abil
to invert the sense of parity check and thereby ver:
correct operation of the parity circuits.

Figure 3-15 shows the serial number register bit usage and
Table 3-18 provides a deSCription of each bit.
3.6.14 Tape Control (MTTC) Register (772472)
The tape control register is a 16-bit read/write register
which selects an existing transport, the data fonnat, and the
density.

An Interrupt Enable bit in the MTCS3 register allows t
program to enable interrupts without writing into a dri
register as previously described. This bit also appears in t
MTCS1 register for program compatibility and can be set
cleared by writing into either register.

Figure 3-16 shows the tape control register bit usage and
Table 3-19 provides a description of each bit.
3.6.15 Bus Address External (MTBAE) Register (772474)
The MTBAE register contains the upper 6 bits of the
memory address and combine with the lower 16 bits
located in MTBA to form the complete 22 bit address. This
register should be loaded by the program in conjunction

Figure 3-18 shows the MTCS3 register bit usage:, and Tal
3-21 proVides a description of each bit.

[ NSA I TAP I MOH 1 7CH IORQ I SPR~OT
USED

DT]

00
y
DRIVE TYPE (08-00)

Figure 3-14 Drive Type Register Format

3-34

...J
CP-13~,6

Table 3-17
Drive Type Register Bit Assignments
Bit

Set By /Oeared By

Remarks
Neither drive clear or INIT affect this bit.

NSA
Not sector
addressed
Read only

Always set to indicate that the device
is not sector addressable.

TAP
Tape
Read only

Always set to indicate that the device
is a tape transport.

MOH
Moving head
Read only

Always negated to indicate that the
device is not a moving head unit.

7CH
7 Channel
Read only

Asserted if the selected transport is a
7-channel unit. Always negated if the
selected transport is a TUI6.

DRQ
Drive request
required
Read only

Always negated to indicate that the
device is a single-port device.

SPR
Slave present
Read only

Asserted when a transport is powered
up and has been assigned the selection
code contained in the MTTC tape
control register.

Not used.

08-00
DT 08-00
Drive type
Read only

Contains the drive type number for
the selected slave (lis for the
TM02/TUI6). If no slave is assigned in
bits 0-2 of the MTTC tape control
register, the drive type code readback
is 01 Os. If a slave has been assigned a
select code in bits 0-2 of this register,
the drive type code will be a code
from lIs to 17 s. Drive clear or INIT
do not affect these bits.

3·35

SN
00
' - - - - - - . . v , - - - - - - - - ) \ . - - - - - - y - - - - - - " ) "--------..v..--------) ''-------v.------10

digit

0
10 digit

digit

CP-1331'

Figure 3-15 Serial Number Register Bit Usage

Table 3-18
Serial Number Register Bit Assignments
Bit

Set By/Cleared By

Remarks

15-12
SNI5-SN12
Read only

Most significant BCD digit (10 3 ) of
slave serial number.

11-08
SNll-SN08
Read only

102 digit of slave serial number.

07-04
SN07-SN04
Read only

10 1 digit of slave serial number.

03-00
SN03-SNOO
Read only

Least significant BCD digit of slave
serial number.

' - - _ - - - - 1 \_ _ _ _---.. .--_ _ _
--y--y

DENSITY
SELECT

FORMAT
SELECT

\.'---~v-----)

SLAVE
SELECT
CP-133fl

Figure 3-16 Tape Control Register Bit Usage

3-36

Table 3-19
Tape Control Register Bit Assignments
Bit

Remarks

Set By/Cleared By

ACCL
Acceleration
Read only

Set when the transport is not actively
reading or writing data.

ACCL is not affected by drive clear or
INIT.

FCS
Frame count status
Read only

Normally set at the end of a write into
the frame count register. Cleared when
frame count register overflows.
Cleared by drive clear or IN IT .

Loading a space or write command
with the GO bit asserted and FCS
equal to 0 will cause a non-executable
function (NEF -bit 11 of drive status
register) to be asserted and will cause
the command to be aborted. No tape
motion will occur.

TCW
Tape control write
Read only

Set when a control bus write operation
to the tape control register is performed. Cleared by the initiation of
any command requiring tape motion.

TCW is used by the TM02 to determine whether or not to wait for the
completion of the settle down process
(SDWN-bit 4 of the drive status
register). If TCW is asserted, SDWN
should be negated before issuing a new
command to the selected slave.

EAODTE
Enable abort on
data transfer errors
Read/write

This bit, when written to aI, will
cause a data transfer operation to be
aborted as soon as one of the following errors is deleted:
a.
b.
c.
d.

DP AR-bit 5 of MTER register
COR/CRC-bit 15 of MTER
register
FMT/LRC-bit 7 of MTER
register
INC/VPE-bit 6 of MTER register

Not useCI.
Specifies the tape character density
during read or write operations as
follows:

10-08
DEN2-DENO
Density select

DEN2

DEN1

DENO

0
0
0
0

0
0

Density
(bpi)

WO}
556
800
800

NRZ

1600

0
1

1
0

} Reserved

Drive clear and INIT do not affect the
density select bits.

3-37

Table 3-19 (Cont)
Tape Control Register Bit Assignments
Bit

Set By/Cleared By

Remarks
Specifies Massbus-to-tape character
formatting during a write operation, or
tape character-to-Massbus formatting
during a read operation.

07-04
FMT SEL3-0
Format select
Read/write

Data format is selected by the PMT
SEL bits as follows:
FMT SEL Bit
3 2 1 0
I 1 0 0
1 1 0 1
1 1
0

Mode
Normal mode
Core dump
15 mode

If the FMT SEL bits specify a format
not implemented on a TM02/TUI6
system and a valid data transfer (~om
mand is loaded in the MTCSI re~~ster
with the GO bit asserted, the format
error bit (FMT -bit 4 of the MTER
register) will be asserted and the operation will abort (Figure 1-10).
03

If this bit is set in NRZ mode, even
parity will be written on tape and even
parity is expected on read-back. If this
bit is reset, odd parity will be written
on tape and will be expected. on
read-back. When the TM02 is operating in NRZ with EV PAR set, it will
not allow an an zeros character to be
written on tape. If an all zeros eharacter is presented to the TM02, the
TM02 will invert binary bit 4 and the
parity bit before writing the character
on tape. This converts 000 8 to 020 8 •

EVPAR
Even parity
Read/write

This bit is ignored in phase encoded
(PE) mode (DEN2=1). In PE mode,
odd parity is always used.
Specifies the unit number of the transport to be used. Drive clear or l[NlT
does not affect SS2-0.

02-00
SS2-0
Slave select
Read/write

3-38

A21

A20

A19

A1e

o
A17

A16
11-2906

Figure 3-17 Bus Address Extension Register Format

Table 3-20
Bus Address Extension Register Bit Assignments
Bit
15:06
05:00

Remarks

Set By/Cleared By

A(21: 16)
Bus Address
Read/Write

Not Used

Always read as a O.

Loaded by the program to specify the
starting memory address of a data
transfer operation. Cleared by Unibus
INIT or controller clear.

The MTBAE register is incremented
(or decremented) each time a carry
out (borrow out) of MTBA occurs.
A16 and Al 7 can also be set or cleared
through the MTCSI register.

11-2907

Figure 3-18 Control and Status 3 Register Format

Device-Interactive with Unmonitored Status - In this
method the programmer assumes the correct status exists
(WRL, MOL, SPR, PIP) and issues a command without first
checking status. If the wrong status exists, the command
will abort and the system must have the facility to cause
error correction through the error handler. This method has
two disadvantages: (1) the error handler must be expanded
to allow the status error recovery, and (2) IE should only
be set when a command is to be executed; consequently,
the system does not become aware of status changes
through the interrupt facility. As a result, dequeuing of
requests to a multi-transport system is not normally
possible without use of a real time clock (RTC) and status
polling.

3.7 PROGRAMMING EXAMPLES
The TJU16 tape system allows the software to monitor the
status of all transports at all times (via SSC) and to monitor
the readiness of all drives to receive new commands (via
ATA bits). This, however, is a programmer's option.
Actually there are four ways to program the TJU16 system.

Dedicated Processor - In this mode the interrupt enable bit
(IE) is never set and the processor must check status on the
RHll controller, TM02 tape controller and the TU16
transport before initiating each command. The program
must loop on RDY and DRY to establish when the job is
done. This method is impractical in a sophisticated programming environment since it requires a dedicated CPU.

3-39

Table 3-21
Control and Status 3 Register Bit Assignments
Bit

Set By/Cleared By

Remarks

APE
Address Parity
Error
Read only

Set if the address parity error line
indicates that the memory detected a
parity error on address and control
information during a memory transfer.
Cleared by Unibus INIT, Controller
Clear, Error Clear, or loading a data
transfer command with GO set.

APE causes PE, bit 13 of MTCS2,.
When an APE error occurs the MTBA
and MTBAE registers contain the ad..
dress +4 of the double word address at
which the error occurred dming a
double word operation or the address
+2 during a single word operation.

14,
13

DPE,OW,EW
Data Parity
Error
Odd Word,
Even Word
Read only

Set if a parity error is detected on data
from memory when the RH70 is performing a Write or Write Check command. Cleared by Unibus INIT, Controller Clear, Error Clear, or loading a
data transfer command with GO set.

DPE causes PE, bit 13 of MTCS2.
When a DPE error occurs, the MTBA
and MTBAE register contain the
address +4 of the double word address
at which the error occurred during :a
double word operation or the address
+2 during a single word operation.

12,

WCEOW,EW
Write Check
Error
Odd Word,
Even Word
Read only

Set when data fails to compare
between memory and the drive.
Cleared by Unibus INIT, Controller
Clear, Error Clear, or loading a data
transfer command with GO set.

Causes WCE, bit 14 of MTCS2. The
word read from the drive which did
not compare is locked in the data
buffer and can be examined by reading
the MTDB register.

DBL
DouBle word
Read only

Set if the last memory transfer was a
double word operation. Cleared by
Unibus INIT, Controller Clear or
loading a data transfer command with
GO set.

9-7 Not Used
6

IE
Interrupt
Enable
Read/write

5-4 Not Used

Always read as a O.
IE is a control bit which can be set
under program con trol. When IE = 1,
an interrupt may occur due to ROY or
SC being asserted. Cleared by Unibus
INIT, Controller Clear, or automatically cleared when an interrupt is
re cognized by the CPU. When a 0 is
written into IE by the program, any
pending interrupts are cancelled.
Always read as a O.

3-40

This bit can be set or clea.red by
writing into MTCSI register. If written
through MTCS3 register, a register
write operation is not performed into
a drive register simultaneously.

Table 3-21 (Cont)
Control and Status 3 Register Bit Assignments
Bit
3-0 IPCK (3:0)
Invert Parity
Check (3:0)
Read/write

Set By/Cleared By

Remarks

These bits are written by the program
to control the data parity detection
logic. When set inverse parity is
checked with data during memory
transfers of Write and Write Check
operations.

Parity control is provided for each
byte in double word addresses, i.e.,
IPCK 0 - Even Word, Even Byte
IPCK 1 - Even Word, Odd Byte
IPCK 2 - Odd Word, Even Byte
IPCK 3 - Odd Word, Odd Byte
During maintenance operation of the
MTDB data buffer, if IPCK 0 or IPCK
1 is set when the first word is written
into the MTDB, that data word (containing bad parity) will sequence
through the data buffer and when it
reaches OBUF, the parity checkers
(controlled by the PAT bit) will detect
the bad parity as an MDPE error. Note
if both IPCK 0 and IPCK 1 are set, no
bad parity will be generated. The same
explanation applies for IPCK 2 and
IPCK 3 which are associated with the
alternate data word (i.e., the second
data word loaded in the data buffer).

NOTE
This method is capable of controlling multidrives and multi-transports simultaneously. In
the other three modes, if dequeuing is to be
done it must be done via the "system clock"
facility, and the RH70, TM02, and TU16 must
all be assigned to the user.

Device-Interactive with Monitored Status - In this method,
the software checks the status previous to issuance of a
command. The disadvantage is that IE should only be set
during command execution and "multi-transport" dequeuing is not possible without use of a real time clock and
polling of slave status.
Monitored Status via Interrupt Facility - In this method,
IE is always set except while actually servicing an interrupt.
Because the system is always monitoring "slave-status
changes" and "attention active" on all TU16s and TM02s,
dequeuing may occur as soon as the device becomes ready.

The following paragraphs show several typical programmil
examples. These are write, read, space, and tape rna
operations.

3-41

J.7.l Write Data Transfer
I'he write data transfer causes data words from memory to
be transferred to the RH70 Massbus controller, then to the
fM02 tape drive where they are converted into tape
~haracters and finally to the slave transport where they are
mitten on tape. A typical sequence of steps necessary to
initiate a write data transfer is enumerated below. It is
Issumed that this is the first record to be written on tape.
!\s a result, additional steps are required that would not be
lecessary when writing subsequent records.
1.

NOTE
If the tape is not at BOT, issue a rewind
command. However, the DRY bit must
be set. To issue the rewind command,
load a function code of 078 (GO bit
asserted) into the MTCSI control register.
The DRY bit will temporarily be negated
and will be reasserted as soon as the
rewind function is transmitted to the
slave. This allows the drive to accept
another command before completion of
the rewind.

Issue an RH70 clear by setting bit 5 in the
MTCS2 register in the RH70. (First time only
error bits should be cleared by the error handler
and ATA bits by the interrupt handler).

Select a TM02 tape drive by writing bits 0
through 2 of the MTCS2 status register in the
RJ-I70.

Read the MTDT drive type register in the TM02
to see what type of drive is specified. In this
case, bit 14 (TAP) should be set indicating a
tape drive.

Read bit 12 (non-existent drive) of the MTCS2
status register to see if the drive that was
addressed is an actual drive.

Read the following bits in the MTDT drive type
register.

Examine the MTER register for errors. If the
error is a TM02/TU16 error, a drive clear
should be issued which clears only the se:lected
drive. The drive clear is issued by loading a 118
function code in the MTCS 1 control register
with the GO bit asserted. If the error is an
RH70 error, an INIT should be issued. The
INIT is issued by setting bit 5 (CLR) in the
MTCS 1 register.

When rewind is completed, the slave will assert
SSC which will cause the TM02 to raise ATTN
on the Massbus. In addition, the PIP bit will be
negated and BOT asserted. The clear can be
accomplished by performing a drive clear to the
TM02.

Read the MTDS drive status register and monitor the following bits.

Bit 10 (SPR) - This bit is set if the slave
specified in bits 0 through 2 of the MTTC tape
control register is powered up and properly
assigned.
Bits 0 through 7 - These bits specify the drive
type and are designated 0118 for the TU16
slave transports.
6.

Bit 15 (ATA) - This bit will set immediately (if
DRY is set) to indicate status change (completion of the rewind operation). If DRY is
negated, ATA will be asserted as soon as DRY
is asserted.
Bit 14 (ERR) - If this bit is set, it indicates an
error condition that can be detennined by
reading the MTER error register. At this point,
the software should enter the error recovery
procedure.
Bit 6 (SSC) - This bit will be set indkating
completion of the rewind operation.
Bit 1 (BOT) - This bit is set since the selected
slave detects the BOT marker when the wwind
is completed.

Read the following bits in the MTDS drive
status register.
Bit 12 (MOL) - If the medium on-line bit is
set, the drive is powered up and ready to go.
Bit 11 (WRL) - If the write locked bit is set,
the write operation is inhibited and it is
necessary to insert the write enable ring.
Bit 07 (DRY) - If this bit is set, it indicates
that the drive has concluded a previous operation (if one was specified) and is prepared to
accept or send data.
Bit 01 (BOT) - This bit is set if the tape is at
the BOT.

10.

3-42

Select the format, density and type of parity by
writing the MTTC tape control register in the
TM02. The format is written into bits 4
through 7 of the MTTC register (paragraph
1. 7.1).

The density is selected by writing bits 8
through lOin the MTTe register and is
described in Paragraph 3.6.14. The parity can
be specified even or odd for NRZI operation by
writing bit 3 of the MTTC register. If this bit is
set, even parity is read or written from tape.
Odd parity is always performed during PE
operation.
11.

Select the starting memory address by writing
the MTBA bus address register in the RH70.

12.

Select the number of 16-bit data words to be
transferred by writing the MTWC word count
register in the RH70 with the two's complement of the number of words to be transferred.

13.

Load the MTFC frame count register in the
TM02 with twice the word count for normal
format and with four times the word count for
core dump format. For normal format, two
tape characters are generated for each 16-bit
word, and, for core dump, four tape characters
are generated for each 16-bit word.

The read function code of 718 (with GO bit
asserted) is loaded in the MTCS 1 register
instead of the write function code.
If it is desired to do a read reverse operation,
the MTBA bus address register should be loaded
with the start of the buffer plus the size of the
record since the RH70 decrements the bus
address in a read reverse whereas it increments
the bus address in a read forward operation.

3.7.3 Space Operation
When a space operation is desired, the software must
specify the spacing length by loading the MTFC frame
count register with the two's complement of the number of
records it is desired to space.
A space operation will terminate either due to frame count
overflow (desired records are spaced over) or when BOT,
EaT, or TM (tape mark) is detected (signifying the end of
the fIle). The space operation allows random access of any
record within any file on tape.
3.7.4 Tape Mark Operation
To perform a write tape mark operation (to indicate the
end of file for example), it is merely necessary to load a
278 function code (with GO bit asserted) into the MTCS 1
control register. This can be monitored by reading bit 2
(TM) of the MTDS drive status register. When the bit is set,
the tape mark is detected.

14.

Load the MTCSI register in the TM02 with the
write function code (GO bit asserted) of 61 8 . If
the interrupt facility is employed, set the IE bit
(bit 6 of the MTCSI register in the RH70).

IS.

Read bit 4 (IDB) of the MTDS drive status
register. Upon completion of writing the
record, this bit should be set if PE density is
selected and should be cleared if NRZi density
is selected.

Tape marks can be used to indicate logical end of tape. A
single tape mark indicates termination of the previous file
while two tape marks indicate the logical end of tape (no
more data has been written).

This procedure will cause one record to be written on tape.
If it is desired to write another record, it is merely
necessary to reload the MTBA bus address register, the
MTWC word count register, and the MTFC frame count
register. Then the data transfer can be implemented by
loading the MTCSI register with the 618 write function
code (GO bit asserted).

3.8 SUGGESTED ERROR RECOVERY
Table 3-22 gives the suggested procedures for recovering
from drive or controller errors. The numbers in the column
titled "Recovery Procedure" are keyed to the following
steps:

3.7.2 Read Data Transfer
In order to do a read data transfer, a similar operation to
that just described is followed with the exceptions listed
below.
1.

It is not necessary to write the MTFC frame
count register, as this is automatically cleared
for a read data transfer.

If not programmer or operator error, then this
condition is fatal. Disconnect from drive, report
error to operator.

Tape position is lost, three possible recovery
procedures are indicated.
a.

3-43

If physical position of desired record is
known, Rewind, Space Forward to
desired record and retry.

The error classes are:
Qass A: EXC is asserted immediately but
transfer to the end of the current sector is
completed and normal EBL is asserted.

If neither alternatives a or b are possible
or practical, consider error fatal.

Qass B: EBL and EXC are asserted immediately. Data transfer stops.

Step
a.

Read Reverse

Read Forward

Repeat steps a and b until successful or
re-try count overflows (suggest 20
re-tries)

NOTE

If each record contains an identifiable
label (or sequence number), Read FWD
and/ or Read REV commands may be
used to re-establish tape position.

The numbers in the "Possible Operator Error" collumn are
keyed to the following steps:
Possible Operator Errors

If re-try count overflows, report to
operator

Wrong unit number (plastic button) plugged
into TM02.

Dirty read/write hea.ds or tape path (operator
PM). Also could be bad tape.

Operator did not insert rubber write-ring before
mounting tape which was to be written on.

Wrong unit number (plastic button) plugged
into TUI6, or tape not loaded with vacuum on.

Step
3.

Back-space

Erase

Re-write record

Repeat steps a, b, and c until successful
or re-try count overflows (suggest 20
re-tries)

If re-try count overflows, report error to
operator

Operator did not load tape to BOT, program
initiated a rewind, and tape unloaded. Power
was removed from TU16.

Report failure to operator

3-44

Table 3-22
Error Recovery Procedures

MTER
Bit Position

Name

Description

Type

Recovery
Procedure

Bad Data
Transferred

Tape Position
Lost

Possible
Operator Error

Possible Programmer Error

Illegal Function (ILF)

Indicates that an illegal function code has been transmitted.

Class B

Program is selecting function
code not implemented on
TWUl6.

Illegal Register (ILR)

Indicates that a read or write
from a nonexistent register
is attempted.

Class A

Program is selecting a register
which does not exist on TM02.

Indicates that while a transport operation is in progress
(GO = 1), a write into one
of the registers is attempted.
(Does not apply for the
Maintenance or Attention
Summary registers.)

Class A

None

Program did not check for
DRY = 1 before writing a
register (other than AS or MR).

Control Bus Parity (CPAR)

Indicates that incorrect control bus parity was detected
during an attempt to write
a TM02 register.

Class A

None

None if programmer is not using
Maintenance register.

Format (FMT)

Indicates that a data trans·
fer with an incorrect format
code is attempted.

Class B

None

Programmer is selecting a format
code which does not exist.

Data Bus Parity Error
(DPAR)

Indicates that incorrect data
bus parity has occurred during a write data transfer
(i.e., bad data transferred
to the TM02 and written on
tape.)

Class A

Yes

None

None if programmer is not using
PAT bit in RH70_

Incorrectable Data Error
or Vertical Parity Error
(INCjVPE)

During a PE data transfer
operation, indicates that an
incorrectable data error has
occurred.

Class A

(PE READ)-3
(PE WRITE)-4

Yes

None if programmer is not using
Maintenance register.

(NRZ READ)-3
(NRZ WRITE)-4

Yes

None if programmer is not using
Maintenance register.

During an NRZ data transfer
operation, indicates that a
vertical parity error has
occurred or that data has
occurred after the skew
delay is over.

Table 3-22 (Cont)
Error Recovery Procedures
MTER
Bit Position

Name

Description

Format Error or LRC
(PEF/LRC)

Recovery
Procedure

Type

Bad Data
Transferred

During a PE data transfer
operation, indicates that an
incorrect preamble or postamble is detected.

Class A

(PE READ)-3
(PE WRITE)-4

Maybe l
Yes

Indicates that the LRCC
which was written on tape
does not agree with the
LRCC calculated on the
data during a "read" command execution or during
the read after write operation which happens on a
"write" command execution.

Class A

(NRZ READ)-3
(NRZ WRITE)-4

Maybe 2
Yes

Tape Position
Lost

Possible
Operator Error

Possible Programmer Error
None if programmer is not
utilizing Maintenance register.

Nonstandard Gap (NSG)

Indicates that a tape character is detected during the
first half of the inter-record
gap. (i.e., tape unit thought
it saw end of record but
detected more data afier
shut-down process began.)

Class A

(READ)-3
(WRITE)-4

Maybe l
Yes

None if programmer is not
utilizing Maintenance register.

Frame Count Error (FCE)

Indicates that either:
I) a space operation has terminated and the Frame
Counter is not cleared.
(This is not a hardware
failure if space operation
was tenninated by TM,
EDT, or BOT if that
termination was expected.)

Class A

(SPACE)-2

Yes

Programmer loaded wrong frame
count on space command.

(WRITE)-I

Yes

2) A write command was
executed and the frame
count overflowed before
the word count.

I
I

3) A read command was
executed and the end of
record was detected before
word count overflow.

None

Programmer loaded a word count
value which was not proportional
to the frame count.

Table 3-22 (Cont)
Error Recovery Procedures
MTER
Bit Position

Recovery
Procedure

Bad Data
Transferred

Tape Position
Lost

Possible
Operator Error

(PE READ)-None
(PE WRITE)-4

No
Yes

No
No

2
2

None

(NRZ Read or Space)
TMK expected-None

None

(NRZ Read or Space)
TMK not expected-5

Yes

Software lost track of tape
position

(NRZ Write TMK)-4

Yes

None

Programmer did not check WRL
status.

2) A Space Reverse, Read reverse,
or Write Check Reverse is
attempted when the tape is
at BOT.

Yes

None

Program did not keep track of
tape position.

3) The DEN2 bit in the Tape
Control register does not
agree with the PES status
bit.

Program selected a transport
incapable of density mode
specified.

4) A space or write operation is
attempted when FCS = 0 in
the Tape Control register.

Program is trying to write
without specifying record
length.

5) An NRZ write operation is
attempted with the 2s complement of a number less
than 13 in the Frame Count
register.

Program is specifying record
length shorter than minimum of
I3 characters.

Name

Description

Type

Correctable Skew or Illegal
Tape Mark (CS/ITM)

During a PE data transfer operation, indicates that excessive
but correctable skew is detected
for read_ (This condition is only
a warning and does not indicate
bad data.) For a write, it indicates that data of questionable
quality was written and the
record should be re-written.

Class A

In NRZ mode, indicative of
illegal tape mark written on
tape after a "write tape mark"
command, or Read from tape
after a Read or Space command.

Nonexecutable Function
(NEF)

Indicates one of the following:
Class B
I) A write operation is attempted
on a write-protected transport.

Possible Programmer Error

Table 3-22 (Cont)
Error Recovery Procedures
MTER
Bit Position

Name

Description

Type

Drive Timing Error (DTE)

Indicates one of the following:
1) During a write operation,
the controller did not supply a tape character to
TM02 in time for it to be
written.

Class B

2) A data transfer (read/write)
was attempted when the
data bus of the Massbus
was already occupied (i.e.,
transfer in progres~ on
some other drive).

J:.-

Operation Incomplete (OPI)

I) During a read or space
operation, indicates that
a tape record has not
been detected within
7 sec from command initiation. Assume that the
drive is beyond valid data
on the tape.

Class B

Recovery
Procedure

Possible
Operator Error

Bad Data
Transferred

Tape Position
Lost

Yes

None

Program did not check controller "ROY" before issuing
data transfer command.

Yes

None on a write operation.
On a Read or Space, programmer
did not keep track of tape position.
On a Rewind operation, programmer did not check for BOT
before issuing command.

2) During a write operation,
indicates that a read-afterwrite tape record has not
been detected within 0.7
sec from command initiation. Assume write operation
has failed.
3) Additional data has been
detected after minimum gap
length has been traversed.
This condition causes a loss
of tape position.
4) Rewind command initiated,
tape already at BOT

Possible Programmer Error

Table 3-22 (Cont)
Error Recovery Procedures
MfER
Bit Position

Description

Type

Indicates one of the follOwing:
I) A program-rontrolled operation is attempted on a selected transport which is not
powered up, on-line, vacuum

Class B

Name
Unsafe (UNS)

Recovery
Procedure

Bad Data
Transferred

Tape Position
Lost

Possible
Operator Error

Possible Programmer Error

Yes
(If transfer
was in
progress)

Yes

Program did not check MOL
before issuing command.

(PE READ)-None
(PE WRITE)-4

No
Yes

None

(NRZ READ)-3
(NRZ WRITE)-4

Maybe 2
Yes

on.
2) An imminent power failure
is detected (AC LO L).

Correctable Data Error
or CRC Error (COR/CRC)

During a PE read operation,
indicates that a single dead
track has occurred. (Data is
corrected, this is only a
warning.)
PE Write - questionable
quality. Re-write.
During an NRZ operation,
indicates that the CRCC
read off the tape does not
match the CRCC computed
from the data read off the
tape.

Table 3-22 (Cont)
Error Recovery Procedures
MTCS2
Bit Position

Name

Description

Type

Massbus Data Bus Parity
Error (MDPE)

Set when a parity error occurs
on the Massbus data bus while
doing a read or write-check
operation.

Class A

Missed Transfer (MXF)

IClass B

Set if the drive does not respond
to a data transfer command
within 650 !AS.

Possible
Operator Error

Bad Data
Transferred

Tape Position
Lost

Yes

None

None if programmer is not
using PAT bit in RH70.

No
(No data
has been
transferred)

None

Programmer loaded a data
transfer command into a
drive which has ERR set.

Recovery
Procedure

Possible Programmer Error

ProGram Error (PGE)

Set when the program attempts
to initiate a data transfer operation while the RH70 is currently
performing one.

Class A

None

Program did not check RDY
prior to issuance of data
transfer command.

Non-Existent Memory
(NEM)

Set when the controller is
performing a DMA transfer
and the memory address
specifIed in MTBA is nonexistent (does not respond
to MSYN within 10 !AS.

Class A

Yes
(Transfer
incomplete)

None

Program specified memory
locations (via WC & BA
registers) which did not
exist.

Non-Existent Drive
(NED)

Set when the program reads or
Class A
writes a drive register (CSI, DS,
ER, MR, FC, DT, CK, TC, or SN)
in a drive [selected by U(02:00)]
which does not exist or is powered
down_ (The drive fails to assert
TRA within 1.5 !AS after assertion
ofDEM.)

Program attempted to read or
write a drive register on a drive
that did not exist.

Parity Error (PE)

Set if the RH70 detects bad data par- Class A
ity for a write or write check command or if cache notifies RH70 that
memory detected a bad address or
control parity on any data transfer.

Yes

None

I
(See CS3 register bits 15 - 13.

Table 3-22 (Cont)
Error Recovery Procedures
MTCS2
Bit Position

Name

Write Check Error (WCE)

Set when the controller is
performing a write-check
operation and a word on
the tape does not match
the corresponding word
in memory.

Class A

Data LaTe (DLT)

Set when the controller is
unable to supply a data
word during a write operation or accept a data word
during a read or write-check
operation at the time the
drive demands a transfer.

Class A

Description

Type

MTCSI
Bit Position

Name

Description

Recovery
Procedure

Bad Data
Transferred

Tape Position
Lost

Yes

None

WRITE-4
READ-3

Yes

None

Type

Possible
Operator Error

Possible Programmer Error
None

Massbus Control Bus
Parity Error (MCPE)

Set by parity error on
Massbus control bus while
reading a remote register
(located in the drive).

Class A

Transfer Error (TRE)

Set by DLT or WCE or PE
or NED or NEM or PGE or
MXF or MDPE or a drive
error during a data transfer.

See associated
error bits
above

Recovery
Procedure
1

Bad Data
Transferred

Tape Position
Lost

Notes:

Possible
Operator Error
None

Possible Programmer Error
None if programmer is not
using maintenance register.

Ilf the programmer knows how many frames should have
been read and the FC equals that number and there are
no other errors, the data is valid.
2

Possibility exists that CRCC character is in error so if
software checksum tallies, data is valid.

CHAPTER 4
TWU16 COMMAND REPERTOIRE

4.1 INTRODUCTION
This chapter contains a description of the TWU16 commands and provides a flow diagram of each command
showing the interaction between the RH70 Massbus Controller and the TUI6/TM02 Tape System.

(150 in./sec) rewind operation. The TU16 completes the
rewind operation independently, and the Massbus Controller and TM02 may divert attention to other transports.
When the reflective beginning-of-tape (BOT) marker is
detected, the TU16 terminates its high-speed reverse
motion, but will overshoot the BOT marker. The TU16
then initiates forward tape motion at read/write speed (45
in./sec). When it encounters the BOT marker again, the
capstan motor is deactivated. When the TU16 has completed its rewind operation, it asserts SET SSC (Slave Status
Change) on the slave bus and clears PIP. This causes the
Attention bit in the TM02 to be set, which results in ATTN
H being asserted on the Massbus thereby notifying the
Massbus Controller. If the Interrupt Enable {IE-bit 6 of
MTCSl) bit is set, the RHII will interrupt the CPU.

4.2 REWIND
A program-controlled rewind operation may be initiated by
one of two commands from the processor. One of these
commands (07 8 ) performs the rewind operation and retains
the transport on-line. The other command (03 8 ) places the
transport off-line immediately after command initiation.
Following completion of the 03 8 command, the operator
must use the ON-LINE/OFF-LINE switch on the transport
to return it to the on-line status.
To initiate a program-controlled rewind operation, the
address of the desired TM02 is placed on the Drive Select
lines of the Massbus via the MTCS2 Control and Status 2
Register in the RH70 (see Figure 4-1). The RH70 then
performs a register write into the MTTC Tape Control
register, selecting the slave TU16 desired to perform the
rewind operation. The TM02 places the Slave Select bits of
the Tape Control register on the slave bus. The RH70.
Massbus Controller then writes the operational function
code of the rewind command (03 8 or 07 8 ) into the MTCSI
Control and Status 1 register. The TM02 decodes the
function code and asserts RWND L on the slave bus. (If a
rewind/off-line operation has been specified, the TM02 also
asserts WRITE L.) It then checks for errors, and, if there
are none, initiates tape motion. The TM02 asserts DRY
(drive ready) which, in turn, asserts ATA and PIP (bit 13
MTDS register). If the Interrupt Enable (IE-bit 6 of MTCS 1
register) bit is set in the RH70, the ATTN will cause the
RH70 to in term pt the CPU.

4.3 SPACE
To initiate a space operation, the address of the desired
TM02 is placed on the Drive Select lines of the Massbus via
the MTCS2 Control and Status 2 Register in the RH70 (see
Figure 4-2). The RH70 then performs a register write into
the MITC Tape Control register selecting the slave TU16
desired to perform the space operation. The TM02 places
the Slave Select bits of the Tape Control register on the
slave bus.

The RH70 Massbus Controller then loads the 2s complement of the number of tape records to be spaced into
the TM02 Frame Count register. Following this, the RH70
loads the MTCSI Control and Status 1 register with the
operational function code of the space command (31 for
space forward, 33 for space reverse). The TM02 decodes the
function code and asserts FWD L or REV L on the slave
bus. It then checks for errors and, if there are none,
initiates tape motion.

The TUI6, enabled by its address code on the Slave Select
lines (SS 0-2), activates the capstan drive for a high-speed

4-1

LOAD CONT.
& STATUS 2
REGISTER

SELECTS
TMO:2

LOAD TAPE
CONTROL
REGISTER

SEU,CTS TU16

LOAD COMMAND
INTO CONTROL
REGISTER

REWIND
COMMAND

YES

COMMAND
ABORTED·SEE
ERROR FLOW

INITIATE TAPE
MOTION
(GO OFF·LlNE*1
REWIND
OFF·LlNE

TERMINATE
TAPE
MOTION

ASSERTSSC,
CLEAR PIP

TM02 ASSERTS
ATTN

RH70 INTERRUPTS
PU IF IE BIT SET

*THESE EVENTS DO NOT OCCUR IF REWIND GOES OFF·LINE.
11-3015

Figure 4-1 Rewind Operation Flowchart

4-2

If end-of-tape (EaT), beginning-of-tape, or tape mark is
detected, tape motion is terminated. If not, spacing
continues until the interrecord gap (IRG) is reached. This
causes the MTFC Frame Count register to increment and a
motion delay to occur which terminates tape motion. If the
frame count is not equal to zero, or EaT or BOT is not
detected, tape motion is initiated again until an interrecord
gap is detected again which reincrements the Frame Count
register. This sequence continues until the Frame Count
register is equal to zero or until EaT or BOT is detected
indicating that the desired number of records has been
spaced over. The space operation is performed at a constant
speed of 4S in./sec.
When frame count overflow, or EaT or BOT is detected,
the TM02 asserts DRY indicating completion of the
operation by the drive. The TM02 also asserts ATTN to the
RH70. If the Interrupt Enable (IE-bit 6 of MTCSl) is set,
the RH70 will interrupt the CPU.

COMMAND
ABORTED
SEE ERROR
FLOW

4.4 ERASE
To initiate an erase operation, the address of the desired
TM02 is placed on the Drive Select lines of the Massbus via
the MTCS2 Control and Status 2 Register in the RH70 (see
Figure 4-3). The RH70 then performs a register write into
the MTTC Tape Control register selecting the slave TU16
desired to perform the erase operation. The TM02 places
the slave select bits on the Tape Control register on the
slave bus. The RH70 then loads the MTCSI Control and
Status 1 register with the operational function code (25 8 )
of the erase command. The TM02 decodes the function
code and asserts FWD L and WRITE L on the slave bus. It
then checks for errors, and, if there are none, causes the
TU16 to energize the write and erase heads and initiates
tape motion.

ABORT
TERMINATION
SEQUENCE

The TU16, which is enabled by its address code on the
Slave Select lines, responds to SLAVE SET Pulse by
activating the capstan drive (starting forward tape motion)
and by activating the write and erase heads.
Since the erase head is activated and the wri te heads receive
no data input during an erase operation, all the tape moving
past the erase head will be dc erased.
The erase operation is terminated by the TM02 asserting
STOP L on the slave bus which deactivates the capstan
motor in the TU16. When tape motion has ceased, the write
and erase heads are deenergized. The TM02 asserts DRY
indicating completion of the operation by the drive. The
TM02 also asserts ATTN to the RH70. If the Interrupt
Enable (IE-bit 6 of MTCSl) bit is set, the RH70 will
interrupt the CPU.

11-3014

Figure 4-2 Space Operation Flowchart

4-3

LOADCONT.
& STATUS 2

4.5 PE DATA READ
To initiate PE read operation, the address of the desiired
TM02 is placed on the Drive Select lines of the Massbus via
the MTCS2 Control and Status 2 register in the RH70 (see
Figure 44). The RH70 then performs a register write inte
the MTTC Tape Control register specifying th(: selec:tec
TU16 slave, tape character format, and tape dens.ity (160(
bpi for PE).

SELECTS
TM02

SELECTS
TU16

The TM02 places the slave selects (SS 0-2) and densit)
(DEN 0-2) bits of the Tape Control register on the slavl
bus. The RH70 then loads the MTCSI Control and Status:
register with the operational function code of a lrea(
operation (718 read forward, 77 read reverse, 51 writl
check forward, or 57 write check reverse) and aS8erts Rill
on the Massbus. The TM02 decodes the function code anI
asserts FWD L or REV L on the slave bus. It then check
for errors, and, if there are none, asserts OCC on thl
Massbus to notify the controller and other drive~i that it i
occupying the data bus of the Massbus. The TM02 the]
transmits SLA VB SET Pulse to the TUI6.

ERASE
COMMAND

YES

COMMAND
ABORTED-SEE
ERROR FLOW

ENERGIZE
WRITE AND
ERASE HEADS
INITIATE
TAPE
MOTION

The TUI6, which is enabled by its address code on th
Slave Select lines (SS 0-2) of the slave bus, responds tl
SLAVB SET Pulse by activating the capstan drive moto
and initiating tape motion.

The TU16 read amplifiers are on continuously. Even as th
tape accelerates, the TM02 PE read circuitry checks for
PE identification burst (IDB) and begins looking ~or
preamble. When the tape is at speed, the preamble wiU b
detected and read; the tape characters immediately afte
the preamble all-Is character are data characters.

TM02 ASSERTS
DRY

The characters are assembled into 18-bit words and place
on the data bus of the Massbus. TIlis action contlnues unt
the first character of the postamble is detected.

TM02 ASSERTS
ATTN

RH70 INTERRUPTS
CPU IF IE BIT SET

The TM02 reads the postamble which signifies the en d e
the record and asserts EBL H (end-of-block) on th
Massbus. When the gap has been detected, the TMO
terminates tape motion, asserts DRY, and negates EBL. Th
negation of EBL causes the .RH70 to go to the RD'
(Ready) state causing the RH70 to interrupt the CPU if th
Interrupt Enable (IE-bit 6 of MTCSl) bit is set.

'1·3012

Figure 4-3 Erase Operation Flowchart

CONVERT DATA
CHARACTERS
INTO 18 BIT WORD
TRANSMIT WORD

TM02 ASSERTS
EBL

COMMAND
ABORTED - SEE
ERROR FLOW

IF ALL DATA
TRANSFERRED
TO MEMORY

11-3013

Figure 4-4 PE Data Read Operation Flowchart

4-5

4.6 NRZ DATA READ
To initiate an NRZ read operation, the address of the
desired TM02 is placed on the Drive Select lines of the
Massbus via the MTCS2 Control and Status 2 register in the
RH70 (see Figure 4 5). The RH70 then perfonns a register
write into the MTTC Tape Control register, specifying
selected slave TUI6, tape character fonnat, and tape data
density. The TM02 places the slave select (SS 0-2) and
density (DEN 0-2) bits of the Tape Control register on the
slave bus. The RH70 then loads the MTCSI Control and
Status 1 register with the operational function code of a
read operation (718 read forward, 77 read reverse, 51 write
check forward, or 57 write check reverse) and asserts RUN
H on the Massbus. The TM02 decodes the function code
and asserts FWD L or REV L on the slave bus. The TM02
then checks for errors, and, if there are none, asserts OCC
on the Massbus to notify the controller and other drives
that it is occupying the data bus of the Massbus. The TM02
then transmits SLAVE SET Pulse to the TU16. The TUI6,
which is enabled by its address code on the Slave Select
lines (SS 0-2) of the slave bus, responds to SLAVB SET
Pulse by activating the capstan drive motor and initiating
tape motion.

CRCC is encountered next, and strobed into the Check
Character register, but otherwise it is ignored. No CRC or
LRC error is generated. Then the data is read; assembly of
characters into data words may differ when reading in the
reverse direction, but this depends on the data format
selected.

When the data and LRCC/CRCC have been read, the TM02
asserts EBL. When the interrecord gap is detected, the
TM02 asserts DRY, terminates tape motion, and negates
EBL. The negation of EBL causes the RH70 to go to the
RDY (Ready) state and will cause the RH70 to interrupt
the CPU if the Interrupt Enable (IE-bit 6 of MTCS 1) bit is
set.

4.7 PE DATA WRITE
To initiate a PE write operation, the address of the desired
TM02 is placed on the Drive Select lines of the Massbus via
the MTCS2 Control and Status 2 register in the RH70 (see
Figure 4-6). The RH70 then performs a register write into
the MITC Tape Control register, specifying selected slave
TUI6, tape character format, and tape data density
(PE - 1600 bpi). The TM02 places the slave select (SS
0-2) and density (DEN 0-2) bits of the Tape Control
register on the slave bus. The RH70 then loads the 2s
complement of the number of tape characters to be written
into the TM02 Frame Count register. Following this, the
RH70 Controller loads the MTCS1 Control and Status 1
register with the operational function code (61) of the da1ta
write command. The TM02 decodes the function code and
assets FWD L and WRITE L on the slave bus. It then checks
for errors, and, if there are none, asserts OCC on the
Massbus to notify the controller and other drives that it is
occupying the data bus of the Massbus.

When a tape character is detected by the TUI6, it is
multiplexed onto the slave bus Read Data lines and is
strobed into the TM02. LRCC and CRCC are generated
from the data and will be used to check the validity of the
data read.
The TM02 assembles the characters into IS-bit data words
and places them on the data bus of the Massbus. When a
data word is assembled by the TM02, the TM02 notifies the
RH70 which strobes the word from the data bus. The
assembling of data characters into IS-bit words continues
until the end of the data record as represented by an all-Os
tape character.

When the RH70 has data available for transfer, it asserlts
RUN H on the Massbus. The TM02 responds by a:iserting
SLA VE SET Pulse on the slave bus and accepting the first
data word from the RH70.

During a forward read, the rest of the read circuitry
continues its operation, reading the CRCC and strobing it
into the Check Character register, and then reading the
LRCC. Discrepancies between generated CRCC/LRCC and
detected CRCC/LRCC cause their respective error bits to be
set.

The TU16, which is enabled by its address code on the
Slave Select lines (SS 0-2) of the slave bus, responds to
SLAVE SET by activating the capstan drive motor for
forward tape motion and by turning on the write and erase
heads. The first data word, loaded on the Massbm when
RUN is asserted, is accepted by the TM02.

During a reverse read, the LRCC character is encountered
first at the start of the read operation, but is ignored. The

4-6

CONVERT DATA
CHARACTERS TO
18·BIT WORD AND
TRANSMIT WORD

ASSERT EBL

COMMAND
ABORTED SEE
ERROR FLOW

IF ALL DATA
TRANSFERRED
TOMEMORV

11·3011

Figure 4-5 NRZ Data Read Operation Flowchart

4-7

LOAD CONT.
& STATUS 2
REGISTER

SELECTS
TM02

LOAD BUS
ADDRESS

LOAD TAPE
CONTROL
REGISTER

SELECTS TU16

IGENERATE
WRITE CLOCK
LOAD FRAME
COUNT
REGISTER

LOAD COMMAND
INTO CONTROL
REGISTER

WRITE
COMMAND

RECEIVE
DATA WORD

COMMAND
ABORTED
SEE ERROR FLOW

TM02 ASSERTS
EBL

TURN ON
WRITE AND
ERASE HEADS
START TAPE
MOTION

RECEIVE
DATA WORD

TM02 NEGATES
EBL

~_R_D_Y ~~------~

__R_H_7_0__
L

TM02 ASSERTS
DRY

RH70
INTERRUPTS
CPUIFIE
BIT SET

11-3010

Figure 4·6 PE Data Write Operation Flowchart

4·8

When the TU16 is up to speed, it transmits a WRT CLK
signal to the TM02. Upon receipt of WRT CLK, the TM02
begins generating a preamble. When forty all-O characters
and one all-l characters have been written, the TM02 begins
disassembling the first data word into characters. When it
has disassembled the first data word, it requests the next
data word from the RH70 Massbus Controller and continues to do so until all the data words have been
transferred. Each time the TM02 generates a character, the
Frame Count register is incremented, a vertical parity bit is
generated, and the tape character is converted to PE mode
and transmitted to the write circuitry of the TU16. When
the Frame Count register overflows to zero, the TM02
generates a postamble which is written on tape and asserts
EBL. During the entire operation, the TU16/TM02 read
operation is active and reads the record being written.

When the TU16 is up to speed, it transmits a WRT Cll
signal to the TM02. Upon receipt of WRT CLK, the TMO:
begins disassembling the first data word into characters.

When the TUI6/TM02 read circuitry detects the end of the
record, the TM02 asserts DRY, terminates tape motion, and
negates EBL. The negation of EBL causes the RH70 to go
to the RDY state, and causes the RH70 to interrupt the
CPU if the Interrupt Enable (IE-bit 6 of MTCS 1) bit is set.

During the time that the tape is moving at speed, th(
TUI6/TM02 performs a read-after-write operation.

When it has disassembled the first data word, it requests thl
next data word from the RH70 Massbus Controller, ane
continues to do so until all the data words have bee I
transferred. Each time the TM02 generates a character, thi
Frame Count register is incremented, a vertical parity hit i
generated, the CRCC is generated, and the tape character i:
transmitted to the write circuitry of the TU16 where it i:
converted from binary to NRZ mode (1s become transi
tions) and written on the tape. When the Frame Coun
register overflows to zero, the TM02 transmits EBI
(end-of-block) to the RH70. It then generates the timing t<
write the generated CRCC and the LRCC.

When the TUI6/TM02 read circuitry detects the end of,
record, the TM02 asserts DRY, tenninates tape motion, an<
negates EBL. When tape motion stops, the write and eras(
heads are deenergized.

4.8 NRZ DATA WRITE
To initiate an NRZ write, the address of the desired TM02
is placed on the Drive Select lines of the Massbus via the
MTCS2 Control and Status 2 register in the RH70 (see
Figure 4-7). The RH70 then performs a register write into
the MTTC Tape Control register specifying selected slave
TUI6, tape character fonnat, and tape data density. The
TM02 places the slave select (SS 0-2) and density (DEN
0-2) bits of the Tape Control register on the slave bus. The
RH70 then loads the 2s complement of the number of tape
characters to be written into the TM02 Frame Count
register. Following this, the RH70 loads the MTCSI
Control and Status 1 register with the operational function
code (61) of the data write command. The TM02 decodes
the function code and asserts FWD L and WRITE L on the
slave bus. It then checks for errors, and, if there are none,
asserts OCC on the Massbus to notify the controller and
other drives that it is occupying the data bus of the
Massbus.

The negation of EBL (end-of-block) causes the RH70 to gc
to the RDY (Ready) state and causes the RH70 to interrup1
CPU if the Interrupt Enable (IE-hit 6 of MTCS 1) is set.
4.9 WRITE TAPE MARK
To initiate a write tape mark operation, the address of the
desired TM02 is placed on the Drive Select lines of the
Massbus via the MTCS2 Control and Status 2 register in the
RH70 (see Figure 4-8). The RH70 then performs a registeI
write into the MTTC Tape Control Register, selecting the
slave TU16 to perform the write tape mark operation and
the density at which the tape mark characters are to be
written. The TM02 places the slave select (SS 0-2) and
density select (DEN SEL 0-3) bits of the Tape Control
register on the slave bus.

When the controller has data available for transfer, it asserts
RUN H on the Massbus. The TM02 responds by asserting
SLAVB SET Pulse on the slave bus and accepting the first
data word from the RH70.

The RH70 Massbus Controller then loads the MTCSI
Control and Status 1 register with the operational function
code (27) of the write tape mark command. The TM02
decodes the function code and asserts FWD L and WRITE
L on the slave bus. It then checks for errors, and, if there
are none, issues SLAVB SET to the TU16.

The TUI6, which is enabled by its address code on the
Slave Select lines (SS 0-2) of the slave bus, responds to
SLAVE SET by activating the capstan drive motor for
forward tape motion and by activating the write and erase
heads. The first data word, loaded on the Massbus when
RUN is asserted, is accepted by the TM02.

The TUI6, which is enabled by its address code on the
Slave Select lines, responds to SLAVB SET by activating
the capstan drive (starting tape motion) and by activating
the write and erase heads. As tape moves past the heads, it
is erased. After a 3 inch acceleration delay, the TM02
generates the tape mark.
4-9

LOADCONT.

8r STATUS 2
REGISTER

SELECTS
TM02

CONVERT DATA
WORDS TO TAPE
CHARACTERS

RECEIVE DATA
WORD

SELECTS TU16.
DENSITY
FORMAT

LOAD FRAME
COUNT REGISTER

LOAD COMMAND
INTO CONTROL
REGISTER

WRITE
COMMAND

TM02 ASSERTS

COMMAND
ABORTED· SEE
ERROR FLOW

CHARACTERS
AND WRITE

SPACE 3
CHARACTERS
AND WRITE
LRCC

TERMINATE
TAPE MOTION

TM02 NEGATES
EBL

ASSERTS
DRY

ERASEIRG

TURN OFF WRITE
8r ERASE HEADS

TURN OFF
ERASE AND
WRITE HEADS

INITIATE
TAPE
MOTION

ERASE IRG

RH70
INTERRUPTS
CPU IF IE
BIT SET

ERASE
IRG
RECEIVE
DATA
WORD

TURN OFF WRITE

8r ERASE HEADS

11-3008

Figure 4-7 NRZ Data Write Operation Flowchart

4-10

LOAD CONT.
& STATUS 2
REGISTER

SELECTS
TM02

NO
SELECTS TU16 DENSITY

LOAD COMMAND
INTO CONTROL
REGISTER

WRITE TAPE
MARK
COMMAND

TM02
ASSERTS
DRY

COMMAND
ABORTED
SEE ERROR FLOW

TERMINATE
TAPE
MOTION

TM02
ASSERTS
ATTN

TURN OFF
WRITE AND
ERASE HEADS

RH70 INTERRUPTS
CPU IF IE BIT SET

TURN ON WRITE
AND ERASE
HEADS
INITIATE TAPE
MOTION

GENERATE
AND WRITE
TAPE MARK

GENERATE
WRT CLOCK

11-3009

Figure 4-8 Write Tape Mark Operation Flowchart

4-11

If the TU16/TM02 is operating in PE mode, slave bus write
lines WD 3, 4, 6, and 7 are forced high, while PE Os are
generated for WD 0, 1, 2, and 5. At the same time record
pulses (40 X 2 = 80) are transmitted to the TU16. As a
result, forty Os are written in tracks 1, 2, 4, 5, and 8, and
the remaining tracks are erased.

4.10 ERRORS
TM02 errors may occur at command initiation or at
command execution. The error handling for each type is
described below.

Command Initiation - Any error that occurs when a
command is initiated (GO bit asserted) will cause an
immediate abort. The error will assert EXC (if it is a data
transfer command) and during command initiation will also
assert ATINand EBL (see Figure 4-9). The assertion of
EBL and ATTN will cause the RH70 to interrupt the CPU
if the IE bit is set. The assertion of EXC causes TRE in the
RH70 to set. TRE is monitored in bit 14 of the MTCS1
register.

If the TU16/TM02 is operating in NRZ mode, the tape
mark character is forced onto the slave bus WD lines, and a
record pulse is transmitted to the TU16. The TU16 is then
allowed to erase seven character lengths of tape at which
time it receives LRC STROBE on the slave bus and writes
an LRCC (which will be the same as the tape mark
character).

Command Execution - During the execution of a com-'
mand, Class A or Class B errors may occur and are handled
in the following manner.

After writing the NRZ or PE tape mark, the TU16/TM02
continues to erase tape. As the write tape mark operation is
performed, the read circuitry performs a read-after-write.

Class A: If a class A occurs during execution of a
data transfer command, EXC is raised immediately
but the command will not terminate until the
operation is completed. This occurs at the end of the
record when ATIN and EBL are asserted. Note that
EXC asserts TRE which can be monitored vita bit 14
of the MTCS1 register.

After the read circuitry has detected the written tape mark,
the TM02 transmits STOP L to the TU16. This signal
deactivates the capstan motor to terminate tape motion.
When tape motion has stopped, the write and erase heads
are deenergized. The TM02 asserts DRY indicating that the
drive is ready to perform another function. The TM02 also
asserts ATIN to the RH70. The RH70 will interrupt the
CPU if the Interrupt Enable (IE-bit 6 of MTCSl) bit is set.

Class B: If a class B error occurs during execution of
a command, EXC, ATTN and EBL an~ raised
immediately and the command is terminated. If 1the
command is a data transfer command, EXC is also
asserted which sets TRE in the RH70.

4-12

CHAPTER 5
THEORY OF OPERATION

5.1 GENERAL
This chapter describes the theory of operation of
the RH70 Controller in two functional groupings the Register Control Path and the Data Path.
These are described in detail in the following
paragraphs.

addresses may vary in different subsystems, depending on the number of registers within a given system. Consequently, the registers are logically
defined as being the last two registers in a system.
The number of registers is classified as the register
length field.
The logic implements this in the following manner.
Address bits 4 - 2 from the Unibus are compared
to the register length field consisting of a set of
jumpers weighted 2, 4, 8, and 16.

5.2 REGISTER ACCESS CONTROL PATH
The Register Control Path provides the interface
that enables the program to read from or write into
any register in the RH70 or associated drive. Specific bits in these registers are designated as follows:

NOTE
If the subsystem contains more than 16 registers, address bit 5 from the Unibus is also compared to the
jumpers selected in the register length field.

Read only bits indicate that the program can read
the status of these bits but cannot load them; write
only bits indicate that the program can load them
but will read back a 0; read/write bits indicate that
the program may load them and read back the
status.

The Unibus address bits and the register length
field jumpers are compared in a comparator which
yields the following outputs:
A> B - denotes that the register length field is
greater than the Unibus address specified, indicating that a valid register has been addressed. If the register is remote, a Massbus
cycle is initiated.

The RH70 examines Unibus address bits 17 - 05
(17 - 06 if there are a total of more than 16 registers) to determine if the register being addressed is
an RH70 register (Figure 5-1). The address field
can be defined by a set of jumpers within the
RH70. The Unibus address is compared with the
set of jumpers and if the two match, the addressed
register is a valid RH70 register, which enables the
circuitry for a register function. If the Unibus address does not compare with the jumpers, the
RH70 will not accept the address and will not initiate a data transfer with the processor.

A <B - denotes that the Unibus address is
greater than the register length field, indicating that an illegal register has been
addressed.
A= B - indicates that either the CS3 or BAE
register has been specified. If address bit 01 is
asserted, the CS3 register is specified; if the
bit is unasserted, the BAE register is specified.
For this case, no Massbus cycle is initiated.

The RH70 contains two registers (Bus Address Extension and Control and Status 3 registers) which
float in the Massbus address field. Their respective

5-1

BUS
DATA

BAE OUT
(FROM
DECODER)

BUS
SSYN

BA OUT
(FROM
DECODER)

SSYN
(FROM BAE
SSYN BUS
LOGIC)
ADDRESS
EXT AWRB

CSI OUT
(FROM
DECODER)

BA
BUS
ADDRESS
AWRA,B

CSI
CONTROL
8 STATUS
CSTA,B
CLOCK
BA

CS2 OUT
(FROM
DECODER)

CS2
CONTROL
8 STATUS
CSTA,B

DATA
BUFFER
(8 WORDS)

MDPB,C,F
CLOCK
CS2

CLOCK
CSI

CS3 OUT
(FROM
DECODER)

DB OUT
(FROM
DECODER)

WC OUT
(FROM
DECODER)

WC
WORD
COUNT
AWRD,E

CS3
CONTROL
STATUS
CSTA,C

RECEIVERS

MBSA,B,C
III

CLOCK
CS3

CLOCK
DB

MASS
C(15'OO)

ffi

MASS

~C.:...(1-5-'O-O....:.)--4~ ~
III
III

BUS
MSYN

III

!"REGiSTER - - ~~fR - - -

I CLOCK LOGIC
I (TYPICAL)
WC IN L
I
(FROM

MSYN

- - - - - -r---------,
RECEiVERS

o
z
o

HI, LO BYTE

a::

:I:

III

L _ -"~O~R2.... _ _ _ _ _ _ -1

BUS
A(17'05)

------

MASS TRA

ADDRESS
LOGIC
BCTA

BUS
A0,C0,Cl

BUS
A(04'OO)

CNTRL OUT L
WC IN L, WC OUT L
AS IN L, AS OUT L
CSI IN L, CSI OUT L
CS2 IN L, CS2 OUT L
CS3 IN L, CS3 OUT L
DB IN L, DB OUT L
BA IN L, BA OUT L
BAE IN L, BAE OUT L

------

-----BCTA

MASS CTOD

CTOD
....---...,REG SELECT
MASSBUS
DEMAND

L-----------------------------------~CONTROL

DRIVERS ~------------------------------------------------------~
MASS DEM

REMOTE
BCTA,B

MBSA,B,C

11-2588

Figure 5-1

5.2.1 Writing a Local Register
Unibus address bits 04 - 01 (05 - 01 if more than
16 registers are employed) select a cell in a Read
Only Memory (ROM) which specifies a unique register. The ROM outputs are register select signals
(RSEL 04:00), two coded bits (M 6 and M7), and a
LOCAL REG H signal. Since this description involves accessing a local register (one contained in
the RH70), LOCAL is generated at the output of
the ROM as LOCAL REG H. When this signal is
unasserted or low and a register operation is being
performed, a remote register (unless CS3 or BAE)
is selected. Signals RSEL 01:00 and M6 and M7
are supplied to the register decoders to select one of
the local registers. RSEL 04:00 is also supplied to
the Massbus control logic, but is inhibited from the
Massbus because a "write local register" function is
specified and REMOTE REG remains unasserted.

The data is clocked into the WC register at the
time of REG STR. The trailing edge of this signal,
which is ISO ns long, causes SSYN to be asserted.
The central processor receives SSYN and lowers
MSYN, which deselects the RH70 from the
Unibus. The lowering of MSYN then causes SSYN
to be lowered, and 75 ns after the lowering of
MSYN, the address lines change and the cycle is
completed.

5.2.2 Reading a Local Register
The process of reading a local register is the same
as that described for writing a local register (Paragraph 5.2.1) with the following exceptions:

Unibus control lines AO, CO, and CI specify the direction of transfer and also specify byte or word addressing. When writing a register, the CO and CI
lines are encoded for a DATO or DATOB (if byte
addressing is specified). The AO, CO, and CI control lines are supplied to a direction control network which generates IN, OUT, HI BYTE, or LO
BYTE signals, depending on the cycle desired.
These signals are fed to the register decoder where
they are used in decoding the various register enable signals.

The CO and CI Unibus control lines are
decoded for a DA TI or DA TIP
operation.

When reading a local register, the register "OUT" signals of the register select
decoders gate the contents of the register
on the BUSI lines for transmission to
the processor via the Unibus.

5.2.3 Writing a Remote Register (Figure 5-2)
A remote register is defined as a register located in
the drive. The data path for writing a remote register is from the Unibus via data lines DOO-DI5 IN
H on to the Massbus, via control lines MASS
COO-CIS H, where the data is received by the selected drive and loaded into the specified register in
that drive. A CTOD (Controller to Drive) signal on
the Massbus specifies the direction of transfer to
the drive.

The Unibus data lines are connected to the RH70
and contain the data used to load the desired
register.
When BUS MSYN is received from the central processor (150 ns after the data, control and address
are placed on the Unibus), a DEV SEL (Device Select) signal is generated, which enables the register
decoder to generate the appropriate enable signal
for the register specified. Signal REG STR is created 85 ns later and is ANDed with the HI BYTE
or LO BYTE signal and the specified register enable signal from the register decoder. The signals
designated IN are used for writing local registers;
the signals designated 0 UT are used for reading local registers. For example, if it was desired to write
into the WC (Word Count) register, the register
decoders specify the WC IN L signal, which is ANDed with HI BYTE or LO BYTE and REG STR
to generate a clock used to load the WC register.

The upper address bits of the Unibus address are
compared with a set of jumpers in the RH70 to enable the register selection logic, previously described. Unibus address bits 04 - 0 I (05 - 0 I if
more than 16 registers are employed in the system)
select a cell in the ROM (Read Only Memory)
which specifies a particular register. The outputs of
the ROM are register select signals RSEL (04:00),
two coded bits (M6 and M7), and the LOCAL
REG signal. The selected drive, whose unit number
was preloaded by the programmer in the CS2 register, is specified by device select lines DSOO - DS02
on the Massbus.

5-3

CENTRAL
PROCESSOR

RS04/RSlO3

RH70 CONTROLLER

I,CONFIGURATION
JUMPER ~
BUSA A (17:05)

.....

XOR
V

BUSA A (04:01)

.....

CS2

~~
H

BUSA C (01:00)
JDIRECTION
CONTROL

BUSA AOO

MASS RS (04:00)"

"
/

'-----MASS C (15:00) .....

)

...
'----MASS CTOD

~
DRIVER
ENABLE
LINE

EQUAL

I
I

DIR TRANS

I
I
I

150NS

DRIVERS

~ -----

L..REMOTE

BUSA 0 (15:00)

MASS OS (2:0) ....

.....,

RSEL

ENCODER;
(ROM) I

I
~ (02:00)~

~DEV SEL

:Q
I I

BUSA MSYN

85NS
DELAY

1150NS

~~REG
STR

REMOTE-

r----

MASS OEM

OEM
STROBE
DATA
INTO
REG.

Lc
~

BUSA SSYN

J SET SSYN L
I

J DESELECT I

BUSA MSYN

-, (DEV SEL)

MASS TRA

J CLR a OEM 1
I SSYN r
I

BUSA SSYN

MASS OEM
MASS TRA

r:i!i~J
RS03

~~ ALL EVENTS WITHIN BRACKET OCCUR
AT APPROXIMATELY SAME TIME.
11-3464

Figure 5-2 Writing Remote Register Interface

5-4

When the MSYN signal is received over the Unibus
by the RH70, the DEV SEL signal is enabled and a
delay of 235 ns occurs before the RH70 issues
DEM to the Massbus. This delay allows the select
and data lines to settle and be decoded on the Massbus before the drive strobes the Massbus control
lines. When the drive receives DEM and recognizes
the unit address as its own, and when the data has
been clocked into the appropriate drive register, it
issues transfer (TRA) to the RH70. When the
RH70 receives TRA, indicating that the drive has
obtained the data, it issues SSYN to the processor.
SSYN signals the processor that the slave (RH70)
has finished the cycle, and the processor removes
MSYN, which in turn causes SSYN to go unasserted. Also, MSYN going unasserted, removes the
DEV SEL signal which causes DEM to drop. This
action in turn causes TRA from the drive to go
unasserted. The address and data is then removed
from the Unibus and Massbus to complete the
cycle.

designed to accept or provide memory with single(16 bits) or double-word (32 bits) data and to convert double words to single words for transfer to
the Massbus. Parity checking and generating is also
provided for Massbus and memory data words.
Due to the complexity of the Data Buffer (DB), a
built-in maintenance feature has been incorporated
that allows the programmer to write into the DB as
a register, thereby allowing a succession of data
words to be sequenced through the DB and read
back via a read from the DB. In this way, the data
path and parity generator and checker for the Massbus can be easily verified.
5.3.1 Data Buffer Maintenance Operation
Figure 5-4 shows the data path used when the programmer attempts to read or write the DB register
during maintenance operations. The RA, RB, RC,
RD and RE - OBUF registers contain associated
flags (RA FULL, RB FULL, RC FULL, RD
FULL, RE FULL, - OBUF FULL) to designate
the status of their respective registers. The RA or
RB FULL flags are presented to the programmer
via the IR (Input Ready) status bit (bit 06) in the
CS2 Control and Status 2 reg ister. When the hardware selected flag (RA FULL or RB FULL) is asserted (register is full), the Input Ready Status is
negated, indicating that the register is not available
to receive a word. The OBUF FULL flag is presented to the programmer via the OR (Output
Ready) status bit (bit 07) of the CS2 Control and
Status 2 register. When the OBUF FULL flag is asserted, it indicates that the contents of OBUF are
full (has a valid data word) and that the programmer can read the data buffer.

5.2.4 Reading a Remote Register (Figure 5-3)
The process of reading a remote register is similar
to that of writing a remote register with the following exceptions:
1.

The data path for reading a remote register is from the drive to Massbus control
lines COO - CI5 H, to the RH70 opencollector multiplexers (8234), to the
BUSI lines, and then to the Unibus data
lines DOO-D 15.

Upon receipt of TRA when writing a remote register, SSYN is immediately sent
to the CPU. When reading a remote register, however, SSYN is delayed 220 ns
from TRA to ensure that the data is present and settled on the Unibus.

The data path also contains three steering signals
used to alternate the flow of data between the
right- and left-hand sides of the data path: RB
ENA, RD ENA, and MXR SEL. When the system
is first initialized, by asserting INIT on the Unibus,
or by setting the CLR bit in the CS2 register, the
RB ENA flip-flop is pointing to the RA register,
the RD ENA flip-flop is pointing to the RC register, and the MXR SEL logic is pointing to the RC
register. This primes the right-hand side of the data
path to accept the first data word.

5.3 DMA DATA PATH
The DMA data path (Figure 1-2) is used for memory-to-Massbus data transfers or from Massbus-tomemory data transfers. The data path consists of
an eight-word data buffer and associated data buffer control logic. The data buffer provides for temporary storage of up to eight data words. It is

5-5

RS04/RS03

RH70 CONTROLLER

CENTRAL
PROCESSOR

JUMPER

CONFIGURATION

BUSA A (17:05)

Jo\,.

I
~ (02:00)~
CS2

XOR
If'

BUSA A (04:01)

I\,.

~'"

C) -----

RSEL

ENCODER!
(ROM) J

L.REMOTE
BUSA C (01:00)

I
I

EQUAL

150;NS

MASS RS (04:00)"

....

-----

MASS CTOD

4~
DRIVER
ENABLE

~
I

BUSAtMSYN

....

DIR TRANS

JDIRECTION
CONTROL

BUSA AOO

MASS OS (2:mJo\,.
DRIVERS

~DEV SEL
~

85NS
DELAY

I +

150NS
DELAY

r--REMOTE

MASS OEM

OEM
GATE
DATA
TO
BUS

A BUS A 0 (15:00)

MASS C (15:00)

REC E I VERSI
I DRIVERS

~
1'10..

....,.

BUSA SSYN

SET
SSYN

....,.

I 220NS L
I DELAY I

J DESELECT I
I (DEV SEll I

BUSA MSYN

J CLR sOEM I
I SSYN I
J

BUSA SSYN

MASS TRA

j )*

MASS OEM

OESELED
MASS TRA

RS041
RSO:~

* ALL EVENTS WITHIN BRACKET OCCUR
AT APPROXIMATELY SAME TIME.

11-3465

Figure 5-3

Reading Remote Register Interface

5-6

UN I BUS
(READ RSoB)

rRH70DATA -

-------.,

BUFFER (DB)
OBUF
<PA ,15:00>
PARITY
CHECKER
(PAT)

MXR
SEL

PARITY
GENERATOR

MoPC

I
I
I

I
I

~---r~

'--

MoPH

_______ J
o<15:00>IN
(WRITE RSoB)

U NI BUS
11-2910

Figure 5-4

Data Buffer Maintenance Operation

5-7

5.3.1.1 Writing the Data Buffer During Maintenance Operation - To understand maintenance operation of the data buffer, the following description
assumes that eight words are to be sequentially
loaded into the data buffer and none of the words
are to be read out.

WORD 3 - As previously stated, the right-hand
side of the data path is primed and the third word
loaded by the programmer is transferred from the
Unibus to IMX, AMX, RA, RC through the: MXR
to RE, and finally to RF. The description of how
this word sequences through the DB is similar to
that described for word 1. The difference is that
word 3 remains in RF since word 2 is in RG and
word 1 is in OBUF. All the pointers are now
primed to enable the left-hand side of the data
path.

J..f70RD 1 - The first word loaded in the DB by the
programmer is transferred from the Unibus to
IMX, AMX and then to the RA register. This action causes two events: the RA FULL flag is asst;~rted (which negates the IR Status in CS2) and the
RB ENA flip-flop is toggled to point to the RB register (which, if empty, will cause the IR Status to
again be asserted). Since the RC register is empty
(RC Full flag negated) and the RA register is full,
the data word in RA sequences to the RC register.
This causes the RC FULL flag to be asserted, the
RA FULL flag to be negated, and the RD ENA
flip-flop to toggle to the RD register. The data
word then sequences to the RE register through the
lVlXR since the MXR SEL was pointing to RC.
The RC FULL flag is cleared, the RE FULL flag
is asserted, and the MXR SEL switches to the RD
register. Now, the logic is set up to enable the lefthand side of the data path. The data word in RE is
transferred to RF, to RG, and then to OBUF,
which causes the OBUF FULL flag to be asserted.

WORD 4 - The fourth word is transferred from the
Unibus to IMX, BMX, RB, RD, and finally to RE.
The description as to how this word sequences
through the DB is similar to that described for data
word 2; however, the fourth data word remains in
RE, since word 3 is in RF, word 2 is in RG, and
word 1 is in OBUF. The pointers are now all
primed to enable the right··hand side of the data
path.

WORD 5 - The fifth word loaded by the programmer is transferred from the Unibus to IMX, AMX,
RA and then to the RC. The word can sequc;mce no
further because RE is already full with the fourth
word. The RB ENA and RD ENA flip-flops are
toggled to point to RB and RD, respectively; however, the MXR SEL is not affected since no word
was transferred through the mixer in this ca:ie. The
left-hand side of the data path is now primed to al~
cept the sixth data word.

U10RD 2 - The second word loaded into the DB
by the programmer is transferred from the Unibus
to IMX, BMX, and then to the RB register. The
RB FULL flag is asserted and the IR (Input
Ready) status is cleared. The RB ENA flip-flop is
toggled to point to RA again (which causes IR to
be asserted, since RA is empty). Since the RD register is empty (RD FULL flag negated) and the RB
register is full, data word 2 sequences to the RD
rt;~gister. This negates the RB FULL flag, asserts
the RD FULL flag and toggles the RD ENA flipflop to point to the RC register again. The word in
RD is then transferred to RE via the MX R SEL
logic, since the MXR SEL is pointing to RD. At
this point, the MXR SEL is changed to point to
RC again. Now, the right-hand of the data path is
primed to receive the next data word. Data word 2
in RE is transferred to RF, then to RG, and remains there since data word 1 is still in OBUF.

WO RD 6 - The sixth word loaded by the pr ogrammer is transferred from the Unibus to IMX, BMX,
RB and then to RD. Both the RB ENA and RD
ENA flip-flops are toggled to point to RA and RC,
respectively, in order to prime the right-hand side
of the data path to accept data word 7. The: MX R
SEL again remains unchanged, since no word is slequenced through the mixer. At this point, word 1 is
in OBUF, word 2 is in RG, word 3 is in RF, word
4 is in RE, word 5 is in RC and word 6 is in RD.
Since both RC and RD are full, the RD E1\'A flipflop can now be ignored, as is the case with the
MXR SEL.

5-8

WORD 7 - The seventh word loaded into the DB
is transferred from the Unibus to IMX, AMX, and
then to RA. The word remains in RA since word 5
is still in RC. The RB ENA flip-flop is toggled to
prime the left-hand side of the data path in order
to accept the eighth data word.

RF, RD to RE (since the MXR SEL is pointing to
RD), and RB to RD. This process causes the MXR
SEL to switch to RC, the RD ENA flip-flop to
point to RC and the RB ENA flip-flop to re main
unchanged (pointing to RA). At this point, word 3
is in OBUF, word 4 is in RG, word 5 is in RF,
word 6 is in RE, word 7 is in RC and word 8 is in
RD, with both RA and RB cleared. As successive
reads are performed, the words are sequenced out
of the DB in the same order in which they are
loaded into DB.

WORD 8 - The eighth word loaded is transferred
from the Unibus to IMX, BMX, and then to RB.
The eighth word remains in RB since all the remaining registers in the DB are filled. The RB ENA
flip-flop is toggled to point to RA. Since a word is
in RA (RA Full flag asserted), the IR (Input
Ready) status is negated.

5.3.1.3 Parity Generation/Checking During Maintenance Operation - Whenever a word is clocked into
RA and then to RC, the parity checker/generator
circuit (shown between RA and RC) generates odd
parity for each byte as the word is sequenced to
RC. For example, assume that the low byte contains all 1s; in this case, a parity bit is generated.
Assume that the high byte contains all Os; in this
case, a parity bit is also generated. A similar parity
generator / checker is located between RB and RD,
and as a word is transferred from RB to RD, odd
parity for each byte is created.

The programmer can verify that the DB is full by
examining the OR (Output Ready-bit 07 of CS2)
and IR (Input Ready-bit 06 of CS2) status bits. If
OR is asserted and IR is negated, it indicates that a
word is in OBUF and words are in RA and RB,
and due to the "bubble" technique of word sequencing, it is evident that the data buffer is full. If the
programmer attempts to write a ninth word into
the DB, he would overwrite the entire contents of
RA and would cause the RB ENA flip-flop to
toggle to point to RB.

As the data word sequences the RE, the parity bits
are X-ORed, resulting in one parity bit for the
word. This parity bit is transferred along with the
data word until the data word reaches OBUF.
There is a third parity generator/checker prior to
OBUF. This circuit checks the parity of the data
word to ensure that it is odd parity. If it is not, the
parity checker will cause the MDPE (Massbus Data
Parity Error) condition (bit 8 of CS2) to be asserted, indicating that a hardware failure occurred
between inputting the data word into the data buffer and the outputting of the data word from the
data buffer.

5.3.1.2 Reading the Data Buffer During Maintenance Operation - When the programmer does a
read from the DB register, the contents of OBUF is
supplied to the Unibus as data and the OBUF
FULL flag is cleared (OR status bit negated).
When this occurs, the contents of RG (word 7) is
sequenced to OBUF (OBUF FULL sets and OR if
asserted), RF sequences to RG, RE to RF, RC to
RE (since the MXR SEL was pointing to RC) and
RA to RC. This action causes the MXR SEL to
now point to RD, the RD ENA flip-flop to point
to RD and the RB EN A flip-flop to remain unchanged (pointing to RA). At this point, all the registers in the Data Buffer are filled, except for the
RA register, and the IR status indicator is asserted
in the CS2 register to indicate that space is available for additional data words.

Additional flexibility is provided the programmer
for maintenance checking of these parity circuits by
allowing bad (even) parity to be generated as words
are input or by allowing bad (even) parity to be
checked as the words are input. The IPCK bits control the parity generators between RA and RC and
between RB and RD. The PAT bit controls the parity checker between RG and OBUF.

When the second word is read from OBUF, the
OBUF FULL flag is cleared. The contents of RG
(word 6) is sequenced to OBUF, RF to RG, RE to

5-9

5.3.2 Write Commands (Data Buffer Operation)
In a write operation, data is transferred from memory to the RH70 Massbus controller, to the Massbus, and subsequently to the drive. The data buffer
in the RH70 is the device that accepts data to be
written on or read from the drive (Figure 5-5). In a
write operation, words are obtained from memory
in one of four ways: single word, double word,
words whose addresses are sequentially incremented
and words whose addresses are sequentially decreme:nted. When one of these operations is specified,
the RH70 data buffer is initialized for that type of
operation. When bus address bit 01 (BA 01) is a 0
(even word address), the right-hand data path (RA
and RC) is initialized; when this bit is a 1 (odd
word address), the left-hand data path (RB and
RD) is initialized.

For a data transfer, the program specifies the bus
address, bus address extension, word count, desired
address and the data transfer command code - a
writ,e command in this case. When the write command is loaded and the data buffer is full, or word
count overflow or an error condition occurs, the
RUN line is asserted on the Massbus and the drive
starts searching for the sector specified by the desired address. When the desired address is found,
the drive sends SCLK (Sync Clock) signals to the
RH70. The RH70 returns SCLK as a WCLK
(Write Clock) signal, along with the data word. On
the trailing edge of WCLK (SCLK plus the cable
delay), the drive strobes the data word into its data
buffer. This process continues until either word
count overflow is detected or until an error condition is asserted.

Bus Address Increment Inhibit - If this
bit (BA I-bit 3 of CS2) is asserted, the
memory addresses are not incremtmted
and the same data word is written in successive locations in the drive.

If the memory address of the data word
is on a single-word boundary, it is necessary to do a single-word transfer to arrive on a double-word boundary. VVhen
this occurs, normal double-word tlransfers can be accomplished. If memory addresses are being incremented, and the
least significant digit of the address is a
o or 4, the word is on a double-word
boundary. In this case, Bus Address bit
01 (BA 0 I) is a O. If the least signifiican t
digit of the address is a 2 or 6, the word
is on a single-word boundary and BA 01
is correspondingly a 1 (Figure 5-6).
The reverse case is true when memory
addresses are being decremented. In this
instance, a least significant digit of 2 or
6 specifies a double-word boundary (BA
01 equals a 1) and a least significant digit of 0 or 4 specifies a single-word
boundary (BA 01 equals a 0).

The following paragraphs describe a write data
transfer using incremented memory addresses followed by a write data transfer using decremtmted
memory addresses.
5.3.2.1 Incremented Memory Addresses - To understand the data buffer, assume that BA 01 is a 0,
which places the memory address on a double-word
boundary and initializes the right-hand data path
with the RB ENA pointer pointing to RA. It is further assumed that a double-word data transfer is to
be performed, followed by a single-word transfer
(i.e., a word count of 3).

The normal operation of the data buffer is to transfer double words as the memory addresses are sequentially incremented. The hardware also
implements double-word transfers as the memory
addresses are sequentially decremented. (This command code is not implemented in the RP04 Drives.)
I n certain conditions, it is necessary to do singleword transfers. These conditions are enumerated
below.
1.

The low word from memory is applied to RA via
AMX and the high word from memory is simultaneously applied to RB via BMX. During double-word
operation, the RB ENA pointer is overridden. This
can be thought of as adding two to the RB ENA
pointer which is actually a' flip-flop; adding two to
this device reverts it to its original state. Consequently, after this double-word transfer, the RB
ENA pointer will remain pointing to RA. In, addition, the RD ENA pointer is not employed during
a write command and can be ignored.

Word Count - If the word count indicates that the word to be transferred is
the last word, a single word transfer will
occur.

5-10

MASSBUS

------------.
PARITY
GENERATOR
MOPE

MOPO

~____- r______~MOPO

PARITY
CHECKER

I
I

_ _ _ _ ...1

11-2911

Figure 5-5

Write Command Data Path

5-11

BAI7

......... .

BEGINNING DBl BOUNDARY

---

BA01

"""0

NCREMENTING MEMORY ADDRESSES

BAI-' . . . . .

BEGINNING DBl BOUNDARY

BA00

BA02

-------I-

BA00

BA02

BA01

DECREMENTING MEMORV ADDRESSES
~1-2916

Figure 5-6

Data Word Boundaries

When the double word from memory is clocked
into RA and RB, the RA FULL and RB FULL
flags are asserted. Since RC and RD are empty, the
double word is clocked into RC and RD, respectively, clearing the RA and RB FULL flags and asserting the RC FULL and RD FULL flags. Each
data word consists of two bytes, plus a parity bit
for each byte. The byte parity is checked by a parity checker as the double word is transferred from
RA to RC and from RB to RD. If the parity is correct, the act of transferring a word from RA to RC
or a word from RB to RD will initiate a new memory cycle. If the parity is incorrect, the data parity
error is flagged and the memory transfer is frozen
in order to allow the programmer to determine the
address of the incorrect data word.

Since RC and RD are full, and the MXR SEL is
pointing to RC, the word in RC is transferred to
RE, clearing the RC FULL flag, and switching the
MXR SEL to RD. The word in RE sequences
through the data buffer and is followed by the
word in RD which is now transferred to RE. As a
result, the RD FULL flag is cleared and the l\1XR
SEL points once again to Re. The double word
has thus been converted into two single words .- the
low word followed by the high word. As the data
word is transferred from RG to OBUF, a parity bit
is generated if required (for odd parity). This ensures correct parity for the data as it is clocked
onto the Massbus.
For descriptive purposes, assume that the programmer had requested a three-word transfer and a
single word must follow behind the double word
which is now located in OBUF and RO. This word
from memory is applied to RA via AMX, since RB
ENA is pointing to RA and it is an even word.
Since RC is empty, the word is transferred to RC,
the RC FU LL flag is asserted, the RA FULL flag
is cleared, and the RB ENA pointer is switched to
RB. Since the MXR SEL is pointing to RC, the
word in RC is transferred to RE via the mixer. The
MXR SEL is switched to RD, the RC FULL flag
is cleared, and the single data word continues 1to sequence through the data buffer to RF. Two memory cycles have been performed to read three words
from memory. The first word is in OBUF, th4~ second in RG and the third in RF, ready to be transferred to the drive via the Massbus.

5.3.2.2 Decremented Memory Addresses - To understand the operation using decremented memory
addresses, assume that BA 01 is set to a 0, indicating that the data word is on a single·,word
boundary. In order to perform double-word memory cycles, the memory address must be on a
double-word boundary. To accomplish this, a single
word transfer is first performed; then the next memory address will be on a double word boundary.

NOTE
The data word mayor may not be written in the
drhe. This depends on whether the parity error is synchronized with the SCLK from a previous word, or
with the SCLK associated with the word in question.
In the former case, the data word will remain in the
data buffer; in the latter case, the word will be written in the drive.

NOTE
Decremented memory addresses' subscript for a writE~
a write command code of 678 which will fill thf! data.
buffer with words from memory, but will cause an ille·'
gal function error (ILF) in the disk drives.

5-12

Since BAO 1 is a 0, the right-hand data path (RA
and RC) is initialized. The single word from memory is clocked into RA via AMX. The RB ENA
pointer is switched to RB and the RA FULL flag is
asserted. Since RC is empty, the word in RA is
transferred to RC, the RA FULL flag is cleared,
and the RC FULL flag is asserted. As the word is
transferred from RA to RC, a parity check is performed. If parity is correct and if RA and RB are
empty, a new double-word memory cycle is initiated. If parity is incorrect, the memory transfer is
frozen as previously described.

For a data transfer, the program specifies the bus
address, bus address extension, word count, and the
data transfer command code - a read command in
this case. When the read command is loaded, the
RUN line is asserted on the Massbus. After the
tape is up to speed, the TM02 receives two tape
characters from the TUI6, assembles them into a
16-bit word, and sends it to the RH70, accompanied by an SCLK signal. On the trailing edge of
SCLK, the data is strobed into the RE register in
the data buffer. The data sequences from RE to
RF, to RG and the OBUF. Parity is checked as the
data is transferred from RG to OBUF.

Since the MXR SEL is pointing to RC and since
RE is empty, the word in RC is transferred to RE.
The RC FULL flag is cleared and the MXR SEL is
switched to RD. The word in RE continues to sequence through the data buffer and as the word is
transferred from RG to OBUF, a parity bit is generated, if required.

NOTE
Parity is calculated on the 16 data bits, the parity
bit, and the exclusive-OR of data bits 16 and 17 from
the Massbus. Bits 16 and 17 are written as Os during
write commands. If a parity error occurs, a Massbus
Data Parity Error (MDPE) is flagged.

If RA and RB are empty and no parity error is detected, the transfer of the word from RA to RC initiates a double-word memory cycle (BAOI isa 1
which now points to a double-word boundary). The
double word is clocked into RA and RB, then into
RC and RD, as previously described. Since the RB
EN A pointer does not switch for double words and
the RD ENA pointer is not used for write operations, they can be ignored. The MXR SEL is
pointing to RD and the high word in RD is transferred to RE, followed by the low word in RC. The
description of the words sequencing through the
data buffer is similar to that described for incremented memory addresses.

The data word in OBUF is transferred to RA (if
BAOI = 0) or is transferred to RB (if BAOI = 1).
If double-word operation is occurring, the next
data word is assembled with this one as a doubleword in RA and RB for transfer to RC and RD
and subsequently to memory. As previously described, during incremented memory operations, addresses whose least significant bit is a 0 or 4 are on
a double-word boundary while addresses whose
least significant bit is a 2 or 6 are on a single-word
boundary. The reverse holds true for decremented
memory addressing.
5.3.3.1 Incremented Memory Addresses During
Read Operation - To understand double-word transfers during a read operation, assume that BA 01 =
o so that the RB ENA pointer points to RA and
the RD ENA pointer points to RC. The word
reaching OBUF from the drive is clocked into the
RA register. At this point, the RA FULL flag is asserted and the RB ENA pointer switches to RB.
Since this is a double-word transfer, the data path
logic prevents the word in RA from being clocked
into RC until a word is loaded in RB. Now, a
double word is assembled in RA and RB and, since
RC and RD are empty, the double word is clocked
into RC and RD. The RC FULL and RD FULL
flags are asserted. The RA FULL and RB FULL
flags are negated, and the RD ENA pointer is incremented twice, which effectively leaves it pointing
to RA. The act of transferring the word from RA
and RB to RC and RD initiates a memory request.

The important distinction is that the low word follows the high word of a double-word block in decremented memory addresses and the MXR SEL
points to RD for a double-word boundary, which is
the reverse of what occurs in incremented memory
addressing.
5.3.3 Read Command (Data Buffer Operation)
In a read data transfer, data is transferred from the
drive to the Massbus, to the data buffer in the
RH70 Massbus Controller and subsequently to
memory. The data buffer in the RH70 is the device
that accepts data to be written on or read from the
drive (Figure 5-7). In a read operation, single words
are clocked into the data buffer, via the Massbus,
and are normally assembled into double words for
subsequent transfer to memory.

5-13

MEMORY

o <31: 16> a

r;H700m

0< 15:00>

B~>~ _ _ _ ...,

B~3.:!?PL _

BUFFER (DB)
MOPH

MOPH

RC
<PAHB,PALB,15:00>

I.-_ _ _~~--~MOPB

MOPC

MOPO

PARITY
GENERATOR

MOPC

I.--__:r------' MOPF

PARITY
CHECKER

I . - - - - - , r - - - - - - ' M 0 PF

' - - - - _ _ : r - - - - - M OPF

MOPE
1.-_--:1..._----' MOP F

______ J
SYNC 0<17:00>

a SYNC PA

~
"
'-----------,/
MASS BUS

11-2915

Figure 5-7

Read Command Data Path

5-14

empty and both RA and RB are full. The next data
word from the drive sequences through the data
buffer and is clocked into RA since the right-hand
data path is primed. Now, a double word is in RA
and RB, RC and RD are empty and the double
word is transferred into these locations. This clears
the RA FULL and RB FULL flags, asserts the RC
FULL and RD FULL flags, and initiates a memory request, causing the double word to be transferred to memory. Successive double words
continue to be transferred in this manner.

In single-word transfers, the RD ENA pointer ensures that the RC or RD register is clocked at the
proper time. After memory acknowledges the
request and completes the transfer, the RC FULL
and RD FULL flags are cleared. The process continues with data being clocked into RE, RF, RG,
OBUF, and subsequently to RA and RB, where it
is assembled into double-words for transfer to RC
and RD.
NOTE
The double-word operation will normally take place
if the word is on a double-word boundary, if it is not
the last word, or if the BAI (Bus Address Increment
Inhibit) bit is negated.
Parity generators attached to RA and RB examine
each data byte and generate an odd parity bit, if required. Each l6-bit word consists of 2 8-bit bytes
and an associated parity bit for each byte. Both
data and parity are sent to memory.
5.3.3.2 Decremented Memory Addresses During
Read Operation - To understand read data transfer
operations using decremented memory addresses, assume that BA 01 is a 0, which primes the righthand data path and indicates that the data word is
on a single-word boundary.
The drive places a data word on the Massbus with
a SCLK signal. On the trailing edge of SCLK, the
RH70 strobes the word into RE and it sequences
through RF, RG, OBUF and into RA, since the
right-hand data path is enabled. The RA FULL
flag is asserted and the RB ENA pointer is
switched to RD. The act of transferring the contents of RA to RC initiates a memory request and
the data word is then transferred to memory. At
the completion of the memory transfer, the RC
FULL flag is cleared.
The next data word is then on a double-word
boundary and is transferred to the RE register from
the drive via the Massbus. The word sequences
from RE to RF, RG, OBUF and then to RB, since
the left-hand data path is enabled. The RB FULL
flag is asserted and the RB ENA pointer is
switched to RA. However, since a double-word
transfer is specified, the contents of RB will not be
transferred to RD until both RC and RD are

5.3.4 Write Check Command (Data Buffer
Operation)
In the write-check operation, data previously written onto the drive is compared with the corresponding data from memory. Using this technique,
transmission errors from memory to the drive can
be detected.
The data words from the drive are transferred to
the RE register in the data buffer via the synchronous portion of the Massbus (Figure 5-8). The data
sequences from RE to RF, RG, and then to
OBUF. This portion of the data path is similar to
that described for the Read command (Figure 5-7).
Data from memory is normally input as double
words to AMX and BMX and then to RA and RB,
respectively. In the case of a single-word transfer,
the data word is clocked into RA (if BAOI = 0) or
into RB (if BAOI = 1). This portion of the data
path is similar to that described for a write operation (Figure 5-5).
NOTE
As previously described in the write operation, a
double word is clocked into RA and RB. This causes
the RA FULL and RB FULL flags to be asserted.
The RB ENA pointer is overridden for double-word
transfers. If both R C and RD are now empty, the
double word is clocked into RC and RD, the RC
FULL and RD FULL flags are asserted and the RA
FULL and RB FULL flags are cleared. A parity
check is performed on the data as it is clocked into
RC and RD. If a parity error is detected, a data parity error is flagged and the next memory request is inhibited. The act of clocking the double word into RC
and RD with no parity error initiates another memory request.

5-15

-------,

IRH70 DATABUFFER (DB)

~
~-=E
WCE

CLOCKC

MOPE

'---_ _.... MOPD
.&-.z---:II~ MOPB

RG
PA,1617,15:00

MDPF
RD
<15:00>

RC
<15:00>
MDPB

MDPC

READ
WRITE
PARITY
CHECKER

PARITY
CHECKER

RF
]
<PA,1617,15:00>
MDPF

RE
<PA.1617,15:00:;:J

MDP'E,
MOPF

MEM 0<31:16> a
MEM BYTE<3:2>
PAR (ODD DATA
WORD)

SYNC 0<17:00>
a SYNC PA

MEM 0 <15:00> a
MEM BYTE <1 :0>
PAR (EV EN DATA
WORD)

MEMORY

MASSBUS
~~---------------v

>
11-2914

Figure 5-8

Write-Check Command Data Path

5-16

To understand the write-check operation, assume
that a data word from the drive has been transferred to the RE register and has sequenced up to
OBUF; also assume that a double word from memory has sequenced into RC and RD. Also, assume
that the MXR SEL is pointing to RC. In this case,
the output of RC is applied to one input of the exclusive-OR (XOR) network and the output of
OBUF is applied to the other input of the XOR network. The RC output is the data word from memory and the OBUF output is the corresponding
word from memory which was previously written
onto the drive. These two words are compared in
the XOR network on a bit-by-bit basis. If any of
the bits do not compare, the XOR network yields a
1 which is used to set the WCE (Write-Check-Error) flip-flop when it is clocked. If the data words
do compare, the WCE flip-flop remains in the reset
state.
When the WCE flip-flop is clocked by the clock signal, the OBUF FULL flag is cleared (if no WCE
occurs) and the RC or RD flip-flop is cleared
(whichever was being selected by MXR SEL). In
this case, it is the RC flip-flop. This action releases
the word in RC and OBUF to allow subsequent
words to be write-checked. At the same time, the
MXR is switched to RD. The data word in RD is
now compared with the next data word from the
drive which has sequenced up through OBUF. The
MXR switches back to RC after this check and the
process continues.
For write-checking memory addresses which are
decremented, the procedure is similar, except that
the high data word is write-checked before the low
data word. IF BA01 is a 1, the left-hand data path
is primed, which means hat the high word in RD is
write-checked before the low word in RC. If BA01
is a 0, the right-hand (low word) data path is
primed and, in decrementing operations, this word
is on a single-word boundary.

the necessary priority arbitration logic to select the
appropriate controller when multiple requests are
initiated.
The backplane slots are designated A, B, C and D
for the various controllers which it can accommodate (refer to Figure 6-1). The logic for the controllers is identical; therefore, in order to make one
set of logic diagrams common to all controllers, certain signals are designated with an X in the signal
designation. Examples of this are CSTC CNTLX
REQ L, CDPJ SELADRS CNTLX Hand CDPJ
SELDATA CTRLX H. The X in these signal
names designates A, B, C or D, depending upon
which controller is specified. For example, the signal CSTC CNTLX REQ L for Controller A is
CSTC CNTLA REQ L. The following paragraphs
provide the interface description of write data transfers (data read from memory to be written on a
Massbus device) read data transfers (data read
from a Massbus device to be written into memory)
and write-check data transfers (data read from
memory to be compared with data from a Massbus
device in the RH70).
5.4.1 Write or Write-Check Operation (Read from
Memory)
Figure 5-9 is an interface diagram showing the relationships among the RH70jCache Interface and the
Cache/Memory Bus Interface. Figure 5-10 is a timing diagram showing the RH70jCache timing
relationships.
When the RH70 wishes to make a memory access,
it issues a CSTC CNTLX REQ signal. For example, if Controller A is making the request, CSTC
CNTLA REQ is issued. The Cache receives the
RH70 request along with requests from other devices and arbitrates them to determine which controller will access memory. The Cache then
transmits CDPJ SELADRS CNTLX H to the Controller which has been selected. If Controller A was
selected, Cache issues CDPJ SELADRS CNTLA
H.

5.4 RH70/CACHE INTERFACE
Data Transfers between the RH70 Massbus Controller and Cache take place over the RH70/Cache
Interface. The transfers are asynchronous in nature
and normally consist of two data words (32 bits,
plus four parity bits). The Cache interfaces with up
to four RH70 Massbus Controllers and contains

Upon receipt of this signal, the RH70 gates the address and control bits (CO, C1, and CX) to Cache.
The Cache latches the address and control bits for
subsequent transfer to Main Memory.

5-17

..
CACHE

ARBITRATE
REOUEST

RH7C1
MASSBUS
CONTRO·LLER

CSTC CNTLX REO L

CDPJ SEL ADRS

--,

CNTLX H

MAIN
i MEMORY

I
I
ADDRESS a CONTRQL

-------

ADDRESS a CONTROL
(22 BITS ADRS a C0, C',CX)
CDPJ

I
_J
GATE TIME
OUT TO APE
a NEM
FLIP FL.OPS

SEL DATA CTRLX H

NEGATES
REQ, a
INCREMENTS
WC, BA,a BAE

CCBE MBC REO ACKN

rI
1-- -

START
MAIN

ACK

---------

CCBE MBC

MAIN DATA

- - - ---

DATA (32 BIT a 4 PARITY BITS)

ADRS ACKN L

I
I

1-I
I

MAIN DATA READY

----

OATIGJ

BUFFER
COPE DATA ROY CNTLX H (DATA STROBE)

T
11-2903

NOTE:

This figure assumes no Address Parity Error and no
Non-Existent memory. both of which cause CCBD
MBC TIMEOUT. The RH70 monitors for these
conditions while CDPJ SEL DATA CNTLX His
asserted.

Figure 5-9

Memory Interface Write or Write- Check Operation
(Read from Memory)
properly. The assertion of MAIN ACK inhibits the
TIMEOUT signal (which denotes an error conclition when asserted). After receiving MAIN ACK
from memory, the Cache issues CCBE MBC
ADRS ACKN L to the RH70. In the RH70, ME:C
ADRS ACKN is made into a 50-ns pulse and
causes CSTC READ DONE L. The trailing edge of
READ DONE clears the memory cycle control
logic in the RH70.

The Cache then transmits CDPJ SELDATA
CTRLA H to the RH70. During write or writecheck operations, this signal is used to gate CCBD
MBC TIMEOUT from Cache. CCBD MBC TIMEOUT will occur only as a result of addressing a
nonexistent memory or as a result of an address
parity error on the Main Memory Bus. Either condition causes an error status to be indicated in the
RH70 (APE-bit 15 of CS3 and NEM-bit 11 of
CS2). The Cache then issues a CCBE MBC REQ
ACKN signal to the RH70 that it can now unassert
the request signal and the address and control bits.

If ADDR ACK is not received within 10 micro-

After the Cache issues CCBE MBC REQ ACKN,
it issues a START signal to Main Memory. This
causes the address and control bits, whic:h were
latched in Cache, to be transferred to Main Memory. A memory cycle is initiated and memory issues
MAIN ACK, indicating that memory is responding

seconds after START, Cache issues a CCDI) ME:C
TIMEOUT signal and the RH70 examines the Address Parity Error line. If TIMEOUT and Address
Parity Error are asserted, the CSTC APE Oilt-flop is
set. If TIMEO UT is asserted and therE is no address
parity error, the CSTC NEM (Non-Existenlt Memory) flip-flop is set.

NOTE

5-18

*SMC(1)H

- 150 NS

CSTC CNTLX REO
(COMPLEMENT OF REO (1) H)

*CIP(OH

CDPJ SEL ADRS CNTLX

WC,BA a BAE
INCREMENTED

CDPJ SEL DATA CN TLX

CCBE MBC REO ACKN

CDPK DATA ROY CNTLX

NOTE:

----------------------~~

SELDATA CNTLX is only used during Write or
Write-Check Operations to gate MBC TIMEOUT
signal to the RH70 for APE and NEM error
conditions.
11- 2921

*INTERNAL RH70 SIGNALS

Figure 5-10

Write or Write-Check Command Memory Bus Timing
(Read from Memory)

Main Memory then places two words on the data
lines of the Main Memory Bus. After a data deskew delay, memory issues MAIN DATA
READY. The data words are then routed from
Cache to the RH70, selected by the priority arbitration logic (controller A, in this example). The
CDPK DATA RDY CNTLA H signal is the
MAIN DATA READY signal from Cache to the
RH70 and causes the data from memory to be
transferred to the data buffer in the RH70. The
trailing edge of CDPK DATA RDY CNTLX
clears the memory cycle control logic in the RH70.
While Cache is transferring data to the RH70, it
may already be in the midst of servicing some other
request for memory access.

order to determine which device will obtain access
to memory. If this RH70 has been selected (assume
Controller A), the Cache returns a CDPJ SELAD RS CNTLA H signal.
Upon receipt of this signal, the RH70 gates the address and control bits (CO, C 1, and CX) to Cache.
The Cache latches the address and control bits for
subsequent transfer to Main Memory.
The Cache then transmits CD PJ SELDAT A
CNTLA H to the RH70 (Controller A). This signal
allows the RH70 to gate the data from its data buffer onto the RH70/Cache Interface. The data is
placed on the Main Memory Bus as long as MAIN
acc is un asserted (indicating that the data lines
are free).
NOTE
When a read from memory is being performed, the assertion of MAIN oee indicates that the data lines
are in use.

5.4.2 Read Operation (Write Into Memory)
Figure 5-11 is an interface diagram showing the
relationships among the RH70/Cache Interface and
the Cache/Memory Bus Interface. Figure 5-12 is a
timing diagram showing the RH70/Cache timing
relationships.
When the RH70 wishes to make a memory access,
it issues a CSTC CNTLX REQ L signal. The
Cache arbitrates this request with other requests in

The Cache now issues a CCBE MBC REQ ACKN
signal to the RH70 to notify the RH70 that it can
negate the request signal and the address and control bits.

5-19

CACHE

MAIN
MEMORY

IARBITRATE
REQUEST

CDPJ SEL ADRS CNTLX H

- --- --

DATA

NOTE:

..,
I

ADDRESS AND CONTROL
(22 BITS ADDRESS
CO,C1,CX)

CDPJ

MAIN START

MAIN ACK

SELDATA

-----

CTRLX H

a 4 PARITY BITS)

GATE DATI]
OUT
TO CACHE:

CCBE MBC REQ ACKN

I
NEGATES~
REQ, a

CCBE MBC ADRS ACKN

INCREMENTS
WC, BA,a 13AE

DATA (32 BITS

-----

RH70
MASSBUS
CONTROLLER

CNTLX REQ L

l
ADDRESS
CONTROL

CSTC

This figure assumes no Address Parity Error and no
Non-Existent memory, both of which cause CCBD
MBC TIMEOUT. The RH70 monitors for these
conditions while CDPJ SEL DATA CNTLX His
asserted.

Figure 5-11

*SMC

II·· 2904

Memory Interface - Read Operation
(W rite into Memory)

(1)H~

""150NS

CSTC CNTLX REQ - - - - (COMPLEMENT OF REQ (1) H)

*CIP (1) H

CDPJ SEL ADRS CNTLX

CDPJ SELDATA CNTLX

WC, BAa BAE
INCREMENTED

CCBE MBC REQ ACKN

CCBE MBC ADRS ACKN

* Internal RH70 siQnals.
11-2905

Figure 5-12

Read Command Memory Bus Timing
(W rite into Memory)

5-20

RH70/CACHE
INTERFACE FLOW
MASSBUS FLOW
CSTA

PROGRAM LOADS
RHWC, RHBA,
RHBAE, & DESIRED
ADDRESS

BCTA,AWR
BCTA,BCTB,

CSTC

MDPB
MDPA
RD +- RB
RD FULL +-1
RBFULL .... O

CSTB

MDPC
MDPA

AWRC
CSTE

CSTB

MBCBUS 'A' +- SA &
BA'E
MBCBUS C1, CO +- DATI
MBCBUS CX +- 0

CSTA
CSTD

AWRC

CSTE
CSTB

CSTC

CSTE

CSTB

CSTC
CSTB
CSTC

o
CSTC
CSTC

AWRD
AWRA
CSTB
CSTC

CSTB
MDPA

RA,RB-MEMORV
DATA
RA FULL +-1
AND/OR
RB FULL-1

CSTB

CACHE
FUNCTION

CSTC
MDPC,D
MDPA

YES
OBUF +- 0
MASS DA TA +- OBUF
OBUF FULL +- 0
NEGATE RUN

MDPD, F
MBSA, B, C
MDPD
CSTB

CSTC
CSTC
CSTB
CSTC
CSTB
CSTC

CSTB

'The CDPJ SE LDA TA CNTL signal
will be asserted for the active RH70
Controller (refer to logic diagram
CSTC).

'-- -

WAIT 100 NSEC

MDPA

CSTC

CSTB

",2927

Figure 5-13

Write Command Flow Diagram

After the Cache issues CCBE MBC REQ ACKN,
it issues a START signal to Main Memory. This signal causes the address, control bits and data on the
Main Memory Bus to be transferred to Main Memory. A memory cycle is then initiated and MAIN
ACK is generated by Main Memory and sent to
Cache. The memory cycle causes the data to be
written into core. Upon receipt of MAIN ACK
from memory, Cache issues CCBE MBC ADRS
ACKN to the RH70, notifying the RH70 that the
Main Memory operation has completed.
The receipt of MAIN ACK by Cache indicates that
Main Memory has properly responded, and inhibits
the generation of a Main Memory Bus timeout,
which would occur if an address parity error occurred or a non-existent memory was addressed. After receiving MAIN ACK from memory, the Cache
issues CCBE MBC ADRS ACKN L to the RH70.
In the RH70, MBC ADRS ACKN is made into a
50-ns pulse and causes CSTC READ DONE L.
The trailing edge of READ DONE clears the memory cycle control logic in the RH70.
NOTE
This figure assumes that no address parity error has
occurred and assumes that non-existent memory has
not been addressed. Both of these conditions cause
CCBD MBC TIMEOUT. The RH70 monitors for
these conditions while CDPJ SELDATA CNTLA H
is asserted.
5.5 WRITE COMMAND FLOW DIAGRAM
DESCRIPTION
The flow diagram for the write command is shown
in Figure 5-13. This paragraph describes the write
command, where data is transferred from memory
to the RH70 data buffer and is then written onto
the drive. The RH70 must be in the Ready State (indicating it is not doing a data transfer command).
The assertion of bit 07 (RDY) in the CS I register
puts the RH70 in the Ready state. The program
loads the word count, bus address, bus address extension registers and the frame count.
The write command is then loaded, which negates
the RDY bit (RH70 becomes busy) and causes the
data buffer and control to be initialized.
At this point, the flow divides into two major
flows: I) an RH70jCache Interface flow, which
transfers words from memory to the RH70 data
buffer, and 2) a Massbus flow, where words are
transferred from the RH70 data buffer to the drive.
Both flows operate asynchronously until both

DONE and EOS (End of Segment) are asserted (see
connector B at right of figure). DONE indicates termination of the RH70jCache Interface flow and
EOS indicates termination of the Massbus flow.
When both flows are terminated, RDY is asserted
to allow a new command to be loaded. Paragraph
5.5.1 describes the RH70jCache Interface flow; Paragraph 5.5.2 describes the Massbus flow.
5.5.1 RH70jCache Interface Flow
The RH70 requests that a memory cycle be asserted
CNTLX REQ to Cache. At the same time, the
RH70 sets a Cycle in Progress (CIP) flip-flop, internally indicating initiation of a memory cycle. The
CNTLX REQ signal increments a Start counter.
When four such requests have been made (indicating that the data buffer is probably full), the
RH70 asserts a START signal. If word count overflow occurs, or if an error condition is posted, the
ST AR T signal is asserted previous to this. This signal primes the Massbus cycle (Paragraph 5.5.2).
At the same time this is happening, the RH70 is
waiting for SELADRS CNTLX from Cache. This
signal allows the RH70 to gate its address and control information to Cache. Thus, the bus address,
bus address extension, and the CO, C I and CX control lines are gated onto the MBCBUS. CI and CO
indicate a read from memory and CX is specified
as O.
After gating the address and control onto the
MBCBUS, the RH70 waits for REQ ACKN from
Cache. This signal indicates that Cache has acknowledged the request and this controller will perform the next memory cycle. REQ ACKN clears
the CNTLX REQ signal, which informs Cache that
the REQ ACKN has been received by the RH70.
On the trailing edge of REQ ACKN, the bus address, bus address extension and word count are incremented since the address and control
information has been stored in Cache by this time.
The RH70 then waits for ADDR ACK, which, in a
write command, has no significance other than to
let the RH70 know that memory has responded to
Cache. If ADDR ACK is not received by the
Cache within 10 p,s, Cache sends a Timeout signal
to the RH70. If the Timeout signal is asserted and
the Address Parity Error interface line is also asserted, Address Parity Error (APE bit 15-CS3), (PE
bit 13-CS2) and Transfer Error (TRE bit- 14-CSl)
are set. If the Timeout signal is asserted and there
is no address parity error, Non-Existent Memory
(bit ll-CS2) and Transfer Error are both asserted.

In both cases just described, the Cycle in Progress
(CIP) flip-flop is cleared and the flow branches to
connector D where DONE is asserted. DONE is asserted upon termination of the RH70/Cache Interface flow. Termination of the Massbus flow is
indicated by End-of-Segment (EOS). When both
flows are completed, the RH70 returns to the
Ready state to accept another command.
Assume that there is no error condition and
ADDR ACK has been received within 10 p,s. The
RH70 now waits for a DATA RDY CNTLX signal
from Cache, indicating that memory has sent a
data word. Upon receipt of DATA RDY CNTLX
from Cache, the data is strobed into the RA
and/or RB registers in the data buffer, and the RA
FULL and/or RB FULL flip-flops are set. If a
double-word operation is specified, both the RA
and RB registers are loaded. If a single-word operation is specified, either RA or RB is loaded. A
100-ns delay is initiated to allow time for checking
the parity on the data as it is strobed from RA into
RC and/or from RB into RD.
If the word is an even word, the data is clocked
from RA into RC, RA FULL is cleared, and RC
FULL is set. If the word is odd, the data is clocked
from RB into RD, RB FULL is cleared, and RD
FULL is set. If a double-word operation is specified, the contents of RA and RB are both transferred. If a parity error is detected on the data as it
is being strobed into RC and/or RD, Data Parity
Error (DPE OW bit 14 or DPE EW bit 13 - CS3),
Parity Error (PE bit 13-CS2), and Transfer Error
(TRE bit 14-CS 1) are set. This causes the assertion
of DONE to terminate the RH70/Cache Interface
flow. With no error conditions present, the flow
loops back to the CNTLX REQ which initiates another memory cycle. This process continues until
the number of words specified by the Word Count
register have been transferred from memory to the
Data Buffer, or until an error condition occurs. In
either case, DONE is asserted and the flow
branches to connector B, where it waits for the
Massbus flow to complete. The completion of both
flows returns the RH70 to the RDY state.

5.5.2 Massbus Flow
When the command is loaded by the program and
the RH70 becomes busy, the Timeout for the assertion of OCC (Occupied) is initiated. The assertion
of OCC indicates that the drive has recognized the
command and is able to execute it. If the drive does

not respond to OCC within 650 p,s, a Missed Trans~er error (MXF) is asserted and RUN is negated (if

It was asserted). Also, the RH70 becomes Ready
and waits for a new command.
The RH70 awaits the assertion of START, which
occurs when the start counter has a count of four
word count overflow occurs, or Transfer Error is as~
serted. The RH70 then waits until a word in the
data buffer has sequenced to OBUF. At this time,
the RUN line is asserted on the Massbus and the
contents of OBUF is placed on the Massbus data
lines. The assertion of RUN signals the TM02 to
begin assembling characters and waiting on tape.
The TM02 accepts the first data word, converts it
into two tape characters and outputs it to the TU16
transport. The TM02 now issues a SCLK (Sync
Clock) signal, requesting another data word. The
RH70 reroutes this to the drive as WCLK (Write
Clock) with the next data word.
When SYNC CLK is negated, drive word count is
incremented. Drive word count keeps track of the
number of Massbus cycles. In addition to incrementing drive word count, the negation of
SYNC CLK creates a 50-ns pulse, designated
DRIVE CLK.
If drive word count overflow occurs, or an error
conditiQn is posted (TRE), the OBUF register is
cleared and Os are written onto the remainder of
the record. Also, RUN is negated and the OBUF
FULL flip-flop is cleared. If frame count in the
drive is set to less than twice the word count, frame
count overflow will occur (EXCP asserted) and
may cause a Frame Count Error (FCE). If frame
count is set to more than twice the word count,
word count will overflow first, negating the RUN
line. The RH70 now waits for End of Block (EBL)
from the drive. Since RUN is negated at this time,
End of Segment (EOS) is asserted, terminating the
Massbus flow. The flow branches to connector B to
wait for termination of the RH70/Cache Interface
flow. When both flows are complete, the RH70
goes to the Ready state to be able to accept another command.
If there is no error or drive word count overflow
the above described path is bypassed and the flo~
sequences down to the block designated "Does RG
RDY = I?" If RG RDY is a 0 (unasserted) indicating that a word is not available to be loaded
into OBUF, a Data Late (DLT bit 15 of CS2) error
is posted, Transfer Error is posted, the OBUF register is cleared, and the remainder of the segment is
zero-filled.

5-23

5.6.1 Massbus Flow
When the Read Command is loaded by the program and the RH70 becomes busy the timeout for
the assertion of OCC (occupied) is initiated from
the drive. The assertion of OCC indicates that the
drive has recognized a data transfer command and
is able to execute it. If ace is not received from
the drive within 650 J.lS a missed transfer error
(MXF bit 9-CS2) and Transfer Error (TlRE bit
14-CS1) are asserted, RUN is negated (if it was asserted) and the flow branches to connector A where
the RH70 returns to the Ready state.

If RG ROY is asserted, indicating that a word is
available in RG, the word in RG is transferred to
OBUF. The contents of OBUF is directly gated
onto the Massbus data lines. If both EXC (asserted
due to a drive error) and EBL are asserted, Transfer Error is set. At the time of EBL and EXC there
are no more SYNC CLK signals from the drive,
and the RH70 thus asserts EOS. The flow branches
to connector B to wait for termination of the
RH70/Cache Interface flow.
If there was no drive error, the flow loops back to
the point where the RH70 waits for the assertion of
SYNC CLK, since the data has been changed and
a new word is available for transfer. This process
continues until an error is asserted or drive word
count overflow occurs, both of which cause the operation to terminate.

The RH70 asserts the RUN line, indicating to the
drive that it is ready to accept data. When the tape
is up to speed, the TM02 receives two tape characters from the TU 16 transport, assembles them into
a 16-bit word and sends it to the RH70, accompanied by SCLK. On the negation of SCLK, the
RH70 increments the drive word count which keeps
track of the number of Massbus cycles. The: TM02
waits for the next two characters from the TUI6, assembles them into a I6~bit word and sends it into
the RH70, accompanied by SCLK. This proce:ss
continues until an error condition is posted, word
count overflow is detected, or the interrecord gap is
detected in the drive. On the trailing edge of
SCLK, the RE register is examined. If the register
is full (RE FULL= 1), Data Late (OLT bit I5-CSI)
and Transfer Error (TRE bit 14-CSI) conditions
are asserted, since there is no place to store the
data word from the Massbus. The R UN line is negated and at EBL time, EOS (End of Segment) is
asserted terminating the Massbus flow. The flow
branches to connector B to wait for termination of
the RH70/Cache Interface flow. When both flows
complete, the RH70 returns to the Ready state.

5.6 READ COMMAND FLOW DIAGRAM
DESCRIPTION
The flow diagram for the Read command is shown
in Figure 5-14. This paragraph describes the read
command, where data is read from the drive and
transferred to memory via the RH70 data buffer.
The RH70 must be in the Ready state (indicating
that it is not doing a data transfer command). The
assertion of bit 07 (ROY) in the CS 1 register puts
the RH70 in the Ready state. The program loads
the word count, bus address, bus address extension
rt:gisters and the frame count.
The read command is then loaded which negates
the ROY bit (RH70 becomes busy) and causes the
data buffer and control to be initialized.
At this point, the flow divides into two major
flows: 1) a Massbus flow, which causes data words
from the drive to be transferred to the RH70 data
buffer, and 2) an RH70/Cache Interface flow,
which transfers words from the RH70 data buffer
to memory. Both flows operate asynchronously until both DONE and EOS (End of Segment) are asserted (see connector B of right of flow diagram).
DONE indicates termination of the RH70/Cache
Interface flow and EOS indicates termination of the
Massbus flow. When both flows are terminated,
RDY is asserted to allow a new command to be
loaded. Paragraph 5.6.1 describes the Massbus
flow; While Paragraph 5.6.2 describes the
RH70/Cache Interface flow.

If the RE register was empty, the data from the
Massbus is strobed into it and the RE FULL flag
is asserted. Should an error condition be asserted,
or drive word count overflow occur at this time,
the RUN line is negated and the RH70 waits for
EBL, ignoring any data words prior to EBL. With
R UN negated at EBL time, EOS is asserted to terminate the Massbus flow. The flow branches to connector B, where it waits for the RH70/Cache
Interface flow to complete, so the RH70 may return to the Ready state.

5-24

RH70/CACHE
INTERFACE FLOW

MASSBUS FLOW
CSTA

CSTC
BeTA. AWR
BeTA. BeTB

CSTB

CSTC

CSTB

CSTC
CSTB

CSTc
CSTB

CSTB

MDPA

CSTB

RC'*'""" RA
RC FULL-1

RA FULL-O
AND/OR
RD-RB
RD FULL-l

CSTB

RBFULl-O

Figure 5-14

Read Command Flow Diagram

MOPe
MDPA

and bus address extension are incremented since by
this time, Cache has accepted and stored the ad··
dress and control information.

However, if no error occurs, or if drive word count
overflow does not occur, the EXC line is monitored. If EXC is asserted (denoting a drive error)
at EBL time, the transfer error bit is set after the
RH70 data buffer has been emptied. This allows
the RH70/Cache Interface flow to transfer all data
words currently in the data buffer to memory, prior
to asserting the error condition. The RH70 terminates the Massbus flow and the flow branches to
connector B to wait for completion of the
RH70/Cache Interface flow.

The RH70 now waits for the ADRS ACK signa]
from Cache. Cache has a timeout feature which
causes a Timeout signal to be asserted to the RH70
if ADRS ACK is not received within 10 J.LS. If th~:
Timeout is asserted (indicating no ADRS ACK).,
the Address Parity Error line is monitored. If then:
is an address parity error, Address Parity Error
(APE bit 15-CS3), Parity Error (PE bit 13-·CS2).,
and Transfer Error (TRE bit 14-CSl) are all as··
serted. If there is no address parity error, the time··
out is due to non-existent memory and NE~A (bilt
11 in CS2) is asserted along with Transfer Error. In
both cases, the CIP flip-flop is cleared and DONE
is asserted, terminating the RH70/Cache Interfact:
flow. When EOS occurs to terminate the Massbwi
flow, the RH70 returns to the Ready state.

If there was no drive error, the flow loops back to
the point where the RH70 waits for the assertion of
SYNC CLK and the next data word is loaded into
the data buffer. This process continues until an error is asserted, or until drive word count overflow
occurs, both of which cause the data transfer to
terminate.

5.6.2 RH70/Cache Interface Flow
The RH70/Cache Interface flow is not initiated until the data words from the drive have sequenced
through the data buffer and into RC and/or RD
via the Massbus flow. When a data word reaches
RC and/or RD, the RH70 sends a CNTLX REQ
signal to Cache, requesting a memory cycle. In addition, the RH70 sets the CIP flip-flop, indicating
that a cycle is in progress.

Assume that ADRS ACK was received within tht:
10 J.LS Timeout. The receipt of ADRS ACK, during
a Read command, indicates that Main Memory has
received the data and now the RC FULL and RD
FULL flip-flops can be cleared. After a 50-l1s de··
lay, the CIP flip-flop is cleared, indicating term i··
nation of the memory cycle. If there is an error
condition, or if word count overflow occurs,
DONE is asserted to terminate the RH70/Cache In··
terface flow. However, if there is no error and if
word count has not overflowed, the RH70 waits for
the RA or RB register to be loaded and the corre··
sponding RA FULL or RB FULL flag to be as··
serted. If a double-word operation is specified, both
RA and RB will be loaded and the RA FULL and
RB FULL flags are both asserted.

The RH70 now waits for Cache to acknowledge the
memory request by issuing SELADRS CNTLX.
This signal allows the RH70 to gate its address and
control information onto the address and control
lines of the MBCBUS, respectively. The bus address and bus address extension is gated onto the
address lines and a DATO operation is gated onto
the CO and C 1 control lines. If a double-word transfer has been specified, the CX line is asserted; if a
single-word operation is specified, the CX line is
unasserted.

The RH70 then waits 100 ns and transfers thle con··
tents of RA into RC and/or RB into RD and sets
and clears the appropriate flags. For exampl'e, if a
double-word transfer is specified, the contents of
RA is transferred into RC, the RA FULL jl1ag is
cleared and the RC FULL flag is set. Also, the con·
tents of RB is transferred into RD, the RB FULL
flag is cleared and the RD FULL flag is set. The
flow now loops back to the point where the RH70
makes another request to memory (CNTLX REQ).
This request will transfer the contents of RC
and/or RD into memory. This process continue!)
until there is an error, or until word count oVlerflow
occurs. Either condition causes the operation to terminate, as previously described.

At this point, the RH70 waits for a SELDATA
CNTLX signal from Cache. Upon receipt of this
signal, the RH70 gates the data from RC and/or
RD onto the MBCBUS data lines. After the addre:ss, control, and data have been transferred to
Cache, the RH70 waits for REQ ACKN, indicating
that Cache has acknowledged the memory request,
accepted the address and control, and is about to
start a Main Memory cycle. The assertion of REQ
ACKN causes the CNTLX REQ to drop. On the
negation of REQ ACKN, word count, bus address

5-26

RH70/CACHE
INTERFACE FLOW
MASSSUS FLOW
D

CSTA

START TIMEOUT
FOR oce ASSERTIONI

CSTS

BCTA,AWR
BCTA,BCTB

CSTC

MOPS
MDPA

+
CSTB

andfor
RO - RB
RO FULL-1

MOPC
MOPA

CSTB
CSTA

AWRe
WRITE CHECK LOOP

CSTB
CSTB

CSTB

MBCBUS 'A' .... BA &
BAE
MBCBUS C1, CO"" DATI
MBCBUS CX +- 0

CSTA
CSTO

MOPE
AWRC

CSTB
MDPE
CSTC
eSTC

AWRD
CSTB

CSTB
CSTC
YES

NO
MOPE
CSTS

CSTC
CSTC
CSTB

MOPO
MDPA

AWRO
AWRA

MDPE, F
MDPE

OBUF FULL +- 0
RC FULL +- 0
OR
RO FULL-

CSTB
eSTC
YES
,CSTB
CSTB

MOPA

CSTB

RA, RB-MEMORY
DATA
RA FULL .... 1
ANOfOR
RS FULL +-1

CACHE
FUNCTION

CSTC
MOPC, 0
MOPA

YES

CSTB

CSTC
CSTC
CSTS
CSTC
CSTB
CSTC

'--

Figure 5-15

M.OPA

CSTC

Write-Check Command Flow Diagram
11-2928

CHAPTER 6
DETAILED LOGIC DESCRIPTION

6.1 GENERAL
This chapter provides a detailed description of the
RH70 Massbus Controller logic diagrams. These diagrams should be used in conjunction with the flow
diagrams in Chapter 4 to provide both an overall
and detailed understanding of the RH70. The diagrams described in this chapter are tabulated· in
Table 6-1.

Detailed timing diagrams are also included in the
chapter and may be used in conjunction with the detailed logic descriptions to show timing relationships between signals. The timing diagrams
included are listed below:
Figure 6-1 Read or Write-Check Massbus
Timing Diagram
Figure 6-2

The M8150 module is designated MDP and contains the data buffer and the associated parity
checking and generating logic. The M8151 module
is designated CST and contains the control and
status logic. The M8152 module is designated
A WR and contains the address and word count register logic. The M8153 module is designated BCT
and contains the bus control logic.

Write Massbus Timing Diagram

Figure 6-3 Data Buffer Maintenance Operation Timing Diagram
Figure 6-4 Data Buffer Write Command
Timing Diagram
Figure 6-5 Data Buffer Read Command Timing Diagram
Figure 6-6 Data Buffer Write-Check Command Timing Diagram

6-1

Table 6-1
Listing of RH70 Logic Diagrams
Logic Print

Functions

BCTA
BCTB
BCTC
BCTD

AWRA
AWRB

Bus Address Reg (11:01)
Bus Address and Extension (21:12)
and Control Parity Out
BUSI MUX (BA and BAE Registers)
and Address Drivers
Word Count Register (07:00)
Word Count Register (15:08)
and WC OFLO
BUSI MUX (WC and Remote Registers) and MCPE

AWRC
AWRD
AWRE
AWRF
MDPA
MDPB
MDPC
MDPD
MDPE
MDPF
MDPH
MDP]

Memory Register Control
Even Word Memory Data Registers and Mixer
Odd Word Memory Data Registers
and Memory Parity Generator/Checkers
Data Registers Control
Write-Check Logic, Clock RE and Data Parity
Data Buffer Registers
IMX and Data Drivers
Data Path Block Diagram

CSTA
CSTB
CSTC
CSTD
CSTE

CS1, CS2, and CS3 Control and Status, Function Select
Errors, IE, Intr. Req. and Massbus Control
PE, NEM, and Memory Cycle Control
BUSI MUX (CS 1 and CS2 Registers) and Clear Logic
BUSI MUX (DB and CS3 Register) and START Logic

MBSA
MBSB
MBSC

Massbus Transceiver (Massbus Cable A)
Massbus Transceiver (Massbus Cable B)
Massbus Transceiver (Massbus Cable C)

6-2

---------------.1.1

r~---------- FIRST BLOCK READ
MASSBUS
DATA WORDS
IN BLOCK
CSTA GO CLR L
CSTA RD +WR CHK H
CSTBRUN H
MBSA SYNC CLK H

ST
1

INTER
BLOCK
GAP

1oe-!4------------- LAST BLOCK READ

·1

~______________________________________________________________________________________________=====1-I __________________________________________

:~~~~=

0_0_N_E_*_E_O_S_====4
____

DRwe OFLO

----\',~

MBSB EBL H
C STB EOS (1) H
CSTB DRIVE ClK H

________

.....Iry.\. ______-.....Iry,. . ___----InL..-__________________---\\~

~,\__--------II 1I........l\ \ -______

l\-oJ_ _ _ _ _ _

......I~~ REMAINING WORDS I N BLOCK IGNORED

AWRE DRWC OFLO (11 H
CSTB DIS SCLK (1) H
MOPE ClK RE L
MDPE RE FULL (1) H
MDPD CLR RE l
MOP E REG F U L L H
CSTB OLT (1) H

----~~7~~~rl-----~\~
'tJ

t...=J

~\~~----------~~\-I

r----------------,

~\~~_ _ _ _ _ _ _ _ _ _ _ _ _ __

11-2954

Figure 6-1

Read or Write-Check Massbus Timing Diagram

,.1------------

FIRST BLOCK WRITTEN

MASSBUS
DATA WORDS
IN BLOCK
CSTA GO CLR L
CSTA WRITE (1) H

-------------~.!

1-1--------------

NTH

LAST BLOCK WR ITTEN

---------------«-1
N TH

~~------------------------------------------------------------------------------------------------------------------------------------------------D~O~N~E~*~E707S-~---,

CSTB RUN H ___.......,~ DATA BUFFER FULL
MBSA SYNC CLK H

INTER
BLOCK
GAP

DRWC OFLO---=lL._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

~~~~~~"-------------Irty~~~~~~"--------

-------...-.'

Gr---

--------------~----------------------------------------------------------------------------------------------------------------------------------~

L.------------------------~\~\r------ny~~--------------------------------J
\
C STB CLR OBUF DATA L
MDPD eLK OBUF H
MDPD OBUF FULL (1) H
MDPD RG FULL (1) H
M DPD RG RDY (1) H
MDPD CLR RG L
CSTB DL T (1) H

-----1~:
~(L.---~
~------/~------~----------------------------------------------------~
1

L..-------.J

L.._______

I REMAINING WORDS IN BLOCK WRITTEN AS

0 S

~~"----~~--,~--:~~~~I~J----l"----~I~~I"----~I~---------------------------~:~------------------_____________________
'tJ
r------I
I

11-2955

Figure 6-2

Write Command Massbus Timing Diagram

~I·---- FIRST WORD
MDPA DB IN H

------..1.1

~I.----SECOND WORD - - -.......aoIl

-.J

BCTB REG STROBE H
MDPA IR H
M DPD RB EN (1) H
MOPA CLK RA H

-----------t'

------...,

MDPA RA FUll (I) H
MOPA ClK RB H
MDPA RB FULL (1) H
MDPD RD EN (1) H
MDPA CLK RC H

---------~\

MDPA ClR RA l
MDPA RC FUll (1)H _ _ _ _ _ _ _ _ _..r
MDPA ClK RO H
MOPA CLR RB l
MOPA RD FULL (1) H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
MOPO MXR SEL (1) H

----------------P

MOPE ClK RE l
MOPE RE FUll (1) H _ _ _ _ _ _ _ _ _ _ _ _~
MOPE ClR RC L
MOPE ClR RD l
MDPD RF FULL (1) H _ _ _ _ _ _ _ _~----------''"'"''
MDPD ClR RE L
MDPD ClK RG

H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..1)

MOPDRGFUlL (1) H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
MDPD CLR RF L
MDPDCLK OBUF H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
MOPDOBUF FULL[1)H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

MDPD CLR RG L
BCTA DB OUT H _________________________________________________________________________

BCTBDBOClK H _______________________________________________________________________________________________

NOTE:
A 2 WORD (MOV) TO RHOB FOLLOWED BY A 2 WORD
(MOV) FROM RHOS.

II - 2 956

Figure 6-3

Data Buffer Maintenance Operation Timing Diagram

I---

CCBE REO ACKN L
CSTA GO CLR L

·1...--- DOUBLE WORD MEMORY TRANSFER--I

SINGLE WORD MEMORY TRANSFER - - -..

CSTC CTRLX REO L - - - - - - ' r = : C S T O FIRST REO L

1 ..____...

AWRA BAOI (1) H
MDPA REO ClKH ____________________________________________~r__l~
AWRA DBL {1} H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

____________________________

__'t--- CSTC CTRlX REO

~r_l~

___________________________________________________________________________________________________

* CSTA BAI (O)

CDPJ DATA ROY CRTlX H =~~==~-------------4
MDPD RB ENABLE(1} H
MDPA ClK RB H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _""""l
MDPA RS FUll (1)H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----'
MDPA ClK RA H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~-------------~)
MDPA RA FUll (1}H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~------------~
MOPA ClK RDH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
MDPA RD FUll 11l H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.......
MDPA ClR RB l

~--~'------------------------~~---------------------~-------------------------------------------------------------------------------U

MDPA ClK RC H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~~------_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

MDPACLR RA l _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
MOPA RC FUll (1) H

~~LJ
J

MDPO MXR SEl (1) H
MDPD ClK REl
MDPD RE FULL (1) H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1-.......
MOPE ClR RC l
MOPE ClR RD l
MDPDRF FUll(1) H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

MOPO ClR RE l
MOPOCLKRG H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
M OPO RG FULL (1) H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

MOPO RG ROY (1}H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _+-~----'
MOPO CLR RF l
MOPO CLK OBUF H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

MDPDOBUF FUll(OH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _il~--r--------------------------------t-~_CMn~IRt~FLU~R»_;~~~~TE~*;(C~S~T~BlCo~RmIV~Ef(cil~K-=====~
MDPD ClR RG L
MBSA SYNC ClK H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _;' .
~
I~
.
CSTB DRIVE elK H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

NOTE:
3 WORD WRITING STARTING ON AN ODD WORD BOUNDARY (BAQ1 BIT -1)
A SINGLE WORD FOllOWED BY A DOUBLE WORD.

11-2957

Figure 6-4

Data Buffer \Vrite Command Timing Diagram

~I·---- FIRST DRIVE WORD

-----.""1. . ----

1,..-----

SECOND DRIVE WORD - - - - -...

THIRD DRIVE WORD-----~.I

Jr--------------------------------------------------------------------------------------------------------------------------------------------------------------------

CSTAGO ClR l -,~__________
CSTB DRIVEClK H

------------------------------------~

MOPE ClK RE
MOPE RE FUll (1) H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..1)
MOPE REG FULL H ____________________________________________-J
MDPD E62-PIN 8
MDPD RFFUlL(1)H __________________________________~
MDPD elK RE l
MDPD CLKRGH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
MDPD RG FU LL (1) H

---------------------------------------------------~~

MDPD ClR RF L
MDPD CLKOBUFH _____________________________________________

MDPD OBUF FUll (1)H
MDPD ClR RG l
MDPA ClKRAH ___________________________________________

MOPD RBEN(1)H ________________________________________________
MDPA RAFULLn)H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
MDPA CLK RB H

+-~~~

----------------------------------------------------~----~----------------~

MDPARB FULL(tIH _____________________________________________

~----~---

MDPACLROBUFH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

____________

AWRAEN DBLH-----------------------~---------------------------------------------------~--(AWRE WC HIB=I*AWRD WC LOB=IH)

-+________________

MDPDRO EN(llH ___________________________________________________~--------------------------------------------__________________________________

MDPA ClK RC H

--------------------------------------------------------------------------------~

MOPA CLK RA L--------------------------------------------------------------------------------~L__
MDPARCFULLnIH ______________________________________________________________________________________
MDPA CLKRDH ___________________________________________________________________________________________________________________

MOPA CLR RBL---------------------------------------------------------------------------------------t~
MOPA RDFULL(1IH ____________________________________________________________________________________________________________________

MDPA REQCLK H________________________________________________________________________________________________________

CSTC ADRS ACKN H

-------------------------------------------------------------------------------~-----------~~

-+____________________

AWRA BA01 (1JH _________________________________________________________________ _ _ _ _ _ _ _ _

~~~t-------~L-------------------~~

CSTC CTRlX REQ L
CCBE REQ ACKN L--------------------------------------------------------------------------------------------------------~
CSTC READ DONE l
NOTE:
3 WORD STARTING ON AN EVE N WORD
BOUNDARY (BAOI BIT =0 I
A DOUBLE WORD FOLLOWED BY A SINGLE WORD

WORD MEMORY _ _ _ _ _.....II..____ SINGLE WORD MEMORY _ _ _ _ _ 1
~'I--____ DOUBLETRANSFER
TRANSFER
+1
..

II-Z958

Figure 6-5

Data Buffer Read Command Timing Diagram

I--CSTC CTRlX REQ l
AWRE WC HIB= 1 H * AWRD WC lOB= 1 H
CCBE REQ ACKN l
AWRA EN DBl H
AWRA D8L Pl H

1·----

DOUBLE WORD MEMORY TRANSFER ----.·...

SINGLE WORD MEMORY TRANSFER

--1

)~~~~:~'~5----------I
\

______
___

-+{_________________________________________________________________________________________

~--------------------------------------------------------------------------------------

CDPJ DATA ROY CNTlX H
MDPD RB EN (1) H
MDPA ClK RB H
MDPA RB FUll (1) H
MDPA ClK RA H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~)
MDPA RA FUll (1) H
MDPD RD EN (1)H - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -__
MDPA ClK RD H
MOPA RD FUll (1) H

____________________~r:---------------------~~______________________________________________
U

MOPAClR RBl

MDPA ClK RC H ___________________________________ ~~------------------------------~~-----------------_______________________________________________________________
MOPA ClR RA

M0 PA RC FUll (I) H

--------------------------------~

MOPO MXR SEl (1) H
MOPE ClK MXR WD H
MOPE WCE H
MOPE INC MXR SEl H
MOPE ClR RD l
MOPE ClR RC l
MDPD ClR RG l
MDPD OBUF FUll (1) H
MDPD ClK OBUF H
MDPD ClR RF l
MDPD RG FUll (11 H
MDPD ClK RG H
MDPD CLR RE l
MO PO RF FULL (1) H
MOPE RE FULL (1)H
MOPE ClK RE l
CSTB DRIVE

CLK H
NOTE:
3 WORDS STARTING ON AN EVEN WORD BOUNDARY (BAOI BIT = 0)
A DOUBLE WORD FOllOWED BY A SINGLE WORD.
11-2959

Figure 6-6

Data Buffer Write-Check Command Timing Diagram

6.2 BCTA LOGIC DIAGRAM
This diagram contains the register selection logic
used by the program to select local RH70 registers
or remote registers in the associated drive. The register address is supplied to 15 Unibus receivers
(8640) via the Unibus. Bits 17 - 13 of the register
address are asserted designating the I/O area. Bits
12 - 6 are fed to a series of jumper Exclusive-OR
gates, whose outputs are collector-ORed to compare the device address against the Unibus address
that is received. This detects if the program is addressing this device. If any of the outputs of these
,;ates go low, it forces the output line low, as is the
case where the Unibus address does not match the
selected address of the RH70. The addresses to
which the RH70 responds can be relocated by modifying the jumpers. If a jumper is left in, it represents a logic 0; if it is cut, it represents a logic 1.
The register address bits are asserted low on the
Unibus. For example, address bit 12 is low at the
input to the 8640 Unibus receiver. The output of
this gate goes high. This is compared to the jumper
in place which is low. The output of the ExclusiveOR gate, after inversion, is low and this drives the
collector-ORed output line low to inhibit DEV
SEL. On the other hand, if the jumper is out (representing a 1), the Exclusive-OR gate compares two
high inputs, yielding a high output which enables
the DEV SEL signal for that bit.

are incremented by 2. The ROM also contains a
BCT A LOCAL REG H signal, which specifies a local (RH70) register when asserted and specifies a re
mote register when unasserted. The M6 and M7
outputs of the ROM are used to select additional
registers within the RH70.
Address bits 04 - 02, in addition to feeding the
ROM, are input to Comparator E046 where they
are compared with the register length field. The register length field is equal to the weighted value of
the jumpers removed, plus 2. If more than 16 registers are specified, address bit 05 is also applied to
the comparator. If the subsystem contains a total of
16 registers for example, (as in the TWU16 subsystem) the jumpers corresponding to a value of 8
(pins 7 and 10), 4 (pins 6 and 11) and 2 (pins 5 and
12) are cut. This yields 14 plus 2 or 16. The "plus
2" is to allow for the CS3 and BAE registers which
represent the last two registers in a subsystem.
The comparator has three outputs: A = B, A> Band
A <B; only one of these can be asserted at any
given time. Each is described below.
A = B - The A = B output is asserted if the CS3 or
BAE register is specified, which is defined as the
end of the field of registers for this subsystem (register length field = incoming address). This output,
in conjunction with the state of address bit 01
(BUS AOI L), is applied to BCD-to-Decimal Decoder EO lOin order to determine whether the CS3 or
BAE is addressed. If address bit 01 is asserted, the
CS3 register is specified and if this bit is negated,
the BAE register is specified. Note that BCTA Cl
Land BCTA DEV SEL L are also applied to the
decoder. With Cl L asserted, it indicates that a
write operation is to be performed; with Cl L unasserted, it indicates that a read operation is to be performed to the register. The DEV SEL signal
ensures that this is the device that has been selected. As an example of the operation, assume that
a subsystem has been cut for 14 registers (the 8 and
4 jumpers being removed from E041) and that the
program specifies a write into the BAE register.
The A = B output of the comparator is asserted and
address bit 01 will be negated. These signals are fed
to decoder EOI0, along with Cl L asserted, causing
the decoder to assert BCT A BAE IN L.

The BAE and CS3 registers "float" over the Massbus addresses; their addresses will vary based on
the number of subsystem registers. These registers
are logically defined as the last two registers in the
system. The following paragraphs describe how
these registers are addressed.
Bits 4 - 1 of the Unibus address are supplied to a
32-cell Read-Only Memory (ROM). These bits specify one of 16 registers in a subsystem. In subsystems with 16 registers or less, address bit 05
(BUS A05 L) is applied to the exclusive-OR gates
to decode the device address; otherwise, there
would be two fields where a register address might
be located (one field where bit 05 is a 1 and one
field where bit 05 is a 0). In subsystems with more
than 16 registers, bit 05 is applied to a ROM
(E050) where it is used with bits 04 - 01 to specify
one of 32 registers (Figure 6-7). F or example, if all
the inputs to the ROM are Is (corresponding to an
octal address of 37), the ROM maps this to a Massbus address of 33. This corresponds to a Unibus address of the base address (defined as the address of
the first register) plus 76, since Unibus addresses

A> B - The addresses of the CS3 and BAE registers
are variable, depending on the number of registers
employed in the subsystem. They will be assigned
some address between the base address +22 and

6-9

OCTAL
ADDRESS
00
01
02
03
~,
04
05
06
07
10
~~11
12
13
~,
14
~,
15
16
17
20
1-,
21
1-,
22
23
24
25
26
27
30
31
32
33
34
35
36
37

M7
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

M6
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

LOCAL
REG
M5
L
H
H
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

RSEL4
M4
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H

RSEL3
M3
L
L
L
L
L
L
L
L
L
L
L
-,
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H

RSEL2
M2
L
L
L
H
L
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L

RSEL1
M1
L
H
L
L
H
L
H
L
H
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

RSELO
MO
L
H
L
H
L
H
L
L
H
H
H
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

UNIBUS
ADDRESS

RHCS1
MASSBUS (00)
RHWC
RHBR
MASSBUS (05)
RHCS2
MASSBUS (01)
MASSBUS (02)
MASSBUS (04)
MASSBUS (07)
RHDB
MASSBUS (03)
MASSBUS (06)
MASSBUS (10)
MASSBUS (11)
MASSBUS (12)
MASSBUS (13)
MASSBUS (14)
MASSBUS (15)
MASSBUS (16)
MASSBUS (17)
MASSBUS (20)
MASSBUS (21)
MASSBUS (22)
MASSBUS (23)
MASSBUS (24)
MASSBUS (25)
MASSBUS (26)
MASSBUS (27)
MASSBUS (30)
MASSBUS (31)
MASSBUS (32)
MASSBUS (33)

BASE
ADDRESS
BASE +2
BASE +4
BASE +6
BASE +10
BASE +12
BASE +14
BASE +16
BASE +20
BASE +22
BASE +24
BASE +26
BASE +30
BASE +32
BASE +34
BASE +36
BASE +40
BASE +42
BASE +44
BASE +46
BASE +50
BASE +52
BASE +54
BASE +56
BASE +60
BASE +62
BASE +64
BASE +66
BASE +70
BASE +72
BASE +74
BASE +76

*Address bit 05 may be grounded if there are less than 16 registers in the subsystem.
**The BAE and CS3 registers are assigned Massbus addresses which may vary depending on the number of registers employed in a
particular subsystem. These registers are respectively located at addresses 772070 and 772072 for the RWS04 subsystem; 7'76750
and 776752 for the RWP04 subsystem, and 772474 and 772476 for the TWU16 subsystem.

Figure 6-7

Mapping MassbusjU nib us Addresses

6-10

the base address +76 (Figure 6-7). Note that this
area is in the Massbus register field and since these
registers are local, it is necessary to inhibit a Massbus control bus cycle when either of these registers
is specified.

signal is asserted. The decoder decodes the CS2,
DB, and BA registers and whether an input (from
processor to RH70) or output (from RH70 to processor) function is to occur.
6.2.3 Decoder Inputs
Inputs DO, Dl, and D2 to decoder E019 specify
one of 8 outputs from fO - f7 (outputs f8 and f9 are
not used). RSEL 00 and RSEL 01 are applied to inputs DO and Dl of the decoder, respectively, and
specify one of the three above mentioned registers.
BCTA Cl L is applied to input D2 of the decoder
and specifies an input or output function. When
BCTA Cl L is asserted, the D2 input to the decoder is low, enabling the register codes on outputs
fO, fI, f2, and f3. This indicates a DATO or DATOB where the data is transferred from the master
(processor) to the slave (RH70). The register signal
names which incorporate the word IN denote a
"write register" operation. When BCTA Cl L is
not asserted, the D2 input to the decoder is high,
enabling the register codes on outputs f4, f5, f6,
and n. This indicates a DATI or DATIP where the
data is transferred from the slave (RH70) to the
master (processor). The signal names designated the
word OUT denote a "read register" operation. Input D3 is asserted low if the BCT A LOCAL REG
H signal indicates that a local register is addressed.
DEV SEL H is asserted for both read register and
write register operations to select this device.

The A> B output of Comparator E046 is asserted
when the register length field is greater than the
Unibus address specified. This means that a valid
register has been addressed and causes the Comparator to assert BCTA REM ENA H. This signal
is ANDed with BCTA LOCAL REG H in NOR
gate E030-pin 1. If a local register has been designated, the gate is inhibited and BCTA REMOTE
REG H is negated, inhibiting the Massbus cycle. If
a remote register is designated, the gate is enabled
and BCT A REMOTE REG H is asserted to allow
the Massbus cycle to be initiated.
A<B - The BCTA ILLEGAL REG H output of
the Comparator is asserted when A<B (that is,
when the Unibus address specified is greater than
the register length field). This condition indicates
that an illegal register has been addressed and this
device is prevented from being selected by negating
the BCTA DEV SEL signal in AND gate E038-pin
12.
6.2.1 Local/Remote Register Selection
In addition to encoding the register address, the
ROM asserts the BCT A LOCAL REG H signal if
a local register is being accessed. The Massbus
handshaking sequence, necessary to access a register located in a drive, is inhibited in this case. If a
remote register is being addressed, the BCTA LOCAL REG H signal is not asserted (the Massbus
handshaking sequence is enabled) and the DEMAND signal is initiated.

6.2.4 Decoder Outputs
With input D3 low, outputs fO - f7 are enabled. If
input D3 is not asserted, the outputs from fO - f7
are inhibited and the decoder outputs are switched
to f8 and f9, which are not used. Since the RSEL
04 - RSEL 00 signals are not used for selecting a
drive register when the BCT A LOCAL REG H signal is asserted, it is possible to redefine the two bottom bits of the ROM (RSEL 00 and RSEL 01),
depending on whether the register specified is local
or remote. If a remote register is specified, RSEL
00 and RSEL 01 are used with RSEL 02, RSEL 03
and RSEL 04 to decode the register. If a local register is specified, RSEL 00 and RSEL 01 are fed to
decoder E019 to decode the CS2, DB, and BA
registers.

NOTE
The CS 1 register is shared by the RH70 Controller
and the associated drive. The LOCAL REG H signal
is not asserted to address this regist~r. If LOCAL
REG H is asserted, the Massbus handshaking sequence is inhibited. This would prevent access to the
portion of the CS 1 register located in the drive.
6.2.2 RSEL Signals
The BCTA RSEL 04 - RSEL 00 signals from the
output of the ROM are supplied to the Massbus,
which will be decoded in the drive to select a specific register. In addition, RSEL 00 and RSEL 01
are supplied to a 7442-BCD-to-decimal decoder
(EO 19) and are used when BCT A LOCAL REG H

Decoder E015 is similar to E019 with a few exceptions noted below.
Input D2 operates exactly the same as described for decoder E019.

6-11

6.2.8 Device Select (DEV SEL) Logic
The upper portion of BCTA shows the DEV SEL
LOGIC. Bits 17 - 5 of the Unibus address an~ used
to generate BCT A DEV SEL L when BCT A
MSYN H occurs. MSYN is delayed from the ad·,
dress 150 ns to allow the address to be properly de·,
coded by the jumper Exclusive-OR gates. The:
MSYN signal then keys the DEV SEL signal which
starts the register strobing sequence.

ROM outputs M6 and M7 are applied to DO
and 01 of decoder E015 and are used to decode the WC, CS 1, and AS registers.
Input 03 is enabled when DEV SEL L is asserted. BCTA LOCAL. REG H is not required since the M6 and M7 outputs of the
ROM are not dual-defined and may be used
anytime.

6.2.9 Control Out (CNTL OUT) Signal
The BCTA CNTL OUT L signal is used when read·,
ing a remote register in the drive. CNTL OUT Lis,
generated when the BCTA LOCAL REG H signal
is not asserted (remote mode), DEV SEL is asserted
and the BUSA Cl L signal is not asserted. This sig·,
nal switches the multiplexer on logic diagram
A WRF to gate the Massbus asynchronous data to
the Unibus data lines, making the register informa·,
tion available to the program.

6.2.5 Word or Byte Addressing
The logic network with the AO, CO, and Cl inputs
determines whether word or byte addressing is required and whether an input or output function is
occurring. The network implements the chart
shown below.
BUS Cl L

BUS CO L

H
L
L

L
H
L

DATI (read from device)
DATIP
DATO (write into device)
DATOB*
*If BUS A 00 L =H, low
byte is specified.
*If BUS A 00 L = L, high
byte is specified.

6.2.6 Control Lines
The Cl line from the Unibus generates the BCTA
CTOD H (direction of transfer) signal. When this
signal is asserted, the direction of data transfer is
from the RH70 to the drive register via the Massbus. When the signal is not asserted, the direction
of data transfer is from the drive register to the
RH70, and then to the Unibus to be made available to the program.

6.2.7 OD D BYTE L Signal
The BCT A ODD BYTE L signal is asserted when
performing a DATOB to the high byte and is used
to generate BCTB INH DEM H (Inhibit Demand).
INH DEM prevents the low (even) byte of the CSI
register (located in the drive) from changing when
thc~ program is doing a byte operation to the upper
(odd) byte. (This is necessary since the Massbus
does not implement byte operations and writeable
bits in the low byte of CS 1 are located in the
drive.)

6.3 LOGIC DIAGRAM BCTB
This logic diagram contains the register strobe logic
for loading local registers, and the SSYN and DEMAND logic. The logic for addressing a non·,existent device is also contained on this diagram.
6.3.1 Loading Local Registers
The leading edge of the BCTA DEV SEL :signal
triggers one-shot multivibrator E006. The external
components associated with this multivibrator are
chosen to provide an 85-ns delay. Consequently,
the one-shot produces a negative-going, 85-ns pulse
from the 0 output. At the end of 85 ns, the positive-going transition triggers a second one-shot
(E006) multivibrator. When this one-shot is triggered, it causes BCTB REG STR H to be asserted,
via gate E002-pin 8. This signal is used for clocking
local registers contained in the RH70.
6.3.2 Deskew of DEMAND Signal
The second one-shot multivibrator (E006) jU:it described provides a delay of 150 ns. The 0 output of
this one-shot produces a negative-going pulse" 150ns in duration. The positive-going transition of this
pulse (which occurs approximately 235 ns after
MSYN) clocks the SET OEM (Set Demand) flipflop set if the BCTB INH OEM H signal remains
unasserted. When asserted, INH DEM H inhibits a
Massbus cycle if:
1.

6-12

The register address is a local regist'er ad·
dress (BCTA LOCAL REG H).

The BCTA REM ENA L signal is not
asserted, which means that the CS3 or
BAE register is being selected (local
RH70 registers).

If the access is to the odd byte (BCTA
ODD BYTE L) in the CSI register
(BCT A CS 1 IN L). The CS 1 register is
shared by the RH70 and the drive, with
the odd byte being in the RH70 and the
even byte being in the drive. ODD
BYTE Land CS 1 IN L generate BCTB
INH DEM H to inhibit the Massbus
handshake sequence. This prevents altering the even (low) byte of the CS 1 register located in the drive, when the
program is doing a byte operation, to
the odd (high) byte in the RH70. This is
necessary because the Massbus cannot
differentiate byte from word operations.

6.3.4 Writing a Remote Register
The BCTB GATE CNTL H signal is used when
writing a remote register in the drive. BCTB GATE
CNTL H is generated when BCTA CTOD H
(write) and BCTA DEV SEL H are asserted and
gate the Unibus data signals to the Massbus control lines.
.
6.3.5 SSYN Logic
The SSYN logic determines when SSYN is sent to
the Unibus. Each of the various methods of setting
SSYN is described below.
1.

The STOP DEM L signal is asserted
when the processor tries to load a function code, specifying a data transfer operation, into the drive while the RH70 is
already busy executing a data transfer
function with that drive or some other
drive. For example, if unit 0 is doing a
read data transfer and the processor tries
to do a read or write data transfer in
unit 1, the CSTB STOP DEM L signal
prevents the function code from being
transferred to unit 1; otherwise, there
would be the OR condition of data from
unit 0 and unit 1 on the synchronous
Massbus and the program could not distinguish unit 0 data from unit 1 data.

With the SET DEM flip-flop set, the DEMAND
flip-flop is set, provided the TRA from the previous
Massbus cycle has completed. If the previous Massbus cycle has not completed, the BCTB TRA L signal prevents the DEMAND flip-flop from setting.
The DEMAND signal is sent to the drive via the
Massbus and requests a Massbus control bus cycle.

6.3.3 Register Strobe (REG STR)
A BCTB REG STR H signal is generated 85 ns after MSYN and is used for clocking the local
registers.

6-13

Setting SSYN-Writing Remote Register
(register electrically located in the drive)
- When the program writes a remote register via the RH70, the unit select bits,
the RSEL 04 - 00 signals, and the data
are gated onto the Massbus. The unit select bits select the specified unit and the
RSEL 04 - 00 signals select the appropriate register in that unit. If the RH70 is
writing into a remote register, BCTA
CTOD H is asserted. After a 235-ns deskew period, the RH70 asserts DEMAND on the Massbus. When the drive
sees DEMAND and recognizes its own
unit select code, it takes the data and issues MBSC TRA. The MBSC TRA signal is applied to one input of gate E001pin 13, provided the Attention Summary
register was not addressed. If the Attention Summary register was addressed,
BCTA AS IN Lor BCTA AS OUT L inhibits gate E001-pin 13, which inhibits
MBSC TRA from being applied to
EOl2-pin 12. The other two inputs to
EOl2-pin 12 are DEMAND (1) H (doing
a Massbus cycle) and BCTA CTOD H
(indicating a write data transfer) which,
when enabled, generate BCTB SET
SSYN L which is applied to the directset input of the SSYN flip-flop.
NOTE
The A ttention Summary register is a I-bit
per drive pseudo register. When this register is accessed, more than one drive may
respond. Therefore, the TRA signal cannot be used to indicate the availability of
data. In order to ensure that all drives
have their respective Attention Summary
bits loaded, a 1.5 microsecond delay is incorporated before the setting of SSYN.

at the 0 output clocks the SET NED (Set Non-Ex··
istent Drive) flip-flop set if the Attention Summary
register is not addressed (BCTB AS REG H).

Setting SSYN-Reading Remote Register
- If the RH70 is reading a remote register (accepting data from the drive), the
drive, after recognizing its unit select
code, the negation of direction of transfer (CTOD H) and DEMAND, issues
TRA and the data. TRA, BCTB DEMAND (1) Hand BCTA Cl L are applied to one-shot multivibrator E008.
BCTB DEMAND (1) H is asserted (denoting a Massbus cycle) and BCTA Cl
L is high (denoting a read from a device). With these conditions present, the
oneoshot is fired. The external components are selected to provide the 225ns pulse, designated BCTB DESK
D AT A L. This delay is designed to allow the data from the drive to propagate
to the RH70 and onto the Unibus before
SSYN is set. In other words, SSYN cannot be asserted on the Unibus until the
data from the drive has been transferred
to the Unibus and has stabilized. Consequently, when the one-shot fires, the 0
output goes low for 225 ns, forcing the
clock input to the SSYN flip-flop low
for this period. At the end of 225 ns, the
positive-going trailing edge of the pulse
sets the SSYN flip-flop (E017) which is
asserted on the Unibus as BUS SSYN L.

If the RH70 issues BCTB DEMAND (1) H and th(~
drive responds with MBSC TRA within 1:S J.j:S, th(:
one-shot is cleared. The MBSC TRA signal gener ..
ates BCTB DESK DATA L (reading remote regis··
ter) or BCTB SET SSYN L (writing rc~mot(~
register). Either of these signals direct-clears both
the 1.5 I-LS one-shot and the SET NED flip-flop via
gate E013-pin 6.
NOTE
If the drive does not respond within 1.5 microseconds,
the BCfB SET SSYN L (writing remote register)
and BCTB DESK DATA L (reading remote register)
signals are inhibited, preventing the 1.5 micro!iecond
one-shot and the SET NED flip-flop from beinu
cleared. This action causes the one-shot to time-out
and the SET NED flip-flop to set.
The BCTA DEV SEL H signal is applied to the di··
rect-clear input of the one-shot and SET NED flip ..
flops. If set, the flip-flops are cleared aftt:r tht:
Unibus cycle is completed and the addressed regis ..
ter has been deselected.
A second function of the one-shot is to provide a
1.5 I-LS waiting period to allow the Attention Sum..
mary register in the various drives to be properly
read from or written into. In this case, the one-sholt
times out because the TRA signal is inhibited by
BCTA AS IN L or by BCTA AS OUT L and all
the end of 1.5 I-LS, SSYN is set. BCTA AS IN L is
associated with writing the AS register and BCTEI
AS OUT L is associated with reading the AS regis··
ter. The SET NED flip-flop is not set, since it can
be set only when a register other than the Attc~ntion
Summary register has been addressed and no TRA
is received from the drive.

Setting SSYN-Access Local Registers SSYN is set during the access of local
registers as a result of BCTB REG STR
Hand BCTB INH DEM H being asserted. REG STR H is generated 85 ns
after MSYN and is used as a strobe input to the local register being accessed.
The signal INH D EM H indicates that
the Massbus cycle is inhibited and a 10
cal register is being accessed. At the trailing edge of the REG STR signal, SSYN
is set, indicating that data has been accepted or is present on the Unibus when
writing or reading a local register.

6.3.7 Data Buffer Out Clock (DB OCLK H)
The DB OCLK H signal is used to release data a1t
the output of the data buffer when the DB n:gistel'
is read by the program. The BCTA CO L signal i!l
used to inhibit the assertion of DB OCLK during
Unibus DATIP operations. This is necessary so
that a read-modify-write instruction does not falsely
remove data from the data buffer. DB register selec..
tion is used for maintenance purposes when veri··
fying the operation of the data buffer. DB OCLK
is asserted when the RH70 responds with SSYN to
the register operation (if not a DATIP) and is re ..
leased when the processor removes MSYN.

6.3.6 One-Shot Multhibrator (1.5 I-Ls)
The 1.5 I-LS one-shot multivibrator (EOO)8 serves two
purposes. First, it determines whether a non-existent drive has been accessed. The one-shot is fired
when DEMAND is asserted. If the drive does not
respond with MBSC TRA within 1.5 ,."s, the oneshot times out and the positive-going trailing edge

6-14

6.3.8 SSYN and TRA Light Emitting Diodes
(LEDs)
When the SSYN flip-flop in the RH70 or the TRA
signal on the Massbus is stuck in the asserted condition, it can hang up the Unibus. The SSYN and
TRA LEOs are provided for Field Service and
maintenance personnel so they may visually monitor either of these conditions. If the LED is illuminated in this case, it indicates that the associated
signal is stuck in the asserted state.

6.4 LOGIC DIAGRAM BCTC
This diagram contains the interrupt control logic to
prepare the Unibus to do an interrupt. The logic
contained herein is similar to that on the M7821 Interrupt Control module, which can be found in the
PDP-II Peripherals and Interfacing Handbook.

The SACK flip-flop is set 100 ns after
the BG IN H signal is issued. The set input to the SACK flip-flop is enabled because the GRANT flip-flop is reset and
the BG IN H signal is asserted. This
forces both inputs to gate E030-pin 10
low, which causes the output to go high
to set the SACK flip-flop. The setting of
the SACK flip-flop removes the BUS
BR5 L level from the Unibus by inhibiting gate E027-pin 1. BUS SACK L is
asserted on the Unibus.
When the processor receives SACK, it removes the BG IN H signal. At this
point, the RH70 waits for SSYN and
BBSY from the previous cycle on the
Unibus to become unasserted. With
BUS BBSY L and BUS SSYN L unasserted and the removal of BG IN H,
gate E021-pin 8 is enabled which clocks
the BBSY flip-flop set.

6.4.1 Interrupt Request
The interrupt control logic is initiated by CSTB
INTR REQ L which is asserted if: 1) the IE bit and
the Special Condition (SC) bit are set while the
RH70 is in the ROY state (not doing a data transfer command) or 2) the RH70 has completed a data
transfer and the ROY bit has gone from a 0 to a 1
or 3) the program writes Is into the IE and ROY
bit positions of the CSI register.

NOTE
When BBSY is set, it enables the set input to the
GRANT flip-flop through gates E02S-pin 3 and
E030-pin 13. The next BG IN H signal from the processor will set the G RANT flip-flop which will pass
the BG IN H signal to the next device on the bus.

This logic is implemented on logic diagram CSTB.
THE CSTB INTR REQ L signal is a request to interrupt the Central Processor and is applied to priority jumper plug E022 which causes a bus request
on a specific BR level. Normally for this device,
BUS BR5 L is asserted. The other BR outputs
from the plug are un asserted at this time. BUS BR5
L causes a bus request on the Unibus. When the
processor is ready to allow the RH70 to become
bus master, it returns BUS BG5 IN H which is
routed through the priority jumper plug and is output as BCTC BG IN H. This signal performs the
following functions:

In addition, BUS BBSY L and BUS INTR L are asserted on the Unibus along with the 7-bit vector address of the device (the vector address being 224 for
the TWU16 subsystem). The vector is jumper-selectable. If the jumper is left in, the corresponding bit
is a 1; if the jumper is cut, the corresponding bit is
a O.

It is applied to the clock input of the
GRANT flip-flop. However, the data input to GRANT is inhibited by the low
output of gate E030-pin 13. The output
of this gate is low since BBSY is not set
and INTR REQ is asserted which forces
the output of E025-pin 3 to go high.
This is applied to one input of E030-pin
13. Consider that the other input to
E030 is high since BUS NPR L is not asserted at this time.

6.4.2 Interrupt Done
When the processor has accepted the interrupt vector, it asserts BUS SSYN L which is used to generate BCTC INTR DONE via gate E025-pin 11.
INTR DONE is used to terminate the interrupt sequence by direct-clearing the IE and the INTR flipflops on diagram CSTB. This negates the CSTB
INTR REQ signal, which in turn, direct-clears the
BBSY flip-flop. The clearing of the BBSY flip-flop
removes the BUS BBSY, BUS INTR signals and
the vector address.

Note that the data input to BBSY is high because
SACK is set. The setting of BBSY clears the SACK
flip-flop via gate E025-pin 3, gate E030-pin 13, and
gate E021-pin 12.

6-15

DBL flip-flop also controls the single- or doubleword operation of the Data Buffer, the Word
Count register, and the Bus Address register.

6.4.3 BG IN, SACK and BBSY Light-Emitting
Diodes (LEDs)
The BCT module contains BG IN, SACK and
BBSY LED indicators, which are used by Field Service and maintenance personnel to determine if one
of these signals is hanging up the Unibus. F or example, if the BBSY flip-flop is stuck in the set
state, it will illuminate the associated LED. This
will allow Field Service personnel to quickly correct
the problem.

Note that the output of AND-OR gate E058-pin 8
is applied to the DBL flip-flop. When the output of
this gate is driven low, the DBL flip-flop is inhibited from setting, and the AWRA EN DBL H signal is negated. In this situation, single~-word
operation will take place. The conditions unde:r
which single-word operation will occur are d<;~
scribed below.

6.5 LOGIC DIAGRAM BCTD
The logic diagram contains the Unibus data transceivers for driving data on or receiving data from
the Unibus. When reading a register, data is driven
onto the Unibus from the internal bus (BUSI DOO
OUT L - D15 OUT L). This internal bus accepts
multiplexed data from the open-collector multiplexers in the RH70 register control logic. The data
is enabled by the assertion of BCTB SSYN (l) L.
When SSYN is negated, the data is removed from
the Unibus.

AWRE WC HIB=1 and AWRD WC LOB=1
When asserted, these signals designate that the
word count is all 1s, representing a last word condition, thereby inhibiting double-word operation.
AWRA CNT DWN (1) Hand AWRA BA 01 (0) H
When asserted, these signals indicate that tlh.e Bus
Address register is decrementing and is on a singleword boundary which is not a double-word by
definition.

When writing a register, the Unibus data is supplied to the RH70 as BCTD DOO IN H - 015 IN
H. These control lines feed all RH70 registers and
also feed the M assbus when writing remote
n~gisters.

6.6 LOGIC DIAGRAM AWRA
This logic diagram contains the DBL (Double) flipflop, the CNT DWN (Count-Down) flip-flop, bits 1
- 11 of the BA Bus Address register and the associated control logic. The Bus Address register increments by two for single-word operations or by
four for double-word operations. The register also
decrements by two for single-word reverse operations or by four for double-word reverse
operations.
6.6.1 DBL Flip-Flop
The DBL flip-flop determines whether the register
counts by two or by four, while the CNT DWN
flip-flop determines whether the register counts up
or counts down. The DBL flip-flop is clocked by
the CSTC CNTLX REQ L signal. The X designates Controller A, B, C or 0 since this logic print
is common to all controllers. The CNTLX REQ sig. nal is asserted when the REQ flip-flop on diagram
CSTC is set. This signal is sent to Cache and also
clocks the DBL flip-flop set or clear. This flip-flop
controls the C lines to Cache, designating whether
a single- or double-word transfer is to occur. The

NOTE
When memory addresses are incrementing and BAOI
is aI, the word is on a single-word boundary. Conversely, when memory addresses are decrementinlg,
and BA 01 is a 0, the word is on a single-word boundary (see Paragraph 5.3.2).
AWRA CNT DWN (0) Hand AWRA BA 01 (1) HI
When asserted, these signals indicate that the Bus
Address register is incrementing and is on a singleword boundary, which also prevents double-word
operation.
CSTA BAI (1) L
When asserted, this signal indicates that the bus address is inhibited from incrementing or decrementing and thus causes only single-word transfers Ito
occur.
MDPD LAST WORD Hand CSTB READ EXCP
H
When a read operation is taking place and a drive
error occurs, the RH70 will attempt to continue
transferring all remaining words in the data bufft!r .
If the last word in the buffer is part of a doubleword data block, the RH70 would normally wait
for a second word before accomplishing th,e memory transfer. In the first word of a double-word operation, the drive will not send the second word,

6-16

due to the error condition. However, the RH70 expects to receive this word; in this case, the last
word in the data buffer will assert MDPD LAST
WORD H, which will inhibit the A WRA EN DBL
H signal and force a single-word operation to
occur.

Note that the A WRA D BL (0) H signal (D BL flipflop reset) is applied to the J-K inputs, which
means that the flip-flop will toggle each time a
clock is applied (single-word operation). If the DBL
flip-flop is set, the J and K inputs are driven low
and the flip-flop is locked in its present state.

The DBL flip-flop is cleared by the AWRE CLR
signal or by loading a data transfer command into
the drive (GO CLR L).

The clock signal to the BAOI flip-flop is asserted if
the CD PJ SELAD RS CNTLX H signal and the
A WRD RACK H signals are asserted and the BAI
flip-flop is not set. CDPJ SELADRS CNTLX H is
a level from the Cache which indicates that this controller has been selected. The AWRD RACK H signal is a pulse which occurs during the RH70
memory cycle with Cache and indicates that the
Cache has acknowledged the request made by this
controller and has stored the bus address and control information. The CST A BAI (0) H is the bus
address increment inhibit signal. If this flip-flop is
reset, the bus address will increment or decrement
in its normal fashion. The BAOI flip-flop is loaded
or cleared by the direct-set or direct-clear input.
BCTB REG STR H, BCTA LO BYTE H, BCTA
BA IN L and the state of BCTD DOl IN H from
the Unibus determine whether the flip-flop is
loaded or cleared. The first three signals indicate
that the low byte of the Bus Address register is
being written during the time of the register strobe.
If DOl is asserted, the flip-flop is clocked set; if
DOl is negated, the flip-flop is clocked reset.

6.6.2 CNT DWN Flip-Flop
The CNT DWN flip-flop determines whether the
Bus Address register is to be incremented or decremented. This flip-flop is clocked by the trailing
edge of the CSTA GO CLR L signal which is asserted when a data transfer command has been
loaded. The function codes for the various commands are listed in Paragraph 3.5. Note that all reverse operations have function code bits FO and Fl
(corresponding to BCTD DOl IN Hand BCTD
D02 IN H, respectively) asserted. Since the GO bit
is also asserted, the least significant octal digit of
the command code is a 7. When these conditions
are met, the CNT DWN flip-flop is set and will
cause the Bus Address register to decrement. The
CNT DWN flip-flop is cleared by the CSTD CLR
H signal, which is asserted as a result of a program
clear, DC LO signal or INIT signal.
6.6.3 BAOI Flip-Flop
The BAO 1 flip-flop represents bus address bit 01.
For single-word operations, this flip-flop is toggled,
causing the address to be incremented or decremented by two. There is no countup or countdown logic associated with bit 01 due to the
following reasons. If the flip-flop is reset, incrementing or decrementing the address will set the
flip-flop. Conversely, if the flip-flop is set, incrementing or decrementing the address will reset
the flip-flop.
NOTE
For double-word operations, this flip-flop is not toggled; instead bus address bit 02, which is part of a
74193 4-bit binary counter chip, is employed. This bit
causes the bus address to increment or decrement by
four.

6.6.4 BA02, BA03 Bus Address Bits
There are three 74193 4-bit binary counter chips on
this diagram which yield bus address bits 02 - 11
(AWRA BA 02 H - AWRA BA 11 H).
Note that bus address bits 02 and 03 are on one
chip, bits 4 - 7 are on a second chip, and bits 8 11 are on a third chip. The bits are implemented
this way since the bus address is loaded as a byte
and this configuration minimized the logic required.
Note that bits 2 - 7 are loaded by AW RA LOAD
BALB L and bits 8 - 11 (and 12 - 15 on AWRB)
are loaded by AWRA LOAD BAHB L, corresponding to the low byte and high byte, respectively.
As previously stated, BA02 is incremented or decremented 1) during double-word operations, or 2)
when a carry propagates from BAOI. During
double-word operations, gates E053-pin 6 and
E053-pin 3 are enabled. If the bus address is being
incremented, A WRA CNT DWN (0) H is asserted
and enables gate E060-pin 6, which will cause

The BAO 1 flip-flop is a J -K type with J and K inputs tied together. In this configuration, when a
high input is applied to J and K and the clock input is clocked, the flip-flop will toggle. If a low input is applied to the J and K inputs and the clock
input is clocked, it has no effect on the flip-flop.

6-17

binary counter chip E043 to increment on the trailing edge of the AWRD RACK H signal. If the bus
address is being decremented, A WRA CNT DWN
(1) H is asserted and enables gate E060-pin 8,
which will cause binary counter chip E043 to decrement on the trailing edge of A WRD RACK H.
Note when decrementing or incrementing during
double-word transfers, that the BAOI bit is inhibited from changing state due to the negation of the
AWRA DBL (0) H signal.
In the case where a carry is propagated from bit
BAOI, assume that the operation is a single-word
transfer and the address is being incremented. In
this case, BAOI is a I which enables gate E053-pin
3. This in turn enables gate E060-pin 6, causing
binary counter chip E043 to increment on the trailing edge of A WRD RACK H. In addition, the
BAOI flip-flop is toggled, since the DBL input is no
longer holding it disabled. Consequently, in this
case, BA02 incremented while BAOI went from a I
to a O. For decrementing, a similar analysis is followed with BAOI on a O. Gates E053-pin 6 and
E060··pin 8 are implemented. On the trailing edge
of AWRD RACK H, BA02 decrements and BA01
changes from a 0 to a 1.
Since the upper two bits of binary counter E043 are
not used, the carry and borrow condition for bus
address bits 02 and 03 must be calculated. A carry
condition is generated if BAO I, BA02 and BA03 are
asserted, or if BA02 and BA03 are asserted and a
double-word operation is to occur (see gate E049pin 6). The output of this gate enables NAND gate
E054·-pin 8 to increment BA04 during incrementing
[AWRA CNT DWN (0) H], if AWRA COUNT
BA H is asserted. COUNT BA H is asserted if this
RH70 has been selected, Cache has issued the REQ
ACKN signal to the RH70, and the Bus Address Increment Inhibit flip-flop is reset (see AND gate
E059-pin 6).
When bus addresses are decremented a borrow condition must be calculated. A borrow is generated if
BAOI, BA02 and BA03 are all negated or when
BA02 and BA03 are negated and a double-word operation is specified. This is implemented in NOR
gate E055-pin 8. The output of this gate enables
NAND gate E054-pin 6. The other inputs to this
gate are enabled when decrementing addresses
[AWRA CNT DWN (1) H] if AWRA COUNT BA
H is asserted.

6.6.5 BA04 - BAlI Bus Address Bits
Binary counter E047, which is associated with bus
address bits 04 - 07, generates an internal borrow
or carry to the next counter chip E046 as all bit positions of E047 are used. The count up input to
E046 is incremented by a carry while the count
down input is decremented by a borrow. Note that
AWRA LOAD BALB L (Load Bus Address-Low
Byte) is used to load the low byte of the bus address (bit 01 - 07). Bus address bits 08 - 11 are part
of the upper byte and is loaded by A WRA LOAD
BAHB L (Load Bus Address-High Byte).
6.7 LOGIC DIAGRAM AWRB
This diagram contains the upper part (bits 12 - 15)
of the high byte of the Bus Address register, contains the Bus Address Extension register (bits 16 21), and the control parity logic.
6.7.1 BAI2 - BAIS Bus Address Bits
Bus address bits 08 - 11 are shown on logic diagram A WRA; bus address bits 12 - 15 are shown
on logic diagram AWRB. Bits 12 - 15 represent the
upper bits of the high byte of the bus address register and are loaded by A WRA LOAD BAHB L.
The carry and borrow outputs of binary counter
E047 on sheet A WRA, which process bus address
bits BA07 - BAll, are applied to the Countup
(CUP) and Countdown (CDN) inputs of binary
counter E041 (sheet AWRB), which process bus address bits BAl2 - BA16.
6.7.2 Bus Address Extension Register (Bits BAII~ BA21)
The borrow and carry outputs of binary counter
E041 are applied to the CDN and CUP inputs to
binary counter E035, which processes bus address
extension bits 16 - 19. The borrow and carry outputs of E035 are applied to the CDN and CUP inputs of binary counter E036, which processes bus
address bits BA20 and BA21. Consequently, the
borrow or carry propagates through the Bus Address register to bits 20 and 21 of the Bus Address
Extension register.

If the program is writing bits A 16 and A 17, it <:an
write these bits in two registers: bits 8 and 9 of the
CS 1 Control and Status 1 register (high byte) and
in bits 00 and 01 of the BAE (Bus Address Ext'ension) register (low byte). Note that there is only one
load input into binary counter E036. Consequently,
AND-OR gate E045-pin 8 is provided to allow loading from the CSI register or from the BAE register.

6-18

If A16 and A17 are written via the BAE register,
the upper AND gate is enabled (AWRB BAE IN
H, BCTA La BYTE H, and BCTB REG STR H).
BCTD DOO - D03 in H are loaded via multiplexer
E040 into A 16 and A 17 positions of binary counter
E036. If A16 and A17 are written via the CSI register, the lower AND gate is enabled (BCTB REG
STR H, BCTA HI BYTE H, BCTA CSI IN Land
CSTA RDY H).

If BCTA BA OUT L is asserted, the AO - A3 inputs of each multiplexer are supplied at the output
which feed the bus address onto BUSI. If BeTA
BAE OUT L is asserted, the BO - B3 inputs of eachmultiplexer are supplied to the output.

This gates the bus address extension bits onto
BUSI. Since the bus address extension is only six
bits, the remaining ten inputs to the B side of the
multiplexer are grounded. The BUSI internal bus,
in turn, is used to provide the appropriate register
contents to the Unibus data lines when the program reads a register.

Since binary counter E035 is a four-bit chip and the
program is writing bits AI6 and A17, AWRB A18
Hand AWRB A19 H are fed back to the input
multiplexer (E040) to preserve their contents.
6.7.3 Asynchronous Massbus Parity (CPA OUT)
The two 74180 chips shown on sheet A WRB are
employed for parity generation when writing into a
register in the drive. The 16 data inputs to the chips
are from the Unibus data lines. Note that odd parity is normally selected. (CSTA PAT H is normally
negated.) Parity on the Massbus is odd.

6.8.2 Address Drivers
There are 21 address drivers for the Bus Address
and Bus Address Extension Registers that are used
to drive address information onto the MBCBUS
which serves as the RH70/Cache Interface. The
MBCBUS lines are common to all RH70 Controllers. The address is gated onto the MBCBUS by
the CDPJ SEL ADRS CNTLX signal for this
controller.

Assume that the data inputs contain an even number of Is. This is summed with the ODD input to
assert the EODD output which generates PA OUT
H. This is the parity bit generation and is supplied
to the Massbus driver for transfer to the drive. If
the data inputs contain an odd number of I s, the
PA OUT H signal is not asserted and no parity bit
is generated. When reading from a drive register, a
different set of data lines is used and this necessitates two additional 74180 chips to check parity.
(See sheet AWRF.)

NOTE
This diagram is common to all four RH70 Controllers. The X in CNTLX actually refers to the Controller (Controller A, B, C or D) that has been
selected by the Cache.

6.8 LOGIC DIAGRAM AWRC
This logic diagram contains the BUSI internal bus
mUltiplexers for the Bus Address and Bus Address
Extension registers. The diagram also shows the address drivers which drive bus address and bus address extension information from the RH70 to the
MBCBUS, which is the RH70/Cache Interface.

6.8.3 Control Signals CX and Cl
There are two drivers for driving the CX and C 1
signals onto the MBCBUS. When asserted, the ex
signals, specify a double-word operation and when
unasserted, specify a single-word operation. CX is
not used during a write operation or write-check operation, since double words are normally transferred from memory to the RH70. If a single-word
operation has been specified, the memory will still
transfer a double word; however, only the appropriate word is clocked into the RH70; the other one is
disregarded. During a read operation, the CX line
is used to specify writing a double (CX asserted) or
single word (CX negated) into memory.

6.8.1 BA and BAE Multiplexers
The four open-collector multiplexers (E020, E024,
E026 and E030) gate the bus address and the bus
address extension bits onto the BUSI internal bus.

NOTE
The CO signal (if it was implemented) defines read
pause or write byte. However, since the subsystem
only reads or writes words, this bit is not used.

The PAT H signal can be asserted by the program
(bit 4 in CS2) to generate even parity on the Massbus. This maintenance feature allows verification of
the parity logic in the drive.

6-19

The chart below shows the various control signal
combinations for the data transfer operations.
OPERATION

MBCBUS CX L

MBCBUS Cl L

W rite, write-check
Read (double word)
Read (single word)

un asserted
asserted
unasserted

un asserted
asserted
asserted

6.9 LOGIC DIAGRAM AWRD
This diagram contains the low bytes of the Drive
Word Count register (DRWC) and the Word
Count register (WC).
6.9.1 Drive Word Count Register
The Drive Word Count register is loaded in parallel
with the Word Count register. CSTB SYNC CLK
B H is applied to the Countup (CUP) input of the
register and causes the register to be clocked on the
trailing edge of the SYNC CLK signal. This register is incremented by one, since single words are
gated on/off the Massbus.
Bits 00 - 03 of the Drive Word Count register are
located on E037; bits 04 - 07 are located on E032.
The Carry (CRY) output from E037 is fed to the
Countup (CUP) input to E032. The CRY output of
E032, in turn, is fed to the high byte of the Drive
Word Count register (see logic diagram A WRE), in
order to propagate the carry through the register.
The: Drive Word Count register is loaded by ANDing BCT A WC IN L, BCT A LO BYTE Hand
BCTB REG STR H, which is similar to the loading
of the other RH70 registers.
6.9.2 Word Count Register
The Word Count register for the low byte is configured differently than the Drive Word Count register. Bit 00 of this register is a single J-K flip-flop
with J and K inputs connected together. Consequently, a clock signal with asserted J-K inputs
cause the flip-flop to toggle, while a clock signal
with negated J-K inputs has no effect. For doubleword operation, WCOO is prevented from toggling
due to A WRA DBL (0) H being unasserted. Instead, WCOI is toggled for each double word. During single-word operation, WCOO is toggled with
each clock input applied to the register. Only bits
01 .- 03 of the Word Count register are located on

E022 since WCOO is implemented as a single flipflop. This leaves one unused input on this counter
since it is a four-input device. It is necessary therefore to calculate the carry from this stage. Bits 04 07 are located on EOn. Note that the output of
WCOO or DBL (0) H is applied to E042-pin 11
which then enables a carry condition to E042-pin 8,
E028-pin 8, and EOO5-pin 6. A carry condition
from bits 01 - 03 is applied to E028-pin 8 and
E005-pin 6 via gate E005-pin 8. In effect, this configuration ANDs the bits of the low byte to determine if a carry is propagated to the next stage. For
example, if bits 00 - 03 are all asserted, or if bits 01
- 03 are asserted and double-word operation is specified, AND gate E028-pin 8 is qualified when the
register is clocked, causing bit 04 in E017 to increment. Similarly, if bits 00 - 07 are all asserted,
or bits 01 - 07 are asserted and double-word operation is specified, AND gate E005-pin 6 is ass(~rted
yielding A WRD WC LB CRY H. This signal iii applied to the high byte of the Word Count register
to increment the EO 11 low order stage in that register (see logic diagram A WRE).
NOTE
The MAX output on pin 12 in E017 is asserted if the
counter is incremented to all Is. The MIN output is
not utilized as the word counter is only allowed to increment and not to decrement.
The Word Count register is clocked in the Harne
manner as the Drive Word Count register. Vv'hen
the bus address is incremented, the word count :lS incremented. This occurs as a result of the CCBE
REQ ACKN L signal from the Cache and the
CDPJ SEL ADRS CNTLX H signal which specifies this controller. These signals are ANDed in
AND gate E005-pin 12 to yield AWRD REQ
ACKN H. Note that the entire Word Count register is clocked by A WRD REQ ACKN H (see logic
diagram AWRE).

6-20

The Word Count Overflow flip-flop is cleared by
CST A CLR + GO CLR L, which is asserted by
DC LO, INIT, PROGRAM CLEAR or by initializing the RH70 during a data transfer
command.

6.9.3 Detection of Maximum Word Count
When bits 00 - 07 of the Word Count register are
all Is, A WRD we LOB 1 H is asserted at the output of E003-pin 10. This signal is ANDed with
A WRE WC HIB 1 H on logic diagram A W RE to
detect an all Is condition in the Word Count register. This all Is condition signifies that the last word
is being transferred and inhibits the data input to
the DBL flip-flop (see logic diagram AWRA).

6.11 LOGIC DIAGRAM AWRF
This logic diagram contains the BUSI open-collector multiplexers, the parity checkers, and the Massbus Control Parity Error (MCPE) flip-flop.

6.10 LOGIC DIAGRAM AWRE
This diagram contains the high bytes of the Drive
Word Count and the Word Count registers. They
are incremented similar to the drive word count
low byte and word count low byte, described on
logic diagram A WRD. Since all chips on this diagram are four-input chips, with all inputs being
used, the carry from one chip is rippled to the
Count-up (CUP) input of the next chip.

6.11.1 BUS I Multiplexers
The BUSI open-collector multiplexers (E007, EOO8,
E013 and EOI4) gate the word count or the contents of a remote register onto BUSI. BUSI is the
internal bus which is driven onto the Unibus data
lines. When reading the Word Count register, the
multiplexer gates the word count (A WRD WC
OO-WC 07 and A WRE WC08-WCI5) onto the
Unibus data lines. When reading a Remote Register, the multiplexer gates the Massbus C lines (COO
IN H - CI5 H) onto the Unibus data lines. The
word count is enabled onto BUSI via BCTA WC
OUT L and the Massbus C lines are enabled onto
BUSI via BCT A CNTL OUT L.

The high bytes of the Drive Word Count and Word
Count registers are loaded similarly to the low
bytes previously described. Note, however, that
BCT A HI BYTE H is used instead of BCT A LO
BYTE H.

6.11.2 Parity Checker, MCPE Flip-Flop
The parity checkers monitor the CPA parity bit
and the 16 Massbus control bus data lines when a
remote register is being read. If the parity is odd,
the EVEN output is forced low and inhibits the
Massbus Control Parity Error flip-flop from setting. However, if a parity error occurs (even parity), the EVEN output is asserted and enables the
set input to the MCPE flip-flop. When the flip-flop
is clocked by the negation of BCTA CNTL OUT L
signal (asserted during a remote register read operation), the MCPE flip-flop is set. This condition is
reflected in bit 13 of the CS I register. When the
MCPE flip-flop is set, the reset output latches the
flip-flop set via NAND gate EOI0-pin 6.

6.10.1 Drive Word Count Overflow
For Drive Word Count, when all bits are Is and a
carry is propagated through the register, the lowgoing carry from the most significant bit (bit 15) is
inverted and is applied to the clock input of the
Drive Word Count Overflow (DRWC OFLO) flipflop as a positive-going transition. Consequently,
this flip-flop will be clocked on the leading edge of
the clock pulse, and causes AWRE DRWC OFLO
(0) H to be asserted. This signal inhibits further
Massbus cycles by causing the CSTB DIS SCLK
(Disable Sync Clocks) flip-flop to set.
The Drive Word Count overflow flip-flop is cleared
by the CST A CLR + GO CLR L signal, which is asserted by CD LO, INIT, PROGRAM CLEAR or
by initializing the RH70 during a data transfer
command.

When reading the Attention Summary (AS) register, the parity check logic is inhibited, since it is not
known how many devices will respond with their respective Attention Summary bits. Consequently,
when the AS register is read, BCTB AS REG H is
asserted which inhibits the setting of the MCPE
flip-flop.

6.10.2 Word Count Overflow
For Word Count, when all bits are Is and a carry
is propagated through the register, the carry (RIP
CLK) output of WCI5 is applied to the WC OFLO
flip-flop, which causes this flip-flop to set on the
trailing edge of the clock pUlse. This asserts A WRE
WC OFLO (0) H which inhibits the CSTC SMC
(Start Memory Cycle) flip-flop from setting, thus
terminating further memory data transfers.

The MCPE flip-flop is cleared by CSTB CLR ERR
L which is a function of CLR . GO CLR, or the
posting of a I in the TRE bit position (bit 14) of
the CS 1 register.

6-21

6.12 LOGIC DIAGRAM MDPA
This sheet contains the control logic which controls
the clocking sequence for the RA, RB, Re, and
RD registers. Refer to Figures 4-5, 4-7, and 4-8 for
the following detailed description of the data
buffer.

MDPA CLK RB H is derived from AND-OR gate
EI04-pin 8 as a result of one of the following
conditions:

6.12.1 RA FULL and RB FULL Flip-Flops
The RA FULL and RB FULL flip-flops are shown
in zone D2 and C2 and indicate the status of the
RA and RB registers, respectively. MDPA CLK
RA H is the signal used to clock the RA FULL
flip-flop; MDPA CLK RB H is the signal used to
clock the RB FULL flip-flop. These flip-flops are
clocked on the leading edge of the clock signals.
When either flip-flop is clocked, the set output goes
high, indicating that the respective register is full.
The RA FULL flip-flop is cleared by the generalpurpose initialize pulse (CSTD DB INIT L) or by
th(~ MDPA CLR RA L signal. MDPA CLR RA L
is generated approximately 50 ns after the data has
been clocked from RA into RC. (Note that MDPA
CLK RC H occurs at the l00-ns tap on delay line
EI02 and at the 150-ns tap, AND gate EI00-pin 6
is asserted low which creates MDPA CLR RA L to
direct-clear the RA FULL flip-flop.) The 1OO~ns delay ensures that the data has been transferred to
RC and has had time to stabilize.

6.12.2 MDPA CLK RA H, MDPA CLK RBH
MDPA CLK RA H is derived from AND-OR gate
EI13-pin 8 as a result of one of the following
conditions:
In a read operation, when the contents
of OBUF is being clocked into RA (twoinput AND gate-pins 2, 3)

In data buffer maintenance operation,
when Unibus data is being clocked into
RA (three-input AND gate-pins 4, 5, 6)

In a Read operation, when the contents
of OBUF is being clocked into RB during a Read command (two-input AND
gate-pins 2, 3)

In data buffer maintenance operation,
when Unibus data is being clocked into
RB (three-input AND gate-pins 4, .5, 6)

When memory data is being clocked into
RA or RB, or both, during a Write or
Write-Check command (four-input AND
gate-pins 1, 11, 12, 13).

6.12.2.1 Assertion of CLK RA, CLK RB During
Read Command - The topmost AND gate in EI13pin 8 is grounded and is not used. In a Read command, data from the drive is transferred to R E, sequences up to OBUF, and is transferred to RA or
RB, then to RC or RD for transfer to memory.
The two-input gate in E 113-pin 8 is asserted during
a Read command if OBUF is full, Input Ready
(IR) is asserted, and the RB ENA pointer is pointing to an even word. Assertion of the IR signal
(MDPA IR H) indicates that the RA register is.
empty and has been selected to receive a data word
from OBUF or that the RB register is empty and
the RB register is selected to receive a word from
OBUF. MDPA IR H, MDPH READ H~, and
MDPD OBUF FULL (1) Hare ANDed in AND
gate EII4-pin 8. The output of this gate is driven
down delay line EI19 by driver Q6. 100 ns after the:
start of the delay line, AND gate EII4-pin 12 i~;
qualified. If the RB ENA pointer is selecting the:
even word [MDPD RB ENA (0) H], the two .. input
AND gate of AND-OR gate EIl3-pin g is qual·,
ified. This causes the MDPA CLK RA signal to be:
generated which clocks the RA register with the:
contents of OBUF. If the RB ENA pointer is select··
ing the odd word [MDPD RB ENA (1) H], the
two-input AND gate in AND-OR gate E104"pin 8
is qualified. This causes the MDPA CLK RB H sig·'
nal to be generated, which clocks the RB n:gister

The RB FULL flip-flop is cleared in exactly the
same manner as the RA FULL flip-flop. In other
words, approximately 50 nanoseconds after the RD
register is clocked, MDPA CLR RB L is generated
(note the 150-ns tap on delay line E091). This ensures that the data has had time to be transferred
from RB to RD and stabilize. At this point, the RB
FULL flip-flop can be cleared.

When memory data is being clocked into
RA or RB, or both, during a Write or
Write-Check command (four-input AND
gate 1,11,12, and 13).

6-22

with the contents of OBUF. At the same time,
AND gate El14-pin 6 is asserted, which generates
MDPA CLR OBUF H. 50 ns later (150-ns tap on
delay line E1l9), the CLR OBUF signal is negated,
and the OBUF FULL flag is cleared, releasing that
data word from the OBUF register.
NOTE
At the 200-ns tap on delay line E119, AND gate
El14-pin 12 becomes negated. This means that the
eLK RA or eLK RB signal is approximately 100 ns
wide, plus additional gate delays.

four-input AND gate of El13-pin 8 for the CLK
RA signal and the four-input AND gate of EI04pin 8 for the CLK RB signal. The inputs to these
gates are described below.

The CSTA WR + WR CHK H signal
designates that a Write or Write-Check
command has been loaded into the
drive.

The CDPK DATA RDY CNTLX H signal is the clock pulse from the
RH70jCache Interface, which is used to
clock memory data into the RA or RB
register. When this signal is asserted to
the RH70 Controller, it means that the
Cache arbitration logic has recognized
this controller. The X designates one of
four RH70 Controller (Controller A, B,
C, or D) which may be installed in the
system.

AWRA DBL (1) L and the sense of the
RB ENA pointer. If AWRA DBL (1) L
is asserted, it indicates that the DBL
flip-flop is set and the bottom gate of
El13-pin 8 and EI04-pin 8 are both enabled. As a result, both RA and RB will
be clocked simultaneously. When the
DBL signal is not asserted, the CLK RA
or CLK RB signal is generated as a result of the sense of the RB ENA pointer.
If MDPD RB ENA (0) H is asserted,
RA CLK is generated, which will transfer the even word from memory to the
RA register. If MDPD RB ENA (1) H
is asserted, RB CLK is generated, which
will transfer the odd word from memory
to the RB register.

The output of AND-OR gate El13-pin 8, used to
yield the CLK RA signal, and the output of ANDOR gate EI04-pin 8, used to yield the CLK RB signal, are ORed in OR gate E099-pin 3 to assert
MDPA INC RB ENA H. On the trailing edge of
this signal, the RB ENA pointer is incremented to
switch to the opposite side of the data path (odd
word to even word or even word to odd word).
6.12.2.2 Assertion of eLK RA or CLK RB During
Maintenance Operation - When writing the data buffer during maintenance operation, data from the
Unibus can be sequenced through the data buffer
and transferred back to the Unibus. This is accomplished as described below. BCTA DB IN L from
the register decoder enables one input of the threeinput AND gate in E1l3-pin 8 and in one input in
AND gate EI04-pin 8. A second input to each of
these gates is the register strobe signal (BCTB REG
STR H) which allows the registers to be clocked
with data. A third input to each gate is the RB
ENA pointer which determines whether data will
be clocked into the RA (even word) or RB (odd
word) side of the data path. For example, assume
that the data buffer is initialized to point to the RA
register [RB ENA (0) H asserted]. The first word
written by the program is clocked into the RA register since the CLK RA H signal will be asserted. In
addition to clocking the RA register, this signal is
applied to OR gate E099-pin 1, generating MDPA
INC RB ENA H. This switches the RB ENA
pointer, which will now point to the odd word (RB
register) portion of the data path. As a result, the
next data word from the Unibus will be clocked
into the RB register.

6.12.3 RC FULL and RD FULL Flip-Flops
The RC FULL and RD FULL flip-flops are shown
in zones B2 and A2 and designate the states of the
RC and RD registers, respectively. MDPA CLK
RC H is the signal used to clock the RC FULL register; MD P A CLK RD H is the signal used to
clock the RD FULL register. These flip-flops are
clocked on the leading edge of the clock signals.
The RC FULL and RD FULL flip-flops can be
cleared in one of the following ways:

6.12.2.3 Assertion of CLK RA or CLK RB During
Write or Write-Check Command - In a Write or
Write-Check command, data from memory is applied to RA and RB. This is accomplished via the

6-23

By the general-purpose CSTD DB INIT
L signal which initializes the data buffer.

NOTE
The third input [RD ENA (0) H] to AND
gate EI07-pin 6 is not required, but is
merely implemented to verify that the
pointer is switching as required.

By the MDPE CLR RC Land MDPE
CLR RD L signals, which are asserted
after the contents' of the RC or RD has
been transferred through the MX R to
the RE register during write, write-check
or data buffer maintenance operations.
This occurs approximately 150 ns after
the transfer of data from RC or RD into
RE.
By the CSTC READ DONE L signal,
which is a timing signal derived from the
RH70/Cache Interface during read operations. When asserted, this signal indicates that merriory has accepted the
data and the RC or RD register may be
cleared in order to allow new data to be
loaded into these registers.

During a write or write-check operation,
when both RC and RD are empty and
RA is full (see AND gate EI07-pin 8).

During a single-word transfer to memory (read operation), either the thn:e-input AND gate in AND/OR gate EI06pin 8, or the three-input AND gate in
AND/OR gate EI05-pin 8 is assertt:d. If
the RD ENA pointer is pointing to RC,
MDPD RD ENA (1) H is negated and
the three-input AND gate associated
with E 106-pin 8 is qualified, causing the
next data word to be transferred from
RA to RC. Conversely, if the RD lENA
pointer is pointing to RD, MDPD RD
ENA (0) H is negated and the thn:e-input AND gate in EI05-pin 8 is qualified,
causing the next data word to be transferred from RB to RD.

During a double-word transfer to memory (read operation), when RA and RB
are both full, RC and RD are both
empty, a Read command and doubleword operation is specified, all inputs to
the four-input AND gates in AND-OR
gates EI06-pin 8 and EI05-pin 8 are
qualified, which ultimately cause both
RC and RD CLK signals to be asserted.

6.12,.4 MDPA eLK RC H, MDPA CLK RD H
Data is clocked into the RC and RD registers under the following conditions:
1.

During maintenance operation, or when
the program is executing a Write or
Write-Check conimand, data is transferred from RA to RC and/or RB to
RD.
Normally, durin$ a Read command,
double words are: transferred to memory
from RC and RD. The act of transferring either RA in~o RC or RB into RD
initiates a Cache memory request. Thus,
during double-ward transfers the RH70
logic forces the assembly of a double
word into RA and RB before attempting
a transfer to RC and RD.

When the output of E 106-pin 8 goes low as a result
of one of the conditions just mentioned, it is driven
down delay line EI02 by driver Q6. 100 ns afte:r the
pulse is sent to the delay line, AND gate E090-pin
12 is asserted, which causes MDPA CLK RC H to
be asserted. Similarly, if E 105-pin 8 goes low, this
pulse is driven down delay line E091 via driveJr Q7.
100 ns after this pulse is applied to the delay line,
AND gate E090-pin 8 is qualified, which causes
MD P A CLK RD H to be asserted. Both signals
are cleared 50 ns later (see 150-ns tap on delay line
EI02, which inhibits E090-pin 12 and the IS0-ns
tap on delay line E091, which inhibits E090-pin 8).

MDPA CLK RC H is derived from delay line EI02
as a result of one of the following conditions:
MDPA CLK RD H is generated in a similar manner to delay line E09I. The differences between the
two are noted.
1.

During data bUffer maintenance operation, when RA is full [MDPA RA
FULL (1) H] and RC is empty [MDPA
RC FULL (0) H]. This is implemented
in AND gate EI07-pin 6.

6-24

6.12.5 Parity Check Enable
When a write or write-check operation is specified,
one input to AND gate E1l5-pin 10 and one input
to AND gate E 1I5-pin 13 is enabled. If the output
of E106-pin 8 goes low, MDPA EN EWPCK H is
asserted to enable the even-word parity check circuitry, which monitors the contents of the RA register,
plus the parity bits. If EI05-pin 8 goes low, MDPA
EN OWPCK H is asserted to enable the odd word
parity check circuitry, which monitors the contents
of the RB register, plus the parity bits. When
double-word operation is specified, both the odd
and even-word parity check circuitry are enabled.
For read or data buffer maintenance operations,
the parity check enable signals (MDPA EN
EWPCK H, MDPA EN OWPCK H) are inhibited.

memory data during write or write-check operations, OBUF data during read operations, and
Unibus data during maintenance operations. The
OBUF data and Unibus data are multiplexed in the
IMX multiplexer shown on logic diagram MDPH.
The output of the IMX in turn feeds the AMX.
During write or write-check operations, the A inputs (AO, AI, A2, and A3) inputs to AMX are enabled; during read or maintenance operations, the
B inputs (BO, Bl, B2 and B3) inputs are enabled.
6.13.2 Parity Bits (AMX)
A section of the AMX monitors the memory parity
bits during write or write-check operations. CDPC
MEM BYTE 1 PAR H represents parity for the
high byte of the even data word; CDPC MEM
BYTE 0 PAR H represents parity for the low byte
of the even data word. In the case of data buffer
maintenance operations or read operations, the parity signals are unasserted into the RA register.

6.12.6 START MEM Enable
When either EI06-pin 8 or EI05-pin 8 goes low
(causing the RC CLK or RD CLK signals, respectively), MDPA START MEM H, at the output of
OR gate EI00-pin 11, is asserted. This signal is sent
to the memory control where error conditions are
examined (refer to logic description of logic diagram CSTC).

6.13.3 RA, RC Registers
The output of the AMX is applied to the RA register, due to assertion of the MDPA CLK RA H signal. The output of the RA register in turn is
applied to the RC register (due to assertion of the
MDPA CLK RC H signal) and also to the parity
generator/checker logic on logic diagram MDPC.

NOTE
During data buffer maintenance generations, this signal is inhibited in the memory control logic since no
memory transfer takes place in this mode.

6.13.4 MXR
The output of the RC and RD registers are connected to the Mixer (MXR). If MDPD MXR SEL
(1) H is asserted during write, write-check or data
buffer maintenance operations, the output of the
RD register is applied to the MXR and if MDPD
MXR SEL (1) H is not asserted, the output of the
RC register is applied to the MXR.

If no errors are present by the time of the REQ
CLK signal (which occurs approximately 100 ns
later), the next memory request is issued. fifty ns after the data has been clocked into RC, or RD, or
both, MDPA CLR RA L, or MDPA CLR RB L,
or both, are asserted, which direct-clears the RA
FULL or RB FULL flip-flops. At the same time
(see the 150-ns tap on delay lines EI02 and E091),
MDPA CLR SMC H is asserted, which clears the
Start Memory flip-flop on CSTC that previously
monitored and synchronized the error conditions.

During a read operation, the contents of the RC
register is applied to drivers on the RH70/Cache Interface, which eventually asserts data to the even
word in memory.
6.13.5 Parity Bits (MXR)
Parity bits which are transferred through the MXR
are applied to an MXR multiplexer.. In this multiplexer, the STB (Strobe) input is used. Consequently, during write operations, this multiplexer
forces Os as parity bits. This prevents false parity
from being sent through the data buffer so that correct parity can be generated in the parity generator

6.13 LOGIC DIAGRAM MDPB
This diagram contains the even word memory data
registers. This includes the AMX, the RA and RC
registers and the MXR logic.
6.13.1 AMX Multiplexer
The AMX consists of four and one-half two-input
quad multiplexer chips. This multiplexer accepts

6-25

between RG and OBUF for transfer to the drive. If
a write-check or mainten~nce operation is specified,
the RC or RD parity bits are selected, depending
on the state of the MXR SEL flip-flop. If MDPD
MXR SEL (1) H is asserted, the parity bits associated with RD are applied through the MXR; if
MDPD MXR SEL (1) H is not asserted, the parity
bits associated with RC are applied through the
MXR.

word-low byte, parity even word-high byte and parity even word-low byte. During read operations,
parity is generated by these circuits when data is
written into memory. While in write and writecheck operations, parity is checked by these drcuits. For data buffer maintenance operations, parity is generated as data is written through the data
buffer.
The upper two parity generator/checker chips (parity odd word-high byte and parity odd word-low
byte) accept the 16-bit data word from the RB register while the two lower parity chips accept the 16bit data word from the RA register. In addition,
each chip has a ninth input, which is the actual parity bit from memory in write or write-check operations and which are Os for data buffer
maintenance operations or read operations. The parity bit for each chip is exclusively-ORed in the
XOR gate EI03 with one of four invert signals:
CSTA INV 0, CSTA INV 1, CSTA INV 2 or
CST A INV 3. The assertion or negation of these
signals is controlled by four corresponding control
bits in the CS3 register, and allows bad parity to be
simulated in order to check the parity generator/checker circuits themselves. During a read operation, the outputs of the parity generator I checker
circuits are applied to the RC and RD registc~rs.
During write or write-check operations, the parity
outputs are applied to logic to see if there is a parityerror.

6.14 LOGIC DIAGRAM MDPC
This diagram contains the odd word memory data
registers, BMX, RB and RD registers and parity
generator /checker circuits. The odd word memory
data registers are similar i to the even word memory
data registers described on logic diagram MDPB.
Note that the left-hand side of the diagram shows
the BMX which is similar to the AMX on MDPB.
However, the BMX is as~ociated with the odd word
(that is, bits 16 - 31 from memory). The BMX accepts data from memo~y during write or writeIcheck operations or accepts data from the IMX
multiplexer during read br data buffer maintenance
operations. The IMX selects data from OBUF during read operations or s¢lects Unibus data if data
buffer maintenance operation is employed.
16.14.1 Parity Bits (BMX)
A section of the BMX: monitors the parity bits
from memory during write or write-check operations. CDPD MEM BY~E 2 PAR is the parity bit
associated with the 10\\f byte of the odd word;
CDPD MEM BYTE 3 PAR is the parity bit associated with the high byte; of the odd word. In the
Icase of data buffer maintenance operations or read
operations, these parity signals are unasserted to
the RB register.

6.15 LOGIC DIAGRAM l\1DPD
This diagram contains the control logic which controls the clocking sequence for the RF, RG Blnd
OBUF registers. The diagram also shows the RB
ENA pointer, RD ENA pointer, and the MXR
SEL pointer.

6.14.2 RB and RD Registers
The output of the BMX .is applied to the RB register due to assertion of the MDPA CLK RB H signal. The output of the RB register in turn is
applied to the RD register (when the MDPA CLK
RD H signal is asserted) and also to the parity genlerator / checker circuits (shown on this diagram).

6.15.1 Clocking the RF Register, RF FULL FlipFlop
The RF register is clocked on the leading edge of
the MDPD RF FULL (1) H signal. Note that this
signal is derived from a flip-flop configured as a
latch; there is no CLK RF signal as with the other
registers. Although the configuration is different,
the principle of operation remains the same.

6.14.3 Parity Generator fChecker Circuits
The parity generator/checker circuits consist of
four chips: parity odd word-high byte, parity odd

6-26

6.15.5 RG RDY Flip-Flop
When the RG RDY flip-flop is set, it indicates that
the data in the RG register has previously been
loaded, the data has had time to settle and stabilize, and the parity has been checked. This is used
for Data Late (DLT) or data overrun conditions.
Normally, when writing the drive, the data in
OBUF is strobed into the drive on the leading edge
of SCLK and the data in OBUF is changed on the
trailing edge of SCLK. Before the data can be
changed however, it must be ensured that a data
word is in RG and has stabilized because this is the
next word to be transferred to OBUF. The setting
of the RG RDY flip-flop indicates that this condition has been satisfied.

When MDPE RE FULL (1) H (designates RE register full) and MDPD RF FULL (0) H (RF register
empty) are asserted, the output of AND gate E060pin 6 is asserted and is driven down delay line E071
via driver Q4. 100 ns after this signal is applied to
the delay line, the set condition of the latch is asserted, which yields MDPD RF FULL (1) H, causing the data from the RE register to be clocked
into the RF register.
NOTE
The TEST INPUT A signal of pin 3 of E060 is a
test input for module checkout.
6.15.2 Clearing the RE FULL Flip-Flop
At 150 ns on the delay line, MDPD CLR RE L is
asserted, which allows the RE FULL flip-flop to
now be cleared since the contents of RE has already been transferred to RF. At 175 ns on the delay line, MDPD CLR RE L is negated, resulting in
a 25-ns pulse.

The RG RDY flip-flop is set 150 ns after the
MDPD RG FULL (1) H signal is asserted. The 150
-ns delay is comprised of two 75-ns delays. The first
75-ns delay is a result of the delay line (150 -ns tap,
minus 75-ns tap); the second 75-ns delay is due to
the fact that the trailing edge of the 75-ns pulse
traveling down the delay line clocks the RG RDY
flip-flop. The pulse traveling down the delay line is
75 ns in length since the delay line is turned off at
the 75-ns tap by the setting of RG FULL.

6.15.3 Clocking the RG Register, RG FULL FlipFlop
The data in the RF register is transferred to the
RG register upon assertion of MDPD CLK RG H.
This signal is dependent on the RG register being
empty and the RF register being. full. These conditions cause AND gate E060-pin 8 to be asserted.
The output is driven down delay line E052 via
driver Q3. After 75 ns, MDPD CLK RG H is asserted via AND gate E050-pin 11. The CLK RG
signal clocks the contents of the RF register into
the RG register, and causes the RG FULL flip-flop
to be direct-set.

The clearing of the RG FULL flip-flop after the
data has been transferred to OBUF causes the clearing of the RG RDY flip-flop, which indicates that
the data in RG is not valid.

6.15.6 Clocking OBUF, OBUF FULL Flip-Flop
To clock a data word from RG into OBUF requires the RG register to be full and the OBUF register to be empty. When these conditions are
satisfied, AND gate E060-pin 12 is qualified and
the output is driven down delay line E041 via
driver Q2. At 150 ns, MDPD CLK OBUF H is asserted via gate E040-pin 8 and gate E062-pin 3. The
150-ns delay allows the data in RG to settle and
stabilize and provides additional time for parity
checking, since the parity check is situated between
RG and OBUF. MDPD CLK OBUF H clocks the
data from the RG register into the OBUF register
and also direct-sets the OBUF FULL flip-flop,
which then turns the delay line off.

6.15.4 Clearing RF FULL Flip-Flop
50 ns after the CLK RG signal is asserted (125-ns
tap on delay line E052), MDPD CLR RF L is asserted, which clears the RF FULL flip-flop to allow new data to be entered into the RF register. 50
ns after the CLR RF signal is asserted (175-ns tap
on delay line E052), the signal is negated, resulting
in a 50-ns pulse.
The RF FULL flip-flop is cleared by the generalpurpose CSTD DB INIT L signal, or approximately 125 ns after the transfer of data from RF
into RG by the MDPD CLR RF L signal.

6-27

During a write operation, :once OBUF is full and
th{~ OBUF FULL flip-flop 'is set, OBUF FULL re-

seLK

mains set for the entire transfer until an error or
word count overflow occurs. It may be recalled in
the other data buffer registers that the delay line
was used to generate the clock and clear signals necessary to transfer data from one register to the
next. However, the delay line is not used in a write
operation after the first data word reaches OBUF.

Jr----~l--Ict'r---I~l_.
~.3

~~6~~ __________________1

L~"_____________r--~.
11-2966

Figure 6-8
3.

NOTE

Delay line E041 is used hi the normal fashion for
read, write-check and data buffer maintenance operations, in addition to the first data word in a write
operation.
At this point, a word is in OBUF and the OBUF
FULL flip-flop is set. Ass~me that successive data
words have filled the rest .of the data buffer. The
RH70 then asserts the RUN line to the drive and
th(! drive proceeds to rotate to the correct address.
When the correct address is found, the drive issues
a SCLK pulse. The leading edge of SCLK causes
the data in OBUF to be transferred to the drive.
The trailing edge of SCLK, initiates a Drive Clock
pulse which causes the data in RG to sequence to
OBUF (provided RG RDY is set, indicating that a
word has been loaded in RG and has stabilized).
Successive SCLK signals cause the data in OBUF
to be transferred to the drive, while successive
Drive Clock (trailing edge of SCLK) signals cause
th(~ data in RG to sequence to OBUF by causing
E50-pin 3 and E62-pin 3 tp assert CLK OBUF H
signals without using the 'delay line. The process
continues until an error condition is flagged or
word count overflow occurs.

Massbus Data Transfer Sequence

Drive Clock (trailing edge) - clears RG
FULL flip-flop since RG is now lempty.
This flip-flop is cleared on the positivc;:going transition from gate E050"pin 3.
This gate went negative on leading edge
of Drive Clock and goes positive on trailing edge.

NOTE
If RG FULL is reset, the output from the
1 side direct-clears the RG RDY flilp-flolt,
indicating that the data in RG is no
longer valid.

SCLK (leading edge) - second data
word transferred from OBUF to drive.

SCLK (trailing edge) - third data word
had transferred from RF to RG 150 ns
after RG was emptied (in step 3). This
data word now transfers from RG to
OBUF, provided RG RDY flip-flop :is
set, indicating that the data in RG has
had time to settle and have the parity
checked.

This process is implemented :by the logic as described in Figure 6.8.
'

The transfer of the data word from RG
to OBUF is caused by MDPD CUi(
OBUF H which is asserted as a n:sult of
MDPD WRITE Hand CSTB DRIVE
CLKH.

SCLK (leading edge) - clocks first data
word from OBUF to drive.

This process continues until error condition is
flagged or word count overflow occurs.

SCLK (trailing edge creates Drive
Clock) - second data word in RG sequences to OBUF. This is accomplished
by MDPD WRITE Hand CSTB
DRlVE CLK H, which are ANDed in
E050-pin 3 td assert MDPD CLK
OBUF H. RG, register is now transferred to the OB,UF register.

6.15.7 Clearing the RG FULL Flip-Flop
The RG register and the RG FULL flip-flop is
cleared by MDPD CLR RG L. This signal is generated 50 ns after the data word is transferred from
RG to OBUF. (At 150 ns on the delay line, data iis
clocked from RG to OBUF and at 200 ns, the RG
FULL flip-flop is reset by the MDPD CLR RG L
signal).

6-28

In addition to resetting the RG FULL flip-flop via
the delay line, there are two other conditions which
can reset the RG FULL flip-flop. One is the general-purpose CSTD DB INIT L signal which intializes the RH70. The second is the positive-going
transition from gate E050-pin 3 which clocks the
flip-flop reset. This occurs on the trailing edge of
Drive Clock during a write operation.

During a read operation when the data
in OBUF has been clocked into the RA
or RB registers. The MDPA CLR
OBUF H signal is asserted at the time
that the data is clocked into RA or RB.
50 ns later, the negation of CLR OBUF
H causes the OBUF FULL flip-flop to
clear.

6.15.8 Clearing OBUF FULL Flip-Flop

During maintenance operation, the
OBUF FULL flip-flop is cleared when
the program has read the data buffer.
This is the result of ANDing BCTB DB
OCLK Hand BCT A DB OUT L in gate
E059-pin 11. The BCTB DB OCLK H
signal is asserted when the processor has
recognized that the data has been read
from the data buffer. On the trailing
edge of the BCTB DB OCLK H signal,
the OBUF FULL flip-flop is clocked
clear.

The OBUF register is cleared as a result of SCLK
from the drive which clocks the data out of OBUF.
The OBUF FULL flip-flop is cleared in one of the
following ways:
1.

By the general-purpose CSTD DB INIT
L signal which initializes the RH70.
(This is a direct clear.)

On the trailing edge of MD PE CLK
MXR WORD H during a write-check
operation. On the leading edge of
MDPE CLK MXR WORD H, data
from the RC or RD register is compared
to OBUF data. If the write-check
showed no error, the data in the RC or
RD register and data in OBUF can be
invalidated by clearing the respective
Register Full flip-flops.

6.15.9 MDPD DB EMPTY L, MDPD LAST
WORDH
These signals are used during a read operation
when an error has been detected in the drive but
not in the controller. In this case, the data in the
data buffer is transferred to memory, which allows
error correction on those drives using error correction hardware. The error condition from the drive
causes the transfer to stop at the next EBL pUlse.
The data buffer is empty (MDPD DB EMPTY L)
when all the register flags are unasserted. These include the RA, RB, RC, RD, RE, RF, RG and
OBUF registers which are ANDed in gate E049-pin
8.

If a write-check error (MDPE WCE L)
occurs, the data is frozen in OBUF. This
keeps AND-OR gate E061-pin 8 low to
prevent the clearing of the OBUF FULL
flip-flop. When the programmer recognizes the error, it will clear the WCE bit
(bit 14, CS2 register), which in turn
causes the OBUF FULL flip-flop to
clear.
3.

In the case where word count overflow has not yet
occurred during a read operation and an error has
occurred in the drive and not in the RH70. The
RH70 contains logic to determine if the operation
is a single- or double-word transfer. If the last transfer should be a double word, the RH70 tries to assemble a double word and if an error occurred,
preventing the drive from sending additional words,
the RH70 would be left waiting for a word which it
will never receive. To avert this situation, the RH70
must detect the fact that the last word is in the data
buffer and also must force the memory operation
to be performed as a single-word rather than as a
double-word operation. This is the function of the
MD PD LAST WORD H signal. Note that the
single-word section of the data buffer must be

When the last data word has been transferred during a write operation (from
RG to OBUF). This occurs when there
is no word in RG to transfer to OBUF
[MDPD RG FULL (0) H]. On the leading edge of Drive CLK, the output of
E061-pin 8 goes low. On the trailing
edge of CSTB DRIVE CLK H, the positive-going transition from this gate
clocks the OBUF FULL flip-flop clear.
Consequently, OBUF FULL is cleared
on the last transition of Drive CLK during the normal completion of a Write
command.

6-29

SEL H. On the trailing edge of this signal, the flipflop is toggled to the alternate state. There is one
condition in which the MXR SEL flip-flop is prevented from toggling. This occurs during a data
transfer command when the BAI (Bus Address Increment inhibit) bit is set. In this situation, it is desired to do transfers to or from the same 10Gation
and the same memory data register (either RC or
RD).

empty (RE, RF, RG, and OBUF). In the doubleword section, if either MOPA RA FULL H or
MDPA RB FULL H is ~sserted, but not both,
MDPD LAST WORD H 1s asserted. If both RA
FULL and RB FULL are lasserted, meaning there
are two words in the buffed MDPD LAST WORD
H is inhibited, and the ope~ation is performed as a
double-word transfer. MDHD LAST WORD H is
ANDed with CSTB REAd EXC H on logic diagram AWRA. With MDPr? LAST WORD Hand
CSTB READ EXCP H b:oth asserted, the DBL
flip-flop is prevented fromi setting (see logic diagram AWRA), thus forcina a single-word memory
operation.

NOTE
If the RH70 is in the RDY state (ready to receive a
command), the state of the BAI bit is immaterial!1
since no memory transfers will take place and in-,
crementing the MXR SEL pointer will always occur
during data buffer maintenance operation.

6.15.10 Mixer Select (MDrD MXR SEL)
The MXR SEL flip-flop sw~tches the select lines on
the: mixer multiplexer to alternately point to the RC
and RD registers. In write: or data buffer maintenance operations, the MX;R output is applied to
RE. In write-check operatibns, the contents of the
MXR loaded from RC or ~D is compared with the
contents of OBUF in tqe Exclusive-OR gates.
When the RH70 is initialized by CSTD DB INIT
L, the MXR SEL flip-flop is initially set or cleared
to control the MXR. If DB INIT is a result of
Unibus INIT, PG CLR, or ;Power Fail, the Bus Address register is cleared [BA 01 (0) H asserted] and
th(~ MXR SEL flip-flop is cleared by gate E080-pin
8. When a data transfer cotnmand with the GO bit
is loaded in to the drive, CST A GO CLR L is asserted in the RH70, causing: a DB INIT.

6.15.11 RD ENA Pointer
The RD ENA pointer is primarily used for thl~ read
operation to allow the RC and RD registers to bt~
clocked at the appropriate times.
During write-check or write operations, the pointer
toggles but is not examined, and in data buffer
maintenance operations, the pointer is alternately
toggled as individual words are being sequenced
through the buffer.
The RD ENA pointer is direct-set and direct·
cleared in the same manner as the MXR SEL flip,·
flop just described. This pointer is also wired to
toggle on alternate clock inputs. The clock input is
MD P A REQ CLK H, which is the ORed condition
of the RC and RD Clock signals (MDPA CLK RC
Hand MD P A CLK RD 1-1). During read operations, there are two cases where the RD ENA
pointer is inhibited from toggling. One is the Betting
of the Bus Address Increment Inhibit [CSTA BAI
(1) H] bit, which causes data transfers to or from
the same memory location and causes the RC or
RD register (but not both), to be utilized. The second occurs when the DBL (Double) flip-flop is set.
In this case, when doing double-word transfers to
memory, the RD ENA pointer is overridden by
AWRA EN DBL H. Conceptually, this can he
thought of as adding two to the flip-flop pointer,
which leaves it in its original state since two words
are clocked simultaneously (one in RC and one in
RD).

NOTE
CSTA GO CLR L is one of the means of generating
CSTD DB INIT L. However, the GO CLR signal
will not cause the Bus Address registers to clear
[does not affect BA 01 (0) H].
If AWRA BA 01 (1) H is asserted (odd-word
boundary), the MXR SEL flip-flop is directly-set,
causing the MXR to point ~o the RD register (even
word). If the bus address bit (BA 01) is reset, (even
word) the MXR SEL flip-flop remains reset due to
the DB INIT signal leaving the flip-flop pointing to
the RC register.
The MXR SEL flip-flop is wired to toggle on every
clock input. The clock inpu~ is MDPE INCR MXR

6-30

6.15.12 RB EN A Pointer
The RB ENA pointer is used during all operations
(read, write, write-check and data buffer maintenance). It is direct-set and direct-cleared in the
same manner as that previously described for the
MXR SEL pointer. This flip-flop pointer is wired
to toggle on alternate clock inputs and to control
the clocking of the RA and RB registers. The clock
input to this pointer is the MDPA INC RB ENA
H signal, which is derived from the logic that generates the clock signals for the RA and RB registers.
Consequently, when the MDPA CLK RA signal is
asserted, the MDPA INC RB ENA H signal is asserted, causing the RB ENA pointer to switch and
point to the odd-word RB register. When the CLK
RB signal is generated, MDPA INC RB ENA H is
again asserted and causes the RB ENA pointer to
toggle to the even-word RA register.

The MDPE CLK MXR WORD H is derived from
delay line EOll and driver Ql. This input to the delay line is from OR-AND gate E028-pin 8.

6.16.1.1 Write Operation - For a write operation,
this gate is qualified as follows:

If a write or write-check operation is being performed, the RB ENA pointer is inhibited from
toggling if a double word from memory is transferred to RA and RB simultaneously. The pointer
is overridden in this case and can conceptually be
thought of as being incremented by two, which effectively leaves the flip-flop pointer in its original
state. The top two-input AND gate in AND-OR
gate E039-pin 6 accomplishes this function.
If the RH70 is not in the RDY (ready) state (performing a read, write, or write-check operation),
and the BAI (Bus Address Increment inhibit) bit is
set, the pointer is inhibited from toggling, since it is
desired to transfer data to or from the same memory location. The lower two-input AND gate in
AND-OR gate E039-pin 6 performs this function.

The top two two-input gates are asserted
when the MXR SEL flip-flop is pointing
to the RD register [MDPD MXR SEL
(1) L] and the RD FULL flip-flop is full
[MDPA RD FULL (1) L] or when the
MXR SEL flip-flop is pointing to the
RC register [MDPD MXR SEL (0) L]
and the RC FULL flip-flop is full
[MDPA RC FULL (1) L]. These two
gates, in essence, are asserted when the
MXR SEL pointer is pointing to the register that is full.

During a write, CST A WR L is asserted,
qualifying the three-input gate.

RE FULL (0) L must be asserted, since
it is necessary to have a word in the
MXR and no word in the RE register to
transfer a word to RE. This is accomplished in the four-input gate of E28.

With the above conditions satisfied, OR-AND gate
E028-pin 8 is asserted and the pulse is driven down
delay line EOl1. 100 ns after this, MDPE CLK
MXR WORD H is asserted which asserts MDPE
CLK RE L. This signal clocks the MXR data into
the RE register. This pulse is 50-ns long and is
turned off at the 150-ns tap on the delay line. Also
at 150 ns, MDPE INC MXR SEL H is asserted
and is ANDed with the state of the MDPD MXR
SEL flip-flop to clear the RC or the RD register.
For example, if data was transferred from the RD
register to RE, MD PD MX R SEL (1) H is asserted, and when the MDPE INC MXR SEL H signal is asserted, MD PE CLR RD L is asserted,
indicating that the contents of the RD register has
been transferred to RE; the RD FULL flip-flop can
now be cleared. This logic is accomplished for RD
in AND gate E038-pin 8 and for RC in AND gate
E038-pin 6. The MDPE CLR RC and MDPE CLR
RD signals are 50-ns long as they are turned off at
the 200-ns tap on delay line EO 11. On the trailing
edge of the MDPE INC MXR SEL H signal, the
MXR SEL pointer on MDPD is toggled to switch
from the RC to RD or from the RD to RC
register.

6.16 LOGIC DIAGRAM MDPE
This logic diagram contains the logic for clocking
the RE register, the RE FULL flip-flop, data parity
circuit and the exclusive-OR network used to compare the MXR contents with the OBUF contents
during a write-check operation.
6.16.1 MDPE CLK MXR WORD H
The MDPE CLK MXR WORD H signal is used in
data buffer maintenance operations, write and
write-check functions. During data buffer maintenance and write operations, MXR data is clocked
into the RE register as a result of MDPE CLK
MXR WORD H. During write-check operations,
the WCE (Write-Check Error) flip-flops are clocked
by MDPE CLK MXR WORD H. In read operations, the RE register accepts data from the Massbus and the clocking logic is consequently inhibited
for a Read command.
6-31

6.16.1.2 Data Buffer Maintenance Operation - During data buffer maintenan;ce operation, the MDPE
CLK MXR WORD H signal is generated in the
same manner, except that in the third OR gate
from the top in E028-pin :8, MDPE RDY L is asserted instead of CSTA WRITE L. The RDY signal is asserted when the RH70 is not doing a data
transfer command.

6.16.3 Inhibiting Delay Line EOll
During a Read command, the delay line is inhibite:d
since Massbus data rather than MXR data is
clocked into RE. This is accomplished in AND
gate E030-pin 8 by CSTA R D L.
During a write-check operation, if a write-check error occurs, the delay line is inhibited by th<;: assertion of MDPE WCE L which inhibits AND gate
E030-pin 8. This allows the data in OBUF to be frozen that so the programmer can examine it.

6.J6.1.3 Write Check Operation - During writecheck operation, the delay! line driven by the output
of E028-pin 8 is assert~dunder the following
conditions:
1.

The two two-input gates of E228-pin 8
function the same as that described for
write; in other words, they are asserted
when the MXR SEL pointer is pointing
to a register that is full.

The three-input 0 R gate is qualified
when MDPD OBUF FULL (1) L is asserted. This is! required since MDPE
CLK MXR WORD H in a write-check
operation is UStid to clock the WCE flipflops and these flip-flops monitor the
XOR compari$ion of the MXR and
OBUF.
.

6.16.4 RE FULL Flip-Flop
The RE FULL flip-flop is clocked-set with assertion of the MD PE CLK RE L signal, indicating
that the RE register is full. This flip-flop is cleare:d
by the general-purpose CSTD DB INIT L or by
the MD PD CLR RE L signal. After the data in RE
is transferred to RF, MOPE CLR RE L is asserted,
indicating that the data has been transferred to RF
and the data in the RE register in now invalid.
6.16.5 MDPE REG FULL H Signal
The MOPE REG FULL H signal is used to flag
the programmer of Data Late (OLT) conditions.
Ouring read or write-check operations, data from
the Massbus is applied to the RE register. If the
RE register is full [MOPE RE FULL (1) L] or if
the RH70 is in the process of clearing the RE
FULL flip-flop (MOPO CLR RE L), MOPE REG
FULL H is asserted, meaning that data cannot be
accepted by the RE register at that time.

CST A WR CHK L must be asserted for
a write-check operation which qualifies
the four-input gate to E028.

When the above conditions are satisfied, the
IV1DPE CLK MXR WORD H is asserted similar to
that described for the write operation.

NOTE
The purpose of ORing CLR RE with RE FULL is to
cover the condition where the RH70 is in the procelSS
of clearing RE FULL at the same time a clock pul!ie
may be applied, which would normally cause the
clock pulse to be lost.

6.16.2 MDPE CLK RE U Signal
The MDPE eLK RE L signal is generated by
NIDPE CLK MXR WORD H in a write operation
and data buffer maintenance operation. Note that
the output of AND gate EOI0-pin 6 is MDPE CLK
MXR WORD H and is applied to AND-OR gate
E039-pin 8, qualifying that gate to assert MDPE
CLK RE L (except for a write-check operation).

If the next Orive Clock signal (derived from the
trailing edge of SCLK) occurs while MOPE REG
FULL H is asserted, a OLT condition is flagged, indicating that the drive is ready to send anothc~r
word to RE before the last word in RE has had
time to be transferred to RF. This is shown on
logic diagram CSTB.

During a read or write-check operation, data is
taken from the drive to be: loaded into RE. In these
cases, the Drive Clock (CSTB DRIVE CLK H) signal qualifies AND-OR gate E039-pin 8 to assert
MD PE CLK RE L. Drive Clock occurs on the trailing edge of SCLK and is a: 50-ns pulse.

6.16.6 Exclusive-OR Network
In write-check operations, 16 Exclusive-OR gates
compare the contents of the MXR with the contents of OBUF. The MXR data may be eith(:r from
the RC register if the data is an even word or from
RO if the data is an odd word.

6-32

The outputs of the Exclusive-OR gates are opencollector ORed. If any two bits mismatch, the output line is pulled low. The four jumpers (W 1, W2,
W3, and W4) are provided as a maintenance aid to
isolate a defective XO R gate on one of the integrated circuits (lCs). If a defective gate in an IC
is pulling the output line low, the defective IC can
be found by removing the associated jumpers,
which isolate that IC from the output.

register from the RF and RE registers, at which
point the signal name is MBSC SYNC P A.
NOTE
The Massbus data is 18-bits wide and the RH70 data
is 16-bits wide. As a result, bits 16 and 17 are XORed into one input of the parity circuit (MDPF
RG1617 H).
If the sum of the data plus parity (RGOO-RG 1617,
plus RGPA) is odd, MDPE DATA PA L is asserted and no error is registered. If the sum is even
DATA PA is negated (high) at the D input of the
MDPE Massbus (Data Parity Error) flip-flop.

6.16.7 Odd Word and Even Word Write-Check
Error
The output of the Exclusive-OR network is applied
to the D inputs of the WCE OW (Write-Check Error-Odd Word) and WCE EW (Write-Check Error- Even Word) flip-flops. One of these flip-flops
is clocked during a write-check command when
MDPE CLK MXR WORD H is asserted. If the
MXR SEL flip-flop is set, indicating an odd word
in a double-word block, the WCE OW flip-flop is
set and if the MXR SEL flip-flop is reset, indicating an even word in a double-word block, the
WCE EW flip-flop is set when a write-check error
occurs. To find out which memory word caused the
write-check error, it is necessary to examine the Bus
Address register which will reveal the last doubleword block transferred. By implementing the logic
with two WCE flip-flops (each having an associated
status indicator in the CS3 register), the programmer can determine whether the write-check error
was caused by the odd word or the even word in
that double-word block.

When data is clocked into OBUF (MDPD CLK
OBUF H), except during a write, the MDPE flipflop is clocked-set, registering a data parity error.
Once the flip-flop is clocked-set, the 0 output inhibits the clock input, keeping the flip-flop locked until the error is recognized and cleared by the CSTB
CLR ERR L signal.
The CLR ERR signal is a function of program
clear, GO clear, Init, or DC LO (see logic diagrams
CSTB and CSTD), or by posting a I in the TRE
bit position of the CSI register (error clear).
The Parity Test (PAT) bit is a control bit from the
CS2 register which is used to invert the sense of the
parity detection generation to allow the parity
checker / generator circuits to be exercised.
6.16.9 RE Register Chip
The RE register chip shown on this diagram is a
quad two-input mulitplexer and register which accepts Massbus data during read or write-check operations, or accepts MXR data during write or data
buffer maintenance operations. Consequently, when
MD PF RE SEL L is asserted, the AO - A3 inputs
to the multiplexer are enabled. These inputs accept
Massbus data bits MBSC SYNC D 17 Hand
MBSC SYNC D16 Hand Massbus Parity bit
MBSC SYNC PA H. The fourth input (A3) is tied
high to provide for the logic inversion through the
Exclusive-OR gate E018-pin II of the parity bit.
The two Massbus data bits (D16 and D17) are Exclusively-ORed to yield MDPE RE1617 H, since
these data bits from the Massbus represent the extra two bits not used (18 Massbus data bits versus
16 bits of data in the buffer). The two bits are monitored, however, to sense their parity. As a result,
when the data is transferred to the RG register,an
18-bit parity check can be performed.

The output of the WCE flip-flops are ORed in
EOl9-pin 11 to assert MDPE WCE L, indicating
the existence of a write-check error. The summary
WCE bit can be read from bit 14 of the CS2
register.

6.16.8 Parity Checkers
Two nine-bit parity checker/generators are employed which examine the data in the RG register.
During a write operation when the data in RG is
transferred to OBUF, parity is computed and if the
number of Is in the data word is even, a parity bit
is generated to OBUF so odd parity can be transferred to the Massbus. This parity bit is designated
MDPE DATA PA L.
During read or write-check operations, a Massbus
parity bit (MDPE RGPA L) is applied to the parity
checker / generators along with the Massbus data.
This Massbus parity bit has sequenced to the RG
6-33

register to be cleared to zero-fill the rest of the sector (for disks) or record (for magtape). By stor:tng
the parity bit (OBUF PA) in the inverted sense, it
is possible to receive correct (odd) parity when this
clear signal is used.

During write or data buffer maintenance operations, MD PF RE SEL L is .unasserted which enables the BO - B3 inputs to the multiplexer.
These inputs are tied to the MXR circuit. Note that
BO and Bl are grounded since the MXR is only 16
. bits wide. The B2 and B3 inputs represent the byte
parity for each word. These parity bits are Exclusively-ORed at the multiplexer output, resulting in
word parity designated MDPE REPA L. The
MD PE CLK RE L signal clocks the selected multiplxer inputs into the RE register which is part of
this IC chip. Note that the output of Exclusive-OR
gate El8-pin 11 (MDPE REPA L) is defined low,
even though no logical inversion occurs between
this signal and the input: to the RE m ultiplexer /register. Conceptually, to maintain odd parity when converting byte parity to word parity via
X-ORing of the byte parity bits, it is necessary to
invert the sense 0 f the resultant word parity bit.

The output of the OBUF register is applied to the
Massbus drivers, (see logic print MBSA, MBSB,
and MBSC) during a write operation, is applied to
the IMX for the assembly of double words during a
read operation, or is applied to one input of the
XOR network in a write-check operation.
The output of the OBUF register is also supplied to
the Unibus via the open-collector mUltiplexers
shown on logic print CSTE for maintenance operation when reading the data buffer.
6.18 LOGIC DIAGRAM MDPH
This logic diagram contains the IMX and the
MBCBUS data drivers for the RH70/Cache Interface. The IMX multiplexes OBUF data or Unibus
data for transfer to the AMX or BMX which feeds
the RA and RB registers.

6.17 LOGIC DIAGRAM MDPF
This diagram shows the RE register (except for the
RE register chip shown on diagram MDPE), the
RF register, the RG register and OBUF. These registers comprise the single-word section of the data
path. The RE register multiplexer accepts data
from the Massbus during read or write-check operations, or accepts MXR data during write or data
buffer maintenance operation . The RE register consists of quad two-input multiplexer chips and a
four-bit register. The AO - A3 inputs are enabled
during read or write-check 'operations by CST A
RD + WR CHK H. During write or data buffer
maintenance operations, the BO - B3 inputs are: enabled. MDPE CLK RE L clocks: the selected input
data into the RE register.
. .

During data buffer maintenance operations, the
Unibus data is supplied to IMX; during read operations OBUF data is supplied to the IMX.
The right half of this diagram shows the 32 data
drivers and the four parity drivers for the
RH70/Cache Interface. Note that the contents of
the RC register are supplied to data lines DOO DI5 (even word) and the contents of the RD register are supplied to data lines DI6 - D3I (odd
word). These lines accept data from the RC and
RD registers for transfer to memory during a r,ead
operation. The data and parity drivers are consequently enabled by MDPH READ H and the appropriate SEL DATA signal from the Cache. This
diagram is common to all four RH70 Controllers
(Controller A, B, C, or D) and the signal is designated CDPJ SELDATA CNTLX H. When the
RH70 makes a request to Cache, the Cache arbitrates this request with all other requests. If this
module is plugged into the Controller D slot for example, the Cache will send a CDPJ SELDATA
CNTLD H signal to this module, which will allow
the data in the data drivers from this module to be
transferred to memory. Each of the four RH70
slots in the CPU backplane has a separate wire
from the Cache, which allows Cache to select one
of the four controllers by one of the four SEL
D ATA CNTL signals.

The output of the RE register ·is fed to the RF register. In addition, the two Massbus data bits (which
were Exclusively-ORed on diagram MDPE) and the
parity bit are fed to the RF register. The RF register is clocked when the RF FVLL flip-flop is set.
The output of the RF register is applied to the RG
register when the MDPD CLK RG H signal is asserted. The output of the RG register is applied to
the OBUF register and to the parity checkers on diagram MDPE when the MDPD CLK OBUF H signal is asserted. The OBUF register is the only
register with a clear signal designated CSTB CLR
OBUF DATA L. This signal is generated as a result of drive word count overflow or an error condition during a write operation; it allows the OBUF
6-34

6.19 LOGIC DIAGRAM CSTA
This diagram contains the command code decoding
logic, various control and status bits, the FCTN
LOAD, BAI, and BUSY flip-flops.

6.19.2 GO Bit, GO CLR Pulse
The GO Bit is stored in the drive in bit 00 of the
CSI register and must be asserted for the execution
of all data transfer commands. This results in all
data transfer commands having odd command
codes. For example, the data transfer command
codes for a write-check operation are 51, 53, 55 and
57. In addition, all reverse operations are specified
by a 7 in the least significant digit. For example,
the read reverse command code is 77. The CST A
GO H signal is asserted when the following conditions are satisfied:

6.19.1 Command Code Decoding Logic
The command code is represented in the least significant bits of the CSl register as shown below.
005

004

003

MSD
octal
digit

-I

002

001

000

A data transfer command is specified
which enables one of the inputs to gate
E52-pin 6, depending on the command
specified.

BCTD DOO IN H is asserted which designates the GO bit.

The signals associated with writing the
low byte of the CS 1 register are asserted.
These signals are BCTB REG STR H,
BCT A CS 1 IN L, and BCT A LO BYTE
H.

LSD
octal
digit

5=write-check
6=write
7=read

The three data transfer command codes (read,
write, and write-check) are decoded by BCD-todecimal decoder E56. This decoder decodes data
bits D03 - D05 from the Unibus data lines. If a
Write-Check command is specified, a binary code
of 5 is supplied to the decoder; the F5 output is asserted and fed to the data input of the WR
CHECK flip-flop. If a Write command is specified,
a binary code of 6 is supplied to the decoder, the
F6 output is asserted and fed to the data input of
the WRITE flip-flop. If a Read command is specified, a binary code of 7 is supplied to the decoder,
the F7 output is asserted and fed to the data input
of the READ flip-flop. The GO bit must be asserted for the hardware to execute the command requested by the program. The command flip-flops
are clocked by the trailing edge of the GO pulse if
the RH70 is in the ready (RDY) state. At the completion of the command execution, the flip-flop
which had been set will be cleared by the assertion
of BUSY (0) H, if a register is not currently being
accessed by the program (DEV SEL unasserted).
This is accomplished by gate E46 pin 6.

If the three data transfer command flip-flops are all
reset, indicating that the RH70 is in the ready state
(RDY asserted) the GO bit asserts CSTA GO CLR
L via NAND gate E62-pin 8. GO CLR initializes
the data path, clears all error conditions, and sets
up for a data transfer operation. In addition, the
GO CLR pulse sets the BUSY flip-flop, which indicates that a data transfer command is being
executed.

6.19.3 Function Load Flip-Flop
The Function Load (FCTN LOAD) flip-flop is set
when a data transfer command code is being
loaded. The trailing edge of the GO CLR signal
clocks the FCTN LOAD flip-flop set. The BCTA
DEV SEL H signal is asserted, indicating that the
RH70 is selected to do a register read or write and
holds the direct clear input high, preventing FCTN
LOAD from resetting. The RH70 can monitor for
non-existent devices this time, or can request the
first word from memory during write or writecheck operations. When the RH70 is deselected
(DEV SEL unasserted), the FCTN LOAD flip-flop
is direct cleared.

Various gates are shown on the outputs of these
flip-flops and provide buffered versions of the signals and also provide combinations of these signals
for use by the data buffer control logic.

6-35

6.19.6 Invert Parity Check (IPCK)
CSTA IPCKO - CST A IPCK3 are the four least significant bits of the CS3 register and are used to invert parity checking on the data words re(:eived
from memory during write and write-check operations. IPCKO is the bit associated with the even
word-low byte, IPCK 1 with even word-high byte,
IPCK2 with odd word-low byte, and IPCK3 with
odd word-high byte.

6.19.4 Ready State (RDY)
When the READ, WRITE and WR CHECK flipflops are cleared, the CST A ROY H signal is asserted, indicating that the RH70 is not doing a data
transfer command.
The 0 outputs of these flip-flops are ANDed in
AND gate E57-pin 6 and AND gate E50-pin 12 to
assert ROY.

6.19.5 BUSY Flip-Flop
The BUSY flip-flop is set when the RH70 is doing
a data transfer command. When a data transfer
command is specified, it is transferred to the drive
with the GO bit set. The GO bit creates a GO
CLR, which directs-sets the BUSY flip-flop. Normal completion of a data transfer operation occurs
upon receipt of a clock pulse with the data input
grounded to clear BUSY. When the drive reaches
the End of Segment (EOS) with the RUN line unasserted, CSTB EOS (1) H is set. This indicates that
the RH70jMassbus transfer is complete. When
CSTC DONE H occurs (indicating completion of
the RH70jMemory data transfer), along with EOS
(1) H, the BUSY flip-flop is clocked clear, indicating termination of the data transfer. The
BUSY (0) H signal is supplied to the READ,
WRITE and WR CHECK flip-flops and clears
them.

The IPCKO - IPCK3 bits are applied to the opencollector BUSI multiplexers on logic print CSTE
(which may be read when reading the CS3 register).
The IPCKO - IPCK3 bits are also ANDed with
CST A READ (0) H to create invert signals CSTA
INVO H - CSTA INV3 H, respectively. When a
read operation (transferring data to memory) is
specified, parity should not be inverted. Consequently, the CST A READ (0) H is un asserted
(driven low) during a read operation, inhibiting the
invert signals. For any other operation, the invert
signals are enabled. During data buffer m,aintenance operation, the IPCK bits invert the parity
bits generated when moving data through the
RSDB.

CSTD CLR L, which is a function of initializing the RH70, power up, etc.

CSTB MXF L, which is an error condition in the CS2 register, indicating that
the hardware failed or that the data
transfer did not complete in the normal
manner. This error condition forces termination by direct-clearing the BUSY
flip-flop.

6.19.7 Unit Select Bits and Program Clear (PG
CLR)
The Unit Select bits are three bits which specify
one of eight drives. They are located in bits 0 -- 3 of
the CS2 register and drive the Drive Select
(DSOO-DS03) lines on the Massbus. The unit to be
selected is specified by aCTD 000 IN H - BCTD
003 IN H from the Unibus. The Unit Select bits
are clocked by BCTA CS2 IN L, BCTA LO BYTE
H, and BCTB REG STR. These signals are ANOed in AND gate E54-pin 8. The output of the
gate, in addition to clocking the Unit Select bits,
also asserts CST A PG CLR L if BCTD 005 IN H
is asserted. 005 IN H is asserted when the program
writes a 1 in bit 5 (CLR) of the CS2 register. The
PG CLR signal clears the RH70 and the associated
drives.

CSTA FCTN LOAD (1) Hand CSTB
NED H. These two signals are asserted
when a data transfer command is attempted to be loaded into a non-existent
device. Since there will be no response
from the device, the data transfer is terminated by direct-clearing the BUSY
flip-flop.

6.19.8 PAT Bit
The Parity Test (CSTA PAT H) bit controls the
parity generator between the RG and OBUF registers in the data buffer (see logic diagram MlDPE)
and inverts parity associated with Massbus data. Inverting the PAT bit during a write operation will
convert odd (correct) parity to even (wrong) parity

The BUSY flip-flop is also direct-cleared under the
following conditions:

6-36

block. If RUN is unasserted, the data transfer operation is terminated. The transfer of data to or from
the drive is accomplished by drive-generated SCLK
signals. In a read or write-check operation, the
drive provides a data word on the Massbus, on the
leading edge of SCLK, and the RH70 strobes the
data in its buffer on the trailing edge of SCLK. In
a write operation, the RH70 places a data word on
the Massbus, on the trailing edge of SCLK and the
drive strobes it into its buffer on the leading edge
of SCLK. The SCLK signal from the drive to the
RH70 is rerouted back to the drive as a WRITE
CLK signal. WRITE CLK is used during a write
operation to cause the drive to clock the data from
the Massbus into its buffer.

to allow exercising of the drive's parity checking circuits. Inverting the PAT bit during a read or writecheck operation will convert odd parity to even parity to allow the exercising of the RH70 parity checking network. The PAT bit is clocked by the same
signals which clock the Unit Select bits.
The PAT bit also controls the generation of the parity bit associated with the control lines on the Massbus. When PAT is set, even (wrong) parity is sent
along with the data over the control data lines
when writing a remote register. During data buffer
maintenance operation, the PAT bit will invert the
parity checking for data words bubbling from the
RG register to OBUF.
6.19.9 Bus Address Increment Inhibit Flip-Flop
The Bus Address Increment Inhibit (BAI) flip-flop,
when set, inhibits the incrementing of the bus address. The BAI flip-flop is clocked by BCTA CS2
IN L, BCT A LO BYTE H, and BCTB REG STR
H, which are ANDed in AND gate E54-pin 8. The
RH70 must be in the ROY state (not performing a
data transfer command) in order for the BAI flipflop to be clocked. This ensures that the BAI flipflop will not change state during the middle of a
memory transfer, which could cause a spike on the
address lines. BAI is loaded from data bit 003 on
the Unibus and is cleared by the general-purpose
CSTD CLR L signal (INIT, DC LO, or Program
Clear-bit 5 of CS2).

At the trailing edge of SCLK, a 50-ns pulse, called
DRIVE CLK, is generated unless drive word count
overflow or an error condition occurs. This pulse indicates that the RH70 is going to receive or change
data.
6.20.1.1 RUN Flip-Flop - The RUN line is asserted on the Massbus as a result of setting the
RUN flip-flop. This flip-flop is set under any of the
following conditions:
1.

6.20 LOGIC DIAGRAM CSTB
This diagram contains the Massbus control logic,
the interrupt logic, and the various error
conditions.
6.20.1 Massbus Control Logic
To effectively understand the Massbus control
logic, the following signals are reviewed. When
transferring data to the drive (write operation), the
RUN line is asserted on the Massbus, provided
that the required number of words are in the data
buffer (four memory cycles). When transferring
data from the drive (read or write check operations), the RUN line on the Massbus is asserted
immediately, indicating that the RH70 is prepared
to receive data from the drive.
At the end of each logical block of data transferred
to or from the drive, the drive asserts an EBL
(End-of-Block) pulse. At the trailing edge of EBL
the drive monitors the R UN line. If it is asserted, it
will continue a data transfer of the next logical

6-37

When a write operation is specified, a
word is in OBUF and the required number of words are stored in the data buffer. The CSTA WRITE (1) H signal
denotes that a write command has been
loaded, the MDPD OBUF FULL (1) H
flip-flop sets when a data word is in
OBUF, and CSTE START H is asserted
when four memory cycles have taken
place. Four memory cycles could mean
as few as four words in the data buffer
(four single-word transfers) or as many
as eight words (four double-word transfers). Typically, the data buffer is designed for double-word operation and
will contain seven or eight data words.
For example, if the first word to be
transferred is on a single-word boundary, one word would be transferred on
the first memory cycle and double words
are then transferred, resulting in a data
buffer containing seven words. CSTE
START H, CSTA WRITE (1) H, and
MDPD OBUF FULL (1) Hare ANDed
in gate E40-pin 6 and clock the RUN
flip-flop set, which asserts CSTB RUN
H at the output of Inverter E43-pin 10.

When a read [CSTA READ (1) L] or
write-check [CST A WR CHECK (1) L]
operation is specified, the RUN flip-flop
is clocked set immediately, indicating
that the RH70 is prepared to accept
data.

6.20.1.2 End of Segment (EOS) Flip-Flop -- Tht~
drive monitors the RUN line at the trailing edge of
EBL and if the RUN line is unasserted, the driv(~
will stop transferring data. The RH70 also detects
this condition and when detected, the CSTB EOS
flip-flop is set. Note that the RUN signal is applied
to the D input of EOS. The EBL pulse is applied to
the clock input of the flip-flop. The positive.. going
trailing edge of EBL sets the flip-flop if RUN is
unasserted. The setting of EOS indicates termi·
nation of the Massbus data transfer. CSTB EOS (1)
H is ANDed with CSTC DONE H, indicating ter··
mination of the RH70/Memory data transfers.
These conditions clear BUSY, which denotes that
the data transfer is completed on the Massbus and
on the Memory bus. The EOS flip-flop is cleared
by the general-purpose CLR signal, or by GO
CLR, which is asserted when a data transfer command has been loaded in the drive.

If an error is detected in the RH70 before the ST ART signal is asserted, the
Transfer Error (TRE) condition clocks
the RUN flip-flop set and forces the
R UN line asserted, which allows the
drive to normally end the command
execution.

The RUN flip-flop is cleared under the following
conditions:
1.

The TRE condition is applied to the set
input of the DIS SCLK flip-flop. The
clock input to this flip-flop is the SYNC
CLK signal. When SYNC CLK is asserted, DIS SCLK is set, which disables
SYN C CLK signals and causes the
R UN flip-flop to be direct-cleared,
which in turn negates CSTB RUN H.

When the drive detects an error, it asserts the EXC (Exception) line. This signal is ANDed with EBL and causes the
CSTB EXC SAVE flip-flop to set. CSTB
EXC SAVE (1) direct-clears the RUN
flip-flop via gate E25-pin 12.

When the required number of words
have been transferred on the Massbus,
the drive word count overflow [A WRE
DRWC OFLO (1) L] flip-flop is set,
which direct-clears the RUN flip-flop.

When the RH70 is not busy [CST A
BUSY (0) L], the RUN flip-flop is direct-cleared. The conditions under which
the BUSY flip-flop are cleared are:

When the RH70 attempts to load at
data transfer command into 2l non··
existent drive.

6.20.1.3

Disable Sync Clock (DIS SCLK) Fllp-Flop

- When the DIS SCLK flip-flop is set, it indicate:~
that the data transfer has been completed or that
an error condition has occurred, in which case, it is
desired to inhibit SYNC CLKs and to terminatl~
the transfer. A Data Late (DLT) condition causes
DIS SCLK to be direct-set since the DLT condition
is detected at the time of SYNC CLK. It is therefore necessary to immediately set DIS SCLK. DIS
SCLK can also be set by a transfer error [CSTB
TRE (1) L] or by drive word count overflow
[A WRE DRWC OFLO (1) L]. These signals are
ORed in E45-pin 8 and applied to the D input of
DIS SCLK. The CSTB SYNC CLK signal is applied to the clock input and the leading edge of
SYNC CLK sets DIS SCLK if either condition is
present. DIS SCLK is cleared by the general-purpose CLR signal, or by the GO CLR signal, which
is asserted when a data transfer command has been
loaded into the drive.

6.20.1.4 DRIVE CLK Signal - The DRIVE CLK
a.

Normal data transfer termination.
CSTB EOS (1) Hand CSTC
DONE H are asserted.

General-purpose
(CSTD CLR H).

Missed transfer error occurs.

clear

signal is a 50-ns pulse used by the RH70 and is initiated on the trailing edge of SYNC CLK. The circuitry that generates it is Driver E22-pin 8, 50-ns
delay line DL2, and Receiver El7-pin 13. To understand the operation, assume that DIS SCLK (0) II
is asserted and the MBSA SYNC CLK H signal is
present. These conditions turn Driver E22 on. The
low output of the driver is applied to the delay lim~.

signal

6-38

The DRIVE CLK signal, however, is not generated
since the SYNC CLK H signal inhibits pin 11 of
Receiver E 17. After a period of time, the SYNC
CLK signal is driven low by the drive. Now, the
driver is turned off and the receiver is enabled, producing CSTB DRIVE CLK H.

6.20.3 Program Error (PGE) Flip-Flop
The PGE flip-flop is set when the program attempts to load a data transfer command while a
data transfer command is already in progress.
CSTA RDY is applied to the D input of the flipflop and is un asserted when the RH70 is not ready
(in the busy state). The CST A GO H signal is applied to the clock input, which indicates that an attempt has been made to load a data transfer
command with the GO bit set. When this occurs
with the RH70 in the busy state, PGE sets. This
causes CSTB STOP DEM L to be asserted. This signal prevents the data transfer command from being
loaded on the Massbus.

When the driver is turned off, a positive-going transition appears at its output. This transition is fed to
the receiver after 50 ns (the time required to propagate down the delay line). At this point, the receiver becomes inhibited again and the DRIVE
CLK signal becomes unasserted. This results in a
50-ns pulse initiated at the trailing edge of SYNC
CLK. If DIS SCLK (0) H is unasserted, the driver
is inhibited, which in turn inhibits the receiver,
thereby preventing generation of the DRIVE CLK
signal.

The PGE flip-flop is cleared by the CLR ERR signal as a result of Unibus INIT, Power Fail, loading
a 1 in bit 5 (CLR) of the CS2 register, or posting a
1 in bit 14 (TRE) of the CS 1 register. PGE is bit 10
in the CS2 register.

6.20.1.5 Zero Filling the Sector or Record - During a write operation, it is necessary to gate the
data from OBUF onto the Massbus data lines. This
is accomplished by the CSTB G ATE SYNCD H
signal. If an error condition [CSTB DIS SCLK (1)
L] occurs, or if drive word count overflow [A WRE
DRWC OFLO (1) L] occurs before the end of a
segment (disks) or a record (magtapes), the rest of
the segment or record is filled with zeros. This is accomplished by clearing the OBUF register at the
trailing edge of SYNC CLK when either of these
conditions exist. The logic that accomplishes this is
gates E39-pin 11 and E40-pin 8.

6.20.4 Missed Transfer (MXF) Latch
When a command is loaded into the drive and the
drive recognizes this command as one that it implements, it sends an OCC (Occupied) signal to the
RH70. This signal remains asserted until the last
EBL pulse, or until an EBL pulse with the RUN
line unasserted is received. When the RH70 becomes busy, CSTB RDY L becomes unasserted,
providing a high level on pin 10 of 650 /-lS one-shot
multivibrator E27. With no SYNC CLK signal applied, pin 9 of the one-shot is low. These conditions
fire the one-shot and it begins to time-out for 650
/-lS. However, when the RH70 loaded a command
into the dri:ve and the drive recognized the command, it returned OCC. This signal is applied to
the one-shot to terminate it and is also applied to
the CSTB set MXF flip-flop, keeping it directcleared. In this case, no MXF (missed transfer) condition occurs. If the drive did not respond with the
OCC signal, the one-shot would time-out. After
650/-ls, the positive-going transition from the 0 output of the one-shot is applied to the SET MXF
flip-flop. Since this flip-flop is not held directcleared by OCC, it sets and causes CSTB MXF H
to be asserted. This signal is applied to the TRE
flip-flop via gate E20-pin 8, causing TRE (Transfer
Error) to be raised (bit 14 of the CS 1 register). This
operation describes the time-out feature associated
with the initiation of a data transfer command.

6.20.2 Non-Existent Drive (NED) Flip-Flop
When the program reads or writes a remote register, the RH70 asserts Demand on the Massbus.
Within 1.5 /-lS, the drive should respond with TRA
(transfer). If not, a 1.5 /-lS one-shot multivibrator
times out and asserts BCTB SET NED L. This signal is fed to a latch which generates CSTB NED H,
indicating that a non-existent drive has been accessed. CSTB NED H is applied to the clock input
of the TRE flip-flop via gate E20-pin 8 and clocks
TRE set, indicating that a transfer error has
occurred.
NED is cleared by the CSTB CLR ERR B L signal
which is a result of Unibus INIT, Power Fail, setting bit 5 (CLR) in the CS2 register, or posting a 1
in bit 14 (TRE) of the CSI register (error clear).
NED is bit 12 in the CS2 register.

6-39

A similar time-out feature is present during the
completion of a data transfer command and is implemented as follows. Assume that the RH70 has
loaded a command, the drive has recognized the
command and has returned the acc signal, which
remains asserted throughout the transfer. When the
drive completes the transfer and reaches the last
EBL (or EBL with the RUN line un asserted), it removes the OCC signal from the' Massbus, thus removing the direct-clear from the one-shot and the
SET MXF flip-flop. Since the inputs to the 650 jlS
one-shot are sti1l enabled (low on pin 9, high on
pin 10), the one-shot begins to time-out again. If
the BUSY flip-flop is not cleared within 650 jlS of
the removal of acc, the one-shot times-out and
the positive-going transition at the output sets the
SET MXF flip-flop. If the BUSY flip-flop is
cleared within 650 jlS of the removal of acc, the
one-shot is cleared and the SET MXF flip-flop is
prevented from setting. MXF is bit 9 in the CS2
register.

6.20.5 Data Late (DLT SYNC) Flip-Flop
The Data Late synchronizing flip-flop provides for
synchronization of data late conditions - i.e., to prevent clocking of data late conditions just as they occur. The DLT SYNC flip-flop causes the data late
condition to settle for the width of Drive Clock. At
the end of Drive Clock, the DLT SYNC flip-flop is
sampled to see if a DLT condition has occurred. If
it has, the DLT flip-flop is set.

The DLT SYNC and DLT flip-flops are cleared by
the general-purpose CSTB CLR ERR L signal.
D LT is bit 15 of the CS2 register.
6.20.6 Exception Save (EX C SAVE) Flip-Flop
When the drive is doing a data transfer and has detected an error, it raises the Exception (EXC) line
on the Massbus. The RH70 sets the EXC SAVE
flip-flop at EBL time. MBSB EBL Hand MBSB
EXCP Hare ANDed in gate E41-pin 3 and dock
the EXC SAVE flip-flop set.

A Data Late condition can occur as a result of the
following:
1.

During a write operation, where data is
transferred from the OBUF register in
the RH70 to the drive, a word must be
available for transfer to OBUF from the
RG register when the present word in
OBUF is transferred to the drive. This
information is implemented by MDPD
RG RDY (0) H. Consequently, during a
write operation [CSTA WRITE (1) H],
if RG RDY (0) H is asserted (indicating
a data word is not available for transfer
to aBUF), the DLT flip-flop is set on
the trailing edge of Drive Clock. In the
case where the word in OBUF is the last
word to be transferred, RD RDY (0) H
will be asserted since there are no more
words to transfer. Consequently, AVIRE
DRWC OFLO (0) H becomes Ulnasserted, indicating that all words have
been transferred onto the Massbus. This
signal inhibits gate E50-pin 6 from setting the DLT SYNC flip-flop.

During a write or write-check operation, CSTA
WRITE (1) L or CST A WR CHK (1) L, respectively, is asserted. Either signal is ANDed with
EXC SAVE in gate E46-pin 11 to yield the Exception Error condition (CSTB EXC ERR L). The error condition is asserted immediately in the write or
write-check operation.

During a read or write-check operation
(when reading data from the drive), the
drive attempts to put a word in the
RH70 while a word is already stored
where the data is to be transferred. In
the case of Read or Write-Check commands (CST A RD + WR CLK H), the
words from the drive are transferred to
RE and a Data Late condition occurs
when the drive attempts to put a word
in RE when RE is already full (MDPE
REG FULL H). With these two conditions present, the DLT flip-flop is set on
the trailing edge of DRIVE CLK.

In a read operation, it is necessary to wait until the
data buffer is emptied before the EXC ERR condition is asserted. This ensures that all good data in
the data buffer, including the word which caused
the posting of the error, has been transferred to
memory. The signals that implement this. are

6-40

MDPD DB EMPTY Land CSTB EXC SAVE,
which are ANDed in gate E46-pin 11. When the
CSTB EXCP ERR L signal is asserted, the transfer
error (TRE-bit 14 in CS 1) flip-flop is set.

MCPE (Massbus Control Bus Parity Error). The
SC bit will cause an interrupt if the Interrupt Enable (IE) bit is set.

6.20.7 Read Exception Circuitry
If a drive detects an error during a data transfer
read operation, CST A READ (l) Hand CSTB
EX C SAVE are asserted and yield CSTB READ
EXCP H via AND gate E35-pin 8. READ EXCP
controls the double-word logic shown on logic diagram A WRA. This is to force a single-word memory operation if only one word is in the data buffer
(MDPD LAST WORD), the drive will not send
more words (due to the Exception Error), and the
RH70 is waiting to assemble a double word.

6.20.10 Interrupt Logic
The Interrupt Request logic, when enabled, causes
CSTB INTR REQ L to be asserted. This signal is
applied to the logic on logic diagram BCTC and initiates an interrupt to the CPU over the Unibus.
An interrupt may be generated in one of the following ways:
1.

A programmed interrupt which occurs
by writing Is into the IE and RDY bit
positions of the CS 1 register (bits 6 and
7, respectively). This is implemented by
gate E52-pin 8 which direct-sets the
INTR flip-flop. The CSTA CLK CSI
LO signal enables the low byte of the
CS 1 register.

Successful completion of a data transfer
command. When the RH70 goes from
busy to the ready state, CST A RDY H
clocks the INTR flip-flop.

A Special Condition (SC) which occurs
as a result of the assertion of SC when
IE (Interrupt Enable) is set with the
RDY bit asserted (RH70 not busy). If
the RH70 is busy, it is inhibited from
causing an interrupt until the control is
back into the Ready state. This logic is
implemented in NAND gate E44-pin 6.
In order to set the INTR flip-flop, the
IE flip-flop must set. This flip-flop is set
as a result of loading bit 6 from the low
byte of the CS 1 or CS3 registers during
register strobe. The gating for this is
shown at the input to the IE flip-flop.

6.20.8 Transfer Error (TRE) Flip-Flop
The TRE flip-flop summarizes all RH70 and all
drive error conditions. The RH70 error conditions
are:
Write-check error - MDPE WCE H
Parity error - CSTC PE H
Data Late - CSTB DLT (1) L
N on-existent drive - CSTB NED L
N on-existent memory - CSTC NEM (l) L
Programming Error - CSTB PGE (1) L
Missed transfer - CSTB MXF (1) L
Massbus data bus
Parity error - MDPE (1) L
The drive error condition is reported as an exception error (CSTB EXCP ERR L). The TRE error
conditions are summarized in the Special Conditions (SC-bit 15 of CSl) bit. The TRE flip-flop is
cleared by the CSTB CLR ERR L signal which is
asserted as a result of CSTD CLR . GO CLR L
(see logic diagram CSTD) or by loading a 1 in the
TRE bit position of the CS 1 register. The gating
for clearing TRE in this instance is CSTA CS 1 IN
H, BCT A HI BYTE H, BCTB REG STR H, and
BCTD D 14 IN H, which are ANDed in gates E59pin 8 and E52-pin 12.

The IE and the INTR flip-flops are
cleared by BCTC INTR DONE H or by
CSTD CLR H. The INTR DONE signal
indicates that the CPU has recognized
the interrupt and has accepted the interrupt vector. The IE and INTR flip-flops
are cleared by INTR DONE to prevent
further interrupts during the interrupt
service routine.

6.20.9 Special Conditions (CSTB SC H)
All conditions requiring action by the CPU are summarized in the Special Conditions (SC bit 15 in
CS 1) bit. This is accomplished by gate E44-pin 8
which ORs TRE (Transfer Error), ATTN (Attention condition from a drive on the Massbus), or

6-41

6.21 LOGIC DIAGRAM CSTC
This logic diagram contains the memory cycle control logic and memory cycle error logic, including
data parity error, address parity error, and non-existent memory.

START MEM

REQ ClK

ClR SMC H

6.21.1 Memory Cycle Control Logic
The memory cycle is divided into three states: a
Start Memory Cycle (SMC), a Request (REQ), and
a Cycle-in-Progress (CIP). Initially, the memory
cycle is started by MDPA START MEM H which
occurs when the data in RAjRB is transferred to
RC JRD (Figure 6-9). This signal clocks the SMC
flip-flop, which sets to indicate that the RH70 is
ready to make a memory request. The SMC flipflop must be set in order for the RH70 to send a
memory request to Cache.

SMC (1) H

----------'--------"'"--------

'---------

REQ (IlH

CIP (1)H
-WRITE OR WRITE CHECKyL
DATA READY
-READ
ADRS ACKN
11-2965

Figure 6-9 Memory Cycle Simplified
Timing Diagram

Approximately 100 ns after SMC is clocked,
MDPA REQ CLK H is generated via the delay line
on the data buffer module. This signal clocks the
REQ flip-flop set, indicating that a memory request
is issued to Cache. The memory request is designated CSTC CNTLX REQ L. (As previously described, the X in the signal name designates one of
four controllers.) The reset output of the REQ flipflop is applied to the direct-set input of the CIP
flip-flop and sets it. The setting of this flip-flop indicates that a memory cycle has been initiated. The
elP flip-flop remains set until the transfer is completed. Approximately 50 ns after REQ is set, the
SMC flip-flop is reset by the MDPA CLR SMC H
signal.

This allows the SMC flip-flop to synchronize these
conditions. If one of these conditions has been asserted for 50 ns and the memory cycle has not belen
started [SMC (0)], CSTC DONE H will be asserted
(if the memory cycle has been started) one more
memory cycle is accomplished before CSTC DONE
can be asserted (see gate El7-pin 3 and gate E35pin 6). When DONE is asserted, it indical:es that
the data transfer command has completed on the
RH70jCache Interface.
The SMC flip-flop is direct-cleared by the generalpurpose CSTD CLR . GO CLR signal, or by
MDPA CLR SMC H. CLR SMC occurs at the end
of REQ CLK and is a 25-ns pUlse. REQ CLK is a
50-ns pulse occurring at the end of SMC, which is
a 100-ns pulse.

For a read operation (words written into memory),
the memory cycle is completed when the Cache returns Address Acknowledge (CCBE MBC ADRS
ACKN L). For write or write-check operations, the
memory cycle is completed upon receipt of the
Data Ready (CDPK DATA ROY CNTLX H) signal from Cache.

6.21.1.2 REQ Flip-Flop - The REQ flip-flop s~:ts
when the RH70 is ready to perform a memory
request and indicates that the RH70 requests use of
Cache. SMC must be set in order for REQ to SC!t.
With SMC in the reset state, the 0 input to REQ is
held low. Once REQ is set, CSTC CNTLX REQ L
is issued to Cache. The RH70 now waits for Cache
to acknowledge the request. When Cache acknowledges the request with CCBE REQ ACKN, this signal is ANDed with COP] SELADRS CNTLX H
to assert A WRD REQ ACKN H (sl!e logic diagram AWRD). AWRD REQ ACKN H then direct-clears the REQ flip-flop.

6.21.1.1 SMC Flip-Flop - The SMC flip-flop is
clocked at MD PA ST ART MEM H time. This signal is a timing pulse from the delay lines which
clocks the data from RAjRB into RCjRD. The
SMC flip-flop is set if there is no error [CSTB TRE
(1) Lj, no word count overflow [A WRE WC
OFLO (1) L], or no program clear or initialize operation [CSTD PG CLR + INIT (1) L] in progress.
The three signals are ORed into the 0 input of the
SMC flip-flop and are also fed through a 50-ns delay line.

6-42

NOTE
If the 650 microsecond transfer error one-shot times
out due to a hardware failure (see logic diagram
CSTB), the time-out will clear the BUSY flip-flop,
putting the RH70 back into the RDY state. In this
case, CST A RDY B H direct-clears REQ to ensure
that the REQ flip-flop is not locked in the set state.

DATA RDY CNTLX H. This is one of the gating
signals from Cache used to generate CLK RA
AND CLK RB signals for clocking data into the
data buffer. For read operations, the CIP flip-flop
is clocked by the trailing edge of CSTC READ
DONE L. READ DONE is asserted upon receipt
of CCBE MBC ADRS ACKN L from Cache during a read operation if this controller is selected.
This logic is implemented by ANDing CCBE MBC
ADRS ACKN L, CSTA READ (1) H, and CDPJ
SELDAT A CNTLX H in NAND gate E24-pin 6.
Delay line DLI converts ADRS ACKN into a 50ns pulse.

There are several conditions which hold the D input to the REQ flip-flop low, thus preventing a
memory request to Cache:
1.

CSTC SMC (0) H - if this flip-flop is
cleared, it drives the D input to REQ
low, preventing the REQ flip-flop from
setting.

NOTE
The leading edge of the READ DONE signal clears
the RC FULL and RD FULL flip-flops (see logic diagram MDPA) to allow new data to be sequenced into
RC and RD.

If there is a data parity error associated
with the odd word or the even word, the
D input to REQ is driven low (see pins
9 and 3 of AND-OR gate E38-pin 8).

When the RH70 is in the data buffer
maintenance mode of operation, memory requests are inhibited by the assertion of CSTB RDY L.

If a write-check error occurs, further
memory requests are inhibited as a result
of MDPE WCE H being asserted.

The CIP flip-flop is direct-cleared due to:

In a write or write-check operation, the timing to
perform the memory cycle is a REQ CLK signal
from the data buffer when data is clocked from
RAjRB into RCjRD. However, for the first word
transferred there is no REQ CLK signal. Consequently, when a data transfer command is loaded
and a non-existent device has not been addressed,
45-ns one-shot E27 is triggered which asserts CSTC
FST REQ (first request). This signal is applied to
the direct-set input of the REQ flip-flop to force
the flip-flop set for the first memory cycle.
6.21.1.3 CIP Flip-Flop - When the REQ flip-flop
sets, the low-level 0 output direct-sets the elP flipflop, indicating that a memory cycle has started.
The CIP flip-flop remains set for the rest of the
memory cycle. The CIP flip-flop is used to indicate
a DONE (CSTC DONE H) condition after the last
memory cycle has completed.

Address Parity Error [CSTC APE (1) L]
on the memory address and control
lines. In this error, the RH70 does not receive any timing signals from Cache so
the CIP flip-flop must be direct-cleared.

Addressing Non-Existent Memory
[CSTC NEM (1) L]. When this condition occurs, there are no timing signals
from Cache so the CIP flip-flop must be
direct-cleared.

RH70 going to Ready State (CSTB
RDY L). If the 650 J.lS Missed Transfer
error one-shot times-out due to a hardware failure, the BUSY flip-flop is
cleared, forcing the RH70 back into the
Ready state. This ensures that the REQ
and CIP flip-flops are cleared so that
they are not latched in the set state.

6.21.2 Data Parity Error
The data parity error logic contains two flip-flops
and associated gating. One flip-flop is designated
DPE OW (Data Parity Error - Odd Word) and is
used during write or write-check operations to detect a parity error on the odd data word. The second flip-flop is designated DPE EW (Data Parity
Error - Even Word) and is used during write or
write-check operations to detect a parity error on
the even data word.

For write or write-check operations, the CIP flipflop is clocked clear on the trailing edge of CDPK

6-43

sends address and control information to Cache~,
Cache computes parity and transfers the address~.
control, and parity to memory. Memory performs a
parity check, and if a parity error is detected, sends,
a signal to Cache, which in turn causes Cache to assert the ADML ADRS PAR ERR H signal 1:0 the:
RH70.

If a single-word operation is specified, one of two
enable signals is asserted. When an odd data word
is being transferred during a write or write-check
operation, MDPC EN OWPCK (Enable Odd Word
Parity Check) is asserted. If one of the odd word
parity bits, high byte or low byte (MDPC OWHB
PAB H or MDPC OWLB PAB H) is raised (denoting an odd word parity error), the data input to the
DPE OW flip-flop is asserted. At REQ CLK time,
the: flip-flop is clocked set, indicating an odd word
high byte or odd word low byte parity error.

Cache also sends a CCBD MBC TIMEOUT 1-1 signal which is applied to both the APE and NEM
flip-flops. Since the TIMEOUT signal is apphed to
all four controllers, it is ANDed in gate E35-pin 3
with the proper controller select signal (COP] SELDA T A CNTLX H). If the time-out occurs dlli~ to a
non-existent memory, the NEM flip-flop is set and
the APE flip-flop remains cleared. If a time-out occurs due to an address parity error, the APE flipflop is set and the NEM flip-flop is inhibited from
setting.

When an even data word is being transferred during a write or write-check operation, MDPe EN
EWPCK (Enable Even Word Parity Check) is asserted. If one of the even word parity bits (MDPC
EWHB PAB H or MDPC EWLB PAB H) is raised
(denoting an even word parity error), the data input to the DPE EW flip-flop is asserted. At REQ
CLK TIME, the flip-flop is clocked set, indicating
an even word low byte or high byte parity error.

The APE error condition is bit 15 of the CS3 register and is ORed in gate E24-pin 12 to cause a parity error (PE bit 13 of CS2 register). The :\J"EM
error condition is bit 11 of the CS2 register. Both
the APE and NEM flip-flops are cleared by the
CSTB CLR ERR B L signal.

If double-word operation is specified, all four parity bits are monitored and both enable signals
(MDPA EN OWPCK Hand MDPA EN EWPCK
H) are asserted. If any of the four parity bits is asserted high, it indicates a parity error and will
cause either or both of the data parity error flipflops to set, depending on the parity bit(s) asserted.
When a parity error is detected, the output of
AND-OR gate E38-pin 8 is driven low, which prevents the data input of the REQ flip-flop from
being enabled, thus preventing further memory cycles from occurring. The DPE OW and DPE EW
error conditions are indicated in bits 14 and 13 of
the CS3 register and are ORed together in gate
E24-pin 12 to cause a parity error (PE bit 13 of
CS2 register). The data parity error flip-flops are
cleared by the CSTB CLR ERR B L signal.

6.22 LOGIC DIAGRAM CSTD
This logic diagram contains the BUSI multiplexers
for the CS 1 and CS2 registers, and the clear logic
used to store INIT or Program Clear conditions if
they occur during a memory cycle.
6.22.1 BUSI Multiplexers (CS 1, CS2)
The BUSI multiplexers consist of four open-collector 8234 multiplexers used to gate out data from
the CS 1 and the CS2 registers when the program
reads those registers.
BCTA CSI OUT L, when asserted, enables the AO
- A3 (containing CS 1 data) inputs to the multiplexer. BCTA CS2 OUT L enables the BO - B3
(containing CS2 data) to the multiplexer. The BUSI
outputs are applied to the Unibus as BUS DO L D15 L.

6.21.3 Address Parity Error (APE), Non-Existent
Memory (NEM) Flip-Flops
The APE flip-flop is asserted when memory detects
a parity error on the parity generated by Cache for
RH70 address and control information. The RH70

6-44

6.22.2 INIT and Program Clear (PGCLR) Logic
If the programmer sets a 1 in the CLR bit position
of the CS2 register, or if an INIT on the Unibus is
raised due to a Reset instruction, the CSTD
INIT.PGCLR flip-flop sets. This flip-flop stores the
INIT or PGCLR condition in order to allow any
memory cycle which might be in progress to complete, and to then prevent the next memory cycle
from occuring. The CSTD PGCLR.INIT (0) signal
from the flip-flop is applied to 50-ns delay line DL3
(see logic diagram CSTC) which causes CSTC
DONE H to be asserted at the completion of any
memory cycle in progress. This signal, coupled with
the CSTD PGCLR.INIT signal, fires 400-ns oneshot E37-pin 4, causing CSTD CLR Land CSTD
CLR H signals to be generated. These signals clear
the RH70 and the associated drive. If the RH70 is
in the RDY state and an INIT or PG CLR is asserted, 400-ns one-shot E37-pin 4 is fired immediately (due to RDY enabling pin 1 of E37), which
causes the CSTD CLR Land CSTD CLR H signals to be generated.
The CSTD CLR L signal is also applied to discrete
element Ql, resistor R15 and capacitor C67 to provide a small delay before clearing the CSTD
PGCLR.INIT flip-flop.
If the RH70 is currently performing a memory
cycle, the CST A RDY B Hand CSTC DONE H
signals (both being unasserted) prevent the 400-ns
one-shot from firing. When the memory cycle completes and DONE is asserted, or the RH70 goes to
the Ready State, it will clear the RH70 and drive
when an IN IT or PGCLR condition occurs. A second 400-ns one-shot is shown (E37-pin 12). The
function of this one-shot is to extend the period of
the CST A GO CLR pulse. GO CLR is asserted
when a data transfer command is loaded in the
drive. The output of the one-shot is ORed in NOR
gate E32-pin 6 with BCTC DC LO L and the
INIT.PGCLR output of one-shot E37-pin 4. The assertion of any of these signals asserts CSTD DB
INIT L which initializes the data buffer logic (see
logic diagram MDPA-MDP1).

6.23 LOGIC DIAGRAM CSTE
This logic diagram contains the BUSI multiplexers
for· the data buffer and CS3 registers and the Start
logic used to initiate Massbus cycles during write
operations.
6.23.1

BUSI Multiplexers (DB, CS3)

B~TA CS3 OUT L, when asserted, enables the AO

- A3 inputs (containing data from the CS3 register)
to the mUltiplexers. BCT A DB OUT L, when asserted, enables the BO - B3 inputs to the multiplexers. These inputs contain data from OBUF in
the data buffer. DB OUT L is asserted when the
program attempts to read the data buffer during
data buffer maintenance operation. The outputs of
the multiplexers are supplied to the Unibus as
BUSI DOO OUT L - BUSI DI5 OUT L.

6.23.2 Four Counter
The four-count circuit counts memory cycles. After
four counts, a carry is obtained which causes CSTE
START H to be aserted. In the event that fewer
than four memory cycles are to occur, AWRE WC
OFLO (1) L is set, which also causes CSTE
ST ART H to be asserted. The START signal will
cause the R UN line on the Massbus to be asserted.
When the four counter overflows, the R3 output is
fed back to the CUP (Countup) input via NAND
gate E7-pin 8 to prevent the counter from counting
higher than four.
The counter is loaded with the 2's complement of
four (1100) when the CST A GO CLR L signal is asserted. This signal is asserted when a data transfer
command is loaded in the drive.
When the counter reaches a count of four, it indicates that four memory transfers have been initiated. This may mean that as many as eight data
words are in the data buffer if all the transfers were
double words. Typically, there will be eight words
or seven words (allowing one single-word transfer)
to put the next memory address on a double-word
boundary.

6.24 M5904 MASSBUS TRANSCEIVER MBSA,
MBSB, MBSC
The Massbus consists of three Massbus cables and
associated Massbus transceiver modules. A 40-pin
connector on each M5904 Massbus Transceiver
module connects the transceivers to the Massbus
cables.

THE CST A GO CLR L signal, in addition to being
supplied to the 400-ns one-shot, is ORed in OR
gate E4-pin 8 with the BCTC DC LO Land BCTC
INIT .PGCLR to yield CSTD CLR.GO CLR L,
which clears certain error and control bits in the
RH70.

6-45

The signals sent from the drive to the Massbus are:
SYNC DOO - SYNC D17, which represent synchro··
nous data, and COO H - C15 H, which represent
the contents of a drive register. Control signals
which include EXCP, EBL, ATTN, SYNC CLK"
CPA IN, OCC and TRA are also shown.

Each signal on the Massbus is applied to a differential driver circuit (75113) which transmits the true
signal and an inversion of the signal along the bus.
At the other end of the bus, the signals are received
by differential receivers (751 07B) which output the
true form of the signal. The differential circuitry
serves to eliminate noise, since any common mode
noise will be cancelled at the differential receivers.
For additional description, refer to the M5904
Massbus Transceiver module description in this
chapter.

6.25 M5904
MASSBUS
TRANSCE1[VER
MODULE
The M5904 Massbus Transceiver module contains
nine differential driver chips (75113) and seve:n dif.·
ferential receiver chips (75107B). Each driver chip
and each receiver chip is capable of carrying two
signals. Thus, the chips can be designated dual driv ..
ers and dual differential receivers. The transmission
line connected to the transceivers are bidirectional
in that they can both receive and transmit informa ..
tion. This is illustrated for one signal line in Figum
6-10.

The three Massbus cables are designated Massbus
Cable A, Massbus Cable B, and Massbus Cable C
(sheets 1,2,3 of drawing D-BS-RH70-0-1).
The M5904 Massbus Transceiver is functionally
shown with the dotted block on each block schematic. The 40-pin connector is shown in the center
of the dotted block. The differential transmitters
which drive signals onto the Massbus from the
RH70 are shown to the left of the connector. These
signals originate at the drive and are routed to the
RH70 via the differential receivers.

+2.~J1.

To minimize switching of signals on any transceiver
module at a given time, the signals are grouped on
different modules. For example, OBUF 00-05 H is
contained on MBSA, OBUF 06-11 H is contained
on MBSB and OBUF 12-15 H is contained on
MBSC. The DOO IN H - D15 IN H signals from
BUSA are also divided on the three module~ in a
similar manner. The RSEL 0 H - RSEL 4 H signals are grouped on MBSA and MBSB.

DRIVER
(1/2 OF 75113)

~:}
RECEIVER
(1/2 OF 751078)

PART OF M5904
11-2347

The OBUF signals are gated by GATE SYNCD H,
which enables the output of OBUF to be gated
onto the MASS "D" lines of the Massbus. The
DOO IN H - D 15 IN H signals, which form the
MASS "C" lines are enabled by BCTB GATE
CNTL H, which occurs when the RH70 is writing a
remote register. GATE CNTL H is the assertion of
BCTA DEV SEL Hand BCTA CTOD H. The
RSEL signals select a drive register and are enabled
by the DEV SEL signal. Unit select signals UOO H
- V02 H are also enabled by DEV SEL and specify
one of eight possible drives. The remaining control
signals which are supplied to the drive are also
shown. These include WCLK, RUN, CTOD, CLR,
AC LO, OEMAND (1), OBUF PA, CPA OUT.

Figure 6-10 Typical Differential
Driver/Receiver Connection

The advantage of differential circuitry is that any
noise picked up is generally picked up on both thc~
inverted and non-inverted signal lines. The differential receiver takes the difference between the signals, regardless of the noise level, and the noise is
effectively cancelled out.
Each driver on the M5904 must be terminated sinct~
the M5904 is used to drive transmission lines (Fig ..
ure6-11).

6-46

Vee

6.25.1 75113 Dual Differential Driver Chip
The 75113 Tri-State Dual Differential Driver Chips
provide differential outputs with high current capability in order to drive balanced lines. The chips feature a high output impedance, making it possible to
connect many drivers on the same transmission
line. A simplified schematic of the 75113 is shown
in Figure 6-12.

82.0.

-I

1::1120ft. MAXIMUM

-,
I

I
I
: TRANSMISSION
ICABLE
I
I

+3~JL

82.0.

'_I
82.0.

82.0.

The inverting output of the driver chip is the transistor collector, while the non-inverting output is
the transistor emitter, shown at point B. When the
input is low, neither transistor conducts and line A
is biased to +2.5 V, while line B is biased to 0 V by
the terminator resistors (refer to diagram). When
the input is high, the upper transistor collector is
driven low (0 V) and the lower transistor emitter is
driven high (+2.5 V). The pin connection diagram
for the dual differential driver is shown in Figure 613.

-:I:"

11-2348

Figure 6-11

Driver Termination

The M5904 Massbus Transceiver requires input
voltages of +5 Vdc and -15 Vdc. The dual drivers
require +5 Vdc operating voltage while the dual differential receivers require +5 Vdc and -5 Vdc. The
-5 Vdc is obtained from the -15 Vdc source via a
resistor and Zener diode.

r------,

+5V

1/2 OF DRIVER CHIP
82.0.

~---,

INVERTING
OUTPUT

OFF

112 OF DRIVER

NEAR
1CHIP
END OF LINE

I
I

+5V

OFF

82n

I
II
I
II

L_,_..J

NON-INVERTING
OUTPUT

JL
82!).

82!).

L _ _ _ _ _ _ ..1
11-2352

Figure 6-12

Driver Chip Simplified Schematic

6-47

Vee +5V
INVERTED
OUTPUT
INVERTED OUTPUT
NON -INVERTED
OUT PUT
NON -INVERTED
OUTPUT

LOGIC INPUT

LOGIC INPUT
TO+3V
TO +3V

11-2350

Figure 6-13

Dual Differential Driver Pin Connection Diagram

6.25.2 75107B Dual Differential Line Receiver
Chips
The 75107B Differential Receiver Chips feature
dual independent channels with common voltage
supply and ground terminals. The circuits operate
as follows. If the voltage at pin 1 is positive with respect to the voltage at pin 2, the output at pin 4
goes positive (Figure 6-14).

+3V~~-

Figure 6-14 Simplified Line Receiver
Logic Diagram

If the voltage at pin 1 is negative with respect to
pin 2, the output at pin 4 goes negative. The pin
connection diagram for the receiver is shown in Figure 6-15.

INPUTS {

6.26 H870 TERMINATOR
The H870 B us Terminator provides a simple and reliable method of terminating the Massbus. The
Massbus is terminated by plugging H870 terminators into each M5903 transceiver module in the
last drive.

TO +3V
OR
STROBE
NC

The H870 consists of 38 82-1/4 Watt resistors
wired between each Massbus line and a common
ground connection.

TO-t-3V
OR
STROBE
NC

GROUND

VEE

OUTPUT

TO +3V
OR
STROBE

Vee

11-2351

NOTE
The H870 terminators are to be installed on the
M5903 transceiver module with the resistors facing
up.

Figure 6-15 751 07B Differential Receiv(!r
Pin Connection Diagram

6-48

CHAPTER 7
INSTALLATION AND MAINTENANCE

7.2.3 Module Locations
The 11/70 CPU mounting box houses the Floating
Point Unit, Central Processor, Memory Management, Unibus Map, Cache, 5 Small Peripheral Controller (SPC) slots, the K W 11 clock, and up to four
RH70 Controllers. The location of the respective
modules is shown in Figure 7-1.

7.1 INTRODUCTION
This chapter describes the necessary installation information required to install the RH70. The chapter also describes the preventive and corrective
maintenance procedures that apply to the RH70
when connected to a TM02/TUI6 drive. A major
point in the maintenance philosophy of this manual
is that the user understand the normal operation of
the RH70.

7.2.4 Massbus Cables
Massbus connections to the RH70 are made via
three 40-conductor ribbon cables. These cables plug
into three M5904 Transceivers in the RH70 and are
designated Massbus Cable A, Massbus Cable B,
and Massbus Cable C. The connections are made
as shown in Figure 7 -2.

This knowledge, and the maintenence information
contained in the TU16/TM02 Tape Drive System
Maintenance Manual, will assist maintenance personnel in isolating system malfunctions.

7.2 INSTALLATION
The following paragraphs describe the mechanical
and electrical installation, power checks, jumper
configurations, visual inspection, and diagnostics associated with the RH70.

The Massbus cables are marked and should be inserted with the edge-marking facing the module handles. To terminate the Massbus, three H870
Massbus Terminators, supplied with the RH70,
should be plugged into the M5903 modules located
in the last drive on the Massbus (Figure 7 -2).

7.2.1 Mechanical
The RH70 uses one hex-height module, three quadheight modules and three double-height modules
(Massbus connectors). There is no mechanical unit
to mount. The modules are merely inserted into the
appropriate slots in the 11/70 CPU box as shown
in the Module Utilization chart in Figure 7-1. The
Massbus Cables are plugged into the double-height
slots and the jumpers are configured for the proper
address and interrupt vector.

7.2.5 Jumper Configurations
The following paragraphs describe the various
jumper configurations on the BCT (M 8153) module
and on the MDP (M8150) modules.
7.2.5.1 BCT Module (M8153) - The BCT module
contains jumpers for register selection, BR level interrupt and vector address.

7.2.2 Electrical
The 11/70 CPU mounting box contains a wired
backplane that runs the full depth of the box. The
Unibus signals are prewired on the backplane.
Power to the RH70 is provided by the cabinet
power supply as follows:
+5 V@18.5 A max.
-15 V@0.5 A max

Register Selection
The RH70 is capable of responding to 32 possible
Unibus addresses. The number of addresses, however, is dependent on the Massbus device. Jumpers
W8 - W15 select the block of Unibus addresses to
which the TWU16 subsystem responds. The standard addressing block assigned is 772440 - 772476.

7-1

SPC'S

MASSBUS

MAP

CACHE

MEM. MAN.

CPU

~~~~ ~~I
44 43 42 41 40 39 38 "$] 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
U

o
U
T

M M M M M M M

M M

M M M M M

M M M

5
9

8
1
5

5
9

8
1

5
9

888

3
6

1
3

44433
32087

1
3

0
4

8
1
4
4

5
9
0

8
1
5

440

555
999

000
444

FPU

""'--~~
09 08 07 06 05 04 03 02 01

M\ ~

8
1

1
1
2

1
1

M
8
1

3
3

3
2

3
1

S
A

M
B
S
C

M
B
S
B

M
B
S
A

M M M

8
1
5
2

~ I~

S
C

S
B

M
B
S
C

M M
B B
S S
B A

M M M
B B B
S S S

P
M

N
T

A
I

M M M M

~I~I~IPI~I~

r--

I I I I~

8
1
5
1

0
P

5
3

I--

M M M

I
N

S
P
C

I--

S
A

M
8

I~ IC

U
B

T
M

P
0

A
P

c
I-K

S
P
C

1
1

r----

B
C
T

A
W
R

C
S
T

C
T

W
R

S
T

I
G

9
3

F
CNTLR

CNTLR

A
11-2942

Figure 7-1

Module Utilization Chart

(LAST DRIVE ON MASSBUS)

(BEGINNING OF MASSBUS)

RH70

I
I
I
*

DRIVE

DRIVE
M5904
SLOT
AB25*

M5904
SLOT
AB26*

M5904
SLOT
AB27*

MASSBUS
CABLE A

I
MASSBUS
CABLE B

MASSBUS
CABLE C

,..

MASSBUS
CABLE A

M5903
SLOT
AB01

M5903
SLOT
AB02

MASS BUS
CABLE B

M5903
SLOT
AB03

MASSBUS
CABLE C

((
/I

M5903*
SLOT
AB01

SLOT
1 M5903*
AB02

((

,..

M5903*
SLOT

I
I
I

AB03

H870 terminator cards plug into M5903
modules in last drive on massbus.

MASSBUS CABLE A

CONTROLLER
A
AB25

CONTROLLER
B
AB29

CONTROLLER
C
AB 33

CONTROLLER
D
AB37

MASSBUS CABLE B

AB26

AB 30

AB34

AB38

MASSBUS CABLE C

AB27

AB 31

AB 35

AB39
11-2941

Figure 7-2

Massbus Cable System Configuration

For the TWU16 subsystem, the following jumper
configuration should be used (see D-CS-M8153-0-1,
sheet 2 of 6).
Jumper In = Binary 0

ADDR.
BIT

17 16
1 1

Jumper

Jumper In/Jumper Out

12
11
10
9
8
7
6
5

W14
WIO
W9
W8
Wll
W13
W15
W12

OUT
IN
OUT
IN
OUT
IN
IN
OUT

12
1

11
10 9
010

8
1

6
0

543
1
X
X

15
1

Address Bit

14
1

13
1

7
0

to
7

7-3

The jumpers in E41 (D-CS-M8153-0-1, sheet 2 of 6)
are selected for the appropriate number of registers
in the subsystem,minus 2. For example, there are
16 registers in the TWU 16 subsystem, so the jumpers are selected for a weighted value of 16, --2 or
14, as shown below. This procedure is described in
detail in Paragraph 6.2.

7.2.5.2 MDP Module (M81S0) - The MOP module contains jumpers which allow maintenanc:e personnel to disconnect wired-OR connections from
the Exclusive-OR network used to detect writecheck errors. These jumpers are designated \VI-W4
and are shown on D-CS-M8I50-0-I, sheet 6 of 9.
The jumpers provide maintenance personnel with a
method of isolating a faulty output (stuck low) of
the wired-OR bus to one of four integrated circuit
(lC) chips which perform the Exclusive-OR function during write-check operations. For example, if
the output of the E2I and E23 open-collector line is
stuck low when scoping of the inputs indicates that
it should be high, the faulty I C (E21 or E23) I:!an he
ascertained by removing jumpers W2 and WI. If after removing the jumpers, the outputs of the Exclusive-OR gates in E23 are still low, it indicatt:s that
the E23 chip is defective. If E23 outputs are: high,
the E2I chip is defective (outputs stuck low).

Jumper In = Binary 0
Slot

Jumper

Jumper In/Jumper Out

E41

1-16
2-15
3-14
4-13
5-12 (2)
6-11 (4)
7-10 (8)
8-9 (16)

IN
IN

OUT
OUT
OUT
OUT
OUT
IN

BR Level Interrupt
The priority jumper plug for the RH70 is normally
set for the BR5 level. This plug is located in E022
(refer to D-CS-M8153-0-1, sheet 4 of 6).

7.2.6 Light-Emitting Diodes (LEDs)
The following light-emitting diodes ar,e incorporated in the RH70 Massbus Controller logil:;
on the MSI53 BCT module (Figure 7 -3).

Vector Address Jumpers
The interrupt vector transferred to the processor is
jumper-selectable via jumpers WI - W7, representing vector bits 2 - 8. The TWU16 subsystem has
been assigned a vector address of 000224. The
jumper configuration for this vector address is
shown below:

SSYN (Slave Sync) D-CS-MSI53-0-I, Sheet :3
of 6
TRA (Transfer) D-CS-MSI53-0-I, Sheet 3 of
6
BG IN (Bus Grant In) D-CS-MSI53-0-I,
Sheet 4 of 6

Jumper In = Binary I
Ve:ctor Bits

Jumper

V2
V3
V4
V5
V6
V7
V8

W7
W3
W6
W2
W5
WI
W4

SACK (Selection Acknowledge) D-CS-l\ISI530-1, Sheet 4 of 6

Jumper In/Jumper Out

BBSY (Bus Busy) D-CS-MS153-0-1, Sheet 4
of 6

OUT
IN

OUT
OUT

These LEOs are provided to aid maintenanc:e personnel in isolating system faults as described below:

OUT
1.

V8
0

V7
1

V6
0

V4
1

V3
0

V2
1

VI
0

VO
0

7-4

Unibus on PDP-II/70 is in "hung" condition (no operations can be performed
on Unibus).

This condition may be caused by:

illuminate. If this LED is brightly illuminated, it indicates that the Unibus BG
IN signal coming to that device is stuck
high.

Stuck SACK
Stuck BBSY or
Stuck SSYN

3.
The associated LED will be continuously
illuminated. LEDs may flicker intermittently during normal operations.

Processor attempts to read or write a remote register in the TWU16 subsystem
and receives an address error indication
on the console (CPU traps to location
4).
This condition may be caused by a stuck
TRA signal on the Massbus which prevents the SSYN response from the
RH70. Determination of this condition
may be made if local registers in the
RH70 can be successfully accessed. If no
register responds, the address jumpers
may be improperly selected.

TOP OF MODULE

TRAcj}:

7.3 VISUAL INSPECTION AND ELECTRICAL
CHECK
Before the diagnostics are run, the following visual
inspection and electrical checks should be made.
LlGH T EM ITTING
DIODES (LED'S)

Verify that all modules have been configured correctly in accordance with Figure 7-1.
NOTE
The M5904 modules should be marked on
the etch with REV E or later for proper
positioning of the cables.

BCT MODULE( M8153)

Ensure that all modules are firmly seated
in the system backplane assembly.

Inspect backplane wiring for broken
wires or damaged pins. Repair or replace as required.

Clean air filters at the top of the cabinet.

Ensure that all Unibus and Massbus cables are properly terminated and firmly
seated. The Unibus should be terminated
with an M9301 Terminator in slots E, F
01, and an M9302 Terminator in slots
A, B 44. The Massbus cables are terminated in the last drive with H870 Miniterminators which are plugged into the
M5903 Transceiver modules.

Check cabinet fans
operations.

11-2940

Figure 7 -3

LED Physical Locations

Unibus device interrupt sequence not
functioning properly (processor continuously loops in service routine and fails
to execute instructions).
This condition is caused by discontinuity
of the bus grant signal on the Unibus
from the processor to the device interrupting and may be caused by missing
Grant continuity cards or defective circuitry, which normally passes Grant signals from device to device. This will
cause the BG IN light emitting diode to
7-5

for

proper

Verify that Grant continuity cards that
should be installed are properly installed
in slots 027, 031, 035, and 039 if no
controllers are housed in these slots.

Check the power receptacle to be used
for the 861 for correct hot, neutral, and
ground connections. Refer to the 861A,B,C,D,E,F, Power Controller Maintenance Manual, EK-861AB-MM-002 for
the plug and receptacle diagrams for the
particular 861 being used.

Ensure that all jumpers are properly configured (refer to Paragraph 7.2.5).

Check for power shorts with an ohmmeter. +5 V is contained on pin AA2 of
each module slot, -15 V is contained on
pin AB2 of the M5904 module; pin AC2
on each module is grounded.

Plug the 861 power cord into the power
receptacle.

Set the 861 circuit breaker to the: ON
position.

10.

Power-up system and verify voltages indicated in step 9.

Set the 861 LOCAL/OFF/REMOTE
switch to LOCAL.

11.

Verify that all LEOs are extinguished.

Verify the following:
Cabinet fan operating
TM02 fan operating
TU16 PWR indicator lit.
TM02 power LEO (bottom LEO) lit.

7.4 TM02/TU16 INSTALLATION
This paragraph describes the installation procedure
and voltage checkout of the TM02/TUI6 Tape
Orive Subsystem.
1.

Unpack the TM02/TU16 cabinet and
bolt it to the system cabinet.

Install the cabinet ground strap.

Set the 861 circuit breaker to the OFF
position.

10.

Remove the TU 16 shipping brackets and
slide the transport out.

11.

Check the power supply voltages listed
in Tables 7-1 and 7-2.

NOTE
The voltage settings are critical. Do not
attempt to adjust the voltages unless a
well-calibrated scope or digital voltmeter
is available.

Set the 861 LOCAL/OFF/REMOTE
switch to OFF.

Table 7-1
TUI6 Backplane, Regulated Voltages
Designation
+5V
+12V
-6.4V
+12V (NRZ)
+5V (PE) *
GND

Pin No.

Voltage (Vdc )

Tolerance (Vdc)

Control
Po ten tiometer

D01A2
B04Sl
C04N2
C02J2
C02J2
D01C2

+5.25
+12.05
-6.35
+11.875
+5.6

+0.05
+0.05
+0.05
+0.125
+0.1

R16
R37
R44
R26
R57

7-6

Table 7-2
P4 Connector, Unregulated Voltages

19.

Check the power supply voltages listed
in Table 7-3 and adjust if necessary.

20.

Set the 861 LOCAL/OFF/REMOTE
switch to OFF.

21.

Connect the Massbus and slave bus cables going into and out of the TM02 as
described in Paragraphs 7.4.1, 7.4.2, and
7.4.3.

22.

Install the remote power control cable to
the 861 power controller.

Load a scratch tape on the TU16 and
check out all manual functions:

23.

Set the 861 LOCAL/OFF/REMOTE
switch to REMOTE.

Load
Brake Release
Forward
Reverse
Rewind
Start
Stop

24.

Apply system power. Verify that the
TM02 and TUI6 power indicators are
lit.

25.

Attempt to examine locations 772440 772476 (standard TWU16 addresses). If
the processor traps, refer to Figure 7-4
for possible addressing jumper problems.

26.

Attempt to deposit and examine all I s in
location 772446. If any bits are missing,
check out the Massbus cabling (Paragraph 7.4.1 and 7.4.3).

Designation

Wire Color

+17V
-17V
+18V
-18V
GND

Orange
Yellow
Pale Green
Blue
Black

12.

13.

Minimum
Voltage (Vde)
+17.0
-17.0
+18.0
-18.0

Connect the slave bus cables to the
TU 16 as described in Paragraphs 7.4.2
and 7.4.3.

14.

Set the 861 LOCAL/OFF/REMOTE
switch to OFF.

15.

Slide the TU16 back into the cabinet.

16.

Remove the shipping brackets from the
TM02 and slide it out of the cabinet on
its slides.

17.

Remove the top and side covers of the
TM02.

18.

Set the 861 LOCAL/OFF/REMOTE
switch to LOCAL.

7.4.1 RH70/TM02 Massbus Cable Installation
Massbus cables must be installed between the
RH70 and the TM02 as shown in Figure 7-5. The
ribbed surface of the Massbus cables must face up
at the RH70 output, and the smooth surface of the
cables must face up at the input of the TM02. Refer to Paragraph 7.4.3 for cable identification
markings.
CAUTION
All Massbus cables must be installed with the red
line toward the module handle. Otherwise, a signal
line will be grounded.

Table 7-3
TM02 VoItage Ch eck
Designation

Pin No.

Wire Color

Voltage (Vde)

+5V
+15V
-15V
ACLO
DCLO

A01A2, F01A2
F01V1
A04B2
A09H1
A09Jl

Red
Orange
Blue
Yellow
Violet

+5.00
+15.0
-15.0
+4.85
+4.85

7-7

Tolerance (Vde)
+0.25
+1.0
+1.0
+0.15
+0.15

Control
Potentiometer
R50
R35
R26
-

first (or single) TU16, but if multiple TU16s are installed, a half-twist of the slave bus cable mu:st be
used between TUI6s. Refer to Paragraph 7.4.3 for
cable identification markings.

If more than one TM02 is used:
I.

All TM02s must have the smooth side of
the BC06R Massbus cable up at the input of the TM02, and the ribbed side up
at the output.

Mid-bus TM02s use M5903 modules.

The end-of-bus TM02 (as in the case of
a single TM02) uses M5903 modules
with H870 miniterminators.

CAUTION
All slave bus cables must be installed with th4~ red
line toward the module handle. Otherwise, the +5 V
will be applied to a signal line instead of the shield
where it belongs.
Mid-bus TU 16s use different modules than an endof-bus (or single) TU16.

7.4.2 TM02/TU16 Slave Bus Cable Installation
Slave Bus cable connections between the TM02 and
the TU 16 and between daisy-chained TU 168 are
shown in Figure 7-6. A half-twist in the slave bus
cable is not required between the TM02 and the

Cable A
Cable B
Cable C

M8153

Mid-Bus

End-of-Bus

M9001
M8913
M9001YA

M9001YB
M8913YA
M9001YC

JUMPERS

ADDRESS SELECTION
(FOR UNIBUS ADDRESS 772440)
JUMPER IN = BINARY 0
W14 W10 W9 W8
OUT IN OUT IN

W11 W13 W15 W12
OUT IN IN OUT

JUMPER
JUMPER IN/OUT
11
0
0

o 1 ADDRESS BITS
0

BINARY ADDRESS
OCTAL ADDRESS

-- -- --

VECTOR SELECTION
(FOR UNIBUS VECTOR 224)
JUMPER IN = BINARY 1
W4 W1 W5 W2 W6 W3 W7
JUMPER
r----r_-r----,-_.,.---r_-r----,r---,-_.y-O_U_Ty--IN--r-0_U_T-r0_U_T-r-I_N..,..;...OU,;;...T...,..;.I_N-r----,r--~ JUMPER IN lOUT

~11-4..L..1-13...L.1-'2-L.1-11-L.1_1O-L1-9--!-1-8--1.1_7......11_6~1~5---J1L-4---L-13---L-1_2.1-1_1..1-1---101 VECTOR BITS

,.....1_7......
11_6......
11_5

o g log
0

~~;AR:

LEGAL REGISTER SELECT
(SELECTS DECIMAL 16 REGISTERS)
SLOT E041

BINARY
EQUIVALENT

JUMPER
1
2

3
4
16-2 = 14

{ :

6
7
8

TO
TO
TO
TO
TO
TO
TO
TO

JUMPER IN/OUT
16
15
14
13
12
11
10
9

IN
IN
OUT
OUT
OUT
OUT
OUT
IN

I
\

11- 3078

Figure 7-4

Jumper Summary
7-8

RH70 (CONTROLLER A,B,C OR D)
(CABLES MARKED CONTROLLER A)
MASSBUS CABLE A OUT

EACH CABLE
MUST HAVE A
HALF TWIST

M5904~/~
MASS BUS CABLE BOUT
M5904

M5904

~M-A-S-S-B-U-S-C-A-B-L-E-C--O-U-T~~

r---------------~~--~r__<~

RIBBED SURFACE OF CABLE
MUST FACE UP AT THIS END

MID-BUS TM02
(CABLES MARKED CONTROLLER B)

EACH CABLE
MUST HAVE A
HALF TWIST

.,t.1i--

MASSBUS CABLE A OUT

MASSBUS CABLE A IN

"
M5903

(A/B04)

M5903

(A/B05)

)-M-A-S-S-B-US-C-A-B-L-E-B-O-U-T-I

MASSBUS CABLE B IN

MASSBUS CABLE C OUT

MASSBUS CABLE C IN
(A/B06)

M5903

RIBBED SURFACE OF CABLE
MUST FACE UP AT THIS END

SMOOTH SURFACE OF CABLE
MUST FACE UP AT THIS END

END OF BUS TM02
(CABLES MARKED CONTROLLER B)
MASSBUS CABLE A IN
M5903

* (A/B04)

M5903

* (A/B05)

M5903

* (A/B06)

MASSBUS CABLE B IN

MASSBUS CABLE C IN

*LAST
DRIVE TERMINATED WITH H870
MINITERMINATORS

SMOOTH SURFACE OF CABLE
MUST FACE UP AT THI SEND
11- 3079

Figure 7-5

RH70/TM02 Massbus Cabling Diagram

7-9

TM02 TO FIRST TU16
TM02

CABLE A OUT I\..

M8907 (AB01)

....
CABLE B OUT '"

M8908YA (AB02)

TO FIRST TU16

v
CABLE C OUT .....

1. SMOOTH SIDE OF CABLE UP
2. RED LINE TOWARD MODULE HANDl.E

M8908 (AB03)

....

3. CONTROLLER DESIGNATION "B"

4. DIRECTION DESIGNATION "OUT"

MID- BUS TU16
( MULTI TRANSPORT SYSTEM)
CABLE A IN

CABLE A OUT"

TU16
M9001 (AB01)

....

CABLE BIN
FROM TM02 OR
PREVIOUS TU16

CABLE BOUT.....
TO NEXT TU16

M8913 (CD01)

CABLE C IN

CABLE C OUT",
M9001 YA (EF01)

1. SMOOTH SIDE OF CABLE UP

OUT

1. RIBBED SIDE OF CABLE UP
2. RED LINE TOWARD MODULE HANDLE
3. NO CONTROLLER DESIGNATION
4. DIRECTION DESIGNATION "our"
5. HALF TWIST IN CABLE BETWEEN
THIS AND NEXT TU16

2. RED LINE TOWARD MODULE HANDL E
3. NO CONTROLLER DESIGNATION
4. DIRECTION DESIGNATION "IN"

END-OF-BUS TU16
CABLE A IN

TU16
M9001YB (AB01l

CABLE B IN

FROM TM02 OR
PREVIOUS TU16

1. SMOOTH SIDE OF CABLE UP

M8913YA (CD01)

CABLE C IN
M9001 YC (EF01)

2. RED LINE TOWARD MODULE HANDLE
3. NO CONTROLLER DESIGNATION
4. DIRECTION DESIGNATION "IN"

11- 2802

Figure 7-6

TM02/TU16 Slave Bus Cabling Diagram

7-10

7.4.3 Markup of Massbus and Slave Bus Cables
Both surfaces of each end of the Massbus and slave
bus cables are stamped as shown in Figure 7a 7. The
stamps are marked up to indicate cable designations at the time the cables are installed. Mark the
BC06R Massbus cables as follows when installing
them:
1.

Cross out the designation THIS SIDE
UP on the under side of the cable.

Cross out the CONTROLLER designation that does not apply. Cross out B
when plugging into the RH70; cross out
A when plugging into the TM02.

Cross out the CONNECTOR MODULE designations that do not match the
cable letter being used.

Cross out IN for the output cables; cross
out 0 UT for the input cables.

Figure 7-8 shows an example of a cable that is
marked up to be plugged into the M5903 module in
slot A/B06 of end-of-bus TM02.

THIS SIDE UP

Idli\gliltlall\
PART NO.
BC06R-10

CONNECTOR
MODULE

RED LINE MUST BE
ON SIDE CLOSEST
TO MODULE HANDLE

SMOOTH SIDE UP

THIS SIDE UP

Idlilglqtlall\

11-2804

PART NO.

Figure 7-8

CONNECTOR
MODULE

ABC

DEC]
~

11-2803

Figure 7-7

Massbus Cable Stamp

Marked-Up Massbus Cable

7.5 MAINTENANCE TOGGLE PROGRAM
This paragraph lists and describes a maintenance
program (Figure 7-9) which may be used by maintenance personnel for exercising the data buffer. This
program allows maintenance personnel to select a
data pattern and load it into the data buffer in the
RH70 via the OAT A switches on the console. This
pattern is loaded into the right-half, or even-word
section of the data buffer, will sequence through
the data buffer, and be transferred to the DATA
lights on the console. The pattern displayed on the
lights should agree with the data pattern loaded in
the switches.
A second pattern or data word can be loaded into
the data buffer via the DATA switches. This word
is loaded into the left-half, or odd word section, of

7-11

· the data buffer. The second data word will sequence through the data buffer and will be transferred to the DATA lights on the console, similar
to the first data word. The data pattern on the

LOC.

CONTENTS

1000/
1002/
1004/
1006/
1010/
1012/
1014/
1016/
1020/
1022/
1024/
1026/
1030/
1032/
1034/
1036/
1040/
1042/
1044/
1046/
1050/
1052/
1054/
1056/
1060/
1062/
1064/

052737
000040
172450
013737
177570
172462
013737
177570
172462
005000
105737
172450
100403
105200
001373
000000
013737
172462
177570
000403
013737
172462
177570
105737
172451
001746
000000

lights should agree with the data pattern loaded in
the switches. This program is strictly an i.nternal
RH70 verification program; no peripheral device or
Massbus cycle is required.

PROGRAM
START:

BIS #CLR, @#MTCS2

MOV @#SWR, @#MTDB

WAIT:

CLRRO
TSTB @#MTCS2

ROUT:

BMIROUT
INCB RO
BNEWAIT
HALT 1
MOV @#MTDB, @#LITES

BR TEST
MOV @#MTDB,@#LI~ES

TEST:

TSTB @#MTCS2+ 1
BEQSTART
HALT2

NOTES:
1.

To loop on no Output Ready, deposit 000760 in location 1036 .

To display second data word, deposit 000240 in location 1046.

To loop on error condition, deposit 000745 in location 1064.

Figure 7-9

Maintenance Program to Exercise Data Buffer

7-12

7.5.1 Maintenance Program to Exercise the Data
Buffer
The first instruction in location 1000 is a Bit Set instruction to bit 5 (CLR bit) in the MTCS2 register.
This instruction initializes the data buffer and all error conditions. The next instruction is a MOV instruction, which transfers the contents of the
DAT A switches into the right-half, or even word
section, of the data buffer. The DATA switches are
loaded by maintenance personnel with some desired
data pattern. The third instruction is another MOV
instruction, which transfers the data pattern set into
the switches into the data buffer. This pattern is
loaded into the left-half, or odd word section, of
the data buffer, which now allows the entire data
buffer to'be ex,ercised. The next instruction in location 1022 is a CLR RO instruction which clears the
RO register. This register functions as a wait loop
counter. If a hardware failure prevents data words
from being read out of the data buffer, the Output
Ready (0 R) signal will not be asserted and the program might end up in an infinite loop. To prevent
this condition, the wait loop is included in the program. The wait loop is initiated by a TSTB instruction which examines the low byte of the MTCS2
register. Assume that the Output Ready (OR) signal is asserted and the first d.ata word is in OBUF.
The OR signal is bit 7 of the low byte of MTCS2.
Bit 07 is also the sign bit for the low byte and indicates a minus when asserted.
As a result, the branch condition of the BMI instruction in location 1030 is met and the program
branches to the ROUT (Read Out) loop. The first
instruction in this loop is a MOV instruction,
which transfers the contents of OBUF (first data
word) to the DATA lights on the console. The pattern on the lights should agree with the data loaded
in the switches. The next instruction is a BR TEST
which branches the program to location 1056. A
TSTB instruction in this location tests the upper
byte (MTCS2 + 1) of the MTCS2 register for error
conditions.
If there are no errors, this byte is 0 and the next instruction (BEQ) loops the program back to START
(location 1000). If an error condition was present,
the upper byte of MTCS2 would not be 0 and the
program would sequence to location 1064. A
HALT instruction in this location causes the program to halt.

NOTE
The address lights will indicate the address,
(which is location 1066).

+2,

If it is desired to loop on this error condition,
000745 is deposited into location 1064. This causes
the program to loop back to START.

Now, return to the Output Ready wait loop. If
there is no Output Ready signal (indicating a hardware failure), the program sequences to location
1030, the branch condition is not met, and the program sequences to the next instruction at location
1032. This location contains an INCB instruction,
which causes the low byte of the RO register to be
incremented. If the low byte is not equal to 0, the
next instruction, which is a Branch on Not Equal
(BNE), loops the program back to location 1024,
where the Output Ready (OR) signal is again monitored. If the OR signal is still not available, the
low byte of RO is again incremented. This continues
for 256 counts if no OR signal is available, and at
this time, the low byte of the RO register overflows
to all Os. Now, the program sequences to the next
sequential location (location 1036) which contains a
HALTI instruction, thus halting the program. This
means that the MTCS2 register has been examined
256 times with no OR signal being asserted and indicates that a hardware error has occurred. To loop
on this error, 000760 is deposited in location 1036.
This causes the program to loop back to START,
enabling maintenance personnel to examine the error condition.
Up to this point, only the first data word has been
examined on the DATA lights. If it is desired to examine the second data word loaded in the data buffer, a NOP (000240 8 ) is loaded in location 1046,
replacing the BR TEST instruction. Now, the program will merely sequence through location 1046 to
1050. This location contains a MOV instruction,
which moves the second data word into the DATA
lights on the console. The pattern on the lights
should correspond to the DATA switches on the
console.
The next instruction in location 1056 is the TSTB
instruction, which checks for error conditions in the
second data word by monitoring the high byte of
MTCS2. If there are no errors, the high byte of
MTCS2 is 0 and the next sequential instruction
(BEQ) branches the program back to START. If
there is an error, the high byte of RSCS2 will not
be equal to 0 and the program will sequence to the
next instruction at location 1064. This location contains a HALT2 instruction which halts the program. The error condition can be looped on by
depositing 000745 in location 1064, which will
cause the program to loop back to START.

7-13

7.(. DIAGNOSTIC MAINTENANCE
The diagnostic programs described herein are employed with the TWUI6 subsystem. Refer to the applicable diagnostic operating procedures for
detailed information.

written on yields unpredictable data. However, if a
tape has been written with this program, it (:an be
read as often as desired without being rewritten.
This is good procedure to use for testing tape
compatibility.

7.().l RH70 Controller Test Diagnostic (DZRHA)
This diagnostic verifies that the RH70 Controller is
operating correctly. The diagnostic can test up to
four RH70 Controllers simultaneously, however, an
operating Massbus peripheral must be connected to
each RH70 Controller. The major tests in the diagnostic are:

7.6.3 TM02/TUl6 Basic Function Dia~:nostk
(DZTUB)
This diagnostic provides for testing all fum:tional
level operations of the TM02/TU16 Magtape System. The following is a list of all tests in their
proper sequence. A basic description of each test is
provided to aid in understanding the error messages
associated with each.

Determining whether all registers in the
controller can be read from or written
into.

RH70 Tests
The first ten tests will perform basic RH70 operations as far as possible without requiring thl~
TM02/TUI6.

Checking error conditions in the controller by causing an error and observing
the results on the associated error bit in
the CS 1, CS2, or CS3 registers.

FTl: RH70 Addressing
This test will ensure that the RH70 will re:spond
without causing a bus trap to all TM02 register
addresses in sequence, starting at the address of
CS 1 entered by the operator.

Checking that the data buffer can accurately store and transfer data.

FT2: RH70 Register Bits Read/Write
This test will ensure that all bits of the RH70
write/read registers can be set and reset.

7.6.2 Data Reliability Diagnostic (DZTUA)
This diagnostic provides for evaluation and debugging of magnetic tape drives. The program is capable of exercising any tape drive that is
compatible with the Massbus and the TM02. Any
number of drives up to eight (single or multi-drive
systems) may be tested by a single execution of the
program. This flexibility is possible because the program has no fixed parameters or testing sequence.
The entire test plan, including parameters and operatilng sequence, is determined by the operator
through responses to teletype writer requests and
setting of console switches.

FT3: RH70 Initialize
This test will ensure that an RH70 Initialize (bit
5 of CS2 = I) will indeed clear the RH70 {~rrors.
FT5: Data Buffer Test 2
This test will ensure that both the IR and OR
bits will respond correctly to loading thl~ data
buffer with all zeroes followed by a word of al:l
ones.
FT6: Data Buffer Test 3
This test will write and then read the entire data
buffer to ensure that data can be properly
loaded into and read from the data buffer. The
proper status of IF and OR are also checkl~d.

The program provides for testing all tape drive functions such as writing, reading, rewinding, tape positioning, EOTBOT sensing, and assumes a properlyoperating RH70 Massbus controller and TM02
tape controller. During a test cycle, checks are
made for status errors, data errors, position errors,
word count, and memory address errors wherever
applicable.

FT7: Data Buffer Test 4
This test will ensure proper RH70 response to
data buffer overflow.

The program will attempt to perform any operation. Therefore, caution should be used to ensure
that the unit can perform as requested. For example, an attempt to read tape that has not been

FTlO: Data Buffer Test 5
This test will ensure data buffer reset by RH70
Initialize.

7-14

TM02/TU16 Basic Functions
The following 14 tests will ensure operation of the
Magtape basic functions.

FT24: Rewind
Off-line, this test will ensure that the unit will
rewind and go off line (not if in continuous
cycle).

FTll: NOP Test
This test will ensure that the NOP function executes with no error.

7.6.4 TM02/TU16 Control Logic Test (DZTUC)
This diagnostic sequentially tests all control logic
and data formatting within the TM02 formatter.
Each test will attempt to isolate failures to the module level and provide printout information that will
identify the failing module.

FT12: Rewind Test
This test will ensure that the rewind function will
position the tape to BOT with no error.
FT13: Write/Read Test
This test will ensure that the unit under test can
write and read in all densities.

There are two major areas of testing - control logic
and data formatting. The control logic testing will
test all error and status conditions, as well as address protocol and operational logic sequences. On
the first line, the printout will contain a header
which calls out the test number, function being
tested, and the suspected module(s}. The second
line will contain information regarding the actual error. Both expected and actual results will be given.
Line three will show the contents of the major registers at the time of the error and line four will print
the iteration number, as applicable.

FT14: Space Test
This test will ensure that proper positioning is
maintained by both space forward and reverse.
FT15: Erase Test
This test will ensure that the erase function will
indeed erase tapes.
FT16: Tape Mark Write/Read
This test will ensure that a tape mark can be
written and read in both PE and NRZ.
FT17: Tape Mark Space Test
This test will ensure that spacing will be terminated by recognition of tape mark both in PE
and NRZ.

The data formatting section will test all data formats and transfer paths in all possible combinations. These tests will print a header containing
the test number and a description of the
wraparound function under test. A list of major registers, with expected and actual values, will follow
the header. Any bad data will be printed (per character) following the register information, or following the header if no status errors were encountered.

FT20: W rite-Check Test
This test checks write-check forward and reverse
in both PE and NRZ modes.
FT21: Erase Head Test
This test will ensure that the erase head is
operating.

7.6.5 TM02 Drive Function Timer (DZTUD)
This diagnostic measures the time required and the
gap sizes produced by the TM02/TUI6 Magtape
Drive. The program requires a PDP-II family central processor with 4K memory and with up to 64
TM II/TM02 Controller/Magtape stations.

FT22: Buffered Command
This test will ensure that the TM02 will accept
and execute another command while its selected
slave is rewinding.
FT23: Read in Preset
This test will ensure that unit 0 is rewound and
set to 800 bpi normal (only if slave 0 is selected).

Two types of errors are detected by this program hardware errors and incorrect function times.

7·15

7.6.6 TU16 Utility Driver (DZTUE)

7.6.7 Data Tape Create (DZTUF)

This diagnostic uses a brute force routine to continuously execute an operation or series of operations,
regardless of the results. Because of the complexity
of the TU16 tape system on the Massbus, it is not
always possible to provide for every contingency in
normal programs. Therefore, this utility driver will
allow an operator to execute anything desired (in
any order). There are no error checks or printouts
made; any variation from preset sequences and values are made by changing the appropriate memory
locations.

This diagnostic is not a test program but a supplement to both the TMll/TU10 and TM02/TU16
data reliability programs. The purpose of this supplement is to allow the operator to create a paper
tape for any data pattern desired; it is used by the
data reliability programs when data pattern zero is
selected.

The program requires that the operator be knowledgeable of the TU16 tape system as operated with
the RH70 Massbus controller. The operator must
be able to decide which sequence of operations is required and to assign val 11es to the various parameters required to execute them.

7-16

APPENDIX A
INTEGRATED CIRCUIT DESCRIPTIONS

A.I INTRODUCTION
This appendix contains descriptions of some of the
integrated circuits used in the RH70 Massbus Controller. Where applicable, logic diagrams, schematics, truth tables, and pin connection diagrams are
shown.

A-I

A.2 7442 4-LINE-TO-tO-LINE DECODERS (tof-tO)
These monolithic decimal decoders consist of eight
inverters and ten 4-input NAND gates. The inverters are connected in pairs to make BCD input
data available for decoding by the NAND gates.
Full decoding of valid input logic ensures that all
outputs remain off for all invalid input conditions.

The 7442 BCD-to-decimal decoder features familiar
transistor-transistor-Iogic (TTL) circuits with inputs
and outputs that are compatible for use with other
TTL and DTL circuits.

TRUTH TABLES
BCD Input

D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

B
0

0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Decimal Output
A

0
1
0
1
0
1
0
1
0
I
0
I
0
1
0
1

0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

A-2

1
1
0
1
1
1
1
1
1
1
1
I
I
1
1
1
1

2
1
1
0
1
1
1
1
1
1
I
1
1
1
1
1
1

3
1
1
1
0
1
1
1
1
1
1
1
1
I
1
1
1

1
1
1
1
0
1
1
1
1
1

1
1
1
1
1
1

5
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1

6
1
1
1
1
1
1
0
1

1
1
1
1
1
1
1
0

1
1

I
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
I
0
1
1
1
1
1
1

I
1
1
1
1
1

o
Vee = PIN 16
GND=PIN 8

IC·0016

A-3

A.3 74H74 D-TYPE EDGE-TRIGGERED FLIPFLOPS
The 74H74 consists of two D-type edge-triggered
flip-flops. Each flip-flop has individual clear and
preset inputs and complementary Q and Q outputs.
I nformation at input 0 is transferred to the Q output on the positive-going edge of the clock pulse.

Truth Table (Each Flip-Flop)
tn

tn+l

Signal/Pin Designation

INPUT
D
L

OUTPUT
Q
L

OUTPUT
Q

2
3
1

CLOCK
CLEAR
PRESET

H = high level, L = low level

Circuit #1

Signal Name

4
5
6

NOTES:

A. tn = bit time before clock pulse.
B. tn+ 1 = bit time after clock pulse.

CLE AR 0--..-.------4

CLOCK 0--+-+___-..,

oQ o - - - - - - i
IC-0049

A.4 74S74 D-TYPE EDGE-TRIGGERED FLIPFLOPS
The 74874 D-Type Edge-Triggered flip-flop is similar to the 74H74 flip-flop described in Paragraph
A.2. The major difference is that the 74S74 is a faster flip-flop.

A-4

Circuit #2
12
11
13
10

9
8

A.5 7485 4-BIT MAGNITUDE COMPARATORS
The 7485 performs magnitude comparison of
straight binary and straight BCD (8421) codes.
Three fully decoded decisions about two 4-bit
words (A, B) are made and are externally available
at three outputs.

TRUTH TABLE
COMPARING

CASCADING

INPUTS
A3, B3

A2,B2

OUTPUTS

INPUTS

A1, B1

AO, BO

A>B

A<B

---

A=B

A>B

-~-.-.-

--~----

A=B
L

NOTE

A3 > B3

A3 < B3

A3 = B3
A3 = B3

A2 > B2

A2 < B2

A3 = B3

A2 = B2

Al > B1

A3 = B3

A2 = B2

A1 < B1

A3 = B3

A2 = B2

A1 = B1

AO;. BO

A3 = B3

A2 ~ B2

A1 = B1

AO < BO

A3 = B3

A2 = B2

A1 = B1

AO c. BO

A3 = B3

A2 = B2

A1 = B1

AO = BO

A3 = B3

A2 = B2

A1 = B1

high level, L

= low level, X = irrelevant

, - - - - - - - - - ---

A>B

A2 o:.:.:"-+-+--l++--1~
B2 D---+-+-4__ +-.t-1-----./

!A<BIIN 0-'=2'-+-+--+-1_
I A W 81 IN

0-=-+-+---+ +

(A>B I IN O---+-+--+

(1]1

81 ~-1,I-++.~

Lj----+-+-l+-L-.-/
A<B

Pin (16) = VCC' Pin (8) = GND
IC-0159

A-5

__._--

A<B
--

A.6

749106

DUAL

J-K

EDGE-TRIGGERED

FI~IP-FLOPS

The 74HI06 J-K flip-flops are negative-edge triggered. J, K, clock, asynchronous preset, and clear
inputs are available. When the clock goes high, the
inputs are enabled and data will be accepted. The
logical state of the J and K inputs may be allowed
to change when the clock pulse is in a high state
and will perform according to the truth table as
long as minimum setup times are observed. Input
data is transferred to the outputs on the negative
edge of the clock pulse.

GND

VCC
2
2
2
CLOCK PRESET CLEAR

TRUTH TABLE
t n +l

tn
J

CLOCK PRESET CLEAR

positive logic: Low input to preset sets Q to logical 1
Low input to preset sets Q to logical 0
Clear and preset are Independent of clock

NOTES: 1. tn = Bit time before clock pulse

2. tn+'- Bit time after clock pulse

t Pin assignments for these circuits are the same for all packages

IC-0145

MINIMUM

SETUP ~

l+I

J.K

ENABLED

t . . - INPUTS --..-I

J-K INPUTS
INHIBITED

CLOCK WAVEFORM

A-6

J-K INPUTS
INHIBITED

A.7 74123 RETRIGGERABLE MONOSTABLE
MULTIVIBRA TOR
The 74123 Monostable Multivibrator provides dc
triggering from gated low-level active (A) and highlevel active (B) inputs. Overriding direct-clear inputs and complementary outputs are also provided.

By triggering the input before the output pulse is
terminated, the output pulse may be extended. The
overriding clear capability permits any output pulse
to be terminated at a predetermined time independently of the external timing components.
The waveshapes below show the input/output pulses when the one-shot is triggered by the high-level
active (B) inputs.

RETRIGGER PULSE
(SEE NOTE)

n ___---I!n. . ______- :- ___

B INPUT

I - - - tW+tpLH~,

',I
J1r---tw---~·rouTPUT

OUTPUT Q

WITHOUT RETRIGGER

OUTPUT PULSE CONTROL USING RETRIGGER PULSE

BINPUT~~_______________________

CLEAR

r--_ _ _ _

OUTPUT WITHOUT CLEAR

OUTPUTQ~I....__-_-_-_-_I~I_______________
OUTPUT PULSE CONTROL USING CLEAR INPUT
IC-OI46

A-7

Vee

CLEAR

I
CLEAR

2
Cext

2 Rext/ GND
Cext

FUNCTIONAL LOGIC/PIN LOCATOR

TRUTH TABLE
INPUTS

OUTPUTS

J'L
J'L

-U-U-

NOTE: H" high level (steady state), L" low level (steady state),
t & transition from low to high level, I" transition from
high to low level, J'L" one hioh-ievei pulse, -U-" one
low-level pulse, X= irrelevant (any input, includino transitions).
Ie-01B6

A-8

A.8 74157 QUADRUPLE 2-LINE TO I-LINE
MULTIPLEXER
The 74157 quadruple 2-line to I-line multiplexer features buffered inputs and outputs. All outputs are
low when disabled (enable high). The truth table
and logic diagram are shown below.

INPUTS

OUTPUT Y

OUTPUTW

SN54/74157,
ENABLE SELECT A B

X
L
L
H

L
L

SN54S/74S157

SN54S/74S158

H
H

X X
L X
H X

L
H

X L
X H

H = high level, L = low level, X

L
H

= irrelevant

(2)
1Y

(3)

(5)

(6)

(14)
3A

3B
4A

(13)
(11 )

(10)

SELECT
Pin 16 = Vee, Pin 8 = GND

ENABLE 0 ' - - - - 0
Pin (16) = VCC, Pin (8) = GND
IC-0160

A.9 74S157 QUADRUPLE 2-LINE TO I-LINE
MULTIPLEXER
The 74S 157 Quadruple 2-line to I-line multiplexer
is similar to the 74157 multiplexer described in paragraph A.S. The major difference is that the 74S157
is a faster multiplexer.
A-9

A.tO

74174 HEX D-TYPE FLIP-FLOPS

The 74174 contains six flip-flops with single outputs. The flip-flops contain direct-clear inputs and
buffered clock inputs.

A .13)

TRUTH TABLE
INPUT

QA ~

OUTPU
t n+

°
H

tn = Bit time befor e
clock pulse.
t n +1-Bit time aft oar
clock pulse.

-C CLOCK
CLEAR

9
B (4)

QB ~

~ CLOCK

CLEAR

9
C (6)

QC ~

~ CLOCK

CLEAR

9
o (11)

QD ~

: CLOCK
CLEAR

~
E (13)

QE ~

<: CLOCK
CLEAR

9
F (14)

CLOCK~

QF ~

)

CLEAR~

)

,....
"'"

"..,

::: CLOCK
CLEAR

Pin (16)- Vec.Pin (8)- GND
Ie-OOH

A.Il

74S174 HEX D-TYPE FLIP-FLOPS

The 74S 174 D-type flip-flops are similar to the
74174 flip-flops described in paragraph A.lO. The
major difference is that the 74S 174 are faster flipflops.

A-tO

A.12 74175 QUAD D-TYPE FLIP-FLOPS
The 74175 contains four D-type flip-flops with dual
outputs. Each flip-flop has direct-clear and buffered
clock inputs.

TRUTH TABLE
INPUT
tn

OUTPUTS
tn + 1

H
l

l
H

tn .. Bit time before
cloc k pulse.
tn ... 1 =Bit time ofter
clock pulse.

(4)

(2)

ClK QA
CLEAR

(3)

(7)

(5)

ClK 'OB
CLEAR

(12)

(6)

(10)

ClK QC
CLEAR

(11)

(15)

(13)

CLOCK

elK QD

(14)

CLEAR
CLEAR
Pin (16)- Vce. Pin (8)-GND
IC-0018

A-II

A.13 74180
PARITY
GENERATOR/CHECKER

CONTROL

The 74180 is an 8-bit parity generator/checker featuring odd and even outputs and control inputs to
provide odd or even parity operation. Word length
is expandable by cascading. The truth table, pin
connection diagram, and functional block diagram
are shown below.

/------1 NPUTS
Vee

\
o

TRUTH TABLE
OUTPUTS

INPUTS
IOF ,'sAT EVEN
o THRU 7

EVEN ODD
I
INPUT INPUT EVEN

ODD

EVEN

ODD

EVEN

ODD

I
EVEN

I
ODD

,
,

ODD

X= IRRELEVANT

~
INPUTS

EVEN ODD I·EVEN I'ODD GND
INPUT INPUT OUTPUT OUTPUT

o
1

IEVEN
OUTPUT

2
3

DATA
IN PUTS

IODD
OUTPUT

5
6
7

IN~B~ 0______- - - - - - - ,
EVENo----------------------~

INPUT
lC-01157

A-12

A.14 74191 4-BIT BINARY COUNTER
The 74191 is a 4-bit binary counter that counts in
BCD or binary and can operate as an up/down
counter. The counter can be preset by the load control and uses a ripple clock output for cascading.

DOWN/UP

ENABLE

LOAD

MODE

X
X
L
H

X
H
L
L

L
H
H
H

Parallel Load
No Change
Count Up
Count Down

H = high level, L = low level, X = irrelevant

Signal/Pin Designation
Signal Name

Pin Designation

CLOCK
DOWN/UP
DATA INPUT A
DATA INPUT B
DATA INPUT C
DATA INPUT D
LOAD
RIPPLE CLOCK
MAX/MIN OUTPUT
OUTPUTOA
OUTPUTO B
OUTPUTOc
OUTPUTO D

A-13

14
5
15
1

10
9

11
13
12
3
2
6
7

CLOCK

DOWN/
UP

DATA
II'IIPUT A

(!5)

~B'"

lV']

~CLOCK
""PC'
(12)

J- f-,

(4)

le:= ""

..,(15)

EI'IIABl E..,

DAT
II'IIPU

-:1.

D
J- .r

I _

1l.

(10)

....,.j

()--_

]

I -

L
(11)

~O UTPUT

Cl!fA~l
_

-':1.
PRE SE T

CLUCI(

9c 1-..,

L . - _ I(

CLE.AR

-=:I
J

~
""'- n

...

(6)

(9)

~OUT PUT

(H CLOCI(

r--J

.J
.J

(2)

J- f

II'IIP liTe

'PRESET

I-- J

LOAD

"ll"

(1)

I.-- ~

1'II~0~ 0 U"

"'OUTPU

K QAI-]

°A

~ CLOCK

--.
I~-

OA TA

(3)___

PRESET

MAX I M IN
OUTPU T

PRE Sf T

r-jJ
....,.j

°0

(7)

--,

.J"\ OUTPUT 00

L...c CLOCl(

II(

a 1-.

~I ~.DI ]
IC-0158

A-14

A.IS 74193 4-BIT BINARY COUNTER
The 74193 Binary Counter has an individual asynchronous preset to each flip-flop, a fully independent
clear input, internal cascading circuitry, and provides synchronous counting operations.

COUNT UP

COUNT DOWN

MODE

LOAD

Parallel Load

CLOCK

Count Up

CLOCK

Count Down

H = high level, L = low level, X = irrelevant

Signal/Pin Designation
Signal Name

Pin Designation

DATA INPUT A
DATA INPUT B
DATA INPUTC
DATA INPUT D
CLEAR
LOAD
DOWN COUNT
BORROW OUTPUT
CARRY OUTPUT
UP COUNT
OUTPUTQA
OUTPUT QB
OUTPUTQc
OUTPUTQD

A-IS

15
1
10
9

14
11
4
13
12
5
3

2
6
7

~--o

BORROW
OUTPUT

-0

CARRY
OUTPUT

DATA 0INPUT A

DOWN
COUNT

UP
COUNT

DATA
INPUT B

OUTPUT QB

DATA
INPUT C

--0

OUTPUT QC

DATA
INPUT D

OUTPUT QD

IC-0002

A-16

A.16 74298
QUADRUPLE
2-INPUT
MULTIPLEXER
The 74298 Quadruple 2-input multiplexers with storage selects one of two four-bit data sources and
stores the data synchronously with the system
clock.

When the WORD SELECT input (pin 10) is low,
word 1 (A 1, B 1, C 1, and D 1) is applied to the flipflops. When the WORD SELECT input is high,
word 2 (A2, B2, C2, and D2) is applied to the flipflops. The selected word is clocked to the output
terminals on the negative-going edge of the clock
pulse.

(TOP VIEW)
OUTPUTS

DATA
WORD INPUT
Qo CLOCK SELECT C1
\

VCC

OUTPUTS

INPUTS
WORD
SELECT
CK
B2

Q
A
al

QAO Q 8 0

QCO

QOO

·QB

CLOCK

H = high level (stead y state)
L = low level (steady state)
X = irrelevant (any input including transitions)

• = transition from high to low level
B2

\~------------~v~------------~

aI, a2,etc. = the level of steady-state input at AI, A2, etc.
QAO' Q BO' etc. = the level of Q A, Q 8, etc. entered on the
most-recent, transition of the clock input.

GNO

DATA INPUTS

logic: see function table

FUNCTIONAL BLOCK DIAGRAM
AI
WORD SELECT
A2

(3)
(10)

(2)

(4)

(1)

(9)

(5)

(7)

(12) QO
02

CLOCK

(6)

(11)

-+ ...

Dynamic input activated by a transition from a high level
to a low level
IC-OI47

A·I7

A.17 75107
DUAL
DIFFERENTIAL LINE
RECEIVER
This chip is described in the Massbus transceiver
portion of Chapter 5 in this manual.
A.18 75113 DUAL DIFFERENTIAL DRIVER
Thiis chip is described in the Massbus transceiver
portion of Chapter 5 in this manual.
A.19 8223 256-BIT BIPOLAR FIELD-PROGRAMMABLE ROM (32 X 8 PROM)
The 8223 is a TTL 256-bit read only memory, organized as 32 words with 8 bits per word. The
words are selected by five binary address lines; fullword decoding is incorporated on the chip. A chip
enable input is provided for additional decoding
flexibility, which causes all eight outputs to go to
the high state when the chip enable input is high.

32 X S ARRAY

Vee = (16)
GND=(S)
( ) = DENOTES PIN NUMBERS
lC-01!15

A-I8

A.20 8234
2-INPUT
DIGITAL
4-BIT
MULTIPLEXER
This device is a 2-input, 4-bit digital multiplexer designed for general-purpose, data selection applications. The 8234 features inverting data paths. The
8234 design has open-collector outputs which permit direct wiring to other open-collector outputs
(collector logic).

0--------/

t(7)

Vee = (16)
GND-(8)
( ) = DENOTES PIN
NUMBERS
IC-Ol54

A-19

A.:Zl 82S62
PARITY
GENERATOR
AND
CHECKER
The 82S62 9-input parity generator/checker is an ultra high speed Schottky chip, used to detect errors
during data transmission or data retrieval. Even
and odd outputs are provided. An INHIBIT input
is provided to disable both outputs. A logic 1 on
the INHIBIT input forces both outputs to a logic

When used as a parity generator (during data trans,·
mission), the 82S62 supplies a parity bit which is
transmitted along with the data word. When used
as a parity checker (during data retrieval), the chip
indicates that the data has been received correctly
or that an error has been detected.

A, F PACKAGE

EVEN
. . - - - - - 0 OUTPUT

(9)

ODD
OUTPUT
(s)

LOGIC EQUATIONS
ODD OUTPUT = PI. P2 • P3 • P4 • P5 • Ps • P7 • Pe • P9
EVEN OUTPUT = PI. P2 • P3 • P4. P5 • Ps • P7 • Pe • P9
IC-0148

A-20

I
I
I
I
I
I
I
I
I

Reader's Comme

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