Digital PDFs

EK-OTK50-TM-001

May 1985

120 pages

Original

4.4MB

Document:	EK-0TK50-TM-001 TK50 Tape Drive Subsystem Technical Manual Jul85
Order Number:	EK-OTK50-TM
Revision:	001
Pages:	120
Original Filename:	EK-0TK50-TM-001_TK50_Tape_Drive_Subsystem_Technical_Manual_Jul85.pdf

OCR Text

EK-OTKSO-TM-001

.. TK50 Tape Drive

Subsystem
Technical Manual

EK-OTKSO-TM-001

TK50 Tape Drive

Subsystem
Technical Manual

Prepared by Educational Services
of
Digital Equipment Corporation

1st Edition, July 1985
Copyright 0 1985 by Digital Equipment Corporation.
All Rights Reserved.
Printed in U.S.A.
The reproduction of this material, in part or whole, is strictly
prohibited. For copy information, contact the Educational Services
Department, Digital Equipment Corporation, Maynard, Massachusetts
01754.

The information in this document is subject to change without
notice. Digital Equipment Corporation assumes no responsibility
for any errors that may appear in this document.
CompacTape is a shared trademark of Digital Equipment Corporation
and Minnesota Mining and Manufacturing Company.
The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts.
DEC
DECmate
DECnet
DECUS

DECwriter
DIGITAL
LA
MASS BUS
PDP

P/OS
Professional
Rainbow
RSTS
RSX

UNIBUS
VAX
VMS
VT
Work Processor

CONTENTS

CHAPTER 1 INTRODUCTION AND SPECIFICATIONS
1.1
1.2
1.3

Gene r a 1 ••••••••••••••••••••••••••••••••••••••••
TK50 Tape Drive Unit Specifications ~ •••••••••••
Drive to Controller Interface Specifications

1-1
1-2
1-2

CHAPTER 2 DRIVE UNIT THEORY OF OPERATION
2.1
2.2
2.2.1
2.2.2
2.3
2.4
2.5
2.5.1
2.5.2
2.6
2.6.1
2.6.2
2.6.3
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.4.1
2.7.4.2
2.7.4.3
2.7.5
2.7.6
2.7.7
2.7.8
2.7.9
2.7.10
2.7.11
2.7.12
2.7.13
2.7.14
2.7.15

· ..

General ••••••••••••••••
Uni t Des igna tions ••••••••••
Drive Unit Variations
M7546 Controller
Cabling ••••••••••••.
Power
•••••••••••••
Physical Description
Drive Board •••••••
Tape Transport •••••
Controls and Indicators
Load Procedures
Unload Procedures
Lights •••••••••••
Drive Board Description
Write Data Chain
Wri te Erase ••••••••••
Write Head Selection
DC Low Circuit
+12 Volt Path
+5 Volt Path
Low Voltage Effect
••••
DAC Reference Voltage Generation Circuit
Automatic Gain Control Circuit
Read Head Select Circuitry ••••••
Read Amplifier Circuit •••••
Phase Lock Loop Circuit ••.•••
Pump Down Circuit
Pump Up Circui t •••••
• ••••••
VCO Gene ra ti on •••••••
• ••••
Pump Up and Pump Down Signal Generation
Data Detection •.•••.•••••
• ••••
Drive Commands and Status
••

·.
.
...
··...
... . ..
. .. ... . ..
..
.....
··..
. . . . . .. .
·..
. ..
....

... ·. .

iii

2-1
2-1
2-1
2-2
2-3
2-4
2-4
2-5
2-6
2-6
2-7
2-8
2-9
2-10
2-10
2-11
2-11
2-12
2-12
2-12
2-13
2-13
2-14
2-14
2-15
2-16
2-16
2-17
2-17
2-18
2-19
2-19

2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.19.1
2.19.2
2.19.2.1
2.19.2.2
2.20
2.21
2.21.1
2.21.1.1
2.21.1.2
2.21.1.3
2.21.1.4
2.21.1.5
2.21.2

Tape Hub •••••••••••••••••••••••••••••••••••••••
Link Arms ••••••••••••••••••••••••••••••••••••
Tape Cartridge Insertion ••••••
• ••••••••••
Tape Load to Beginning of Tape ••••••
• •••••
Tape Motion
Read/Wri te Head ••••••••••••••••••••••••••••••
Initialization: Writing and Reading CALTRACKS ••
Wr i t i ng Da ta ••••••••••••••••••••••••• ••••••••••
Differential Signal Pair Description •••••••••••
Signal Interface Timing ••••••••••••••••••••
••
Serial Controller to Drive Communications
Basic Controller/Drive Communications Protocol
Contro11er-to-Drive Command Protocol
•••••
Drive-to-Contro1ler Status Protocol
•••
Change of Dri ve Sta te
•••••••••••••••••
Dr i ve De tec ted Errors
•••
••••
• •••
TK50 Commands •••••••••••
•••
• •••••••••••
TK50 Drive States
•••••
• • • • • ••••
Drive State Status
•••
•••••
• ••
Done ••••••••••••
•••
• ••••
Enable Write Gate •••••••••
Dropou t Sensed ••••••••••••
Track Boundary.....
• ••••
Load/Run State Change •••••••
Drive Error Status ••••••••••••

.... . .......
..
.......

2-20
2-20
2-20
2-20
2-21
2-21
2-21
2-23
2-26
2-26
2-29
2-29
2-30
2-30
2-30
2-30
2-31
2-32
2-32
2-33
2-33
2-33
2-33
2-33
2-34

General ••••••••••••••••••••••••••••••••
Err 0 r Cod e s ••••••••••••••••••••••••••••
Failure to Load to Beginning of Tape •••••••••
Failure to Load Tape into Cartridge ••••••••••
General Motor or Tachometer Failure
••••••
Motor A Failure ••••••••••••••••••••••••••
Motor B Failure ••••••••••••••••••••••••••
Drive Lost Control of Tape or Bad Tachometer
Excessive Drag in Tape Transport •••••••••••••
Failure to Stop Tape or Remain Stopped
Cartridge Insert Error
•••••••••
Cartridge Extract Error
•••••
Move ErrQr ••••••••••••••••••••
Deceleration Error
••••••••
Ree 1 Error ••••••••
Check Byte Error
•••••••.•
Unload Error ••••••••••••••••••
8155 Memory Error •••••••••••••
•••
• ••
8155 Timer Error
••••••
• ••••••••••••
Read Head 1 Error
•••
• ••••• • ••• •
• ••••••
Read Head 2 Error
•• ••• •••••••
•••••
• ••
Cartridge Insert/Extract Error •••••
• ••
EOT Sensed in Read/Write/Seek State
•••
BOT Sensed in Read/Write/Seek State
••••

3-1
3-1
3-1
3-2
3-2
3-3
3-3
3-3
3-4
3-4
3-5
3-5
3-6
3-6
3-6
3-7
3-7
3-7
3-8
3-8
3-8
3-9
3-9
3-10

...................................

CHAPTER 3 DRIVE UNIT REPAIR
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.11
3.2.12
3.2.13
3.2.14
3.2.15
3.2.16
3.2.17
3.2.18
3.2.19
3.2.20
3.2.21
3.2.22

........
.
.
.
. ...
.
.
.
. .....
.... . ....
. ....

3.2.23
3.2.24
3.2.25
3.2.26
3.2.27
3.2.28
3.2.29
3.2.30
3.2.31
3.2.32
3.2.33
3.2.34
3.2.35
3.2.36
3.2.37
3.2.38
3.2.39
3.2.40
3.2.41
3.2.42
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3 .6
3.3.7
3.3.8
3.3.9
3.3.10

Address Overflow Error
Address Underflow Error
Servo Error ••••••••
Failure in Tracking •••••
Command Error
Illegal Command
Write Lock Error
Write Gate Signal Timing Error
No Write Gate Error •••••
Error Sensing CALTRACKI
Error Sensing CALTRACK2
CALTRACKI Error ••••••••
CALTRACK2 Error •••••••
CALTRACK2 Offset Error
Tape Edge Error ••••••••
Top Tape Edge Tolerance Error
Drive is Overheating
BOT Sensor Error ••••••
No Hall Switch Signals
No Tachometer Pulses Present
Subassembly Remove/Replace Procedures
Drive Board Removal ••••••••••••••••
Front Bezel Removal ••••••••••••••••
Read/Write Head Bracket Assembly Removal
Tachometer Removal •••••••••••••••
Solenoid/Interposer Removal
Take-up Motor Removal
Stepper Motor Removal
Heat Sensor Removal
Supply Motor Removal ••••••
Receiver Assembly Removal

.....

3-10
3-11
3-11
3-11
3-12
3-12
3-12
3-13
3-13
3-14
3-14
3-15
3-15
3-16
3-16
3-17
3-17
3-17
3-18
3-18
3-19
3-19
3-19
3-20
3-20
3-21
3-21
3-22
3-22
3-23
3-23

CHAPTER 4 TQK50 CONTROLLER THEORY OF OPERATION
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.5.1
4.2.5.2
4.2.5.3
4.2.6
4.2.6.1
4.2.6.2
4.3
4.3.1
4.3.2
4.3.3

Gene r a 1 ••••••••••••••••.
The 80186 Microprocessor
Power-up Reset •••••••••
Microprocessor Cycle Time
Memory Chip Select Lines
Peripheral Chip Select Lines
In te rrup ts ••••••••
MPSC Interrupts
FPLS Interrupts
Non-Maskable Interrupt
DMA Operations
•••••
DMA Write
DMA Read
Memory
EPROM
Data Transceivers
RAM

...
....

4-1
4-3
4-3
4-4
4-4
4-5
4-6
4-6
4-6
4-7
4-7
4-7
4-7
4-7
4-7
4-8
4-9

4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.1.3
4.4.1.4
4.4.1.5
4.4.1.6
4.4.1.7
4.4.1.8
4.4.2
4.4.2.1
4.4.2.2
4.4.2.3
4.4.2.4
4.4.2.5
4.4.2.6
4.4.2.7
4.4.2.8
4.4.2.9
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8
4.4.9
4.5
4.5.1
4.5.1.1
4.5.1.2
4.5.1.3
4.5.2
4.5.3
4.5.4
4.5.5
4.5.5.1
4.5.5.2
4.5.6
4.6
4.6.1
4.6.2
4.7
4.7.1
4.7.2
4.7.3
4.7.4

Control and Status Register ••••••••••••••••••••
Miscellaneous Control Register •••••••••••••••
Dri ve Erase ••••••
•••••••••••••• ••• ••
• ••
Drive Write Gate •••••••••••••••••••••••••••
Enable Gap Detect ••••••••••••••••••••••••••
Clear SA Initialization ••••••••••••••••
Clear IP Initialization •••••••••••••••••
Di ag nos tic Mode •••••••••
• •••••
Reset LED 1 • ••• ••••••••
••••
• ••••••••
Rese t LED 2 ••••••••••••••••••
• ••••••••••
Unit Number and Status Register ••••••••••••
SA Write Initialization ••••••
.•••••••
IP Read Initialization •••••••
• ••
Drive Erase..................
• ••••
Drive Write Gate ••••••••••••••••••
Q-bus Interrupt Request •••••••••
Q-bus Interrupt Request Done
••••
Q-bus Memory Parity Error ••••••••••••••
Drive Cable In
•••••••
Unit Number ••••••••••••••••
Vector Register
•••
• ••••••
Hardware Revision Register
••• ~
SA Register •••••••.•••••••••••
• •••
I P Reg i s te r •••••••••••••••••••
• •••••••••••
Module Starting Addresses/Interrupt Vectors
Unit Number DIP Switch •••••••••••••••••
Revision Level Switch Pack
••••.
Q22 Bus Interface Logic ••••••••••••
FPLS Control Logic ••• •••••••••••
• •••••
Bus Mastership Acquisition Phase
•••
Data Transfer Phase ••••••••••••••••••••••••
Bus Mastership Relinquish Phase
Error During Q-bus DMA Transfer •••
FPLS Interrupt •••••••••••••••••
Q22 Bu s Reg is te r •••••••••••••••
DMA Address and Data Registers
•••
DMA Address Register
•••••••••
DMA Data Register
••••••••••
Q-bus Interrupt Logic
•••••
• •••••••
Tape Dri ve Interface •••••••••••••••••
7201 Multi Protocol Serial Controller
Differential Drivers and Receivers
Diagnostic Hardware ••••• "........
• ••
Diagnostic Indicators ••••••••••
• ••
Miscellaneous Register Loopback
•••
7201 MPSC Diagnostic Loopback
•• ••
• •••
Soft Grounds ••••.•••••••••••••••••••••

....
....

.....

4-9
4-9
4-10
4-10
4-10
4-11
4-11
4-11
4-12
4-12
4-12
4-12
4-12
4-13
4-13
4-13
4-13
4-13
4-13
4-13
4-13
4-14
4-14
4-16
4-16
4-20
4-20
4-21
4-21
4-22
4-23
4-24
4-24
4-24
4-25
4-26
4-26
4-26
4-26
4-27
4-27
4-29
4-30
4-30
4-30
4-31
4-32

APPENDIX A TQKSO DETAILED BLOCK DIAGRAM, TKSO EXPLODED VIEW
APPENDIX B TKSO SUBSYSTEM ERROR CODES AND STATUS
INDEX
FIGURES
2-1
2-2
2-3
2-4
2-5
2-6
2-7

2-8
2-9
2-10
2-11
4-1

4-2
4-3

A-I
A-4

System Integrated TKSO •••••••••••••••••••••••••
Desktop TK50 •••••••••••••••••••••••••••••••••••
Block Diagram: Drive Board •••••••••••••••••••••
TK50 Tape Drive Transport ••••••••••••••••••••••
TK50 Front View ••••••••••••••••••••••••••••••••
TK50 Rear View •••••••••••••••••••••••••••••••••
Physical Tape Configuration ••••••••••••••••••••
Recording Direction ••••••••••••••••••••••••••••
Signal Interface Timing {A-P} ••••••••••••••••••
Signal Interface Timing {Q-U} ••••••••••••••••••
Frame Format of Data Coming from Controller ••••
TQK50 High Level Block Diagram ••••••••.••••••••
Q-bus Timing •••••••••••••••••••••••••••••••••••
Read Data Timing •••••••••••••••••••••••••••••••
TQK50 Detai led Block Diagram •••••••••••••••••••
TK50 Exploded View •••••••••••••••••••••••••••••

2-3
2-4
2-5
2-6
2-7
2-11
2-23
2-24
2-27
2-27
2-29
4-3
4-23

TK50 Related Documentation •••••••••••••••••••••
States of Lights •••••••••••••••••••••••••••••••
TK50 Signal Definition •••••••••••.•••••••••••••
Differential Signal Pairs ••••••••••••••••••••••
Signal Interface Timing ••••••••••••••••••••••••
TK50 Command s ••••••••••••••••••••••••••••••••••
Non-Error Drive States •••••••••••••••••••••••••
Send Status Byte Bit Assignments •••••••••••••••
Miscellaneous Control Register Bit Assignments •
Common Jumper Pack Settings ••••••••••••••••••••
Address/Vector Worksheet •••••••••••••••••••••••
Floating CSR Address Chart •••••••••••••••••••••
Unit Number Switch Pack Settings •••••••••••••••
Revision Level Switch Pack •••••••••••••••••••••
Drive Error Sub-code Values ••••••••••••••••••••
Controller Internal Status Byte ••••••••••••••••
Drive Error Code Byte ••••••••••••••••••••••••••
Recoverable Dri ve Faul ts •••••••••••••••••••••••
Unrecoverable Drive Faults •••••••••••••••••••••
Dri ve Flag s ••••••••••••••••••••••••••••••••••• ,.
U/Q Port Generic SA Error Codes ••••••••••••••••
Controller Specific SA Error Codes •••••••••••••

1-3
2-9
2-25
2-26
2-28
2-31
2-32
2-33
4-10
4-17
4-18
4-19
4-20
4-21
B-1
B-2
B-2
B-3
B-4
B-4
B-5
B-6

4-28
A-3
A-4

TABLES
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
4-1

4-2
4-3
4-4
4-5
4-6
B-1
B-2
B-3
8-4
B-5
B-6

B-7
B-8

vii

CHAPTER 1
INTRODUCTION AND SPECIFICATIONS

1.1

GENERAL

The TK50 Tape Drive Subsystem is a mass storage device. It uses
removable 94.5M byte tape cartridges to provide backup storage
capacity and a software distribution capability for Digital's
low-end computer systems.
The subsystem consists of three components: the TK50 Tape Drive,
the TK50 Tape Drive Controller, and an interface cable that
connects the tape drive to the controller. The TK50 Subsystem may
reside entirely within· the system unit of a MicroPDP-ll or
MicroVAX (I or II); or it can be set up as an external add-on
peripheral that can be plugged into other systems, including the
PDP/II-23+. The drive unit and the controller are the only field
replaceable units (FRUs) in the subsystem.
Future updates of this manual will describe controllers used with
buses other than the Q-bus. This version contains information on
the TK50 Tape Drive and the TQK50 controller (M7546).
This manual does not contain installation or remove/replace
procedures for the two FRUs.
Since the TK50 fits a 5-1/4 inch
footprint and is power-plug compatible with the RX and RD50 series
disk drives, it may reside in a variety of different systems. It
may replace the RX50 in certain configurations.
Refer to the appropriate system documentation for installation and
FRU remove/replace
procedures.
For example,
if
you are
troubleshooting a TK50 subsystem problem when the TK50 is in a
MicroPDP-ll computer, refer to your Micro-II Pocket Service Guide.
NOTE
See Chapter 4 for detailed information
about the TKSO Subsystem controller(s).
See Chapters 2
and 3 for detailed
information about the TKSO streaming
tape drive.

1-1

The storage medium is a tape cartridge containing a magnetic tape
that is 1/2 inch wide and 600 feet long. The tape cartridge is
about 4 by 4 inches square, and is labeled CompacTape.
1.2

TK50 TAPE DRIVE UNIT SPECIFICATIONS

Tape speed

75 inches per second (in/s)

Bi t densi ty

6667 bits per inch (bits/s)

Data rate

500 Kbits/second; 45 Kbytes/second

Number of tracks

Media type

Single reel, 1/2 inch, 600 feet long

Capacity

131
megabytes unformatted,
megabytes formatted

Read/wri te gap
spacing

0.3 inches

Recording method

MFM, bit
recording

Power required

+5 Vdc, 1.2 amps (typ),
1 .4 amps (max)
+12 Vdc, 2.0 amps (typ),
2.4 amps (max)

1.3

94.5

serial

data,

serpentine

DRIVE TO CONTROLLER INTERFACE SPECIFICATIONS

Interface type

Differential using
and rece i vers

Connector type

26-pin flat ribbon, polarized; right
angle header; PN 12-16832-02

Cable type

26-wire flat ribbon; PN 17-00034-02;
max length 10 ft

Receiver type

AM 26LS32, differential

Driver type

AM 26LS3l, differential

1-2

RS-422

drivers

Table 1-1

TK50 Related Documentation

Title

Order Number

Contents

TK50-D, -R Tape Drive
Subsystem Owner's Manual

EK-LEP05-0M

Provides installation,
service, use, and
programming
information for the
desktop and
rack-mounted versions
of the TK50.

TK50 Tape Drive
Subsystem User's Guide

EK-OTK50-UG

Provides information
on using the TKSO Tape
Drive. Written for
operators and
secretaries with
little or no technical
background.

TK50 Tape Drive
Subsystem Illustrated
Parts Breakdown (IPB)

EK-OTK50-IP

Provides an exploded
view drawing of the
TK50 Tape Drive
Subsystem and a
comprehensive parts
list.

TK50 Tape Drive
Subsystem Field
Service Print Set

MP-20S4 (Dri ve
uni t) MP-20 55
(M7546 module)

The complete set of
prints needed to
troubleshoot the TKSO
Tape Drive Subsystem
to the component
level.

1-3

CHAPTER 2
DRIVE UNIT
THEORY OF OPERATION

2.1

GENERAL

This chapter provides theory of operation information about the
TK50 Tape Drive. The controller(s) to which the drive connects is
discussed in succeeding chapters.
Use the block diagrams and mechanical drawings referenced to help
you understand the text.
For troubleshooting, the Field Service
Print Set takes precedence over any block diagrams or mechanical
drawings in this book.
This chapter describes how the various components in the TK50
Drive Unit interact during operation.
Following the overview
theory is more specific information including signal definition
and timing, command summary and explanation, and a discussion of
the basic drive/controller communications protocol.
Chapter 3 provides the information necessary to remove and replace
a subassembly that failed in the drive.
2.2

UNIT DESIGNATIONS

This section lists and describes the unit variations in which the
TK50 Tape Drive Subsystem is available.
2.2.1
TK50
TK50-AA
TK50-AX
TK50-D
TK50-R

Drive Unit Variations
Plain drive, ordered with no system.
Single unit in packaging with tape cartridge.
Single unit in packaging, no tape cartridge.
Desktop version of TK50 -- external drive
version.
Rackmount version of TK50 -- external drive
version.

2-1

2.2.2

M7546 Controller

TQK50-AB

This variation is the controller and cable for a BA23
enclosure and an external TK50-D, -R drive, and
accommodates the MSCP Q-bus. One controller handles
one TK50 drive.
Use this kit when configuring a
MicroVAX system in a BA23 enclosure.

TQK50-PB

MicroPDP-ll

This kit is the same as the one above, except that
the controller
cable accommodates
a PDP-ll/23+
system.
Use this kit when configuring a PDP-ll/23+.

17-00484-01

This 2.75
meter (9 foot) host-to-external-drive
interface cable is a 50-pin subminiature male to a
50-pin "D"
subminiature female shielded, molded
cable. This cable comes with the TK50-D, TK50-R
subsystem.

TQK50-AA

Controller and cable in BA23 cabinet,
with BA23 specific access door.

TQK50-BA

Controller in BAl23 cabinet, 30 inch cable.

TQK50-BB

Controller in BA123 and external drive, 21 inch cable
with I/O panel insert.

TQK50-CB

Controller in cabinet mount BA23 with H3490 I/O panel
and external drive. Also, 36 inch cable with I/O
panel insert.

TQK50-RB

Controller in non-FCC compliant Q-bus enclosure with
no I/O panel, 120 inch cable with bracket to mount
I/O panel insert on cabinet rails. For Field upgrade
only.

30 inch cable

The TK50 Tape Drive Subsystem must always be ordered in two
separate pieces: the drive unit itself and, separately, the
controller. For example, if customers own a MicroVAX I system
(BA23 enclosure) and want to add an external TK50 Subsystem, they
would order the following parts.
1.
2.
3.

TK50-D -- Desktop, external version of drive
17-00484-01 -- External drive-to-system cable.
TQK50-AB -- Controller and internal cable.

2-2

2.3

CABLING

In the system-integrated version of the TK50 (Figure 2-1), the
drive is connected to the controller via a 26-pin flat ribbon
cable. When the TK50 is in a tabletop or rackmount enclosure, the
configuration includes an FCC shielded cable that connects the
separate enclosure to the host system (Figure 2-2).

Figure 2-1

System Integrated TK50

2-3

GREEN----...ioI..
LED

CARTRIDGE
RELEASE
HANDLE
LOAD/UNLOAD SWITCH
AND RED LIGHT

Figure 2-2

TABLE TOP VERSION
POWER SWITCH
SHR-0306-84-B

Desktop TK50

The signal lines on these cables provide serial commands and data
sent from the controller to the drive, via differential lines.
The drive recognizes the commands and data by interpreting the
differences in voltages on the lines.
The differential method
provides good noise isolation.
See Table 2-2 and Sections 2.16
and 2.17 for signal definition, connector pin-outs, and timing
diagrams.

2.4

POWER

The TK50 has no internal power supply.
The host system must
provide the TK50's required voltages, which are: +12 Vdc at about
2 amps and +5 Vdc at about 1 amp.
The power connector is the same
as the RX and RD50 series floppy diskette drives.
The drive uses
a 4-pin power plug (PN 12-18855-00), located at J7 on the drive
board, to accept power provided by the host system. If an external
TK50-D, or -R drive is used, the ac power source should be the
same as that used for the host computer.

2.5

PHYSICAL DESCRIPTION

The TK50 drive unit consists of two major components: the tape
transport and a printed circuit board attached to the bottom of
the drive. These two assemblies together are one FRU.
The
controller that resides in the system backplane is the other FRU.

2-4

2.5.1

Drive Board

The drive board is connected to the bottom of the
discrete analog and digital components.

drive and has

This module includes an 8751 microprocessor that interprets
commands, runs on-board diagnostics, and controls the entire drive
operation. The write and read circuits necessary to translate data
to and from the MFM format reside on this board. Also included is
an 8155 I/O and RAM chip used to sense various conditions,
including Beginning of Tape/End of Tape (BOT/EOT), Handle Switch
Open/Closed, and Load/Unload Switch Open/Closed. The circuits on
this board are detailed as they apply to a specific operation.
Figure 2-3 is a simplified block diagram of the entire drive,
including the drive board.

VCO EN
MISC
SNS
CNTRL

TACH

8751
RD EN

INTO

NRZ RD DATA

VCO
+
DATA
SEP

RD CLOCK

•

MPU SNS

PLS-L

(AMPL, TRACKING)
SER CMD

SER
STATUS
(ECHO)

EN
DUAL
DAC
GAP

FWD

INTI

BWD
CHAN

-L
8155
MPU

8X256
RAM

600+ FEET
OF TAPE

WRT GATE
MISC
SENSE
CNTRL

WRT/ER

SERVO
TIMER

ENCODE
WRT
WRT DATA (NRZ)
COMP
-----------~ (PAL'S)

WRT CLOCK

ERASE GAP

ONE 'LS 32
QUAD DIFF RECVR

ONE 'LS 31
QUAD DIFF

DRVR

16 MHZ
SH R-0212-85

Figure 2-3

Block Diagram: Drive Board

2-5

2.5.2

Tape Transport (Figure 2-4)

The
tape drive
transport encompasses
the
mechanical and
electromechanical components that allow the TK50 to perform its
functions; that is, to read and write data to magnetic tape.
These components include: the magnetic read/write head and its
stepper motor; the take-up reel and its motor; the tape hub (which
serves, effectively, as the supply reel when a tape cartridge is
inserted) and its reel motor; and the tachometer, which provides
feedback to the 8751 microprocessor regarding tape speed.

LEADER, TAKE-UP

REEL, TAKE-UP

EXTERNAL
SHIELD
ASSEMBLY
TACHOMETER
ASSEMBLY

BRACKET &
HEAD ASSEMBLY

TK50 DRIVE
MODULE
INSULATOR
ASSMEBLY
BEZEL
ASSEMBLY

SH R·0213·85

Figure 2-4

2.6

TK50 Tape Drive Transport

CONTROLS AND INDICATORS

On the front of the TK50 Drive is a combination Load/Unload switch
and LED indicator (Figure 2-5).
When power is applied and a tape
cartridge is in place, the Load/Unload switch is used to load the
tape for operation.
Loading the tape involves coupling two
leaders together (one is on the beginning of the tape and the
other is part of the drive), then bringing the tape to the
Beginning of Tape (BOT) indicator.
Unloading the tape· involves
rewinding to BOT, then unbuckling the two leaders so the tape can
seat in the cartridge for removal.

2-6

Also on the front of the drive is the cartridge release lever or
handle.
This handle must be raised to insert or remove a tape
cartridge, and lowered to lock the cartridge in place. The handle
must never be raised when the light is on or blinking, or when the
system power is off.

Figure 2-5
2.6.1

TK50 Front View

Load Procedures

When power is turned on and no cartridge is in the drive,
the red light goes on steady during initialization (about
two seconds).
Then the red light goes off and the green
light comes on.

With the
handle.

Insert the cartridge. As soon as the cartridge is within
about 1/2 inch of being fully inserted, the solenoid
clicks, the red light goes on steady, and the cartridge
locks in place. The green light is off.

4•

Lower the handle so the reel drive engages the tape
cartridge hub. The red light goes off, and the green
light goes on. You may lift the handle and remove the
cartridge now, if desired.

Press the switch to the in position.
on and the green goes off.

red light off and the green

2-7

light on, lift the

The red light goes

2.6.2

Tape loads to BOT (beginning of tape). When the tape is
successfully loaded and waiting at BOT, the green light
is on steady. During the time the drive is responding to
a command to read or write, including the time to seek
the correct part of the tape, the green light is
blinking.
Unload Procedures

Red light is on. Press the switch to the out position.

Red light and green light both blink (slowly, but not
together) as the tape is being rewound to BOT. This
rewind operation can also be initiated from software. The
lights blink in either case.

Red light stays on and green light goes off as the tape
continues rewinding to the unload position.

When the tape is completely rewound into the cartridge,
the red light goes off. Then the green light comes on.

Raise the handle. The cartridge comes
easily grasp and remove it.

Lower the handle. The green light
that there is power to the drive.

out far enough to

is still on

NOTE
Do not power down the TK50 when the tape
cartridge is still in the drive. Always
remove the cartridge before powering
down.

2-8

to show

2.6.3

Lights

Table 2-1 describes the state of the lights.
Table 2-1

States of Lights

Red

Green

Conditions

Off

No power to the drive.

Off

The handle can be lifted.

Off

Do NOT lift the handle:
Self-test (initialization) is running
Cartridge is inserted but handle is
still up
-- Tape is loading or unloading
-- Tape is stopped.

Tape loaded successfully (at BOT, no
controller command yet).

Flashing

Tape motion (except rewind) -- Read/Write
commands are being processed. Irregular,
fast blinking means calibration is
occurring.

Flashing

Tape is being rewound.

Fast flash

Off

Fault.

In summary, when both lights are off, there is no power to the
drive. When one or both lights are on, the red light indicates
handle and fault conditions.
•

Red light
lifted.

on steady always

means the handle

may NOT be

•

Red light off steady means the handle MAY
insert or remove a cartridge.

•

Red light flashing fast always means a fault condition;
the handle may NOT be lifted. Double toggling the switch
clears the fault.

•

Blinking light means
can soon be lifted).

be lifted to

rewind is occurring (and the handle

2-9

The green light indicates tape and power conditions.
•

Green light on steady means two things.
1.

Power is on and the handle may be lifted to
insert or remove a cartridge (if red light is
off).

Tape has loaded properly (if red light is on).

•

Green light off steady means the tape is not being
used (it is stopped, initialization is occurring,
tape is loading or unloading, or fault).

•

Green light blinking always means that tape is in
motion.
1.
2.
3.

2.7

Calibration is occurring.
Read/write activities are being performed.
The tape is rewinding to BOT.

DRIVE BOARD DESCRIPTION

Refer to the drive board schematics in the TK50's Field Service
Print Set (MP-2054-CS) while reading this section.
In the following logic description, the component being described
is followed in parentheses by the circuit schematic sheet number
and location zone. For example, E13 (1-B8) is in Field Maintenance
Print Set MP-2054, Circuit Schematic (CS) sheet 1, location zone
B8.
2.7.1

Write Data Chain

Write data comes into the drive's logic board via the differential
signal cable on 26-pin connector Jl' (PN 12-16832-01) (see Figure
2-6).
It connects to pins one and two of the differential
receiver at E13 (1-B8). The shift register at E4
(to which the
output of the differential receiver is connected) accepts serial
data and outputs a five-bit parallel data pattern into the
Programmable Array Logic (PAL) at E9 (1-B5). The data is clocked
through the shift register by the 500 KHz clock.
The 500 KHz
clock is divided down by the PAL from the 24.0 MHz crystal
oscillator. The 500 KHz clock is the write pulse rate, or write
data rate.
The M7546 controller that is in the host computer
accepts this clock also, and must keep up with it.

~
.... -..................:wJr.rnn
W@J]j "'''-''-'-DO II
~ ........................
~~~
1iiiiiiiiii~~~~iiiiiii7
.

POWER CONNECTOR (J71

J1 (26 - PIN SIGNAL CONNECTOR)
SH R-0215-85

Figure 2-6

TK50 Rear View

The PAL at E9 accepts the five parallel bits from the shift
register at E4 (1-B6), and from those bits generates WR PLS L.
This PAL performs the precompensation and encoding needed to
translate data to MFM format.
The signal WR PLS L is connected to pin 3 of the 74S74 flip-flop
at E19 (2-D4), which is set up as a toggle flip-flop.
The sense
of the flip-flop switches each time WR PLS L goes high.
The
toggling of E19, in conjunction with the 7426 at E23 (2-D4) and
the write driver circuit, pumps current alternately into each coil
of the selected write head. This toggle action results in the
transitions necessary to write data to tape.
2.7.2

Write Erase

The PAL at E9 controls the write erase function. When the signal
WR ERASE L (write erase) is asserted, the PAL shuts off write
pulses.
Write current, however, is still flowing to the write
heads. Therefore, an erase function is performed; that is, write
with no data. This function is used to write gaps on tape. When
the write erase signal is released, the PAL goes back to MFM
encoding and resumes the generation of write pulses.
2.7.3

Write Head Selection

The write heads are selected by the signals WR HD I SEL or
WR HD 2 SEL (E23 pins 8, 9, 10; pins 11, 12, 13). Head one writes
data in the forward direction, head two in the reverse direction.

2-11

With the signals HD 1(2) SEL H asserted high, a logic 1 is applied
to pin 10 or pin 13 of the 7426 at E23.
E23 then outputs a logic
0, which grounds the centertap of the selected write head.
Current is then alternately applied to each side of the write head
coil, through the transistor pairs at E30 (pins 8, 9, 10 and 12,
13, 14), or E30 (pins 5, 6, 7 and 1, 2, 3), each time the sense of
flip-flop E19 switches.
This provides a constant current source
of 15 milliamps to
each write head coil.
The alternate
application of the current results in the transitions needed to
write data to magnetic tape.
2.7.4

DC Low Circuit (Sheet 2)

The DC Low circuit senses a low voltage condition (either +5 or
+12 V dropping below their acceptable levels) and shuts down the
functions of the tape drive.
It shuts down the motor current,
resets the 8751 microprocessor at E1
(1-D6), and disables the
write current circuitry.
2.7.4.1 +12 Volt Path -- As long as +12 volts doesn't go below an
acceptable level (about 10 V) the transistor at E6 (pins 1, 15, 16
I-AI) is turned on.
If the voltage drops lower than the base-emitter junction voltage
of that transistor, E6 (1, 15, 16) turns off.
Pin 1 rises,
turning on E6 (6, 7, 8).
When E6 (6, 7, 8) turns on, its pin 7
drops, asserting the signal DC LOW L.
A 330 nf capacitor (C47) provides positive feedback and some
hysteresis. When DCLOW goes to a logic level 0, the capacitor
discharges, dumping some charge back to pin 16 of E6, and turning
it off harder.
The hysteresis prevents the transistor from
oscillating if there is noise at its base (pin 16) when the
voltage drops.
The hysteresis, then, is to make sure that the
DCLOW signal is of a long enough duration.
Also as E6 pin 1 rises (pulled up by R19 to +5 V), transistor E6
(pins 2, 3, 4)
is turned on and the reset signal RST H is
asserted. The 1 MF capacitor at C3 (1-A3) discharges. C3 holds
the reset line to the 8751 microprocessor asserted on power-up
until +5 volts has ramped up completely and cleanly.
2.7.4.2 + 5 Volt Path -- The signal DCLOW is asserted through the
same transistor pair as +12 V (E6).
The +5 V low circuit consists essentially of E6 (9, 10, 11) and E6
(12, 13, 14).
If +5 V drops lower than about 4.6 V, E6 pin 12,
and E6 pin 11 reach about 3.9 V. This asserts DCLOW through E6
(1, 15, 16) and E6 (6, 7, 8).

2-12

2.7.4.3
Low Voltage Effect -- When DCLOW is asserted, it places
a low on the set input of the 74874 flip-flop at E19, pin 10
(2-D4).
When the set input is asserted, it causes the flip-flop
to assert pin 9 of the PAL at E9. When this pin is asserted, the
PAL shuts off the 1 MHz clock.
In this way the -1.25 volt
reference is shut down. DCLOW also disables the write head select
circuit at E23 pins 13 and 9.
When the PAL shuts off the 1 MHz clock, it also shuts off the
-1.25 reference voltage used by the DACs which drive the reel
motors. Regardless of what else happens at this point, the motor
current is shut down when the minus voltage reference is removed.

2.7.5

DAe Reference Voltage Generation Circuit

This section explains how the minus reference voltage is generated
and how the DACs use that voltage to energize the reel motors.
The minus reference voltage is generated from the 1 MHz clock that
originates at pin 17 of the PAL at E9 (1-B5).
When the 1 MHz signal rises to about 4 V, it charges capacitor C6
(plus voltage on pin 1, minus voltage on pin 2). When the 1 MHz
signal comes down, C6 discharges, and, through diode D5, charges
Cll.
When the 1 MHz signal goes up again, D5 is reve~se biased
and Cll holds the charge.
This provides a minus 2.1 V constant
voltage source at pin 1 of Cll.
The minus voltage source goes to the lK resistor at R3 (3-D6).
The diode at D4 develops a -1.25 reference voltage for the
multiplying Digital-to-Analog Converter at E8 (3-D5). The inputs
to the DAC
at E8 are the data bus
bits from the 8751
microprocessor. The micropocessor selects the DAC, then writes
numbers into it, using the data bus.
The DAC acts like a
programmable current source.
Its output current through the
op-amps at E16 (3-03) controls the speed of the reel motors. Thus
the microprocessor can speed up or slow down the motors by writing
larger or smaller numbers into the DAC.
The signals Control A and Control B drive the two reel motors
(control A for motor A and control B for motor B). These signals
are actually connected to three darlington transistors on the
motors' printed circuit board. The signals Feedback A and Feedback
B are current return signals from the motors that provide a
reference to the DAC.

2-13

2.7.6

Automatic Gain Control (AGe) Circuit (Sheet 2)

The 4024 at E12 (2-07) binary ripple counter and resistor network
(R31 -- R36) make up a digita1-to-ana10g converter (DAC).
The
existence of the AGC circuit means that the microprocessor has
only to set up a value initially by asserting CLR AGC H (E12 pin
2), then applying the signal STP AGC L to step the counter up to
the desired gain value.
The gain value is translated to a voltage across R21 (12K) and is
applied to the op-amp at E16 (2-C8)(pin 10).
The LM324 at E16
(2-C8) compares the gain voltage (set by the microprocessor
through E12) to a voltage developed by the intensity with which
transistors Q2 and Q3 are turned on. Q2 and 03 are turned on by
developing a voltage across R104 and R105. These voltages are
averaged together and then applied to E16 pin 9.
The intensity with which 02 and 03 are turned on can be controlled
by the op-amp.
The output of the op-amp (pin 8) is connected to
resistors R94 and R95. The higher the voltage goes, the harder Q2
and 03 are turned on.
This configuration, then, works to control
the gain of this pre-amp circuit:
The microprocessor clears the
counter at E12 and steps it up to a desired gain. The gain value
is translated to an analog voltage that is then applied to the
op-amp at E16.
The output of the op-amp turns 02 and 03 on with
the appropriate intensity, which results in a value being averaged
at the junction of R94 and R95, then applied to pin 9 of the
op-amp.
2.7.7

Read Head Select Circuitry (Sheet 2)

The quad-transistor package at E27 (sheet 2 -- lower left) is the
read head select circuit.
Unlike the write head, the read head
coil is not centertapped. E27 (5, 6, 7) and E27 (8, 9, 10) select
read head 1; E27 (1, 2, 3) and E27 (12, 13, 14) select read head
2.

The two transistor pairs are biased at different levels, so either
one of the pairs may be selected by a single control signal (HD 1
SEL H).
For example, the bases of the top pair of transistors (read head
1) are set at about 3.1 V and are not switchable. The other pair,
though, (head 2) are influenced by the select signal HD SEL 1 H.
When HD SEL 1 H is a logic 1, then about 5 V is applied to E27 pin
2 and E27 pin 13.
In this case, the top two pairs of transistors
are turned on because the emitters of all four transistors are
tied together and pulled up to +12 V. If HD 1 SEL H is low,
however, the bottom pair of transistors is turned on and head 2 is
selected.

2-14

2.7.8

Read Amplifier Circuit (Sheet 2)

The differential preamplifier circuit feeds into the differential
input of the 3470 read amplifier chip at E26 (2-B5).
Pins 3 and 4 on the 3470 control the gain of the amplifier. RlOO
and RlOl are controlling the gain of the 3470: if their combined
resistance was lower,
the gain of the read amplifier would be
higher.
The output of the first stage of the 3470 is on pins 16 and 17
The read amplifier chip raises the
(differential output).
approximately 40 millivolt signal on its inputs (pins 1 and 2) to
about 1 V peak-to-peak on each line, or 2 V differential
peak-to-peak at ouput pins 16 and 17.
The first stage output is connected to transistors E18 pin 6 and
E18 pin 3, and then to inductors L5 and L6. These inductors, along
with transistors E18, form a differentiator circuit.
This differentiator circuit takes the signal from the 3470
circuit, amplifies it, and performs a differentiating function.
The differentiated, amplified differential analog read signal now
passes through a low pass filter composed of L3, L4, C40, C39, Ll,
L2, and C38.
The output of the differentiator and filter circuit (ANAl and
ANA2) goes back to the 3470 (pins 14 and 15).
With the 3470's
pins 12 and 13 tied together,
this 3470 stage acts like a
comparator and is used as a zero crossing detector for peak
detection.
The differentiated and filtered signals ANAl and ANA2 are also
connected to an amplitude detection circuit consisting of E18 9,
10,11; and 12,13,14.
The purpose of the 3470 chip is to generate the digital signal
RD DATA PLS H. This signal represents the data read from the tape
and it consists of a positive pulse for each detected peak.
Pin 10 of the 3470 (RD DATA PLS H) outputs a 100 ns pulse when a
zero-crossing detection "is found on its input pins 14 and 15. The
position of this pulse represents the timing of the analog peaks
that were read from the tape. This raw data is sent to the phase
lock loop where the clock signal is recovered and the MFM data is
decoded and sent to the controller in the host system via the
serial bus.

2-15

2.7.9

Phase Lock Loop Circuit (Sheet 4)

The read data pulse from the read amplifier circuit is connected
to the PAL at E25 (4-D4)(pin 9) in the phase lock loop circuit.
The 500 KHz write clock is also connected to the PAL at E25 (pin
8)•

Whenever there is a gap going into the phase lock loop (a burst of
non-existent or invalid data), the phase lock loop locks in high
gain mode on the 500 KHz write clock. This is so the integrating
capacitor C25 stays charged nominally, keeping the voltage control
oscillator (VCO) running at a nominal frequency.
Keeping the
integrating cap
charged nominally means that
not as much
correction has to occur when the preamble (first burst of valid
data) to the data field comes along.
On the left side of sheet 4, three signals enter the analog
circuitry: Pump Up L, Pump DN L, and RD EN H.
The PAL at E29
(4-D7) sources these signals.
Pump Up L and Pump Dn L are the
phase error correction signals to the charge pump. These signals
are in place so that the frequency of the VCO can be changed. The
signal RD EN H is a gain control signal for the charge pump. It
changes the gain of the charge pump to about 5 to 1, so that in
high gain mode, there is about five times more current for the
corrections than when in low gain mode.
In the gap (and during the early part of the preamble), the phase
lock loop is in high gain mode. When in high gain mode, the Read
Enable signal is low. When the Read Enable signal goes high, the
circuit is in low gain mode.
The circuit goes into low gain mode
about halfway through the preamble and stays there during the data
field.
When the phase lock loop is locked on the 500 KHz clock (write
clock) the loop is in high gain mode and RD EN H is low. With RD
EN H low, E22 (2,3,4) is turned off. With E22 (2,3,4) turned off,
there are two constant current sources providing charge to the
loop filter consisting of C24, R53, and C25.
2.1.10

Pump Down Circuit

When the signal Pump On L goes low, transistor E22 (8,7,6) is
turned off, enabling the pump down constant current source.
A resistor-divider network is connected to the base of E22 (11,
10, 9), which produces about 2.9 V at the base of E22 (pin 9).
There is a 0.7 V drop across the base-emitter junction of E22,
producing about 2.1 V at pin 10.
This results in a current
through diode 010 and resistors R79 and R83 in high gain mode, and
through R79 alone in low gain mode.

The collector of transistor E22 is connected to the filter cap at
C25.
C25 is the major integrating cap in this circuit.
R53
develops the phase correction voltages for the VCo.
2-16

80 when a pump down occurs (Pump Dn L goes low), a pump down
correction is telling the veo clock to slow down, through the
748124 chip at E2l. The output of E2l (VeO OUT H) is connected to
the clock input of the PAL at E25.
When the Pump Dn signal is not asserted, E22 (6, 8, 7) turns on,
pulling up pin 10, reverse biasing the base-emitter junction of
E22 - 10 and 9, and turning the constant current source off.
2.7.11

Pump Up Circuit

The constant current source for the pump up circuit consists of
resistors R49 and R50, diodes 07 and D8, and transistor Ql.
A resistor-divider network is connected across the base (pin 1) of
transistor Ql.
When the Pump Up signal (Pump Up L) is asserted
low, it pulls the base of Ql down to about 4.5 V. When the base
is pulled to 4.5 V, a drop across the base-emitter junction means
that the emitter voltage is about 5.2 V.
At this point, there is 5.2 V on one side of the parallel network
(R49, R50, 07, 08) and 12 V on the other side (R49 and R50 pins
2).
The current [determined by 6.8 volts across R50
(low gain
mode) or that current plus the six volts which is across R43 in
high gain mode] goes to the loop filter through the collector at
Ql.
A pump up correction causes the charge to be dumped into
integrating capacitor e25 and develops a phase error correction
voltage across R53.
Both the charge being dumped and the phase
error correction voltage cause the VCO to run faster.
In the case of pump down, the cap at C25 was discharged slightly.
In this case, however, e25 is charged slightly.
2.7.12

veo Generation

The VCO E21
(4-C3) chip's output frequency is essentially
controlled by the voltage at it's input pin 2.
The higher that
voltage is, the higher frequency its clock output will be (pin 7).
The circuit that consists oE E22 (12, 13, 14)
(4-A4), R48, R55,
and 09 is a compensation circuit that compensates fo~ differences
in VCO chips' center frequencies.
It also eliminates the need for
adjustments to the frequency-determining capacitor that is part of
the VCO circuit.
Optimum range and linearity are achieved by operating the VCO such
that the center frequency occurs at 3.2 input volts. To achieve
this goal, and to compensate for differences between VCO chips, a
varactive diode (09) is included in the circuit.
This diode
adjusts its capacitance based on how much reverse bias voltage is
across its capacitor (09).
2-17

The 8751 microprocessor sends out the Read Enable control signal
(RD EN H) by synchronizing on the occurences of the gap interrupt
(the s i g na 1 GAP Lon the mi c rop'roc e s so r • s i npu t pin 13). Wh e n the
microprocessor is first locking on the gaps (after the tape has
come up to speed), it looks for the assertion of the gap interrupt
signal, sets an internal timer running, waits until about halfway
through the preamble, then asserts read enable.
When Read Enable is asserted, transistor E22 (2, 3, 4) turns on.
When the transistor turns on, it pulls the anode (pin 2) of the
IN4l52 diode at D7 (junction of R49) low, and pulls the cathode of
DlO and R83 up, so it effectively disconnects R49 and R83 from
being part of the network for the pump up and pump down current
sources.
On the lower half of the constant current source (DlO), 2.1 V are
present at the emitter of E22 (pin 10). But instead of 5 milliamps
of current from the constant source,
there is only about 1
milliamp.
This lower current results because the diode DI0 and
resistor R83 have effectively been eliminated from the circuit.
The result is that there is only 1 milliamp of correction current
going to the loop filter.
The upper half of the constant current source (D7, R49, R50) works
much the same way as the lower half; that is, R49 and D7 are
effectively out of the circuit, which means that R50 limits the
current flowing to about 1 milliamp.
The Read Enable Signal, in addition to being connected to the
transistor E22, is also connected to the PAL at E25 (pin 7).
When the read enable signal is asserted, the phase lock loop
circuit is decoding the data, which it knows is all logic Is, in
the preamble. When it sees a missing transition in a data cell (a
0), it clocks out that first zero onto the serial bus, through the
quad driver at E5 (26LS31).
The read clock is also output from
this quad driver at the same time. E5 is connected to the
differential signal cable that connects to the 7201 chip on the
controller.
This zero acts almost like a start bit, in that it informs the
7201 to begin its eRe checking and to start its serial UART.
Followed by the zero is the data, the eRe, and the postamble from
the phase lock loop circuit.
2.7.13

Pump Up and Pump Down Signal Generation (Sheet 4)

The PAL at E25 (4-D4), in conjunction with the PAL at E29 (4-D7),
generates the Pump Up and Pump Down signals. The PAL at E29 is
being used as a phase detector.

2-18

The PAL at E25 has the 140 ns (approximately) read pulse on its
input pin 9.
It uses the read pulse, with the VCO clock on its
pin 1, to form the load pulse LOAD PLS H.
The load pulse lasts
exactly one VCO clock period in duration. The result is one load
pulse per read data pulse through the PAL at E25.
This synchronized (in effect)
version of the read pulse is
connected to the PAL at E29 (pin 6).
E29 provides a counting
function (CNTO - CNT4) such that each data cell has 16 VCO clocks
and each clock cell has 14 VCO clocks.
So the data cell has a
maximum of eight clocks for pump down and eight clocks for pump
up.
If the read data is exactly on time, the load pulse to E29 is at
the exact center of the data cell, and no correction needs to be
performed. But if the load pulse is early (due, for example, to
peak shift), then the VCO clock has to go faster to catch up to
the pulse in relation to the data cell.
In this case, the PAL
asserts the signal Pump Up L. Pump up increases the frequency of
the vco clock. When the center of the cell occurs, the Pump Up
signal is withdrawn and the PAL at E29 continues counting.
If the load pulse is late, the counter at E28 gets loaded with the
2's complement of the number of VCO periods for which it was late;
then pump down is asserted until the carry signal is asserted.
2.7.14

Data Detection

When a load pulse occurs in any part of a data cell, it is
considered a logical one and is clocked out from the PAL at E25 as
a one. Any missing load pulse within a data cell is considered a
zero.
2.7.15

Drive Commands and Status

Serial Drive status is sent back to the controller by the
microprocessor, via the 26LS31 quad driver at E5
(4-02).
Drive
status is sent to the 7201 MPSC chip on the controller over the
serial bus.
Commands are received by the 8751 microprocessor via the 26LS32
quad receiver at E13 (1-08).
Commands are sent over the serial
bus from the 7201 MPSC chip on the controller.
Status information is sent back to the controller from the
microprocessor's TxD pin.
It is usually sent in response to a
commmand from the controller which is accepted on pin 10 of the
microprocessor.
The 8751 in this case is set up similar to a
full-duplex uart.

2-19

2.8

TAPE HUB (Refer to Figures 2-4 and Appendix A-2)

When the cartridge release handle is lifted, the supply motor's
hub is withdrawn (see Figure A-2
in Appendix A).
The part of the
hub containing the teeth mates with the hub in the tape cartridge
to align the height of 'the tape in the drive.
This vertical
alignment is needed for two reasons:

2.9

The tape must be at the correct height for the leader in
the cartridge to couple with the leader in the drive.

The height of the tape must be the same on both the
supply reel
(tape cartridge) and the take-up reel,
because tight tolerances are needed for the read/write
heads to correctly access the tracks on the tape.
LINK ARMS

The link arms to the left and right of the hub align the cartridge
horizontally in the drive. Horizontal alignment is neeeded to
make sure that the cartridge cannot shift forward or backward.
The handle mechanism controls both the tape hub and link arms.
2.10

TAPE CARTRIDGE INSERTION

As the cartridge is inserted the door on the cartridge opens,
exposes the leader mechanism, and then swings out of the way.
Two plastic arms are used as guides to mate the supply leader with
the take-up leader.
When the cartridge is completely inserted, the interposer is
released, locking the cartridge into the drive. The front reel
lock inside the cartridge is now also released.
The rear reel
lock is held until the handle is lowered.
As the handle lowers,
the tape hub moves to mate with the cartridge and provide vertical
tension.
At the same time, the link arms move into place to
provide horizontal stability to the cartridge.
2.11

TAPE LOAD TO BEGINNING OF TAPE (BOT)

The next operation is to instruct the tape drive to load the tape
to the BOT hole.
To do this, press and lock the Load/Unload
switch on the front right side of the drive. (See also the TK50
Tape Drive Subsystem User Guide EK-OTK50-UG.)
Pushing in the
switch informs the drive to move the tape from the Load Point
(where the leaders couple) to the BOT marker.
The 8155 senses
both the Load/Unload switch closing and· when the tape reaches BOT.
When the 8155 senses BOT it informs the controller, through the
8751, that the drive is on-line and ready for use.

2-20

2.12

TAPE MOTION

The tachometer senses tape motion. The tachometer consists of a
capstan and a finely etched disk.
The rear portion of the
tachometer has an LED and phototransistor that senses the holes in
the etched disk.
The capstan and the disk spin as the tape moves
across the capstan.
In this way, the tachometer can sense the
speed of the tape.
The 8751 controls all tape speed and tensioning.
The TK50 does
not use any driven capstans or air bearings.
The tachometer
provides all feedback regarding tape speed to the 8751.
Tach
pulses are connected to the 8155 via one of its I/O Ports.
The tachometer (tach) has a sensor on a phototransistor to tell
the microprocessor that the tach is working correctly.
The
feedback loop from the tach is tested as part of the power-up
diagnostics.
The tape moves forward to BOT at about 6 inches per second under
about 3 ounces of tension.
When the tape reaches BOT, the 8155
informs the 8751, which then informs the controller that it is
ready for use.
The controller responds by telling the drive to
complete the initialization.
2.13

READ/WRITE HEAD

The read/write head consists of four cores: a read core and write
core for the forward direction and a read and write core for the
reverse direction. The write cores are 18 mils wide and the read
cores are 8 mils wide.
The different widths between the track written (18 mils) and the
track read (8 mils) give the read core more leeway to read data.
It allows for easier recovery from soft errors inherent in tape
media, and it also provides the flexibility to move slightly to
either side, to compensate for defects in the tape.
The four cores are physically on one head mechanism.
The head is
driven by a 1 mil per step stepper motor and is held in contact
with the stepper by two springs around the head carriage.
2.14

INITIALIZATION: WRITING AND READING CALTRACKS

The next step is for the head to read or write/read calibration
tracks 1 and 2 (CALTRACKI and CALTRACK2). The controller sends a
command to write and read the CALTRACKS.

2-21

If the cartridge has never been used, the following sequence takes
place.
1.

The drive tries to find and read CALTRACKS 1 and 2.
Finding neither, it decides that this is a new cartridge.

The head seeks to the top of the tape.

Once at the top, the head moves down about 0.2 inches.

The write core writes a
forward direction.

The read core immediately reads CALTRACKI.
This is
called a read-after-write operation. The read core lags
the write core by 0.3 inches, so a slight delay is to be
expected before the CALTRACK is read back.

The head performs the same
direction for CALTRACK 2.

data burst (CALTRACK

operation

in the

1) in the

reverse

If the cartridge has a previously written CALTRACK, the following
sequence takes place.

The linear actuator moves the head to its top position.

Once at the top, the head moves down about 0.2 inches.

The read core reads CALTRACK 1.

The head
direction

performs the same
for

operation in the
CALTRACK

reverse
2.

Writing and reading the CALTRACKS are done at operational speed
(75 in/s) and tension (5 ounces).
After the TK50 reads the first
CALTRACK (used cartridge), it comes to a controlled stop, then
reverses direction, ramps up to speed, and reads CALTRACK 2.
If CALTRACKI is not found but CALTRACK2 is okay, or if CALTRACKI
is okay but CALTRACK2 is not found, there is a defective component
(refer to Chapter 3).
If neither CALTRACKS 1 and 2 are found, the
current cartridge is a new one and the CALTRACKS are written.
Three retries are performed before the CALTRACK error is reported.
NOTE
There is no way to rewrite CALTRACKS
except to bulk erase the cartridge,
which destroys all data on the tape.

2-22

2.15

WRITING DATA (Figures 2-7 and 2-8)

The TK50 writes data in a serpentine fashion over the entire
length of the tape.
It writes data down the entire length of
tape, on one track, until it reaches a logical EOT marker.
(The
physical EOT marker is a hole in the tape. The logical EOT marker
is a preset, microprocessor-calculated location.)
The tape
direction is then reversed and the reverse write and read cores
are used to write data in the reverse direction the entire length
of the tape until it senses logical BOT. Then the direction is
changed to the forward direction, the head is stepped up 19 mils,
and the forward direction cores are again used.
I
LOGICAL
BEGINNING
OFTRACK
(FORWARD)

3FT
914
MM
MIN

2FT
610
MM
MIN

I R
IA

DATA AREA

I C
K
I

3 FT I
914 I
MM
,
I
MIN
I
I

600 FEET
183 METERS
NOMINAL

11FT I

I ~o~ I
, MIN I

, ,
C
A
L
I
B
R
A
T
I

0
N
BOT
HOLE,

G
U
A
R
D
B
A
N
D

I
I
I
I

G
U
A
R
D

E
X
T
E
N
S
B I
A 0
N N
D

I
I
I

16
14
12

B
A
N
D

I 8
I 6

I 4

'EDT I 2
I HOLEI 21

I
I

1
1

,I
I

1
LEADER
END

20
18

I
I

I B
I E
I R

G
U
A
R
D

I G E
I U x
IA T
R E
I D N
S
I B I
A 0
INN
ID

I N

I
I
I

,
1

19
17
15

I 13
, 11
, 9
, 7

I 5
1 3
, 1

11FT I

REFERENCE EDGE

4 FT
1219
MM
MIN

I ~o~ I
I MIN 1

HUB
END

LOGICAL
BEGINNING
OF TRACK
(REVERSE)
SHR-0219-85

Figure 2-7

Physical Tape Configuration

2-23

_d_I,....__R_E_LA_T_I_V_E_T_A_PE_M_O_TI_O_N....,._--._~_ REV (TO CARTRIDGE)

FWD .....

OfjiS

----<U K 2I1FWD- - (DIRECTION OF RECORDING)

'---rI

CHANNEL 1
ALL EVEN TKS
R/W FWD

11 TRACKS

X .019 = .209"
.005

GUARDBAND
--------

- - - - c t TK 0FWD - - -

-ctTK 21 REV -

.000
.500±.005

-- - - -

.214± .002
REF

CHANNEL 2

11 TRACKS

~~ ~~S TKS

048 NO:

---<t.TK1 R E V . - - - - -

~I~-----B-O-TT-O~)\--E-D-G-E-O-F-T-A-PE--------------------~~I

.0'1

.209"

1_
.0000
.0385±.0025
SHA·0220·S 5

Figure 2-8

Recording Direction

2-24

Table 2-2 lists the 26 signals generated by the controller and
accepted over the 26-pin flat ribbon cable by the drive.
Table 2-2

TKSO Signal Definition

Signal

1
2
3
4

GND
WRT DATA HIGH
WRT DATA LOW
GND
DR CMD HIGH
DR CMD LOW
GND
WRT GATE HIGH
WRT GATE LOW
GND
ERASE LOW
ERASE HIGH
GND
DR RD CLK LOW
DR RD CLK HIGH
GND
RD DATA LOW
RD DATA HIGH
GND
DR STATUS HIGH
DR STATUS LOW
GND
DR WRT CLK HIGH
DR WRT CLK LOW
GND
CABLE SENSE

6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

2-25

2.16

DIFFERENTIAL SIGNAL PAIR DESCRIPTION

Eight differential signal pairs, along with the non-differential
signal Cable Sense, are shown in Table 2-3.
The direction of
these signals is with respect to the drive.
Table 2-3

Differential Signal Pairs

Pins

Signal

Direction

Description

2,3
5,6

WRT DATA
DR CMD

In
In

8,9
11,12
14,15
17,18
20,21
23,24
26

WRT GATE
ERASE
DR RD CLK
RD DATA
DR STATUS
DR WRT CLK
CABLE SENSE

In
In
Out
Out
Out
Out
Out

Write data in NRZ format
Serial Drive Command (see
also Table 2-5 )
Write enable gate
Erase enable
Drive read clock
Read data in NRZ format
Serial drive status
Drive write clock
Cable sense. Used by the
controller to determine drive
presence ( 0 = present).

2.17

SIGNAL INTERFACE TIMING

The critical timing for the signals back and forth between the
drive and the controller is shown in Figures 2-9 and 2-10. The
notes in the timing diagrams are coded A through U. Table 2-4
explains the coded portions of the timing diagrams.

2-26

READ AFTER WRITE TIMING

1-"----------(0~------~·1
WR I TE GATE

.-.J~

ERASE

-11

~I-@

:J~~

WRITE ClK

I-----iSJ--

F==I

n~___. Jn

I
I~

t"-@

'------ill--

__________________________~--~----~~

II~___-'II____
~---B---1 r-®
---II
I
II
II'______
---Il

READ DATA

READ ClK

Figure 2-9

Signal Interface Timing (A-P)

READ AFTER WRITE TIMING

~~·~I·----------~®~------------~·I
I

WRITE GATE

----.-..,.JJ---

---JII------'

1-%-1~

ERASE ----?;,'l-1_ _ _~n'___

I I'-- - - - I I I - -

__-..Jn'____. . .Inl..._____In

-l ~

f---0---I

1-0--1
I

~~f-~--T-----T+---T~----~~r_----_r------~/~
WRITE DATA

WRITE ClK

:J)~
READ DATA

__________________________ ____ __
~

0-j ~

:30 I

REA D C lK

I IL--__. . .I 1"'--__. . .1 I

II......_ _~II. . . ._ _~II

L..-_ _- - . . J

@----.j I---®-------I

:JOI
+---IJ--®--.J

11,--_~II

~SL:

·1
I

11-SH R-021 7·85

Figure 2-10

Signal Interface Timing (Q-U)

2-27

Table 2-4

Signal Interface Timing

Code

Activity

Time

Write gate active
Erase i nac t i ve
Erase active
Erase inactive for
last block written
Erase active for last
block written

From beginning to end of write
8960 us + 10 us (overhead)
128 us + 10 us (overhead)
8960 us + 10 us (overhead)

Write data active
Write data inactive
Write data active
for last block
First erase to read
data active
Read data active

8480 us + 10 us (overhead)
608 us + 10 us (overhead)
8480 us + 10 us (overhead)

Read data inactive
Read data active
for last block
First erase to
read eLK acti ve
Read eLK acti ve
Read eLK inactive

608 us + 1.5% (speed var)'
8480 us + 1.5% (speed var)

B
C
D
E

F
G
H

I
J
K
L

M
N

o
p
Q

R
S

Read eLK active for
last block
Read eLK to write
gate for append
Write gate active for
appended write
Read eLK to erase
acti ve
Read eLK to write
data active
Minimum number of
good blocks for veo
lookup

3872 us + 1.5% (speed var)

4000 us + 1.5% (speed var)
8480 us + 1.5% (speed var)

4000 us + 1.5% (speed var)
8480 us + 1.5% (speed var)
416 us + 1.5% (speed var)
8480 us + 1.5% (speed var)
4642 us + 1.5% (speed var)
(Same as A)
4640 us + 1.5% (speed var)
5024 us + 1.5% (speed var)
3

Overhead time (overhead)
in Table 2-4 is due to microprocessor
interrupt handling delays.
Speed variation time (speed var) is
due to tape speed variation.

2-28

2.18

SERIAL CONTROLLER TO DRIVE COMMUNICATIONS

The
controller sends
commands to
the drive
through the
differential signal pair DR CMD.
Status is returned to the
controller via the differential signal pair DR Status.
The
drive's 8751 microprocessor receives and interprets the commands
through its built-in serial port, set up as a full-duplex UART.
The drive receives drive commands via the AM26LS32 differential
receiver (E13) and the microprocessor's RxD (receive data) line.
Drive status is transmitted to the controller, via the AM26LS31
differential driver, from the microprocessor's TxD (transmit data)
line.
The communications (UART)
follows (Figure 2-11).

portion of the

8751 is

programmed as

1 start, 8 data, 2 stop bits.

Frame format

This is the 875l's UART Mode 2, with T88 set high to create the
second stop bit.
Baud rate

187500

Frame time

59 microseconds

IDLE
STATE

11+.-----8
STARTr~~
BIT

-____ ___

---..I

DATA BITS ----~.I

RETURN TO
IDLE STATE
OR
START BIT OF
NEW CHARACTER

i--l- ---:---l- -- i----:---l-~s~i -----,,......,L-I
i -,--_
:
2 STOP BITS

I- - __ IL ___ IL __ -l.
I ___ L
I __ ...JI___ ...JI ___ .L
I __ -.II

II.. __ ...JI

14-

5.33 US +/- 1% PER BIT CELL TIME

! . - - - 5 8 . 6 US +/- 1% PER FRAME OF 11 BITS

•

BAUD RATE = 187.5 KHZ
SH R-0218-85

Figure 2-11

2.19

Frame Format of Data Coming from Controller

BASIC CONTROLLER/DRIVE COMMUNICATIONS PROTOCOL

This section explains the handshaking needed to transfer commands,
data, and status between the drive and the controller.

2-29

2.19.1

Contro11er-to-Drive Command Protocol

The drive always echoes commands back to the controller to insure
the integrity of the transmission.
If data bytes other than the
initial command byte are required by the command in question, they
are also sent by the controller and echoed by the drive.
All commands but one must be echoed by the drive within 500
milliseconds, and all other solicited bytes must be received by
the controller
within one second,
or it assumes
that a
communications error exists.
The only exception is the send
status command, which allows up to 9.75 seconds for the status
message to be received.
2.19.2

Drive-to-Contro11er Status Protocol

Status sent from the drive to the controller always requires the
transmission of an acknowledge message from the controller "(40H),
before the drive proceeds with any further communication.
Two
types of status messages can be transmitted from the drive to the
controller: solicited and unsolicited.
Solicited status messages are those drive transmissions sent in
response to a controller invoked command.
Unsolicited status
messages are those sent to the controller that were not requested.
Drive "change of state" and "drive detected error" result in
unsolicited status messages.
2.19.2.1 Change of Drive State -- A drive change of state results
in the tranmission by the drive of the one-byte drive status
message.
Examples of this change of state message are: up to
speed, rewind complete, and change of load switch state. Change
of
state 'message
transmission causes
an
interruption of
drive/controller communication until the controller acknowledges
the message.
2.19.2.2 Drive Detected Errors -- An error detected by the drive
results in an unsolicited "drive detected error" message to the
controller.
This
message is always preceded by an error
notification (80 hex) to the controller.
After the controller
acknowledges the error notification message, one of the error
codes defined in section 3.2 is transmitted to the controller.
The transmit/acknowledge protocol is used throughout the error
message interchange between the drive and the controller.

2-30

2.20

TK50 COMMANDS

Table 2-5 lists and defines the commands that the controller
provides to the drive via the 26-pin flat ribbon cable. These
serial
commands
are received
and
decoded
by the
8751
microprocessor at El on the drive logic module. The 8751 controls
the remainder of the circuits in the drive logic, to perform the
operations necessary to successfully execute the command.
Table 2-5 TK50 Commands
Command

Code

Definition

RESET
SNDREV
SDSTAT
CLRERR
SDREGO

00
01
03
04

Reset MPU and drive
Send software/hardware revision level
Send Drive Status Byte (DRSTAT)
Clear Drive Error Bytes
Send register contents

SDREGC
SDBKAD
LDBKAD
SNDERR
SDDOCT

05
06
07
08
09

Continue sending register contents
Send tape count
Load tape count
Send the two error bytes
Send dropout data

SKTRKX
STDAGC
LOAD
MEDIA
B5CMD

OA
OB
OC
OD
OE

Step head to track X
Set read gain to standard value
Load tape command (Diagnostic)
Diagnostic test for media dropout
Diagnostic automatic exercise

CALEDG
CALlBR
REWIND
UNLOAD
LOAD

OF
10
11
12
13

Calibrate to tape edge only
Calibrate track position
Rewind to BOT
Software unload tape
Move forward at load speed

MOVFWD
MOVBWD
SEEK
BSPACE
FSPACE

14
15
16
17
18

Move forward (TRKADR)
Move backward (TRKADR)
Seek to block
Backspace for R/W forward
Space forward for R/W backward

DOSTOP
BSTOP
STOP
HEADI
HEAD2

19
lA
IB
lC
ID

Media test, stop on dropout
Space opposite, before stop
Stop tape
Select head 0
Select head 1

2-31

Table 2-5

TK50 Commands (Cont)

Command

Code

Definition

ENWRT
CLRWRT
SMPDRP
ENVCO
ENREAD

IE
IF
20
21
22

Enable write
Clear write and erase mode
Sample dropout data, in "WM"
Software enable VCO
Software enable read (Diagnostic)

DISCRP
SMPCIR
TRK-l
TRK+l
ONESTP

23
24
25
26
27

Disable sampling dropouts
Sample motor current, tape speed
-1 mil offset during present move
+1 mil offset during present move
1 mil step command

TK50 commands can be grouped into four basic types:
Motion, On-the-Fly, and Diagnostic commands.
2.21

Control,

TK50 DRIVE STATES

There are two classes of drive states: Drive Normal Status and
Drive Error Status.
Changes in drive state into either one of
these classes cause an unsolicited status message to be sent to
the controller (see Section 2.19.2
Drive to Controller
Protocol). The controller processes and acts on state change
messages as detailed in this section.
2.21.1

Drive State Status

Drive state changes that do not indicate a drive detected error
result in the drive sending a hexadecimal code to the controller
indicating the current drive state (or state changed to).
The
controller responds to this type of state change transmission with
an acknowledge.
Table 2-6 lists the non-error drive states and
the following subsections explain them.

Table 2-6

Non-Error Drive States

Code

Status

40
50
60
70
NA

Done
Enable write gate
Dropout sensed
Track boundary
Load/run state change (see Paragraph 2.21.1.5)

2-32

2.21.1.1 DONE (40) -- The Done state has mUltiple meanings,
depending on the drive/controller events occuring before the Done
message is transmitted.
This state usually signifies that the
drive has completed a controller-invoked event, such as up to
speed, BOT sensed, or tape motion stopped.
2.21.1.2 ENABLE WRITE GATE (50) -- The enable write gate state is
used during the head calibration sequence.
It requests the
controller to assert the Enable Write Gate signal.
2.21.1.3
DROPOUT SENSED (60)
Dropout Sensed status is
transmitted for every dropout detected by the drive when in the
dropout test diagnostic mode.
2.21.1.4 TRACK BOUNDARY (70) -- The Track Boundary state signals
to the controller that the beginning or end of a logical track was
encountered during normal tape motion.
2.21.1.5 LOAD/RUN STATE CHANGE (Table 2-7) -- Load/Run State
Change is sent to the controller when the drive senses that its
front panel load switch is changed from run to unload.
Drive
initiation of
the unload operation won't
begin until the
controller issues a Stop or Reset command.
Table 2-7 Send Status Byte Bit Assignments
Bits

0
0
0
0
0
0
0
0
1

0
0
0
0
0
0
0
0
0

0
X
X
X
X
X
1
1
0

0
X
X
X
X
1
X

0
X
X
X
1
X
X
X
0

0
X
X
1
X
0
0
0
0

0
X

0
1
X
X
X
1
1
1
0

X
X
X
X
X
0

Request for initialization
Cartridge is present
Head is positioned on Track 0
Unload state
Write Lock state
BOT state
Run state
Rewind in progress
Error state

X = Don't care

2-33

2.21.2

Drive Error Status

When a drive detected error occurs, it causes the drive to send an
unsolicited error message (80H) to the controller. The controller
acknowledges the error indication with a normal acknowledge
message (40H).
When the drive receives and decodes the 40H, it
sends the error code that corresponds to the drive detected error.
Drive error status messages all have bit 7 of their corresponding
hexadecimal code set. All drive error status codes that are less
than 90H are fatal drive errors and cause the termination of
drive/controller communication. All non-fatal drive errors have a
hexadecimal code of 90H or greater, and allow resumption of
drive/controller communication after the controller issues a Clear
Drive Error command.

2-34

CHAPTER 3
DRIVE UNIT REPAIR

3.1

GENERAL

This chapter provides information on diagnosing and repairing the
Drive Unit of the TK50 Tape Drive Subsystem.
The chapter is
divided into two major sections: first, it lists the error codes
that the subsystem microcode generates when an error is detected;
second, it provides instructions on how to remove a failed
subassembly.
This chapter is not intended to be used for field troubleshooting.
Since the drive unit is a Field Replaceable Unit (FRU), the field
engineer will not be troubleshooting it to the subassembly level,
but replacing it as a whole. This chapter is for technicians at
Field Repair Depots.

3.2

ERROR CODES

This section provides error codes, lists probable causes for the
error, and recommends actions to be taken to repair the drive.
Section 3.3
gives instructions for
removing and replacing
subassemblies that failed.
The error codes listed are those
reported to the operating system error log.
3.2.1

Failure to Load to Beginning of Tape (BOT) -- (81H)

Causes:
1.

Supply/takeup leader length is incorrect (if second error
byte = 96H = BaTER).

There is an obstruction in tape path (if second error
byte = 87H = DRAGER).

BOT sensor is marginal.

3-1

Recommended Action:
1.

Replace cartridge and retest.

Check for and fix causes of drag, if possible.

Inspect BOT/EaT sensor and wiring.
sensor if necessary.

3.2.2

Replace BOT/EaT

Failure to Load Tape into Cartridge (82H)

Causes:
1.

Supply/takeup leader length
byte = 096H (BaTER).

is incorrect:

second error

There is an obstruction in tape path: second error byte
87H (DRAGER).

Motor A (supply motor) rotated in wrong direction: second
error byte = 8FH.

Recommended Action:
1.

Replace cartridge, retest.

Check for and fix causes of drag, if possible.

Inspect BOT/EaT sensor and wiring.
necessary.

Replace BOT sensor if

3.2.3
General Motor or Tachometer Failure (83H) -- A hard pull
on Motor B produces less than 5 tach pulses with BOT off.
Causes:
1.

Motor B stalled or is not connected.

Tachometer is bad or not connected (produces no pulses).

Leader is stuck in tape path.

Cartridge jammed.

Recommended Action:
1.

Check all cable connections.

Check for and remove friction in tape path.

Replace Motor B or tachometer.
3-2

3.2.4

Motor A Failure (Supply Motor) -- (84H)

Motor A was pulling against motor B without sensing a reversal of
direction via the motor A Hall switches.
Causes:
1.

Supply motor is bad or not connected.

Recommended Action:
1•

3.2.S

Replace Motor A (supply motor).
Motor B Failure (Take-up Motor) -- (8SH)

Motor B was pulling with excessive current and motor A did not
rotate a minimum of 90 degrees.
Tachometer pulses were present.
Causes:
1.

Motor B
path.

is bad or

there was an obstruction

in the tape

Motor A Hall switches are not functioning or not properly
received.

Recommended Action:
1•

Check for obstruction in tape path and cabling problem.

2•

Check whether both Hall switches at MPU are toggling when
Motor A rotates.

3•

Replace faulty motor (A or B).

3.2.6

Drive Lost Control of Tape or Bad Tachometer -- (86H)

The drive experienced either incorrect spacing of tach pulses
or an insufficient number of pulses were detected.
Causes:
1.

Motor A or Motor B is bad.

Tach problem, high
stalled.

There is no tape in path.

friction on

3-3

the

tape, or

the tape

Recommended Action:
1•

Check for tape presence.

Check for drag in tape path.

Check motors.

4•

If no trouble is found, reset drive and get detail error
report (if any) via initialization procedure.

3.2.7

Excessive Drag in Tape Transport -- (87H)

Currents to the motors exceeded limits in servo mode.
Causes:
1.

There is a jam or interference in tape path.

Tape overran EOT marker, now is at tape end.

One of the motors is bad.

Recommended Action:
1•

Check for obstruction in tape path.

Reset drive and observe any error messages during drive
initialization (repeat several times).

3.2.8

Failure to Stop Tape or Remain Stopped -- (88H)

Excessive tach pulses during deceleration mode.
Causes:
1.

Motors are out of spec.

One of the motors is bad.

Bad tape reel estimate during initialization.

Recommended Action:
1.

Reset drive several times and observe
and after rewind.

Replace faulty motor(s).

3-4

stop at low speed

3.2.9

Cartridge Insert Error -- (89B)

The drive experienced improper timing or occurrences of the
unload/BOT signal or tachometer signal.
Causes:
1.

Leaders are misaligned.

EOT/BOT circuit is bad.

There is high drag in tape path.

Handle switch is bad.
NOTE:
Specific error in second error byte.

Recommended Action:
1.

Check for and remove obstruction in tape path.

2•

Check and repair leader alignment.

3•

Check and/or replace cartridge.

4•

Check and/or replace leader mechanism.

3.2.10

Cartridge Extract Error -- (8AB)

BOT sense was lost or there were insufficient tachometer pulses in
25 seconds.
Causes:
1•

Leaders are misaligned.

BOT/EOT circuit is bad.

3•

Cartridge only partially ejected.

4•

There are
engage.

too many

tach pulses.

Recommended Action:
1.

Check for interference in receiver.

Check eject mechanism and springs.

Replace drive leader if damaged.

3-5

Drive leader

did not

3.2.11

Move Error

(8BH)

The controller tried to move the tape while the drive was
in an error state, or the drive was still in an error state when
the controller issued a tape motion command.
Causes:
1.

Block address overflow or underflow is not received by
the controller.

A new command and error message occurred at the same
time.

Controller is out of sequence.

Operator interfered.

Recommended Action:
1•

3.2.12

Restart.
Deceleration Error -- (8CH)

The servo exceeded the time
per second.

allotted to slow down

to 8.5 inches

Causes:
1.

Motor A is bad, or motors are out of spec.

Recommended Action:
1•

Reset drive and observe detail error messages, if any.

Replace Motor A.

3.2.13

Reel Error -- (8DH)

A second attempt to balance the reels in the unit failed.
Improper balance or distribution of tape between take up and
supply reel.
Causes:
1.

Tape overran logical EOT and is now at tape end.

Tape is too short between EOT hole and end.

Tachometer and/or Motor A Hall switch connection is
intermittent.
3-6

Recommended Action:
1•

Rewind tape 20 turns minimum into cartridge if at tape
end.

Power up.

3•

Replace cartridge.

3.2.14

Check Byte Error -- (8EH)

Causes:
1.

8751 microprocessor is bad.

Recommended Action:
1•

Replace drive board.

Replace microprocessor.

3.2.15

Unload Error -- (8FH)

The unload microdiagnostic test failed.
Causes:
1.

Motor A went in the wrong direction.

The motor is bad.

Recommended Action:
1.
3.2.16

Replace Motor A.
8155 Memory Error -- (90H)

The memory microdiagnostic test failed during initialization.
8155 RAM locations were loaded with an address, then read back
wrong.
Causes:
1.

The 8155 is bad.

The 8751 microprocessor has a bad bus.

Recommended Action:
1.

Inspect drive board for broken leads, etches.

Re-seat socketed 8751 microprocessor, retest.

Replace drive board.
3-7

3.2.17

8155 Timer Error -- (91H)

A timer in the 8155 failed. The 8155 timers were tested against
the 8751's timers and were incorrect or not operational.
Causes:
1.

The 8155 is bad.

The 8751 has a bad I/O bus.

Recommended Action:
1.

Re-seat 8751 microprocessor and retest.

Replace the 8155 or the drive board.

3.2.18

Read Head 1 Error -- (92H)

The read amplitude on head 1 was too low during calibration.
signal during calibration was insufficient.

The

Causes:
1.

Calibration tracks on the tape are bad.

Read head cables are bad or intermittent.

Head is contaminated.

Recommended Action:
1.

Inspect the head and cables. Is there continuity?

Wipe the head with a dry tissue (not on customer site).

Replace the head.

3.2.19

Read Head 2 Error -- (93H)

The read amplitude on head 2 was too low during calibration.
signal during calibration was insufficient.
Causes:
1.

Calibration tracks on the tape are bad.

Read head cables are bad or intermittent.

Head is contaminated.

3-8

The

Recommended Action:
1.

Inspect the head and cables. Is there continuity?

Wipe the head with a dry tissue (not on customer site).

Replace the head.

3.2.20

Cartridge Insert/Extract Error -- (94H)

A runaway condition during the insertion or extraction of the tape
cartridge.
Causes:
1.

Handle microswitch is bad or not connected.

Recommended Action:
1.

Check handle microswitch connector.

Replace handle microswitch connector.

3.2.21

EDT Sensed in Read/Write/Seek State -- (95H)

The drive failed to handle the logical end of tape marker and
reached physical end of tape.
Causes:
1.

Communication between the drive and the controller is
faulty.
The controller lost power while the tape was
moving.

There is a drive/controller communications protocol
problem.

Tachometer is intermittent.

Tape is too short.

There are hole(s) in the tape.

BOT/EDT circuit failed.

Recommended Actions:
1.

Inspect tachometer connections.

Reset.

Restart, retest.
3-9

4.
3.2.22

Replace the drive board.
BOT Sensed in Read/Write/Seek State -- (96B)

The drive failed to handle the logical beginning
and encountered physical beginning of tape.

of tape marker

Causes:
1.

Communication between the drive and the controller is
faulty. The controller lost power while the tape was
moving.

There is a drive/controller communications protocol
problem.

Tachometer is intermittent.

Tape is too short.

There are hole(s) in the tape.

BOT/EaT circuit failed.

Bad reel size estimate during initialization.

Recommended Actions:
1.

Inspect tachometer connections.

Reset.

Restart, retest.

Replace the drive board.

3.2.23

Address Overflow Error -- (97B)

A drive block address overflow
area on the tape.

occurred and exceeded

the usable

Causes:
1.

The controller failed to issue a stop command or lost
power.

Recommended Action:
1.

Clear error and rewind.

Reset, restart.
3-10

3.
3.2.24

Troubleshoot loss of power; replace controller.
Address Underflow Error -- (98B)

A drive block address underflow occurred
area on the tape.

and exceeded the usable

Causes:
1.

The controller lost power while tape was moving backward.

Recommended Action:
1.

Clear error and rewind.

Reset, restart.

Troubleshoot loss of power; replace controller.

3.2.25

Servo Error -- (99H)

Excessive speed variations,
problem in tape reels).

exceeding limits,

wobble

(balance

Causes:
1.

There is a problem with the cartridge, bearing, and
spring load.

There is a problem with the radial/vertical runout of
hubs.

There is a problem with the runout/balance of capstans.

Tach connection is intermittent, extra pulses.

One motor is bad.

Recommended Action:
1.

Inspect for excessive runout.

Inspect tachometer connection.

Reset drive.

3.2.26

Observe detail error messages, if any.

Failure in Tracking -- (9AH)

Reserved for future use.

3-11

3.2.27

Command Error

(9BR)

The command from the controller was not recognized.
Causes:
1.

Interface cabling is faulty.

There is a bad receiver chip on the drive module, or bad
driver chip on the controller module.

Recommended Action:
1.

Reinsert or replace cable.

Replace module(s).

3.2.28

Illegal Command -- (9CR)

The command issued was incompatible with the drive state.
Causes:
1.

There is a communication/protocol error with controller.

Operator forced an unload while the controller started to
read, write, or seek.

Recommended Action:
1.

Restart and observe sequence.

Potential hardware/software problem.

3.2.29

Write Lock Error -- (90R)

The tape was in a
requested.

write-locked state when a

write operation was

Causes:
1.

Cartridge write protect tab was in wrong position.

Write protect switch on the cartridge is faulty or
misaligned.

There is a bad cable connection or broken wire.

There is a bad cartridge (broken plastic pin).

3-12

Recommended Action:
1.

Check the write protect switch on the cartridge.

Check the cable.

Replace the cartridge.

3.2.30

Write Gate Signal Timing Error -- (9EH)

The write gate signal from
tape was stopped.

the controller was

received when the

Causes:
1.

There is a problem with the controller timing/logic.

Drive to controller cable.

Bad receiver chip on the drive board.

Bad driver chip on the controller.

Recommended Action:
1.

Restart, retest.

Replace modu1e(s)

Replace the cable.

3.2.31

controller, then drive.

No Write Gate Error -- (9FH)

Write gate was not asserted after the request during calibration.
Causes:
1.

There is a problem with the controller timing/logic.

There is a problem with the drive/controller cable.

Receiver (drive) or driver (controller) is bad.

Pin connection on microprocessor is bad.

Recommended Action:
1.

Reinsert the cables.

Reinsert the 8751 microprocessor.

3-13

Restart.

Replace module(s).

3.2.32

Error Sensing CALTRACKI -- (AOH)

Causes:
1.

Media has degraded.

There is a problem with head cables, connector.

Head is failing.

4•

Head is contaminated.

Tape is partially erased or overwritten.

Recommended Action:

Replace cartridge.

Inspect head cables and connectors.

Wipe the
site) •

Replace the head.

3.2.33

head with a

clean dry tissue

(not on customer

Error Sensing CALTRACK2 -- (AlB)

Causes:

Media has degraded.

There is a problem with head cables, connector.

Head is failing.

Head is contaminated.

Tape is partially erased or overwritten.

Recommended Action:
1.

Replace cartridge.

Inspect head cables and connectors.

Wipe the
si te ) •

Replace the head.

head with a

clean dry tissue

3-14

(not on customer

3.2.34

CALTRACK 1 Error -

(A2H)

Edge detection of CALTRACKI was out of specification.
Causes:
1.

Media has degraded.

2•

There is a problem with head cables, connector.

Head is failing.

4•

Head is contaminated.

Tape is partially erased or overwritten.

Recommended Action:
1•

Replace cartridge.

2•

Inspect head cables and connectors.

Wipe the
si te ) •

4•

Replace the head.

3.2.35

head with a

clean dry tissue

(not on customer

CALTRACK2 Error -- (A3H)

Edge detection of CALTRACK2 was out of specification.
Causes:
1.

Media has degraded.

2•

There is a problem with head cables, connector.

3•

Head is failing.

Head is contaminated.

5•

Tape is partially erased or overwritten.

Recommended Action:

Replace cartridge.

Inspect head cables and connectors.

Wipe the
si te ) •

Replace the head.

head with a

clean dry tissue

'3-15

(not on customer

3.2.36

CALTRACK2 Offset Error -- (A4H)

The offset of CALTRACK2 from CALTRACKI is too' great.
The distance
and number of steps needed to move from CALTRACKI to CALTRACK2 is
too great.
Causes:

Tape is partially erased.

The read/write head is bad.

Stepper motor is bad.

Recommended Action:
1•

Replace cartridge.

Wipe head with clean dry tissue (not on customer site).

Inspect head cables and connectors.

Replace the head.

Replace the stepper motor.

3.2.37

Tape Edge Error -- (ASH)

A search for the top edge of the tape failed.
Causes:
1.

Stepper motor is bad.

Top head is not writing or reading.

There is excessive feed through.

Drive board is bad.

Head is contaminated.

Recommended Action:
1.

Inspect cables and shield.

Wipe the
si te ) •

Replace the read/write head.

Replace the drive board.

head with a clean, dry

3-16

tissue (not on customer

3.2.38

Top Tape Edge Tolerance Error -- (A6H)

Causes:

Stepper motor is bad.

There is a problem with the cabling to stepper motor.

Recommended Action:
1.

Check the mounting of the stepper motor and the cabling
to it.

Operate the stepper motor in self-test mode if not
cycling.

Replace the stepper motor.

3.2.39 Drive is Overheating -- (A7H)
Causes:
1.

Airflow is blocked.

System fans are inoperative.

Thermal sensor is bad.

Recommended Action:

Remove air flow blockage.

Troubleshoot system fan problem.

3.2.40

BOT Sensor Error -- (A8H)

There is no current in the BOT/EaT sensor/assembly.
Causes:

Cable is unplugged.

BOT/EaT sensor is faulty.

LED driver/sense circuit is bad.

3-17

Recommended Action:
1.

Check cable, replace if necessary.

Replace the BOT/EDT Sensor.

Replace the drive board.

3.2.41

No Hall Switch Signals -- (A9H)

The microprocessor on the drive board does not receive hall switch
signals from motor A.
Causes:
1.

There is a problem with the cable connection between
motor A (supply) and the 8751 microprocessor.

Motor A is bad.

Recommended Action:
1.

Inspect and/or repair cable connections if necessary.

Reseat the 8751 microprocessor in its socket.

Replace the supply reel motor.

3.2.42

No Tachometer Pulses Present -- (AAH)

The tachometer does not produce tachometer pulses while the tape
is moving, as sensed by the motor A hall switches.
Causes:
1.

The cable connection is bad, plugged in incorrectly.

Tachometer is bad.

Comparator in drive board is bad.

Pulley seized on bearings.

Recommended Action:
1.

Inspect the cabling. Check to be sure that plugs are in
the right place.

Reseat the 8751 microprocessor in its socket.

Replace the tachometer.

Replace the drive board.
3-18

3.3

SUBASSEMBLY REMOVE/REPLACE PROCEDURES

The following subsections
provide
subassemblies that fail.
To replace
removal procedure.

instructions for removing
a subassembly, reverse the

The following procedures assume that the drive has already been
removed from
the host system, that
all cables have been
disconnected, and that the cartridge has been removed.
NOTE
While performing the removal procedures,
refer to the annotated exploded view
drawing of the
TKSO Tape Drive in
Appendix A.
Also required
are the
manufacturing
tools,
jigs,
and
procedures used to build a TKSO.
3.3.1

Drive Board Removal

Remove the four 6-32 x 1/2 inch panhead screws on the
bottom of the drive, holding the skid plate on.

Remove two 6-32 x 1/4 inch panhead screws holding the
drive board.

Stand the drive on its front bezel with the
drive board oriented up and down.

Disconnect read/write head connectors J8 and J9.

Disconnect Jl06 (tachometer and EOT/BOT connectors).

Disconnect J6 (handle down switch connector, stepper
motor and head sensor).

Disconnect JlOO (connectors for motors A and B).

Disconnect Jl03 (LED and load switch connector).

Swing the drive board out and pull gently to unseat it
from its snap mounts.

3.3.2
1.

Front Bezel Removal
Trip the interposer.
one direction.

The interposer only moves easily in

3-19

While holding the
handle.

interposer, lift the cartridge release

CAUTION
Do not force the handle up.
Lift the
handle gently while holding the white
interposer in the "tripped- position.
3.

Remove the two 6-32 x 1/4 inch screws that are visible
under the handle after it has been lifted up.

Unsnap the locks and remove the bezel by pulling it
straight out.
CAUTION
Don't pull it out too far until you've
unplugged the connectors.

5.
3.3.3

Unplug connectors Jl03 and J17.
Read/WriteHead Bracket Assembly Removal

Remove the skid plate, then loosen the two screws holding
the drive board.

Disconnect connectors J8 and J9.

Pull the grommets up through the edges of the casting (be
careful of the rear one because the EaT/BOT assembly
wires are underneath it).

Remove the quarter cover.

Remove the leader by retracting the link arm and pulling
out the plastic leader.

6•

Remove the
springs
read/write head.

Slide the head up and off the mount.

3.3.4

from

Tachometer Removal

Pre-conditions for Tachometer Removal
1.

Remove the quarter enclosure.

Remove the read/write head.

3-20

their

connections

the

Tachometer Removal
1.

Disconnect connector JlO. NOTE PLACEMENT OF CONNECTORS.
There are two double connectors with red and green wires.
Place them in the same position when reassembling.

Remove two 6-32 x 5/8
EaT/BOT assembly).

Remove a 6-32 x 3/4 inch panhead screw that holds a small
silver plate in place.

Lift off the tachometer assembly.

3.3.5

inch panhead screws

(holding the

Solenoid/Interposer Removal

Disconnect JI03 (pins 1, 2, and 3).

Disconnect connector JI00 (pins 21 and 22).

Snap out the top white piece of the interposer.

Pull the interposer up and
small springs.

Pull the solenoid up and out.

out.

Be careful to watch for

When replacing the solenoid and interposer, they should snap back
into place without being forced, and should move freely on its
pivot.
3.3.6

Take-up Motor (Motor A) Removal

Preconditions for Take-up Motor Removal
1.

Remove the skid plate covering the drive board.

Remove the drive board.

Remove the quarter enclosure.

Remove the tape leader.

Take-up Motor Removal
1.

Remove the take-up reel by unscrewing the screw at its
top. Take care because there are several parts holding
in the take-up reel, including small spring washers.

Remove the plastic tape constraint. The tape constraint
is snap fitted in place, but can be removed by inserting
a screwdriver under one corner.

3-21

Turn the tape drive metal casting over.

Remove three 6-32 x 5/8 inch panhead screws. Take care
"that the screws don't fall inside the motor due to its
magnet.

3.3.7

Stepper Motor Removal

Preconditions for Stepper Motor Removal
1•

Remove the skid plate covering the drive board.

Remove the d ri ve board.

3•

Remove the quarter enclosure.

4•

Remove the tape take-up leader.

Stepper Motor Removal

The stepper motor can be removed by
5/16 inch panhead screws.

removing two 6-32 x

CAUTION:
The small plate under the stepper motor
is a magnetic shield.
It must be in
place when the stepper is replaced, or
the stepper motor will interfere with
read/write operations, due to its coil
windings.
3.3.8

Heat Sensor Removal

Preconditions for Heat Sensor Removal
1.

Remove the skid plate covering the drive board.

Remove the drive board.

Heat Sensor Removal
1.

Remove the two 6-32 x 1/2 inch
the heat sensor.

3-22

panhead screws to remove

3.3.9

Supply Motor Removal

Preconditions for Supply Motor Removal
1.

Receiver assembly must be removed.

Remove the skid plate covering the drive board.

Remove the drive board.

Supply Motor Removal
1.

Remove the three panhead screws that hold the motor in
place.

Lift the motor out.
CAUTION
See the
manufacturing procedure for
building a TKSO Tape Drive when trying
to re-install the supply motor. There
are some close tolerances that must be
observed and which may require special
shims.

3.3.10

Receiver Assembly Removal

Remove the front bezel (see Section 3.3.2)

Put the handle back down.

Remove springs (how many, what kind).

Remove four screws.

Feed connectors up through the holes.

Make sure that the springs are put back in the correct
places when replacing the receiver assembly.

3-23

CHAPTER 4
TQKSO CONTROLLER THEORY OF OPERATION

4.1

GENERAL

This chapter details
(module M7S46).

the TKSO

Subsystem Q-bus

TMSCP controller

The TK50 M7546 controller is a standard size (8 X 5.5 inch)
dual-height printed circuit board that connects a TK50 Tape Drive
to the Q22 Bus. The main functional element on the controller is
the 80186 microprocessor. The board also contains the following
hardware.
1.
2.
3.
4.
5.
6.

Two 27128 16K ROMs
Two 6264 8K RAMs
One 82Sl05 Field Programmable Logic Sequencer (FPLS)
One 7201 Multi-Protocol Serial Communications Chip
(MPSC)
Q-bus Drivers and Receivers
Tape Drive Interface Drivers and Receivers

4-1

NOTE
The M7546 controller operates on the
Q-bus under the control of the Tape Mass
Storage Control Protocol (TMSCP). It is
not the purpose
of this manual to
document TMSCP operations.
Since all
Q-bus activity with respect to this
controller (during normal operation) is
under TMSCP
control, you will find
several instances of the phrase "the
controller responds as TMSCP requires.Usually, this phrase indicates that for
more information
about exactly what
happens in an operating environment,you
should refer to the TMSCP specification.
In many cases, problems with this board
are
diagnosed
and
fixed
in
an
environment not associated with TMSCP.
Therefore, ONLY hardware operations have
been detailed in this manual.
For
example,
when
the
controller
is
communicating over the Q-bus, this book
explains the DMA sequencing operations
involved, as well as explaining how the
internal circuitry
functions so the
controller can
work on
the Q-bus.
However,
data and
command packets,
response rings, and other specific TMSCP
constraints are not discussed.
There . are six main functional blocks
(Figures 4-1 and A-I).
1.
2.
3.
4.
5.
6.

the M7546

controller

80186 Processor
Memory (ROM and RAM)
Miscellaneous Control and Status Registers
Q22 Bus Interface and Control Circuitry
Drive Interface and Control Circuitry
Diagnostic Hardware

The 80186 microprocessor (with two DMA channels) is connected to
the 7201 MPSC chip. One DMA channel is used for write operations
to the tape, the other for read operations. The 80186 also has
three timer/counters and two external interrupts that control two
on-board Programmable Array Logic (PAL) chips and the 82Sl05 FPLS.
The PALs and the FPLS handle data transfer to and from the Q-bus.
Following is a functional/technical description of
Q/TMSCP controller.
Refer to the Field
Service
(MP-2055-CS) when reading this chapter.

4-2

the M7546
Print Set

Q-BUS

II
I
II I

M7546 Q-BUS CONTROLLER

I"~ERFACE I I
r-----II

Q-BUS
INTERFACE

~~F-;;-

- - --

UART

-1
I

MICROPROCESSOR

RAM

ROM

~ _ _ _ _ ---.J

DRIVE
TRANSCEIVERS

_L-=-_J!

TO
DRIVE
FROM
DRIVE

SH R-0221-85

Figure 4-1

4.2

TQK50 High Level Block Diagram

THE 80186 MICROPROCESSOR

This section details the main engine of the M7546 Q-bus controller
-- the 80186 Microprocessor.
4.2.1

Power-up Reset

When the controller is powered-up, the 80186 is reset through
assertion of the Reset signal, which is connected to pin 24 of the
80186.
The reset line must be asserted for a minimum of four
clock cycles, after the dc power has stabilized, to insure proper
operation.
The signal MTC2 RESET H is asserted when either -BDCOK L or -BINIT
L from the backplane (CPU signals) are a logic level 0 (2-A7).
MTC2 RESET H resets the 74LS74 flip-flop at E5 (5-B3) to generate
MTC5 MICRO RESET Hand -MTC5 MICRO RESET L. MTC5 MICRO RESET L is
the signal that is connected to pin 24 of the 80186 (2-B7).

4-3

MTC5 RESET COUNT L, from the 74LSOO at E6 (5-A4) and MTC5 MICRO
RESET H together let the 74LS16l counter (El)
(5-B4) begin
counting. The counter counts up to 4 (which resets the FPLS that
handles O-bus interfacing) and then up to 8, which sets the D
input of E5 to a logic 1.
On the next count, E5 is set (MTC5
MICRO RESET H is de-asserted), and the counter is disabled.
At this point, both the
executing code.

80186 and the

FPLS are reset

and begin

The same counter reset circuitry is used when the host CPU
executes a "Write IP Register." The reset of the board whenever
the CPU writes to the IP register is part of the U/O Port Protocol
(see the U/O Port Protocol Specifications).
The rest of the circuitry on the board is reset when the 80186
generates a reset from its pin 57. This Reset signal is inverted
and driven to the rest of the board by the 7414 at E36 (2-A6) to
become MTC2 INIT L.
4.2.2

Microprocessor Cycle Time

The processor cycle time is derived from the 12 MHz crystal
oscillator (E37) that is inverted and driven by the 7414 at E36
(2-D6).
MTC2 CLK H connects to pin 59 of the 80186. The 80186
divides this 12 MHz clock by two to generate MTC2 CLK/2 H. This 6
MHz signal is the processor's clock rate and equates to 166 ns per
clock.
A bus cycle is 664 ns in duration (four 80186 clock periods).
Under certain conditions, a bus cycle can take more than four
clock periods.
Refer to the 1983 Intel Microprocessor and
Peripheral Handbook.
4.2.3

Memory Chip Select Lines

The 80186 uses an internal memory select unit, which is programmed
when power is applied.
This memory select unit asserts the
appropriate chip select lines for the memory addresses used by the
controller. These memory select lines access the on-board ROM and
RAM, as well as a 64K byte block of O-bus memory.
The Upper Chip Select (UCS) line (80186 pin 34) accesses the 27128
EPROMs E28 and E29 (3-A6, C6), which are the upper 32K bytes of
address space (F8000-FFFFF).
The 80186 address lines ADO-AD15
access a particular location within the selected 64K byte block.
The Lower Chip Select (LCS) line (80186 pin 33) accesses the 6264
RAMs [E20 and E2l (2-A2, C2)], which are the lower 16K bytes of
address space (OOOOO-03FFF).

4-4

The Middle Chip Select Line 0 (MCSO) signal enables reads and
writes to the Q-bus memory. The controller accesses a 64K byte
block of Q-bus memory. Since the entire MCS block in the 80186
can access 256K bytes of memory, each MCS line is able to access
64K bytes.
MCSO enables access to 64K bytes, beginning on a 64K
byte boundary (40000-4FFFF).
The M7546 controller does not use MCS1-MCS3.
4.2.4

Peripheral Chip Select Lines

In addition to the memory select unit, the 80186 also uses a
peripheral chip select unit.
The 80186 has seven peripheral chip
select lines that it uses to access external peripheral devices
such as the 7201 MPSC chip, serial ports, and various registers.
The peripheral chip select lines are memory mapped on the M7546
for fast interrupt servicing. The memory mapped locations for
these lines follow.

pcso
PCSl
PCS2
PCS3
PCS4
PCS5
PCS6

F800-F87F
F880-F8FF
F900-F97F
F980-F9FF
FAOO-FA7F
FA80-FAFF
FBOO-FB7F

The 80186 first
addresses lines ADO-AD15, then accesses a
particular location or locations, within the 128-byte range of a
PCSX line, to address a particular register.
This addressed
register may be a register consisting of discrete components on
the board, such as the Miscellaneous Control Register, or one of
the programmable registers within a device such as the MPSC.

4-5

The Peripheral Chip Select Lines are assigned as follows:

pcso

Reserved.
Enable 7201 MPSC chip.
Enable Q22 bus register loading.
Enable SA register writes and reads1 terminate
Q-bus transfers.
Enable writes to vector register1
Enable reads from hardware revision level
register1
Reset FPLS interrupts after a Q-bus error.
Enable Miscellaneous
Control Register for
writes1
Enable Miscellaneous Status Register for reads
Enable 7201 MPSC Chip (DMA Acknowledge)

PCS1*
PCS2
PCS3
PCS4

PCS5
PCS6*
4.2.5

Interrupts

The 80186 uses two types of interrupts: internal and external.
Internal interrupts occur when a terminal count is reached during
a DMA transfer, or when a counter/timer maximum count has been
reached.
There are two external interrupts serviced by the 80186. The 7201
MPSC chip can interrupt the 80186 when communicating with the tape
drive.
The FPLS can interrupt the 80186 to alert it of a Q-bus
transfer error (for example, a Q-bus memory parity error).
4.2.5.1 MPSC Interrupts -- The MPSC interrupt line is connected to
pin 44 of the 80186 (INTI). The 80186 acknowledges this interrupt
by asserting INT3 (pin 41).
The 80186 is configured in cascade
mode, so that it gives two interrupt acknowledges (INTAS) to the
MPSC chip. The first INTA from the 80186 acknowledges receipt of
the interrupt and informs the MPSC that the interrupt is being
serviced. The second INTA pulse from the 80186 tells the MPSC to
place its interrupt vector on the internal data bus.
4.2.5.2 FPLS Interrupts -- The FPLS interrupt to the 80186 is not
responded to with an INTA.
Instead, the 80186 responds to this
interrupt by asserting PCS4 (MTC2 ENB VEC REG L). PCS4 performs
two functions:
1.

It resets the memory parity error flip-flop at E2 (5-A7)
to inform the system that a Q-bus error occurred.

It resets FPLS interrupts.

The 80186 also interrupts the host CPU and puts the vector on the
Q-bus. It asserts pin 19 of E19 (6-B5). E19 is connected to the
DC003 on page 5 (E27)(5-A1).
* PCS1 and PCS6 are logically ANDed for an MPSC enable so that
assertion of both lines enables the MPSC.
4-6

4.2.5.3 Non-Maskable Interrupt (NMI)
The 80186 accepts a
non-maskable interrupt on pin 46.
This pin monitors BPOK (BBI on
the backplane). This signal is an early indication that power is
going down, and alerts the 80186 to take the proper steps to
power-down cleanly.
4.2.6

DMA Operations

4.2.6.1 DMA Write -- The 80186 has two DMA channels to which DMA
request lines are connected from the 7201 MPSC chip (E4, 7-CA).
Each time the MPSC chip requests data to write on the tape, the
80186 moves the data from RAM to the MPSC, a byte at a time, until
a terminal count is reached. The terminal count is pre-programmed
into the DMA controller in the peripheral control block of the
80186.
The MPSC asserts the signal MTC7 WR DRQ H through the
74LS74 at E5 (7-C2) and the 74Sll gate at E17.
MTC7 WR DRQ H
connects to the DMA write request pin of the 80186 (pin 18). DMA
HAl clears the flop and the request.
4.2.6.2 DMA Read -- The MPSC chip alerts the 80186 that it has a
byte of data to be read by asserting the MTC7 RD DRQ H signal
through the 74LS74 at E2 (7-D2) and the 74LSll at E17. The DMA
controller in the 80186 transfers the data, a byte at a time, to
RAM until a DMA terminal count is reached.
DMA HAl clears the
flip-flop and the request.
4.3

MEMORY

This section details the memory (RAM and EPROM) that is contained
on the M7546 Q-bus controller.
4.3.1

EPROM

The M7546 controller contains two EPROMs (E28 and E29, 3-C7 and
B7) that make up its 32K bytes of read only memory.
The 80186
accesses this ROM space through two 74LS373 address latches at E52
and E57 (2-C4 and B4).

4-7

The 80186 signal labeled MTC2 ALE H (Address Latch Enable) latches
address lines 0
14, as well as -HIGH BYTE ENB H (Byte High
Enable) into the 74LS373 latches at ES2 and ES7 (2-A4, B4). Byte
High Enable, in conjunction with Address Line 0 (ADRO), enables
either a l6-bit word or an 8-bit byte to be read from the ROMs.
For a byte-wide access, either the high or low byte may be chosen.
See the following chart.
HIGH BYTE ENB L

MTC2 ADO H

Word access
enabled

E28,29

High byte access

E28 enabled

Low byte access

E29 enabled

No access

4.3.2

Data Transceivers

The 80186 reads data from the ROM area through the transceivers at
E33 and E46 (2-A2, C2). It enables the transceivers in the receive
direction by setting the signal -MTC2 DTR H to a logic O.
In this
way, the 80186 can read and execute the microcode resident in the
ROMs, via MTC2 ADO-MTC2 ADlS H.
When the 80186 wants to output data to other devices (for example,
the MPSC chip), it sets -MTC2 DTR H to a logic levell, then
outputs MTC2 ADO H through MTC2 AD15 H.
The data is then
transmitted out the transceivers at E33 and E46.
There is one other condition necessary for the 80186 to transmit
and receive data
through the transceivers: pin 19 of the
transceivers must be a logic level O. The 80186 can enable the
transceivers by setting the signal MTC2 DEN L to a logic level O.
Under normal circumstances, this sets the enable pin of the
transceivers to a logic 0 and enables a data transfer. However,
if a Q-bus memory access or a write or read of the SA register is
in progress, the transceivers cannot be enabled. The 74LSOO gate
at E30 (2-A3) outputs a logic 1 if either of the above conditions
is true.
Therefore, the 74LS32 at E47 is not able to output the
logic 0 necessary to enable the transceivers, even if the 80186
sets MTC2 DEN L to a logic O.
In this way, internal bus
contention problems are avoided.
For a summary of the conditions
necessary for enabling data in either direction through the
transceivers, see the following charts. All enable signals in the
charts are the signals from the 80186, before buffering or gating.

4-8

80186 Read Through Transceivers
-MTC2
MTC2
MTC2
MTC2

DTR H = 0
DEN L = 0
ENB SA REG L = 1
ENB QBUS MEM L = 1
80186 Write Through Transceivers

-MTC2
MTC2
MTC2
MTC2
4.3.3

DTR H = 1
DEN L = 0
ENB SA REG L = 1
ENB QBUS MEM L = 1
RAM

The M7546 controller's RAM area consists of two 6264 RAM chips,
located at E20 and E2l (2-D2, B2). Logically, the RAM area is at
addresses 00000-03FFF.
Write and read operations to and from the on-board RAM use the
same data path through the transceivers as a ROM read, except that
the 80186 asserts its pin 33 (MTC2 ENB RAM L) rather than pin 34
(MTC2 ENB ROM L). Byte high enable and address line 0 determine
high-byte, low byte, or word-wide access from the RAM exactly the
same way as they do for ROM read operations.
The signal MTC2 WR L from the 80186 is used to write to the RAMs.
4.4

CONTROL AND STATUS REGISTERS

This section details two of the I/O Registers used
microprocessor to perform part of its functions.
4.4.1

by the 80186

Miscellaneous Control Register

This register is a
(4-C6).

74LS259 8-bit addressable latch located at E35

The o~tput bits
functions on the
those functions.

associated with this latch perform various
controller. This section lists and describes

The 80186 can set or reset any of the bits in the latch, by
setting a combination of ADR 1 -- ADR 3, accessing an address in
the range of PCS5 (FA80-FAFF), then either asserting (to set) or
negating (to reset) DATO. Table 4-1 lists the addresses of each
bit in the Miscellaneous Control Register, and the subsections
following the Table describe each function.

4-9

Table 4-1

Miscellaneous Control Register Bit Assignments

Address

Latch-Bit Function

MTC2 ADR3 H-MTC2 ADRIH

FABO
FAB2
FAB4
FAB6
FABB
FABA
FABC
FABE

Drive erase
Drive write gate
Enable gap detect
Clear SA initialization
Clear IP initialization
Diagnostic mode
Reset LED 1
Reset LED 2

000
001
010
011
100
101
110
III

4.4.1.1 Drive Erase (High True) -- Drive erase signals the drive
to start an erase operation on the tape. The purpose of the erase
is to put gaps between data blocks on the tape.
Erase works only
if Drive Write Gate is also set, and the tape cartridge is not
write protected.
If the tape cartridge is write protected, the
drive returns an error message to the controller that informs it
of the write protected condition.
The signal MTC4 DRV Erase H, from the 74LS259 latch at E35 (4-D6)
connects to the 26LS31 quad differential transmitter at E25
(7-B2). The quad transmitter drives the signal out the interface
cable to the drive.
4.4.1.2 Drive Write Gate (High True) -- Drive write gate signals
the drive to start writing to the tape. Drive write gate must be
asserted to perform an erase or write operation.
If the tape
cartridge is write protected, and a write operation is tried, the
drive returns an error message to the controller.
As with drive
erase, the signal is driven by the 26LS31 differential transmitter
at E25.
4.4.1.3 Enable Gap Detect (High True) -- Enable gap detect
connects to pins one and two of the 74LS164 shift register at E10
(7-D6).
Each time a drive write clock (DRIVE WR CLK H) occurs,
the shift register shifts another position.
Either one of two
conditions clear the shift register: a reset (MTC2 INIT L): or the
occurrence of a Drive Read Clock.
If neither clear condition occurs, the shift register continues
shifting until it reaches an 8 count.
At the eighth count, it
clocks the gap detect flip-flop at Ell, which causes pin 9 to
toggle. The transition of 1 to 0 or 0 to 1 on pin 6 of the MPSC
(which is connected to the gap detect flip-flop) causes the MPSC
to issue an interrupt to the 80186.
The interrupt signals the
B0186 that a gap on the tape has been detected.

4-10

Note the 74LS157 multiplexer at E12 (7-C6). This MUX lets a
diagnostic signal clock the shift register for diagnostic checking
of the MPSC and Gap Detect circuitry.
See Section 4.7 for a
detailed explanation of on-board diagnostic hardware.
4.4.1.4 Clear SA Initialization (High True) -- The CLR SA INIT
signal clears the flag indicating that the CPU has written to the
SA register. The flag is set in the PAL at E40 (5-B7) -- pin 12.
The 80186 continually monitors this flag in a polling loop. Once
it detects that the flag has been set, it clears the flag by
asserting CLEAR SA INIT (connected to pin 8 of the PAL).
The
80186 then executes the appropriate response to the WRITE SA REG
command from the CPU, according to TMSCP protocol.
The Flag is
set under the following conditions.
1.
2.
3.
4.

MATCH address from DC005 transceiver is asserted.
TS DAL 1 is set.
RSYNC is set.
RDOUT is set.

The combination of the above signals decodes as a WRITE SA REG
from the CPU
according to the Digital standard for Q-bus
interfacing. It sets the SA WR INIT flag at pin 15 of the PAL.
4.4.1.5 Clear
IP Initialization
(High True)
Clear IP
Initialization clears the flag (PAL at E40, pin 14), indicating
that the CPU has read the IP Register.
The 80186 continually
monitors the flag in a polling loop. Once the 80186 detects that
the flag has been set, it executes an appropriate response that
TMSCP requires. The following conditions result in the flag being
set in the PAL.
1.
2.
3.
4.

MATCH address from DC005 transceiver is asserted.
TS DAL 1 is not set.
RSYNC is set.
RDIN is set.

The combination of those signals decodes as a read from the IP
register according to the Digital standard for Q-bus interfacing.
4.4.1.6 Diagnostic Mode (High True) -- This bit, when set, enables
the loopback diagnostic MUX at E12 (7-C6) and disables the 26LS31
drive differential transmitter at E25 (7-B2). With the diagnostic
MUX enabled, diagnostic tests can be run that check out the Gap
Detect circuitry and the MPSC chip. With the transmitter at E25
disabled, no commands or data reach the drive.

4-11

4.4.1.7 Reset LED 1 (High True)· -- On power-up, the 74LS259
addressable latch is reset, which turns on LED 1.
After the
power-up diagnostics have completed, this signal turns off the
LED.
4.4.1.8 Reset LED 2 (High True) -- On power-up, the 74LS259
addressable latch is reset, which turns on LED 2. After the TMSCP
port has gone through its four step initialization process, this
signal turns off the LED.
This indicates that the board is fully
functional.
4.4.2

Unit Number and Status Register

E24, E32, and E4l on page 4 of the schematics make up a 16-bit
buffer that is enabled by the signals RD and ENB MISC REG.
ENB
MISC REG is peripheral chip select line 5 (PCSS) from the 80186.
The Unit Number and Status Register provides a TMSCP unit number
for the controller, as set in the switch pack at E31; as well as
eight status bits that reflect the status of the controller. The
assigned bits in the Unit Number and Status Register are listed in
the following chart, and detailed in the following subsections.
DATAO
DATAl
DATA2
DATA3
DATA4
DATAS
DATA6
DATA7

SA write initialization
IP read initialization
Drive erase
Drive write gate
Q-bus interrupt request
Q-bus interrupt request done
Q-bus memory parity error
Dri ve cable in

DATA8 -- - - - - - -- -- - - -.- - - - - LS B
DATA9
DATAl 0
DATA11
---------TMSCP
DATA12
Unit number
DATA13
DATA14
DATA15------------------MSB
4.4.2.1 SA Write Initialization (High True) -- DATAO -- This bit
is a flag that indicates to the 80186 that the ufQ Port Protocol
has written to the SA Register and that the controller should
respond as TMSCP requires.
4.4.2.2 IP Read Initialization (High True) -- DATAl -- This bit is
a flag that indicates to the 80186 that the UfQ Port has read the
IP Register and that the controller should poll the command rings
in CPU memory as TMSCP requires.
4-12

4.4.2.3 Drive Erase (Low True)
DATA2 -- This bit is for
diagnostic use.
It determines whether the 80186 can set and reset
the Drive Erase signal through the drive erase circuitry.
The
80186 generates this signal through the Miscellaneous Control
register and reads it back through the Unit Number and Status
register.
4.4.2.4 Drive Write Gate (Low True) -- DATA3
The 80186
generates this signal through the Miscellaneous Control register
already explained.
The read back capability through the Unit
Number and Status register is for diagnostic purposes, to check
that the 80186 can set and reset the bit.
4.4.2.5 Q-bus Interrupt
Request (Low True)
DATA4
A
diagnostic loopback signal that lets the 80186 check that it can
set and reset its Q-bus Interrupt Request (Host CPU Interrupt
Request) through the Q22 Bus register.
4.4.2.6 Q-bus Interrupt Request Done (Low True) -- DATA5 -- This
bit indicates to the 80186 that its Q-bus interrupt request has
been serviced and that the host has read the interrupt vector into
the CPU.
4.4.2.7 Q-bus Memory Parity Error (Low True) -- DATA6 -- This flag
indicates to the 80186 that a parity error occurred during a Q-bus
memory transfer, and that the 80186 should transfer the data block
again.
4.4.2.8 Drive Cable In (High True)
DATA 7
This signal
indicates to the 80186 that the cable to the drive is connected.
4.4.2.9 Unit Number (High True) -- DATA8-DATA15
These eight
lines are connected to switch pack E3l. The user can set the
switches to reflect a unit number for each controller board in a
system, per TMSCP.
The 80186 reads the Unit Number and Status
register bits DATA8-DATA15, and returns the information to the
host CPU via TMSCP.
4.4.3

Vector Register (High True)

The Vector register is a l6-bit register that consists of E50 and
E56
(74LS646 bi-directional a-bit registers)
(6-A7, C7).
This
register is a multi-function register, and serves as the Vector
register, the SA register, and the DMA Data register.
This
section details the functions of the Vector register only.

4-13

The 80186 loads the Vector register with the Q-bus Interrupt
Vector. The value of the vector address is loaded by the U/Q Port
Protocol on initialization (TS DALO-TSDALlS). When the controller
interrupts the host CPU, the host enables the interrupt vector
onto the Q-bus at the appropriate time, as required by the U/Q
Port Protocol.
The register is loaded and enabled through the PAL at E4S (6-DS)
of the schematics. The PAL decodes the signals WR and ENB SA REG
to generate the signal CLK A, which loads the register with the
vector. To enable the vector onto the Q-bus, the signal Vector is
decoded, which generates the signal ENA from the PAL.
This
signal is connected to the Vector register, and is the Enable
signal that lets the vector be placed on the Q-bus.
4.4.4

Hardware Revision Register (High True)

This register, which is a buffer for the 80186 bus, lets the 80186
read switch pack E38 (4-C7).
The switch pack is set at the
factory and
reflects the
hardware revision level
of the
controller, as required by TMSCP.
The Hardware Revision Level
register consists of two 74LS240 drivers at E32 and E41.
The
following chart shows the relationship of the switch pack to the
80186 data bus.
DATAO
DATAl
DATA2
DATA3
DATA4
DATAS
DATA6
DATA7
4.4.S'

SWl
SW2
SW3
SW4
SWS
SW6
SW7
SW8

LSB

MSB

SA Register

The SA register is part of the U/Q Port Protocol, and is used to
initialize the controller and return status to the host cPU.
To initialize the controller, the U/Q Port Protocol uses the SA
register to send the vector address, command and response ring
address, and to inform the controller how long the rings are.
The SA register consists of the two 8-bit multifunction chips at
ESO and E56 (6-C7, B7).
These two registers also make up the
Vector register discussed in Section 4.4.3, and the DMA Data
Register (Section 4.5.5.2)

4-14

The PAL at E45 controls SA register loading and enabling, as it
does the vector register.
The SA register IS a bi-directional,
latched register. It consists of two sets of registers: one loaded
and enabled in one direction, and one loaded and enabled in the
other direction. This configuration allows the 80186 to write to
one register, which the Q-bus can read; and lets the Q-bus write
to the other register, which the 80186 can read.
The 80186 writes to the SA register by generating the signals ENB
SA REG and WR, which the PAL at E45 decodes to generate CLK A.
CLK A enables the 80186 to write data to the SA register. The
80186 reads the SA register by generating the signals ENB SA REG
and RD, which the PAL decodes to generate ENA and DIR. ENA and
DIR enable the contents of the SA register onto the 80186's data
bus.
The following sequence
controller's SA register.

occurs

when

the

CPU

writes

the

PAL at E40 (sheet 5) decodes MATCH, TS
RDOUT to generate WR SA REG.

DAL, RSYNC, and

PAL at E45 decodes WR SA REG to generate CLK B.

CLK B enables the host CPU to write to the SA register.

The combination of MATCH, TS DAL, RSYNC, and RDOUT generates WR SA
REG through the PAL at E40
(5-B7). The 80186 monitors the signal
SA WR INIT continually in a polling loop. When the 80186 finds
this flag set, it responds as required by TMSCP.
The following
register.

occurs

when the

CPU

reads

the controller's

The PAL at E40 (5-87) decodes MATCH, TS DAL 1, RSYNC, and
RDIN to generate RD SA REG.

The PAL at E45 (6-D5) decodes RD SA
signals ENA and DIR.

ENA and DIR enable the contents of the SA register onto
the Q-bus transceivers at E44, E49 (1-B2, D2), E53, and
E54 (1-B4, D4).
INIT SA RD from the PAL at E45 enables
the data through the transceivers to the host CPU.

REG to generate the

The combination of MATCH, TS DAL 1, RSYNC and RDIN are decoded by
the PAL at E40 to generate RD SA REG.
After power-up or after a WRITE IP REGISTER command, the SA
register always contains zero.
The CPU reads zero from the SA
register until the 80186 has loaded it with the correct value.
This prohibition is accomplished by keeping the INIT SA RD signal
low to disable the DC005 transmitters (E44, E49, E53, and E54)
from transmitting data onto the Q-bus.
4-15

For further information about the
Port Protocol Specification.

4.4.6

SA register, refer

to the U/O

IP Register

Logically, the IP
register is part of the TMSC Protocol.
Physically, however, it is not a register on the M7546 Controller.
The 80186 must only decode whether the host CPU has written to or
read from the IP Register I/O Location, and then respond as TMSCP
requires.
The PAL at E40 on page 5 of the schematics decodes the signals
MATCH, TS OAL de-asserted, and RSYNC to generate the signal IP REG
SEL.
The following sequence
Register.

occurs

when the

host CPU

reads the

The signals ROIN and IP REG SEL generate the flag IP RO
INIT, which the 80186 can read through the Miscellaneous
Control register E4l (4-C6». The 80186 then takes the
appropriate steps as required by the U/O Port Protocol,
after detection of the flag.

The flag stays set until the 80186 clears it through
assertion of the signal CLR IP INIT, generated through
the Miscellaneous Control register E35 (4-06).

The following
register.
1.

sequence

occurs during

CPU

write

to the

The signals IP REG SEL and RDOUT are used to set the
power-up reset circuitry to initialize the controller, as
part of the U/Q Port Protocol.

For further information about the
Port Protocol Specification.
4.4.7

IP register, refer

to the U/Q

Module Starting Addresses/Interrupt Vectors

Any M7546 module you install must be set to the correct starting
address and interrupt vector. The interrupt vector (260) is under
program control and does not need to be set. The starting address
of the first TK50 module installed in a system is fixed at
1774500. Table 4-2 lists the jumper setting for the first M7546
modules.

4-16

Table 4-2 Common Jumper Pack Settings
774500

7760404

7760444

0--0
0--0
o 0
o 0

o
o
o

0
0

0
0
0
0

0
0--0
o 0
o 0
o 0
o 0

0
0
0

0
0 0
0 0
o 0
o 0
0--0

0
0

o
0

0
0

Unit
Number 1

Unit
Number 0

0
0
0
0

Unit
Number 2

The starting address of any additional TQK50 modules installed in
your system is a floating address of 17760nnn and is set using the
jumpers. The floating address of the M7546 module starts at
17760404 and increments by 4; for example 17760404, 17760410,
17760414. Table 4-4 shows the floating CSR address of some common
combinations of devices that require configuration.
Check off all the devices in the system you want to reconfigure
and find the column in Table 4-4 that makes the best match. In
most cases, if you do not install a device listed in the middle of
the column, the addresses of the devices that follow changes.
Observe the following rules.
1.

Check each module installed in the system.

Find the column
modules, where:

that corresponds

to all

the installed

Number = installed
*number = may be ipstalled or not.
NOTE
When an address is preceded by an *, the
address of the following device(s) does
not change.

Assign the floating CSR address according to the numbers
shown in Table 4-4. The numbers are the last three digits
of the address for the module.

4-17

Use Table 4-3 to determine the starting address
may be installed in your system.

of modules that

Table 4-3 Address/Vector Worksheet

Option

Module

Check
Unit
Number

KDJII-BC
MSV11-PL
MSVII-PL
MSV11-PL
MSVI1-PL

M8l90
M8067
M8067
M8067
M8067

1
2
3
4

DEQNA
DPVII
DRVI1-JP
DRVI1-JP
DRVl1-B

M7504
M8020
M8049
M8049
N7950

1
1
I
2
1

DRV11-B
LPVl1
DLVE1
DLVJ1
DLVJ1

M7950
M8027
M8017
M8043
M8043

2
1
1
1
2

V
200
V

DZV11
DHV11
DMV11-CP
DUV11
TQK25

M7957
M3104
M8064
M7951
M7605

1
1
1
1
1

V
V
V
V

TQK50
TQK50
KLESI-QA
RLV12
RQDXl,2

M7546
M7546
M7740
M8061
M8639

1
2
1
1
1

If In
System

Vector CSR Address (N=177)
N72l00
N72102
N72l04
N72l06
120
V

N74440

N64l20
N64140
N724l0

V
124

V
V

224
260

154
160
154

* The

address=O
address=512
address=1024
address=1536

N72420
N77514
N75610
N76500
N76510
F
F
F

N60040
N72520
N74500
N60404
N72150
N74400
N72150

vector for additional TQK50 modules
vector and is set under program control.

4-18

start
start
start
start

becomes a

floating

NOTE
If a module has a floating vector and
CSR address, additional modules of the
same type also have a floating vector
and CSR address.
Substitute the numbers in Table 4-4 for the nnn in address l776nnn
to find the floating CSR address for a second TQK50 module.

Table 4-4 Floating CSR Address Chart
Option
DZQ/V 1
DZQ/V 2
DZQ/V 3
DPV11
DMV11
Second
MSCP
Second
TK50
DHV11
DHV11

Common Configurations
100
*100
*120
*270

*404
440
460

*270

*270
320

*310

100
100
120
*330

334

*354

354

*444
500
520

100
*100

500
520

100
100
*310
340

100
100
120
*330
360

374

414

*504
540

504

If the system you want to configure does not resemble the common
configurations shown in Table 4-4, refer to the following list for
information. See also your system technical manual; Configuration
Chapter.
•

The first DUVl1 CSR address is 17760040.

•

The first DZV11 CSR
present.

•

The first DPV11 CSR address is 17760270
DZV1ls are present.

•

The first DMV11 CSR address is
DZV11s, or DPV11s are present.

•

The first disk MSCP CSR address is always 17772150.

•

The second disk MSCP CSR address is 17760334 if
DUVl1s, DZV11s, DPV11s, or DMV11s are present.

•

The first tape MSCP CSR address is always 17774500.

address is 17760100 is no DUVlls are

4-19

if no DUVl1s or

17760320 if

no DUV11s,

•

The second tape MSCP CSR address is 17760404 if no
DUVlls, DZVlls, DPVlls, or DMVlls are present and no more
than one disk MSCP is present.

•

The first DHVll CSR address is 17760440 if no DUVlls,
DZVlls, DPVlls, or DMVlls are present and no more than
one disk MSCP is present and no more than one tape MSCP
is present.

4.4.8

Unit Number DIP Switch

The unit number DIP switch must be set to correspond to the jumper
setting. The first setting in Tables 4-5 and 4-2 shows the factory
switch setting that matches the jumper setting for a starting
address of 17774500. The remaining settings show the DIP switch
setting for additional modules set for a starting address of
17760nnn (second device) and 17760nnn (third device) respectively.

Table 4-5 Unit Number Switch Pack Settings
Jumper Set
for an
Address of

774500
760nnn
760nnn
760nnn

0
1
0
1

Unit Number
Switch Pack Bits
3 4 5 6 7 8

Unit Number Name

0
0
1
1

0
0
0
0

MUO
MUl
MU2
MU3

0
0
0
0

(first TK50)
(second TK50
( thi rd TK50)
(fourth TK50)

0 = switch open
1 == switch closed
4.4.9

Revision Level Switch Pack

Make sure the revision level DIP switch matches the revision level
of the module that is stamped on the back (see Table 4-6).

4-20

Table 4-6 Revision Level Switch Pack
Revision
Level
Number

2
0
0

3
4
5

1
0
1

= Switch open
= Switch closed

Rev Level 0
1 2 3 4 5 6 7 8 -

4.5

Off
Off
Off
Off
Off
Off
Off
Off

Switches
3
4

1
1

0
0
0
0

0
0

1
1

0
0

0
0
0
0

0
0

0
0
0

0
0

0
0
0
0
0

0
0
0

0
0

Rev Levell

Rev Level 2

1 2 3 4 5 6 7 8 -

On
Off
Off
Off
Off
Off
Off
Off

Off
On
Off
Off
Off
Off
Off
Off

022 Bus Interface Logic

This section explains the fourth major functional block of the
M7546 Controller:
The Q-bus Interface Logic.
Included in this
functional block are:

•
•
•
•
4.5.1

FPLS Control Logic
Q22 Bus Register
DMA Address and Data Registers
Q-bus Interrupt Logic
FPLS Control Logic

The 82S105 Field Programmable Logic Sequencer (FPLS) at E3 (5-C5)
works directly with the 80186 to control all Q-bus address and
data transfer, as well as handling all the timing requirements
that let the controller work on the Q-bus.
A DMA transaction on the Q-bus can be divided into three phases:
1.
2.
3.

Bus mastership acquisition
Data transfer
Bus mastership relinquish phase.
4-21

4.5.1.1 Bus Mastership Acquisition Phase -- To initiate a Q-bus
transfer, the 80186 accesses a Q-bus memory location within the
range accessible by its MCSO line (40000-4FFFF).
The FPLS
recognizes the signal MCSO (ENB QBUS MEM) from the 80186 through
the synchronized latch E9 (74F374, 5-D7). Assertion of MCSO, with
Address Latch Enable (ALE), also enables the DMA address through
the DMA Address Registers at E5l and E55 (6-B2, C2), to the DC005
Q-bus Transceivers at E44, 49, 53, and 54 (sheet 1). See also the
section on the Q22 Bus Register for information on the upper six
bits of Q-bus address (16 -- 21).
The DMA Address is now on the inputs of the Q-bus Transceivers.
When the FPLS detects the ENB QBUS MEM signal through the latch,
it asserts the signal TDMR/TDOUT.
Asserting this signal is the
start of a Q-bus DMA operation.
TDMR/TDOUT becomes the DMA
request signal to the host CPU, BDMR L through the 8881 at E13
(5-Dl).
The controller waits for the host CPU to respond to the request
through assertion of the signal BDGMI L (Bus Grant) on pin AR2.
BDGMI L becomes DMGI through the 8640 Q-bus Receiver at E7 (5-C8).
DMGI lets the controller know that it has control of the bus (has
become bus master) for the duration of its transfer.
The FPLS sees the Bus Grant signal on its pin 4, and asserts
TSACK. TSACK enables the Q-bus drivers at E15 (8641), E13 (8881)
and E23 (8881) (sheet 5 B-1, C-l, D-l), onto the Q-bus, per Q-bus
DMA protocol. The controller waits until BSYNC Land BRPLY L are
negated, then asserts BSACK L (E23) and negates BDMR L. The host
then ends the bus grant sequence.
It negates BDMGO L and waits
for the DMA transfer to be completed. The FPLS handles all bus
handshaking operations once the 80186 has started the process. See
Figure 4-5 for Q-bus DMA timing.

4-22

SECOND
REQUEST

,TTT
I

TDMR - - - - - '

R DMG - - - - - - '

TSACK

R/T SYNC

r-300NS MAX

R/T RPLY

-..J

1:=0 NS MIN
o NS MIN
T DAL
(ALSO BS7
WTBT REF)

ADDR

DATA

f.-100 NS MAX

\
SH R·0222·85

Figure 4-2

Q-bus Timing

4.5.1.2 Data Transfer Phase -- After a delay to enable the Q-bus
transfer address through the DC005 Transceivers, the FPLS asserts
the TSYNC signal, which clocks the address of the transfer through
the transceivers.
This is the address of the DMA slave device
(memory in this case), which was placed on the transceivers by the
80186.
TSYNC asserts the RSYNC signal through the 8641 at E15 (5-Bl).
RSYNC is connected to the PAL at E40 (5-B7).
The PAL generates
the DAL XMIT signal when it decodes RSYNC.
During the address transfer time, the FPLS asserts TDMGO/TWTBT to
signal the DMA slave device that the transfer is either a read or
write. When TWTBT is a logic 1, the operation is a write.
After a delay (see Q-bus transfer timing), the FPLS asserts the
ENB DATA/FPLS INTR signal to enable data onto the Q-bus, or clock
data from the Q-bus (depending on whether the transfer is a read
or write).
In the case of a DMA write, ENB DATA/FPLS INTR tells
the 80186 to gate data from the RAM area, through the transceivers
at E33 and E46 (2-B2, 2-D2), through the DMA Data register at E56
and E50, to the Q-bus transceivers at E44, E49, E53, and E54
(sheet 1).
In the case of a DMA read from the Q-bus, the FPLS tells the 80186
to transfer data from the Q-bus transceivers, through the DMA data
register
(in
the opposite
direction),
through the
data
transceivers at E33 and E46, to RAM.

4-23

During the data transfer, the FPLS decodes Byte High Enable (on
its input pin 23) and ADRO (on its input pin 24), and asserts
TDMGO/TWTBT if the transfer is byte-wide.
TDMGO/TWTBT is not
asserted if the transfer is wordwide.
4.5.1.3 Bus Mastership Relinquish Phase -- The FPLS relinquishes
its mastership of the bus by negating TSACK, which, through the
8881 at E23, negates BSACK L to the Q-bus. The FPLS negates this
signal after completing or aborting the last data transfer cycle.
4.5.2

Error During Q-bus DMA Transfer

During the DMA request/grant sequence (Bus Mastership Acquisition
Phase), the FPLS waits for BRPLY from the slave device.
While
waiting, it de-asserts the ARDY signal, which stalls the 80186
until BRPLY is negated.
If BRPLY does not occur within a
specified time, a timer (TMRl, or DIAG eLK) in the 80186 times
out, informing the FPLS that the response did not occur.
An example of this type of error would be the controller trying to
access non-existent memory.
If the time-out occurs, the FPLS terminates Q-bus transfers by
de-asserting TSACK and interrupting the 80186 to inform it of the
error. The 80186 then determines if the error was a Q-bus parity
error, or if the controller had tried to access non-existent
memory.
If the DMA transfer completes with no errors, the 80186 writes to
the SA register.
The FPLS decodes the SA register write and
de-asserts TSACK to end the DMA operation.
4.5.3

FPLS Interrupt

An FPLS interrupt can occur during a Q-bus acquisition phase.
This can happen when the 7201 MPSC chip interrupts the 80186 for
servlclng.
In this case, the TSACK L signal (80186 pin 47) had
been stalling the 80186 while the controller was waiting for the
bus grant signal (BDGMI).
The FPLS monitors interrupts (pin 2)
during this time, and, if an MPSC interrupt occurs, it withdraws
the DMA request (BDMR) by de-asserting TDMR/TDOUT, then interrupts
the 80186.
The 80186 clears the FPLS interrupt by reading the
hardware revision level register (ENB VEe REG) and services the
MPSC interrupt.

4-24

4.5.4

022 Bus Register

The Q22 bus register consists of the 74LS273 flip-flop at E19 and
the 8881 Q-bus drivers at E13, E18, and E23 (sheet 6). The 80186
uses this register to access up to four megabytes of Q-bus slave
memory for data transfers.
The 80186 configures its data bus (DATAO -- DATA5) for the memory
page it has to access, then performs a write (WR), and at the same
time, asserts its PCS2 line (ENB Q22 REG).
The signal enable
address (ENB ADDR) enables these bits onto the Q-bus through the
Q-bus drivers.
Each time the controller needs to cross a 64K byte boundary, this
register must be updated before the transfer involved in crossing
the boundary.
The Q22 bus register cannot be changed during a
Q-bus transfer, which means that the controller has to do variable
length transfers, making sure that it updates the Q22 bus register
before crossing a 64K byte boundary.
In addition to the six upper address lines already mentioned, the
022 bus register has two more bits under control of the 80186=
BBS7 and QINTR.
BBS7 lets the controller access the I/O Page in Q-bus memory;
QINTR is a Q-bus interrupt request line to the host cpu.
This
signal is normally low, and must be asserted high to initiate a
Q-bus interrupt to the host.
The following is a list of the relationships between
data bus and the Q-bus bits already mentioned.
DATAO
DATAl
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7

BDAL16
BDAL17
BDAL18
BDAL19
BDAL20
BDAL2l
BBS7
OINTR

4-25

the 80186

4.5.5

DMA Address and Data Registers

4.5.5.1 DMA Address Register -- This register consists of two
8-bit latches on page 6 of the schematics (74S374s at E51 and E55
6-B2, 6-D2).
Each time the 80186 accesses a Q-bus memory
location, these registers are loaded with that address (through
the 80186's transceivers at E33 and E46 -- 2-B2, D2).
The FPLS
controls the timing regarding when the address is loaded onto the
Q-bus transceivers, but the PAL at E45 provides the signals that
actually enable the address. The PAL decodes the TSACK, ENBDATA
(de-asserted) and TDIN (de-asserted) signals, from the FPLS, to
generate the ENB ADDR (enable address) signal. The FPLS provides
the correct combination of TSACK, ENB DATA, and TDIN when the
appropriate signals are asserted on its inputs.
4.5.5.2 DMA Data Register -- This register consists of the same
two 74LS646 multifunction registers that make-up the SA and Vector
registers already mentioned.
During a DMA Write to the Q-bus, the 80186 retrieves data from
on-board memory, gates it through its bus transceivers with the
DEN and ENB QBUS MEM signals, and loads it into the DMA Data
register with the CLK A signal.
CLK A is generated by the PAL at
E45 after it has decoded the 80186 signals WR (write) and ENB QBUS
MEM (enable Q-bus Memory).
The contents of the DMA data register
are enabled onto the Q-bus transceivers with ENA and DIR. ENA and
DIR are generated by the PAL at E45 when it decodes TSACK and ENB
DATA (provided by the FPLS at the appropriate time).
The FPLS
provides TSACK and ENB DATA when the appropriate signals have been
asserted on its inputs.
During a DMA Read from the Q-bus, the host CPU loads the DMA Data
Register (through the Q-bus transceivers). The DMA Data register
is actually loaded by the eLK B signal, which is generated by the
PAL at E45 after it decodes TSACK and ENB DATA (from the FPLS).
The FPLS generates TSACK and ENB DATA when the appropriate
combination of signals on its inputs are asserted.
The 80186
reads the data (through its bus transceivers) by asserting RD and
ENB QBUS MEM, which the PAL decodes to generate ENA and DIR
(connected to the DMA Data register).
4.5.6

Q-bus Interrupt Logic

When the controller has to interrupt the host CPU, it asserts the
QINTR signal in the Q22 bus register logic.
QINTR clocks the
request into the De003 Interrupt Control Chip at E27, sheet 5
(pins 17 and 14 are the request and clock, respectively).
The
DC003 then enables BIRQ (pin AL2) onto the backplane of the CPU.
When the De003 detects the signal BIAKI (pin AM2) on the
backplane, and it receives the signal BDIN, it generates Vector.
The Vector signal is decoded by the PAL at E45, which generates
CLK A to clock the vector address through the Vector register to
the Q-bus Transceivers.
4-26

The PAL at E40 also detects the Vector signal, which it decodes to
generate XMIT DAL to the Q-bus transceivers. XMIT DAL enables the
vector address onto the Q-bus for the host CPU to read.
To initiate another interrupt, QINTR is reset, then set again.
The DC003 needs the low to high transition to assert BIRQ.
4.6

TAPE DRIVE INTERFACE

This section describes the fifth main functional block of the
M7546 Controller. The tape drive interface circuitry consists
essentially of the 7201 Multi-Protocol Serial Controller (MPSC)
Chip at E4 on sheet 7, the 26LS31 quad driver at E25, and the
26LS32 quad receiver at E22. Also included in this section is a
connector, into which the tape drive signal interface cable is
plugged.
4.6.1 7201 Multi Protocol Serial Controller (MPSC)
The 7201 MPSC provides the communications interface between the
drive and the 80186. It communicates commands and status to and
from the drive and also handles data transfer between the drive
and the 80186. It accepts parallel data from on-board memory on
its DO -- D7 inputs (pins 19
12), then transmits the data
serially to the drive, via the 26LS31 Quad Driver at E25.
Conversely, it accepts serial data from the drive, via the 26LS32
Quad Receiver at E22, converts it to parallel format, then sends
the data to on-board memory through its DO -- D7 outputs (also
pins 12 -- 19).
Once programmed by on-board microcode, the MPSC works with the DMA
control block in the 80186 to transfer data. The MPSC is
configured so that Channel B is in asynchronous mode for commmand
and status transfers, while channel A is in synchronous mode for
data transfer to and from the tape drive. The timing for read data
transfers is shown in Figure 4-3.

4-27

SYNC MARK OF
THE PREAMBLE

DATA FIELD

__------------~A~------------~
0
£I
£I

READ DATA

I
2

568

ON THE 8th CLOCK AFTER
THE SYNC CLOCK THE
UART WILL INTERRUPT THE
80186 WITH A DMA REQUEST

ONE CLOCK IS REQUIRED
AT THE BEGINNING OF A
BLOCK TO SYNC UP THE
UART ON THE CONTROLLER

SHR-0223-85

Figure 4-3

Read Data Timing

On power-up, the MPSC's internal registers are programmed for the
configuration already mentioned. The registers are altered during
data transfer, to let the MPSC interrupt the 80186.
The MPSC
interrupts the 80186 under the following conditions:
1.
2.
3.

On detection of a read gap.
First character received, to start read DMA transfers.
Transmit Buffer Empty, to append the CRC on a write to
the tape drive.

The MPSC is programmed so that DMA is enabled each time a byte is
requited on a write or read.
The MPSC asserts a DMA request (pin
11 or pin 32, read and write respectively), to one of the DMA
request lines to the 80186, through E2 and E17 (sheet 7) for DMA
reads, and E5 and E17 for DMA writes.
The MPSC interrupts
the 80186 when it receives the first
character, either from the drive or from on-board memory. This is
the beginning of the DMA transfer.
The sequences forDMA read
(data), DMA write (data) follow:
DMA Read
1.

The MPSC generates DRIVE DR CMD from its TxDB pin.

The MPSC receives a clock (DRIVE RD CLK) on RxCA (pin 35).

The MPSC receives serial data from the drive (DRIVE RD DATA)
RxDA (pin 34), through E22.

The MPSC generates a DMA Read Request (RDYA, pin 32) to the
80186 through E2 and E17.

The 80186 responds with DMA HAl through E6 to enable the MPSC.
4-28

The 80186 asserts RD (MPSC pin 22).

The MPSC sends parallel data via DO -- D7 (pins 19 -- 12) to
on-board memory.

The MPSC asserts Read DMA Request for each byte, until the
80186 DMA terminal count is reached.

DMA Write
1.

The MPSC generates a DMA Write Request (from RDYB).

The 80186 responds with
MPSC.

The 80186 provides WR (MPSC pin 21) and data on DO -- D7
(MPSC pins 19 -- 12) from on-board RAM.

The MPSC ouputs
(DRIVE DR CMD).

The Drive provides DRIVE
35 ) •

6•

The
80186
provides
DRIVE
Miscellaneous Control register.

The MPSC
pin 37).

WR DATA from

The MPSC asserts WR DMA REQ for each succeeding byte
until an 80186 DMA terminal count is reached.

4.6.2

DMA HAl through E6 to enable the

serial

characters for

write

command

WR CLK for MPSC input RxCA (pin

provides serial DRIVE

GATE

through

the

TxDA (MPSC

Differential Drivers and Receivers

There is one differential driver that sends data and commands to
the drive and one differential receiver that accepts clocks, data,
and status from the drive.
The 26LS3l differential driver at E25
signals to the drive.
•
•
•
•

Serial Drive
Serial Drive
Serial Drive
Serial Drive

(7-B2) sends the following

Write Gate (DRIVE WR GATE)
Erase (DRIVE ERASE)
Commands (DRIVE DR CMD)
Data (DRIVE WR DATA)

4-29

The 26LS32 differential
following signals.

•
•
•
•

driver at E22

(7-A7, 1-C7)

accepts the

Serial Drive Status (DRIVE DR STATUS)
Serial Drive Read Data (DRIVE RD DATA)
Drive Read Clock (DRIVE RD CLK)
Drive Write Clock (DRIVE WR CLK)
Diagnostic Hardware

4.7

The last major section of logic on the M7546 Controller is the
gates that have been assigned diagnostic functions.
The hardware
detailed in this section has been specifically provided for
diagnostic checking
of the various logic
elements on the
controller.
4.7.1

Diagnostic Indicators

LEDI and LED2, controlled by the 80186 through the Miscellaneous
Control register (Section 4.4.1), signal pass/fail of the on-board
microdiagnostics.
On power-up, both LEOs light.
After the
power-up diagnostics have completed, LEDI goes out.
LED2 goes out
after TMSCP has successfully initialized the controller.
4.7.2

Miscellaneous Register Loopback

Three signal lines in the Miscellaneous Read register are for
direct diagnostic feedback to the 80186. This is so the register
can check that the lines can b~ set and reset.
•

Drive Write Gate
This signal is set in the Miscellaneous Write register by
the 80186, then
checked by the 80186 through the
Miscellaneous Read register.

•

Drive Erase
This signal is also
register and checked
register.

•

QINTR
This signal is set by the
register
and
checked by
Miscellaneous Read register.

set in the Miscellaneous Write
through the Miscellaneous Read

4-30

80186 through the 022
the
80186 through

bus
the

4.7.3

7201

MPSC Diagnostic Loopback

The 7201 MPSC chip can be tested without a tape drive connected to
the controller.
This is accomplished by the 74LS157 quad
two-to-one multiplexer at E12 (7-C6). Commands sent by the MPSC
are looped back through this mutiplexer as drive status, and write
data sent by the MPSC is looped back as read data.
In this
mode,
the 80186 asserts the
signal DIAG in
Miscellaneous Control register (74LS259 Latch at E35, 4-D7).
signal DIAG performs the following functions.

the
The

DIAG connects write data (from the MPSC's pin 37
TxDA) , through the MUX (pin 13), to the MPSC's input pin
34 (RxDA).
The 80186 sends data out through the MPSC,
with DIAG asserted, reads it back through the MPSC, and
compares it to the data originally sent. This checks that
the MPSC can read and write data through Channel A.

DIAG connects drive commands (from the MPSC's pin 8-TxDB) , around through the MUX (pin 10) to the MPSC's
input pin 9 (RxDB) for drive status.
The 80186 sends
data out through the MPSC's channel B, then, with DIAG
asserted, reads it back through the receive section of
MPSC Channel B.
The 80186 compares the data received to
the data sent. This checks that the MPSC can write and
read data through its channel B (commands and status
during normal operation).

When data
read/write and
command/status diagnostic
operations are happening, the 80186 is using DIAG CLK to
clock the data to and from the MPSC. This makes sure
that the MPSC can accept transmit and receive clocks
(Drive Read and Drive Write Clocks, respectively, during
normal operation).
DIAG CLK can also be gated through the MUX to the Gap
Detect Counter at EIO (7-D6).
In this configuration, the
MPSC can be checked to make sure it is capable of
generating an interrupt when a gap on the tape is
detected.
This capability also checks the Gap Detect Counter (ElO)
and the Gap Detect Flip-flop at Ell.
The counter
generates a clock to the gap detect flip-flop on the
eighth occurrence of DIAG CLK. The Gap Detect Flip-flop
generates the GAP DETECT signal (connected to pin 6 of
the MPSC). When the MPSC detects the falling edge of GAP
DETECT, it interrupts the 80186 to inform it of the gap.

4-31

4.7.4

Soft Grounds

For GR and QV testers, the M7546 controller provides resistors to
ground on some gates.
These can be used by testers to disable
these gates for testing.
The following are the locations of soft
grounds.

Page 2 of the schematics. The Output Enable Pins (pin 1)
of the 80186 address latches, by a 68 ohm resistor. The
enable can be pulled high so the testers can inject any
address into the latches.

Page 5. The output enable (pin 1) of the 74F374 latch at
E9.
The testers can pull the enable high to inject any
combination of signals into the FPLS.

Page 7. Connects the enable signal of the MUX at E12 to
ground with a 68 ohm resistor. The testers can pull up
the enable signal so they can inject signals into the
MPSC to test it.

4-32

APPENDIX A
TQKSO DETAILED BLOCK DIAGRAM,
TKSO EXPLODED VIEW

A-I

ClKO

6MHZ ClK OUT

TMOO 1 - - - - UART ClK

12 MHZ
OSC

TMOI

ENB ROM _______

DIAG ClK

ADDR/DAT ~

'~r----------------------------'
1--_
_ DMA HAl

80186

POWER
UP & IP
RESET
CIRCUIT

ADDR/DATA BUS <15:0>

~--------------------~

1--___ ENB 022 REG

lATCHED ADDR BUS<14:0>
ADDR
lATCHES

FPlSINT_

1----_ ENB VEC REG

1----- ENS UART
1 - - - - UART I NT A
UCS 1 - - - _ ENB ROM

TSA CK ______

lCS

ARDY-

DEN_

~-....

DATA
TRANSCEIVERS

ENB RAM

MCSO

,-..

ENBRAM_

1 - - - _ ENB MISC REG
UARTINT_
HOLD ______

DRIVE
INTERFACE
J3

-AlE_

1 - - - _ ENB SA REG
PCS 0 - 6 ~

16Kx 16
ROM

DTR_

ENB OBUS MEM

.....

1.....------.-/

)

8K x 16
RAM

BI-DIRECTIONAl DATA BUS<15:0>

---+- UART INT
r_---~

~~ALL---------------~D~A~T~A~<~7~:0~>----------------------~

022
ADDR
REG

I--- ENB 022 REG

DATA<- 7:0>

REV
SWITCH
PACK

)

-VECTOR
DC003
OINTR

' - - _ _ _oJ

16-BIT

~TE ADDR/DATA

~~~~

'--REG----'~,..-------,II

HOST CPU BUS
(OBUS) INTERFACE"<

16-BIT
SA, VEe,
&DMA
REG
OBUS
RECE I VE R
8640

(-------~
JI
~---~'---.....

......------.....

IIAn-------------v-.......""""!

'"ENB OBUS MEM_

~----~VA,~

____~

'r-- -

Io-----L__-'"

OBUS
FPlS
ENBSAREG_

DIAG_
DIAG_
ClK

)

...

DIAG
lOOP
MUX

UARTINTA~

DIFF
DVR

~
DIFF
RECV

UNIT
SWITCH
PACK

)

ENS MISC REG -----+

UNIT
NUMBER
REG

..
lATCHED ADDR<3:1> ...

......------'

SAWRINIT_

f----- ENB GAP DETECT
DATABITO

II"

OINTTR DONE_

f---- ClR SA INIT

I--- ClR IP INIT

r---- DIAG
f---- RED lED

DRVWRGATE_
OINTR_

MISC
CNTRl
REG

MISC
STATUS
REG

ENBMISCREG_

I-GREEN lED

DRIVE CABLE IN _ _

WR_
RD_

DATA<7:0>

~
DRIVE
UART

MEM PARITY ERROR_

VECTOR-

r------ FPlS INT

DRVERASE_
SA, VEC,
DMA
REG
CNTRl
PAL

SA/IP
CNTRl
PAL

---

,..

IPRDINIT _

EN B SA REG _

8641

OBUS
DRIVERS
8631

<:"r-----------,

DATA<7:0>

ENBUART-

ENBVECREG _
4 - - OINTR

DC005
ADDRI
DATA
REG

HARDWARE
REV
REG

lATCHED
ADDR<2:1>

ENB MISC REG_
'--_ _ _-oJ

---HOLD
-

TSACK

ENBVECREGENB OBUS MEM---+-

f----- ARDY
S H R-O 159-85

Figure A-I TQK50 Detailed Block Diagram

A-3

TAKE-UP~

LEADER

QUARTER
ENCLOSURE

TAKE-UP
REEL

EaT/BOT

ASSE~

RECEIVER
ASSEMBLY

4--1 NTERPOSER)HERE
(NOT SHOWN

~CARTRIDGE
RELEASE
HANDLE

FRONT
/BEZEL

READ/WRITE
SERVO CARD
SHR-0160-85

Figure A- 2 TK50 Exp loded View

A-4

APPENDIX B
TKSO SUBSYSTEM ERROR CODES AND STATUS

This Appendix lists error and
controller to the host system.
Table B-1

Drive Error

Subcode

Code + Sub-code
Dec
Oct
Hex

status codes

sent from

the TKSO

Sub-code Values
E
V

S
T

Drive command timeout.
The controller has timed out
a command exchange with the
dri ve.

113

* *

Controller detected
transmission error.
The controller has detected a
protocol violation during a
command exchange with the
drive.

107

153

Recoverable drive fault
The drive has detected and
reported a recoverable fault
during a transfer operation.

139

213

* *

a-I

Status or Event Sub-Code

Unrecoverable drive fault
The drive has detected and
reported an unrecoverable
fault during a transfer
operation.

Table B-2

Controller Internal Status Byte

Dec

Value
Oct

0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34

0
2
4
6
10
12
14
16
20
22
24
26
30
32
34
36
40
42

Table B-3

Hex

Controller Internal Status

Done
Retry
Hard Error
Tape Mark Read
Logical EOT Detected
End of Media
Drive Error
Communications Exc~ption
End of Data
Failed to Find Append Target
Leaving EOT Trailer Region
ECC Correction on Data
ECC Correction on Tape Mark
BOT Encountered
Data Synchronization Error
EOTdetected
Seek Aborted
Unload

4
6
8

A
C
E
10
12
14
16
18

lA
lC

IE
20
22

Drive Error Code Byte
\

Dec

Value
Oct

Hex

Drive Error Code

1
2
4
6
16
19
34
35
39

1
2
4
6
20
23
42
45
47

1
2
4
6
10
13
22
23
27

Hardware Write Protect
Drive Fault
Communications Exception
Wrong Track
Sync Failure
Communications Error
Positioning Error
Channel B Overrun
Channel A Overrun

B-2

Table B-4

Recoverable Drive Faults

Dec

Value
Oct

Hex

Recoverable Drive Fault Code

144
145
146
147
148
148
149
150
151
152
153
154
155

220
221
222
223
224
225
226
227
230
231
232
233
234

90
91
92
93
94
95
96
97
98
99
9A
9B
9C

8155
8155
Read
Read

156
157
158
159
160
161
162
162

235
236
237
240
241
242
243
244

90
9E
9F
AO
Al
A2
A3
A4

164
165
166
167
168
169

245
246
247
250
251
252

A5
A6
A7
A8
A9
AA

RAM failure in self-test
timer failure
amplitude (HOI) too low in calibrate
amplitude (HD2) too low in calibrate

EOT sensed in R/W/S state
BOT sensed in R/W/S state
Drive block address overflow
Drive block address underflow
Servo error -- excessive speed variations
Failure in tracking
Command error -- command not recognized
Illegal command -- incompatible with drive
state
Write lock error
Write gate at wrong time
No write gate for cal track write
Error sensing cal track 1 -- bad head
Error sensing cal track 2 -- bad head
Detection of edges of cal track lout of spec
Detection of edges of cal track 2 out of spec
Offset of cal track 2 from cal track 1 is too
large
Search of bottom tape edge failed
Bottom tape edge tolerance error
Drive is overheating
No current in LED of BOT sensor (cable?)
Hall switch sense lines Motor A questionable
Tachometer failure

B-3

Table B-5

Unrecoverable Drive Faults

Dec

Value
Oct

129
130
131
132
133
134
135
136
137
138
139
140
141

201
202
203
204
205
206
207
210
211
212
213
214
215

Table B-6

Hex

Unrecoverab~e

81
82
83
84
85
86
87
88

Failure to load to BOT
Failure to unload tape into cartridge
General motor or tach failure
Motor A failure
Motor B failure
Drive lost control of tape or bad tach
Excessive drag in tape transport
Failure to stop tape or remain stopped
Cartridge insert error
Cartridge extract error
CU attempted to move tape with drive in error
Deceleration timeout error
Second attempt to balance reels in init
failed

8A
8B
8e
80

Drive Fault Code

Drive Flags

Bit
Bit Mask
Number Oct
Hex

Drive Flags

0
1
2
4
5
6

Cartridge Present
Head at Track Zero
Tape Unloaded
Hardware Write Protected
Positioned at BOT
Drive in Run State

1
2
4
10
20
40

Note: Bits
to BOT

1
2
4
8
10
20

5 and 6 together indicate that

B-4

the drive is rewinding

Table B-7

Dec
1
2
3

4
5
6

ufQ Port Generic SA Error Codes

Value
Oct

1
2
3

Hex

1
2
3

5
6

7
8
9

7
10

7
8

14
15
16
17
20

C
D
E
F
10

19
20
21

23
24
25

13
14

15
16

11
12
13

14
15
16

Failure Code
Envelope/Packet Read (parity or timeout)
Envelope/Packet Write (parity or timeout)
Controller ROM and RAM parity
Controller RAM parity
Controller ROM parity
Queue Read (parity or timeout)
Queue Write (parity or timeout)
Interrupt Master
Host Access Timeout (higher level protocol
dependent)
Credit Limit Exceeded (reporting this
condition optional)
Bus Master Error
Diagnostic Controller Fatal Error
Instruction Loop Timeout
Invalid Connection Identifier
Interrupt Write Error
MAINTENANCE READ/WRITE Invalid Region
Identifier
MAINTENANCE WRITE Load to non-Ioadab1e
controller
Controller RAM error (non-parity)
INIT Sequence Error
High Level Protocol Incompatibility Error
Purge/poll hardware failure
Mapping register read error (parity or
timeou t)
Attempt to set port data transfer mapping
when option not present

Note: 24 -- 99 are unassigned

B-5

Table B-8

Controller Specific SA Error Codes

Dec

Value
Oct

Hex

Failure Code

600
601
602
603
604
605
606
607
608
609
610
611
612

1130
1131
1132
1133
1134
1135
1136
1137
1140
1141
1142
1143
1144

258
259
25A
25B
25C
25D
25E
25F
260
261
262
263
264

Divide Interrupt Error
Single Interrupt Error
Non-maskab1e Interrupt Error
Breakpoint Interrupt Error
INTO Detected Interrupt Error
Array Bound Interrupt Error
Unused Opcode Interrupt Error
ESC Opcode Interrupt Error

625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
651
652
653
654
655

1161
1162
1163
1164
1165
1166
1167
1170
1171
1172
1173
1174
1175
1176
1177
1200
1201
1213
1214
1215
1216
1217

271
272
273
274
275
276
277
278
279
27A
27B
27C
27D
27E
27F
280
281
28B
28C
28D
28E
28F

ROM Checksum Error
MPU Error
RAM Error (Odd Byte)
RAM Error (Even Byte)
MPU Timer Error
Miscellaneous Register Wrap Error
Gap Detection Circuitry Error
USART Wrap Mode Error
USART Wrap Mode Error (Good CRC)
USART Wrap Mode Error (Bad CRC)
Drive Cable Error
FPLS Buffer Error
Nibble 1
FPLS Buffer Error
Nibble 2
FPLS Buffer Error
Nibble 3
FPLS Buffer Error
Nibble 4
Word Count Error
FPLS Test Error
Reserved -- ECC
Write Sequence Fault
ECC Logic Error Type 1
ECC Logic Error Type 2
ECC data structure consistency failure

Reserved Interrupt Error
INTO Interrupt Error

Note: 613 -- 624, 642 -- 650 and 656 -- 699 are unassigned

B-6

INDEX

Cable type 1-2
Calibration 2-10
Caltrackl error 3-15
Caltrackl 2-21, 2-22
Caltrack2 error 3-15
Caltrack2 offset error 3-16
Caltrack2 2-21, 2-22
Capacity 1-2
Cartridge 2-8, 2-10, 2-20, 2-22
extract error 3-5
insert error 3-5
insert/extract error 3-9
release handle 2-7, 2-20
Change of drive state 2-32
Check byte error 3-7
Circuit schematics 2-10
Clear IP initialization 4-11
Clear SA initialization 4-11
Clock 2-10
Command error 3-12
Common jumper pack settings 4-17
CompacTape 1-2
Connector type 1-2
Constant current source 2-12,
2-18
Control and status registers 4-9
Controller 2-36, 4-3
Controller to drive command
protocol 2-32
Controls and indicators 2-6
Crystal oscillator 2-10

12 volt path 2-12
5 volt path 2-12
Address overflow error 3-10
Address underflow error 3-11
Address/vector worksheet 4-18
B

BOT 2-5, 2-8, 2-20
logical 2-23
sensed in read/write/seek
state 3-10
sensor error 3-17
Basic controller/drive
communications protocol 2-31
Binary ripple counter 2-14
Bit Densityl 1-2
Bus mastership acquisition phase
4-22
Bus mastership relinquish phase
4-24

I-I

DAC reference voltage generation
circuit 2-13
DC low circuit 2-12
DMA
address and data registers
4-26
data register 4-26
operations 4-7
read 4-7, 4-28
wri te 4-7, 4-29
Data
rate 1-2
transceivers 4-8
detection 2-19
transfer phase 4-23
Deceleration error 3-6
Desktop TK50 2-4
Device, mass storage 1-1
Diagnostics 2-5
Diagnostic hardware 4-30
Diagnostic indicators 4-30
Diagnostic mode 4-11
Differential
drivers and receivers 4-31
preamplifier circuit 2-15
receiver 2-10, 2-31
signal pair description 2-28
Done (40H) 2-35
Drive
board 2-5
board description 2-10
board removal 3-19
cable in 4-13
commands and status 2-19
detected error 2-32, 2-36
erase 4-10, 4-13
error status 2-36
is overheating 3-17
logic board 2-10
logic module 2-33
lost control of tape or bad
tachometer 3-3
state status 2-34
to controller interface
specifications 1-2
to controller status protocol
2-32
unit variations 2-1
write gate 4-10, 4-13
Drive/controller communication
2-36
Driver type 1-2
Dropout sensed 2-35

EOT 2-5
logical 2-23
physical 2-23
sensed in read/write/seek
state 3-9
EPROM 4-7
Enable gap detect 4-10
Enable write gate 2-35
Error
codes 3-1
during Q-bus DMA transfer 4-24
sensing caltrackl 3-14
sensing caltrack2 3-14
Excessive drag in tape transport
3-4
F

FPLS control logic 4-21
FPLS interrupt 4-6, 4-24
Failure
in tracking 3-11
to load tape into cartridge
3-2
to load to BOT 3-1
to stop tape or remain stopped
3-4
Fault conditions 2-9
Field maintenance print set 2-10
Field programmable logic
sequencer (FPLS) 4-1
Field service print set 2-1
Filter circuit 2-15
Flat ribbon cable 2-3
Floating CSR address chart 4-19
Floppy diskette drives 2-4
Front bezel removal 3-19
G

Gap 2-16
General motor or tachometer
failure 3-2

I-2

ROM and RAM 4-2
MicroPDP-11 1-1, 2-2
MicroVAX 1-1, 2-2
Microprocessor (80186) cycle
time 4-4
Microprocessor
80186 4-1, 4-2, 4-3, 4-5, 4-6,
4-8
8751 2-5, 2-18, 2-19, 2-21,
2-31, 2-33
Minus reference voltage 2-13
Miscellaneous control register
4-9
Miscellaneous register loopback
4-30
Module starting
addresses/interrupt vectors
4-16
Motor A failure 3-3
Motor B failure 3-3
Move error 3-6
Multi-protocol serial
communications chip 4-1

Handle switch 2-5
Handle 2-9
Hardware revision register 4-14
Heat sensor removal 3-22
I

I/O, RAM chip (8155) 2-5
IP read initialization 4-12
IP register 4-16
Illegal command 3-12
Initialization: writing and
reading caltracks 2-21
Initialization 2-7
Interface cable 1-1
Interface type 1-2
Interrupts 4-6
L

Lights 2-9
Link arms 2-20
Load procedures 2-7
Load/run state change 2-35
Load/unload switch 2-20
Load/unload switch 2-6
Loading 2-9
Low voltage effect 2-13
Lower chip select 4-4

No hall switch signals 3-18
No tachometer pulses present
3-18
No write gate error 3-13
Non-maskable interrupt 4-7
Number of tracks 1-2
p

PAL 2-11
PDP-11/23 plus 2-2
Peripheral chip select lines 4-5
Phase lock loop circuit 2-16,
2-18
Phase lock loop 2-16
Phototransistor 2-21
Physical description 2-4
Power 2-4
conditions 2-10
required 1-2
supply 2-4
Preamble 2-16
Programmable array logic (PAL)
2-10

M7546 4-18
M7546 controller 2-10, 4-5
M7546 Q/TMSCP controller 4-2
MFMformat 2-11
MFM format 2-5
MPSC 4-27
chip 2-19
diagnostic loopback 4-31
interrupts 4-6
MSCP 2-2
Magnetic tape 1-2, 2-6, 2-12
Media type 1-2
Memory 4-7
chip select lines 4-4
error 3-7

1-3

Pump down circuit 2-16
Pump up and pump down signal
generation 2-18
Pump up circuit 2-17

o
O-bus 2-2
drivers 4-1
interrupt logic 4-26
interrupt request done 4-13
interrupt request 4-13
memory parity error 4-13
recei vers 4-1
TMSCP controller 4-1
022 bus register 4-25
022 bus interface logic 4-21
R

RAM 4-9
RAMs 4-1
RD50 1 -1, 2 -4
ROMs 4-1
RX50 1-1, 2-4
Read amplifier circuit 2-15,
2-16
Read
core 2-22
head 1 error 3-8
head 2 error 3-8
head select circuitry 2-14
Read/Wri te
activities 2-10
Gap Spacing 1-2
head 2-6, 2-21
head bracket assembly removal
3-20
Receiver assembly removal 3-23
Receiver type 1-2
Recording method 1-2
Reel error 3-6
Reel motors 2-13
Reset LED 1 4-12
Reset LED 2 4-12
Revision level switch pack 4-20
Rewind 2-9

s
SA register 4-14
SA write initialization 4-12
Seek 2-8
Self-test 2-9
Serial controller to drive
communications 2-31
Servo error 3-11
Shift register 2-11
Signal interface timing 2-28
Soft grounds 4-32
Solenoid 2-7
Solenoid/interposer removal 3-21
Specifications 1-2
Start bit 2-18
States of lights 2-9
Stepper motor 2-6
Stepper motor removal 3-22
Subassembly remove/replace
procedures 3-19
Supply motor removal 3-23
Supply reel 2-6
Switch 2-9
T

Tachometer 2-6, 2-21
Tachometer removal 3-20
Take-up motor (motor A) removal
3-21
Take-up reel 2-6
Tape 2-11
cartridge 1-1, 2-7, 2-20
cartridge, insertion 2-20
conditions 2-10
drive interface 4-27
drive interface drivers and
recei vers 4-1
edge error 3-16
hub 2-6, 2-20
leaders 2-6
load to beginning of tape 2-20
mass storage control protocol
(TMSCP) 4-1
motion 2-21
speed 1-2
transport 2-6

1-4

Timer error (8155) 3-8
TK50 2-1, 2-23
commands 2-33
drive states 2-34
M7S46 controller 4-1
related documentation 1-3
Streaming Tape Drive 1-1
subsystem 4-1
tape drive 2-1, 4-1
Tape Drive Controller 1-1
Tape Drive Subsystem 1-1, 2-1,
2-2, 3-1
tape drive subsystem field
service print set 1-3
tape drive subsystem IPB 1-3
tape drive subsystem user
guide 1-3, 2-20
system integrated 2-3
TK50-AA 2-1
TKSO-AX 2-1
TKSO-D, -R tape drive subsystem
owner's manual 1-3
TK50-D 2-1
TKSO-D 2-4
TKSO-R 2-1
TKSO-R 2-4
TMSCP 4-12
Top tape edge tolerance error
3-17
TQKSO-AA 2-2
TQKSO-AB 2-2
TQKSO-BA 2-2
TQKSO-BB 2-2
TQKSO-CB 2-2
TQK50-PB 2-2
TQK50-RB 2-2
TQK50 1-1,4-17,4-18
Track boundary 2'-35

u
UART 2-31
Unit designations 2-1
Unit number and status register
4-12
Unit number dip switch 4-20
Unit number 4-13
Unload error 3-7
Unload procedures 2-8
Unloading 2-9
Upper chip selec~ 4-4

1-5

veo clock 2-17, 2-19
veo generation 2-17
Vector register 4-13

w
Write
core 2-22
data 2-23
data chain 2-10
driver circuit 2-11
erase 2-11
gate signal timing error 3-13
head 2-11
lock error 3-12

Digital Equipment Corporation. Shrewsbury, MA01545