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ER-BK7B1-TM

2000

362 pages

Original

11MB

Document:	TechMan Feb80
Order Number:	ER-BK7B1-TM
Revision:	0
Pages:	362
Original Filename:	ER-BK7B1-TM_TechMan_Feb80.pdf

OCR Text

ER·BK7Bl·TM

BK7B1 ElF DISK DRIVE
TECHNICAL MANUAL'

This document reprinted with permission of Control
Data Corporation.

digital equipment corporation. maynard, massachusetts

83323810

I';:J c:\ CONTI\OL DATA
\=:i r::::J CORfOR(\TION

CDC® STORAGE MODULE DRIVE
BK7B1-E,F

GENERAL DESCRIPTION
OPERATION
THEORY OF OPERATION
MICROCIRCUITS

HARDWARE REFERENCE MANUAL

REVISION RECORD

REVISION

DESCRIPTION

01
(8-10-79)

preliminary Manual Released

Manual released

(2-22-80)

REVISION LETTERS I, 0,
AND X ARE NOT USED.

Address comments concerning this
manual to:
Control Data Corporation
Technical Publications Dept.
7801 Computer Avenue
Minneapolis, Mn 55435
or use Comment Sheet in the back
of this manual.

83323810 A

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Cover

vii

PRIEFACE

This manual contains information applicable to the BK7BIE and
BK7BIF Storage Module Drives (SMOs). Since this manual covers
all the various configurations available on the SMD~ it is
necessary to understand exactly which configuration you have,
in order to know which procedures in this manual are applicable
to your drive ..
This manual has been prepared for customer engineers and other
technical personnel directly involved with maintaining the SMD.
Reference information is provided in three sections in this
manual:
•

Section 1 - General Description

•

Section 2 - Operation

•

Section 3 - Theory of Operation

Other manuals, also applicable to the SMD's covered in this
manual, are as follows:
Publication No.

Title

83323800

Hardware Maintenance Manual

83323810

Hardware Maintenance Manual

83322440

Normandale Circuits Manual

83323810 A

CONTENTS

Configuration Chart
Abbreviations
1. GENERAL DESCRIPTION

xxi
xxiii

Introduction
Drive Functional Description
General
Interface
Seeking
Reading and Writing
Drive Physical Description
General
Assemblies
Logic and Circuitry
Equipment Configuration
General
Equipment Identification Plate
General
Equipment Identification Number
Series Code
Part Number
Serial Number
FCO Log
Manual to Equipment Correlation

1-1

1-1
1-4

1-4

1-4
1-6
1-6
1-6
1-6
1-6
1-6
1-6
1-6

1-11
1-12
1-12
1-12
1-12

1-13

OPERATION

Introduction
Controls and Indicators
General
Operator Control Panel
Power Supply Control Panel
83323810 A

2-1
2-1
2-1
2-1
2-5

Operating Instructions
General
Disk Pack Storage
Disk Pack Handling (CE and Data Packs)
Disk Pack Inspection and Cleaning
Disk Pack Installation
Disk Pack Removal
Power On Procedure
Power Off Procedure
3.

2-11

THEORY OF OPERATION

Introduction
Power System Functions
General
Power Distribution
Local/Remote Power Sequencing Control
General
Local Control
Remote Control
Power On Sequence
Power Off Sequence
Emergency Retract
Electromechanical Functions
General
Disk Pack Rotation
General
Drive Motor
Spindle
parking Brake
Speed Sensor
Pack On Switch
Pack Access Cover Switch
Pack Access Cover Solenoid

xii

2-5
2-5
2-5
2-6
2-7
2-8
2-9
2-10

:3-1
3-3
3-3

3-4
3-4
3-4
3-6
3-6
3-6

3-14
3-14
3-19
3-19

3-22
3-22
3-22
3-25
3-28
~l-28

3-28
3l-28
3-31

83323810 A

3-31
3-31
3-31
3-34
3-36
3-37
3-37
3-37
3-40
3-40
3-42
3-44
3-44
3-44
3-44
3-52
3-52
3-52
3-58
3-59
3-59
3-61
3-61

Head positioning
General
Actuator and Magnet
Velocity Transducer
Heads Loaded Switch
Heads
General
Head-Arm Assemblies Physical Description
Head Load i ng
Head Unloading
Air Flow System
Interface Functions
General
I/O Cables
I/O Signal processing
Unit Selection
Seek Functions
General
Overall LOOP Description
Servo Disk Information
General
Dibits
Dibit Tracks
Outer and Inner Guard Bands
Servo Zones
Cylinder Concept
position Feedback Generation
General
Track Servo Preamp
Dibit Sensing
Automatic Gain Control (AGC)
Track Servo Signal
Odd/Even Dibits Clock Generation
Cylinder Crossing Detection
End of Travel Detection

3-61
3-63
3-63
3-64
3-64
3-65
3-67
3-67
3-69
3-70
3-72
3-74

83323810 A

xiii

Velocity Feedback Generation
position Signal Amp1ifica~ion
Return to Zero Seek position Control
Unload Heads position Control
Seek End and Error Detection
General
Timeout Error
Maximum Address Fault
End-of-Trave1 Errors
Machine Clock
General
Servo Clock Multiplier
Write Clock Frequency Multiplier
Index Detection
Sector Detection
Head Selection
Read/Write Functions
General
Basic Read/Write principles
General
Writing Data On Disk
Reading Data From Disk
Peak Shift
principles of MFM Recording
Read Circuits
General
Analog Read Data Detection Circuits
Read Analog To Digital Converter
Lock To Data And Address Mark ratection Circuits
Read PLO And Data Separator
Write Circuits
General
NRZ to MFM Converter/Write Compensation Circuits
Write Driver Circuit
Write Current Control
Write Data Protection
xiv

3-75
3-78
3-101
3-103
3-103
3-103
3-107
3-107
3-107
3-108
3-108
3-109
3-111
3-111
3-113
3-116
3-118
3-118
3-118
3-118
3-118
3-121
3-121
3-126
3-127
3-127
3-130
3-131
3-131
3-136
3-142
3-142
3-144
3-147
3-147
3-149

83323810 A

Fault and Error Conditions
General
Errors Indicated by Fault Latch and Register
General
write Fault
More Than One Head Selected
Read and Write
(Read or Write) and Off Cylinder
voltage Fault
Errors Not Indicated By Fault Latch Or Register
General
Low Speed or voltage
No Servo Tracks Fault
Seek Error
4.

3-150
3-150
3-153
3-153
3-153
3-153
3-153
3-154
3-154
3-154
3-154
3-154

MICROCIRCUITS

Introduction
4A.

3-150
3-150

4-1

GENERAL THEORY

Introduction
Transistor-Transistor-Logic (TTL)
Standard TTL Characteristics
Tri-Level Circuits
Open Collector Circuits and Wired Logic
Unused Inputs
Duality of Function
Basic TTL Circuits
Standard Series
Low-Power Series
High-Speed Series
Schottky Clamped Series
Low-Power Schottky Series

4-11

83323810 A

4-3
4-3

4-4
4-4
4-5
4-5
4-5
4-7
4-7
4-10
4-10
4-10

Logic Interface Circuits
TTL Packaging
Emitter-Coupled-Logic (ECL)
Circuit Theory
Loading Characteristics
Unused Inputs
Wired Logic
ECL Packaging
Complementary Metal-Oxide Semiconductor
Advantages/Disadvantages
Advantages
Disadvantages
Operating Voltages
Input Protection Network
Representative CMOS Gates
Transmission Gate
Operating Speed
Unused Inputs
CMOS/TTL Interface
CMOS/ECL Interface
CMOS packaging
Operational Amplifiers
Introduction
Basic Circuit Elements
Input Stage
Second Stage
Basic Circuit Functions
Schmitt Trigger Circuits
4B.

(CMOS)

4-18
4-19
4-21
4-21
4-22
4-22
4-22
4-23
4-23
4-24
4-25
4-26
4-27
4-27
4-29
4-29
4-31
4-31
4-32
4-32
4-32
4-35
4-35
4-35
4-37
4-38

LOGIC SYMBOLOGY

General
Supplemental Notation
Modifiers
Indicators

xvi

4-12
4-12

4-45
4-46
4-46
4-47

83323810 A

Function Names
Direct Seek Position Control
General
Direct Seek Coarse Control
Direct Seek Fine Control
Load Seek position Control
General
Load Seek Coarse Control
Load Seek Fine Control
4C.

4-48
3-78
3-78
3-80

3-88
3-95
3-95
3-98
3-98

DATA SHEETS

Introduction
Data Sheet Interpretation
Data Sheet List

4-1
4-1
4-2

FIGURES

1-1
1-2
1-3
2-1
3-1
3-2
3-3
3-4
3-5
3-6\
3-7
3-8

Drive Functional Blocks
Drive Assemblies
Equipment Identification l)late
Controls and Indicators
Drive Functional Block Diagram
Power Distribution
Local/Remote Power Sequencing Control Circuits
Remote Mode power Sequencing
Power On Circuit
Power On Sequence Flow Chart
Power Off Circui ts
Power Off Sequence Flow Chart

83323810 A

1-5
1-7
1-11
2-2
3-2
3-5
3-7
3-8
3-10
3-12
3-15
3-17

xvii

3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
3-35
3-36
3-37
3-38
3-39

3-40
3-41
3-42
3-43

xviii

Emergency Retract Circuits
Electromechanical Functions Block Diagram
Disk Pack Rotation Functional Block Diagram
Drive Motor Assembly
Spindle Assembly
Parking Brake Assembly
Speed Sensor and Park On Switch Assemblies
Pack Access Cover Switch and Solenoid
Head Positioning Functional Block Diagram
Actuator and Magnet Assembly
Velocity Transducer Assemoly
Heads Loaded Switch Assembly
Heads
Head-Arm Assembly
Head Loading
Air Flow System
I/O Cables
I/O Signal Processing
Unit Selection Flowchart
Servo System Functional Block Diagram
Servo Disk Format
positive and Negative Dibit Pattern
Cylinder Concept
position Feedback Circuits.
Servo preamp Output
Track Servo Amplifier ~ircuit and Signals
Odd/Even Dibit Clock - Logic and Timing
Cylinder Crossing Detection
End of Travel Detection Circuits
Velocity Feedback Circuits
position Signal Amplifier Circuits
Direct Seek Flow Chart
Direct Seek Coarse Position Control Circuits
Direct Seek Coarse Position Control Signals
Fine position Control Circuits

3-20
3-21
3-23
3-24
3-26
3-27
3-29
3-30
3-32
3-33
3-35
3-36
3-38
3-39
3-41
3-43
3-45
3-47
3-55
3-57
3-60
3-62
3-64
3-66
3-68
3-71
3-73
3-75
3-76
3-77
3-79
3-81
3-84
3-87
3-90

83323810 A

3-44
3-45
3-46
3-47
3-48
3-49
3-50
3-51
3-52
3-53
3-54
3-55
3-56
3-57
3-58
3-59
3-60
3-61
3-62
3-63
3-64
3-65
3-66
3-67
3-68
3-69
3-70
3-71
3-72
3-73
3-74
3-75
4-1
4-2
4-3

Fine position Control Timing
On Cylinder Detection Logic
Load Sequence Flow Chart
Load Seek Circuits
Load Seek Timing
Return to Zero Seek Timing
Return to Zero Seek Flow Chart
Seek End and Seek Error Detection Logic
Servo Clock Multiplier
write Clock Multiplier
Index Detection - Logic and Timing
Sector Detection - Logic and Timing
Head Select Circuits
Read/Write Circuits Block Diagram
Writing Data
Reading Data
Write Irregularity-Typical Waveforms and Timing
Peak Shift Timing
MFM Recording - Waveforms and Timing
Read Circuits Block Diagram
Analog Read Data Detection Circuits
Read Analog To Digital Converter Logic and Timing
Lock to Data/Address Mark Detection
Lock to Data/Address Mark Detection Logic
Read PLO and Data Separator Circuits
Data Separator Logic
RD PLO and Data Separator Timing
Write Circuits Block Diagram
Write Compensation/NRZ to MFM Converter Circuits
Write Compensation Timing
Write Driver Circuits and Timing
Fault and Error Detection Logic
Open-Collector Circuits and a Wired AND
Basic T~rL Gates
TTL NAN!) Circuit, Low-Power Series

83323810 A

3-91
3-94
3-96
3-99
3-100
3-102
3-104
3-106
3-110
3-112
3-114
3-115
3-117
3-119
3-120
3-122
3-123
3-125
3-128
3-129
3-132
3-133
3-134
3-135
3-138
3-140
3-141
3-143
3-145
3-146
3-148
3-151
4-6
4-8
4-11

xix

4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20

TTL NAND Circuit, High-Speed Series
TTL NAND Circuit Schottky Series
TTL NAND Circuit, Low-Power Schottky Series
TTL/ECL Interface
Typical TTL packaging
Typical ECL Gate
Typical TCL Packaging
FET Symbol
Typical CMOS Inverter
Diode-Resistor Input Protection
Typical CMOS Gates
Use of Transmission Gates in Flip-Flop Circuit
ECL-To-CMOS Interface
Typical CMOS Packaging
Simplified Op Amp Schematic
Op Amp Circuit Functions
Op Amp Used as Schmitt Trigger

4-12
4-13
4-14
4-15
4-17
4-20
4-23
4-25
4-25
4-27
4-28
4-30
4-32
4-33
4-36
4-39
4-43

TABLES

1-1
1-2
2-1
2-2
3-1
3-2
3-7
3-8

Equipment Specifications
Drive Assemblies
Operator Control Panel Functions
Power Supply Control Panel Functions
Controller To Drive Signal Line Functions
Drive To Controller Signal Line Function
Read Circuit Functions
Write Circuit Functions

1-2
1-9
2-3
2-4
3-49
3-53
3-130
3-144

83323810 A

CONFIGURATION CHART
EQUIPMENT

INPUT VOLTAGES*

TLA NUMBER**

BK7B1E

208 V - 60 Hz

77456058

BK7B1F

220 V - 50 Hz

77456059

*208 V - 60 Hz drives can be rewired for 230 V - 60 Hz.
220 V - SO Hz drives can be rt~wi red for 240 V - SO Hz.
**For factory use only.

83323810 A

xxi

ABBREVIATIONS

ABR

Absolute Reserve

CYL

Cylinder

ABV

Above

DES

Desired

ADDR

Address

D/A

Digital to Analog

ADRS

Address

OC:DR

Decoder

AGC

Automatic Gain
Control

DIFF

Difference

DIR

Direction

Address Mark
Dr.. Y

Delay

AMPL

Amplifier
Amplitude

DRV

AMPTD

Drive

DRVR
BLK

Black

Driver

Below

DSBL

Disable

,BL~r

EeL

Emitter Coupled Logic

ECO

Engineering Change
Order

EMER

Emergency

Enable

EOT

End of Travel

EQUIV

Equivalent

FCO

Field Change Order

FCTN

Function

!IF

Flip Flop

E'IG

Figure

:AE~

Cylinder Address
Register

Channel

CHJ!~

Channel

CN'l~LGL

Centrifugal

(!NTR

Counter

CO~~P

Compensaton

COHFIG

Configuration

CONTD

Continued

CR REF

Cross Reference

83323810 A

xxiii

FLT

Fault

PC PT

Piece Part

FREQ

Frequency

PLO

Phase Lock Oscillator

FTU

Field Test unit

Part Number

FWD

Forward

POS

positive

GEN

Generator

PWR

Power

GND

Ground

RCVRS

Receivers

Head
RD

Read

I/O

Input-Output
ROY

Ready

INTLK

Interlock

REC

Receiver

INTGRTR

Integrator

REF

Reference

Load

REG

MAINT

Maintenance

REV

Reverse

MAX

Maximum

RGTR

Megabyte
TRM

Reserve Timer

MFM

Modified Frequency
Modulation

RTZ

Return to Zero

Mark

S&IOBC

Sector and Index
on B Cable

MULT

Multiple
Series Code

No Connection

SIC

SEC

Second

NEG

Negative

SEL

Select

NOM

Nominal

SEQ

Sequence

NORM

Normal

SER

Servo

NRM

Normal

Sheet

NRZ

Nonreturn to Zero

SOL

Solenoid

xxiv

83323810 A

Ser.vo

Switch

Track

TBS

To Be Supplied

'lILA

Top Level Assembly

'l'P

Test Point

'I'RK

Track

'I'TL

Transistor Transistor
Logic

trNREG

Unregulated

83323810 A

VCO

Voltage Controlled
Oscillator

W+R

Write or Read

W·R

Write and Read

With

WIO

Without

WRT

Write

White

XDUCER

Transducer

XMTR

Transmitter

xxv

GENERAL DESCRIPTION

SECTION 1

GENERAL DESCRIPTION

INTRODUCTION

The Control Data storage Module Drives (SMDls) are high speed,
random access digital data storage devices that connect to a
central processor through a controller. The total data storage
capacity of the units is 300 megabytes.
All the equipment
specifications for each drive are listed in table 1-1.
The remainder of this section provides a general description of
the drive and is divided into the following areas:
•

Drive Functions - Explains the major functional areas of
the drive.

•

Drive Physical Description - Provides description of the
drives physical characteristics.

•

Equipment Configuration - Describes the
configurations and how to ioentify them.

various

drive

DRIVE FUNCTIONAL DESCRIPTION
GENERAL

The major functional areas of the drive are shown on figure 1-1
and descr ibed in the following paragraphs. More detailed descriptions of each Qf the following areas is found in section 3
of this manual (Theory of Opera'tion).
The disk pack is the recording medium for the drive. The disk
pack consists ()f ten, l4-inch disks, center mounted on a hub.
The recording surface of ea9h disk is coated with a layer of
magnetic oxide and related binders and adhesives.
There are nineteen recording surfaces and one servo surface.
The servo surface contains prerecorded information that is used
by the servo circuits to position the heads at the desired area
on the disk pack.

83323810 A

1-1

TABLE 1-1.

EQUIPMENT SPECIFICATIONS

Specification
Size
-,eight
width
Depth
Weight

Value
920 nun (36 in)
914 mm (36 in)
584 mm (23 in)
252 kg (550 1bs)

Temperature
operating

15.5
0c
(59 0
F)
0
0
32.2 C (90 F)
Operating Change/Hr
6.6 0 C (12 0 F) per hr
Transit (packed for shipment) -40.4 0
C
(-40 0
F)
Non-Operating Change/Hr

70 0 C (158 0 F)
.20 0 C (36 0 F) per hr

Relative Humidity
Operating
20t to 80t
Transit (packed for shipment) 5% to 95%

to
to

No Condensation
No Condensation

Altitude
Operating

ft)

to 2000 m

Transi t

ft)

to 4572 m

-305 m (-1000
(6500 ft)
(packed for shipment) -305 m (-1000
(15 000 ft)

Disk ~
Type
Disks/Pack

883-91 (one per drive)
12 (Top and bottom disks are

for protection only.)

Data Surfaces
Servo Surfaces
Usable Tracks/Surface
Tracks/Inch
Track Spacing (center to
center)
Coating

P.!i! Capacity

Bytes/Track
Bytes/Cylinder
ByteS/Spindle
Cylinders/Spindle

19
1
823
384

0.0666 mm (0.0026 in)

Magnetic Oxide
300 MB

20 160
383 040

309 496 320
823

NOTE:
Based on 8 bit bytes
not allowing for tolerance
gaps for sectoring etc.
Table Continued on Next Page

1-2

83323810 A

TABLE 1-1.

EQUIPMENT SPECIFICATIONS (Contd)

Specification
Recording Characteristics
Mode
Density (nominal)
Outer Track
Inner Track
Rate (nominal)
Heads
Read/Write
Servo
Read/Write Width
Seek Characteristics
---rrecfianism
Max Seek Time (411 or 823
Tracks)
Max Track Seek Time
Average Seek Time
Latency
Average
Maximum

Value
Modified Frequency Modulation
(MFM)
4038 bits/in
6038 bits/in
9.67 MHz (1209 600 bytes/sec)
19
1

0.051 mm (0.002 in)
Voice
Loop
55 ms

Coil,

Driven

Servo

6 ms

30 ms
8.33 ms (at 3600 r/min)
17.3 ms (at 3474 r/min)
NOTE:
Latency is time required
to
reach
specific
track location after drive is
on cylinder.

Spindle Speed

3600 r/min

Controllers Per Drive

Refer to Configuration Chart
in front matter of this manual.

Input VoltageE!,

Refer to Configuration Chart
in front matter of this manual.

83323810 A

1-3

The recording surfaces are used for data storage.
Each of
these furfaces has its recording tracks grouped in a 2 inch
band near the outer edge of the disk.
The number of tracks
contained on each recording surface and the spacing between the
tracks is found in table 1-1.
The disk pack is portable and is interchangeable between
dr i ves.
Both the BK6XX and BK7XX use the same type of disk
pack.
POWER SYSTEM

The dr ive has its own self contained power supply which receives its input from the site main power source. The power
supply provides all the voltages necessary for drive operation.
INTERFACE

The drive can communicate only with the controller.
The controller issues all commands to the drive, which decodes the
commands and initiates the proper operation.
In addition to
the commands, the controller sends wr i te data, wr i te clock and
power sequence information to the drive.
The drive sends various status signals, read data, read clock,
and servo clock information to the controller.
These signals
are used by the controller to moni tor and control operations
performed by the drive.
SEEKING

The dr ive must position the heads over the desired data record
before it writes or reads data. This function is called seeking and it is performed by a servo system consisting of control
logic and a head positioning mechanism.
READING AND WRITING

The drive is capable of both writing data on and reading it
from the disk pack.
During a write operation, the drive receives data from the controller, processes it and writes it on
the disk pack. During a rad operation, the drive recovers data
from the disk pack, and transmits it to the controller.

1--4

83323810 A

r---------------------------- -...,
I

COMMANDS

WRT DATA AND CLK!

PWR SEQUENCE

CONTROLLER

DRIVE

~STATUS SIGNALS
SERVO CLK
RD DATA AND CLK

I"
A

SEEKING

1.-_

READING
AND
WRITING

HEADS

I
I

I
I
I

I
I
IL ______________________________ JI

9E86

Figure 1-1.

83323810 A

Drive Functional Blocks

1-5

DRIVE PHYSICAL DESCRIPTION
GENERAL

The following describes the physical characteristics of
drive. The discussion is divided into two major areas (1)
semblies and (2) logic and circuitry.

the
as-

ASSEMBLIES

The major drive assemblies are shown on figure 1-2 and described in table 1-2. A more complete description of the drive assemblies is found in the Parts Data section of the maintenance
manual.
LOGIC AND CIRCUITRY

The drive contains integrated and discrete component circuits
as well as relays, switches and other electromechanical elements.
All of these work together in per forming the var ious
drive functions.
Diagrams showing all circuits and interconnecting wiring are
contained in the maintenance manual. Sections 5 and 6 of this
manual descr ibe character istics of individual discrete and integrated circuits.
EQUIPMENT CONFIGURATION
GENERAL

The equipment configuration is identified by the equipment identification plate and by the FCO log.
It is necessary to identify the equipment configuration to determine if the manuals
being used are applicable to the equipment. The following describes the cabinet identification plate, FCO log and manual to
equipment correlation.
EQUIPMENT IDENTIFICATION PLATE
General

This plate is attached to the frame at the rear of the drive
(refer to figure 1-3)
This plate identifies the drives basic
mechanical and logical configuration at the time it leaves the
factory. The information contained on this plate is defined in
the following.
It

1-6

83323810 A

DECK COVER

PACK ACCESS COVER

PANEL

FRONT DOOR

9W67-1

Figure 1-2.

83323810 A

Drive Assemblies (Sheet 1 of 2)

1-7

ACTUATOR

READ/WRITE CHASSIS

PACK ACCESS
COVER SWITCH
CONTROL
PANEL
PARKING __~~~~~~__~·
BRAKE

DRIVE
MOTOR

PACK
ACCESS
COVER
SOLENOID

SPEED SENSOR

Figure 1-2.

1-8

9W67-2

Drive Assemblies (Sheet 2 of 2)

83323810 A

TABLE 1-2.

DRIVE ASSEMBLIES

Actuator

Contains voice coil and carriage.
This
assembly positions the heads over the disk
pack.

Blower Assembly

Contains a blower motor that
cooling air for the drive.

Deck Cover

Provides an electrical interference shield
for the drive and also reduces noise level
output from drive.

Drive Motor

Provides
rotational motion
spindle and disk pack.

Front Door

Provides access to blower assembly and the
lower front part of cabinet.

Heads

Detect data transitions that are on the
Writes data
pack if drive is reading.
transi tions' on the disk pack if drive is
writing.

Log ic Chassis

Contains logic cards
tion of drive.

Magnet

Provides permanent magnetic field that is
used in conjunction with voice coil to
move carriage and heads.

Operator Control
Panel

Contains switches that allow operator to
control and monitor basic operation of
drive.

Pack Access Cover

Provides access to disk pack and pack area.

Pack Access Cover
Solenoid

Prevents pack access cover from being
opened if the pack is spinning.

Pack Access Cover
Swi tch

Interlock that de-energizes drive motor if
pack access cover is opened while pack is
spinning.
It also prevents motor from
starting unless cover is closed.

that

circulates

that

turns

control opera-

Table Continued on Next Page

83323810 A

1-9

TABLE 1-2.

DRIVE ASSEMBLIES (Contd)

Pack On Switch

Interlock that prevents drive motor
starting when pack is not installed.

Parking Brake

Holds spindle while disk pack is being installed and removed.

Power Supply

Furnishes all necessary voltages for drive
operation.

Read/Write
Chassis

Contains cards that are essential to drive
read/write operations.

Rear Door

Provides access to power supply,
chassis and lower rear of cabinet.

Shroud and
Shroud Cover

Provides protection and ventiliation for
disk pack.

Side Panels

Provide access to either side of drive.

Spindle and
Lockshaft

Provides mounting surface for disk pack.
Lockshaft secures disk pack to spindle.
Drive motor transmits rotational motion to
spindle via drive belt thereby causing
disk pack to rotate.

Top Cover

Covers entire top of drive thereby protecting dr ive assemblies and reducing output noise level.

1-10

from

logic

83323810 A

CONTROL DATA
CORPORATION
MINNEAPOLIS, MINN.
/

NORMANDALE DIVISION """

I STORAGE MODULE DRIVE~
EQUIP.
IDENT. NO .1 BK6A2A
PART
177456104
NUMBER

SERIES
CODE
SERIAL
NUMBER

02
147

\..

9WI72

Figure 1-3.

Equipment Identification plate

Equipment Identifico,tion Number

This number is divided into the two parts shown in the example:
EXAMPLE:
A2A

Equipment
Identifier-

83323810 A

j T

Type
Identifier

1-11

The equipment identifier indicates the basic functional capabilities of the drive.
This number will be either BK6 or
BK7..
The differences between these uni ts can be determined by
referring to table l-l~
The type identi f ier indicates differences between dr ives that
have the same equipment number.
These differences are necessary to adapt a dr ive to specific system requirements.
However, they do not change the overall capabilities of the drive
as defined in table 1-1.
Series Code

The series code represents a time period within which a unit is
built. While all units are interchangeable at the system level, regardless of ser ies code, parts differences may exist
wi thin uni ts buil t in different series codes.
When a parts
dif.ference exists, that difference is noted in the parts data
section of maintenance manual volume 1.
Part Number

This number indicates the top level
equipment and is for factory use only.

assembly

number

the

Serial Number

Each drive has a unique serial number assigned to it.
Serial
numbers are sequentially within a family of drives. Therefore,
not two equipments will have the same serial number.
FCO LOG

Field Change Orders
(FCO's)
are electrical or mechanical
changes that may be performed either at the factory or in the
field.
FCO changes do not affect the series code but are indicated by an entry on the FCO log that accompanies each
machine. The components of a machine with an FCO installed may
not be interchangeable with those of a machine without the FCO;
therefore, it is important that the FCO log be kept current by
the person installing each FCO.

1-12

83323810 A

MANUAL TO EQUIPMENT CORRELATION

Throughout the life cycle of a machine, changes are made either
in the factory build (a series code change) or by FCOs installed in the field.
All of these changes are also reflected in
changes to the manual package.
In order to assure that the manual correlates with the machine,
refer to the Manual To Equipment Correlation sheet located in
the front matter of the hardware maintenance manual.
This
sheet records all the FCOs which are reflected in the manual.
It should correlate with the machine FCO log if all the FCOs
have also been installed in the machine.

83323810 A

1-13

OPERAT~ON

SECTION 2

OPERATION

INTRODUCTION
This section provides the information and instructions necessary for operating the drive and is divided into the following
areas:
•

Controls and Indicators - Locates and describes various
controls and indicators related to operation of the drive.

•

Operating Instructions - Describes procedures for operati ng the dr i ve •

CONTROLS AND INDICATORS
GENERAL

The drive has two basic types of operator controls and indicators.
These are (1) operator control panel (2) power supply
control panel.
These are shown on figure 2-1 and explained in
the following.
NOTE

Additional controls and indicators contained
on cards in the logic chassis and used pr imari1y for maintenance are described in the
hardware maintenance manual.
OPERATOR CONTROL PANEL

The operator control panel contains switches and indicators to
control and monitor the basic operation of the drive.
Figure
2-1 shows these controls and :indicators and table 2-1 explains
their functions.

83323810 A

2-1

N
N

NOTES:

~ LOGICAL ADDRESS MAY
BE ANY NUMBER FROM
o TO 7.

LOGICAL ADDRESS
PLUG INSTALLS HERE

LOGICAL
ADDRESS 1:\
PLUG
~

POWER SUPPLY
CONTROL PANEL
9W68

Figure 2-1.

Controls and Indicators

TABLE :2-1.

OPERATOR CONTROL PANEL FUNCTIONS

Control or Indicator

Function

Logical Address Plug

Determine logical address of drive.
Address can be set any number from 0
to 7 by installing the proper plug.
If no plug is installed the address
is 7.
Drive comes from the factory
wi th complete set of log ica1 address
plugs each having a unique address.
The available plugs with their associated address and part number ar\~
listed in the parts data section of
the hardware maintenance manual.

START switch/Indicator

pressing button when drive is in
power off condition (disk pack not
spinning) lights indicator and starts
power on sequence, provided the following conditions are met.
•

Disk pack is installed •

• - Pack access cover is closed.
•

All power supply ci rcui t
ers are on.

break-

Pressing the indicator when drive is
in power on condition
(disk pack
spinning), extinguishes indicator and
starts power off sequence.
READY Indicator

Lights when uni t is up to speed, the
heads are loaded and no f aul t cond i tion exists.

FAULT
Switch/Indicator

Lights if a fault condition exists
within the drive. It is extinguished
by any of the following providing
reason for fault is no longer present:
•

l)ressing FAULT switch on operator control panel

Table Continued on Next page

83323810 A

2-3

TABLE 2-1.

OPERATOR CONTROL PANEL FUNCTIONS (Contd)

Control or Indicator

Function
•

Faul t Clear signal f r.om controller

Fault Clear switch
• Maintenance
on fault card in logic chassis
location Al7.
Conditions causing fault are descr ibed in the· discussion on Fault Detection in section 3 of this manual.
WRITE PROTECT
switch/Indicator

Pressing switch to light indicator
disables the driver write circuits
and prevents it from writing data on
the pack.
pressing the switch to extinguish the
indicator removes the disable from
the write circuits.

POWER SUPPLY CONTROL PANEL

The power supply control panel contains circui t breakers, test
points and a time meter.
These provide the means of controlling and monitoring operation of the power supply. The control
panel is accessed by opening the rear door of the dr ive cabinet.
Figure 2-1 shows the power supply control panel and
table 2-2 explains their functions.

OPERATING INSTRUCTIONS
GENERAL

This discussion describes the procedures that are performed
during normal operation of the drive.
These procedures are:
disk pack storage, disk pack removal and installation, power on
and off.

2-4

83323810 A

TABLE 2-2.

POWER SUPPLY CONTROL PANEL FUNCTIONS

Control or Indicator

Function

MAIN AC Circuit
breaker

Controls application of site AC power
to drive.
Closing this breaker applies power to blower and elapsed
time meter.

HOURS Elapsed
time meter

Records accumulated AC power on
time. Meter starts when MAIN AC circuit breaker is closed.

LOCAL/REMOTE

Controls whether drive can be powered
up from drive or controller
(remote).
In LOCAL position,
drive
power on sequence star ts when START
switch is pressed.
In REl-10TE position, drive power on sequence starts
when START swi tch 1S pressed and Sequence power ground is received from
controller.

+20Y, MOTOR, +46,
-46, +9.7, -9.7,
+20, -20, +28

Controls application of associated
voltages to drive and also provides
overload protection.

DISK PACK STORAGE

To ensure maximum disk pack life and reliabili ty, observe the
following precautions:
•

Store disk packs in machine-room atmosphere
90°F, 10% to 80% relative humidity).

•

If disk pack must be stored in different environment, allow two hours for adj ustment to compu ter env ironment before use.

83323810 A

(60°F

2-5

•

Never store disk pack in eli rect s'Jr"I.light or in di rty environment.

•

Store disk packs flat, not on edge.
with similar packs 'when stored.

•

Always be sure that hoth top and bottom plastic covers
are on disk pack and locked together whenever it is not
actually installed in a drive.

•

When marking packs, use pen or felt tip marker that does
not produce loose residue. Never use a lead pencil.

•

Do not attach any label to the disk pack itself.
Labels
will not remain attached when the pack is spinning and
catastrophic head crashes may resul t.
All labels should
be placed on the pack cannister if required.

•

Cleaning of pack surfaces is not recommended.

They may be stacked

DISK PACK HANDLING (CE AND DATA PACKS)

The positive pr~ssure filtration system of the drive eliminates
the need for per iodic inspection and cleaning of the disk pack
(media).
However, should improper operating conditions of the
pack be indicated by any of the following symptoms, immediately
remove the pack from the drive.
1.

A sudden increase in error rates related to one or more
heads is observed.

An unusual noise such as pinging or scratching is heard.

A burning odor is smelled.

Contamination of the pack
like is suspected.

from dust,

smoke,

oil or

the

If any doubt about the pack's functional condi tion exists, return it to the vendor, enclosing a descr iption of the known or
suspected malfunction.

2-6

83323810 A

CAUTION
Do not attempt to operate the media on another
drive until full assurance is made that no
damage or contamination has occurred to the
media.
Do not attempt to operate the drive with another media until full assurance is made that
no damage or contamination has occurred to the
drive heads or to the shroud area.
DISK PACK INSPECTION AND CLEANING

In some cases, the user may attempt to inspect and clean the
disk pack rather than return it to the vendor. This task must
be performed by properly trained personnel only, using the following procedure.
NOTE
Inspection and cleaning of disk packs in
field can cause additional problems for
following reasons:

the
the

•

Exposure of the pack to non-cleanroom conditions during
inspection and cleaning may additionally contaminate the
pack.

•

Disk surfaces may be scratched by using contaminated or
improper cleaning equipment.

•

The pack may be damaged while the covers are removed.

•

Deposits of cleaning solution residue may be left on disk
surface if improperly cleaned or if commercial grade solutions are used.

CAlJTION
Disk pack cleaning should never be attempted
with the pack mounted on the drive, since this
setup can introduce contamination into the
drive itself.
1.

Mount the pack on a commercially available pack inspection fixture.

83323810 A

2-7

Dampen, but do not soak, a lint-free swab-paddle with
media cleaning solution (refer to the list of Maintenance
Tools and Materials), or with a solution of 91% reagent
grade isopropyl alcohol and 9% deionized water by volume.

Using a sweeping motion, insert the damp swab-paddle between the disks and manually rotate the pack while applying the swab-paddle lightly to the disk surface to be
cleaned.

After the swab-paddle has been applied for one full
cleaning rotation, withdraw it with a sweeping motion
while maintaining contact with the disk surface (do not
lift the swab-paddle from the surface.

If oxide or contaminants are observed on the swab-paddle,
repeat steps 2, 3, and 4, using a clean swab-paddle for
each pass, until no oxide or contaminants are observed on
the swab-paddle.

6..

Repeat steps 3 and 4 using a dry swab-paddle to remove
all cleaning solution residue.

Repeat steps 2 through 6 for each surface.

DISK PACK INSTALLATION

The disk pack must be installed prior to performing any drive
operations.
Disk pack installation consists of setting the
pack on the drive spindle and rotating the pack until the pack
lockscrew is locked to the spindle lockshaft.
The following
describes this procedure.

CAUTION
Make certain that no dust or other foreign
particles are present in shroud area.
Also,
ensure that blowers operate for at least two
minutes prior to disk pack installation in order to purge blower system.
1.

Set circuit breakers to on and observe that blower starts.

Raise pack access cover.

Disengage bottom dust cover from disk pack by squeezing
levers of release mechanism in center of bottom dust
cover and set cover aside to an uncontaminated storage
area.

2-8

83323810 A

CAUTION
Non-fully retracted heads indicate a problem
in the dr i ves servo and may resul t in damage
to the pack or heads dur ing pack installation
or removal. If heads are not fully retracted,
contact: maintenance personnel. DO NOT push on
heads.
NOTE
Top dust cover actuates parking brake when
pack is set on spindle. Actuating brake holds
spindle stationary while pack is in~talled. A
click is heard as brake engages.
4.

Set disk pack on spindle, avoiding abugive contact between disk pack and spindle, then twist clockwise llnti 1
it is secured to spindle lockshaft.

Lift top dust cover clear of drive and store it with bottdm dust cover.

CAU1'ION
Spin pack to ensure that removing
cover released parking brake.
'6.

top

dust

Close pack access cover immediately to prevent entry of
dust and contamination of disk surfaces.

DISK PACK REMOV.AL

Disk pack removal consists of :cemoving the pack from the spindle, installing the dust covers and setting the pack aside in
an uncontaminated storage area.
The following descr ibes this
procedure.
1.

Press START switch to ~top drive motor and unload heads.

When disk pack rotation has stopped completely, open pack
access cover.

83323810 A

2-9

CAUTION
Non-fully retracted heads indicate a problem
in the drives servo, and may result in damage
to the pack or heads dur ing pack installation
or removal. If heads are not fully retracted,
contact maintenance personnel. DO NOT push on
heads.
3,.

Place top dust cover over disk pack so post protruding
from center of disk pack is received into dust cover handle.

Turn cover counterclockwise until disk pack
spindle.

free of

CAUTI·ON
Avoid abusive
spindle.

contact

between

disk

pack

and

Lift top cover and disk pack clear of drive
pack access cover.

and close

Place bottom dust cover on disk pack and store pack in an
uncontaminated storage area.

POWER ON PROCEDURE

following procedure descr ibes how power
drive.

ThE~

is applied to the

Set all power supply circuit breakers to on, and observe
that blowers start.

CAUTION
Allow blowers to operate for at least two minutes before installing disk pack.
2.

Install disk pack as instructed in disk pack installation
procedure.

Set LOCAL/REMOTE switch to desired position.

2-10

83323810 A

Press START switch to light START indicator. If drive is
in local mode, drive motor starts immediately and heads
will load when motor is up to speed.
If drive is in remote mode, drive motor starts and heads load whenever sequence power ground is available from controller (refer
to d iscI.lssi0n on power system in section 3 of this manual) •

Observe that READY indicator lights when heads have loaded. The drive is now ready for online operations.

POWER OFF PROCEDURE

The power off sequence can be started either locally or remotely depending on the setting of the LOCAL/REMOTE switch.
If
th is swi tch is in LOCAL, the sequence star ts when the START
swi tch is pressed to extinguish the START indica tor.
I f the
swi tch is in REMOTE, th~ sequence starts ei ther when the STA.RT
swi tch is pressed or when the sequence power g round signal is
disabled at the controller (refer to discussion on Power System
in section 3 of this manual).
In either case, the power off sequence unloads the heads, stops
the drive motor and extinguishes the REA.ny indicator.

83323810 A

2-11

THEORY OF OPERATION

SECTION 3

THEORY OF OPERATION

INTRODUCTION

The theory of operation section describes drive operations and
the hardware used in performin~~ them.
It is divided into the
following major areas (refer to figure 3-1):
•

Power System Functions - Describes how the drive provides
the voltage necessary for drive operation.

•

Electromechanical Functions
Provides a physical and
functional descr iption of the mechanical and electromechanical portions of the drives disk pack rotation, head
positioning and air flow systems.

•

Interface Functions - Describes the signal lines connecting the dr ive and controller.
It also descr ibes the I/O
signals carried by these lines and how they are processed
by the drive logic.

•

Uni t Selection - Explains how the controller log ically
selects the drive so the drive will respond to controller
comrnandso

•

Seek Functions - Explains how the servo logic controls
the movements of the head pos.i. tioning mechanism in positioning the heads over the disk pack.

•

Machine Clock Functions - Explains how this circui t uses
signals derived from the disk pack to generate timing
pulses for the index, sector and read/write circuits.

•

Sector Detection - Explains how the dr ive der ives the
sector pulses, which are used to determine the angular
position with respect to Index of the read/write heads.

83323810 A

3-1

FAULT AND
......... ERROR DETECTION

UNIT
- - - SELECTION

ELECTROMECHANICAL FUNCTIONS
rDRIVE
COOLiNGl
L
___
_ _ ...J

r----...,
r---, r-----,
HEAD
DISK

IpOSITIONING I I HEADS I I ROTATION I
L __ "__ -I L __ .J L ___ - J

I
N

T
E

F
A
C
CONTROLLER ......-"--...1"........

SEEK

~ FUNCTIONS

E
TRACK
ORIENTATION

F
U

r-----,
SECTOR
~D':TECTI~NJ

N
C

T
I

r----j

INDEX
I Dt::TECTION I

I
~

...
MACHINE
CLOCK

L ____ .J ~--....-....

RD/WRT
FUNCTIONS

POWER SYSTEM
FUNCTIONS

HEAD
SELECTION

9W69

Figure 3-1.

3-2

Drive Functional Block Diagram

83323810 A

•

Head Selection - Explains the head selection process.

•

Read/Nr i te FU.'lctions - Descr ibes how the cJr i ve processes
the data that it reads from and writes on the disk pack.

•

Fault Detection - Des~ribes the conditions that the drive
interprets as faults.

The descriptions in this secti.on are limited to drive operations only.
In addition, they explain typical operations and
do not list variations or unusual conditions resulting from unique system hardware or software environments.
Functional descriptions are frequently accompanied by simplified logic and timing diagrams.
These are useful both for instructional purposes and as an aid in troubleshooting.
However, they have been simplified to illustrate the principles of
operation.
Therefore, the diagrams (and timing generated from
them) in the hardw~ce maintenance manual should take precedence
over those in this manual if there is a conflict between the
two.

POWER SYSTEM FUNCTIONS
GENERAL

The major element in the drives power system is the power supply.
The power supply receive~ its input from the site ac
.- Ner source and uses it tc.") produce all the ac and dc vol tages
necessary for drive operation.
These voltages are distributed
to the drive circuitry via circuit breakers.
The drive motor is started and heads load function initiated
dur i ng the power on sequence.
The power of f sequence unloads
the heads ana stops the drive motor.
The drives LOCAL/REMOTE
switch permits these sequences to be initiated either at the
drive (local) or at the controller (remote).
The remainder of this discussion provides further descr iption
of the power system and is divided into the following areas:
•

Power Distribution - Describes how the power
uted to the drive circuitry.

•

Local/Remote Power Sequencing - Explains how the drive
may be powered up either at the drive or the controller.

83323810 A

is distrib-

3-3

•

Power On Sequence - Describes how power is applied to the
drive motor and the heads load sequence initiated.

•

Power Off Sequence - Describes how the heads are unloaded
and the drive motor stopped.

•

Emergency Retract - Explains sequence performed when conditions exist requiring the heads be unloaded immediately
to avoid damage to them or the disk pack.

POWER DISTRIBUTION

Power distribution consists of routing power to the various elements in the power supply and rest of the dr ive so that the
pOI,wer on sequence can be performed. The distribution is controlled by ci rcui t breakers located wi thin the power supply.
These circuit breakers also provide overload protection for
their associated voltages. The power distribution circuits are
shown on figure 3-2 and basic operation is explained in the
following.
Site main ac power is input to the power supply via the MAIN AC
circuit breaker. When this breaker is closed, it applies power
to the HOUR meter. It also provides the input to the drive motor control triacs; however, the motor does not start until the
power on sequence.
Closing CB2 applies power to T3 and enables +20Y. With +20Y
available, the transformers control triacs are enabled and
power is applied to transformers Tl and T2 and the blower motor.
These transformers provide inputs to the rect if ier and
capac i tor board (-YEN), which in turn produces the dc vol tages.
The dc voltages are applied to the rest of the drive
when their associated circuit breakers are closed.
When all ci rcui t breakers are closed, the dr ives power on sequence can begin.
LOCAL/REMOTE POWER SEQUENCING CONTROL
General

The power on and off sequence of each dr ive can be controlled
either locally or remotely depending on the setting of it
LOCAL/REMOTE switch. When this switch is set to LOCAL, the sequences are initiated at the drive. When the switch is set to
REMOTE, the sequences are initiated at the controller.

3-4

83323810 A

TO BRAKING

r-------~ C I RCUIT

______ ~--~1~6V~---------------~

+46V

TO VOICE

r---------..,:. CO IL

; . j~~/WRT

o----------------~~~

CHASSIS

u----------------~~~

~
H~~~

LINE

FILTERS

!5 VOLT
REGULATOR

TRANSFORMER
CONTROL
TRIACS

+20Y

CB2
/j""

IT31
<>-1J

~--.-+-Q~I
,

TO
LOGIC
CARDS

TO
SERVO
PREAMP

RECTIFIER!
CAPACITOR
BOARD
(-YEN)

RElAY BOARD
( -HN)

@[g][UJ
[MJ~

9W70
w
I

Figure 3-2.

Power Distribution

The LOCAL/REMOTE swi tch is located on the power supply control
panel and controls the mode of operation by determining how the
drives
sequence power
relay
(Kl)
is energized and deenergized.
This relay works in conjunction with the drives
START switch to control the power on and off sequences.
Figure 3-3 shows the LOCAL/REMOTE power sequencing control circuits. The operation of these circuits in both local and remote modes is explained in the following paragraphs.
Lc»cal Control

When the dr i ve is in the local mode, the sequence power relay
(Kl) energ izes whenever '+20Y is available.
This vol tage is
available whenever the MAIN AC circui t breaker (CBI) and +20Y
ci rcui t breaker (CB2) are closed.
In this mode, the power on
sequence begins when the START switch is pressed (providing all
circuit breakers are closed). The powe~ off sequence is initiated by pressing the START switch to extinguish the indicator.
Remote Control

the dr i ve is in the remote mode, the power sequence relay
(Kl) is energized by the power sequence signals (Pick and Hold)
from the controller. The power on sequence does not begin un1 e S5 the se s i g nal s are r ece i ved and the START sw itch is pre ssed. Both must occur for the power on sequence to take place.
I f

The drive is powered down either when the START switch is pressed or when the power sequence signals from the controller are
deactivated.
l~igure 3-4

is a flow chart of ' the remote power control sequence.

IPOWER ON SEQUENCE

'rhe power on sequence
loading of the heads.

starts

the

dr ive motor

and

ini tiates

The sequence is ini tiated by pressing the START swi tch on the
operator control panel.
If all circuit breakers are closed,
the disk pack is installed and the pack access cover is closed,
pressing this switch energizes the Start relay (K2).

3-6

83323810 A

CONTROLLER
r------,
I

DRIVE

r--- -----------...,
I

I
I

REMOTE

PICK

I.
I

~AL
--

I
I

REMOTE

1-=

L Lr~AL

I
I

T
I

I
I

I
L ____ ..J

L____.

_ _ _ _ _ _ _ _ _ _ -lI

NOTE: I. ALL RELAYS SHOWN IN THEIR NORMAL POWER OFF CONDITION.

9W71

Figure 3-3.

83323810 A

Local/Remote Power Sequencing Control Circuits

3-7

I
CX)

DRIVE LOCALI
REMOTE SWITCH
IN REMOTE

PICK AND
HOLD AVAILABLE FROM
CONTROLLER

PICK SEQ PWR
RELAY Kl

START
SWITCH
ON

INITIATE DRIVE
PWR ON
SEQUENCE

PICK SPEED
RELAY K3

9W72
co
w
W

tv
W
CX)

.....
o

Figure 3-4.

Remote Mode Power Sequencing

The Start relay causes the Motor relay (K4) to energize and enable the Motor Control triacs. This applies power to the drive
motor causing it to start. The drive motor transfers motion to
the spindle via the drive belt and the disk pack starts to rotate.
When the speed sensing circuits indicate the spindle speed is
about 2700 r/min, the Speed relay (K3) energizes.
This does
two things (1) energizes the Emergency Retract relay (K7) and
(2) triggers the 10 second Load Delay one shot.
Energizing the Emergency Retract relay connects the power amplifier to the voice coil and connects the Emergency Retract
capacitor to -16 volts.
This prepares the voice coil to respond to commands from the servo logic and charges the Emergency Retract capacitor so it is ready for an emergency retract
condition.
The Heads Load Delay allows the spindle time to reach 3000
r/min before enabling the heads load logic.
When the delay
times out, the heads load sequence is initiated causing the
heads to load.
This sequence is covered in the discussion on
Load Seeks.
Figure 3-5 shows the circuitry involved in the power
quence and figure 3-6 is a flow chart of the operation.

83323810 A

se-

3-9

+ 9. 7V

-9.7V

+20V

CB5

CB6

CB7

START
~

r-o"'o-----<5'o---<>~

&
+5V

+20Y

@
A3S1

D---.-----<-T

~(>-----I

PACK ACCESS
COVER SWITCH

PACK ON
SW

'----.J

HDS LOADED
SW

r----,

HDS
I
LOADED

+20Y

HDS
I
':" UNLOADED

L_____ J

CD G)
K2

~ r-----I

(812) (812)

r-- - - - - - - - ,
I
RUN
:
I

I
I
1 .,..,
...__---t!4t--_ _

(812)

PULL MOTOR

~I_R_E_LA_Y___-i.o-'F_'-;---

I
I

I
-I

IL... _ _ _ _ _ _ _ _ _ .....I

MOTOR RELAY LOGIC
(082)
PACK
+20Y
ACCESS
COVER
SOLENOID

NOTES:
1. ALL RELAYS ARE SHOWN IN
THEIR NORMAL POWER OFF
CONDITION.
2. NUMBERSr-JSHOW SEQUENCE AS
INDICATEDION FIGURE 3-7.
3. NUMBERS (XXX) REFER TO
DIAGRAMS REF. NO.
9W73-1

Figure 3-5.

3-10

Power On Circuit (Sheet 1 of 2)

83323810 A

r - - - - - - - - - - -,
DRIVE MOTOR (2)
I

I
I

RUN CD

RUN

I---+--~--:- - - - - - I WI NO I NG
I

TRIAC

I
I

RUN CD

CB3

I'"i'

0--0 I 0--+--+--+--1 I - - - + - - + - : V f - - - - - - - t - ' Lr+----'

TRIAC

208V

:
I
I

0--0

CNTFGL
SW

START0®-=

~1)---t---+-------4 I----+---,---+-~

TRIAC
~,

(804)

IL- _

_ _ _ _ _ _ _ _ .J

+20Y
& 1------1

@
K3
1
(81 2)

+20Y

SPEED

--{iiJ~--I(812)

SPEED
X OCR
(083)

SPEED DETECTION LOGIC
(083)

10 SEC LOAD

DELAY
(082)

'---_ _~ PWR

AMP
(832)

LOGIC

(,~

VOICE
COIL

HDS LOAD

QJD

(83~ CARRIAGE ~HEADSI

!MAGNIT,l'
-=-

9W73-2

Figure 3-5.

83323810 A

power On Circuit (Sheet 2)

3-11

HOTES:
I.

"UM8rRS 0 RHER TO [L[I1ElnS ON POUFIl
CIRCUIT DIAGRAM.

~U"BER§

(XXX) REF£R TO DIA~RAM Rrr.

READY ll~HT STOPS
AP.E LOADED.

rlASHlh~

~O.

AFTER "fAOS

'HI74-1

w
W

N
W

co
I-'

Figure 3-6.

power On Sequence Flow Chart (Sheet 1 of 2)

. . p/'-

/~/f.Jr-'

fT.;; /

c1a ft·
r

.; riA

W
t.J
W

"..
.' (.,1}

t) (.. t:
(t:;

,J:;
'r (;':.---_ _ _-.

\!..r

I'ROVI DES DOWER
TO DR I V[ r~OTOR
CAUSIIlG IT TO
START

Q)
.....,

(804 )

KEEPS PACK
ACCESS COVER
LOCKED UNT Il
PACK STOPS
TUiHl i NG

.-----'------.

YES

9W74-2

Figure 3-6.
w

I
.....,

Power On Sequence Flow Chart (Sheet 2)

POWER OFF SEQUENCE

The power off sequence unloads the heads and stops the dr ive
mote)r.
The sequence begins when either the START switch is pressed or
the Sequence Power relay (Kl) is deenergized.
In either case
the Start relay (K2) deenergizes and the RTZ logic is enabled
(refer to discussion on Return to Zero Seeks). This causes the
heads to move in the reverse direction.
When the heads unloaded swi tch indicates the heads are unloaded, the RTZ logic is disabled and the motor relay (K4) is deenergized. Deenergizing the Motor relay (K4) removes power from
the drive motor and enables the braking logic.
Enabling the
brake logic initiates the braking sequence.
The braking sequence begins by energizing the Brake Power r.elay
(K5) which in turn energizes the Brake relay (K8). The Brake
relay applies -16 Vdc causes a current to flow through the
winding and the magnetic field generated by this current has a
braking effect on the motor.
The motor slows down and when its speed is less than 2700
r/min, the Speed relay (K3) deenergizes. This in turn causes
the Emergency Retract relay (K7) to deenergize thus disconnecting the power amplifier from the voice coil.
The Brake power and Brake relays deenergize approximately 30
seconds after the start of the braking sequence. This removes
braking voltage from the drive motor, which by this time is
stopped. This also removes power from the pack access solenoid
thus allowing t~e pack access cover to be opened.
Fig 'J re 3-7 shows the circuitry involved in the power off sequence and figure 3-8 is a flow chart of the operation.
EMERGENCY RETRACT

The emergency retract function provides an emergency means of
retracting the heads from the pack area. This sequence is initiated if disk speed is reduced or if conditions indicate that
it may be reduced.
Failure to retract the heads under these
condi tions could result in head crash a subsequent damage to
the heads and disk pack.
Any of the following conditions ini tiate an emergency retract
sequence:
•

Loss of AC Power - If site ac power is lost, all dc power
is also lost. This power loss includes +20Y, +9.7, and
-16 V, any of which cause an emergency retract to occur.

3-14

83323810 A

+9. 7

--crb--o

STt

A3S1

A3S4

START

+20Y

CD ....------.

K2
Kl ENABLE RTZ
PWR
""----1 AMP
(812 ) ( 812 )
LOG I C
(832 )

+5V

O--O-~~----41 K2 I t

0--0

@
K7

VOICE COIL
~....I--++-I

CARRIAGE

HDS LOADED
SW

,-------,
I

0---,

HDS,
LOADED :,

-...L

'HDS

II UNLOADED

I'- _ _ _ _ _ _ _ _ ..JI

r--- -----,

0:,
K4 ,

~~'~I
I

BRAKE
Jj i--ooAo-.&.;II,I SEQ
-.:- (812 )
LOG I C
(813

MOTOR
, PULL
RELAY

STOP:

BRAKE
PWR

+20Y

I
I

(812 ) IL ________
(082) J:

-= MOTOR RELAY LOGIC
(082)

NOTES:
1. ALL RELAYS ARE SHOWN IN (812)
THEIR NORMAL POWER ON
CONDITION.
2. NUMBERSc-)SHOW SEQUENCE
AS INDICATED ON FIGURE 3-9.
3. NUMBERS (XXX) REFER TO
DIAGRAM REF. NO.
4. AUXILIARY CONTACTS OF
THESE CIRCUIT BREAKERS.

Figure 3-7.

83323810 A

MOTOR
K4
(812)

0+20Y
TRIAC PWR

9W75-1

Power Off Circuits (Sheet 1 of 2)

3-15

FROM
T1

16 VAC
K8
(804)

0(8)
8 14

MOTOR
CB2

I
I
I

RUN

RUN
WINDING
(804)

--0

(804)
208V

I
I

I
I
I

I
-~

RUN

--0

(804)
+20Y

~PEED
DETECTION

Figure 3-7.

3-16

(812) ((12)

@ +20Y EMERGENCY

SPEED
I K3 I
(082)

1 RETRACT
I K7 ]
(812)

0©

BRAKE
1(8
(813)
PACK ACCESS
COVER SOL

(8l2)

@
K3

Jr l
--

9W75-2

Power Off Circuits (Sheet 2)

83323810 A

w
W
N

co
I-'

START SUI Tell
OH SEn
!'WR PELAY
DEUI[HGIZES

rR£S~ED

( ~RP.ll\rf flf)V[ S
PI VI 'l~l AT
1 I!l/ '>I C

t---~ 1'1

(77 3)

110 as:

tlurlBERS
RfffR TO [L[rl[IHS ON JlO"f~
Off CIRCUIT DIAGRAM.

tllIHBERS (XXX) Rlf[P To..OIAI;P.AI1 Rrf. IWI1(H II'>

77':<'"

flt'MPVC'
jIl!'At ,.,

/",,: ......-,;.,;"'-,
r.I PI ( &
(;...&11 "",

?~2

Figure 3-8.
w

I
I--'

......

~
/'

f2 eAPY
CO(f"",)

9W7f-l

C)vr-

1?e~·-(. t~ J"i"" A- a.cc"J~/

Flow Chart (Sheet 1 of 2)

e.DI/CI'(

,j'Qc.IP/('ID

w
I
r-

(I)

O[[N[ RG III

BRAKE PHR
RElAY K5
(813 )

OEENERGI Z£

BRAK[ RELAY
KIl

END or
SEOUENC[

( 913)

PACK ACCESS

COVER SOLENOID
ENERGIlfS

91-176-2

Figure 3-8.

(I)

w
W
N
W
(I)

Power Off Sequence Flow Chart (Sheet 2)

•

Loss of +20Y, -16, or +9.7 V - Losing any of these voltages directly causes the emergency retract relay to deenergize thus starting the emergency retract sequence.

•

Loss of Speed - If spindle motor speed drops below 2700
rlmin, the speed detection circuits cause the emergency
retract capacitor to deenergize.

•

Drive Motor Thermal Overload - If the drive motor overheats, a thermal relay within the motor opens.
This results in t.he Motor circuit breaker opening and removing
power from the dr ive motor.
The motor then slows down
and the loss of speed causes a emergency retract.

Figure 3-9 shows the circui try
tract sequence.

involved

in the

emergency

re-

ELECTROMECHANICAL FUNCTIONS
GENERAL

Certain dr ive functions are a result of the electromechanical
devices working under the control of logical circuitry.
These
functions include disk pack rotation, head positioning, and
dr ive cooling and ventilation.~
Disk pack rotation is performed by the disk pack rotation mechanism, which is controlled by the power system.
The purpose
of disk pack rot.ation is to create a cushion of air on the disk
surfaces.
The cushion of air allows the heads (which read and
write the data) to move over the disk surfaces without actually
contactinq them.
The heads are posi tioned over specific data tracks on the disk
surface by the head positioning mechanism.
The mechanism is
controlled by the servo circuits (refer to discussion fo Seek
Operations) and the power system.
Dr ive cooling and ventilation is provided by the air flow system. The main element in this sytem is the blower motor which
receives its power from the power system.
Figure 3-10 is a block diagram showing each of the previously
discussed mechanisms.
A more detailed physical and functional
description of each is provided in the following discussions.

83323810 A

3-19

UN~ED

~-HDS
-

-16V

HDS
LOADED

HEADS ~
+20V
LOADED
RELAY
LOADED
K6 ,......- - - -

I
CD

POWER AMP
( 83 2 )
1--4.........-7---:..V"
....0I0r.""'" CAP. RI AGE

0·

(803)
2 (803) +20V

CD
EMERGENCY

(832)IRETRACT CAP

EMER
RETRACT
RELAY
K7
(812)
SPEED
DETECTION __--I SPEED
LOGIC
X OCR
(083)
(083)
NOTES:
1. ALL RELAYS ARE SHOWN IN ENERGIZED CONDITION.
2. NUMBERS () REFER TO SEQUENCE OF EVENT DURING EMERGENCY
RETRACT.
3. NUMBERS (XXX) REFER TO DIAGRAM REF. NO.
9W77

Figure 3-9.

3-20

Emergency Retract Circuits

83323810 A

r- - - - - - - - - - - - - - - - - - - - - - - - - - - - - . . ,

ELECTROMECHANICAL

READ/WRITE
FUNCTIONS
SEEK FUNCTIONS

r""
""-

HEAD
POSITIONING

r""

I
'v
HEADS

AIR FLOW
SYSTEM

DISK PACK

DISK PACK
ROTATION

L----

- - - - _________________ .J

NOTE:
1. c::::JMECHANICAL
-POWER
----CONTROL SIGNAL
POWER SYSTEM
9WI77

Figure 3-10.

83323810 A

Electromechanical Functions Block Diagram

3-21

DISK PACK ROTATION
General

The disk pack must be rotating fast enough to allow the heads
to fly before any dr ive operation can be performed. The following mechanisms work in conjunction with the po~er system to
control disk pack rotation (refer to figure 3-11):
•

Drive Motor and disk pack.

Provides rotating motion for

•

Spindle pack.

•

Parking Brake - Holds spindle while pack is being installed.

•

Speed Sensor - Generates pulses that are used to determine speed of spindle.

•

Pack On Switch - Actuated when pack is installed on spindle, th is device must indicate the pack is installed before the power on sequence can be performed.

•

Pack Access Cover Switch - Ensures that pack access cover
is closed before disk pack rotation begins.

•

Pack Access Cover Solenoid - Prevents pack access cover
from being opened while pack is rotating.

Provides

rotating 'mounting

the spindle

surface

for

disk

These mechanisms are fllrther descr ibed in the following paragraphs.
Drive Motor

The drive motor provides the rotational energy required to rotate the spindle and disk pack. The motor is mounted on a movable plate which in turn is mounted on the under s ide of the
deck casting (refer to figure 3-12).
Motion is transferred from motor to spindle via the drive
belt. This belt connect~ the pulley on the shaft of the drive
motor to the pulley on the lower end of the spindle.
'I'he springs attached between the motor mounting plate and deck
casting, maintain enough tension on the plate to keep the drive
belt tight. The spring tension is adjustable so tension on the
belt can be adjusted to provide the best coupling between drive
motor and spindle pulleys.

:3-22

83323810 A

PACK ACCESS
COVER SWITCH
PARKING BRAKE
SPINDLE
SPEED SENSOR

PACK ACCESS
COVER SOLENOID

POWER SYSTEM
NOTE:

1.0 MECHANlCAL
_

POWER

---- CONTROL SIGNAL
9Wl79

Figure 3-11.

83323810 A

Disk Pack Rotation Functional Block Diagram

3-23

SPINDLE
PULLEY

MOUNTING

9EI02

Figure 3-12.

3-24

Drive Motor Assembly

83323810 A

The motor starts during the power on sequence when power is applied to its start and run windings (refer to Power On Sequence
discussion). The start winding helps the run winding start the
motor in motion and get it up to speed. When the motor speed
reaches approximately 1700 rlmin, the start winding is no longer needed and a -centrifugal switch (within the motor) opens
thus disabling the start winding. The motor continues to accelerate (using only its run winding) until it reaches its maximum speed (approximately 3600 r/min). This speed is maintained until power 1s removed from the motors run winding (refer to
discussion on Power System).
The temperature of the motor :is monitored by the thermal
switch. If the motor overheats, this switch opens resulting in
loss of power to the drive motor. The motor slows down causing
an emergency retract and power off sequence. The dr ive motor
cannot be restarted until it cools off, thereby causing the
thermal switch to close.
Spindle

The spindle (refer to figures 3-13 and 3-14) provides the means
of mounting the disk pack within the drive and also of rotating
the pack when the drive motor is energized.
iihen the pack is mounted, its lower disk rests on the pack
mounting plate. This plate connects to a shaft which in turn
connec ts to the pulley on the lower end of the spindle. When
the drive motor starts, it trans:fers motion to this pulley via
the drive belt and causes the pack mounting plate and disk pack
to rotate.
The disk pack must be secured to the mounting plate with enough
force so the two of them will rotate together. This force is
provided by the lockshaft, which is a spring loaded shaft located wi thin the spindle.
When the pack is installed, the
mounting screw on the bottom of the pack is threaded into the
internal threads in the upper end of the 10ckshaft. As the
pack is tightened down against t:he mounting plate, the spr ings
holding the lockshaft exert a downward force on the pack. When
this force is sufficient, a release mechanism (in the handle of
the disk pack top dust cover) releases the top dust over from
the pack. The pack is now installed and will rotate whenever
the drive motor is energized.
A ground spr irig (refer to figure 3-13)
electricity accumulating on the spindle.

83323810 A

bleeds off any static

3-25

PACK MOUNTING
PLATE

INTERNAL
THREADS
I

LOCKSHAFT

~===dG;~:~:'5:e!~==~~
I'

SPINDLE
HOUSING

STATIC GROUND SPRING

Figure 3-13.

3-26

9W78

Spindle Assembly

83323810 A

BRAKE
ACTUATOR BUTTON

ESRAKE TOOTH

Figure 3-14.

83323810 A

9EI04

Parking Brake Assembly

3-27

Parking Brake

The parking brake (refer to figure 3-14) holds the spindle stationary whenever a disk pack is installed or removed.
It is
actuated by the disk pack top dust cover which contacts the
brake actuator button. This causes the brake tooth to move up
and engage a slot in the bottom of the spindle thus preventing
the spindle from rotating. When the dust cover is removed, the
actuator button is released, the brake tooth disengages, and
the spindle is free to turn.
Speed Sensor

The speed sensor (refer to figures 3-15 and 3-16) is a device
that generates signals used to determine if spindle speed is
suff ic ient to allow the heads to fly.
The sensor is mounted
beneath the spindle and consists of a small coil and core assembly.
The coil has a current flowing through it and each
time the pin mounted on the bottom of the rotating spindle aligns itself with the core of the coil, a signal is generated.
The speed sensor logic moni tors these signals and uses them to
determine if spindle speed is at least 3000 r/min. When this
speed is reached, the speed relay is energized; and it remains
energized as long as this speed is maintained.
However, if
spindle speed drops below 3000 rlmin the speed relay deenergizes refer to discussion on Emergency Retract).
Pac:k On Switch

The disk pack must be securely installed on the spindle for the
drive motor to run. This condition is ensured by the pack on
sw:L tch.
The swi tch is located beneath the spindle (refer to
figure 3-15) and is actuated by the lockshaft when the pack is
installed.
If the pack is not completely installed, the switch will not be
closed and the drive motor will not start.
If the pack comes
l~ose during drive operation and the pack on switch opens, the
po'wer off sequence is initiated thus stopping the drive motor.
Pack Access Cover Switch

In addition to the pack on switch, the pack access cover switch
(refer to figure 3-16) must be closed for the drive motor to
run. This switch ensures that the pack access cover is closed.
Opening the switch has the same effect as opening the pack on
switch.

3-'28

83323810 A

-:--'SPINDLE

WIRES TO [
SPEED
DETECTION
LOGIC

SPEED SENSOR

~~tP']WIRES TO POWER SYSTEM
CIRCUITS

PACK ON SWITCH

Figure 3-15.

83323810 A

9W79

Speed Sensor and Park On Switch Assemblies

3-29

PACK ACCESS COVER
SOLENOID

PACK ACCESS
COVER SWITCH
9W80

Figure 3-16.

3-30

Pack Access Cover Switch and Solenoid

83323810 A

Pack Access Cover Sotenoid

If the drive is equipped with a pack access cover solenoid (ref er to f i gur e 3-16), the pack access cover can be opened only
if the drive is in the standby condition, that is with the circuit breakers on but the heads unloaded and the disk not rotating.
The solenoid controls the operation of the pack access
cover as follows.
Our ing the power on sequence when the pack starts turning, the
solenoid is deenergized and a spring pushes the solenoid arm
upwards. This locks the pack access cover latch and prevents
the cover from being opened.
If the drive is in the standby condition, the solenoid is ener9 ized and the arm is pulled down. This releases the pack access cover latch and allows the cover to be opened.
HEAD POSITIONING

General

Data is read from and wr i tten on the disk by the heads. However, the drive must position the heads over a specific data
track on the disk before a read or write operation can be performed. Head positioning is performed by the head positioning
mechanism.
This mechanism consists of the actuator, magnet, velocity transducer and heads loaded switch.
The actual positioning is performed by the actuator and magnet. The Fositioner is controlled by signals received from the
servo circuits (refer to discussion on Seek Functions).
The velocity transducer and heads loaded switch provide signals
that are used by the servo circui ts in controlling head positioning.
Figure 3-17 is a functional block diagram of the head positioning mechanism. The following paragraphs provide further description of the elements shown on this figure.
Actuator and Magnet

General
The actuator and magnet (refer to figure 3-18) work in conjunction to posi tion the heads. The following is a physical and
functional description of the actuator and magnet assemblies.

83323810 A

3-31

HEADS LOADED
SWITCH

. . FEEDBACK
I'

I
SERVO
CIRCUITS

MAGNET

1- I
ACTUATOR ....JAI
C
______
POSITION
SIGNAL .., 1
I ~ I
VOICE
I I 1
I
COIL
1
I~ I

HEADS

DISK PACK

1------1[,1

..._FEEDBACK

VELOCITY

TRANSDUCER

I
9WI78

Figure 3-17.

3-32

Head Positioning Functional Block Diag~am

83323810 A

ACTUATOR

MAGNET

BEARINGS
ACTUATOR
HOUSING
UPPER
RAIL

VOICE COIL
FLEX LEADS
CARRIAGE

LOWER
RAIL
NOTE:

ALL HEADS ARE NOT SHOWN
CARRIAGE ALSO HAS LOWER
REAR BEARINGS NOT SHOWN.
9W81

Figure 3-18.

83323810 .A

Actuator and Magnet Assembly

3-33

Actuator and Magnet Physical Description
The actuator and magnet are located on the
deck (refer to figure 3-18).

rear

half of

the

The actuator consists of the carriage and voice coil both of
which are contained in the actuator housing.
The carr iage is
mounted on bearings that allow it to move in a forward or revel'se direction along rails attached to the actuator housing.
The rear of the carriage forms a cylinder around which the
voi.ce coil is wrapped.
The heads are mounted on the forward
end of the carriage, therefore, the heads, carriage, and voice
coil move together as a unit.
ThE! magnet mounts directly behind the actuator and is a one
piece assembly consisting of large permanent magnet. The magnet: contains a circular cutout which allows the voice coil to
move in and out of the magnet as the carriage moves.
Actuator and Magnet Functional Descriptio~
The movement of the carriage and voice coil (and therefore the
heads) is controlled by positioning signals from the servo
logic.
The positioning signals are derived in the seek logic
and processed by the power amplifier. The output of the power
amplifier is a current signal which is applied to the voice
coil via two flexible insulated metal str ips called the voice
coil flex leads.
The current from the power amplifier causes a magnetic field
around the voice coil which reacts with the permanent magnetic
field· around the magnet. This reaction either draws the voice
coil into the magnetic field or forces it away, depending upon
the polarity of the current through the voice coil. The acceleration of the voice coil is dependent on the amplitude of the
voice coil current.
Velocity Transducer

The velocity transduc'er (refer to figure 3-19) mounts within
the magnet and consists of a stationary coil and a movable magnetic core. The core is contained within the coil and connects
to the carriage via an extension rod. Therefore, when the carr iage moves, the motion is transfer red via the extension rod to
the core.

3-34

83323810 A

~r-~CItt",J.?"""}.....7.,,,'---41" LOGIC
CARRIAGE \ ------i CORE I
t-

VELOCITY

COIL HOUSING (CONTAINS COIL)

EXTENSION ROD
(CONNECTS
MOVABLE CORE
TO CARRIA,\

9W82

Figure 3-19.

83323810 A

Velocity Transducer Assembly

3-35

When the carr iage and core move, an EMF is induced in the
coil.
The amplitude of this EMF varies directly with the veloc i ty of the carr iage and the polar i ty of the EMF depends on
the direction of carriage motion.
The output of the veloci ty transducer is sent to the servo
logic which uses it to control the acceleration of the carriage
during seek operations.
Heads Loaded Switch

The heads loaded switch (refer to figure 3-20) mounts in the
actuator housing and indicates whether the heads are loaded or
unloaded. This information is used by the seek logic and power
on/off s~quencing circuits.

HEADS LOADED SWITCH

9W83
Figure 3-20.

3-36

Heads Loaded Switch Assembly

83323810 A

The switch is actuated by the carriage as the heads are loaded
(moved out over the disk surfaces) or unloaded (moved clear of
the disk surfaces and pack area). The switch indicates an unloade~
status when the carriage is fully retracted and the
heads are clear of the pack area.
Dur i ng an unload· sequence, the car r i ag e ret r ac ts and tr ans fer s
the switch, to indicate an unloaded condition, just as the
heads leave the pack area.
HEADS
General

The heads are electromagnetic devices that record data on and
reaJ it f rom the disk pack. They are mounted in the end of a
supporting arm and head and arm "together are called a head-arm
assembly. The head-arm assembliE!s attach to the carr iage (refer to figure 3-21).
The drive has 20 heads, one for each disk surface. There are
two types of heads (1) read/write and (2) servo. There are 19
read/wr i te heads which are used to record data on and read it
f rom the data su:rface. There is one servo head which is used
to read information from the servo surface. This information
is used by the drives servo circuits.
The following describes the physical characteristics of the
head-arm assemblies and also how they function during head load
and unload sequences. Further information concerning the heads
Head-Arm Asse mblies Physical Description

Each head-arm assembly consists of a rigid arm, heads load
spring, gimbal spring, and the head (refer to figure 3-22).
is found in the discussions on read/write and seek functions.
The rigid arm is mounted on the carr iage and causes csrr iage
motion to be transmi tted to the head. However, the arm does
not provide the action necessary for the head to load, unload
and follow the disk surface. This action is provided by the
head load and gimbal springs.
The head load spring attaches to the
mounting point for the gimbal !;pr ing.
taches to the gimbal spring.

83323810 A

rigid arm and is the
The head in turn at-

3-37

HEADS
(ALL ARE
NOT SHOWN)

HEAD CAMS

CARRIAGE

Figure 3-21.

Heads

9W84

Dur ing head loading and unloading, the head load spr ings ride
on the head cams and keep the heads from contacting one
another. When the heads are loaded, the head load and gimbal
springs work together and allow the heads to move independently
of the rigid arms in the directions shown in figure 3-22. Such
motion is necessary because when the heads are over the disk
surfaces they do not contact the disk buyt actually fly on a
cushion of air created by the spinning of the disk pack.
Information is sent to and from the heads via the head-arm cables.
One end of each able connects to a head and the other
end has a plug which connects to a card in the read/write chassis.

3-38

83323810 A

HEAD HAS FREE VERTICAL
MOVEMENT IN Z DIRECTION
INDEPENDENT OF RIGID ARM.

_D_I~It-K_R_OT_A_T_I_O_N_ _D_IR~CTION ~

CARRIAGE

RIGID

------I
ZA~

NOTE:
1. HEAD CABLE CONNECTING
HEAD TO DRIVE
IS NOT SHOWN

THIS SURFACE RIDES ON CAM
HEAD, LOAD IS APPLIED AT CENTER.
Y AXIS
X, Y AND Z AXES PASS THROUGH
'~CENTER
,
HEAD HAS FREE
ROTATION ABOUT THIS
AXIS INDEPENDENT
OF RIGID ARM.

HEAD LOAD
SPRING

Figure 3-22.

eN
\0

HEAD HAS FREE
ROTATION ABOUT THIS
AXIS INDEPENDENT
OF RIGID ARM

Head-Arm Assembly

9W168

Head Loading

The heads must be loaded before the heads can be positioned to
a data track for the recording and readi.ng of data.
Loading
the heads consists of moving them forward from their retracted
(unloaded) positions until they are over the disk surfaces.
All heads are loaded simultaneously.
The load sequence is ini tiated dur ing the power up sequence
when the disk pack has reached 3000 r/min. At this speed the
spinning disk creates a sufficient cushion of air to allow the
heads to fly.
When the pack is up to speed and the load logic is enabled, the
heads move forward wi th the head load spr ings riding on the
head cams.
As the heads move out over the disk surfaces, the
head load springs ride off the surfaces, of the head cams (refer to figure 3-23).
The load springs, while riding off the cams, unflex and force
the heads toward the air cushions on the spinning disk surfaces.
When the cushions of air are encountered, they resist
any further approach by the heads.
However, the head load
springs continue to force the heads down until the opposing air
and spring pressures are equal.
The air cushion pressure varies directly with disk speed and if
the disk pack is rotating at the proper speed, the air and
spr ing pressures should be equal when the heads are flying at
the correct height above the disks.
If the disk pack drops below this speed, air cushion pressure
decreases and the head load spr ings force the heads closer to
the disks.
Sufficient loss of speed causes the heads to stop
flying and contact the ~isk surfaces.
Because insufficient disk speed causes head crash, loading occurs only after the disk pack is up to speed.
For the same
reason, the heads unload automatically if disk pack speed drops
below a safe operating level (refer· to discussion on emergency
retract) •
.
Head Unloading

The heads must be unloaded whenever the pack is stopped or if
it is spinning too slowly to fly the heads. Unloading consists
of retracting the heads until they are no longer over the disk
surfaces.

3,-40

83323810 A

HEAD LOAD SPRING
RIGID ARM
r----.,---:------r-

L- - - - - - .

UNFLEXED PROFILE
OF HEAD ASSE MBLY

CAM SURFACE

HEAD

~~~_

DUAL SURFACE DISK
(PART OF DISK PACK)

CAM lOWER RAMP

CARRIAGE

\17 ==-=-:c~J=--L-~~_-_-_-~
S==;;--i.
=:

CUSHIONING LAYER OF AIR EXISTS
ON SURFACE OF SPINNING DISK.
HEAD GIMBALS COMPENSATE FOR
DISK VAR lATIONS.

~
~

HEADS LOADED-CAM SURFACE ON EACH
HEAD ASSEMBLY RIDES OFF CAM TOWER AS
CARRIAGE EXTENDS. MOVEMENT OF
HEAD LOAD SPRING MOVES HEAD
TOWARD DISK SURFACE UNTIL OPPOSING
FORCE OF AIR LAYER CANCELS
FORCE OF HEAD ASSEMBLY.

9H48

Figure 3-23.

HEAOS UNLOADED-CAM
SURFACE ON EACH HEAD
ASSEMBLY RIDES ON CAM
TOWER WHEN CARRIAGE IS
RETRACTED. HEAD FACE
MOVES CLEAR OF
DISK SURFACE.

Head Loading

The unload sequence is ini tiated either dur ing a normal power
off sequence, or during an emergency retract function. tn both
cases current is applied to the voice coil that causes the carriage to move back towards the retracted stop.
As the carr iage retracts, the head load spr ings encounter the
head cam sur faces and the heads are pulled away from the disk
surfaces. The carriage continues to move back until it is fully retracted.
AIR FLOW SYSTEM

The air flow system (refer to figure 3-24) provides ventilation
and cooling air for the drive.
The heart of the air flow system is the blower assembly. This
assembly consists of the blower motor, absolute filter, input
port from primary filter and output ports to the logic chassis,
power supply and pack area.
The blower motor provides the pressure needed to draw air into
and push it through the system. The system intake port is located beneath the rear of the cabinet. This port is covered by
the primary filter which keeps large particles from being drawn
into the system. Air flows from the intake port through a duct
in the floor of the cabinet to the blower motor.
The blower motor forces the air to the power supply, logic
chassis, pack area and deck areas. The air to the logic chassis and power supplies, flows through hoses connected between
these assemblies and the blower assembly. The air exhausted by
the power supply and logic chassis circulates through the lower
part of the drive cabinet and provides cooling air for the
spindle motor.
The air to the pack area is filtered by the absolute filter
which removes particles that might cause damage to the pack or
heads.
The air is forced into the pack area from all sides
causing a positive pressure. This results in an upward dispersion of air, thus preventing the entrance of contaminated air
through the pack access cover.
. The air intake for the pack area is also forced into the deck
area through vents in the rear of the shroud. This air cools
the deck components and exits through vents on each side of the
deck cover.

3-42

83323810 A

-----------~

SIDEVIEW

-...........-ABSOLUTE
FILTER

~.:...-+-t-t-

POWER SUPPLY
TO
EXHAUST
CHASS I S

Figure 3-24.

83323810 A

BLOW ER
MOTOR

INPUT TO
POWER SUPPLY
9WI70

Air Flow System

3-43

INTERFACE FUNCTIONS
GENERAL

All communications between drive and controller must pass
through the interface.
This communication includes all commands, status, control signals and read/write dasta transmitted
and received by the drive.
The interface consists of the I/O cables and the logic required
to carry and process the signals sent between dr ive and controller.
The following descr ibes both the I/O cables and I/O
signal processing.
I/O CABLES

All the signal lines between the dr ive and controller are contained in two flat ribbon type I/O cables.
They are r.eferred
to as the A and B cables.
The A cable contains lines connected in twisted pairs, which
carry commands and control information to the dr ive and status
information to the controller. This cable carries a maximum of
60 signals between drive and controller..
Figure 3-25 shows all lines in the A and B cables. The function of each of these lines is explained in tables 3-1 and 3-2.
I/O SIGNAL PROCESSING
I/O signals from the controller initiate and control all drive
operations. The I/O signals are sent to the receivers in the
dr i.ve and are routed from the receivers to the appropr iate
dri.ve logic.
The drive in turn sends information, concerning
the operation back to the controller via the transmitter~.
Figure 3-26 shows the basic logic involved in the routing of
I/O signals.

All commands are sent to the drive via the tag and bus bit
lines. These lines work in conjunction, the tag lines defining
the basic operation to be performed and the bus bit lines further defining the basic operation.
Table 3-1 explains the
function of all tag and bus lines.

3-44

83323810 A

I--

POWER SEQUENCE PICK
POWER SEQUENCE HOLD
TAG 1
TAG 2
TAG 3
BIT 0
BIT 1
BIT 2
BIT 3

0
N

T
R

BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
_ PLUG VAL 10
':SELECT ADDRESS 1
SELECT ADDRESS 2
-:SELECT ADDRESS 4
=SECTOR COUNT 1
=SECTOR COUNT 2
:SECTOR COUNT 4
-=SECTOR COUNT 8
~SECTOR COUNT 16
':INDEX
":SECTOR
FAUL T
=SEEK ERROR
":ON CYLINDER"
=UNIT READY
~WRITE PROTECTED

0
L
L
E

----

V
E

-----

-------

=
-

I--

A CABLE

9W85-1

Figure 3-25.

83323810 A

I/O Cables (Sheet 1 of 2)

3-45

CONTROLLER

....

GROUND
- SERVO CLOCK
+ SERVO CLOCK
GROUND
- READ DATA
+ READ DATA
GROUND
- READ CLOCK
+ READ CLOCK
GROUND
- WRITE CLOCK
+ WRI TE CLOCK
GROUND
- WR I TE DATA
+ WR I TE DATA
GROUND
- SECTOR 30+32
+ SECTOR 30+32
- START ENABLE
+ START ENAtiLE
GROUND
SPARE
SPARE
GROUND
+ INITIALIZE
- INITIALIZE

B CABLE

DRIVE

9W85-2

Figure 3-25.

3-46

I/O Cables (Sheet 2)

83323810 A

CJ)

w
W
N
W
CD

.--_.... wRlTE

PROTECTED

WRITE DATA

....o

--------,

r - - - - - - REA'Di;RITE- I

I
HEAD SE ECT TAG 2

I
I
I

RODATA
RO ClK

I
I

BIT 0

- - - _. ___ -

__ - - - -

- - -I

BUS

BITS

BIT I

0-2

BIT

MRS

WRTGATE

BIT

RO GATE

BIT4

OATA STROBE

AR Y

FUNCTION DATA STROBE lATE
DECOOE CLEAR FAULT

B1T~

SERVO OFFSET

BIT 6

BITT
BIT 8
BtT9

SEEK
CIRCUItS

CYLINDER SELECT TAG I

IIITIALIlE

9W86-1

Figure 3-26.

I/O Signal processing (Sheet 1 of 2)

...
I

+ ~2

r------.,
MACHINE CLOCK I

I
I

I
I
I

I
SERVO ClI<

FREQ
t-r----t
MULTIPLIER
I

.;;-~'E~9Jcc.._ _ _ _ _ _~.1 RCVA t-I------~II ... =~ CLK II:
••

MULTIPLIER

•

L ______ .J

9W86-2

Figure 3-26.

I/O Signal processing (Sheet 2)

TABLE 3-1.

CONTROLLER TO DRIVE SIGNAL LINE FUNCTIONS

Signal Line

Function

Power Sequence pick
(A Cable)

Used for power sequencing. A ground
on this line powers up drive if
LOCAL/REMOTE swi tch is in REMOTE and
START swi tch is on (refer to discussion on Power Sequencing).

Power Sequence Hold
(A Cable)

Used for power sequencing. This line
must be grounded at controller for
drive to complete and hold remote
power up sequence (refer to discuRsion
on Power Sequencing).

Cylinder Select Tag 1

Used in conjunction with Bus Bit lines
This tag
to initiate seek function.
strobes the cylinder address, contained in Bus Bit lines, into drive
logic. Drive must be on cylinder before this tag is sent. Bus Bits are
interpreted as follows:

(A Cable)

Bus Bit
0

1
2
3
4
5
6

8
9

Function
Cyl Adrs Bit 0
Cyl Adrs Bit 1
Cyl Adrs Bit 2
Cyl Adrs Bit 3
Cyl Adrs Bit 4
Cyl Adrs Bit 5
Cyl Adrs Bit 6
Cyl Adrs Bit 7
Cyl Adrs Bit 8
Cyl Adrs Bit 9

Table Continued on Next Page

83323810 A

3-49

TABLE 3-1.

CONTROLLER TO DRIVE SIGNAL LINE FUNCTIONS (Contd)

Signal Line

Function

Head Select Tag 2
(A Cable)

Used in conjunction with Bu£ Bit lines
to
initiate head select function.
This tag strobes the head address,
contained on Bus Bit lines, into drive
logic.
Bus Bits are interpreted as
follows:
Bus Bit
0

1
2

3
4

5-9
Control Sele~t Tag 3

Function
Head Adrs Bit 0
aead Adrs Bit 1
Head Adrs Bit 2
Head Adrs Bit 3
Head Adrs Bit 4
Not Used

Ini tiates var ious operations to be
performed by the dr ive. Used in conjunction with Bus Bit lines, which operation is ini tiated depends on content of these lines which are def ined
as follows:
Bus Bit

Function

Wr i te Ga te drivers.

Read Gate Enables the
digital read data lines.
Leading edge triggers read
chain to sync on all-zeros
pattern.

Enables wr i te

Table Continued on Next Page

3-50

83323810 A

TABLE 3-1.

CONTROLLER TO DRIVE SIGNAL LINE FUNCTIONS (Contd)

Signal Line

Function

Servo Offset
positive
Offsets the actuator from
the nominal on cylinder position toward the spindle.

Servo Offset
Negative
Offsets the actuator from
the nominal on cylinder posi tion away from the spindle.

Fault Clear - A 100 ns
(minimum)
pulse
sent
to
drive.
Clears the Fault
Latch if fault condi tion no
longer exists.

Not Used

RTZ Seek - A pulse (250 ns
to 1.0 ms wide) sent to
dr ive to cause actuator to
seek to track zero, clear
head address register, and
clear seek error latch.

Data Strobe Early - Enables
the PLO data separator to
strobe the data at a time
earlier than optimum.

Data Strobe Late - Enables
the PLO data separator to
strobe the data at a time
later than optimum.

Not Used

Bus Bits 0 - 9
(A Cable)

Used in conjunction with Tags 1, 2 and
3 to define ·commands to the drive.

Write Data
(B Cable)

Carries NRZ data to be recorded on
disk pack.
Table Continued on Next Page

83323810 A

3-51

TABLE 3-1.

CONTROLLER TO DRIVE SIGNAL LINE FUNCTIONS (Contd)

Signal Line

Function

Write Clock
(B Cable)

Synchronized to NRZ write Data, it is
a return of the Servo Clock.
This
signal is transmitted continuously.

Sector 30 + 32
(B Cable)

Used to determine the number of sectors per revolution.
When line is
high, there are 32 sectors per revolution. When line is low, there are 30
sectors per revolution (refer to track
orientation discussion).

Initialize
(B Cable)

Clears the Fault, Voltage Fault, and
Seek Error latches provided the errors
no longer exist.

UNIT SELECTION
Unlike drives that have common interface lines connecting them
to the controller, each BK7 drive has unique I/O lines connecting it to the controller. Therefore, the controller does not
select a particular drive before placing a command for it on
the I/O lines.
However, the controller must receive certain
signals from a drive before issuing a command to it. The sequence of these signals appears in the flowchart in figure
3-27. When the drive has completed its power on sequence and
has sent these signals to the controller, it will respond to
every command appearing on its I/O lines.

SEEK FUNCTIONS
GENERAL

The drive must move the heads to the desired position over the
disk pack before any read or write operation can be performed.
This is done during seek functions and is performed by the
drive's servo circuits.

3-52

83323810 A

TABLE 3-2.

DRIVE TO CONTROLLER SIGNAL LINE FUNCTION

Signal Line

Function

Plug Valid
(A Cable)

Used to indicate that a logic plug is
installed in the control panel.

Select Address 1,2,4
(A Cable)

Three lines which carry the binary
coded logical address of the drive.
The logical address is controlled by
the logical address plug installed in
the control panel.
There are eight
valid addresses (plugs 0 through 7).

Sector Count 1,2,4,
8, and 16
(A Cable)

Five lines which carry the binary
coded sector address. The output on
the lines represents the contents of
the Sector Address register. The sector count changes on the leading edge
of either Index Detection).

Index
(A Cable)

Occurs once per revolution of disk
pack and its leading edge is considered leading edge of sector zero (refe::-:t,o ,'discussion on Index Detection).

Sector
(A Cable)

Der~ived

from servo surface of disk
pack, this signal can occur ei ther 30
or 32 times per revolution of disk
pack. The number of sector pulses occuring depends on the condition of the
Sector 30 or 32 line from the controller.

Fault
(A Cable)

Indicates that one or more of the following faults exist~ write fault, multiple head select fault, write and
read fault, voltage fault, read or
write and not on cylinder.
~able

83323810 A

Continued on Next Page

3-53

TABLE 3-2.

DRIVE TO CONTROLLER SIGNAL LINE FUNCTION (Contd)

Signal Line

Function

Seek Error
(A Cable)

Indicates that the unit was unable to
complete a move within 500 ms, or that
carr iage has moved to a posi tion outside recording field. A seek error is
also generated if an address greater
than cylinder 822 has been selected.

On Cylinder
(A Cable)

Indicates drive has positioned the
heads over a track (refer to discussion on seek functions).

unit Ready
(A Cable)

Indicates that drive is selected,
disks are up to speed, heads are loaded, and no fault conditions exists.

Write Protected
(A Cable)

Indicates that drives write circuits
are .disabled. Write Protected is active under any of the following conditions:
head alignment is being performed,
a Fault condition exists,
WRITE PROTECT switch on control panel
is activated.

Servo Clock
(B Cable)

9.667 MHz clock signals derived from
servo track dlbits (refer to discussion on Machine Clock).

Read Data
(B Cable)

Carries NRZ data recovered from disk
pack (refer to discussions on Read/
Write functions).

Read Clock
(B Cable)

Clock signals derived from NRZ Read
Data (refer to discussions on Read
/Write functions).

Start Enable
(B Cable)

Reflects the condition of the START
switch.
When the switch is in the
start condition the line is active.

3-54

83323810 A

PRESS
START
SWITCH

""-

START

ENM~

LINE TO
CONTROLLER
GOES HIGH

POWER ON
SEQUENCE
TAKES PLACE

PLUG VALID
LfNE GOES
HIGH

FAULT
CONDITION
MUST BE
CLEARED

LOGICAL
.......... ADDRESS
GOES TO
CONTROLLER

HEADS
ARE
LOADED

DOES A YES
FAULT CONDITION
EXIST?

HEADS ARE
OVER SERVO
SURFACE

-...

UNIT READY LINE
CONTROLLER CAN
0 CON TR0 LLER t--~_ COM MAN 0 0RI VE
OES HIGH
OPERATIONS

I----~T

9W87

Figure 3-27.

83323810 A

Unit Selection Flowchart

3-55

The servo circui ts form a closed-loop servo system that controls movement by compar ing the present pos i tion of the heads
to the desired future position and generating a position control signal proportional to the difference between them.
The major elements in the servo loop are shown on figure 3-28.
The drive servo loop, the circuits it contains, and how it
works during seek functions, are described in the following
discussions. These discussions are organized as follows:
•

Overall LOOp Descr iption - Provides overall explanation
of servo loop and how it functions during various seeks.

•

Servo Disk Information - Descr ibes the information that
is permanently recorded on the servo surface of the disk
pack and used by the servo loop to control positioning.

•

Posi tion Feedback Generation - Explains how the servo
disk information is converted to feedback signals that
control positioning of the heads.

•

Veloci ty Feedback Generation - Explains how the speed of
the carriage is monitored and how this information generates signals to control the speed of the carriage.

•

position Signal Amplification - Explains how the position
signals from the posi tion control circui ts generate current for the voice coiL.

•

Direct Seek position Control - Explains how the positioning signals are generated and how the overall loop functions during direct seek sequences.

•

Load Seek Posi tion Control - Explains how the posi tioning
signals are generated and how the servo loop functions
dur ing load seeks.
These occur dur ing the power up sequence when the heads are loaded.

•

Return-to-Zero Seek position Control - Explains how the
posi tioning signals are generated and how the servo loop·
functions when the controller commands a return-to-zero
(RTZ) seek.

•

Unload Seek position Control - Explains how the positioning signals are generated and how the servo loop functions during power off sequences when the heads unload.

•

Seek End and Seek Error Detection - Describes the indications sent to the controller at the end of a seek and also describes the various seek errors detected by the
drive.

3-56

83323810 A

(J)

w
W
N
W

(J)

POSITION CONTROL CIRCUITS

I-'

LOAD HEADS
UNLOAD HEADS
FROM
PWR SYSTEM

F~ Jl

RTI

VELOCITY
,.----.,--------- ~!:;.O£I!~ FEEDBACK iot----,
I
I
CIRCUITS
I
I
r lnutcmn7'• II
:

I
UNLOAD
:
: COARSE
r
• POSITION :

-CONTfru... _J

CYL SEL

eYL ADRS

I
I
I

CONTROlLER

1
I

r-o~ttT--'

SEEK
:
: COARSE
L
I
POSITION :
I.. -t.O~IfQl.. - .J
I

I
I

I
I
I

,
•

I HEAD

' POSITIONING
I MECHANISM

r-C'

r j.____ J AR I

POSITION
SIGNAL
I-- r+:I VOICE
COIL ,
L _____
AMPllF IERS

I
I

;ERVO

I: HEAD,

L- - -

I
I
I

-f --- J

: SEEK END

r SEEK END
~

FINE
I
: POSITION :
: CONTROL :

I ( SERVO 1SK )

MAGNET L-E_ J

r~---+"---,
I

R I
A

: ON CYl

AND SEEK
ERROR
DETECTION

: SEEK ERROR~
I
I

I
I

,---------

REVERSE EOT PULS~/(FWD EOT·ODO 0IB1TS)

TO
CONTROLLER

TRACK
SERVO SIGNAL ,.-------,

t _____ .f!.!-lN~E! !l1!-~E.?

}

OIBITS

-----------..1
NOTES:
1. _
POSITION SIGNAL
- - - FEEDBACK SIGNAL
- - CONTROL S 1GNAL

NOT PART OF SERVO CIRCUITS.

9W88
Figure 3-28.

w
I

U1
....,J

Servo System Functional Block Diagram

OVERALL LOOP DESCRIPTION

The servo loop (refer to figure 3-28) consists of the position
control circuits, position signal amplifiers, head positioning
mechanism, and feedback circuits (both velocity and position).
The inputs to the loop are applied to the position control circui ts.
These inputs come ei ther from the controller (in. the
case of a direct or return-to-zero seek) or from the power system (in the case of a load or unload sequence). This is explained further in the discussions on position control.
The position control circuits are divided into three parts (1)
RTZ (return-to-zero)/load/unload coarse position control (2)
direct seek coarse position control and (3) fine position control. Which of these controls positioning depends on the type
of seek being performed and how close the heads are to the desi red posi tion.
The following explains the action of the position control circuits and the rest of the servo loop during a
typical seek operation.
At the start of a seek, the initial positioning information is
input to ei ther the RTZ/1oad or di ('eet seek coarse posi tion
control circuits (depending on the seek being performed).
These ci rcui ts then generate a control signal proportional to
the distance to the destination.
The signal polarity depends
on the direction of the seek.
The posi tion control signal is processed by the posi tion signal
am~lifier,
which uses it to generate current for the voice
cOll. The voice coil is attached to the carriage, which is the
d~~vice that supports and moves the heads.
The voice coil is
within a magnet and whenever a current passes through the coil
w:Lndings, the interaction between the induced EMF and the magnetic flux field causes the voice coil and carriage to move.
The acceleration of the motion is proportional to the polarity
and magni tude of the voice coil current (the head posi tioning
mechanism is discussed in detail in the discussions on Electromechanical Functions).
As the heads move, feedback signals are generated that indicate
how fast the heads are moving (velocity feedback) and how far
the heads have moved toward the desired destination (position
feedback).
The veloci ty information is der ived from the veloci ty transducer, which generates signals proportional to carr iage speed.
The position feedback signals are generated from information
read from the servo disk by the servo head.

3,-58

83323810 A

:Both velocity and position feedback signals are used by the
coarse posi tion feedback circui ts to vary the posi tion control
signal as the destination is approached. They are also used to
determine when the servo system should swi tch from coarse to
fine control .
When this switch is made, the coarse position control circuits
are disabled and the fine position circuits are enabled. Fine
control is necessary to ensure that the heads are accurately
positioned over the destination and also to keep it posi tioned
once the seek is complete. The fine position control circuits
also use signals f:rom the feedbacl< circuits to control positioning.
The seek-end and seek-error detec,tion circui ts sense when the
seek is complete and at this time :indicate if the seek was successful.
The preceding deo(:!ribed basic loop operation.
More detailed
descriptions of the elements in the loop and loop operation are
contained in the following discussions.
SERVO DISK INFORMATION
GENERAL

The servo disk sur face (refer to figure 3-29) contains servo
ositioning information that is recorded on the disk at the time
of manufacture.
This information is read by the servo head and processed by the
position feedback circuits.
These circuits generate .position
feedback signals that are used by the positioning circuits to
control the positioning of the heads.
The servo disk information also generates clock signals' used by the Index and Machine
clock circuits.
This discussion describes the servo disk information and is divided into the following areas:
•
•
•
•
•

Dibits
Dibit tracks
Outer and Inner Guard Bands
Servo Zones
Cylinder Concepts

83323810 A

3-59

/""'---SERVO OISK

9EI61A

Figure 3-29.

3-60

Servo Disk Format

83323810 A

Dibits

The servo posi tioning information is recorded on the disk as
specific patterns of flux reversals referred to as dibits.
There are two types of dibits: positive and negative.
The positive and negative dibits are classified according to
the type of wave"form produced when they are read by the servo
head (the waveform actually appears at the output of the track
servo preamp). The positive dibits produce a waveform with the
leading pulse positive and the trailing pulse negative.
The
n~gative dibits produce a waveform with the leading pulse negative and the trailing pulse positive.
The dibit patterns and
their associated waveforms are shown on figure 3-30.
Dibit Tracks

The dibits are recorded in track "patterns around the disk. The
servo surface has 833 dibit tracks, each recorded exclusively
"Nith either positive or negative dibits. These tracks are recorded adj acent to one another wi th no void area between them.
Those tracks containing only positive dibits are known as
positive-odd dibit tracks and those tracks containing only negative dibits are known as negative-even dibit tracks.
Outer and Inner Guard Bands

The outer 24 tracks are positive-odd dibit tracks and contain
only positive dibits. This ar.ea is known as either the ollteL"
guard band or the reverse end of travel (reverse EDT).
The inner 36 tracks
known as ei ther the
travel (forward EDT).

are negative-even dibit tracks and are
inner guard band or the forward end of

Both the outer and inner guard bcLnds are shown on figure 3-29.

83323810 A

3-61

W
I

POSITIVE

0\
N

~;IBITS~
~

rr-.-......---...'

DIB IT
INN SIS
NIN sis
NtN ijS
J
TRACK
PATTERNS [ t~~~~~.~N~~~~~:~~*~~~~~~-.~~~~~
I

\.--..-.J

¢:J

~!
\
/:
i ~NEGATIVE
:

DIS K
MOVEMENT
RELATIVE
TO HE AD

DIBITS

POSITIVE DIBITS
SIGNAL FROM
SERVO HEAD

NEGATIVE DIBITS
SIGNAL FROM
SERVO HEAD
*INTERVAL AT 3600 r/min DISK SPEtD
Figure 3-30.

positive and Negative Dibit Pattern

9W89

Servo Zones

In between the inner and outer guard bands is an area called
the servo zone. The servo zone consists of alternately spaced
positive-odd and negative-even dibit tracks. Because the dibit
tracks are adj acent to one another, junctions are formed between the posl ti ve and negati ve tracks.
These junctions are
referred to as servo tracks. The servo zone contains 823 servo
tr.acks, numbered from 000 to 822.
When the servo head is centered over a servo track, it will alternately detect both positive and negative dibits. The combination of these signals results in each servo track being divided into exactly 13 440 intervals (where an interval is the
time between the leading peaks of successive dibits).
In addition to this, each dibit track in the servo zone is encoded with a pattern of missing dibits and this results in each
servo track also containing a pattern. This pattern, referred
to as Index, is the same on each servo track and is recorded at
a specific circumferential location on the tracks.
Further information about Index and its application is given in
the discussions on Track Orientation.
Cylinder Concept

The data recording zones on the data surfaces are aligned vertically with the servo track zone on the servo sur·face. For
this reason, all head movement and positioning is referenced to
the position of the servo head over the servo surface.
Therefore, when the servo head is positioned over a specific
servo track on the servo.surface, all other heads are positioned over the corresponding data tracks on their respective data
surfaces. For example, if the servo head is over track 10, all
other heads are also over track 10. The vertical alignment of
these tracks create an imaginary cylinder as shown on figure
3-31.

83323810 A

3-63

/CYLINDER 10

HEADS

"."..-- -

..... ,

TRACK 10

~ ..... -----~

A
DATA ~
SURFACE

C
A
R
R
I
A

SERVO
SURFACE

DATA
SURFACE

E
I

, _---_

r.....
NOTE:

,.
I

-----, '"

NOT ALL HEADS AND
it SURFACES
ARE SHOWN.
9W90

Figure 3-31.

Cylinder Concept

POSITION FEEDBACK GENERATION
General

All position feedback information is generated by the position
feedback circuits. These circuits use the dibit data read from
the servo disk to generate the feedback signals required by the
position control circuits.
The feedback signals generated and their basic functions are as
follows:
'.

Track Servo signal - Used by the fine position control
circuits to control positioner movement during the last
half track of a seek.

3-64

83323810 A

•

Cylinder Pulses - PuJ.ses that occur each time the servo
head crosses a servo track. These pulses are used by the
coarse position control to determine the distance to the
desired cylinder.

•

Reverse EO'!,' Pulse - Provides feedback to the RTZ coarse
posi tion control circui ts dur ing a return to zero seek
(RTZS).

•

Forward EOT Enable and Odd Dibi ts - Provides feed back
during RTZ, Load, and Unload seeks that cause positioning
control to be swi tched from the RTZ, Load, and Unload
coarse position control circuits to the fine position
control circuits.

In addition to providing these signals, the position control
feedback circuits also produce the Odd/Even dibit signals used
by the Machine Clock and Index Detection circuits.
A basic block diagram of the position feedback circuits is
shown on figure 3-32 and each of the following elements are explained in the following discussions:
•
•
•
•
•
•
•

Track Servo Preamp
Dibit Sensing
Automatic Gain Control (AGC)
Track Servo Signal Amplifier
Odd/Even Dibit Clock Generation
Cylinder Crossing Detection
End of Travel Detection

Track Servo Prea mp

This signal from the servo head must be processed by the track
servo preamplifier before the servo track information can be
used by the rest of the position feedbaCk circuits.
The signal received from the servo head depends on the type of
servo dibi t track it is reading. When the head is over the
outer or inner guard bands, it reads from tracks that have
either all positive or all negative dibits. In this case, the
preamp produces either all positive or all negative dibit waveforms (refer to figure 3-30).

83323810 A

3-65

C
,....-_---1 A
R t-------,
~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~ VOICE

r SERVO HEAD

POS tTlON
.....-------IIIISIGNAL
rMPllFIER

COIL
A
'------4 G
E

fiNE
POSITION
CONTROL

I
I

POSITION FEEDBACK CIRCUITS
r. - :- - - - - TRACK
- - - -:;- AGC' ED - - - - - - - - ~
I

'I ---------------------------i-I

....

TRACK SERVO SIGNAL

I CYL
10",S Cll
I L~;Sl! .J1... DETECT
I

I
I
I
I

•

I
'(012)
I

(072)

DETECT cn
~_J
A
CROSSING. I
DETECTOR:

(I8S)

DIBITS

AGC
+OlBITS
(182.
184) - 0 IBtT S

SERVO

-'GC'EO
i~~~~~ I ER DI8ITS
183 185

TRACK
I
SERVO
.!!LB1~"
PREAMP ~
(763 )

I
I

DETECT cn
I
SENS ING
B
CROSSING
,
DIBITS
OlBlTS
~~ ~~~ TOR ~~...._-J+----t-----+-+..::..:.~:--:....---1

i
:

n:H

L _________________ •
•
REV EOT PULSE

L-----r ------------------ ~:~V~~
000 OIBITS·FWO EOT ENA8LE

VELOCITY
A
EVEN 018ITS

OIBIT
RD GATES

ODD/EVEN
018ITS
CtOt~

(EOT)

'- - - - -----i- - ---- ---- - - - - - - - _. DE TEC TION ,.....0;;0.;0__0---..;01; . ,;:;8;. :,I. .;. T,:;. S- - - - - i - - . . - - f (184)

L ___________________
INDEX
DETECTION
MACHINE
CLOCK

Figure 3-32.

ODD + EVEN
018 ITS

_______

~_-_~

NOTES:
-POSITION SIGNAL
1. ___ FEEDBACK SIGNAL
--CONTROL SIGNAL

Position Feedback Circuits.

9W91

When the head is over the servo zone, it passes over both types
of dibi t tracks and the preamp :produces a waveform that is a
mixture of both types of dibit signals.
The ampli tude of each dibi t component in the waveform is proportional to how much the servo head is overlapping the
tracks.
If the head is centered over a servo track the signal
has equal positive and negative dibit components.
However,
when the head is away from the centerline, the amplitude of one
dlbi t component is greater than the other (this is shown on
figure 3-33).
I f the servo head is mov ing through the servo zone, each component alternately increases and decreases as the servo tracks
are passed. This is also shown on figure 3-33.
The output of the track servo preamp is sent to the AGe and
dibits detect circuit.
Dibit Sensing

'l·he dibi ts sense circui t (refer to figure 3-32) detects the
presence of dibi its data. The output from this circui t is the
Dibits Sense signal and it must. be active (indicating dibits
are present) for the posi tion feedback circlJi ts to function.
This prevents them from generating false signals when no dibits
are present (as for example, during a heads load or when heads
are unloaded).
The Dibits Sense signal is first enabled during the heads load
sequence when the heads loaded swi tch transfers.
The signal
goes acti ve when dibi ts wi th an ampli tude of at least 145 mv
peak to peak have been present for 3 ms. If the Dibits Signal
should drop below this level for more than 50 ~s, the Dibi ts
Sense signal goes inactive thus disabling the cylinder crossing, odd/even dibits clock and t.rack servo amplifier circuits.
Therefore, losing dibits results in totally disabling the position feedback circuits.
Automatic Gain Contlrol (AGC)

The purpose of the AGe circuits (refer to figure 3-32) is. to
provide gain control for the Clibi ts signals before applYlng
them to the track servo amplif ier and odd/even dibi ts clock
circuits. This gain control is necessary for proper servo system operation.
The outputs from the AGe circuits are the
AGC'ed Servo signals.

83323810 A

3-67

w
!

PATH OF SERVO HEAD
ACROSS DIBIT TRACKS

0'\
Q)

. . MOTION OF DISK

TRAC~~~~~~~~~~~~~~~~~~~~~~~~~~

-EVEN TRACK
+000
+000 TRACK

... MOTION
OF HEAD

DETECTED
DIBIT
SIGNALS
SERVO
HEAD
CENTERED
OVER
+ DIBIT
TRACK

SERVO
HEAD
CROSSING
OVER
SERVO
TRACK

SERVO
SERVO
HEAD
HEAD
CROSSCENING
TERED
OVER
OVER
- DIBIT SERVO
TRACK
TRACK

SERVO
HEAD
CENTERED
OVER
+ DIBIT
TRACK

SERVO
HEAD
CENTERED
OVER
SERVO
TRACK
9W92

Figure 3-33.

Servo Preamp Output

Gain control is obtained by feeding back a signal from the
track servo circuit to the ~C circuits. This feedback signal,
referred to as AGe, is derived from the AGC'ed Servo signals
and the amplitude of the AGC and AGC'ed Servo signals are directly proportional. Therefore, when the AGC' ed Servo signals
increase it ca~ses an increase in the AGC signal and vice versa.
When the AGe signal increases~ it causes a decrease iri the gain
of the AGe circuits. This results in reducing the amplitude of
the AGC'ed Servo signal.
the AGe signal decreases, the gain of the AGC circui ts increases and the AGe'ed Servo signal becomes larger.

\~hen

The net result is that the output amplitude of the AGe Circuit
remains constant.
Track Servo Signal

The track servo amplifier circuits (refer to figure 3-34) use
tho AGe'ed Servo signal from the AGC circuit and the oibit read
gate signals from the odd/even dibi t clock circui ts to produce
a signal that varies as the position of the servo head changes
with respect to the dibit track£;. This signal is referred to
as the Track Servo signal.
The main elements in the track servo circuits are the peak detectors, peak detector buffers, AGe control amplifier and differential amplifier (refer to figure 3-34).
The peak detectors moni tor the AGe' ed oibi ts signals and are
enabled by the positive-Odd and Negative-Even Dibit Read Gate
signals.
The positive peak detector is enabled by ihe positive-Odd oihit
Read Gate signal and is active during the positive portioll of
the positive-odd dibit cycle. The negative peak detector is
enabled by the Negative-Even Dibit Read Gate signal and is active during the negative portion of the negative-even dibit
cycle. The peak detectors are inactive at all other times.
This results in peak detector outputs that are proportional to
the amplitude of the dibit signals they are monitoring. Therefore, the posi tlve peak detectc)r output is maximum when the
servo head is over a posi tive-odd dibi t track and the negative
peak detector output is maximum when the head is over a
negative-odd dibit track (refer to figure 3-34).

83323810 A

3-69

+000 0181T RO GATE

AGC ED D18 ITS
I

POSITIVE
PEAK
DETECTOR

-EYE" OIIIT RD GATE

VE
--!!.GC ED DUITS "EGAlI
PEAK
DETECTOR
I

I IUFFER I+PEAKS
~I
I

DIFFERENT tAL
AMPLIFIER

AGC
CONTROL
AMPL IF 1ER
8UFFER

I ·PEAKS
I

PATH OF SERVO HEAD
ACROSS DIBIT TRACKS
-EVEN TRACK
+000
+000 TRACK
TRACK

...

TRACK
SERVO
SIGNAL
AGC

t
"MOTION OF DISK

~~~~~~~~~~~~~~~~~~~
MOTION
OF HEAD

DETECTED
DIBIT
SIGNALS
POSITIVE
PEAK DETECTOR---------------------------------OUTPUT
NEGATIVE
PEAK DETECTOR--------------~------------------------
OUTPUT
TRACK
SERVO
SIGNAL
NOTES:
~ MOTION OF HEAD EXAGGERATED.
~
ALL WAVEFORMS IDEALIZED FOR
PURPOSES OF ILLUSTRATION.
Figure 3-34.

3-70

9W93

Track Servo Amplifier Circuit and Signals

83323810 A

The outputs of tbe peak detectors are processed by tne peaK a~
tector buffers to provide signals of the proper' amp1i tude and
polarity for the AGe and differential amplifiers.
The AGC control amplifier uses the buffer outputs to generate
the AGe voltage that is used by the AGC circuits.
The differential amplifier uses t:he two buffer outputs to produce a voltage with a polarity and magnitude directly proportional to the difference between them. This is the Track Servo
signal.
The Track Servo signal is at its maximum pos i ti ve value when
the servo head is over negative-even dibit tracks and maximum
negative when the servo head is over positive-odd dibit tracks.
If the servo head is centered over a servo track (between
positive-odd and negative-even dibit tracks) the signal is
zero. Therefore when the servo head moves through the servo
zone, the Track Servo signal passes through zero each time the
head crosses a servo track (refer to figure 3-34).
The Track Servo signal is applied to the Fine position control
and Cylinder crossing detection circuits.
The Fine Posi tion
control circui ts use the signal to generate the posi tioning
signal that controls movement during the last one half track of
a seek (and during forward EOT.conditions). The Cylinder crossing detect circuits use the signal to generate cylinder pulses
as each servo track is crossed.
Odd/Even Dibits Clock Generation

The odd/even dibits clock circuits (refer to figure 3-35) generate the Odd Dibits, Even Dibits and also the Odd and Even Dibi ts Read Clock signals. These signals are der ived from the
AGC'ed Dibits signals that are applied to the level detectors.
The level detectors create digi tal pulses from the AGe' ed Dibits signals by switching to their low state whenever they
sense their respective dibit signals. The level detectors are
enabled by the Sensing Dibi ts signal that is active only when
dibits are being read from the disk.
The outputs from the level detec:tors produce both the Dibi ts
Read gate and Odd/Even dibits signals.

83323810 A

3-71

EVEN DISIT RO GATE

POSITIVE

+ AGC'ED DlBITS PEAK

LEVEL
DETECTOR

ODD
OIBlTS
S

D18IT
... EVEN
RD GATE
~HOT

+ 5- J

890 ns

ONE

FF
ODD D181TS

SEMSING DlBITS

- AGC'ED DIBlTS

NEGATIVE
PEAK
LEVEL
DETECTOR

....

ODD DIBlT
RD GATE
ONE SHOT

890 ns

EVEN
DIBlTS
S
~

+ 5- J

...

ODD

+ EVEN
D18lTS

FF
EVEN DIBITS
ODD DIBIT RO GATE

OIBITS

POSITIVE PEAK
LEVEL DETECTOR

EVEN OIBIT
RO GATE
000 DIBIT
READ GATE
EVEN OIBITS
ODD DIBITS
EVEN + ODD
01BITS
NOTES:

RETRIGGERS ONE SHOT
TIME = 890 ns

Figure 3-35.

3-72

9W94

Odd/Even Dibit Clock - Logic and Timing

83323810 A

The Odd and Even Dibi ts Read Gate signals are generated when
their respective one shots are triggered by the negative going
edge of the level detector outputs. The dlbl t read gate signals enable the track servo amplifier circuits.
The Odd Dibi ts and Even Dibi ts edgna1s are produced by the outputs of the level detectors working in conjunction wi th the
output of the dibits read "gate one-shots. The logic and timing
for this is shown on figure 3-35.
The 'Odd Dibits and Even Dibits signals have a nominal frequency
of 403 kHz. However, because they are in turn derived from dibits that are derived from the rotating disk, this frequency
will vary with disk speed.
The Odd or Even Dibits signal is generated by ORing the Odd Oibi ts and Even D:ibi ts signals. This produces an 806 kHz (nominal) signal that also varies with disk speed.
The Odd Dibits, Even Dibits and Odd or Even Dibits signals are
used by the machine clock, index detection and End of Travel
Detection circui ts (refer to discussion on these circui ts for
more information).
Cylinder Crossing Detection

The cylinder crossing detection circuits (refer to figure 1-15)
use the Track Servo signal to generate a pulse as each servo
track is crossed.
When the servo head crosses a servo track, the heads are crossing a cylinder (refer to discussion on Cylinder Concept);
therefore, these pulses are called Cylinder Pulses.
The cylinder crossings are detected by cylinder crossing detectors A and B. Cylinder crossing detector A produces an output
pulse from the time the Track Servo signal goes through zero in
a positive direction until it goes through -0.4 V in a negative
direction.
Cylinder crossing detector B produces an output
pulse from the time the Track Servo signal goes through zero in
a negative direction until it goes through +0.4 V in a positive
direction.
This results in an overlapping of the two pulses after each
zero crossing (refer to figure 3-36) and combining them produces a pulse to trigger the 40 microsecond 10 microsecond Cylinder Pulse one shot.

83323810 A

3-73

The 10 microsecond Cylinder pulses from the one shc)t are used
by the direct seek coarse control circui ts to count the number
of cylinders crossed during a seek. They are also used by the
End of Travel Detection circuits. Refer to the discussions on
these circuits for further descriptions of how they are used.
It should be noted that the cylinder crossing detection circui ts are operative only when the heads are loaded and dibi ts
are being read from the disk. At all other times, the Sensing
Dibits signal is inactive thus disabling the cylinder crossing
detectors. This prevents false Cylinder Pulses from being generated.
End of Travel Detection

The end of travel (EOT) detection logic (refer to figure 3-37)
senses when the heads are outside of the data area and over one
of the guard bands. Depending on the type of seek being performed, the output from this circuit will be interpreted as
either an error indication or a feedback signal.
If the drive is performing a direct seek to one of the tracks
in the data area, an EOT is interpreted as a positioning error
and the proper error sequence is initiated. However if an RTZ
OI' Load seek is being performed, the EOT signals are used as
fE~edback for the RTZ/Load coarse posi tion control ci rcui ts.
The main elements in the EOT detection circuits are the EOT IntE~grator, EOT detectors and the Forward and Reverse EOT FFs.
The EOT Velocity Integrator works similarly to the Desired Veloci ty Integrator in the direct seek coarse position control
circuits. It monitors the Velocity signal and generates a sawt()oth output waveform that rises from zero until reset by either a Cylinder pulse (when moving through data area) or by the
Reverse EOT Pulse (during an RTZ when it detects the reverse
EOT). If neither of these are present (as when moving over the
outer or inner guard band), the output continues to rise.
The output from the EOT Velocity Integrator is monitored by the
Forward and Reverse EOT detectors. The Forward EOT Detector is
enabled whenever the integrator output exceeds +1.35 volts.
This occurs either duri~g a load when the heads are moving forward through the inner guard band or whenever the heads move
into the outer guard band. In both of these cases the Velocity
signal is of the proper polar i ty, and there are no pulses to
reset the integrator.

3-74

83323810 A

TRACK

~i~~RL':iiV\WJ\J\J~
, I

-f:

~I,-I_

B.f1

CYL DETECT A "

CYL DETECT
,
DE
T
E
C
TED
JI
CYL
CYL PULSES

.....

L--.J
L--.J

1,------,

L
L

JL---"_-.6n. . .__n,____n,---,nL--_fL

--J l- lO~sec

Figure 3-36.

9W95

Cylinder Crossing Detection

The Reverse EOT Detector is enabled whenever the Integrator
output is more negative than -1.35 volts. This occurs when the
heads are moving in reverse over the outer guard band.
The Forward and Reverse EOT Enables are applied to the Forward
and Reverse EOT FFs.
The conditions causing these FFs to set
and clear are shown on figure 3-37
VELOCITY FEEDBACK GENERATION

The ve10ci ty of the carr iage Jnust be controlled to have the
shortest seek time without having the heads overshooting or oscillating around the desired cylinder.
The signal to provide
this control is generated by the velocity feedback circuits
(refer to figure 3-38).
The veloci ty of the carr iage is sensed by the veloci ty transducer.
Tnis is mounted within the magnet and consists of a
stationary coil and movable magnetic core (refer to figure
3-38).

83323810 A

3-75

ODD DIBITS

ENABLED: DURING REV EDT
OR RTl WHEK REV EDT
DETECTED ALSO ENABLED
BY CYl PUlSES WHEN
I-CLAMP ENABLED INTEGRATOR
OUTPUT IS RESET TO lERO

CLAMP

EDT
VELoe ITY
INTEGRATOR

VELOCITY

:+1. 35

FWD~
: :

REV

r0-

(192 )

WHEN FWD
EDT DETECTED

FWD EDT
S

FWD

EDT

LATCH

CLAMP '-1.35
ENABLED

f--

t--

R
WHEN ODD DIBITS
f-- DETECTED FOLLOWING FWD EDT

(063)

III
(192)

REV EDT
DETECTOR

FWD EDT ENABLE

FW:l EDT
DETECTOR
REV EOT
ENABLE

I FWD EDT ENABLE
I INS LOAD SEEK

EI)T DETECTED

EVEN DIBITS
;..;..;:;-------------------+-.....,j WHEN
ARE DETECTED FOL-

ODD DIBITS

•

(063)

'--1 GOES ACTIVE OUR- t ? J - R E V EDT
~ REV

(192 )

FWD EOT ENABLE

S
LATCH

REV EDT

R
(063)

N DIBITS

EVE
~~~~.
NOTES:

1--_....1

LOWING REV EDT
PULSES ARE ALSO THIS POLARITY WHEN CARRIAGE MOVES
&
FORWARD THROUGH REVERSE EOT AS DURING A LOAD,
'--------------------../
DETECTORS ENABLED WHENEVER DISK IS UP TO SPEED

40"S REV EDT
J'L PULSE

(064)

EXCEPT DURING HEADS UNLOAD.

9W96

Figure 3-37.
(X)

W
N
W

(X)
~

End of Travel Detection Circuits

VELOCITY FEEDBACK CIRCUITS

r----------.,

VELOCITY I
: VELOCITY
:
... ---\ AMPLIFIER :.-- ... TRANSDUCER ... ·~- ..
II
1(202)
:(792)
II
L _________ :
J:
I

'-_. _ _ _ _ _ _ _ _

I
I
I
I

I
I
I

I
I

POSITION
CONTROL
CIRCUITS

POSITION
~--.c VOICE
t--.---~ SIGNAL
COIL
AMPLIFI[RS

A
R~~~--,

R
I

SERVO
HEAD

A
G

NOTES:
1

POSITION SIGNAL
- - - FEEDBACK SIGNAL
9W97

Figure 3-38.

83323810 A

Velocity Feedback Circuits

3-77

When the carriage moves, the core moves thus inducing an EMF in
the coil. This EMF is converted by the velocity amplifier into
the velocity signal.
The ampli tude of this signal var ies wi th the speed of the carr iage and the polar i ty depends on the di rection of movement.
If the seek is in a forward direction, the polarity is n~ga
tive, and if it is in a reverse direction, the polarity is positive.
Refer to the discussion on Electromechanical Functions for further description of the velocity transducer.
POSITION SIGNAL AMPLIFICATION

The signals from the position control circuits are processed by
the position amplifier circuits (refer to figure 3-39) to provide the current for the voice coil.
Anyone of the three position signals may provide the input to
thE~se circuits depending on the type of seek being performed
and how close the heads are to the destination.
This input
signal is applied to the summing amplifier.
ThE~

output fron, the summing amplifier is then applied to the
power amplifier driver, which uses it to generate the Forward
and Reverse Current signals.
These signals are sent to the
power amplifier.
ThE~

power amplifier uses the Forward and Reverse Current signals to produce a voice coil cur rent wi th the proper polar i ty
and amplitude to move the voice coil and carriage thereby positic)ning the heads.
DIRECT SEEK POSITION CONTROL
General

A direct seek is one in which the drive is commanded by the
controller to move the heads from their current logical cylinder location to another, specified by the controller. ~he controller initiates the direct seek via Cylinder Select Tag 1 and
Bus Bits 0-9.
The direct seek . function is divided into two modes:
(1) coarse
and (2) fine.
The coarse mode consists of all but the last
half track of the seek. The servo system is in fine mode durin~~ the last half track and while the heads are tracking over
the desired cylinder.

3-'78

83323810 A

r --------------------I

POSITION CONTROL CIRCUITS

r--------------------,
: RTZ/lOAD/UNlOAD COARSE:

r - - - POSITION SIGNAL AMPLIFIERS -

~--------------------j

~--------------------,

: DIRECT SEEK COARSE

SUMMING
t-+--w-~ AMPL I FI ER

(204)

~--------------------~
~--------------------~

FINE

POSITION

~--------------------~

VELOCITY
FEEDBACK 14--------------,
CIRCUITS

POWER
AMPLIFIER
DRIVER

POWER

--,

I
c
1'------1 :

AMPLIFIERJ-+o~VOICE

(832)

204)

L ______________

I
~

COIL

1-------.

SERVO
HEAD

:
I

L~~~~~====== _____

___

NOTES:
_
POSITION SIGNAL
1 - - - FEEDBACK SIGNAL

Figure 3-39.

J~~~~~!~~ l-----------------____J
I CIRCUITS I

Position Signal Amplifier Circuits

9W98

The following discussions describe both the coarse and fine
modes.
Figure 3-40 is a flow chart of the entire direct seek
function.
Dir'ect Seek Coarse Control

General
The direct Sf ~ek is controlled by the direct seek coarse control
cir'':lJits for all but the last half track of the seek.
Figure
3-41 shows these circuits and the signals they generate.
The three main inputs to these circuits are the address of the
destination cylinder (received from the controller in conjunction with the cylinder address tag), the Cylinder pulses (received from the position feedback circuits), and the Velocity
signal (received from the velocity feedback circuits).
These
signals are used to produce a coarse positioning signal that
varies with distance and also controls the speed of the carriage as it moves toward the destination.
How the coarse positioning signal is generated and also how the
loop operates under coarse control is explained in the following paragraphs.
Coarse position Signal Generation
At the start of the seek, the distance to the destination cylinder is determined by the adder.
It does this by compar ing
the address sent by the controller with the address presently
contained in the cylinder address register (this is the address
at which the heads are presently located) and then generating a
di.fference count indicating how many logical cylinders the
heads will have to cross in reaching the new address.
The difference count is loaded into the Difference counter.
After the difference counter is loaded, the new address (received from the controller) is loaded into the Cylinder Address
register and will be the present address at the start of the
next seek.
The Difference counter is decremented by the cylinder pulses as
each logical cylinder is crossed thus keeping track of the number of logical cylinders left in the seek.
The seven lower order bits of the Difference counter go to the
O/A converter, as shown in figure 3-41.

3'·80

83323810 A

(X)

ADDER COMPARES
OLD ADRS (CONTAINED If~ CAR)
YITH NEW ADRS TO
DETERMINE SEEK
LENGTH & DIR •

N
W
(X)

....
o

CLR DIR rr AND
GA TE 01 A CONVERTER OUTPUT TO
DESIRED VEL FCTfI
GEt! VIA FWD GATE

POLARITY OF POSITION SIGNAL
WILL CAUSE CARRIAGE TO MOVE
FORWARD

(20J)

SET DIR FF AND
GATE D/A CONL...._ _ _ _

GEt! VIA REV GATE
(203)

'fOTES:
••

NU~BERS (
) REFER TO
REF[R[r4(E tWMBERS.

~ ~gJ~~o O~irU~c~?

POLARITY OF POSITION SIGNAL
Will CAUSE CA RRIAGE TO MOVE
REVERSE

OIAr.RA~'

COARSE POSIT 1011
SIGNAL (COIISISTINr, OF D/A CONVE RTE R OUTPUT)
GATED TO POSITION
SIGNAL AMPLIFIERS
SIIEn 3

Figure 3-40.

w
I

(X)

....

Direct Seek Flow Chart (Sheet 1 of 3)

SHEET
9\199-1

w
I

co
flo)

"'>--..:.____1.._ _ _ _

COARSE POSITION
SIGNAL IS SMOOTH
CURVE WI TH AMPTD
PROPORTIONAL
DISTANCE 10 'i0

D
AND THEREFORE
DES VEl AIID
1-----~COARSE POSITION
SIGNALS ARE MAX

VEl SI GNAL
PRODUCED THAT
OPPOSES D[S VEl

(204)

CARRIAGE

cn PULSES
GENERATED AS
EACH cn IS
CROSSED

CARRIAGE
DECELERATES

ACCElERATES

CARRIAGE
COASTS

cn PULSE SETS
YES
_____

_____

VEL INTGRTR TO
~ZERO

(203

VALUE IN DIH
CNTR DECREASE'1-_ _ _~
BY 1 BY EACH
cn PUlSE(124)

INTGRTR
OUTPUT STARTS
I KREA S IIIG
AFTER
PULSE
DROPS (203)

OUTPUT OF D/A
CONVERTER STEPS

t----Jt~~NW~~~ :~T~~~ii
OUTPUT
(203)

SHEET 3

9W99-2

Figure 3-40.

Direct Seek Flow Chart (Sheet 2)

FINE POSITIon SIGNAL IS FINE POSITION ANALOG COM81NED WITH VELOCITY AND DECREASES
AS DESTINATION IS
APPROACHED

FINE LATCH SETS
I NO I CA Tl NG I /2
.,...---,,,, cn TO DESTINATION

(072)

HEADS MOVE TOWARDS DESTINATION UNDER CONTROL OF FINE POSITION SIGNAL

DISABLE COARSE
GATE AND ENABLE
FINE GATE

(204 )

INDICATES HEADS
ALMOST ON cn
AND TRIGGERS
1.75 ms ON CLY
DElAY

PRODUCES FINE
POS IT I ON S I GlfAL
POLARITY
OPPOSITE THAT
Of V[lOCtTY

t---~ WITH

&'
START SOD 115
TIME OUT DElAY

(073)

IF' SEEK I S NOT
CO"PLETE. W!THIN 500 1115. A
SEEK ERROR IS
INDICATED.

NOTES:

REFER TO DISCUSSION ON SEEK END AltO
S£EK ERROR DETECTION.

910/99-3

Figure 3-40.

w
I

Direct Seek Flow Chart (Shee~ 3)

.
w
I

Q,')

NOTES:

1. OTHER NUMBERS (XXX) REFER 10
DIAGRAM REF NUM6ERS.
POS IT ION SIGNAL
FEEDBACK SIGNAL
- - CONTROL SIGNAL
I
~-----~--~------

,
,
I

I
I
I

FWD + REY

:r ________

~ll~!~~

____ _

_ _______

~_~

____________

~~!~

______________________ J
9WlOO

Q,')

w
W
N
W
Q,')

Figure 3-41.

Direct Seek Coarse position Control Circuits

The output of the D/A converter is determined by the value of
the input bi ts from the Difference counter.
When these bi ts
are all active, the D/A converter output is maximum. This is
the case where the number of logical cylinders to go exceeds
128. However, when logical cylindefs to go are less than 128,
the D/A Converter output steps down (wi th the counter output)
as each logical cylinder is crossed.
The D/A Converter output signal is gated via either the Forward
or Reverse 9~te to the Desired Velocity Function Generator.
The output of the Desired Velocity Function Generator (Desired
Ve10ci ty) var ies in ampli tude wi th the D/A Converter output
(and therefore with distance to t.he destination) and in polarity depends upon the direction of the seek.
The seek direction is determined at the start of the seek by
the adder, which generates the Forward or Reverse signal. This
signal ei ther sets or clears the Direction FF and thereby enables either the Forward or Reverse Gate.
If the seek is in a forward direction (toward the spindle), the
Direction FF is cleared thus enabling the Forward gate.
This
causes a Desired Velocity signal that varies from a negative
voltage to zero.
If the seek is in a reverse direction (away from the spindle),
the Direction FF is set thus enabling the Reverse gate.
In
this case, the Desired Velocity signal varies from a positive
voltage to zero.
In either case, the output from the D/A Converter must be
smoothed out during the last 128 logical cylinders of a seek to
prevent steps from appear ing in the Desired Velocity output.
This function is performed by the Velocity Integrator.
The Velocity Integrator is enabled when logical cylinders to go
reaches 128 and at this point starts generating sawtooth pulses.
These pulses start from zero at the time the Cylinder
pulse goes false (which occurs after the cylinder crossing) and
rise until by the next cylinder pulse (which occurs at the next
cylinder crossing).
When the sawtooth pulses are summed with the D/A Converter output, the resul ting Desi red Veloci ty signal is a smooth curve
that decreases in ampli tude wi th distance to the destination
cylinder.
The Des ired Veloc i ty s igna1 is 'then summed with the Veloc i ty
signal recei ved from the ve10ci ty feedback circui ts. The Velocity signal varies in amplitude with carriage speed and is opposite in polarity to the Desired Velocity signal.
It is necessary to sum Desired Veloci ty wi th Veloci ty in order to control carr iage speed thus ensur ing minimum seek time wi thout
overshooting the destination cylinder.
83323810 A

3-85

The resultant signal, Desired Velocity summed with Velocity, is
the final output of the coarse position circuits and is applied
to the position signal amplifiers via the coarse gate.
Loop Operation During Coarse Control
The posi tion signal amplifiers use the output from the coarse
position amplifier circuits to produce current for the voice
coil. This current controls carriage motion.
The Coarse control portion of a typical direct seek can be divided into three phases:
•

Accelerate Phase - Voice coil receives maximum current
and carriage accelerates from zero to maximum velocity.

•

Coast Phase - Carr iage is at maximum veloci ty and coasts
along under its own inertia.

•

Deceleration Phase - Carriage approaches destination and
must slow down to avoid overshoot.

It should be noted that it takes about 60 cylinders for the
carriage to reach maximum velocity (about 55 in/s).
During
shorter seeks, particularly those less than 128 logical cylinders, maximum velocity will not be obtained.
In cases where
maximum veloci ty is not reached, the pr imary functions remain
the same but the coast phase will not occur (or be very short),
and the carriage begins to decelerate sooner.
The following descr ibes how the servo loop operates dur ing a
typical direct seek 10n'g enough for the drive to obtain maximum
velocity. The signals generated are shown in figure 3-42.
The acceleration phase occurs during the first part of the
seek. At this time, the carriage is stationary and the output
from the coarse gate is due entirely to the Desired Velocity
signal with no opposing Velocity signal. Therefore, voice coil
cur rent is maximum in the direction necessary to cause maximum
carriage acceleration.
As the carriage accelerates, a Velocity signal is generated by
t:he veloci ty feedback circui ts.
Because this signal opposes
the Desired Velocity signal, the resultant signal to the position signal amplifiers is reduced thereby reducing voice coil
current. However, Desired Velocity signal is still greater and
the carriage continues to accelerate.

3-86

83323810 A

TRACKS TO GO

T = 300

VELOCITY
TRANSDUCER

DIA CONVERTER +
INTEGRATED
VELOCITY

--I~I--O
..........,.....

V·-----r-----i'~

o V--~-----ILIWY1VVV'l1~W
+ V · - - - t - - - -.......
I

I
I

f--J

I
I

~OV
I

Th-

'::OV
3 I

I
I

+ V---

ACCELERATE

~~~~lL T~M~~ig~~~ P

+--

I
I

DECELERATE
-

-~OV

DESIRED VELOCITY :

- V

'. --7-----

-~:--~I
0 V
,4
I

J_ - - - - - - - -

FINE POSITION ~ _______________________ ~
SIGNAL

I
I

J- - -

I
I

I :A: ·0 V
I

'\'- -

NOTES:
1.

SIGNALS SHOWN APPLY TO FWD SEEK ABOUT 300 CYL IN LENGTH,
ALL POLARITIES EXCEPT DIA CONVERTER ARE OPPOSITE FOR REV
SEEKS. TIMING AND AMPLITUDE ARE NOT TO SCALE.
OUTPUT DECREASES WITH EACH CYLINDER PULSE.
SERVO SYSTEM SWITCHES TO FINE CONTROL WHEN INTEGRATED
VELOCITY EXCEEDS 0.9 V.
GAIN CHANGE CAUSED BY SWITCH FROM COARSE TO FINE CONTROL. SIGNAL FOR LAST HALF TRACK IS DUE TO FINE POSITION INPUT AND IS SHOWN HERE FOR REFERENCE ONLY.
FROM FINE POSITION CONTROL CIRCUITS AND IS SHOWN FOR
REFERENCE ONLY.
SCALE EXPANDED FOR CLARITY BEYOND T = 1.
9WIOl

Figure 3-42.

83323810 A

Direct Seek Coarse position Control Signals

3-87

Eventually carriage speed increases to the point where the Veloei ty signal equals the Desired Veloci ty signal and the two
signals cancel one another. This causes the positioning signal
fr.om the coarse gate, and therefore the voice coil current, to
drop to zero. The carr iage now coasts along at a maximum velocity of about SS in/s.
As the carriage coasts, friction losses and back EMF of the
moving voice coil tend to slow it down. However, when this occurs, the velocity signal becomes less than the Desired Veloci ty signal (which is still maximum) thus causing enough voice
coil current to speed up the carr iage until the two signals
cancel again.
This continues as long as the Desired Velocity signal remains
at its maximum value, which is until less than 128 cylinders
remain in the seek. Beyond this point, the carriage starts to
decelecate.
When less than 128 cylinders remain, the D/A converter starts
to step down thus causing the Desired Velocity signal to decrease.When Desired Velocity is less than Velocity, current is
applied to the voice coil in the reverse direction causing the
carriage to slow down until the Velocity signal is again equal
to Desired Velocity. The carriage now coasts under its own inertia until the D/A Converter steps down again.
This process continues and the carr iage slows down as the destination cylinder is approached. When the heads are within one
half track of the destination, the servo system swi tches to
fine control.
Direct Seek Fine Control

General
The last half track of a direct seek is controlled by the fine
position control circuits (refer to figure 3-43). These circuits generate the signal used to bring the drive over the desiired cylinder and to keep it tracking properly over this cylinder.
In addition to this, these circuits also control coarse to fine
switching and generate the On Cylinder signal. The following
paragraphs describe all of these functions and is divided into
these areas:
•
•

3-88

Coarse to Fine switching
Fine position Signal Generation

83323810 A

•
•

On Cylinder Detection
Track Following

Figure 3-43 shows the fine position control circuits and figure
3-44 shows timing during fine position control.
Coarse tow Fine Switching
Coarse to fine switching is controlled by the Fine latch. When
th is latch is set, the Fine gate is enabled and the output of
the fine position control circuit gates to the position signal
amplifiers. Whenever this latch is cleared, the coarse gate is
enabled thus putting the servo system in coarse control.
During a direct seek, the Fine latch clears at the start of the
seek and remains clear until the heads are within one half cylinder of destination.
The coarse to fine sequence starts when the Difference counter
indicates one cylinder to go. At this time the T~l signal goes
active indicating the last cylinder is being crossed.
The one half cylinder point is sensed by the fine control level
detect circuit.
The input to_ this circuit is the Integrated
Velocity signal (refer to discussion on Direct Seek Coarse Control), which is set to zero by the same cylinder pulse that decrements the Dif:ference counter to one.
When this cylinder
pulse drops, the Velocity Integrator output starts to increase
again. When it reaches 0.9 V, the heads are about one half
cylinder from the centerline of the destination cylinder and
this causes the fine control level detect output to go active.
This causes the Fine Enable signal to go active. The Fine Enable signal is then ANDed with the T< 1 signal to set the Fine
latch.
When the Fine la'tch sets, the coarse gate is disabled and the
Fine gate is enabled thus gating the fine positioning signal to
the position signal amplifiers.
Fine position Signal Generation
The fine posi tioning signal is produced by combining the Fine
Position Analog and Velocity signals. The Fine position Analog
signal varies with distance to the destination cylinder centerline and Velocity varies with speed of the carriage.

83323810 A

3-89

i
\D

1"TEGIlATEO f"'rio:=-",-t

VELOCITY

FINE

RWO + REV EOT

VElOCITY
fEEDBACK
r-----..
I
CIRCUITS

lATCH

-------,

R
(012)

CAR BIT 0
FWD EOT

POS JT ION
SIGNAL
AMPLIFIERS

~~+~RT~Z~+~SE~E~K~E~R~~~R________~~R~~~T-__~

(072)

t-t}-

ON en

I
I
I

,
I

I
I

•

TRACK SERVO SIGNAL

~-----------------------

r---------------------,
1 r
... FWD SEEK

EVEN NUMBER
DATA TRACK
•

REV SEEK

POSITION
FEEDBACK
CIRCUITS

NOTES:

000 NUMBER 000 NUMBER
DATA TRACKf DATA TRACt(

•

I i '

Dt IITS : + : - : + :

! _ y:"X _ !
TRACK SEfWO Q,- ~
FINE POSITION: : : :
ANALOG
! _ !I:'{ _ ~
(SEEK TO OOO)M - ~.
!,.0! _ Y'!
FINE POSITION ~ - KA - ~
ANALOG
I
(SEEK TO EVEN) ;-i~lOV

I: :

: -: +: - :
Y'"\!

. - - CONTROL SIGNAL

h
i :

!-~-1'

ASSOCIATED TIMING SHOWN
ON FINE POSITION CONTROL
TIMING DIAGRAM.

Y:X ~ Y:"!.

~
~

-:v. - ~

_!f':\!.
_:
D'
- x::,..:

9WI02

~.: :
~-!"~OV

SLOPE OF ;...-;-: I
VELOCITY
[V EN NUMBER]

L ________

---- POSITION SIGNAL
- -- fEEDBACK SIGNAL

DATA~RA~

_______ ~

Figure 3-43.

Fine Position Control Circuits

PATH OF SERVO HEAD
ACROSS DIBIT TRACKS

~MOTION

OF DISK

----r-_ _(_). . , . . - - - - _ - - L - _ - - - - ,(_)- _
--L.
( +)

----r-

(+)

(_)

--L,-----r--------~--___,r___ c:::>
(+)

(+)

MOTION
OF HEAD

CYL PULSES
DIFF CNTR

INTEGRATED
VELOCITY

FINE ENABLE
ON CYL
,
DE TECTEN ABLE-'----------i____-

o
----

FINE POSITION
ANALOG

ON CYL SENSE __~.________________~-------~--~
ON CYL
NOTES:
1. REFER TO FIGURES SHOWING FINE POSITION
CONTROL AND ON CYL DETECTION CIRCUITS
FOR LOGIC ASSOCIATED WITH THIS TIMING.
9W103

Figure 3-44.

83323810 A

Fine Position Control Timing

3-91

ThE~

Fine Posi tion Analog signal is der ived from the Track servo
signal that is received from the position feedback circuits and
provides the position feedback during fine control. The amplitude of the Fine position Analog and Track Servo signals are
directly proportional and as the heads approach the centerline
of the destination cylinder both signals decrease from maximum
to zero.
The Fine position Analog signal is summed with the Velocity
sIgnal to provide speed control. These signals are of opposite
polar i ty wi th the polar i ty of Fine Pos i tion ~na1og such as to
cause an increase in carr iage speed and the polar 1 ty of Velocity such as to cause a decrease.
Because, dur ing this phase, the carr iage must decelerate, the
amplitude of the Velocity signal will normally be greater than
that of Fine position Analog. How much greater depends on the
speed of the carriage.
If the carriage starts moving too fast, the Velocity signal
will increase and therefore exceed Fine posi tion Analog by a
greater amount.
This results in greater deceleration.
However, if the carriage decelerates too quickly the Velocity signal decreases and approaches that of Fine position Analog resulting in less deceleration.
Ideal speed is obtained when the two signals are nearly equal
and the resul tant signal produces a voice coil current that
brings the heads to rest at the destination cylinder without
overshoot or oscillation.
Because the polarities of the Velocity and Fine .Position Analog
signals must be opposite, it is sometimes necessary to invert
the Track Servo signal. to obtain the proper polar 1 ty of Fine
position Analog. This is the case, because although the Velocity signal always has the same polarity (negative for focward
seeks·, posi tive for reverse seeks), the polar i ty of the Track
Servo signal depends on whether it is approaching an odd or
even numbered physical cylinder. On forward seeks, the Trac~
Servo signal decreases from a maximum positive to zero when approaching an odd cylinder and increases from a maximum negative
tC) zero when approaching an even cy1 inder.
The opposi te is
true for reverse seeks. Refer to discussion on position feedback for more information on Track Servo signal generation.
What polarity the Fine position Analog signal, which is derived
from the Track Servo signal, will have is controlled by the
Slope FF. This FF is either set or cleared at the start of the
sE~ek •

3··92

83323810 A

If the seek is to an odd numbered cylinder, the FF is set and
the Fine position Analog and Track Servo signals are of the
same polar i ty.
If the seek is to an even numbered cylinder,
the FF is cleared and the signals are of opposi te polar i ties.
The phase relationships between the Track Servo and Fine position Analog signals are shown on figure 3-43.
When the heads are centered over and tracking over the destination cylinder, both the Fine position Analog and Velocity signals are zero. When this occurs the heads are considered ,to be
on cylinder.
This condition is sensed by the on cylinder detection circuits.
On Cylinder Detection
On cylinder detection is enabled when the servo system goes into fine control (Fine latch sets). At this time, the on cylinder detection circuits (refer to figure 3-45) start to monitor
the Fine position Analog signal.
When this signal is small
enough to indicate the heads are approximately over the servo
track (if the destination cylinder), Cylindp.r Detect A and B
signals go active thus enabling the On Cylinder Sense si~nal.
The On Cylinder Sense signal tr iggers the 1.75 ms On Cyllnder
Delay, which allows the heads time to settle out over the servo
track. When the delay times out, the On Cylinder FF sets.
The On Cylinder signal causes the On Cylinder line to the controller to go active and is also used to perform various functions within the drive logic.
Track Following
Even after the on cylinder position is obtained, it is necess~ry to keep the servo system under control of the fine position control cireui ts.
This is necessary to ensure that the
heads do not drift far enough off the track centerline to cause
errors during a read or write operation.
If the heads should drift off centerline, the Track Servo signal will increase or decrease slightly from zero (depending on
the direction of the dr ift) and this is translated into the
Fine position An,alog signal. The polarity of the Fine position
Analog is such that the position signal amplifier generates the
proper voice coil current to dri.ve the heads back to the track
centerline.

83323810 A

3-93

FROM FINE POSITION FINE POSITION ANALOG
CONTROL CIRCUITS

r-----....., ON CYL
DETECT A
ON CYL
ON CYL
DETECTION DETECT B
(202)

ON CYL
DETECT
ENABLE

HEADS LOADED
AND SERVO IN
FINE CONTROL
(FINE LATCH SET)
SERVO OFFSET
OPERATION
IS NOT
COf+1ANDED

ON CYL
DELAY

ON CYL
I----~S

1. 75 ms

(084)

OFF CYL
DELAY
800 IJS

FF
R
(073)

HEADS
UNLOAD
DIRECT, LOAl'
OR RTZ SEEK
INITIATED

NOTES:
1.

ON CYL
& SENSE

ASSOCIATED TIMING SHOWN ON FINE
POSITION CONTROL TIMING DIAGRAM.

Figure 3-45.

On Cylinder Detection Logic

9WI04

If the heads drift sufficiently to cause a Fine Position Analog
signal greater than 0.4 V for more than 800 ~s, the Off Cylinder Delay times out causing the On Cylinder FF to clear. This
causes a seek error to be generated (refer to discussion on
Seek End and Seek Error Detection).
It is possible for the controller to command the drive to move
the heads slightly off the track centerline via a wr i te to the
error recovery register if it is necessary for data recovery.
This is done via an Error Recovery Command (Tag 3 and either
Bus Bit 2 or Bus Bit 3 active.
If Bus Bit 2 (Servo Offset Plus) is active, the heads move
about 250 microinches towards the spindle. If Bus Bit 3 (Servo
Offset minus) is active, the heads move about 250 microinches
away from the spindle.
I n both cases, 1:he bias signal is summed wi th the normal pos ition signal at the input to the fine position amplifier (refer
to figure 3-43).
This causes the carriage to move until the
Track Servo signal, which is of a polar i ty to move the heads
back to the centerline, equals and cancels the bias signal.
LOAD SEEK POSITION CONTROL

General

Our ing a load seek, the heads move from the fully retracted position and position out over the disk pack at cylinder 000.
The load seek must be successfully completed before the dr i ve
can respond to c:l read, wr i te or seek command f rom the controller. When the sequence is completed, the On Cylinder line goes
true and the READY indicator on the drive's control panel
lights.
The seek is initiated at the same time as the power on sequence
by pressing the START swi tch.
However, the actual posi tioning
dt)es not beg in until after the power on sequence is complete
(disk pack is up to speed).
The posi tioning is divided into
coarse and fine modes which are explained in the following.
The power on sequence is described in the Power System Discussion.
Figure 3-46 is a flow chart of the entire load sequence (except
for power on).

83323810 A

3-95

w
I

\D
0\
POLARITY OF FINE
POSITION SIGNAL
Will BE PROPER
FOR SEEK TO EVEN
CYLINDER

PRESS START

t----=)I~~!~~H P~~ ON
SEQU[11CE( 773)

SHEET

(193)

CLEAR
SLOPE FF
(072)

EOT VEL INTGRTR
OUTPUT INCREAS[S
BUT no CYL PULSES
GENERATED TO R(.
SET IT
(192)

"OSliIONlIIG SIr.NAL APPLIEIJ TO
I'OS IT 10M SIGNAL
AMPLIFIERS AIIO
CARRIAr;E STARTS
FWD

FAUL T CLEARE 0
AT CONTROLLER OR
OPERATOR PANEL
OR FAULT CARD

CLR LOAD LATCH

t-_ _:.tAND SET RTl
LATCH

(063.074 )

RTZ GATE ENABLED
AND CARRIAGE
MOYES IN REVERSEI-_ _ _~
UNTIL HEADS UNLOADED.

NOTES:
1.

NUMBERS (XXX) REFER TO DIAGRAM
REFERENCE NUMBERS
REFER TO DISCUSSION ON POWER
SYSTEM.

9W105-1

co
w
W
N
W

....o
>-

Figure 3-46.

Load Sequence Flow Chart (Sheet 1 of 2)

SHEET

ClR LOAD LATe
I---'--?I ~gAgI~:~~[
(064.074)

SET RE V EOT FF
THUS GENERATING FINE ENABLE SIGNAL

FINE POSITION
SIr.NAL STARTS
TO DECREASE
TOWARD ZERO

INDICATES H[ADS
ARE ALMOST 011
CYl AND TRIGGERS
1.7S MS Ol~ cn
DElAY
(073)

9WI05-2

Figure 3-46.

Load Sequence Flow Chart (Sheet 2)

Load Seek Coarse Control

The servo system is under coarse control from the time the load
is initiated until the reverse end-of-travel zone (refer to
discussion on Servo Disk Information) is detected.
The circuits involved are shown on figure 3-47 and the timing is on
figure 3-48.
The load seek coarse control sequence begins when the power on
sequence h3s been completed and the disk has reached 3000 revolutions per minute. At this time, the Load latch sets and enables the Load gate. The Load gate combines a bias signal with
the Velocity signal and applies the resultant signal to the position signal amplifiers.
This causes the carriage to move
forward at about seven inches per second.
As the heads move forward from the retracted position, the
heads loaded switch transfers to the heads loaded position thus
enabling the dibits sense logic (refer to discusslon on Dibits
Sensing). The drive now starts seact:hing for the positive-odd
dibits indicating the reverse end of travel area.
Because the heads are moving in a forward direction and the polar i ty of the Veloci ty signal is such as to cause the Forward
EOT Enable signal to go active (refer to discussion on End-ofTravel Detection), when posi tive-odd dibi ts are detected, the
Forward EOToOdd Dibi ts signal also goes active.
This causes
the Load latch to clear thus disabling the Load gate. It also
sets the Reverse EOT FF which in turn causes the Fine latch to
set thus enabling the Fine gate. The carriage is now controlled by the fine position control circuits (refer to figure
3-48).
If for any reason the dibits signals are not detected within
350 ms after the Load latch is set, the RTZ latch sets and the
heads unload to the fully retracted position. This also causes
the Fault latch to set and FAULT indicator to light.
pressing the FAULT switch (extinguishing the indicator) clears
the fault latch and initiates another load seek. However, the
heads will unload again thus lighting the FAULT indicator and
setting the Faul t latch if dibi ts are not detected wi thin 350
ms.
Load Seek Fine Control

The fine posi tioning signal used dur ing load seek fine control
is the same as is used during direct seeks and the component of
this signal that varies with distance to the destination is also derived from the Track Servo signal.

3-98

83323810 A

----------------,
+Y

LOAD

.....- .. pos InON
SIGNAL
AMPLIFIER

S
LATCH

G
E

r r----~~I ~!~E I

(074)

r----~------------~------SET
RTZ (MIANO
RTZ
FROM
CONTROLLER
NORMAL POWER OFF
WHEN HOS ARE
I UNLOADED

X
,...Y-0....
1C:-"E-t ft t--:~__
CO ILl t------r----.J

- Y

(204)

RTZ
.----~S

LATCH
R

NORMAL POWER OFF
WHEN HEADS HAYE
BEEN UNLOADED

NOTES:
1. ----- POSITION SIGNAL
--- FEEDBACK SIGNAL
- - CONTROL SIGNAL

(074)

REV EOT ENABLE
RTZ START FWD/
NO SR TRK UNLD
D

rFWD + REV EOT

•L__

R
!~J~_~~~

L ______________

_________________ _
POSITION
___________ _ FEEDBACK

~~~!!~~~~~~~lli

CIRCUITS

\Q
\Q

Figure 3-47.

DIBITS

----------------------~
9WI06

Load Seek Circuits

w
i

DIRECTION OF HEAD MOTION I

.....

SERVO
TRACKS

II-_ _ _ _

o
o

HEAD LOADI NG
ZONE
A

REVERSE
EOT AREA

CYL
000

CYL
001

CYL
002

u~------------~£--------------~\
(+) DIBITS

I -

LOAD LATCH
VELOCITY
FWD EOT ENABLE
FWD EOT ENABLE.
ODD DIBITS
REV EOT FF
FINE LATCH
OUTPUT FROM
FINE GATE

ON C1tINDER

9W107

Figure 3=48.

Load Seek Timing

Therefore, because the heads are over the reverse end of traveland all posi tive-odd dibi ts are being detected, the Track
Servo signal is at its maximum negative value and the Fine Position Analog sign,a1 (derived from it) is at its maximum positive value. This value is such that a constant forward motion
is obtained at the proper speed.
.
When the heads approach cylinder 000, negative-even dibi ts are
detected.
This causes the Track servo signal, and therefore
the Fine position Analog signal to decrease towards zero. The
carriage now decel'erates and servos onto the on cylinder position. On Cylinder detection and track following is the same as
discussed for direct seeks.
RETURN TO ZERO SEEK POSITION CONTROL

The return to zero seek (RTZS) function is an alternate means
for the controller to command the drive to seek to cylinder 000
without issuing a direct seek command. This might be necessary
in cases where a seek error has occurred.
The controller initiates a return to zero seek via a Tag 3 accompanied by Bus Bit 6 (RTZ).
~lhen the drive receives this
command, the RTZ latch sets and-enables the RTZ gate (refer to
figure 3-50).
The RTZ gate, like the Load gate, combines a
bias signal with the Velocity sign.a1 and applies the result to
the position signal amplifiers. However, in this case the resu1 tal'lt signal causes the carr iage to move in reverse at about
seven inches per second.
When the carr iage moves past cylinder 000, it enters the reverse end of travel area and no more cylinder pulses are generated. The loss of cylinder pulses allows the EOT Velocity Integrator output (which is normally reset to zero by cylinder
pulses) to exceed -1.4 V•• This causes the Reverse EOT Enable
signal to go true and set the Reverse EOT Enable FF (Refer to
discussion on End of Travel Detection).
Setting the Reverse
EOT FF causes the Velocity Integrator to reset but the carriage
continues moving in reverse and the integrator output starts to
rise again.
After an addi tiona1 reverse motion of about two tracks, the
Velocity Integrator output again exceeds -1.4 V. This time the
Reverse EOT Enabvle signal enables the set Load signal which
sets the Load latch and clears the RTZ latch.
Setting the Load latch causes the carriage to reverse direction
and start back towards cylinder 000.
During the remainder of
the operation, the drive seeks to cylinder 000 as during a load
sequence (refer to discussion on Load Seek position Control).

83323810 A

3-101

Fi~~ure

3-49 shows the timing for and figure 3-50
chart of the entire return to zero seek function.

is a

flow

UNLOAD HEADS POSITION CONTROL

The heads are normally unloaded at the start of the power off
sequence (refer 'to discussion on Power System). This is necessary to make certain the heads are not over the disk when it
slows down as this would cause head crash. The heads are also
unloaded during certain error conditions (refer to discussions
on Emergency Retract and Seek End and Seek Error Detection).
The following describes the heads unload sequence occurring
during a normal power off.
The sequence is initiated when the START switch is pressed and
the power supply circui ts generate signals that set the RTZ
latch (refer to discussion on Power System).
Setting the RTZ
latch enables the RTZ gate and· the carr iage starts retracting
at seven inches per second. The action is similar to an RTZ
except that the EOT detec'cion circuit is disabled so that the
Reverse EOT Enabl e signal never goers active.
Therefore, the
RTZ latch remains set and motion continues until the heads unload.
When the heads loaded switch transfers, indicating the heads
are unloaded, the RTZ latch is cleared. This disables the current to the voice coil and the carriage stops driving in reverse.
However, the power off sequence continues and this is
described in the discussions on the Power System.
SEEK END AND ERROR DETECTION
Gteneral

Successful completion is indicated when the drives On Cylinder
si.gnal is active and the Seek Error latch is not set. An unsllccessful seek is indicated whenever the Seek Error latch is
set (ei ther wi th or wi thout On Cylinder).
This occurs if the
drive cannot complete the seek or if an error occurs during the
seek operation. If the seek error latch is set, the drive cannot perform another seek until the latch is cleared. This is
done via an RTZ command (Tag 3, Bus Bit 6).
The controller determines whether the seek was successful or
unsuccessful by monitoring the On Cylinder and Seek Error
lines.
Whn On Cylinder is true it indicates heads are positioned over a cylinder and when Seek Error is true it indicates
a seek error has occurred.

3--102

83323810 A

RTZ COMMAND
Rl~Z

LATCH
AROUNG <D

t t
J,.....- - -.........
REV-··-,
---'
I
FWD - .. - - - - - - - - - - .. - - - .. __:__

VIELOCITY

:0.--_ _ __

VIELOCITY
CYLINDER PULSES
REV EOT ENABLE

- - - - - - - f { 1------',

FWD EOT ENABLE

---------~{ I---~~--~~ ~-----~--------------

. REVERSE EOT FF

--------tJ 1---4--1

REVERSE EOT PULSE
RTZ START FWD/NO
SR TRK UNLD FF
LOAD LATCH
FINE LATCH

- - - - - I } 1 - - - -......
---------------~J I------~

- - - .. - -- .. - - .. - _. - ,- -.. - -.. -r-------t-------k-----®----

OUTPUT FROM
FINE GATE

--J\I\J 1\

~
1

,-I

~\--

CYL 000

--------4/ JI-'--------------11= 1 . 75 ms
ON CYLINDER
NOTES:
1 CLEARING RTZ AND SETTING LOAD LATCH CAUSES CARRIAGE TO
REVERSE DIRECTION AND MOVE FWD.
2
CYLINDER PULSES RESET VELOCITY INTEGRATOR.
3
REV EDT FF CLEARED WHEN NEGATIVE-EVEN DIBITS ARE DETECTED
AS HEADS AP~ROACH 000.
4
FINE LATCH IS JAMMED (BOTH INPUTS HIGH) THUS DISABLING BOTH
COARSE AND FINE GATES AS LONG AS EITHER LOAD OR RTZ LATCH
IS SET
9WI08

Figure 3-49.

83323810 A

Return to Zero Seek Timing

3-103

....oI

...

CONTROllER
RTZ COM-~......- ' ) I
MAND (TAG 3.
BUS BIT 6)

I--_~~SENDS

POSITIOtlINr. SII;·
MAL APPLIED TO
POSIT Ion SIGNAL
AMPlI F IE RS AIID
CARRIAGE STARTS
IN REVERSE

VEL FED BACK TO
RTZ r.ATE AND
CARRIAGE SPEED
STABILIZES AT
ABOUT 7 IN/SEC

NO HORE en
PULSES GENERATED
TO RESET EOT VEL
INTGRTR AIID ITS
OUTPUT STARTS TO
INCREASE
(192)

9WI09-1

Figure 3-50.

Return to Zero Seek Flow Chart (Sheet 1 of 2)

CARRIAGE STOPS

GENERATE AN_ _ _ OTHER REV EOT

HOYING IN RE-

J ; - - - - ; M VE RS E AND

STARTS t - - - - ; M
MOVING FWD AT
ABOUT 7 IN/SEC

PUL:lE
(063)

GENERATE FWD
EOT Elf ABLE -

EDT YEL

I NTtRTR OUTPUTL-.lL..-~
~-~ S TARTS TO III:;.
CREASE POS(92)

~--4f 000

0 I B ITS

SIGNAL (063)

CLR LOAD
1----;MlATCH
(074)

SHEET

CARRIAGE MOYES
FWD UNDER CONTROL OF FINE POSITION SIGNAL. RE-

MAtNDER or SEQUENCE
ts SAME AS FOR A
LOAD

Figure 3-50.
tAl

.....
o
V1

Return to Zero Seek Flow Chart (Sheet 2)

9"109-2

The conditions interpreted by the drive as seek error are described in the following paragraphs.
The basic logic if; shown
on figure 3-51.
Timeout Error

If the drive does not generate On Cylinder within 500 ms of the
start of the seek, the Seek Error latch sets.
Setting the Seek Error latch causes the Difference counter to
be reset to zero and the Slope FF to be cleared. This causes
the dr ive to seek to the nearest even numbered cylinder and
generate On Cylinder.
Maximum Address Fault

If the controller commands the drive to seek to a cylinder address greater than 822 the Seek Error latch is set and the
drive will not perform the seek.
End-of-Travel Errors

General
Whenever a direct seek is being performed and the heads are positioned outside of the normal data area, an end of travel condition exists and the Seek Error latch sets.
It is possible for the heads to be posi tioned over ei ther the
forward or reverse end-of-travel area and both of these sequences are descr ibed in the following (also refer to discussion on End-of-Trave1 Detection).
Forward End-of-Travel
When the heads move past cylinder 822 they enter
end-af-travel area (inner guard band).

the forward

Because cy1 inder pulses are not generated as the heads move
over this area, the EOT Velocity Integrator output is ab1~ to
exceed +1.35 V (refer to discussion on End of Travel Detection). This causes the Forward EOT Enable signal to go active
and set the Forward EOT FF.
This causes the following:
•

3-106

Seek Error latch sets thus causing a Seek End to the controller.

83323810 A

co
w
W
N
W

co
....o

SEEK NOT
COMPLETED
WITHIN 500 ms
OF INITIATION
END OF TRAVEL
DETECTED
(EXCEPT DURING
LOAD OR RTZ)
CYL ADRS WAS
LARGER THAN

--1

SEEK
ERROR

...

-'-

HEADS UNLOAD

RTZ + INITIALIZE

---

Figure 3-51.

-..J

-- \

TO CONTROLLER

(073)

ON CYLINDER SENSE

....oI

SEEK ERROR

LATCH

822

ON CYL
~

ON CYLINDER

...

LATCH
(073)

Seek End and Seek Error Detection Logic

9Wl10

•

Seek FF (set at start of seek) clears.

•

Difference counter set to 000 (T=O).

•

Fine Enable signal goes active.

•

Slope FF is cleared to indicate a seek to an even numbered cylinder.

When the Fine Enable signal is active and the Difference counter equals zero the Fine latch is enabled thus enabling the
Fine gate.
Because the heads are over the inner guard band and all
negative-Aven dibits are being detected, the Track Servo signal
is at its maximum positive value. This results in a Fine Position Analog signal that .is at .i ts maximum negative value and
the carriage moves in reverse towards cylinder 822.
When cylinder 822 is approached, posi tive-odd dibi ts are detected, the Track Servo and Fine position Analog signals decrease, and the carriage decelerates until it is on cylinder at
physical cylinder 822. The heads remain at this location until
the drive receives an RTZ command.
Reverse End-of-Trave1
A Reverse End-of-Travel. condi tion indicates the heads have
moved in reverse past cylinder 000 and into the outer guard
band.
When this occurs, the Reverse EOT FF sets and initiates a load
sequence that returns the heads to cylinder 000. The heads remain at this In::ation until the drive receives an RTZ command
which clears the Seek Error latch.

MACHINE CLOCK
General

The machine clock circuits generate the clock signals necessary
for drive operation. These circuits are divided into two areas
(1) Servo Clock Multiplier and (2) Write Clock Multiplier.
These are both explained in the following discussions.

3-108

83323810 A

SERVO CLOCK MULTIPLIER

The servo clock multiplier circuits generate clock pulses used
by th~ sector detection, Index detection and the Read PLO circuits.
It also generates the 9.67 MHz Servo Clock signal that
is sent to the controller.
The main element in the servo clock multiplier circuit is the
phase lock loop. This loop consists of a phase and frequency
detector, error amplifier, voltage controlled oscillator and a
divide by 12 circuit.
The function of the loop is to adjLlst
itself until its output is identical in phase and frequency to
its input.
The input to the loop consists of the dibi t signals from the
track servo circuit. The nominal frequency of these signals is
806 kHz: however, their actual frequency is a function of and
varies directly with disk pack speed. This means that the output of the loop will also vary with disk pack speed.
The phase and frequency detection circuit makes the compar ison
between the input dibits and the output of the loop.
The input dibits are applied via two retriggerable multivibrators.
One of these multivibrators provides a 750 ns (approximate) output pulse which is then fed through a pulse forming
circuit to provide a 25 ns input pulse for the phase and frequency detector.
These pulses vary at the dibit frequency.
The other multivibrator has a 1.6 microsecond output which is
used to enable the feedback pulses from the loop output to the
input of the phase and frequency detector. The 1.6 microsecond
pulse is longer than the period c)f the nominal dibit frequency
(806 kHz): therefore, the feedback pulses are continuously gated as long ad dibits are present.
The outputs from the detector are fixed amplitude pulses which
are a function of the time (or phase) difference between the
positive going edges of the two inputs (refer to figure 3-52).
These outputs are applied to the error amplifier which integrates them and generates a voltage proportional to the phase
difference between them.
This 'yoltage is used as a control
voltage for the voltage controlled oscillator.
The control vol tage causes the veo frequency to vary in the direction necessary to eliminate the phase or frequency difference between the input and outpu1t of the loop. The veo output
is then divided by 12, by the divide by 12 circui t, and fed
back to the loop input.

83323810 A

3-109

0+ E Ot8ITS

VOlTAGE
CONTROlLED
OSCILLATOR

FROM
CIRCUITS {

1---4"=:'::=":"::::"'::'::~~":"'::::~" !~-OLLER
_'"

9.17 MHz NOM

TRACK
SERVO

RO RE' eLI(
"

000 OIBITS

TO
RO PLO

(4.88 MHZ)

TO IMlEX

~--------------=~~~~~~~~~ ~TECT~
NOTE
I. LOGIC
ON TtIS
PAGE
IS FOUNQ
ON DIAGRAM
L

__________________________________

.....- -.... TO IMlEX
~

....._ _....

~TECTION

REF NO 102

r-e.
0+ E OIBITS

CDLJ
I

24 }LSEC(NOM)1

+12
OSCILLATOR
OUTPUT

OSCILLATOR
PHASE

~103NSEC

;

OIBIT PHASE

FILTER INPUT

® -------~---------u-------~Ur=,1
~25NSEC

u------------u~!--------i.-~

I I

__._. ____ ~J.~ __________.I I
+ 0.7 V

U
I

_ _

'_ _ __

--u_ -----__U

+2.2V--n~----·--n

9WIII

Figure 3-52.

Servo Clock Multiplier

When the VCO output is 9.67 MHz, the feedback provided by the
divide by 12 circuit will be 806 kHz and the loop will be synchronized.
Both the 9.67 MHz and 806 kHz signals are divided by two thus
producing 4.84 MHz and 403 kHz signals. All four of these frequencies are used by the drive as shown on figure 3-52.
WRITE CLOCK FREQUENCY MULTIPLIER

The wr i te clock frequency multiplier circui t (refer to figure
3-53) generates the 19.34 MHz and 9.67 MHz signals used during
write operations.
This circuit consists mainly of a phase lock 100~ and operates
essentially the same as the servo clock mul tipller.
However,
the input to the write clock multiplier is the 9.67 MHz Write
Clock signals f rom the controlleJ:.
The phase lock loop synchronizes to these signals and provides the 19.34 MHz and 9.67
MHz outputs. These outputs are used by the NRZ to MFM converter and Write Compensation circuits during write operations.

INDEX DETECTION
Each track on the servo disk contains a pattern of missing aibits referred to as the Index pattern. When the drives Index
Detection circuits (refer to figute 3-54) detect this pattern,
they generate a 2~5 microsecond Index signal. The Index signal
indicates, both to the drive and controller, the logical beginning of a track.
The Odd Or Even Dibi ts signal provides the data necessary to
actually detect the missing dibit pattern. This signal is ~e
rived from the dibits detected fl'om the disk and has a nominal
frequency of 806 kHz. Because this signal is derived from the
dibits, whenever a dibit is missing an Odd or Even Dibits pulse
is also missing.
~t~tection

of missing dibits is done by the Missing Dibits one
shot.
This one shot is tr iggered by the Odd Or Even Dibi ts
signals and will not time out as long as dibits are present.
However, if two or more consecutive dibi ts are missed the one
shot times out. The output .of the Missing Dibits one shot provides the data input for the first stage of the Index Shift
register.

83323810 A

3-111

WRITE CLOCK
(9.67 MHZ)
FROM
CONTROLLER

PHASE
FREQUENCY
COMPARATOR

VOLTAGE
CONTROLLED
OSCILLATOR
19.34 MHZ
NOM

NOTE
I. lOGIC ON THIS PAGE IS FOUND
ON DIAGRAM REF. NUMBER 103

Figure 3-53.

3-112

FILTER

HIGH FREQ CLK
(19.34 MHZ)

...

WRT PLO CLR
(9.67 MHZ)

TO NRZ/MFM
CONVERTER
CIRCUITS

9WI12

write Clock Multiplier

83323810 A

The Index Shift register loads the output of the missing Dibits
one shot into its first stage (and also performs its shift)
each time a 403kHz Index Reference Clock pulse occurs. When
the one shot is in a tr iggered state . (indicating dibi ts were
present), a one is loaded into the register. However, when the
one shot is timed out (indicating two or more dibits were missing) a zero loads into the register.
The contents of the Index shift register are continuously compared to the Index pattern by the Index Decoder and when the
shift register contains the pattern indicating Index has occurred, the Index Decoder generates an Index signal. The missing
tiibit pattern associated with Index and the pattern contained
in the shift register when Index has occurred are shown on figure 3-54.
In summary,
elements:

the

Index

detection circuit contains

three main

•

Missing Dibits one shot - Detects the missing dibits in
the Index pattern.

•

Index Shift register - Accumulates the dibit .pattern so
that it can be compared with the pattern occurring during
Index.

•

Index Decoder - Compares the contents of the Index Shift
register with the Index pattern and generates an output
signal when Index is detected.

These elements work in conjunction with the two input signals
(Odd or Even Dib! ts and 403 kHz Index Reference Clock) to produce the Index signal.
The Index signal is sent to the controller and is also used to reset the oe lves sector detection
circuitry.
SECTOR DETECTION

The sector detection circuits (refer to figure 3-55) generate
signals which are used by the system to determine the angular
position of the heads with respect to Index. These signals are
called Sector pulses and either 30 or 32 of them are generated
dur ing each revolution of the disk pack.
The Sector pulses
logically divide the disk into areas called sectors.

83323810 A

3-113

lNDEX REF CLK (403 KHZ)
FROM

000+

MISSING 0181TS

SERVO EVEN DIBITS
CLOCK
MULTIPLIER

INDEX REF eLK

® J L I------®--..

INDEX
SHIFT
REG

(062)

3.2 JJsec

CD-n-n--.
,
: : : : : : I:
I

ODD + EVEN 0lBI15

•

' .

®LrL.n __ r~ _ ~:tnJT1 __ r~ _ iTLfl--ITI-JlJTl __ r-~_-j~
,

MISSING DI81TS

TO SECTOR
DETECTION
ORCUIT
TO
t----------CONTROLLER

@GJLiJLlj""'--I

•I

@ _ _ _ _ _ _- - , ' ; . . - - - . . . . . . I

,------,I
-

~
INDEX
SHIFT
REG

• •

' - - - - - - 'I

---=----L

L._~_~'-':
•

~-----------IL

___~

cv--------------------------~

l®------------------------~

L---_~I
,
I

L
I

INDEX

~~~~R ®
NOTES;

- ... ~~ ---.----.

2.5"SEC··-t~~-~;_
I

& MISSING DlBITS SHOWN BY DASHED LINES.

NOMINAL FREQUENCY OF 000+ EVEN OIBITS
SIGNAL IS 806 KHZ.

Figure 3-54.

Index Detection - Logic and Timing

9WI71

SECTOR
COUNTER
Jo-----'JM PRESET

Q)INOEX

o
SECTOR
PULSES

& SEC. 32

I--.....----~TO CONTROLLER

@806 KHZ

..kCLOCK

t- 2.S p. SEC--1

Q) ..DEX

~)
I

(062)

& ~,- - - - - - - - - - - - I

0~~
NOTE:
~ THIS PULSE DOES NOT INCREMENT COUNTER
BECAUSE INDEX IS STILL ACTIVE: THEREFORE,
SECTOR 000 ALWAYS CONTAINS ONE MORE
806 KHZ PULSE THAN ANY OTHER SECTOR.
WHEN SECTOR 30 OR 32 LINE FROM CONTROLLER IS HIGH, COUNTER IS PRESET TO 32
SECTORS.
w
I

.....
.....

Figure 3-55.

Sector Detection - Logic and Timing

9Wl13

The controller governs whether there will be 30 or 32 sectors
by use of the Sector 30 or 32 line. If this line is high the
dr ive presets the Sector Counter to produce 32 sector pulses.
If the line is low, 30 sector pulses are produced. The Sector
pu'.3es are generated by the Sector counter, which causes a
pulse to be generated each time it indicates its maximum value
of 4095.
The Sector counter is incremented by the 806 kHz clock pulses.
These clock pulses are derived from the servo track dibl.t signals (refer to discussion on track servo circuit) and exactly
13 440 clock pulses occur dur ing each revolution of the disk
pack.
The fact that the same number of 806 kHz clock pulses occur
during each revolution makes it possible to program the counter
to reach the maximum count (thus generating a Sector pulse) either 30 or 32. times oer revolution. This is done by presetting
the counter to the proper value at the beginning of each sector.
For example, if it is desired to have 32 sectors, the
counter would have to count 420 clock pulses in each sector
(13 440 divided by 32) and the counter would be preset to
3676.
In this case the counter starts at 3676 and increments
each clock time until it reaches the maximum count of 4095.
Reaching the maximum count causes the Sector pulse to be generated. The next clock pulse (420) presets the counter back to
3676 (thus disabling the Sector pulse) and the counter begins
the next sector. The 3676 is Obtained by subtracting 420 from
4096, which is the total number of clock pulses the counter is
capable of counting (0 through 4095 = 4096).
HEAD SELECTION
A head must be selected before a read or wr i te operation can be
performed. Head selection starts when the controller sends the
drive a Head Select tag (2) and a head address. The head address is sent on Bus Bits 0 through 4.

The Head Select tag gates the address into the Head Address
register. This address is then decoded to a Head Enable signal
(0 through 18 depending on bus 0 Bits 0 through 4). This signal then enables the head current driver associated with the
addressed head and allows the head to conduct as shown on figure 3-56.
If more than one bead is selected, a fault is indicated (refer
to discussion on Fault and Error Conditions).

3-116

83323810 A

MULTIPLE
HEADS
SELECTED

TO FAULT
AND ERROR
DETECTION
LOGIC

HEAD 00
HEAD
ADRS HEAD SELECT
REG
(083) BITS 0-4

FROM
CONTROLLER
SEL

HEAD HEAD
DECODE ENABLES 0-18
(653)

HEAD
CURRENT
DRIVERS
(654)

HEAD 18

LOAD

FROM : t i : = T O
WRT
RD
DRIVER
PREAMP

NOTE:
1. NUMBERS (XXX) REFER
TO DIAGRAM REF. NO.

9Wl14
Figure 3-56.

Head Select Circuits

READ /WRITE FUNCTIONS
General

When the drive is on cylinder and has a head selected, it is
ready to perpform a read or write operation.
The controller
initiates a read or write operation by sending the drive a Control tag (3) and the proper bus bits (refer to discussion on
Interface function).
During a read operation, the drive recovers data from the disk
and transfers it to the controller.
During a write ope:cation,
the drive receives data from the controller and records it. c)i)
the disk.
Figure 3-57 is a block diagram of the read/write circuits. The
remainder of this discussion describes the read/write circuits
and is divided into the following areas:
•

Basic Read/Write Principles - Explains the basic prin,::iples of recording data on and recovering data from a magnetic disk.

•

Read Circuits - Describes the circuits used by the drive
to recover data from the disk.

•

Write Circuits - Describes the circuits used by the drive
to record data on the disk.

BASIC READ /WRITE PRINCIPLES
General

Information is recorded on and read from the disk by the read/
wr i te heads.
The following discusses the phys ica1 pr inc iples
involved and techniques used in this process.
Writinq Data on Disk

Data is wr i tten by passing a current through a read/wr i te coil
wi thin the selected head.
This generates a flux field across
the gap in the head (figure 3-58). The flux field ma9netize~
the iron oxide particles bound to the disk surface.
Each particle is then the equivalent of ~ miniature bar magnet wi th a
North pole and a South pole.
The writing process orients the
poles to permanently store the direction of the flux field as
the oxide passes beneath the head.
The direction of the flux
field is a function of Write current polarity while its amplitude depends on the amount of cu,rrent:
the greater the current, the more oxide particles that are affected.

3-118

83323810 A

CD
W
W

l'-'
W
CD

r------------------------------------,
READ/WRITE CIRCUITS

I
I

t-J

I
I

FROM
{
CONTROllER

,
NRZ WRT DATA :
----------------~~
HIGH FREQ ClK:
WRT PLO CLKI

WRT
COMPENSATED
CIRCUITS MFM WRT DATA

,..--''----''---., RD

r----OOU

EAD/WRIT
EADS

REF ClK

NRZ RD DATA

TO
CONTROLLER

, - - - - - - - - : - - - - 1 CI RCUI TS

RD ClK
L ___________________________________

HEAD SELECT
CIRCUITS
Figure 3-57.

Read/Write Circuits Block oiagram

9Wl15

WRITE CURRENT

CURRENT
/FLOW
MAGNETIC FLUX

FLOW~

MAGNETIC COATING

RECORDING
HEAD

t
SURFACE MOTION
NOTE: RELATIVE HEAD TO SURFACE MOTION, RECORDING (WRITE OPERATION)

Figure 3-58.

3-120

iii

1S17A

Writing Data

83323810 A

Information (data) is wr i tten by reversing the current through
the head. This change in current polar i ty swi tches the direction of the flux field across the gap. The flux change defines
a data bit.
Erasing old data is accomplished by writing over any data which
may already bo on the disk.
The write current is zoned in
eight current zones to ensure proper saturation level for best
head resolution.
The write current is maximum on the outer
tracks and progressively decreased for inner tracks.
Reading Data From Disk

As the disk passes beneath the read/write head, the stored flux
intersects the gap (figure 3-59). Gap motion through the flux
induces a vol tage in the head windings. This vol tage is anal¥zed by the read circui t to define the data recorded on the
dlSk. Each flux reversal (caused by a current polarity change
while writing) generates a readback voltage pulse. Each pulse,
in turn, represents a data bit.
Peak Shift

Peak shift is an effect that degrades read accuracy by distorting the waveform. This condition exists because no electromechanical device can be perfect.
Ideally, the flux reversal command by the write toggle would be
instantaneous as shown in the Ideal Recording portion of figure
3-60.
Current would immediately swi tch from one polar i ty to
the other. As a result, the distance required to complete the
magnetic flux reversal on the disk would be so narrow as to be
insignificant: the readback pulse would then also be extremely
narrow.
To carry the principle one step further, the heads
would be an infinitesimal distance from the disk surface.
Therefore, the head gap itself could be made very small for two
reasons:
•

The magnetic field strength increases as the head moves
closer to the disk.

•

The head gap must be· wide enough to intersect sufficient
lines of force from the magnetic flux field to generate a
signal.
The weaker the signal, the wider the gap must
be. .iith the substantial flux amplitude gained by having
the head very close to the disk surface, a very small
head gap can generate a reliable readback voltage.

83323810 A

3-121

- - - - - - - - - - - - - - - READ BACK SIGNAL

~"'.--READCURRENT

~~
l-': U

,,--.. or--

FLOW

i \"'~~-'''''-;Lr---ilNr-------......,\

SURFACE MOTtON
NOTE: RELATIVE HEAOTO SURFACE MOTION, REPRODUCING (READ OPERATION)
7S18A

Figure 3-59.

3-122

Reading Data

83323810 A

IDEAL RECORDING

FLUX
REVERSAL

I
Jlr

DISK
WRITE
TOGGLE

WRITE
CURRENT

Jlr Jlr

READBACK ~
VOLTAGE

V
ACTUA~

RECORDING

DISK
WRITE
TOGGLE
WRITE
CURRENT

Figure 3-60.

83323810 A

L _ ____
~

~rite

[

Irregularity-Typical Waveforms and Timing

3-123

Howev~r,

it takes time for the current to reverse, and the flux
change is not instantaneous. Furthermore, heads must fly a finite distance from the disk. The greater the distance between
the head and the oxide, the wider the head gap lnllst be. The
resulting readback voltage is more or less sinusoidal with
peaks less easily defined in time or amplitude.
With modern high frequency recording techniques, adjacent
clock/data pulses are close enough to interact wi tl) ~ach ()t~l
ere This is shown in figure 3-61. Pea~ shift is the res~lt of
the interaction of the pulses. Because two pulses tend to have
a portion of their individual signals superimpose themselves on
each other, the actual readback voltage is the algebraic summation of the pulses.
When all "1' sn or all "0' s" are being recorded, the data frequer1cy is constant: pulses are placed apart by one cell (103
ns). As a result, the pulse spacing causes the overlap errors
to be equal and opposi tee
The negative-going and posi tivegoing errors cancel each other. This is the "zero peak shift"
condition of the " •.• 111 ••• " pattern in figure 3-61.
Peak shift occurs ~hen there is a change in frequency. A "011"
pattern represents a frequency increase since there is a delay
of about 1.5 cell between the "01" and only 1.0 cell between
the It 11 n •
As a resul t, the squeezing of the cells causes the
1n3thematical average (the actual readback voltage) to shift the
apparent peak to the left. This is early peak shift.
On the other hand, a "10" pattern represents a frequency decrease since a pulse is not written at all in the second cell.
In addition, a "001" pattern is also a frequency decrease since
there is a 1.0 cell interval between the first two bits and 1.5
cell between the last two bits.
The examples listed above examined only two or three bits without regard to the preceding or subsequent data pattern.
The
actual combinations are somewhat more complex. The drive logic
examines and defines the following patterns:
Pattern

Freguency Change

.011
1000

Increasing
Increasing
Decreasing
Decreasing

•• 10

.001

3-124

83323810 A

WRITE
TOGGLE

1'--_____---'

L
I
I

I
ZERO
PEAK~~

SHIFT

RESULTANT
(ACTUAL)
REAOBACK
VOLTAGE

NOTE:

<D IDEALIZED
INDIVIDUAL
READBACI< VOLTAGES

I
I

EARLY

tE- PEAK

SHIFT

Figure 3-61.

I
I

LATE

fci-- PEAK

Peak Shift Timing

SHIFT

7M36A

~O____O___l~1 ~I_l__I_O__~1

INCREASING
FREQUENCY

DECREASING
FREQUENCY

~ 0..J
I
9E251

Any data pattern will have considerable overlapping of the data
?attern frequency changes. Consider the overlap of these basic
~-;?ight bits:
~ny of these peak shift conditions can cause ~rrors during subsequent read operations.
The device compensates for these
known errors by intentionally writing a pulse earlier or later
than nominal. This function is accomplished by the write compensation circuit.

Principles of MFM Recording

In order to define the binary dibits stored on the pack, the
frequency of the flux reversals -must be carefully controlled.
Several recording .methods are available, each has its advantages and disadvantages.
This unit uses the Modified Frequency
Modulation technique.
The length of time required to define one bit of information is
the cell.
Each cell is nominally 103 ns in width.
The data
transfer rate is, therefore, nominally 9.677 MHz.
MFM defines a "1" by writing a pulse at the half-cell time
(figure 3-62).
A "0" is defined by the absence of a pulse at
the half-cell time.
A pulse at the beginning of a cell is
Clock7 however, Clock is not always written. Clock is suppressed if there will be a "1" in this cell or if there was a "1"
in the previous cell.

3-126

83323810 A

The rules for MFM: recording may be summar ized as follows:
•

There is a flux transition for each "1" bit at the time
of the "I".

•

There is a flux transition between each pair of "0" bits.

•

There is no flux transition between the bits of a "10" or
"01" combination.

The advantages and disadvantages ofMFM recording are as follows:
•

Fewer flux reversals are needed to represent a given binary number because there are no flux reversals at the
cell boundar iee, achieving· higher recording densi ties of
data without increasing the number of flux reversals per
inch.

•

Signal-to-noise ratio, amplitude resolution, read chain
operation, and operation of the heads are improved by the
lower recording frequency achieved because of f(~'wer flux
reversals required for a given binary number.

•

Pulse polar i ty has no relation to the value of a bi t
wi thout defining the cell time along wi th cell polar 1. ty.
This requires additional read/write logic and high quality recording media to be accomplished.

READ CIRCUITS
General

Read operations are initiated by a Control tag (3) with jus bit
1 true. This enables the analog data detection circuits, which
sense the data wr i tten on the disk and generate analog read
data signals.
The analog data goes to the read analog
which changes it into digital MFM data.

to dig i tal conver ter

The read PLO and data separator change the r~M da ta to l~RZ and
also generate a 9.67 MHz' Read Clock signal.
Both data and
r~lOGk are then sent to the controller.
The read circuits a18:) deteGt the Address Mark area and send an
Address Mark Found signal to the controller.
Figure 3-63 ShO¥o1S the main elements in the' read circuits anr.i
table 3-7 br iefly descr ibes eac::h of these elements.
The followin] paragraphs further describe the read circuits.

83323810 A

3-127

w
I

t-'

MFM
WRITE
DATA

MFM
WRITE

® ~

~IE

"I·

~IE

~I·

~,¥III!!

~ ..Ii\.-=

~~III!!

=- L)\. 4:

® --.J

RECORDED
FLUX

READ
BACK
VOLTAGE

JlI"

~JIt... -=

RAW

n n

~iff ®~- - - - - - - - - ' '----------' ' - - - - - - - - - - '

OUTPUT

---~-

'----

NOTES:

co
w
W

@ TIMrNG RELATIVE TO DRIVE AT 1/0 CONNECTOR

® SIGNAL AS IT WOULD APPEAR AT HEAD COl L.

tv
W

co
~

Figure 3-62.

MFM Recording - Waveforms and Timing

8M25

W
W
tv
W

MACHINE
ClK

(X)

RD REF ClK
(4.84 MHZ)
RD elK
ANALOG TO
DIGITAL
_---~ CONVERTER
(142)

RD PLO
AND DATA
~~~ SEPARATOR
(152-154)

L - -_ _ _

r--~---1

'-------I

ANALOG
RD DATA
DETECTION
(633)

RD/WRT
HEADS
(642)

LOCK TO DATA
ADRS MK

ADRS r-1K
OETECTI::;N
AND lOCK
__A~O_R_S_M_K_ _ _ _ _ _ _ _ _--1 TO DATA
(143)
NOTE:
1. NUMBERS (XXX) REFER
TO DIAGRAM REF. NO.
+

Figure 3-63.

Read Circuits Block Diagram

9Wl16

TABLE 3-7.

READ CIRCUIT FUNCTIONS

Circuit

Function

Analog Read Data
Detection
Circuits

Processes the analog signals sensed by the
read/write heads so that they can be used
by the digital to analog converter.

Digital to
Analog Converter

Changes the analog MFM data to NRZ and also
generates a 9.67 MHz Read Clock signal. It
transmits both of these to the controller.

Address Mark
Detection

Detects the Address Mark and transmits an
Address Mark Found signal to the controller.

Analog Read Data Detection

Circuits

The analog read data detection circui ts (refer to figure 3-64)
processes the analog MFM data detected from the disk so it can
be used by the analog to digital converter circuits.
The Read Pre-amplifier provides preliminary amplification of
the analog vol tage induced in the read coil. Th i s vol tage is
induced in the coil by the magnetic flux stored in the disk oxide during write operations (refer to discussion on Basic Read!
Write principles).
The frequency of the magnetic field flux
transitions sensed by the read coil.
The low pass filter on the output of the Read pre-amplifiE~r attenuates the high frequency noise on the read data signals and
provides a linear phase response over the range of read data
frequencies.
The output of the filter is applied to the AGe
amplifier.
This circuit generates an output signal amplitude
that remains wi thin certain limi ts regardless of the ampli tude
of the input signal. The AGe Gain Control circuit provides the
control voltage for the AGC amplifier and also provides inputs
to the Address Mark detection circuits.
The Buffer amplifier processes the AGe amplifier output to provide the proper input for the analog to digital converter circuit.

3-130

83323810 A

Read Analog to Dighal Converter

The read analog to digi tal converter circui ts (refer to f i~u~e
3-65) receive analog detection circuit and convert it to dlgltal MFM data.
The analog to digi tal converter circui t consists of high and
low resolution channels and the Data Latch FF.
The high and
low resolution channels detect the analog data by means of zero
cross detectors consisting of Schmitt triggers. The zero cross
detectors convert the analaog data to digi tal pulses which are
then applied to the Data Latch FF. The FF uses the outputs of
both channels to produce a digital MFM data output.
The low
resolution channel provides the D input to the FF and the high
resolution channel provides the clock. This produces an output
from the Data Latch FF which retains the timing of the high resolution channel.
Both channels a,re necessary because of certain high frequency
components present in the analog read data signals. These components can cause extraneous zero crossings which are detected
by the zero cross detectors.
However, the low pass f il ter in
the low resolution channel attenuates the high frequency components thus eliminating any possible extraneous outputs from
the channels zero crossing detector.
The high resolution channel still detects the crossings and
generates clock inputs to the FF, but without the D input provided by the low resolution channel the extraneous clock pulses
are ignored.
The digital MFM read data is sent to the PLO and data separator
which use it to generate the NRZ data and Read clock.
Lock to Bata and Address Mark Detection Circuits

These circuits generate (refer to figure, 3-66 and 3-67) the
Lock to Data signal and also detect the Address Mark area. The
Lock to Data signal is used to synchronize the read PLO and
data separator. The Address Mark signal is used to synchronize
the read PLO and data separato:, and is also sent to the controller.
The Lock to Data signal is active whenever the Lock to Data one
shot is in the set state. This one shot is tr iggered (to the
set state) when ei ther the Read Gate signal goes inactive or
the Address Mark is detected.

83323810 A

3-131

w
I

.....

~
~

READ/WRITE
~
HEAD

PREAMPLIFIER

!----II

LOW
PASS
FILTER

AGC
AMPLIFIER

eUFFER
AMPLIFIER

ANALOG
MFM RD
TO RD
DATA ...... ANALOG TO
DIGITAL
CONVERTER
~

AGC
GAIN
CONTROL

ADDRESS
MARK
DETECTION

TO LOCI< TO

AM DETECT. DATA AND

.. ADRS MK
DETECT
CIRCUITS

9WII7

co
w

"->
W

.....
o

Figure 3-64.

Analog Read Data Detection Circuits

CD
W
W
tv
W
Q)

t-w

FROM
ANALOG
RD DATA
DETECTION
CIRCUITS

DATA LATCH

LOW RESOLUTION CHANNEL
ANALOG MFM
READ DATA

LOW PASS
FILTER

DIGITAL MFM

TO RO PLO
~~~M~O=A~~~__~ANOM~

ZERO CROSS
DETECTOR

SEPARATOR
CIRCUITS

HIGH RESOLUTION CHANNEL
ZERO CROSS
DETECTOR

PULSE
SHAPER

0~:~OGD:J,.M ~

DELAY

/'\----7\

~'C7

f2\ LOW RESOLUTIONr--_ _---.

\.::.J DATA PULS~

'--_ _ _ _- - - J

~ HIGH RESOLU-

o "Jl~:PuLsU1"____~n1_

~ ::D~~!~~
o MFM DATA

~I-

L..._ _ _ _ _. j

LJLJ~_.fl"________Jn~___

____

--!9~& n&---:!p__-~
~I-

~--

~----q

NOTE:
THESE DO NOT AFFECT DATA LATCH
BECAUSE LOW RESOLUTION DATA
PULSE DOES NOT CHANGE.

I
~

Figure 3-65. Read Analog To Digital Converter Logic and Timing

9E 1378

FROM
ANALOG
RD DATA
DETECTION
CIRCUIT

AM
DETECT0
AM DETECT

COMPARATOR

~--~--------------------~

DATA
DETECT

f?\ AM
~ ENABLE

1.1JJ. SEC

0--READ GATE

.I"L

LOCK TO DATA
+ADRS MK
TO
DATA SEPARATOR

----

.-.--... >

7.5p. SEC

CD
W
W
N
W
CD

ADRS MARK

t---.tR

NOTES'
I. NUMBERS
ON FIGURE

0 3-67
REFER TO WAVEFORMS

.....
o

Figure 3-66.

TO
CONTROLLER

Lock to Data/Address Mark Detection

9WII8

co
Vol
Vol
N
W

ex>

I-'
0

Q) READ GATE ~,__----~~~r----~------------------~fJ~r--------.------------------------,

··l
® AM ENABLE -------~;J~'--------~

~------------~~~'--------

0
0
0

COMPARATOR ------~f~----------~
OUTPUT
(IDEALIZED)

-J
tc-- 2 .4 jLSEC -~

'_~'J-r- - - - - - - - - -

~L2.f4~

JJ~'--------~~____i_~SEC -I / yl'-----4JJ~--------

DATA
DETECT
AM

DETECT

).1

·;+--

LOCI< TO
@ DATA
ADDRESS
0 MARl<

rr
" .I

7.51' SEC

L~r__----------____

{~
;

(

., J

RESET

® ADDRESS
MARK

~------------~:f-

J.I

J J

NOTES'
I. NUMBERS
REFER TO ELEMENTS ON
FIGURE 3-66

______Pl~-______

Figure 3-67.

9WI76

Lock to Data/Address Mark Detection Logic

When the Read Gate signal goes inactive it tr iggers the one
shot and also causes it to be held in the set state. When the
Read Gate signal goes active again, it removes the set conditions from the one shot and allows it to time out after 7.75
microseconds. Detecting the Address Mark also tr iggers C! 7. 75
microsecond pulse from the one shot. Therefore, a 7.75 microsecond lock to data period occurs at the beginning of every
read operation and following every Address Mark area.
The Address Mark consists of an area about 2.4 microsec()nd in
length that contains neither MFM ones or zeros. When the drive
detects this area it generates a 7.75 microsecond Address Mark
signal.
The address mark detection circui t is enabled only dur ing read
operations (Tag 3 and Bus bit 1 active). The controller activates the circuit by raising Bus Qit 4 (Address Mark Enable).
The Address Mark Enable signal causes the comparator to start
generating output pulses that tr igger and retr igger the Data
Detect one shot.
The comparator generates the output pulses
only when there are input data pulses.
Therefore, dur ing the
Address Mark area the comparator stops generating pulses and
the one shot times out 1.7 microsecond after the last data
pulse was detected. The first data pulse following the Address
Mark area enables the Address Mark Detect gate. This triggers
the Lock to Data one shot which causes the 7.75 microsecond
Lock to Data and Address Mark signals to be generated.
Read PLO and Data Separator

General
This circuit has two functions:
(1) to convert the I~M data
from the analog to digital converter into NRZ data and (2) to
generate a Read Clock signal which is locked to the frequency
of the read data (9.67 MHz nominal). Both the NRZ data and the
Read Clock signal are transmitted to the controller.
The read PLO and data separator circuits consist of four main
parts (refer to figure 3-68):
•

Input Control - Controls whether MFM data or 4.84 MHz
clock pulses will furnish the input to the circuit.

•

Data Strobe Delay - Delays the pulses to provide the proper input to the VCO. These circuits also providE~ error
recovery capability.

3-136

83323810 A

•

Phase Lock Loop - Synchronizes the circuit outputs to the
phase and frequency of the inputs.

•

Data Separator - Converts the MFM data to NRZ data and
generates the Read clock.
This circuit is actually a
part of the phase l-ock loop.

The remainder of this discussion further describes the read PLO
and data separator circuits.
Input Control
The input control circui t (refer to figure 3-68) selects the
input that will be used by the read PLO and data separator circuits. This input will always be either MFM data from the read
analog to dig i tal converter or 4.84 MHz clock pulses from the
~ervo frequency multiplier circuit.
The 4.84 MHz clock signal is used only when the dr ive is not
reading MFM data, such as before Read Gate is raised. It also
uses the 4.84 MHz clock whenever the Address Mark Enable signal
is active because this indicates the drive is expecting the Address Mark which contains no MFM data.
The dr ive uses the
clock signal as a substi tute for the read data for two reasons:
(1) the signal is deri'ved from the track servo dibits
and therefore, its frequency (like that of the read data) varies directly with disk pack speed and (2) after being prodessed
by the pu1 se formi ng c i r cu i ts , it has about the same nomi na 1
frequency as the read data (9.67 MHz). This results in it being easier for the phase lock loop to synchronize to the proper
frequency when switching from one of the signals to the other.
Once selected the signal is applied to a pulse forming network
which generates a 20 ns pulse for each transi tion of the input. These pulses are then applied to the data strobe delay
circuits and also furnish the data input to the data separator.
Data Strobe Dela~
The purpose of the data strobe delay circui t (refer to figure
3-68) is to de1,ay the data pU1EJeS sufficiently to provide the
proper timing relationship at the input to the phase lock
loop. The output of the data strobe delay ci rcui t is delayed
by a time determined by the state of the Data Strobe Early and

83323810 A

3-137

INPUT CONTROL

r-------------------------··-----------..,

FROM
RD ANALOG
TO DIGITAL
CONVERTER

DIGITAL I'j\
MFM DATA I.:..J

I
I

-r-------------,
READ GATE

FROM
CONTROLLER

PULSE
FORMER

AM
I EN ABLE

,
I

RD REF ClK
(4,84 MHZ)

~------------------------------------~
DATA STROBE

FROM
{
CONTROLLER

DATA
STROBE LATE
DATA
STROBE EARLY

PHASE LOCK LOOP

r------------------------,
I

DATA
STROBE
DELAY

DELAYED
DATA

®:
I

I
I

PHASE
FREQUENCY
COMPARATOR

FILTER

veo

I
I

r
I

FEED8ACK
CLOCK PULSES

®
DATA
SEPARATOR

:_______________________ , ____ J:
NOTE
I.

NUMBERS
REFER TO
TIMING ON AD PL.O AND DATA
SEPARATOR TIMING DIAGRAM.

RD eLK

lro

RD DATA (NRZ) _ J C':'NTROLLER

9[1398

Figure 3-68.

3-138

Read PLO and Data Separator Circuits

83323810

Data Strobe Late signals. These signals facilitate the recovery of marginal data and are enabled by Data Strobe Early or
Late (Bus Bit 7 or 8) and Control Tag (3).
The output of this circuit is the Delayed Data signals which
are sent to the input of the phas,e lock loop.
phase Lock LOOp
The phase lock loop (refer to figure 3-68) synchronizes the
read PL~/data separator circuit outputs (NRZ data and Read
Clock) to the input (either MFM data or 4.84 MHz clock).
The
loop accomplishes this by comparing and following two signals:
(1) the Delayed Data signals which have a constant phase and
frequency relationship to the input MFM data or 4.84 MHz Clock
(whichever is used) and (2) the Feedback Clock Pulse signals
which have a constant phase and "frequency relationship to the
output NRZ data and Read Clock signals.
The loop inputs are
applied to the phase/frequency comparator.
The phase/frequency comparator generates output pulses which
are a function of the phase and frequency between the positive
going edges of the inputs. The filter circuit uses the comparator outputs to generate a contol voltage for the voltage controlled oscillator (VCO).
This control voltage causes the frequency of the VCO to vary in
the direction necessary to eliminate the phase and frequency
differences between the two signals that were input to the comparator.
The output frequency of the veo is actually twice that of the
input so for an input of 9.67 MHz it has an output of 19.34
MHz.
However, the data separator divides this by two before
generating the Feedback Clock pulse signals thereby providing a
feedback to the comparator that satisfies the loop.
Data Separator
This circui t determines if the data pulses represent a one or
zero and then converts the data to NRZ.
It also generates the
Feedback Clock Pulses to the comparator and the 9.67 MHz Read
Clock that is sent to the. controller.
Figures 3-69 and 3-70
show simplified logic and timing for the data separator circuit.

83323810 A

3-139

RD CLK
DATA
WINDOW

","s

ENABLE
---------r-.------~D

D
FF

RD DATA@3 }

~_4--------------~D

.--------i~:> F F

~(_N_RZ-.;.)_ _

~gNTROLLER

A t----.t>

f4\

FEEDBACK
CLOCK PULSE\:) TO
COMPARATOR

110"5

:>
FROM ADRS MK
AND LOCK TO
OATA LOGIC

ENABLE

5
LOCK TO DATA + ADRS MK

DATA STROBE

11
NOTE

>
R

I. NUMBERS
REFER TO
TIMING ON RD PLO AND OATA
SEPARATOR TIMING OtAGRAM.

Figure 3-69.

Data Separator Logic

9EI40A

lliulTAL
,1"-',
,-,- MFM C)ATA

.-J:

f , · - ---I,--_~

;:'
-n~~_,~n~!~~r,~
::

DATA

, ;:'

C\4 FEEDBACK
\:..J CLOCK
PULSE

vco

•

•
•

I'
I

____~n~:__~n~________~n~__~n_____~~
:

__~n~l~n~___~n~~n~____~
h n
n
n
n
:

'--------'

'------.~..

~_:~n~i~n~

DELAYED
DATA

•

OUTPUT~rLJuu~~uLJLruLr-'ururul1u~

(';;'\ DATA
WINDOW FF

: ! : : : ~ : ~ :
: i i i ! r:-t
~

---.!.-.J
:

1"7'
READ CLOCK
\!.) FF

: :

••

L.!-J

: . :

;

: : : : :
:

L'
I

•

t,.
I

•

----~~--~~--------~~------~~------· . ..
1
v
L
n
n
n
n
n
n
n
n
n
n.
·
,

NOTE
NUMBERS

0 REFER TO THOSE ON FIGURE

9EI41A

SHOWING RD PLO AND DATA SEPARA1t)R CIRCUITS

w
I

~
~

.....

Figure 3-70.

RD PLO and Data Separator Timing

The vee outputs provide the proper timing relationships for the
data separator by c,:>ntrolling the Data Window and Read Clock
FFs.
The Read Clock FF generates the 9.67 MHz Read Clock signal and also provides timing signals to th\~ datd sep·3.rai::.H"
logic.
The Data Window FF generates the Data Will~t-)W which is
used to determine whether the input data pulses represent ones
or zeros. The actual decoding of the data is done by thp. "l's"
Enable and no's" Enable FFs.
If a data pulse represents a one it OCCu(~ during t~e data window and sets the II l' s" Enable FF. Setting this FF generates a
Feedback Clock pulse and causes the Data Buffer FF to generate
a NRZ one.
If the data pulse represents a zero the "l's" Enable FF is not
set an~ the Data Buffer FF generates a NRZ zero.
Tn this case
the "0' s" Enable FF which is set by ~very data pulse generates
the Feedback Ciock Pulse signal •.
Before accurate det.~ct lOll ·:>f data can begin, the proper phase
relationship must be established between the data (representing
ones and zeros) and the vee output pulses. This is done during
a 7.75 microsecond lock to data period which is initiated by
the Lock to Data signal.
This signal is a 7.75 microsecond
pulse tha·t or';Cllrs when the A.ddress Mark is detected.
The Lock
to Data signal holds the "0' s" Enable FF set and disables the
output 0f tne "l's" Enable FF. Therefore, if the circuit is to
synchronize properly the pulse must occur during a period when
tha deive is reading only zeros.
WRITE CIRCUITS
General

The Write circuits operation is initiated by a Control tag (3)
with Sus hit 0 true. This allows the drive to start processing
serial NRZ data received from the controller.
The write data
is received via the bidirectional Read/Write data line and is
first sent t.:> the R·rz to ~"'FM coverter/write compensation circuits~
These circuits convert the data to MFM and also compensate it for peak shift (refer to discussion on basic read/write
principles for more concerning peak shift).
The compensated
data is then processed by the write drive circuits and written
on the disk.
Figure 3-71 shows the write circuits and table 3-8 brie.fly explains their function.

3-142

83323810 A

CD
W

W
N
W

CYL ADRS
REG

CD
~

MACHINE
CLK

HIGH
FREQ CLK
(19.34 MHZ)

WRi PLO elK

(9.67 MHZ)

WRT CURRENT

CONTROL
(613)

NRZ TO MFM

WRITE
~
)W~R~T-D-AT-A~ ~ CONVERTER AND ~~~~1'\..
COMPENSATFD "\ DRIVER

COMPENSA- MFM DATA
/ CIRCUITS
( (NRZ) V_ WRT
TION CIRCUITS
V

~ RD/WRT r-MFM WRT DATA _ "\ HEADS
~
(DRIVER CURRENTV (642) ~

FROM
CONTROLLER

(132, 133)

I (622)

NOTE:
1. NUMBERS (XXX) REFER
TO DIAGRAM REF NO.

WRT GATE
AM ENABLE

Figure 3-71.

Write Circuits Block Diagram

9W119

TABLE 3-8.

WRITE CIRCUIT FUNCTIONS

Circuit

Function

NRZ to MFM Converter
and Write Compensation Circuits

Converts the NRZ data from the
controller to MFM data and also
compensates the data for
problems
caused by variations in the wrlte data
frequency.

write Driver
Circuits

Uses the MFM data to produce the
current necessary to record data
the disk.

write Current
Control

Reduces the write current amplitude as
the heads move from the outer tracks
to inner tracks.
This ensures that
the correct amount of current will be
used as the' circumference of the cylinders decreases.

NRZ to MFM Converter/Write Compensation Circuits

The NRZ to MFM Converter/Write Compensation circuits convert
the NRZ data into MFM data and also shift the output MFM pulses
to compensate for peak shift (refer to discussion on basic
read/write principles). Figures 3-72 and 3-73 show simplified
logic and timing for these circuits.
The 9.67 MHz and 19.34 MHz signals from the servo frequency
multiplier circuit provide basic timing signals for the write
compensation circuits. The NRZ data from the controller provides the data input. These inputs are applied to the pattern
decode and NRZ to MFM converter circuits.
The NRZ to MFM converter converts the NRZ data, into lJIFM data
and applies it to a delay line. The delay line has three outputs which are combined with the outputs of the pattern decode
logic (at the Early, Late and Nominal gates) to produce compensated write data.

3-144

83323810 A

I Ir - - - - -,I I~----------------~
MFM OATA
I

MFM TO

NRZ
: CONVERTER:

WRT GATE

® HIGH
FREQ ClK
(19.34 MHz)

L ______ -1

CD (9.67
WRT ClK
MHz)

r -:- -- -- - ..,

1000

lATE

I
I XOII
I
I
PATTERN
EARLY
I DECODE I
I XOOI
I

@WRT DATA
(NRZ)

I
L ____ -'

NOTES:

AM ENABLE

XXIO

@)
COMPENSATED
TO WRT
WRT DATA
DRIVER
CIRCUITS

I. NUMBERS
REFER TO TIMING ON
WRITE COMPENSATION TIMING OIAGRAM.

®
9EI43A

Fig~re

3-72.

Wr.it~ ~ompensation/NRZ

to MFM Converter Circuits

WRT PLO
eLK
I
(9.67 MHZ)
HIGH FREQ
eLK
(19.3 MHl)

L..J

;::::: I
:::::::
: ;:
I: I
: :
•

WRT DATA
(NRl)

.
•

oj; i! i

MFMDATA

EARLY DATA
ENABLE

I
I

@ COMPENSATED
MFM DATA

I 0 I 0

I
I

In
.."

II
II

"
l.

--::-1217 5

:fLlJEl

(El

I
I

(1"l

..::

I
I

,
·:
:
In
m ________________r--l_~-··
n
n
ILSLJl
·
________________~rl_~--

·
rn
."• ·•

rTl· .
n ·n

LATE DATA
® ENABLE
DATA
ENABLE
® NOMINAL

EARLY
PATTERN

@ LATE
PATTERN

'0
0
------~--------~
•

0 RAW
0

,I
I

rEl
1

I 0

I 0 I 0

NOTE:
NUMBERS ( ) REFER TO LOGIC FOR
WRT COMPENSATION/NRl TO MFM
CONVERTER CIRCUITS.

Figure 3-73.

9EI44A

Writp, Compensation Timing

The pattern decode logic analyses the NRZ data and determines
if its frequency is constant (00000 or 11111), increasing (011
or 1000), or dec:reasing (10 or 001). The outputs from the pattern decode logic enable either ,the Early, Late or Nominal gate
(depending on the input frequency) to provide compensated write
data as follows:
•

If frequency is constant, there will be no peak shift.
In this case the data is defined as nominal and is delayed 6 ns.

•

I f frequency is decreasing, the apparent readback peak
would occur later than nominal. To compensate for this,
the data is not delayed and is therefore 6 ns earlier
than the nominal data.

•

I f frequency is increasing, the apparent readback peak
would occur earlier than nominal.
Therefore, this data
is delayed 12 ns which is 6 ns later than nominal.

After being wr i te compensated the data
write driver circuits.

transmi tted

to the

Write Driver Circuit

The compensated write data is sent to the read/write chassis
and applied to a differential receiver in the write driver circuits (refer to figure 3-74). The output of the receiver then
serves as a clock for the Write Toggle FF. This flip flop toggles only when the Wr ite Enable signal is active.
The output
of this flip flop provide the input to the Write Driver which
in turn generates the current for the read/write heads.
The
magnitude of the current applied to the heads is controlled by
the write current control circuits.
Write Current Control

The magni tude of the wr i te current sent to the heads is controlled as a function of cylinder address. This is referred to
as wr i te current zoning as the zones are divided into the following segments of tracks:
0-127, 128-255, 256-511, land 512
through 822.
Wr,ite current is reduced at each zone boundary
from outer to inner tracks.

83323810 A

3-147

COMPENSATED ._--=~
MFM DATA
~l

OIFF

RCVR

~--=~WRT

WRT

DRIVER

TOGGLE

---J

o
I

COMPENSATED'i'
II
II
~~
MFM DATA
~~
L-~
~
I

WRT
TOGGLE

SELECTED HEAD

WRT
CURRENT
CONTROL

@
WRT ENABLE _ _

I--~ WRT CURRENT TO

WRT
ENABLE

I r - -_ _ _--.

CD
W
W
tv
W

~_ ____..;,.j:1

WRT
IA\
CURRENT ~

L
9E!45

co
~

Figure 3-74.

Write Driver Circuits and Timing

Write Data Protection

General
Write data protection consists of disabling the write driver
circuit whenever there is danger of writing faulty data on the
disk pack. It is initiated if the drive detects the Write Protect signal active, Fault latch set, or a low voltage condition. All of these are described in the following.
Write Protect
The Write Protect signal goes active if any of the following
occurs.
•

Controller commands a write while the heads are in an offset posi tion (refer to discussion on Direct Seek Fine
position Control-Track Following).

•

WRITE PROTECT switch on drive operator panel has been depressed to light the indicator. In this case, depressing
the swi tch to extinguish the indicator causes the Wr i te
Protect signal to go inactive.

•

Head alignment is being performed.

•

Low dc voltage condition is detected or the disk pack
speed slows down below 2700 r/min.
Both of these conditions will also cauee an emergency retract of the heads
(refer to discussion on (Emergency Retract).

Fault
The Fault latch sets as a result of a number of drive malfunctions. The conditions causing the Fault latch to set are described in the discussion on Fault and Error Conditions.
Loss of Voltage
If power is lost or drops below a certain level, an emergency
retract is performed.
However, in this case it is possible
that other signals used to disable the write driver (Write Protect and Faul t) will not function properly and the dr ive will
continue to write while the heads are being retracted.
This
could al ter or destroy data already on the pack.
The loss of
voltage protection circuit consists of a capacitive discharge
network that ensures the write circuits are disabled until the
heads are unloaded.

83323810 A

3-149

FAULT AND ERROR CONDITIONS
GENERAL

The following descr ibes those condi tions which are interpreted
by the drive as errors.
All of theRe conditions either: light
an indicator at the drive and/or send a signal to the controller indicating an error has occurred.
These errors are divided into two -:ategories: (1) those indicated by Fault Latch and register (2) tho::le not indicated by
Fault T.latc~ and reg ister. Both are explained in the followi'1g
(refer to figure 3-75).
ERRORS INDICATED BY FAULT LATCH AND REGISTER
General

Certain erc::>cs set the drives Fault latch and also set
fault registet l.:ttches a$~ociated with the ~rror condition.

the

Setting the Fault Latch does four things (1) enables the fault
line to the controll~r (2) li3hts the FAULT indicator on the
drives operator control panel (3) clears the drives Unit Ready
signal (4) inhibits the drives write and load cir~uitry. These
events prevent further drive operations from being performed
until the error is corrected and the Fault latch is cleared.
Providing the error condition or conditions no longer
the Fault latch is cleared by any of the following:
•

FAULT switch on op~rator panel.

•

Controller Fault Clear signal from the controller.

•

Initialize signal from the controller.

•

Maintenance Fault Clear switch on Fault card.

•

Powering down the unit.

exist,

Whenever an error occurs that set:; the Fault latch, it also
sets a latch in the fault r.eg ister.
These latches provide a
means of stor ing the error indication uni t so i t <..'~a~l b~ referred to later for maintenance purposes.
The fault register
latches are cleared only by power ing down the dr ive or by the
Maintenance Fault Clear switch on the fault card.

3-150

93323810 A

WRT FAULT
FAULT

+5V

MULTIPLE HD SELECT

SHEET 2

HD SELECT
FAULT

LIGHTS OPERATOR
FAULT
INDICATOR
ENABLES FAULT
SIGNAL TO
CONTROLLER

~~PANEl

CLEARS DRIVE
READ., LATCH
DISABLES DRIVE
WRITE CIRCUITS

WRT GA_TE.
RD GATE
WRT FAULT

oN eyl

LOW ~46 VOLTS
LOW ~ 5 VOL TS
LOW :t20 VOLTS

VOLTAGE
FAULT
S

SHEET 2

LATCH

SPEED
DETECTION

SPEED +
VOLTAGE
J--F_A.....,:U:...,:L...;,.T_---.....- 0 I SA BLES WRT
CIRCUITS
ENABLES WRT
PROTECT TO
CONTROLLER

r---------------~--~R

Flqilre 3-75.

FaQlt

9W120-1
~nd

Error D~t~ction Logic (Sheet 1 of 2)

I
I-'
U1

SHEET'

PWR UP MASTER CLR
MAINT FAULT
ClR SW
CONTROLLER INITIALIZE
OPERATOR FAULT CLR SW
CONTROLLER FAULT CLR

NO SERVO
DIBITS
TRACKS
LIGHTS OPERATOR
NO OIBITS
0181TS
.-,;...~------t DE TECT ~----.;~-----t--t S
...-------------4It--pAN ELF AU LT
CIRCUIT
LATCH
INDICATOR
R

TIMEOUT ERROR
(FWD + REV EOT) + (MAX AORS)
~

RTZ
CONTROLLER INITIALIZE

SEEK ERROR
S
LATCH
R

SEEK ERROR

ENABLES SEEK
ERROR TO CONTROLLER
L.....-. INHIBITS SEEK
LOGIC

t....-.-

9W120-2

CD
W
W

tv
W
CD

......
o

Figure

3-75~

Fault and Error Detection Logic (Sheet 2)

The following describes each of the conditions
Fault latch and fault register latches to be set.

causing

the

Write Fault

A wr i te faul t
exist.

is indicated if any of the following condi tions

•

Low output from write driver indicating it may not be operating properly.

•

Low current input to write driver.

•

Low +22 volts to write driver.

•

No write data transitions when Write Gate is active.

More Than One Head Selected

This fault is generated whenever more than one head is selected. The outputs of the head select circuits are monitored by
summing and voltage comparator circuits. If more than one head
is selected, the circuit generates a Multiple Select Fault.
Read and Write

This fault is generated whenever the drive receives a Read gate
and Write gate simultaneously from the controller.
(Read or Write) and Off Cylinder

This fault is generated if the drive is in an Off Cylinder condition and it receives a Read or write gate from the controller.
Voltage Fault

This fault is generated whenever the ±46, ±S or ±20 voltages
are below satisfactory operating levels.

83323810 A

3-153

ERRORS NOT INDICATED BY FAULT LATCH OR REGISTER
General

The following e.rrors are detected by the drive but are not
stored in the fault reg ister and do not set the Faul t latch.
However, they do sense the drive to give other error indications and this is explained in the following paragraphs
Low Speed or Voltage

The Speed or Voltage Fault signal goes true when the drive detects either a low voltage condition or that drive spindle
speed is below 2700 r/min. When either of these are detected,
the drive write circuits are Qisabled and the write Protect
signal is sent to the controller.
These also resul t in an
emergency retract of the heads (refer to discussion on Emergency Retract).
No Servo Tracks Fault

If dibi ts are not detected wi thin 350 ms after the 10c!d seek
sequence begins, the No Servo Tracks latch is set. This lights
the FAULT indicator on the drive operator control panel and also enables the Return to Zero (RTZS) logic. Enabling the RTZS
logic causes the heads to unload.
Another load cannot be
started until the No Servo Tracks latch is cleared.
The No
Servo Tracks latch is cleared in the same manner as the Fault
latch.
Seek Error

The Seek Error latch is set by any of the following error conditions:
•

On Cylinder was not obtained within 500 ms from the start
of the seek.

•

Forward or reverse end of travel (EOT) sensed.

•

Dr ive is commanded to seek to a cylinder address greater
than 822.

Setting the Seek Error latch enables the Seek Error line to the
controller and also inhibits the drive from performing another
seek until the Seek Error latch is cleared.
The latch is
cleared by a Return to Zero Seek command.

3-154

83323810 A

MICROCIRCUITS

SECTION 4

MICROCIRCUITS

INTRODUCTION

This section provides a functional understanding of the various
microcircuits (integrated circuits or ICs) used in the equipment, including their MIL STD 806 (B/C) symbols as depicted in
each logic diagram set. The section divides into three subsections each of which is described in the following paragraphs.
Section 4A discusses the charclcter is tics , operational theory,
and physical packag ing of the TTL (transistor-transistor logic), ECL (emitter-coupled logic), and CMOS (complementary metal
oxide semiconductor) microcircui t families.
It concludes wi th
some general information on operational amplifiers.
Section 4B describes the symbology used on the individual data
sheets in section 4C, including the meanings of the var ious
modifiers and qualifiers that are part of each logic symbol.
Section 4C contains the data sheets, arranged numerically by
CDC element identifier, and information regarding data sheet
interpretation.

83323810 A

4-1

GENERAL 'THEORY

SECTION 4A

GENERAL THEORY

INTRODUCTION
A microcircuit is an electronic circuit in a miniature package
that performs a specific binary or linear function.
Microcircui t complexi ty var ies from a few logic gates to more than
100 9ates on a single silicon chip. The term small-scale integratlon (881) is sometimes used to refer to a level of complexity of up to 12 logic gates. Medium scale integration (MSI)
refers to circuits containing from 13 to 100 gates.
Large
scale integration (LSI) generally indicates circuits containing
100 or more gates.
These gates may be interconnected within a
microcircuit to form flip-flops, multivibrators, etc., which in
turn are further interconnected, again within an individual
microcircuit, to form registers, counters, coders/decoders,
mul tiplexers/demul tiplexers, etc.
Thus it is possible for a
microcircuit to provide simple gating functions (AND, OR, NAND,
NOR) as in SSI/1 or to provide complex functions (registers,
counters, arithmetic logic units, memories, etc.) as in LSI.

TR ANSI ST 0 R.. TR AN51ST OR·LOGIC (TTL)
TTL microcircui ts provide small physical size and high per formance-to-cost ratio.
Reliability also improves because relatively few interconnections are necessary.
Most TTL microcircuits are of the monolithic type. That is, a complete circuit or group of circuits is fabricated on a single silicon
chip. Another type-of microcircuit is the hybrid. Hybrid circuits consist of small discrete components mounted on a ceramic
substrate. A metallization pat1:ern on the substrate forms the
interconnections. Hybrid circuits usually appear in relatively
small quantities.
Ordinarily, microcircuits cannot be opened
for repair or troubleshooting.

83323810 A

4-3

STANDARD TTL CHARACTERISTICS

There are fi ve ser les of TTL circui ts:
Standard, Low-Power,
High-Speed, Schottky-Clamped and Low-Power Schottky TTL circuits. These series are functionally identical except for propagation time and power consumption. All five series are compatible, circuits from any series can interface with any other
series.
These series are described under their individual
headings further in this section. A circuit of a series normally drives 10 circuits of the same series. However, combining circuits of different series varies the output drive capability (fan-out) from 1 to over 50. Typical values of the essential characteristias for all series are:
Supply voltage
High output voltage
Low output voltage
High input voltage
Low input voltage

Min
+4.75
+2.4
+2.0

Nom
+5.0
+3.3
+0.2
+3.3
+0.2

Max
+5.25
+0.4
+0.8

The logic levels may be observed as indicated below, depending
on the circuit load:
HIGH - from +2.0 to +3.3 volts.
LOW - from +0.2 to +0.8 volts.
TRI-LEVEL CIRCUITS

Tri-Level (tristate) cir-cuits are similar to conventional TTL
circuits.
In addition to the normal high or low, tri-level
circuits have a special control input that places the output of
the circuit into an "off" (high impedance) state. In the off
state, the circuit effectively disconnects from the output
line. This characteristic is useful in a bus or party-line application where a number of driving circuits connect to a common transmission line, but only one circuit is active at any
given time. A trilevel circuit draws significantly less input
current when it is in the "off" state.

4-4

83323810 A

OPEN COLLECTOR CIRCUITS AND WIRED LOGIC

Some TTL microcircuits have an open-collector output. That is,
th~ collector loaj or active pull-up portion of the output is
not present.
The output pin of the package connects ')111y t,,)
thp. collector of "an npn transistor.
An open-collector output
can go low only. It cannot drive the input of a following circuit high.
To operate properly, an open-collector output must
connect to an external pull-up resistor tied to Vcc.
More than one open-co11ec tor ou tpu t may connec t to the same
pull-up resistor to form wired logic. This is sometimes called
"collector dotting".
Figure 4-1 illustrates open-collector
circuits and a wired - A~D gate.
Each gate accomplishes the
NAND operation for active-high inputs, and the NOR operation
for active-low inputs.
The expression for the function performed at the wired output is Y =. AB+CD or Y = AB+CD. Although
sometimes referred to as "wired - OR" or "dot - OR", "wired AND" is the (~()rreGt descr iption of the logic performed by this
circuit.
UNUSED INPUTS

Generally unused inputs ')f TTL microcircuits are te.(minated in
one of the following methods:
•

Unused inputs are connected to used inputs if this does
not exceed the fan-out of the driving output.

•

Unused inputs are connected to Vec through a 1 kn resistor.
The resistor protects the input from transients.
Up to 25 inp~ts may be connected to one 1 kn resistor.

•

Unused inputs are connected to the output of
gate. This output must always be high.

•

Unusea inpu ts are connected to a separate supply vol tage
between 2.4 V and 3 V.

Leaving unused inputs open degrades
characteristics of TTL microcircuits.

the

switching

and

unused

noise

DUALITY OF FUNCTION

Figure

4-2 shows the four basic TTL gates (NAND, NOR, AND,
As implied by the logic symbols and truth tables, each of
the two invert ing gates may be considered as performing ei ther
the NAND function or the NOR function, depending upon which of

OR).

83323810 A

4-5

r"OPE'N -CoLLECToR- -

...,

NAND GATE

Vec

r ..,

COMMON EXTERNAL
~ PULL - UP RESISTOR

I
I

L...J
I

~ WIRED GATE
GND

L ___________

IOPEN COLLECTOR - - - - - - - --,
NAND GATE

INPUTS

!IF:-----+---..
L _ _ _ _ _ _ _ _ _ _ ....lI

TRUTH TABLE
INPUTS

OUTPUT

A B

..,

to!

X L

LI
X: IRRELEVANT

..J
9K I A

Figure 4-l.

4-6

Open-Collector Cireui ts an·j a Wi red

.~~D

83323810 A

the input states (high- or low-level) is regarded as being more
significant -- that is, "activE~".
Likewise, the two non-invertin~ gates can perform either the AND or the OR function,
dependlng upon the polarity of the active inputs.
This principal of duality applies to all of the microcircuit
families, not just to TTL. Later in this manual, these symbols
are used in either representation to illustrate the logical
construction of more complex circuits. When each of these composite circuits is constructed, a new symbol is generated.
These symbols are then used to construct yet a more complex
circui t, such as flip-flops being used to construct registers,
counters, etc.
BASIC TTL CIRCUITS

Generally, all ~rTL microcircui ts are dr ived by using combinations of the four basic (or "standard") gates shown on figure
4-2.
These standard gates may be modified in various ways to
meet the requirements for faster switching speed or lower power
consumption.
The several "series" thus produced are differentiated as follows:

•

xxx

•

XXXL

•

XXXH

•

XXXS

•

XXXLS

= Standard series
= Low-Power series
= High-Speed ser ie!>
= Schottky Clamped series
= Low-Power Schottlty series

The following paragraphs describe the characteristics of each
series. Electrical schematic diagrams are included to show how
the standard NAND gate (depicted at the top of figure 4-2) is
modified for each series. The other basic gate types would, of
course, undergo similar alterations.
Standard Series

Because of the effect of capaci'ty, decreasing the impedance of
a circuit tends to make the circuit switch faster.
However,
decreasing the circui t impedance also tends to increase power
consumption.
The Standard Series TTL attempts to compromise
speed and power requirements.
Typical swi tching speed is 10
ns. Power consumption is 10 mW per gate. The stanoard-series
NAND gate, shown at the top of: figure 4-2, operates as follows: If one or both inputs are low, 01 conducts, bringing the

83323810 A

4-7

I
CD

Vee
R4

l30n

)-v
:~

y= AB
Y=A+B

INPUTS [
OUTPUT

INPUT OUTPUT
y
A B
H
L L
L H
H
H H
H
H H
L

IKn

GNO

POSITIVE NAND
Vee

I~TS[~

________

---oQ'OUTPUT

)-V

Y=A+B
y=i.B
INPUT OJTPUT
A B
Y
H
L L
L
L H
H L
L
H H
L

--------------------~---oGND

POSITIVE NOR

Figure 4-2.

9W169-1

Basic TTL Gates (Sheet 1 of 2)

~------~----------~------~----QVcc

:~ 8)-Y

4Kfi

..---QOUTPUT

Y=AB
INPUT OUTPUT
A B
Y

L
H
H

L
L
L

IKfi

L-~--------4-----~--~~----~----oGND

POSITIVE AND·
----~----~~--------~------~--~Vcc

" ' - - - 0 OUTPUT

R4
IKfi

)-Y

Y=A+B
INPUT OUTPUT
A B
Y
L
L L
H
L H
H L
H
H

~~--------~-----4----~----~~~GND

POSITIVE

Figure 4-2.

9W169-2
Basic TTL Gates (Sheet 2)

base voltage of 02 close to ground. 02 turns off, causing 03
to be off and 04 to be on. Thus, the output is high. If both
inputs are high, the base-collector j unction of 01 is forward
biased.
This allows current to flow through Rl into the base
of 02 turning 02 on.
When 02 is on, base current flows into
Q3, and it turns on, causing the output to be low.
The ~u1tip1e-emitter input transistor, 01, replaces combinations of resistors, diodes, and transistors found in other
types of logic.
This configuration results in smaller size,
which reduces stray capacity.
Low stray capacity and lo'w circu it impedances help to increase swi tching speed. At the output, 03 and 04 form an active pull-up or totem pole drive circuit. When the output is low, 03 is saturated, providing a low
source impedance.
I f the output is high, 04 acts as an emi tter-fo110·~~r. that also provides a low source impedance.
This
arrangement per.ni ts dr iving several loads and reduces the effect of capacity on switching time.
Low-Power Series

The low-power gate circuit is shown in figure 4-3.
Typical
switching speed is 33 ns, and power· consumption is 1 mW per
ga te.
Generally, an L suff ix on the element identi f ier nlrnber
indicates the low-power series.
High-Speed Series

Figure 4-4 shows the basic high-speed gate.
Typical switching
speed is 6 ns. Power consumption is 22 mW per gate.
Usually,
an H suff i x on the element identi f ier indicates the high-speed
series.
Schottky Clamped Series

Figure 4-5 shows the basic Schott~y s.er. ies gate.
This ser ies
uses Schottky-barr ier diodes as base-collector clamps.
Clamping the collector prevents a transistor from saturating and
thereby improves switching time.
Switching time is 3 ns and
power dissipation is 20 mW per gate. An 3 suff i){ ·-:>0 the element identifier indicates the Schottky series.

4-10

83323810 A

Vee

INPUTS

[0>-__--'

OUTPUT

Q4
12K

GROUND
9K3

Figure 4-3.

TTL NAND CiI'cuit, Low-Power Series

Low-Power Schottky Series

The low-power Schottky gate is shown in figure 4-6. The suffix
letters LS on the element identifier denote this series of microcircuit.
The LS series offers a happy substitute for the
standard TTL microcircuits, and in fact enjoys the best speedpower product of any of the· five TTL series. Switching time is
typically 9.5 ns per gate . (as against 10 ns for the standard
series), while power dissipation is 2 mW per gate as opposed to
10 mW for the standard TTL gate.

83323810 A

4-11

LOGIC INTERFACE CIRCUITS

Special microcircuits are used to interface different families
of microcircuits. In the case of interfacing TTL (logic levels
of HIGH =+3.3 volts, LOW = +0.2 volt) to EeL (logic levels of
HIGH = -0.5 volt, LOW = 1.7S volts), circuits such as those illustrated in figure 4-7 are used.
TTL PACKAGING

TTL microcircuits are manufactured in several physical config,lrations.
Three common ones are the dua1-in-line packages,
flt:lt paf.:kages, and plug-in packages. These uni ts are hermet ically sealed and have from 8 to 40 pins.
Flat packages and
plug-in packages are available with various numbers of leads.
Figure 4-8 shows an example of each package.

~------~

________.-________oVcc

OUTPUT

470n

GROUND
9K4

Fig u r e 4 - 4 •

4-12

TTL NAND C i r t;: '1 it, Hi 9 h - S P e eo S e r i e s

83323810 A

TRANSISTOR AND SCHOTTKY
BARRIER DIODE CLAMP

SYMBOL FOR TRANSISTOR WITH
SCHOTTKY BARRIER DIODE CLAMP

OUTPUT

--~----------~------.-.------------~l~------~OGROUND
9K5

Figure 4-5.

83323810 A

TTL NAND Circuit Schottky Series

4-13

R2
8K

22K

OUTPUT

R5
21K

R6
1.5K

GROUND
9K6A

Figure 4-6.

TTL NAND Circuit, Low-Power Schottky Series

CD
W

W
CD

....o

TTL ~ EeL DUAL TRANSLATOR
GND

750fl

Ve8
9W121-1

Figure 4-7.

....U1I

TTL/EeL Interface (Sheet 1 of 2)

Eel ----.. TTL QUAD TRANSLATOR

-0
'----+--+-----0
3.4K

3.4K

8500

w
W

N
W
CD

--------------G)

----.-----{~

9W12J-2

Figure 4-7.

TTL/EeL Interface (Sheet 2)

0.77 in
19.5mm

Ql~

~----!lIf--- 0.35 in
8.9mm

5mm

IIS . . . . 7

O.8Sin
\E--21.8mm ~

FLAT

DUAL INLINE
PACKAGE

PACKAGE

Wo
. L_o.185in
u 0 Du
4.7mm

PLUG - IN

PACKAGE
9K8

Figure 4-8.

83323810 A

Typical TTL Packaging

4-17

EMITTER-COUPLED-LOGIC (EeL)

The emitter-coupled-logic (ECL) microcircuit is, by design,
nonsaturating, and therefore avoids transistor storage time and
its attendant speed limitation, characteristic of transistortransistor logic (TTL).
The high speed of ECL microcircui ts
has either or both of two characteristics1 switching rates of
over 50 megahertz and/or gate propagation delays of less than 5
nanoseconds.
In general, the gate propagation delays o:f ECL
logic are approximately 2 nanoseconds.
Some of the salient features of EeL microcircui ts are as follows:
•

High input impedance/low output impedance properties enable large fanout and versatile drive characteristics.

•

Minimal power supply noise generation due to differential
amplifier design.

•

Nearly constant power supply current drain.

•

Minimal crosstalk due to low-current switching on signal
path.

•

Low on-chip power consumption (e.g., less than 8 milliwatts in some complex function chips)

•

No line drivers needed due to open emitter outputs of EeL

•

Capabili ty of dr iving twisted pair transmission lines of
up to 1000 feet in length.

•

Simultaneous complementary outputs available at logic element output without using external inverters.
Logic and Power Levels
Nom
Supply voltage (VEE)
Noise immunity
High output voltage
Low out.put voltage
High input voltage
Low input voltage

Min

Max

-5.2

-0.924

-0.96

-1.75

-1.65
-1.105
-1.85

-0.81
-1.85
-1 .. 475

*Noise immuni ty of a system involves line impedances,
circuit output impedances, propagation delays, and noise
margin specifications.
Noise margin is a dc parameter
calculated from specified points tabulated on an EeL data
sheet for the particular microcircuit in question.

4-18

83323810 A

CIRCUIT THEORY

A typical ECL gate circuit is shown in figure 4-9 and consists
of a differential amplifier input circuit, a temperature and
voltage compensated bias network, and emitter-follower buffering transistors for transmission line driving. To explain
operation of the gate, each of the major sections is discussed
in the following paragraphs.
The differential amplifier is an emitter-coupled current switch
consisting of transistors 01 through OS. The multiple gate inputs provide an OR function (01 through 04) which is amplified
by current switch OS. To understand the gate's operation, assume that all gate inputs are low (-1.7S V and 01 through 04
therefore cutoff). Under this condition, OS is forward biased,
the base being held at -1.29 volts by the bias supply voltage
(VBB) , and its emi tter is at one diode vol tage drop (0.8 V)
more negative than its base (-2009 volts total). The base-toemi tter differential then becomes the difference between the
low logic level (-1.7S V) and VBB (-1.29 V), or 0.34 vol t.
Since this vol tage is less than the threshold vol tage to turn
01 through 04 on, they remain in the cutoff state. The current
through 05 will be about 4 milliamperes with a voltage of -2.09
volts at the emitter nodes of 01 through 04 using an emitter
resistor RE of about-780 ohms.
The emitter-follower outputs- buffer the current switch from
loading and restore output voltages to proper ECL levels. The
OR output is obtained through 08 producing the low-level logic
signal of -1.7S volts. Similarly, the NOR output is obtained
through 07 producing the high-level logic signal of -0.924 volt.
When any or all of the logic inputs is switched to the high
logic level, the appropriate input transistor turns on, a current flows through resistor ReI in the differential amplifier,
and transistor QS cannot sustain conduction due to forward biasing, so is cut off. After translating through the emi tter
followers, the NOR output is a nominal -1.7S volts and the OR
output a nominal -0.924 volt.
The differential action of the switching transistors (one section off when the other is on) produces simul taneous complementary signals at the output.

83323810 A

4-19

DIFFERENTIAL
AMPLIFIER

BIAS
NETWORK

COMPLEMENTARY
OUTPUTS

~
Vcel *-

* VCCI •VCC2 ARE TIED TO GROUND.
SEPARATE LEADS PREVENT OUTPUT
LOADING FROM AFFECTING THE BIAS
VOLTAGE (VBB '

VCC2*

Q8~-..........
RCI
220

RC2
245

907
OR

co
w

W
N

MULTIPLE INPUTS

o
VBB = -1.29V

\..oJ

c:o

.....

NOR

Figure 4-9.

Typical EeL Gate

9WI22

The bias network provides a reflerence voltage (Vss) of -1.29
vol ts. Th is network compensates :for var iations in power supply
voltage and temperature changes to ensure that the bias voltage
threshold point remains in the proper operating region.
LOADING CHARACTERISTICS

The differential input to EeL circuits offers several advantages.
Its common mode rejection feature offers immunity
against power supply noise, and its relatively high input impedance enables any circuit to drive a large number of gate inputs wi thout deter ioration of noise margins.
The dc loading
factor (the number of gate inputs of the same family that can
be driven by a circuit output) 1:or EeL circuits is 90. While
dc loading causes a change in output vol tage levels, thereby
tending to affect noise margins, ac loading increases the capacitances associated with the circuit, and therefore affects
c ircui t speed.
For EeL circui ts, best per formance at fanouts
of greater than 10 will occur with the use of transmission
lines.
The propagation delay and rise time of a dr iving gate
are .affected very li ttle by capaci tance loading along a matched
parallel-terminated transmission line.
However, the delay and
characteristic impedance (Zo) of the transmission line itself
are affected by the distributed capacitance and loading due to
stubs off the line. Maximum allowable stub lengths for loading
of an EeL transmission line vary with line impedance. For example, a transmission line wi th a Zo of the line is changed
to 100 ohms, stubs may be only 2.8 inches (71.1 mm) long.
The input loading capacitance ojE an EeL 10109 is 2.9 picofarads. Therefore, fanouts in a non-transmission line environment
should be limi ted to a maximum of 10 loads due to line delay
increases which in turn limit speed.
UNUSED INPUTS

The input impedance of the differential amplifier used in the
typical EeL ci tcui t is high when the applied signal level is
low. Under low signal conditions, any leakage to the input capacitance of the gate may cause a gradual buildup of voltage on
the input lead, thereby adversely affecting switching characteristics at low repetition rates.
All but a few of the EeL
circui ts con1:.ain input pull-down resistors between the input
transistor bases and the -5,.2 volt power supply
(VEE) •
Therefore, unused inputs may be left unconnected because leakage current is dissipated by the resistor, keepin~ inputs sufficiently negative so that cireui ts will not tr 19ger due to
noise coupled into those inputs.

83323810 A

4-21

Input pull-down resistors must not be used as pull-down resistors for preceding open-emitter outputs.
If an EeL ci.rcuit
(such as the 10116) does not contain input pull-down resistors,
one input of a circuit must be connected to the reference bias
supply voltage (Vss) and the other input to VEE.
WIRED lOGIC

Wired-OR gates can be produced in ECL microcircui ts by wir ing
au tpu t emi t ters together (to max imum of 10) ou ts ide the i r r espective packages. Wired-OR gates can be connected directly to
a bus, also.
Propagation delay is increased by approximately
50 picoseconds per wired-OR gate. To economize on power dissipation, a single output pull-down resistor is used per
wired-OR gate. Normally, wired-OR gates are connected between
gates on the same logic board.
ECl PACKAGING

EeL microcircuits are manufactured in a variety of physical
configurations. Two of the more common ones used for the EeL
microcircui ts descr ibed in this manu,al are the ceramic dual
in-line and the plastic dual in-line cases having both 16 and
24 pins, depending upon the size of the package.
Figure 4-10
illustrates these packages.

COMPLEMENTARY METAL-OXIDE .SEMICONDUCTOR (CMOS)
CMOS microcircuits use four-terminal, enhancement-type field
effect transistors (FETs), the symbol for which is given in
figure 4-11, to form the basic inverter.
As shown in figure 4-12, '8 complementary inverter may be formed
by applying the input signal to the gates of two opposi te-polarity FETs.
In this circuit, a low input signal turns the N-channel transistor 01 off, and turns the P-channel transistor (02) on. The
output is shorted to the positive supply, but virtually no load
current is drawn if the load is assumed to be another CMOS device wi th high-impedance input.
When the input signal. goes
high, 01 is turned on and 02 is turned on. The output is pulled to ground, but no steady-state current is drawn.
Power
dissipation in the circuit is thus limited to the crossover
points as the device changes state, and wi th proper design is
typically 2 nanowatts per gate.

4-22

83323810 A

ADVANTAGES/DISADVANTAGES
Advantages

•

High circuit density

•

High noise immunity

•

Lower power dissipation (2.S nW per

•

High fan-out to other CMOS elements (>50)

•

Logic swing independent of fanout

•

Input threshold is Cl)nstant over wide temperature
(5% vari3tion, typic~l)

7.9mm
~

gat~,

typical)

range

O.84in_~

rm\

O.ISin
4.6mm

3.4mm

16-PIN DUAL INLINE PLASTIC (CASE 648)

O.31in

79mm

-1:::\

O.2in

5mm

16-PIN DUAL INLINE CERAMIC (CASE 620)

Figure 4-10.

83323810 A

9W123-1

Typical TeL Packaging (Sheet 1 of 2)

4-23

Disadvantages

•

Fabrication complex and more costly than TTL or ECL

•

Buffering required ~hen driving several TTL loads

•

Level translation required when driving ECL loads

•

Characteristic complementary output
cludes use of "wired-OR" schemes.

•

Inputs extremely electrostatic sensitive -- require special precautions when handling.

configuration

pre-

0.54 in
13.2 mm

0.61 in
15.5mm

1.265 in
32.lmm

0.2in
-sm;n

24-PIN DUAL INLINE PLASTIC (CASE 649)
0.54 in

~--

0.605in~_j
15.4mm

1.27 in

3~
0.2in

~- 5mm

f~n
3.4mm

24- PIN DUAL IN LINE CERAMIC (CASE 623)
9W123-2

Figure 4-10.

4-24

Typical EeL Packaging (Sheet 2)

83323810 A

GATE(Gl

iJW=

DRAIN(O)
SUBSTRATE (B)
SOURCE (5)

GATE (G)

iItE

DRAIN (0)
SUBSTRATE (B)
SOURCE (5)

N - CHANNEL

P - CHANNEL

9WI24

Figure 4-11.

FET symbof

INPUT

OUTPUT ~

INPUT

1 _____

--1

9WI25

Figure 4-12.

Typical CMOS Inverter

OPERATING VOLTAGES

An additional advantage of the CMOS family is its wide range of
operation voltage (VDn), which may vary fro~ll 3 V de to 16 V
de although, as is shown later, operating speed suffers for the
lower supply voltages. Noise immunity is typically 45% of the
. supply vol t ag e.
The r an']e of i npu t and ou tpu t \1t')1 t~g es i fi
shown below for a Vce of +5 V.
Min
Nom
Max
4.99
5.0
High output voltage
Low output voltage
0
0.01
3.5
5.0
High input voltage
Low input voltage
0
1.5

83323810 A

4-215

INPUT PROTECTION NETWORK

CMOS devices can be seriously damaged if subjected to high
electrical fields in the gate oxide region. Any potential over
about 100 V between the gate and the substrate breaks down the
oxide, resulting in permanent damage.
The input protection
network shown in figure 4-13 protects the CMOS against v,oltages
in the hundreds region, which is normally sufficient for ICs
mounted on a circuit card that is already plugged into a logic-chassis connector.
When removing, replacing, shipping, or
otherwise handling these electrostatic-sensitive cards, special
precautions should be observed to prevent static buildup between the handler and the card. These precautions are outlined
in the maintenance manual for any equipment using such cards.
The CE is strongly advised Against attempting to remove and replace CMOS' ICs on these cardsJ adequate measures to avoid harmful electrostatic discharges during such repair procedures are
simply not realizable in the fie.ld.
The diode-resistor input protection network shown in figure
4-13 is built into every external input lead as part of the
fabrication process.
The circuit, while adding some delay
time, provides protection by clamping positive and negative potentials to VOD and ground, respectively.
(The protection
network is not usually shown in CMOS electr ical schematic diagrams. )
The series isolation resistor, RS, is typically 1500 ohms.
Diodes Dl and 02 clamp the input vol tages between vcc and
ground.
Diode 03 is a useful parasi tic structure resulting
from the diffusion fabrication of RS. The 6 to 7 ns delay of
RS allows excess energy present at the input pin to be diverted through the protective diodes before reaching the sensitive gate dielectric.
Diodes Dl and 02 have a sharp 30-35 vol t avalanche breakdown
characteristic.
positive (breakdown mode) and negative (forward conduction) over-voltage' protection, with respect to
ground when VOD is open, is provided by 01.
Diode 02 similarly provides positive (forward conduction) and
negati ve (breakdown mode) protection wi th respect to VOD when
ground is left open. Both diodes limit the applied voltages to
well within the critical breakdown potentials of the gate dielectric. The avalanche characteristic of 03 and 04 is typically 120 v.

4-26

83323810 A

REPRESENTATIVE CMOS GATES

Figure 4-14 contrasts a 2-input NAND with a 2-input NOR. The
dashed-line boxes enclose the output buffer that is usually a
part of the gate.
Buffering achieves high performance, standardized output drive, highest noise imm'Jnity, and decreased
sensitivity to output loading.

r- -

-- --.

I
I _______
L

•

I
JI

INPUT

OUTPUT
RS
01

9WI74

Figure 4-13.

Diode-Resistor Input protection

TRANS,MISSION GATE

The transmission gate (TG) is a valuable too' in CMOS design.
Two representations of the gate, as found in vendor literature,
are shown below. The symbol on the left is used in functional
diagrams in this manual.

83323810 A

4-27

Voo
A

r------- ---------,

INPUTS
B

OUTPUT

L ______ • _________ J

NOR

;------------------,
,

OUTPUT
A

__ • _ _ _ _ _

--!~~

1--lI--......

,,
I

L ______ _

NAND
9KI4

Figure 4-14.

4-28

Typical CMOS Gates

83323810 A

The two control inputs,' one on t:he top and the other on the
bottom of the symbol, are most usually fed complementary signa1s.
A high on the top control input turns the gate off; a
high on the bottom control input turns the gate on.
A typical use of the transmission 9ate is shown in figure 4-15,
which depicts a positive-edge-tIlggered J-K master-slave FF
(circui t 4027).
Here, four transmission gates are controlled
by complementary Ic10ck signals (G, G). When the clock is low,
TGl and TG4 are on, while TG2 and TG3 are off. This logically
disconnects the Master from the Slave. Gates 3 and 4, however,
are cross-coupled through TG4 (which is on), and the output
state remains stable. Assuming that the Sand R inputs are inactive, TG1 transmits the state of the J and K inputs to Gates
1 and 2.
When the clock goes high, TG2 al1ld TG3 turn on, while TGl and
TG4 turn off. Now gates 1 and 2 are cross-coupled through TG2,
and latch into the state they held when the 10w-to-high clock
transition took place.
With TG3I on, the logic state of the
Master section (output of Gate 1) is fed through an inverter to
the 0 output. Simultaneously, the 0 output receives the double
inverted output of Gate 1.
OPERATING SPEED

propagation delay and rise/fall times are functions of the device temperature, operating voltage, and output load capacitance.
Delay and transi tion times increase approximately 1/4
of one percent for each degree Celsius above +25°C, and decrease approximately as the inverse of the operating vol tage.
For a given VDDL' the rise, fall, turn-on and turn-off times
are about equal for a load capacitance of 25 picofarads and increase at different rates above that point.
The table below
gives representative figures.
UNUSED INPUTS

Unused CMOS inputs should be connected to an appropriate logic
voltage, depending upon the function of the logic device.
Unused NAND lnputs should be connected to the +5 V bus, unused
NOR inputs to ground.
This prevents the input protection
structure from floating to some undesired voltage level that
prevents the de~lice from functioning properly.
In addition,
"floating" inputs may be subject:ed to electrostatic potentials
that will permanently damage the device.

83323810 A

4-29

w
o

MASTER

SLAVE

TG
J

GATE 1

3
G

TG
1

TG
4

-cf>

C~~CK_ _ _[>o~1

XMSN
GATE
NO.

CLOCK
G G

GATE
STATE

ON
OFF
OFF

1.4

TG
2.3

9K30

Fi]J~e

4-1S.

US~

of Transmission Gates in Flip-Flop Circuit

DELAY/TRANSITION TIMES FOR VARIOUS OPERATING VOLTAGES
Time
Measured

Voo = 10 V

VOO = 5 V

Voo = 15 V
units

Load Capacitance
15

100

Turn off/on 60

120

200

Fall

130

220

110

Rise

220

*320

170

120

CMOS/TTL INTERFACE

The majority of CMOS devices will not sink the 1.6 rnA required
for the logical zero input (+0.4 V) to a TTL device. The sinking capabi1i ty is usually increased by using a 2- or 4-inJ?ut
NOR gate (CMOS) to drive the TTL input. For multiple TTL 1nputs, special CMOS buffers are used.
Sourcing the ~A-range
needed for a TTL logical one is no problem for the CMOS device.
When coverting from TTL to CMOS, it is important that the TTL
output device does not source other TTL circuits, but only the
CMOS input.
(Sourcing 400 ~A for a TTL logical one drops the
TTL output to about 2.4 V, considerably below the 3.5 V CMOS
threshold required for a logical one~) Sourcing the 10 pA for
a CMOS logical one resul ts in a TTL output of around 3.6 V.
This is adequate, but provides little noise margin. For this
reason, a 2000-ohm pullup resistor is usually inserted between
the TTL output and Vcc.
CMOS/ECl INTERFACE

The -5.2 V typical for an ECL supply is easily handled by a
CMOS device. If higher negative voltages are advisable because
of required CMOS speed, a diode clamp on each ECL input is required to prevent the input fro:m going below the -5.2 V ECL
supply.
Level translation is required when going from ECL to CMOS. The
800-mV output swing of an ECL device is not sufficient to drive
a CMOS input, so a pnp transistol~ is used (figure 4-16). A diode in ser ies wi th the transistor's emi tter provides a reverse
bias of about 900 mV, which is beyond the output voltage typical of an ECL logical one (-0.924 V). The transistor switches
from about -0.9 V to -5.2 V, which is well wi thin the -1.7 V
typical for an EeL logical zero output.

83323810 A

4-31

Eel

-5.2V
(VEE)

Vss

VSS

9K31

Figure 4-16.

ECL-To-CMOS Interface

CMOS PACKAGING
CMOS microcircuits are manufactured in dua1-inline ceramic
(DIC) and dua1-inline plastic (DIP) packages with 14, 16, or 24
pins.

Figure 4-17 shows the various packaging dimensions.

OPERATIONAL AMPLifiERS
INTRODUCTION

operational amplif ier (op amp) is a high-gain integrated
circuit that can apply signals ranging in frequency from dc to
its llpper frequency limit, which may be mor~ chan one meg,-=th~rtz.
It is used frequently in a uis~ drive -39 a linear 3m·plifier of servo analog signals.
Because of its versatilitj,
however, it has multiple applications.
The

4--32

83323810 A

....~I'--_""

ffim[He\
0.31 in _

0.84in _ _ _

""'2i:3mm

16- PIN DUAL INLINE PLASTIC (DIP) (CASE 648)
O.26in
nm;--

~~~
7.9mm

If~1

.9.J!l!!..

4.6mm

14-PIN DUAL IN LINE PL~STIC (DIP) (CASE 646)
0.56 in

.Q..§Qln. --1'I"'~--j

IS.2 mm

;,---- \

O.2in
5mm

3.6mm

24- PIN DUAL INLINE PLASTIC (DIP) (CASE 709)

Figure 4-17.

83323810 A

9W126-1

Typical CMOS Packaging (Sheet 1 of 2)

4-33

O.3lin
7.9mm

j
t:.

19.8mm

O.2in
5mm

4mm

16- PIN DUAL INLINE CERAMIC (DIC) (CASE 620)

.22!tm--19.9mm

O.2in

Smm

14-PIN DUAL INLINE CERAMIC (OIC) (CASE 632)

..Q.6~J.!'
15.8mm

--t----=1
r===1

____ 9~i55~_

1.215in
--31.Smm

.3.~mm

... -~ ...

O.S6in

~--

24-PIN DUAL INLINE CERAM'C (OIC) (CASE 6841
:jW~26-2

Figure 4-17.

4-34

Typical CMOS packaging (Sheet 2)

83323810 A

The op amp approaches the following characteristics of an ideal
amplifier:
1. Infinite voltage gain
2. Infinite input resistance
3. Zero output resistance
4. Zero offset: output is zero when input is zero
5. High bandwidth frequency response
BASIC CIRCUIT ELEMENTS

Figure 4-18 is a simplified schematic of a typical op amp with
its basic feedback network. Detailed circuit analysis information may be obtained by referring to the manuals prepared by
the applicable manufacturers.
INPUT STAGE

All op amps utilize a differential amplifier in the input
stage. This circuit may be relatively simple, as shown, or may
consist of multiple circui ts wi th FETs or Darlington-connected
transistors. The advantage of thi,s type of amplifier is that
it amplifies the difference between the two input signals. For
example, if 10 mV are applied tC) the non-inverting input while
9 mV are applied to the inverting input, the 1 mV difference is
amplified. The amplification, which may be a voltage gain of
up to 100000, is linear until the op amp saturates or until increasing frequency causes rolloff.
,If the same input is applied to both input terminals, the signal is referred to as the common-mode input signal.
In the
precedin9 example, 9 mV is the c:ommon-mode input, while 1 mV is
the differential input.
In the ideal op amp, the output is
zero with identical inputs; only the difference (1 mV in this
case) is amplifi.ed. Since the common-mode input is not amplif ied, signals common to both, such as noise and hum, are cancelled.
SECOND STAGE

Not all op amps have a second stage. If used, however, it may
contain additional amplification and level shifting.

83323810 A

4-35

C I
I

r--~,
,

,'"

':---,
...
I

I
I

I
•

INItUT STAGE

2 .... STAGE

OUTPUT STAGE

\/+

\/4

\/3

\/-

NOTES; (;\,

\V TO COMMON CONSTANT-CURRENT SOURCE.

NOT APPLICABLE TO ALL TYPES.
REFER TO MANUFACTURER'S DATA SHEET.
FOR BALANCED INPUT IMPEDANCE,
R3= RI R2

Rt+R2

Figure 4-18.

4-36

9Wl73

Simplified Op Amp Schematic

83323810 A

BASIC CIRCUIT FUNCTIONS

Resistors Rl and R2 provide degenerative feedback to control
the overall gain of the circuit. As long as the ratio R2/Rl is
low compared to the open loop gain at the operating frequency,
circuit gain is independent of the characteristics of the specific op amp.
Rapid analysis of this circuit is possible if two basic principles of op amps are assumed:
1.

Insignificant current flows into either
therefore it is assumed to be zero.

input terminal;

The differential voltage (V3) is insignificant and therefore is assumed to be zero.

Rule 11 may be presumed since the input impedance is. very
high. As a result, all current (11) entering the summing point
must leave it (12). These currents are:
11 = Vl/Rl
II = -V4/R2
The minus (-V4) indicates that the output is the inversion of
the input. Since no current flows into the op amp, II must be
equal to 12. By Ohm's Law:
V4/Vl = -R2/Rl or V4 = -VI (R2/Rl)
Therefore, the output is simply the ratio of R2/Rl. This linear output/input relationship holds true as long as the input
(VI) is not of sufficient amplitude to saturate the op amp.
Resistor R2 is frequently shunted by a capaci tor.
This controls the roll-c)ff character ist:lcs of the circui t where the
full op amp bandwidth is not required. The effective feedback
to the input is the resistance of R2 in parallel wi th the capacitive reactance of Cl.
Capacitive reactance decreases as
frequency increases, the effective impedance of R2/Cl decreases
to reduce overall gain.
If Cl is large enough, its ~harging time becomes more of a factor. The output cannot react as fast as the input may change.
This is the integrating or low pass function.
For example,
doubling the frequency halves the gain.
The output is the
mathematical integral of the input when the effects of Cl predominate over the effects of R2. Thus, if the input voltage is
proportional to veloci ty, the output is proportional to distance.

83323810 A

4-37

Since there is actually a slight current (measured in nanoamperes) entering the differential stage, the difference or unbalance between the two input currents would be amplified.
This results in an error known as dc offset; that is, the output would be non-zero with a zero common-mode input. If, however, the currents are made equal, that is, the same input impedance is presented to both, they are therefore common-mode
and are cancelled. Resistor R3 is selected to balance out the
offset voltage and current by making the impedance to ground of
the two inputs equal.
Rule 2 holds true as long as feedback is provided by R2 or its
equivalent. As long as the amplifier is not saturated, it will
adjust its output voltage to maintain the differential voltage
V3 at zero. Therefore, the summing point is at V2. Since V2
is usually at ground potential, the summing point is also at
ground. This is a virtual ground; that is, it is at ground potential even though there is no connection between this point
and true ground. If the summing point is monitored with an oscilloscope, little or no signal can be observed.
Typical op amp circuit functions are illustrated in figure 4-19.
SCHMITT TRIGGER CIRCUITS

Operational amplifiers can also be connected in the Schmi tt
trigger configuration (figure 4-20). Note that the degenerative feedback path is not provided. It is replaced by a regenerative feedback path.
This is the open-loop configuration:
if the voltage at the non-inverting input is greater than the
voltage at the inverting input,' the output is saturated at its
most positive value.
Reversing the inputs causes. the circuit
to slew (change) at its maximum possible rate to saturate negatively.
All Schmitt triggers have hysteresis. Hysteresis is supplied
by regenerative feedback from the output to the non-inverting
input.
Consider A376 of figure 4-20.
Assume the voltage at A is
zero. A voltage divider network (not shown) sets point B at
+1.28 V). The differential voltage is then zero, so the output
starts to switch to a zero-volt output. However, there is now
a path from Y to B; the B input becomes less positive than the
A input. The output very quickly saturates negatively.
With about -14 V available at Y, the voltage at B is reduced to
+1.10 V. The input must now swing to less than +1 . 10 V for the
output to change its state back to positive saturation.
The remaining circuits work in a similar manner .

4-38

83323810 A

V ,N

INV£RTING
AMP

IN VE RTING
AMP WITH
REFERE NCE
VOLTAGE

OUTPUT (0

SYMBOL

CIRCUIT TYPE

OBSERVE

ALGEBRAIC SIGNS
COMPUTING

'lOUT =0

-V

REF

NON
INVERTING
AM PLI FIER
'lOUT =

IF· V U~= VREF

+v(
R3
)
R3 + R4
-

R, + R 2 )
-------RI

JR,

SUMMING
AMPLIFIER

~,~

__~~

R,
'lOUT

[~
R

(V + V + V )]
I
2
3

NOTE S:

MINUS

SIGtll(-}

USED

SYMMETRICAL

Figure 4-19.

83323810 A

INDICATES

PROVIDE
ABOUT

THAT

OUTPUT

FEEDBACK

GROUND.

INVERTED

KEEP

OUTPUT

9W127-1

Op Amp Circuit Functions (Sheet 1 of 4)

4-39

CIRCUIT

TYPE

SYMBOL

OUTPUT0

INVERTING
AMPLIFIER
WITH OUTPUT
LlMITING

~ "Z

± "OUT

INTEGRATING
AMPLIFIER

"OUT

- fV 1N dt
R, c

Y,N

= -

CONSTANT,
Y,N
RIC

INTEGRATING V IN
AMPLIFIER CONTROLLED
BY

X TIME

VOUT

P - C HAN N E L
J F E T

( A ) IF

VOUT

( 8 ) IF
V

OUT

°v
IS

+ 14 V

= . ._ - - )V, N dt
", c

NOTES.

(i)

MINUS

SIGN ( - )

USED

Fi~~re

4-40

SYMMETRICAL

INDICATES

PROVIDE

ABOUT

4-19.

THAT

OUTPUT

FEEDBACK

INVERTED.

KEEP

OUTPUT

9W127-2

GROUND.

Op Amp Circuit Functions (Sheet 2)

83323810 A

CIRCUIT TYPE

FUNCTION

SYMBOL
R2
...

R,
DIFFERENTIAL

AMPLIFIER

d/dt

-'"'
"-J

R,
...........

(V2 -

R2
"OUT

:..~= Rz

...----t----VOUT

"OUT

",N

" 0-IN

"OLTAGE
FOLLOWER

~ r>OV

V I 0-

OPEN LOOP
( CO,.. PARATOR)

V 2 0-

"OUT

=
VOUT = OV
"OUT = - VSAT

< YZ

= V2

:> "2

= + V SAT IF

= V2

+ VSAT

"OUT

I11II...I
."

V I 0--

SATURABLE

.J""'l,
yy

L>OV

COMPARATOR

V OUT

VOUT

V OUT =
"OUT

NOTE:

(1)

"OUT IS __
LOOP

ACT_U~LLY_. _ P_RO~UCT

VOLTAGE

GAIN

(A V )'

.,,, I

AV::::

, -

I. "2 , X

lo.oeo.

"oUT

AMPL I FIER
CANNOT

EXCEED THE SATURATION
VOLTAGIE (V SAT ) '
WHICH
Z
VOLTS
LESS
THAN
THE SUPF)LY VOLTAGE.

V, )

-------

R Z USED TO PROVIDE
SY MM E T It. C-A L--- ABOU T

fEEDBACK

KEEP

OPEN

ACTUALLY

ABOUT

OUTPUT

GRO UN D.
9W127-.~

Figure 4-19.
83323810 A

Op Amp Circuit Functions (Sheet 3)
4-41

SYMBOL

C1RCUIT TYPE

v, r.
-

SA TU R ABLE
COMPARATOR

FUNCTION

......
......

,..

""" L>OV
\lOUT

'F V,

'12

\lOUT

= 0"

\lOUT

= -\lSAT

IF V,

> "2

(0
NONL 'N EAR
COMPARA TOR

OUT

= \lZ

\lOUT

VOUT = OV
\lOUT =

NO TE:

"OUT IS
LOOP

ACTU ALLY

VOL TAG EGA I N

EXCEED
2

PROOUC T

THE

VOLTS

( A V ).

SATURATION

LESS

THAN

I I- I I
V,

A V :::

'0, 0 0 O.

VOLTAGE
THE

SUPPLY

(V SAT ) '

\1'2

FIEI~ OPE~

'Iou T

CAN NOT
IS

= "2

AMPL I

WHICH

IF V,

ACT U ALL Y'

ABOUT

VOLTAGE.

9W127-4

Figure 4-19.

4-42

Op Amp Circuit Functions (Sheet 4)

83323810 A

< 0.IOV: Y

> 1.2IV=Y
Y

---+

A'~~-"';"'----:---\--------""""-

\
\

< O.30V: Y

> 0.10 V:Y

\
\

11'1
Y

---.

AfF
+ 0.30 V

<-L.28V:Y

>-1.10'1 :Y

B{+ 1.28

---Il1o

I. '0

\Y{ + 14
- 14

\
Y

n'--l:

\
B

liRH

-',2ev

< - 0.10 V: Y
> -0.30 v:Y

_~~~~~ ~y 1+

SWITCHES

WHEN

=B.

DIVIDER

"----

DIVIDER. se.E BELOW.

\
\

WITH
DIODE IS ON.
Y HIGH
0 FEEDBACK
THRU olODE DRIVES
I

POSITIVE.

TYPICAL DIVIOER

.'1-R2

VREF:r +V

(~)

\a{ ~

\{~

I
I
I

0,30
0.10

14
14

RI + R2

Figure 4-20.

83323810 A

ONLY.

V REF WORE

Y HIGH I DIODE tS '")F'F .
SUPPLIED
BY VOLTAGE

WITH
V REF

® vAEF SU PPL lED By RESISTIVE
VOLTAGE

\
NOTES

I
1

I
I
I
I

9K28A

Op Amp Used as Schmitt Trigger

4-43

LOGIC SYMBOLOGY

SECTION 4B

LOGIC SYMBOLOGY

GENERAL
The logic symbols used with the data sheets in section 3 of
this manual follow MIL STD 806-B/C. In addition to the symbol
outline itself, a symbol consist~J of a function name, var ious
modifiers and/or indicators, pin numbers, an element identifier, and a location code that specifies the physical placement
of the microcircuit on the logic module or printed-circuit
board. These items are placed within or adjacent to the symbol
outline, as shown below.

MODIFIER

AN NUMR..

~.~tTIVE - - - - - - - 9
INDICATOR

NO INDICATOR MEANS
A HIGH·ACTIVE
SIGNAL (BINARY)

FUNCTION

1-~rut:E:"~~~R
e

COMPTR
310"

J.Q! .!..
{-LOCATION
CODE

DENOTES SECTION IN
MULTIPLE-SECTION
ELEMENTS

SIGN (ANALOG)
INDICATORS

ANALOG INDICATORS
(USED ONLY TO AVOID CONFUSION
WITH .NA"'" SIGNALS)

83323810 A

4-45

The function name is usually omitted from distinctive-shape
symbols (see the amplifier above), but may be included to further define the general function implied by the distinctive
shape:

The pin number in parentheses (10) denotes a pin that is common
to other section(s) of the microcircuit.
In this case, the
symbol for the "A" section of the driver would show pin 10
without the parentheses.

SUPPLEMENTAL NOTATION
In addition to the standard 806-B/C logic-symbol modifiers -D, R (CLR), LD, Q, weighting modifiers, etc. -- and which are
discussed in the individual microcircuit descriptions, the data
sheets in section 4C employ the additional symbol notations reviewed below.
MODIFIERS

4-46

An enable signal.
A viable output from the microcircuit depends upon the presence
(active
state) of the G modifier. Hence, G i,s oft:en referred to as a dependency modifier.

J,C

A differential input, or a differential output,
respectively.
The microcircuit derives the differential by comparing the input signals appearing at the two pins spanned by the bracket, or by
applying the generated differential signal to the
two bracketed output pins.

The heavy vertical bar is a mnemonic device to
aid in distinguishing line drivers and receivers
from other microcircuits using the same distinctive-shape (amplifier) symbol.
The bar always
appears within the symbol (as do all modifiers).
It is near the input (left) side of the symbol
for receivers and near the output side (right)
for drivers.

83323810 A

INDICATORS

Except for the analog sign indicators shown below, indicators
appear in or on the signal lines just outside the logic symbol,
but as close to it as practical without interfering with pin
numbers.

-I-

Non-standard logic level:
The slash on an input
or output line identifies a binary level that
differs from that ~considered standard.
(Refer to
standard levels for TTL, ECL, CMOS as given in
sec tion 4A.)

+.-

Analog sign indicators:
The plus sign indicates
the normal (non-inverting) analog input' or outputJ the minus sign identifies the inverting input or output.
Analog signals most frequently
appear in pairs. When they do not, only the inverting signal (-) is identified; the lack of a +
indicator, then, implies a non-inverting input or
output.

-A-

Analog signal:
The inverted "Un (input or output) on a signal line is used only if confusion
between analog and digital signals might otherwise arise. It is not used, for example, in conjunction with the + and - modifiers that in themselves define a signal as analog.

-#-

Binary (digital) logic:
This symbol differentiates binary from. analog signals (input or output).
It is used only if confusion might otherwise arise.
Open-collector output:
If the open-collector
output line is continued on another diagram
sheet, the diamond may be repeated just to the
left of the off-sheet indication. This serves as
a reminder that the pull-up resistor (usually
part of a wired-OR configuration for which the
diamond is the ,ANSI representation) is shown
elsewhere.
(A microci rcui t
elemen t
can only
drive an open collector lowJ the high level must
be provided by a source outside the element.)

-II

83323810 A

Dynamic Active State (positive): This represents
"the transi tion from the inactive to active static
state of the input (not merely the presence of
the active static state).

4-47

Dynamic A~tive state (negative): This represents
the transition from t~~ active to inactive static
state of the input (n·:')t merely the presence of
the inactive static state).

FUNCTION NAMES
The following list identifies the function names found ~~ithin
the logic symbols on the data sheets of section 4C. Abbreviations are those approved by ANSI Yl.l (1972).
Functioll (lames
that are not a!::>breviated within the symbol (e.q., ADDER) have
been omitted.
COMPTR

Comparator

CNTR-4

counter (4-bi t)

CUR AMP

Operational Curre~t

0/1\ ':-:ONV

Digital-to analog Convert~~

DCDR

Decoder

DRVR

Dr 1tIer

E COMPTR

Voltage Comparator

FF'

Flip-flop

MUX

Multipl~xer

Multivlbrator

rn VR

Voltage Regulatoi (The regulated output-voltage
value replaces "m n . )

OP AMP

Operational Amplifier

RCVR

Receiver

tSR-4

Shi ft Reg ister (4-bi t) •
(The arrow direction
here indicates a right -,- or down -- shift.

Single-shot (also One-shot)

n Gate
¢ f DET

Analog Gate

4-48

~mplifier

Phase-frequency Detector

83323810 A

DATA SHEETS

INTRODUCTION

This section contains a cream-colored divider sheet sAp.ltatin)
the information into two subsections:
1.

Introductory remarks.

Data sheets arranged by element

Identifi~r.

In subsection 2, the element identifier also appears as a page
number at the bottom of the data sheet.
Speed variations (H,
L, LS, S, etc.) are shown on the same page as the basic circuit.
DATA SHEET INTERPRETATION
~ll

the data

.sheets

in this

section contain

th~

following

kin.1.3 of information:

LOGIC SYMBOL - The 806-B/C symbol for the high-active
version of the microcircuit and, where applicable, the
alternate low-active version.
Pin numbers are included
as !.)art of the symbol.
Special notations to clarify the
'lar ious input and output functions are added when helpful, but are not to be construed as part of the symbol.

nESCRIPTION - An explanation of the function or fUlv::tionc;
performed by the microcircuit.

NOTES - Helpful information, such as:
•

Vendor reference number

•

Package pin configu·ration.
Defines pins used for.- (~x
tarnal voltage sources
(VC~,
VEE, GND, etc.)
and
keys, sl.)ts or marks Ilsed to orient'"'the microcirC1Jit.

In addition, the following information
dual data sheets, when applicable:

83323810 A

included on indivi-

4-49

DATA SHEETS

SECTION 4C

FUNCTIONAL DIAGRAM - Basic logic symbols (NAND, NOR, FF,
etc.) arranged to show the internal logic of the microcircuit.

TRUTH TABLE - A table showing the state (s) of the microcircuit's output for varying input conditions.

TIMING DIAGRAM - Used to clar ify complex
tionships between inputs and outputs.

timing

rela-

DATA SHEET LIST

The list on this page shows the order in which the data sheets
appear, and also provides a quick reference to the family (TTt,
ECL, CMOS) to \<lhich ?\ particular microcircuit belongs.
If a
circuit requires more than one data sheet, the number of sheets
is given in parentheses.
TTL
140
141
143
145
146
148
149
158
159
161
162
164
172
173
175
176
182
188
191
195
200
'202
208

4-50

OP AMPS
300
301
306
307
309
315
316
320
322
326
327
329
330
331
332/353
333
338
339

TTL

EeL

500
501
519
520
521
527
538
581
916
926

10102
10104
10105
10106
10116
10125
10131
12040

986

CMOS

4001
4011

4017
4023
4027
4049

83323810 A

DESCRIPTION
Element 140 is a 4-section
(quad), 2-input, positive NAND
gate.

140
3
(A~
xxx
(8)

(e)

NOTES:
1.

Element identifier and
location (xxx) repeated
for each section.

=r=r2

Vendor identification:

Element

. Vendor Number

140

7400, 9002

l40H

74HOO

140L

74LOO

l40LS

74LSOO

l40S

74800

~
140

xxx

Package pin configuration.

~
11

LOGIC SYMBOL
1

14 Vee

12
11

4
6

10
9

GNO 7

TRUTH TABLE
A

140
Sheet 1 of 1
83323810 A

4-51

DESCRIPTION
Element 141 is a 3-section,
3-input, positive NAND gate.

( A ) - -.....
(8) _ _...
2

141

xxx
(C) ____1....
3

NOTES:
1.

Element identifier and
location (xxx) repeated
for each section.

Vendor identification:

Element

Vendor Number

141

7410, 9003

141H

74H10

141L

74L10

141L5

74L510

1415

74510

----,:1

~::I

}OR

package pin configuration:

TRUTH TABLE
A

14 Vee

5
6

10
9

GND 7

~ )~~

~>LOGIC SYMBOL

141
Sheet 1 of 1

4-52

83323810 A

DESCRIPTION
Element 143 is a 2-section,
4-input, positive NAND gate.
2

NOTES:

143

xxx

Element identifier and
location (xxx) repeated
for each section.

Vendor identification:

9
10

Element

Vendor Number

143

7440, 9009

143H

74H40

143S

74840

____
1....
31-----

package pin configuration.

1
2

3
4

O~ID

5
6
7

14 Vee
13

12
11
10

9
8

LOGIC SYMBOL

143
Sheet 1 of 1

83323810 A

4-53

DESCRIPTION
Circuit 145 is a dual, expandable AND-OR-INVERT gate. The
second section of this circuit
is expandable. If not expanded, pins 11 and 12 are open.

(C)

NOTES:

CO)

Element identifier and
location (xxx) repeated
for each section.

If not used, expander
pins may not be shown.

Vendor identification:

Element

Vendor Number

145

9005

145H

74HSO

(B)
(E)

(A)

~6~_(E)

Package pin configuration.

14 +Vcc

5
6

10
9

GND 7

8
TOP
VIEW

LOGIC SYMBOL

145
Sheet 1 of 2

1···54

83323810 A

TRUTH TABLE

H H

H L

H H

= LOW; H = HIGH; Y = DON'T CARE.

For non-expandable section, or if
expander inputs (X,X) are not used,
disregard shaded portion of Truth
Table.

145
Sheet 2 of 2

83323810 A

4-55

DESCRIPTION
Element 146 is a six-section
(hex) inverter.
NOTES:

Element identifier and
location (xxx) repeated
fo~ each section.

Vendor identification:

Element
-----

Vendor Number

146

7404, 9016

146B

74H04

l46L

74L04

146LS

74LS04

1465

74S04

3•

package pin configuration.
1

14 Vee
13

4
5
6

GND 7

LOGIC SYMBOL

10
9

146
Sheet 1 of 1

4-56

83323810 A

DESCRIPTION
Element 148 is a quad, 2-input,
positive NOR gate.
NOTES:
1.

Symbols may appear separately.

Vendor identification:

Element

Vendor Number

148

7402

l48L

74L02

l48LS

74LS02

148S

74S02

Package pin configurationo

+vcc

~vW~
7 GND

~:) >~4
~:) >~IO_

__. . -.:~ ) >~13__
OR

-------:...d~~~ )...,:1----~:d

)~4

_____:d )~IO_
------:~~d
LOGIC

)~t3~____
SYMBOL

148
Sheet 1 of 1

83323810 A

4-57

DESCRIPTION
The 149 circuit is a quad,
2-input, Exclusive OR gate that
performs the function Y = AS +
AB. When the input states are
complementary, the output goes
to the high level.

(A)
(B)

NOTES:
1.

Element identifier and
location (xxx) repeated
for each section.

Ven00r identification:

Element

7486

149H

3021

149LS

74LS86

1498

74586

xxx

::) ) )

Vendor Number

149

:) ) 14;)
:) ) )
1:) ) )

(e)

(A)~
(B)
2
......

Package pin configuration.

5
1

14 Va;

5
6

GND 7

TRUTH TABLE
(ANY SECTION)
A

~1132'--__'wI

...!lQ-L

LOGIC SYMBOL

149
Sheet 1 of 1

4-58

83323810 A

DESCRIPTION
The 158 circuit is a 4-bit synchronous binary counter. This
circuit can be preloaded with
data at the data inputs when
the load input is low. This
disables the counter and enables the data inputs. Input
data will be transferred to the
outputs the next time the clock
input has a low to high transition.

CNTR-4

168
xxx

IOATA {
INPUTS

In order for the counter to
tLOAO)
count, the load (pin 9), clear
(CLOCK)
(R), and P and T enable inputs
must be high. A low level to
(CLEAR)
the clear input will clear the
outputs to low level regardless
of the level to any other input.

(CARRY
OUT)

I
R

When P is low, the clock input
is disabled so that the counter
can not count. When T is low,_
the clock input and carry output are both disabled.

COUNT

ENABLES

NOTES:
1.

Vendor identification:

Element

vendor Number

158

74161, 9316

158A

74161

158LS

74LS161

package pin configuration.

GND

2
3
4

15
14
13

11
10

•
•

+Vcc

9
TOP
VIEW

158
Sheet 1 of 3

83323810 A

4-59

PIN
I

(CLEAR)

9 (LOAD)

Jrt-_ _ _ _ __

l}NPUTS

2 (CLOCK)
7 (ENABLE p) _ _
~------

10 (ENABLE T)

::1aUTPUTS
I

(TC CARRY)

--.J,

,-I_ __

::-:

,,'-_ __

/ 0 t12/13 14 15 0 I 2/

= DON'T

CARE
CONDITION

CLEAR

.
/.--COUNT
@
PRESET
TO 12

•
INHIBIT
COUNT

®
NOTES:

® MODE SELECTION WITH POSITIVE-GOING CLOCK IS:
PINS

7 a 10

MODE

COUNT UP

NO CHANGE

PRESET

® PIN 15 IS HIGH WHEN ALL OF THE FOLLOWING
PINS ARE HIGH: 10, II, 12, 13, AND 14.
© ILLUSTRATED ABOVE IS THE FOLLOWING:
I. CLEAR OUTPUTS TO ZERO
2. PRESET TO BINARY 12
3. COUNT TO 13, 14, 15, 0, I AND 2
4. INHIBIT

PIN(S)
I

2
3,4,5,6

7
9
10
11,12,13,14
15

FUNCTION
MASTER RESET (ACTIVE LOW) INPUT (CLEAR)
CLOCK ACTIVE HIGH GOING EDGE INPUT
PARALLEL INPUTS
COUNT ENABLEPARALLE L INPUT
PARALLEL ENABLE (ACTIVE LOW) INPUT
COUNT ENABLE TRICKLE INPUT
PARALLEL OUTPI'TS
TERMINAL COUNT OUTPUT (CAR RY)

TIMING SEQUENCE

158
Sheet 2 of 3

4-60

83323810 A

LOAD~
CLOCK

DATA A

CLEAR

D-

~
3

.()

tJ-p

K CLR

I
0

D-J

"'U

~ .r

L.J

DATA

4
B0

~),

K CLR

D-J
--.

J
I

DATA

5
C0

12
-00 C

"'..I" .r

~-r

CLR

D-J
-~

COUNT
7
ENA8LE P
DATA D

10
COUNT
,...
ENABLE T ...,

~
r-

CLR

0..-

CARRY
OUTPUT

FUNCTION DIAGRAM

158
Sheet 3 of 3

83323810 A

4-61

DESCRIPTION
The 159 circuit is a synchronous 4-bit shift register capable of shifting, counting,
storage, and serial code conversion.

+ SR·4
159
xxx

SERIAL{
DATA
INPUTS

Data entry is synchronousJ the
outputs change state after each
low to high transi tion of the (LOAD/SHIFT)
clock. When the load/shift input is low, the parallel inputs
(CLOCK)
determine the next condition of
the shift register. When the
load/shift input is high, the
shift register performs a one
PARALLEL
bit shift to the right, with
DATA
data entering the first stage
INPUTS
flip-flop through the J-K (serial) inputs. By tying the J
and K inputs together, D-type
entry is obtained (see truth
table).
A low level to the clear input
will clear the outputs to a low
level regardless ~f the levels
to any input.

2 J

°A

9 LD
10

°B

°c

4 DA

°0

15
14
13
12

~ 0!1-

5 DB

6 DC
7

DO
R

(RESET)

LOGIC SYMBOL

159
Sheet 1 of 4

83323810 A

NOTES:
1.

Vendor identification

Element

Vendor Number

159

74195, 9300

l59LS

74LS195

2. Pin Names
pin

Function

Master Reset (clear)

First stage J input

First stage K input

4,5,6,7

Parallel data inputs

Load/Shift control

O(NOCHANGE)

I (TOGGLES)

Clock

1::,13,
14,15

Para.lle1 outputs

OUTPUT PIN

output
(12) for last stage

INPUT PINS

C~plementary

package pin configuration.
~

16 +Vcc

GND 8

9
TOP
VIEW

159

Sheet 2 of 4

83323810 A

4-63

aD 00

PINS- 15

...---t--I R

.......---t--I R

CLR

1213 14

CLR

~-+---fR

10
7
5
6
0
B
C
SHIFTI ~ _A_ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - - - - . . . . : . - - - - - - - - - ClK
LOAD
SERIAL
PARALLEL

w
w
w

CONTROL INPUT

CLR

INPUTS
FUNCTIONAL DIAGRAM

co
~

159
Sheet 3 of 4

PIN
I

CLEAR

9 LOAD I SHIFT

L~
I

--1',
INPUTS

--.J:,

~
---1;
;
I

10 CLOCK
I

________

~
____

~_~~~

1
I \

...-1_ _

:~III
I . I ~I------------~----

--------~I.~~I~------------I

010

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ J

: :

__~r~~-------------

------~:~
~
I

~I------__--------~

OUTPUTS

--------r---------------I ,
I

--~,~--~---~~
~
~_____~'------------------~__~__r___

CLEAR LOAD

NOTES:

®
®
©

SHIFT

ENTER SERIAL DATA AND SHIFT

(!)

Parallel data entered v:~ A,B,C,D inputs by pin 9 low
and positive-going signal on pin 10.
Data shifts down (Pin

l5-~Pin

14, etc.) with clock.

Serial data entered intooJ-K inputs by pin 9 high and
positive-going clock. Pin 4 input inhibited because
pin 9 is high. Outputs follow Truth Table shown below.
(Were J and K tied together, o~tput at pin 15 would
track the J input with no deviation from the Truth
Table. )
159
Sheet 4 of 4

83323810 A

4-65

DESCRIPTION
The 161 circuit is a monostable
retriggerable multivibrator
that provides an output pulse
whose duration is a function of
external timing components.

2
3

xxx

Input pins 3 and 4 trigger on
the positive going edge of the
-L:
input pulse and pins 1 and 2
~cx
trigger on the negative going
input pulse. The 161 circuit
V«.4
-will retrigger while in the
R
pulse timing state (pin 8
x
high); the end of the last
LOGIC SYMBOL
pulse will be timed from the
last input.
OUTPUT PULSE
FOLLOWS:

NOTES:

substitute delay period
for 'M'

Vendor identification:
9601

package pin configuration.
1

14 +Vcc

12
11

4
5
6

GNO 7

161

WIDTH (t) IS DEFINED AS

t =0.32 Rx ex ~ + ~.:

Rx IS IN knt ex IS IN pF. t IS IN ns

TOP
VIEW

161

Sheet .1 of 2

4-66

83323810 :A

:L_J____--.--cf..-,.
__q_-f
3--I

I
I

4.J

AETAIGGER

I
I

I
I
I

8::[ r* I
61._. . .
*
I

I
--1111

f.4-- It
I

PULSE WIDTH DETERMINED BY
RC TIMING NETWORI<

TIMING SEQUENCE
TRUTH TABLE
INPUT PINS

OUTPUT PINS
OPERATION

H..... L

TRIGGER

. H..... L

TRIGGER

L ...... H

TRIGGER

L ...... H

TRIGGER

L..... H

TRIGGER

L-..H

TRIGGER

n
n
n

U
U

I1 U
I1 U
I1 U

X = DON'T CARE
161
Sheet 2 of 2

83323010 A

4-67

DESCRIPTION
The 162 circuit is a dual differential line receiver. A
minimum differential voltage of
25 mV is required to ensure a
high or low output level. Common mode voltages of ±3 V or
less will be rejected. The
minimum allowable differential
input voltage is 5 volts. The ( GI)-w-----'
l62C features open-collector
(G2) - f - - - - - - '
outputs.

(Gil .........----1
(G2)

-t----.

NOTES:
1.

The two sections may be
shown separately by duplicating pin 6 in the
second section.

(G2)------I

Vendor identification:

Element

(G2)-----J

LOGIC SYMBOLS

Vendor Number

162

75107

1'32C

75108

l62S

NE5~lF

Package pin configuration.
1

14 +Vcc

13 -VEl

12
11

10
I

OND 7

(G1t-....- - - - - '
(G2t--I---------'

TOP
VIEW

ANALOG TO DIGITAL
CONVERTER APPLICATION

162

Sheet 1 of 3

4-68

83323810 A

V b b - -n

162 DUAL DIFFERENTIAL RECEIVER USED AS A
SCHMITT TRIGGER WITH EXTERNAL FEEDBACK
NETWORKS AND FIXED BIAS ENABLING G1 AND
G2 STROBE INPUTS'

TWOSTED PAl R
RECEIVER APPLICATION

DIFFERENTIAL
INPUTS

STROBES

VIO~ ~5MV

LOR H LOR H

LOR H

INDETERMINATE

LOR H

-25MV<V ID < 25MV

V 10 ~ -25MV

OUlPUT

THE DIFFERENTIAL INPUT
VOLTAGE POLARITIES SHOWN
MEASURED AT PIN A WITH
RESPECT TO PIN B. A MINUS
POLARITY INDICATES THAT
PIN A IS MORE NEGATIVE
THAN PIN B.

TRUTH TABLE
(RCVR APPL ICAT ION)

162
Sheet 2 of 3

83323810 A

4-69

PIN
PIN

5,6,8 - - - - + V - - -

--1

...

1 _ _ __

5
6

-------'

__I
I

PIN 4 IS LOW ONLY IF GI AND G2 ARE
HIGH AND PIN I IS MORE NEGATIVE
THAN PIN 2. G2 IS COMMON TO BOTH
CONVERTERS.

----

II
9

162 DIGITAL TO ANALOG
CONVERTER APPLICATION

----

162 TWISTED PAIR
RECEIVER APPLICATION

5,6,8 - - - - + V - - - -

1.12-\--8-1\--)-fC>

ov
-o.sv

TIMING SEQUENCE

9
162 SCHMITT TRIGGER

2---t
5 ------.~-I
6

-4

------.,.....---1

FUNCTION DIAGRAM
12 ----l~
II - - - - I

--9

8-----162
She~t

4 --70

3 of 3

83323810 A

DESCRIPTION
The 164 circuit is a dual negative-edge-triggered JK flipflop. Each flip-flop is provided with a direct SET input.
These direct inputs provide a
means of presetting the flipflop to initial conditions.
Data may be applied to or
changed at the clocked inputs
at any time during the clock
cycle, except during the time
interval between the set-up and
hold-times. The inputs are inhibited when the clock is low
and enabled when the clock
rises. The JK inputs continuously respond to input information when the clock is high.
The data state at the inputs
throughout the interval between
set-up and hold time is stored
in the flip-flop when the clock
pulse goes low. Each flip flop
may be set at any time without regard to the clock state by
applying a low level to the SET
input.

!4
S

3 J

164
xxx
(CLOCK)

-1

0,,6

2 K

A'S 0
11 J

1 9

164
xxx

(CLOCK)

-1

13~

o~8
r-

LOGIC SYMBOL

NOTES:
1.

SymDol repeated for each
flip-flop.

vendor identification:

Element

Vendor Number

164H

3062

1645

74Sll3

Package pin configuration.
+VCC 14

~TOP

~VIEW
1

83323810 A

GNO

164
Sheet 1 of 2

4-71

3 (12)
4(IO)L.j

1 (13)
2(12)

I
I

I
L

5(9)-.J

6(8))

TIMING SEQUENCE

INPUT

OUTPUT
OUTPUT
BEFORE eLK BEFORE eLK

SET CLEAR

0
0

TRUTH TABLE

164
Sheet 2 of 2

4-72

83323810 A

DESCRIPTION
The 172H circuit is a quad,
2-input, positive NOR gate.

:::_....;;.:_~tCI

-....;;.:_D__'.:_D.

NOTES:
1.

Symbol sections may appear separately.

Vendor identification:
3002

12[Y11

_...;1;,;;.3__

package pin configuration.

14 +Vcc
13

0
__:01,:01-

(AI

4
5
6

(81--

GNO 7

9
TOP

'72

3_ _ CCI
1-

xxx

8
--

VIEW

__:2.3. 0~1.;..1

LOGIC SYMBOL

A B

L
L

TRUTH TABLE

172
Sheet 1 of 1

83323810 A

4-73

DESCRIPTION
The l73H circuit is a quad,
2-input, positive NAND gate
with an open collector output.
NOTES:
1.

Symbol sections may appear separately.

Vendor identification:
3004

The output of each gate
is an open collector.

package pin configuration.
1

14 +Vcc

12
11

5
6

GND 7

TOP
VIEW

LOGIC SYMBOL

TRUTH TABLE

173
Sheet 1 o:E 1

4-74

83323810 A

DESCRIPTION
The 175 circuit is a dual, positive-edge-triggered, D-type
flip-flop. This device consists of two completely independent 0 flip-flops, both
having direct SET and RESET inputs for asynchronous operations such as parallel data entry in shift register application.
Information at input CD is
transferred to output Q (pin
5/9) on the positive-going edge
of the clock pulse~ Clock
pulse triggering occurs at a
voltage level of the pulse and
is not directly related to the
transition time of the positive-going pulse. When the
clock is at either the high or
low level, the CD-input signal
has no effect.
NOTES:

3 I

12..--.......:~~
-~D

LOGIC SYMBOL

Symbol repeated for each
flip-flop.

Vendor identification:

Element

Vendor Number

175

7474

l75L5

74LS74

1755

74S74

2 0

package pin configuration.
+vcc

~TOP

~VIEW
1

GNO

175
Sheet 1 of 2

83323810 A

4-75

4,10 (SET)

1,13 (RESET) D - - _ - I - - - - - - d

""----06,8

3,I1(CLOCK)u--~-I--'---£]

2,12 (DATA)

FUNCTION DIAGRAM
(EACH FLIP-FLOP)
PIN

4 (IO)
2 (l2)_~O

3 (II)
I

(13)
I
I

5(9}

6 (8)

TIMING SEQUENCE

175
Sheet 2 of 2

4-76

83323310 A

DESCRIPTION
The 176 circuit is a dual dif2
ferential line driver. This
circuit accepts a DTL or TTL
log ic signal and transmi ts it (F1 ENABLEt---3....r--over a differential line pair.
10
"On" state output current is
(F3STROBE)-_---t~___'
typically 12 mAe "Off" state
output current is 100 ~A max.
The output common mode voltage
range is -3 V to +10 V with respect to the circuit ground.
NOTES:

(F2 ENABLEI----I____

Type 176 Vendor identification: 75110

Package pin configuration.
TOP VIEW

In:~:::

GND

7Ue

(F1 E~NABLEI----=r-"'"
(F3 STROBE) - -.......100..-___'

(F2 ENABLE) - - - - I
'----'

LOGIC SYMBOL

176
Sheet 1 of 2

83323810 A

4-77

10~

....
1 ______

_=DON'T 'CARE CONDITION

TIMING SEQUENCE

LOGIC
INPUTS

INHIBIT
INPUTS

OUTPUTS*

OUTPUT
CONDITION

1,5

2,6

3,4

9,12

8,13

lOR 0
lOR 0
0
lOR 0
I

lOR 0
lOR 0
lOR 0
0
I

0
lOR 0
I
I
I

lOR 0
0
I
I
I

I
I
I
I
0

I
I

INHIBITED

0
0

ACTIVE
DATA
STATE

LOW OUTPUT REPRESENTS THE CURRENT ON STATE.
HIGH OUTPUT REPRESENTS THE CURRENT OFF STATE.

TRUTH TABLE

176
Sheet 2 of 2

4-78

83323810 A

is a 4-bit biuring the count
cransfer. of in.e ouputs occurs
a-going edge of
;e. The direct
), when taken low,
?uts low regardless
s of the clocks
6). The 182 is
ammable: that is,
l may be preset to
by placing a low
the count/load input
lnd entering the de.ta at the inputs. The
will then change to
.
the data inputs int ..w...Jf the s ta te of the
~ts.
This allows the
o be used as a 4-bit latch
Lster application) by in~ating the clock inputs and
~g the count/load input as a
.a strobe.

-_'
'

.......... 03

CNTR ..

182

R3 1 2 _

--3..... 02

R2 ....2_ _

10 0'
_ _4....
00

R1 .....· - RO .....6___

LOGIC SYMBOL

JTES:

Vendor identification:
Vendor Number

182

74197, 8291

1825

82S91

Package pin configuration.

182
Sheet 1 of 3

COUNT
0
I

2
3
4
5
6
7
8
9
10
II
12
13
14

OUTPUT
R3 R2 RI RO

0 0
0 0
0 0
0 0
0 I
0 1
0 1
0 I
I 0
I 0
I 0
I 0
I
1
I
1

I
I
I
1

0
0

I
1

0
0

I
I

0
0

I
I

0
0

I
1
1

I
I

I
I 0
1 1

TRUTH TABLE
(WITH PINS 5 AND 6 WIRED TOGETHER)
PIN

~u
:

U--

GATE D INPUTS

I
U
H~SET REG TO ZERO

13U
8

5,6
I

~
t

9 _---'
2 _ _ _~

12 _______________r-L
I

COUNTER
APPLICATION

4---1
5_~

10 --1r----~_ _ __
9 ____

3 _ _ _---'
2 ____________~r--II --.J

12_----'

TIMING SEQUENCE

182
Sheet 2 of 3

4-80

83323810 A

Connect pins 5 , 6 for 4-bit counting, using data input A. As
a 3-Bit counter, data input B is used. First stage may then be
used as an independent data latch if count/load and Clear Functions coincide with those of the counter.

I
I

I
I
I

DATA

COUNT/LOAD

r---·---4----aT
CLEAR

I
I

CLOCK 0 O"':;'----+-4---J

I
I

DA TA B

I
I

- - -

CLEAR

_0_ _ _ _+--+-4
01

- - I
PRESET
I6
a t--~9.(")OB
CLOCK 1 o,-;.-----+--+------f---.aT
B

DATA C

2 Q

CLEAR

DATA 0 o_II_ _ _ _+_-+-I

PRESET

0 0 1----';;;;;0 00

FUNCTION DIAGRAM

182

Sheet 3 of 3

83323810 A

4-81

DESCRIPTION

The 188 circuit consists of one
4-input and three 2-input positive NOR gates.

12
14

NOTES:
1.

Symbol sections may appear separately.

_---.:) >1004

Vendor identification:
9015

package pin configuration.
16 +Vcc
15
14
13
12

1
2
3
4
5
6

_____:_~~7-----

_____:~_~~9----OR

11
10

GND 8

TOP

188
xxx

6
10
11

)4
d
d )7
d )9

LOGIC SYMBOL

188
Sheet 1 of 1

4-82

83323810 A

DESCRIPTION
Circuit type 191 is a BCD-todecimal (1-0£-10) decoder.
Four active-high BCD inputs
provide one of ten mutually exclusive active-low outputs.
When a binary code greater than
9 is applied, all outputs are
high. This facilitates BCD to
decimal conversions and eightchannel demultiplexing and decoding.

9~7

DCDR
191

xxx

1II""It.6
...,

7....,
-6

The 191 circuit can serve as a
one-of-eight decoder with the D
input acting as the active-low
enable. Eight-channel demultiplexing then results when the
desired output is addressed by
inputs A, B, and c.

",,4

CD)

2 8

CC)

1 4

(8)

5_
",,9
4 ....,

CA)

15 1

",,3

",10

11
2 ""
~

-...,

1",,12
0

~13

NOTES:
LOGIC SYMBOL

Vendor identification:
9301

package pin configuration.
"'Vee

~~TOP

~VIEW
I

8
GNO

INPUT PIN

2
0
0
0
0

0
0

0
()
I

I
I
1
I
I

0
0

0
1
1
0

0
I
I
I
I

0
0
0
0
I
I

0
1
1
0
0
I
I
0
0
I
I

15
0

LO ("0") OUTPUT PIN
OTHER OUTPUTS ="111
13
12

10
9
3

0
I
0
I
0
I
0
I
0
I
0
I

5
6
7

* =ALL OUTPUT PINS HIGH
TRUTH

***
**
*'

TABLE

191

Sheet 1 of 2

83323810 A

4-83

INPUT
PIN

OUTPUT

(BINARY)

INPUT A

"'r"

r-----iC

.flli.

OUTPUT

OUTPUT 2

OUTPUT 3

OUTPUT 4

--,t~

"'J

----f>:>

- -c
..(O

B
I"- ~"C"

~D
A
B

INPUT B

- ~i

A
"B"

~
-

-'0

~
B

INPUT

.....,

---i

0 UTPIJT 5

-!:

.....

i
--

0 UTPUT 6

0 UTPUT 7

OUTPUT 8

OU TPUT 9

---I

INPUT 0

A
B

c
0

-A
0

t!1£

-A

--I I"-C
---! 0

FUNCTION DIAGRAM

191
Sheet 2 of 2

4--84

83323810 A

DESCRIPTION
The 195 circuit is a dual retriggerable monos table mUltivibrator. Input pins 4 and 12
trigger on the positive-going
edge of the input pulse and
pins 5 and 11 trigger on the
negative-going edge. The 195
circuit will retrigger while in
the pulse timing state (pin
3/13 high) and the end of the
last pulse will be timed from
the last input. A low level to
the reset input (pin 3/13) resets pin 6/10 to low level and
inhibits data inputs.

2
6

ss
195

xxx

NOTES:
1.

The full timing network
would be shown on the
logic diagram.

Vendor identification:
9602

LOGIC SYMBOL

195

Sheet 1 of 2

03323810 A

4-85

Package pin configuration:

+vcc

~TOP

~VIEW

GND

H = high level (steady
state), L = low level
(steady state), 1 =
transition from low to
high level,
transition from high to low
level, Jl... = one high
level pulse, L.j= one
low level pulse, x = irrelevant (any input, including transitions).

OUTPUT PINS
INPUT PINS
6(7) lO(9)
4(12) 3(13)

5(11)

1-----.

Output pulse width (t) is
defined as follows:

JL lS
JL LS
L

TRUTH TABLE

t = 0.32 RxCx (1 + 0.7)

(SEE NOTE 4)

Rx
Rx is in kQ, ex is in pF

t is in ns

I
'3

I
-1111 *JL S ,....

I
I
I

n=RETRIG~ __
I

UI --1*JLS ~
L.I~._J--'L,__
I

n~_~--~-

* PULSE
DURATION IS A FUNCTION OF THE
RC TIMING NETWORK.
TIMING SEQUENCE

195
Shee't 2 of 2

4-86

83323810 A

DESCRIPTION
The 200 circuit is a hex inverter buffer/driver with an
open-collector output.
NOTES:
1.

Symbol sections may be
shown separately.

Vendor identification:
7406

package pin configuration.
1

14 +Vcc

3
4

12
11

GNO 7

TOP
VIEW

LOGIC SYMBOL

200

Sheet 1 of 1

83323810 A

4-87

DESCRIPTION
The 202 circuit is a quad,
2-input, positive NAND gate
with open-collector outputs.

NO:~S: pear separ a tely •

Symbol sections may ap-

)

0 ~ ~~D 3 0
-

Vendor Number

202

7403

202H

74H01

202LS

74LS03

202S

74S03

Vendor identification:

Element

~. ~~~ -

~ ~~
~ ~
10

Package pin configuration.
+VCC 14

t==:J~?:w
1

7GND

INPUTS

OUTPUT

TRUTH TABLE
(EACH GATE)

202

Sheet 1 of 1

4-88

83323810 A

INPUTS

OUTPUT

A B C 0

DESCRIPTION
Type 208 is a dual, 4-input,
positive NAND gate.

Symbol sections may appear separately.
Vendor identification:
Vendor Number

Element
208

7420

208H

74H20

208L

74L20

208LS

74LS20

208S

74S20

0
t
I
0
0
I
I
0
0
I
I
0
0
I
I

I
0
I
0

0
0
0
0
0
0
0
t
I
I
I
I
I
I
I

NOTES
1.

0 0 0
0
0
0
I
I
I
I
0
0
0
0
I
I
I
I

0
I
0
I
0
I
0
I

TRUTH TABLE
... Vcc

~TOP

package pin configuration.

~VIEW

7 GND

(A)
(8)

208

(el

xxx

(D)

OR
9
10
12
13

LOGIC SYMBOL

208
Sheet 1 of 1

83323810 A

4-89

DESCRIPTION
Element 300 is a high-gain operational amplifier mounted on
a single chip.
Pin

Function

Input Frequency Comp.

Inverting Input

Non-inverting Input

-v (Connected to Case)

Output Frequency Comp.

Output

Input Frequency Camp.

FREQ

+15V

....

-15V FREQ

LOGIC SYMBOL

NOTE:
1.

Vendor Identification:
709C

PACKAGE PIN CONFIGURATION

300
Sheet 1 of 1

4-90

83323810 A

DESCRIPTION
Element 301 is a frequency compensated, high gain, operational amplifier.

NULL
,.

+15V

Function

Pin
1

Offset Null

Inverting Input

Non-inverting Input

-v

Offset Null

Output

Not Used (no connection)

·15V

NOTE:
1.

LOGIC SYMBOL

Vendor Identification:
741C

PACKAGE PIN CONFIGURATION

301
Sheet 1 of 1

83323810 A

4-91

DESCRIPTION

+15V

Element 306 is a pair of frequency compensated, high gain,
operational amplifiers.
Function.

Inverting Input A

Non-inverting Input A

Offset Null A

-v

Offset Null B

Non-inverting Input B

Inverting Input B

Offset Null B

Output B

No Connections

Output A

Offset Null A

separated sections have

Vendor Identification:

747C

LOGIC SYMBOL

(A)

pin 4 (-15 V) shown in
pa~entheses for second
section.
2~

...4_ _ _ _~..... -15V

(B)

NOTES:
1.

+15V

14·+Vcc

5
6

GND 7

TOP

VIEW

PACKAGE PIN CONFIGURATION
306

Sheet 1 of 1

4-92

83323810 A

DESCRIPTION
Element 307 is a differential
vol tage comparatc,r.

+12V
j

Function
GND

8
E COMPTR

307

Non-inverting Input

Inverting Input

-v

No Connection

No Conn1ect ion

Output

xxx

4,C
-6V

LOGIC SYMBOL

NOTES:
1.

Vendor Identification:
710

PACKAGE PIN CONFIGURATION

307

Sheet 1 of 1

83323810 A

4-93

DESCRIPTION
Element 309 is a wide-band differential amplifier with a nominal voltage gain of 9.

BIAS

+6V

BIAS

-6V

NOTES:
1.

Vendor identification:
3001

PACKAGE PIN CONFIGURATION

LOGIC SYMBOL

309

Sheet 1 of 1

833.23810 A

DESCRIPTION
Element 315 is a wide-band amplifier for frequencies up to
200 MHz.

BIAS

+6V

NOTES:
1.
2.

Vendor identification:
CA3040

OPAMP

+~--

315

xxx

package pin configuration:

- - - -6V
BIAS

LOGIC SYMBOL

2+V

-r-----~-----l
TO

ALL

STAGES

INPUT

OUTPUT

6
TO

ALL

STAGES

FUNCTIONAL DlAGRAM

BIAS
CIRCUITS

L _________ _

___ .-J
8

'--.;-oJ

SUBSTRATE
( -V)

315
Sheet 1 of 1

83323810 A

4-95

DESCRIPTION

+V1 +V2

Element 316 is a wide band,
unity-gain current amplifier
capable of providing peak currents of ±200 rnA into a 50-ohm
load. The symmetrical class-B
output provides a constant low
output impedance for both the
positive and negative slopes of
the output pulses.
Separate connections are provided for + (Vcc ) and (VEE) voltages to both the
input and output stages (see
electrical schematic diagram).
This increases the versatility
of operation by allowing a decreased voltage to be applied
to the output stage (Q3, Q4),
thereby minimizing the power
dissipation.
Typical applications: differential input/output op amp,
booster amplifier, level
shifter, pulse-transformer
driver, and transmission-line
driver.

LOGIC SYMBOL
-V1 -V2

03
:3

NOTES:
1.

Vendor identification:
LH0002CH
I NO---f

OUT

package pin configuration:
5

ELECTRICAL
SCHEMATIC

DIAGRAM
316
Sheet 1 of 1

4-96

83323810 A

DESCRIPTION
The 320 circuit is a negative
voltage regulator that can be
programmed by an external resistor to provide any voltage
from -40 V to 0 V while operating from a single unregulated
supply. Regulation is 1 mV, no
load to full load. The full
load current of 25 rnA can be
increased by adding external
transistors.
See page 320 Sheets 2 and 3 for
typical applications.
1

NOTES:
1.
2.

Vendor identification:

MVR

LM304

xxx

320
7

Package pin configuration: (pin 10 is unused)
T

-v

T =TERMINATION
D =DIVIDER COMPONENTS
B = BIAS CIRCUIT (REFERENCE VOLTAGE)
-V =UNREGULATED INPUT
C =CURRENT MONITOR
REPLACE m WITH NOMINAL VOLTAGE AS
DETERMINED BY D
REPLACE m' WITH NOMINAL CURRENT AS
DETERMINED BY C

LOGIC SYMBOL

320

Sheet 1 of 3

83323810 A

4-97

20 kn

4.7 fL

VOUT

320
7

6
4
~

2
5,C
2.4
kn

V1N

BASIC REGULATOR

0.01 IJ-F

4.7 IJ-F

t-'-~--,--- Vou T

320
7

6
9

22 n

5,C

2.4
470
pF

VS1AS : 10 V

__.-

'---_-.._----,,,-_.

SEPARATE BIAS SUPPLY

320

Sheet 2 of 3

4-98

83323810 A

I---~,.-----,- VOUT

320

'::.-

432
2.4
NC
kn

V1N

(-12 v)

~'::.1. 4.7 fLF

0.2

HIGH- CURRENT REGULATOR

.tl

100 pF
10 Mn

2.5 kn

80 /'oF

..8::~---l-_---r"--'--_ _ VOUT

320
7

2.4

100

47 n
V 1N

(< -8.5 V)

SWITCHING REGULATOR

320
Sheet 3 of 3

83323810 A

4-99

+1SV

DESCRIPTION
Element 322 is a frequency compensated, high-speed operational amplifier.
Pin

Function

Offset
Null/Compensation 1

Inverting Input

Non-inverting Input

-v

Offset Null/Compensation 3

Output

Compensation 2

2
6

-1SV

.__-.,. .

_~J

LOGIC SYMBOL

NOT~S:

Vendor Identification:
LM318

PACKAGE PIN CONFIGURATION

322
Sheet 1 of 1

4-100

83323810 A

DESCRIPTION
Element 326 is a high-gain operational amplifier.

No Contact

Offset Null

Inverting Input

Non-Inverting Input

No Contact

Offset Null

Output

No Contact

NOTE:
1.

NULL+15V

Function

-15V

LOGIC SYMBOL

Vendor Identification:
741C

Vee
II

~TOP
Sr------u-d

VIEW

6 7
VEE

PACKACE PIN CONFIGURATION

326
Sheet 1 of 1

83323810 A

4-101

DESCRIPTION
Element 327 is a dual-polarity
voltage regulator for providing
balanced positive and negative
output voltages at currents up
to 100 mAe Internally, the
device is set for tlS V outputs, but voltage and balance
pins permit simultaneous adjustments from 8 to 20 volts.
Input voltages up to ±30 V can
be used, and current monitor
connections provide for adjustable current limiting.

VOLTAGE
ADJUST

FREQ
COMP(-)

,...--..

CURRENT
MONITOR

+mVR
+ 5

327

-mVR

~.J

CURRENT
MONITOR

-v

typical applications, see
page 327 Sheets 2 and 3.

For

REPLACE m WITH NOMINAL VOLTAGE
AS DETERMINED BY VOLTAGE AND
BALANCE ADJUST COMPONENTS.

NOTES
1.

Vendor identification:
MC1468L

LOGIC SYMBOL

package pin configuration.
GND I

Vee 7

327
Sheet 1 of 3

4-102

83323810 A

11500 pF

NOT
USED

'"' +VOUT

+20 V1N 0

114

~ RSC

4.7 n

+
1.0
fLFt

I---

1.0

:1_

fL~

J
1500 pF

NOT

.~ RSC
4)

4.7

USED
....

'"'

-20 V1N 0

BASIC 50 mA REGULATOR

327
Sheet 2 of 3

83323810 A

4-103

39 kn

.......

20 kn

39 kn

·t·

...

-t.L

+VOUT

11.0 p. F
1:1500PF
~)

: Rsc

- - 1500 pF

-" ) 100 kn
~

" RSC

~ -VOUT

+.r 1.0

VOLTAGE ADJUST/BALANCE CIRCUIT

327
Sheet 3 of 3

4-104

83323810 A

DESCRIPTION

The 329 circuit is a wide-band
RF/IF/Audio amplifier with external AGe control.
NOTES:
1.

Vendor identification:
1590

Package pin configura1
tion. (TO-99 metal case) - ' - -.......

TOP
VIEW

LOGIC SYMBOL

329
Sheet 1 of 1

83323810 A

4-105

DESCRIPTION

+6V

The 330 circuit is a differential voltage comparator. The
circuit has differential analog
inputs and complementary logic
outputs compatible with EeL. A
latch function allows the comparator to be used in a samplehold mode. If the latch enable
input is high, the comparator
functions normally. When the
latch enable goes low, the comparator outputs are locked in
their existing logical states.

Non-inverting Input

Inverting Input

Latch Enable

-v

No Connection

Q Output

GND

330
xxx
8

LOGIC SYMBOL

INPUT

E COMPTR

Function

NON-INVERTING

PACKAGE PIN CONFIGURATION

2
0----1

~______~~~7~Q OUTPUT

GND
INVERTING

INPUT

o---a

" " ' O - - _ - - f - - . : .-o Q

OU T PU T

NOTE:

Vendor Identification:
AM685

LATCH
ENABLE

FUNCTION DIAGRAM
330
Sheet 1 of 1

4-106

83323810 A

DESCRIPTION

331A

Element 331A is a dual-polarity
tracking voltage regulator that
provides balanced or unbalanced
positive and negative output
voltages at currents up to 200
rnA.
A single external resistor
adjustment changes both outputs
between the limits of ±SO mV
and ±42 V. The 331A comes in a
9-pin (type H) "top hat" package that can dissipate up to 3
w. Both output voltages drop
to zero if the junction temperature rises above 175°C.
Element 331 is similar to the
331 A, except that it comes in
a l4-pin DIP that can dissipate
up to 900 mW.

... ,
, FREQ

+mVR

331A

-mVR

L..--J

'----

L..--J

-v

FREQ

NOTES:
1.

331

Vendor identification:

Element

Vendor Number

331

RC4194D

331A

RC4194TK

FREQ

+mVR

1
G r----

331

Package pin configuration.
-mVR

14 Vee

12 GND

GND
Vee

L--J
FREQ

CASE CONNECTED TO VEE

331

331A

L...-

-v

REPLACE m WITH NOMINAL VOLTAGE AS
DETERMINED BY BIAS (B) AND BALANCE (N)
COMPONENTS

LOGIC SYMBOL
331

Sheet 1 of 1

83323810 A

4-107

DESCRIPTION

The 332 and 353 circuits are
positive voltage regulators.
Output voltage is adjustable
from 4.5 to 40 volts. The
full-load output current of the
332 is 45 mA, that of the 353
is 25 mAe Either of these may
be increased in excess of 10 A
by using an external pass transistor.

3
7

+mVR

-::"

FREO
COMP

NOTES:

Vendor identification:

Element

Vendor Number

332

LM305A

353

LM376

-::"

]:1__}o

The 332 comes in a a-pin metal
can and the 353 in an a-pin DIP.

353

package pin configuration:

FREO
COMP

~1
-}

353

PIN 4 CONNECTED
TO CASE

332

332, 353
Sheet 1 of 1

4-108

83323810 A

DESCRIPTION

BAL-

Element 333 is a dual-polarity
tracking voltage regulator that
provides balanced positive and
negative 15 V outputs at currents up to 100 rnA. The type-H
packaging permits heat dissipation of up to 2.4 W. Both output voltages drop to zero if
the junction temperature rises
above 175°C.
The 333 circuit may also be
used as a single-output regulator with up to +50 V output,
where:

ANCE +V

FREQ

+ 15VR

333

XXX

- 15VR

Iv in \60 V

(V out +3 V)
NOTES
1.
2.

-v
Vendor identification
RC4l95TK

LOGIC SYMBOL

package pin configuration:

+VOUT

3'!3

T'O

1'0~F
'="

15 kn

":IF

1'0~F

333

+VOUT

"liP'

:
VOUT : +15 V (I +

=~)

R2
35 kn

BALANCED OUTPuT
(± 10 :s 100 mAl

....
SINGLE +50 v OUTPUT
(1 0 S 100 mAl

TYPICAL APPLICATIONS

333
Sheet

83323810 A

of 1

4-109

FREO

DESCRIPTION

f----.A.----~

Element 338 is a dual high-gain
operational amplifier.
NOTES:
5

Symbol sections may appear separately.

Vendor identification:
MC1437

Package pin configuration:

12
9

14 Vee

FREO

LOGIC

SYMBOL

OUTPUT I

EQUIVALENT CIRCUIT

-V

.....
7_ _---4

5
INPUT 2

OUTPUT 2

OUTPUT

LAG
2

338

Sheet 1 of 1

4-110

83323810 A

DESCRIPTION
Element 339 consists of two
high-speed voltage comparators
in one package. Each section
provides an open-collector output capable of driving lamps or
relays requiring up to 25 mAe
Inputs and outputs can be isolated from system ground.
The 339 can operate from a single +5 V supply, or from ± supplies with a total potential
difference of up to 36 V. Maximum differential input voltage
is ±5 V.
If pin 4 (9) is more positive
than pin 5 (10), the output is
open. If pin 4 (9) is equal to
or less positive than pin 5
(10), the output is grounded.
NOTES

LOGIC SYMBOL

OUTPUT

INPUT 2
Vcc~

GND

If sections appear sepa-

rately, the supply-voltage pins are repeated as
needed and only the applicable ground pin is
shown for each section.
2.

Vendor identification:
LM3l9

Package pin configuration
and functional diagram.

GND

VEE OUTPUT

339

Sheet 1 of 1

83323810 A

4-111

DESCRIPTION
The 500 circuit is a synchronous 4-bit up/down counter.
Synchronous operation is provided by having all flip-flops
clocked simultaneously so that
the outputs change coincidently
with each other when so instructed by the steering logic. The outputs of the four
master-slave flip-flops are
triggered by a low-to-high-level transition of either count
(clock) input. The direction
of counting is determined by
which count input is pulsed
while the other count input is
high.
The counter is fully programmable: that is, the counter may
be preset to any state by entering the desired data at the
data inputs while the load input (pin 11) is low. The output will then change to agree
with the data inputs independently of the count pulses. A
high level applied to the clear
input forces all outputs to the
low level. The clear function
Is independent of the count and
load inputs.

13
CRY

(0)

BRW

UP/ON CNTR·4
03

500

xxx

(°0)

te)

(Oe)

tB)

(Oe)

(A)

(OA)

COUNT
CLR LO UP ON
4

LOGIC SYMBOL

NOTES:
1.

Input/Output identifiers
are not part of the symbol.

500
Sheet 1 of 3

4-112

83323810 A

Vendor identification:

Element

Vendor Number

500

74193, 9366

SOOLS

74LS193

+vcc

~TOP

~VrEW
I
8
GNO

package pin configuration.

Elli
14

CLEAR

LOAD

.~
I

, , -----------------I

-.J

I~-----------------_________________ _
I

,..--------------------

---_---II

...J~--~L_================_-=

DATA

I
--,--------------L
_________________
_

1,....-------,

1 I

COUNT

.tl

COUNT DOWN

=l1
Qc -l

QS
OUTPUTS

I
I
I

=-,

CARRY
BORROW

I
I
I
I

II
I

L.J

I
I
--~-------~-----------------I----~LJ
I I
I
I
I
0
15
10 1 113
15
0
~

CLEAR

ll4

-·COUNT

I
14
131
I.-- COUNT DOWN-...I

PRESET

NOTE:
ILLUSTRATED ABOVE IS THE FOLLOWING SEQUENCE:
I. CLEAR OUTPUTS TO ZERO.
2. LOAD (PRESET) TO, BCD THIRTEEN.
3. COUNT UP TO FOURTEEN, FIFTEEN, CARRY, ZERO, ONE AND TWO.
4. COUNT DOWN TO ONE, ZERO, BORROW, FIFTEEN, FOURTEEN AND THIRTEEN.

COUNTING SEQUENCE

500
Sheet 2 of 3

83323810 A

4-113

r-----

L-/

- r---'-.,..

SORROW
.... OUTPUT

,.., CARRY

OUTPUT

DATA
INPUT A

rL.J
4

DOWN
COUNT

UP
COUNT

DATA

INPUT SO-

IPAES~T

°A
_
°ACLEAR

rVwy
~T

-I-

l\..

~~V

DATA

0---

INPUT C

OUTPUT 0A

r-L---/

PRESET
HT Os

OUTPUT 0e

.. OUTPUT 0c

0 UTPUT 00

-..,

~E'-

CLEAR

rL-'"

+-OL

PRESET
~T °c

r-uVLr\ ------1,

~.-

CLEAR

9
14

OATA

0---

INPUT D

CLEAR

1
~~:[>- PRE~~

g-y
I

LOAD

~T_

CLE~~f-

~LJT

FUNCTION DIAGRAM

500

Sheet 3 of 3

4-114

83323810 A

DESCRIPTION
The 501 circuit is a 5-bit comparator that provides comparison between two 5-bit words and
gives three outputs: "less
than", "greater than", and
"equal to". A high level on
the active low enable (pin 1)
forces all three outputs low.

A4
COMPTR·5
501 .
xxx

A3
A2
A1
AO

A>B

NOTES:

A-B
B4

Vendor identification: 9324

1.
2.

pin names:

Function

+vcc'6

B2
TOP

VIEW

GNO

Enable (active low)'
input

LOGIC SYMBOL

9,10,11,
12,13

Word A parallel inputs

3,4,5,

Word B parallel inputs

6,7

Less Than B (A<B)
output

A Equal to B (A=B)
output

INPUi
I

OUTPUT

L WORD A = WORD B
L WORD A > WORD B
L WORD A < WORD B

A Greater Than B
(A>B) output

Package pin configuration

A<B A>B

A=B

L
L
L

H =HIGH LEVE L

L =LOW LEVEL

X =EITHER HIGH OR LOW LEVEL

TRUTH TABLE

501

Sheet 1 of 2

83323810

4-115

A=B

~~---A>B

FUNCTION DIAGRAM

501
Sheet 2 of 2
Q)

W
W

IV
W
Q)
....,

DESCRIPTION
The 519 circuit is a register
made up of six D-type flip-flops with common clock and
clear inputs.

NOTES:
1.

Vendor identification:

Element

Vendor Number

519

74174

5195

74S174

LATCH
519
05
xxx

J CLRRO

LOGIC SYMBOL

package pin configuration.
+vcc

~TOP

~VIEW
8

CLEAR

CLOCK

I GND

3,4,6 _ _
DATA
INPUT
11,13,14
DATA
2, 5,7
OUTPUT 10,12,15

Jl.SU

II = DON'T CARE
FUNCTION SEQUENCE

519
Sheet 1 of 2

83323810 A

4-117

0
v I

f"'o.

0
.r-.
'-" S

Y
D
-""' S

'-J

DATA

INPUTS

OUTPUTS
I

1""'1

?
13

0
.r-.
v

.()

CLOCK

CLEAR

%-[>

0
.r..
'-"

I
FUNCTION

DIAGRAM
519
Sheet 2 of 2

4-118

83323810 A

DESCRIPTION
Element 520 contains four positive-edge-triggered D-type
flip-flops with common clock
and reset (clear) inputs. Each
FF has complementary outputs.
Information at the input is
transferred to the output on
the positive-going transition
of the clock pulse. When the
clock is either high or low,
input data has no effect on the
outputs.

LATCH
520
xxx

2
~3

ifooo.

i""

10
12

~ 11

r-'

15
13

NOTES:

Il00\.14

CLR

r-..r

~~1

Vendor identification:

Element

Vendor Number
LOGIC SYMBOL

520

74175

520LS

74LS175

5208

745175

Package pin configuration.

+VCC 16

~v~~~
8 GND

OUTPUTS

INPUTS

CLEAR
L

CLOCK

H
H
H

f
f

L
X

L
NC

L
H

.,. =TRANSITION FROM LOW TO HIGH
LEVEL
X=DON'T CARE
NC SAME AS BEFORE INDICATED
INPUT
CONDITIONS WERE ESTABLISHED

TRUTH TABLE

520

Sheet 1 of 2

83323810 A

4-119

-~4

)

--0 "'L

ClR

-0 iO
(2 )

.0 I~

(;)

(5)

0 20
( 7)

--0 "'L

ClR

f- 20

()

0
(12 )

L--c LClR

(10)

(II )

i
c

- ClK

40 n

(13)

CLOCK

o-~
(9)/"

,..,

(15 )

(14)

CLEAR

(I )

FUNCTION DIAGRAM
520
Sheet 2 of 2

4-120

83323810 A

DESCRIPTION

The 521 circuit performs the
addition of two 4-bit binary
number s. The sum (II) outputs 10
are provided for each bit and
the resultant carry (C4) is obtained from the fourth bit.
II

:o-----!2

_ _--.
B I - - - l - + - t - + L...--_
-i

CO - - - l H - + - - I

NOTES:

Vendor identification:
7483

Package pin configuration.
GNO
12

A3--~+1

83 --+-+-++-L.-J

C~~O:W
5
Vee

1 A8
3 A4
8 A2
10
16
4
7

ADDER

'-------,

521

xxx

CRY 14
OUT

8 15

):r----! 4

lI:>--6---C4

13 CRY
IN

FUNCTION DIAGRAM
LOGIC SYMBOL

521

Sheet 1 of 2

83323810 A

4-121

OUTPUT

INPUT
WHEN

CO=L

L
L

H
L

L
H

L
H
L
H
L
H
NOTE I:

H
L
L
H
H

L
L
H
H

L
L
H

H
H

L
L
L
L

L
L

L
H
H
L

H
H

H
L

H
L
H
H
H

L
L

H
H

L
L
L
L
H

H
H
H
H
H

L
L
L
L

L
L

L
L
H
H
H
H

L
H
H

H
H
H

L
H
H

L
L
H
H

L
L

L
L
H
H

L
L
H

L
H
H
H

H
L
L
L
L
H
H
H

L
L
L
L

L
H
H
H
L
H

H
H
H

INPUT CONDITIONS AT AI, A2, BI, 82, AND CO
ARE USED TO DETERMINE OUTPUTS LI AND
I2 AND THE VALUE OF THE INTERNAL
CARRY C2. THE VALUES AT C2, A3, B3, A4,
AND B4, ARE THEN USED TO DETERMINE
OUTPUTS I3, ~4, AND C4.

TRUTH TABLE

521
Sheet 2 of 2

4-122

83323810 A

DESCRIPTION

The 527 circuit is an 8-bit
shift register with gated serial inputs and an asynchronous
clear. The gated serial inputs
(pins land 2) permit complete
control over incoming data as a
low at either (or both) input(s) inhibits entry of the
new data and resets the first
flip-flop to the low level at
the next clock pulse. A highlevel input enables the other
input which will then determine
the state of the first flipflop. Data at the serial inputs may be changed while the
clock is high, but only information meeting the setup requirements will be entered.
Clocking occurs on the low-tohigh-level transition of the
clock input.

~ 527

SR·8

----l

"'\

----!

xxx

5
6

10
11
12

J
8

13
CLR
~}9

LOGIC SYMBOL

NOTES:

Vendor identification:
74164, 8570

Package pin configuration.
+VCC

~TOP

~VIEW
1
7

GND

527

Sheet 1 of 3

83323810 A

4-123

®CLEAR-U-SERIAL
INPUTS

{CD

~~--------------------

A
®B
I

®CLOCK

CVQA~~~'~I______________~

~~------------------

~~--------------~~------------
~J

OUTPUTS

f6\ Qo

== ~ l

~________________________~

~~_____________

LSl'---_______

@ QE =~ ~;

@QF =~=~

I
~-,-------------

____________
~QH=~=1~______________________________________~r-l~____________
~QG=~=~

~--~~l
I

INHIBIT

SHIFT

CLEAR

INHIBIT

CLEAR

NOTES: I. TYPICAL CLEAR, INHIBIT, SHIFT, CLEAR, AND INHIBIT SEQUENCES.
2.
= PIN ASSIGNMENTS.

IV
W
00
~

FUNCTION SEQUENCE

527
Sheet 2 of 3

ex>

OUTPUT

w
w
IV
w
ex>
......

:J:lI
.------IS

CLOCK

o = PIN ASSIGNMENTS
A
w

SERIAL INPUTS

0®

CLOCK CLEAR

®
FUNCTION DIAGRAM

527
Sheet 3 of 3
~

......
IV
U1

DESCRIPTION
Element 538 is a dual 1-of-4
decoder with low-active outputs.
NOTES:
1.

Symbol sections may appear separately.

Vendor identification:

Element

Vendor Number

538

9321

ENCOOEOY

538S

74Sl39

538LS

74LS139

INPUTSt-.-.-..

10
II

___
15.., E

LOGIC

SYMBOL

Package pin configuration.
16

GND

Vee

INPUTS

OUTPUTS

INH/
-.fNA

TRUTH TABLE

538
Sheet 1 of 1

4-126

83323810 A

DESCRIPTION
The 581 circuit is a phase-frequency detector. This device
contains two digital phase detectors, an emitter following
amplifier, and a charge pump
circuit that converts TTL inputs to a dc voltage for use in
frequency discrimination and
phase-locked-loop applications.
The two phase detectors have
common inputs. Phase-frequency
detector A is locked in (indicated by both outputs high)
when the negative transitions
of the variable input (pin 3)
and the reference input (pin 1)
are equal in frequency and
phase. If the variable input
is lower in frequency or lags
in phase, output pin 13 goes
low; conversely, output pin 2
goes low when the variable input is higher in frequency or
leads the reference input in
phase. The variable and reference inputs to phase detector A
are not affected by duty cycles
because negative transitions
control operations.

Of DET

581
xxx

RE FERENCE -----4III---U
INPUT

---t-"'\..t..-...::... . .

VARIIABL E _3.....
INPUT

DETECTOR
A
I-------f

DETECTOR
B --

LOGIC SYMBOL

CHARGE
PUMP

[>
581
Sheet 1 of 2

83323810 A

4-127

phase detector B is locked in
when the variable input phase
lags the reference phase by 90°
(indicated by output pins 6 and
12 alternately going low with
equal pulse widths). If the
variable input lags by more
than 90°, pin 12 will remain
low longer than pin 6. Conversely, if the variable input
phase lags the reference phase
by less than 90°, pin 6 remains low longer. In phase detector B, the variable input
and the reference input must
have 50% duty cycles.
The charge pump accepts the
phase detector outputs and converts them to fixed-amplitude
posititve and negative pulses.
NOTES:

Vendor identification:
4044, 4344

Package pin configuration
Vee

c=:J
1

7 GND

581

Sheet 2 of 2

4-128

83323810 A

DESCRIPTION
The 916 circuit may be used as
a one-shot, a free-running
multivibrator, or a comparator-input FF. Descriptions are
provided for each of these applications.

NOTES:

I 3

FF
916
XKX

Vendor identification:
NE555

Package pin configuration

108

GND
TRIGGER 2
OUTPUT:3
RES E T 4

Vee
7 DISCHARGE
6 THRESHOLD
5 CONTROL VOLTAGE
F

MV
916
xxx

B =TO BIAS NETWORK
f =TO FREQ. COMPONENTS
Arrows in the line to pin 5 are omitted for
fixed-frequency or fixed delay applications.

LOGIC SYMBOL

916
Sheet 1 of 5

83323810 A

4-129

Vee

6
,_~__~____________~__
50CONTROL
THRESHOLDu---+---I COMPARATOR rVOLTAGE

COMPARATOR

1----+---0

RESE T

DISCHARGE o--7--t--.

FLIP FLOP

OUTPL;T

STAG~

:3
OUTPUT

GROUND

BLOCK DIAGRAM

916
Sheet 2 of 5

4-130

83323810 A

MONOSTABLE OPERATION
In this mode of operation, the
timer functions as a one-shot.
Referring to Figure la, the external capacitor is initially
held discharged by a transistor
inside the timer.

+Vcc(5 TO 15V)
O---------------4--------e----~

RESET

upon application of a negative
trigger pulse to pin 2, the
flip-flop is set. This releases the short circuit across the
external capacitor and drives
the output high. The voltage
OUTPUT
across the capacitor now increases exponentialJy with the
time constant I = RAC. When
the voltage across the capacitor equals 2/3 Vee, the comparator resets the flip-flop
which, in turn, discharges the
capacitor rapidly and drives
the output to its low state.
Figure lb shows the actual
waveforms generated in this
mode of operationD

8
7

INPUT = 2V/CM

0
/

~t'

O' }LF

Figure lao

t =0.1 MS/CM

OUTPUT VOLTAGE = 5V/CM

CONTROL
VOLTAGE

III f - - -

"[ -

JI"

JI/
7

CAPACITOR VOLTAGE =2V/CM

R A =9.IKn. C=.OlfLF, RL=IKn

Figure lb.
916

Sheet '3 of 5

83323810 A

4-131

The circuit triggers on a negative going input signal when
the level reaches 1/3 Vee.
Once triggered, the circuit
will remain in this state until
the set time is elapsed, even
if it is triggered again during
this interval. The time that
the output is in the high state
is given by T = 1.1 RAe. Because the charge rate and the
threshold level of the comparator are both directly proportional to supply voltage, the
timing interval is independent
of supply. Applying a negative
pulse simultaneously to thereset terminal (pin 4) and the
trigger terminal (pin 2) during
the timing cycle discharges the
external capacitor and causes
the cycle to start over again.
The timing cycle will now commence on the positive edge of
the reset pulse. During the
time the reset pulse is applied, the output is driven to
its low state.
When the reset function is not
in use, it is recommended that
it be connected to Vee to
avoid any possibility of false
tr igger ing.
t =O.S MS/CM

OUTPUT VOLTAGE

SV/CM

Figure 2b.

CAPACITOR VOLTAGE

IV/CM

916

Sheet 4 of 5

4-132

83323810 A

Astable Operation
If the circuit is connected as
shown in figure 2a (pins 2 and 6
connected) it will trigger itself
and free run as a multivibrator.
The external capacitor charges
through RA and RB only. Thus
the duty cycle may be precisely
set by the ratio of these two resistors.
In this mode of operation, the capacitor charges and discharges between 1/3 CCC and 2/3 Vce. As
in the triggered mode, the charge
and discharge times, and therefore
the frequency are independent of
the supply voltage.
Figure 2b shows actual waveforms
generated in this mode of operation.

+Vcc (5 TO 15V)

o---------------__

------~----~

The charge timer (output high) is
given by:
tl

= 0.693 (RA + RB) C

OUTPUT

0-------13

7t----..

and the discharge time {output
low} by:
t2 = 0.693 (RB)

CONTROL
VOll'AGE
.01 fLF

Comparator-Input Flip-Flop

This appllcation is depicted by·
the top two symbol drawings on
sheet 1. pin 5 determines the
quiescent voltage levels of the
trigger (pin 2) and the threshold
(pin 6). In practice:
Vpin6

= VpinS7

6r-.....---..

Figure 2a.

Vpin2 = VpinS
2

When the level at pin 6 exceeds
that at pin 5, the FF sets. When
the level at pin 2 exceeds onehalf of that at pin 5, the FF resets.
916

Sheet 5 of 5
83323810 A

4-133

DESCRIPTION

Element 926 is a bidirectional
analog gate that switches on
and off under the control of a
binary input. A logic "0"
turns the gate on and allows it
to pass an analog signal from
input to output. A logic "1"
turns the gate off and causes
it to block the analog signal.
Pin

Function

3,6,11,14

Analog Inputs

1,8,9,16

Analog Outputs

2,7,10,15

Binary Inputs

4,5,12,13

Ground

n 926

GATE

926

NOTES:
1.

Symbol sections may appear separately; show applicable ground pin for
each section.

Vendor Identification:
IH5012
16

~vW~
I

PACKAGE PIN CONFIGURATION

BINARY
INPUT FUNCTION
BLOCKS
ANALOG
I
SIGNAL
PASSES
0
ANALOG
SIGNAL

TRUTH
TABLE

926
Sheet 1 of 1

4-134

83323810 A

DESCRIPTION
The 986 circuit is an eight-input
digital-to-analog converter that
provides its maximum output current (IO) when all digital inputs are high (K=255), decreasing
in discrete steps as the count
goes from 255 to zero.

+VREF

13
D/A CONY

5 128
6

A reference current amplifier provides a constant current into the
R-2R ladder, which divides the
DIGITAL
current into binary-related comINPUTS
ponents that are fed to the current switches. Current from the
reference amplifier is controlled
by adjusting the positive/negative
reference voltages. The output
voltage (EO) range may be varied
by the voltage applied to pin 1.
The compensation input, pin 16,
RANGE
maintains correct phase margin
CONTROL
throughout the range.
The Typical Application diagram
shows the 986 connected to provide
128 discrete output current values
to an op amp (not part of the 986
circuit). The op amp feed-back
resistor is selected to provide an
EO of 10 volts when input current to the op amp is maximum that is, ~or a count of 127.

8
9
10
11

986
xxx

64
32
16
8
4

COMP -vREF

-v

LOGIC SYMBOL

DIGIT AL INPUTS

128

I 4
CURRENT SWITCHES

GND

BIAS
CIRCUIT

+V~3REFERENCE
CURRENT

AMPLIFIER

+VREF 14

-VR EF

COMP

-v

RANGE
CONTROL

986

Sheet 1 of 2

83323810 A

4-135

NOTES:
1.

On a logic diagram, usually
only the digital input and
analog output pins are shown.

Vendor identification:

Element

Vendor Number

9a6A (6-Bit)

MC140aL-6

986B (7-Bit)

MC140aL-7

986D (a-Bit)

MC1408L-8

986E (8-Bit)

MC1408L-7.5

Package pin configuration.

TOP
VIEW
8 GND

+5V

+ 15 V -.AJiA_(4_M_A~)M_A_X....,)

+Vcc

128

32
16

986

EO ~ IOV

4
2

TYPICAL
APPLICATION

986

Sheet 2 of 2

4-136

83323810 A

DESCRIPTION
The 4001 circuit is a CMOS
package consisting of four
2-input positive NOR gates.
NOTES:
1.

Symbol sections may appear separately.

Vendor identification:
4001

Package pin configuration:
14

VDD

_____~~) \~~3_____

----:.oJ:) >.....:.----4

:, >..:.:-10_

__I~:&...-)_ _>~II-_
OR

Vss '1
(OND)

•

4001)3
xxx

:d )4
:d )10
II:d )11
LOGIC SYMBOL

4001
Sheet 1 of 1

83323810 .A

4-137

DESCRIPTION
The 4011 Circuit is a CMOS
package consisting of four
2-input positive NAND gates.

~I \~I~ )3

NOTES:
1.

Symbol sections may appear separately

Vendor identification:
4011

Package pin configuration:
14

Voo

:1
:1
::1

)4
)10
)11
OR

v55 7 """L...-_r- •
(tNO)

~j\0~~3

:~ )4

:j )10
::j )"
LOGIC SYMBOL

4011
Sheet 1 of 1

4-138

83323810 A

DESCRIPTION
The 4017 circuit is a CMOS decade counter with an asynchronous, active-high reset and a
built-in count decoder.
Changes in the output occur
either on the positive-going
edge of pin 14 provided that
pin 13 is low or on the negative-going edge of pin 13 provided that ,pin 14 is high.

10 CNTR
4017 C p!L-

XXX

II
8 9

9
~

Outputs are normally low, going
high only at the appropriate
decimal count time.

"'~" I

A Carry output is provided that
is high for all counts less
than 5, and low for counts 5
through 9.

7 6
5
6
5 I
4 10
7
3
4
2
I 2
0 3

LOGIC SYMBOL

NOTES:

Vendor identification:
4017

Package pin configuration:
.& Ycc

GNO

•

---

4017
Sheet 1 of 3

83323810 A

4-139

CLOCK
CLOCK

-,0

--~I--~--~----~----~--~~--~~~

:, -

~------------------~--~~--~~---,~i
I

L
,I
I

t
,

I- .- - - - - - - - - - - ' fr I

II
r
l

I_ _

__~r_l~______________________~'~~
Q2

______

__________~r_l_________________~-------____________~r_l_______________~________

~r__l~

____________________

_________

________________~r_l~____________________

_________ 11_________,

Q
7

______________________

_______________

~r_l

__________________________

____________

~r_l

____________________________

~r_l~

_________

TIMING DLAGRAM
4017
Sheet 2 of 3

4-140

83323810 A

0 At----+--,.---4

14 CLOCK

15~--~
r-t--t-...o.---tD

~~~--------~2

r-;-;----------Q6

03
t---t---t-------c7

09
t---t--t---------Qi I

R
~-----------~12

CARRY
FUNCTION

DIAGRAM

4017

Sheet 3 of 3

83323810 A

4-141

DESCRIPTION

______~~1\~~3~~9~-----

The 4023 circuit is a CMOS
package consisting of three
3-input positive NAND gates.
NOTES:

-----!~51

Symbol sections may appear separately.

Vendor identification:
4023

Package pin configuration:

~~6

____

OR
14

1 ______.r- •

(GHD)

------~~ 4~:D)ooo:9~-

_______~~ )}.;:6::'--___

LOGIC SYMBOL

4023

Sheet 1 of 1

4-142

83323810 A

DESCRIPTION

The 4027 circuit is a CMOS
package consisting of two positive-edge-triggered J-K flipflops with asynchronous set and
clear inputs.

FF
XXX

The functional (logic) diagram
for the 4027 circuit appears as
figure 4-15 in section 4A of
this manual.

5 K

R
4

----~

NOTES:
1.

11-l1~_ _-

4027

Symbol sections may appear separately.
Vendor identification:
4027

19
5

10 J

I 15

Package pin configuration:
16

Voo

0 ~14
~

R
112

Vss B ~_---r

LOGIC SYMBOL

(GNO)

OUTPUT
On+1

INPUTS

= STATE OF a OUTPUT PRIOR TO
CLOCK TIME.

an + I = STATE OF OUTPUT AFTER
CLOCK TIME.

x = DON'T CARE

.J""

0
0

S-

0
0

= CLOCK TIME (L - TO - H TRANSITION)

NO
CHANGE

TRUTH TABLE
TOGGLE

4027
Sheet 1 of 1

83323810 A

4-143

DESCRIPTION
The 4049 circuit is a CMOS
package consisting of six inverting buffers, each capable
of driving up to two TTL loads
when used as a CMOS-to-TTL converter. For that application,
the high-level input voltage
may exceed the TTL supply voltage (VCC).
Pin 16 (normal VOO) is not
connected internally in this
circuit, nor is pin 13.
NOTES:
1.

Symbol sections may appear separately.

Vendor identification:
4049

Package pin configuration:
'tc I

OR
9

16 NC
13 NC

Vss 8

(GNO)

4049
Sheet 1 of 1

4-144

83323810 A

DESCRIPTION
The 10102 is an EeL quad 2-input NOR gate. The last section
provides complementary (OR/NOR)
outputs.
NOTES:
1.

Vendor identification:
MC10102L

Package pin configuration

Vee1

INPUT PINS

OUTPUT PINS

TRUTH TABLE
(LAST SECTION)

16 Vee2
15
14

13
12
11

9
TOP

VIEW

=!Y-

~~
12
13

_15_ _

--:-:D12[=t=15
-13

LOGIC SYMBOL

10102

Sheet 1 of 1

83323810 A

4-145

DESCRIPTION
The 10104 is an ECL quad 2-input AND gate. The last section
provides complementary (AND/NAND) outputs.
NOTES:
1.
2.

Vendor identification:
MC10I04L
package pin configuration

OUTPUT PINS

TRUTH TABLE
(LAST SECTION)

V~t==j
I

INPUT PINS

10104

xxx

__:. .0 . .

14
_ --

-ELJ_15__

4>~

-..;.;;::~~
LOGIC SYMBOL

10104
Sheet 1 of 1

4-146

83323810 A

DESCRIPTION
The 10105 is an ECL triple
OR/NOR gate with a 3-2-2 input
configuration. All sections
provide complementary outputs.
NOTES:
1.

Vendor identification:
MClOl05L

16Vcc2

Vee1 1

3
4

TOP
VIEW

package pin configuration.

6
10105

xxx
7

-.:-0=
.
12~

12D14
13

......
13;...~

LOGIC SYMBOL

10105

Sheet 1 of 1

83323810 A

4-147

DESCRIPTION
The 10106 is an ECL, triple,
4-3-3-input NOR gate.
NOTES:
1.

Vendor identification:
MC10I06L

package pin configuration:

Vee1 1

16 Vcc2

10
9

VEE

TOP
VIEW

LOGIC SYMBOL

10106

Sheet 1 of 1

4-148

83323810 A

DESCRIPTION

The 10116 is an EeL, triple
differential line receiver.
The line receivers are essentially very high speed linear
differential amplifiers with
standard ECL outputs.
If any amplifier is unused, one
input of that amplifier must be
tiad to VBB (pin 11) to prevent upsetting the current
source bias network.
NOTES:
1.

Vee1

When sections are shown
separately, the VR function (pin 11) is shown
only with the last section.
Vendor identification:
MCIOl16L

VEE

16
15

13
12

5
6
7

11
10

Package pin configuration:

5 .....
4 -]

RCVR
10116
xxx

4,..,

-5 ]

9 .....

.....7

9-]

""-01

13 .....
12

TOP
VIEW

10 ....

·'.29 VR

Vcc2

l-15
,..,

12_

RCVR
10116

>L3

",,6
...,

]

,",14

1
·1.29 VR

LOGIC SYMBOL

10116

Sheet 1 of 1

83323810 A

4-149

DESCRIPTION
The 10125 is a quad ECL to TTL
level translator.
NOTES:
1.

2.
3.

When sections are shown
separately, the VR function (pin 1) is shown
only with the last section. The ground (pin
16) is shown for each
section, with the pin
number in parentheses for
the second, third, and
fourth sections.

V..

16 GND

2
3

15
14

13
12

5
6

Vu 8

Vendor identification:
MCl0125L

9 Vee
TOP
VIEW

package pin configuration.

2.J-11

-3

+6V

ECL-+TTL

10125

3
ECL-+TTL

xxx

--10

6
OR

10~

14 ....

10125

·1.29 VR

-1.29 VR

LOGIC SYMBOL

10125
Sheet 1 of 1

4-150

83323810 A

DESCRIPTION
The 10131 is an EeL circuit
containing two master-slave,
type-D FFs. The FFs are controlled either by the set and
reset inputs or by the clock
input used in conjunction with
the D (data) input.
When both the set and reset inputs are low, the FFs are in
the clocked mode and their output states change on the positive transition of the clock.
The resulting change depends on
the intormation present at the
data (0) input.
The FFs have both common and
exclusive clock inputs. The
FFs change separately, under
control of their exclusive
clock inputs, whenever the common clock input is held low.
They change states simultaneously, under control of the
common clock, whenever the exclusive clock inputs are held
low. In either case, the final
state of each FF depends on the
information present at its data
input at the time of the clock.

Vee'

NOTES:

Vendor identification:
role lO 131
Vn

Package pin configuration:

16 Vcc2

3
4

6
7

11
10

TOP
VIEW

10131
Sheet 1 of 2

83323810 A

4-151

(0)

(EXCLUSIVE
CLOCK)

10131

(COMMON

("'.. OCK::

XX"

'.,

(a)

13
S

(a)

10131
xxx

(EXCLUSIVE
CLOCK)

o 14

(0)

LOGIC SYMBOL

TRUTH TABLES
INPUTS
COMMON
CLOCK

EXCLUSIVE
CLOCK

L
L

OUTPUTS

INPUTS

OUTPUTS

DATA

SET

RESET

L
H
NC

H
L
NC

NC
L

H
X
X
X

CLOCKED OPERATION

H • HIGH

L· LOW

SET/RESET
OPERATION

X· DON'T CARE

NC • No change from previous state
NO • Not Defined (Indefinite)

10131
Sheet 2 of 2

4-1~2

33323810 A

DESCRIPTION
The 12040 is a logic network
designed for use as a phase
comparator for EeL-compatible
input signals. It determines
the "lead" or "lag" phase rel.tionship and the time difference between the leading edges
of the waveforms.

PHASE COMPTR
12040
xxx
OA>OB 4
6 OA
",3
OA>OB r• 1~ ~w:

Operation of the 12040 is best
described by assuming that two
waveforms of the same frequency, but differing in phase, are
applied to input pins 6 and 9
(see timing diagram). If the
logic had established by past
history that the waveform at
pin 6 was leading the waveform
at pin 9, the output of the
comparator at pin 4 would be a
positive pulse whose width is
equal to the phase difference;
and the output at pin 11 would
remain low.

oa>OA r0B

OB>OA

LOGIC SYMBOL

If the logic had established by
past history that the waveform
at pin 9 was leading the waveform at pin 6, the output of
the comparator at pin 11 would
be a positive pulse width equal
to the phase difference; and
the output at pin 4 would remain low.
INPUT. PIN

6.J

INPUT. PIN 9

OUTPUT PIN 4

_! J

'-----Ir --

•

: :

I I

.r-

-:t' ~LEAD i i, ____' i'_""

(WHEN PIN 6 LEADS PIN 9) OUTPUT PIN II -: :
(WHEN PIN 9 LEADS 'PIN 6)+U

_ ..---'i

L-

: :

LAG

U
fE--

n,:,

I L
u· -

TIMING DIAGRAM
12040

Sheet 1 of 2

83323810 A

4-153

Both outputs for the sample
condition are valid, since the
determination of lead or lag is
dependent on past edge crossings and initial conditions at
start-up. A stable phase-locked loop will result from
either condition. Phase error
information is contained in the
output duty cycle - that is,
the ratio of the output pulse
width to total period. By integrating or low-pass filtering
the outputs of the comparator,
and by shifting the level to
accommodate EeL swings, usable
analog information for a volt~
age-controlled oscillator can
be developed.

VCC2~TOP

NOTES:
Ven'dor identi f ication:

MC1204'O

Package pin identifica-

tion.

~VIEW
Veel I

7 VEE

1--.---------0

LOGIC DIAGRAM
12040

Sheet

4-154

of 2

83323810 A