Digital PDFs

EK-RK67F-OP-001

February 1978

88 pages

Original

3.8MB

Document:	EK-RK67-OP-001 RK06ex Feb78
Order Number:	EK-RK67F-OP
Revision:	001
Pages:	88
Original Filename:	EK-RK67-OP-001_RK06ex_Feb78.pdf

OCR Text

RK6/7 FTB
operating and service
manual

00
II II

RK6/7 FTB
operating and service
manual

EK-RK67F-OP-001

digital equipment corporation • maynard, massachusetts

1st Edition, February 1978

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

This document was set on DIGITAL's DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
PDP

DEC

DECtape

DECCOMM

UhCU~

KSl:S

DECsystem-lO

DIGITAL

DECSYSTEIvi-20

IviASSBUS

TYPESET-8
TYPESET·II
UNIBUS

VAX

CONTENTS
Page
PREFACE
CHAPTER 1

GENERAL INFORMATION

1.1
1.2
1.3

INTRODUCTION .............................................................................................. 1-1
CAPABILITIES OVERVIEW ............................................................................. 1-1
REFERENCE DOCUMENTS ............................................................................ 1-2

CHAPTER 2

UNPACKING AND ACCEPTANCE TESTS

2.1
2.2
2.3

SCOPE ................................................................................................................ 2-1
UNPACKING PROCEDURE ............................................................................ 2-1
ACCEPTANCE TESTS ....................................................................................... 2-2

CHAPTER 3

CONTROLS AND INDICATORS

3.1
3.2

SCOPE ................................................................................................................ 3-1
OPERATOR CONTROLS .................................................................................. 3-1

CHAPTER 4

UTILIZATION

4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.4
4.5
4.5.1
4.5.2
4.5.3

SCOPE ................................................................................................................ 4-1
BASIC LOOP DESCRIPTION .......................................................................... .4-1
Status Reporting .......................................................................................... 4-1
Interface Description .................................................................................... 4-3
CABLING SETUP PROCEDURES .................................................................. .4-3
Single Port RK06 or RK07 Setup Procedure (without uncabling system) ..... .4-6
Dual Port RK06 or RK07 Setup Procedure (without uncabling system) ........ 4-6
FTB OPERATING INSTR UCTIONS ................................................................ 4-7
HEAD ALIGNMENT ....................................................................................... 4-10
Head Alignment Principles ......................................................................... 4-10
Head Alignment (with FTB) ...................................................................... .4-11
Head Alignment (Program Control) ........................................................... 4-16

CHAPTER 5

MAINTENANCE

5.1
5.2
5.3
5.4

SCOPE ................................................................................................................ 5-1
OFF-LINE TEST PROCEDURE ........................................................................ 5-1
ON-LINE TEST PROCEDURE ........................................................................ 5-10
HEAD ALIGNMENT METER CHECK .......................................................... 5-20
111

CONTENTS (CONT)
Page
APPENDIX A

FTB-TO-DRIVE MESSAGES

A.I
A.2

MESSAGE LINE A .................................. ,.",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,." .................. A-l
MESSAGE LINE B ............................................................................................ A-3

APPENDIX B

DRIVE-TO-FrB STATUS MESSAGES

B.1
B.2
B.3
B.4
B.5
B.6
B.7
B.8
B.9

INTRODUCTION ............................................................................................. B-l
MESSAGE LINE AO .......................................................................................... B-2
MESSAGE LINE BO ........................................................................................... B-3
MESSAGE LINE Al .......................................................................................... B-6
MESSAGE LINE B 1........................................................................................... B-9
MESSAGE LINE A2 ........................................................................................ B-ll
MESSAGE LINE B2 ......................................................................................... B-l1
MESSAGE LINE A3 ........................................................................................ B-12
MESSAGE LINE B3 ......................................................................................... B-12

APPENDIX C

RK6/7 FTB FLOW DIAGRAMS AND BUS MAPS

FIGURES
Figure No.
2-1
3-1
4-1
4-2
4-3A
4-3B
4-4
4-5
5-1
5-2
5-3
5-4
5-5
5-6
A-I
A-?

Title

Page

Field Test Box (Internal View} .............................................................................. 2-2
Field Test Box Backplane ..................................................................................... 2-3
Field Test Box Controls and Indicators ............................................................... 3-2
MESSAGES A and B Status Indicators ............................................................... .4-2
FTB jDrive Interface Lines ................................................................................... 4-3
Drive Module/Slot Layout (RK06 Ddve) ........................................................... .4-4
Drive Module/Slot Layout (RK07 Drive) ........................................................... .4-5
Read/Write Module Test Points ........................................................................ .4-12
Read/Write Heads and Alignment Fixture ........................................................ .4-15
Field Test Box Module Utilization ....................................................................... 5-2
Timing Diagram; Transmission of MESSAGE A to Drive .................................... 5-4
Timing Diagram, Transmission of MESSAGE B to Drive .................................... 5-6
Timing Diagram, Delay ofDISPLA Y-L ............................................................. 5-10
Timing Diagram, WRITE GATE-L ................................................................... 5-18
Timing Diagram, RFAD GA TE-H .................................................................... 5-19
MESSAGE LINE A FTB-to-Drive ..................................................................... A-l
MP~~AGP I fNB B FT:B-~0-D:!'i"e .. ,....................................................................~ 3

FIGURES (CONT)
Figure No
B-1
C-l
C-2
C-3

Title

Page

MESSAGES A and B Drive-to-FTB .................................................................... B-l
RK6/7 FTB Flow Diagram ................................................................................. C-2
Field Test Box, Bus A Map .................................................................................. C-3
Field Test Box, Bus B Map .................................................................................. C-4

TABLES
Table No.
3-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12

Title

Page

Controls and Indicators ........................................................................................ 3-3
Definition of MESSAGE A Bits TO to T15 ........................................................... 5-5
Definition of MESSAGE B Bits TO to TI5 ................................................ " .......... 5-7
Head Counter Operation (Modulo 3) ................................................................... 5-8
Reset of Sequential Address Count (RK07) .......................................................... 5-8
Cylinder Address and Head Count Sequencing ..................................................... 5-9
Reset of Sequential Address Count (RK06) .......................................................... 5-9
Head Counter Operation (Modulo 3) .................................................................. 5-14
Reset of Sequential Address Count (RK07) ........................................................ 5-15
Reset of Sequential Address Count (RK06) ........................................................ 5-16
SWR Display and Head Count ........................................................................... 5-16
Cylinder Address and Head Count Sequencing ................................................... 5-17
Typical Offsets ................................................................................................... 5-22

PREFACE

This manual describes the RK6/7 Field Test Box (FTB). The FTB is designed to test, exercise, and
perform off-line head alignments. Also included is information detailing operator controls and indicators, head alignment, and troubleshooting techniques for testing and isolating disk drive malfunctions.

CHAPTER 1
GENERAL INFORMATION

1.1 INTRODUCTION
The RK6/7 FTB is a self-contained, portable suitcase tester designed to test and exercise an RK06 or
RK07 disk drive off-line directly through the drive's interface hardware. The FTB also provides the
user with a method of testing and aligning an RK06 or an RK07 disk drive with or without a processor. When used in conjunction with the system head alignment diagnostic, it provides the user with a
method of performing on-line alignment verifications.
CAUTION
If a formatted disk pack is used in conjunction with
the FTB for testing puposes, the disk format will be
destroyed (written over) and the pack will have to be
reformatted before it can be used for on-line data
usage.
All write/read data transmissions, disk drive commands, and status messages are connected from the
FTB to the drive via a standard interface cable. A separate cable, adapter, and preamplifier assembly
connect the FTB directly to the drive's write/read module for head alignment.
The FTB is configured so that the head alignment logic is functionally independent from the tester's
interface logic. This feature allows on-line head alignment (without disconnecting the controller/drive
interface cable) using the head alignment diagnostic to run the drive and the FTB to monitor the
readings using the head alignment meter.
NOTE
In order to realize the full potential of the ITB, the
user should have a thorough understanding of the
controller / drive interface logic of both the RK06 and
the RK07 drive. Refer to the RK06/RK07 Disk
Drive Technical Description Manual (EK-RK067TD-001).
1.2 CAPABILITIES OVERVIEW
The FfB is designed around a repetitive loop concept (basic loop) that can be modified through front
panel controls by the operator. The basic loop is designed to put the disk drive through complex
write/read exercises that test both electrical and mechanical operations of the drive. The basic loop
causes the write/read heads to be positioned on all cylinders, to write data on and read data from all
tracks and sectors of the disk pack (simulates system operation), and to check for errors.

1-1

The versatility of the FTB is a direct result of the flexibility by which the basic loop can be modified by
the operator. The options that can be selected via the front panel controls are:
• Halt on errors/ignore errors
• Address a specific cylinder
• Address a specific head
• Positioning only
• Read only
• Write only
c Status reporting
• Continuous/single cycle operation
• Sync on FTB clock (lNT) or drive clock (WRCLK)
• Address all sectors or sector 0 only
• Run interface FAST (normal mode) or SLOW (for scoping ease).
in addiiion to these features, the FTB contains design features that allow the user to diagnose problems in the drive's logic that are very difficult for the system's diagnostics to test. These special features
are as follows.
• Generates A and B parity errors independently
• Generates a multiple drive select (MDS) condition
• Generates a controller power-off condition
• Provides a synthetic clock (INT) for test use in case the drive's WRCLK is not working correctly or is inoperative
• Provides two speeds for interface operation for scoping ease
1.3 REFERENCE DOCUMENTS
It is recommended that the following documents be reviewed prior to using the FTB under actual test
conditions.
EK-RK067-UG-OOI
EK-RK067-TD-OOl
EK-RK067-SV-OOl
EK-RK06-IP-OOl
EK-RK07-IP-OOl

RK06/RK07 Disk Drive User's Manual
RK06/RK07 Disk Drive Technical Description Manual
RK06/RK07 Disk Subsystem Service Manual
RK06 IPB Manual
RK07 IPB Manual

1-2

CHAPTER 2
UNP ACKING AND ACCEPT AN CE TESTS

2.1 SCOPE
The following paragraphs include unpacking and basic acceptance test procedures.
2.2

UNPACKING PROCEDURE
1.

Remove the suitcase (carrying case) from the shipping carton and perform a visual inspection for any signs of damage. Damage claims should be forwarded to the responsible
shipper.

Release and open the carrying case cover. Perform a visual inspection to ensure no physical
damage is evident and that there are no broken controls or indicators.

Release and open the tester's control panel so that internal components can be inspected
(Figure 2-1). Check for loose or broken wires and ensure that the printed circuit boards are
seated properly and are installed in the proper location.

Check the equipment tag on the lower right corner to ensure that the unit lists the proper
line voltage and correct model number (as ordered).

NOTE
Model RK6/7-TA is 115 V, 50/60 Hz; Model
RK6/7-TB is 230 V, 50/60 Hz.

2-1

MA-1083

Figure 2-1

Field Test Box (Internal View)

2.3 ACCEPTANCE TESTS
The RK6/7 Field Test Box is thoroughly tested and certifIed at the factory before it is shipped. Therefore, the following acceptance tests are designed to reaffirm that there was no damage to the tester's
electronics during shipping and handling.
NOTE
If any faults are detected in the following procedures,
refer to Chapter 5 and correct the fault before proceeding to the next step.
1.

Remove the printed circuit boards from the tester.

Connect the tester's line cord to a converiient wall receptacle and turn the tester's ON/OFF
switch to the ON position.

2-2

Check the following pins on the wired backplane (Figure 2-2) for the correct voltage levels.

Voltage Level

AIA2
A2A2
A3A2
A4A2

+5V
+5V
+5V
+5V

DIB2
C4B2

-15 V
-15 V

DID2
D3D2
A4D2
C4D2

+15 V
+15 V
+15 V
+15 V

DIR2
B3F2
D3F2
A4R2

-5 V
-5V
-5 V
-5V

...........

., . / '

c.
•

c.
&.

, ..
(.
C.

<.
t.

(..

(.
~

<
t
(.
t..

c..

(.
~

eo.

(,.

c.
(.

<.
Co

,
Co
"

(..

...
c.

c...

c.
c

c.
(.

<
,

(..
,

,
'-

c..

c,..

t..

r..
'"'

(..

c.. c..

(..
C.

C.
t.

<..

c
"

c:
..

Co
(.

C.
(..

c. ("
(..

<..

(,.

(..

(.
Co

Co
""

Co.

C
C.

(..
'"

c..

c. c. c.
c... c... c.. c.
C.
(..
c..
,
<;.
(.
<.. c. c. G c.. c. t:.
c:..
,
(.,
c... c.. '- c.. c.. <.. Co
to c.. <. (. (. (.. (.. C. <. C.
Co. c..', c. c. t.(.. c

C.
C.

'"
C.

(.
C.

c..

(...

c..

MA-1097

Figure 2-2

Field Test Box Backplane

Turn tester off and disconnect line cord.

Disconnect the dc power cable between the backplane and the power supply.

Install printed circuit boards into tester and check resistance from voltage pins to ground. A
list of the approximate resistance levels that can be expected when measuring from voltage
pins to ground is as follows.

Voltage
Pin
+5 V
+15 V
-15 V
-5 V

Resistance
Level

}

Between on and 10 Kn

Reconnect the dc power cable between the backplane and the power supply.

Install printed circuit boards (Figure 2-1).

Refer to Chapter 5 and perform the off-line checkout procedures outlined in that chapter.

2-3

CHAPTER 3
CONTROLS AND INDICATORS

3.1 SCOPE
This chapter describes the function of each front panel control and places special emphasis on how the
user can vary the basic loop function. Where applicable, potential uses for deviating from the basic
loop function will be described.

3.2

OPERATOR CONTROLS

Figure 3-1 and Table 3-1 illustrate and define the RK6/7 FTB controls and indicators. It should be
noted that the basic loop configuration (except for cylinder switch register switches 20-2 9) consists of
putting all applicable switches in the underlined positions as indicated on the control panel. The
cylinder switch registers (SWR) that are underlined denote cylinder address 245. This defines the
cylinder address which is used during head alignment on an RK06 drive, when an RK06K-AC alignment pack is installed in the drive. The cylinder switch registers that have dots underneath them denote
a cylinder address of 496. This defines the cylinder address that is used during head alignment on an
RK07 drive, when an RK07K-AC alignment pack is installed in the drive.

3-1

DRIVE
TYPE

RK06

DRIVE

~.
~ DESELECT

~ SEEK
p.:.;'t RECALiBRATE

I I

'~ RELEASE

II
.
---!·~I CDI. .- ~I ~
SELECT

EXERC!SE

START SPINDLE

- - - - - !..

STATUS

POLLED
ATTENTION

I
I

~ CLEAR ERROR &

--I1 1 '~
MUL~~~~~RIVE I
~ ~:::~:~::
ATTENTiON

ADDR ESSi NG

CYLINDER

HEAD

SECTOR

ALL

SWR

256 128

. . . . ..

!N~~K ~
HALT ON ERROR
.,~~ " .... "

~'Ut'~
DRIVE DATA/D -+ C PARITY
FAULT
ERROR

ZERO
ONLY

RK06
Xl0=,uIN

METER VALID

-RK06
• RK07 ALIGNMENT TRACK

I
I

SYNC

@@@@@@@~~(@@~
26

SLOW ~ FAST

SWR

512

ONLY

a' - 'a)

SEEK & W/R

SET VOLUME
VALID

SEQUENTIAL

MAX ...

SEEK & READ

---.----"""T'""----,

OSC (SWR f-4 0)

DELAY

~ F~UNCT~~~K

~ OFFLINE

'----------"

~ CONTINUOUS

SiNGLE
CYCLE ~

.~ RTC

SEEK & WRT

1---_ _
0 _ _.L..1_ _

r - LOOP CONTROL ---,

r COMMAND TO RK0617l

RK07

RK07
X 5 = .uIN.

YI
I

MESSAGE
SELECT
2

MESSAGE A

!T15

(~@, 10

Tl4 Tl3

T12

T11 T10

ITo TO 0 0 0 0 0 0 0 0 0 0 0 0 0 0
T13 T12 T1i TlO

PARITY
EVEN

ODD

PARITY
EVEN©ODD

I MESSAGE B

~D~DDmD

INIT
CONTROLLER /F-{\

rk06/07 field tester

PVVR OFF

(@)
VA lOR?

Figl_l!,,~ ~-1

Fidd T~5~ B0.'f. ('0~t!01'l
and Indicators

3-2

Table 3-1

Controls and Indicators

Switch Indicator

Function

DRIVE TYPE
RK06

Puts FTB in mode for testing RK06 disk drive

RK07
EXERCISE/STATUS

Puts FTB in mode for testing RK07 disk drive
In the exercise mode, the tester sends the drive a message, receives MESSAGES A and B (TO-TI5) from the drive, checks
for a drive-to-tester Parity Error or a Drive Fault and then a
Drive Ready. This is done repetitively until a Drive Ready is
generated by the drive and sent to the FTB. When Drive Ready
is received, the write process starts followed by a read. If any
data errors are found during a read operation, the error is
stored and the cycle continues until the revolution is completed;
then it halts operation.
In status mode, the tester formulates a drive message which
requests a return of the message to the FTB as set in the MESSAG E SELECT switch, transmits the message once, receives
back the requested message, and displays it in the MESSAGE A
and MESSAGE B LEDs and halts.
Potential Uses:
If the tester halts on a Drive Fault error in the exercise mode,
status mode may be selected, and START pushed to display any
of the eight message lines (as determined by the SELECT switch
positions). The MESSAGES A and B LEDs can be consulted to
determine the specific error generating the DRIVE FAULT
condition.

DRIVE SELECT

The DRIVE SELECT switch is used to select the drive number
(under test) to which messages will be transmitted. The DRIVE
SELECT switch also determines which drive number will be
transmitted on the polled address interface lines (i.e., 20 , 2 1, and
22).

POLLED ATTENTION

The POLLED ATTENTION LED indicates the condition of
the POLLED ATTENTION interface line. If the drive, whose
address is in the DRIVE SELECT switch, has attention set, the
LED will light.
NOTE
The LED will appear to be lit all of the time.
However, the 2° POLLED ADDRESS line
sent to the selected drive is inverted for a very
short time in order to toggle the drive logic
and to facilitate scoping for troubleshooting
purposes.

3-3

Table 3-1

Controls and Indicators (Cont)

Switch/Indicator

Function

SACK

The SA.CK LED displays the condition of the SELECT ACKNOWLEDGE line transmitted by the drive. It will light after
the drive number (set in the DRIVE SELECT switch) is transmitted to the drive. The SACK LED will only light if the
DRIVE SELECT switch matches the number in the FTB
DRIVE SELECT switch and if the deselect/release bit is negated.

MULTIPLE DRIVE SELECT

The MULTIPLE DRIVE SELECT LED displays the state of
the MULTIPLE DRIVE SELECT line, transmitted by the
drive. The LED will light when the MULTIPLE DRIVE SELECT button is pushed. Pushing the button causes the tester to
assert the INDEX-SECTOR line. When sensing INDEX and
SECTOR assertions other than its own, the drive under test will
detect a MULTIPLE DRIVE SELECT message, assert the
MULTIPLE DRIVE SELECT line, and light the LED.

COMMAND TO RK06/7
NOTE
The next nine switches in the
COMMAND TO RK06/7 block
set message bits which the tester
sends to the drive in message A,
bits T3 through TIl.
DESELECT/RELEASE
I

The DESELECT/RELEASE command sets the drive available
status bit to the other controller in dual-access system configuration. The drive is deselected when this bit is asserted.
A request may be cancelled via a message containing a DESELECT /RELEASE command. Note that no message line status
information is received when such a command is issued.

SEEK

This command directs the drive to seek to the cylinder address
transmitted on MESSAGE LINE B. The selected binary-encoded address is transmitted to the drive with the ieast significant bit first.

RECALl BRA TE

This command directs the drive to seek to cylinder number 0
and to reset the cylinder address register. This command is used
to resynchronize the drive position with its electronics if for any
reason it gets out of step.

3-4

Table 3-1

Controls and Indicators (Cont)

Switch/Indicator

Function

START SPINDLE

This command directs the drive to start its spindle and subsequently to perform a brush cycle and load heads if and only if
the RUN/STOP switch on the front panel is depressed (RUN).
The START SPINDLE command can be used to restart a drive
in the event that a SET MEDIUM OFF LINE command has
caused the heads to unload or any of the error conditions that
unload heads has occurred. Under such conditions, the error
must be cleared before this command will allow the heads to
reload.

RTC

The return-to-centerline (RTC) command is used to reset head
offsets when a write operation is to take place. The clearing of
the offset mode requires 3 ms to complete at which time a
DRIVE ATTENTION is transmitted to the FTB. An RTC
command is implied by any non-zero cylinder seek or upon detection of a write gate in the event that an R TC command is not
detected.

CLEAR ERROR &
ATTENTION

When the CLEAR ERROR & ATTENTION command is asserted, it clears the drive status change flip-flop (DRIVE
CLEAR) as well as clearing all error flags in the selected drive
provided that the errors no longer exist.

20/22 SECTORS

This bit, when asserted, commands 20 sector pulses per disk
rotation; when not asserted, 22 sector pulses are commanded.
Twenty sectors correspond to I8-bit data words; 22 sectors correspond to I6-bit data words. Whenever a change in the format
is made with this select bit, sector pulses cease, until the next
sector 0 at which time the drive is synchronized to the new format.

SET MEDIUM OFF-LINE

This bit, when asserted, unloads the drive heads and stops the
spindle.

SET VOLUME VALID

This bit, when asserted, sets the volume valid flip-flop, thereby
acknowledging a power turn-on, change of cartridge, or the removal of the unit select plug.

LOOP CONTROL
NOTE
All switches in the LOOP CONTROL block (upper right of
panel) allow modification of the
basic loop mode of system operation.

3-5

Table 3-1

Controls and Indicators (Cont)

Switch/Indicator

Function

SI~1GLE CYCLE/
CONTINUOUS

If this switch is moved from the continuous mode to the single
cycle mode, a command is formulated and messages are continuously transmitted and received until DRIVE READY is asserted. Writing and reading are done, errors are checked, and a
new command is formulated in the tester but is not transmitted.
In the single cycle mode, the new message is sent only when the
START pushbutton is pressed, (Le., repetitive operations in the
single cycle mode must be manually initiated by repetitive activation of the START switch.)
Potential Uses:
1. To write on only one track of the disk and have the writing
stop at a track boundary.
CAUTION
Pushing the STOP pushbutton would stop
operations instantly and thus could cause an
error in the current sector because writing
could cease in the middle of a sector.
2. If positioning problems are encountered which cause the
drive to shut itself down, the single cycle feature provides a
method to manually initiate seeks at a very low rate while
scoping the logic.

DELAY

The DELAY knob is an adjustable time delay control that delays tester recognition of DRIVE READY from approximately
220 J.ls to approximately 700 ms. Thus, it offers a method of
adjusting the time between completion of a SEEK and the initiation of a WRITE/READ.
Potential Uses:
1. If the settling time of the servo is taking longer than recommended, increasing the delay before writing could eliminate the data errors and thereby indicate a possible clue to
the problem source.
2. If a problem exists that causes the drive to cease operation,
a long delay between SEEKS will provide additional time
for scoping before the drive stops.
3. Any unwanted resonances could be isolated by varying
(tuning) the time delay between seeks.

3-6

Table 3-1

Controls and Indicators (Cont)

Switch/Indicator

Function

FUNCTION

The FUNCTION switch is used to modify basic loop operations involving positioning, writing, and reading. The modifications (to the basic loop) offered by this switch involve SEEK
ONLY, SEEK & WRT, SEEK & READ, and SEEK & W /R.
Potential Uses:
The positions are useful when working on positioning problems
not involving reading or writing, or when working on data
problems to separate write problems from read problems.

SYNC
INT/WR CLK

In the basic loop mode, the clock source is the interface write
clock which is generated by the drive disk pack. Because difficult-to-detect problems with write clock can cause random data
errors, write clock accuracy is critical and imperative to proper
read/write operation of a drive.
Potential Uses:
To help isolate random data errors, the SYNC switch can be
put in its INT position. This causes the tester to use an internal
oscillator as a system clock and to ignore the interface write
clock. In summary, if random data errors are occurring, and
switching to SYNC/INTernal stops the errors, write clock
problems should be suspected.

CLOCK SLOW IFAST

The main clock on the interface clocks status and command
information between the FTB and the drive. In the fast mode,
the control clock repetition rate is at standard system speed (465
ns/cycle) and in the slow mode, control clock rate is 29.8
JLs/cycle. Slow speed enhances scoping and is also useful in detecting speed problems.

HALT ON ERROR NO/YES

The HALT ON ERROR switch is self-explanatory. The
DRIVE FAULT LED is lit (in exercise mode only) whenever
the interface drive fault bit is asserted by the drive. Simply, this
LED indicates an error detected by the drive. The DA T A/D---+C
PARITY ERROR LED indicates any error detected by the
tester. These may be of two types.
1. Data error (if FUNCTION includes a read)
2. Drive-to-tester parity error.
NOTE
To aid in debugging intermittent problems,
the LEDs will light when errors exist independent of the setting of the HALT ON ERROR switch.

3-7

Table 3-1
Switch/Indicator

Controls and Indicators (Cont)

II Function

NOTE
The ADDRESSING block provides many addressing variations
from the basic loop operation addressing scheme previously described.
SEQUENTIAL

Successive cylinder addresses may be SEQUENTIAL cylinder
addressing, which positions the drive to the address in a register
that is incremented by 1 every cycle (one complete basic loop
cycle).
Example:
Example:

OSC (SWR ~ 0)

Oscillate cylinder addressing positions the drive between cylinder and a cylinder number set in the switch register.

Example:
ALT (SWR ~ SEQUENTIAL)

0, (SWR), 0, (SWR), 0, (SWR), 0, (SWR) ...

ALT (SWR ~ SEQUENTIAL) cylinder addressing positions
the drive between the switch register address and an address in a
register that is incrementing by one every other basic loop cycle.
Example:

SWR

(RK06) 0, 1,2, 3 ... 410, 0, 1,2 .. .
(RK07) 0, 1, 2, 3 ... 814,0, 1,2 .. .

0, (SWR), 1, (SWR), 2, (SWR), 3, (SWR) ...

SWR cylinder addressing positions the drive to the address in
the switch register (and does not change the cylinder address on
sequential loop cycles).

NOTE
In the SWR mode, successive messages call
for the same cylinder (contained in the switch
register) and allow repetitive writing and
reading without performing any SEEKS.

3-8

Table 3-1

Controls and Indicators (Cont)

Switch/Indicator

Function

HEAD ALL/SWR

When the HEAD switch is placed in the ALL position, it causes
all the heads (0, 1, and 2) to write and read on the selected
cylinder in the following sequence after the seek is complete:

W rite head 0, read head
Write head 1, read head 1
W rite head 2, read head 2
Seek to new cylinder address
Write head 0, read head 0, etc.
When the HEAD switch is placed in the SWR position, it causes
only the head selected by switches 2° and 21 to be used for write
and/or reading.
NOTE
Any head (0, 1, or 2) can be selected using
the HEAD SWR switches. The function performed depends on the FUNCTION switch
position.
NOTE
The LEDs under the cylinder and head
switch registers always display the last cylinder and head addresses sent to the drive.
SECTOR ALL/ZERO ONLY

Sectors that are to be written and read may be ALL sectors (20
in 20-sector mode or 22 in 22-sector mode) or sector ZERO
ONLY.

MESSAGE SELECT

When the tester is in the exercise mode, the FTB requests and
receives messages AO and BO only from the drive. This allows
the tester to monitor Drive Ready and Drive Fault for errors. If
an error message is detected and/or the user wants to view the
contents of the other message lines (l, 2, or 3), the status mode
can be selected. Upon actuation of the START button, the FTB
requests and receives the message line selected by the MESSAGE SELECT switch. The selected message line status/error
bits are then displayed in the MESSAGE A and MESSAGE B
LEDs. The message lines A l-A3 and BI-B3 will provide more
specific status/error information concerning the composite error /status that was indicated in the exercise mode in messages
AO and BO.

3-9

Table 3-1

Controls and Indicators (Cont)

Switch/Indicator

Function

PARITY ODD/EVEN

The ~1ESSAGE A and MESSAGE B PARITY switches cause
the tester to transmit wrong (EVEN) parity to the drive independently on MESSAGE A and B lines to ensure that the drive
can detect these errors.

CONTROLLER PWR OFF

The CONTROLLER PWR OFF button is used to verify that
the drive is capable of sensing this line in case a real power loss
occurs at the controller. This interface line is also connected to
the +5 V in the FTB to disable the interface in case tester power
is lost.

INIT

The INIT button generates an assertion on the initialize interface line. It performs the same function as the controller initialize command.

START/STOP

The START and STOP switches start and stop commands and
data from the tester. Operation is not guaranteed if switches are
changed without stopping the tester first. STOP clears the
tester, and all addressing, etc., and will start at an initialized
state when START is pressed and released. If the tester halts on
an error, status may be checked by selecting STATUS and repeatedly pushing START without pushing STOP. In this case,
the tester-formulated message will not change. In the single
cycle mode, repetitive STARTs will increment the tester
whereas a STOP will initialize the tester.

3-10

CHAPTER 4
UTILIZATION

4.1 SCOPE
This chapter stresses general and special operating procedures and describes both the basic loop and
interface principles that are incorporated into the RK06/7 FTB. Also included in this chapter are basic
setup (cabling and connections) and head alignment procedures.
4.2 BASIC LOOP DESCRIPTION
The basic loop setup is the most complicated and thorough test that can be used to exercise and test a
good device drive.
In this mode, the tester sends the drive a message as defined by COMMAND TO RK06/7 and LOOP
CONTROL switch selections and receive status messages in MESSAGE A and MESSAGE B LEDs
(lines AO and BO) from the drive. The tester checks for a drive-to-tester Parity Error, a Drive Fault,
and then a Drive Ready. These steps occur repetitively until a Drive Ready flag is asserted at which
time the selected track is written and read and checked for errors. If no errors are present, the tester
generates the next command. Repetitions of this cycle provide a method of sequencing through all
sectors of all tracks of all cylinders and in that order.
Each cycle monitors and indicates any Drive Fault errors (line BO, bit T7) and any tester-detected
errors (DATA/~C PARITY ERROR). The operator can choose to HALT ON ERROR (YES) or
to ignore an error HALT ON ERROR (NO) and continue the repetitive loop cycle.
High and low frequency patterns (only) will be alternately written in odd and even sectors. These
frequency patterns provide a method of checking the recovery system within its specified frequency
range and to qualify write/read system performance by scoping the ratio between the high and low
frequency amplitudes.
4.2.1 Status Reporting
The FTB can be switched into the status mode at any time (after pushing STOP) for the purpose of
examining the status/error bits in the MESSAGE A and B LEDs (words 00,01, 10, and 11).
NOTE
In the exercise mode, message words AO and BO are
always monitored because they contain the composite Drive Ready and Drive Fault bits which are necessary for basic loop operation.
In the basic loop mode of operation, if a composite error bit is received, the FTB halts on the error and
displays the bit in the MESSAGE AO or BO LEDs. The operator then switches the FTB into the status
mode and views the words received from the drive to determine what error bites) caused the composite
error. Figure 4-1 illustrates the 8-word status messages. A more detailed description of these messages
is given in Appendix A.

4-1

WORD ¢¢
T15

T14

T13

T12

PIP

SPINDLE

DR
RD/WR OFF
B!Zl PARiTY UNSAFE

SPEED

PARITY STATUS

WORD 01
T15

T14

Tl0

Tll

LOCK

VI~

NXF

FAULT

SPARE

LOG
HDS

REV

FWD

SPEED CART DOOR BRUSH HEADS SERVO
OK
PRES LTCHD HOME HOME SIGNAL SPARE

Til

Tl0

1
1

T 3

1
1

I
I

I DRIVE SELEC~ CODE
(1) (0)
I

SPARE

MESS 10

T0
1

DRIVE SELECT CODE
1
I

CYLINDER ADDRESS
I

CYLINDER DIFFERENCE/OFFSET VALUE

CD I

(0)1 (0)

I
WRITE WRCNT
RES FOR
GATE aNO SECTOR
ADD'L MESS
ERR
WRITE
T~A1.?S GATE
I

T8
I

MESS 1D

INDEX MULT HEAD
ERR HD SEL FAULT

T0
I

DRIVE SELECT CODE

RES FOR
ADD'L MESS

RTZ

T12

!NV
ADDR

AC
LOW

PARITY RESVD

SPARES

T10

T2
1

T11

T3
I

T12

T13

PARITY RESVD

~~t !A~~L

T13

SEEK SERVO TRIBIT
SERVO LIM
PARITY UNSAFE DETON a NO. SIG ERR ERR
SEEK MOTION

READY

LOSS

T14

TRACK

PARITY UNLDG
HDS

T15

CoD
SEEK PRTY
INC
LOCK
ERR

WORD 10

20
DRIVE
OFFSET SECT
ON FORMAT TYPE

......

RES FOR
ADD'L MESS

(0) (1)

MESS ID

~ ~

WORD L 1
T15

T14
\

Tl1
1

TlO
I

T9
I

PARITyl
I

T12

T13
I

T5
I

T4
I

I
I

DECODED HEAD
ADDRESS
I
-'CDNOTE' THESE BITS ARE USED ONLY ON THE RK07 DRIVE,

Figure 4-1

I
I

10
I ADD'L
RES FOR
I MESS
Ii
(1) (1)
MESS i
i

!v1ESSAG ES A and B Status Indicators

4-2

T0
I

DRIVE SELECT CODE

SECTOR COUNT
I

DRIVE SERIAL NUMBER

I
IIRESVD RESVDI
PARITY!RESVD

T7
I

CP -29 42

4.2.2 Interface Description
Communication between the FTB and the drive under test is accomplished via a 17-signal serial data
and control signal interface cable. Signals for drive selection, commands, addressing, and status reporting are handled serially on two signal pairs, message lines A and B (Figure 4-2). The remaining
lines consist of read/write data, timing and control, and attention flag signals.
4.3 CABLING SETUP PROCEDURES
The FTB is connected to the disk drive via the A or B port bus interface. Thus, when the tester is
connected to either interface, the corresponding access switch (A or B) on the drive's front panel must
be enabled (pressed in) and the other switch must be disabled. Depending on the access port (A or B)
being used in the system configuration, an M7706 Interface and Timing logic module will be in slot 2
(B port) or slot 3 (A port). Refer to Figure 4-3.
In the case of a dual access drive system configuration, one of the daisy-chain bus interfaces (A or B)
must be temporarily disconnected so that the tester can be connected. In this configuration, one of the
controllers and one disk subsystem will be disconnected until the tester box and cabling are removed
and the system configuration is returned to normal.

READIWRITE DATA
MESSAGE LINE "A"
MESSAGE LINE "B"
STROBE
WRITE GATE
CONTROLLER-TO-DRIVE (CTD)
CONTROL CLOCK
INITIALIZE
POLL DRIVE 22

FTB

POLL DRIVE 2'
POLL DRIVE 2°
CONTROLLER POWER ON

RK06
OR
RK07
DRIVE

SELECT ACKNOWLEDGE (SACK)
MULTIPLE DRIVE SELECT
INDEX/SECTOR PULSES

WRITE CLOCK
POLLED ATIENTION

CP-2949

Figure 4-2

FTB /Drive Interface Lines

4-3

8~1

___________________________TR_A_C_K__PO_S_I_T_IO_N_S_E_N_S_O_R_M__77_0_8__________________________~

Ii ;;:)t::nVU
t:.'r'n\ II""\.
..,,,:1"\ I
1"\1'\II"\LU\l i \.. D IVIII'£~ I

.....

i
MAINTURUN
SERVO RELEASE
SW2

SERVO CONTROL LOGIC M7707

UUUUUUUUO

"""'''''

VEL~
POT

, RUN~MAINT
SAFETY
SW2

A .... A I " , . . .

CYL. ADDR.

28 27 2 6 25 24 2 3 22 2' 20

RTZ

LD
REV FWD
HDS

DRIVE CONTROL LOGIC M7705

I UNLO HOSO o BRUSHES

l@ qmo

u uu

OFF- 2°2 i
SET L......-I
HD

OKI

SPEED OK POT
I
DUAL-PORT DRIVE CONTROL LOGIC M7730 (SEE NOTE 2)

A B
SEIZED

00
A

INV~NORM

1
REQUESTED INTERFACE & TIMING LOGIC M7706 (SEE NOTE 1)
u

PORT B ADDRI
INV SW

DRIVE SELECT A

INTERFACE & TIMING LOGIC (M7706) (SEE NOTE 1)

DRIVE

~LECT B

CABLE BOARD

I
!

(DC POWER CONN.)

PORT J2

OU~' 0

POR~i 0

0 I 0u

(f)

'1 zz

OUT J1
POR;,

a::
0

I-

I::J

IN J3
PORT

Q..

I::J

NOTES
1. T'vVO M7706 BOARDS USED VliiTH DUAL
ACCESS ONLY; OTHERWISE ONLY ONE IS
USED AS FOLLOWS:
IN SLOT 2 WHEN B ACCESS IS
SELECTED.
IN SLOT 3 WHEN A ACCESS IS
SELECTED.
2. DUAL PORT LOGIC USED ONLY WITH
DUAL ACCESS OPTION

I-

o IJ ~I

Bj 0

CP-2456

Figure 4-3A

Drive Module/Slot Layout
"
unve)

,- -- -,

~K1\...VO

4-4

TRACK POSITION SENSOR M7908
8

I
IRUNL-JMAINT

SERVO
ANALOG PCB M7906

~OFFSEV~~
ADJ

SAFETY
SW2
6

SERVO CONTROL LOGIC M7907

OOUOOOOOOO 0

MAINT L-.J RUN
SERVO RELEASE
SW1

ADJ

2 9 2 8 27 2 6 2 5 24

2 3 22 2' 2 0

OFFSET

00 0

2 0 2'

LD FWD REV
HDS

DRIVE CONTROL LOGIC M7705

IUNLD HDSU

RTZ

HDS

~ U6~EED

OBRUSHES

SPEED OK POT
DUAL PORT DRIVE CONTROL LOGIC M7730 (SEE NOTE 2)
4

A B
SEIZED

AB
REQUESTED

INTERFACE &
TIMING LOGIC M7706 (SEE NOTE 1)

INVL-.JNORM
PORT B ADDR
INV SW

0
DRIVE SELECT A

INTERFACE & TIMING LOGIC M7706 (SEE NOTE 1)

DRIVE SELECT B
CABLE BOARD

I
I

(DC POWER CONN)

'--

POR;lo
OUT

0
PO~~I 0
PO~il 0
J4

POR~I
OUT

o I' u

CJ)

a::

01
01

z
z

u
t-

:::J

a..
t-

:::J

NOTES
1. TWO M7706 BOARDS USED WITH DUAL
ACCESS ONLY; OTHERWISE ONLY ONE IS
USED AS FOLLOWS:
IN SLOT 2 WHEN B ACCESS IS
SELECTED.
IN SLOT 3 WHEN A ACCESS IS
SELECTED.
2. DUAL PORT LOGIC USED ONLY WITH
DUAL ACCESS OPTION.

"t:::J

o IJ z

a..

MA-0923

Figure 4-3B

4-5

Drive Module/Slot Layout
(RK07 Drive)

4.3.1

Single Port RK06 or RK07 Setup Procedure (without uncabling system)
1. Disable the port currently in use.
2,

Press the RUN/STOP pushbutton on drive to the STOP position.

3. Turn power off to the disk drive.
4.

Remove the rear cover from the disk drive unit.

5. Pull the card cage open (out and downward) and inspect logic to determine which port (A or
B) is currently being used in the system confIguration.
6.

Remove the M7706 module and install it in the alternate slot position (i.e., if A port is used,
remove M7706 from slot 3 and install in slot 2 for B port.)

7. Connect "spares" interface cable to PORT B IN (J3B) on the INPUT jOUTPUT connectors.
8. Connect "spares" terminator block into PORT BOUT (J4B).
9. Connect the other end of the "spares" interface cable to connector on FTB front panel.
10. Turn on power to the disk drive.
11. Remove system data disk pack from drive.
12. Instali a known good scratch pack into drive.
13. Push B port switch in (the new port just cabled up to the FTB).
NOTE
This will be access switch A if PORT A IN is used in
steps 4, 5, and 6.
14. Connect the FTB's line cord to the same ac power source as that of the drives.
15.

Refer to Paragraph 4.4 for operating instructions.

4.3.2 Dual Port RK06 or RK07 Setup Procedure (without uncabling system)
In the following procedure, it is assumed that this is the initial setup procedure for a dual port system.
Therefore, many of the steps outlined in the single port setup procedure (Paragraph 4.3.1) are also
listed here for clarity purposes in cabling a dual port system. It should be noted that a dual port system
consists of two controllers with up to eight drives on each controller. Thus, one controller and all of its
drives will be disconnected to faciliate testing of the drive.
1. Press the RUN jSTOP pushbutton on the drive (to be tested) to the STOP position.
2. Turn off power to the disk drive.

4-6

Remove the rear cover from the disk drive unit.

Pull card cage out and downward.

5. Remove daisy-chain cable from PORT A IN (J1A) or from PORT B IN (J3B).
6. Connect "spares" interface cable into the selected port (PORT A IN or PORT BIN).
7. Connect "spares" terminator block into selected port out connector (PORT A OUT OR
PORT BOUT).
8. Connect the other end of the "spares" interface cable into the connector on the FTB front
panel.

9. Turn on power to the disk drive.
10. Remove system data disk pack from drive.
11. Install a known good scratch pack into drive.
12. Push A or B port switch in (depends on port chosen in step 4 and the one that is now
connected to the FTB).
13. Connect the FTB's line cord to the same ac power source as that of the drives.
14.

Refer to Paragraph 4.4 for operating instructions.

4.4 FTB OPERATING INSTRUCTIONS
The cabling setup procedures outlined in Paragraph 4.3 must be performed before initializing the disk
drive/FTB configuration. Once the cabling is complete, the operating procedures for exercising and
testing the drive from the FTB are the same for both types of system.
NOTE
Steps 1 through 4 of the following procedure initializes both the drive and tester for test purposes.

Perform initial FTB test setup by setting the front panel controls as follows.
Control

Position

DRIVE TYPE

Up (RK07) for testing RK07 drive
Down (RK06) for testing RK06 drive

EXERCISE/ST ATUS
DRIVE SELECT

EXERCISE
Same as drive under test

4-7

COMMAND TO RK06/7
DESELECT/RELEASE
SEEK
RECALIBRA TE
START SPINDLE
RTC
CLEAR ERRO'R & ATTENTION
20/22 SECTORS
SET MEDIUM OFF LINE

SET VOLUrvfE VALID

To the left (negated)
To the left (negated)
To the left (negated)
To the left (negated)
To the left (negated)
To the left (negated)
Tn th ... ~~n:ht (22\
"''''''H'''~~5~''
)
To the right (asserted)
To the ieft (negated)

LOOP CONTROL
C'T~T~ T "C' I"""'VI"""'T "C' Il"""'n1\.TTT1\.TT TnT TC"
" ' . l " ' - ' L L ' - ' . '-'LL/ '-'V 1 'I .l.l1'1 uvu~

~Vl"l

FUNCTION
SYNC
CLOCK
HALT ON ERROR

SEEK ONLY
WRCLK
FAST
NO

r'I"1Ir.TTT1Ir.TT T"T TiC'"

111"1 UVU",

ADDRESSING

CYLINDER
CYLINDER SWITCH REGISTER (2 0-2 9 )
HEAD
Head Switch Register (2 0-2 1)
SECTOR

SWR
All down (negated)
SWR
Down (negated)
ZERO ONLY

MESSAGE A and B PARITY

ODD

Perform the following steps to start the disk drive from the drive's control panel.
a.

Press the STOP pushbutton on the tester.

Press the drive's RUN/STOP to the RUN position. The spindle motor should start
and when up to speed, the heads will load and stop on cylinder O.

Perform the following steps to stop the disk dive from the tester.
NOTE
The initial FTB setup outlined in step 1 is configured
to stop the drive when the START pushbutton is asserted.
a.

Press the START pushbutton on the tester. The carriage assembly will retract and
unioad the heads to the Hhome" position. The spindie motor wiB then come to a gradual stop.

4-8

Perform the following steps to start the disk drive from the tester.
a.

Set the following front panel controls on the tester as indicated.
Control

Position

START SPINDLE
SET MEDIUM OFF LINE
SET VOLUME VALID

To the right (asserted)
To the left (negated)
To the right (asserted)

Press the START pushbutton on the tester. The spindle motor should start and when
up to speed, the heads will load and stop on cylinder o.
NOTE
Assertion of the tester's START/STOP pushbuttons
will now start and stop tester operation. In order to
stop the disk drive (unload heads etc.), the STOP
pushbutton must be pressed (asserted) and the SET
MEDIUM OFF LINE asserted (to the right),
START SPINDLE negated (to the left), and SET
VOLUME VALID negated (to the left), followed by
ST ART. Reverse the above procedure to start the
drive (load heads etc).

If the drive to be tested is a known good drive, the basic loop mode can be used to exercise
the drive. To initiate basic loop operation, perform the following steps.
a.
b.

Press the STOP pushbutton on the tester.
Set the FTB front panel controls to the following positions.
Control

Position

EXERCISE/STATUS
DRIVE SELECT

EXERCISE
Same as drive under test

COMMAND TO RK06/7
DESELECT/RELEASE
SEEK
RECALIBRA TE
STAR T SPIND LE
RTC
CLEAR ERROR & ATTENTION
20/22 SECTO RS
SET MEDIUM OFF LINE
SET VOLUME VALID

4-9

To the left (negated)
To the right (asserted)
To the left (negated)
To the right (asserted)
To the left (negated)
To the left (negated)
To the right (22)
To the left (negated)
To the right (asserted)

LOOP CONTROL
SINGLE CYCLE/CONTINUOUS
FUNCTION
SYNC
CLOCK
HALT ON ERROR

CONTINUOUS
SEEK & 'VIR

"Tn r"IT TT
W.I\.\...,Lh.

FAST
YES

ADDRESSING
CYLINDER
ALT (SWR SEQUENTIAL)
CYLINDER SWITCH REGISTER (2°-2 9 )All down
HEAD
ALL
SECTOR
ALL
MESSAGE A and B PARITY

ODD

Press the START pushbutton on the tester. The disk drive should perform alternate seeks
[ALT (SWR+-+SEQUENTIAL)] and write/reads (SEEK and W /R) on all heads (ALL) and
all sectors (ALL).

Observe MESSAGE A and MESSAGE B status LED for error indications. If any errors
occur, the tester will halt operation [HALT ON ERROR (YES)].

If a Drive Fault occurs, set the EXERCISE/STATUS switch to the STATUS position and
check each status message line using the MESSAGE SELECT switch. Refer to Appendix B
for a detailed description of the status messages.

To stop the drive from the tester, press the STOP pushbutton and set the SET MEDIUM
OFF LINE to the right (asserted), START SPINDLE to the left (negated), and SET VOLUME VALID to the left (negated). Press START on the tester. The heads will retract and
the carriage assembly will move to the "home" position. The spindle will slow down and
come to a gradual stop.

4.5 HEAD ALIGNMENT
The RK6/7 FTB contains functionally independent circuitry and hardware for performing read/write
head alignment. The READ/WRITE signal is amplified and displayed on the dc microamperes meter
on the FTB's control panel. This is similar to the manner in which the disk drive processes the tracks
following servo signals.
4.5.1 Head Alignment Principles
There are several critical principles that must be understood before attempting head alignment. These
principles make the head alignment procedure easier to understand and will help avoid damage or
improper alignments of the heads. These principles are as follows.
1.

Do not attempt to perform head alignment on a malfunctioning drive. The head alignment
procedures are based on the assumption that the drive being aiigned is a properiy operating
drive.

The drive's WRITE PROT switch should always be asserted (on) when an alignment pack is
installed in the drive. As an additional precautionary measure, set the safety switch (S2) on
module M7729 (on the RK06) or M7906 (on the RK07) to the MAINT position. This
..~~ .. ,,-~ --"' .. "' .... +... +l.", l."'n~ ... r.. "" ......
1,..n~; .... n ;r n "''''
.. ",.. """"''1f"" ........ "r!,t, ..... " ........... l11'C r!111'11"10 t,Po:lrl
1""U"' .............. 1-"' .......... ,..,.&.1.""..., "' ................. """- ....... ...., ...... " ........... -.... ........ ""- .............. 0 ....... .... _ ... , - _ .......... - ... - -_ ....... __ ............. - - - - - ....
----alignment.
11 ....

--~----o

4-10

Do not apply more than minimum lateral force to the carriage when performing head alignment. Excessive force will cause damage to the heads, pack, and positioner.

The head alignment fixture and positioner parts are precision mechanical devices and must
be handled carefully.

Use recommended tools and fixtures to ensure that critical alignments are secure and to
avoid damage to the precision parts and fixtures.

Power up the disk drive and allow it to run for 2 hours before attempting head alignment.

Install the correct alignment pack (RK06K-AC for an RK06 drive, RK07K-AC for an
RK07 drive) and allow it to rotate 1/2 hour prior to beginning head alignment.

The servo head is fixed and only the data heads are aligned.

4.5.2 Head Alignment (with FTB)
The following equipment is required.
•
•
•
•
•
•

RK6/7 Field Test Box
Head alignment fixture
Torque wrench (adjustable) from 2 to 5 in-lb
Hex bits (0.062 and 0.093 bits)
RK06K-AC alignment cartridge (for aligning heads on an RK06)
RK07K-AD alignment cartridge (for aligning heads on an RK07)
1.

Refer to FTB operating procedures (Paragraph 4.4) for tester setup and operating procedures.

Stop the disk drive from the tester
a.
h.
c.
d.
e.

Press the FTB's STOP pushbutton.
Set the SET l\1EDIUM OFF LINE switch to the right (asserted).
Set the START SPINDLE switch to the left (negated).
Set the SET VOLUME VALID switch to the left (negated).
Press the FTB's START pushbutton.

After the drive spindle stops, remove the scratch pack and install an alignment pack.

Remove the rear cover from the disk drive and trip the main circuit breaker to the OFF
position.

Pull the card cage open (out and downward) and set the safety switch (S2) on the M7729 (on
an RK06) or M7906 (on an RK07) module to the MAINT position.

Press the WRITE PROTECT switch on the drive's control panel to the on position (asserted). This provides dual protection against accidently writing on the alignment pack.

Secure the read/write preamplifier (from FTB) to the drive's base casting using the Velco
strips that are provided.

8. Connect the FfB's head alignment preamplifier plug into the drive's read/write pins. On
early-model drives, an adapter is used to connect the head alignment cable to the read/write
module along with a ground lead (Figure 4-4).

4-11

READ/WRITE PINS
TP1. TP2

IRK071
Figure 4-4

Read/Write Module T est Pomts
.
4-12

Set the following switches on the FTB.
Control

Position

EXERCISE/STATUS
SINGLE CYCLE/CONTINUOUS
LOOP FUNCTION
SYNC
CYLINDER ADDRESSING
CYLINDER SWITCH REGISTER (20-2 9 )

EXERCISE
SINGLE CYCLE
SEEK ONLY
INT
SWR
All underlined switches up (asserted)
for an RK06
All dotted switches up (asserted) for
an RK07
SWR
Down (i.e., head zero selected)

HEAD
HEAD SWITCH REGISTER (20_2')

10. Set the main circuit breaker on the disk drive to the ON position.
11. Perform the following steps to start the disk drive from the tester.
a.
b.
c.

Set the START SPINDLE switch to the right (asserted).
Set the SET MEDIUM OFF LINE switch to the left (negated).
Set the SET VOLUME VALID switch to the right (asserted).

12. Press the START pushbutton on the tester. The spindle motor will start and come up to
speed and the heads will load. The drive will do a single seek to cylinder 245 if the underlined
cylinder switches were asserted (RK06 alignment), or to cylinder 496 if the dotted cylinder
switches were asserted (RK07 alignment).
13. Check that the METER VALID LED lights and does not flash and the meter does not peg.
Check that the appropriate drive type LED (to the left of the meter) is lit.
14. Read/write head 0 is now selected, since both head register switches are down (see Step 9).
15. Select head 1 by asserting switch 20 located under the HEAD SWR and pushing START.
Check that the METER VALID LED lights and does not flash and the meter does not peg.
16. Select head 2 by asserting switch 2' and pushing START. Check that the METER VALID
LED lights and does not flash and the meter does not peg.
)
U.e. O:t 50p Z /J.
17. If all read/write heads are within tolerance (Le.: 0 ± 1.0 /-LA), the test is complete and no
adjustments are necessary. However, if any (or all) heads fail to meet the recommended
tolerance, they must be adjusted using the head alignment fixture.
18. Stop the disk drive from the tester.
a.
b.
c.
d.
e.

Press the FTB's STOP pushbutton.
Set the SET MEDIUM OFF LINE switch to the right (asserted).
Set the START SPINDLE switch to the left (negated).
Set the VOLUME VALID switch to the left (negated).
Press the FTB's START pushbutton. The carriage will retract to the home position and
unload heads and the spindle will slow to a gradual stop.

4-13

19. If no alignments are necessary, remove the alignment pack and head alignment cabfes from
the drive and return the drive to normal operation. If alignments are required, continue with
the next step in this procedure.
20.

V/ith the read/write heads unloaded, install the head alignment fixture on the head needing
alignment as illustrated in Figure 4-5.
NOTE
Turn both vertical adjustment screws fully counterclockwise (ccw) to facilitate installation of the fixture.

21.

Using the torque wrench, tighten the head alignment fixture hex-head mounting screw to 5
in-lb. Loosen the read/write head set screw and torque it to 2 in-lb.

22.

Perform the following steps to start the disk drive from the tester.
a.
b.
c.
d.

23.

Set the START SPINDLE switch to the right (asserted).
Set the SET MEDIUM OFF LINE switch to the left (negated).
Set the SET VOLUME VALID switch to the right (asserted).
Set the head needing alignment in the HEAD SWR switches.

Press the FTB's START pushbutton. The drive will do a single seek to cylinder 245 (for an
RK06 head alignment) or to cylinder 496 (for an RK07 head alignment).

24. To move the read/write head toward the spindle, adjust the forward vertical adjustment
screw using the 5 in-Ib torque wrench. To move the read/write head toward the carriage
assembly, adjust the rear vertical adjustment screw using the 5 in-Ib torque wrench.
NOTE
The head alignment fixture set screws operate on a
ramp, fighting each other. Therefore, one of the set
screws must always be in the fully counterclockwise
(ccw) position to ensure proper adjustment.
25.

Adjust the head alignment set screws until the head alignment meter indicates 0 ± jo /lA and
the METER VALID LED glows steadily.
tit. O!:. SOjA.,z AI:

26.

Adjustment is complete when both vertical adjustment screws are loose (no forward or
reverse tension) and the head alignment meter indicates 0 ± 10 /lA.
e't. 0 ± SOjA IN.
27. Perform the following steps to stop the disk drive.
a.
b.
c.
d.
e.

28.

Press the STOP pushbutton on the tester.
SET MEDIUM OFF LINE switch to the right (asserted).
Set the START SPINDLE switch to the left (negated).
Set the SET VOLUME VALID switch to the left (negated).
Press the FTB's START pushbutton.

Tighten the head set screw to 5 in-lb.

4-14

DISK HEAD
(DATA) (HEAD 1)
VERTICAL ADJUSTMENT
SCREWS

SERVO HEAD
~NOT ADJUSTABLE)
DISK HEAD
(DATA) (HEAD 2)

HEAD
ALIGNMENT
TOOL

IRK061
HEAD SET SCREW
FIXTURE MOUNTING
SCREW
DISK HEAD
(DATA) (HEAD 0)
DISK HEAD
(DATA) (HEAD 1)
VERTICAL ADJUSTMENT
SCREWS

SERVO HEAD
(NOT ADJUSTAB LE)

DISK HEAD
(DATA) (HEAD2)

IRKo71
HEAD SET SCREW
FIXTURE MOUNTING
SCREW

Figure 4-5

MA-l076

Read/Write Heads and Alignment Fixture

4-15

29.

Perform the following steps to start the disk drive.
a.
b,

Set the START SPINDLE switch to the right (asserted).
Set the SET MEDIUM OFF LINE switch to the left (negated),
~of fl."" ~J:;'T

U'-'L

LU'-'

UL.J.I.

''',"\T
T Tl\,fJ:;' "A
T Tn C'nl~f,...h fn fl.o .. ~nhf loC'C'"" .. f""ri\
Y'-'L.JVJ.1'.I.L.J
l' ~J.....;.I..LJ ":'.-.11.'-'11 I. ..., 1.11'-' 115U!' \U":''':''-'IL'-'U}_

Press the FTB's START pushbutton

30.

Check the head alignment meter to ensure that head alignment adjustments are within the
specified tolerances. If adjustments fail, repeat steps 25 through 30.

31.

Stop the disk drive (see step 27) and remove the head alignment fixture.

32.

Repeat steps 20 through 31 and verify alignment for read/write heads 1 and 2.

33.

When the alignments are complete, stop the disk drive and the tester and remove the alignment pack.

34.

Set the safety switch (S2) on the M7729 (on an RK06 drive) or M7906 (on an RK07 drive)
servo module to the normal position and deselect the WRITE PROT switch on the drive's
control panel.

35.

Remove the head alignment cable and preamplifier from the disk drive.

36.

Return disk drive to system configuration.

4.5.3 Head Alignment (Program Control)
The following equipment is required for RK06 or RK07 drive head alignment via program control.
• Head alignment program (MAINDEC Il-DZR6N) -:;'"
• RK6/7 Field Test Box (FTB)
• Head alignment fixture
• Torque wrench (adjustable) 2 and 5 in-Ib
• Hex bits (0.093 and 0.062 bits)
• RK06K-AC alignment cartridge (for aligning heads on an RK06)
• RK07K-AC alignment cartridge (for aligning heads on an RK07)

Press the drive's RUN/STOP pushbutton to the STOP position.

Remove the rear cover from the drive unit and trip the main circuit breaker to the OFF
position.
CAUTION
Ensure power is removed (OFF) from both the FTB
and the disk drive before attaching the alignment
cable to the read/write board.

Pull the card cage open (out and downward) and set the safety switch (82) on the M7729 (on
an RK06 drive) or M7906 (on an RK07 drive) servo module to the MAINT position.

Press the WRITE PROTECT switch on the drive's front panel to the on position (asserted).
This provides dual protection against accidentally writing on the alignment pack.

5. Secure the read/write preamplifier (from FTB) to the drive's base casting using the Velcro
strips that are provIded.

4-16

6. Connect the FTB's head alignment preamplifier plug into the drive's read/write pins that
are available for this purpose. On early model drives, an adapter is used to connect the head
alignment cable to the read/write module along with a ground lead (Figure 4-4).
7. Set the main circuit breaker on the disk drive to the on position.
8. Connect the FTB to ac power source (same as drive's, if possible) and turn the tester ON.

9. Load MAINDEC-ll-/ZR6N into the computer and start at address 224 (Figure 4-6).
10. Install the alignment pack into the disk drive (per program instructions).
11. Respond to program printout as illustrated in the sample program printout (Figure 4-6).
a.
b.
c.
d.
e.

MANUAL OR AUTO MODE (M or ~)? =.A ,}/I
ENTER DRIVE NO. (0-7): = 0
ALIGN, VERIFY, OR EXERCISE (A, V, or E)? = A
ENTER HEAD NO. (0-2): = 0
TYPE R WHEN READY: = R

12. Check that the carriage does a single seek and that the program printout indicates that the
heads are at cylinder 365 octal (RK06) or.J.Hi octal (RK07).
-'(,0

13. Verify that the METER VALID LED lights and does not flash and that the meter does not
peg.

(i..e:J

14. Repeat step 13 for head 1 and 2.

± SOp 7. Al/l)

15. If all read/write heads are within tolerance (i.e., 0 ± 10 JIA), the test is complete and no
adjustments are necessary. However, if any (or all) heads fail to meet the recommended
tolerance, they must be adjusted using the head alignment fixture.
16. If no alignments are necessary, type < iC> to exit the program and set the driver's
RUN /STOP pushbutton to the STOP position. Remove the alignment pack and head alignment cables from the drive and return the drive to normal operation.
If adjustments are required, continue with the next step in this procedure.
17. Type < i c> to exit the program. The carriage will retract to the home position and unload
the heads.
18. Set the drive's RUN/STOP pushbutton to the STOP position.
19. With the read/write heads unload, install the head alignment fixture as illustrated in Figure
4-5.
20.

Using the torque wrench, tighten the head alignment fixture hex-head mounting screw to 5
in-lb.

21. Loosen the read/write head set screw and torque it to 2 in-lb.
22. Set the drive's RUN /STOP pushbutton to the RUN position and load the MAINDEC-IIDZR6N as outlined in step 11.
4-17

DZR6N-D - RK611/RK06-RK07 SUBSYSTEM VERIFICATION

PART 2

*** RK06-07 HEAD ALIGNMENT AID ***
FOR HELP TYPE H, ELSE CR
H
INSTRUCTIONS FOR USING RK06-RK07 HEAD ALIGNMENT AID :
***************************************************
MOUNT AN RK06 OR RK07 ALIGNMENT CARTRIDGE ON THE DESIRED

DRIVE, AND INSURE THAT THE DRIVE IS WRITE-LOCKED.
CONNECT THE ALIGNMENT INDICATOR TO THE DESIRED DRIVE,
VIA THE HEAD ALIGNMENT CABLE ONLY, AND CYCLE UP THE
DRIVE. AFTER MOUNTING THE PACK ON THE DRIVE,
THE OPERATOR SHOULD WAIT 30 MINUTES FOR THE DRIVE
TEMPERATURE TO STABILIZE, BEFORE PROCEEDING WITH
ALIGNMENT.
RESPOND TO ALL REQUESTS FOR PA~~ETERS, BY ENTERING
THE DESIRED PARAMETER VALUE (NO <CR') NEEDED).
THERE ARE TWO MODES OF OPERATION : MANUAL MODE
ALLOWS SELECTION OF DRIVES AND HEADS BY TTY INPUT,
AND AUTO MODE ALLOWS DRIVES AND HEADS TO BE SELECTED
BY OFF-ON OPERATION OF DRIVE PORT SELECT SWITCHES.
IN EITHER MODE, UP TO 5 MINUTES OF SEEK EXERCISES
MAY BE REQUESTED FOR EACH DRIVE.
ALSO IN EITHER MODE, A VERIFY OPERATION ALLOWS HEAD
SELECTION WITHOUT THE UNLOADING AND LOADING OF
THE DRIVE BY THE PROGRAM, WHICH OTHERWISE OCCURS
TO ALLOW MANIPULATION OF THE ALIGNMENT TOOL.
TO RESTART EITHER t-10DE, TYPE "z .
TO RESTART ALIGNMENT AID, TYPE ". R .
TO SELECt NEW [)RIVES IN MANUAL MODE, TYPE A C •
FOR HEAD ALIGNMENT PROCEDURE, REFER TO FIELD
TEST BOX (RK06-07TA, RK06-07TB) OPERATOR'S MANUAL.
MANUAL OR AUTO MODE (M OR A)?
M

* MANUAL SELECT MODE *
ENTER DRIVE NO. (0-7):

DRIVE SER. NO.

ALIGN, VERIFY OR EXERCISE (A, V, OR E)?
A
Figure 4-6

Sample Program Printout (Sheet 1 of 2)

4-18

* MANUAL SELECT ALIGNHENT *
ENTER HEAD NO.

(0-2)

TYPE <R':> WHEN READY:,
R

HEADS POSITIONED AT CYLINDER 365 (OCT)
HEAD 0 SELECTED
ENTER HEAD NO. (0-2)
1
TYPE <" R~ WHEN READY:
R

HEADS POSITIONED AT CYLINDER 365 (OCT)
HEAD 1 SELECTED
ENTER HEAD NO. " (0-2)
2
TYPE

<R') WHEN READY:

HEADS POSITIONED AT CYLINDER 365 (OCT)
HEAD 2 SELECTED
ENTER HEAD NO. (0-2) :

ALIGN, VERIFY, OR EXERCISE (A, V, OR E) ?
E

TYPE <R") WHEN READY
R

*RANDOM SEEK EXERCISES IN PROGRESS ON DRIVE 0
AZ
ALIGN, VERIFY, OR EXERCISE (A, V, OR E) ?
V

• MANUAL SELECT VERIFY *
ENTER

HEAD NO.

(0-2)

HEADS POSITIONED AT CYLINDER 365 (OCT)
HEAD 2 SELECTED
ENTER HEAD NO.
AZ

Figure 4-6

(0-2) :

Sample Program Printout (Sheet 2 of 2)

4-19

N
01:5 0
.
23. Adjust the head alignment set screws until the head alignment meter indicates 0 ± ~ p.A and
the METER VALID LED glows steadily. Tighten the read/write head set screw to 5 in-lb.
24.

Reneat 17 throui!h 23 for heads 1 and 7.
~.!-

---

---- -

--g--

---

------

----

25. When adjustments are complete, type < iC> to exit the program. Set the drive's
RUN/STOP pushbutton to STOP position,
26.

Remove the head alignment fixture.

27.

Repeat steps 9 through 15 to ensure that alignment is within specifications.

28. When alignments and verifications are complete, stop the disk drive and remove the alignment pack and head alignment cables.
29.

Set the safety switch (S2) on the RK06 M7729 or RK07 M7906 servo module to the normal
position and deselect the WRITE PROT switch on the front panel of the drive.

30.

Return the drive to the system configuration.

4-20

CHAPTER 5
MAINTENANCE

5.1 SCOPE
This chapter provides a complete description to aid service personnel in isolating and repairing faults
in the FTB circuitry and components. There are no recommended preventive maintenance steps; however, both visual and operational checks should be performed at periodic intervals to ensure proper
operation.
5.2 OFF-LINE TEST PROCEDURE
The off-line test procedure is intended to demonstrate that the FTB circuitry, front panel controls, and
indicators are functioning properly.
NOTE
In performing the series of tests that follow, UNLESS OTHERWISE STATED, the DRIVE TYPE
switch on the tester must be left in the RK07 position. Toward the end of the series of tests, a few special tests will be performed to ascertain the proper
functioning of the sections of the tester that are
unique to the testing of an RK06 drive.
The following steps and procedures are designed to thoroughly checkout the FTB for any maifunctions.
1. Open suitcase cover and remove the tester from carrying case.
2.

Remove all modules from the card cage.

Place the tester on a convenient working surface.

Attach the power supply cable and attach the LOAD BOARD.

5. Connect the ac power cord to a wall receptacle.
6. Check for the following voltages.
+5V

+15V

-5V

-15V

AIA2
A2A2
A3A2
A4A2

DID2
D3D2
A4D2
C4D2

DIRI
B3F2
D3F2
A4R2

DIB2
C4B2

5-1

Remove the ac power cord from the wall receptacle.

Remove the LOAD BOARD and attach the power supply extension cabie from the power
supply to the backplane connector.

Replace modules in the slots as indicated (Figure 5-1), with the control module (G5256) on a
quad extender and the transceiver module (G5166) on a dual extender.
A

SHIFT REGISTER MODULE (G5255)

CONTROL MODULE (G5256)
TRANSCEIVER (G5166)

IDATA SEPARATOR(G5161) 3

TRACKPOSITION 'BOARD (M7708)

-14
MA-l075

Figure 5-1

Field Test Box Module Utilization

10. Check the resistance of voltage pins to ground and to each other.
Voltage Pin
+5 V
+15 V
-5V
-15 V

Resistance Level

}

Between on and 10 Kn

11. Connect the power extension cable to the backplane connector.
12.

Replace the ac power cord in the wall receptacle.

13. Check the clock frequency on the data separ~tor board (05161) by attaching an oscilloscope
probe to D312 and observing that eight clock periods equal 116.25 ns X 8 = 930 ns. If this is
not the case, 'adjust potentiometer R 15 on this board.
14.

Put the switches on the front panei to the positions indicated.
EXERCISE/STATUS to EXERCISE
DRIVE SELECT to proper position
COMMAND TO RK06/7 switches:
DESELECT to the left position (negated)
SEEK to the left position (negated)
RECALIBRATE to the left position (negated)
RTC to the left position (negated)
CLEAR ERROR & ATTENTION to the left position (negated)
20/22 SECTORS to the right position (22 SECTORS)
SET MEDIUM OFF LINE to the left position (negated)
SET VOLUME VALID to the left position (negated)

5-2

LOOP CONTROL switches:
SINGLE CYCLE/CONTINUOUS to CONTINUOUS
FUNCTION to SEEK ONLY
SYNC to INT
CLOCK to FAST
HALT ON ERROR to NO
ADDRESSING switches:
CYLINDER to SWR
HEAD to SWR
SECTOR to ZERO ONLY
SWITCH REGISTER - all switches down (negated)
15. Push the START button and then the STOP button. All 32 of the LEDs in MESSAGE
words A and B should be 0 FF.
16. Take a chip clip and, on the shift register module (G5255), jumper E40-13 to E40-7
(ground). This makes the tester receive all Is in MESSAGE words A and B. In the A message word, the READY bit is always asserted to allow the tester to increment the cylinder
address counter.
NOTE
For the remainder of this test procedure (off-line
testing), whenever the tester is to be started, first
push the STOP button and then push the START
button.
17. Start the tester and then stop it. All the A and B MESSAGE LEDs should be ON. Ifnot,
check the LEDs that are off and see that they have approximately 3 V on the anodes. The
cathodes should all be common and at ground potential. If these conditions are met and any
LEDs are not on, replace them. If the anode of an LED is at ground, then look for a fault on
the shift register module (G5255). DRIVE FAULT and DATA OR PARITY ERROR
should be on, dimly, when the tester is started.
18. Disconnect the jumper to E40-13 but leave E40-11 connected to E40-7.
19. Start the tester.
20.

Enable HEAD SWR 2° and 21 and ensure that the LED above each switch comes on when
the switch is enabled.

21.

Enable CYLINDER ADDRESS SWITCHES 2° to 29 sequentially and ensure that all corresponding LEDs come on. As the ADDRESS switches are enabled, the T4-T13 LEDs in
MESSAGE B should come on dimly, with the following relationship:
CYL SWR:
20
MSG BLED: T4

21
T5

22
T6

23
T7

24
T8

25
T9

26 27 28 29
TI0 TIl T12 T13

22. Transmit MESSAGE A to drive.
a.

Put probe No.1 on E17-2 on the shift register module (G5255), and put probe No.2 on
E25-9 (CTD-H) of the same module. Sync on the leading edge.

Ensure that the MESSAGE A switches are all down (negated).

5-3

Enable the MESSAGE A switches, one at a time, and check the parity for each one
before disabling it.

When checking bit 0, STROBE XMIT should be asserted. Check this at EI-17 on the
control module (05256).

As successive bits are asserted, the STROBE XMIT H pulse should appear in successive positions on the oscilloscope, whereas CTD H should be high for a total length of
17 bits (Figure 5-2).

Put CLOCK switch in SLOW position. CTD-H (at E25-9) should be approximately 7.8
= 500 /lS. After checking time, put CLOCK back to FAST.

/lS X 64

Table 5-1 indicates the meaning of the bits TO through TIS.

CTD-H
(E25-9. G5255)

I-

7.S ,uSEC

-I

(17 BITS)

STROBE XMIT-H
(E1-17. G5256)

(1 BIT)

MESSAGE A-H
(E17-2. G5255)

ITO

(16 BITS)

T151
MA-1072

Figure 5-2

23.

Timing Diagram, Transmission of
MESSAGE A to Drive

Transmit MESSAGE B to drive. Bits TO through TIS are checked in a manner similar to
that in Step 22.
a.

Place these switches as indicated.
COMMAND TO RK06j7 switches:
DESELECT jRELEASE to the left (negated)
SEEK to the left (negated)
RECALIBRA TE to the left (negated)
ST AR T SPINDLE to the left (negated)
RTC to the left (negated)
CLEAR ERROR & ATTENTION to the left (negated)
20/22 SECTORS to the right (22 SECTORS)
SET MEDIUM OFF LINE to the left (negated)
SET VOLUME VALID to the left (negated)
SWR switches - all down (negated)

Move probe No. I and chip clip at E17-2 to E33-2, but leave sync probe No.2 at E25-9
(CTD-H).

l:.

CU:SUH:i llHlL IVIC';'';'i"\.VJ:, D

.........

~~~.,....T"""'I

....

·,1

.1.~_.

____ A_.l'\

~W1L~l1~~ dl~ dll UVVVU \IH'oaL.IO.iU).

5-4

Table 5-1

Definition of MESSAGE A Bits TO to T15

Bit

Meaning

TO
T1
T2

DRV SELECT 1H when BCD switch asserted
DRV SELECT 2H when BCD switch asserted
DRV SELECT 4H when BCD switch asserted

Bits TO through T2 are asserted in this order:

T3
T4
T5
T6
T7
T8
T9
T10
TIl
T12
T13
T14
T15

BCD Switch
DRVSELCODE

Bit
TO

Bit
Tl

Bit
T2

0
1
2
3
4
5
6
7

0
1
0
1
0
1
0
1

0
0
1
1
0
0
1
1

0
0
0
0
1
1
1
1

DESEL RELEASE H when switch asserted
SEEK H when switch asserted
RECALIBRATE H when switch asserted
START SPINDLE H when switch asserted
RTC H when switch asserted
CLR ERR AND ATTENTION H when switch asserted
FORMAT 20 SECTOR when switch asserted
SET MEDIUM OFF LINE H when switch asserted
SET VOLUME VALID H when switch asserted
20 HEAD H when asserted (HEAD switch up)
21 HEAD H when asserted
LOGIC oALWAYS
PARITY SWITCH in ODD position:
T15 is H if TO - T14 contain an even number of Is
T15 is L if TO - T14 contain an odd number of Is
PARITY SWITCH in EVEN position:
T15 is H if TO - T14 contain an odd number of Is
T15 is L if TO - T14 contain an even number of Is

5-5

Enable the MESSAGE B switches, one at a time, and check the parity for each one
before disabling it.

\Vhen checking bit 0, STROBE Xl\,1IT should be asserted. Check this at E 1-17 on the
control module (G5256).

As successive bits are asserted, the STROBE XMIT H pulse should appear in successive positions on the oscilloscope, whereas CTD H should be high for a total length of
17 bits (Figure 5-3).

Enable STATUS switch in the upper left-hand corner of the front panel. In the
ST ATUS mode, the tester will cycle once and come to a halt, so the intensity of the
oscilloscope screen will have to be turned up to see if bits TO and T1 are asserted.

The MESSAGE SELECT switch is located on the lower left section of the front panel.
Table 5-2 shows the coding of this switch. Check to see that bits TO and T1 are correct.

Put the EXERCISE/STATUS switch back to the EXERCISE mode and turn down the
intensity of the oscilloscope, because the tester will now cycle continuously.

The next set of steps checks the operaton of the tester with MESSAGE A IN asserted and B
IN negated.

CTD-H
(E25-9, G5255)
STROBE XMIT-H
(E1-17, G5256)
MESSAGE 8-H
(E33-2. G5255)

7.8 ,uSEe

;

(17 BITS)

(1 BIT)

ITO

(16 BITS)

T151
MA-l073

Figure 5-3

Timing Diagram, Transmission of
MESSAGE B to Drive

24. Adjust the switches as follows:
SINGLE CYCLE/CONTINUOUS to SINGLE CYCLE
CYLINDER to SWR
SWR switches all DOWN
HALT ON ERROR to NO
CLOCK to FAST
SYNC to INT
HEAD to ALL
DELA Y potentiometer should be adjusted for ease of viewing LEDs in the following tests

5-6

25. Loop Control Test: Single Cycle Mode - In this mode, when START is pushed, the tester
formulates a message and transmits it to the drive repetitively until the drive responds with
DRIVE READY. The tester then increments itself and halts.
NOTE
No individual test will be performed specifically on
this feature. However, it will be used in the following
addressing tests, and any misoperation of this feature
will cause failure of the test. Do not push STOP after START, because this will initialize the tester and
all counter information will be cleared.

Table 5-2

Definition of MESSAGE B Bits TO to TI5

Bit

Meaning

TO
TI
T2
T3
T4
T5
T6
T7
T8
T9
TIO
TIl
TI2

STWRDO
oPosition (00)
STWRD 1
1 Position (Ol)
Logic 0 always
2 Position (10)
Logic 0 always
3 Position (11)
H when 1 in the SWR is asserted
H when 2 in the SWR is asserted
H when 4 in the SWR is asserted
H when 8 in the SWR is asserted
H when 16 in the SWR is asserted
H when 32 in the SWR is asserted
H when 64 in the SWR is asserted
H when 128 in the SWR is asserted
H when 256 in the SWR is asserted
H when 512 in the SWR is asserted
Logic 0 always
PARITY SWITCH in OnD position:

113
TI4
TI5

MESSAGE SELECT Switch

TI5 is H if TO - T 14 contain an even number of Is
TI5 is L if TO - TI4 contain an odd number of Is
PARITY SWITCH in EVEN position:
TI5 is H if TO - TI4 contain an odd number of Is
TI5 is L if TO - TI4 contain an even number of Is

26.

Head Switch Test - The head counter is a 2-bit modulo three counter that is enabled with the
switch in the ALL position. It increments every cycle time and sequentially selects heads in
this manner: 0, 1, 2, 0, 1,2, 0, 1, ...
Table 5-3 is a chart of the head counter operation. Push START and check that the counter
increments once every time START is pushed. The SINGLE CYCLE/CONTINUOUS
switch should be on SINGLE CYCLE.

5-7

Table 5-3

Head Counter Operation (Modulo 3)

Selected Head

o
1
o
o

1
2

After checking, put SINGLE CYCLE/CONTINUOUS back to CONTINUOUS mode.
Put the HEAD switch back to SWR position and the HEAD SWR switches in the down
position.
27. Oscillation Test - Put CYLINDER switch into the OSC mode. A IO-bit iatch is ioaded by
the CYLINDER SWR switches and 0 alternately. Put the 29 switch (512) in the up position.
Start tester and see if LEDs alternate between the two modes.
28.

Sequential Test - Put CYLINDER switch in SEQUENTIAL mode. A 10-bit latch is loaded
by the contents of a IO-bit binary counter located on the G5255 shift register module. When
the tester is started, this IO-bit counter should reset to 0 and start incrementing until the
count of 814 is reached, then it will reset to 0 and start counting over again (Table 5-4). To
check the counter at 814, wait until 512 (2 9 ), 256 (2 8 ), and 32 (2 5) are asserted. Then put
SINGLE CYCLE/CONTINUOUS to SINGLE CYCLE, and push START until the count
of 814 is reached and resets to O.

Table 5-4

512
29

256
28

Reset of Sequential Address Count (RK07)

128
27
I

64
26

32
25

16
24

8
23

4
22

2
21

1
20

Count of
814

Next
Count

Put the HEAD switch to the ALL position and manuaily push START and see that when 2i
in the HEAD counter is reached, the next count increments the 10-bit binary counter and
the head counter goes to O.
29.

Alternate Mode Test - Put CYLINDER switch to ALT mode. Table 5-5 shows how the
cylinder address and head counters sequence with the SINGLE CYCLE/CONTINUOUS
s~itch in SINGLE CYCLE mode. Ass~ert the 29 bit of the cylinder SWR.
In this mode, the cylinder address switch alternates between SEQUENTIAL and SWR
mode. The 10-bit counter in the SEQUENTIAL mode is incremented once by the HEAD
counter after 21 is reached, which, in turn, toggles flip-flop E15-5 to the SWR mode. The
head. counter resets
to 0, counts to 2 1, and toggles E15 to the SEQUENTIAL mode but does
.. ..
not mcremem: tne omary counter.

5-8

Table 5-5

Cylinder Address and Head Count Sequencing

Cylinder
Address Mode

10-Bit Binary Counter
29 28 27 26 25

2°

SWR
SWR
SWR
SEQUENTIAL
SEQUENTIAL
SEQUENTIAL
SWR
SWR
SWR
SEQUENTIAL
SEQUENTIAL
SEQUENTIAL
SWR
SWR
SWR
SEQUENTIAL
SEQUENTIAL
SEQUENTIAL
SWR

1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0

0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

Head Count
21
22
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0

0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0

Put SINGLE CYCLE/CONTINUOUS back to CONTINUOUS and start the tester.
30. FTB in RK06 Mode - Two of the tests described previously, with the tester in the RK07
mode, must be repeated with the tester in the RK06 mode.
a.

Oscillation Test - With DRIVE TYPE set to RK06, put the CYLINDER addressing
switch to OSC. Put the 29 and 28 cylinder SWR switches up. Start the tester. Only the 28
LED should light because the tester is in the RK06 mode.

Sequential Test - With DRIVE TYPE set to RK06, put the CYLINDER addressing
switch to SEQUENTIAL. The IO-bit latch is loaded by the contents of the IO-bit
binary counter. When the tester is started, the IO-bit counter should reset to 0 and start
incrementing until the count of 410 is reached. It will reset to 0 and start counting over
again. To check the counter at 410, wait until 256 (2 8) and 128 (27) are asserted. Then,
put SINGLE CYCLE/CONTINUOUS to SINGLE CYCLE and push the START
button until the count of 410 is reached and resets to 0, as shown in Table 5-6.

Table 5-6 Reset of Sequential Address Count (RK06)
512
29

256
28

128
27

64
26

32
25

16
24

8
23

4
22

2
21

1
2°

Count of
410

Next
Count

After the completion of both of these tests, return the DRIVE TYPE switch to RK07.

5-9

31.

DELAY KNOB Test - This variable control delays the READY signal asserted from the
drive for approximately 220!J.s to 0.7 seconds. Move probe No.2, which is at E33-2, to E339 (DISPLAY-L). The time between DISPLAY-L pulses, when DISPLAY-L is negated,
should vary as the DELAY knob is rotated. DISPLAY-L is the sum ofCTD-H and RCV=H
signals. Vary the knob over the entire range. It should be a smooth tiansition (Figure 5-4).

32. HALT ON ERROR Switch Test - Place switch in YES position. Note that the LED counter
halts immediately and the DATA/D to C PARITY ERROR LED comes on. It halts because all Is are going into MESSAGE A. Sixteen Is is EVEN PARITY, which is an error
condition because MESSAGE A and MESSAGE B are always sent with ODD PARITY.
33. Set the tester up for on-line testing.
a.

Take chip clips off the shift register module.

Disconnect the jumper from E40-11 to E47-7.

Hook up the 40 conductor flat cable (BC06R-2) to the transceiver board (G5166),
making sure that the red stripe is at Pin 1 of the connector on the board. The other end
of the cable goes to the I/O connector on the front panel. Make sure that Pin 1 agrees
with the connector.

Leave the control module on the extender, for use in the on-line testing.

CTD-H
(E25-9. G5255)
RCV-H
(E6-8. G5255)

DISPLAY-L
(E33-9. G5255)

~~________~I~__________~r_

I-

TIME

-I

BETWEEN 220 J,LSEC AND 0.7 SEC
AS THE DELAY KNOB !S TURNED
MA-1074

Figure 5-4

Timing Diagram, Delay of DISPLAY-L

5.3 ON-LINE TEST PROCEDURE
The on-line test procedure is intended to demonstrate that the FTB is functioning properly. If it is
possible that the FTB is malfunctioning, the off-line test procedure described in Paragraph 5.2 should
be performed and successfully completed before attempting anyon-line checks.

NOTE
It is necessary that the drive used in the on-line testing is known to be functioning properly.
1. Connect one end of the drive I/O cable to 11 A in the drive connector, and connect the other
end to the tester I/O connector.
2.

Connect terminator to 12A on the drive connector block.
5-10

3. Check that the RUN/STOP switch on the front of the drive is in the OUT position
(negated).

4. Turn on the breaker on the rear of the drive and check that the drive spindle motor does not
turn on.

5. Insert a known good scratch pack (not an alignment pack) into the drive. Use only an
RK06K-DC cartridge in an RK06 drive, and only an RK07K-DC cartridge in an RK07
drive.
6.

Ensure that the M7706 module is in slot 3 of the drive card cage.

Push the drive's PORT A button in.

Place the DRIVE TYPE switch on the tester to RK07. Make sure that the RK07 LED
immediately to the left of the alignment meter is on and that the RK06 LED is off.

Place these switches in the indicated positions:
EXERCISE/STATUS to EXERCISE
DRIVE SELECT switch - to match the number on the drive's UNIT SELECT plug (on the
front of the drive)
COMMAND TO RK06/7 switches:
DESELECT IRELEASE to the left position (negated)
SEEK to the left position (negated)
RECALIBRATE to the left position (negated)
START SPINDLE to the left position (negated)
CLEAR ERROR & ATTENTION to the left position (negated)
RTC to the left position (negated)
20/22 SECTORS to the right position (22 SECTORS)
SET MEDIU~1 OFF LINE to the right position (asserted)
SET VOLUME VALID to the left position (negated)
LOOP CONTROL switches:
SINGLE CYCLE/CONTINUOUS to CONTINUOUS
FUNCTION to SEEK ONLY
SYNC to WR CLK
CLOCK to FAST
HALT ON ERROR to NO
ADDRESSING switches:
CYLINDER to SWR
SWR - all 10 switches down (negated)
HEAD to SWR
HEAD SWR - both switches down (negated)
SECTOR to ZERO ONLY
MESSAGE A PARITY to the ODD position
MESSAGE B PARITY to the ODD position

10.

Push STOP button on tester.

11. Push RUN/STOP switch (on the drive) in. The drive spindle should start up and, when it is
up to speed, the carriage assembly should load the heads and stop at cylinder O.
5-11

12. Start the tester. The tester switches are set to stop the drive. Note that the heads unload and
the spindle motor slows, then stops.
13. Stop the tester.
14. Place the COMMAND TO RK06/7 switches as indicated:
DESELECT to the left position (negated)
SEEK to the left position (negated)
RECALIBRA TE to the left position (negated)
START SPINDLE to the right position (asserted)
CLEAR ERROR & ATTENTION to the left position (negated)
RTC to the left position (negated)
20/22 SECTOR to the left position (20 SECTORS)
SET MEDIUM OFF LINE to the left position (negated)
VOLUME VALID to the right position (asserted)
15. Start the tester. The drive spindle motor should start and then the heads will load.
16. Stop the tester.
17. Place the DESELECT/RELEASE switch to the right (asserted) position, and the SINGLE
CYCLE/CONTINUOUS switch to SINGLE CYCLE.
18. Check that the SACK LED is on.
19. Start the tester.
20. Check that the SACK LED goes off and that the DA T A/D to C PARITY ERROR LED
goes on.
21. Stop the tester.
22.

Put the DESELECT/RELEASE switch to the left position.

23. Start the tester.
24. Check that the SACK LED goes on and that the PARITY OR DATA ERROR LED goes
off. The SACK assertion from the drive shows that it has received a message from the tester
and is selected.
25. Check that the POLLED ATTENTION LED is on.
26. Stop the tester. Place the tester switches as indicated in Step 9.
27. Start the tester. This will stop the drive.
28. Start the drive by repeating Steps 13, 14, and 15.
Before the drive can assert the POLLED ATTENTION line, two conditions have to be
satisfied in the drive. The STATUS CHANGE flip-flop has to be set and the number on the
three POLLED ADDRESS LINES from the tester's transceiver board has to agree with the
drive number. The number on these POLLED ADDRESS LINES is derived from the tester
UKIVt SELBel SWITCH.
5-12

29. Stop the tester.
30. Place the SINGLE CYCLE/CONTINUOUS switch to SINGLE CYCLE and the MESSAG E B PARITY switch to EVEN.
31.

Start the tester. The DRIVE FAULT LED should go on.

32. Put the CLEAR ERROR & ATTENTION switch to the right position and put the MESSAGE B PARITY switch to ODD.
33. Press START and check that the DRIVE FAULT LED goes off.
34. Place these switches as indicated:
CLEAR ERROR & ATTENTION to the left position
SEEK COMMAND to the right position
HALT ON ERROR to YES
MESSAGE A PARITY to EVEN
35. Start the tester. These LEDs should come on:
DRIVE FAULT
POLLED ATTENTION
SACK
36. Place MESSAGE A PARITY to ODD.
37. Push CONTROLLER POWER OFF. The DRIVE FAULT LED should be on and the
POLLED ATTENTION and SACK LEDs should be off.
38. Start the tester. The DRIVE FAULT, POLLED ATTENTION, and SACK LEDs should
be off.
39. Push the INITIALIZE button. Check that SACK and POLLED ATTENTION go off and
that DRIVE FAULT remains on.
40. Start the tester. Check that DRIVE FAULT goes off and that POLLED ATTENTION and
SACK go on.
41,

Push the MULTIPLE DRIVE SELECT pushbutton. The tester asserts the SECTOR AND
INDEX line, which normally can only be asserted by a drive. The drive being tested detects
sector and index pulses that are not its own and shuts down. Check that the heads retract to
the home position and that the MULTIPLE DRIVE SELECT LED goes on.

42. Check that the POLLED ATTENTION, SACK, and DRIVE FAULT LEDs are all on.
43. Place these switches as indicated:
HALT ON ERROR to NO
CYLINDER ADDRESS - SWR mode, 27 (128) asserted
CLEAR ERROR & ATTENTION to the right (asserted)
SINGLE CYCLE/CONTINUOUS to SINGLE CYCLE
SEEK to the right (asserted)
FUNCTION to SEEK ONLY
5-13

44.

Start the drive by repeating Steps 13, 14, and 15. After the drive is up to speed, the heads
should load (to cylinder 0) and then seek to cylinder 128.

45.

Check that the following are on:
SACK LED
POLLED ATTENTION LED
READY light (on front of drive)
MESSAGE A bit T7

46.

Place the switches as indicated:
LOOP CONTROL switches:
SINGLE CYCLE/CONTINUOUS to SINGLE CYCLE
FUNCTION to SEEK ONLY
HALT ON ERROR to NO
CLOCK to FAST
SYNC to WR CLK
DELA Y potentiometer should be adjusted for ease of viewing LEDs in the following tests
ADDRESSING switches:
CYLINDER to SWR
SWR - all switches down (negated)
HEAD to ALL

47.

Loop Control Test - In the SINGLE CYCLE mode, when START is pushed, the tester
formulates a message and transmits it to the drive repetitively until the drive responds with
DRIVE READY. The tester then increments itself and halts.
NOTE
No individual test will be performed specifically on
this feature. However, it will be used in the following
addressing tests, and any misoperation of this feature
will cause failure of the test. Do not push STOP after START, because this will initialize the tester and
all counter information will be cleared.

48.

Head Switch Test - The head counter is a 2-bit modulo three counter that is enabled with the
head switch in the ALL position. It increments every cycle time and sequentially selects
heads in this manner: 0, 1, 2, 0, 1, 2, 0, 1, ...
Table 5-7 is a chart of the head counter operation. Push the START button and check that
the counter increments once every time START is pushed. SINGLE
CYCLE/CONTINUOUS should be on SINGLE CYCLE.
Table 5-7

Head Counter Operation (l\'lodulo 3)
Selected Head

0
0

1
2

5-14

1
I

49.

Put HEAD switch to the SWR position and put all the HEAD SWR switches in the down
position.

50. Cylinder Address Test - Put the CYLINDER switch (under ADDRESSING) to the SWR
mode. The 10-bit cylinder latch and 2-bit head latch located on the shift register module
(G5255) are loaded with the contents of the cylinder and head address registers when the
tester is started. To test, enable the 2° bit in the CYLINDER ADDRESS SWR, push
START, and check that the 2° LED and only the 2° LED comes on.
Disable the 2° switch and enable the 21 switch. Push START and check that the 21 LED and
only the 21 LED comes on. Continue this process until all ten switches and their respective
LEDs have been tested. Every time the START switch is pushed, the drive should have
performed a seek to the address in the SWR.
51. Oscillation Test - Put the CYLINDER switch (under ADDRESSING) to the OSC position.
The 10-bit latch on G5255 is loaded with the contents of the SWR switches and zero, alternately. Put the 29 CYLINDER switch in the up position. Push START several times in
succession and check that the LEDs and the carriage assembly of the drive alternate between
512 (2 9 ) and o.
52. Sequential Test (Part 1) - Put the CYLINDER switch in the SEQUENTIAL mode. A 10-bit
latch is loaded by the contents of a 10-bit binary counter located on the shift register mod-:ule. When the tester is started, this 10-bit counter should reset to 0 and start incrementing
until the count of 814 is reached. Then, it will reset to 0 and start counting over again. To
check the counter at 814, wait until 5 i2 (2 9 ), 256 (2 8), and 32 (2 5) are 'asserted. Then, put
SINGLE CYCLE/CONTINUOUS to SINGLE CYCLE, and push the START button until the count of 814 is reached and resets to O. Table 5-8 shows the coding for a count of 814
and then a count of o.

Table 5-8

Reset of Sequential Address Count (RK07)

512

256
28

128
27

64
26

32
2s

16
24

8
23

4
22

2
21

1
2°

Count of
814

Next
Count

Sequential Test (Part 2) - Put the DRIVE TYPE switch to RK06 mode. Put SINGLE
CYCLE/CONTINUOUS to CONTINUOUS and the CYLINDER switch to the
SEQUENTIAL mode. The 10-bit latch on G5255 will be loaded with the contents of a 10-bit
binary counter located on the shift register module. Stop the tester, then press START.
When the tester is started, the 10-bit counter should reset to 0, start incrementing until the
count of 410 is reached, and then reset to 0 and start counting over again. To check the
counter at 410, wait until 256 (28) and 128 (27) are asserted, then put SINGLE
CYCLE/CONTINUOUS to SINGLE CYCLE. Push the START button, repetitively, until
the count of 410 is reached. The next time START is pushed, the count will go to 0 (Table
5-9).

5-15

Table 5-9

Count of
410

Next
Count

Reset of Sequential Address Count (RK06)

Put the HEAD switch to the ALL position. Push STOP and then, repetitively, push START
and check that when 21 in the HEAD counter is reached that the next count increments the
IO-bit binary counter and the head counter goes to 0 per Table 5-10.

Table 5-10

SWR Display and Head Count

SWR

HEAD Switch - ALL Position
Head Counter

2°

0
0
0
0
0
0
0
0
0
0

0
0

0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
1
1
1
1

0
0
0
1
1
1
0
0
0
1

0
0

0
1
0
0
1
0
0
I
0
0

53.

0
0
0
0
0
0
0

0
0
1
0
0
1
0

Put DRIVE TYPE switch back to RK07 mode and put the CYLINDER switch to the
HALT position.

54. Alternate Mode Test - In this mode, the cylinder address latch is loaded alternately from the
sequential counter and the SWR switches. The IO-bit sequential counter is incremented once
by the head counter after 21 is reached, which, in turn, toggles flip-flop E15-5 to the SWR
mode. The head counter resets to 0 and then counts to 21 and toggles E15 to the sequential
mode but does not increment the binary counter.
Table 5-11 shows how the CYLINDER ADDRESS and HEAD COUNTERS sequence
with the tester in SINGLE CYCLE operation. Push STOP, and then START, and check
that the tester CYLINDER and HEAD LEDs appear as in Table 5-11.

5-16

Table 5-11

Cylinder Address and Head Count Sequencing

10-Bit Binary Counter

Cylinder
Address Mode

SWR
SWR
SWR
SEQUENTIAL
SEQUENTIAL
SEQUENTIAL
SWR
SWR
SWR
SEQUENTIAL
SEQUENTIAL
SEQUENTIAL
SWR
SWR
SWR
SEQUENTIAL
SEQUENTIAL
SEQUENTIAL
SWR

1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0

0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0

0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0

0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1

Head Count

55. Stop the tester.
56. Place the switches in the indicated positions:
20/22 SECTORS to the right (22 SECTORS)
LOOP CONTROL switches:
SINGLE CYCLE/CONTINUOUS to CONTINUOUS
FUNCTION to WRITE
HALT ON ERROR to NO
ADDRESSING switches:
CYLINDER to SWR
512 (in SWR) up (asserted)
all other SWR switches down (negated)
HEAD to SWR
SECTOR to ZERO ONLY
57. Sync Switch Test - Put the SYNC switch to the WR CLK position. Take probe No.1 and go
to backplane pin C2Kl of tester (PPL DATA DRIVE-L) and check that there are clock
transitions. Put SYNC switch to the INT position and check that the clock transitions stop.
Put SYNC switch back to WR CLK position.
Start the tester and check that the drive seeks to cylinder 512. Take a chip clip, go to the
G5256 module, to EI5-3, with probe No.1, and use it to sync on the leading edge of INDEX-L. Take probe No.2, go to EI5-11, SECTOR-L, and count the number of SECTOR
pulses between INDEX pulses. There must be 22 sector pulses corresponding with the
COMMAND TO RK06/7 switch for 22 SECTOR format. Stop the tester and change to 20
SECTOR format. Start the tester and check that there are 20 sector pulses between index
pulses.
5-17

Figure 5-5 shows timing diagrams to correspond with the following procedure and explanation.
Take probe No, 2; go to E9-6 (WRITE GA TE-L) on the G5256 module and check that the
signal is low just for sector 0 time (the SECTOR switch is in the ZERO ONLY position). Put
the SECTO R switch to the ALL position and check that the WRITE G ATE-L signal is low
for each and every sector. Check that between sectors, WRITE GATE-L is high for approximately 1 J.ls. The reason is that WRITE GATE cannot be asserted as SECTOR-L trailing
edge time or the drive will get a drive error (READ /WRITE UNSAFE). Check with probe
No.2 that one shot E13-12 on the G5256 module is approximately 0.8 J.Ls wide and located
as shown in Figure 5-5. Take probe No.2. go to E28-12 (WRITE DATA-H) on module
G5256. Check that sector 0 and all other even sectors have a high frequency signal of 232
nsjcyc1e and all odd sectors have a low frequency of 434 ns/cyc1e. Put the SINGLE
CYCLE/CONTINUOUS switch to SINGLE CYCLE.

3.75 /lsec

INDEX-L
(El5-3, G5256)

---Ur----------------------.U
I_

25 MSEC

SECTOR-L
(E15-11. G5256)

ONE SHOT
(E13-12. G5256)

1.8/lSEC

.....

EiS-9 (G5256). i /lSEC. USED
FOR NEGATING WRITE GATE L _ _ _.....

0.8 /lSEC

1.0 /lSEC

WRITE GATE-L
(SECTOR 0 ONLY)
(E9-S. G525S)
\IIA-1080

Figure 5-5

Timing Diagram, WRITE GATE-L

5-18

58. Seek/Read Test - Place these switches as indicated.
LOOP CONTROL switches:
SINGLE CYCLE/CONTINUOUS to CONTINUOUS
FUNCTION to SEEK & READ
HALT ON ERROR to NO
20/22 SECTORS to the left (20 SECTORS)
SECTOR to ALL
Figure 5-6 gives a timing diagram to accompany the following discussion.
Start the tester and take probe No.2 to E28-8 (READ GATE-H) on the G5256 module.
READ GA TE-H should be asserted for each and every sector. Between sectors, check that
READ GA TE-H is low for approximately 50 IlS. This 50 IlS is a one-shot that is triggered by
the leading going edge of SECTOR-L. The reason for the delay in reading is that the phaselocked loop in the tester data separator module (G5156) must have time to lock to the
written data so that it will decode data correctly. Put the SECTOR switch to ZERO ONLY.
Check that READ GATE-H is asserted only for sector O.
Take probe No.2 and go to E21-1. This is READ DATA-L from the drive. Check that
sector 0 and all even sectors have the high frequency of 232 ns/cycle and sector 1 and all odd
sectors have the low frequency of 464 ns/cycle.
3.75~SEC

--I ~

INDEX-L
(E15-3, G5256)--""""IUr-~----------25-M-S-EC--------~.U
190 j.LSEC

-it---

READ GATE-H
(E2S-S, G5256)

SECTOR 0 ONLY _ _~nL..

___________________---.lnL...___
1.S j.LSEC

-l~
SECTOR-L (E15-11, G5256) --~Ur-----

READ GATE-H (E2S-S, G5256)

MA-l081

Figure 5-6

Timing Diagram, READ GATE-H

5-19

59.

Read Error Detection Test - Put HALT ON ERROR in the YES position. The tester must
continue reading data with no errors. Stop the tester. Put the SECTOR switch to ALL and
the 20/22 SECTORS from 20 sectors to 22 sectors. Start the tester and check to see that the
drive immediately comes to a halt with the DA.,T,A,,-/D to C PARITY ERROR LED coming
on. The reason is that the data was written in the 20 sector format, and it is being read in the
22 sector format, and the 20 sector mode sector pulse areas appear as read error areas in the
22 sector mode.

60.

Seek/Write and Read Error Detection Test - Place these switches as shown:
FUNCTION to SEEK & W /R
HALT ON ERROR to YES
CYLINDER to SEQUENTIAL
HEAD to ALL
Start the tester and let it sequence through all 814 cylinders several times and check that
there are no data errors. If there are consistent errors, check the tester data separator module (G5161).

61.

Read/Write Inhibit Test - Place these switches as shown:
LOOP CONTROL switches:
SINGLE CYCLE/CONTINUOUS to CONTINUOUS
FUNCTION to SEEK & W /R
HALT ON ERROR to YES
ADDRESSING switches:
CYLINDER to SWR
HEAD to ALL
Put 256, 128, 16, 8, and 2 cylinder switches in the asserted (up) position. Start the tester. Put
a finger on the head selector diodes on the read/write module in the drive. They are situated
just to the right of the read/write connectors on the read/write module. This action will
generate errors in the drive. If the tester continuously runs and does not halt on any errors
this means that, in the RK06 mode, read and write functions are inhibited and the artificially
generated errors are not being detected. This is the expected result. Put the DRIVE TYPE
switch back into the RK07 mode.

5.4 HEAD ALIGNMENT METER CHECK
The following steps are designed to functionally check the head alignment section of the tester box.
NOTE
This procedure is not intended to check the accuracy
of the head alignment section since the validation is
accomplished at the factory.
1.

Ensure that the DRIVE TYPE switch is in the RK07 position.

Push the RUN/STOP switch on the drive to stop the drive.

Wait until the drive stops, then remove the scratch pack.

Open the drive card cage, if it is not already open.

5-20

5. Place the safety switch (S2) on the M7906 servo analog module to the MAINT position
(toward the rear of the drive). This switch is the closer switch to the carriage assembly; it
enables WRITE PROT on the front panel of the drive and disables the servo brake.
6. Check that the WRITE PROT light is on, then press the button.
7. Install an RK07K-AC alignment pack into the RK07 drive.
8. Attach the tester alignment preamp to the Velcro strips on the base casting of the drive. Plug
the preamp into the RK07 read/write board alignment pins (Figure 4-4).
9. Place the tester switches as indicated.
EXERCISE/ST ATUS to EXERCISE
LOOP CONTROL switches:
SINGLE CYCLE/CONTINUOUS to SINGLE CYCLE
FUNCTION to SEEK ONLY
SYNC to INT (for all alignment reading)
ADDRESSING switches:
CYLINDER to SWR
HEAD to SWR
HEAD SWR switches - both down (i.e., head zero is selected)
Assert the dotted switches: 256, 128, 64, 32, and 16. This addresses cylinder 496 where the
servo information is written.
10. Press the RUN/STOP switch on the drive.
11. Start the tester. Check that the drive does one seek to cylinder 496 and that the LED above
the alignment meter is on but not flashing.
12. Select head 0 by negating 2° and 2' in HEAD SWR.
13. Start the tester. Observe that the ALIGNMENT VALID LED is on and that the meter is
steady and not pegged.
14. Repeat Steps 12 and 13 for heads 1 and 2. Select head 1 by asserting only 2° in HEAD SWR;
select head 2 by asserting only 2'.
15. Pick the head with the best alignment reading (i.e., the smallest meter reading) and set the
HEAD SWR switches for that head.
16. Offset Function Test - Set SEEK to the left position (negated), SINGLE
CYCLE/CONTINUOUS to SINGLE CYCLE, and all CYLINDER SWR switches in the
up position.
When 256 and 128 are up and SEEK is negated, the drive goes into the offset mode. The 26
bit (64) is the polarity of the offset.
NOTE
The alignment meter's microamp to microinch conversion is "5" for the RK07 mode (as indicated by
the RK07 alignment LED).

5-21

Table 5-12 shows some of the offsets and their corresponding codes. Put the CYLINDER
SWR switches in the positions indicated in the table, pushing START after each new line is
loaded. Check that the meter moves about the indicated amount in the indicated direction
from the nominal setting,

Table 5-12

Typical Offsets

2°

Meter Movement for RK07 Mode
(\

1
1
0

1
0
1

1
1
1
0

~..,

+ 12.5 ~in to the left
+25.0 ,uin to the left
+ 50.0 ~in to the left

0
1
1

4.-1()()
() "..,
IIln
.a. ....,"'._
......... to thp
........ _ lpft
... _ ......

0
0
0
0
0

/WJ.U

1
1
0
1

1
0
1
1

0
1
1
1

-12.5 ~in to the right
-25.0 ~in to the right
-50.0 ~in to the right
-100.0 ~in to the right

NOTE
The polarity of meter movements for the RK07 is
opposite that for the RK06.

17. Final Preparation of Drive and Tester - After the alignment test has been completed, shut
the drive down, from the tester. Remove the alignment pack from the drive, put S2 on the
M7906 servo analog module back to the normal position (RUN), and disengage the WRITE
PROT switch on the front of the drive. Stop the tester. Shut off ac power to the tester and
remove the I/O cable .fr~m the drive a~d tester. ~emo~e the card extend~r in sl~t ,No. 2 ~nd
put the control module \05256) back mto slot No.2 In the tester. Put the mOOUle retalr..ei
(74-67503) back into place on the card cage and secure it to the cage.

5-22

APPENDIX A
FTB-TO-DRIVE MESSAGES

A.I MESSAGE LINE A
This is a bidirectional signal line that transmits drive selection, commands, and head select data in
serial form in a 16-bit format from the tester. At the time of drive selection determination, all other
drives are inhibited from receiving the remainder of the transmission. Data from the selected drive to
FTB on MESSAGE LINE A transmits status information via the MESSAGE A and MESSAGE B
lines and displays them in the 16-bit message LEDs on the tester's front panel.

G)NOTE THIS BIT IS USED ONLY IN THE RK07.

Figure A-i

CP-2943

MESSAGE LINE A FTB-io-Drive

Clock
Period

Command

Description

TO - T2

Drive Select Code

A 3-bit drive select code transmitted with the least
significant bit first. All other drives are deselected.

Deselect/Release

This command sets the drive available status to the
other controller in a dual-access configuration. The
drive is also deselected when this bit is asserted.

Seek

This command directs the drive to seek to the cylinder address transmitted on MESSAGE LINE B.

Recalibrate

This command directs the drive to seek to cylinder
number 0 and to reset the cylinder address register.
This command is used to resynchronize the drive
position with its electronics if, for any reason, the
two get out of step.
A-l

Clock
Period

Command

Description

Start Spindle

This command directs the drive to start spindle
and, subsequently, to perform a brush cycle and
load heads if, and only if, the RUN/STOP switch
on the drive's front panel is depressed. It may also
be used to restart a drive in the event that a set
medium off-line command has unloaded heads or
any of the error conditions that unload heads have·
occurred. However; the error must be cleared before this command will allow the heads to reload.

Return to Centerline (R TC)

This command is used for resetting head offsets
whenever a write operation is to take place. Clearing the offset mode requires 3 ms to complete, at
which time a DRIVE ATTENTION signal is
transmitted to the FTB. An RTC is implied by any
non-zero cylinder seek or upon detection of a write
gate in the event that an RTC command is not detected.

Drive Clear

This bit, when asserted, clears the drive status
change flip-flop as well as clearing all error flags in
the selected drive (provided that the errors no
longer exist).

20-Sector Format Select

This bit, when asserted, commands 20-sectorpulses
per disk rotation; when not asserted, 22-sector pulses are commanded. Twenty sectors correspond to
I8-bit data words; 22 sectors correspond to 16-bit
data words. Whenever a change in the format is
made with this select bit, sector pulses cease, until
the next sector 0 at which time the drive is synchronized to the new format.

TIO

Set 1\1edium Off Line

This bit, when asserted, unloads the drive heads
and stops the spindle.

TIl

Set Volume Valid

This bit, when asserted, sets the volume valid flipflop, thereby acknowledging a power turn-on, a
change of cartridge, or the removal of the unit select plug. This must be set in order to perform a
write or seek function.

TI2 - T13

Head Select Code

A 2-bit head select code (in binary-encoded form)
is transmitted at these clock times with the LSB
first. The seek command bit must be asserted in
order to load the head addresses.

TI4

Third Head Select Bit

This head select bit is reserved; it is always a logical

1'15

Parity

The state of this bit will be such that the number of
logic 1s in the 16-bit transmission is odd.

A-2

A.2 MESSAGE LINE B
This bidirectional line transmits cylinder addresses, offset commands, and status message requests
from the FTB to drive. When a drive is selected, all other drives will be inhibited from receiving the
remainder of the transmission. Data transmitted from a selected drive to FTB on this line consists of
various drive status messages in any of four MESSAGE B LEDs as requested from the FTB.

CDNOTE: THIS BIT IS USED ONLY IN THE RK07.

Figure A-2

CP-2943

MESSAGE LINE B FTB-to-Drive

Clock
Period

Command

Description

TO - TI

Message Request

When CTD is asserted, the state of these two-bits
establishes which of the four sets of status messages
(MESSAG E A or MESSAGE B) are transmitted
from the selected drive to the FTB. TO represents
the least significant bit.

T2 - T3

Reserved

Reserved for additional message request bits.

T4 - T13

Cylinder Address/Offset
Command

These data bits (ali ten are used on the RK07, but
only nine, T4 - TI2, are used on the RK06) represent, when a seek command is asserted on MESSAGE LINE A, the desired cylinder address with
the least significant bit transmitted first in binary
form.
When the seek command and recalibrate bits are
low on MESSAGE LINE A and MESSAGE
LINE B is true at TIl and TI2 time, an offset command is generated with these bits. The codes for
the different offsets are presented in Table A-3.
NOTE
A seek, RTC command, or recalibrate will clear the offset
condition. Additionally, ready
will be reset until the offset
seek or the clearing of the offset condition is completed. Furthermore, a write gate received,
when offset is on, causes a drive
off-track error and fault.
A-3

Clock
Period

Command

Description

T14

Reserved

Not Used.

TI5

Parity

Parity bit for this I6-bit transmission.

Command

Direction*

Tt2 Ttt

TtO

I
1
1
1
1
1
1
1
1

1
1

I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

]

1
1
1
1
1

1
1
1
1
1
1

0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1

Magnitude
T9

1
1

1
1
1
1
1
1
1
1
1
1
1
1

1
1
1

1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1

1
1
1
1

0/1

1
1
1
1
1
1
1
1
1

0/1
0/1
0/1

1
1
1

0/1

0/1
0/1
0/1
0/1
0/1

1
1
1

1
1

011

I 1

0/1
0/1
0/1
0/1

1
0
0
0

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

1
1
1
1
0
0
0
0
1

1
1
1

1
0
0
0
0

1
1
1
1
0
0
0
0
0
0

1
1
1
0
0
0
0

1
1
1
1
0
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1

1
0
0

1
1
0
0
1
1
0
0

1
1

0
1
1
1

0
1
1

0
1
1
0

* 1 is the" +" or Forward direction
A-4

1
0
1
0
1
0
1
0
1
0
1
0

1
0
1
0

1
0

1
0
1
0
1
0
1
0
1
0

Pin
Offset Value
(microinches)
RK06

RK07

0
± 25
± 50
± 75
± 100
± 125
± 150
± 175
± 200
± 225
± 250
± 275
± 300
± 325
± 350
±375
± 400
±425
± 450
±475

0
± 12.5
± 25.0
± 37.5
± 50.0
± 62.5
± 75.0
± 87.5
± 100.0
± 122.5
± 125.5
± 137.5
± 150.0
± 162.5
± 175.0
± 187.5
±200.0
±212.5
±225.0
±237.5

± 500

±250.0

±525
± 550
±575
± 600
±625
± 650
±675
± 700
0 ±725
± 750
0 ±775
1 ± 800
0 ±825
1 ± 850

±262.5
±275.0
±287.5
±300.0
±312.5
±325.0
±337.5
±350.5
±362.5
±375.5
±387.5
±400.0
±412.5
±425.0

Command
TI2 TIl

1
1
1
1
1
1
1
1
1
1
1
1
1
1

Direction*
TIO

Magnitude
T9 T8 T7 T6 T5 T4

0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1

0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
0

1
1
1
1
1
0
0
0
0
0
0
0
0
1

* 1 is the "+" or Forward direction

A-5

1
0
0
0
0
1
1
1
1
0
0
0
0
1

0
1
1
0
0
1
1
0
0
1
1
0
0
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1

Pin
Offset Value
(microinches)
RK06

RK07

±875
± 900
±925
± 950
±975
± 1000
±1025
± 1050
± 1075
± 1100
± 1125
± 1150
± 1175
± 1200

±437.5
±450.5
±462.5
±475.0
±487.5
±500.0
±512.5
±525.0
±537.5
±550.5
±562.5
±575.0
±587.5
±600.0

APPENDIX B
DRIVE-TO-FTB STATUS MESSAGES

B.l INTRODUCTION
When the tester is in the exercise mode, the FTB requests and receives messages AO and BO only from
the drive. This allows the tester to monitor Drive Ready and Drive Fault for errors. If an error message
is detected and/or the user wants to view the contents of the other message lines (1,2, or 3), the status
mode can be selected. Upon actuation of the START pushbutton, the FTB requests and receives the
message line selected by the MESSAGE SELECT switch. The selected message line status/error bits
are then displayed in the MESSAGE A and MESSAGE B LEDs.

WORD 00
T15

T14

T13
PIP

T12

Tll

T10

PARITY STATUS

DR
SPEED WR
PARITY RD/WR OFF
UNSAFE TRACK LOSS LOCK

SEEK
INC

20
SPINDLE WR OFFSET SECT DRIVE
DR
ON
LOCK
ON
FORMAT TYPE READY

VOL
VAL

DR
AVAIL

AC
LOW

INV
ADDR

T0
I

SPARES

DRIVE SELECT CODE
I
I

C-D
PRTY
ERR

NXF

FAULT

SPARE

RES FOR
ADD'L MESS

MESS [0

(0) (0)

WORD 101
T15

T14

T13

T12

T11

T10

T 3

Tl
I

LOG
HDS

PARITY UNLDG
HDS

SEEK SERVO TRIBIT
SERVO LIM
PARITY UNSAFE DETON 8 NO SIG ERR ERR
SEEK MOTION

RTZ

REV

SPEED CART DOOR BRUSH HEADS SERVO SPARE
PRES LTCHD HOME HOME SIGNAL
OK

FWD

T0
I

DRIVE SELECT CODE
I

INDEX MULT HEAD
ERR HD SEL FAULT

WRITE WRCNT
GATE
8NO SECTOR
ERR
WRITE
GATE

RES FOR
ADD'L MESS

(1) (0)

T~AWs

MESS 10

WORD 110
T15
A2

T14

T13

T12

T11
I

I
I

PARITY RESVD

T8
I

T7
I

SPARE
I

T1
I

DRIVE SELECT CODE
I

CYLINDER ADDRESS
I

T2
I

CYLINDER DIFFERENCE/OFFSET VALUE

CD I

PARITY RESVD

T10

RES FOR
ADD'L MESS

(0) (1)

MESSID

WORD 11
T15

T14

T13
I

T12
I

T11
I

Tl0

PARITY

T8
I

T6
I

I
I

T3
I

DRIVE SERIAL NUMBER

PARITY RESVD RESVD RESVD

DECODED HEAD
ADDRESS
I

MESSAGES A and B Drive-to-FTB

B-1

I
I

RES FOR
ADD'L MESS

(DNOTE: THESE BITS ARE USED ONLY ON THE RK07 DRIVE.

Figure B-1

T0
I

DRIVE SELECT CODE

SECTOR COUNT

T1
I

MESS 10
(1) (1)
I
CP-2942

D.2

MESSAGE LINE AO

Clock
Period

Command

Description

TO - T2

Selected Drive Address

This binary-encoded address for the selected drive
is transmitted as an identification with the least significant bit LSB first. These bits are generated by
the contact of the unit select plug.

T3 - T4

No data is transmitted. Consequently, these bits
are logical O.

Drive Available

This bit, when asserted, indicates that the drive is
not conducting any operations with another controller. It is for use in dual-access configurations.
In single-access configurations, it is always asserted.

Volume Valid (VOL VAL)

This bit is reset by change of cartridge, removal of
power, or removal of the unit select plug. It is set
by a transmission from the FTB.

Drive Ready

This bit, when asserted, reports that the drive is
detented on a cylinder and can receive any command from the FTB.

Drive Type

This bit is designated for transmission of the disk
drive type. For the RK06, it is a logical 0 and for
the RK07, a logical 1.

Drive Format

This bit is designated for identification of the drive
as used for 16- or 18-bit-per-word read/write data
and correspondingly 22 or 20 sectors per rotation
respectively. When asserted, I8-bit words (20
sectors/rotation) are indicated.

TIO

Offset On

This bit indicates that an offset command has been
issued to the drive and that the offset has been enabled. The offset flip-flop is set at T 14 time of the
FTB/DRIVE transmission cycle.

TIl

Write Lock

This bit, when asserted, (Le., set by WRITE PROT
switch) reports that the drive is in write lock condition (write protected).

T12

Spindle On

This bit, when asserted, indicates that the selected
drive's spindle is energized.

T13

Positioning in Progress

This status bit when asserted is used to indicate
that a positioning seek is occurring.

B-2

Clock
Period

Command

Description

Tl4

Drive Status Change

This bit is the logical OR of any status change in
the selected drive. This status bit is identical to the
ATTENTION interface line.
The following are the conditions that cause drive
status change.
1. The completion of a seek or offset or offset
clearing operation

2. The unloading of heads
3. Change of write lock status
4. Any fault condition
It is cleared by the drive clear command, initialize,
power-up reset, and the run switch reset.

TI5

Parity

B.3

MESSAGE LINE BO

This bit is the odd parity for the drive to FTB
transmission.

Clock
Period

Command

Description

TO - TI

Message Identifier Bits

These two bits identify this transmission from the
drive to FTB and correspond to the message requested on the FTB to drive transmission.

T2 - T3

Reserved for additional message ID bits. Both bits
are logical O.

Reserved, it is a logical o.

Invalid Address

This bit, when asserted, indicates that the drive has
received an invalid head or cylinder address. This
bit also asserts fault, drive status change, and attention. When this error occurs, the assertion of
fault will prevent any head motion. As a result, the
heads are prevented from potentially traveling beyond the limits. This bit is reset by the drive clear,
initialize, power-up reset, or the run switch clear.

B-3

Clock
Period

Command

Description

AC Low Error

This bit, when asserted, reports that a low ac line
voltage has been sensed in the drive when the heads
are loaded. AC low error is the occurrence of an
rms voltage of less than 85 ± 4 V for the low voltage units or 170 ± 8 V for the high voltage unit. An
ac low condition will cause the heads to unload,
beginning with the first sector pulse following ac
low detection. This feature allows for the completion of a read or write operation in the current
sector. This error is reset by the drive clear, initialize, power-up reset, or the run switch reset provided that ac power has been restored.

Fault

This bit is the logical OR of all of the drive error
conditions. The occurrence of fault lights the
FA ULT indicator on the control panel. The following conditions cause the fault bit to be asserted.
1. More than one drive is selected.

2. Positioner, when detented, has moved too far
from its nominal position (e.g., due to the
drive being jarred).
3. Parity error is in a control transmission from
the FTB to drive.
4. A read/write unsafe condition is in the drive.
(Refer to T14 of this message for an explanation the read/write unsafe components.)

5. A write lock error condition exists, (i.e., the
receipt of a write gate when the drive is write
locked).
6. A low ac voltage is in the drive.
7. A seek incomplete condition exists.
8, A non-executable function exists from the
receipt of a write gate or seek command with
VOLUME VALID reset.
Fault is reset when all of the components are reset.

B-4

Clock
Period

Command

Description

Non-Executable Function
(NXF)

This bit, when asserted, indicates that a seek command or a write gate was received with VOLUME
VALID not set. It is reset by the drive clear, initialize, power-up reset, or the run switch reset.

Controller-to-Drive
Parity Error

This bit is asserted whenever a parity error occurs
in a transmission from the FTB to the drive on either MESSAGE LINE A or B. This error is then
reported at this clock time. It is reset by the drive
clear, initialize, power-up reset, or the run switch
reset.

TIO

Seek Incomplete Error

This bit is asserted and transmitted if a seek incomplete occurs. The seek incomplete error occurs
whenever the drive fails to successfully complete a
seek to a new cylinder. These conditions include
the following.
1. A servo unsafe error (see Message Bl, Tl4 for
...J~C:_~4-~~_ \
U~l1111l1Ull).

2. Seek and no motion (see Message BI, T12 for
definition).
3. Limit detection seek (see Message BI, Tl3 for
definition).
4. Invalid address (see Message BO, T5 for definition).
This error is reset by the drive clear, initialize,
power-up reset, or the run switch reset (provided
that, if a servo unsafe error occurs, the heads must
also be home).
TIl

Write Lock Error

This bit, when asserted, reports that the drive has
received a WRITE GATE signal when the drive
was write protected. It is reset by the drive clear,
initialize, power-up reset, or the run switch reset.

B-5

Clock
Period

Command

Description

T12

Speed Loss Error

This bit, when asserted, indicates that the spindle
speed is no longer satisfactory, that the heads are
or have unloaded, that no servo unsafe condition
exists, and that the spindle motor should be energized. It is cleared by a drive clear, initialize,
power-up reset, or the run switch clear (depressing
the run switch while heads are home). This bit
could be set from such probable causes as the
spindle belt falling off or breaking, spindle speed
sensor defect, or a problem in spindle motor circuits.
Assertion of this bit also asserts fault, drive status
change, and attention.

T13

R TZ (Return-to-Zero)

This bit, when asserted, indicates that a recalibrate
operation is underway. A recalibration takes place
upon command from the contrller or upon detection of inner limit while loading heads. When (as
mentioned above) the inner limit is reached, the
heads move in a reverse direction until the outer
limit is sensed. At this time. the carriage reverses
and moves forward and stops at cylinder O. When
the carriage settles on cylinder 0, this bit is cleared.

T14

Unloading Heads

This bit, when asserted, indicates that the heads are
unloadng and are not at the home position.

TI5

Parity

This bit is the odd parity bit for this 16-bit byte.

B.4

MESSAGE LINE Al

Clock
Period

Command

Description

TO - T2

Seiected Drive Address

The selected drive binary-encoded address is transmitted as an identification with the least significant
bit first.

Not used; it is a logical O.

Servo Signal Present

This bit, when asserted, indicates that the drive
heads are loaded and located between the outer
and inner limits and that servo signals from the
servo surface are being detected.

Heads Home

This bit, when asserted, indicates that the heads are
unloaded and at the home position. This bit is gent:lCilt:u by lhe horne switch.

B-6

Clock
Period

Command

Description

Brushes Home

This bit, when asserted, indicates that the disk
cleaning brushes are at their home position. This
bit is generated by the brushes-home switch.

Door Latched

This bit, when asserted, indicates that the cartridge
door is latched. This is generated by the lid locked
switch.

Cartridge Present

This bit, when asserted, indicates that a cartridge is
present and seated properly in the drive. This bit is
generated by the cartridge present switch.

Speed OK

This bit, when asserted, indicates that the disk
spindle rotational speed is safe for head loading.
This bit is set at a nominal 85 percent of 2400
rev/min

TIO

Forward

This bit, when asserted, indicates that the servo has
been enabled to move in a forward direction toward the spindle.

Tll

Reverse

This bit corresponds to the forward bit, but is for
reverse motion.

TI2

Heads Loading

This bit, when asserted, indicates that the heads are
in the process of loading. In the head loading routine, the heads advance forward until the inner
limit is detected. During this time, this bit is asserted. Upon detection of the inner limit, this bit is
reset and the RTZ bit, which is reported at T 13
time, is asserted.

TI3

Drive-Off-Track Error

This bit indicates that a disturbance has caused the
head to move an unsafe distance from its nominal
detect position while it is in detent mode and wrte
gate is asserted or the drive is not ready and receives write gate. For the case where the drive is
detented, this error will be sensed if the heads are
offset by a nominal 300 ~in for a period of at least
0.85 ms. This error is reset by the drive clear, initialize, power-up reset, or the run switch reset.

B-7

Clock
Period

Command

Description

T14

Read /W rite Unsafe

This bit is used for reporting a drive unsafe condition.
1. The drive has been selected along with another in the system.
2. Write current is sensed with no write gate.
3. Write gate is received but there are no write
data transitions.
4. A head fault is detected (i.e., a head circuit
imbalance is sensed).
5. More than one head has been selected.
6. An index error is detected (Le., an index has
not been sensed or sensed in the wrong location).
7. A tribit error has been sensed (Le., three successive tribits are missing).
8. Servo signal present error is sensed (I.e., the
loss of detection of servo signals from the
servo surface).
9. A write gate is coincident with a sector pulse
trailing edge.
When asserted, the drive unloads the heads but the
spindle will not stop. This error is reset by drive
clear, initialize, power-up reset; or the run switch
reset (provided that the heads are home and the
unsafe condition has been cleared).

T15

Parity

This bit is the odd parity bit for this drive-to-FTB
transmission.

B-8

B.5

MESSAGE LINE Bl

Clock
Period

Command

Description

TO - 1

Message Identifier Bits

These two bits identify this transmission from the
drive to FTB and correspond to the message requested on the FTB-to-drive transmission with the
LSD transmitted first.
Reserved for additional message ID bits.

T2 - T3
T4

Sector Error

This bit, when asserted, indicates that the drive has
received write gate coincident with the trailing edge
of a sector pulse. This error also causes the
read/write unsafe condition and fault. It is cleared
by drive clear, initialize, power-up reset, or run
switch reset.

Write Current and
No Write Gate

This bit, when asserted, indicates that head write
current has been detected without a write gate.
This error also causes the read/write unsafe condition and fault. It is reset by drive clear, initialize,
power-up reset, or run switch reset (provided that
the condition has cleared).

Write Gate and No Transitions

This bit reports that the drive has received a write
gate signal but has not received any write data.
This signal also causes the read/write unsafe condition and fault. It is reset by drive clear, initialize,
power-up reset, or run switch reset (provided that
the condition has cleared).

Head Fault

This signal, when asserted, indicates that a head
fault or head circuit has failed which would cause
erroneous data to be recorded on the disk. This error also causes the read/write unsafe condition and
fault. It is reset by drive clear, initialize, power-up
reset, or run switch reset (provided that the condition has cleared).

M ultiple-Head-Select

This bit, when asserted, reports that more than one
head is enabled which could cause data to be recorded on more than one surface. This error also
causes the read/write unsafe condition and fault. It
is reset by drive clear, initialize, power-up reset, or
run switch reset (provided the condition has
cleared).

B-9

Clock
Period

Command

Description

Index Error

This bit; when asserted; indicates the absence or
misplacement of an index pulse. This condition
also causes the read/write unsafe condition and
fault. It is reset by drive clear, initialize, power-up
reset, or run switch reset.

TID

Tribit Error

This bit, when asserted, indicates the detection of a
minimum of three successive tribits are missing.
This error also causes the read/write unsafe condition and fault. It is reset by drive clear, initialize,
power-up reset, or run switch reset.

TIl

Servo Signal Error

This bit, when asserted, indicates the detection of
the loss of servo signals from the servo surface.
This condition also causes the read/write unsafe
condition and fault. It is reset by drive clear, initialize, power-up reset, or run switch reset.

Tl2

Seek and No Motion Error

This bit, when asserted, indicates that a seek command was issued to the drive, but no track count
pulses were detected for 1D ms. This condition represents one of the seek incomplete conditions. It is
cleared in the same manner as all errors. '

T13

Limit Detection on Seek

This bit, when asserted, indicates that one of the
limits was detected during a seek operation. If a
limit is detected, the heads will unload, but the
spindle will remain on. It is one of the seek incomplete conditions and is cleared in the same
manner as an errors.

T14

Servo Unsafe

This bit, when asserted, indicates that the servo
amplifier has been saturated for an excessive length
of time, thereby indicating a servo runaway condition. This condition causes the heads to do an
emergency retract under battery power and stop
the spindle. It also causes the seek incomplete condition and is reset in the same manner as all errors
once the heads are at home position.

TI5

Parity Bit

This bit represents odd parity for this transmission.

B-IO

B.6 MESSAGE LINE A2
Clock
Period

Command

Description

TO- T2

Selected Drive Address

The binary-encoded address for the selected drive
is transmitted as an identification with the least significant bit first. The selected bit reflects the number of the unit select plug.

Reserved

This bit is reserved; it is logical O.

T4 - T13

Cylinder Difference/Offset
Position

These bits represent (all ten on the RK07, but only
nine, T4 - T12 on the RK06) represent the binaryencoded cylinder difference that exists during a
seek from a seek command and new cylinder address received from the FTB. When the positioner
is in detent on a cylinder, these bits represent the
offset position if in offset mode. It should be noted
that when these bits represent offset status, they are
inverted from the input offset bits. This difference
is invalid if the drive is seeking and a track-crossing
count occurs during the transmission of this count.

T14

Reserved

This bit is reserved. It is a logical O.

TI5

Parity

Parity bit for this I6-bit message.

B.7 MESSAGE LINE B2
Clock
Period

Command

Description

TO - TI

Message Identifier Bits

These two bits identify this transmission from the
drive to FTB and correspond to the message requested on the FTB-to-drive transmission with the
least significant bit first.

T2 - T3

Reserved for additional message ID bits; both are
10gicalO.

T4 - T13

Cylinder Address

These bits (all ten on the RK07, but only nine, T4TI2, on the RK06) report the current cylinder address in binary-encoded form with the least significant bit transmitted first.

TI4

Reserved

This bit is reserved. It is a logical O.

TI5

Parity Bit

This bit represents odd parity for this transmission.

B-ll

B.8

MESSAGE LINE A3

Clock
Period

Command

Description

TO - T2

Selected Drive Address

The binary-encoded address of the selected drive is
transmitted as an identification with the least significant bit first.

T3 - TI4

Drive Serial Number

These 12 bits are used to report the three LSD of
the drive's serial number. This identification is reported in BCD form with the LSD first and the
LSB of each digit first. It is used for error logging
purposes.

TI5

Parity

This bit represents the parity bit for this 16-bit message.

B.9

MESSAGE LINE B3

Clock
Period

Command

Description

TO - Tl

Message Identifier Bits

These two bits identify this transmission from the
drive to FTB and correspond to the message requested on the FTB-to-drive transmission.

T2 - T3
TI4 - T8

These bits are reserved for additional message ID
bits. Both are logical Os.
Encoded Sector Count

These bits are used for transmitting the present sector address to the FTB. The least significant bit is
transmitted first. The sector count is invalid if a
sector pulse occurs during these clock times.

Head 0 seiected.

TIO

Head I selected.

TIl

Head 2 selected,

T12-T13

Decoded Head Address

T14

TIS

These two bits are reserved; both are logical o.
Not used.

Parity Bit

This bit is used for transmission of odd parity for
this byte.

B-12

APPENDIX C
RK6/7 FTB FLOW DIAGRAMS
AND BUS MAPS

C-l

START)

CLR ROY FF
InA'"
.... un...,

TRANSMIT
RECEIVE
READ
YES (STATUS L)

DISPLAY AND
SAMPLE ERROR

YES

DELAY
(USER
SELECTED)

INCREMENT

(CONTINUOUS)
YES
(SINGLE CYCLE L)
WRITE
HALT

NOTES
1. HEAVY LINE INDICATE CONTINUOUS
MODE
2. NUMBERS IN PARENTHESES INDICATE
OPERATION CODES FOR MULTIPLEXER
E17 ON DRAWING D-CS-G5255-0-1
ISH 2 OF 5).

CP-3070

FigLiit: C-l

RK6/7 FiB Flow Diagram

C-2

15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

BUS A ~

0
,

, ,hln "11'\ if ,

,In ,

0
\

,
"

5 10 12 3 5 10 12
4 6 1113 4 6 11 13
r----E17
E23-

SHIFT REGISTER
BUSAOH 15

•,II'

8 10 12 1 9 11 13 2
9 111"3 2 10 12 1 r;
E21--1~
I-----E 18

PARITY GENERATOR
BUS AO H 15

, , , 'In ,1/\ -,II

11
I~ 1

12
,

'In

CONN #2

5 11 9 5 11
7 3 13 7 3 13
-E13
E20-

LED DISPLAY
BUSAOH 15

PANEL SWITCHES
BUS AO H 11

r-"--

15
I

1, '1

15 19 18 10 6 4 3 7
17 20 16 8 1 2 5 9

13'-

1,-

r-"5-

11
E32

13
E24

E19

ADDR.
TRK
TRK
ADDR. ADDR.
LATCH
CNTR. SWITCHES BUSA
BUSA BUSA
12.13
12, 13 12, 13

,
~
......

.....

.....
I

PAR.
CHECKER
BUSA
15

BKl

-----

UNUSED READY H
BUSA
BIT
7
DRIVER
BUSA
14
MA-1079

Figure C-2

Field Test Box, Bus A Map

C-3

15~

__________

~--

________

____________________________________

'2'3'r-++-,411--r+-t-,11---r+-t-,11-~_~_
I

9
8
7
6
5
4
3
2
1
0

I
I
I
11111

I
I

II I I III I

II Iii

II I
I

i
I

I II

1111111

1111

°jjjjljljlll :jjlJ5

I iI
!

11111111

III

11111

111,5 a

: !

II I I II I

III I ! I
! I
I I II I
II

i 1

. I

1/ I

1I11I1111

BUS B -+

I
I

I~E33

• •

E37----i1

I
I

,.,

SHIFT REGISTER
BUS BO ...... 15

,--a.

II--E28

E30---1a

I 1
I

~ ~

CONN #4

II
I I

PAR!TY GENERATOR
BUS BO ...... 15

LED DISPLAY
BUS BO ...... 15

I I

1111111

15
~

11111

In
~+il
' ,
Ii 3 4 5 6 101113
12 3 5 10 12 ,I
1,8 10 12 1 1 12 10 9 I 112 16 19 20 13 5 1 4 I
4 6 11 13
9 1113 2 13 11 8 u:
14 18 17 15 11 3 2 6
n

I ! 1111 ! III

I
II

I I

11111

99 I 19 7 5 3 11137 5 3 9
I rE32+-E34~~ I ~-E29-+E315

7 11 5
13 3 7
I

._.

III
111111

II
i i

13
h ' 'If

14 12 4 12 4 :1
. 5 1~ 5 1~ 13
r-E25+E22-h191

CYL. ADD SWITCHES
BUS B4 H 13

iii i

III
II
I

II I

ILJl
CYL. ADD. COUNTER
BUS B4 <-'> 13

I
I

3 41
}3
U
41111111 II I , 11111 I

I I I I ! Ii

III II I
I

ADDRESS LATCH
BUS B4-13

I
I

}4 aU

n
U U UD
~ M
M
I
11

Ell

E311

IE271

UNUSED
BIT
DRIVERS
BUS B
2,3,14

STATUS
WD.
BUS B

PAR
CHECKER
BUS B
15

DRIVE
FAULT
BUS B

,..

V, I

7
MA-1078

Figure C-3

Field Test Box, Bus B Map
C-4

RK6/7 FTB
OPERATING AND
SERVICE MANUAL
EK-RK67F -OP-OOI

Reader's Comments

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our
publications.

What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well
wr~~n,ctcJIs~easytouse? ~~~~~~~~~~~~~~~~~~~~~~~~~~~~

What faults or errors have you found in the manual? _~~~~~~~~~~~~~~~~~~_

Does this manual satisfy the need you think it was intended to satisfy? _~_~_~~_~~~_ _
Does it satisfy your needs? _ _ _ _ _ _ _ _ _ _ _ _~ Why? _________________

Please send me the current copy of the Technical Documentation Catalog, which contains information on
the remainder of DIGITAL's technical documentation.

Name ~___~~~_ _~~~~~__~_
Title _~__~~~_ _ _~_~~~_~_
Company~~~_~_______________
Department ____________________

Street _ _~~~~_~_ _~_ _ _~~___
City _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
State/Country _ _ _ _ _ _ _ _ _ _ _ _ _ __
Zip

Additional copies of this document are available from:
Digital Equipment Corporation
444 Whitney Street
Northboro, Ma 01532
Attention: Communications Services (NR2/M 15)
Customer Services Section
Order No. __
E_K_-R_K_6_7_F_-O_P_-_OO_I_ _ _ _ __

-- -

FoldHere -

Do Not Tear-Fold Here and Staple

FIRST CLASS
PERMIT NO. 33
MA YNARD, MASS.
BUSINESS REPLY MAIL
NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES
Postage will be paid by:

Digital Equipment Corporation
T"""hni".,,)
.... -_••••• -_. -nn"l11'n""nt'!»tinn
- - _••• _ .......- ....... _ •• -n""n'!»rtnH'nt
- y - ........... _ .......

Maynard, Massachusetts 01754