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XX-CD8E4-A8
August 2000
2 pages
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21264pb
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XX-CD8E4-A8
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2
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http://sup.xenya.si/sup/info/digital/Alpha/21264pb.pdf
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Alpha 21264 DIGITAL Semiconductor Alpha 21264 Microprocessor Product Brief The Alpha 21264 microprocessor, with benchmarks over 30 SPECint95 and 50 SPECfp95, and with spectacular bandwidths over 4 GB/s for L2 cache TM and over 2 GB/s for memory, enables the system designer to produce the highest performance systems ranging from PC clients to enterprise servers. Systems implemented with Alpha microprocessors have been the industry’s performance leaders since their introduction in 1992. Applications • Supports Windows NT—the world’s fastest growing operating system. – Microsoft has chosen Alpha as the first Windows NT 64-bit platform. – Microsoft releases Windows NT applications concurrently for Alpha and Intel systems. • Runs Windows 95 and non-native Windows NT applications using the DIGITAL FX!32 binary translator. • Supports DIGITAL UNIX—the first 64-bit UNIX operating system. • Supports OpenVMS, VxWorks, and Linux. • Optimizes visual computing (video and 3D graphics) using its powerful floating-point unit and the new Alpha motion-video instructions (MVI). – Real-time DVD authoring (MPEG2 and AC-3). • Simplifies development of a single or dual Alpha 21264-based system using the 21272 core logic chipset (21272). Benefits • System developers can deliver a 21264 solution that: – Will exceed end-user expectations in performance and Windows NT compatibility. – Provides investment protection by way of a migration path to higher speed 21264s and future generations of Alpha microprocessors. – Has multiple chip sources—DIGITAL Semiconductor, Samsung, and Mitsubishi. • The 21264 will provide end users with a quantum leap in performance that will: – Enable real-time visual computing. – Perform instant data mining. – Implement internet commerce. – Enhance medical imaging. – Solve the most complex, large data-set problems quickly. – Aid research centers in developing solutions to complex problems in disciplines such as medicine and polymers. Description The 21264 is the third-generation 64-bit Alpha microprocessor. It includes the latest Alpha architecture enhancements, such as motion-video instructions and byte/word operations. The 21264 completely controls its optional L2 cache and provides flexible bus timing to support a wide range of L2 cache memory devices such as those listed here: • Commodity 133-MHz register-to-register burst SRAMs (2+ GB/s) • 250-MHz late-write SRAMs (4+ GB/s) • 333-MHz dual-data clock-forwarded SRAMs (5+ GB/s) 18 August 1997 – Subject to Change Preliminary EC–R2YTC–TE Pipeline Operation Sequence For More Information The 21264 is a four-way out-of-order-issue microprocessor that performs dynamic scheduling, register renaming, and speculative execution. The 21264 pipeline contains four integer execution units. Two of the integer execution units can perform memory address calculations for load and store operations. The 21264 pipeline also contains two floatingpoint execution units to perform add, divide, square root, and multiply functions. The 21264 pipeline stages perform the following operations: Cycle 0—Instruction fetch using branch prediction Cycle 1—Instruction data is transferred to the register rename map hardware Cycle 2—Rename (map) instruction registers Cycle 3—Issue instructions from the queues Cycle 4—Read register file Cycle 5—Execute integer or floating-point instructions Cycle 6—Write integer results or access cache To learn more about the availability of the 21264, contact your local semiconductor distributor. To learn more about DIGITAL Semiconductor’s product portfolio, visit the DIGITAL Semiconductor World Wide Web Internet site: The bus interface unit, containing the memory and cache control units, maintains coherency between the Dcache and the optional L2 cache and main memory. 0 1 3 2 5 4 Integer Register Rename Map Integer Issue Queue (20) Integer Register File 6 ALU Shifter Multiplier System Bus (64 Bits) Address ALU ALU Address Four Instructions Instruction Cache (64KB) (2-Set) FloatingPoint Register Rename Map 64KB Data Cache FloatingPoint Issue Queue (15) FloatingPoint Register File Bus Interface Unit Floating-Point Add, Divide, and Square Root Floating-Point Multiply Cache Bus (128 Bits) Physical Address (44 Bits) FM-05575.AI4 Characteristics 2 Power supply Vss = 0.0 V, Vdd = 2.0 V ±5% Operating temperature Tj =100°C maximum Storage temperature range –55°C to +125°C Power dissipation @ 500 MHz 60 W (estimated) Package Transistor count Process Die size 588-pin pin grid array (PGA) 15.2 million 0.35 micron CMOS six-layer metal Approximately 3.1 cm2 Preliminary or you can contact the DIGITAL Semiconductor Information Line: United States and Canada 1–800–332–2717 Outside North America 1–510–490–4753 Electronic mail address semiconductor@digital.com For technical support, contact the DIGITAL Semiconductor Customer Technology Center: ALU Shifter Branch Predictor http://www.digital.com/semiconductor Phone (U.S. and international) 1–508–568–7474 Fax 1–508–568–6698 Electronic mail address ctc@hlo.mts.dec.com While DIGITAL believes the information in this publication is correct as of the date of publication, it is subject to change without notice. © Digital Equipment Corporation 1997. All rights reserved. Printed in U.S.A. DIGITAL, DIGITAL FX!32, DIGITAL Semiconductor, the DIGITAL logo, OpenVMS, and the AlphaGeneration design mark are trademarks of Digital Equipment Corporation. DIGITAL Semiconductor is a Digital Equipment Corporation business. Intel is a registered trademark of Intel Corporation. Linux is a registered trademark of Croce, William R. Della, Jr. Microsoft and Windows 95 are registered trademarks, and Windows NT is a trademark of Microsoft Corporation. Mitsubishi is a registered trademark of Mitsubishi Denki Kabushiki Kaisha. Samsung is a trademark of Samsung Electronics America, Inc. UNIX is a registered trademark in the United States and other countries, licensed exclusively through X/Open Company Ltd. All other trademarks and registered trademarks are the property of their respective owners. 18 August 1997 – Subject to Change
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