Digital PDFs

DIGITAL-8-35-5-8,

December 1965

20 pages

Original

4.2MB

Document:	maindec-826a-d
Order Number:	DIGITAL-8-35-5-8,
Revision:
Pages:	20
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/maindec-826a/maindec-826a-d.pdf

OCR Text

IDENTIFICATION
I .I

PDP—8 Maindec 826-A

I. 2

680 8-Bif Character Exerciser

I .3

November 8, I 965

PDP

8
LIBRARY

PDP—8 Maindec 826—A

Page I
2

ABSTRACT
The 680 8—Bit Character Exerciser program further verifies correct operation of the 680 DCS

system.

This test assumes that the Teletype lines are full duplex.

However, if the line outputs are jumpthe test does verify that the input characters are received as transmitted.

ered to the line inputs,

REQUIREMENTS

3.I

Storage

3.I .I

Exerciser Program

ADDRESS
Concurrent Output Test

l2008
I4008
I6008
20008

Data Table

Output

Concurrent

Input Test

Output Switch Register Routine

3.I .2

to
to
to
to

I3778
I5358
I6I68
20748
23778
25778

Output Buffer

2200

Input Buffer

2400

Interrupt Routine

000I

0004

33768
4I778
45778
47778
5I778
0I448

Character Assembly Subroutines (List of Items)
’

TTBBGN

(sum of Subroutines)

T8IN

(TTI Area)

T8IBF

(Input Buffer)

TBOBF

(Output Buffer)

30008
33778
42008
46008

T808F2

(Second Output Buffer)

50008

0I268
0I778

TTSPGO (Page 0 Constants)

3.2

TTCHAR

(Character Register)

;T8AXI

(Autoindex)

to
to
to

’

T8AX2

(Autoindex)

T8AX3

(Autoindex)

I5
I6

Subprograms and/or Subroutines
Digital—8—35—S-B, 680 8—Bit Character Assembly Subroutines

3.3

Equipment
Minimum Configuration PDP-8
680 DCS hardware

3.4

(including a IIO Baud Clock)

Miscellaneous
The IIO Baud Clock in CLOCK 2.

PDP-8 Ma indec 826-A

Page 2
4.

USAGE

4.1

4.1.1

If the Binary Loader beginningsat address 7777 is in memory,

the RIM Loader and/or the

4.1.2

Section 4.1 .2.

see

Otherwise

Binary Loader must be loaded into memory.

The 680 8-Bit Character Exerciser may now be loaded into memory as follows:
Set 77778 in the SWITCH REGISTER
Press the LOAD ADDRESS key

Place the Character
Press START

Exerciser

the keyboard reader

Engage the keyboard reader
4.3

Switch Settings (See Section 4.4)

4.4

Start up

4.4.1

Concurrent Output Test

and/or Entry

Set the SWITCH REGISTER to 1200
Press the LOAD ADDRESS key.

Set the SWITCH REGISTER equal to the lowest

line number to be tested.

Press START; the processor halts at address 1202.

”a

Set the SWITCH REGISTER eqUaI to the number of lines

to be tested.

1M2 ,1

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Press CONTINUE, the program outputs a fixed message on all the lines selected

4.4.2

Concurrent Input Test
Set the SWITCH REGISTER to 1600.

"153..

Press the LOAD ADDRESS key.

I
J

2:7,,

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Press START, the program scans 128 lines for input and retransmits
same

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I“

characters recered

,1:

(

Therefore, it is necessary to do the following before running the Concurrent Input

Set the SWITCH REGISTER to 1616.
Press the LOAD ADDRESS key.

Set the SWITCH REGISTER equal to the number of lines on the system.
Press the DEPOSIT key.

The Concurrent
4.4.3

the

Note that the 680 8-Bit Character Assembly subrOutines as currently coded will not process

Test:

Input Test may be run as above.

Output the contents of the SWITCH REGISTER.
Set the SWITCH REGISTER to 2000.
Press the LOAD ADDRESS key.

Set the SWITCH REGISTER to the line number to be tested.

”My“,

line as they are received.

128 lines at 110 Baud.

;

PDP—8 Maindec 826-A

Page 3
Press START; the processor halts at address_2002.

Set SWITCH REGISTER bits 4 through II
as

equal to the character to be transmitted, and SWO

follows:
SWO
SWO

—

Do not test for input.

down:
up:

Wait for input and verify that it is the same character as transmitted.

Press CONTINUE; the program transmits a carriage return, line feed, the contents of the

AC switches 64 times, and then repeats.
Note that since the input is two characters behind the output,

(due to the double buffering

of the Character Assembly Subroutines), SWO may not be changed from O to a I once the program is running. It may, however, be changed from a I to a O and switches 4 through II may be altered at any time.

4 5
.

Errors In Usage
Hardware malfunctions detected by the program result in a processor halt.

The following is

list of these error halts and their meanings:

4.5.I

Address 0002 Not Clock Interrupt

interrupt was received from a device other than Teletype Clock 2 or the IOT 643I
interrupt from Clock 2.

Either an

did not skip after an

4 5.2
.

Address I3I 2 Data Error
The processor halts with a line number displayed in the AC,

should have been received in the AC.
that is received in the AC.
4.5.3

Press CONTINUE again and the processor halts with the character

Address 2060 Data Error (Output AC Switches Routine)
Processor halts with the character transmitted in the AC.

indicating that a data error has

Press CONTINUE and the processor halts at address IBI 5 with the character that

occurred on that line.

line feed, or the code contained in the SWITCH REGISTER.

This could be a carriage return,

Press CONTINUE, and the processor halts

with the character that is displayed in the AC.

4.5.4

Detection of an Open

Input Line.

If the data error halt at address I3I2 is consistently executed with a specific line number
and the'character received is always 0, it indicates that the input line is in a constant ”SPACE" or open

line state.
4.5.5

Detection

Constant I'MARK“

The 680 Character Exerciser was written with the assumption that the Teletype lines being

duplex. Also, the program assumes that any input received during the Concurrent Output
Test is due to the fact that the line outputs are tied to line inputs. Therefore, if there is no input on a
tested are full

line or any of the lines, the program does not consider it an error. Assuming the test is operating with
inputs tied to outputs, the only way to be sure that a line is transmitting and receiving is to open the in-

put line in order to force a data error.
Note that thisprocedure is also likely to display any errors in translating line numbers; i.e.,
The line is then closed again and an error “is

input line I7 is opened and the processor does not halt.
indicated on line 37.

The malfunction is probably in the decoding of line I7.

PDP~8 Maindec 826-A

Page 4

Recovery from Such Errors

4.6

Pressing CONTINUE causes the program to proceed.

It is possible that an error halt will

leave some of the output lines in a ”SPACE" condition. If this happens, any Teletypes that are tied to
these outputs will run freely until the program continues. Also, in the process of opening lines to test for

transmitting and receiving, it is possible to get the input of a line out of sequence with the output.
this case, it is necessary, that the test be restarted.

Restrictions

The Character Assembly Subroutines scan the lines in even multiples of eight lines. Therefore, it is possible that an error could be indicated on a line or lines that have not been selected to be
.e., the Output SWITCH REGISTER Routine, if line I is selected to be run, the inputs of lines 2, 3,
run,
4, 5, 6, 7 and I08 should be placed in the "MARK“ state.
6.

‘

DESCRIPTION

é.l

Discussion

6.I .I

General
The 680 8—Bit Character Exerciser transmits and/or receives ASCII Teletype data at the line

speed of Teletype clock 2 and verifies correct operation of the 680 DCS hardware.

The program allows

parameters to exercise up to l28 lines and includes three modes of test: Concurrent Output, Concurrent

Input, and Output the Switch Register.
6.l .2

Test Descriptions

6.I .2.I

Concurrent Output Test

The Concurrent Output Test will accept parameters to transmit on from I to I28 lines.

The

program assumes that all of the lines selected are full duplex and that any input is due to an output line
iumpered to an input line. The following message is transmitted on all lines selected:

THE QUICK BROWN FOX JUMPED QVER THE LAZY DOG'S BACK
OI23456789

:"#$%' ()*+

./:,-<=>?@[\]

14-

If input is received on any of the lines selected, the program verifies that the characters
received are received in the same order that they are transmitted. Also, since the input is tested almost

independently of the output, it is possible to iumper input lines to output lines in any configuration that
s desired,
including and/or other than I for l
.

o.l .2.2

Concurrent Input Test

The Concurrent

Input Test initializes to scan all I28 lines for input.

received on a line, the program transmits the character received on the'same line.

o.I .2.3

When a character is

(See Section 4.4.2.)

Output the Switch Register Routine
This routine transmits the code contained in SWITCH REGISTER bits 4 through II

line specified by the contents of the SWITCH REGISTER when the routine is started.

the

The program trans-

mits a carriage return, line feed, the contents of the SWITCH REGISTER 64 times, and then repeats.

SWITCH REGlSTER bit 0 is a

verfies that the output and the input are equal.

Since the

input is two characters behind the output, (due

to the double buffering of output characters in the Character Assembly Subroutines) the compare mode
must

the program transmits a character, waits for it to be input, and then

be selected at the time the processor halts at address 2003.

PDP-8 Maindec 826-A

Page 5
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3221

3335

3233

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3141

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3173
3173
3175

TEKSB

3145
3337

3321
3322

3323
3339
3325
3149

3323

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3327

3336
3331
3332

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3341
3342
3141

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DIAGRAMS (Not Applicable)
12.

3339

Digital-8-35-S-B
680 8-Bi1‘ Character Assembly Subroutines

3343
3149
3147

3131
3132
3153
3134
3143
3142
3133

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4333

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3167
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3135
3344
4539
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4534

19334
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3431
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3135

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3172

4533

3133
3137