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MAINDEC-14-D7LA-D

December 2000

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Document:	maindec-14-d7la-d
Order Number:	MAINDEC-14-D7LA-D
Revision:
Pages:	26
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/maindec-14-d7l/maindec-14-d7la-d.pdf

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IDENTIFICATION

product Code:

MA~M)EC~14“D7LA-D- (D)

Product Name

TE ST

Date created;

Maintainor:

Diagnostic Group

Author

Edward P. steinberger

14L
r

1^7^

.. .

abstract

to be run on a PDP-8 I/L
TEST-141, is a program written

computer to thoroughly test a
TTclllT
loaded
It is
oxes.
os a PDP-14L processor, and I-, 0-®**‘
under
the PDP-14L
into and run on an 8 I/L connected to
error halts ana oscilloscope
The program provides error type outs,
a short penoa of time
looping. The program can be run for
or it may be run for a
(minutes) to initially test a P0P-14L,
provide a comprehensive
long time (approximately 2 hours) to
test to all the logic circuitry.
2

requirements
2.1

Equipment
PDP-8 I/L Computer
PDP-14L to PDP-8 I/L Interface Module (M745)
PDP-14L Computer
output of the O Boxes
PDP-14L, I-, 0"# a nd S- Boxes with the
input: s of the
tied back (electrically) to the respective
I- Boxes.

2.2

Storage
The program occupies most of PDP-8 l/L memory

2.3

Preliminary programs
None

LOADING PROCEDURE
3.1

Method
Binary
The program is loaded using the "standard” PDP-8
Loader technique.

- 2-

STARTING PROCEDURE
4.1

Control Switch Settings
switch register settings
The following is a program of
program:
and their operation upon the

Set £s

0
I

0
1

4.2

Action
Loop on Current Test
Don t Loop
Don’t Halt on Error
Halt on Error
Don't Print Errors
print Errors
Long Test
Short Test
Repeat All Tests
Stop at End of Tests
Test Memory logic
Don't Test Memory Logic
'

Starting Addresses
it is desired to
Start the program at location 0* .3 if
f i gu r at ion
con
interrogate operator about PDP-i
-<

if the PDP— 14L
Start the program at location 020 1
to the progrs®.
defined
configuration has been previous.-.

4.3

program and/or operator Action
3

connect the PDP-14L to be tested to the PBP-Sl/L
revision of the M74S
using the appropriate cables nd
interface module
i

0-, and S-Boxes to
4.3.2 Connect to the PDP-14L the I-,
must occupy
be used in the test. The I- Lax cables
of
consecutive address slots in the I -Box section
occupy
also
must
the PDP-14L. The 0-Box cables
section
consecutive address slots, but in the 0-Box
The S-Box c-bles must occupy consecutive
of the PBP-14L.
immediately following
address slots in the O-Box action
connect the output
the last O-Box cable. Elect ically
inputs of the Z-BOKit
of the 0- Boxes to the respect ive
there ar® extra
etc
2 to
(i.e. O to o, \ tc

-3-

In-Box inputs left over, connect these respectively to
outputs 0, 1, 2 etc. (i.e. input 40 to output 0, input
41 to output 1, etc) until all input terminals are
Return to output 0
connected. to a respective output.
Connect the
this.
accomplish
much
as
necessary
to
as
voltage
Volts,
60 Hz)
110
(normally
supply
appropriate
to the 0-Boxes.
.

If the memory logic is to be tested, plug the special test
module into the PDP-14L.
(see the Engineering Checkout Procedure)

4.3.3

4.3.4

Power up the PDP-8I/L and the PDP-14L computers.

Load the binary program
4.3.5
the PDP-8 Binary Loader.

TEST-14L” into the 8I/L using

Start the program at location 0200.
4.3.6
per 4 . 1 above

Set Switch register

Answer the questions asked by the program, concerning how
4.3.7
many X-,o-, and Half - S Boxes are connected to the PDP-14L
(1 S-Box * 2 Half S-Boxes) and the presence of a ROM via
the PDP-8I/L Teletype Keyboard (See below)
HOW MAM

.T-

BOXES?

MANY 0-i?GX£S?

HO**
-4

HOW MANY HALF

S - BO X£ S V

0
f

SOrt

INSTALLED (Y-Y£5 «~NO)

Program will now run to completion (assumiacr. no errors) and will
4.3.9
type out "PASS N* 'COMPLETE" upon completing each pass of the progxm
(See Below)
5

PASS 000

COMPLETE

PASS 0002 COMPLETE
PASS 0003 COMPLETE

OPERATING PROCEWTRS

5.1

Operational Switch Set rings
See 4 1 above
.

5.2

Subroutine Abstracts
None

Program and/or Operator Action

5*3

the operator and
Thera ia normally no communication between
except via
the computer after the initial interrogation communicate with
the Switch Register. The computer will not tne computer
the operator except when an error occurs or
completes a pass through the program.

LABORS
4.X

Error Halts and Description

preceded by error
Most of the error halts in the program are
of the error
cause
the
about
doubt,
However, if in
tyoeouts.
lifting.
halt, consult the program
4.2

Error Recovery

set the switch
TO scope an error condition after an error halt,

restart the program
After replacing suspected bad modules, always
interrogation
at location 0201 (it is not necessary to repeat
program
tne
or
if the PDP-14L configuration has not changed
has not been reloaded)
6.3

Error Messages

(with very few excdptlonft)
The error messages output by the program
error number) followed
tter
le
2
(a
or
it
design,
will contain as error
and/or description of
by a description of the test being perfo rraed operator can us© the
the
if desired
the failing error condition.
the module call list to
to
directly
go
to
designator
2 letter error
if he desires, he may
see which modules should be replaced. O r PDP-14L
to determine
set up a program 'scope loop and probe t ha
module.
failing
the failing condition, then replace the
of the various types of error messages are shown
,,

SgMplee

below:
6,3.1

6* 3. 1.1

JfAP

0L0
pc

TEST
©0OO 8$0

t4£'24J>

00&0

-5In the example shown of the previous page, the
error designator is "AX". The operator can go
to the module call table and looK up ‘‘AX" or he
can analyze the rest of the message. The test
being performed involves some of the basic gating
instruction. The
of the PDP-14L and the
the "output
possibly
(or
PCI
failing
3.1.2 register was
this point
at
register" as it is impossible to tell
in the testing scheme)

Multiple Register Errors

6.
*.*AL*#

TRtf

OLD

OUTPUT

(

42 2&1 TEST
.

6 OOP

0AD

0b4Z

PCI

6.3.2

It is possible that more than one register can be
affected in a test. In the example shown above
both the "Output Register'' and "PCI" were in error

Non Register Errors
6. 3. 2.1

I/O Instruction Errors

TEST FLOP

MOT SET B Y TXK @06©

The above example indicate a problem in the I/O section
of the PDP-14L. The operator can refer to the sscisle
call for error "8Z ” after reading this message, or he
can further analyze the message if he desires to 'scope
the error. In this test he would 'scope the "TXtf" class
of instruction to chech puls generation, addressing,
gating, decoding, etc. in the PDP—14L processor and in
the I-Box affected.
i

;

6. 3. 2.

PDF- 8 to PDP-14L Interface Errors

EXTERNAL FLA6 NOT CLEARED 8Y POWER CLEAR OR 6161 ALWAYS SKIPS
The above example .indicates - problem in the M>P*8
to PDP-X4L Interface module fM745) , .’Scope loops
provided, however it is generally easier to simply
replace th® M74! module and rr y agarn
'

-6-

6.3.3

Non --Diagnostic Errors

PPP-14 HUNG
POP- 14 STOPPED

Un fo rtuna t ly , these are a few errors which the
PDP-14L can perform which are not analyzible by
These
the program, although they are detect ible
if the PDP-14L stops or hangs,
are shown above,
one of the above printouts will occur. Depressing
PDP-8 "continue’ may provide more information about
the error.
.

6.4

Error Identifier - Module Call
Note: In addition to the modules listed for each error
identifier, the following module?; are coMtson to all errors

M774 - IE Decoder
M235 - Major Registers
M745 - PDP-8 to PBP-14L Interface
Identifier

Module Type (s) and Function (i

M741 Major states and timing

See Mote

See Note

See A

M743 I/O interface
K207 O— Box
K 1 3 5 0— Box
K.161 0-Box

ee BH

M743 I/O interface
K161 I -BOX
K378 X-Box
•Cl 3 5 I— Box

-7-

Identifier

Modu le Type s ) and Function (f 1

See BJ

See BH

See BJ

See BH

See AX

See BH

See hi

See BH

See AI

See BJ

See AI

See BH

X6L4

See BS

See BH

See AI

See Mete

See AI

0-Box, See BJ

Identifier

Moudle Type (s) and F unction (S

See AI

•See

See AI

RESTRICTIONS
7.1

Starting Restriction.?

PDP-14L Power Clear Ls expected at program start time,
don't stop TEST-14L in the middle of the I/O test and
restart at 0200 or 0101 without powering down and
powering back up the PDP-14L
7.2

Operating Restrictions
All X- # G~» and S—Bo< cables must- occupy consecutive
address slots starting with address slot 0 in the
respective area of tie PDP-14L processor
the
Th© special test modal® must be plugged in to test
memory logic.

MISCELLANEOUS
8.1

Execution Tims
the t/O
The execution time oE the program is dependent upon
configuration of the POP- 14; under test.
The short test should take no more than five
The long test should take approx:. lately two

(5)
(2)

minutss.
hours*

_c _

PROGRAM DESCRIPTION
9.1

Test

{SA

operation of the
The first test performed checks the
on the PDP-S
external flag to set and clear and operate
interrupt bus properly.
9.2

Test

(SA=1200)

Test 9 (SA *3200)
!

(long test) jump
Checks JMP instruction (4224). If SR3-1
test) jump
from and to all locations. If SR3-0 (short
.from 0 to all locations.

9.4

Test 12 (SA&3 400)

Checks the instruction TRM (4226)
9.5

Test 15 (SA~3600)
locations
Check the instruction NOP (0000) at all

9.6

Test 18 (SA«3666)
jump properly.
Checks the instruction JFF (5000) to
and .rom all locations.
SR3-1 (long test) JFF is executed to
to all locations -.row
If SB3=0 (short test) JFF is executed
all page location 0’s.

9.7

Test 34 (SA*5606)
checks that
The first test to be performed on the 1/0
are on.
after an "SYF 377" (3377) no outputs

9.6

Test- 35

(SA*5644)

all output. *r« o«.
Checks that after an "SYF 377” (3377)
9.9

Test 36 (SA^5677)
an
Checks that no 'inputs are on after

>77

- 10 -

9.10 Test 37 (SA=5733)
"SYF 377"
Checks that all inputs are off after an

9.11 Test 39 (SA*6002)

flop
Checks a TXD "N" status worci with the "TEST"
set and input off
9.12 Test 40 (SA«60,04)

set
Checks a TYD "N" status word with the "TEST" flop
and output off
9.13 Test 41 (SA*6006)

Checks the JFM Y instruction with the "TEST"
flop set
9.14 Test 43 (SA=6054)

cleared
Checks the JFF Y instructions with the "TEST" flop
9.15 Test 44 (SA=6X12>

Check a TXD "N" states word with the "TEST" flop
cleared and input off-

9.16 Test 45 (SA~6115)
Checks a TYD "hi" eta -us word with the "TEST" flop
cleared and output off
9.17 Test 47 (SA*6122)

Checks the JFF Y instruction with the "TEST" flop set
9.18 Test 49 (SA*6200)

Checks the JFH Y instruction with the "TEST" flop
cleared
9.19 Test 54 (SA*6237)

Checks that with output "N" on, only TYN
the -TEST* flop.

K" sets

- 11 -

9.20 *Teat 55 (SA*6314)

Checks a TXD "N" status word with the "TEST" flop
set and input on.
9.21 Test 56 (SA-6317)

Checks a TYD "N" status word with the "TEST" flop
set and output on.
9.22 Test 57 (SA=6322)

Checks that with output "N" on, all TYF's set the
"TEST" flop ekcept TYF "N"
9.23 Test $8 (SAsm6400)

Checks a TYD '*M H status word with the
cleared and output on.
9.24 *T«9t 59

TEST " flop

<SA=*641f?)

status word with the "TEST" flop
Checks a TXD
cleared and input on

9.25 *Test 60 <SA*6413)

Checks that with output "N" on, only T3©? *»"
and "offsets" (other inputs connected to output
set the "TEST" flop.
"Iff")
9.26 •Test 61 (SA«64?6)

Checks that with output "N" on, only TXF
"offsets" do not set the "TEST" flop.

B" and

9.27 Test 66 (S»46j9)

Checks that only SYF

"ST"

and SYF 377 clears output

"ST

9.28 Test 68 (SA«7000)

Checks that only SYH

turns on output "B"

- 12 -

9.29 Test 69 (SA-5517)

by
Checks the operation of memory circuitry
The number in the OUTPUT
<pjyij
(4426) using 6165 IOT.
in PCI.
Register should be tie same number as was

These tests are not performed when an S-bojc is being
tested