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MAINDEC-08-D71A-D

December 1967

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MAINDEC-OB-D7IA-D

IDENTIFICATION
Product Code:

Maindec-O8-D7TA-D

Product Name:

680 DCS Expanded Static Test

Date Created:

May 15, I967

Maintainer:

Diagnostic Group

Author:

Kenney

PDP-B
LIBRARY

“wwwmmm

F.“

”a“... -w

0......“

,m..-.. a.

“0......

MAINDEC-08-D7lA-D

ABSTRACT

The 680 DCS Expanded Static Test consists of two independent test sequences intended to

verify correct operation of the IOT instructions and control logic associated with the

Test failures will result in a processor halt at a halt location associated with the

munications System.

failing test.

680 Data Com-

Each test halt is interpreted as to failing test sequence,

suggested failure source (where

possible), and program restart instructions.
2

REQUIREMENTS

2 .l

Storage
Starting Address

End Address

Line Clock Test

0200

0513

IOT and Control Test

0674

2706

lest

2.2

(Section 4)
(Section 5)

Equipment
Minimum configuration PDP-8
Minimum configuration 680 DCS

(i .e.

68l Data Line Interface and 685 Multiplexer

Control)
3

PROGRAM LOADING
a.

If the Binary Loader is resident in memory proceed to step b.

Otherwise load the

Binary Loader into memory.
b.

Set the AC switch register to 7777 and depress the LOAD ADDRESS key.

Then

depress the START key.
c.

Place the 680 DCS Expanded Static Test in the keyboard reader and turn the reader

on.

When the binary program tape has been completely read into memory, the AC should

contain zero indicating correct program tape checksum.

LINE CLOCK TEST

4.1

General Description
The line clock test verifies correct execution of the three IOT instructions associated with a

specified clock number, and correct operation of the logic associated with each clock.
The three IOT Instructions are listed below:

LOl

Octal Value

TTXSKP

64Yl

Skip if specified clock flag is set

TTXON

64Y4

Reset and enable specified clock flag

TTXOFF

64Y2

Reset and disable specified clock flag

NOTE:

X =1,

2, 3, or 4 and Y

Operation

2, 3, 4, or 5, respectively
I

MAINDEC-OB-D71A-D

With SR 2 set, the time intervals in microseconds of eight successive clock interrupts will

be typed on the Model 33 Teleprinter.

The Following chart lists the correct interrupt time intervals for various clock speeds:
Bit Time

Interrupt Time Interval (psec)

110

9.09 ms

1136

13.3

1665

20.0

2500

22 .2

2780

Crystal Frequency

Line Baud Rate

14.08 l<c

l<c
6.4 kc
5 .76 kc
9.6

NOTE:

The interrupt time intervals will be reported within a tolerance of 1 percent.

The following example is the interrupt time interval report for clock no. 1

(110 baud):

CLOCK1
1124

1132

4.2

1132

1124

1132

Operating Procedure
0.

Set SR to 0200 and depress LOAD ADDRESS

Select number of clock to be tested (SR 9, 10, and 11):
SR 11 set; SR 9 and 10 reset
Clock No. 1
2
SR 10 set; SR 9 and 11 reset
Clock No.
SR 10 and 11 set; SR 9 reset
Clock No. 3
SR 9 set; SR 10 and 11 reset
Clock No. 4
-

Select desired program control according to the following Switch Register Summary.
SRO

Set

Reset
SR1

Bypass halt and continue to cycle

Normal test sequence consists of
Reset and disable all clocks (TTXOFF)

Set
1

Halt when error occurs
-

2. Reset and enable specified clock

(TTXON)

3. Enter Interrupt timer loop and wait for clocl< interrupt
4. Verify interrupt from specified clock and repeat steps 2 and 3,

indefinitely

(Interrupt time intervals are not stored or reported.)
Reset

Normal test sequence consists of
1. Reset and disable all clocks (TTXOFF)

2. Reset and enable specified clock

(TTXON)

3. Enter interrupt time loop and wait for clock interrupt

4. Verify interrupt from specified clock and store interrupt time interval

Repeat steps 2, 3, and 4, eight times
5. After eight clock interrupts, reset and disable clock and return to interrupt
timer loop to verify correct execution of the TTXOFF instruction

6. When the interrupt timer expires (4MS), the eight stored interrupt time

intervals may be typed

step 1

(SR 3 reset)

(SR 2 set) and the test sequence is restarted at

MAINDEC-O8-D7lA-D

SR2

Type eight successive clocl< interrupt time intervals
Reset
Bypass type routine

Set

SR3

Set

Reset
SR4

Set

Reset
d.

(step 6)
Continuously cycle through steps l-o

Halt at completion of clock test
-

Ring bell if error is detected
-

Bypass bell

Depress START. Clock test will now cycle.

Note:

Since the program stores the

clock number specified in SR 9, l0, and II each time it recycles, the number of the
clock to be tested may be changed while the clock test is cycling.

4.3

Description of Clock Test Error Halts
(halt location),

All clocl< test halts are referenced by an absolute octal memory address
and a mnemonic tag
a

(halt tag). The Description of Halt associated with each program halt provides

statement of conditions

leading to the halt and the program sequence following depression of

CONTINUE.

NOTE: Except where otherwise specified, selection of bypass error halt
(SRO Reset) will result in the program sequence described for Continue.

Halt Location

Halt Tag

206

ECTl

Description of Halt

Operator selected nonexistent clock number

(i .e.

neither clock no. l, 2, 3, or 4 was specified).
Select desired clock number and depress CONTINUE.

(SR 0 will not cause this halt to be bypassed.)
072

ECT2

Interrupt resulting from incorrect clock flag. AC
contains number of clock causing error. Depress
CONTINUE to reset and disable all clocl< flags,
enable the clock specified by SR 9, l0, and II,
and restart clock test.

Note:

If error halts are by-

passed (SR 0 reset) the clock causing the error will
be reset and disabled and the clock test will
continue.

134

ECT3

Interrupt resulting from source other than the 680
clock flags (l 2, 3, and 4) or the Model 33 Teleprinter flag.
,

Depress CONTINUE to restart clock test at location
200.
257

EC T4

Specified clock did not generate an interrupt within
Depress CONTINUE to

4 ms after being enabled.
restart clock test at

location 200.

MAINDEC-08-D7l A-D

Halt Location

Halt Tag

466

ECT5

Description of Halt

Specified clock generated an interrupt within 4 ms
after being disabled. Depress CONTINUE to reset
and disable clock and reenter interrupt timer.

5l2

End of clock test (SR 3 set).

ECT

to restart clock test at

Depress CONTINUE

location 200.

IOT AND CONTROL TEST

5.1

General Description
The IOT and control test is divided into 3 groups of related subtests involving:
a.

681 and 685 device selection (40 and 4l ,

IOT instructions (listed below) line selection register (LSR) and control

respectively).
logic

associated with the 685.

Octal Value

I9_T_
TTCL

64ll

TTSL

64l2

Operation
Clear the LSR to 0
Load LSR from AC and clear AC to 0

(AC 5-ll inclusive or to LSR 0-6)
64l4

TTRL

Load AC from LSR (LSR 0-6 inclusive OR
to

640l*

TTINCR
*

AC 5-l l)

Increment the LSR by l

Decoded in 68]
c.

IOT instructions (listed below) and control

Line Interface

Octal Value

I91

Operation
Transfer data from the 681 to the computer's

6402

TTI

logic associated with the 68l Data

MB register

6404

TTO

Transfer data from the AC to the 685

Execution of the IOT and control test does not require any connection of input data lines to

output data lines.

(Line

I77 will be addressed during any tests requiring a mark level on the in-

put data line .)
5.2

Operating Procedure
a.

Set SR to 0674 and depress LOAD ADDRESS.

Select desired program control according to the following Switch Register Summary:
SRO

Set

Reset
SRl

Set

Reset

Halt when error occurs
-

Disregard error, bypass halt and continue to cycle

Scope mode
-

Normal

test

(don't test for error, loop in current test)
cycle

MAINDEC—O8-D7lA-D

SR2

Set

Reset

SR3

Set

Reset

SR4

Set

Reset

SR5

Set

Reset
c

5.3

Verify mode (test for errors, cycle in current test)
Cycle through all tests
-

Halt at completion of all tests
-

Repeat all tests

Ring bell if error is detected
Bypass bell

Ring bell after 680 complete test cycles (approximately l0 sec.)
-

Depress START

Bypass bell
-

The IOT and control test will be executed

Description of IOT and Control Test Error Halts
All test halts are referenced by an absolute octal memory address (halt location) and a mne-

monic tag

(halt tag). The Description of Halt associated with each program halt provides a statement

of conditions leading to the halt and the program sequence following depression of CONTINUE.

NOTE:

All 680 clocks are disabled during execution of the IOT and control

test; the interrupt system is enabled (ION).

All error halts are listed below their associated subtest mnemonic and starting

address

NOTE: DST

68l-685 Device selection test group

LSR

685 Line selection register test group

T568]

68l IOT and control test group

Octal Location

Halt Tag

Description of Halt

I60

BADINT

Interrupt occurred from source other than the Model 33
Teleprinter flag.
Depress CONTINUE to clear and disable all 680 clock
flags and return to the particular test in progress.
(Note: The return address is stored in location 0)

Test DSTA
722

ERDSTI

(location 674)

AC before execution
IOT 64l4 (TTRL)

4000; the 685 is addressed via
Expected contents of AC 4000;
=

actual results are displayed in the AC
IOT 64l4 should affect AC 5-H only.
AC
as

2000,

If resulting
IOT 6414 may have been decoded in 68]

IOT 6404

Depress CONTINUE to repeat test DSTA

MAINDEC-08-D71A-D

Octal Location

Description of Halt

Halt Tag
Test DSTB

746

ERDST2

(location 724)

AC before execution

0000; the 681 is addressed via
Expected contents of AC 0000;
actual results are diSplayed in the AC
If AC 5-11 75 O, IOT 6404 may have been decoded
=

IOT 6404 (TTO).

in 685 as IOT 6414

Depress CONTINUE to repeat test DSTB
Test LSRA

1017

ERLSRI

(location 1000)

AC before execution

7777; the 685 is addressed via
Expected contents of AC 0000;

IOT 6412 (TTSL).

actual results are displayed in the AC
IOT 6412 should clear the AC to 0 at IOP2 time

Depress CONTINUE to repeat test LSRA
Test LSRB

1044

ERLSR2

(location 1023)

AC before execution

IOT 6411

7777; the 685 is addressed via
7777;

(TTCL). Expected contents of AC
actual results are displayed in the AC

IOT 6411 should not effect the AC

Depress CONTINUE to repeat test LSRB
Test LSRC

1067

ERLSR3

(location 1046)

AC before execution
IOT 6414 (TTRL)

7777; the 685 is addressed via
Expected contents of AC 7777;
=

actual results are displayed in the AC
The inclusive OR transfer of the LSR to AC should not
affect the contents of the AC
tents of the

(regardless of the con-

LSR)

Depress CONTINUE to repeat test LSRC
Test LSRD

1113

ERAC1

(location 1071)

IOT 6412 (TTS L) associated with this subtest failed to

clear the AC

Depress CONTINUE to reexecute test LSRA
1121

ERLSR4

With the AC preset to 7777, IOT 6412 (TTSL) is issued
to

load the LSR with 177 and clear the AC to 0

With the AC

0000, IOT 6414 (TTRL) is issued to load
Expected conactual
are
results
0177;
displayed in the

the AC with the contents of the LSR.
tents of AC

Error could be a result of incorrect execution of IOT

6412 or IOT 6414,

both

Depress CONTINUE to repeat test LSRD

MAINDEC-08—D71A-D

Octal Location

Description of Halt

Halt Tag
Test LSRE

1156

ERAC2

(location 1125)

IOT 6412 (TTSL) associated with this subtest Failed to

clear the AC

Depress CONTINUE to reexecute test LSRA
1164

ERLSR5

The LSR is loaded with 177 twice, via two sequential
IOT 6412 instructions (TTSL).

With the AC

0000,

IOT 6414 (TTRL) is issued to load the AC with the contents of LSR. Expected contents of LSR and AC
0177;
actual results are displayed in the AC
=

Error indicates problem in inclusive OR gating of LSR

Flip-Flops
Depress CONTINUE to repeat test LSRE
Test LSRF
1227

ERAC3

(location 1200)

IOT 6412 (TTSL) associated with this subtest failed to

clear the AC

Depress CONTINUE to reexecute test LSRA
1235

ERLSR6

The LSR is sequentially loaded with 177 and 000 via
two

IOT 6412 (TTSL) instructions

0000, IOT 6414 (TTRL) is issued to
Expected
contents of LSR and AC
0177; actual results are dis-

With the AC

load the AC with the contents of the LSR.
=

played in the AC
Error indicates problem in inclusive OR gating of LSR
flip-flops
Depress CONTINUE to repeat test LSRF
Test LSRG
1 262

ERAC4

(location 1240)

IOT 6412 (TTS L) associated with this sulotest Failed to

clear the AC

Depress CONTINUE to reexecute test LSRA
1267

ERLSR7

The LSR is loaded with 177 via IOT 6412 (TTSL).

6411

reset the

LSR to 0 and transfer the LSR to the AC

Expected contents of LSR and AC
are

IOT

(TTC L) and 6414 (TTRL) are sequentially issued to
=

000; actual results

displayed in the AC

Error indicates incorrect execution of IOT 6411

(TTCL)

Depress CONTINUE to repeat test LSRG
Test LSRH

1315

ERAC5

(location 1271)

IOT 6412 (TTSL) associated with this subtest failed to

clear the AC

Depress CONTINUE to reexecute test LSRA

MAINDEC-08-D71A—D

Octal Location

Halt Tag

1323

ERLSR8

Description of Halt
The LSR is cleared to 0 via IOT 6411

(TTCL). With the
0125, IOT 6412 (TTSL) is issued to set LSR 0, 2,
4, and 6 to 1. IOT 6414 (TTRL) is then issued to load
AC

the AC with the contents of the LSR

Expected contents of LSR and AC
are

displayed

125; actual results

in the AC

Depress CONTINUE to repeat test LSRH
1353

ERAC6

Test LSRI

(location 1327)

IOT 6412 (TTSL) associated with this subtest failed to

clear the AC

Depress CONTINUE to reexecute test LSRA
1361

ERLSR9

The LSR is cleared to 0 via IOT 6411

(TTCL). With the
0052, IOT 6412 (TTSL) is issued to set LSR 1,
3 and 5 to 1. IOT 6414 (TTRL) is then issued to load

the AC with the contents of the LSR

Expected contents of LSR and AC

displayed

are

052; actual results

in the AC

Depress CONTINUE to repeat test LSRI
Test LSRJ

1431

ELSR10

(location 1400)

The LSR is sequentially cleared, loaded and read for
all bit configurations (000—177) via IOT 6417
The expected contents of LSR and AC Following execution of IOT 6417 are displayed in the AC

Depress CONTINUE to cause the actual results to be
displayed in the AC
Depress CONTINUE again to repeat test LSRJ with the
failing bit configuration
Note: Selection of scope mode (SR1) causes the error
check to be bypassed and the current bit configuration
to

be cycled continuously

Selection of verify mode (SR2) allows the error check
to be performed and all bit configurations (000-177) to
be cycled continuously
Test LSRK

1500

ELSR11

(location 1441)

The LSR is initially cleared to 0 via IOT 6411
The LSR is now incremented from 001
successive IOT 6401

(TTCL)
through 000, via

(TTINCR) instructions.

The contents

of the LSR are read and compared following each IOT

6401 instruction
The expected contents of the LSR are displayed in the

Depress CONTINUE to cause the actual results to be
displayed in the AC
Depress CONTINUE again to repeat test LSRK for the
failing bit configuration

MAINDEC—OB-D71A-D

Octal Location

Description of Halt

Halt Tag

Selection of scope mode (SR1) causes the error
check to be bypassed and the current bit configuration
Note:

be cycled continuously

Selection of verify mode (SR2) allows the error check
to be performed and the LSR to be continuously incremented from 001

TS681A

through 000

(location 1600)

The 681 Data line Interface is addressed via IOT 6400

(NOP).

The 681 should take no action and the next

instruction in sequence should be executed.
1 625

‘ERTTOI

The instruction immediately following IOT 6400 was
not executed

Error could be a result of incorrect generation of skip

enable

Depress CONTINUE to repeat test TS681A
1631

ERTTO2

Two instructions immediately following IOT 6400 were
not executed

Error indicates that IOT 6400 was incorrectly inter-

preted as IOT 6402 (TTI)
Depress CONTINUE to repeat test TS681A
1635

ERTT03

The link bit was cleared to 0 indicating that IOT 6400

incorrectly interpreted as IOT 6404 (TTO)
Depress CONTINUE to repeat test TS681A

was

TS681B

(location 1641)

With the AC

0000 and the Link

1, IOT 6404 (TTO)

Following execution of IOT 6404 the AC and

is issued.

Link should contain 0.
1663

ERTTO4

The Link contained 1

following execution of IOT 6404

The resulting contents of the AC and Link are displayed

Check operation of zero Link and RAR in the 681
Depress CONTINUE to repeat test TS681 B
1670

ERTTOS

The Link was reset but ACO was set to 1.
contents of the

The resulting

Link and AC are displayed

Check operation of zero Link

Depress CONTINUE to repeat test TS681 B
TS681C
1715

ERTTO6

(location 1672)

With the AC
issued.

4001 and L.nk

1, IOT 6404 (TTO) is
If IOT 6404 is executed correctly the Link will
=

be cleared to 0, AC 11 will be inhibited from shifting
into the Link and AC 0-10 will be shifted one place to
the right. The expected test results are AC
2000 and
Link
0; the actual test results are displayed
=

MAINDEC-08-D7IA-D

Octal Location

Halt Tag

Description of Halt

I723

ERTTO7

Link was not reset to 0. Assuming TS68I B was executed
correctly, this error indicates failure of Link rotate
disable
Depress CONTINUE to repeat test TS68]C
AC did not contain 2000 indicating incorrect execution
of RAR

Depress CONTINUE to repeat test TS68IC
TS68lD

(location I727)

With the AC

5252 and Link

issued.

O.
I75]

ERTT08

0, IOT 6404 (TTO) is

test results are

2525 and Link
AC
Expected
The actual test results are displayed

Link was set to I

Check for incorrect execution of

CML

Depress CONTINUE to repeat test TS681D
I 760

ERTTO9

AC did not contain 2525 following execution of IOT
6404. Check execution of RAR

Depress CONTINUE to repeat test T568] D
TS68IE

(location 2000)

This test verifies correct execution format of IOT 6402

(TTI)
IOT 6402 instruction format:
Location A (6402)
A+l

A+2
A+3

(LSW)
(CAW)
(XXXX)

TTI Instruction

Line Status Word

Character Assembly Word
Next Instruction in

Sequence
A+4
2020

ERTTII

(XXXX)

The contents of AH

were

incorrectly interpreted as an

Check for generation of the S cycle and
its associated control functions (e.g.
TTSET, PC“‘>MA,
instruction.

Enable, Spec. cycle)
Depress CONTINUE to repeat test TS68I E
2024

ERTTI2

Location A+I

was

correctly interpreted as the LSW but

A+2 was incorrectly interpreted as an instruction.

2030

Check for correct operation of skip bus in enable during
the S cycle
Depress CONTINUE to repeat test T568] E

ERTTI3

The instruction in location A+4 was the first instruction
executed after completion of the TTI instruction.

Since
A+3 was not executed check for incorrect (extra) skip

enable during the S cycle

Depress CONTINUE to repeat test TS68I E

MAINDEC-OB-D7lA-D

Octal Location

Description of Halt

Halt Tag

TS68l F

See IOT 6402 format (pg

(location 2034)

l0)

With the LSW and CAW preset to 2000, IOT 6402 (TTI)
is issued

Correct execution of IOT 6402 should result in the contents of LSW shifted one position to the right with

LSWO

0 (resulting LSW

unmodified (resulting CAW

1000). The CAW should be
2000)
=

The LSR is loaded with l77 before the test is

Note:

executed

2073

ERTTI4

Resulting LSW 7-! l000. Actual results are displayed
in the AC. Check operation of shift MB
Depress CONTINUE to repeat test TS68l F

2l04

ERTTI5

The LSW was shifted correctly but LSWO
a

l indicates

level on the Teletype data in lead.

start

operation of MBO shift enable.

Check

(Resulting LSW is dis-

played in the AC)
Depress CONTINUE to repeat test TS681F
2] l5

ERTTI6

10, and II were 75 0 following execution of

LSW 9,

IOT 6402 indicating incorrect execution of count MB

Depress CONTINUE to repeat test T5681 F
2l2]

ERTTI7

Resulting LSW 7g l000. Actual results are displayed
in the AC
error

Check for a combination of the above three

conditions

Depress CONTINUE to repeat test TS68l F
2l27

ERTT18

CAW was modified; results are displayed in the AC

Check for incorrect generation of C cycle. (C cycle
l and LSW 9, l0,
should be executed only when LSWO
=

and II

0, I, 1, respectively)

Depress CONTINUE to repeat test TS681F
TS68l G

(location 2200)

See IOT 6402 format (pg

10)

With the CAW preset to 4000 and the LSW present to
the condition required for entry into the C cycle

(LSW

4003), IOT 6402 (TTI) is issued.

ecution of IOT 6402 should result in LSW

CAW
Note:

2234

ERTTI‘?

Correct ex=

The LSR is preloaded with 177

st # 4004.

Check operation of count MB, shift MB
(The actual LSW results are

and MBO shift enable.

displayed in the AC)
Depress CONTINUE to repeat test TS68l G

4004 and

6000

MAINDEC-08-D7IA—D

Octal Location

Halt Tag

2246

ETTIIO

Description of Halt
CAW 7‘ 6000.

(Actual CAW results are displayed in
shift MB,
MBO shift enable, TTSET, etc.)
Check C cycle execution (e.g.

the AC).

Depress CONTINUE to repeat test TS681G
2252

ETTIll

CAW 7'5 6000,

contents of

location A+3 were modified

(Actual results of CAW are displayed in the AC)
Check for incorrect sl<ip enable during the S cycle
Depress CONTINUE to repeat test TS68l G
TS68l H

(location 2262)

See IOT 6402 format,

(pg. I0)

IOT 6402 (TTI) is issued with successive LSW counts of
4, 5, 6, 7, 0,'l and 2 (i.e., 4004 4002)
-

The LSW and CAW are examined after each TTI execution to insure correct execution of count MB and correct
LSW count interpretation
Note:

2 340

ETTII2

The LSR is preloaded with I77

LSWO was reset to 0 (resulting LSW is displayed in AC)

Check operation of S cycle MB shift

Depress CONTINUE to repeat test TS68l H
2347

ETTII3

The LSW count was not correct following execution of
IOT 6402.

The expected contents of the LSW are
in the AC

displayed
Depress CONTINUE to display the actual LSW results
Depress CONTINUE again to retest failing count
236]

ETTII4

The CAW was modified indicating incorrect entry into

(Expected contents of CAW

C cycle.

"—‘

4000, actual

CAW results displayed in AC)

Depress CONTINUE to retest failing count
Note: Selection of scope mode (SRI) causes the error
check to be bypassed and the current LSW count to be

cycled continuously
Selection of verify mode (SR2) allows error check to
be performed and LSW counts 4 through 2 to be continuously tested
TS6811

(location 2400)

This test verifies correct Operation of MBO (I) shift
enable and MBI-ll (I) shift
2440

ERMBSI

Incorrect MB shift results.

Expected results are displayed

in the AC

Depress CONTINUE to display the actual MB shift
results in the AC
Depress CONTINUE again to retest failing MB shift
Note: Selection of scope mode (SRI) causes the MB
shift error check to be bypassed and the current MB
shift configuration to be cycled continuously

MAINDEC-OB-D7IA-D

Octal Location

Description of Halt

Halt Tag

Selection of verify mode (SR2) allows the MB shift error
check to be performed and the full MB shift test to be

cycled continuously
TSéBIJ

(location 2456)

This test verifies correct operation of MBI-ll
2517

ERMBS2

Incorrect MB shift results.

(0) shift

Expected results are displayed

in the AC

Depress CONTINUE to display the actual MB shift results in the AC
Depress CONTINUE again to retest failing MB shift

(See note for T568ll)
TSéBIK

(location 2600)

This test verifies correct operation of MB shift via a
shift pattern of alternate Is and Os

2654

ERMBSB

Incorrect MB shift results.

played

Expected results are dis-

in the AC

Depress CONTINUE to display the actual MB shift
results in the AC
Depress CONTINUE again to retest failing MB shift
(See note for TSéBII)
2674

ENDTST

End of Static Test.
all tests.

Depress CONTINUE to repeat

MISCELLANEOUS

It is suggested that the IOT and Control Test be run with appropriate voltage margins before

attempting to execute the 680 DCS Data and Control Test (MAINDEC-08-D72A-D)
7

PROGRAM_gSTING
EXPANDED

lbfifl

DCS

/IUT

INSTRUCTIUN

STATIC

TEST

DEFINITIONS

TTlOFF=6422
TT20FF=6432
TTSOFF=6449
TT4OFF=645P

TTIUNz6424
TT?0N:6434
TT30N=6444
TT40N:64S4

TT1$KP=6421
TTPSKP=6451
TTSSKP=6441
TT4$KP=6451

MAINDEC-OS-D7IA—LA

REGISTFR

/SRITCH

SETTINGS

FOR

IOT AND CONTROL TEST:

/SRO

/SR1
/SR2
/SR3
/SR4

/SR5

HALT

—

ERROR

(DON'T TEST FOR ERROR: LOOP IN CURRENT TEST)
VERIFY MODE (TEST FOR ERRORS. LOOP IN CURRENT TEST)
HALT AT COMPLETION OF STATIC TEST
SIGNAL ERROR WITH BELL
SIGNAL COMPLETION OF 4096 TEST CYCLES:

SCOPE

—

MODE

/SR1
/SR2
/SR3
/SR4

SETTINGS FOR 680 CLOCK TEST:
HALT 0N ERROR
SCOPE MODE
TYPE 8 SUCCESSIVE INTERRUPT TIME INTERVALS,
HALT AT COMPLETION OF CLOCK TEST
SIGNAL ERROR WITH BELL

/SwITcH
/SRO

—

/PAGE
%

CONSTANTS

?ERO¢

AND

(SR1

RESET)

SUBROUTINES

i3
(/3

0000

A001

3010

INTRPT.

A002

7010

PAR

A003

3011

OCA

STORL

A004

5142

JMP

CHTPTR

A005

V345

CLSURR.

A006
A007

V000

cOUNT,

0000

A010

0000

KEFPAC.

0011

V000

STURL.

0012
A013

U000

v200

MSKSR4.

OZMO

A014

0207

RELL.

0207

A015

4000

DCA

/STORE

KEEPAC

/STORE
/TEST

FOR

LINC

TELEPRINTER FLAG

JMPC Ll-l

S<§S

4000

/CONTAINS CLOCK
/EOUALS ZERO TO

INTERRUPT COUNT IN MSEC
lST CLOCK INTERRUPI

SIGNIFY

MAINDEC-OB-D7IA-LA
*0020

SNITCH

/DFCODF
SRO,

4020

V000

4081

7604

CLA

DSR

4022

$015

AND

MSKSRO

4023

7640

SZA

CLA

4024

0020

ISf

SRO

A025

7604

CLA

A026

V013

AND

DSR
MSKSR4

0027

7640

SZA

CLA

/RING

4050

c032

JMP

.+2

/YES

A051
4032
A033

R420

JMP

#002

IOF

1014

TAD

4054

6046

TLS

0055

6041

4056

9035

6041
JMP .-l

A037

7300

CLA

0040

6001

ION

0041

L420

JMP

A042
4043

0000

7604

CLA

OSR

A044

V050

AND

MSKSR1

A045
0046

7640

SZA

CLA

9042

ISZ

SR1

A047

R442

JMP

0050

7000

MSKSR1.

A061

I”000,

SR2,

4052

7604

CLA

”SR

4053
0054
4055

V057

AND

MSKSRZ

7640

SZA

CLA

2051

18%

SR2

A056

c451

JMP

0057

1000

MSKSRZ,

A060

V000

/UECDDF
SR5.

0061

7604

CLA

OSR

4052

0066

0ND

MSKSR3

1053

7640

CLA

0064

?060

SZA
IS?

a0o5

9460

JMR

0066

0400

MSKSP3.

/ADD

ONE

RETURN

ADDRESS

SRO

SET

BELL?
/N0

SRO

RELL

TELEPRINTER

/SKIP

/ADD

ONE

RETURN

ADDRESS

SR1

SET

/ADD

ONE

RETURN

ADDRESS

SR2

SET

/ADD

ONE

RETURN

ADDRESS

SR3

SET

FLAG

CLL
I

/DECODE

SRO

SwITCH

SR].

/DECDDF

SR1
2000

SWITCH

SR2
1000

SWITCH

SR3

SR3
0400

MAINDEC-O8—D7IA-LA
/COME

HERE

9067

4920

/CLOCKI
ERCLI,

0070

R(674

JMP

.+4

A071

1126

TAO

ONE

4072

74%?

ECT2.

A073

c~477
6422
“saw

V220

ACLELG.
ARSTRT,

A1wg

0233

AINTONI

Alfll

4620
R19.36

W1U3

1127

41M4

SD72

TAD
JMP

A1US
A1W6
fl1U7

“477

JMP

ERROR
JMS SRO

/HALT

/RESET
/RETURN

AND

(SRO

HALT?

DISPLAY

TEST
DISABLE CLOCK

SET)

ERROR

CLOCK

AND

FLAGl

TIMER

/DO

/OON'T

,+4

WISH

HALT?

(SRO

SET)

HALT

TWO

ECT2
I ARSTRT

TTZOEE

”11%
4111
4112
3113

4020

ERCLS,

c>115
1130

JMP

,+4

TAD

THREE

6072

JMP

$114

S477

JMP

ECT2
ARSTRT
I

/CLOCK3

A115

6442

TTSOEE

A116

Esme

JMP

”117

462%

ERCL4,

412@
’I121
4122
0123
A124
4125

5124

JMP

1131
S072

TAD
JMP

/CLOCK4

AINTON
IN

/OO

/DON'T

AINTON
IN

/HALT AND DISPLAY ERROR CLOCK NUMBER
/RE-INITIALIZE CLOCK TEST
/RESET AND DISABLE CLOCK ELAG2
/RETURN TO TIMER

ERROR
JMS SRO

/DDN'T

.+4

EOUR
ECT2
JMP I ARSTRT
TT4OEE
JMP I AINTON

9001
9002
RODS

ONE.

DOOI

TWO,

THREE,

ODDZ
ODDS

A131

VOO4

EOUR.

OOM4

WISH

/HALT

(SRO

HALT?

SET)

HALT

/HALT AND DISPLAY ERROR CLOCK
/RE-INITIALIZE CLOCK TEST
/RESET AND DISABLE CLOCK FLAC
/RETURN TO TIMER

ERROR
JMS SRO

4127
4160

A126

/RE-INITIALI?E CLOCK

ERROR
JMS SRO

JMP

6452

WISH

HALT

SELECT
INTON‘l

SSOO

S500

/DO

/DON'T

6432

S477

INTERRUPTS

CLRELG

/CLOCK2
ERCLZ.
JMP

CLOCK

HLT

A075
A076
5077

41%2

WRONG

JMP I ARSTRT
TTIOEE
JMP I AINTON

A674

V232

/DO
HALT
AND

DISPLAY

WISH

ERROR

/RE-INITIALIZE CLOCK TEST
/RESET AND DISABLE CLOCK
/RETURN TO TIMER

NUMBER
3

(SRO

HALT?

CLOCK
FLAG

NUMBER
4

SET)

NUMRER

MAINDEC—O8—D71A-LA
/INTERRUPT
4152
4133

R477

NOFLAC.
JMP I

4154
4155

7402

ECTs.

:«477

JMP

492m

FROM
JMS

UNDETERMINFD

/DO

/DON'T

ARSTRT

4156

V000

TIMOUT.

V000

TSF

0140

V000

0141

0000

3142

£041

CHTPTR,

“153

JMP

4144

6042

TCF

4145

7300

INTERRUPT

/CLOCK INTERRUPT
/CONTAINS NUMBER

SOURCE

AND

TIME-OUT STATUS
BEINC TESTE

CLOCK

4146

1011

A147
4150
0151
4152

7004

RAL

1010

TAD

6001

ION

9400

JMP

4153

1136

A154
4155
4156
4157
4160

7500

Jlbl

6422

4162
0163
A164

6432

TT10FF
TTZOFF

6442
6452

TTSOFF
TT4OFF

0165

5145

JMP

/SKIP

TELEPRINTER

FLAG

SET

CHKINT
/CLEAR

/RESOME NORMAL PROGRAM
CLA CLL
RNPS.
TAD STORL

TELEPRINTER

FLAG

SEOOENCE

/RESTORE LINC
/RESTORE

KEEPAC

BIT
AC

INTRPT—1

/TEST INTERRUPT
CHKINT,
TAO

STATUS

TIMOUT

/SKIP

4020

JMS

CLSURR
SRO

‘161

JMP

.+2

7402

RADINT,
/CLEAR

HALT?

4143

SMA
JMP

/UNDETERMINFD

HLT

CLOCK,
STORAC.
AUXAC.

WISH

HALT

ARSTRT

J157

5405

SOURCF

SRO

FOR

/TEST

/HALT

OCCURRFD

ERROR?

/NO

HLT
AND

IF INTERRUPT ERROR HAS
SPECIFIED CLOCK FLAG

DISABLE

/HALT
ALL

680

CLOCK

RNPS

FLAGS

DUE

INTERRUPT

ERROR

MAINDEC-OB—D7IA-LA
/6HO

DCS

TEST

CLOCK

/LINE

STATIC

EXPANDED

*ZWO

/OPERATOR

Izflfl

7604

SELECT,

wgwl

V342

AND

CLA

92W?

3137

DCA

CLOCK

1137

CLOCK

apn4

7440

TAO
SZA

I2o/IS
42/6

F521?}
7402

JMP

.+3

ECT1,

4227

RZOO

JMP

SELECT

I210
4211

1343

TAD

75OO

SMA

3212

R206

JMP

OSR

/PRINC S.R.
INTO A.C.
/OISREGARO ACO-ACB

/STORE

CLOCK

HLT

SELECTION
THAT

CLOCK

/OPERATOR

/SKIP

MINUS

1-4

SELECTED

NON

EXISTANT

CLOCK

.—4

SELECTED

cLOcK

RESTRT,

I214

73OO
1345

TAD

JMPADO

4215

1137

TAD

CLOCK

4216

KOOS

OCA

CLSURR

4217

3136

OCA

TIMOUT

A29g

3007

OCA

FSTPAS

/RESET

AND

2221

6422

TTlOFF

6432

TTZOFF

0223

6442

TT3OFF

1294

6452

TT4OFF
/ENARLE

EXISTANT

SURROUTINE

CLA

0222

SELECTED

1137

TAD

4226

7106

CLL

RTL

0227

7Ufl4

RAL

7250

1352

A251
“252
A253

3232
10M7

ALLCLK
CLRFLG
b4?4
CLRFLG.
TAD Z ESTPAS

1234

60W1

INTON,

4255

764m

SEA

CLA

4236

9241

JMP

0257

8240

JMP

TIMER+1
TIMER

WITH

CLOCK-PROCEED

ADDRESS

TEST

POINTER

CLL

/CLSUBR NOW POINTS TO CORRECT CLOCK
/SUBROUTINE
/RESET TIME-OUT ADDRESS POINTER
/RESET FIRST PASS INDICATOR

DISABLE

3225

6424

NUMPER

/VERIFY

/OPERATOR

/SFT

CLOCK

MASK1

3243

9213

SPECIFY

MUST

ALL

CLOCK

FLAGS.

(64X2)

CLOCK

TAD

DCA

/THIS
/SPECIFIED

INSTRUCTION

/ENABLE

ION

/DON'T

MODIFIED

CLOCK

RESET

COUNT

THE

INTERRUPT

FSTPAS

ONE

SYSTEM

ENABLE

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MAINDEC-OB-D7TA-LA
/INTERRUPT SUBROUTINE
TTISKP
CLOCKZ,
JHP .+?
JHP P FRCLI
TTSSKP

CLOCK

/SKIP

“275
..2'Ib
1277
*3fl0

#421
R300

L3m1
93m

r‘3913

JMP

8110

ASMS
4354
nsws

6451

JHP
TT4SKP

S117

03M6
A3M7

6431

TTZSKP

8132

JMP

NOFLAG

/NO

”31%

5741

JHP

CLOKOK

/INTFRRUPT

”311

6421

0312
3313
4314

6314
6067

A315
U316

‘067

6441

8396

6431
9317

1321

5101
6451
6322
S117

7322
4323
0324

6441
6132
:741

4325

6421

W396

5330
6067

A317
”3)“

1327
436%

6431

.+2
Z ERCL3

/CLOCK 1 FLAG
/SKIP IF

SET

/CLOCK 3 FLAG
/SKIP IF

SET

JHP .+2
JHP Z ERCL4
/CLOCK
/VERIFY THAT SPECIFIED CLOCK

/INTERRUPT SUBROUTINE
TTlsKP
CLOCKS,
JHP ,+2
JMP Z ERCLI
TTZSKP
JMP ,+2
JMP Z ERCL2
TT4SKP
JMP
JMP

4 FLAG
CAUSED

WRONG

FLAG

SET.

CLOCK

FLAG

SFT

(CLOCK

CLOCK

FLAG

SET

(CLOCK

FLAG

SET,

SET
CAUSED BY

CORRECT

CLOCK

/SKIP

/CLOCK 1 FLAG
/SKIP IF

SET

FLAG

SET

/SKIP

WRONG

CLOCK

FLAG

SET.

CLOCK

FLAG

SET

(CLOCK

CLOCK

FLAG

SET

.+2

/CLOCK 4 FLAG SET
Z ERCL4
/VERIFY THAT SPECIFIED CLOCK CAUSED INTERRUPT
TTSSKP
/NO CLOCK FLAG SET
JMP Z NOFLAG
/INTERRUPT CAUSED BY CORRECT
JMP I CLOKOK

/INTERRPT SUBROUTINE
TTISKP
CLOCK4,
JMP .+?
JMP Z ERCLl
TTZSKP

/SKIP

/CLOCK 1 FLAG
/SKIP IF

SET
WRONG

/CLOCK 2 FLAG
/SKIP IF

SET
WRONG

WRONG

CLOCK

FLAG

SET

(CLOCK

CLOCK

FLAG

SET

(CLOCK

.+2

JMP

1354
4335

5101
6441
9336
5110

4355

6451

1367

E13?.

434m

5741

Z FRCL3
/CLOCK 3 FLAG SET
/VERIFY THAT SPECIFIED CLOCK CAUSED INTERRUPT
TT4SKP
/NO CLOCK FLAG SET
JMP } NOFLAG
/INTFRRUPT CAUSED BY CORRECT
JMP I CLOKOK

4341

M400

CLOKOK.

ERCL2

TT3SKP

CLOCK

JMP

‘

JMP
JMP

(CLOCKI)

SET
INTERRUPT

8333

4331
4332
4353

CLOCK

FLAG

CLOCK

/CLOCK

WRONG

.+2

COMCLK

CLOCK

(CLOL

)

MAINDEC-OB-D7lA-LA
4342

WOO7

MASKl;

0343

7773

MS.

-5

Asaa

V470

AEXIT,

FXIT

A345

V345

JMPAOD,

"346

5261
5275

/INTERRUPT

4347
435%

‘3311

6361

L~325

MMM7

ADDRESS POINTER
JMPCLl-l

/JUMP TO SPECIFIED CLOCK
JMP CLOCKl
JMPCLl,
JMP CLOCKZ
JMP CLOCK3
JMP CLOCK4

4352

6414

ALLCLK.

6414

0353
”354

vzwe

nsfis

0017

PASS.
M412:
TIME.

7366

SUBROUTINE

/N0

INTERRUPT

TIME

OUT

COUNTER

"412

/OCTAL

17
/FOH

ONE

TIMER

LOOP

TIME.

MICROSECONDS,

RFOUIPEF

MAINDEC-O8-D7I A-LA
#400

/INTERRUPT
14M)

7300

COMCLK.

ROUTINE
CLL

1401

1136

TAD

14A2

7640

SEA

CLA

1403

S264

JMP

INTERR

4404

1007

TAD

TIMOUT

4405

7640

SZA

CLA

0217

JMP

NORMAL

4407

1234

TAD

441%

3237

DCA

4411
4412
1413

1241

TAD

3240

DCA

2007

P142

INTERRUPT

COUNT

4416

S476

JMP

4417

4042
6223

4423

SPECIFIED

NOT

/RETURN

ACLFLG

JMP

2240

IS?

1006

TAD

STORE
Z COUNT
I

13T

INTERRUPT

PASS

COUNTER

ADDRESS

COUNT

3640

DCA

9237

A427

S231

ISZ
JMP
JMP

LSTPAS

1450

5252

4451
0462
A453

1236
3006

TAD

P161

DCA

COUNT

S476

JMP

4434

7770

M1,Mp

STORAGE

'1M

A435

9142

P142.

0142

04é6
4440

00am

4441

V441

P161.
INTCNT,
STORE.
ATABLE.

0161

4457

0161
uemm

1442

V000

TIMTBL.

4443

V000

RE-ENTERING

BEFORE

INTERRUPT

TIMER

PASS

/SCOPE

MODE?

(SR1

SET)

/N0

/YES:

ENABLE
TO

AND
TIMER

CLEAR

CLOCK

AND

FLAG

PASS?

/N0

/YES.
/PRESET
/RETURN

ACLFLG

CONSTANTS

COUNT

/STORE INTERRUPT TIME INTERVAL
/IS THIS THE EIGHTH INTERRUPT

STORE
INTCNT
.+2

0425

INTERRUPT

/RETURN

ACLFLG

A476

THE

CLOCK

/PRESET

/COME HERE FOR NORMAL
JMS Z SR1
NORMAL.
JMP .+3
DCA E COUNT

/PG2

/JUMP TO ERROR ROUTINF
THE 18T INTERRUPT?

/PRESET

DCA

A424

STATUS

FSTPAS

3006

FROM

INTERRUPT

THIS

/PRESET

1235

e476

CLOCK

ATABLE
STORE

1414

A421

/IS

M10
INTCNT

4415

d422

CLOCKS

/THIS

182
TAD

A420

ALL

/CHECK

FSTpAS

4406

/FIRST

CLA

AND

DISABLE

CLOCK

COUNT BEFORE
TO TIMER

FLAG

RE-ENTERING

TIMER

VARIABLES

TIMTBL-l

/INTERRUPT TIME INTERVALS FOR
/SUCCESSIVE PASSES WILL BE STORED IN
/THIS

1444

V000

1445

V000

H446

0000

A447

V000

4450

9000

4461

V000

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MAINDEC-OB-D7I A-LA
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JMP

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JMR

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JMR

SR?

/VERIFY

TTSL
SRO

REPEAT?

(SR2

SET)

(SR2

SET)

/HALT

ERROR?

/HALT

ERROR?

/NO

FMFXTl
HLT

/REPFAT

ALSRA

LSRE

FAILED
J49 Z

TEST

LSRA

SRM
/NO

FNFxTz
Z

RESULT
/§COPE

HEAD

L2/1

/TFST

(D)

/AC

/STUHE

/SKIP

LOT

LSR

/NO

L222
L??3

/Au

STILL

TTRL

JMP

DMD.

TRACE

MQT’VL

AND

177

/NO

/WAS

AJXAC

114%

1237

/STORE

AUXAC

1215
L217

CMA

/AC9-11
Z

L216
LPRD

OLA

/7777

12/01

RTORAC

HLT

/AC

/REPEAT

LSRF

-177

TEST

AND

LSRF

LSR

SHOULD

EQUAL

177

MAINDEC-OB-D7TA-LA
/TFST

LSRG

TRY

CLL

CLA

CLEAR

LSR
/7777

CMA

124M

734%

1241
L242

6412

TTSL

744M

SEA

1243

8266

JMP

1244

6411

L245

6414

CNFXTl,
TTPL

L246

314%
A842

OCA

}

STORAC

L247

JMS

SR1

125%

%262

JMP

.+?

/NO

1251
1252

L24‘?)

JMP
TAD

LSRG
Z STORAC

/YES

114W

1253

744m

82A

1254

9264

L255
L266
1257

4051
L271
L524m

JMP
JMP

126%

4®70

/AC NOT
FRACC.

1261

6244

JMR

74m?

FRAC4,

“766

JMP

l2h4

402%

1265

‘*2‘55

L256

1140

1207

74%?

127M

324M

CLEARFD

TTCL

ZERO?

/RESET LSR TO ZFRO
CONTENTS OF LSR
READ RESULTS
/SCOPE REPEAT? (SR1

/READ

/STORE

/OOES

EQUAL

SET)

ZERO?

/NO

/VERIFY

SR2

LSRH

/NO

LSRG

/YES
RY TTSL
JMS z SRM

REPEAT?

(SR2

SET)

RESET

/HALT

ERROR?

(SRO

SET)

/HALT

ERROR?

(SRO

SET)

/NU

GNFXT1
HLT
I

/REPEAT

ALSRA

/T{ST LSRG FAILED
JMS Z
ERLSRG,
JMP CNFXTz
TAn 4 STORAC
HLT
ERLSR7.
JMP

/wAS

LSR
/NO

PRLSRG
JMS
GNEXTZ.

1202

FRACG

JMP

1963

/ACS-11

LSRG

TEST

LSRA

SRO
/N0

/IOT

/REPEAT

TEST

6411

LSRG

DID

NOT

CLEAR

LSR

MAINDEC—O8-D7TA—LA
/TFST

LSRH

SFT

LSR

AND

~41l

LSHH.

73mm

CLA

CLL

i?73

13?5

TAD

C1?5

L2/4

#412

TTQL

/AC5-11

L275

744m

S£A

/DID

IP76

“313

JMP

l?77

#414

HNFXTI,

LSflfl

314%

HCA

QTORAC

L K V? 1

4W4?

JMS

9R1

LSAZ

R3W4

JMP

.+?

/NO

/YES

R271

JMP

LSRa

1146

TAD

L3fi5

1376

TAM

M1?5

13fi6

744M

85A

/STURE

EQUAL

/SKIP

FQUAL

AC?

SFT)

HNEXTQ,

L311

R3?7

JMP

LSRI

/NO

1312

5271

JMP

LSPH

/YES

L313

am2w

FRACH,

L314

A277

JMP

1315

74“?

FRACS.

L316

R766

JMP

L317

4g?“

L32M

“31%

JMP

L591

71mm
114%

CLL

7407

FRLSRB,

L524

L271

JMP

1395

”IRS

C125,

M195

L326

76R$

M1?5.

~U1?5

FRlbfiH

JMS

RESET

JMS

SR?

/VERIFY

TTSL
99%

RFPEAT?

(SR2

<3T)

/HALT

ERROR?

(SRm

§ET)

/HALT

ERROR?

(SRM

SET)

/NU

HNPXTl
HLT

/YES

/REPEAT

ALSRA

/TEST LSRH
FRLSRH,

MIPS?

/NO

JMP

4M51

TEST

LSRA

FAILED
JMb

SRM
/NO

erng
?

LSP

RESFT

/DOFS

5317

TAD

RFC

STDRAC

L3fl7

SELFCTIDN

/READ LSR T0 AC
RESULTS
/SCOPH REPEAT? (SR1

READ

131%

NOT

LINE

/N0

TTRL

L3fl3

L392
L393

TTSL

FRACH

'L 3 M? 4

DNF

/9ESET

TTCL

1271
1272

/AC

STDRAC

HLT

/AC

/REPEAT

LSRH

TEST

AND
LSRH

LSR

SHOULD

FUUAL

125

MAINDEC-OB-D7TA-LA
/TFST

LSHI

LSRl.

SET

AND

ONE

/RESET

1327

F411

LSHI.

1350

73mm

CLA

CLL

L3€1
1332

1363

TAD

PCS?

6412

TTSL

/AC5‘11

1333

744%

85A

/DID

1334

R361

JMP

L335

6414

INEXTl.

1336

314m

DCA

TTCL

TTHL
STORAC
591

/STORE

4042

JMS

JMP

.+?

/NO

/YES

1341

“(542
“327

JMP

LSQI

1342
L343

114%
1364

TAD

STORAC
MMSQ

L344

744a

1345
1346

9355

82A
JMP

ERLSRI

1347
1350

JMP
JMP

/DOES

ALSRJ
LSRI

9335
74%?

FRACé.

1354

5766

JMP

L355

402%

1356

;5346

l3b7

71mm

1350

114%

1301
1362

7402
L3P7

HLT
ALSRA

LSRI

M52?

/VERIFY
/NO.

/AC NOT QESET RY TTSL
ERACT.
JMs 2 SR“
JMP INEXTl

/TEST

EQUAL

SR2

SET)

/NO

JMS

1351
L352
1353

4690

AC?

/READ LSR T0 AC
RESULT
/SCOPE REPEAT? (591

TEST

1337

INEXT2.

LSR
RESET
/N0

ERACI

i340

4G81
L765
8327

TTSL

LSR

ENTER
/YES.

NEXT TEST
REPEAT TEST

REPEAT?

(SR2

SET)

LSRI

/HALT

ERRoR?

(SHM

SET)

/HALT

ERROR?

(SRW

SET)

/N0

/REPEAT

TEST

LSRA

FAILED

JMS
ERLSPI.
JMP INEXT2

SRm
/N0

CLL
TAU ¥ STORAC
HLT
ERLSRQ,
JMP LSHI

1363

l70‘32

CMB2,

1364

7726

M052.

~ww52

L365

140%

ALSRJ.

LSRJ

1366

160W

ALSRA,

LSRTST

/AC

/REPEAT

MM62

TEST

AND
LSRI

LSR

SHOULD

EQUAL

M52

MAINDEC-O8—D7TA-LA
*14AM

/TEST

LSRJ

CLEAR.

LOAD

AND

LSR

REAR

IANM

73vn

LSRJ,

L4/1

1237

UCA

1452

1?37

TATI

14A3

#417

6417

1454

314W

RCA

QTORAC

14x5

am42

JMS

9R1

1446

c2m

JMP

.+?

/NO

14fi7

rraw-«I2

JMR

LSPJ+2

/REPEAT

LAIM

1737

TAO

LINCNT

L411

7w41

CIA

L412

114w

TAO

L413

744%

SZA

1414

L225

I415

9237

L416

1937

JMP

CLL

/RESET

/WAS

RTURAC

124a

TAT)

VQI/TM

7640

52A

FLA

L421

L2w2

JMP

LSRJ+2

L422

Awa1

JMS

I423

9241

JMP

LSRK

L424

RQVfi

JMP

LRRJ

L485

aw?m

14/6

“215
71mw

CLL

1237

TAM

L4fi]

74w?

FLlew,

145?

72mm

FLA

SAME

LINE

SET)

(SR1

NHMHER

INCREMENT

LINE

COUNT

ENTER

/YES$
NEXT

VERIFY
TEST

177

LINE

BEEN

COUNT

TESTED?

/NO

/NO,

FAILED
JMS Z

SRM

REPEAT?

/HALT

ERROR?

(SRO

SET)

/NO

JNFXTI

14/7

REPEAT?

/YES:

LINCNT

9R?

/TEST LSRJ
FHLSHJ,

L45W

WITH

LSR

READ

AND

/AC EOUALS MINUS LINCNT
CORRECT LINE COUNT READ?

/HAS

L417

LOAO

RESULT
/SCOPF

RFAO

/NO

ERISRJ

IS?
JNEXTl,
TAO LIVCNT

JMP

/STORE

COUNT

LINE

/CLEAR,

I42M

6417)

CLA

LIACNT
LIPTTNT

(IOT

LIACNT

/HALT

HLT

WITH

CORRECT

LINE

COUNT

RTURAC

L453

114m

TAD

L434

74%?

HLT

14€5

720%

FLA

1456

5?“?

JMP

L457

(BMW

LIRCNTy

L44M

76PM

M2I/‘fl’

“VTQQWI

/HALT
L9HJ+2

WITH

INCORRECT

TEST

RESULT

MAINDEC-OB—D7lA-LA
/TEST
1441

73mm

LSHK.

1442

3237

HCA

1443

+411

TTCL

LSRK

CLL

£4fi1

ADDl.

4042

JMS

1446

825m

JMP

.+?

L447

6271

JMP

145%

9237

IS;

AGAIN
LINCNT
LINCNT

1237

TAD

$313

AND

3237

DCA

1454

6414

TTPL

L465

314a

UCA

LINCNT

TAD
CIA

1440

1140

TAD

1441

744:8

SEA

1402

r~274

JMP

177

LINE COUNT
LSR T0 ZERO
/INCRFMENT

TTINCR

1451

1237

/CLEAR

/SCOPF

SR1

i432
1453

7641

“WM

FROM

/CLFAR

1444

L457

LSR

CLA

LINCNT

1445

L456

INCREMENT

LSR

REPEAT?

ONE

(SR1

/NO

/YES

C177K
LINCNT
STORAC

/READ
/STORE AC
/AC

LSR

CONTAINS

—

LINE

COUNT

STORAC
/DID

ERLSRK

/N0

LSR

INCREMENT

CORRECTLY?

SET)

MAINDEC-OB—D7T A- LA
I403

1237

KNIXT,

1464

744%

5ZA

1455

L?44

JMP

TAU

/YES

LINCNT
/DOFS

/YES;

8R2

"651

JMS

I447

“512

JMP

fXLSH

141%

“741

JWP

LSHK

1471
L472

1237
(413

AGAIN,

L473

L244

JM9

14/4

”0?”

FRLSPK,

Ld/S

“[263

1476
14/7

\TMP
CLL

1237

TAM

LIVCNT

S'M

74w2

FLSRll,

72MM

CLA

AQJNH

114M
74w2

TAD
HLT

72v”?-

CLA

LS; UT

1237

TA“

LIWCNT

IS/b

1314

TAD

/SURTRACT

15fi7
LSJM

'313
7237

ANN

DOA

P177K
LINCNT

/HETEST

L271

\JP’IP

AGAIN

“715

FXLSR,

JMP

L5“
LSv

LSfi

:54

I511

71““

HFPFAT

/YES.

(8H2

SFT)

LSRK

REPEAT
LINCNT

TAU

6413

/L8Q

RFPEAT?

VERIFY

/NO

QCOPE

“MM

/NO

AOfll

L456

/SET

EQUAL

COUNT

LINF

bflfll

WIN

NUT

INGREMENT
JMS

/CLFAR

LSR

/LINE

(NTUNT

WITH

CURRENT

CORRECTLY
/HALT

ERROR?

(SHfl

SFT)

/NO

/HALT

HLT

wITH

CORRECT

LINE

s,TIFRAC

/HALT
/IN

1513

I177

C177“:

@177

i514

7777

M 1

-£M®1

3515

1, 6 M ’1’.

ATHéhl.

LOAD

SR”

VFXT

AND

INCORRECT

wITh

SAME

/EMTFR

ATSbBl

T8681A

LINE

COUNT

FROM

LINE

681

COUNT

INSTRUCTION

TESTS

COUNT

MAINDEC-O8-D7IA-LA
PAUSE

J(d .1!-

EXPANOED STATIC
INSTRUCTION TFST

nus

/68O

/681

TFST

TAPE

*16OM

/TS681A
TdelA.

—

681

ACTIVITY

(TOT

TEST

72VO

lbfll
1652

1237

TAD

32M7

UCA

OKJMPl
NOAC+1

16m3

124w

TAD

FRJMPI

16%4

321w

UCA

NOAC+2

/PRESET

16W5

712W

ELL

CML

16W6

(*4WW

NOAC r

16W7
1610

c212

JMP

L”223

JMP

1611

b‘12’27

JMP

1612

4M4?

NOSTAT,

1613

JMP

/ADORESS

JMP

743%

SiL

1616

azpm

JMP

.+?

1617

“233

JMP

TTUER

162%

4951

JMS

1671
16??

L241

JMP

Egmw

JMP

T3651B
T§681A

1623

4M2O

L624

SR1

DEFINE

/SCOPE

ACTION

EXECUTED

SFT)

(SR1

REPEAT?

/NO

/YES
/WAS

THE

LINK

RESET?

/NO

/YES

9R?

/NU,

/IKSTRUCTION FOLLOWING
JMS Z SRO
SKIRFR.
JMP NOSTAT
HLT
FRTTnl.
JMP T§651A

L625

“21?
74M?

1626

k2W?!

1627

402%

165m

“212

JMP

1661

74M?

ERTTOQ.

1652

H2mm

JMP

1633

AOPU

TTUER,

1654

52PM

1655

74w?

SKIPFR-S
HLT
ERTTn3,

1656

RQMM

JMP

1637

L212

UKJMPl.

JMP

164M

“223

FRJMPl.

JMP

/Tu0

INSTRUCTIONS
JMS Z
TTIEP,

64UO

WAS

ENTER
/YES,
NOT

/VERIEY REPEAT?
NEXT TEST
REPEAT T8681A

(SR?

SET)

EXECUTED
/HALT

ERROR?

(SRM

SET)

/NO

/REPEAT

FOLLOWING
SRO

NOSIAT

64EO

/HALT
TEST

WERE

NOT

ImcoRREcT

EXECUTED
/HALT

681

SKIP

ERROR?

ENABLE

(SRw

SET)

/NO
HLT

/HALT

TSfiblA
WIT

BUT

INSTRUCTION SHOULD
'
/[)ON T EXECUTE
/OON'T EXECUTE
JMS

“79%

681

/THIS

.+2
T8661A

1614

INSTRUCTIONS

LINK

64mm

NOSTAT
SKIPER
TTIFP

1615

/LINK

64OM)

CLA

16V“

/REPEAT

WAS

IOT

64mm

INTERPRETED

IOT

54m2

TEST

RESET
Z SRO

JMS

/HALT

ERROR?

(SRO

SET)

JMP

T8681A

/REPEAT

NOSTAT
SKIPER

/HALT
TEST

IOT

6400

INTERPRETEO

IOT

64%4

MAINDEC-OS-D7IA-LA
/T$5R1H
I641

75Qfl

TSRSIR.

L64?

r4V4

TTO

TEST,

TTD

CLA

CLL

PART

(64D4),

1643

714%

DCA

STURAC

I644

Am4?

INS

SAT

1645

L‘247

JMP

.+?

NOT

TSfiblR

/STURE

1646

k241

JWP

743W

SEL

16"“

“26W

JMP

LNOT?

1061

114%

TAD

L652

75%”

SNA

L653

Lgcic;

JMP

.+?

I6D4

”.7255

JNP

ACRSET

I635

4M51

RTINXT,

(bfi6

8272

JMP

L677

C24.1

JMD

LOCO

4M?w

LNCTz.

1601

k“2‘66

JMP

/YES;

JMS

114M

I603
T6h4

74M2
5241

1665

AOQM

ACMSFT.

L666

ngg

JMP

PTTNXT
2

LINK

NON

EXAMINE

/SKIP

/LINK

BIT

AND

/HALT

T3681R

/REPEAT
TO

SFT

JMS

TSSBIC.

I673

13?5

TAD

I674

6404

TTO

1675

314%

DCA

STORAC

I676

404?

JMS

SR1

16/7

R3W1

JMP

.+?

/NO

17AM

927?

JMP

TSRSJC

I741

7430

SiL

/YES
/IS LINK

L7W2

L312

AMP

LRDTFR

/NO

K317

L7Ifl

“3?7

L711

R27?

PART

OK;

VERIFY

REPEAT?

CONTENTS

ERROR?

(8RD

SET)

/AC FOLLOWING TTO
TTO TEST, PART 1

/HALT

739fl

4851

SHIFTED

EXECUTION

ERROR?

(SRO

SET)

/NO

36/2

L7M6

WAS

8RD

JAR

17d7

(1)

ONE.

L‘241

SiA

ACm

ACM

DISPLAY

I671

744M

ZERO?

/HALT

TAD

L7fl5

SET)

/NO

EPTTUS.

TAD
TAO

8RD

114“

1140

(SR1

RESET.

7492

1326

REPEAT?

/TEST

Lélfl

L743

RFCISTE”

TEST

SR2

1657

I704

RESET

/NO, ENTER TEST
/REPEAT PART 1

WAS NOT
JMS z

L602

STURAC
HLT

/HALT

TSAHIR
—

THIS

/N0

pTINXT
TAU ? STORAC
HLT
ERTTU4,

/TS681C

SELECTION

LINE

AFFECT

IINC

/YES

TSARJC
TSCRIR

WAS

LINK

/SCOPF

STDRAC

RIT

TRE

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/LINC

{FRO
I

AC.

/N0

1647

/AC@

CHECK

/CONTENTS
/SHOULD

JMP

1
/w

CML

AND

DISPLAY

CONTENTS OF
/FOLLONING TTO

/REPEAT

TTD

TEST.
CLL

CLA

PART

CHECK

CML

TTO
LINC

C4DA]

/STORE

LINK

AND

RAR

ACM

AND

AC11

RAR

/SCOPE

STORAC

DISABLE

REPEAT?

(SR1

SET)

RESET?

/YES

M2MAM

JMP SHFIER
PT2NXT,
JMS
JMP TSRSID
JMP TSAHJC

ROT.

LINK
/1

PART

TEST,

EXECUTION

/EXECUTION

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TTO?

EOOAL

2000

AFTER

/NO

SR2

/VER1EY
/NO.

ENTER TEST PART
/YES. REPEAT PART 2

REPEAT?

(SR2

SET)

(SR;

MAINDEC-OB-D7TA-LA
4M?@

LRnTpR,

i713

l53017

JMP

RTPNXT

1714

1140
74%?

TAD

1715

ERTTOb,

1716

527?

JMP

1717

4O?”

17?O

5307

DISABLED

NOT

ROTATE

/LINK

171?

JMS

STORAC
HLT

/HALT

/REPEAT

/RAR NOT EXECUTED
SHETFR,
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JMP PTQNXT

1721

7]?”

114M

TAD

17?}

7402

ERTTO7,

L724

5272

JMP

(SRO

SET)

/N0

TSSBlC

1722

ERROR?

/HALT

SRO

PART

AND

DISPLAY

TEST

RESULTS

CORRECTLY

/HALT

SR%

ERROR?

(SRO

SET)

/N0

ELL
¥

STORAC

/HALT

HLT

/REPEAT

TSfidJC

1725

4%“1

C4¢MT.

4mw1

L726

fiflflfl

Mzwmw.

~2MOO

1787

73mm

/T5681
TSRBlO,

1750

136?

TAD

i731

6424

TTO

1732

314%

UCA

STORAC

RR1

TTO

TEST.
CLA

PART

AND

DISPLAY

TEST

RESULTS

CLL

C525?

/TEST
/STORE

4242

JMS

L754

5336

.+2

/NO

1735

5327

TS68JD

/YES

L766

743m

JMP
JMP
RZL

1757

R347

JMP

FRFML

1740

114m

TAn

1741
L742

1363

TAO

M2525

744%

92A

STORAC

/LINK

LINK

1743

R354

3MP

4m51

PT3NXT,

1745

8764

JMP

1746

5327

JMP

1747

492m

FRCML,

1752

5344

JMP

i751

114%

ERTTOB.

1752

7472

HLT

1763

5327

JMP

1764

4GPO

L755

L"I344

1750

71VO

1757

114M

l7nM

740?

1761

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