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MAINDEC-08-D1L0

December 1968

20 pages

Original

0.6MB

Document:	Basic PDP-8, 8/I Memory Checkerboard
Order Number:	MAINDEC-08-D1L0
Revision:
Pages:	20
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/maindec-08-d1l0/maindec-08-d1l0-d.pdf

OCR Text

IDENTIFICATION
Product Code:

MAINDEC—OB—D 1 L0

Product Name:-

Basic PDP-B,

Date Created:

June 10,

Maintainer:

Diagnostics Group

Author:

i8/I Memory Checkerboard

1968

W. Richardson

ABSTRACT

The PDP—8, 8/1 MemoryCheckerboard diagnostic tests memory for core failure on halfselected lines under worst case conditions.

REQUIREMENTS

2 .l

Eguipment

Itsuse is intended for basic 4K memory systems.

A standard PDP-8 or 8/1.

2 2

Storage

There are two versions of this MAINDEC.

The Low End program occupies locations 0005

through 0l50 octal, and tests memory from l5l through 7700 octal

The High End program occupies locations 7430 to 7573 octal , and tests memory from 0000
to

7400 octal

2.3

Preliminary Programs
The RIM loader must be in locations 7756 through 7776 octal

LOADING PROCEDURE

3.
_

3. 1

Method
Load the program with the RIM loader.

remove

a .

Turn off the Teletype reader.

Set the SWITCH REGISTER to 7756.

Press LOAD ADDRESS, and then START.

Place the program tape in the reader and turn on the reader.

When the program has been loaded, stop the computer, turn off the reader, and

the tape.

4..

STARTING PROCEDURE

4 l

Starting Addresses

0005 Low End Checkerboard
7430 High End Checkerboard

Control Switch Settings

4.2

One of the four possible patterns that can be written in memory is obtainable by each of
the following SR

settingsi
,

0100

This setting is ued for the standard PDP—8 core unit.

This setting is used for the standard PDP-8/I core unit.

.0000

0001

}

These are for special core units from other suppliers.

Operator Action

4.3

With the program in memory, set the SWITCH REGISTER to the starting address, 0005 for

Low End or 7430 for High End.
Press LOAD ADDRESS

Set the SWITCH REGISTER to one of the four settings given in Paragraph 4.2 to obtain

the correct pattern.

For most PDP—8's, this will be 0l00.

For most PDP-8/I's, the setting will be OIOI.

Press START.

The program will run until an error is detected, or stopped by the operator.

OPERATING PROCEDURE

5.l

Operational Switch Settings
See Paragraph 4.2

5.2

’

Subroutine Abstracts

The program writes the selected pattern into the area of memory to be tested.
The contents of each word are then read, complemented, and written back into the same

location, until the contents of the entire area have been complemented. This procedure is repeated
'

l4 times before the contents of each word is checked for incorrect bits.
Error checking begins by reading a location and checking for incorrect bits

The contents are complemented, written back into the same location, and rechecked for
incorrect bits.

The original

contents

are

returned to the

location, and the next sequential location is then

checked.
.

After all of memory is tested, the program writes the complement of the pattern and proceeds
to

check as before

Operator Action

5 .3

See Paragraph 4.3

ERRORS

Any location containing an incorrect bit will Create an error halt when detected by the
program.

The contents of a given memory-location should always be 0000 or 7777.

Anything other

than 0000 or 7777 will result in an error halt.

Error Halts and Description

6.1

Two halts are provided For each error, and are described below

for each halt; the first is For the Low End

C(MA)

199.

0] 24

7546

Two addresses are given

Test, and the second For the High End Test.
Description.
A memory location does not contain 7777 or 0000.

The AC diSplays the contents of the location in
error.

.0127

ElA

755i

6 2

The AC diSplays the address of the location in
error.

Error Recovery

Operator Action

Tag
El

Record the C(AC).

Press CONTINUE to reach

the-next halt.
ElA.

Record the C(AC).

Press CONTINUE to resume

testing with the next sequential memory location.

7. l

RESTRICTIONS

Starting Restrictions
None

7 2
.

Operating Restrictions
None

MISCELLANEOUS

8. I

Execution Time
The time to write and test any pattern and its complement is approximately 3 seconds.

PROGRAM DESCRIPTION
In a standard core plane,

given core is selected when the combined currents of the x- and

ywselection lines produce a magneto motive Force which exceeds the threshold for reversing the flux
direction of the core

This occurs at the intersection of the activated selection lines.

which are threaded onto the activated lines will be slightly disturbed.

Under

All other cores

marginal voltage con-

ditions, such halt—selected cores might also reverse polarity if their states are properly established by
the pattern which the Checkerboard Test writes into memory.

When a selected core is in the I state, the read current will cause it to reverse polarity
and become 0.

When the core is in the 0 state, the write current will cause it to become I.

Thus,

the possibility of a reading error is greatest when all the halt-selected cores are in the I state; a

writing error is most probable when ail the hali-seiected cores are in the 0 state

It a haiiwselected core changes polarity, the error wili be detected when the memory

For a reading error, the contents of that core
/

will appear as a O in a tield oi I‘s, and vice verse For a writing error.

Every Checkerboard Test pattern consists ei alternating pairs of memory cells; one pair
containing 7777's the other containing 0000's.

Since memory manufacturers wire their core stacks

in different ways, the same pattern of alternations cannot be used for every type of core, and still allow
a

"worst case”

condition, that is, one in which all halt-«selected cards undergo the greatest possible

disturbance which can occur when testing memory.

The Following pattern is used For the Ferroxcube

memories with which most PDP-8's are provided.

x-axis

(MAO_5)

A O

I
.

y-axis (MA6_ I 1)

Since the y-axis selection lines are conditioned by the low—order six bits of the memory
address register (MA

6—l T

), and the x—axis lines by the high-order bits (MA 0-5)

’

the above array is

interpreted as follows: (x- and y-axis should be interpreted as shown above).
Positions on the x-axis represent consecutive locations in memory from 00 through 77.
.

Positions on the y-axis represent consecutive

location 0000.

This-position contains

at address 0000 are

1008's. Thus, the lower left

corner

represents

0, which means that the contents of the entire memOry cell

0; likewise, the contents of memory cell 020i are l's or 7777. This is determined

by reading the third row up on the ‘x-axis, and across one position on the y—axis.
The pattern in memory appears as follows:

Address
0000

Contents
0000

000l

0000
‘

0002

7777

0003

7777

30004

0005
.

0006

0000
0000

‘

7777

0007

The pattern matrix, shows that after

7777

778 registers, the pattern will

reverse

Address

Contents

0076

7777

0077
0] 00

7777
'

7777

0 l OT

and so on through memory.

itself, thus:

7777

0T 02

0000

CT 03

0000

0 l 04

7777

0 l 05

7777

0 l 06

0000

CT 07

0000

The pattern reverses every

l008 registers.

The patterns generated by the other three switch register settings are defined by the following

pattern matrices

Setting

Pattern Matrix

010]

x-axis

.
.

y-axrs

Setting

‘

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0000

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0001

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