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MAINDEC-08-D1D

December 1965

12 pages

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Document:	maindec-08-d1da-d
Order Number:	MAINDEC-08-D1D
Revision:
Pages:	12
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IDENTIFICAT.ION

-``

Product code:

MAINDEC 08-DIDA-D

Product Name:

Extended Memory Checkerboard - Pal.t 2

Date created:

September 8,1965

Maintainer:

Diagnostic Group

Previouscode:

MAINDEC 820-2

Maindec 08-D-DI DA-D
Page 1
1.

ABSTRACT

MAINDEC 08-DI DA-D is a preliminary test for core memory failures on halif-selected lines
under worst-case conditions of reading and writing . It is used to test memory module X while running

the program in memory module Y.

This is applicable for test of Type 184 Memory Modules and MMO8

Memory Modules.
MAINDEC 08-DICA-D w:ll also tea+ the control pc)rticin of the Extended Memory Type 138
or Extended Memory Type 185 .
2.

REQUIREMENTS

Storage
The program occupies registers 00008 -01118 and tests memory from 00008 -77768 .
The RIM Loader must be in registers 77568 -77768 .

Subprograms and/or Subroutines
High RIM Loader, Binary Loader Digital-8-2-U-RIM

Equipment

Standard PDP-8 and. Extended Memory Module Type 183.
3.

USAGE

u3.1

If the Binary Loader is in memory, go to the Ext.ended Memory Checkerboard Test..
wise, the RIM Loader and/or the Binary Loader must be loaded into memory.

Other-

The Extended Memory Checkerboard Test may now be loaded as follows:

i::s!7L73AinAhDeD:?S15ck:yREGISTER
Place obiect tape in the ASR 33
Press START key on the operator console
Engage recider

3.2

Switch Settings

Starting address:

00008 DF(X), IF(X).

Program Control Settings - One of four possible patterns that can be written is obtainable by
each of the following SR settings.
This setting is used for the standard PDP-8 unit.

These are used for special core units from other supplies.

(Reference section 5 .2 .)
This setting is used for Type 185,186 or MMO8 Memories

of the PDP-8 .

Maindec O8-DI DA-D
Page 2

3.3

Start u
With the program in the desired memory field set the following:

+:.emLo°r;dc:::::;;n°g°:h°e8:b|e°catdptrhoegrdaaj:i:e!dandinsTructionfieldofthe
b.

Set the instruction CDF (62N1) to the fi.eld to be rested :n +he SWITCH

Press DEPOSIT.

Repeat step a.

Reference Program Control Settings (section 3.2).

Press START.

Errors in Usage

3.4

The contents of a given memory cell should be either 7777 or 0000.
becomes a 0, or vice verso. The following pair of stops occurs for each error:

C(MA)

Error

0071

Memory cell does not con+ain 7777 or 0000.
displays cont.ents of cell in error.

0074

EIA

AC contains address of cell causing previous error stop.

Recover

Cause of Error

from Such Errors

Error

An error occurs if a 1

Recovery procedure

Record the c(AC).

Press CONTINUE to reach the next halt.

EIA

Record the c(AC).

Press CONTINUE to resume testing.

RESTRICTIONS

This program is only a preliminary test and should only be used to simplify memory adiust-

ments and maintenance procedures.
Maindec 802* should be loaded iht.o the memory module under test for a 'final test. (Reference

Maindec 802* for usage)
5.

DESCRIPTION

5.1

Discussion

* See Appendix

Maindec 08-DI DA-D
Page 3

In a standard core plane, a given col.e is selected when the combinecl voltages of the xand y-selection lines exceed the thl.eshold vol+age for reversing the polarity of the core. This occurs at
the intersection of the activated selection lines. However, all other cores which are threaded onto the
activated lines will be slightly disturbed. Under marginal voltage conditions, such half-selected cores
may also reverse polarity if their states are properly established by the pattern which the Checkerboard
Test writes into memory.

When a selected core is in the I state, the read current causes it to reverse polarity and
become 0.

When the col.e is in the 0 state, +he write current causes :+ +a become I.

Thus, +he possibili+y

of a reading error is greatest when all the half-selected cores are in the 1 state; a writing error is most probable when all the half-selected cores are in 0 state.

If a half-selected core changes polarity, the error is detected when the memory register containing that core is tested by the progi.am. For a reading error, the contents of that core will appear as a
0 in a field of I 's, and vice versa for a writing error.
Every Checkerboard Test pattern consists of alternating pairs of memory cells, one pair containing 7777's, the other containing OOOO's. Since many manufacturers wire their core stacks in different

ways, the same pattern of alternations cannot be used for every type of core and still allow a worst-case
condition; that is, one in which all half-selected cores undergo the greatest possible disturbance which
can occur when testing memory. The following pat+ern is used for the Ferroxcube memoriles with which
most PDP-8`s are provided.

x-axis

0011

(MAo-5)

1100

0011

y.axis (MA6.1 1)
Since the y-axis selection lines are conditioned by 1.he low-order six bits of the memory

:edrdprreestse:e8:S:::,!#£6-(*|):nadn;.tahxee::::|S[:i::Sj:¥e:::e::8ha-s°:#i:§b!#-5)rtheabovearrayisinPositions on the x-axis represent consecutive locations in memory from 00-77.

Pos:lions on the y-axis represent consecutive 1008's. Thus, the lower left corner represen+s
location 0000. This position cont.ains a 0, which means that the contents of the entire memory cell at
address 0000 are O's. Likewise, the contents of memory cell 0201 are 1 's or 7777; this is determined by
reading the third row up on the x-axis, and across one position on the y-axis.
The pattern in memory appears as follows:

Address

Contents

Maindec 08-DI DA-D
Page 4

lt can be seen from the pattern matrix, that after 778 registers, the pattern reverses itself,
thus:
Acldress

Contents

0076

7777
7777
7777
7777

0077
0100
0101

0000
0000

0102
0103

7777
7777

0104
0105

0000
0000

0106

0107
®®

And so on through memory.

5.2

The pattern reverses every 1008 registers.

Pattern Generation

The patterns generated by the other three switch register settings are defined by the
following pattern matrices.

SR setting

0000

x-axls

Pattern Matrix
100

100
011

011

0001

x-axis

001
001

Ilo
Ilo

0021

x-axi s

110

001

Ilo

Maindec 08-DI DA-D
Page 5
SR se+ting

x-axis
0101

Pattern Matrix
TOOT

0TIO

1001

METHODS

6.I

Discussion

The program writes the pattern into the area of memory to be rested.
word as follows:

11 then fesl.s each

The contents of the word are checked for incorrect bits.
The content.s are complemented, deposited in the same register, and ret.ested for inc6rrect
bits .

The original contents are ref.urned to the register, and the next one is checked.
After all memory is +esled, +he pi.ogrcim wri+es +he complemen+ of +he pa++ern and proceeds

+a check as before.

In this way, every core is rested for errors that might occur when it is read and when

information is wril't.en into it..

EXECUTION TIME

2 seconds

PROGRAM LISTING

/MAINDEC 08-DI DA-D
/EXTENDED MEMORY CHECKERBOARD-PART 2

*8
8
CLL

CML IAC

DCA

COM

LAS
TAB

MUD

DCA

PAT

TAD

MUD

DCA

/2
/10
/COMPLEiMENT

THE

PATTERN

Ma:ndec 08-DI DA-D
Page 6

/1©©

/TEST

FOR

FINAL ADDRESS

/ 2 8 Ej

8
TAD

NOT

TAD

HOT

/Y I.INE PRESETS X
/T0 SNA 0R SZA

LINE

DCAX

TAD

PAT

AND

DOT

CMA

21®6

21©5

©©42

11©6

¢®43

8®44

765©

®845

5©17

©©46

5831

/STORE PATTERN
/WORD

WHEN

AND RECOMPLEMENT

CHECKTNG

/77

/CHECK

PATTEF3N

/ERROR

CORE

/COMPLEMENT

/IN

THE

WORD

CORE

/TEST

COMPLEMENT

WORD

/ERROR
TAD

WED

CLL
JMP

STD-i

/ERROR: AC CONTAINS INCORRECT WORD

/AC CONTAINS
/FiEGISTER IN

JMP

ADDRESS
ERROR

CC2

•.-I

Maindec 08-DI DA-D

Page 7

®@77

/CONSTANTS

E " Z]m
rna " H H

81©2
©1©3
©1®4

81©5

8©@©

FAT,

©©8©

SA,

®®©©

COM,

®110

©®©©

RD,

©®®8

MUD,

/VARIABLES

Maindec 08-DI DA-D
Page 8

APPENDIX

MAINDEC 802 -Memory Checkerboard Test

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