Digital PDFs

DEC-LB-H8EMM-B-D

December 1973

211 pages

Original

15MB

Document:	LAB8E Maintenance Manual
Order Number:	DEC-LB-H8EMM-B-D
Revision:
Pages:	211
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/dec-lb-h8emm/dec-lb-h8emm-b-d.pdf

OCR Text

0..

M333;rdmfi's‘é'éthué’éfli'atm"

manual:

LAB-8/E MAINTENANCE MANUAL

laboratory data products

Dma-hw-mmng-w-_u

_.>w..m\m

_<_>_Z._._mZ>ZOm _<_>ZC>_I

Ist Edition, March 1972
2nd Printing (Rev) August 1973

The material in this manual is for informational purposes and is
without notice.

subject

change

The following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

CONTENTS

Page
CHAPTER 1

INTRODUCTION

1.1

Purpose of Manual

1.21

System Features

1-1

1.2.1

Analog-to-Digital Converter (AD8—EA)

1-3

1.2.2

Analog Preamplifier and Multiplexer (AM8—EA)

1-3

1.2.3

Point-Plot Display Control (VC8—E)

1-3

1.2.4

Buffered Digital l/O (D R8-EA)

1-3

1.2.5

Real-Time Programmable Clock (DK8-EP)

1-3

1.2.6

Analog Input Panels (AM8-ED and AM8-EC)

1-4

1.2.7

Real-Time Programmable Clock Input Panel (DK8-EF)

1-4

1.2.8

Digital l/O Panel (D R8-EB)

1-4

1.3

Physical Description

1-7

1.4

Documentation

1-7

CHAPTER 2

INSTALLATION

2.1

Site Considerations

2—1

2.1.1

Power Source

2-2

2.2

l/O Panels and Cabling Requirements

2-2

2.2.1

A/D Converter Connections

2-2

2.2.2

Buffered Digital l/O Connections

2—4

2.2.3

Real-Time Programmable Clock Input Connections

2-5

2.2.4

Point-Plot Display (VC8-E) Control Connections

245

2.3

Fire And Safety Precautions

2-6

2.4

Installation Procedures

2-6

2.4.1

Unpacking and inspection

2-6

2.4.2

Installation Procedure

2-12

2.5

Acceptance Test

2-18

2.5.1

Central Processor Acceptance Test

2-19

2.5.2

Analog-to-Digital Converter (ADB-EA) and Analog Multiplexer
(AM8—EA) Acceptance Test

2-19

2.5.2.1

Acceptance Test

2-20

2.5.3

Point-Plot Display Control (VC8-E) Acceptance Test

2-24

2.5.3.1

Control

2-24

2.5.3.2

VC8-E Ramp Slewing Test

2-25

2.5.3.3

VC8-E Display Test

2-25

Logic Acceptance Test

2.5.4

Real-Time Clock (DK8—EP and DK8-ES) Acceptance Test

2-28

2.5.4.1

Acceptance Tests

2-28

2.5.4.2

DK8-ES Acceptance Test

2-29

2.5.5

Buffered Digital I/O (D R8-EA) Acceptance Tests

2-30

2.5.5.1

Visual Inspection and Test Setup

2-31

2.5.5.2

DR8-EA Acceptance Test Without DR8—EB Panel

2-31

5247
P?
77'“;

few

602

”0d?

CONTENTS (Cont)

Page
CHAPTER 3

OPERATING PROCEDURES

3.1

Computer Operation

3.1.1

Controls and Indicators

3-1

3.1.2

Keyboard Operation

3-5

3-1

3.1.3

Printer Operation

3-6

3.1.4

Paper-Tape Reader Operation

3-6

3.1.5

Operating Procedures

3-6

3.1.6

Manual Data Storage and Modification

3-6

3.1.6.1

Power for Manual Operation

3-6

3.1.6.2

Memory Addressing for Manual Operation

3-6

3.1.6.3

Manual Data Input to Addressed Memory Location

3-6

3.1.6.4

Checking the Contents of Any Address In Core Memory

3-7

3.1.7

Loading Data Under Program Control

3-7

3.1.7.1

Initializing the System

3-7

3-8

3.1.8

Program Loading Operation

3.1.9

Loaders

3-9

3.1.9.1

Read-In-Mode (RIM) Loader

3-9

3.1.9.2

Binary (BIN) Loader

3-1 1

3.1.10

Off-Line Teletype Operation

3-1 2

3.2

Display System Operating Procedures

3-1 3

3.2.1

VR14 Display Operation

3-1 3

3.2.2

Guidelines for VC8-E Interfacing for Oscilloscopes and XY Plotters

3-1 5

3.2.2.1

lntensification Pulse

3-1 5

3.2.2.2

X and Y Outputs

3-1 5

3.2.2.3

Drive Capabilities

3-1 5

3.2.2.4

External Controls

3-1 5

3.2.2.5

Ground Loops

3-1 6

3.2.2.6

VC8-E Restrictions

3-1 6

CHAPTER 4

PRINCIPLES OF OPERATION
Section 1

System Operation
4.1

Introduction

4-3

4.1.1

Analog Data Input to the A/D Converter

4-4

4.1.2

A/D Converter (ADB-EA)

4-4

4.1.3

Buffered Digital I/O (D R8-EA)

4-4

4.1.4

Real-Time Programmable Clock (DK8-EP)

4-6

4.1.5

Point-Plot Display Control (VC8—E)

4-6

4.1.6

33 ASR Teletype

4-9

4.1.7

HQ Power Supply

4-9

CONTENTS (Cont)

Page
Section 2

Analog-To-Digital Converter (AD8-EA)
4.2

introduction

4-1 1

4.2.1

A/D Converter Block Diagram

4-14

4.2.2

A/D Converter Detailed Logic

4-17

4.2.2.1

Device and Operation Select Logic

4—1 7

4.2.2.2

External A/D START and Time Pulse Logic

4-17

4.2.2.3

interrupt, Skip, and Control

4-17

4.2.3

Status Register

4-21

4.2.4

BUSY Flip-Flop

4-21

4.2.5

MUX Register Logic

4-21

4.2.6

Enable Register

4-23

4.2.7

Analog Buffer and Sample and Hold Circuits

4—23

Logic

4.2.8

A/D Converter Internal Clock

4—26

4.2.9

Analog Switches

4—26

4.2.10

Comparator

4-31

4.2.11

A/D Buffer and Shift Register

4-31

4.2.12

Positive and Negative References

4-33

Section 3

Analog Preamplifier and Multiplexer
4.3

Introduction

4-35

4.3.1

Analog Preamplifier and Multiplexer Expander Block Diagram

4—35

4.3.2

Analog Preamplifier and Multiplexer Expander Detailed Logic

4—36

4.3.2.1

Differential Amplifiers

4-36

4.3.2.2

Channel Decoder and Analog Switches

4-37

4.3.2.3

Reference Voltages

4—39

4.3.2.4

Optional Multiplexer Configurations

4-39

Section 4

Point-Plot Display Control (VC8-E)
4.4

Introduction

4-43

4.4.1

Functional Block Diagram Description

4-46

4.4.2

Point-Plot Display Control Detailed Logic

4-49

4.4.2.1

Device and Operaiton Select Logic

4-49

4.4.2.2

Enable/Status Register

4-49

4.4.2.2.1

DONE Logic

4-49

4.4.2.2.2

interrupt Enable Logic

4-51

4.4.2.2.3

Channel Select Logic

4-51

4.4.2.3

Intensity Pulse Generation

4-51

4.4.2.4

Data Gates

4-51

4.4.2.5

Holding Registers

4-51

4.4.2.6

Analog Switches and Summing Amplifier

4-53

4.4.2.7

Positive Reference Source

4-54

CONTENTS (Cont)

Page
Section 5
Buffered Digital l/O (DR8-EA)

4-57

4.5

Introduction

4.5.1

Buffered Digital I/O Functional Block Diagram

4-57

4.5.2

Buffered Digital I/O Detailed

4-59

4.5.2.1

Device Select and Operation Decoder

4—59

4.5.2.2

Interrupt and Skip Logic

4-59

4.5.2.3

Input Register and Control Logic

4-59

4.5.2.4

Output Register and Control Logic

4-61

4.5.2.5

AC Bus Register

4-64

Logic

Section 6
Real-Time Programmable Clock (DK8-EP)
4.6

4-6 5

Introduction

4.6.1

Block Diagram Discussion

4-66

4.6.2

Detailed Logic

4-7 1

4.6.2.1

IOT Decoder Logic

4-7 1

4.6.2.2

Clock Enable Register Logic

4-7 1

4.6.2.3

Clock Rate Select Logic

4-7 1

4.6.2.4

Load Buffer Register Logic

4-74

4.6.2.5

Clock Buffer/Clock Counter Logic

4-7 5

4.6.2.6

Overflow Flip-Flop Logic

4-80

4.6.2.7

Interrupt/Skip Logic

4-80

4.6.2.8

Input/Overflow Status Logic

4-82

4.6.2.9

Schmitt Trigger Logic

4-84

Section 7

High Quality Power Supply
4.7

Introduction

4-87

4.7.1

High Quality Power Supply Operation

4-87

4.7.1.1

Regulator Circuitry

4-87

4.7.1.2

Current—Limiting Circuitry

4-89

CHAPTER 5

MAINTENANCE
Section 1

Preparation for Maintenance and Maintenance Requirements
5:1

Equipment

5-3

5.1.1

Programs

5-4

5.1.1.1

Display Line on VR14 or User Oscilloscope

5—4

5.1.1.2

Display Converted Value in AC (AD8—EA only or channel 0 of AM8-EA)

5-4

5.1.1.3

Display Converted Value in MO with AM8-EA

5-5

CONTENTS (Cont)

Page
5.1.1.4

Display Converted Value of A/D on VR14

5-5

5.1.1.5

Start A/D Converter with Real—Time Clock

5-6

5.1.2

Preventive Maintenance Inspections

5-6

5.1.3

Scheduled Maintenance

5-7

5.1.3.1

Weekly Preventive Maintenance Schedule

5-8

Section 2
Corrective Maintenance
5.2

Maintenance Procedures

5-9

5.2.1

Preliminary Investigation

5-9

5.2.2

System Troubleshooting

5-9

5.2.3

Logic Troubleshooting

5-1 1

5.2.4

Circuit Troubleshooting

5-1 1

5.2.5

Repairs and Replacements

512

5.2.6

Validation Tests

5-15

5.2.7

Log Entry

5-1 5

5.2.8

CPU Troubleshooting

5-16

5.2.9

Memory Troubleshooting

5-1 7

5.2.9.1

Memory Resistance Checks

5-19

5.2.9.2

Memory Circuit Variables

5—20

5.2.9.2.1

Field Select Jumpers

5-21

5.2.9.2.2

Strobe Adjustment

5-21

5.29.2.3

Slice Level

5-21

5.29.2.4

XY Current Control (G227)

5-21

5.2.9.2.5

Temperature Tracking

5-21

52926

Inhibit Current

5-21

52.9.27

Strobe Setting Procedure

5-21

5.2.10

H724 Power Supply Troubleshooting Procedures

5-23

5.2.10.1

Overcurrent Protection

5-24

5.2.10.2

Hold-Up Time

5-24

5.2.10.3

Thermal Protection

5-24

5.2.10.4

Contact Protection

5-24

5.2.10.5

input Switching

5-24

5.2.10.6

POWER ON/OFF Switch Adjustment

5-24

5.2.10.7

Parallel Operation

5-24

5.2.10.8

Large Configuration

5-24

Section 3

Teletype Maintenance
5.3

Introduction

5-25

5.3.1

Special Tools

5-25

5.3.2

Programs

5-25

vii

CONTENTS (Cont)

Page
Section 4

System Calibration
5.4

Calibration of the LAB-8/E Options

5-27

5.4.1

A/D Converter (ADS-EA) Calibration Procedure

5-27

5.4.1.1

Minor Calibration

5-27

5.4.1.2

Major Calibration

5-28

5.4.2

Common Mode Rejection (CM R) Calibration

5-29

5.4.3

Calibration of the Point-Plot Display Control (VC8-E)

Using VR14 or Tektronix 602 Display

5—29

5.4.4

VC8—E Calibration Procedure Without a VR14 or VR03

5-31

5.4.5

Analog Preamplifier and Multiplexer (AM8—EA) Calibration Procedure

5-32

5.4.6

VR14 Calibration

533

5.4.7

Calibration of the Tektronix 602 Using the VCB-E

5-34

Section 5
Preventive Maintenance Procedures
5.5

Preventive Maintenance

5-35

5.5.1

Weekly Tasks

5-35

5.5.2

Preventive Maintenance Tasks

5-35

Section 6
Corrective Maintenance
5.6

Corrective Maintenance Procedures

5-37

Section 7

Special Troubleshooting Procedures
5.7

Test Clock (M499)

CHAPTER 6

LAB-8/E SYSTEM SPARE PARTS

6.1

Introduction

6-1

6.2

LAB-8/E Central Processor (PDP-8/E and 33 ASR Teletype Spare Parts)

6-1

6.3

Basic LAB~8/E System Spare Parts

6-1

APPENDIX A

IC CIRCUIT DESCRIPTION

A.1

SN 74193 IC

A-1

DEC 17090 IC

A-1

DEC 7475 IC

A-4

A.4

DEC 749010

DEC 7470 IC

A-4

DEC 74197 IC

A-4

APPENDIX B

LAB-8/E MODULE JUMPER REQUIREMENTS

5-39

viii

ILLUSTRATIONS
Title

Figure No.

Page

1-1

LAB-8/E Basic System

1-2

LAB-8/E Rack-Mounted Version

1-8

2-1

Single-Ended Measurement Connection

2-2

Differential Input Measurement Connection

2-2

2-3

AM8—ED Analog Input Panel

2-3

2-4

AM8-EC Analog Input Panel, Front and Rear View

2-3

2—5

Front View of DB-255 Connector and Telephone Plug

2-3

2-6

Edge Connector Installation (top view)

2-1 5

2-7

Analog Inputs for Accuracy Check

2-20

1-2

2-8

Negative Input Checkout

2-22

2-9

Oscilloscope Display for Ramp Test

2-25

3-1

Programmer’s Console

3-1

3—2

Teletype Model 33 ASR Console

3-2

3-3

Teletype Keyboard

3-5

3-4

Loading Data Under Program Control

3-8

3-5

Loading Programs with Mass Storage Devices

3-9

3-6

Loading the RIM Loader

3-10

3-7

Checking the RIM Loader

3-10

3-8

Loading the BIN Loader

3-1 1

3-9

Loading a Binary Tape Using BIN

3-12

3-10

VR14 Display Oscilloscope

3-13

4-1

LAB-8/E Block Diagram

4-3

4—2

A/D Converter Flow Chart

4-5

4-3

Buffered Digital I/O Flow Chart

4-6

4-4

Real-Time Programmable Clock Flow Chart

4-7

4-5

Point-Plot Display Control Flow Chart

4-8

4-6

Analog-to-Digital Converter Block Diagram

4—1 1

4-7

Enable/Status Register Contents

4-12

4-8

A/D Converter Functional Block Diagram

4-14

4-9

A/D Buffer and Switch Logic

4-1 7

4-10

Device and Operation Select Logic

4-18

4-1 1

Interrupt, Skip, and Control

4-19

Logic

4-12

Interrupt Timing Diagram

4-20

4-13

MUX Register Logic

4-22

4-14

Enable Register Logic

4-24

4-15

Analog Buffer and Sample and Hold Circuits

4-25

4-16

Signal at AA1 with a Slow Ramp Input to the A/D Converter

4-26

4-1 7

Analog-to-Digital Converter Internal Clock

4-27

4-1 8

Analog-to-Digital Converter Internal Timing Diagram

4-28

4-19

A/D Converter Shift Register and Data Buffer

4-29

4-20

Analog Switches

4—30

4-21

Comparator Circuits

4-31

4-22

A/D Buffer Signal

4-32

4-23

Summing Junction and Comparator Output Signals

4-33

ILLUSTRATIONS (Cont)

Figure No.

Title

Page

4—24

Signals at AA1 and Collector of 020 on the A841 Module

4-33

4-25

Positive and Negative References

4-34

4-26

Analog Preamplifier and Multiplexer Block Diagram

4-35

4—27

Analog Preamplifier and Multiplexer Expander Functional
Block Diagram

4-36

4-28

Differential Amplifier

4-37

4-29

Channel Decoder and Analog Switches

4-38

4-30

AM8-EA Reference Voltages

4-39

4-31

Point-Plot Display of Coordinate Data

4-43

4-32

Point-Plot Display Control Block Diagram

4-44

4-33

AC Input Data Format

4-44

4-34

Analog Switches and Summing Amplifier

4-45

4-35

One Analog Switch and Summing Amplifier

4-45

4-36

Device and Operation Select Logic

4-48

4-37

Enable/Status Register

4-50

4-38

Enable/Status Register Word Contents

4-51

4-39

DONE and Interrupt Logic

4-52

4-40

intensity Pulse Logic

4-53

4-41

Data Gates

4-54

4-42

X-Axis Holding Register

4-54

4-43

Analog Switches and Summing Amplifier

4-55

4-44

+5V Reference

4-55

4-45

Buffered Digital l/O Block Diagram

4-57

4-46

Device Select and Operation Decoder Logic

4-60

4-47

Interrupt and Skip Logic

4-61

448

lnput Buffer Register and

Logic

4-62

4-49

Output Register and Logic

4-63

4-50

AC Bus Register

4-63

4-51

DK8-EP Functional Block Diagram

4-67

4-52

lOT Decoder Logic

4—69

4-53

Clock Enable Register Logic

4-72

4-54

Clock Rate Select Logic

4-73

4-55

Load Buffer Register Logic

4-74

4-56

Load Buffer Register Timing

4—76

4-57

NOT LAST TRANSFER Logic

4-77

4-58

Clock Buffer/Clock Counter Logic

4-78

4-59

Clock Buffer/Clock Counter Control Signals

4-79

4—60

OVERF LOW Flip—Flop Logic

4-81

4—61

Interrupt/Skip Logic

4-82

4-62

Input/Overflow Status Logic

4-83

4-63

Schmitt Trigger Logic

4-84

4-64

DK8-EF Front Panel Schematic

4-85

4—65

High Quality Power Supply Schematic

4-88

ILLUSTRATIONS (Cont)
'

Figure No.
4-66

Title

Current Limiting Circuitry

Page
4-88

4-67

Regulator Circuitry

4-89

4-68

Power Mate (20885-8) HO Power Supply

4-90

4-69

Deltron (C13495) HQ Power Supply

4-91

5-1

System Troubleshooting Flow Chart

5-1 0

5-2

IC Location

5-1 3

5-3

IC Pin Location

5-1 3

5-4

Memory Troubleshooting Flowchart

5-1 8

5-5

Memory Waveforms

5-20

5-6

Setting of Strobe

5-22

5-7

AD8-EA Common Mode Rejection Calibration Connection

5-29

5-8

Teletype Signal Waveform and Bit Relationship for the Character U

5-38

A-1

74193 IC Logic Diagram

A-2

74193 IC Pin Location (Top View)

A-3

DEC 1709C IC Illustrations

A-3

A-4

DEC 7475 IC Illustrations

A-6

A-5

DEC 7490 IC Illustrations

A—7

A-6

DEC 7470 IC Illustrations

A-8

A-7

DEC 74197 IC Illustrations

A-9

TABLES
Table No.

Title

Page

1-1

LAB-8/E System Specifications

1-2

LAB-8/E Handbooks, User’s Manuals, Maintenance Manuals, and

Engineering Drawings

1-9

2-1

Summary of Installation Functions

2-1

2-2

AM8-ED and AM8-EC Analog Panel Pin Connections

2-3

Analog Connection Using 7008533 Cable

1-4

2-4

BC08J-X Connection and Bit Assignments

2—4

2-5

Connections for DR8—EB Panel Assembly

2-4

2-6

Real-Time Programmable Clock Connections

2-7

VCB-E Cable Connections

2-5

2-8

AD8-EA Accessory and Component List

2-7

2-9

AD8-ES Accessory and Component List

2-8

2-10

AM8-EA Accessory and Component List

2-8

2-1 1

AM8—EC Accessory and Component List

2-9

2-12

AM8—ED Accessory and Component List

2-9

2-13

DK8—EF Accessory and Component List

2-9

2-14

DK8-EP Accessory and Component List

2-9

2-15

DK8-ES Accessory and Component List

2-10

2—1 6

DR8-EA Accessory and Component List

2-10

2-17

DR8-EB Accessory and Component List

2-10

TABLES (Cont)
Table No.

Title

Page

2-1 8

DR8—EC Accessory and Component List

2-1 1

2-19

yC8-E Accessory and Component List

2-1 1

2-20

VM03 Accessory and Component List

2-1 2

2-21

Recommended LAB-8/E Module Installation Positions

2-1 2

2-22

High Quality Power Supply Parameters

2-14

2-23

Switch Requirements for VCB-E Modules

2-16

2-24

VM03 Tektronix 602 Modification Kit Parts List

2-1 7

2-25

LAB-8/ E Acceptance Test Diagnostics

2-19

2-26

A/ D Converter and Analog Preamplifier and Multiplexer Acceptance Test

2-20

2-27

Switching Points and Theoretical Voltage Readings

2-21

2-28

Theoretical Voltage and Reading in the AC

2-22

3-1

Programmer’s Console Control and Indicator Functions

3-2

Special Keyboard Functions

3-5

3-3

RIM Loader Programs

3-10

3-4

VR14 Input Voltages

3-13

3-5

VR14 Controls

3-14

3-6

Unit Top Panel Control Settings

3-14

4-1

Enable/Status Register

4-1 3

4-2

C-Line Logic Levels

4-20

4-3

MUX Register Contents and Look-Ahead Bits

4-23

4-4

Applied Voltages and Octal Equivalents

4-32

4-5

Resistors for Changing Input Configuration

4-40

4-6

AM8—EA Configuration Change Parts List

4-40

4-7

Point~PIot Display Control Enable/Status Register

4-46

IOT Device Code

4-59

4-9

DK8-EP IOT Instructions

4-68

4-1 0

Clock Enable Register Enable Signals

4—70

4-1 1

Frequencies Selected by Rate Enable Bits 3—5

4-70

4-1 2

Control Signals for Clock External and Internal Transfers

4—78

4-1 3

High Quality Power Supply Parameters and Specifications

4-87

4-14

Side Connector for H0 Power Input and Output

4-87

5-1

Maintenance Equipment

5-3

5-2

Processor Preventive Maintenance Schedule

(3 months or 500 hours)

5—7

5-3

Processor Troubleshooting

5-16

5-4

Memory Data Errors

——

Possible Causes

5—1 9

5-5

Memory Module Test Point Voltage Levels

5-19

5-6

Memory Circuit Variables

5-20

5-7

H724 Power Supply Parameters

5-23

5-8

Component Troubleshooting Aid for H724 Power Supply

5-23

5-9

POWER ON/OFF Switch Adjustment

5-24

5-1 0

Teletype Maintenance Tools

5-25

5-1 1

EDC Connection to A841 Module

5-28

xii

TABLES (Cont)
Title

Table No.

Page

EDC Voltage and AC Readings

5—28

5-13

Major Calibration Voltages and AC Readings

5-29

5-14

AM8-EA Calibration Connections

5-33

5-15

Gain and Bias Potentiometers

5-34

5-16

Connections of Teletype Cable

5-37

5-17

Teletype Cabling, Fusing, and Test Points

5-37

6—1

Analog-To-Digital Converter (ADS-EA) Recommended Spare Parts

6-1

6-2

Point-Plot Display Control (VC8—E) Spare Parts

6-2

6-3

Analog Preamplifier and Multiplexer Expander (AM8—EA)
Recommended Spare Parts

6-2

6-4

Buffered Digital I/O (D R8—EA) Recommended Spare Parts

6-2

5-12

6-5

Real—Time Programmable Clock (DK8-EP)

Recommended Spare Parts

6-3

xiii

CHAPTER 1

INTRODUCTION

1.1

PURPOSE OF MANUAL

This manual provides the user with the installation procedures, theory of operation, and maintenance procedures
necessary to install and operate the LAB-8/ E System manufactured by Digital Equipment Corporation.

The theory of operation and maintenance procedures for the LAB-8/ E processor are contained in the PDP-8/E
Maintenance Manual, Volume /.

When operating and performing maintenance on the LAB-8/ E, the user should

be familiar with Chapter 4 of the PDP-8/E manual. This manual deals with the options that have been added to

the PDP-8/E to form the LAB-8/E System.

Paragraph 1.4 contains a list of companion documents to this manual

and other documentation for the LAB-8/E.

1.2

SYSTEM FEATURES

The LAB-8/ E System performs arithmetic calculations, controls machintD operations, makes on-line measurements
of both analog and digital information, displays data on an oscilloscope, and stores large quantities of data for
future use and/or modification. The user may use control tapes provided by

Digital, or write his own programs

to shape the LAB-8/ E to his own needs and to perform sophisticated handling of analog or digital data. The

LAB-8/E is a truly sophisticated system allowing flexibility for the user in data acquisition and processing.
The LAB-8/E design enables the user to purchase the basic LAB-8/E and to add on options as requirements increase.

The basic system comprises the following:
A PDP-8/ E general purpose 12-bit digital computer with a basic 4096-w0rd memory and a 1.2-us

cycle time.

Teletype®, 10-bit l/O device with a paper-tape reader and punch.

A 33 ASR

A laboratory mounting panel with precision power supply for use with LAB-8/E peripherals.

d. A 10-bit Analog-to-Digital Converter with sample and hold circuitry and optional preamplifier
and multiplexer expander.
e.

A 10-bit Point-Plot Display Control for the graphical display of data on an oscilloscope.
A Real-Time Clock with five programmable ranges from 1 us per count to 10 ms per count, plus

three Schmitt triggers.

Expansion is easily accommodated through a two—way bus, called

OMNIBUS®, which all LAB-8/E modules

plug into directly or indirectly. Figure 1-1 shows the basic PDP-8/E and the options added, shown inside the
dotted lines, to form the basic LAB-8/ E. One OMNIBUS contains 20 non-dedicated slots that can contain up to

®Teletype is

registered trademark of Teletype Corporation.

OMNIBUS is a trademark of Digital Equipment Corporation.

1-1

I—
I

CARRY

ANALOG
INPUT PANEL

AM8-EC
OR

AMa— ED

ANAILOO

DRB-EB

MULTIPLEX
EXPANDER

OUTPUT
PANEL

AM8-EA (A232)

| 1 T
I AglAIéIOPA‘lr-O
I
Inn3
I
I
I

CONVERTER
“73‘“ (A841)
I

DATA

5
CL

g
E
8

g
<
0

SCHMITT
TRIGGER
DKB-EP

‘

(M863)

(M860)

(M518)

0)
.1

(”II
_l

<25“:

E
8

0 J

25%
o

5235
«SP:
I:

I
(n

I
m

wa'o

5555
—

D-

REOVIPRTgR
C
L

RFI

SHIELD

(M849)

U)
_1

I
I
_J(
Iggzgfiolzflqggg
2522555252323

8
‘T'M'NG
POWER
CONTROL
DATA

<
0

LOAD

(MM8—3)

—

<[ (D

3 1: D

<1:

I
(D

(M8300)

I-I

I—

Egggg
2:33:
I:

—-‘

—J

<
I—

go
g:-

0
0

8
'2

OM N I BUS

I
.J
.—

)5
o

Po1NT

REIéIchERs

(M8310)
I

:1)

LMD
aus

MEMORY

(M833)

PL OT
DISPLAY
CONTROL
VC8 E (M869)

DATA

TIMING

GENERATOR

‘0
.1

(r
m

SEgISTERS

LOAD
LOAD
LOAD

1
REALTIME
CONTROLS
CLOCK
DK8-EP

4
‘3

I/O DRe-E

‘

m)
_|

I
I
I z
I
I
I

BBIEIETIIAED

(A231)
TIMING

I
TO
ANALOG
CONVERTER
vce E
(M885)

A/D
CONTROL
ADS-EA

DG
1
1 TAL

1 1

CONTROLQ

Z‘I

OKs—E1.INPUT/
OUTPUT
PANEL

INPUT/

ENABLE

HO
POWER

HO POWER
——> T0 LAB 8/E
MODULES

.1
o

E
z

o
v

VR14
RM503
OR
602
OSCILLOSCOPE

I
I
I
I
I
|
I
I

If)

'3'

<
o

5
U

22 as a

E 3< 3 5
O _] 5 E :
0
I“

POWER
SUPPLY

BUS
LOADs

TELETYPE
CONTROL

(H724)

(M832)

(M865)

I
.

PROGRAMMERS

CONSOLE
KCB-E

TTY

EE-OIBB

Figure 1-1

LAB-8/E Basic System

20 PDP-8/E or LAB-8/E options. The user can add one or more additional OMNlBUS modules to accommodate
more

options, if required.

Three categories of options are provided with the LAB-8/ E:

internal options, OMNIBUS options, and external
options. Internal options are units, such as Extended Memory, and Extended Arithmetic Element, that extend

the capability of the processor but do not control peripherals. OMNIBUS options include internal and external

options that plug directly into the OMNIBUS. External options are units that indirectly plug into the OMNlBUS
through an l/O Bus Adapter interface.
The specifications for the LAB-8/E Central Processor and options are shown in Table 1-1. The options are de-

scribed in the following paragraphs.

1.2.1

Analog-to-Digital Converter (ADS-EA)

The Analog-to-Digital (A/D) Converter consists of the A841 and A231 modules. The A841 module contains

analog circuitry, including the A/D weighing switches, comparator, and sample and hold. The A231 module
contains all the control logic for the A841 module. The ADS-EA receives a $5 Vdc signal and produces a 9-bit
+

sign digital word representing the input. The two modules are joined by an H851 Edge Connector.

1.2.2

Analog Preamplifier and Multiplexer (AM8-EA)

The AM8-EA is a single A232 quad module containing eight analog preamplifiers and eight multiplexer channels
that select the output of one preamplifier to be applied to the A/D converter. An additional module expands
the multiplexer to 16 channels.

Input to the AM8~EA is :1 V differential and the output is :5V single-ended to

the A841 module of the AD8-EA.

1.2.3

Point-Plot Display Control (VC8—E)

The VC8-E consists of the M885 and M869 modules. The M885 module receives 9 bits + sign of digital data and
converts it to $5 Vdc voltage to be applied to the oscilloscope display.

The M869 module contains all the control

logic to control the Digital-to-Analog (D/A) converter.
1.2.4

Buffered Digital l/O (DR8-EA)

The DR8-EA consists of one M863 module.

It can provide 12 digital inputs and 12 digital outputs for the LAB—

8/ E and can be used to sense external events. The inputs and outputs are TTL compatible; ground (0V) represents

logical true and high (+3V) represents logical false.
1.2.5

Real-Time Programmable Clock (DK8-EP)

The DK8-EP consists of the M860 and M518 modules. The M518 module contains the input logic and Schmitt

triggers.
a

The M860 module contains the control logic, registers, and IOT decoding logic. The DK8-EP provides

programmable time base that allows the user to control and/or record internal and external events. It can be

used to measure time between events, record number of events in a given time, or initiate repetitive operations
at specified intervals of time.

NOTE
The following panels are single-width or double-width
modules which are mounted in the H945 option cab-

inet, Nuclear Installation Module (NIM) Binary Load(BIN), for connecting inputs and/or outputs to the
LAB-8/ E System.

1-3

1.2.6

Analog Input Panels (AM8—ED and AM8-EC)

The AMS-ED and AM8—EC panels are used to supply inputs to the analog multiplexer and are mounted in the
H945 cabinet. The AM8~ED has two DB-258 25-pin connectors with matching plugs. The AM8—EC has four
inputs from potentiometer channels 0 through 3. As on the AM8-ED, channels 48 through 178 are supplied on
the DB-25S.

1.2.7

Real-Time Programmable Clock Input Panel (DK8-EF)

The DK8—EF panel has inputs for the Schmitt triggers.

It also provides connections for EXT CLOCK or EXT

STA RT signals.

1.2.8

Digital l/O Panel (DR8-EB)

The DR8-EB provides a front panel assembly with two M904 modules, with connections for input and output to
the DR8-EA Buffered Digital I/O.

Table 1-1

LAB-8/ E System Specifications

Specifications

Equipment
Central Processor

Processor Speed

Two memory cycles:
a.

Fast cycle accomplishes a FETCH, Internal IOT, or
DEFER (non-Auto Index) in 1.2 Ms.

b. Slow cycle accomplishes (after FETCH) an instruc—
tion execution, or DEFER (Auto Index) in 1.4 ps.
Instruction Execution Time (MRI only)

The instruction execution time, beginning with the instruction completely executed, requires one fast and one slow
memory cycle, or 2.6 us.

Word Length

12 bits

Addressing

Direct memory addressing is controlled on front panel or

through the Data Break system. Programmed addressing is
accomplished as a function of software. 200 octal memory
locations may be directly accessed (except when on page 0)
by the program during any one memory cycle.

Program Loading

Programs may be loaded by Read-ln-Mode (RIM) or Binary
Loader (BIN). RIM is read into memory using toggle
switches on front panel. BIN is a program used to load other
programs.

Input/Output Capability

Three types of input/output transfers (IOTs) are provided:
a.

Programmed input/output or transfers

Programmed Interrupts

Data Break

Data Break is a method used to read out of, or write into, a

block of memory during normal processing.

(continued on next page)

1-4

Table 1-1 (Cont)

LAB-8/ E System Specifications

Equipment

Specifications

Central Processor (Cont)

Memory Capacity

4096 12-bit word memory locations which can be expanded
to 32K of memory

Power Requirements

95—130 Vac, 47—63 Hz, approximately 6A single-phase, or
185—250 Vac, 47—63 Hz, approximately 3A single-phase
with 450W power dissipation

Power Requirements (Teletype)

115 i 10% Vac, 60 Hz i 0.45 Hz, or 230 i10% Vac, 50 Hz
i 0.50 Hz,

Environment

2A line current drain, 150W power dissipation

The LAB-8/E is designed to operate at 0°C to 55°C with a relative humidity of 10% to 95% (without condensation).

Cable Requirements

The LAB-8/E I/O cable is a combination shielded and coaxial
cable. The maximum length of Data Break l/O Bus cable is

30 ft, using a coaxial cable. Maximum length of the programmed l/O Bus is 50 ft, using a coaxial cable.
Instructions

Eight basic instructions constitute the instruction set:
AN D

0000

Logical AND

TAD

1000

2’s complement add
Increment and skip if 0
Deposit and clear AC

lSZ

2000

DCA

3000

JMS

4000

JMP

5000

Jump to subroutine
Jump to another memory location

IOT

6000

In/out transfer

OPR

7000

Operate

A/D Converter (ADS-EA)

Input Voltage

lnput Impedance

i5.0 Vdc

Differential. Plus input greater than 10 M52; negative input
with jumper, greater than 10 k9 (negative input intended for
use as an external

ground sense; i.e., impedance from negative

lead to computer ground < 20 Q for given common mode

rejection (CMR) specification).

Output Format

Parallel data, 10 bits, right justified, and sign extended 2’s

complement
Common Mode Rejection

At least 35 dB at 60 Hz. Common mode voltage less than
5V to ground

Resolution

0.1% (1 bit in 1024)

Accuracy

0.2% of full scale*

Conversion Rate

50 kHz maximum

Power Requirements

i5 Vdc i10%1A,+15 Vdc i 0.1% 150 mA, -15 Vdc i 0.1%
150 mA

Temperature StabilityH

0.01% full scale/°C

(continued on next page)

1-5

Table 1-1 (Cont)

LAB-8/ E System Specifications

Specifications

Equipment
Analog Multiplexer (AM8-EA)
Input Voltage

Differential i 1V; 16 channels, maximum

Input Impedance

Non-inverting input is 70 k9 in parallel with 300 pF.
verting input is 35 k9 in parallel with 300 pF.

Common Mode Rejection

Greater than 25 dB, 35 dB typical

Overload Protection

:67V from fault line

Overload Recovery Time

8 us

Frequency Response

Flat from 0 to 30 kHz, -3 dB at 60 kHz

Leakage Current
Temperature Stability*

In—-

Negligible at 70k impedance
*

Output

0.01% full scale/°C
:5V full scale, single-ended, 0.2% accuracy*

Point-Plot Display Control (VCB-E)

Input Format

10 bits of data in 2’s complement format

Output Voltage

+5.01 to

Resolution

10 mV i 2.5 mV

Slewing Speed

1.25 V/ps

Driving Capability

Capable of driving loads greater than 1 k9 minimum, in
parallel with 5000 pF; l.e., 100 ft of 50 pF/ft cable

Power Requirements

+5 Vdc= 10% 1A, +15 Vdc:L 0.1% 150 mA, -15 Vdc i' 0.1%

5.01 i 0.1 Vdc offset (adjustable)

150 mA
2 Axis Intensity Pulse

1 us, + 4V to -2V or + 4V to -10V positive- or negative-going

Buffered Digital l/O (DR8-EA) Programmable Input and Output

Input

12 parallel bits or 12 independent bits selected by jumpers.

Output

12 parallel buffered bits or 12 independent bits

Input Levels

TTL compatible levels.

Output Levels

TTL compatible levels.

Input lines are clamped at +5V for
positive input protection. Input source must sink 3 mA in
the 0 (true) state.

Outputs can sink 20 mA in the 0

(true) state.
Power Requirements

+5V, 2.25A (worst case)

Programmable Real-Time Clock (DK8-EP)
Control

20 MHz crystal controlled

Schmitt Triggers

Three threshold detectors that accept pulse or varying analog

inputs (i5V variations)
(continued on next page)

1-6

Table 1-1 (Cont)

LAB-8/ E System Specifications

Specifications

Equipment
Programmable Real-Time Clock (DK8-EP) (Cont)
Input

i50V maximum differential input, 50 k9.
common

Input impedance,

mode rejection 35 dB

input Pulse Width

Minimum input pulse width 2 us

Propagation

60 ns

Time Base

Programmable time base, rate set in clock. Enable Register
1 MHz to 100 Hz

Slope

i switch selectable

Data Format

12 parallel bits

Overall system accuracy with AD8-EA and AM8-EA is 0.3% full scale.

Overall system temperature stability with ADS-EA and AM8-EA is i 0.02% full scale/0C.

1.3

PHYSICAL DESCRIPTION

The LAB-8/E System is available in rack-mounted and table-top configurations.

Both configurations can be in-

stalled in a small space for easy operation and maintenance, and can be expanded as the user's requirements are
increased.
The rack-mounted version of the LAB-8/ E allows the user to place the processor and an assortment of peripherals

in one area. The basic cabinet (see Figure 1-2) will hold all of the peripherals in the basic LAB-8/E System. The
two pairs of frame uprights have 9/32 in. holes drilled at standard EIA spacings (5/8

—

5/8

—

1/2) the full length

of the 63 in. mounting panel height. The processor and peripherals can be installed on slides to allow easy access
for maintenance and troubleshooting. The cabinet has a filter cover for equipment ventilation.
The table-top LAB-8/ E requires less space than the rack-mounted version. The table-top version, placed on a desk
or

table-top puts all controls within easy reach of the operator. The display or other peripherals can be installed

in a system—expander box and placed alongside the processor. This configuration will allow the user to sit at his

desk, operate the LAB-8/ E, and have access to all controls on the processor and display units.
1.4

DOCUMENTATION

Computer handbooks, maintenance manuals, and engineering drawings are supplied with the LAB-8/ E to assist
the operation and maintenance personnel. A list of the documents necessary for the LAB-8/ E System is provided
in Table 12. Some of the documents listed are used for only one option and will not be shipped with the system
if that option was not purchased. Additional copies of these documents may be purchased from Direct Mail,

Digital Equipment Corporation, Maynard, Massachusetts 01754.

1-7

x3,
,

Stinaquiavéza

é:

As:

,91ezfisfii.

Figure 1 -2

LAB 8/E Rack-Mounted Vers Ion

1-8

Table 1-2

LAB-8/ E Handbooks, User’s Manuals, Maintenance Manuals, and Engineering Drawings
Title and Document No.

Description

LAB-8/E User’s Handbook

Provides installation, system description and operating

DEC-LB-H RZA-D

instructions for the LAB-Bl E System.

PDP-8/E Maintenance Manual

Installation, acceptance test theory of operation, and

DEC-8E-H R l B-D

maintenance procedures, programming data for LAB-8/ E
processor

PDP-8/E Small Computer Handbook

—

1972

PDP-8/E options, interface, installation, and DEC support
services

VR 74 CRT Display User’s Manual

Provides operation, maintenance, and interfacing infor-

DEC-12-H RZA-D

mation for the VR14 display.

33 ASH Teletype Operators Manual

Provides operation and maintenance information for the

Bulletin 273B, Volume 1

Teletype Model 33 ASR.

A-ML-VC8-E Print Set

Prints for Point-Plot Display Control modules (M869
and M885)
Prints for Real-Time Clock and Schmitt trigger modules

A-M L-DK8-EP-0

(M860 and M518)
A-M L-DK8-ES-0

Prints for Real-Time Clock Input and Output Panel

A-M L-D R8-EA-0

Print set for Buffered Digital I/O module (M863)

A-M L-AM8-EA-0

Print set for Analog Multiplexer module (A232)

A-M L-AD8-EA-O

Print set for A/D Converter modules (A841 and A231)
Print set for Analog Input Panel with two DEC 25-pin

A-M L-AM8-ED-0

connectors

Print set for Analog Input Panel with two DEC 25-pin

A-M L-AM8-EC-O

connectors, phone jacks, and potentiometers on channels 0 octal through 3 octal

A/D Converter and AM8-ED panel (modules A231 and

A-M L-ADS-ES-O

A841)
A-PL-DR8—EB—O

D-UA-DR8-EC-0

}

Prints for Buffered Digital I/O panel assembly with

M904 and M953 modules

A-M L-LAB-8/E-0

Print set for LAB-8/E

845X 00471 1513/003/2.5

LAB-8/ E Programming Card

1-9

CHAPTER 2

INSTALLATION

This chapter contains supplementary information and procedures for installation of the LAB-8/E System. Basic
installation and planning information, such as space requirements, installation requirements, and system config—
uration is provided in Chapter 11 of the PDP-8/E Small Computer Handbook and Chapter 2 of the PDP-8/E
Maintenance Manual.

Installation functions and requirements are summarized in Table 2-1 of this manual.

l/O

cabling requirements and cables supplied by DEC for use in interfacing with the LAB-8/E and connecting options
to each other are listed in Paragraph 2.2.

Table 2-1

Summary of Installation Functions
Function

Responsibility
User

Identify space and power required for system configuration.

2.1

User/ D EC Representative

Survey proposed site.

User

Prepare site in accordance with environmental space and
power requirements.

User/DEC Representative

Unpack equipment and check inventory checklist.

DEC Representative

Install equipment.

SITE CONSIDERATIONS

Adequate site planning and preparation can simplify the installation process and result in an efficient, more
reliable LAB-8/E installation. DEC Sales Engineers or Field Service Engineers are available for consultation with
user

personnel regarding the installation.

Site planning should include a list of the actual components to be used in the installation and a list of such items
as storage

cabinets, Teletype supplies, work tables, peripherals, etc.

Primary planning considerations are:
The availability and locations of adequate power

$09.9?!”

Protection against direct heat sources
Electrical-noise radiation
Protection from shock

Existence of fire protection devices

2-1

2.1.1

Power Source

The power source should be free of conductive interference. DEC offers a line filter, as an option, to provide an

interference-free power source. All computer system supplies should be connected to the same power source to
avoid loading and source differentials that may affect operation.

2.2

I/O PANELS AND CABLING REQUIREMENTS
For rack-mounted equipment, cables can

The cabling for table-top and rack-mounted computers differs slightly.

be routed into the cabinet through a panel located at the bottom of the cabinet.

Subflooring is not necessary

because casters elevate the cabinet enough to provide sufficient cable clearance.

For table-top models, cables are

routed from the lower rear side through the adjustable strain relief of the processor. All cabling should be located
where it cannot be damaged. ‘This is especially important if the processor and peripherals are not in proximity.
The A/D converter, multiplexer, digital I/O, and the point-plot display require additional cabling and panels for

interface with the outside world. The following paragraphs discuss each of the LAB-8/E peripherals and their

special cabling requirements.
2.2.1

A/D Converter Connections

The A/D converter provides a differential input capable of 35-dB rejection of common-mode noise at 60 Hz.

Inputs can be single-ended or differential. For differential connections, potential between input source and
chassis ground must be less than 5V, and the impedance from negative input to computer ground should be less

Figures 2-1 and 2-2 show the two input wiring schemes.

than 20 82.

A/D CONVERTER

OUTO

GND

0—

INPUT

A/D

—O

INPUT
SOURCE

0—

INPUT
SOURCE

LOSHIELD

~OSH|ELD

OCHASSIS

CHASSIS

8E-02918

Figure 2-1

c0Nv

INPUT

BE-OZSIA

Figure 2—2

Sing|e~Ended Measurement Connection

Differential Input Measurement
Connection

The AM8—ED and the AM8—EC Analog Input Panels (see Figures 2-3 and 2-4), and a cable are available for use

with the A/ D converter. The AM8—ED panel provides the user with two DB-ZSS receptacles (see Figure 2-5).
This provides ample inputs for a maximum configuration 16-channel system. The same panel is supplied with an

AD8-ES option where the single input is wired into channel 0 of the panel. Field expansion with AM8—EA (two

maximum) options can utilize the same panel for signal inputs. Two DEC 12-05886 DB-25P connectors are

supplied with these options. The second panel available, the AM8—EC analog panel, is similar to the first type,
except that parameter potentiometers are supplied for channels 0 through 3.
The potentiometers, with i1 Vdc applied, are useful for varying thresholds and moving pointers across display

tubes. The $1 Vdc inputs to channels 0 through 3 can be disconnected from the potentiometers by installing
a 3-conductor

1/4 in. phone jack (DEC No. 12-09430) in the proper channel. Four phone jacks are supplied with

each AM8—EC panel. Table 2-2 and Figure 2-5 show pin connections on the AM8-ED and AM8-EC panels. The

wiring of channels 10 to 17 on both panels is identical to the wiring of channels 0 through 7 on the AM8-ED
panel, except that channel 0 corresponds to channel 10, 1 to 11, etc.

2—2

CNANNELS
A

CHANNEL-S
10

ANALOG INPUT

Figure 2-4 AM8—EC Analog Input Panel, Front and Rear View
Figure 2-3

AM8—ED Analog Input Panel

Table 2-2

AM8-ED and AM8-EC Analog Panel Pin Connections
Channel
130

Number

Input

Pin on

AM8-ED

AM8-EC

.25
120
'24
110

.20

'19
'18

:1:

Phone plug

Shield

Phone plug

.14

Shield

—

5.
“7

Phone plug

—

.21

10-

Shield

Phone plug

Shield

Phone plug

Shield

GROUND
_

Figure 25

7
Front View of

08-258 Connector and

Telephone Plug

2-3

A 7008533 cable is also available for analog input con-

Table 2-3

nections; Table 2-3 shows the connections for this con-

Analog Connection Using 7008533 Cable

figuration. No analog panel is required when this cable

Channel

is used.

Input

Number

The A/ D converter can also receive inputs from the

Red
Black

nector. When the AM8—EA is used, the cables from the

analog panel

Wire

Color

AM8-EA Preamplifier and Multiplexer via an edge con-

or the

Cable
Number

Shield

7008533 cable will be connected to

Drain
Green

Black

—

the AM8—EA module.

Shield

2.2.2

Buffered Digital l/O Connections

Drain
1

White

Black

Shield

The Buffered Digital I/O provides 12 digital inputs and

12 digital outputs for the LAB-8/ E System. inputs and

Drain
2

Red
Black

—

outputs are TTL compatible (low true), giving the user

Shield

the option of providing level converters or signal condi-

tioners. Each input may monitor the external line

directly,

Drain
2

Green
Black

may sense the occurrence of a negative-

Drain

Shield

going transition. Skip and Interrupt capabilities are

White
Black

—

provided for the Input Register.

Shield
Two ways of interfacing to the Buffered Digital l/O are

available. The first is by two BCO8J-X cables. Each of

Red

Black

—

Drain

Shield

these cables is a ribbon type, terminated by a Berg connector on one end and a

Drain

standard DEC cable connector

Green

Black

module on the other end. One cable is used for input

Shield

and the other for output. See Table 2-4 for cable pin

Drain

NOTE: Channel 10 is the same as channel 0,

assignments. The second interface is by way of the

11 as 1, etc.

DR8—EB panel which contains two H807 module conA standard M904 is used for cable connection.

nectors.

The DR8—EB panel is NIM-dimensionally compatible and may be used in the DEC H945 Laboratory Expander
Box or any NIM BIN. Table 25 shows correct configuration for connection to the DR8-EB panel.

Table 2-4

Table 2-5

BC08J-X Connection and Bit Assignments

Connections For DR8-EB Panel Assembly

Bit No.

Pin No.

Bit No.

Pin No.

Bit No.

Pin No.

Bit No.

Pin No.

Grounds A1, C1, F1, K1, N1, R1, T1, CZ, F2,
J2, L2, N2, R2, U2

Grounds A1, C1, F1, K1, N1, R1,T1, C2, F2,
J2, L2, N2, R2, U2

2-4

2.2.3

Real-Time Programmable Clock Input Connections

Inputs to the clock are supplied by a DK8-EF panel containing three cables which connect to the M518 module.
Inputs and outputs to the panel are supplied by three phone jacks and five BNC connectors. Table 2-6 shows the

panel connectors and pins.
Table 2-6

Real-Time Programmable Clock Connections
Panel Connector

Description

In 1*

(+) Plug tip

Schmitt trigger, 1-Input

(-—) Plug center

(ground) Shell
In 2

(+) Plug tip

Schmitt trigger, 2-Input

(—) Plug center

(ground) Shell
(+) Plug tip
(—) Plug center

Schmitt trigger, 4-Input

In 4

(ground) Shell
Out 1

Schmitt trigger, 1-Output

BNC

Out 2

Sch mitt trigger, 2-Output

BNC

Out 4

Schmitt trigger, 4-Output

BNC

User-supplied clock frequency

BNC

Clock-overflow bit output

BNC

Ext. Clock In**

Overflow

*Each slope switch and threshold potentiometer determines the input slope and firing voltage of the respective
Schmitt trigger.
**

2.2.4

Rate Select 001 chooses the External Clock In as the time base rather than internal timing (see Paragraph 4.6.2.3).

Point-Plot Display (VC8-E) Control Connections

The VC8-E interfaces with the VR14 by means of the BC01 K cable, and with the Tektronix 602 by means of the

BCO‘I L cable. Both cables connect to a Berg connector on the M885 module. A 7008499 Cable Assembly is

supplied with basic systems when an oscilloscope is not purchased to connect to the M885 module. Table 2-7
shows connections for each of the cable assemblies used on the VC8—E. All three cables have a DB-25P connector
to connect to the DB-25S Berg connector on the VC8-E.

Table 2-7
VC8-E Cable Connections

VC8-E

Signal Name
CHANNEL L

Cofiileitor
.

Pm
2

BCO1K*

BC01L*

25-Pin Side

703?:99
Color

VR14

Signal Name**

Green

ZSELECT

Shield

Chassis ground

LOGIC G ROUND

Black

Chassis ground

2 AXIS

Shield

Z BNC

Red

2 INPUT

Shield

Chassis ground

*Connection of cable determined by user.
”See the W? 14 CRT Display User’s Manual, page 2-5, for more information on pin assignments.

(continued on next page)
2-5

Table 2-7 (Cont)
VC8-E Cable Connections

VC8-E

Signal Name

Cossgtor
.

3cm”

BC01L*

25—Pin Side

mgfigg

VB”

Signal Name**

Color

LOGIC GROUND

Z BNC

Black

Chassis ground

X ANALOG

X BNC

Green

+ X

X BNC

Black

ANALOG GROUND

Shield

Y ANALOG

ANALOG GROUND

Shield

INPUT

X INPUT

Shield

i X

INPUT SHIELD

Y BNC

Red

+ Y

INPUT

Y BNC

Black
Shield

—

Y INPUT

’5 Y

INPUT SHIELD

13
*Connection of cable determined by user.
”See the VI? 14 CR T DI’Sp/ay User’s Manual, page 2-5, for more information on pin assignments.

2.3

FIRE AND SAFETY PRECAUTIONS

The power supplies for the LAB-8/ E contain a thermal cut-out switch, a circuit breaker, and fuses for protection

against overheating and overloading. The thermal cut-out switch will remove the ac input when the temperature
reaches 90 i 5°C. The PDP-8/E Maintenance Manual lists the fusing and circuit breakers used on power supplies
in Paragraph 3.5. Both the cabinets and power receptacle must be adequately grounded to ensure safe operation.

A water pipe or steel beam provides an adequate ground. Refer to Chapter 11 of the PDP-8/E Small Computer

Handbook for grounding and power installation procedures.
WARNING
The frame of the computer must be grounded to

protect personnel from dangerous electrical shock.

Grounding is usually automatically achieved if a 3-wire plug is used; however, a voltage reading from ground to
frame should be performed during installation.
Electrical fires, although extremely unlikely, should be extinguished by a Class 3 (002) fire extinguisher.
2.4

INSTALLATION PROCEDURES

Installation of a LAB-8/ E requires only normal hand tools. No special tools or equipment are necessary; however,
a fork

lift, truck, or pallet handling equipment should be available for installing the rack-mounted system.
NOTE
Refer to the PDPB/E Maintenance Manual for
processor installation.

2.4.1

Unpacking and Inspection

Unpack and inspect the LAB-8/E using the following procedure:
CAUTION
Do not attempt to unpack or install the system until the DEC Sales Office has been notified and a

Field Service Representative is present. This is required to validate the warranty.

2-6

Procedure

Step
1

Remove the packing material.

Visually inspect system.
Inventory all components and accessories. Refer to the tables listed be-

low for a list of items to be shipped with each option.
a.

ADS-EA

Table 2-8

AD8+ES

Table 2-9

AM8—EA

Table 2-10

AM8—EC

Table 2-11

AM8-ED

Table 2-12

DK8-EF

Table 2-13

DK8—EP

Table 2-14

DK8—ES

Table 2-15

1'.

DR8-EA

Table 2-16

1'.

DR8-EB

Table 2-17

DRS—EC

Table 2-18

VCB-E

Table 2-19

VM03

Table 2-20

Table 2-8

ADS-EA Accessory and Component List

Quantity
Item

Identification

Number

A231

Description

AD8—EA control module

ADS-EA

ADg-EA
W'th

Alone

AM8‘EA.
ED, or EC

A841

10—bit A/D converter module

H851

Edge connector

7008533

Analog cable assembly

Analog HQ power supply assembly

70083701

115 Vac tabletop mounting

7008370-2

230 Vac table-top mounting

7008477-1

115 Vac rack mounting

7008477-2

—

230 Vac rack mounting

7008375

Analog power cable

AD8-EA-0

AD8—EA master drawing set

LAB-8/ E

LAB-8/ E master drawing set

MAINDEC-BE-D6BB-PB

AD8-EA/AM8—EA diagnostic binary tape

MAI NDEC-8E-D6BB-D

AD8-EA/AM8-EA diagnostic document

DEC-LB-HRZA-D

LAB-8/E User’s Handbook

DEC-LB-HXZA-D

LAB-8/E Maintenance Manual

845X 00471 1513/C-03

LAB 8/E programming card

*ltem number 5 is not to be supplied to system in the field with a VC8-E installed.

specific system in systems production.

2-7

HQ power supply type and part number are tailored to a

Table 2-9
ADS-ES Accessory and Component List

ldefizflgfion

MESS”

Quantity

Description
V

A231

ADS-ES control module

A841

10-Bit A/D converter module

H851

Edge connector

7008386

LAB-8/E simple analog input assembly

12-05886

DB~25P connector

12-05885

DB~51226—1 hood

Analog HQ power supply assembly

70083701

115 Vac table-top mounting

70083702

230 Vac table-top mounting

7008477-1

115 Vac rack mounting

7008477-2

230 Vac rack mounting

7008375

Analog power cable

1
1

AD8-ES-0

AD8-ES master drawing set

LAB-8/ E

LAB-8/ E master drawing set

MAINDEC-8E-D6BB-PB

AD8-EA/AM8-EA diagnostic binary tape

MAlNDEC-8E-D6BB-D

AD8—EA/AM8—EA diagnostic document

DEC-LB-H RZA-D

LAB-8/E User’s Handbook

DEC-LB-HXZA-D

LAB-8/E Maintenance Manual

845X 00471 1513/C-03

LAB-8/ E programming card

12
,

*Item number 7 is not to be supplied to systems in the field with a VC8-E already installed.
to a specific system

HQ power supply type and part number are tailored

in systems production.

Table 2-10

AM8-EA Accessory and Component List

Quantity
AMS'EA
It em

ld en t'f'
I ma t'non

Number

Description

Number

AM3 EA

With

Alone

AM8-EC
or

AM8-ED
1

A232

Analog Preamplifier and Multiplexer Expander

H851

Edge connector

7008533

Analog cable

AM8—EA-0

AM8—EA master drawing set

D-lA-7008533-0-0

Analog cable assembly drawing

2-8

Table 2-11

AM8-EC Accessory and Component List
Item

Identification

Number

Des c ri p tion

0 u anti W

7008387

LAB-8/E Analog Input Assembly

AM8-EC-0

Analog panel master drawing set

12-05886

DB-25P connector

12-05885

DB-51226-1 hood

12—09430

Phone plug, Switchcraft No. 90

Table 2-12
AM8-ED Accessory and Component List

Item

Identification

Number

Descri p tion

Quantity

7008386

LAB-8/E simple analog input assembly

AM8-ED-0

Simple analog input assembly print set

12-05886

DB-25P connector

12-05885

DB-51226-1 hood

Table 2-13
DK8-EF Accessory and Component List
Item

Identification

Number

Descri ption

Q u anti ty

7008382

LAB-8/E clock assembly panel

7008492

DK8-EP diagnostic cable assembly

D-CS-7008382-0-1

DK8-EF circuit schematic

A-PL-DK8-EF-0

DK8-EF panel parts list

12-01455

BNC plug, Amphenol No. 31-002

12-09430

Phone plug, Switchcraft No. 90

A-PL-7008382-0-0

Real-Time Clock assembly parts list

Table 2-14

DK8-EP Accessory and Component List
Item

Identification

Number

Descri p tion

Quanti ty

M518

Schmitt trigger module

M860

Real-Time Clock Control module

H851

Edge connector

DK8-EP

DK8-EP master drawing list

LAB-8E

LAB-8/ E master drawing

MAINDEC-8E-D8AB-PB

DK8-EP diagnostic binary tape

MAI NDEC-8E—D8AB-DL

DK8-EP diagnostic document

DEC-LB-HRZA-D

LAB-8/E User’s Handbook

DEC-LB-HXZA-D

LA B-8/E Maintenance Manual

845x 0047 1513/C-03

LAB-8/E programming card

2-9

Table 2-15

DK8-ES Accessory and Component List
Item

Identification

Number

Quantity

Description

M518

Schmitt trigger module

M860

Real-Time Clock Control module

H851

Edge connector

7008382

LAB-8/ E clock panel assembly

7008492

DK8-EP diagnostic cable assembly

12-01455

BNC plug, Amphenol No. 31-002

12-09430

Phone plug, Switchcraft No. 90

DK8—ES-0

DK8-ES master drawing set

MAINDEC-8E-D8AB-PB

DK8-EP diagnostic binary tape

MAINDEC-8E-D8AB-DL

DK8-EP diagnostic document

1
1

DEC-LB-H RZA-D

LAB-8/E User’s Handbook

DEC-LB-HXZA-D

LAB-8/E Maintenance Manual

845X 00471 1513/C-03

LAB-8/ E programming card

LAB8-E-0

LAB-8/ E master drawing list

Table 2-16

DR8-EA Accessory and Component List
Item

Identification

Number

Quantity

Description

M863

12-channel Buffered Digital l/O module

BC08S-1

1-ft l/O cable assembly

BC08J-10

10-ft l/O cable assembly

DR8-EA

DR8-EA master drawing list

LAB8-E

LAB8-E master drawing set

MAINDEC-8E-DOOA-PB

DR8-EA diagnostic binary tape

MAI NDEC-8E-DOOA-D L

D R8-EA diagnostic document

D EC-LB-H RZA-D

LA B-8/E User’s Handbook

D EC-LB-HXZA-D

LA B-8/E Maintenance Manual

Table 2-17

DR8-EB Accessory and Component List
Item

Identification

Number

Description

Quantity

7008388

Digital l/O panel assembly

BC08R-12

12-ft l/O cable assembly

M904

Coaxial cable connector module

A-PL-DR8-EB-0

DR8-EB parts list

D-UA-DR8-EC-0

DR8-EC unit assembly drawing

DEC-LB-H RZA-D

LAB-8/E User’s Manual

2-10

Table 2-18

DR8-EC Accessory and Component List
Item

Identification

Number

Description

Quantity

M863

12-channel Buffered Digital l/O module

BC08R-12

12-ft l/O cable assembly

7008388

Digital I/O panel assembly

M904

Coaxial cable connector module

BC088-1

1-ft l/O cable

DR8-EC

DR8-E digital l/O master set

LAB-8/ E

LAB-8/ E master list

MAINDEC-8E-DOOA-RB

DR8-EA diagnostic binary tape

MAI N DEC-8E-DO0A-D L

D R8-EA diagnostic document

DEC-LB-H RZA-D

LAB-8/E User’s Handbook

1 1

DEC-LB-HXZA-D

LAB-8/E Maintenance Manual

Table 2-19
VC8-E Accessory and Component List

Quantity

NLti'Eer
1

”833221?“
M869

V53:

fof

VR14

VM03

VCS-E

°“'V
VC8-E Point-Plot Display Control module

‘

Desc'ipm"

M885

Point-Plot Display Control, D/A
module

H851

7008499

User display cable

BCO1 K

VR14 display cable

BCO1 L

Tektronix 602 Display cable

Analog HO power supply assembly

Edge connector

7008370-1

115 Vac table-top mounting

7008370-2

230 Vac table-top mounting

7008477-1

115 Vac rack mounting

7008477-2

230 Vac rack mounting

7008375

Analog power cable

VC8-E

VC8-E master drawing set

LAB-8/ E

LAB-8/ E master list

MAI NDEC-8E-D6CA—PB

VC8-E diagnostic binary tape

DEC- LB—H RZA-D

LA B-8/E User’s Handbook

DEC-LB-HXZA-D

LAB-8/E Maintenance Manual

845x 00471 1513/C-03

LAB-8/ E programming card

*Item number 7 is not to be supplied to systems in the field with an ADS-EA already installed. The HQ power supply type and number are tailored
to a specific system

in systems production.

2-11

Table 2-20
VM03 Accessory and Component List

2.4.2

Item

Identification

Number

Description

Quantity

74-08919

Single panel

74-08926

Oscilloscope support

74-08927

Oscilloscope brace

74-08931

Front panel

BC01L-10

10-ft oscilloscope cable assembly

1-300479

Resistor 10 K9, 1/4W 5% CC

1-300365

Resistor 1

1-300510

Resistor 33 K9, 1/4W 10% CC

1-301327

Resistor 68 K9, 1/4W 5% CC

1-000026

Capacitor 680 MM F, 100V 5% DM

1 1

74-09544

High voltage oscilloscope cover

74-09545

Hold-down bracket

VM03-0

VM03 master drawing set

K52, 1/4W 5% CC

2
1

Installation Procedure
NOTE
Refer to Step 13 for procedure needed to install
each of the LAB-8/ E options as they are added to
the basic system. Table 2-21 shows recommended

module positions.

Table 2-21
Recommended LAB-8/ E Module Installation Positions
Module

Description

KC8/E

Control Panel

M833

Timing Board

M8340

Extended Arithmetic Element (EAE)

M8310

Central Processor Major Register Control

M8300

Central Processor Major Registers

M837

Extended

Memory and Time Share Control

M869

Point-Plot

Display Control

M885

Digital-to—Analog Converter

A841

Analog-to-Digital Converter

A231

Analog-to-Digital Control Module

A232

Analog Multiplexer Expander

M860

Real-Time Clock

M518

Schmitt Triggers

M863

Buffered Digital I/O

M835

External l/O Bus Interface

M849

RFI Shield

G104

Memory Sense Inhibit (0)

(continued on next page)
2-12

Table 2-21 (Cont)

Recommended LAB-8/ E Module Installation Positions
Module

Description

H220

Memory Stack (O)

6227

Memory X/Y Drivers (0)

G104

Memory Sense Inhibit (n)

H220

Memory Stack (n)

6227

Memory X/Y. Drivers (n)

G105

Memory Sense/Inhibit (Parity)

H220

Memory Stack (Parity)

G227

Memory X/Y Drivers (Parity)

M832

Bus Loads (always in last slot)

Cther Memories

Install the LAB~8/E using the following procedures:

Step

Procedure

Ensure all ac power is supplied by one source.
WARNING
Do not touch computer after plugging it in, until it
is checked for proper ground.

Connect ac power.

Before touching computer, check frame-to-ground voltage. If a voltage is read,
disconnect power and check power and ground cables before continuing.
Connect ac power.
Turn on computer power switch and circuit breaker.
Check dc voltage at output of H724 power supply. See PDP—8/E Maintenance
Manual for voltages and monitoring points. Cover must be removed from power

supply for access to test points.
Turn off computer power switch.
Install HQ power supply on back of cabinet for rack-mounted system, or in
H945 option box for table—top system.

Connect HO power ac input cable.
NOTE
HQ power for 115 Vac system indicated by —2, and
240 Vac indicated by —4 after part number on power

supply.
1O

Connect HQ power supply to A231 or M869 module in this order.

Turn on computer power and measure HO power supply voltages with a dc voltmeter.

Voltages and monitoring points are shown in Table 2-22.
(continued on next page)

2-13

Table 2-22

High Quality Power Supply Parameters
Minimum

Maximum

Current

Maximum

Voltage

Rating

Ripple

+15.015

1.5A

1 mV rms

15.015

1.5A

1 mV rms

Voltage*

Wire
Coior

+15V

Orange

+14.985

15V

Blue

—14.985

Output

‘

—

*When installing the system in the field, a crude measurement (15%) of HO power i15V may be made to assure proper operation of the supply. If the HQ power supply is replaced, a precision measurement should be made to the specifications
in this table. The 7008375 HO power cable must be plugged into a module to join the voltage-sense lines before measurements are made.

Procedure

Step
12

Turn off power.

Check module positions with Table 2-21 and install modules. Refer to the steps
indicated below for installation of specific LAB-8/E options:

Step to Install

Option
a.

AD8-EA

AM8-EA, EC, ED

VC8-E

DR8—EA, EB, EC

DK8-EP, ES

VM03

VR14

RM503

21
NOTE

The recommended order of modules on the

OMNIBUS will result in best-case timing and permit
widest margins.
14

Install AD8-EA as follows:
a.

If HQ power supply is not installed, install the HQ power assembly

7008370 in second OMNIBUS mounting holes on basic cabinet or in
the H945 option box in the expanded system.

Assembly 7008482 is

to be installed in the rack-mounted system in back of the LAB-8/ E

cabinet.

NOTE
If AM8-EA is to be installed, remove jumper W1 on

split lugs in upper right-hand corner of A841 module
and install W2 jumper on the module.
b.

Install A231 and A841 modules in the OMNIBUS. See Table 2-21

for recommended module positions.
0.

Install edge connectors as shown in Figure 26.

Connect HO power supply to Mate-N-Lok connector on the A231
module.

Connect ac input to H0 power supply.

(continued on next page)

2-14

Procedure

Step
14

Connect analog input cable to Berg connector on the A841 module.
If an AM8-EA preamplifier is installed, the analog input will be

(cont)

supplied by an edge connector from the A232 module.
'

CONFIGURATION #1

1M863}DR8-EA
M518

M860}
}ADB-EA

DK8-EP

A231

A841

M885

VCB-E

M869

CONFIGURATION #2

M863}088-EA
M518
M860

A232

}DK8-EP
}AM8-EA

A231

}AD8-EA
M885}VC8_E
A841

M869

CONFIGURATION #3

1M863}DR8-EA
M518
M860

}DK8-EP

A232
AMB-EA

A232
A231
ADS-EA

A841
M885
VCB-E
M869
BE-OZSO

Figure 2-6 Edge Connector Installation (top view)
15

Install AM8—EA, AM8—EC, or AM8—ED as follows:
a.

Install one or two A232 modules in the OMNIBUS.

Refer to Table

2-21 for recommended module positions.
b.
0.

Install edge connectors as shown in Figure 2-6.
If an AM8-EC or AM8-ED front panel is installed, insert cable for

channels 0 through 7 in the A232 module behind the A231 module.
Insert cable for channels 10 through 17 in the second A232 module

(see Table 2-2).
0’.

If front panels are not installed, connect the 7008533 cables supplied
with the modules.

Install VCB-E as follows:
a.

Set switches and install jumpers as shown in Table 2-23 if oscilloscope
is used.

(continued on next page)

2-15

Step

Procedure

b. If AD8-EA was not previously part of system, install HO power supply

(see Step 14a) on back of cabinet for rack-mounted, or in H945 option

(cont)

box for table-top system.

If BE8~E is not used, install power supply in

the back of the OMNIBUS.
c.

Install M869 and M885 module in OMNIBUS. Refer to Table 2-21 for
recommended module positions.

d. Install edge connectors as shown in Figure 2-6.
9.

Connect H0 power supply cable to Mate-N-Lok connector on M869 module if ADS-EA is not installed.

7‘. Check HO power with a dc voltmeter (see Table 2—22).
9. Connect cable to Berg connector on M885 module.

Refer to Table 2-7

for cable to match system configuration.
NOTE
If two VC8—E options are installed, device selection code
on one must be 05 and the other must be

15. The device

code is selected by changing jumpers on the M869 module.
Table 2-23
Switch Requirements for VC8-E Modules
2 Switch

OscilloscOpe

Delay Switch

V R 14

Negative

Long

Tektronix 602

Positive

Short

RM503

Positive

Long

NOTE
On the RM503, remove W1 and install a jumper in AB.
17

Install DR8-EA, DR8—EB, or DR8-EC as follows:
NOTE
When more than one DR8-EA is installed, increment the
IOTs to 51, 52, etc. A maximum of eight M863 modules can be installed in the system. If an ADB-EA is in-

stalled, device code 53 must not be used.
a.

Ensure all flip-flop jumpers installed in the A position.

b. Ensure all Interrupt jumpers are installed in W1 to W12.
0.

Ensure all IOT jumpers are in the H position (on device code 50 only).

d. Install M863 module in OMNIBUS. See Table 2-21 for recommended
module positions on the OMNIBUS.
e.

If the DR8-EB panel is not installed, connect BCOBJ cables to connectors marked INPUT and OUTPUT.

f. If the DRB-EB panel is installed, connect BC08R cables and the module adapters. See Table 2-5 for connections.

NOTE
Cable connection is standard on M863 module, but cable

connected to front panel must be inserted with writing on
cable plug adjacent to module (upside down).

2-16

(continued on next page)

Procedure

Step
Installation of DK8-EP or DK8-ES:

Install M860 and M518 in the OMNIBUS.

Refer to Table 2-21 for

module positions.
Install edge connectors as shown in Figure 2-6 for DK8-ES or DK8-EP.
If this is a DK8—ES, install DK8—EF front panel and connect front
panel cable to M518 module.
Install VM03 modification kit for the Tektronix 602 oscilloscope as follows:

NOTE
See Table 2-24 for parts list.
Refer to page 2-3, Figure 2-2 in the Tektronix manual.
Remove the jumper wire from the stand-off pins on the X and Y de-

flection amplifier.

Replace the jumpers (add in series) with a 10K

resistor on the X and Y axis.

Install the 1K resistor and a 680 pF capacitor in the slots marked
ADD SHUNT on the X and Y deflection amplifiers.
Refer to page 2-4, Figure 2-3 in the Tektronix manual.

Remove the

resistor and capacitor from the stand—off pins marked SERIES

RESISTOR (Z axis).
Install the 33K resistor (shunt and 68K resistor in series).
Connect BC01 L cable to VC8—E option.

NOTE
Refer to Paragraph 5.4.7 for calibration procedure.

Table 2-24
VM03 Tektronix 602 Modification Kit Parts List
Part

Quantity

DEC Part No.

Resistor

10K, 1/4W, 5%

13—00479

Resistor

1K, 1/4W, 5%

13-00365

div-ANA.)

Resistor

Capacitor
Interface Cable

Description

33K, 1/4W, 10%

13-00510

68K, 1/4W, 5%

13-01327

680 pF, 100V 5%

10-000026
BCO1 L

Install VR14 oscilloscope as follows:
a.

Install VR14 oscilloscope in the H945 equipment rack or place on a
table beside the LAB-8/E if this is a table-top system.

b. Connect BCOI K cable between VR14 and VC8—E (see Table 2-7).

(continued on next page)

2-17

Procedure

Step
20

CAUTION

(cont)

Ensure the intake and exhaust for equipment cool-

ing are not blocked. Air is drawn in from the bottom of the unit and exits through the rear. The

VR14 must not be pushed against a wall or other

vertical surface which blocks the cooling air flow.
0.

Connect ac power cable to the VR 14.
NOTE
Refer to the VR14 manual and Paragraph 3.2 of
this manual for more information on the VR14.

Install the RM503 as follows:
a.

Connect ac power to the RM503.

Connect a 7008491 cable between the VC8-E and the RM503 oscil-

Ioscope.
NOTE
Refer to the RM503 instruction manual for operation and calibration of the RM503.

Turn on power.

Check HQ power for +15V on orange lead and -15V on blue lead.
NOTE
Procedures for assembling and installing the PDP-8/ E
and the Teletype are in Chapter 2 of the PDP-8/E
Maintenance Manual.

2.5

ACCEPTANCE TEST

The acceptance test will check out the central processor and each of the LAB-8/ E options to ensure that they
function properly as a system. The acceptance test should be performed before operating the system, after installation is completed, and periodically thereafter to verify there has been no system deterioration or change in

calibration of the analog units. If performance of the acceptance test indicates units are out of calibration, or
should other problems develop, refer to Chapter 5 for calibration and troubleshooting procedures. Users are ad-

vised not to adjust the LAB-8/ E System until they are familiar with the calibration and maintenance procedures,
which should be followed closely to accomplish an accurate calibration.
The following paragraphs describe the procedures for testing the LAB-8/ E System. All modules, connectors,

panels, etc., should be installed as specified in Paragraph 2.4 before attempting the acceptance test.
The acceptance test diagnostics needed to check the LAB-B/ E and its peripherals are shown in Table 2-25.
NOTE
All diagnostics require a programmer’s console, a

working Teletype, and at least 4K of memory with
the basic system.

2-18

Table 2-25

LAB-8/ E Acceptance Test Diagnostics

Diagnostic Number

Setting

SA/CR

Execution
Time

Acceptance
Time

Instruction Test l & ll

MAINDEC-BE-DOAA

200/000

2 sec

3 min

Instruction Test ||

MAlNDEC-8E-DOBA

200/000

2 sec

3 min

Adder Test

MAINDEC-8E—DOCA

200/000

35 min

Basic JMP JMS Test

MAI NDEC—8E-DOIA

200/000

10 sec

3 min

Random TAD Test

MAINDEC-8E-DOEA

200/000

5 sec

3 min

Random AND Test

MAINDEC-8E-DODA

200/000

2 sec

3 min

Random lSZ Test

MAINDEC-8E-DOFA

200/000

8 sec

3 min

Random DCA Test

MAINDEC-8E-DOGA

200/000

5 sec

3 min

Random Jump Test

MAlNDEC-8E-DOJA

200/000

8 sec

3 min

Random JMP JMS

MAINDEC-8E-DOJA

200/000

11 sec

3 min

Memory Address Test

MAlNDEC-8E-D LEA

200/000

50 sec

5 min

Checkerboard Test

MAINDEC-8E-DLAA

200/000

5 min

Teletype Control Test

MAINDEC—8E-02AA

200/000

Memory ON/OFF Test

MAINDEC-8E—DLGA

200/000

Real-Time Clock (DK8—EP) Test

MAINDEC-8E-08AB

200/4000

2 passes

Buffered Digital l/O (DR8-EA) Test

MAINDEC-BE-DOOA

200/000

10 min

Point-Plot Display Control (VCB-E)

MAINDEC—8E-D6CA

200/000

20 passes

A/D Converter (AD8—EA) and

MAINDEC-8E-DBBA

200/000

20 passes

Program Name

DEC

15 min

40 min

Symbolic Tape Editor

Analog Multiplexer (AM8—EA) Test
NOTE: When ordering from Program Library:
PB for Binary Tape
D for Document

2.5.1

}

6.9., after MAI NDEC-8E-DOAA-PB

Central Processor Acceptance Test

Perform the acceptance tests listed in Table 2-25. If abnormal indications are encountered, terminate testing and
refer to Chapter 5 for maintenance procedures. The procedure to load the diagnostic programs is in Chapter 3.
NOTE

Refer to the PDP-8/E Maintenance Manual for information on the Central Processor Acceptance
Test.

2.5.2

Analog-to-Digital Converter (ADS-EA) and Analog Multiplexer (AM8-EA) Acceptance Test

The AD8-EA and AM8-EA options are used in many configurations in the LAB-8/E; the configuration for each

system is determined by the users needs. Table 2-26 shows the different options and the item designations in

Paragraph 2.5.2.1 that contain the procedures to be followed to check each configuration.

2-19

Table 2-26

A/D Converter and Analog Preamplifier
and Multiplexer Acceptance Test

Designation

Option

2.5.2.1

Acceptance Test

—

AD8—EA

A, B

AD8-EA, AM8—ED

A, B

AD8—EA, AM8—EA

A, C

AD8—EA, AM8-EA, AM8—EC

A, C, D

AD8-EA, AM8—EA, AM8—ED

A, C

AM8-EA

A, C‘

DK8—E

DK8-E, VCB-E, VR14 or equivalent

E, F

The following steps will checkout all the configurations of the Analog-to-Digital

Converter and Analog Preamplifier and Multiplexer options.
A.

Control Logic Test
Procedure

Step
Load MAINDEC-8E-D683-PB.

Refer to diagnostic document, for loading instruc—

tions.

Set the switch register (SR) to 0200, depress ADDR LOAD, and then clear the

switch register.

Depress the CLEAR key and then the CONT (continue) key.

\lCDU‘l-bw
3.

When the program halts, set the SR to 0000, then continue.

After each pass, the program will print END OF LOGIC TEST (every 12 sec).
Run the test for 5 min.

Pass if there are no error printouts for the 5-min run.

Accuracy Check

—

AD8—EA
Procedure

Step
1

EnsureW1 and W2 are removed from the A841 module. Connect the Electron-

ic Development Corporation (EDC) precision dc voltage source to the side connector on the A841 in a double-ended configuration as shown in

Figure 2-7.

NOTE
Ensure the connections are properly made, or large
errors may result.

Connect test equipment to the

,processor.

EDC

+<>

PIN LL

*PIN NN

—A841

JUMPER
3 HIE LD

SHIELD

*PIN LL AND NN ARE LOCATED ON THE SIDE CONNECTOR OF THE A841 MODULE.
8E~0309

Figure 27

Analog Inputs for Accuracy Check

2-20

Procedure

Step
2

Connect a ground wire from the EDC voltage source chassis to the computer
chassis.
Load 0202 into the switch register.

Clear the switch register, then depress CLEAR and CONT.
Check the switching points as listed in Table 2-27.
NOTE

Each point must fall within i10 mV of the given
theoretical voltage.

Carefully check that the con-

verter does not triple state.

Table 2-27

Switching Points and Theoretical Voltage Readings

Switching Point

Theoretical Voltage

From

7000

7001

7002

—4.985

7003

7004

—4.966

7007

7010

--4.927

7017

7020

—4.849

7037

7040

-4.692

7077

7100

-4.380

7177

7200

-3.755

7377

7400

—2.505

7777

0000

-0.005

0000

0001

0.005

10 mV

—4.995

0001

0002

0.015

0002

0003

0.024

0377

0400

2.495

0577

0600

3.745

0776

0777

4.985

Pass if all switching points fall within i10 mV of the theoretical voltage and triple

6
.

stating is not observed.
Connect the input as shown in Figure 2-8.
8

Set the EDC voltage source to +5V, then set the polarity switch to —.
a.

The Accumulator (AC)

counts.

Set polarity switch to + position; the AC Register should read 7000
i2 counts.

Accuracy Test

—

AM8-EA
Procedure

Step
1

Connect the EDC voltage source to each channel in succession (see Tables 2-2
and 23).

(continued on next page)
2-21

EDC

><
|

*Pm NN

_A841

SHIELD

PINS LL AND NN ARE

ON A841 SIDE CONNECTOR.
8E 03”)

Figure 2-8

Negative Input Checkout
Procedure

Step

NOTE
EnSure all connections are properly made or large
errors

may occur.

Load 0202 into the switch register.
a.

Set the switch register to 0000.

Depress CLEAR and CONT.

Bits 8—1 1 determine the channel selected.

Check the voltages listed in Table 2-28 for each channel to be within the theoretical
number :2 counts.

NOTE
For AM8-EC panel, test the first four channels with

phone plug removed by rotating the four potentiometers 0, 1, 2, and 3, and reading

70008 to 07778'

Table 2-28

Theoretical Voltage and Reading in the AC
Theoretical AC Reading

Theoretical Voltage

i2 Counts

7000

—

7001

—

7002

—

7004

—

7010

—

7020

—

7040

—

7200

—

7400

—

0000

1.000

0.9981
0.9962
0.9922
0.9844

0.9687
0.9375
0.7500
0.5000
0.0000

0400

+0500

0777

+0998

Pass if all points on each channel fall within i2 counts of the theoretical number.

NOTE
Connect negative terminal to the shield terminal on
the EDC.

(continued on next page)

222

Complex Analog Panel Test
Step

Procedure

Connect the AM8-EC into the A232 module. Do not apply an input to the panel.

Load 0202 into the switch register. Depress ADDR LOAD.

Clear the switch register, then depress CLEAR and CONT.
displaying channel 00.

The AC Register is now

Rotate the potentiometer on the panel for channel 00. Ensure that from one end
of the potentiometer to the other, the AC displays 7000 up to 0777.

Repeat steps 1 through 4 for channels 1 through 3. Select the next channel with
SR8—1 1.
E.

External Start Test

CAUTION
This test is to be performed only if the system con-

figuration contains a DK8-EP clock option that has
undergone prior acceptance testing.
Procedure

Step

Load address 0203 into the switch register. Depress ADDR LOAD.
Set the switch register to 0200, then depress CLEAR and CONT.
The Teletype bell should ring approximately every 4 sec for each pass.

Run test

for 1 min.
4

Pass if no error printout for 1 min.

System Test
CAUTION
This test is to be performed only if the system con-

figuration contains a DK8-EP, a VC8-E, and a VR14
display oscilloscope that have undergone prior acceptance testing.
Procedure

Step
Load 0210 into the switch register.
a.

Depress ADDR LOAD.

Clear the switch register.

Depress CLEAR, then CONT. Program will halt.
Set the desired clock frequency into SW3-5 of the switch register.

Refer to

LAB-8/E programming card for SR setting and frequency.

Depress CONT.
Follow the instructions that are printed out.
a.

For a system with the AD8-EA and AM8-EA, the switch register
would be set to 0107.

(continued on next page)

2-23

Procedure

Step

NOTE
Unless a voltage is applied to every channel, the
sweeps on the oscilloscope will all be in the middle
of the screen.
b.

Depress CONT.

The oscilloscope should show a trace for every channel that the operator selected.
a.

Can have from 1 to 16 traces, depending upon system configuration.

b. The trace vertical position reflects the input voltage to that channel.

2.5.3

Point-Plot Display Control (VC8—E) Acceptance Test

Perform the following steps to set-up the VC8-E, M869, and M885 modules for the acceptance test:
Procedure

Step
1

Set switches on M869 module as follows:
a.

If VR14 is installed, set 2 switch to

if Tektronix 602 is installed, set 2 switch to + and delay switch to S.

if RM503 is installed, set Z switch to + and delay switch to L.

On M885 module, ensure that the W1 jumper is removed and the AB

—

and delay switch to L.

jumper next to W1 is installed if RM503 is used.
2

Reinstall the M869 module into the OMNIBUS.
Connect HO power cable to M869 module unless it is connected to the A231

module on the OMNIBUS.
Turn system power on.

\IOIU‘l-l>
2.5.3.1

Measure the HQ power supply with a precision meter for i15 Vdc (see Table 2-22).
Reinstall the M885 module into the OMNIBUS.
Connect oscilloscope cable if an oscilloscope is installed in the system.

Control Logic Acceptance Test
Procedure

Step
1

Load MAlND EC-8E-D6CA-PB according to the diagnostic document.

Set switch register to 0200.

Depress ADD R LOAD.

Clear switch register.

Depress CLEAR, then CONT.

After the printout is complete, set bit 11, then bit 07, on the switch register.
a.

Teletype will print CONTROL LOGIC TEST.
(continued on next page)

2-24

Procedure

Step

NOTE
The system is now running the Control Logic Test.
b.

After each pass, the program prints CO NTRO L LOGIC TEST. One
'

pass takes approximately 1

min, 50 sec.

Run the Control Logic Test and pass if test runs for 5 min without an error printout.

2.5.3.2

VC8-E Ramp Slewing Test
NOTE

This test is performed only if the system configuration does not include a display oscilloscope option.

Procedure

Step

The diagnostic should still be running (see Paragraph 2.5.2.1); if not, restart the
program.

Set bit 10 to 1, and bit 11 to a 0 on the switch register.

(Tl-PWM

Set bit 07 to a 0, then back to 1.

Teletype will print out RAMP TEST.
Connect an oscilloscope probe from the 453 oscilloscope to the point marked X
on the

M885 module.

The oscilloscope should display a positive-going ramp starting at the —-5V level and

rising to the +5V level, then deflecting full scale and starting again.

See Figure 2-9.

To check the Y output, repeat steps 2 through 6 with bit 01 set to 1.

NOTE
The ramp should be a straight unbroken line. Any
breaks or steps in the ramp indicate the D/A module is not calibrated properly. If display is not cor-

rect, refer to Paragraph 5.4 for calibration procedure.
Monitor the ramp for 1 min.
+5V

0V
‘5V

——*

—: ; ;7A/: j¥; ; ’(/ / ‘/ / /d/ /l\___

____

—__——

BE-OZSS

Figure 2-9 Oscilloscope Display for Ramp Test

2.5.3.3

VCS-E Display Test
CAUTION
Perform this test only if the system configuration
contains a display oscilloscope.

2-25

Crossing Diagonals Display
Procedure

Step
1

Clear the switch register and then set bits 09 and 11 to 1.

Set bit 07 to 1 and monitor printout for CROSSING DlAGONA LS.

On the display oscilloscope, monitor the crossing diagonals. The diagonal lines do
not extend fully from corner to corner.

Ensure that the pattern is in the center of the oscilloscope.

If it is not, perform

calibration according to the procedure for display used with the system.
NOTE

Display sizes refer to approximate size of the display
on a VR14 oscilloscope; size may vary on other oscilloscopes.
'

Horizontal Flyback Display Test
Procedure

Step
1

Ensure diagnostic is still running.

Clear the switch register and then set bits 9 and 10 to 1.

Set bit 07 to 1 and monitor printout for HORIZONTAL FLYBACK.

On the display oscilloscope, monitor the display for four horizontal bars, one in
each corner of the display. Each bar is 1-1/2 in. long and should start in the
corners.

NOTE
If display is not correct, perform appropriate oscil-

loscope calibration procedure.
C.

Vertical Flyback Display Test

Procedure

Step
1

Ensure diagnostic is still running.

Clear the switch register, then set bits 09, 10, and 11 to 1.

Set bit 07 to 1 and monitor the printout for VERTICAL FLYBACK.

On the display oscilloscope, monitor the display for four vertical bars, one in each
corner.

Each bar is about 2 in. long and should start in the corners.

NOTE
If display is not correct, perform the appropriate

calibration for oscilloscope used in the system.

Corners Display Test
Procedure

Step
1

Ensure diagnostic is still running.

Clear the switch register, then set bit 08 to 1.

(continued on next page)

2-26

Procedure

Step

Set bit 07 to 1 and monitor the printout for CORNERS TEST.

On the display oscilloscope, the display will have four diagonal arrows pointing to
the four corners. The head of the arrow starts at the corner and the shaft runs

diagonally toward the center. Each arrow is about 1-1/2 in. long.
corner has an arrow

Ensure each

in it.

NOTE
If display is not correct, calibrate the oscilloscope
with the calibration procedure for oscilloscope in-

stalled in the system.
E.

Diagonal Line Display Test
Procedure

Step
1

Ensure diagnostic is still running.

Clear the switch register, then set bits 08 and 11 to 1.

Set bit 07 to 1 and monitor printout for DIAGONALS.

Monitor the oscilloscope display for a diagonal line running from the lower left
corner to the upper

right corner.

Ensure the line is straight without lines in it.

If the line is not straight, calibrate

the oscilloscope using appropriate procedure (see Paragraph 5.4).
F.

VM EQTW

Step

Procedure

Ensure diagnostic is still running.

Clear the switch register, then set bits 08 and 10 to 1.

Set bit 07 to 1 and monitor printout for VERTICAL BAR TEST.

Monitor the oscilloscope display for a vertical line running from top to bottom and

sweeping left to right across the oscilloscope.
Ensure the line does not have spaces or bright spots in it. If there are spaces or
bright spots, the Point-Plot Display Control D/A module needs calibration.
NOTE

The line may be held at any position on the screen

by setting switch register position 5 1 when performing Vertical or Horizontal Bar Display Test.
The line must be completely scanned before test can
be changed.
=

Horizontal Bar Display Test
Procedure

Step
1

Ensure diagnostic is still running.

Clear the switch register, then set bits 08, 10, and 11 to 1.

(continued on next page)

2-27

Procedure

Step

Monitor Printout for SELECT TEST.

Set bit 07 to 1 and monitor printout for HORIZONTAL BAR TEST.
Monitor the display oscilloscope for a horizontal bar from left side to right side,
sweeping from the bottom to the top of the oscilloscope.
Ensure the horizontal line does not have spaces or bright spots in it.

If it does, the

Point-Plot Display Control D/A converter module needs calibration.

NOTE
If the system contains two VC8-E options, the sec-

ond VCB-E should be set for IOT 615X. When run-

ning the acceptance test for the second VC8-E, bit
06 is set to 1 to tell the program that the second
VC8—E is being tested.

Real-Time Clock (DK8-EP and DK8-ES) Acceptance Test

2.5.4

The following tests will check the Real-Time Clock and the clock panel.

2.5.4.1

Acceptance Tests

DK8-EP and DK8-ES Register Test

Procedure

Step
1

Load MAI NDEC-8E—D8AB-PB.

Follow directions on diagnostic document.

Load 0200 into the switch register.

mumpw

Depress ADDR LOAD, then clear the switch register. Set SWO to 1.
Depress CLEAR, then CONT.
Monitor printout for DK8E CLOCKS DIAGNOSTIC.

After each pass the program will printout DK8E PASS COMPLETE.
Allow the test to run for five passes. Each pass takes approximately 3.5 min.
Pass if five passes are completed without an error printout.
NOTE
If the clock option is a DK8-ES, proceed to Paragraph
2.5.4.2.

External Pulse Test

Procedure

Step
1

Load 0200 into the switch register and depress ADDR LOAD.

Set switch register to 0200 and depress CLEAR, then CONT.

Monitor printout for DK8E CLOCKS DIAGNOSTIC.

(continued on next page)

2-28

Step

Procedure

With the oscilloscope, observe a 40-,us pulse rate at pins FJ2, FJ1, HM1, and HM2
on

the edge connectors which connect the M860 and the M518 modules.

NOTE
Set TIME/DIV to 10 us to observe this signal. Oscil-

loscope synchronization may be difficult; the waveform is aperiodic.

2.5.4.2
A.

DK8-ES Acceptance Test

External Pulse Test

Procedure

Step
1

Load 0200 into the switch register, then depress the ADDR LOAD key.

Set switch register to 0020, depress CLEAR, then CONT.

Monitor printout for DK8E CLOCKS DIAGNOSTIC.

With the oscilloscope, observe a 40115 pulse rate at pins FJ2, FJ1, HM1, and HM2
on

the edge connectors that connect the M860 and M518 modules.

NOTE
Set TIME/DIV to 10 us to observe this signal. Oscil-

loscope synchronization may be difficult; the waveform is aperiodic. Period of pulse is approximately
40 us.
5

Place the oscilloscope probe on the connector labeled OVE RF LOW on the front

panel. Observe a 40-145 pulse rate signal.
B.

External Clock Test

Step

Procedure

Load 0020 into the switch register, then depress ADDR LOAD.

Set the switch register to 0014. Depress CLEAR, then CONT.

Monitor printout for DK8E CLOCKS DIAGNOSTIC.

On the DK8-EF front panel, ground the input CLOCK IN. The Teletype bell
should ring when pass is complete.

WARNING
Never install or remove the 7008492 cable while
power is on. Serious damage to the H724 power
supply transformer may occur as plug is inserted
or removed.

DK8-EF Front Panel Check

Step

Procedure

Plug the test cable No. 7008492 into the 28-Vac receptacle J5 on the processor.
Plug the three phonejacks into the front panel inputs marked IN 1, IN 2, and IN
4. Place SLOPE 1, 2, and 3 switches to the + position.
(continued on next page)

2-29

Procedure

Step
2

Place an oscilloscope probe on OUT 1.
a.

Observe a 60-Hz square wave.

Check OUT 2 and OUT4 for the same square wave.

Place a probe on OUT 1 and a second probe on OUT 2.
a.

Place SLOPE 2 to the

—

position.

b. OUT 2 signal should be 180° out of phase with OUT 1.
4

Place the second probe from OUT 2 to OUT 4.
a.

Place SLOPE 4 to the

OUT 4 signal should be 180° out of phase with OUT 1.

—

position.

OUT 1 and OUT 4 should be in phase. Place the three SLOPE switches
to the + position.

While monitoring OUT 1 on the scope, rotate the appropriate TH RESHOLD poten-

tiometer.
a.

There should be a noticeable movement of the waveform in both ends
of the TH RESHOLD potentiometer movement.

Repeat for OUT 2 and OUT 4. Leave the THRESHOLD potentiometers
at midtravel.

Schmitt Trigger Input Logic Test
Procedure

Step
1

Load 0200 into the switch register.
a.

Depress ADDR LOAD.

Set switch register to 2000.

Depress CLEAR, then CONT.

Monitor printout for DK8E CLOCKS DIAGNOSTIC.

After each pass, the program will printout DK8E PASS COMPLETE.

NOTE
Random errors may be caused by noisy 60-Hz power.
This can be verified by using a single generator set to

60 Hz as the input to the Schmitt triggers.

2.5.5

Allow the program to make five passes. Each pass takes approximately 2 min.

Pass for five passes without an error printout.

Buffered Digital I /O (DR8-EA) Acceptance Tests

The following tests will check the DR8-EA Buffered Digital l/O.

2-30

2.5.5.1

Visual Inspection and Test Setup

Procedure

Step
1

Ensure the A flip-flop jumpers are installed on all 12 bits on the M863 module.

Ensure the W interrupt jumpers are installed on all 12 bits.

Ensure the selected device code is the same as the device code label on the module.
H and L jumpers are used to select device code. See Paragraph 4.5 for more infor-

mation.

2.5.5.2

DR8-EA Acceptance Test Without DR8-EB Panel
Procedure

Step
1

Connect test cable 7008418 (BCOBS) between J1 and J2 on the M863 module.

Install M863 module in the OMNIBUS (see Figure 2-6 for correct location).

Load diagnostic MAINDEC-8E-DOOA~PB (refer to diagnostic document for loading information).
Load 0200 into the switch register.

mum§

Depress ADDR LOAD.
Clear the switch register, depress CLEAR, then depress CONT.
Monitor printout for SET SR, DEVICE CODE, and CONT.

After printout, set the switch register to 00X0. X is equal to 0—7 determined by
the device code label on the module under test.

Monitor printout for SET SR, INTERRUPT JUMPE RS, and CONT.

After printout, set the switch register to 7777 and depress CONT.

Monitor printout for SET SR, F LlP-F LOP JUMPE RS, and CONT.

After printout, set the switch register to 7777 and depress CONT.

Monitor printout for SET SR, RUN, and CONT.

After printout, set the switch register to 0100 and depress CONT.

Allow the test to run for 5 min. After each pass (10 sec), the TTY bell will ring.

Pass if there are no error printouts for the 5-min run.

2-31

CHAPTER 3

OPERATING PROCEDURES

3.1

COMPUTER OPERATION

The LAB-8/E computer allows the operator to manually program the machine using the switch register located on
the programmer’s console. The processor can also be loaded automatically by means of the 33 ASR Teletype

console which contains the paper-tape reader/punch combination, as well as the standard Teletype keyboard.
This chapter defines the operations required to communicate with the processor in both the manual and program

modes.
The user should be thoroughly acquainted with the contents of Chapters 4 and 5 of this manual, and the PDP-8/E
Maintenance Manual, before operating the LAB-8/E System.

3.1.1

Controls and Indicators

Figure 3-1 shows the controls and indicators on the programmer’s console that provide manual control and indicate the program conditions.

The controls on the console provide the operator with the hardware to start, stop,

examine, modify, or continue a program. The controls are switches and keys; the keys are momentary (springreturn) switches.

Figure 3-1

Programmer’s Console

3-1

The indicators on the console provide a visual indication of the machine’s status and current program, the contents of the major registers, and the condition of the control flip-flops.

A lighted indicator denotes the presence

of a binary I in a specific register bit position or control flip-flop.

Figure 3-2 shows the controls and indicators on the standard 33 ASR Teletype console. Table 3-1 describes the
functions of the controls and indicators on both consoles.

Figure 3-2

Teletype Model 33 ASR Console
Table 3-1

Programmer's Console Control and Indicator Functions
Control or Indicator
OF F/POWER/PANEL LOCK

Function
This is a key-operated switch. In the counter-clockwise, or OFF

position, the switch disconnects all primary power to the machine.
In the POWER, or straight up position, it enables all manual con-

trols and applies primary computer power.

In the PANEL LOCK,

position, it disables all keys and switches, with the
exception of the switch register (SR). In this position, a running

or clockwise

program is protected from inadvertent switch operation, and all

panel indicators except the RUN light are turned off.
(continued on next page)
3-2

Table 3-1 (Cont)

Programmer’s Console Control and Indicator Functions
Function

Control or Indicator
SW

When this switch is up, the line on the OMNIBUS line called SW is

high; when the lever is down, the line is low. This switch is used
by special peripheral controls, such as the Bootstrap Loader.
SWITCH REGISTER Switches

These 12 switches provide a means of communication between

operator and machine. They allow a 12-bit word to be input.
When the switch is up, it designates a binary 1 to the machine;

switch down designates a 0. These switches are used during manual
operations or under program control.
Load Address Key (ADDR LOAD)

This key loads the contents of the switch register into the CPMA
and forces FETCH to be set (no major states while ADD R LOAD

is depressed).
Extended Address Load Key

(EXTD ADDR LOAD)

This switch loads the contents of SR6—11 into the Data Field and

Instruction Field Registers of the Memory Extension Control.
SR9—11 goes to Data Field 0—2. SR6—8 goes to Instruction Field
0—2.

Clear Key (CLEAR)

This key issues an INITIALIZE PULSE, clearing the AC, LINK,

interrupt system, and I/O flags.
Continue Key (CONT)

This key resumes the computer program by issuing a MEM START
and setting the RUN flip—flop. The word stored at the address cur-

rently held by the CPMA is taken as the first instruction.
Examine Key (EXAM)

Puts the contents of core memory at the address specified by the
contents of the CPMA into the MB. The contents of the PC and

CPMA are incremented by one to allow examination of the contents of sequential core memory addresses by repeated operation

of the EXAM key.
Halt Switch (HALT)

This switch clears the RUN flip-flop and causes the machine to stop
at T81 of the next FETCH cycle.

This switch is also used for single

instruction stepping.

Single-Step Switch (SING STEP)

This switch clears the RUN flip-flop and causes the machine to
stop at T31 of the next cycle.

Thereafter, repeated depressing of

CONT steps the program one cycle at a time, so that the contents
of registers can be observed in each state.

Deposit Key (DEP)

Loads the contents of the SR into the MB and core memory at the
address given by the current contents of the CPMA. Then the contents of the PC and CPMA are incremented by one. This allows

storing of information in sequential memory address by repeated
operation of the deposit switch.
Indicator Selector Switch

This is a 6—position rotary switch, used to select a register for dis-

play. The six positions are as follows:
a.

STATE

—

Indicates an individual function for each bit:

BitO— FETCH
1—DEFER
2

—

EXECUTE

3-— IRO

(continued on next page)

Table 3-1 (Cont)

Programmer's Console Control and Indicator Functions
Function

Control or Indicator
Indicator Selector Switch (cont)

(cont)
Bit

—

-—

—-

—

11
b.

—

STATUS
Bit

—

|R1
IR2
MD DIR
DATA CONTROL

PAUSE
BREAK IN PROG

BREAK
—

Indicates an individual function for each bit:

LINK

1— GREATER THAN flag
2— INTERRUPT BUS

3— NO INTERRUPT ALLOWED
4- INTERRUPT ON
5

—

—-

—

—-

11
0.

0’.

—

USER MODE

INSTRUCTION FIELD 0
INSTRUCTION FIELD 1
INSTRUCTION FIELD 2
DATA FIELD O
DATA FIELD 1

DATA FIELD 2

Indicates bits 0—11 of the accumulator at TSl.

—

Indicates information just written or rewritten into

memory.

MEMORY ADDRESS

BUS

—

Indicates contents of MO Register during TS1.

Indicates bits 0-1 1 of the DATA Lines.

Indicates the contents of the memory address that will be accessed next.

EMA

RUN Light

Indicates which Extended Memory Field is being accessed.

Machine’s timing is enabled and capable of executing instructions
when lit.

RE L Pushbutton

Disengages the tape in the punch to allow tape removal or tape
loading.

B SP Pushbutton

Backspaces the tape in the punch by one space, allowing manual
correction or rub out of the character just punched.

OF F/ON Pushbuttons

Controls use of the paper-tape punch with operation of the Tele-

type keyboard/printer.

START/STOP/F R EE Switch

Controls use of the paper-tape reader with operation of the Tele-

type. In the FREE position, the reader is disengaged, permitting
the paper tape to be manually moved within the reader without re-

loading or unloading it. In the STOP position, the reader mechanism is engaged but de-energized. In the START position, the reader
(continued on next page)

Table 3-1 (Cont)

Programmer's Console Control and Indicator Function
Function

Control or Indicator

is engaged and operated under program control. The tape may be

START/STOP/FREE Switch (cont)

loaded or unloaded in either the FREE or STOP positions.

Provides a means of printing on paper when used as a typewriter,

Keyboard

and of punching tape when the punch ON pushbutton is pressed;
also provides a means of supplying input data to the computer
when the LlNE/OFF/LOCAL switch is in the LINE position.
Controls application of primary power to the Teletype and data

LlNE/OFF/LOCAL Switch

connection to the processor.

In the LINE position, the Teletype
In the OFF

is energized and connected as a computer l/O device.

position, the Teletype is de-energized. In the LOCAL position, the
Teletype is energized for off-line operation, and signal connections
to the processor are disconnected.

Both LINE and LOCAL use of

the Teletype require that the computer be energized through the

POWER switch.

3.1.2

Keyboard Operation

The Teletype keyboard shown in Figure 3-3
is similar to a typewriter keyboard, except that
some

non-printing characters are included as

upper case elements.

©©OOW®©©
OQGWQG
CQMQQCDQ

For typing characters or

QQQLQO®®®©©

symbols such as $, %, #, which appear on the

SPACE

upper portion of numeric keys and certain

]

““254

alphabetic keys, the SHIFT key is held depressed while the desired key is operated.

Figure 3-3 Teletype Keyboard

Designations for certain non-printing functions are shown on the upper part of some alphabetic keys. By holding
the Control Key (CTR L) depressed and then depressing the desired key, these functions are activated. Table 3—2

lists several commonly-used keys that have special functions in the symbolic language of PD P-8/E systems.

Table 3-2

Special Keyboard Functions
Key
SPACE

Function

Space

Use
Used to combine and delimit symbols or numbers in a symbolic
program.

RETURN

Carriage return

Used to terminate line of symbolic program.

HERE IS

Blank tape

Used for leader/trailer (effective only in LOCAL).

RUB OUT

Rub out

Used for deleting characters, punches all channels on

CTRL/REPT/P

Code 200

Used for leader/trailer of binary program paper tapes (keys must
be released in reverse order:

LINE FEED

Line feed

paper tape.

P, REPT, CTR L).

Follows carriage return to advance printer one line.

3-5

3.1.3

Printer Operation

The printer provides a typed copy of input and output at 10 characters per second, maximum rate. When the

Teletype unit is on-line (LINE), the copy is generated by the computer; when the Teletype unit is off-line

(LOCAL), the copy is automatically generated whenever a key is struck.
3.1.4

Paper-Tape Reader Operation

The paper-tape reader is used to input into memory, data punched on 8-channel perforated paper tape at a maximum rate of

10 characters per second. The reader control positions are shown in Figure 3-2 and are described

below.

3.1.5

START

Activates the reader; reader sprocket wheel is engaged and operative.

STOP

Deactivates the reader; reader sprocket wheel is engaged but not operative.

F R EE

Deactivates the reader; reader sprocket wheel is disengaged.

Operating Procedures

The method used for loading and unloading LAB-8/E information is dependent upon the form of information,
time limitations, and the peripheral equipment connected to the system. The following procedures are basic to
any use of the systems, and although they may be used infrequently as the programming and use of the computer

become more sophisticated, they are valuable in preparing the initial programs and in learning the function of

machine l/O transfers.

3.1.6

Manual Data Storage and Modification

Programs and data can be manually stored or modified by means of the programmer’s console.

Manual data

storage is primarily used to load the Read-ln-Mode (RIM) Loader program into the computer core memory. The
RIM Loader is a program used to automatically load programs into the computer from perforated tape in RIM

format (see Paragraph 3.1.9). Use the following procedures to manually store data in the computer core memory.

3.1.6.1

3.1.6.2

Power For Manual Operation

Step

Procedure

Turn the OFF/POWER/PANEL LOCK switch clockwise to the POWER position.

Memory Addressing for Manual Operation
Procedure

Step
1

Set the SR switches to correspond to the address bits of the word to be stored.

Depress the ADDR LOAD key.

Observe that the address in the switch register is held in the computer as designated

3.1.6.3

by lighted MEMORY ADDRESS indicators corresponding to switches in the 1 (up)
position and unlighted indicators corresponding to switches in the 0 (down) position.

Manual Data Input to Addressed Memory Location

Step

Procedure

Set the SR switches to correspond to the data or instruction word to be stored at
the address just set into the CPMA.

3-6

(continued on next page)

Procedure

Step

Rotate the Indicator Selector switch to MD.
Lift and release the DEP key.
Observe that the data in the switch register is the same as the data shown on the
MD indicators. Data is now stored in the addressed location.
Check to see that the MA has been incremented by one so that additional data can
be stored at sequential addresses by repeated switch register settling and DEP key

operation.
3.1.6.4

Checking the Contents of Any Address In Core Memory
Procedure

Step
1

Perform the memory addressing procedure.

Depress the EXAM key.

01-wa

Rotate the Indicator Selector switch to the MD position.
Observe the data shown on the MD indicators.
To observe the next location in core, the contents of the PC and the CPMA are

automatically incremented by one. The operator depresses the EXAM key and
observes the contents of the new location.

3.1.7

Loading Data Under Program Control

Information can be automatically stored or modified only by using programs previously stored in core memory.
The RIM Loader stored in core memory allows RIM format tape to be loaded as described in the following para-

graphs.
3.1.7.1

lnitializing the System
Step

Procedure

Rotate the OFF/POWER/PANEL LOCK switch clockwise to the POWER position.

Set the Teletype LINE/OFF/LOCAL switch to the LINE position.

Load the tape in the Teletype reader by settling the START/STOP FREE switch
to the F REE position, releasing the cover guard by means of the latch at the right,

loading the tape so that the sprocket-wheel teeth engage the feed holes in the tape,
closing the cover guard, moving the tape eight forward or backward until the
punched leader section is over the read station, and setting the switch to the STOP
position. Tape is loaded in the back of the reader so that it moves toward the
front as it is read. Proper positioning of the tape in the reader results in three bit
positions being sensed to the left of the sprocket wheel and five bit positions being
sensed to the right of the sprocket wheel. The directional arrow printed on the
tape should point toward the operator.
Load the starting address of the RIM Loader program (not the address of the program to be loaded) into the PC by means of the SR and the ADDR LOAD switches.
In sequence, press the CLEAR and CONT keys, and set the 3—position Teletype

reader switch to the START position. The tape is then read automatically.

Stop the computer program by means of the HALT switch when the reader
reaches the trailer section of tape.

3-7

3.1.8

Program Loading Operation

Automatic storing of the BIN program is performed by means of the RIM Loader program, as described below.
With the BIN Loader stored in core memory, program tapes assembled in the program assembly language (PA'L Ill)

binary format can be sorted as described in the previous procedure, except that the starting address of the BIN
Loader (usually 7777) is used in step 4. When the BIN program is loaded, the computer stops. At this point, the

AC should contain all Os if the program is stored properly.

If the computer stops with a number other than 0 in

the AC, a checksum error has been detected. When the program has been stored, it can be initiated by loading
the program starting address (usually designated on the leader of the tape) into the PC by means of the SR and
ADDR LOAD switches, then pressing and releasing the CLEAR key, and then pressing the CONT key.
The steps involved in loading programs and bringing the system to the point where the user can communicate with
the processor is illustrated in Figure 3-4. The loading flow diagram for each type of program to be loaded is ref-

erenced, and each flow diagram is accompanied with a corresponding procedure.
RIM LOADER
LISTING

TOGGLE IN
RIM

LOAD BINARY
LOADER

Bl[“AF'.‘I=BEOG

MACHINE CAN
NOW, ACCEPT
BINARY TAPES‘

SYMBOLIC
ITOR TAPE

1
LOAD

LOAD

m
(I/~

MAKE AND
CORRECT
ACS |l TAPES

OLD TAPE

NEW PROGRAM
l

SYMBOLIC
ASCII TAPE)

ASSEMBLE
PROGRAMS
1
PASS
PASS 2

LOAD

______________

SYMBOL
TABLE TAPE

BINARY
OBJECT TAPE

PAL III is used to translate symbolic Programs
into binary-coded Programs (binary Programs)

RUN NEW
PROGRAM
PASS 1
PAL reads the symbolic Program Tape and de-

Instructs computer to receive and store in
core, data punched on paper tape in RIM

The Editor Program is punched out on paper

fines all symbols and places these user symbols

tape in binary coded format. It is loaded into

in a symbol Table for use during PASS 2 PAL

using BIN loader.

checks for undefined symbols and other errors.

core memory

coded format.
The symbolic Editor is a service Program

PASS 2

Instructs the computer to read binary-coded

which allows the user to Write and prepare

PAL rereads the symbolic Program tape and

data punched on paper tape and store it in

symbolic Programs and to generate a symbolic
program tape of his Programs.

generates the binary Tape using the symbols

core

memory.

Figure 3-4

defined during PASS 1..

BE- 0265

Loading Data Under Program Control

This loading procedure is greatly simplified when the user employs a mass storage device such as the Disk Monitor

System. Using the monitor, stored programs are called in from disk files. This is illustrated in Figure 3-5.

3-8

/——

Bootstrap is used to bring in the monitor
Program from DISK_

LOAD BOOTSTRAP

CALL

BOOTSTRAP

IN MONITOR

THE DISK SVSTEM EDITOR

CALL IN

MONITOR

DISK

EDITOR

symbolic programs online from the
Teleprinter Keyboard.

The user may now type in his own Source

INPUT
PROGRAM
AND
STO RE

E D ITOR

enables the user to generate and edit

Pr"9'6""-

PALD assembles the source Program statements

CA LL IN

M 0 N ITOR

PAL

DISK

by translating mnemonic operation codes into binary
codes needed in machine instructions, relating symbols
to numeric values, assigning absolute core addresses

for Program instructions and data, and preparing an
output Listing of the Program which includes notification
of any errors detected during the assembly Process.

CALL
STO R E D
PROGAM

DISK

PA L
PA 8 S 1
PA S S 2

ASSEMBLED

DISK

P R0 G R A M

LOAD

MONITOR

SAVE ,STORE

LOAD, SAVE & STORE
COMMANDS enables the user to write core images

P R06 R AM

of system or user Programs from core onto his

U SE R
INPUT

I N

C0 RE

system device for subsequent call-in (CALL) and
.

execution.

0 UT PUT
BE- 02 3 2

\_/—\

Figure 3-5
3.1.9

Loading Programs with Mass Storage Devices

Loaders

When a LAB-8/E System is first received, it should be assumed that no useful information is in memory. The

system can not perform any arithmetic operations or receive data.
Because all tapes in the Program Library are written in binary format, the user must load the system so that it can

accept binary tapes.

Initially 16 RIM instructions are manually toggled into memory. The BIN Loader tape is

then used to eliminate the necessity of toggling in 86 additional instructions.
RIM allows the BIN Loader tape to be read into memory; and BIN, in turn, allows the use of any tape in the Program Library, such as a symbolic editor.

3.1.9.1

Read-ln-Mode (RIM) Loader

—

The RIM Loader, the first program loaded‘into the system, is loaded by

the programmer using the console switches. The RIM Loader instructs the computer to receive and store in core,
data punched on paper tape in RIM-coded format. The RIM Loader is used to load the BIN Loader described in

Paragraph 3.1.9.2.

3-9

There are two RIM Loader programs:

Table 3-3

is used when

one

RIM Loader Programs

the input is to be from the low-speed paper-tape reader;
the other is used when input is to be from the high-speed

Instruction

paper-tape reader. The locations and corresponding in-

Location

Low-Speed

High-Speed

Reader

7756

6032

6014

7757

6031

6011

7760

5357

structions for both loaders are listed in Table 3-3.
The procedure for loading (toggling) the RIM Loader

into core is illustrated in Figure 3-6.

lNTlALlZE

USING
EXTENDED

MEthRY

YES

SET*
DF-DESIRED FIELD
IF= DESIRED FIELD

7761

6036

6016

7762

7106

7763

7006

7764

7510

7765

5357

5374

NO
SET SR= 7756

DEPRESS
LOAD ADD
*DEC TAPE USERS SHOULD
LOAD RIM INTO FIELD O

7766

7006

7767

6031

6011

7770

5367

7771

6034

6016

7772

7420

7773

3776

7774

3376

7775

5356

5357

7776

0000

YES
SET SR FIRST
INSTRUCTION
=

DEPRESS

DEP

lllflfiflflflillb

SET SR= NEXT
INSTRUCTION

DEPRESS

DEP

USING
EXTENDED

MEM?ORY

SET

DF'CORRECT FIELD
I F-CORRECT FIELD

ALL
INSTRUCTIONS
IN

SET

SR-7756

YES
RIM IS LOADED

DEPRESS LOAD ADD
8E-0267

Figure 3-6

DEPRESS

EXAM

Loading the RIM Loader

After RIM has been loaded, it is good programINSTRUCTION
?

ming practice to verify that all instructions were
stored properly. This can be done by perform-

SET SR= MA

ing the steps illustrated in Figure 3-7, which
also shows how to correct an incorrectly-stored

DEPRESS LOAD ADD

instruction. When loaded, the RIM Loader oc-

cupies absolute locations 7765 through 7776.

INSTRUCTIONS
SET SR = CORRECT
INSTRUCTION

DEPRESS DEP

CHECKED
?

RIM IS LOADED
BE-023l

Figure 3-7

3-10

Checking the RIM Loader

3.1.9.2

Binary (BIN) Loader

-—

The BIN Loader is a short utility program which, when in core, instructs the

computer to read binary-coded data punched on paper tape and store it in core memory. BIN is used primarily
to load the programs furnished in the software package (excluding the loaders and certain subroutines) and the

programmer’s binary tapes.
BIN is furnished to the

programmer on punched paper tape in RIM-coded format. Therefore, RIM must be in

core before BIN can be loaded.

Figure 3-8 illustrates the steps necessary to properly load BIN.

When loading,

the input device (low- or high-speed reader) must correspond to the version of RIM loaded in the machine. When

stored in core, BIN resides on the last page of core, occupying absolute locations 7625 through 7752 and 7777.

oUSING
EXTENDED

YES

MEthRY

SET *
DF=CORRECT FIELD
IF=CORRECT FIELD

NO
SET SR

7756

DEPRESS LOAD ADD

WHICH

HIGH-SPEED READER

LOW SPEED READER

READER
?
PUT BIN TAPE
l
HSR

T U RN TTY T0 L lNE

DEPRESS START

READS

PUT LSR TO FREE

PUT IN TAPE
'N LSR

P UT L S R

T O S TART

YES

HSR STOPS AT
END OF TAPE

DEPRESS START

TAPE
READS IN
?

YES

LSR STOPS AT
END OF TAPE

DEPRESS START
*SAME FIELD
AS RIM

SETTINGS

REMOVE TAPE
FROM READER

BIN

Figure 3-8

LOADED

Loading the BIN Loader

BIN was purposely placed on the last page of core so that it would always be available for use in DEC’s software

package. The programmer must be aware that if he writes a program which uses the last page of core, B IN will be
destroyed when that program runs. When this happens, the programmer must load RIM, and then BIN, before he
can

load another binary tape.

Figure 3—9 illustrates the procedure for loading binary tapes into core.

3-11

o—
USING
EXTENDED
MEMORY
?

SET
DF=DESIRED FIELD
lF=FlELD OF BIN

YES

SET SR=7777

DEPRESS LOAD ADD

HIGH-SPEED READER

WHICH

LOW SPEED

READER

?
SET SR= 3777

TURN TTY TO LINE

PUT TAPE IN HRS

PUT TAPE IN HSR

SET LSR TO START
DEPRESS START

TAPE
READS IN

?
YES

TAPE STOPS
AT BEGINNING OF
TRAILER'TAPE

YES

DEPRESS CONT

YES

END

or TAPE

?
YE S

OBJECT TAPE
IS LOADED
8E-0234

Figure 3—9
3.1.10

Loading a Binary Tape Using BIN

Off-Line Teletype Operation

The Teletype can be used separately from the computer for typing, punching tape, or duplicating tapes. The

following procedures will enable the Teletype'to be used in this manner:
Procedure

Step
1

Ensure that the computer OFF/POWER/PANEL LOCK switch is positioned to the
PANE L LOCK position.

Set the Teletype LlNE/OFF/LOCAL switch to the LOCAL position.

(continued on next page)

3-12

Procedure

Step

If the punch is to be used, load it by raising the cover, manually feeding the tape

from the top of the roll into the guide at the back of the punch, advancing the tape

through the punch by manually turning the friction wheel, and then closing the
cover. Energize the punch by pressing the ON pushbutton, and produce about 2 ft
of leader. The leader-trailer can be code 200 to 377. To produce the code 200
leader, simultaneously press and hold the CTRL and SHIFT keys with the left hand,
press and hold the REPT key, and press the ## (P) key. When the required amount
of leader has been punched, release the ## (P) key, and then all keys. To produce
the 377 code, simultaneously press and hold the REPT and RUB OUT keys until a
sufficient amount of leader has been punched.
3.2

DISPLAY SYSTEM OPERATING PROCEDURES

The following paragraphs deal with the operation and use of the LAB—8/E display options. The user must be

familiar with the controls and adjustments to effectively use the displays. Guidelines for VC8—E interface with

oscilloscopes are in Paragraph 3.2.2. Refer to the appropriate manual for more display information.
3.2.1

VR 14 Display Operation

The VR14 is supplied either as a standard Retma 19 in. x 10—1/2 in.

Table 3-4

101/2 in. rack-mounted unit, or as a table-top model with its

VR14 Input Voltages

own

decorator cover (see Figure 3—10). The VR14 can operate

De5|gnatlon Letters

Line Voltage

VR14C

115 Vac

3—4). The VR 14 can be made to operate with any of these vol-

VR14AD

230 Vac

tages; refer to the VR 14 user’s handbook for instructions to change

VR14BE

100 Vac

With a power line frequency of 47 to 63 Hz. The input line vol-

tages are specified by the letter designation after VR 14 (see Table

jumpers for different voltage inputs.

rncamu

‘9
1S

Figure 3-10

VR14 Display Oscilloscope

313

Equipment cooling is the most important VR14 installation requirement. There should be sufficient space below
and behind the unit for fans to draw air from the bottom of the unit and for air to exit behind the unit.

The controls and connections necessary for operating the VR 14 are shown in Tables 3-5 and 3-6.

If the VR14

oscilloscope requires calibration or internal adjustment, refer to the VR14 manual for adjustment and calibration
procedures.
Table 3-5
VR 14 Controls

Function

Controls

Location

ON/OFF/B R IGHTNESS

Front Panel

Turns on input power and adjusts brightness of display
when turned cloCkwise.

CHANNEL Select

Selects channel 1, channels 1 and 2, or channel 2. When in

Front Panel

the 1 and 2 position, channel will be selected by instructions to control display.

X-slide switch

Rear Panel

Selects polarity of the X-channel input signal by switching
BNC connectors.

Y‘slide switch

Selects polarity of the Y-channel input signal by switching

Rear Panel

BNC connectors.

Table 3-6
Unit Top Panel Control Settings*

In p ut Deflection

Position Settin g

Rear

Polarity Switch

i2V to 5V

With no inputs, set position

Down

0, 0

X and Y to center (0V

(-)

center

i2V to 5V is up

at A02—A

(for X) A03-A

and to right

(for Y))

0V to +2V to +5V

With no inputs, set -2.2V

0, 0

@ A02-A,

upper right

A03-Agwith X-

Up
(+)

and Y-position potentio-

screen

meters

OV to -2V to -5V

0, 0

lower left

With no inputs, set +2.2
Vdc @ A02—A A03-A with
X- and Y- position poten-

tiometers
*

Refer to VR14 manual.

NOTE
All signals are +BNC with respect to ~BNC. Revers-

ing input connections is the same as reversing the
polarity switches. A|| single-ended signals applied to +BNC must have —BNC tied to signal-source
ground. The negative signals are automatically
grounded when the BC01K cable is inserted in rear
panel connector.
rear

3-14

Up
(+)

Guidelines for VC8-E Interfacing for Oscilloscopes and XY Plotters

3.2.2

The VC8-E Display Controller was designed to accommodate the VR 14, Tektronix 602, and the RM503 oscillo-

However, with certain modifications, the VC8-E can interface to many other oscilloscopes and plotters.

scopes.

The responsibility for interfacing with other oscilloscopes lies with the user. The following guidelines must be
considered before attempting to control an oscilloscope that has not been specified by DEC.

Intensification Pulse

3.2.2.1

—

The VC8-E can supply a Hts pulse width; however, to avoid reflection on long

cables, a 200-115 rise time (fall time if negative) is incorporated into the pulse width. Therefore, the width is defined from the start of the pulse to the completion.

Many oscilloscopes, other than the ones mentioned above, require longer pulse widths. As an example, some
storage oscilloscopes require approximately a 5- to 6415 pulse width. The VC8-E cannot accommodate such

oscilloscopes unless the user changes the 1-us pulse generator (on M869) to a larger value. This would require

changing the capacitor to another value which is appropriate to the user's application. All oscilloscope manuals
should define pulse width.
The VC8-E contains provisions to change the polarity of the output signal by a switch or by the M869 module.

Improper value of the intensity polarity will result in signal blanking at the wrong times. (Retraces may be seen.)
The VC8—E can generate pulse voltages from +4V to -2V. With the removal and addition of certain jumpers on
the M885 module, it can also generate a +4V to -10V voltage swing; however, note that the rise and fall times
will be greater.

In many cases, the intensity pulse input requirements to various oscilloscopes are 0V to 1V. An

external adjustment on the oscilloscope or a special attenuating network must be used. This is the user’s respon-

sibility and must be considered before attempting to interface. As in the case of the Tektronix 602, DEC offers
a VM03 kit which

includes mounting hardware, and attenuating resistors and capacitors to be applied to the 602.

The Tektronix 602 has provisions in its circuitry for the addition of external components; however, this may not
be true of other oscillosco pes.

X and Y Outputs

3.2.2.2

—

The voltages generated by the X and Y outputs of the VCB-E are i5V; this cannot

be modified. The user must have external attenuators or an internal oscilloscope gain adjustment. Note that
many oscilloscopes call for only positive voltage swings; however, an offset position can usually be adjusted to
correct input polarity problems.

The VC8-E is an oscilloscope control and not a D/A converter. The settling time from maximum deflection is
4 us.

Many oscilloscopes have settling times faster than 4 us. In this case, the user should use the internal delay

set by the option at its minimum value (6 us).

Oscilloscope settling times may vary from 1 us to 50 us. A DONE flag will occur when either oscilloscope has
reached its settling time; Le, 20 us for the VR14, and 6 us for the Tektronix 602. Note that all oscilloscopes
differ somewhat in settling times. The user must determine if the VCB-E time delay is adequate for his oscilloscope.

For slow oscilloscopes, software delays may be incorporated in the system or the user may change the

20-ps delay circuit by adding a larger capacitor.
3.2.2.3

Drive Capabilities

—

Cabling should be carefully selected. The X and Y outputs are capable of driving

loads greater than 1K in parallel with 5000 pF of capacitance; e.g., 100 ft of cable at 50 pF/ft.

3.2.2.4

External Controls

—

The VR 14 has a 2-channel input whereby the user can select a channel by setting a

bit in the Status Register. This signal is usually not used by other oscilloscopes; however, the user may be able to
use

it as a pen-up, pen-down capability on an X/Y plotter. The output signal is 0 to +5V with a 10-mA source and

a 30—mA

sink current. This bit can also be used as a signal for partially controlling a storage oscilloscope.

3—15

3.2.2.5

Ground Loops

—

The analog signals present at the output of the VCB-E are the ANALOG VOLTAGE,

the ANALOG GROUND, and the LOGlC GROUND (shield). When using differential inputs, the ANALOG

VOLTAGE and ANALOG GROUND must be used.
When using single-ended inputs, use only ANALOG VOLTAGE and LOGIC GROUND. Do not connect the
ANALOG GROUND to the SYSTEM GROUND.

3.2.2.6
a.

VCS-E Restrictions
The VC8—E cannot fully control storage oscilloscopes; it can only plot points.

b. The VC8-E can use two different IOT device codes: 05 and 15.
0.

Maximum of two VC8-E controllers in one system.

316

CHAPTER 4

PRINCIPLES OF OPERATION

This chapter presents the theory of operation of the LAB-8/E System and of the options that have been added to
the PDP-8/E to form the LAB-8/E. The options are presented in three levels of discussion.
block diagram presenting the primary parts of the option is discussed.

First, a simplified

Second, a block diagram relating instruc-

tions to time states is presented and discussed with appropriate references to the third level discussion. The third

level discussion presents logic theory and is divided into functional groups of logic.

Chapter 4 is divided into seven sections:

one

section for system operation, and one section for each option.

Section 1

System Operation

Section 2

An-alog-to—Digital Converter (ADB-EA)

Section 3

Analog Preamplifier and Multiplexer (AM8—EA)

Section 4

Point-Plot Display Control (VC8—E)

Section 5

Buffered Digital Input/Output (DR8-EA)

Section 6

Real-Time Clock (DK8-EP or DK8-ES)

Section 7

High Quality Power Supply

This sectional format is provided to aid the user in understanding the principles of operation and to distinguish the
individual parts or circuits of each option.
NOTE
The component designations are for reference only

and do not necessarily correspond to those designations on Engineering drawings.

4-1

SECTION 1

SYSTEM OPERATION

4.1

INTRODUCTION

The LAB-8/E System (see Figure 4-1) consists of the PDP-8/E processor and memory, a 33 ASR Teletype, and
the following options which plug into the OMNIBUS or are mounted in the equipment rack or expansion box:
a

Analog-to-D igital Converter (ADS-EA)

Analog Preamplifier and Multiplexer Expander (AM8-EA)

Point-Plot Display Control (VC8—E)

VR14 or Tektronix 602 Displays (mounted in equipment rack, expansion box, or placed in the
area of the

LAB-8/ E)

Buffered Digital I/O (D R8—EA)

Real-Time Programmable Clock (DK8-EP)

HQ Power Supply (mounted in expansion box or in back of equipment rack)

The LAB-8/E can be operated in many configurations using one or all of the options listed, depending on the
users application.

The system can be expanded at a later date to include all the options shown in Figure 4—1. To

expand the system, the user need only insert modules and connect necessary cables and edge connectors (see
Chapter 2 for installation and test procedures).

REAL
TIME
CLOCK
mm

SCHMITT

TRIGGER—fl

INPUT

/D
START

ANALOG
PREAMPLFIER
AND
MULTIPLEXER

A/D
CONVERTER

CHANNEL SELECT

DIGITAL
DATA

CENTRAL
PROCESSOR

PROGRAMS
FROM

MENNODRY

RsEvéIET’ER

(PDPa/E)

DIGITAL
DATA
OUT

CONTROL

TAPES
AND
PAPERTAPES

INSTRUCTIONS

(ADS/E)

INSTRUCTIONS
—

POINT
PLOT
DISPLAY

VR14
TEKTRONM

(VC8/E)

USERS
OSULLOSCOPE

DIGITAL
DATA
IN

BBfGfiTELED

33 ASR
TELETYPE

DATA

1,0

—_—.

DIGITAL DATA OUTPUT

(DKa—EA)

DIGITAL
DATA INPUT
8E-0340

Figure 4—1

LAB-8/E Block Diagram

4.1.1

Analog Data Input to the A/D Converter

The A/D converter can be used in the LAB-8/E with one input to a side connector on the A841 module; or the

system can be expanded using the AM8-EA Preamplifier and Multiplexer Expander option (see Figure 4—1). One
AM8—EA will supply 8 channels of analog data; an additional module will expand the system to 16 channels. The
AM8—EA receives iIV inputs through a cable tied to a side connector on the A232 module, or from an analog

panel and cable assembly. The AM8-EA supplies its i5V output to the A/D converter through H851 Edge Connectors which connect the output of the AM 8-EA to the A/ D converter. The AM8-ED (simple analog panel) or

AM8-EC analog panels can be used to supply inputs to the AM8-EA. The AM8—ED is a single-width front panel
to mount on the H945 option cabinet. The AM8-ED has a DEC 25-pin (DB-25S) receptacle and a matching plug

(DB-25F) to provide 16 analog inputs to the AM8-EA. The AM8-EC provides four potentiometer inputs for
channels 0 through 3. Channels 4 through 17 octal are available on a 25-pin connector, as in the AM8—ED. Four

phone jacks are provided to disconnect inputs from the potentiometers and to utilize channels 0 through 3 as

analog channels. Note that there are several ways to supply inputs to the A/ D converter and that the LAB-8/ E
can be

expanded from a 1-channel system to provide for 16 channels of analog data by adding 2 AM8—EA modules.

4.1.2

A/D Converter (ADS-EA)

The AD8—EA (see Figure 4-1) is a 10-bit successive approximation A/D converter. The option is contained on the

A841 and A231 quad modules which plug into the OMNIBUS. The A841 module contains analog circuitry, in

cluding A/D weighing switches and comparator, sample and hold, and an Analog Input Buffer.

The A231 module

contains all control logic for the A841 module; the modules are tied together by an H851 Edge Connector. The
AD8—EA can have a single bipolar input or it can be multiplexed to provide 16 channels of data. The analog input
is converted to 10 bits of digital data in 2's complement form to be transferred to the AC by programmed instructions. The digital data in the AC can be displayed, stored, or transferred to another system, as the user requires.

Inputs to the A/D converter from the Real-Time Clock (see Figure 4-1) can be used to start an A/D conversion
and, under program control, set up sampling rate and determine the number of samples to be taken.

A detailed

discussion of the A/D converter is contained in Paragraph 4.2.

Figure 4—2 is a flow chart of the programmed instructions used to monitor and control an A/D conversion. These
instructions will also provide enabling signals for Interrupt and Skip logic, and for selecting alternate methods of

starting the A/D converter. See Paragraph 4.2 for a detailed description of instructions used in the AD8-EA, the
AM8-EA, or the DK8—EP.
DK8—EP,
4.1.3

Note that the only interaction between modules is between the AD8—EA and the

AM8—EA; all other options interact only through the central processor by programmed instructions.

Buffered Digital I/O (DR8-EA)

The DR8—EA Buffered Digital I/O provides 12 digital inputs to the LAB-8/E and 12 digital outputs to the outside

world. The DR8—EA is contained on an M863 quad module installed in the OMNIBUS. The system can be ex-

panded to include a maximum of eight modules. Inputs and outputs can be supplied directly to the M863 module

through cables or a DR8—EB panel. The DR8-EB panel has two M904 modules to connect signals from the outside world to the panel. Two BC08J cables are used to connect to the M863 module when the panel is not used.
A diagnostic jumper cable is provided to jumper input to output for troubleshooting and testing of the D R8—EA.

See Paragraph 4.5 for a detailed discussion of the DR8-EA.

Figure 4-3 is a flow chart of the Buffered Digital I/O instructions.

These instructions provide the means to clear

and set the registers, and to transfer the contents of the l/O Register to the AC.

provided to generate an
assert the IN flag.

INTER RUPT ENABLE is also

Interrupt request when an input is applied to the digital I/O from the outside world to

X299
N0|l3n8.LSN|
Z'b

]
ovaa snnus 831.8!938 03:!)

‘

OJ.|8
l
O

3NOCl
.L3S

’

tile

I
j

8V3'IO
mama
81LS|938

8V3“
SILLVLS

83LS|938

avz-m
xnw
ususmaa

H-BJJS

£299 (W‘IOV)

Z299 (.LSCIV)

ave-1 xnw 83.LS|938
HJ.|M 3v u-s o;
133139 xnw 13NNVH3

avz-no 9leu aoaaa

01-80

I
amino an; 3NOG

SLL

8V3—IQ
CI/V 3NOG

avano a/v
3NOCl
svu

7 5V

swims

G3L83ANOO SI
canvas A8
xnw answau

80883
SI 1.39

|
.IJEI l=9 .LN3W380NI XfllN
N3HM
3NOCl

I W299] [(MSCIV) 9299]

(380V)

a/v aaasna

ow—
G/V

J.8VJ.S a/v NOISHEIANOZ)
13NNVH3 01 38

”0333

9N||NIL

J
L

2299 (880V)

0 l

0N
3NOCl
G38V313
SNIWLL
80883
CI/V .LON
31318WOO

4-5

0299 ('IOCIV)

3NOO

DNIWLL 80883

LNT—T

.L,NOG dIMS J.X3N

NOLLOntLLSNII

dlMS .LX3N
NOIlOnHiSNI

Lmri

XflW 83LS|938
3V “-8
SAL-80 S'IEINNVHD

.L,NOCl dIMS .LX3N
NOLLOn8.LSNI

9299

dlMS .LX3N
NOLLOn8.LSNI

(310V)

GVOW 318VN3 83.131938
HUM 3V 9-2

9.1.]

318VS|C|
.Ldn883.LNI
N0 G/V
3NOO

318VN3
.Ldfl883lNI
N0 O/V
3NOCl

8V3’IO
.Ldn883J.NI
318VN3 NO
9N|WLL
80883

138 .Ldn883lNI
318VN3
N0 9NlW|.L
80883

8V3'13 318VN3

1VN83iX3
.L8V.LS

J.3S 318VN3
'IVN83.LX3
1.8113

Ll—m—J

8V3‘IO omv

J.N3|N38DNI
3-8WV Nl
OanNON
.LN3IN383NI
300w

1.38 .LNBW380NIOM'IV
300W 3-8WV 'I'IIM
38 138 Cl J.X3N
13NNVH3 NI
30N3n038 NO O/V
3N00

2220-38

amfiH 3-17

g/V Jaye/moo MOH 1.1qu

65XX

4.5

I 65X0lDBDI)J I 65X1(DBEI)I I65X4(DBRI)I I ssxzmesfi I 65X3(DBLI)I I 65x7(DBRO)I L65x5IOBCOII I 65X6(OBSOII
ENABLE

SKIP ON
INPUT
FLAG"

INTERRUPT
0N INF’UT
FLAG

OUTPUT REGISTER-’AC

ONES IN

OUTPUT

SET

DISABLE

ONES IN

INTERRUPT
ON INPUT
FLAG

INPUT REGISTER—>Ac

CLEAR

ONES IN

RESPECTIVE BITS

CLEAR

RESPECTIVE BITS

IN THE INPUT

IN THE OUTPUT

8E-0323

Figure 4-3
4.1.4

Buffered Digital l/O Flow Chart

Real-Time Programmable Clock (DK8-EP)

The Real-Time Programmable Clock consists of two quad modules that plug into the OMNlBUS and are intercon-

nected by an H851

Edge Connector. The M860 module, Real-Time Clock Control, contains control logic. The

M518 module contains input logic and Schmitt triggers. The DK8—EP provides a programmable time base that
allows the user to record and/or control the occurrence of internal and external events. The Real-Time Clock can
be used in the LAB-8/E to Start an A/D conversion and, under program control, set up sample rates and control

the number of samples taken. Note that the Schmitt triggers can also be used to control the A/D converter since

they are threshold detectors that trigger when a signal reaches a certain level. The DK8-EF clock panel can be
added to supply external clock inputs and to set up Schmitt trigger threshold levels. The DK8—EP panel provides
three adjustable inputs to the Schmitt triggers and slope switches to Change the direction of the triggering on the

input Signal. See Paragraph 4.6 for a detailed discussion of the clock.

Figure 4-4 is a flow chart showing the instructions used by the DK8-EP and their functions to control clock operation. The instructions will set up the mode of operation and generate signals to control external devices or options
in the LAB-8/E (A/D converter). See Paragraph 4.6 for an explanation of the instructions.

4.1.5

Point-Plot Display Control (VC8-E)

The VC8—E Point-Plot Display Control converts 10 bits of digital data in 2’s complement form ($07778) to :5
Vdc analog signals. The $5 Vdc signal is applied to the deflection circuits of an oscilloscope; an intensity pulse

generated by the VC8—E will intensify a point on the oscilloscope.

A series of points can be plotted on the oscillo—

scope to produce a graphical display of X and Y coordinate data.

The VC8—E comprises the M869 control module and the M885 module with analog circuits and switches. These
modules plug into the OMNIBUS and interface with each other by H851

Edge Connectors. The input to the

VC8—E is from the AC in the central processor and the output is supplied by a 7008499 cable. A BC01 K cable
will be supplied if the VR 14 is used; if the Tektronix 602 is ordered, a BC01L cable will be supplied. The RM503
user will

require a 7008491 cable.

The VC8-E is controlled by programmed instructions from the central processor.

Figure 4-5 is a flow chart of

VCB-E instructions (see Paragraph 4.4 for a list of instructions). The instructions applied to the VC8-E will load
the X and Y Holding Registers, Enable Registers, and will generate Skips or Interrupts to control the display of
data.

613x
INSTRUCTION
4.7

6130(CLZE)

6131(CLSK)

AC—> CHECK

SKIP ON CLOCK

CLOCK

ENABLE

INTERRUPT

COUNTER

6133 (CLAB)

6135(CLCA)

6136 (CLBA)

6137 (CLLA)

CLOCK ENABLE

STATUS REGISTER

CLOCK BUFFER

CLOCK COUNTER

-—>

6I34 (CLEN)

ONES IN Ac

SKIP

CLEAR RESPECTIVE

ENABLE REGISTER

BITS

INSTRUCTION
.

DON T

6132 (CLOE)

SKIP
NEXT

L17

INSTRUCTIONS

AC _. CLOCK
ENABLE
REGISTER

I
BIT o

T
BIT 1 AND 2

I
BITS 3.4,AND 5

BIT 6

BIT 7

BIT 8

MODE ENABLE

RATE ENABLE

CLOCK ENABLE

(SEE TABLE 4-9)

(SEE TABLE 4—9)

INTERRUPT

I
BIT 9
ENABLE
EVENT 9
1

ENABLE

ENABLES

DISABLES

DISABLE

ENABLE

DISABLE

ENABLE

AND SKIP

INTERRUPT

CLOCK

EXTERNAL

CLOCK

INTERRUPT

DISABLE

ON OVERFLow

COUNTER

START

PULSES T0

PULSES To

REQUEST

COUNTER

LOGIC

OVERFLOW

l
BIT 11
ENABLE

l
BITIO
ENABLE

EVgNT111

EYDENTRO

DISABLE

ENABLE

ST?

TO GENERATE
EXTERNAL
START TO ADBE

DISABLE
ST4

ENABLE
ST4

DISABLE ENABLE
ST‘I
STI
650325

Figure 4-4

Real-Time Programmable Clock Flow Chart

605x

INSTRUCWON
4.4

6050(DICL)

6051(DICD)

6052(DISD)

CLEAR ALL LOGIC

6053(DILX)

[6054(DILY) I

[C055(DIXY)|

CLEAR DONE

DONE

CLEAR

DONOT fiflP

sxu=

DONE

INTERRUPT

CHANNEL

DONE

GO TO NEXT

ENABLE

SELECT

FLAG

INSTRUCHON

CLEAR

NOT
x

LOAD

LOAD Y

INTEN$FY

SET DONE

DONE
SET DONE

8'?

6056(DILE)

6057(DIRE)

LOAD ENABLE
REGISTER erH AC

TRANSFER ENABLE STATUS
REGISTER CONTENTS T0 AC

BrT11
O

SET

CHANNEL

INTERRUPT

NOE
SELECTED

ENABLE

NSPLAY

CLEAR

CHANNEL

INTERRUPT

No.1

ENABLE

CHANNEL

No.1

No.2

DONE=0

DONE=1

(CLEARED)

(SET)

INTERRUPT
ENABLE=0

ENABLE=1

(CLEARED)

(SET)

INTERRUPT

8E—0324

SELECTED

Figure 4—5

Bn11

BIT10

BH'O

mspLAY

’j

BIT1O

Point-Plot Display Control Flow Chart

4.1.6

33 ASR Teletype

The 33 ASR Teletype, used as an l/O device, enables the user to load programs into the LAB-8/E System from
control and program tapes.

Operation and maintenance information for the Teletype is presented in Volume 1

of the PDP-8/E Maintenance Manual.
In addition to using the 33 ASR Teletype as an l/O device, the user can also program the LAB—8/E using the

switch register on the operator’s console. There are several short programs in Paragraph 5.1.1 that may be used

for troubleshooting and maintenance (see Chapter 3 for loading procedures).

4.1.7

HQ Power Supply

The i15 Vdc HQ power supply provides high quality power to the LAB-8/E options. The output of the power

supply is tied to the AD8—EA or VC8—E by a cable and is distributed to the other modules through H851 Edge
Connectors.

4—9

SECTION 2

ANALOG-TO-DIGITAL CONVERTER (AD8-EA)

4.2

INTRODUCTION

Figure 4-6 shows a block diagram of the A/D converter. The l/O panel receives analog voltages which are fed to
the analog preamplifier and multiplexer. Two AM8—EAs can be added to expand the system to 16 channels. A

single bipolar input can be supplied to the A/D converter by an edge connector from the AM8-EA, or by a cable
to a Berg connector on the A841 module.

The AM8-EC and AM8—ED analog panels can be installed in the equip-

ment rack to supply inputs to the AM8-EA or the A841 module (see Paragraph 2.2.1).

INTERNAL
I/o L

MD3-MDoa

DEVICE
SELECT

CONTROL
OPERATION SIGNALS
MOS-11
SELECT
_____.‘
,

|—-+

C0 c1
,

CONTENTS or STATUS, ENABLE,AND MULTIPLEX

GATING AND
CONTROL
LOGIC

DIGITAL

CONTROL

CHANNEL SELECT
(MUX BITS 8,9,10,11)
PREAMP

ANALOG
pANEL
AM8-EC

fixELE/é

+ “gUé-Jfkfi’e‘fg

gfiéggg SAMPLE

1 0F8

PREAMP

AND
HOLD

we-“

was...

”OLD

a CHANNELS

10F e

REGISTERS

DATA
2—11

ANALOES

SWITCH
COMPARATOR
AND
——>
WEIGHTED

DATA
REGISTER

RESISTORS

1‘ j

SAMPLE

Vsj

SAMPLE
AND
HOLD
SWITCH

POSITIVE
5 VOLT
REFERENCE
SOURCE

> o

V5]

O = O

NEGATIVE
5 VOLT

REFERENCE
SOURCE
BE-OISS

Figure 4-6

Analog-to-Digital Converter Block Diagram

The selected channel of the multiplexer, or the input to the side connector on the A841 module (if the multi-

plexer is not used), will be applied to the Analog Buffer-and the sample and hold circuits in the A841 module.
The sample and hold circuits will hold a dc level to allow sampling of fast-changing signals. The analog signal will
be sampled during the Sample Mode. When a HOLD signal is generated by the control module, it will go into a

Hold Mode and will apply the analog voltage to a summing junction for the A/D conversion process.
The comparator will monitor the voltage at the summing junction and send a signal to the control module, which
will determine the final condition of the analog switches. The comparator will output a 1 when the voltage at the

summing junction is less than 0V, and a 0 if the voltage is greater than 0V. The analog switches will be turned on
to supply current to the summing junction.

Each analog switch has a weighted resistor which will supply a cur-

rent to the summing junction proportional to its position in the weighted-resistor network.
cause the

The control logic will

right combination of switches to be turned on to null the voltage at the summing junction.

The A231 module, which controls the A/D conversion process, consists of the Enable/Status Register, Multiplexer

(MUX) Register, Data Register, Clock and Switch Register, Device and Operation Select Decoder, and the Interrupt and Skip logic.

4—11

The Enable/Status Register is used to transfer the status of the A/D converter to the processor and to enable logic
in the control module (see Figure 4-7). The Status Register provides the DONE flag and TIMING ER ROR flag to

the AC in bit 0 and 1

positions. The Enable Register consists of AC bits 2—5 and is used to enable Interrupts on

TIMING ERROR or A/D DONE, enable EXT A/D START, or select the Auto-Increment Mode of selecting multi-

plexer channels.

1=ENABLE
INTERRUPT
0N
TIMING
ERROR

STATUS
REGISTER

DONE=1
FLAG

<—MULT|PLEX REGISTER———~
1=AUTO
INCREMENT

(CURRENT CHANNEL

08-178)

1=ENABLE
EXT.
START

TIMING
1=ENABLE
ERROR=1 INTERRUPT
FLAG
ON
AD DONE
~——ENABLE

———+
8E-0192

Figure 4-7

Enable/Status Register Contents

The MUX Register consists ofAC bits 8—11 and is used to select the multiplexer channel from the AC; or if it is
incremented in the Auto-Increment Mode, to select Channels in sequence from

reaches 178

in the Auto-Increment Mode, it will reset to

08 and start over.

08 to 178. When the MUX Register

Loading the MUX Register from the

AC after each A/D conversion will allow randOm sampling of multiplexer channels.
The Data Register will contain 10 bits of data after the A/D conversion is complete; this data will be transferred
to the AC by programmed

instructions. The Data Register will also select the analog switches to null the summing

junction during the A/D conversion when it is strobed by the (internal) Clock and (Analog) Switch Register.
The Clock and Switch Register provides logic to strobe each bit position in the Data Register, starting with the
most significant bit, and to generate a LAST SHIFT pulse when the last bit is strobed to complete the A/D con-

version.

The Device Select logic will notify Operation Select logic that an A/D conversion is to take place. The Operation
Select logic will decode the instructions from the processor and control the A/D conversion. The Operation
Select logic will also gate information from the Enable/Status and MUX Registers to the AC.
The following instructions will be decoded by the control module and used to control the A/D conversion:

Clear All Logic (ADCL)

Octal Code:

6530

Operation:

Clear A/D DONE and TIMING ERROR flags. Clear MUX and Enable/Status Registers.

Load MUX Register (ADLM)
Octal Code:

6531

Operation:

Load MUX Register from AC bits 8—1 1, then clear AC.

Start Conversion (ADST)
Octal Code:

Operation:

6532
Clear A/D DONE and TIMING ERROR flags, start A/D converter. Channel to be converted is
determined by MUX Register.

4-12

Read A/D Buffer (ADRB)
Octal Code:

6533

Operation:

Clear A/D DONE flag and transfer contents of A/D Buffer into AC bits 0—1 1.

Skip on A/D DONE (ADSK)
Octal Code:

6534

Operation:

Skip next instruction if A/D DONE

1. Do not clear DONE flag.

Skip on TIMING ERROR (ADSE)
Octal Code:

6535

Operation:

Skip next instruction if TIMING ERROR flag

1. Do not clear TIMING ERROR flag.

Load Enable Register (ADLE)
Octal Code:

6536

Operation:

Load Enable Register from AC bits 2~5. Clear AC (see Table 4-1).

Read Status Register (ADRS)

Octal Code:

6537

Operation:

Read A/D Status Register into AC bits 0—11 (see Table 4-1).

Table 4-1

Enable/Status Register
Bit Position
0

Function

Signal Name

DONE indicates A/D conversion is complete when

DONE flag

DONE is set (DONE =1).
1

TIMING ERRORfIag

TIMING ERROR flag isset(1)whenADLM orADRB is

attempted while an A/D conversion is taking place.
2

ENABLE INTERRUPT

When bit position 2 isa 1, ENABLE INTERRUPT will

on A/D

DONE

allow an Interrupt to be generated when DONE is set (1).

ENABLE INTERRUPT

When bit position 3 isa 1, TIMING ERROR INTERRUPT

on TIMING

ERROR

ENABLE will allow an Interrupt to be generated when
TIMING ERROR =1. TIMING ERROR is set if an A/D

conversion is attempted while an AD RB or AD LM is

being executed.
4

ENABLE EXT START flag

When ENABLE EXT START is set (1), an A/D conversion can be started by an EXT CLOCK or EXT START

signal.
5

AUTO INCREMENT

When AUTO INCREMENT is set, the multiplexer channels will be incremented after each A/D conversion and
will select each channel in sequence 08 to 178.

Not used

(continued on next page)

443

Table 41 (Cont)

Enable/Status Register

8—11

Function

Signal Name

Bit Position

Bits 8—11 are used to load the MUX Register with chan-

MUX Register

nel to be sampled for an A/D conversion.

They can be

transferred to the AC to indicate current channel being

sampled.
A/D Converter Block Diagram

4.2.1

Figure 4-8 shows the functional block diagram of the Analog-to-Digital Converter. The A/D converter will be
broken down into the following functional areas for discussion purposes:
a.

Device Select

Operation Select

Analog Buffer

Sample and Hold

Analog Switches and Comparator

Interrupt and Skip Logic

Enable Register

Status Register

A/D Buffer

HOLD

BUSY
PRESET INPUT

START—u

o———>5AMPLE
‘

CLoochlNPUT
B
(1
S)
DATA INPUT

AD BUFFER

RESET
OUTPUT

8511A *——4H10 BITS)

(10 BITS)

l—-

-_|

ISAMPLE

HOLD

REF

—~.|ANALOG

SWITCHES

15 VOLTS

Vs.J

(OPTIONAL)---

rCOMPARATOR

I
I

HOLD I’SAMPLE/
’

HOLD

Figure 4—8

Vsj<0,COMP=l
Vsj >0, COMP=0

OFFSET

NEG REF

SAMPLE

8E-0l96

A/D Converter Functional Block Diagram

4—14

The analog preamplifier and multiplexer is not part of the A/D converter but is shown on the functional block

diagram to illustrate how the A/D converter interfaces with an analog input.
The Analog Buffer on the A841 will receive i5V analog data from the analog preamplifier and multiplexer or
from the outside world. The channel in the multiplexer will be selected by bits 8—11 from the MUX Register in
the A/D converter. In the Auto-Increment Mode, these bits will be incremented and applied to the multiplexer

after each cycle of A/D conversion to select the next multiplexer channel; bits 8—1 1 of the AC will be used to
select an analog channel in the Non-Auto-lncrement Mode.

If the AM8—EA is not used, one channel of analog

input will be applied directly to the A841 module by 3 7008533 cable to the side connector.
The output of the Analog Buffer will be applied to the sample and hold circuitry for an A/D conversion.

For

this discussion, we will leave the signal applied to the sample and hold circuits and deal with the operation of
control logic to perform the A/D conversion.

Before an A/D conversion can be executed, the control logic must be initialized and instructions must be generated to set up the logic for an A/D conversion. The first step in this process will be the generation of an IOT instruction which will be decoded by the Device Select logic. The Device Select logic will have MD03—M D08 ap-

plied to its input and when a 653x instruction is generated, it will output an INTERNAL l/O L and a SELECT L
(see Figure 4-6). The INTERNAL I/O L will cause the positive l/O bus to ignore all other lOTs. The SELECT L
will gate bits MD9~MD11 to the Operation Select Decoder. The Operation Select Decoder will decode the in-

structions and apply them to the control logic (see Paragraph 4.2.2.1).
The control logic will be initialized when a 6530 instruction is performed. The 6530 instruction will clear A/D

DONE and TIMING ERROR flags, the Enable Register, Status Register, and the MUX Register. After the logic
is cleared, the Enable Register may be loaded with bits AC2—AC5 to set up the logic for an A/D conversion. The

6536 instruction is used to load the Enable Register, (see Figure 46). A 1 will set the flip-flop and select the
condition indicated; i.e., a 1 in bit position 5 will select the Auto-Increment Mode of channel selection (see Para-

graph 4.2.6).
The channel selected for the A/D conversion will be determined by the contents of the MUX Register. The MUX

If the Auto-Increment Mode in the

1), the MUX Register will start at the channel loaded into the MUX Register

and increment the MUX Register to select a new channel.

If the MUX Register is not loaded with a 6531 instruc-

tion, and if the 6530 was performed, the first channel selected will be channel 08 if the ADCL instruction cleared
the MUX Register. In the event neither instruction was performed, the MUX Register will start at whatever channel it contains.
Random selection of the channel to be converted can be accomplished by loading the MUX Register with a new

channel after each A/D conversion. If the AM8-EA is not installed, the MUX Register will have no effect and the

input to the A841 module will be applied to the Analog Buffer. (See Paragraph 4.2.5 for detailed MUX Register

logic.)
The Status Register, a part of the control logic, contains the TIMING ERROR and A/D DONE flags. TIMING
ERROR will set if a 6533 or 6531 instruction is attempted while an A/D conversion is in progress. A/D DONE

will set when LAST SHIFT is generated by the Clock and Shift Register logic at the time the last bit position is
strobed. A/D DONE may be used to enable a Skip after the A/D conversion is complete and data is ready for

transfer to the AC. A 6535 instruction will check the TIMING ERROR flag and generate a Skip if the flag is set.
The contents of the Status Register can be transferred to the AC by a 6537 instruction for status checks.

Paragraph 4.2.2 for detailed logic.)

4-15

(See

After the logic in the control module is initiated, a 6532 (A/D START) instruction may be performed to start
the A/D conversion. The 6532 instruction will clear TIMING ERROR and A/D DONE, and set the BUSY flip-

flop used to generate a HOLD command in the sample and hold circuits.

Note that the A/D converter can be

started by an EXT START or EXT CLOCK START if the EXT START ENABLE (bit 4 of Enable Register is 1)

flip-flop was set by a 6536 instruction. An EXT START or EXT CLOCK START would set the BUSY flip-flop
and start the A/D conversion if EXT START ENABLE is set. The EXT START and EXT CLOCK STA RT signals

originate in the Real-Time Clock when an overflow signal is generated or a Schmitt trigger fires (see Paragraph
4.6).
The signal on the input to the Analog Buffer will be applied to the sample and hold circuits shown inside the
dotted lines in Figure 4-8. The sample and hold circuit has two modes of operation:

Sample or Hold.

in the

Sample Mode of operation, the input to the amplifier will be applied to a capacitor on the output. The switches
will, as shown in the diagram, apply a ground to the other side of the capacitor allowing the capacitor to charge
to the input voltage.

The other two switches will be as shown to allow the capacitor to charge.

In the Hold Mode,

the two switches that are shown closed will open and remove the input to the amplifier and the capacitor. The
other two switches will close, ground the output of the Analog Buffer, and allow the voltage on the capacitor to
be applied to the input of the amplifier. The amplifier will maintain the voltage on the capacitor at the summing

junction during the Hold Mode for an A/D conversion. The mechanical switches shown are for explanation only.
The switches in the sample and hold circuits are FET semiconductors. The mode of operation is determined by
the BUSY flip-flop in the control logic. When BUSY is cleared, the Sample Mode is enabled; when BUSY sets,
the Hold Mode is enabled.

The BUSY flip-flop will set when a 6532 instruction or an EXT CLOCK START pulse is present. The setting of
the BUSY flip-flop will trigger a 2-us delay network in the clock and assert the PRESET and HOLD signals.
PRESET will set the switch register to the most-significant-bit position of the A/D Buffer and the HOLD signal
will switch SAMPLE and HOLD to the Hold Mode. The clock pulse will be delayed an additional 100 ns to allow
the sample and hold amplifier to settle before the A/D conversion starts. After the delay, the clock pulses will
start the Shift Register counter which was preset to bit position 2.

The Clock and Shift Register will strobe each

bit position from M88 (2) to LSB (11). (See Paragraph 4.2.2 for detailed logic).
As the Shift Register strobes each bit position (see Figure 4-8), the comparator will be checking the summing

junction and comparing it with 0. If the summing junction is below 0, the comparator will output a 1; if the
comparator is above 0, a 0 output will be applied to the data input of the flip-flops in the A/D converter. This
will determine the final state of each bit in the A/D Buffer.

(See Paragraph 4.2.10 for detailed logic.)

The analog switches and weighted resistors will act as current sources for the voltage at the summing junction to

supply the current necessary to reduce the voltage at the summing junction to 0V. Each switch and weighted
resistor will supply current to the summing junction if the switch is turned on by the flip-flop in the A/D Buffer.

Figure 4-9 shows one flip-flop in the A/D Buffer and an analog switch tied to the 0 side of the flip-flop. Initially,
the flip-flop will be reset, producing a high output to l1.

l1 will have a low output and will enable E2 to apply
positive voltage to the base of O1. 01 will conduct and cut 02 off. No current will be supplied to the summing

junction by 02 or to the weighted resistor tied to its emitter. When a clock pulse and Shift Register pulse are
applied to E3, the gate will be enabled and will set the flip-flop to apply a 0 to l1. l1 will invert the low to a high
and turn 02 on to supply current to the summing junction.

If the comparator output is 1

(summing junction <

0), the flip-flop will set when SR02 is applied to the clock input and will turn the switch off. The Clock and
Switch Register will strobe all the bit positions to turn on the right combination of switches to null the voltage at
the summing junction. Each switch will supply current to the summing junction, the amount determined by its

position in the network. After the last bit is checked, a LAST SHIFT will set the A/D DONE flip-flop. A/D
DONE will generate a Skip if the 6534 instruction was performed, or an Interrupt if the A/D DONE lNTE RRUPT

4-16

CLOCK
SR PULSE 1

|
I
l
l
l

3—1

DATA our H ___.D 5

Vsi<d=1

+15VHQ

o—wv—Loelusv

Vsj>0=0

I
|

SR PULSE 2

3: D1

Loélc

WEIGHTED
RESISTOR

I
@

+5.,
REFERENCE

SUMMING
JUNCTION

8E-0339

Figure 4-9 A/D Buffer and Switch Logic
ENABLE was set in the Status Register. The contents of the A/ D converter may then be transferred to the AC

by programmed instructions. (See Paragraph 4.2.2 for detailed logic.)
4.2.2

A/D Converter Detailed Logic

4.2.2.1

Device and Operation Select Logic

——

The Device Select logic (see Figure 410) will receive bits MDS L—

MD8 L and the I/O PAUSE L signal as inputs. I/O PAUSE will be generated 150 ns after the generation of TP1
in the FETCH cycle. The I/O PAUSE will be applied to AND gates in the Device Select logic to gate bits MD3 L——

MD8 L.

If these bits are 53 octal, an INTERNAL l/O L will be generated to indicate that the A/D converter will

perform this operation.
The operation to be performed by the A/D converter will be determined by bits MD09 L and MD 11 L.

INTERNAL

I/O L will be applied to the AND gates and will allow the bits to be applied to the 8251 IC, which is a BCD-toDecimal Decoder. The IC will output a low on the appropriate line for the instruction that has been decoded.
Truth tables, timing diagrams, and logic for the 8251 IC are shown in Appendix A of the PDP-8/E Maintenance

Manual.

4.2.2.2

External A/D START and Time Pulse Logic

—

Figure 4-10 shows the EXT START and EXT CLOCK

START logic. EXT CONV START out of E2 will be low if the EXT START ENABLE flip-flop in the Enable

Programmable Clock, or other peripheral, is used to determine when an A/D conversion is to be performed.
The TP3 AND AD LE signal will be used to allow loading of the Enable Register from bits 2—5 of the AC. The
INIT or TP3 AND ADCL signal will generate a CLEAR L to clear all flip-flops in the control logic.

INIT is gener-

ated to clear all logic when CLEAR is depressed on the control console, or when the power is turned on.

4.2.2.3

Interrupt, Skip, and Control Logic

——

The control logic (see Figure 4-11) will select the proper C lines

and generate or receive a BUSY, TIMING ERROR, A/D DONE, Interrupt request, and Skip.
the registers in the A/D converter.

4-17

It will also clear all

EXT START

FMZ
-

FL”
EXT
CLOCK
START

1°

EXT c0Nv

5
EXT ST EN (1) H-——1

HM1

R2
1

+5V

(1N1T+A0CL«TP3)

E19

CLEAR

AP‘

MD03

M004

LMC
E32

—-1—C

8H7

M005

LB;1

M006

BM‘

‘5‘
—4d

1°

E32

M00?

12
CL1

INTERNAL

L——E’P11E

M008 L

0'“
4

q
11

I/O PAUSE

Lem—O

M909

E27

‘3

o—A00L165301

—C

D—-—AOLM(6531)
'

p—d

0M1

£27

D—A05T16532)

an
\J

o—q
ADLE-TP3 A

M011

L_DP1_Q12

825‘
E28
E27

\13

D——-ADRB(6533)

o———A051<16534)

o—A03E16535)

D——A0LE (6536)

_5d
6

9
3

TP3

M010 L __Q

L——0—30

E31

0L1
_

L—O

A0LE

I/O L

——0
4

A0LE _TP3

D—ADRS(6537)

L-——-0——Q
8E~0197

Figure 4-10

Device and Operation Select Logic

ADRS L
ADRB L

—\

i‘E44

‘

‘2

ADLE L

E35

3CH1

CIL

E35

E44

ADLM L

4CE1

COL

c»

TMG

ERR
3

cE500 s

excouv ST L——0

E39

ADSK

L—C{>——
'

6H7

‘3

23mm

DONE
11

5°
c

8
0—-

TMG ER

INT EN (1)H

INITIALIZE H—

AD DONE (1) H
(SAMPLE H)

E47

E43
11

539

13 cm

BUSY (UH

109.3

CLR SR L

“MT + ADCL.TP3)H

Figure 4-11

SKIP L

E486

LAST SHIFT L

‘°

10 cs1

BE-OISB

Interrupt, Skip, and Control Logic

INT ROST L

4.2.2.3.1

C-Line Select Logic

—

The C-Line Select logic will be used to control the direction of data flow to and

from the AC by asserting CO and C1 (see Figure 4-12). C0 and Cl will be pulled high or low by programmed in-

structions to OR gate E44. AD RS or AD RB will cause a
Table 4—2

high output on pin 8 of E44, which will cause E35 pin 3 to

C-Line Logic Levels

Any of the instructions applied

go low and pull C1 low.
to p ins 9,

10, 12, and 13 of E44 will cause the OR 9 ates to

Type of Transfer

low out of E40 will be inverted and applied to pin 5 and 6

Output, AC unchanged

of E35 and will pull C0 low. Table 4-2 shows the status

Output, AC cleared

input AC cleared with

output a 1, which WIII cause pm 4 of E40 to be low. The

of C lines to control data flow between the A/D converter

and the processor. C2 will remain high because the A/D

input data

converter never asserts thIs Me for any InstructIon.

INTERRUPT

T31

JAM input

TlMlNG

T32

T54

T83

T32

T81

T83

T34

TP1J--| szrl TP3r-l TP4|-—l TPIH szlnl TP3|_-l TP4r-L
Lu

INT

STROBE

INT

ENABLE

Z
LIJ

E
‘

‘l
|

IOT

INST

==
|

FETCH

I
l

INT

‘

DELAY

INT
,

SYSTEM II'ULLY ENIABLED
I

CYCLE OF INST WHEN
<— ___LA3T
INT RQST GOES L0

INT

WITH

INT ENABLE AND

‘

—>:<-—EXECUTE

DELAIY

SET

l
CYCLE 0F FORCED JMS->

-_',___..____._____._..r_

RQSTL

SYNC

PROGRESS

INT ENABLE

INT

1!
Lu

E
a
5’
3

INT

'—

E
INT

DELAY

JMS

J,:

EXECUTE

m—
:
SYSTEM
DISABLED—9
:<——-INT
I

8E-O194

Figure 412

Interrupt Timing Diagram

4-20

4.2.2.3.2

Interrupt and Skip Logic

—-

Program interrupts are used in the A/D converter to allow the processor

to continue the program while the A/D conversion is performed, and to interrupt the processor if a timing error

is detected. To generate an Interrupt when the TIMING ERROR flip-flop sets, the TIMING ERROR ENABLE

flag must be set in the Enable Register.

The TIMING ERROR INT ENABLE flag and TIMING ERROR flip-flop

input to pins 1 and 2 of E43 will enable the OR gate and assert the Interrupt request line at pin 13 of E39.

Interrupt on A/D DONE is similar to the timing for Interrupt logic shown in Figure 4-12. Refer to Paragraph
3.9.6 of the PDP-8/E Maintenance Manual for a more detailed discussion of Interrupts.

4.2.3

Status Register

The Status Register consists of TIMING ERROR and A/D DONE flags (see Figure 4-7). The TIMING ERROR

flag will be used by the A/D converter to detect application of new data to the sample and hold circuits while the
A/D conversion is in process. A TIMING ERROR will be generated if instructions ADRB L or ADLM are decoded during an A/D conversion. The BUSY applied to pin 2 of E47 will be present while the HOLD portion of
the A/D conversion is in process.

If these programmed instructions or EXT CONV START are applied to pin 1

of E47, the gate will output a 1, and set the TIMING ERROR flip-flop. The TIMING ERROR may cause a Skip
to be generated and the processor may go to the next instruction without completing the A/D conversion if the

ADSE instruction was programmed. Instruction ADSE enables gate E43 and generates a Skip if the TIMING
ERROR flip-flop sets. TIMING ERROR will generate an Interrupt request if a TIMING ERROR INTERRUPT
ENABLE flag is set in the Enable Register.
The A/D DONE flip-flop will be set by the LAST SHIFT L signal from the Shift register. The set side of the A/D

DONE flip-flop will be AN Ded with ADSK instruction to generate a Skip.

If the DONE INTERRUPT ENABLE

flag is set, A/D DONE will enable AND gate E47 and will generate an Interrupt request.
4.2.4

BUSY Flip-Flop

The BUSY flip-flop is set to start an A/D conversion by EXT CONV START or an ADST instruction (see Figure

411). The EXT CONV START or the ADST instruction will cause the set side of BUSY to go high, clear A/D

DONE, and start the A/D internal clock. The clear side of BUSY will clear the switch register in the switching
logic when BUSY is cleared by CLEAR L, INIT, or an ADCL instruction and TP3.
4.2.5

MUX Register Logic

The MUX Register (see Figure 413) will select a channel to be applied to the sample and hold circuitry of the

A/D converter. The contents of the register will indicate which channel in the multiplexer is currently being

sampled.

In the Auto-Increment Mode (lNC EN

I), the output will be incremented to select the next channel.

The 8235 IC will be used to gate MUX8—MUX11 to the AC when the ADRS instruction is performed, or to gate

ADBBwADBII to the AC when an ADRB instruction is performed. The ADRB bits are not used in the MUX

Register, but this portion of the IC is used to supply these bits to the Data Bus from the A/D Buffer. Truth
tables, timing diagrams, and logic for the 8235 IC are shown in Appendix A of the PDP-8/E Maintenance Manual.
The 8235 IC is a 4-bit dual-channel data input logic element. The output is controlled by instructions AD RB and
AD RS.

The Look-Ahead data bits, or MUX data bits, will be gated to the data input on the MUX Register flip-flops and
will set them to the channel desired. The flip-flops can be set to any octal number 0 through 17. The Look-Ahead

output, which is one more than the MUX Register, will also be gated back to the MUX Register by NOT AD LM H,
and will increment the register by 1 on RESET H asserted. The Look-Ahead will always be one channel ahead of

the MUX Register to allow selection of the next channel. Table 4-3 shows the MUX Register contents and the

output of logic which produces the incremented Look-Ahead bits for all 178 channels.

4-21

+5V

ADLM-TP3 L

INC EN

+3V

RESET

MUXB (1) H

LK AHDBH

E45

LK AHD 8 H

E29

0R1
DATA 8 L

MUX9 (1 )H
ADRB L
ADRS

HF1

DATA 9 L
51

5
E29

LK AHD 9 H

ADBB(1)L2

ZZ'V

ADBQ(1)L
A0810 (1)

LlI1

ADBH(1)L

14
+3v

MUX8(1)H

LK AHD 10 H

‘

MUXS (1)

MUX10(1)H
HH1

MUX10(1)H
MUXH(1)H

LKAHDioH

DATA1O L

+3V
LK

AHD11H
3

MUX11H)H
HM

DATA11

CLEAR

LK AHDHH

DV‘

W3
eE-Q‘QQ

Figure 413

MUX Register Logic

Table 4—3
MUX Register Contents and Look-Ahead Bits
Look-Ahead Bits

Contents of MUX Register

LK AHD 11

MUX8

MUX9

MUX10

MUX11

LK AHD 8

LK AHD 9

LK AHD 10

The MUX Register will be cleared by CLEAR L which was generated in the control logic by the ADCL instruction

and the lNlT L signal. The W3 jumper between A and B of the Clear line can be removed to isolate malfunction-

ing ICs when troubleshooting.
4.2.6

Enable Register

The Enable Register (see Figure 4-14) will receive AC2—AC5, and will provide enabling signals to the Interrupt

and control logic in the A/D converter. The Enable Register (see Table 4-1) is made up of DONE lNTERRUPT

ENABLE, TIMING ERROR lNTERRUPT ENABLE, EXTERNAL START ENABLE, and INCREMENT ENABLE.
Any flip-flop in the Enable Register will be set by a 1 from the appropriate AC bit to enable the control logic in
the A/D Converter. The 8235 IC will select either AD BZ—ADB7 from the A/D Buffer or the contents of the

Enable Register for transfer to the AC. The 8235 IC is a 4-bit dual-channel data input logic element which will
be controlled by instructions ADRB or ADRS to gate data to the AC. The ADRB instruction will gate the A/D

Buffer bits to the Data Bus and the AD RS instruction will gate the contents of the Enable Register to the Data
Bus. The AD LE instruction will gate AC data bits 2—5 from the Data Bus to the Enable Register. AD LE and

TP3 will be applied to the clock input of each flip-flop to set the flip-flop if there is a 1 on the data input.
The set side of the flip-flops in the Enable Register will be used to enable gates in the control logic (see Figure

4-7). DONE lNTERRUPT ENABLE will allow an Interrupt request at the completion of the A/D conversion.
To set DONE INTER RUPT ENABLE, a 1 must be transferred from the AC in bit position 2. The other flip-flops
will be set in the same manner by bits 3, 4, and 5 from the AC enable gates in the control logic. See Figure 4-7

for bits used by the Enable Register.
4.2.7

Analog Buffer and Sample and Hold Circuits

Figure 4-15 shows the Analog Buffer and the sample and hold circuitry. The E8—E9 Analog Buffer is a differential amplifier with a common-mode balancing potentiometer to balance amplifier gain and null unwanted inputs.

4—23

ADLE

L—u—fic
E6

\ 13

‘25
2

AR1

ADBZU)

TMG ER

INT EN(1) H

DATA 2 1.

+3V

AL“

n12

‘0
15

C)L
c?

TAV‘

DATA

0
E6

\14

17317

ADRS

L—-—-—0

EEMIfiT

3 L

0—30

fl 2

E15

L10
0

53—.__4

T1
+3v

8235

EXT ST EN

L—d

(1)H

0—8——

L————C
DATA5

ADBS(1)L—H-C E 16
(1)

EXT ST EN (1)

A087

E20
EXT
ST EN

ADLE-TP3 A H
7

A035 (1)

+3v

DATA 4 L

A084 (1) L

TMG ER
INT EN ( 1 ) H

E12

‘9

R6
1|—MN-—-—+5V

ADRB

8231/5
E

TIMING ERR0R(1) H

DONE INT EN(1) H

A81

0—— DATA 1

DONEH) H

INT
EN

0—— DATA 0 1.

DONE INT EN(1)H

E12
DONE

A033“) L—C

L,P

‘-

1331

—c
4

(L4

E15

\ 3

1r5———INC EN(1)H

520
mo
EN

ADLE-TP3 B H

CLEAR

L———J

85-0193

Figure 4-14

Enable Register Logic

NEGATIVE
REFERENCE
R102

c12

HAH—
D33

+8v————

AA1
TO

029]:
ANALOG FK 1
NODE
OR+ INPUT

5&8

'\
E8

SUMMING
JUNCTION

R97

OAS

030

*8V

1331
R89
-INPUT «2-

023

1\C13

—3v

F195;.

‘

032

::R94

R961;

AD
G

-8V

R98

o—--<>

043“

032

1! D42

SHIELD—fl
SHIELD

GND——_L

O/\s

r1 O 1

98'17

$6
§ER1o4

025
8

MUX FL1
RTN

027

:D G

‘4‘
0

mac +5v
R35

° 26

10
029
12

9
o

R100::
1:
R10"

‘

030

R992;

Fsz
RESET

‘,

1£R105¢R106
2)

03411
‘3

1:037

$940

0331:

03631
0361:

“‘2
SAMPLE

FRZ

”“03

D39” K D41
HQ GROUND
—15v

eE-ozoO

Figure 4-15 Analog Buffer and Sample and Hold Circuits

The CMR potentiometer is adjusted at the factory with a (50on signal applied to both input lines. The signal is
monitored at AA1 and the CMR potentiometer is adjusted for a minimum signal. A W1 jumper must be installed
if the A232 Analog Preamplifier and Multiplexer Expander module is not installed. The CMR circuit is only use-

ful when W1 is installed to apply differential inputs to the A841 module.
The output of the Analog Buffer is applied to switching circuits which will determine if it is applied to the sample
and hold amplifier.

Amplifier E10 has two inputs:

the output of the Analog Buffer during Sample Mode, and

the voltage on capacitor C13 at the summing junction during the Hold Mode. The input to E10 will be deter—
mined by the FET transistors 028, 027, 031, and 032, which are controlled by the MODE SELECT flioflop E1
and its associated transistors. The FET transistor characteristics are such that they will conduct with 0V on the

gate, and cut off with

—

15V on the gate. When the FETs are conducting, they look like closed switches; when

they are cut off, they look like open switches.
During the Sample Mode, SAMPLE H Will enable E2 and clear E1. This will put a low on the base of 030 and a
high on the base of 029. The 029 collector will rise to 0V and allow 032 and 028 to conduct. 032 will apply a
ground to C13 to allow it to charge to the input voltage, and 028 will allow the analog signal to be applied to E10.
031 and 027 will be cut off by the negative voltage on the gates. The output of E 10 will charge C13 during the

Sample Mode for sampling during the Hold Mode.
During the Hold Mode, the SAMPLE signal will be removed and HOLD H
will be applied to the clock input of E1.

HOLD

20ps—~>f

E1 will now set and switch the

voltages on 029 and 030. When the voltage switches, 028 and 032 will
cut off and remove the ground from C13 and the analog input from E 10.

031 will conduct and the voltage on C13 will be applied to the input of
E10. 027 will conduct and ground the analog input voltage. E10 will
maintain the voltage on C13, which will be applied to the summing

junction for an A/D conversion. The Sample and Hold Modes can be

86-0367

monitored by applying a 0V to 5V ramp input to the A/D converter,
and by monitoring at AA1

(see Figure 4-16). The hold time should be

20 us; the sample rate will be determined by the program.

4.2.8

Figure 4-16
a Slow

Signal at AA1 with

Ramp Input to the A/D
Converter

A/D Converter Internal Clock

The A/D converter internal clock (see Figure 4-17) will be used to delay the BUSY signal and to generate a HOLD

signal. The clock will supply clock pulses to the Shift Register (see Figure 4-18) to cause the Shift Register to
preset to bit position 2 (MSB) and strobe each bit position during an A/D conversion.

The clock will start when

the BUSY signal is received and generate PR ESET, which is applied to the sample and hold circuit putting it into
the Hold Mode. The BUSY signal will be applied to three delay networks and will produce a clock high on the

outputs of E5. Once the clock is started, it will produce 100—ns pulses, 1.8 us apart, as long as the BUSY signal is
present at E5. These clock pulses will cause the Shift Register to supply a clock input to each flip-flop in the A/D
Buffer (see Figure 4-19) to allow each bit position's analog switch to be turned on for checking by the comparator. The timing diagram for the A/D clock is shown in Figure 4-18.
to bit position 2.

PRESET is used to preset the switch register

SR1 through SR10 will be applied to the clock input on each flip-flop in the A/D Buffer to

turn on the analog switch for that position.

The clock signal is delayed to allow the sample and hold to settle

before the A/ D conversion starts.

4.2.9

Analog Switches

The analog switches in Figure 4-20 will be turned on to supply current to the summing junction. Each switch has
a transistor and

weighted resistor which will supply current to the summing junction when a high is applied to the

4-26

2
4

(1) H

BUSY

Doe—imam
F

+5V

+5v

:ERs

.ER4

C57

C56

II
I\

1
1

U
LZ‘V

1
1

FPZ

CLOCK H

E10
100ns

CLOCK

SE -0201

Figure 4-17

Analog-to-Digital Converter Internal Clock

BUSY

__|
l_

.mm

nnnnmvwmm

UUULflLl-LILJ-LM

E (c Loc K)

PRESET

lUUUUflLLMl

__.[

SR1

SR2

SR3

SR4

SR5

SR6

SR7

SR8

SR9

L.—

smo

*—

RESET H

BE- 0202

Figure 4-18 Analog-to-Digital Converter Internal Timing Diagram
transistor associated with it. The conduction of the transistor will be determined by the flip-flop in the A/D

Buffer, which is set by the Shift Register, to allow each switch to be turned on for the comparator to check the
summing junction (see Figure 4-21). The output of the comparator will determine whether the switch is to be
turned off or left on. Each switch will supply a given amount of current to the summing junction, based on its

position in the weighted-resistor network. The right combination of switches will be selected to supply current
to the summing junction and reduce the summing junction to a null voltage when the last bit (bit 11) is checked.

The summing junction will be very near 0V. Switches that remain on or off in the A/D Buffer will represent a

digital value in proportion to the input voltage.
A switch is turned on (see Figure 4-21), bit ADB10 for example, when the inverter receives a low input. The low
into the inverter will apply a high to the base of 02. 02 will conduct and supply current to the summing junction

through R8, a part of the weighted-resistor network. The switch emitter circuits are discharged to ground through
03, R7 and R9 to provide a fast recovery time for switches during the A/D conversion.

4-28

A08 2 (1) H
B W2
—————————

PRE SET

F52

FNZ

—{

DATA

2'0
‘20
59
A032

(B4
13—

3—0

12—

‘20

159
FTZ

“

i CSS

FV2

112

ADBS

L-I

ADBOS(1)LJ

80
43

11
E22
ADBS

FV1

(B4
1—2—

13—
A0310

FR‘I

‘1

A0309 (1)L

ADB 10(1)

ADB11

FP1

E17

E25

——————————

13
r

RESET

5‘

4
1»—

FN1

éi——ADB1(1)

L‘I

i
E26

E26

CLOCK H

ADBO4(1)

(B4

£0
E14

ADB4

FUZ

ADBO3(1)L—|

ADBOZ (1) Ld

13
E14

A033

0—8—0

525

LAST
SHIFT

657
-x—
,———J~———-———‘
I

1
|

SR8
SR9

SR5 SR6 SR7
SR4

SRO

10
12

$—

11
L

13
+3v

+3V

SR1

—-

—

*Dotted lines indicme pins 5,6.10 and 11
bits 6. 7.and 8 n01 shown.

1
-

9
——

SR2

521

SR2
6

SR”
3

—

SR10

SR3

E13

E8
SR1

SRO

CLOCK

+3V

74164

CLR

SHIFT

3—10

13
v

IC and

Logic for
8E-0203

Figure 4-19 A/D Converter Shift Register and Data Buffer

~15V HQ

R11

‘

C8,?

1'$

02
1':

R44

“a

010
1‘

§ER3
HQ
GROUND

IER13 R14

:;R8 ::R9

018

q
(
R521:
1

1:R53
1

3R4?

011

5v REFERENCE

4:.»

R463»

R50

016

)

R12

v‘v‘v

3: R49
A

_____

‘M

3: R43

R10

LOGIC GROUND

_____

SUMMING JUNCTION

.....

08’17
LOGIC +sv

_____

+ 5"

::R64
I

‘

:3 R66

020

021

7'
_____

£5

FP1

FUZ

FTZ

A0811 (1) L

-----

ADB 10(1) L

12
E5

ADB 09(1) L

ADB 03(1) L

INDiCATES M!$S|NG SWITCHES

Figure 4-20 Analog Switches

ADB 02(1) L

Ema“

+15V HQ

_A A

A A.

vviv

.; R61
1

R62

SUMMING

SDA5

JUNCTION

02‘

D:
=

aav

+ 5v

7.5V

1—

-o.7

LOGIC

3: R87

R86

Ip—— DATA OUT H

024

Loélc

R82

-15VHQ
8E-0326

Figure 4-21
4.2.10

Comparator Circuits

Comparator

The comparator (see Figure 421) will compare the voltage at the summing junction with UV (H0 ground) and

output a 1 if the voltage at the summing junction is less than 0V, and a 0 if the voltage at the summing junction
is greater than 0V. The comparator output will be used to determine the final condition of the flip-flops in the

A/D Buffer that control the analog switches.
When the summing junction voltage applied to the base of 021 is greater than 0V, that side of the transistor will

conduct; current from R60 and R62 will flow through the emitter of 022 to the *15V power supply. The voltage
at R83 will be applied to the base of 023 and will cause the emitter to go positive.

The positive voltage on the

collector of 023 will be applied to the base of 024 and the collector of 024 will go to 0. A O on the collector of
024 will give a low data output to the A/D Buffer.
When the summing junction is less than 0, the right-hand side of 021 will conduct and current will flow through

the right half of 021 instead of 022. The collector on 022 will go negative and be applied to the base of 023.
The emitter of 023 will go negative and cause the collector on 024 to go positive and produce a 1 to be applied
to the A/D Buffer as DATA H.

4.2.11

A/D Buffer and Shift Register

The A/D Buffer and Shift Register (see Figure 4—19) will control the analog switches and provide a storage register
for the 10 bits of digital data until they are transferred to the AC.
The Shift Register will receive a preset input to clear the flip-flops in the A/D Buffer and select bit position 2 to
start the A/D conversion. The clock will also supply pulses to clock the Shift Register and set each bit position

for checking by the comparator. The clock pulses (see Figure 4—17) will be 100 ns in duration, will occur every

1.8 us, and will cause the switch register to strobe each bit position.
The clock pulse (see Figure 4-19) will also enable the gates for the output of the Shift Register to be applied to
the set input of the flip-flops in the A/D Buffer. The flip-flop will set and turn on the analog switch to supply

4-31

current to the summing junction and will supply an amount of current proportional to its position in the

weighted-resistor network. The comparator will be monitoring the summing junction; it will supply a 0 if the
voltage at the summing junction is greater than 0V, and a 1 if it is less than 0V. The Shift Register will then
switch to the next bit position, supply a signal to be gated by the clock pulse, and set the next flip-flop.

It will

also supply the clock input of the previous flip-flop. This flip-flop will now have a positive-going edge on the

clock input and low or high on the data input.
that bit position will output a low (0).

If the data input is high (Vsj>0), the flip-flop will remain set and

if the data input is low (Vsj<0), the flip~flop will clear and that bit posi-

tion will output a high (1). Note that the output of the buffer is taken from the 0 side of the flip~flop and the

digital data will be in 2’s complement form.
The Shift Register and clock will check each bit position and when bit position 11 is checked, LAST SHIFT will

LAST SHIFT will be applied to the set side of the A/D DONE (Figure 4-11). It will set A/D DONE to

below.

generate an interrupt request if A/D DONE interrupt is enabled, or a Skip if the ADSK instruction is performed.
The contents of the A/D Buffer will be transferred to the AC using an ADRB instruction.

RESET H will be ap-

plied to the BUSY flip-flop (Figure 4-11) and will clear the BUSY flip-flop. When BUSY clears the A/D

converter,

sample and hold will return to the Sample Mode.
Each flip-flop in the A/D Buffer will hold a 1 or a 0 when the

Table 44

A/D conversion is complete. The output of bit position 2 will

Applied Voltages and Octal Equivalents

be taken from the set (1) output and all others will be taken
from the clear (0) side of the flip-flop. ADBZ will be used to

Appl'ed voltages

octa' Equ'va'ent

indicate the sign of the 2’s complement number transferred to

+4.990

0777

lf ADBZ remains set, it will be transferred to the AC

+3.750

0600

O, to indicate a positive number, or if it is cleared, a 1 will

+2.500

0400

indicate a negative number. Table 4-4 shows the applied vol-

0.000

0000

tages and octal numbers in 2’s complement form generated by

-2.500

7400

the A/D conversion. The display-converted value in the AC

-3.750

7200

program in Chapter 5 may be used to read the contents of the

—5.000

7000

the AC.
as a

A/D Buffer.
The A/D Buffer contents may also be monitored with an oscil-

loscope at test points on the A841 module. The test points
are

marked 012 for bit 2, and 3—11 for the remaining bits.

With a

—

contain

7V input to the A/D converter, the A/D Buffer will

00008'

or all

is run with a —7V
_

0’s. If the display in the AC program

input and the AC reads 7000, the signal
.

j
j

/:
{

‘5”

’

“g

’i

1-8!“

NOTE:
Tr and Tf should

be less than

750ns

for each bit Will be as shown In Figure 4-22. The osc:l|oscope should display a

+5V

eE-oaea

1.8-,us square pulse with a rise and

fall time of less than 750 ns. A rise of fall time of more

Figure 4'22 A/D Buffer Signal

than 750 ns indicates that the bit being checked is not set-

tling fast enough for the A/D converter to perform accurate conversions.

The signal monitored at AA1, the output of the operational amplifier, should be as shown in Figure 4-23 with a

5V input. AA1 should display a pedestal less than i 50 mV, approximately 20 us wide. These pulses are not

clearly defined nor free of noise when displayed on the oscilloscope. A faster oscilloscope loop may be loaded to

display a brighter waveform.
The summing junction signal and the comparator response to that signal is shown in Figure 4-24. The upper trace

shows the summing junction response to an input voltage corresponding to 0106 octal. The first bit is inverted
and the remaining bit positions are at different levels to produce a 0106 octal value. The lower trace shows the

4-32

Figure 4—23 Signals at AA1 and Collector of 020 on the A841 Module

Figure 4-24 Signals at AA1 and Collector of 020 on the A841 Module
signal produced on the data output in response to the input signal. When the voltage at the summing junction is
greater than 0V, data output is 0. When the voltage at the summing junction is less than 0V, the data output will
be 1.

NOTE
The signals in Figure 4-23 illustrate SAMPLE and HOLD. The

top trace is from the collector of 020 and the bottom trace
was taken from test

point AA1. AA1 was monitored with the

Y axis set to 10 mV/cm and data output was monitored at 10

V/cm. Input selector should be set to AC to prevent saturat-

ing the oscilloscope.
4.2.12 Positive and Negative References
The positive and negative references (see Figure 4-25) are set as a constant current source for the summing junction during an A/D conversion. The positive reference will be applied to the transistor for each analog switch

(see Figure 4-20) to supply a +5V reference. R57 is used to adjust the positive reference. The reference voltages

effectively adjust the gain and offset of the A/D converter. The positive reference affects gain and the negative
reference affects the offset.

If i5V inputs cannot be spanned, the reference voltages should be adjusted (see

Chapter 5). The negative reference will supply a constant current to the summing junction; R35 is used to adjust
the negative reference.

433

‘——-’—"’__—‘——“”"_—_7

POSITIVE REFERENCE
‘

+15VHQ

1F012
8.2V
»

D14

‘

A—cp

arms

imss
¥ my

:;R48

1‘ D15
SUM MING

JUNCTION

COMPARATORI

—-|

NEGATIVE

I REFERENCE

-15VHQ
b

I
I

I
I
l

R28

R“ 0

R35 0
use
-REF
ADJ

D
-6,“

:Ecm

JL D44

:: R54

B—fi

|
I
I

3312104 ¥ D47

”045

I
—J

EL
HQ

8E-0327

Figure 4-25

Positive and Negative References

4-34

SECTION 3
ANALOG PREAMPLIFIER AND MULTIPLEXER

4.3

INTRODUCTION

The AM8-EA Analog Preamplifier and Multiplexer consists of one A232 quad module plugged into the OMN IBUS

(see Figure 4-26). The AM8-EA interfaces with the AD8-EA by an H851 Edge Connector, and with the outside
world through an AM8-ED or AM8—EC Analog Input Panel, or a 7008533 cable plugged into a side connector.
Each A232 module provides for eight i1V inputs and provides the A/D converter with i5V output. The AM8—EA
8-channel multiplexer consists of multiplexer switches and scaling amplifiers for 8 analog channels. The AD8—EA

A/D converter can be expanded to 16 channels by using 2 AM8—EA modules.
INSTRUCTIONS
CHANNEL SELECT
I/O PAUSE

CONTROL
MODULE

COMPARATOR
OUTPUT
—

—

:1voc

ANALOG
INPUT
PANEL

I
I

/
8

PREAMPLIFIERS

CONTROLS

I-*AM8-EA
—-—+

DATA

(A231)

e
CHANNEL

\
/

I
_|

I—

2 sum

COIIXBEESER

tsvoc
FROM
OUTSIDE

*ONE MORE AM8-E CAN BE ADDED TO EXPAND SYSTEM TO 16 CHANNELS

8E-0190

Figure 4—26 Analog Preamplifier and Multiplexer Block Diagram
Multiplexer channel selection is controlled by the AD8-EA Analog-to-Digital Converter to allow random or sequential sampling of analog inputs. There are two modes of operation: Auto-Increment and Non-Auto-lncrement.
The mode of operation is selected by the AD LE instruction which loads the Enable Register in the A/D converter.

If bit 5 is a 1, the lNCREMENT ENABLE flip-flop will set and the multiplexer will be in the Auto-Increment
Mode. The Look-Ahead bits from the A/D converter will select channels 0 octal through 17 octal, in sequence.
If bit 5 is a 0, the lNCREMENT ENAB LE flip-flop will not be set and the MUX Register in the A/D converter
will be loaded from the AC to select a channel in the multiplexer.

HO E15 Vdc power is supplied by an H851 Edge Connector from the ADB-EA. The AM8-EA provides ’31 Vdc to
the AM8-EC analog panel, if it is part of the system. This voltage is applied to the four potentiometers on chan‘
nels 0 through 3.

4.3.1

Analog Preamplifier and Multiplexer Expander Block Diagram

The analog multiplexer expander (see Figure 4-27) consists of eight differential amplifiers, a Channel Select De-

coder, and eight analog switches. The input to the differential amplifiers is a i1V signal which will be amplified
to 15V for the A/D converter. The differential amplifiers have a gain of 5 and contain compensation cirCUits for

amplifier stability. Linearity is maintained by feedback networks and gain adjustments.

4-35

DIFFERENTIAL
AMPLIFIERS
:5v

ANALOG
NODE

IDIFFERENTIAL
I AMPLIFIERS

DIFFERENTIAL
AMPLIFIERS

l
MUXII—->

MUX10—————~

|
L——.——

mux09—>

CHANNEL
SELECT
DECODER

15V
A/D

CONVERTER

ANALOG

(A841)

SWITCHES
MUX8

—O C

W2 (IO-IT)

O—GL—Vm
WI (0-7)

8E-0206

Figure 4-27 Analog Preamplifier and Multiplexer Expander
Functional Block Diagram
The Channel Select Decoder will receive MUX8—MUX11 and will generate a low on one line to the analog switch.
This turns the switch on to choose that channel of data. The switch will be turned off with —15V when a high

output is supplied by the decoder to the gate of the switch. The analog switches are FET transistors which look
open with —15V on the gate, and short with UV tied to the gate. The output of the differential amplifier selected

will be fed through an edge connector to the A/D converter. MUX8 will be inverted and supplied to the second

multiplexer module, if there is one installed, to expand the system to 16 analog channels. The second module
will be selected when MUX8 is 1. The 0—7 or 10—17 jumper must be installed on the corresponding A232 module to allow correct channel selection.

4.3.2

Analog Preamplifier and Multiplexer Expander Detailed Logic

Figure 428 shows one of the eight differential amplifiers used in the preamplifier and multiplexer expander module. For this discussion, we will refer only to channel 1 (E9 circuitry). The

4.3.2.1

Differential Amplifiers

—

positive input to channel 1 is applied to pin FF, negative to JJ. Two adjustments are provided for this circuit.
R138 (bias) is an offset adjustment which sets to amplifier output (OUT 1) equal to 0V for UV input between
FF and JJ. The gain adjustment, R133, will set the amplifier gain to swing i5V for a i1V change across F F and

JJ.
Diodes D47 and D48 clamp pin 3 at 13V, while diodes D51, 052, D49, and D50 tend to keep E9 from going into

saturation when the output voltage begins to exceed i6V. This allows an 8-us

voltage and protects the circuitry'from damage.

recovery time due to input over-

Capacitor C33 rolls off the gain at about 30 kHz to give the am-

plifier a low pass characteristic and to stablize the circuit against oscillations.
g

The amplifier output circuit contains a number of resistances in series-to-ground connected to R131 on the am-

plifier output. When the gain is properly adjusted, 1/5 of the output voltage will appear on the wiper of R133.
This signal is fed back to the input to give the amplifier its inherent gain of 5. The voltage on R130 is varied by

4—36

:iR136
810K

@224

051

31k“

052

T—
qRIsa

OUT

D49

‘i D664

050

7F1N753

£21731

W‘J

7? 1 N753

7:0664

‘>1.96K

HQ GND

73133

GAIN

“00

3R137
<’10K

5RI34
{422

R185

{3,2530

—

1 5v

6N0¥~fi

§;R184
éwmsa
BIAS

"5K

HQ+15V
NOTE:

R184,185 OPTIONAL
8E-0207

Figure 4-28 Differential Amplifier

adjusting the potentiometer R138, which is reflected on the amplifier output as a dc offset.
are

optional resistors used to shift the offset above or below 0V.

R184 and R 185

R 131 serves as a current limiter to protect the

E9 operational amplifier from damage in case of a short circuit.

4.3.2.2

Channel Decoder and Analog Switches

The Channel Decoder (see Figure 4-29) will receive MUX8—MUX11 from the A/ D converter, decode the four bits,

and produce a low on one output line. The 8251 is a BCD-to-Decimal decoder which will produce a low output
on one

line to represent one number. As an example, 0011 on the input will produce a low on line 3 to allow the

channel 3 voltage to pass through the analog switch to the analog node. The truth table, logic diagram and pin
locator for the 8251 IC are shown in Figure A-7 of the PDP-8/E Maintenance Manual.
The FET transistors are used as analog switches. All but one of the switches will be cut off to select an output

channel. To cut off the switch, -8V must be applied from gate-to-source and 0V must be applied to turn it on.
As an example, assume channel 1 is turned off and pin 12 of E1 is high. 044 is turned on because of a current

flowing through R 180 to the base of 044 (clamped at 3.6V). Because 044 is on, the collector current will raise
the potential on R 172, turning 035 on and reducing the voltage on 027 to almost
now

—

15V. The gate of 027 is

negative, thus making the drain~to-source resistance of 027 very high, not allowing the channel 1 output to

appear on ANALOG NODE.

Turning the channel on involves the use of the MPX RETURN signal. The MPX RETURN signal, originating in
the A841 module, is identical to ANALOG NODE except that it is 0.7V (1 diodedrop) less. When channel 1 is

selected, the current through R 180 is removed from 044 and channeled through D73. 044 and 035 turn off
and the gate of 027 (the FET) starts rising towards +15V. As soon as this voltage is 0.7V higher than MPX

RETURN, diode D65 is turned on and the gate rests at a voltage equal to that of ANALOG NODE. The gate-tosource

voltage of 027 is now near 0V, leaving the drain-to-source resistance at its minimum, and allowing chan-

nel 1 to appear on ANALOG NODE. The rise time of the maximum change on ANALOG NODE (10V) should

be less than 2 HS.
4-37

CHANNELS
_A

HQ+15V

ANALOG NODE
MPX

RETURN

HL|.FK|
HK' FLI

HQ- 15V
C40

8 '17
+5V

MUX 11

MUX 10

MUX

FMI,HJI

FNI.HH|
FPI HFI

HA2
MUX 8

86-0208

Figure 4-29 Channel Decoder and Analog Switches

4.3.2.3

Reference Voltages

—

The AM 8-EA provides :1 Vdc and A or B $2.1 Vdc reference voltages (see Figure

430). The ’53 Vdc is used by the diodes on the input of the differential amplifiers to limit the input to :6 Vdc.
The i2.1V is taken off the diodes as shown in Figure 4-30. The diodes and resistors make up voltage divider networks to produce i3V. The 11V reference is generated in the AM8-EA and applied through a cable to the
AM8—EC panel, if it is installed, for parameter potentiometers. The i1V is produced by a voltage divider network

made up of a 6.2V Zener and resistors. The i15V HQ power is supplied to the voltage dividers from the H851

Edge Connector.
HQ+15V

HQ+15V

Ho-15v

A—-2.1V
B ”‘1"

R76

R75

+3v

HQ-15V

-3v

$R80

+1v

025

030

026

029

027

028

$1232

-1v

3.7.?

R3;
*

3E R77

‘flGZV

5E R78

;Le.2v

#:cw

sue
SEA-0328

Figure 4-30 AM8-EA Reference Voltages
4.3.2.4

Optional Multiplexer Configurations

The A232 preamplifier and multiplexer module is standardly supplied with a i1V input to achieve a i5V output

(gain of 5).

It is sometimes useful to a given application to be able to span other input ranges in a given experi-

ment or process measurement.

Should a user wish to have special input parameters, each channel can be adapted by changing components on the
module. Note that alteration of the module is not the responsibility of Digital Equipment Corporation, nor is it
the company’s responsibility to warrantee or maintain the module once it has been altered. Note also that alteration of channels 0 through

38 of a system will affect the operation of the parameter knobs of the AM8-EC panel.

These knobs have a i1V output, and feeding this into an amplifier of other than i1V input will not allow the
knob to properly span the full 10-bit range.

Table 4—5 shows the differences in values for the most useful input ranges. Channel 1 is cited as an example, but

again, it is not recommended that the first 4 channels be altered.
The components in Table 4-5 may be ordered from DEC using the part numbers shown in Table 4-6. All component changes are part-for-part replacements except in the case of R 184 and R 185.

Mounting holes for these op-

tional resistors are provided on A232 etch-revision D modules and higher. Lower revisions will require mounting
these parts on the module where convenient.

Any change to the module may alter any of the specifications stated for the unit so that parameters such as gain,
common

mode rejection, input impedance, etc., will vary in accordance with the part values and tolerances

utilized.

4-39

Table 4-5
Resistors for Changing Input Configuration

Input Range

R121

R122

R124

R127

R128

R132

R134

R130

R184

R185

’31 Standard

34.8K

4.7M*

1.96K

422

38.3

None

34.8K

4.7M*

1.96K

348

90.9

None

1.2K*

34.8K

68.1 K

68. 1 K

12.1 K

12. 1K

365K

2.61 K

422

90.9

None

:10

64K

3.48K

39K

2.61K

261

38.3

None

34.8K

4.7M

1.96K

348

90.9

1.2K*

None

68.1K

12.1K

274K

2.61K

422

None

1.2K*

68.1K

21.5K

1M*

2.74K

422

51.1

None

1.2K*

—-

—

—2

0— +10

68.1K

0—+5

*These resistors are 1/4W carbon composition devices; all other resistors are 1/8W 1% metal film units.

Table 4-6
AM8—EA Configuration Change Parts List

N323)”

Description

N311”

1303156

Resistor 34.8K 1/8W 1% 100 MFP

1302873

Resistor 261 1/8W 1% 100 MFP

1304833

Resistor 1.96K 1/8W 1% 100 MFP

1303155

Resistor 21.5K 1/8W 1% 100 MFP

Description

1303067

Resistor 422 1/8W 1% 100 MFP

1301506

Resistor 1M 1/4W 10% CC

1305121

Resistor 38.3 1/8W 1% 100 MFP

1305131

Resistor 274K 1/8W 1% 100 MFP

1309341

Resistor 4.7 Meg 1/4W 5% CC

1305515

Resistor 64K 1/8W 1% 25 MFP

1305122

Resistor 51.1 1/8W 1% 100 MFP

1305266

Resistor 365K 1/8W 1% 100 MFP

1303303

Resistor 2.61K 1/8W 1% 100 MFP

1304868

Resistor 2.74K 1/8W 1% 100 MFP

1305252

Resistor 68.1K 1/8W 1% 100 MFP

1303064

Resistor 75 1/8W 1% 100 MFP

1303313

Resistor 12.1K 1/8W 1% 100 MFP

1303037

Resistor 90.9 1/8W 1% 100 MFP

1305114

Resistor 3.48K 1/8W 1% 100 MFP

1301320

Resistor 1.2K 1/4W 5%

1302514

Resistor 39K 1/4W 5% CC

1304858

Resistor 348 1/8W 1% 100 MFP

‘

When an amplifier has been modified, the unit's bias and gain adjustment will have to be adjusted. The bias ad-

just (R138) should be set to switch the AC between 7777 and 0000 with the analog input 1/2 bit below midscale (see calibration procedure in Chapter 5 for set up). The value of 1 bit can be determined by dividing 9.76
mV by the amplifier gain.

Next, adjust the gain adjust (R 133) to switch between 0776 and 0777 when the input

voltage is 1-1/2 bits below full scale. Setting the input voltage 1/2 bit positive above negative full scale should
achieve the 7000—7001 switching point in the AC.

Slight readjustment of the gain and bias potentiometers

might be required to get the best symmetry near midscale.
For example, on a 0V to +5V amplifier, readjust gain and bias as follows:
a.

The gain is:

10V (output)

5V (input)
b.

1 bit

9.76 mV
2

=4.88mV~5mV

Set 0000—7777 switching point at:
2.500

.0025 E 2.498V

with bias potentiometer.

440

0'. Set 0776—0777 switching point at:

5.000

.0075 a 4.993V

with gain potentiometer.
9.

Check 7000—7001 switching point at:
0.000 + .0025

2.5 mV

Readjust gain and bias, if required, to obtain correct readings in the AC.
NOTE
The components utilized, and the environment in
which the A232 module operates, do not allow operation of unit at a gain greater than 5.

441

SECTION 4
POINT-PLOT DISPLAY CONTROL (VC8-E)

4.4

INTRODUCTION

The VC8-E PointPlot Display Control is made up of two quad modules which plug into the OMNIBUS. The

VC8—E consists of one M869 control module and one M885 D/A converter module. The two modules are joined

by H851 Edge Connectors. The inputs to the VC8-E are two 10-bit digital words from the AC, representing X
and Y coordinate data. The outputs of the VCB—E are two analog signals proportional to the digital input, and an

intensity pulse. The analog signals are 15 Vdc for display on an oscilloscope.
The VC8-E display control provides deflection

(1001,0777)

(0777,0777)

(0000,0777)

and intensity signals for DEC VR14, VR20,

Tektronix 611, 613, 602, or user oscilloscopes.
The display on the oscilloscopes is in the form
of a 10248 by 10248 dot array (see Figure 4-31).

(0'0)

(0777,0000)

(1001,0000)

The LAB-8/ E can produce a bright spot at any

point on this array and a series of bright dots
can be

programmed to produce a graphical dis(1001,1001)

play.

(0777,1001)

(0000,1001)

8E-0153

The basic VC8—E (see Figure 4-32) comprises
the following functional logic and controls:
a.

Figure 4-31 Point-Plot Display of Coordinate Data

OMNIBUS interface, lOT decoding, Skip, CLEAR AC, and Interrupt Control.

b. X-axis Buffer, D/A converter, summing amplifier, and bipolar line driver.
0.

Y-axis Buffer, D/A converter, summing amplifier, and bipolar line driver.

0’. Z-axis control consisting of INTENSI FY PULSE and CHANNEL SELECT signals for the oscilloscope.
e.

A color, 611, 613 controller available only on M869 Rev D and M885 Rev F or higher revs.

NOTE
The VRZO color display is no longer available at the time
of this printing.

However, information pertaining to the

VR20 control is supplied for information purposes.
The VC8—E receives two 10—bit data words from the accumulator for each dot to be displayed on the oscilloscope.

One word will represent the X—axis position and one word will represent the Y-axis position. This data comes
from bits 2—11 of the accumulator and must be in the range of i0777 (octal) (see Figure 4-33). Bit 2 is the sign

bit that determines the polarity of the dc voltage out of the Point-Plot Display Control (1

negative, 0

positive).

The 10 bits of data from the AC will be used by the Point-Plot Display Control to control analog switches (see

Figure 4—34) in series with the input to a summing amplifier. The analog switches, in conjunction with a weighted
resistor, will supply current to the input of a summing amplifier. Each switch that is turned on will supply a current to the summing amplifier proportional to its position in the weighted-resistor network.

The sum of all the

currents flowing through the individual switches and resistors will be proportional to the 10-bit octal value trans-

ferred from the AC. The switches shown in Figure 4-34 are mechanical switches, but the electrical switches (see

Figure 4-35) will perform the same function. A low input on the transistor will cut the transistor off and allow

4-43

diode D1 to conduct and supply current through the weighted resistor RW to the input to the summing amplifier.
A high input will cause the transistor to conduct; current flow will be through the transistor to ground and no
current will be supplied to the node by the weighted resistor.

Using two sets of analog switches and two summing

amplifiers (X and Y axis), along with the necessary control logic, the Point-Plot Display Control will produce
:5 Vdc analog signals for display on an oscilloscope.
CONTROLS
_

—

I
I

—

X*5VREE

LINE
DRWER

X-AXS
AMP

D/A

885

NEGAHVE
CURRENT
REFERENCE

X—AXIS
,

ACCUMULATOR

—

MODULE

l
|

CONVERTER

Y-AXIS

I
I

"esteem-Er

REFERENCE

LINE
DRIVER

Y-Axm
AMP

CONVERTER

I
._

CONTROLS

_I__

M869

|
__J

1 ”A885
I

MODULE

M 0 DU LE

INTENSIFY
(3 DIXY L)

lpsec
TIME

RIEEE
0R
TEXTROMX
602

INTENSITY
PULSE

DELAY

PULSE 3

I
MDO-MDI'I ——>

CONTROLS

DECODER

_________

LINE
DRIVER

I
J L__J
8E-0209

Figure 4-32

Point-Plot Display Control Block Diagram

SIGN

UNUSED

DATA

2's

COMPLEMENT)
85-0147

Figure 4-33 AC Input Data Format
The following instructions are decoded and used by the Point-Plot Display Control to control the generation of

analog data and an intensity pulse for an oscilloscope to display X and Y coordinate data.
Clear All Logic (DICL)

Octal Code:

6050

Operation:

Clears ENABLEs, flags, and delays.

Clear DONE Flag (DICD)

Octal Code:

6051

Operation:

Clear DONE flag.

Skip

DONE Flag (DISD)

Octal Code:

6052

Operation:

Skip if DONE flag

(1). Do not clear DONE flag.
4-44

RW1

o/cfi

Ai;v v1

0/07

Jm—qb

RWZ

SUMMING

t 5VDC

AMPLIFIER

TO OSCILLOSCOPE

RW3

0/0

RW4

‘m——0

c/c

RW5
__

0/6

o/c

gx/V\,

RWG

RW7

O/Gi

‘VVV

RW8

1>———0/0fi

RW9

#Nv

RW1O

4/cfi

+5V
REFERENCE

NEGATIVE

8E-0329

REFERENCE

SOURCE

Figure 4-34 Analog Switches and Summing Amplifier
+15v

1p———-fi—— +5v

4AA.

iRw
1

summme
AMP

*— 1

5VDC T0 OSCILLOSCOPE

INPUT
LOW=I
HwH=o

BE- 0330

Figure 4-35 One Analog Switch and Summing Amplifier
Load X Register (DILX)

Octal Code:

6053

Operation:

Clear DONE flag, load X, wait for settle, set DONE flag. Do not clear AC.

Load Y Register (DILY)

Octal Code:

6054

Operation:

Clear DONE flag, load Y, wait for settle, set DONE flag. Do not clear AC.

Clear DONE and Intensify (DIXY)

Octal Code:

6055

Operation:

Clear DONE flag, intensify, set DONE flag.

445

Load Enable Register (DILE) (see Table 4-7)

Octal Code:

6056

Operation:

Load Enable Register, clear the AC.

Transfer Enable Register to AC (DIRE)
Octal Code:

6057

Operation:

Transfer contents of Enable Register to the AC.

Table 4-7
Point-Plot Display Control Enable/Status Register
Bit Position

Signal Name
DONE Flag

Operation
Set (DONE

1) to indicate data point has been inten-

sified.
Write Through

When set to a (1) causes the 611 or 613 to go into a

write through mode.
7

Store

When set to a (1) causes the 611 or 613 to go into a
store mode. When equal to a (0) causes the 611 or 613
to go into a non-store mode.

Erase

When set to a (1) will cause the 611 or 613 to initiate
an erase

Color

cycle.

When color is set to a (1), the controller is in a red mode.
When color is set to a (0) the controller is in a green
mode.

CHANNEL

When CHANNEL SELECT is set (1), channel 2 is se-

lected; when it is cleared (0), channel 1 is selected.
11

INTERRUPT ENABLE Flag

When INTERRUPT ENABLE flag is set (1), an
lNTERRUPT can be generated to intensify the display,

after the display settles.

NOTE:

4.4.1

Bits 1—5 are not used by the Enable/Status Register.

Functional Block Diagram Description

The primary logic functions are indicated by the blocks in Figure 4-32. The Device Select logic ensures that the
processor is communicating with the display control, and not some other device.

It receives bits MD3—MD8,

decodes them, and when a 605x is decoded, sends SELECT L to the Operation Decoder so that it can process

bits MDQ—MD11 to determine the operation to be performed. The l/O PAUSE signal is used as a gating input to
ensure that the

instruction is an IOT instruction.

|/O PAUSE is generated 150 ns after TP1 of all IOT instruc-

tions. (See the PDP-8/E Maintenance Manual for more information on IOTs.)
The Operation Decoder begins to function when the Device Select logic asserts INTERNAL I/O L. The Operation Decoder looks at bits MDQ—MD11 and determines what type of instruction is to be performed. The Opera-

tion Decoder then enables the necessary blocks to perform the instruction.

If the instruction is to Load X Regis-

ter (DlLX), the Operation Decoder will cause LOAD ENABLE and LOAD X to be generated; the X-axis data will

then be loaded into the X Holding Register from the AC.

446

If the instruction is Load Y Register (DILY), the de-

coder will generate LOAD ENABLE and LOAD Y to allow the contents of the AC to be loaded in the Y Holding

Register. The instructions will also set up CO and C1 to transfer data from the AC to the Holding Registers. The
input data gate (see Figure 4-32) is used to transfer X- and Y—axis data from the Data Bus to the X- and Y-axis

Holding Registers. The DIXY and DI LY instructions are used to generate LOAD ENABLE and to enable the
gates to load the X- and Y-axis Buffer Registers (see Paragraph 4.2.6).
The Buffer Register is a 74193 lC with its control input pulled high at all times by +5V through a resistor. When
the Buffer Register is loaded, the 12 bits of data will be applied immediately to the analog switches because the

control input is always high.
The analog switches are in series with the input to the summing amplifier. Switches that are turned on will supply
current to the summing amplifier.

off, the switch in that position.

Each bit will be applied to its respective analog switch and will turn on, or cut

A logic 0 (high) in the AC will cause current to be supplied to the summing

amplifier input by the weighted resistor; a logic 1 in the AC will cause the current to flow to ground through a
transistor. The sum of the current supplied to the node (summing amplifier input) will produce an output from
the summing amplifier proportional to the digital input. The summing amplifier will supply i5 Vdc to the line

drivers which act as boosters to drive the deflection circuits in the oscilloscope.
The DIXY instruction will be delayed, and after the X and Y Registers have been loaded, the DIXY instruction
will be used to intensify the dot on the array to display the X- and Y-axis data. The Operation Decoder will decode this instruction, and when TF3 is generated, the intensity puise wiii be generated by a one-shot and be ap-

plied to the display circuits. The intensity pulse will be delayed 6 its for the Tektronix 602, 100 us for the 611
or

613, 21 us for the VR14, 21 us for green and 16 us for red for a VR20. The delay and pulse polarity are

selected by SW1 and SW2 on the M869 module. The delay allows the deflection circuits in the oscilloscope to
settle before intensifying the oscilloscope. The delay switch, marked LONG and SHORT, will be set to LONG
for the VR 14, VR20, 611 and 613 and to SHORT for the Tektronix 602. The Z-axis switch, marked + and —,
will be set to + for the 602, 611, 613 and

—

for the VR14, and VR20. The positive and negative reference volt-

ages are applied to the node and switches to supply a constant current source.

The Channel Select logic is used to select a channel on the oscilloscope for data display. The Dl LE instruction
will be decoded, and if data-bit 10 is a 1, the CHANNEL SELECT flip-flop will set and select channel 2.

If the

flip-flop is not set, the data will be displayed on channel 1.
An Interrupt will be generated by setting the DONE flag if the INTERRUPT ENABLE flip-flop is set. The DISD

instruction will generate a Skip after the display has been performed if an Interrupt is not used.
used if it is necessary to use all available time for performance of an instruction.

Interrupts are

If an INTER RUPT ENABLE is

set, the processor can perform instructions while waiting for a DONE flag.
The Enable/Status Register contains INTERRUPT ENABLE, the DONE flag, and a CHANNEL SELECT flip-flop,

color flip-flop, erase, store, and write through. The INTERRUPT ENABLE flip-flop can be set by transferring a 1
in bit position 11 from the AC, using the DI LE instruction. Channel 2 is selected by transferring a 1 in bit position 10, a 0 will select channel 1; color (red) can be selected by transferring a 1 in bit position 9, a 0 will select
green; a bit in position 8 will select an erase; a 1 in bit position 7 will select a store mode, 0 will select a non~store

mode; a 1 in bit position 6 will select a write through. The status of the DONE flip-flop (set

1) can be checked

using the DI RE instruction to transfer bit position 0 to the AC for checking. The Dl RE instruction also transfers
bits 6, 7, 9, 10, and 11 to the AC to show the channel selected, the status of the INTERRUPT ENABLE flip-flop,
and the status of the color, store, and write through flip-flop.

4-47

M03

L—--—C
66

—c

M04

“33

BTP3

‘10:

BTP3

—————o—

M05

L-E—ZC
E6

0—0
L

M07

E11
4

L——O

—40

IOT

5
4
6

(CLI)INTERNAL I/O

£9

0—~

0—50
M08

+5v

1/0 PAUSE

E14

R1
+5v

81717
M09

E14

‘-

12
11

DICL

m2?-

DICD

0180

DILX

DILY

1
C

30*
E15
3251

4'3

L-—-———-C

\14
E14

L<1
DIRE

o____/j

‘100
M011

0023

L‘—1——C
‘

M010

~20

E14

5,3

DIXY L

\ 13

15A

634

DILE

735

DIRFL

E13

CO L

DIRE H

E12

C1L

8E-0211

Figure 4-36

Device and Operation Select Logic

4.4.2

Point-Plot Display Control Detailed Logic

4.4.2.1

Device and Operation Select Logic

—

The Device and Operation Select logic (see Figure 4-36) decodes

MD03-MD11 and selects the device and type of operation that will be performed. MD3—MD8 are gated for each
MD Line by I/O PAUSE. An internal I/O PAUSE signal is generated in the timing generator whenever MD bits

0—8 are decoded as a 65 (octal). The 8251 IC is a BCD-to-Decimal Decoder that will provide low outputs on one

line; e.g., MD9—MD11 is 011. Pin 3 will have a low output, indicating that this is a 6053 (DILX) instruction. The
truth tables, logic diagrams, and pin locator for the 8251 IC are in Appendix A of the PDP-8/E Maintenance Manual.
The output of the Operation Select logic will provide signals to enable Interrupt logic, select the C lines, allow

loading of the X and Y Registers, generate a Z-axis pulse, and clear the logic after the data is displayed.
C1 and C0 control the direction of data flow between the AC and the Data Bus. C0 and C1 should be high for
data to be transferred from the AC to the Data Bus; they are not asserted for a DILX or DlLY instruction. A
DI LE instruction will assert C0 to transfer data from the AC to the Enable Register and then clear the AC. The
Dl RE will assert both C0 and C1 to JAM-transfer the contents of the Enable/Status Register to the AC.

Timing Pulse 3 logic is shown with the Device and Operation Select logic in Figure 3-36.
a

The logic will generate

high and low output to enable various gates for DI LY and DILX instructions in the Point-Plot Display Control

logic during EXECUTE.
4.4.2.2

Enable/Status Register

—

The Enable/Status Register consists of the CHANNEL SELECT, COLOR

SELECT, ERASE, STORE, WRITE TH ROUGH, INTERRUPT ENABLE, and DONE flip-flops (see Figures 4-37
and 4-38). The Enable/Status Register will provide signals to enable the interrupt system, select a channel in the

oscilloscope for displaying data, select color, store, write through, produce an erase cycle, and provide status bits
to be transferred to the AC.

4.4.2.2.1

DONE Logic

—

The DONE flip-flop on the M869 module is used to indicate the completion of the

display and to generate an Interrupt if the INTER RUPT ENABLE flag is set (1) (see Figure 4-39).
DONE can be cleared by any of the inputs to pins 1, 4, 2, or 5 of E2. INITIALIZE or CLEAR H, applied to pin 1,
will be applied to the clear side of DONE and will clear the flip-flop. The DICD and DIXY instructions applied to

pins 4 and 2 will clear the DON E flip-flop. When changing color or generating an erase, the done flag will be

cleared by CLEAR DONE L on E 19 Pin 11. The DIXY instruction is used to clear DONE to ensure that it will
not be set before the LOAD DELAY signal is applied to the clock input.

LOAD ENABLE, which is pulled low by

DI LX or DlLY, is present at pin 8 of E16, or pin 13 of E13. DONE will be cleared by the load instructions to ensure that it is not set

until the LOAD DELAY signal is applied to the set input.

DONE will be set by LOAD DELAY, which is generated by LOAD ENABLE and TP3. LOAD DELAY will be

delayed 21 us for the VR14; 16 ,us in red, 21 us in green for the VR20; 100 us for the 611, 613; and 6 us for the
Tektronix 602. SW2 will select the delay time by selecting C24 or C20 in the LOAD DE LAY network. SW2 will
be set to the LONG position for the VR14, and to the SHORT position for the Tektronix 602. When the VR14,
or

VR20, 611, 613, or Tektronix 602 are not used, the user should refer to the handbook for the oscilloscope

being used and see Paragraph 3.2 for information on interfacing an oscilloscope with the VC8—E. A JUMPER is
provided to select either VR14, VR20 delay or 611, 613 delay (refer to E-CS-M869-0-1).
When LOAD DELAY is applied to pin 3 (clock), DONE will set and apply a 1 to E8 and E9.

If INTERRUPT

ENABLE is set (see Figure 4-39), an Interrupt will be generated. DONE will also enable E9 pin 3 to allow a skip
if the DISD instruction is performed.

If the DI RE instruction is performed and DONE is set, DATA 0 will be gated

to the Data Bus to indicate the status of the DONE flag.
not set, when the DIRE

A high will be transferred to the Data Bus, if DONE is

instruction is executed.

LOAD X, LOAD Y, and LOAD ENABLE will be used to load the X- and Y-axis Holding Registers in the M885
module.

449

DIRE

H———-J
12

+3V

Brr1o H
4

DATA 10 L

mo
DILE

L-1

DIRE

DAtA11 L

7
e

BIT n

+5V

+3v

J)
12

-—C‘

_2:(:
L

CHANNEL

R12

CLEAR

0917

BTP3

E10

EZ
CHAN

,_3_ C
LOAD ENABLE L

E3
INT
EN
n

+3v

—3C
13
CLEAR

8E-02l2

Figure 4-37

Enable/Status Register

4.4.2.2.2

INTERRUPT ENABLE Logic

—

INTERRUPT ENABLE is used to enable the Interrupt logic shown in

Figure 4-39. INTERRUPT ENABLE E3 will be cleared by CLEAR L from the programmer’s console, or by the
DILE instruction ANDed with TP3 at E16 if DATA 11 is low. When DATA 11 is high, the INTERRUPT ENABLE

flag will set.

DATA 11 is transferred to the M869 module by the DILE instruction (see Figure 4-37). DI RE on

pin 9 of E8 will enable E8 and will allow the set side of E3 to be applied to the Data Bus. The set side of E3 will
be transferred to the AC by a DIRE instruction to indicate the status of the INTERRUPT ENABLE flag.

4.4.2.2.3
on the

CHANNEL SELECT Logic

—

The CHANNEL SELECT flip-flop E2 will be used to select one channel

oscilloscope for display of data (see Figure 4-37). DATA 10 is transferred from the AC by a D l LE instruc—

tion to set E2 if bit 10 is low, or clear E2 if bit 10 is high. DILE out of E13 and E10 will enable E5.

If DATA

10 is low, E2 will set and select channel 2. If DATA 10 is high, the data input to E2 will be low and the clock in-

put from E16 will clear E2 to select channel 1. The set side of E2 is tied to pin 12 of E8 and the DIRE instruction will enable E8. When E2 is set, a low (1) will be transferred to the AC to indicate channel 2 is selected.

When E2 is cleared, DATA 10 will be high (0), and will indicate channel 1 is selected when DIRE is executed.

CHANNEL N0.
1=CHANNEL 2

DONE=1

INTERRUPT ENABLE

_l l—I=ENABLED
“l
I011|213|4i5|6l7l8l9|10|11|
F—fl

NOT USED

—b'
8E-0331

Figure 4—38
4.4.2.3

Enable/Status Register Word Contents

INTENSITY PULSE GENERATION

—

The intensity pulse for the system is generated when a DIXY

instruction is fed to the control module. It will be gated by TP3H and applied to a 2 us one-shot or a 6 us oneshot. When color (0) H is low and non-store is high, this will reverse bias D1 and switch in R18. The time will
be determined by R18 and C40 and will produce the 6 us intensity pulse. When non-store (H) is high and color

(0) H to high, this will fon/vard bias D1 and put R18 in parallel with R17. The time will then be determined by
R18 in parallel with R17 and C40, and produce a 2 us intensity pulse. The delayed output will feed to the

Polarity Select switch. The intensity pulse is applied to an amplifier in the M885 module for pulse shaping and
amplification. The amplitude of the pulse can be changed by the A—B jumper to select R58 or R59. With the
jumper installed as shown by the dotted lines in Figure 4-40, the pulse will be +4V to —2V. If the jumper is re—
moved and placed between the other two split lugs, the pulse will be +4V to —10V. The jumpers will change the

amplitude of the voltage, but the polarity will be determined by the position of SW1 in the M869 module.
4.4.2.4

Data Gates

—

The Data Gates (see Figure 4-41) receive their inputs from the Data Bus when the DI LX or

DILY instruction is executed. LOAD ENABLE, also generated by these instructions (see Figure 4-39), will enable
the Data Gates to apply the 10 bits to the X and Y Holding Registers. Data Gates for bits 02—09 are located in
the M885 module; the gates for bits 10—11

are

located in the M869 module. Bits 10 and 11 are applied to the

Holding Register through the H851 Edge Connector.
4.4.2.5

Holding Registers

~—

The X- and Y-axis Holding Registers (see Figure 442) will receive inputs from the

Data Gates when the DI LY and DILX instructions are executed, and will provide outputs to the analog switches.
The Holding Registers consist of three 74193 ICs for each axis.
locations of the 74193 IC.)

(See Appendix A for the logic diagram and pin

Figure 4-42 shows only the X Holding Register, but the Y Holding Register is iden-

tical. The LOAD X or LOAD Y generated by DILX or DILY (see Figure 4-38) will enable gates in the IC to load
bits 02—11 into the Holding Register. The output of the Holding Register will be applied to the analog switches

(see Figure 4-43).

4-51

CLEAR H

(FNU

CLEAR

+5V

INITIALlZE H

CLEAR

B DICD
1

BTP3

L——C2

DICL

Lie

B DIXY
8 LOAD

ENABLE

+5v

01cc

1°

BTP3

L-—30 E12

3917

+5v

€24

2700pf

LONG

sw2
€20

R10
22“

SHORT

520m
1

oxxv

E12

4‘

E18

‘LOAD ENABLE L

E19
LD

H 4

DEL

+3V———BTP3
BTP3 H

LXH

5
6

o—

LD DEL L

E13

INTERRUPT
-—LOAD

DILY L

E12

INTERRUPT

ENABLE

SKIP L

1»—

LY “‘3
BTP3 H

0180 1.
D---LOAD

E13

LOAD

DIRE

DATA 0 L

85-0213

Figure 4-39

DONE and Interrupt Logic

[-:;869

-1

‘

+5v

R7
(:23

47mm:

BDIXY

13
'

105:“

J ipsec

BTP3 H——-——
4
”V

sw1

+5v

+5V

£1258

:; R56
1

IKE

R59

inc
f
c 23

l.___j(__

R61

>°'3

+5v

caz

333.5

~<Z>Z AXlS

vvv

‘——‘l

55’.“

5014

C24

ih————-|E——0

+15v

‘in62

:E R63

—

8E-0218

Intensity Pulse Logic

Figure 4—40
4.4.2.6

Analog Switches and Summing Amplifier

—

The analog switches, weighted resistors, and summing ampli-

fier will receive 10 digital bits as input and will supply a :5 Vdc output (see Figure 4-43). The digital input will
turn on or cut off the switches which supply current to the summing junction.

The summing junction is tied to

the input of E17. The sum of the currents supplied by the analog switches will produce a voltage on the output
of the summing amplifier which is proportional to the contents of the Holding Register.

The analog switches (see bit 11 in Figure 4—43) supply current from the +5V reference to the summing junction

through D3 when a low input is applied to the base of Q1. The current supplied will be determined by the resistance of the weighted resistor R99.

The current produced by turning off 01 and allowing D31 to conduct will be

approximately 5V/Rw; Rw being the value of R99. D30 and D33 are added to the least-significant bit positions
to isolate the transistor capacitance from the summing junction.

When a high input (1) is applied to 01, the

transistor will cut off D30 and all the current will flow through the transistor to ground.

The negative reference is used as a constant current source for the summing junction.

017, 018, and the Zener

diodes in the negative reference will supply a constant current. R88 will adjust the output of the negative refer-

summing amplifier to span the full range of voltages for the i0777 octal input to the analog

ence to allow the

switches. The negative reference offsets the amplifier output by +5V.
The E17 summing amplifier is a feed-back amplifier that tries to seek the same voltage on both inputs. The current supplied by the analog switches and weighted resistors will flow through the feed-back resistor.

The output

will adjust in a negative direction to drop the amOunt of voltage necessary to satisfy Ohm's law (V=l R). 029 and

030 are boosters that drive the oscilloscope circuitry.

4.4.2.7

Positive Reference Source

——

The +5V reference is used by the analog switches to supply a constant cur-

E14 and E 15 are adjusted to maintain a constant output current

rent to the summing junction (see Figure 444).

The output will be adjusted to 5.12V :5 mV and the amplifiers will maintain this level as current requirements
V

change.

1
I

DATA 09
LOAD ENABLE

DATA 10

M869

B—DATAW I
DATA 11

{:3—
1-:5

LOAD ENABLE

I—

Figure 4.41

+5V

DATA 11

DI 09

DI 08

0107

0106

x10

‘9

LOAD XH
————1 11

x09

0105

0104

LOAD

——

1
XS

x03

15
1

x02

9
x5
~————

9
11

‘

LOAD
x

E5
13

0103

0102 H

X08

5
x7

15
j

Data Gates

5
x11

15
DATA 10 H

DATA 11 H

I
I

+5V

I I

I
I
|

DI 09“

I13

BE-0334

Figure 4-42 X-Axis Holding Register

4-54

-15V HQ.

+ 5v

+15v

REFERENCE
______

"°'

-—

“023 R1031E

R98

“035

243110

“036

R1061:
121K‘

—

‘

—

R132

R138

0.__.

R99
511nm

—

«:R104

2;R136

R133
2011

qmo
‘>

:’ 256m

0341!

+15V

037

0——

$030

1331

lav.
KPCBS
9’

R137

D33

4w:

R143

R144

Y ANALOG

“052

051

+5v

029

c36‘

RI39

E17

A Av r

N»
5

K053

‘

1’
l

Y11'

Y1O

C41

‘v‘v‘v

-15V

R147

eE-0335

Figure 4—43 Analog Switches and Summing Amplifier
+15VHQ

3'0"

R51

024?

390 4"

011

R50§
317K

$1153

(9-2"

areas
+15VHQ
7
3

R551}

E15

D—-——————-————+5V

R54;

:ER52

Teas

III—
65-0219

Figure 4-44 +5V Reference

455

SECTION 5

BUFFERED DIGITAL I/O (DR8-EA)

4.5

INTRODUCTION

The DR8—EA 12-channel Buffered Digital l/O provides 12 digital inputs and 12 digital outputs. The DR8—EA is
contained on one M863 quad module inserted into the OMNIBUS. The M863 module consists of an Input Regis-

ter, Output Register, AC Bus Register, and control logic. The Input Register will receive 12 bits of data from the
outside world or from the AC, with instructions. The Output Register will receive data from the AC and supply

12 bits of data to the outside world. The contents of the Output Register may be transferred to the AC or cleared

by 1’s from the AC. The AC Bus Register will select the contents of the Input or Output Register for transfer to
the AC.
ers or

Inputs and outputs are TTL compatible (low true), giving the user the option of providing level convert-

signal conditioners. Each input may monitor an external line directly, or may sense the occurence of a

negative-going transition. Skip and Interrupt capabilities are provided for the Input Register when the IN flag is
asserted. Up to eight DR8—EA modules can be utilized in one system, but if an ADS-EA is installed, only seven
DR8—EA modules can be used. The DR8-EA is connected to the outside world by a DR8—EB panel, one for each

module, or two BC08J cables tied to the J1 input and the J2 output on the M863 module. The DR8—EB panel
has two M904 modules for connecting user cables to the panel.

4.5.1

Buffered Digital l/O Functional Block Diagram

The basic module is divided into two sections:

12-bit digital inputs and 12-bit digital outputs (see Figure 445).

The 12-bit digital Input Register consists of 12 flip-flops and associated circuitry. Each flip-flop can be cleared

by an IOT instruction (DBCI) in which the AC clears the respective bits in this register. INITIALIZE will clear
all flip-flops. Each flip-flop can be set independently by a signal from the outside world.
select either the flip-flop output, or go directly to the Buffer OMNIBUS.

Jumpers can be used to

Each jumpered bit can be read (DBRI)

into the AC. All jumpered bits are ORed together to form a Skip condition if pulled by the computer (DBSK),
or to cause a

Program Interrupt if Interrupts are enabled (DBEI) and jumpers are installed to assert the IN flag.

DEVICE AND
OPERATION
SELECT
DECODER

MDZ-MDII

I/O

LAB 8/E

ACCUMULATOR

PAUSE————-—1
TRANSFER
INPUT
T0 AC

INPUT

OUTPUT BUFFER

BUFFER

SELECT OUTPUT

FROM

INPUT DATA

OUTPUT DATA

(FROM OUTSIDE WORLD)

(T0 OUTSIDE WORLD)

12 BITS

12 BITS
sE-ozzo

Figure 445

Buffered Digital I/O Block Diagram

457

The 12—bit digital output flip-flops can be set, each bit independently, by the DBSO instruction and respective 1's
in the AC. The DBCO instruction clears the respective flip-flops in the AC; lNlTlALlZE will clear all flip~flops.

Jumpers are provided so that the device code 5X can be used, where X is 0 through 7, allowing use of eight
DR8—EAs if an AD8-EA is not used. When the AD8—EA is installed, octal code 53 is illegal; therefore, only seven
DR8—EA modules can be used.
When an IOT cycle using a 65XX octal code is selected, the instruction will be decoded by the Operation Select

logic and will allow data to be transferred from the outside world to the AC, or from the AC to the outside world.
Programmed instructions can also clear the Input or Output Buffers when the DBCO or DBSO instructions are
executed.

The following programmed instructions are decoded by the Operation Decoder and used to perform operations
in the Buffered Digital I/O:
Disable Interrupts (DBDI)

Octal Code:

65X0

Operation:

Disables all Interrupts.

(X808 through 78, dependent on jumper)

Enable Interrupts (DBEI)

Octal Code:

65X1

Operation:

Enables Interrupts.

Skip on INPUT Flag (DBSK)
Octal Code:

65x2

Operation:

Skip on INPUT flag.

AC Clear Input Register (DBCI)

Octal Code:

65X3

Operation:

1’s in AC clear respective bits in Input Register.

Transfer Contents of Input Register to the AC (DBRI)

Octal Code:

65x4

Operation:

The contents of the Input Register are transferred to the AC.

Clear Output Register (DBCO)

Octal Code:

65x5

Operation:

1’s in AC clear respective bits in Output Register.

AC Set Output Register (DBSO)

Octal Code:

65X6

Operation:

1’s in AC set respective 1's in Output Register.

Transfer Output to AC (DBRO)
Octal Code:

65x7

Operation:

Transfer contents of the Output Register to the AC.

4-58

Buffered Digital l/O Detailed Logic

4.5.2

The detailed logic of the Buffered Digital I/O is divided into the following functional groups for purposes of discussion:

Device Select and Operation Decoder

Interrupt and Skip Logic

Input and Output Registers

4.5.2.1

Device Select and Operation Decoder

The Device Select logic in Figure 4-46 will have bits MD3L—

MD11 and I/O PAUSE as inputs. I/O PAUSE will be generated 150 ns after TP1 of any IOT cycle.

In the Buf-

fered Digital I/O, it will enable the AND gates to allow decoding of MD3L—MD8L. When these gates are enabled
and a 6X octal code is present, a SELECT H and INTERNAL I/O are generated. SELECT H will be used to enable
the Operation Decoder.
The device code can be changed by changing jumpers in the Device

Table 4-8

Select logic. Table 4-8 shows the jumper combination required for

IOT Device Code

each code. Octal 50 is the normal configuration and the unit comes
_

from the factory With this code selected.

Octal Code

Jumper

*53

The 3-bit input to the BCD-to-Decimal Decoder will qualify one gate

and produce one low output; all other gates will be disqualified. As

The Operation Select logic will receive bits MDQL—MD 1 1 L. When

SELECT H is present, these bits will be gated to the Operation

Decoder, which is a BCD-to—Decimal Decoder. The logic diagram, the
truth table, and pin locations are shown in Appendix A of the
'

PDP-8/E Ma/ntenance Manua /.

example, 011 on the input would enable gate 3, pull line 3 low,
_

and allow the DBCI Instructlon to be executed.

4.5.2.2
an

Interrupt and Skip Logic

—

*Device Code 53 cannot be used if the ADS-EA
is instaued,

The Interrupt and Skip logic (see Figure 4-47) is used to generate a Skip or

Interrupt request when the IN flag is asserted, indicating that data has been transferred to the DR8—EA Input

Register. To generate an Interrupt request, DBEI must be executed to set INTERRUPT ENABLE E9. The DBEI
instruction is ANDed with TP3 and applied to the set input of E9 to set INTERRUPT ENABLE.

If INTERRUPT

ENABLE is set, the IN flag applied to E48 will generate an Interrupt request and a subroutine may be performed
to transfer the contents of the Input Register to the AC.

INTER RUPT ENABLE is cleared by the execution of

the DBDI instruction or by INITIALIZE.
The DBSK instruction will be ANDed with the IN flag to generate a Skip if the DBSK instruction is programmed.

Note that the IN flag is pulled low by data inputs when the proper jumpers are installed in the Input Register (see

Figure 4-48).
C-Iine Select logic (see Figure 4-47) is used to control the direction of data flow between the registers and the AC.
DBRI will assert C0 and C1 to allow the contents of the Input Register to be transferred to the AC. DBRO will
assert CO and C1 to allow the contents of the Output Register to be transferred to the AC.

4.5.2.3

Input Register and Control Logic

world at J1.

—

The Input Register (see Figure 448) receives inputs from the outside

Inputs from J1 will be applied through an inverter to the clock input of the flip-flop in the Input

Register. The data input is high at all times; therefore, a 1 applied to the clock input will set the flip-flop. The
output of the Input Register is taken from the set side and applied to a group of split lugs that can be jumpered.

4-59

MD03 L

API

—\

M004

Lfl—Jiq

M005

E43

)

BLI

<>———EL3
BMI

—-H—---

5d
E43

H?
------

E46

CLI

INTERNALI/O

——0

0L6

BPI

E43

M006 L

MDO7

____100
__9_..o

SELECT H

0L7

L-——T—C
..___6d

M008 L—

-—"'—8-——

E43

0L3+5v
R51

0917

1/0 PAUSE

£39

L—fiq

E40

E44
6

SELECT

H‘5DO-0-C

M009 L

DLI

E49

D!Efl

12 DBEI

—o

3—

Mo
M010 1.

0M!

E49

E311013s1<
8

3100001

__0

22:;

0—0
MD11L

091

E49

SDBRI

330300

_q
2

u——00

40050

0500120

151252
1
+ 0' <

86- 0313

Figure 4-46

Device Select and Operation Decoder Logic

DBEI

E47

12
‘

12
BTP3

H——0

E
N

5&3

1°

543

CP'

INTRQSTL

INlTALIZE—L TE

E4?
0801

E47

5
,

R53
1239
IN FLAG L

14>2

DBSK

6
.

E44

E45

SKIP L

DBRI

E42

DBRO

TP3

CS'

E45

CEI

E45

CHI

p—w

BTP3 H
10

INITIALIZEH

14
0

B INIT L

BE» 0221

Figure 4-47

lnterrupt and Skip Logic

The output of inverter E2 is also applied to the split lugs. The jumpers can select the high input from the inverter
or from the set side of the

flip-flop and apply it to the AC Bus Register. The set side of the flip-flop can also be

jumpered to an inverter (see

E8 in Figure 4-48) to assert the IN flag. The W flag will generate an Interrupt re-

quest if it is asserted and INTERRUPT ENABLE has been set by the DBEI instruction.
The lnput Register can be cleared by 1’s from the AC when a DBCI instruction is performed. To clear a flip-flop,

there must be a 1 input to an AND which is enabled by the DBCI instruction (see E3 Figure 4—46). Inverter E1,
which has its output tied to E3, will receive BOO H from the Data Bus. The contents of the AC (see Figure 4-48)
will be applied to AND gates (see E6 in Figure 4—48); the gates will be enabled by SELECT H which is present on
any instruction to the DR8-EA. The outputs of the AND gates (BOO H—B11

H) will be applied to the gates en-

abled by the DBCl instruction (see Figure 4—48). The DBCI and the output of E1 will enable E3 and be applied
to E2. The output of E2 is tied to the clear side of the flip-flop; a 1 will clear this bit.

The Input Register will

also be cleared if CLEAR or INITIALIZE are applied to E2.

4.5.2.4

Output Register and Control Logic

—

The Output Register (see Figure 449) receives inputs from the AC

and applies them to the outside world. The Output Register can be cleared by 1’s in the AC and the contents

transferred to the AC.
To set the Output Register flip-flops with 1’s from the AC, the data bits tied to E6 (see Figure 4-49) will be gated
to E5 by SELECT H.

Note that data bits 03L

—

11L are tied to identical gates and only bit 00 will be discussed.

E5 will be enabled by the D880 instruction from E2 and the data input (1) will set the E16 flip-flop. The set side
of E16 is applied to inverter E14, and then to J1 which is connected to the outside world. The DBCO instruction
and TP3 will enable gate E7 and a 1 from the AC (data 00

clear it.

461

——

data 11) will be applied to the clear side of E16 to

AC BUS REGISTER

IN\H

INOO

INFLAG

('3

:OA
6:

:
E?

E12

513

ul—Dk

IN FLAG

———————————

——

—————

CLR 0 H ————-1

E10

—

BINIT L

E11

39'?
BOOH

BHH

BTP3 H
E42

DBCI

+5v

+5v
47a

T
t

azoo

INOOL

INHL
8E-0336

Figure 4-48

Input Buffer Register and Logic

+5v

+sv

OUT 00L

J|,D
R2

$121

J|,DD

1§R4

OUT 11L

+5v

Um,

’

E15

E14
00 L

l—OUT

Tom

11 1.

1
E16

BINIT L

E“

________

DBCO
res L

C—fi
E3

————————

'———<J_J
DBSO

:fl
*0_/
E2

—————————

-—

B11(1)H

30011111
E10

SELECT H

________

DATAIOO L—0—-—-AC eus REGISTER

AL eus REGISTER en 11

DATA 11 L.

BIT 0

8E~0337

Figure 4-49 Output Register and Logic
The clear sides of the flip-flops in the Output Register are applied to the AC Bus Register (see Figure 4-50) for
transfer to the AC when a DB RO instruction is performed.

INITIALIZE will clear all flip-flops in the Output

Register as it is tied to the clock input and the data input is grounded. A high on the clock input from the inverter will clear the

flip-flop if the data input is low.

DBRI
DBRO

OUT 00 L
IN

00 L

OUT 01

OUT 02

OUT 03 L
IN

o
OUT 04 L

BO
A0

DATA 00 L

04 L

OUT 05L

81
A1

DATA 01

05 L

‘

OUT 06 L

‘82
A2

DATA 02 L

06 L

OUT 07 L

S‘DATA 03L

8235

07L

o
OUT 08 L

BO
A0

DATA 04 L

08 L

OUT 09L

‘DATA 05 L

82
A2

DATA 06 L

DATA 07L

8235

09 L

OUT

10 L

OUT 11

7,
80

DATA 08 L

AC
81

DATA 09 L
‘

82
4

DATA 10

DATA11

‘

‘83

8235

8E-0338

Figure 4-50 AC Bus Register

4-63

4.5.2.5
IN 00 L

AC Bus Register
—

—

The AC Bus Register (see Figure 4-50) will have OUT 00 L

OUT 11 L and

IN 11 L applied to it from the Output and Input Registers. The AC Bus Register will select the con-

tents of either the Output or Input Register to be applied to the Data Bus for transfer to, or from, the AC.

The

DBRI and DB RO instructions are applied as control inputs for the 8235 lC. See Appendix A of the PDP-8/E
Maintenance Manua/ for the truth table, logic diagram, and pin locator for the 8235 1C.

DB R0 will enable gates

to select the Output Register contents; DBRI will enable gates to select the Input Register contents.

output will be applied to the Data Bus to load the AC.

4-64

The selected

SECTION 6
REAL-TIME PROGRAMMABLE CLOCK (DK8-EP)

4.6

INTRODUCTION

The DK8—EP Real-Time Programmable Clock consists of two PDP-8/E quad modules that plug into the OMN lBUS
and are interconnected by an H851

Edge Connector. The M860 module, Real-Time Clock Control, contains a 12-

bit binary counter, a 12-bit buffer register, and logic. The logic controls the counter/ register operation and the

companion quad module operation. This second quad module is the M518, containing Input logic and Schmitt
triggers. Included on this module is a 12-bit storage register, logic that derives five different clock frequencies
from a crystal-controlled oscillator, and three Schmitt trigger circuits that enable the user to control certain clock

operations from external sources.
The DK8-EP provides a programmable time base that allows the user to control and/or record the occurrence of
events both internal and external to the PDP-8/E. The clock can be used to count the number of events in a given
amount of time, to measure the amount of time between two given events, or to initiate repetitive operations at

specified intervals of time.
Tn nnr'Fnrm flatten annl o:m:|
l

PVI

IUIIII

I-IIVW

ullu

ul'llll

r operations, the

major logic components listed must interact. The fundamental com—

ponent is the 12-bit storage register, called the Clock Enable Register. This register can be loaded, bit by bit,
under program control. Different bits are used to control different functional sections of the DK8—EP.

ample:

For ex-

bit 7 of the register enables internally-generated clock pulses to be applied to the Clock Counter Register;

bit 9, by enabling one of the Schmitt trigger circuits, allows an external source to control some aspects of clock

operation. The Clock Enable Register can be set or cleared under program control and its contents can be transferred to the CPU AC Register at any time by a program instruction.
The Clock Counter Register counts clock pulses in a way that is predetermined by the state of Clock Enable

signal (OVERFLOW L) each time it overflows to 0.

In other circumstances, the programmer might wish the

OVERF LOW L signal to be generated each 2000 clock pulses. The Clock Counter Register can be preset, to a
count of 2096 in this example, in order to produce the desired result. The contents of the Clock Counter Register
can be transferred to the AC

the logic makes use of a 12-bit Clock Buffer Register.

The Clock Buffer Register is essential to the DK8-EP operation. Data is transferred between the AC Register and
the Clock Counter Register via the Clock Buffer Register. To preset the Clock Counter Register, as in the example

given, the program causes the Clock Buffer Register to be loaded from the AC Register with the preset count. Bits
1 and 2 of the Clock Enable Register can then be set so that the preset count, 2096, is loaded into the Clock

Counter Register each time the OVERFLOW L signal is generated. Thus, the Clock Counter Register counts re-

petitively from 2096 to 4096. The Clock Buffer Register can be controlled by the program, and to a certain
extent, by an external source. For example, Clock Enable Register bits 9—11 allow an external source to cause
the Clock Buffer Register to be loaded; however, transfers between the AC and Clock Buffer Registers are limited
to program control.

465

4.6.1

Block Diagram Discussion

The functional block diagram shown in Figure 4—51 illustrates the relationship between the registers and the
remainder of the clock logic.

applicable logic

can be found

Each functional block is discussed in detail in the following paragraphs and the
in the indicated figures.

The lOT Decoder logic provides signals in response to the eight lOT instructions listed in Table 4—9. These IOT

signals are distributed to the various functional sections as shown in Figure 4—52. The enabling signals from the
Clock Enable Register are shown on the block diagram and are listed and explained in detail in Table 4-10.
For operations not involving external sources, the signal flow description can begin with the Clock Rate Select

logic. The desired frequency of clock pulses is selected by the Rate Enable bits, while the Count Enable bit gates
the clock pulses to the Load Buffer Register logic. This logic converts the clock pulses to B COUNT pulses that
are counted

by the Clock Counter Register. The logic also generates the LOAD BUFFER signal in response to

program instructions and ensures that the B COUNT and LOAD BUFFER signals do not occur at the same
moment (the significance of this is detailed in Paragraph 4.6.2.4).

The LOAD BUFFER signal causes the Clock Buffer Register to be loaded with data from either the AC Register,
via the DATA 0—11

lines, or from the Clock Counter Register. The B COUNT pulses are counted by the Clock

Counter Register in a way that is determined by signals from the Buffer/Counter Control Signal logic. These

signals are asserted by combinations of lOT signals and Mode Enable bits 1 and 2.
The OVERFLOW L signal that is generated by the Clock Counter Register is applied to the OVERFLOW flip~flop

logic. This logic asserts two signals that can be used by devices (e.g., analog-to-digital converters) to initiate some
operation. OVERFLOW (0) L is suitable for external devices, while EXT PULSE L is designed to be used by
OMNlBUS devices (A/D START). The status of the OVER FLOW flip-flop can be checked under program control
and transferred to bit 0 of the AC Register via the DATA 0 line.
The logic also provides the OVERFLOW (1) signal that is applied to the lnterrupt/Skip logic. Thus, each time the
Clock Counter Register overflows:

internal and external devices can begin some operation; the DK8-EP can re-

quest a program lnterrupt; a program instruction can be skipped; or any combination of these events can occur,

depending on the state of Clock Enable bits 0, 6, and 8.
Except for transfers between the Clock Buffer Register and the AC Register, the clock operates in much the same
manner when an

operation is initiated by external sources. Signals applied to the external input channels can ac-

tivate one or more of the Schmitt triggers. The resulting signal, SCHMITT IN 1 L (or 2, or 3) is applied to the

Input/Overflow Status logic.

Here the status of each input channel can be checked under program control and

forwarded to the AC Register. (Event Enable bit 9 enables the status of Schmitt trigger input 1 to be transferred
to AC9 via DATA 9.)

The Input/Overflow Status logic allows the external event to generate the appropriate lNT ROST (1, 2, or 3) L

signal. This signal is applied to the Interrupt/Skip logic and can cause a program Interrupt. The INPUT 1+2+3 L
signal is also asserted by the Input/Overflow Status logic and causes the Clock Rate Select logic to produce clock
pulses. The Load Buffer Register logic and the Buffer/Counter logic then operate as already outlined.

4-66

OMNIBUS

SIGNALS

DATA 0-11

‘

CLOCK

DATIA

OVERFLOWIOIL
‘L___________,

ENABLE 0.6.8
——>

TP3
—‘—‘——.

CLOCK
ENABLE
REGISTER
LOGIC

ENABLE SIGNALS

MODE
ENABLE 1.2

.————.—.

-—————-—y

BUFFER/
COUNTER
LOGIC

OVERFLOW L

OVERFLOW
F/F LOGIC

LOGIC

DATA

CLEN,CLOE,CLZE

CpL,mL

BU FFER/
COUNTER
CONTROL
SIGNAL

E XT START L

OVERFLOW (1)

CLSA
CLSK

0,9,10,11

INTERNALI/OL
IOT
INSTRUCHONS
—-——>

LQ‘V

I/O PAUSE

3- n L

CLOCK
ENABLE o

COUNT
ENABLE 7

RATE
ENABLE 3.4.5

STATUS
LOG'C

EVENT

-——-——--9

$3sz

DECODER
LOGIC
SELECT

ENABLESJOJI

MODE
ENABLE 1,2

——————>

"‘—"—"

CLOCK
RATE
SELECT
LOGIC

SELECTED
FREQUENCY

LOAD
BUFFER
REGISTER
LOGIC

INPUT 1+2+3 L

SCHMITT IN 1,2,3,L

CLAB
CLBA

CLOE
C LZE

CLCA

SCHMITT
TRmGERs

L2.3

INT RQSTL

I
SKIP L

CLOCK
ENABLE

INT/SKIP
LOG'C

0,8

CH 1,2, 3

INT RQST L2,3L

CLSK

____|

6E-0304

Figure 4-51

DK8-EP Functional Block Diagram

Table 4-9
DK8-EP IOT Instructions
Octal Code

Mnemonic

Function

6130

CLZE

Clear Clock Enable Register per AC Register. Each bit in the

Clock Enable Register is cleared if the corresponding bit in
the AC Register is set. The AC Register is unchanged.

6131

CLSK

Skip on a CLOCK flag. The next program instruction is skip
ped if either of the following skip conditions exists:
a.

An enabled Schmitt trigger has fired

b. The Clock Counter Register has overflowed

6132

CLOE

Set Clock Enable Register per AC Register.

Each bit in the

Clock Enable Register is set if the corresponding bit in the AC

CLAB

AC Register to Clock Counter Register. The contents of the
AC Register are transferred to the clock and loaded into both

the Clock Buffer and the Clock Counter Registers. The AC

CLEN

Clock Enable Register to AC Register. The contents of the
Clock Enable Register are transferred to the computer and
JAMed into the AC Register. The Clock Enable Register is

unchanged.
6135

C LSA

Status to AC Register. The state of the OVERF LOW flip-flop
and of the three Schmitt input circuits is transferred to the

computer and JAMed into the AC Register.
ing AC bits are affected:

6136

CLBA

Only the follow-

AC Bit

Status Condition

Enabled OVERFLOW flip-flop

Enabled Schmitt input 3

Enabled Schmitt input 2

Enabled Schmitt input 1

Clock Buffer Register to AC Register. The contents of the
Clock Buffer Register are transferred to the computer and

JAMed into the AC Register. The Clock Buffer Register is

unchanged.
6137

CLCA

Clock Counter Register to AC Register. The contents of the
Clock Counter Register are transferred, via the Clock Buffer

4—68

MD09 L

CLZE (6130) L

(6131)

CLOE (6132)

CLSK

MD1O L

MD“

E44

BCD- T0DECI MAL
DECODER

CLAB (6133) L

DEC
8251

CLEN (6134)

(6135)

CLBA (6136)

CLSA

CLCA (6137)

M003 L
CO L

6917

MD04 L
C1 L

M005 L
MD06

M007

MDOB

SELECT

8 SELECT

I/O PAUSE L

INTERNAL I/O

NOTE:

Logic

is par? of M860 module.
8E-O303

Figure 4-52

IOT Decoder Logic

Table 4-10
Clock Enable Register Enable Signals

Enable Signal Name

F unction

CLOCK ENABLE 0

Enables a status check of the OVERF LOW flip-flop (CLSA), an
instruction Skip on an overflow condition (CLSK), and a possible Interrupt request on an overflow condition.

MODE ENABLE 1

Determine the Clock Counter Register mode of counting. The

MODE ENABLE 2

four possible modes are:

Register counts at the selected rate. An external event can
sample the register at any time, causing the sample count
to be transferred to the Clock Buffer Register. The Clock
Counter Register continues counting.

Register counts at the selected rate. An external event can
sample the register at any time. The sample count is trans
ferred to the Clock Buffer Register and the Clock Counter
Register is cleared before it resumes counting.

RATE ENABLE 3

Select the frequency of the internally-generated clock pulses

RATE ENABLE 4

(see Table 4—9 and Paragraph 4.6.2.3).

RATE ENABLE 5

CLOCK ENABLE 6

Enables each Clock Counter Register overflow to generate the
EXT PULSE L pulse that can be used by other OMNIBUSconnected devices (A/D START).

COUNT ENABLE 7

Inhibits clock pulses from being applied to the Clock Counter

Connects the Clock Interrupt logic to the computer interrupt

system, enabling the Clock Interrupt conditions to assert the
OMNIBUS INT RQST L signal.

9—11

EVENT ENABLE 9

Enable Schmitt trigger firings to turn on the clock, to cause a

EVENT ENABLE 10

program interrupt, and to sample the Clock Counter Register

EVENT ENABLE 11

(as set by bits 1, 2, 7, and 8).
Table 4-11

Frequencies Selected by Rate Enable Bits 3—5
Selected Multiplexer Output

Contents of Bits 3—5

000

No output

001

External frequency

010

100 Hz

011

1 kHz

100

10 kHz

101

100 kHz

110

1 MHz

111

No output

4-70

4.6.2

Detailed Logic

4.6.2.1

IOT Decoder Logic

—

The IOT Decoder logic is shown in Figure 4-52. The SELECT signal is asserted by

NAND gate E23 when a 613x instruction is decoded. The SELECT signal, in turn, asserts the B SELECT L signal;

the INTERNAL l/O L signal, which causes the positive l/O Bus interface to ignore the IOT instruction; and the

SELECT L signal, which is used to gate MD bits 9—11 to the BCD-to—Decimal Decoder. The DEC 8251 IC decoder provides instructions 6130 through 6137, as illustrated in Figure 4—52.
Note that instructions 6134 through 6137 cause the OMNIBUS CO L and C1 L signals to be asserted. Each of

these instructions call for a transfer of data to the CPU AC Register. With CO L and C1 L both asserted, the data

is JAM-transferred into the AC Register, instead of being ORed with data already in the register.

4.6.2.2

Clock Enable Register Logic

—

The Clock Enable Register logic is shown in Figure 4-53. The register

consists of 12 DEC 7474 flip-flops, only 2 of which are shown in the logic. Each flip-flop is given a descriptive
title that characterizes the function of the flip-flop.

For example: the MODE ENAB LE 1 flip-flop is used to se-

lect, along with MODE ENABLE 2, the particular mode of operation of the Clock Counter Register; the COUNT
ENAB LE 7 flip-flop inhibits the Frequency Multiplexer from producing clock pulses at the selected frequency; the
EVENT ENABLE 9 flip-flop enables an external event to control clock operations. (See Table 4-10 for a com-

plete listing of the enable signals and their functions.)
Three program instructions deal exclusively with the Clock Enable Register. The CLEN (6134) instruction gates
the register contents onto the DATA 0—11 lines. The information on the DATA lines is gated through the CPU

Major Register and loaded into the AC Register. The CLZE (6130) and CLOE (6132) instructions clear and set,
respectively, those Clock Enable Register flip-flops that correspond to set AC Register bits. For example, if bit 0
of the AC Register is logic 1, the CLOCK ENABLE 0 flip-flop can be set by the CLOE instruction or cleared by
the CLZE instruction.

The Clock Enable Register can be cleared by the CLEAR signal. This signal is generated by the lNlTlALlZE signal that is produced when power is turned on, when the CLEAR key is depressed, or when the CAF instruction

is issued.

4.6.2.3

Clock Rate Select Logic

frequency is provided by

—

The Clock Rate Select logic is shown in Figure 4-54. The basic 20-MHz clock

crystal-controlled oscillator (see logic drawing E-CS—M518). This frequency is divided

by the J—K flip-flop, E33. (When both the J and K inputs are high, the 1 output is changed with each positive
transition at the C input.) The 10-MHz clock frequency is applied to a chain of DEC 7490 decade counters, each
counter being wired to divide by ten. The output of each counter, which can be monitored at a test point, is ap-

plied to the E10 Frequency Multiplexer, a DEC 74151 IC.

An external pulse source of any frequency can also be

applied to the multiplexer, via pin R R on J1 of the M518 module. The desired frequency of clock pulses is obtained by selectively setting or clearing RATE ENABLE flip-flops 3, 4, and 5 with the CLOE or CLZE lOT instructions. Table 4-11 shows the relationship between the 1 outputs of these flip-flops and the multiplexer-output

frequency.
Note that COUNT ENABLE 7 must be cleared if output pulses are to be obtained from the multiplexer. This

particular Clock Enable Register flip—flop is illustrated because it differs from the remaining register flip-flops in
an

important way. Bit 7 can be cleared by an external event as well as by program instructions. Any of the three

Schmitt-trigger input circuits can cause the INPUT 1+2+3 L signal to be asserted, thereby clearing the COUNT
ENABLE 7 flip-flop and turning on the clock.

4-7 1

DATA 1 L

DATA 0 L

_____________

:M518 MODULE

P/O

M860 MODULE

CLEN (6134) L

I
l

E48

I
4

E52

CLEAR

INITIALIZE
E36

“1‘9

CLOCK
ENABLE

l 011)

---(TO BIT 2-11)

CLOCK
ENABLE o
0

0"?

M00
ENABLE

‘

MODE
ENABLE
1 (1)

—l-

—-—(T0 BIT 2—11)

I
E50

CLZE (6130) L

ZL'V

E29
E42

CLOE (6132) L

---(T0 BIT 2-11

I
TP3

|
SELECT

E50

I
I

E31

-——1To B1T 2-11)

-(TO BIT68 8)

‘
'"

(T0 BIT 2-5.
7, 9—11)

NOTE:
Unless indicmed

otherwise, logic is P/O M518 module‘
8E-O302

Figure 4-53 Clock Enable Register Logic

1MHz
100

KHz

10 KHz

1KHz

E10

FREQ
MUX

15
1

CLOCK PULSES AT
SELECTED FREQUENCY

100 Hz

8| 9|

E5
+10
7490

(F'10 MHl)

E11
+10
7490

E6
+10
7490
1

+5V

CL°CK OUT

E4
+10
7490

E15
+10
7490
1

DEC
74151
9

+5V

EXT PULSE m

(J1

’

RR)

RATE ENABLE 3(1)
RATE ENABLE 4(1)

RATE ENABLESU)

8L1?

753730
c

COUNT1

ENABLE 7
c 7474 D

INPUT 1+2+3 L

CLEAR
H

CRYSTAL
CONTROLLED

TRANSISTOR
OSCILLATOR

(Cng-Tp3)

(CLOE-TP3)

F'ZOMHZ

SELECT

NOTE:
1. Logic is P/O M518 Module
2. See appendix A for details of 7470 and

DATA 7 L

74901C's
8E-0301

Figure 4-54

Clock Rate Select Logic

Load Buffer Register Logic

4.6.2.4

—

The Load Buffer Register logic is shown in Figure 4—55. The logic gener-

LOAD BUFFER signal that loads the Clock Buffer Register and the B COUNT L pulses that are counted
by the Clock Counter Register. The LOAD BUFFER signal can be asserted in response to either the 6133 IOT

ates the

instruction, or the 6137 lOT instruction. The signal can also be asserted in response to an external event.

e
COUNT

+5V

Jase...
'

l—MODEi (1)

COUNT

0
E38
9601

‘1:

r-——————C
E46
INPUT 1+2+3 L—-——C
+5v
=

i>—INHB OUT

lr—COUNT

.__..

P/O M518
MODULE

mHB

IN —‘ '

l
ElO—PS
(SELECTED
FREQ.)

E16

fi—

INPUT

1+2+3

BUFFER TO

CLCA (6137) L
CLBA (6136) L
E16

I»——¢——CLAB

I
E4, PS

E4,P8

I—

:l >

(6133)L

E29
TP3
o

NOTEI

Unless indicated otherwise.

logic is P/O M860 module.
eE-oaoo

Figure 4-55

Load Buffer Register Logic

If the 6133 instruction is decoded, NAND gate E29 is enabled at TP3 time and, in turn, enables NOR gate E28
to assert the

LOAD BUFFER signal. If an external event generates the INPUT 1+2+3 L signal, E28 again asserts

the LOAD BUFFER signal. However, the enabling path is more complex than that of the 6133 instruction, for
two reasons.

First, the external event is allowed to generate the LOAD BUFFER signal only when Mode 10 or

Mode 11 has been selected by Mode Enable bits 1 and 2 (NAND gate E15 can be enabled in either case).
an

Second,

external event must not be allowed to assert the LOAD BUFFER signal when an lOT instruction is being car-

ried out (NAND gate E46 is inhibited by thelNHB lN signal during an IOT instruction). To illustrate the need
for this prohibition, consider the 6136 and 6137 instructions. If the 6136 instruction is issued, the BUF TO AC

signal is asserted. This signal gates the Clock Buffer Register output to the DATA lines. If the lNHB lN signal
were not

asserted, an external event could generate the LOAD BUFFER signal during the IOT. Thus, the result

would be identical to that achieved by a 6137 instruction.
The majority of the logic is designed to make the 6137 instruction operative. While the 6133 instruction loads
the Clock Buffer Register with data from the CPU AC Register, the 6137 instruction loads the Clock Buffer with

4-74

the contents of the Clock Counter Register. Precautions have been taken to ensure that, if the 6137 instruction
is issued, the LOAD BUFFER signal is not asserted at the moment the Clock Counter is changing its count. This

prevents false counts that would result from reading the Clock Counter as one or more bits are in transition.
The precautionary logic includes flip-flop E21A and latch E24 shown in Figure 4—55. These two components and
related gates generate signals that are illustrated in the timing diagram of Figure 456. Also shown in the timing
diagram are signals generated by flip-flop E218 and one-shot E38. Both figures are referred to during the follow-

ing discussion.

Flip-flops E21A and E213 are clocked by signals derived from the first decode counter in the Clock Rate Select
logic (see Figure 4-54). The D input of E2lB is controlled by the selected frequency output of the Frequency

Multiplexer.

In the timing diagram, this frequency is chosen as 1 MHz. When E21B is set, its 1 output triggers

one-shot E38; E38 produces the B COUNT L signal for approximately 300 ns. The Clock Counter Register then
counts the B COUNT L pulses which occur at the selected frequency.

When the 6137 instruction is issUed, the CLCA L signal produced by the lOT Decoder logic asserts the GO READ

signal. Because the clock is free-running, the GO READ signal can occur at any time with respect to the signal at
the C input of E21A.

If it occurs at the instant shown in the timing diagram, just before the pulse marked (A),

E21A is set 200 ns before the B COUNT L signal is asserted. Because each bit of the Clock Counter Register consists of a master/slave flip-flop, the register bits are in transition on the leading edge of the B COUNT L pulse.

Thus, the LOAD BUFFER signal causes the Clock Counter to be loaded into the Clock Buffer approximately
100 ns before the Clock Counter can change in response to the next B COUNT L pulse. (A delay of approximately

100 ns is introduced by the gating between E21A and NOR gate E28.) If the GO READ signal is asserted just
after the leading edge of pulse (A), E21A is set by pulse (B), 300 ns after the B COUNT L signal is asserted.

Thus, the Clock Buffer is loaded approximately 200 ns after the Clock Counter changes in response to the B
COUNT pulse; enough time for the data to settle in the Clock Counter.
The amount of time between pulse (A) and pulse (B) is always 500 ns; therefore, the GO READ signal must be
asserted for a longer amount of time to ensure that either (A) or (B) can set flip-flop E21A. This requirement is
not met by normal CPU timing.

In addition, under normal CPU timing it would be possible to lose the data that

is being transferred from the Clock Counter Register. This could happen if the CLCA L signal were asserted just

after the (A) pulse, for example. Under normal CPU timing for an internal lOT instruction (6137 is such an in-

struction), the AC LOAD L signal is asserted at TP3 time.

In the present example, TP3 could occur before the

count has been placed on the CPU Major Register Bus; thus, the count would be lost.

Both these difficulties may

be overcome by increasing the period of time during which the CLCA L signal is asserted. The logic shown in

Figure 4-57 is designed to increase the available time to approximately 650 ns.
When the BUF TO AC signal is asserted, one-shot E47 is triggered and remains set for approximately 650 ns. The

OMNlBUS NOT LAST TRANSFER L signal is asserted for the same amount of time. Because NOT LAST
TRANSFER L is low when TP3 of the lOT instruction (6137 in the present example) occurs, the CPU timing is

interrupted and stalled in T83. Until normal timing is resumed, the OMNlBUS l/O PAUSE L signal remains low,

keeping CLCA L low and, thus, GO READ high. When one-shot E47 times out, NOT LAST TRANSFER L is
negated. Perhaps 40-ns later, time enough for the NOT LAST TRANSFER line to settle, latch E24 causes the
OMNlBUS BUS STROBE L signal to be asserted. This signal causes normal CPU timing to begin from the point
of interruption. l/O PAUSE L is negated, in turn negating the CLCA L signal and, finally, the GO READ signal.

The Clock Buffer/Clock Counter logic is shown in Figure 4—58. The
logic for bits 1—10 is identical to that for bit 11. The Clock Buffer Register is a storage register composed of

4.6.2.5

Clock Buffer/Clock Counter Logic

—

DEC7474 IC flip-flops. The Clock Counter Register is a presettable binary counter composed of DEC 74197 ICs

(see Appendix A for a detailed description). Each bit can be preset at the S input and cleared at the R input.

475

~uI

I‘—

t=100ns

CLOCK OUT
f=10 MHz

*E4,P9
f=4MHz

*E4P8
f=2 MHz

*E‘IO.P5
f=1MHz

I
I

*E218,P11
**B COUNT

E21A,P3

91:17

CLCA L

**60

READ

**COUNT BUSY(U

F—

(A)

(B)
i

I
I

WWW

—_

dc-SET INPUT

**PA(n
**L0AD BUFFER

Origin

‘*

Origin

ihe M518 moduie.

is on the M860 module.
aE—oaos

Figure 4-56

Load Buffer Register Timing

BUS STROBE

£33
BUF

TO AC

CLAB(6133)L

524
7475

+5V

+5v

+5v
L
i

jv r
IIH

E47
9601

a? <

‘

READ

533

NOT

LAST TRANSFER

+3V
NOTES

Logic

P/O

M860 module.
8E-0299

Figure 4-57

NOT LAST TRANSFER Logic

The B COUNT pulses are applied to the bit 11 toggle (T) input; the negative transition of each B COUNT L pulse
causes the

1 output to change. The 1 output of each bit is connected to the T input of the following bit‘and the

Buffer Multiplexer, a DEC 8266 IC.
The logic enables the exchange of data between the Clock Buffer Register and the Clock Counter Register, and
between these two registers and the CPU AC Register. Data transfers between the Clock Buffer and the Clock

Counter can be controlled by external events; however, transfers between these two registers and the AC can be

accomplished only under program control. The first type of transfer, between Clock Buffer and Clock Counter,
can be considered an

internal transfer (internal to the clock), while the second can be considered as external.

Three different transfers can be grouped under each type, as shown in column 1 of Table 4-12. Column 2 of this
table shows both the source register and the destination register of each transfer. Column 3 shows the control

signals that must be asserted for each transfer. For example, if the DK8—EP is operating in mode 10, an external
event can cause a transfer from the Clock Counter to the Clock Buffer by asserting the CTR ENABLE and the

LOAD BUFFER signals. The output of the Clock Counter Register is applied to the Buffer Multiplexer. Because
CTR ENABLE is asserted (this signal is asserted for all transfers except CLAB), the Clock Counter data is gated
through the multiplexer to the Clock Buffer, which is then loaded by the LOAD BUF FER signal. Note that
Mode 11 transfers are similar, but that the CLR CTR L signal clears the Clock Counter after data is transferred to
the Clock Buffer.

The data placed in the Clock Buffer by any of these internal transfers can be passed to the AC only by an external-

type transfer. The CLBA instruction asserts the BUF TO AC signal that gates the Clock Buffer output onto the
OMNIBUS DATA lines. The information on the DATA lines is then gated to the AC Register and loaded at BUS
STROBE L time.
Data can be transferred from the AC to the Clock Counter by the CLAB instruction.

In this case, information in

the AC Register is placed on the DATA lines and gated to the Buffer Multiplexer (B SELECT L is asserted by the
IOT Decoder logic). The AC ENABLE signal is asserted, gating the data to the Clock Buffer. The LOAD BUFFER

signal loads the register and the BUF TO CLR L signal gates the Clock Buffer output to the S input of the Clock
Counter.

4-77

DATA 11 L

DATA 0 L

E 6

BUF TO Ac

_____

—————

TI
I

CLEAR L

LOAD

1
0
BUFFER"
7474
c
D

_____

BUFFER

_____

BUFFER
MULTIPLEXER 0
P/O 8266 IC

BUFFER
MULTIPLEXER 11

Ac ENABLE

Flo 8266

SELECT L

_____

0—

—————

——————

IF—OVERFLOW L
—

IP/O
74197 IC

1
CLOCK
COUNTER 11
T
s

I
B

COUNT

CLR CTR L

CTR ENABLE

“l

_______

1
BUFFER O
7474
D

——

—

I
l

I
j) I

—

[370
74197 IC

—

CLOCK‘

COUNTER
r

I
|

r
_____

—————

BUF TO CTR L

I
I

_______

—————

SE-OZSB

NOTE:

Logic is P/O M860 Module

Figure 4-58

Clock Buffer/Clock Counter Logic

Table 412
Control Signals for Clock External and Internal Transfers
Transfer Type

From/To

Control Signal Asserted

Internal
Mode 01

Clock Buffer/Clock Counter

BUF TO CTR L, CTR ENABLE

Mode 10

Clock Counter/Clock Buffer

CTR ENABLE, LOAD BUFFER

Mode 11

Clock Counter/Clock Buffer

CTR ENABLE, LOAD BUFFER, CLR CTR L

CLAB

AC Register/Clock Counter

AC ENABLE, LOAD BUFFER, BUF TO CTR L

CLBA

Clock Buffer/ACRegister

BUF TO AC, CTR ENABLE

CLCA

Clock Counter/AC Register

CTR ENABLE, LOAD BUFFER, BUF TO AC

External

The control signals are asserted by the logic illustrated in Figure 4-59. BUF TO AC and AC ENABLE are used

only during external transfers and, thus, are asserted only by program instructions. (Note that the AC ENABLE
and CTR ENABLE signals are mutually exclusive.)

However, because the Clock Buffer is loaded during both

4-78

external and internal transfers, external events, as well as program instructions, can generate the LOAD BUFFER

signal. The BUF TO CTR L signal is also used for both internal and external transfers (the Mode 01 transfer can
be accomplished only when the M33 of the Clock Counter Register asserts the OVER FLOW L signal).
CLCA (6137) L
BUF

E52

TO AC

CLBA (6136) L

f'”‘"‘"l

CLCA(6137)L
1+2+3

INPUT

(MODE 10,11)

1'
l____J
(—

—

LOAD BUFFER

‘I

CLAB (6133) L

I...
CLAB (6133) L

—

._..J

‘

AC ENABLE

CTR ENABLE

INITIALIZE
CLEAR L

CL R C TR L
INPUT 1+2+3 L
INHB

(1)
(1)
MODE ENA 2(1)

COUNT

BUSY

MODE

ENA

1
551
OVERFLOW
7474
c
D

OVERFLOW

(0)

MODE

ENA

MODE

ENA 2 (1)
BUF T0 CTR L

CLAB (6133)

NOTE:

Logic

is P/O M860 module.
8E-0297

Figure 4-59

Clock Buffer/Clock Counter Control Signals

The CLR CTR L signal is asserted only when a Mode 11 transfer is initiated by an external event. Bi-stable latch

E24A (one-shot) asserts the CLR CTR L signal. Note that the 1 output of the latch is applied to the E51
OVERFLOW flip-flop via NOR gate E46. The MSB of the Clock Counter might go from a high toa low when
CLR CTR L is asserted. Such a transition asserts the OVERFLOW L signal, thereby enabling NOR gate E37. The
1 output of latch E248 goes high (one-shot). The OVERFLOW flip-flop would be set unintentionally if E46 was

4-79

not enabled. The same problem could arise when the CLAB instruction is issued; thus, NOR gate E10 is also

applied to E46.

Although the CLR CTR L signal can be asserted only by an external event, the Clock Counter can be cleared under program control. The Clock Buffer must first be cleared. This can be done either by issuing a CAF (Clear All

Flags) instruction, or by depressing the CLEAR key on the programmer's console. The INITIALIZE signal is asserted by either method (and by power turn-on). The CLEAR L signal then clears the Clock Buffer Register and
the contents of the Clock Buffer can be transferred to the Clock Counter.

4.6.2.6

OVER FLOW Flip-Flop Logic

—

The OVERFLOW flip-flop logic is shown in Figure 4-60. The logic mon-

itors the M88 of the Clock Counter Register via the OVERFLOW L signal. When the register asserts the

OVERF LOW L signal, the OVERFLOW flip-flop, E51, is normally set. (NOR gate E46 prevents the flip-flop from

being set unintentionally; see Paragraph 4.6.2.5.) The set state of the flip-flop enables the logic to assert various
signals selectively. The selectivity depends on the state of certain Clock Enable Register flip-flops and on the particular program instruction, if any, that is issued.
The OVERFLOW (0) L signal and the EXT PULSE L signal have similar purposes; i.e., to initiate some operation,
such as analog-to-digital conversion, when overflow of the Clock Counter Register occurs. When OVERF LOW L

is asserted, latch E24 enables NAND gate E5, provided that the CLOCK ENABLE 6 flip-flop was set by a previous
CLOE instruction, and sets the E51 OVERFLOW flip-flop. The 1 output of E51 enables NAND gate E19, thereby

asserting the EXT PULSE L signal. E24 remains latched for approximately 100 ns. (The duration of the latch is
determined by the RC time constant of the D input; see Appendix A for details.) Thus, the EXT PULSE L signal
is a pulse that can be generated each time an overflow occurs.
The EXT PULSE L pulse is designed to be used with an A/D converter that plugs into the OMNIBUS.
can

be taken from the M860 module, conveniently, only via an H851

Edge Connector.)

(The signal

In such an application,

the EXT PULSE L pulse sets the rate at which an analog signal is sampled by the A/D converter.

The 0 output of E51 is buffered before it asserts the OVE R FLOW (0) L signal. This signal, once asserted, remains
so until

E51 is cleared under program control. The OVERFLOW (0) L signal is made available at a 40—pin con-

nector on the M518 module.

Thus, it can be used by both external and internal devices in a variety of applications.

No matter what the application, the OVE RF LOW (O) L signal is useful, generally, only when it can be continu-

ously asserted. Therefore, flip-flop E51 must be repeatedly cleared. The flip-flop can be cleared, not only by the
INITIALIZE signal (generated at power turn-on, by the CLEAR key, or by the CAF instruction), but also by the

6135 instruction, STATUS TO AC. The 6135 instruction can clear E51 only if the CLOCK ENABLE 0 flip-flop
has been previously set by a CLOE instruction. When E51 is set, NAND gate E50 is enabled and it, in turn, enables NOR gate E49. When CLSA is issued, the STATUS TO AC signal enables NAND gate E48, asserting the
DATA 0 L signal. At TP3 time, E51 is cleared and can be set by the next Clock Counter Register overflow.
The status of E51 can be checked either by the CLSK instruction alone, or via the Interrupt system and the CLSK

instruction. The Interrupt system can be used only if the CLOCK ENABLE 8 flip-flop has been set.

E51 can

then assert the INT ROST L signal. The CLSK instruction in the Interrupt-servicing routine will cause a Skip to
the DK8—EP subroutine, where CLSA causes the status of E51 to be transferred via the DATA 0 line to ACO.

4.6.2.7

Interrupt/Skip Logic

—

The Interrupt/Skip logic is shown in Figure 4-61. As indicated in previous dis-

cussions, program Interrupts can be caused by external events and by overflow from the Clock Counter Register.
The DK8—EP can be logically connected to the computer Interrupt system if the CLOCK ENABLE 8 flip—flop is
set by a CLOE

instruction. When this flip-flop alone is set, an external event can cause a program Interrupt. The

event causes the INT

REG 1, 2, or 3 L signal to be generated by the Input/Overflow Status logic. This signal first

enables NOR gate E15, and finally causes NAND gate E34 to assert the OMNIBUS INT ROST L signal.

4-80

[

CLSK (6131) L

E34

SKIP L

E34

INT
ROST

E48

DATA 0 L

CLK ENA 8(1)

—

lP/O

M518

*5V

OVERFLOW (0) L

mum

l
SELECT L

CL5M6135)

‘-

STATUS
AC

L—(1>T°
TP3

‘l

OVERFLOW
c

L817

551

INITIALIZE
O

CLAB

E24(CLR CTRNH

5‘9

‘

CLK ENA 6(1)

E24
7475

1
D

L-

OVERFLOW L

NOTE:
Unlus Indicated

otherwiso.Logic is No M860 Module

;

-15V

+5V

at if
BE-OZOG

Figure 4-60 OVERFLOW Flip-Flop Logic

EXT
PULSE L

ENABLE O (1)

CLOCK

OVERFLOW (1 )

CLOCK

INT

REQI

INT

REG 2 L

INT

REG 3 L

E34

INT RQST

E34

SKIP

E15

ENABLE 8(1)

CLSK

NOTE:

Logic

P/O

M860 module.
8E—0295

Figure 4—61

Interrupt/Skip Logic

If the OVE R FLOW (1) signal from the OVE RFLOW flip-flop logic is to generate an Interrupt request, the CLOCK

ENABLE 0 flip-flop must also be set. This signal can then cause the INT ROST L signal to be asserted by NAND

gate E34.
When the computer enters the Interrupt-servicing routine in response to the DK8-EP Interrupt request, the CLSK

instruction causes NAND gate E34 to assert the OMNIBUS SKIP L signal.

Thus, the computer can be directed to

the particular subroutine that services the request. The CLSK instruction may still be used when the clock is not
connected to the computer Interrupt system. The program can enter a waiting loop which checks the status of
the two conditions (overflow and external event). When either condition is met, the appropriate subroutine is

entered.

4.6.2.8

Input/Overflow Status Logic

—-

The Input/Overflow Status logic, shown in Figure 4—62, enables the pro-

grammer to check the status of the OVERFLOW flip-flop and the Schmitt trigger input channels.

Input channel

3 is illustrated fully in Figure 4-62; the logic functions are as follows. An external event can cause the SCHMITT
IN 3 L signal to be asserted.

If the EVENT ENABLE 09 flip-flop has been set by a previous CLOE IOT instruc-

tion, the SCHMITT IN 3 L signal sets the STATUS 3 flip-flop and asserts the INPUT 1+2+3 L signal. The latter

signal can either actuate the clock or cause the contents of the Clock Counter Register to be transferred to the
Clock Buffer Register. When the STATUS 3 flip~flop is set, it asserts the INT ROST 3 L signal. This signal can
result in a program Interrupt request, if the CLOCK ENABLE 8 flip—flop has been set by some previous CLOE

instruction.
Assume that the external event causes a program Interrupt. The OMNIBUS INT ROST L signal is asserted and
the CPU enters the Interrupt-servicing routine. The CLSK instruction in the servicing routine causes the program
to proceed to the DK8-EP subroutine.

The CLSA IOT instruction determines how often the event occurs in a

given amount of time and/or which input channel caused the program Interrupt. When this instruction is issued,
the Select logic generates the CLSA L signal that, in turn, generates the STATUS TO AC signal (see Figure 4-62).
The leading edge of the STATUS TO AC signal sets the SYNC 3 flip—flop (the D input of the flip-flop Is high be
cause the STATUS 3

flip-flop is set). NAND gate E3 and NAND gate E8 are enabled, the latter gate asserting

the DATA 09 L signal. The CLSA L signal causes the OMNIBUS CO L and C1 L signals to be asserted, resulting
in a JAM—transfer to the AC Register of the information on the DATA 09 line.

4-82

SCHMITT TN 1 L

—o>——

E14

EVENT ENABLE 11 (1) —-—————-fi
STATUS TO AC

CLEAR—H
SCHMITT IN 2 L

—cD——-

INT RQST

SI MILAR TO

L‘-—‘L

LOGIC—Il—bDATA 11 L

FOR DATA 9L
____..l

£14

EVENT ENABLE 10(1)
STATUS TO

@—

INPUT 1020 3L

AC—Drl
5 MILAR T0 LOGIC
I—bDATA 10 L

CLEAR—H
SCHMITT IN 3 L

INT ROST 2 L <—L

FOR DATA

E32

EVENT ENABLE 9 (1)

STATUS 3
SYNC
EVENT ENABLE 9(0)

7474

INT RQST 3 L

8 '17

I._.____.._.______.________________.___.
13/0 M860

__‘

MODULE

OVERFLOW11)-—4

CLOCK ENABLE

CLEAR—J

CLSA (6135)L

————————4>———

TP3

E51 1
OVER FLOW

0
E45

rSTATUS TO AC E45
E28

E31

O11)

E35

SELECT L

E29

I;___._._________.__.______.___..____._____._J
NOTE
Unless indica'ed otherwise, Logic is P/O

M518 Module

Figure 4-62

OE-OZSZ

Input/Overflow Status Logic

DATA 0 L

At approximately the same time that the DATA 09 L signal is asserted, the STATUS 3 flip-flop is cleared via

NAND gate E29 (the SYNC 3 flip-flop 0 output enables E29).

Approximately 500 ns later (a function of the

CPU Timing Generator), the CLSA L signal is negated. The SYNC 3 flip-flop is then cleared via NAND gate E25.
The two flip-flops are cleared so that only one occurrence of an event is transferred for each interrogation, and so

that an event is indicated only when the event actually does occur.
The OVER FLOW flip-flop also can cause a program Interrupt (see Figure 4—61 for the interrupt logic). The

CLSA instruction allows the programmer to differentiate between external-event-generated Interrupts and
For example, if the OVERF LOW flip-flop is set, and if the CLOCK ENABLE 0

overflow-generated Interrupts.

flip-flop has been set by a CLOE instruction, the CLSA L signal causes the DATA 0 L signal to be asserted. At

the same time, the CO L and C1 L signals are asserted and the data is JAMed into the AC Register. At TP3 time,
the OVERFLOW flip-flop is cleared via NAND gate E45; the flip-flop can now be set by a new overflow from the
Clock Counter Register.

4.6.2.9

Schmitt Trigger Logic

—

The Schmitt trigger logic for channel 1 is shown in Figure 4—63. The logic for

channels 2 and 3 is identical to that shown for channel 1. The logic consists of a Schmitt trigger circuit, the com-

ponents to the left of inverter E41, and the 2—output pulse-shaping circuits to the right of E41.
J1,FF
(REFERENCE VOLTAGE)

+5.5v

SCHMITTOIN

1 L

02/03
R16

J1,D

+5V

+5.5V

04/05
R18

J1. F

OUT 1 L
J1. DD

NOTE'.
LOGIC

P/O

M518

MODULE
85-0294

Figure 4-63 Schmitt Trigger Logic
The Schmitt trigger circuit is built around a DEC 1709C IC, E37 (see Appendix A for details). This IC is an operational amplifier used as a comparator in the Schmitt trigger.

In this application, only half of the 10 internal

circuitry is being used; the output of E37 is taken from pin 8 rather than pin 6. The output at pin 8 has the same

relationship to the input at pins 2 and 3, as does the output at pin 6; Le, pin 8 inverts the input at pin 2, but not
the input at pin 3.

For clarity, many of the components comprising the Schmitt trigger inputs have been repre-

sented by the logic inverters designated 02/03 and 04/05 (see logic drawing E-CS-M518—O-1 for the actual

circuits). The differential input to the Schmitt trigger is applied between MD and J1 F. The firing threshold voltage, which can be varied between i5V, is applied at J 1 F. The hysteresis voltage, 0.3V, is determined by the value
of resistors R20, R21, and R22.

484

Assume a threshold voltage of +4V. Until this voltage isexceeded by the differential input, the non-inverting

input of E37 (pin 3) is positive with respect to the inverting input (pin 2), and pin 8 is at approximately +15V.
Thus, transistor 06 is in the non-conducting state and the input to inverter E41 is near ground. Both the
SCHMITT IN 1 L and the OUT 1 L signals are negated. When the differential input crosses the threshold, going

positive, the inverting input goes positive with respect to the non-inverting input. The voltage at pin 8 drops to
near

ground and 06 switches on. The positive-going edge at the input of E41 triggers the latch circuit and E36

generates a pulse (duration determined by C53/R46 time constant), the SCHMITT IN 1 L signal, which is applied
The OUT 1 L signal goes low when E41 is enabled, remaining low until the

to the Input/Overflow Status logic.

Schmitt trigger is reset. The trigger remains in the fired state until the differential input falls below +3.7V (threshold voltage minus hysteresis voltage). When this occurs, 06 is turned off and remains off until the threshold is

again exceeded.
The Schmitt trigger logic is part of the M518 module, Input logic, and Schmitt triggers. The DK8—EP user must

provide cabling for the Schmitt trigger differential inputs and outputs, as well as for ground connections and
threshold voltages; without these signals, the Schmitt triggers are inoperable. The connections to the M518 module are made via J1 on the module.
The DK8—ES user is provided with a DK8-EF front panel that not only simplifies the interconnection of signal
sources and Schmitt

triggers, but also includes potentiometers that allow the user to control the threshold voltages.

The circuit schematic of this front panel is illustrated, in part, in Figure 464. The schematic is shown for channel 1 only; the circuits for channels 2 and 3 are identical.

I
+6.2v

(TO J1T)
CABLE 2
-6.2V

CH1 1+)

(TO .11 FF)

(““1"

BNC,

l- I

THRESHOLD

CABLE 3

OUT 1 L

(FROM J1 BB)

BNC4

CH1

(TO JlF)

CH11—)
(TO J10)

(T0 J1X)

CABLE 1

I
l“ I

«’97

v*°———“‘

H———J.

OVERFLOW 10) L (FROM .11 NN)

BNC5
C

EXT

CLOCK

(TO J1 RR)

8E-0293

Figure 4-64 DK8—EF Front Panel Schematic
The source signal, designated lN1, is applied at phone jack J1 on the front of the DK8—EF. The SLOPE switch
allows the user to select a positive- or negative—going slope on which to fire the Schmitt trigger.

Note that a posi-

tive slope is accompanied by a positive threshold voltage; when a negative slope is selected, the threshold voltage
is switched negative. The input signal is switched through 81 and connected by cable 1 to J1 on the M518 module. The reference voltage is taken from the wiper arm of R1 and connected by cable 3 to J1. The OUT 1 L sig-

nal from the M518 module is also connected by cable 3 to the BNCl connector on the front panel. Channels 2
and 3 are wired in similar fashion. Note that cables 1, 2, and 3 are wired directly to the BNC connectors, the

switches, and the potentiometers, with no intervening jacks or connectors. The three cables are joined in one 40
pin Berg connector that mates with J 1.

4-85

Also note that two signals, not directly associated with the Schmitt triggers, are accessible at the front panel connectors.

One of these signals is the OVERFLOW (0) L signal from the OVERFLOW flip-flop logic. The other is

the EXT CLOCK lN signal (input) which is applied to the Clock Rate Select logic.

4-86

SECTION 7
HIGH QUALITY POWER SUPPLY

4.7

INTRODUCTION

The LAB-8/E High Quality power supply provides regulated :15 Vdc power. The HO power supply has remote

sensing, supplies 1.5A, and has less than 1 mV/RMS of ac ripple on the output. Table 4-13 gives the power sup-

ply specifications and operating characteristics.
Table 4—13

High Quality Power Supply Parameters and Specifications
Parameter

Specification

Input Frequency

47 to 420 Hz

Output Voltage

15 i 15 mV

Input Voltage

105 -—125 Vac (or 240 Vac)

Output Current

1.5A maximum, each half

Ripple

1 mV/RMS

Overload Protection

Can be overloaded or shorted indefinitely without damage

Remote Sensing

Remote load sensing provided at plug

Regulation

0.05% line, 0.2% load

Operating Temperature

—20°C to +71°C (ambient)

All transistors and diodes are silicon-type semiconductors.

Table 4—14

Two holes are provided on the case for power supply out-

Side Connector for H0 Power
Input and 0mm”

put adjustment. Table 4-14 shows the power supply input and output pin connections. The HQ power supply

Color

Signal

(TOP)

Orange

+15 Vdc

provides i15 Vdc to the AD8-EA and VCS-E modules
through a 7008375 cable to a side connector on the mod-

ule.

Orange

Blue

Black

HO ground

The High Quality power supply shown in Figure 4-65

Black

HQ ground

provides :15 Vdc to the LAB-8/E System. The power

7 (Bottom)

Black

Logic ground

4.7.1

High Quality Power Supply Operation

+15V sense
—

15 Vdc

15V sense

supply is divided into parts A and B. The A side supplies
+15 Vdc and the B side supplies —15 Vdc. The operation

of both sides is identical so only the A side will be discussed.

4.7.1.1

The current-limiting circuitry shown in Figure 4—66 represents components of the
regulator circuitry shown in Figure 4-67. Both circuits are part of the HO power supply shown in Figure 4-65.

Regulator Circuitry

—

The components regulate the output voltage. Because 3+ and 3+ are B—— and S— are tied together at the end of
the analog power cable (to provide local voltage sensing), they are shown tied together for simplicity.

487

T101
3

.1101-2

J101-1

I
6

4;?

CR1

liens
_..0

R18

R3:,

iich

‘3 J101-4VB+\

3R4

Item

1rca4

CR3

tires

jc‘

1; R15

I
I
|
I
I

R,
w.

‘

I
I

c2T

«R13
'

casii

§,R12
1

R141»
1

475+
J101'5

.1101-2

JlOI-l
Ac NEUT

$OUTPUT A

l
I

OUTPUT A
VOLTAGE
ADJUST

,€J101-6_S_

\(i—fiB-J
J101-7

l__._——I 0101L_———_——_——_——_—J

I
I

I
9

CE:
p—J.

I J101LB+W

ttcns

la
1313

R3:

1rca2

,'< J101-9_ 5+

»
’

“R6
’

FFCI

‘

‘:R15

I
I
I
I

VCR“

IICR7

it;
B].

C33:

KCRS

8'13

.;R13

: R12

:ERH

,»

R141:

R17
1

OUTPUT B
VOLTAGE
ADJUST

cw
..

I'—

._..._

_.....n

0,02

>OUTPUT a

J101-1()¢'s_

3, JlOl-ll

“
a

|___._____.________.__

Reproduced with permission of Deltron Incorporated
890263

Figure 4-65 High Quality Power Supply Schematic

In operation, 0101 (on the outsude of the case)

IS the controlled

u m+

o +

series-pass element that varies the current, and thus the voltage,

applied to the external load (at output A). The voltage sense ls

proportional to output A, and IS compared to Zener reference

$125
R18

35 R4

OUTPUT

11cm,

CR4. A change in voltage sense will alter the base current to 01,

R111
w‘

and thus, vary the current through R9. A portion of this current
is applied to the base of 03, amplified, and applied to the base

of 0101 via emitter follower 04. The change in 04 base current

alters the collector current in 0101, and thus, changes the volt—
age across the load applied at output A.

This feedback action tends to decrease the output current when

U ,N

(To BASE
or 03)
BE- 0365

output A increases, and to increase the output current when the
terminal voltage begins to drop.

Capacitors C2 and C3 are filter-

ing elements, while diode CR5 prevents negative transients on

4-88

Figure 4-66 Current Limiting Circuitry

R9
R1
+

__+
_..__

CR4

R15

U IN

B+,S+

#7‘.‘.

1: R5

A _¢

R10

/ P

(TO COLLECTOR
0F 02)

‘
‘

__+
__

OUTPUT

:ER15
‘

R121.

1,’ m7

.»’ R8

CR5]:

OUTPUT A .>
VOLTAGE 1.
ADJUST

R14

333‘

0101
8E—0366

Figure 4-67

Regulator Circuitry

output terminals from damaging external circuitry during power-up. Potentiometer R 14 (accessible on the outside of the case) will alter the voltage sense. This varies the nominal power supply output voltage by about 1V.

Network R15—C1 gives the device a low-pass characteristic to avoid high-frequency oscillation. Point A is tied to
the current-limiting circuit described below.

4.7.1.2

Current-Limiting Circuitry

—

The current-limiting circuitry (see Figure 466) is included to protect the

regulator and external circuitry from damage when too much current (1.5A) is supplied to the load.

It reduces

the output voltage when the voltage-drop across R1 increases (due to increased output current).

This increased voltage will cause a current to flow from the emitter to the base of 02, and a collector current to
be applied to the base of 03 (via A). This extra current decreases the base drive of 0101 (see Figure 467) via

04. The smaller base current reduces the output current that the regulator can supply to the overload.
The 3— output of the A side of the power supply and the B+ side of the B output are tied to ground.

By tying

the points to ground, the A output will be +15 HO power, and the B output will be —15V HQ power. The out-

put of the HQ power supply is tied to side connectors on the AD8—EA or VC8-E and distributed to the other
modules by H851

Edge Connectors.

All measurements must be made when the load and sense connections are made by connecting the power supply
to the ADS-EA or VC8-E modules.

When both modules are installed in the system, the HQ power supply should

be connected to the AD8-EA module.

NOTE
The Power Mate (20885-8) or Deltron (C 13495) power sup-

plies may be supplied with the LAB-8/ E System. The schematics shown in

Figures 4-68 and 4-69 should be used for

troubleshooting.

4-89

CR5
0.75A
100v
N

CR6
0.75A
100v
‘

l 10,.F

:qx

150V

CR7
IN751

R1
12K

52$ 1:

1o,LF fl\_
150V

...

1/2w

‘

r
.

(2333055

‘:

389M

R15
1.8K
1

0|
2N3569

CR1CR4
2A

T‘

‘02
2N3394
D

100V

}

.
._

*RM
8'2K

4)“)

is;

.
-_J

2.2K
-..-.

34709.
w’

3&3

1500

48v

-4.
\‘

1: £1}
’1/2w

2N3394

C4
-—

0047!”:
100V

‘

CR8

IN751A7p

+
2N3394
’

1/2w

,R5

1/2w

0.64,.F

2N3394

$123K

:;1K

¢1eon

+j—c5 5K1’:J
R10

#45

R 2
3 3K ‘>
:
1/2w

5,171

—

4.7K

new

50’;

4.,
5
‘5 (_)

‘V‘V‘f

in
3w

NOTES:

*Jumper used only when 02 and R14 are not used
Resistors are 1/4 W, unless oiherwise indicated.
35039:

Reproduced with permission of Power Mate Corporation

Figure 4-68

Power Mate (20885-8) HQ Power Supply

4-90

R16 S.I.T.

P31

iié‘v‘SJJ.
RA'Z‘15K
105V T0 125V

J1 01-2
2

PBt-8

#01

—-

CR6:

CR7

MOI-2
NOTES:
1.Resistor wattage 0.5 watt unless
otherwise indicated.
N .All potentiometers are wirewound.
3. Resistors above 2 watts are wirewaund.
4. Resistor tolerance 1 l0% unless
otherwise indicated.
5. If remote sensin is not used connect
4to$,6to7,8to .& 10 to H.
6. 8.1 .T.- Indicates select in test.
7. Diodes ore MH69 unless otherwise
indicated.

A)»e+

R3"
10K ::

“CR2

:R4

33.11.
I8T3’47on :zCR3

3‘"

CR4
mums

02
2N
4356

‘

m
M
4356

‘

5.20

‘

1.2K

OUTPUT A
>‘15V
1.5A

’1

FILM

up
25V

5K ‘.

::§‘;K

“01'5

:ER13 4.64K 1% (2—5150

CR5“

zsoour
50v

>>-’S*

C3»:

FILM
“61%
5.1m

401-4

PB1~4

AC NEUT

Rt 1n325w57.

CR1

;
cw

93mg:
ADJUST

Pal-9

o4 2N 3053
PB‘l-Z

JIO‘l-S

>>+ 5>>+ 9JtOt-‘l

Pat -6\

PBt-t

0101
I 2N3055
L

OUTPUT

6'17

R16 3.1.7

p32

l.nm-a

932-4

r—fl» 3+

a“,

R_2“S.I.T.

Zea-s C51

R1‘1n325w57.
R3 ‘th

CR6 :
0
U
T

105V
TO
125V

CR7}:
/
‘

“CR?

ionising 11147011

‘: R5
:- S.I.T.
1: CR3

‘ERStVoFILM

'N 706

02
2”

Fez-5
'

‘

R10
1K

«'5.11K

“v"

4356’

C3+
zooour 1‘

3‘56

:5R12
1"
‘

40V

1500?
25v

.th3 4.64K

1’17. FILM

—-

NEUT

Jim-9
5+

Pea-7

«(CR4

“(ms

OUTPUT
b 15V

‘C

1.5A

OUTPUT 3

LVOLTAGE

MODEL 6575-?

5K‘ ADJUST

R1413
‘

PBZ-9

JtO‘l-IO

%%*5m

f 0102

$321
-

>*""
PBZ-Z

JiOt-tt
4

Reproduced with permission of Deltron incorporated

Figure 4-69

Deltron (C13495) HO Power Supply

8E-O392

CHAPTER 5

MAINTENANCE

This chapter contains information pertinent to preventive maintenance, corrective maintenance, and trouble-

shooting techniques for the LAB-8/E. The chapter is divided into the following sections:
Section 1

Preparation for Maintenance and Maintenance Requirements

Section 2

Corrective Maintenance

Section 3

Teletype Maintenance

Section 4

System Calibration

Section 5

Preventive Maintenance Procedures

Section 6

Corrective Maintenance

Section 7

Special Troubleshooting Procedures

5-1

SECTION 1
PREPARATION FOR MAINTENANCE AND MAINTENANCE REQUIREMENTS

5.1

EQUIPMENT

Table 5-1 lists the equipment and relevant specifications needed for maintenance of the basic LAB-8/ E System.
Also included in the list is the equivalent equipment used by DEC Field Service personnel.

Table 5-1

Maintenance Equipment

Equipment

Specifications

Equivalent

Precision Voltmeter Multimeter

10 kQ/V minimum

Triplett Model 310

Oscilloscope

dc to 50 MHz with calibrated deflec-

Tektronix Type 453

tion factors from 5 mV to 10V/div.
Maximum horizontal sweep rate of

0.1 us/div.

Delaying sweep is desirable

and dual trace is a necessity.
Probes

X10 with response characteristics

Tektronix Type P6010

matched to oscilloscope
Recessed Probe Tip (2)

Tektronix

Ground Leads (for each probe)

Tektronix

Integrated Circuit Pin Extender

AP Inc

D EC 29-10246

Double-Height Extender (2)

W984

Double—Height, Double-Width

W983

Extender Module (2)
DR8—E Diagnostic Jumper Cable

700841 8

Edge Connector Extender

BC08M-O M

Cables ( 2)

Light Bulb Extractor

DEC 12-09195

Tool Kit

DEC Type 142

Black Spray Paint

DEC 120-68

White Spray Paint

DEC 120—94

Jumper Wire

30—G uage with TERMI
POINT Connections

Silicon Grease

Dow Corning Compound

1/16 in. Allen Wrench

Hunter 42 035

Single-Height Extender Module (1)

W980

Precision Voltage Standard

EDC No. MV105G or

equivalent

5.1.1

Programs

Table 2-5 in Chapter 2 lists the maintenance programs supplied by DEC for ascertaining proper operation of the

LAB-8/E. To supplement these programs, there are five short test routines detailed in the following paragraphs.
These routines may be used as needed to perform the required maintenance. Chapter 5 of the PDP-8/E Maintenance Manual contains some programs which can be used to check the processor and Teletype.

NOTE
All diagnostics require a programmer’s console, a

working Teletype, and at least 4K memory with the
basic system.

5.1.1.1

Display Line on VR14 or User Oscilloscope
NOTE
The system must have a VB 14 to run this program.

5.1.1.2

Location

Contents

200

6007

Initialize

201

7001

Increment AC

Function

202

6053

Load X

203

6054

Load Y

204

6052

Skip on DONE

205

5204

Jump-1

206

6055

lnten sify

207

5201

Jump to beginning

Display Converted Value in AC (ADS-EA only or channel 0 of AM8—EA)
Location

Contents

Function

200

6530

Clear all flags (A/D converter)

201

6532

Start A/D conversion

202

6534

Wait for flag

203

5202

Wait for flag

204

6533

Read converted value in AC

205

7000

No operation*

206

7000

No operation*

207

7000

No operation*

210

7000

No operation*

211

7000

No operation*

212

5200

Jump to beginning

*No operations are performed to allow Operator to read value displayed in AC or monitor signals on an oscill05cope.

5-4

5.1.1.3

Display Converted Value in MO with AM8-EA

Select channel with switch register 8—1 1.

5.1.1.4

Function

Location

Contents

200

6530

Clear all A/D flags

201

7604

Transfer contents of switch register to the AC

202

6531

Transfer contents of AC to MUX Register

203

6532

Start A/ D conversion

204

6534

Wait for DONE flag

205

5204

Wait for DONE flag

206

6533

Transfer contents of A/D Buffer (converted value) to the AC

207

7421

Transfer contents of AC to M0

21 0

7000

N0 operation*

21 1

7000

No operation*

21 2

7000

No operation*

213

7000

No operation*

214

7000

No operation*

21 5

5200

Jump to beginning

Display Converted Value of A/D on VR14

Choose channel from switch register 8—1, or Auto-Increment all channels with switch register 5
Location

Contents

200

6530

Clear all A/D flags

201

7604

Transfer contents of switch register to the AC

Function

202

6531

Transfer contents of AC to MUX Register

203

7604

Transfer contents of switch register to the AC

204

6536

Transfer contents of AC to A/D Enable Register

205

6050

Clear display

206

1250

X axis left-most point

207

3253

X Coordinate Register

210

1251

Total number of points

21 1

3252

Counter

212

6532

Start A/D converter

213

7200

Clear AC

214

1253

X coordinate

215

6053

Load X Register

216

7001

Increment X

217

3253

Store new X value

220

6534

Skip on A/D DONE =1

221

5220

Jump—1

222

6533

Read A/D

223

6054

Load Y Register

224

6052

Skip on Display

(continued on next page)
*No operations are performed to allow operator to read displayed value in MO or monitor signals on an oscilloscope.

5-5

5.1.1.5

Location

Contents

225

5224

226

6055

Intensify point

227

2252

Increment count skip after 2000 points

230

5212

Start new A/D conversion

231

5200

Initialize and start again

250

1000

251

6000

252

0000

253

0000

Function

Jump Back -1

Start A/D Converter with Real-Time Clock

The resulting conversion of the AD8-EA (or channel 0 of AM8~EA) will be displayed in M0 on every clock over-

flow. Overflow will be generated as set by the switch register every 1 to 4096 ms.
NOTE
The CLOCK START signal monitored at FJ1 on the

M860 module, with the switch register set to 7777,
is a 100—ns pulse with 1 ms between each pulse. For
best results, oscilloscope should be set to 0.2 V/cm

and 0.1 us/cm.
Function

Location

Contents

200

7240

201

6130

Clear Clock Enable Register

202

7200

Clear AC

203

1250

Clock Enable word

204

6132

1 to Clock Enable Logic

205

6530

Clear all A/D flags

206

7200

Clear AC

Set AC to 7777

5.1.2

207

1251

A/D ENABLE word to Enable Register in A/D

210

6536

AC to A/D Enable Register

21 1

7604

Transfer contents of switch register to the AC

212

6133

Transfer AC to Clock preset

213

6534

Skip on A/D DONE =1

214

5213

Jump—1

215

6533

Transfer contents of A/D Buffer to AC

216

7421

Transfer contents of AC to M0

217

5211

Restart

250

1340

251

0200

Preventive Maintenance Inspections

Preventive maintenance consists of procedures that are performed prior to the initial operation of the computer,
and periodically during its operating life. These procedures include visual inspections, cleaning, mechanical checks,
and operational testing. A log should be kept for recording specific data that indicates the performance history

and rate of deterioration; such a record can be used to determine the need and time for performing corrective
maintenance of the system.

Scheduling of computer usage should always include specific time intervals that are set aside for scheduled
maintenance purposes. Careful diagnostic testing can then reveal problems which may only occur intermittently

during on-line operation.
5.1.3

Scheduled Maintenance

The LAB—8/E must receive certain routine maintenance attention to ensure maximum life and reliability.

Digital

Equipment Corporation suggests the schedule defined in Table 5.2.
Table 52

Processor Preventive Maintenance Schedule

(3 months or 500 hours)
Action

Type
Cleaning

Clean the exterior and interior of the computer cabinet, using a vacuum cleaner

and/or clean cloths moistened in nonflammable solvent.

Clean the air filters in the processor and the display unit.
uum cleaner to remove accumulated dirt and

Use a vac-

dust, or wash with clean

hot water and thoroughly dry before using.
0.

Lubricate

Clean face of display unit.
Lubricate slide mechanisms and casters with a light machine oil or

powdered graphite. Wipe off excess oil.
inspect

Visually inspect equipment for general condition. Repaint any
scratched areas.

Inspect all wiring and cables for cuts, breaks, fraying, wear, deterioration, kinks, strains, and mechanical security. Tape, solder, or replace
any defective wiring or cable covering.

Inspect the following for mechanical security: key switches, control
knobs, lamps, connectors, transformers, fans, capacitors, etc. Tighten
or replace as required.

Inspect all module mounting panels to be sure that each module is
securely seated in its connector. Remove and clean any module that
may have collected dirt or dust.

Inspect power supply components for leaky capacitors, overheated
resistors, etc. Replace any defective components.

Check the output of the H724(A) power supply (see Table 5-8). Use
a

multimeter to make these measurements without disconnecting the

load. If any output voltage is not within tolerance, the supply is considered defective and corrective maintenance should be performed.

Perform

Run all MAlNDEC programs to verify proper computer operation in
Table 2-25. Each program should be allowed to run for at least 3

min, or two passes, whichever is longer.
b.

Perform all preventive maintenance operations for each peripheral device included in the LAB-8/ E System as directed in the individual
maintenance instructions supplied with each peripheral device.

Run the LAB-8/E calibration procedures in Paragraph 5.4, if required.

Enter preventive maintenance results in log book.

5-7

5.1.3.1

Weekly Preventive Maintenance Schedule

Time should be scheduled each week to operate the

MAlNDEC programs as listed in Table 2-25 of Chapter 2. Run each program for a minimum of 3 min. Take any
corrective action necessary at this time and log the results. External system cleanliness should also be maintained
on a

weekly basis.

Computer downtime can be minimized by rigid adherence to a preventive maintenance schedule. Because a dirty
air filter can cause machine failure through overheating, all filters should be cleaned periodically. The procedure

for filter cleaning is described in Table 5-2.

SECTION 2

CORR ECTIVE MAINTENANCE

MAINTENANCE PROCEDURES

5.2

The LAB-8/E is constructed of highlyqeliable MSI lC logic modules. Use of these circuits and a minimum amount
of preventive maintenance ensures relatively little equipment downtime due to failure.

If a malfunction occurs,

maintenance personnel should analyze the condition and correct it as indicated in the following paragraphs. A

broad-bandwidth oscilloscope, an EDC voltage source, and a multimeter are the only special test equipment re-

quired for corrective maintenance. The best corrective maintenance tool is a thorough understanding of the physical and electrical characteristics of the equipment. Persons responsible for maintenance should become thorough-

ly familiar with the system concept, the logic drawings, the operation of specific lC circuits, and the location of
mechanical electrical components.
It is virtually impossible to outline any specific procedures for locating faults within complex digital systems such
as the

LAB-8/ E; however, diagnosis and remedial action for a fault condition can be undertaken logically and sys

tematically in the following phases:

Preliminary investigation

5.2.1

System troubleshooting

95.509.5.69)

Logic troubleshooting
Circuit troubleshooting

Repairs and replacement
Validation tests

Log Entry
Preliminary Investigation

Before beginning troubleshooting procedures, explore every possible source of information. Gather all available
information from those users who have encountered the problem and check the system log book for any previous
reference to the problem. The troubleshooting flowchart (see Figure 5—1) should be used to localize the problem.
This flowchart is not a complete guide to determining system fault; it is intended to give the user some thoughts
on where a
on

problem could'be, possible solution, and how to describe it to the DEC representative before he arrives

site.

Do not attempt to troubleshoot by use of complex system programs alone.

Run the MAINDEC programs and se-

lect the shortest, simplest program available that exhibits the error conditions. MAINDEC programs are carefully
written to include program loops for assistance in system and logic troubleshooting.

5.2.2

System Troubleshooting

When the problem is understood and the proper program is selected, the logical section of the system at fault
should be determined. The program that has been selected gives a reasonable idea of what section of the system
is failing; however, faults in equipment that transmit or receive information, or improper connection of the system,

frequently give indications similar to those caused by computer malfunctions.

5—9

PANEL
LIGHTS ON

CALIBRATE

?
POWER

SUPPLY

CAN

YOU LOAD

REPAIR OR
REPLACE
REFER TO

PARA.

5.4

START DEPOSIT
8x

E)?(AM
CPU
REPAIR OR

CALIBRATE

RIM

CHECK

REPAIR OR
REPLACE
REFER TO
PARA 5.4

PERFORM
DIAGNOSTICS
TABLE 2-25

LOADERS
LOAD MEMORY
TESTS

BINARY

01:9

REPAIR OR
REPLACE

GOOD
SUM CHECK

ELIMINATE BY
DISCONNECTING
PERIPHERAL 8/
OR INTERFACE

(AC;O)

I
REPAIR OR
REPLACE

YES
RUN
TTY TEST
TABLE 2‘3
OF POP 8/E

MAINTENANCE
MANUAL

PERFORMO FF- LI N E

*PROBLEM IN

CHECK BI ADJUST
OR REPLACE

OPTION OR
PERIPHERAL
NOT CHECKED
PERFORM

ACCEPTANCE

DIAGNOSTICS

DOES
TEST RUN

PROCEDURES
IN PARA 2 .5

REFER TO
VOLUME III
OF PDPB/E
MAINTENANCE
MANUAL

IN ACCEPTANCE
TEST 2

MEMORY

BE-OZSZ

Figure 54

System Troubleshooting Flow Chart

Disconnect any peripheral devices that are not necessary to operate the failing program. At this time, reduce the

program to its simplest oscilloscope loop and duplicate this loop in a dissimilar portion

of memory to verify, for

instance, that an operation failure is not dependent on memory location. This process can aid in distinguishing
the problem to a modmemory failures from processor failures. The techniques described above often pinpoint

ule or several le.

5.2.3

Logic Troubleshooting

Before attempting to troubleshoot the logic, make certain that proper and calibrated test equipment is available.

Always calibrate the vertical preamplifier and probes of an oscilloscope before using. Make sure the oscilloscope
has a good ground via the ac line cord, and keep the ground to the probe as short as possible with the aid of probe

ground leads.
To extend the suspected module in the OMNlBUS, perform the following procedure:
Procedure

Step
1

Turn off power.
Remove the H851 Edge Connector, if applicable, from the module.
Remove the module.

(humor-bom

Insert two double—extender boards into the same slot.

Insert the suspected module into the extender board.
If applicable, connect the two edge connector extender cables (BC08M~OM).
Turn power on.

Use lC pin extender for signal tracing and for grounding the oscilloscope.

NOTE
Test points on individual modules can be observed

by connecting the oscilloscope to available pins on
the extender.
Use the oscilloscope and IC pin extender to trace signal flow through the suspected logic elements.

Oscilloscope

sweep can be synchronized by control pulses or by level transitions which are available on individual IC pins at

the component side of the module. Exercise care when probing the logic, to prevent shorting between pins.

Shorting of signal pins to power supply pins can result in damaged components. Within modules, unused gate inputs are held at +3V.
NOTE
If vibration of the LAB-8/ E is desired during trouble-

shooting, make certain that the vibration amplitude
is low enough that inter-module shorts will not occur.
5.2.4

Circuit Troubleshooting

Engineering schematic diagrams of each module are supplied with each LAB-8/E System and should be referred
to for detailed circuit information.

Visually inspect the module on the component side and the printed wiring side to check for heated or broken
components, or etch. If this inspection fails to reveal the cause of trouble, or to confirm a fault condition ob-

served, use the multimeter to measure resistance of suspected components.

511

CAUTION
Do not use the lowest or highest resistance ranges of
the multimeter when checking semiconductor devices.
The X10 range is suggested. Failure to heed this

warning may result in damage to components.
Measure the forward and reverse resistances of diodes. Diodes should measure approximately 2082 forward and

100052 reverse. If readings in each direction are the same and no parallel paths exist, replace the diode.

more than

Measure the emitter-collector, collector-base, and emitter-base resistances of transistors in both directions. Short
circuits between collector and emitter, or an open circuit in the base-emitter path, cause most failures. A good
transistor indicates an open circuit in both directions between collector and emitter.

Normally 50 to 10082 exist

between the emitter and the base, or between the collector and the base in the forward direction; an open circuit
condition exists in the reverse direction. To determine forward and reverse directions, consider a transistor as two

diodes connected back-to-back. In this analogy, PNP transistors would have both cathodes connected together to
form the base, and both the emitter and collector would assume the function of an anode.

ln NPN transistors,

the base would be a common-anode connection; and both the emitter and collector, the cathode.
Multimeter polarity must be checked before measuring resistance because many meters apply a positive voltage to

the common lead when in the resistance mode.

le contain complex integrated circuits with only the input, output, and power terminals available; thus, static
multimeter testing is limited to continuity checks for shorts between terminals.

lC checking is best done under

dynamic conditions using a module extender to make terminals readily accessible. Using LAB-8/E logic diagrams
and M-series module schematics, locate an IC on a circuit board as follows:

Procedure

Step
1

Hold the module with the handle in your left hand; component side facing you.

le are numbered starting at the contact side of the board; upper right-hand corner.

The numbers increase toward the handle.

When a row is complete, the next IC is located in the next row at the contact end
of the board (see Figure 5-2).

5.2.5

The pins on each lC are located as shown in Figure 5-3.

Repairs and Replacements

When soldering semiconductor devices (transistor, diodes, rectifiers, or integrated circuits) that may be damaged

by heat, physical shock, or excessive electrical current, take the following special precautions:

Step

Procedure

Use a heat sink, such as a pair of pliers, to grip the lead between the joint and de—
vice being soldered.

Use a 6V iron with an' isolation transformer. Use the smallest iron adequate for the
work. Use of an iron without an isolation transformer may result in excessive vol-

tages presented at the iron tip. Use only pencil-pointed tip soldering irons on PC
boards.
3

Perform the soldering operation in the shortest possible time to prevent damage to
the component and delamination of the etched wiring.

(continued on next page)

5-12

SIDE1

VIEW

M—

Ple ABC ——--——-—>TUV
o

510

L.___

TV—
E9

_.__l

irl

I’l

vUT<—-———- CBA PINS

SE-OO'IG

Figure 5-2

lC Location

TOP VIEW
14

l—‘ll—ll—‘lmf—ll—IF—l

L_.IL_JI_IL._JL_II_J[_|
1

Figure 5-3

IC Pin Location

Step

Procedure

An IC may be removed by using a solder puller to remove all excessive solder from
contacts and then, by straightening the leads, lift the IC from its terminal points.

If it is not desired to save the defective IC for test purposes, perform steps 5

through 6. If the IC is to be saved, perform steps 7 through 12 (remove IC following step 8).
5

Clip lC leads at top of lead at the connection to chip.

Remove chip portion of IC.

(continued on next page)

5-13

Procedure

Step

Apply heat to individual leads from side 1 and remove leads slowly from side 1,
using a pair of needle nose pliers. Do not hold lead with pliers while applying heat;
the pliers will act as a heat sink.
Turn module over to side 2 and heat each hole individually, removing excess solder

with desoldering tool.
Insert new component, bending appropriate leads.

(Only leads with tear drop leads

should be bent; they should be bent in the direction of the point.)
10

Clip protruding leads of components from side 2. Do not cut flush with the module. (Leads and solderjoints cannot exceed 1/16 in. from bottom of the module.)

Solder all leads on side 2.

Clean flux from both sides of module with trichlorethylene, freon, or equivalent.
Be careful; both substances will damage the plastic handle.

In all soldering and unsoldering operations in the repair and replacement of parts, avoid placing excessive solder
or flux on

adjacent parts or service lines. When repair has been completed, remove all excess flux by washing

junctions with a solvent such as trichlorethylene. Be very careful not to expose painted or plastic surfaces to this
solvent.

CAUTION
Never attempt to remove solder from terminal points

by heating and rapping module against another surface. This practice can result in module or component damage.

Remove solder with a solder-sucking

tool or solderwick.
When removing any part of the equipment for repair and replacement, make certain that all leads or wires that are

unsoldered, or othenNise disconnected, are legibly tagged or marked for identification with their respective terminals.

Replace defective components only with parts of equal or better quality and equal tolerance.

To remove a switch on the programmer’s console, follow the procedure below:

Procedure

Step
—-I

Turn off power.
Loosen Allen screw and remove knob from rotary switch.

Remove four screws from Bezel.

(OONOU'l-bw

Carefully remove the face plate.
Remove two screws retaining aluminum mounting bracket.
Remove two wires from tab terminals on the left-hand side of the console.
Remove programmer’s console board.

Remove faulty switch.
When replacing the panel, the yellow wire goes to the top tab terminal and the blue
wire on the bottom.

5-14

To remove the power supply heat—sink assembly (see Paragraph 5.2.10), follow the procedure below:

Procedure

Step
1

Remove ac power by turning off 081 and disconnecting the ac plug.

NOTE
If the LAB-8/ E is rack-mounted, remove carefully

and place on table.
2

Remove the power supply assembly from the chassis as follows:
a.

Remove five Phillips-head screws. Two are located on the front side

of the chassis, one on the rear side, and two on the left side.
NOTE
If the LAB-8/E is rack-mounted, the chassis tracks

and the five mounting screws must be removed.
b.
0.

Unplug the OMNIBUS power and switch power harness.
Lift up the power supply and slide it back just far enough to remove
the blue and the yellow power wires from the front panel.

0'.
3

Lift out the power supply.

Remove the protective screen from the side of the power supply by removing the
12 countersunk screws on the screen.
Remove the heat-sink assembly as follows:

5.2.6

Remove the nylon plug from the heat-sink assembly bracket.

Remove the six screws from the heat-sink assembly bracket.

Lift out the heat-sink assembly.

During replacement, the yellow wire goes to the top tab terminal of the front panel.

Validation Tests

If a defective module is replaced. by a new one while repairs are being made, tag the defective module noting the
nature of the failure.

When repairs are completed, ascertain that the repairs have resolved the problem.

To confirm that repairs have been completed, run all the tests that originally exhibited the problem.

If modules

have been moved during the troubleshooting period, return all modules to their original positions before running
the validation tests.

5.2.7

Log Entry

A log book is supplied with each LAB-8/ E System. Corrective maintenance is not complete until all activities are

recorded in the log book.

Record all data indicating the symptoms given by the fault, the method of fault detec-

tion, the component at fault, and any comments that would be helpful in maintaining the equipment in the future.
The log book should be maintained on a daily basis, recording all operator usage and preventive maintenance results.

5-15

5.2.8

CPU Troubleshooting

After it is established that the CPU is causing the problem (see Figure 5—1), Table 5-3 can be used as a trouble-

shooting aid to isolate the trouble. The symptoms and causes are examples that may help the computer technician
find the area in which to look, once an abnormal indication is noted on the programmer's console.

Table 53

Processor Troubleshooting
Item

Symptom

A signal on the OMNIBUS is always low.

Likely Cause

Module

Bus loads, diode from ground to the

M832

OMNIBUS is shorted.
2

Unable to start automatic operations

Missing MEM START, M883, which is a

KC8/E

300- to 500-ns pulse for everytime CONT,

(RUN light always off).

DEP, or EXAM key is depressed
b.

POWER NOT OK L delayed, or POWER
NOT OK L is true.

M831

Unable to change major states.

Missing CPMA LOAD L. MA, MS LOAD
CONT grounded.

Unable to modify any memory locations.

MB LOAD

M831

Memory direction always low

M833

INHIBIT H always low, WRITE stays low

M833

d. WRITE stays low

M833

SOURCE stays low

M833

FIELD L is high

G104

(Refer to Table 54, Memory Data Errors.)
5

Data from memory is not getting to the
MB-

Memory direction always high

M833

No MB LOAD

M831

No TIME STROBE

G104

d. WRITE staying high

M833

(Refer to Table 5-4, Memory Data Errors.)
6

When loading an address, the word in the

LA ENABLE is always high (this causes the

MA is not the same as the switch register.

switch register to be ORed with the AC,

KC8/E

MO, or STATUS if the rotary switch is in
positions).

one of these

M831

When using ADDR LOAD, DEP or

ENO,EN1, EN2, or LEFT, RIGHT, TWICE

EXAM, the MA changes to an incorrect

are

value (EX:0020 <- 0634).

M831 logic print, sheet 3 of 3.

Depressing ADD R LOAD key will enter

DATA T always high.

M831

The MA decrements when doing an

DATA F is always low. Refer to truth table

M831

EXAM or DEPOSIT.

incorrect levels.

Refer to truth table on

all 1's in the MA. By examining and ob-

serving the MD, it will be noted that the
register will change when the key is released.

M831 logic print, sheet 3 of 3.

(continued on next page)

5-16

Table 5-3 (Cont)
Processor Troubleshooting
Item

Likely Cause

Symptom

(lfjust one of MA 0—4,

Module

M831

When doing an EXAM, DEPOSIT,

PAGE Z is high.

CONTINUE, or a JUMP instruction, the

check PAGE 2 circuit on M830.)

M830

CARRY IN L is always high to the adder. It

M831

MA bits 0—4 are zeroed.
11

CPMA, MB, PC, or AC do not increment.

should be generated:
3.

During T31 with DEP, EXAM, or EX TO
LOAD depressed.
T31 of FETCH state.
T32 of DEFER state.

EXECUTE state and T32 of an ISZ, or
T33 of a JMS.

T33 of a group 2 OPR instruction.
If SKIP is set: T32 of EXECUTE doing a

JMS, or T34 of an MRI.
12

Unable to Skip on an ISZ instruction.

Information being read from Teletype is
loading into MA and PC.

.9.

SKIP flip-flop will not clear.

No carryout.

No overflow.

M831

C2 is always low, which causes PC LOAD at

M832

Bus Strobe (TP3) time instead of AC loading.

M831
M833

When troubleshooting the LAB—8/E, remember that the OMNIBUS is designed so that all pins that are lettered
the same are connected to each other, and that a signal can be provided from more than one place. An example
is MD06, which is on pins BM1 of all slots of the OMN IBUS. The source of MD06 can come from either the

Major Register module (M830) or the Sense/Inhibit module (G104) and is used by five of the nine modules in
the basic computer. To find the source and destination of all the signals used in the basic computer, refer to

Appendix B.
5.2.9

Memory Troubleshooting

Establish that the memory is the source of the problem through system analysis, using the system troubleshooting
flowchart in Figure 5-1, the memory troubleshooting flowchart in Figure 5-4, sheets 1 and 2, and associated

troubleshooting Tables 5-4 and 5-5. The waveforms in Figure 5—5 may then be used to isolate the problem.

5-17

LOAD CHECKER B OARD
MAINDEC

RUN CHBD.

RUN FOR .10
MINUTES
(TWO TYPE- OUTS)
RUN CHECKER
I

BOARD HIGH
SA 7600

HLT

AT ERROR
LOCATION
P

RECORD AC
FOR INCORRECT
DATA

8I‘9

HLT
AT ERROR

“'35
I

LOCA;ION

DOES
CHBD HIGH
RUN

YES

R U N M EMORY

AD DRESS
TEST

DEPRESS
CONT.

a.
RECORD AC
FOR FAILING
ADDRESS

TROUBLE SHOOT
UTILIZING TABLES
4-4.4-5 BI FIG .4-5

RUN
INST. TEST
PART 1,ETC.

YE 3

6
NO

ENOUGH

INFORMATION
,3

FAILURE IS MOST
LIKELY IN 6227
OR IN DIODES ON
MEMORY STACK

GO TO PRINT
FOR 6104 FOLLOW
AND SCOPE CIRCUIT
CHAIN FOR BITIS)

8—.

DERESS
CONT.

WHEN FINISHED

MAKE APPROPRIATE
CHBD

LOW

LOG ENTRY

CHBD HIGH
8E-0I45

Figure 5-4 Memory Troubleshooting Flowchart

BE-Ol46

Table 5-4

Memory Data Errors

—

Module

Cause

Symptom

Possible Causes
Check

One Bit

1 OR 0

Inhibit Driver

G 104

Collector of 2007 transistors

One Bit

1 OR 0

Sense Amplifier

G104

E31—42 pin 8

1 OR 0

Time Strobe

G104

E9—3

Random

Random/All
Random/All
Random/All
Random/All

Random/All
Random

XY current/voltage is low

6227

XY current/voltage is high

6227

Same as above

Slice voltage low

6104

5.3V across gnd and test point DA1

Slice voltage high

6104

5.3V across gnd and test point DA1

Inhibit current/voltage low

6227

—-15 Vdc power

Inhibit current/voltage high

6227

—15 Vdc power

5.3V across +5V and pin JU2

Table 55

Memory Module Test Point Voltage Levels
Pin

8'9 nal

Approximate
Readings

HA1

6104

1.2V

HV2

6104

2.3V

JU2

6227

1.4V

FU2

G104

0.25V

Test Point

DA1

6104

~5.3V

Test Point

CB1

6104

Test Point

D81

6104

—6V

Current Source

HU2

6104

FA1

6104

2.3V

F31

6104

-4V

017 emitter

6104

—4.8V

Current Control

Current Source

Top of thermistor

Memory Stack
Test Points

5.2.9.1

Module

Memory Resistance Checks

—-

2.5V

018 collector

6104

-6V

Q15, 16 emitter

G104

+3V

013 base

6104

+1 .3V

Some resistance checks that can be performed to aid in isolating a trouble

in the memory are summarized below:

Procedure

Step
1

Turn off power.

Remove memory stack module.

Resistance of thermistor network is approximately 1509.

Resistance of individual thermistor when out of the circuit is approximately 5652.

Resistance of winding for one bit is approximately 352 (for example, between pins
FA and FB for bit 6).

(continued on next page)

5-19

Procedure

Step
6

Resistance of diodes FSA2501 is as follows: forward
reverse

—

approximately 2452;

approximately greater than 1 MSZ.
CAUTION

Metal can transistors have their casing connected to

the collector. Care should be exercised to prevent
a ground lead or the back of another module from
touching the metal can during troubleshooting.

OV
PIN EK?
DURING READ
RXO (G227)

l5V

—l5V

l
F—lAps—‘i

+5V

PIN EKI
DURING WRITE
WXO (G227)

I
l

20V
-l5V

+5V
PIN FP2
INHIBIT FOR

11 (6104)
-|5V

+5V

PIN EH2
DRIVE VOLTAGE
FOR Y70 (6227)
-l5V
EXAMPLE OF WAVE FORMS
DURING SLOW CYCLE AND
RUNNING INCREMENT AC
TEST ROUTINE
8E—0070

Figure 5-5 Memory Waveforms
5.2.9.2

Memory Circuit Variables

—

There are a number of variables in the MM8—E memory system, such as cur-

rent, slice, and field, that have to be set properly.

Although some of the settings are permanent for a particular

board, interchangeability in the field is assured. These variables are summarized in Table 5-6 and detailed in the

following paragraphs.
Table 5-6

Memory Circuit Variables
Variables on MMS-E

Means for Settings

Memory System
Field Select

Three Jumpers:

EMAO, EMA1,

Location

Who Makes the Settings

G 104

Factory or Field Service

EMA2

Strobe

6-position rotary switch

Slice

Two Jumpers:

SLA, ALB

XY Current Control

Two Jumpers:

CCA, CCB

Temperature Tracking

Thermistor/Resistor Combination

R1, R2, R3

5-20

G 104

Factory or Field Service

G104

Factory only

G227

Factory only

G619

Factory only

5.2.9.2.1

Field Select Jumpers

—

The octal combination of the appropriate cut jumpers represents the selected

field; therefore, for the basic system (no extended memory), all jumpers must be in place.
5.2.9.2.2

Strobe Adjustment

A 6-position rotary switch optimizes the strobe positioning in discrete steps of

—

10 ns. For detailed setting procedures, see Paragraph 5.2.9.7.

5.2.9.2.3

Slice Level

——

Any variation on the +5V power supply will cause a proportional change of the absolute

value of the slice level. The slice level can be set to four different levels according to the following truth table:

Slice Level

Jumpers
SLA

SLB

(Test point DA‘I on G104)

-4.3V

Out

—4.8V

Out

-5.3V

Out

-6V
CAUTION

Do not field-adjust the slice level under any circumstances.

5.2.9.2.4

XY Current Control (G227)

—

On the G227 module there are two jumpers in the upper center of the

module. These jumpers can be removed and a 24 AWG wire loop soldered in their place, if it is necessary to
measure currents with a current probe.

The XY current control can be set to four discrete levels to calibrate the current source. The nominal voltage

Its corresponding XY current is 370 mA, measured on a loop between the XY drive and

varies with temperature.

the stack module. The pertinent truth table follows:
Current Control Voltage
(Voltage across +5V and Pin JU2 on 6227)

Jumpers
CCB

CCA
In

+3.7V

Out

+2.2V

Out

(~ +3.5V at 25°C)

Out

—1.7V

CAUTION
Do not field-adjust current control voltage under any

circumstances.

5.2.9.2.5

Temperature Tracking

—

A thermistor/resistor combination on the memory stack module provides a

temperature-sensitive voltage divider that is connected to the current control circuit.
5.2.9.2.6

Inhibit Current

The inhibit current is fixed; however, it varies proportionally to the —15V supply

and its corresponding nominal value is 340 mA.

5.2.9.2.7

Strobe Setting Procedure

——

Setting the strobe properly is very important and must be done carefully.

The chosen setting scheme makes this procedure relatively simple.
the XY current-sense amplifier output and strobe.

5—21

Figure 5-6 illustrates the relationship between

X-Y CURRENT

"‘" S'GNAL

SENSE AMP
OUTPUT PIN IO

"0'55

"0" SIGNAL

STROBE DELAY TIME

TIME STROBE

PIN 9

32?.235
swnc”

CLOCKWISE = INCREASE DELAY
COUNTER CLOCKW|$E= DECREASE
/

NOMINAL
tl
STROBE ADJUSTMENT POT

"I" OUTPUT +5V
0F SENSE
AMP (MCI540)
PIN8

ov
8E-OO7I

Figure 5-6 Setting of Strobe
It is not advisable to set the strobe timing using an oscilloscope and a current probe.

Because of the length of the

current probe cables, the bandwidth of the probe and scope may vary in each case.

The resulting correlation error

can exceed the tolerance

allowed, resulting in a misadjusted memory. To set the strobe accurately, perform the

following procedure at room temperature:

Step

Procedure

The switch has to be set to one of the three possible nominal positions (see Figure

5-6).
2

Load and run Memory Checkerboard maintenance program (MAlNDEC-8E-D1AA-D).

Program should run without error.

Halt program and delay strobe 10 ns (1 position clockwise), then restart.

If program still runs without error, proceed to the next position. When errors occur,

stop and memorize this strobe position.
6

Repeat the same procedure advancing the strobe (counterclockwise) until errors
occur, then stop and memorize this position.

A reliable system must have a minimum of three working consecutive positions.

Finally, set strobe to the middle working position. lf there is an even number of
working positions, favor the most delayed (clockwise) of the two center positions.
In checkout, Memory Checkerboard should always run in the middle position, and

for at least 15 min in the positions to the left and right of middle with no errors.
10

Acceptance is to be run only in the final strobe position.

Setting strobe for External Memories, load basic Memory Checkerboard into Extended Fields and proceed to set strobe position according to steps 1 through 10.

5-22

5.2.10

H724 Power Supply Troubleshooting Procedures

The H724 power supply provides power for CP logic, memory, bus loads, and the lamps on the programmer's
console.

If the power supply is established to be the source of the problem through symptom analysis, with the

aid of the system troubleshooting chart (see Figure 5-1), voltage checks should be performed.
ances are given in Table 5—7.

Voltages and toler-

Component troubleshooting aid, Table 5—8, is included as an aid to isolating and cor-

recting the malfunction.
Table 5-7

H724 Power Supply Parameters

Output Voltage

Wire

Minimum

Maximum

Color

Voltage

Current Maximum

Tolerance

Rating Ripple

+5V

Red

4.85V

5.15V

t3%

20A, 50 mV pp

—15V

Blue

-14.25V

—15.75V

i5%

8A, 50 mV pp

+15V

Orange

13.5V

16.5V

110%

1A, 75 mV pp

+8V

Yellow

10V

i26%

dc voltage OK

Gray

3.75V

126%

0.2A

Overvoltage
Protection

6.5V

14 Vac

AC INTLK

0.12A

Table 58

Component Troubleshooting Aid for H724 Power Supply

Output Voltage
+5 Vdc

Wire

Jack

Color

Red

J3-3

+15 Vdc

Blue

Orange

J3-4

Transistors

Adjustment

Use

25A

0200

R21

CPU Logic

Memory

Bus Loads

0201-6
10A

0300

J44

0301

J6-3

0304

J3-5

Module

J4—3
-15 Vdc

Fuse

0100

J4—5
+8 Vdc
14 Vdc

Yellow
—

J6—4

25A

Lights

J5—1

.5A

Options

J5-3

Overvoltage

Power Surge

Protection
dc voltage 0 K

( 3.75)

Gray

J3-6

J4-6

R29

(FactoryAdjustable
Only)

NOTE: Static ohmmeter reading of thermistor is approximately 2352.

5-23

Power Loss

The following paragraphs describe some of the power supply features and characteristics that may aid in isolating

the malfunction.

5.2.10.1

Overcurrent Protection

—

The power supply should not be loaded by more than 175 percent of the

rated output current (see Table 5-7).

5.2.10.2

Hold-Up Time

The regulated output voltages under maximum load conditions should remain stable

—-

for a minimum of 2 ms after loss of line voltage.

5.2.10.3

Thermal Protection

A thermal switch is in series with the interlock circuit. This switch is located in

the fon/vard top section of the power supply.

It will disconnect primary power at 90°C 5°C. The thermal switch

must be reset manually if it is tripped.

5.2.10.4

Contact Protection

—-

Contact protection is provided to limit the primary power at the input to the

convenience outlet to twice the nominal peak voltage.

In addition, protection is provided against a rate of change

in the voltage exceeding 10V per second as the solenoid or circuit breaker is Opened.

5.2.10.5

Input Switching

—

The primary power is switched by a 24—Vdc relay, controlled by an interlock circuit.

Grounding pin A on the interlock panel will operate the solenoid and apply power to the computer.

The solenoid

will break both sides of the line.

5.2.10.6

POWER ON/OFF Switch Adjustment

-—

The POWER ON/OFF switch is cam-adjusted according to

Table 5-9.

Table 5-9
POWER ON/OFF Switch Adjustment
Three Cam-Operated Switches

Power Switch Position

Switch Position
Back 2 Switches

5.2.10.7

Front Switch

0FF

OFF

PANEL LOCK

OFF

Parallel Operation

—

Two or more power supplies must not be wired in parallel to extend the current

driving capability.
5.2.10.8

Large Configuration

—

When more than one box is in the system, the interlock panel is wired so that

the front panel power switch of the first box and the thermal cut-out switch of each additional box is in series
and will control power to all boxes, though they may be connected to independent primary power sources.

5-24

SECTION 3
TELETYPE MAINTENANCE

5.3

INTRODUCTION

This section contains information pertinent to the maintenance of the Teletype and associated control logic. Per-

form the test routines described in Paragraph 5.1.1 to localize trouble in the Teletype.

5.3.1

Special Tools

Table 5-10 lists the special tools needed for maintenance of the 33 ASR Teletype. All of these items may be obtained from Digital Equipment Corporation or from the Teletype Corporation.

Table 5-10

Teletype Maintenance Tools
Part Number

Item
Set of gauges

5.3.2

117781

Offset screwdriver

94644

Offset screwdriver

94645

Handwheel

161430

Handwheel adapter

181465

Contact adjustment tool

172060

Gauge

180587

Gauge

180588

Gauge

183103

Bending Tool

180993

Extractor

192697

Tweezer

1 51392

Spring hook (push)

142555

Spring hook (pull)

142554

Screw holder

151384

Programs

The Teletype control test referenced in Table 23 of Chapter 2 of the PDP-8/E Maintenance Manual serves as an
aid in maintaining the 33 ASR Teletype and associated control logic.

5-25

SECTION 4

SYSTEM CALIBRATION

5.4

CALIBRATION OF THE LAB-8/E OPTIONS

Once the problem has been pinned down to a specific LAB-8/ E option by performing the acceptance test (see

Figure 5-1), the calibration procedures should be run for a better indication of the problem. The problem might
be only a minor adjustment or a faulty component. The calibration procedures in the following paragraphs will
tell you what adjustments to make to correct the problem.

5.4.1

A/D Converter (AD8-EA) Calibration Procedure

The following steps will calibrate the A/D converter and check the analog multiplexer.

Paragraph 5.4.1.2 will be

performed when the readings obtained are non-linear.
5.4.1.1

Minor Calibration

—

Perform the following steps for a minor calibration of the ADS-EA:
Procedure

Step
1

Toggle in the following program to display converted value in the AC:
Location

Contents

200

Function

6530

Clear All

201

6532

Start conversion

202

6534

Skip next instruction if A/D DONE

203

5202

Wait for A/D DONE

204

6533

Read into AC

205

2220

Increment and Skip if 0

206

5205

Time delay for reading AC easily

207

5200

Restart

Connect the EDC voltage source output as shown

Table 511

2-7 and

allow a 2-min warm up.

Run display converted value in AC.

‘

'7"
7.? t? ‘7’”
.

ONODU'l-bw

Set EDC voltage source to W-

Adjust -5V reference formto m displayed in AC.

7 0 0‘0

70 a ’

Set EDC voltage source to +4.985V.

Adjust +5V reference for 0776 to 0777 in AC.
Set the EDC voltage source to values shown in Table 5-12 and check the AC read-

ings.
NOTE
If AC readings are non-linear, a major calibration may
be required.

5-27

Table 5-12

EDC Voltage and AC Readings

Table 5-11

EDC Connection to A841 Module

EDC Voltage

AC Reading

Si 9 nal In pu t

AM8‘ED or

7008533

+4.990

0777

AMB-EC Panel

Cable

+3750

0600

Red to LL

+
—

ground

5.4.1.2

Major Calibration

Black to NN

Shield

——

0400

0'000

0000

’2'500

7400

~3.750

7200

—5.000

7000-_.

The following steps will accomplish a major calibration of the A/DconVerter.

Procedure

Step
1

+2500

Turn power off.
Mount the A841 on module extender and connect to the A231 control module.

Install temporary jumper across split lugs marked SUM JUNCTION and H0
POWER on A841 module.

Turn power on and allow equipment to warm up for 20 min.

coowoum-b
10

Perform steps 1 and 2 of the minor calibration procedure (see Paragraph 5.4.1.1).
Run display converted value in the AC and adjust R60 for 0777—7000 in the AC.

Remove jumper from split lugs.
Connect EDC voltage source to A841 as shown in Table 5-11 and Figure 2-7.
Set EDC voltage source to —-4.692V and adjust negative reference to 7037—7040

switching point in the AC.
Refer to Table 5-13 and calibrate bits 5, 4, 3, and 012 as follows:
a.

Adjust EDC voltage source to find switching point listed in column 1.

Add +10 mV to negative voltage on EDC voltage source.

Adjust the potentiometer listed in column 3 to the switching point in the
AC listed in column 5.

Repeat for other bit positions.
NOTE

For example, in step a, adjust EDC to achieve 7076—
7077 switching in AC. If EDC reads 4.397V, reduce
to 4.387V and adjust bit 5 potentiometer to 7077—

7100 switching point. If bit 5 turns on while trying
to read 7076—7077, move it until problem ceases.

If any bit does not calibrate properly, set as close as
possible, finish the calibration, and attempt the cal—
ibration again.
11

Set EDC voltage source to +4.985V and adjust +5V reference potentiometer to

0776—0777 switching in the AC.

If this reading is obtained within :5 mV, no

adjustment is required.
12

Reinstall module in system, allow system to run for 20 min, and check all calibra—
tion points. The temperature change might make a minor calibration necessary.

5—28

Table 513

Major Calibration Voltages and AC Readings
Find

Switching
.

Pornt

5.4.2

A pproximate

Ad'ust
1

EDC Voltage

Potentiometer

Approximate
EDC Voltage

AC Reading

+10 mV

7076~7077

—4.390

Bit 5

~4.380

7077—7100

7176—7177

-3.765

Bit 4

-3.755

7177—7200

7376—7377

—2.515

Bit 3

~2.505

7377—7400

7776—7777

-0.015

Bit 012

—0.005

7777—0000

Common Mode Rejection (CMR) Calibration

If the CMR potentiometer has been moved or the user wishes the CMR to be peaked at a particular frequency,

perform the following steps:
NOTE
This calibration is performed for differential operation (with no AM8-EA) only.

Jumper W1 must be

installed on the A841 module and W2 must be re-

moved.
Procedure

Step
‘

.59...

Connect a sine wave generator to i analog input as shown in Figure 5-7.
NOTE
Source output impedance must be less than 2052.

Monitor AA1 on the A841 module with an oscilloscope.

Set sine wave generator to 60 Hz or desired frequency. Signal input should be

3V/rms.
4

Adjust OMB for a minimum signal (nulled) at AA1.
NOTE
If a sine wave generator is not available, pins LL and
NN can be jumpered together to allow adjustment

potentiometer for minimum noise signal
(nulled) at AA1.

of CMR

*PIN LL‘

ANALOG +
ANALOG

*PIN Nu

ADB'E

SINE WAVE
GENERATOR
GROUND

*PINS

LL, NN AND VV

ARE

3
ON

*PIN

vv
‘

A841

SIDE CONNECTOR.
8E-03l2

Figure 5-7 AD8-EA Common Mode Rejection Calibration Connection
5.4.3

Calibration of the Point-Plot Display Control (VC8—E) Using VR14 or Tektronix 602 Display

Perform the following steps to calibrate the Point-Plot Display Control using the VR 14 or Tektronix 602:
NOTE

The VR14 or Tektronix 602 must be calibrated be-

fore performing this procedure. Refer to the calibration procedure for the VR14 in Paragraph 5.4.6.
529

Procedure

Step

Place M885 module on extender modules using a jumper cable from the F connector on the M885 to the F connector on the M869.

Place the DVM or the null meter between pin UU (+5V) and pin F (gnd) in the

Berg connector located on the M885 module.
Adjust R50 (upper right—hand corner on the M885) for 5.120V to i.002V.
Place the DVM or the null meter between pin SS (+5V) and pin F (gnd) on the

Berg connector located on the M885 module.
Adjust R55 (upper right—hand corner on the M885) for 5.120V $.002V.
Load and start VC8-E diagnostic according to diagnostic write-up.
Select TEST 4 of the diagnostic write-up. Use this test to calibrate the X-axis and

Y-axis D/A converters as follows:
a.

Xaxis=bit1=0

Type out

Procedure

0000

Place the DVM or null meter between pin D (X output) and pin F (gnd) on the Berg connector. Adjust

R86 for UV i.002V.
0001

There should be no discernable breaks or overlaps in

0003

the line displayed.

0007

correct or the diode to +5V reference shorted or

0017

opened.

If there are, a resistor value is in

0037

0077

Adjust R29 for no gaps or overlap.

0177

Adjust R34 for no gaps or overlap.

0377

Adjust R38 for no gaps or overlap.

0777

Adjust R42 for no gaps or overlap.

1777

Adjust R46 for no gaps or overlap.

Yaxis=bit 1 =1
Procedure

Type out
0000

Place the DVM or null meter between pin L (Y out-

put) and pin F (gnd) on the Berg connector. Adjust
R88 for UV i.002V.
0001

There should be no discernable breaks or overlaps in

0003

the line displayed.

0007

correct or the diode to +5V reference shorted or

0017

opened.

If there are, a resistor value is in-

0037
0077
0177
0377

0777
1777

Adjust R116 for no gaps or overlaps
Adjust R121 for no gaps or overlaps
Adjust R 125 for no gaps or overlaps
Adjust R129 for no gaps or overlaps
Adjust R 133 for no gaps or overlaps
(continued on next page)

5-30

Procedure

Step
Select TEST 6.

If the image is not within 1/4 in. of the edge of the screen, adjust

R55 (gain for Y). There will be an interaction between R55 and R88. This proce
dure will require readjusting R88 as in step 7 b.

Select TEST 7.

If the image is not within 1/4 in. of the edge of the screen, adjust

R50 (gain for X). This procedure will require readjusting R86 as in step 7 a.
10

Select TEST 11. A straight diagonal line should be displayed. Check for gaps, over-

laps, or steps in the line. If any small inconsistancies are seen, repeat steps 7 a and
7 b.

5.4.4

VC8-E Calibration Procedure Without a VR14 or VR03

Perform the following steps to calibrate the VC8—E when a VR14 or VR03 is not used:

Step

Procedure

Place M885 module on extender boards, and connect the jumper cable from the F
connector on the M885 to the F connector on the M869.

Place the DVM or the null meter between pin UU (+5V) and pin F (gnd) on the
Berg connector located on the M885 module.

Adjust R50 (upper right-hand corner on the M885) for 5.120V 1.002V.
Place the DVM or the null meter between pin 88 (+5V) and pin F (gnd) on the Berg
connector on the M885 module.

Adjust R55 (upper right-hand corner on the M885) for 5.120V 1.002V.
Load and start VC8—E diagnostic according to diagnostic write-up.

Select TEST 3. Place the DVM or the null meter between pin D (X output) and

pin F (gnd) on the Berg connector on the M885.
NOTE

Voltage readings k1, k2, etc., are taken as a reference
for the following step.
a.

X axis

Procedure

Type out
0777

Adjust R86 for 5.11V i.005V.

0776

Read 5.100V $.005V.

0775

Read 5.090V i.005V.

0773

Read 5.070V i.005V.

0767

Read 5. 030V 1.005V.

0757

Read 4.950V i.005V.

0740

Read voltage K1.

0737

Adjust R29 for k1 —10 mV i.002V.

0700

Read voltage K2.

(continued on next page)

5-31

Procedure

Step
a.

X axis (cont)

(cont)

Typeout

Procedure

0677

Adjust R34 for k2 —10 mV i.002V.

0600

Read voltage k3.

0577

Adjust R38 for k3 —10 mV 1.002V.

0400

Read voltage k4.

0377

Adjust R42 for k4 —10 mV $.002V.

0000

Adjust R86 for UV i.002V.

1777

Adjust R46 for —10 mV.

Y axis

—

Place the DVM or null meter between pin L (Y output) and pin

F (gnd) on the Berg connector on the M885.

Procedure

Typeout

5.4.5

0777

Adjust R88 for 5.110V 1.002V.

0776

Read 5.100V 1.002V.

0775

Read 5.090V 1.002V.

0773

Read 5.070V i.002V.

0767

Read 5.030V $.002V.

0757

Read 4.950V i.002V.

0740

Read voltage k1.

0737

Adjust R116 for k1 —10 mV i.002V.

0700

Read voltage k2.

0677

Adjust R 121 for k2 —10 mV i.002V.

0600

Read voltage k3.

0577

Adjust R 125 for k3

0400

Read k4.

0377

Adjust R 129 for k4

0000

Adjust R88 for 0V 1.002V.

1777

Adjust R 133 for —10 mV.

—

10 mV i.002V.

Analog Preamplifier and Multiplexer (AM8-EA) Calibration Procedure

Perform the following steps to calibrate the preamplifiers in the AM8-EA:

Step
1

Procedure
Load A/D converter (AD8-EA) and Analog Preamplifier and Multiplexer (AM8—EA)

diagnostic.
Run display converted value in AC test.

(continued on next page)

5-32

Procedu re

Step
3

Connect EDC voltage source to channel to be checked as shown in Table 5—14.

Table 5-14

AM8-EA Calibration Connections
EDC Output
+
-

AM8-EA Input
+ Channel

Voltage

Channel

Computer Ground

Ground

NOTE
Refer to Table 2-2 for pin numbers on all channels
4

Set EDC voltage source to 0V.

Read 0000 :2 counts in AC, if not adjust bias.
6

Set EDC voltage source to +0.9972, adjust gain for channel 00 to 0776—0777
i2 counts switching point in AC.

Set EDC voltage source to —.9991, check for 7000—7001 :2 counts switching

point in AC. If this is out of specification, readjust steps 5 and 6 until all readings
Refer to Table 2-28 for linearity checking.

are accurate.

NOTE
The gain and bias adjustments are located along the
side of the module (see Table 5-15).

5.4.6

Repeat steps 1 through 7 for all channels on the AM8-EA.

VR 14 Calibration

Perform the following steps to calibrate the VR 14:
Procedure

Step
1

Remove signal input cables on the rear of the VR 14.

Connect a meter between A02A and ground; adjust X position potentiometer for

UV.
3

Connect a meter between A03A and ground; adjust position potentiometer for UV.

Reconnect the signal input cable.

Run display in AC test.

Connect meter between A02A and ground; adjust X gain for i2.3V.

Connect meter between AO3A and ground; adjust Y gain for i2.3V.

5-33

5.4.7

Calibration of the Tektronix 602 Using the VC8-E

Perform the following steps to calibrate the Tektronix 602 oscilloscope.
NOTE
The VC8-E must be calibrated before connecting the

Tektronix 602.
Procedure

Step

Load VC8~E diagnostic. Follow instructions in the diagnostic document.
Load portion of diagnostic that displays a point.
When point is displayed in center of oscilloscope, adjust intensity and focus on the

Tektronix 602.

Adjust intensity and focus until point is in good focus.
Load test to display vertical line.

Adjust vertical gain and vertical position on the Tektronix 602 until the line spans
the front grid.
Load test to display horizontal line.

Adjust horizontal gain until it spans the horizontal grid.
Load ramp test and examine the line for discontinuity and position error.

Table 5—15
Gain and Bias Potentiometers
Channel

Distance from Top

Purpose

Gain

Bias

Gain

Bias

Gain

Bias

Gain

Bias

Gain

Bias

Gain

Bias

Gain

5’34

SECTION 5
PREVENTIVE MAINTENANCE PROCEDURES

5.5

PREVENTIVE MAINTENANCE

Teletype preventive maintenance should be scheduled every three months.
CAUTION
Do not use alcohol, mineral spirits, or other solvents
to clean plastic parts with protective decorative fin-

ishes.

Normally, a soft, dry cloth should be used to

clean parts or subassemblies.
To clean plastic surfaces, we recommend using any household cleaner/waxer liquid. To clean the printer platen,
we recommend a

lacquer thinner. During an overhaul, subassemblies and metal parts can be cleaned in a bath of

trichlorethylene. Proper lubrication should be performed often.
5.5.1

Weekly Tasks

The following procedures should be followed on a weekly basis:

Procedure

Step

5.5.2

Inspect platen and paper guides, wipe clean, using a soft, dry cloth.

Clean external areas of paper-tape punch and reader, using a soft brush or cloth.

Remove and empty the paper-tape punch chad box.

Run the Teletype control test for approximately 15 min.

Preventive Maintenance Tasks

Follow the procedure outlined below:

Step

Procedure

Inspect platen and paper guides. Clean platen, using a lacquer thinner to remove
shiny surface.
Clean ribbon guides and replace ribbon, if necessary.
Remove cover and check for vibration effects, loose nuts, screws, retaining clips, etc.
Clean distributor rotor and clean disk surface, using cotton swab moistened in freon
or

trichlorethylene.

Clean between selector magnet-pole piece and armature with bond paper to remove
any lubricant or dirt.

Clean and lubricate the Teletype, per Teletype Bulletin 2738.

Follow instructions

carefully; do not over lubricate.

(continued on next page)

5-35

Procedure

Step
7

The following adjustments should be checked.

Pages indicated are in Bulletin 2733,

Volume 2.

Trip Shaft

574-122-700

Page 13

Trip Lever

574-122-700

Page 14

Brush Holder (Distributor)

674-122—700

Page 15

Clutches

574-122-700

Pages 16—24

Code Bar Reset

574-122—700

Pages 30—34

Print Suppression

574-122-700

Page 35

Blocking Levers

574-122-700

Page 37

Print suppression

574-122-700

Page 43

Carriage Drive Ball

574-122-700

Page 44

Print Trip Lever

574-122-700

Pages 61—62

Dashpotentiometer

574-122-700

Page 78

Final printing alignment

574-122-700

Page 85

Line Feed

574-122~700

Page 89—95

Keyboard Trip Lever

574-122-700

Page 141

Reader Trip Lever

574-122-700

Pages 6—9

Detent Lever

574—124-700

Page 10

Sensing Pin

574-124-700

Page 15

Tape Lid Latch Handle

574-124-700

Page 18

Feed Pawl

574-124-700

Page 11

Registration

574-124-700

Page 12

Run each of the Teletype MAlND EC programs; at least two passes each.

Check that tape holes are being cleanly punched.

5-36

SECTION 6
CORRECTIVE MAINTENANCE

5.6

CORRECTIVE MAINTENANCE PROCEDURES

Details of the cable connector fusing and test points are included in Table 5-16. During off-line operation, the

keyboard distributor effectively drives the printer—selector magnet; thus, any character received from the keyboard
or paper-tape reader

is automatically reproduced on the printer and paper-tape punch.

During on-line operation,

this continuity is broken and a Teletype receiver (M865) is used to accept the input from the reader or keyboard,
while a Teletype transmitter (M865) is used to drive the printer and paper-tape punch.

Table 5-16

Connections of Teletype Cable
33 ASR

W0760

Mate-N-Lok

M865

Connections

Split Lug

Pin Number

Split Lug

(WC)

0 (WC)

*TB pin 6

TB pin 3
i15

3
4

+Relay

8 (WC)

0 (N/C)

-30V (WC)

Advance

3
4

TB pin 4

Printer

—Relay

TB pin 7
**To CP (F)

Reader

Keyboard

X
X

“Terminal board (TB)

“Wheellock Relay Card.

Table 5-17

Teletype Cabling, Fusing, and Test Points
Check

Reader

Fuses

1/2A

Terminal No.
Test Points

Transmitter

Receiver

3, 3/8, 2.5, 3A

6 and 4

7 and 3

5 and 2

DA1 Reader Run

ABl Receiver Active

A crystal clock is used to shift the bits through the transmitter and receiver buffers; therefore, no clock adjustments are required.

Most Teletype problems can be traced to one of the following.

33 ASR keyboard or reader

33 ASR printer or punch

M865 receiver/transmitter

Isolation of bit-related problems is relatively simple. Off-line duplication can usually determine whether the problem is in the teleprinter or the control logic. Steps may be taken to isolate the problem to subassemblies within
the teleprinter. Bit pick-up during a read operation can be caused by a defect in any of three sets of contacts that

5-37

are tied

in parallel.

Reader, keyboard, and answer—back contacts provide parallel inputs to the distributor contact

disk. Bit pick-up problems can be isolated to one of these areas by disengaging the related contact from the sus-

pected contact set.
Printer/ punch problems can sometimes be isolated by comparing the printed character with the output of the
paper-tape punch. If the printed character agrees with the punch output and both are incorrect, then the problem
lies in the selector mechanism or in the Teletype receiver/transmitter module (M865). If the printed character

disagrees with the paper-tape punch output and the paper-tape punch output is correct, then the problem lies
within the printer assembly. Figure 58 shows the Teletype signal relationship between the computer and the

Teletype.
PDP-BE
i

ACCUMULATOR
7

‘0

\
\

\\\
\

START

’

+ 2.5V

’

z’

/7//”,”/
/’/’
/

//”/

\/5;/,’

GND
I

UNIT

fil

____________

*4 ll

UNIT

2
UNITs

IIUNITs OF TIME

7‘
81—OOIO

Figure 5-8 Teletype Signal Waveform and Bit Relationship
for the Character U

5-38

SECTION 7
SPECIAL TROUBLESHOOTING PROCEDURES

5.7

TEST CLOCK (M499)

The Test Clock module serves as a troubleshooting tool for the LAB-8/E when problems within memory prevent
the use of troubleshooting programs. The M499 module provides a MEM START signal of 100— to 500m width

every 15 us with the DEP or EXAM key depressed. This procedure makes signals available for associated trouble—
shooting at a continuous rate. Troubleshooting procedures using the M499 Test Clock are as follows:
Procedure

Step
1

Insert M499 into any slot in row A of the OMNIBUS.

Refer to Figure 2—6 for open

slots.

Depress the SING STEP key on the programmer’s console.
3

The switch register may now be used in conjunction with the EXAM or DEP key
to check manual functions.

The EXAM or DEP key may be taped into the depressed position (thus leaving the

operator free).

5-39

CHAPTER 6
LAB-8/E SYSTEM SPARE PARTS

6.1

INTRODUCTION

This chapter identifies the recommended spare parts for the LAB-8/E System.
It is recommended that those spare parts needed to remove and replace components, in each of the options that

make up the LAB-8/ E System, be kept in stock at the computer facility to maintain minimum down time. If the
user desires, he can purchase modules from DEC to allow removal and replacement at the module

level. DEC

Field Engineers will have spare modules available, if they are needed.

6.2

LAB-8/E CENTRAL PROCESSOR (PDP-8/E and 33 ASR TELETYPE SPARE PARTS)

The PDP-8/E and 33 ASR Teletype spare parts are listed in Volume I, Chapter 5, of the PDP-8/E Maintenance
Manual.

6.3

BASIC LAB-8/E SYSTEM SPARE PARTS

The spare parts for each option in the basic LAB-8/E System are identified in Tables 61 through 65.

Table 6-1

Analog-To-Digital Converter (ADS-EA) Recommended Spare Parts
DEC Part

Number

Recommended

DEC Part

Number

Description

Number

Recommended

Description

11-03441

Diode 1N756A

19-05547

11-01385

Diode 1N825

19-05575

IC 7400

11-00144

Diode D664

19-09004

IC 7402

1509681

Transistor 2N5245

19-05579

IC 7440

1509338

Transistor DEC 6531

1909705

IC 881
IC 380

IC 7474

15-09142

Transistor 2N4250

19-09485

15-09090-01

Transistor DEC 6B

19-09686

IC 7404

1503100

Transistor 3009B

10-09935

IC 8235

15-08157

Transistor SBA-55

19-09373

IC 9601

15-01881

Transistor 2N2219

19—05580

IC 7450

19-09928

IC 7416

19-09486

IC 384

19-09848-03

IC BB 3278-2114

19-09704

IC 314

19-09761

IC 1439

19-09594

IC 8251

1909343

IC 302

19—10041

IC 74164

1909004

IC 7402

Table 6-2
Point-Plot Display Control (VCS-E) Spare Parts
DEC Part

Number

Recommended

Description

DEC Part

Number

Recommended

Description

15—01881

Transistor 2219

1909594

IC 8251

15-03100

Transistor 3009B

19-09485

IC 380

15-03409

Transistor 6534B

19-09373

IC 9601

15-05715

Transistor 2N4313

19-09058

IC 74H21

19-09343

IC LM 302

19-09004

IC 7402

19-09686

IC 7404

1905575

IC 7400

19-94961

IC M6 1439

19-05547

IC 7474

1909935

IC 8235

D664

Diode D664

19-09971

IC 6380

IN 825

Diode |N825

19-10018

IC 74193

IN 752A

Diode IN752A

19-09928

IC 7416

FD 777

Diode FD777

19-09705

IC 8881

IN 571

Diode IN571

19-09704

IC 314

Table 6-3

Analog Preamplifier and Multiplexer Expander
(AM8-EA) Recommended Spare Parts

121921;":ch

DEC Part Number

Description

1 105508

Diode IN823

11-02451

Diode IN753

19-09686

IC 7404

1909594

IC 8251

1909344

IC MC 17090

15-09233

Transistor 2N5163

15—09142

Transistor 2N 425

15-03409-01

Transistor 6534-B

15-03100

Transistor 3009B

Table 6-4
Buffered Digital I/O (DR8-EA) Recommended Spare Parts
DEC Part

Number

Recommended

11-00114

DEC Part

Number

Recommended

Diode D664

19-09594

IC 8251

Description

11-04860

Diode IN746A

19-09704

IC 7404

1905547

IC 7474

1909705

IC 8881

19-05575

IC 7400

19-09928

IC 7416

19-09004

I C 7402

1909935

IC 7405

19-09485

IC 380

19006735

IC 8235

Table 6—5
Real-Time Programmable Clock

(DK8-EP) Recommended Spare Parts
DEC Part

Number

Recommended

18-09880

Description
20 MHz crystal

15-09142

Transistor 2N4250

15-03100

Transistor DEC 3009B

150909001

Transistor DEC 6B

11-00114

Diode D664

11-02808

Diode iN752A

19-09485

IC 380

1909686

IC 7404

19-09705

IC 8881

19-09936

IC 74151

1909929

IC 7417

19-05575

IC 7400

19-05547

IC 7474

19-09004

IC 7402

19-09051

IC 7475

19-05589

IC 7470

19-09344

IC 1709C

19-09436

IC 384

19-09373

IC 9601

19-05579

IC 7440

19-05577

IC 7420

1905576

IC 7410

19-10035

1C 74197

19-09594

IC 8251

19-09972

IC 6314

19-09971

IC 6380

19—09934

IC 8266

6-3

APPENDIX A

IC CIRCUIT DESCRIPTIONS

Only those integrated circuits used in the LAB-8/ E which are not discussed in the PDP-8/E Maintenance Manual
will be covered in this appendix.

A.1

SN 74193 IC

The SN 74193 monolithic circuit is a synchronous, reversible (up/down), 4-bit binary counter having a complexity

of 55 equivalent gates.

Synchronous operation is provided by having all flip-flops clocked simultaneously so that

the outputs change coincidently with each other when so instructed by the steering logic. This mode of operation
eliminates the output counting spikes which are normally associated with asynchronous (ripple-clock) counters.

See Figure A-1 for the logic diagram and Figure A-2 for the pin location.
The outputs of the four master/slave flip-flops are triggered by a low-to-high level transition of either count (clock)

input. The direction of counting is determined by which count input is pulsed while the other count input is high.
The counter is fully programmable; i.e., the outputs may be preset to any state by entering the desired data at the

data inputs while the load input is low. The output will change to agree with the data inputs, independently of
the count pulses. This feature allows the counters to be used as Modulo-N Dividers by simply modifying the count

length with the preset inputs.
A CLEAR input has been provided which forces all outputs to the low level when a high level is applied. The

CLEAR function is independent of the count and load inputs. An Input Buffer has been placed on the CLEAR,

COUNT, and LOAD inputs to lower the drive requirements to one normalized load. -This is important when the
output of the driving circuitry is somewhat limited.
This counter was designed to be cascaded without the need for external circuitry. Both BOR ROW and CAR RY

outputs are available to cascade both the up- and down-counting functions. The BORROW output produces a

pulse equal in width to the COUNT-DOWN input when the counter underflows. Similarly, the CAR RY output

produces a pulse equal in width to the COUNT UP input when an overflow condition exists, The counters can
then be easily cascaded by feeding the BORROW and CARRY outputs to the COUNT-DOWN and COUNT-UP

inputs, respectively, of the succeeding counter.
NOTE

Voltage values are with respect to network ground
terminal.

A.2

DEC 1709C IC

The DEC 1709C IC is an operational Amplifier. The circuit schematic and the pin locator are shown in Figure

A-3.

BORROW
OUTPUT

CARRY
OUTPUT

DATA
INPUT A

PRESET
DOWN
COUNT

OUTPUT

UP
COUNT

DATA
INPUT 8

PRESET

Q B

OUTPUT 03

DATA
INPUT

PRESET

OUTPUT

00
CLEAR

DATA
INPUT D

CLEAR
PRESET

5b
CLEAR

LOAD

8E-0227

Figure A-1

74193 IC Logic Diagram

A-2

Sinle

$1.0le

W—’
ViVG

A 33

k—v—J

smdmo

ava‘xo

\—w_/

moauoa

mum

ovm

AHHVD
BVEWO
M08808
OVOW

VLVO

VLVG
a

l
VLVO
9
1.0le

iNflOOiNnOO
°9
NMOG
cm

anoo .LNOOO
nmoo
an

Clo

ONE)

F—H fl r—“fi
Sindmo

M01=3I90fi

smdmo

smam

LfldN1 01 ovow $133

0Nv‘3=°o‘e=90'v=vo 0:00
9920'38

amfiaa z-v

cam on um uoueorn don (Mam

A+

inle 9V1
4

v vAA

vvA A

AONBOOEEd
NouVSdeoa

indi“°

"*”'
...

9NLLHEANl-NON
+indM

SNLLHBANI
.A-inle

AV,

Ava

indan
9V1

v vA A
p

dOL M3|A

LONEHOBHA
NOUVSNEdWOD

Lfile

ouuuaANI
Lnle

9V1

/\+

annuaANI-NON

indino

Lnle

indlno 9V1

A-

CLEO-38

31"5!:| S'V

330 360“ OI suogleJlsn|||

S'V

The IC is designed for general purpose analog amplifier application.

In the Real-Time Programmable Clock option,

DK8-EP, the 1709C is used as a comparator and, as such, is the central component in the Schmitt trigger circuits
on the M518 module.

In this application, only half the IC circuitry is used, the output being taken from pin 8 of

the IQ As can be seen from the circuit schematic, the output at pin 8 has the same relationship to the summing

inputs as does the output at pin 6.
A.3

DEC 7475 IC

The DEC 7475 IC is a 4-bit bi-stable latch. The logic diagrams, a truth table, and a pin locator are shown in Figure

A-4.

Information present at the data input (D) of a latch is transferred to the 1 output when the clock input (C) goes

high. If the C input remains high, the 1 output follows‘the D input. When the C input goes low, the 1 output
holds the state it was in prior to the transition.

A.4

DEC 7490 IC

The DEC 7490 IC is a high-speed counter consisting of four master/slave flip-flops, connected to provide a divide-

by-2 counter and a divide-by~5 counter. The logic diagram, truth tables, and a pin locator are shown in Figure
A-5.
The 7490 can be used in three independent counting modes:

divide-by-2/divide-by-5 mode, a divide-by-10 mode,

and a BCD-count mode. External interconnections of the IC pins are not necessary in the first mode. An input at

pin 14 is divided by 2 by flip-flop A and the result is taken from pin 12; an input at pin 1 is divided by 5 by flipflops B, C, and D, and the result is taken from pin 11. The output of each flip-flop is made available and all four

flip-flops are reset simultaneously, if the gated reset lines are used.
If the divide-by-10 mode is desired, pin 11 must be connected to pin 14. The input at pin 1 is divided by 10 and
the output is taken from pin 12. (This mode of operation is used in the Real-Time Programmable Clock option.)
The third mode is obtained by connecting pin 1 to pin 12 and applying the input at pin 14; the BCD-count sequence is shown in Truth Table A. The reset inputs are provided to reset a BCD count for 9’s complement decimal

applications.
A.5

DEC 7470 IC

The DEC 7470 IC is an edge-triggered J-K flip-flop. The logic diagram, pin locator, and the truth table are shown
in Figure A-6.
The 7470 features gatéd inputs and direct CLEAR and PRESET inputs.

lnput information is transferred to the

outputs on the positive edge of the clock pulse. Direct-coupled clock triggering occurs at a specific voltage level
of the clock pulse; when the input threshold has been exceeded, the gated inputs are locked out. The PRESET
and CLEAR inputs have effect only when the clock input is low.

A.6

DEC 74197 IC

The DEC 74197 IC is a presettable binary counter that can also be used as a latch. The IC consists of four dc-

coupled master/slave flip-flops connected to provide a divide-by-2 counter and a divide-by-8 counter. The logic
diagram, truth table, and pin locator are shown in Figure A7.
The 74197 can be used in any one of three modes: the divide-by-2/divide—by-8 mode (requiring no external inter-

connection of IC pins), the latch mode, and the binary counter mode. If the first mode is used, an input at pin 8
is divided by 2 by flip-flop A and the result is taken from pin 5; an input at pin 6 is divided by 8 by flip-flops B, C,

A-4

and D and the result is taken from pin 12. Transfer of information to the outputs takes place on the negative-

going (trailing) edge of the clock pulse.
If one wishes to use the latch mode, one must enter data at the four data inputs (pins 4, 10, 3 and 11) and enter
a strobe

pulse at pin 1. The output pins 5, 9, 2, and 12, respectively, will follow the inputs when pin 11 is low,

but will remain unchanged when pin 1 is high and the clock inputs are inactive.

The binary counter mode is used in the Real-Time Programmable Clock option. Pin 5 must be externally con—
nected to pin 6. The clock input is applied at pin 8. The initial count can be preset to any value by placing a low
on

pin 1 and entering the data on pins 4, 10, 3, and 11. When pin 13 is taken low, all outputs are set low, regard-

less of the state of the clock inputs.

A-5

NOTE: tn

t(n+ 1)

High

Low

bit time before C—input transition

t(n+1)

bit time after C-input transition

0,—
_.()

r— o

\\\44,
b
D

J—LI—illl

BiT1,0‘OUTPUT

\J BIT 1.1-OUTPUT

BIT 1, D-OUTPUT

BIT 2,1-OUTPUT

BIT 2,D-|NPUT

snap—ourpur

BiTS 3,4.C-INPUT

BiTS 1.2,C-INPUT

GND

VCC

BITS 3,D-|NPUT

BIT 3.0-0UTPUT

BIT 4,D-|NPUT

BIT 3,1-OUTPUT

BiT 4,0-OUTPUT

BiT 4,1—OUTPUT

8E-0369

Figure A-4 DEC 7475 IC Illustrations

BCD-Count Sequence

RESET/COUNT

Output

Reset Inputs

Output

Count

R011)

R012)

R9”,

R912)

DCBA

0000

1001

COUNT

NOTE:

X in table indicates either 1 or0 may be

present.

INPUT
*

A
14

GND

wcp

1
80

INPUT

*NC

2
R

0(1)

—————0 CP

0(2)

VCC

9(1)

R 9(2)
SE- 0374

No internal connections.

Figure A-5

DEC 7490 IC Illustrations

A-7

_|—|O<._
NOTES:

1
0
1

Bit time before Clock pulse

tn+1

J=J1 -J2 ~J3
K=K1 ~K2 K3

CLEAR

—-q

Bit time after clock pulse

i__

o”—

0
o— PRESET

CLOCK

E‘vcc

*NCE
CLEAR

passer

CLOCK

.12

JSE

Pam

5E
GND

*NC

Elia
30

No Connection
aE~037i

Figure A-6 DEC 7470 IC Illustrations

A-8

Count

Output

Clock 1 Input

0A
0

NOTE:

fiJ

COUNT/LOAD

Vcc

CLEAR

DATA C

DATA A

DATA D

DATA

CLOCK 2

GND

CLOCK 1

85‘0“?

0A connected to Clock 2 input.

DATA A
COUNT/LOAD

CLEAR ———<

CLOCK 1——T

___| >
DATA

H}
CLOCK

DATA C

2—fiT

:3
L—T

DATA D

-—T

8E-0273

Figure A-7

DEC 74197 IC Illustrations

A-9

APPENDIX B

LAB-8/E MODULE JUMPER REQUIREMENTS

Option

Module

Jumper

AD8~EA

A231

Function

Normally installed during system operation. W1 can be
removed for troubleshooting if PR ESET L is always low
or

ground.

Normally installed during system operation. W2 can be
removed for troubleshooting to remove DATA OUT H
from the comparator circuit. Removal of this jumper
disables the A/D converter to allow a bad chip in the
A/D Buffer to be located.

Normally installed during system operation. W3 can be
removed for troubleshooting to break the CLEAR L line
to the MUX Register flip-flops.

Used to isolate bad

CLEAR inputs to these chips.
w4

Normally installed during system operation. W4 can be
removed for troubleshooting to break the CLEAR L line
to the Enable Register between E20 and E24.

W4 is re-

moved to isolate CLEAR inputs on the Enable Register.

Normally installed during system operation. W5 can be
removed to break the BUSY H line to the clock and

preset circuits. W5 is removed for module automatic

testing only.
A841

W1 is installed to make the analog input differential. Do
not install W1 if an AM8—EA (A232) is installed.

On Etch

Revision C and below, input pin NN on the Berg cpnnector must be tied to pin MM

(ground) when W1 is re-

moved.

On Etch Revision D and above, W2 will be installed when
W1 is
removed.

AM8-EA

A232

W1 selects the module as channels 08 through 78. W2
must not be installed (on Etch Revision D or higher).

W2 selects the module as channels
must not be installed (on Etch

VC8-E

M869

108 through 178. W1

Revision D or higher).

Installed to select device code (IOT) 05. W2 must be removed.

Installed to select device code (IOT) 15. W1 must be removed.

(continued on next page)

3-1

Option

Module

Jumper

M885

Function
Installed when the RM503 oscilloscope is used to increase
the Z-output voltage.

Thejumper adjacent to AB must

be cut when the AB jumper is installed.

DK8-EP

DR8—EA

Used only in special test.

M518

None

M860

None

M863

through

0A through 1 1 A select a flip-flop as an edge—detecting

input buffer for individual bits 0 through 11.

11A
OB

through

OB through 11B select a direct input (for level-type signal

inputs) for individual bits 0 through 11.

Either an A or

11B

B jumper must be installed in each bit position.

W1 through W12 allow individual bits to generate an in-

through
W12

terrupt when they are set. Inputs must be present in the
direct mode (B jumpers) long enough to avoid an un-

identified interrupt.
H6A and H63

through
H8A and H83

Thesejumpers are used to select the device code ( lOT).
The A jumpers select 0's and B jumpers select 1's when
they are installed.

B-2

LAB-8/E MAINTENANCE MANUAL
DEC-LB-H8EMM-B-D

READER’S COMMENTS

Digital Equipment Corporation maintains a continuous effort to improve the quality and usefulness of its publications. To do this effectively we need user feedback
your critical evaluation of this manual.
—

Please comment on this manual’s completeness, accuracy, organization, usability, and readability.

Did you find errors in this manual?

How can this manual be improved?

DEC also strives to keep its customers informed of current DEC software and publications. Thus, the following

periodically distributed publications are available upon request. Please check the appropriate boxes for a current
issue of the publication(s) desired.

Cl Software Manual Update, a quarterly collection of revisions to current software manuals.
El User’s Bookshelf, a bibliography of current software manuals.
C] Program Library Price List, a list of currently available software programs and manuals.

Please describe your position.

Name

Organization

Street

Department

City

State

Zip or Country

——

—

—-—-

-—

——

———-

—

--——

DoNotTear-FoldHereandStaple

—

——

—

——

—

——

FIRST CLASS
PERMIT NO. 33

MAYNARD, MASS.

BUSINESS REPLY MAIL
N0 POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES

Postage will be paid by:

Digital Equipment Corporation
Technical Documentation Department
146 Main Street

Maynard, Massachusetts 01754