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DEC-8L-HR1B-D

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Document:	PDP-8/L Maintenance Manual Volume 1
Order Number:	DEC-8L-HR1B-D
Revision:	000
Pages:	82
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/dec-8l-hr1/dec-8l-hr1b-d.pdf

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DEC-8/L-HR1B-D

PDP-8/L

MAINTENANCE MANUAL

VOLUME

DIGITAL

EQUIPMENT

CORPORATION

•

MAYNARD, MASSACHUSETTS

\st

Printing October 1968

2ncl Printing

May 1969

3rd Printing (Rev) December 1969
4th Printing July 1970

The material in this manual is for information purposes and is subject to change with-

out notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDF

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

CONTENTS
Page

CHAPTER

INTRODUCTION AND DESCRIPTION
1.1

IntroducHon

1-1

1.2

Description

1-1

1.3

Pertinent Documents

1-1

CHAPTER 2
INSTALLATION
2.1

Space Requirements

2-1

2.2

Environmental Requirements

2-3

2.3

Internal Option Installation

2-3

2.4

Interface

2-3

2.4.1

I/O Bus

2-3

2.4.2

I/O Cables

2-4

2.4.3

Cable Connectors

2-4

2.5

Interface Connections

2-4

2.6

External Equipment Cable Locations

2-5

2.7

Bus DriverAeceiver Modules

2-5

2.7.1

Mil 1/M906 Positive Input Circuit

2-5

2.7.2

M516 Positive Bus Receiver Input Circuit

2-6

2.7.3

M623/M906 Positive Output Circuit

2-7

2.7.4

M660 Bus Driver Output Circuit

2-7

CHAPTER 3

OPERATION
3.1

Controls and Indicators

3-1

3.1.1

Computer

3-1

3.1.2

Teletype

3-4

3.2

Operating Procedures

3-4

3.2.1

Manual Loading Procedures

3-4

3.2.2

Teletype Loading Procedures

3-5

3.2.3

Off-Line Teletype Procedure

3-6

CONTENTS (Cont)
Page

CHAPTER 4

THEORY
Section I:

4.1

Block Diagram Discussion
Registers

4-1

4.1.1

Accumulator (AC)

4-1

4.1.2

Link (L)

4-1

4.1.3

Program Counter (PC)

4-1

4.1.4

Memory Address Register (MA)

4-1

4.1.5

Memory Buffer Register (MB)

4-1

4.1.6

Sense Register (Sense)

4-1

4.1.7

Instruction Register (IR)

4-1

4.1.8

Switch Register (SR)

4-1

4.2

Major Register Gating Network

4-1

4.3

Timing and Control Elements

4-3

4.3.1

Timing Elements

4-3

4.3.2

Control Elements

4-3

4.4

Input/Output

4-3

4.5

Memory

4-3

4.5.1

Core Array

4-3

4.5.2

Memory Control

4-3

4.5.3

Address Selection

4-3

4.5.4

Inhibit Drivers

4-4

4.5.5

Sense Amplifiers

4-4

Section II:

General Theory

4.6

Time States/Time Pulses

4-4

4.7

Major States

4-4

4.8

Internal Data Flow

4-4

4.9

Instructions

4-4

4.9.1

Memory Reference Instructions

4-5

4.9.2

Augmented Instructions

4-6

4.10
4.10.1

Program Interrupt
Instructions

4-11
4-11

CONTENTS (Cont)
Page
Section III:

Detailed Memory Theory

4.11

Overall Memory Theory

4-11

4.12

Memory Operation

4-12

4.12.1

Memory Control

4-12

4.12.2

Read/Write

4-12

4.12.3

Address Selection

4-16

Section IV:

4.13

Detailed Processor Theory

Timing

4-19

4.13.1

Manual Function Timing Generator

4-19

4.13.2

Manual Operations

4-19

4.13.3

Time States

4-21

4.14

I/O Timing

4-21

4.15

Memory Protect

4-24

4.16

Major States

4-25

4.17

Internal Data Flow

4-26

4.17.1

Source

4-27

4.17.2

Route

4-27

4.17.3

Destination

4-27

4.18

Operating Instructions

4-28

4.18.1

Instructions

4-29

4.18.2

Memory Reference Instructions

4-29

4.18.3

Direct/Indirect Addressing

4-34

4.18.4

Augmented Instructions

4-35

CHAPTER 5

MAINTENANCE
5.1

Equipment

5-1

5.2

Programs

5-2

5.3

Preventive Maintenance

5-3

5.3.1

Weekly Checks

5-3

5.3.2

Preventive Maintenance Tasks

5-3

5.4

Corrective Maintenance

5-3

5.4.1

Preliminary Investigation

5-4

5.4.2

System Troubleshooting

5-4

CONTENTS (ConO
Page

5.4.3

Logic TroubleshooHng

5-5

5.4.4

Circuit Troubleshooting

5-5

5.4.5

Repairs and Replacement

5-6

5.4.6

Validation Tests

5-6

5.4.7

Recording

5-7

5.5

5-7

Adjustments

5.5.1

Power-Up Threshold Adjustment

5-1

5.5.2

Memory Alignment Procedure

5-7

5.6

ASR33 Teleprinter and Control Maintenance

5-11

5.6.1

Equipment

5-11

5.6.2

Programs

5-12

5.6.3

Preventive Maintenance

5-12

5.6.4

Corrective Maintenance

5-15

ILLUSTRATIONS
1-1

PDP-8A

2-1

Table Top PDP-8A Dimensions

2-1

2-2

Rack-Mounted PDP-8/L

2-2

2-3

Chassis-Track Specifications

2-2

2-4

Rack-Mounted PDP-8/L Frame with Track -Slide Specifications

2-3

2-5

I/O Bus Configuration

2-4

2-6

I/O Signal Connections

2-5

2-7

Cable Location Convention on Option Mounting Panels

2-6

2-8

Ml 1/M906 Logic Diagram

2-6

2-9

Typical M516 Positive Bus Receiver Input Circuit

2-6

2-10

Typical M623/M906 Positive Output Circuit

2-7

2-11

Typical M660 Bus Driver Output Circuit

2-7

3-1

PDP-8/L Front Panel

3-1

3-2

Teletype Model ASR33 Console

3-3

4-1

System Block Diagram

4-2

Memory Reference Instruction Bit Reference

4-5

4-3

lOT Instruction Bit Assignments

4-6

4-4

Group 1 Operate Instruction Bit Assignments

4-7

ILLUSTRATIONS (Cont)
Page

4-5

Group 2 Operate Instruction Bit Assignments

4-9

4-6

Memory System, Block Diagram

4-13

4-7

Memory Timing Diagram

4-14

4-8

Simple Core Memory Plane

4-15

4-9

Memory Address Selector or Read/Write Current Control

4-17

4-10

Manual Function Timing Diagram

4-18

4-11

System Timing Diagram

4-22

4-12

I/O Timing Diagram

4-23

4-13

Data Flow

4-28

4-14

Direct and Indirect Address Selection, Simplified Flow Chart

4-36

5-1

IC Location

5-6

5-2

IC Pin Location

5-6

5-3

Memory Control Waveforms

5-9

5-4

Representative Read/Write Current Waveforms

5-10

5-5

Representative Inhibit Current Waveforms

5-12

5-6

Representative Sense Amplifier Waveforms

5-14

5-7

Teletype Connections

5-16

5-8

Teletype Signal Waveform and Bit Relationship for the Character "U"

5-17

TABLES
3-1

Computer Controls and Indicators

3-1

3-2

Teletype Controls and Indicators

3-4

3-3

Readin Mode Loader Program

3-5

4-1

Example of Register Contents During JMS Instruction

4-33

5-1

Maintenance Equipment

5-1

5-2

Maintenance Programs

5-2

5-3

Power Supply Specifications

5-4

Teletype Maintenance Tools

5-13

5-5

Teleprinter Maintenance Programs

5-13

VII

PDP-8/L MAINTENANCE MANUAL

VOLUME

Figure 1-1

PDP-8/L

CHAPTER 1
INTRODUCTION AND DESCRIPTION

1.1

INTRODUCTION

quotient in the accumulator, and a 12-bit remainder
in

core memory

This manual covers installation, operation, theory,

and maintenance of The Programmed Data Processor 8/L (PDP-8/L). It is the intent of this manual to
provide the field service engineer or maintenance
technician who is familiar with digital logic circuitry
with the information he needs to install and maintain
a PDP-8/L system. The bulk of the manual assumes
that the reader is conversant with DIGITAL'S system
of logic notation. If this is not the case, the reader
should refer to applicable sections in the appendix

Flexible, high-capacity, input/output capabilities of
the computer allow

to operate a variety of periph-

reader, line printer, analog-to-digital converters,

cathode-ray-tube displays, magnetic-drum systems,
magnetic disk-file systems, and magnetic-tape equipment. Instruments or equipment of special design can
also be connected into the PDP-8/L system. The
computer itself needs no modification for the addition

for a description.

1.2

equipment. In addition to the Teletype keyboard/printer and perforated-tape reader/punch
equipment supplied with a basic PDP-8/L, the system
can operate a number of optional devices, such as a
high-speed perforated-tape reader and punch, card
eral

DESCRIPTION

of these peripheral devices.

The Digital Equipment Corporation integrated-circuit
Programmed Data Processor-8/L (PDP-8/L) (see Frontispiece) serves as a small-scalegeneral-purposecomputer that functions as an independent informationhandling facility in a large computer system, or as
the control element in a complex processing system.

The PDP-8/L is completely self-contained, and, under
normal conditions, requires neither special power
sources nor rigidly controlled environmental conditions.

A single source of 105-130 Vac, 47-63-Hz,

single-phase power permits internal power supplies to

produce all required operating voltages. M- Series*
modules, using TTL-type integrated-circuit packs,
ensure reliable operation in ambient temperatures between +10° and +55 X.

The PDP-8/L is a one-address, 12-bit, fixed-wordlength, parallel computer using two's complement
arithmetic. Normal cycle time of the 4096-word
(referred to as 4K) random-access, magnetic core

memory is 1.6 ^. An additional 4K of memory may
be available to the system simply by adding an MC

1.3

PERTINENT DOCUMENTS

8/L memory expansion and control unit.
The following documents serve as source material and
Standard features of the system include indirect ad-

complement the information in this manual:

dressing, facilities for instruction skipping and pro-

gram interruption as functions of input/output device
conditions, and optional high-speed information
transfers into peripheral mass memory devices via a

1
Logic Handbook, C-105 (1969 edition) printed
by DIGITAL, which notes the function and specifications of the M-Series modules and module ac-

cycle stealing data break.

cessories for the

The PDP-8/L performs one addition in 3.2 |js (with
one number in the accumulator), permitting a compu-

tation rate of 312,500 additions per second to be

Technical Manual, Automatic Send and Receive Sets (ASR) (Bulletin 273B Volumes
and 2).
This manual covers operation and maintenance of
the Teletype unit.

PDP-8/L.

PDP-8/L Users Handbook.

achieved. It performs subtraction in 6.4
(with
the minuend in the accumulator) using two's complement addition. Multiplication takes approximately
384 |js, using a subroutine that operates on two signed
12-bit numbers to produce a 24-bit product, leaving
the 12 most significant bits in the accumulator. Division of two signed 12-bit numbers takes approximately
490 ps, using a subroutine that produces a 12-bit
|jts

*M Series is a registered trademark of Digital Equipment Corporation.

1-1

Model 33 Page Printer Set (Bulletin
1184B) contains an illustrated parts breakdown to
serve as a guide to disassembly, reassembly, and
4.

Parts,

Instruction manuals and MAINDEC programs

for appropriate input/output devices are

prepared

by DIGITAL.

ordering replacement parts for the Teletype unit.

Digital Program Library Documents.

Perfo-

rated program tapes and descriptive matter for the

Program Assembler Language (PAL III), FORTRAN,
FOCAL, utility subroutines, and the maintenance
programs (MAINDEC) prepared by DIGITAL are
available to PDP-8/L users. The list of programs
currently in the library and available is provided

DIGITAL.
This is a shirt-pocket list of all memory reference
instructions, all augmented instructions, the most
common lOT instructions, and the ASCII code used
with many I/O devices.
5.

Instruction List F-816, printed by

1-2

Appendix D.

CHAPTER 2
INSTALLATION

This chapter contains installation and interface infor-

18-1/4 in. deep. The teletype signal cable requires
the teletype to be placed near the computer.
Figures 2-1 through 2-4 provide PDP-S/l dimensions

mation for the PDP-8/L and its options.
2.1

SPACE REQUIREMENTS

for both tape top and rack-mounted configurations.

If DEC cabinets are not purchased, the cabinets at
the instal lotion should provide for access to all doors

Figure 2-1 illustrates the table top dimensions, and
Figure 2-2 illustrates the rack-mounted PDP-8/L.

and panels for maintenance.

The rack-mounted configuration is attached to the
cabinet on sliding chassis tracks. There are two sets
of tracks; one set for each frame side
The track sections interlock; one section being bolted to the cabinet and the other bolted to the logic main frame.

The PDP-8/L is available in either the table top or
rack-mounted configuration. The rack-mounted con-

figuration and peripherals may be purchased com-

pletely installed in

DEC cabinets or unmounted for

installation in a customer cabinet.

The standard
teletype automatic send receive (ASR) set requires a

Figure 2-3 shows the chassis track specifications. A
rear view of the rack-mounted PDP-S/L and track-

floor space of approximately 22-1/4 in.

slide specifications is illustrated in Figure 2-4.

wide by

Figure 2-1

Table top PDP-8/L Dimensions

2-1

Figure 2-2

Rack-Mounted PDP-8/L

AUTOMATIC LOCK OUT

QUICK DISCONNECT
RAISE MANUAL RELEASE ARM
TO REMOVE OR RETURN CHASSIS

AUTOMATIC CHANNEL STOP

BASIC CABINET

^' CHASSIS"^

i^
li_

2 45/64

OF MOUNTING HOLES

OF SLIDE
TtOF
(I

FROM

TOP OF CHASSIS

5/32"
21

7/8"

SIDE VIEW OF
MOUNTING HARDWARE

Figure 2-3

Chassis-Track Specifications

2-2

REAR VIEW OF
MOUNTING HARDWARE

Hh
I

1/4

"tOF SLIDE

Figure 2-4

2.2

Rack- Mounted PDP-8/L Frame with
Track-Slide Specifications

ENVIRONMENTAL REQUIREMENTS

module of all internal
an option involves an external device,
dress connecting cables through the opening at the
ing for the locations of each

options.

5-0

The PDP-8/L is designed to operate between 32° and
130° F (0°and 55° C). The life-expectancy of the
system, however, can be extended

rear of the

PDP-8/L to the option.

the temperature

is maintained at between 70°
and 85° F (between 21 ° and 30° C).

at the installation site

2.4 INTERFACE
During shipping or storing of the system, the ambient
temperature should be maintained within 32° to
130° F to prevent damage to the system. Although
all

exposed surfaces of Digital cabinets and hardware
are treated to prevent corrosion, exposure of systems

2.4.1

to extreme humidity for long periods of time should
be avoided.

The PDP-8/L uses a series l/O bus system to permit
interface connections to be made between external
devices and the 8/L without modifying the computer

wiring.

In a series I/O bus, the computer sends all
I/O signals to the first device. This device uses the
pertinent signals and sends all of the signals to the
next I/O device (see Figure 2-5). This allows one set
of cables to be connected to the PDP-8/L and two
sets connected to each device: one receiving the
I/O bus signals from the computer itself or the previous device, and one passing the l/O bus signals to

For external options, forced air cooling should be used

more than a few module-filled H911 mounting panels are needed. The low power consumption of Mseries modules results in approximately 15W dissipation
in a typical H911 mounting panel of 64 modules.
If
only one or two panels of logic are used, convection
if

cooling is sufficient.

2.3

I/O Bus

the next device.

INTERNAL OPTION INSTALLATION

The data break cables are used in

the same manner.

The installation of the internal options involves the
addition of the logic modules in the proper locations.

When the equipment location does not make series bus

WHEN INSERTING OR REMOVING ANY MODULES

connections feasible, or when cable length becomes
excessive, additional interface connectors can be
provided near the computer.

IN THE LOGIC FRAME THE 8/L SYSTEM MUST BE
TURNED-OFF. Refer to the module utilization draw-

2-3

DEVICE
2
(2)

®-® ^

10 CABLES

10 CABLES TO
'ADDITIONAL DEVICES
'

DATA BREAK

DATA

BREAK CABLES

DATA BREAK CABLES
TO ADDITIONAL DEVICES

CABLES

Figure 2-5

2.4.2

I/O Bus Configuration

are used with flexprint cable.

I/O Cables

The M904 connectors

terminate the coaxial coble ends.

Eighteen conductor coaxial cables or flexprint cables
with either M904 or M903 coble connectors, respectively, provide signal connection between the computer and optional equipment. These cables are connected by plugging the connectors into standard FLIP
CHIP module receptacles. Use of coaxial cable pro-

Both connectors are wired double-sided with 36 pin
Each connector terminates two coaxial or

contacts.

flexprint cables.

The conductors from both types of

cables terminate at the connector pin locations indicated below. Each signal conductor is isolated by a

The connector pin locations for

tects systems from radiated noise and cross talk be-

ground conductor.

tween individual lines. Coaxial cable used between
the PDP-8/L and options has the following specifica-

Dl, El, HI, Jl, LI, Ml, Pi, SI,
and D2, E2, H2, K2, M2, P2, S2, T2, V2. The
ground pin locations on each connector are: Al , CI
Fl, Kl, Nl, Rl, Tl, and C2, F2, J2, L2, N2, R2,
U2.
signals are:

tions:

Zq = 95Q ±5%

Bl ,

= 13.75 pf/ft approximately (unterminated)

= 124 Nhy/ft approximately

= 0.095 ohm per foot nominal

assigned module receptacle connectors in the mounting
frame. Capitol letters designate horizontal rows of

= 79% of velocity of light, approximately

modules within a mounting frame from top to bottom,
i.e., A is the first row, B is the second row, etc.
Module receptacles are numbered from left to right as
viewed from the wiring side (right to left from the
module side). Terminals of a connector or module are
assigned capital letters from top to bottom omitting
G, I, O, and Q. Double sided connectors or mod-

2.5

INTERFACE CONNECTIONS

All interface connections to the PDP-8/L are made at

(=;

1.5ns/ft.).

The flexprint cable is generally used because of its
flat
high flexibility. The conductors ore '*'30
copper

AWG

The maximum length of I/O cabling, from the PDP8/L to the last device is 50 ft. This can be 50 ft. of
coax or a combination of coax and flexprint, in which
case the flexprint cannot exceed a total length of

ules are used with the suffix number "1" designating

the one side and suffix number "2" designating the
other side.

15 ft.
Figure 2-6 shows the signals and pin locations at each
connector block. The I/O cable connectors are inserted into these locations to form the I/O bus. The

2.4.3 Cable Connectors

arrows associated with each signal show the signal
The arrows pointing to the connectorblock

The M903 and M904 cable connectors are used with
the coble types described above. M903 connectors

direction.

2-4

DATA ADD 08
DATA ADD 01
DATA ADD 02

DATA ee
DATA ei
DATA 82
DATA 03
DATA e^l
DATA 85
DATA 86
DATA 07
DATA 88
DATA 09
DATA 10
DATA 11

DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA

EAIA^,

3 CYCLE

CA INCREMENT

DATA IN

BWC OVERFLOW
EXT DATA ADD

B ADD ACCEPTED (1)

^UNUSED

ME MORY INCR EMENT

BMB00 (I)

BAC00
BAC01
BAC02
BAC03
BAC04

BMB0I II)

BMB02 (I)
BMB03 (0)
BMB03(ll
BMB04(0)
BMB04(I)
BMB05(0)
» BMBe5(l)
BMB06(e)
BMB06(I)
BMB07(0)
BMB07II)
BMB08(0)
BMB08(I)
BMB09(I)

I/O SKIP
INT RQST

AC CLEAR
B

B BREAK (01

B INITIALIZE

INPUT BUS 00
INPUT BUS 01
INPUT BUS 02
INPUT BUS 03
INPUT BUS 04
INPUT BUS 05
INPUT BUS 06
INPUT BUS 07
INPUT BUS 08
INPUT BUS 09
INPUT BUS 10
NPUT BUS
I

RUN (0)

BAC05
BAC06
BAC07
BAC08
8AC09

• BAC

Figure 2-6

indicate signals coming to the computer from tiie

BACH
BI0P1

BI0P2
8I0P4
BTS 3 (I)

BMBI0 (I)
BMB
(I)

bus.

ADD 03
ADD 04
ADD 05
ADD 06
ADD 07
ADD "06
ADD "g9
ADD 10

BTS 1(1)
*• B

INITIALIZE

I/O Signal ConnecHons

I/O

option mounting panel are wired in parallel with the

Similarly, the arrows pointing away from the

top module slot locations 1 through 5.

To continue

connector block indicate signals from the computer to

the I/O cabling to the next device, the bottom slots

external devices through the l/O bus.

are used.

2.6

EXTERNAL EQUIPMENT CABLE LOCATIONS

2,7 BUS DRIVE IVRECEIVER MODULES

The I/O cables connected within the computer at the
locations specified by Figure 2-6 are generally connected on an option mounting panel as indicated in
Figure 2-7. This illustration shows the DEC convention for cable terminations.

The following paragraphs describe each bus driver
and receiver module type shown on Engineering
Drawing BS-8L-&-10. These circuits provide isolation and drive for signals between the processor and

l/O cables.

Module slot locations 1 through 3 (looking at the
wiring pin side) in the A row of an option mounting

panel are reserved for program interrupt cable connections in (or out).

2.7.1

Min/M906

Positive Input Circuit

Module slot locations 4 and 5
Figure 2-8 shows the M111/M906 logic configuration.
The Ml 11 Inverter module is used in conjunction with
the M906 Cable Terminator module which clamps the
Input to prevent excursions beyond +3V and ground.

are reserved for Data Break cable connections In
(or out).

Module slot locations I through 5 in the B row of the

2-5

^f
DATAOO

BACOO

BMBOO

ACOO BUS

DATA ADDOO

BAcn

BMBll

AC 11 BUS

DATA ADD 11

DATA 11

BIOP 1, 2, 4

SKIP BUS

BRK RQST

3 CYCLE

BTS 3,

INT RQST BUS

DATA IN

CA INCREMENT

AC CLEAR

MB INCREMENT

EXT DATA ADD

B INITIALIZE

CONT BUS
B

ADD

OVERFLOW

ACCEPTED

B RUN

BREAK

B INITIALIZE

-^ f

SAME ASSIGNMENTS AS ABOVE
-!

S-

Figure 2-7 Cable Location Convention on Option Mounting Panels

The incoming DATA and DATA ADD signals for data
break and other signals (Drawing BS-8L-0-10) are

2.7.2

inverted and isolated from the I/O cables through

Figure 2-9 shows the M516 logic configuration. Six
gates with overshoot and undershoot
four-input

NAND

this logic.

M516 Positive Bus Receiver Input Circuit

Bl p

OUTPUT SIGNAL TO PROCESSOR

9 OUTPUT SIGNAL TO PROCESSOR

(

M It
I

U5I6
GATES

SI X

)

S INVERTERTS)

?TO
n

r
-V^

INTERNALLY
-O Bl

+5V

-V^

M906
(ta

CIRCU ITS)

BIO POSITIVE BUS INPUT SIGNAL
(FROM EXTERNAL DEVICE)

6 POSITIVE BUS INPUT SIGNAL

(FROM EXTERNAL DEVICE)

Figure 2-9

Figure 2-8

+5V

Mil 1/M906 Logic Diagram

Typical M516 Positive Bus Receiver
Input Circuit

2-6

clamp on one input of each gate. The I/O SKIP gate
(Drawing BS-8L-0-10) is an example of M516 application. The input signals applied to pins Bl, CI,
and Dl are from intern al options
With the I/O SKIP
gate, th ese signals are PWR SKIP, RDR SKIP, and

level. The ACOO through ACl signals (Drawing
BS-8L-0-10) are examples of M623 applicotion.

TTSKIP,

Figure 2-1 1 shows the M660 logic configuration This
bus driver circuitry provides low impedance 100 ohm

2.7.4 M660 Bus Driver Output Circuit

M623/M906 Positive Output Circuit

2.7.3

terminated cable driving capability, using M-Series

The M623 Bus Driver module contains 12 negative
NAND circuits. Used with the M906 Cable Terminator module, the output is clamped to prevent excur-

levels, or pulses of duration greater than 100 ns.
Each output can drive +5 mA at the high level and
sink 20 mA at the low level, in addition to the termination current required by the G717 Termination
module. The M660 module is used in the PDP-8/L

sions beyond +3V and ground.

for the following output signals:

Figure 2-lOshows the M623/M906 logic configuration

The output can drive
+5 mA at the high level and sink 20 mA at the low

M906

lOP , lOP 2,
lOP 4, TS 3 and TSl (Drawing BS-8L-0-10).

(18 CIRCUITS)

POSITIVE BUS OUTPUT SIGNALS
(TO EXTERNAL DEVICE)

POSITIVE BUS OUTPUT SIGNAL
(TO EXTERNAL DEVICE)

M660
(

3 CIRCUITS)

r CIRCUITS)
M623
(12

=•"
AlO
681
OUTPUT SIGNALS FROM PROCESSOR
I

OUTPUT SIGNAL
FROM PROCESSOR

Figure 2-10

Figure 2-1

Typical M623/M906 Positive Output Circuit

Typical M660 Bus Driver Output Circuit

2-7

CHAPTER 3
OPERATION

This chapter contains operating information for the

regarding the controls and indicators of the PDP-8/L
and the ASR33 Teletypewriter.

PDP-8/L and the ASR33 Teletypewriter.

Operating
information for the peripheral input/output devices
is contained in their respective manuals.

3.1.1
3.1

CONTROLS AND INDICATORS

Computer

Figure 3-1 shows the location of the controls and
Indicators of the

The following paragraphs contain detailed information

Figure 3-1

PDP-8/L, and Table 3-1 describes

their functions.

PDP-8/L Front Panel

Table 3-1

Computer Controls and Indicators
Control or Indicator

OFF-POWER-PANEL LOCK switch

Function

OFF position, all power is removed from machine; in POWER

position, the machine operates normally, in PANEL

LOCK position

power is applied and all manual controls except the switch register
are disabled

3-1

Table 3-1 (Cont)

Compufer Controls and Indicators
Function

Control or Indicator

MEM PROT switch

When up, protects last page of memory (locations 7600

^^^

from modification; when off, normal read/write operation prevails.

DATA FIELD switch

Determines which core memory field (if extra 4K has been added) is
being addressed for data storage and retrieval

INST FIELD switch

Determines which core memory field (if extra 4K has been added) is
being addressed for instruction storage and retrieval

EA indicator

Indicates when extended memory

MEMORY ADDRESS indicators

Indicates address of memory that is being operated upon.

MEMORY BUFFER indicators

Indicates content of above address.

ACCUMULATOR indicators

Indicates contents of AC.

LINK indicator

Indicates contents of L.

SWITCH register

Provides a means for manually setting a 12-bit word into the machine.

INSTRUCTION indicators

Indicates contents of Instruction Register.

MAJOR STATES indicators

Indicates which of the six major states (Fetch, Execute, Defer,
Word Count, Current Address, or Break) the processor is in.

ION indicator

Indicates that interrupt system is enabled.

PAR indicator

Indicates (when parity option is installed) a parity error.

PROT indicator

Indicates that a memory protect violation has been detected.
Machine will halt with this condition.

RUN indicator

Indicates RUN flip-flop is set.

LOAD ADDR switch

Transfers contents of switch register into PC and into MA.

START key

being addressed.

Starts the program by turning off the

program interrupt circuits,

clearing the AC and L, setting the Fetch state, and starting the
central processor timing

CONT key

This key sets the

STOP key

Causes the RUN flip-flop to be cleared at the end of the instruction
in progress at the time the key is pressed.

RUN flip-flop to continue the program in the state
and instruction designated by the lighted console indicators, at the
address currently specified by the PC if SING STEP key is not on.

3-2

Table 3-1 (Coni)

Computer Controls and Indicators

Control or Indicator

Function

SING STEP switch

Steps program one cycle-at-time so that operator can observe contents of register in each major state.

EXAM key

This key transfers the content of core memory at the address specified
by the content of MA, into MB. The content of the MA is then incremented by one to allow examination of the contents of sequential
core memory addresses by repeated operation of the EXAM key
The
major state flip-flop register is cleared.
.

This key transfers the content of switch register into MB and core

DEP i<ey

memory at the address specified by the current content of MA. The
major state flip-flop is cleared. The contents of PC and MA are then
incremented by one to allow storing of information in sequential core

memory addresses by repeated operation of the DEP key

BXSiiii^!^
i.
...

-...

...-Sjl*

WM
Figure 3-2

Teletype Model ASR33 Console

3-3

3.1.2

as the programming and use of the computer become

Teletype

more sophisticated, they ore valuable in preparing
the initial programs and learning the function of machine input and output transfers.

Figure 3-2 shows the location of the ASR33 Teletypewriter controls and indicators, and Table 3-2 is a
list

of the

ASR33 controls and indicators with an exAll of the procedures described in the following para-

planation of their functions.

graphs require that the OFF-POWER-PANEL LOCK
switch be set to POWER.

OPERATING PROCEDURES

3.2

3.2,1

Manual Loading Procedures

Many means are available for loading and unloading
Programs and data can be stored or modified manually
by means of the facilities on the operator console.

The means used depend upon
the form of the information, time limitations, and the
peripheral equipment connected to the computer. The

PDP-8/L information.

following procedures are basic to any use of the

8/L.

The chief use of the manual data storage facility is to
load the Readin Mode Loader program into the computer core memory. The Readin Mode Loader (RIM)

PDP-

Although these procedures are used infrequently

Table 3-2
Teletype Controls and Indicators

Function

Control or Indicator

REL. pushbutton

B. SP. pushbutton

Disengages the tape in the punch to allow tape removal or tape
loading
Backspaces the tape in the punch by one space, allowing manual
correction or rubout of the character just punched.

OFF and ON pushbuttons

Control the use of the tape punch with operation of the Teletype

keyboard/printer

START/STOP/FREE switch

Controls use of the tape reader with operation of the Teletype.

the lower FREE position, the reader is disengaged and can be loaded
or unloaded. In the center STOP position, the reader mechanism is
engaged but de-energized. In the upper START position, the reader
is engaged and operated under program control.

Keyboard

Provides a means of printing on paper in use as a typewriter and
pushbutton.
punching tape when the operator presses the punch
The keyboard also supplies input data to the computer when the LINE/

OFF/LOCAL switch is in the LINE position.
LINE/OFF/LOCAL switch

Controls application of primary power in the Teletype and controls
In the LINE position, the Teletype
energized and connected as an I/O device of the computer. In
the OFF position, the Teletype is de-energized. In the LOCAL
position, the Teletype is energized for off-line operation, and signal
connections to the processor are broken. Only line use of the Teletype requires that the computer be energized through the POWER
switch if primary power for the Teletype is supplied from a source
other than the outlet at the back of the computer.

data connection to the processor.
is

3-4

is a program used for loading into the PDP-8/L other
programs that have been assembled on perforated tape

RIM format.

To check the contents of an address in core memory,
the EXAM key.

This program and the

RIM tape format
are described in the PDP-8/L Users Handbook (see
Small Computer Handbook, C-800, 1968 edition) and
in Digital Program Library descriptions. The RIMproin

the contents of the address.

The contents of the MA

are incremented by Iwith the operation of the EXAM

key, so that the contents of consecutive addresses can
be examined by repeated operation of the EXAM key

gram is also listed in Table 3-3 for rapid reference
and can be used as an exercise in manual data storage.
To store data manually in the PDP-8/L core memory
proceed as follows:
a .

MA as in step a; then press
The MEMORY BUFFER lights indicate

set the address into the

after the original (or starting) address

loaded.

Any

address can be modified by repeating steps a and b.

Set the bit switches of the SWITCH REGISTER

3.2,2 Teletype Loading Procedures

(SR) to correspond with the address bits of the first

word to be stored.

Press the

LOAD A DDR key and

Information can be stored or modified in the computer
under program control
For example, havingtheRIM
Loader stored in core memory allows RIM format tapes
to be loaded as follows.

observe that the address specified by the SR is held
in

the MA,

MEMORY ADDRESS.

Set the SR to correspond with the data or in-

struction word to be stored at the address [ust set

Set the Teletype LINE/OFF/LOCAL switch to

into the MA.

the

LINE POSITION.

the

Lift

DEP key and observe that

the MB, and hence the core memory, holds the

word set by the SR.

Load the tape in the Teletype reader by setting
the START/STOP/FREE switch to the FREE position,
b.

Observe that the contents of the MA have been incremented by
so that additional data can be stored at
sequential addresses by repeated SR setting and DEP
key operation

releasing the cover guard by means of the latch at
the right, loading the tape so that the sprocket

wheel teeth engage the feed holes in the tape,
closing the cover guard, and setting the switch to

Table 3-3
Readin Mode Loader Program

Address

7756,
7757,
7760,
7761,
7762,
7763,
7764,
7765,
7766,
7767,
7770,
7771,
7772,
///3,
777 A,
7775,
7776,

Octal
Content

Tag

6032

BEG,

Mnemonic

Comments

/CLEAR AC AND FLAG

KCC

6031

KSF

/SKIP IF FLAG =

5357
6036
7106
7006
7510
5357
7006

JMP .-1

/LOOKING FOR CHARACTER

KRB
CLL RTL

/READ BUFFER

RTL

/CHANNEL 8 IN ACO
/CHECKING FOR LEADER
/FOUND LEADER
/OK, CHANNEL 7 IN LINK

SPA

JMP BEG+1
RTL

6031

KSF

5367
6034
7420
3776
3376
5356

JMP .-1
KRS

SNL

DCA TEMP
DCA TEMP
I

JMP BEG
TEMP,

3-5

/READ, DO NOT CLEAR
/CHECKING FOR ADDRESS
/STORE CONTENTS
/STORE ADDRESS

/NEXT WORD
/TEMP STORAGE

the STOP position.

Load the tape in the back of
the reader so that it moves toward the front as it is
read. Proper positioning of the tape in the reader

3.2.3 Off-Line Teletype Procedure

finds three channels being sensed to the left of the

for typing,

sprocket wheel and five channels being sensed to

use the Teletype in this manner:

The Teletype can operate separately from the PDP-8/L
punching tape, or duplicating tapes. To

the right of the sprocket wheel

c .

Set the

MEMORY PROTECT switch to down

Assure that the primary Teletype power is on.

Set the Teletype

LINE/OFF/LOCAL switch to

the LOCAL position.

position.

c. Load the punch as follows. Raise the cover
and manually feed the tape from the top of the roll
into the guide at the back of the punch. Advance
the tape through the punch by manually turning the
friction wheel; then close the cover.

Load the starting address of the RIM Loader
program (7756 ) into the MA using the SR and the

LOAD ADDR l<ey.

Energize the punch by pressing the

ON push-

button, and produce about 2 ft of leader.

START key and set the 3position Teletype reader switch to the START position. The tape is read into memory by program
e.

leader-trailer can be either 200

Press the computer

or 377

The
code

To produce the 200- code leader, simultaneously
press and hold ihe. CTRL and SHlFT keys with the
left hand; press and hold the REPT key; press and
release the P key. VVhen the required amount of
leader has been punched, release the REPT key,
then CTRL and SHIFT kgys. To produce t he 377
code leader, simultaneously press and hold both

control

The RIM Loader program loads the Binary Loader (BIN)
program as previously described. With the BIN Loader
stored in core memory, program tapes assembled in

the REPT and RUB OU T keys until a sufficient
amount of leader has been punched.

Program Assembly Language (PAL III) binary format
can be stored as described in the previous procedure,
except that the starting address of the BIN Loader
(7777_) is used in step d. After storing a program in
this manner, the computer stops; the AC should contain
all O's if the program is stored properly.
If the computer stops with a number other than
in the AC, a
checksum error has been detected; therefore, the program has been stored incorrectly, and the storage procedure should be repeated. When the program has
been stored correctly, initiate it by loading the program starting address (usually designated on the leader
of the tape) into the PC and MA using the SR and
LOAD ADDR key. Then press the START key.

an incorrect key is struck while punching a tape,

the tape can be corrected as follows.

the error is

noticed after typing and punching N characters, press,
the punch B. SP. (backspace) push-button N+1 times

and strike the keyboard RUB OUT Key N+1 times.
Then continue typing and punching with the character
which was in error

To duplicate and obtain a listing of an existing tape,
load the tape to be duplicated in the paper tape reader

LOCAL/LINE switch to LOCAL and turn the
punch on, and turn the paper tape reader on.
or set the

3-6

CHAPTER 4
THEORY

This chapter is divided into four sections and covers

4.1 .5

Memory Buffer Register (MB)

the theory of operation of the PDP-8/L Computer.
All data to be written into core memory Is loaded

Section I contains a discussion of the theory at a
block diagram level; Section II contains a discussion
in terms of general theory of operation; Sections III

first

into the 12-bit MB.

Through the facilities

and IV cover detailed memory theory and detailed

provided by the major-register gating network, the
MB accepts data from any of the major registers In

processor theory, respectively.

the processor and, during a high-speed data -break
transfer, from peripheral devices.

SECTION

Its

only output

capability, other than its direct access to core memI

ory, is through the processor interface to optional

BLOCK DIAGRAM DISCUSSION

peripheral equipment.

The following paragraphs discuss the major functional elements of the PDP-8/L as shov/n in the system
block diagram (Figure 4-1).

4.1 .6

Sense Register (Sense)

All data read from core memory is strobed first into

4.1

this 12-bit register.

REGISTERS

It accepts

data only from the

core memory and transfers data directly to the
Instruction Register (IR) and, through the major reg-

4.1 .1

ister gating

Accumulator (AC)

network, to any other register in the

processor.

The 12-bit AC serves as an input/output register for
programmed information transfers between core memory and peripheral equipment, and as a transfer register through which arithmetic and logic operations

4.1 .7 Instruction Register (IR)
This 3-bit register contains the operation code of the

instruction currently being performed by the comput-

are performed

er.

The three most-significant bits of the current

instruction load into the IR from Sense during a

4.1.2

Link

Fetch cycle. The contents of the IR are decoded to
produce discrete levels for each of the eight basic

(L)

instructions.

This 1-bit register extends the arithmetic facilities

of the accumulator and serves as the carry register
for two's complement arithmetic.

4.1 .8
4.1 .3

Switch Register (SR)

The 12-bit SR performs a dual function in that it
permits the manual loading of either a discrete corememory address into the PC or a 12-bit data or control word into core memory. The SR is loaded by 12
toggle switches located on the operator's console.

Program Counter (PC)

This 12-bit register contains the address of the core-

memory location from which the next instruction will
be taken

Actuation of either the LOAD ADDR or DEP keys
then causes the stored information to be loaded into
4.1 .4

the

Memory Address Register (MA)

MA or MB, respectively.

This 12-bit register contains the address in core mem-

4.2

ory that is currently selected for reading or writing.
This address is decoded by the memory selection

MAJOR REGISTER GATING NETWORK

matrix to permit addressing of all 4096 words of the

All internal data transfers occurring in the PDP-8/L

core memory

are implemented through the major-register gating

4-1

<±.

<./

ACCUMULATOR

PROGRAM

MEMORY

MEMORY
ADDRESS
REGISTER [MAI

COUNTER

(ACI
[12

Clock
PULSES

—

BUS

(12

euFFER

PC)

BITS)

[12

[MB]

BlTSl

(12

eiTS)

L- _

-—
W

DRIVERS/
RECf IVERS

;

PDSiTu,; B-S

L_
p

TTfTT TT

IZ^

I t

ho
4096 12-BiT
WORD
CORE -PLANE

MEMORY
NT

NPUT euS

NAl J

BUS^
SENSE AMPL

ti
COI^TROL

SENSE
REGISTER

MEMORY EXT

[12

•jfitl-t n

SIGNALS \4f-

•

SWITCH
REGISTER

INDICATORS

(SR)

Figure 4-1

OPERATOR'S CONSOLE

System Block Diagram

BITSI

ml
INSTRUCTION
REGISTER
(3

BITS)

network.

The network contains a separate gate

structure and a

PR8/L
PP8/L

common register input bus for each

of the 12 bits. Transfers between registers and into
and out of memory occur through the network. Data
and address information received through the I/O
interface also pass through this network.

High-Speed Tape Reader
High-Speed Tape Punch

The. data -break peripherals, also optionally available, are represented by moss memory devices, such
as magnetic tape, magnetic drum, and disk file

systems

4.3

TIMING AND CONTROL ELEMENTS

A Teletype ASR33 Automatic Send-Receive Set is
provided as standard equipment with the PDP-8/L.
In addition to a

4.3.1

Timing Elements

manual keyboard and hard-copy

printout facilities, the ASR33 contains on 8-level

paper-tape punch and a paper-tape reader, all of
which are interfaced with the processor through the
Teletype control logic and internal positive bus.

The processor and memory control circuits in the
standard PDP-8/L use fixed ond variable delay
lines in place of timing clocks.

Interleaving of

fixed delay sequences provides asynchronous control

between the processor and the memory. The overall
cycle time of approximately 1 .6 )js is determined by
the memory timing

4.5

MEMORY

For applications involving real

time, the KW8I Real Time Clock option is added to

The standard memory supplied with the PDP-8/L is a
random-access, coincident current , magnetic-core

the system

memory with a storage capacity of 4096 12-bit words.
The core planes and diode matrices that make up the
4.3.2 Control Elements

core array are mounted on printed-circuit cards.

Circuits in the PDP-8/L control program advance

These cards plug directly into the PDP-8/L logic rack
receptacles with the sense and inhibit inputs attached

and instruction skipping.

operate in response to conditions established in

on connector cards. An additional 4K of core memory may be optionally added externally to the PDP-

either the processor or peripheral equipment, control

8/L frame

These circuits, which

the flow of information between registers.

addi-

tion, they initiate program interrupt operations

The major elements of the core memory are described
paragraphs.

during which subroutines enable the servicing of

in the following

peripheral equipment.

4.5.1

4.4.

Core Array

INPUT/OUTPUT
The ferrite-core array consists of 12 (64 x 64) core
planes. This provides a total of 4096 12-bit words
of data and program storage. A thirteenth core

The PDP-8/L operates with two basic types of input/
output O/O) equipment. Peripherals which communicate with the processor through the external positive
programmed transfer I/O bus, and those which use
the external positive data break facility. In addition the high-speed perforated paper tape readerand
punch peripherals operate directly from control
modules located within the PDP-8/L processor assem-

plane is optionally available to permit a parity bit
for each word in memory.

4.5.2 Memory Control

Memory control circuits determine the sequence of

biy.

operations of the complete read/write memory cycle,
starting and stopping

each function as required.

Typical of optionally available programmed transfer

I/O bus peripherals are:

VC8/L
KV8/L
CR8/L
VP8/L

4.5.3 Address Selection

Oscilloscope Display Control
Storage Tube Display and Control
Low- Speed Card Reader
Incremental Plotter

The Memory Address register (MA) contains the 12-bit
address of the currently selected core-memory locat-

4-3

Count (WC)

This address is decoded through the selection

ion.

Current Address (CA) , and Break

(B)

The outputs of these flip-flops generate enabling
levels used within the control elements of the processor to implement particular machine functions.

switches and the diode matrix to enable passage of
read/write currents through specific X and Y drive
lines of the memory . The coincidence of these
currents selects the specific 12-bit core-memory

location desired.

The first three major states (F, D, and E) are sufficient to perform most machine functions in the areas of

4.5.4 Inhibit Drivers

and data transfers through the I/O bus. The last three
major states (WC, CA, and B) are used only for highspeed data transfers through the optional KD8L Data-

logical operations,

The PDP-8/L memory is so configured that, unless

memory read/write operations,

prohibited, all bit locations of the addressed memory
1
during the write

Break facility.

portion of the memory cycle.

The processor determines, near the end of each computer cycle, which major state will be peeded for the
activities to be performed in the next computer cycle.
At the very end of the cycle (TP4) the new riiajorstate will be entered by the setting of that particular

cell would be switched to a logical

Inhibit drivers, therelevels stored

fore, are used to ensure that the logic
in the

MB will be retained in the corresponding bit

locations of the addressed memory cell

flip-flop.

4.5.5

Sense Amplifiers

INTERNAL DATA FLOW

During the read portion of the memory cycle, sense
amplifiers detect analog signals induced in the sense

4.8

windings of the core array. These signals are amplified and used to set corresponding bits of the Sense

The simplified system block diagram shown in Figure
4-1 depicts the flow of data through the major elements of the PDP-8/L. Note that all data transfers
into the four major registers (AC, PC, MB, and MA)
occur through a register gating network and a common

SECTION II
GENERAL THEORY

The outputs of these four registers, plus

the Sense and SR, and the data input from the external interface are all connected to the input gates

The following paragraphs discuss the major functional
elements of the PDP-8/L in terms of their operational
dynamics. These dynamics will be discussed in greater detail In Sections III and IV.

of the major-register gating network.
This permits incoming data to be strobed into any

desired major register, or the contents of any register
to be complemented, incremented, or transferred into
any other major register. The complementing function
output of the
is implemented by transferring the
desired register through the gating network and back
into the same register. The incrementing function is
output of the register
performed by transferring the

4.6 TIME STATES/TIME PULSES
Each computer cycle consists of four basic time divisions, Tl , T2, T3, and T4, as denoted on the system

Each time division consists of a time
state (TS) and its associated time pulse (TP)
The
time states each extend throughout their particular
time division (TSl , TS2, TS3, TS4) and end with a
time pulse (TPl TP2, TP3, TP4)

through the gating network while inserting a carry
into the low-order bit of the word. The data is then

flow diagrams.

transferred back into the desired register.

4.9 INSTRUCTIONS
In general, the time states generate enabling levels

associated with the register outputs.
used to strobe data into registers.

Instruction words are of two types:

Time pulses are

and augmented.

memory reference

Memory reference instructions store

or retrieve data from core memory, while augmented

instructions do not.

4.7

MAJOR STATES

All instructions utilize bits

through 2 to specify the operation code. Operation
codes of Og through 5g specify memory reference
instructions, and codes of 68 and 7q specify augment-

The PDP-8/L contains six major-state flip-flops.
These are: Fetch (F), Defer (D), Execute (E), Word

ed instructions. Memory reference instruction execu-

4-4

tion Hmes are multiples of the

.6 |js

memory cycle.

Execution Time: 3.2 |js with direct addressing,
4.8 ps with indirect addressing.
Operation: The AND operation is performed between
the content of memory location Y and the content of
the AC. The result is left in the AC, the original
content of the AC is lost, and the content of Y is
restored. Corresponding bits of the AC and Y are
operated upon independently. This instruction, often
called extract or mask, can be considered as a bitby-bit multiplication. Example:

Indirect addressing increases the execution time of a

memory reference instruction by

.6 |js. The augmented instructions, input-output transfer and operate, are performed in 4.25 and .6 ps, respectively.
(All computer times are ±12%.)
1

4.9.1

Memory Reference Instructions

Since the PDP-8/L system contains a 4096-word core

memory, 12 bits are required to address all locations.
To simplify addressing, the core memory is divided

Original

Final

AC,

ACj

into blocks, or pages, of 128 words (2008 addresses)
;

Pages are numbered Og through 37g, each field of
4096-words of core memory uses 32 pages
The seven

address bits (bits 5 through 11) of a memory reference
instruction can address any location in the page on

which the current instruction is located by placing
a

in bit 4 of the instruction .

By placing a

4 of the instruction, any location in page

Symbol:

ACja Yj = >ACj

in bit

can be
Two's Complement Add (TAD Y)

addressed directly from any page of core memory.
All other core memory locations can be addressed
indirectly by placing a

Octal Code:

in bit 3 and placing a 7-bit

effective address in bits 5 through

Indicators:

of the instruct-

1 1

IRl ,

FETCH, EXECUTE

shown in Figure 4-2 and the instructions perform as

3.2 ps with direct addressing
4.8 ps with indirect addressing
Operation: The content of memory location Y is
added to the content of the AC in two's complement
arithmetic
The result of this addition is held in the
AC, the original content of the AC is lost, and the

follows:

content of Y is restored.

Execution Time:

ion to specify the location in the current page or

which contains the full 12-bit absolute address
of the operand
page

Word format of memory reference instructions is

If there is a

carry from

MEMORY

OPERATION
CODES 0-5

PAGE

ADDRESS

INDIRECT

ADDRESSING

Figure 4-2

Memory Reference Insfruction Bit Reference

Logical

AND (ANDY)

ACO, the link is complemented.
ful in

This feature is use-

multiple precision arithmetic.

Octal Code:
Indicators:

IRO,

FETCH, EXECUTE

Symbol:

4-5

ACO - 11 + YO -

1 1

= >ACO - 11

Execution Time: 3.2 ps with direct addressing,
4.8 ps with indirect addressing.
Operation: The content of the PC is deposited in core
memory location Y and the next instruction is taken
The content of the
from core memory location Y +
AC is not affected by this instruction.

Increment and Skip If Zero (ISZ Y)

Octal Code:
Indicators:

IR2,

FETCH, EXECUTE
3.2 p with direct addressing

Execution Time:

4.8 ys with indirect addressing .
Operation: The content of memory location Y Is incremented by one in two's complement arithmetic

Y +

If the

resultant content of Y equals zero, the content

of the

PC is incremented by one and the next instruc-

tion is skipped.

Jump to Y (JMP Y)

resultant content of Y does

If the

PC + 1 = >Y
= > PC
1

Symbol:

not equal zero, the program proceeds to the next

Octal Code: 5
Indicators: IR5, FETCH
Execution Time: 1 ,6 ps with direct addressing,
3.2 ps with indirect addressing .
Operation: Address Y is set into the PC so that the
next instruction is taken from core memory address Y.
The original content of the PC is lost. The content of

The incremented content of Y is restored
The content of the AC is not affected by

instruction.
to memory.

this instruction.

Symbol:

Y +

= >Y

If resultant

Deposit and Clear AC

Octal Code:
Indicators:

11=0, then PC +

= >PC

the AC is not affected this instruction.

(DCA Y)

Symbol:

IR3,

Y = > PC

FETCH, EXECUTE

3.2 |as with direct addressing,
4.8 ps with indirect addressing.
Operation: The content of the AC is deposited in
core memory at address Y and the AC is cleared.
The previous content of memory location Y is lost.
Execution Time:

Symbol:

4.9.2 Augmented Instructions
There are two augmented instructions which do not
reference core memory. They are the input-output
transfer, which has an operation code of 6, and the

AC = >Y
= >AC
then

operate which has an operation code of 7. Bits 3
through 1 1 within these Instructions function as an
extension of the operation code and can be micro-

Jump to Subroutine
Octal Code:
Indicators:

programmed to perform several operations within one
instruction. Augmented instructions are one-cycle

(JMS Y)

(Fetch) instructions that initiate various operations

IR4,

as a function of bit microprogramming.

FETCH, EXECUTE

OPERATION
CODE 6

GENERATES

AN I0P4
PULSE AT
EVENT TIME 3

AN TOP
PULSE AT
EVENT TIME 1

IF
.

A
A

DEVICE
SELECTION

GENERATES
AN lOP 2

PULSE AT

EVENT TIME
IF A 1

Figure 4-3

lOT Instruction Bit Assignments

4-6

A
A

1
.

4.9.2.1
Input/Output Transfer Instruction - Microinstruct ion7"ortIieTnput-oiItpuMTansferO
group
initiate operation of periplieral equipment and effect
information tronsfers between the processor and an I/O
device. Specifically, upon recognition of the operation code 6 as an lOT instruction, the computer
enters a 4.25 )js expanded computer Fetch cycle by
setting a PAUSE flip-flop and enabling the lOP
generator to produce lOP 1, lOP 2 and lOP 4 pulses
as a function of the three least significant bits of the
instruction (bits 9 through 11). These pulses occur
at 1 )js intervals designated as event times 1,2 and

4.9.2.2.1

3 as follows.

operate microinstruction format is shown in Figure

The operate instruction consists of two groups of

Group 1 (OPR 1) is principally
complement, rotate, and increment opera-

microinstructions.
for clear,

tions and is designated by the presence of a

in bit

Group 2 (OPR 2) is used principally in checking

the content of the accumulator and link and continuing to, or skipping, the next instruction based on the

check.

in bit 3 designates an

OPR 2 micro-

instruction .

Group 1 Microinstruction - The Group 1

4-4 and the microinstructions are explained in the
Instruction

lOP

lOT

Event

(MB)

Pulses

Pulse

Time

IOP1

lOT 1

10
9

IOP2
IOP4

IOT2
IOT4

Bit

succeeding paragraphs. Any logical combination of
bits within this group con be combined into one

For example,

microinstruction.

possible to

it is

assign ones to bits 5, 6, and 11; although it is not

logical to assign ones to bits 8 and 9 simultaneously

since they specify conflicting operations.

The lOP pulses are gated in the device selector of
the selected equipment to produce lOT pulses that
enact a data transfer or initiate a control operation. Program selection of an equipment is accom-

No Operation (NOP)

plished by bits 3 through 8 of the lOT instruction.

Octal Code: 7000
Sequence: None

These bits form a 6-bit code that enables the device
selector of a given device. The format of the lOT
instruction is shown in Figure 4-3.

Indicators:

IR7,

Execution Time:

FETCH
1

.6 ps

Operation: This command causes a 1 -cycle delay in
the program and then the next sequential instruction
is initiated.
This command is used to add execution
time to a program, such as to synchronize subroutine
or loop timing with peripheral equipment timing.

4.9.2.2 Operate Instruction - With operate instructions, the programmer can consider logical sequences
occurring during one computer Fetch cycle. These
sequences provide a logical method of forming micro-

Symbol:

instructions.

None

ROTATE

OPERATION
CODE 7

CMA

CLA

—

CONTAINS
A
TO
SPECIFY
6R0UP1

CLL

7
V
—CML

IF A
.

ROTATE
AC AND L

LEFT

Figure 4-4

Group 1 Operate Instruction Bit Assignments

4-7

POSITION IF A 0,
2 POSITIONS

ROTATE
AC AND L
RIGHT

1
.

—V
I

Symbol: ACj = >ACj + 1

Increment Accumulator (lAC)

AC11 =>L
L =

Octal Code: 7001
Sequence: 3
Indicators:

IR7,

> ACO

Rotate Two Right (RTR)

FETCH

Execution Time: 1 .6 ^iS
Operation: The content of the AC is incremented by

Octal Code: 7012
Sequence: 4

one.

Indicators:

IR7,

Execution Time:

Symbol:

AC +

= >AC

FETCH
1

.6 ps

The content of the AC is rotated one
binary position to the right with the content of the
link. This instruction is logically equal to two
Operation:

Rotate Accumulator Left (RAL),

successive RAR operations.

Octal Code: 7004
Sequence: 4
Indicators:

IR7,

Symbol: ACj = >ACi +2
ACIO = L

FETCH

ACll =AC0

Execution Time: 1 .6 ^s
Operation: The content of the AC is rotated one
binary position to the left with the content of the

= >AC1

Complement Link (CML)

The content of bits ACl - 1 1 are shifted to the
next more significant bit, the content of ACO is
shifted into the L, and the content of the L is shifted
link .

Octal Code: 7020
Sequence: 2

into AC11.

IR7, FETCH
Execution Time; 1 .6 ps
Operation: The content of the L is complemented.

Indicators:

Symbol: ACj = > ACj - 1

ACO = > L
L =

>AC11
Symbol:

Rotate Two Left (RTL)'

IR7,

Octal Code: 7040
Sequence: 2

FETCH

Indicators:

Execution Time: I .6 |js
Operation: The content of the AC is rotated two
binary positions to the left with the content of the
link.

Complement Accumulator (CMA)

Octal Code: 7006
Sequence: 4
Indicators:

L =

IR7,

FETCH

Execution Time: 1 .6 ps
Operation: The content of the AC is set to the one's
complement of the current content of the AC . The

This instruction is logically equal to two

content of each bit of the AC is complemented
individually.

successive RAL operations

Symbol: ACj = > ACj - 2
ACl = >L
ACO = >AC11
L = >AC10

Symbol: ACj = >ACi

Complement and Increment Accumulator (CIA)
Octal Code: 7041
Sequence: 2,3

Rotate Accumulator Right (RAR)

IR7, FETCH
Execution Time: 1 .6 ps
Operation: The content of the AC is converted from
a binary value to its equivalent two's complement
number. This conversion is accomplished by combining the CMA and lAC commands, thus the content
of the AC is complemented during sequence 2 and is
Indicators:

Octal Code: 7010
Sequence: 4
Indicators:

IR7,

Execution Time:

FETCH
1

.6 ps

The content of the AC is rotated one
binary position to the right with the content of the
link . The content of bits ACO - 10 are shifted to the
next less significant bit, the content of ACl 1 is shifted into the L, and the content of the L is shifted into
Operation:

incremented by one during sequence 3.
Symbol: ACj = >ACj,
then AC + 1 = > AC

ACO.

4-8

Clear Link (CLL)

Indicators:

Octal Code: 7100
Sequence: 1

Execution Time: 1 .6 |js
Operation; Each bit of the AC is set to contain a
binary 1 . This operation is logically equal to com-

Indicators:

IR7,

FETCH

IR7,

bining the CLA and

Execution Time: 1 .6 (is
Operation: The content of the L is cleared to contain

Symbol:

CMA commands.

= >ACi

aO.
4.9.2.2.2 Group 2 Microinstructions - The Group
2 operate microinstruction format is shown in Figure
4-5 and the primary microinstructions are explained
in the following paragraphs. Any logical combination of bits within this group can be composed into
one microinstruction.

= >L

Symbol:

Set Link (STL)

Octal Code: 7120
Sequence: 1 ,2
Indicators:

IR7,

Execution Time:

FETCH

If skips are combined in a single instruction, the

inclusive OR of the conditions determines the skip

.6 ^s

when bit 8 is a 0; and the AND of the inverse of the
conditions determines the skip when bit 8 is a
For
.
example, if ones are designated in bits 6 and 7 (SZA
and SNL), the next instruction is skipped if either
the content of the AC = 0, or the content of L =

The L is set to contain a binary 1 . This
instruction is logically equal to combining the CLL
Operation:

and CML commands.
Symbol:

= >L

and 8, the next

If ones are contained in bits 5, 7,

instruction is skipped if the AC contains a positive

number and the L contains a 0.

Clear Accumulator (CLA)

Halt (HLT)

Octal Code: 7200
Sequence: 1
Indicators:

IR7,

Octal Code: 7402
Sequence: 3

FETCH

Execution Time: 1 .6 |js
Operation: The content of each bit of the AC is
cleared to contain a binary 0.

Symbol:

Indicators:

RUN off

IR7,

Execution Time: 1 .6 ps
Operation: Clears the RUN flip-flop at Sequence 3,
so that the program stops at the conclusion of the
current macTiine cycle. This command can be combined with others in the OPR 2 group that are executed during either sequence 1 , or 2, and so are per-

= >AC

Set Accumulator (STA)

formed before the program stops

Octal Code: 7240
Sequence: 1 ,2

0= >RUN

Symbol:

REVERSE
SKIP

OPERATION
CODE 7

SENSING OF

CLA

SZA

BITS 5,6,7

HLT

•

—

CONTAINS A1
TO SPECIFY

SMA

SNL

OSR

GROUP 2

CONTAINS AO
TO SPECIFY

GROUP 2

Figure 4-5
Group 2 Operate Instruction Bit Assignments

4-9

OR With Switch Register (OSR)

Skip on Zero Accumulator (SZA)

Octal Code: 7404
Sequence: 3

Octal Code: 7440
Sequence: 1

Indicators:

IR7,

FETCH

Indicators:

the SR.

IR7,

Execution Time:

Execution Time: 1 .6 ^js
Operation: The inclusive OR operation is performed
between the content of the AC and the content of

FETCH
1

.6 ps

Operation: The content of each bit of the AC is
sampled, and if any bit contains a
the content of
the PC is incremented by one so that the next sequential instruction is skipped. If all bits of the AC

The result is left in the AC, the original

content of the AC is lost, and the content of the SR
is unaffected by this command. When combined with

contain a 0, no operation occurs and the next sequen-

the CLA command, the OSR performs a transfer of the

tial instruction is initiated.

content of the SR into the AC.

Symbol:

Symbol: ACj V SRj = >ACi

ACO -

1 1

= 0, then PC + 1 = > PC

Skip on Non-Zero Accumulator (SNA)

Skip, Unconditional (SKP)

Octal Code: 7450
Sequence: 1

7410

Octal Code:
Sequence:

Indicators:

IR7,

Indicators:

FETCH

Execution Time: 1 .6 |js
Operation: The content of the PC is incremented by

PC +

FETCH
1

.6 |js

The content of each bit of the AC is
sampled, and if any bit contains a
the content of
the PC is incremented by one so that the next seOperation:

one so that the next sequential instruction is skipped.
Symbol:

IR7,

Execution Time:

quential instruction is skipped.

= > PC

If all bits of the

AC contain a 0, no operation occurs and the next
sequential instruction is initiated.

Skip on Non-Zero Link (SNL)

Symbol:

Octal Code: 7420
Sequence: 1
Indicators:

IR7,

contains a

ACO - 11 / 0, then PC +

= > PC

Skip on Minus Accumulator (SMA)

FETCH

Octal Code: 7500
Sequence: 1

Execution Time: 1 .6 |js
Operation: The content of the L is sampled, and if
it

Indicators:

the content of the PC is incremented

IR7,

Execution Time:

by one so that the next sequential instruction is skipped. If the L contains a 0, no operation occurs and

FETCH
1

fjs

Skip on Zero Link (SZL)

Operation: The content of the most significant bit of
the AC is sampled, and if it contains a 1 , indicating
the AC contains a negative number, the content of
the PC is incremented by one so that the next sequential instruction is skipped. If the AC contains
a positive number no operation occurs and program
control advonces to the next sequential instruction.

Octal Code: 7430
Sequence: 1

Symbol:

the next sequential instruction is initiated.

Symbol:

If L = 1,

Indicators:

IR7,

then PC + 1 = > PC

ACO = 1, then PC +

= > PC

FETCH

Execution Time: 1 .6 ^js
Operation: The content of the L is sampled, and if

Skip on Positive Accumulator (S PA)

it contains a
the content of the PC is Incremented
by one so that the next sequential instruction is skipped
If the L contains a 1 , no operation occurs and

Octal Code: 7510
Sequence: 1
Indicators:

the next sequential instruction is initiated.

Symbol:

If L

IR7,

FETCH

Execution Time: 1 .6 \is
Operation: The content of the most significant bit
of the AC is sampled, and if it contains a
indicat-

= 0, then PC + 1 = > PC

4-10

4.10.1

ing a positive number (or zero), the content of the

Instructions

PC is incremented by one so that the next sequential
instruction is skipped. If the AC contains a negative
number, no operation occurs and the program control advances to the next sequential instruction.

Symbol:

ACO = 0, then PC +

The two instructions associated with the program
interrupt synchronization element are lOT microin-

These instructions are:

structions.

Interrupt Turn On

= > PC

(ION)

Octal Code: 6001

Not applicable
FETCH, ION
Execution Time: 4,25 ps
Event Time:

Clear Accumulator (CLA)

Octal Code: 7600
Sequence: 2
IR7,

Indicators:

IR6,

Operation:

This command enables the computer to

respond to a program interrupt request.

FETCH

computer executes the next instruction, then enables
The additional instruction allows exit
from the interrupt subroutine before allowing another
interrupt to occur. This instruction has no effect upon
the condition of the interrupt circuits if it is given
when the interrupt is enabled.
the interrupt.

a binary 0.
= >AC

Symbol:

4.10

If the inter-

rupt is disabled when this instruction is given, the

Execution Time: 1 .6 ps
Operation: Each bit of the AC is cleared to contain

Symbol:

Indicators:

= >INT. ENABLE

PROGRAM INTERRUPT
Interrupt Turn Off (lOF)

Some of the I/O devices used with the PDP-8/L reOctal Code; 6002
Event Time: Not applicable

quire several instructions to complete a data transfer

Others are so slow
in operation, relative to the computer, that it would
consume a prohibitive amount of time to have the
computer wait in a skip loop for their operation to be
completed. These devices, therefore, employ the
program interrupt facility.

or perform a specified operation.

Indicators:

lR6,

FETCH

Execution Time: 4.25 |js
Operation: This command disables the program interrupt synchronization element to prevent interruption
of the current program.

When the program enables the program interrupt

Symbol:

= >INT. ENABLE, INT. DELAY

facility, the computer senses interrupt requests from

peripheral devices.

The interrupt may also be in-

itiated in response to a

programmed lOT instruction.

SECTION III
DETAILED MEMORY THEORY

An interrupt is allowed to occur only on completion
of the instruction currently in process and takesaffect

The following paragraphs discuss memory theory at a

at the beginning of the following Fetch cycle.

detailed level.

A program interrupt is similar in effect to a JMS to
memory address 0000. The content of PC is saved in
location 0000 and the next instruction taken from
location OOOIs.

4.11

OVERALL MEMORY THEORY

The instruction stored at this

location is usually a JMP to a peripheral servicing

The basic PDP-8/L contains a single 4096-word,
12-bit core memory which performs all normal functions of data storage and retrieval. All necessary
control elements for the memory are contained within

subroutine.
After identifying the interrupting device and ser-

vicing it, the processor performs a

JMP

the basic PDP-8/L.

0000 (jump

to the address specified by the content of location

The memory capacity of the computer can be increased, to a maximum of 8192 words with or without

0000) to return to the point at which the program was
interrupted.

4-n

parity.

triggers the f irst delay, (Drawing

If the parity option is selected, the parity

bit is carried as the thirteenth bit in each word.

LOCK flip-flops. The READ flip-flop enables the
read/write switches to provide the read currents to

of the extended memory option, however, necessitates the addition of the type MC8/L Memory Extension Control.

BS-8L-0-13),

MEM BEGIN is produced, setting the READ and

Use

The extended memory is located

The LOCK flip-flop prevents

the memory stack.

Initiation of another memory cycle until the present

external to the processor.

cycle is completed.

Another tap of the delay line

Figure 4-6 is a block diagram showing the interrela-

provides the pulse input to the variable delay en-

tionship of the major elements of the PDP-8/L mem-

abled by the READ flip-flop. The pulse output of
the varia ble delay generates STROBE FIELD
and
STROBE. The variable delay is adjusted so these
signals occur toward the end of the read cycle.
STROBE FIELD gates the sense amplifier outputs
(Drawing BS-8L-0-14) Into the Sense register.

ory and its control elements.

4.12

MEMORY OPERATION

PDP-8/L memory operation involves five major
functions:

write.

STROBE returns to the central processor to clear the
MEM IDLE and PAUSE flip-flops (Drawing BS-8L-0-2)

address selection, Vead, sense, inhibit,

The memory control provides the timing and

and continue the processor timing cycle.

initiation of the read, sense, inhibit and write

functions.

Address selection is performed by the

contents of the

MA register, applied through the

Approximately 400 ns after Read Is initiated, a CYC
DONE pulse is produced. CYC DONE terminates the
Read cycle, sets the CYCLE flip-flop, and initiates
the second transition of the memory cycle-through the
same delay lines. The setting of the CYCLE flip-flop
enables CYC DONE (delayed) to set the INHIBIT flipflop. The inhibit output gates the data from the MB
to the inhibit drivers (Drawing BS-8L-0-14). The
Write portion of the memory cycle is Initiated approximately 50 ns after the INHIBIT flip-flop Is set. When

address selection X and Y Diode Selection Matrices.

4.12.1

Memory Control

The memory control consists of series-connected delay lines with associated logic gates and control
flip-flops (Drawing BS-8L-0-13). An initiating
signal,

MEM START, from the central processor,

cycles through the delay lines alternately setting and

set, the WRITE flip-flop enables the read/write

clearing the varies control flip- flops, and returns to

switches to provide the write currents to the memory

the prbcessor as^he

MEM DONE signal.

stack, and clear the LOCK flip-flop.

The timing
for this cycle Is fixed by prewired taps on the delay
lines. The control flip-flops enable the read/write
and inhibit currents, and control the memory cycle.

layed CYC

Another de-

DONE pulse clears the CYCLE flip-flop

during the write portion of the memory cycle.

A second CYC DONE pulse, generated approximately
400 ns after the Initiation of the Inhibit operation,
terminates the inhibit and write operations. In addition, this C YC DONE pu lse combines with LOCK (0)
to generate MEM DONE, indicating the end of the

Figure 4-7 illustrates the waveshapes of the memory

The transition and duration times
are approximate due to the Inexact delay through
the pusle amplifiers (approximately 50 ns) , and gates
(approximately 20 ns)
For explanation purposes. It
Is assumed that the processor POWER CLEAR signal
has been generated, and the START key actuated
producing MEM START.
control signals.

memory timing cycle.

The MEM START signal to the memory control circuitry Is gated by the field selection signal

EA.

MEM DONE sets the MEM

IDLE flip-flop (Drawing BS-8L-0-2) in the processor
control, reinitiating another processor/memory cycle.

4.12,2_Read/WrUe_

Initially,

MEM START sets the MEM ENABLE flip-flop when

The ferrlte-core memory consists of 12 planes (13 If

EA specifies basic memory field operation. The
buffered MEM ENABLE output enables the contents

the parity option Is selected), each containing 4096

of the sense register to the major register bus; the

core assumes a stable magnetic state corresponding
either to a binary
or a binary 0,

ferrite cores arranged In a

X- and Y-axis selection current drivers, and the

64 x 64 core array.

Each

inhibit drivers

Selection and switching of the cores is provided by

The memory timing cycle consists of two transitions
through the same delay lines. After MEM START

four windings traversing each core in the memory in

a standard 3D selection technique.

4-12

An X-axis read/

—

{

TO INSTRJCTION REGISTER

CURRENT
LIMITING

RESISTORS

•

(G6241
-

AB25/AB26

SENSE AMPLIFIERS
AND MEM REGISTER

HEM 00
MEM 01
MEM 02

TO MAJOR
"

IGOZOl
i

MEM SUPPLY

NETWORK

AI8-AZ0/BI8-B20

MEM SUPPLY-*-

MEM ENABLE
MEM BEGIN

INHIB IT

FROM

4096
12-BIT WORD
CORE MEMORY

DRIVERS

MEMORY -<

(G228'5)

BUFFER

STROBE

Fl ELD

A23.B23,B24

BMEM ENABLE
INHIBIT

•

ooe

MAOO (0) i

MA06 (01

MAoetn

MEMORY CONTROL
ADDRESS
DECODING
AND
SELECTION
SWITCHES
{G22rs)
C23/C24

MAOO (t) I
MA01 (1)

MA02 [1)1
S MEM ENABLE
X

(G610

MI13

AND

MA07(1)

SELECTION
SWITCHES
[G22rS)
CI8/CI9

G61 1}

CD20/CD2Z

M2I6
M3I0

M360
M6I7

MACS

•

CIS
016
Dt4,DI5

MEM DONE
MEM START

CI7
DI7

« B MEM ENABLE

CLAMP

MA03(0)

YR/W

R/W

RETURN

I
MA04(1)

MA03{11

REGULATION AND
DETECTION
AB27

STOP OK -

ADDRESS DECODING

MEM ENABLE

AND SELECTION
SWITCHES
(G22rsi D23-'024

TTTTI

B MEIi

MA05(11

R/W RETURN
SELECTION

MEMORY VOLTAGE
(GB261

R/W SOURCE
INHIBIT ^

(G221'S1 018 /DI9

•

R/W SOURCE
ADDRESS DECODING
AND SELECTION
SWITCHES

POWER CLEAR '
SHUT DOWN

ADDRESS
DECODING

Y-AXIS
DIODE SELECTION
MATRIX

X-AXIS
OIOOE SELECTION
MATRIX
[G610,G61 1]
CD20 /CD22

RESISTORS

SWITCHES

(G624'S)
AB25 /AB 26

(G2281

D25

RW/SOURCE
SELECTION
SWITCHES
(G228)
C 25

THERMISTOR
[IN

MEMORY
STACK)

Figure 4-6

Memory System, Block Diagram

*—
POWER CLEAR

MEM START
OV
+ 3V

MEM ENABLE
OV

+ 3V

+3V

+ 3V
OV

+ 3V

+3V
OV
t-3V

INHIBIT

+3V
OV

+3V

The MEM START pulse width depends on the path of its origin i.e., approximately 150
nsflc if generated by a monuol function tike actuating Dep key, and approximately 500
nsec if generated from a previous program instruction.

Figure 4-7

Memory Timing Diagram

known as the half-select value. Only

write winding passes through all cores in each of 64

current level

horizontal rows; a Y-axis read/write winding passes

the reinforcing magnetic field caused by the coinci-

through all cores in each of 64 vertical rows; and a
sense and an inhibit winding pass through all cores of

dent current of both an X and a Y read/write winding
can cause the core located at the point of coincidence

each of 12 (or 13) planes.

to change state.

Through the use of select-

It is

this principle that allows the

ion circuits controlling the inputs of the X and Y

relatively simple winding arrangement to select one

read/write windings, any one of the 4096 12-bit word

and only one memory word out of a possible 4096 in
each array

locations can be addressed for writing data into, or

reading data out of memory.
Figure 4-8 shows a simple 4x4 core array. The
winding scheme shown on this array is identical to

The level of the read, write, and inhibit currents
passing through these windings is such that no single
winding produces a magnetic field strong enough to
cause a core to change its magnetic state. This

that used in the planes of the

PDP-8/L memory.

A half-select current passing through the X2 winding
from right to

4-14

left (write

direction) produces a magnet-

flow, therefore, the X2Y3 core on each plane
changes to, or remains in, the 1 state. This makes
each of these cores equivalent to one bit of a 12-bit

ic field fhat tends to change all the cores in that

horizontal row from the

to the

state.

The flux

produced by this current is, however, insufficient to
complete the state transition in any core. Simultan-

storage cell

eously, passing a half-select current through the Y3

winding from top to bottom (write direction) tends to
produce the same effect on oil cores in that particular
vertical row. Note, however, that both currents
pass through one core, located at the intersection of
the X2 and Y3 windings. This then becomes the
selected core

should be noted that passing half-select value write

currents through a particular pair of X and Y windings

produces the 1 state in all 12-bit positions of the
selected core-memory storage cell. To store usable
Information, however,
the

it is

also necessary to write

state during the write cycle in any or all bit

locations of the selected storage cell
This is performed by the inhibit windings, and the prior occurrence of a read cycle which put all the cores in the
.

The X and Y windings are so configured that, when
half-select value write currents are passed through
each, their resultant magnetic fields add in the core
at their point of intersection.

"0" state.

Their combined (full-

select) current then ensures that the selected core is
left in

the

state

Each inhibit winding, shown as a broken line on
Figure 4-8, passes through all cores on a particular

PDP-8/L core memory the X2 windings of all
12 planes are connected in series, as are the Y3

In the

windings.

When X2Y3 half-select write currents

plane. Unlike the X and Y windings, in which the
read and write currents flow in opposite directions,
the half-select value current in the inhibit windings

WRITE
WRITE -«

WINDING

Figure 4-8

Simple Core Memory Plane

4-15

always flows in the same direction. The magnetic
field generated by the inhibit current of a value and
polarity which effectively cancels the field generated by the Y-axis half-select write current. This
prevents the setting to the 1 state of any core through
which inhibit current is flowing.

MB for restoration to its original location during the

Each of the 12 inhibit windings is connected to the
output of an inhibit driver circuit. Each driver, in
turn, is controlled by the output of one bit of the
memory buffer register, which contains the data to
be stored in memory. When the write operation commences, each inhibit driver connected to an MB bit
containing a
is activated.
The resulting half-current
value output of the driver then prevents the writing of
a logic 1 in its assigned core plane. The MB bits

MA and select the proper source
and return lines for both the X- and Y-axes. These
selection circuits are shown on Drawings BS-8L-015 (X-axis selection), and BS-8L-0-16 (Y-axis
selection) in Volume II of this document. The polar-

write portion of the memory cycle.

4.12.3 Address Selection
The memory selector switches decode the address
specified by the

ity of the magnetic field applied to the cores of the

addressed cell is determined by the direction of
current flow through the core read/write windings.
It differs for

drivers.

a read or v/rite cycle.

The read/write

current selection circuits are shown on Drawing

containing logic "Is" disable their respective inhibit

BS-8L-0-13 (Memory Control).

This allows the cores pertaining to these bits

to have "Is" written into them.

The content of the
MB is therefore written intact into the selected core-

Figure 4-9 provides a combined and simplified version
of these two drawings showing the selection of a Y-

memory storage cell

axis memory cell and the method of determination of

To read out information contained in the 12-bit X2Y3

read/write current direction. The drawing assumes a
content of
in bits 6 through 1 1 of the MA, address-

memory cell, half-select read currents are passed

ing cell GO on Drawing

through both the X2 and Y3 windings.

BS-8L-0-16.

Since read

current flows in the opposite direction of write current,
all cores in the

X2Y3 cell previously set to the 1 state

NOTE

Cores already in the
state are, of course, unaffected.

are switched to the

state.

A sense amplifier circuit is provided for each of the

The component designation numbers used in
Figure 4-9 have been arbitrarily assigned to
assist in this discussion and do not relate to

12 core planes in the memory.

actual designations.

The input to each

amplifier is a sense winding which passes through

every core on the associated plane. If, during the
read operation, the addressed core in a plane makes
the 1 to
state transition, the flux change induces a
current in the sense winding of that plane. This
current develops a 20-30 mV pulse at the input to
the sense amplifier. This input is amplified, shaped,
and after threshold detection is used to set a SENSE
flip-flop connected to the output of the sense amplifier when STROBE FIELD
is generated.

With a read operation in process, the READ (1) line
will be affirmed enabling gates 3 and 6. The outputs
of these gates turn on both Q3 and Q6. This establishes a positive source and negative return for the
windings of all Y-axis cores serviced by address1 and 2.
This is the proper polarity
and current direction for a read operation

selection gates

With MA06-11 = 0, gates and 2 have been enabled,
and both Ql and Q2 will conduct. Current then
flows through Dl and Ql to D8. The read current
1

Addressed cores which were already in the
state,
when saturated by the full-select read flux, will
induce a limited amount of noise into their sense
winding. The voltage level produced by this noise
(in the order of 5 mV) will be insufficient to activate
the sense amplifier associated with that plane. The
SENSE flip-flop for that bit will therefore remain
clear, indicating a logic

then passes through the winding of the cores on the

Y-axis of 00 attempting to switch the cores to the
state. There are 12 X 64 cores along this Y-axis;
one for each bit and each X-axis. The read current
then passes through D4, bypassing Q2 and returns to
the memory supply (-) through Q6. The current does
not pass through the cores on the 01 through 07 and
10 through 77 Y-axis because of back biased diodes
within the matrix, and on the address selection
switches (Drawing BS-8L-0-16).

in that location.

Since this type of readout destroys the content of the
addressed cell (by switching all cores to Os), the data
stored in the Sense Register will be transferred to the

4-16

Q4 and Q5 would be turned on
by gates 4 and 5, reversing the direction of current
flow. The address selection path, however, remains
the same through the core winding on the Y-axis of

stated, each core through. which write current passes

The new current direction (write) attempts to
set the cores to the 1 state. As has been previously

the MB

In a write operation ,

00.

will

be set to the 1 state unless the inhibit driver

associated with that core has been activated by the
sensing of a logic

in that particular bit-position of

TO AXES Y10-Y70

ALL CORES
ON AXIS YO °

-C>

—

V.
r

TO AXES

Y0I-Y07

07
08

MEMORY SUPPLY

(

MEMORY SUPPLY I-)

MA06(0) MA07(0) -

MA08I0) B MEM ENABLE

MA09(0) -

MA10(01 -

MAI 1(01 READ (1) WRITE(l) -

Figure 4-9

Memory Address Selector or Read/Write
Current Control

4-17

KEY OPERATIONS- MANUAL FUNCTIONS

FLTR

ST FLTR
OUTPU".

OUTPUT

Ml *

SWITCH BUMPS, CONTACT BOUNCE ETC

INTEGRATING FLTR CIRCUIT RENDERS 100 MS DELAY (IN—OUT)

Lz:

ji*
•«•

— 2m5 del AY =( MFTP

(1 SI DE

OF FF

•

manual PRESET)

)

-^
2 >i5

2^5

(

DEL AY = (MFTP2)

SIDE OF FF

)

STANDARD PULSE ISOrstSOns

Figure 4-10

Manual Function Timing Diagram

4-18

SECTION IV
DETAILED PROCESSOR THEORY

2 ^is to generate MFTP2 which clears the MFTS2
flip-flop.

The MFTS2(0) level then generates the

MFTS3 timing level through a NAND gate.
The applications of the manual function timing levels
and pulses are described with the key functions.

This section describes in detail the computer timing,
data flow, and the generation of the instruction set.
This detailed discussion of theory enables the service
technician to bridge the gap between the engineering

4.13.2 Manual Operations

drawings and the various logic functions,

The following keys and switches are provided on the

START, STOP, LOAD ADDR,
CONT, EXAM, DEP, SING STEP, MEM PROT,

operators' console:

4.13

TIMING

DATA FIELD, INST FIELD, and the Switch Register.
All are single switches with the exception of the SR

The following paragraphs discuss the internal timing

which consists of a bank of 12 switches.

of the processor

These switches, used singly or in combination, permit
manual intervention to start the program, stop the
program, load data into a selected memory location,

Manual Function Timing Generator

4.13.1

When the computer is initially started, or when data
is

examine the contents of a memory location, and run
the program step-by-step for troubleshooting the

manually deposited, examined, or continued, or

the memory addressed, the processor and/or memory
cycles are entered by application of the Manual

system, or debugging new programs.

Function Time signals. These signals include the
time-state levels MFTSO, MFTSl , MFTS2, and MFTS3,

The following paragraphs contain detailed descriptions of the main control switches.

and timing pulses MFTPO, MFTPl and MFTP2 (Drawing BS-8L-0-2). The levels and pulses are independent from, and not to be confused with, the processor
timing-generator signals. The generator and the
manual timing signals are described in the following
paragraphs. Figure 4-10 shows the timing relationship between the manual timing signals.

described in Paragraph 4.15 of this chapter.

LOAD ADDR - The memory location to be addressed
toggled Into the switch register, and LOAD ADDR

keyed. This clears the major state register. MANUAL
PRESET, which performs this operation, is generated
by the MFTPO pulse when LOAD ADDR is pressed.

When on y of the levels KEY LA, KEY ST, KEY EX,
KEY DP or KEY CONT are activated by pressing
one of the associated keys, a low-to-high level
transition occurs. The transition is smoothed by an
integrating filter which eliminates the noise generated by the closure of the key. To perform this
function, a 100 ms delay is incorporated as part of
the filter. The filter output activates the ST(Schmitt
Trigger ) which combines with RUN (0) to generate
MFTSO. The RUN (0) level controls the timing generator by preventing manual time levels and pulses from
occurring if a key is pressed when the computer is
running
MFTSO is inverted to produce MFTSO which
sets the MFTSl flip-flop. MFTSO also combines with
KEY EX + DEP to enable clearing of the RUN flipflop during T3 of the processor cycle.

The DATA and

INST FIELD switches are described with extended
memory operation. The MEM PROT switch function

No further operations occur until MFTS2 when the
address toggled into the switches is loaded into the
PC and MA. This occurs through the generation of
an SR ENABLE signal (Drawing BS-8L-0-4) a MA
LOAD signal at MFTPl and a PC LOAD signal at
MFTP2 (Drawing BS-8L-0-6).
Deposit (DEP) - If data is to be manually loaded into

memory, the starting location is placed in the PC, as
described with LOAD ADDR, and the data loaded,
word-by-word through the SR (Switch Register) by the
action of DEP.

Pressing

DEP clears the major state registers during

MFTO by generating the MANUAL PRESET level
Manual time-pulse MFTPO generates MANUAL PRE-

Timing level MFTSO generates an MFTPO pulse. This
pulse is delayed 2 |js to produce MFTPl . The MFTPl

SET when DEP is pressed.

pulse sets the MFTS2 flip-flop which clears the MFTSl

(starting address) of the PC are transfen-ed to the

flip-flop ending that time state,

MFTPl is delayed

During MFTl the contents

MA.

The generation of the PC ENABLE signal (Drawing

4-19

BS-8L-0-4) by MFTSl -KEY ST+EX+DP, and the AAA
LOAD signal (Drawing BS-8L-0-6) by MFTP-KEY

contents of the location addressed by observing the

ST+EX+DP perform this transfer operation

MB indicator lights located on the console panel.

During MFT2, the address in MA is incremented and

During the write portion of the memory cycle, the
content of the MB containing the word examined is
restored to the original memory location. Thus, the

stops.

transferred back to PC, leaving the current address
in

MA and placing the next consecutive memory

address in PC

content of the examined address remains in the MB
and in the memory location. The content of the
address examined may be modified through the use of

This transfer Is accomplished by an

MA ENABLE level (at MFTS2), and a PC LOAD
pulse (at MFTP2) .

This permits the operator to examine the

The address is incremented by the

insertion of a Carry into the adder of the least-signi-

the Switch Register switches and DEP.

ficant bit during the transfer of the address into PC.

noted, however, that as part of the cycle which
extracted the data from memory, the PC was incremented by one to set up the address of the next instruction. The next word, therefore, would be loaded

This occurs by generating a CARRY INSERT level

(Drawing BS-8L-0-5) during MFTS2.

should be

During this transfer operation the memory cycle is

into the core-memory address next in sequence to the

started to permit loading of the SR data into the

address of the presently displayed word.

currently addressed memory location.

SR and LOAD ADDR must therefore be used to set the
PC back to the address of the displayed word prior to
insertion of the new word .

The actuation

of ony manual key, except LOAD ADDR, generates
a MEM START pulse at MFTP2 (Drawing BS-8L-0-2),

The 12-bit

initiating the memory cycle.

START - Pressing START initiates execution of a program previously loaded into core memory. When this
key is pressed, MFTPO is combined wit h the KEY S T
level to generate the INITIALIZE and INITIALIZE

During MFT3, the actuation of Deposit generates

SR ENABLE (Drawing BS-8L-0-4).

This gates the

data as signified by the Address switch positions,

onto the major-register bus. TP2 of each cycle, the
MB LOAD pulse (Drawing BS-8L-0-6), permits MB
to accept the Address register data present on the
major-register bus. During the write portion of the
memory cycle, this data is written into the memory
location specified by the contents of MA. This completes the deposit cycle.

signals (Drawing BS-8L-0-2) v^rhich clear the tele-

type circuits and initialize the machine.
pulse also generates

The MFTPO

MANUAL PRESET, which sets the

TSl flip-flop.

During MFT1 , the contents of the PC transfer through
the major register gating network to the MA, and the

MFTSl (0) level clears the lOP flip-flops.
Subsequent data is loaded in sequential memory
locations by toggling the data into the SR and actuating DEP. The PC is incremented for each deposit,
making further addressing unneccessary until such
time as access to a non-sequential memory address is

During MFT2, the AC, LINK (Drawing BS-8L-0-8)
and INT ENABLE (Drawing BS-8L-0-7) flip-flops are
cleared and the Fetch flip-flop is set. The memory
cycle is also initiated at this time by the generation
of MEM START (Drawing BS-8L-0-2).

required.

Examine (EXAM) - The actuation of EXAM permits
inspection of the word in the currently addressed
memory location. This sequence is identical to the

The memory sign al STRO BE is activated during the
memory cycle. STROBE initiates the automatic sequences of the processor by continuing the processor
cycle. The RUN flip-flop is set by processor timepulse TP3, and the program instructions are executed
until either a halt command is encountered, or the
computer is manually stopped.

previously discussed deposit operation up to the start
of the memory cycle.

During the read portion of the memory cycle, the
contents of the address specified, when the LOAD
ADDR key was pressed, are transferred from core

STOP - Pressing the STOP key will halt a program at

memory to the Sense register. The memory signal
STROBE FIELD allows this transfer and also ends
processor time-state TSl , and initiates TS2.

the termination of the current cycle.

Operation of
key generates a KEY STOP level which clears the
RUN flip-flop at the next TP3 pulse. Clearing RUN

this

At the

inhibits generation of the next MEM START pulse preventing another memory cycle. The transfer of any

end of T2, time-pulse TP2 generates an MB LOAD
pulse which completes the examine operation by
transferring the contents of the Sense register to the

data between registers is inhibited after completion

MB. Upon completion of this transfer, the processor

of the current cycle, preventing

4-20

loss

of data .

The

operator can examine the contents of the registers

During processor time-state TS3 the INHIBIT and
WRITE control flip-flops (Drawing BS-8L-0-13) are
set by the delayed MEM START signal . At the end of
the memory cycl e, the INHIB IT and WRITE flip-flops

prior to the start of the next cycle

SING STEP - Pressing the SING STEP switch causes
The RUN

the program to step one cycle at a time.

are cleared and

Subsequent actuation of the
CONT key generates a single MEM START pulse, but
prevents the processor from automatic execution of
the program, therefore permitting only a single processor/memory cycle to be executed.

MEM DONE is generated.

flip-flop is not set.

MEM DONE sets the MEM IDLE flip-flop (Drawing
BS-8L-0-2).

The setting of this flip-flop allows the

generation of MEM START (initiating another memory
cycle) and TP4, if RUN is still set and PAUSE is cleared.

Time pulse TP4 clears TS4 and sets TSl , initiat-

ing another processor cycle.

4.13.3 Time States
The paragraphs above describe the relationship between the PDP8/L processor and memory timing cycles
when the previous cycle initiates the next cycle by
generating TP4 and MEM START. This assumes that
the PDP-8/L is running. When the computer is
initially started (by pressing START, LOAD ADDR*,
DEP, or CONT) the processor and memory cycles are
entered in the following manner.

Four time-state levels (TSl , TS2, TS3, and TS4) and
associated time pulses (TPl , TP2, TP3, and TP4) are

generated during each computer cycle.

This train of

levels and pulses is initiated at the start of each mem-

ory cycle and terminated upon its completion.

The

generation of the time state and time pulses and their
relationships are discussed below and are shown in

Figure 4-11 .

The processor timing cycle is initiated by generating

MANUAL PRESET whi.ch sets the TSl flip-flop, and
TSl , the first time-state produced (Drawing BS-8L0-2), is entered at the end of the previous processor

simultaneously clears the TS2, TS3, and TS4 flip-

cycle by TP4. The memory cycle is also initiated at
this time by generating MEM START (Drawing BS-8L0-2). The duration of TSl and generati on of tim e
pulse TPl depends on the memory signal STROBE
which is produced during the Read portion of the
memory cycle. Therefore, the duration, of TSl
depends on the memory used and the STROBE delay
adjustment.

of the keys mentioned above except for CONT.

flops.

this key is pressed, a

By pressing any of the keys above with the exception
MEM START is generated initiating

of LOAD ADDR,

a memory eye le

Although normal computer operation is through the
use of a continuously running stored program, proceeding in sequence from instruction-to-instruction,
this process must be started manually. The SING
STEP key previously mentioned may also allow computer program progression, a cycle at a time, for
maintenance and program debugging purposes.

(Drawing BS-8L-0-13) . MEM START is delayed to
generate MEM BEGIN which starts the Read function

by setting the READ flip-flop. The memory signal
STROBE (Drawing BS-8L-0-13) is generated by an
adjustable delay toward the end of the Read portion
of the m emory cycle by MEM START (delayed).

STROBE allows the transition from processor timestate
TSl to TS2, a nd gener ates time pulse TPl (Drawing
BS-8L-0-2).

STROBE also clears the MEM IDLE flip-

MEM START.

4.14 I/O TIMING
The processor timing cycle is interrupted between T3
and T4 to perform an I/O cycle, if specified by an

lOT (input/output transfer) instruction. During the
I/O cycle, up to three pulses (lOPs) can be generat-

When STROBE generates TPl , the processor-timing
progression continues.

TPl

is delayed

When

TP4 is forced, setting the TSl

flip-flop.

During processor time TSl , MEM START initiates the
memory cycle by progressing through a delay chain

flop disabling

MANUAL PRESET is generated by pressing any

by 0.15 \js

to generate TP2 which clears the TS2 flip-flop and
sets the TS3 flip-flop. TPl is also delayed 0.4 jjs to
generate TP3. The third time-pulse (TP3) clears TS3,
and if the instruction performed is not an input/output
instruction (lOT), TP3 sets the TS4 flip-flop.

* When

LOAD ADDR is pressed, MEM START is

inhibited, therefore, there is no memory cycle,

4-21

L
o
o

via
111

E
D
>D)

C3)

l/>

\
D5

o
o

4-22

ed, depending on the lOT Instruction performed (see
lOT instruction description in Paragraph 4.18.4).
The lOP pulses provide control between the processor
and peripheral equipment such as the ASR33 Teletype,
the PR8/L High-Speed Reader, and others.

The fol-

lowing paragraphs describe the I/O timing and the
associated logic circuitry.

is transmitted

through the de lay lines, re-enters the

same lines as I/O RE CYCTE and ends the cycle by
generating I/O END which initiates processor time
state TS4.

Refer to Figure 4-12

illustrating the I/O timing, and

TP3

The lOP generator consists of delay lin es with assoc iated logic gates and an lOP register. I/O START

Drawing BS-8L-0-2.

I/O START

I*- 300 ns -J

PAUSE
1/0 ROT—W330n»

_J
SeOnsI/O ON

I/O STROBE

I/O STROBE PULSES
OCCUR 580 ni AFTER
THE START OF EACH
lOP LEVEL

I/O RECYCLE

lOP A-

lop e
lOP c

lOP 1

10 P 2

10 P 4

NOTE: Timing Tolerance! 12 %

Figure 4-12

I/O Timing Diagra m
4-23

When activated, I/O START sets the PAUSE flip-flop

T he protec t functi on is performed by generating the

(Drawing BS-8L-0-2) to prevent initiation of an othe r
process or/memory cycle during the l/O cycle. I/O

of either the

PROTECT lev el

levels combined with TS2(1) and the following signals.

START also triggers the delay ed pulse se quence.
Approximately * 200 ns after l/O START, I/O ROT is
produced, setting the lOPAand l/O ON flip-flops.
This allows generation of an lOPl pulse if MBII is
set. l/O STROBE is generated 600 ns later from another tap of the delay line. I/O STR OBE clears I/O
ON terminating lOPl and generating l/O RECYCLE.
I/O STROBE is also used in conjunction with lOP
pulses to enable

PROTECT is produced by assertion
MEM ALT 2, or WC(0)

MEM ALT

KEY PROTECT (asserted by the MEM PROT key);

EMA (enabling the protect function in the basic
memory; disabling it if the extended memory field
is added to the system);

MAOO (1) through MA04 (1) (defining the restricted

AC LOAD (Drawing BS-8L-0-6) for

clearing and loading data from a device into the

area 7600o through 7777 q in memory).

accumulator. However, the clearing and loading
operations normally occur as a res ult of IOP2, an d
IOP4 (refer to Paragraph 4.18.4.) I/O RECYCLE
indicates the end of the first pass through the delay
lines. This signal feeds back through the same delay

in the following

lines, generating another l/O

The MEM ALT 1 and MEM ALT 2 levels are produced
manner to allow generation of

PROTECT. MEM ALT 1 (Drawing BS-8L-0-4) is produced when the MB is altered by executing the DCA
or JMS instructions, by incoming da ta with a do ta

ROT and l/O STROBE.

break request, or by pressing DEP, MEM ALT 2
(Drawing BS-8L-0-5) is generoted when the MB could
be altered by producing CARRY INSERT with the

On this pass lOPB is set, and IOP2 is produced if
MBIO is active. W hen the second l/O STROBE is
generated, another I/O RECYCLE is issued, and another pass through the delay lines occurs. On the
third pass, lOPC is set by I/O ROT, and IOP4 is producedJfAAB09_h_active. The setting of lOPC disables I/O RECYCLE; how ever, ano ther path is enabled for I/O STROBE, and l/O END is generated Time

ISZ instruction, CA INCREMENT or MEMORY INCREMENT with and 3 cycle data breaks, or the
EXAM or DEP key.
1

WC(0) generates PROTECT at the beginning of a 3-

state TS4 is entered by I/O

delay PAUSE is cleared.

cycle data break to prevent alteration of the MB.

END, and after a 300 ns

This ends the I/O cycle,

and the processor cycle is continued.
4.15

When PROTECT is active, the following events occur:

MEMORY PROTECT

ILLEGAL REF flip-flop is set by TP2,
ILLEGAL REF (0) is logically ORed with KEY SS.

When the MEM PROT key is activated, access to

This clears the RUN flip-flop at TP3.

memory addresses 7600o to 7777 q in the top memory
field is prohibited. Normally, the RIM and BIN
loader programs are stored in this memory area
When
an additional 4K of memory is added to the system,

b .

MEM ENABLE 0-4/5-1

disabled prevent-

ing a data transfer from the Sense register to the

MB.

these loaders are usually stored in the optional field
in the same area of memory, instead of in the basic

memory field.

AC ENABLE is disabled during the DCA

instruction

The protect feature ensures that no alteration of the
restricted memory area occurs, either by inadvertent
manual operation, or with program debugging/editing processes**. This feature also allows programming
use as a "read only" section of memory, when the
RIM and BIN loaders are shifted elsewhere. The
following paragraphs describe the protect circuitry
on Drawing BS-8L-0-3.

SR ENABLE is disabled for the DEP operation,

CARRY INSERT is disabled (see MEM ALT 2

previously described)

PC LOAD is disabled during the JMS instruc-

tion .

*I/0 timing references do not include transition time through logic gates, therefore timing

tolerance is ±20%.

**The MEM PROT key must be unactuated when
loading data into the restricted area of memory.

4-24

4.16

MAJOR STATES

bits

4 through

of the instruction .

The process of

address deferring is called indirect addressing because

A total of six major states are provided to perform all

access to the operand is addressed indirectly, or de-

computer operations. These states are Fetch (F),
Defer (D), Execute (E), Word Count (WC), Current
Address (CA), and Break (B) . Each major state occurs
in one complete 1 .6 [is computer cycle. The execution of a computer instruction consumes one or more
major states, depending upon the operations to be
performed. The following paragraphs describe the
relationship between the states, their functions and

ferred, to another memory location.

The Defer state can be entered only from the Fetch
state when one of the multiple-cycle instructions

AND, TAD, ISZ, DCA, JMS, or JMP is indirectly
addressed (MB03 = 1)

(F )

Under these conditions, entry

flop. It is generated by the active levels MB03 = 1
and B FETCH (1), and the inactive level fOT + OPR.

generation

Fetch

made during T4 time by TP4 in the Fetch cycle.
D SET (Drawing BS-8L-0-3) enables the DEFER flip-

- During this state an instruction is read into

If the

multiple-cycle instruction being performed is

the Sense register and the memory buffer at the address

not a JMP command, entry into the Execute state is

specified by the content of the program counter.

made from the Defer state. When the JMP instruction
performed with no BRK REQ, the instruction is
completed and the Fetch state is entered.

The

instruction is restored in core memory and retained in

the memory buffer.

The operation code of the in-

struction is transferred to the instruction register for

decoding, and the content of the program counter is
incremented by one.

Execute (E) - This state is entered for all memory
During an AND,
TAD, or ISZ instruction the content of the core memory location specified by the address portion of the
instruction is read first into the Sense register and
subsequently into the memory buffer, and the operathrough 2 of the instruction
tion specified by bits
(instruction operation code) is performed. During a
DCA instruction, the content of the accumulator is
reference instructions except JMP.

The Fetch state is entered by pressing START. The
Manual Function Time Generator is then activated,
and MFTP2 (Drawing BS-8L-0-2) is produced. This
pulse, combined with Key ST sets the FETCH flip,

flop.

transferred into the memory buffer and is stored in

The Fetch state can also be entered during T4 time,
by TP4 of a Fetch cycle or on Execute cycle. Entry

core memory at the address specified by the instruction . During a JMS instruction the content of the

occurs from a single-cycle Fetch cycle including all
of the OPR and lOT commands and the JMP command

program counter is written into the next core memory

when directly addressed. Entry nto the F etch state
occurs from the Execute cycle if BRK REQ occurs.

address and the address specified by the instruction is

When these conditions are met, F SET (Drawing

gram control

transferred into the program counter to change pro-

BS-8L-0-3)is active, enabling the FETCH flip-flop.
F SET is pr oduced when t he following sign als are
inactive
D"SET, E~SET, BREAK OK, and SPECIAL

The Execute state can be entered at the conclusion of

CYCLE

the Fetch, Defer, Execute, or Break state if there is
a PROGRAM BRK REQ, In this event the EXECUTE

If a multiple-cycle Instruction is

flip-flop is enabled by the E SET level (Drawing BS8L-0-3). Wi th a PRO GRAM BRK REQ, E SET is
generated by INT OK (Drawing BS-8L-0-7)

fetched, the follow-

ing major state will be either Defer or Execute.

The
multiple-cycle instructions include the AND, TAD,
ISZ, DCA, JMS, and the indirectly-addressed JMP
instruction. When the above instructions are directly

Entry into the Execute state can also occur from two

other methods.

One of these occurs at the conclusion

of the Fetch state when the instruction being perform-

addressed, the EXECUTE flip-flop is set; when the
instructions are indirectly addressed the DEFER flipflop is set. The following major state entry is execu-

ed is a directly-addressed multiple-cycle command.

ted by TP4 in both cases

When the signals MB03 (0) and B FETCH (1) are active
and JMP is inactive, E SET is generated enabling the
EXECUTE flip-flop.

is present in bit 3 of a memory
Defer (D) - When a
reference instruction, the Defer state is entered to
obtain the full 12-bit address of the operand from the

The other Execute-state entry method is from the
Defer state when any instruction except JMP is performed. In this event, E SET is produced by the

address in the current page or page 0, specified by

DEFER (1) level and the JMP level inactive.

4-25

The Break state immediately follows

Regardless of the source of the Execute-state entry,

same location.

the EXECUTE flip-flop is set in the previous major

the Current Address state

state during T4 by time-pulse TP4.

Since the only entry path to the Current Address state
is by progressing through the Word Count state with a

The Execute state is the last state that a multiplecycle instruction enters. At the conclusion of this
state the Fetch state is entered again except when the
PDP-8/L acknowledges a device requesting any type
of break request at this time.

3-cycle data break, the CURRENT ADDRESS flip-flop
is set during T4 time by TP4 when the WORD COUNT
flip-flop is reset (Drawing BS-8L-0-3).
Break

Word Count (WC) - This state is entered when an
external device supplies signals requesting a data

When
break and that the break is a 3-cycle break
this state occurs, a transfer word count in a core
memory location designated by the device is read into the memory buffer, incremented by 1 , and rewritten in the same location. If the word count overflows,
indicating that the desired number of data break
transfers will be enacted at the completion of the
.

current break, the computer transmits a signal to the

device.

The Current Address state immediately fol-

(B)

- This state is entered to enact a data trans-

computer core memory and an external
device, either as the only state of a 1 -cycle data
break or as the final state of a 3-cycle data break.
When a break request signal arrives and the cycle
select signal specifies a 1 -cycle (3-cycle) break,
the computer enters the Break state at the completion
of the current instruction. Information transfers occur
between the external device and a device-specified
core memory location, through the memory buffer.
When this transfer is complete, the program sequence
resumes from the point of the break . The data break
fer between

lows the Word Count state

(one or three cycle) does not affect the contents of

the accumulator, the link, or the program counter.

The Word Count state is entered at the end of each
major state excepting the Current Address or the
Word Count States when there is a request for a 3cycle data break.
durir^ T4 time.

The Break state is entered by the active B SET level
and time pulse TP4 in the final major state of the
current instruction. In this event, B SET (Drawing
BS-8L-0-3) is generated by the inactive BREAK OK

The request is acknowledged

level.

The WORD COUNT flip-flop is enabled in the
SET level (Drawing
previous major state by the
BS-8L-0-3). This level is generated by the active
3-cycle and BREAK OK levels. The WORD COUNT
flip-flop is set by time-pulse TP4 in the previous
major state.

Synchronization of the asychronous Break

signal (from the device) is done with the

BREAK

SYNC flip-flop (which is set during TPl of either a
one or three-cycle break)
Entry into the Break state also occurs when there is a
3-cycle data break. This is the last cycle of this
type of break and Break state entry is entered directly from the Current Address state. When this occurs,
B SET, generated by CURRENT ADDRESS (0) (Draw-

At the conclusion of the Word Count state, the
combination of WORD COUNT (1) and time-pulse
TP4 sets the CURRENT ADDRESS flip-flop to the one

ing BS-8L-0-3), enables the BREAK flip-flop.

This

flip-flop is set by time-pulse TP4 in the Current

state enacting Current Address entry.

Address state
Current Address (CA) - As the second cycle of a 3cycle data break, this cycle establishes the address
for the transfer that takes

At the conclusion of the Break state; the Word Count
state is entered if there is still a 3-cycle break, the
Execute state is entered if there is a program break,
and the Fetch state is reinstated if there is no longer

place in the following cycle

(Break state) . Normally the location following the
word count is read from core memory into the memory
buffer and incremented by one to establish sequential
addresses for the transfers, and also is transferred to

a break request.

the Memory Address register to determine the address

selected for the next cycle.

4.17 INTERNAL DATA FLOW

An inhibit signal (from

the data break device) can be supplied to the com-

When the content of one of the major registers (MB,
MA, AC, PC) is transferred or modified, the data flow

puter so that the word read during the cycle is not

incremented. Incrementation, if it occurs, occurs
on the transfer to the memory buffer from core memory. This word is rewritten into core memory at the

proceeds as illustrated by Figure 4-13. For ease in
understanding the data flow, the sequence of events

4-26

described in three steps:

(1)

source,

(2)

the content of the Link shifts to ACOl , ACOO shifts

route,

and (3) destination.

two places to the right (AC02), ACOl shifts to AC03

4.17.1

to the AC bits occurs with each bit.

etc.

Source

As Figure 4-13 illustrates, the 12-bit inter -register
transfers are gated into the major register network by
enable gates. The basic gating levels include: MA
ENABLE, SR ENABLE, PC ENABLE, MEM ENABLE,
and AC ENABLE. All enable gates are partially conditioned by processor or manual function time-state
levels such as TS2(1), MFTS(l), TS3(1). The enable
levels allow the data from one register to enter the
major register gating network (Drawing BS-8L-0-9)

Identical data shifting into the REG

BUS lines

When the AND instruction is performed the contents
of the MB are gated in on the lower level, bypassing
the adders. The
SHIFT signal does not gate the

contents of the MB; however, the AC is gated by this
signal.

Thus, to allow the MB data to flow to the

REG BUS lines, AND ENABLE is generated, and
applied in the same manner as the
for

NO SHIFT level,

each MB bit.

in a parallel transfer.

4.17.3 Destination

4.17.2 Route
All 12-bit inter-register data transfers enter onto the

After the contents of a register(s) ore enabled, the

REG BUS lines 00 through

data enters the major register gating network includ-

the major register gating network.

ing the adders and input to the REGister BUS lines

the data input.

after passing through

These lines are
The data on these lines is loaded
into the specified register by a c locking pulse, i.e.,

(Drawing BS-8L-0-9, all sheets). The major register
gating network consists of an upper and lower gating

if the

network and adder for each of 12 bits.

AC is the destination, the AC LOAD pulse is

generated. There are three other major-register load
pulses. They are: MB LOAD, MA LOAD, and PC
LOAD. Each load pulse occurs at the end of a processor or manual function time period by time pulses
such as TP3, TP4, and MFTPl
It should be remembered that time-state levels partially condition the
enable levels, and time pulses partially condition

The upper level gating permits the register data to
enter the adders by combining major register levels
such OS ACOO(O), DATAOO, MEM03, and other data
inputs with an enable level, or levels, depending on
the operation performed.

the load pulses

The lower level gating network includes the adder
circuitry, and logic gates for shifting operations. The
adder circuits permit propogation of carries, and provide a method of incrementing data as the ISZ, I AC,
and MA + l->-PC functions require whether or not the
operation requires a carry. The data in the upper

As Figure 4-13 illustrates, data can enter the major
register gating network from the MB (AND instruction),
MA, PC, AC, SR, the INPUT BUS, DATA BUS, DATA
ADDR BUS, or from the Sense (MEM) register. However, data transfers from the REGister BUS can flow
only to the MB, MA, PC, or AC.

gating levels passes through the adders to the lower
level gates (Drawing

BS-8L-0-9, all sheets).

When any inter-register transfer within the PDP-8/L is
performed, excepting rotate, shift operations, and the

Data flow into core memory always occurs through

AND instruction, a NO SHIFT (Drawing BS-8L-0-5)

the MB under

is generated.

NO SHIFT allows data to pass from the

adders directly through the lower level gates to the

When a shift or rotate instruc-

tion is performed, specific upper,

and lower gating

levels direct data to the adder through a particular

lower-level gate to the bus.

For example, when the

MA addressing control.

For example,

when data in the AC is transferred to core memory
(DCA instruction), the AC data transfers to the MB
through the major-register gating network. The
contents of the MB are sampled, inhibited if necessary, and written into memory.

The contents of the

MA determine the address location in which the

RTR instruction (rotate every AC and Link bit right
two places) is performed, AC ENABLE and DOUBLE
RIGHT ROTATE levels are generated (Drawing BS-

Write operation occurs.

8L-0-5). AC ENABLE allows the AC data into the
adders. DOUBLE RIGHT ROTATE directs each adder
output two places to the right. For the RTR command.

SENSE register. The data then transfers to the IR

When the contents of a

memory location are transferred to the MB, the data
flow occurs through the Sense Amplifiers into the
for decoding, and through the major register gating
network to the MB

4-27

The normal mode of PDP-8/L operation is execution

The data flow from outside the major registers to one
of them, occurs through the INPUT BUS for devices
such OS the Teletype and through the DATA, and

of a prestored programmed instruction sequence. A
program interrupt can modify programmed operation,

DATA ADDR lines for DATA BREAK devices.

or a data break can temporarily suspend programmed

operation.

A program interrupt transfers program

control from the main program to a subroutine to
effect an information transfer with an I/O device or

4.18

peripheral equipment.

OPERATING INSTRUCTIONS

A data break is an automatic

operation suspending the main program for one or
three cycles to permit a high-speed l/O device to

The following poragraphs describe in detail, the
dynamics of the computer operations.

exchange information with the core memory.

Figure 4-13

4-28

Data Flow

4.18.1

each AC bit is compared with the corresponding memory-cell bit
Only when the AC bits
corresponding to the addressed memory-cell bits are
both a 1 will the particular AC bit remain a 1 at the
end of the operation. The logical AND is therefore

Instructions

In effect,

The following explanations of the functions performed
during the execution of each instruction assume that
the PDP-8/L is energized and is operating normally
under control of the main program. Each explanation
address of the instruction is in the

The original contents of the

a transfer of binary Os.

AC are lost.

begins at the start of the Fetch cycle, when the

MA and a memory

read operation is initiated.
Instructions performed by the PDP-8/L are either

The sequence of events listed below describe the
order in which the AND instruction is enacted. The

memory reference instructions or augmented instructions. A memory reference instruction contains an
operation code

events described in a through k are common to all

through 2) and an address in
core memory at which the operation is to occur (in
bits 3 through 11), An augmented instruction is

memory-reference instructions.

(in bits

The Fetch state is always entered with all

used when the operand is already in a register such

as the AC; in this case, no memory address is requir-

instructions at the completion of the last instruc-

ed. Bits
through 2 of an augmented instruction
contain the operation code which determines the
general class of the instruction. Bits 3 through 11 of
the instruction contain information which permits the

tion performed.
is

set during

In all

cases, the FETCH flip-flop

T4 by time-pulse TP4.

b. With all instructions the functions that occur
during times Tl and T2 are the same.

required operations to occur during the two or three

execution time states of a single (Fetch) cycle.
Operations performed in this manner are said to be

c. During TS1 of the Fetch cycle, the MA is
incremented and its contents transferred to the
PC by TPl . This will provide the address of the
next instruction. The word in the currently
addressed location is also read into the Sense reg-

"microprogrammed," since several such operations

may take place during a single instruction.

4.1 8.2

Memory Reference Instructions

ister at this time

The format of a memory reference instruction appears
in Figure 4-2. With the exception of JMP, instructions which reference a memory address in page
or
in the current page occur in two cycles: Fetch and
Execute. Instructions which reference any other
page require three cycles: a Fetch cycle in which
the instruction word is brought out of memory and
contains the effective address of the operand in the
current page or page 0; a Defer cycle (refer to Direct/
Indirect Addressing in this chapter) in which the
absolute address of the operand is brought out of
memory and enters the MA; and the Execute cycle,
in which the operand is brought out of core memory
and operated on

During TS2 the word in the sense register is
ready to transfer into the MB. The Sense bits
through 2 are also enabled to the IR. Time-pulse
d.

TP2 loads the Sense bits
through 2 into the IR
and the complete word in the Sense register into
the MB. For the AND instruction, the IR will be
loaded with Os because the AND operation code
The contents of the IR (Og) produce the
is Og.
AND level. This level is used by the processor
for

input-gating control functions for this instruc-

tion .

No operations occur for the AND, TAD,ISZ,
DCA, JMS and indirectly addressed JMP.

The following explanations of memory reference
instructions assume that the instruction is directly
addressed; however, the JMP instruction is described
with direct and indirect addressing as an example.
It is also assumed that no break cycle has been initiated .

During TS4, Sense register bits 5 through

are enabled to the corresponding

MA bits, and

during time-pulse TP4 these bits are gated into
the MA.

the contents of the addressed memory cell and the

The same enabling and gating signals
through 4 and MA bits
through 4 depending on the status of MB04. This
memory buffer bit determines whether the addressed cell is on the current page (MB04 = 1), or on
page zero (MB04 = 0)
If it is on page zero,

contents of the AC .

zeroes are transferred into MAOO through

affect Sense register bits

AND - The logical AND operation occurs between

The result is stored in the AC

4-29

MA04.

tion code lo is decoded by the IR to generate the

Also during T4 the next major state entry is
g
determined by the status of MB03. If this bit
contains a 1 , indirect addressing is indicated and
.

the DEFER flip-flop is set by TP4.

TAD gating level used by the processor to implement
the TAD operations.

The actual two's complement
add is performed in the Execute cycle in the following sequence

If this bit

contains a 0, direct addressing occurs and TP4 sets
the EXECUTE flip-flop. Only one major statecan
be entered at any time. The state entered depends on the input-gating of each major state
controlling flip-flop during TS4.

During the memory strobe portion (Tl) of the
Execute cycle, the addend reads into the Sense
register from the addressed memory cell

a .

Towards the end of the processor cycle, the

During T2 the operand in the Sense register

memory Write function occurs and the instruction is written back into core memory. When this

transferred to the MB and IR for processing

and decoding

done, MEM DONE is generated, and TP4 is
produced initiating another processor cycle and
clearing TS4, MEM DONE also enables another
memory cycle to be initiated.

During T3 the MB and AC outputs are enabled
and applied to the major register input gating network. Carries are generated and propogated in
the adders as required. Time pulse TP3 allows
generation of an AC LOAD pulse during the
AC LOAD
Execute cycle of the TAD instruction
transfers the sum of the AC and MB into the AC
c .

During the strobe portion of the Execute cycle,

the operand stored at the address currently held by

the

MA reads into the Sense register.

At TP2 the

operand transfers to the MB.
During the Write portion of the memory cycle the
operand in the MB is rewritten into the original
address cell
If there is no break request and SKIP =
0, the contents of the PC are loaded into the MA at
this time by TP4. This time pulse also clears the IR
and sets the FETCH flip-flop.

During TS3 the AND ENABLE level permits
the AND-combining of the AC and MB through the
j.

major register gating network.

Time-pulse TP3
sets the AC bits whose register inputs are active
(high), and clears the other AC bits.

This concludes the TAD instruction; the program is
ready to fetch the next instruction from the location
specified by the contents of the MA.

k . Toward the end of the Execute cycle the
operand, which is unaltered in the AND process,
is rewritten into memory during the Write portion
of the memory cycle. The operand of other
instructions such as the DCA, JMS, and ISZ is
altered before it is rewritten.

If there is

Increment and Skip if Zero (ISZ) - The ISZ instruction
reads the contents of the addressed memory cell into
the Sense register, and transfers the contents of this
register through the major register gating network with
a carry insert to the MB. If the incremented contents
of the MB are not 0, the program proceeds to the next

no break request and SKIP = 0, the

contents of the PC are loaded into the

Execute T4 time by TP4.

MA during

This time pulse also

incremented contents of the MB

clears the IR and sets the FETCH flip-flop. This

instruction.

concludes the logical AND operation; the program
is ready to fetch the next instruction from the

are equal to 0, the contents of the PC increment by

location specified by the contents of the MA.

events that occur in performing the ISZ instruction

1 ,

If the

and the program skips the next instruction.

The

are listed in sequence below.

Operations during the Fetch cycle of an ISZ

Two's Complement Add (TAD) - The contents of the
addressed memory cell add to the contents of the

AC in 2s complement arithmetic

cycle of an AND instruction . Refer to events a
through h of the AND instruction. The only difference between these two instructions during the
Fetch cycle is the operation code 2p decoded by
the IR for the ISZ instruction.

The result of the
addition is stored in the AC, and the operand (addend)
The original contents of the
is restored to memory.
.

AC are lost.
During the Fetch cycle, the TAD instruction operates
in the same manner as the

AND instruction.

events a through h for these operations.

instruction are similar to those during the Fetch

During Tl of the Execute cycle, the word at

the memory location signified by the contents of

Refer to

The opera-

the

4-30

transferred into the Sense register.

c .

During T2 of the Execute cycle the Sense reg-

ister is transferred to the

The levels TSl(l), DCA, and B EXECUTE (1) combine
to generate AC ENABLE during T2. This allows the

MB through the major

contents of the AC to transfer through the major reg-

ister gating bus to the

MB.

level to the adder of the least significant bit

during the transfer operation.

At the end of T2, time-pulse TP2 generates an MB

If the carry insert

level produces a carry out from the most signifi-

LOAD pulse that allows the contents from the AC to

cant bit, indicating an all

be loaded into the MB.

condition in the

d. No event occurs during T3 of the Execute
cycle. However, if the SKIP flip-flop has been
set, the

MA.

PC is incremented and transferred to the

During T3, time-pulse TP3 generates an AC

LOAD pulse; however, no enable levels are

This causes the next sequential instruction

to be skipped during T4.

If the SKIP flip-flop
was not set, the contents of the PC are transferred
to the MA without incrementation, resulting in a

generated. This lack of enable levels places
the equivalent of all Os on the input to the
major register gating network. The AC LOAD

skipping

pulse therefore, loads these Os into the AC,

effectively clearing the register.

During the memory Write portion of the

memory cycle the incremented contents of the

e. During the Write portion of the memory cycle
the contents of the MB are written into the core

MB are written into the address cell from which

location specified by the AM.

they were removed

During T4, if

neither a break request not a skip =
f.

Time-pulse TP4 (at the end of TS4) sets the

level

present, the contents of the PC are transferred to

FETCH flip-flop if there is no break request.

the

MA to specify the next desired core location.

Time pulse TP4 sets the FETCH flip-flop allowing
entry into the Fetch cycle.
Deposit and Clear Accumulator (DCA) - The DCA

AC into the
addressed memory cell and the AC clears. The origininstruction deposits the contents of the

Jump to Subroutine (JMS) - The JMS instruction

al contents of the addressed cell are destroyed.

The
sequence of events that occur in performing the DCA
instruction are listed below.

provides an exit from the main program into a subroutine.

The contents of the PC (current program

count) incremented by 1 , are written into the core

memory address specified by the JMS instruction.
That address transfers to the PC and increments by 1;
a .

Operations during the Fetch cycle of a DCA

this

incremented address fetches the first subroutine

instruction are similar to those occurring during

instruction during the next instruction cycle.

AND instruction. Refer to
events a through h of the AND instruction. The

the subroutine ends, the main program is re-entered

the Fetch cycle of the

by a jump indirect to the address specified by the
JMS instruction. The contents of that
address are now the incremented main-program count;
and transferring this count into the PC causes the
main program sequence to continue.

operation code for the two instructions differs.

original

The operation code 3q decoded by the IR for the
DCA command generates a DCA level which is
used as a gate-enable signal for this instruction.
b.

When

The sequence of events in performing the JMS instruc-

During T4 of the Fetch cycle the EXECUTE

tion are listed below.

flip-flop is set to allow entry into this state.

In addition, to further clarify

the JMS operation, a sample programwith thisinstrucc .

During T2 of the Execute cycle, the

DCA

tion is given in Table 4-1 .

level combined with B EXECUTE (1) inhibits

MEM ENABLE 0-4/5-1 1 . This prevents the
contents of the Sense register from transferring
to the MB.

Therefore, the contents of the
addressed cell are lost.

a .

Operations during the Fetch cycle of a JMS

instruction are similar to those occurring during

4-31

the Fetch cycle of the

AND instruction. Refer
AND instruction

to events a through h of the

b. During TSl of the Fetch cycle for instruction
2I3, the contents of cell D21g reads into the
Sense register. Upon completion of the Read

The operation code for the two instructions
differ. The operation code 4g decoded by the
IR for the JMS command generates a JMS level
which is used as a gate-enable level for this

operation the Sense register contains JMS/0/100
(4100g).

instruction.

b .

During Tl of the Execute cycle no operations

occur.
c .

During T2 of the Execute cycle the contents

of the PC ore transferred to the MB if there is

The JMS operation code 43 is in bits 00 through 02;
(denoting a direct
page
is specified by bit 03 =
(denoting page 0). Bits 05
address) and bit 4 =
through 11 specify location lOOg (of page 0). Also
during TSl the contents of the MA increments as it
transfers into the PC.

no skip condition (SKIP = 0) . In order to perform
this operation, PC ENABLE and MB LOAD are
generated.

c .

During T2, the contents of the Sense register

(the JMS instruction) transfers into the MB.

PC ENABLE allows the contents of

Bits

00 through 02 transfer into the IR where they are
decoded to produce the JMS level.

the PC to enter the major register bus. The
contents of the bus are loaded by MB LOAD into
the MB,

d.
d.

e. During T4 of the JMS Fetch cycle, the
contents of the MB (the JMS instruction) is
written back into its original core location (D2I3).

To do this, the
by one and transferred to the PC
MA ENABLE, CARRY INSERT, and PC LOAD
signals are generated. MA ENABLE allows the
contents of the MA to enter the major register
network bus
CARRY INSERT adds one to the
.

f .

contents of the bus.

Finally,

At TP4, the contents of bits 05 through 1

are transferred to the corresponding bits of the

PC LOAD loads the

MA and, because bit MB04 = 0, bits MAOO
through 04 are cleared to indicate page 0. The
MA now contains (0/100)3, the address specified

PC with the incremented contents of the bus.
e.

No operations occur during TS3.

During T3, the current address is incremented

During the Write portion of the memory cycle,

by the JMS instruction.

the contents of the MB (described in event c of
this instruction) are written into memory at the

location specified by the JMS instruction.

During Tl of the JMS Execute cycle, the

contents of core location (O/IOO3), as specified
f .

During T4 the FETCH flip-flop is set by TP4
neither a break request nor a SKIP = 1

by the address portion of the JMS instruction,

now in the MA), reads into the Sense

if there is

(which

level

h. During T2 of the JMS Execute cycle, the
content5 of the PC, which is D/22g, (address of
the next sequential main-program instruction)

The events above describe the JMS operation. These
events are easier to understand, however, if a concrete example is given. The following events desThe program
cribe the sample program of Table 4-1
sequence assumes that the main program is in page D

transfers into the MB.

The SKIP flip-flop is

assumed cleared

of memory (current page), and that the 21st instruction is JMS directly page

During T3, the contents of the MA, (0/1 OOs),

which is the current subroutine address, is incremented by one as it is transferred to the PC.

The
following conditions are also assumed for this example: memory pages are designated 0, A, B, C,
D, E; each page contains locations designated
starting
through 77©; and the subroutine is in page
at location TOlg.
location IOOq.

During T4, the contents of the MB (D/223)

are written into memory location (O/lOOn).

TP4, the contents of the PC (O/lOlg) transfer to
the MA to select the core memory location containing the first active instruction of the subroutine. At this time, the JMS Execute cycle is
terminated and the Fetch cycle of the first instruction of the subroutine entered.

During T4 of instruction 2O3 in the main
program, the PC contains the address of the
next instruction, location 213 in page D (current
page). This address is transferred into the MA.
a .

4-32

main-program instruction (D/22_).

During Tl of the Fetch cycle, the first Instruc-

(0/1 01 8) into the Sense register.

By this means

the subroutine is terminated ancTthe main prcsgram
re-entered at the point at which it was interrupted.

tion of the subroutine reads from core location

The program then

proceeds to execute the subroutine.

The last instruction of the subroutine must be a
jump indirect to the location originally specified
by the JMS instruction, in this case (0/1 OOg). As
noted in step above, location (0/1 OOg) contains
I

the address in core memory of the next sequential

Jump (J MP) - The J MP instruction links two program
instructions that are executed consecutively when the
instructions are not in sequential locations.

This

instruction is commonly used to link a program to-

gether when the program length extends over more

Table 4-1
Example of Register Contents During JMS Instruction

PC Contents
Cycle

Fetch or

Time

0-4

5-n

(page)

(location)

TS4

D/20 Unknown

D/21

MB Contents

MA Contents

0-4

5-11

Unknown

5-11

Command

PC -MA

MA+1 -PC

Execute
Fetch

TS1

JMS/0/100

Unknown

Memory -ME
TS2

D/21

JMS/0/100

MEM-M
MEM-1

TS3

No Operations

TS4

D/21

JM5/0/100

JMS/0/100

MB-Memory

MEM-MA
1-E

Execute

TS1

0/1 00

xxx/x/xxx

TS2
TS3

0/100
0/100

xxx/x/xxx

0/101

D
D

22
22

100

Memory -MB

100
100

PC-MB

MB-MEM
MA+1 -PC

TS4

0/100

0/101

100

MB-MEM
PC-MA
1-F

Fetch

TS1

102

0/101

1st subroutine

instruction

4-33

101

AAA+1-

Memory —

JMP

than one page (177q locations) of core memory.
is also

For an indirectly addressed JMP during T4,

05 through 1 1 of the Sense register transfer
MA and bit 04
(absolute
of the MB is examined
If MB04 =

extensively used in program loops such as

bits

to the corresponding bits of the

counting and comparing in conjunction with the skip
instructions.

address of operand on page 0) MAOO through

MA04 are cleared. If MB04 =

The JMP instruction contains either the absolute corememory address of the next operand (direct addressing)
or the address of a location containing the absolute
core-memory address of the next operand (indirect
addressing). When the next operand is located either
in the current page or page zero of memory, direct
addressing is used requiring only a single fetch cycle
to extract the operand and prepare for its execution.
If, however, the next operand is located in any other
page in memory, its 12-bit absolute address must be
stored in either the current page or page zero at a location specified by bits 05-1 of the JMP instruction.

of the

MA (current page address) are circulated
MA bits. Also

out of, and back into, the same

during T4, the JMP instruction is restored, intact,
in its original core

memory location. At the end

of T4 the DEFER flip-flop is set allowing entry
into the Defer state.

The following events relate to the JMP instruction when the Defer state is entered.

This state

can be entered with any of the memory reference
instructions and is not restricted to JMP instruc-

This is known as indirect addressing,

(absolute address

of operand on current page) bits 00 through 04 of

and requires

both a Fetch cycle and a Defer cycle to extract the

tion exclusively.

operand for processing.
e.

The events that occur in performing the JMP instruction are listed in sequence below,

During Tl of the Defer cycle, the absolute

12-bit address of the operand is read from the

memory location specified by the JMP instruction (or any of the memory reference instruction^

Operations occurring during Tl and T2 of the

into the Sense register.

JMP Fetch cycle are identical to those events of
the AND instruction in the same time periods

except for the operation code Ss decoded by the

are transferred to the MB if an Auto Index is not

IR for the JMP instruction.

Refer to events a

During T2, the contents of the Sense register

required.

When there is an Auto Index, the

through d of the AND instruction.

contents of Sense are incremented by 1 in the

Operations during T3 of the Fetch cycle
depend upon whether the JMP specifies direct
(MB03 = 0) or indirect (MB03 = 1) addressing.

the MB.

major register gating network before loading into

If direct addressing is

indirectly addressed in one of the locations

lOo through 17q on page zero of memory.

indirect addressing is indicated no operationsoccur

during T3.

An Auto Index occurs when a memory

reference instruction such as the JMP command

indicated, the
g . During T3 the contents of the Sense register
are transferred to the PC (intact if an Auto Index

specified address (SENSE 05 through 11) is loaded
into the corresponding bits of the PC.

If the

in-

is not specified, and incremented by one if an
Auto Index is specified).

struction specifies that the operand is located on

(MB04 = 0), bits 00 through 04 of the PC
If, however, the instruction specifies that the operand is in the current page (MB04=
1) bits 00 through 04 of the MA are transferred to
the corresponding bits of the PC.
page

are cleared.

c .

h .

During T4 if no break request is specified, the

contents of the PC are transferred to the MA. Also
during T4 the contents of the MB are written back
into memory at the original location (intact if

Auto Index was not performed, or incremented by
1
At the end of T4
if Auto Index was performed)

The following events occur during T4 of the

Fetch cycle of a direct address. JMP (if neither
a break request nor a skip is specified):

the FETCH flip-flop is set allowing Fetch cycle
entry for the next instruction performed.

During

the ensuing Fetch cycle the operand is read from

memory and its operations begun.
The PC transfers to the MA, the JMP instruction
is

restored intact, to its original core memory

location, and the FETCH flip-flop is set.

4,18.3 Direct/Indirect Addressing

The

operand is removed from core-memory during the
next machine cycle (Fetch) and implemented.

Six of the eight basic instructions in the PDP-8/L
repertoire are designated as memory-reference instruc-

4-34

These insfrucf-ions (AND, TAD, ISZ, DCA,
JMP, and JMS), as part of their function either write

transferred to the MA.

into or read from memory.

a 1 , bits

Hons,

extracted from memory, only bits 5 through

11 are

If bit 4 of the instruction

through 4 of the

MA are left unchanged

and the next location addressed is on the current page.
If, however, bit 4 is a 0, bits
through 4 of the MA

The first three bits (0-2) of these 12-bit instructions
contain the operation code designating the specific
function to be performed. The remaining nine bits

are cleared.
tion on page

This addresses the bit 5 through

loca-

of the memory.

(3-11) are, therefore,available to specify the memory

location involved in the required operation.

A com-

Figure 4-14 is a simplified flow chart showing the
sequence of operation of both the direct and indirect

plete specification of any one of the 4096 locations
in the basic

PDP-8/L memory, however, requires the

use of 12 address bits (2

= 4096).

addressing functions.

To minimize the

number of instructions required to access memory,
therefore, both direct and indirect addressing is used
in the

4.1 8,4 Augmented Instructions

PDP-8/L.
The two classes of augmented instructions used in the
PDP-8/L are: The input/output transfer (lOT) which
has the operation code 6g and the operate instruction
(OPR), which has the operation code 7_. Augmented

The memory is organized into 32 pages (or blocks),
each containing 128 consecutive memory locations.
These pages are numbered
through 37^,. The specification of any of the 128 locations on a particular
page requires only seven bits (2' = 128). Bits 5

instructions are single-cycle (Fetch) instructions

which initiate various operations as a function of bit
mi croprogrammi ng

through 11 of the memory-reference instructions are
used for this purpose.
carried in bits

With the operation code

through 2, bits 3 and 4 remain to

specify the direct/indirect addressing

Input/Output Transfer - The lOT class of augmented
instructions generate pulses (lOP pulses) that allow

mode of opera-

tion .

the PDP-8/L processor to communicate with both the

The status of bit 3 of the instruction specifies whether
direct or indirect addressing is to be performed. When
bit 3 =

direct addressing is specified, i .e., the

location specified in bits 5 through

1 1

fer f uncti ons

The format of the lOT instructions differs from that of
the memory reference instructions as illustrated in

Figure 4-2. Bits-OO through 02 contain the operation
code (63), bifs 03 through 08 form a code that enables
device selector circuitry in a given I/O device, and
bits 09 through
enable the generation of lOP pulses
1
which control the data transfer, clearing, and sync-

addressing is specified, i.e., the location specified
1 1

contains the absolute 12-bit

address of the operand.

control applications, synchronization, and data trans-

contains the

operand upon which the function described in bits
through 2 is to be performed. If bit 3 = 1 indirect
in bits 5 through

internal and external devices. The lOP pulses generated by performing this instruction are used for timing,

An additional computer cycle

(Defer) is therefore required to extract the 12-bit

address of the operand from the specified address.

chronization operations.

The status of bit 4 determines whether the location

The following events describe the operation of the

specified by bits 5 through 11

lOT instructions

on the currently
addressed page of memory, or on page
(1 = current
=
Through
the
use
of
bit
page
page,
0)
4, therefore, a memory reference instruction can address 256
locations; 128 in the current page, and 128 in pageO.
is

a. Operations during Tl and T2 of the lOT
Fetch cycle are identical to events a through d

of the

AND instruction, except for the operation

address of the desired location must be present in the

code 6g decoded by the IR for lOT instructions
during T2. The resulting IR generated lOT level
is used in lOP generation and other processor

MA to permit access to that location.

control functions.

should be noted that the full, 12-bit absolute

The 12-bit
program is entered into the MA
through the switch register and the LOAD ADDR key
when programmed operation commences. In normal
operation, the PC is incremented during each Fetch
starting address of the

At the end of TS3 of the Fetch cycle, TP3
PAUSE flip-flop and triggers the lOP
generator. The processor timing sequence is
interrupted between T3 and T4 to allow the I/O
b.

sets the

cycle to step the address to the next sequential memory location. When a memory reference instruction

cycle to occur

4-35

LOAD STARTING
ADDRESS Y

—» PCO-11)

(SRO-11

RETRIEVE FIRST
INSTRUCTION FROM

Y AND SET INTO MB

SET OP CODE

INTO

[SENSE 0-2*IRO-2)

SET

EFFECTIVE

ADDRESS OF OPERAND

ADDRESS OF

(Z) INTO

OPERAND

MA (SENSE

5-11-* MA5-11)

SELECT CURRENT
PAGE (MAO -5
NOT CHANGED)

SET DEFER
STATE
i__

ABSOLUTE
ADDRESS
RETRIEVAL

»>

YES

<^l>
\
NO

RETRIEVE ABSOLUTE
ADDRESS (X) OF OPERAND
FROM LOCATION Z IN PAGED
OR CURRENT PAGE

SET EXECUTE
STATE

SET ADDRESS OF

OPERAND [XI INTO MA
(SENSED- n-<-MAO-in

1
SET

EXECUTE
STATE
RETRIEVE OPERAND
FROM LOCATION Z
IN
PAGE
OR
CURRENT PAGE
'

RETRIEVAL

RETRIEVE OPERAND
FROM LOCATION X
(MAY BE IN
ANY PAGE)

EXECUTE THE
INSTRUCTION

ON OPERAND

1
SET ADDRESS OF
NEXT INSTRUCTION
INTO MA
(Y + 1)
(PCO-n
»MA0-1I1

—

1
SET FETCH
STATE

1
INCREMENT PC
(NOW HOLDS Y +2}

1
RETRIEVE SECOND
INSTRUCTION FROM
LOCATION Y+
1

Figure 4-14

Direct and Indirect Address Selection,
Simplified Flovi' Chart

4-36

c. During the I/O cycle specific lOP pulses
are generated depending on the status of bits

MB09 through MBH

tion, when set to 1 specifies an RAR (rotate AC and
L to the right one place) operation.

specifies an

Bit

09 similarly

RAL (rotate AC and L to the left one

place) operation. It is physically possible, by setting
both bit 09 and 08 to the 1 state, to request an im-

Any lOP pulses that are generated are gated
in the device selector of the addressed I/O device
to produce lOT pulses. The lOT pulses control
d.

possible, conflicting operation,
L both right and left one

the operation of the device, effect a transfer of

.e., rotate AC and

place simultaneously.

information between the device and processor, or
Both groups of OPR microinstructions are single-cycle

initiate action in the processor such as clearing

the AC, or incrementing the PC.

(Fetch) instructions. The following sequence of events
describe the operations of this class of instructions.

In addition,

with each lOP pulse generated, l/O STROBE is

The instruction descriptions contain the primary signals

produced and used within the processor to allow
AC LOAD (Drawing BS-8L-0-6) to clock data
from the l/O device into the AC.

necessary to perform the specified operations.

Refer-

ence to the mechanization charts indicates where and
how the primary signals are generated.

Certain lOT instructions are normally combined
to clear the

For ease of explanation, the signals and conditions

lator in

common to most of the OPR instructions are listed be-

AC and transfer data to the accumuone computer cycle. This is performed

low

by generating AC LOAD as described above, and
disabling A C ENABLE (Drawing BS-8L-0-4),
AC CLEAR (Drawing BS-8L-0-4), gated by I/O

The operation code is 7q.

Actual AC and L operations occur during T3

STROBE, disables AC ENABLE, thus Os are loaded
into each AC bit when l/O STROBE occurs.

Dur-

of the Fetch cycle.

lOP 2 or 4, time data is loaded into the AC by
I/O STROBE
ing

The OPR level decoded by the IR serves as
an enabling level, and also combines with MB03
c .

Two lOT instructions used with the PDP-8/L

to form OPl

and OP2 levels.

to enable/disable the program interrupt facility.

These instructions ION (dOOlg), and lOF (6002g)
are processor lOT instructions.

When ION is

Time pulse TP3 generates the load signals

such as AC

performed, the program interrupt facility is enabled by setting the INT ENABLE flip-flop. lOF

LOAD, that perform the transfer of

data from the major register gating network to

the indicated register.

disables the program interrupt facility by ensuring that the INT ENABLE flip-flop is cleared.

e. The ma [or state B FETCH (1) and time-state
TS3 signals are used as enabling levels.

Operate (OPR) - The OPR class of augmented instructions consists of two categories of microinstructions

Group

Except for the rotate OPR 1 instructions, the
is generated to allow all transfers from the adder of the major register gating
network onto the network bus.
f.

NO SHIFT signal

and Group 2. The formats of these groups
appear in Figures 4-4 and 4-5, respectively. In each
case, bits 00 through 02 contain the operation code
commands, designated by a
in bit 03,
7g. Group
1

are called OPR

instructions.

OPR

instructions

perform AC and Link operations such as clearing,

complementing, rotating, and incrementing.
in bit 03 and a
2, designated by a
in bit

NOP Instruction

(7000o); however, each bit Is discussed in order.
Therefore, several events occur when this in-

Group

are
These commands check
the contents of the AC and Link, and on the basis of
the results, determines whether the next sequential
instruction is to be performed or skipped.
1

There is only one OPR 1

struction is performed.

1 1

called OPR 2 instructions.

The OPR instructions and their operations are
described below.
a

The OPR

operations may occur either singularly or

During Tl and T2 of the Fetch cycle the

operations, that occur are identical to events

combinations. Care must be exercised,
however, to ensure that contradictory or conflicting
operations are not specified within the same instruction. For example, bit 08 of the OPR
microinstrucin logical

a through d of the

AND instruction.

During T3 bit 03 of the OPR instruction is
examined to determine whether the instruction
b.

4-37

is an OPR 1 (MB03 = 0) or an OPR 2 (MB03 =1).
Appropriate levels are generated in the control
circuits to implement the requirements of each

group.

NOP (no operation). When the 70008 in-

(5)

struction is performed,

MB05 = 0, MB07 = 0,

and no other operand_exists (refer to instruction
description 1)
The L -» L circulation occurs and

The descriptions of the instructions that

the contents of the Link are circulated through
the major register gating network and returned

follow should be carefully traced in the flow
chart (Drawing BS-8L-0-1) to facilitate under-

unaltered to the Link.

standing of the system operation. The order of
appearance of the instruction descriptions parol lels the order shown in the flow diagram. It
should be noted that, through microprogramming,
operations may be combined during the same
cycle. For instance; AC -*AC (CMA) and L -*L
(CML) may occur in the same instruction to complement both the AC and the Link

the L ENABLE, AC

This transfer occurs when

LOAD, and NO SHIFT

signals are generated.

CML (complement the Link). When the
(6)
70208 '"struction is performed, MB05 =0,
MB07 = 1 , and no other operand exists . The
side of the Link bit (L) transfers through the

major register gating network into the Link

During T3 when the OPR 1 instructions are
specified (MB03 = 0) the following instructions
c.

- L)

This transfer occurs when L ENABLE,

AC LOAD, and NO SHIFT levels are generated.

can be performed. They are:

NOP (no operation). When the 70008 in-

(1)

struction is performed,

(7)

CLL (clear the Link). When the 71008 in-

MB05 = , with no other
level is transferred
and a logic
to the Link. The operation is performed by generating AC LOAD and NO SHIFT signals with
no enable levels existing.

struction is peformed,

MB04 = 0, MB06 - 0,and

operand exists,

The contents of the AC
ore circulated through the major register and

no other operand exists.

odder network, and returned unaltered to the
AC (AC -* AC) . This transfer occurs when AC
SHIFT are generENABLE, AC LOAD, and
in
5 and 9 of the
The
events
described
ated
OPR 1 instructions also occur simultaneously

(8)

CAAA (complement the AC)

7040p instruction is performed,

When the 71200 inMB07 = and
MB05 =
1 ,

no other operand exists, the combined operations
of the CML and CLL instructions described in
The Link is set
6 and 7 above occur (L + L L)
state by clearing it, then complemento the

with the AC circulation.
(2)

STL (set the Link).

struction is performed,

When the
MB04 = 0,

MBOo = 1, and no othej^ operand exists. The

ting it.

AC bits (AC) is transferred through
he m ajor register gating network to the AC
This tronsfer occurs when the AC
(AC * AC)
ENABLE, NO SHIFT and AC LOAD signals are
side of all

(9)

MB08 = 0, MB09 = 0,

and no other operand exists.

In addition to the

1
and 5,
generated. This level
controls transfers of all data from the adder onto
the major register bus. This signal is generated
for all OPR 1 instructions, and is gated by
MB08 = 0, and MB09 = 0. It should be noted

events described for this instruction in

generated

the

CLA (clear the AC). When the 72008
MB06 = 0,

(3)

NOP (no operation). When the 7000g in-

struction is performed,

instruction is performed MB04 = 1 ,

and no other operand exists, logic
transferred to all AC bits.

levels are

This transfer occurs

by producing AC LOAD and NO SHIFT levels,
with no-enable levels existing.

NO SHIFT level

that the

NO SHIFT signal

also generated for

except for the EAE shift group,
but there is a different path activated.

all instructions

This operation

clears (sets all bits to 0) the AC register (0 -*

AC).
(10)

CLA/CMA (clear and complement the AC)

(4)

When the 7240q instruction is performed MB04 =
and no other operand exis ts. The
MB06 =
1

ed,

-»

)

When the 7010o instruction is performMB08 = , and no other operand exists.
1

The contents of the AC and L are shifted one
bit to the right. The Link status is transferred
into ACOO, while ACl 1 status transfers into the
Link. The RAR operation occurs when the L
ENABLE, AC ENABLE, RIGHT SHIFT and AC
LOAD signals are generated.

AC is cleared then complemented (AC + AC
AC set AC = -1 This effectively sets all of
sta te
This operation occurs
the AC bits to the
when the AC ENABLE, AC ENABLE, NO SHIFT
and AC LOAD signals are generated.
,

RAR (rotate the AC and Link right one

place).

4-38

(11)

RAL (rotate AC and the Link left one

The operations performed during T1 and T2 of the Fetch
cycle of the OPR 2 class of instructions are identical

When the 7004^ instruction is performed, MB09 =
and no other operand exists.
place) .

to those previously described for those time states in

The contents of the AC and Link are shifted one
bit to the left. The content of ACOO is transferred to the Link, and the content of the Link
bit is transferred to ACl 1 . The RAL operation
is performed when LEFT SHIFT, L ENABLE,
AC ENABLE, and AC LOAD signals are generated.
(12)

the

during T3 of the Fetch cycle.

(1)

SZA (skip on zero AC). When the 74408

instruction is performed MB06 = 1 and no other

operand exists. The contents of the AC register
are checked and if the AC = 0, the next se-

RTR and RTL (double rotate, right or left).

the AC = 0, the SKIP flip-flop is set to the one

the operand for either the RAR or RAL instruc-

state by TP3, B FETCH (1),

tion exists. However, to avoid confliciting
operations, only one of these operands should

of all AC 0-side outputs.

exist at one time.

OPR, and a skipenable level generated by AND-combination

The RTR command rotates

the contents of the AC and Link two places to

(2)

SMA (skip on minus AC)

When the 7500g

performed MB05 = 1 and no other
operand exists. The content of ACOO is sensed
to determine its status. If ACOO = 1 , a minus
instruction

Similarly, the RTL command rotates

the right.

When

quential program instruction is skipped.

When the 70128 instruction (RTR) or the 70063
instruction (RTL) is performed, MBlO =
and
1

AND

instruction. The following instruction
descriptions therefore, describe the OPR 2 instructions

the contents of the AC and Link two places to
the left.

AC is specified, the SKIP flip-flop is set, and
Both the RTR and RTL instructions occur when

the next sequential program instruction is skip-

AC ENABLE, DOUBLE RIGHT
ROTATE or DOUBLE LEFT ROTATE, and AC
LOAD are generated.

ped. This flip-flop is set by a load pulse generated by the TP3, B FETCH (1) and OPR signals.

L ENABLE,

The skip-enable level is produced by MB05 (1)

combined with ACOO (1).
(13)

lAC (increment the AC). When the

SNL (skip on non-zero Link). When the
(3)
74208 instruction is performed, MB07 = and
no other operand exists. The Link bit is sensed
to determine whether it is in the
state, and if
it is, the next sequential program instruction is
skipped. The SKIP flip-flop is enabled by
LINK (1), and MB07 (1), and set by the combination of TP3,"B FETCH (1), and OPR signals.

7001p instruction is performed, MBll = and
no other operand exists. The AC is incremented
by 1 , by transferring the contents of the AC to
the major register gating network, adding a
logic
through the network adder, and transferring the incremented contents into the AC.
The AC ENABLE, AC LOAD, and CARRY INSERT signals are generated to perform this in1

struction.
(4)

MB08 = , and no other
operand exists. The next sequential instruction
is skipped regardless of the contents of the AC
and Link. The SKIP flip-flop is enabled by
MB08(1), MBl 1(0), and OP2; it is set by the
combination of TP3, B FETCH (1), and OPR.

The lAC command can be combined with either

CMA commands to perform the

the CLA or

When the
CLA/tAC instruction or the CIA (lAC/CMA)
functions of both during one cycle.

instruction is performed, the operations of both
separate instructions are performed simultaneously, during

SKP (skip unconditonaily). Whenthe74108

instruction is performed,

the OPR 2 group of

When one of the SZA, SMA, or SNL operands
is combined with MB08 (1), reverse sense skipping occurs, i.e., SZA becomes SNA (skip on
non-zero AC, 7450g) SMA becomes SPA (skip
on plus AC, 75103), and SNL becomes SZL (skip

These microinstructions

on zero Link,7430g).

When NAB03 =

and MBl 1 =

microinstructions is specified.

may be performed singly or in useful logical combinations. The available commands include: CLA, HLT,
OSR, and seven skip instructions dependent upon the
status of the

AC and/or Link

(5)

HLT (halt operation). When the 74028 is

performed, MBIO = 1 and no other operand
exists.

4-39

This operation clears the

RUN flip-flop.

inhibiting the generation of a

the OSR and CLA may be made resulting in the
LAS (load the AC with the contents of the SR)

MEM START level

which prevents the start of another machine
cycle. The computer stops after T4 time.

(8)

NOP (no operation)

instruction is performed,

OSR (inclusive OR between the SR and AC).
When the 7404g instruction is performed,
and no other operand exists. The
MB09 =

other operand exists.

(6)

for the

When the 74008
and no
MB03 =
1 ,

The same events described

NOP conditions of the OPRl instruction

descriptions

1 ,

5, and 9 occur.

result of the inclusive OR remains in the AC

The OSR operation occurs when the AC ENABLE, AC LOAD, SR ENABLE, and NO SHIFT
signals are generated.

CLA (clear the AC). When the 7600g
and no other
instruction is performed MB09 =
(7)

The OPR2 instructions listed above may be logically

combined to perform more than one operation in a
single Fetch cycle. Examples of two of the combined
microinstructions are listed below; however, many
other useful combinations exist.

operand exists. The AC is loaded to all Os
This Instruction is identical to the
(0 - AC)

(1)

OPR J CLA instruction with the exception of
the OP 2 and MB04 levels. The CLA instruction

SZA CLA (76408)

•

When this instruction

performed, the content of the AC is sensed.
If each AC bit is a binary 0, the next instruction is skipped and the AC is cleared.
is

(OPR 2) exists in order to combine with

SNA SZL (74708). ^'^^" *^'^ instruction
performed the next sequential instruction is
and the Li nk = .
ski pped f both the AC =

the OPR 2 microinstructions.

As a result the
AC can be cleared after it is sensed by one of
the skip instructions, or combination between

(2)

4-40

CHAPTER 5
MAINTENANCE

This chapter contains information pertinent to preven-

5.1

EQUIPMENT

tive maintenance, corrective maintenance, and

troubleshooting techniques for the PDP-8/L,

Table 5-1

lists

the equipment and relevant specifica-

tions needed for maintenance of the basic PDP-8/L.

Also included is the actual equipment used by Digital
Equipment Corporation field service personnel.

Table 5-1

Maintenance Equipment

Equi pment

Specifications

Model or Type

Multimeter

lOK ohms/volt-20K ohms/volt

Triplett

Osci loscope

dc to 50 mc with calibrated
deflection factors from 5 mV
to lOV/div. Maximum horizontal sweep rate of 0.1 fis/div.
Delaying sweep is desirable and

Tektronix Type 453

Model 310

dual trace is a necessity.
Probes

XI with response characteristics
matched to oscilloscope

Tektronix Type P6010

2 mA/mV or 10 mA/mV

with passive terminator

Clip-on
current probe

Tektronix Type P6019

Recessed

Tektronix

Probe Tip

Unwrapping

Gardner-Denver
505-244-475

tool

Wire -Wrap
tool

Gardner-Denver
A-20557-29

30 gauge bit
for wrap tool

504221

Gardner-Denver

Sleeve for 30

Gardner- Denver
500350

gouge bit
Spray paint

Krylon 1501
Glossy white

5-1

Table 5-1

Maintenance Equipment (cont.)
Equipment

Model or Type

Specifications

Spray paint

DEC black

Module

DEC No. W982

Extender (2)
Assorted lengths affixed

Jumper Wires

with 30 gauge termi -point

connectors

5.2

PROGRAMS

Table 5-2 lists the Maintenance Programs supplied
by DEC for ascertaining proper operation of the

PDP-8/L.

Table 5-2

Maintenance Programs*
DEC Number

Program Name
Instruction Test

MAINDEC8I-D01B

Use
Tests

AND, TAD, and Operate

Instructions only

Instruction Test 2

MAINDEC 8I-D02B

Extensive test of Auto Index,
Indirect Address, and the

DCA

Instruction

Instruction Test 2B

MAINDEC 08-D02A

Tests 2s add and rotate logic

Random JMP Test

MAINDEC 08-D04B

Extensive test of JMP instruction

Random JMP-JMS

MAINDEC 08-D05B

Extensive test of J MS instruction

Random ISZ Test

MAINDEC 08-D07B

Extensive test of ISZ instruction

Memory

MAINDEC 08-DlJO

Test

Checkerboard

Memory Address

Tests memory circuits susceptibility

to noise

MAINDEC 08-Dl BO

Tests address selection logic

Test

Memory Power

MAINDEC 08-Dl AB

on/off Test

Test ability to retain memory

information during

* Programs are subje ct to change

5-2

loss

of power

5.3 PREVENTIVE NAAINTENANCE

Clean the air filter. Use a vacuum cleaner to
remove accumulated dirt and dust.
b.

A systematic preventive maintenance program can be
a useful deterrent against system failures. Proper
application of such a program is an aid to both service-

Lubricate slide mechanisms and casters, with a

light

man and user, since detection and prevention of
probable failures can reduce maintenance and down-

time to a minimum.

tion .

machine oi

Wipe off excess oi

Visually inspect equipment for general condi-

Repaint any scratched areas with DEC black

paint or Krylon glossy white

No. 1501

Scheduling of computer usage should always include
time set aside for maintenance purposes.

e. Inspect all wiring and cables for cuts, breaks,
fraying, wear, deterioration, kinks, strains, and

Careful

diagnostic testing can make evident problems which

may only occur Intermittently during on-line opera-

mechanical security.

tion .

defective wiring or cable covering.

We suggest weekly program checks scheduled on the

Tape, solder, or replace any

Inspect the following for mechanical security:
key switches, control knobs, lamps, connectors,

following criteria:

transformers, fans, capacitors, etc.

1000-hours - electrical
500-hours - mechanical

Tighten or

replace as required
Inspect all module mounting panels to ensure
g
that each module is securely seated in its connect.

or at least every three months.

Remove and clean any module which may have
collected excess dirt or dust.
or.

5.3.1

Weekly Checks

h. Inspect power supply components for leaky
capacitors, overheated resistors, etc. Replace

Time should be scheduled each week to operate the
^AAINDEC programs. Run each program listed in
Table 5-2 for at least five minutes. Take any

any defective components.

corrective action necessary at this time and record

supply as specified in Table 5-3.

the results in the log book.

meter to make these measurements without dis-

External cleanliness of

Check the output voltage of the 718 power
Use a multi-

connecting the load. With the exception of Memory Supply + the outputs of the supply are not
adjustable; therefore, if any output voltage is not
within tolerance, the supply is considered defective and corrective maintenance should be performed.

the system should also be maintained on a weekly
basi s

Many hours of computer downtime can be avoided by
rigid adherence to a schedule based on the condition

of the air filter.

A dirty filter can cause machine
Run all MAINDEC programs to verify proper

failure through overheating which has a number of

bad effects. The frequency of this practice depends
upon system environment and usage. After several
weeks, the frequency of cleansing for the particular
environment will be determined. The procedure for
filter cleansing is described under Preventive Maintenance Tasks.

equipment operation. Each program should be
allowed to run for at least five minutes.
k.

Perform all preventive maintenance operations

for each peripheral

device included in the system.

Enter preventive maintenance results in the log

book.

5.3.2

Preventive Maintenance Tasks

5,4 CORRECTIVE MAINTENANCE

The following tasks should be performed on at least

a three-month's schedule:

The PDP-8/L is constructed of reliable TTL M-series
modules. Use of these circuits with faithful performance of the preventive maintenance tasks ensure relatively little equipment downtime due to failure.

Clean the exterior and interior of the equipment cabinet, using a vacuum cleaner and/or
clean cloths moistened in nonflammable solvent.

a .

5-3

5.4.1

Should a malfunction occur, maintenance personnel
should analyze the condition and correct it as indicated in the following procedures. Neither special

Before commencing troubleshooting procedures,
explore every possible source of information. Think
over the problem. Gather all available information

equipment nor special tools are required for corrective maintenance other than a broad-bandwidth
oscilloscope, a Tektronix Type P5019 current probe,
and a multimeter. The best corrective maintenance
tool is a thorough understanding of the physical and
electrical characteristics of the equipment. Persons
responsible for maintenance should be thoroughly
familiar with the system concept, the logic drawings,
the operation of specific module circuits, and location of mechanical and electrical components.
test

It is

Preliminary Investigation

from those users who have encountered the same
problem and check the system log book for any previous references to the problem.

Do not attempt to troubleshoot by use of complex
system programs alone.

Run the AAAINDEC programs

and select the shortest, simplest program available
which exhibits the error conditions. MAINDEC
programs are carefully written to include program
loops for assistance in system and logic troubleshoot-

virtually impossible to outline any specific pro-

cedures for locating faults within complex digital systems, such as the PDP-8/L. However, diagnosis and

ing.

remedial action for a fault condition can be undertaken logically, and systematically in the following

5.4.2 System Troubleshooting

phases:

Repairs and Replacement

Validation Test

Once the problem is understood and the proper program is selected, the logical section of the system
at fault should be determined. Obviously, the
program which has been selected gives a reasonable
Idea of what section of the system is fai ling . However, faults in equipment which transmits or receives

g .

Recording

Information, or improper connection of the system.

Preliminary Investigation

b.
c.

System Troubleshooting
Logic Troubleshooting

Circuit Troubleshooting

Table 5-3

Power Supply Specifications

Pins (G7B5)

Voltage

Current

Use

+7V (rms) ± 20%

1.75A

Panel Lights

AN2, AP2,AR2,AS2

+5V, ±3%

Logic

AA2,AF2,AH2,AJ2,AK2
AL2,AM2,BA2

-15V (-14V

1.5A

Keys and Switches,
Sense Amplifier
Main Supply

AB2

N/A

Sense Amp Slice
Reader Clock

AV2

Memory Supply -,

BS2,BT2,BU2,BV2

to -19V)

-15V (Zener
Regulated)

-30V (-28V

1.75A

BB2

Teletype

to -38V)

-6V (varies)

(AB28)

1.7A

Memory Supply +

5-4

BM2,BN2,BP2,BR2

CAUTION

frequently give indicaHons similar to those caused

by computer malfunctions.

Do not use the lowest

or highest resistance

Disconnect any peripheral devices which are not

ranges of the multimeter when checking

necessary to operate the failing program.

semiconductor devices. The XI range is
suggested. Failure to heed this warning
may result in damage to components.

Now, reduce the program to its simplest scope loop
and duplicate this loop in a dissimilar portion of
memory to verify, for instance, that an operation
failure is not dependent upon memory location. This
process can aid in distinguishing memory failures
from processor failures. Use of the technique described above often pinpoints the problem to a few

Measure the forward and reverse resistances of
Diodes should measure approximately 20Q
forward and more than lOOOfi reverse. If readings

diodes.

in each direction are the same and no parallel paths

exist, replace the diode.

modules.

5 .4 .3

Measure the emitter-collector, collector-base, and
emitter-base resistances of transistors in both directions. Short circuits between collector and emitter or

Logic Troubleshooting

Before attempting to troubleshoot the logic,

an open circuit in the base^emitter path cause most
failures. A good transistor indicates an open circuit
in both directions between collector and emitter.
Normally 50tol00Q exist between the emitter and
the base, or between the collector and the base in
the forward direction, and an open circuit condition

make

sure that proper and calibrated test equipment is
available. Always calibrate the vertical preamp

Make
and probes of an osci loscope before using
sure the oscilloscope has a good ac ground and keep
.

exists in the reverse direction.

the dc ground of the probe as short as possible.

Use the oscilloscope to trace signal flow through the
suspected logic element. Osci loscope sweep can be
synchronized by control pulses or by level transitions
which are available on individual module terminals
I

at the wiring side of the logic.

To determine forward

and reverse directions, consider a transistor as two
diodes connected back to back. In this analogy,
PNP transistors would have both cathodes connected
together to form the base, and both the emitter and
collector would assume the function of an anode.
In NPN transistors the base would be a commonanode connection; and both the emitter and collector,

Care should be

exercised when probing the logic, to prevent shorting
between pins. Shorting of signal pins to power

the cathode.

supply pins can result in damaged components. Within modules, unused gate inputs are held at +3 V.
This voltage is introduced from pin Ul or VI of

Multimeter polarity must be checked before measuring
resistance, since many meters apply a positive volt-

age to the common lead when in the resistance mode.
Since IC's contain complex circuits with only the
input, output, and power terminals available, static
multimeter testing is limited to continuity checks for
shorts between terminals. IC checking is best done
under dynamic conditions using a module extender

modules Ml 13, Mil?, or M617. The number in
parentheses beside each +3V input represents the
wiring run number for that +3V line. Each line can
handle a maximum of 15 loads.

to make terminals readily accessible.

Using PDP-8/L

engineering drawings and M-series module schematics,
you may locate an IC on a circuit board as follows.

5.4.4 Circuit Troubleshooting

a .

Engineering schematic diagrams of each module are
supplied with each PDP-8/L system and should be
referred to for detailed circuit information. Copies

Hold the module with the handle in your left

hand; component side facing you.
b.

of engineering schematic diagrams are contained in

IC's are numbered starting at the contact end

of the board; upper right hand corner.

Volume II
c.

The numbers increase toward the handle.

When a row is complete, the next IC is

Visually inspect the module on both the component

side and the printed-wiring side to check for overheated or broken components or etch. If this in-

located in the next row at the contact end of the
board. (See Figure 5-1).

spection fails to reveal the cause of trouble or to
confirm a fault condition observed, use the multi-

The pins on each IC are located as Figure 5-2

illustrates.

meter to measure resistances.

5-5

eleclrical current, take the following special pre-

cautions:
El

Use a heat sink, such as a pair of pliers, to

grip the lead between the joint and device being

soldered.

b. Use a 6V iron with an isolation transformer.
Use the smallest iron adequate for the work. Use
of an iron without an isolation transformer may
result in excessive voltages presented at the iron

tip.

Perform the soldering- operation in the shortest

possible time to prevent damage to the component

and delamination of the module etched wiring.
d.

IC's may be easily removed by using a solder

puller to remove oil excessive solder from contacts.

Then, by straightening the leads,

its

terminal points.

If it is

lift

the IC from

not desirable to save

the defective IC for test purposes; then the terminals may be cut at the IC body and each terminal

//^

removed from the board individually.

CAUTION

Figure 5-1

Never attempt to remove solder from terminmodule
against another surface. This practice can
result in module or component damage.
Always remove solder by the use of a solderal points by heating and rapping

IC Location

sucking tool

When removing any part of the equipment for repair
14

and replacement, make sure that all leads or wires
which are unsoldered, or otherwise disconnected,
are legibly tagged or marked for identification with

n n n n n n n

Replace defective component only with parts of equal or better quality, and
equal tolerance.
their respective terminals.

o
u u u u u u u
1

In all soldering and unsoldering operations in the

repair and replacement of parts, avoid placing ex-

cessive solder or flux on adjacent parts or service

Figure 5-2

lines.

IC Pin Location

When repair has been completed, remove all

excess flux by washing junctions with a solvent such

Be very careful not to expose
painted or plastic surfaces to this solvent.

as trichlorethylene .

5.4.5

Repairs And Replacement

5.4.6 Validation Tests

When soldering semiconductor devices (transistor,
diodes, rectifiers or integrated circuits) which may
be damaged by heat, physical shock, or excessive

Always return repjaired modules to the location from
which they were taken. If a defective module is

5-6

replaced by a new one, while repairs are being made,

hold voltage.

tag the defective module noting the location it was

set when the voltage at test point A27U2 changes

taken from and the nature of the failure.

When re-

from a low voltage (-6V) to a higher voltage (-2V)

pairs are completed, return the repaired module to
its

The threshold reference is properly

as the

original location and ascertain that the repairs

+5V supply voltage passes through 4.75V after

turn-on.

The threshold voltage is adjusted by the

have resolved the problem.

G826 variable resistor R2, lOOOQ Minneico, and
performs several functions. When the +5V supply

To confirm that repairs have been completed, run all
exhibited the problem. If
modules have been moved during the troubleshooting

voltage is

less than this

threshold, the regulated

memory supply voltage is held off.

tests which originally

A comparison

amplifier on the G785 module, continually monitors

period, return all modules to their original postions

the raw power supply input to the +5 regulator and

before running the validation tests.

anticipates any voltage decrease.

When a change

occurs, the LINE LOW level is asserted.

LINE LOW

Anytime that a module is replaced by one from spares
to correct a problem, always return the module to its

controls vari ous logic sig nals to the central processor

original location to confirm its defectiveness before

SHUT DOWN; a STOP OK level from the processor
allows a shut down of the memory supply voltage

by initiating POWER OK and a power failure action

initiating repair procedures.

when the +5V supply volta ge fails. As the threshold
is

5.4.7 Recording

reached during turn-on, POWER CLEAR produces

a pulse to ground and then re turns to a hi gh level

Also, with these conditions,

PO WER OK is a low

DOWN

A log book is supplied with each PDP-8/L system.

logic level, and SHUT

Corrective maintenance is not complete until all

The inverse of these levels should exist before the
threshold is reached. The STOP OK level originates

activities are recorded in the log book.

Record all

a high logic level.

data indicating the symptoms given by the fault, the

from the central processor and its undriven input

method of fault detection, the component at fault,
and any comments which would be helpful in maintaining the equipment in the future. The log should
be maintained on a daily basis, recording all operator
usage and preventive maintenance results.

should remain high having no effect during alignment.

5 .5 .2

Memory Alignment Procedure

To adjust or check the memory currents, the PDP-8/L
should be allowed to warm up for approximately 1 hr

5.5

ADJUSTMENTS

Note:

before measurements are made.

In addition, the

measurements should be performed at an ambient
temperature of 25 °C.

The measurements and adjustments in the

following paragraphs are analog in nature, and are
not of the on-off, high-low nature.

The G826 negative regulator control module at loca-

These areas re-

present tuned sections of the computer that must be

tion AB27 and the negative regulator portion of the

properly aligned by qualified personnel.

718 power supply control the memory voltage regulation, and therefore control the memory currents.

Adjustments of the PDP-8/L should never be undertaken unti it has been confirmed that a failure is
I

The voltage difference between MEMORY SUPPLY+
and MEMORY SUPPLY - provides the read/write,
and inhibit currents through the memory stack.

due to circuit aging or misalignment rather than a
component failure. Replacement of certain components or excessive environmental handling may

preclude any other corrective action.

The negative regulator control (G826) serves to vary
the 718 regulator for temperature variations by a

5.5.1

thermistor and difference amplifier tracking circuit
which compares the regulated memory voltage to an

Power-Up Threshold Adjustment

A Trimpot (R28, 2000Q Bourns)
located on the G826 module varies this reference volt-

This adjustment is preset at the factory and should

adjustable reference.

only be attempted in the field by skilled personnel

age, and therefore, varies the memory currents.
The G826 Negative Regulator Control module contains a difference amplifier that compares the +5V
supply voltage with an adjustable reference thres-

Adjustment of the trimpot varies the MEMORY
SUPPLY+ voltage between approximately -IV and

5-7

ence in current should not be confused with amplitude

-12V; the subsequent variation of the regulated
memory supply voltage should be between -18V and
-29V. Normally, the regulated memory voltage
should be set to approximately -22.5V, measured
with a multimeter across memory 5upply+ and memory

variations within the read/write current due to bad

address decoding selection switches; these di fferences

are also apparent at the memory stack inputs and vary
with different addresses. The current loops, provided
for use with a

supply-.

Tektronix Type P6019 current probe,

are as fol lows:
If the voltage

can be adjusted but not to the above

X Source
Y Source
X Return
Y Return

value, the thermistor across the regulator control
(pins B27R2 and B27S2) should be investigated. The
thermistor is located within the memory stack and

outputs on the inhibit connector card (pins B22S2
and B22T2); its resistance should be 3300^10% at
25°C. Shunting resistance in the regulator control
would reduce this value if a measurement is made
with the modules connected.

Examination of the current at these loops has the
advantage that the currents for all memory addresses
pass through these common points. The waveshape
should be inspected on each of the four loops to check
that no leakage to ground exists between the voltages,

If no voltage adjustment is possible, either the

MEMORY SUPPLY+'and MEMORY SUPPLY-.

Negative Regulator (G785) portion of the 718 power
supply or the Regulator Control (G826) can be at

The regulated memory voltage was previouslyadjusted
in a static condition for -22.5V; there should be no
change although the memory is now cycling. The resultant stack current should be approximately 320 mA
(this value varies with stack vendors, and is best
determined by adequate core output with minimum
noise). The lower read/write current amplitudes on

fault.

In alignment of the

C23T2 to C25K1
C18T2 to C2551
D19T2 to D25K1
D23T2 to D2551

memory, the actual outputs of

the various memory control flip-flops should be

checked against those of Figure 5-3. An approximate initial STROBE adjustment can be such that its
leading edge occurs 500 ns after the leading edge of
MEM START. The width of the strobe signal should
be less than or equal to 80 ns and hove on approximate adjustment range for its leading edge from
MEM START from 350 ns to 650 ns. A clockwise
rotation of the adjustment on the variable delay line
(M360 at CI 7) increases this delay. The final ad-

the current amplitudes on the current loops equal the

current amplitudes in the stack windings; the current

measurements can conveniently be made there. Correlation between the voltage and current should exist.

Variations in current amplitude at successive addresses should

be less than 20 mA.

Failure of the R/W

selection switches is indicated by the lack of proper

justment of strobe must be made in relation to the
analog data signal from core memory.

read/write currents of any address.

If all the

R/W

selection switches appear to have failed, inspection

should be made at the input logic signals, READ (1)
and WRITE (1), and the input supply voltages. To
analyze the read/write currents for individual addresses, the following program may be used:

The R/\N selector switches are examined by inspecting the current wave forms on the current loops at
the source and return signals. The current waveturns are similar to those of Figure 5-4 which represent the equal amplitude read/write currents measured on the memory stack input. When running a
multiple-selection program such as MEMORY

0000

CHECKERBOARD, the wave forms differ in the
amplitudes of the read/write currents due to the
contribution of the base currents to the emitter

Beg, LAS

0001

DCA Temp

0002
0003
0004

TAD

Temp

J MP Beg

Temp,

7604
3004
1404
5000
0000

currents of the address decoding and selection switches.

The read/write currents for individual addresses may
be examined by setting the desired address into the

The additional current (approximately 30 mA) appears
on the return current through the R/W selection
switches to MEM SUPPLY-. Depending upon the
loop examined, it is sometimes additional read current
and sometimes additional write current. This differ-

all

switch register.

Of course, since the currents for

memory addresses pass through the common test

point, you will also be examining the currents for

those locations which the test program occupies.

You

must first ascertain that the currents are proper for
those addresses within the program; if not, relocate

5-8

c
o
o
E

CO
I

lO
(U
I-

5-9

the program to some other area of memory.

does not correct the problem; then , the logic signal

By select-

ing individual addresses via the switch register, wave-

inputs from the memory address (MA) registershould be

form deformities may be traced to defective associated

inspected.

R/W switches

If those signals are correct and vary according to the selected address, attention should be

•

turned to the memory stack with its attendant diode

improper waveform remains fixed to a specific
address and replacement of the associated R/\V switch
If the

selection matrices.

MEM START

0.38;js

0.76;js

50MS

A/\/V

< ZOma

WRITE

O.Z8;lS

NORMAL READ/WRITE
CURRENT WAVEFORM
320 ma

I.ZSiis

1.5m«

OPEN DIODE, BAD R/W SWITCH

SHORTED DIODE

ABNORMAL READ/WRITE
CURRENT WAVEFORMS

Figure 5-4

(BOTH WAVEFORMS MAY ALSO BE NEGATIVE)

Representative Read/Write Current

Waveforms

5-10

The diode selection matrices (0611 and G610) sandwich the memory planes of ferrite cores between them
Also connected to this unit are two W025 cable connectors, one for the inhibit inputs, the other for the

Twelve 6020 sense amplifiers are associated with each

memory stack; each amplifier transforms the analog
pulse output of ferrite core to a usable logic level

The sense windings for each bit enter a differential

sense outputs.

amplifier with a threshold voltage established as a
function of the fixed SLICE voltage.

The test points
and K2) after the amplifiers allow observation of the waveforms for comparison wi th those of
Figure 5-6. The preliminary setting of STROBE
should now be modified as a function of the data out-

The X-axis Diode Selection Matrix (Drawing D-BS8L-0-15) has half its diodes on the G610 board and
half on the G61
board; the same is true of the Yaxis Diode Selection Matrix (Drawing D-BS-8L-0-I6).
The inductor symbol connecting the centers of the
two sets of diodes represents the stack winding traversing the 12 core planes. The windings are identified
on the diode matrix selection boards as X, 0-64 and
X, 0-64 for the X-axis windings and Y, 0-64 and Y,
0-64 for the Y-axis windings. Suspected opens and
shorts in the windings, detected during dynamic tests,
should be verified by measurements across Jhese

(pins El

put from core memory.

The leading edge of STROBE is set approximately at
the center or just past the midpoint of the amplifier

"one" output.

lay, and yet centered in the "zero" data output.
Each sense amplifier test point should be examined
and the final adjustment of the strobe signal should
be made using the most sensitive sense amplifier as

points with an ohmeter.

The resistance of the read/
The forward and reverse
resistance of the diodes in the matrix should also be
write winding is 3.5Q ±10%.

checked when address selection
ed to stack failures.

This adjustment should be late enough

to sense all "one" data with normal variations in de-

a criteria

failures are attribut-

The lack of proper waveforms at all addresses indicates that the sense amplifier or the core winding
in error. The sense amplifier may be checked by
exchanging a known good amplifier with the suspected one
The absence of an Input signal indicates
the stack sense winding should be checked or the
sense connector ^025 at AB21)for a resistance of
is

CAUTION

The memory stack is expensive and
fragile; it is easily damaged and must
be handled with care.

21Q ±10%.
Testing and adjustment of the memory section of the

Twelve inhibit drivers are associated with each memory stack. To inspect the inhibit currents you will
need two module extender boards (W982) at AB22.
These extender boards provide current loops for each
of the 12 inhibit lines. Inhibit current should be
inspected and compared with the waveform in Figure
5-5. Inhibit current amplitude is approximately
290 mA as noted; more important, however, is the
ratio of read/write and inhibit currents. This ratio is
0.85 of the read/write current and should exist regardless of the read/write current amplitude.
Failure of
a specific inhibit driver can be determined by movement of the suspected driver to another location.
Movement of the failure indicated that the module
should be repaired or replaced.

PDP-8/L is now completed by running the memory
address test and memory checkerboard test (worst
pattern) .

Final adjustment of the read/write currents

may be necessary to Increase or decrease the amplitude of the core input and corresponding noise.

5.6 ASR33 TELEPRINTER AND CONTROL

MAINTENANCE
This section contains information pertinent to the

maintenance of the ASR33 and its associated control
logic.

No movement of

the fai lure indicates that either the input signals or

output load is causing the failure.
B INHIBIT and B

The logic inputs,

MEM ENABLE, from the memory

5.6.1

Equipment

control; the connection through the current limiting
resistor; and the

memory buffer signals should be
checked. If the stack is suspected, the specific
winding should be measured for a resistance of 14Q

Table 5-4 lists the special tools needed for maintenance of the ASR33 Teleprinter. All of these items
can be obtained from Digital Equipment Corporation

±10%.

or from the Teletype Corporation.

5-11

5.6.2 Programs

CAUTION

Table 5-5 lists the maintenance programs supplied by
DEC for aid in maintaining the ASR33 and associated

other solvents to clean plastic parts

control logic

with protective decorative finishes.

Do not use alcohol, mineral spirits, or

Normally, a soft, dry cloth should be
used to remove dust, oil, grease, or

5.6.3 Preventive Maintenance

otherwise clean parts or subassemblies.

Teletype preventive maintenance is scheduled on the
same frequency as discussed in Paragraph 5.4.

To clean plastic surfaces, we recommend using any
of several household cleaner-waxer liquids such as

MEM START
0.0 Jis

1.5ms

290ma

l_J_

NORMAL INHIBIT
CURRENT WAVEFORM
t.OMt

ABNORMAL INHIBIT
CURRENT WAVEFORM

BAD TRANSFORMER, OPEN DIODE

OPEN WINDING

Figure 5-5

Representative Inhibit Current Waveforms

5-T2

Table 5-4
Teletype Maintenance Tools

Item

Part

No,

Part No.

Item

80993

8 oz . sea le

110443

Bending Tool

32 oz. scale

110444

Extractor

182697

64 oz. scale

82711

Tweezer

151392

Set- of gauges

117781

Spring hook (push)

142555

Offset screwdriver

94644

Spring hook (pull)

142554

Offset screwdriver

94645

Screw holder

151384

Handwheel

161430

Handwheel adaptor

181465

Contact adjustment tool

172060

Gauge

180587

Gauge

180588

Gauge

183103

Table 5-5
Teleprinter Maintenance Programs

Program Name

DEC No.

Reader Test

MAINDEC-8I-D2PB

Use
Function test and exerciser
paper

for ASR33/35 teletype

tape reader

Punch Test

/v\AINDEC-8I-D2QB

Function test and exerciser
for ASR33/35 teletype paper

tape punch

Keyboard Test

AAAINDEC-8I-D2RB

Function test and exerciser
for ASR33/35 teletype key-

board

Combination Test

MAINDEC-8I-D2TB

Exerciser program used to
test ASR33/35 printer and

punch simultaneously

5-13

E
>

a>
<n

5-14

"Jubilee" or "Jato. " To clean the printer platen,
we recommend using a lacquer thinner.

Brush Holder (Distributor)

Clutches

Code Bar Reset
During overhaul, subassemblies and metal parts can
be cleaned in a bath of trichlorethylene. Proper
lubrication should be performed often.

Print Suppression

Blocking Levers
Print Suppression

Carriage Drive Bail
Print Trip Lever

Weekly Tasks

Dashpot
Final Printing Alignment

Inspect platen and paper guides.

Wipe

Line Feed

Keyboard Trip Lever

clean, using a soft, dry cloth.
b.

Reader Trip Lever
Detent Lever
Sensing Pin
Tape Lid Latch Handle
Feed Pawl

Clean external areas of paper tape punch

and reader, using a soft brush or cloth.
c.

Remove and empty paper tape punch chad

box.
Run teleprinter combination test (MAINDEC8I-D2TB) for approximately 15 min.

Registration

574-122- -700 Page 15
574-122- 700 Pages 16-24
574-122- 700 Pages 30-34
574-122- -700 Page 35
574-122- 700 Page 37
574-122- 700 Page 43
574-122- -700 Page 44
574-122- -700 Pages 61-62
574-122- -700 Page 78
574-122- -700 Page 85
574-122- -700 Pages 89-95
574-122- -700 Page 141
574-124 -700 Pages 6-9

574-124 -700 Page 10
574-124 -700 Page 15
574-124 -700 Page 18
574-125 -700 Page 1
574-125 -700 Page 12

Run each of the Teletype MAINDEC Programs
for at least two passes each.
i.

Preventive Maintenance Tasks
a.

Inspect platen and paper guides.

Check that tape holes are being punched

cleanly.

Clean

platen, using a lacquer thinner to remove shiny

5.6.4

Corrective Maintenance

surfaces.
b.

Clean ribbon guides and replace ribbon,

necessary.
c.

Remove cover and check for vibration effects;

loose nuts, screws, retaining clips, etc.
d.

Remove distributor rotor and clean disk

surface, using cotton swab moistened in "Freon"
or "Trichlorethylene."
e.

Check selector magnet coil for signs of over-

heating.

Clean between selector magnet pole piece
and armature with bond paper to remove any
f.

lubricant or dirt.

Figure 5-7 is a simplified drawing of the control
Details of the
circuits for the ASR33 Teleprinter.

cable connector are included to show how a teleprinter is modified to operate with the PDP-8/L.
During off-line operation, the keyboard distributor
effectively drives the printer selector magnet. This
means that any character received from the keyboard
or paper tape reader is automatically reproduced on

the printer and paper tape punch. During on-line
operation, this continuity is broken and a teletype
receiver (M706) is used to accept the input from the

reader or keyboard while a teletype transmitter (M707)
is used to drive the printer and paper tape punch.
The clock (M452) develops a TTI clock (880 Hz) and
a TTO clock (220 Hz).

Clean and lubricate Teletype as instructed
Follow instructions
in Teletype Bulletin 273B.
lubricate.
not
to
over
literally so as

The following adjustments should be checked.
Pages indicated are in Bulletin 273B, Volume II.

Trip Shaft
Trip Lever

574-122-700 Page 13
574-122-700 Page 14

These clocks are used to shift the bits through the
transmitter and receiver buffers. Adjustment is made
by viewing the TTO clock output with the oscilloscope
probe on C33K2 and adjusting the trimpot for a 4.5 to

4.6 ms repetition rate. Most teletype problems can
be traced to one of four areas as follows.
a.
b.
c.

5-15

ASR33 keyboard or reader
ASR33 printer or punch

M706 receiver
M707 transmitter

c
o
4u
9)
c
c
o

s.
>s.
•I-

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0)

I—

K
1.

5-16