Digital PDFs

DEC-8L-D4BA-D

April 1970

14 pages

Original

0.6MB

Document:	MC8-L FuncDescr Jun70
Order Number:	DEC-8L-D4BA-D
Revision:	000
Pages:	14
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/dec-8l-d4b/dec-8l-d4ba-d.pdf

OCR Text

DEC-8L-D4BA-D

MC8/L

MEMORY EXTENSION CONTROL
OPTION FUNCTIONAL DESCRIPTION

DIGITAL

EQUIPMENT CORPORATION n MAYNARD

MASSACHUSETTS

1st

Printing April 1969

2nd Printing June 1970

The material in this manual is for information purposes and is subject to change without notice.

The following are trademarks of Digital Equipment
Corporation, Moynard, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

MC8/L
INST FIELD key raised, or by the program
through the Instruction Buffer (IB) register.

MEMORY EXTENSION CONTROL

All

program executed transfers of the IF come from
the IB.

INTRODUCTION

The content of the INST FIELD key is

loaded directly into the IF and the IB by manuoperation of the LOAD ADDR key. When a
JMP or JMS instruction is executed, the con-

An additional 4096 (4K) core memory can be
added io the standard PDP-8/L 4K core memory to yield the maximum storage capacity of
8192 words. Figure 1 shows the MC8/L modules and their locations lin the BA08 Peripheral
Expander and Figure 2 illustrates the Memory
Extension Control organization, and it's relationship to the standard memory.

The Memory

placed in the BA08 Peripheral Expander Cabinet as shown in Figure 2.
Extension Control

tent of the IB is transferred into the IF.

When an interrupt occurs, the content of the
IF is transferred to the

ter.

Save Field (SF) regis-

At the end of the interrupt subroutine the

IF status is restored

through the IB from the SF

by execution of the RMF instruction.

When the CIF instruction is executed (refer to

Transfer of MC8/L control and data signals

Memory Extension Control Instruction Descrip-

occurs mainly through the special signal cables

tions in this section) the content of MB08 is

and connectors. The PDP-8/L I/O BUS is connected to the BA08. Some of the l/O BUS signals are used by the MCB/L option; however,
other options make use of this bus so it must be

transferred to the IB; the content of the IB is

supplied.

gram interrupts are inhibited.

transferred to the IF at the execution of a
or JMS instruction.

JMP

During the time between

the CIF instruction and the JMP or JMS, pro-

The following paragraphs describe the use of
the MC8/L control logic, and the Memory

Extension Control instruction set.

It is

assumed

that the reader understands the memory timing,
read, write, inhibit and sense elements of the

Data Field Register (DF)

basic memory system described in Volume I,

This 1-bit register determines the field used for
data storage and retrieval
The DF can be

Chapter 4, of the PDP-8/L Maintenance Manu-

loaded from three discrete sources:

al.

The memory system elements described
above are identical to those in the expanded 4K
core memory; therefore, maintenance and operation are the same.

Save Field (SFl), and the DATA FIELD key.

LOGIC DESCRIPTION

FIELD key by manual operation of the LOAD
ADDR key. While the program is running, a
CDF (change data field) instruction can be used

Initially, the

MB08, the

DF is loaded from the DATA

to alter the content of the DF to permit selec-

tion of the other memory field.

Instruction Field Register (IF)
This 1-bit register determines the memory field
to be used for storage and retrieval of program
instructions.

The IF register can be loaded

directly by pressing

LOAD ADDR with the

08 of the
CDF instruction contains the desired field address (either
or 1). Once loaded, the content of the DF remains unchanged until altered;
either manually by LOAD ADDR and the asserted DATA FIELD key, or under program control
by a CDF instruction.
Bit

Figure

Memory Extension Control in the BA08 Peripheral Expander

During a program-interrupt operation, the content of the DF is automatically stored in the

Save Field register (SFl) and is restored to the
DF upon completion of the interrupt subroutine
by the RMF instruction.

Extended Address (EA) Field Selection

The EA flip-flop (drawing D-BS-MC8-L-2)
allows access^either memory field.
flop outputs,

The flip-

EA (for field 0, the standard core

memory) and EA (for the extended memory)
enable each memory timing generator when at
a high logic level.

Instruction Buffer Register (IB)

The EA extended address field enable flip-flop
can be activated from one of three sources: the
This 1-bit register provides input buffering for

the IF register, the DF register, or the BF regis-

data transfers made into IF under program con-

The IF register is gated to the EA flipflop except during a break cycle or an indirectly

trol .

Manual transfers are made directly Into

IF and,

simultaneously, into IB.

of data Into both registers

This transfer

necessary to pre-

vent inadvertent changing of the content of IF.
The output of IB is loaded into IF at the execution time of every JMP or JMS instruction
strobes the output of IB into IF.

ter.

referenced data handling instruction (AND,

TAD, ISZ and DCA).

addition, when the

LOAD ADDR and the INST FIELD keys are
operated, the IF is gated to EA to generate the

memory field enable level. The DF register is
gated to EA when any indirectly-addressed

memory reference instruction other than JMP or
JMS is executed (AND, TAD, ISZ or DCA).
The BF decoder allows the BF to generate the

Save Field Register (SF)

memory field select code during a break cycle.

This 2-bit register provides temporary storage
for the content of both IF and

DF during a pro-

gram interrupt. This is necessary to permit IF
and DF to be cleared so the program interrupt
subroutine can start in field 0. At the conclusion of the interrupt subroutine, an RMF instruction loads the content of SFO into IB for
subsequent transfer into IF, and the content of
SFl into DF. The last instruction in the subroutine (JMPIO) completes the transfer from IB,
to IF.

Interrupt Inhibit

The interrupt inhibit (drawing D-BS-MC8L-2)

OK (drawing D-BSPDP-8-L-7) level in the processor from the time
a CIF instruction is decoded until a JMP or
JMS command finishes the CIF instruction.
This prevents operation of an interrupt before
the field is changed. Interrupt synchronizalogic disables the INT

tion is restored after the IF is loaded from the
IB, allowing further program interrupt to occur.

Break Field Register (BF)

MEMORY EXTENSION CONTROL INSTRUCTION DESCRIPTIONS
This 1-bit register determines the field to be

used for storage and retrieval of data transfers

The following paragraphs describe the basic

from I/O devices using t he data break fac ility.

microinstruction set necessary to control pro-

The BF is loaded from the EXT DATA ADD line
by BTP2 of the cycle before a data break is

gram execution with the Memory Extension Control option. See Table 1 Basic lOT Micro-

initiated.

instruction Set for the MC8/L.

Table

Basic lOT Microinstruction Set for the MC8/L

Mnemonic

Octal

Operation

62N1

Change to Data Field N. The data field register is

Program Interrupt

CDF

loaded with the selected field number (0 or 1). All
subsequent memory requests for operands are automatically switched to that data field until the data
number is changed by a new CDF command, or

field

MBS = >DF

during a program interrupt.

GIF

62N2

Change Instruction Field. The instruction buffer
register is loaded with the selected field number

The next JMP or JMS instruction causes
the new field to be entered . MB8 => IB
(0 or 1).

RDF

Read Data Field.

6214

The content of the data field

Bits 6

and 7 are cleared, all other bits of the AC are not
affected
DF = > ACS
.

RIF

Same as RDF, except reads the instruction field.

6224

=>AC8

RIB

6234

Read Interrupt Buffer. The instruction field and data
field, stored in the same field during an interrupt,
are read into AC 8 and 1 1 respectively. SFO = >
ACSSFl - >Acn

RMF

6244

Restore Memory Field, Used to exit from a program
interrupt.

Change Instruction Field (CIF)

Change Dote Field (CDF)
This instruction (octal code 62N1, where

N is

This instruction (octal

code 62N2, where N is

the octal number of the field to which the pro-

the octal number of the field to which control
is changing, N is Og for field 0, and Ig for

gram is changing) Is executed prior to JMP or

field 1) is used prior to storing or retrieving

JMS instruction. The 62N2 Instruction allows
MBOS (N = MB06 a 0, MB07 a and MB08

data with any indirectly-addressed memoryreference instruction other than JMP or JMS.

either a

This instruction is generated by combining

loaded into the IB by combining

BIOPl and MB03 through MB07 levels (drawing
D-BS-MC8-L-2).

clocking the clock input with LOAD IB.

for field

(0) to enable

the IB

for field 1) to be
it

with BMB09

flip-flop data input and

The

content of IB is then transferred to the IF when
the next JMP or JMS command is executed

Read Data Field (RDF)

(LOAD IF active).

This Instruction (octal code 6214) reads the
contents of the DF flip-flop onto the ACI08

Restore Memory Field (RA/lF)

bit AC08 in the same manner as with the RIB

line.

The data is transferred to accumulator

instruction.
This instruction (octal code 6244) restores the

contents of the SF to the DF and IB registers.

The conclusion of an interrupt subroutine (JMP
I

)

loads the IF from the IB.

Read Instruction Field (RIF)

RMF (drawing

D-BS-MC8-L-2) allows bit SFl to be loaded in-

This instruction (octal code 6224) reads the con-

to the DF.

tents of the IF flip-flop onto the ACI08 line.

The content of the IB is transferred

to the IF by executing a

JMP or JMS instruction.

The data is transferred through the INPUT BUS
08 line to bit AC08 in the same manner as the
RDF.

Read Interrupt Buffer (RIB)
This instruction (octal code 6234) allows storing
that same field in memory if the power failure

ENGINEERING DRAWINGS

option is installed.

The following drawings pertaining to the

This instruction reads the
contents of the 2-bit SF register into the AC on

the AClOSand ACIl 1 lines (drawing D-BS-

MC8-L-2). These lines activate the INPUT
BUS 08 and 1 lines in the processor.
1

MC8/L option are contained in this section.
Drawing Number

D-BS-MC8-L-1
D-BS-MC8-L-2

Execution of the RIB instruction generates AC

LOAD and AC ENABLE in the processor which

Title

Memory Control
Memory Extension Control

D-BS-MCa-L-3

Sense Amp and Inhibit

allows transfer of the data on INPUT BUS 08

Drivers

and 11 to the accumulator. AC LOAD (drawing D-BS-PDP8-L-6) is generated by I/O ENABLE and I/O STROBE as a result of performing

D-CS-MC8-L-4
D-CS-MC8-L-5

X-Axis Selection
Y-Axis Selection

I>-IC-MC8-L-6

lOT (6234) command. I/O ENABLE also
produces AC ENABLE (drawing D-BS-PDP8-L-

Special Signal Con-

D-UA-BC08A-0-0

this

4).

nectors

BC08A Cable

» LOOPS FOR MEASURIN8 MEMORY
HALF SELECT CURRENTS

D-BS-MC8-L-1

Memory Control

CLR

IB,rF, DF-

eM« 00

BMA 03

BMA ae

BMA 09

BMB 00 (J)

BMB 01 (0

BMBflZ^l)

SF
KEY Cl£AR

*- \.OAO

D-BS-MC8-L-2

Memory Extension Control

D-BS-MC8-L-3

Sense Amp and Inhibit Drivers

-| 'cvd

6221
cza

io-

iS2'

CDB7*

-J

CU2

7!_i

72_1

notes;

CT2
l«G6ll

^==t>

CS2

«rf—i-t»

C0I27

REPLACED WTTH A

G6I2 IF INSTALLED

cn2

^£>--_50_5_
CN2

CLAMP
'

5221

C09

_47_J_

38 f

CL2

J"^

t-^-trS-

F^
I

CK2

—1»—»-

CJZ

'a*

CH2

—

-t<i=^f«.

20 f

CFZ

m:^^ r=c-3
Clamp

BMA02
NES

CE2

ga ^

YCM £-.AaLE

,^
T2

(
X
X

DC2

002

-0(t--C+.

.t;ti-_<J-,

aCct-

03^

0E2

0H2

^
OJZ

iOK2

-r
-t»C-M.

04 ^
0L2

OMZ

06 f
'

0N2

ff2~L-?

R/W SOURCE

R/'W

DR2

>0P2

BTji

0T2

0S2
P"2

0U2

0V2

fz-ff^

) ena5

ixi

RETURN

MEM ENABLE
BMA03

E2.

NEG _
CLAMP
NES

6221

'CLAMP

004

BMASS

BMAOS

BMA
94

_ _

r
I

D-CD-MCa-L-4
15

X-Axis Selection

^->. 6610

J. Cv4

6221

Fa>

"='"'*

>»i--e*.

CU2

7tf

t*v
72

-J

•»*-+»

'
'

i4Cct.

1±X

-J

G6I2 IF InSYaLLEO

'=5a>

-»

CS2

—«—

=f^^ r=a>

.^.
CP2

50 Y

CNZ

^t>

CM2

IKZI

i.'.

t04

_40_5_

CL2

S22I

CA2

Clamp

IN C007
REPLACED WITH *

»e6ll

CT2

-a—f-

notes:

7S_J

CK2

H4-

30 ^

CJ2

Jn2

==a>

urr:
|P2

20 f

CF2

m:^^ r=I>

CE2

C02

^H>
NEG

CLAMP

BMAas —
3 M£'/

-J

-t>

ENABLE

r B/W

—IW
CC2

hA»

aS—-a-

>c4—--a-

00 f
>0C2

002

DE2
I

02 f

f
•0F2

OH 2

04 ^
0J2

0L2

0M2

05 I
DN2

0P2

06 ^
0R2

'0S2

07
>0T2

0U2

£yD"iU

source

RETURN

MEM ENABLE
BMAOS

NEG
CLAMP

NEG

CLAMP

Y-Axis Selection

D-CS-MC&-L-5
17

M903
A29

M9e3
829

b'i

CI
•

6MA ea
BMA 01
BMA 02
BMA 03
BMA 04
BMA 06
BMA 0e

BMA 07
BMA 06
BMA 09
BMA
BMA

—

1
"

02
E2
F2

F2
H2

±
1

MEM STAHT
STROBE
BTP2

MEM 02
MEM 03
MEM 04
MEM 05
MEM 08

MEM 07
MEM 08
MEM et9

J2
K2

MEM 00
MEM ai

-'f

K2
L2

MEM

M903 M903

M90J M9a3

A30

B30

A31

£1

02
E2
F2

n'2

N2
P2

KEY

l'2

INT iiNHlBiT
LOAD SF

T2
U2
V2

BTPS
KEY CLR

BF ENABLE

J2
K2

S2
T2
02

r'2

SP CYC NEXT

P2
R2
S2

N2
P2

OF ENABLE

H2
J2
K2

M2
N2
P2
R2
S2
T2
U2

MB PARITY ODD

B3I

KEY OF
SET + F SET
JMP + JMS
KEY LOAD

1
~

S2
T2
U2

±
1

STOP OK

CP PWR.OK

^<-J

D-IC-MC8-L-6

Special Signal Connectors

PART NO.
BCaSA BCasA- 2
1

3 FT

4 FT
5 FT

FT
7 FT
8 FT
6

BCizsA - q

BCOBA-IO
BC08Asre NJOTE

10 FT

NOTES
1.

2 FT

BCtaSA - 3

BC(a8A-8

SIDE

BC08A - 4
BC08A- 5
BCeSA- 6

BC08A-7

DIM "A"

JO
(T^PE)
PRINT Clamp)
THEN ASSEMBLE
ITEM *3
TO
item'soR^G
ITEM *
(flip chip) with
ITEM
(flex

(ErELE TS").
FLEXPRINJT
2.

TO BE CUT TO THE
to
lengths
prior
fabrication:
3
flexprint "a" - dim "a" plus i4 inches
flexf^int *b"- dim "a" plus /-is

f0llcwin6

3 /£ FT

ATTACH
ITEM *3

-:.e;<print
3.

'c-dim a

wired

the

example
pi-ai
wired to p2-ai
and
is
to
wired
p2-b2
SO OKI.
rns,

4 TOLE.RANCES:

("STD.

O TO 2
2't" to
1"

6:i-ECTF<.\c<».l— l_Y

2 INCHES

INCH

?^.
'Ervi

CCNNl_oT

—y^

D-UA-BC08A-0-0
21

and

^ INCH

SEE NJOTE 5

pi-b2

FLEXPRINT "A

SIDE

—
same

CABUE)

5 FT

TO 10 FT
5 FL-EIXPRINT 'c\
5'

pl^ ?

p2 on

BC08A Cable

tSiOT