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DEC-8L-D0BA-D

April 1969

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Document:	KP8L Power Failure Option Functional Description Apr69
Order Number:	DEC-8L-D0BA-D
Revision:	000
Pages:	6
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/dec-8l-d0b/dec-8l-d0ba-d.pdf

OCR Text

DEC-8L-D0BA-D

KP8/L

POWER FAILURE
OPTION
FUNCTIONAL DESCRIPTION

DIGITAL

EQUIPMENT CORPOnATION d MAYNARD

MASSACHUSETTS

1st Printing April

1969

crease in the +5V dc voltage, and generate

KP8/L

POWER FAILURE

a low logic level, SHUTDOWN.
signal sets theKP8/LPWR

This

LOW flag flip-flop

(Drawing D-BS-KP8L-0-1). PWR Low (0)
generates INT RQST (Drawing D-BS-PDP8-L10). Aprogram interrupt occurs if the proces-

The interrupt is effected In the usual manner with a

sor interrupt facility is enabled.

FUNCTIONAL DESCRIPTION

search subroutine using the octal instruction
6102 (SPL, Skip on Power Low) to enable the

INTRODUCTION
The KP8/L Power Failure Option causes an
interrupt signal to the PDP-8/L computer,
allowing computer operation for a fixedtime after a primary power interruption.
With proper programming, an interrupt from
the KP8/L insures data storage of the several

machine registers of interest (accumulator,
link, program counter, etc.) in core memory. When the option is enabled, restoration of power restarts the computer at memory location OOOOs, after a suitable delay,
to allow for voltage stabilization, A pro-

gram subroutine, entered when power returns
places the previously stored data back in
The option can be
their proper registers
.

PWR SKIP gate signal to locate the interrupting source. The PWR SKIP gate Is enabled
by PWR LOW (1), the power-fail device
selection code (lOs, from MB03 through
MB08), a nd the inter rogation timing signal
PWR SKIP generates l/O SKIP
(Drawing D-BS-PDP8-L-10) which allows
entry into the power fail service subroutine
The service subroutine stores the
(Figure 1)
contents of the AC, Link, and PC in core
memory. Also, any critical information that
might be lost in a power failure is transferred
first to the AC, and then into core memory
IOP2(l),

during this subroutine. When a program
interrupt occurs, and the interrupt facility is

enabled, the contents of the PC are automatically stored in location OOOOg. Because

disabled to prevent restart.

location OOOOg is used later with the restart
program, this content (PC word) is then re-

The KPB/L Option consists of an M703
Integrated-Circuit module partially controlled by the PDP-8/L G826 Regulator and
Power Detector module. Both modules are

located in memory.

contained within the processor logic frame.

Finally, a JMP Instruc-

tion to address X is stored in location OOOOg,

and the HLT instruction is executed. Address

X is the starting location of the restart program.

The HLT instruction must be included

in the power fail service routine following

LOGIC DESCRIPTION
The following paragraphs describe the
sequence of events that occurs when power
The basic power-fail prois interrupted.
gramming technique is also described.

the instructions that store the contents of the
registers after a register storage has occurred
1

Adequate time for search and execution of
the above subroutine is provided by the 1-ms
single-sh ot delay activated by the SHUT
DOWN signal. The activated low output,

When primary power is removed, detection
circuits in the G785 module and G826

of the G826 module from initiating the

module (Regulator and Power Detector,
Drawing D-BS-PDP8-L-13) react to a de-

normal machine down cycle. After the 1-ms
delay, the STOP OK signal goes high; the

STOP OK, inhibits the Regulator Control

PROGRAM
IN OPERATION

ENTER DEVICE
"SEARCH"
SUBROUTINE

POWER FAIL SUBROUTINE NOT ENTERED.
THE REGISTER CONTENTS ARE NOT
SAVED. PROGRAM HAS TO BE MANUALLY
RESTARTED FROM BEGINNING.

YES

THE PROGRAM CONTINUES FLAG CHECKING.
NOTE WITH REAL TIME APPLICATIONS
THE TIME REQUIRED FOR
CHECKING REDUCES THE TIME
FOR THE REAL TIME SERVICE
SUBROUTINE. POSITION KW8/I

SKIP THE NEXT SEQUENTIAL

INSTRUCTION AND ENTER
KPe/L SERVICE ROUTINE

INQUIRY NEAR THE BEGINNING,

OCA AC
RAR
OCA LINK

MQA
DCA MQ
TAD OOOOa
DCA PC
TAD RESTRT X
DCA OOOOj
HLT

Figure

Power Fall Service Subroutine

Regulator Contro disables the memory voltage;
I

and STOP OK and POWER OK combine to
Insure that the

RUN flip-flop is cleared (re-

set) at the next processor time pulse

/INTERRUPT WAS CAUSED BY POWER LOW FLAG
/SAVE AC
/GET LINK
/SAVE LINK
/GET MQ
/SAVE MQ
/GET PC
/SAVE PC
/GET RESTART LOCATION
/DEPOSIT RESTART LOCATION IN OOOOs

TP3

(Drawing D-BS-PDP8-L-2)

signals:

KEY ST and KEY ST + EX + DP

(Drawing D-BS-PDP8-L -2)

A 00 00s start-

ing address is forced by RESTART, inhibiting

the transfer from the PC register to the

MFTSI(I) (Drawing D-BSProgram events are shown in

PDP8-L-4)
Restoration of primary power initializing

Figure 2.

signals throughout the PDP-8/L to clear the

major timing and machine-state flip-flops,
including

PWR LOW.

NOTE

Before the computer

can start, a restart signal must be generated.
The integrating 300 ms single shot delay (draw-

A JMP or JMS instruction must be in

ing D-BS-KP8L-0-1) is enabled when normal

location OOOOs because it cannot be

voltages are restored (both SHUT

DOWN,

and STOP OK are high logic levels). If no
additional power interruptions occur, the
single-shot will time out and try to generate
the restart signal after the 300-ms delay.
The microswitch on the M703 module handle
can be set to DISABLE to inhibit this pulse,
or to ENABLE to allow it. When a 1-ms RE-

predicted what the PC register will

contain when a power failure occurs
since the PC register contents are not

known.

ENGINEERING DRAWINGS

START pulse is generated, itacts as a KEY

The following drawings D-BS-KP8L-0-1 and

ST signal in activating the manual function
timing generator, by producing the same

D-CS-M703-0-1 pertaining to the KP8/L
Option are contained in this section.

ENTER DEVICE
"SEARCH"
SUBROUTINE

PROGRAM INTERRUPTED AND
POSSIBLE ERRONEOUS DATA.
UPON POWER RETURN PROGRAM
IS STARTED FROM BEGINNING

SKIP THE NEXT SEQUENTIAL

INSTRUCTION AND ENTER
KP8/L SERVICE ROUTINE

CHECK FLAG STATUS OF EACH
DEVICE UNTIL THE
INTERRUPT-REOUESTING
DEVICE IS LOCATED.
SERVICE THE DEVICE

OCA AC
RAL
DCA LINK
STORE ANY CRITICAL
INFORMATION THAT
MIGHT BE LOST WHEN

POWER FAILS
TAD OOOOe
DCA PC
TAD K (JMP X)
DCA OOOOe
HLT

YES

PROGRAM MUST BE RESTARTED
MANUALLY. POSSIBLE ALTERATIONS
OF STORED PROGRAM, OR DATA
RESULTING FROM POWER FAILURE
MAY REQUIRE RELOADING OF SOURCE

MA IS ZEROED UPON
RESTART. THE
INSTRUCTION IN
LOCATION OOOOg

PROGRAM.

LOCATION
0/JMP X

LOCATION X CONTAINS THE
BEGINNING OF THE RESTART
PROGRAM WHICH RESTORES
THE CONTENTS OF LINK, AC, PC,
AND ANY OTHER INFORMATION
STORED BY PWR FAIL SERVICE
SUBROUTINE. CONTINUATION OF
THE PROGRAM AUTOMATICALLY
OCCURS. THE ONLY DOWNTIME
RESULTS FROM LACK OF POWER

c
Figure 2

PERFORMED

CONTINUE
MAIN PROGRAM

;

Power Restoration Program Events

M7(Z3

A36

(switch on module)

DISABLE

i
N2

1
1

a Ul

SHUT DOWN

MBa3
MBa4
MB?5
MBse

l(Z

o
(I

MB2I7

(sa

MB08

(12

lOP 2

PWR LOW

D-BS-KP8L-0-1

Power Failure