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DEC-8I-HR2A-D

December 1970

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DEC-8I-HR2A-D

8/1
MAINTENANCE MANUAL
OPTION DESCRIPTIONS

AND
ENGINEERING DRAWINGS

VOLUME

1st

Printing October 1968

2ncl Printing (Rev)

May 1969

3rd Printing July 1969

4th Printing (Rev) May 1970

The material in this manual is for information purposes and is subject to change with-

out notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts;

DEC

PDP

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

CONTENTS

PART I

OPTION DESCRIPTIONS
ASR33 Teletype Option
Data Break

MC8/I, MM8/I Extended Memory Option
MP8/I Memory Parity Option

VCB/l Oscilloscope Display Option
VP8/I Incremental Plotter Option

KW8/I Real-Time Clock Option

PART II

ENGINEERING DRAWINGS
PART III

APPENDICES
Logic Symbology

Tables of PDP-8/I Instructions
Perforated Tape Loader Sequence

Programs

Teletype Codes

Mathematical Data

III

INTRODUCTION
This volume contains three parfs:

Functional Descriptions of Options,
Engineering Drawings, and Appendices. The part containing the
Functional Descriptions is supplemented by the below listed separate
publications.
Title

BB08 General Purpose Bus Interface Option

Number

DEC-08-HIZA-D

KA8/I Positive I/O Bus Option Functional
Description

KB8/I General Input/Output Interface Option

DEC-8I-HODA-D

Description

KE8/I Extended Arithmetic Element

DEC-8I-HOCA-D

KP8/I Power Failure Option Functional
Description

KT8/I Time-Sharing Option Functional Description

DEC-8I-H8NA-D

PP8/I High-Speed Paper-Tape Punch Option

DEC-8I-H2CA-D

Functional Description

PR8/I High-Speed Perforated Tape Reader and
Control Option Functional Description

DEC-8I-H2DA-D

PART

OPTION
DESCRIPTIONS

VII

LIST OF FUNCTIONAL DESCRIPTIONS

ASR33 Teletype
Data Break

MC8/1, MM8/1 Extended Memory
MPS/l Memory Parity Option

VC8/I Oscilloscope Display Option
VP8/I Incremental Plotter Option

KW8^ Real-Time Clock Option

FUNCTIONAL DESCRIPTION
OF
OPTIONS

ASR33
TELETYPE
OPTION
FUNCTIONAL DESCRIPTION

ASR33
TELETYPE
INTRODUCTION
The Model ASR33 Teletype unit is provided as
standard equipment with the PDP-8/lo The unit

The control logic contains the flags which enact
a program interrupt, or an Instruction skip based
upon the aval lability of the teletype unit, thus
control ling the information transfer between the

serves as a keyboard and perforated-tape reader

Teletype and the processor as a function of the

input, and as a page-printer and tape-punch output for the computer. The unit is described in

program

Teletype Corporation bul letlns 273B and 1 1 84B.

Teletype-control logic adjustments, andASR33

maintenance are described in Chapter 5 of
this manual.
The Teletype unit is modified as follows, to
permit operation with the PDP-8/1.

Operation

for the teletype

The WRU (who are you) pawl is removed
mechanism. In network
communications operation, this pawl is trig-

The teletype control logic can be considered as
two separate and independent devices: the
teletype receiver, and the transmitter. The

gered to respond to the WRU command received from a transmitting station. When

teJetype receiver (drawing 65-81-0-11), performs a "read " operation in which an asynchron-

triggered, the pawl causes a "here is" code

ous serial data word from the teletype keyboard

to be generated and transmitted, identifying

or reader, is assembled by the receiver (M706)

the unit to the interrogating station.

for a parallel transfer to the accumulator.

A cable from main frame location J 12 is
connected between the teletype control , and

The teletype transmitter (drawing BS-8I-0-12)
performs a "print/punch" operation in which a

the teletype unit. This signal cable connects

parol lei data transfer from the accumulator to

to a terminal block within the teletype stand.

the transmitter logic (M707) occurs.

A relay is added and connections are made to

The logic
converts the parallel word to a serial word, and

a tape reader advance magnet. These connections enable tape motion whi le the control
assembles a character, and disable the magnet

sends it to the teletype unit to be decoded and

whenacharacterbeginsaserial transfer. The
teletype conversion requires little time to

Certain program instructions are used to initiate
the transfer of the assembled parol lei data to the

complete, and does not permanently limit any
normal use of the ASR33.

accumulator In the "read "operation, and the
loading ofthe parallel data from theaccumulator

punched on paper tape, or printed.

into the transmitter logic in the "print/punch"

The control logic, which consists of three
integrated-circuit modules located within the
processor mainframe, assembles or disassembles

operation. These instructions are decoded as

serial information for the teletype unit for

tions contain the octal

lOT instructions by the processor and generate
lOPpulseSo

Bits

through 2 of these instruc-

parallel transfer to, or from, the PDP-8/1 pro-

code 6, indicating an
input/output (lOT) instruction. Bits 3 through

cessor accumulator.

8 of the instruction provide a 6-bIt octal code

I-Tl

(I/O address code) sensed by the teletype control
logic to allow control of the transmitter and
receiver operations. This I/O address code is
038 for the teletype receiver, and 048 ^°^ ^^^
teletype transmitter. A 6-input NAND gate
in both the receiver and transmitter logic senses
the coding, and allows the lOP pulses to perform

the following functions.

(03)

IOP1 - generates TTI SKIP if the key-

receiver circuitry is shown on engineering

drawing BS-8I-0-11.

The clock (drawing BS-8I-0-12) is free-running,
producing TTI CLOCK pulses at 880 Hz. The
clock is common to both the receiver and transmitter functions; however, the clock frequencies

needed for these units differ.

board flag is set.
(03)

Read Cycle - Figure 1 shows the sequence of
events that occur when a serial word from the
teletype unit Is assembled in the receiver. The

IOP2 - Clears the keyboard flag, clears

accumulator, and starts reader if the reader

When the computer is turned on, or the Start

switch is ENABLED.

key is depressed, the processor INITIALIZE
level is generated. INITIALIZE clears the IN
ACTIVE flip-flop,the SPIKE DETECTOR flip-flop,
and generates KCC to clear the KEYBOARD
FLAG and set the READER RUN flip-flop (drawing BS-8I-0-11). Clearing the I N ACTIVE flip-

(03)

IOP4 - transfers (reads) the assembled

parallel word through the positive internal

bus to the AC.
(04)

lOPl

- generates TTO

SKIP if the tele-

printer flag is set.
(04) IOP2 - Clears the teleprinter flag.
(04)

flop generates the START ENABLE level .

IOP4 - Loads the parallel word into the

This

level, combined with the start bit at the output

of the Schmitt trigger (ST), which Is produced by
the Teletype Distributor by program control allows

TT0-TT7 buffer and initiates the release of
the serial word to the teletype unit.

a TTI

CLOCK pulse to generate PRESET.

The

PRESET pulse allows the serial data from the

Signals used by the teletype unit are standard
11 -unit-code serial current pulses consisting of

teletype to synchronize with the receiver logic

manner.

marks (bias current), and spaces (no current).

in the following

The marks correspond to binary Is; the spaces
Each 1 1-unit teletype
correspond to binary Os

"Fl^ESrr sets the IN ACTIVE flip-flop and each

character consists of three sections: a 1-unlt
start bit, eight 1-unit character bits (ASCII

the

TTI register flip-flop to a binary 1 , and clears

code), and two 1-unit stop bits. The start bit
(a space) indicates the beginning of a character
and allows synchronization between the control
logic and the serial word. The eight data bits
represent the actual binary data . Following the

READER RUN flip-flop. With READER RUN

cleared, a relay in the tape reader is energized
to release the tape-feed latch, stopping tape

start bit, the data bits are assembled, or dis-

motion only when the beginning of a character
has been sensed, and before sensing of the next
character begins. In addition, the SPIKE
DETECTOR flip-flop is set to sample the line 1/2

assembled with the least significant bit first.
The two stop bits (marks) allow the computer and

bit is not present at this time, the

teletype to resynchronize

flip-flop clears and awaits another

If the start

unit after the start bit is received.
I

N ACTI VE
PRESET signal.

This eliminates noise on the start bit that is less

than 1/2 unit.

LOGIC DESCRIPTION

.e., no false start due to noise, TTI SHIFT pulses
are generated and the start bit is loaded (a binary
0) Into TTI 0. The shift pulses are synchronized
I

The following paragraphs describe the read and
print/punch cycles, and the program instruction
set for teletype operation.

If the start bit is still present,

to occur during the middle of each serial bit

time.

I-T2

As Figure 6-1 illustrates, each succeeding

ROR
RUN

SET BY KCC INSTRUCTION(6032)--

'J
—

'1L
CONTINUOUS PULSES AT eBOHz RATE

TTl

CLOCK

SERIAL
CHARACTER
DISTRIBUTION

TTO
SHIFT

INHIBITED WHEN

220HI

IN ACTIVE IS

CLEARED

RATE

nmiT

^CLEARED BY KCC
INSTRUCTION (60321

KEYBOARD
FLAG

Figure

Teletype Read Cycle Timing Diagram

TTI SHIFT pulse loads the character bits into the
receiver serial shift register. When the start bit

enabled, INT RQST Indicates to the PDP-8/I
that a device is requesting service. The program
is shifted into TTI 7, the next TTI SHIFT pulse
then enters a "search" subroutine to determine
produced sets the IN LAST UNIT and KEYBOARD which device issued the interrupt. This is
FLAG flip-flops. Setting of IN LAST UNIT
accomplished by executing a series of "flagclears the IN ACTIVE flip-flop, disabling further checking" skip instructions. When the KEYTTI SHIFT pulses. When cleared, IN ACTIVE
BOARD FLAG sensing Instruction KSF (6031) Is
allows the CLOCK SCALE 2 pulses to set the

IN STOP I and IN STOP 2 flip-flops which
IN STOP 2 when set,
clears the IN LA ST UNIT f lip-flop , allowing
START ENABLE to produce PRESET when the

I/O SKIP (Drawing BS-8I-0-10) in the processor.
lO SKIP forces the processor program counter to

next character appears at the
output of the Schmitt trigger (ST).

skipped.

performed, and the flag Is raised, TT SKIP

count out the stop time.

(Drawing BS-8I-0-12) is generated producing

start bit of the

increment by one, thus the next instruction is

A service routine for the teletype re-

ceiver is entered when the skip occurs.

When th e KEYBOARD FLAG flip-flop is set,
TT INT (drawing BS-8I-0-12) is generated.
TT INT generates INT RQST (BS-8I-0-10) in the
processor.

If the

program interrupt facility is

In this

routine, the KEYBOARD FLAG is cleared,

READER RUN Is set to release a new serial word
to the receiver, and the previously assembled

word is sent, in parallel, to the processor.

I-T3

After the data is loaded into the TTO register,
TTO SHIFT pulses are generated, and the serial

Print/Punch cycle - Figure 2 illustrates the
sequence of events that occur when a parallel
word from the accumulator is loaded into the

commences. TTO SHIFT pulses are produced through the complementing action of the
FREQUENCY DIVI DE flip-flop w hich is clocked
at a 220 Hz rate by TTO CLOCK. Synchroniza-

shift

transmitter logic, and disassembled into serial

word format for use by the teletype unit. The
transmitter logic is shown on engineering drawing BS-8I-0-12.

tion is provided by using both of these clocks as

indicated in Figure 2, and described below.
LOAD AND PRINT/PUNCH THE SECOND WORD

TLS
(60461

the OUT ACTIVE flip-flop is set,
the start bit is placed on the line to the PRINT

take place:

SELECTOR MAGNET DRIVER (PSM line), and
OUT STOP1 is set (discussed later). Alternate

OUT
ACTIVE

TTO CLOCK pulses produce a TTI SHIFT pulse
which shifts the data word bit-by-bit into the
LINE flip-flop. The first TTI SHIFT pulse clears
the ENABLE flip-flop. As data is shifted onto

TTO
CLOCK

TTO
SHIFT
S

BITS 1-8 DEPEND ON THE DATA

LOADED FROM THE TTO REGISTER

OUT
STOP

When the first TTO CLOCK pulse following the
setting of ENABLE occurs, the following events

to-serial conversion has completed, an 8-input

NAN D gate se nses all z eroes in the TTO register,
I

OUT
STOP (.5

OUT
STOP 2
TELE-PRINTER
FLAG

the PSM line, binary Os are shifted into the TTO
register through ENABLE. When the parallel

allows OUT ACTIVE to
and its output TTO =
clear with the nex t TTO CLOCK pulse. In
enables the TELEPRINTER
addition, TTO =
FLAG to set with the next (and last) TTO SHIFT
pulse. When OUT ACTIVE iscleared, TTI SHIFT
is disabled, and the two 1-unit stop bit times
are counted out by the OUT STOP register. The
first TTO CLOCK pulse occuring after OUT
ACTIVE was cleared, clears the OUT STOP
flip-flop. The OUT STOP 1 .5 and the OUT
STOP 2 flip-flops are cleared by the next two
consecutive pulses. If another TLS instruction
1

Figure 2

Print/Punch Cycle Timing Diagram

When the computer is turned on, or whenever
the Start key Is pressed, the processor INITIAL-

IZE level is generated.

This level clears the

ENABLE, OUTACTIVE, TELEPRINTER FLAG,
and TTO register flip-flops. Execution of the
program instruction TLS (6046) generates TTO
SELECT in the transmitter logic, and lOPl and
IOP2 in the processor. IOP4 and TTO SELECT

combine in the transmitter logic to load the
parallel word (accumulator bits AC04 through
ACll) into the TTO register, and set the
ENABLE flip-flop. IOP2 and TTO SELECT are
combined to clear the TELEPRINTER FLAG.

has been issued (print/punch another character),
the oper ation commen ces with the occurrence of
the first TTO CLOCK pulse after OUT STOP 2
For the print/punch operation with
is cleared.
the ASR33,a 2-unitstop time period is required

because of the inherent electro-mechanical delay time in the teletype unit.

When the TELEPRINTER FLAG is set, TT INT
(drawing BS-8I-0-12) is generated. TT INT
produces INT RQST (drawing BS-8I-0-10) in the
processor. If the program interrupt facility is

I-T4

enabled, INT RQST indicates thai- a device is

next instruction is skipped. A service routine
forthe teletype transmitter is entered when the

requesting service. The program then enters a
"search "subroutine to determine which device
issued the interrupt.

skip occurs. For the transmitter service, a new

This is accomplished by

character is transferred to the transmitter to be
printed or punched by the teletype unit.

executing a series of "flag-check" skip
Instructions.

When the TELEPRINTER FLAG

sensing instructio n TSF (60 41 ) is performed and

Teletype Instruction Description

the flag is raised, TT SKIP (Drawing BS-8I-0-1 2)

isgenerated producing I/O SKIP (Drawing BS81-0-10) in the processor. I/O SKIP forces the
program counter to increment by one, thus the

Table 1 containsdescriptlonsof the teletype

keyboard/reader and the teleprinter/punch
Instructions.

Table 1
Teletype Instruction Descriptions

Mnemonic

Octal Code

Description

KSF

6031

Generates IOP1 to sense the status of the

KEYBOARD FLAG. When the flag is set,
the next sequential program instruction is
skipped. This indicates that the assembled
word is ready for transfer to the accumulator.

KCC

6032

Generates IOP2 to clear the KEYBOARD
FLAG and set READER RUN, In addition,
TT AC CLEAR Is generated to clear the
accumulator.

KRS

6034

Generates IOP4 to transfer the assembled
word in parallel to the accumulator through
the major register bus.

The KEYBOARD

FLAG is not cleared.
KRB

6036

Generates IOP2 and IOP4 to perform the
functions of the KCC and KRS commands
during a single computer cycle. The KEY-

BOARD FLAG is cleared.
TSF

6041

Generates IOP1 to sense the status of the

TELEPRINTER FLAG. When the flag is set,
the next sequential program instruction is

skipped . This indicates that the print/punch
operation has completed.

I-T5

Table 1 (Cont)
Teletype Instruction Descriptions

Mnemonic

Octal Code

TCF

6042

Description

Generates IOP2 to clear the TELEPRINTER

FLAG.
TPC

6044

Generates IOP4 to load the parallel word
into the transmitter register, initiating the

print/punch operation.

TLS

6046

Generates both IOP2 and IOP4 to combine
the functions of the TCF and TPC instructions
in one computer cycle.

I-T6

DATA BREAK
FUNCTIONAL DESCRIPTION

DATA BREAK

INTRODUCTION

transfer, then the Fetch state is entered to con-

tinue the main program.
Peripheral equipment connected to the data break
facility can cause a temporary suspension in the
program In progress to transfer information with
the computer core memory, via the MB. One
l/O device can be connected directly to the
data break facility or up to seven devices can
be connected to it through the Type DM01 Data
Multiplexer. This cycle stealing mode of opera-

tion provides a high-speed transfer of individual

words or blocks of Information at core memory
addresses specified by the l/O device. Since

Data breaks are of two basic types: single-cycle
In a single-cycle data break,
registers in the device (or device interface)

and three-cycle.

specify the core memory address of each transfer

and count the number of transfers to determine
the end of data blocks. In the three-cycle data
breaks two computer core memory locations perform these functions, simplifying the device
interface by omitting two hardware registers.

program execution is not involved in these transfers, the program counter,

accumulator, and

instruction register are not disturbed or involved

The computer receives the following signals

in these transfers. The program is merely suspend- from the device during a data break (these
ed at the conclusion of an instruction execution, Input/output signals can be changed to positive "bus" logic as described In Chapter 1).
and the data break is entered to perform the

-3V

Signal

Break Request

No break request

Break Request

Cycle Select

One-cycle break

Three -Cycle break

Transfer Direction

Data into PDP-8/1

Data out of PDP-8/1

Increment CA inhibit
Increment MB (pulse)
Address (12 bits)
Data (12 bits)

CA incremented
MB not incremented

CA not incremented
MB incremented

Binary

Binary 1

Binary

Binary 1

The computer sends the following signals to the device during a data break,

Signal

Data (12 bits)
Address Accepted

WC Overflow

Characteristics

-3V = binary 0, OV = binary

TP4 of a break cycle.
-3V level change occurring at TP2 time of
the WC state and lasting for one machine
cycle.

Buffered Break

.35 - .45 |js negative pulse beginning at

-3V when in Break state.

1-DBl

To initiate a data break, an I/O device must

When adata break occurs, the address designated

supply four signals simultaneously to the data
questsignal, which sets the BRK SYNCflip-flop

by the device Is loaded intotheMAatTP4tIme
of the last cycle of the current instruction, and
the major state generator is set to the Word Count

in the major state generator to control entry into

state if the cycleselect signal

the data break states . (Word Count for a three-

cycle data break or Break for a single-cycle

is set to the Break state If this signal is at -3V.
The program Is delayed for the duration of the

data break); a Transfer Direction signal , supplied

data break, commencing in the following cycle.

break facility. These signals are the Break Re-

to the

at ground, or

A break request is granted only after completion

MB control element to a low data to be
I

strobed into the MB from the peripheral equip-

of the current instruction as specified in the

ment and to inhibit reading from core memory;
a cycle select signal which controls gating in the
mafor state generator to determine If the one-

following conditions:

cycle or three -cycle data break Is to be selected;
and a core memory address of the transfer which

JMP instruction

supplied to the input of the MA„

At the end of the Fetch cycle of an OPR

or lOT instruction, or a directly addressed
b. At the end of the Defer cycle of an indirectly addressed JMP Instruction

When the

break request Is made, the data break replaces
entry into the Fetch state of an instruction.

At the end of the Execute cycle of a

JMS,DCA,ISZ,TAD, or AND instruction

Therefore the data break is entered at the conclusion of the Execute state of most memory reference instructions and at the conclusion of a

At the beginning of the Word Count cycle of a

Fetch state of augmented instruction. Having
established the data break, each machine cycle

one-cycle data break, the address supplied to

Word Count, Current Address, or Break cycle

the computer supplies an address accepted signal

Is a

until all data transfers

three-cycle data break or the Break cycle of a

have taken place, as

the input of the

strobed into the

MA and

to the device. Entry into the Break cycle is

Indicated by removal of thebreak requestslgnal

Indicated to the peripheral equipment by a

by the peripheral equipment.

buffered break signal and by an address accepted
signal that can be used to enable gates in the

More exactly, thebreak requestslgnal enables

At TP4timeof each machine cycle, the major

device to perform tasks associated with the
transfers. The address accepted signal Is the
most convenient control to be used by I/O
equipment to disable the break request signal,
since this signal must be removed at TP4 time
to prevent continuance of the data break Into

state generator

the next cycle.

the BRK SYNC flip-flop.

At TP1 time, the
BRK SYNC flip-flop is set if thebreak request
has been received, and is cleared otherwise.

set to establish the state for

If the transfer direction signal

the cycle. At this time, the status of the BRK

establishes the direction as out of the computer,

SYNC flip-flop is sampled and, if in the

the content of the core memory register at the

state,

the Word Count or Break state is set into the

address specified Is transferred into the MBand

ma jor state generator and a data break commences

immediately available for strobing by the

peripheral equipment.

If the transfer direction

Therefore, to initiate a data break, the break

signal specifies a data direction into the PDP-

request must be at ground potential for at least

500 ns preceding TPl of the cycle preceding the

8/1, reading from core memory is inhibited and
data is transferred into the MB from peripheral

data break cycle. A break requestslgnal should

equipment.

be supplied to the computer when the address,
data, transfer direction, and cycle select sig-

The statusof the BRK SYNCflip-flop is sensed

nals are supplied to the computer.

at the beginning of a Break cycle to determine

I-DB2

so that the PC and AC are not disturbed.

Break cycle is required. If a
break request signal has been received since

if an additional

With-

in one Break cycle of 1 .5 ps, a word is fetched

from a device-specified core memory location,
Incremented by one, and is restored to the

TP4, the Break state is maintained in the major
state generator; if the break request signal has

same memory location. The increment MB
signal-input must be supplied to the computer
is set into the major state generator to continue
only during a Break cycle In which the direction
should
signal
the program. The break request
of transfer is out of the PDP-8/l . These restrictbe removed by the end of the address accepted
signal if additional Break cycles are not required ions can be met by a simple AND gate In the
device; an increment MB signal is generated
only when an event occurs, the buffered break
SINGLE-CYCLE DATA BREAK
signal from the computer is present, and the
transfer direction signal supplied to the computer
One-cycle breaks transfer a data word into
is at ground potential
computer core memory from a device, transfer
or
memory,
core
from
a data word Into a device
not been received by this time; the Fetch state

increment the content of a device-specified core
memory location In each of these types of
data break, one computer cycle is stolen from
the program by each transfer; break cycles occur
.

THREE-CYCLE DATA BREAK

singly (interleaved with the program steps) or
continuously (as in a block transfer), depending

The three-cycle data break provides an economical method of controlling the transfer of data
between the computer core memory and fast

upon the timing of the break request signal at
rates of up to 660 kHz

peripheral devices. Transfer rates in excess of
200 kHz are possible using this feature of the

PDP-8/1
During the memory-strobe portion of the Break
cycle, the content of the addressed cell is read

TS3 and TS4 times of the Break cycle. In an
outward transfer, the write operation restores

The three-cycle data break differs from the onecycle break in that a ground-level cycle select
signal is supplied so that when the data break
conditions are fulfilled the program is suspended
and the Word Count state is entered. The Word
Count state is entered to increment the fixed
core memory location containing the word count.
The device requesting the break supplies this
address as in the one-cycle break, except that
this is a fixed address supplied by wired ground

the original content of the address cell to

and -3V signals rather than from a register.

into the MB,

If the

transfer direction

out of

the computer (into the I/O device). If the
transfer direction is into the computer, generation of the Memory Strobe pulse is inhibited so
that the MB (cleared during the previous cycle)
remains cleared. Information Is transferred from

the output data register of the I/O device into
the MB and is written Into core memory during

memory
If there is a further

break request, another Break
If there is no break request,

cycle is initiated.
the content of the PC is transferred into the
MA, the IR is cleared, and the major state
The program then
generator is set to Fetch
.

executes the next instruction .

The increment MB faci ity is usefu for counti ng
iterations or events by means of a data break.
I

Following the Word Count state a current address
state occurs in which the location following the
word count address (bit 11 =1 after + 1 =>MA)
is read, incremented by one, restored to memory,

and loaded into the MA to be used as the transfer address. Then the normal Break state is
entered to effect the transfer between the device
and the computer memory cell specified by the

MA.
I-DB3

Word Count State

LOGIC DESCRIPTION

When this state is entered, the contents of the

The data break facility allows I/O devices to

core memory address specified by the external

transfer information directly with the

device plus 1 is loaded Into the MB at TP2 time.
The word count, established previously by in-

core memory on a cycle-stealing basis.

structions,

the 2's complement negative num-

PDP-8/l

Up to

seven devices can connect to the data break
facility through the optional Data Multiplexer

Type DMOI .

ber equal to the required number of transfers.

The data break is particularly
word becomes
when incremented, the
•we -suited for devices which transfer large
computer generates a WC overflow signal and
amounts of information in block form.
supplies it to the device. During TS3 and TS4
times, the incremented word count is rewritten
Peripheral I/O equipment operating at high
in memory, the content of the MA is incremenspeeds can transfer information with the comted by 1, to establish the next location as the
puter through the data break facility more
address for the following memory cycle, and the
efficiently than through programmed means.
major state generator is set to the current address The combined maximum transfer rate of the
If the

state.

data break facility is over 7.8 million bits per
second. Information flow to effect a data
break transfer with an I/O device appears in

Current Address State

Operations during the second cycle of the threecycle data break depend upon the condition of
the increment CA inhibit (+1 —» CA inhibit) sig-

Figure 1

MEMORY
EXTENSION

computer from the I/O deAt TP2 time, the MB is loaded with either

nal supplied to the

vice.

TYPE MCa/1

ADDRESS

the contents of the memory cell following the

MEMORY
ADDRESS

DATA ADDRESS
^112 BITSl

CORE

word count (current address register) or the incremented contents of the current address re-

MEMORY

DATA INFORMATION
DATA

MEMORY
BUFFER
REGISTER

CA inhibit is at ground, the
contents are loaded; if CA inhibit is at -3V,

gister (i.e.,

EXTENDED DATA
ADDRESS (3 BITS)

CONTnOL

(MB)

(12

BITS IN)

DATA INFORMATION
OUT)

(12 BITS

ADDRESS
ACCEPTED

DEVICE

the incremented contents are loaded).

The
current address register may be incremented to
advance the address of the transfer to the next
sequential location. During TS3 and TS4 times,

OVERFLOW
BREAK STATE
DATA

BREAK
FACILITY

BREAK REQUEST
TRANSFER
^DIRECTION UN)

CYCLE SELECT

the content of the MB is rewritten into core

+ -» CA INHIBIT

memory, the address word in the MB is transfer-

INCREMENT M8

red into the

CONNECTIONS TO

V INPUT / OUTPUT

WORD COUNT

to designate the address to be
used in the succeeding memory cycle, and the

ma|or state generator is set to Break state.

Figure

Break State

Data Break Transfer Interface
Block Diagram

The actual transfer of data between the external device and the core memory, through the

programmed operations, the data
break facilities permit an external device to

MB, occurs during the Break state as during a

control information transfers.

In contrast to

single-cycle data break, except that the address is determined by the current content of the

MA rather than directly by the device.

Therefore, databreak device interfaces require more control
logic circuits, and are more costly than programmed-transfer interfaces.

I-DB4

Provide a logical signal to indicate
sing le-cycle or three-cyc le break operation.

Data breaks are oftwo basic types: single-cycle
and three-cycle. In a single-cycle data break,
registers in the device (or device interface)
specify the core memory address of each transfer
and count the number of transfers to determine
the end of data blocks. In the three-cycle data

e. Request a data break by supplying a
proper signal to the computer data break
facility.

break, two computer core memory locations per-

Single-Cycle Data Breaks

form these functions, simplifying the device
interface by omitting two hardware registers.

Single-cycle breaks are used for input data
transfers to the computer, output data transfers

In genera terms, to initiate a data break transI

from the computer, and memory increment data
breaks. Memory increment is a special output

fer of information, the interface control must

do the following.
a.

data break in which the content of a memory
address is read, incremented by one, and re-

Specify the affected address in core

written at the same address.

memory.

It is useful

for

counting iterations or externa events without
I

disturbing the computer program counter (PC)

Provide the data word by establishing

or AC registers.

the proper logic levels at the computer interface (assuming an input data transfer), or

provide read in gates and storage for the word
(assuming an output data transfer).

Input Data Transfers

Provide a logical signal to indicate
direction of data word transfer.

data break

Figure 2 illustrates timing of an input transfer
The address to be affected in core
.

COMPUTER TiME

»\*

PREVIOUS CYCLE

BY PROCESSOR

BREAK CYCLE -

m\*

NEXT CYCLE

SIGNAL MUST GO TO -3V AT START OF ADDRESS ACCEPT PULSE IF NEXT CYCLE IS NOT TO SE A BREAK

SAMPLE AT TP 4 -

USED TO SELECT BREAK CYCLE AT TP 4

J CYCLE

CYCLE

HARDWIRED FOR A OIVEN DEVICE

SAMPLED ATTP3,

t
DATA ADDRESS
INPUT LEVELS

END Of BREAK CYCLE

START OF BREAK CYCLE

EARLI5T TIME POSSIBLE TO REMOVE ADDRESS IS AT START OF BREAK CYCLE

UNPuT TO PROCESSOR)

TP,-T,

SAMPLED AT TP2 BY PROCESSOR -

CAN CHANGE ANYTIME AFTER TP Z

IN I-5V)

AVAIL IGNDl

NOT AVAIL.
IL.1-3V1

[—

-1

SAMPLED AT TPZ BY PROCESSOR

AVAIL IGND)

TIME DUniNG WHICH DATA MUST BE STROBED BY l/OOEVICt

AVAILABLE AT TP 2

—J

NOT AVAIL 1-3VI
REQUEST IGNDi

MUST RISE EARLIER THAN TP 4

REQUIRED J

MUST OCCUR ONLY WHEN B BREAK •

MUST FALL BY

"!_
GNO

r—

-3V

(OUTPUT TO I/O DEVICE!

tFigure 2

Single-Cycle Data Break Input Transfer Timing Diagram

I- DBS

normally provided in the device interface in

or three-cycle breaks, but not both, the cycle

the form of a 12-bit flip-flop register (data

select signal can usually be supplied from a

break address register) which has been preset

stable source (such as a ground connection or a

by the interface control by programmed transfer
from the computer.

bistable device as shown in Figure 3.

-3V clamped load resistor) rather than from a
Otherportionsof the device interface, not

External registers and control flip-flops supply-

shown in Figure 3, establish the data word In

ing information and control signals to the data

the input buffer register, set the address into

break facility and other PDP-8/l interface

elements are shown in Figure 3. The inputbuffer register (IB in Figure 3) holds the 12-bit data

word to be written into the computer core memory locationspecified by the address contained
in the address register

(AR in Figure 3).

Appropriate output terminals of these registers
are connected to the computer to supply ground
potential to designate binary Is. Since most
devices that transfer data through the data break
facility are designed touseeithersingle-cycle

the address register, set the direction flip-flop
to indicate an input data transfer, and control

the break request f ip-f lop . These operations
I

can be performedsimultaneously or sequentially,
but all transients should occur before the data
break request is made. Note that the device
interface need supply only static levels to the
computer, minimizing the synchromzing logic
circuits necessary in the device interface.

When the data break request arrives, the computer completes the current instruction, generat-

DATA BREAK INTERFACE
OF PDP-8/I

AR = ADDRESS REGISTER
IB = INPUT BUFFER
= TRANSFER DIRECTION FLIP-FLOP
BR = BREAK REQUEST FLIP-FLOP

CS = CYCLE SELECT (USUALLY SUPPLIED
BY FIXED WIRING TO -3V0LTS

RATHER THAN BY A FLIP-FLOP)

Figure 3

Device Interface Logic for SingleCycle Data Break Input Transfer

I-DB6

es an address accepted pulse (at TP4 time of the

put data register (OB in Figure 5) is usual lyre-

cycle preceding the data break) to acknowledge
receipt of the request, then enters the Break state
to effect the transfer. The address accepted

quired in the device interface to receive the

computer information. The device, and not the
PDP-8/I, controls strobing of data into this register. The device mustsupply strobe pulsesfor
all data transfers out of the computer (program-

pulse can be used in the device interface to

clear the break request flip-flop, increment
the content of the address register, etc .

med or data break) since circuit configuration

If the

break request signal is removed before TPl time
of the data break cycle, the computer performs
the transfer inone 1 .5 |js cycle and returns to
programmed operation.

and timing characteristics differ in each device.

When the data break request arrives, the computer completes the current instruction and

generates an address accepted pulse as in input

data break transfers. At TP4 time the address
supplied to the PDP-8/lis loaded into the MA,

Output Data Transfers

the Break state Is entered, and the MB Is cleared. Not more than 450 ns after TP4(at TP2
time), the content of the device-specified core
memory address is read and available in the MB.
(This word is automatically rewritten at the
same address during the last half of the Break

Timing of operations occurring inasingle-cycle
output data break is shown in Figure 4. Basic
logic circuits for the device interface used in
this type of transfer are shown in Figure 5.

Ad-

dress and control signal generators are similar to

cycle and Is available for programmed operations when the data break is finished.) Data bit
signals are available as static levels of ground
potential for binary Is and -3V for binary Os.

those discussedpreviously for input data transfers,

except that the transfer direction signal

must be at ground potential to specify the output transfer of computer information. An out-

————
I

PREVIOUS CYCLE
-

>)<l

SAMPLED AT TPl BY PROCESSOR

BREAK CVCLE -

»\m

NEXTCICLE

SIGNAL MUST GO TO -3V AT START OF AOCESS ACCEPT PULSE IF NEXT CYCLE IS NOT TO BE A BREAK

SAMPLE AT TP4 -

TP3

TP2

TPl

TP2

TPl

COMPUTER TIME

USED TO SELECT BREAK CYCLE AT TP 4

SAMPLED AT TP3, TYPICALLY HARDWIRED FORAGIVEN DEVICE

CYCLE

DATA ADDRESS
INPUT LEVELS
(INPUT TO PROCESSOR)

BVPTOCESSOR

IN (-3VI

START OF BREAK CYCLE

»U

EARLIST TIME POSSIBLE TO REMOVE ADDRESS 15 AT STARTOF BHEAK CYCLE

SAMPLED AT rp Z BY PROCESSOR

E^0 OF BREAK CYCLE

^^Zlh

CANthflNGE ANYTIME AFTEW TP J

1—

AVAIL. (6ND)

MOT AVAIL. ((-3V)

-I

SAMPLED AT TP 2 BY PROCESSOR

AVAIL (GNDl

TIME DURING WHICH DATA MUST BE STROBED QY I/O DEVICE

AVAILABLE AT TPZ
NOT AVAIL (-3V1

REQUEST (GNOl

MUST RISE EARLIER THAN TP 4

NO REQUEST (-3VI

iREOUIREDyi

MUST OCCUR ONLY WHEN B BREAK

MUST FALL av TP 4

USED FOR STROBING OUTPUT DATa

;_r
"t^

Figure 4

Single-Cycle Data Break Output
Transfer Timing Diagram

I-DB7

MB OUTPUT

OB = OUTPUT BUFFER
AR = ADDRESS REGISTER
D = DIRECTION FLIP-FLOP
BR = BREAK REQUEST FLIP-FLOP
CS = CYCLE SELECT (USUALLY SUPPLIED
BY FIXED WIRING TO -3 VOLTS

RATHER THAN BY A FLIP-FLOP)

Figure 5

Device Interface Logic for SingleCycle Data Break Output Transfer

The MB is cleared at TP2 time of each computer
cycle, so the data word is available in the MB
for approximately 1 .5 |js to be strobed by the
device interface.

of the output buffer register has DCD gates.

Conventional DCD gates require a minimum
setup time of 400 ns, which is adequately pro-

vided between the time when data Is available
In the MB and TS1 time.

Generation of thestrobe pulse by the device
interface can be synchronized with computer
timing through use of timing pulses BTS1 or BTS3,

which are available at the computer interface.
In

addition to a timing pulse (delayed or used

directly from the computer), generation of this
strobe pulse shou Id be gated by condition signa Is
that occur only during the Break cycle ofanout-

puttransfer.

Figure 6 shows typical logic cir-

cuits to effect an output data transfer. In this
example, the B Break signal and an inverted

transfer direction signal are combined in a

diode NAND gate to condition a diode-capacitor-diode gate. A buffered BTS1 pulse

DCD gate to produce the strobe
The BTSl pulse determines the timing of
the transfer In this example, since the Input
triggers the

Figure 6

pulse.

I-DB8

Device Interface for Strobing
Output Data

Signal interface for a memory increment data

By careful design of the input and output gating,
one register can serve as both the input and the
output buffer register. Most DEC options using
the data break faci ty have on ly one data-buffer
registerwith appropriate gating toallow it to

break is similar to an output transfer data break
except that the device interface generates an
increment MB signal and does not generate a

I i

strobe pulse (no data transfer occurs between

the PDP-8/I and the device). Timing of memory

serve as an output buffer when the transfer
direction signal isat ground potential or as an
input buffer when the transfer direction signal

increment operations appear in Figure 7, and an
example of the logic circuits used by a device

is-3V.

interface appears in Figure 8.

Memory Increment

An interface for a device using memory increment data breaks must supply twe Ive data address
signals, a transfer direction signal, a cycle se-

type of data break , the content of core
memory at a device-specified address is read Into
In this

the MB,

lect signal, and a break request signal to the
computer data break facility as In an output
transfer data break. In addition, aground potential increment MBsignal must be provided
at least 250 ns before TP2 time of the Break
cycle. This signal can be generated in the device interface by AND-combining the B break
computer output signal, the output transfer condition of the transfer direction signal, and the
condition signal in the device that indicates that
an increment operation should take place. When
the computer receives this increment MBsignal,

incremented by one, and is rewritten

at the same address within one l.Sjjscycle. This

feature is particularly useful in building a histo-

gram of a series of measurements, such as in
pulse-height ana lysis applications. For exam.

ple, in a computer-controlled experiment that

counts the number of times each value of a parameter is measured, a data break can be requested
for each measurement, and the measured value
can be used as the core memory address to be

incremented (counted).
TPI

TP!

oDMPUTEH TIME
J

SREAK REQUEST SIGNAL
(INPUT TO PROCESSOfll

:j [*-

(INTERMAL)

TP4

TPI
1

SAMPLE AT TP 4 —»|

TP2

TP3

111

TP4

p— SIGNAL MUST GO TO -3V AT START OF ADDRESS ACCEPT PULSE

SAMPLED A T TPI BY PROCESSOR

L- SET AT TP

BREAK SVNC FLIP FLOP

TP3

TPZ

TPI

NEKT CYCLE IS NOT TO BE A BREAK

I*— USED TO SELECT BREAK CYCLE AT TP 4

3 CYCLE

-1

CYCLE SELECT
(SAMPLE TO PROCESSORl

'i^— SAMPLEDATTP3, TYPICALLY HARDWIRED FOR AG1VEN DEVICE

GND

U— START OF BREAK CYCLE

B- BREAK SIGNAL

END OF BREAK CYCLE

—J

-3V

GND

DATA ADDRESS
INPUT LEVELS

av
BY n1,^J«l™
PHlJl,t5i»U"

1
1

(INPUT TO PROCESSORl

-3V

-* *- EARLIST TIME POSSIBLE TO REMOVE ADDRESS IS AT START OF BREAK CYCLE

GND -

TP4-TP1
,3S-45MSEC

ADDRESS ACCEPT PULSE
(OUTPUT TO I/O DEVICE!
-3V
OUTIGNO)

-1

TRANSFER DIRECTION

SAMPLED AT TP2 BY PROCESSOR

(INPUT TO PROCESSOR)
IN (-3V)

AVAIL.IGNDI

* DATA SIGNAL INPUT TO MQ

,i.S,¥'K2«1iS!.'S'lf?o%='rtl

(INPUT TO PROCESSORl

WTAVAIL,(-3V)

-W

K— CAM CHANGE ANYTIME AFTER TP2

|- ""'^=° " '" - -==«'>«

-1

AVAIL IGNDl

OUTPUT DATA AVAILABLE IN MB

AVAILABLE AT TP;

»L

TIME DURING WHICH DATA MUST BE STROBED BY I/O DEVICE

-J

(OUTPUT TO I/ODEVICEI
40T AVAIL (-3V1 -

REQUEST (GNDl

MU5TRISEEARLIERTHANTP4

,„iss=;s%"cisi
''

REQUEST (-3V1

eTS3

-J

l^OmRED^

MUST OCCUR ONLY WHEN B BREAK -

L— MUST FALL BY TP 4

GND -

(OUTPUT TO 1/0 DEVICE)
-3V

GND
BTSl
(OUTPUT TO I/O DEVICE)

-3V

GND

11
MEMORY INCREMENT
OCCURS
L
p— PULSE
AND THE WORD COUNT OVERFLOWS
IF

WORD COUNT OVERFLO*
(OUTPUT TO I/O DEVICE)
-3V

**SI6NALN0TUS[GD
SHOWN FOR RE FEHANCEONLY

Figure 7

Memory Increment Data Break Timing Diagram
I-DB9

REQUESTED

|
|

Figure 8

Device Interface Logic for Memory
Increment Data Break

forces the MB control element to generate a

count MB pulse at TP2 time to increment the
content of the MB.

data transfer operation to skip on the overflow

condition to determine the cause of a program
interrupt, to clear the overflow flip-flop, and
to clear the device flag.

The device Interface logic shown in Figure 8,
samples the word count overflow signal to determine if word count overflowed when the data

Note that the devices

that use data break transfers almost always use

programmed data transfers to start and stop operation of the device, to initialize registers, etc.,

word was incremented. If overflow occurs, this
and do not rely on data break faci lities alone to
logic requests a program interrupt to allow the
control their operations.
program to take some appropriate action, such
as incrementing a core memory for numbers above Three-Cycle Data Breaks
4096, stopping the test to compile the data
gathered to the current point in the operation,
reinitializing the addressing, etc. The logic in
Figure 8 uses the select code of programmed

Timi ng of input or output three-cycle data breaks
is

shown in Figure 9.

The three-cycle break

uses the block transfer control circuits of the

I-DBIO

TPf

TP2

TP3

TP4

TPl

TP3

TP2

TP4

III

SET AT TPl

TP2

TPl

TP4

TP3

III

» U CURRENT ADDRESS STATE -

t*— WORD COUNT STATE -

TP3

SAMPLED AT TP4

SAMPLED AT TP 3, TYPICALLY HARD WIRED FOR A GIVEN DEVICE

ALWAYS AVAILABLE
-

SAMPLED ^T TP4, IF Ff BECISTER SUPPLIES THESE INPUTS TIMING IS IDENTICAL To THAT ShO*N OH FiG

r—

T IGNDl

SAMPLED AT TP 2 OF BREAK CVCLf!
N I-3V1

rP2

TPl

— BREAK CYCLE

U- 3AMIIPLED AT TP2 Br PROCFSSOfi

LATEST POSSIBLE TIME TO SPECIFY INPUT DATA IS 600 NS BEFORE TP 2 —•J
NOT AVAIL 1-SVl AVAIL IGNOI
AVAJI Afti F AT TPP

NOT AVAIL (-3Vl

—fcJ TIME DURING which DATA MUST

11^ STROBED BY I/O DEVICE

R.
BIT CA

^!
^

TPZ OCCURS ONLY DURING LAST TRANSFER OF A BLOCK TRANSFER

Ll,
[*" SAMPLED AT TP2 BY PROCESSOR

IETP2 —

START OF BREAK CYCLE

GND

-3V

GND
I

-3V

Figure 9

"l_J

"LJ"

E^D OF BREAK CYCLE

IT
^J"

"LJ

Three-Cycle Data Break Timing
Diagram

computer. The block transfer control provides
an economical method of controlling the flow
of data at high speeds between PDP-8/l core
memory and fast peripheral devices, e .g ., drum
disk, magnetic tape and line printers, allowing
transfer rates in excess of 200 kc

fer data to or from core memory, the three-cycle

data break facility performs the following seq-

uence of operations:
a. An address is read from the device to
indicate the location of the word count
register. This address is always the some

The three-cycle data break facility provides
separate current address and word count registers
in core memory for the connected device, thus

for a given device; thus it can be wired in

eliminating the necessity for flip-flop registers
in the device control. When several devices

are connected to this facility, each is assigned

fore rewriting .

a different set of core locations for word count
and current address, allowing interlaced operarate does not exceed 200 kc . The device speci-

becomes Oasa resultof the addition, a WC
overflow puJse will be transmitted to the device. To transfer a block of N words, this
register is loaded with -N during programmed

fies the location of these registers in core memory,

initialization of the device . After the block

and does not require a flip-flop register.

The content of the specified address Is
1
is added to it be-

read from memory and

tions ofal devices as long as their combined
I

the content of this register

thus the software remains the same regardless of

has been fully transferred this pulse is gener-

other equipment that may be connected to the
machine. Since these registers are located in

ated to signify completion of the operation.

standard memory, they may be loaded and unloaded directly without the use of lOT pulses.

In a procedure where a device requests to trans-

though the content of this register is normally

I-DBll

The next sequential location is read from

memory as the current address register. Al-

incremented before being rewritten, an incrCA inhibit) signal from
ment CA inhibit (+1
the device may inhibit incrementation. To
transfer a block of data beginning at location
A, this register is program initialized by load-

Increment CA Inhibit. When ground potential, this device-supplied signal inhibits inb.

crementation of the current address word.

ing with A-1 .
d .

mitted to the device when the word count be-

comes equal to zero.

The content of the previously read current

address is transferred to the

MA to serve as the

In summary, the three-cycle data break

entered similarly to the single-cycle data break,

This transfer may

with the exception of supplying a ground-level

go in either direction in a manner identical to

cycle select signal to allow entry of the
(Word Count) state to increment the fixed core-

address for the data transfer.

the single-cycle data break system.

memory location containing the word count. The
The three-cycle data break facility uses many of
the gates and transfer paths of the single-cycle
data break system, but does not preclude the use
of standard data break devices. Any combination
of three-cycle and single-cycle data break devices can be used in one system, as long as a
multiplexer channel is avai lable for each . Two

device requesting the break supplies this address
as in the one-cycle data break, except that this

address is fixed and can be supplied by wired

additional control lines are provided with the

ground and -3V signals, rather than from a register. The sole restriction on this address is
that it must be an even number (bit 11 = 0)
Following the WC state a CA (Current Address)
state is entered in which the core memory loca-

three-cycle data break.

tion following the

These are:

PC +

WC address (bit 11=1 after

= >PC) is read, incremented by one,

restored to memory, and used as the transfer

a. Word Count Overflow. A level change
to -3V, from TP2 to TP2, is transfrom

GND

address (by MB = >MA).

Then the normal B

(Break) state is entered to effect the transfer

I-DB12

MC8/I MM8/I

EXTENDED MEMORY
OPTION
FUNCTIONAL DESCRIPTION

MC8/I MM8/I

EXTENDED

MEMORY
INTRODUCTION

Local memory timing for both field
is

AddiHonal capacify can be added io the standard PDP-8/I4K core memory in 4096-word increments. The addition of seven 4K fields, plus
the standard memory, yields the maximum storage capacity of 32,768 words. Figure 1 illustrates the extended-memory organization. As
shown in this block diagram, the PDP-B/l main
frame contains: the standard memory (field 0);
and MCB/I which is the first memory extension
(field 1) and the memory selection control (DBS-MC8I-0-l)for all eight memory extensions.

MM8I's provide external memory expansion with

common local memory timing control for every
two 4096 word segments. This control, and associated read/write and addressing techniques

(D-BS-MC8I-0-2 through 4), does not differ
from that of the basic PDP-8/L as discussed in
Chapter 4.

A discussion ofextended memory control follows

CENTRAL
PROCESSOR
SIGNALS

CORE MEMORY
FIELD

I0-4K)

fhCMORY TIMfNoV
CONTROLLER O

CONTROLLER
FOR FIELDS
Z AND 3

FOR FIELDS

AND

(MM8/I)

CORE MEMORY

_^B_BUFFERS_ J
I-

» MCBMB

fi3

HY •«ER
JS

CORE MEMORY

I
'

"r-

FIELD 1
l4.eK)

FIELD 3
nz-t6Kj
I

W
I

CORE MEMORY

ENABLE
'

.instruction'

|«
SAVE
FIELD
iREGISTEHS;

FIELD
REGISTER

MEMORY
CONTROLLER 2

FIELD 4
(16-20K)

CATE
^1

ENABLE ^

EA0,EAI.EA2

FOR FIELDS
4 AND 5
(MM 8/1)

CORE MEMORY

GATE
I

r" BREAK
FIELD
^H REGlSTER

MEMORY EXTENSION l_

(8-1ZK)

MEMORY

1^
'
1

CONTROL MCe/1

EAO, EAI,EA2

L'?}^:

MEMORY

» TIMING
I

CHAIN
I

STROBE

THE MM8/1 LOGIC FOR FIELDS 0-5
CONTAINS THE SAME CIRCUITRY AS
SHOWN IN THE EXPANDED DIAGRAM
PORTION FOR FIELDS 6 AND 7

FIELD D/FIELD

AND Y
AXIS

ADDRESS
SELECTORS

CORE MEMORY
FIELD

-*-

(24-2eK)

s
DRIVERS
s'

STROBE
K AND y

ADDRESS

MA* SELECTORS

s
**

a
«

FIELD

AXIS

CORE MEMORY
FIELD 7
128- 32 K)

INHIBIT

«-n

Figure

and field 1

provided by the basic memory.

DRIVERS

Extended Memory Block Diagram

I-EM1

ENABLE
GATES

LOAD ADD through the DFSR, or under program

LOGIC DESCRIPTION

control by a CDF instruction.
Instruction Field Register

This 3-bit register determines the memory field

During a program-Interrupt operation the content

to be used for storage and retrieval of program-

of the DF is automatically stored in the Save
Field register and restored to the

The IF register may be loaded

instructions.

pletion of the interrupt subroutine by the RMF

from either the IF switch register (IFSR) or the
instruction buffer (IB) register.

All

program-

instruction.

executed transfers to the IF enter from the IB.
The content of the IFSR, however, is loaded
directly into the IF, and the IB, under manual

Instruction Buffer Register (IB)

controlof the LOADADDkey. WhenaJMPor
JMS Instruction Is executed, the content of IB,
is

DF upon com-

This 3-bIt register provides input buffering for

data transfers made into IF under program control. Manual transfers from IFSR are made di-

transferred to the IF.

rectly Into IF and, simultaneously. Into IB. This

When an Interrupt occurs, the contents of the

transfer of data into both registers

necessary

prevent inadvertent changing of the content

IF are transferred to the save field register (SF).

At the end of the interrupt subroutine the con-

of IF.

tents of the SF are restored to the IF through

execution time of every JMPor JMS instruction .)

(The output of IB is loaded Into IF at the

the IB by execution of the RMF Instruction.
Transfers into IBaremadeunder program control

When the CIF instruction is executed (refer to

during the execution of CIF (change instruction

extended memory instruction descriptions In

field)

are transferred to the IB; the contents of the BI

and RMF (restore memory field) Instructions. The content of IF, however, remains
unchanged until the execution of the next JMS

are transferred to the IF at the execution of a

or JMP instruction strobes the output of IB into

JMP or JMS Instruction. During the time between the CIF instruction and the JMP or JMS,
program interrupts are inhibited.

IF.

this chapter) the contents of MB06 through MB08

Save Field Register (SF)
Data Field Register (DF)
This 6-bit register provides temporary storage,
This 3-bit register determines the field to be

used for data storage and retrieval

The DFcan

be loaded from three discrete sources: MB06
through MB08, the Save Field, and the Data
Field switch register (DFSR).

DF is loaded manually from the
DFSR by actuating LOAD ADD. While the

Initially, the

program is running, a CDF (change data field)
Instruction can be used to alter the content of
the DF to permit selection of a different field
of memory.

Bits 06,

during a program interrupt, for the contents of

both IF and DF.

This is necessary to permit IF

and DF to be cleared so the program interrupt
At the conclusion
of the interrupt subroutine, an RMF instruction
loads the contents of SFO-2 Into IB for subsequent transfer Into IF, and the content of SF35 Into DF. The last instruction in thesubroutine
(JMP I 0) completes the transfer from IB to IF.
subroutine starts In field 0.

Break Field Register (BF)

07, and 08 of the CDF

Instruction contain the desired field address.

This 3-bit register determines the field to be

Once loaded, the content of the DF remains

used for storage and retrieval for data transfers

unchanged until altered either manually by

from I/O devices using the data break facility.

I-EM2

data handling instructions are AND,TAD,ISZ,
and DCA. In addition, when the Start, Exam,

The BF is loaded from the EXT DATA ADD 0, 1
and 2 lines byTPSofthe cycle before a data
break Is initiated.. Each device puts its own
fie Id address on the EXT DATA ADD 0, 1, and

orDepkey is actuated, the IF register is gated
to EAO, EAl, and EA2 to generate the memory
field select code. The DF register is gated to
the extended addressing bits when any indirectly-

2 when It requests a break.
Field Selection (EAO, EAT, EA2)

addressed memory-reference Instruction other

As Figure 1 illustrates, the MC8/1 Memory Ex-

than JMPor JMSisexecuted(AND,TAD,ISZor
DCA). The BF decoder a lows the BF to generate

tension Control contains gating that allows access

the memory field select code during a break

to all memory fields. The gate outputs EA0,EA1,
and EA2 (drawing BS-MC8I-0-1; sheet 1), taken
collectively, forma code that selects one of the
memory fields. TheEAOandEAl levels enable
one of the fourmemory controllers (each of which
controls two memories). The EAOand EAl conand 1), 01 (for
figurations are: 00 (for fields
fields 2 and 3), 10 (for fields 4 and 5) and 11 (for
fields 6 and 7). The third enable level (EA2)
specifies which of the two memory fields within
the group indicated by EAO and EAl is selected.
Table 1 clarifies the field select coding, and
the distinction between the enable levels.

cycle.

set necessary to control program execution with

Field

Controller

EA2

Selected

This instruction contains the octal code 62N1,

where N is the octal numberof the field to which
control is changing. The CDF command Is used
prior to storing or retrieving data with any indirectly-addressed memory-reference instruction

]J
1
1
1
1

O']

n
1/

the extended memory option.

Change Data Field (CDF)

0^
oj

BS-8I-0-7) level in the processor from the time
a CIF instruction is decoded, until a JMP or
JMS command finishes the CIF command. This
prevents honoring of an interrupt before the
field is changed. Interrupt synchronization is
restored after the IF is loaded from the IB, allowing further program interrupts to occur.

The following paragraphs describe the instruction

Memory
Selected
(EAO and EAl)

OK (drawing

DESCRIPTIONS

Field Select Codes

EAl

The interrupt inhibit (drawing BS-MC8I-0-1;
sheet 2) logic disables the INT

EXTENDED MEMORY INSTRUCTION

Table 1

EAO

Interrupt Inhibit

2
1

6
7

other than JMP or JMS.

This instruction is

generated by combining the MEM EXT level
(62), the contents of MB06 through MB08 (N),

ondMBl
The memory field enable gates maybe activated
from one of three sources: the IF register, the
DF register, or the BF register. The IF register
isgatedtothe EAO, EAl, andAEA2 levels at all
times except during a break cycle or an indirectly referenced data handling instruction. The

(1), with the EXT

GOsignal (drawing

BS-MC8I-0-1, sheet 2).

Change Instruction Field (CIF)
This instruction contains the octal code 62N2,

where N Is the octal number of the field to

I-EM3

tor bits AC06 through AC08 in the same manner
which the program is changing. The CIF command Is executed prior to a JMP or JMS instruc- as with the RIB Instruction.
tion. The 62N2 instruction allows MB06 through
Read Instruction Field (RIF)
MB08(N) to be loaded into the IB by combining
these bits with MEM EXT (62), and MBIO (DrawThis Instruction (octal code 6224) reads the coning BS-MC81-0-1, sheet 2). The IB is loaded
tents of IFO through IF2 onto the ME9 through
by EXT GO and the conditions MB09 = 0,
MEn lines. The data is transferred through the
MB10=: 1, MBll = 0. The IB is then transferred
INPUT
BUS 06 through 08 to bits AC06 through
to the IF when the next JMP or JMS command
AC08 in the same manner as with the RIB and
is executed.

RDF instructions.
Restore Memory Field (RMF)

ENGINEERING DRAWINGS

This instruction (octal code 6244) restores the

contents of the SF to the DF and IB registers.

The following drawings pertaining to the MCB/I,
The conclusion of an interrupt subroutine (JMP
SF ENABLE (Draw- MM8/I are included in this section.
I 0) loads the IF from the IB.
ing BS-MC8I-0-1, sheet 2) allows bits SF3
Revision
Title
through SF5 to be loaded into the DF. The con- Drawing Number
tents of the IB are transferred to the IF by executing a JMP or JMS instruction.

D-BS-MC8I-0-1

Read Interrupt Buffer (RIB)

D-BS-MC8I-0-2
D-BS-MC8I-0-3
D-BS-MC8I-0-4

Memory Exten-

sion Control

The purpose of this instruction Is to allow storing
that same field In memory if the power failure
option is installed. This instruction (octal code
6234) reads the contents of the 6 -bit S F register
Into the AC on the ME6 through MEl 1 lines
(Drawing BS-MC8I-0-1, sheet 2).. These lines
activate the INPUT BUS 06 through 1
lines In

D-MU-MM8I-0-1
D-BS-MM8I-A-1
D-BS-MM8I-A-2
D-BS-MM8I-A-3

Not Available

Memory Control

X Axis Selection

Sense Amplifiers

and Inhibit Drivers

X Axis Selection,

Field

D-BS-MM8I-A-4

the processor.

Y Axis Selection

C
C
C

Inhibit Drivers

Y Axis Selection,

Field

Execution of the RIB command generates MEM

EXT I/O ENABLE (Drawing BS-MC8I-0-1 , sheet
MEM EXT AC LOAD ENABLE which
produce AC LOAD and lO ENABLE In the
processor. lO ENABLE allows INPUT BUS 6
through
lines to load into the AC when AC
2), and

0-BS-MM8I-B-1

Inhibit Drivers,

D-BS-MM8I-B-2

X Axis Selection,

D-BS-MM8I-B-3

Y Axis Selection,

Field

1 1

LOAD Is generated
Read Data Field (RDF)
This instruction (octal

DF2 onto the ME6 through
The data Is transferred to accumula-

tents of DFO through

ME8 lines.

code 6214) reads the con-

B-CS-G020-0-1
B-CS-G021-0-1
B-CS-G221-0-1
B-CS-G228-0-1
B-CS-G229-0-1
B-CS-G624-0-1
B-CS-G805-0-1

I-EM4

Memory Selector

H
H
D

Inhibit Driver

Sense Amplifier
Sense Amplifier

Not Available

Resistor Board

Negative Regulator

Drawing Number

C-CS-G826-0-1
B-CS-M1 13-0-1
B-CS-Ml 15-0-1
B-CS-M21 6-0-1
B-CS-M3 10-0-1
B-CS-M360-0-1
B-CS-M61 7-0-1

Title

Revision

Regulator Control

10 2-Input NAND
Gates
8 3-Input NAND
Gates

Six Flip-Flops

Delay Line
Variable Delay
6 4-Input NOR

B
B

Buffers

B-CS-M720-0-1

Memory Detection

I-EM5

-0-lQjn Sa a 2

-EM7

«rty ot Digital Equipment Corporation and shall not b
iwwtiue"^ 0' copied or u»ed in irtiole or ir part a
Hie basis for ttie maniriactupe or salt of item*

w"—

I-EM9

2— 0— I83W Sa a 2

—

^^'"

MaannN

This drawing and spacificatiam, herein, are the property of Digital Equipment CorpoWto^ and shall not be
leprodutted or copied or used in wHole or in part as
he basis for the mennfacture or sale of items without
iritten permission.

WO 2 5

C2f D2
T2 IS6»

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MEMORY
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FIELDCDI-

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NOTES'.
00

I.DRAWIN6 DEPICTS MCSI-B
2.F0R MCSI'A REMOVE

6223

LOCATION A57
3. SIGNAL NAMES INQCATE
ASSERTED STATES FOR HIGH (H)
LEVELS PER DEC STD 054
IN

UNLESS OTHERWiSE SPECiFIED

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UNLESS OTHERWISE SPECIFIED
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'^f^^

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^--

DECIMALS

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DATE

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MCBMB03C05

MCBMB06 (0)

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4AP2 MR2

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*BK2 *BL2

BH2

BK24

*BP2 •BR2

aM2i

iBL2

BP2i

BN2

BR2)

302[-)
UNLESS OTHERWISE SPECIFIED

NOTE:
SIGNA^ NAMES INDICATE
ASSERTED STATES FOR
HIGHvH) LEVELS PER DEC
STD

D*VTE

UNLESS OTHERWISE SPECIFIED

DIMENSION

DATE

INCHES

TOLEfWNCES
OeCIMALS

FRACTICmS

ANGLES

I .005

* 1/64

± O'W

FINAL SURFACE QUALITY
REIMOVE lURRS ANt> tREAK SHWP

CORNERS

mrk.^^

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EQUIPMENT

SDIDDSD CORPORATION

DATE

SENSE AMPS $
INHIBIT DRIVERS

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RRST riecn'Viw
USED ON

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:-ua-mmbi -0-0 SIZE CODE
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UNLESS DTh«RW13E SPECtflB)

TOLQUNCES

NEG CLAMP

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rwut. auVTACt OUAUTV

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EQUIPMENT
CORPORATION

BXff

?t£2

SELECTION
FIELD

X AXIS

il^ii

CORMCM

"^
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-UA-MM8I —0 -0
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SHEET

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•rty of t>«iW Equtpmwrt CorpoWion and dwll not ba
r*ptMuC«d or npiKl or uMd in wtat* ar in pwt
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tor ttM mwiubckir* or ni* of

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MB PARITY ODD
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A 23

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MCBMB02 Co)

MCBMB03 (0)

AI3

MCBMB04 CO)

MCBMB05 (0)

MCBMBO6CO)

G228

812

BI3

MCBMBIO CO)

NICBMB09 (0)

MCBMBOS (0)

MCBMB07 C03

MCBMBIt (0)

-L'

MEMORY
SUPPLY

-4

MEMORY
SUPPLY

-5

MEMORY
SUPPLY

-6

DiVG DEPICTS MM8IB.
FOR MM8IB WITHOUT PARITY
REMOVE G228 IN LOCATION A23.

CjIGNAL names. INDICATE
ACjSERTED STATES FOR
HIGH(H)

LEVELS PER DEC

STD C 54

EQUIPMENT

UNLE^ OTHERWISE SPECIFIED

-I-

UNLESS OTHERWISE SPECIFIED
-

TOLERANCES
DECIMALS

FKACTIONS

ANOLES

OHAL SURFACE (JOAUTT

HMOVE aURKS AND BMAK SHW
COKNEM

DATE

SUDISD CORPORATION

^-''^^Af.

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C-UA-MM81

ry.

0-0 SIZE CODE

NUMBER

D B5 MM 87 —

;
I

D£C FORM NO

I-EM25

I-EM27

1-EM29

JNLESS OTHERWISE INDICATED!

RESISTORS ARE l/4W,S%
MF RESISTORS ARE l/8W,l%
CAPACITORS ARE .OIMFD.IOOV,
20%
DIODES ARE 0662
El, E3 ARE MCIS408
E2 IS DEC7400N
PIN 7 ON EACH 10 • OND
PIN 14 ON E2= + 5V
PIN 2 0lJ EI,E3=+5V

USE THE ETCH BOARD OF THE 6021

B-CS-G020-0-1

Sense Amplifier

B-CS-G02i-0-l

Sense Amplifier

UNLESS OTHERWISE INDICATED!

RESISTORS ARE I/4W, 9%
MF RESISTORS ARE l/8W,l%
CAPACITORS ARE .01 MFD, I00V,20%
DIODES ARE 0662
E4 a E5 ARE MCIS40
E3 IS DEC 7400 N
PIN 7 ON EACH IC > SNO
PIN 14 ON E3=+5V
PIN 2 ON EI,E2,E4,E5=+5V
CI, E2,

I-EM31

UNLESS OTHERWISE INDICATED:
TRANSISTORS ARE 0EC2904
DIODES ARE D672
RESISTORS ARE I/4W, 5%
RESISTORS ARE 1,500
CAPACITORS ARE330MMFD,I00V, 5%
EZIS DEC7400N
ES a El ARE DEC7440N
PIN 7 ON EACH IC ' SND
PIN 14 ON EACH IC-+5V

B-CS-G221-0-1

Memory Selector

C2,TI

8ND

IRI

UNLESS OTHERWISE INDICATED:
TRANSISTORS ARE DECI008
RESISTORS ARE I/4W, 5%
TRANSFORMERS ARE T2037
IC'S ARE 0EC7440N
PIN 7 ON EACH IC = SND
PIN 14 ON EACH IC'-I-SV
CAPACITORS ARE .OIMFD IC0V,20%
,

20MFD. 50V. -10 + 75%

B-CS-G228-0-1

Inhibit Driver

I-EM32

R5
se

--WV-

M O-

FO
R6

470

UNLESS OTHERWISE INDICATED;
CAPACITORS ARE ESQ MMFD
RESISTORS ARE lOW, 1%, LOW INDUCTANCE

20 MFD, SOV

I/2W

10%
CI
.01

B-CS-G624-0-1

MFD

Resistor Board

TAB 2

8ND<

—<

-TAB4

?R2

10,000

< 10,000

1/4W

f I/4W

10%

-O AE
-O AF

-O AH
-O AJ
-O AK
-O AM

UNLESS OTHERWISE INDICATED:
CAPACITORS ARE 20MFD SOV
TABS ARE 2S0 SERIES FASTON TABS TYPE 80469-2 lAMP INC)
Ql IS MOUNTED ON HEAT SINK, WAKEFIELD TYPE NC-623-A USING AN
ANODIZED ALUMINUM INSULATING WASHER S WAKEFIELD TYPE 120

THERMAL JOINT COMPOUND
PARTS LIST A-PL-Ge05-0-0

B-CS-G805-0-I

Negative Regulat-or

I-EM33

R39

10%

I2J

®r5
5
CO

220

'T^IOOV

45-

'^i£>^'

750

5%
TO + TEMP. COEFF. THERMISTOR 330
25"c CARSORUNDUM A0905P-8 OR EOUIV.

UNLESS OTHERWISE INDICATED:
TRANSISTORS ARE DEC3009B-S
RESISTORS ARE 1/4W, 5%
CAPACITORS ARE .0) MFD
El a E3 ARE DEC740ON
E2 IS 0EC744ON
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC = +5V

±10%

C-CS-G826-0-1

Regulator Control

+5V

NOT USED -I5V

-62

OND

•C2, Tl

A
•f

—•— + 5V

-VI

+3V
•Rl

>R3

+3V

S;C2
*

notes:
pin 7 on each ic • ond
pin 14 on each ic

+9v

B-CS-Mlia-O-l

10-2 Input NAND Gates

+SV
NOT USED -IBV -

ONO-

-A2
-B2
-C2,TI

f5V

[.,

—

y,i2

02E2F2-

N2P2R2-

2
1

\-)l2

—
4

>•

—

4
5

\>S

notes:
pin 7 on each ic'ond
PIN 14 ON EACH IC "t'SV

B-CS-MI 15-0-1

J2K2L2-

Vl8

8-3 Input NAND Gates

I-EM35

T2Ul

U2 -

V2-

^r\>i

OND

CLEAR
.,

4 SET

PZ
9

If,

-q

P-— HI

C
II

C
3

NOTES:
PIN 7 ON EACH IC ' 8ND
PIN 14 ON EACH IC-+SV

B-CS-M31 0-0-1

Delay Line

UNLESS OTHERWISE INDICATED;
TRANSISTORS ARE DEC3009B
RESISTORS ABE I/4W, 5%
CAPACITORS ARE

.01

MFD, lOOV, 20%

DEC7440N
DEC7400N
PIN 7 ON EACH IC = OND
PIN 14 ON EACH IC=+5V
DIODES ARE D664
OLD IS DECIG-06530

El IS

t--c

KZ LZ MZ NZ PZ RZ SZ TZ

B-CS-M36G-0-1

8ND

D
II

AZ
ez

+ 5V

<-3V

NOT USED -CSV

Variable Delay

I-EM36

::i:oz ::i::c3

T T SNO

notes:
PIN 7 ON EACH IC=eND
PIN 14 ON EACH IC = +5V

Variable Delay M360

B-CS-M360-0-1

+-SV

-A 2

NOT USED -I5V

-B2

QND

Al
Bl
CI
01

F
HI
Jl
Kl

D2 E2 FZ
HZ

K2
L2
M2
N2

F>
E>

~i0X

MINI

R2
S2
T2
U2

13,
'

notes;
pin 7 on each ic'snd

pin 14 on each ic =*sv
use the etch board of the mii7

B-CS-M61 7-0-1

6-4 Input NOR Buffers

I-EM37

F>
F>

-CZ, Tl

MEM
START
V

>RI

>Ri

>3,000

^TS/>00

CI
«.•

c«

:mfd^c2 :^C3 TfZ:c4 ^c» :i:.ooi
3av

20%

5
00

UNLESS OTHERWISE INDICATED:
CAPACITORS ARE .01 MFD
DIODES ARE 0684
RESISTORS ARE IMW, S%
TRANSISTORS ARE DEC9009B
El, E3, E4 ARE DECT400N
PIN 7 ON EACH IC < GND
PIN 14 ON EACH IC < f SV
E2 IS DEC7460N

B-CS-M720-0-1

Memory Detection

MP8/I
MEMORY PARITY

OPTION
FUNCTIONAL DESCRIPTION

MP8/I

MEMORY PARITY
INTRODUCTION
The MP8/I option provides a data-transmission
check of each word written into or retrieved
from memory. A parity bit is generated, and is
written into memory with each MB data word
This option uses "odd parity" which generates a

an even number of these are asserted. If an even
number are, the number of MB bits asserted is
even and a parity bit Is generated.

MB PARITY ODD, which is the fourth section
output, is active and the P Inhibit Driver (Drawing BS-8I-0-14)

disabled.

This allows a

be written with the MB word into the address

1
In the parity bit when the contents of the MB
contain an even number of Is. The resulting

specified by MA.

number of Is in both the MB and parity bit is
always an odd number. The contents of the MB

Parity Check

Network

and parity bit are sensed when the memory read
function occurs, and if the total (MB and parity) After the data word and parity bit (PB) are read
number of Is is even, a parity error is generated. from memory to the SENSE register, the register
outputs (designated MEMOO through MEMll) are
The MP8/I option, contained within the PDP-8/f applied through Inverters to the parity-checking
processor main frame, replaces the 12-bit core
network (Drawing BS-MP8I-0-1, sheet 2). This
memory system with a 13-bit system that Includes network senses the number of Is read from a
driving, inhibiting, sensing, parity generating,
memory address in the same way as the parity
and parity-checking circuitry, as well as a core- generator senses Is In the MB. The parity bit
memory array constructed of 13 planes. The
Is sampled in the fourth section, with Inversion
thirteenth plane stores the status of the parity bit of MEM signals occurring prior to the first three
in

each memory address.

sections.

The total memory word consisting of parity (MEMP)
and data (MEMO-P) (Drawing BS-8I-0-14) should
contain an odd number of Is. If It does, MEM

LOGIC DESCRIPTION

The following paragraphs describe the parity
PARITY ODD (the fourth section output) is active
generation and checking networks, and the parity- and program operation continues normally. When
error condition.
the parity and data contains an even number of
Is,

^EM PARITY EVEN output

active.

Parity Generator

Parity Error

The parity generator network consists of four
sections (Drawing BS-MP8I-0-1 , sheet 1) each
of which samples inputs and provides specific
outputs when the number of asserted inputs is
odd. Three of these sections sample sets of four

When an odd number of data bits are "picked
up" or "dropped", MEM PARITY EVEN is generated, and combined with TP3 of the Fetch
cycle of all Instructions. This sets the PARITY

MB inputs (using both MB polarities) to deter-

ERROR flag (Drawing BS-MP8I-0-1, sheet 1),

mine within the sets of 4 an odd number of asserted bits. The fourth section samples the out-

indicating that the data word In the MB has been
altered, and

puts of the first three sections to determine if

flag

I-MP1

is Incorrect.
The PARITY ERROR
connected to the PDP-8/t interrupt line

MP INT, and generates INT RQST (Drawing

BS-8I-0-10).

code 1). MP SKIP is produced by combining
the decoded lOT address level (10), and lOPl
with MP INT.

MP8/1 PROGRAM INSTRUCTIONS
Clear Memory Parity Error (CMP)

Two instructions are used with the memory parity
option.

Their generation and application are

This instruction (octal code 6104) clears the PE

described below.

flip-flop after a parity-error condition has been

Skip On No Parity Error (SMP)
This instruction (octal code 6101) senses the

PARITY ERROR (PE) flag status.
flop contains a 0,

If the

PE flip-

MP SKIP (Drawing BS-MP8I-

1) is produced generating I/O SKIP
(Drawing BS-8I-0-10). I/O SKIP forces the PC
to increment by 1 , thus the next sequential

acknowledged by the PDP-8/I. The 6104 instruction decodes to produce an IOP4 pulse and
the octal address level 10. These two signals
combine in the MP8/1 option logic to produce
CLR PARITY ERROR (Drawing BS-MP8I-0-1,
sheet 1), which clears the PE flag.

0-1, sheet

instruction

skipped.

the PE flip-flop con-

The following drawings pertaining to the MP8/I
are contained in this section.

tains a 1, the next instruction occurs and an

appropriate subroutine is initiated.

When the SMP instruction is executed, the octal
code 6101

decoded in the following manner.

through 2 of the instruction (octal code 6)
decoded within the processor specify an lOT
instruction. Bits 3 through 8 are decoded by the
Bits

ENGINEERING DRAWINGS

Drawing Number

Title

D-BS-MP8I-0-1
B-CS-G020-0-1
B-CS-G228-0-1
B-CS-M1 13-0-1

Memory Parity Option

Sense Amplifier

MP8/I logic to form the address code (octal code
10) of this option. Bits 9 through 1 1 allow genB-CS-M11 5-0-1
eration of lOP pulses. Bit 11, in conjunction
with an lOT instruction, generates lOPl (octal
B-CS-M1 62-0-1

I-MP2

Revision

Inhibit Driver

10-2 Input NAND

Gates
8-3 Input NAND
Gates

Parity Circuit

I-MP3

— 0— I8dW sa a 2

NOTE:

SIGNAL NAMES iNni^ATE A-,-,FkT=d
FOR HIGH LEVELS f'ER D" C s'O C^^

UI62

MEM

A08
LI

PARIT Y
EVES

MEM
PARITY

ODD

Qon
to

H
CO

TZ MEM
07 l_B09

EQUIPMENT
UNLESS OTHERWISE SPECIFIED

TOLERANCES
DECIMALS

FRACTIONS

i .005

= 1/6*

ANGLES
- CBO'

FINAL SURFACE QUALITY
REMOVE. BURRS AND BREAK SHiUP

CORNERS

CORPORATION

^^.^.^^^;7

DIMENSION IN INCHES

DATE
C.

L-tfcytrt

Ti'f^
OJ',^-,..v
FIRST USED ON

E- UA— 81-

MEMORY
PARITY
OPTION

CODE

BS V-SJT;

SHEET

I-MP5

UNLESS OTHERWISE INDICATED:

RESISTORS ARE I/4W, 9%
MF RESISTORS ARE l/eW,l%

CAPACITORS ARE .OIMFD.IOOV,
20*/<
DIODES ARE pe62
El, E3 ARE MCIE40e
EZ IS DEC7400N
PIN 7 ON EACH IC • 8ND
PIN 14 ON EZ= + 6V
PIN 2 0(J EI,E3=+5V

USE THE ETCH BOARD OF THE 0021

B-CS-G020-0-1

Sense Amplifier

UNLESS OTHERWISE INDICATED:
TRANSISTORS ARE DECI008
RESISTORS ARE I/4W, 5%
TRANSFORMERS ARE T2037
IC'S ARE DEC7440N
PIN 7 ON EACH IC ' SND
PIN 14 ON EACH IC = +5V

CAPACITORS ARE .OIMFD IOOV,ZO%
,

20MFD.50V. -10 + 75%

B-CS-G228-0-1

Inhibit Driver

I-MP7

+5V

NOT USED -I5V

8ND

CZ, Tl

iR4

>R2

;i;ci

+3V
'Rl

>R3

+3V

:cz

notes:
PIN 7 ON EACH IC = OND
PIN 14 ON EACH IC --fSV

10-2 Input NAND Gates

B-CS-M1 13-0-1

+5V
NOT USeO -I8V -

ONO-

-A2

B2
•C2, Tl

•+BV

ici icz
cz ~:
:::r^c3
aNO

2
13

-H2

-Nl

N2
P2

El
Fl

-S2

Rl
SI

-Jl

4
5

-Jl

notes;
pin 7 on each ic'sno
pin 14 on each ic-+sv

B-CS-M1 15-0-1

8-3 Input NAND Gates

I-MP8

K2
L2

T2
U2
VZ

M
10

ry^

4
3

GND

VZ^-Q

UNLESS OTHERWISE INDICATED:
CAPACITORS ARE ,01 MFD
PIN 7 ON EACH IC = ONO
PIN 14 ON EACH IC =4-5V
El, E2, E4,E5,E6,E7,E8, ElO a
EN ARE DEC7420N
E3 a E9 ARE DEC7430N

B-CS-Ml 62-0-1

I-MP9

Parity Circuit

VC8/I

OSCILLOSCOPE DISPLAY
OPTION
FUNCTIONAL DESCRIPTION

VC8/I

OSCILLOSCOPE DISPLAY

INTRODUCTION

PDP-8/1 and the display oscilloscope. Operational and maintenance data on the Tektronix

The VC8/I Oscilloscope Display consists of a
Tektronix Model RM503 Oscilloscope and its
associated control logic. PDP-8/1 control logic
accepts 12-bit control instructions and 10-bit
beam-positioning data wordso The control in-

RM503 Oscilloscope is provided in the oscilloscope maintenance manual, provided by the
manufacturer.

The maintenance procedures pertaining to the
PDP-8/1 also apply to theVC8/l control logic
Recommended maintenance procedures for the

structions are interpreted to permit communication with the processor and Intensity control of

RM503 Oscilloscope are described in the re-

displayed points. Thedata wordsare converted
to discrete analog voltages to provide 1024 display points on each of the X- and Y-axis of the

spective Tektronix manual

cathode ray tube.

The VCS/t logic is contained on the M701
double-width integrated-circuit module and
two A607 D/AConverterModules located in the
central processor main frame. Figure 1 shows
the functional relationship between the PDP-8/1,
the VCS/t control logic, and the display oscillo-

The VC8/1 control logic accepts 10-bit words,
describing horizontal and vertical plots, into
X-axis and Y-axis buffers. The buffer outputs,
converted from digital to analog levels, provide
dc-level deflection inputs to the RM503. Logic
circuits implement these operations by interpretinga 12-bit Instruction located in the PDP-8/1

memory buffer register.

scope.

A photomultiplier light pen is optlonallyavailablefor use with the VC8/I. This Type 370 light
pen permits control over, or communication with,
a running computer program.

The paragraphs which followdescribe the operation of the control logic as tt relates to both the

A60 7

The decoded instructions generate VCS/l control
signals in the following manner. Memory buffer
bits 0-2 contain the processor operation code 6q,
indicatingan input/output instruction. Bits 3-8
contain the 6-bIt address code identifying the
instruction as one which pertains to the VC8/1.

Three different address codes have been assigned
to performthenecessary control functions. These

X-AXIS CONTROL,

MB03 THROUGH MBit

Y-AXIS CONTROL
flC04 THROUGH fiCIl

VC8I

lOP PULSES

CONTROL

Z-AXIS CONTROL.

LOGIC

TEKTRONIX

RM503
OSCILLOSCOPE

LIGHT PEN OUTPUT
INITIALIZE

TYPE 370

Figure

LIGHT PEN

VC8/1 Oscilloscope Display
Block Diagram

I-VC1

addresses, and their functions are as follows:

05q

Table 1 (Cont)

(X-axis plotting and intensity control); O63 (Y-

Control Instructions

axis plotting and intensity control); and 0/3

(light-pen control).
Bits 9,

10, and 11 of the instruction generate

lOP pulses in the PDP-8/I. The lOP pulses

AND with levels produced by the decoding of

Mnemonic
DSB

Octal Code

607X

Operation
Generates an IOP4

the address bits to generate specific VC8/I con-

pulse to load the

trol signals.

content of bits 10

Table 1

struction into the

and 11 of the inlists

the VC8/1 control instructions and

brightness register

their respective operations

Bits 10 and 11 are
decoded by the BR

as follows:

Table 1
Control Instructions

6075 = minimum
brightness

6076 = minimum

Mnemonic

DCX (DCY)

Octal Code

Operation

brightness

6077 »= maximum
6051 (6061)

Generates an lOPl

brightness

pulse to clear the

X(Y) buffer.

DXL (DYL)

6053 (6063)

Generates an lOPl
pulse to clear the

X(Y) buffer, and
an IOP2 pulse to
11.

The following paragraphs describe the operation
of the VC8/I control logic. Logic circuitry for
the oscilloscope display option appears on DEC

Generates an IOP4

Engineering Drawing D-BS-VC8I-0-1 . Since
the X-and Y-channels operate identically only

load data from AC02-

DIX (DIY)

6054 (6064)

pulse to intensify the

oscilloscope display

electron-beam to the
degree indicated by
the BR. This command

combined with DXL
(DYL) becomes the

DXS(DYS) command.

DXS (DYS)

6057 (6067)

LOGIC DESCRIPTION

the horizontal (X) channel logic and operation
is discussed.

When the computer is turned on, or whenever the
Start key

pressed, the PDP-8/I INITIALIZE

level clears the light-pen flag flip-flop, and
sets the brightness register flip-flops

BRl to the

BRO and

state.

Generates lOP pulses
Clearing and Loading the Buffer
1,2, and 4 to perform
all

functions of the

three instructions
listed above.

I-VC2

The DCX (6051) instruction in the PDP-8/1 memory buffer register is performed to clear the Xbuffer register on the A607 module. When this

content of PDP-8/1 memory buffer bits 10 and 1
into BRO and BRI .

There ore four possible BR

combinations; 00, 01, 10, and
assignments are listed below:

11 .

andgenerates a negative voltage level, which
is applied to the VC8/1 control logic .
This
voltage level is not a standard DEC level, and
is therefore an emitter follower buffered to provide the signal and impedance characteristics

Their

required for DEC logic operation.

BRO BRl

Assignment

The buffered light pen output, combines with
1

LIGHT PEN STROBE to set the light-pen flag
LIGHT PEN STROBE is generated by

Partially enables low intensity

flip-flop.

AND gate

the active instensity amplifier.

Partially enables medium intensity

AND gate
1

Wh en the flag is set, its output partially enables
the IP BUS N SKIP gate and activates theTQ"

Partially enables high intensity

AND gate

BUS IN INT line, informing the PDP-8/1 that
some device is requesting service The PDP-8/1
then entersa programmed subroutine to determine
.

NOTE

which device caused the interrupt. This is performed by a series of "flag checking "skip in-

The 00 combination is not used because it disqualifies each intensity

A skip instructio n is executed for
each device attached to the lO BUS IN INT
structions.

AND gate.

When the 6071 instruction (skip
pen f lag is a l)is executed, the
lO BUS IN SKIP lineactivates, incrementing
the program counter by 1 and skipping the next
request line.

Three intensityamplifiers INT1 (low), INT2
(medium), and I NTS (high) control the RM503
Z-axis oscilloscope intensity. These amplifiers

areAND-gate control led by the combination of
the intensity pulse and the output of the BR.

if the light

sequential instruction.

After the instruction is
skipped, the PDP-8/1 enters a servicing routine
for this device.

The intensity pulse can be generated by either
the DIX (6054) or DIY (6064) instruction. Both
instructions are employed because each can be
modified to form either the DXS and DYS instructions, respectively .

The light pen flag Is cleared by either the INITI-

ALIZE level or by the combination of an IOT07,
IOP2 and memory buffer bit 9 in the state.

The DIX (DIY) address

code IOT05(IOT06)and IOP4combine to generatethe intensify pulse. Aftera 1 [jsdelayto
ensure thatthe BR has sett led, the intensity pulse
turns on the intensity amplifier specified by the
BR.

ENGINEERING DRAWINGS
The following drawings pertaining to the VC8/1
option are contained in this section.

Drawing Number

Title

D-BS-VC8I-0-1
D-CS-A607-0-1

Display Control

10-BItD-A

Converter
Power Supply
Display Control

Rev.

Light Pen Operation

The Type 370 Photomultiplier Light Pen communicates with, or controls a computer program

when used with the VC8/I

The light pen detects a point of lighten the cathode ray tube.
.

B-CS-A701-0-1

C-CS-M701-0-1
I-VC4

I-VC5

5 SCHEMATIC IS FURNISHED ONLV FOB TtST AHD M
CUITS ARE PROPRIETARY IN NATURE AND SMOUID BE TfiWiTED ACCORDl^GLY
COPYRIGHT IM7 BY DIGITAL FQUIPMENT CORPORATION

tfiO

—

-^AA^

—

V
'^"^WZ
S-*

/CCn
ten

^
Hh-

5-0.O

s«od
~

a* »

oik

-,>^i

L«<U

lil

tfi

S tt ui

rx???

f to tocc It

'd*te

TRANSISTOR i DIODE CONVERSION CHART

10 BIT

D -A

CONVERTER A607
JEOU IPMENT

'Ml

CORPORATION

PniNTED CIRCUIT REV

I-VC7

W N

D5
+ I5V

DO-

(RE6)

D8
!

DIO

N W T

-O A +IOV
(DEC)

-OV +3V

:7:c3

:c2

-OC GND

COM FO-

-OB -I5V

- 5V E O(RE6)
1

(DEC)

B-CS-A70 1-0-1

Power Supply

I-VC9

<
n
UNLESS OTHERWISE INDICATED;
TRANSISTORS ARE DEC6534B
RESISTORS ARE I/4W, 5%
DIODES ARE 0664

CAPACITORS ARE .01 MFD
IC = GND
IC =f 5V

PIN 7 ON EACH
PIN 14 ON EACH

E6,E8,EII,ARE 0EC74(0N
EI,E3,E9,EI2,EI4 ARE 0EC7400N
E 2,EI0 ARE DEC7474N

E5,E7.Ei3ARE DEC7420N
E4

DEC7460N

C-CS-M701-0-1

Display Control

instruction is executed, the address code 05g

OVand -2V by the A607D/A Converter and

3 through 8) decodes to produce IOT05,
andlOPl isgenerated from MBll in the pro-

Buffer Register Module . The analog voltage can

(bits

cessor. These signals

be vari ed in 1 024 (2 ^) di screte nterva Is betweenits upper and lower limits in direct propori

NAND together in the

control logic generating the CLEAR X pulse.

tion to the numeri ca va lue of the coordinate data.

The DCX instruction, norma ly used only at the
start of the program, is usually combined with
the load instruction (DXL) to increase the speed

A OV input signal from all X-buffer flip-flops to

the D/A converter produces a OV ana log output;
conversely, a +3Vinput from all these flip-flops

of operation. This combined instruction (6053)
produces both lOPl an d IOP2 pu lses in the same

computer cycle. The CLEAR X pulse (IOT05
lOPl) clears the X-buffer register. The load
pulse (IOT05 lOP2)is generated 1 jos later. The
load pulse appears on the X-buffer flip-flop C
inputs and transfers a data word from PDP-8/l
accumulator bits AC02 through ACll into the
X-buffer register.

generates a -2V output. The X and Y analog
voltages are produced identically. The location
of the osci loscope beam on the cathode ray tube
I

determined by the vector sum of the twovoltagesappliedtothe RM503inputs. Table 6-4
is

shows the relationship between the buffer register data and the analog voltage output.
Intensity Circuits

The brightness of the point displayed is determined by the 2-bit brightness register (BR). A
PDP-8/l DSB (607X) instruction generates a load
This pulse transfers the
pulse (IOP4 IOT07)

Digital To Analog Conversion

The 10-bit data word contained in the X-buffer
register generates an analog voltage between

Table 2
Buffer Data - D/A Converter Correlation

Digital Address

Buffer Output

and

and
D/A Converter Input

Flip -Flop States

n n n
nn

xxxxxxxxxx
xxxxxxxxxy

100000000
000000000
111111111
111111110

xyyyyyyyyx
xyyyyyyyyy
yxxxxxxxxx
yxxxxxxxxy

00 0000000

yyyyyyyyyX

0000 000000

yyyyyyyyyy

- Zero State
= One State
1

X=OV
y -+3V

1-VC3

D/A Converter Output
most positive (OV)

most negative (-2V)

VP8/I

INCREMENTAL PLOTTER
OPTION
FUNCTIONAL DESCRIPTION

VP8/I

INCREMENTAL
PLOTTER
vided in the CalComp Digital Incremental Plotter
Maintenance Manual supplied with the system.

INTRODUCTION
The VP8/I Incremental Plotter consists of a California Computer Products Inc. digital incremental
plotter and

its

associated control logic.

The

control logic accepts 12-bit instructions from the

PDP-8/l and converts them to specific operational commands which are retransmitted to the plotter, producing the desired pen and drum movements. Discrete points may be plotted, and
vertical, horizontal, or diagonal lines produced
in any combination by the application of the
proper programmed commands.
The control logic of the VP8/I is contained on
one M704 double-width integrated-clrcult module
located in the central processor main frame. The
control logic is compatible with CalComp Digital
Incremental Plotter Models 563, 564, 565, or
566. Figure 1 shows the functional relationship between the PDP-B/l, the VPS/l control
logic, and the incremental plotter.

The maintenance procedures pertaining to the
PDP-8/I also apply to the VP8/I control logic.
The recommended maintenance procedures for
the CalComp Plotters are described in the respective California Computer Products Inc.

manuals.

LOGIC DESCRIPTION
The VP8/I control logic Interprets a PDP-8/l
instruction in the memory buffer register to gen-

erate control pulses that set one or more motion-

These flip-flops Initiate
plotter motion by moving the pen up, down,
control flip-flops.

left

or right, and/or moving the drum up or down.

The PDP-8/l instructions decode to initiate plotter functions In the following manner. Memory
buffer bits 0-2 contain the operation code 6q,
indicating an input/output instruction. PDP-8/l
memory buffer bits 3 through 8 contain a 6-bit
address code that identifies the instruction as
Three address codes
one pertaining to the VP8/I
control
These
plotter
the
assigned
to
have been
.

codes and their functions are as follows: 50g
(plotter flag and pen up); 51g (pen right and drum
motions); and 52g (pen left and down, drum up).

;-;
MB03 THROUGH MBOS
I

CALCOMP

VPBI

LOGIC

» CONTROL

lOP PULSES 1,2,4

DIGITAL

DRUM DOWN

INCREMENTAL
PLOTTER

Bits 9,
I

Figure

10, and 11 of the instruction generate

lOP pulses in the PDP-8/l. The lOP pulses

combine with levels In the VP8/I control logic
produced by decoding the address bits to gener-

VPS/l Block Diagram

ate specific control signals that initiate plotter

motions.

The paragraphs which follow describe the operation of the control logic portion of the plotter as

Logic Operation

relates to both the PDP-8/l and the mechanism.
The following paragraphs describe the operation
Maintenance procedures, and a description of
of the VP8/1 control logic. Logic circuitry for
the plotter mechanism and its operation are proit

I-VPl

this option appears

on DEC Engineering Drawing

second 35-ms delay is triggered

SLOW OP

D-BS-VP8I-0-1.

DONE clears both the PEN UP and PEN DOWN

Whenever the computer is turned on, or the
Start key is pressed, the PDP-8/l INITIALIZE

mot on -control flip-flops. After the second delay time (70 ms total) the plotter flag sets. This
long delay time allows the drum to settle in
I

level

generated.

This signal

cl ears

the P LTR

position.

This prevents erroneous or vague plots.

FLAG (plotter flag) and generates FAST OP
DONE (fast operate done) to clear the PEN
RIGHT, PEN LEFT, DRUM UP, and DRUM

The plotter flag is set by the execution of any

DOWN motion control flip-flops.

plot ter-motion instr uction.

The plotter lOT (PLTR lOT) and the 50 INST
level are the decoded address levels used in the
VP8/I control logic. PLTR lOT is generated
whenever the PDP-8/l l/O instruction contains
5O3, 51g, or 52g (from memory buffer register

When active, this level is
at +3V. It is the main lOT level and is used to
bits

3 through 8).

generate every plotter motion.

10 BUS IN S KIP gate is partially enabled. lO
BUS IN INT indicates to the PDP-8/I that a device is requesting service if the program interrupt
facility Is enabled. Under program control, the

PDP-8/I then enters a search subroutine to
determine which device caused the Interrupt.
This search is performed by a series of "flag

The 50 INST level is generated and active (+3V)
only when PDP-8/I memory buffer bits 7 and 8
are cleared. The inverse of this level, 50 INST,
is also used.
501 NST is generated whenever

MB07 or MB08 is set;

When this occurs,

the 10 BUS IN INT line activates (OV), and_th_e

.e . , a 51q or 52g address

code
These lOT levels (PLTR lOT, 50 INST,
and 501 NST) combine with the lOP pulses to
.

generate specific control pulses.

The plotter operations are classified as being
either fast (pen right, pen left, drum up, drum
down) or slow (pen up, pen down) motions.

checking" skip Instructions. A skip instruction
is executed for each device attached to the
interrupt line. The plotter flag status is checked
by the 6501 instruction. When the plotter flag
Is set and thi s instruction Is performed, the lO
BUS IN SKIP gate Is enabled, activating the
skip line (OV). This line causes the PDP-8/I
program counter to increment by one, skipping
the next sequential instruction In the program.
When 6501 results In a skipped Instruction, the
program enters a VP8/I service routine. Usually,
instruction 6502 is the first command performed
In this routine.

This instruction clears the plot-

The next VP8/I motion instruction Is
then performed.
ter flag.

When a fast-motion instruction is executed, the
following events occur In sequence.

The motion

control flip-flop sets initiating the plotter motion,

and the firs t 2.5-ms delay is triggered. After
FAST OP DONE is generated to clear
all fast motion -control flip-flops, and the second
2.5-ms delay is triggered. After this second
delay time (5.0 ms total), the plotter flag sets.
the delay,

When a slow -motion instruction is performed,
the events occur in a manner simlliar to the fast-

The slow-motion flip-flop
UP, or PEN DOWN) sets, and the

motion operation
(either PEN
first

VP8/I INSTRUCTION DESCRIPTIONS

35-ms delay is trigge red. After this delay

period,

SLOW OP DONE is generated and the

Table 1 describes each plotter instruction.

I-VP2

Table 1

VP8/I Instructions

Mnemonic

Octal Code

Operation

PLSF

6501

Skip On Plotter Flag. This instruction decodes to
generate PLTR lOT, 501 NST, and lOPl to check the
flag status. If the flag is set, lO BUS IN SKIP is
generated

PLCF

6502

Clear The Plotter Flag. This instruction decodes to
generate PLTR lOT, 50INST, and IOP2 to clear the
flag.

PLPU

6504

This instruction decodes to generate PLTR
lOT, 50INST, and IOP4 to raise the plotter pen
from the surface of the paper. PLPU is a slow

Pen Up.

operation

Pen Down.

PLPD

6524

After the drum and/or pen are moved, a
PLPD instruction decodes to generate PLTR lOT,
IOP4 and MB07(1). This lowers the pen to the
surface of the paper. PLPD is a slow operation.

PLPR

6511

Pen Right. This instruction decodes to generate
PLTR lOT, lOPl and MB08(1) to move the plotter
pen one increment to the right. It is a fast operation. This instruction can be combined with
the drum up (6512) or drum down (6514) instruction
to produce a diagonal plot.

PLPL

6521

Pen Left. This instruction decodes to generate
PLTR lOT, lOPl and MB07(1). It is a fast operation. PLPL moves the plotter pen one increment
to the left. This instruction can be combined with
the drum up (6522) instruction to produce a diagonal
plot.

PLDU(PLUC)

6512(6522)

Drum Up. These instructions decode to generate
PLTR lOT, 501 NST, and IOP2. Both instructions
move the drum up one increment. Each is a fast
Both instructions ore needed so the
drum up motion can combine with pen right (pen

operation.
left)

PLDD

6514

motion instructions.

Drum Down. This instruction decodes to generate
PLTR lOT, 10P4, and MB08(1). PLDD is a fast
operation that moves the drum down one increment.
It can combine with the PLPR instruction.

I-VP3

ENGINEERING DRAWINGS
The following drawings pertaining to the VP8/I
are included in this section.

Drawing Number

Title

Revision

D-BS-VP8I-0-1

Plotter Control

D-CS-M704-0-1

Plotter Control

I-VP4

)

NOTE:

SIGNAL NAMES INDICATE
ASSERTED STATES FOR HIGH (H)
LEVELS PER DEC STD 054
ITIALIZE

MB08 (0)

-SLOW ,0P DONE

00
Q-

MB0 5 (I)
MB06 (0)

MB03
MB04 (0)

PLTR FLAG (O)

PLTR lOT

I0P4 (
MB07 (0)

lOP

(0)

Jul

I0P2 (0)

SS
<12.5

MS
50

MB07 Cl)

INST

^O
x>-c>^

FAST OP DONE

M704
HJ29

MB08 CO

DATE

UNLESS OTHERWISE SPECIFIED
UNLESS OTHERWISE SPECIFIED
DIMENSION

INCHES

J^i.^Se^.
CHK'D.

.^„.

TOLERANCES
DECIMALS

FRACTIONS

ANGLES

.006

i 1/6A

± a°30'

FINAL SUHFACE quality

REMOVE URRS AND BREAK SH^

'MIJL

DATE

l/zi-..^-, ^

COftNEBS

DATE

s:
HATERIAL

M£L

DATE

EQUIPMENT

BBSnOSD CORPORATION

PLOTTER
CONTROL

FIRST USED (SH

DBS V P8I -0-1
NUMBER

SHEET

TTT

0£C FORW NO

I-VP5

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PUfiPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.

AA2,BA2 -t-SV

-A82,BBZ -I5V

.AC2,BC2 g„o
ATI, BTl

DEC
3009B
BE2
SKIP

AK2
MBS(I1

lopidl

UNLESS OTHERWISE INDICATED:
TRANSISTORS ARE 0EC6S34B
RESISTORS ARE l/4W,5%
DIODES ARE 0664
PIN 7 ON EACH IC'GND
PIN 14 ON EACH IC = +SV
El IS A DEC7430N
E2.E5,Ea,EI4 ARE DEC7474N
E3, E6, E9, El I, EI2, Eie, EI7 ARE DEC7400N
E4, E7, ElO, EI3, EI9 ARE DEC7460N
EIS, EI8 ARE DEC74I0N

CAPACITORS ARE .01 MFD

PARTS LIST IS A-PL-M704-0-0

TRANSISTOR & DIODE CONVERSION CHART

digital
EQLUPMENT

CORPORATION

PLOTTER CONTROL M704
SirE
I

CODE

NUMBER

CS 111704-0PWtHTED CIRCUIT REV.

|b|

[

I-VP7

KW8/I
REAL-TIME CLOCK

OPTION
FUNCTIONAL DESCRIPTION

KW8/I
REAL-TIME

CLOCK
tions are performed (refer to KW8/1 Instruction

INTRODUCTION

The initial pulse output from
by the clock control,
"masked"
this clock
therefore, the first pulse allowed is approximately
Descriptions).

This option provides a method of accurately
measuring time intervals. There are six KW8/I

that of the clock period.

The basic KW8/I consists of a
The
frequency source, and a clock control
configurations.

The Line Frequency Clock (KW8/IA) produces
voltage
its output by stepping -down the line
The
Vac.
to
6.3
through a clock transformer
frequency Is either 50 Hz or 60 Hz depending on
the line source, and is an important consideration in time-interval measurements. The step-

basic real-time clock configurations are:
KW8/IA (M501 Line Frequency source); KW8/IB

(M401 Variable Clock); and KW8/IC (M405
Crystal Clock).

An M709 Clock Control Module (M709) can be

ped -down voltage is applied to a Schmitt trigger
which generates a square wave used as the clock

added to each of the basic clocks to provide six
KW8/I configurations. The M709 Clock Counter

contains preset and readout registers with associa- source
ted controls. Addition of this module allows hard
-

ware -interval counting, reducing program
instruction time; therefore, more efficient use is
made of computer time. The real-time clock
options are then designated as KW8/1D, KW8/IE,
and KW8/IF, respectively. The logic for the
KW8/! option is contained within the PDP-8/I
processor main frame. The KW8/I maintenance
procedures are the same as those of the PDP-8/I.

The M405 Crystal Clock (KW8/IC), and the Line
Frequency Clock (KW8/IA) outputs are asynchronous to program execution. This allows the variation of the first clock pulse occurrence to be as
long as one full period. The variable clock has
less inaccuracy in its first period because of the
masking, therefore, the overall accuracy of the
variable clock may exceed that of the crystal,
or line frequency clocks.

LOGIC DESCRIPTION

The basic accuracy and stability of the KW8/I is
of the frequency source. The overall accurThe following paragraphs describe the frequency- that
acy of the real-time clock, however, involves
source configurations, the clock control logic,
the clock frequency and its relationship to the
and the clock counter.
Instruction time of the service loop. The number
of clock pulses counted In a time interval is also
a consideration because of the inaccuracy of the

Frequency Sources

The clock period should be
clock period
greater than the time required to service the

The frequency sources provide pulses at a specific first
frequency, to the clock control.

Refer to En-

loop including the skip and lOT instructions,
to prevent occurrence of more than one pulse

gineering Drawing BS-KW8I-0-1.

The M401 Variable Clock Source (KW8/IB) produces pulses only when enabled by CLOCK ENABLE. This enable level is generated by the
M708 Clock Control when specific lOT instruc-

count during the service routine. A maximum
frequency of 100 kHz is required for KWS/lA,
B, and C configurations because of finite instruction time.

I-RTCl

Clock Control

number is loaded into the count register by the
CECL instruction which generates LOAD
COUNTER in the M708 Clock Control . The
rising edge of each clock pulse transfers the con-

The M708 Clock Control decodes various lOT
instructions to allowa skipand/orinterruptafter

a clock pulse has set the flag. Certain lOT commands may also enable or disable the M401 Variable Clock bygeneratingriI!5T!irFR7^5IE. The

tents of the count register to the outputbuffer.

The contents of this buffer can be read into the
accumulator by the CRCA instruction without

interrupt flag (IF) may also be disabled prevent-

disturbing the contents of the count register.
The count readis the last counter value if this

ing real-time clock operation.

instruction occurs during the clock pulse.

When a c lock pulse sets the flag I/O BUS N NT
,

isgenerated, indicating to the PDP-8/I that an

The trai ling edge of the clock pulse increments

I/O device is requesting service. A subroutine

the count register.

checked.

containsa one, the service

generated. This level enables the flag within

A PDP-8/I memory location

the M708 Clock Control, and permits the nest

If the flag

loop is performed.
is

When the desired number of
counts minus one have occurred, OVERFLOW is

then entered, and the status of the flag is

incremented to store the number of counts.

clock p ulse to set the flag, producing I/O BUS

IN INT.
Clock Counter

Since the addition of the M709Clock Counter

TheKW8/lA, B,andC configurations may be
modified to become the KW8/ID, E, and F options by theaddition of theM709 Clock Counter
Module. This logic containsa counter register,
an output buffer register, input/output gating,
and control logic for loading reading, counting
and synchronizing.

allows logic hardware to perform the counting
function, when counts greater than 10 are per-

formed, themaximum counting frequency can
be extended to a limit imposed by the propogation delay of the counter. This limit is 1 MHz.

KW8/I INSTRUCTION DESCRIPTIONS

A number in the accumulator containing the
desired number of counts is complemented, and
incremented by the c lock counter logic . The

Table 1

lists

the KW8/I instructionsand contains

descriptions of their operations.

Table 1

KW8/I Instruction Description
Mnemonic

CCFF

Octal Code

6132

KWa/l's Affected

KW8/IA
KW8/IB
KW8/IC

CCEC

6136

KW8/IA
KW8/IB
KW8/IC

Description

The flag, flog buffer, clock enable, and interrupt
enable flip-flops are cleared. This disables the
real time clock
All clock control flip-flops are first cleared, then

the clock enable flip-flop is set.

For the variable
frequency clock, the frequency source is enabled
synchronously with program operation. With all
clocks the data input to the flag is enabled after
IOP2 time. This represents an 800-ns mask, after
the clock is enabled.

I-RTC2

Table 1 (Cont)
KW8/t Instruction Description

Mnemonic
CECI

Octal Code

6137

Description

KW8/l's Affected

KW8/IA
KW8/IB
KW8/IC

All clock control flip-flops are cleared, then the
clock enable, and interrupt enable flip-flops are
set.

The clock enable flip-flop is described with

the CCEC instruction. The interrupt enable flipflop allows an lO BUS IN INT signal when the
flag

CSCF

6133

set.

KW8/IA

When the flag flip-flop has been set by a clock

KW8/IB
KW8/IC
KW8/ID
KW8/IE
KW8/IF

pulse, the flag buffer flip-flop is set to a one.

Upon execution of this instruction an lO BUS IN
SKIP is generated if the flag is set.

The content

of the PC is incremented by one so the next sequenThe flag flip-flop is then
tial instruction is skipped.

cleared.

the flog flip-flop has not been set, no

skip is generated nor is the flag flip-flop cleared.

CCFF

CECL

6132

6136

KW8/ID

The operations described above for this instruction

KW8/IE
KW8/IF

are performed.

KW8/ID
KW8/IE

The operations are the same as that of the CCEC
instruction, except that the data input to the flag is
not enabled until both CLOCK ENABLE and OVER-

KW8/IF

In addition, the

OVERFLOW gating

disabled

FLOW are set.

All

M709 counter bits are set at

IOP2, and then cleared according to the accumulator prior to IOP4. At IOP4 the contents of the
counter (the one's complement of the accumulator)
are transferred to the output buffer. At the end
of IOP4, the counter is incremented by one to
provide the two's complement of the accumulator.

CEIL

6137

KW8/ID
KW8/IE
KW8/IF

CRCA

6134, or

KW8/ID

6135

KW8/IE
KW8/1F

Operations are the same as those described in the
CECI instruction, except that the M709 is loaded

according to the CECL instruction.

The output buffer is gated to the l/O BUS during
IOP4, and a CLK AC CLR signal generated. This
register contains the last count in the count register.

The transfer from the count register is synchronized
with this instruction so that a transfer that would
occur during this instruction is not made.

I-RTC3

PROGRAMMING EXAMPLES

Single count with KW8/I

The following examples further clarify the KW8/I

6136
6133

instruction set.

Counting in program for KW8/IA, KW8/IB, and

KW8/IC clocks.

CLR control flip-flops. Enable Clock.
Skip if flag is set.

— JMP

-1

By using the Variable Clock (KW8/IB), one
clock cycle can be counted accurately. This
improvement of first cycle accuracy can be used

6136
6133

CLR control flip-flops, enable clock. for multiple counts either in a Fixed Interval
Clock (KW8/IB), or with Preset and Readout
Skip and clear flag.

JMP -1

ISZ B

— JMP

Counter (KW8/IE).

-3

Measurement of an Interval.

Location B - Two's complement of desired

7200

count.

— CLA
TAD

6136

CLR control flip-flops, enable
clock and load counter

Counting with Preset and Read-out Clock
(KW8/ID, KW8/IE, and KW8/IF)

Begin interval
•
9
•

7200
1

—

6137

End of Interval

CLA
TAD B

6134

CLR control flip-flops, enable clock,

6135

Read clock

and interrupt.
Location B - (OOOOg), two's complement of
Location B - Desired count of clock pulses.

The preset count register with the interrupt
facilffy enabled allows a more efficient use of
machine time. While counting out an interval
of time, the machine can process other programs
instead of looping.

zero.

The initialization of the preset and read-out clock
with zero at the beginning of the interval allows
a direct read-out of the number of clock pulses
occurring during the interval
If the interval is
.

greater than {7777 q) pulses, a service of OVER-

FLOW would have to be effected.

I-RTC4

ENGINEERING DRAWINGS
The following drawings pertaining tothe KW8/1
are included in this section.

Drawing Number

Title

Rev.

D-BS-KW8I-0-1

Real Time Clock

D-BS-KW8I-0-2

Option
Clock Control

M708
D-BS-KW8I-0-3

Clock Counter

M709
B-CS-M401-0-1
B-CS-M405-0-1

Clock
Not Available

J
-

B-CS-M50 1-0-1

Schmitt Trigger

I-RTC5

-l8M>ISaa
I

A3ti

This drawing and speeificatiorN. herein, art the ptot
erty of Digital EquipriMnt CorporMior ard Shall not b
raomfluced or copied or used in whole Ot id part a

FREQUENCY 'SOURCE.
W4.01

OR M4-05 OR M-S^l

MA-OI VARIABLE. CLOCK

CLOCK ENABLE.

CLOCK COMTROL

1.4401

, „
CAP
COMM

INT

CAP

D?.

MB4- CO) -

MBS (0

TS.

MB<bC(Z)-

PZ.

MB7
MBS CO -MBS C®) )

M'V^S CRYSTAL CLOCK

MB=)CI)

MBiacn-MBll CU

CRYITAL CLOCK

lOPi caiT)-

CLOCK

AUTO TAP

M5<jf)l

3^
p^

N2.

10P2.C®)-

INFflXLlZE-

CE.

SCHMHT

NOTE

CLOCK LOAD
LOT
COUl^ER

MOUTPUT

CLOCK

JNI

CLOCK COUNTER
JJ'J.

OVERFLOW

MBiaCO)

•

MBIOCO

JPI

M-IO=1

JSl

HF2
JDI
HFI
JBI

HJl
HLII
l-UI

HV2
ACt3<Z><:0 -

HEl

HMl

ACOICl) -

JAl
HVI

HPi

HHI

HSl

Aca-j-co -

AC^'S CI ) ACt24.C0-

ACW5C0

THE FOLLOWlStS CONFlGURATIOtsia OF THE REAL TIME CLOCK OPTION! ABE PO-SSIBLE.
KWalA

SIGNAL NAMES INDICATE
ASSERTED STATES FOR HIGH (H)
LEVELS PER DEC STD 054

TRIGGER

^OORCoOru

OPTIOM TYPE

SOURCE)

-> FLAG T.R
-^ INTERRUPT ENKBLE T.P.
-> FLAG. BUFFER T.P.

HZ.
Li

SCHMITT TRIGGER TO LINE FREQUBJCY

ii'j.v:

AT FAM

H^<3

IOP4-t»')-

"rRAK'5 f OBJOER
(DEC I(i-oq50/ )

I/O BUS IM 'SKIP
-* I/O BUS IM INT
-^ CLOCK. ENABLE CTO FREQUENCY
->

CLOCK

OUTPUT

DZ.

fa.

N2.

(+)

^
I

DESCBIPTTON
LINE FREQUENCY INTERRUPT

MODULES

LOCAT10b4

Mloa,

HBO
JBO

U50I

AOZkoCD-

ACOT CO -

Acascii-

HRI

AC'B'^CI)-

ACI® CO-

HU%
HKI
HTZ.

ACH 01-

HMZ.

-» I/<a BUS IN 00
-^ i/<a BU'3 iNab
-> i/a BUS iN'a2-^ I/O) &US INg>B
-» I/gi BO'S INgi'q-» :i/(g BUS iKica 5
-^ I/O BUS IMOife
-^ I/g) BUS INiqt7
-» I/IB But) INgia
-^ 1/(B BUS INg>M
-^ I/<a BUS TKIlia
-> l/tZ) BUS INI

HWL

JRl

HR'2.

<JMI

-> CLOCK TO COUNTER T.R
-> SET COUNTER T- P.
-> TRAN-SFER T. P.
-> READ 0-5 T.P.
-» READ &-\l T.P.

HP\

jHi
JMe

-3>

JFl
JHl
HE2.

-> GATE cn T.P.

CLOCK AC CLR
I

CLOCK TRAMSFORMER FAN BRACKET*

KWalB
Kwaic

KWBID

VARIABLE CLOCK IMTERRUPT

CRYSTAL CLOCK INTERRUPT

KWSIA WITH PRE-oET AMD READOUT

MTOS

HSO

M4.01

J30

MTOS

H=iO

M4-OS

030
H^O

M-IOS

M-70=l

HJ^I

M501

j=>o

SCO

CUOCKTRANSFORMER FAM BRACKET^K

KWaiE

KWSIB WriH PRESET AMD READOUT

MTOS.
MTO=l
M4-01

KwaiF

KWalC WITH PRE=>eT AND READOUT

H?>C:

HU5.1
J'SO

MTOa

H3Q

MTO=1

HJB\

M4-05

J^O

* MXG ^V^JIRING IWFORWA.T10M OM PRINT * D-UA-KYVSI-5i-<Jb
EQUIPMENT

UNLESS OTHERWISE SPECIFIED
UNLESS OTHERWISE SPECIFIED
DIMENSION IN INDHES

SDIDDSD CORPORATION
I

TOLERANCES

DECIMALS

FRACTIONS

ANQLES

£006

£ 1^6A

± O'SO'

FINAL SURFACE QUALITY

REALTIME CLOCK
OPTION KW8I

-7^
SIZE CODE

a: ^

"It

NUMBER

DBSKW8I-0-I
-^'-y-

rr-i

I-RTC7

Z-5l-I8M>< sa
THIS drawing aiW specifications, hereati. are 1
erty of Digital Equipmant CoriMfation and shs
reprodjced or copied or used ir >fitm\« or ir

Mtil for the manulacture or sale ol item!

,
'

£ „ MBS co^

agMBAco:,

—/

,_^S

P n MBfaCO)
Pec

,;x MB-? CO

,1OP4C0)

CUOCK lOT
31

I/O BU'b IN^KLP

—O HI

FLA.a BUFFER "T-P.

-OJFLNi BUFFER

FL/kG. T.R

CLOCK, pa,

C>^"
o

I/O BUS uT

lO PICiyi)

uqMBkSco

[]^T~^

INT

NOT&
SIGNAL NAMES INDICATE ASoERTEO STATfS
FOR HIGH CH} LEVELS PER DEC STD 054

INTERRUPT eM^&UE-T.R

O-

t—

EQUIPMENT

UNLESS OTHERWISE SPECIFIED

UNLESS OTHERWISE SPECIFIED
DIMENSION IN INCHES

yj--y^S'

TOLERANCES
DECIMALS

FRACTIONS

ANGLES

± ,005

- 1^64

= °30'

FINAL SURFACE QUALITY

REMOVE BURRS AND BREAK SHARP
CORNERS

VVt^

°"Aj(^
DAT€

SDIDGID CORPORATION
I

DATE

iLiE
ItL^.jsf

MATERIAL

^'%f<ici<L^

DATE

CLOCK CONTROL,

M708

^/Lf

FIRST USED ON

D-'J^-K\AjaT-CB- «)

NUMBER

REV.

D BS KW8I-0- 2

SIZE CODE

I-RTC9

I-RTC1

U-^^p7

ii^Tr\U:i ~Tr\i-ii^"Tr\^—

—H
>R4

T. P.

|r6

C
R3

VW-

II_,

notes;
pin 7 on each ic
pin 14 on each ic

snd

+5v

B-CS-M501-0-1

Schmin Trigger

1.0

MFC

UNLESS OTHERWISE INDICATED:
DIODES ARE D66Z
CAPACITORS ARE .01 MFD,I00V,20%
RESISTORS ARE I/4W, 8%
El IS DE07400N, E2 IS DEC74H00N
PIN 7 ON IC « SND

35V
10%

PIN 14 ON IC> -l-SV

TRANSISTORS ARE DeC42BB
R8 IS A HELITRIM POT I0%-78PR

B-CS-M401-0-1
1-RTC13

Clock

PART

ENGINEERING

DRAWINGS

ENGINEERING DRAWINGS

This Section contains reduced copies of DEC

FLIP CHIP Modules Catalog and the System
Modules Catalog but are often simplified.

block schematics, circuitschematics, and other
engineering drawings necessary for understanding and maintaining this equipment. Only
those drawings which are essential and are not
available in the referenced pertinent documents are included. Should any discrepancy
exist between the drawings in thischapter and
those supplied with the equipment, assume that
the latter drawings are correct.

LOCATION DESIGNATIONS

the type of drawing (BS); a

The following scheme is used to specify signal
locations. The first capita lletter designates one
of the horizontal rows of modules within the
mounting frame. The module receptacles within
these rows are numbered from left to right as
viewed from the wiring side. The module receptacle number follows the first capita letter.
The second capital letter denotesthe pin location. Finally, the last number specifies the
group. Since M-series modules are doublesided, they consist of two groups of 18 connectors, each containing all ofthe letters except
G, I, O and Q; this number specifies the
group. For example, the signal BMB08(0)

fying the size of the original drawing (D); the

terminates at location J04M2 . This location is

type number of the equipment (9999); the manufacturing series of the equipment (1); and the

found in row J, the fourth cable connector slot,
pin
on side 2.

DRAWING NUMBERS

DEC engineering drawing numbers contain five
groups of information, separatedbyhyphens.

drawing number such as BS-D-9999-1-5 consists of the following

left to right:

information reading from

a 2- or 3- letter code specifying
1 -letter code speci-

drawing number within a particular series (5).
The drawing type codes are:

ENGINEERING DRAWINGS
block schematic PW
or logic diagram RS
CD cable diagram
UML
CL cable list
circuit
schematic
CS
FD flow diagram
BS

power wiring
replacement
schematic

Drawing Number

utilization

D-FD-8I-0-1
D-BS-8I-0-2

module list

wiring diagram

wiring

D-BS-8I-0-3

list

CIRCUIT SYMBOLS

D-BS-8I-0-4

Block schematic engineering drawings of DEC
equipment indicate signal flow, logical func-

D-BS-8I-0-5

tions, circuit type and physical location, wiring,
and other pertinent information. Individual circuitsare shown inblockor semiblock form, us-

D-BS-8I-0-6

Title

Rev.

Flow Diagram
Timing Manual
Functions and Run
Instruction Reg and
Major States
Reg Output Gate

Z
J
J

Control
Shift and Carry

Gate Control
Reg Input Control

and Skip
D-BS-8I-0-7

Interrupt and Break

Control

ing symbolsthat define circuit operation. These

symbolsare similar to those appearing in both the

II-1

D-BS-8I-0-8

Major Registers

Drawing Number

Title

lev.

D-BS-8I-0-9

Mo {or Registers

D-BS-8I-0-10

Gating
I/O Level Converter

D-BS-8I-0-n

Teletype Receivers

D-BS-8I-0-12
D-BS-8I-0-13
D-BS-8I-0-14

Teletype Transmitter C
Memory Control
F
D
Sense Amp Is and

D-BS-8I-0-15
D-BS-8I-0-16

Inhibit Drivers

X Axis Selection

C
C

Y Axis Selection

B-CS-M 160-0-1
B-CS-M 162-0-1
B-CS-M2 16-0-1

Six F lip-Flops

Major Registers
Delay Line
Variable Delay
Clock
Variable Clock

Negative Input
Converter

B-CS-M6 17-0-1

6-4 Input NOR

B-CS-M 113-0-1

B-CS-M 115-0-1
B-CS-M 117-0-1

10 Bit D-A Converter C

C-CS-M70 1-0-1

Display Control

B-CS-M703-0-1
D-CS-M704-0-1
C-CS-M705-0-1
C-CS-M706-0-1
C-CS-M707-0-1
C-CS-M710-0-1
C-CS-M715-0-1
B-CS-M720-0-1

Power Fail

Plotter Control

Reader Control

Memory Selector

C-CS-M700-0-1

Inhibit Driver

Resistor Board

D
F

Solenoid Driver
10-2 Input NAND

Gates
8-3 Input NAND
Gates
6-4 Input NAND
Gates

A
A

Sense Amplifier

Negative Regulator

Negative Output
Converter
Manual Timing
Generator

B-CS-M650-0-1

Regulator Control

Schmitt Trigger

D
B

Buffers

H
H

Sense Amplifier

D-CS-M220-O-1
B-CS-M310-0-1
B-CS-M360-0-1
B-CS-M40 1-0-1
B-CS-M452-0-1
B-CS-M501-0-1
B-CS-M506-0-1

Circuit Schematics

D-CS-A607-0-1
B-CS-G020-0-1
B-CS-G02 1-0-1
B-CS-G22 1-0-1
B-CS-G228-0-1
B-CS-G624-0-1
B-CS-G805-0-1
C-CS-G826-0-1
B-CS-M040-0-1

Gate Module
Parity Circuit

C
E

II-2

Teletype Receiver

Teletype Transmitter

Punch Control
Reader Clock

Memory Detection

—

FETCH

specifications, herein, ars the prop'

ment Cerporation ant) sliali not be
si or USMI in whola or in part as
inutactun or Mis of ittim vritiiout

DEFER

EXECUTE

)

-0-18 aj a 2
3003 32IS

aaQHON

CUR ADD

BREAK

MA+I—PCj
I

strobe;

AUTO INDEX

"AUTO INDEX

AND TAD

ISZ

Mem-»mb

MEM-V'MB

MEM+I-»HB

1
MBO4C0>MB06C0;
AC —AC

MB03(l)

IZ3_

MB07(I)» L=

AC—* AC

I
MB04(I). MB06C0)

MBIKO

0—AC

lOP

MB05CO) • MB07C0)

MBIOfl> MBIKO)

MEM-^MB

DATA-»MB

MEM + I-»MB

CARRY

WCOVFLO

AUTO INDEX

MEM + I-^PC

MEM-»PC

—
1

PC 0-4

MA 0-4
PC 0-4

MBIOCl)

lOP

TAD

AND

MB04(0)|mB04CI)

AC«MB

—AC

AC+MEM

—AC

MA+

0-^AC

—PC

MB05( l)_» MB07(I)
L

M B04(0;»MB09(i; IMBO
AC + SR
AC |lOP

MB07(0)

—*L

L +

MEM +

;\CiL>.-I.

I
•

MEM—MB
"MEM 41 =

M,^i

MB04 C0>MB09(0)
AC
AC

MB05(I)

I
—

MB0^(O)» MB07 CO
L

—

DATAirOUT

RUN

AUTO INDEX

MB0 8 (I)
5kTP —SKIP

—MB

DATA
i

iuc:.ii_^/o

IN-

JMP

MEM 5-11

—SKIP

I
—

r^-^+

AC-*MB

MB04 (0 •MBOSCi)
AC + A? ^AC

MEM +1

IN -

"tra

CRE.MENT (' CPEMENT
MEM-tl»-MB

PAUSE

MB04C0)«MBO6 (0

SKI P (0)^ SKIP (0

ISZ

JtDT

MB06(I)»AC =

JMP
MB03C 0')|mB0 3(I]AND DCA
TAD JMS
PROCESSCS!

lOT

+
MB05(0»ACO =

JMS

MEM+i = CAflRY

OPR

DCA

PC-»M8

MEM-»IR.

MB03 (0)

)

MBO40>MBO9(.O)

—AC

MB08C0)»MB09 COJ MB04U;«MB09(i)
SR AC
NO SHIFT
MBIO (0)i MBIOd)

—

MSOS U)
ROT

RIGHT

L
MB08 0)

MB09 UJ
LEFT ROT

RIGHT ROT 2

MB09 U)
LEFT ROT Z

zzi
MBIIU;

+ I-»AC
t
brk

MEM

DA TA

DONE

—B

I—»WC

MEM5-H
MA
MB04(0)i MB04(0

SKIP(O)isKIPCl)

MAO—
PC +
—
MA

PC-*I/A

MA 0—4

^
DATA ADD

—MA

MA 0-4

BRK R EQ ^bRI<'
D ATA |PR06 RAM

JMS

CYCLEr 3 CYCLE

REQ

0-»MA
'

Ibrk

PROGRA M

DATA Abo

req

CYC,
1

—B

Re q

AUTO

INDEX V INDEX

BRK

AUTO
D ATA

0-^MA

i_
JMS
—IR
-

DATA ADD

MEM+I
MEM
—MA
—MA

•MA
CY CLE i 3 CY CLE

'
'

H^E

I—

I-

1—
3CYC4

1—WC

REQ

BRK REQ

SKI P (OJJSKI P (

I—

0-»MA

MEM

MA+I

-»MA

MB03COu MB03(b)

REQ JBRK

i PROGR AM

MEM +1

DATA

—MA

•MA

IT"

PROGRAM

ski pCo)^ S K P (
I

DATA ADD |0-^MA

PC-h
—
MA

-CA

CYCf

—JMS
IR

I—

JMS

3CYC£|

I—WC

!-£
,

UNLESS OTHERWISE SPECIFIED
UNLESS OTHERWISE SPECIFIED

T£(a^

EQUIPMENT
CORPORATION

1/7/^

DiMENSiON IN INCHES
/p. h;(i^jfV.-£i^oci4

TOLERANCES
DECIMALS

FRACTIONS

i .DOS

± 1/64

ANGLES

FINAL SURFACE QUAUTY
-I"
REMOVE BURRS AND BREAK SHARP
CORNERS

DATE

^ Cu^^

PROJ^ENG^

DATE

T^.jo...-.-f
i5

DEC FORM NO

nRST USED ON
E

FLOW DIAGRAM
^UTO FUNCTIONS)

-UA^eiSI2E CODE

NUMSER

D FD 81- 0-1
SHEET

:i:

-3

—

1-0 -18 |aJa|2
iital

Equipment Corporation ii

a or copied or used it wfioie
tor the manufaenire or lak oi

MFTO

0—MAJOR STATES

+EX + DP

CONT

—MAJOR STATES

EX + DP

AC
MA

-I-

— PC

0— L
MEM START

MFT2

ICO

MEM START

iO
I

MEM START

To
DP

MEM

—MB

"MB

—RUN
UNLESS OTHEBWISE SPECIFIED

UNLESS OTHERWISE SPECIFIED

DATE

?,^
DATE

DIMENSIOW IN INCHES

TOLERANCES
DECIMALS

FRACTIONS

ANGLES

± .005

- 1/6*

- Or'30'

nNAL SURFACX QUALITY

mmn

EQUIPMENT
CORPORATION

^.jto-j/ 5-/'-4 ' TITLE'

REtMlVE BURRS AISD BREAK SHAItP

DATE

FLOW DIAGRAM

C^Z-

CORNERS

DATE

^.JL.'^^:t
FIRST USED ON

E -UA —81

a-&

(MAN
SIZE CODE

-UNCTIONS)
NUMBER
^
REV,

DFD 8I-Q -I
°|^

17T"

II-5

II-7

Z-

S9 a 2

-19

3Q03 3ZIS
il

EouipoMnt Cerponrtion and tfwi not b*

MM3
D07

-»•

s(0-

^-j^3:^y^ —

S(0)-

:^0

as^n

.aas

>gg

LH*HS

^i^)-4ir"VL
&>^
L^^ziD^
i>^

E09

IM3I0

jD06

L-

TPI

TO (El 7 H2)

UNLESS OTHERWISE SrednED

OWL

l~>

EQUIPMENT

n»TE

SBIDDgO CORPORATION

UNLESS OTHERWISE SPECinED

K IHMr

BJiir'

TIMING MANUAL
FUNCTIONS^ RUN

RRST USED ON

E-UA-ai-0-0

SOECaOE

NUMBER

DBS
f

of2

"'^l

81-0-2
I

I^T
1

II-9

II-ll

11-13

11-15

11-17

— o — iQ saa 2
3a0J szis

aaawnw

s drawing arfd specifications, tiarein. are the prop'
erty of Digital Equipment Corporation »nd shall not bm

lepraiucrnl at copied or used ih whole or

c*it as

NOTE:

SIGNAL NAMES INDICATE
ASSERTED STATES FOR HIGH (H)
LEVELS PER DEC STD 054

803

UNLESS O'mERWISE SPECIFIED

'.^
'-g^-n,^.

UNLESS OTHERWISE SPECIFIED

1-^

DIMENSION IN INCHES
/;q.&^7-S^j>

TOLERANCES

If*
5?,_::

^ijy

FRACTIONS

EQUIPMENT

DATE^

SfllDDID CORPORATION

ANCLES

± .005
± 1/6*
± o'ao"
HMAL SURFACE QUALITY
REMOVE BURRS AND BREAK SHARP

{

Coi^-t^

-•:?

INTERRUPT $
BREAK CONTROL

FIRST USED ON

E-UA-8I-(

-y^^k^
EC FDftM ^0

DECIMALS

NUMBER

SIZE CODE

DBS

bl-

0-7

a±Ld tl

11-19

11-21

11-23

—

6-0-18 Saa 2

drawing a«l speeilcatons.

herem. ar

"'»°^'" '"*
•S ot DigiOl Eo.ipm.nt
MpW "< u»^ '^ "*"^

°'

oduced or

the basis tor U«

manofaoture or sale of rti

RES BUS 03
EK2

\0^B

M220
E35

MZ2

F35

F36

BEG BUS 05

E36

REG BUS 04
1

EK2

EJI

SISNAL NAMES INDICATE
^ccEPT'^D STATES FOR HIGH (H)
L^VEi S PER DEC STD 054

MB05^

MB^4«Jl

FB2

MB03I?»

£02

AND ENABLE

ED2

RIGHT SHIFT
DOUBLE RIGHT ROTATE
NO SHIFT
LEFT SHIFT
DOUBLE LEFT ROTATE

EDI

ADDER02

EFI

ADDER 03
ADDER 04
ADDER 05
A DDER 06

EH2

EEI

EF2

OUT

ECl

EE2
EFI

EH2

—

IT LINE SHIFT
CARRY

EDI
EEI
EF2

EB2
-CARRY

EB2

OUT

ADD
ADD

lO
I

AC05(1) AC05C0) M0LO5(0

DATAO5ius"05"05C,)PCO5C0ME«O^«0

ACO4C0 AC04(0) MQO40)

SCO

Fd2

ENABLE
MQ ENABLE
SR ENABLE
SC ENABLE
FLI
DATA ENABLE
FL2
I/O ENABLE
FR2
MA ENABLE 0-4
FS2
PC ENABLE
FVI
MEM ENABLE 0-4DATA ADO ENABLE

FF
FCI

FF2

FLI

FL2

FPI
I

FS2
FU2
FT2

5-1

ENABLE

WEM ENABLE

FH2
ITEM
HO.

DESCRIPTION

ENABLE

PARTS LIST

UNLESS OTHFPWISF SPECIFIED
UNLESS OTHERWISE SPECIFIED
DIMENSION IN

HCHES

°/^9,/&^Jz,

fi'^%1

CHK'D

DATE

;

FRACTIONS

. ,005

± 1/84

TITLE

ANGLES

»»

HNAL SURFACE QUALlTf
SHARP
REMOVE BURRS ANO BREAK SHJ
CORNERS

DATE

^tr

T.
P80J, EN6.

Tl'j/^
MATERIAL

CORPORATION

-11-1.7

TOLERANCES
DECIM*15

FIRST

U^D ON

E-UA-8I-

fl>-u-,
\

MAJOR
REGISTER
GATING

SIZEtCODt

B5 81FINISH

SHeET

EQUIPMENT

NUMBER

0-9

tzJ

11-25

6—0-19 Sa a 2
drawing and speeificttiom, berBio, are th« property of DiBital Equipnwnt Corporation nncl shal not be
i- n-rf
'- "*-"
or

copied

reproduo**
the bMi

—

M220

wiubcture or sal* of ItEnn witrnul

REG BUS 07

REG BUS 06

M220
E38

F37,

F38

REG BUS 08
EJI

|eK2

EJI

NOTE-

E37

SIGNAL NAMES INDICATE
ASSERTED STATES FOR HIGH (h;
LEVELS PER DEC STD 054

Fsa

MB08®

AND ENABLE

ED2

RIGHT SHIFT

DOUBLE RIGHT ROTATE
NO SHIFT
LEFT SHIFT

EDI
EEI

EDI

EF2

EF2
EHI

DOUBLE LEFT ROTATE

ADDER

ADDER 06
ADDER 07
ADDER OS
A DDER 09
TT LINE SHIFT

CARRY

OUT

EFI

EBI
ECl

EH2
EJ2

EFI

FJI

ADD

ADO

FK2

OUT

-CARRY

lO
I

ACOStO AC06(0) MQ06(0
W0777 —-___,

A40

AC ENABLE

MQ ENABLE
SR

ENABLE
SC ENABLE
DATA ENABLE
I/O ENABLE
MA ENABLE 5-M
PC ENABLE
MEM ENABLE 5-B
DATA ADD ENABLE
AC ENABLE

^R
21.

V2 *

OATilOe INPUT

BUS 06

MAOSO) PC06CI MEM 06
)

DATA
ftCDOe

)

AC07(0 AC07C0) MQ 07(0

W077 ^
B40 (

(l)

DATA07

NIPUT MA07CI ) PC07(|) I

Acoeco

BU5_07

2L1
SCQ

FJ2

FFI
FCI

FCI
FLI

FL2
FR2
FS2

FS2

FT2

UNLESS OTHERWISE SPECIFIED
UNLESS OTHERWISE SPECIFIED

"^.^S^

DIMENSION \K INCHES
.

TOLERANCES
DECiM*LS

FRACTIONS

ANGLES

- .005

- 1/M

i 0°30'

FINAL SURFACE QUALITY
REMOVE BURRS AND BREAK SHARP

DATE

,JL

^j.

^JL

EQUIPMENT
CORPORATION

f.jaA.^/JJXO

PJOJ, EN£

MAJOR

ti-'
,

DATE

RRST USED ON

E -UA- 81-0

CODE

0-9

BS 8T-

11-27

11-29

erty nf Digital £c|uipm*n< Corporation and (hall not b
repfoduc« or copied m
the bavs tor the -nanufa

— 0—18 59 a 2
a i«(!Ti;.Li2t

00(0

BAC

(I)

02(0

BAC 03(1)

BAC 04 CO
t

M2
K2

H08
'

JM2|N2[P2

AC 01 (I)

AC 03 (I)

A R2
1

JT2|U ^V

AC 04 (0

07(0

BAG

t S2

M65I

AC 00 (0

BAC 06( 1)

BAC 05 (l)

BAG 10(0

BAG

vIDL^l'C

TE2

»H2

K2 M65I

+3V

H09
E2

(49)

w3j r"

08(0

BAG

BAG 09(1)

HIO

(50)

IfSThzIjz

AG 05 (0

AG 06 (I)

M2|N2 |P2"

rrzlua v

AC 07 (0

F2H4J2
AC09 (0

8 (I)

+ 3V|

M2JN2 r

BIOP 1(0)

BIOP

• M2

M65i

11(1)

BIOP 4(0)

2(0)

PZ
U&5I

F2H2J2

lOP 1(0)

MaN2 [P2

?T2

TZ UZ V2
l

•F2|H2 lJ

lOP 2 (0)

fV2~)
M65:
HI2

+ 3V
(50

HII

AGII (I)

BTSKQ)

(50),

T2[U2l'V2"

BTS3(0)

I0P4(0)

M2|N2lP

TS3(0)

'bMB09(0

BMB

rr2|u2 lv

INITIALI2

(0)

BMBOO (I)
J03

BMB02(0

BMB01 (0

won

BMB03(0)

BMB03(I)

BMB04 (0)

BMB05 (0)

BMB04 (I)

BMB05 (0
—'^

-i"

M6&I
HI3

M65I
+ 3V
(52)

|F2|h2 |J2

VISJNZ PZ

m2|n^P2

'~INPUT BUS GO

MBOI (!)

MB02 (0

MB 03 (0)

MBOJ(I)

BMB06 (0

BMB07(0)

F2H2IJ2

T2|u2lvg

MB04(0)

MB04(I)

M2|N^ P

•^2

BME

10(1)

M6 5r

•^Z

+ 3V'

M65I
HI7

(53)1

|h^J2

|M2|N2[p2
|

MB06 (0)

MB06 (I)

INPUT BUS 01 INPUT BUS 02 INPUT BUS 03 INPUT BUS 04 INPUT BUS 05 HnPUT BUS 06 INPUT BUS 07 INPUT BUS 08 INPUT BUS 09 INPUT BUS
.J2
y\LI
/KfZ
y\S\

rz|U2JV2

|F2|h2 j2

JM2|N2[ P2

[

/^V2

MB07 (I)
|

M65I
HIS

-I-3V

(54)

MB07 (0)
INPUT BtJS

'<2

j/q SKIP

/\EI

M506

J-2p2JV2

Mn2[P2

|F2|H2 J2
|

MB08 (I)

INT RQST
yKJZ

AC CLEAR
,LI

(54)

MB08(0)

(I)

vr3

HI6

T2 U2 hV2

MBOSd)

BMB08(I)

TE2

MB05(0)

BMB08(0)

BMB07(I)

(53)

MBOO (0

BMB06 (O)
\

+ 3V

(52)

;|h^j
FZH^JZ

!''^
j

M65I
HI 5

+ 3V

mr \ji
nWOI

Jj04 (fD2^

MB09 (I)

JT2|u2[v2

MBIO (0

MBII (0

LINE (0)
Im506
p7
I

WOn /

B TT INST

B RUN(0)

~—

|J|5

4
I

IHJ

JOS C TS2
D2 M65I
HI9

won

__|12

|^__h

__\°}_

DATA ADD 06

DATA ADD 07

iE2

H2
K2
M2
P2
JOS
^AT^ ADD^ 00 _pATA AD^ 0I_ DATA^ADp_0Z_ _DATA_Amj)3 _DATA_ADp^4_ D_ATA ADD 05

/\.p,

/\j2

^" M606 Ap2
JI6

Av"2"r--A-i|

Asi
I

\\^l\

^y?
I

|i2

lUTo'iCI^
_
DATA

DATA ADD 08

ADD 09

Afl "m506~/Y2'
I

JI7

m^
*E2
DATA ADD 10

/V'
II

ZJ^_

H2
DATA ADD II

+ 3V(55),

|D2

BRK RQST

7^'
/V^'
(11'^
"^

p^-^^

^"-^

FzMJZ 1
RUN (0)

PJMPZ
TT

INST

Zo^a^

^a-1

MEMORY INCREMENT

M505

11-31

11-33

n-35

11-37

-0-18
gwnN

sg a 2

3Q03 3JIS

drawing and specifications, herain. »re tfie prop- [
efty ot Digital Eauiprunt Corporation and shall not tw
reproduced or copied or used in w^ole or in fiart as I
basib loi tne marufalilirt or »ale of items witnout
|

W02

R|Tg624
M il B39
X2

lo
I

SCO

SLICE

|_0_2_E2
W025,
A8?4 C

FZ_>^ D2_ E2_ F2_ H2

^A12iAT2

"_!_

Nl _ P^,

D2 _ E2 F2_ H£
*AH2 •AJ2

•AE2 *AF2

'AC2 *AD2

W025^
Ab29

J^l

l^_!li

f^l

_ ^Jj £5_ |i L^_ li

'IL

!11

^ L 5?_

11.

[miTnI

|D2 |E2 |F2

[pi

\HZ Tu

|n1

[pn
TdFIezTfFThZ Tili
'nlD

[MiTnTTpi

._l

*AE2 iAF2

BH2 iBJ2

'AP2 •AR2

iAP2*AR2

iBE2 *BF2

*BK2 *BL2

BM2 *BN2

BK2iBL2

BH2 BJ2

BM2 BN2

**USED WITH MP8I

^ USE 602C

ONLY

MC8I

*BP2*8R2')

NOT .INSTALLED
UNLESS OTHERWISE SPECIFIED

NOTE:

SIGNAL NAMES INDICATE
ASSERTED STATES FOR
HIGHCHJ LEVELS PER DEC
STD 054

UNLESS OTHERWISE SPECIFIED
DIMENSION IN INCHES

TOLEiMNCES
DECIMALS

FRACTIONS

ANGLES

• .005

± l/fi4

± 0°3D'

FINAL SURFACE QUAUTY
REMOVE BURRS AND BREAK Shi
SHARP

CORNERS

^ i^.Uje4.*u^^

JsM 7

'^^^^^—-^

f yXi

EQUIPMENT

DATE
DATE

SDIDQSD CORPORATION

DATE

dfiXf*-

T^f^x.
DATE

MATERIAL

SENSE AMPS $
INHIBIT DRIVERS

FIRST USED ON

£— UA -BI CODE

NUMBER

8I-0-I4

DIST.
I

DEC FORM NO.
ORG 10:

11-39

>rc th» prop-

-iwni -itHout

SI— 0-19 99

* ;-

^-^ G6M

• Ckgitfc tqjiDn^nl CorpOfWitu

CD36*

Isz

CU2

"-t3-

CT2
"-D*-

CS2

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MS"

CR2

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MAOI

s:gnal HfiKis

n; gate

ASSERTED STi-i^s FOR

JL2^

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(!)

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CP2

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CM2
T2

'M3-

40 ^

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J 7

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CK2
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CJ2
'-cf-

;0'-»-

CH2

CF2
.-ct-

MAOI (0

m:^^ r=a>

CE2

St*"

CD2

MA02 (I)
NEG
1

LAMP

i£>
Vi

MAOO CO)-

-O-

B FIELD CO)i—2-?-

^XiJcD34

R/W SOURCE

W RETURN
5

MA05 CI)
UNLESS OTHEIIWISe SPECIFIED
UNLESS OTHERWISE SPECiriED
DIHEMION IN INCHES

°^g,^Skv^

^7/fc^

cHiijij:

DATE

TOLERANCES
OECIMAU

FHACTIONa

ANQLEl

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± i/«4

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C A tl-OtT

nnM. SUKFICE QUAUTV
KCUOVE MJRM AND MEAX ShJ
HUP

n.^'^wfr

EQUIPMENT

SflSDDSD CORPORATION

DATE

«fr7JX

AXIS

SELECTION

CtMNEn
MATERIAL

1/u.l

RRST USED ON

- JA-8I

X,;:' 3

-0-0

i
SHEET

COM
S

NUMtER

"litv-

81- 0-15

11-41

U-43

5 SChLMAIiC is FURMSHtD ONI.T FOR TEST AND MAiNTtNftNCE F=URPOSES. TH
CUirs APe PfiOPRI£TAHV in NATUHE and should be TRPlWeD ACCORDINGLY
COPYRIGHT IIBT Br DIGIIAL (QUIPMENT CORPORAriON

,_w^
f%

Jo. I-

^»°
"7

-to

|»f!

3
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r* oe c «

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X
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dice (£

n^x

TRANSISTOR S DIODE CONVERSION CHART

—

D-A

10 BIT

CONVERTER A607
^EQU

P M E N Tl

.iCORPORATlONl
DEC FORM HO.

CODE

NUMBER

CS [A607- 0-I
M»PNTED CIBCOIT REV

11-45

UNLESS OTHERWISE INDICATED:

RESISTORS ARE I/4W, S%
MF RESISTORS ARE l/8W,l%
CAPACITORS ARE .OIMFD.IOOV,
20%
DIODES ARE p662
ARE MCI540e
E2 IS DEC7400N
PIN 7 ON EACH IC =6ND
PIN 14 ON E2= + 6V
PIN 2 0tJ EI,E3=+5V

El, E3

USE THE ETCH BOARD OF THE 6021

Sense Amp.

B-CS-G020-0-1

f4H>7ff^
H^^f^^T)?-.

XDII

D6E2

vDIO

^0662

RI7

>470

MFD
35V
20%:

C6
:.oi

MFD

20%
UNLESS OTHERWISE INDICATED:
TRANSISTORS ARE DEC2904
DIODES ARE D€72
RESISTORS ARE l/4YI(, 5%
RESISTORS ARE 1,500
CAPACITORS ARE33OMMFD,IO0V, 5%
EZIS EC7400N
E3 a El ARE DEC7440N
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC:+5V

B-CS-G22 1-0-1

Memory Selector

11-47

^.01
MFD

MFD

20%

20%
C7

:.oi

^.01

MFD
cs
;6.8

CIO

C8
:.oi

,09
.0662

20%

MFD

20%

-O AN
INDICATED:

UNLESS OTHERWISE
CAPACITORS ARE 2°"''° *°)'„ ^._. -vpc 60465-8 (AMP INC)
USING AN
TABS ARE 250
f„'''VJ";°"«;KEP,ErD TYPE NC-623-A
aWAKEPIE.0 TTPE 1.0

SVo^X^lVlNUM^srACfwisHER
THERMAL JOINT COMPOUND

B-CS-G805-0-1

Negative Regulator

11-49

UNLESS OTHERWISE INDICATED:
DIODES ARE MR2066
TRANSISTORS ARE DEC6S940
El IS DEC74Z0N
PIN 7 ON IC • 6ND
PIN 14 ON IC ' *5V
RESISTORS ARE 1/4 W, 10%

B -I5V

Solenoid Driver

B-CS-M040-0-1

+SV

NOT USED -I5V

OND

C2, Tl

A
E3

L2 M2

P2 R2

notes:
pin 7 on each ic = ono
pin 14 on each ic'+sv

B-CS-Mll 3-0-1

10-2 Input NAND Gates

-51

+5V

NOTES
PIN 7 ON EACH IC= SND
PIN 14 ON EACH IC = «5V

B-CS-M160-0-1

Gate Module

UNLESS OTHERWISE INDICATED:
CAPACITORS ARE .01 MFD
PtN 7 ON EACH IC=GND
PIN 14 ON EACH IC =+5V
EI,E2, E4,E5,E6,E7, E8, ElO a
Ell ARE DEC7420N
E3 a E9 ARE 0EC743ON

K2 L2

B-CS-Ml 62-0-1

n-53

Parify Circuit

SCHEMATiC IS FUBMSHED ONLY FOB TEST AND MfllNTENflNCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
fRIGHT 1967 BY DIGITAL EQUIPMENT CORPORATION

AV2

AVI

-AC2, ATI,BC2, BTl

-+5V

+1
rizcB

+
i"^
^750

::J:;ci

tL
+L
tL 3! tL cs
::j::c2
^C3 *L
^C4 +1
::^C5 :±:C6 :±:ct
ij:

GND

^i'°

aI
e[^5

^000

>3,000

f3V

^'^^''^

SHIFT RIGHT
SHIFT RIGHT TWICE

ADDER 5
AJ2

SHIFT LEFT TWICE

ADDER
3
EI3
a

PQBQQ

UNLESS OTHERWISE INDICATED:
E4,EB,E9,£10 ARE DEC7474N
E3.E5,E6 ARE DEC7460N
E2 EI2, EI5, E 14, EI6, EI7,EI8 ARE DEC74S3N
E
EI3 IS DEC74e2N
PIN 7 ON EACH IC EXCEPT EI3 = GNO
PIN II ON EI3=6ND
PIN 14 ON EACH IC EXCEPT EI3 =
PIN 4 ON E13=+5V
I

RESISTORS ARE t/4W;iO%
CAPACITORS ARE 6.8 ypD, 35V,
E7

a Ell ARE DEC7440N

MQ3(1}

SR3

BN2

BD2

AC ENABLE -

AC ENABLE MO ENABLE SR ENABLE '
SC ENABLE DATA ENABLE 10 ENABLE '
MA ENABLE
PC ENABLE
MEM ENABLE DATA ADDRESS ENABLE -

PARTS LIST A-PL-M220-0-0

TRANSISTOR t, DIODE CONVERSION CHART

E^Zfy_
ta

MAJOR REGISTERS M220
0EC3OOW

ZH5001

EQUIPMENT
CORPORATION

NUMBER

CODE

SIZE
I

MZZO-O-I

PRINTED CIRCUIT REV.

11-55

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 19*7 BY DIGITAL EQUIPMENT CORPORATION

R<^
3,000

INTERRUPT

aF2

3,0005

-AA2,BA2 +5V
1

<RII

$3>000

^
1

DEC
3009B
BE2
SKIP

AK2

MB3(ll

MBSd)

;:' MB4(»1

fgf MBSd)

MBTCI) "pjUBBMl

AS2

Apia)

B02

SLOW

ilZ^
^-

lapllal

UNLESS OTHERWISE INDICATED:
TRANSISTORS ARE DECeS34B
RESISTORS ARE l/4W,S%
DIODES ARE 0664
PIN 7 ON EACH IC«GND
PIN 14 ON EACHIC:+5V
El IS A DEC7430N

E2,ES,Ee,EI4 ARE 0EC7474N
E3, ES, E9, Ell, EI2, Ei6,er7ARE DEC7400N
E4, E7, EI0,EI3,EI9 ARE DEC74eON
EIS, Eia ARE DEC74I0N

CAPACITORS ARE .01 UFD

UDI

PARTS LIST IS A-PL-M704-0-0

TRANSISTOR A DIODE CONVERSION CHART

PLOTTER CONTROL M704
a8

.EQUIPMENT
JC0RP0RAT10N

M704-O-I

PRINTED CIRCUIT REV

11-65

i<B3(ei

tr\^

EIO

HB4(e)
MBSlet
NB6I«)
MB7(e)

MBSdl

AAZ.BAZ

CI9

|Jj

C2i

6.8

e.B

^MFD

CI7

::f:ci5

:mfd

35V

~CI8

:ci4

C2a

35V

-r-6.8

MFD
3SV

— ^—V
T.P.

•

"^ SKIP

I
E2
RD 2

E2
RD 3

RD4

RD 5

r
SHIFT

ei2

ENABLE (0]
BK2

UNLESS OTHERWISE INDICATED:
CAPACITORS ARE .01 MFD
PIN 7 ON EACH IC - GNO
PIN 14 ON EACH IC>4-5V
EI,E2,E3,E4, ES,EII,EI2 ARE
0EC7474N
E6, E7, ES ARE DEC740IN
EB, EIS,Eie,EI7, Eia ARE DECT400N
EIO IS DEC7430N
EI3 IS 0EC7440N
EI4 IS 0EC74I0N

EI2

POWER

l-d

ENABLE

"£>
Ell

A
C

BN2
BNI
STOP
T.P
COMPLETE

C-CS-M705-0-1

PRDT
II

BDl

J-d

RD6

Os
NI

Reader Control

liz

Y FOR ItST AND MttlNTEMiNCE

rUHPOSES THE

>UD ACCORT

CIRCUHS
'WENT com

"
"

GND
CIS

ATI

AC2
BTI

BC2

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4IW, 9%
TRANSISTORS ARE DEC6934B
CAPACITORS ARE .01 MFD
PIN 7 ON EACH IC = GND
PIN 14 ON EACH 10 =f5V
El, E2,E5,E4,EI0 ARE DEC7474N
E5,E7 ARE 0EC74O0N
E6 IS DEC74I0N
EB IS DEC7430N
E9 IS DEC7440N
EII,EI2 ARE 0EC7460N
DIODES ARE D6G4

C-CS-M71 0-0-1

Punch Control

STROBE
E

UNLES« OTHERWISE INDICATED:
CAPACITORS ARE .01 MFD
DIODES ARE 0664
RESISTORS ARE I/4W, S%
TRANSISTORS ARE DEC300BB
El, E3, E4 ARE DEC7400N
PIN 7 ON EACH IC • SND
PIN 14 ON EACH IC • f SV

E2 IS DEC7460N

J5 ^-

A
.02'

MMFD

MFD

B-CS-M720-0-1

vvA
C8
660

220

• "*

CRS

>220

Memory Detecfion

11-72

PART

III

APPENDICES

APPENDIX A
LOGIC SYMBOLOGY
The symbology employed with the PDP-8/l and
OR - The symbol shown below represents the
M-serles modules is similar in nature to MIL-STD- OR function. The OR output (F) is high if any
806B. This appendix describes the modified DEC one or more inputs (A and B) is high,

symbology with definitions of logic functions,
graphic representations of the functions, and ex-

amples of their application.

A Table of Combi-

—

nations is also shown.

~\
,

OUTPUT
SIDE

LOGIC SYMBOLS

A.l

In the following list of logic symbols, truth tables

accompany the graphic representations The truth
tables use the letters H to mean HIGH (+3V),
and L to mean LOW (OV).
.

A. 1

INPUT

OUTPUT

B
L

L
L

H
H

H
H
H

State Indicator

The presence of the small circle symbol at the

A. 1 1 .2 State Indicator Present - NAND The symbol shown below represents one version
of the NAND function. The output is low only
.

input(s) of a function indicates that the rela-

tively low (L) input signal activates the functions;
the absence of this smol circle indicates that a
relatively high (H) input signal activates the
I

NAND logic

when all of the inputs are high.
is

the major gate configuration of the PDP-8/I.

function. Similarly, a small circle at the output of a function indicates that the output ter-

minal of the activated function is relatively
A

low, whereas, with the absence of the circleat
the output of the symbol, the output is relative-

Examples of this symbology are shown
below with the AND and OR functions, and
also in Table A-1
ly high.

AND - The
symbol shown below represents the AND funcA. 1

L
L
L

H
H
H
H

INPUT
B C

OUTPUT

L
L

L
H

H
H

H
H
H
H
H
L

State Indicator Absent -

NOR - The symbol shown below represents one
version of the NOR function. The output is

The output (F) is high only when the inputs (A and B) are high.
tion.

INPUT
SIDE

D
r>

low if one or more of the inputs is high.
.

OUTPUT
SIDE

INPUT
A
B

OUTPUT
F

A-1

INPUT

ABC
L
L

OUTPUT
F

L
H

L
L

NOR - The symbol shown below represents another version of the NOR functions. The output

A. 1.3.

Flip-Flop

high if one or moreof the inputs is low. Note
that the truth table for this function is identical
is

to one version of the

NAND function.
INPUT

ABC

OUTPUT
F

L
L

L
H

H
H

A. 1.2 Table of Combinations

The fl ip-flop is a device that stores a single bit
of information. It has three possible inputs, set
(S), clear (R), and the data input (C and D).

There are two data outputs,

and 1

The graph-

D type flip-flop is

ical representation of the

shown below. If the D input is high when a pulse
appears at the C input, the flip-flop will set (1).
Similarly, if the D input is low when input C is
pulsed, the flip-flop clears (0). The converse of

Figure A-1

i I

lustrates the applications and func-

tionsof two variablesand equivalents as well as

the relationship to DEC-DTL logic.

the above two statements is true when the graph c
symbol D input hasa small circle preceding it.
Thedirect clear and direct set inputs are normali

AND

I^- :=^:>-"
:^::^- :=r>:

:--^I>- :=^:>-

:^I>-' :=!>-

ABC
H

L
L

L
H

H
H
L

H
L
H

L
L

L
H

:^D— :=^:^-

H
L

L
H
L

L
H
H

:^D—

L
L

H
H

H
L
L

:z^I>-' :=!:>-

D— :^ivA-2

L
L

H
L

L
H

H
M

The clear and set functions occur with
a high-to-low transition.
ly

high.

opposite state and remains there until the input

no longer remains above the actuating threshold
voltage.

Uiiecl

A. 1.6 General Logic Symbols
A. 1.4 Single-Shot Functions
The symbol shown below represents the singleshot (SS) function.

Output signal shape, amp-

Symbols for functions not specified elsewhere are
normally represented as shown below. An example
of this symbology is the PDP-8/I Inhibit Driver.

litude, duration and polarity are determined by

the circuit characteristics of this device. The
unactuated state of the SS is either a Oor a 1.

When the input is actuated by a high-to-low level
change, the 1 output goes high and remains high

A. 1.7 Amplifier

for the duration of the active time of the device.

Similarly, when the input isactuated, the

out-

put goes low for the time duration of the device.

This symbol represents a linear or nonlinear current or voltage amplifier. Level changers, inverters, emitter followers and lamp drivers are
examples of devices for which this symbol is

SS
2.5

applicable.

ONE OUTPUT
(ORI

^\tL -4^^ -^^^ -^

SS
2,5

TWO OUTPUT

A. 1.8 Time Delay Symbo

A. 1.5 Schmitt Trigge r
The symbol for a delay is shown below.

The

The symbol shown below represents the Schmitt
trigger (ST) function. The device is actuated

when there are two or more outputs, in this

when the Input signal crossesa certain threshold

case the outputs have the duration time adja-

voltage. Output signal amplitude and polarity
are determined by the circuit characteristics of

cent to each output.

duration is specified within the symbol except

The unactuated state of the ST is
or 1 . When actuated, it changes to the

this device.

either

A-3

—

5MS)
I

<0R1-

~\MS

f-1

SMS
3MS

APPENDIX B
TABLES OF PDP-8/1 INSTRUCTIONS
Memory Reference Instructions
Direct Addr. Indirect Addr.

Mne-

Opera-

monic
Symbol

tion

Code

ExecuStates

Entered

AND Y

F,E

tion

Time

ExecuStates

Entered

3.0

F,D,E

Operation

tion

Time

4.5

AND.

Logical

The AND op-

eration is performed between
the content of memory location

Y and the content of the AC.
The result is left inthe AC, the
original content of the AC is lost,

and the content of Y is restored
Corresponding bits of the AC and
Y are operated upon Independently.

ACj A Yi=>ACi

TAD Y

F,E

3.0

F,D,E

4.5

Two's complement add. The
content of memory location Y
is

added to the content of the

AC in two's complement arithThe result of this ad-

metic.
dition

held in the AC, the

original content of the AC
lost,

and the content of Y is

restored.

If there is a carry
from ACO, the link is comple-

mented.

ISZ Y

F,E

3.0

F,D,E

4.5

AC + Y = > AC

Increment and skip if zero.
The content of memory location Y is incremented by one.

Y then equals zero, the
content of the PC is increIf the

mented and the next instruction
is skipped.
If the resultant content of Y does not equal zero,
the program proceeds to the next
instruction. The incremented
content of Y is restored to mem-

B-1

ory.

PC +

resultant Y = 0,

= > PC

Memory Reference Instructions (Cont)
Direct Addr. Indirect Addr.

Mne-

Opera-

monic
Symbol

tion

States

Code

En-

Execu-

Time

tered

tion

En-

F,E

3.0

Time

tered

(ps)

DCA Y

Operation

States
tion

(ms)

F,D,E

4.5

Deposit and clear AC.

The

content of the AC is deposited
in core memory at address Y

and the AC is cleared. The
previous content of memory
location Y is lost.
AC = > Y
= > AC

JMS Y

F,E

3.0

F,D,E

4.5

Jump to subroutine.

The con-

tent of the PC is deposited in

core memory location Y and
the next instruction is taken

from core memory location

Y+ 1.
PC +

Y+
JMP Y

1,5

F,D

3.0

= > Y
= > PC

Jump to Y. Address Y is set
into the PC so that the next
instruction

taken from core
The orig-

memory address Y.
inal

content of the PC is lost.

Y = > PC

B-2

Group
Mnemonic

Octal

Symbol

Code

Operate Microinstructions

Sequence

Operation

NOP

7000

No operation. Causes a

lAC

7001

Increment AC. The content of the AC is incremented by one in two's complement arith-

,5 jas program delay.

metic.

RAL

7004

RTL

7006

Rotate two places to the left. Equivalent to
two successive RAL operations.

RAR

7010

Rotate AC and L right. The content of the AC
and L are rotated right one place.

RTR

7012

Rotate two places to the right. Equivalent to
two successive RAR operations.

CML

7020

Complement L.

CMA

7040

Complement AC. The content of the AC is set
to the one's complement of its current content.

CIA

7041

2,3

Rotate AC and L left. The content of the AC
and the L are rotated left one place.

Complement and increment accumulator. Used
to form two's complement.

CLL

7100

CLLRAL

7104

1,4

Shift positive

CLL RTL

7106

1,4

Clear link, rotate two left.'

CLL RAR

7110

1,4

Shift positive

CLL RTR

7112

1,4

Clear link, rotate two right.

STL

7120

1,2

Set link. The L is set to contain a binary

CLA

7200

CLA AC

7201

1,3

Set AC =

GLK

7204

1,4

Get link.

CLA CLL

7300

STA

7240

Clear L.

number one left.

number one right.

Clear AC, To be used alone or in OPR 1
combinations.
1

Transfer L into ACll

Clear AC and L.
Set AC = -1 .

contain a

B-3

Each bit of the AC is set to

Group 2 Operate Microinstrucfions
Mnemonic

Octal

Symbol

Code

HLT

7402

Operation

Sequence

Halt.

Stops the program after completion of

the cycle in process.

If this

instruction

combined with others in the OPR 2 group the
other operations are completed before the
end of the cycle.

OSR

7404

OR with switch register.

The OR function is

performed between the content of the SR and
the content of the AC, with the result left in
the AC

SKP

7410

The next instruction is

Skip, unconditional.

skipped.

SNL

7420

Skip if L 7^0.

SZL

7430

Skip if L = 0.

SZA

7440

Skip if AC = 0.

SNA

7450

Skip if AC 7^ 0.

SZA SNL

7460

Skip if AC = 0, or

SNA SZL

7470

Skip if AC 7^ Oand L = 0.

SMA

7500

Skip on minus AC.
is

L= 1, or both.

the content of the AC

a negative number, the next instruction is

skipped.

SPA

7510

Skip on positive AC.

If the

content of the AC

a positive number, the next instruction is
skipped.
is

SMA SNL

7520

Skip if AC < 0, or L = 1 , or both.

SPA SZL

7530

Skip if AC >0and if L = 0.

SMA SZA

7540

Skip if

SPA SNA

7550

Skip if AC > 0.

CLA

7600

Clear AC. To be used alone or in OPR 2
combinations.

LAS

7604

1,3

Load AC with SR.

SZA CLA

7640

1,2

Skip if AC = 0, then clear AC.

SNA CLA

7650

1,2

Skip if AC 7^ 0, then clear AC.

SMA CLA

7700

1,2

Skip if AC < 0, then clear AC.

SPA CLA

7710

1,2

Skip if AC > 0, then clear AC.

B-4

AC< 0.

Exfended Arithmetic Element Microinstructions
Mnemonic

Octal

Symbol

Code

MUY

7405

Sequence

Operation

Multiply.

The number held in the

mul-

tiplied by the number held in core memory lo-

cation PC +
(or the next successive core
memory location after the MUY Command). At
the conclusion of this command the most signif1

icant 12 bits of the product are contained in

the AC and the least significant 12 bits of the

product are contained in the MQ.

Yx MQ = > AC, MQ.
DVI

7407

The 24-bit dividend held in the AC

Divide.

(most significant 12 bits) and the
significant 12 bits)

MQ (least

divided by the number

held in core memory location PC + 1 (or the
next successive core memory location following the

DVI command).

At the conclusion of

command the quotient is held in the MQ,
the remainder is in the AC, and the L conthis

tains a 0.

If the L contains a 1 , divide overflow occurred so the operation was concluded

after the first cycle of the division.

AC, MQ- Y = >MQ.

NMI

7411

Normalize. This instruction is used as part
of the conversion of o binary number to a
fraction and an exponent for use in floating-

point arithmetic.
the AC and the

The combined content of

shifted left by this one

command until the content of ACO is not
equal to the content of ACl , to form the
fraction.

Zeros are shifted into vacated

MQll positions for each shift.

At the con-

clusion of this operation, the step counter

contains a number equal to the number of
shifts performed.

The content of L is lost.

ACj = > ACj -1

ACO = > L

MQ0 = > ACll
MQj - >MQi -1
= > MQll until ACOt^ ACl
SHL

7413

Shift arithmetic left.

This instruction shifts

the combined content of the AC and

MQ to

the left one position more than the number of
positions indicated by the content of core

memory at address PC +
(or the next successive core memory location following the SHL
command). During the shifting, zeros ore
1

shifted into vacated MQll positions.

B-5

Extended Arithmetic Element Microinstructions (Cont)
Mnemonic

Octal

Symbo

Code

i~i„«..„f;^„
Operation

Sequence

SHL (Cont)

Shift

Y+

positions as follows.

AC] = > ACj -

ACO = > L

MQO= > ACll
MQj = > MQj -

= >MQ11

ASR

7415

The combined content
shifted right one
position more than the number contained in
Arithmetic shift right.
of the AC and the

(or the next succesmemory location PC +
sive core memory location following the ASR
command). The sign bit, contained in ACO,
1

enters vacated positions, the sign bit

pre-

served, information shifted out of MQl 1
lost,

and the L is undisturbed during this op-

eration.

Shift Y +

positions as follows:

ACO = > ACO
ACj = > ACj +

ACll => MOO

MQj = > MQj +
LSR

7417

Logical shift right.

the AC and

The combined content of
shifted left one position

more than the number contained in memory
location PC + 1 (or the next successive core

memory location following the LSR command).
This command is similar to the ASR command
except that zeros enter vacated positions instead of the sign bit entering these locations.

Information shifted out of MQl 1

lost

and

the L is undisturbed during this operation.
Shift

Y +

positions as follows:

= > ACO

ACj = > ACj +
ACll => MQO

MQi = > MQj +

MQL

7421

Load multiplier quotient. This command clears
MQ, loads the content of the AC into the

the

MQ, then clears the AC.
= >

AC = > MQ
= > AC
SCA

7441

Step counter load into accumulator.

The con-

tent of the step counter is transferred into the

AC, The AC should be cleared prior to issuing
this command or the CLA command can be

B-6

Extended Arithmetic Element Microinstructions (Cont)
Mnemonic

Octal

Symbol

Code

Sequence

SCA (Cont)

Operation

combined with the SCA to clear the AC, then
effect the transfer.

SC V AC = > AC

SCL

7403

Step counter load from memory.

Loads com-

plement of bits 7 through 1 1 of the word in

memory following the instruction into the step
counter.

MBy.ii => SC
PC + 2 = > PC

MQA

7501

Multiplier quotient load into accumulator.

The content of the

AC.

transferred into the

This command is given to load the 12

least significant bits of the product into the

AC following a multiplication, or to load the
quotient into the AC following a division. The
AC should be cleared prior to issuing this command or the CLA command can be combined
with the MQA to clear the AC then effect the
transfer.

MQ V AC = > AC
CLA

7601

CAM

7621

1,2

Clear accumulator. The AC is cleared during
sequence 1 , allowing this command to be
combined with the other EAE commands that
load the AC during sequence 2 (such as SCA
and MQA).
= > AC
Clear accumulator and multiplier quotient.

CAM= CLA LMQ.

B-7

Basic lOT Microinstructions

Mnemonic

Octal

Operation

6001

Turn interrupt on and enable the computer to respond to an interrupt
request. When this instruction is given, the computer executes the

Program Interrupt

ION

next instruction, then enables the interrupt.

The additional in-

struction allows exit from the interrupt subroutine before allowing

another interrupt to occur.

lOF

6002

Turn interrupt off; i.e.

disable the interrupt.

High Speed Perforated-Tape Reader and Control

RSF

6011

Skip if reader flag is a

RRB

6012

Read the content of the reader buffer and clear the reader flag.

(This instruction does not clear the AC.)

RFC

6014

VAC 4-11 => AC 4-11

Clear reader flag and reader buffer, fetch one character from tape
and load it into the reader buffer, and set the reader flag when

done.

High Speed Perforated-Tape Punch and Control
PSF

6021

Skip if punch flag is a

PCF

6022

Clear punch flag and punch buffer.

PPC

6024

Load the punch buffer from bits 4 through 1 1 of the AC and punch
(This instruction does not clear the punch flag or

the character.

punch buffer.)
AC 4-11 V PB = > PB
PLS

6026

Clear the punch flag, clear the punch buffer, load the punch buffer
from the content of bits 4 through 1 1 of the accumulator, punch the
when done.
character, and set the punch flag to
1

Teletype Keyboard/Reader

KSF

6031

Skip if keyboard flag is a

KCC

6032

Clear AC and clear keyboard flag.

KRS

6034

Read keyboard buffer static.

(This

a static command in that

neither the AC nor the keyboard flag is cleared.)
TTI V AC 4-11

KRB

6036

=> AC 4-11

Clear AC, clear keyboard flag, and read the content of the keyboard buffer into the content of AC 4-11.

Teletype Teleprinter/Punch

TSF

6041

Skip if teleprinter flag is a

TCF

6042

Clear teleprinter flag.

XPC

6044

Load the TTO from the content of AC 4-1 1 and print and/or punch
the character.

B-8

Basic lOT Microinstructions (Cont)

Mnemonic

Octal

Operation

Teletype Teleprinter/Punch (cont)

TLS

6046

Load the TTO from the content of AC 4-1

clear the teleprinter

flag, and print and/or punch the character.

Oscilloscope Display Type VC8/I and Precision CRT Display Type 30N

DCX

6051

Clear X-coordinate buffer.

DXL

6053

Clear and load X-coordinate buffer.
AC 2-11 = > YB

DIX

6054

Intensify the point defined by the content of the X- and Ycoordinate buffers.

DXS

6057

Executes the combined functions of DXL followed by DIX.

DCY

6061

Clear Y-coordinate buffer.

DYL

6063

Clear and load Y-coordinate buffer.
AC 2-11 => YB

DIY

6064

Intensify the point defined by the content of the X- and Y-

coordinote buffers.

DYS

6067

Executes the combined functions of DYL followed by DIY.

Oscilloscope D splay Type VC8/I

DSB

6075

Set minimum brightness.

DSB

6076

Set medium brightness.

DSB

6077

Set maximum brightness.

DSB

6074

Zero brightness.

Precision CRT C isplay Type SON
'

DLB

6074

Load brightness register (BR) from bits 9 through

AC 9-11 => BR
Light Pen Type 370

DSF

6071

Skip if display flag is a

DCF

6072

Clear the display flag.

Memory Parity Type MP8/I

SMP

6101

Skip if memory parity error flag = 0.

CMP

6104

Clear memory parity error flag.

Automatic Restart Typ e KP8/I
SPL

6102

Skip if power is low.

B-9

of the AC.

Basic lOT Microinstructions (Cont)

Mnemonic

Operation

Octal

Memory Extension Control Type MC8/I

CDF

62N1

Change to data field N. The data field register is loaded with the
selected field number (0 to 7). All subsequent memory requests for
operands are automatically switched to that data field until the
data field number is changed by a new CDF command.

CIF

62N2

Prepare to change to instruction field N. The instruction buffer
The next
is loaded with the selected field number (0 to 7).

JMP or JMS instruction causes the new field to be entered.
RDF

6214

Read data field into AC 6-8.

Bits 0-5 and 9-11 of the

AC are not

affected.
RIF

6224

RIB

6234

Same as RDF except reads the instruction field.
Read interrupt buffer.

The instruction field and data field stored

during an interrupt are read into AC 6-8 and 9-11 respectively.

RMF

6244

Restore memory field.

Used to exit from a program interrupt.

Data Communications Systems Type 680

TTINCR

6401

TTI

6402

The content of the line select register is incremented by one.
The line status word is read and sampled.

If the

line is active for

the fourth time, the line bit is shifted into the character assembly
word. If the line is active for a number of times less than four, the

count is incremented. If the line is not active, the active/inactive
is recorded.

status of the line

TTO

6404

The character in the AC is shifted right one position, zeros are
shifted into vacated positions, and the original content of ACl 1
transferred out of the computer on the Teletype line.

TTCL

6411

The line select register is cleared.

TTSL

6412

The line select register is loaded by an OR transfer from the content of AC5-1 1 , then the AC

TTRL

6414

cleared.

The content of the line select register is read into AC5-11 by an

OR transfer.
TTSKP

6421

Skip if clock

TTXON

6424

Clock 1
is

TTXOF

6422

flag is a

enabled to request a program interrupt and clock

flag

cleared.

Clock 1
flag

disabled from causing a program interrupt and clock

cleared.

Incremental Plotter and Control Type VP8/I

PLSF

6501

Skip if plotter flag is a

PLCF

6502

Clear plotter flag.

PLPU

6504

Plotter pen up.

Raise pen off of paper.

B-10

Basic lOT Microinstructions (Cont)

Mnemonic

Octal

Operation

Incremental Plotter and Control Type VP8/I (Cont)

Serial
*

PLPR

6511

Plotter pen right.

PLDU

6512

Plotter drum (paper) upward.

PLDD

6514

Plotter drum (paper) downward.

PLPL

6521

Plotter pen left.

PLUD

6522

Plotter drum (paper) upward.

PLPD

6524

Plotter pen down.

(Same as 6512.)

Lower pen on to paper.

Magnetic Drum System Type 251

DRCR

6603

Load the drum core location counter with the core memory location
in the accumulator.
Prepare to read one sector of information from the drum into the specified core location. Then
information

clear the AC.

DRCW

6605

Load the drum core location counter with the core memory location
Prepare to write one sector of information into the drum from the specified core location. Then
information in the accumulator.

clear the AC.

DRCF

6611

Clear completion flag and error flag.

DREF

6612

Clear the AC then load the condition of the parity error and data
timing error flip-flops of the drum control into accumulator bits
and 1 respectively, to allow programmed evaluation of an error
flag.

DRTS

6615

Load the drum address register with the track and sector address
Clear the completion and error flags,
and begin a transfer (reading or writing). Then clear the AC.
held in the accumulator.

DRSE

6621

Skip next instruction if the error flag is a

DRSC

6622

Skip next instruction if the completion flag is a
is

DRCN

6624

(no error).
1

(sector transfer

complete).

Clear error flag and completion flag, then initiate transfer of next
sector.

Serial

Magnetic Drum System Type RM08

DRCR

6603

Load the drum core location counter with the core memory location
Prepare to read one sector of information from the drum into the specified core location. Then
information in the accumulator.

clear the AC.

DRCW

6605

Load the drum core location counter with the core memory location
Prepare to write one sector of inin the accumulator.

information

formation into the drum from the specified core location.
clear the AC.

DRCF

6611

Clear completion flag and error flag.

B-n

Then

Basic lOT Microinstructions (Cont)

Mnemonic
Serial

Octal

Operation

Magnetic Drum System Type RM08 (Cont)

DRES

6612

Clear the AC then load the condition of the parity error and data
timing error flip-flops of the drum control into accumulator bits
and 1 respectively to allow programmed evaluation of an error flag.
The contents of the drum sector counter are transferred into bits AC
6-11.

DRTS

6615

Load the drum address register with the track and sector address
Clear the completion and error flags, and
begin a transfer (reading or writing). Then clear the AC.
held in the accumulator.

DRSE

6621

Skip next instruction

the error flag

DRSC

6622

Skip next instruction

the completion flag is a

DRFS

6624

(no error).
1

(sector transfer

complete).

Loads the drum field register with the contents of the accumulator
bits 10 and

1 1

Loads the sector number register with the contents

of the accumulator bits 0-5, to specify the number of sectors to be
transferred.

Loads the three most significant bits of the drum core

location register (DCLo-2) with the contents of the AC bits 5, 7,
8 to specify the core memory block to be used during the drum
transfer

Random Access Disk File (Type DF32)

DCMA

6601

Clears memory address register, parity error and completion flags.
This instruction clears the disk memory request flag and interrupt
flags.

DMAR

6603

The contents of the AC are loaded into the disk memory address
register and the

AC is cleared.

Begin to read information from the
Clears parity error and com-

disk into the specified core location.

pletion flags.

DMAW

6605

Clears interrupt flags.

The contents of the AC are loaded into the disk memory address
is cleared.
Begin to write information into the
disk from the specified core location. Clears parity error and comregister and the AC

pletion flags.

DCEA

6611

Clears the disk extended address and memory address extension
register.

DSAC

6612

Skips next instruction if address confirmed flag

(AC is

cleared.)

DEAL

6615

The disk extended address extension registers are cleared and
loaded with the track data held in the AC.

DEAC

6616

Clear the AC then loads the contents of the disk extended address
register into the AC to allow program evaluation. Skip next instruction if address confirmed flag is a 1

B-12

Basic lOT Microinstructions (Cont)

Mnemonic

Octal

Operation

Random Access Disk File (Type DF32)(Cont)
DFSE

6621

Skips next instruction

lock switch flag

DFSC

6622

parity error, data request late, or write-

a zero.

Indicates no errors.

Skip next instruction if the completion flag is a

1 .

Indicates data

transfer is complete.

DMAC

6626

Clear the AC then loads contents of disk memory address register
into the

AC to allow program evaluation.

AutomaHc Line Printer and Control Type 645
LSE

6651

Skip if line printer error flag is a

LCB

6652

Clear both sections of the printing buffer.

LLB

6654

Load printing buffer from the content of AC 6-11 and clear the AC.

LSD

6661

Skip if the printer done flag is a

LCF

6662

Clear line printer done and error flogs.

LPR

6664

Clear the format register, load the format register from the content
of AC 9-1 1 , print the line contained in the section of the printer

buffer loaded last, clear the AC, and advance the paper in ac-

cordance with the selected channel of the format tape if the conIf the content of AC 8 = 0, the line is printed
and paper advance is inhibited.
tent of AC 8 =

DECtape Transport Type TU55 and DECtape Control Type TCOl

DTRA

6761

The content of status register A is read into ACO-9 by an OR
transfer. The bit assignments are:
ACO-2 = Transport unit select number
AC3-4 = Motion
AC5 = Mode

AC6-8 = Function

AC9

= Enable/disable DECtape control flag

DTCA

6762

Clear status register A.

DTXA

6764

Status register A is loaded by an exclusive OR transfer from the
content of the AC, and AClOand ACll are sampled. If ACIO = 0,
the error flags are cleared. If ACll = 0, the DECtape control flag
is

All flags undisturbed.

cleared.

DTSF

6771

Skip

DTRB

6772

The content of status register B is read into the AC by an OR transfer. The bit assignments are;
= Error flag
ACO

ACl

AC2
ACS

error flag

= Mark track error
= End of tape
= Select error

B-13

DECtape control flag is a

Basic lOT MicroinstrucHons (Cont)

Mnemonic

Operation

Octal

DECtape Transport Type TU55 and DECtape Control Type TCOl (Cont)

AC4
ACS

= Parity error

AC6-8

= Memory field

= Timing error

AC9-10= Unused
= DECtape flag
AC 11
DTLB

6774

The memory field portion of status register B is loaded from the
content of AC6-8.

Card Reader and Control Type CR8/I

RCSF

6631

Skip if card reader data ready flag

RCRA

6632

The alphanumeric code for the column is read into AC6-11

and

the data ready flag is cleared.

RCRB

6634

The binary data in a card column is transferred into ACO-11
the data ready flag

and

cleared.

RCSP

6671

Skip if card reader card done flag

RCSE

6672

Clear the card done flag, select the card reader and start card
motion towards the read station, and skip if the reader-not-ready
flag

RCRD

6674

Clear card done flag.

Automatic Magnetic Tape Control Type TC58

MTSF

6701

The status of the error
(MTF) are sampled. If either
the content of the PC is incremented by one

Skip on error flag or magnetic tape flag.
flag (EF) and the magnetic tape flag
or both are set to

to skip the next sequential instruction.

MTCR

6711

Skip on tape control ready (TCR). If the tape control is ready to
receive a command, the PC is incremented by one to skip the next
sequential instruction.

MTTR

6721

Skip on tape transport ready (TTR).
is

MTAF

6712

6724

The next sequential instruction

skipped if the tape transport is ready.

Clear the status and command registers, and the EF and MTF if tape
control ready. If tape control not ready, clears MTF and EF flags only.
Inclusively OR the contents of the command register into bits 0-11
of the bits 0-11 of the AC.

MTCM

6714

Inclusively OR the contents of AC bits 0-5, 9-11 into the command
register;

MTLC

6716

_ _

6704

JAM transfer bits 6, 7, 8 (command function).

Load the contents of AC bits 0-1

into the command register.

Inclusively OR the contents of the status register into bits 0-1
of the AC

B-14

Basic lOT Microinstructions (Cont)

Mnemonic

Octal

Operation

Automatic Magnetic Tope Control Type TC58 (Cont)

MTRS

6706

MTGO

6722

Read the contents of the status register into bits 0-11 of the AC.
Set "go" bit to execute command in the command register if com-

mand is legal
6702

Clear the accumulator.

General Purpose Converter and Multiplexer
Control Type AFOIA

ADSF

6531

Skip if A/D converter flag is a

ADVC

6532

Clear A/D converter flag and convert input voltage to a digital

number, flag will set to 1 at end of conversion.
converted number determined by switch setting,

ADRB

6534

Read A/D converter buffer into AC,

ADCC

6541

Clear multiplexer channel address register.

ADSC

6542

Number of bits in
11 bits maximum.

left justified,

Set up multiplexer channel as per AC 6-11 .

and clear flag.

Maximum of 64 single

ended or 32 differential input channels.

ADIC

6544

Index multiplexer channel address (present address + 1). Upon
reaching address limit, increment will cause channel GO to be
selected.

Guarded Scanning Digital Voltmeter Type AF04A

VSEL

6542

The contents of the accumulator ore transferred to the AF04A control register.

VCNV

6541

The contents of the accumulator are transferred to the AF04A channel address register.

Analog signal on selected channel is auto-

maticdlly digitized.

VINX

6544

The last channel address is incremented by one and the analog signal on the selected channel is automatically digitized.

VSDR

6531

Skip if data ready flag is o

VRD

6532

Selected byte of voltmeter is transferred to the accumulator and the
data ready flag is cleared.

VBA

6534

Byte Advance command requests next 12 bits, data ready flag is set.

VSCC

6571

Sample Current Channel when required to digitize analog signal on
current channel repeatedly.

B-15

APPENDIX C

PERFORATED TAPE LOADER
SEQUENCE
C. 1

READIN MODE LOADER

A perforated tape to be read by the RIM loader
must be in RIM format:

The readin mode (RIM) loader is a minimum

Tape Channel

length, basic, perforated -tape reader program
for the ASR33.

87654 S32
10
0.000

initially stored in memory

by manual use of the operator console keys and

The loader is stored permanently in
18 locations of page 37.

switches.

forated-tape reader). Because a tape in RIM
format is, in effect, twice as long as it need be,

00
00
00

(Note that PDP-8 diagnostic program tapes are

RIM format.)

Absolute address to
contain next 4 digits

X2
X4

Content of previous
4 -digit address

A2
A4

Address

X2
X4

Content

A3
XI

Leader-trailer code

A2
A4

suggested that the RIM loader be used only

to read the binary loader when using the ASR33.
in

00
00
00

The RIM loader can only be used in con|unction
with the ASR33 reader (not the high-speed per-

it is

Format

(Etc.)

The complete PDP-B/l RIM loader (SA = 7756)
is

10000.00

as follows:

Absolute
Address

Octal
Content

7756,
7757,
7760,
7761,
7762,
7763,
7764
7765,
7766,
7767,
7770,
777},
7772,

6032
6031

7772,,

777A,
7775,
7776,
7777,

Tag

BEG,

5357
6036
7106
7006
7510
5357
7006

Instruction I Z

Comments

KCC

/CLEAR AC AND FLAG

KSF

/SKIP IF FLAG =

JMP

-1

KRB
CLL RTL

/LOOKING FOR CHARACTER
/READ BUFFER

/CHANNEL 8 IN ACO
/CHECKING FOR LEADER
JMP BEG+1 /FOUND LEADER
RTL
/OK, CHANNEL 7 IN LINK
RTL

SPA

6031

KSF

5367
6034
7420
3776
3376
5356

JMP

-1

/READ, DO NOT CLEAR
/CHECKING FOR ADDRESS
OCA I TEMP /STORE CONTENT
DCA TEMP /STORE ADDRESS
JMP BEG
/NEXT WORD
KRS

SNL

TEMP,

5XXX

Leader-trailer code

JMP X
C-1

AEMP STORAGE
/JMP START OF BIN LOADER

C.2 BINARY LOADER

Placing the RIM loader in core memory by way
of the operator console keys and switches is

The binary loader (BIN) is used to read machine
language tapes (in binary format) produced by the
program assembly language (PAL). A tape in
binary format is about one half the length of the
comparable RIM format tape. It can, therefore,.
,be read about twice as fast as a RIM tape and

accomplished as follows.
1

Set the starting address 7756 in the switch

Press

LOAD ADDRESS key.

Set the first instruction (6032) in the SR.

Press the

Set the next instruction (6031) in the SR.

reason, the more desirable format to
use with the 10 cps ASR33 reader or the Type

Press DEPOSIT key.

PR8/I High Speed Perforated -Tape Reader.

is, for this

DEPOSIT key.

Repeat steps 5 and 6 until all 16 instructions
The format of a binary tape is as follows.
have been deposited

To load a tape in RIM format, place the tape in
the reader, set the SR to the starting address
7756 of the RIM loader (not of the program being

LEADER: about 2 ft of leader -trailer codes.

read), press the Load Address key, press the Start
key, and start the teletype reader.

machine language program in easy-to-read
binary (or octal) form. The section of tape may

Refer to Digital Program Library document Digital-

contain characters representing instructions
(channels 8 and 7 not punched) or origin re-

8-1 -U for additional information on the Readin

settings (channel 8 not punched, channel 7

Mode Loader program

punched) and is concluded by 2 characters

BODY:

characters representing the absolute,

Example of the format of a binary tape

Tape Ch<annel

87654 S32

Memory
1

10000 .000
1000 .010
00111 .010
00000 .000
0000 .010
00111 .111
000 11 .010
00111 .110
00111 .100
00000 .010
1000 .010
00111 .111
00000 .000
00101 .011
0000 .000
00000 .111
10000 .000

Location

Content

Comments
leader-trailer code

0200

CLA

0201

TAD 277

0202

DCA 276

0203

HLT

origin setting

0277
0277

origin setting

0053

1007

sum check
leader-trailer code

C-2

Operation of the BIN loader in no way depends
upon or uses the RIM loader. To load a tape in
BIN format place the tape in the reader, set the
SR to 1777 (the starting address of the BIN loader),
press the Load Address key, set SR switch
up

(channels 8 and 7 not punched) that represent
a checksum for the entire section.

TRAILER: same as leader.

for loading via the teletype unit or down for

After a BIN tape has been read in, one of the

loading via the high speed reader, then press

two following conditions exists.

the Start key, and start the tape reader.

No checksum error: halt with AC Checksum error halt with AC = (computed
:

checksum) - (tape checksum)

Refer to Digital Program Library document Digital

8-2-U-RIM for additional Information on the
Binary Loader program.

C-3

APPENDIX D

PROGRAMS
The following programs, which were produced
for or are usable with the PDP-8/I are available from the Digital Program Library.

Program Number

Function

DEC-08-FMDA

Program Number

Function

DEC-08-FMEA

Definitions for 338

DEC-08-FMFC
DEC-08-FMGB
DEC-08-FMHA

Double Precision Signed
Mult
Double Precison Signed
Div
Double Precision Sine
Double Precision Cosine

DEC-08-AEAA
DEC-08-AFCO
DEC-08-AJAE

Pal

III

4K FORTRAN

FOCAL and INIT (4K,

Package

INIT)

DEC-08-AJ1E

FOCAL UTILITY OVERLAYS (4 word, 8K)

DEC-08-AJ2E

DEC-08-AJ3E

DEC-08-FM1A
DEC-08-FMJA

FOCAL GRAPHIC OVER-

Logical Subroutines

Arithmetic Shift Subroutines

LAYS

DEC-08-FMKA

Logical Shift Subroutines

FOCAL 3D SURFACE

DEC-08-A2B1
DEC-08-A2D2

8K FORTRAN
8K FORTRAN SABR

PLOT Demonstration
Program

DEC-08-AJ5E

FOCAL EXTENDED
FUNCTIONS
FOCAL DF32 Option

DEC-08-AJ6E

FOCAL RF08 Option

DEC-08-AJ4E

Four Word Floating Point

Assembler

DEC-08-A2C3

FORTRAN 8K-32K Linking

DEC-08-A2B4

8K FORTRAN Library Sub-

Loader

MULTI-USER OVERLAYS

routines

DEC-08-A2B5

MULTI-USER OVERLAYS

of 2

8K FORTRAN Library Subroutines 2 of 2

8K FORTRAN DECtape l/O

FOCAL PT08 Option
FOUR USER OVERLAYS
FOCAL DC02 Option
FOUR USER OVERLAYS

DEC-08-A2B6

DEC-08-A2C7

FORTRAN 8K-32K Linking

DEC-08-ASB1

Pal

DEC-08-A2A8

8K FORTRAN SABR - DISK

DEC-08-CDDB
DEC-08-CMAB

DDT-8

DEC-08-COCO

ODT-8

DEC-08-ESAB
DEC-08-EUFA
DEC-08-FFAC

Symbolic Editor
DECtape Formatter
Program Library MATH

DEC-08-AJ7E
DEC-08-AJ8E

III

MACRO-8

ROUTINES

DEC-08-FMAA

Single Precision Square

DEC-08-FMBA

Single Precision Signed

Root

Mult

DEC-08-FMCB

Subroutines

Loader (Disk)

I/O

DEC-08-LBAA
DEC-08-LHAA
DEC-08-LRAA
DEC-08-LUAA

DEC-08-PMPO
DEC-08-PMP1

DEC-08-PMP2
DEC-08-PMP3

Single Precision Signed

Div

D-1

Binary Loader

Help Loader
RIM Loader

TCOl Bootstrap Loader
Read-In-Mode (RIM) Punch
RIM Punch Low Memory

ASR-33
RIM Punch High Memory
ASR-33
RIM Punch High Memory
ASR-75

Program Number

DEC-08-PMP4

Program Number

Function

RIM Punch Low Memory
ASR-75
TCOl DECtape SubrouHnes

DEC-D8-PDZE

DEC-D8-ASAC

DEC-D8-AFA4

FORTRAN-D Operating

DEC-08-US1B

(Paper tape source only)
Multianalyzer
Single Parameter Height
Analysis AC
Dual Parameter Height
Analysis AC
Multichannel Analyzer
Program Group
Multichannel Analyzer

DEC-08-US2B

Program SING. 81
Multichannel Analyzer

DEC-D8-AFA5
DEC-D8-AFA6

FORTRAN-D Symbol Print
FORTRAN-D Debugging

DEC-08-US3B

Multichannel Analyzer

DEC-08-SUCO
DEC-08-USA0
DEC-OB-USA
1

DEC-08-USA2

DEC-08-USYA

DISK System PIP for RF08
Option Only

DEC-D8-ESAB

DISK Editor
DISK System Assembler

PAL-D

DEC-D8-AFAI

FORTRAN-D (4K FORTRAN) Compiler Loader

DEC-D8-AFA2
DEC-D8-AFA3

FORTRAN-D Compiler
FORTRAN-D Operating
System Loader

System

Program-DUAL8I

Program (DIAGnose)

Program-SING.SL

DEC-D8-CDE1
DEC-D8-CDE2

Disk DDT System

DEC-08-US4A

Multichannel Analyzer

DEC-D8-RWDA

DISK System Restore

Program-PKLOCS

Digital-8-21-F

Signed Multiply Single

DEC-08-YIRA

Variable Stroke Character
(Double Size) Generator

Digital -8-22-F

DEC-08-YISB

DEC-08-YPPA
DEC-08-YPTA
DEC-08-YXYA

Digital-8-23-F

Double Precision EAE

Octal Memory Dump

Digital-8-25-F

Floating Point EAE

DECtape Copy Routine

Digital-8-15-S
Digital-8-15S
DIgital-8-35-S-A

Digital -8-3-U

Oceanographic Analizer
Master Tape Duplicator
TTY 680 5-BIt Character
Assembly
TTY 680 5 -Bit Character
Assembly
DECtape Loader 552

Digital-8-lO-U

BCD to Binary Conversion

Binary Punch (Binary

DEC-08-YQYA
DEC-08-ZJ1B
DEC-08-ZJ2B
DEC-08-ZJ3B
DEC-08-ZJ4B
DEC-08-ZJ5B

EDGRIN
EDGRIN Translator
EDGRIN Link Generator
EDGRIN Cursor Mosaic
EDGRIN Disk Editor

Digital-8-35-S-B

Subroutines

Digital-8-ll-U

DEC-D8-PDAD

Double Precision BCD to
Binary Converter

DIgital-8-12-U
Digital-8-14-U
Digital-8-15-U

Translator

DEC-D8-SBAF

Signed Divide Single precision EAE

(Single Size) Generator

Speed or Teletype Punch)
Binary Punch -Teletype
(ASR-33)
Binary Punch-High Speed
(ASR-75)
Floating Point Package

DEC-08-YX2A

Precision EAE

Variable Stroke Character

Code Dump for High

DEC-08-YX1A

Disk DDT Driver

Incremental Plotter Routine
Binary to BCD Conversion

Binary to BCD Conversion
(4 Digit)

DISK System Builder,
DF32/RF08
DISK System PIP for
DF32 Option Only

Digital-8-17-U

EAE Instruction Set
Simulator

Digital-8-18-U

D-2

Alphanumeric Message
Typeout

Program Number

Function

D 'gital -8-19--U

Teletype Output Sub-

Maindec-08-D2GE High Speed Reader and

routines

D gif-al -8-20--U
D gital -8-21-U

Character String Typeout
Symbolic Tape Format
Generator
Signed Decimal Print,

Punch Test
Maindec-08- D20A CR03 Card Reader Test
Maindec-08- D2PE Teletype Test Part 1
Maindec-08- D2QD Teletype Test Part 2
Maindec-08- •D3BC TCOl Basic Exerciser
Maindec-08- D3EB TCOl Extended Memory

D gital -8-23--U

Single Precision

D gital -8-24-U
D gital -8-25-U
D gital -8-28-u

Digital-8-29-U

Digital-8-33-U
DigItal-8-34-U

Maindec-828

Unsigned Decimal Print,
Double Precision
Signed Decimal Print,
Double Precision
Single Precision Declmalto-Binary Conversion and
Input ASR-33, Signed or
Unsigned
Double Precision Decimalto-Binary Conversion and
Input ASR-33, Signed or
Unsigned
5/8 TOG (552)
DECEX for 552
LT08/PT08 Teleprinter
Test

Maindec-08-DOUA Family-of-8 Random Add
Rotate Test

Mainclec-08-D02B
Mainclec-08-D04B

Instruction Test 2B

Random JMP Test
Maindec-08-D05B Random JMP-JMS Test
Maindec-08-D07B Random ISZ Test
Maindec-08-DlAC Memory Power ON/OFF

Test

Maindec-08- D3RA TCOl DECTREX
Maindec-08- D4^0 Basic Memory Parity
Checkerboard

Maindec-08-D4BA Extended Memory Parity
Checkerboard

Maindec-08-D4CB Incremental Compatibility
Test

Maindec-08-D4EB

Incremental Instruction
Test

Maindec-08-D4FA Incremental Random
Exerciser

Maindec-08- D5BB DF32 Diskless, Mini Test
Maindec-08- D5CC DF32 Disk Data Test
Maindec-08- D5DB DF32 Multi Disk Test
Maindec-08- D5EB RF08 Disk Data
Maindec-08- D5FA Multi Disk
Maindec-08- D6GC A to D Calibration Test
Maindec-08- D6HA AF04A Diagnostic and

Demo

Test

Maindec-08-DlBO
Maindec-08-DlEB

Exerciser

Maindec-08-D3FC Incremental Tape Delay

Memory Address Test
Extended Memory Checker-

Maindec-08- D6JD AD08A/B Diagnostic
Maindec-08- D6KB 34DAC8I Display Test
Maindec-08- D6MA VS38 Diagnostic
Maindec-08- D6QA Low Level Multiplexer

AM03/AM08

board Test

Maindec-08- D6RA AF04 Diagnostic Test
Maindec-08- D6TA AA05A/AA07A Diagnostic

Maindec-08-DlGB Extended Memory Control
Test

Maindec-08-DlHA Extended Memory Address

Exerciser

Test

Maindec-08-DlKA KR01/KP8I Power Fail
Test

Maindec-08-DlLO Basic Checkerboard Test
Maindec-08-D2AA Family-of-8 Teletype Test
MaIndec-08-D2FC High Speed Reader Test

Maindec-08- D8EB DPOIA lOT and Data Test
Maindec-08- •D8FA lOT & Data Test for 637
Maindec-08- D8HB DPOIA Test 6301-6354
Maindec-08- D8LB DPOIA Test 6501-6564
Maindec-08- D8MB DPOIA Test 6701-6764
Maindec-08- D8NA VA38 Character Generator
Test

D-3

Program Name

Function

Maindec-08-D8PA PT08 Test for Dotophone
Maindec-08-D8QA 689 ADF On-line
Diagnostic

Maindec-08-D8RA 689 Control & Data Test
Maindec-08-D8SB DM01 Exerciser
Maindec-08-D8WA DC02 Diagnostic
Maindec-08-D8XA XOR Buffer for DPOIA
Maindec-08-D9AC TC58 Data Reliability
Test 7 Track

Maindec-08-D9BA TC58 Drive Function
Timer

Maindec-08-D9CB TC58 Random Exerciser
Maindec-08-D9DD TC58 Instruction Test 1
Maindec-08-D9EC TC58 Instruction Test 2
Maindec-08-D9FC TC58 Data Reliability
Test 9 Track

Maindec-08-D9GA TC58 Data Reliability
Test 9 Track

Maindec-8I-F8VA

6801 8-Bit Character
Subroutines

Maindec-8I-D0AA
Maindec-8I-D01C
Maindec-8I-D02B
Maindec-8I-D0BA
Maindec-8I-D4CA
Maindec-8I-D5BB
Maindec-8I-D6AC
Maindec-8I-D6CE
Maindec-8I-D8AD

EAE Test Part 1
Instruction Test

Instruction Test 2

EAE Instruction Test
Memory Parity lOT Test
DF32 Logic, Mini Test

AX08 Diagnostic

KV 8/l Display Diagnostic
KW8I Real Time Clock
Test

Maindec-8I-D8AC DC08T1-DC08 Off Line
Diagnostic

Maindec-8I-D8CA 689 ACT 1-689 AG Control

and Data Test

Maindec-8I-D8DA 689 AFT-2-689 AG On
Line Exerciser

D-4

APPENDIX E
TELETYPE CODES

and 377 are sufficient for Teletype operation.
The Model ASR33setcan detect all characters,
but does not interrupt all of the codes that it can
generate as commands.

The 8-bit code used by the Model ASR33 Teletype unit is the American Standard Code for Information Interchange (ASCII) modified. To
convert the ASCII code to teletype code, add
200 octal (ASCII + 200g = Teletype). This code
punched in the paper tape reads in reverse of
the normal octal form used in the PDP-8/1 since
bits are numbered from right to left, from 1
through 8, with bit 1 having the most significance. Therefore, perforated tape is read.
The Model ASR33 set can generate all assigned
codes except 340 through 374 and 376. Generally, codes 207, 212, 215, 240 through 377,

AC04

AC05

The standard number of characters printed per
line is 72. The sequnece for proceeding to the
next line is a carriage return followed by aline
feed (as opposed to a line feed fol lowed by a
carriage return). Key or key combinations are
required to produce octal codes from 200 through
337, 375, and 377 are indicated in Table E-1
with the associated ASCII character.

AC06

AC07

Feed
Hole

Tape is loaded into the reader:

AC09

AC08

ACIO

AC 11

Most-Significant

Least-Significant

Octal Bit

Feed
Hole

Tape
Motion
Table E-1
Teletype Code (Numerical Order)
Octal

Character

ASCII

Code

Name

Character

220

Null/Idle

NULL

201

Start of Message

Teletype
Character

—
—

Key or Key
Combinations

CTRL @

202

End of Address

203

End of Message

SOM
EOA
EOM

204

End of Transmission

EOT

___

CTRL D

___

CTRL E

___

CTRL A

CTRLB

CTRLC

205

Who Are You

WRU

206

Are You

CTRL F

207

Audible Signal

BELL

CTRL G

E-1

Table E-1 (Cont)
Teletype Code (Numerical Order)
Octal

Character

Code

Nome

210

Format Effector

CTRL H

211

Horizontal Tabulation

HTAB

212

Line Feed

—

CTRL

213

Vertical Tabulation

VTAB

__.

CTRL K

214

Form Feed

215

Carriage Return

216

Shift Out

—

Shift In

___

Device Control Reversed
Data Line Escape

DCO

CTRLP

DCl

CTRLQ

217
220

ASCII
Character

Teletype

Key or Key

Character

Combinations

CTRL J

___

CTRL L

CTRLM
CTRL N

CTRLO

for

221

Device Control

222

Device Control (TAPE)

DC2

—

223

Device Control OFF

DC3

___

CTRL S

224

Device Control (TAPE)

DC4

___

CTRLT

225

Error

ERR

226

Synchronous Idle

SYNC

227

Logical End of Media

LEM

—
—
—

___

CTRLX

___

CTRL Y

230

Separator, Information

231

Separator, Data Delimiters

232

Separator, Words

233

Separator, Groups

234

Separator, Records

235

Separator, Files

CTRLR

CTRLU
CTRL V
CTRL W

SHIFT CTRL K

—
—
—
—

SHIFT CTRL N

CTRL Z

SHIFT CTRL L
SHIFT CTRL M

236

Separator, Misc.

___

237

Separator, Misc.

___

SHIFT CTRL O

240

Space

Space Bar

241

Exclamation Point

SHIFT

242

Quotation Marks

243

Number Sign

SHIFT #

244

Dollar Sign

SHIFT $

245

Percent Sign

SHIFT

246

Ampersand

SHIFT &

247

Apostrophe

SHIFT

250

Parenthesis, Beginning

(

SHIFT (

251

Parenthesis, Ending

)

SHIFT )

252

Asterisk

E-2

%
'

SHIFT *

Table E-1 (Cont)
Teletype Code (Numerical Order)
Octal

Character

ASCII

Code

Name

Character

253

Plus Sign

254

Comma

255

Hyphen

256

Period

257

Virgule

260

Numeral

261

Numeral

Teletype
Character

Key or Key
Combinations

SHIFT +

262

Numeral 2

263

Numeral 3

264

Numeral 4

265

Numeral 5

266

Numeral 6

267

Numeral 7

270

Numeral 8

271

Numeral 9

272

Colon

273

Semicolon

;

274

Less Than

SHIFT <

275

Equals

SHIFT =

276

Greater Than

SHIFT >

277

Interrogation Point

SHIFT ?

300

SHIFT

301

Letter A

302

Letter B

303

Letter C

304

Letter D

305

Letter E

306

Letter F

307

Letter

310

Letter H

311

Letter I

312

Letter J

313

Letter K

314

Letter L

315

Letter

E-3

Table E-1 (Cont)
Teletype Code (Numerical Order)
Octal

Character

Code

Name

ASCII
Character

Teletype
Character

Key or Key
Combinations

316

Letter

317

Letter

320

Letter P

321

Letter

322

Letter R

323

Letter S

324

Letter T

325

Letter U

326

Letter V

327

Letter

330

Letter X

331

Letter Y

332

Letter Z

333

Bracket, Left

[

SHIFT K

334

Reverse Virgule

SHIFT L

335

Bracket, Right

]

SHIFT M

336

Up Arrow (exponentiation)

337

Left Arrow

SHIFT

—

ALT MODE

___

RUB OUT

340 through 374 are not available
375

Unassigned Control

376

Not Available

377

Delete/Idle/Rub Out

DEL

SHIFT

Table E-2
Teletype Code (Character Order)

Character

8-Bit Co de
(in

Character

octc 1)

8-Bit Code
(in octal)

301

302

303

243

304

244

305

245

306

246

307

247

310

(

E-4

241

242

250

Table E-2 (Cont)
Teletype Code (Character Order)

Character
I

8-Bit Code

Character

8-Bit Code
(in octal)

(in octal)

311

)

251

312

252

313

253

314

254

315

316

317

320

321

273

322

274

323

275

324

276

325

277

326

300

327

[

333

330

334

331

]

335

332

336

255
256
257

272

337

260
1

261

Leader/Trailer

200

262

Line-Feed

212

263

Carriage-Return

215

264

Space

240

265

Rub -out

377

266

Blank

000

267

act-mode

375

270

escape

233

271

E-5

Table E-3

Model 33 ASIVKSR Teletype Code (ASCII) In Binary Form
1 = HOLE PUNCHED = MARK
^MOST SIGNIFICANT BIT
- NO HOLE PUNCHED = SPACE

/^ LEAST

SPACE

SIGNIFICANT BIT \

7654S32

NULL/IDLE

START OF MESSAGE

END OF ADDRESS
END OF MESSAGE

END OF TRANSMISSION

WHO ARE YOU

ARE YOU

BELL

FORMAT EFFECTOR
HORIZONTAL TAB
LINE FEED

VERTICAL TAB

FORM FEED

CARRIAGE RETURN

SHIFT OUT

SHIFT IN

DCO
READER ON
TAPE (AUX ON)

READER OFF

(AUX OFF)

ERROR

SYNCHRONOUS IDLE

LOGICAL END OF MEDIA

SO
S 1

S2
S3

RUB OUT

S 7

SAM^

SAME
SAME

SAME

E-6

Table E-4
Card Reader Code
Card Code

Card Code
Internal

Zone Num.

—

8-3

01 0000
11 1011

12
12
12
12

8-4

11 1100

8-5

11 1101

8-6

1110

Blank

11
11

]

)

8-7

nil

-*-

1 1

0000

10 1011
10 1100
10 1101
10 1110
10 nil
10 0000
01 0001
01 1011
01 1100
01 1101
01 1110
01 nil
00 1011

8-3

8-4

8-5

8-6

8-7

8-3

8-4
8-5

8-6
8-7

—
12
12
12
12

Internal

Zone Num.

Character

8-3
8-4
8-5

8-6
8-7

2
3

00 1100
00 1101
00 1110
00 1 1 1
11 1010
11 0001
11 00 lO
11 0011
11 0100
11 0101

100101
100110
100111

010101

(

01 Olio
01 0111
01 1000
01 1001

8-2

—

8
9

—

(•"

--,

A
B
C
D

12
12

110110

11 0111

12.

8
9

1000
1001

10 1010
10 0001
10 0010
10 0011
10 0100

Character

10 1000
10 1001
01 1010
01 0010
01 0011
01 0100

12
12

Code

All

E-7

4
5

6
7

8
.9

other codes

00 1010
00 0001
00 0010
00 0011
00 0100
00 0101
00 0110
00 0111
00 1000
00 1001
00 0000

K
L

M
N
P

Q
R
S

U
V

w
X
Y
Z
1

2
3

4
5

6
7

8
9
.4-

Table E-5

AutomaHc Line Prini-er Code
Character
(ASCII)

Character
(ASCII)

6-Bit Code
(in octal)

40
41

C
D

5
6
7

(

42
43
44
45
46
47
50

)

!
tl

%
&
'

52
53

54
55
56

N
O

22
23

24
25
26
27
30

64
65
66
67
70

w
X
Y
z

3
5
6

[

32
33

]

36
37

E-8

57
60
61

62
63

72
73
74
75
76
TJ

APPENDIX F

MATHEMATICAL DATA
Scales of Notation

2^ IN Decimal
0.001
0.002
0.003
0.004
0.005
0.006
0.007
0.008
0.009

1.00069 33874 62581
1.00138 72557 11335
1.00208 16050 79633
1.00277 64359 01078
1.00347 17485 09503
1.00416 75432 38973
1.00486 38204 23785
1.00556 05803 98468
1.00625 78234 97782

0.01

1.00695 55500 56719
1.01395 94797 90029
1.02101 21257 07193
1.02811 38266 56067
1.03526 49238 41377
1.04246 57608 41121
1.04971 66836 23067
1.05701 80405 61380
1.06437 01824 53360

0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09

1.07177 34625 36293
1.14869 83549 97035
1.23114 44133 44916
1.31950 79107 72894
1.41421 35623 73095
1.51571 65665 1C398
1.62450 47927 12471
1.74110 11265 92248
1.86606 59830 73615

0,1

0.2
0.3
0.4
0.5
0.6
0.7

0.8
0.9

10+" IN Octal
10"

101

144
750
23 420

303 240
3 641 100
46 113 200
575 360 400
7 345 545 000

4
5

6
7

8
9

10"

1.000 000
0.063 146
0.005 075
0.000 406
0.000 032

000 000 000 000 00
314 631 463 146 31
341 217 270 243 66
111 564 570 651 77
155 613 530 704 15

0.000 002
0.000 000
0.000 000
0.000 000
0.000 000

476 132
206 157
015 327
001 257
000 104

610 706 64
364 055 37
745 152 75
143 561 06
560 276 41

12
13
14

0.000 000
0.000 000
0.000 000
0.000 000
0.000 000

34 327 724 461 500 000
434 157 115 760 200 000
432 127 413 542 400 000
405 553 164 731 000 000

15
16
17
18

0.000 000 000 000
0.000 000 000 000
0.000 000 000 000
0.000 000 000 000

n log^Q 2, n log 2 10 IN
n logio 2
0.30102
0.60205
0.90308
1.20411
1.50514

3.32192
6.64385
9.96578
13.28771
16.60964

80949
61898
42847
23795
04744

10
11

000 006 676 337 66
000 000 537 657 77
000 000 043 136 32
000 000 003 411 35
000 000 000 264 11

6
7

8
9
10

n logio 2

n log2 10

1.80617 99740
2.10720 99696
2.40823 99653

19.93156 85693
23.25349 66642
26.57542 47591
29.89735 28540
33.21928 09489

2.70926 99610
3.01029 99566

Addition and Multiplication Tables
Addition

Multiplication

Binary Scale

0+1 =

+
1
1

44-

0X0 =

=
= 1
= 10

0X1=1X0=0
=
1X1

Octal Scale
01

Mathematical Constants in Octal Scale
IT

3.11037

552421,

2.55760

521305.

IT-'

0.24276

301556,

e-i

0.27426

530661,

V^ =

1.61337

611067,

Ve =

1.51411

2307041

1.11206

404435,

logio

e= 0.33626

754251,

logjTT

1.51544

163223,

logie= 1.34252

166245,

V'io =

3.12305

407267,

logi 10

3.24464

F-1

741136,

000 022 01
000 001 63
000 000 14
000 000 01

Decimal

n logj 10

99957
99913
99870
99827
99783

10-"

112 402 762 000
1 351 035 564 000
16 432 451 210 000
221 411 634 520 000
2 657 142 036 440 000

y =

0.44742 147707,

In 7

0.43127 233602,

logi 7

- ,0.62573

030645,

V? =

1.32404

746320,

In 2

0.54271

027760,

2.23273

067355,

Powers of Two
-n

0.5

4
8
16

0.25

0.125
0.062 5
0.031 25
0.015 625
0.007 812 5
0.003 906 25
0.001 953 125
0.000 976 562 5
0.000 488 281 25
0.000 244 140 625
0.000 122 070 312 5
0.000 061 035 156 25
0.000 030 517 578 125
0.000 015 258 789 062 5
0.000 007 629 394 531 25
0.000 003 814 697 265 625
0,000 001 907 348 632 812 5
0.000 000 953 674 316 406 25
0.000 000 476 837 158 203 125
0.000 000 238 418 579 101 562
0.000 000 119 209 289 550 781
0.000 000 059 604 644 775 390
0.000 000 029 802 322 387 695
0.000 000 014 901 161 193 847

1.0

32
64
128
256
512
1 024
2 048
4 096
8
16
32
65

192

384
768
536
131 072
262 144
524 288
048 576
1
2 097 152
4 194 304
8 388 608
16 777 216
33 554 432
67 108 864
134 217 728
268 435 456
536 870 912
1 073 741 824
2 147 483 648
4 294 967 296
8 589 934 592
17 179 869 184
34 359 738 368
68 719 476 736
137 438 953 472
274 877 906 944
549 755 813 888
1 099 511 627 776
2 199 023 255 552
4 398 046 511 104
8 796 093 022 208
17 592 186 044 416
35 184 372 088 832
70 368 744 177 664
140 737 488 355 328
281 474 976 710 656
562 949 953 421 312
1
125 899 906 842 624
2 251 799 813 685 248
4 503 599 627 370 496
9 007 199 254 740 992
18 014 398 509 481 984
36 028 797 018 963 968
72 057 594 037 927 936
144 115 188 075 855 872
288 230 376 151 711 744
576 460 752 303 423 488
152 921 504 606 846 976
1
2 305 843 009 213 693 952
4 611 686 018 427 387 904
9 223 372 036 854 775 808
18 446 744 073 709 551 616
36 893 488 147 419 103 232
73 786 976 294 838 206 464
147 573 952 589 676 412 928
295 147 905 179 352 825 856
590 295 810 358 705 651 712
1
llo 591 620 717 411 303 424
2 le? ill 241 434 822 606 848
4 722 366 482 869 645 213 696

4
5

6
7

8
9
10
11

12
13
14

15
16
17

18
19
20
21

22
23
24
25
26
27
28
29
30
31

32
33
34
35
36
37
38
39
40
41

42
43
44
45
46
47
48
49
50
51

52
53
54
55
56
57
58
59

60
61

62
63
64
65
66
67
68
59
70
71

25
625
312 5
656 25
0.000 000 007 450 580 596 923 828 125
0.000 000 003 725 290 298 461 914 062 5
0.000 000 001 862 645 149 230 957 031 25
0.000 000 000 931 322 574 615 478 515 625
0.000 000 000 465 661 287 307 739 257 812 5
0.000 000 000 232 830 643 653 869 628 906 25
0.000 000 000 116 415 321 826 934 814 453 125
0.000 000 000 058 207 660 913 467 407 226 562 5
0.000 000 000 029 103 830 456 733 703 613 281 25
0.000 000 000 014 551 915 228 366 851 806 640 625
0.000 000 000 007 275 957 614 183 425 903 320 312 5
0.000 000 000 003 637 978 807 091 712 951 660 156 25
0.000 000 000 001 818 989 403 545 856 475 830 078 125
0.000 000 000 000 909 494 701 772 928 237 915 039 062 5
0.000 000 000 000 454 747 350 886 464 118 957 519 531 25
0.000 000 000 000 227 373 675 443 232 059 478 759 765 625
0.000 000 000 000 113 686 837 721 616 029 739 379 882 812 5
0.000 000 000 000 056 843 418 860 808 014 869 689 941 406 25
0.000 000 000 000 028 421 709 430 404 007 434 844 970 703 125
0.000 000 000 000 014 210 854 715 202 003 717 422 485 351 562 5
25
0,000 000 000 000 007 105 427 357 601 001 858 711 242 675 781
0.000 000 000 000 003 552 713 678 800 500 929 355 621 337 890 625
5
0,000 000 000 000 001 776 356 839 400 250 464 677 810 668 945 312
25
0,000 000 000 000 000 888 178 419 700 125 232 338 905 334 472 656
125
0,000 000 000 000 000 444 089 209 850 062 616 169 452 667 236 328
5
0.000 000 000 000 000 222 044 604 925 031 308 084 726 333 618 164 062
25
0.000 000 000 000 000 111 022 302 462 515 654 042 363 166 809 082 031
625
000 000 000 000 000 055 511 151 231 257 827 021 181 583 404 541 015
5u7 812 5
0.000 000 000 000 000 027 755 575 615 628 913 510 590 791 702 270
25
0.000 000 000 000 000 013 877 787 807 814 456 755 295 395 851 135 253 906
953 125
0.000 000 000 000 000 006 938 893 903 907 228 377 647 697 925 567 626
5
0.000 000 000 000 000 003 469 446 951 953 614 188 823 848 962 783 813 476 562
25
000 000 000 000 000 001 734 723 475 976 807 094 411 924 481 391 906 738 281
625
0,000 000 000 000 000 000 867 361 737 988 403 547 205 962 240 695 953 369 140
570 312 5
0,000 000 000 000 000 000 433 680 868 994 201 773 602 981 120 347 976 684
156 25
0.000 000 000 000 000 000 216 840 434 497 100 886 801 490 560 173 988 342 285
171 142 578 125
994
086
745
280
443
400
217
248
550
420
108
000
000
000
000
0.000 000
571 289 062 5
0.000 000 000 000 000 000 054 210 108 624 275 221 700 372 640 043 497 085
785 644 531 25
0.000 000 000 000 000 000 027 105 054 312 137 610 850 186 320 021 748 542
822 265 625
0,000 000 000 000 000 000 013 552 527 156 068 805 425 093 160 010 874 271 392
132 812
0,000 000 000 000 000 000 006 776 263 578 034 402 712 546 580 005 437 135 696 411
565 406
0,000 000 000 000 000 000 003 388 131 789 017 201 356 273 290 002 718 567 848 205
102 783 203
0,000 000 000 000 000 000 001 694 065 894 508 600 678 136 545 001 359 283 924
051 391 601
0,000 000 000 000 000 000 000 847 032 947 254 300 339 068 322 500 679 641 962
695 800
0,000 000 000 000 000 000 000 423 516 473 627 150 169 534 161 250 339 820 981 025
000 000 000 000 000 000 211 758 236 813 575 084 767 080 625 169 910 490 512 847 900
0,000

F-2

125
562 5
781 25
390 625

Octal -Decimal Integer Conversion Table

0000

6777

0311

(Octal)

(Dtcimol)

Octal

Decimal

10000 - 4096
8192
20000
30000 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 28672

0001

0002
0010
0018
0026
0034
0042
0050
0058

OOOjJ

0005 0006 0007
0013 0014 0015
0021 0022 0023
0029 0030 0031
0037 0038 0039
0045 0046 0047
0053 0054 0055
0061 0062 0063

0400
0410
0420
0430
0440
0450
0460
0470

0256
0264
0272
0280
0288
0296
0304
0312

0257
0265
0273
0281
0289
0297
0305
0313

0259
0267
0275
0283
0290 0291
0298 0299
0306 0307
0314 0315

0260
0268
0276
0284
0292
0300
0308
0316

0261 0262
0269 0270
0277 0278
0285 0286
0293 0294
0301 0302
0309 0310
0317 0318

0279
0287
0295
0303
0311
0319

0321

0000
0010
0020
0030
0040
0050
0060
0070

0000
0008
0016
0024
0032
0040
0048
0056

0009
0017
0025
0033
0041
0049
0057

0019
0027
0035
0043
0051
0059

0004
0012
0020
0028
0036
0044
0052
0060

0100
0110
0120
0130
0140
0150
0160
0170

0064
0072
0080
0088
0096
0104
0112
0120

0065 0066 0067
0073 0074 0075
0081 0082 0083
0089 0090 0091
0097 0098 0099
0105 0106 0107
0113 0114 0115
0121 0122 0123

0068
0076
0084
0092
0100
0108
0116
0124

0069
0077
0085
0093
0101
0109
0117
0125

0070
0078
0086
0094
0102
0110
0118
0126

0079
0087
0095
0103
0111
0119
0127

0500
0510
0520
0530
0540
0550
0560
0570

0320
0328
0336
0344
0352
0360
0368
0376

0329
0337
0345
0353
0361
0369
0377

0322
0330
0338
0346
0354
0362
0370
0378

0323
0331
0339
0347
0355
0363
0371
0379

0324
0332
0340
0348
0356
0364
0372
0380

0325
0333
0341
0349
0357
0365
0373
0381

0326
0334
0342
0350
0358
0366
0374
0382

0327
0335
0343
0351
0359
0367
0375
0383

0200
0210
0220
0230
0240
0250
0260
0270

0128
0136
0144
0152
0160
0168
0176
0184

0129
0137
0145
0153
0161
0169
0177
0185

0132
0140
0148
0156
0164
0172
0180
0188

0133 0134
0141 0142
0149 0150
0157 0158
0165 0166
0173 0174
0181 0182
0189 0190

0135
0143
0151
0159
0167
0175
0183
0191

0600
0610
0620
0630
0640
0650
0660
0670

0384
0392
0400
0408
0416
0424
0432
0440

0385
0393
0401
0409
0417
0425
0433
0441

0386
0394
0402
0410
0418
0426
0434
0442

0387
0395
0403
0411
0419
0427
0435
0443

0388
0396
0404
0412
0420
0428
0436
0444

0389
0397
0405
0413
0421
0429
0437
0445

0390
0398
0406
0414
0422
0430
0438
0446

0391
0399
0407
0415
0423
0431
0439
0447

0300
0310
0320
0330
0340
0350
0360
0370

0192
0200
0208
0216
0224
0232
0240
0248

0193 0194
0201 0202
0209 0210
0217 0218
0225 0226
0233 0234
0241 0242
0249 0250

0198
0206
0214
0222
0230
0238
0246
0254

0199
0207
0215
0223

0700
0710
0720
0730
0740
0750
0760
0770

0448
0456
0464
0472
0480
0488
0496
0504

0449
0457
0465
0473
0481
0489
0497
0505

0450
0458
0466
0474
0482
0490
0498
0506

0451
0459
0467
0475
0483
0491
0499
0507

0452
0460
0468
0476
0484
0492
0500
0508

0453 0454
0462
0469 0470
0477 0478
0485 0486
0493 0494
0501 0502
0509 0510

0455
0463
0471
0479
0487
0495
0503
0511

0011

0258
0266
0274
0282

0263
0271

lOOO

0512

1777

1023

(Oclol)

(Dtcimol)

0130
0138
0146
0154
0162
0170
0178
0186

0513
0521
0529
0537
0545
0553

0131

0139
0147
0155
0163
0171
0179
0187

0195 0196 0197
0203 0204 0205
0211 0212 0213
0219 0220 0221
0227 0228 0229
0235 0236 0237
0243 0244 0245
0251 0252 0253

0239
0247
0255

0517
0525
0533
0541
0549
0557
0565
0573

0518
0526
0534
0542
0550
0558
0566
0574

0519
0527
0535
0543
0551
0559
0567
0575

1400
1410
1420
1430
1443
1450
1460
1470

0769
0777
0785
0793
0801
0809
0817
0825

077P
077a
0786
0794
0802
0810
0818
0826

0779
0787
0795
0803
0811
0819
0827

0772
0780
0788
0796
0804
0812
0820
0828

0789
0797
0805
0613
0821
0829

0581
0689
0597
0605
0613
0621
0629
0637

0582
0590
0598
0606
0614
0622
0630
0638

0583
0591
0599
0607
0615
0623
0631
0639

1500 0832 0833
1510 0840 0841
1520 0848 0849
1530 0856 0657
1540 0864 0865
1550 0872 0873
1560 0880 0881
1570 0888 0889

0834
0842
0850
0858
0866
0874
0882
0890

0835
0843
0851
0859
0867
0875
0883
0891

0836
0844
0852
0860
0868
0876
0884
0892

0837 0638 0839
0845 0846 0847
0853 0854 0855
0861 0862 0863
0869 0870 0871
0877 0878 0879
0885 0886 0887
0893 0894 0895

0644 0645
0652 0653
0659 0660 0661
0667 0668 0669
067 5 0676 0677
0683 0684 0685
0691 0692 0693
0699 0700 0701

0646
0654
0662
0670
0678
0686
0594
0702

0647
0655
0663
0671
0679
0687
0695
0703

1600
1610
1620
1630
1640
1650
1660
1670

0896
0904
0912
0920
0928
0936
0944
0952

0897
0905
0913
0921
0929
0937
0945
0953

0898
0906
0914
0922
0930
0938
0946
0954

0899
0907
0915
0923
0931
0939
0947
0955

0900
0908
0916
0924
0932
0940
0948
0956

0901

0709
0717
0725
0733
0741
0749
0757
0765

0710
0718
0726
0734
0742
0750
0758
0766

0711
0719
0727
0735

1700
1710
1720
1730
1740
1750
1760
1770

0960
0968
0976
0984
0992
1000
1008
1C16

0961
0969
0977

0512
0520
0528
0536
0544
0552

0514
0522
0530
0538
0546
0554
0560 U561 0562
0568 0569 0570

0515
0523
0531
0539
0547
0555
0563
0571

0516
0524
0532
0540
0548
0556
0564
0572

1100
1110
1120
1130
1140
1150
1160
1170

0576
0584
0592
0600
0608
0616
0624
0632

0577
0585
0593
0601
0609
0617
0625
0633

0578
0586
0594
0602
0610
0618
0626
0634

0579
0587
0595
0603
0611
0619
0627
0635

0580
0588
0596
0604
0612
0620
0628
0636

1200
1210
1220
1230
1240
1250
1260
1270

0640
0648
0656
0664
0672
0580
0688
0696

0641

0642
0650
0658
0666
0674
0682
0690
0698

0643

1300
1310
1320
1330
1340
1350
1360
1370

0704
0712
0720
0728
0736
0744
0752
0760

0705
0713
0721
0729
0737
0745
0753
0761

0231

0461

1000
1010
1020
1030
1040
1050
1060
1070

0649
0657
0665
0673
0681
0589
0697

0071

0651

0706 0707 0708
0714 0715 0716
0722 0723 0724
07 30 0731 0732
0738 0739 0740
0746 0747 0748
0754 0755 0756
0762 0763 0764

F-3

0743
0751
0759
0767

0768
0776
0784
0792
0800
0808
0816
0824

0962
0970
0978
0985 0986
0993 0994
1001 1002
1009 1010
1017 1018

0771

0963 0964
0971 0972
0979 0980
0987 0988
0995 0996
1003 1004
1011 1012
1019 1020

0773
0781

0774
0782
0790
0798
0806
0814
0822
0830

0775
0783
0791
0799
0807
0815
0823
0831

0902
0910
0918
0926
0934
0942
0950
0958

0903
0911
0919
0927
0935
0943
0951
0959

0965 0966
097 3 0974
0981 0982
0989 0990
0997 0998
1005 1006
1013 1014
1021 1022

0967
0975
0983
0991
0999
1007
1015
1023

0909
0917
0925
0933
0941
0949
0957

Octal -Decimal Integer Conversion Table (Cont)
1

1286
1294
1302
1310
1318
1326
1334
1342

1287
1295
1303
1311
1319
1327
1335
1343

2000
2010
2020
2030
2040
2050
2060
2070

1024
1032
1040
1048
1056
1064

1072
1080

1025
1033
1041

1049
1057
1065
1073
1081

1026
1034
1042
1050
1058
1066
1074
1082

1027
1035
1043
1051
1059
1067
1075
1083

2100 1088 1089 1090 1091
2110 1096 1097 1098 1099
2120 1104 1105 1106 1107
2130 1112 1113 1114 1115
2140 1120 1121 1122 1123
2150 1128 1129 1130 1131
2160 1136 1137 1138 1139
2170 1144 1H5 114C 1147

1029
1037
1045
1053
1061
1069
1077
1085

1030
1038
1046
1054
1062
1070
1078
1086

1031
1039
1047
1055

1092 1093
1100 1101
1108 1109
1116 1117
1124 1125
1132 1133
1140 1141
1148 1149

1094
1102

1095
1103

1028
1036
1044
1052
1060
1068
1076
1084

1063
1071
1079
1087

UIO nil
1118 1119
1126 1127
1134 1135
1142 1143
1150 1151

1154
1162
1170
1178
1186
1194
1202
1210

1155
1163
1171
1179
1187
1195
1203
1211

1156
1164
1172
1180
1188
1196
1204
1212

1157
1165
1173
1181
1189
1197
1205
1213

1158
1166
1174
1182
1190
1198
1206
1214

1159
1167
1175
1183

1219
1227
1235
1243
1251
1259
1267
1275

1220
1228
1236
1244
1252
1260
1268
1276

1221

1249
1257
1265
1273

1218
1226
1234
1242
1250
1258
1266
1274

1229
1237
1245
1253
1261
1269
1277

1222
1230
1238
1246
1254
1262
1270
1278

1223
1231
1239
1247
1255
1263

1539
1547
1555
1563

1540
1548
1556
1564
1571 1572
1579 1580
1587 1588
1595 1596

1541

1542
1550
1558
1566
1574
1582
1590
1598

1543

1569
1577
1585
1593

1538
1546
1554
1562
1570
1578
1586
1594

3100 1600 1601
3110 1608 1609
3120 1616 1617
3130 1624 1625
3140 1632 1633
3150 1640 1641
3160 1648 1649
3170 1656 1657

1602
1610
1618
1626
1634
1642
1650
1658

1603

1605
1613

1659

1604
1612
1620
1628
1636
1644
1652
1660

3200
3210
3220
3230
3240
3250
3260
3270

1664
1672

1665
1673

1680
1688
1696
1704
1712
1720

1681

1666 1667
1674 1675
1682 1683
1690 1691
1698 1699
1706 1707
1714 1715
1722 1723

1668
1676
1684
1692
1700
1708
1716
1724

1669
1677
1685
1693

3300
3310
3320
3330
3340
3350
3360
3370

1728
1736
1744
1752
1760
1768
1776
1784

1729
1737
1745
1753

1730
1738
1746
1754
1762
1770
1778
1786

1732 1733
1740 1741
1748 1749
1756 1757
1764 1765
1772 1773
1780 1781
1788 1789

2200 1152
2210 1160
2220 1168
2230 1176
2240 1184
2250 1192
2260 1200
2270 1208

1153

1216
1224
1232
1240
1248
1256
1264
1272

1217
1225
1233

2300
2310
2320
2330
2340
2350
2360
2370

3000
3010
3020
3030
3040
3050
3060
3070

1536
1544
1552
1560
1568
1576
1584
1592

1161

1169
1177
1185

1193
1201
1209

1241

1537
1545
1553
1561

1689
1697
1705
1713
1721

1761

1769
1777
1785

1611
1619
1627

1635
1643
1651

1731

1739
1747
1755
1763
1771
1779
1787

1191

1199
1207
1215

1271

1279

2400
2410
2420
2430
2440
2450
2460
2470

1280 1281
1288 1289
1296 1297
1304 1305
1312 1313
1320 1321
1328 1329
1336 1337

1282
1290
1298
1306
1314
1322
1330
1338

1283

2500
2510
2520
2530
2540
2550
2560
2570

1344 1345 1346
1352 1353 1354
1360 1361 1362
1368 1369 1370
1376 1377 1378
1384 1385 1386
1392 1393 1394
1400 1401 1402

1347
1355
1363

2600
2610
2620
2630
2640
2650
2660
2670

1408
1416
1424
1432
1440
1448
1456
1464

1409
1417
1425
1433

1410
1418
1426
1434
1442
1450
1458
1466

1411

2700
2710
2720
2730
2740
2750
2760
2770

1472
1480
1488
1496
1504
1512
1520
1528

1473

1670 1671
1678 1679
1686 1687
1694 1695
1702 1703
1710 1711
1718 1719
1726 1727

3600
3610
3620
3630
3640
3650
3660
3670

1920
1928
1936
1944
1952
1960
1968
1976

1921

1735
1743

3700
3710
3720
3730
3740
3750
3760
3770

1984
1992

1985
1993
2001
2009
2017
2025
2033
2041

1759
1767
1775
1783
1791

2000
2008
2016
2024
2032
2040

1478
1486
1494
1502
1510
1518
1526
1534

1479
1487
1495
1503
1511
1519
1527
1535

1794 1795
1802 1803
1810 1811
1818 1819
1826 1827
1834 1835
1842 1843
1850 1851

1796
1804
1812
1820
1828
1836
1844
1852

1797
1805
1813

1858 1859
1866 1867
1874 1875
1882 1883
1890 1891
1898 1899
1906 1907
1914 1915

1860
1868
1876
1884
1892
1900
1908
1916

1861
1869
1877
1885

1922
1930
1938
1946
1954
1962
1970
1978

1923

1924
1932
1940
1948

1925
1933

1986
1994

1987
1995

1857
1865
1873

1751

1477
1485
1493
1501
1509
1517
1525
1533

1856
1864
1872
1880
1888
1896
1904
1912

1734
1742
1750
1758
1766
1774
1782
1790

1476
1484
1492
1500
1508
1516
1524
1532

3500
3510
3520
3530
3540
3550
3560
3570

1709
1717
1725

1469

1415
1423
1431
1439
1447
1455
1461
1471

1489
1497
1505
1513
1521
1529

1801

1809
1817
1825
1833
1841

1849

1B81

1889
1897
1905
1913

1929
1937
1945
1953
1961

1969
1977

F-4

1350 1351
1358 1359
1366 1367
1374 1375
1382 1383
1390 1391
1398 1399
1406 1407
1414
1422
1430
1438
1446
1454
1462
1470

1475
1483
1491
1499
1507
1515
1523
1531

1606 1607
1614 1615
1621 1622 1623
1629 1630 1631
1637 1638 1639
1645 1646 1647
1653 16j4 1655
1661 1662 1663

1701

1348 1349
1356 1357
1364 1365
1371 1372 1373
1379 1380 1381
1387 1388 1389
1395 1396 1397
1403 1404 1405

1474
1462
1490
1498
1506
1514
1522
1530

1481

1559
1567
1575
1583
1591
1599

1589
1597

1339

1459
1467

1441

1449
1457
1465

1793

1581

1331

1413

1792
1800
1808
1816
1824
1832
1840
1848

1551

1299
1307
1315
1323

1285
1293
1300 1301
1308 1309
1316 1317
1324 1325
1332 1333
1340 1341
1284
1292

1412
1420
1428
1436
1444
1452
1460
1468

3400
3410
3420
3430
3440
3450
3460
3470

1549
1557
1565
1573

1291

1419
1427
1435
1443
1451

1931

1939
1947
19j5
1963
1971

1979

2002 2003
2010 2011
2018 2019
2026 2027
2034 2035
2042 204 3

1956
1964
1972
1980

1421

1429
1437
1445
1453
1461

1821

1829
1837
1845
1853

1893
1901

1909
1917

1941

1949
1957
1965
1973
1981

1798 1799
1806 1807
1814 1815
1822 1823
1830 1831
1838 1839
1846 1847
1854 1855
1862
1870
1878
1886
1894
1902
1910
1918

1863
1871

1879
1887
1895
1903
1911

1919

1926 1927
1934 1935
1942 1943
1950 1951
1958 1959
1966 1967
1974 1975
1982 1983

1989 1990 1991
1997 1998 1999
2005 2006 2007
2013 2014 2015
2020 2021 2022 2023
2028 2029 2030 2031
2036 2037 2038 2039
2044 2045 2046 2047
1988
1996
2004
2012

1024

2000
to

2777

1J35

(Octol)

(Oecimol)

Octal

Decimal

10000- 4096
20000- 8192
30000- 12288

40000-16384
50000 - 20480
60000 24576
70000 - 28672
-

3000

1S36

3777

2047

(Octal)

(Decimal)

Octal-Decimal Integer Conversion Table (Cont)
6

4000

20-18

4777

2559

(Ociol)

iDecimal

Octal

Decimal

10000- 4096
20000 - 8192
30000- 12288
40000 • 16384
50000- 20480
60000- 24576
70000 - 28672

4010
4020
4030
4040
4050
4060
4070

2048
2056
2064
2072
2080
2088
2096
2104

2049
2057
2065
2073
2081
2089
2097
2105

2050
2058
2066
2074
2082
2090
2098
2106

4100
4110
4120
4130
4140
4150
4160
4170

2112
2120
2128
2136
2144
2152
2160
2168

4200
4210
4220
4230
4240
4250
4260
4270
4300
4310
4320
4330
4340
4350
4360
4370

•1000

2099
2107

2052
2060
2068
2076
2084
2092
2100
2108

2053
2061
2069
2077
2085
2093
2101
2109

2054
2062
2070
2078
2086
2094
2102
2110

2055
2063
2071
2079
2087
2095
2103
2111

4400
4410
4420
4430
4440
4450
4460
4470

2113 2114
2121 2122
2129 2130
2137 2138
2145 2146
2153 2154
2161 2162
2169 2170

2115
2123
2131
2139
2147
2155
2163
2171

2116
2124
2132
2140
2148
2156
2164
2172

2117
2125
2133
2141
2149
2157
2165
2173

2118
2126
2134
2142
2150
2158
2166
2174

2119
2127
2135
2143
2151
2159
2167
2175

4500 2368 2369 2370
4510 2376 2377 2378
4520 2384 2385 2386
4J30 2392 2393 2394
4540 2400 2401 2402
4550 2408 2409 2410
4560 2416 2417 2418
4570 2424 2425 2426

2176
2184
2192
2200
2208
2216
2224
2232

2177
2185
2193
2201
2209
2217
2225
2233

2178
2186
2194
2202
2210
2218
2226
2234

2179
2187
2195
2203

2180
2188
2196
2204
2211 2212
2219 2220
2227 2228
2235 2236

2181

2189
2197
2205
2213
2221
2229
2237

2182
2190
2198
2206
2214
2222
2230
2238

2183
2191
2199
2207
2215
2223
2231
2239

4600
4610
4620
4630
4640
4650
4 660
4670

2432
2440
2448
2456
2464
2472
2480
2488

2433
2441
2449
2457
2465
2473
2481
2489

2240
2248
2256
2264
2272
2280
2288
2296

2241

2242
2250
2258
2266
2274
2282
2290
2298

2243 2244
2251 2252
2259 2260
2267 2268
2275 2276
2283 2284
2291 2292
2299 2300

2245 2246 2247
2253 2254 2255
2261 2262 2263
2269 2270 2271
2277 2278 2279
2285 2286 2287
2293 2294 2295
2301 2302 2303

4700
4710
4720
4730
4740
4750
4760
4770

2496
2504
2512
2520
2528
2536
2544
2552

2249
2257
2265
2273
2281
22B9
2297

5000

2560

5777

3071

(Ocloll

(Decimol)

5000
5010
5020
5030
5040
5050
5060

2560
2568
2576
2584
2592
2600
2608
5070 2616

2561

2051

2059
2067
2075
2083
2091

2562
2570
2578
2586
2594
2601 2602
2609 2610
2617 2618

2563 2564
2571 2572
•2579 2580
2587 2588
2595 2596
2603 2604
2611 2612
2619 2620

2627 2028 2629 2630
2635 2636 2637 2638
2643 2644 2645 2646
2651 2652 2653 2654
2659 2660 2661 2662
2667 2668 2669 2670
2675 2676 2677 2678
2683 2684 2685 2686

2631
2639
2647
2655
2663
2671
2679
2687

2569
2577
2585
2593

2565 2566 2567
2573 2574 2575
2581 25^2 2583
2589 2590 2591
2597 2598 2599
2605 2606 2607
2613 2614 2615
J621 2622 2623

5100
5110
5120
5130
5140
5150
5160
5170

2624
2632
2640
2648
2656
2664
2672
2680

2625
2633
2641
2649
2657
2665
2673

5200
5210
5220
5230
5240
5250
5260
5270

2688
2696
2704
2712
2720
2728
2736
2744

2689
2697
2705
2713
2721
2729

2690
2698
2706
2714
2722
2730
27 37 2738
2745 2746

2691 2692 2693
2699 2700 2701
2707 2708 2709
2715 2716 2717
2723 2724 2725
2731 2732 2733
2739 2740 2741
2747 2748 2749

2694
2702
2710
2718
2726
2734
2742
2750

2695
2703

5300
5310
5320
5330
5340
5350
5360
5370

2752
2760
2768
2776
2784
2792
2800
2608

2753 2754
2761 2762
2769 2770
2777 2778
2785 2786
2793 2794
2801 2802
2809 2810

2755
2763
2771
2779
2787
2795
2803
2811

2758
2766
2774
2782
2790
2798
2806
2814

2759
2767
2775
2783
2791
2799
2807
2815

2681

2626
2634
2642
2650
2658
2666
2674
2682

2756
2764
2772
2780
2788
2796
2804
2812

2757
2765
2773
2781
2789
2797
2805
2813

F-5

2711
2719
2727
2735
2743
2751

2304
2312
2320
2328
2336
2344
2352
2360

2305 2306 2307
2313 2314 2315
2321 2322 2323
2329 2330 2331
2337 2338 2339
2345 2346 2347
2353 2354 2355
2361 2362 2363

2308
2316
2324
2332
2340
2348
2356
2364

2309
2317
2325
2333
2341
2349
2357
2365

2310
2318
2326
2334
2342
23SO
2358
2366

2359
2367

2371
2379
2387
2395
2403
2411
2419
2427

2372
2380
2388
2396
2404
2412
2420
2428

2373 2374
2381 2382
2389 2390
2397 2398
2405 2406
2413 2414
2421 2422
2429 2430

2375
2383
2391
2399
2407
2415
2423
2431

2435
2443
2451
2459
2467
2475
2483
2491

2436
2444
2452
2460
2468
2476
2484
2492

2437
2445
2453
2461
2469
2477
2485
2493

2438
2446
2454
2462
2470
2478
2486
2494

2439
2447
24SS
24^3

2497 2498 2499 2500
2505 2506 2507 2508
2513 2514 2515 2516
2521 2522 2523 2524
2529 2530 2531 2532
2537 2538 2539 2540
2545 2546 2547 2548
2553 2554 2555 2556

2501

2502
2510
2518
2526
2534
2542
2550
2558

2434
2442
2450
2458
2466
2474
2482
2490

2509
2517
2525
2533
2541
2549
2557

2311
2319
2327

2335
2343
23SI

2471
2479
2487
249S

2503
2511
2519
2527
253S
2543
2551
2559

Octal-Decimal Integer Conversion Table (Cent)
1

«000
eoio
6020
6030
6040
6050
6060
6070

3072
3080
3086
3096
3104
3112
3120
3128

3073
3081
3089
3097
3105

6100
6110
6120
6130
6140
6150
6160
6170

3136
3144
3152
3160
3168
3176
3184
3192

3137
3145
3153

6200 3200
3208
6220 3216
6230 3224
6240 3232
6250 3240
6260 3248
6270 3256

'6210

6300
6310
6320
6330
6340
6350
6360
6370

3113
3121

3129

3161

3169
3177
3185
3193
3201

3209
3J17
3225
3233
3241
3249
3257

3264 3265
3272 3273
3280 3281
3288 3289
3296 3297
3304 3305
3312 3313
3320 3321

7000
7010
7020
7030
7040
7050
7060
7070

3584
3592
3600
3608
3616
3624
3632
3640

3585
3593
3601
3609
3617
3625
3633
3641

6400
6410
6420
6430
6440
6450
6460
6470

3328
3336
3344
3352
3360
3368
3376
3364

3329
3337
3345
3353
3361
3369
3377
3385

3330
3338
3346
3354
3362
3370
3378
3386

3392
3400
3408
3416
3424
3432
3440
3448

3393

3159
3167
3175
3183
3191
3199

6500
6510
6520
6530
6540
6550
6560
6570

3206 3207
3214 3215
3222 3223
3230 3231
3238 3239
3246 3247
3254 3255
3262 3263

6600
6610
6620
6630
6640
6650
6660
6670

6700
6710
6720
6730
6740
6750
6760
6770

3074
3082
3090
3098
3106
3114
3122
3130

3075 3076
3063 3084
3091 3092
3099 3100
3107 3108
3115 3116
3123 3124
3131 3132

3077
3085
3093
3101
3109
3117
3125
3133

3078 3079
3086 3087
3094 3095
3102 3103
3110 3111
3118 3119
3126 3127
3134 3135

3138
3146
3154
3162
3170
3178
3186
3194

3139
3147
3155
3163
3171
3179
3187
3195

3MI

!il43

3202
3210
3218
3226
3234
3242
3250
3258

3203 3204
3211 3212
3219 3220
3227 3228
3235 3236
3243 3244
3251 3252
3259 3260

3140
3148
3156
3164
3172
3180
3188
3196

3142
3149 3150
3157 3159
3165 3166
3173 3174
3181 3182
3189 3190
3197 3198

3205
3213
3221
3229
3237
3245
3253
3261

3266 3267
3274 3275
3282 3283
3290 3291
3298 3299
3306 3307
3314 3315
3322 3323

3268
3276
3284
3292
3300
3308
3316
3324

3588
3596
3604
3612
3620
3628
3636
3644

3589
3597
3605
3613
3621
3629
3637
3645

3590
3598
3606
3614
3622
3630
3638
3646

3591

3599
3607
3615
3623
3631
3639
3647

7400
7410
7420
7430
7440
7450
7460
7470

3654
3662
3670
3678
3686
3694
3702
3710

3655
3663
3671
3679
3687
3695
3703
3711

3586 3587
3594 3595
3602 3603
3610 3611
3618 3619
3626 3627
3634 3635
3642 3643

3269 3270
3277 3278
3285 3286
3293 3294
3301 3302
3309 3310
3317 3318
3325 3326

3151

3271

3279
3287
3295
3303
3311
3319
3327

3349
3357
3365
3373
3381
3389

3334 3335
3342 3343
3350 3351
3358 3359
3366 3367
3374 3375
3382 3383
3390 3391

3409
3417
3425
3433
3441
3449

3394 3395 3396
3402 3403 3404
3410 3411 3412
3418 3419 3420
3426 3427 3428
3434 3435 3436
3442 3443 3444
3450 3451 3452

3397
3405
3413
3421
3429
3437
3445
3453

3398
3406
3414
3422
3430
3438
3446
3454

3456
3464
3472
3480
3488
3496
3504
3512

3457
3465
3473
3481
3489
3497
3505
3513

3458 3459 3460
3466 3467 3468
3474 3475 3476
3482 3483 3484
3490 3491 3492
3498 3499 3500
3506 3507 3508
3514 3515 3516

3462 3463
3469 3470 3471
3477 3478 3479
3485 3486 3487
3493 3494 3495
3501 3502 3503
3509 3510 3511
3517 3518 3519

3520
3528
3536
3544
3552
3560
3568
3576

3521

3401

3332
3340
3347 3348
3355 3356
3363 3364
3371 3372
3379 3380
3387 3388
3331
3339

3522 3523
3529 3530 3531
3537 3538 3539
3545 3546 3547
3553 3554 3555
3561 3562 3563
3569 3570 3571
3577 3578 3579

3840
3848
3856
3864
3872
3880
3888
3896

3841
3£49
3857
3865
3873
3881
3889
3897

3842
3850
3858
3866
3874
3882
3890
3898

7500
7510
7520
7530
7540
7550
7560
7570

3904
3912
3920
3928
3936
3944
3952
3960

3905
3913

3906 3907
3914 3915
3922 3923
3930 3931
3938 3939
3946 3947
3954 3955
3962 3963

3968 3969
3976 3977
3984 3985
3992 3993
4000 4001
4008 4009
4016 4017
4024 4025

3843 3844
3851 3852
3859 3860
3867 386S
3875 3876
3883 3884
3891 3892
3899 3900

3650
3658
3666
3674
3682
3690
3698
3706

3651
3659
3667
3675
3683
3691
3699
3707

3652 3653
3660 3661
3668 3669
3676 3677
3684 3685
3692 3693
3700 3701
3708 3709

7200
7210
7220
7230
7240
7250
7260
7270

3712
3720
3728
3736
3744
3752
3760
3788

3714
3722
3730
3738
3746
3754
3762
3770

3715
3723
3731
3739
374T
3755
3763
3771

3716
3724
3732
3740
3748
3756
3764
3772

3717 3718
3725 3726
3733 3734
3741 3742
3749 3750
3757 3758
3765 3766
3773 3774

3719
3727
3735
3743
3751
3759
3787
3775

7600
7610
7620
7630
7640
7650
7660
7670

7300
7310
7320
7330
7340
7350
7360
7J70

3776 3777 3778
3784 3785 3786
3792 3793 3794
3800 3801 3802
3608 3809 3810
3816 3817 3818
3824 3825 3826
3832 3833 3834

3779
3787
3795
3803
3811
3819
3827
3835

3780
3788
3796
3804
3812
3820
3828
3836

3781
3789
3797
3805
3813
3821
3829
3837

3782
3790
3798
3806
3814
3822
3B30
3838

3783

7700 4032 4033 4034 4035 4036
7710 4040 4041 4042 4043 4044
7720 4048 4049 4050 4051 4052
7730 4056 4057 4058 4059 4060
7740 4064 4065 4066 4067 4068
7750 4072 4073 4074 4075 4076
7760 4080 4081 4082 4083 4084

3713
3721

W29
3737
3745
3753
3761
3769

3791
3799
3807

3815
3823
3831
3839

3929
3937
3945
3953
3961

7770 4088 4089

F-6

3970
3978
3986
3994
4002
4010
4018
4026

3908
3916
3924
3932
3940
3948
3956
3964

4090 4091

3526
3534
3542
3550
3558
3566
3574
3582

3527
3535
3543
3551
3559
3567
3575
3583

3845 3846 3847
3853 3854 3855
3861 3862 3863
3869 3870 3871
3877 3878 3879
3885 3886 3887
3893 3894 3895
3901 3902 3903
3909
3917
3925
3933
3941
3949
3957
3965

3972 3973
3980 3981
3988 3989
3995 3996 3997
4003 4004 4005
4011 4012 4013
4019 4020 4021
4027.4028 4029
3971
3979
3987

3399
3407
3415
3423
3431
3439
3447
3455

6000

3072

6777

3S83

(Oclal)

(Decimal)

Octal

Decimol

10000
4096
20000
8192
30000- 12288
40000 16384
50000 20480
60000 24576
70000 28672
-

3461

3524 3525
3532 3533
3540 3541
3548 3549
3556 3557
3564 3565
3572 3573
3580 3581

7100 3648 3649
7110 3656 3657
7120 3664 3665
7130 3672 3673
7140 3680 3681
7150 3688 3689
7160 3696 3697
7170 3704 3705

3921

3333
3341

3910
3918
3926
3934
3942
3950
3958
3966

3911
3919
3927
3935
3943
3951
3959
3967

3974 3975
3982 3983
3990 3991
3998 3999
4006 4007
4014 4015
1022 4023
4030 4031

4037 4038 4039
4045 4046 4047
4053 4054 4055
4061 4062 4063
4069 4070 4071
4077 4078 4079
4085 4086 4087
4092 4093 4094 4095

7000

3584

7777

4095

(Octal!

(Decimal)

Octal-Decimal Fraction Conversion Table
DEC.

OCTAL

000000
.001953
.005859
.007812
.009765
.011718
.013671

.100
.101
.102
.103
.104
.105
.106
.107

.010
.011
.012
.013
.014
.015
.016
.017

.015625
.017578
.019531
.021484
.023437
025390
.027343
029296
,

.110
.111
.112
.113
.114
.115
.116
.117

.020
.021
.022
.023
.024
.025
.026
.027

.031250
.033203
.035156
.037109
.039062
.041015
.042968
.044921

.120
.121
.122
.123
.124
.125
.126
.127

.030
.031

.130

.036
.037

.046875
.048828
.050781
.052734
.054687
.056640
.058593
.060546

.040
.041
.042
.043
.044
.045
.046
.047
.050
.051
.052
.053
.054
.055
.056
.057

OCTAL
.000
.001
.002
.003
.004
.005
.006
.007

.032
.033
.034
.035

.060
.061
.062
.063
.064

.065
.066
.067
.070
.071
.072
.073
.074
.075
.076
.077

(J03906

DEC.

OCTAL

DEC.

OCTAL

UKC.

125000
126953
128906
.130859
.132812
. 134765
.136718
.138671

.200
.201
.202

.250000
.251953
253906
.255859
,257812
.259765
.261718
.263671

.300
.301
.302
.303
.304
.305
.306
,307

.375000
.37C953
.378906
.380859
.382812
.384765
.386718
.388671

140625
142578
.144531
.146484
.148437
.150390
.152343
154296

.210
.211

.310
.311
.312

.212
.213
.214
.215
.216
.217

.265625
.267578
.269531
.271484
.273437
.275390
.277343
.279296

.390625
.392578
.394531
.396484
.398437
.400390
.402343
.404296

.281250
.283203
.285156
.287109
.289062
.291015
.292968
.294921

.320

296875
.298828
.300781
.302734
.304687
.306640
.308593
.310546

.330
.331
.332

.333
.334
.335
.336
.337

.421875
.423828
.426781
427734
.429687
.431640
.433593
.435546

.340
.341
.342
.343
.344
.345
.346
.347

.437500
.439453
.441406
.443359
.445312
.447265
.449218
.451171

.350

.355
.356
.357

.453125
.455078
.457031
.458984
.460937
.462390
.464843
.466796

.203
.204
.205

.206
.207

.313
.314
.315
.316
.317

.406250
.408203
.410156
.412109
.414062
.416015
.417968
.419921

156250
.158203
.160156
.162109
164062
.166015
. 167968
.169921

.220
.221

.132
.133
.134
.135
.136
.137

.171875
.173828
.175781
177734
. 179687
.181640
.183593
185546

.230
.231
.232
.233
.234
.235
.236
.237

.062500
.064453
.066406
.068359
.070312
.072265
.074218
.076171

.140
.141
.142
.143
.144
.145
.146
.147

.187500
.189453
191406
193359
.195312
197265
.199218
.201171

.240
.241

.245
.246
.247

.312500
.314453
.316406
.318359
.320312
.322265
.324218
.326171

.078125
.080078
.082031
.083984
.085937
.087890
.089843
.091796

.150
.151
.152
.153
.154

.155
.156
.157

.203125
.205078
.207031
.208984
.210937
.212890
.214843
.216796

.250
.251
.252
.253
.254
.255
.256
.257

.328125
330078
.332031
.333984
.335937
.337890
.339843
.341796

093750
.095703
.097656
.099609
.101562
.103515
105468
.107421

.160
.161
.162
.163
.164
.165
.166
.167

.218750
.220703
.222656
.224609
.226562
.228515
.230468
.232421

.260
.261
.262
.263
.264
.265
.266
.267

.343750
.345703
.347656
.349609
.351562
.353515
.355468
.357421

.360
.361
.362
.363
.364
.365
.366
.367

.468750
.470703
.472656
.474609
.476562
.478515
.460468
.482421

109375
.111328
.113281
.115234
.117187
.119140
. 121093
123046

.170
.171
.172
.173
.174
.175
.176
.177

.234375
.236328
.238281
.240234
.242187
.244140
.246093
248046

.270
.271
.272
.273
.274
.275
.276
.277

.359375
.361328
.303281
.365234
.367187
.369140
.371093
.373046

.370
.371
.372
.373
.374
.375
.376
.377

.484375
.486328
.48S2B1
.490234
.492187
.494140
.496093
.498046

131

.222
.223
.224
.225
.226
.227

.242

.243
.244

F-7

.321

.322
.323
.324
.325
.326
.327

.351
.352

.353
.354

Oct-a -Decimal Fraction Conversion Table (Cont)
I

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

, 000000
.000001
.000002
000003
.000004
000005
.000006
.OOOOOT

000000
.000003
.000007
.000011
.000015
.000019
. 000022
. 000026

.000100
.000101
.000102
.000103
.000104
.000105
.000106
.000107

000244
.000247
. 000251
.000255
.000259
.000263
.000267
.000270

. 000200
.000201
.000202
.000203
.000204
.000205
. 000206
. 000207

.000488
.000492
000495
000499
.000503
.000507
.000511
.000514

000300
.000301
. 000302
.000303
. 000304
.000305
.000306
.000307

.000732
.000736
000740
000743
000747
.000751
. 000755
. 000759

.000010
.000011
.000012
.000013
.000014
.000015
. 000016
.000017

000030
.000034
.000038
.000041
000045
.000049
000053
. 000057

,000110
.000111
.000112
.000113
.000114
.000115
.000116
.000117

000274
.000278
.000282
. 000286
. 000289
. 000293
.000297
.000301

.000210
.000211
.000212
.000213
.000214
.000215
.000216
.000217

.000518
.000522
. 000526
. 000530
.000534
000537
. 000541
. 000545

.000310
.000311
.000312
.000313
.000314
.000315
.000316
.000317

000762
.000766
000770
000774
000778
000782
000785
. 000789

000020
.000021
.000022
.000023
000024
.000025
.000026
.000027

000061
000064
. 000068
.000072
. 000076
.000080
. 000083
. 000087

.000120
.000121
.000122
.000123
.000124
. 000125
.000126
.000127

.000305
.000308
.000312
.000316
.000320
.000324
.000328
.000331

000220
.000221
.000222
. 000223
. 000224
. 000225
. 000226
.000227

000549
000553
. 000556
000560
.000564
000568
. 000572
.000576

000320
.000321
. 000322
000323
. 000324
. 000325
. 000326
. 000327

000793
.000797
.000801
.000805
000808
.000812
.000816
000820

.000030
.000031
.000032
.000033
.000034
. 000035
. 000036
. 000037

.000091
. 000095
.000099
.000102
.000106
.000110
.000114
.000118

.000130
.000131
.000132
.000133
.000134
.000135
.000136
.000137

.000335
.000339
.000343
.000347
.000350
.000354
.000358
.000362

.000230
.000231
.000232
.000233
,000234
.000235
.000236
.000237

000579
000583
000587
.000591
. 000595
.000598
. 000602
. 000606

000330
.000331
. 000332
. 000333
. 000334
.000335
.000336
. 000337

000823
000827
.000831
000835
.000839
.000843
. 000846
. 000850

000040
.000041
.000042
000043
000044
000045
000046
.C00047

.000122
.000125
.000129
.000133
.000137
.000141
.000144
.000148

.000140
.000141
.000142
.000143
.000144
.000145
.000146
.000147

.000366
.000370
.000373
.00037T
.000381
. 000385
. 000389
.000392

.000240
.000241
. 000242
. 000243
.000244
. 000245
.000246
000247
.

.000610
.000614
.000617
.000621
000625
.000629
000633
.000637

000050
. 000051
.000052
. 000053
. 000054
. 000055
.000056
. 000057

.000152
.000156
.000160
.000164
.000167
.000171
00017S
.000179

.000150
.000151
.000152
.000153
.000154
.000155
.000156
.000157

.000396
000400
000404
. 000408
.000411
.000415
.000419
. 000423

000250
. 000251
.000252
000253
000254
.000255
. 000256
.000257

000640
. 000644
.000648
.000652
.000656
.000659
000663
.000667

.000350
.000351
.000352
000353
. 000354
. 000355
. 000356
.0003-.

000060
.000061
.000062
.000063
.000064
.000065
.000066
.000067

.000183
. 000186
000190
.000194
.000198
.000202
000205
.000209

.000160
.000161
.000162
.000163
.000164
.000165
.000166
.000167

.000427
.000431
.000434
000438
000442
.000446
000450
.000453

000260
000261
. 000262
000263
. 000264
000265
000266
.000267

,000671
. 000675
.000679
. 000682
000686
.000690
.000694
000698
.

000360
.000361
. 000362
. 000363
000364
000365
. 000366
000367
.

.000915
.000919
. 000923
. 000926
.000930
000934
.000938
.000942

.000070
.000071
.000072
.000073
.000074
000075
000076
.000077

.000213
. 000217
. 000221
. 000225
.000228
.000232
.000236
.000240

.000170
.000171
.000172
.000173
.000174
.000175
.000176
.000177

.000457
.000461
.000465
000469
.000473
.000476
.000460
000484

000270
.000271
.000272
000273
000274
.000275
.000276
.000277

.000701
.000705
.000709
.000713
.000717
.000720
. 000724
000728

.000370
.000371
. 000372
000373
.000374
. 000375
000376
.000377

.000946
000949
.000953
.000957
.000961
. 000965
. 000968
. 000972

.
.

F-8

.
.

000340
.000341
.000342
000343
000344
000345
00034b
000347
.

.
.

000854
000858
. 000862
.000865
. 000869
. 000873
.000877
.000881
.
.

000885
.000888
. 000892
.000896
000900
.000904
.000907
.000911
.