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DEC-8I-H8NA-D

December 1970

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Document:	KT8I Time-Sharing Option
Order Number:	DEC-8I-H8NA-D
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Pages:	18
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OCR Text

DEC-8I-H8NA-D

TIME-SHARING OPTION
FUNCTIONAL DESCRIPTION

DIGITAL

EQUIPMENT CORPORATION n MAYNARD

MASSACHUSETTS

1st Printing June

1969

2nd Printing February 1970

The material

in this manual

for informa-

tion purposes and is subject to change with-

out notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

KTB/I

TIME-SHARING OPTION
FUNCTIONAL DESCRIPTION

The KT8/I Time-Sharing Option provides the
additional logic circuits required for use by

the PDP-8/I in the TSS/8 Time-Sharing System.

Certain configurations of PDP-8/l I/O devices
and other options must also be used with the
TSS/8 Time-Sharing System. The minimum
equipment required for a four-user TSS/8 Time-

executed for only a fraction of a second at a
time, and the different programs are interspersed without interfering with each other and
without noticeable delays in the responses to

each user.

TSS/8 MONITOR PROGRAM

Sharing System is:
a. PDP-8/I with KT8/I Time-Sharing Option
b.

MC8/I-A Memory Extension Control and

8192 Words of Memory
c.

RF08 Disk Control

d. RS08 Disk File

Time sharing of the PDP-8/l central processor
among a group of users is controlled by a group
of subprograms called the TSS/8 Monitor which
coordinates the operation of various I/O devices, allocates central processor time and
services to the users, and controls user access
to the central processor.

User programs are usually stored in disk memory and are transferred into core memory to be

e. PT08C Asynchronous Serial Line InterfacesFull

Duplex (Dual Channel) (Four Required)

PR8/1 High-Speed Tape Reader-300 Char-

acters per Second

g. KE8/1 Extended Arithmetic Element (EAE)
h.

CAB 8/IA Option Cabinet

The TSS/8 Time-Sharing System permits up to
16 users to operate their individual programs in

run. Activation of the user programs is handled
by a sequential -loop algorithm under the control of the TSS/8 Monitor. The user program is
allowed to run for a fixed period of time, and
is then stopped .
The contents of the program
counter and the various registers are stored at
the time execution is stopped; the program is
returned to disk storage; and the next user program is read into core memory for processing

User programs are terminated by the TSS/8
Monitor for various reasons other than the ex-

the PDP-8/I in an apparently simultaneous

piration of their allotted time period.

manner.

are terminated when an output buffer is filled,

Operation and reaction time of some
I/O devices and of human operators is slow
compared to the speed of the central processor.
Time sharing allows the central processor to
proceed to other tasks rather than wait for slow
operations of I/O devices and human operators.
In this way the processor can deal with many
users and make it appear as if each had full
use of the processor. Each user's program is

They

when an input is requested and the input buffer
is not filled, and for certain other conditions.
Thus, central processor time is not wasted
waiting for comparatively slow I/O devices.

User programs are not allowed to perform HLT,

OSR, or IOT instructions in the usual manner
because normal processing of these instructions

executive mode and the TSS/8 Monitor is in
control of the central processor. The three added instructions are used by the TSS/8 Monitor
only in the executive mode and are never used

would disrupt the operation of the central processor or interfere with the operation of I/O

devices shared with other users. When one of
these instructions appears in a user program, a
user interrupt takes place and the TSS/8 Mon-

by a user program. If a user program attempted
to use one of these instructions, execution of
the instruction would be blocked and a user
interrupt would result because they are IOT
(octal code 6XXX) instructions. The KT8/1
option adds the necessary hardware to the
PDP-8/I to implement these three instructions.

itor takes control of the central processor.

Three instructions are added by the KT8/1 to
permit the TSS/8 Monitor to process user interrupts caused by HLT, OSR, or IOT instructions.

KT8/1 PROGRAM INSTRUCTIONS

HARDWARE
The KT8/I uses three instructions to permit the
TSS/8 Monitor to handle user interrupts and to
instructions are listed with their octal codes

The backplane wiring necessary for the KT8/I
Time-Sharing Option is included in the PDP-8/I
computers with basic frame serial numbers

and descriptions in Table 1

greater than 996

control the user interrupt logic circuits.

These

Table 1

KT8/I Program Instructions

Mnemonic
Code

Octal

CINT

6204

Description

Code
Clear user interrupt.
flop to the

SINT

6254

state.

Skip on user interrupt.
flop is in the
to the

Resets the user interrupt (UINT) flip-

When the user interrupt (UINT) flip-

state, sets the user skip flag (USF) flip-flop

state and causes the program to skip the next

instruction.

CUF

Change user flag.

6264
6274

to the state of

Changes the user buffer (UB) flip-flop

MB 08 of the CUF instruction word.

In-

JMP or JMS inthe
next JMP or
IF during
Generation of IB

hibits processor interrupts until the next

struction.

JMS instuction transfers the state of UB to the user field
(UF) flip-flop.

The KT8/1 operates in two modes as denoted by
the user flag (UF) flip-flop. When the UF
flip-flop is in the logic

state, operation

the user mode and a user program is running in
the central processor. When the UF flip-flop
is

in the logic

state, operation

in the

To implement the KT8/I option in PDP-8/I
computers with earlier serial numbers, a new
logic frame must be purchased and installed.
Installation of the logic frame must be per-

formed by DEC Field Service personnel.

Four modules and one module that is shared

KT8/1 Time-Sharing Option.

with the PDP-8/1 and the extended memory

are shown installed

option are required for the logic circuits of the

and are listed in Table 2.

These modules

the PDP-8/1 in Figure

wSSaSm

MM
fp

S^Sfy&JftS?

Figure

PDP-8/1 with KT8/I Modules Installed

Table 2
KT8/I Modules

Module
Type No.

Quantity

Use

Location

Row

Slot

M216

Flip-Flops

M113

NAND Gates

A
A

05
06*

M115

''This mc

Jule

NAND Gates

shared with the PDP-8/1 and the extended memory option.

]

The 1-side output of the UF flipflop is applied to an AND gate; the other in-

GENERAL LOGIC DESCRIPTION

in Figure 2.

put to the

a signal resulting from

OSR, or IOT instruction.
Output of the AND gate sets the UINT flipflop when UF(I) is high and an HLT, OSR, or
IOT instruction is dec oded. When UINT is
set, the signal UINT goes low and provides a

a decoded HLT,

Types of Interrupts

The PDP-8/I central processor operates in the
executive mode (UF(0) high) so that the TSS/8
Monitor can perform the necessary housekeeping and service routines, or in the user mode
(UF(I) high) so that an individual user program
can use the central processor to perform its
programmed tasks. Either mode of operation is
subject to program interrupts which are handled
by the interrupt logic of the central processor.
In the TSS/8 Time-Sharing System,

AND gate

program

interrupts are caused by I/O devices, the real-

signal to the interrupt bus of the central pro-

cessor .

Processing Interrupts

The I/O, real-time clock, or user program
interrupts cause the following sequence of
operations:

time clock, and the user program.
a. The state of the user flag (UF) flip-flop is
Interrupts caused by I/O devices are similar to
the I/O interrupts that occur with a single-user
PDP-8/I and are processed in the same way.

transferred to the save user flag (SUF) flipflop (refer to Figure 2) by signal IF

* SF.

b. The user flag (UF) and use r buffer (UB)

The real-time clock, a required option for the

flip-flops are cleared by the CLEAR IF signal.

time-sharing system, also causes interrupts. A
real-time clock interrupt occurs about every

Operation is changed to executive mode
(UF (0) high) if operation was in the user

17 ms while the user program is running, so
that the executive mode can be used for the
TSS/8 Monitor to perform the housekeeping

mode.

routines required for management of the time-

sharing system.

c The interrupt logic of the PDP-8/1 causes
an automatic JMS 0000 instruction.
.

For instance, on every third

17 ms interrupt the teletype lines are scanned.

d. One of the first instructions in the sub-

Real-time interrupts also terminate the user
program operational period of approximately
200 ms

transfers the state of the SUF onto the

routine is a read interrupt buffer (RIB) which

ME 05

line so that the SUF bit can be stored in

memory along with the content of the save

When a user program is running (user mode),
programming of an HLT, OSR, or IOT instruction causes an interrupt. The user interrupts
are necessary to prevent a user program from

field register.

e. The subroutine checks for the cause of the
interrupt.

disrupting the operation of the central pro-

One of the final instructions in the sub-

cessor or from interfering with the operation of

I/O devices shared with other users.

routine is a turn interrupt on (ION) which

re-enables the interrupt logic.

A simplified block diagram of the logic circuits
OSR,
shown
mode
is
or IOT is programmed in the user
that generate an interrupt when an HLT,

interrupt is caused by an I/O device, a
jump is made to a subroutine which services the
I/O device.
If the

SINT.

SET

HLT+OSR+IOT.

SET

USER
INTER-

USER

TP2-E

SKIP

RUPT
(UINT)

CINT.

FLAG

TPI-F

(USF)

RESET

SKIP

ORED
SKIP(0)

.UNIT

CUF6274'

SET

CUF6264.

CLEAR

DATA

USER
BUFFER

USER

FLAG

SAVE
USER
FLAG

(UB)

(UF)

(SUF)

RESET
CLEAR

IB-IF_^ CLOCK G

IF-SF.,

RIB.

CLOCK

CLEAR

,_a

RMF

Figure 2

KT8/[ Simplified Block Diagram

ME05

If the

interrupt is caused by the real-time

available to the user of the TSS/8 is provided

clock, a jump is made to a subroutine that
checks the timing pulse count. An appropri-

in Appendix C of the TSS/8 Monitor Manual

ate subroutine is used for the housekeeping
functions scheduled for that timing count. If

Monitor handles the processing of the IOT instruction in the executive mode in such a man-

the timing count designates the end of the user
program running period, the user program queue

ner that I/O devices shared by other users are
not interfered with, no central processor time

checked for availability of another user program.

wasted waiting for a slow I/O device, and
the user program accomplishes the I/O function.

User Program Interrupts

Use of RMF Instruction

To check whether the interrupt is caused by
the user program, a skip on user interrupt

In some cases where the TSS/8 Monitor can

(SINT) instruction is used (refer to Figure 2).
The 1 side of UINT is AND gated with signal

interfering with the save field register, the

SINT so that the user skip flag (USF) is set

a RIB instruction. When interrupt processing is
completed, the instruction field register and
the user flag (UF) are restored by use of a re-

when UINT is set and a skip on user interrupt
(SINT) instruction is decoded. With USF set,
the SKIP ORED signal is high and the next
The USF is reset by
progra m step is skipped
the execute or
during
TPI
-F
signal TP2-E or
.

fetch cycle of the next instruction after the
skip instruction.

The skip causes the program

(DEC-T8-MRFA-D).

In general, the TSS/8

process an interrupt quickly and without

SUF bit is not transferred to memory by use of

store memory field

(RMF) instruction .
RMF transfers the bit in SUF into UB.

Signal

The

TSS/8 Monitor then uses a JMP instruction to
return to the appropriate program address.
Signal IB

* IF is generated when the JMP

to enter a subroutine that services the interrupt.

instruction is used and transfers the bit in

One of the first instructions in the subroutine

into UF.

a clear user interrupt (CINT) which clears

the user interrupt (UINT) flip-flop.

The program then continues in either

the executive or user mode until the next
interrupt.

Performance of any HLT, OSR or IOT instruction in the user program is automatically

Return Routine

blocked by the KT8/I logic circuits and the
For an
TSS/8 Monitor takes program control
the
halts
Monitor
HLT Instruction, the TSS/8
.

user program and checks the user program
queue for the next user program available to be

run.

For an OSR instruction, the content of

the core location which has been designated as
the switch register for this user program is processed under TSS/8 Monitor control in accordance with the switch register instruction in the
user program.

For an IOT instruction, the TSS/8 Monitor takes

a different course of action for the various IOT
instructions. A complete list of IOT instructions

After completion of a subroutine which services

an interrupt, a return routine is used to go
back to the operating status at the time the
As part of this return
interrupt occurred
field
(UF) flip-flop must be
routine, the user
restored to the state it was in at the occurrence
.

of the program interrupt.

At the start of the interrupt the UF was transferred to the SUF and fro m there to the central
processor memory via the ME 05 line. Since
no hardware provision is made to transfer the
SUF bit from the core memory back into the UF
logic circuits, the TSS/8 Monitor must check

the status of the SUF bit and then program a

Time-Sharing Option.

change user flag (CUF) instruction to restore
the UF. The CUF instruction either clears

interrupt (UINT) and user skip flag (USF) flip-

(6264) the UB or sets (6274) the UB (refer to

Figure 2).

When the TSS/8 Monitor has re-

The user buffer (UB),
the user flag (UF), save user flag (SUF), user
flops with their associated gating circuits are

stored all registers and memory fields to the

shown on this diagram. The UB, UF, and
SUF flip-flops can be considered as 1-bit

status they occupied at the time of the inter-

extensions of the instruction buffer (IB) regis-

rupt, a JMP instruction returns to the program

ter, the instruction field (IF) register,

address following the address that was inter-

save field (SF) register, respectively.

and the
These

rupted . The JMP instruction causes the generation of signal IB - IF which transfers the UB
bit into the UF flip-flop. The program then

and are shown on engineering drawing

continues in either the executive or the user

used to transfer bits among these registers are

mode until the next interrupt.

registers are part of the extended

memory logic

D-BS-MC8I-0-1, sheets 1 and 2. The signals
also used to transfer a bit among the

UB, UF,

and SUF.

Flow Diagram
User Buffer

The flow diagram for the KT8/I Fetch cycle of
user program instructions is shown in engineering drawing D-FD-KT8-I-2. This diagram

The bits of the instruction word are decoded by

shows when the UINT flip-flop is set for an

the logic gates shown in area B6 and 7 of
engineering drawing D-BS-KT8-I-1 . Decod-

IOT, HLT, or OSR instruction.

ing of the octal instruction 6264 (CUF) results

When processing an IOT instruction and UF(1)
is high, the UINT is set at TP3 time.
When
processing an OPR Instruction in Group 2

in a clock input to the UB flip-flop. Because
memory bit 08 is 0, the data input to the UB
remains low so that UB is reset. When the
instruction word is octal 6274, memory bit 08
is 1 so that the data input to UB is high when

(MB 03 = 1 and MB II = 0) and UF(1) is high,
UINT is set for two different conditions.
An HLT instruction (MB 10 = 1) or an OSR
instruction (MB 09 = 1) causes the UINT to be
the

set at TP3 time.

the clock input is high and the flip-flop is set.

The UB i s cleared by the PC LOAD

•

ENABLE signal when the LOAD ADD switch on
the front panel of the PDP-8/1 is used.

Clear-

When UINT is set for an IOT, HLT, or OSR

ing of the UB is also accomplished by the

instruction, the interrupt bus to the central
processor goes high and activates the interrupt

CLEAR IF signal which occurs when the content of the IF register of the extended memory

logic circuits of the central processor.

unit Is transferred to the SF register

Opera-

tion is changed to the executive mode (UF (0)
high) and a JMS 0000 becomes the next pro-

(D-BS-MC8I-0-1 , sheet 1) in preparation for
processing an interrupt.

gram instruction.

The state of the SUF flip-flop is transferred to
the UB flip-flop when the TSS/8 Monitor issues

DETAILED LOGIC DESCRIPTION

a restore mem ory field (RMF) instruction.
inverted RMF signal

Engineering drawing D-BS-KT8-I-1

a de-

The

NAND gated with the

tailed block schematic of the logic circuits

EXT
signal to provide a clock input to UB.
Signals SUF (1) and SF ENABLE are combined

that are added to the PDP-8/1 for the KT8/I

in a

NAND gate to supply the data input of UB

The bit in the SUF flip-flop is transferred to
the UB flip-flop when the TSS/8 Monitor issues
a restore memory field (RMF) instruction. A
description of the logic circuits that accomplish

with a signal that transfers the state of SUF to

UB.

this transfer is provided in the user buffer sec-

User Flag

tion.

The 1-side output of UB is NAND gated with
the KEYLA MFTS

Signal INITIALIZE clears the SUF during startup of the system when the power supply reaches

signal so that transfer of

the bit in UB to the UF is inhibited during a
key load address operation. Signal IB - IF,

the proper level, when power begins to fail, or
when the START key is depressed

which occurs at TP3 during a JMP or JMS
instruction, is used to clock UF and thereby
transfer the state of the UB to the UF

User Interrupt

The UF is clea red at the same time the UB is
T he clearing
cleared by the CLEAR IF signal
of the UF and UB by the CLEAR IF signal is
done when an interrupt is being processed and
the central processor must go into executive

The user interrupt (UINT) flip-flop is shown in
area D3 of engineering drawing D-BS-KT8-I-1.
Gates located in area DC6 and 7 of this same
engineering drawing decode an HLT or OSR

mode (UF (0) high).

instruction and provide an input to a

Prior to the clearing of

gate

the two flip-flops, the bit in UF is transferred
to the save user flag (SUF) flip-flop.

NOR

The other nput to th is NOR gate is
i

provided by signal I - IOT, which is low whenever an IOT instruction (octal code 6XXX) is
decoded The output of the NOR gate is combined in a NAND gate with the 1-side output
.

Save User Flag

of UF, and the output of the

NAND gate pro-

vides the data input to the UINT. The result
of this gating is that the UINT is set at TP3

The I -side output of UF provides the data
input to SUF so that the bit in UF is trans-

time when the UF is in the

ferred to SUF when SUF is clocked by signal
IF - SR. This signal is the same signal that

state and an

HLT,

OSR, or IOT instruction is decoded.

transfers the contents of the information field

When the UINT is set to the

drawing D-BS-MC8I-0-1 , sheet 1) of the extended memory logic. Transfer to the SUF is
done when the TSS/8 Monitor is processing an
int errupt. Sig nal INT OK is used to generate

in this state until

state,

remains

a clear user interrupt (CINT)
gate in area
A

instruction is decoded.

NAND

D4 of engineering drawing D-BS-KT8-I-1 has
Inputs of CINT and UINT (1) so that the data
input to UINT remains high until the NAND
gate shown in area C6-7 de codes a CINT instruction and signal CINT goes low. Signal
INITIALIZE also clears UINT during start-up of

the LOAD SF signal at TS4 time (engin eering
drawing D-BS-8I-0-7), and LOAD SF generates signal IF

- SF

The 1-side output of SUF is combined in a NAND
gate with RIB, which is high when the read
interrupt buffer (RIB) instruction is decoded by
the extended memory logic (engineering drawing BS-MC8I-0-1, sheet 2). The RIB instruction therefore reads th e bit in SUF into bit 5 of
the AC on the ME 05 line which activates the
INPUT BUS 05 line in the central processor.

the system when the power supply reaches the
proper level, when power begins to fail, or

when the START key is depressed
The UINT signal is generated by a NOR gate
that has as inputs the UINT (0) signal and the
signal that originally set the UINT flip-flop.

The UINT signal is used, by the logic circuits
shown in area A6 on engineerin g drawi ng
D-BS-8I-0-12, to generate the TT INT signal

the next program instruction is skipped.

These teletype logic circuits provide a signal

the

Thus,

a SINT instruction causes the next program
instruction to be skipped when the
1

UINT is in

state.

to the interrupt bus of the central processor.

Therefore, whenever the UINT is in the

state,

the interrupt bus of the central processor Is

Instruction Inhibit Logic

activated

Operation of the TSS/8 Time-Sharing System
requires that the user program be prevented

from interfering with the operation of the cen-

User Skip Flag

tral

processor and the operation of the I/O

The user skip flag (USF) flip-flop is shown in
area D2 of engineering drawing D-BS-KT8-I-1.
Gates shown in area B6 of this same engineering
drawing are used to decode the skip on user
interrupt (SINT) instruction. The output of
these gates is combined in a NAND gate with
TP3 and UINT (1). Output of the NAND gate

of the OSR instruction Is necessary because the

provides the set input for USF so that USF is

various users who are sharing time on the cen-

set at TP3 when

UINT is in the

state and a

SINT instruction is decoded.
The clock input of US F is provid ed by a NOR
gate which has signals TP2-E and TPI *F as
inputs. These input signals are generated by
the logic circuits shown in area D2 and 3 of
engineering drawing D-BS-8I-0-6. Since the
data input is grounded, the SUF is cleared at
TP2 of the Exe cute cycle or at TPI of the Fetch
cycle. Signal INITIALIZE also clears the USF
during start-up of the system when the power
supply reaches the proper level , when power
begins to fail, or when the START key is
depressed

The 0-side output of USF and signal SKIP (0)
provide inputs to the NOR gate shown in area
D2 of engineering drawing D-BS-KT8-I-1
Output signal SKIP ORED from this gate is used
by the logic circuits shown in area B4 of engineering drawi ng D-BS-8I-0-5 t o genera te a
CARRY I NSERT signal . With the CARRY

devices.

Therefore, normal execution of the

HLT or the IOT instructions in the user program
is

inhibited.

Normal execution of an OSR instruction in the
user program is also inhibited .

This treatment

processor do not have access to the switches
on the front panel of the PDP-8/I. Switch
register entries are made by use of the Teletype
keyboard. The TSS/8 Monitor interprets a
properly coded teletype entry as a switch register input and allocates the data to a core
tral

location designated as the switch register for

the user program being executed.

Therefore,
an OSR instruction in the user program must be
handled in a different manner.

Programming of an HLT, IOT, or OSR instruction by the user program results in the inhibition of normal execution of the instruction and
the sending of an interrupt request to the central processor. Operation 's changed to the
executive mode and the TSS/8 Monitor processes the Instruction.

An HLT instruction in the user mode (UF (1)
high) causes the UINT flip-flop to be set and
the HLT instruction to be inhibited.

Blocking

of the HLT instruction is accomplished by use

INSERT signal present, the content of the program counter is incremented by one when it is
transferred to the memory address register at

of the UF (0) signal as an input to the

T4 time of the Fetch cycle with the result that

sheet 1).

AND

gate which resets the RUN flip-flop for an HLT
instruction (engineering drawing D-BS-8I-0-2,

ENGINEERING DRAWINGS

An IOT instruction (octal code 6XXX) in the
user mode (UF (1) high) causes the UINT flipflop to be set and the IOT instruction to be
inhibited. Blocking of the IOT instruction is

The engineering drawings for the KT8/I TimeSharing Option listed below are included in

accomplished by use of the UF (0) signal as an
input to the NAND gate which decodes the
instruction register bits and generates the IOT
and IOT signals (engineering drawing

this section.

It is

also necessary to consult the

block schematic diagrams for the Memory
Extension Control Option (D-BS-MC8I-0-1
1 and 2) and for the basic PDP-8/l
Computer (D-BS-8I-0-XX series) to follow the

sheets

D-BS-8I-0-3).

logic discussions in this publication.

An OSR instruction in the user mode (UF (1)
high) causes the UINT flip-flop to be set and

Drawing Number

Execution of the OSR instruction is blocked because

D-BS-KT8-I-1

KT8/I Time Sharing Option

D-FD-KT8-I-2

KT8/I Fetch Cycle

A-SP-KT8-I-4

Engineering Specification

the OSR instruction to be inhibited.
the UF (0) signal

NAND gated with signal

Title

OSR to generate the SR ENABLE signal (engineering drawing D-BS-8I-0-4)

Mil 5

TP3

\_Ma

B?4

SHOT

USF
-

TP2.E (FROM F25S2)*PC LOAD

fMM!
04

\NI

e<zs-

(FROM FZS5I )*

INITIALIZE

D BB5

+3V<ip3~)

IWT(|)

USF (0)
SKIP (<S)
+ 3V(Sf)
Ul

INITIALIZE

£_

S UF

3-«\l(655

Nil

(TO E27LI) *

SI
1

M2IS
C B8I5

SKIP OREO

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+ 3VC&51

MB 0T (0)

MB 08 C^)
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BEXT

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B041

RIB
F (0

MB. OS «)

MB 0<H

"B 06

(

Ml 13
J2

A.05

ME.05 (TO JI3V2) *

* MOTES

(I)

PINJ

MB 07 C0)

JI3UE
Fiqkll

ON PRIN/T AT LOCATION
61-0-10
8I-<ZH2

E27L.I

SI- 0-5

F25S2

BI-0-C
SI-0-G

F25SI

C-C
A -G
B-4
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D-BS-KT8-I-1

KT8/I Time Sharing Option

T«

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MB0 8

SKIP

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)

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THIS REPLA.CES TWE FETCH
CYCLE OF THE STMiJDAFLD
ST PRIMT 0-FD-SX-<2-i

D-FD-KT8-I-2

KT8/I Fetch Cycle

REVISIONS

REV

DESCRIPTION
ORIGINATED

A-SP-KT8-I-4

CHG NO
81-00025

ORIG

DATE
12/23/ i8

Engineering Specification

Sheet

APPD BY

DATE

tf.0

OVERALL DESCRIPTION
The KT8I option converts the PDP-8I for time sharing by:
A.

Adding means for interrupt

Adding four

Extending by one bit (in the memory extention
control type MC8I the instruction buffer (IB),
instruction field (IF) and the save field (SF).

new IOT's for control

(4)

1.0

GENERAL SPECIFICATION

1.1

Opterational Description
The instructions for HLT, OSR and IOT are modified
in "user mode" (UF=1) so the normal machine functions
are inhibited. The new function (only UF=1) is a
means of interrupt for the user. If the program is
the normal machine functions
in "executive mode" (UF=0)
for HLT, OSR and IOT are returned to normal. A JMS or
JMP transfers the contents of the user buffer (UB) to
Interrupt acknowledge or load
the user field (UF).
address (key) will transfer the user field (UF) to
save user field (SUF) and clear the UF and UB.
,

Restore memory field (RMF 6244g) loads the user buffer
(UB) with the contents of same user field (SUF).
1.2

Packaging
The KT8I option is part of the PDP-8I main framing wiring.

1.3

Environmental Specifications

1.3.1

Operating temperature

1.3.2

Noise Immunity

1.3.3

Power comsumption for the KT8I option modules are:

0° - 130°F

volt

+5 volts DC at 169 ma.

A-SP-KT8-I-4

Engineering Specification

Sheet 2

2.0

SPECIFICATION OF VENDOR-SUPPLIED EQUIPMENT
None

3.0

PROGRAMMING

3.1

IOT codes, mnemonics and description

MNEMONIC

OCTAL CODES

DESCRIPTION

CUF (Change User Field)

6264

Sets the User Buffer flip-flop
to a zero (state of ME-8). The
following JMP or JMS will
transfer the state of UB to
the user field.
EXECUTION TIME: 1.5 microsec.

CUD (Change User Field)

6274

Sets the User Buffer flip-flop
to a one (state of MB8)
The
following JMP or JMS will
transfer the state of UB to
the user field
EXECUTION TIME: 1.5 microsec.
.

CINT (Clear Interrupt

6204

Resets the User Interrupt flip
flop.
EXECUTION TIME: 1.5 microsec.

SINT (Skip on Interrupt)

6254

Causes the program to skip if
the User Interrupt flip-flop
is in the ONE state.
EXECUTION TIME: 1.5 microsec.

3.2

Test and/or Diagnostic
There are two (2) tests available for the KT8I options.
MAINDEC T8-D8A (KT08 Test) and MAINDEC T8-D8B (Systems Test

3.2.1

Requirements and procedures for MAINDEC T8-D8A (KT08 test).

A-SP-KT8-I-4

Engineering Specification

Sheet 3

3.2.1.1

Requirements
A. DF32 Disk
B.

3.2.1.2

Standard PDP-8I computer with KT8I time shared
option and type MC8I memory control.

Procedure
A.

Load MAINDEC T8-D8A using standard binary loader

Starting address is
Note:

2/2(08

During operation the switch register
should never equal zero and "JUMP to
self" is used for error conditions.

The program should halt at PC212s and PC2208The program will
Press continue in each case.
run for about five minutes and come to rest
(JUMP to self) at PC753 8
Program listing and write-up should be consulted
if more detail is required.
.

3.2.2

Requirements and Procedures

MAINDEC T8-D8B (System Test)
3.2.3

Requirements
Being developed.

A-SP-KT8-I-4

Engineering Specification

Sheet 4