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DEC-8I-H6MA-D

December 1970

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Document:	KV Graphic Display System Maint
Order Number:	DEC-8I-H6MA-D
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Pages:	116
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OCR Text

Equipment Corporation
Maynard, Massachusetts
Digital

PDP-8
Maintenance Manual

KV GRAPHIC
DISPLAY SYSTEM

^""^'

DEC-8I-H6MA-D

PDP-8

KV GRAPHIC DISPLAY SYSTEM
MAINTENANCE MANUAL

DIGITAL

EQUIPMENT

CORPORATION

•

MAYNARD, MASSACHUSETTS

APRIL 1970

The following are registered trademarks of Digital
Equipment Corporation, Maynard Massachusetts:

DEC
FLIP CHIP

DIGITAL

PDP

FOCAL
COMPUTER LAB

TABLE OF CONTENTS

Chapter

Page

GENERAL iNFORMATiON

1.1

General

1.2

Purpose of the Equipment

1-1

1.3

Basic System Description

1-1

KV Controller

1.3.1

1.6

1-1

1-3

1.3.3

1.3.4

Model 33 Automatic Send-Receive Keyboard

1-4

Options

1-3

1-4

1.4.1

Multiplex Interface Option

1.4.2

Type KVGT Graphic Display Unit
VS08 Storage Tube ControUer Interface

1.4.3
1.5

TypeVTOl Storage Tube Display Unit
The H306 Joystick Controller

1.3.2

1.4

1-1

Accessory Equipment
1.5.1

Hardware

1.5.2

Software

Specifications

1-4
1-4
1-4
I.5
I.5
I.5

2-5

INSTALLATION

2
2.1

General

2-1

2.1.1

Power Requirements

2-1

2.1.2

Space Requirements

2-1

Environmental Considerations
Unpacking
Modification Data
2.1.3

2.2
2.3

2.4

2.3.1

Computer

9^9

Stnrnoe Tiihp rUs^l^iv TTnit

2-2
2-2

2-2
2-2
^.O

Installation and Checkout

2-2

2.4.1

Installation

2-2

2.4.2

Checkout

2-3

OPERATION AND PROGRAMMING

Section

Operation

3.1

General

3-1

3.2

Operating Controls

3-1

Section II Programming
3.3

General

3.4

Display Capabilities

3.4

3.5

The Oscilloscope Display
3.5.1
The Addressable Coordinates
3.5.2
Visible Image Area

3-5

3.5.3

Line-Drawing Capabihties

3.5

3-5
3-5

TABLE OF CONTENTS (cont)

Page

Chapter

3.6

3.5.4

Circle-Drawing Capabilities

3-8

3.5.5

Point-Plotting Capabilities

3-9

3.5.6

Joystick and Cursor

Basic Machine-Language Programming
3.6.1

3.6.2
3.6.3

3.6.4

The KV Controller
JOT Instruction Format
Programming Techniques
Using the IDT Instructions

3-9

3-10
3-10
3-11
3-11

3-15

PRINCIPLES OF OPERATION

Section I

4.1

4.2

4.3

Operational Amplifiers

4.5

Idealized Operational Amplifier

4-1

4.1.2

Integrators

4-3

4.1.3

Scaling Adder

4-3

Field-Effect Transistors

4-4

4.2.1

General

4-4

4.2.2

Application

4-4

Sample and Hold

4-5

System Analysis
4-6

4.4.

Internal Digital Registers

4.4.2

Digital-to-Analog and Analog-to-Digital

4.4.3

Conversion Facilities
Analog Function Generator

Control Circuits
4.5.2

4.7

1 1

General

4.5.1

4.6

4-1

4.1.1

Section

4.4

Fundamentals of Operational Amplifiers

Input/Output Transfer Control
Skip and Interrupt Control Facilities

Timing Circuits
4.6.1
Load Data Timer
4.6.2
Execute Delay Timer
4.6.3
Long and Short Vector Timing Circuit
Digital-to-Analog and Analog-to-Digital Conversions
4.7.1

Digital-to-Analog Converter

4.7.2

Analog-to-Digital Converter

4-6

4-9
4-9

4-12
4-12
4-12
4-12

4-12

4-14
4-14

4-14

4.8

Sample and Hold

4-14

4.9

Integrators

4-18

4.10

Output Drivers

4-18

4.11

Modes of Operation

4-18

Point Mode

4-18

4.11.1

4-12

4.11.2 Vector Mode

4-18

4.11.3 Cursor Mode

4-21

Power Supplies

4-21

TABLE OF CONTENTS (cont)
Chapter
Page

MAiNTENANCE
Section

5.1

introduction

Warranty

c_,

5.1.1

Modules and Accessories

5.2

5.1.2

Shipping

r_2

5.1.3

Systems
Other Warranty Conditions

5.1.4
5.2

Service Policy

5.3

Maintenance Concept

5.2
5-2

'5.9

Section II System Maintenance
5.4

^.^

5.6

5.7

Preventive Main'
Maintenance

5.3

5.4.1

General

5.4.2

Mechanical Inspection

5.3

5.4.3

Diagnostic Testing and Minimum Performance Tests

5.3

5-3

xiuuuic rtaiaiysis
5.5.1

Power Supply

5.5.2

Analog Faults

5.5.3

Joystick Controller

5.5.4

Component Part

c ^

5.4
5-4
5.4
5.5

Alignment and Adjustment
5.6.1

Preliminary Instructions

5.6.2

Test and Adjustment

5.5
5.5
5.5

Repair and Replacement

5.^!

REPAIR PARTS LISTS

DIAGRAMS

LIST OF ILLUSTRATIONS

Title

Figure

Type KV Graphic Display System
1-1

1-2
1-3

1-4
1-5

2-1

3-1

Page
viii

KV Controller, Simplified Block Diagram

1-2

TypeVTOl Storage Tube Display Unit
Type H306 Joystick Control

1-3

Type ASR'33 Teletype Keyboard
Type KVGT Graphic Display Unit
Storage Tube Display Unit Overall Dimensions and
Location of Remote Programming Connector
Storage Tube Display Unit VTOl, Location of

1-4

1-3

1-4

2-1

Controls and Indicators

3-2

Effective and Visible Image Areas

3-5

3-3

Specification of Start and End Linear Vectors

3-6

3-4

Specification of Center, Start and Circumference of
3-8

Circular Vectors

3-12

3-5

Basic lOT Instruction Format

3-6

Typical Coordinate Reference System for Machine

3-7

3-8

Language Programming
Basic Data-Word Format
Basic Parameter-Word Formats

4-1

Basic Operational Amplifier, Idealized

4-2

Integrator, Basic Configuration

4-3

Scaling Adder, Basic Configuration

4-3

4-4

Typical KV Controller, PET Switching Circuit With Driver

4-5

Sample and Hold Register, Simplified Schematic Diagram
KV Controller, Functional Block Diagram
lOT Control Circuit, Logic Diagram
lOP Timing Diagram
Load Data Timer (LDT), Simplified Logic Diagram
Execute Data Timer, Long/ Short Vector and Vector Continue Timing
Circuit, Simplified Logic Diagram

4-6

4-6
4-7

4-8
4-9

4-10
4-1

3-15

3-16
3-17

4-13
5-1

4-11

4-13
4-15

Digital-to- Analog/ Analog-to-Digital Converter,

4-17

Functional Block Diagram

4-12

4-7

4-10

Sample and Hold Register Input Buffer, Simplified
Schematic Diagram
Analog Function Generator In Circle Mode Configuration
and Circle Generation Geometry
Digital-to- Analog Converter and Gate Logic Module/Analog

4-18

4-19
5-5

5-4

Function Generator Module Interface
Circle Mode Zero and X and Y Sample/Hold Zero Adjustment Display Pattern
Circle Mode Rate, Adjustment Display Pattern
Stroke Timing Generator, Adjustment Display Pattern

5-5

Absolute Vector, Adjustment Display Pattern

5-8

5-6

Circle Mode Center Gain, Adjustment Display Pattern

5-8

5-7

Point Mode Zero, Adjustment Display Pattern
Short Vector Gain, Adjustment Display Pattern

5-9

5-2

5-3

5-8
5-9

... 5-7
5-7
5-7

5-9

Digital-to- Analog Converter and Gate Logic Module A612,

5-14

Adjustable Parts Location Diagram

LIST OF ILLUSTRATIONS (cont)

Figure
5- i

Title

Page

Analog Function Generator Module A3 1 2, Adjustable
Parts Location Diagram

5-1

6-1

6-2

Timing Generator Module M7

5.J5
2, Adjustable Parts

Location Diagram
Timing Generator Module M712, Parts Location Diagram
Digital-to-Analog Converter and Gate Logic Module A6 1

5_ j g

6-2

Parts Location Diagram

5.5

6-3

Analog Function Generator Module A3 1 2, Parts

6-4

Voltage Regulator Module, Parts Location Diagram

5.IQ
6-13

7-1

Timing Generator Module M7 1 2, Schematic Diagram
M712-0-1

7.3

7-2

Digital-to-Analog Converter and Gate Logic Module A3 1

Location Diagram

Schematic Diagram, A6 12-0-1
7-3

.7.5

Analog Function Generator Module A3 1 2, Schematic Diagram
A312-0-1
VoltageRegulatorModule A7 12, Schematic Diagram, A7 12-0-1
'

7-4
7-5

General Wiring Sheet for KV8I Modification, KV8I-0

7.7
7-9

.7-11

'-U

JVV81 L/ispiay <^ontroi, Kvjsi-u-u

7-7

KV8I Control Logic, KV8I-0-2

7-8

Module Utilization KV8I, KV8I-0-3

7-9

General Wiring Sheet for KV8I, KV8I-0-5

7-10
7-1

KV8I Display Acceptance Procedure, KV8I-0-6
Performance Specifications for KV8I Controller and
VTOl Display, KV8I-0-7

7.23

7-12

Joystick Control Assembly, H306-0-0

7-25

7.I3
1-\S

....'.'.'.'.'.'.'.'.'.'..

l-Vl
l-\9
7-21

LIST OF TABLES

1-1

2
2-1
3.1

Page

Title

Number

Accessory Hardware Complement
Accessory Hardware Required but not Supplied

l'^

PDP-8/I Modification Wiring List
Function of Controls and Indicators, Graphic Display System

2-3

1-5

3-3

Type KV Controller Instruction Set

3-12

Table of Absolute and Relative Coordinates for Figure 3-6
Analog Function Generator, Input/Output Signals

3-16

Analog Function Generator Digital Control Signals
X or Y Sample and Hold or Integrator Calibration Tests
X and Y Sample and Hold and Integrator Drift Rate
Adjust Routines Using Reset and the CRT
Analog Function Generator and Timing Generator

4-10

Adjustment Routines

5-12

5-4

Starting Addresses

5-12

5-5

Function of Gain and Centering Potentiometers
Function of X and Y Absolute Zero and Absolute Gain

3-2
3-3
4-1

4-2
5-1

5-2

5-3

5-6

4-9

5-11

5-12
5-12

Potentiometers

Function of X and Y Point Mode Zero and Gain Potentiometers
Function of X and Y Short Vector Gain Potentiometers
Function of Gain and Centering Potentiometers

5-13

6-2

Switch Positions for Visual Check
Repair Parts Cross Reference List
Timing Generator Module M7 12 Repair Parts List

5-13

6-3

Digital-to- Analog Converter and Gate Logic Module A6 1 2,

5-7
5-8
5-9

5-10
6-1

5-13
5-13

6-1

6-3

6-7

Repair Parts List
6-4

Analog Function Generator Module A3 1 2, Repair Parts List

6-11

6-5

Voltage Regulator Module A7 12, Repair Parts List

6-13

7-1

List of Diagrams

7-1

INTRODUCTION

Graphic Display System manufactured by
This publication covers maintenance instructions for the
the Digital Equipment Corporation, MaynardJVIassachusetts. The instructions in this manual are directed
to the basic configuration of the system (KV Controller, the VTOl Storage Tube Display, and the H306
Joystick Controller) and its implementation into the PDP-8, 8/1, 8/L, 8/S, 12 and LINC processor.

This manual is intended for use by personnel responsible for installation and maintenance of the
Graphic System and is arranged into the following seven chapters:

Chapter 1 — briefly describes the system and its

amplifiers and other circuits is provided to aid in

the understanding of the operation of the

general specifications.

controller.

Chapter 2 — contains instructions for inspecting,
installing, performing preliminary checkout and

Chapter 5 — contains maintenance instructions
for the equipment. Included in this chapter are
waiTanty and service policies of the Digital

adjusting the equipment.

Equipment Corporation and alignment and adpreventive and corrective mainten-

Chapter 3 — contains a description of the operaiiiig

^./Uiitiuib

justm.ent,

aiiU inUn^aiOia aiiu piOVAuea tiie

ance, and repair and replacement instructions.

instruction set, along with sample programs, for

programming the system.
Chapter 6 — lists and locates each of the replaceable parts of the KV controller to facilitate
repair parts procurement for the equipment.

Chapter 4 — contains a functional block diagram
KV controller together with a

discussion of the

detailed circuit analysis of each of the individual

Chapter 7 - contains the necessary' engineering
drawings to assist in the performance of mainte-

functional circuits that comprise the basic controller. In addition,

a discussion of operational

nance tasks.
Related Documents
Publication No.

Title

PDP-8/I

Maintenance Manual

PDP-8

User's Handbook

DEC-8I-HR1A-D
DEC-8I-HR2A-D

Maintenance Manual

F-87

PDP-8/L

User's Handbook

PDP-8/S

User's Handbook

F85S

Maintenance Manual

F-875

PDP-12

User's Handbook

DEC-12-GRZA-D

LINC-8

User's Handbook

Maintenance Manual

F-L85P
F-L87

Storage Display Unit

Type 611, Tektronix

Instruction Manual

(Modified)

VTOl

Vll

Type KV Graphic Display System

bnMpicii

GENERAL INFORMATION

1.1

cross section of a beam can immediately reveal
its ability to withstand a given load, and a

GENERAL

KV Graphic Display System (consisting of the KV controller, the VTOl Storage

change in the value of a resistor can immediately
demonstrate the relative stability of an electrical

Tube Display Unit, the optional H306 Joystick
Controller, and associated cabling as shown in

circuit.

the frontispiece) may be used with a PDP-8, 8/1,

1.3

The

basic

1 2 or LINC computer. The system can
expanded
to a multi-terminal (up to eight
be
display units on line) with the addition of the
Multiplex Interface Option and VT02 Storage
Tube Display Units with keyboards.

8/S, 8/L,

1.2

PURPOSE OF THE EQUIPMENT

BASIC SYSTEM DESCRIPTION

The basic KV Graphic Display System, shown in
Figure 1-1, consists of a Type KV Controller, a
VTOl Display (Modified Tektronix Type 611
Storage Display Unit), a Type H306 Joystick
Control (that permits the user to locate a visual
nonstored spot or cursor anywhere on the usable
image area of the display), and a Teletype Model

Automatic Send-Receive (ASR-33) Keyboard, all working into an 8-family, LINC or
33

Common applications of computer graphic display systems permit immediate solution of a

broad range of electrical, physical, and mechanical design and analysis problems. While there can

be little doubt about the value of the computer
in solving complex design problems, the graphic
display system accelerates the exchange of data

between the user and the computer. Visualwhether it be a simple
curve that displays the interaction of two vari-

ization of a problem,

ables or a

PDP-12 Central Processor. Software includes a
64-character (ASCII-compatible) symbol generator,

general-purpose

text

editor, a graphics

interactive programming system called EDGRIN
(for EDitor with GRaphic INterpreter), and a

cursor reading subroutine that can be used to
the position of the joystick-generated

define

cursor upon command of the user.
1.3.1

KV Controller

complex network synthesis, permits

define a point outside a curve can be immediate-

The basic KV Controller, shown in Figure 1-1,
consists of the four modules: (1) Type A712
Voltage Regulator, (2) Type M7 12 Timing Generator, (3) Type A612 Digital-to-Analog Con(4) Type
verter and Gate Logic Module and
These
modGenerator.
Function
A3 12 Analog

ly displayed as irrelevant data, the change in the

ules are described in the subsequent paragraphs.

rapid

selection

new

parameters. Graphical

output permits the user to create a visual model
of an electrical, hydraulic, mechanical, or other
system while the computer operates on its mathematical counterpart. Thus, parameters that

1-1

COMPUTER
I/O

X OUT

BUS

MEMORY

AC BITS

BUFFER BUS

7-11

=0
I0P'S(I,Z,4)

SKIP

TIMING
GENERATOR
M7I2

COMPARATOR
OUT
I

INTERRUPT

GATING
SIGNALS

OT CONTROL
SIGNALS

DIGITALTO-ANALOG
CONVERTER
AND GATE
CONTROL
MODULE

X OUT

STORAGE
TUBE
DISPLAY

A3I2

UNIT

—YOUT

D/A OUTPUT

A6I2

VTOI

ANALOG
FUNCTION
GENERATOR
•

7T
Y OUT

AC BITS 2-1

SCOPE CONTROL SIGNALS

CURSOR
INTERRUPT

JOYSTICK
CONTROL
H306

X AND Y CURSOR

d^ DIGITAL SIGNALS
-*- ANALOG SIGNALS

Figure 1-1.

KV Controller, Simplified Block Diagram

Type A712 Voltage Regulator Module

Type A612
Gate Module

Digital-to-Analog

Converter and

The A712 module converts 60-cycle power to
±11.5 volts which is used by the
modules in the controller. Primary a-c power is
supplied to the module by a step-down transformer which must be installed onto the CPU
main frame. Other do voltages required by the
KV controller are supplied from the CPU.
regulated

This module contains a digital-to-analog converter

(D/A) which converts a 10-bit word to a dc

analog signal ranging from

to -4 volts. Included

the D/A is a comparator which permits
program controlled analog-to-digital conversions
in

to locate

the position of the joystick in the

cursor mode. This module contains four controls

Type M712 Timing Generator Module

for adjustment of the comparator. The module
also

This module decodes the input lOT instructions

from the computer and generates system timing
signals

machine

synchronism

with

the

computer

cycle. This module has an internal
adjustment that controls vector stroke timing.

1-2

contains

the

input

data buffer, which
from the computer,
and generates gating signals which are applied to
the A3 12 Analog Function Generator module.
These gating signals establish analog signal paths;
receives data-word inputs

hence, the mode of operation of the system.

Type A312 Analog Function Generator
The Type A3 12 Analog Function Generator
receives 10 gated outputs and the analog output

of the D/A from the Type A612 D/A converter.

The gating signals establish the permanent signal
paths of the module. The module converts the
analog output of the D/A to the appropriate X
and Y deflection voltages for the VTOl display.
This module contains 22 controls for adjustment

of point, vector, and chcle patterns on the VTOl
display.

1.3.2

Type VTOl Storage Tube Display Unit

The Type VTOl Storage Tube Display Unit
(Figure 1-2) is a modified Tektronix Type 611
Storage Display Unit that is driven by the
output signals from the KV Controller. The
VTOl Storage Display Unit contains a Type
T6110 bistable direct view storage tube, which
has an aspect ratio of 3/4 and which measures

16 X 21 centimeters (6-1/2 x 8-1/4 inches). The
V4.^D^xCLjr

xl-O-iS

J.\/U\J±I^^X\J±1.

^-'J.

T^\yO

horizontal stored line pairs.

y WJ. kJ-WdX

lX±l\^

^\J\J

Two front panel

Figure 1-2.

Type VTOl Storage Tube Display Unit

pushbuttons allow the user to select either a
VIEW or an ERASE mode.

An additional mode that is utilized by the KV
Controller

vwite-through

the

write-through

mode of

operation

mode.
is

The

used to

locate and position the cursor with the

Type

H306 Joystick Controller. When the cursor is
moved, the small generated circular spot will not
be stored by the display nor will it destroy
previously stored information.
1.3.3

The H306 Joystick Controller

The H306 Joystick Controller (Figure 1-3) is the
means by which the user can interact directly
with the graphical or text information presented

by the system. The joystick is used to position
the cursor anywhere in the effective image area
of the display. The joystick output produces
two analog voltages corresponding to the X and

Y position coordinates (address) of the cursor.
The coordinate addresses
computer, when
button.

are

read

into

the

commanded by the interrupt

A successive approximation program

together with the digital-to-analog ckcuits of the

KV Controller produce a digital representation
of the cursor position in the accumulator of the

computer.

Figure 1-3.

Type H306 Joysticl< Control

1-3

1.3.4

Model

Automatic

Send-Receive

Keyboard

The Teletype ASR-33 keyboard (Figure 1-4) is
the means by which the user enters the digital
data into the computer. The keyboard is the link
between the user, the display and the computer.
Commands entered into the computer through
operation of the keyboard are processed by the
computer and stored as data, or perform some
manipulation of the viewed display.

1.4

OPTIONS

1.4.1

Multiplex Interface Option

The KV Graphic Display System can also accommodate a multiplex interface option (which
consists of an eight-channel multiplexer module
and a line driver module) that permits up to
eight

remote graphic display consoles to be

operated in a time share mode through a single
KV Controller. The multi-terminal Graphic Dis-

System combines the assemblies of the
basic KV Controller and up to eight VT02

play

Figure 1-4.

Type ASR-33 Teletype Keyboard

Figure 1-5.

Type KVGT Graphic Display Unit

graphic terminals.

1.4.2

Type KVGT Graphic Display Unit

The KVGT Graphic Display Unit (Figure 1-5) is
a complete remote station consisting of a VTOl

and a keyboard which includes the appropriate
interface

logic.

systems,

The KVGT,

multi-station

used with the multiplex interface

option exclusively.

1.4.3

VS08 Storage Tube Controller Interface

The VS08 Storage Tube Controller Interface
provides

location

for basic

KV Controller

modules in a half-rack of logic circuitry together
with a suitable power supply and interface modules to permit operation of the KV Graphic

System with the PDP-8, PDP-8/S and LINC

Computer

Systems.

The multiplex

option can be added to the
that up to eight remote

interface

VS08 interface so

KVGT graphic terminals

can be on line in a multi-terminal system.

1-4

1.5

ACCESSORY EQUIPMENT

supplied,

Each KV Graphic Display System is shipped
with an accessory complement including both
hardware and software. The hardware and software complements are described in the subsequent paragraphs.

aiiu iiiaiiiidlll llic bySLCIIl.

1.5.2

Software

The type KV software complement is listed in
Chapter 7.
1.6

1.5.1

Hardware

Table

1-1

but should be available to properly

iiidiciii

SPECIFICATIONS

The specifications covering the KV Controller
lists

the tools that are suppUed with

KV Controller. Table 1-2 lists tools that are not

are Hsted in detail in Chapter 7. (Refer to Table
7-1 for page location.)

TABLE 1-1. ACCESSORY HARDWARE COMPLEMENT
Name

Type

Double Module Extender

W983

Qty

Purpose

Used to gain access to contacts or
components on modules during alignment and
maintenance.

Al:

Bourns

Use to access potentiometers for adjustment.

TABLE 1-2. ACCESSORY HARDWARE REQUIRED BUT NOT SUPPLIED
Name

Type

Wrapping Tool

H811

Unwrapping Tool

H812

Qty

Purpose

Used to wire-wrap terminals of module
connectors during maintenance or repair.

Used

unwrap

connectors

terminals

during

module

maintenance

repair.

1-5/1-6

CHAPTER 2
INSTALUTION

GENERAL

2.1

2.1.2 Space Requirements

This chapter covers installation of the Type

Graphics Display System. Instructions are provided

for

unpacking,

transformer installation

and wiring, installation of modules and system
The instructions are based on the
assumption that the entire modification and

intercabling.

installation
facility.

will

take place at the customer's

In cases where this is not true, disregard

those instructions that are not applicable.

2. 1

Adequate space should be provided to permit
access to the computer and VTOl for maintenance.

The outline dimensions of the VTOl are

shown in Figure 2-1. (Refer to the applicable
computer User's Handbook for computer dimensions.) The equipment should be arranged so
that the display unit is clearly visible and the
computer console, teletype and Joystick Controller are readily accessible to the operator.

Power Requirements
FRONT
f'^X^-'

Controller

-^^

— The controller operates from the

»v,

\^21.75"

115-volt, 60-Hz, single-phase fan power bus of

the computer. Internal power supplies provide

+11.5 ±1 and -11.5 ±1 volts dc, each at 100 mA.
Additional +5 volts at 395

mA and -15 volts at

mA are supplied to the controller from the
50"

11.

power supplies of the computer.

VTOl -The VTOl operates from a

25-PIN CANNON

115-volt,

60-Hz, single-phase source. For 230-volt operation, refer to the Tektronix 61 1

Joystick Controller

CONNECTOR
IKtMUIt
PROGRAMMING)

BACK

11.50

manual.

~ The Joystick Controller

operates from the +11.5- and -11.5-volt power

supply of the controller.

Figure 2-1. Storage Tube Display Unit Overall Dimensions

and Location of Remote Programming Connector

2-1

Environmental Considerations

2. 1 .3

environment
ranging in temperature from 10° to 40° C (50°
to 104°F) with a maximum temperature deviation of ±3°C (±5°F). The humidity at the

The

controller

operates

installation must not exceed

use a computer that has not been factory wked
for the controller. The modification consists of

mounting and wiring the Triad 9 IX step-down
power transformer and wiring of the option
panel. Perform the following modifications, as
required:

70%. (Refer to the

VTOl instruction manual for environmental con-

NOTE

siderations for the VTOl.)

Refer to Chapter 7 for location of

module

UNPACKING

2.2

compartment

associated wiring

list

connectors,

and for trans-

former mounting instructions.

unpack the equipment and ascertain
that the appropriate items have been supplied
Carefully

and that no damage was incurred in shipping.

The following items comprise a typical Type KV

a. Align the transformer mounting holes with
the holes in the fan housing and fasten with

Graphics Display System:

hardware provided.

— Programmed Data Processor and Main-

tenance Manual

Connect transformer leads in accordance

with the wire list of Table 2-1 using Hand Wire

- Type VTOl

Storage Display Unit and

Wrap Tool.

Instruction Manual

- Type H306 Joystick Controller (optional)

~ 20-foot Dual I/O Cable Assembly (Part

2.3.2 Storage Tube Display Unit

No. D-IA-7 006289-0-0)
1

- Type A712 Power Supply Module

- Type M7 1 2 Timing Generator Module

The Storage Tube Display Unit modification
alters
fiers

the write-through and deflection amplito reduce phosphor burnout and noise

hazards.
1

- Type A612 D/A Converter Module

-Type A3 12 Analog Function Generator

2.4

INSTALLATION AND CHECKOUT

Module
2.4.1
1

- Triad F91X Power Transformer

— Alignment Tool

- Type W983 Module Extender

Installation

Install the Type

2.3

Check the voltage and range selectors at

the rear of the VTOl and set them, if necessary,
to agree with the Une voltage source.

MODIFICATION DATA

2.3.1

Computer

The computer modification procedure is applicable to

2-2

KV Display System as follows:

KV Graphics Display Systems that will

the module cover from the
Check
the wiring runs associated with
PDP-8/I.
the Triad transformer mounted on the fan housing for physical damage. If no damage is found,
b.

Remove

TABLE 2-1. PDP-8/I MODIFICATION WIRING LIST
Wire Color

From

Blk/Wht

Fan Pwr AC

Xfmr Primary

AC Input

Blk/Red

Fan Pwr AC

Xfmr Primary

AC Input

Grn

H21N2

Xfmr Secondary

AC Output

Yel

H21F2

Xfmr Secondary

AC Output

Red

H21R2

Xfmr Secondary

AC Output

plug the A712 power supply modules into location

H21 and power up the computer. Using a

voltmeter or oscilloscope check for +11.5 ±1
volts

dc at H21-U2 and -11.5 ±1 volts dc

H2 -K2. Turn off the computer.
1

Function

produce a clear, well-defined display. Excessive
beam, current m.ay cause either a bright

bum

condition or, if intense enough, a more serious

dark bum condition. A bright bum condition is
the appearance of a residual display image after

bum images can be erased by
OPERATING LEVEL control to

erasure. Bright
c.

Place VTOl in a convenient location to the

adjusting the

CPU and teletype and within the limits of the

establish

Dual I/O Cable Assembly. The H306 Joystick

required for a fade-positive condition to effect a

Controller is placed beside the

VTOl either to

the left or right side depending on the operator.

fade-positive

condition.

The time

complete erasure is dependent on the severity of
the bum.

A severe burn may require up to 12

G778 module end of the Dual I/O

hours for complete erasure. Operate the instru-

Cable into location J21 and route the cable to

ment in the fade-positive mode only as long as

CPU, teletype and VTOl so as

necessary, since in addition to the loss of useful

not to interfere with the operator. Plug the can-

operating time, extended fade-positive operation

non connector into the remote program connector located at the rear of the VTOl. Plug the
7-pin ampucnui CunncCuji iniu uic uaCK ui inc

will decrease the life

H306 Joystick Controller. This completes the

beam current. This condition is evidenced by a

Plug the

the back of the

dark burn condition
i^aiiiuuc

lay

expectancy of the CRT. A
is the destmction of the

uuOe piiuSupiiui

uic iiiuciiaivc

spot or area that will not react to the writing

cable connections.

As with a conventional CRT, the only
remedy for this condition is replacement of the

gun.
d.

Install

the

remaining modules in

their

proper compartment locations.

2.4.2

Checkout

VTOl Operating Precautions
To prolong the useful life of the cathode ray
tube, observe the following precautions when
operating the equipment.

Adjust the

cathode ray tube.

DRIVE control for the mini-

mum writing gun-beam current level that will

Erase the display when the information is

no longer needed. If a display is left on the CRT
for an extended period of time, it can cause a
residual image that may appear as a negative
image of the erased display or a positive image
superimposed on the new display. Whether the
image appears positive or negative will depend
on the brightness level of the image phosphor as

compared to the brightness level of the new
display's background phosphor. The residual
image may be erased by establishing a fadepositive condition.

2-3

NOTE

VT01 Set-Up

Storage capability and resolution are
by the interaction of the

This procedure positions the front panel controls prior to the application of power.

affected

Preliminary Instructions

OPERATING LEVEL, WRITING INTENSITY and FOCUS control
settings.

Disconnect all external signal cables from

the rear panel connectors.
d.
b.

Set the front panel controls as follows:

OPERATING LEVEL control pro-

The

adjustment of the Storage Target BackThe procedure for this adjustment is given in Chapter 3 of the Tektronix

vides

plate potential.

POWER

OFF

WRITING INTENSITY

CCW

OPERATING LEVEL

Do not change the

Manual.

Pull the

TEST SPIRAL switch to its FO-

trol.

CUS position. A spiral waveform should appear
on the display. Adjust the FOCUS and WRITING INTENSITY controls for an overall clear,

FOCUS

Midrange

well-defined

TEST SPIRAL

NORMAL

setting of this con-

display

the

desired

viewing

brightness.

Ensure that the rear panel VOLTAGE and

RANGE

selectors

are

set

to the appropriate

power source and
positions
then connect the power cord to the power
for the

available

Push and hold the TEST SPIRAL switch to
STORE position for about 3

spring-loaded

its

seconds

until

stored

spiral

waveform

source.

appears on the display. The stored spiral should
remain clearly visible for about 60 to 90

VT01 Energizing Procedure

seconds, then appear to be almost erased as the
VIEW switch is illuminated. An illuminated

Turn

the POWER

switch

ON. The

ERASE switch should illuminate and as the instrument warms up, the display area of the CRT

VIEW switch indicates that the instrument is in
a holding mode of operation.
g.

Press

and

release

the illuminated

VIEW

should assume the bright luminance of a fade-

switch. The stored spiral should again appear on

positive condition.

the display and the VIEW switch should be extinguished. The instrument should remain in this

Press and release the

ERASE switch. The

instrument should cycle through an erase func-

condition for about 60 to 90 seconds and again
assume a holding mode of operation.

tion and assume a ready-to-write condition. The

display should appear to be at a uniform lumi-

nance level, much lower than the brightness level
of the fade-positive condition.

Press

and release the ERASE switch. The

instrument should cycle through an erase function and assume a ready-to-v^rite condition. This

completes the instrument-energizing procedure.
c.

Slowly turn the

WRITING INTENSITY

control in a clockwise direction while observing
the display for the indication of a bright spot. If

Type KV Graphics Display System Checkout

a bright spot appears, immediately turn the control

counterclockwise.

the control

can be

turned fully clockwise without a spot appearing,
this test of the instrument operating condition is

and load and run the
MainDEC diagnostic self test routines. Perform
Refer to

the

Chapter

alignment

and

adjustment

procedure

normal. Set the WRITING INTENSITY control

contained in Chapter 5 to the extent required to

to midrange and proceed.

align the system.

2-4

GHAPTEP 3
OPERATION AND PROGRAMMING

This chapter is divided into two sections which provide operation and programming instructions for the

Graphic Display System described in this manual. With the exception of oscilloscope adjustments and
joystick manipulation, there are no special operating procedures described in Section I. The techniques
for programming described in Section II are at the machine-language level. Source level programs are

generated using EDGRIN, a special source-language assembler that simplifies the work of originating a
graphic display. EDGRIN commands deal almost exclusively with input-output program modifications,
line

and text display, compilation and execution of programs written in the EDGRIN language. This

language gives EDGRIN the properties of an editor, compiler and operating system.

SECTION I

OPERATION

3.1

GENERAL

With the exception of some VTOl Display adjustments, required prior to operation, and the

MAINDEC

diagnostic

routines,

described

on the computer console and certain adjustments at the KV Controller modules must be
made. Switches and controls on the VTOl
Display are shown in Figure 3-1.

Chapter 5, there are no special operating procedures for the graphic display system. Operation

of the

VTOl

Display and the

3.2

OPERATING CONTROLS

H306 Joystick

Cursor Control (with the exception of manually

Visible on the VTOl Display front panel are two

and a program
determined entirely by the KV
Controller and the source program. However,
during maintenance checkout, certain controls

pushbuttons; below these pushbuttons is a panel

selected

coordinate

interrupt),

positions

door which, when opened, exposes the power
switch and five vernier controls. The functions
of these controls are described in Table 3-1.

3-1

Figure 3-1. Storage Tube Display Unit VT01, Location of Controls and Indicators

3-2

TABLE 3-1. FUNCTION OF CONTROLS AND INDICATORS,
Index

Name

Not
Shown

ERASE pushbutton

Function

Used to delete

all

stored information from the

storage tube (oscilloscope),

NOTE
The VTOl display has a hardware
safety feature that controls the
intensity of the display. When an

image has been displayed for 90
seconds, and no additional information has been added to the
display, this device reduces the

of the display. Thus,
appears to vanish;

intensity

the

display

however,

this

reduction in the

no
on the information stored

intensity of the display has
effect

on the oscilloscope image area.

Not
Shown
1

VIEW pushbutton

Used to restore the display to full intensity for a

new 90-second period.

INTENSITY control
(outer concentric)

Used to adjust the intensity of the writing beam
during normal writing functions.

Write-Thru

Used to adjust the intensity of the writing beam

INTENSITY control

during write-thru writing functions.

(inner concentric)

FOCUS control

Used to obtain a sharply defined writing beam.
This

switch

used

conjunction

with

the

TEST SPIRAL pushbutton (6).

OPERATING LEVEL

Used

control

oscilloscope.

stallation,

adjust

the

This

storage

control,

properties

adjusted

of the

during

in-

does not normally require a change in

setting.

POWER switch

Used to energize the Storage Display Unit.

TEST SPIRAL

Used to change the oscilloscope circuits from a
normal operating configuration to either of two

pushbutton

test

configm"ations.

The test positions are Store

and Focus.

3-3

TABLE 3-1. FUNCTION OF CONTROLS AND INDICATORS,
GRAPHIC DISPLAY SYSTEM (cont)
Index
No.
6

Function

Name
When

Normal

the

TEST SPIRAL pushbutton is in its

center position, the oscilloscope circuits are con-

(cont)

figured for normal operation.

When the TEST SPIRAL pushbutton is depressed

Store test

and held in for one second or longer, a stored spiral
waveform should appear on the oscilloscope. This
spiral waveform should remain intensified for
between 60 and 90 seconds whereupon the VIEW
switch will light and the displayed image will
appear to be erased.
illuminated,

When the VIEW switch is

the oscilloscope will enter

VIEW

mode. Depressing the

switch

its

store

again will

restore the spiral image.

When the TEST SPIRAL switch is pulled out to its

Focus test

waveform should
appear on the oscilloscope. The FOCUS control
should then be adjusted for the sharpest image on

focus

test

position,

spiral

the display.

Not
Shown

Not

TYPE H306 JOYSTICK

When depressed, a software routine automatically

CONTROLLER INT

places the digital equivalent of the coordinate value

pushbutton

of the cursor position in the PDP-8/1 accumulator.

Joystick control

This control can be moved in two axes. Its position
defines the position of a spot, called a cursor, on

Shown

the image area of the oscilloscope.

SECTION

PROGRAMMING
3.3

GENERAL

Graphic Display System. Also, simple display
routines are given as samples.

The descriptions in this section are addressed to
machine-language programming requirements
and acquaint maintenance personnel with the
controller instruction-word set. Parameter and

3.4

DISPLAY CAPABILITIES

data-word formats are described so that simple
machine-language programs can be compiled for

The

KV Graphic Display System, which com-

four

the purpose of testing and checkout of the

3-4

prises the controller

primary

and the VTOl display, has
capabilities and a

line-drawing

text generation capability.

software-controlled

source language, the parameter words are prede-

termined through programmer selected ASCII
characters by the EDGRIN assembler. The XStraight Lines

and Y-axis coordinates, however, are exnumbers by the programmer
numbers by EDGRIN.
binary
but assembled as
axis

Circles

pressed as digital
d. Arcs

b. Points

3.5.2 Visible Image Area

THE OSCILLOSCOPE DISPLAY

3.5

The visible image area of the display oscilloscope
The oscilloscope display (or image) area (Figure

normally used when defining a coordinate

divided into a square four-quadrant rectangular coordinate system whose effective area

position.

limits are ± 512 decimal (1000 octal) units along

Any definable point between the visible image

3-2)

both the X and Y axes (this is approximately 85
decimal (125 octal) units/linear inch). Of this
effective area, the visible image-area limit along
the X-axis is ± 256 decimal (0400 octal) units;

along

the

Y-axis

visible

limit

± 320

decimal (0500 octal) units.

3.5. 1

Any

image area
area

definable

point

the visible

considered as the hardware limit.

and the effective image area (shaded area.

Figure 3-2)

considered a software limit. All

addressable coordinates should

lie

within the

image area unless origin shifting, scaling,
or light button features of EDGRIN are used.
Origin shifting, scaling, and light button features

visible

of programming are described in the EDGRIN
Programming Manual and are beyond the scope

The Addressable Coordinates

of this publication.
.(-111

\^V^V1 VJXllCl LV/O

£ii

their displacement

V//^J^J.

vuOvw*

^*.%r^^vj.

^^^

^^i ^^^x

from the origin or with re-

3.5.3

Line-Drawing Capabilities

spect to the last program-named coordinate position.

Any point within the image area must be

defined by both

X-axis and Y-axis coordi-

its

with the X-axis coordinate always expressed first. If the desired position of a coordinates

nate

given as absolute,

its

displacement

The

KV controller draws lines on the oscillo-

scope screen through a linear vector stroke that
is generated by the controller analog function
generator module. Depending on whether the

taken from the origin. If the desired coordinate
position for either axis is expressed as relative,
its

displacement

taken from the last named

position for that axis.
In machine-language programming the characteristics of the desired graphic form, such as point,
line,

arc, or circle,

must be specified together

with the X- and Y-axis coordinates that locate
the position of the line form in the display.

These requirements are met by two distinct
word formats that are used to define the characteristics and the coordinates; the parameter
defines the desired line form characterthe data word locates the X- and
and
istics
Y-position coordinates of the line form. In this
description, both parameter and data words are

word

expressed as octal numbers, but are written into
the accumulator or memory registers of the

computer and the registers of the controller, as
binary numbers. When using EDGRIN as the

Figure 3-2. Effective and Visible Image Areas

3-5

starting and end-point coordinates for the linear

to be generated are referenced to the
origin or to the last named coordinate positions,

stroke

the stroke generation format

320

expressed as

absolute, or relative, respectively.
RFI

Linear Vectors

AX
^

Parameters that define a wanted linear vector are
1

short or long, relative or absolute, and intensified (visible) or unintensified (invisible).

VECTOR 2

\INTENSIFIED-.

Such
,

coordinate location and an end point which can

VECTOR

NOT

/ INTENSIFIED

be specified in either absolute or relative mode

and are executed in either a short or long
format. The vector can be drawn visible or
invisibly between the given starting point and
specified end point.

linear vectors are always drawn between a given

The end-point coordinates may be

REL

-h-

ABY

ABX-

0,0^

+256

Figure 3-3. Specification

specified

Start

and

End Linear

Vectors

relative to the given starting point coordinates

by specifying the relative mode and sequentially
entering the X and Y coordinate positions,
which define the incremental displacement (AX
and AY) of the line along the X- and Y-axes
(Figure 3-3), into the X and Y sample and hold
registers (XSH and YSH, respectively) of the
controller.

The end-point coordinates may also

be entered absolutely (with respect to the origin)

by specifying the absolute mode and

se-

Figure 3-3 shows two linear vectors: vector

which

illustrated

as the

dashed line, has its

starting point at the origin

tensified

(invisibly).

and is drawn uninThe coordinates of end-

point A of vector 1 are (85,255). This vector can

be expressed in relative mode if the integrator
reset bit in the parameter word was previously
set, or directly in absolute mode. The coordin-

positions,

of end-point B of vector 2 are 255,85
absolute or 170, 170 relative. This vector would

which define the absolute displacement of the
end point along the X- and Y-axes, into the X
and Y sample and hold registers, XSH and YSH,
of the controller.

be specified as long because it is greater than 3/8
inch in length and should be drawn intensified
so that it will be displayed on the oscilloscope

quentially

entering

the

coordinate

Drawing Modes - Relative and absolute modes
are program ordered by depositing the desired
parameter as a binary bit of a 9-bit parameter

word into the PDP-8 family accumulator and
then issuing an execute input-output transfer
instruction.

Other line-vector parameters that

are defined by the 9-bit parameter word are long

and short format, the intensification of the
wanted line, erasure of the display currently
shown on the oscilloscope screen, and integrator
reset.

integrator

reset

ensures

that

the

line-vector will be properly referenced to the
origin. If the integrator reset is not specified by

one of the bits in the parameter word, the Mne
vector should start from the
point.

3-6

last

named end

ates

image area.

Long and Short Linear Vectors - The length of
the generated linear vector stroke is determined

by the stroke-control timing circuits in the
controller. For line vectors, the stroke-control
timer operates at two discrete time intervals
depending upon whether a long- or short-stroke
bit is set in the 9-bit parameter word. When a
long stroke is chosen, the stroke control timer
will provide a

time signal 2700 machine cycles

long (for a total of 4.05 milliseconds at 1.5
cycle).
When a short
chosen, the stroke control timer will

microsecond/machine
stroke

provide a time signal that is 1/16 the period of
the long stroke time period (for a total of 250

microseconds). The vectors illustrated in Figure
3-3 are long.

Long Linear Vectors

coordinate of point B is loaded into the Y-axis

A long vector execution is required if the vector
length

exceeds 3/8 inch. Choosing the long-

vector bit in the 9-bit parameter control word

The parameters for the visible vector are
t.Ai.V

for a line less than 3/8 inch in length will cause

deterioration of the line quality which will result
in excess line width and low resolution.

V^J.il.~

puter in their proper bit positions so that an
absolute (or relative, depending on how the X-

and Y-axis coordinates were chosen) long inten-

Whenever the vector length is over 3/8 inch but
less than

6 inches, the long vector bit should be

specified in the parameter word. When the start-

ing X- and Y-axis coordinates for the vector are

chosen, and if these coordinates do not occur at

sified vector is generated. The

execution of this

vector causes the output voltage of the respective

X and Y integrators to be driven to the same

analog levels as those held in the respective X

and Y sample and hold registers.

the origin in the display, an invisible vector must
first

be drawn to the starting point of the visible

The visible vector A*B in Figure 3-3 is
drawn in just this manner. The programming

vector.

The program is held in the skip test waiting

loop until the ready flag is detected. This completes the execution of the visible vector A'B.

sequence is as follows:

NOTE
a.

The oscilloscope display is first erased and

the integrators in the controller are reset to

obtain an origin (0, 0) starting-point setting both

Unlike digital registers a property

the X and Y integrators.

of analog registers
to

bility
b. Next

their ina-

remember their values

over long periods of time. Thus,

the X-axis coordinate is loaded into

analog registers are subject to

the X-axis sample and hold register and the

all

Y-axis coordinate is loaded into the Y-axis sam-

drift.

ple and hold register. This occurs as two sequen-

drift is

tial subroutines in the program.

positions per second in the sam-

In the

KV Controller this

not greater than 30 spot

ple and hold registers and 6 spot

The parameters for the vector are then
loaded into the computer accumulator in their

positions per second for the in-

proper bit positions and an absolute long nonin-

± 3° C (± 5° F) range about the

tegrate anu iioiu registers, over a

tensified vector

ambient temperature when they

voltage

are initially adjusted. This spec

is executed. When the output
from the integrators equals the same

voltage level as that of the analog value of the

means

that

end-point (A) coordinates in the respective sam-

taken

and hold registers, an invisible vector will
have been executed to point A.

when analog data is not renewed.

ple

Hence,

some

reset

care

the

must be

integrators

good practice to

reset whenever a vector sequence
is broken.

d.
is

When the vector is executed, the program

held in a waiting-loop microprogram called a

skip test, until the vector is completed.

At the

Short Linear Vectors

completion of the vector, the controller returns
a

skip

signal

(ready

flag)

to the interfacing

computer to permit the program to continue.

A short vector execution is desired if the vector
length

is less

than 3/8 inch. Choosing the short

vector bit in the 9-bit parameter control word,

A*B

the

for a line greater than 3/8 inch in length, may

X-axis coordinate of point B is loaded into the

exceed the storage capability of the oscilloscope

X-axis sample and hold register and the Y-axis

and the accuracy of the KV-8 Controller.

generate the visible vector

3-7

3.5.4 Circle-Drawing Capabilities

+320
VECT

The KV-8 controller is capable of drawing arcs
and circles on the oscilloscope with a circular
vector stroke that is generated by the controller
analog function generator module.
circle

drawn by

first

^^^-" -A

An arc or

specifying the X- and

B«=^

Y-coordinates of a point on the circumference
of the wanted circle and then initializing the

VECTOR PLOT
NOT INTENSIFIED

integrators to these values using the linear vector
VECT

mode and drawing an invisible linear vector to

CVECT

this point. This point defines the start of the arc

or circle vector. Next, the X- and Y-coordinates

of the center of the circle are determined relative to the origin at 0,0 and then the arc or circle
is

drawn

circular

vector

mode

using the

ARC VECTOR^

<<>

/
0,0

INTENSIFIED

1- + 256

coordinates of the center. Depending on the
length of the arc,

may be executed in either

short, long, or continuous circular vector mode.

Figure

ference of Circular Vectors

The difference between the center coordinates
and the circumference coordinates determines
the radius of the circle or arc.
Circular Vectors

Specification of Center, Start and Circum-

3-4.

mined by the stroke-control timing circuits in
KV controller. For arc vectors the stroke-control
timer operates at two discrete intervals depending upon whether a long or short circular stroke
bit is set in the 9-bit

Parameters that define a wanted circular vector
are short, long, or continuous; and intensified or
unintensified. Circular vectors are always drawn

clockwise with respect to the starting location.
The arc or circle can be drawn visibly or invisibly

between a given starting point and the end
The starting point coordinates must be

point.

then the center of the arc or
circle is computed to give the radius. In Figure
specified

first;

3-4, the circular vector is specified by giving the

X and Y coordinates of starting point A as
absolute from the origin. A linear vector is then

drawn invisibly to point A to give the start of
the wanted arc. Next, the coordinates of point B
are specified and the circular vector is drawn.
(The coordinates for the center of a circle in
circular arc mode are always referenced to the
origin 0,0.) If a short vector has been chosen,
the arc vdll subtend 5.625°; if a long vector has

been chosen, the arc wih subtend 90°; and if a
continuous vector has been chosen, the arc will
be continuously drawn until the arc is stopped

by giving the suitable stop command.

Long and Short Circular Vectors — The arc angle
of a generated circular vector stroke

3-8

deter-

parameter word. When a

chosen, the stroke control timer

will provide a

time signal that permits an arc of

long stroke

90 degrees to be subtended. The circular vector
illustrated in Figure 3-4 is long.

Whenever the

circular vector to be generated

subtends an integer multiple of 5.625°, the short
vector mode bit should be specified in the

parameter word. The desired arc angle is then
obtained by executing the correct number of
short circular arc vector commands. When this is

done,

may not be necessary to reload the

coordinates

of the

center prior to each ex-

ecution if the arc can be completed in less than
20 milliseconds (that is, if there is no long wait

between the completion of each 5.625° segment
and the initialization of the next 5.625° segment).

Continuous Circular Vectors - When a circular
arc with an arc angle not divisible by 90° or
5.625° is to be generated, it is necessary that the
bit controlling the continuous mode of the 9-bit
parameter word be set. Setting this bit disables
the vector stroke timer in the controller. Hence,

timing must be controlled externally by the

program in a real-time mode. The arc writing
rate is 0.1 degree per 4.5 microsecond. Continuous mode may also be used for angles divisible

age of the

circular arc on the face of the display.

by 90° or 5.625° if desired.

program is held in the skip-test waiting

g. The

To draw the circular arc shown in Figure 3-4,
the following programming sequence is required:

X and Y integrators to be driven by

,..„.^:^„i
quauiaiuic smuauiuai aigiiaio ±11 oi^>..ji ci xxxu.±lxx^x
that they trace out the parametric path of a

loop until the ready flag is detected. This completes the execution of the visible arc vector.

NOTE

The oscilloscope display is first erased and

the integrators in the controller

are reset to

Whenever a circular vector is exe-

obtain an origin (0, 0) setting in the X and Y

cuted,

integrators.

format to obtain the absolute vector mode, the X-axis coordinate of the

lOclUCU inuu

LllC

command

registers

given.

Refer

sample programs at end of chap-

-aAia hdinyis^ itiivt x^vt.\^ x\y^i.^*.v±-.

The loading of these

of the parameter

should always be loaded into the
accumulator before the execute

the X-axis sample

and hold register and the Y-axis coordinate

word must be set to zero. The
parameters for the wanted vector

b. Using the load

linear vector is loaded into

bit

ter.

occurs as two

small sequential subroutines in the program:
3.5.5 Point-Plotting Capabilities

The required parameters are then loaded
into the computer accumulator in their proper
c.

and the absolute long nonintensiis executed. When the output
vector
fied linear
voltage from the integrators equals the same
voltage level as that of the analog value of the
end-point (A) in the respective sample and hold
registers, an invisible vector vnll be executed to
bit positions

point A.

When

program

the

linear vector

executed the

held in the skip-test waiting-loop

until the vector is completed. At the completion
of the vector, the controller returns a skip signal

(ready

flag)

the

interfacing

computer to

permit the program to continue.

Then, to generate the visible circular vecand
tor, the circular vector load format is chosen
e.

The KV controller plots points on the oscilloscope screen simply by reading the data-word
analog

value

registers.

stored

When

the sample and hold

point-plot

graph

to be

generated it is only necessary to specify the X
and Y coordinates of each wanted point in point

Spot diameter is 0.008 inch approximately and the distance between addressable
screen coordinates is a^i^roximatelv 0.012 inch

mode.

so that specifying

X and Y coordinates in con-

tinuous increments of 1 will generate what will
appear essentially as a continuous graph of the
function

of two

variables.

For points more

widely separated, or for estimates of a general
direction of the variables, the vector mode
should be used to connect the separated points.
A short vector (3/8 inch in length) will contain

approximately

32 decimal (40 octal) coordi-

the X-axis coordinate of point B is loaded into
the X-axis sample and hold register and the

nates.

Y-axis coordinate of point B is loaded into the
Y-axis sample and hold register as in (b) above.

3.5.6 Joystick And Cursor

The parameters for the visible circular vec-

Any coordinate on the display viewing area can
be identified with the Type H306 Joystick

tor are then entered into the accumulator of the
computer in their proper bit positions so that a

Control which slews a small light spot (cursor)
anywhere in the visible viewing area in both the

The

X and Y planes. The Joystick control moves in

execution of this vector causes the output volt-

two planes and its physical position corresponds

long

intensified

arc

vector

generated.

3-9

with the position of the cursor in the viewing
area. An interrupt button on the Joystick behind the control permits the computer program

on demand from the user.
is interrupted, and if the
computer is programmed to recognize the interto be

interrupted

When

the program

rupt, a routine is entered that obtains the coor-

dinate of the current position of the cursor. The

routine must be executed twice, once for each
coordinate. (Refer to
Program Ex-

ADCONV

significantly

reduced. The unrefreshed system

also permits display data file subroutines
data-file linking programs to

and

be stored in highly

compacted algorithms that can be linked in any
combination to draw the picture of a desired
graphical structure. Once the file subroutines
have been programmed, they need only be
linked by a main program. These links can be
updated by defining new positions with the
cursor.

ample at end of chapter.)

The KV Controller consists of essentially three
3.6

BASIC MACHINE-LANGUAGE PRO-

GRAMMING

functional groups: (1) the control and timing
circuits, (2) the digital-to-analog conversion cir-

and, (3) the analog function generator.

cuits,

parameter-word and data-word transfers
between the PDP family computer and the
VTOl graphic display take place through the
All

accumulator.

Hence,

each

accumulator-held

word must be transferred to the digital register

The control and timing section accepts commands from the computer accumulator via the
input-output bus, and transmits commands back
to the

computer through its skip and interrupt

facilities in

the control logic.

The circuits also

establish system timing.

in the controller through

an input-output trans(lOT) instruction. These input-output transfer (lOT) instructions tell the controller whether

an analog output that

the word held in the accumulator is a parameter

digital number in the

or data word and also what action should be
taken by the controller in processing the para-

in the

fer

meter or data word.

The digital-to-analog converter (DAC) produces
is proportional to the
accumulator. The number

accumulator is given in 2's complement

notation in bit positions ACj through ACi j for
a total of 10 bits; this 10-bit binary number
gives a signed 5 1 2 point address range. The third

3.6.1

major functional unit is the analog function
generator which is actually a hybrid computer.

The KV Controller

commands to this unit establish various
analog functions such as line and vector genDigital

The KV Controller (Figure 1-1) converts digital
data inputs from the computer accumulator into
an analog signal that drives the X- and Y-axis
deflection circuits of the VTOl Storage Display
Unit. The digital inputs required by the Type

KV Controller are entered into the accumulator
through

the computer program stored in

its

memory, which tells the control what to do with
the accumulator data. The program contains
data files for generation of any desired ASCII
(teletype compatible) character, character string,

or any arbitrary vector sequences and an interruptable entry for converting the cursor position

coordinates

digital

data that immediately

updates the data file. The VTOl Storage Display
Unit

an unrefreshed system; hence, a large
data file or refresh memory is not required to
is

eration and circle generation.

In programming the

KV Controller, instructions

are given by a combination of the input-output

instruction set and the contents of the accumulator.

The KV Controller has two major control

states, data and parameter, which are selected by

the input-output (lOT) instructions. In the data
state,

the content of the accumulator is inter-

preted as a data word representing a positional
coordinate (i.e., part of an address) that defines
a point

specified

on the VTOl display. This position is
by the lOT instruction which is inter-

preted as an X or a Y address. This address is
accepted by the controller as either an absolute
address (which is always referenced to the origin

The oscilloscope itself
has a memory so that the amount of computer

position) or as a relative address (which is always
referenced to the previously stored display ad-

core

dress).

regenerate

3-10

the

storage

display.

required

for

given

display

The interpretation of the address as absolute or
relative is
state.

determined during the second major

During

this

state,

called the

parameter

and 2 tell the computer that the instruction is an
input/output transfer. In the 8 family of computers, this three-bit word is 1 1

(or 6 octal).

state, the contents of the accumulator are inter-

preted as a microprogrammed instruction that
controls the execution of the desired vector (i.e.,

long linear vector, short linear vector, circle
vector, circular arc vector, or point) within the

analog function generator. The parameter constate

trol

also

used to control the output

display mode of the VTOl display.

the

correct

lowered and

presented to the control unit in
format,
will

the

ready

The next six bits (3, 4, 5, 6, 7, and 8) of the lOT
word are the device selection code.
The six-bit length of this code permits up to 64
instruction

peripheral addresses. However, many peripheral
devices require two or more codes because they

The KV Controller uses two independent events
to communicate with the computer. The first
event is the ready-to-receive event. Whenever an
instruction

Device Selection Code

flag

will

then automatically be raised

can perform a large number of discrete operations.

The

the instnjction has been executed.

ready flag produces an interrupt request which

The

appears on the computer interrupt bus.

status of the ready flag can be sampled by a skip

instruction.

KV controller; these device codes are

000 1012,000 1102,and000 lllj (05, 06, and
07

octal).

Generally device code OSg

used

with the joystick to recognize or clear the cursor
device code 063

flag;

after

For example, there are three device codes

for the

the

generally used to load

X and Y registers of the controller and to

execute a wanted vector; device code 078 is used
to recognize the completion flag and for operation of the digital-to-analog converter and com-

rmratnr

The second event that also causes an interrupt is
external interrupt request key physically
located on the rear of the joystick cursor control
device. When this key is depressed, the status of
the cursor flag is sampled by a skip instruction.
an

Controller Operation Codes

The last three bits (9,

10,

and 11) of the lOT

instruction are the device operation code. Setting any one of these three bits separately or in

addition

the

above

two

skip

combination obtains a wanted response from the

instructions, a third (non-flag) skip instruction is

from the display. These bits control a timing generator in the computer that
provides serial output pulses on the input/
output (I/O) bus which are used by the controller to perform its operations. For each of the (7)
possible combinations of the output pulses, a
separate response is provided by the controller
(VTOl), but not simultaneously. Although the

i:ivnilaHlf»*

fViiQ

flag

inctrnptir^n r^ror1iir»pc q cVir\ r»nlcp

on the computer skip bus if the output voltage
of the DAC is greater than the output voltage of
the selected cursor axis. This instruction is used
to read the X- and Y-axis cursor coordinates

through a successive approximation program.
3.6.2

lOT Instruction Format

controller or

effective number of separate responses available

The lOT instruction is a standard 12-bit word
used by the 8 family of computers to eUcit
specific responses from the peripheral device
(the VTO 1 controller). This 1 2-bit word (Figure

with the three-bit device operation code is 7,

3-5) comprises three basic multi-bit parts: the

group, five in the 063 group, and four in the 078

computer operation code, the device selection
code, and the device operation code.

is hsted in Table 3-2.

Computer Operation Code

3.6.3

The computer operation code uses the first three

Typical machine-language programs to produce

bits

of the instruction word; hence, bits

this number is somewhat idealized. In the three-

number device selection code group, there are
1 1
separate operating codes, two in the 05 3
group. The instruction set for the KV controller

Programming Techniques

line, arc,

and circle generation include the octal

3-11

DEVICE - SELECTION

VT01
OPERATION

CODE

COMPUTER
OPERATION
CODE

Figure 3-5.

Basic iOT Instruction Format

TABLE 3-2. TYPE KV CONTROLLER INSTRUCTION SET
Octal

Code

Mnemonic

6051

SNC

Function

Operation
Skip the next program instruction

This instruction senses the condition of the

the cursor interrupt flag has not

cursor interrupt flag. The flag produces an

been set.

interrupt request

when set by operation of

the interrupt pushbutton on the joystick.

The flag is initially cleared when the computer is started. As with all flag-sense instructions, SNC can be used under interrupt
conditions to detect the source of the
interrupt, or it can be used under interrupt
on (ION) when the interrupt request has
been caused by the operation of the cursor
interrupt button. In a program ruiming with
the interrupt off, SNC can be used to ignore
the

cursor

routine

successive

the

approximation

program

sub-

a request for

service has not been made from the joystick

controller.

6052

CCF

Unconditionally

clear

the

flag.

cursor

This instruction
flag

after

used to clear the cursor

request for service has been

acknowledged by the program.

6062

SAC

Select the analog comparator.

The analog comparator is set to compare the
analog content of any one of six analog
sources with the content of the digital-to-

analog converter. The six analog sources are

chosen according to a 3-bit binary code. This

code establishes the parameter for choosing
the wanted register according to the content

of bits AC2

AC3 and ACg in the computer

accumulator

(refer

to paragraph 3.6.4) as

follows:

Accumulator Bits
2

1
1
1

3-12

Selected Source

XINT
YINT

XSH
YSH
XCUR
YCUR

TABLE 3-2. TYPE KV CONTROLLER INSTRUCTION SET (cont)
Octal

Code

Mnemonic
TDR

Operation
T rvofl

Function

In /-»T-t-no +

mode in which a wanted graphic is to be
produced
code.

according

This

code

wanted vector
tive,

two-bit

binary

determines whether the

will

be linear absolute rela-

whether the point plot mode will be

used or whether the cursor vvdll be displayed.
This

code establishes the parameters for

these formats according to the content of
bits

AC2 and AC3 in the computer accumu-

lator (refer to paragraph 3.6.4).

instruction

must precede the

The LDP

LDX and/or

LDY instructions.
6064

LDX

Load the X-axis sample and hold

The X-axis sample and hold register is loaded
witii

tiic

uinary

equivalent

of the X-axis

coordinate according to the content of bits

AC2 through AC

J J

in the

computer accum-

ulator. This data appears at the output of

the digital-to-analog converter as the analog

equivalent of the X-axis value of the binary

word stored

the accumulator (refer to

paragraph 3.6.4). The LDX instruction clears

an existing ready flag and sets the ready flag
after 100 ± 20 microseconds.

6065

LDY

Load the Y-axis sample and hold

The Y-axis sample and hold register is loaded

with the binary equivalent of the Y-axis
coordinates according to the content of bits

AC 2 through ACj

in the

computer accum-

ulator. This data appears at the output of

the digital-to-analog converter as the analog
equivalent of the binary word in the accumulator (refer to paragraph 3.6.4). The LDY

instruction clears an existing ready flag and
sets the

ready flag after 100 ± 20 micro-

seconds.

6066

EXC

Execute the instruction according
to

the parameter

word

held in the accumulator.

currently

Used to execute the wanted vector according
to the content of bits

ACg through ACu
mulator.

AC2 AC3 AC4 and

of the computer accu-

The parameter word

establishes

long or short formats circular vectors, display erasure, reset of the integrators, and
intensification of the vector (refer to para-

graph 3.6.4). The EXC instruction clears an
existing ready flag and sets the ready flag as

follows:

3-13

TABLE 3-2. TYPE KV CONTROLLER INSTRUCTIONS SET (cont)
Octal

Code

Function

Operation

Mnemonic

After 20 ± 5 microseconds for a point

or vector continue.

After 250 microseconds for short vec-

tors.
c.

After 4.05 milliseconds for long vec-

tors.

d. After 500 milliseconds for an erase.

SRF

6071

Used to determine when the controller is
ready to perform the next execute instruc-

Skip if the ready flag is set.

The ready flag produces an interrupt
condition when set. The flag can be set by
pressing the erase pushbutton the VTOl.
tion.

Normally, however, the state of this flag is

determined

V the

initially

controller. This flag

computer

when

cleared

started and prior to an

the

LDX, LDY, or EXC

instruction.

CRF

6072

Unconditionally

clear

the

ready

This instruction
flag

flag.

after

used to clear the ready

instruction has been ac-

skip

knowledged.

SDA

6073

Skip when the output of the
tal-to-analog

converter

digi-

output

greater than the selected source.

This instruction

used

the successive

approximation subroutine to determine the
digital

equivalent

of the

selected

analog

holding register. This instruction is used with
the SAC (60628) instruction.

LDA

6074

Load the

digital-to-analog conver-

ter.

This instruction

used to load the content

of bits AC2 through ACj 1 of the computer
accumulator. This instruction is used with

SDA (60733)

the

successive-

approximation subroutine to determine the
digital value

of the content of the selected

analog holding register. This instruction does

not change flag states.

equivalents

of the addresses and instructions

stored at those addresses. (A typical program is
given in Program Example 1 at the end of this
chapter.)

When

defining the addressable coor-

dinates of the visible and effective image areas of

the display unit, a simple decimal system can be
used once the linear decimal points have been

determined for the graphic construction desired.

3-14

The octal value of the coordinate must be given
when programming in the machine language.
There are 1023/12 or 85.3 coordinates per linear
inch in either the X- or Y-axis planes of the
visible and effective image areas of the display
Hence, the desired graphic construction can be laid out on standard 10 x 10
graph paper (Dietzgen Type 340-10 or equivaoscilloscope.

lent, for example),

each point plotted, and then

3.6.4 Using the lOT Instructions

these points converted to octal using the tables
in the appendix. When EDGRIN is used as the

The

source language, this conversion is performed by

comprise the complete set of machine-language

the assembler.

instructions for the graphic display system. In

In Figure 3-6 four graphic constructions are laid

stored in the accumulator of the interfacing
computer. This word may specify either a coor-

out on 10 X 10 graph paper so that there is one
figure in each of the four quadrants. These four
figures

require

13 coordinate points for their

definition so that the linear equivalent of each

of these

1 3

points must first be determined. If

the linear unit distance is set to be 85 per linear

inch instead of 85.3 per linear inch, a negligible
error is introduced. Hence, it is only necessary
to measure the distances in inches and multiply

by 85 to obtain the linear coordinates of each of
these points. These values are listed in the X and
Y subcolumns of the Absolute Decimal column
of Table 3-3. If desired, these points can be
converted to relative decimal and then to octal.
Absolute and Relative. There are many ways to
determine the wanted coordinates; the foregoing
description offers only one of many possible
ways.

lOT

instructions listed in Table

3-2

dinate or a set of parameters for the wanted
display.

Any word stored in the accumulator

that specifies a coordinate

considered a data

word and any word that specifies parameters for
the wanted display is a parameter word. The
lOT instructions LDX and LDY (6064 and
6065, respectively) wiU accept the content of
accumulator bits ACj through ACj i as data.

Accumulator bit AC2 (Figure 3-7) is the data-

word

sign

bit.

If this

bit

set,

the data

considered negative. Accumulator bits ACq and
ACi have no meaning in the data word; the lOT
instructions

SAC,

LDF and EXC (6062, 6063

and 6066, respectively) will accept the content
of the accumulator as a parameter word. The
lOT instruction LDF (6063) reads the data held

and AC3 only. The lOT
reads the data held in
SAC
(6062)
instruction

in accumulator bits AC2

accumulator bits AC2

AC3 and ACg

while the

lOT instruction EXC (6066) reads the data in
AC2, AC3 and AC4 together with bits ACg
through ACi 1 as a parameter word (Figure 3-8).

There are two interrupt producing flags which
can be sampled by separate skip tests, and one
170

controher.

flag

the

A cursor interrupt flag

obtained

non-interrupt producing skip

from a pushbutton behind the joystick on the
-170

-85

170

H306 joystick controller. (Refer to Table 3-1.)
When the pushbutton is depressed, and if the
interrupt facilities of the interfacing

computer

are enabled, the program currently being opera-

K •

fH -85

ted upon by the computer is interrupted. This
interrupt can be used to permit the successive-

-170

approximation subroutine to be entered and a
digital equivalent of the cursor or analog register

• J -255

to be

produced

in the accumulator.

The suc-

cessive-approximation subroutine is called for as
a JMS

ADCONV with the proper octal code for

the source selected held in the accumulator.

(Refer to ADCONV Program Example 2.) The
wanted analog source is selected using the SAC
Figure 3-6. Typical Coordinate Reference System for

Machine Language Programming

instruction (listed in Table 3-2) according to the

following octal code;

3-15

NOT
USED

ESTABLISHES THE COORDINATE
POSITION FOR ALL POINTS
BETWEEN
AND 511io IN EITHER
AXIS IN THE VISIBLE AND
EFFECTIVE IMAGE AREAS

SIGN BIT

0=(+)
1

=(-)

Figure 3-7.

Basic Data-Word Format

TABLE 3-3. TABLE OF ABSOLUTE AND RELATIVE
COORDINATES FOR FIGURE 3-6

Point

Absolute

Decimal

Octal

128

255

213
43
213
213
43

0053
0200
0325
0053
0325
0325
0053

0125
0377
0125

D
E
F

G
H

Note:

85
-85
-85

-255
-255

-85

-255

-170

-255

-170

-85

-128

170

-128

255

1653
1653
1526
1526
1600
1600

1653
1653
1453
1453
1653
1401
1453
1653
0252
0377

To specify a negative decimal number in octal, drop the sign

and add 1000 to the two's complement octal magnitude. To get an
octal equivalent of the two's

complement, take the octal comple-

ment and add 1 to the least significant digit.

0000 will select the X-axis integrator ana-

log source.

0040 will select the Y-axis integrator ana-

1400 will select the X-axis coordinate of

1440 will

select the Y-axis coordinate of

the cursor.

log source.

the cursor.

1000 will select the X-axis sample and hold

The subroutine will be exited with the full two's
complement answer left in the accumulator. The
subroutine requires 25 consecutive locations in

memory and requires approximately 900 microd.

1040

will

hold register.

3-16

select

the Y-axis sample and

seconds to complete the worst case
conversion.

(all

ones)

NOT
USED

RST

IFY

EXECUTE VISIBLE

SPARE

vc.v!wr\ Kjr\ r\j\i'i

.RESET INTEGRATOR AND
SAMPLE AND HOLD
ERASE DISPLAY

SPARE
DEFINES MODE FORMAT
DEFINES MODE FORMAT

SHORT VECTOR

CIRCULAR VECTOR IFACg'O

ACg'O

VECTOR CONTINUED
LONG VECTOR IF ACg AND AC4 =

SPARE

AC2 AC3
RELATIVE LINEAR VECTOR MODE OR CIRCULAR VECTOR MODE
1

ABSOLUTE LINEAR VECTOR MODE
POINT MODE

CURSOR MODE

Figure 3-8.

Basic Parameter-Word Formats

Program Example 1
JMS

DSPLY
{

)

(

)

/CALL DISPLAY SUBROUTINE WITH

/FORMAT
IX DATA
/Y DATA
/RETURN ADDRESS

DSPLY,

CLACLL
TAD DSPLY
I

/ENTER W AC = AND FORMAT, X, Y PRESET TO
/DESIRED VALUES, FOLLOWING JMS CALL

ISZ DSPLY

6063

DCA FORMAT
TAD DSPLY

/LOAD FORMAT
/AND SAVE FOR EXECUTION

/LOAD X

6064

CLA
ISZ DSPLY
6071

/WAIT FOR X TO BE LOADED

JMP.-1

TAD DSPLY
I

6065

/LOAD Y

CLA
ISZ DSPLY

6071
JMP.-1

/WAIT FOR Y TO BE LOADED

TAD FORMAT
6066

/EXECUTE THE FORMAT

CLA
,

IGZDDPL¥
6071

/WAIT FOR COMPLETION OF EXECUTION

3-17

Program Example 1 (cont)
JMP.-1

JMP

DSPLY

/EXIT SUBROUTINE

/SAVE FORMAT

FORMAT,

Program Example 2
/KW ANALOG TO DIGITAL CONVERSION SUBROUTINE
/CALL AS JMS ADCONV WITH SOURCE SELECTION CODE IN AC:
/OOOO FOR X INTEGRATOR
/0040 FOR Y INTEGRATOR
/1000 FOR X SAMPLE AND HOLD REGISTER
/1040 FOR Y SAMPLE AND HOLD REGISTER
/1400 FOR X CURSOR
/1440 FOR Y CURSOR

/EXITS WITH FULL 2'S COMPLEMENT ANS IN AC

/REQUIRES 25 CONSECUTIVE IN PAGE REGISTERS (DECIMAL)
/APPROXIMATE 900 US TO COMPLETE THE CONVERSION WORST CASE
/SET LOCATE TO THE DESIRED ORIGIN ADDRESS

LOCATE=200
*

LOCATE

ADCONV,

/SELECT ANALOG COMPARATOR

6062

CLACLLCMLRTR
DCA TEST
RC1,

TAD K7000
DCA TEMP
TAD TEST

/+2000IN AC
/INITIALIZE TRIAL BIT REGISTER
/INITIALIZE PARTIAL CONVERSION REGISTER

/SAVE PARTIAL CONVERSION

CLLRAR
DCA TEST
TAD TEMP

/ADVANCE TRIAL BIT

SZL
JMP ADCONV
TAD TEST

/EXIT WHEN TRIAL BIT OVERFLOWS LINK

6074

/LOAD D/A WITH TRIAL VALUE

CLACLLCML

/SET LINK

RAR
SNL
JMP .-2
K7000,

/WAIT 54 US

NOP

TAD TEMP
6073

/TEST D/A

TAD TEST

/SKIPS IF TRIAL TOO LARGE

JMP RC1

/CONTINUE

/VARIABLES SET BY ADCONV
7000
TEMP,
TEST,
$

3-18

2000

/PARTIAL CONVERSION SAVE
/TRIAL BIT

CHAPTER 4
PRINCIPLES OF OPERATION

KV controller. The chapter
two sections: Fundamentals of Operational Amplifiers, and Circuit Analysis. Section I
provides a brief analysis of operational amplifiers and field-effect transistors (FET) as they are relevant to
This chapter of the maintenance manual covers principles of operation of the

divided into

KV controller. Section II is concerned with the
KV controller as a functional part of the KV Graphics Display System and

the understanding of the principles of operation of the
principles of operation of the

with the principles of operation of each of the modules or functional circuits, whichever is applicable,
that comprise the controller. Detail dicussions of options are not included in this chapter. The reader
should refer to the

list

of related documents contained in the introduction to this manual for the

publications covering equipments in this category.

SECTION

FUNSAMENTALS OF OPERATIONAL AMPLIFIERS

4.1

OPERATIONAL AMPLIFIERS

output impedance must be very low for driving
purposes; (4) the amplifier response tim_e must

An operational amphfier is basically a dc amplifier

with a negative feedback loop which pro-

be very short to provide a phase-gain characterthat will allow for a strong negative feed-

istic

duces a circuit with a precise gain characteristic

back; (5) the bandwidth must be wide (dc to

that depends only on the feedback used. Opera-

tens of kilo Hertz); and (6) offset must be low.

tional amplifiers are used in the

KV controller to

(such as addition and integration) and to provide

We will also see in the subsequent paragraphs
why these characteristics are essential to the

impedance buffering for the analog outputs of

operation of operational amplifiers.

perform

mathematical

analog

computations

the controller.

The basic requirements of an operational amplifier are: (1) the open loop gain (A), without
feedback, must be very high, A = 10"* to 10^;
(2) the input impedance must be very large to
prevent loading the input signal source; (3) the

4. 1

idealized Operational Amplifier

The circuit shown in A, Figure 4-1 is the basic
configuration of an operational amplifier. E^ and

represent

the

source and output signals,

4-1

With the summing point at ground potential,
equal currents flow in Zj and Zq.
(A)
lo

SUMMING
POINT

Therefore:

[IT

-\in-^

-o

but by definition

Eo = AEi

therefore,

(B)

SUMMING
POINT

-E,
E:

As A approaches infinity,
and equation (1) becomes:

Figure 4-1. Basic Operational Amplifier, Idealized

Ej approaches zero

respectively, and Ej is the resultant signal at the

input of amplifier.

Assume

that

the characteristics of the opera-

tional amplifier are idealized and that the open

loop gain (A) of the amplifier is infinite. Ej is
very small compared to Eg and for purposes of
this discussion we can say that no current flows
into the amplifier, amplifier current (I^) = 0. We

However the

gain

defined as:

A =

from the simplified diagram (B, Figure 4-1)
that if Ig - 0, then the input current Ij and the
see

feedback current Iq are equal placing the sum-

ming point

virtually

ground potential (0

volts). In view of this we can show that the gain

characteristic is dependent upon only the select-

ed values of input and output impedances, Zj

and Zr,.

4-2

by substitution then

_Zo

of operational amplifier

Hence, the gain characteristic of the operational
amolifier is determinp.rl hv tinp vijIucc r.f 7 ^^a
Zj

components selected. From the above it is
when Zq = Zj the gain of opera-

evident that

tional amplifier is unity., Unity gain operational

amplifiers

used in the

are

KV controller for

impedance buffering.

4.1.2 Integrators

Operational amplifiers configured as integrators
provide an output signal (Eq) that is proportional to the integral of the source signal (Eg).

They

are

Figure 4-2. Integrator, Basic Configuration

constructed by placing a capacitive

element (Cq) in the feedback network (Z^) and
a resistive element (Rj) in the input network (Z,)
as shown in Figure 4-2. The time constant of the

by the selected values

integrator is determined

of the

and capacitor. The current
through the feedback loop (Iq) charges the
capacitor and the stored charge (Eg) is seen by
the load on the integrator as the integral of the
resistor

source signal (Eg), which is:

RjCg

E,dt

Figure 4-3. Scaling Adder. Basic Configuration
If the

input voltage is a constant (dc), Eq is a

ramp equal to

cision resistors as the input impedance (Zj) and a

Eo =

Est

RjCq

the amplitude of the ramp (Eq), as we can see, is
directly

dependent upon the time (t) the capaci-

tor is permitted to charge.

precision resistor for the feedback impedance
(Zq). In this type of adder each input is seen at

the

summing point as the input resistance (Zj).

Assuming that the summing point is idealized
(virtually at ground potential or
vohs) each
input is multiplied by a constant (which is
determined by the value of the resistor in each
leg

of the resistor ladder) before summingand the input current (Ij) at the

inverting;

4.1.3 Scaling Adder

summing point is, therefore, equal to the algesum of the current in each leg of the

braic

The scaling adder is used in the digital-to-analog

precision resistor ladder network. Hence,

converter and the sample and hold analog regis-

equals 1q then

ters

if Ij

of the KV controller. As shown in Figure

4-3, the adder, basically, comprises a precision
resistive ladder

network with n number of pre-

'o =

+ 1.

4-3

and the output voltage (Eq) equals

R-

Eo =

-^oi^l

Rn/

The FET, when in the "on" state, appears to the
signal source as a simple ohmic resistor; not a
resistance in series with an offset voltage. As it is
used in the controller, the FET introduces no
error due to offset making it ideally suited for
its application here.

Input signals Ej, Ej, etc. in the application of
the scaling adder in the D/A converter are
applied from a common reference source (Eg)

and Eq is only dependent upon the resistances
selected. The above formula in this case becomes

4.2.2 Application

Consider now the circuit shown in Figure 4-4.
should be noted that the circuit shown is

(It

typical of the FET switches and drivers used in

the controller.) The FET (Q16) is a series samp-

Eq - -^o^s (

-R^

R-

Re ^

•^)

However, in its SH application, input voltages
(Ej and Ej) are applied from two distinct
sources, D/A output and reference supply, and
Eo in this case is dependent upon both input
voltage and resistance (Rj and R2 ).

with the signal source (Vg)

ling gate, in series

and the load (Rl)- Driver Ql controls the state
of FET and is normally off due to the biasing
arrangement established by resistors Rj thru R3.

The resultant -15V at the collector of the driver
maintains the FET in "off or open state and
the

FET appears to the signal source as a very

large resistor, in the order of megohms; hence,

the path to the load is open. Upon command of

Eo-Ro^R^ + ^j

the timing circuits, a negative-going signal

applied to the driver and the driver conducts
4.2

FIELD-EFFECT TRANSISTORS

causing a

5-volt transition at its collector.

The

FET alters state; and in the on or closed state,
the FET appears as a small resistor (175 to 350
4.2.1

ohms) establishing a low impedance path for the
signal source (Vg) to the load. The potentio-

General

(FET) is a unipolar
which has broad applications as a
sampling gate for multiplexer switching and

meter in series with FET permits adjustment of

switches

period that the FET is on is determined by the

The

field-effect transistor

transistor

other

switching

functions.

Ideally,

should introduce zero impedance into a circuit

when closed and should exhibit infinite impedance when open. Relay switches approximate
this ideal situation; however, when high-speed
switching is required, electromechanical devices
are too slow and

must give way to the use of

solid state switches, such as FET's.

the

resistance

exhibited at the input of the

operational amplifier when the

FET is on. The

time duration of the gating pulse which, in turn,
is

established

by the timing circuits of the KV

controller.

The

5-volt

amplitude of the gating pulse ex-

ceeds the required gating specifications to ensure
that the FET remains in the on state for the

duration of the gate.

Convention bipolar transistor switches in the

"on" state exhibit a small impedance, and in
addition an offset voltage which, in the case of
the controller switches, is in series with the
signal source.

some

applications this offset

The limitations of the FET, as it is used here, are
Vs must not exceed the breakdown voltage of
the FET, and the speed of the FET, when
compared with other solid state switching deslow (2 microseconds switch-

voltage is negligible; however, when deaUng with

vices, is relatively

low-level analog signals in the millivolt range it

ing

can be troublesome. FET's have the important
advantage of having effectively no offset voltage.

very important precaution to be observed in
troubleshooting the KV Controller, Quite often

4-4

time, typical).

The former limitation is a

OPERATIONAL
AMPLIFIER
LOAD

DRIVER

ANALOG
SIGNAL

-aW-

016

-I5V

(MOTOROLA)
2N5459

R4
2.7K

2N3638

R2
2K

SWITCHING

COMMAND

-I5V

SIGNAL
IN

+ 5V

f4.5V—
OV

SWITCH

—

fc'

-«

CLOSURE
TIME

Figure 4-4. Typical KV Controller^ FET Switching Circuit with Driver

failures of FET's are caused by excessive inverse

voltage across their terminals.

have the same value). Hold switch SI
v..i\jacu, pcimiis application oi tne
analog data to be stored. The length of time SI
resistors
vi i-'±j,

4.3

SAMPLE AND HOLD

storage

device;

indefinitely,

i.e., it stores an analog signal
assuming there is no drift or leak-

age. For simplicity, we can consider a sample
and hold as a capacitor to ground (in the

controller

the

capacitor

closed

the

A SH register can best be described as an analog

vViieii

determined by the time duration of

gatmg

signal; hence the timing circuits.
During the period SI is closed, capacitor C
charges to the value of the analog input signal.

The charge on the capacitor is held on the one
side by the high impedance of the open hold
switch and on the other by the low output
impedance of holding amplifier Q2.

connected to the

summing point or virtual ground of an opera-

When a new value is to be stored, SI is closed. If

tional amplifier) that

the value of the analog signal is lower than the
previously stored value, the capacitor will discharge to the new value of the analog signal. If

impedance isolated by

an input buffer amplifier with a switch (FET),

which disconnects it from the capacitor after the
capacitor has charged.

the value of the analog signal is greater, then the
reverse occurs.

Figure 4-5 illustrates a simplified version of the

SH. Amplifier Ql is the input buffer amplifier
and has unity gain (the input and feedback

In the

KV controller, a FET is connected across

the capacitor for reset purposes.

The

FET is
4-5

STORAGE

HOLD
SWITCH

INPUT

BUFFER

DEVICE

-^h

TO INVERTER
SIGNAL
SOURCE

Figure 4-5. Sample and Hold Analog Register, Simplified

normally open and leakage through it is negligible since it exhibits such an extremely high

impedance

this state.

However, when

Schematic Diagram

closed, a low impedance discharge path (approx-

imately 175 ohms) to ground is provided and
the capacitor; hence the SH, is reset.

SECTION

SYSTEM ANALYSIS

4.4

GENERAL

The KV Controller is divided into three major
functional groups as indicated in Figure 4-6:
lOT control and timing, digital-to-analog converfuncter and gate control logic and the analog
tion generator.

The I/O control and timer is

communications with the
computer. It accepts inputs from the accumulator (via the appropriate lOT instruction) and

responsible

for

all

parator which can be selected to perform, via
the appropriate software program, a 10-bit
analog-to-digital (A/D) conversion upon one of
four possible internal analog sources and one of
two external analog sources, normally representing the output position of the joystick control-

The resolution of the D/A is one part in
1024 ± 1/2 least significant bit. The overall

ler.

accuracy of the A/D process is one part in 256.

communicates back to the computer via the skip
and interrupt bus only. The D/A converter and
gate control accepts inputs from one or more of
the internal hardware registers and generates the

4.4.1

Internal Digital Registers

There

are

appropriate analog and digital control signals to
the analog function generator (AFG). The AFG
comprises the major control portion of the

nal timing registers.

system and produces the actual X and Y deflection voltages necessary

display lines, arcs,

points or the cursor from the H306 Joystick
Controller onto the surface of the VTOl Storage

Tube Display Unit.

4-6

registers,

two

interrupt producing flag registers, and four inter-

The D register is a 10-bit

data register used to hold the data during a load
data instruction and also to hold part of the

microprogrammed execute instruction. The FT,
AB, and L/S registers are one-bit control registers used to establish and maintain the necessary

permanent paths within the AFG to perform the
desired function. These three registers are also

and initialize the
A/D converperforming
comparator for use in

used
In addition to the analog output capabilities of
the AFG, the system includes an analog com-

four internal input

sions.

select

the

source

MNALU^s i-UNUMUN

CONVERTER AND GATE
LOGIC MODULE A6I2

n r

ACCUMULATOR
BUS BITS 2-1

UtNtKAlOR MODULE A3I2

10-BIT

,ABS

DATA
BUFFER

D/A

DISITALTO-ANALOG

CONVERTER

—f

X INTERGRATOR

CM
VECTOR
CONTINUE

OUTPUT
DRIVER

RST

BIT 7

FROM
COMPUTER

XFX

OUT

CUR

VC
RST

X CUR COORDINATE

XDT

MEMORY

lOT

BUFFER BUS

CONTROL
CIRCUIT

I0P'S(I,2,4)-

TIMERS

H306
JOYSTICK
CONTROL

LDT
Y CUR COORDINATE

RST

ICLI

.BIT 2

MODE
CONTROL

^ PM

-f-»-CUR

^-r
ABS
AC
.BIT 3

ABS

LOAD
DATA
CONTROL

CUR

XFY
Y SAMPLE
AND HOLD
REGISTER

Y INTERGRATOR

-»-XFX

OUTPUT
DRIVER

YOUT

,PM

-•>-XFY

-^ABS

BITS 8,10

EXECUTE
STROKE
CONTROL

BIT 4,

L/S

'CM
-RST

LV
SV

-•*-

WRT

BITS
9,11

- Z

DISPLAY

CONTROL
-ERS/ERD

SKIP BUS

SKIP

CONTROL

CURSOR

CURSOR INTERRUPT

INTERRUPT
FLAG

TO
COMPUTER

COMPARATOR
-*

INTERRUPT
BUS

INTERRUPT
CONTROL

READY
FLAG

drzr^

Y OUT

X OUT

r^rz^zi
Figure 4-6.

KV Controller Functional Block Diagram

4-7/4-8

Tlie

KV control contains two flags which are
me cursor interrupt

nominal

to -4 volt analog signal with an overall

gdiSu lO uiS interrupt uus.

resolution

of one part in 1024. The analog

flag is raised upon pressing the interrupt button

comparator

on the H306 Joystick controller. The ready flag
is raised either by pressing the erase button on
the VTOl, or upon completion of any load or
execute operation. Both flags are initially cleared when the computer is started.

multiplies

accepts

il-volt

analog signal,

by 2 and adds -2 volts to make it
to -4 volts, and then compares this

become

against the analog output of the D/A converter,

producing a high output
negative

the

D/A is more

than the suitably scaled
unknown, and producing a low output if the
opposite is true. This comparator output is

There are four internal timing sources in the KV
control and these determine the duration of a

voltage

sampled by a skip instruction and the resultant
skip/no skip condition is used to create a digital

given operation as denoted by the setting of the

ready flip-flop. The load data timer (LDT) is set

image of the unknovm analog signal in the AC
by a successive-approximation program^.

nominally to 100/xs ±20,us and represents the
time necessary to load data. The execute delay
timer (XDT) is set to 20/iS ±5jus and is activated

by an execute command. This timer will set the

4.4.3

Analog Function Generator

ready flip-flop at the completion of a point plot

command or at the start of a vector continue
(VC) command only. For all other execution
commands it initiates the stroke timer (ST). This
latter

unit

will

machine cycles
milliseconds)

time
(l.SjUS

The AFG basically operates like a hybrid comcombining the properties of an analog
computer with digitally selected signal paths.
There are 1 input digital control signals, which
estabUsh the signal paths and the mode of
operation of the KV controller, and four analog
inlput signals applied to the AFG. There are two
analog output signals which are produced as a
puter,

out precisely to 2700
each or nominally 4

or exactly

1/16 this time (250
microseconds), depending on the setting of the
long/short vector (LS) register.

the

ready

flip-flop

The ST will set

the completion of

its

of the input

result

The last internal timing register, the
VC, is activated by the XDT at its completion
operation.

listed in Tables 4-1

signals.

These signals are

and 4-2.

and inhibits the ST, replacing the precise hard-

CONTROL CIRCUITS

ware timing function with a timing function
which can be scaled under direct program

4.5

by AC bit 7 at execute time.

4.5.1

Input/Output Transfer Control

The

Input/Output

4.4.2 Digital-to-Analog

and

circuits

Analog-to-Digital

shown

Transfer (lOT)
control
Figure 4-7 interface directly

with the I/O bus of the computer and accept

Conversion Facilities

Memory Buffer (MB) levels and Input/Output
Pulses (lOP) to logically form the necessary lOT

The D/A converter in the KV controller transforms the contents of the

which are subsequently used to
prime gates for the generation of the internal

instructions

D register into a

TABLE 4-1. ANALOG FUNCTION GENERATOR,
INPUT/OUTPUT SIGNALS
Analog Input Signals

XDA
YDA
XCUR
YCUR

Range

Source

D Register
to -4V D Register

to -4V

± IV
± IV

X Position of joystick
Y Position of joystick
4-9

MB3{0)
MB4(0)
MB5(0)
MB6(i

MB7(0
MB8(I

)

M68(0
MB7(I

0P64 4 10P74

MBII (I )

I0P72

TO READY
FLAG (FF)
I0P2

Figure 4-7.

lOT Control Circuit, Logic Diagram

TABLE 4-2. ANALOG FUNCTION GENERATOR, DIGITAL

CONTROL SIGNALS
Action or Use

Signal

OUTPUT PATH
PM (Point Mode)

Closed in point plot mode to connect the SH
registers to the VTOl

VM (Vector Mode)

Closed

vector

mode to connect the INTH

registers to the VTOl

CUR (Cursor Mode)

Closed in cursor mode to connect and display X

CUR

and

Y CUR

from

the

H306

off-line as a non-stored elliptical pointer.

4-10

joystick

TABLE 4-2. ANALOG FUNCTION GENERATOR, DIGITAL
Signal

Action or Use

ABS (Absolute Mode)

Closed only during a load data operation to load
data from the D register as absolute data.

Closed to load the X sample and hold register

XFX (Transfer X)

from XDA. Data is interpreted according to the
state of ABS during load time.

Closed to load the Y sample and hold register

XFY (Transfer Y)

from YDA. Data is interpreted according to the
state of ABS during load time.

lOP execution commajids and to perform other
control functions. The lOT instructions, I0T5,
6, and 7, are logically formed by NAND gates
E17A-C and E16A'and NAND gates E13A-C
from levels MBS through 8. The lOT levels are
used to prime

NAND

execution

commands at the event time of the

lOP's from the computer. (See Figure 4-8.) The

lOP execution commands are IOP52,
74 and perform the following

internal

62, 64, 72, and

control functions:

gates for generation of

I/O START = TP3- SLOW CYCLE

I/O START

Hi-20

-rrsr.

00 n '

\f»

•

400 ns

•

IIF

[IF

MBn= 1)

Men =1)

j*-200ns-

(IF

MB!

MB 10= 1)

= 1)

1— 2 00ns-

(IF

NOTE: TIMING TOLERANCE

MB 09= 1)

MB 99= 1)

20 %

Figure 4-8. lOP Timing Diagram

4-11

IOP52

Resets the Cursor flip-flop.

output of the D/A into the X and Y SH registers
of the AFG. The LDT is primed by MBIO (1)

IOP62

Resets the ^16 Counter and PASS

and Vector Continue

flip-flops in

and initiated by execute command IOP64 which
also clocks Bl flip-flop ElO. Depending upon

vector mode. Clocks

PT and AB

the setting of Bl

LDT (1)

nent path (mode of operation) of
the AFG. Clocks LONG/SHORT

XFX Driver Q2 to load the Y or X SH register,

Resets the
the

READY flip-flop. Sets

PASS flip-flop from the condi-

tions
flop.

established

on the L/S

the

Initiates

flip-

LOAD DATA

When the Bl flip-flop ElO is set,
MBl 1 (1) is high, NAND gate ESC is primed and
the Y SH register is loaded. When the Bl
flip-flop is reset (MB 11 (1) is low) NAND gate
E5D is primed and the X SH register is loaded.
At the completion of each LDT function, the
LDT (0) output is applied to skip and interrupt
respectively.

MB 10 = 0, or the
EXECUTE DELAY TIMER (d2) if
MB 10 = 1. Forms the clock pulse

control circuit to set the READY flip-flop. The

D register from the

(AB is set by IOP62 generated during a 6062,
6063, 6066 or 6067 instruction.)

Timer (Dl)

load the

accumulator.

IOP72

ElO, the

output is applied to either the XFY Driver Ql or

vector flip-flop.

IOP64

flip-flop

registers which establish the perma-

LDT is also used to load data in the absolute
mode when NAND gate E2 is primed by AB (1).

Resets the Ready flip-flop.
4.6.2 Execute Delay Timer

IOP74

ORed

with

IOP64 to form the

CLOCK pulse to load the D register.

The XDT E9, shown in Figure 4-10, provides a
delay of 20 ±5 microseconds and is actuated by
execute command IOP64. The XDT (1) output
sets

4.5.2 Skip and Interrupt Control Facilities

The KV controller communicates with the
computer via the skip and interrupt circuits of
the timing generator. The circuit consists of CFL
and READY flip-flops E19A and E19B, six logic
gates (El 8, E20A, E20B, E21A, E21B, and E22)
and Interrupt bus driver Q2 and Skip bus driver
Ql. When either CFL or READY flip-flop is set
NAND gate El 8 is enabled and an interrupt
command is applied to the computer. A skip

command is executed when any one of the four

NAND gates of the skip circuit is primed and an
command is applied. IOP72 and IOP52
execution commands reset the READY and CFL
lOPl

flip-flops, respectively.

4.6

TIMING CIRCUITS

the

enabling

READY flip-flop in point mode by
NAND gate E7C which is already

primed by level PT + B7 in this mode. When the
KV controller is in a VM level, PT + B7 is low
and the XDT ( 1 ) output is used to initiate vector
timing functions.

4.6.3

Long and Short Vector Timing Circuit

The vector timing circuit shown in Figure 4-10
provides two hardware timing functions: long
vector, approximately four miUiseconds, and
short vector, approximately 250 microseconds.
Both timing functions are initiated by XDT E9
which starts the ST consisting of series connected monostables E2 and El. The ST introduces a 250-microsecond delay each time it is
pulsed. In long vector mode the ST will time out
after it has cycled sixteen times. In short vector

mode the ST times out after one cycle.
4.6. 1

Load Data Timer

The LDT circuit shown in Figure 4-9 establishes
the time, 100 ±20 microseconds, to load the
4-12

Long Vector Timing
In this mode the L/S and PASS flip-flops are set.
Bit

AC4, which is used

to prime

NAND gate

D/A AND GATE
CONTROL MODULE

LOAD DATA
TIMER (LDT)

+3V

^ DRIVER

\—

ESC
MBIO(l)

MBIOd

)

XFYdOAD Y)
DI(0)TO SKIP
DRIVER
INT CONTROL

T
Dl
100 /tSEC

MBIK!)

ElO
81
KPi

XFX (LOAD X)

V->_

10P64

A C3C

ABd

Load Data Timer (LDT), Simplified Logic Diagram

Figure 4-9.

EISA directly and NAND gate E6A after invererter E15B is low. Execute command
IOP62 sets the L/S flip-flop and resets the ^ 16
Counter. The L/S (1) output along with AC4 (1)
primes NAND gate E6A and is ANDed by
execute command IOP64 to set the PASS
flip-flop. The Pass (1) output of the flip-flop
primes NAND
preconditioning
necessary
gate

)

E5B which establishes the

disables

NAND gate

E5B and

the Pass (0)

output primes NAND gate
(1)

E5A. The final ST
output, which occurs approximately 250

microseconds after the PASS flip-flop is reset is
ANDed with the Pass (0) output by NAND gate

E5A to set the READY flip-flop. The output of
the ST in this mode is a positive going level four
milliseconds in duration which is taken at the

timing. The XDT (1) from the XDT is applied to

output of each of its monostables and applied to
OR gate E6B. The output of the OR gate is

OR gate E7D to uaitiate the ST and to

integrated by resistor R17 and capacitor C20 to

pin 10

for

long

vector

enter one count into the + 16 Counter. This
cycle is repeated until 16 counts are entered into
the

counter.

After the

sixteenth

pulse,

the

out the spikes caused by the propagation
delay time in cycling and the delay in triggering

filter

of monostable El by monostable E2.

counter resets the PASS flip-flop which, in turn,
disables NAND gate E5B and the Pass (0) output

primes

NAND gate E5A. The final ST (1)

Short Vector Timing

output, which occurs approximately 250 micro-

seconds

after

the

PASS

flip-flop

reset

ANDed with the Pass (0) output by NAND gate
E5A to set the READY flip-flop. The output of

mode the L/S and PASS flip-flops are
reset; hence, NAND gate E5B is inhibited and
NAND gate E5A is primed. After the ST is
In this

4-13

initiated as described in the previous paragraph,

ary levels of each of the flip-flops of the buffer.

the ST will time out after one cycle and set the

[Transistors

READY flip-flop since there is no return path to

lected,

verse

the ST.

Q13 through Q22 are specially se-

matched

transistors operating in an in-

mode as saturating switches. Replacement

of a faulty transistor will require replacement of
an entire set of four (Q13 - Q17 orQ18-Q22).
4.7 DIGITAL-TO-ANALOG AND ANALOGTO-DIGITAL CONVERSIONS

The specifications on these transistors are listed
on the circuit schematic for the A612 in Chapter
7.

4.7.1

Digital-to-Analog Converter

The

D/A

4.7.2 Analog- to-Digital Converter

shown

converter,

Figure

4-11,

produces an analog voltage that corresponds to

By adding a comparator, a NAND gate (skip

an applied 10-bit binary word, accumulator bits
AC2 through ACll. The data word conversion

control) and a clock, as

corresponds to the following:

shown in Figure 4-11,

D/A converter discussed above becomes a
successive approximation type A/D converter
the

which converts the X and Y analog outputs of
Data Word

Analog

(octal)

Voltage

1000

making a bit-by-bit comparison starting with the
most significant bit to determine its digital

0000

-2V

value. This comparison is accomplished by alge-

0777

-4V

-4 volts) and the output of the

the

AFG to a

10-bit binary word. The D/A
converter operates by repeatedly dividing the
possible input voltage (AFG output) in half and

braically

AFG

(±1 volt) at
the inverting input of comparator K2 and com-

paring

The circuit consists of a

summing the output of the D/A (0 to

10-bit buffer, a preci-

sion resistor network and operational amplifier

Kl. The buffer stores the data word from the
The precision resistor network,
consisting of resistors R68 through R77, is a
binary weighted summing network with R68
accumulator.

representing the most significant bit and

R77

the least significant bit.

ground reference at the nonEach leg of the comparator is
precisely weighted to compensate for the disparit

inverting input.

ity in the voltage range of the

AFG output and

the output of D/A converter. (The cause of this
disparity will be discussed later in the description of the sample and hold.) When the algebraic

sum of the two signals is less than ground (D/A
output is less than or equal to the AFG output),
the

The precision resistor network and operational
amplifier comprises a scaling adder such as the

one described in paragraph 4. 1 .3 with a common
source voltage. The input current (Ij) seen at the

comparator produces a positive output
which primes skip control, NAND gate E20A.
Through the successive approximation subroutine, instruction

6073, the bit

entered and

stored in the AC.

input of the operational amplifier is, therefore,
the algebraic

sum of the current in each leg of

the precision resistor network; and from the

SAMPLE AND HOLD

same discussion, the input current is equal to the
output or feedback current. Hence, the output

4.8

current is the analog equivalent of the data word

As previously discussed the SH register is an
analog voltage storage device which upon a load

stored in the buffer.
establishes the

signal

The operational amplifier
range and converts the

output current signal to a voltage signal.

The transistors, Q13 through Q22, in each leg of
the precision resistor network, equate

4-14

the bin-

data command charges to a dc voltage
value
corresponding to the output of the D/A; hence,
the data word stored in the input buffer register.'
The output of the D/A ranges from to -4 volts.
The analog value stored in the SH, however.

+3V

AC06(

MBIKI)

AC04(

)

MB!0(! )

I0P64

SET
READY
FLAG

TO
-f

20 /L SEC

C20 -L

DRIVER
CIRCUITS

:CUTE DELAY
IMER (EDT)

Figure 4-10. Execute Delay Timer, Long/Short Vector and Vector

Continue Timing Circuit, Simplified Logic Diagram
^1^5/4-16

I/O

BUS

BUS
^^vjiviru

ivitiviunT

TO ACCUMULATOR

'Xj

FROM

Vref

lOT CONTROL

(+2. 45V)

10-BIT

PRECISION
RESISTOR

CLI

DATA WORD

FOR
CONVERSION

THRU

B2)

NETWORK

FROM
ACCUMULATOR

Figure 4-11. Digital-to-Analog/Analog-to-Digital Converter, Functional Block Diagram

ranges from -2 to +2 volts. The relationship of
the data

word stored in the input data register

We shall see in the subsequent detail discussion
how this transition is accomplished.

and the respective output of the D/A and the
value stored in the SH is:

The circuit configuration for both the X and Y
Data Word
(octal)

D/A
Voltage

1000

0000
0777

SandH
Voltage

closes providing a low inpedance path for output

of input buffer El to E2. Capacitor CI (storage
capacitor) charges to the applied voltage level.

-2

-4

SH is identical; therefore, only X SH is covered
When an X load data command is applied to Ql (hold switch), the switch

in this discussion.

-2

The stored charage on CI is reflected back to
the input (El) through inverter E3 and R5.

4-17

SH equals the D/A voltage with +2 volts added.
This is the required method of loading the SH

{±2V)
FROM OUTPUT

for point mode, circular vector mode, and linear

OF SH

relative vector mode.

For absolute linear vector mode, however, the

R5
lOK

ABS FET Q4 will be closed during the load data

lOK

—w\^

period. Under these conditions, the holding out-

(0T0-4V)

put of the X integrator (E4) will be inverted by
E3 and subtracted from the equivalent ±2v D/A
input voltage by adder E. Thus, the SH output

TO
STORAGE
DEVICE

lOK
.

FROM D/A

will charge to a value equal to the equivalent
„,

"2
II. 5K
L+2.3V

2.45V

D/A input voltage minus the present voltage on

REF
"i

the integrator. See paragraph 4.1 1.2 for a discussion of how this voltage produces absolute hnear

200

vectors.
R2
I.2IK

4.9

INTEGRATORS

The integrator circuit shown in Figure 4-13,
upon an SV or LV command, integrates the

analog value stored in the associated X or Y SH.

E4 and E9
Sample and Hold Register Input Buffer,
Simplified Schematic Diagram
Figure 4-12.

Input buffer El is a three-input adder as shown
in Figure 4-12. The input seen at El is the
algebraic sum of the output of D/A (R4), SH

feedback (R5) and +2.3-volt reference voltage
(R3) which is established by the biasing arrangement of Rl and R2. Initially, assuming the SH
has been reset, the feedback input is

volts. The

input is, therefore, the algebraic sum of the D/A
output and reference supply. If we refer to
formula (4) or paragraph 4.1.3, we see that the
reference voltage and the value of R3 are so
selected to cause the output of El to range from

+2 to -2 volts in direct proportion with the
-4 volt output range of the D/A.

As previously discussed the charge on CI

•

are

the

and

integrators,

respectively. The integrators are isolated by their

respective

input and output FET's, therefore,

the charge on the integrating capacitors, C2 (X)
and C6 (Y), are effectively stored values. For the

operation

of integrators, refer to paragraph

4.1.2.

4.10

OUTPUT DRIVERS

The output drivers are unity-gain operational
amplifiers. E5 and El
are the X and Y output
drivers, respectivley. The input impedance to
each of the amplifiers consists of a resistor and a

FET. The resistance exhibited by the FET, when
closed, and the value of fixed resistor is approximately equal to the respective output resistor.
4.11

4.11.1

MODES OF OPERATION
Point Mode

reflected back to the input, making R5 another
leg in the summing network. (Refer to paragraph

In the point

The reflected signal tends to maintain the
volts by reflecting back a
output of El at
current corresponding to the amount of drift in

of their respective output drivers, bypassing the

4. 1.3.)

mode of operation, FET's Q9 and
Q25 are closed and the analog value stored in
the X SH and Y SH are appUed directly to input

the SH, thus maintaining the voltage held by the

integrators.

SH at the analog equivalent of the word stored
in the D/A buffer.

4.11.2 Vector Mode

The above discussion assumed that the ABS FET
gate (Q4) was open. Hence, the ouptut of the
4-18

In a vector

mode of operation VM FET's Qll

and Q24, which place the output

X and Y

(0,0)

ORIGIN

*1 h-V;xc

Y SAMPLE AND

HOLD
X IN ItOKAlUK

STORAGE
OPERATIONAL
AMPLIFIER

INVERTER

QI5

R40

R46

I8.2K

-A'VV

S^iHg)

XOUT

X SAMPLE AND HOLD

STORAGE
OPERATIONAL
AMPLIFIER

INVERTER
RI6

—vvv

^-M

Y OUT

0.27

Y INTEGRATOR

Figure 4-13. Analog Function Generator in Circle Mode Configuration and Circle Generation Geometry

4-19

drivers in circuit with either the

SH registers or

sinusoidal signals

90 degrees out-of-phase with

tion generator generates either linear or circular

one another, i.e., the X and Y inputs are functions of the sine and cosine, respectively. If both

vectors.

the X and Y signals are referenced to

both, are closed. In this mode, the analog func-

circle

volts, the

described about the origin (0, 0) or

center of the viewing screen. On the other hand,

Linear Vectors

some
In a linear vector mode,
are in circuit and the

long

all

microseconds)

stages of the

AFG

AFG may generate either

milliseconds)

(4.08

one or both signals are referenced to

if either

vectors.

short

±10
mode,

(275

In long vector

offset voltage, the circle is described about

the coordinates established by the offset voltage.
Figure 4-13 illustrates the relationship of the

coordinates of the center of the circle with
respect to the origin and the

X and Y input

Point P represents the

Q5(X) and Q21(Y) FET's are closed to connect

signals.

SH to the integrator. In short vector FET's
and
Q22 are closed for the same purpose.
Q6

point.

In the linear vector mode, the Analog Function

Obviously, the circuit required to generate a

Generator processes either

circle

the

relative or absolute

circle

starting

Vxc and Vy^ are the offset voltages that

determine the center of the circle.

or arc pattern

an oscillator capable of

vectors. In relative linear vector mode the volt-

providing two outputs at the same frequency

age on the SH, AXj-gi, equals the corrected input

that

D/A

voltage,

voltage to

its

XDA. The

integrator adds this

present holding value of

achieve the new holding value X, (the end point

are

degrees

out-of-phase

with one

another and capable of being offset. This is
precisely the circuit configuration of the AFG in
the circle mode of operation.

of the vector). This end point thus equals:
In

Xi = Xo + Xrei = Xq + XDA

the circle

mode

of operation, the analog

function generator initially operates in a linear
vector mode and stores a set of coordinates in

Thus,

XDA represents a relative increment to

the

X and Y integrators that corresponds to a

the present position of the integrator.

point on the circumference of the circle or arc.

In absolute linear vector mode, the voltage

The coordinates of the center of circle or arc are
then stored in the X and Y SH registers. The

the SH, AXy^Bs, equals the corrected voltage

difference in the value stored in the integrators

from the D/A, (XDA), less the present voltage
held on the integrator, i.e.,

and the SH is the radius of the circle. With both
sets of coordinates stored a circle mode command is applied and the circle configuration of

XabS = XDA-Xo

the analog function generator in the

mode of

operation is as shown in Figure 4-14. The circle

The integrator again adds this voltage to its
present holding value of Xq to achieve the end
point voltage Xj
Xi = Xo + AXabS = Xo + XDA - Xq = XDA
Thus, the

new end point equals the corrected

D/A input voltage directly, producing an absolute address.

Circular Vectors

A circle or arc pattern is displayed on the screen
of the display unit when the X and Y inputs are
4-20

mode FETs (Q12 through Q15) and vector
mode FETs (Qll and Q24) are closed. As
shown, the X and Y integrators are crosscoupled to form a low frequency oscillator
whose frequency is dependent upon the RC

network formed by the respective integrator
capacitor and the resistance in the cross-coupling
network, resistors R24 and R23 for the X
integrator and resistors R61 and R62 for the Y
integrator along with the closed resistance of the
respective FET's. (The potentiometers permit
adjustment of the resistance in the coupling

network to compensate for the variation in
resistance exhibited by the closed FETs in
series.)

The coordinate of the center stored in the Y SH
register

(taken at the output of the storage

joystick can be converted to 10-bit binary words

and stored in the

by the A/D process

operational amplifier and bypassing the inverter

described in paragraph 4.7.2 and, subsequently,

E3) biases (offsets) the summing point of the X
R15 and

placed in the respective

integrator through scaling resistance

desired.

R16; X output from the SH register (taken at
output of the inverter E8) biases the Y integrator through the scaling resistance of R40 and

4.12

SH for line drawing, if

POWER SUPPLIES

R46. Consider now the instant the center mode
FET's are closed (Figure 4-13), the output of

The KV controller contains two regulated power

X integrator (/Ix) appears at the summing
point of the Y integrator. The output of the Y

of which are contained in the

the

integrator is, therefore, the

sum of the second

integral of Ix and the first integral of ly- The

integrator output is inverted by

Y output driver

ElO and appears at the summing point of the X
integrator closing the oscillator loop.

The state-

ment above can be made starting at the output
of the Y integrator and tracing through the X
integrator, so that both X and Y coordinates are

supplies (nominally +1 1.5 and -1 1.5 volts) both

A712 Voltage

Regulator Module. (See Figure 7-4.) Primary ac

power (center tapped 28 volts ac) is supplied to
the module from an external step-dowTi transformer. The module contains a full-wave bridge
two type LM300 regulators (one for
each supply) and two series pass transistors.
Transistors Ql and Q3 are the respective +11.5
and -11.5 volt series pass transistors. A booster

rectifer,

transistor, Q2 is included in the negative supply

double integrated and provide the necessary

to drive series pass transistor Q3.

coordinates of a circle.

regulation references of the respective supplies

4.11.3 Cursor Mode

The output

are set by resistors R2 and R3 and resistors R4

and R5. Transistor Q4 and resistors R6 through

In cursor mode, FET's QIO and Q26 are closed

and the output (position) of the joystick (±1V)
is applied directly to the respective X and Y
driver. (See Figure 7-3.) In this mode of operation the coordinates of the position of the

supply.

provide current limiting for the negative
Capacitors

C8 through CIO filter the

unregulated dc output of the bridge

rectifier.

Capacitors C3, C6, Cll, and CI 2 provide filtering of the regulated output voltages.

4-21/4-22

CHAPTER 5
MAINTENANCE

This chapter is divided into two sections: Introduction and System Maintenance.

Section I covers infor-

mation concemmg the Digital Equipment Corporation's warranty and service policies and
concepts. Section II covers alignment and adjustment, trouble analysis, preventive

maintenance
and corrective mainte-

nance.

SECTION I

INTRODUCTION

5.1

WARRANTY

repair or replacement of the

module and ex-

cludes all costs of shipping, customs clearance,
5.1.1

Modulesand Accessories

or any other related charges.

System Modules

Type B, R, W, M, K and A Modules
System Modules, Laboratory Modules, High
Current Pulse Equipment, G, S, H, Non-Catalog
All

W, M,

All B, R,

K and A Modules shown in

Catalog C-105, as revised from time to time, are
warranted against defects in workmanship and
material under normal use

period

and service for a
of ten years from date of shipment

(providing parts are available).

DEC will repair

W, M, K, or A modules
found to be defective in workmanship or mateor replace any B, R,

rial

within ten years of shipment for a handling

charge of $5.00 or

whichever

10% of list price per unit,

higher. Handling charges will be
from one year after delivery. Not-

applicable

Modules and Accessories are wardefects in workmanship and
material under normal use and service for a
period of one year from date of shipment. DEC
will repair or replace any of the above items
found to be defective in workmanship or
material within one year of shipment. Handling
Flip-Chip

ranted

against

charges

are

available

the purchaser

upon

request. Notwithstanding anything herein con-

tained

to the contrary the

Module Warranty

outside the continental U.S.A. and Canada

withstanding anything herein contained to the

limited to repair or replacement of the module

Module Warranty outside the

and excludes all costs of shipping, customs
clearance, or any other related charges.

contrary,

the

continental

U.S.A. and Canada

limited

5-1

5.1.2 Shipping

All

modules must be returned prepaid to the
Equipment Corporation. Transportation

Digital

charges

covering

the

return

of the repaired

modules shall be paid by the Digital Equipment
Corporation except as required by paragraph
5.1.1. The Digital Equipment Corporation will
select the carrier, but by doing so will not
thereby assume any liability in connection with
the shipment nor shall the carrier be in any way
construed to be the agent of the Digital Equip-

were intended and do not cover products which
have been modified without DEC's approval, or
which have been subjected to unusual physical
or

electrical

stress

or on which the original

marks have been removed or al-

identification

These warranties will not apply; (i) if
adjustment, repair or parts replacement is required because of accident, neglect, misuse, fail-

tered.

ure of electric power, air conditioning, humidity
control, transportation or causes other than

ordinary use, or (ii) if the equipment is installed
by the customer without prior written approval

from DEC, or (Mi) if the equipment is removed
from its location of initial delivery.

ment Corporation. Please ship all units to:
Digital Equipment Corporation

5.2

Module Marketing Services

SERVICE POLICY

Repair Division
Unless explicitly agreed upon by the owner and
the Digital Equipment Corporation, the respon-

146 Main Street
Maynard, Massachusetts 01754

No module will be accepted for credit or ex-

preventive

and

corrective

main-

sibility

for

tenance,

after warranties have elapsed, lies solely

change without the prior written approval of

with the owner of the Type KV Storage Tube

DEC, plus proper Return Authorization number.

Control Unit. Replacement stockpiles, special
tools, test equipment, or other auxiliary equipment listed as a requirement for maintenance in

5.1.3 Systems

manual, will not be supplied by the Digital
Equipment Corporation.

Systems are warranted against defects in workmanship and material under normal use and
service, as discussed below, for a period of three
Not(3) months from the date of installation.

this

withstanding the aforesaid, in the event that
DEC is prevented by causes beyond its control
from properly installing the equipment, the

5.3

period

for

this

warranty

commence on the
delivery, or upon

shall

thirtieth

be deemed to

(30th) day after

installation,

whichever

sooner. DEC's sole responsibiUty under this warranty shall be, at its option, to either repair or
replace any

component which fails during this

period; providing the purchaser has promptly
reported same to DEC in writing and DEC has,

upon inspection, found such components to be
defective. The purchaser must obtain shipping
instructions for the return of any item under

warranty provision. Compliance of such
instructions shall be a condition of this

this

MAINTENANCE CONCEPT

Maintenance is divided into two categories: preventive and corrective. Preventive maintenance is

performed periodically to ensure that the equipment is operating properly. Corrective maintenance, on the other hand, is performed whenever a failure occurs in the course of normal
Controller is
operation. In either case, the

connected in

system

configuration

and

subjected to a rigorous diagnostic self-test routine for detection of improper or marginal operation, in the case of preventive maintenance,
and for the localization and subsequent isolation

of equipment failures, in the case of corrective

maintenance.

warranty.

5.1.4 Other Warranty Conditions

should also be noted that the information
presented in this chapter assumes that maintenance personnel understand the operation of

All above warranties are contingent upon proper

the

use in the appHcation for which the products

peripherals and options on line with the system;

5-2

central

processor unit

(CPU) and other

and,

addition,

are

familiar with

the pro-

in the applicable Computer User Handbook and
ir,

111 \_-iiapi.Ci

^ \ji LiLia puuin^^auiUil.

SECTION !

SYSTEM MAINTENANCE
5.4

PREVENTIVE MAINTENANCE

Visually inspect the equipment for com-

pleteness and general
5.4.1

General

Repaint any

condition.

scratched or corroded areas.

The preventive maintenance procedures for the

KV Controller consists of visual mechanical in-

breaks,

Inspect

all

wiring

and cables for

cuts,

fraying,

wear,

deterioration,

kinks,

spection and running the diagnostic test routine

strain, and

check for marginal operation and system
calibration. Mechanical inspection consists of

replace,

mechanical security. Tape, solder, or

any defective wiring or

required,

cable covering.

checking module seating, clearing, and visual
inspections.

The diagnostic checks are intended

any marginal

isolate

circuit

condition or

intermittent failures so that they can be correc-

components for
switches, connectors, and capacitors.

Inspect

security:

following

the

Tighten or replace as required.

ted.
e.

Inspect

module mounting panels

ail

Operators or maintenance personnel should re-

ensure that each module is securely in its con-

cord data obtained during preventive mainten-

nector.

ance in a log book. Analysis of this data can
indicate the rate

of circuit deterioration and

component degradation so

that

steps

can be

taken to prevent system failure.

allow efficient functioning of cabinet air filters.
diagnostic

routine

should be performed

every 600 equipment operating hours or every
three months whichever comes first. Appreciable

changes in the temperature-humidity environment of the system may require the perform-

ance of the diagnostic

self-test

Inspect

module components for overand faulty solder connections.

Repair as required.

The periodicity of mechanical inspection should
be at least once a month, particularly cleaning to

The

heating, breaks

routine

and

recalibration of the system.

c /I o
j.~T.j

rv:
j.:Ly I a y I lua lib

esting

and

minimum

Performance Tests

Minimum performance tests for the KV Controller are

based on the diagnostic program and the

procedures given below.

When

the

minimum

performance requirements of the graphic display
system are checked the program exercises the
system and detects a KV Controller malfunction

and a visual examination of each display indicates apparent abnormal operation of the controller or display. The

5.4.2 Mechanical Inspection

no malfunction
Perform the following mechanical inspection of
the system to ensure efficient operation:

a. Clean the exterior and the interior of the
equipment using a vacuum cleaner.

KV Controller diagnostic

routine is based on the assumption that there is
in either the interfacing

com-

puter or in the display unit. If the minimum

performance check is not successful, a calibration check should be made.

Whenever a malfunction of the KV Controller is
detected, the diagnostic routine will halt. If the

5-3

program halts, the address register on the interfacing computer console should be consulted.
The address at which the program halts provides

Voltage

AC Input

a key to the apparent malfunction. Accompany-

ing the diagnostic routine is a listing of the halt

H21R2 to H21N2

±2.8V

addresses and a description of the corresponding
fault.

DC Output

Method

J25E1 to Ground
J25B1 to Ground

+ 11.5±1 V
-11.5+1 V

Using the binary loader, load diagnostic self-test

NOTE

MAINDEC-8I-D6 CE-D-(D) into memory

tape

and select starting address 2008 using the switch
registers on the computer console and then start

the program. If a program halt occurs, consult
the Action column of the diagnostic routine.

There exist two distinct grounds in the KV
controller, analog and digital ground. Care

For any halt between address OlTSg and 04428

must be taken in the selection of the
proper ground when performing measure-

refer to the troubleshooting procedure in para-

ments on the KV controller.

graph 5-5.
If the a-c input to the power supply is not with-

in tolerance, the transformer

NOTE

at fault. If the

power supply is not within
power
supply is at fault.
the
tolerance,
d-c output of the

Because there are no lOT control circuit calibration procedures, a halt at

between OlVSg and
04428 is caused by an apparent malfunction in the computer or in the KV

It is

controller control circuit.

tine to determine

any

address

5.5.2

Analog Faults
virtually impossible for the diagnostic rou-

whether the D/A Converter

and Gate Control Logic Module or the Analog
Function Generator Module is at fault when an
5.5

analog halt instruction is encountered. To determine which module is at fault, the iterative

TROUBLE ANALYSIS

Trouble analysis consists of, essentially, isolating
failures to a module of the KV Controller with
the diagnostic routine. Although the diagnostic
routine provides a complete overall check of the

system,

there

may occur

troubles where the

actual module that is causing the failure cannot
readily be isolated.

The subsequent paragraphs

are intended to supplement the diagnostic routine in locating the cause of such failures.

features of the diagnostic routine and an oscillo-

scope or a voltmeter can be used to isolate the
trouble. The Switch Register must be set to the
applicable address and the analog and applicable
gate control signals monitored at the interface of
the two modules. (See figure 5-1.)

If either the

analog or gate control output signals of the D/A

Converter

abnormal, the module should be

replaced. If the output signals are normal, the

Analog Function Generator Module should be
replaced.
5.5.1

Power Supply

A power supply failure is manifested by a

5.5.3 Joystick Controller

complete failure of the analog circuits. To check

To check

the input to, and the output from, the power
supply, connect a voltmeter to the following

oscilloscope or a voltmeter to the output termi-

pins and monitor the voltage at each pin:

nals

5-4

the joystick controller, connect an

indicated in Figure 5-1

and measure the

DieiTAL-TO-ANALOG

MODULE

The display unit must be on line with the
controller, and the diagnostic self-test tape
(MAINDEC-8I-D6 CE-D(B)) loaded into the
CPU. Maintenance personnel need only to run

H25C1(XDA)

the diagnostic routine, as described in paragraph

J21B1

patterns shown in Figures 5-2 through 5-8 at the

ANALOG FUNCTION

ANALOG
SIGNALS

GATE CONTROL

MODULE
D/A OUT(0

H24B1

—

4V)

X OUTPUT (t IV)
(CURSOR)

H25S1
H25U1

5.4.3,

Y 0UTPUT(±1V)

H25V2
H25N2

(CURSOR)

various switch register settings. If the patterns

J21P1

distorted,
the potentiometers specified
should be adjusted until they approximate the

are

-15 VOLT
GATE CONTROL
PULSE

H25J1(XFY)
H25B1(XFX)

J24R1
J24P1
H24U1
J24J1
J24H1

and observe the display unit for the

idealized patterns shown.

NOTE

H25R1 (ABS)
J25F1 (VM)
J25J1 (CUR)
J25K1 (PM)
H25E1 (RST)
»j J25P1 (CM)
*\ J25M1 (LV)
J25N1 (SV)

H24V2
J24F1
J24K1
J24N1
J24L1

When

5.6.1
Figure 5-1. Digital-to-Analog Converter and Gate Logic
Module/Analog Function Generator Module interface

voltage in each axis while operating the joystick

through a full sweep in both the X and Y axes.

the equipment

full

Preliminary Instructions

Control Switch Settings

The control switch settings for the various tests
are given in Tables 5-1 through 5-3.

NOTE

screen
Place the analog function generator on

deflection.

5.5.4

Module Extender W983 for access to
1-tum potentiometers,

Component Part

of these potentiometers

when

a replacement

component

part,

following procedures

shovwi

optimized

are

To troubleshoot to a
patterns

the iterative features of the

a voltmeter can be used to signal trace digital

and pulses and analog signals to isolate a

trouble to a component part. Reference should

be made to the logic diagrams contained in
Chapter 7 and the parts location diagrams in

are

shown

Figures 5-2 through 5-8.

diagnostic routine along with an oscilloscope or

levels

required.

of the potentiometers cited in the

module is not

readily accessible or when a customer desires to

maintain his equipment.

adjustment
is

Unless otherwise noted, the locations

Troubleshooting to a component part may be
necessary

in-

all

The voltage in both the X and Y axes should
range from -0.5 to +0.5 volts for

initially

potentiometers should be
set to mid-range.
stalled,

5.6.2 Test and Adjustment

Analog Function Generator and Timing Generator

Chapter 6 when signal tracing. The module
under test must be installed onto Module Exten-

der W983 for access to test points. Use standard

and Timing Generator potentiometers,
the following procedures should be used. In
these procedures two dots are displayed on the

shop practices to remove and replace component
parts.

initially

adjust

or to verify

the current

adjustment settings of the Analog Function Generator

screen. One dot will remain stationary, while the

5.6

ALIGNMENT AND ADJUSTMENT

There are 27 potentiometers contained in the

KV Controller which require adjustment when
the

equipment

initially

installed

or after

replacement of a component part of module.

other will move in response to adjustments made

on the potentiometers. The vector formed by
the two dots represents the error vector and
indicates the relative adjustment necessary

the

X and Y potentiometer. This error vector is

to be decreased to zero (both dots merging).

5-5

NOTE

Increase the

number in Switch Register 5

to 11 for a longer delay and readjust if necessary

The octal number appearing in Switch
Register 2 to

control

(do not disturb the
settings) is propor-

1 1

and

tional to the delay time between dot

until there

only one point ± 1 dot size when

Switch Register equals 1 OOg

Adjustment of X and Y Sample and Hold Zeros

repetition rates, a tail may appear on

and Circle Mode Zeros - (It will be necessary to
place the A3 1 2 module on an extender card if
readjustment is required.) Turn the VTOl OP-

the display. This is normal and is to be

ERATING LEVEL control fully counterclock-

ignored.

wise.

displays, with Switch Register 11 the
least

significant

bit.

very

fast

When performing initial adjustment only,
remove left side of cover of VTOl and turn both
potentiometers

gain

(R45 and R145, Figure

X and Y Sample and Hold Drift Rates - To

5-13 of 61 1 Manual) fully counterclockwise, and

check the X and Y sample and hold drift rates
perform the following:

turn the two centering potentiometers (R44 and
R144 at bottom right of Figure 5-10 in 611

ERATING LEVEL controls (behind front panel

Manual) to their middle position Put the two
slide switches (SW204 and SW202) at upper
right to their center position, if not previously
accomplished. The control Switch Register settings for the following tests are summarized in
the Table 5-3. The function of the four poten-

access door) to mid range.

tiometer adjustments relative to the pattern of

Start the program at location

2600 with

Switch Register = 2000.
b.

Set

the

INTENSITY and OP-

VTOl

Figure 5-2 are given in Table 5-5.

Adjust X Sample and Hold Drift Rate (R8)
and Y Sample and Hold Drift Rate (R39) until
c.

Start the program at location 3000 with Switch
Register = 0001 and perform the following:

only one point is seen on the screen.

Increase the

number in Switch Register 5

to 11 for a longer delay and readjust if necessary
until there is only one point ± 1 dot when

Switch Register equals lOOg.
Erase the screen with the ERASE switch
on the VTOl as required to clean up the trace.

Adjust

X Sample and Hold Zero (Rl)

and/or Y Sample and Hold Zero (R32) so that
all corners meet ± 1 coordinate (.02 inches).

Integrator Drift Rate

Adjust X Circle Mode Zero (R44) for
circle to be centered along the Y axis.
b.

- To check the integrator
Adjust Y Circle Mode Zero (R63) until the
maximum
circle becomes a dot. It should have a

drift rate perform the following:

Start the

2600 with

diameter of 2 with the center just showing a
non-stored opening, as shown in Figure 5-2.

Two dots should appear on the screen. If

they appear as lines instead, adjust the X and Y
sample and hold zero (Rl and R32) pots until

Adjustments of Circle Mode Rates - The function of the two potentiometers. Circle Mode
Rate 1 (R24) and Circle Mode Rate 2 (R62) is

the lines become dots.

program
=
6000.
Register
Switch

at location

make the pattern, shown in Figure 5-3, a

circle rather than an elipse.

Adjust X Integrator Drift Rate (R17) and
Integrator Drift Rate (R50) until only one

point is seen on the screen.

5-6

Start program at location 3000 Switch Register
= 0002 and perform the following:

M712 until the arc just meets the top of the Y
axis calibration line.

Figure 5-2.

Circle

Mode Zero and X and Y Sample/

Hold Zero, Adjustment Display Pattern

(R24) and Rate 2 (R62)
until the circle is an equal distance from all four
a.

Adjust Rate

Figure 5-3. Circle

Mode Rate, Adjustment Display Pat-

tern

calibration Unes.

Adjust Rate

directions until the

and Rate 2
circle closes

in opposite

and

ail

four

calibration lines touch the edge of the circle, as

NOTE
It

may be necessary

retouch

Sample and Hold (Rl) and Y Sample
and Hold (R32) to obtain an exact
crossing of the four calibration lines at

the center.

Adjustment of the Stroke Timing Generator —
The function of the potentiometer (R7) on

M712 is to adjust the timing used to genreate
arcs correctly as shown in pattern Figure 5-4.

Start the program at location 3000 Switch Register

= 0004 and adjust potentiometer (R7) on

Figure 5-4. Stroke Timing Generator, Adjustment Dis-

play Pattern

5-7

Adjustment of X and Y Absolute Zero and
Absolute Gains — The function of the four
potentiometer

adjustments

relative

Start the program at location 3000 Switch Register = 0020 and perform the following:

the

Adjust X CM Center Gain (R15) until the

pattern of Figure 5-5 are given in Table 5-6.

circle at the right is a dot.

Start the program at location 3000 Switch Register = 0010 and perform the following:

Adjust

Adjust Y CM Center Gain (R40) until the

X Absolute Zero (RIO) and Y

circle at the top is a dot.

Absolute Zero (R41) until the dot in the middle

NOTE

of the cross is minimum size.
b.

Adjust

X Absolute Gain (R20) until the

two

vertical

Hnes are parallel and the upper

left-hand and lower right-hand comers close.
c.

Adjust

Y Absolute Gain (R52) until the

opposite two comers close. All four should be
closed, if not, it may be necessary to retouch

Absolute Gain (R20).

may be necessary to shghtly retouch the settings on X Circle Mode
Zero (R44) to get a perfect dot at the
top, Y Circle Mode Zero (R63) to get
It

perfect

dot

the right, and

Absolute Zero (RIO) and Y Absolute

Zero (R41) to get a perfect dot at the

bottom left.

Adjustment of X and
Gains

Y Circle Mode Center
— The function of the two potentio-

meters,

X CM Center Gain (R15), and Y CM

Adjustment of X and Y Point Mode Zeros and

Center Gain (R40), is to minimize the size of the
three circles to three dots as shown in Figure

Gains — The function of the four potentiometer
adjustments relative to the pattern of Figure 5-7

5-6. They are actually circles with zero radius.

are given in Table 5-7.

Figure 5-5. Absolute Vector, Adjustment Display Pat-

Figure 5-6. Circle

tern

play Pattern

5-8

Mode Center Gain, Adjustment Dis-

Start the program at location 3000 with Switch

Adjust X Point Mode Zero (R27) so that

the dots are an equal distance from the
in^ai iijica

two

anu uic i^cilici UOl lailS On

the center cross line.
b. Adjust Y Point Mode Zero (R58) so that
the dots are an equal distance from the two
outside horizontal lines and the center dot falls

on the center cross lines.
Adjust X Point Mode Gain (R26) so that

vpftiral

flip

Hr^fc

foil

oli^nfT

+Vi^

-t-uTT^

-JT^,^;^^!

outside lines.
d. Adjust Y Point Mode Gain (R55) so that
the horizontal dots fall along the two horizontal

outside lines.

NOTE
5-7. Point

Figure

The four dots appearing outside the
box pattern will be used later to align

Mode

Zero,

Adjustment

Display

Pattern

VTOi gain and positioning potentiometers.

Adjustment of X and Y Short Vector Gains The function of the two potentiometer adjust-

Adjustment of VTOI Gain and Centerings This step centers the pattern and sets the correct
scope gain. (Refer to 611 Manual Figures 5-13
and 5-10 for potentiometer locations.)

ments relative to the pattern of Figure 5-8 are
given in Table 5-8.
Start

program

location

3000 with Switch

Adjust

X Short Vector Gain (R13) until

the two horizontal hnes are equal.

Adjust

Y Short Vector Gain (R48) until

the two vertical lines are equal.

NOTE
Ignore any slight skew which may be
present in this pattern.

Composite Picture - A composite picture of all
adjustments may be obtained by setting Switch

Figure

Pattern

5-8. Short

Vector Gain,

Adjustment Display

5-9

3000 with Switch

Start the program at location

the main potentiometers in the joystick hardware. Depress the cursor interrupt button. The
teleprinter

should

ring.

does not, the

of the

ometers (R44, R45, R144 and R145
VTOl) until the four outside dots of Figure 5-7

computer will halt if an error occurred. If the
computer did not stop (and the bell didn't ring),
the computer never saw the cursor interrupt.

just contact the edge of the storage tube visible

Check that portion of the control logic circuitry

area.

for malfunctions.

Adjust the gain and

potenti-

centering

Replace the left side cover of the VTOl

Adjustment of VTOl Display Characteristics
Push the VTOl TEST SPIRAL switch (red
button at bottom of front panel controls behind
access door) and hold it in until a spiral pattern
appears on the screen. Adjust the INTENSITY
control to approximately two thirds full range
(clockwise) and then adjust the

LEVEL

OPERATING

control until the stored image remains

Adjustment of X and Y Comparator Zeros, X
and Y Comparator Gains - Start the program at
location 2200. A horizontal and vertical axis
should be plotted on the CRT. The current
position of the Joystick should also show on the
screen and a point which will

move with the

cursor.

Move the cursor to the origin (center) and adjust

X Comparator Zero (R93) and Y Comparator
Zero (R83) until the point falls in the center of
the cursor circle. These adjustment controls are

on the A612 D/A Board. Move the

stored and neither bleeds up (blots) or drops out
(decays). This will place the OPERATING

located

LEVEL control about mid range. Then decrease
the INTENSITY control until the spiral just

adjust

X axis and
X Comparator Gain (R86) until the point

falls in

the center of the circle. Move the cursor

begins not to be stored on the outer loop.

to the farthest point on the

cursor to the farthest point on the

Y axis and adjust Y

Comparator Gain (R88) until the point falls in
Adjustment of Joystick Balance Potentiometers
and Checking of Cursor Interrupt Flag - Turn

the center of the circle. Slowly move the cursor
circle around the screen, the point should stay in

the VTOl controls as follows:

the circle at

all

points on the screen. If not,

readjust the appropriate potentiometer until

OPERATING LEVEL - mid range
INTENSITY - mid range
fully

counterclockwise
the

program

location

2000.

horizontal and vertical axis should be plotted on
the CRT. Center the Joystick and turn the

WRITE-THRU INTENSITY

Verification of Digital to Analog CirComparator, and Relative Worth
Analog
cuitry,
of X and Y Sample and Hold and Integrator
Circuits - Start the program at location 1600.
and 1 to the settings in
Set Switch Register

Visual

WRITE-THRU INTENSITY Start

does.

control

the

VTOl until the current position of the Joystick
begins to show on the screen. If not, move it
until it does. The correct setting for WRITETHRU INTENSITY control produces a visible
pointer which does not remain stored
(except at very edges of screen). Adjust the
Balance Pots in the joystick hardware so that the
cursor circle is at the origin (center when the

Table 5-10 for unit to be tested. Switch Register
2 to 1 1 for value to be output to unit under test.

The reference value sent to the selected unit will
appear as returned on the accumulator indicator
lights.

This should agree within 4 counts of the

reference value.

elliptical

and the fuU limits of the
screen may be reached in plus and minus X and
Y. This may require mechanical adjustment of

Joystick

5-10

vertical

Visual Verification

of Stroke Vector Character

Generator - Start the program at location 2400.
Type characters on the TTY keyboard. The
characters should appear on the display unit and

the image should be legible and well formed. If
excessive distortion or noise is present, the

characters may be viewed in the refreshed mode

Error Diagnosis of Program Diagnosible Errors

by raising Switch Register bit 0. The code in the
Switch Register, bits 6 through

1 1 ,

will be the

refreshed character code.

Start

Program at Location 0200

the

program

will

test

the basic

JOT

set

— The
(except

X and Y Sample and Hold and Integrator drift
rates; and

NOTE

then the reset signal zeros the Sample

and Hold and Integrator Circuits. Teleprinter

The typing can be returned to the top left
by using the control K key.

bell will ring after each pass through all tests.

0200 — Depress cursor
interrupt button repeatedly. The bell should ring
Start

the Program at

on the teleprinter each time the button

CAUTION

occurred. If the bell

phosphor of the screen

not rung, the program

does not see the cursor interrupt flag.

The writing intensity may have to be
lowered to prevent possible damage to
the

depressed. If the computer stops, an error has

the

refreshed mode.

5.7

REPAIR AND REPLACEMENT

Repair and replacement of repair parts of KV
Controller require no special instructions. Refer

The refreshed patterns provide convenient test
signals

which can be synchronized using AB(1).

hsts of chapter 6 for parts replacement.

TABLE 5-1. X OR Y SAMPLE AND HOLD OR INTEGRATOR CALIBRATION TESTS
Switch Register

X Sample and Hold
X Integrator
Y Sample and Hold
Y Integrator

1
1
1

Test

Switch Register 2 to 1 1 -D/A value to be sent to circuit

TABLE 5-2. X AND Y SAMPLE AND HOLD AND INTEGRATOR DRIFT RATE
ADJUST ROUTINES USING RESET AND THE CRT
Switch Register

Test

Setting

Sample and Hold Drift Rates
1

Integrator Drift Rates

Do Not Issue Reset

Issue Reset

Switch Register 2 to 1 1 - Delay between plots

5-11

TABLE 5-3. ANALOG FUNCTION GENERATOR AND TIMING GENERATOR
ADJUSTMENT ROUTINES
Switch Register

Test

Setting

Force Short Vector (Write thru)
5

Short Vector Gains

Point Mode Zeros, Point Mode Gains

Circle Mode Gains

Absolute Zeros, Absolute Gains

Stroke Timing Generator

Circle Mode Rates

Sample and Hold Zeros, Circle

Mode Zeros

TABLE 5-4. STARTING ADDRESSES
Address

Routine or Test

0200

lOT Tests, D to A Test, Comparator Test, Sample and Hold and Integrator Drift

1000
2000
2200
2400
2600

X or Y Sample and Hold or Integrator Calibration Tests

Rate Tests, Reset Tests
Joystick balance potentiometers adjust and cursor interrupt test routines

X and Y Comparator Gains and Comparator Zeros Adjust Routine
Character generator exercisor (for determining sources of analog noise)

X and Y Sample and Hold and Integrator drift rate adjust routines xx^ing Reset and
the CRT

3000

Analog Function Generator and Timing Generator Adjustment Routines

TABLE 5-5. FUNCTION OF GAIN AND CENTERING POTENTIOMETERS
Function

Potentiometer

X axis.

X Sample & Hold Zero (Rl)
Y Sample & Hold Zero (R32)

Displaces the pattern along the

X Circle Mode Zero (R44)

The circle inside the smaller triangle will open up

Displaces the pattern along the Y axis.

along the X axis.

Y Circle Mode Zero (R63)

The circle inside the smaller triangle will open up
along the Y axis.

TABLE 5-6. FUNCTION OF X AND Y ABSOLUTE ZERO AND
ABSOLUTE GAIN POTENTIOMETER
Potentiometer

Function

X Absolute Zero (RIO)

Displaces the dot in the middle of the cross line

along the X axis.

Y Absolute Zero (R41)

Displaces the dot in the middle of the cross lines

along the Y axis.

5-12

TABLE 5-6. FUNCTION OF X AND Y ABSOLUTE ZERO AND
ABSOLU lE GAIN POTENTIOMETER (cont)
Potentiometer

Function
Displaces the pattern along the

Y Absolute Gain (R5 2)

Displaces the pattern along the

X axis.
Y axis.

TABLE 5-7. FUNCTION OF X AND Y POINT MODE ZERO AND GAIN POTENTIOMETERS
Potentiometer

X Point Mode Zero (R27)
Y Point Mode Zero (R58)
X Point Mode Gain (R26)

Function

Moves only the dots alon<* the X axis.
Moves only the dots along the Y axis.
Increases or decreases the distance between the

dots on the

Y Point Mode Gain (R55)

X axis only.

Increases or decreases the distance between the

dots on the Y axis only.

TABLE 5-8. FUNCTION OF X AND Y SHORT VECTOR GAIN POTENTIOMETERS
Potentiometer

Function

X Short Vector Gain (R13)

Moves only one of the horizontal lines along the X

Y Short Vector Gain (R48)

Moves only one of the vertical lines along the Y

axis.

TABLE 5-9. FUNCTION OF GAIN AND CENTERING POTENTIOMETERS
Potentiometer

R45
R145
R44
R144

Function
Adjust X gain on VTOl.
Adjusts Y gain on VTOl

Adjust X centering on VTOl.
Adjusts Y centering on VTOl.

TABLE 5-10. SWITCH POSITIONS FOR VISUAL CHECK
Unit

X Sample and Hold
X Integrator
Y Sample and Hold
Y Integrator

Switch Register

Switch Register 1

1
1
1

5-13

XCOMP
ZERO
(R93)

Y COMP.
ZERO
(R83)

X COMP.
GAIN
{R86)

Y COMP.

GAIN
(R88)

Adjustable Parts Location
Figure 5-9. Digitai-to-Analog Converter and Gate Logic Module A612,

5-14

Diagram

xsv

XABS

YABS

GAIN

ZERO

{R13)

(R20)

(RIO)

(R41)

XPM

YSV

GAIN

(R26)

(R48)

YPM
ZERO
(R58)

XPM

YCM

XCM

ZERO

(R27)

(R63)

(R44)

Figure 5-10. Analog Function Generator Module A312, Adjustable Parts Location Diagram

5-15

STROKE
TIMING
ADJ
R7

R18

Figure 5-11. Timing Generator Module IV1712, Adjustable Parts Location Diagram

5-16

CHAPTER 8
REPAIR PARTS LISTS

Controller. The parts are listed in
of the
This chapter Usts the replaceable parts of the modules
data, such as, DEC stock number and
alphanumerical order according to reference designation. Pertinent
provided for each part. Table 6-1 is a
manufacturer's type or part, number or both and descriptions, are
schematic diagram and parts location
associated
the
cross reference list for location of the parts list and
modules and equipment are not
optional
diagram for each module of the controller. Repak parts lists for
applicable instruction manual hsted in
provided. For repair parts data of optional equipment, refer to the
the Related Documents paragraph of the Introduction.

NOTE:

Unless otherwise specified:
1.

Resistors are expressed in ohms, 1/4 Watt, ±5%.

2. Capacitors are expressed in microfarads.

TABLE 6-1 REPAIR PARTS DATA CROSS REFERENCE LIST
.

Parts

Schematic

Location

Diagram

Parts

Name

Module
Type

List

(Table)

Diagram

(Figure)

M712

6-2

6-1

7-1

Converter and Gate Logic

A612

6-3

6-2

7-2

Analog Function
Generator

A312

6-4

6-3

7-3

Voltage Regulator

A712

6-5

6-4

7-4

Timing Generator
Digital-to-Analog

6-1

— »«._«»

jBjEI

«••*-

.V.

«i*S*-^f

• »•« «• * » 9 ll#

«.-„„. ^ „ *f

.ftg* B0

M «*'<••««*>

#«t#tt«f

MSB-"
S^^^-''Ht-.-#,-,

A W^
••'"^
,.,^.

_-.__-

• «lltt*ft

• «IP«||J|.

^•«,^#-

.'1t'«%«..«

.•#».,«.

I
'.'.fen

Figure 6-1. Timing Generator Module M712, Parts Location Diagram

6-2

ll7

TABLE 6-2. TIMING GENERATOR MODULE, M712 REPAIR PARTS LIST
Ref

DEC. Stock

MFR. Type

Desig

No.

or Part No.

10-00011

C2 and C3
C4

10-02630

CAPACITOR, 47 pfd
CAPACITOR, MYLAR, 0.015
CAPACITOR, 0.0022
CAPACITOR, MYLAR, 0.015
CAPACITOR, 1.0
CAPACITOR, 0.01
CAPACITOR, .001

10-00055

C5
C6
C7 thru CI

10-02630

C20

10-00043

19-09487

Description

10-01776

10-01610

9601

INTEGRATED CIRCUIT

(Fairchild)

19-09487

9601

INTEGRATED CIRCUIT

(Fairchild)

19-05547

SN7474N

INTEGRATED CIRCUIT

(Texas Instrument)

19-09004

SN7402

INTEGRATED CIRCUIT

(Texas Instrument)

19-05575

SN7400

INTEGRATED CIRCUIT

(Texas Instrument)

19-05576

SN7410

INTEGRATED CIRCUIT

(Texas Instrument)

19-05575

SN7400

INTEGRATED CIRCUIT

(Texas Instrument)

19-09487

9601

INTEGRATED CIRCUIT

(Fairchild)

19-09487

9601

INTEGRATED CIRCUIT

(Fairchild)

ElO

19-05547

SN7474

INTEGRATED CIRCUIT

(Texas Instrument)

Ell

19-09054

SN7493

INTEGRATED CIRCUIT

(Texas Instrument)

E12

19-05575

SN7400

INTEGRJlTED CIRCUIT

(Texas Instrument)

E13

19-09004

SN7402

INTEGRATED CIRCUIT

(Texas Instrument)

E14

19-05576

SN7410

INTEGRATED CIRCUIT

(Texas Instrument)

E15

19-09004

SN7402

INTEGRATED CIRCUIT

(Texas Instrument)

E16

19-05577

SN7420

INTEGRATED CIRCUIT

(Texas Instrument)

E17

19-05575

SN7400

INTEGRATED CIRCUIT

(Texas Instrument)

E18

19-05575

SN7400

INTEGRATED CIRCUIT

(Texas Instrument)

E19

19-05587

SN7473

INTEGRATED CIRCUIT

(Texas Instrument)

E20 thru E22

19-05577

SN7420

INTEGRATED CIRCUIT

(Texas Instrument)

E23

19-09371

LM300

INTEGRATED CIRCUIT

6-3

TABLE 6-2. TIMING GENERATOR MODULE, M712 REPAIR PARTS LIST (cont)
Ref

DEC. Stock

MFR. Type

Desig

No.

or Part No.

Ql and Q2

15-05302

15-09390

2N4274
2N4036 (RCA)

13-00295

R2
R3 and R4
R5
R6
R7

13-01401

13-00365
13-03313
13-05128

13-09409

Type 78 PR

Description

TRANSISTOR
TRANSISTOR

RESISTOR, fxd, 330
RESISTOR, fxd, 750
RESISTOR, fxd, .IK
RESISTOR, fxd, 12.1K, ± 1%, l/8w
RESISTOR, fxd, 5.62K, ± 1%, l/8w
POTENTIOMETER, 15 turns, 20K

(Helitrim)

R8
R9
RlOandRll
R12
R13
R14andR15
R16
R16
R17
R18

13-03155

13-09417

13-00510
13-02388
13-00295
13-01401

13-00295
13-00295

13-00250
13-09150-06

Type 62 PR
(Helitrim)

6-4

RESISTOR, fxd, 21. 5K, ± 1%, l/8w
RESISTOR, fxd, 27.4K, ± 1%, l/8w
RESISTOR, fxd, 33K, ± 10%, l/4w
RESISTOR, fxd, 2K
RESISTOR, fxd, 330
RESISTOR, fxd, 750
RESISTOR, fxd, 330K
RESISTOR, fxd, 330
RESISTOR, fxd, 150
POTENTIOMETER, 50K

HIS PAGE PURPOSELY LEFT BLANK

6-5

Figure 6-2. Digital-to-Analog Converter and Gate Logic Module A612, Parts Location Diagram

6-6

TABLE 6-3. DIGITAL-TO-ANALOG CONVERTER AND GATE LOGIC MODULE A612,
DCPATD DAPTC T TCT
Ref

DEC. Stock

MFR. Type

Desig

No.

or Part No.

CI thru C7, CI 2

10-01610

C8,C11
C9
CIO

10-01776

10-00067

11-00123

IN750

D2
D3

11-00114

D664
D664

19-09050

19-05575

19-09050

19-05575

CAPACITOR, 0.01
CAPACITOR, 1
CAPACITOR, 47 pf
CAPACITOR, 6.8

10-00079

11-00114

Description

SN7475N

SEMICONDUCTOR DEVICE
SEMICONDUCTOR DEVICE
SEMICONDUCTOR DEVICE

INTEGRATED CIRCUIT

(Texas Instrument)

SN7400N

INTEGRATED CIRCUIT

(Texas Instrument)

SN7475N

INTEGRATED CIRCUIT

(Texas Instrument)

SN7400N

INTEGRATED CIRCUIT

(Texas Instrument)

19-09050

SN7475N

INTEGRATED CIRCUIT

(Texas instrument)

19-05576

SN7410N

INTEGRATED CIRCUIT

(Texas Instrument)

19-05576

SN7410N

INTEGRATED CIRCUIT

(Texas Instrument)

19-09498

LM301A

OPERATIONAL AMPLIFIER

(Motorola)

19-09499

LM307

OPERATIONAL AMPLIFIER

(Motorola)

ElO

19-09371

LM307

VOLTAGE REGULATOR

(Motorola)

Ql thruQ12

Q13thruQ17*
Q18 thru Q22*
Q22
Q23
Q24 and Q25
Q26

15-02979
15-03097

2N3638

15-03097
15-09390

15-09374
15-05302

13-00365

R2
R3
R4
R5
R6
R7
R8
R9

13-02388
13-00496
13-00426
13-00365

13-02388
13-00496

13-00426
13-00365

2N4036
2N5459
2N4274

TRANSISTOR
TRANSISTOR
TRANSISTOR
TRANSISTOR
TRANSISTOR
TRANSISTOR, FET
TRANSISTOR
RESISTOR, fxd, IK, ±5%, l/4w
RESISTOR, fxd, 2K, ±5%, l/4w
RESISTOR, fxd, 15K, ±5%, l/4w
RESISTOR, fxd, 2.7K, ±5%, l/4w
RESISTOR, fxd, IK, ±5%, l/4w
RESISTOR, fxd, 2K, ±5%, l/4w
RESISTOR, fxd, 15K, ±5%, l/4w
RESISTOR, fxd, 2.7K, ±5%, l/4w
RESISTOR, fxd, IK, ±5%, l/4w

6-7

TABLE 6-3. DIGITAL-TO-ANALOG CONVERTER AND GATE LOGIC MODULE A612,
REPAIR PARTS LIST (cont)

6-8

Ref

DEC. Stock

MFR. Type

Desig

No.

or Part No.

RIO

13-02388

Rll

13-00496

R12
R13
R14
R15
R16
R17
R18
R19
R20

13-00426

R21

13-00365

R22
R23
R24
R25
R26
R27
R28
R29
R30

13-02388

R31

13-00496

R32
R33

13-00426

R34
R35
R36
BG7
R38
R39
R40

13-02388

R41

13-00365

R42
R43
R44
R45
R46
R47
R48
R49 thru R58
R59
R60

13-02388

R61

13-00417

R62 thru R67
R69
R70

13-02388

R71

13-05513

R72
R73
R68

13-05514

13-00365

13-02388

13-00496
13-00426
13-00365

13-02388
13-00496
13-00426

13-00496

13-00426
13-00365

13-02388

13-00496
13-00426
13-00365
13-02388

13-00365

13-00496

13-00426
13-00365

13-02388

13-00496

13-00426

13-00496

13-00426
13-00365

13-02388
13-00496

13-00426
13-01320

13^0444
13-00426

13-05511

13-05512

13-05516
13-05510

Description

RESISTOR, fxd, 2K, ±5%, l/4w
RESISTOR, fxd, 15K, ±5%, l/4w
RESISTOR, fxd, 2.7K, ±5%, l/4w
RESISTOR, fxd, IK, ±5%, l/4w
RESISTOR, fxd, 2K, ±5%, l/4w
RESISTOR, fxd, 15K, ±5%, l/4w
RESISTOR, fxd, 2.7K, ±5%, l/4w
RESISTOR, fxd, IK, ±5%, l/4w
RESISTOR, fxd, 2K, ±5%, l/4w
RESISTOR, fxd, 15K, ±5%, l/4w
RESISTOR, fxd, 2.7K, +5%, l/4w
RESISTOR, fxd, IK, ±5%, l/4w
RESISTOR, fxd, 2K, +5%, l/4w
RESISTOR, fxd, 15K, ±5%, l/4w
RESISTOR, fxd, 2.7K, ±5%, l/4w
RESISTOR, fxd, IK, ±5%, l/4w
RESISTOR, fxd, 2K, ±5%, l/4w
RESISTOR, fxd, 15K, ±5%, l/4w
RESISTOR, fxd, 2.7K, ±5%, l/4w
RESISTOR, fxd, IK, ±5%, l/4w
RESISTOR, fxd, 2K, ±5%, l/4w
RESISTOR, fxd, 15K, ±5%, l/4w
RESISTOR, fxd, 2.7K, ±5%, l/4w
RESISTOR, fxd, IK, ±5%, l/4w

RESISTOR, fxd, 2K, ±5%, l/4w
RESISTOR, fxd, 15K, ±5%, l/4w
RESISTOR, fxd, 2.7K, ±5%, l/4w
RESISTOR, fxd, IK, ±5%, l/4w
RESISTOR, fxd, 2K, ±5%, l/4w
RESISTOR, fxd, 15K, ±5%, l/4w
RESISTOR, fxd, 2.7K, ±5%, l/4w
RESISTOR, fxd, IK, ±5%, l/4w
RESISTOR, fxd, 2K, ±5%, l/4w
RESISTOR, fxd, 15K, ±5%, l/4w
RESISTOR, fxd, 2.7K, ±5%, l/4w
RESISTOR, fxd, IK, ±5%, l/4w
RESISTOR, fxd, 2K, ±5%, l/4w
RESISTOR, fxd, 15K, ±5%, l/4w
RESISTOR, fxd, 2.7K, ±5%, l/4w
RESISTOR, fxd, 1 .2K, ±5%, l/4w
RESISTOR, fxd, 3.9K, ±5%, l/4w
RESISTOR, fxd, 2.7K, ±5%, l/4w
RESISTOR, fxd, 2.2K, ±5%, l/4w
RESISTOR, fxd, 2K, ±5%, l/4w
RESISTOR, fxd, 4K ±0.01%, .3w
RESISTOR, fxd, 8K, ±0.01%, .3w
RESISTOR, fxd, 16K, ± .01%, .3w
RESISTOR, fxd, 32K, ± .1%, l/8w
RESISTOR, fxd, 64K, ± .1%, l/8w
RESISTOR, fxd, .2K +01%, .3w

TABLE 6-3. DIGITAL-TO-ANALOG CONVERTER AND GATE LOGIC MODULE A612,
DCD Air) T> AUTO T TOT r^^-n+\
Ref

DEC. Stock

MFR. Type

Desig

No.

or Part No.

R74
R75
R76
R77
R78
R79
R80

13-05517
13-05518
13-05519

R81

13-02388

R82
R83

13-03155

RESISTOR, fxd, 128K, + 1%, l/8w
RESISTOR, fxd, 256K, + 1%, l/8w
RESISTOR, fxd, 512K, ±1%, l/4w
RESISTOR, fxd, 1024K, ±1%, l/4w
RESISTOR, fxd, 6.81K, ±1%, l/8w
RESISTOR, fxd, 2.74K, ±1%, l/8w
RESISTOR, fxd, 1.62K, ±1%, l/8w
RESISTOR, fxd, 2K, ±5%, l/4w
RESISTOR, fxd, 21 .5K, ±1%, l/8w

13-05519

13-04870
13-04868

13-04862

13-09150-04

Description

TYPE 62 PR

POTENTIOMETER, 5K, 1 turn

(Helitrim)

R84
R85
R86

RESISTOR, fxd, 24 .3K, ±1%, l/8w
RESISTOR, fxd, 9.09K, ±1%, l/8w

13-09418
13-04855

13-09410

TYPE 62 PR

POTENTIOMETER, 2K, 1 turn

rt^olitrim"^

R87
R88

RESISTOR, fxd, 9.09K, ±1%, l/8w

13-04855
13-0915-07

TiTE 62 PR

POTENTIOMETER, 2K, 1 turn

(Helitrim)

R89
R90
R91
R92
R93

RESISTOR, fxd, IK, ±5%, l/4w

13-00365

DccTCxfiD
f^A -itn
i'VJwfkSxfcJ X OlV, X./VVL, tJ^\J

13-00295

-yZOL
^-.^

/t/,

1 /4.,„
i/TYT

RESISTOR, fxd, 750, ±5%, l/4w
RESISTOR, fxd, 820K, ±10%, l/4w

13-01401

13-03187
13-09150-06

TYPE 62 PR

POTENTIOMETER, 50K, 1 turn

(Helitrim)

6-9

Figure 6-3. Analog Function Generator Module A312, Parts Location Diagram

6-10

TABLE 6-4. ANALOG FUNCTION GENERATOR MODULE A3 12, REPAIR PARTS LIST
Ref

DEC. Stock

MFR. Type

Desig

No.

or Part No.

Description

CAPACITOR, 0.47, ±10%
CAPACITOR, 0.27, ±2%
CAPACITOR, 0.27 pf, 100 wvdc
CAPACITOR, 0.27 pf, 100 wvdc
CAPACITOR, 0.047, ±10%
CAPACITOR, 0.27, ±2%
CAPACITOR, 0.27 pf, 100 wvdc
CAPACITOR, 0.27 pf, 100 wvdc
CAPACITOR, 10, 20 wvdc
CAPACITOR, 1,35 wvdc
CAPACITOR, 680 pfd, 100 wvdc

10-09463

C2
C3
C4
C5
C6
C7
C8
C9 and CIO
CllthruCl?

10-09464

C18andC19

10-00026

ElthruElO

19-09499

LM307

15-03409-01

2N5459
2N6534B
2N5459
2N6534B

10-01739

10-01739
10-09463

10-09464
10-01739
10-01739
10-04813

10-01776

OPERATIONAL AMPLIFIER
TRANSISTOR, PET

15-09374

15-03409-01

Q3 thru Q6
Q7
ns
V
\^^ +Vii-Ti Vi X A

15-09374
15-09374

TKT:A<iQ
^L-^^~r^^

TR.WSISTOR, FET

Q17

15-03409-01

15-09374

Q20

15-03409-01

Q21 thru Q26

15-09374

2N6534B
2N5459
2N6534B
2N5459

TRANSISTOR

Q18andQ19

13-09408

TYPE 78 PR

l-XJJ.

W-

TRANSISTOR
TRANSISTOR, PET

TRANSISTOR

TRANSISTOR, FET

TRANSISTOR
TRANSISTOR, FET
POTENTIOMETER, 200, 15 turns

(Helitrim)

R2
R3

RESISTOR, fxd, 1.21K, ± 1%, l/8w

13-02871

13-05338

TYPE 78 PR

POTENTIOMETER, lOOK, 15 turns

(Helitrim)

R4 and R5
R6
R7
R8

RESISTOR, fxd, lOK, ±1%, l/8w
RESISTOR, lOK, + 1%, l/8w
RESISTOR, fxd, 820K, ± 1%, 1/4 w ±10%

13-03312
13-03312

13-03178
13-05338

TYPE 78 PR

POTENTIOMETER, lOOK, 15 turns

(HeUtrim)

R9
RIO

13-03312

Rll

13-02212

R12
R13
R14
R15

13-09416

13-09407

RESISTOR, fxd, 1 OK, ± 1%, l/8w

TYPE 62 PR

POTENTIOMETER, 50K, 1 turn

(Helitrim)

13-09150-08

RESISTOR, fxd, lOK, ± 1%, l/8w
RESISTOR, fxd, 31. 6K, ± 1%, l/8w

TYPE 62 PR

POTENTIOMETER, 500, 1 turn

TYPE 62 PR

POTENTIOMETER, 5K, 1 turn

RESISTOR, fxd, 1.62K, ± 1%, l/8w

13-04862
13-09150-04

(Helitrim)

R16
R17

RESISTOR, fxd, 18.2K, ± 1%, l/8w

13-09412
13-05338

TYPE 78 PR

POTENTIOMETER, lOOK, 15 turns

(Helitrim)

R18
R19

13-09413

13-03187

RESISTOR, fxd, 3.83K, + 1%, l/8w
RESISTOR, fxd, 820K, ±10%, l/2w

6-11

TABLE 6-4. ANALOG FUNCTION GENERATOR MODULE A3 12, REPAIR PARTS LIST (cont)

R20

Ref

DEC. Stock

MFR. Type

Desig

No.

or Part No.

13-09159-03

TYPE 62 PR

Description

POTENTIOMETER, IK, 1 turn

(Helitrim)

RESISTOR, fxd, 2.7m, ± 10%, l/4w
RESISTOR, fxd,19.6K, ± 1%, l/8w
RESISTOR, fxd, 8.25K, ± 1%, l/8w

13-09680

R21
R22
R23

13-09419

R24

13-09150-07

13-09420

TYPE 62 PR

POTENTIOMETER, 2K, 1 turn

(Helitrim)

R25
R26

13-09413
13-09150-04

RESISTOR, fxd, 9.76K, ± 1%, l/8w

TYPE 62 PR

POTENTIOMETER, 5K, 1 turn

(Helitrim)

R27

13-09150-06

TYPE 62 PR

POTENTIOMETER, 50K, 1 turn

(Helitrim)

R28
R29
R30

13-09680

RESISTOR fxd, 2.7m, ±10%, l/4w

13-09414

RESISTOR, fxd, 9.76, ± 1%, l/8w
RESISTOR, fxd, lOK, ± 1%, l/8w
RESISTOR, fxd, 2.7m, ± 10%, l/4w

R31

13-03312
13-09680

R32

13-09408

TYPE 78 PR

POTENTIOMETER, 200, 15 turns

(Helitrim)

R33
R34
R35
R36
R37
R38
R39

13-02871

RESISTOR, fxd, 1.21K, ± 1%, l/8w
RESISTOR, fxd, 11. 5K, ± 1%, l/8w
RESISTOR, fxd, lOK, ± 1%, l/8w
RESISTOR, fxd, lOK, ± 1%, l/8w
RESISTOR, fxd, 820K, ±10%, l/4w
RESISTOR, fxd, lOK, ± 1%, l/8w

13-09415

13-03312
13-03312

13-03187
13-03312
13-05338

TYPE 78 PR

POTENTIOMETER, lOOK, 15 turns

(Helitrim)

R40

13-0915040

TYPE 62 PR

POTENTIOMETER,

5K, 1 turn

(HeHtrim)

R41

13-09150-06

TYPE 62 PR

POTENTIOMETER, 50K, 1 turn

(Helitrim)

R42
R43
R44

RESISTOR, fxd, 2.7m, ±10%, l/4w
RESISTOR, fxd, 1 OK, ± 1%, l/8w

13-09680

13-03312
13-09150-04

TYPE 62 PR

POTENTIOMETER, 5K, 1 turn

(Helitrim)

R45
R46
R47
R48

13-03312

RESISTOR, fxd, lOK, ±1%, l/8w
RESISTOR, fxd, 18.2, ±1%
RESISTOR, fxd, 3 1.6K, ± 1%, l/8w

13-09412
13-09416
13-09150-08

TYPE 62 PR

POTENTIOMETER, 500, 1 turn

(Helitrim)

R49
R50

13-04862
13-05338

RESISTOR, fxd, 1 .62K, ± 1%, l/8w

TYPE 78 PR
(Helitrim)

6-12

POTENTIOMETER, IK, 15 turns

TABLE 6-5. VOLTAGE REGULATOR MODULE A712, REPAIR PARTS LIST
Ref

DEC. Stock

MFR. Type

Desig

No.

or Part No.

CAPACITOR, 47 pf
CAPACITOR, 1,35 V
CAPACITOR, 47 pf
CAPACITOR, 1,35 V
CAPACITOR, 47 pf
CAPACITOR, 100
CAPACITOR, 0.01

10-00011

C2 and C3
C4

10-01776

C6
C7 thru CIO

10-00079

CllandC12

10-01610

11-03441

1N756A

11-03016

MOTOROLA

10-00011

10-04815

El and E2

19-09371

HI and H2

12-02313

11-03016

Q2
Q3
Q4

15-02979

13=09421

13-02941

15-09391

15-02937

13-03303

13-02941

R5
R6
R7
R8
R9

13-03303

13-09422
13-00229
13-00391

13-00229

Description

SILICON DIODE, ZENER DIODE, 1N756A

MDA 942-3

SILICON DIODE BRIDGE

LM300

REGULATOR
HEAT SINK, THERMALLOY, #221 IB

2N4036
2N3638B
2N2270
2N3568

TRANSISTOR
TRANSISTOR
TRANSISTOR
TRANSISTOR
RESISTOR, 2,± 5%, Hw
RESISTOR, fxd, 14.7K, ± 1%, l/8w
RESISTOR, fxd, 2.61K, ± 1%, l/8w
RESISTOR, fxd, 14.7K, + 1%, l/'8w
RESISTOR, fxd, 2.61K, ± 1%, l/8w
RESISTOR, fxd, 5.1
RESISTOR, fxd, 100
RESISTOR, fxd, 1.5K
RESISTOR, fxd, 100

Figure 6-4. Voltage Regulator Module, Parts Location Diagram

6-13/6-14

CHAPTER 7
DIAGRAMS

This chapter contains general reference diagrams that will aid in maintenance and repair of the

TABLE 7-1. LIST OF DIAGRAMS
Page

Figure

Title

No.

No.
7-1

Timing Generator Module M712, Schematic Diagram, M7 12-0-1

7-2

Digital-to- Analog Converter and Gate Logic Module A612,

Schematic Diagram, A6 12-0-1
7-3

7-5

Analog Function Generator Module A3 12, Schematic Diagram,

A3 12-0-1
7-4

7-3

7-7

Voltage Regulator Module A712, Schematic Diagram,

A7 12-0-1

7-9

7-5

General Wiring Sheet for KV8I Modification, KV8I-0-1

7-11

7-6

KV8I Display Control, KV8I-0-0

7-13

7-7

KV8I Control Logic, KV8I-0-2

7-15

7-8

Module Utilization KV8I, KV8I-0-3

7-17

7-9

General Wiring Sheet for KV8I, KV8I-0-5

7-10

KV8I Display Acceptance Procedure, KV8I-0-6

7-11

Performance Specifications for KV8I Controller
and VTOl Display, KV8I-0-7

7-26

Joystick Control Assembly, H306-0-0

7-35

7-18

7-12

7-21

7-1/7-2

I- o-Z!iW

S3
i

;

a
I

THIS SC«E.MAIIC :S fll-^MSHED ONIY FOS T 5^ UNO WMP
CIRCUITS ABE PROPHIETftfiY IN NAruHE AND S-<0UID BE
tDP"RIGHT 1969 BY OIGIlAi. hOUIl-ME^T tOPPOBAIION
S

AA2,BA2
+ 5V

TTT
-1.

_ABI
REG

AAi
t-11.5V

.CIS

;

:=fcCI7

330

2 7.4K

I/3W
1%

AC23C2
ATl.BTi-

GND

.015 MFD

10%
;IMFD

-^1

35V

RI7

D3+04tC0NT«UE

ISO
STK
-'SAA^-f

.„„

ADS
"

[P250V

RI3

330
D2-PTB74-D4. PASS

T
EIO
D

EIO

> R12

?2K

L/S

< RIO

< 3ZiK
lie*

33K

10%

LIL

(02)

E9
C5
OISMFO

C4
22CaMMF!

10%

250V

-hso.t

—

PrD2>Bf D2<0HER0»PASS D4

02
2N4274

CFL..

READY

C EI9

I0P64+I0P74

U"W

2N4274
/J>k 2N4;

^Vn,/skip

iNITIALI2EtlOP52

EI8^

I0P5I CFL H0P53 KBRET
+I0P7I READY+I0P73-C0MP

WITIAHZE4-IOP72f I0P64

UNLESS OTHERWISE INDICATED
CAPACITORS ARE .OIMFD, lOOV
RESISTORS ARE I/4W 5%
R7 IS HELITRW POT TYPE 78PR
EI,E2,E8,E9 ARE TTiiL960l
E3,EI0 AREDEC7474N
E4,EI3,EI5 ARE DEC7402N
E5,E7.EI2.EI7,EI8 ARE DEC7400N

BEI

BPI

AHI

I0T5

AUI

AT2

BSI

BT2

CLI

XFX

02(11

PT-I-B7

KBRET

lOPI

BD2

BBI

AU2

BVI

I0P41I)

SHORT

BU2

ANI

Did)

CINTR

COMP

MBIO(I)

ARE DEC74I0N
Ell :S DEC7493N
EI6,E20,E2I,E22 ARE DEC7420N
E5, EI4

EI9 IS DEC 7473
E23 IS LM300
PINS ON Ell- GHD

ON EII- + 3V
PIN 4 ON EI9>t5V
PIN II ON EI9 >CND
PIN 10

TRANSISTOR & DIODE CONVERSION CHART

PIN 7 ON EACH IC (EXCEPT Ell, EI9I-GND
PIN 14 ON EACH IC (EXCEPT Ell, ElSWiSV

^'m^c S.
?**^>^
'^.kJm

7/v/if

TIMING GENERATOR M7I2
,

EQUIPMENT
CORPORATION

MINTED CIRCUIT REV

Figure 7-1. Timing Generator Module IVI712,

Schematic Diagram, M71 2-0-1

7-3

Figure 7-2. Digital-to-Analog Converter and Gate Logic Module A61 2,

Schematic Diagram, A6 12-0-1
7-5

THIS SCHEMtllC IS rURMSHE D QNL1 FOB TEST AND MAINTENANCE PUftPOSES. TM
ClRCUilS *HE PROPftlEIflBY iri NATURE AMD SHOULD SE TREATED ACCOROINGLV
COPYRIGHr Ift69 8* OICnAL EQUIPMENT COPPOBATION

UNLESS OTHERWISE INOtCATED:
CAPACITORS ARE 1MF0 35V
El- ElO ARE LM507

TRANSISTORS ARE 2N 5459 FET
RESISTORS ARE 1%, I/8W
Ri,R8,RI7,R32,R39,R50 ARE HELITRIM POT TYPE 78 PR
ALL OTHER POTS ARE HELITRIM TYPE 62 PR

GENERATOR
SIZE

number

IcooeI
I

A312-0-I
I

PKtNTEO CIRCUIT KV

[E]

III!

Figure 7-3. Analog Function Generator Module A312,

Schematic Diagram, A31 2-0-1
7-7

this schematic is furnished only for test and maintenancc purposes. the
circuits are proprietary in nature and should be treated accordingiv.
Copyright i9K9 by digital equipment corporation

+ 11. 5V

47MMF
lOOV

TO F9IX TRIAD <

TRANSFORMER

Tic

2.6I.K

/aw

IMFD

35V

17.

V) >J
o
3- ri^
(D
0)

<
o
I4 7K

I/8W

O •8
n)

1«

>
VI

OIMFO

—•

finu

lOOV

UNLESS OTHERWISE INDICATED

s
o
a
9
^
>
^
-A
ro

CAPACITORS ARE I00MFD20V
E^E2 ARE LM300

RESISTORS ARE 1/4 W

-±:.

IMFD

1 '"^

? I/8W
\

dZfM^

TRANSISTOR 4 DIODF CONVERSION CHART

VOLTAGE REGULATOR
A7I2

EQUIPMENT

CORPORATION

PRINTED CIRCUIT REV.

DEC FORM NO

DEC FORM NO
RA104

Figure 7-5. General Wiring Slieet for KV8I Modification,

KV8I-0-1

7-11

- I8A>f 'Vfia
Tn;* dfiwirj »nO ipKFficrtiori. h«nKP, ite Bw prop- t
erty of Digrwl EauiDnieit Coipoiafitm »n<i ifnH not ba I
r«(H«ai»c»(l or cotued or used m whota or in part at

NOTES-

the btus 'v Thii fflinuficturc or uhi of itarm without
I,

00 NOT CifT TSAMSFORMER
LEADS MOT UF-ED.TAPEl EMDS

WHT ) EXISTING
J8I FAN

WIRING

SEE DETAIL B
-FORIVITG OF TRANSFORMER

USE EXITING HOLES IN FAN HSG.

SECTION A-A

JOY STICK

H306

o 7 SECONDARY

PRIMARY

'WHT^ZZAWS/A AC INPUT

RED

gr RED'ZZAWG/
BLK/Y EL-,
EL^

^/SEE NOTEI

GRN/BLKJ

^^'^

<,
SEE NOTE"

TO
END FAN

DETAIL B

risST js£o ON opt;ivwd£l

KV8I
DATE

UNLESS OTHERWISE SPECIFIED
UNLESS OTHERWISE SPECIFIED
DIMENSION IN INCHES

^^;.T^^

TOLERANCES
DECIMIUS

FOACTIONS

s oos

= 1/e*

ANGLES
- o-M-

P M E NT
IEQU
CORPORATION

KV8I
CONTROL

mA.
"wMxJL- T^-i,
RRSTU5ED0N
-f
SCALE

MQME.

PV^

FINAL SURFACE gUALiTY
REMOVE BUdftS AND BREAK SHMP

COflNERS

mum

DISPLAY

NUMBER

SIZE CODE

DUA KV8I -0-0
""1^1

Figure 7-6. KV8I Display Control, KV8I-0-0

7-13

Figure 7-7. KV8I Control Logic, KV8I-0-2

7-15

1
Thli drtwlng and ipKitlcatlont, tiirvin, ara lh« proparty of Dfg'tal Fqulpmtnt CarporaDon and ihill not b«
Kfiroducad of copM or utad in whota or In part
th« b«»[i tot ttia mtnulactun or uto of Kwni wfttmirt
wrltttn pwmliilon.

NOTES
I.

SEE NOTE

VOL

REG

ANAL ANAL

TIMING TIMINC

GEN>

A3I2

A6I2

M7I2
2

2
A7l2
U5AGE

SLOT HJ22 RESERVED FOR KV OF'TION

GEN
d/a

D/A

FUNC FUIMC
GEN GEN

CONV CONV

a
c_
(S

G?"?©
USAGE

CABLE 2
DIG- XOUT

ITAL

SND

WRT
YOUT

ANALOG

o
3

6ND

XCUR
2

<
00

CINTR
ERS/

ERD
ro

YC'UR

<
00

If
c

o
M

KV81
UNLESS OTHERWrSE SPECIFIED

./^

UNLESS OTHERWISE SPECIFIED
DIMENitlON IN INCHES

TOLERANCES
DECIMALS

FRACTIONS

ANGL£S

± .005

± 1/64

± 0'30'

FINAL SURFACE QUAUTY
v/
REMOVE BUnilS AND BREAK SHARP

CORNERS

MATERIAL
-i-

^^M4-

-wm;/-

chiAU
DATE

Usf

fl-ML-KV8I-0

MODULE

Qu PM NT
CORPORATION
;

A-4Sr
M^4vllL~
NEXT HIGHER flSSY

—

-h

'Wj^^^

DATt,

DATE ,

UTILIZATION
KV8I
CODE

NUMBER

MU KV 8 1-0-3

r.V

H2 3C1

J24A1

yp-/:

H23F1

J24S1

XFX"

H2 3H1

J24U1

J33F2

J23T2

lOP 1(1)

INIT

H23M1

D2(l)

H23U1

J24E1

H23U2

H24K2

H23T2

H24V1

LONG

H23M2

J24P2

STK

H23D2

J24M1

AC05(1)

J2 3A1

H24S2

SHORT

J23B1

AC04(1)

J23D1

H24M2

IOP52

J23C1

H24E1

CLl

J23P1

H24K1

erd/ers

J24U2

J21S2

erd/ers

J23S2

J24U2

COMP

J23U2

J24K2

J21K2

WRT

H24M1

J21M1

CUR INTR

J23V1

J21M2

K BRET

J23S1

J23C2

DIGITAL GND

H21H2

J21D2

ANALOG GND

H21F2

J21E2

CUR
YD/A

H24M1

J24L2

H24B1

H2 5M1

Did)

PT + B7

REV.

DATE

CHG. NO.

J23L1

J24N2

DATE

RUSS

K.
APP'D.

4/8/6

DATE

CHK'D.

H24L1

DRN.

REVISIONS

REMARKS

COLOR

TO PIN

FROM PIN

SIGNAL NAME

RUSS

4/8/6

ENG.

DATE

PROJ. ENG.

DATE

nnniiiiii equipment
CORPORATION
HCJHllHlM MAYNARD, MASSACHUSETTS
E DmnUEJU
TITLE

^ C kl C n A

v
.

PROD.

IXIIDIKIO
Yvirvii-vvj

CUCCT
^iii_i-i

FOR

DATE

vaciNt.r\Mi.

KV8I

FIRST USED ON

SCALE

SHEET
DEC FOR M NO.

DRA 104

7-18

SIZE CODE

#
#
1

A WL

Of^

NUMBER

KV8T-0-5

DIST.

i
Figure 7-9. General Wiring Sheet for KV8I, KV8I-0-5 (Sheet 1)

REV.

i
5 »

SIGNAL NAME

FROM PIN

TO PIN

XD/A

H25M1

H25C1

ABS

H24U1

H25R1

CURG

J24H1

J25J1

J24J1

J25F1

H24V2

J25K1

J24L1

J24N1

J25M1

XFX

J24P1

H25B1

XFY

J24R1

H25J1

J24K1

J25P1

RST

J24F1

H25E1

RATE

J24M2

J24T2

X OUT

J24V1

J25U1

X,OUT

J25U1

J21B1

Y OUT

J241S72

J25N2

Y OUT

J25N2

J21P1

CUP.

H25S1

J21H2

Y CUR

H25V1

+3V

D10E2

E^9M1

B0qv]

E09L2

E09M1

E09P1

E^9P2

COLOR

REMARKS

Ci
of or

operty whole
ssion.

In )erml

td [
he

J25N1

use
are

tten

•
3
£00
'5.

c J; S
™
OTJ III

i
re sail
and

not
wing

ture

2«g

ifi

J21T2

REMOVE IF PRESE-NT

+3V
lOP 1

(6)

E09M2

E19R2

lOP

(0)

E09R1

E19U1

lOP 4

(0)

E09R2

E19V1

REV.

DATE

CHG. NO.

DATE

DRN.

REVISIONS

K.RUSS
APP'D.

1/8/69
DATE

CHK'D.

M113 REQ'd in E09
IF NOT PRESENT

RUSS 1/8/69
DATE

=-^/./,.

E
BH

corporation
uSDuSIi
CJ Hi
IB
MASSACHUSETTS
MAYNARD,

TITLE

GENERAL WIRING SHEET

DATE

PROJ. ENG.

M/ FOR

DATE

KV8I

l/H^htuM-,
FIRST USED ON

SHEET

A WL

SCALE

NUMBER

SIZE CODE

REV.

KV81i^0-5

D!ST.

5ec form no.

Sraio4

Figure 7-9. General Wiring Sheet for KV8I, KV8I-0-5 (Sheet 2)

7-19

SIGNAL NAME

FROM PIN

TO PIN

lOP

E09N2

J33F2

E09S1

J33H2

E09S2

J33F1

lOP

(1)
2

lOP 4

(1)
(1)

REMARKS

COLOR

.§>°-

O.E

OS
S J S
'^.EE

«>

io*
|o o
0 S- *>

eg £

111
I-

» E

REV.

DATE

CHG. NO,

K.
APP'D.

EQUIPMENT

DATE

DRN.

REVISIONS

RUSS

4/8/69

CHK'D.

DATE

K. RUSS

4/8/69

ENG.

DATE

PROJ. ENG.

DATE

CORPORATION

MAVNAMO. MASSACHUSETTS

TITLE

GENERAL WIRING SHEET
FOR

ROD.

DATE

KV8I
FIRST USED ON

SIZE CODE

A WL

SCALE

SHEET

NUMBER

KV8I^J^-5

DIST.

PEC FORM NO
npA 104

Figure 7-9. Genera! Wiring Sheet for KV8I, KV8I-0-5 (Sheet 3)

REV.

DIGITAL. EQUIPMENT CORPORATION
MAYNARD, MASSACHUSETTS
D
,-

""
,.

ENGINEERING SPECIFICATION
TITLE

DATE 5/15/69

°-5

KV8/I Display Acceptance Procedure

o »_

REVISIONS

Sou

DESCRIPTION

REV

e 2 i
JS

CHG NO

ORIG

DATE

00001

Q. "

APPD BY

DATE

^/^B.

8/8/69

£ E
C w V

« -Q f

s c .0 a

ego.

I?:
C w 3
'151
Q.-C o
)

u»

3 > £

/^,

ENG
DEC FORM NO.
DRA 107

APPD

±Mi

SIZE

CODE

NUMBER

REV
A

KV8X-0-6

SHEET

Figure 7-10. KV8I Display Acceptance Procedure,

KV8I-0-6 (Sheet 1)

7-21

ENGINEERING SPECIFICATION

CONTINUATION SHEET

TITLE

Scope:

to define the procedure to accept a KV8/I system for

shipment

Test Hardware:
1)

PDP8/I computer wired for KV8/I option and

with Teletype.
2)

KV8/I display option modules (M712, A612,
A312, A712)

VTOl Storage Display Unit (modified Tektronix
511) .

Test Software:

H306 Joystick Control.

Display system, dual cable.

KV8/I Display Diagnostic
DC6A-PB(L)

binary tape, Maindec-8/I-

writeup, 8/I-DC6B-D(D)

and listing.

Procedure:
1)

Perform Q C inspection.

Check KV8/I and VTOl alignment using diagnostic
(Sec.

5.3.1. thru 5.3.3), and touchup where re-

Patterns must meet the performance specs

quired.

given in performance specs for KV8/I controller
writeup.
3)

Run the main diagnostic (Sec. 5.3.5.1, S/A200)
for ten minutes

Run the cursor diagnostic (Sec. 5.3.5.2) for

approximately 20 interrupts.
SIZE

CODE

NUMBER

kvbx-o-g

DEC FORM NO
DRA 108

SHEET

Figure 7-10. KV8I Display Acceptance Procedure,

7-22

KV8I-0-6 (Sheet 2)

REV
A

ENGINEERING SPECIFICATION

CONTINUATION SHEET

TITLE
5)

Unit is accepted when steps

thru 4 can be

successfully completed and performance specs
for KV8/I controller writeup, is met.

halts greater than 500 is step

Error

can be corrected

by suitable realignment performed in step 1.
.

Shipping Hardware:
1)

PDP8/I computer wired for KV8/T with Triad F91X
transformer.

PDP8/I may or may not be already

installed.
2)

KV8/I display option (modules M712, A612,
A312, A712).

VTOl Storage Display Unit in special shipping

container
4)

H306 Joystick Control.

20 ft, display system dual cable.

Shipping Software:

Display System Software Package

KV8l

KV Maintenance Manual.

Tektronix 611 Manual.

Complete set of prints.

SIZE

CODE

DEC FORM NO
DRA 108

NUMBER

REV

KV8I-0-6

SHEET _i

Figure 7-10. KV8I Display Acceptance Procedure,

KV8I-0-6 (Sheet 3)

7-23

DIGITAL. EQUIPlVtENT CORPORATION
MAYNARD, MASSACHUSETTS
" Hi F

5i«|
° ^Z.

ENGINEERING SPECIFICATION

°"§i!

TITLE

DATE

5/15/59

Performance Specifications for KV8/I Controller and VTOl Display

O i_

REVISIONS
J!

REV

St;

DESCRIPTION

CHG NO

DATE

ORIG

APPD BY

DATE

o 2 c
i;

Q. TO

C cu 0)

tf)

= w

5 «>i=.2
Q.

O CO -—

c o Q. a„„ ° •-

g¥ ° 5
_£
° §^ =
CO

Q.-g

ENG

'%.e.^^

SIZE

CODE

DEC FORM NO.
DRA 107

NUMBER

REV

K\rT_o-7
SHEET

OF _LCL

Figure 7-11. Performance Specif ications for KV8I Controller

7-75

ENGINEERING SPECIFICATION

CONTINUATION SHEET

TITLE

(1),(2)

Line Drawing Capability
A.

Scope

Controller.

The KV8/I controller shall be capable of drawing
linear vectors, circular vectors, or point plotting,

A. 1,1.

Linear vectors shall be drawn using a stroke method.
Such vectors may either be addressed in absolute
mode, giving the x,y coordinates of the end point
of the vector, or in relative mode, giving ^ x, /^

coordinates of the end point of the vector relative
to the present location.
A. 1.2.

Maximum length of any stored vector should not
exceed 8" to guarantee storage.

A. 1.3.

Linear absolute vectors shall close within .02" for
vectors up to 6".

A. 1.3.1 There is no guaranteed closure

cor linear relative

vectors.
A. 1.4.

Linear vectors may be executed at two execution
rates, short vector 275 us + 10 us or long vector
(4.08 ms)

(1)

All performance specifications stated herein are only valid
after the KV controller has been aligned according to the
procedures outlined in the KV diagnostic write up ( Maindec-8 I-D6CA)
(2)

All performance specifications as given are only valid for the
temperature at which the system was initially aligred, except
where stated otherwise. See Section VI of this writeup.
SIZE

CODE

DEC FORM NO
DRA 108

NUMBER
SHEET

Figure 7-1 1. Performance Specifications for KV8I Controller

7-26

and VT01 Display, KVSI-a? {Sheet 2)

REV

KV8I-0-7
OF .JJL

ENGINEERING SPECIFICATION

CONTINUATION SHEET

SUglOilO

TITLE

A. 1.4.1. A long vector execution is required if the vector

A long vector execution of less

length exceeds 3/8".

than 3/8" will cause deterioration in line quality
(excess line width and lower resolution)
A. 1.4. 2. A short vector execution exceeding 3/8" length violates

the storage capability of the VTOl and the accuracy of

Short vectors of less than 3/8"

the KV controller.

will meet all accuracy specifications stated herein.
A. 2.1.

Circular arc vectors shall be drawn by a stroke method.
Such vectors are addressed by giving the x,y coordinates
of the center of a circular arc.

The present location

(which may be established by an

of the integrators

invisible absolute linear vector) defines the starting
location of the arc and hence
A. 2. 2.

Maximum radius of

point on the circumference

stored arc vector should not

exceed 3" to '"'uarantee storaoe.
A. 2. 3.1 Circular arc vectors up to 6 inches diameter shall

close within .02 inches radially and within .02 inches

circumferentially.
A. 2. 3. 2 Circular arc vectors shall center (rotate about)

the

selected screen location within an accuracy of .02 in.
(A zero radius circle

may just begin to show an open

center) .

DEC FORM NC
DRA 108

SIZE

CODE

NUMBER

REV

KV8 1-0-7

SHEET _J

Figure 7-11. Performance Specifications for KV8i Controller
and VTOl Display, KV8I-0-7 (Sheet 3)

7-27

ENGINEERING SPECIFICATION

CONTINUATION SHEET

TITLE

Circularity of circular vectors shall be + 5% (i.e.
semi-major and semi-minor axis not to differ by more
than + 5%)

,5.1

Circular arc vectors shall be 90
o

vector execution or 5.525

+ .07

+1 o for long
for short vector

execution.
A. 2. 5. 2 Circular arc vectors shall rotate at a radian rate

of .1

per 4.5 us adjustable + 10%.

A. 2. 5. 3 All circular vectors rotate clockwise from their

starting location about the selected center.
dot addressed as X,Y.

A. 3.1

Point plot mode shall store

A. 3. 2

Maximum point plot range is

+ 12"

about origin

(+511 to -512 decimal coordinates)
A. 3. 3.

Point plot shall position within .02" of an

address referenced by
B.

The KV controller shall provide
B.l

Reset will position

long linear absolute vector.

hardware reset function.

subsequent point plot or linear

vector to within .04" of the true origin (i.e.
absolute linear vector) when executed from

0,0

position

not to exceed 6" from the origin using long vector

execution.
B.2

Reset shall recover from

latch-up condition

(integrators or sample-holds saturated at power supply
potential) in less than

seconds, when issued as
SIZE

CODE

DEC FORM NO
DRA 108

SHEET

Figure 7-11. Performance Specifications for KV8I Controller

7-28

NUMBER
KV8I-0

and VT01 Display, KV8I-0-7 (Sheet 4)

REV

ENGINEERING SPECIFICATION

continuation sheet

afllBOID

TITLE

reset-continue.
C.

The KV controller shall provide

vector-continue function.

The vector continue permits disabling of the hardware

C.l

timer allowing auxilliary timing of the reset and circular arc vectors.

Reset continue shall be permitted in cursor display

C.2

mode.
II.

Line Drawing Capability - VT01 Display

A. 1.1 The VT01 shall provide a resolution of at least 300

stored line pairs in point plot mode (line width of
.01 inches) measured along the X or

Y axis.

A. 1.2 The VT01 shall provide a resolution of at least 150

stored line pairs in linear vector mode (.02 in line
width) measured along the X or Y axis,
A. 2

Maximum variation in line width shall not exceed 3:1
over the quality area of the scope (6" by

1/2")

for

long or short vectors executed under the definition of
Par .lA. 1.4.
A. 3

Line straightness deviation from the mean shall not

exceed + »5% of line length.
A. 4

Line continuity:

dropout shall not exceed .01" per

dropout for each dropout area

SIZE

CODE

DEC FORM NO
DRA 108

NUMBER

REV

KV8T-0-7
SHEET

Figure 7-11. Performance Specifications for KV8I Controller

and VT01 Display, KV8I-0-7 (Sheet 5)

7-29

ENGINEERING SPECIFICATION

continuation sheet

EHIgliaSO

TITLE

Line smoothness: noise and wiggle amplitude not to

A. 5

exceed +
B.

.015'

VT01 Cursor

Cursor intensity shall be at least

B.l

ft.

lamberts

without causing storage of the cursor within the

quality area.
C.

Warmup and Stabilization
The VT01 shall require a maxim\am of 30 minutes warmup

C.l

to provide stable cursor write-thru and vector storage

properties
D.

All other VTjZfl specs are given in the Tektronix 611 manual
except where such specs conflict with those given here.
Scope Control Functions

III.
A.

The KV controller shall provide means for programmed

erasure of the VT01 display with hardware lockout of the

ready flag performed by the VT01.
B.

The KV controller shall provide means to activate and

display the VT01 write- thru cursor.

Such cursor will

appear as an ellipse of approximately .1" major axis and
will respond to the application of + .5 volt analog signals
to the external cursor input terminals of the controller,

producing full screen deflection of the cursor.
C.

The controller shall provide for programmed control of the
Z axis

(intensify)

function of the VT01
SIZE

CODE

NUMBER

DEC FORM NO
DRA 108

SHEET _6

Figure 7-11. Performance Specifications for KV8I Controller

7-30

and VT01 Display, KV8I-0-7 (Sheet 6)

REV

KV8I-0-7
OF

ENGINEERING SPECIFICATION

continuation sheet

SDgflDiO

TITLE

Timing Functions

IV.

A. The KV control shall provide two hardware timing functions -

long
B.

(~4 ms)

and short

(

— .25 ms)

The-KV control provides a delay of 100 us + 30 us to allow input
data to settle.
C.

Drift Rates.
C.l

The input (sample-hold) registers shall not drift

greater than + 30 coordinates (.36" for pt plot)
per second.

(This means the maximum permitted

time between the load data and execute commands

should not exceed 15 ms)
C.2

The output (integrator) registers shall not drift

greater than +
per second.

coordinates (,072" in vector m.ode)

(This means absolute vectors should

be executed at least 10 vectors per second, and

relative vectors should be executed at the full
speed rates of Par. D. below)
D.

Vector Execution Rates
D.l

Linear vectors may be executed up to 1750 short vectors/
sec. or 225 long vectors/sec.

D.2

Points may be executed up to 3000 pts./sec.

D.3

Circles require 16.2 ms per circle, or an

angular rate of

degree per 4.5 us.

This

time if invariant (i.e. all circles are executed
SIZE

CODE

DEC FORM NO
DRA 108

NUMBER
KV8I-0-7
SHEET

REV

Figure 7-11. Performance Specifications for KV8I Controller

and VT01 Display, KV8I-0-7 (Sheet 7)

7-3

ENGINEERING SPECIFICATION

mmH

continuation sheet

TITLE

at the same angular rate)
V.

d/A and A/P Facilities
A.

The controller shall contain

converter producing

a 10

bit digital to analog

to -4 volts + 5% for a 0777 to 1000

two's complement input range {0000 produces -2 volts
nominally)

The reference for this D/A shall be internally

supplied and shall be 2.45 volts +
B.

volts.

The KV controller shall provide an analog comparator
and suitable switching paths to measure any of six analog
sources (X or Y sample-hold, X or Y integrators, and

X or Y external (cursor) input) .

This comparator shall

provide an accuracy of at least 1%

(+ 4

digital counts)

of the true input, when used with a successive approx-

imation A to D conversion subroutine program.
B.l

The external (cursor) inputs shall accept +

volt

+ 10% input signals to provide the full +511 to -512

coordinate range.
B.2

The comparator shall require at least 50 us per
successive approximation step (or approximately
1

ms to make a complete 10 bit reading)

to permit

the comparator to settle to the accuracy stated

above

SIZE

CODE

NUMBER

DEC FORM NO
DRA 108

SHEET
Figure 7-1 1. Performance Specifications for KV81 Controller

7-32

and VT01 Display, KV8I-0-7 (Sheet 8)

REV

KV8I-0-7
8

OF _!£.

ENGINEERING SPECIFICATION

CONTINUATION SHEET

TITLE

VI. Environmental
o

Maximum permitted operating temperature range 10"c to 40 C.

Maximum temperature deviation before readjustment of system

may be required +

o
3

o
C (+ 5 F)

about temperature when

initially calibrated.
C.

Maximum humidity not to exceed 70% to meet above specs.

Ccntroller cannot tolerate shock or vibration since the
alignment is likely to change.

VI I .
A.

Po'A'er

Supply

A 712 power supply requires an input of 28 volts CT AC +2.8
Volts @ 47 to 63 H„.

This is normally supplied by a

TRIAD F91}C/trans former mounted to receive power off the
fan power bus of the computer.
B.

The A712 supplies +11. 5V +1V @ 100 ma and -11.5 +1V @ 100 ma

with ripple not to exceed 50 mv.
C.

It is preferred to use KV8/I graphic system on AC power

lines free of inductive loads.
D.

Total dissipation of the KV controller is less than

The KV controller requires + 5V (a 395 ma and - 15V

(a)

watts.
37 ma

supplies in addition to the AC supply above.
VIII.
A.

Physical
The basic controller consists of 4 Flip Chip Modules:

A712

Power Supply:

Standard size Flip Chip module

SIZE

CODE

DEC FORM NO
DRA 108

NUMBER

REV

KV8I-0-7
SHEET _9

OF _10_

Figure 7-11. Performance Specifications for KV8I Controller

and VT01 Display, KV8I-0-7 (Sheet 9)

7-33

ENGINEERING SPECIFICATION

CONTINUATION SHEET

TITLE

M712

Timing Generator

Double height standard size

Flip Chip module.
M612

D/A Converter - Double height standard size
Flip Chip module.

A312 - Analog Function Generator

Double height

standard size Flip Chip module.
In the PDP 8/1, these modules occupy the following

locations
H21

A712

HJ23

M712

HJ24

A612

HJ25

A312

The KV8/I requires a special cable connector type

G778 which occupies slot J21.
The KV controller in addition requires a TRIAD F91X, trans,

mounted next to the fan housing.

SIZE

CODE

DEC FORM NO
DRA 108

NUMBER
SHEET

Figure 7-11. Performance Specifications for KV8I Controller

7-34

and VT01 Display, KV8I-0-7 {Sheet 101

REV

KV8I-0-7
10

0-j2!-90£Httfn|a!2

NOTES
I.

.FOR DRKWit^G. \HDEX USsT RtTE^ TO

rv/n^

arrr^rar

r.u,:7

-ri>,^F^--t^

SEt DtiAiL A

RUBBER

MAT

FIRST USED OM OPTION MODEL

UNLESS OTHERWISE SPECIFIED
UNLESS OTHERWISE SPECIFIED
DIMENSION IN INCHES

EQUIPMENT

DATE

DRN.

CORPORATION
:hk'd.

-/"/^f

TOLERANCES
DECIMALS

FRACTJONS

- .005

s 1/6*

ANGUS
± O-M'

FINAL SURFACE QUALITY

"^U/g^aZt-l/^j/A?
BatT

PaOJ. ENG.

REMOVE BURRS AND BREAK SHMP
CORNERS

MATERIAL

Mfe'^JW'
SCALE

]

JOYSTICK CONTPOL
ASS'Y
d|uAH306-0-0
DisT.
I

G\tiH\i^'i\ni\i>,\

Figure 7-12. Joystick Control Assembly, H306-0-0

7-35

Digital Equipment Corporation

l\4aynard,

printed

U.S.A.

Massachusetts