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DEC-8I-H2CA-D

December 1969

9 pages

Original

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Document:	PP8I High-Speed Paper Tape Punch Option
Order Number:	DEC-8I-H2CA-D
Revision:
Pages:	9
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/dec-8i-h2c/dec-8i-h2ca-d.pdf

OCR Text

DEC-8I-H2CA-D

PP8/I

HIGH-SPEED PAPER-TAPE PUNCH
OPTION
FUNCTIONAL DESCRIPTION

DIGITAL

EQUIPMENT CaRPORATION n MAYNARD

MASSACHUSETTS

1st Printing April

The following are registered trademarks of Digital
Equipment Corporation, Maynard, AAossachusetts:

DEC

PDP

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

1969

PP8/I
HIGH-SPEED
PAPER-TAPE PUNCH

INTRODUCTION

LOGIC DESCRIPTION

The PP8/I Paper-Tape Punch (Figure 1) con-

The PP8/I Paper-Tape Punch punches the
data received from the PDP-8/I accumulator into the paper tape. The 12-bit instructions from the PDP-8/1 are decoded to generate control pulses that operate the punch
mechanism. The decoding Is performed as

50-character-per-second, Royal
McBee Model 500 electro-mechanical punch,

sists of a

and its associated control logic elements.
Eight-bit parallel data Is accepted from the
PDP-8/I, stored in a buffer register, and
punched in one-inch-wide paper tape.

The control logic of the PP8/1 is contained
on one, double-height, integrated-circuit,
module located in the central processor mainframe.

Figure 2 shows the functional rela-

tionship between the PDP-8/I, the PPB/l
control logic,

and the paper-tape punch.

The following paragraphs describe the operation of the control logic portion of the tape

punch as it relates to the PDP-8/1 and the
punch mechanism. Maintenance procedures
and a description of the punch mechanism
and its operation are provided in the Royal
McBee Model 500 Maintenance Manual

Figure 1

follows:

When an lOT (Input/Output Transfer) is initiated, the PDP-8/1 memory-buffer bits

through 2 contain operation code 6g and
memory-buffer bits 3 through 8 contain a
6-bit device code; for the PP8/I, this device code Is 02g.

Memory-buffer bits 9, 10,

1 1

of the instruc-

lOP pulses. These
pulses (lOPl, IOP2, IOP4), when gated by

tion generate PDP-8/1

device code 02g, are sent to the punch control logic to generate pulses that control

the PP8/1 functions.

PP8/1 High-Speed Paper-Tape Punch

PDP -8/1

*
BUS

BUS
SKIP

INT

1'
I/O

MB03-08

1
I/O

DATA

L_^

AC04-11

PP8/I

PP8/I
TAPE

CONTROL
lOP PULSES
INITIALIZE

PUNCH

FEED SWITCH

L
r

Figure 2

FEED CONTROL

LOGIC

J
J
n

Block Diagram PP8/t Paper-Tape Punch

When the PDP-8/I is turned on or the STA RT

complished either by executing a 6024 in-

key is pressed, the PDP-8/I INITIALIZE
level is generated and applied to the control logic (Drawing D-BS-PPB/l-O-l). INITIALIZE clears the punch buffer flip-flops
PBO through PB7, the PUN ACTIVE flip-flop,
and the PUN FLAG flip-flop by applying a
direct clear input level to each flip-flop.

struction or by pressing the manual

Punch, a single, continuouslyrotating shaft drives both the punch and tape-

flip-flops that are set, enable the solenoid

In the PP8/1

feed mechanical operations.

Primary power,

applied to the punch mechanism, activates
a drive motor that operates continuously as
long as power is applied.

FEED

switch (FEED switch with Royal -McBee only)

on the punch panel. In either case, the
feed -hole and data are punched and the tape
is advanced one position regardless of the
data stored in the punch buffer register. The
data is punched according to the status of
the punch register. The PBO through PB7
drivers which then activate the respective

hole punches.

Program Instructions

A reluctance

pickup senses the rotation of the shaft and

Table 1 describes the program instructions

sends SYNC PUN pulses to the control logic.

that control the operation of the PP8/I Tape

These pulses synchronize the timing between

Punch.

the computer and the rotating shaft.

First,

the shaft causes the punches to be driven

through the paper tape; then it causes the

tape to be fed to the next position for punching the next character.

The punch cycle is initiated by activating
the feed-hole solenoid driver. This is ac-

The PP8/I instructions and logic implementation are described below.

PCF(6022)
This instruction, used at the start of the pro-

gram, clears the PUN FLAG flip-flop, the

Table

PP8/1 Instructions

Mnemonic

Octal Code

PSF

6021

Operation

Skip if Punch Flag is a 1 .

Punch

Flag= 1, then PC+1 = > PC
PCF

6022

Clear Punch Flag and Punch Buffer.
= > Punch Flag, PB

PPC

6024

Load the Punch Buffer from bits 4 - 11
of the AC and punch the character.
(This instruction does not clear the
punch flag or punch buffer.) AC 4-11

V PB = > PB
PLS

6026

Clear the Punch Flag, clear the Punch
Buffer, load the Punch Buffer from the

content of bits 4-11 of the AC, punch
the character, and set the Punch Flag

= > Punch Flag,
PB AC 4-11 = >PB 1 > Punch Flag

when done.

when done

PUN ACTIVE flip-flop, and the Punch Buffer
flip-flops (PB) PBO through PB7.

PCF is gen-

through ACll) into the PB register through
the flip-flop data inputs.

The pulse also

PUN ACTIVE flip-flop to precondi-

erated by combining the device codes with
IOP2(l). The resulting pulse is applied to

sets the

the Direct Clear flip-flop inputs. Normally,
this Instruction is combined with PPC for the

The PUN ACTIVE(l) output (+3V),

remainder of the program.

allows the PUN

tion the unit for punching data into the tape.
to the data input of the

PUN FLAG

applied

This

FLAG to set when the PUN

DONE signal pulses the clock input.

The

PUN ACTIVE (0) output (OV) is ORed with
the PUN Feed switch. When either signal

PPC (6024)

at OV, the ORed output combines with

The PPC instruction, performed after the
PCF instruction in the program, consists of
the device selection code and IOP4(l) pulse.

the SYNC PUN pulse to trigger a delay.

This control pulse is applied to the clock in-

the delay is adjusted to 10 ms.

put of the PB flip-flops, permitting the trans-

BRPE II Punch (Teletype Corporation), the
delay adjustment is 4.5 ms.) The delay al-

fer of PDP-8/I accumulator data

(AC04

(The delay depends on the model of the

punch used.

With the Royal -McBee Punch,
For the

lows completion of the punch operation be-

entered to issue a new punch instruction.

fore the PDP-S/l attempts another PCF in-

Normally, the PLS (6026) instruction is used
next to continue punching.

struction.

When the delay input is triggered, the output changes from +3V to OV for the duration

PLS (6026)

of the time delay.

This instruction decodes to IOP2(l) and

This output is inverted
activating the FEED-HOLE solenoid driver

NAND gate.
1

The solenoid drivers for holes

through 8 activate when the controlling

IOP4(1) in the same computer cycle.

The

clears the PB, PUN FLAG, and
PUN ACTIVE flip-flops, and the second

first pulse

the

gates are enabled by both the leading edge

initiates the

of the inverted delay output, and active PB

viously.

(+3V on the 1 side). The solenoid
drivers then release the punch mechanisms
and the tape is punched.

In PP8/I options that contain revision

punch cycle as described pre-

flip-flops

the

the contents of the PUN

When the delay has elapsed, PUN DONE is
generated.
sets the

This transition from low to high

PUN FLAG flip-flop and clears the

PUN ACTIVE flip-flop by pulsing their clock
inputs.

PSF (6021)

D of

M710 Punch Control module however,

FLAG flip-flop are

preserved during a feed operation.

(This

important when feed operations are accomplished during a program loop that is searching
for the punch flag.)

In activating the punch,

FEED switch signal clears only the PB
flip-flop, leaving PUN ACTIVE and PUN
FLAG unaltered. This change was accompthe

lished by clocking the PUN FLAG unaltered.

This change was accomplished by clocking

When the PU N FLAG is set, th e (1) output
activates the I/O

BUS IN INTerrupt line
(OV), and enables the I/O BUS IN SKIP
Gate. I/O BUS IN INT indicates to the

PDP-8/t that some device is requesting service. The PDP-B/t then enters a programmed search subroutine to determine the device that caused the interrupt. This search
is performed by a series of "flag checking"
skip instructions. A skip instruction is executed for each device attached to the interrupt line. The PPB/I PUN FLAG status
When
is checked by the PSF instruction.
is
ins
truction
the PUN FLA G is set and this
executed, the I/O BUS IN SKIP gate is activated causing the PDP-S/I program counter
to increment by one, thereby skipping the
next sequential instruction in the program.
The PDP-8/1 then recognizes that the high-

speed punch has finished punching a character and a programmed service routine is

PUN FLAG flip-flop with the PUN ACTIVE (0) signal rather than with the PUN

the

DONE signal. Thus, when a programmed
operation occurs, the clocking of PUN ACTIVE to a logic zero by PUN DONE sets the

PUN FLAG flip-flop; during a feed operation,
however, PUN ACTIVE is not altered.
Another logic change in revision D eliminates
the clearing of the PB flip-flop upon INITI-

ALIZE and IOB3(1).

This does not alter the
external operation however, because the
transfer of information through the PB flip-

flop is a jam transfer.

Maintenance
The maintenance procedures pertaining to
the PDP-8/1 also apply to the PP8/I control
logic. The recommended maintenance pro-

cedures for fhe Royal -Mc Bee or Teletype

ENGINEERING DRAWINGS

Corporation punches are found in their respective manuals.

The following engineering drawing D-BSPP8I-0-1, and the circuit schematic C-CS-

M71 0-0-1 pertaining to the PP8/1 option
are contained in this section.

11
*C33

LOCATED ^
PUNCH

—'^

W077A

(

',,ijz

,^Z

iFZ

..C2

NOTEtl)

DELAY lOMSEC FOR ROTAL PUNCH
4.5M5EC FOR BPRE PUNCH

SIGNAL NAMES INDICATE
ASSERTED STATES FOR
HIGh(h) LEVELS PER DEC
STD 054

IOP2(ll
I

Sl«>^>-

M7hO
SWITCH

HJ28

al>

lOP KO-

D-BS-PP8I-0-1

High-Speed Punch

PBOdI

PBKII

AKI

ALI

rKF?^^*^"K^

UNLESS OTHERWISE INDICATED:
RESISTORS ARE I/4W, 9%
TRANSISTORS ARE DEC6S34B
CAPACITORS ARE .01 MFD
PIN 7 ON EACH IC = SND
PIN 14 ON EACH IC^-f-SV
EI,E2,E3, E4,EI0 ARE 0ECT474N
E9,E8 ARE DEC7400N
Ee IS DEC74I0N
E7 IS DEC7490N
E9 IS 0EC7440N
EII,EI2 ARE DECTAtON
DWOES ARE DU4

C-CS-M710-0-1

Punch Control M710