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DEC-8E-HR3B-D

December 1973

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OCR Text

MMHM
EJUgJUQaU

Equipment Corporation
Maynard, Massachusetts
Digital

DEC-8E-HR3B-D-VT8-E

VT8-E
HIGH SPEED VIDEO DISPLAY TERMINAL
AND CONTROL OPTION

The information in this preliminary manual will become, in its final
form, a part of the PDP-8/E/F/M Maintenance Manual, Volume 3.

PRELIMINARY

1st Edition, May 1973

The material in this manual is for informational
purposes and is subject to change without notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

CONTENTS
Page

CHAPTER 12

VT8-E HIGH SPEED VIDEO DISPLAY TERMINAL AND CONTROLS
Section 1 — Introduction

12.1
12.1.1

12.1.2

SYSTEM OPERATING SPECIFICATIONS
CRT Operating Specifications (Motorola Raster Display)

12-2
12-2

12-3

Visible Display Specifications

12.1.2.1

Alphanumeric Mode

12-3

12.1.2.2

Graphic Mode

12-3

Section 2 — Installation and Acceptance Test

12.2

UNPACKING

12-4

Primary Power

12-4

12.2.2

VT8-E Installation

12-5

12.2.3

Acceptance Test

12-8

12.2.1

Section 3 — Operation and Programming

12.3
12.3.1

FUNCTIONAL DESCRIPTION

12-8

VT8-E Printer/Keyboard Control Module (M8335)

12.3.1.1

MD Bus Gating

12-8

12.3.1.2

IOT Decoders

12-9

12.3.1.3

Data Bus Gating

12-9

12.3.1.4

Keyboard Buffer

12-10

12.3.1.5

I/O Transfer Control

12-10

12.3.1.6

Interrupt and Skip Logic

12-10

12.3.1.7

Interrupt Logic

12.3.1.8

Starting Address Register and Counter (SAR)

12-10
.

12-10
12-10

12.3.1.9

Extended Starting Address Register

12.3.1.10

Printer Buffer

12-10

12.3.1.11

PRINT DONE Flag

12-10

Higher Priority Detection

12-10

VT8-E Line Buffer Module (M8337)

12-11

12.3.1.12
12.3.2
12.3.2.1

Line Buffers A and B

12-11

12.3.2.2

ASCII Decoding ROMs

12-11

12.3.2.3

Graphic Video Buffer

12-11

12.3.2.4

Character Display Mode Detection Logic

12-11

12.3.2.5

Visible Field Detection Logic

12-11

12.3.2.6

Single Cycle Data Break Control Logic

12-12

12.3.2.7

Processor Control Signals

12-12

12.3.2.8

Break Counters

12-12

12.3.2.9

MA and EMA Bus Gates

12-12

12.3.2.10

Data Bus Gates

12-12

12.3.2.11

Maintenance Enable

12-12

12.3.2.12

Frequency Divider Board (M8336)

12-12

12.3.2.13

Display IOT Decoder

12-12

CONTENTS (Cont)
Page

12.3.3
12.3.3.1

12.3.3.2

12.3.4

VT8-E Clock and Frequency Divider (M8336)
Real Time Clock Flag
Video and Sync Combining Circuits

12-12

OT Instructions

12-13

12-12

12-13

12.3.4.1

Display Instructions

12-13

12.3.4.2

Keyboard Instructions

12-14

12.3.4.3

Printer Instructions

12-16

12.3.5

Display Data Format

12.3.5.1

Alphanumeric Data Format

12.3.5.2

Graphic Data Format

12.3.6
12.3.6.1

12.3.6.2

12.3.7

Display Monitor and Keyboard Switches and Controls
Display Monitor Switches and Controls

Keyboard Controls
Programming Examples

12-17
12-17
12-18

12-18
12-18
12-18
12-22

12.3.7.1

Graphic Display Program Example

12-22

12.3.7.2

Alphanumeric Display Program Example

12-22

Section 4 — Detailed Logic Description

12.4
12.4.1

INTRODUCTION
Keyboard/Printer Logic

12-23
12-24

12.4.1.1

IOT Decoder Logic

12-25

12.4.1.2

Printer Receive Logic

12-25

12.4.1.3

Keyboard Transmit Logic

12-29

12.4.1.4

INT/SKIP Logic

12-30

12.4.2

Display Logic

12-31

12-34

12.4.2.2

VT8-E Timing
VT8-E Timing Logic

12.4.2.3

Starting Address Register Logic

12-39

12.4.2.4

Data Break Counting Logic

12-40

12.4.2.5

Data Break Control Logic

12-44

12.4.2.6

Data Break Halt, Line Feed, and End-of-Screen Logic

12-47

12.4.2.7

Priority Logic

12-47

12.4.2.8

Line Buffer Register and Control Signal Logic

12-47

12.4.2.9

ROM Character Generator Logic

12-53

12.4.2.10

Alphanumeric Video Buffer Control Logic

12-56

12.4.2.12

Visible Field Logic

12-59

12.4.2.13

Display Mode Logic

12-61

12.4.2.14

Maintenance IOT Logic

12-63

12.4.2.15

Display Interrupt and Skip Logic

12-63

12.4.2.16

Bell

12.4.2.1

12.5

Logic

DISPLAY MONITOR CIRCUITS

12-35

12-64
12-64

12.5.1

Keyboard Logic

12-64

12.5.2

Motorola CRT Display

12-66

12.5.2.1

Video Amplifier

12-66

12.5.2.2

Sync Separator

12-66

12.5.2.3

Phase Detector

12-66

CONTENTS (Cont)
Page

12.5.2.4

Horizontal Oscillator

12-67

12.5.2.5

Pulse Shaper and Horizontal Drive

12-67

12.5.2.6

Horizontal Output

12-67

12.5.2.7

Vertical Oscillator Driver and Output

12-67

12.5.2.8

Retrace Blanking

12-68

12.5.2.9

PowerSupply

12-68

Section 5 — Maintenance

12.6

INTRODUCTION

12-68
12-69

12.6.2

Equipment Required
Diagnostic Programming

12.6.3

Preventive Maintenance

12-69

Mechanical Checks

12-70

12.6.1

12.6.3.1

12.6.4
12.6.4.1

12.6.4.2

12.6.4.3
12.6.4.3.1

12-69

12-70

Troubleshooting

System Troubleshooting
Module Troubleshooting

12-70

VT8-E Assembly/Disassembly
VT8-E Module Boards

12-70

12-70
12-70

12.6.4.3.2

Cover Removal

12-70

12.6.4.3.3

VT8-E Keyboards Removal

12-71

12.6.4.3.4

CRT Removal

12-71

APPENDIX A

ROM PATTERN TABLES
ILLUSTRATIONS

Figure No.

Title

Page

12-1

12-3

VT8-E Display Monitor
VT8-E Module Installation
VT8-E Block Diagram

12-4

Extended Address and Sense Switch Data

12-14

12-5

Keyboard Data Format

12-15

12-6

Printer Data Format

12-16

12-7

Alphanumeric Display Data Format

12-17

12-8

VT8-E Functional Block Diagram

12-24

12-9

Printer/Keyboard Block Diagram

12-24

12-10

IOT Decoder Logic

12-26

12-11

Printer Receive Logic

12-27

12-12

Printer Receive Logic Timing

12-28

12-13

Keyboard Transmit Logic

12-29

12-14

Keyboard Transmit Logic Timing

12-30

12-15

Keyboard/Print Interrupt and Skip Logic

12-31

12-16

Display Logic Block Diagram

12-32

12-17

Video Presentation for the Letter F

12-33

12-18

Two Alphanumeric Characters Displayed on the CRT

12-34

12-1

12-2

12-8
12-9

ILLUSTRATIONS (Cont)
Page
12-19

Sweep and Sync Signals

12-35

12-20

Clock Pulse Generator

12-36

12-21

4-Bit Counter

12-36

12-22

VT8-E Timing Chain

12-37

12-23

Horizontal and Vertical Sync Circuits

12-38

12-24

Horizontal and Vertical Zone Flip-Flops

12-25

Alphanumeric and Graphic Line Timing

12-26

Starting Address Register Logic

12-41

12-27

Starting Address Register Control Logic

12-42

12-28

Data Break Control Logic

12-43

12-29

Data Break Counting for 32 Characters/Line

12-44
12-44

12-39
.

12-40

12-30

PRESET BRK Generation Graphic Mode

12-31

Data Break Control Logic

12-45

12-32

Data Break Halt, Line Feed/EOS Logic

12-46

12-33

Priority Logic

12-48

12-34

Line Buffer Register Logic

12-49

12-35

Line Buffer Register Control Logic

12-50

12-36

Line Buffer Register

12-51

12-37

Line Buffer Timing for 32 Character Line

12-52

12-38

Line Buffer Timing for 64 Character Line

12-52

12-39

Line Buffer Timing

12-53

12-40

12-54

12-41

ROM Character Generation Logic
ROM Functional Logic Diagram

12-42

Alphanumeric Video Buffer

12-57

12-43

Character Timing for a 32 Character Line

12-58

12-44

Character Timing for a 64 Character Line

12-59

12-45

Graphic Video Buffer Control Logic

12-60

12-46

Graphic Word Timing

12-61

12-47

12-Bit Data Word Format

12-61

12-48

Display Control Logic

12-62

12-49
12-50

BBF and EBF Timing
Display Mode Logic

12-63

12-51

Maintenance IOT Logic

12-64

12-52

Display Interrupt and Skip Logic

12-65

12-55

12-62

12-53

Bell

12-54

CRT Horizontal Oscillator Waveforms
CRT Vertical Oscillator Waveforms

12-55

Logic

12-65
12-67

12-68

TABLES
Table No.

Title

Page

12-1

AC Power Cable

12-2

Device Code Select Jumper Installation

12-6

12-3

Priority Jumper Installation

12-7

12-4

Switches and Controls

12-18

12-5

VT8-E Transmit Codes- Full ASCII Operation
VT8-E Transmit Codes -Half ASCII Operation

12-19

12-6

12-4

12-20

TABLES (Cont)
Page

12-7

VT8-E Receiving Codes

12-21

12-8

Character H, EVEN ROM Data Bits

12-55

12-9

Character H, XTRA ROM Data Bits

12-56

12-10

Equipment Required

12-69

A-1

ROM Pattern Table (EVEN ROM)
ROM Pattern Table (ODD ROM)
ROM Pattern Table (XTRA ROM)

A-2

A-3

A-1

A-5
A-9

CHAPTER 12
VT8-E HIGH SPEED VIDEO DISPLAY

TERMINAL AND CONTROL

SECTION

INTRODUCTION

The VT8-E, a video display option for the PDP-8/E, PDP-8/F, and PDP-8/M, consists of a display monitor and three
quad modules that plug into the OMNIBUS. The quad modules control the display monitor operation and can
interface the VT8-E to either an LA30A-P DECwriter or an LS01-E Centronics Line Printer. Up to four VT8-E
display options can be used simultaneously with the same computer.

The display monitor comprises a CRT with its associated power supply, deflection circuits and video circuits, and a
Teletype keyboard with its control logic. The monitor is contained in a desk-top enclosure (Figure 12-1).
Data

transferred

from the monitor keyboard to the computer AC Register by program interrupts. Data to be

displayed by the monitor is transferred from memory by Single Cycle Data Breaks to the VT8-E OMNIBUS control

modules. The control modules convert the parallel data to serial video information that is displayed on the viewing
screen.

The monitor can display both alphanumeric characters and graphic symbols, either alone or in combination.

Figure 12-1

VT8-E Display Monitor

® Teletype is a registered trademark of Teletype Corporation.
12-1

LA30A-P nor the LS01-E line printers is discussed here. Details concerning these two printers should be
VT8-E are:
obtained from the respective maintenance manuals. Publications and documents relevant to the
Neither the

12.1

PDP-8/E and PDP-8/M Small Computer Handbook - DEC, 1 972

PDP-8/E, PDP-8/F, and PDP-8/M Maintenance Manual, Volume 1

VT8-E Diagnostic; MAINDEC-08-DHVTB-A (Graphic), MAINDEC-08-DHVTA-A (Alphanumeric)

DEC Engineering Drawings, E-CS-M8335-0-1, E-CS-M8336-0-1, and E-CS-M8337-0-1 (interface modules)

DEC Engineering Drawing, D-CS-540991 7-0-1 (DEC Keyboard #2)

DEC Engineering Drawings, D-CS-301 0326-1-0 (Motorola Raster Display)

SYSTEM OPERATING SPECIFICATIONS
U

to 43" C

Operating Temperature Range

Operating Humidity Range

10% to 90% (Relative)

(without condensation)

Power Requirements

100-130 Vac, 50 or 60 Hz

(display monitor)

±5% single phase at 2A
200-260 Vac, 50 or 60 Hz
±5% single phase at 1

55W at 1 1 5V
65W at 230V

Power Consumption
(display monitor)

12.1.1

CRT Operating Specifications (Motorola Raster Display)
Screen Size

10-1/8 in. X 7-5/8 in.

Phosphor

P4 (white)

Deflection Type

Magnetic

Deflection Method

Raster Scan

Input Impedance

75S2 ± 5%

(at

VIDEO IN input)

Video Input Signal

0.9 to 2.2V with separate horizontal and vertical SYNC.

Video Pulse Rise and Fall Time

40 ns (10% to 90% point), measured at cathode with 1.0V
p-p input and 30V p-p output.

Video Output Amplitude

30V p-p (minimum), measured at cathode with 1.0V p-p input.

Resolution

Screen Center — 600 lines (minimum)
Screen Corners - 400 lines (minimum) (using shrinking raster

method)

12-2

Horizontal Sweep Frequency

15.6 kHz

Vertical Sweep Frequency

50 or 60 Hz (selectable)

Horizontal Retrace

11 /us (maximum)

Vertical Retrace

21 horizontal lines @ 15.6 kHz

High Voltage

kV (minimum) @ 50 juA beam current @ 24 Vdc power

supply adjustment

High Voltage Regulation

12 MJ2 (maximum), for a beam current change from 50 to

150 nA @ 24 Vdc power supply adjustment.

CRT Refresh Rate
1 2.1 .2

50 or 60 Hz

Visible Display Specifications

Screen Refresh Rate

60 or 50 frames/sec (determined
by local line frequency)

Refresh Method

12.1.2.1

Raster Scan

Alphanumeric Mode
Viewing Area

8-1/4 in. (horiz) X 6-1/4 in. (vert)

(32 characters/line)
8-1/4 in. X 4-1/4 in. (64 characters/line)

Character Lines

Character Size

20
0.185 in. width
(32 characters/line)

0.220 in. height
0.090 in. width
0.150 in. height

(64 characters/line)

Character Spacing

Horizontal

0.0740 in. (32 characters/line)
0.0370 in. (64 characters/line)

Vertical

0.0946 in. (32 characters/line)
0.0645 in. (64 characters/line)

Character Set

64-character ASCII set

(upper case)

Character Generation Method

12.1.2.2

5X7 dot matrix

Graphic Mode

Viewing Area

7 in. X 6-1/4 in. (if wired for 32

alphanumeric characters per line)

12-3

7 in. X 4-1/2 in. (if wired for 64

alphanumeric characters per line)

Display Lines

200

Flicker-Free Points per Line

189

SECTION 2 INSTALLATION AND ACCEPTANCE TEST
The VT8-E Video Display and Control are installed on site by DEC Field Service personnel. The customer should
not attempt to unpack, inspect, install, checkout, or service the equipment.
12.2

UNPACKING

The VT8-E Display Monitor is packed in a specially designed carton to avoid damage during shipment.

NOTE
Carefully examine the VT8-E for

damage as it is unpacked.

Any damage should be reported immediately.
Unpack the VT8-E Display Monitor as follows:
Procedure

Step

12.2.1

Remove the Display Monitor from the shipping container.

Remove the polyethylene cover.

Remove any tape, etc., from the display monitor cabinet.

Remove the display monitor from the shipping skid.

Place the display monitor in the desired location.

Verify all items listed on the Inventory List shipped with the VT8-E have been received.

Primary Power

The Display Monitor uses a single ac power cable (permanently connected) to connect the site power source to the
display monitor. The monitor operates at 110-130 Vac, 50-60 Hz, single phase, or 200-260 Vac, 50-60 Hz, single
phase.

Each wire in the ac power cable is color-coded as shown in Table 12-1. The display monitor is normally supplied
with a 15A connector. The selected ac service outlet must be capable of at least 2A, 1 10 Vac, 50 or 60 Hz, or 1 A,

200 Vac, 50 or 60 Hz.
Table 12-1

AC Power Cable
Line

Wire Color

Terminal Strip

Nomenclature

Frame Ground

Green

Frame Ground

Neutral/Line 2

White

Neutral or Line 2

Line 1

Black

Line 1

12-4

12.2.2

VT8-E Installation

Install

the VT8-E as follows:

Step

Procedure
Ensure PDP-8/E power is off.
Ensure the Display Monitor Power Select switch, located on the side of the Display
Monitor, is set correctly for the power source (115 Vac or 230 Vac).

Use

meter to measure the voltages on the wall receptacle and ensure that the hot,
and ground connections are the same as those on the Display Monitor power

neutral,

connector (Table 12-1).

On the M8336 and M8337, ensure the 5 jumpers are installed to select only 64 or 32
characters per line. All jumpers must be installed for the same mode.

On the M8335 module ensure the correct device code jumpers are installed. Table 12-2
contains a

list

of the split lugs which should be connected in each of the 6 groups (A— F)

to select one of the 64 possible device codes. Split lug locations (by groups) are shown on

D-CS-M8335-0-1-Engineering Drawing cover sheet.

On the M8337 and M8335 modules, ensure the jumpers are installed correctly to select
the priority assigned to this VT8-E (Table 12-3). Only priorities 9 (highest), 10, and 11
(lowest)

may be assigned to the VT8-E. Refer to M8337-0-1 and M8335-0-1 cover sheet

for jumper locations.

Connect J1 of the 7009042 Cable Assembly to J1 on the M8336 module.

Connect J2 of the 7009042 Cable Assembly to J1 on the M8335 module.

a line printer is used,

connect the printer cable assembly to J2 on the M8335 module.

the VT8-E modules on the OMNIBUS as shown in Figure 12-2. Refer to Figure 2-3
Volume 1 for recommended module installation priorities. The VT8-E is not a memory
option. The VT8-E modules must be installed in this order;
Install

M8336
M8337
M8335
11

Install

Front
Middle
Rear

H851 Top Connectors as follows (Figure 12-2):

Between M8336H and M8337H

Between M8337E and M8335E

Between M8337F and M8335F

Route the 7009042 Cable Assembly to the Display Monitor and connect J3 Winchester
Connector to the mating connector on the rear of the console.

12-5

If a line printer is used,

route the printer cable to the line printer and connect it.

NOTE
more than one VT8-E is installed in one system (up to four may
be installed in one system), the second control goes on the
If

OMNIBUS directly behind the first, and the third behind the second,
etc. The two controls are

interconnected by installing an H851 Top

Connector between M8335J of the first control and M8336J of the
second control. The controls must be assigned different device codes
(Tables 12-2 and 12-3).

Turn on PDP-8/E power and run the acceptance test in Paragraph 12.2.4.

Table 12-2
Device Code Select Jumper Installation

Group A

Group B

Group C

Group D

Group E

Group F

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

03
04
05
06
07

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

22
23

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

.2-1

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

33
34
35
36

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

Device

Code

12-6

Table 12-2 (Cont)
Device Code Select Jumper Installation

Group A

Group B

Group C

Group D

Group E

Group F

37
40

2-1

2-3

2-1

2-3

42
43
44
45
46
47
50

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3
2-3

Device

Code

•

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-3
2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

57
60

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

62
63
64
65
66
67
70

2-3

2-1

2-3

2-1

2-3

2-3
2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

73
74
75

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

Table 12-3
Priority Jumper Installation

M8337 Install

M8335 Install

Jumper

Jumpers

9 (highest)

W2
W3

P9and P10
P9'andP10
P9'andP10'

Priority

11 (lowest)

12-7

M8336

M8337

OPERATORS
CONSOLE

VT-8E No.1

VT8-E No. 2

Figure 12-2

VT8-E Module Installation

Acceptance Test

12.2.3

The VT8-E is checked for proper operation by running the two diagnostic programs. Both MAINDECs referenced in
the introductory remarks and the A-SP-VT8-E engineering specification give detailed instructions for their
performance

the

instructions shipped

with the paper tapes.

instructions, both in this manual and in Volume

problems

arise,

refer to the

maintenance

SECTION 3 OPERATION AND PROGRAMMING
H

This section provides a functional description of the VT8-E logic, operation and programming information, a list of

IOT instructions, and some VT8-E programming examples.
12.3

FUNCTIONAL DESCRIPTION

Each of the functional groups of logic in the VT8-E are described in the following paragraphs (Figure 12-3). Their
purpose, location (on what module), and function are provided to familiarize the reader with VT8-E operation. A
detailed description of VT8-E logic and timing is given in Chapter 4. Refer to Chapter 9 of the Small Computer

Handbook — DEC, 1972 for information about data transfers via IOT instructions and data breaks. A detailed block
diagram of the VT8-E which shows data flow and the interrelationship of the functional groups is in the VT8-E
Video Display Control Engineering Drawings.
12.3.1

VT8-E Printer/Keyboard Control Module (M8335)

The functional groups of logic on the M8335 module are discussed in the following paragraphs.
12.3.1.1

MD Bus Gating -Data from the MD lines

applied to the

M8337 module by I/O PAUSE if IOT

by the program or by MD EN during Single Cycle Data Breaks. Single Cycle Data Break is
data between memory and the display control (Paragraph 12.3.4.1).
transfer
method
used
to
the
instructions are executed

12-8

VT8-E PRINTER/KEYBOARD CONTROL (M8335)
(1) KEYBOARD AND PRINTER IOT DECODERS (2)
(2) MD BUS GATING
(3) DATA BUS GATING
(4) KEYBOARD BUFFER
(5) KEYBOARD FLAG
(6)1/0 TRANSFER CONTROL
(7UNTERRUPT AND SKIP LOGIC
(8) STARTING ADDRESS REGISTER AND COUNTER
(9) EXTENDED ADDRESS REGISTER AND COUNTER
(10) PRINTER BUFFER
(11) PRINTER FLAG
(12) HIGHER PRIORITY DETECTION

C0.C1
DATA 0- DATA 11

MD3-MD11

DATA (ASCI

KEYBOARD
48 KEY

CODE)

(ASCI CODE)

BUF MEM DATA

XADX CNTR
ADR CNTR
DATA

CODE)

PRINTER

LA30A-P
OR
LS01E

INT REQ

SKIP

MA0-MA11
.EMAO- EMA2
VT8-E LINE BUFFER (M8337)
(1) LINE BUFFER A AND B
(2) ASCII DECODING ROM
(3) VIDEO CONTROL
4) GRAPHIC VIDEO BUFFER
(5) CHARACTER BLANK DETECT
(6)E0S,BBF, AND EBF DETECT
(7) BLINK.CURSOR, BRIGHT, OR NORMAL DETECT
(8) DATA BREAK CONTROL
(9)

CONTROL
VIDEO

BREAK COUNTERS

(101MA AND EMA BUS GATING
(11JDATA BUS GATING
(12)

MAINTENANCE ENABLE

BRK RQST, MA, MS LOADCONT MS.IR DISABLED, MD DIR.CPMA PIS, BRK IN PROG
(PROCESSOR CONTROL SIGNALS)

CONTROL

MD9-MD11

FREQUENCY DIVIDER BOARD (M8336)
(1) DISPLAY IOT DECODER
(2) CLOCK AND FREQUENCY DIVIDER
(3) 64 OR 32 CHARACTER SELECTION
(4) ALPHANUMERIC TIMING CONTROL
(51GRAPHIC TIMING CONTROL
(6)CHARACTER COUNTER
'7) LINE COUNTER
8 ROW COUNTER

COMPOSITE. VIDEO
(SYNC AND VIDEO)

GRAPHIC

OR
ALPHANUMERIC
DISPLAY

!9) VIDEO CONTROL
(KDHORIZONTAL SYNC PULSE SHAPE
(11) VERTICAL SYNC PULSE SHAPER
(12)VIQ£0 AND SYNC COMBINING CIRCUITS
(13JVIDE0 ENABLE CONTROL
(14) REAL TIME CLOCK FLAG

Figure 12-3

12.3.1.2

VT8-E Block Diagram

IOT Decoders — The M8335 module contains two IOT decoders, one for the printer and one for the

keyboard. The decoders are assigned different device codes so that the printer IOT decoder is selected when printer

lOTs are programmed, and the keyboard IOT decoder

selected

when keyboard lOTs are programmed. The

keyboard and printer may be assigned any two of the device codes listed in Table 12-2. The device codes assigned to
the keyboard and printer must be different from each other and different from the display device code. The

decoders decode

IOT

MD9— MD11 from the MD lines and generate control signals to control keyboard and printer

operations; i.e., data transfers. The keyboard and printer instructions are listed in Paragraph 12.3.4.

12.3.1.3

Data Bus Gating - The Data Bus gates are enabled and DATA0-DATA1 1 are applied to the M8337 logic

when the following occur:
a.

If the program executes the

PNPC or PNLP instructions to load the Printer Buffer.

the program executes a DPLA instruction to load the Starting Address Register or a DPGO instruction

to load the Extended Starting Address Register.

During a Single Cycle Data Break. DAT0-DATA8, 9, or 10 monitored by the VT8-E during data breaks
to determine if the VT8-E has the highest priority for a data break.

12-9

Keyboard Buffer — The Keyboard Buffer receives a 7-bit ASCII code from the keyboard when one of the

12.3.1.4

is pressed. The keyboard also generates a KEYBOARD STROBE which enables the 7-bit
ASCII code to be transferred to the buffer and sets the KYBD flag. When the KYBD flag is set, an INT RQST is

keys on the keyboard

made if interrupts are enabled, or a SKIP if the DKSF instruction is executed by the program. An INT RQST or
SKIP notifies the program that data in the Keyboard Buffer is available to be read into the AC. The program must
transfer the data in the buffer to the AC and clear the KYBD flag so that a new 7-bit ASCII character can be
transferred from the keyboard to the buffer.
I/O Transfer Control — The I/O Transfer Control logic determines the direction of data flow on the Data

12.3.1.5

Bus and whether the AC is cleared or not. CO and C1 (the C lines) are asserted by IOT instructions which transfer
data to or from the AC.
Interrupt and Skip Logic — The Interrupt and Skip logic allows the program to enable the interrupts and

12.3.1.6

INT RQST when the

generate an

KYBD and PRINT DONE flags are set or to check the flags using a SKIP

instruction; i.e., the DKSF instruction.

Interrupt Logic — The Keyboard and Printer Interrupt logic is enabled

12.3.1.7

bit 1 1 in the

AC is set (1) when

DKIN instruction is executed by the program. If the interrupts are enabled, an INT RQST is made when the
KYBD flag is set or the PRINT DONE flag is set. The KYBD flag is set when a keyboard key is pressed, and the
PRINT DONE is set when the printer has finished printing a character.

the

Starting Address Register and Counter (SAR) - The Starting Address Register (SAR)

12.3.1.8

a 12-bit register

that is loaded from the AC with the memory address of the first word to be transferred by the Single Cycle Data

Break facility. The contents of SAR are transferred to the Starting Address Counter after the DPGO instruction is
executed by the program and the counter is incremented at the end of each data break to select the next sequential

memory address. The contents of the counter are applied to the Memory Address lines (MAO— MA11) to address a
location in memory.

Extended Starting Address Register — The Extended Starting Address Register (XSAR) is loaded from bits

12.3.1.9
6, 7,

and 8 of the AC by the DPGO instruction. The contents of XSAR are transferred to the XSAR Counter and

used to select a field in memory for data transfers. The XSAR is incremented when the SAR overflows to select the
next memory field. At this time the SAR starts reading memory locations in the newly selected memory field.
12.3.1.10
instruction.

Buffer -The Printer Buffer is a 7-bit register that is loaded from the AC by the PNLP
The data from the AC contains a 7-bit ASCII code for a character to be printed. The seven data bits are

Printer

transferred along with a PRINT STROBE pulse, and when the Print operation is completed, the PRINT DONE flag is
set. If

interrupts are enabled, an

INT RQST is made at this time, or if the flag is checked by the PNSK instruction,

the SKIP line is grounded. The program may perform a routine to transfer another character to the printer at this
time.

PRINT DONE Flag -The PRINT DONE flag is set each time the printer completes a print operation to

12.3.1.11

inform the program that the printer is ready to accept a new character.
Higher Priority Detection — The Higher Priority Detection logic monitors the Data Bus to determine if
VT8-E has the highest priority for a data break. If there are any peripherals connected to the OMNIBUS that
have a higher priority than the VT8-E, one of the lines on the Data Bus will be low to prevent the VT8-E from doing
12.3.1.12

the

a data break.

asserted

(low)

As an example, if the peripheral assigned the highest priority wants to do a data break, DATAO is
and the VT8-E cannot do a data break until

DATAO goes high at the completion of the other

peripheral's data break. When the VT8-E is ready to do a data break, DATA9, DATA10, or DATA1 1 will be asserted

low to prevent peripherals with a lower priority from doing a data break before the VT8-E. As can be seen from the
previous discussion, the VT8-E may be assigned one of the three lowest priorities.

12-10

12.3.2

VT8-E Line Buffer Module (M8337)

The functional groups of logic located on the VT8-E Line Buffer Module are discussed in the following paragraphs.

12.3.2.1

Line Buffers A and B - Line Buffers A and B provide temporary storage of 32 or 64 words from memory

the Alphanumeric mode or 32 words from memory in the Graphic mode. In the Alphanumeric mode the word
from memory (Figure 12-7) selects the visible field, display mode, and character to be displayed. In the Graphic
in

mode, the word from memory (16 words per line) consists of 1s (display a dot) and Os (do not display a dot) to
-»
produce a line on the face of the CRT. The display mode (Alphanumeric or Graphic) is selected by bit 10 (0
'->
program.
by
the
is
executed
ALPHA and 1 GRAPHIC) from the AC when the DPGO instruction
Each alphanumeric character is displayed on the face of the CRT in a 5 (width) X 7 (height) dot matrix. To display
one row of characters (32 or 64 characters), the Display Monitor makes 10 horizontal sweeps across the face of the

CRT. The first two scans are used to load the Line Buffers from memory via the Single Cycle Data Break. The third
scan addresses a blank ROM location and the remaining seven scans display the alphanumeric data. The first of the
seven scans displays the first line of each character in the row of characters to be displayed, the second scan the
second line, etc., until seven scans are completed to display a row of characters (32 or 64). When the tenth scan is

completed, the program must set up for a new break and initiate a new break cycle to reload the Line Buffers if
additional rows of characters (20 maximum) are to be displayed. During the display operation the 7-bit ASCII code
(Figure 12-7) is decoded by the ASCII decoding ROMS to generate the video signals to be displayed and the four
control bits are decoded to determine the display mode and visible field.

A display may be stopped after any number

of characters have been displayed, if the display is less than 20 rows, to save computer time. This is done by setting

CB1 and CB2 to 1s when the last character is displayed.
Graphic mode, data is displayed on the face of the CRT in a 189 (width) X 200 (height) dot matrix. Each line
(189 dots) requires 16 12-bit words. The last three bits of the sixteenth word are not used. Each bit of the data word
In the

represents a dot or space on the face of the

CRT. A logical 1 causes a dot and a logical

leaves a space.

As an

example, 16 words of data containing all 1s displays a row of dots on the face of the CRT. In the Graphic mode,
3200 (200 X 16) words must be defined because there is no way to generate End-of-Screen (EOS). If the full screen
is

not used, the remainder of the memory locations used should contain all 0s.

12.3.2.2

ASCII Decoding ROMs - The ASCII decoding ROMs decode the 7-bit ASCII code from the Line Buffers

and generate a video signal for each line of each character to be displayed. After the start of a horizontal scan, data is
ROM
shifted out of the Line Buffers to address (the buffer is in a recirculating mode, thus an end-around shift) a

ROM

character generator locations are
character generator location and generate video for one line of the character.
are
addressed seven times (once for each horizontal scan). The video signals generated each time it is addressed

changed by the assertion of signals inside the ROM to change the video pattern and produce the desired character
Buffer where it
after seven scans. The video out of ROM (VIDE01-VIDE05) is applied to the Alphanumeric Video
is

spaces to appear
shifted out to the Video Control logic as five serial video pulses. These pulses will cause dots or

on the face of the CRT and after seven scans, an alphanumeric character is formed.
Graphic Video Buffer - In the Graphic mode, the contents of the Line Buffer are transferred one word at
is converted to serial video
a time to the Graphic Video Buffer. From the Graphic Video Buffer the 12-bit word
12.3.2.3

pulses and applied to the Video Control logic. Dots are displayed for data 1s and spaces for data 0s.

12.3.2.4
(Figure

Character Display Mode Detection Logic - The Character Display mode is determined by CB3 and CB4
in the
12-7) of the data word from memory. As shown in Figure 12-7, the character may be displayed

Normal, Blink, Bold, or Cursor modes. The Mode Detection logic decodes CB3 and CB4 to assert the control signals
necessary to select the four modes.

12.3.2.5

Visible Field Detection Logic

word. As shown

- The visible field is determined by CB1 and CB2 (Figure 12-7) of the data

Figure 12-7, the character may be displayed in the mode selected by CB1 and CB2 (NOP), a

12-11

blank field may be ended and the display enabled (EBL), a blank field may be started (BBF) or an End of Screen

(EOS) may be selected to end the display.

EOS is particularly helpful because it allows smaller displays to be

displayed without using the entire core buffer. This saves core buffer space and reduces processor loading.
Single Cycle Data Break Control Logic - The Single Cycle Data Break Control logic is used to force the

12.3.2.6

processor into the Direct Memory Access (DMA) state and transfer data between core memory and the VT8-E Line
Buffers via the Memory Data lines. Memory is addressed by the outputs of Starting Address and Extended Starting

Address counters which are applied to the Memory Address lines at the beginning of the break cycle.
Processor Control Signals - When the processor is forced into the

12.3.2.7

DMA state, the VT8-E must generate

control signals to control the processor. The control signals required to accomplish this are shown in Figure 12-3 and

explained in Chapter 9 of the Small Computer Handbook - DEC, 1972.

Break Counters — The Break Counters

12.3.2.8

overflow after 32 words

are

used to count the words

are transferred in the 32 character

data transfer. The counters

mode or after 64 words are transferred in the 64

character mode to stop data transfers and release the processor.

MA and EMA Bus Gates -The MA and EMA Bus Gates apply the contents of the Starting Address
Counter and Extended Starting Address Counter to the OMNIBUS MA lines during a data transfer. This allows the
12.3.2.9

selection of a memory field and memory location to be used in a data transfer.

12.3.2.10

Data Bus Gates -The Data Bus gates are enabled when the

DPMD instruction is executed by the

program to transfer data to the Data Bus. This allows VT8-E registers and buffers to be read into the AC for display
or evaluation by the program. To read the Display Buffers and Register with IOT instructions the Maintenance logic

must be enabled.

12.3.2.11

Maintenance Enable - The Maintenance

logic

enabled by the

DPSM

instruction. This allows the

program to read the VT8-E registers and buffers using the maintenance instructions. It also allows data breaks to be
taken by the VT8-E at a rate determined by the program.
12.3.2.12

Frequency Divider Board (M8336) - The functional groups of logic on the M8336 module are discussed

in the following paragraphs.

12.3.2.13

Display IOT Decoder - The Display IOT Decoder decodes the Display instructions and generates the

necessary control

signals

to set up for data

breaks,

maintenance operations, and data transfers using IOT

instructions. The decoder is enabled when I/O PAUSE is asserted and the device code assigned to the display for this

VT8-E is decoded and decodes bits MD9— MD11 of the IOT instruction. At this time the C lines are asserted to
control the direction of the data transfer,

INTERNAL I/O is asserted to prevent the processor from performing

other lOTs, and the instruction is executed by the VT8-E.

12.3.3

VT8-E Clock and Frequency Divider (M8336)

The VT8-E Clock and Frequency Divider generates the necessary CRT sync pulses and control signals required to
display data on the CRT. The timing chain consists of a 21.84 MHz crystal controlled oscillator and a chain of
divide-by counters with selected outputs used to generate sync and control signals. Jumpers are provided to allow

the selection of 64 or 32 character display control signals. These jumpers allow control signals of different
frequencies to be selected for the display of 32 or 64 characters per row. The counters in the timing chain and their

function are discussed in detail in Paragraph 12.4.2.2.

12.3.3.1

Real Time Clock Flag - The Real Time Clock flag

interrupts are enabled, an interrupt request

set (1) at the start of each vertical retrace.

made, or if a Skip instruction is being executed by the program, the

SKIP bus is grounded and the program will skip an instruction.

12-12

Video and Sync Combining Circuits -The Video and Sync Combining circuits combine the horizontal
and vertical sync with the video pulses from the ROM Character Generator to produce a composite video signal.
12.3.3.2

12.3.4

IOT Instructions

The following instructions are used to program the VT8-E.
12.3.4.1

Display Instructions — The Display instructions assume device code 05

used. There are

64 possible

device codes which can be used (Table 12-2) for the display. The device code for the display, keyboard, and printer

must be different (e.g., device code 03 for the keyboard, 04 for the printer, and 05 for the display). If more than
is installed in the same system, three new device codes must be selected for the second VT8-E. They

one VT8-E

must also be different from each other and different from the device codes assigned to other PDP-8/E options
installed in the system.

Load Starting Address Register (DPLA)
Octal Code:

6050

Operation:

Transfer the contents of the AC to the Starting Address Register (SAR) and clear the AC. The AC

must contain the address of the first memory location to be used in a data transfer. The contents of
SAR are transferred to the Address Counters and incremented at the end of each Single Cycle

the

Data Break. This allows the sequential selection of locations in memory for data transfers.

Load Extended Starting Address (DPGO)
Octal Code:

Operation:

6051
Transfer the contents of AC10 and AC1 1 to the Mode Select logic, and AC6— AC8 to the Extended
Starting Address Register (XSAR). AC10 and AC1 1 are used to select Alphanumeric or Graphic mode

and enable or disable the interrupt system as follows:

AC10

AC11
Alphanumeric Mode, Interrupt Disabled
1

Alphanumeric Mode, Interrupt Enabled
Graphic Mode, Interrupt Disabled

1
1

Graphic Mode, Interrupt Enabled

AC6-AC8 must contain the memory field to be used in a data transfer. The XSAR Register is
incremented when the SAR overflows at the end of each memory field to select the next memory
field. The SAR selects the first location (0000) in the new memory field. Data transfers may start
immediately after this instruction is executed.

STOP the Display (DPSM)
Octal Code:

6052

Operation:

STOP the display and inhibit video and VT8-E initiated data breaks. This instruction also transfers
AC11 and AC6-AC8 from the AC to the Maintenance logic and the Extended Starting Address
Register. If AC1 1 is 1, the Extended Address Register is loaded with the contents of AC6— AC8. If
AC1 1 is 0, the contents of the Starting Address Register are transferred to the Address Counters and
the VT8-E is set up for a maintenance break. The AC must contain the memory field in AC6— AC8
and AC1 1 must be 1 or
to determine which operations are to be done before this instruction is

executed.

12-13

Maintenance Instruction (DPMB)
Octal Code:

6053

Operation:

Transfer the contents of the memory location specified by the Address Counter to the Data Buffer.

The Address Counter is incremented by 1 to select the next location in memory.
Maintenance Instruction (DPMDj
Octal Code:

6054

Operation:

Jam-transfer the contents of the Data Buffer to the AC. Note that the DPMB and DPMS may be used
to transfer data from memory to the Data Buffer and then to the AC where it is displayed. This could
aid in troubleshooting the VT8-E.

Maintenance Instruction (DPMS)
Octal Code:

6055

Operation:

Transfer the contents of the Extended Address Counter to AC6-AC8 and the state of the SENSE

switch into ACO (Figure 12-4). This allows the program to determine what memory field is selected
is a logical 1 when the SENSE switch is on
and determine the condition of the SENSE switch. Bit

and

when the SENSE switch is off. This switch is located on the keyboard and the

logical

programmer determines its use and meaning.

LSB

MSB
MSB

SENSE
SWITCH
1 =ON
0=OFF

LSB
c DNTEN1 S

EXTEN
ADDRE SS REG ISTER
(MEM ORY Fl ELD)

- NOT

USED

Figure 12-4

NOT
USED

Extended Address and Sense Switch Data

Skip On Real Time Clock Flag (DPCL)
Octal Code:

6056

Operation:

Skip the next instruction if the Real Time Clock flag is set (1) and clear the flag. Real Time Clock flag
is set

at the start of each vertical retrace.

Generate A Bell Tone (DPBL)

Octal Code:

Operation:

6057
Generate a half-second audible tone for use as a bell. This tone can be heard by the operator and can

be used to alert the operator that he must respond; i.e., supply data to the program via the keyboard.

12.3.4.2

Keyboard Instructions - The keyboard instructions assume a device code of 03 has been selected for the

keyboard.

12-14

Clear Keyboard Flag (DKCF)

Octal Code:

6030
Clear the Keyboard flag. The Keyboard flag is set when the Keyboard transmitter is ready to transfer

Operation:

data, usually after one of the keyboard keys has been pressed.

Skip on Keyboard Flag (DKSF)
Octal Code:

6031

Operation:

Skip the next sequential instruction

Keyboard flag is set. Keyboard flag sets when one of the

keyboard keys has been pressed to supply data to the program.
Clear Keyboard Flag and

AC (DKCC)

Octal Code:

6032

Operation:

Clear the Keyboard flag and the AC.

Logically OR Keyboard Buffer and the

Octal Code:

6034
Logically

Operation:

AC (DKOB)

the

contents

AC5-AC11, and transfer a

the

Keyboard Buffer with AC5-AC11, deposit the

result

to AC4. AC0-AC03 remain unchanged. When DKOB is combined with

the CLA instruction, the contents of the Keyboard Buffer are transferred to AC5-AC1 1

Enable Keyboard Printer Interrupt (DKIN)
Octal Code:

6035

Operation:

Enable Keyboard Printer interrupt if AC11 = 1 or disable if AC11 = 0. AC11 must be set to 1 or
before this instruction is executed by the program.

Read Keyboard Buffer (DKRB)
Octal Code:

Operation:

6036
Jam-transfer the contents of the Keyboard Buffer to AC5-AC11 (Figure 12-5), set AC4 to 1, clear
AC0-AC3, and clear the Keyboard flag. AC5-AC6 contains a 7-bit ASCII code which represents the

key pressed on the keyboard.

DATA BITS

8.9

I
Figure 12-5

MOST SIGNIFICANT ASCII BIT

Keyboard Data Format

12-15

12.3.4.3

Printer Instructions

- The following instructions assume a device code of 04 is used for the printer.

Set Printer Flag (PNSF)
Octal Code:

6040

Operation:

Set the Printer flag

Skip on Print Done Flag (PNSK)
Octal Code:

6041

Operation:

Skip the next sequential instruction if the Print DONE flag is set.

Clear Printer Flag (PNCF)

Octal Code:

6042

Operation:

Clear the Printer flag.

NOTE
Octal Code 6043 is not used.

Load Printer Buffer (PNLP)
Octal Code:

Operation:

6044
Load the Printer Buffer from AC5-AC1 1 (Figure 12-6) and Print. AC5-AC1 1 contains a 7-bit ASCI
code which determines the character to be printed.

8
i

t BIT ASCII

L MOST

ANT A 3CII Bl T

£ IGNIFK

GNORE D BY F'RINTEF

Figure 12-6

Printer Data Format

Skip on Keyboard or Printer Interrupt (PNSI)
Octal Code:

6045

Operation:

Skip if the interrupt is enabled and either the Keyboard or Print DONE flag is set.

Load Printer Buffer (PNPC)
Octal Code:

6046

12-16

Operation:

Load Printer Buffer from AC5-AC11 (Figure

12-6), Clear Print

DONE flag, and Print. The 7-bit

ASCII code determines the character to be printed.
12.3.5

Display Data Format

The two types of data that can be displayed on the VT8-E CRT are alphanumeric and graphic data.
12.3.5.1

Alphanumeric Data Format - Alphanumeric data displayed on the CRT is determined by the 12-bit word

memory during a Single Cycle Data Break. This word determines the visible field,

(Figure 12-7) transferred from

character display mode, and the character to be displayed as shown

Figure 12-6. The VT8-E can display 20 lines

of alphanumeric information; 64 normal sized characters or 32 enlarged characters can be displayed on each line.

NOTE
EOS allows termination of the display and LF code 012 allows
termination of the current row. Both termination methods
save core

memory and computer time for display with less

than 20 lines.

MD BIT

NOT
USED

7 BIT ASCII CODE

CB2

CBl

(SEE TABLE 3-2)

CB4

CB3

MSB
VISIBLE
FIELD

CHARACTER

CONTROL

MODE
CONTROL

BITS

LSB

DISPLAY

B ITS

CBl

CB2

CB3

VISIBLE FIELD CONTROL BITS

NOP

CB4

CHARACTER DISPLAY MODE CONTROL BITS

NORMAL

VISIBLE FIELD, DISPLAY

ACCORDING TO CBl, CB2.

EBF

END BLANK

FIELD.

ENABLE

BLINK

1.9Hz

CHARACTER.

EOS

BLINK THIS CHARACTER AT A

RATE (1.6Hz FOR 50Hz
SYSTEMS) IF IN VISIBLE ZONE.

VIDEO STARTING WITH THIS

BBF

DISPLAY THE CHARACTER IN BITS
AT NORMAL INTENSITY IF IN
VISIBLE ZONE.

5-1

CHARACTER IN BITS 5-11

BOLD

BEGIN BLANK FIELD. DISABLE
VIDEO FOR THIS CHARACTER
AND THOSE FOLLOWING.
BLANK FIELD CAN BE TERMINATED BY EBF CONTROL
CODE.

DISPLAY THIS CHARACTER AT IN-

CREASED INTENSITY IF

CURSOR

VISIBLE

DISPLAY THIS CHARACTER AS A
CURSOR IF IN A VISIBLE ZONE.

THE CHARACTER AND ITS DOT
MATRIX COMPLEMENT ARE DISPLAYED ALTERNATLY AT A 3.7Hz
RATE (3.1Hz FOR 50Hz SYSTEMS).

END OF SCREEN. THE PREVIOUS CHARACTER IS THE
LAST TO APPEAR ON THE
SCREEN. VIDEO AND DATA

BREAKS ARE INHIBITED UNTIL
THE NEXT VERTICAL RETRACE.
THIS ALLOWS ABREVIATED
DISPLAY BUFFERS WHEN IT IS
NOT DESIRED TO USE THE
ENTIRE SCREEN. THIS SAVES
CORE BUFFER SPACE AND REDUCES PROCESSOR LOADING.

Figure 12-7

ZONE.

Alphanumeric Display Data Format

12-17

12.3.5.2

Graphic Data Format — The VT8-E is capable of displaying graphic information on a 189 (width) X 200

(height) dot matrix.

Each dot position corresponds to a bit of a data word in the core buffer. The first word of the

buffer defines the first 12 dots on the first row. Bit
1, a

the first to be displayed and bit 1 1 the last. If a bit is set to

dot is displayed and if it is set to 0, no dot is displayed. Sixteen 12-bit words are required to display one line of

graphic data. The

last

3 bits of the sixteenth word are not used. As an example, 16 words of all 1s (7777) from

memory would cause a line of 189 dots to be displayed on the face of the CRT. In the Graphic mode there is no way
to terminate the buffer short of 3200 words (200

lines),

thus the entire buffer must be defined even if a major

portion is blank.

12.3.6

12.3.6.1

Display Monitor and Keyboard Switches and Controls
Display Monitor Switches and Controls — Table 12-4 lists the switches and controls found on the Display

Monitor enclosure.

Table 12-4
Switches and Controls
Control/Switch

Location

Function

CONTRAST Control

Right-hand side

Used to adjust the picture for contrast.

BRIGHTNESS Control

Right-hand side

Used to adjust the

CRT brightness

(intensity).

VERTICAL Control

Right-hand side

Used to synchronize the raster in the
vertical direction.

HORIZONTAL Control

Right-hand side

Used to synchronize the raster in the
horizontal direction.

ON/OFF Switch

1 1

5V/230V

AC Circuit Breaker

Keyboard upper-

Applies primary

right corner

ON position.
115V or 230V

the

Right-hand side

Selects

of CRT frame

power for the display.

Rear panel

Resets circuit breaker after
momentary fault (do not hold in).

pushbutton

SENSE switch

power when

Right-hand side

primary

Use determined by the programmer

ON = logical 1
OFF = logical

12.3.6.2

Keyboard Controls - The basic function of the Keyboard is to provide a convenient, on-line method of

transmitting ASCII-coded characters to the CPU for processing and, perhaps, display on the VT8-E CRT screen. The

keyboard transmits an ASCII code directly to the computer each time a key is pressed, and the computer, in turn

may transmit the character code to the VT8-E Control Logic. The Control Logic determines if the received data is to
be displayed or used to control the displayed text format.

12-18

The keyboard can transmit either full ASCII or a 97-character subset. The selected code is determined by an internal
selector switch. With the switch set to position 1, the keyboard transmits the full ASCII character set listed in Table
12-5. With the internal switch set to position 2, the keyboard transmits the 97-character ASCI

subset listed in Table

12-6.

The VT8-E Display Monitor does not display lower case alphabetical characters. However, it c?n receive both upper
and lower case characters, which are interpreted and displayed as upper case characters (Table 12-7).

Table 12-5

VT8-E Transmit Codes - Full ASCII Operation
7
Bit No.

4 3 2

••

[

t:jj'"E^<W'\

•1

10
1

110
111

•

c<-

*;:lS*;* r

(BS)
1

10 10

space

;

ftps
i

fr\ .:!sS''i~s
!

ALT

ci '\st)
;

110

{

,'"""

110

1110
1111

HOMEI^

;

y—~—

ERAS^fc

''"

ERASER ')

SCREEN-

f' "

LINE O;

•^'ff,^0fi

;jr !

,3"*

CTRL
Shifted

12-19

" j.;*"

;;;

':n'-

]

}
rs?

DEL
(rub out)

Table 12-6

VT8-E Transmit Codes - Half ASCII Operation
(switch in position 2)

7
Bit No.

5
4 3 2

1
1

(0)

110

space

'y| 'Jj'j »:!::;
:

111
10
10

c<(BS)
1

10 10

10 11

c->

""iM&:
;

1110
1111

[

HOME

]

ALT

ERASE

DEL

...

110

(0)

LINE

ERASE
SCREEN

Shifted

12-20

(rub out)

Table 12-7

VT8-E Receiving Codes
7
Bit No.

4 3 2

6
1

D
1

110

111

(

)

10
10

10 10

10 11

[

110

]

110

1110
1111

space

/""\

[

]

r—\

12-21

>
/

space

•'

>
1

Programming Examples

12.3.7

The following VT8-E programming examples are programs that may be used to display alphanumeric or graphic data
on the CRT.

12.3.7.1

Graphic Display Program Example - This program displays data from the Switch Register in a 189 X 200

dot matrix. A dot is displayed for those bits on the Switch Register that are set to 1s and a space is displayed for
those bits in the Switch Register that are set to 0.

Location

Instruction

0200

6007
1216
6050

0201

0202
0203
0204
0205
0206
0207
0210

Mnemonic

VTGRPH

0212
0213
0214
0215

VT,

0221

0222

/THE DATA IN THE SR.

/LENGTH OF DISPLAY BUFFER
/SET COUNTER FOR FILLING BUFFER.
/READ DATA PATTERN FROM THE SR.
/STORE IN BUFFER
/BUFFER FILLED.
/NO, CONTINUE FILLING IT.
/RELOAD BUFFER AGAIN.

COUNT

LAS

5205
0400
0377
0000
0002
1600

TAD
DPGO
TAD
DCA
TAD
DCA
DCA

5211

0216
0217
0220

M6200

BUF

DPLA

6051

0211

BUFM1

/CLEAR AND INITIALIZE.
/LOAD THE STARTING ADDRESS
/OF THE DISPLAY BUFFER INTO THE VT8-E.
/CODE FOR GRAPHIC
/DISPLAY IN GRAPHIC MODE.
/SET AUTO INDEX FOR STORING

CAF

TAD

1221

1217
3010
1222
3220
7604
3410
2220

Operation

ISZ

COUNT

JMP
JMP

BUF,

400

BUFM1,
COUNT,

400-1

K2,

M6200,

-6200

-3

/STARTING ADDRESS OF BUFFER.
/STARTING ADDRESS OF BUFFER -1.
/COUNTER FOR FILLING BUFFER.
/GRAPHIC ENABLE WORD.
/COUNT FOR FILLING BUFFER.

12.3.7.2 Alphanumeric Display Program Example — This program echos the character typed on the console
keyboard on the VT8-E display. The Switch Register is ORed with the character to display the character in the
Normal, Blink, Bright, or Cursor mode. The display mode is selected from the Switch Register (Figure 12-7) as
follows:

0000
0200
0400
0600

Normal
Blink
Bright

Cursor

12-22

Memory
Location

Instruction

0200

6007
1233
3010

Mnemonic

VTALPH

Operation

CAF

TAD
DCA

BUFM1

1235
3410
1240
3234

TAD
DCA
TAD
DCA
TAD
DCA

0211

1232

TAD

0212
0213
0214
0215
0216
0217
0220

6050

DPLA
DPGO

0221

1235
3410
7604

0201

0202

0203
0204
0205
0206
0207
0210

0222
0223

0224
0225
0226
0227
0230

12*3
3011

6051
6031

INPUT,

5214
6036
0236

0236
0237
0240

0177
0600
5400

COUNT
BUF

/CHARACTER YET
/NO, WAIT.

.-1

/READ THE CHARACTER.

K177

/KEEP ONLY 7 BITS.
/SAVE IN THE MQ REGISTER.

EOS

/MOVE THE END-OF-SCREEN
/CHARACTER UP ONE IN THE BUFFER.
/READ DISPLAY MODE CONTROL BITS
/FROM THE SR.
/SAVE ONLY THE CONTROL BITS.
/"OR" THE CHARACTER WITH THEM.
/STORE CHARACTER WITH CONTROL BITS.
/FULL SCREEN (64 CHAR MODE)?
/NO, GET ANOTHER CHARACTER.
/YES, RESTART THE PROGRAM.

LAS

AND
MQA
DCA

3411

0400
0377
0000
3000

M2400

KSF
JMP

DCA

7501

0232
0233
0234
0235

KRB

0237

0231

EOS

AND
MQL
TAD

7421

2234
5214
5200

K600

ISZ

COUNT

JMP
JMP

VTALPH

BUF,

400

BUFM1,
COUNT,

400-1

EOS,

3000

/CLEAR AND INITIALIZE.
/ADDRESS OF BUFFER -1.
/SET AUTO INDEX FOR POSITIONING
/THE END OF SCREEN CHARACTER.
/ADDRESS OF BUFFER -1.
/SET AUTO INDEX FOR STORING CHARACTERS.
/GET THE END-OF-SCREEN CHARACTER (3000).
/PUT END OF SCREEN IN DISPLAY BUFFER AREA.
/SET COUNTER SO PROGRAM IS RESTARTED
/AFTER A FULL SCREEN IS DISPLAYED.
/(64 CHARACTER MODE)
/LOAD THE STARTING ADDRESS
/OF THE DISPLAY BUFFER INTO THE VT8-E.
/GO DISPLAY.

INPUT

/STARTING ADDRESS OF BUFFER.
/STARTING ADDRESS OF BUFFER -1.
/FULL SCREEN COUNTER.
/END-OF-SCREEN CHARACTER.

K177,

177

II BIT MASK.

K600,

600
-2400

/CONTROL BIT MASK.
/LENGTH OF BUFFER.

M2400,

SECTION 4 DETAILED LOGIC DESCRIPTION
12.4

INTRODUCTION

A simple block diagram of the VT8-E Video Display and Control is shown in Figure 12-8. The interface supplies the
monitor with video and sync signals, and an audio tone. The video is either alphanumeric character information or
graphic information, or a combination of the two that is made possible by switching the display mode at the screen
refresh rate.

12-23

INTERFACE MODULES
PDP8/E,
8/F.8/M

DATA BREAK XFER,
DISPLAYABLE DATA

DISPAY MONITOR

M8337

^PROGRAMMED INTERRUPT

^96-128-CHARACTER ASCII
SET

M8335

XFERS

128-CHARACTER ASCII
SET

Figure 12-8

CRT DISPLAY CKTS

VIDEO.AUDIO.SYNC

M8336

OMNIBUS

DEC STANDARD

KEYBOARD

LA30(A)-P

OR
LS01-ED PRINTER

VT8-E Functional Block Diagram

The keyboard transfers data directly to the computer's AC Register by program interrupts or flags. Each character
code transmitted can either be displayed or used to control the displayed text format. Data transmitted to the
system printer is also transferred by program interrupts or flags. When the Interrupt System is disabled, flags are
checked by the SKIP instructions.

The

logic

description

divided

into

two

parts:

one part concentrates on the interface

logic for

both the

keyboard/printer and the display, while the second part concentrates on the keyboard and CRT circuits.

12.4.1

Keyboard/Printer Logic

A block diagram of the VT8-E Keyboard/Printer logic is shown in Figure 12-9. Pin assignments for OMNIBUS signals
and connector signals can be found on Engineering Drawing E-CS-M8335-0-1.

OMNIBUS

KYBD(O) L

DATA 4-11 L
IOT

CONTROL
SIGNALS

•

KEYBOARD
TRANSMIT
LOGIC

KEYBOARD
"STROBE L
-BIT 1-7 L

SKIP L-«INT

RQST L-*IOT,

INTERNAL J/O L-*-

CONTROL
SIGNALS

CO L,C1 L-*-

INT/SKIP
LOGIC

DATA
l/O

PAUSE L-

MD 3-11 L-

DEVICE

AND IOT
DECODER
LOGIC

IOT
INSTRUCTIONS

-INITIALIZE L
PRINT(O) L

-BIT 1-7
.PRINTER
INITIALIZE L

INITIALIZE-

7T>

STROBE L
IOT,

CONTROL

PRINTER
RECEIVE
LOGIC

SIGNALS

DATA 5-11 L-

-DEMAND

Figure 12-9

Printer/Keyboard Block Diagram

12-24

The VT8-E Keyboard/Printer logic has two distinct functions:
Printer Buffer Register and transfer of data from the

transfer of data from the CPU

AC Register to the

Keyboard Register to the AC Register. The transfer of data to

the Printer Buffer is carried out by the Printer Receive logic. When the printer is able to receive data, it asserts the

DEMAND signal. This signal sets the PRNT FLG flip-flop in the Printer Receive logic. The resulting PRNT (0) L
causes the INT/SKIP logic to assert the OMNIBUS INT RQST L signal, if the VT8-E has been logically
connected to the interrupt system. Alternatively, PRNT (0) L can be tested by a program skip instruction in the
signal

INT/SKIP logic.
transfer.

In either case, the

computer ultimately proceeds to a program subroutine that begins the data

When this subroutine is executed, the information is transferred from the AC Register to the DATA 5—1

and clocked into a 7-bit register in the Printer Receive logic. The register outputs are available at J1 as the BIT
1-7 signals. The logic then generates a PRINTER STROBE L signal that clocks the BIT 1-7 data into the Printer

lines

Buffer Register, clears the PRNT FLG flip-flop, and causes the printer to negate the

DEMAND signal.

The transfer of data from the Keyboard Buffer Register to the AC Register is carried out by the Keyboard Transmit
logic. When a keyboard key is pressed, information is applied, via the BIT 1—7 lines, to a 7-bit register in the
Keyboard Transmit logic. When the keyboard generates a KEYBOARD STROBE L signal, the information is clocked
into the 7-bit register and the

with

SKIP

KYBD FLG flip-flop

set. The

instruction, or the interrupt system can

KYBD (0) L signal can be tested in the INT/SKIP logic

be used to cause the program to enter an appropriate

subroutine. When the subroutine is executed, the information is gated from the register in the Keyboard Transmit
logic to lines

DATA 5—1 1 (the logic asserts the DATA 4 L signal separately so that the input character is compatible
Teletype code), then to the AC Register. The AC is loaded and, simultaneously, the KYBD

with the modified- ASCI

FLG flip-flop is cleared.
12.4.1.1

IOT Decoder Logic — The IOT Decoder logic is shown in Figure 12-10, which includes the Video Display

Decoding logic for reference. The VT8-E Keyboard/Printer uses 12 IOT instructions, 6 for the keyboard and 6 for
the printer. (One of the listed printer lOTs, Skip on Printer or Keyboard Interrupt, apply to both functions and one
of the keyboard lOTs, Interrupt Enable/Disable.) More than one keyboard/printer can be interfaced to the PDP-8/E
at the same time.

The VT8-E (or other control module) associated with each keyboard/printer must be assigned a

unique device selection code for both the keyboard and the printer. Therefore, the M8335 module is fabricated with

jumpers and solder terminals that allow the user to assign any one of 64 possible device selection codes to both the

keyboard and the printer (care should be taken when assigning device selection codes to preclude multiple
assignments of the same code). Figure 12-10 illustrates the octal codes and mnemonics that pertain when the VT8-E
is

manufactured. The octal codes and mnemonics for the instructions are listed in Paragraph 12.3.2. A complete list

of device codes and the jumpers required to select each device code is shown in Table 12-2.

12.4.1.2

Printer Receive Logic

— The Printer Receive logic is shown in Figure 12-11. Significant signals are related

by the timing diagram in Figure 12-12. Refer to both figures when reading the logic description.

The printer routine is initiated by DEMAND changing to the true state, indicating that the printer is ready for
another character. This sets the PRNT flag flip-flop. This flip-flop can also be set by the PNSF instruction at TP3
time.

the VT8-E is logically connected to the interrupt system, as this discussion assumes, the PRNT FLG (1) L

signal causes the

INT/SKIP logic to assert the OMNIBUS INT RQST L signal. The program proceeds to an interrupt

servicing routine to determine the identity of the requesting device. The PNSI instruction in the routine causes the

program to jump to a VT8-E routine that determines whether the printer or keyboard requested the interrupt (other
options are open to the programmer, this is but one example). Ultimately, the VT8-E printer routine executes the

PN PC instruction.
During TS2 of the PNPC instruction, information is gated from the AC Register to the DATA lines and remains on

DATA lines through TS3. When PNPC L is decoded in the IOT Decoder logic, it enables NOR gates E25Cand
E25D (Figure 12-11). NOR gate E25-D asserts the DATA EN signal; both DATA EN A L and DATA EN B L are
derived from this signal. The difference between the DATA EN A L and DATA EN B L signals is significant only
when considering the Display logic; for the present one must know only that one of these two signals gates lines
the

DATA 9 and DATA 10 to the 7-bit register. The remaining DATA lines are gated to the register flip-flops as shown.

12-25

P/0

M8336 MODULE

^=>

E46

DPLA L
DPGO L

DPSM L

BCD-TO- 3
DECIMAL

7442

DPMB L

•

DPMDL

•

DPCL L
SELECT DISPLAY L

MD11 L—*

604X-

7b— DPBL L

MSB

tDr

.INTERNAL
I/O L

603 X605X-

MD10 L-

rcy

MD9 L-

MD3 L-

i>]
DKCFL
DKSKL

MD4 LE18

DKCC L

DKOBL

BCD-TO DECIMAL

7442

=33

M05 L-

5 P^DKTNL

-t>~

MSB

M06 Li

2
E26
BCD-TO- ,
DECIMAL 3

7442

MD7 L-

BZ>

KYBD

4
S

i>~ MSB

DKRB L

-PNSF L
-PNSK L
-PNCF L

-PNLP L
-PNSI
-PNPC L

MD8 L-

'AW
+ 5V

I/O PAUSE

CO L

"ENABLE L

NOTE:
Logic is P/0

DKOB L

M8335 module, unless noted otherwise.

Figure 12-10

IOT Decoder Logic

12-26

PNSF L

d
\
E24 yq
J

DATA 11 L

DATA 10 L
I

~i
"

PRNT FLG

e— —

—

°l

E24

V-

°a

BIT1

El 9

DATA 9 L

E24

|BIT2-5l

SAME

74174

HEX
F/F

DATA 8 L

E24
DATA 7 L

P V

E23

°F

E23

DATA 6 L
pi
nrir
CLOCK

j-T>j
"^

BIT 6

DATA 5 L

E23

"€>
ro
-j

DATA

\tH AL

-^P—Qtp

«,.
+ 5V

+3V

b.
D

STROBE

E38

E39

TS2

PJE>
TP3 L-

Printer Receive Logic

BIT 7

+ 3V

STROBE

Figure 12-11

-•

Logic is P/0 8335 Module unless noted

-> f

7474
F/F

DATA
EN BL

NOTE:

E38

E41

_PRINTER
\j__^STROBE
L

^Z"

At TP3 time of the instruction, NAND gate E-17 is enabled and the information on the DATA lines is clocked into
the 7-bit register. Simultaneously, flip-flop STROBE 1 sets and the PRNT FLG flip-flop is cleared. The register data
applied, via the BIT 1-7 lines, to the Printer Buffer Register. At the beginning of TS2 of the instruction following
PNPC, flip-flop STROBE 2 sets and asserts PRINTER STROBE L. This signal loads the Printer Buffer Register and

DEMAND signal. Both STROBE and STROBE 2 are cleared by the next TP3. When the print cycle
again asserted and a new transfer can be started.
ends approximately 30 ms later, the DEMAND signal
negates the

PRINT CYCLE.
ss30MS

DEMAND.

PRNT FLG (1) L

INT ROST L

PNSI

SKIP L

PNPC

TS2

TP3.

DATA 11-5 L

BIT 1-7.

INSTRUCTION

xxxx

RCVR STROBE

note:

T1.T2 and T3 are distinct time periods.
The amount of time between periods is
a function of program-routine execution time

Figure 12-12

Printer Receive Logic Timing

12-28

12.4.1.3

Keyboard Transmit Logic - The Keyboard Transmit logic is shown in Figure 12-13. Significant signals are

related by the timing diagram in Figure 12-14. Refer to both figures when reading the logic description.

DKCF L-

"7E>-r-[>
DKCC L

E37

KYBD
FLG

KEYBOARD
STROBE H

— KYBD FLG

(1)

OKOB
DKRB

'zJB>-

BIT 1L

°a

;^g>>— DATA

-M-

BIT 2 L

BIT 3 L

r ^:
»
-WV

74175 -zr

D B QUAD OB
F/F

CLOCK

e>a

—

-WV—

°C

E28 JO

DATA 10 L

E28

DATA 9 L

E28

DATA 8 L

BIT4 L

E32

tz:;

BIT

•-

Db
E31

74175

;z£^>— DATA

7 L

;zzE>— ATA

6 L

QUAD
F/F
BIT 6 L

r^.:
-AM

BIT 7L

•>

-+•—<>

CLOCK

+3V

NOTE:
Logic Is P/0

;=E^

°D

M8333 module

Figure 12-13

Keyboard Transmit Logic

12-29

DATA 5 L

DATA 4 L

BIT

1-7 L,

KEYBOARD STROBE

„_TL

KYBD FLG (1) L

INT RQST

PNSI L

SKIP L

DKRB L
77,

DATA 11-4 L

CO L, CI L

TP3.

Figure 12-14

Keyboard Transmit Logic Timing

The user initiates the keyboard sequence by pressing a key on the keyboard. The character information is placed on
the
the BIT 1-7 lines. After a period of time that allows the BIT lines to settle, the keyboard generates

KEYBOARD STROBE H signal. The trailing edge of this signal clocks the information into the 7-bit register and sets
logically connected to the interrupt system, as assumed, the KYBD FLG
the KYBD FLG flip-flop. If the VT8-E
is

L signal causes the INT/SKIP logic to assert the OMNIBUS INT RQST L signal. The program proceeds to an
routine
interrupt servicing routine to determine the identity of the requesting device. The PNSI instruction in the
(1)

interrupt.
causes the program to jump to a VT8-E routine that determines if the printer or keyboard requested the

Ultimately, the VT8-E keyboard routine executes the DKRB instruction.

When the DKRB instruction is decoded, the IOT Decoder logic generates the DKRB L signal and activates the
OMNIBUS CO and C1 lines. The DKRB L signal enables NOR gates E17C and E17D; the output signal from E17D
gates the information from the register outputs to

DATA lines 5-11, and also causes NAND gate E27 to assert the

DATA 4 L signal. The DATA lines are gated to the AC Register and the information is clocked into the register at
TP3 time. Also at TP3, the KYBD FLG flip-flop is cleared, readying the logic for a new data transfer.
INT/SKIP Logic -The INT/SKIP logic is shown in Figure 12-15. The PRNT FLG (1) L signal and the
KYBD FLG (1) L signal can cause program skips when tested by instructions PNSK and DKSK, respectively. The
12.4.1.4

signals

can also be tested by the PNSI instruction, provided the

ENA flip-flop, E37, has been set, logically

connecting the VT8-E to the interrupt system. When E37 is set, the PNSI L signal enables NAND gate E29, which, in

NAND gate E34, either the PRNT FLG (1) L signal or the KYBD FLG (1) L signal
Simultaneously, NAND gate E13 asserts the INT RQST L signal.

turn, enables

12-30

asserted.

INITIALIZE L

B DATA

L-

-0(D

E37
ENA

TP3-

|E33

|E|2

E30

PRIOTSL^
(PNSI)L <

F/F
C

EE9

E34^>

1
,

INITIALIZE H

E34

— SKIP L

E35 p

KYIOTSL(DKIN)

7E>
tEE>

INT
"RQST L

NOTELogic

P/O M8335 module.

Figure 12-15

Keyboard/Print Interrupt and Skip Logic

The ENA flip-flop is set by the OMNIBUS INIT signal for the PDP-8 family computers. To clear the flip-flop,
remove the VT8-E from the interrupt system, load AC1 1 with logic and then program the DKIN instruction. The
in AC1 1 keeps the DATA 1 1 L signal negated. Thus, the D input of E37 remains high. At TP3 time, NAND
logic
gate E22B provides a clock pulse for E37, clearing the flip-flop. E37 can be set at any time with the same instruction
merely by loading AC11 with logic 1.
12.4.2

Display Logic

Information displayed by the VT8-E is transferred by data breaks from the PDP-8/E memory. As with all data break
devices, the start of the data transfer is under program control. However, the VT8-E is a 1 -cycle data break device;
consequently, it needs only a starting memory address to carry out the complete data transfer. The starting address,
Register by a
i.e., the memory address of the first data word to be transferred to the VT8-E, is placed in the AC

program TAD instruction. Program IOT instructions gate this address onto the OMNIBUS DATA lines and cause it
to be loaded into a starting address register in the VT8-E (Figure 12-16). At the same time, the VT8-E Data Break
logic is readied for triggering.

When the CRT sweep is in a specified position, a synchronizing signal is generated by the VT8-E Timing logic. This
signal enables the

Data Break logic to request a data break and check priority.

no higher priority device has

requested a break at this time, the Data Break logic asserts a number of OMNIBUS control signals, enabling direct
communication between the interface and memory for one PDP-8/E timing cycle. At the same time, other Data

Break logic signals gate the starting address onto the OMNIBUS MA lines. During the data break timing cycle, the
data word in the addressed memory location is transferred on the MD lines and loaded into the interface Line Buffer
Register. At TP4 time of the timing cycle, the Data Break logic increments the address in the Address Counter. The

data word in this new address is transferred during the next data break timing cycle, which might occur immediately
after the first (priority is checked during TS4 of each data break cycle; a higher priority device can interrupt the

VT8-E data breaks).
After each transfer, the address

the Address Counter

incremented, and the data word in the new address is

loaded into the Line Buffer Register. This register holds 32 or 64 data words, depending on the mode (graphic or
alphanumeric) or the desired number of alphanumeric characters per line. The Data Break logic counts the number
of data breaks; when the specified number of data words has been loaded into the Line Buffer Register, the Data

Break logic ceases to request breaks.

12-31

ALPHA VID
BUFFER 8 DISPLAY

ROM CHAR
GEN LOGIC
I

MODE LOGIC

ALPHA VID
BUFFER CONT
LOGIC
IOT

DECODER
LOGIC

MAINTENANCE

INT/SKIP

IOT LOGIC

LOGIC

GRAPHIC VID
BUFFER LOGIC

MDO-11L(DATA)
^BREAK CONTROL SIGNALS
LINE BUFFER
REGISTER LOGIC

^EMAO-EL

GRAPHIC VID
BUFFER CONT
LOGIC

'
i

STARTING ADDRESS
REGISTER LOGIC
,

DATA 0-11 L

(STARTING ADDRESS)

LOAD/SHIFT

MAC 1(1)

REG CONT LOGIC
(GRAPHIC)
>

MY PRIORITY L

DATA BREAK
CONTROL LOGIC

PRIORITY
LOGIC
i

INT STROBE

CONT BRK
MAC
TP1

(0)^

DATA BREAK
COUNTING LOGIC
i

DPLA L
DPGO L

MAINT L
STARTING ADDRESS
MODE CONTROL LOGIC

MD1,2L,(E0S) MD5-11L(LN FEED)

LINE BUFFER

MAC 0(1)

LOAD/IN CREMENT

LOAD/SHIF T

ALPHA/GRAPH

DATA BREAK
HALT LOGIC

BRK SHIFT

DATA 0-11 L (PRIORI!rv)

Figure 12-16

Display Logic Block Diagram

LINE BUFFER
REG CONT LOGIC

(ALPHANUMERIC)
i

VIDEO

If the VT8-E logic has been programmed to display 32 alphanumeric characters per line; for example, each data
word in the Line Buffer Register contains: the 7-bit ASCII code representation of an alphanumeric character (bits
5—1 1 ); data that controls how the character is displayed (bits 3 and 4); and data that controls the visible field (bits 1

and 2). Because the VT8-E displays only a 64-character set, bits 6—11 of the Line Buffer Register contain sufficient
data to display all alphanumeric characters. Characters are formed on the CRT screen when the CRT video circuits
selectively intensify points within a 5 X 7 dot matrix.

The letter F is illustrated in Figure 12-17. Each horizontal

scan line corresponds to one row of the letter. As the sweep scans along a line, video signals selectively intensify
points as illustrated (5 video signals in

row 1 of the

letter F).

32 alphanumeric characters per line are to be

displayed, for example, row 1 of each character is swept out by the same scan line. The next scan line sweeps out

row 2 of all 32 characters, and so on until the 7th scan line sweeps out row 7 of the characters, completing the
character line.

•

8E-0626

Figure 12-17

Video Presentation for the Letter F

The video signals are generated, indirectly, by a ROM Character Generator. After the start of a horizontal scan line, a
6-bit ASCII character is shifted from the Line Buffer Register (at this time, the register is in the recirculating mode;
hence, an end-around shift is performed). The character addresses a ROM Character Generator location. This
location contains the video information for one row of the character. For example, assume that the letter F is the
first character to be displayed in a particular character line. The 6-bit ASCII representation of the letter F addresses
a particular ROM Character Generator location. The information in this location causes row 1 of the letter to be
painted during this scan line. The next character to be displayed is shifted from the Line Buffer Register and
addresses its unique ROM Character Generator location; the information in the location causes row 1 of this
character to be displayed just after character F. Row 1 of all 32 characters is displayed during this scan line.
After the start of the next horizontal scan line, the 6-bit ASCII representation of the letter F is again shifted from
the Line Buffer Register. Meanwhile, certain

ROM control signals have been asserted so that the addressed location

Row 2 of the letter F to be
Row 2 of all other characters is displayed during this scan line in similar fashion.

differs from that of the first scan line. This location contains information that causes

painted during this scan

line.

Consequently, the Line Buffer Register is shifted 32 times during each scan line; after 7 end-around shifts of the
register, a character line has been displayed.

Each character line comprises ten scan lines, rather than the seven just described. The three additional lines occur at
the beginning of the character line. During the first two scan lines, the Line Buffer Register is loaded from the

OMNIBUS MD lines; during the third scan line, a blank ROM location is addressed. Figure 12-18 represents two
character lines as they would appear on the CRT screen. Character line spacing (43% of character height) is provided
by the three blank scan lines.
If the

scan

VT8-E has been programmed for a graphic display, one line of graphic data is displayed during each horizontal
A line of graphic data is represented by 16 12-bit data words; each bit of a data word represents a dot or a

line.

12-33

space on the CRT screen. The Line Buffer Register is loaded with two lines of graphic data by 32 data breaks. As the

sweep scans along a line, video signals selectively intensify points to paint the graphic symbol. Although 16 12-bit
data words contain 192 bits, only 189 points can be painted by each scan.

10 SCAN

•

LINES PER

•
•
«

CHARACTER
LINE

•

—

•-•
•

•-•-•
•
«
•
•

—

*
•
•

•-•—

•

LINE
ME BUFFER >
IS LOA[
OADED FOR J
NEXT
<T ROW OF \

•

•
•

•

» • • • »

•
•

•

•
•

•
*

»
•
•
•
•-•
»-•

_»

•

•
•

•

» » » • •
•
•

•

•
•
•

•

» » » « «

•
•
•
•

•

m
•
» • • • •
•
•
•
•

•
•

CHARACTERS

•-•-•

—
—
—
—
—

•-•-«

» • » »

•-•-•

•
•
•

•

—
—
—

•
•
•

•
» » » »

« » > «

•

•
•

•

Figure 12-18

•-•-•

• • • •

•
•
•

•
•

•-•-•

• • » m

» m « m
•
•

•

•
• • • •

•

•——

•

•
•

•

• m » m
•

•

• • • •

• • m •

•

•
•
•

•

•
•

m » »\
A
]
1

•
• • • •

• • • •

Two Alphanumeric Characters Displayed on the CRT

VT8-E Timing — The VT8-E Timing logic generates signals that sync the Display logic and the CRT sweep
circuits. Figure 12-19 illustrates the CRT vertical and horizontal sweep signals and the VT8-E sync signals.
12.4.2.1

For 60 Hz operation, the VT8-E timing generates a V SYNC L signal every 16.7 ms. This sync signal causes a vertical
retrace,

which

carried out in approximately

20 scan

lines.

A VZONE flip-flop in the timing controls the

displayable area in the vertical direction. When the flip-flop is set, the VZONE (1) signal enables a vertical display of

200 scan lines (the horizontal sweep rate is set at 15.6 kHz; a total of 60 scan lines is made non-displayable to
remove distortion-prone areas on the CRT screen).
The timing generates an HSYNC signal every 64.1 /xs. A HZONE flip-flop in the timing controls the displayable area
in

the horizontal direction. When the flip-flop is set, the HZONE (1) signal enables graphic or alphanumeric video to

be painted in the distortion-free area of the screen (exceptions to this statement are pointed out in the detailed logic
discussion).

12-34

-16.7ms-

V SYNC L(f = 60Hz)

VERT SWP

V ZONE (1)

n_r
.

»«

NON- DISPLAYED
SCAN LINES

200 SCAN LINES
-AT HORIZ. SWP RATE
OF 15.6KHZ

-H 20

NON -DISPLAYED
SCAN LINES
-64. Vs-

H SYNC

_J1

_n_

HOR IZ SWP(f=15.6KHz) *^V_

H ZONE (1)

-I-

90R18

34.6VS (GRAPHIC)

NON-DISPLAYED

ORIS

NON-DISPLAYED
CHARACTERS

CHARACTERS
41.02/iS

"(ALPHANUMERIC)"

Figure 12-19

Sweep and Sync Signals

The VT8-E timing is such that either 50 or 100 alphanumeric characters could be displayed between HSYNC signals.
The HZONE (1) signal reduces the number of characters to either 32 or 64, respectively (an equal number of
characters

removed on both sides of the screen). Note that the HZONE (1) signal is of shorter duration for the

graphic display. This

is explained as follows. Clock pulses of the same basic frequency are used to shift
the
Alphanumeric Video Buffer Register and the Graphic Video Buffer Register. Seven shift signals are needed to display

the rows of the 5 X 7 alphanumeric character matrix (five signals intensify the scan, two signals provide spacing

between each character). Thus, 7 X 32, or 224 shift pulses are needed for an entire character line. An entire graphic
line

needs only 192 shift pulses. Consequently, it seems that the HZONE (1) signal should be reduced by an amount

192 shift pulses to be generated (if the display area is not shortened, an improper display will result).
This would mean reducing the graphic displayable area by an amount equal to 32 shift pulses. However, this is not a
that allows

multiple of seven, which

it must be to enable correct alphanumeric display. The closest number that is a multiple of
7 is 35. Thus, the horizontal zone for graphics allows only 189 shift pulses to be produced, cutting off the last 3 data

in each scan line (note that 28 could not be used because then too many graphic shift pulses
would be
produced). The pulses are derived from a 5.46 MHz clock (t = 183.15 ns). Therefore, 189 shift pulses require an
HZONE (1 ) signal of only 34.61 vs.

bits

12.4.2.2

VT8-E Timing Logic - The VT8-E Timing logic generates the CRT sync pulses and the interface control

signals. All

timing and control signals are derived from a crystal-controlled transistor oscillator that produces pulses

at a frequency of

21.84 MHz. These pulses are applied to a Clock Pulse Generator, shown in Figure 12-20. The
generator divides the basic frequency by 2 and 4, producing well-shaped clock pulses of 10.92 MHz and 5.46 MHz.

Two test points are available which allow the oscillator clock to be inhibited and external clocks injected to drive the
timing chain.

12-35

+ 5V

-e>

CNT
UP

>64
TP-

CRYSTAL

c£

CLOCK
F = 21. 84MHz

IN IT + REM V SYNC-

TRUTH TABLE
(Each Fllp-Flop)

*n+)

NOTES:
1. Logic is

*n +

BIT TIME
l

P/O M8336 Module

64 Alphanumeric Character/Line
Connect jumper "32" for 32 Alphanumeric Character/Line
3. DEC 7473 J-K F/F Truth Table
2. Connect jumper"64"for

BEFORE CLOCK PULSE.

BIT TIME AFTER CLOCK PULSE.

Figure 12-20

Clock Pulse Generator

The clock pulses selected are applied to a chain of DEC 74161 4-Bit Counters that counts down the pulse frequency
to 3.75 Hz (for 60 Hz operation). Selected outputs of the timing chain are gated to produce sync pulses and control
signals.

A logic block representation of the DEC 74161 4-Bit Counter Integrated Circuit (IC) is shown in Figure 12-21. This
IC, E17, is the first one in the timing chain. Because it is a 4-bit counter, E17 can produce one pulse at its CARRY
output for each 16 pulses at its COUNT UP input. However, because the IC can be preset to any count, it can
produce a CARRY output for any number of input pulses less than 16. The preset inputs are labeled A through D in
Figure 12-21 {A is the LSB). They are wired so that E17 is preset with a count of 1001 2 whenever a signal is applied

to the LOAD input and a clock pulse occurs. The CARRY signal is generated when the count is in the 1 1 1

and

ENP and ENT are true. A Load signal

generated by the OR gate and E17 is preset to 1001 2

2 state

Seven more

CARRY signal and, again, the counter is preset. Thus, the counter divides
by seven. The counter can also be preset by a REMOTE V SYNC IN L signal, enabling the timing to be controlled by
some external device. The output of each bit, designated QA through QD (QA the LSB), is available for gating to
pulses at the clock input produce another

generate the sync and control signals.

REMOTE
VSYNC H

T~l
«>64

CARRY

CL0CK
32

ENABLE P
+

E17+7
74193

LOAD

3V—L ENABLE T QA

Figure 12-21

4-Bit Counter

12-36

Figure 12-22 shows the entire chain of 74161 ICs. Each IC in the figure is represented in shorthand form:

i.e.,

the

PRESET inputs is not shown, the LOAD input circuits are not shown, and the destination of each

wiring of the

output is now shown (only those output bits that are used are indicated on the ICs). The binary designations above
each IC block represent the way the preset inputs are wired. For example, E16 is wired thus:
tied to +3V; PRESET input C is grounded; PRESET inputs B and

count of 101

F = 10.92MHz

PRESET input D is

A are tied to +3V. Therefore, E16 is preset with a

and divides by 5.

«(1001)2

*(1011)2

A64CH

•COUNTER IS PRESET TO THIS BINARY VALUE

IC OUTPUT FREQUENCY
IC

NOTE:
Logic

P/0

M8336 Module

FREQ. OUTPUT

60Hz LINE

EI7

780KHz(32!
1560KHz(64)

El 6

156KHZ

El 8

15.6KHZ

50Hz LINE

SAME
AS

60Hz

E19 1.56KHZ

E8 780HZ

Figure 12-22

E9 60Hz

50Hz

E42 3.75Hz

3.125Hz

VT8-E Timing Chain

Each IC has a NOR gate at its LOAD input, exactly as shown in Figure 12-21; this gate ORs the CARRY output
with REMOTE V SYNC and INIT(E17, E12, E16), or with REMOTE V SYNC and 50 Hz RESET (E18, E19, E8,
E9>. The bit output destinations are shown, in part, only for ICs E 19, E8, and E9.

The table in Figure 12-22 indicates the frequency of the CARRY output pulses of each IC. The output frequency
from E17 differs for 32 character/line and 64 character/line operation. The bit output signals from E1 7 determine
the alphanumeric character rate, the rate at which characters are painted on the CRT screen. Thus, the rate is twice
as

fast for

64 character/line operation. E12 divides by two; therefore, the input of E16 is the same for both

character rates.

12-37

When a 50 Hz line is used, the timing is modified in the last three ICs. For 60 Hz operation, E9 is preset with a count
of 001

and its CARRY output provides the LOAD input for E9. E8 and E9, together, divide the output of E19 by

26, producing a

CARRY output pulse from E9 at a frequency of 60 Hz. This output

is gated

elsewhere in the logic

V SYNC L signal that causes a CRT vertical retrace. For 50 Hz operation, the 50 Hz jumpers are
connected, and E9 is preset with a count of OOIO2 Furthermore, the LOAD input of E9 is controlled by REMOTE
V SYNC IN or 50 Hz RESET H. When E9 attains a count of 001 2 and both E19-D and E8-A are high, E9 is preset
and a V SYNC pulse is generated. E8 and E9, together, divide the output of E19 by 31.2, producing pulses having a

to generate the

frequency of 50 Hz. The table shows the output of E9 as 50 Hz (the output is not actually from E9, as for 60 Hz
operation, but it is convenient to think of it as so). As for 60 Hz operation, the output is gated to generate the V

SYNC L signal.

Note that the REMOTE V SYNC IN or 50 Hz RESET line is activated when E9 is preset; thus, ICs E18, E19, E8,

and E9 are preset at the moment of vertical retrace. This active step is not necessary during 60 Hz operation because
all

ICs automatically overflow to the preset state.

Figure 12-23 shows the logic that generates the horizontal and vertical sync signals, while Figure 12-24 shows the

HZONE and VZONE flip-flops and those signals that control the two flip-flops. The timing diagram in Figure 12-25
shows the line timing for both alphanumeric and graphic display. Two hundred of the HZONE (1) signals are
generated for each VZONE signal, as shown in Figure 12-19.

+ 5V

n
+ 5V
E16 CARRY'CLK
E18-A
E18-D

J^C

E46B
74123
500ns

E18-B

CLEAR

E18-C

~T~
+ 3V

-H SYNC

+ 5V

CLK

REMOTE VSYNC
+ 50HZ RESET
E9 CARRY

E46A
741 23
.
_J\ >124*is

e0Hz
o

50 Hz

CLEAR

+ 3V
NOTE'
Logic

P/O M8336 module

Figure 12-23

Horizontal and Vertical Sync Circuits

12-38

+ 5V

SYNC
L

V SYNC

D—^D^H ^EI6-B

EI6-A

EI8-B-

•

H ZONE (

CH>

EI6 ENABLE T

CLK

EI8-A

^3°^H

EI8-B

EI8-C

EI8-B

EI8-C

FOR GRAPHIC /SELECT A
LO FOR ALPHANUMERIC/
SELECT B

E9-B—

r- E9-C

-VZONE(I)

EI9
EI9

HZONE

J
'

(1)

ZONE

EI9-D

3DH

=^77)J
E9-D

Figure 12-24

12.4.2.3

Horizontal and Vertical Zone Flip-Flops

Starting Address Register Logic - The Starting Address Register logic is shown in Figure 12-26. The logic

includes two Starting Address Registers: one is a 12-bit register comprised of two DEC 74174 ICs (hex flip-flop);
the other uses three bits of a DEC 74175 IC (quad flip-flop). The Address Counter is comprised of four DEC 74193
ICs (4-bit up-counters) connected in series and is preset from the Buffer Registers.

The control signals that load and clock the Starting Address Registers and the Address Counter are generated by the
Starting Address Control logic, shown in Figure 12-27. When the program IOT instruction DPLA is issued, the 12-bit
starting address

placed on the DATA lines. The DPLA L signal causes both the DATA EN A L and DATA EN B L

signals to be asserted.

The starting address is gated through the NAND gates to the DEC 74174 inputs and loaded

into the buffer at TP3 time by the LD ST

ADD signal.

The extended field must also be identified by the EMA bits. The extended field address bits are placed on lines

DATA 6, 7, and 8 by the DPGO IOT instruction. The DPGO L signal causes the DATA EN signals to be asserted,
DEC 74175 inputs. At TP3 time the XST ADD REG loaded by the LD XST
ADD signal (DPGO).

gating the extended address to the

12-39

E16 CLK UP
780 KHz

iiiiimmiiiiiiiiiiiiiiiiimiiiim

(32 CH/LINE)

E16-A

liinjii^viJirinriJiniinnnjinnr

E16-B

——
u

E16-C

E16 CARRY
156 KHz

E18-A

E18-B

E18-C

E18-D

E18-CARRY
(LINE COUNT)

HSYNC
15.6 KHz

H ZONEd)

GRAPHIC

—'

ALPHANUMERIC

Figure 1 2-25

Alphanumeric and Graphic Line Timing

The DPGO L signal also clears the MAINT/GO flip-flop (Figure 12-27) at TP3 time, negating the MAINT L signal.
This negated signal enables a vertical sweep synchronizing signal, E46(Q), to assert the LD ADD CNTR L signal. This
signal loads the starting address (including the extended address) into the 15-bit Address Counter.

At approximately the same time that the Address Counter is loaded, the Data Break Counting logic is readied for
triggering. When the sweep is in the specified position, the

Control logic to request a data break.

COUNTING signal is generated, enabling the Data Break

the VT8-E has highest priority, the MACO and MAC1 flip-flops in the Data

Break Control logic are set. The MAC0(1) and MAC10) signals gate the 15-bit starting address from the Starting
Address Register outputs onto the MAO-11 and EMAO-2 lines. At TP1 of the data break timing cycle, the MAC2
flip-flop in the Data Break Control logic is set. The MAC10) signal then enables the Starting Address Control logic
to assert the CLK

ADD CNTR signal at TP4 time of the data break timing cycle. Thus, the address in the Starting

Address Register is counted up by one. The next data break timing cycle transfers the data word in the new address
to the VT8-E.

12.4.2.4

Data Break Counting Logic — The Data Break Counting logic is shown in Figure 12-28. This logic
COUNTING signal that enables the Data Break Control logic to request data breaks. When the

generates the

PRESET BRK signal is generated, flip-flop E43A is set, asserting the COUNTING signal. The COUNTING signal
enables the NBR flip-flop in the Data Break Control logic to be set at INT STROBE time. If the VT8-E has highest
gate E42 (Figure 12-28) to
priority, data breaks begin. Each TP1 signal of a data break timing cycle causes

NAND

assert the

COUNT BRK signal. This signal

counted by the 4-bit up-counter, E53. When the correct number of data

breaks has been performed, flip-flop E43A is cleared via NOR gate E33 and data breaks cease.

12-40

CLK ADO CNTR-

P/0 M8337
UP COUNT
°A
Qa

=3E>

DATA11 L-

DATA10 L-

1 24 "N)P10
o, o~y-q
J
DATA ENBL-f
DATA 9 L

°B

op, VJ
P9

MAR 10

35"

MA10 L

74193

4-BIT
UP CNTR

E16

MA11 L

°c
E15

o-J

MAR 9

°C

MACO (1)

74174

HEX

DATA 8 L-

F/F Q D

MAR 8

Qd
load carry

UP COUNT

DATA 7 LDA

SZV

MA9 L

£>

MA8 L

MAR 7

MA7 L

DATA 6 L-

:E>

MAR 6

CLOCK

MA6 L

E12
74193

DATA

5 L-

°C

DATA 4 L-

qd
Dd
load carry

74174

DATA 3 L

UP COUNT

•

DATA O L

LD ST ADD

MAR 3

°A

DATA 2 L-

DATA

MAR 2

O
O

°D

°d

°E

Dd
°d
load c arry

CLOCK

MA3 L
MA2 L

E8
74 193

— MA4

°B

MA5 L

MAR

-MAO L

MAC1 (1)

UP COUNT

H A E3 °A
D

°a

74175
DB

EMAR 2

QUAD
F/F

E4
74193

EMAR

Do
LOAD

OD
CLOCK

EMAR

-o

LD X ST ADDLD ADD CNTR LNOTE^
Logic

P/0

M8335 unless noted.

Figure 12-26

Starting Address Register Logic

12-41

b— EMA2 L
EMA1 L

-jty EMAO

+ 5V
DPLA L

T=tB>r{Hi>^7^^

DATA EN B L

DATA EN A L

E45>0-

LD ST ADD

TP3

TE>'

W8^>^>

DPGO L

LD XST ADD

INITIALIZE

+3V-

E56
MAI NT/

GO
MAINT L

i>
-JE)

DATA ,0L

GRAPH/ALPHAO)

E55
GRAPH/
ALPHA
C
O

GRAPH L

E46 (Q)
(V SYNC TIME)

E44 )0— LD ADD CNTR L

P/O M8337
TP4
I

MAC2(1)

CLK ADD CNTR
I

NOTELogic

P/0

M8336 module unless noted.

Figure 12-27

Starting Address Register Control Logic

12-42

V SYNC L

GRAPH/ALPHA(1)H.
(LO FOR ALPHANUMERIC SELECT B)

+ 3V

TP1

CLEAR

E53-M6
DEC 74193

COUNT UP

MAC 1(0)
COUNT BRK

1. Logic is P/0

—

NOTES:

M8337 Module, unless noted.

p/o

|_j___M8335J

2.W4 connected-32 characters/line

W5 connected'-64 characters/line

INITIALIZE

8E-0637

Figure 12-28

Data Break Control Logic

If the logic has been programmed for an alphanumeric display (assume 32 characters/line), 32 data words must be
loaded into the Line Buffer Register during two scan lines of the character row. During each of the eight remaining

scan lines, the Line Buffer Register is recirculated. Thus, new information is loaded once every ten scan lines and the

PRESET BRK signal must be generated only once every ten scan lines.
Note that the logic within the dashed line in Figure 12-28 generates the PRESET BRK signal. The VSYNC L signal

GO AFTER VSYNC signal (the
MAINT L signal is negated by the Starting Address Control logic when a DPGO instruction is issued). VSYNC L also
clears the 4-bit up-counter and the two J-K flip-flops. When the VZONE flip-flop is set, NAND gate E7 is enabled.
Each E19 CARRY signal that occurs causes PRESET BRK to be generated. Because E19 CARRY occurs once every
prepares this logic for triggering by setting flip-flop E43B, thereby asserting the

ten scan lines, the Line Buffer Register is loaded once every ten scan lines, as required.

Figure 12-29 illustrates the timing of the counting network for an alphanumeric display of 32 characters/line. This

timing applies to a graphic display, as well, although the GRAPH L signal would be asserted for such a display. If the
logic has

been programmed for a graphic display, the PRESET BRK signal must be generated differently. Sixteen

data words are needed to display one line of graphic data. Thus, the Line Buffer Register can hold two lines of

graphic data. Since a line of graphic data is displayed by one scan line, a PRESET BRK signal is required once every

two scan lines. The logic in Figure 12-30 is used to generate the Graphic mode PRESET BRK signal. It is similar to

PRESET BRK logic in Figure 12-28. The VSYNC L signal is used in the same way and the data breaks are
counted by the counting logic in the same way. The LN CNT signal occurs at the end of each scan line, but the

the

E19-A signal is high for every other scan line. Consequently, the graphic PRESET BRK occurs once every two scan
lines.

12-43

V SYNC t

PRESET BRK

COUNTING

E488(0)

E48A(0)

TP1

(WHEN MAC (1)IS SET)

GRAPH

E33A

"1
Figure 12-29

Data Break Counting for 32 Characters/Line

E9-C
GRAPHIC
PRESET
fn=An

NOTE:
Logic

(HI
is

FOR GRAPHIC SELECT A)

P/O M8336 Module unless noted

Figure 12-30

PRESET BRK Generation Graphic Mode

12.4.2.5 Data Break Control Logic -The Data Break Control logic is shown in Figure 12-31. When the
COUNTING signal is asserted by the Data Break Counting logic, NAND gate E52 is enabled. {MAINT L is negated
by the DPGO instruction and HALT BRK L is asserted only for line-feed or end-of -screen.) The NBR flip-flop is set
at INT STROBE time, asserting the NBR (1) signal. This signal asserts OMNIBUS signals CPMA DISABLE L and
BRK IN PROG L and causes the VT8-E priority to be placed on the DATA lines during TS4. CPMA DISABLE L
causes the CPU CPMA Register to be disconnected from the OMNIBUS MA lines, while BRK IN PROG L ensures
that only data break devices place priority information on the DATA lines during TS4.

12-44

NBR(1)

I0T3MAINT L
COUNTING
HALT BRK L
MAINT L

CPMA DISABLE L
1

E52

INT STROBE

MY PRIORITY L

NOTE:
Logic is P/O M8337 Module unless noted

Figure 12-31

If the

Data Break Control Logic

VT8- E has highest priority, MY PRIORITY L is asserted by the Priority logic (Figure 12-33). This signal is

NANDed with the 0-output of the NBR flip-flop to produce a high logic level at the D-input of both the MACO and
MAC1 flip-flops; the flip-flops are set at TP4 time via NAND gate E28. The MAC0(1) signal asserts MS, IR DISABLE
L, BREAK CYCLE L, and MD Dl R L, and enables the MAC2 flip-flop to be set at TP1 time of the data break cycle,
thereby asserting MALC L. These OMNIBUS signals complete the CPU takeover process. MS, R DISABLE L forces
the CPU to enter the Direct Memory Access (DMA) state and disables the CPU IR Register. The MALC L signal
prevents the CPMA Register from being clocked during the data break operation, while the BRK CYCLE L signal is
I

applied to the programmer's console and can be monitored on the display panel.

The MD DIR L signal is asserted so that the data word transferred during the data break timing cycle is rewritten in
the memory location during the write half of the memory timing cycle.

The MAC1(0) signal is applied to NOR gate E42 to ensure that MACO and MAC1 can be cleared by TP4 whenever

NBR is cleared at INT STROBE time. The MAC1 and MAC2 outputs are used as gating signals elsewhere in the
Display logic.

12-45

LF CODE L

BMD 10

BMD 9

BMD 8
BMD 11
BMD 7
BMD 6
BMD 5

<»

MD1 L

MD2 L
MAC 2(0)
to

TRUTH TABLE
J-K FLIP-FLOP
Tn
J

Tn + 1

Q
On

1
1

Tn- bit lime before clock
Tn*1-bit time after clock

NOTE:
Logic is P/0 M8337 Module

Figure 12-32

Data Break Halt, Line Feed/EOS Logic

Data

12.4.2.6

Break

Halt,

Line

Feed,

and

End-of-Screen

Logic - The

Data

Break

Halt,

Line

Feed, and

End-of-Screen logic is shown in Figure 12-32. This logic is used to clear the NBR flip-flop and stop Single Cycle Data
Breaks as follows:

the line feed ASCII code (012) is detected on the

MD lines, E47A sets. This clears NBR

if the

counter

has not overflowed and the Maintenance mode is not enabled.

If the Character Counter overflows

If the

when 64 or 32 characters are transferred, counting is negated.

EOS code is detected (Figure 12-7) and EOS CODE L is asserted.

V SYNC L is asserted at the end of the vertical scan.

If NBR is cleared by EOS CODE or LF CODE before the Character Counters have counted 64 or 32 characters, FIN
SHIFT (E51) sets. This allows the counters to continue counting until they overflow (read all 0s) so that they will
contain a
count when the next data break is initiated. FIN SHIFT also allows BRK SHIFTS to be generated in
order to shift the line buffer data into the correct position. FIN SHIFT is clocked at each TP4 time and will clear at

the first TP4 time after COUNTING is negated.

IOT3 • MAIN L is used to set NBR to cause one Single Cycle Data Break if the DPMB Maintenance instruction is
executed by the program.

Priority Logic

12.4.2.7

— The Priority logic

that connect to the OMNIBUS. Priority
sets the

shown in Figure 12-33. Similar logic is contained on all interfaces

checked during TS4 immediately following the INT STROBE signal that

NBR flip-flop.

The VT8-E can have priority 10, 1 1, or 12. The device having the lowest priority (12) asserts the DATA 1 1 L signal
is assigned. This priority causes the VT8-E to assert the DATA 10 L signal
during TS4 L (jumper W2 in the Data Break Control logic is connected). Jumpers P10 and P9'must be connected in
during TS4. Assume that priority 11

the Priority logic. Because the DATA EN B L signal is asserted when NBR(1)

high, any data break device with a

higher priority can enable one of the NAND gates (the DATA EN A L signal is high throughout the priority check).

Thus, MY PRIORITY L is not asserted and VT8-E data breaks do not begin.

VT8-E is assigned priority 10, jumpers P10 and P9 are connected. Higher priority devices can assert any of
through 8, thereby preventing the VT8-E from beginning data breaks. However, any device with a
lower priority, 11 or 12, must wait until the VT8-E relinquishes control of the CPU.
If

the

DATA lines

12.4.2.8

Line Buffer Register and Control Signal Logic — The Line Buffer Register logic is shown in Figure 12-34.

The register comprises four DEC 2518 ICs (hex 32-bit Shift Registers) and is loaded from the MD lines during each
data break cycle

[MAC2 (0) is asserted low] by control signals generated in the Line Buffer Register Control logic

(Figures 12-35 and 12-36).

32 alphanumeric characters are to be displayed. Component Registers B1 and B2 are used as a 12 X 32-bit Shift
Register that is loaded with the 32 ASCII-coded characters. If 64 characters must be displayed, the A1 and A2

Component Registers are also used as a 12 X 32-bit Shift Register. However, the two 12 X 32-bit registers are loaded
alternately, word by word from the MD lines. Consequently, they function together as a 12 X 64-bit Shift Register.
If graphic data is displayed, the A and B Registers operate as two independent 12 X 32-bit Shift Registers. While one
is displaying two scan lines of data, the other is refreshing for the next two scan lines.

When the LD B L signal, for example, is asserted, the 12 X 32-bit B Register can be loaded from the MD lines. Data
gated to the LOAD inputs is shifted by the CLK B signal. When the LD B L signal is negated, the LOAD inputs are
disabled; the CLK B signal produces an end-around shift of the data that has been loaded.

12-47

DATA 11 L
DATA EN A L

DATA 10 L

DATA 9 L

DATA 8 L

DATA 7 L

DATA 6 L

DATA 5 L

DATA 4 L

Hi^-o—H>-

DATA 3 L

MY PRIORITY L

DATA 2 L

DATA 1 L

DATA

NOTE:
Logic

P/0

M8335 module

unless noted.

P/0 M8336
NRB (1)

|OH>td-M

DATA EN B L

TO OBTAIN

CONNECT JUMPER

PRIORITY 12
PRIORITY 11

p 9, p 10'

PRIORITY 10

Figure 12-33

p 9', p 10
p9, p 10

Priority Logic

Three DEC 74157 ICs (quad multiplexers) are included in the Line Buffer Register logic. The READ SELECT signal
outputs. The outputs
inputs to be gated to the f
controls the multiplexers, causing either the A
inputs or the B
n
n
n
are transferred to the Video Buffer logic, alphanumeric or graphic, and converted to serial video information.

Figure 12-37 shows a timing diagram that illustrates how the Line Buffer Register and the multiplexer are controlled
when 32 alphanumeric characters are to be displayed. The timing shown is relative; pulse durations, gate widths, etc.,
may or may not be actual.

12-48

[p/o
1

MD11 L-

M8335

7=33

MD10 L-

M09 LMD8 L-

MD7LMD6 L-

:=Ol

LOAD

INPUTS
A1
HEX.32-BIT
SHIFT

;^Q
:=o
;^Q

E16

A
Al

A?tQUAD Fi
A3
MULTIPLEXER
B

74157
F2

B,
B2

F3
B3
SELECT

LOAD
INPUTS

A
Bl

2518

*3 E15

MD5 L-

MD4 L-

;^Q
;^0

74157

E7
B2
B3

SELECT

MD3 L-

MD2 LMD1 L-

MDOL-

IH2J-

LOAD
INPUTS

3333MD

A2
2518
4

ENABLE L

A3 E14

74157

F r "1
H>k>J|
5V

MAC 2
(0)

P/0

E6
B2

M 8335

SELECT

LOAD
INPUTS

B2
2518

NOTE:

LD AL-

Logic is P/O M8337 Module unless Noted

LDBLCLK ACLK B-

READ
SELECT"

Figure 12-34

Line Buffer Register Logic

12-49

The period of time represented as t x is that period during which 32 data breaks are being performed (remember that
two scan lines are set aside for this purpose). During ti the Line Buffer Register must be loaded from the MD lines.
The Line Buffer Register Control logic (Figure 12-35) asserts the LD B L signal (the signal E19-D is low throughout
data word to be gated to the B Register
ti, keeping the VIS ZONE L signal high). Each data break cycle causes a

LOAD inputs. The BRK SHIFT signal that occurs during TS3 L of the break cycle gated through NAND gate
always cleared during a 32 character operation. This causes a CLK B signal to
E37A, since the ALPHA CLK ALT
be produced. When 32 data words have been loaded into the register, the COUNTING signal goes low and data
breaks cease (COUNTING goes low atTP1 of the break cycle, while BRK SHIFT is asserted during TS3 L).
is

VIS

ZONE (I)-

ZONE L

ZEH-py

V ZONE (1)-

E19-DMAINT/GOCD-

E33
82S6

E32

CLK-

E17

SHIFT LINE BUFFER

J Es0 )

Fn = Bn

INIT

L—«

e—

Fn 3

VSYNC L
B 1

E28
8266

READ SELECT

M8336 Module

Logic

Connect jumper '32' for 32 Char/Line

Connect jumper '64' for 64 Char/Line

E38B

F l

NOTE:
P/O

CLK AL

-LD B L

E38A

E22

OCCUR BETWEEN EACH E17
CARRY IN VIS ZONE)

3— LD AL

-o-

BRK

(2,3, OR 4 DECODED BY

SHIFT

*3
D

MAINT
GO (1)H

"(LO SELECTS A)

A3
B3

CLK B L

T"
64

GRAPH/ALPHA (I) H
(LO FOR ALPHANUMERIC)
_

•-a

Figure 12-35

Line Buffer Register Control Logic

Throughout each of the next eight scan lines, the Line Buffer Register must be shifted end-around. Period t 2
represents the third scan line and the beginning of the fourth. The VIS ZONE L signal is asserted when HZONEO)
goes high. The LD B L signal is negated, placing the register in the recirculating mode. During the time that VIS
ZONE L is low, the VT8-E timing generates 32 SHIFT LINE BUFFER signals. These signals enable NAND gate
E37A, thereby generating the CLK B signal. The register is shifted end-around by 32 CLK B signals. (Note that 31
CLK B signals are sufficient to shift all 32 characters through the multiplexer, but 32 are needed for the
Each time a character is placed on the register outputs, the multiplexer gates it to the ROM Character
logic (only the 6-bit ASCII code, bits 6-11, is gated to the ROM). There it is converted to serial video information

recirculation.)

for display.

12-50

V SYNC L

Fn=An

PRESET BRK

-C

E32
GRAPH
LOAD
ALTA/B

LD A L

E33
8266

B,1

LD B L

O B2
+ 3V

N^_CLK A L

-C*

-O A 3

E18-CARRY

T
Fn= An

B
B

E28

A 2 8266 p
B2

-0 A*

READ SELECT
(LO SELECTS A)
CLK B L

-t>

*3 7

GRAPH/ALPHAIMH
(

FOR GRAPHIC)

(PIN 9 HI :Fn = An)
(PIN 9 LO'Fn = Bn)

NOTE:
Logic is P/O

M8336 Module

Figure 12-36

Line Buffer Register

The same operation is performed during each succeeding scan line. At the end of the tenth scan line, the character
line has been displayed. Another PRESET BRK signal is generated and 32 more characters are loaded into the Line
Buffer Register. Note that as these next 32 characters are shifted into the register, the 32 displayed by the
just-completed character line are shifted out. Because video is not enabled unless VIS ZONE L is low, there is no
danger of these earlier characters being displayed again.
Figure 12-38 shows a timing diagram that illustrates how the Line Buffer Register and the multiplexer are controlled
lines. Both the A and B Registers are used, providing 64
when 64 alphanumeric characters are loaded from the

bits of storage space. As the timing diagram illustrates, the A and B Registers are loaded alternately so that each
contains 32 characters when 64 data breaks have been completed. The registers are alternately recirculated during

each succeeding scan line (this timing is not shown, but is similar to that of Figure 12-37); when the characters have
been displayed, 64 new characters are shifted into the register.
Figure 12-36 shows the logic that controls the Line Buffer Register and the multiplexer during a graphic display.
Figure 12-39 shows a timing diagram that illustrates how the graphic data is transferred through the Line Buffer

Read Select changes every Graphic PRESET which corresponds to every other scan line within the
When displaying Reg A, CLK A L is generated once for every 12 graphic dot positions that are
displayed. This shifts a new word to the output of the Shift Register. The word is then loaded into the Video Buffer
Register logic.

visible zone.

after the 12 bits of the previous word have been displayed.

Both the A and B Registers are used when graphic data is displayed. One register is loaded from the MD lines with 32
data words; simultaneously, the information in the other register is displayed.

12-51

PRESET BRK

_TL

-tf-

-ff-

"L_

-ff-

juuuuuuuinn.

-ff-

COUNTING

BRK SHIFT
SHIFT LINE

BUFFER

juuiniuuuinruuL

-ff-

JUUUUUUUUU1

ALPHA CLK ALT
A/B (1)

READ A/B (1)

READ SELECT

-ff-

-rff-

-ff-

SELECT B
-*f-

LD B L

RECIRCULATEB

LOAD 8

-ff-

CLK B

nnnnnnnnn n

nnnnnnnnnnn
-ff~

-ff-

H ZONE (t)

-ffVIS

ZONE L

-ff-

Figure 12-37

Line Buffer Timing for 32 Character Line

-ffV SYNC L

PRESET BRK

BRK SHIFT

r^% j
i

-ff-

juinnnniuruuuuL

ALT

e ad a/b (

-ff-

COUNT ;ng

LTLTLa

Jim

uijiruji_n_r

SELECT A

READ SELECT 1

/ RaJb] fl T1 fl

LD A L.LD B L

l"1

-Tf-

^ __[Ul_fUl>JUL
JUULJUUL
A

CLKB

Figure 12-38

RECIRCULATE B

ff-

-ff-

CLK A

Line Buffer Timing for 64 Character Line

12-52

JUUUUUUUUIJI

tl
t =

128.2ps

2SCAN LINES

PRESET BRK

T"|

GRAPH LOAD ALT A/B (1)

LD B L

BRK SHIFT

RECIRCULATE A

RECIRCULATE B

LOAD B

32 PULSES

32
ft

lllilllll

UULJll

455KHZ
PULSES

OIL

32 PULSES

CLK A

READ SELECT
AL/B H

HZONEC1)

V ZONE (t)
16

455KHz
PULSES

32 PULSES

iliiiiiiil

Figure 12-39

Line Buffer Timing

ROM Character Generator Logic -The ROM Character Generator logic

12.4.2.9

shown

Figure 12-40.

Included in the figure is a representation of the alphanumeric Video Buffer Register. The major components of the
character generator are three 23-XXA2 1024-bit read-only memories; each
locations.

A functional logic diagram of 23-XXA2

organized to provide 256 4-bit word

shown in Figure 12-41.

ASCII-coded characters are gated from the Line Buffer Register to each ROM on the six lines designated BIT 6—11.
The five most significant bits of the character, bits 6-10, are applied to a 1-of-32 decoder (Figure 12-41 ). The ROM
ROW CNT signals, generated in the VT8-E timing, are applied to 1-of-8 decoders. These three signals select one of
256 4-bit data words. The LSB of the ASCII character, bit 1 1, is used to gate the 4-bit word out of the ROM to the
Video Buffer Register, a DEC 7496 5-bit Shift Register. As Figure 12-40 shows, an odd ASCII character (bit 11 is
logic

1 )

causes the

ODD ROM outputs to be selected, while an even character causes the EVEN ROM to be selected.

The XTRA ROM provides the necessary fifth bit of the data word and is selected for both even and odd characters.

Remember that ten horizontal scan lines are required to display one character line. During the first two scans, the
characters are shifted into the Line Buffer Register. During each of the next eight scans, the Line Buffer Register is
recirculated. Bits 6—1 1 of a character are the same during each scan. The

ROM ROW CNT signals change during each

000 2 to 111 2 where ROM LS ROW CNT is the LSB. Consequently, eight
consecutive locations are selected for each ASCI character. The first location is blank, the next seven contain the
scan,

cycling through the counts

video information that is ultimately displayed.

12-53

ROM MS ROW CNT
ROM ROW CNT
ROM LS ROW CNT
BIT

CLK
LD
ALPHA
ALPHA
BUFFER VIO BUFFER

VI D

NOTE:
Logic is P/O

Figure 12-40

M8337

Module

ROM Character Generation Logic

Consider the ASCII code for the character H: 001 000 (10 8 ). Bits 6-10 (001 00) are applied to the 1-of-32 decoder
during each scan. During Scan Line 3, the ROM ROW CNT signals are low (000 2 ). The data in the addressed location
CNT signals are 001 2 The data in this
is 0000. and no video is displayed. During Scan Line 4, the ROM

ROW

1000 and is displayed as video. Table 12-8 relates the eight scan lines, the
representations, and the data in the addressed locations.
location

ROM ROW CNT binary

The fifth data bit for each scan is taken from the XTRA ROM. Note that only two outputs are available from this

ROM. If the character is even, the output at pin 11 is gated to the Video Buffer; if the character is odd, the output
at pin 12 is gated. This ROM is addressed exactly as is the EVEN ROM, as indicated in Table 12-9. The fifth data bit
for H is taken from pin 1 1 of the XTRA ROM. The result is shown below.
Scan Line

Data Bits Gated to

Video Buffer
3

00000

10001

11111

10001

NOTE: The pattern is generated for H.

12-54

BIT 6

BIT 7

BIT 8

BIT 9

1024- BIT MEMORY CELL
32 X 32
MEMORY MATRIX

1-0F-3E

DECODER

BIT 10-

ROM MS ROWCNT
ROM ROW CNT
ROM LS ROW CNT

1-0F-8
DECODER

1-0F-8

1-0F-8
DECODER

DECODER

BIT

""T!I=0

9
Figure 12-41

ROM Functional Logic Diagram

Table 12-8
Character H, EVEN

Scan Line

3
4
5

6
7

8
9
10

Bits 6-10

ROM Data Bits

ROM ROW CNT Binary

Data Word in

Representation

Addressed Location

000

011

0000
1000
1000
1000

100

1111

101

1000

110

1000
1000

00100
00100
00100
00100
00100
00100
00100
00100

001

010

111

12-55

1-0F-6
DECODER

Table 12-9
Character H, XTRA ROM Data Bits
Bits 6-10

Scan Line

00100
00100
00100
00100
00100
00100
00100
00100

3
4
5
6
7

8
9
10

ROM ROW CNT Binary

Data Word in

Representation

Addressed Location

000

0000
0010
0010
0010
0010
0010
0010
0010

001

010
011

100
101

110
111

PIN 11

PIN 12

The pattern table for each ROM is included in Appendix A. To locate the pattern for an ASCII character, use the
following procedure:

Procedure

Step

the character is even, divide the 6-bit binary representation by 2. The result gives the 6

most significant bits of the location.
2

Find this location in the Octal Location column of the EVEN ROM pattern table (Table
A-1) for 4 of the data bits; find the same location in the Octal Location column of the

XTRA ROM pattern table (Table A-3) for the fifth data bit.
For example:

When the binary representation of character T, 010 100 (24 8 ), is divided

by 2, the result

001 010 (12 8 ); octal locations 120-127 of the

EVEN and XTRA

ROMs contain the video information for the character.
3

the character

odd, take the even binary representation immediately preceding the

odd binary representation and divide by 2.
4

Find this location in the ODD and XTRA ROM pattern tables (Tables A-2 and A-3).

For example: To find the pattern for character G, 000 111 (07 8 ), divide 000 110 (06 8 )

by 2; the result, 000 01 1 (03 8 ), identifies locations 030-037 as yielding G.

Alphanumeric Video Buffer Control Logic — Figure 12-42 shows the alphanumeric Video Buffer Control
logic. The logic generates the signals that allow the Video Buffer to convert the parallel ROM bits to serial
alphanumeric video bits. The logic is shown for 32 characters per line; if 64 characters per line are being displayed,
the input clock frequency is 10.92 MHz. Figure 12-43 shows a timing diagram for the 32 character per line
12.4.2.10

operation. Refer to both figures when reading the logic description.

The 5.46 MHz signal is gated by the logic to produce the LD ALPHA VIDEO BUFFER and CLK ALPHA VIDEO
BUFFER signals. The E17 up-counter provides the necessary gating signals. The A, B, and C outputs of E17 are
applied to the

DEC 7442 BCD-to-Decimal Decoder, E22. When E22 decodes decimal 2, E26C is enabled and the

next clock produces a LD ALPHA VIDEO BUFFER signal. When E22 decodes decimal 3 through 7, E26B is enabled

12-56

and 5 clock pulses are gated through to produce CLK ALPHA VIDEO BUFFER. A VID EN signal is also
when E22 decodes decimal 3 through 7. This signal is asserted through the E28 multiplexer when the VIS ZONE L
through 7).
signal is low (note that the VIS ZONE L must be low for E22 to decode decimal 1
generated

CLK

Because E17 determines character rate, one LD ALPHA VIDEO BUFFER signal, one VID EN
ALPHA VID BUFFER signals are generated each time a character is shifted from the Line Buffer Register.
Remember that 32 SHIFT LINE BUFFER signals are used to recirculate the Line Buffer Register during each scan.
BUFFER signal generates a CLK B signal that shifts a different character to the ROM Character
signal, and five

Each SHIFT LINE

Generator. The character generator produces five bits that represent the character. A LD
signal then parallel loads these bits into the Video Buffer Register.

ALPHA VIDEO BUFFER

CLK ALPHA VIDEO BUFFER signals shift the data bits out of the buffer to the video logic. The VID EN
LD ALPHA VID BUFFER signal,
signal enables the video logic to generate signals for the display. Note that the
Register by the CLK B signal
Buffer
Line
the
from
shifted
designated A in Figure 12-43, loads the character that is
Five

character is being gated to
designated A. While this character is being shifted from the Video Buffer, the new 5-bit
the
gating of the 5.46 MHz
by
determined
is
spacing
the buffer inputs. Note, also, that the character horizontal
the horizontal
characters/line);
for
inches
32
(0.185
signal. The character width is represented by five clock pulses
by the
(indicated
gated
not
that
are
period
character
spacing is represented by the two clock pulses in each
0.074
or
width,
character
the
of
percent
is
40
spacing
the
ALPHA VIDEO BUFFER pulses). Thus,
dotted-line CLK
inches.

Figure 12-44 shows the timing of the alphanumeric Video Buffer Control logic for 64

characters per line. The logic is

the same as for 32 characters per line operation.

+ 3V

CARRY
F=5.46 MHz
(32 CH/LINE)"

CLK

E17 + 7
74161

LOAD

LD ALPHA VID BUFFER

CLK ALPHA VID BUFFER
2
E2Z
7442
BCD-DEC
DECODER 3D

H ZONE (11V Z0NE0)—

E19-D

E14J0-

MSB

(F-1.56KHZ)

-VID EN

VIS ZONE L

NOTE:
Logic is P/0 M8336 Module

GRAPH/ALPHAd)
(LO FOR ALPHANUMERIC)

Figure 12-42

Alphanumeric Video Buffer

12-57

5.46 MHz

1n.nnnnr

E17 A
I

—H

-*|

fi^*

k- 183.15ns

l_l

E17B
J

E17C

CHARACTER RATE 780KHZ

U.PHA VID BUFFER 780 KHz

SHIFT LINE BUFFER

—549.45ns

CLK B

(B-H)
|

l"l

M
II

CLK ALPHA VID BUFF

DC)T1

l"l

II
II

D0T2 D0T3 ID0T4 |D0T5

CH SPAC NG

|-|

i"i

JUULJUL

ALPHA VID ENAB 780KHZ

Figure 1 2-43

12.4.2.11

1.28ijs

8E-0652

Character Timing for a 32 Character Line

Graphic Video Buffer and Control Logic -The Graphic Video Buffer and Control logic is shown

Figure 12-45. This logic converts the parallel data in the Line Buffer Register to the serial graphic video signals that
are applied to the Display Mode logic.

When a data word is shifted from the Line Buffer Register, it is applied to the Graphic Video Buffer on the lines
designated BIT 11-0. The Video Buffer Register comprises three DEC 7595 4-bit Shift Registers that can be parallel

loaded and serial shifted. The DEC 74161 counter, E31, counts down the 5.46 MHz clock pulses to produce an LD
GRAPH VID BUFFER signal at a frequency of 455 kHz. The derivation of this signal is shown in the timing diagram
in Figure 12-46. Graphic Video Buffer
loaded by CLK GRAPH VID BUFFER when LD GRAPH VID BUFFER
is

true. This occurs every 12 clock pulses.

When the Video Buffer has been loaded, the LD GRAPH VID BUFFER signal goes low. The DEC 7495 Shift
Register cannot be shifted while this signal

out of the

pulses are available. Twelve
dots. This occurs at

shifted out first).

high. The next eleven

Note that bit 11

CLK GRAPH VID BUFFER signals shift data

not shifted from the register since only 11

shift

CLK GRAPH VID BUFFER signals are also used to chop graphic video into distinct

AND gate E28.

12-58

~» -LmrLnjiTLTLTirLnLnjirLrLru
i_^L_r~L_r

E17 A

E17B

E17C

E17D

E12

E12-CARRY.780 KHz

641ns

CHARACTER RATE

1.56 MHz

LD ALPHA VID BUFF

J~L
*

SHIFT LINE BUFF

CLK A
(780 KHz)

274 ns

•

CLK B

READ SELECT (B-H, A- L)

CLK ALPH VID BUFF

ALPHA VID EN

niLnLTin
12
3

Figure 12-44

junrui^

Character Timing for a 64 Character Line

12.4.2.12 Visible Field Logic- When an alphanumeric character is to be displayed, the data word transferred to
the Line Buffer Register contains not only character information, but also information that controls the visible field

and the mode of display. The 12-bit data word is shown in Figure 12-47.

The ASCII-coded character is contained in bits 5-11. Because the VT8-E displays a 64 character set, only bits 6-1
are used to generate character video. Control bits
visible field

1 and 2 (referred to as CB1 and CB2) are used to determine the
by selectively blanking the video display. Control bits 3 and 4 (referred to as CB3 and CB4) determine

how the video is displayed.
Figure 12-48 shows the visible field bits logic. These bits control the visible fieid as outlined in the table
accompanying the logic. When J-K flip-flop E44 is set, the BLANK L signal is asserted and the alphanumeric Video

Buffer output is inhibited (Figure 12-50 shows how the BLANK L signal inhibits video). Flip-flop E44 is controlled

an intricate manner that can best be described by a timing diagram. This diagram is shown in Figure 12-49. The
timing begins with the start of a character line, represented by the PRESET BRK signal.
in

12-59

GRAPH VIS ZONE L

FMAn

+ 3V E18-CARRY(LINE COUNT)

A
F=5.46 MHz

=c^

CARRY

CLK

V ZONE
H ZONE

E31

VID EN

;:=o^

LOAD
A

LD GRAPH VID BUFFER
GRAPHIC/ALPHA (1) H)
(HI FOR GRAPHIC)
CLK GRAPH VID BUFFER

r,P/O M8337

£1
BIT 11 BIT 10BIT 9 BIT 8 -

3 E20 8

DEC

7495
10

BIT 7
BIT 6
BIT 5
BIT 4

BIT 3
BIT 2
BIT 1
BIT

2
6
3 E19 8
10

3 E18 8
7495 9

•

GRAPH1H

NOTE:
Logic is P/O
less noted

ezb\

^> J

J GO AFTER V SYNC

M8336 Module

GRAPH
VIDEO

NOTE:
Logic is P/O

M8336 Module unless noted.

Figure 12-45

Graphic Video Buffer Control Logic

Assume that a character in the previous character line had directed the beginning of a blank field; i.e., CB1 of this
character was high, while CB2 was low. When this character was shifted from the Line Buffer Register, the next LD
ALPHA VID BUFFER signal to occur sets the J-K flip-flop E50B (Figure 12-47). Each succeeding character is either

NOP direction or another BBF direction (both have the same result in the present situation). At the beginning of
the present character line, a PRESET BRK signal and a LINE CNT signal occur simultaneously. The leading edge of
the LINE CNT signal clears the E44 flip-flop, while the trailing edge of the PRESET BRK signal sets flip-flop E50A.
The next LINE CNT signal sets E44 again, because now E50A is set. All three flip-flops would remain in this state
a

throughout the entire character line and into and through each succeeding character line if no EBF direction were
received.

However, if an EBF direction is programmed into a data word, the blank field must be ended at the same point in
Scan Lines 3 through 10 (although nothing is displayed in Scan Line 3). Assume that character 16 of the present
character line directs an end to the blank field. The LD ALPHA VIDEO BUFFER signal corresponding to character
16 clears flip-flops E44 and E50B. For the rest of Scan Line 3, the BLANK L signal is negated. At the start of the

fourth scan

line, flip-flop

E44 has to be set again to blank the first 15 characters. The LINE CNT signal sets the

flip-flop, thereby blanking the first 15 characters of Scan Line 4. Again, the sixteenth character says EBF and clears
flip-flop E44 (flip-flop B stays clear throughout). This procedure continues until the character line is completed. The

second LINE CNT signal of the next character line clears flip-flop E44, which then remains clear until another BBF
or an EOS is directed.

12-60

GRAPH VIS ZONE H

5.46Mhz

nruinnrrinnrwwYTinririnrinrin

CLK GRAPH VI D BUFFER

E31

"mjrrLTLjm^^-mrLn

•31-B

E31-C

E31

-.1

LD GRAPH VID BUFFER

f=455Khz

LOAD
455Khz

SHIFT LINE BUFFER H-

Graphic Word Timing

Figure 12-46

CB1

CB2

CB3

CB4

VISIBLE
FIELD

DISPLAY

BITS

T ASC11

MODE

Figure 12-47

12-Bit Data Word Format

When the 7-bit ASCII code for line feed (012) is detected, NAND gate E1 1 is enabled, putting a high on the J input
of flip-flop E44. The LD ALPHA VID BUFFER signal corresponding to the character 012 sets E44, and the rest of
It would be contradictory to have the EBF control bits set for the line feed character.
The K input of E44 should not be a 1 when the LF (012) character is detected.

the character line is blanked.

12.4.2.13

Display Mode Logic - The Display Mode logic is shown in Figure 12-50. These bits determine how the

alphanumeric video is displayed, as outlined in the table accompanying the logic.

When the character is to be displayed with normal intensity, the LD ALPHA VID BUFFER signal clears flip-flops
E27A and E27B. NAND gate E30B gates the serial output of the alphanumeric Video Buffer Register to NAND gate
E39. If the BLANK L signal is not asserted, the asserted ALPHA VID EN signal and the negated GRAPH L signal
gate the five data bits to the VIDEO line. If the character is to be displayed at increased intensity, E27A is set, while
E27B is cleared. NAND gate E34C is enabled, in addition to E30B. Inverters E29A and E29B have open-collector
outputs. For increased intensity, both gates are inactive. Consequently, the VIDEO output is approximately 5V. For

normal intensity E29B is active and there is a voltage drop in the neighborhood of 3.5V across the 1 kJ2 resistor.
Therefore the VIDEO output is approximately 3.5V.
12-61

LINE CNT

BMD

TRUTH TABLE
Tn
J

Tn*1
K

CB1

CB2

Q
On

OPERATION

DESCRIPTION

NOP

DISPLAY CHARACTER IN BIT 6-11 IF IN
VISIBLE ZONE
END BLANK FIELD.DISPLAY THIS

EBF

CHARACTER AND THOSE FOLLOWING
BEGIN BLANK FIELD.FROM AND INCLUDING THIS CHARACTER. VISABLE FIELD CAN
BE STARTED LATER IN BUFFER BY EBF

1
1

1
t

BBF

Tn= bit time before clock
1

Trn-1 =bit time after clock

END OF SCREEN. VISIBLE FIELD IS
ENDED BEFORE DISPLAYING THIS CHARACTER UNTIL NEXT VERTICAL RETRACE

EOS

NOTE:
Logic is P/O

M8337 Module

Figure 12-48

E50AC1)

Display Control Logic

E50B(1)

PRESET BRK

LN CNT

n _fi.

~Lr"~L.r~

E44(1)
J

CHARACTER
16

SAYS
EBF

Figure 12-49

ri_

BBF and EBF Timing

12-62

n
i

CLK ALPHA VID BUFFERLOAD ALPHA
VID BUFFER

PRESET

OUTPUT
OF

CLOCK

7496

5-BIT S.R.

ROM

OUTPUT

E32
7474
3.75 Hz-

BLANK L

E30B

_^T)°-^>

E34

CB3

^E30A

(BMD3)

E34B

ALPHA
VID EN

E27A
7474

——
C

E29B

GRAPH L
CB4

*•

(BMD4)

CB3

CB4 OPERATION

NOP

E27B
7474

BRIGHT

NOTE:
Logic is P/O M8337 Module

Figure 12-50

BLINK

CURSR

DESCRIPTION
DISPLAY CHARACTER AT NORMAL
INTENSITY

BLINK CHARACTER AT 1.875Hz RATE
DISPLAY CHARACTER AT INCREASED
INTENSITY
DISPLAY CHARACTER AS CURSOR

Display Mode Logic

A character is blinked at a 1.875 Hz rate when CB3 is logic

and CB4 is logic 1. The 3.75 Hz signal clocks flip-flop

E32. The 0-output of the flip-flop alternately enables and disables NAND gate E30C, resulting in a VIDEO signal
that blinks at the desired rate. If CB3 and CB4 are both logic 1,

NAND gate E30A

alternately enabled and disabled

by the 3.75 Hz signal. NAND gate E30B is enabled by the character bit, while NAND gate E34B is enabled by the
character's bit matrix complement. Thus, the character is displayed as a cursor.

12.4.2.14

Maintenance IOT Logic — The Maintenance IOT logic, shown in Figure 12-51, is enabled at TP3 time if

the program executes the DPSM instruction to set the MAI NT/GO flip-flop (E56). Refer to Paragraph 12.3.4 for a
description of the IOT instructions enabled when the VT8-E

the Maintenance mode. These instructions allow

the registers and buffers in the VT8-E to be read into the AC. Data may also be transferred from memory using the

DPMB instruction. DPMB sets the BRK RQST flip-flop on the M8337 module and the VT8-E executes one Single
Cycle Data Break to transfer data from the memory location determined by the Starting Address Register to the
Line Buffer.

12.4.2.15

Display Interrupt and Skip Logic — The Interrupt and Skip logic is shown in Figure 12-52. Interrupts are

in the AC is 1 when the DPGO instruction is executed by the program. This sets INT EN A and the
VT8-E makes an INT RQST when the Real Time Clock (RTC) flag sets at the start of a vertical retrace and signifies

enabled if bit 1 1

the end of the display frame.

The Skip Bus (SKIP L) is asserted at I/O PAUSE time of the DPCL instruction cycle to cause the program to skip
the next sequential instruction. The program may at this time switch modes (Alphanumeric/Graphic) without
disturbing the visible presentation.

12-63

INITIALIZE

X>
-MAINTVGO(I)

E56
MAINT/

DPSM L

TP3

E48C

DPMB L-

MAINT L

^O—

-I0T3- MAINT L

LD AODR CNTR L

LD X ST ADD

—O-rrv

HZ^tO"

DATA EN A L

-DATA EN B L

-CO L
-C1 L
-

BRK ADD RD EN

- RD D

BUFFER EN

NOTE:
Logic is P/0 M8336 Module

Figure 12-51

Maintenance IOT Logic

12.4.2.16 Bell Logic - The Bell logic is shown in Figure 12-53. BELL EN, a 74123 IC, outputs a 476 ms pulse
when the DPBL instruction is executed by the program to enable the 1.56 kHz signal from E1 1-0 to be applied to
the bell. The volume of the tone is adjusted by potentiometer R25 on the M8336 module.

12.5

DISPLAY MONITOR CIRCUITS

12.5.1

Keyboard Logic

The keyboard (Drawing D-CS-301 01 66-0-0) provides the VT8-E output to the computer. There are 128 ASCII
characters or codes that can be generated by the keyboard. A 2-way slide switch is mounted on the Keyboard Logic
circuitry board to allow the

keyboard to be set for upper/lower case ASCII (128 codes) or lower case ASCII (96

codes) operation. Each key has a variable capacitance that is actuated when the key is pressed, causing an excitation
voltage to be applied to one side of the capacitor, generating base drive for the transistor amplifier. A sequential

scanning technique is used, employing a MOS integrated circuit that consists of an 8-bit and an 1 1-bit ring counter
(to compose an 8 X 11 matrix), and circuitry to sample the conductance of each transistor amplifier (one per key).
As the two (8-bit and 11 -bit) registers cycle, the 8-bit counter provides a collector voltage to as many as eleven of

Up to eight of the transistor emitters are connected to each of the sensing circuits gated
by the 1 1-bit counter. The two sets of lines that form the 8 X 1 1 matrix are theoretically capable of sampling up to

the key output amplifiers.

88 keys.

12-64

+ 5V
DATA EN A

rDH>

DATA

1 1

*-C
D

J-4

DPGO L
TP3

INT ROST L

TP4

INT
ENA

x>-

RTC

SKIP L

3D—I>
JT D

DPCL L

E9SYNC)

NOTE:
Logic

P/0 M8336 module.

Figure 12-52

Display Interrupt and Skip Logic

+ 5V

TP3

DPBL

XH>f&C

•

74123

BELL
EN

(1.56KHz)

NOTE:
is

— ——

~^°

vvv

AUDIO

VOLUME ADJUST

E11-D

Logic

P/0 M8336 module.

Figure 12-53

12-65

Bell

Logic

The VT8-E uses the small 8-key keyboard as an extension of the main keyboard to generate cursor control codes to
position the cursor and to erase text. The keys used for cursor control or positioning are: cursor up (f), cursor
down (|), cursor left {•*), cursor right (), and HOME. The erase-to-end-of-line (EOL) and erase- to-end-of -screen
(EOS) keys are used in conjunction with the LOCK key. The EOL and EOS codes will not be transmitted unless
they are used in conjunction with the LOCK key.

Motorola CRT Display

12.5.2

The following circuit descriptions refer to the detailed circuit schematic of the Motorola CRT Display Module shown
in

Drawing D-CS-301 0326-0-3.

Video Amplifier — The Video Amplifier has four stages incorporating devices Q1, Q2, Q3, and Q4. The
Q1, functions as an emitter follower to provide a high impedance input with the 75£2 terminating resistor
removed. The high impedance operation permits use of bridging connections to drive a number of monitors from the
12.5.2.1

first stage,

same signal source. The low output impedance of the first stage permits use of a low resistance contrast control
which furnishes flat video response over its entire range without the need for compensation. The collector output of
Q1 is used to drive the Sync Separator. C3 provides high frequency roll off to limit the collector output to the
band-width required to pass synchronization signals. Q2 is a common emitter stage and is directly coupled to Q4. Q3
and Q4 are connected in a cascade configuration. This common emitter/common base connection greatly reduces
the effect of Miller capacity compared with a conventional single transistor video output stage. C6 provides a ground
for video at the base of Q3, the grounded base transistor of the video output cascade pair.

The video bias control (R10)

used to set the quiescent collector voltage of Q3 r C5, C7, C8, and R15 for high

frequency compensation. Restoration of dc voltage is accomplished by setting the video bias control so that sync
tips,

which are negative-going at the collector of Q3, just go into saturation. Variations in video drive result in

variations in the base current of Q2 during sync time due to the low load reflected back when Q3 is saturated. The

charge on

C4 will thus depend on the amplitude of output collector current during sync time. The result is a

clamping action which holds sync tips at the same level despite video signal variations. The Video Amplifier output is
direct coupled to the control grid of the CRT. R18 is used to isolate Q3 from transients that may occur as a result of

CRT arcing.
12.5.2.2
signal.

Sync Separator — The Sync Separator uses a single stage, Q5, to recover sync from the composite video

A single-stage Sync Separator is adequate due to the high impedance of the following stages. The video input

to the Sync Separator is black positive. C1 1 is charged by the peak base current that flows when the positive peak of
the input takes Q5 to saturation. This charge depends on the peak-to-peak input to Q5 and thus makes the bias for

Q5 track the amplitude of the input signal. As a result, Q5 amplifies only the positive peaks of the input signal. The
initial bias current through

12.5.2.3

R24 sets the clipping level.

Phase Detector — The Phase Detector uses two diodes in a key clamp circuit. Two inputs are required to

generate the required output, one from the Sync Separator and one from the horizontal deflection system. The
required output must be of the correct polarity and amplitude to correct phase differences between the input sync

and the horizontal time base. The horizontal collector pulse is integrated into a sawtooth by R45 and C15. During
sync time, both diodes in D7 conduct, shorting C15 to ground.

The sawtooth on C15 is thus clamped to ground at sync time. If the horizontal time base is in phase with the sync,
is passing through its ac axis and the net charge on C15 will be
(Figure 12-54). If the horizontal time base is lagging the sync, the sawtooth on C15 will be clamped to ground at a

the sync pulse will occur when the sawtooth

point negative from the ac axis. This will result in a positive dc charge on C16 (Figure 12-54). This is the correct
polarity to cause the Horizontal Oscillator to speed up to correct the phase lag.

Likewise,

the horizontal time base is leading the sync, the sawtooth on C15 will be clamped at a point positive

from its ac axis, resulting in a negative charge on C15. This is the required polarity to slow the horizontal oscillator
(Figure 12-54). R33, C17, C16, and R32 comprise the Phase Detector Filter. The bandpass of this filter is chosen to
correct the Horizontal Oscillator phase without ringing or hunting.

12-66

REFERENCE

inr

HORIZ.

SYNC
OSC ON FREQ

«.

r^s.

C^. NO CORRECTION
VOLTAGE DEVELOPED

OSC SLOW POS
CORRECTION VOLTAGE

."ly^r

rsT"

Figure 12-54

12.5.2.4

OSC FAST NEG
CORRECTION VOLTAGE

CRT Horizontal Oscillator Waveforms

Horizontal Oscillator - Q6 is employed in a modified type of Hartley oscillator. The operating frequency

of this oscillator is sensitive to its base input voltage. This permits control by the output of the Phase Detector and
also by the setting of the horizontal hold control. The horizontal hold range is set by adjusting the core of L1

12.5.2.5

Pulse Shaper and Horizontal Drive - Q7

the Horizontal Driver.
Horizontal Driver.

used as a buffer stage between the Horizontal Oscillator and

provides isolation for the Horizontal Oscillator as well as a low impedance driver for the

R38 and C20 form a time constant which shapes the oscillator output to the required duty cycle

(approximately 50 percent), to drive the Horizontal Output circuitry. The Horizontal Driver stage, Q8, operates as a
switch to drive the Horizontal Output transistor through T1. Because of the low impedance drive and fast switching
times furnished by Q7, very little power is dissipated in Q8. C21 and R42 provide damping to suppress ringing of the

primary to T1 when Q8 goes into cutoff.
12.5.2.6

Horizontal Output - The secondary of T1 provides the required low drive impedance for Q9.

R44 and

C24 form a time constant for fast turn-off of the base of Q9. Q9 operates as a switch that, once each horizontal
period, connects the supply voltage across the parallel combination of the horizontal deflection yoke and the
primary of T2. The required sawtooth of the deflection current through the horizontal yoke is formed by the L-R
time constant of the yoke and output transformer primary. The Horizontal Retrace pulse charges C27 through D2 to

G2 of the CRT. Momentary transients at the collector of Q9, should they occur, are
limited to the voltage on C27, since D2 will conduct if the collector voltage exceeds this value.
provide operating voltage for

The damper diode, D1, conducts during the period between retrace and turn-on of Q9. C28 is the retrace tuning
capacitor. C29 blocks dc from the deflection yoke. L3 is a magnetically-biased linearity coil that shapes deflection
current for optimum trace linearity. L4 is a series width control. C31 and R49, C42 and R68 are damping network
components for the linearity and width controls. C43D is charged through D5 developing the video supply voltage.

12.5.2.7

Vertical Oscillator Driver and Output - Sync from the collector of Q5 is integrated by R26 and C35. Q10

The series combination of C37 and C38 charges through R58 and
D3 until Q10 turns on. This occurs when the emitter of Q10 exceeds its base voltage and causes current to flow into
the base of Q1 1, turning that device on. When Q10 and Q1 1 conduct, C37 and C38 are discharged to nearly 0. Q10
and Q1 1

are connected as a regenerative switch.

and Q11 then shut off and the cycle repeats. The setting of the vertical hold control determines the repetition rate
of the charge and discharge of C37 and C38. The waveform generated is a positive-going ramp or sawtooth with a
fast retrace to 0.

D3 provides a small incremental voltage above ground to overcome the forward base-emitter drop
Q12 is an emitter follower used to transform the high impedance drive sawtooth to a

of the two following stages.

low impedance drive for Q13.

T3 matches the collector of Q13 to the vertical yoke. When Q13 is cut off during Vertical Retrace, a high voltage
pulse is developed across the primary of T3. To limit this pulse to a safe value a varistor, R81, is connected across

12-67

the primary. R66 and C41 provide damping to shape the collector pulse so it may be used for retrace blanking. Since

the primary impedance of T3 decreases with current, the degree to which the primary shunts the reflected load

impedance varies with collector current. This would result in severe vertical non-linearity unless some compensation
is

employed.

Resistors

R60 and R59 couple the emitter voltage of Q13 to the junction of C37 and C38. Since this path is

resistive, the

waveform coupled back will be integrated into a parabola by C38. This results in a pre-distortion of the

drive sawtooth as shown in Figure 12-55. This is done to compensate for the non-linear charging of C37 and C38 and

the changing impedance of the primary of T3. An additional feedback path through R62 and C40 serves to optimize
the drive waveshape for best linearity.

PARABOLA
FROM EMITTER
OF Q24
EXISTING

VERTICAL SAWTOOTH
WITHOUT
VERT PARABOLA ADDED

PARABOLA PULSE AND
VERTICAL SAWTOOTH ADDED
TOGETHER, HENCE PRODUCING
THE REQUIRED VERT DRIVING SIGNAL

Figure 12-55

12.5.2.8

CRT Vertical Oscillator Waveforms

Retrace Blanking — Both Vertical and Horizontal Retrace blanking are provided by positive pulses applied

to the CRT cathode. The collector pulse from the Horizontal Output transistor is placed across R23 through R46.

The vertical

collector voltage

differentiated

by C30 to remove the sawtooth portion of the waveform. The

remaining pulse appears across R23. The mixed vertical and horizontal pulses on

R23 are coupled to the CRT

cathode by C10.

Power Supply — The regulated power supply uses a series pass circuit. Q16 is the series pass transistor,
Q14 is the driver, and Q15 is the reference amplifier. The output voltage of the regulator appears at the emitter of
Q16 and is fed into a voltage divider consisting of R71, R74, and R73. The voltage appearing on the arm of
potentiometer R74 is used as an error input to Q15. R74 is thus used as the output voltage adjustment.
12.5.2.9

Zener diode D13 establishes a reference voltage at the emitter of Q15. R72 establishes the minimum bias current for

D13 to ensure proper Zener operation.
The voltage at the arm of R74 is compared with the reference voltage at D13 by Q15. If the voltage at the base of

Q15 increases due to an increase in input voltage to the power supply for example, Q15 conducts more current. This
decreases the current available to the base of Q14, so Q14 and Q1 6 conduct less current, resulting in less voltage at

the emitter of Q16. In this manner, input voltage changes are reduced by the overall gain of the regulator, which is
quite high.

R79 reduces the power dissipation in Q16 by carrying some of the supply current. This does not impair

regulation over the operating range of the power supply due to the large amount of gain available.

SECTION 5 MAINTENANCE
12.6

INTRODUCTION

VT8-E maintenance theory is directed to the module replacement level. The maintenance effort is divided into two
basic categories:

preventive maintenance and corrective maintenance.

12-68

Preventive maintenance consists of routine periodic checks such as visual inspections, standard maintenance
procedures that involve cleaning and lubricating, and diagnostic tests that expose possible weakening conditions to

allow corrective action to be taken, eliminating the causative factor(s) of possible failures.
Corrective maintenance consists of isolating the fault or problem and making necessary adjustments and/or
replacements when a malfunction occurs. This involves the use of diagnostic routines prepared on paper tape and

designed to test the functional units of the system. The procedures and techniques of periodic checking aid in fault
isolation.

Power requirements can be checked through the checkout procedures for power requirements contained in

Paragraph 12.2.2.

12.6.1

Equipment Required

Maintenance procedures for the VT8-E Video Display and Control require the standard equipment (or equivalent),
standard hand tools, and test probes listed in Table 12-10.

Table 12-10

Equipment Required

Equipment

Manufacturer

Designation

Multimeter

Triplett or Simpson

Oscilloscope

Tektronix

X10 Probe

Tektronix

Model 630-NA or 620
Type 453
P6010

Recessed Tip

Tektronix

01 3-0090-00

Diagnostic Self-Test

Routines

12.6.2

Diagnostic Programming

The diagnostic

routines, supplied as paper tapes, are used to test the various VT8-E functions and modules. A
complete description with instructions is provided with each tape.

12.6.3

Preventive Maintenance

Preventive maintenance consists of tasks performed periodically; its major purpose

is to prevent failures caused by
minor damage or progressive deterioration due to aging. A preventive maintenance log book should be established

and necessary entries made according to a regular schedule. This data, compiled over an extended period of time, can
be very useful

anticipating possible component failures resulting in module replacement on a projected module or

component reliability basis.
Preventive maintenance tasks consist of mechanical and electrical checks. All maintenance schedules should be
established according to the environmental conditions at the particular installation site. Mechanical checks should be

performed

often as

maintenance tasks

required

should

to allow the fan and air filter to function efficiently. All other preventive

performed

on a regular schedule determined by reliability requirements.
recommended schedule is every 600 operating hours or every four months, whichever occurs first.

12-69

Mechanical Checks — Use the following procedure to perform a mechanical check on the equipment.

12.6.3.1

Procedure

Step

Unplug the VT8-E main power and remove the cover.

Clean the exterior with a clean cloth moistened in a mild detergent. Only a very soft cloth

should be used to avoid scratching the protective screen used on the face of the CRT.
Clean the interior using a vacuum cleaner and ensure that the cabinet air exhaust vents are

thoroughly clean and unobstructed to promote adequate cooling. Should the vents

become obstructed, premature component failure may occur due to an increase in the
VT8-E internal temperature.
4

Inspect

all

wiring and cables for cuts, breaks, fraying, deterioration, kinks, strain, and

mechanical security. Tape, solder, or replace any defective wiring or cable covering.
Inspect the following for mechancial security: jacks, connectors, keyboard, etc. Tighten

or replace as required.

12.6.4

Troubleshooting

12.6.4.1

System Troubleshooting — Begin troubleshooting by repeating the operation

which the malfunction

was initially observed, using the same program or function. Thoroughly check the program for proper settings and
determine if the fault is definitely located in the VT8-E.

the fault

isolated to the

VT8-E, but cannot be immediately localized to a specific logic function, an effort
the fault to one of the VT8-E modules, e.g., keyboard, M8335 module, CRT

should be made to further

isolate

module, etc. Some helpful

aids during functional analysis are the

VT8-E engineering drawings, circuit schematics,

timing diagrams, and the applicable VT8-E diagnostic programs.

12.6.4.2

Module Troubleshooting — Once the fault has been isolated to a specific module, carefully remove the

suspected module. Inspect the receptacle for wear or damaged contacts. When the operability of the module is
verified, repair the faulty

diagnostic program.

module or replace it with a module known to be operating properly and run the last

the system performs properly, return the system to an operating status and log an entry to

record all pertinent data concerning the fault or malfunction. When the individual defective part(s) within a module
is

located and repaired or replaced, the module should be verified by a validation test.

VT8-E Assembly/Disassembly — The following procedures are provided for removal, replacement, and
of the various VT8-E modular components. Special and cautionary notes contained within the
procedures afford special attention and should be adhered to. Only procedures for the removal of the VT8-E
modular components are provided; for installation, the procedures should be performed in their reverse order.
12.6.4.3

installation

12.6.4.3.1

VT8-E Module Boards - The M8335, M8336, or M8337 module boards should be inserted straight into

the OMNIBUS, never at an angle. When inserting a module board be certain it is fully seated in the OMNIBUS.

12.6.4.3.2

Cover Removal - The VT8-E cover

secured with four Phillips-head screws. Screw locations are

midway on the two sides. The screws are inserted up through the lower casting and
into four cover-retaining brackets. To remove the cover, remove the four retaining screws and lift the cover off.

center-front, center-rear, and

NOTE
When the cover is removed, the 3-position interlock switch on
the left-hand side (viewing from the front) will go from the
fully depressed position

(ON) to the middle position (OFF)

and must be pulled up to the third position (ON).

12-70

To install the cover, place the cover back on the lower casing, insert and tighten the four Phillips-head retaining
screws. The interlock switch should be in the fully depressed (ON) position.

12.6.4.3.3 VT8-E Keyboards Removal - The VT8-E contains two keyboards, a large teletypewriter-type keyboard,
and a small 8-key cursor control keyboard. The small keyboard is secured by four Phillips-head screws that are
inserted

down through the four corners of the mounting board into the mounting bracket. The large keyboard is
down through the keyboard mounting bracket. These four

secured by four Phillips-head screws that are inserted

screws should not be confused with the smaller and brighter Phillips-head screws that secure the keyboard to the

keyboard logic board. The smaller, brighter screws should not be removed.
Use the following procedure to remove the small keyboard:
Step

Procedure
Disconnect the ribbon cable from the small keyboard input connector.

Remove

the

four Phillips-head

retaining screws

from the four corners of the small

keyboard mounting board.
3

Slide the keyboard to the left and lift it out.

Use the following procedure to remove the large keyboard:
Step

Procedure
Disconnect the 44-pin Berg connector from the keyboard output connector.

Remove the four, larger keyboard Phillips-head retaining screws from the keyboard
mounting bracket and remove the keyboard

12.6.4.3.4

CRT Removal - The CRT is secured to the VT8-E lower casting with four Phillips-head screws that are
VT8-E and into the bottom four corners of the CRT chassis. Use the following

inserted through the bottom of the

procedure to remove the CRT:

CAUTION
Protective goggles and

heavy gloves should be worn when

removing and/or carrying the CRT. Never grasp the CRT by
the neck, nor chip or scratch any part of the tube.

Step

Procedure

Press the interlock switch down to ensure main power is off.

Viewing the VT8-E from the front, locate (15-pin and 12-pin) Mate-N-Lok connectors P1
and P2 on the lower right-hand side of the CRT chassis and disconnect both connectors.

Locate and remove the four Phillips-head retaining screws on the bottom of the VT8-E,
used to secure the CRT chassis to the lower casting.

NOTE
Upon removal, the CRT should be placed face-down on a soft clean
cloth or pad.

Under no circumstances should the CRT be grasped by

the neck

Lift the

CRT out of the lowercasing.
12-71

APPENDIX A

ROM PATTERN TABLES

Table A-1

ROM Pattern Table
(EVEN ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

000

0000

0111

24
25

030

001

031

1111

002
003

1000

26
27

032
033

1000
1000

1010

28
29

1000

007

0111

034
035
036
037

1111

1011

004
005
006

010

0000

040

011

1111

041

012
013

1000
1000

042
043

014
015

1111

1000

016
017

1111

020

021

3
4
5

1011

1000
1000
1000

0000
1000
1000
1000

044
045
046
047

1000
1000

0000
1110

050

0000

051

0011

022

1001

0001

023

1000

052
053

024
025
026
027

1000

44
45

1001

1110

054
055
056
057

0001

1000

13
14

A-1

1111

1000

0001

1001
1001

0110

Table A-1 (Cont)

ROM Pattern Table
(EVEN ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

48
49
50

060

0000
1000
1000
1000

84
85
86
87

124

0010
0010
0010
0010

064
065
066
067

1000

130

1000
1000

131

132

1111

133

56
57

070

134

072
073

93
94

135

58
59

0000
1000
1000
1100

136

0101

137

0010

074
075

1010

140

076
077

1000

142

0000
1000
1000

1000

96
97
98
99

143

0101

64
65
66
67

100

0000

100

144

0010

101

1111

101

0101

102

103

1000
1000

145
146
147

68
69
70

104

1111

104

150

0000

105

1000

105

151

1111

106

152

0000

107

1000
1000

107

153

0001

110

0000

108

154

73
74
75

111

1111

109

155

0010
0100

112

1000
1000

110

156

1000

113

111

157

1111

76
77
78
79

114

1111

112

160

115

1001

113

161

116

1000
1000

114

162

117

115

163

0000
0000
1000
0100

120

0000

116

164

0010

121

1111

117

165

0001

82
83

122

0010
0010

118

166

119

167

0000
0000

52
53
54
55

061

062
063

071

123

1001

103

A-2

125

126
127

141

0000
1000
1000
1000
1000
1000

1000
1000

Table A-1 (Cont)

ROM Pattern Table
(EVEN ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

120

170

0000

156

234

0100
1010

121

171

0111

157

122

172

1000

158

235
236
237

0110

1001

123

173

0000

159

124

174
175

0000
0000
0000
0000

160

240

0000

161

241

0001

162

163

242
243

0010
0100

164

244

165

0100
0100
0010

167

245
246
247

168

250

169

251

170

252
253

125
127

176
177

128

200

129

201

130

202

131

203

0000
0000
0000
0000

132
133
134
135

204
205
206
207

0000
0000
0000
0000

126

166

171

254
255
256
257

0001

0000
0010
1010
0111

136

210

0000

172

137

211

0101

173

138
139

212

0101

174

213

0101

175

0000
0000
0000
0000

176

260

177

261

178

262
263

0000
0000
0000
0000

0000
0010

180

0111

182

1000

183

264
265
266
267

0000
0010
0010
0100

140

214

141

215

142

216
217

143
144
145

220

146

222
223

147

221

151

224
225
226
227

152

230

153

231

154

232

155

233

148
149

150

179

181

1101

0111

1010

0010

0111

184

270

0000

185

271

272
273

0000
0000
0000
0000

274
275
276
277

0000
0000
0000
0010

1111

186

0010

187

0000
0100
1010
1010

188
189
190
191

A-3

Table A-1 (Cont)

ROM Pattern Table
(EVEN ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

192

300

0000

301

0111

341

0111

302

1000

195

303

1001

224
225
226
227

340

193
194

342
343

1000
1000

196
197
198

1010
1100

344
345
346
347

0111

1000
0111

228
229
230

199

304
305
306
307

200

310

0000

311

0111

202
203

312
313

1000
0000

232
233
234
235

350

201

0000
0000
0000
0010

204
205
206
207

314
315
316
317

0011

354

1111

236
237
238
239

355
356
357

0000
0010
0000
0000

208
209
210

320

0000

240

360

0000

321

0001

241

361

0001

322

0011

211

323

0101

242
243

362
363

0010
0100

212

324

1001

213
214
215

325
326
327

1111

0001

244
245
246
247

364
365
386
367

0100
0010

216
217
218
219

330

0000
0011

332

0100
1000

248
249
250

370

331

372

0000
0100
0010

251

373

0001

220

334
335
336
337

252
253

1000
0111

254
255

374
375
376
377

0000

1000

221

222
223

333

231

0100
1000

0001

1111

A-4

351

352
353

371

1000
1000
0111

1000

0001

0010
0100

Table A-2

ROM Pattern Table
(ODD ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

000

0000
0010

36
37

0010
0010
0010

3
4
5

001

002
003
004
005

0101

1000

044
045
046
047

0111

1000

050

1111

051

0000
1000

006
007

1000

052

1001

1000

053

1010

010

0000

011

0111

012

1000

013

1000

44
45
46
47

054
055
056
057

1100

014
015

1000

060

0000
1000

1000

016
017

48
49
50

0111

020

0000

021

1111

022
023

1000
1000

024
025
026
027

13
14

20
21

22
23

24
25
26
27
28
29
30
31

32
33
34
35

1000

061

1010
1001

1000

062
063

1101

064
065
066
067

1010
1000
1000
1000

1111

070

0000

1000

071

0111

1000

1111

072
073

1000
1000

074
075
076
077

1000
1000
0111

1010

030

0000

031

0111

032
033

1000
1000

034
035
036
037

1000

100

0000

101

0111

1000
0111

64
65
66
67

102

103

1000
1000

040

0000

1000

0111

0010
0010

105
106
107

1010

042

68
69
70

104

041

043

1011

A-5

1000

1001

0110

Table A-2 (Cont)

ROM Pattern Table
(ODD ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

110

0000

108

154

1100

73
74
75

111

0111

109

155

1100

112

110

156

1100

113

1000
1000

111

157

1111

114

0111

112

160

0000

115
116

0000
1000

113
114

161

1111

162

0001

117

0111

115

163

0001

120

164

0001

121

117

165

0001

122

118

166

0001

123

0000
1000
1000
1000

116

119

167

1111

84
85
86
87

124

1000

120

170

125

1000

121

171

126

1000

122

172

127

0111

123

173

0000
0000
0000
0000

88
89
90

130

124

174

125

175
176

133

126
127

0000
0000
0000

0000
1000
1000
1000

177

1111

92
93
94
95

134

1010

128

200

135

1010

129

201

136

1101

130

137

1000

131

202
203

0000
0010
0010
0010

96
97
98
99

140

0000

132

141

1000

133

142

1000
0101

134
135

204
205
206
207

0010
0010
0000
0010

100

144

211

0101

212
213

0101

147

136
137
138
139

0000

145
146

0010
0010
0010
0010

210

101

150

0000

140

1111

141

152

1100
1100

142

214
215
216
217

0101

151

78
79

102
103

104
105
106
107

131

132

143

153

143

A-6

1111

0101
0101

Table A-2 (Cont)

ROM Pattern Table
(ODD ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

264
265

Location

Data

Location

144

220

0000
1100
1100

180

266
267

145

221

146

222

181

182

147

223

0001

183

148
149

224

0010
0100

184

270

185

271

151

225
226
227

152

230

150

1111

0000
0000
0000

1001

186

272

0000
0000
0000

0001

187

273

0001

188

274

189

275

0010
0100

190
191

276
277

1000
0000

0000
0010
0110
0010

153
154

232

155

233

0000
0010
0010
0010

156

0000
0000
0000
0000

192

300

193

301

194

302

159

234
235
236
237

195

303

160

240

161

162

242

0000
0100
0010

196

241

0010
0010
0010

163

243

0001

199

304
305
306
307

164

244

0001

200

310

0000

245
246

0001

201

311

1111

0010
0100

202

312
313

0000

204

314
315

0011

205

252
253

0000
0000
0010
0010

206
207

316
317

0111

1111

320

0000

0010
0010
0000

208
209
210

321

1111

322
323

1000

175

254
255
256
257

176

260

324
325
326
327

0000
0000

157

158

165

166
167
168
169
170
171

172

173
174

231

247

250
251

177

261

178
179

262
263

197

198

203

211

0000
0000
0000
0000

212

213
214
215

A-7

0111

0001

0000
1000

1111

1000
0111

Table A-2 (Cont)

ROM Pattern Table
(ODD ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

216
217
218

330

0000

331

1111

332
333

0000

236
237
238

0001

239

354
355
356
357

0000
0010
0010
0100

334
335
336
337

0010
0100
0100
0100

240

360

241

361

242

243

362
363

0000
0000
0000

340

0000
0111.
1000

244
245
246
247

364
365
366
367

0000

341

370

0000

371

0111

0001

248
249
250

1110

251

372
373

0001

0000
0000
0000
0010

252

374
375
376
377

0010
0010
0000
0010

219

220
221

222

223
224
225
226
227

228
229
230
231

232
233
234
235

342
343

344
345
346
347
350
351

352
353

1000
0111

0000

253
254
255

A-8

1111

0000
0000

1000

Table A-3

ROM Pattern Table
(XTRA ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Lo' Jtion

Data

Location

Data

000

0000
0000
0010
0011

36
37
38
39

044
045
046
047

0010
0010
0010
0010

0011

050

0000

0011

051

0011

0001

42
43

052
053

0000
0000

44
45
46
47

054
055
056
057

0000
0000
0000

060

0000

061

0001

0011

48
49
50
51

062
063

0001

0000

4
5
6
7

001

002
003
004
005
006
007

0011

010

011

012
013

0011

0000
0010

014
015
016
017

020

0000

021

0001

022
023

0000
0010

064
065
066

0001

53
54
55

067

0011

024
025

0010
0010
0000

070

071

0000
0010

0001

072
073

0000
0010

60
62
63

13
14

20
21

0000
0000

0010

026
027

030

031

032
033

0001

0000

034
035
036
037

040

33
34
35

041

28
29

042
043

0000

64
65
66
67

0001

0000

0000
0010
0010
0010

A-9

074
075
076
077

0001

0001
0001

0001

0011
0011
0011

0011
0011

0010

101

0000
0000

102

0011

103

0011

104

0001

69
70

105

0001

106

0000

107

0001

100

Table A-3 (Cont)

ROM Pattern Table
(XTRA ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

110

154

73
74
75

0000
0000

108

111

109

155

112

0011

110

156

0000
0000
0000

113

0010

111

157

0011

114

0000

112

160

0000

115

0001

113

161

0001

0011

114

162

0001

116
117

0010

115

163

0001

120

0000

116

164

0001

121

0011

117

165

0001

82
83

122

118

166
167

0011

123

0001
0001

124

0001

120

170

125

0001

121

171

126
127

0001

122

172

0000

123

173

0000
0000
0010
0000

130

0000

124

174

131

0011

125

175

132
133

0011

126

0011

127

176
177

134
135

0011

128

200

0011

129

201

136
137

0001

130

0001

131

202
203

140

0000

132

204

141

0011

98
99

142

0011

133
134

143

0000

135

205
206
207

100

144

210

145
146
147

0000
0000
0010
0010

136

101

137

211

138

212
213

104
105

150

0000

140

151

0011

141

106

152
153

0010
0000

142

87
88
89
90
91

93
94
95

102

103

107

119

139

143

A-10

214
215
216
217

0001

0000
0000
0000
0001

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001

0000
0001

0000

Table A-3 (Cont)

ROM Pattern Table
(XTRA ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

180

0001

144

220

0000
0000
0000

145

221

0000
0000

146

222

0011

183

264
265
266
267

147

223

0000

0000
0000

148

0000
0010

181

182

184

270

185

271

186

272
273

0001

150

0000

151

224
225
226
227

0000
0000
0000
0000

152

230

153

231

154

191

274
275
276
277

232
233

0000
0000
0000
0000

192

300
301

194

302
303

0000
0000
0010
0010

156

193

159

234
235
236
237

0000
0010
0000
0010

199

304
305
306
307

0010
0010
0010
0000

200

310

0000

164

201

311

0001

165

202
203

312
313

0011

166

0010

204
205

314
315
316
317

187

188
189
190

195
196
197

198

206
207
208
209
210
211

212

213
214
215

149

155

157

158

0001
0001

160

240

161

241

162

242
243

0000
0000
0000
0000

167

244
245
246
247

0000
0000
0000
0000

0000

168

250

0001

169

251

0001

170

0010

171

252
253

0000
0000
0010
0000

320

0000

172

321

0001

173

322
323

0000
0000

174

324
325
326
327

163

0011

175

254
255
256
257

0001

176

260

0011

177

261

0001

178

0000

179

262
263

0000
0000
0000
0000

A-11

0000
0010
0000

Table A-3 (Cont)

ROM Pattern Table
(XTRA ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

0000
0000
0000
0000

Location

Data

Location

216

330

0000

236

217

331

0011

237

218

332
333

0001

238

0000

239

354
355
356
357

334
335
336
337

0000
0010
0010
0000

240

360

241

361

242

362

0000
0000
0000

243

363

0001

224
225
226
227

340

0000
0000

342
343

364
365
366
367

0000

0011

244
245
246
247

228
229
230

0001

248
249
250

370

0000
0000

231

344
345
346
347

232

350

233
234
235

351

0000
0000
0000
0000

219

220
221

222
223

341

352
353

0011

0010
0000

251

252

253
254
255
-

A-12

371

0001

0000
0000

372
373

0001

374
375
376
377

0010
0000
0000
0000

0000

VT8-E High-Speed Video Display Terminal

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FIRST CLASS
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