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December 1971

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OCR Text

Equipment Corporation
Maynard, Massachusetts
Digital

RJDI^DQSII
UllUUliUU

DEC-8E-HR2B-D-KM8

KM8-E MEMORY EXTENSION
and TIME-SHARE OPTION MANUAL

The information in
final form, a part

this preliminary

manual will become, in its

of the PDP-8 IE. Maintenance Manual, Volume 2.

PRELIMINARY

The material in this manual is for infoimational purposes

and

subject

to change

without notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDP

FUPCHIP

OMNIBUS

DIGITAL

DECTAPE

(_UNIt(Ni:5

Page

QFrTTOM

TKiTpnniirTinM

1.0

Memory Extension and Time Share General Description

1.1

Memory Extension General Description

1.1.1

The Memory Extension

Time-Share General Description

Extended Memory and Time-Share Summary

Software

Companion Documents

1.3
1

1.5

SECTION 2

INSTALLATION AND CHECKOUT

2.0

General Requirements

2.1

Installation

2.2

Checkout

SECTION 3

SYSTEM DESCRIPTION

3.0

Introduction

3.1

Block Diagram Description

3.1.1

Control Logic

3.1 .2

Instruction Field Registers and Controls

3.1.3

Interrupt Buffer A

3.1 .4

Data Field Register and Controls

3.1.5

Inten-upt Buffer B

3.1 .6

Extended Memory Addressing Output Control

3.2

Operating Functions

3.2.1

Status Operation

3.2.2

Interrupt Buffer Transfer to Memory and Restoration

3.2.3

Instruction Field Register Loading Operation

3.2.4

Time-Share Operation of the System

SECTION 4

DETAILED LOGIC DESCRIPTION

SECTION 5

MAINTENANCE

SECTION 6

SPARES

ILLUSTRATIONS
Figure

No.

Title

Page

Memory Extension Simplified Block Diagram

Typical Time-Share System

Memory Extension & Time Share Control Block Diagram

Extended Memory Addressing Flow Diagram

IF and

DF Displayed Status During TSl

Interrupt Buffer Transfer to Memory and Restoration

Flow Diagram

Interrupt Buffer Transfer to Memory and Restoration

Instruction Register Loading Flow Diagram

TABLES
Table No.

Title

Page

KM8-E Extended Memory and Time Share Option
Instructions

SECTION 1
1

INTRODUCTION

MEMORY EXTENSION AND TIME SHARE GENERAL DESCRIPTION

The KM8-E option generates a three-bit address for the extended memory address lines allowing the
use of more than 4K

memory and when required is used as a prerequisite in a time sharing system.

All logic is contained on one

OMNIBUS.

QUAD size module designated M837 which plugs directly into the

All signals entering and leaving the module are via the OMNIBUS.

MEMORY D<TENSION GENERAL DESCRIPTION

1.1

The Memory Extension hardware is a requirement whenever more than 4K of memory is to be addressed.
Except for Data Break devices, the Memory Extension is the only means by which extended memory
addresses can be applied to the three extended memory address lines called

divided into 4K fields starting with field

memory is employed.

for the basic 4K

EMA 0-2. Memory is

memory up to field 7 when up to 32K

Each 4K memory receives and decodes the EMA signals.

dressing capability of up to 32,768 memory locations.

This provides the ad-

There are two types of fields - the Instruction

Field (which acts as an extension to the PC and direct argument addresses) and the Data Field (which

augments the address of indirectly obtained arguments).
for instructions and a different field for data,

When the programmer desires to use one field

he directs the corresponding field address to either the

Instruction Field Register or the Data Field Register contained on the KM8-E option.
dresses are applied to the

EMA lines by specific instructions and conditional logic.

The field adSafeguards ore

provided so that during unplanned events such as interrupts and data breaks, no field addresses are
lost.

Program instructions allow any field address to be stored.

This is significantly important to the

programmer desiring to nest interrupts on time-share.

1.1.1

The Memory Extension

A simplified block diagram showing the basic transfer paths dealing with memory addressing and field
addressing is shown in Figure 1
selected.
its

The KM8-E is the only route by which fields above field

may be

The only exception to this is the data break device which has the capability of selecting

own memory field. The programmer has two methods by which memory fields may be selected. One

method is via the Console Switch Register and the second method is via an lOT instruction.
event, the field information is loaded into the appropriate register in the extension control

In either
.

The ex-

tension control automatically responds to the appropriate instructions and major states by placing the

contents of the correct field register onto the EMA lines.

FROM
DATA

BREAK

DECODER

EMA BITS
I

EMAa MA

4K MEM
FIELD
FIELD
FIELD

EMA

MEMORY
EXTENSION

FIELD

FIELD 5

7^ DATA BUS

FIELD 6
FIELD 7

Y>
PROCESSOR

i>
IMING

Figure 1

1.2

MEMORY
CONTROL

;

Memory Extension Simplified Block Diagram

TIME-SHARE GENERAL DESCRIPTION

The Time Share portion of the KM8-E is used only when a Time Sharing system Is to be employed. The

KM8-E module contains a jumper in the Inhibit Logic which prevents the operation of the time share
function.

Therefore, unless this jumper is to be removed from the module, the reader need not be

concerned with the time share description in this manual

The KM8-E Memory Extension and Time Share option provides the necessary additional hardware for a
general purpose time sharing system.

This option, coupled with a time sharing program, such as TSE,

and 8K or more of core, allows up to 24 users to independently run programs such that the appearance
is

created that each user has the computer to himself.

As a system, the user can be considered operating in one of three levels: a) not logged-in level,
b) monitor level, and c) user level.
to the system

the KL8-E Teleprinter Control.

trolling the operation

processor

A typical system is illustrated in Figure 2.

The user interface

The monitor program performs a dominant role in con-

between the processor and the KM8-E option and between the users and the

I
I

_1_L_
USER 3
DEVICE CODE
(34,35)

TIME-SHARE USERS
(UP TO 24 USERS)

Figure 2

Typical Time-Share System

Monitor is a complex of subprograms used to coordinate the operations of various programs and user
consoles.

Monitor allocates the time and services of the computer to various users; it grants a slice

of processing (computing) time to each job, and schedules jobs in sequential order to make the most
use out of the mass storage device.

Monitor handles user requests for hardware operations (reader,

punch etc.), swaps (moves) programs between memory and mass storage, and manages the user's
private files.

Thus, the primary time sharing capability is provided by the system monitor and the

PDP-8/E processor.
is

However, certain additional hardware not provided by the PDP-8/E processor

required to accommodate the special requirements of time sharing and extended addressing capa-

bility.

For more information on the monitor and user programming, refer to Chapter 10 of Introduction to

Programming - Digital Equipment Corporation.

EXTENDED MEMORY AND TIME-SHARE SUMMARY

As a memory extension control, the KM8-E provides:

the hardware to allow the programmable selection of the extended memory field (fields 1
through 7); allowing the extended addressing capability of the processor from a basic sys-

tem of 4096 addresses to an extended memory system up to 32,768 addresses,
b.

the hardware to prevent an interrupt or data break from interferring with the extended

addressing scheme,
c.

the hardware to save and restore a field return address.

As a time-shore control, the KM8-E provides:
a.

the hardware to distinguish between user and monitor modes,

the hardware to trap certain instructions, causing an interrupt and placing the time-share

system in monitor mode,
c.

1.4

the ability to establish user mode.

SOFTWARE

The following programs are used in the operation of time sharing and memory extension operations:
a.

System Programs
1

TSE Time-Sharing Monitor (DEG-T8-MRFB)

TSE (Time Sharing System for the PDP-8/E computer) is a general purpose, stand-alone,
time-shoring system, TSE offers each of up to 24 users a comprehensive library of
programs that provide facilities for compiling, assembling, editing, loading, saving,
calling, debugging, and running user programs on-line.
b.

Diagnostic Programs
1

Extended Memory Address Test (MAINDEC-8E-D1FA)
This program tests all of memory (up to 32K) not occupied by the program to verify
that each location can be uniquely addressed.

Extended Memory Checkerboard (MAINDEC-8E-D1BA)
This diagnostic program is designed to provide worst-case half-select noise conditions
in order to determine the operational status of core memory. The patterns generate
worst-case noise conditions in all used fields of a PDP-8/E equipped with at least

8K of core memory.
3.

Extended Memory Control and Time Share Test (MAINDEC-8E-D1HA)
This program tests the Extended Memory Control and Time Share Option logic for
proper operation. The program exercises and tests the i.">ntrol lOT's Time-Share
instruction trapping, the ability to address all field, program interrupt, and auto-

index.

1.5

COMPANION DOCUMENTS

The following documents and publications are necessary in the operation, installation, and maintenance of this option:

DEC PDP-8/E & PDP-8/M Smai! Computer Handbook - 1972

PDP-8/E Maintenance Manual - Volume 1

DEC Introduction to Programming

DEC Engineering drawing. Memory Extension and Time Share option, number KM8-E

Extended Memory Address Test, MAINDEC-8E-D1FA-D

Extended Memory Control and Time Share Test, MAINDEC-8E-D2HA-D

INSTALLATION AND CHECKOUT

SECTION 2
2.0

GENERAL REQUIREMENTS

The KM8-E Memory Extension and Time Share Option is installed by on-site DEC Field Service
Personnel.

No attempt should be mode by customers to unpack, inspect, install, checkout, or service

the equipment.

2.1

INSTALLATION

Perform the following procedures to install the KM8-E option:

2.2

1 .

Remove the module from the shipping container,

Inspect the module for any apparent damage,

Connect the module to a convenient OMNIBUS slot.

CHECKOUT

Perform the following procedures to checkout the KM8-E option:
1 .

Verify that the extended memory modules have been installed,
Verify that the con-esponding jumpers have been installed to reflect the appropriate

memory fields,
3.

Perform acceptance tests provided in Paragraph 2.3, Chapter 2 of Volume 1,

Load MAINDEC-8E-D1FA Extended Memory Address Test.

This program tests all of

memory (up to 32K) not occupied by the program to verify that each location can
be uniquely addressed.
5.

Load MAINDEC-8E-D1BA. This diagnostic program provides worst-case half-select
noise conditions and verifies the operational status of core memory.

Load MAINDEC-8E-D1HA Extended Memory Control and Time Share Test. This program tests the Extended Memory Control and Time-Share option logic for proper
operation. The program exercises and tests the control lOT's, Time-Share instruction

trapping,

(if time-share is

interrupt,

and auto-index.

implemented) the ability to address all fields- rvonrnm

Moke proper entry on user's log that the acceptance test for the KM8-E option was
performed satisfactorily.

SECTION 3
3.0

SYSTEM DESCRIPTION

INTRODUCTION

The system description of the Memory Extension and Time Share option is given in terms of the
functional operation.

From the functional point of view, instructions which make either the Memory

Extension or Time Share portion do something must be considered as well as the philosophy of why the

The system description is therefore, a composite treatment of the hardware,

events happen as they do.

represented in block diagram form, and of the flow of events, represented in flow diagram form.

The

events as they happen in the Memory Extension and Time Share option are fully considered and the

events within the processor are only partially considered.

Such areas as Major Register gating and

how the processor functions are completely described in Volume 1 of this Maintenance Manual.

3.1

BLOCK DIAGRAM DESCRIPTION

A block diagram representing all of the functional elements of the Memory extension and Time Share
option is illustrated in Figure 3.

The logic con be considered divided into three groups - the control

(located on the left portion of the illustration), the Instruction Field Registers (located in the center
of the illustration) and the Data Field Registers (located in the far right of the illustration).

The only

interface is the OMNIBUS.

Therefore, all signals entering and leaving the block diagram are directed

from and to the OMNIBUS.

Data paths between the Memory Extension and Time Share option and the

processor is via the DATA BUS.

Data is directed to the console status indicators via the DATA BUS

during TS1 for the purpose of informing the operator of which instruction and data fields have been
addressed.

When the Data Field and/or the Instruction Field are to be stored in memory, the data

path is the DATA BUS to the AC register.

A DCA instruction is then used to store the information in

memory. The data paths between the processor and the Memory Extension and Time Share option is
via the DATA BUS or the

MD lines.

Special inhibiting features are designed into this option.

For example, during a data break operation

where some peripheral such as a disk is being operated, control lines such as CPMA Disable prevent
the transmission of data to the EMA lines.

For the case of Programmed Interrupt, the logic provides

the means of holding back an interrupt until a CIF,

RMF, or RTF instruction ..as been completely

processed

Another design feature is trap logic that signals monitor whenever certain instructions are used by the
user.

•

«.

IRDFtniFtniBIU

—

«'"',

TR.I.

'^"ToVi'c"""
L

I"
'

MTlflLIZE

CIMT.rP

—

D CONT

'OWER OK

Figure 3

Memory Extension & Time Share Control System Block Diagram

3.1.1

Control Logic

The control logic (refer to Figure 3) for the Memory Extension and Time Share option contains elements
similar to most I/O devices.

These are the Device Selector Logic, Operations Decoders, the CI, INT

RQST and SKIP signal lines.

Therefore, before the operation of this option begins, an lOT instruction

addressed to this option is required.

The INT RQST and SKIP lines are directly controlled by the USER

INT flip-flop which functions to detect a TRAP signal
detected.

This signals monitor that a TRAP has been

Monitor evaluates and takes appropriate action.

in the processor to prevent the processor

Inhibit flip-flop

The USER MODE L control signal is used

from responding to HLT,

OSR and lOT instructions. The Int

serves to ground the INT IN PROG line, thereby preventing an interrupt fi-om occur-

ring whenever instruction field changes are being processed.

For the user not desiring to use the Time Share portion of the option, a simple jumper on the module

prevents the User Flag from being loaded.

Share option are given in Table 1.

The instructions used with the Memory Extension and Time

For detailed explanation of each instruction, refer to the KM8-E

memory option description in Chapter 7 of the PDP-8/E and PDP-8/M Small Computer Handbook - 1972.

Table 1

KM8-E Extended Memory and Time Share Option Instructions

MEMORY EXTENSION OPERATIONS
Data Field and Instruction Field Operations

RMF

(Restore

RIB

(Read Interrupt Buffer)

Memory Field)

Data Field Operations

CDF

(Change to Data Field)

RDF

(Read Data Field)
Instruction Field Operations

RIF

(Read Instruction Field)

CIF

(Change to Instruction Field)

FLAG OPERATIONS

GTF
RTF

(Get The Flags)
(Restore The Flags)

TIME SHARE OPERATIONS

CINT
SI NT
CUF
SUF

(Clear User Interrupt)
(Skip on User Interrupt)

(Clear User Flag)
(Set User Flag)

3.1.2

Instruction Field Registers and Controls

The Instruction Field Registers and Controls function to receive new instruction field from any one of
r\i.

!•-_ I\ niATA niif^

the Instruction Buffer Register and the Instruction Field Register.

The output lines of the Instruction

Field Register are connected to the Extended Address Output Multiplexer and when selected address
the Instruction Field by means of a combination of 3 bits on the EMA lines.

The simplified blocks (see Figure 3), concerned with the Instruction Field Register and Instruction
Field Operation represents the flow of data, the necessary gating and the primary control signals to

enable the gating, loading, clocking, etc.

They function to select either the Save Field, the DATA

BUS, or the Memory Data Lines as an input and output this information to either the Extended Address
Output Multiplexer or to the DATA BUS.
tration.

The flow of data is from the bottom to the top of the illus-

When the contents of the Interrupt Buffer are transferred to the Instruction Field Register, a

RMF instruction gates the Save Field bits through the Instruction Field Multiplexer. When the contents of the Instruction Register was previously stored in some memory location, the CIF instruction

gates bits MD6-8 through the Instruction Field Multiplexer.

The DATA BUS Receiver Gates function to receive the data from the AC Register or from the console
Switch Register.

During TS3 of the FETCH state, the contents of the AC are applied to the DATA BUS

while the KM8-E Operations Decoder is decoding the RTF instruction.
into the Instruction Buffer Input OR Gates.

RTF immediately gates bits 5-8

This information may have been fetched from memory dur-

ing the previous memory cycle or may have been inputted from the console Switch Register.

The contents of either the MD lines or the Save Field are gated through the Instruction Field Multiplexer by instruction RMF or CIF.

The Instruction Buffer Input OR Gates in turn apply either Data

5-8, MD6-8 or the Save Field to the Instruction Buffer Register and applies the User Flag obtained
from the Save Field to the User Buffer.

The purpose of the Instruction Buffer is to prevent the logic

from prematurely loading the Instruction Field Register.

If a

CIF, RTF or RMF instruction is issued, the actual change of field does not take place until the

next JMP instruction has been completed or until the Execute cycle of a JMS instruction has been
entered

The new Instruction Field is first loaded into the Instruction Buffer and then the transfer is made from
the Instruction Buffer to the Instruction Register.

It is

loaded at TP4 so that memory is not disturbed.

Although data is available for input to the Instruction Buffer Register and the User Buffer, loading does
not occur until the loading lines are asserted.

For loading the Instruction Buffer, signal line KEY

CONT must be grounded or one of the three loading instructions - RTF, CIF, RMF must be asserted

(grounded) and clocked in by TP3.

Manual loading of data at the console Switch Register creates

LD ADDR for the Instruction Buffer Clock input and KEY CONT for the buffer loading.

Bits IF 0-2

representing one of eight possible instruction fields ore on the buffer output lines when the buffer is

loaded.

The Instruction Field Input logic receives IF 0-2 and the User Flag.

0-2 bits are then

OR'd with DATA 5-8 unless the operator is manually loading data into the Switch Register or an RTF
instruction is executed.

These conditions allow only DATA 5-8 to enter the Instruction Field Register.

The User Flag is inhibited if the TIME SHARE DIS signol is asserted.

The program loading of the Instruction Field Register is accomplished by a directly addressed JMP or

JMS instruction at the end of FETCH or by a JMP or JMS at the end of DEFER or by an RTF instruction.
The manual loading is accomplished by signal KEY CONT developed when the operator loads data into
the console switch register.

The clocking for the programmed loading occurs at TP4 and for manual

input occurs any time.

Once the Instruction Field Register is loaded, the contents are ready to be loaded into either the
Extended Address Output Multiplexer or the Interrupt Buffer.

3.1.3

Interrupt Buffer A

The Interrupt Buffer A functions to save the contents of the Instruction Field when an interrupt occurs.
Signal INT IN PROG H loads the User Flag and IF 0-2 bits at TP4.

When the interrupt has been

serviced and the Memory Extension is again activated, the contents of the Interrupt Buffer are inputted
to the Instruction Field Multiplexer by an RMF instruction and the field change sequence of events will

be repeated.

Should the programmer wish to nest inten-upts, he may store the contents of the Interrupt

Buffer using the GTF instruction (or RIB instruction).

The machine may be restored to its original

condition using the RTF (or CIF and CDF) instruction.

3.1 .4

Data Field Register and Controls

The Data Field Register and controls function to receive a new data field from any one of three
sources:

a) Memory Data Lines; b)

DATA BUS; c) the Interrupt Buffer. The output lines of the Data

Field Register are connected to the Extended Address Output Multiplexer and when selected address
the Data Field by means of a combination of 3 bits on the EMA lines.

The simplified blocks (see Figure 3) concerned with the Data Field Register and Data Field Register
operation represent the flow of data, the necessary gating and the primary control signals to enable
the gating, loading, clocking, etc.

They function to select either the Save Field, the DATA BUS,

or the Memory Data Lines as an input and output this information to the

EMA lines or the DATA BUS.

The flow of dat-a is from the bottom to the top of the illustration.

When the contents of the Internet

Buffer are transferred to the Data Field Register, a RMF (Restore Memory Field) instruction gates the

Save Field bits through the Data Field Control Multiplexer,
struction is executed, bits

When a CDF (Change Data Field) in-

MD 6-8 are gated through the Data Field Control Multiplexer.

The DATA BUS Receiver Gates receive the data from the AC Register or from the Console Switch
Register.

During TS3 of the FETCH state, the contents of the AC are applied to the DATA BUS while

the KM8-E Flag Instruction Decoder is decoding the RTF instruction.

RTF gates bits 9 through 11 into

the Data Field Register.

The contents of either the MD lines or the Interrupt Buffer (RMF instruction) are gated through the
Data Field control Multiplexer.

3.1.5

At TP3, the new Data Field is loaded into the Data Field Register.

Interrupt Buffer B

The Interrupt Buffer B saves the contents of the Data Field whenever an Interrupt occurs.

Signal

INT IN PROG H loads the Data Field bits DF 0-2 at TP4. When the interrupt has been serviced and
the memory extension is to be activated, the Data Field is restored to the Data Field Register by
instruction RMF.

3.1 .6

Extended Memory Addressing Output Control

The three EMA 0-2 lines address any one of 8 memory fields. When any combination of these lines
are grounded, the result is a selected memory field.

The Extended Address Output Multiplexer with

th« DF EN flip-flop determines whether the EMA bits will be the data field or the instruction field
(see Figure 3).
is

A simplified flow diagram illustrating the conditions which determine the selection

shown in Figure 4.

Beginning at the top of the flow diagram, the logic tests for a JMP or JMS instruction.

JMS instruction is activated, the Instruction Field may be addressed.
DEFER state.

If the

JMP or

Otherwise, the logic tests the

The DF EN flip-flop is clocked by TP4 or signal LD ADDRESS if the field is applied at

the console switches.

If a

applied to the EMA lines.

data break is in operation, the extended address will not at that time be

As soon as data break ends, the Extended Address Output Multiplexer will

be enabled to either gate the Instruction Field or Data Field bits out to the EMA lines and thereby
select a memory field.

The rule for usage of the Data Field is as follows:

the current instruction is an AND, TAD, ISZ,

DCA or EAE instruction, and if the processor is currently in the DEFER state, the next EXECUTE cycle
will use the Data Field.

All other machine cycles which are not Data Break cycles use the Instruction

Field.
11

YES

JMP

POSSIBLE
INSTRUCTION
FIELD

CHANGE

y^ DEFER \. NO
\.

STATE

Jyes
1

TO INPUT OF DF
EN F/F

IFO-2
EMAO-2

Figure 4

TO INPUT OF DF

EN F/F

YES

DFO-2
EMAO-2

Extended Memory Addressing Flow Diagram

Notice that the DEFER state is tested at the end of the current processor cycle. The decision
of
whether the processor is to go to the EXECUTE state or the FETCH state is clearly indicated in
Finiirft .'5—17 in
if the

Vrtliimo

^f fkle KAstir^i-^w^j^^^^ AAm«.»I

-f _i_ _•_•_

next state is to be EXECUTE or FETCH determine if the Instruction Field or Data Field

to be

addressed

OPERATING FUNCTIONS

3.2

The following paragraphs provide some examples of the KM8-E operation.

These descriptions reflect

the flow of events for illustrative purposes and do not reflect the method by which

this option

be programmed.

3.2.1

Status Operation

Occasionally the user will want to select the STATUS position on the console selector switch.
he does this, signal IND will be generated at the start of TSl and remain until TS2,
used in the Memory Extension and Time Share logic to gate the contents of the IF

through the Output Multiplexers and on to the DATA BUS.
in Figure
1

When

Signal IND is

and DF Registers

Refer to the system block diagram given

3 and to Figure 5 for the bit arrangement illustrating the status.

Only bits 3 and 5 through

1 represent the status of the Memory Extension and Time Share control

Bit 3 represents the interrupt status of the Interrupt Inhibit flip-flop.

at TP3 whenever an RTF,

JMP or JMS instruction occurs.
interrupt.

Signal INT INHIBIT

generated

KEY CONT, CIF, or RMF signal is asserted and negated at TP3 whenever a
This prevents any memory field from being lost during a program

Thus, whenever bit 3 of the status indicator is illuminated, indicating a program
interrupt

inhibiting condition, the processor has not started a JMP or JMS instruction
since the last Instruction

Field change inslruction was performed.

When the IF and DF registers are loaded and signal INT IN

PROG H is asserted, the contents of the registers are then loaded into the Interrupt Buffers at TP4.
Bits 5 through 8 represent the contents of the Instruction Field
in the IF Register and bits 9 through

represent the contents of the Data Field in the (DF) Register.

3.2.2

Interrupt Buffer Transfer to Memory and Restoration

A simplified explanation of how the Interrupt Buffers could be stored in memory and restored to the
Instruction Field and Data Field Registers is illustrated in Figure 6 and Figure

A Read Interrupt

Buffer (RIB) or Get Flags (GTF) instruction creates the necessary gating signals
to allow the Instruction

Field and Data Field to pass through the corresponding output Multiplexers
Bus.

and be applied to the Data

The same instruction grounds the CI line which causes the contents of the DATA BUS to

be loaded

X X X

NO
INT

IFO

IF1

IF2

DFO

DFt

DF2

t
INT
INH

INSTRUCTION FIELD

DATA FIELD
1

IND

Figure 5

IF and

DF Displayed Status During TS1

ACTION

LOAD OUTPUT
MULTIPLEXERS

RESULT

—DATA BUS
—AC

GROUND C1

DATA BUS

FETCH DCA

SAVE FIELD—*MEMORY
LOCATION X

EXIT TO
MAIN PROGRAM

WAIT FOR TADX

AC
DATA BUS
RECEIVER GATES

DATA 5-8
DATA 9-M

Figure 6

fclB

— DF

Interrupt Buffer Transfer to Memory

and Restoration Flow Diagram

DF REGISTER

IF BUFFER

IFO

DFO DF1 DF2

IF2

IFl

^AC9-1I|

|aC5-8|

AC 5 -11

AC—MEM

LINK
*

»•

INT

BUS

INT

BUFFER 8 DF REG

ION

SUF

SFO

SF1

*
3

INT

SF2

INTERRUPT BUFFER A

SUF

CO NT

SF3

SF4

SF5

SFO

SF1

SF2

INTERRUPT BUFFER B

SF3

SF4

NOT GENERATED BY KM8-E

Figure 7

Interrupt Buffer Transfer to Memory and Restoration

SF5

into the

AC Register. A DCA instruction transfers the contents of the AC Register to the corresponding

addressed memory location.

—

The next time the field is to be addressed, the TAD instruction returns

the data to the AC
Ranicfar nnA
~M~..,. iiU.
_ PTP 'nc¥r,,^H,^
._ .._,j
_.._ nn
,., W.-..W.. u,,w"3 MIS
.

Instruction Buffer and Data Field Registers at TP3.

ir-_ Lfi.. ...I.I
t=u!i!sspu!!a!ng Dirs ro ce ioaasa snTo rns

The addition of PC, AC and MQ handling will

allow nesting of interrupts.

3.2.3

Instruction Field Register Loading Operation

The Instruction Field Register Loading operation is illustrated in the Instruction Field Register
Flow Diagram given in Figure 8.

of the blocks contain a status of "yes".

operator depresses the EXTD ADDR
If the

For example, signal KEY

CONT is developed whenever the

LOAD key. The corresponding clock input is signal LD ADDR.

loading of the Instruction Field Register is under program control, the next 3 conditions

are

A restore flag instruction will allow the Instruction Field Register to be loaded at TP4. Other-

tested.

wise the major states are tested. If the processor is in the FETCH state and not doing
signal

The first four decision blocks represent a "go" condition if any one

an RTF instruction,

JMP or JMS is tested and finally MD3L is tested. When MD3H is present (indicating direct ad-

dressing), the Instruction Field Register will be loaded at TP4. Otherwise, a DEFER state
with JMP or

JMS is tested. Note that the Instruction Field Register will not be loaded during a Data Break. The
clock input is set at TP4 to assure that there is no address mixup during the current memory

3.2.4

cycle.

Time-Share Operation of the System

Because much of the logic is shared between the time share operation and the memory extension
tion,

The time share portion operates in two modes as denoted by the User Flag (UF) flip-flop
system block diagram presented in Figure 3).
is

opera-

may not be obvious what logic is specifically dedicated to the time share function.

When the UF flip-flop is in the logic 1 state, the systeim

operating in the user mode and a user program is running in the central processor.

flip-flop is in the logic

(refer to the

When the UF

state, the system is operating in the executive mode and the
time-sharing

monitor is in control of the central processor.

The four instructions developed by the Time-Share operations Decoder are used by the
executive mode and are never used by a user program.

monitor in the

The Trap Logic is a monitoring device to assure

the system that the user is programming valid instructions.

When signal TRAP is developed, both the

INT RQST and the SKIP lines are grounded. Monitor then takes over and examines the
invalid instruction and determines what action must be taken

The User Flag (UF) also plays an important role in monitoring for valid instructions.
a one, signal USER MODE L is developed and the grounded line which goes to

When the UF is

the processor inhibits

DEFER

YES

LOAD INSTRUCTION
FIELD REGISTER

Figure 8

Instruction Register Loading Flow Diagram

signal

STOP and signal I/O PAUSE. The processor is operating in the executive mode during the time

that memory extension or time-sharing instructions are being processed.

an SUF instruction has been completed.

The User Mode begins when

This sets the User Buffer flip-flop and inhibits the processor

inten-upt until the next JMP or JMS instruction.

At the conclusion of either of these instructions,

the User Flag is transfen-ed into the Instruction Field Register.

At that time, the User Flag signal is

applied to the Processor I/O Control Output Gating where signal USER MODE L is developed.

The following is a summary concerning valid and trapped instructions:

FUNCTION NORMALLY:

AND
TAD
ISZ

DCA
JMP
JMS
most OPERATES

TRAPPED INSTRUCTIONS:
HLT
Monitor Return. Machine must not stop because all users
would be shut down.

OSR, LAS

A user does not

Requires special action via Teleprinter.

have his own Switch Register.

lOT

Requires interpretation (usually a device code change) by
the monitor.

For example, any user can use a KSF in-

struction (octal 6031).

If executed

by the computer, this

instruction would test the flag of tfie console TTY.

(the

However, the monitor alters this instruction by
changing the middle 6 bits to the device code of the User's
TTY.
operator).

SECTION 4

DETAILED LOGIC DESCRIPTION

This information will be supplied at a later date.

SECTION 5

MAINTENANCE

The general procedures concerning preventive and corrective maintenance are given in Volume 1,
Chapter 4 of the Maintenance Manual.

When corrective Maintenance is required, the technician

should use the maintenance programs given in Section 2 of this option manual to determine the nature
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locations and pin numbers.

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Test points have been provided on the module to facilitate troubleshooting.

SECTION 6

SPARES

This information will be supplied at a later date.

Equipment Corporation
Maynard, Massachusetts

Digital

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