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DEC-8E-HR2B-D

December 1971

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OCR Text

Digital

Equipment Corporation

l\/laynard, l\^assacliusetts

DEC-8E-HR2B-D-KA8

POSITIVE I/O BUS

INTERFACE OPTION

The information in this preliminary manual will become, in its
final form, a part of the PDP-8/E Maintenance Manual,

PRELIMINARY

Volume 2.

1st

Preliminary Edition, August 1971

The material in this manual is for informational purposes

and

subject to change

without notice.

The following are trademarks of Digital Equipment
Corporation, Maynord, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

CONTENTS
Section

Page

1.0

Intrcxduction

2.0

Block Diagram

3.0

Detailed Logic

3.1

BIOP Pulse Generator Logic

3.2

BMB Buffers/Inverters

3.3

lOP Timing Logic

3.4

Data Gating Logic

3.5

Skip Counter Logic

4.0

Maintenance

5.0

Spare Parts

ILLUSTRATIONS
Figure No.

Title

Page

2-1

Block Diagram, Positive I/O Bus Interface

3-1

BIOP Pulse Generator Logic

3-2

BMB BuiTers/lnverters

3-3

lOP Timing Logic

3-4

Waveforms, lOP Timing Logic

3-5

Data Gating Logic

3-6

Skip Logic

3-7

Timing, Skip Logic Application

TABLES
Table No.
4-1

Title

Page

KA8-E Cable Information

1.0

INTRODUCTION

The Positive I/O Bus Interface, KA8-E, permits use of a PDP-8/I or PDP-8/L-type peripheral with
a data break device, a Data Break interface,

KD8-E, must also be

the PDP-8/E.

If the peripheral

in the system.

The concept of data transfers and the interrelationship of the Positive l/O Bus Interface,

the Data Break Interface, and the OMNIBUS are explained in Chapters 6 and 10 of the Small Computer

Handbook - 1971.

A detailed discussion of the CPU operation during a programmed I/O transfer is

presented in Volume 1, Chapter 3, Section 6 of this maintenance manual.

The reader should be

thoroughly familiar with this referenced information to benefit from the detailed logic discussion presented in this chapter.

2.0

BLOCK DIAGRAM

Figure 2-1

a functional block diagram of the Positive l/O Bus interface.

When an lOT instruction

has been placed on the OMNIBUS MD lines, the I/O PAUSE L signal is asserted by the CPU Timing

Generator.

INTERNAL I/O L is not asserted by an internal peripheral, I/O PAUSE L causes the

interface lOP Timing

at TP3 time.

to assert the

NOT LAST TRANSFER L signal.

Thus, CPU timing is suspended

Simultaneously, lOP timing is initiated and the lOP signal that is subsequently generated

enables the BIOP Pulse Generator to produce one or more pulses.
eral in conjunction with

These pulses are used by the periph-

BMB bits to decode lOT instructions.

The lOT instruction can clear and set flags and registers within the peripheral , or it can direct a data

word transfer or a SKIP operation.

Data words are transferred between the Data Gating logic and the

CPU via the DATA 0-11 lines; between the peripheral and Data Gating, the data path depends on the
direction of transfer, as shown in the block diagram.

The OMNIBUS C-lines are asserted within the

Data Gating logic in combinations that depend on the type and direction of transfer.

If a

Skip operation is directed by the lOT instruction, the peripheral asserts the external SKIP L signal

when conditions warrant,
line, or both,

lOP Timing clocks the Skip Counter and either the DATA 10 or DATA 11

is activated.

EXTERNAL BUS
BMB()0-11

BIOP 1, 2, 4

AC CL EAR

SKIP L

BAC 00 -U

ACOO--H
1

DATA

GATING
LOGIC

DATA

SKIP

DATA

COUNTER

;

BUFFERS/

INVERTERS
i

BIOP
PULSE
GENERATOR

,IOP

lOP
TIMING

STOP L

MD9 -H
'

MDO-11

I/O
PAUSE L

NOT
LAST
TRANSFER L

TP3

BUS
STROBE

C2L

DATAO-11

OMNIBUS

Figure 2-1

Block Diagram, Positive I/O Bus Interface

3.0

DETAILED LOGIC

3.1

BIOP Pulse Generator Logic

Figure 3-1 shows the BIOP pulse generator logic, which converts
pulses 4, 2,

and 1, respectively.

for enabling at TP2 time.

on any MD line conditions a corresponding NAND gate

When the NAND gate is enabled, it dc-sets a flip-flop that, in turn, con-

NAND gate.

ditions another

A logic

MD bits 9, 10, and 11 to BIOP

Simultaneously, the flip-flop causes the STOP L signal to be negated.

I/O transfer involving an external bus peripheral is in progress, the STOP L signal enables TP3

If an

to initiate the lOP Timing operation.

The lOP Timing logic (Paragraph 3.3) responds by asserting a

sianal
the- flio-fioo-conditioned
flOP)
-^
-/ that enables
|X
-

NAND Gats.
—

The resultina
sinnal is buffered and
is ~ ^
-

designated BIOP4, BIOP2, or BIOPl.

For example,

MD bit 9

a logic

are cleared at each TPl time).

flip-flop I04 is dc-set at TP2 time (note that the lO flip-flops

1 ,

The 0-output of the flip-flop causes STOP L to be asserted and, pro-

viding the lOl and I02 flip-flops are cleared (MD bits 10 and 11 are logic 0), the 1-output conditions

NAND gate E24 for enabling by the lOP signal. When the lOP Timing asserts the lOP signal, E24
enabled and the BIOP4 pulse is generated.

The width of the pulse can be varied by adjusting a poten-

tiometer in the lOP Timing logic, thereby asserting the lOP signal for the desired amount of time (see

Paragraph 3.3).

When the lOP signal is negated, E24 is disabled. Because the output of E24 is con-

nected to the clock input of I04, the flip-flop is cleared when E24 is disabled (note that the D inputs
of the lO flip-flops are connected to ground; thus, a positive transition at a clock input clears the
flip-flop).

The 0-outpuf of I04 negates the STOP L signal and this action causes the lOP Timing

logic to terminate the l/O dialogue.

This example stipulated that

MD bits 10 and 11 were logic 0. Suppose, instead, that all three MD bits

are logic 1, All three lO flip-flops are then set at TP2. The STOP L signal
of lOl conditions EllC for enabling by the lOP signal.

both

asserted and the 1-output

Observe that the 0-output of lOl disables

NAND gate E8B and NAND gate E24. Thus, the lOP signal enables EllC first and the BIOPl

pulse is generated.

When the lOP signal is negated, EllC is disabled and lOl is cleared.

This ac-

tion removes the disabling signal from E8B; however, E24 remains disabled because the 0-output of I02
is

one of its inputs.

nal

NAND gate E8B is now conditioned for enabling by the lOP signal. When this sig-

again asserted by the lOP Timing logic, BIOP2 is generated.

removing the disabling signal from E24.

When BIOP2 ends, I02 is cleared

Now the BIOP4 pulse is generated, as detailed earlier.

Thus, the BIOP Pulse Generator logic operates in such a way that the BIOP pulses are not assigned
specific time slots.

4, or 2, or 1 ,

only one of the

MD bits

a logic 1, then the corresponding BIOP pulse, whether

generated at the first assertion of the lOP signal.

more than one MD bit is a logic

the least significant bit is selected first and its corresponding BIOP pulse is generated; the most signifi-

cant bit is selected last.

lOP
(FROM lOP TIMING)

EUA

jO-

-BI0P4

104
E7B

BUFFER

E20

EHO p-

"-C

TO
-BIOPZ
BUFFER

102

Y>^STOP L

.ST
E20
E11B

o-C

TP2
E15

E11C

101
E6

E10

TO
-BI0P1
BUFFER

LIT

TP1-

note:
FLIP-FLOPS ore DEC 7474

(

See Volume

Appendix A

Figure 3-1

for dctoils)

BIOP Pulse Generator Logic

BMB Buffers/Inverters

3 2
=

A perrpherai uses these BIOP pulses in

The preceding section discussed the BIOP pulse generator.
conjunction with BMB bits to decode lOT instructions.

The BMB bits are derived from the OMNIBUS

MD bits, which are buffered and inverted by the interface.

Figure 3-2 shows the buffer/inverter

network

BMB bits 03-08 are used in peripheral device selection logic.
these bits are derived from the corresponding

the external peripheral.

Both the true and the false states of

MD bit; this minimizes the device selection network in

Although programmed transfer peripherals use the BMB bits only for device

selection, data break peripherals receive output (from the CPU) data via the BMB 00-11 lines.
all

Thus,

12 BMB bits are derived, as shown in Figure 3-2.

3.3

lOP Timing Logic

Figure 3-3 shows the lOP Timing logic, which determines the duration of BIOP pulses and the separation between individual pulses,

more than one is programmed.

Separation and duration can be

individually varied by potentiometers that are indicated on the logic diagram and on the KA8-E etch
as lOP SEP and lOP WIDTH.

These potentiometers determine the triggered delay time of associated

one-shot multivibrators, shown as part of DEC 74123 ICs.

Briefly, the one-shots contained within a

74123 can be triggered by:
a.

a positive transition at pin 2,

if, prior to the transition, pin 1 is low and the clear (C)
input is high (for the 'B' half of the IC, substitute pin 10 and pin 9 for pin 2 and pin 1,

respectively),
b.

a negative transition at pin 1 , if, prior to the transition, pin 2 is high and C is high,

a positive transition at the C input, if, prior to the transition, pin
is

low and pin 2

high (see Appendix A for details about the DEC 74123 IC).

Figure 3-4 shows the lOP timing for a typical I/O transfer.

The lOP signal is asserted twice during

the time that l/O PAUSE is active; thus two BIOP pulses are generated by the BIOP Pulse Generator
(the identity of the BIOP pulses does not affect the waveform relationship).

The waveforms representing

SEP and WIDTH are shown for the minimum allowable triggered delay time, viz. , 200 nano-seconds for
SEP and 600 nano-seconds for WIDTH.

The potentiometer values allow these delay times to be in-

creased to five times the minimum value.

If the

Refer to both figures while studying the following description.

I/O transfer involves an external bus peripheral (INTERNAL l/O L remains negated) and the

BIOP Pulse Generator negates the STOP L signal, NAND gate E28 asserts the NOT LAST TRANSFER L
signal; this signal indicates to the CPU Tlmina Generator the imoendina interruDtion of normal timina.

At TP3 time the lOP Timing is initiated, while the CPU timing is suspended in TS3.

BMBOO

BMB01

BMB04

BMB03

BMB02

BMB06

BMB07

BMB09

BMB08

GATING FOR BITS 4-B SAME
AS FOR BIT 3

BMB10

BMB11

GATING FOR
AND 2
SAME AS FOR

BITS

8MB05

GATING FOR BITS
9-n SAME AS FOR
BIT

BIT

V A A

"'A

17\

/e13\

I
I

/e13\

TO BIOP
-PULSE
GEN.

E12
7J

MDO

TjJ—CT

MDI

MD2

EZO

E20

E20
(p

y
1

M04

Figure 3-2

MD5

MD6

MD7

BMB Buffers/Inverters

MD8

MD9

MD10

MD11

STOP

lOP
L

I/O PAUSE L

NOT LAST

TRANSFER L

Figure 3-3

lOP Timing Logic

^TLl

'
1

i
'

;

Mi:.!

I/O PAUSE L

111"

;

i
'

;

I'M!

^
;

,
!

NOT LAST TRANSFER L
'

STOP L

ill

;

'
i

.
:
:

;

SEP

(0)

;

i
:

100 (0)

WIDTH (0)

ZOO (1)

REST

(0)
i

STB

'I
\

(0)

.
1

lOP (BIOP)

1
1

Ml
1

1
1

BUS STROBE

Figure 3-4

Waveforms, lOP Timing Logic

;

lOP Hming begins when the SEP one-shot is triggered by the positive transition at its C-input. SEP (0)
is used

to trigger the 100 one-shot, which, in turn, triggers WIDTH.

WIDTH (0) sets the lOP fiip-fiop

and the resulting lOP signal enables the BIOP pulse generator to begin the BIOP pulse.

The STB

(Strobe) one-shot, triggered by the end of WIDTH (0), clears the lOP flip-flop; thus, the duration of

the BIOP pulse is 100 nano-seconds longer than the duration of WIDTH (0).
is generated

A BUS STROBE L signal

by STB (1) at the end of each BIOP pulse to execute the instruction represented by the

BIOP pulse (BUS STROBE L causes the AC LOAD L signal to be asserted in the CPU; see Volume 1,
Chapter 3, Section 6 for details).

When the first BIOP pulse has ended, the sequence outlined begins

anew, this time with STB(O) triggering the SEP one-shot. When the last BIOP pulse ends, the STOP L
signal

is asserted

by the BIOP pulse generator.

triggered by the next transition of 100(0).

mainder of the lOP timing.

This signal ensures that the WIDTH one-shot is not

Therefore, the lOP flip-flop remains clear through the re-

When REST(O) (the Re-start one-shot), which is triggered by the STOP L

signal transition, goes positive after 275 nano-seconds, STB is triggered again, producing a final

BUS STROBE L signal.

This

BUS STROBE terminates the I/O dialogue and reinstates the CPU timing.

The 100 one-shot is necessary for proper triggering of WIDTH.
pin 9 of WIDTH when SEP times out.
itself,

provides a negative transition at

the negative transition were supplied by the 0-output of SEP,

WIDTH would trigger at the same time as SEP. On the other hand, if the negative transition

were supplied by the 1 -output of SEP, WIDTH would trigger at TP2 time, when the STOP L signal is
negated.

Consequently, the 100 one-shot is quite important to the timing operation.

The 200 one-shot is also important to the timing logic.

Note on Figure 3-4 that the STOP L signal is

shown to have a spike that Is coincident with the trailing edge of the first BUS STROBE signal (if three

BIOP pulses were generated, there would be two spikes shown).

This spike is a representation of the

tendency of the STOP L signal to go low at the end of the lOP signal (NAND gate E8A in the BIOP
Pulse Generator becomes momentarily indecisive at this point in the timing).

The 200 one-shot

brackets this spike in time and, thus, prevents the REST one-shot from triggering prematurely.

3.4

Data Gating Logic

The data gating logic is shown in Figure 3-5.
to or from the CPU on the

During a programmed l/O transfer, data is transferred

OMNIBUS DATA 0-11 lines.

Output data (from Hie CPU) is gated from the

DATA lines through an interface buffer/inverter network (illustrated in Figure 3-5 for bits
to the external bus BAC 00-11 lines.

and 11)

the output transfer is to be accompanied by a clearing of the

CPU AC Register, the peripheral is directed (by the BIOP pulse) to assert the OMNIBUS CO L signal
TUp nerinh^ral d<^e5 this •ndirf'c*'!'-' hv nrrsiindinn thf» f>5{t6rr!ai hup. AC CLEAR linesignal causes

NAND gate E25D on the interface to assert the CO L signal.

have to be cleared, the C-lines remain negated throughout the transfer.

The AC CLEAR L

the AC Register does not

'BAcn

INT
ROST L

NOTE.

*AC

"INT

CLEAR

ROST L

*Oenoles External Bus Signoi.

Figure 3-5

Data Gating Logic

C line. Note that when a data word is transferred from the peripheral on the external bus AC 00-1
lines, the interface DATA IN L signal

lines during the

asserted by

NOR gate E29.

the data

placed on the AC

BIOP pulse (as it must be), NAND gate E25C asserts the Cl L signal.

Simultaneously,

the AC INPUTS -* DATA BUS signal gates the data onto the OMNIBUS DATA 0-1 1 lines.

The result of

these actions is an 'OR' operation of the AC contents and the data on the DATA 0-11 lines.

The

peripheral can cause a JAM input by grounding the AC CLEAR line, thereby asserting the CO L signal.

Thus, only the information on the DATA 0-11 lines is placed in the AC Register.

Note that if data

word OOOOp is transferred from the peripheral, the DATA IN L signal is not asserted.
*Uq ^^g^•l^^lQr•J;j mijcf ^[-Qiji^d the AC CLEAR line and

in sffsct-

cause

To transfer OOOOg

JAM in^ut of zeros^

These are the four types of data transfers that can be made by the PDP-8/T-type peripherals.

Another

form of I/O transfer, other than a 12-bit data word, that is, utilizes the interface SKIP logic to up-

date the CPU PC Register.

3.5

This type of transfer is discussed in Paragraph 3.5.

Skip Counter Logic

The peripheral, when directed by an lOT instruction, can cause a skip of 1 , 2, or 3 program instructions.

initiates a skip operation by grounding the external bus SKIP line.

The interface Skip logic,

shown in Figure 3-6, asserts the OMNIBUS DATA 10 and/or DATA 11 lines, depending on the number of
instruction skips required (during a SKIP operation the peripheral does not place data on the ACOO-11
lines).

At the same time, the OMNIBUS C-lines are manipulated to provide a path for the DATA bits

through the CPU ma [or register gating to the PC Register.

The DATA bits are added to the contents

of the PC register, increasing the program count in the register by

1,2, or 3.

The timing diagram of a typical skip operation is shown in Figure 3-7.
Figure 3-6 while studying the description that follows.
1

Refer to this diagram and to

The timing diagram shows that two BIOP pulses,

The imaginary peripheral that applies to this ex-

and 2, are generated during the lOT instruction.

ample decodes these 2 BIOP pulses and responds by grounding the SKIP line.
is an

Keep in mind that this

example, only, and that this imaginary peripheral does not necessarily exist.

The combination

of BIOP1 and BIOP2 can produce a variety of operations, depending on how a peripheral decodes the
pulses.

Nevertheless, when TP3 starts the lOP timing, this peripheral

by asserting SKIP L.

directed to initiate a skip operation

The SKIP line controls the D input of flip-flop E9, which is clocked when the

STB one-shot is triggered.

Because STB is triggered at the end of each BIOP pulse, E9 can be clocked

twice during lOP timing.

Note that the 100 one-shot dc-sets E9.

Thus, E9 is set at the first trigger-

ing of the 100 one-shot, or (as is shown in Figure 3-7) during a previous lOP timing cycle.

STB are triggered alternately thereafter.

100 and

Thus, E9 is alternately cleared and set, as long as SKIP L is

DATA10

CEL

A
E28A

-DAI

SKIP

-C|

T R

(

CEN

SKIP 2

-d

•

T, P.

CA1

r
D

INITIALIZE-

C
CO

o
ca

(

TP3

INTERNAL

I/O PAUSE

STOP L

SKIP L

I/O L

HM ^
I

See

Figure

3-3

for

detail.

E3A
100

E3B
STB

^ E2A

^>^

REST

BI0P2

Jl
IS

100 (0)

SKIP

2 (1)

(

REST

(0)

CEN

(0)

„n

SK P
i

DATA 11

DATA 10

Figure 3-7

Timing, Skip Logic Applicafion

asserted.
this

Each time E9 is cleared, SKIP!, the first stage of the 2-stage binary counter, is clocked.

example, the binary counter is clocked twice, indicating that two instructions are to be skipped,

SKIP2 is set at the second triggering of STB.
one-shot, enabling
it is

The C-line enable (CEN) flip-flop is dc-set by the REST

NAND gates E25 and E28B (note that CEN

clocked by STB at the same time that

dc-set by REST; the dc-input takes precedence in such a case). The assertion of C2L, while C1L

and COL are left negated, provides a path for DATAIO through major register gating to the PC Register.

C2L and BUS STROBE (generated when REST times out) assert PC LOAD L and DATA 10 is added to the
contents of the PC Register, updating it by two.
is

triggered by the trailing edge of REST (0).

Note that the SKIP line must be negated before STB
not, the binary counter is erroneously clocked one

more time.

4.0

MAINTENANCE

There are no specific maintenance procedures for the KA8-E, itself.

Each DEC peripheral that con-

nects to the KA8-E has an associated MAINDEC or exerciser program that enables the technician to

maintain both the option and the KA8-E interface.

Because all these peripherals use the one interface,

a fault in the interface can be isolated by running a number of MAINDEC programs.
result in errors,

If all

programs

one can reasonably conclude that the KA8-E is at fault.

General information concerning corrective maintenance is included in Volume 1, Chapter 4.
technician will find this material helpful.
test points,

The

The Interface schematic, E-CS-M8350, indicates important

IC locations, and pin numbers and should be used whenever maintenance is being

performed

The KA8-E connects directly to a single peripheral via three cables that are supplied with the interface
(see the Small Computer Handbook - 1971,

Chapter 10 for cabling rules and suggestions).

Each cable

connects to the Interface with a 40-pin Berg connector and to the peripheral with a DEC M953A cable
connector.

From-To information for the cable is given in Table 4-1 (the cables are identical; see

Chapter 10 of the Small Computer Handbook - 1971 for details concerning proper connection of the
cables).

5.0

SPARE PARTS

To be supplied.

Table 4-1

KA8-E Cable information

(M953A Cable Conn.)

(Berg Conn.)

Gnd
Gnd
Gnd

-D

Gnd
D2

(M953A Cable Conn.)

(Berg Conn.)

Gnd

CC
DD

Gnd

FF
JJ

Gnd

Gnd
Ml
Gnd

Gnd

Gnd
V2
Gnd
Gnd

Gnd

Pins A2, B2,

RR
SS

Ul , and VI on M953A not used.
Kl, Nl, Rl, T1,C2, F2, J2, L2, N2, R2, and U2 on M953A

Pins Al, CI, Fl,

are ground pins.

Equipment Corporation
Maynard, Massachusetts
Digital

printed

U.S.A.

SBinQSQ
yubiuyuy

MASTER DRAWING LIST
UNIT VARIATIONS

MAINTENANCE
MANUALS

m
1

TITLE

NO.

KA8-E POSITIVE l/O BUS
INTERFACE

_
X

USED

ON OPTIONS

8-71

CORPORATION

DATE l7

CHKD
K. GULICK,
ai

EQUIPMENT

DATE 1/

DRN
K. GULICK

AAyMAHU Vt*?»'>*

8-71

DATE
»,

TITLE

3-5-7
PROJ. ENG.

DATE

PROD

DATE

c/:i<

S:^

POSITIVE I/O BUS INTERFACf:

3-5-7

FIRST USED ON
SIZE

PDP8/E

< «u

SCALE

NONE

SHEET

CODE

A ML

NUMBER

KA8-E

REV

^^^TTTTTT

DRA 131

Dk 16-(325)-l048-N471

—

PRWr SET
EJ
1

CWG. NO.

REV. NO. OF

OPTION

TITLE

LET, SHEETS

NO.

—

A-PL-KA8-E-0

POSITIVE I/O BUS INTERFACE (PARTS LIST)

E-CS-M835i»'j5-l

POSITIVE. I/O

A-SP-KA.8-E-1

-BEE-

..2_..,

TITLE

ElUS

INTERFACE

KAfi-E/KOa-E MANUFACTURINQ, TEST PROCEDURE

SIZE

POSITIVE I/O BUS INTERFACB
SHECT

DRA 132
DEC IM32S)>-IOM-l-N471

CODE

A ML

NUMKR

REV.