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DEC-8E-HMM3A-C-D

December 1973

546 pages

Original

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Document:	PDP-8e Maintenance Manual Volume 3 External Bus Options
Order Number:	DEC-8E-HMM3A-C-D
Revision:
Pages:	546
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/dec-8e-hmm3a/dec-8e-hmm3a-c-d.pdf

OCR Text

external bus options

maintenance manual
volume 3

mmnm

MAINTENANCE MANUAL

VOLUME 3

For additional copies order No. DEC-SE-HIViiViSA-C-D from Direct Mail, Digital

Equipment Corporation, Maynard, Massachusetts

01754

Price:

$25.00

digital equipment corporation • nnaynard, massachusetts

1st Edition, July

1972

2ncl Printing (Rev) July 1973

The material in this manual is for informationpurposes and is subject to change without

notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

CONTENTS
Page

PART 1 CONSOLE TELEPRINTER

CHAPTER 1

LC8-E DECWRITER CONTROL
Section 1

Introduction

Section 2

Installation

Section 3

Description

Section 4

1.1

1.2
1.3
1.4

Detailed Logic

lOT DECODER LOGIC

1-3

PRINTER RECEIVE LOGIC
KEYBOARD TRANSMIT LOGIC
INT/SKIP LOGIC

1-3
,

1-7

1-8

Section 5

Maintenance

Section 6

Spare Parts

PART 2 PAPER-TAPE READER/PUNCH

CHAPTER 2

PC8-E HIGHSPEED PAPER-TAPE READER/PUNCH
Section 1

Introduction

Section 2

Installation

Section 3

Description

Section 4

2.1

2.2

2.3
2.4
2.5
2.6
2.7

2-8

2.9

2.10

Detailed Logic

lOT DECODER LOGIC

2-5

TAPE READ LOGIC
CLOCK LOGIC

2-5
2-9

READER MOTOR CONTROL LOGIC
RDR INT/SKIP LOGIC
RDR BUFFER LOGIC

2-9

2-11
2-11
2-11

TAPE STATUS LOGIC
TAPE PUNCH LOGIC
PUNCH BUFFER LOGIC
INT/SKIP LOGIC

2-16
2-18
2-18

Section 5

Maintenance

Section 6

Spare Parts

III

CONTENTS (Cont)
Page

PARTS X/Y PLOTTER
CHAPTER 3

XY8-E PLOTTER CONTROL
Section 1

Introduction

Section 2 Installation

3.1

3.2

3.3
3.4

Section 3

Block Diagram

Section 4

Detailed Logic

IDT DECODER LOGIC
TIMING LOGIC
DIRECTION TRANSFER LOGIC
INTERRUPT/SKIP LOGIC

3-3
3-5
3-5
3-5

Section 5

Maintenance

Section 6

Spare Parts

PART 4 LINE PRINTER

CHAPTER 4

4.1

4.2

LE8-E LINE PRINTER
Section 1

Introduction

Section 2

instellation

UNPACKING
CHECKOUT

4-1

4-2

Section 3

Block Diagram Description

Section 4
4.3
4.4
4.5

Detailed Logic

SELECT LOGIC
INTERRUPT LOGIC
DATA TRANSFER LOGIC

4-5
4-7

4-8

Section 5

Maintenance

Section 6

Spare Parts

CONTENTS (Cont)
Page

PART 5 DATA COMMUNICATIONS EQUIPMENT

CHAPTER 5

DP8-E SYNCHRONOUS MODEM
Section 1

Introduction

Section 2

Installation

Section 3

5.1

5.2

5.3

Block Diagram Description

TRANSMITTER-MODEM DIALOGUE
MODEM-RECEIVER DIALOGUE
DP8-E DATA BREAKS
Section 4

5.4

5-^

^'^
•

•

Detailed Logic

lOT DECODER LOGIC

5.15

CONTROL WORD LOGIC
BREAK ROST, RECEIVE LOGIC
RECEIVE DATA REGISTER LOGIC
BREAK ROST, TRANSMIT LOGIC
TRANSMIT DATA REGISTER LOGIC
BRK ROST LOGIC
BREAK GRANT LOGIC
ACCESS ADDRESS COUNTER LOGIC
CURRENT/ACCESS ADDRESS REGISTER LOGIC
LOAD FIELD LOGIC
DETECTED CHARACTER REGISTER LOGIC

5.16

INT/SKIP LOGIC

5.17

READ STATUS/TEST PULSE LOGIC
LEVEL CONVERSION CIRCUITS

5.5

5.6
5.7

5.8
5.9

5.10
5.11

5.12
5.13
5.14

5.18

CHAPTER 6

Section 6

Spare Parts

6.1.3
6.2

5-19
^'^^

^-23
^'^^
^''^^

^-28
5-30
5*30

5-33

KG8-E GENERATOR/DETECTOR

Section 3

6.1.2

^'^^

5-39

Maintenance

Section 2

6.1.1

^"^^
^'^^

5-^^
5-36

Section 5

Section 1

6.1

^'^

PARITY CHECK

VRC Parity Check
LRC Parity Check
CRC Parity Check
BLOCK DIAGRAM

Introduction

Installation and Checkout

Parity Check/Block Diagram

^"^
®"2
^'^
^'^

^'^

CONTENTS (Cont)
Page
Section 4

6.7

lOT DECODER LOGIC
CONTROL REGISTER LOGIC
VRC LOGIC
BCC CLOCK LOGIC
I/O TRANSFER LOGIC

6.8

BCC LOGIC

6.3
6.4
6.5

6.6

Detailed Logic

g.,Q

,
'

g 10
6-12
.

q -15

6 ,6

6-17
Section 5

Maintenance

Section 6

Spare Parts

PART 6 CARD READERS

CHAPTER 7

CM8-E/CR8-E CARD READERS
Section 1

Introduction

Section 2

installation

Section 3

Block Diagram Description

Section 4
7.1

7.2
7.3

7.4
7.5

7.6

Detailed Logic

lOT DECODER LOGIC
SELECT CARD LOGIC

7 5
.

READ DATA LOGIC
INTERRUPT/SKIP LOGIC
STATUS LOGIC
READ GATING LOGIC

77
77
^q
7 10

7.13

Section 5

Maintenance

Section 6

Spare Parts

PART 7 MAGNETIC TAPE

CHAPTER 8

TD8-E DECTAPE CONTROL

8.1

INSTALLATION

8.2

ACCEPTANCE TEST
TD8-E INTERFACE

8.3

Section 1

Introduction

Section 2

Installation

3 2

[]\

"
."

g'2

CONTENTS (Cont)
Page

Section 3

Functional Description

8.4

INSTRUCTION AND STATUS BITS

8-4

8.5

FUNCTIONAL OPERATION

8-5

I/O Decoder

8-6

8.5.2

Command Register

8-6

8.5.3

8-7

8.5.4

Data Register
Mark Track Register

8.5.5

Flags and Status Bits

8-7

8.5.6

Time Pulse Generator

8-8

8.5.1

8-7

8-8

TD8-E TIMING

8.6

Timing for Writing Time and Mark Tracks
Write Data Timing
Read Data Timing

8.6.1

8.6.2

8.6.3

Section 4

8-8
8-8

8-17
8-17

Control Logic

8.7.1

•

Detailed Logic

INPUT/OUTPUT DECODER LOGIC

8.7

8-8

8.7.1.1

C Line Select Logic

8-17

8.7.1.2

Time Pulse 3 Logic

8-18

8.7.1.3

Initialize Logic

8-18

RunSignalandCON ALL HLT Logic
COMMAND REGISTER

8.7.1.4

8.8

8-18
8-18

8.8.1

Unit Select Logic

8-18

8.8.2

Forward/Reverse (F/R) Logic

8-18

8.8.3

Stop/Go Logic

8-18

8.8.4

ReadA/Vrite Logic

8.9

8.10
8.10.1

8.10.2
8.11

8-20

UTS DELAY LOGIC
TIME PULSE GENERATOR

8-20

Write Time Track Pulses
Read Time Track Pulses
FLAGS AND SKIP LOGIC

8-21

8-20
8-22

8-23
8-23

8.11.1

Single Line Flag

8.11.2

Ouad Line Flag and Counter Logic
Time Error Flag

8.11.3

8-23
8-25
8-25

8.13

MARK TRACK REGISTER
DATA REGISTER AND GATING LOGIC

8.14

DATA GATING LOGIC

8-27

8.15

WRITE FUNCTION REGISTER
WRITE ECHO AND SELECT ECHO CIRCUITS

8-27

8.12

8.16

Section 5

Maintenance

Section 6

Spare Parts

VII

8-26

8-27

CONTENTS (Cont)
Page

CHAPTER 9

TM8-E DECMAGTAPE CONTROL
Section 1

9.1

9.1.1

Introduction

RECORDING METHODS AND DECmagtape FORMATS
NRZI Recording Method

9-2
,

9.2

9.1.2

9-Track Tape Format

9.1.3

7-Track Tape Format

9.5

9.1.4

Cyclic Redundancy Check Characters (CRC)

9.5

9.3

9.1.5

Longitudinal Redundancy Check Character (LRC)

9.7

9.1.6

Data Files

9.7

9.1.7

Track Assignments

9.7

9.2

COMPANION DOCUMENTS
SOFTWARE DOCUMENTS

9-8

9.3

Section 2

9-8

Site Preparation, Installation, and Acceptance Test

9.4

SITE PLANNING AND CONSIDERATIONS

9.5

INSTALLATION
ACCEPTANCE TEST
TM8-E INTERFACE

9.6
9.7

9.9

9-10
9-10
Section 3

9.8
9.8.1

9.8.1.1

9.8

Principles of Operation

BLOCK DIAGRAM DESCRIPTION

9.I7

M8321 Output Control Module
lOT Instruction Decoder

9. 17

9.I7

9.8.1.2

Function Decoder

9.I7

9.8.1.3

Gating Logic

9.I8

9.8.1.4

Read/Compare Error Detection Logic

9-18

9.8.1.5

Skip Logic

9.I8

9.8.2

M8327 Registers Module

9. 18

9.8.2.1

Multiplexer and Data Register

9.8.2.2

Command Register

9.I8

9.8.2.3

Function Register

9.I9

9.I8

9.8.2.4

Current Address Register

9.20

9.8.2.5

Word Count Register

9.20

9.8.3

M8323 Transport Status and Control Module

9-21

9.8.3.1

Main Status Register

9.8.3.2

Second Status Register

9.21

9.8.3.3

ERROR Flag

9-22

9.8.3.4
9-8.3.5

9.8.3.6

9.8.4

Illegal

Function Detection

PR ESET and SET Pulse Generator
Control Busy (CNTL BSY)
M8322 Control and Data Break Module

9.21

9-22
9-22

9.22
9-22

9.8.4.1

Data Break Control Logic

9.8.4.2

Function Decoder

9.23

9.8.4.3

Interrupt Logic

g.23

9-22

CONTENTS (Cont)
Page
9.9

9.10

INSTRUCTIONS AND STATUS BITS
OPERATION AND PROGRAMMING

9 24
9-35

Single Cycle Data Break

9 44

9.10.1.1

Signal Conventions

9-45

9.10.1.2

Write Data

9-45

9.10.1.3

9 45

9.10.1.7

Read Data
Read/Compare
Extended Gap
Write End of File
Space Forward

9.10.1.8

Space Reverse

9-59

9.10.1.9

Rewind

9-59

9.10.1.10

Continuous Operation

9-59

Programming Notes and Examples
Programming Notes
Programming Examples

9-59

9.10.1

9.10.1.4
9.10.1.5

9.10.1.6

9.10.2
9.10.2.1

9.10.2.2

Section 4

9-48
9-48

9 48
9-59

9-59
9-59

Detailed Logic

M8321 OUTPUT CONTROL MODULE

9-61

9.11.1

Input/Output Instruction Decoder

9-61

9.11.2

C Line Select Logic
TP3 Logic

9-61

9-63

9.111.5

CLR ALL Logic
AC ENABLE Logic

9.11.6

Skip Logic

9-63

9.11.7

9-63

9.11.8

Output Control Function Decoder
Read/Compare Logic

9.11.9

Write Data Select Logic

9-65

TM8-E REGISTERS (M8327)

9-65

9.11

9.11.3
9.11.4

9.12

9-61

9-63

9-65

9.12.1

Data Buffer Register and Multiplexer

9-65

9.12.2

AC Input Gating

9-65

9.12.3

Current Address (CA) Register

9-71

9.12.4

Word Count (WC) Register

9-71

9.12.5

Function Register

9-71

9.12.6
9.12.7

9.13
9.13.1

Command Register
Buffered Command Register (BCM)
M8323 TRANSPORT STATUS AND CONTROL MODULE
Main Status Register

9-72

9-75
9-75

9-75

9.13.1.1

SC-2 ERROR Flag Logic

9.13.1.2

Illegal

9.13.1.3

Data Late Logic

9-77

9.13.1.4

Record Length Incorrect Logic

9-79

9.13.1.5

9-79

9.13.1.8

Tape Rewinding
End of Tape
Beginning of Tape
Read/Compare Error

9.13.1.9

Parity Error

9-79

9.13.1.10

File Mark (EOF)

9-79

9.13.1.6
9.13.1.7

Function Logic

9-75
9-75

9-79
9-79
9-79

CONTENTS (Cont)
Page
9.13.1.11

Select Remote

9-79

9.13.1.12

File Protect

9-79

9.13.2

Second Status Register

9-80

9.13.2.1

EMA 7 Increment Error

9.13.2.2

Vertical Parity Error (C VPE)

9-81

9.13.2.3

LRC ERROR
CRC ERROR

9-81

9.13.2.4

9-80

9-81

9.13.3

Main and Second Status Register Multiplexer

9-81

9.13.4

Extended Memory Address Increment Logic

9-83

9.13.5

Control Busy (CNTL BSY)

9-83

9.13.6

PRESET and SET Pulse Generator

9-83

9.13.7

Data Late Error Check Logic

9-83

9.14

M8322 CONTROL MODULE

9-85

9.14.1

Control Function Decoder

9-85

9.14.2

Data Break Request Logic

9-85

9.14.2.1

Word Count Overflow Logic

9-85

9.14.3

Data Break Priority Logic

9-86

9.14.4

Processor Control Logic

9-89

9.14.5

MTTF (JOB DONE) Logic

9-89

9.14.6

Interrupt Logic

9-89

9.14.7

Change Transport Control Logic

9-89

9.14.8

Change Direction Control Logic

9-90

9.14.9

Write Data Ready Logic

9-90

9.14.10

Read and Write Control Logic

9-91

9.14.11

Data Multiplexer Control Logic

9-91

9.14.12

POWER OK Logic

9-93

9.14.13

Initialize Logic

9.95
Section 5

Maintenance

Section 6

Spare Parts

Section 7

IC Descriptions

DEC 74153 IC
DEC 74174 10
DEC 74175 IC
DEC 74197 IC

CHAPTER 10

9.97

9.99

9.100
9-101

TA8-E CASSETTE SYSTEM INTERFACE
Section 1

10.1

PHYSICAL DESCRIPTION

10.2

POWER REQUIREMENTS
TAPE FORMAT
DOCUMENTATION

10.3
10.4

Introduction

10-2
„

10-2
i0-2

10-3

CONTENTS (Cont)
Page

Installation and Acceptance Test

Section 2

10.5
10.6
10.7

10-4

INSTALLATION
ACCEPTANCE TEST
TA8-E INTERFACE

10-5
10-5

Section 3

10.8

Functional Description
10-6

FUNCTIONAL DESCRIPTION

10-6

10.8.1

lOT Decoder

10.8.2

Status A Register

10.8.3

Function Register

10-8-4

Status B Register

10-9

10.8.5

Read/Write Buffer Register

10-9

10.8.6

Data Flag

10.9
10.9.1

10.10
10.10.1
10.10.1.1

10.10.1.2

10.10.1.3

10.10.1.4
10.10.1.5

10-8
•

10-9
10-9

INSTRUCTION AND STATUS BITS

10-9

Programming Sequence

INPUT AND OUTPUT INTERFACE SIGNALS
Output Interface Signals

1012
1012

SELECT ENABLE L
DRIVE B L
START L
REWIND L
BACK BLOCK GAP L

10-12
'0''2

10.10.1.10
10.10.1.11

INITIALIZE L

10.10.1.7

10.10.1.8
10.10.1.9

10.10.2
10.10.2.1

10.10.2.2

10.10.2.3
10.10.2.4
10.10.2.5

10.10.2.6
10.10.2.7

10.10.2.8
10.10.2.9

10.10.2.10

10.12
10.12.1

1013
1013
1013
1013
10-14

1014
10-14

in
14
'""'^

Input Interface Signals

OFF LINE L

10-14

READY L
END FILE L

^^"""^

EOT/BOT L
REWIND L
WRITE PROTECT L
WRITE STATUS L

10-'I4

TRANSFER REQUEST L
TIME ERROR L
CRC BLOCK ERROR L

1015

10-14

Section 4

10.11

10-9

10-12

BACK FILE GAP L
READ/WRITE FILE GAP L
WRITE MODE L
TRANSFER L
READ/WRITE CRC L

10.10.1.6

10-9

10-14
10-14

10-14
10-15

1015
Detailed Logic

DEVICE SELECT AND lOT DECODER
CONTROL LOGIC
C Line Select Logic

10.12.2

Time Pulse Logic

10.12.3

Initialize and Clear All

10-15

]°]^
10-15
1017

Logic

CONTENTS (Cont)
Page
10.13

10.14
10.15
10.16

STATUS A REGISTER
FUNCTION REGISTER
START LOGIC
READ/WRITE BUFFER REGISTER

10.16.1

Data Flag

10.17

INTERRUPT LOGIC

10.18

SKIP

10.19

OUTPUT DATA MULTIPLEXER

10-18

10-18
10-20
.

10-20

10-22

„

10-22
'

10.23
10-23

Section 5

Maintenance

PREVENTIVE MAINTENANCE
CORRECTIVE MAINTENANCE

10-24

10.21
10.21.1

lOT Decoder Check

10-25

10.21.2

Status A Register Check

10-25

10.21.3

Status B Check

10-26

10.21.4

Read/Write Buffer Check

10-26

10.21.5

Command Decoder Check

10-27

10.20

10-24

Section 6
Section 7

Spare Parts

IC Descriptions

DEC 7442 IC

10-27

PARTS DISKS
CHAPTER 11

RK8-E DISK DRIVE CONTROLLER
Section 1

11.1

11.2
11.2.1

11.3
11.3.1

PURPOSE
PHYSICAL DESCRIPTION
RK05 Disk Drive
RECORDING METHODS AND FORMATS
Double Frequency Recording Method

11.3.2

Disk Addressing

11.3.3

Sector Format

11.3.3.3

HEADER Word
CRC Character
Formatting A Cartridge

11-3.3.4

Write Protect

11.3.3.1

11.3.3.2

11.4

Introduction

11-1

11.2

11-2

................

"
.'

11.2

II.3
II.4
II.4

^^.4
II.5
11.6

H.g

MAJOR REGISTERS

.•...................]. ^^.6

11.4.1

Command Register

11.4.2

Current Address Register

H.g
H.g

11.4.3

Disk Address Register

11.6

XII

CONTENTS (Cont)
Page
11.4.4

Status Register

11-8

11.4.5

Data Buffer Register

11-8

11.4.6

CRC Register

11-8

11.4.7

iVlajor State

11.4.8

Bit Counters

11-11

128- or 256-Word Counter

11-12

11.4.9

11.5
11.5.1

11-8

COMPANION DOCUMENTS

11-12
11-12

Software
Section 2

Site Preparation, Installation, and Acceptance Test

11.6

SITE PREPARATION

11-12

11.7

INSTALLATION
ACCEPTANCE TEST
RK8-E INTERFACE

11-13

11.8

11.9

Section 3

11.10
11.11
11.11.1

11-13
11-15

Operation and Programming

SINGLE CYCLE DATA BREAK DESCRIPTION
INSTRUCTIONS AND STATUS BITS
Command Functions

11-34
11-34
11-40

11-40

11.11.1.2

Read Data
Read All

11.11.1.3

Write Data

11-41

11.11.1.4

Write All

11-41

11.11.1.5

Write Protect

11-42

11.11.1.6

Seek Only

11-42

11.11.1.7

Interrupt Enable

11-42

11.11.1.8

TRANSFER DONE on SEEK COMPLETE

11-42

11.11.1.9

11-42

11.11.1.10

Read or Write Half Block (128 Words)
Extended Memory Addressing

11.11.1.11

Unit Select

11-42

11.11.1.1

11.11.1.12
11.11.2

11-41

Extended Cylinder Address
Maintenance Functions

11-42
11-42
11-43

11.11.2.1

Maintenance Mode

11-43

11.11.2.2

Shift Enable

11-43

11.11.2.3

Check CRC Register
Check Command Register
Check Surface/Sector Register
Check Data Buffer
Check Data Break Request
Check Lower Data Buffer

11-43

11.11.2.4

11.11.2.5
11.11.2.6
11.11.2.7

11.11.2.8
11.11.2.9

11.12
11.12.1

11.12.2

11.12.3

11.12.4

11-43
11-43
11-43

11-44
11-44
11-44

Maintenance Data

PROGRAMMING SEQUENCES
Format A New Disk Cartridge

11-44

Normal Read/Write
Bootstrap Loader
...
Seek Only

11-45

11-44
11-45

11-45

XIII

CONTENTS (Cont)

11.12.5

Overlapped Seeks

11-46

11.12.6

Recalibrate Selected Drive

11-46

11.12.7

Data Transfers on Consecutive Sectors

11-46

11.13
11.13.1

PROGRAMMING EXAMPLES

11-47

Write All

11.13.2

Recalibrate

11.13.3

Seek Only

11.13.4

Overlap Seek

11.13.5

Write Data

11.13.6

Read All
Read Data

11.13.7

11-47

11-48
11-49

11-50

11-51
11-51

Section 4

11.14

11-46

Theory of Operation

BLOCK DIAGRAM DESCRIPTION

11-52

11.14.1

I/O Bus Interface

11-52

11.14.2

Command Register

11-54

11.14.3

Status Register

11-54

11.14.4

Data Break Control Logic

11-54

11.14.5

Data Buffer Register

11-55

11.14.6

CRC Register

11-55

11.14.7

Control Sequencer

11-58

11.14.7.1

Major States

11-58

11.14.7.2

IDLE State

11-58

11.14.7.3

RESTORE State
STROBE State

11-61

11.14.7.7

HEADER AState
HEADER B State
HEADER estate

11.14.7.8

SECTOR SEEK State

11-61

11.14.7.9

HEADER D State
HEADER E State
DATA State
CRC State
END State

11-61

11.14.7.4
11.14.7.5

11.14.7.6

11.14.7.10
11.14.7.11

11.14.7.12

11.14.7.13
11.14.8

Read/Write Delays, Clocks, and Counters

11-61

11-61
11-61

11-61
11-71
11-71
11-71
11-71

11.14.8.1

Write Data Clock

11-71

11.14.8.2

Write Sync Delay

11-71

11.14.8.3

Read Delay
Read Clock Data

11-71

11.14.8.5

Counters

11-72

11.14.9

Maintenance Logic

11-72

11.14.8.4

11.15
11.15.1

DETAILED LOGIC DESCRIPTION
I/O Bus Interface

11-71

11-72

11.15.1.1

MD Receivers

11-72

11.15.1.2

OT Decoder Logic

11-73

CONTENTS (Cont)
Page
11.15.2

Control Logic

11.15.2.1

Line Select Logic

11-75

11.15.2.2

11-75

11.15.2.3

Time Pulse 3 (TP3) Logic
IDLE

11.15.2.4

Clear Logic

11-75

11.15.2.5

Interrupt Logic

11-76

11.15.2.6

Skip Logic

11.15.3

11-75

11-76

Command Register

11-76

11.15.3.1

Function Decoder

11-76

11.15.3.2

Unit Select Decoder

11-76

11.15.4

Status Register

11-78

11.15.4.1

11-78

11.15.5

TRANSFER DONE
HEADS IN MOTION
SEEK FAIL
DRIVE STATUS ERROR
CONTROL BUSY ERROR
TIME OUT ERROR
WRITE LOCK ERROR
CRC ERROR
DATA REQUEST LATE
DRIVE STATUS ERROR
CYLINDER ADDRESS ERROR
ERROR Flag

11.15.6

Sector Address Comparator

11-80

11.15.7

Data Break Control Logic

11-81

11.15.4.2

11.15.4.3
11.15.4.4
11.15.4.5
11.15.4.6

11.15.4.7

11.15.4.8
11.15.4.9

11.15.4.10
11.15.4.11

11-78

11-78
11-78
11-78
11-78

11-78
11-80
11-80
11-80
11-80
11-80

11.15.7.1

Current Address Register

11-81

11.15.7.2

Data Transfer Control Logic

11-84

11.15.7.3

Priority Logic

11-84

11.15.7.4

CPU Control Logic

11-84

11.15.8

Data Buffer Register and Control Logic

11-85

11.15.8.1

Data Buffer Register Control Logic

11-85

11.15.8.1

Data Buffer Control 1 and Data Buffer 1

11-87

11.15.8.3

Data Buffer Control 2 and Data Buffer Register 2

11-87

11.115.8.4

Data Buffer Control 3 and Data Buffer Register 3

11-89

11.115.8.5

Data Buffer Control 4 and Data Buffer Register 4

11-89

11.15.9

Output Data Multiplexer

11.15.10

Read/Write Logic

11-90

Write Clock

11-90

Read Delay

11-92

11.15.10.1

11.15.10.2
11.15.11

11-90

CRC Register

11-92

11.15.11.1

Disk Address

11-92

11.15.11.2

CRC Character Computation
CRC Character Check

11-95

11.15.11.3

11-94

11.15.12

Major States

11-95

11.15.13

RK8-E Counters

11-95

11.15.13.1

12-Bit Counter

11-95

11.15.13.2

Word Counter

11-95

11.15.13.3

16-Bit Counter

11-99

Break Counter

11-99

11.15.13.4

CONTENTS (Cont)
Page
Section 5

Maintenance

PREVENTIVE MAINTENANCE
CORRECTIVE MAINTENANCE

11-99

11.17
11.17.1

Check Data Buffers

11-100

11.17.2

Checking the Command Register

11-101

11.17.3

11-102

11.17.4

Check Surface and Sector Register
Check CRC Register

11.17.5

Single Cycle Data Break Transfers (Read Operation)

11-104

11.17.6

Single Cycle Data Break Transfers (Write Operation)

11-105

11.17.7

Single Cycle Data Break Transfers (Write then Read)

11-106

11.16

Section 6

11-99

Section 7

11-103

Spare Parts
IC Descriptions

11-109

11.20

DEC 74155 IC
DEC 74193 IC
DEC 7485 IC

11.21

DEC74161 IC

11-115

11.18
11.19

11-109
11-109

PART 9 DISPLAYS

CHAPTER 12

VT8-E HIGH SPEED VIDEO DISPLAY TERMINAL AND CONTROL
Section 1

12.1

12.1.1

12.1.2
12.1.2.1

12.1.2.2

SYSTEM OPERATING SPECIFICATIONS
CRT Operating Specifications (Motorola Raster Display)
Visible Display Specifications

Alphanumeric Mode
Graphic Mode
Section 2

12.2

Introduction
12-2
12-2
12-3

12-3
12-3

Installation and Acceptance Test

UNPACKING

12-4

12.2.1

Primary Power

12-4

12.2.2

VT8-E Installation

12-5

12.2.3

Acceptance Test

12-8

Section 3
12.3
12.3.1

Operation and Programming

FUNCTIONAL DESCRIPTION
VT8-E Printer/Keyboard Control Module (M8335)

12-8
12-8

12.3.1.1

MD Bus Gating

12-8

12.3.1.2

lOT Decoders

12-9

12.3.1.3

Data Bus Gating

12-9

CONTENTS (Cont)
Page
12.3.1.4

Keyboard Buffer

12-10

12.3.1.5

I/O Transfer Control

12-10

12.3.1.6

Interrupt and Skip Logic

12-10

12.3.1.7

Interrupt Logic

12-10

12.3.1.8

Starting Address Register and Counter (SAR)

12-10

12.3.1.9

Extended Starting Address Register

12-10

12.3.1.10

Printer Buffer

12-10

12.3.1.11

PRINT DONE Flag

12-10

12.3.1.12

Higher Priority Detection

12-10

12.3.2

VT8-E Line Buffer Module (M8337)

12-11

12.3.2.1

Line Buffers A and B
ASCII Decoding ROMs

12-11

12.3.2.2
12.3.2.3

Graphic Video Buffer

12-11

12.3.2.4

Character Display Mode Detection Logic

12-11

12.3.2.5

Visible Field Detection Logic

12-11

12.3.2.6

Single Cycle Data Break Control Logic

12-12

12.3.2.7

Processor Control Signals

12-12

12.3.2.8

Break Counters

12-12

12.3.2.9

MA and EMA Bus Gates

12-12

12.3.2.10

Data Bus Gates

12-12

12.3.2.11

Maintenance Enable

12-12

12.3.2.12

Frequency Divider Board (M8336)

12-12

12.3.2.13

Display lOT Decoder

12-12

12.3.3
12.3.3.1

VT8-E Clock and Frequency Divider (M8336)
Real Time Clock Flag
Video and Sync Combining Circuits

12.3.3.2

12.3.4

12-11

OT Instructions

12-12

12-12
12-13

12-13

12.3.4.1

Display Instructions

12-13

12.3.4.2

Keyboard Instructions

12-14

12.3.4.3

Printer Instructions

12-16

12.3.5
12.3.5.1

12.3.5.2

12.3.6
12.3.6.1

12.3.6.2
12.3.7
12.3.7.1

12.3.7.2

Display Data Format

Graphic Data Format

12.4,1

12-17

12-18

Display Monitor and Keyboard Switches and Controls
Display Monitor Switches and Controls

Keyboard Controls
Programming Examples
Graphic Display Program Example
Alphanumeric Display Program Example
Section 4

12.4

12-17

Alphanumeric Data Format

12-18
12-18
12-18
12-22
12-22

12-22

Detailed Logic Description

INTRODUCTION

12-23
12-24

Keyboard/Printer Logic

12.4.1.1

lOT Decoder Logic

12-25

12.4.1.2

Printer Receive Logic

12-25

12.4.1.3

Keyboard Transmit Logic
INT/SKIP Logic

12-29

12.4.1.4

12-30

xvii

CONTENTS (Cont)
Page
12.4.2

12-31

Display Logic

12.4.2.2

VT8-E Timing
VT8-E Timing Logic

12.4.2.3

Starting Address Register Logic

12-39

12.4.2.4

Data Break Counting Logic

12-40

12.4.2.5

Data Breal< Control Logic

12.4.2.6

Data Break Halt, Line Feed, and End-of-Screen Logic

12.4.2.7

Priority Logic

12-47

12.4.2.8

Line Buffer Register and Control Signal Logic

12-47

12.4.2.9

ROM Character Generator Logic

12.4.2.10

Alphanumeric Video Buffer Control Logic

12.4.2.11

Graphic Video Buffer and Control Logic

12.4.2.12

Visible Field Logic

12.4.2.13

Display Mode Logic

12.4.2.14

Maintenance lOT Logic

12.4.2.15

Display Interrupt and Skip Logic

12-63

Bell Logic

12-64

12.4.2.1

12.4.2.16
12.5

12-34
12-35

12-44
.

12-47

12-53
.

12-56
12-58

12-59
12-61

12-63

DISPLAY MONITOR CIRCUITS

12-64

12.5.1

Keyboard Logic

12-64

12.5.2

Motorola CRT Display

12-66

12.5.2.1

Video Amplifier

12-66

12.5.2.2

Sync Separator

12-66

12.5.2.3

Phase Detector

12-66

12.5.2.4

Horizontal Oscillator

12-67

12.5.2.5

Pulse Shaper and Horizontal Drive

12-67

12.5.2.6

Horizontal Output

12-67

12.5.2.7

Vertical Oscillator Driver and Output

12-67

12.5.2.8

Retrace Blanking

12.5.2.9

Power Supply
Section 5

12.6

12-68
.

12-68

Maintenance

INTRODUCTION

12-68

12.6.2

Equipment Required
Diagnostic Programming

12-69

12.6.3

Preventive Maintenance

12-69

Mechanical Checks

12-70

12.6.1

12.6.3.1

12.6.4

12-69

12-70

Troubleshooting

12-70

12.6.4.2

System Troubleshooting
Module Troubleshooting

12.6.4.3

VT8-E Assembly/Disassembly

12-70

12.6.4.1

APPENDIX A

12-70

ROM PATTERN TABLES

xvtii

ILLUSTRATIONS
Figure No.

1-1

1-2

Page

Title

LC8-E Block Diagram
LC8-E lOT Decoder

1-4

1-2

1-3

Printer Receive Logic

1-6

1-4

Timing, Printer Receive Logic

1-7

1-5

Keyboard Transmit Logic

1-8

1-6

Timing, Keyboard Transmit Logic

1-9

1-7

INT/SI<ip Logic

1-9

2-1

PC8-E Control, Block Diagram

2-3

2-2

2-6

2-3

lOT Decoder Logic
Tape Read Logic

2-4

Reader Timing

2-8

2-5

Clock Logic

2-10

2-6

Clock/Shift Pulse Timing

2-11

2-12

2-7

Reader Motor Control Logic

2-8

RDR INT/Skip Logic

2-13

2-9

Reader Buffer Logic

2-14

2-10

3-4

Tape Status Logic
Tape Punch Logic
Punch Buffer Logic
Punch INT/Skip Logic
XY8-E Block Diagram
lOT Decoder Logic
Timing Logic
Function Timing; Pen Up, Pen Down, Start Zip (Encoded Plotter)

3-5

Direction Transfer Logic

3-6

INT/Skip Logic

3-10

4-1

4-2

LE8-E Line Printer Control Block Diagram
LE8-E Control Timing

4-4

2-11

2-12
2-13
3-1

3-2

3-3

2-15
2-17

2-19

2-20

32
3-4
3-6
3-7

3-9

4-3

Select Logic

4-6

4-4

Interrupt Logic

4-7

4-5

Skip Logic

4-7

4-6

Data Transfer Logic

5-1

Simple Block Diagram, DP8-E

5-4

5-2

Detailed Block Diagram, DP8-E

5-3

Timing, Receive Break Request

5-10

5-4

Timing, Transmit Break Request

5-11

5-5

DP8-E lOT Decoder Logic

5-14

5-6

Control Word Logic

5-15

5-7

Break RQST, Receive Logic

5-16

5-8

Sync Character Detection, Timing Diagram

5-18

5-9

Receive Data Register Logic

5-19

5-10

Break Request, Transmit

5-22

5-11

Transmit Data Register Logic

5-12

BRK RQST Logic

5-25

5-23

5-13

Break Grant Logic

5-26

5-14

Access Add Counter Logic

5-28

5-15

Current/ Access Address Register Logic

5-31

5-16

Load Field Logic

5-32

XIX

ILLUSTRATIONS (Cont)
Figure No.

Page

Title

5-17

Detected Character Register Logic

5-34

5-18

INT/Skip Logic (RING, CARRIER/AGO

5-35

5-19

5-20

Read Status Logic

5-21

Test Pulse Logic

5-22
5-23

DP8-E Input Circuit (Receiver)
DP8-E Output Circuit (Driver)

5-24

Self-Test Interconnection

6-1

LRC BCC Accumulation for Four 8-Bit Characters
CRC BCC Accumulation for Two 12-Bit Characters

6-2

NT/SI<ip Logic (Character Detected, Bus Error,

WC Overflow)

5-37

5-38
5-39
5-39

5-40
5-43
6-3
6-7

6-8

6-4

KG8-E Block Diagram
lOT Decoder Logic

6-10

6-5

Control Register Logic

6-11

6-6

6-13

6-7

VRC Logic
VRC Logic Timing

6-8

BCC Clock Logic

6-15

6-9

9.5 MHz Clock Pulse Generation

6-15

6-10

I/O Transfer Logic

6-16

6-11

6-18

6-13

BCC Logic, Block Diagram
6-, 7-, and 8-Bit LRC BCC Accumulation
BCC Generating Logic (Using LRC Technique- 6-Bit Character)

6-14

Logic Block Diagram:

LRC-12, LRC-16

6-22

6-15

Logic Block Diagram: CRC-12, CRC-16

6-23

7-1

7-3

CR8-E/CM8-E Control Block Diagram
Timing, CR8-E/CM8-E Control
lOT Decoder Logic

7-4

Select Card Logic

7-8

7-5

7-6

Read Data Logic
INT/Skip Logic

7-11

7-7

Status Logic

7-12

7-8

Timing, Transition Network

7-12

7-9

Data Gating, RCRB Instruction

7-14

7-10

Data Gating, RCRA Instruction

7-15

7-11

Data Gating, RCRC Instruction

7-15

8-1

TD8-E Block Diagram
TD8-E Functional Block Diagram

8-1

6-3

6-12

7-2

8-2

6-14

6-19
6-21

7-2

7-6

7-9

8-5

8-8

Format of Data Loaded into the Command Register
Format of Word Transferred to AC
Timing for Writing Mark and Time Tracks
Write Data Timing
Read Data and Mark Track Timing
DECtape Data Format

8-9

I/O Decoder Detailed Logic

8-17

8-10

Command Register and UTS Logic

8-19

8-1

8-21

8-12

Time Pulse Generator Logic
Read Time Track Pulse Timing

8-13

Single Line Flag, Quad-Line Flag, and Skip Logic

8-24

8-14

Mark Track Register

8-25

8-3
8-4
8-5
8-6
8-7

8-6
.

8-7

8-9

8-14

8-15
8-16

8-22

ILLUSTRATIONS (Cont)
Page

Title

Figure No.

8-15

Data Register

^"26

8-16

Data Gating Logic

^"28

8-17

Write Function Register

8-18

Write Eclio and Select Error Circuits

^'29
8-30

9-1

Tl\/I8-E DECmagtape Control and

9-2

Data Recording Structure

9-3

9-Track Tape Format

9-4

7-Track Tape Format

TU 10 Master System, Block Diagram

9-1

9-^
9-4
9-5
9- "10

9-6

TM8-E Module Installation
TM8-E Block Diagram

9-7

Contents of Command Register

9-8

Contents of Function Register

9-9

Contents of Main Status Register
Contents of Function and Second Status Register

9-21

9-25

9-16

LWCR and RWCR Instruction Data Flow
LCAR and RCAR Instruction Data Flow
LCMR and RCMR Instruction Data Flow
LFGR and RFSR Instruction Data Flow
LDBR and RDBR Instruction Data Flow
RMSR Instruction Data Flow

9-17

Single Cycle Data Break Data Transfer Data Flow

9-46

9-18

Core Dump Data Flow

9-47

9-19

Single Cycle Data Break Timing Diagram

9-48

9-20
9-21

TM8-E Flow Diagrams
lOT Decoder Logic

9-22

Skip Logic

9-23
9-24

Output Control Function Decoder
Read/Compare and Write Data Select Logic

9-25

Input Data Multiplexer and Data Register

9-26

9-68

9-27

Data Register and Function Register Output Multiplexer
AC Input Gating and Holding Buffer Register

9-28

Current Address and Word Count Registers

9-70
^'^^

9-5

9-10
9-11

9-12

9-13
9-14
9-15

9-17

9-19

9-20
9-21

9-26
9-27
9-27

9-30
9-31
«

^'^^
9-62

^'^^
9-64
9-66
9-67

9-69

9-29

Function Register

9-30

Command Register and Multiplexer

9-31

Error Flags

9-32

Illegal Function Flag and Control Logic

9-33

Data Late and EM A Increment Error Flags

9-77

9-34

Record Length Incorrect Error Detection Logic

9-78

9-35

Parity Error Flags

9-36

9-38

Main Status Register and Second Status Register Multiplexer
PRESET and SET Pulse Generation Logic
Data Late Error Check Logic

9-39

Control Function Decoder

9-40
9-41

Data Break Control Logic
Priority and Processor Control Logic

9-42

MTTF (JOB DONE Flag) and Interrupt Request Logic

9-88

9-43

Change Transport and Buffered Command Register Control Logic

9-90

9-44

Change Direction Detection Logic

9-37

9-73
®"^^

9-76

9-80
9-81

9-82
9-84

9-84
9-86
9-87

9-91

XXI

ILLUSTRATIONS (Cont)
Figure No.

Title

Page

9-45

Write Data Ready Logic

9-91

9-46

Read and Write Control Logic

9-93

9-47

Data Multiplexer Control Logic

9-93

9-48

Initialize and Clear Logic

9-94

10-1

TA8-E Interface and TU60 Cassette Drive, Block Diagram

10-2

Typical TU60 Format

10-1
.

10-2

10-3

10-4

TU 60 Capacity and Data Rate vs Block Length
TA8-E and TU60 Cabling

10-5

TA8-E Block Diagram

10-7

10-6

Contents of the Status A Register

10-8

10-7

Contents of the Status B Register

10-8

TA8-E Flow Diagram

10-9

Device Select and

10-10

Data Transfer Control Logic

10-17

10-11

Status A Register

10-18

10-3

10-4

10-8

10-10

OT Decoder Logic

10-16

10-12

Function Register

10-13

Start Logic

10-20

10-14

Read/Write Buffer Register

10-21

10-15

TA8-E Flags

10-22

10-16

Interrupt and Skip Logic

10-23

10-17

Output Data Multiplexer
lOT Decoder Output Signal
DEC 7442 IC

10-24

10-18
10-19

10-19

10-25

10-28

11-2

RK8-E Controller and RK05 Disk Drive System Block Diagram
Double Frequency Recording Method

11-3

Disk Format

11-5

11-4

Contents of Command Register

11-7

11-5

Disk Address Register

11-7

11-6

Contents of Status Register

11-7

11-8

Read and Write Flow Diagram
RK8-E Module Installation

11-14

11-9

RK8-E Block Diagram

11-53

11-10

Data Break Control

11-54

11-11

Data Buffer Register

11-56

11-12

CRC Register

11-57

11-13

Major States Register

11-59

11-14

Read/Write Delays and Counters

11-60

11-15

RK8-E Flow Diagrams

11-62
11-73

11-1

11-4

11-8
11-11

11-16

Maintenance Logic

11-17

MD Receivers and OT Decoder

11-18

11-75

11-19

INITIALIZE, CLEAR ALL and Time Pulse 3 Logic
Interrupt and Skip Logic

11-20

Command Register

11-77

11-21

Status Register

11-79

11-22

Sector Address Comparator

11-81

11-74

11-76

11-23

Current Address Register

11-82

11-24

Single Cycle Data Break Control Logic

11-83

11-25

Data Buffer Register

11-86

XXII

ILLUSTRATIONS (Cont)
Figure No.

Title

Page

11-26

Data Buffer Register Control Logic

11-88

11-27

Output Data Multiplexer

11-90

11-28

Read/Write Logic

11-91

11-29

CRC and Surface Sector Register

11-93

11-30

CRC Computation Block Diagram

11-94

11-31

Disk Address Output Buffers

11-94

11-32

Major States Register

11-96

11-33

11-36

RK8-E Counters
DEC 74155 IC Illustration
DEC 74193 IC Illustration
DEC 7485 IC Illustration

11-37

DEC 74161 IC Illustration

11-116

12-1

VT8-E Display Monitor
VT8-E Module Installation
VT8-E Block Diagram

12-1

11-34
11-35

12-2
12-3

11-98

11-110
11-112
11-114

12-8
12-9

12-14

12-5

Extended Address and Sense Switch Data
Keyboard Data Format

12-15

12-6

Printer Data Format

12-16

12-7

12-17

12-8

Alphanumeric Display Data Format
VT8-E Functional Block Diagram

12-9

Printer/Keyboard Block Diagram

12-24

12-10

lOT Decoder Logic

12-26

12-11

Printer Receive Logic

12-27

12-12

Printer Receive Logic Timing

12-28

12-13

Keyboard Transmit Logic

12-29

12-14

12-30

12-15

Keyboard Transmit Logic Timing
Keyboard/Print Interrupt and Skip Logic

12-16

Display Logic Block Diagram

12-32

1217

Video Presentation for the Letter F

12-33

12 18

Two Alphanumeric Characters Displayed on the CRT

12-34
^2-35

12-20

Sweep and Sync Signals
Clock Pulse Generator

12-21

4-Bit Counter

""^-^^

12-22

VT8-E Timing Chain

12 23

Horizontal and Vertical Sync Circuits

^2-^^
12-38

12-24

Horizontal and Vertical Zone Flip-Flops

12-39

12-25

1240

12-26

Alphanumeric and Graphic Line Timing
Starting Address Register Logic

12-27

Starting Address Register Control Logic

12-42

12-28

Data Break Control Logic

12-29

12-30

Data Break Counting for 32 Characters/Line
PRESET BRK Generation Graphic Mode

12-31

Data Break Control Logic

12-32

Data Break Halt, Line Feed/EOS Logic

12-33

Priority Logic

12-34

Line Buffer Register Logic

''2-49

12-35

Line Buffer Register Control Logic

''2-50

12-36

Line Buffer Register

12-4

12 19

12-24

12-31

^2-36

'•2-41

'•2-43

12-44
12-44
^2-45
12-46
^^'^^

^^'^^

XXIII

ILLUSTRATIONS (Cont)
Figure No.

Title

Page

12-37

Line Buffer Timing for 32 Character Line

12-52

12-38

Line Buffer Timing for 64 Character Line

12-52

12-39

Line Buffer Timing

12-53

12-40

12-54

12-41

ROM Character Generation Logic
ROM Functional Logic Diagram

12-42

Alphanumeric Video Buffer

12-57

12-58

12-55

12-43

Character Timing for a 32 Character Line

12-44

Character Timing for a 64 Character Line

12-59

12-45

Graphic Video Buffer Control Logic

12-60

12-46

Graphic Word Timing

12-61

12-47

12-Bit Data Word Format

12-61

12-48

Display Control Logic

12-62

12-49

12-62

12-50

BBFand EBF Timing
Display Mode Logic

12-51

Maintenance lOT Logic

12-64

12-63

12-52

Display Interrupt and Skip Logic

12-65

2-53

Bell Logic

12-65

12-54

CRT Horizontal Oscillator Waveforms
CRT Vertical Oscillator Waveforms

12-67

12-55

12-68

TABLES
Table No.

Title

Page

1-10

2-1

LC8-E lOT Instruction List
LC8-E Recommended Spare Parts
PC8-E lOT Instructions

2-2

Cable/Connector Pin Assignments

2-21

2-3

PC8-E Recommended Spare Parts
XY8-E lOT Instruction List

2-21

3-1

3-2

List of Plotter Directions

3-3

Pin Assignments, Interconnecting Cable

3-11

3-4

XY8-E Recommended Spare Parts
LE8-E lOT Instruction List
LE8-E Recommended Spare Parts

3-11

5-3

Jumper Connections, M839 Module
Jumper Connections, M866 Module
DP8-E lOT Instruction List

5-4

Signal Level Terminology

5-41

5-5

EIA/Current Mode Electrical Specifications

5.41

1-1

1-2

4-1

4-2
5-1

5-2

1-5

2-4

3-3
3-8

4-5
4-8

5.4
5-5

5-6

Modem-Interface Cable Pin Information

5-43

5-7

M866-M839 Top-Connector Signals
Equivalent EIA and CCITT Circuit Designations
DP8-E Recommended Spare Parts
KG8-E lOT Instruction List
KG8-E Recommended Spare Parts
CM8-E/CR8-E Instruction List

5-44

5-8
5-9
6-1

6-2
7-1

5-45
5-46
6-9

6-24
7.4

TABLES (Cont)

7.2

Translation, Hollerith Code - Alphanumeric Code

7-3

Translation, Hollerith Code

7-4

Connector Pin Assignments, J1-J5,J1-J2

8-1

8-2

M960 Module Jumpers

8-3

Device Code Jumpers
TD8-E Signals and Signal Functions

8-4

8-6

C-Line Select Levels and Transfer Operations
Write Echo and Select Echo Signal and Voltage Levels

8-7

TD8-E Recommended Spare Parts

8-5

9-1

9-2

9.3

9-11

Command Register Contents and Function

9-12

Function Register Contents and Functions
Main Status Register Contents and Indications

9.6
9.7

9.8
9.9

9-13
9-15
9-16

c Line Select Levels for TM8-E Transfer Operations

9-118

Data Multiplexer Selection Levels
Read and Write Control Logic Signal Levels

9-19

TM8-E Spare Parts

10-1
101-2

DeviceCodeSelection Jumper Installation
TA8-E Input and Output Signals

10-3

TA8-E Instructions

10-4
10-5

Contentsof the Status A Register
Contents of the Status B Register

10-6

C Line Select Levels for Transfers to the AC

10-7

TA8-E Spare Parts

111-1

RK05 Disl< Drive Specifications

11-2

Major States

11-3

DeviceSelect Jumper Installation

11-4

RK8E Priority Selection
RK8-E-RK05 Interface Cable (P2)
RK8-E-RK05 Interface Cable (PI)

9-17

11-5

11-6

9-12

9 "l^
9 ""^
9 ""^
9-16

99'

^-"^
'

9-96

^^^
10" 5

^^ ^2
^^"^^

^^^^

^
^^ ^
^^ ^

^^^4
^^^^
^^ ^^

^^'^^

11-11

Clear Operations Using the DCLR Instruction

11-9

^-'11

11-tO

11-8

^'^

M7104 Top Connector Signal List
M7105 to M7104 Top Connector Signal List
M7105 to M7106 Top Connector Signal List
M7106 Top Connector Signal List

11-7

°'J^
°'^°
8-29

Second Status Register Contents and Functions
TM8-E Signals and Signal Functions

9-14

7-18

A Five-Character Record
CRCC In Register When Writing
TU 10 Track Assignments for Data and Parity

9.10

9.5

7-17

°'^

TM8-E Module Power Requirements
M8321 Output Control Module Signals and Interface
TM8-E M8323 Transport Status Control Module Signals and Interface
TM8-E M8321 Output Control Module Top Connector Signals
TM8-E M8322 Control Module, Top Connector Signals
TM8-E M8327 Register Module, Top Connector Signals
TM8-EM8323 Transport Status and Control Module, Top Connector Signals

9.4

7-16

- Compressed Code

CR8-E/CM8-E Recommended Spare Parts
TD8-E Signal Interface

7.5

Page

Title

Table No.

XXV

^^"^^

^^^^
^^^^

TABLES (Cont)
Table No.

Title

11-12

Contents of Status Register

11-13

Command Functions

11-36
1^-29

11-14

Maintenance Functions

11-15

C-Line Select Levels and Transfer Operations

11-16

12-3

RK8-E SpareParts
AC Power Cable
Device Code Select Jumper Installation
Priority Jumper Installation

12-4

Switches and Controls

12-1

12-2

12-5

12-6
12-7

-. ..

Character H, EVEN ROM Data Bits
Character H, XTRA ROM Data Bits

12-10

Equipment Required

ROM Pattern Table (EVEN ROM)
ROM Pattern Table (ODD ROM)
ROM Pattern Table (XTRA ROM)

ino

lOlQ

VT8-ETransmltCodes-Full ASCII Operation
VT8-E Transmit Codes -Half ASCII Operation (switch in
position 2)
VT8-E Receiving Codes

A-1

'
'

^^"^

12-8

A-3

ii tk
"

...

12-9

A-2

Page

^2 19

loon
221
1255
1255
a ?

^'g

XXVI

PREFACE
This manual, the third in a series of three, describes peripheral controller options of the PDP-8/E, PDP-8/F, and PDP-8/M.

The content of this manual includes installation procedures, theory of
operation, and maintenance procedures for the options described.
is

assumed that the reader is thoroughly familiar with Volume 1 of

this series, and with the applicable sections of the

PDP-8/M Small Computer Handbook.

1972 PDP-8/E &

PART 1
CONSOLE TELEPRINTER

CHAPTER 1
LC8-E DECWRITER CONTROL

SECTION 1

INTRODUCTION

The LC8-E DECwriter Control interfaces the parallel version of the LA30 DECwriter (LA30P) to the PDP-8/E.
The Control consists of a single M8329 quad module that plugs into the OMNIBUS and connects to the
DECwriter with a signal cable that is supplied with the nnodule.

The LA30 DECwriter is discussed here only to the extent necessary to both fully describe LC8-E Control
operation and present supplementary information concerning installation and checkout. Details concerning the
installation, operation, troubleshooting, and maintenance of the LA30, itself, can be found in the

LA30

DECwriter Maintenance Manual, DEC-00-LA30-DA, Other publications and documents relevant to the LC8-E
are:

PDP-8/E & PDP-8/M Small Computer Handbook - D EC, 1 972
PDP-8/E Maintenance Manual, Volume 1

LA30 DECwriter Diagnostic, MAINDEC-8E-D2FA

DEC Engineering Drawing, DECwriter Control, E-CS-M8329-0-1

SECTION 2 INSTALLATION
The LC8-E DECwriter Control is installed on site by DEC Field Service personnel. The customer should not
attempt to unpack, inspect, install, checkout, or service the equipment.
Insert the LC8-E Control in the PDP-8/E OMNIBUS.

See Table 2-3, Volume 1, for information concerning

rtfcommended module priorities (the LC8-E is a "non-memory" option).

Connect the LC8-E to the DECwriter with the signal cable provided. J1 of the LC8-E, a 40-pin Berg Connector,
connects to module slot A02 of the LA30P logic rack.

See Chapter 2 of the LA30 DECwriter Maintenance Manual for additional information concerning system
installation and for procedures to be followed to checkout both the Control and the DECwriter.

SECTIONS DESCRIPTION
Figure 1-1

is a

block diagram of the LC8-E Control. Pin assignments for OMNIBUS signals and connector J1

signals can be found on engineering drawing no.

E-CS-M8329-0-1. Information concerning pin assignments of

the interconnecting cable is given in Section 5.

1-1

KYBD(0)L

OMNIBUS

DATA 4-11 L

KEYBOARD
TRANSMIT
LOGIC

lOT,

CONTROL
SIGNALS

XMIT STROBE L
BIT 1-7 L
SKIP L

INT RQST L

INTERNAL I/O L

C0L.C1L
TOT

I/O PAUSE L

TOT
INSTRUCTIONS

DECODER

MD 3-11 L

LOGIC

lOT,

INT/SKIP
LOGIC

CONTROL
SIGNALS

BIT 1-7

RCVR STROBE L
PRNT{0) L

PRINTER
RECEIVE

lOT,

CONTROL
SIGNALS

LOGIC

DATA 5-11 L

Figure 1-1

LC8-E Block Diagram

AC Register to the LA30 Printer Buffer
Register and transfer of data from the LA30 Keyboard Buffer Register to the AC Register. The transfer of data

The LC8-E has two distinct functions:

transfer of data from the CPU

to the LA30 Printer Buffer is carried out by the printer receive logic.
asserts the

When the LA30 is able to receive data, it

DEMAND signal. This signal sets the printer flag in the printer receive logic. The resulting PRNT (0) L

signal causes the INT/skip logic to assert

OMNIBUS INT RQST L if the LC8-E has been logically connected to

the interrupt system. Alternatively, PRNT (0) L can be tested by a program skip instruction in the INT/skip logic.
In either case, the computer ultimately proceeds to a program subroutine that begins the data transfer.

this subroutine is executed, the information is transferred from the

AC Register to the DATA 5—1

When

lines and

clocked into a 7-bit register in the printer receive logic. The register outputs are available at J1 as the

BIT 1-7 signals. The logic then generates a RCVR STROBE L signal that clocks the BIT 1-7 data into the
Printer Buffer Register, clears the Printer flag, and causes the LA30 to negate the

DEMAND signal.

The transfer of data from the LA30 Keyboard Buffer Register to the AC Register is carried out by the keyboard

When an LA30 key is depressed, information is applied, via the BIT 1—7 lines, to a 7-bit register
in the keyboard transmit logic. When the LA30 generates an XMIT STROBE L signal, the information is clocked

transmit logic.

into the 7-bit register and the

KYBD (0) signal is asserted. The KYBD (0) L signal can be tested in the INT/skip

logic with a skip instruction, or the interrupt system can be used to cause the program to enter an appropriate

subroutine.

When the subroutine is executed, the information is gated from the register in the keyboard transmit

logic to lines

DATA 5—1

(the logic asserts the

DATA 4 L signal separately so that the input character is comAC Register. The AC loaded and, simultaneously,

patible with the modified-ASCII Teletype® code), then to the

KYBD (0) L is negated.
teletype is a registered trademark of Teletype Corporation.
1-2

SECTION 4 DETAILED LOGIC
lOT DECODER LOGIC

1,1

The lOT decoder logic is shown in Figure 1-2. The LC8-E uses 12 IDT instructions, 6 for the l<eyboard functions
and 6 for the printer functions (one of the listed printer lOTs - Skip on Printer or Keyboard Interrupt - applies
to both functions).

More than one LA30 DECwriter can be interfaced to the PDP-8/E at the same time. The

LC8-E Control associated with each LA30 must have a unique device selection code. Therefore, the M8329
Control Module is fabricated with machine-inserted jumpers and solder terminals that allow the user to assign

any two of 64 possible device selection codes to a particular LC8-E (care should be taken when assigning device
selection codes to preclude multiple assignments of the same code).

Figure 1-2 illustrates the octal codes and

mnemonics that pertain when the LC8-E Control is manufactured. The octal codes and mnemonics are listed in
Table 1-1 and the respective functions, which remain constant regardless of the code or mnemonic, are detailed.
Figure 1-2 identifies the 12 machine-inserted jumpers, W1 through W12, and 6 groups, lettered from A to F, of

4 numbered solder terminals (jumper and terminal designations are etched on the quad module for each identification).

To change a control device selection code, first cut a selected "W" jumper (or jumpers); then, solder a

new jumper between designated terminals associated with the "W" jumper(s). For example, the device selection
code for the keyboard functions can be changed from 03 to 13 by removing W5 and connecting terminals C3 and
C4; the printer functions device code can be changed from 04 to 10 by removing W6 and W8 and connecting
terminals C2 and C4 and D2 and D3,

As Figure 1-2 shows, the device selection code signals, 603X and 604X, are applied to separate DEC 7442 Decoder
ICs.

The device operation codes represented by bits MD 9, 10, and 1 1 are then decoded by E9 and E6 to provide

the listed lOT instruction signals. Note that the device selection code signals assert the OMNIBUS INTERNAL
I/O L signal; thus, the positive I/O bus interface ignores the lOT instruction.

Three of the keyboard lOT instruction signals cause OMNIBUS "C" lines to be activated. When the KCC L
signal

generated, both the CO L and CI L signals are asserted; the resulting transfer of Os clears the AC Register.

The KRB L signal also results in a transfer to the AC; however, this transfer involves data from the keyboard,
rather than Os.

Finally, the KRS L signal causes only the CI L signal to be asserted; the result is an inclusive-OR

transfer of data to the AC.

1.2

PRINTER RECEIVE LOGIC

The printer receive logic is shown in Figure 1-3, The 7-bit register is shown only in part, the logic associated with
bits

DATA 10-6 being similar to that illustrated for bits

1 1

and 5. Significant signals are related by the timing

diagram in Figure 1-4. Refer to both figures when reading the logic description.

The LA30 printer routine is initiated by the program instruction TFL, Set the Printer Flag. At TP3 time of this
instruction,

NAND gate E7 is enabled, causing the PRNT flip-flop to be set. This flip-flop

DEMAND signal, which
signal rather than the

is asserted

is also

set by the

by the printer each time it completes a print cycle (Figure 1-4 illustrates this

TFL L signal).

If the

LC8-E is logically connected to the interrupt system, as Figure 1-4

and this discussion assume, PRNT (0) L causes the INT/skip logic to assert OMNIBUS INT RQST L. The program
proceeds to an interrupt servicing routine to determine the identity of the requesting device. The TSK instruction
in the routine causes the program to

jump to an LC8-E routine that determines if the printer or keyboard

requested the interrupt (other options are open to the programmer, this is but one example). Ultimately, the

LC8-E printer routine executes the TLS instruction.

1-3

— PJ *
o
t * 1- t
o o
o o
(0
«)
ID

(£>

<J-

*
O

(£

DO
o
03

Q
h-

O
CO

1-4

Table 1-1

LC8-E lOT Instruction List
Octal Code

Mnemonic

6030

KCF

Clear the Keyboard flag. Clears the KYBD flip-flop.

6031

KSF

Skip on the Keyboard flag. Senses the state of the KYBD

Function

flip-flop.

If the flip-flop is set,

increments the program

counter so that the next sequential instruction is skipped.

KCC

6032

Clear the flag, clear the AC. Clears both the KYBD flipflop and the AC Register.

KRS

6034

Read the keyboard buffer. Gates character information
from the keyboard transmit logic and ORs it into AC
Register bits 5 through 1 1

6035

KIE

KRB

Sets AC4.

Set/clear interrupt enable. Sets the INT ENA flip-flop if

AC1 1 is logic 1
6036

;

clears the flip-flop if AC1 1

logic 0.

Read the keyboard buffer, clear the flag, clear the AC.
Gates character information from the keyboard transmit
logic and jams it into

AC Register bits 5 through

1 1 .

Sets

AC4. Clears the KYBD flip-flop.

6040

TFL

Set the printer flag. Sets the PRNT flip-flop.

6041

TSF

Skip on the Printer flag. Senses the state of the PRNT
flip-flop.

If the flip-flop is set,

increments the program

counter so that the next sequential instruction is skipped.

6042

TCF

6044

TPC

Clear the Printer flag. Clears the PRNT flip-flop.

Load the printer buffer and print. Causes the character
information to be gated to the BIT 1—7 lines. Sets the

RCVR STROBE flip-flop. At TS2 of the next instruction,
the information is loaded into the LA30 input buffer.

TSK

6045

Skip on a keyboard/printer interrupt request. Skips the
next sequential instruction if the INT ENA flip-flop is set
(the LC8-E is logically connected to the interrupt system)

and if either the KYBD flip-flop or the PRNT flip-flop is
set.

TLS

6046

Load the printer buffer and print. Clears the flag. The
character information is gated to the BIT 1-7 lines. Sets

the RCVR STROBE flip-flop. At TS2 of the next instruction, the information

loaded into the LA30 input buffer.

Clears the PRNT flip-flop.

During TS2 of the TLS instruction, information is gated from the AC Register to the DATA lines and remains on
the DATA lines through TS3.

When TLS L is decoded in the lOT Decoder logic, it enables NOR gates E5B and
E5D (Figure 1-3). The enabled output of E5D causes the information on lines DATA 5—1 1 to be gated to the

D-inputs of the register flip-flops, while at the same time providing a high level on the D-input of E27B, the

RCVR STROBE L flip-flop. At TP3 time of the instruction the register flip-flops are clocked, flip-flop E27B is
set, and the PRNT flip-flop
cleared. The register data is applied, via the BIT 1—7 lines, to the printer buffer
is

1-5

During TS2 of the instruction following TLS, NAND gate E29 asserts the RCVR STROBE L signal

(flip-flop E27B is cleared at TP3 time of this instruction).

the

This signal loads the printer buffer register and negates

DEMAND signal. When the print cycle ends approximately 30 ms later, the DEMAND signal is again asserted

and a new transfer is begun.

BITS 2-6
SIMILAR

BIT 7

RCVR
"STROBE L

E29

E27B

E27A
C

J
E28

\^^^\

TLS L

TPC L

E5D V-1»

— -DATA 10-6 L-data'ii l

similar

d^j^' 5

B^tEM>^
PRNT (0) L

J E 9^
1

^ >^*°

E12

PRNT

INITIALIZE—•

E25A

u
Figure 1-3 Printer Receive Logic

1-6

DEMAND

T2
1

PRINT CYCLE

RJ30MS

DEMA^ in

PRI^JT

(0)

INT RQST

TSK

SKIP L

TS2

n
DATA 11-5

INSTRUCTION

xxxx

RCVR STROBE L

note:

T1,T2 and T3 are disllnct time periods.
The amount of time between periods
a function of program-routine

execution time

Figure 1-4 Tinning, Printer Receive Logic

1.3

KEYBOARD TRANSMIT LOGIC

The keyboard transmit logic is sliown in Figure 1-5. The 7-bit register is shown only in part. Significant signals
are related by the timing diagram in Figure 1-6. Refer to both figures when reading the logic description.
The user initiates the keyboard sequence by depressing a key on the LA30. The character information is placed
on the BIT 1-7 lines. After a period of time that allows the BIT lines to settle, the keyboard generates the

XMIT STROBE L signal. This signal clocks the information into the 7-bit register and sets the KYBD flip-flop.
If the

LC8-E is logically connected to the interrupt system, as assumed, KYBD (0) L causes the INT/skip logic to

OMNIBUS INT RQST L signal. The program proceeds to an interrupt servicing routine to determine
the identity of the requesting device. The TSK instruction in the routine causes the program to jump to an
assert the

LC8-E routine that determines if the printer or keyboard requested the interrupt. Ultimately, the LC8-E keyboard
routine executes the KRB instruction.

1-7

DATA 4 L

DATA 5 LDATA 6-10 L
SIMILAR

DATA 11 L-

E24
C

TP3

—

BITS 2-6
SIM LAR

KYBD (0) L

ji>-

—d E8B^
}
KRB —qL_—
KCC L

+ 3V

INITIALIZE

JE-0389

Figure 1-5 Keyboard Transmit Logic

When the KRB instruction is decoded, the lOT decoder logic generates the KRB L signal and activates the CO and
CI lines. The KRB L signal enables NOR gate E8D; the output signal from E8D gates the Information from the

DATA lines 5-1 1, and also causes NAND gate E18C to assert DATA 4 L. The DATA lines
AC Register and the information clocked into the register at TP3 time. Also at TP3, the KYBD

are gated to the

flip-flop is cleared, readying the logic for a new data transfer.

1.4

INT/SKIP LOGIC

The INT/skip logic is shown in Figure 1-7. The PRNT (0) L signal and the KYBD (0) L signal can cause program
skips when tested by instructions TSF and KSF, respectively.

The signals can also be tested by the TSK instrucENA flip-flop, E10, has been set, logically connecting the LC8-E to the interrupt system.
When E10 is set, the TSK L signal enables NAND gate E4D, which, in turn, enables AND-NOR gate E15 if
either the PRNT (0) L signal or the KYBD (0) L signal is asserted. Simultaneously, NAND gate El 7 asserts the
INTRQST L signal.
tion, provided the INT

The INT ENA flip-flop is set by the OMNIBUS INITIALIZE signal forthePDP-8 Family program compatibility.

To clear the flip-flop, removing the LC8-E from the interrupt system, load AC1 1 with logic
the KIE instruction.

The logic

and then program

AC1 1 keeps the DATA 1 1 L signal negated. Thus, the D-input of E10

remains high. At TP3 time, NAND gate E7 provides a clock pulse for E10, clearing the flip-flop. E10 can be set
at any time with the same instruction merely by loading AC1 1 with logic 1.

1-8

BIT

1-7 L,

XMIT STROBE

KYBD (0) L

INT RQST

DATA 11-4

CO L. CI

TP3.

Figure 1-6 Timing, Keyboard Transmit Logic

PRNT (0) L

INT ROST L

I/O PAUSE L

Figure 1-7 INT/Skip Logic

1-9

SECTIONS MAINTENANCE
Refer to Volume 1 and to the LA30 DECwriter Maintenance Manual for maintenance information that pertains
to both the LC8-E Control and the LA30 DECwriter.

The LA30 DECwriter Diagnostic, MAINDEC-8E-D2FA,

should be run when an error is suspected.

SECTIONS SPARE PARTS
Table 1-2 lists recommended spare parts for the LC8-E. These parts can be obtained from any local DEC office
or from DEC, Maynard, Massachusetts.

Table 1-2

LCB-E Recommended Spare Parts

DEC Part No.
19-10394

Description

Quantity

IC DEC 5384

19-10392

IC DEC 5380

19-10391

IC DEC 5314

19-10046

IC DEC 7442

19-9929

IC DEC 7417

19-9973

IC DEC 97401

19-9686

IC DEC 7404

19-9056

IC DEC74H00

19-9004

IC DEC 7402

19-5580

IC DEC 7450

19-5579

IC DEC 7440

19-5575

IC DEC 7400

19-5547

IC DEC 7474

10-1610

Capacitor, 0.01 mF, 100V, 20% Disk

10-0067

Capacitor, 6.8 /xF, 35V, 20% Tant

10-0024

Capacitor, 47 pF, 100V, 5%

70-8417

Signal Cable

1-10

PART 2
PAPER-TAPE READER/PUNCH

CHAPTER 2
PC8-E HIGH-SPEED PAPER-TAPE READER/PUNCH

SECTION 1

INTRODUCTION

The PC8-E (or the desk-top model, PC8-EB) Reader/Punch option consists of a control module and a high-speed
paper-tape reader/punch manufactured by DEC [Model PC04BL (60 Hz) or PC04BM (50 Hz)]

The control

(DEC M840) plugs into the PDP-8/E OMNIBUS and connects to the external reader/punch via two signal cables
that are supplied with the system.

The PC04 Reader/Punch is discussed here only to the extent necessary to fully describe control operation and
present supplementary information concerning installation and checkout. Details concerning the installation,

operation, troubleshooting, and maintenance of the reader/punch, itself, can be found in the PC04/PC05

Paper-Tape Reader/Punch Maintenance Manual [DEC-00-PCOA-D (1)]

Other publications and documents rele-

vant to the PC8-E are:

PDP-8/E & PDP-8/M Small Computer Handbook - D EC, 1 972
PDP-8/E Maintenance Manual, Volume 1
Roytron Model 500 Maintenance Manual
PC8-E Diagnostic, MAINDEC-8E-D2CA

DEC Engineering Drawing, Reader/Punch Control, E-CS-M840-0-1.

b.
c.

SECTION 2 INSTALLATION
The PC8-E Reader/Punch and Control is installed on site by DEC Field Service personnel. The customer should
not attempt to unpack, inspect, install, checkout, or service the equipment.
Insert the PC8-E Control Module in the PDP-8/E OMNIBUS.

Refer to Table 2-3, Volume 1, for information

concerning recommended module priorities (the PC8-E is a "non-memory" option).

Connect the control to the reader/punch with the two signal cables provided. J1 of the control, a 40-pin Berg
Connector, connects to reader/punch module slot B1, a DEC M955 Connector. J2 of the control connects to

module slot Al (refer to Section 5 for cable and connector pin assignments).
Prefer to Chapter 2 of the PC04 High-Speed Perforated Paper-Tape Reader/Punch Maintenance Manual

(DEC-00-HGPA-D) for additional information concerning system installation and for procedures to be followed
to checkout both the control and the reader/ punch.

2-1

SECTIONS DESCRIPTION
Figure 2-1

is a

block diagram of the PC8-E Control. The functions of the control can be grouped conveniently

according to reader functions and punch functions, as illustrated by the block diagram. Consider the reader
functions, represented by the logic blocks above the broken line.

The control logic generates signals that control the PC04 tape-feed operation. As the paper tape passes over the

PC04 photoarray, signals representing the punched characters are strobed into the Control Buffer Register. The
buffered information is then transferred to the PDP-8/E AC Register and operated on by subsequent program
instructions.

The tape-feed operation can be initiated under program control or by activation of the Reader FEED switch on
the PC04 front panel.

If the switch is used,

from the Control Buffer Register.

the tape feeds through the read station but data is not transferred

If data is to

be transferred, the tape-feed operation must be program-initiated.

Two lOT instructions, 6014 (Fetch Reader Character) and 6016 (Read Buffer, Fetch Reader Character), read the
information currently over the photoarray and then initiate tape feed.

When either of these instructions is

decoded by the lOT decoder logic, the read tape logic generates an ENABLE signal that triggers the clock logic.

The first CLOCK PULSE produced enables the read tape logic to generate an RDR DATA STROBE pulse. This
pulse clocks the RDR Buffer Register, loading the register with the information present on the READ HOLE 1-8
lines.

In addition to clocking the

RDR Buffer Register, the RDR DATA STROBE signal sets the RDR FLAG flip-flop
RDR RUN flip-flops in the tape read logic. If the control has been logically

in the INT/skip logic and clears the

connected to the computer interrupt system by a previous 6010 instruction, or by the INITIALIZE signal, the

OMNIBUS INT RQST L signal is asserted. The computer enters the interrupt servicing routine to determine the
identity of the requesting device.

The 601 1 instruction in the routine causes the computer to proceed to the

PC8-E subroutine to service the interrupt request (refer to Table 2-1 for lOT instruction descriptions).
After producing the first CLOCK PULSE, the clock logic generates a SHIFT PULSE. This causes the motor
control logic to provide stepping signals for the PC04 Reader Motor.

The motor shaft turns, feeding the tape

through the read station. After two steps, the next character on the tape appears over the photoarray; the current
read operation is completed.
is

If a

new 6014 or 6016 instruction has been issued, another RDR DATA STROBE

generated and this character is loaded into the RDR Buffer Register. Each RDR DATA STROBE loads a

character into the register.
tion.

If a

The register data is transferred to the CPU AC Register by the 6012 or 6016 instruc-

6014 or 6016 instruction is decoded between each RDR DATA STROBE and the next CLOCK PULSE,

reader operation is continuous, at a rate of 300 characters/second. Otherwise, the character rate is limited to

25 characters/second.

The tape status logic monitors the FEED HOLE signal from the PC04. When the tape-read mechanism is out of
tape, the tape status logic provides a signal that inhibits program generation of the motor stepping signals and
clears the tape read logic.

Now consider the punch functions, represented by the logic blocks below the broken line in Figure 2-1 The
.

punch motor operates continuously when power is applied to the PC04. The punch mechanism (Roytron Model
500) provides a PUNCH SYNC signal at the beginning of each punch mechanical cycle. This signal synchronizes
If a 6024 or 6026 instruction is decoded, the ENABLE PUNCH
BUFFER L signal is generated by the lOT decoder logic. Whatever information is on the DATA 4-1 lines can
now be clocked into the Punch Buffer Register. At TP3 time of the instruction the PUNCH STROBE signal
clocks the register, transferring the character signals from the DATA 4—1 1 lines to the HOLE 1—8 lines.

the control timing and the rotating motor shaft.

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Table 2-1

PC8-E lOT Instructions
Octal Code

6010

Mnemonic

RPE

Function
Set the INT ENA flip-flop.

The PC8-E is logically connec-

ted to the computer interrupt system.

6011

RSF

Skip on Reader flag. Senses the state of the RDR F LAG
If the flip-flop is set,

flip-flop.

the program counter is incre-

mented so that the next sequential instruction is skipped.

6012

RRB

Read the RDR Buffer Register. Causes the RDR Buffer
Register to be ORed into the AC Register, clears the RDR

FLAG flip-flop.
RFC

6014

Fetch a character from the tape. Clears the RDR FLAG
flip-flop, loads a character into the

RDR Buffer Register

from the tape, sets the RDR FLAG flip-flop when the

RDR Buffer Register is loaded.
RRB, RFC

6016

Microprogram of 6012 and 6014.

RDR Buffer Register

contents are ORed into AC Register, RDR FLAG flip-flop
is cleared,

character is loaded into Register, and RDR

FLAG flip-flop is set.
6020

PCE

Clear the INT ENA flip-flop.

The PC8-E is disconnected

from the computer interrupt system.
6021

PSF

Skip on Punch flag. Senses the state of the PUNCH FLAG
flip-flop.

If the flip-flop is set,

the program counter is

incremented so that the next sequential instruction is
skipped.

6022

PCF

6024

PPC

Clear the Flag. Clears the PUNCH FLAG flip-flop.

Load Punch Buffer Register, punch character. Transfers
the AC4-1 1 contents to the Punch Buffer Register,

punches the character, sets the PUNCH FLAG flip-flop

when done.
6026

PLS

Microprogram of 6022 and 6024. Clears the PUNCH

FLAG flip-flop, transfers AC4— 1 1 contents to the Punch
Buffer Register, punches the character, sets the PUNCH

FLAG flip-flop when done.

At the same TP3 time, the tape punch logic is prepared for the punch cycle. When the PUNCH SYNC signal is
generated at the start of the punch cycle, the tape punch logic asserts the PUNCH DONE signal. This signal
lasts for 10 ms, during which time the punch solenoid drivers are activated and the character is punched onto the

tape.

At the end of the PUNCH DONE signal, the PUNCH FLAG flip-flop is set.

If the

punch logic has pre-

viously been logically connected to the computer interrupt system, the PUNCH FLAG flip-flop asserts the

OMNIBUS INT RQST L signal. The computer enters the interrupt servicing routine to determine the identity of
the device.

The 6021 instruction in the routine causes the computer to proceed to the PC8-E subroutine to

service the interrupt request.

2-4

SECTION 4 DETAILED LOGIC
2.1

lOT DECODER LOGIC

Figure 2-2 shows the lOT decoder logic. Table 2-1
Bits IVID3-8 and I/O PAUSE

respectively.

lists the

PC8-E lOT instructions and a description of each.

L are gated to produce signals 601 X and 602X representing reader and punch lOTs,

Both signals cause the OMNIBUS INTERNAL I/O signal to be asserted, thereby ensuring that the

positive I/O bus interface ignores the lOT instruction.

The 601 X signal and bits MD9-1 1 are applied to the BCD-to-Decimal Decoder, E31 (refer to Appendix A,
Volume 1, for details); the decoder provides the reader JOT signals, as illustrated. The 602X signal and bits

MD9—

1 1

are applied to decoder E27, which provides punch lOT signals; in addition, the 602X signal causes the

ENABLE PUNCH BUFFER L signal to be asserted each time a punch lOT is generated.
2.2

TAPE READ LOGIC

The tape read logic is shown in Figure 2-3. This logic generates control basic timing signals in response to an lOT
instruction or a signal from the PC04 FEED switch.

Assume that the PC04 Reader motor is stopped (either the

reader is between blocks of characters or has just been put on-line).

When the tape is stopped, a character is always directly over the PC04 photoarray.

(Refer to Paragraph 4.1 of

the PC04 High-Speed Perforated Paper-Tape Reader/Punch Maintenance IVIanual for a detailed description of the
tape-feed operation.)

When an lOT instruction (6014, for example) is decoded, the control logic first causes the

character to be loaded into the RDR Buffer Register by the RDR DATA STROBE signal.

It then generates

stepping signals that cause the PC04 Reader Motor to turn.

Refer to Figure 2-3.

The 6014 L signal sets the RDR RUN flip-flop. Both the CLOCK PULSE L signal and the

RDR MOTOR STOPPING L signal are negated at this time; thus, the RDR ENA flip-flop is set via NAND gate
E5 (the clock logic is disabled until the ENABLE signal turns it on; the RDR MOTOR STOPPING L signal applies
only when the stepping signals are removed). The ENABLE signal generated by the 0-output of the RDR ENA
flip-flop initiates both the clock logic and the reader motor control logic.

The clock logic first produces a single

CLOCK PULSE that is applied to NAND gate E32 and to the C-input of the RDR ENA flip-flop. Because the
flip-flop D-input is high at this time, the flip-flop remains set. The NAND gate must be enabled if an RDR DATA
STROBE signal is to be generated. The second high input to this NAND gate is produced by either the (A-B) L
signal or the (A*B)

L signal (one of these two sync signals, generated by the reader motor control logic, is high

when the paper-tape holes are directly over the PC04; assume, for this discussion, that (A'B) L is asserted). The
negative pulse from E32 sets the R/S flip-flop. The FEED HOLE signal, produced by the PC04 photoarray,
The negative-going edge of E23's output resets the

enables the 1 -output of the R/S flip-flop to activate E23.

R/S flip-flop after a small delay determined by the RC network. Consequently, the RDR DATA STROBE signal
generated by NOR gate E35 is a narrow pulse (approximately 100-ns wide) and occurs only when the tape-feed
hole is over the photoarray.

The RDR DATA STROBE signal resets the RDR RUN flip-flop.

After the RDR DATA STROBE signal is generated, the clock logic produces a SHIFT PULSE that causes the
reader motor control logic to generate a stepping signal.

The tape holes move from over the photoarray; the

FEED HOLE signal and the (A-B) L signal are negated. The D-input of the RDR ENA flip-flop is now low. If
a 6014 L is not provided before the clock logic generates another

cleared, initiating a controlled motor-stopping operation.

CLOCK PULSE, the RDR ENA flip-flop is

The clock logic is disabled and the reader motor

The reader motor stops and the tape halts with the holes directly
over the photoarray. The FEED HOLE signal is again asserted and now the (A-B) L signal is high. The RDR
control logic generates a final stepping signal.

RUN flip-flop can be set by an lOT instruction any time after the RDR ENA flip-flop is cleared. However, the
RDR ENA flip-flop can be set again only after a 40-ms delay (the reader motor control logic asserts RDR
MOTOR STOPPING L for 40 ms after the RDR ENA flip-flop is cleared).
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RDR RUN flip-flop had been set by an lOT instruction before the second CLOCK PULSE occurred, the
RDR ENA flip-flop would remain set. The second CLOCK PULSE would then be followed by the second SHIFT
PULSE. At this SHIFT PULSE time the (A-B) L and the FEED HOLE signals are asserted. The third CLOCK
PULSE causes RDR DATA STROBE to be generated and the RDR RUN flip-flop is again cleared. Thus, a 6014
If the

or 6016 instruction must be decoded at least once for every other clock pulse in order to maintain a 300

character/second rate of operation.
Figure 2-4 is a timing diagram that illustrates the tape read logic signals, as well as those of the reader motor

The first clock period illustrated shows the RDR RUN flip-flop being cleared by
A 6014 lOT is decoded before the next CLOCK PULSE. However, between the third

control logic and the clock logic.

an RDR DATA STROBE.

and fourth CLOCK PULSES, no lOT is decoded and, therefore, the controlled motor-stopping operation is begun
(this is covered fully in Paragraph 2.4).

CLOCK PULSE

RDR DATA
STROBE
SHIFT PULSE L

ROTATE PULSE

(A-B) L

-H

(A'B) L

RDR RUN (1)

4—^

lOT 6014 L

+-t-

RDR ENA (1)"\"
ENABLE
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TP3

i
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RDR MOTOR STOPPING

ONE-SHOT

t^V

CATCH PULSE L

FEED HOLE

M"
ore approximate

Figure 2-4 Reader Timing

2-8

2.3

CLOCK LOGIC

The clock logic is shown in Figure 2-5. The logic consists of a ramp generator, a triggered free-running multivibrator, and two pulse-forming delay networks.

During continuous operation, the reader motor is stepped once every 1 .67 ms. However, when the motor must be
started from a dead stop, the inertia of the motor and the tape drive wheel must be overcome.

Initially, the shaft

turns more slowly, and, consequently, the tape moves over the photoarray more slowly than at continuous

operating speed. With each step of the motor the speed of the tape approaches continuous operating speed.

order to maintain a nearly constant ratio of tape speed to CLOCK PULSE frequency, the ramp generator, which
includes transistors 01 and 02, is used.

When the ENABLE signal is asserted by the tape read logic, the free-running multivibrator, 04/05, is triggered on
via 03.

At the same time, the ramp generator is triggered. The emitter of 02 provides the charging potential for

the multivibrator. This potential is initially such that the first CLOCK PULSE period is 5 ms.

The emitter

potential of 02 rises at a rate determined by the RC time constant, which can be varied by R27 (refer to

Paragraph 5.3.8 of the PC04 High-Speed Perforated Paper-Tape Reader/Punch Maintenance l\/lanual for adjust-

ment procedures). As the potential rises, the capacitors in the base circuits of 04 and 05 take less time to charge.
Thus, the on/off cycle of 04 and 05 decreases. Ultimately, when the ramp has ended, the CLOCK PULSE period
is 1 .67

ms.

The method used to generate the SHIFT PULSE L signal and the CLOCK PULSE signal is illustrated in Figure
2-6.

The RC delay circuits are used extensively in the control logic. Because the circuit in Figure 2-5 is more

detailed than others, it has been selected as an example of the technique.

explanatory.

2.4

The timing diagram is mainly self-

The RC delays indicated can be roughly calculated by using the formula Delay = 0.7 RC.

READER MOTOR CONTROL LOGIC

The reader motor control logic is shown in Figure 2-7.

(

Refer to Paragraph 4.1 .1 of the PC04 High-Speed

Perforated Paper-Tape Reader/Punch l\/laintenance l\/lanual for a detailed description of how the reader motor
control logic stepping signals control the reader motor.)
logic, the two one-shot multivibrators,

When the ENABLE signal is asserted by the tape read

E4 and E7, are readied for triggering. During continuous operation, the

clock logic generates SHIFT PULSEs, the first of which sets the PWR flip-flop, thereby asserting the POWER
signal.

Each SHIFT PULSE L signal generates a ROTATE PULSE that clocks the A/B end-around shift register.

At every other ROTATE PULSE either the (A-B) L signal or the (A'B) L signal is asserted, indicating to the tape
read logic that a character is over the photoarray.

RDR ENA flip-flop is cleared, the ENABLE signal is negated (provided the
The down-going edge of the ENABLE signal triggers E4 and E7 (Figure
2-4). After 2.6 ms, E4 times out and a CATCH PULSE L signal is generated. This pulse produces the ROTATE
If,

as explained in Paragraph 2.2, the

reader FEED switch is not activated).

PULSE that steps the motor a final time. The motor stops with either (A-B) L or (A-B) L asserted and the
FEED HOLE signal high.
The E7 one-shot remains set for 40 ms before timing out. During this 40-ms period, the RDR MOTOR

STOPPING L signal is asserted and prevents the RDR ENA flip-flop from being set. At the end of the period,
the 0-output of E7 clears the PWR flip-flop, negating the POWER signal. Reader operation can be restarted by
again setting the RDR ENA flip-flop.

The 40-ms delay provided by E7 ensures that the motor, if not pulsed for continuous operation, has sufficient
time to come to a complete stop before it is activated again.

If the

complete stop were not allowed, undesirable

oscillations in the drive motor would result, causing possible false data outputs.

2-9

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1.67 MS

MULTI OUT

E5, PIN

E5, PIN 2

CLOCK PULSE

ElB, PIN

11
I

E1A, PIN 5

E1A. PIN 4
I
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SHIFT PULSE L

foZ/JiS

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150r
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H
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Figure 2-6 Clock/Shift Pulse Timing

2.5

RDR INT/SKIP LOGIC

The RDR INT/skip logic is shown in Figure 2-8. When an RDR DATA STROBE signal is generated it sets the

RDR FLAG flip-flop (the RDR RUN flip-flop provides the necessary high at E12's D-input before being cleared,
itself, by RDR DATA STROBE). Because RDR DATA STROBE also loads the RDR Buffer Register, the RDR
FLAG flip-flop being set indicates that the control is ready to transfer data. If the INT ENA flip-flop has been
set previously, either under program control or by INITIALIZE, the OMNIBUS INT RQST L signal is asserted.
When the computer enters the PC8-E servicing subroutine, an appropriate lOT instruction reads the Buffer
Register and clears the RDR FLAG flip-flop via

2.6

NOR gate El.

RDR BUFFER LOGIC

The reader buffer logic is shown in Figure 2-9. Data supplied on the READ HOLE 1-8 lines is clocked into the
register by the RDR DATA STROBE signal. Either 6012 L or 6016 L gates the character onto the OMNIBUS

DATA 4-11 lines. At the same time, the lOT instruction asserts the OMNIBUS 01 L signal, resulting in an
ORing of the DATA 4-1 bits and the CPU AC Register contents.
1

2.7

TAPE STATUS LOGIC

The tape status logic is shown in Figure 2-10. The logic monitors both the FEED HOLE signal and the RDR ENA
flip-flop, generating an OUT OF TAPE signal when tape is not loaded in the PC04 Tape Feeder. This signal
ensures that the tape read logic cannot be triggered by a program instruction read command. The complementary
signal,

HAVE TAPE, is generated when tape is in the feeder, enabling the tape-feed operation to begin when

program-directed.

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no tape has been inserted in the feeder, the FEED HOLE signal is high, just as it is when an actual feed hole is

detected by the photoarray.

The RDR FEED HOLES one-shot, E19, is in its stable state; thus, the OUT OF

TAPE signal is asserted.

read command is issued by the program, the RDR RUN flip-flop (Figure 2-3) is pre-

If a

vented from being set by the HAVE TAPE signal that is low at this time. Therefore, the RDR ENA flip-flop is
not set and the clock logic is not triggered.

When a tape is inserted in the feeder, the photoarray light source rays are interrupted briefly by the tape web.
The FEED HOLE signal goes low, and the negative-going edge causes one-shot E19 to be triggered; thus, the

HAVE TAPE signal asserted. At the same time that E19 is triggered, the flip-flop consisting of the cross-coupled
NOR gates cleared. Because the RDR ENA flip-flop also clear, flip-flop E23 latched in the clear state.
NAND gate El 7 enabled; the resulting low at pin of E19 holds the one-shot in the triggered state, i.e., the
the program does not issue a read
-output stays high. The HAVE TAPE signal remains high indefinitely,
is

1 1

command.

When a read command is issued, the RDR RUN flip-flop is set, causing the RDR ENA flip-flop to be set, also.
The 0-output of the RDR ENA flip-flop triggers the clock logic, which generates a CLOCK PULSE, and sets

NAND gate El 7. The one-shot enters the timeout state, during which can be retriggered by each trailing edge of the FEED HOLE signal. A ROTATE PULSE, generated by the clock logic
approximately 2 us after the CLOCK PULSE (Figure 2-4), causes the tape to begin feeding through the read
flip-flop E23, which disables

station.

The resulting negative transition of the FEED HOLE signal re-triggers the one-shot (note that flip-flop

E23 is held in the set state by the 0-output of the RDR ENA flip-flop).

If another trailing edge occurs within

10 ms, the one-shot is again re-triggered (a 10-ms period is necessary because the reader motor is being started

from a dead stop and, consequently, the tape moves more slowly than at continuous operating speed; in continuous operation, a trailing edge occurs at 3.34-ms intervals).

If the

program issues read commands at such a rate

DATA STROBE and the next
TAPE
signal remains asserted.
CLOCK PULSE), one-shot E19 is re-triggered continuously, and the HAVE

that continuous operation results (at least one command between each RDR

Suppose that at some point during this continuous operation a read command is not issued within approximately
3.34 ms of the preceding command. In such a situation, the motor-stopping operation is initiated. At the

moment this operation begins, the RDR ENA flip-flop is cleared, and the FEED HOLE signal is low. Therefore,
flip-flop E23 is again latched in the clear state, and one-shot E19 is held in its triggered state.

The HAVE TAPE

signal remains high while the motor is stopped,

read commands are issued at a continuous rate and the tape runs out of the tape feeder, the OUT OF TAPE

signal

must be asserted. When the last portion of tape web uncovers the light source, the FEED HOLE signal

goes high and remains high. One-shot E19 times out approximately 8.5-ms later, and the OUT OF TAPE signal
goes high. During this 8.5-ms period, three RDR DATA STROBE pulses occur. Each of these pulses loads the

Reader Buffer with Is. Consequently, at least two transfers, possibly three, of Is to the AC Register take place
before the RDR RUN flip-flop is cleared and the clock logic is disabled.

2.8

TAPE PUNCH LOGIC

When the punch ON/OFF switch is in the ON position, the punch motor runs continuously. A tape that is loaded

FEED switch is in the FEED position, or if the program
issues a punch command lOT instruction, 6024 or 6026. Either method results in the PUNCH DONE signal
in the punch feeder mechanism can be punched if the

being generated in the tape punch logic (Figure 2-11).

2-16

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When the 6026 lOT instruction is issued, for example, the PUNCH RUN flip-flop, E10, is set. Setting ETO causes
the D-input of the SYNC PUNCH REQ flip-flop, E14, to go low.

A PUNCH SYNC signal from the tape punch
mechanism can clear E14, thereby triggering the PUNCH BUSY one-shot, E15. This PUNCH SYNC signal occurs

once during each punch motor revolution and signals the start of the punch mechanical cycle. The signal is
applied to the Schmitt trigger, Q9 and Q10, and the output at the collector of Q10 clears E14.

The resulting

10-ms PUNCH DONE signal enables the PC04 solenoid drivers to activate the punch mechanism. The tape is
punched with the character that was placed on the HOLE 1—8 lines by the punch buffer logic, shown in Figure
2-12 and discussed briefly in Paragraph 2.9.

2.9

PUNCH BUFFER LOGIC

The punch buffer logic is shown in Figure 2-12. Either the 6024 L signal or the 6026 L signal enables the Buffer
Register to be loaded at TP3 time with the information carried on the

DATA 4—1

lines.

This information is

then gated to the HOLE 1—8 lines, respectively. Note that the information loaded at this time remains in the
register until another punch instruction is issued or until the

2.10

FEED switch is activated.

INT/SKIP LOGIC

After the tape has been punched and the punch mechanical cycle ends, the PUNCH BUSY one-shot times out. The

PUNCH RUN flip-flop is cleared and the 0-output of the flip-flop sets the PUNCH FLAG flip-flop (Figure 2-13).
If the INT ENA flip-flop, E14, is set at this time, the OMNIBUS INT RQST L signal is asserted. The computer
enters the interrupt routine and proceeds from there to the punch subroutine.

SECTION 5 MAINTENANCE
Refer to Volume 1 and the PC04 High-Speed Perforated Paper-Tape Reader/Punch Maintenance l\/lanual for

PC8-E maintenance Information.
Table 2-2 presents cable and connector pin assignments for the two cables that connect the control and the PC04.

SECTION 6 SPARE PARTS
Table 2-3 lists recommended spare parts for the PC8-E. These parts can be obtained from any local DEC office
or from DEC, Maynard, Massachusetts.

2-18

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Table 2-2

Cable/Connector Pin Assignments

M955 Connector

Signal Name

Control Connector

J2 (Connects to A1)

PUNCH FEED SWITCH

N/C

SCR ACTIVE

RDR ON/OFF LINE

PUNCH SYNC

GND
READ HOLE
READ HOLE 2
READ HOLE 3

C
D

J1 (Connects to B1)

N/C

PUNCH DONE
PUNCH NOT UP TO SPEED

HOLE 6
HOLE 5

Z
BB

COIL BIAS

HOLE 4

HOLES

HOLE 2
HOLE 1

NN
RR
TT

N/C
N/C
N/C

READ HOLE 4
READ HOLE 5
READ HOLE 6
READ HOLE?
READ HOLES
FEED HOLE

HOLES
HOLE?

T
V
X

H
J

K
L

M
M

BA(0)
BA(1)
BB(0)
BB (1)

R
S

POWER
RDR FEED SWITCH

GNDPINS
A, B, C, E, H, K, M, P,S,

U,W, Y, AA, CO, EE, HH,
KK, MM, PP, SS, UU, VV

Table 2-3

PC8-E Recommended Spare Parts

DEC Part Number

Description

19-0554?
19-055? 5

IC DEC ?4?4

19-055?6

ICDEC?410
IC DEC 384
IC DEC 9601
IC DEC ?404
IC DEC 6380
IC DEC 6314
ICDEC9?401
IC DEC 8251
IC DEC ?440
ICDECMC4015P

19-09486
19-0948?

19-09686
1

9-099? 1

19-099?2

19-09973

19-09594
19-055?9
19-1008?
15-03409
15-09338
11-00113
11-00114
10-01610

IC DEC ?400

Quantity

Transistor, 6543 D
Transistor, PMS 6531

Diode, D662

Diode, D664

Capacitor, 0.01 ixF, 100V, 20%

2-21

PART 3
X/Y PLOTTER

CHAPTER 3
XY8-E PLOTTER CONTROL

SECTION 1

INTRODUCTION

The XY8-E Plotter Control interfaces a digital incremental plotter with the PDP-8/E. The XY8-E operates with a
variety of plotters, both encoded and unencoded types, to display data on paper or film. All XY8-E logic is con-

tained on a single quad module that plugs into the OMNIBUS.

The XY8-E connects to the incremental plotter

with a signal cable that is supplied.

The XY8-E transmits directions to the plotter that originate in the computer AC Register. Data is transferred in
six parallel bits that cause pen or drum movement (the plotter can be either a drum or flatbed type) in the plotter.

All plotter operations, except the setting of the coordinates at which plotting begins, are guided by the XY8-E

logic and the CPU.

A series of functions, specified by lOT instructions, initialize the XY8-E logic, initiate plotter

operation, and generate program interrupts to indicate completion of the operation.

The XY8-E will interface readily with any of the following incremental plotters:
a.

CalComp Plotters - Series 500, 600, 700, and 800.

Houston Instruments Plotters - Types 6400, DP-1, and DP-10.

Four Plotter Control/plotter systems, featuring plotters from those listed, are offered by DEC. Details concerning
installation, operation, troubleshooting, and maintenance of these plotters can be found in the respective CalComp

or Houston Instruments instruction manual.

DEC publications and documents relevant to the XY8-E are:

PDP-8/E & PDP-8/M Small Computer Handbook -DEC, 1972
PDP-8/E Maintenance Manual, Volume 1
XY8-E Plotter Control and Display Diagnostic, MAINDEC-8E-D6AB

DEC Engineering Drawing, Plotter Control, E-CS-M842-0-1

SECTION 2 INSTALLATION
The XY8-E Plotter Control is installed on site by DEC Field Service personnel. Customers should not attempt to
unpack, inspect, install, checkout, or service the equipment.
Insert the XY8-E Control Module in the PDP-8/E OMNIBUS.

Refer to Table 2-3, Volume 1, for information con-

cerning recommended module priorities (the XY8-E is a "non-memory" option).

Connect the Plotter Control to the plotter with the signal cable provided (if the plotter is one of those listed in
Section 1).

If the

plotter is an unencoded type, J2 of the Plotter Control, a 40-pin Berg Connector, connects to

the plotter 19-pin Cannon Plug; if the plotter is an encoded type, J1 of the Plotter Control connects to the plotter

Cannon Plug (refer to Section 5 for cable and connector pin assignments).

3-1

The XY8-E can be checked for correct operation by running the diagnostic program, MAINDEC-8E-D6AB.
Refer to the plotter instruction manual for checkout procedures for the plotter itself.

SECTIONS BLOCK DIAGRAM
Figure 3-1

is a

block diagram of the XY8-E Plotter Control. Programmed lOT instructions are decoded by the

lOT decoder logic.

Signals representing the lOT instructions are then applied to the timing logic, the interrupt/

skip logic, and the direction transfer logic.

OMNIBUS
SIGNALS
INITIALIZE
SKIP L

INT RQST L

INTERRUPT/
SKIP LOGIC

6500

DIRECTION REGISTER
OUTPUT

6501

6502
6506
6507

INTERNAL I/O L
I/O PAUSE L

lOT

MD 3-11 L
TP3

DECODER

SET

FLAG L
DIRECTI ON

TRANSFER
LOGIC

LOGIC

6503L
6504L
6505L
6506L
SELECT

(ENCODED PLOTTER

OUTPUT

(UNENCODED PLOTTER
OUTPUT)
TIMING
LOGIC

CLR REGISTER L

DATA 6-11 L

Figure 3-1

XY8-E Block Diagram

Plotter directions are gated from the AC Register via the

DATA 6-1

lines to a 6-bit Decision Register in the

direction transfer logic. The Direction Register outputs are transferred to the plotter, which begins the directed

operation.

At the same time, the timing logic is triggered; after a delay period the timing logic generates a signal,

CLR REGISTER L, that clears the Direction Register, readying it for the next direction. After a further delay
period that ensures completion of the direction by the plotter, the timing logic generates the SET FLAG L
signal. This signal is applied to the interrupt/skip logic where it sets the PLOTTER FLAG flip-flop. This action
causes the Plotter Control to request a program interrupt, resulting in the transfer of another direction from the

AC Register.

3-2

SECTION 4 DETAILED LOGIC
3.1

lOT DECODER LOGIC

The lOT decoder logic is shown in Figure 3-2. The I/O PAUSE L signal gates bits MD3— 8 to generate the

SELECT signal that indicates an XY8-E instruction has been decoded. See Table 3-1 for the XY8-E instruction
list

and a description of each instruction.

Table 3-1

XY8-E lOT Instruction List
Octal Code

Mnemonic

6500

PLCE

Clear the

6501

PLSF

Skip on the Plotter flag. Senses the state of the PLOTTE R

Function
1

NT ENA flip-flop.

FLAG flip-flop. If the flip-flop is set, the program counter
is

incremented so that the next sequential instruction is

skipped.

6502

PLCF

Clear the PLOTTER FLAG flip-flop.

6503

PLPU

Pen up. Raises the plotter pen from the surface of the graph
paper (unencoded plotters only).

6504

PLLR

Load Direction Register, clear Direction Register, set Plotter
Loads the Direction Register from AC06— 1 1 (see Table

flag.

3-2 for the list of directions), clears the register after the
plotter has had enough time to carry out the direction, sets

the PLOTTER FLAG flip-flop.

6505

6506

PLPD

Pen down. Lowers the pen to the surface of the graph paper
(unencoded plotters only).

PLCF,

Microprogram of 6502 and 6504. Clears the PLOTTER

FLAG flip-flop, loads the Direction Register, clears the

PLLR

Direction Register, sets the PLOTTER FLAG flip-flop.

6507

Set the INT ENA flip-flop.

PLSE

The SELECT signal asserts the OMNIBUS INTERNAL I/O L signal that directs the positive I/O bus interface to
ignore the lOT instruction; also, it gates bits
(see Appendix A, Volume 1, for details).

MD9—

1 1

to provide inputs for E21, the BCD-to-decimal decoder

With one exception, E21 provides the signals that represent the XY8-E

lOT commands. The exception is the signal that represents the 6501 instruction, Skip on the Plotter Flag. Note
that the lOT signals generated by E21 are produced at TP3 time.

However, the OMNIBUS SKIP L signal is

sampled at TP3 time by the CPU skip logic. Therefore, the XY8-E Plotter Control must assert the SKIP L signal
before TP3 time; this is the reason for generating the 6501 L signal separately.

3-3

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3-4

3.2

TIMING LOGIC

The timing logic is shown in Figure 3-3. This logic generates delay periods that allow the plotter to carry out the
direction contained in the Direction Register.

The delay periods are initiated simultaneously with the loading of

When the first delay ends, the Direction Register is cleared; when the second delay ends,

the Direction Register.

the PLOTTER FLAG flip-flop is set. Then, if the XY8-E is logically connected to the computer interrupt system,
a program interrupt is requested and another direction is transferred from the

AC Register to the Direction

Three one-shot multivibrators are shown in Figure 3-3. For directions other than Pen Up/Pen Down, only oneshots El and E7 are triggered.
Register, triggers both El

Either the 6504 L or the 6506 L signal, in addition to clocking the Direction

and E7. The plotter begins the directed operation and the direction remains in the

At this time, El times out and the CLR
REGISTER L signal is asserted. This signal is applied to the direction transfer logic and clears the Direction

Direction Register for 3.3 ms (an arbitrary but optimal period of time).

E7 times out after 7.5 ms (more than enough time for the plotter to carry out the mechanical opera-

tion), causing the SET

FLAG L signal to be asserted. This signal is applied to the interrupt/skip logic. Figure 3-6,

where it sets the PLOTTER FLAG flip-flop.
If the direction to

be carried out by the plotter is either Pen Up or Pen Down, the third one-shot, E4, is triggered.

This situation is illustrated by the timing diagram. Figure 3-4.

The timing shown applies to an encoded plotter.

However, an unencoded plotter could be represented by replacing the 6504 L/6506 L signal with either 6503 L
or 6505 L.

If the Pen

Up direction is to be carried out by an encoded plotter, for example, AC Register bits 6-1

must be loaded with octal code 31 (Table 3-2). This code is placed on the DATA 6—1 1 lines and loaded into the
Direction Register by the leading edge of the 6504 L/6506 L signal. At the same time,
3-3, is enabled, and both El

NAND gate E3A, Figure

and E7 are triggered. DR1 1 is set, enabling NOR gate E3B to trigger one-shot E4.

As before, the CLR REGISTER L signal is asserted after 3.3 ms. However, the SET FLAG L signal, rather than
occurring after 7.5 ms, is delayed for 72.7 ms. This period of time is required to satisfy the plotter's pen stabilizing time.
If the

Note that one-shot E7 is superfluous in this operation.

Pen Up instruction, 6503, is issued for an unencoded plotter, E4 is triggered in essentially the same way as

for the encoded plotter.
triggers El

The 6503 L signal dc-sets DRl 1,

NOR gate E3 is enabled, triggering E4 which, in turn,

(E7 is not triggered in this situation). The two delays generated carry out their respective functions as

detailed earlier.

3.3

DIRECTION TRANSFER LOGIC

The direction transfer logic is shown in Figure 3-5. Directions are placed on the DATA 6-1 1 lines from the AC
Register by lOT instruction 6504 or 6506.

At TP3 time, the 6504 L signal or the 6506 L signal loads the

Direction Register. Separate transistor driver outputs are provided for encoded and unencoded plotters; unen-

coded outputs undergo a transition from -15V to -i-5V, while encoded outputs go from ground to +15V. The
Direction Register is cleared by the INITIALIZE signal that is asserted both at power turn-on and by the CAF

(6007) instruction.

3.4

INTERRUPT/SKIP LOGIC

The interrupt/skip logic is shown in Figure 3-6. The Plotter Control is logically connected to the computer interrupt system when the INT EN A flip-flop is set.

The flip-flop is set under program control by the 6507 (PLSE)
lOT instruction or by the 6007 (CAF) lOT instruction that asserts the INITIALIZE signal; in addition, the
INITIALIZE signal sets the flip-flop at power turn-on. The XY8-E is disconnected from the interrupt system by

the 6500 (PLCE)

lOT instruction that clears the flip-flop under program control.

3-5

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3-7

Table 3-2
List of Plotter Directions

Direction

AC06-11

Encoded Plotter

Unencoded

Octal Code
Plotter

Pen up

02
04

Pen down

Drum up
Drum down

—

Pen left

12
13

14
15

21-27
30
31

33
34
35
36
37

41-47
50
51

52
53

54
55
56
57

61-67
70
71

72
73

74
75
76
77

Paper

Film

—
-

—
+y
+x+y
+x

+y
+x+y
+x
+x-y

+x-y
-y

-y

-x-y
-x

-x-y
-X

-x+y

—
—

—
—
—
—
—
—
—
-

Pen up
Pen down

CRT shift
Beam off
Beam on

Start zip

Block code

-z(+Aux 1)

Plot code

+z (+Aux 2)

Start incr

Sync

Pen right

—
—
—
—
—
—
—

+y/2
+x/2+y/2
+x/2
+x/2-y/2
-y/2
-x/2-y/2
-x/2

-x/2+y/2

+x+y/2
-x+y/2
+x/2+y
-x/2+y
+x-y/2
-x-y/2
+x/2-y

-x/2-y

3-8

—

Q
CO

3-9

6501

Ell

b— SKIPL

T RQST L

6500 L

6507 L

SET FLAG L

INITIALIZE

Figure 3-6 INT/Skip Logic

When the INT ENA flip-flop is set, the OMNIBUS INT RQST L signal can be asserted by the PLOTTER FLAG
flip-flop. The PLOTTER FLAG flip-flop is set by the SET FLAG L signal when a direction has been carried out
by the plotter. The computer identifies the requesting device by entering the interrupt servicing routine. The
6501 (PLSF) lOT instruction in the routine directs the computer to the XY8-E subroutine and another direction
is

transferred to the Direction Register,

The PLOTTER FLAG flip-flop is cleared under program control by the

6502, 6506, and 6007 (via the INITIALIZE signal) lOT instructions, as well as at power turn-on by INITIALIZE.

SECTION 5 MAINTENANCE
The relative simplicity of the XY8-E logic precludes the necessity of a detailed maintenance procedure. Use the
diagnostic program to isolate problems that occur in the XY8-E Plotter System. Standard troubleshooting techniques, using the logic drawings and an oscilloscope, will enable the technician to isolate faulty components.

Table 3-3 shows the connector pin assignments for the Plotter Control/plotter interconnecting cable.

SECTION 6 SPARE PARTS
Table 3-4 lists the recommended spare parts for the XY8-E. These parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.

3-10

Table 3-3
Pin Assignments, Interconnecting Cable
Signal Name

From
Cannon 19-Pin

Significant For

Berg 40-Pin

Unencoded Plotter Only

Connector Pin

CalComp Plotter

Houston Inst. Plotter

CHART RIGHT (-X)
CHART LEFT (+X)

DRUM UP(-X)
DRUM DOWN (+X)

3
4

CARRIAGE UP(+Y)
CARRIAGE DOWN (-Y)

9
10

PEN UP
PEN DOWN

PEN LEFT(+Y)
PEN RIGHT (-Y)
PEN UP
PEN DOWN

GND

Pins 5-8, 11-14,

L
J

D
R

N
S
PinsT, V, X, Z, BB, DD,

16-19 not used

FF,JJ, LL, NN, RR,TT,
not used
Pins A, B, C, E, H, K, M,
P, S,

U, W, Y, AA, CC,

EE, HH, KK, MM, PP,
88, UU, VV are gnd.

Table 3-4

XY8-E Recommended Spare Parts

DEC Part Number

Description

15-03409-1

Transistor DEC 6534B

15-03100
19-09705
19-09704

Transistor DEC 3009B

IC DEC 8881
IC DEC 314

19-09686

IC DEC 7404

19-09594

IC DEC 8251

19-09373

IC DEC 9601

19-09485

IC DEC 380

19-05577

IC DEC 7420

19-05576

IC DEC 7410

19-05575

IC DEC 7400

19-05547

IC DEC 7474

13-000391

Resistor 1.5K, 1/4W, 5%

3-11

Quantity

PART 4
LINE PRINTER

CHAPTER 4
LE8-E

SECTION 1

LINE

PRINTER

INTRODUCTION

The LE8-E Line Printer Control interfaces an 80- or 132-column line printer to the PDP-8/E.
tained on a single quad module that plugs into the OMNIBUS.

All logic is con-

The LE8-E connects to the line printer via a

signal cable that is supplied with the system.

The LE8-E Line Printer is discussed here only to the extent necessary to both fully describe LE8-E operation and
present supplementary information concerning installation and checkout. Details concerning the installation,

operation, troubleshooting, and maintenance of the printer itself can be found in Data Products Corporation

Technical Manual DPC-214163A (80-column printer) or DPC-215656A (132-column printer). Other publications

and documents relevant to the LE8-E are:

PDP-8/E & PDP-8/M Small Computer Handbook - D EC, 1 972
PDP-8/E Maintenance Manual, Volume 1
LE8-E Line Printer Diagnostic, MAINDEC-8E-D2BA

DEC Engineering Drawing, Line Printer Control, E-CS-M841-0-1.

SECTION 2 INSTALLATION
The LE8-E Line Printer and Control are installed on site by DEC Field Service personnel. The customer should
not attempt to unpack, inspect, install, checkout, or service the equipment.

4.1

UNPACKING

Place the LE8-E Line Printer close to the ac power source and proceed as follows:

Procedure

Step
1

Cut the two steel straps that secure the telescoping cap and stitched sleeve to
the shipping skid.

Remove the Tri-wall clips from all four sides of the stitched sleeve.
Remove the four bolts, washers, and nuts securing the line printer to the
shipping skid, then remove the printer from the skid and install on the site.

(continued on next page)

4-1

Procedure

Step

Unpack the LE8-E Control and the signal cable. Plug the LE8-E Into the PDP-8/E

OMNIBUS and connect it to the line printer with the cable (refer to Table 2-3, Volume 1,
for information concerning module installation order).

The cable connects to the

control via a Berg Connector and to J1 of the line printer via a Winchester MRAC-50

Connector (refer to Section 1 of the Data Products Corporation technical manual for
the location of J1).

Inspect both printer and control as outlined below and report any damage to the local

DEC sales office.
a.

Inspect external surfaces of the printer and control for surface, bezel,
switch, and light damage.

Open the printer doors and inspect for internal damage.

Inspect the wiring side of the printer logic mounting panels and the control
module for bent pins, cut wire, loose external components, and foreign
matter. Also inspect the signal cable for damage.

4.2

Check equipment received against the packing list to be certain that all
equipment has been unpacked.

CHECKOUT

Use the following procedure to check out the LE8-E Line Printer and Control.
Step
1

Procedure
Insert the ribbon in the printer, following the ribbon installation procedure detailed in

Section 3 of the Data Products Corporation technical manual (referred to hereafter as
the technical manual).

Load the printer with continuous-form paper, following the paper loading procedure
detailed in Section 3 of the technical manual.

NOTE
The READY indicator on the printer control panel
should light 10—15 seconds after the last step of the
procedure (close and latch drum gate, etc.) has been
completed.

See the paper positioning (vertical) procedure in Section 3 of the technical manual.

Check that the TOP OF FORM and PAPER STEP switches operate as in Table 3-1 of
the technical manual.

Set the ON LINE/OFF LINE switch to the ON LINE position and check that the TOP

OF FORM and PAPER STEP switches do not operate.
6

Hold the MASTER CLEAR switch in the "up" position and check that the READY

and ON LINE indicators go out. Release the switch; the READY indicator should light.
7

Check the right tractor for correct adjustment and make sure that the COPI ES

CONTROL switch
8

set to the 1-2 position.

Set the ON LINE/OFF LINE switch to the ON LINE position and run the MAINDEC
diagnostic program, starting at Part 1 of Test 1

While the program is running, adjust

the vertical paper adjustment vernier.

(continued on next page)

4-2

Procedure

Step

Stop the program and set the PRINT INHIBIT switch to the "up" position; set the
ON LINE/OFF LINE switch to the ON LINE position and restart the program from

Part 1 of Test 1.

run as in Step 8.

The PRINT INHIBIT indicator should light and the program should
Run the program for one minute.

Set the PRINT INHIBIT switch to the "down" position and check for printout errors.

Replace the continuous-form paper with single-part paper.

Run all parts of the program

(except Part 1 of Test 1) for one hour.
Inspect all printouts for errors and print quality and compare to the enclosed factory-

printed samples.

SECTION 3 BLOCK DIAGRAM DESCRIPTION
Figure 4-1

a block diagram of the

LE8-E Control.

OMNIBUS pin numbers and pin assignments for both ends

of the signal cable can be found on engineering drawing E-CS-M841-0-1. Connector receptacle J1 on the line
printer is a 20-pin connector with a return pin for each of the 10 signal pins.

the control; Table 4-1 presents the LE8-E lOT instructions.

OMNIBUS

F'DP-8/E
INT

[""

Figure 4-2 is a timing diagram of

Refer to the figures while reading this description.

LE8-E LINE PRINTER

LE8 -E CONTROL

RQST L
SKIP L

6661.6662
5663,6666

SKIP
LOGIC

INITIALIZE

Jl
i

(DEMAND)

(READY)

1
1

MD3-11 L
I/O

SELECT

PAUSE L

INTERNAL

LOGIC

666 2,6665
6666,6667

INTERRUPT
1

LOGIC

I/O L

6664
6666

SE _ECT L__

(STROBE)

DATA

TRANSFER

DATA 5-11 L

LOGIC

TP3

R.V.z:n(D*TA1-7)

L_.

Figure 4-1

LE8-E Line Printer Control Block Diagram

When the line printer is ready to be placed on-line, a READY indicator on the line printer lights. At the same
time, the

READY signal

is asserted.

After the line printer has been placed on-line, it asserts the DEMAND signal

when it is able to accept a character. The DEMAND signal sets the FLAG flip-flop in the interrupt logic.

If the

INT ENA flip-flop is set, the FLAG flip-flop asserts the OMNIBUS INT RQST L signal. The computer then
begins to execute the interrupt servicing routine to determine the identity of the requesting device.

4-3

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4-4

Table 4-1

LE8-E lOT Instruction List
Octal Code

6661

Mnemonic

Function
Skip on the Flag. Senses the state of the FLAG flip-flop.

PSKF

If it is set,

the program counter is incremented so that the

next sequential instruction is skipped.

6662

PCLF

Clear the Flag. Clears the FLAG flip-flop.

6663

PSKE

Skip on an Error. Senses the state of the READY signal.
If it is

low, indicating an error condition in the line

printer, the program counter is incremented so that the

next sequential instruction is skipped.

6664

PSTB

Load Line Printer Buffer Register.

A character is trans-

ferred from the CPU AC Register, via the OMNIBUS

DATA 5-11 lines and the Line Printer DATA 1-7 lines,
to the Printer Buffer Register.

6665

Set INT ENA flip-flop.

PSIE

The LE8-E is logically connected

to the computer interrupt system. Both the READY
signal and the

DEMAND signal can cause a program inter-

rupt.

6666

PCLF, PSTB

Clear the Flag, Load Line Printer Buffer Register. Micro-

program of 6662 and 6664.

6667

Clear INT ENA flip-flop.

PCIE

When the 6661 instruction in the servicing routine is decoded, the skip logic asserts the OMNIBUS SKIP L signal.
The computer then proceeds to the subroutine associated with the LE8-E. When the 6666 instruction (as an
example) in the subroutine is decoded, the FLAG flip-flop is cleared and the information in the AC Register is
placed on the OMNIBUS DATA 5-1 1

lines; at

TP3 time the information is clocked into the Buffer Register of

the data transfer logic. At the trailing edge of the 6666 instruction signal, the STROBE signal is generated and
the information is clocked from the DATA 1-7 lines of the line printer into the 20-character Shift Register

within the line printer.

The DEMAND signal is then negated and, in turn, negates the STROBE signal.

SECTION 4 DETAILED LOGIC
4.3

SELECT LOGIC

The select logic is shown in Figure 4-3. Both the SELECT L and INTERNAL I/O L signals are asserted when a

666X instruction is decoded. The INTERNAL I/O L signal causes the positive I/O bus interface to ignore the
lOT instruction; the SELECT L signal is gated with bits MD9— 1 1 to provide inputs for the BCD-to-decimal
decoder, E17 (refer to Appendix A, Volume 1, for details about the DEC 8251 IC).
signals that represent lOT instructions 6661

through 6667.

4-5

The decoder supplies the

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4-6

4.4

INTERRUPT LOGIC

The interrupt logic is shown in Figure 4-4. When the INT ENA flip-flop is set, the control is logically connected
to the computer interrupt system. This flip-flop is cleared at computer power turn-on by the OMNIBUS

INITIALIZE signal and can be cleared and set under program control by instructions 6667 (or 6007, CAF) and
6665, respectively.

>
CNITIALIZE

E130

INT ROST L

INT ENA

-0|

—

7474 D

rry
6662
6666

LL-

E7
C

FLAG
7474 D

Figure 4-4 Interrupt Logic

When the INT ENA flip-flop is set, both the READY signal and the DEMAND signal can cause a program interrupt.

If the

READY signal

low, indicating an error condition in the line printer (drum gate open, excessive

temperature in paper drive motor, insufficient drum motor speed, or printer out of paper) NAND gate E13 asserts
Instruction 6663 senses the state

the INT RQST L signal and the computer begins the interrupt servicing routine.

of the READY line and causes a skip in the CPU program counter if READY is low (Figure 4-5).

READY
6663 L

6661 L

6666 L
6662 L

E14

>
-0

FLAG

C7474 D

INTIALIZE

—

Laaai

Figure 4-5 Skip Logic

4-7

The DEMAND signal causes a program interrupt by setting the FLAG flip-flop, as outlined in Section 3.
Instruction 6661 senses the state of the FLAG flip-flop and causes a program skip when the FLAG is set

(Figure 4-5).

The FLAG flip-flop is cleared by the INITIALIZE signal and by program instructions 6662 and

6666.

4.5

DATA TRANSFER LOGIC

The data transfer logic is shown in Figure 4-6. The 7-bit code transmitted from the CPU AC Register to the
printer 20-character Shift Register represents characters that appear on the 64- or 96-character printer drum
(refer to the table of code/character relationship in Volume 1, Section 4).

The coded information is gated from

the AC Register to the OMNIBUS DATA 5-1 1 lines when the 6666 or 6664 instruction is decoded in the CPU.

The SELECT L signal enables the DATA lines to condition the D-inputs of the 7-stage Buffer Register. When the
control decodes the 6666 or 6664 instruction, the buffer is loaded at TP3 time and the coded character is placed

on the printer DATA 1—7 lines.
Each character is followed by the STROBE signal that is generated when the STROBE flip-flop is set by the trailing edge of the instruction.

The printer samples the DATA 1—7 lines and negates the DEMAND signal, clearing

the STROBE flip-flop.

SECTIONS MAINTENANCE
Refer to Volume 1 and the Data Products Corporation technical manual for maintenance information that pertains to both the control and the printer.

The LE8-E Diagnostic, MAINDEC-8E-D2BA, should be run when an

error in the LEB-E is suspected.

SECTION 6 SPARE PARTS
Table 4-2 lists recommended spare parts for the LEB-E. These parts can be obtained from any local DEC office
or from DEC, Maynard, Massachusetts.

Table 4-2

LE8-E Recommended Spare Parts

DEC Part Number

Description

19-05547

IC DEC 7474

19-05576
19-05590

IC DEC 7410

19-09485
19-09594

IC DEC 7401
IC DEC 380

IC DEC 8251

19-09686
19-09704

IC DEC 7404

19-09705

IC DEC 8881

IC DEC 314

4-8

Quantity

V !p—

b—

i~C_C^

4-9

PART 5
DATA COMMUNICATIONS EQUIPMENT

CHAPTER 5
DP8-E SYNCHRONOUS MODEM

SECTION 1

INTRODUCTION

The PDP-8/E can communicate with remote data terminals and other computers when it is interfaced to fullduplex or half-duplex synchronous modems. A maximum of four DP8-E Synchronous Modem Interfaces can be
plugged into the OMNIBUS; each interface provides a means of transferring data between the computer and a

communication channel.

The interface consists of two quad modules, M839 and M866, that are connected by an H851 Edge Connector.
A signal cable, supplied with the option, connects the M866 Module to the synchronous modem. The interface
provides level conversion so that the computer can operate with communication channels using bipolar (El
standard), current mode, or TTL signals.

A DP8-E that interfaces bipolar or TTL signals is designated DP8-EA;

one that interfaces current mode or TTL signals is designated DP8-EB. The DP8-EA Interface is designed to
operate with Bell System 200-series synchronous modems, or equivalent; the DP8-EB Interface is designed to

operate with Bell System 300-series modems, or equivalent. Each type of interface connects to its modem with a
special cable assembly, viz., assembly BCOl

V for the DP8-EA and BC01W for the DP8-EB.

Data transfers between a modem and the computer are accomplished by 3-cycle data breaks, initiated and controlled by the DP8-E Interface.

A modem-to-computer transfer involves a modified 3-cycle data break operation

that uses seven computer timing cycles, rather than the normal three cycles.

The extra four timing cycles enable

the program to detect selected characters that might appear in the modem transmission.

Modems are discussed only to the extent necessary to fully describe the interface operation and to present supplementary information concerning installation and checkout of the option. Details of the installation, operation,
troubleshooting, and maintenance of the modems can be found in their technical manuals. Publications and

documents relevant to the DP8-E are:
a.

b.
c.

PDP-8/E & PDP-8/M Small Computer Handbook - D EC, 1 972
PDP-8/E Maintenance Manual, Volume 1
DP8-E Diagnostic, MAINDEC-08-DHDPA-A
DEC Engineering Drawings, Synchronous Modem Interface, E-CS-M839-0-1 and E-CS-M866-0-1.

SECTION 2 INSTALLATION
The DP8-EA/EB Interface is installed on-site by DEC Field Service personnel. The customer should not attempt
to unpack, install, checkout, or service the equipment.

5-1

Before the interface can be plugged into the PDP-8/E OMNIBUS, each module must be carefully checked to
ensure that it is wired correctly. Each module contains many split lugs that can be selectively connected or

disconnected so that the interface can meet the requirements of the PDP-8/E data break system and function
with any of the compatible modems, which have diverse operating characteristics. The split lugs on each module

Each pair of lugs is identified by a number, a letter, or a combination of the two (one symbol — A
(delta)
and two words - ON and OFF - are used, also). The identification is etched on the printed circuit

are paired.

board between or near the two lugs and also appears on the schematics and logic diagrams.
Tables 5-1 and 5-2 list characteristics that relate to the PDP-8/E data break system and to the diversity of compatible modems.

Those jumpers that connect the pairs of split lugs are also listed. Each jumper bears the same

identification as the two lugs it joins.

desired characteristic.

These tables show the jumpers that must be connected to achieve the

For example, if the modem transfers characters that have seven data bits, the M839 module

jumpers B7, C7, and B78 must be connected. All other jumpers in this group (B6, B8, and C8) must be disconnected.
All the pairs of lugs, except those labeled C and A, are connected by machine-inserted jumpers when the boards

are manufactured. Selected jumpers are then removed so that each module can be production tested.
characteristics selected for production testing are listed in paragraphs a. through h. which follow.

The

Unless other-

wise specified, the two modules are wired for these characteristics when received by the user. Therefore, the

jumper selections might have to be changed to suit the user's needs.
a.

The access addresses, the lOT codes, and the break priority for each interface should be assigned on
the basis of channel designations, as follows:

Channel

Access Addresses

lOT Codes

7720-7730
7700-7710
7660-7670
7640-7650
7620-7630
7600-7610

640X, 641X
642X, 643X
644X, 645X
646 X, 647

2
3

4
Spare
Spare
b.

8 bits/character

Normal clock phase

Current mode level conversion (DP8-EB)

Sync code 226

CARRIER/AGC interrupt for both ON and OFF transitions

Full-duplex operation.

Break Priority
5

4
3
2

A level conversion (DP8-EA)

When correct jumper selection has been completed, insert the interface in the PDP-8/E OMNIBUS and connect
the modules with the edge connector. See Table 2-3, Volume 1, for information concerning recommended
module priorities (the DP8-E is a "non-memory" option).
Connect the M866 Module to the synchronous modem with the signal cable provided. Refer to Section 5 for
cable and connector pin assignments.

The DP8-E option can be checked for correction operation by running the diagnostic program.
arises, refer first to Section 5 for ideas.

If a

problem

Refer then to the modem instruction manual for modem checkout

procedures.

5-2

Table 5-1

Jumper Connections, IV!839 IVIodule
Connect Jumper(s)

To Select

(Remove Others)

Figure Reference

Bits/Character

86,08

87, 878, 07

878, 88 (2), 07, 08

5-7,5-9,5-10

BRK Priority
PI

5-12

Access Address

7700-7710
7720-7730
7640-7650
7660-7670
7600-7610
7620-7630

A5
A5, A7

5-15

A6
A6, A7

NONE
A7

Device Code

6400-6407,6410-6417

N6, N7

6420-6427, 6430-6437
6440-6447, 6450-6457
6460-6467, 6470-6477

N6, 7

5-5

N7, 6

6,7

Sync Code (Examples)

NONE

000
226
377

84, S7,S9,S10
S4, 85, S6, 87,88,89, 810,511

Any code from 000-377
is

5-9

possible by selectively

connecting the 'S' jumpers

SECTION 3 BLOCK DIAGRAM DESCRIPTION
The DP8-E includes a receive channel and a transmit channel, each of which can initiate a data break when information is to be transferred between the DP8-E and the PDP-8/E. The channels synchronize the modem and

computer logic and convert computer parallel data to modem serial data, and vice-versa. Figure 5-1 is a simple
block diagram showing the signals used by the interface to synchronize the modem and the computer.

5-3

Table 5-2

Jumper Connections, M866 Module
Connect Jumper(s)

To Select

Figure Reference

(Remove Others)

BRK Priority
1

NONE

P1,P2

P1,P2, P3

P1,P2, P3, P4

P1,P2, P3, P4, P5

P1,P2, P3, P4, P5, P6

5-12

Carrler/AGC Interrupt

ON
OFF
ON & OFF

OFF

5-18

ON, OFF

Level Conversion
E, CE(2)

EIA
*Current Mode

0(6), CE(2),CT

TTL

T (2), CT

E-CS-M866-0-1

**Clock Phase

Normal

N(2)

nverted

A (2)

Half-Duplex

E-CS-M866-0-1
E-CS-M866-0-1

modem is used, jumpers D and X must be connected; if Bell 301 modem is used, jumpers
D and X must be disconnected.

*lf Bell 303

**For maintenance clock (Section 5) connect jumper F.
if

If testing

receive circuits, connect jumper A;

testing transmit circuits, connect jumper N.

TIMING SIGNALS

RING
.

CARRIER/AGC

DATA BREAK CONTROL SIGNALS

MD 0-1

PDP/8E

OMNIBUS

SIGNALS

SCR

DATA O-H L SIGNALS

SCT

EMA 0-2 L SIGNALS

INTERLOCK /DATA
SET READY

MA 0-11 L SIGNALS
SKIP L.INT ROST

DP8-E
INTERFACE

OVERFLOW L

CLEAR TO SEND
RD (RCV DATA)

SEND DATA

TERM READY
SEND ROST
EXTERNALTIMING

Figure 5-1

Simple Block Diagram, DP8-E

5-4

SYNC

MODEM

The modem generates the INTERLOCK/DATA SET READY signal when it is turned on and able to take part in
a data transfer.

The status of this signal can be tested in the DP8-E by the program lOT instruction, SRS1 (see

Table 5-3 for a list of DP8-E lOT instructions).

When the status check indicates that the modem is on, the pro-

gram can issue an SLCC lOT instruction, causing the DP8-E to assert the TERM READY signal. The modem,
which provides the interface with SCT (Serial Clock Transmit) pulses from the moment it is turned on, begins
transmitting SCR (Serial Clock Receive) pulses when it receives the TERM READY signal.

Table 5-3

DP8-E lOT Instruction List
Octal Code

Mnemonic

Description

6400/6420
6440/6460

SSCD

Skip if character detected. Causes the program to skip the
next instruction if the CHAR(acter) DET(ected) flip-flop
is

The flip-flop is set if an assembled character is found

set.

to compare to one of the stored characters in the access address locations.

This instruction clears the flip-flop.

If the

program must identify the test character that compared to
the contents of the Receive Data Register, an SRCD instruction should be used. See the SRCD instruction for
details.

6401/6421
6441/6461

SCSI

Clear DP8-E.

6402/6422
6442/6462

SSRO

Skip if receive word count overflow. Skips the next in-

Initializes all active functions in the DP8-E.

struction if the ROFLO L (receive overflow) signal is
asserted, and negates the signal.

The signal is asserted if,

during a receive data break operation, the OMNIBUS

OVERFLOW L signal
6403/6423
6443/6463

SSTO

is generated.

Skip if transmit word count overflow. Skips the next instruction if theTOFLO L (transmit overflow) signal is
asserted, and negates the signal.

The signal is asserted if,

during a transmit data break operation, the OMNIBUS

OVERFLOW L signal
6404/6424
6444/6464

SGRR

is generated.

Receiver go. Sets the R-GO flip-flop.

The instruction

implies that the program is ready to receive data from the

modem, i.e., the current address (CA) and the word count
(WC) have been updated. The hardware begins memory
references if two consecutive synchronizing characters are
received on the incoming serial data line.

Memory refer-

ences cease when the word count increments to

and

SGRR is not issued in less than one character time.
6405/6425
6445/6465

SGTT

Transmitter go. Sets the T-GO flip-flop. The instruction
implies that the program is ready to transmit data, i.e., the

current address and the word count have been updated.

the CLEAR TO SEND signal has been asserted in response
to the SEND RQST signal, the hardware begins memory
references.

ments to
time.

References cease when the word count increand SGTT is not issued within one character

SEND RQST should be asserted by the SLCC in-

struction; it should not be negated until two bit times after

the last bit has been transmitted, i.e., 1/ [Baud rate x (bits/
character + 2)] second after word count overflow.

(continued on next page)
5-5

Table 5-3 (Cont)

DP8-E lOT Instruction List
Octal Code

Mnemonic

Description

6406/6426
6446/6466

SCSD

and
Clear the sync detect flip-flops. Clears the SYNC
SYNC 2 flip-flops in the break request, receive logic. The
1

instruction enables the programmer to initialize the sync

detection circuits and to clear the receive circuits without
initializing the DP8-E.

6407/6427
6447/6467

SRTA

Read Current/ Access Address Register. Transfers the contents of the register to the AC Register.

The instruction is

used, primarily, for diagnostic and/or program debugging.

6410/6430
6450/6470

SSRG

6411/6431

SSCA

if the

RING flip-flop is set. Clears the flip-flop.

Skip if the CO/AGC flip-flop is set. Skips the next instruction if th 3 CO/AGC flip-flop is set. Clears the flip-flop.

6451/6471
641 2/6432
6452/6472

Skip if the RING flip-flop is set. Skips the next instruction

SLCC

Load control word. Transfers the contents of ACOO— 05 to

AC bits 00-03 are loaded into the
CNTL Register; functions selected by each bit are listed

the control word logic.

below.

ACOO: TERM RDY; permits the modem to enter into
the data mode.

AC01: IDLE; allows continuous transmission from the
same location in core without program intervention. The hardware enters the Idle mode
when the word count goes to 0. Word count and
current address are not incremented. Access to
the last transfer address continues until the SGTT
instruction is issued or the Idle bit is negated.

AC02: ENABLE; allows program interrupts and data
break cycles.

AC03: SEND RQST; activates the SEND RQST line (see

SGTT instruction description).
AC04: Available for customer use. When modem timing
AC05: signals are used, one El A (or current mode) transmitter is available for use with AC04 or AC05.
6413/6433
6453/6473

SLFL

Load field. Transfers the contents of AC00-AC05 to the
EMA bits 0-2,
while bits 03-05 select the transmit EMA bits 0-2. The
load field logic. Bits 00-02 select the receive

selected

EMA bits, combined with the current address, form

the 1 5-bit address to or from which data is transferred.

(continued on next page)

5-6

Table 5-3 (Cont)

DP8-E lOT Instruction List
Description

Octal Code

6414/6434
6454/6474

Transfers information from the read status logic to ACOO-

SRS2

AC07, as follows:
ACOO: CO/AGC L
AC01: RS(1)
AC02: TERM RDY
AC03: CS
AC04: TEMAO
AC05: TEMA 1
AC06: TEMA 2
AC07: RD

641 5/6436

Transfers information from the read status logic to ACOO-

SRS1

AC07, as follows:

6455/6475

ACOO: RRQST L
AC01: TRQST L
AC02; Sync 2 L
AC03: Sync 1 L
AC04: REMAOL
AC05: REMA 1 L
AC06: REMA 2 L
AC07: MODEM RDY L
6416/6436
6456/6476

SSBE

Skip on bus error. Skips the next instruction if the BUS

ERROR flip-flop

set.

Clears the flip-flop.

The flip-flop is

set if a transmit or receive break request is not serviced in
less than

1/baud rate. This implies that the break system is

overloaded or inoperative.

6417/6437

SRCD

Read detected character. The contents of the 2-bit register
that contains the identity of the detected character are trans-

6457/6477

ferred to AGIO and AC1 1.

The two bits correspond to the

low-order bits of the access address where the characters
for detection are stored.

Maintenance Instruction - When ACOO is logic 1, the SRCD instruction causes a
The pulse is placed on the maintenance clock

single clock pulse to be generated.
line to the modem.
is

In the test configuration (see Section 5, Maintenance), this line

returned as the transmit and receive clocks enabling single-step testing of the

transmit and receive circuits.

5.1

TRANSMITTER-MODEM DIALOGUE

After this exchange of ready signals, a data transfer can be initiated by either the modem or the computer.

computer-to-modem transfer is initiated by the computer under program control. An SLCC instruction (either
the same one that causes the TERM READY signal, or a later one) enables the modem free-running SCT pulses
to set a flip-flop in the DP8-E.

The setting of this flip-flop results in the SEND RQST signal being asserted by

The modem responds to this signal by transmitting the CARRIER/AGC signal, followed by the
CLEAR TO SEND signal. The CARRIER/AGC signal can cause the interface to generate an interrupt request.

the interface.

5-7

assuming that the DP8-E has been logically connected to the interrupt system. The program proceeds to a DP8-E
subroutine that initializes certain memory locations (Word Count (WC) and Current Address (CA) Registers) and
issues the

SGTT lOT instruction. This instruction, along with the asserted CLEAR TO SEND signal, enables the

transmit channel to request a data break. During this data break, a character is transferred from memory to a
shift register in the DP8-E.

Subsequently, SCT pulses cause the character to be shifted from the transmit channel

DATA line. At least the first two characters transmitted must be sync characters;

to the modem via the SEND

this requirement enables the remote receiving station to assemble each 6, 7, or 8 successive bits to form the

correct character.

5.2

MODEM-RECEIVER DIALOGUE

After the initial exchange of the two ready signals, a modem can initiate a data transfer in response to a ringing
signal on the transmission line.

interrupt request.

The modem generates the RING signal, thereby causing the DP8-E to generate an

The program proceeds to a subroutine that sets up the WC and CA registers and then waits for

the modem to transmit the CARRIER/AGC signal. This signal, which indicates that the modem is in the data

transmission mode, causes the subroutine to issue the SGRR lOT instruction.

Data transmitted by the modem

on the RD line is shifted into the receive channel by SCR pulses. The lOT instruction enables the receive channel
to request a data break after two successive sync characters have been recognized in the transmission (the sync

characters enable the receive channel to assemble each 6, 7, or 8 successive bits thereafter into data characters).

During the data break, which must be completed between 2 successive SCR pulses, tho character that was shifted
into the receive channel input register from the RD line prior to the data break is transferred to memory.

When

the data break ends, SCR pulses shift the next character in the transmission into the register.

5.3

DP8-E DATA BREAKS

A detailed block diagram of the DP8-E is shown in Figure 5-2. This block diagram illustrates the interface operation during the data break.

Figures 5-3 and 5-4 are timing diagrams that relate the signals shown in the block

diagram (each timing diagram depicts 6-bit character operation). All three figures should be studied and used as
reference material.

Data transfers between the PDP-8/E and a synchronous modem interface are of the data break type.
is

carried out in the Direct Memory Access (DMA) state of the CPU.

A data break

This state provides direct communication

between a data break device and memory by allowing the device interface to assume control of CPU major
register gating.

When the DP8-E interface is ready to begin a data break transfer, it asserts a number of OMNIBUS

control signals to force the CPU into the DMA state. One of the first of these control signals to be asserted (at
TP3 time) is the CPMA DISABLE L signal that causes the CPMA Register outputs to be disconnected from the

MA lines at TP4. During TS4, the interface makes a priority check. If no higher priority device has requested a
MA lines (at TP4 time) the address of the memory location that to be

data break, the DP8-E places on the

accessed during the first timing cycle of the data break. At the same time, the MS,
asserted, forcing the next timing cycle to be carried out in the

R DISABLE L signal is

DMA state. If the synchronous modem were a
DMA cycle, to or from the addressed memory

1-cycle data break device, data could be transferred, during this
location.

At the end of the cycle, the DP8-E would relinquish control of the CPU until a new transfer were to

take place.

The data break operation would be repeated as often as necessary to transfer the entire block of data

words.

5-8

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5-9

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SCR-P

HV-

E5,MSB

RRQST L

__n_ ji___n
TP2
R _rL_Ji
TP3

TP4

r!i

ri_

—
——

f^^__n

TL-

ji_n___n

TPt

n_^^
ri^vJi

ri_

BRK RQST

-^v-

CPMA DISABLE L
BRK IN PROG

—u—u—u u u -n

PRIORITY GO

BRK PRIORITY

BRK GRANT

ACCESS ADDRESS L

MS.IR DISABLE
LD CNTL

_j"
L
(1)

BREAK CYCLE L

MALC L
COMPARE

DO L

^\D1 L

D2 L
D3 L

WC
04 L

~T CA

D5 L

INC,

DATA 11 L
LOAD CURRENT

INC.

—

ADDRESS L

4i-

CURRENT ADDRESS L
D6 L

REMA L
BREAK DATA CONT L

DATA + MO-0-MB

RD TO BUS L

Figure 5-3 Timing, Receive Break Request

However, the synchronous modem is not a 1 -cycle data break device; i.e., it does not continuously update the

memory address to or from which data is transferred and, within its hardware, it does not keep track of the
number of transfers made. Data break devices that do not perform these two necessary tasks are defined as
3-cycle data break devices.

The transfer count and the transfer address are retained in the separate memory loca-

tions that were introduced earlier, viz., the Word Count (WC) Register and the Current Address (CA) Register,

5-10

respectively.

During a data break operation, each location is addressed separately and the data in each location

(the word count or the current address) is updated by the interface.

updating operation.

A single timing cycle

required for each

the word count is

Thus, three timing cycles are required for each data word transferred:

updated during the first cycle; the current address is updated during the second cycle; the data word is transferred
during the third cycle.

BIT

SCT-P

E10, MSB

TRQST L
TP1

TP2

n_ jL__n
n

TL^

il_ri__n__ji
TP4 Jl
itL_JT_JL_ii

TP3

n
n

i^i

TL^vJ"!

n _n_

a
ri

BRK RQST

^v-

CPMA DISABLE L
BRK IN PROG L
PRIORITY GO

BRK PRIORITY

V-

BRK GRANT

-iW
ACCESS ADDRESS L
MS, IR

DISABLE L

LD CNTL

BRK CYCLE

)

^V-

MALC L

-^V-

D7 L

^'r

D8 L
D9 L

.INC

DATA 11 L

|wc

INC,
CA

LOAD CURRENT ADDRESS L

CURRENT ADDRESS L

TEMA L
BREAK DATA CONT

DATA+ MP

Figure 5-4 Timing, Transmit Break Request

If the

data transmission is from the DP8-E to memory, the 3-cycle data break operation is modified somewhat.

The DP8-E Interface is capable of identifying selected data characters that might appear in the data transmission.
The identification is accomplished by comparing each data character in the transmission with a test character.
Four test characters are provided; thus, the interface can identify four different data characters. The test characters are stored in four separate memory locations that are successively addressed at the beginning of the data

5-11

break operation.

Each comparison requires a single timing cycle. Therefore, a receive data break operation

requires seven timing cycles, rather than three, for each data word transferred.

However, the operation is still

considered a 3-cycle data break.

A receive data break operation can begin only after the data character has been shifted completely into the interface Receive Data Register.

When the last data bit is shifted in, the interface requests a data break and asserts the

CPMA DISABLE L signal to remove the CPMA Register from the MA lines. Then the interface places an "access
address" on the MA lines. The memory location represented by this address is one of a group of eight special-

purpose memory locations assigned to the modem/interface in question (each modem/interface occupies one
communication channel). These locations are assigned to the communication channels as indicated in Section 2.

To simplify the discussion, only Channel 1 is considered. Locations 7720 through 7723 contain the four test
characters; locations 7724 and 7725 contain the receive word count and current address, respectively; locations
7727 and 7730 contain the transmit word count and current address, respectively.

The first access address to be placed on the MA lines at the beginning of the receive data break operation is 7720.
This address originates partly in the Current/ Access Address Register logic and partly in the Access Address

Counter logic. The test character stored in this location is gated to the Receive Data Register logic and compared
with the received character stored there. This action can have one of three results:

a) if the two characters are

not equal, no further action occurs during this timing cycle; b) if the two characters are equal, an interrupt
request can be generated during this timing cycle; c)

the two characters are equal, the data break operation can

be terminated near the end of this timing cycle, i.e., the received character is stripped.

either a) or b) results

from the comparison, the access address is incremented by the Access Address Counter logic at the end of the
timing cycle. The test character in location 7721

gated to the Receive Data Register logic during the second

timing cycle and compared with the received character. This comparison can have one of the three results indicated.

Again, the access address Is incremented at the end of the cycle, provided the received character is not

stripped.

The comparison process is carried out for the four test characters.

If a

successful comparison occurs

during the first, second, or third test cycle, the remaining test characters must still be compared.

When the

fourth test character has been compared, the access address increments to 7724, which represents the memory
location of the word count.

During the fifth timing cycle, or WC cycle, the word count is incremented. The

access address then increments to 7725 and, during the sixth timing cycle, the CA cycle, the current address is

incremented.

This incremented current address is the address of the location to which the received character is to be transferred
during the seventh, or data transfer, timing cycle. This "current address" is placed on the

MA lines at the end of

the CA cycle.

During the data transfer cycle, the received character is gated from the Receive Data Register to

the OMNIBUS

DATA lines and from the DATA lines to the location specified by the current address. At the end

of this timing cycle, the data break operation is terminated.

To carry out a transmit data break operation, the DP8-E asserts the same control signals as it does during a receive
data break.

However, no test character timing cycles are necessary; consequently, only three timing cycles are

used to transfer each data character.

Each logic block indicated in Figure 5-2 is discussed in detail in Section 4. The separate sections are arranged to
present the information in the most logical progression; however, some points, because of their complexity, are

covered in more than one section, albeit from a different viewpoint.

5-12

SECTION 4 DETAILED LOGIC
5.4

lOT DECODER LOGIC

The PDP-8/E can accommodate four separate communication channels. Hence, four sets of lOT instructions are
needed. A set consists of 16 instructions, each instruction represented by an octal code and a mnemonic code.

The same 16 mnemonic codes are used with each set of instructions; however, the octal codes vary from set to
set.

The octal codes for each channel are determined by the selective connection of certain jumpers on the M839

Module.

When this module is fabricated, the octal codes are assigned to the channels as detailed in Section 2.

The lOT decoder logic portion of the M839 Module is shown in Figure 5-5. Locations are indicated on the figure
where jumpers can be connected to provide the 16 octal codes for a particular channel. These locations are designated 6, 7, N6, and N7. Assume that this interface is assigned to Channel 1, Octal codes 6400 through 6407 and
641

through 641 7 must be selected. This is accomplished if jumpers are connected at locations N6 and N7.

Thus, NANDgate E19 asserts the THIS CODE signal during TS3 of lOT instructions 640X and 641 X.
Bit
if

MD 8

gated with the THIS CODE signal to provide an enabling signal for one of the DEC 8251 Decoders,

bit 8 is logic 0,

E38 is enabled, and a 640X instruction can be decoded; if bit 8 is logic 1, E26 is enabled, and

a 641 X instruction can be decoded.

The three least significant bits of the instruction are determined by MD bits 9, 10, and 11. These bits are gated
to both decoders; the enabled decoder produces the assigned octal code.

Note that the THIS CODE signal causes NAND gate E33 to assert the OMNIBUS INTERNAL I/O L signal. This
signal ensures that the positive I/O bus interface ignores the lOT instruction.

5.5

CONTROL WORD LOGIC

The control word logic is shown in Figure 5-6. The SLCC instruction gates the contents of the AC Register to
the DATA lines.

The user can load AC bits 0-5 to assert selected DP8-E enabling signals.

The information on DATA lines 0-3 is loaded into the CNTL Register at TP3 time of the instruction. Each of
the four possible enabling signals is discussed in later sections. Flip-flops E27 allow the user to enable functions
of his own choosing.
at connector J1,

The 1 -output of each flip-flop can be taken from the board at the "H" top connector or

jumpers are installed at locations FF andJJ. Note that these outputs are TTL-level rather than

EIA-Ievel signals.

5.6

BREAK RQST, RECEIVE LOGIC

The Break RQST, Receive logic is shown in Figure 5-7. When communication in the receive mode has been
established between the modem and the PDP-8/E, the modem begins transmitting data to the interface.

character bit is shifted into the Receive Data Register (Paragraph 5.7) by an SCR-P L pulse.
also clocks the

Each

Each SCR-P L pulse

RCV CNT binary counter, E5 in Figure 5-7 (note that the counter is wired for 6-bit/character

When an entire character has been shifted into the Receive Data Register, the most significant bit
(MSB) of the RCV CNT counter becomes logic 1 If both the R-GO flip-flop and the SYNC 2 flip-flop are set,

operation).

NAND gate E3 generates the RRQST L signal, and a data break operation can begin. During this operation, the
character in the Receive Data Register is transferred to the PDP-8/E memory.

5-13

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5-14

TERM RDY

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DATAO L

DATA

74197

(JIDD)

INT RQST L
(CP1)

BRK RQST

CNTL

'(FM1)

SEND
RQST

.3Z)^

TERMINAL READY

IDLE L

ENABLE

(FT I)

El 4

NOTE

DATA 2 L

^E>

E16
D

RS(l)

Oe3
c RS

NOTE

2 (-

SEND RQST

( J1 V)

INI L
..-.Tc
r—\ NOTE

EXTERNAL TIMING

SCT

(j,L)

FF (2h

-(JIFF)

(J1JJ)

E27

-Cl

D
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DATA 4 L-

JJ
t

E2 7

-0|

C
-1

^-:H>

NOTES'.
1. Logic is P/O M866 module.
2. See DEC Eng. Drng. E-CS - M866

for gating

TP3-

circuity .

SLCC L

Figure 5-6 Control Word Logic

The R-GO flip-flop, which is cleared at INITIALIZE time, must be set by the SGRR lOT instruction during the
time that communication is first established. The SYNC 2 flip-flop is set only when two successive sync characters have been transmitted by the modem.

The detection of the sync characters is carried out by a comparison

process in the Receive Data Register logic (the comparison is performed in the hardware and does not use the
special break locations).

The character in the Receive Data Register is compared with the jumper-selected inter-

face sync code.

5-15

5-16

Assume that the first character in a particular transmission is a sync character (Figure 5-8 is helpful in visualizing
the sync character detection process). As the SCR-P L pulse shifts the sixth character bit into the Receive Data
corresponding
Register, the COMPARE signal is asserted, because each of the six character bits is the same as the

sync code bit. The COMPARE signal is applied to the D-input of the SYNC 1 flip-flop, and the flip-flop is set,
of the
indicating that one sync character has been detected (the SYNC 1 flip-flop is set by the trailing edge

SCR-P L pulse; the delay of a few nanoseconds is exaggerated in the timing diagram).
detected, the RCV CNT counter, E5, is prevented by the
pulses.

Until this first character is

-output of the SYNC 1 flip-flop from counting SCR-P L

The 1 -output causes the count/load input, pin 1, of the counter to be held low. This low not only pre-

vents E5 from counting, but also presets E5 with a count of 0010.

When the 1 -output of the SYNC 1 flip-flop goes high, E5 can begin counting pulses.

If the

next character shifted

asserted again.
into the Receive Data Register is another sync character, the COMPARE signal is

The MSB output

SYNC 2 flip-flop
of E5 goes high with the trailing edge of the SCR-P L pulse. The low at the D-input of the
enables the output pulse from NOR gate E8 to set the flip-flop.
If

NAND gate E3 asserts the RRQST L signal.

priority requirements are met, the receive data break operation begins at the next

The operation takes place between the two bits indicated on the timing diagram.

occurrence of a TP4 pulse.

Even the fastest modem avail-

able is so slow compared to the computer timing cycle that approximately 1 5 timing cycles can

occur in the time

space indicated by the dashed lines. Figure 5-3 is a timing diagram of a receive data break operation. Bit 6 and
of the computer
bit 1 in each timing diagram correspond, to call attention to the relative timing

and modem

(Figure 5-3 should be referred to when considering any of the receive circuits).
If the first occurrence of a

sync character is not followed by a second, the SYNC 1 flip-flop is cleared at the time

that the MSB of E5 goes high.

In such a case, the timing reverts to that indicated at the beginning

Therefore, two sync characters must occur successively somewhere in the transmission.

of Figure 5-8.

When this happens, both

the SYNC 1 and the SYNC 2 flip-flops remain set throughout the transmission, and can be cleared only by

the

SCSD iOT instruction, or at INITIALIZE time.
Each time the MSB of E5 goes high, a break request results. During the data transfer cycle the RD TO BUS L

RCV DATA Register onto the OMNIBUS DATA lines. At this time, pin of
and the
the RCV CNT counter is taken low, presetting the counter with a count of 0010. The MSB goes low
1

signal gates the character in the

RRQST L signal

negated. After six SCR-P L pulses a new break request can be generated.

Requests are generated until the last character is transferred. During the WC cycle immediately preceding the last
the
data transfer cycle, the OMNIBUS OVERFLOW L signal is asserted, causing ROFLO (0) L to be asserted by

INT/Skip logic (Figure 5-19). The RD TO BUS L signal then clears the R-GO flip-flop, thereby disabling NAND
gate E3.

Note that the RCV CNT counter can be reset to the initial count by the STRIP L signal that enables NOR gate
charE3. This signal is asserted when a received character has compared successfully with one of the stored test
acters and the 0-bit of the test character is logic 1, i.e.,

MDO

after the break cycle in which the comparison took place.

logic 1.

In this case, the data break operation ends

Consequently, neither the word count nor the current

address is incremented, and the character in the Receive Data Register is not transferred to memory.

Paragraph 5.15 for a discussion of the events that occur when MDO

5-17

logic 0.

Refer to

I
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5-18

5.7

RECEIVE DATA REGISTER LOGIC
The logic has two functions: a) to compare received
memory; b) to transfer the received data to
interface sync code or test characters stored in

The Receive Data Register logic is shown
data with either the

in Figure 5-9.

the OMNIBUS DATA lines.

—V\Ar-<i
MOIl L

:)g>-..
COMPARE

"^E)^'
N

IDS L

INT L

C3i

3CS0 L

y {_]

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DATA 8 L

itlo-

B6 B78

'E37-

E3 6

8271

8235

RCV

73a?
,

•"1

DATA

-0|2

6 4 13

+ 5V

3 >

rs7=
«0 6 L

p-WVHI

O-X

E25
8266

y)D5 L

note:
Logic i3 P/0

^D4

E32^)o—

—

SYNC

RO TO BUS L

2(1)-

Figure 5-9 Receive Data Register Logic

5-19

M839 module.

The data is received in serial form as the RD signal (this signal is high, representing logic 1, when the mark
condition exists). Each data bit is shifted into the Receive Data Register, E37 and E54, by its accompanying

SCR-P L pulse. Jumpers B6, B7, B8, and 878 must be selectively removed or connected so that the Receive Data
Register corresponds to the number of bits per character of the received data (see Table 5-1 for information con-

For example, if the data being received contains 6 bits per character, only jumper 86

cerning jumper selection).
is

connected. Only two bits of the 4-bit shift register, E37, are used; thus, E37 and E54 comprise a 6-bit shift

The register is filled each time an entire character has been received. Note that although E54 is in the
"right-shift" mode, as one expects (see Volume 1, Appendix A for 8271 details), E37 is always in the "parallelregister.

load" mode.

However, because of the way E37 is externally wired, the IC operates as a right-shift register.

When an entire character has been shifted into the register, the character is compared and/or transferred to the

DATA lines. A comparison is always made at the beginning of a transmission to determine if the character
received is a sync character.

If it is, it coincides with

the interface sync code.

two successive sync characters

are received, two successful comparisons are made and the interface requests a data break of the CPU.

The received character and the sync code are compared, bit for bit, by Exclusive-NOR gates E32 and E55, each
of which acts as a comparator. Each bit of the received character is applied to one input of a comparator. The
other comparator input is taken from E25 or E45, DEC 8266 ICs (see Volume 1, Appendix A for details). These
ICs are 4-bit logic elements (multiplexers) that are used as selectors.

For example, E25 provides an output at

pin 3 that represents the state of the input signal at either pin 1 or pin 2.

of the control signals at pins 7 and 9.

The selection is determined by the state

If pin 9 is low, E25 provides an output at pin 3 of the same state as the

input at pin 2; if pin 9 is high, the output state at pin 3 is the inverse of the input state at pin 1.

When the received character is being compared to the interface sync code, the SYNC2 (1) signal is low. Thus,
pin 3 is the same state as pin 2.

The state of pin 2 depends on whether or not jumper S7 is connected.

Likewise,

the state of each other output pin of E25 and E45 depends on whether or not a corresponding jumper is connec-

The jumpers are connected or removed to select the desired sync code. Assume that the desired sync code
of the PDP-8/E data word; the LSB of the
is 26g (the LSB of the sync code/character corresponds to the LSB

ted.

received character is the first bit transmitted from the modem).

being removed.
If the

Jumpers S7, S9, and S10 are connected, all others

The signal at each of the following 8266 output pins is low; E25, pin 3; E45, pins 13 and 4.

character in the Receive Data Register is a sync character, the signal at each of the following 8271 output

pins is low.

E37, pin 1 1

;

E54, pins 7 and 9. The input signals at each comparator coincide and, thus, the

COMPARE signal high. As the first bit of the next character is shifted into the Receive Data Register, the
COMPARE signal goes low. When this next character has been shifted in completely, the COMPARE signal again
is

goes high, assuming that this character, likewise, is a sync character.

The SYNC2 (1) signal is asserted, indicating

that two successive sync characters have been received from the modem, and the interface requests a data break
(see Paragraph 5.6 for further details and for a timing diagram that includes the

COMPARE signal and the

SYNC2(1) signal).
Any further comparisons that are made during this transmission involve the received data and a test character
stored in a memory location.

Because the SYNC2 (1) signal remains high throughout the entire transmission,

information on the MD4-1 1 lines is gated through selectors E25 and E45 for comparison with the received data.
This comparison process is described in detail in Section 3, and Paragraph 5.1 1.

The character in the Receive Data Register is transferred to the PDP-8/E memory via the OMNIBUS DATA tines
during the data break operation (unless the character is to be stripped). The RD TO BUS L signal gates the data
through the 8235 4-bit logic elements to the DATA 4-1 1 lines. Note that DATA bits 4 and 5 are negated if the
received data contains 6 bits per character, as has been assumed throughout this discussion.

If the data in

memory location is to be compared with a received character of 6 bits, bits 4 and 5 of the selected location must
be logic 0. The same reasoning applies to bit 4 when the received data contains 7 bits per character.

5-20

5.8

BREAK RQST, TRANSMIT LOGIC

When the modem is turned on, it begins to transmit SCT pulses. After the program has issued an SLCC lOT
Control Word Logic); the
instruction, an SCT L pulse sets the RS flip-flop in the DP8-E (see Paragraph 5.5,

SEND RQST signal causes the modem to activate the CLEAR TO SEND line. The CLEAR TO SEND
the TRQST L signal.
signal enables the Break RQST, Transmit logic. Figure 5-10, to assert
resulting

NAND gate E3 asserts the TRQST L signal if flip-flop E2
must be high if E2 is set).

set and if the

MSB signal is high (the third input to E3

E2 can be set by an SCT-P L pulse if the T-GO flip-flop is set and if the CLEAR TO

SEND signal has been asserted. The SGTT instruction sets the T-GO flip-flop; consequently, the transmit
of the XMIT CNT counter,
synchronization process is, essentially, a program function (note that the initial count
and TRQST L is
cleared
is
flip-flop
T-GO
E10, is unimportant). When the last character is transferred, the
negated, unless the Idle mode was previously loaded into the Control Word

logic.

If this

enabled and the TRQST L signal remains asserted, allowing continuous transmission

was done, E13 remains

from the last addressed core

memory location.
of a

When the TRQST L signal is asserted, the transmit data break operation can begin at the next occurrence
considering any
TP4 pulse. Figure 5-4 is a timing diagram of such an operation and should be referred to when
of the transmit circuits.

During the data transfer cycle, represented by the D9 L signal, the character to be

ferred from memory is gated onto the

MD lines.

trans-

At TP3 time, the character is parallel-loaded into the XMIT

DATA Register (Paragraph 5.9). The register is shifted by each succeeding SCT-P L pulse, until all six bits, for
example, have been shifted out of the interface via the SD (Serial Data) line.

When TS3 of the data transfer cycle is first entered, the XMIT CNT counter, E10, is reset to the

initial

count of

the XMIT
0010 via NAND gate E18. Each SCT-P L pulse that shifts the XMIT DATA Register is counted by

CNT counter. Thus, the sixth pulse not only shifts the MSB of the character onto the SD line, but also causes
The TRQST L signal is asserted again and another break request can
the MSB of the counter to become logic
1

be generated.

immediately preceding the
Requests are generated until the last character is transferred. During the WC cycle
TOFLO
the
(0) L to be asserted by
causing
asserted,
OMNIBUS OVERFLOW L signal is

last data transfer, the

The T-GO flip-flop is then cleared when NAND gate E26 is enabled at the
previously.
beginning of TS3. The TRQST L signal is negated, unless the Idle mode was programmed

the INT/Skip logic (see Figure 5-i9).

signal during the
Note that when the T-GO flip-flop is set, NAND gate E34 asserts the OMNIBUS DATA 1 1 L
data break
transmit
of
the
respectively)
signal,
CA and WC cycles (represented by the D7 L signal and the D8 L

data break,

The B R K Grant logic asserts the B R EAK DATA CONT L signal throughout the transmit
to memory. The process is
thereby enabling the CPU gating to add MD bits and DATA bits and transfer the sum
operation.

asserted during the WC and CA
represented symbolically as DATA+MD->MB. Because the MD11 L signal is
memory.
both the word count and the current address are incremented and returned to
cycles,
If the

Idle mode is entered after the T-GO flip-flop is cleared, a continuous

transmission from the last addressed

such

The D7 L and D8 L signals are repeatedly asserted, in turn, throughout
the word count and
Consequently, NOR gate E47 is enabled in the Idle mode. To prevent both

core memory location takes place.
a transmission.

the current address from being incremented, the 1 -output of the T-GO flip-flop is

applied to

NAND gate E47.

Thus, the word count and the current address are incremented only when T-GO is set

The DATA 1 1 L signal is asserted during the CA and WC cycles (represented by the D4 L signal
signal, respectively) of the receive data break operation, also.

and transfer address. Because an Idle mode is not possible during a receive data break, the
the D4 L signal or the D5 L signal and the B R K G RANT signal to enable E34.

5-21

and the D5 L

Again, the result is an incremented word count
gating requires only

E
in
C
ro

5-22

5.9

TRANSMIT DATA REGISTER LOGIC

The Transmit Data Register logic is sliown in Figure 5-1 1.

Tfiis logic transmits data from the

to the synchronous modem input.

D10 L

E51

}

MD8

LD CNTL (1

)

TP3

N
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J^^^

note:
Logic

P/0

M839 module.

Figure 5-1 1

Transmit Data Register Logic
5-23

OMNIBUS MD lines

The character stored in the current address location is gated onto the MD lines during TS2 of the data transfer
During TS3 of the cycle, NAND gate El 8 is enabled, placing the Transmit Data Register in the parallel-

cycle.

load mode.

At TP3 time, the register is clocked via the E35-E18B-E20 path, and the character on the MD lines is

loaded into the register.
right-shift mode.

When TS3 ends, 50 ns later, NAND gate EISA is disabled, placing the register in the

At this time the LSB of the character is applied to the D-input of the SEND DATA flip-flop.

The first-occurring SCT-P L pulse after the data break ends clocks the SEND DATA flip-flop. This action places
the LSB of the character on the SD L line. Simultaneously, the Transmit Data Register is right-shifted and the

next character bit is applied to the SEND DATA flip-flop's D-input. Six SCT-P L pulses shift-out the register; the
sixth pulse can cause the Break Request, Transmit logic to assert the

TRQST L signal and another data break can

begin.

BRK RQST LOGIC

5.10

The BRK RQST logic is shown in Figure 5-12. Either the RRQST L signal or the TRQST L signal can cause the
INT STROBE signal to set the BRK RQST flip-flop. Note that the flip-flop is cleared when the OMNIBUS

INITIALIZE signal is generated, if the ENABLE signal has been asserted by Control Word logic.
signal has not been asserted, the

If the

ENABLE

BRK RQST flip-flop is held in the clear state.

When the BRK RQST signal goes high, both the BRK IN PROG L and CPMA DISABLE L signals are asserted.
The CPMA DISABLE L signal results in the CPU CPMA Register being disconnected from the OMNIBUS MA
lines, while the BRK IN PROG L signal ensures that only data break devices place priority information on the
OMNIBUS DATA lines during TS4.

When TS4 is entered, the BRK PRIORITY L signal is asserted; i.e., the priority of this interface is placed on the

DATA BUS. Simultaneously, all other data break devices place their priorities on the DATA BUS. There can be
as many as 1 1 other data break devices, including up to three DP8-Es, connected to the

respective interfaces.

OMNIBUS via their

However, only six of these can have a higher priority than this modem.

Assume that there are, indeed, six data break devices that have a higher priority. This means that this DP8-E
has priority 7.

To establish this priority, one must ensure that the following jumpers on the two interface modules

are connected:

P7 on the M839 Module; PI through P6 on the M866 Module (Figure 5-12). Thus, this interface

places its priority on the

DATA 6 line. The priority of all other data break devices is established by connecting

selected jumpers on similar networks within the respective interfaces.
is

usually the fastest device, places its priority on the

DATA

line, and so on.

If,

DATA

line.

The device having highest priority, which

The second-highest priority device uses the

during a particular TS4, no other device is requesting a data break, or, if a requesting

device is of lower priority than this interface, the DATA

L through DATA 5 L signals are negated.

NAND gate

E9 is enabled, causing E23 to assert the PRIORITY GO signal. This signal causes the break request to be granted.
If

any of the six higher-priority devices requests a data break at the same time as this interface, the device places

DATA line. Thus, one, or more, of the DATA line signals, DATA L through
NAND gate E9 disabled and the PRIORITY GO signal remains negated. This interface
must wait until the next TS4, when
again places its priority on the DATA BUS.
its

priority on its assigned

DATA 5 L,

is asserted.

5.11

BREAK GRANT LOGIC

When the DP8-E asserts the PRIORITY GO signal, the Break Grant logic completes the CPU takeover process
that was begun by the

BRK RQST logic. The Break Grant logic is shown in Figure 5-13.

5-24

I-

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CO

5-25

5-26

The PRIORITY GO signal enables the TP4 pulse to settheBRK GRANT flip-flop and, also, to generate the GTP4
pulse.

The 1-output of the flip-flop enables NAND gate E22 to assert the OMNIBUS MS, R DISABLE L signal.
I

This signal forces the CPU to enter the

DMA state and disables the CPU

R Register. At the same TP4 time, the

output of the CPMA Register is removed from the MA lines, the BRK RQST logic having asserted the CPMA

DISABLE L signal at the previous INT STROBE time. The interface now specifies the address of the memory
location that is to be affected during the next memory timing cycle, which is the first cycle of the data break
operation.

This address is placed on the
in Paragraph 5.1 3.

MA lines by the Current/Access Address Register logic, which

discussed in detail

Briefly, this logic places either an access address or a transfer address on the MA lines. Because

the modem is a 3-cycle device, the data transfer cycle is preceded by at least 2 cycles of operation, word count
If the data character is to be transferred from the DP8-E to memory — a receive
—
break request
the WC and CA cycles are preceded by 4 test character recognition cycles. Test characters, the

(WC) and current address (CA).

word count, and the current address are stored in memory locations specified by access addresses. Thus, the first
cycle of a Data Break operation, whether of a Receive Break Request or of a Transmit Break Request, involves an
access address. Although this address is placed on the

MA lines by the Current/ Access Address Register logic, the

Break Grant logic, by asserting either the ACCESS ADDRESS L signal or the CURRENT ADDRESS L signal,
determines which type of address is selected.

Thus, when the BRK GRANT flip-flop is set at TP4 time, NAND gate E26 asserts the ACCESS ADDRESS L
signal (flip-flop E23 is cleared by the

GTP4 pulse). Simultaneously, NAND gate E34 asserts the BREAK DATA

CONT L signal, which provides a convenient method of updating the word count and the current address, as well
as re-writing recognition characters in memory.

This method is explained fully later in this section.

At TP1 time of the next memory cycle, the LD CNTL (Load Control) flip-flop is set, causing NAND gates E22 to
assert the

BRK CYCLE L signal and the MALC L signal. The BRK CYCLE L signal is applied to the programmer's
The MALC L signal prevents the CPMA Register from being

console and can be monitored on the display panel.

clocked during the data break operation (see Volume 1, Paragraph 3.34.1 for details). During the data break cycle

begun by this TP1 pulse, the information in the access address is placed on the MD lines. The type of information

depends on the type of break request that is being carried out.
If a

receive break request is starting, the information on the

MD lines

a test character. This character is com-

When the comparison has been made, the test
character is returned to memory during the write half of the timing cycle. The re-write in memory is made
pared to the received character in the

Receive Data Register logic.

BREAK DATA CONT L signal that results in the CPU operation DATA+MD to the MB. Since
the DATA lines carry no information at this time, only the information on the MD lines, the recognition characpossible by the

ter, is returned to the

memory location.

If the

received character compares bit-for-bit with the test character, an

interrupt request can be generated by the interface, or the received character can be stored with no other action,

or the data break can be terminated immediately (the character is "stripped").

If a

successful comparison is made

and the character is not stripped, or if the received character and the test character differ, the data break operation continues.

During each of the next three break cycles, a new access address is provided by the Access

Address Counter logic (Paragraph 5.12), and a new test character is placed on the MD lines and compared to the
received character.

If a

successful comparison occurs between the received character and one (or more) of the

test characters, that fact is retained by a flip-flop in the Detected Character Register logic described in

Paragraph

5.15.

During the 5th and 6th cycles of the receive break request data break, the information in the memory location
defined by the access address is the word count and the current address, respectively.

MD lines in turn. During each timing cycle, designated D4 L for WC and D5 L
L signal. Thus, the DATA+MD to the MB
NAND gate E34 in the Break Grant logic asserts the DATA

current address are placed on the
for CA,

The word count and the

1 1

5-27

operation forced by the BREAK DATA CONT L signal increments both the word count and the current address.

AtTP3timeof the CA cycle, the Break Grant logic asserts the LOAD CURRENT ADDRESS L signal. At TP4
time flip-flop E23 is set, causing the ACCESS ADDRESS L signal to be negated, while the CURRENT ADDRESS L
signal is asserted.

The combination of the LOAD CURRENT ADDRESS L signal and the CURRENT ADDRESS L

signal causes the current address to be gated through the Current/Access Address Register logic to the

MA lines.

During the data transfer cycle, D6 L, the RD TO BUS L signal is asserted in the BRK RQST Receive logic. The
character in the Receive Data Register is gated onto the DATA lines and placed in the memory location specified

by the current address. The data break ends after this timing cycle, and six more SCR-P L pulses must be received
before a new break request can be generated.
If a transmit break request is carried out, only the WC and CA cycles precede the transfer cycle. The same
OMNIBUS control signals are asserted by the Break Grant logic; differences occurring during the transmit opera-

tion can be noted in the timing diagram. Figure 5-4.

5.12

ACCESS ADDRESS COUNTER LOGIC

The Access Address Counter logic is shown in Figure 5-14. The logic includes the Increment Enable flip-flop,
E57, the Increment Counter, E52, and a BCD-to-Decimal Decoder, E46.

DO L_—Oi
D1

L-

^^>l
^

D2 LD3

L—-0-

STRIP L

COMPARE —

3!BH>^"^
TP3

note:
Logic

P/O

Figure 5-14 Access Add Counter Logic

5-28

M839 module

When the OMNIBUS INITIALIZE signal is generated, the resulting INI L signal clears the Increment Counter and
DO L signal.
the Increment Enable (INC ENA) flip-flop. The BCD output from E52 is 0000; thus, E46 asserts the
Unless a break request is generated, the Increment Counter, the Decoder, and the flip-flop remain in the state
described.

the DP8-E requests a data break and has highest priority, the TP4 pulse immediately preceding the first data

break cycle (the same TP4 pulse that sets the BRK Grant flip-flop) generates a GTP4 pulse.

The resulting

ACCESS ADDRESS RESET L signal from NAND gate E31A sets the INC ENA flip-flop. This signal is also
input loads the
applied to the count/load input of the Increment Counter, E52. A negative-going signal at this
counter with the information present at the data inputs, pins 3, 4, 10, and 1 1.

If this is a

receive data break

that this
operation, the RRQST L signal is asserted and E52 remains in the 0000 output state. However, assume
is a

The RRQST L signal is not asserted. Therefore, E52 is loaded with a BCD
E46 decodes this to assert the D7 L signal. When this signal is asserted, the access address 7727 is

transmit data break operation.

count of 01 1 1

;

MA lines by the Current/ Access Address Register logic. This the access address of the word count
the WC cycle.
location. Thus, the first cycle of the transmit data break operation
placed on the

When the word count has been incremented and returned to memory, TP4 of the WC cycle generates another
GTP4 pulse. Because the first GTP4 pulse sets flip-flop E57, the second GTP4 pulse enables NAND gate E24,
the D8 L signal. When
rather than E31. E52 is clocked, the BCD count is incremented to 1000, and E46 asserts
this signal

asserted, access address 7730 is placed on the

MA lines and the CA cycle

The address in

entered.

an access address, is
location 7730 is incremented to produce the current address. This address, rather than

MA lines at TP4 of the CA cycle. At the same TP4 time, E52

placed on the

is again

clocked, the BCD count is

transfer cycle
incremented to 1001, and E46 asserts the D9 L signal. This signal is asserted throughout the data
break request (by
and is used to gate the data character into the Transmit Data Register, to end the transmit

negating the TRQST L signal), and to clear the INC ENA flip-flop at TP3 time of the

transfer cycle. Because a

GTP4 pulse is not generated during the data transfer cycle, the Increment Counter is not clocked at the end of
count of 1001 and E46 asserting the
this cycle. Thus, the data break operation ends with E52 holding the BCD
D9 L signal. This condition exists until a new data break operation, either receive or transmit, is initiated.
If the

next data break operation is of the transmit type, location 7727 is again addressed

to begin the

WC cycle.

0000
However, a receive data break request would cause the BCD count in E52 to change from 1001
address.
access
an
by
addressed
is
character,
test
contains
a
GTP4 time. Therefore, location 7720, which
to

at the

first

decoder asserts
At each GTP4 time of the receive data break operation, the Increment Counter is clocked. The
during the four test
the DO L through D6 L signals in succession. The DO L through D3 L signals are asserted
character cycles, D4 L is asserted during the
asserted,

WC cycle, and D5 L

is asserted

during the CA cycle.

When D6 L is

the CA
the current address, which was loaded into the Current/ Access Address Register logic during

cycle, is placed on the

MA lines. The D6 L signal

is asserted

throughout the data transfer cycle and enables TP3

Because a GTP4 pulse is not generated during the data transfer
Counter is not clocked at the end of the cycle. Thus, the data break operation ends with

of the cycle to clear the INC ENA flip-flop.
cycle, the Increment

new data
E52 holding the BCD count of 01 10 and E46 asserting the D6 L signal. This condition exists until a
break operation, either receive or transmit, is initiated.

Note that the

NC ENA flip-flop can be cleared in three ways. Two of these have been indicated. The third way

If a test character and the received data
of clearing the flip-flop is by causing a detected character to be stripped.
test character is logic 1, the M DO L
character are the same, the COMPARE signal is asserted. If the 0-bit of the

signal causes

NAND gate E35 to assert the STRIP signal. This signal causes the receive data break operation to

E52 and E46 remain in
be terminated at the end of the current test character cycle and clears flip-flop E57.
character in location 7722 compared
the state that represents the last cycle completed. For example, if the test
successfully with the received character, the data break operation would be

count of 0010 and E46 asserting the D2 L signal.
5-29

terminated with E52 holding a BCD

5.13

CURRENT/ACCESS ADDRESS REGISTER LOGIC

The Current/Access Address Register logic is shown in Figure 5-15. This logic places a memory address on the

OMNIBUS MA lines. Since two types of addresses. Access and Current, are encountered during a data transfer,
a method of selecting one or the other is required.

This requirement is fulfilled by the DEC 8235 ICs E48, E21,

and El, which are 4-bit logic elements.

The type of address gated to the MA lines by these ICs depends on the control signal that is asserted by the Break
Grant logic.

If the

CURRENT ADDRESS L control signal

asserted, pin 7 of each IC is low, and the current

MA lines. On the other hand, if the
ACCESS ADDRESS L control signal is asserted, pin 9 is low, and the access address, which is applied to the

address, which is applied to the inverting input of the IC, is placed on the

noninverting input (indicated by the circle), is placed on the

MA lines.

An access address is formulated from two sources. The state of each of the first eight bits, MAO through MA7, is
determined by the logic in Figure 5-15. Each of MA bits
to these

through 4 is logic 1, since the IC inputs corresponding

MA bits are grounded. The user determines the state of each of MA bits 5, 6, and 7 by selectively con-

necting or removing one or more of jumpers A5, A6, and A7.

address assignment.

The selection depends on the channel access

For example, if the logic in Figure 5-15 represents Channel 1, access addresses 7720 through

7725, 7727, and 7730 are assigned. Therefore, jumpers A5 and A7 are connected, while A6 is disconnected.

The state of each of the last four bits of the access address is determined in the Access Address Counter logic.
During each data break operation, the Increment Counter in that logic counts from 0000 to 01 10 (receive data
break) or from 01 1 1 to 1001 (transmit data break).

the data break.

The count is incremented at the end of each timing cycle of

For example, consider a receive data break. The Increment Counter holds a count of 0000 just

before the first timing cycle of the data break is entered. Thus, each of MA bits 8 through 1 1
at each noninverting input of E48 is high).

data break cycle, the Increment Counter is incremented.
location addressed is 7721.

logic

(the signal

The first memory location addressed is 7720. At the end of the first

MA bit

1 1

becomes logic 1, and the second memory

In this manner, memory locations 7722, 7723, and 7724 are successively addressed.

When the Increment Counter increments to 0101 at the end of the fifth data break cycle, access address 7725 is
placed on the
is

MA lines. The next data break cycle the CA cycle. During the CA cycle, the current address that
MD lines and incremented. The Break Grant logic asserts the LOAD
is

stored in location 7725 is gated onto the

CURRENT ADDRESS L signal that loads the current address into the register consisting of the DEC 8271 ICs
E7, El 2, and E50. At the end of the CA cycle, the ACCESS ADDRESS L signal
negated and the CURRENT
ADDRESS L signal asserted. The outputs from the register, which represent the current address, are placed on
is

the

MA lines. Thus, during the next (seventh) cycle a data character

is transferred

to the memory location speci-

fied by the current address.

Note that the contents of the register can be gated to the DATA lines by the SRTA lOT instruction. This instruction is used for maintenance and program debugging.

5.14

LOAD FIELD LOGIC

The PDP-8/E basic 4K of memory can be extended in 4K increments to a maximum of 32K. Therefore, a 15-bit
address is required to specify completely a memory location.
are carried by the

EMA 0, EMA 1, and EMA 2 lines, the EMA

The three most significant bits of the 15-bit address
bit being the most significant bit.

A data break option can use an extended memory address only when specifying the location that is to take part
in the data transfer.

The word count and the current address locations (and test character locations when con-

sidering the DP8-E)

must be stored in memory field 0, the basic 4K.

5-30

note:
Logic

-MA11 L

P/0 M839 module.

-MA10 L

E48
8235

INCREMENT
COUNTER^
BITS

-o-

-MA8 L
9

^to

-MA9 L

it
-DATA 10 L

E53
8235

E50
8271

-DATA 9 L

-DATA 8 L

+ 5V

—^A(^

-MA7 L

()

-MAS L

|-0 A6 O—

4—O A5 O

•-

Vv/\

-q

E21

8235

—

-MA5 L

•-

-MA4

ll
-DATA 7 L

-DATA 6 L
E12

E36

8271

82 35

-DATA 5 L

-DATA 4 L
9

,JCI

-MA3 L

-MA2 L

CURRENT ADDRESS LEl

8235

ACCESS ADDRESS L-

-MAI L

n
-DATA 3 L

-DATA 2 L

E11

8235

8271

-DATA
-DATA

LOAD CURRENT ADDRESS

.iT^
Figure 5-15 Current/ Access Address Register Logic

5-31

Some data break devices can directly address an extended memory field via the EMA lines. However, if such a
field is used with a synchronous modem, the field can be addressed only under program control.
logic, shown in
is

The load field

Figure 5-16, enables the programmer to select the memory field to or from which a data character

to be transferred.

REMA
DATA

^TIH>
REMA

DATA

Ei1

74197

::tE>

REMA

8235

E>
9

T
REMA L
TEMA L

-n[i>
E2

74197

^-::e>
L

TEMA

Vp
TEMA 2 L

NOTE:
Logic

P/0 M866module.

Figure 5-16 Load Field Logic

The program can specify a separate field address for the receive data break and the transmit data break operations.

AC Register bits 0, 1, and 2 are loaded with the receive extended memory field address, while AC bits 3, 4, and
5 are loaded with the transmit extended memory field address. These addresses are gated onto the DATA 0—5

SLFL lOT instruction. At TP3 time of this instruction, these addresses are parallel-loaded into
DEC 74197 shift registers, the receive field address into Ell, and the transmit field address into E2.
lines by the

If a

REMA L signal throughout
gated onto the DATA lines. The REMA L signal gates the

receive data break operation is being carried out, the Break Grant logic asserts the

the timing cycle in which the received character is

outputs from Ell onto the EMA lines (the Ell outputs are inverted by selector El). Thus, the character gated

onto the DATA lines by the RCV Data Register logic is transferred to a location in the extended memory field
specified by the

EMA bits. If the PDP-8/E has only 4K of memory, the EMA bits are logic 0.

5-32

The TEMA L signal, asserted throughout the data transfer cycle of a transmit data break operation, gates the
output from E2 onto the EMA lines. Therefore, the character to be transferred to the modem is gated onto the

MD lines from an extended memory field location and shifted onto the SD line by the Transmit Data Register
logic.

5.15

DETECTED CHARACTER REGISTER LOGIC

The Detected Character Register logic is shown in Figure 5-17. The logic is used to generate an interrupt request
if a

received character matches a test character, and to identify which test character the received character

matched. For example, assume that the received character compares, bit-for-bit, with the test character stored in
location 7722. This location is addressed at the same time that the D2 L signal is asserted by the Access Address

Counter logic. The D2 L signal is asserted because the Increment Counter in that logic has been incremented to
a count of 0010 (the Increment Counter is included in Figure 5-17 for information).

When the test character in location 7722 is gated onto the MD lines near the beginning of the third data break
timing cycle, the COMPARE signal is asserted in the Receive Data Register logic. At TP3 time NAND gate E42,
Figure 5-1 7, is enabled.
character is to be stored.

CHAR DET

If the 0-bit of the test character is

NAND gate E56

flip-flop via the inverter.

therefore, the E41B flip-flop is set.

enabled.

logic

(i.e., the

Its output clocks the

MDO L signal is logic 0), the received
two E41 flip-flops and sets the

The D-input of E41 is high because of the count in the Increment Counter;

The E41 flip-flops hold the count of 10 for one character period; i.e., until a

new character has been completely shifted into the Receive Data Register. Note that if the received character is
location,
to be stripped, none of the three flip-flops is set. If the same test character is stored in more than one
and if the received character matches this test character and is to be stored, the E41 flip-flops contain the highest
location.

The 0-output of the CHAR DET flip-flop can cause an interrupt request to be generated when the data break has
ended. An appropriate program routine is entered, and the SRCD lOT instruction gates the identifying count
onto the DATA 10 and DATA 1 1 lines for further action.

5.16

INT/SKIP LOGIC

The INT/Skip logic (RING, CARRIER/AGO is shown in Figure 5-18. The logic enables the RING and

CARRIER/AGC signals to cause program interrupts and/or program instruction skips.
\l\lhen the DP8-E senses a ringing signal

from the modem, it generates a Ring flag, indicating that a modem-toIf a jumper is in place

computer transmission is to take place. This signal is applied to the interface at pin J1 X.
at location X (the jumper is removed if the

modem is a Bell 301 type), NAND gate E18 is disabled. The positive

transition at the output of the gate sets the RING flip-flop.

control, setting the RING flip-flop causes

If the

interface has been enabled under program

NAND gate E19D to assert the OMNIBUS INT RQST L signal. The

computer enters the interrupt servicing routine to determine the identity of the requesting device. The SSRG
instruction in the routine causes the lOT Decoder logic to generate the SSRG L signal throughout TS3 of the
instruction.

The SSRG L signal causes NAND gate E19C to assert the OMNIBUS SKIP L signal; thus, at TP3

time the CPU SKIP flip-flop is set and the program instruction following SSRG is skipped. When the SSRG L
subroutine that sets
signal is negated at the end of TS3, the RING flip-flop is cleared. The program proceeds to a

up the WC and CA Registers and then either waits for the modem to generate a CARRIER/AGC signal or exits
the subroutine.

5-33

O
CD
CD

Q
CD

5-34

<0 3
00 -Q

o
o

_e
g^

<
DC
LU

— £!o
tn

DC
DC

<
O
CD

I-

2
00

LfJ

<->0

5-35

—

Hi'

If a

computer-to-modem transmission is to take place, a RING signal is not generated.

Instead, a program sub-

routine sets up the registers and then enables the modem SCT L signal to set the RS flip-flop in the Control
logic.

Word

The setting of this flip-flop causes the interface to generate the SEND RQST signal that is applied to the

modem. The program then either waits for the modem to generate a CARRIER/AGC signal or exits the subroutine.

When the modem generates the CARRIER/AGC signal, whether a transmit or receive operation, the CO/AGC L
signal

is applied to

Schmitt trigger E5. The output signal from E5 takes two paths; only the path to the ON

jumper is significant when the CARRIER/AGC signal is generated at the beginning of a transmission.

If the

jumper

NOR gate El 5 is enabled, and its output sets flip-flop E24. The path leading to the OFF jumper is
significant when the CARRIER/AGC signal is negated. This happens when TERM READY has been negated by
is

in place,

either receiver or transmitter, or when a modem malfunction has interrupted the data stream.

If the

jumper is in

place when this occurs, NOR gate El 5 is enabled and flip-flop E24 is set again. Thus, the circuit can respond to
either or both transitions of the

CAR R E R/AGC signal.
I

When E24 is set, the next occurring TP4 pulse sets the CO/AGC flip-flop, and E19D can assert the INT RQST L
TP3
signal. When the SSCA L signal goes low, the SKIP L signal is asserted, and the CPU SKIP flip-flop is set at
time. The SSCA L signal is negated at the end of TS3, causing flip-flop E24 to be cleared. At TP4 time the

CO/AGC flip-flop is cleared, causing the INT RQST L signal to go high.
The INT/Skip logic (WC overflow, character detected, and bus error) is shown in Figure 5-19. The logic enables
an interrupt request to be generated when one of the events in the parentheses occurs.
During the WC cycle immediately preceding the last data transfer cycle, the OVERFLOW L signal is asserted by
the CPU. One or the other of AND gates E49A and E49C is enabled, setting either flip-flop E27 or flip-flop E29,

The 0-output of the set flip-flop enables NOR gate E43 to assert the INT RQST signal. This signal
causes NAND gate E19D, Figure 5-19, to assert the OMNIBUS INT RQST L signal. The interrupt request is
respectively.

recognized by the CPU during the first timing cycle following the data transfer cycle, provided another data break
device does not assume control of the CPU.

When the program enters the interrupt servicing routine, either the

SSRO or the SSTO lOT instruction causes the SKIP L signal to be asserted and clears the flip-flop that caused
the interrupt request.
If a

The program then proceeds to a subroutine that services the request.

test character has been detected in the transmission, the

CHAR DET flip-flop is set; the 0-output enables

NOR gate E43. When the data break has ended, the SSCD lOT instruction in the servicing routine causes an instruction skip after clearing the CHAR DET flip-flop. The program proceeds to a subroutine to determine the
identity of the detected character.

The third event that can cause an interrupt request is a bus error.

TRQST L signal or the RRQST L
ERROR flip-flop is set. Such an

either the

signal is asserted and a serial clock pulse is received by the interface, the BUS

occurrence indicates that the particular break request was not serviced by the computer because of an overloaded
or inoperative break system. Again, an lOT instruction, SSBE, in the servicing routine causes the SKIP L signal
to be asserted and clears the flip-flop that caused the interrupt request.

5.17

READ STATUS/TEST PULSE LOGIC

The Read Status logic is shown in Figure 5-20.

Significant signals in the interface are gated onto

through 7 by either of two control signals, SRS1 L and SRS2 L.
into the

DATA lines

The information on the DATA lines is loaded

AC Register at TP3 time. The logic and lOT instructions SRS1 and SRS2 are intended primarily for

maintenance and program debugging, but can be used to monitor the state of CARRIER, EMA, etc.

5-36

o
o

5-37

-DATA 7 L

MODEM RDY L
TEMA 2
REMA 2 L
TEMA

DATA 6 L

REMA L
TEMA
REMA L

DATA

SYNC

DATA 3 L

5 L

DATA 4 L

L-

SYNC 2 L

DATA 2 L

Ell

8235
T

P/0 M839

RQST L

DATA

R RQST L

SRS

O E12

RS (1

\>-

)

-^VW-i—
E5

•—O E21

NOTE:
Unless noted otherwise, logic is

P/0 M866 module.

Figure 5-20

Read Status Logic

Another instruction that can be used during maintenance is the SRCD instruction that is normally used to gate
detected character information onto the DATA TO and DATA 1 1 lines.

When used with the Test Pulse logic,

shown in Figure 5-21, the SRCD instruction can cause a single clock pulse to be generated. This pulse is routed
through a test connector and returned to both the SCR and SCT input lines of the interface, enabling single-step
testing of the receive and transmit circuits.

The ACO bit must be logic 1 when the SRCD instruction is issued,

NAND gate E23, Figure 5-21, sets the E23

NOR-gate flip-flop. This flip-flop is cleared by the BTP4 pulse; thus, a negative pulse of approximately 600-ns
width is produced at the emitter of Q1 and gated to the emitter of Q2, as a positive pulse.
at location F, and if the test connector PI

If a

jumper is in place

connected to J1, the pulse is returned on the SCR and SCT lines

(see Section 5, Maintenance, for further information about the test connector).

5-38

DATA

SCR (TEST PULSE)

J1R

SCT (TEST PULSE)

JtN

J1FF

J1L
(EXT TIMING)

NOTE:
Logic is P/0 M866 module

Figure 5-21

Test Pulse Logic

The four-transistor gating circuit can also be used to gate an external clock to the modem, which has an external
timing mode. The external clock is applied at the input designated EXT CLOCK L (etched on the printed circuit
board as EXT CLOCK), and a jumper must be installed at location L.

5.18

LEVEL CONVERSION CIRCUITS

The M866 Module contains the DPB-E level conversion circuits. Figure 5-22 illustrates the method used to convert
either EIA or current mode signals to the TTL levels required by the DPB-E. The CLEAR TO SEND signal conversion circuit is used as an example.

CLEAR
TO

JITO

SEND

Figure 5-22 DPB-E Input Circuit (Receiver)

5-39

If the

CLEAR TO SEND signal is an ElA-type signal (bipolar), a "mark" is represented by a voltage level of -5V

to -15V; a "space" is represented by a voltage level of +5V to +15V.

A mark, which indicates that the CLEAR
TO SEND signal is not asserted, turns off 017, and the CS signal is negated (logic 0); a space turns on 017,
thereby asserting the CS signal.

CLEAR TO SEND signal is a current mode signal, a jumper is connected at location C. An input current of
mA represents a mark, which indicates that the CLEAR TO SEND signal is negated. 017 is nonconducting, and the CS signal is low. A space is represented by an input current of greater than 23 mA, which proIf the

less than 5

duces a base voltage sufficiently high to turn on 017, thereby asserting the CS signal.
Figure 5-23 illustrates the method used to convert the DP8-E TTL signals to either EIA or current mode signals.
The SEND DATA L signal conversion circuit is used as an example.

H5V

SEND DATA

note:
Connect jumper as indicated in table

SIGNAL TYPE

CONNECT JUMPERS
(REMOVE OTHERS)

EIA
CURRENT MODE
TTL

CE(2),CT

E.CE (2)
T(2),CT

Figure 5-23 DP8-E Output Circuit (Driver)

The output transistors, 08 and 016, are connected for push-pull operation and are controlled by transistors 07
and 015. As the table in Figure 5-23 indicates, jumpers E and CE are connected for TTL-to-EIA level conversion.
If the
is

SD L signal is high, logic 0, both 07 and 015 are nonconducting. Diode D12 is reverse-biased, while D1

forward-biased. Thus, 016 connects the SEND DATA line to a voltage that varies between 5V and 15V,

depending on the load.
If the

SEND DATA L signal must be current mode, the CE and CT jumpers are connected.

high, logic 0, 016 provides the load current of greater than 23 mA, indicating
signal

SD L signal is
a space condition. When the SD L

asserted, diode D12 is forward-biased; 08 provides the load current of less than

5-40

If the

5 mA, indicating a mark

condition on the SEND DATA line. Note that the CT jumper, by placing D12's plate just below ground rather

than at -6V, changes the operating point of Q8 from what it was during EIA conversion.

Table 5-4 lists the control signals and data signals and relates the two types to mark/space, logic 1/logic 0, etc.
Table 5-5 lists the EIA and current mode specifications for reference.

Table 5-4
Signal Level Terminology

Data Signals

Control Signals

RING

Mark/

High/

Asserted

Space

Low

Not Asserted

Mark

Low

Not Asserted

Space

High

Asserted

CARRIER/AGC
SCR
SCT

INTERLOCK/DATA SET READY
CLEAR TO SEND
TERMINAL READY
SEND REQUEST
EXTERNALTIMING
J

RECEIVE DATA Ci

Mark

Low

Asserted

SEND DATA L

Space

High

Not Asserted

Table 5-5

EIA/Current Mode Electrical Specifications
Current mode specifications (applicable to Bell 300 Series Modem, or equivalent).

EIA (RS-232-C) Electrical Specifications
Driver output logic levels with 3K to 7K load

1 5V > V^,^ > 5V
-5V>V^, >-15V

Driver output voltage with open circuit

V^ < 25V

Driver output impedance with power off

Z o >3Q0n

Output short circuit current

lo<5A

Driver slew rate

•^<30V/)Us
dt

Receiver input impedance

7kn >R,^>3kn

Receiver input voltage

±15V compatible w/driver

Receiver output with open circuit input

Mark

Receiver output with 300f2 to ground on input

Mark

Receiver output with +3V input

Space

Receiver output with -3V input

Mark

(continued on next page)

5-41

Table 5-5 (Cont)
El A/Current Mode Electrical Specifications

+15
Logic "0" = Space = Control On

Transition Region

Logic "1" = Mark = Control Off

Current Mode Electrical Specifications (Applicable to the Bell 300 Series Modem or equivalent)
Receiver Input Current/Voltage levels with

mA (-0.7 < Ew < 1)

10012 Termination

Mark

Driver Output Impedance with Power Off

Not Specified

Driver Output Short Circuit Current

Not Specified

Driver Slew Rate between the 7

mA and the

mA levels

14mA/100ns
Maximum 14 mA/50 ns
Minimum 14 mA/200 ns

Typical

Receiver Input Impedance

120>Z.in >90

Receiver Output with Open Circuit Input

Logic 1 - Mark-Off

Receiver Output with Input

> 23 mA

Logic

Receiver Output with Input

< 5 mA

Logic 1 - Mark-Off

— Space— On

Mark to Space or Space to Mark must be achieved

Driver Distortion Limits

within 25% of bit interval
Receiver Open Circuit Voltage

-0.8V to -1.3V

SECTION 5 MAINTENANCE
General instructions concerning preventive and corrective maintenance are given in Volume 1, Chapter 4.

Two

maintenance aids are available when corrective maintenance of the DP8-E is required. One, the diagnostic program, MAINDEC-08-DHDPA-A, can help the technician to determine the nature of the problem. The other, a
self-test feature, enables the technician to single-step test both the receive and transmit logic.

To use the self-test feature, the technician must connect the test connector to the plug on the modem side of the
interconnecting cable.
interface signals.

The internal wiring of the test connector enables software simulation of the modem-

Figure 5-24 is a pictorial representation of the signals involved in the self-test feature.

the M866 "F" jumper and either the "N" or "A" jumper (Table 5-2) must be connected.

Note that

When the technician

wishes to check the receive or transmit logic, he can, by careful selection of lOT instructions, assert or negate

any of the signals shown in Figure 5-24. The SRCD instruction generates a single clock pulse that is returned on
both the SCR and SCT lines, thereby enabling all other signals to be generated. See Paragraph 5.16 for additional
information concerning the self-test feature.

5-42

MODEM

TEST
CONNECTOR

CONNECTOR)

CABLE
BC01V/
*BC05C

M866
PI

SEND DATA
(

)

(

(
)

RECEIVE DATA
J

0N0— N
©A©— R
(2^0— FF

SCT
SCR

-k,^

•^

SELF-TEST PULSE
CLEAR TO SEND

SEND REQUEST
V

INTERLOCK/DATA SET RDY

RING
X

CARRIER / AGC
BB

TERMINAL READY

20 •r

8E-0479
*Preferred cob le

Figure 5-24 Self-Test Interconnection

When performing corrective maintenance, the technician should refer to the option schematics, E-CS-M839-0-1
and E-CS-M866-0-1, rather than to the logic extracts in this volume. Table 5-6 lists the modem-interface signals
and the corresponding cable connector pin information. Top-connector "H" on the M866 Module, an alternate

M866-M839 Module
Input/output connector, is shown in parentheses with the J1 pin number. Table 5-7 lists the
interconnecting signals and indicates the source module.

Table 5-6

Modem-Interface Cable Pin Information

Signal Name

J1 (H) M866

P2 (DP8-EA)

P2 (DP8-EB)

40-Pin Berg

25 Pin Cinch

12-Pin Burndy

SEND DATA

F (HE2)

RECEIVE DATA L

J{HF2)

EXTERNAL TIMING

L(HH1)

SCT

N (HH2)

SCR

R(HJ2)

CLEAR TO SEND

T(HK2)

SEND REQUEST

V(HL2)

RING

X(HM2)

Z(HN2)

BB (HP2)

INTERLOCK/DATA
SET READY

CARRIER/AGC

No Connection (Bell 301)
F-Shield (Bell 303)

(continued on next page)

5-43

Table 5-6 (Cont)

Modem- Interface Cable Pin Information
Signal Name

TERMINAL READY
USER FUNCTION

AND SELF-TEST
PULSE

USER FUNCTION

FRAME/SIGNAL

GROUND

J1 (H) M866

DD(HR2)
FF (If Jumpered)

(HAD

P2 (DP8-EA)

P2 (DP8-EB)

25 Pin Cinch

12-Pin Burndy

(HBl)

^^(HT1,HC2)

No J1 Connection
(HS2)

6.4V

No Connection (Bell 301)
M-Shield (Bell 303)

JJ (If Jumpered)

(HC1)

-6V

PI
40-Pin Berg

No J1 Connection

EXTERNAL TIMING,

(HV2)

TTL LEVEL

No J1 Connection

Table 5-7

M866-M83J3 Top-Connect or Signals
Signal Name

SRCD L
THIS CODE
INT RQST
RD

"F" Ccmnector Pin N umber
FA1
FBI
FC1
FD1
FE1

Source Module

M839

M866
*

*
*
*

REMA L
TEMA L

FF1

SCR-P L

FH1

BREAK GRANT

FJ1

INI L

FK1

GTP4

FL1

BREAK RQST

FM1

SSBEL

FN1

*
*

SCT-P L

FP1

FR1

SD L

FS1

IDLE L

FT1

RQST
SRS1 L

FU1
FV1

GROUND

FA2

GROUND

FV2
5-44

*
*
*

z
c
2

LU
DC

LU
1LU

'+3

o
(5

t
o
o
<

Q
Z o
3 u
O Q
DC
Z
CJ
LU O
>

<
1<
Q
Q

<
z
o o
az

Z
<

1—

J3
CO

DC
1-

Q
< z
LU
< o
Q 1Q hUJ
> LU
D
UJ
u
a
UJ
LU
C/D

Q
z
LU
CO

o
H
DC

<
LU
_I

>
Q
<
LU

DC
_i

<
z

o
1-

C/3

DC
LU
h-

<
H
<
Q

\LU

CO
lU

Q
z
C3

z
DC

Q
LU
>
UJ
o
LU
DC

-J
UJ LU
l- to
LU
lU

_l
LU

CO
LU

LU
1-

LU
_l
LU

UJ
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<
Z

<
z

LU
_l

o H H (D
o
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CO
H CC DC CO
z
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< < < LU UJ UJ UJ
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1-

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z UJ 3 <
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03

C/3

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LU LU
h- CJ

cc
13

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< <

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LU
CJ

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CM

CM
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cx)

I
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<
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rCM

t
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O
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LO
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LU
DC

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DC QC
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<
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z
LU
to

<
1<
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LU
>
LU
CJ
LU
DC

Q
Z
LU
1-

Q
Z
LU
C/0

<
1<

O
^

Q
<
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<
LU
_l

<
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DC
LU

DC
LU
\-

C/5

O
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DC
a:

u
t
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5
7

5-45

DC
LU

Q
UJ LU
to
00
a.
1-

n Z
D

^
L

3
Q
O Z
z

o
hu
z

=)
LL
DC
UJ
to

Z Q_
^
ot5
Z u.
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3
LL LU
^
cr
li Q
to Z
3 <

LU
CO
Q.

Q
z
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LU
to

3
H
O
z

DC
CD
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<
Z
CD
to
UJ

<
DC
LL

Table 5-8 relates the DP8-E interface signal designations to both the equivalent EIA (RS-232-C) and
lent CCITT circuit designations.

the equiva-

For example, the DP8-E signal called SEND DATA is brought out to pin 2 of P2

(DP8-EA). The EIA circuit designation for this signal is "BA", while the CCITT circuit designation is "103".

SECTION 6 SPARE PARTS
Table 5-9 lists the recommended spare parts for the DP8-E. These parts can be obtained from any local
DEC
office or from DEC, Maynard, Massachusetts.

Table 5-9

DP8-E Recommended Spare Parts

DEC Part Number

Description

Quantity

19-09667

IC74H74

19-10035

IC 74197

19-09057

IC74H10
IC 74H04
IC74H00

19-09931

19-09056
19-09935

19-05578

IC8235
IC8266
IC8242
IC8881
IC314
IC 7404
IC8271
IC8251
IC384
IC380
IC 7402
IC 7420
IC7410
IC 7400
IC7474
IC74H11
IC7430

19-09373

IC 9601

19-09934
19-09712
19-09705
19-09704
19-09686
19-09615

19-09854
19-09486
19-09485
19-09004
19-05577
19-05576
19-05575
19-05547

19-09267

1
1

3
1

2
1

3
1
1

2
2
1
1

3
1

1
1

11-00114

Diode, D664

11-00113

Diode, D662

15-03100

Transistor, 3009B

15-03409-2

Transistor, 7534C

11-01938

Diode, 1/4M, 2.4AZ

11-00124

Diode, IN750A, 1/4W4.7J

5-46

CHAPTER 6
KG8-E GENERATOR/DETECTOR

SECTION 1

INTRODUCTION

The KG8-E BOG Generator/Detector option consists of a single quad module that plugs into the PDP-8/E

OMNIBUS. The option operates under program control to provide the computer with a parity-check capability.
Although intended to be used with data communication equipment, the option is independent of such equipment
and can be used with other devices.
F'arity checks are carried out in the KG8-E on data characters that are transferred from the PDP-8/E

a programmied I/O transfer.

The KG8-E can perform three types of parity checks:

memory by

a vertical redundancy check

(VRC) can be performed on a 6-, 7-, or 8-bit character; a longitudinal redundancy check (LRC) can be made on a
message consisting of 6-, 7-, 8-, 12-, or 16-bit characters; and a cyclic redundancy check (CRC) can be carried out

on a message consisting of 6-, 8-, 12-, or 16-bit characters.

A VRC can be performed separately or as part of either

an LRC or a CRC.
Publications and documents that are relevant to the KG8-E are:

PDP-8/E & PDP-8/M Small Computer Handbook - D EC, 1 972
PDP-8/E Maintenance Manual, Volume 1
KG8-E Diagnostic Program, MAINDEC-8E-D8CA

DEC Engineering Drawing, E-CS-iVI 884-0-1.

SECTION 2 INSTALLATION AND CHECKOUT
The KG8-E option is installed on site by DEC Field Service personnel. The customer should not attempt to
unpack, install, checkout, or service the equipment.
Insert the module in the PDP-8/E OMNIBUS.

See Table 2-3, Volume 1, for information concerning recommended

module priorities (the KG8-E is a "non-memory" option).

The KG8-E can be checked for correct operation by running the diagnostic program.
refer to Chapter 4, Volume 1.

6-1

maintenance is necessary,

SECTION 3 PARITY CHECK/BLOCK DIAGRAM
6.1

PARITY CHECK

The three types of parity checks performed by the KG8-E are VRC, LRC, and ORG.

A general description of

each type follows.

6.1.1

VRC Parity Check

A VRC is carried out on each character of a message. The summation of all logiic-1 bits within the character
must be even or odd, whichever is desired. The KG8-E examines each character: when the character is part of a
message that is to be transmitted to some external device from memory, the option adds a parity bit (logic 1), if

one is needed; when the character is part of a message transmitted from an external source to memory, an errordetecting software routine is entered, if the character does not exhibit the correct parity.
is

In one instance parity

generated; in the other, parity is tested. Although each operation is different, the terms VRC and parity check

are used to refer to either operation.

6.1.2

The logic implementation of a VRC is detailed in Paragraph 6.5.

LRC Parity Check

A distinction similar to that expressed in the preceding paragraph is unnecessary when either an LRC or a CRC is
performed. Each of these parity checks is the same, regardless of the direction of the message transfer. The LRC
parity check is based on the accumulation of a block check character (BCC).

The KG8-E generates this BCC by

Exclusive-ORing the contents of corresponding bit positions in each character of the message. For example,
consider a message consisting of the following four 8-bit characters:

MSB
Character 1

110

Character 2

Characters

1110

Character 4

LSB

110 10

10
10

BCC

one Exc!usive-ORs corresponding bit positions, the BCC shown results. Figure 6-1 illustrates how Exclusive-

ORing is implemented by the KG8-E logic; the chart shows the state of the BCC Register at various stages of BCC
accumulation for the four characters.

The first character is parallel-loaded into the Parity Register from the DATA lines by a program instruction.
Clock pulses shift the character into the BCC Register (although shown as an 8-bit register, for convenience, the

BCC Register is 16 bits in length; characters are loaded into the register in a right-justified format). With each
clock pulse, the bit in the LSB position of the Parity Register is Exclusive-ORed with the bit in the LSB position
of the BCC Register.

The result is shifted into the MSB of the BCC Register by the next clock pulse. Eight clock

pulses shift the entire character into the BCC Register.

The second character is then loaded into the Parity

the KG8-E and memory are of the programmed I/O type, the operation can be interrupted by program interrupts
or data breaks after each character transfer).

6-2

\ \
\

)j
1L

PARITY REGISTER
1

CLOCK
PULSE

^^y
>^

BCC REGISTER

LSB

CIO

C11

C12 C13 C14 C15

l— DATA 4-11 L
'

8E-0482

CHARACTER 1: 01100010
CHARACTER 2: 10010001
CHARACTERS: 11100000
CHARACTER 4: 10011010
CHARACTER/BIT LOADED

CLOCK PULSE

BCC REGISTER CONTENTS
C8

CIO

C11

C12

CIS

C14

C15

START

CHARACTER 1, BIT
CHARACTER 1,BIT2
1

•
.

CHARACTER 1,BIT8
CHARACTER 2, BIT
CHARACTER 2, BIT 2
1

CHARACTER 2, BITS
CHARACTERS, BIT
CHARACTERS, BIT 2
1

1
1

•

1
1

•

CHARACTERS, BITS
CHARACTER 4, BIT
CHARACTER 4, BIT 2
1

24
25
26

1
1

CHARACTER 4, BITS

r-^

BCC
Figure 6-1

LRC BCC Accumulation for Four 8-Bit Characters

When all four characters have been shifted into the BCC Register (S2 clock pulses), the result in the register is the
BCC.

If the

message is to be transmitted from memory, the BCC is transmitted as the last character of the

message. Similarly, if the message was received from an external device, the four characters already considered
are followed by a BCC that was generated in the transmitting device.
into the Pari-ty Register.

The BCC is treated as a character and loaded
When it has been shifted into the BCC Register by eight clock pulses, the register con-

tents will be zero, it the message has been received free of error.

entered by the computer.

6-S

If not, an

error detecting software routine is

Note that there is no reason why a VRC cannot be performed before an LRC (or before a CRC, for that matter).

Such a procedure enhances the error-detecting capability provided by the KG8-E.

In such a case, bit position

or 7 of the example would contain the parity bit. Although the example illustrates the LRC BCC accumulation
for an 8-bit character, the LRC can be carried out for 6-, 7-, 12-, and 16-bit characters, as well.

The procedure is

the same, as will be demonstrated in Paragraph 6.8.

CRC Parity Check

6.1.3

A CRC is also based on the accumulation of a BCC; however, the generation of the BCC is more intricate than
during an LRC. A number of different CRC codes can be used, but the KG8-E implements only two, viz.,
CRC-12 and CRC-16. Unlike LRC, CRC concepts are best understood through a mathematical background,
followed by a description of the logical implementation of the mathematics.

A CRC code message consists of a specific number of data bits and a BCC that is generated by the KG8-E.

Let n

equal the total number of bits in the message and k equal the number of data bits; then, n-k equals the number of
bits in the BCC.

binary words.

The code message is derived from two polynomials that are algebraic representations of two

The generator polynomial, P (X), reflects the type of code used (CRC-12, CRC-16), and the mes-

sage polynomial, G (X), represents the string of serial data bits.

The polynomials are usually represented algebra-

ically by a string of terms in powers of X, as X"+...+X'^+X^+X+1.

that contains a term; the absence of a term is indicated by a 0.
place the LSB (X°, or 1) at the right.
is

In binary form, a

placed in each position

The convention followed in this manual is to

For example, if a polynomial is given as X^+X+1, its binary representation

1001 1 (third and second degree terms are not present).

Given a message polynomial, G (X), and a generator polynomial, P (X), the objective is to construct a code
message polynomial, F (X), that is evenly divisible by P (X). This is accomplished as follows:
a.

Multiply the message, G (X), by X""^, where n-k is the number of bits in the BCC.

Divide the resulting product, X"'"^ G (X), by the generator polynomial, P (X).

Discard the quotient; add (binary addition) the remainder, C (X), to the product of Step a.
The result is the code message polynomial, F (X), represented by X""'^G (X)+C (X).

The division is performed in binary without carries or borrows.

In this case, the remainder is always one bit less

than the divisor. The remainder is the BCC, and the divisor is the generator polynomial. Thus, the bit length of
the BCC is always one less than the number of bits in the generator polynomial.

A simple example is carried out

in the following steps:

Given: Message polynomial, G (X) = 110011 (X^+X^^+X+l)

Generator polynomial, P (X) = 11001 (X'^+X^-H)

G (X) contains 6 data bits; P (X) contains 5 bits and yields a BCC of 4 bits; thus, n-k=4.
b.

Multiplying G (X) by X""'' gives

X^i^G (X) = X"* (X^+X^+X+l) = X^-hX^+XHx^

The binary equivalent of the product is 1 1001 10000.
c.

Dividing the product by P (X) gives

Quotient

1100110000 ^

X"^G(X)

100001

P(X)-> 11001

11001

10000
11001

1001^

Remainder = C (X) = BCC
(continued on next page)

6-4

Adding the BCC to the product of Step b. gives
F (X) = 1100111001

The code message polynomial is transmitted. The receiving station divides it by the same generator polynomial.
If there is

A remainder indicates an error. The result of the division

no error, the division produces no remainder.

is shown below, with the result indicating an error-free message.

100001

P(X)-»11001

11100111001^

F(X)

11001
11001
11001

00000 ^

Remainder of

A more practical example, the mathematical derivation of a CRC-12 BCC, is now detailed. This example derives
the BCC of a 2-character message. The KG8-E logic implementation of the mathematics is then presented.

The message characters are: character 1 000 000 000 101 and character 2, 000 000 001 000 (PDP-8/E convention is followed throughout; i.e., LSB position is on the right). When a character is transferred to the KG8-E
,

;

from memory, the LSB of character 1 is the first bit shifted into the BCC Register. Therefore, G (X) = X^^+X^ + 1
(000 000 001000 000 000 000 101). P(X) for CRC-12 is X^2+xii+x3+x2+X-H (1100000001111). The BCC
is

always one bit less than the P (X); thus, the quantity n-k is 12. Because of the way that the KG8-E implements

the mathematical derivation, the message polynomial, G (X), is modified and re-designated G' (X).

The modifi-

cation merely reverses the order of the character bits of G (X). Thus, G' (X) in this example is X^-^+X^^+X^

The quantity G' (X)X"'' = (X^^-hX^^'+X^) X^^ = X^^+X^+X^^. The long

(101 000 000 000 000 100 000 000).
division of G' (X)X"-'^

by P (X) follows.

110 000 000 111 100 111 001 100

1100000001111

101 000 000 000 000 100 000 000 000 000 000 000

110 000 000 111

000 000 111 10
1 1 000 000 01111
100 010 100 000
110 000 000 111 1

10010100111 10
000 000 01 1 1
010 100 100 010
1 100 000 001 111

1 1

110 100 101 101
110 000 000 111 1
100 101 010 100
110 000 000 111 1
10 101 010011 10

000 000 011 11
101 010 000 010
1 100 000 001 111
1 010 001 101 000
1 100 000 001 111
110 001 100 111
110 000 000 111 1
001 100 000 100^ BCC

11
1

LSB

6-5

The remainder is the BCC of the two-character message. Note that the LSB is on the left. The BCC is logically
added to the quantity G' (XIX""*" (MSB is added to MSB) to obtain the code message polynomial, F (X), as

shown below.
F (X) = G' {X)X"-^ + BCC = X^+X^+X^°+X^+X^+X^

The F (X) is transmitted. The receiving station divides the F (X) by the P (X). An errorless transmission results
in a remainder of zero (this division is not shown; the reader can verify the fact that the division produces a zero

remainder).
Figure 6-2 is a representation of the BCC Register in its CRC-1 2 configuration (the configuration is different for

CRC-16), The accompanying chart indicates the content of the register after selected bits of the two example
characters have been shifted into the register (space limitations prevent each step from being shown).

The bit in

the LSB position of the character is Exclusive-ORed with the bit in the LSB position of the BCC Register.
result is either shifted directly into the register or Exclusive-ORed again and then shifted.

takes place after the Exclusive-OR has been accomplished.

The

Either way, the shift

The chart carries the process through 36 clock pulses.

The first 24 pulses shift the two characters into the register. After the 24th clock pulse, the BCC has been
accumulated, as shown. Note that the LSB is on the right.
If the

message is to be transmitted, the BCC is added to the G' (X)X""'', as indicated earlier; then, the F (X) is

transmitted.

However, if the message was received from an external source, the two characters are followed by

the BCC computed by the external device.

In this case, the BCC is shifted into the KG8-E

BCC Register by the

next 12 clock pulses, as illustrated in the chart. The result, zero, indicates no error in the transmission.

The procedure is the same for CRC-16, except that the P (X) is different. The BCC Register logic is manipulated
by control signals to implement the mathematical derivation. The logic is explained in detail in Paragraph 6.8.

6.2

BLOCK DIAGRAM

The block diagram of Figure 6-3 presents the various logic sections of the KG8E and illustrates their interrelationship.

A detailed discussion of each section follows the block diagram description.

The lOT Decoder logic decodes bits MD3-1 1 to generate the lOT signals shown in the figure (see Table 6-1 for
a complete list of the KG8-E

lOT instructions). The type of parity check carried out by the KG8-E is determined,

basically, by the lOT instruction issued, viz.,
is

RCCV, RCGB, or RCTV. The way that the selected type of check

performed is determined by control signals generated in the Control Register logic.

The Control Register logic is loaded from the AC Register, via DATA lines 5-11, by the RCLC instruction. This
instruction is issued before the type of parity check is selected.

The control signals generated in response to the

RCLC instruction determine how the parity check is carried out: the PARITY signals (2 signals) determine where
a generated parity bit is placed in a character during a VRC; the

VRC (RCGB) signals (3 signals) are generated

when a VRC is to be carried out along with an LRC/CRC; the CRC/LRC (0) signal manipulates the BCC Register
so that either an

LRC or a CRC is carried out; finally, the BIT signals select the BCC Register configuration and

the number of clock pulses per burst appropriate for the message character bit length.

A character is transferred from the AC Register, via DATA lines 4-1 1, to the VRC logic in response to either an
RCCV instruction or an RCGB instruction. If a VRC check (as opposed to a test) is carried out, the generated
parity bit and the character are returned to the AC Register, again on DATA lines 4-11. The COMPUTE VRC
signal is asserted and applied to the I/O XFER logic to control CPU timing during the return transfer. If a VRC
test is performed, the character is not returned to the AC; rather, the PARITY signal is used to check that the

character exhibits the correct parity.

6-6

FEEDBACK

MSB

— CO

—®—

—-®— —-®—
C2

CIO

C11

C12 C13 C14

—®-^ ^
C15

SERIAL INPUT
FROM PARITY
REGISTER

MSB

LSB

CHARACTER 1: 000 000 000 101
CHARACTER 2: 000 000 001 000
CLOCK

PULSE

CIO

C12

C11

C13

C14

C15

SERIAL
FEEDBACK
INPUT
1

14
16

23
24

1
1

L BCC
25
26

1
1

33
34
35
36

NOTES:
= BCC Register Stage; C-Number refers to the bit used (see Paragraph 6.8)
1.
2. ® = Exclusive-OR

operation

P (X) == Xi2+xii+x3+x2+X+l

Figure 6-2

CRC BCC Accumulation for Two 12-Bit Characters

6-7

1
1

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6-8

Table 6-1

KG8-E lOT Instruction List
Octal Code

6110

Function
Test VRC and Skip.

the VRC logic is wired for an odd

parity check, the next program instruction is skipped when

the character exhibits odd parity; if the logic is wired for an

even parity check, the next program instruction is skipped

when the character does not exhibit even parity.
6111

Read BCC high. Jam-transfers the 8 most significant bits
of a BCC to AC4-1 1 (the MSB goes to AC4); used for a
16-bit accumulation.

6112

Read BCC low. Jam-transfers the BCC to the AC Register.
The number of bits involved depends on the type of parity
check performed. The LSB of the BCC is transferred to
AC11.

6113

Compute VRC.

Transfers a character from AC4— 1 1 to the

Parity Register and clears the AC; causes the

VRC logic to

check for odd or even parity and add a parity bit to the
character if necessary; returns the character to the AC with
the parity bit being jammed into either AC4 or AC1 1

6114

Generate BCC. Generates an LRC or CRC BCC; the BCC is
either transmitted as part of the message or compared to a

BCC that has been received. This instruction causes the

RCTV and RCCV operations to be carried out before the
BCC generation, providing the Control Register logic has
been properly programmed (see the RCLC instruction).
6115

Load Control Register. Defines the type of parity check
carried out, and programs the logic for the correct num-

ber of bits per character. See the Control Register logic.

Paragraph 6.4, for the relation between AC bit and Control
Register function.

6116

Clear BCC Register. Clears the 16-bit BCC Register.

6117

Maintenance Test Clock.

If test

point DAI on the module

is grounded, this instruction causes a single clock pulse to

be applied to the logic; the technician can use this pulse for
single-step testing of the KG8-E.

When a CRC/LRC follows the VRC, or when such a check is performed alone, each character is first loaded into
the VRC logic Parity Register. 9.5 MHz clock pulses shift the character from the VRC logic, via the BCC parity

BCC logic. A BCC is accumulated in the BCC Register in either CRC or LRC format. The generated
BCC is transferred to the AC Register on DATA lines 0-1 1 in a format determined by the type of check perline, to the

formed and by the number of bits per message character. The transfer is directed by either the RCRL instruction
or the RCRH instruction, or both.

6-9

SECTION 4 DETAILED LOGIC
6.3

lOT DECODER LOGIC

The lOT Decoder logic is shown in Figure 6-4.

Bits IVIDS— 8 are gated with the I/O PAUSE

L signal to generate

NAND gate E3 asserts the OMNIBUS INTERNAL I/O L signal, causing the positive I/O bus
interface to ignore the lOT instruction. During TS3, the 61 IX signal
gated with bits MD9—
in the 8251

the 61 IX signal.

1 1

BCD-to-decimal decoder to produce the listed lOT signals.

^-—g>o

17)
DtO L

I/O PAUSE L

E39

MD3 L
011 L

d
f-ol

MD5 L

M[D6 L

E10

)

(

(i_y

t1E>
Figure 6-4

6.4

INTERNAL I/O L

lOT Decoder Logic

CONTROL REGISTER LOGIC

The Control Register logic is shown in Figure 6-5. The logic includes seven flip-flops and a BCD-to-decimal

When the RCLC lOT instruction is issued, the information in the AC Register gated onto the
DATA lines during TS2; the information remains on the lines for the rest of TS2 and throughout TS3. At TP3

decoder, E8.

time, all seven flip-flops in the logic are clocked.

The resulting state of each flip-flop depends on the state of the

appropriate AC Register bit. The AC Register bits are related to the control signal functions as follows:

AC5= 1: CRCBCC
0: LRCBCC

AC6 78
000 16-bit BCC
00

12-bit BCC

8-bit BCC

1
1

7-bit BCC

100

6-bit BCC

AC9 =

Generated parity bit to AC 1

Generated parity bit to AC4

AC1

= 1

AC1 1 = 1

A VRC check RCCV) is performed prior to a BCC accumulation.
A VRC test (RCTV) is performed prior to a BCC accumulation.
(

6-10

CRC/LRC (0)
CRC/LRC
RCLC L

TP3

—

E12
8271

E8
8251

BITS
E12
C

8271

,_I

LSB

BITS
E12
8271

LEFT PARITY
RIGHT PARITY

VRC

E12

——

8271

E29

V
VRC (RCGBXO)
VRC (RCGB)(1
°

VRC

)

(RCGB)
C

10 L

E29

}

VRC TEST (RCGB)(1
VRC
TEST
C

—q_

E29

(RCGB)

\
>
'

Figure 6-5 Control Register Logic

6-11

)

VRC LOGIC

6.5

The VRC logic is shown in Figure 6-6. The logic includes an Exclusive-OR circuit, comprising gates E16, E20,
and El, and jumper locations E and 0, and an 8-bit Parity Register, comprising ICs E14 and E34. Both the
Exclusive-OR circuit and the Parity Register are used when an RCCV instruction is issued. This instruction causes
a character to be gated from the

AC Register onto the DATA lines. The Exclusive-OR logic examines the charac-

ter and generates a parity bit, if one is required.

The character and the parity bit are then loaded into the Parity

DATA lines, and returned to the AC Register.
Only the Exclusive-OR circuit is used when an RCTV instruction is issued. This instruction also causes a character
to be gated from the AC Register to the

DATA lines and examined by the Exclusive-OR circuit. However, a

parity bit is not generated, and the Parity Register is not loaded.

Rather, the I/O Transfer logic monitors the

PARITY signal to determine if a program instruction must be skipped (Paragraph 6.7). Thus, the RCCV instruction is used to provide the correct parity for characters that are to be transmitted from memory; conversely, the

RCTV instruction is used to check the parity of characters that have been received and stored in memory (the
term "a VRC" is used to indicate the execution of either an RCCV or an RCTV instruction). The RCTV instruction logic is described in Paragraph 6.7; the discussion that follows details how the VRC logic provides the correct
parity for characters destined for transmission.

A VRC can be performed independently or in conjunction with either an LRC or a CRC.

If only a

VRC of a

character is to be made, the program issues an RCCV lOT instruction. This instruction gates the character from

the AC Register onto the DATA lines and causes the lOT Decoder logic to generate the RCCV L signal. This
signal enables

NOR gate E28 (Figure 6-6) to assert the COMPUTE VRC signal and causes the Parity Register to

be placed in parallel-load mode (pin 13 of both E14 and E34 is taken low).

The VRC flip-flop in the Control Register logic will have been set or cleared by a previous RCLC instruction.
Therefore, either the LEFT PARITY signal or the RIGHT PARITY signal is high when the COMPUTE VRC signal

asserted. This discussion assumes that the LEFT PARITY signal has been asserted; thus, the character bits on

DATA lines 5—1

are gated to the parallel-load inputs of the Parity Register and to the Exclusive-OR circuit,

which checks for odd or even parity (the state of the DATA 4 line is immaterial, because NAND gate E9A is
disabled).

The discussion assumes that an odd-parity check is desired; thus, jumper

connected.

acter contains an odd number of Is in bits 5—1 1 (odd parity), the PARITY signal is asserted; the

input of El 4 (pin 3)

low, i.e., a parity bit need not be added to the character.

tains an even number of Is in bits 5—1 1, the PARITY signal is negated.

pin 3 of El 4 is high.

If the char-

DATA 4-bit

However, if the character con-

AND-NOR gate E32B is enabled, and

The Parity Register is loaded with an odd number of Is, a parity bit being loaded into the

bit 4 position.

If an

even-parity check is desired, the E jumper, rather than the

jumper, is connected; if the character gated

from the AC Register contains an odd number of Is, a parity bit is added. The parity bit can be loaded into the
bit

1 1

position if the RIGHT PARITY signal, rather than the LEFT PARITY signal, is asserted.

The Parity Register is loaded at TP3 time of the RCCV instruction, on the leading edge of the pulse at pin 6 of
both E14 and E34. At the same TP3 time, but on the trailing edge, the VRC XFER CNTL flip-flop is set, gating
the character in the Parity Register onto the DATA lines.
into the register at BUS

The character is gated to the AC Register and loaded

STROBE time (see Paragraph 6.7 for details).

6-12

o
DC
>
CO
CO

6-13

As noted earlier, a VRC can be performed in conjunction with eitiier an LRC or a CRC. The VRC (RCGB) flipflop in the Control Register logic must be set by an RCLC lOT instruction. Then, an RCGB instruction causes

the lOT Decoder logic to generate the RCGB L signal. This signal causes the COMPUTE VRC signal to be gene-

NAND gate E28 and NOR gate E28) and the Parity Register to be placed in the parallel-load mode.
Thus, the VRC is carried out in the same way as the RCCV instruction. However, after the character in the
rated (via

Parity Register has been gated to the

AC Register and loaded, the same character must be transferred to the BCC
When the RCGB L signal goes high, pin 13 of both E14 and E34 goes

high, placing the Parity Register in the right-shift mode.

The BCC Clock logic (Paragraph 6.6) begins generating

9.5 MHz clock pulses; each pulse shifts the Parity Register. As a bit is shifted out of the Parity Register, it is
shifted into the LSB position of the BCC Register.

After eight clock pulses, for example, the character has been

shifted out of the Parity Register and into the BCC Register.

important signals of the VRC logic.

Figure 6-7 is a timing diagram that includes the

Some of the signals shown have yet to be explained in detail; however, this

diagram is helpful in understanding VRC logic operation.

I/O PAUSE L

RCCV L

"RCGB L

COMPUTE VRC

VRC XFER CNTL

(1!

NOT LAST XFER L

BUS STROBE L

V)l\Jt\

TO AC

CO L,C1 L

CHARACTER FROM AC
DATA 4-11

CHARACTER PLUS PARITY BIT-

PARITY REGISTER 4-11

PARITY REG TO DATA LINES
**9.5

UHLT

MHz CLOCK

*BCC REGISTER BITS
IF

BCC ACCUMULATION FOLLOWS THE VRC.

Figure 6-7

VRC Logic Timing

6-14

VRC (RCGB) flip-flop in the Control Register logic is not set by an RCLC instruction, the COMPUTE VRC
signal cannot be asserted when the RCGB instruction is issued (NAND gate E28 is disabled). Thus, a VRC is not
performed; rather, an LRC or a CRC, alone, is carried out, and the VRC logic is used as the input network for the
see logic. When the RCGB instruction is issued, it causes a character to be placed on the DATA lines. Neither
If the

the LEFT PARITY L signal nor the RIGHT PARITY L signal is asserted; consequently, the character bits on

DATA lines 4-1

(if the character contains eight data bits)

of the Exclusive-OR circuit is ignored by the logic.

are gated to the Parity Register inputs, and the output

As before, the register is parallel-loaded at TP3 time; however,

because the VRC XFER CNTL flip-flop is not set, the register outputs are not gated onto the DATA lines.

When

the RCGB L signal goes high, 9.5 MHz clock pulses begin shifting the Parity Register contents to the BCC Register.

6.6

BCC CLOCK LOGIC

The BCC Clock logic is shown in Figure 6-8. The logic generates clock pulses that shift both the Parity Register
and the BCC Register. Figure 6-9 is a timing diagram that helps explain the logic operation.

(AAAr + 3V

Figure 6-8

BCC Clock Logic

uuuuuu

E43, P12

/WWW

E40, P3

UTRTLrin;

9.5MHZ CLOCK

1
Figure 6-9 9.5 MHz Clock Pulse Generation

6-15

The logic includes a 4-bit binary counter, E2, and a free-running multivibrator, comprising NAND gates E43 and
E40, and the RC network. The binary counter is preset with a count that is determined by the signals at the
parallel inputs.

Figure 6-9 indicates that the 6 BITS L signal has been asserted by the Control Register logic.

Thus, when the RCGB L signal goes low, E2 is preset with a binary count of 0010.
high, the free-running multivibrator is triggered.

When the RCGB L signal goes

The multivibrator output alternately enables and disables AND-

NOR gate E31, thereby producing clock pulses at a frequency of approximately 9.5 MHz. Six clock pulses advance
the binary count in E2 to 1000, at which count the MSB signal is asserted. This signal cuts off the multivibrator

and no more clock pulses are generated.

The RCTC L signal is generated by the lOT Decoder logic when the maintenance test clock instruction, RCTC, is
issued.

If test

point DAI

grounded, the RCTC L signal causes a single pulse to be produced; thus, single-step

testing of the BCC generating logic is possible.

6.7

I/O TRANSFER LOGIC

The I/O Transfer logic is shown in Figure 6-10. The logic asserts OMNIBUS control signals to enable transfers of
data characters and BCCs from the KG8-E to the AC Register.

In addition, the logic is used to assert the

OMNIBUS SKIP L signal when odd parity is detected during a character parity test (RCTV).

NOT LAST XFER L

E25A b

BUS STROBE L

COMPUTE VRC

'"^&^
RCRL
RCRH

L
L

VRC(RCGB)(0)

E44d\>

VRC TESKR CGB) (1

)
1

RCTV L

^:E>

PARITY

SKIP L

Figure 6-10 I/O Transfer Logic

When a VRC is performed on a character transferred from the AC Register (as a result of an RCCV instruction or
an RCGB instruction), the character and the parity bit must be returned to the AC from the Parity Register. In
normal operation, the AC Register is loaded at TP3 time. However, the Parity Register outputs are not gated
onto the DATA lines until TP3 time; consequently, with normal computer timing, the information on the DATA
lines would appear at the

AC Register data inputs too late to be loaded into the register. The I/O Transfer logic

6-16

NOT LAST XFER L signal. This signal prevents the AC Register from being
loaded at TP3 time; instead, the register is loaded when the I/O Transfer logic asserts the BUS STROBE L signal

solves this difficulty by asserting the

(see Volume 1, Section 6, for more details).

The timing diagram of Figure 6-7 demonstrates how the NOT LAST XFER L signal affects the character transfers
from the Parity Register. The NOT LAST XFER L signal is asserted by NAND gate E44B, Figure 6-10, when the

VRC logic asserts the COMPUTE VRC signal. At TP3 time (trailing edge), the VRC XFER CNTL flip-flop is set,
gating the Parity Register outputs onto the DATA lines (see VRC logic) and causing E44B to negate the NOT
LAST XFER L signal. At the same time, both the CO L signal and the CI L signal are asserted, via NOR gate E43,
enabled. The output of E4 rises exponentially until, approximately 200 nanoseconds later,
and NAND gate E4
causes the BUS STROBE L signal to be asserted. Because the CI L and CO L signals are asserted, the BUS
STROBE L signal jam transfers into the AC the information on the DATA lines. The long delay in asserting the
BUS STROBE L signal ensures that the AC Register input lines have settled before the register is clocked.
is

When an LRC or a CRC is performed on a message, the generated BCC must be transferred to the AC Register.
This is accomplished by the RCRL instruction, alone, or by both the RCRL and RCRH instructions. Either

NOR gate E43. The output of this gate enables NAND gates E25C and
D to assert the CI L and CO L signals. The BCC is gated onto the DATA lines and jam transferred into the AC
Register at TP3 time of the RCRL or RCRH instruction (the BUS STROBE L signal is not asserted by the I/O

instruction generates a signal that enables

Transfer logic).

A VRC can be carried out on a character in response to an RCTV instruction; i.e., a parity test is made on the
character. This instruction causes the RCTV L signal to be asserted, thereby enabling NOR gate E28. The
resulting TEST VRC signal enables NAND gate E3 to pull the OMNIBUS SKIP line low, if the PARITY signal is
asserted by the VRC logic. Remember that the PARITY signal, when asserted, indicates that the tested character
either does exhibit correct parity (VRC logic wired for an odd parity check) or does not exhibit correct parity

(VRC logic wired for an even parity check). Therefore, in the case of an odd parity check, the asserted PARITY
signal would cause the program to skip over an error-handling instruction; in the case of an even parity check, the

asserted PARITY signal would cause the program to skip to an error-handling instruction.

Note that the TEST VRC signal also asserts NAND gate E44A, thereby asserting the CO L signal. This action

AC Register being cleared at TP3 time of the RCTV instruction (to be exact, the AC is loaded with
zeros at TP3 time). Because the character is merely tested by the RCTV instruction, it need not be returned to
the AC, as is the case with the RCCV instruction. A similar situation exists when only an LRC or a CRC is performed. Each character is transferred from the AC Register to contribute to the BCC generation. The character
need not be returned to the AC. Consequently, the RCGB L signal causes NAND gate E44D to be enabled,
thereby asserting the CO L signal (remember that the VRC (RCGB) flip-flop is set only if a VRC is to be initiated
results in the

by the RCGB instruction).

6.8

BCC LOGIC

A block diagram of the BCC logic is shown in Figure 6-11. The logic is used to generate a BCC for either an LRC
or a CRC.

Each character that contributes to the BCC accumulation is parallel-loaded into the 8-bit Parity

lOT instruction. The character is then shifted from the Parity Register into

the 16-bit BCC Register by 9.5 MHz clock pulses.

The accumulation is held in the BCC Register until either an

RCRL or an RCRH lOT instruction is issued.
Each bit of the character in the Parity Register is Exclusive-ORed with the bit in the LSB position of the BCC

The result is placed on the SERIAL QUOTIENT line and shifted into the BCC Register. The particular
bit position into which the SERIAL QUOTI ENT signal is shifted depends on the state of the control signals
Register.

6-17

shown in the bottom of the figure. The LRC/CRC (0) signal manipulates the register for an LRC or a CRC, while
the X BITS L signal produces the correct gating configuration for the bit length of the characters.

DATA Q-11 L

RCRL L

GATING
T

——

1—nr

?~~*

——
I

——
?

r
LSB

)Y>ir
CO

PARITY

C2 C3
E18

——

—I

CLOCK

C4 C5 C6 C7
E38

C8 C9 CIO C1

E42

i~rTT

BCC REGISTER

DATA 4-11 L

C12C13C14C15

E22

CRC PARALLEL INPUTS

LRC/CRC

6 BITS L

Figure 6-1 1

^
7 BITS L

f
8 BITS L

p—

-^
•-

GATING FOR BCC REGISTER CONTROL

SERIAL QUOTIENT

SHIFT RIGHT/PARALLEL LOAD

12 BITS L

16 BITS L

LRC/CRC (0)

BCC Logic, Block Diagram

Consider an LRC parity check, which can be carried out on 6-, 7-, 8-, 12-, and 16-bit characters. The BCC is

accumulated in the BCC Register with the LSB right-justified. Therefore, a number of left-most bit positions in
the BCC Register must be ignored when a BCC of less than 16 characters is accumulated.
left-most bit positions (C0-C7 in Figure 6-11)

For example, the 8

must be disregarded when an 8-bit BCC is accumulated. This con-

figuration is illustrated in Figure 6-12, a logic-block diagram that also shows the configuration for 6- and 7-bit
characters.

When the character is parallel-loaded into the Parity Register, the LSB of the character is Exclusive-ORed with the
bit intheC15 position (E42).

The result is placed on the SERIAL QUOTIENT line. The first clock pulse of the

burst (see the VRC logic and the BCC clock logic) shifts the SERIAL QUOTIENT bit into either the C8, C9, or

CIO position of E22, while at the same time shifting the next character bit into the LSB position of the Parity
Register.

Assume that the data character loaded into the Parity Register is 6 bits in length. The 6 BITS L signal and the

CRC/LRC (0) signal are asserted by the Control Register logic (consequently, the 16 BITS L signal is negated).
Therefore, each SERIAL QUOTIENT bit is shifted into the CIO position of the BCC Register and shifted right

by each succeeding clock pulse (note that although E22 is in the parallel-load mode, a right-shift operation is
carried out because of the IC's external wiring). After six clock pulses, the character has been shifted out of the
Parity Register.

Each bit of the character has been Exclusive-ORed and shifted into the 6 most significant bit

positions of the BCC Register.

Each character of the message is handled in the same way.

has been operated on, the BCC has been accumulated.

When the last character

The RCRL instruction can then be issued, causing the

character to be gated to the AC Register via DATA lines 4 through 1 1, as shown.

If the last character of the

sage is a BCC accumulated by a transmitting station, the final content of the BCC Register is 0, if no errors

occurred.

6-18

mes-

DATA 4-11 L

_A_

)E>n

PARITY
REGISTER
E14, E34

C4 C5 C6 C7

E38

E18

fTTTTTTT
4-11
DATA

SERIAL
QUOTIENT
BITS L
7 BITS L
6 BITS L

NOTES:
1.

E22 and E42

CRC/LRC (0) signal

right-shift
is

mode when pin 13

high for

high.

LRC.

—
BITS L

—

CRC/LRC(0)
BE -0493

Figure 6-12

6-, 7-,

and 8-Bit LRC BCC Accumulation

Figure 6-13 shows the actual logic involved in the 6-bit LRC BCC accumulation.

Note that many connections

shown have been left off the logic block diagram of Figure 6-12. One should study Figure 6-13 thoroughly to
pick up fine points not illustrated in the logic block diagram.

Refer to engineering drawing no. E-CS-M884-0-1 for

the complete logic presentation.

An LRC can be used to accumulate a 12-bit or 16-bit BCC, also. The BCC Register configuration in each case is
shown in Figure 6-14. Consider the 12-bit BCC first.
To accumulate such a BCC, the 12 BITS L signal and the CRC/LRC (0) signal are asserted by the Control Register
logic. Therefore, ICs E18 and E42 are placed in the right-shift mode, while E22 is in the parallel-load mode.
IC E38 is wired so that it is always in the right-shift mode.

input line of E22.
is

The output of E38, the C7 bit, is applied to the serial

However, E22 is in the parallel-load mode and ignores the output of E38. Instead, the C3 bit

gated to pin 10 of E22, the parallel-load input of the C8 bit. Thus, the 12 register bits used for the 12-bit BCC

areC0-C3and C8-C15.
To fill these 12 register bits, a 12-bit character must be transferred from the PDP-8/E memory. Because the Parity
Register can accommodate only 8 bits, one must use the following technique:
a.

The 12-bit character is brought from memory and loaded into the AC Register by a TAD instruction.
The RCGB instruction is issued, causing the character to be gated via the DATA lines to the Parity
Register. At TP3 time, the 8 least significant bits are loaded into the Parity Register (bit 1 1 of the
character is loaded into the LSB position). The AC Register is cleared (see the I/O XFER logic).
The BCC Clock logic generates a burst of 6 clock pulses, shifting the 6 least significant bits of the
character into the 6 most significant bit positions of the BCC Register (C0-C3, C8, C9).
While the registers are being shifted, another TAD instruction loads the same character into the AC
Register.

(continued on next page)

6-19

A BSW instruction (swap bytes in AC) is issued, causing the 6 most significant bits of the character to
be placed in the 6 least significant bit positions of the AC (the MSB of the character goes to AC bit 6).
Another RCGB instruction is issued.
of the character; bit
is

Now the Parity Register is loaded with the 6 most significant bits
The AC Register

of the character is loaded into the Parity Register LSB position.

cleared.

Six clock pulses shift the 6 most significant bits of the character into the BCC Register and shift the 6
least significant bits of the character to the right.

The 12-bit character is now contained in the 12-bit BCC Register. Each succeeding character is handled
in the same way.

When the BCC has been accumulated, the RCRL instruction causes the character to be gated to the AC Register.
The 4 most significant bits are gated via DATA lines

through 3, as shown.

If the last character of the

message is

a BCC accumulated by a transmitting station, the final content of the BCC Register is 0, providing no errors

occurred in transmission.

When a 16-bit BCC is accumulated, all 16-bit positions of the BCC Register are used, and each IC is placed in the
right-shift mode, as Figure 6-14 illustrates.

Because the PDP-8/E cannot store an entire 16-bit character in one

memory location, two locations are required. The 8 most significant bits of the character are stored in location
"A", in a right-justified format, while the 8 least significant bits of the character are stored in location "B", also
in right-justified format.

A TAD instruction brings the contents of location B to the AC Register first. An RCGB

instruction transfers the 8 least significant bits to the Parity Register; clock pulses then shift the bits into the

8 most significant bit positions of the BCC Register. Another TAD instruction brings the contents of location A
to the AC.

A second RCGB instruction results in the 8 most significant bits of the character being shifted into the

8 most significant bit positions of the BCC Register. At the same time, the 8 least significant bits of the character
are right-justified into the 8 least significant bit positions.

As Figure 6-14 indicates, the 8 least significant bits of

the BCC are transferred to the AC Register via DATA lines 4 through 1 1 by the RCRL instruction, while the 8

most significant bits are transferred by the RCRH instruction.

The BCC accumulation during a CRC parity check is basically the same as during an LRC: the message characters
are parallel-loaded into the Parity Register; the bits in the LSB positions are Exclusive-ORed; the result is placed

on the SERIAL QUOTIENT line and shifted into the BCC Register. However, to implement the generating
polynomial, P (X), additional Exclusive-ORing is carried out, as illustrated in Figure 6-15.

The logic block diagrams shown in Figure 6-15 illustrate Exclusive-OR gating for both CRC-12 and CRC-16. The
gating enables the logic to implement the two generating polynomials.

For industry-compatible application,

CRC-12 is used with 6-bit characters, while CRC-16 is used with 8-bit characters. CRC-12 could be used to generate the BCC of a message consisting of 12-bit characters, but this would require the same sort of program manipulation as described for LRC-12.

The same can be said when considering CRC-16 with 16-bit characters. Because

the CRC logic is so similar to the LRC-12 and LRC-16 logic, no further logic description is presented.

SECTIONS MAINTENANCE
See Volume 1 for maintenance information that can be applied to the KG8-E option. The diagnostic program

and the single-step test feature should be used to isolate problems that are traced to the KG8-E.

6-20

a
00
CO

o
DC

o
o
00

ET3

OHX
-J

6-21

DATA 4-11 L

DATA 0-3 L

GATING

—

SER QUOT

)E>i
LSB

PARITY
REGISTER

E38
10

-X
+ 3V

DATA 4-11 L

L—KdP>

LRC-12

:ti

E42

^
1

tr-1
L CI2 013 CI4 CI5

Ij C8

C4 C5 C6 C7

C2 C3
E18

+ 3V

16BITS L--dJ>—

CRC/LRC(0)

DATA 4-11 L

DATA 4-11 L
1

GATING
11

C2 C3

i~~?

—

SER QUOT

)E>J
LSB

LSB

C8 C9 CIO CM

CI2 CI3 CI4CI5

E42

E22

E38

E18

PARITY

C4 C5 C6 C7

^L
+ 3V

DATA 4-11 L

+ 3V

CLOCK
CRC/LRC(0)
NOTES:
1

E18,E38,E22,E42 in right -shift mode when pin 131s high.
CRC/LRC(0) signal is high for LRC.
16 BITS L

LRC-16

Figure 6-14 Logic Block Diagram: LRC-12, LRC-16

SECTION 6 SPARE PARTS
Table 6-2 lists recommended spare parts for the KG8-E. These spare parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.

6-22

•^

r
in

So,

;0 tij

z
H
<
10
1

o ^
o
O OJ

o
cc
o

H
m

o
o

>
ro

o
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<j
to
to

inHJ

III

S
Z

2 Hi'

u
o

<
C35

o
J

o
^ CD
~)

o
L

>
+

o
(T O
a:

u
—

_i
'

<
<

6-23

Table 6-2

KG8-E Recommended Spare Parts

DEC Part Number

Description

19-09704

IC DEC 314

19-09485

IC DEC 380

19-05575

IC DEC 7400

19-09004

IC DEC 7402

19-09686

IC DEC 7404

19-05576

IC DEC 7410

19-05580

IC DEC 7450

19-05547

IC DEC 7474

19-10011

IC DEC 7486

Quantity

19-09594

IC DEC 8251

19-09615
19-09705
19-10035

IC DEC 8271

IC DEC 8881

10-00016

Capacitor, 100 pF, 100V, 5%

10-01610
10-00027

Capacitor, 0.01 /xF, 100V, 20%, DISC

13-00293
13-01401
13-00271

IC DEC 74197

Capacitor, 820 pF, 100V, 5%
Resistor, 330n,

1/4W, 10%

Resistor, 750^,

1/4W, 5%

Resistor, 220^,

1/4W, 5%

6-24

PART 6

CARD READERS

CHAPTER 7
CM8-E/CR8-E CARD READERS

SECTION 1

INTRODUCTION

Two card reader options are available for use with the PDP-8/E. Both transfer data from ElA-standard data cards
to the CPU AC Register. The CM8-E Optical Mark Card Reader option reads data from pencil-marked or punched
hole data cards; the CR8-E Card Reader option reads only from punched-hole cards. Each option uses the same
control module to interface the card reader and the computer. This module, DEC M843, plugs into the OMNIBUS

and connects to the external card reader via a signal cable that is supplied with the option.

The card reader used with the CM8-E option is the GDI Model 100-M Optical Mark Reader. That used with the
CR8-E option is the Documation Model M200 Card Reader. These card readers are discussed only to the extent
necessary both to fully describe the control operation and to present supplementary information concerning installation and checkout of the option.

Details of the installation, operation, troubleshooting, and maintenance

of the card reader, itself, can be found in the respective technical manual. Other publications and documents
relevant to the CM8-E and CR8-E are:

PDP-8/E & PDP-8/M Small Computer Handbook - D EC 1 972
PDP-8/E Maintenance Manual, Volume 1
CM8-E Diagnostic, MAINDEC-8E-D2DA, CR8-E Diagnostic, MAINDEC-8E-D2EA

DEC Engineering Drawing, Card Reader Control, E-CS-M843-0-1.

SECTION 2 INSTALLATION
The CR8-E/CM8-E Card Reader option is installed on site by DEC Field Service personnel. The customer should
not attempt to unpack, install, checkout, or service the equipment.
Insert the option control

module (DEC M843) into the PDP-8/E OMNIBUS. Refer to Table 2-3, Volume 1, for

information concerning recommended module priorities (the CR8-E/CM8-E is a "non-memory" option).

Connect the control to the card reader with the signal cable provided. J1 of the control connects either to J2
(CR8-E) or to J5 (CM8-E) of the card reader. See Section 5 for cable and connector pin assignments.

The CR8-E/CM8-E option can be checked for correct operation by running the appropriate diagnostic program.
Re;fer to the respective card reader instruction manual for card reader checkout procedures.

7-1

SECTION 3 BLOCK DIAGRAM DESCRIPTION
Figure 7-1

is a

block diagram of the CR8-E/CM8-E Control.

neering drawing E-CS-M843-0-1.

OMNIBUS pin numbers can be found on DEC engi-

The pin assignments for connector receptacle J 1 are given in Table 7-4.

INTERNAL I/O L
CI

CARD DONE (1)

SELECT

lOT

I/O PAUSE L

MD 3-11 L

DECODER

CARD

LOGIC

lOT 6631,6632

6634-6637
6671,6672
6674,6675

READ ^1

READY/ON-LINE

6677
SKIP L
INT RQST L

6631,6635
6671,6672,6675

INT/SKIP
LOGIC

m.,
DATA

0,1,2,3 L

6677
6637

DATA 0-11 L
DATA 6-11 L

STATUS
LOGIC

DATA 0,4-11 L

6632
6634
6636

— TU

DATA
GATING
LOGIC

"T"

ZONE 12,11,0-9

READ
DATA

DATA READY (1)

LOGIC

INDEX MARKER/ DATA STROBE
ZONE INPUTS 12,11,0-9

Figure 7-1

CR8-E/CM8-E Control Block Diagram

The signals shown on the block diagram are related in the timing diagram. Figure 7-2. The lOT instructions are
listed in Table 7-1 (the same instruction set is used by both the CR8-E and the CM8-E; thus, the two card readers
cannot be used in the same system). Refer to Figures 7-1 and 7-2 and Table 7-1 while reading the block diagram
description.

The card reader asserts the signal READY/ON LINE when the reader is clear of errors and ready to receive a card
read command. When the 6672 instruction is issued, the control's lOT decoder logic asserts the 6672 L signal.
At TP3 time, the select card logic asserts the READ signal that initiates the card pick cycle in the card reader.
A card is brought into the reader card track and advanced toward the read station. The CI R signal is asserted by
the reader when the card has arrived at the read station.

The card columns pass sequentially before the read station sensors beginning with column 1 (note that an 80column card is illustrated in the timing diagram; this applies only to the CR8-E, the CM8-E being limited to use
with 40-column cards). The information in the 12 data rows of the column is transferred, via the Zone Input

The reader generates an INDEX MARKER/DATA
STROBE signal for each card column; this signal clocks the information on the Zone Input lines into the Zone
lines, to the 12-bit Zone

At the same time, INDEX MARKER STROBE causes the read data logic to assert the DATA READY (1]

signal.

7-2

C
o

o
LU
00

2S
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o
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00
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00 oo

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7-3

Table 7-1

CM8-E/CR8-E Instruction List
Octal Code

Mnemonic

6631

RCSF

Function
Skip on the Data Ready flag. Senses tiie state of the DATA

READY flip-flop. If the flip-flop
is

is set, the program counter
incremented so that the next sequential instruction is

skipped.

6632

RCRA

Read alphanumeric. Causes a 6-bit alphanumeric code, which
from the 12-bit code of a card column, to be gated
to AC bits 6-11. Clears the DATA READY flip-flop.
is translated

6634

RCRB

Read binary. Causes the 12-bit code of a card column to be
gated to AC bits 0-1 1 (column rows 12, 11, and

are gated to

ACO, 1, and 2, respectively; rows 1—9 are gated to AC3— 1 1,
respectively).

6635

RCNO

Clears the

DATA READY flip-flop.

Read conditions out to card reader. Selectively sets or clears
two flip-flops that control the INT/skip logic. If AC11 is logic

RCNO instruction sets the DATA AND CARD INT flipDATA READY flip-flop and the
CARD DONE flip-flop to cause a program interrupt and an
instruction skip. If AC10 is logic 1, the RCNO instruction
sets the RDY/TROUBLE INT flip-flop, thereby enabling a
transition in the READY/ON LINE signal to cause a program
1, the

flop, thereby enabling the

interrupt and an instruction skip.

6636

RCRC

Read compressed. Causes an 8-bit code, which is translated
from the 12-bit code of a card column, to be gated to AC bits
4—11. Gates a logic 1 into AC bit 0, if a hardware validitycheck circuit has detected more than one hole or mark in

rows 1-7 of a card column. Clears the DATA READY flipflop.

6637

RCNI

Read conditions in from card reader. Causes the state of the

DATA READY flip-flop and the state of the CARD DONE
flip-flop to be placed on DATA lines
and 1, respectively.
Causes the transition of the READY/ON LINE signal to be
represented by DATA bits 2 and 3. If the signal has gone
high, the DATA 3 L signal is asserted, while the DATA 2 L
signal
negated; if the signal has gone low, the DATA 3 L
signal is negated, while the DATA 2 L signal is asserted.
is

6671

RCSD

Skip on Card Done flag. Senses the state of the CARD DONE
If the flip-flop is set, the program counter is incremented so that the next sequential instruction is skipped.

flip-flop.

6672

RCSE

Select card and skip if ready.

If the

card reader has asserted

the READY/ON LINE signal, the program counter is incre-

mented so that the next sequential instruction is skipped; a
card is started toward the read station. Clears the CARD

DONE flip-flop.

(continued on next page)

7-4

Table 7-1 (Cont)

CM8-E/CR8-E Instruction List
Octal Code

Mnemonic

6674

RCRD

Clear Card Done flag. Clears the

6675

RCSI

Skip if interrupt being generated.

Function

CARD DONE flip-flop.
If

any one of four conditions

has caused a program interrupt, the program counter is incre-

mented so that the next sequential instruction is skipped.

RCTF

6677

Clear Transition flag. Clear the TRANSITION flip-flop in the
status logic.

If the control is

programmed to operate in the interrupt mode, as the timing diagram illustrates, DATA R EADY

causes the INT/skip logic to assert the OMNIBUS INT RQST L signal.
interrupt servicing routine.

(

The computer then begins to execute the

When the appropriate instruction (6631 in this example) in the servicing routine is

decoded, the INT/skip logic asserts the OMNIBUS SKIP L signal. The computer proceeds to an appropriate subroutine to transfer the data from the read data logic to the OMNIBUS DATA lines, via the data gating logic.

The

6634 instruction is used in the present example to transfer the data; this instruction is decoded and the resulting
signal, 6634 L, gates the data through the data gating logic to the

DATA 0—1

lines.

mation is loaded into the AC Register and the DATA READY (1) signal is negated.

At TP3 time, the infor-

When the data from all

columns has been transferred, the CI R signal is negated and the select card logic asserts the CARD DONE (1)
signal.
is

This signal asserts the INT RQST L signal, the card pick subroutine is entered, and a new 6672 instruction

decoded.

The control status logic allows the program to check the status of the DATA READY (1) signal, the CARD

DONE (1) signal, and the READY/ON LINE signal. The significance of this status logic is explained in detail in
F'aragraph 7.5.

SECTION 4 DETAILED LOGIC
7.1

lOT DECODER LOGIC

The lOT decoder logic is shown in Figure 7-3.
signals 667X, and 663X, respectively.

Bits

MD3— 8 are decoded by NAND gates E12 and E16 to produce

Each of these signals causes the OMNIBUS INTERNAL I/O L signal to be

asserted, ensuring that the positive I/O bus interface ignores the lOT instruction.

Also, each signal is gated with

MD 9, 10, and
in decoder E3 to produce the lOT signals shown. The inverted 663X signal, likewise,
gated with bits MD 9, 10, and 11, but in decoder E2. This decoder produces the six lOT signals shown, four of
bits

1 1

which cause the OMNIBUS CI L signal to be asserted. When the CI L signal is asserted, information placed on
the DATA lines is gated through the CPU Major Register Gating and ORed into the AC Register (a jam transfer is

unnecessary because a card reader program always clears the AC Register before data is transferred from the card
reader control).

7-5

]

in
f-

rr-

;: cj

(S>

(—

T-

if)

10
U)

(0 10
(O lO

to
to

^0
ID

o
o

A r\ r^ r\

'05

fTTTf

/^
—n—n—n— —n—rj—
rj

Q
S

Q
hO
CO

CD
t_

-n

—n— —n— —n n
CJ

^r~^

^ in
Q Q
S 2

7-6

7.2

SELECT CARD LOGIC

The select card logic is shown in Figure 7-4. When the 6672 lOT instruction is decoded, the lOT decoder logic
If the card reader
ready, the signal at pin J1J, READY or ON LINE,
high and
NAND gate E20 asserts OMNIBUS SKIP L The two E40 NAND gates at the READY/ON LINE input comprise

generates the RCSE L signal.

a Schmitt trigger that prevents noise on the input line fronn triggering the select card logic (a Schmitt trigger is

placed in the J 1 N input for the same reason)

At TP3 time of the 6672 instruction NAND gates E24 and E27 are enabled. Thus, the CARD DONE flip-flop is
cleared and the READ flip-flop is set, the latter flip-flop causing NOR gate E39 to assert the READ signal. This

When the card is in the read station, the signal at
pin JIN, CIR (Card In Reader), goes high, clearing the Read flip-flop. When the card has been processed the CIR

signal causes the card reader to begin processing the data card.

signal

negated.

The negative-going edge of the signal sets the CARD DONE flip-flop.

Note that both the CARD DONE flip-flop and the READ flip-flop are cleared by the OMNIBUS INITIALIZE
signal via

NOR gate E29. The CARD DONE flip-flop, in addition to being cleared by this signal and by the RCSE
RCRD instruction (Clear Card Done flag). Normally, the CARD DONE flip-flop

instruction, can be cleared by the

generates an interrupt request when it is set; the result of the program interrupt is a re-issue of the RCSE instruction.

Thus, another card is fed into the read station and processed. However, the programmer might wish to halt

the reading operation when a particular card has been processed. Such a halt can be carried out easily by a subroutine; but, the subroutine must issue the RCRD instruction so as to clear the

CARD DONE flip-flop and

remove the ground signal from the OMNIBUS INT RQST line.

The READ flip-flop can also be cleared by a signal other than INITIALIZE. This other signal is taken from the
JIJ input Schmitt trigger, as Figure 7-4 illustrates. Thus, when the READY/ON LINE signal goes low, the READ
flip-flop is cleared, negating the

READ signal. This action prevents an uncontrolled start of the card reading

operation when the reader is manually re-started following a trouble condition.

7.3

READ DATA LOGIC

As each card column passes the read array in the card reader, 12 data row bit signals and one INDEX MARKER/

DATA STROBE signal can be generated (a data row bit signal

generated if a hole/optical mark is present in a

data row).

The data row bit signals are transferred to the Zone Register in the read data logic, as illustrated in

Figure 7-5.

Each bit is applied to the data (D) input of the corresponding Zone Register flip-flop; i.e., the Data

Row 12 bit applied to the ZONE 12 flip-flop, the Data Row bit applied to the Zone flip-flop. The INDEX
MARKER/DATA STROBE signal also transferred to the read data logic. However, before
applied to the
is

it is

clock (C) input of the Zone Register flip-flops, it is delayed for approximately 2 jus by a network that includes
the one-shot multivibrators E32 and E45. This network ensures that the D-input lines of the Zone Register flipflops have settled before the flip-flops are clocked by the INDEX

MARKER/DATA STROBE signal. This pre-

caution must be taken because some card readers do not provide a sufficient amount of time between generation
of the Data Row bit signals and the INDEX

MARKER/DATA STROBE signal (those listed in Section

vide sufficient time; see the various card reader instruction manuals for clarification).

7-7

do pro-

a
CO

7-8

L_
READ GATING
FIG'S

4-7,4-8,4-9

E10
ZONE 12
1

J
LL
(DATA ROW 9)

BB
(DATA ROW 12)

STROBE /MARKER

JU-ODATA STROBE
{CM8/E)
INDEX MARKER
(CR8/E)

Figure 7-5

Read Data Logic

The INDEX MARKER/DATA STROBE signal clocks not only the Zone Register flip-flops, but also the DATA

READY flip-flop. Thus, when the data from a card column
(1) signal

is asserted.

loaded into the Zone Register, the DATA READY

The state of this signal can be tested by a program instruction or by using the interrupt

In either case, the program then enters a subroutine that contains one of the read instructions, RCRA,
RCRB, or RCRC. As illustrated in Figure 7-5, these instructions generate signals that cause the data in the Zone

mode.

DATA lines. At TP3 time of the instruction

the DATA READY flip-flop is cleared and the procedure is repeated for the next card column of data.

7.4

INTERRUPT/SKIP LOGIC

Four conditions in the Card Reader option can cause a program interrupt; viz., the data from a card column is
ready to be placed on the DATA lines, all columns of the present card have been read, the READY/ON LINE
signal has gone high, the

READY/ON LINE signal has gone low. The first two conditions are represented,
DATA READY flip-flop and of the CARD DONE flip-flop; the last two con-

respectively, by the set state of the

ditions are represented by the set state of the TRANSITION flip-flop.

These three flip-flops are illustrated in

Figure 7-6.

Also shown in Figure 7-6 are two interrupt control flip-flops, identified as DATA AND CARD INT and RDY/
TROUBLE INT. These two flip-flops are set under program control and enable the three condition flip-flops to
assert the OMNIBUS INT RQST L and SKIP L signals. Specifically, consider the DATA AND CARD INT flipflop, E23A. This flip-flop can be set at TP3 time of the RCNO instruction, if the AC1
bit is logic
(this flip-flop
1

is set

by the INITIALIZE signal for program compatibility with other PDP-8 family computers; if the programmer

does not want the set state, he must clear the flip-flop by programming the RCNO instruction with a logic
in
theACn bit). The 1-output of E23A is applied to two NAND gates, E15, and an AND/NOR gate, E19. The E15
gates enable the CARD DONE flip-flop and the DATA READY flip-flop to assert the INT RQST L signal. Gate

E19 enables the sarne two flip-flops to assert the SKIP L signal when an RCSI instruction is issued. The RDY/

TROUBLE INT flip-flop, E23B, operates like E23A. It, too, is under program control of the RCNO instruction;

7-9

however, AC bit 10 determines if the flip-flop is set or cleared (note that this flip-flop is cleared, rather than set,

by the INITIALIZE signal).

Its

1-output is also applied to gates E15 and E19; however, in this case, E15 and

E19 are enabled by the TRANSITION flip-flop rather than by the DATA READY or CARD DONE flip-flops.
As with many other PDP-8/E options, the Card Reader option can engage in a programmed I/O transfer of data or
it

can operate in the more efficient interrupt mode of data transfer.

If the

interrupt control flip-flops, E23A and

E23B, are not set, a background program must execute a loop that tests for a desired condition. For example,
the program can repeatedly test the DATA READY flip-flop with the RCSF instruction.
set the RCSF

When the flip-flop is

L signal causes NAND gate E20 to assert the SKIP L signal. The program then proceeds to an

appropriate subroutine. The same method can be used to test the CARD DONE flip-flop with the RCSD instruction, and to test the
If the
is

READY/ON LINE signal with the RCSE instruction.

programmer wishes to use the interrupt mode, he can proceed in a number of ways. For example, if E23A

set, the

DATA READY flip-flop, when set, causes NAND gate E15 to assert the INT RQST L signal. The pro-

gram executes the interrupt servicing routine; the RCSF instruction in the routine results in a jump to the appro-

The same method can be used for the CARD DONE flip-flop. However, note that the
READY/ON LINE signal does not directly cause an interrupt request. Rather, the TRANSITION flip-flop, which
reflects the state of the READY/ON LINE signal, is used to assert the INT RQST L signal. Thus, if E23B is set,
the TRANSITION flip-flop, when set in response to a transition of the READY/ON LINE signal, causes NAND
gate El 5 to assert the INT RQST L signal; the appropriate subroutine is ultimately carried out.
priate subroutine.

Perhaps the most efficient way of using the interrupt capability of the Card Reader option is that which tests all
the interrupt flip-flops simultaneously with the RCSI instruction.
gate E19 is enabled when any of the interrupt flip-flops is set.

routine causes

If both

E23A and E23B are set, AND/NOR

The RCSI instruction in the interrupt servicing

NAND gate E20 to assert the SKIP L signal. A card reader routine

then entered and the specific

reason for the interrupt request must be determined. This determination involves testing with the skip instructions, which is a satisfactory method in the case of the

CARD DONE and DATA READY flip-flops. However,

when the TRANSITION flip-flop has caused an interrupt request another method is necessary. Because the flipflop is set by a transition of the READY/ON

LINE signal, the program must also determine if the signal went

from low to high or vice-versa. The RCSE instruction could determine a low to high transition by causing an
instruction skip via

NAND gate E20; however, the opposite transition could be detected only if the absence of

such a skip caused an error routine to be entered. Another method of making the transition determination is provided by the status logic, shown in Figure 7-7 and discussed in the following paragraphs.

7.5

STATUS LOGIC

As detailed in Paragraph 7.4, any of four conditions can cause a card reader interrupt request.
involve the READY/ON

Two conditions

LINE signal; the status logic has been devised, primarily, to deal effectively with these

two conditions. The READY/ON LINE signal is applied to the Schmitt trigger, E40 (Figure 7-7). The Schmitt
trigger provides an input signal for

NAND gate E5D and for a delay network consisting of inverter E8, delay line

DL1, and AND/NOR gate E19. The delay network gates the Schmitt trigger output in such a way that gate E19
is

enabled when the READY/ON LINE signal undergoes a transition. Figure 7 8 is a timing diagram illustrating

how the output is obtained.

7-10

AA^

_J
Q.

QQ
CD
cu

rr\

f^KM

'^H'

7-11

n
I

JIJ

READY
(CR8/E)
ON LINE

E40 )

--T

~{T^?)>5^™^

(CM8/E)

DATA 2 L

( 30ns")^

J^?)>^^^IMi:

DATA OL

E36

E7
TRANSITION

CARD DONE

DATA READY

RCTF LEl

—

-r

Ell

Elt

'""^E>-^
RCNI L-

Figure 7-7 Status Logic

E40,P.13

E8,P.8

DL1,P.3

E8,P.6

^'r

Figure 7-8 Timing, Transition Network

When a change in the READY/ON LINE signal occurs, the output from E19 sets the

TRANSITION flip-flop, E7.

The 0-output of E7 is one input of NAND gate E35. The other input of E35 is
asserted when the RCNI instruction is issued. When E35 is enabled, NAND gate E5C or E5D
is enabled, depending on the direction
of the

READY/ON LINE signal transition. For example, if the READY/ON LINE signal has gone from low to
high,
E5D asserts the DATA 3 L signal when the RCNI L signal enables E35. Note that the RCNI
L signal also enables

NAND gate El. This gate, in turn, can enable gates E5A and/or EBB, depending on the state of the CARD
DONE
DATA READY flip-flop. Thus, a signal representing the status of each of the card reader

flip-flop and the

7-12

conditions can be placed on a DATA line by the RCNI instruction.

The DATA line information is then gated to

the AC Register and loaded at TP3 time. Although the status logic is more sensibly applied in the interrupt mode,
READY flipit could be used to advantage in the programmed I/O transfer mode, particularly when the DATA
flop is considered. For example, the program could concern itself with a task, periodically issuing a RCNI instruction, followed by a

SMA Operate microinstruction. If the DATA READY flip-flop were set, the ACO bit would

become logic 1 at TP3 time of the RCNI instruction. This is defined as a "minus AC"; thus, a program instruction
would be skipped and a subroutine could be entered. This procedure could conceivably be extended to the other
three DATA bits (1,2, and 3) by making use of the rotate microinstructions.

The status logic is more efficient when used in the interrupt mode. The program can be interrupted when one of
the card reader conditions becomes true.

The RCSI instruction can then direct the program to a card reader

routine that checks each bit of the status word with the rotate microinstructions. This method is particularly
effective in monitoring the state of the

7.6

READY/ON LINE signal.

READ GATING LOGIC

The read gating logic is illustrated in Figures 7-9, 7-10, and 7-11. Each figure shows the logic for one of the three
read instructions, RCRA, RCRB, and RCRC.

The simplest form of reading is that which is accomplished by the RCRB instruction. Read Binary. This logic is

shown in Figure 7-9. The RCRB L signal gates the Zone Register bits through the 12 NAND gates to the DATA
lines; the bit-for-bit correspondence is as indicated.

The DATA bits are gated to the AC Register and loaded at

TP3 time.

A more complex form of reading is that which is accomplished by the RCRA instruction. Read Alphanumeric.
This form of reading converts the code represented by the holes or marks of each card column to a 6-bit alpha-

numeric code. The alphanumeric code is gated onto DATA lines 6 through 1 1 by the RCRA L signal (Figure 7-10)

and loaded into the AC Register at TP3 time.

The data card can be punched or pencil-marked to represent any code desired by the user. However, the most
common code in use, particularly with punched cards, is the Hollerith code. The 47 characters of the Hollerith
code can be converted easily to the 6-bit alphanumeric code, thereby minimizing the size of translation tables.
Table 7-2 shows the relationship between the Hollerith code and the alphanumeric code carried by the DATA
lines.

Each character of the topmost group, numerals 1 through 9, is translated into an alphanumeric code as

follows:

The numeral is represented in BCD code in the four least-significant DATA bits; the two most significant

DATA bits are logic 0. The next three groups of characters are translated in a similar manner; the BCD code for
numerals through 9 is repeated (the fourth group repeats 2 through 9) in each group, but DATA bits 6 and 7 are
1

changed. The last group is translated with less extensive but still noticeable similarities.

The third form of reading, RCRC (Read Compressed), is accomplished by the logic shown in Figure 7-11. This
form of reading is designed to handle a proposed expansion of the Hollerith code. The expanded Hollerith code
is

converted to a 9-bit compressed code that features a validity-check bit. The 9-bit compressed code is gated onto

DATA lines

and 4 through 1 1 by the RCRC L signal and loaded into the AC Register at TP3 time.

Table 7-3 shows the relationship between the Hollerith code (excluding whatever characters may be added as a
result of expansion) and the compressed code.

Note that DATA bit

always logic 0. This bit is the validity-

check bit. Only one of rows 1 through 7 in a card column can contain a hole or mark.

punched or marked, an error exists and the DATA
by the program, for instance, with a

more than one row is

bit becomes logic 1. This error condition could be checked

SMA Operate microinstruction.

7-13

ZONE 9

(i:

DATA 11 L

D"
ZONE 8(1)

- DATA 10 L

E33

ZONE 7(1)
DATA 9 L

ZONE 6(1)
E37

ZONE 5(1)

ZONE 4(1)

ZONE 3

)

DATA

5 L

DATA

2 L

DATA

ZONE 2(1)

ZONE 1(1)

ZONE 0(1)
-

ZONE 11

)

E9
ZONE 12

jO-

(i:

RCRB
(6634) L

Figure 7-9 Data Gating, RCRB Instruction

DATA bits 4 through

1 1

represent the Hollerith code characters in compressed! code.

Each character of the top-

most group, numerals 1 through 9, is translated into compressed code as follov/s: numerals 1 through 8 are
represented in BCD code in the four least-significant DATA bits (all other bits are logic 0); numeral 9 is repre-

sented by logic 1

DATA bit 4. The next three groups of characters are translated in a similar manner; the code
DATA bits 5, 6,

for numerals 1 through 9 is repeated (the fourth group repeats 2 through 9) in each group, but

and 7 are changed. The last group is translated with less extensive but still noticeable similarities.

7-14

ZONE 7 (0)
ZONE 5 (0)
ZONE 3 (0)
ZONE (0)-

E3^X>-

ZONE 9

E41

V-

E41

(0)

ZONE 7 (0)ZONE 6 (0)ZONE 3 (O)ZONE 2 (0)ZONE 7 (0)ZONE 6(0)-

ZONE 5 (0)ZONE 4 (0)ZONE 9 (0)-

E42
ZONE 8 (0)
ZONE

(0)-

Z0NE12 (0)-

E21

ZONE 11 (0)-

ZONE 12 (0)-

RCRA (6632)

Figure 7-10 Data Gating, RCRA Instruction

DATA 11 L

ZONE
ZONE 3(0)
ZONE 5 (0)

(0)

E37

=^I!L>

ZONE 7 (0)

DATA 9 L

ZONE 8 (1)

ZONE 2 (0)
ZONE

(1)

DATA 7 L

ZONE 7 (0)

ZONE 11

(1)

DATA 6 L
ZONE 4 (0)
ZONE 5 (0) —
ZONE 6 (0)

ZONE 12 (1)
^'

ZONE (0)
ZONE 2 (0)
ZONE 3 (0)
1

E26

E30

ZONE 7 (0)
(0)ZONE
ZONE 4 (0)
ZONE 5 (0)

ZONE 9

(1)

~~^—^^

ZONE 2 (0)
ZONE 4 (0)

—

E30

V>—I^ E26\

E30

JO-

E34

ZONE 6 (0)-

RCRC (6636) L

Figure 7-1 1

Data Gating, RCRC Instruction
7-15

Table 7-2
Translation, Hollerith Code — Alphanumeric Code

DATA Bit

Hollerith Code

Character
(card row punched or marked)

12,1

through

1
1

through

12,9

11,1

through

11,9

0,2

through

through
1

through

0,9

=
,

0,1

3,8
0,3,8

11,3,8

12,3,8

4,8
(

0,4,8

11,4,8

12,4,8

)

SECTIONS MAINTENANCE
Refer to Volume 1 and the respective card reader instruction manuals for maintenance information that pertains
to both the control and the card readers.

The diagnostic program should be used to isolate problems that occur in

the system.

Table 7-4 shows the connector pin assignments for the control and the respective card reader.

SECTIONS SPARE PARTS
Table 7-5 lists recommended spare parts for the CR8-E/CM8-E. These parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.

7-16

Table 7-3
Translation, Hollerith Code - Compressed Code

DATA Bit

Hollerith Code

Character
(card row punched or marked)
1

3
4

1
1

12,1

through

H
1

11,1

through

11,8

11,9

0,2

through

0,8

0,9

0,1

1
1

through
1
1

1
1

through
1
1

1
1

=
,

3,8

0,3,8

11,3,8

4,8
*
)

+
-

12,3,8

(

through

12,8

12,9

through

0,4,8

11,4,8

12,4,8

1
1

7-17

Table 7-4

Connector Pin Assignments, J1— J5, J1— J2

M843 Module
J1 (DEC 1209941)

GDI 100M

Documation M200

J5 (AMPHENOL 57-40240)

J2 (ELCO 00-8016-038-000-707)
Pin

Signal

ON LINE X+

RDY (Ready)

DATA STROBE X+

IM (Index Mark)

Signal

READY/ON LINE

INDEX MARKER/

Signal

DATA STROBE
N

CIR

CARD IN READER X+

BSY (Busy)

READ

READ COMMAND X+

PC (Pick Command)

ZONE INPUT 12

DATA ROW 12 X+

D12

ZONE INPUT 11

DATA ROW

X+

D11

ZONE INPUT

DATA ROW 10 X+

ZONE INPUT

DATA ROW

X+

ZONE INPUT 2

DATA ROW 2 X+

ZONE INPUTS

DATA ROW 3 X+

ZONE INPUT 4

DATA ROW 4 X+

ZONE INPUT 5

DATA ROW 5 X+

ZONE INPUT 6

DATA ROW 6 X+

ZONE INPUT 7

DATA ROW 7 X+

ZONE INPUTS

DATA ROW 8 X+

ZONE INPUT 9

DATA ROW 9 X+

1 1

Table 7-5

CR8-E/CM8-E Recommended Spare Parts

DEC Part Number

Description

19-9971

IC DEC 6380

19-9705

IC DEC 8881

19-9704

IC DEC 314

19-9373

IC DEC 9601

19-9686

IC DEC 7404

19-9594

IC DEC 8251

19-9050

IC DEC 7475

19-9004

IC DEC 7402

19-5580

IC DEC 7450

19-5579

IC DEC 7440

19-5577

IC DEC 7420

19-5576

IC DEC 7410

19-5575

IC DEC 7400

19-5547

IC DEC 7474

Quantity
'

(continued on next page)

7-18

Table 7-5 (Cont)

CR8-E/CM8-E Recommended Spare Parts

DEC Part Number

Description

16-5528

Delay Line, 30 ns

10-0025

Capacitor, 560 pF, 100V, 5%

10-0016

Capacitor, 100 pF, 100V, 5%

Quantity

DM
DM

10-0067

Capacitor, 6.8 {jlF, 35V, 20% S. TANT.

10-1610

Capacitor, 0.01 mF, 100V, 20% DISK

70-7252

Cable, Card Reader Interface

7-19

PART 7
MAGNETIC TAPE

CHAPTER 8
TD8-E DECTAPE CONTROL

INTRODUCTION

SECTION 1

The TD8-E Simple DECtape Control is used to control a TU56M or TU56MH Tape Drive Unit (Figure 8-1). The
TD8-E controls the assembly and disassembly of data to be read from or written onto the DECtape and provides
control signals to the drive unit. The TD8-E logic is on one quad board. Module M868, that is inserted into the
PDP-8/E OMNIBUS and connected to a single or dual TU56M Tape Drive by a 7008447 cable.

The TD8-E controls the direction and motion of the tape drive unit with signals generated by flip-flops in the
Command Register. The Command Register allows the TD8-E to select even or odd tape drive, start and stop, move
forward or reverse, and read or write by changing the state of four flip-flops. These flip-flops are controlled by an
instruction (SDLC) that loads the Command Register with four bits of data from the AC.

The assembly and disassembly of the 12 data bits takes place in the Data Register. The Data Register contains the
gating and register necessary to receive data from and place data on the OMNIBUS. The Data Register takes serial
data from the tape during a read operation and puts serial data on the tape during a write operation.*
INT. I/O

I/O

DECODER
CON TROL SIGNALS

TU56M

FROM AC
TO AC "

DATA 0-n
DATA 0-11

READ
DATA
REGISTER

WRITE

TU56MH
TAPE
DRIVE

MARKTRACK SIGNALS
CONTROLS
STATUS AND
MA RKTRACK

Figure 8-1

CONTROL
LO GIG

TD8-E Block Diagram

•See the PDP-8/E & PDP-8/M Small Computer Handbook, page 7-161, for more detailed information on DECtape formatting.

8-1

SECTION 2 INSTALLATION
The TD8-E is installed on site by DEC Field Service personnel. The customer should not attempt to unpack, inspect,
install, checkout, or service the equipment until a Field Service representative is present.
8.1

INSTALLATION

Perform the following to install the TDB-E System.

Step

Procedure

Ensure power is off.

Ensure jumpers are installed on the M868 to select the correct I/O code for this TD8-E
System (see Table 8-3 for a list of device code jumpers to be installed and unit numbers).

Insert the M868 Module into the

Ensure that the jumpers are installed on the M960 Module (Table 8-2).

Connect the 7008447 cable. P3 goes to J1 on the M868 Module and PI to location A6 or A7
and P2 to location AB10 or AB1 1 in the TU56M (Table 8-1).

Ensure that the G742 Module has been installed in place of the M531 and the G888s are
installed in the

OMNIBUS (see Volume 1 for module priority).

Ensure

that

TU56M Drive Unit.

the

power

wired

according

power wiring

TD8-E-3

for

the

configuration used.

8.2

ACCEPTANCE TEST

Perform the following to check the TD8-E System.

Step

Procedure

Run the Formatter Program (DEC-8E-EUZC-D) on each drive. Follow instructions in the
formatter document.

testing a

TU56M (Dual Drive) swap the formatted tapes from one

drive to the other to run the diagnostic test.

NOTE
The Formatter will run only on TDS-Es with device code 677X
(only on units
and 1).

Run the Diagnostic Programs (MAINDEC-08-DHTDA). Refer to the diagnostic document
for instructions necessary to run the diagnostic.

8.3

TD8-E INTERFACE

A 7008447 cable

is used to interface with the TU56M Tape Transport (Table 8-1). M960 and M961 Connector
Modules are used to connect to the TU56M. The M960 Module is used as connector PI and the M961 Module as

connector P2. The M960 Module has unit selection jumpers that must be installed to select the correct unit. Jumpers
are installed between split lugs as indicated in Table 8-2 to select the proper unit code for the unit.

8-2

Table 8-1

TD8-E Signal Interface
J1 (P3)

Wire

Logic on

M960 Module

M961 Module

on TD8-E

Color

M960 or M961

Pin No.

Black -

Brown
Red

—

Orange

Yellow

HH
RR

Green
Blue -

Violet

Gray -

Ml
C2

Ground
Stop

V2
E2

Unit 1

H2
K2

Units

()

White -

Black -

M
T

Brown
Red

Orange

Black -

Brown

Unit 2

J>__l_o

Unit 4

-__5_o

^-o
^-o

Units
Unite
Unit?
Ground
Select Echo
Ground
Write Echo
Ground
Ground
Write Time

<>-

T2
C2
PI

—

•SI

C2
C2

AA1

—

EE
FF

Red
Orange

Yellow

Green

Blue

Track Pulses

AB1

Violet

Gray
White

Black -

Brown

Red
Orange
Yellow
Green -

—

Write Time

Track Pulses

—

C2
B1

_..-J_.o

o- -

Blue

Reverse

Forward

^-O-O

<i-

Ground
Con All Halt
Ground
UnitO

<>- _.__3..o

C
D
U

Time Mark Enable
Ground

M>-?-

Z
K

Description

AC2

Ground

AC1
AD1

WordO

AC2
AK1
AC2
AMI
AC2
ARl

Ground
Read Time Track
Ground
Read Mark Track
Ground
Word 2
Word 2
Ground
Word 1
Word 1
Ground
Word Enable
Ground

AS1

AC2
ATI

AVI
AC2

BA1

AC2
BB1

—

AC2

Read 1
Ground

Violet -

BEl

ReadO

Gray
White -

AC2

Ground
Read 2

—

BK1

8-3

Table 8-2

M960 Module Jumpers
Unit Numbers

Octal Code

Install Select Jumpers

Oand 1

677X
676X
675X
674X

2 and 3

4 and 5

6 and 7

SECTION 3 FUNCTIONAL DESCRIPTION
The TD8-E M868 Quad Module is inserted into the OMNIBUS and used to control either the TU56M orTU56MH
Tape Drives. The PDP-8/E System can have as many as four TD8-E Modules on the OMNIBUS to control a
maximum of 8 tape units (4 dual drive). For each TD8-E System purchased, the user also receives one H716 Power
Supply to supply +5 Vdc and- 15 Vdc to the TU56M DECtape. The TU56MH (tabletop model) does not receive the

H716 Power Supply.
8.4

INSTRUCTION AND STATUS BITS

The TD8-E uses the following instructions:
Simple DECtape Skip on Single Line Flag (SDSS)
Octal Code:

67X1

Operation:

Skip if Single Line flag is set.

Simple DECtape Skip on Time Error (SDST)
Octal Code:

67X2

Operation:

Skip if Time Error flag is set.

Simple DECtape Skip on Quad Line Flag (SDSQ)
Octal Code:

67X3

Operation:

Skip if Quad Line flag is set.

Simple DECtape Load Command Register (SDLC)
Octal Code:

67X4

Operation:

Load Command Register from the AC, clear Time Error, and start UTS Delay if UNIT,

DIRECTION or STOP/GO flip-flops are changed.
Simple DECtape Load Data Register (SOLD)
Octal Code:

67X5

Operation:

Load Data Register from the AC, do not clear the AC, and clear Single Line and Quad
Line flags.

Simple DECtape Read Command Register (SDRC)
Octal Code:

Operation:

67X6
Load contents of Command Register, Mark Track Register, and Status bits into the AC.
Clear Single Line and Quad Line flags.

Simple DECtape Read Data Register (SDRD)
Octal Code:

67X7

Operation:

Load contents of Data Register into the AC, and clear Single Line and Quad Line Flags.

8-4

The X in the octal code of the instruction indicates one of four different I/O codes used so that four TD8-E nnodules
can be used on the PDP-8/E OMNIBUS. The I/O codes used are 677X, 676X, 675X, and 674X. The first two TD8-Es
ordered will have I/O codes 677X and 676X, respectively. If three or four TDB-Es are ordered, they will have codes
675X and 674X, respectively. The jumpers to be installed to select the correct device code and the unit number to
select the correct unit on the TU56M are shown in Table 8-3.

Table 8-3
Device Code Jumpers

8.5

Octal Code

Install Select Jumpers

Unit Numbers

677X
676X
675X
674X

W2 and W4
W2 and W3
W1 andW4
W1 and W3

Oor 1
2 or 3

4 or 5
6 or 7

FUNCTIONAL OPERATION

Figure 8-2 is a functional block diagram of the TD8-E Simple DECtape Control. For discussion purposes the TD8-E
is

broken into functional groups of logic. Section 4 contains a detailed discussion of each logic group.

TD8-E
CON ALL HALT

MD 3-8

MD 9

I/O

jrTj^

DECODER
I/O PAUSE

WRITE TIME TRACK
T/M ENABLE
READ TIME TRACK

INTERNAL I/O
CO a CI

TP3

WRT
DATA

DATA
REG

WRITE
DATA
LINES

(WR MARK TRACK)

SINGLE LINE

0-11

QUAD LINE
READ

u
k^

DATA
LINES

UNIT

COMM REG

OR 1

GO /STOP

UNIT
S/G

MOTION

FWD/REV

CONTROL

F/R
SEL ECHO

STAT
BITS

WRT ECHO

S^
M.T
REG

READ MARK TRACK

Figure 8-2

TD8-E Functional Block Diagram

8-5

8.5.1

I/O Decoder

As stated before, there are four sets of I/O codes that determine which of four possible TD8-Es is being addressed.
The decoding is done by two jumpers connected to MD7 and MD8. When the correct code for the TD8-E goes to the
I/O decoder and an I/O PAUSE is present an INTERNAL I/O is generated to allow decoding of bits MD 9-11 and
generate an INTERNAL I/O L. The INTERNAL I/O L will prevent the positive I/O bus interface from generating
lOTs while this operation is under way and will generate an enable signal (CC67X) to allow bits MD 9—11 to be
decoded. IVID 9—1 1 are decoded and control the transfer of data and commands to the Data Register, Command
Register, and IVlark Track Register. TP3 is used as a timing signal throughout the control logic. CO and CI determine

the direction of data flow to and from the AC, and determine if the AC is cleared or not.

8.5.2

Command Register

The Command

made up of four flip-flops which

are

loaded from the

DATA BUS by the SDLC

instruction. Is set the flip-flop and Os clear it.

UNIT

Selects which drive on the TU56M is to be used. If UNIT is cleared. Unit

F/R

Determines which direction the tape is to move. If F/R is cleared, direction is Forward (CW).

selected.

CAUTION
Because of circuit delays

the

TU56M, the SDLC instruction to

simultaneously change the F/R flip-flop and the S/G flip-flop should

not be executed. If this instruction is executed, the brake signal in
the

TU56M will be applied to the wrong motor, causing the tape

drive to drift

much further down the tape (in the direction it was

going) than it normally would if the brake were applied to stop tape

movement.

S/G

Tells the selected unit to move tape or stop. If S/G is cleared, the selected tape will stop. The

GO signal

delayed 200 ns after an SDLC instruction to ensure that the unit select line has

had time to switch in the Tape Drive Unit before the tape starts to move.

R/W

Instructs the selected unit to read or write data. If R/W is cleared, a read operation will take
place; if it is set, a write operation is executed.

The SDLC instruction also starts the UP TO SPEED (UTS) delay time and clears the TIME ERROR flip-flop. Figure
8-3 shows the format of data loaded into the Command Register when the SDLC instruction is executed.

UNIT

F/R

S/G

R/W

Figure 8-3

NOT USED TO LOAD
COMfV AND REG STER

Format of Data Loaded into the Command Register

Any time an instruction is executed to change the Command Register, except when the R/W flip-flop is changed, it
starts a new delay timeout of 120 ms; at the end of this time, the UTS will set again. UTS will not set when the S/G
flip-flop is cleared.

8-6

The F{/W flip-flop is cleared (set to a read condition) by any of the following:
a.

8.5.3

SELERR

TIME ERROR
WRITE LOCKOUT

POWER NOT OK

INITIALIZE (Clears all logic)

Data Register

The Data Register contains the gating and register necessary to take data from the OiVlNIBUS and put data in the
OIVINIBUS, It also receives data from the tape during a read operation and places data on the tape during a write
operation.

8.5.4

Mark Track Register

After UTS is set, the Mark Track (MT) Register constantly reads data from the mark track. The mark track data is
read bit by bit, and tested by a Single Line Flag (SLF). Each time SLF is set, a new bit has been shifted into the MT
Register. All decoding of mark track data must be done by the program.

The MT Register is cleared by the start of a UTS delay to ensure that no erroneous codes are left in from a previous
operation. The program must be delayed at least six Single Line flags after UTS has timed out to ensure at least one
complete mark track code has been shifted into the Mark Track Register. This delay ensures a valid code has been
shifted into the register.

The contents of the MT Register are transferred to the AC using an SDRC instruction which also transfers the

STATUS bits and the contents of Command Register at the same time. Figure 8-4 shows the format of the word
used for this transfer.

UNIT

F/R

WLO

SEL/
TIMING

MTRO

MTR2

MTR3

MTR4

MTR5

ERROR

Figure 8-4 Format of Word Transferred to AC

8.5.5

Flags and Status Bits

The Single Line flag is set each time the DECtape reads one line of tape and is used to detect codes on the Mark
Track as discussed in Paragraph 8.6.4. The Single Line flag is cleared by a not-up-to-speed condition and when an

SDLD, SDRC, or SDRD instruction is executed.

A Quad Line flag

is set once for each four lines of data read from the tape. Testing the
Quad Line flag allows the
program to read or write a full 12-bit word. The Quad Line flag is cleared by NOT UTS or by SDLD, SDRC, or

SDRD instructions.
TIME ERROR is an indication that the program did not go back to the control in time to work on the Data Register
before the next transfer of the DECtape took place or that the program was executing an SDLD, SDRD, or SDRC
instruction when the DECtape requested another transfer. If the control has been writing data, TIME

the R/W flip-flop to ensure that erroneous data

not written on the tape. TIME

and put onto the OMNIBUS during an SDRC instruction (Figure 8-4).

8-7

ERROR clears
ERROR isORed with SEL ERR

SEL ERR is sent to the TD8-E by the TU56M to indicate that no unit has been selected or nnore than one unit has
been selected. SEL ERR has no effect on the TD8-E logic, but is transferred from the Comnnand Register to allow
the program to make decisions on what to do about the error.

WRITE LOCKOUT is sent to the TD8-E by the TU56M to indicate that the unit selected for writing was not write
enabled. WRITE LOCKOUT clears the R/W flip-flop and has a status bit for transfer to the AC during an SDRC
instruction (Figure 8-4).

8.5.6

Time Pulse Generator

The Time Pulse Generator and its logic reads a signal from the time track and produces full- and half-cycle pulses on
the rising and falling edges of the time track signal. These pulses are required to read data from and write on the
tape.

The time pulses are gated with and synchronized by the UTS flip-flop so that pulses will be produced when the tape
is up to speed. There is a discriminating delay in the Time Pulse Generator to ensure that noise crosstalk picked up
by the time track head during write operation is not converted into extra time pulses.

The Time Generator has a clock to produce the time pulses required to write the time and mark tracks. The time
track is written directly from a complementing flip-flop in the Time Generator, and the mark track is written from
DATA bit 0. The read time track line is gated off while writing the time and mark tracks to ensure that noise coming
off the time track does not generate unwanted pulses.
8.6

TD8-E TIMING

The TD8-E timing discussed in this section does not indicate the correct way or the only way to program the TD8-E.
The information presented here is meant only to show the interaction between groups of logic when various
instructions are executed.

8.6.1

Timing for Writing Time and Mark Tracks

The time and mark tracks are written to format the DECtape for writing and reading data. Data to be written on the
mark track is transferred from the AC to the DATA BUS in bit positions 00„ 03, 06, and 09 (see the PDP-8/E &
PDP-8/M Small Computer Handbook for the format of data on the tape). Figure 8-5 is a timing diagram for writing
the mark arid time tracks (formatting). Note that the T/M Enable switch, SI, must be set to WTM to enable writing
the time and mark tracks (Table 8-4 for signal functions). DEC-8E-EUZC D gives instructions for formatting
DECtapes and the DEC-8E-EUZC-PD Tape Formatter should be used to format all tapes.
8.6.2

Write Data Timing

The timing diagram in Figure 8-6 shows the timing necessary to write data on the DECtape using the TD8-E. The
data to be written is transferred to the TD8-E from the AC and written on the tape in four 3-bit bytes in the tape
block determined by the programmed instructions. Note that the RTT time pulses must be written on tape using the
Formatter prior to writing data.
8.6.3

Read Data Timing

Figure 8-7 shows the timing required to read data and the mark track from the TU56M DECtape (see Table 8-4 for
signal functions).

8-8

L ^ ^
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J p p
p p
J p p

p p
J p p

p p
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8-9

Table 8-4

TD8-E Signals and Signal Functions
Signal

CON ALL HALT

Function
Signal sent to the TU56M to stop the tape drive if the computer program stops.

of the

The loss

RUN signal from the processor will cause the TU56 to stop. CON ALL HLT stops

an unselected drive that might be moving tape, clears the S/G command flip-flop to
stop
the selected drive, and clears the R/W command flip-flop to keep from writing while
the
drive comes to a stop.

F/R

F/R (Forward/Reverse) will control the direction of tape rotation. If F/R and S/G in the

Command Register are set, the tape, moves in reverse (CCW); if F/R is cleared and S/G is
set, the tape will

INITIALIZE

move forward (CW).

Signal generated by Clear key.

Power Up, and CAF instruction used to clear all flags and

control registers.

RDO

Four bits of serial data are taken from the three parallel tracks and assembled in the Data

RD1

RD2

BUS as indicated below:

RDO

RMT

then transferred as 12 parallel bits to the DATA

Data, 00, 03, 06, 09

RD1

Data, 01,04,07, 10

RD2

Data, 02, 05, 08, 1

Read Mark Track is 6-bits of serial data from the mark track of the tape. The mark track
codes and their functions are as follows (Figure 8-8):

Code

Name

Function

REVERSE END ZONE MARK

This code identifies the code for end zone
located at the beginning of the tape. When

moving
will

the reverse direction, this code

be read as 22 meaning the end of tape is

near and the program should HALT
change the direction of tape movement.

INTER BLOCK SYNC

Code 25 is another NO-OP code which lies
between blocks and for several feet in the
inside of the end zone. This code allows for
turnaround time when reading the first and
last

block;

used

by the program to

synchronize its timing logic between blocks.

FORWARD BLOCK MARK

The number assigned the block by the Formatter is stored on this cell. When the computer

searching for a block,

transfers

number into the AC and examines it.
When code 26 is decoded by the program, it
knows that the block number is in the Data
this

and compared with the block wanted.
8-10

Table 8-4 (Cont)

TD8-E Signals and Signal Functions
Signal

Function

RMT (Cont)
Code
32
10

Name

Function

REVERSE GUARD MARK
LOCK MARK

These two cells are NO-OP conditions which
give the progrann time to decide what to do

with the block it has identified.

REVERSE PCC MARK

This

the last cell before a data cell.

used to initiate the parity checksum routine.
If the computer is writing, the first 12-bit
word to be written is transferred to the con-

troller

during this

cell

and every four

lines

thereafter.

10
10

REVERSE FINAL MARK
REVERSE PREFINAL MARK

two codes indicate the first and
second data words, respectively; otherwise,

These

they have no special significance.

DATA MARK

This code simply indicates that a data word
is

written on the data tracks. The program

continuously checks to see that the mark
track is coded.

73
73

PREFINAL MARK
FINAL MARK

These codes indicate that the last two words

PCC MARK

The parity checksum which was being calcu-

of data are being transferred.

lated

by the program during the transfer is

either written here during a write operation

compared by the program during a read

operation.

REVERSE LOCK MARK

These

are

GUARD MARK

useful

when

NO-OP
the

spaces

tape

become

which
traveling

the

reverse direction.

REVERSE BLOCK NUMBER

The block number

is
stored here to be
picked up by the program when the tape is

traveling in the reverse direction.

INTER BLOCK SYNC

Has the same function

INTER BLOCK

SYNC at the beginning of the tape.
22

END ZONE MARK

When

this code comes up, the program
knows that it has just run out of tape (refer

REVERSE END ZONE) and that it had

better do something about it. Note that this

code

the

complement

REVERSE END ZONE MARK.
8-11

55,

the

Table 8-4 (Cont)

TD8-E Signals and Signal Functions
Function

Signal

RTT

Read Time Track is a 16.6-^s square wave signal coming from the time track. Pulses
produced on the rising and falling edges of the time track signal are used to sync the

TD8-E to read and write data.

SEL ERR

Select Error indicates no unit has been selected or that both units have been selected

simultaneously. The software must decide what to do about the error.

SEL ECHO

Select

Echo

sent to the TD8-E by the

TU56M in response to command signals to

indicate TU56M is on line.

S/G

Stop/Go is sent to the TU56 by the TD8-E to command the tape drive to move in the
direction determined by F/R. This signal is generated by the S/G flip-flop in the

Command Register.
TIME ERROR

Time Error is an indication that the program did not come back to the control in time to
work on the Data Register before the next transfer occurred.

T/M ENABLE

Time Mark Enable allows tape to be formatted by writing on the time and mark tracks
when SI on the M868 Module is set to WTM.

WDO

Twelve bits of parallel data transferred from the DATA BUS to the Data Register and

WD1

disassembled by the Data Register to form four 3-bit bytes of serial data. The four bytes

WD2

serial

data are written by these three signals on parallel tracks on the

DECtape as

indicated below.

WTT

Data, 00, 03, 06, 09
Data, 01,04, 07, 10

WD2

Data, 02, 05, 08, 1

Write Time Track is a
is

WRITE LOCKOUT

WDO
WD1

16.6-)Lts square wave signal written

on the time track when the tape

formatted.

Write Lockout is sent to the TD8-E by the TU56M to indicate that the unit to be written

on is not write enabled. This signal will clear R/W in the Command Register and select the

Read mode.

WD ENABLE

Word Enable is generated when R/W on the Command Register is set and UTS is set to
allow writing data on tape.

UTS

Up To Speed is negated by any change in the Command Register except R/W. After a
delay of 120 ms to allow tape to come up to speed, UTS is again asserted to allow reading
or writing data. UTS is used to enable RTT or

WTT time pulses.

TPGO

Time pulses from the Time Pulses Generator which are produced by the rising and falling

TPG1

edges of the RTT signal (WTT signal while formatting).

QLF

The Quad Line flag is set each time four lines of data are transferred to or from the tape,
so that by testing this line the program will know when a full 12-bit word has been read
or written. QLF is cleared by NOT UTS, instructions SDLD, SDRC, SDRD or
INITIALIZE.

8-12

Table 8-4 (Cont)

TD8-E Signals and Signal Functions
Signal

Function

SLF

The Single Line flag is set each time the DECtape transfers one line of data and is used to
detect mark track codes. SLF is cleared by NOT UTS, instructions SOLD, SDRC, SDRD
or INITIALIZE. SLF is ignored while reading or writing data.

NOISE DLY

Noise Delay is a

^0-[ls delay generated by the Time Pulse Generator to prevent the noise
picked up by the time track head during a write operation from generating extra time

pulses.

SYNC

The SYNC is used to generate and separate the TPO and TP1 pulses required to read or
write.

8-13

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8-15

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8-16

SECTION 4 DETAILED LOGIC
The logic in the TD8-E will be broken into functional groups for discussion purposes. The block diagram. Figure 82,
should be used to understand the interaction of the logic, the signal flow within the nnodule, and the input or output
signals.

INPUT/OUTPUT DECODER LOGIC

8.7

The I/O decoder decodes instructions from the Memory Data Bus and generates signals to control the operation of
the TD8-E (Figure 8-9). Bits MD 3-11 are gated by the I/O PAUSE when an I/O instruction is generated. Bits MD 3
to MD 8 generate a signal CC67XH applying bits MD 9, MD 10, and MD 11 to the 8251 10. The 8251 IC is a
BCD-to-Decimal decoder (see Volume 1, Appendix A, for truth table logic and pin locations) which decodes MD
9-11 and produces a low on one output line. The low out of the 8251 IC indicates which instruction is to be
executed. As an example MD 9 Low, MD 10 and MD11 High (100) produces a low on pin 4 which indicates an
SDLC instruction was programmed. The jumpers for MD 7 and MD 8 will select the device code (see Table 8-3 for
device codes) for multiple TD8-E Systems.

-CC

-D-

SOLD H

COL
INTERNAL I/O
CC MD 9 H
CC MD 10 H

MD7>

MD8>

I/O PAUSED-

TP3>-

INITIALIZE>-

^0-tH>

tt>h>-

RUN
CC INIT L
CC INIT H

-PD

CON ALL HALT H

{>-

CC RUN L
CC RUN L

Figure 8-9

8.7.1

8.7.1.1

I/O Decoder Detailed Logic

Control Logic

C Line Select Logic - The C line logic (Figure 8-9) controls the direction of data flow between the DATA

BUS and the AC and determines if the AC is clear or not. Table 8-5 shows the status of CO and CI to transfer data
between the AC and the DATA BUS using the SDLC, SOLD, SDRC, and SDRD instructions.

8-17

Table 8-5
C-Line Select Levels and Transfer Operations
Instruction

SDLC
SOLD
SDRC

Low

High

Low
Low

SDRD

Transfer Operation

AC -> Data Bus then
AC -> Data Bus
Data Bus -^ AC
Data Bus-^ AC

^ AC

Time Pulse 3 Logic — TP3 shown in Figure 8-9 is used throughout the module to enable gates for execution

8.7.1.2

of instructions.
Initialize Logic — INITIALIZE clears all logic when the computer power is first turned on, when the
CLEAR key on the console operated, or when the CAP instruction is executed.

8.7.1.3

Run Signal and CON ALL HLT Logic — The loss of the RUN signal from the computer will generate CON
ALL HLT, stopping the tape drive unit regardless of the status of the Command Register. RUN is negated any time

8.7.1.4

the program stops.

8.8

COMMAND REGISTER

The Command Register (Figure 8-10) consists of the UNIT, Forward/ Reverse (F/R), Stop/Go (S/G) and Read/Write
(R/W) flip-flops. The flip-flops in the Command Register are set or cleared by AC 0—3 when the Command Register
is

loaded by the SDLC instruction (Paragraph 8.5.2).

8.8.1

Unit Select Logic

The UNIT SEL flip-flop determines which TU56M unit is selected. The UNIT flip-flop sets when bit
is

a 1,

cleared. Unit

8.8.2

from the AC

and it is clocked into the flip-flop by TP3 during the execution of an SDLC instruction. If UNIT flip-flop is
is

selected. SDLC and TP3 clear the UNIT flip-flop if the data input is low (AC bit

0).

Forward/Reverse (F/R) Logic

The F/R flip-flop (Figure 8-10) determines the direction of tape movement. When an SDLC instruction is performed
and bit 1 from the AC is a 1, the F/R flip-flop sets and directs the tape drive to move backward. If the data input is
(bit 1 from the AC is 0) F/R clears when the SDLC instruction and TP3 are applied to the clock (C) input, and the
drive is directed to move forward.
8.8.3

Stop/Go Logic

The stop/go
flip-flop.

flip-flop

latch

If
is

logic (S/G)

flip-flop

(Figure 8-9) enables the tape to

move in a direction determined by the F/R

AC bit 2 is a 1 when the SDLC instruction is performed, the S/G flip-flop sets. The output of the

applied to a latch which also has TP4 as an input. TP4 clocks the latch 300 ns after S/G is set and pulls

output low. The 300-ns delay allows the unit select

lines to settle

before the S/G signal

applied to the

TU56M. S/G is ANDed with POWER OK to remove the GO signal from the TU56M during a power down. Power in
the TU56M does not drop as quickly as power on the PDP-8/E and the tape may continue to run and write
erroneous data.
Loss of the RUN signal from the processor generates CON ALL HLT to the TU56M and clears the S/G flip-flop.

8-18

CO
Z)

-a

c
E
E
o

o
o
00

8-19

Read/Write Logic

8.8.4

The Read/Write flip-flop (R/W) (Figure 8-10) selects the read or write mode in the TU56M. If bit 3 from the AC is a
when the SDLC instruction is executed, R/W will clear and the TU56M will not write on the tape. If bit 3 is 1
when the SDLC instruction is executed, R/W sets, and its output is applied to the reset input of a latch. D TPO is
applied to the set input of the latch. When D TPO is received from the Time Pulse Generator, the outputs of the

low if R/W is set. The latch output is ANDed with NOT CC T/M EN, which enables the gate when SI is
OFF (Figure 8-11). The output of the first gate is ANDed with POWER OK H to generate WD ENAB, causing
the TU56M to write on the DECtape. WD ENAB is ANDed with POWER OK to remove WD ENAB from the TU56M
during a power down of the system. R/W is also cleared by any of the following conditions to select read mode and
remove WD ENAB from the TU56M.
latch will be

set to

SELERR
TIME ERROR
WRITE LOCKOUT
POWER NOT OK

b.
c.

d.
e.

INITIALIZE

NOT RUN

The DECtape can read or write in both directions, but the program must take care of the obverse complement data.
8.9

UTS DELAY LOGIC

The UTS delay logic starts a 120-ms delay after S/G is set, to ensure the tape is up to speed before data is read from
or written on the DECtape (Figure 8-10). Any change in the Command Register, except R/W, clears the UTS
flip-flop and starts a new 120-ms timeout. The D input of SET DLY is enabled by the Exclusive-OR gates
which
cause SET DLY to set if the UNIT, S/G, or F/R flip-flops are changed, thus clearing UTS and starting another
120-ms delay. The following conditions set the SET DLY flip-flop clearing UTS:

S/G9^DFDB2(ACBit2)

F/R^DFDB (ACBit 1)
UNIT^DF DBO(ACBitO)

If SET DLY is set, the 74123 IC is triggered and starts a new 120-ms timeout. After
120 ms, if no new changes are
made in the Command Register, the clock input of the UTS flip-flop goes high. This transition causes UTS to set if

S/G is set supplying a true (high) to the D-input. UTS will not set if the S/G flip-flop is cleared. Any time UTS is

ENABLE flip-flop (Figure 8-11) will clear and disable the Time Pulse Generator logic. The SET DLY
by TP4 of each CC SDLC instruction that changes the Command Register. This is to ensure that
the 120 ms (74123) can trigger on each CC SDLC and the only timeout is 120 ms after the last SDLC.
cleared the TT

flip-flop

cleared

When SET DLY clears it also clears the Mark Track Register (Figure 8-14, Paragraph 8.1 1).
8.10

TIME PULSE GENERATOR

The Time Pulse Generator (Figure 8-11)

has two functions, one is to produce pulses to write the time and mark
tracks (formatting) and the other is to produce timing pulses from the time track signal
(RTT) to allow reading

and

writing of data. The

WTT signal, a 33.2-/lis square wave,

written on the time track of the DECtape when the tape is

formatted. The Time Pulse Generator reads the RTT signal from the timing track of the
tape when data is read from
the tape or written on the tape. Full- and half-cycle pulses (Figure 8-5, signals DTP, DTPO,

and DTP1) are produced
on the rising and falling edges of the time track signal. The time pulses are synchronized with the

UTS flip-flops so

pulses will be produced only when the tape is up to speed.

8-20

Figure 8-1 1

8.10.1

Time Pulse Generator Logic

Write Time Track Pulses

The Write Time Track (WTT) pulses are produced by a 74123 IC (Figures 8-5 and 8-11) and two flip-flops (TPG
and TPG 1) arranged in a conventional switch-tail ring counter. The 74123 IC outputs a pulse every 8.3 /is when SI
is set to WTM, SI
removes the low level from the clear input in the 74123 IC and enables the input gate, which
allows the 74123 IC to be triggered. The T/M ENAB signal is also sent to the TU56M to allow writing on the time
and mark tracks. CC T/M EN is ANDed with WRT OK to remove T/M ENAB from the TU56M during a power down
of the PDP-8/E, and any other condition that clears the R/W flip-flop.

The 74123 used to generate TPG CLK H is a retriggerable monostable multivibrator (one shot) that is set for 8.3 jUS.
External circuitry causes this one shot to retrigger itself on its own trailing edge. An inverter and integrator on the
output of the 74123 IC delays the triggering process for 100 ns, establishing a minimum width for TPG CLK H. TPG
and TPG 1 produce overlapping 33.2-/xs square wave pulses (Figure 8-5). The leading edge of TPG occurs 8.3 /is
before the leading edge of TPG 1. The
output of TPG
is applied to the time track (WTT) signal. The outputs of
TPG and TPG 1 are also used to produce DTPO and DTP1 when writing the time and mark tracks. Gates C and D
(Figure 8-11) must be enabled to apply these signals to the control logic to allow writing on the time and mark
track. CC T/M EN H is applied to C and D when SI is set to WTM during a write operation and CC TPG 0(1) H or
CC TPG (0) H are applied to the gates during a write. The source of the DTP signal is explained below.

8-21

CC TPG is combined in an Exclusive-OR gate with the output of SYNC. The output of the Exclusive-OR gate goes
high when SYNC (1) H and CC TPG 1 (0) H are equal. The 74123 IC is triggered only on the rising edge of its input
signal,

and the SYNC flip-flop is complemented each time the

changes state about 7 /xs before CC TPG

10-/is

74123 times out. Thus, the SYNC flip-flop

changes state, this allows TT EDG to go low for about 7 /is. When CC

EDG again goes high retriggering the 10-/ms 74123 (NOISE
DLY). Once the NOISE DLY is triggered its output holds TT EDG high (through an OR gate) thus preventing any
cross-talk noise coming from RTT (0) from retriggering the delay.

TPG

switches to the same level as SYNC, then TT

Note (Figure 8-5) the rising edge of NOISE DLY occurs in the center of CC TPG

(WTT). This produces a 90 degree

phase shift between the writing of the time track and mark track. The phase shift is required so that when the time
track (RTT)

read back during a normal data transfer, the time pulses used to strobe in the mark track occur in the

center of the mark track signal.

The rising edge of the 10-jus 74123 IC (NOISE DLY) triggers the 100-ns 74123 and produces a 100-ns pulse (DTP).
DTP is produced on every edge of CC TPG 1 and is applied to AND gates C and D. When CC TPG (0) is high, D is
enabled and CC DTP
H is produced; when CC TPG 0(1) is high, C is enabled and CC DTP 1 L is produced. This
separates the DTP pulses into two pulse trains, one has pulses on the rising edge of CC TPG 1 and the other has
pulses on the falling edge of DTP 1.

Most signals in the Time Pulse Generator (Figure 8-1 1) are gated against CC TM EN. This is done to ensure the logic
required for writing the time and mark tracks is enabled only for that operation and the logic to read and write data
is

gated off. The reverse is true when reading the time track and transferring data.

8.10.2

Read Time Track Pulses

The RTT signal read from the time track is used to produce time pulses (Figures 8-1 1 and 8-12) which allow data to
be transferred to or from the DECtape. To supply time pulses (CC DTPO and CC DTP1) AND gates A and B must be
enabled by DTP, SYNC, and TT EN. TT EN is set by the first falling edge of NOISE DLY after UTS is set. This
ensures that time pulses are not produced while the tape is getting up to speed. TT EN is cleared by the loss of the

UTS signal.
-^

(FROM TU56)—»|

|*-16.6hs

[*- 16.6ms

. ..

T_^¥imnmoinnnrnr¥¥T¥ir^YTnr^

NOISE DLYCl

iirfflinnnnnjTinnnrYTTiJTinnr^nR

)

-] 33.3US U-

H-'-h

Figure 8-12 Read Time Track Pulse Timing

8-22

Note the WTM switch must be OFF when tapes are not being formatted. If it is in the WTM position and the tape

moves (but it is not being formatted) the time and mark tracl<s will be destroyed and the tape must be formatted.

The third leg of gates A and B is enabled by DTP out of the 100-ns monostable multivibrator which is triggered by
the rising edge of the IO-/LIS NOISE DLY.

The logic to produce CC DTP1 and CC DTPO is the same as that for writing the time track. The only difference is
that now the signal that generates these pulses is the time track (RTT) coming from the TU56I\/I, rather than being
generated on the M868. The SYNC flip-flop separates the DTP pulses through gates A and B, rather than CC TPG
and gates C and D.

As before SYNC is one input to the Exclusive-OR gate which triggers the NOISE DLY every time RTT and SYNC
are at equal levels. The result is that DTP is produced on each edge of the RTT signal (Figure 8-12). When SYNC is
set gate A is enabled and the DTP produced on the rising edge of RTT goes through gate A and comes out as CC
DTPO. When SYNC is cleared, gate B is enabled and DTP produced on the falling edge of RTT goes through gate B
and comes out as CC DTPl.
Thus, the time pulses are produced to shift in the data, set the flags, set WD ENAB (Figure 8-10) and shift the data
out for writing, etc.

8.11

FLAGS AND SKIP LOGIC

The Single Line flag and Quad Line flag are used to count lines of data read from or written onto the tape and to
enable skip logic when the CC SDSS or CC SDSQ instructions are performed (Figure 8-13). Time Error flag indicates
the timing of a transfer was not correct and enables the skip logic when the SDST instruction is executed.
8.11.1

Single Line Flag

The Single Line flag (SLF) is used to detect codes on the mark track. SLF is set by CC DTPl each time a line of data
is read from the DECtape. If SLF is set and the SDSS instruction is executed, the SKIP line on the OMNIBUS is
grounded, causing the program to skip to the next instruction. The SKIP could cause a subroutine to be performed
to determine what code is in the Mark Track Register and take action accordingly; i.e., is the code a Block Mark? If
so, read the Data Register, and check to see if it is the block number required. Is it an End Zone Mark? If it is, then
you have run out of tape; stop, then reverse direction to continue. SLF is ignored by the program after the correct
block of data has been found, as the program must keep track of the number of words being transferred and put the
parity word at the end of the data.
8.11.2

Quad Line Flag and Counter Logic

The Quad Line Flag (QLF) (Figure 8-13) sets each time the counter made up of flip-flops B and C counts up to four,
indicating four lines of data have been read from or written onto the DECtape. DTPl is applied to the clock (C)
is transferred. When QLF is set and the SDSQ
grounded causing the program to skip to the next

input to cause the counter to increment each time a line of data
instruction

performed, the SKIP

line

on the OMNIBUS

instruction and call a routine to either load or read the Data Register. The
logic to detect a TIME

ERROR

output of QLF is also applied to the

(Figure 8-13), as stated before SLF and QLF are cleared by instructions CC SDRC,

CC SDRD, or CC SOLD, and the loss of UTS.

8-23

'-'

z Q:
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CO
00

8-24

Time Error Flag

8.11.3

The Time Error flag (Figure 8-13) is a latch made from two 7410 gates which sets and generates a TIME ERROR to
transferred to or
indicate the program did not transfer data to or from the Data Register before the next byte has
from the tape. Any of the following conditions will generate a TIIVIE ERROR:

TIIVIE

QLF (1),DTP0H,and R/WSet(1) (Write Operation)

QLF (1), DTPl H, and R/W Cleared (0) (Read Operation)

SDRC, SDRD, or SOLD is executed just as the tape is ready to transfer another byte.

ERROR is cleared by INITIALIZE or an SDLC instruction. When TIME ERROR

set

and the SDST

instruction is executed, the SKIP line is grounded, causing the program to skip the next instruction.

8.12

MARK TRACK REGISTER

The Mark Track (MT) Register (Figure 8-14) receives serial data from the mark track (RMT) containing the mark
of two 8271 ICs.
track codes and outputs 6 bits of parallel data for transfer to the AC. The MT Register is made up
shift register
4-bit
(See Appendix A.8, Volume 1, for timing diagram pin locator and truth table). The 8271 IC is a
Register
Data
the
to
applied
that receives a parallel serial input and provides a parallel output. The parallel output is
(Figure 8-16) for the transfer to the AC during an SDRC instruction.

LOAD

CC UTS (1) H

SHIFT

CLOCK
A

8271
B

CC DTP

MTRO

MTR1

SERIAL IN

CC SET DLY (1) L

LOAD

SHIFT

CLOCK
MTR2
A
8271
B
C

MTR3
MTR4
MTR5

SERIAL IN

RMT (1)

Figure 8-14

Mark Track Register

The output of the MT Register has been redefined; i.e., 1 is a low level and a

a high level output.

UTS

(1)
The MT Register is cleared when SET DLY is cleared. When SET DLY is set UTS is cleared, so the CC
data
parallel
the
as
and
of
the
8271,
on the shift input is low. When SET DLY is cleared it enables the clock input
least
at
wait
must
program
the
before,
stated
output are held high the outputs all go high (redefined as output). As

six SLFs before the

MT Register holds a real mark track code.
8-25

signal

8.13

DATA REGISTER AND GATING LOGIC

The Data Register (Figure 8-15) receives data from the DATA BUS and converts it to serial data to be written on the
DECtape or takes serial data from the DECtape and converts it to parallel data to be gated to the DATA BUS for
transfer to the AC. The Data Register consists of three 8271 ICs (see Volume 1, Paragraph A.8, for
timing diagram,
pin location, and logic diagram) and logic to select the input from the DATA BUS (parallel)
or the input from the
tape (serial). The output (the data being written on tape) is taken from SRO, SRI, and SR2.

LOAD R
-CC DSLD H

SHIFT

CLOCK

;Ty

SR9

^^3

SR6

8271
SR3

-:^iy

DDF

[

Vcc

RDOd)

CC DTP1 L >

CC SD

r.^O

^
LOAD R

CC TP3

DATA 10>-

SHIFT

CLOCK

;X>

SR10

:^:0

^X3

SR7

8271
SR4

C
^

V DF DI

RD1 (1)

LOAD R
SHIFT

CLOCK
A

'^^ly
DATA 2

CC 67X L

^X3
RD2(1)

Figure 8-15 Data Register

8-26

SR8

8271
C

::1I>

SR11

SR5

Three outputs are shifted into the Write Register (Figure 8-17) to be written on tape. The serial input from the
DECtape, RDO, RD1, or RD2 are shifted in by the CC DTP1 pulse and taken from the register as parallel data for

DATA EJUS (Figure 8-16). The SOLD instruction applied to the shift input to enable parallel
DATA BUS at TP3 time during a loading operation. At other times, the shift input held

transfer to the

transfer of data from the

high to enable serial shifting of data through the SR.

8.14

DATA GATING LOGIC

The data gating logic (Figure 8-16) will select the data to be applied to the DATA BUS for transfer to the AC by an
SDRC or SDRD instruction. The SDRD instruction enables AND gates to transfer SR0-SR11 to the DATA BUS.

SR0-SR11 are the 12 data bits read from the tape, applied to the Data Shift Register as serial data, and output to
the data gating logic as 12 bits of parallel data. The SDRC instruction enables

AND gates to transfer the contents of

the Command Register, Status Bits, and iVIT Register to the DATA BUS.

8.15

WRITE FUNCTION REGISTER

The Write Function Register (WFO, WF1, WF2) receives data from SRO, SRI, and SR2 (Figures 8-17 and 8-6) and
outputs the data to the TU56M at the correct timing pulse times.

At CC DTPO (rising edge of RTT) the data from the Shift Register is loaded into the WF Register. At the same time,
the Complement Word (COMP WD) output of the latch goes high. COMP WD is then compared to the complement
of the data loaded into WF through the Exclusive-OR gates and if they are the same level, the Word (WD) lines go
high. If a

had been loaded into WFO at the CC DTPO, then its output would have been low. At CC DTP1 (falling

WD goes low and WFO will go high. The positive transition at CC DTP1 causes a 1 to be written
had been written into WFO, then between CC DTPO and CC DTP1 the WDO signal would be high.

edge of RTT) COMP

on tape. If a

When COMP WD switches low at CC DTP1, there is a negative transition at WDO and a is written on tape. By
examining the write timing diagram (Figure 8-6) you can see how alternating Is and Os always produce a negative
and a positive transition for a 1.

transition for a

8.16

WRITE ECHO AND SELECT ECHO CIRCUITS

WRITE ECHO and SELECT ECHO (Figure 8-18) are supplied totheTD8-E by the TU56M. A SEL ERR condition
if no unit has been selected or both units have been selected. Write Lockout exists if the selected drive unit is
not Write Enabled. The voltage level for these signals and the resulting error condition are shown in Table 8-6.

exists

The SEL ERR and WRITE LOCKOUT ERROR signals are applied to the data gates (Figure 8-16) as status bits to be
transferred to the AC by an SDRC instruction. The software must decide what to do when these errors are detected.

Both errors clear the R/W flip-flop to keep from writing under an error condition.

SECTIONS MAINTENANCE
Recommended preventive maintenance should be scheduled on a regular basis to maintain the reliability and
performance of the DECtape. Preventive maintenance schedules are found in the TU56 DECtape Transport
Maintenance Manual, Chapter 6, Paragraph 6.2.
TD8-E DECtape

(MAINDEC-08-DHTDA) and TD8-E Formatter (DEC-8E-EUZC-PB) were written to
TD8-E DECtape Control with TU56M DECtape Transports. The diagnostic program and
formatter check all logic, as well as the ability to read and write. The diagnostic also provides subroutines for
monitoring TD8-E signals with an oscilloscope and display data in the AC. When a malfunction is suspected the
TD8-E Diagnostic should be used to checkout and troubleshoot the TD8-E. Refer to the TU56 Maintenance Manual
checkout and

Diagnostic

test the

for test equipment, troubleshooting aids, and adjustments.

8-27

CC SDRD L
READ DATA REG

SELECT ER H

CC SDRC L
COMAND REG
•MARK TRACK
I-

STATUS BITS

Figure 8-16 Data Gating Logic

8-28

DF SRO H

DF SRI H

CC DTPO L

CC DTP1

Figure 8-1 7 Write Function Register

Table 8-6
Write Echo and Select Echo Signal and Voltage Levels
Signal Voltage Level

Resulting Condition

WRITE ECHO OV (Write Enable)
WRITE ECH0-3V (Write Locl<out)
SELECT ECHO -3V (2 units selected)
SELECT ECH0-5V (1 unit selected)
SELECT ECHO -15V (No unit selected)

Write Lockout False

8-29

Write Lockout True
Select Error (True)
Select Error (False)
Select Error (True)

Hi'

—W

->i

—

•

—w-

wv—

HH"

rli'

O
o

^r--

—wv

o
<i

CO
00

8-30

SECTION 6 SPARE PARTS
Table 8-7 lists recommended spare parts for the TD8-E. These spare parts can be obtained from any local DEC office
or from DEC, Maynard, Massachusetts.

Table 8-7

TD8-E Recommended Spare Parts

DEC Part Number

Description

Quantity

19-10436

IC 74123

19-09935

IC8235

19-09931

15-09338

ICDEC74H04
IC DEC 7417
IC DEC 8242
IC DEC 8881
IC DEC 5314
IC DEC 7404
IC DEC 8271
IC DEC 8251
IC DEC 5384
IC DEC 5380
IC DEC 7493
IC DEC 7475
IC DEC 7402
IC DEC 7401
IC DEC 7430
IC DEC 7410
IC DEC 7400
IC DEC 7474
Transistor DEC 6351

11-00114

Diode, D664

11-00113

Diode, D662

19-09929

19-09712
19-09705
19-10391
19-09686
19-09615
19-09594

19-10394
19-10392
19-09054

19-09050
19-09004
19-05590
19-05578
19-05576

19-05575
19-05547

8-31

2
2

PART 9
DISPLAYS

CHAPTER 9
TM8-E DECMAGTAPE CONTROL
INTRODUCTION

SECTION 1

The TM8-E DECmagtape Control interfaces the PDP-8/E with the TU10 Master System (Figure 9-1).

To perform this function the TIVI8-E:
a.

Decodes programmed instructions.

Accepts and stores word count, current address, command, and function words.

Selects

program-designated transport

maximum

(eight

the system)

and

starts

the operation

designated by the program.

Generates break requests to initiate a Single Cycle Data Break.

Generates interrupts and skips for flag checking

Buffers the input/output data and assembles a 12-bit word into two 6-bit characters to be written on a
7-track transport; also controls the writing of the 8 LSBs of a 12-bit word on 9-track transports.

Performs housekeeping chores for Single Cycle Data Breaks, i.e., increments Word Count and Current
Address Registers.

Provides ERROR and JOB DONE flags.

Provides lOTs for TM8-E maintenance.

PDP-S/E

COMPUTER

n
TU10
DECMAGTAPE
MASTER
SYSTEM
AND
TRANSPORT

TM8-E
DECMAGTAPE

0N_ T_H_E _0MNIBUSJ

Figure 9-1

TM8-E DECmagtape Control and TU10
Master System, Block Diagram

9-1

TU10

TRANSPORTS
(7 MAXIMUM)

The following quad modules comprise the TM8-E:

M8321 Output Control Module
M8322 Control and Data Break Module
M8323 Transport Status and Control Module
M8327 Registers Module
These quad modules must be inserted into the OMNIBUS and connected together via H851 Top Connectors. Two
BC08-L cables are used to connect the TM8-E (input and output) to the TU10 Master System. The TM8-E receives

+5V logic power from the PDP-8/E OMNIBUS. No power is supplied to or received from the TU10 Master System
by the TM8-E or PDP-8/E.
The TU10 DECmagtape Transport operates at 45 ips and is available in the following formats:

9.1

7-track version, with recording densities of 200, 556, or 800 bpi.

9-track version, with recording density of 800 bpi.

RECORDING METHODS AND DECmagtape FORMATS

The DECmagtape system (TM8-E and TU10 Master/Slave System) is an on-line mass storage system for programs or
is

recorded on tape in vertical rows, termed characters. On a 7-track transport, each character consists of

six data bits

and one vertical parity bit; on a 9-track transport, each character consists of eight data bits and one

data. Data

vertical parity bit.

The vertical parity bit is program selected as even or odd on 7- and 9-track transports. The odd

parity bit guarantees that each character records at least one 1 bit, including an all zeroes character.

The parity bit is generated according to the rule that the number of Is in a character (parity bit included) is odd or
even; for example, when odd parity is used if the character contains an even number of 1 bits, a parity bit is
generated to record an odd number of 1 bits. If an even number of bits is read from tape using odd parity, a vertical
parity error is generated to notify the program that the data is in error.

The data characters are recorded in blocks of characters, termed records (Figure 9-2). Each record contains a
specified number of characters determined by the word count and transport selected (7- or 9-track transport). The

minimum record length is 4 characters, which is two 12-bit words for a 7-track transport or the eight LSB from 4
words on a 9-track transport. The minimum word count for a 7-track transport is the 2's complement of 2 or 77768;
the

minimum word count on a 9-track transport is the 2's complement of 4 or 77748. If a write operation is

attempted for a record with

less than 4 characters, there is no Cyclic Redundancy Check (CRC) or Longitudinal
Redundancy Check (LRC) character and the tape transport runs away. When this occurs, an Initialize operation
must be performed to stop the transport.

Records are separated by interrecord gaps (IRQ). The IRG is approximately 0.5 inch at minimum, but may be
extended to 3 inches by performing an Extended Gap operation. Tape IRGs (unrecorded areas) provide areas on the
tape for the transport to start or stop and also separate data records.

9.1.1

NRZI Recording Method

The TU10 employs the NRZI (non-return-to-zero change on one) recording method. In the NRZI method, a 1 bit is
represented by a reversal in the direction of tape magnetization on a track; a
bit is represented by no change in
tape magnetization.

9-2

END
OF

BEGINING

GAP

OF
TAPE

RECORD

RECORD;

RECORD

GAP

TAPE

a'
t

GAP
FILE MARK
ON 7 TRACK
238 ON 9 TRACK

GAP

(IRG)

(IRG)
A

(IRG)

17s

-APPROX 3.8-

FILE MARK
ON 7 TRACK
23f. ON 9 TRACK
I/q

DATA PREVIOUS-.^

RECORD

-DATA NEXT

RECORD

3"t0.12,',_

4 -0.062

H
t

LAST DATA
CHARACTER

LAST DATA J

LRCC
FILE MARK

LRCC

-FIRST DATA

LRCC

CHARACTER

OF NEXT RECORD

OF PREVIOUS
RECORD

FIST DATA-

CHARACTER
NEXT FILE

OF PREVIOUS
FILE

7 TRACK FILE MARK AND GAP

-APPROX

FORMAT

IRG

DATA PREVIOUS—*HRECORD

0.6"-

3.8"-

7 TRACK

-»H
I

O.b

U— ^x

lllh+^H

t
I
I

FILE

LAST DATA

MARK
LRCC

LAST DATA
CHARACTER
OF PREVIOUS

FIRST DATA

RECORD

CHARACTER
OF NEXT

CHARACTER
OF PREVIOUS

NEXT
— DATA
RECORD

_o K

—

^
CRCC

FORMAT

CRCC

t
I

LRCC

FIRST DATA

CHARACTER
OF NEXT
RECORD

FILE

FILE
9 TRACK

Fl LE

9 TRACK IRG FORMAT

MARK AND GAP FORMAT

¥:' 4 CHAR. SPACE

XX= 8 CHAR. SPACE
Figure 9-2

9.1.2

Data Recording Structure

9-Track: Tape Format

The 9-track format (Figure 9-3) is composed of from 18* to 2048 9-bit characters spaced 1 /800th of an inch apart,
followed by 4 character spaces, a CRC character, 4 more spaces, and an LRC character. This unit of data is called a
record. At 800 characters per inch, the record is between 1/32 Inch (minimum) and 5 inches (maximum). Between
each record is a gap of at least 1/2 inch. The tape structure consists of a number of records followed by a File Mark
(Figure 9-2). Since data is recorded and read at high speed, IRGs are used to provide space for starting and stopping
the TU10 Transports. The TU10 Transport accelerates from standstill to full speed or vice versa in approximately
0.2 inch of tape; thus, the 0.5-inch IRG provides adequate space for starting and stopping the tape transport.
The CRC character (Paragraph 9.1.4) is generated in the TU10 Master System during a Write operation and written
at the end of a record. The check character performs the same function to a record as the parity bit does to a
character. A CRC character is not used on 7-track transports.
*UASCII program standards, not a hardware limit.

9-3

The LRC is the final character in the record and is generated so that for each track the sum of 1 bits (CRC character
included) is even. The LRC character is written on tape by clearing the write buffer in the Master System after the
CRC character is written. The LRC Register is gated to the write buffer and a is written on each track containing
1

an odd number of Is; a

written on each track containing an even number of Is.

LRC

0.005" ±10% (NOTE 3)

CRC 0.005" + 10%
800 CPI
0.001 25" ±3%

WRITE TRACK

REFERENCE EDGE
(FRONT FLANGE

r 0.043" MIN

OF REEL)

LOAD POINT
BEGINING OF

ROT
"mar iTfr".^ TAPE REFLECTIVE
BOT_MA_Rj<ER_^g-pR,p
q,^
NONOXIDE(SHINY)
SIDE OF TAPE

PARITY (ODD)

END POINT
END OF TAPE
REFLECTIVE
STRIP ON NONOXIDE
(SHINY) SIDE

TAPE

TAPE MOTION

LEGEND
BPI

EOT
LRC
CRC

NOTES:

Tape Bits Per Inch
Beginning of Tape
Longitudinal Redundancy Check
CycHc Redundancy Check

Tape is shown with oxide side up, Read/Write head
on same side as oxide. Tape shown representing "1"
bits in all NRZI recording; "1" bit produced by reversal of flux polarity, tape fully saturated in each

direction.
2.

Tape to be fully saturated in the erased direction in
the inter-record gap and the initial gap.

An LRC bit is written in any track if the longitudinal
count in that track is odd. Character parity is ignored

LRC character.
CRC Parity of CRC character is odd if an even

in the
4.

number of data characters are written, and even if an
odd number of characters are written.

Figure 9-3

9-Track Tape Format

9-4

9.1.3

7-Track Tape Format

format (Figure 9-4), the CRC character is not written but the LRC character is written at the end of each
record. Tape character density may be 200, 556, or 800 bpi, with even or odd parity selected by the program.
In 7-track

IRGs are approximately 0.75 inch instead of 0.5 inch (minimum). A record consists of 4* characters (minimum) to
8192 data characters (maximum) followed by 4 character spaces and an LRC character (Paragraph 9.1.5). A 0.75
inch IRG between each record allows the tape to be started and stopped (Paragraph 9.1.2).

OXIDE (DULL) SIDE
OF TAPE FACES

HEADS

REFERENCE EDGE
(FRONT FLANGE
OF

TAPE

SKEW

END POINT
END-OF-TAPE
REFLECTIVE STRIP
ON NONOXIDE
(SHINY) SIDE
OF TAPE

EOR DELAY
CHARACTER
SPACES

REEL)

ONE
CHARACTER
SPACE

OF TAPE

-inch)

TAPE MOTION

Figure 9-4

9.1.4

(SHINY) SIDE

EOR MARK
(LONGITUDINAL
PARITY CHECK
CHARACTER)

^800,566

200

LOAD POINT
BEGINNING-OF-TAPE
REFLECTIVE STRIP
ON NONOXIDE

7-Track Tape Format

Cyclic Redundancy Check Characters (CRC)

The CRC character provides a method of error detection and correction on 9-track TU10 DECmagtape Transports
only. The code has nine check bits that form a check character at the end of each record on 9-track TU10
DECmagtape Transports. To perform a correction, a record in which an error has been detected must be re-read into
memory with the LRC and CRC characters for program evaluation. Errors involving more than one track can be
detected but not corrected.

The CRC character is generated as follows:
a.

The CRC Register, located in the Master System, is cleared at the beginning of each record. As each data
bit is written on tape, it is Exclusively-ORed with its corresponding bit in the CRC Register.
The CRC Register is shifted one position to the right after the Exclusive-OR operation has taken place.

•Hardware limit.

9-5

The bits entering CRC 2, CRC 3, CRC 4, and CRC 5 of the CRC Register are inverted if the bit entering

CRCP is a

(Tables 9-1 and 9-2). Data

shown in Table 9-1; the resultant CRC character is shown in

Table 9-2.

Steps a, b, and c are repeated for each data character of record.

At CRC time, all positions of the CRC Register, except CRC 2 and CRC 4, are complemented and the
resultant CRC character is written on tape.

The CRC Register is cleared for the next record.

Table 9-1

A Five-Character Record
Characters

Data

Character

Character 2

Character 3

Character 4

Character 5

Bit

1
1

Table 9-2

CRCC In Register When Writing

CRC Register
CRC
CRC Bits

(b)

CRCP
CRCO

(c)

CRC1

(a)

CRC2
(e) CRC3
(f) CRC4
(g) CRC5
(h) CRC6
(i) CRC7

Cleared

Character 1

Character 2

Character 3

Final

CRCC

Character 4

CRC

On Tape

1
1

(d)

1
1
1

1
1

9-6

9.1.5

Longitudinal Redundancy Check Character (LRC)

The LRC character is written four spaces after the last data character on a 7-track transport or four spaces after the
CRC character on a 9-track transport. The vertical parity bit is always written on the LRC character; the vertical
parity of LRC is never checked. The LRC character makes the longitudinal parity even for the entire record,
including the CRC. The LRC is generated in the Master System by the LRC Register in the following manner:
a.

The LRC Register is cleared at the beginning of a record.
As characters are written on tape, corresponding 1 bits complement the LRC Register at the time data is
written on tape.

At LRC time, the LRC Register is cleared and Is are written on tape in only those channels for which
the LRC is 1 prior to clearing.

Following this method, the LRC character forces an even number of bits to be recorded on each track of
the tape. The

CRC character is included in determining the LRC character (CRC is used on 9-track

transports only).

9.1.6

Data Files

As previously stated, a record is a group of characters preceded by an IRG and terminated by four spaces and an
LRC character. A file is a group of records separated by IRGs and terminated by a 3-inch gap followed by a File
Mark. The File Mark is a record consisting of a single data character [the end of file (EOF) character] followed by
three blank characters and an LRC character. The CRC character is not written on an EOF record. The LRC
character with a File Mark

a duplicate of the

EOF character. On 7- and 9-track TU10 Transports, the EOF

characters are 178 and 238, respectively.

9.1.7

Track Assign ments

The track assignments for Read, Write, and Parity bits are shown in Table 9-3.

Table 9-3

TU10 Track Assignments for Data and Parity
9-Track

Write

Read

7-Track

Write

Read
Data

Transport

Data

Transport

Data

Track Number

Bits

Track Number

Bits

WD5
WD7
WD3
WDP
WD2

RD5
RD7
RD3
RDP
RD2

WD1

RD1

WDO
WD6
WD4

RDO
RD6
RD4

WD7
WD6
WD5
WD4
WD3
WD2
WDP

RD7
RD6
RD5
RD4
RD3
RD2
RDP

(inside)

8
9 (outside)

4
8

9-7

9.2

COMPANION DOCUMENTS

The following documents and publications are necessary for the operation, installation, and maintenance of the
TM8-E:

PDP-8/E & PDP-8/M Small Computer Handbook, 1 972
PDP-8/E Maintenance Manual, — Volumes 1 and 2

b.
c.

Introduction to Programming, DEC 1972

DEC Engineering Drawing, Magnetic Tape (DEC-00-TM8-E-0-0)
TU10 DECmagtape Master System Manual (DEC-OO-TU 1 0M-D)
TU10 DECmagtape Maintenance Manual (DEC-OO-TU 1 OS-DC)

e.
f.

9.3

SOFTWARE DOCUMENTS

The following diagnostics and programs are available for the TM8-E:

TM8-E Control Test Part 1, MAINDEC-08-DHTMA-A
TM8-E Control Test Part 2, MAINDEC-08-DHTMB-A

Drive Function Timer, MAINDEC-08-DHTMC-A

TM8-E Data Reliability Test - 9-Track, MAINDEC-08-DHTME-A
TM8-E Data Reliability Test - 7-Track,.MAINDEC-08-DHTME-A
TM8-E Random Exerciser, MAINDEC-08-DHTMF-A
TM8-E DECmagtape System Module for DEC/8X, MAINDEC-8X-DHTMA-A

d.
e.
f.

The diagnostics have instructions for loading and running to check the TM8-E.

SECTION 2 SITE PREPARATION, INSTALLATION, AND ACCEPTANCE TEST
is installed on site by DEC Field Service personnel. No attempt should be made by the customer to
unpack, inspect, install, test, or service the TM8-E until a DEC Field Service representative is present.

The TM8-E

9.4

SITE PLANNING AND CONSIDERATIONS

Adequate

site

planning and preparation can simplify the installation process and result

in a

more efficient and

TM8-E installation. DEC Sales Engineers or Field Service Engineers are available for consultation with user
personnel regarding installation. The customer should refer to the TU10 DECmagtape Master System Manual and
TU10 DECmagtape Maintenance Manual for TU10 space requirements, environmental requirements, and installation

reliable

procedures to ensure that the installation site has adequate space, cooling, and power.

Primary planning considerations for TM8-E installation are:

Adequate power on the OMNIBUS for the TM8-E modules (Table 9-4).

A 33 ASR Teletype and programmer's console to run diagnostic and MAIN DEC programs.

Space for the TU 1

TM8-E software for acceptance test and system operation.

Tape Transports.

9-8

Table 9-4

TM8-E Module Power Requirements
Module

Power Requirements

M8321
M8322
M8323
M8327

+5V, 1,000 mA
+5V, 775 mA
+5V, 900 mA
+5V, 1,500 mA
Total

9.5

4,175mA

INSTALLATION

Perform the following procedure to install TM8-E modules:
Step

Procedure
Ensure that power is removed from the PDP-8/E and the TU10.

Ensure that the PDP-8/E and the TU10 cabinets are tied to the same ground or install a
ground wire between the cabinets.

Unpack the TM8-E modules and visually inspect each module for shipping damage.

Ensure that the jumpers are installed correctly to select the priority assigned to the

TM8-E (Paragraph 9.14.3).
5

Insert the TM8-E modules into the

OMNIBUS in the order shown in Figure 9-5. (Refer to

Figure 2-3 of PDP-8/E Maintenance Manual

Volume 1, for module priorities.)

WARNING
The modules must not be installed upside down. The -i-5V,
0.01 iiF capacitors should be at the bottom (next to the
OMNIBUS) on all modules installed on the OMNIBUS.
6

Install two

b.
c.

H851 Top Connectors between the following modules (Figure 9-5):

M8321 and M8327
M8327 and M8322
M8322 and M8323

Insert an M989 Terminator Module in slot A06 of the TU10 Master System.

Connect one BC08-L cable as follows:
a.

b.
c.

PI to J1 on the M8321 Output Control Module.
P2 to J2 on the M8321 Output Control Module.
Insert the

M954 Connector Module into slot A07 of the TU10 Master

System.

9-9

Connect the other BC08-L, cable as follows:
PI to J 1 on the M8323 Status and Control Module.

P2 to J2 on the M8323 Status and Control Module.
Insert the M954 Connector Module into slot B07 of the TU10 Master

b.
c.

System.

NOTE
Route cables between the PDP-8/E and TU10 so that they
are protected and out of the way.

Check TU10 slave terminators (refer to TU10 Print Set).

ONE

M8321

TRANSPORT

(N)

N +

M8322

{

)

M8327

(N + 2

)

M8321

(

M8322
F

M8323

N + 3)

Figure 9-5

9.6

M8323

POSITION

J
M8327

TRANSPORT

TWO

TM8-E Module Installation

ACCEPTANCE TEST

Run the Acceptance Test specified in the TM8-E Print Set (D-TD-TM8-E-1).
9.7

TM8-E INTERFACE

Two BC08-L cables are used to connect the TM8-E to the TU10 Master System. One BC08-L cable is connected
between the M8321 Output Control Module and slot A07 of the TUlO Master System to provide control signals to
the tape drive and data to be written on the TUlO DECmagtape (Table 9-5). The other BC08-L (Table 9-6) cable
connects the M8323 Status and Control Module and slot B07 of the Master System to provide status information
and data read from the TUlO DECmagtape to the TM8-E Control. An M989 Terminator Card must be installed in
slot A06.

The signals on the H851 Top Connectors are shown in Tables 9-7 through 9-10. The signal prefix indicates

the origin of the signal, i.e., all signals prefixed by C originate at the TUlO. The following is a list of prefixes and
their origin.

9-10

Prefix

Origin

TU10

M8321 Module

CB
SC
RE

M8322 Module
M8323 Module

d.
e.

Registers Module

The numeral following the prefix indicates the sheet of the module print where the signal originates, i.e., RE-1
indicates the signal originates on the M8327 Module, sheet 2.

Table 9-5

M8321 Output Control Module Signals and Interface

On
TU10
M954

(Slot A07)

M8321

Pin iSllo.

Pin No.

N
LL

Signal

CSELOH
CSEL1H
CSEL2 H
CSEL 16H
CDEN 5H

Description

*Buffered SELECT
*Buffered SELECT 1
^Buffered SELECT 2

Not used
* Density 5

V
X

CDEN8H
CFMK L
CWXG H
CFWDH
CRWDH

CWRE H

Write Enable with CFWD H, go

CWDOH

Write bit

SI
J1

* Density 8

File Mark

Extended gap

Move tape forward
Move tape reverse
off line with

E2
F2

CWD1 H

V
X

CWD2H
CWD3H
CWD4H
CWD5H
CWD6H
CWD7H
C REWH

CINITH

CREW H

Write bit 1
Write bit 2
Write bit 3
Write bit 4
Write bit 5

Write bit 6
Write bit 7

Rewind
Initialize

CSETH

Begin tape operation

Write Data Ready

CWDR H
C PEV W H

Generate or check for even parity

when asserted

U2
•Refer to Table 9-1 1

CWFMKH

Some pins not used are tied to ground.

9-11

Write File Mark

Table 9-6

TM8-E M8323 Transport Status Control Module Signals and interface

On
TU10
M954

(Slot B07)

M8323

Pin No.

CTUR L
C RDOL

C RDl L

V
X

CRD2L
CRD3L
CRD4L

Signal

C RDS L
C SDWN L

C RD5L
C RD6L

Description

Read Data strobe

Tape motion is stopping
Tape Unit Ready
Read bit from tape unit
Read bit 1 from tape unit
Read bit 2 from tape unit
Read bit 3 from tape unit
Read bit 4 from tape unit
Read bit 5 from tape unit
Read bit 6 from tape unit
Read bit 7 from tape unit
Read Parity bit

CRD7L
CRDPL
CFMKL
CWRS L

C CRCS L

CRC strobe, appears with CRC

CRWS L
CBOT L
CWRL L

Tape Rewinding
Beginning of Tape
Write Lock prevents writing on tape

CVPE L
CSELR L
C7CH L

Vertical Parity Error

File Marl< (end of file)

Write Strobe indicates data on CWD
lines has been written on tape

character

CEOT L
CCRCE L

12
U2

NN
RR

C LRCE L
C LRCS L

Existing transport is on line

7 channel asserted when 7 channel
tape unit is selected

End of Tape

CRC Error
LRC Error
LRC strobe appears with the LRC
character

9-12

Table 9-7

TM8-E M8321 Output Control Module Top Connector Signals

To M8327 Connector F
Signal

To M8327 Connector H

Pin No.

Signal

Pin No.

Not used
OC-2 RWCR L

CB-2 MAC 2 H

RE-1 SEL 16 H

RE-1 DB7H

RE-1 PEVN H

RE-1 FROM

SC-1 SET H

DB5H
CB-1 WR 1st7H

Not used

RE-1 DBS H

Not used

RE-1 DB9H

Not used

RE-1 DB10H

Not used

SC-2 ERROR L

CB-1 WR 2nd 7 H

OC-2 LCAR L

RE-1 DEN 8H

RE-1

DB3H
RE-1 DB2H
RE-1

Not used
CB-3 MTTF L

SC-1 TUR L

RE-1 FR1 H

OC-2 LCMR L

RE-1 FR2H

CB-3 CLR ALL L
OC-2 LCM/F/DB H
OC-2 LFGR L
Not used
Not used

T1
U1

OC-2 CWCR L
OC-2 RMSR L
OC-2 RCAR L
Not used
Not used
CB-1 WDR H
Not used

T1
U1
VI

E2
F2

RE-1

DB6H

A2
B2
C2

Not used

OC-1 R/C ERROR L

CB-3INITH

RE-1 CB1 H

E2
F2

OC-2 LWCR L

RE-1 BSEL1 H

OC-1 RDB L
RE-1 DBOH

RE-1 BSELOH

CB-1 WR9 H

OC-2 CCAR L

RE-1 DB11 H

RE-1 DEN5H

0C-2IBCML

OC-2 CLF L

RE-1

FR3 L

RE-1 BSEL2H

SC-1 CONTROL BSY L

OC-2 SB RM L
OC-2 LDBR L
Not used
Not used

OC-2 AC ENABLE L
OC-2 B TP3 H
OC-2 RFSR L
OC-2 RCMR L

T2
U2
V2

Not used
Not used

RE-1

9-13

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P2

R2
S2

T2
U2
V2

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Table 9-10

TM8-E M8323 Transport Status and Control Module, Top Connector Signals
To M8322 Connector H

To M8322 Connector F
Signal

Pin No.

Signal

Pin No.

CB-1 R/RC H

SC-2 ERROR L

RE-1 WR/WFM

SC-1 DATA LATE L

R/RC AFT WR

CB-3 CLR STATUS L

Not used
Not used

CB-1 OFF LINE L

CB-2 B TP 3 H

CB-1 SPACE H

SC-1 WRS H

CB-1 WCOV H

CB-3 CHG TRANS L
SC-2 EOT L

SC-1 SET H

SC-2 B LRCS L

SC-1

RDS •R+ RCH

CB-2 MAC ACC L

SC-1 7 CHANNEL + DEN 5L

CB-3 BTP4 H

CB-3 MTTF L
Not used
SC-2 REWINDING L
SC-2 BOT L
CB-3 SEL ERROR L

CB-3CLR ALL

SC-1 WRS L

SC-1 SELR L

T1
U1
VI

SC-1 PRESET H

T1
Ul

SC-1

FM L

SC-1 Test

Not used

RE-1 DEN8H

B2
C2

OC-2 RMSR L

SOWN L
CB-2 CHG DIR L

OC-1 RC ERROR

E2
F2

SC-2 RDP H

SC-2 RD 5 H

SC-2 RD 3 H

SC-2 RD 2 H

SC-1

RECORD LENGTH

K1
L1

Ml
Nl
PI

INCORRECT
CB-1 SP REV L

REWIND L
CB-1 BRK RQSTH

CB-1

Not used
Not used

OC-2 LCM/F/DB H

RE-2EMA7 L
SC-1 COUNT CA L
RE-2G0H
SC-2 RD 4 H

SC-1 TUR L

D2
E2
F2

SC-1

RD 7 H

OC-2 RFSR L

SC-2 RD 1 H

RE-1 DEN 5H

Not used

RE-1 EMA INC ENABLE L

SC-1

SC-2RD6H

R2
S2
T2

SC-1

Not used
SC-2 SP REV BOTH
Not used

Not used

EMA INC L
OC-2 LBCM L

SC-1 CONTROL BSY H

U2
V2

Not used
Not used

9-16

R2
S2

T2
U2

SECTIONS PRINCIPLES OF OPERATION

BLOCK DIAGRAM DESCRIPTION

9.8

Figure 9-6, a iDlock diagram of the TIVIS-E DECmagtape Control, depicts the flow of signals between the modules,

OMNIBUS, and the TU10 DECmagtape Master System and slaves. The modules are inserted into the OMNIBUS and
signals are carried between the modules by H851 Top Connectors. The TM8-E is connected to the TU10
DECmagtape System by two BC08-L cables. The TM8-E modules are described in the following paragraphs.

TM8-E REGISTER MODULE

EMA00-EMA02

(M8327)
(1) DATA REGISTER
(2) COMMAND REGISTER
(3) FUNCTION REGISTER

TM8-E TRANSPORT
STATUS AND CONTROL

READ DATA

MODULE (M8323)
(1)

(2)

(4)

WORD COUNT
REGISTER

(3)

(5)

CURRENT ADDRESS

(4)

MAIN STAUS REGISTER
SECOND STATUS
REGISTER

CONTROL LOGIC
ERROR FLAG

READ
DATA

BUFFERED COMMAND

TU10
DECMAGTAPE
MASTER
SYSTEM
WRITE DATA
AND
TM8-E OUTPUT CONTROL
TRANSPORT
MODULE (M8321)

STATUS

STATUS TO AC

(1)

TU10
TRANSPORT
(7

SLAVES

MAXIUM)

INSTRUCTION

DECODER
(2)FUNCTI0N DECODER
(3) SKIP LOGIC
(4) READ COMPARE LOGIC

TM8-E CONTROL MODULE
(M8322)
(1) FUNCTION DECODER
(2) PRIORITY LOGIC
(3) DATA BREAK CONTROL
LOGIC
(4) INTERRUPT LOGIC
(5) CONTROL LOGIC
(6)

JOB DONE FLAG

(MTTF)
DATA00-DATA11

\7
Figure 9-6

TM8-E Block Diagram

M8321 Output Control Module

9.8.1

The M8321 Output Control Module comprises three lOT instruction decoders, a Function Decoder, Read/Compare
Error detection logic, buffers, gating logic to multiplex data to be written on DECmagtape during a Write operation,
and Skip logic.

lOT Instruction Decoder — The three decoders (device codes 70, 71, and 72) provide control signals in
listed in Paragraph 9.9. The lOT decoders generate control signals that are
distributed to the logic of the other TM8-E modules to control data transfer between the TU10 DECmagtape and
core memory. The control signals also control the loading and reading of TM8-E Registers and enable the error
9.8.1.1

response to the lOT instructions

detection logic to monitor data transfer operations.

9.8.1.2

Function Decoder — The Function Decoder receives three function

bits from the

Function Register and

decodes them to select one of the following DECmagtape functions (Paragraph 9.8.2.3).

Offline

Rewind
Read
Read/Compare

The function

signals generated

Write

Write End of File

Space Forward

Space Reverse

by the Function Decoder are sent to the TU10 DECmagtape Master System to

control the selected TU10 DECmagtape.

9-17

9.8.1.3 Gating Logic— The WD bits are gated to the Write Data Buffers in response to control signals from the
TM8-E control module and transferred to the TU10 DECmagtape. On a 7-track transport, data is written on tape in

two 7-bit characters (6 data bits plus parity); on a 9-track transport, data is written in 9-bit characters (8 data bits
plus parity). Parity for each character is generated in the TU10 by the Master System.

Read/Compare Error Detection Logic — The Read/Compare error detection logic compares data read from
DECmagtape with data in memory during the Break cycle and generates a Read/Compare error if the data is
different. This operation is accomplished by Exclusively-ORing the memory data with the data read from the
9.8.1.4

the

DECmagtape. Note the parity bit is not checked by Read/Compare.
Skip Logic — The Skip logic grounds the Skip line and causes the program to skip the next instruction when

9.8.1.5

the following conditions exist:

Tape Unit Ready (TUR) and an SKTR instruction is executed by the program.

ERROR flag

Control not busy and an SKCB instruction is executed by the program.

JOB DONE (MTTF) is set and an SKJD instruction is executed by the program.

set and an

SKEF instruction is executed by the program.

This logic is used by the programmer for flag and error checking operations.

M8327 Registers Module

9.8.2

The M8327 Registers Module contains all of the TM8-E registers except the Main Status Register and Second Status
Register. Each of the registers on the M8327 module is described in the following paragraphs.
9.8.2.1

Multiplexer and Data Register — The Multiplexer and Data Register stores information to be multiplexed to

or from the transport or OMNIBUS. It accomplishes this task in the following manner:

receives data to be written on tape from the

receives data from the

d.
e.

MD lines during a Write Break cycle.

AC via lOT instructions.

The OMNIBUS receives data from the tape transport during a Read operation via the Data Bus.
The Data Register receives data from the tape transport.
The Master System receives data from Data Buffers during a Write Break cycle.

Command Register — The Command Register (Figure 9-7) is loaded with a 12-bit word from the AC by an
LCMR instruction. The Command Register is used to select a tape transport (0—7), enable or disable interrupts,

9.8.2.2

select parity

mode (odd or even), select memory field, and select DECmagtape recording densities. The contents of

the Command Register are transferred to the AC for program evaluation by an RCMR instruction.
9.8.2.2.1 Buffered Command Register (BCM) -The Buffered Command Register is loaded with SEL
through
SEL 2 when LBCM is asserted by the control logic. The output of BCM (B SEL through B SEL 2) is compared
with SEL
through SEL 2 to determine when a new transport has been selected by the program. If the program

new transport, CHG TRANS is asserted to inform the controller that a new transport has been selected.
LBCM is asserted when the following conditions exist:

selects a

The CHG TRANS flip-flop is set and the Rewind status from the selected transport is asserted.

CLR ALL is asserted.

At TP4 time, if any one of the following conditions exist.
2.

CTUR L asserted.
C SDWN L asserted.

CSELR L negated.

9-18

DENSITY
SELECTION
I

UNIT SELEC TION
TRANSPORT 0- 7

L DEN

SEL16

UNUSED

)

(

EXTENDED MEMORY,
ADDRESS
EMA
EXTENDED MEMORY,
"ADDRESS
EMA 0)

INTERRUPT ENABLE
)

(

EXTENDED MEMORY,
ADDRESS 2 EMA 2)

INTERRUPT ENABLE ON
ERROR FLAG lEEF )"

MTTF

DEN 8

PARITY; 0= EVEN
= ODD'

(

ON MAGTAPE FLAG(JOB DONE) (lEMF)

(

)

(

Contents of Command Register

Figure 9-7

9.8.2.3 Function Register — The Function Register (Figure 9-8) is loaded from the AC by an LFGR instruction.
The three most significant bits (FO— 2) are decoded by Function Decoders in the M8321 Output Control Module and
the TM8-E M8322 Control Module to select the following DECmagtape functions.

Offline

Selected transport is taken OFFLINE and rewound to beginning of
tape (BOT).

Rewind

The selected transport rewinds to BOT and stops.

Read

Data

transferred

from tape to memory in the forward direction

only.

Read/Compare

Data read from the tape
there

compared to data in core memory; if

comparison error, the Current Address (CA) Register stops

incrementing and the CA Register holds the memory address in error
at the end of the operation.

Write

Data is written on tape in the forward direction only.

Write End of File

The transport leaves a 3-inch gap and writes a File Mark that consists
of one character followed

by three character spaces and an

LRC

character.

Space Forward

The transport moves forward, at 45 ips, the number of records
specified by the Word Count (WC) Register (Paragraph 9.8.2). If File
Mark is encountered, the transport stops at IRG; if EOT is
encountered, the transport stops at the next IRG.

Space Reverse

The transport spaces in
specified

reverse, at

45 ips, the number of blocks

by the WC Register (Paragraph 9.8.2). If at the beginning

of tape (BOT) a File Mark is encountered, the tape stops.

9-19

UNUSED

FUNCTION
SELECTION
000 OFF LINE
001 REWIND
010 READ

EMA INC ENABLE
GO WHEN EQUAL

TO A ONE

READ/COMPARE
100 WRITE
101 WRITE FILE MARK
110 SPACE FORWARD
111
SPACE REVERSE

011

ENABLE CHECK
'CHARACTER
EXTEND GAP

Figure 9-8

Contents of Function Register

The remaining bits of the Function Register enable the following operations if they are set by a 1 from the AC.
Extended Gap

If bit

3 is a 1, there is a 3-inch gap between records. This bit is used

only during Write functions.

Enable Check Character

If bit

4 is a 1 and a 9-track transport is selected, the LRC and CRC
to memory at the end of a record during Read

transferred

are

operations. This operation

Data

Breaks

after

the

accomplished by executing two more
Register

overflows.

Record Length

Incorrect is disabled at this time.

When bit 5 is a 1, the controller asserts GO, sets CNTL BSY (Control
Busy), generates PRESET, and if no Illegal Functions exist, SET is
asserted to start an operation. A GO command is issued to the
transport if it is ready (TUR is true, and SELECT REMOTE is low).

EMA INC Enable

bit

6 is a 1, the EMA bits in the Command Register and the CA

all

PDP-8/E core

memory as a block instead of in 4K segmients.
Continuous Operation

The MTTF (JOB DONE) signifies the end of a specified operation. If
an

LFGR

instruction

desired

immediately, prior to

TUR, this

instruction may be executed by the program.

Current Address Register - The CA Register is loaded from the AC by an LCAR instruction with a memory
address that is one location less than the desired starting memory location. The CA Register is incremented before
9.8.2.4

each data transfer to sequentially address a block of memory during a data transfer operation. The contents of the
lines during a Single Cycle Data Break to address memory.
CA Register are placed on the

9.8.2.5 Word Count Register — The WC Register counts the number of words in a block of data transferred to or
from memory by the TM8-E. The 2's complement of the number of words to be transferred is loaded into the WC
Register by an LWCR instruction at the beginning of a data transfer. The WC Register is incremented before each

data character is transferred until the

WC Register contains all Os, causing an OVERFLOW. When the WC Register

overflows, data transfer is stopped. This register is also used in spacing operations to count records to be spaced over.

9-20

9.8.3

M8323 Transport Status and Control Module

The TM8-E transport status and control logic contains the majority of the Main Status Register, the second Status
Register, the

(ERROR flag), an illegal

Error detection logic

Function detection

logic,

and receives Read data

(RD0-RD7) from the DECmagtape before it is applied to the Data Register.
9.8.3.1

Main Status Register -The Main Status Register (Figure 9-9) retains transport status information that is

transferred to the AC by an RMSR instruction for evaluation by the program.

ILLEGAL

ERROR FLAG-

FUNCTION

TAPE REWINDING-

READ COMPARE
ERROR

BEGINNING OF
TAPE BOT
(

SELECT REMOTE-

FILE PROTECT

END OF TAPE (EOT)

— DATA REQUEST LATE

PARITY ERROR (VERTICAL,
LRC, OR CRC ERROR

)

FILE MARK

(

RECORD LENGTH
INCORRECT

EOF

Figure 9-9

Contents of Main Status Register

Second Status Register - The Second Status Register (Figure 9-10) retains additional transport status
information that is transferred to the AC by an RFSR instruction for evaluation by the program.

9.8.3.2

SECOND STATUS

FUNCTION
REGISTER BITS
1

FUNCTION—

000 OFF LINE
001 REWIND
010 READ
Oil READ COMPARE
100 WRITE
101 WRITE FILE MARK
110 SPACE FORWARD
111
SPACE REVERSE

CRC ERROR

LATERAL
"parity ERROR
I

EMA INCREMENT ERROR

NOT USED

EXTENDED GAP
ENABLE CHECK
CHARACTER

Figure 9-10

LONGITUDINAL
PARITY ERROR

TRANSPORT CHANNEL
(9 CH =

L— GO BIT (1

)

Contents of Function and Second Status Register

9-21

9.8.3.3

ERROR Flag - The ERROR flag is set by any one of the following error conditions:

End of Tape (EOT)
Read/Compare (R/C) ERROR

Parity Error

Beginning of Tape (BOT)

EMA7INCERR

RECORD LENGTH INCORRECT
DATA LATE

ILLEGAL FUNCTION

FILE MARK

9.8.3.4

Illegal

Function Detection - The

ILLEGAL FUNCTION flag sets, setting the ERROR flag, if any of the

following are attempted:

A Rewind is attempted when tape

A Space Reverse

An attempt is made to select other than 800 bpi density on 9-track transports.

An attempt is made to Read after Write on the same transport.

at BOT.

attempted when tape is at BOT.

lOTs are executed to load the Data Buffer Register, Command Register, or Function Register while the

Control is busy.

Issue a Write or Write File Mark to a tape transport with the Write Ring removed.

An attempt is made to start an operation when the following conditions exist:

CHG TRANSPORT L is true.
TUR H is true.

PRESET is true.

PRESET and SET Pulse Generator - PRESET is a fixed delay that is generated to allow adequate time for
interrogation of the control in order to check for errors and illegal functions prior to asserting the SET pulse. If

9.8.3.5

there are no

illegal

functions or errors, the SET pulse

asserted, thus asserting the C SET

H signal to the tape

transport and starting tape motion.

Control Busy (CNTL BSY) - CNTL BSY is set when the GO bit is issued to indicate that an operation is

9.8.3.6

pending.

9.8.4

M8322 Control and Data Break Module

The M8322 Control and Data Break Module comprises the Data Break Control logic, a Control Function Decoder,
and the Interrupt logic.
Data Break Control Logic - The Data Break Control logic allows the TM8-E to transfer large blocks of data
between the TUlO DECmagtape and memory. When the TM8-E asserts BRK RQST, a priority check is made by the

9.8.4.1

controller.

A priority network on the M8322 module

is compared with priorities of other peripherals requesting a
the TM8-E has the highest priority, the Break Control allows the TM8-E to assert the Break
This action enables the TM8-E to assume control of the CP Major Register gating and to address

data break and,

Control

lines.

memory using the Current Address logic and Data Break Control logic. When BRK RQST is granted by the TM8-E,

9-22

data is transferred from the TM8-E Data Register to the Data Bus (read) or from the IVID lines to the M8321 Output
Control Module (Write or Read/Compare), The TM8-E is is capable of one Single Cycle Data Break approximately

every 28 ^s until a complete record
transferred to memory during a
is

is transferred to or from memory. The CRC and LRC characters are also
Read operation if the ENABLE CHECK CHARACTER bit in the Function Register

set,

9.8.4.2

Function Decoder - The Control Function Decoder decodes FR0-FR2 from the Function Register and

same function as the Output Control Function Decoder on the M8321 Output Control Module
(Paragraph 9.8.1.2). The outputs of this Function Decoder are applied to the control logic on the control module.

generates the

The FR0-FR2 function bits are applied to the Control Function Decoder from the Function Register.
Interrupt Logic -The Interrupt logic on the TM8-E control module generates an interrupt request (INT
RQST) when the following conditions exist (Table 9-11):

9.8.4.3

Bit 4 in the Command Register (I EEF)

set (1) and the

Bit 5 in the Command Register (lEMF)

set (1) and the JOB

ERROR flag is set.
DONE flag (MTTF)

set.

Table 9-11

Command Register Contents and Function
Bit No.

Function

BitsO, 1, and 2

SELO

SEL 1

SEL 2

(BitO)

(Biti)

(Bit 2)

Transport
1

Transport 2

1
1

Transport 3

Transport 4

1
1

Bit 3

Transport 1

Transport 5
Transport 6

Transport 7

= Even Parity; 1 = Odd Parity

Bit 4

If bit

Bit 5

Enable interrupt on JOB DONE (MTTF) if bit 5 is a 1.

Bits 6, 7, and 8

Extended Memory Address (EMA), these bits determine
which memory field the controller uses for data transfer

4 is a 1, enable interrupt ERROR flag.

operations during a Data Break. Function Register bit 6
(Table 9-12) determines if the EMA address is to be in-

cremented or used in the wrap-around mode.

9-23

Tableau (Cont)
Command Register Contents and Function
Function

Bit No.

Bite

Bit?

Bits

(EMAO)

(EMA 1

[EMA 2)
Field
1

Field

Field 2

1
1

Field 3
Field 4

1
1

Fields
Field 6

Field 7

Bit 9

Reserved for future use.

Bits 10 and 11

Density bits, these bits select the density for tape transport operation and are referred to as Den 8 (bit 10) and

Den 5 (bit 11).

Bit 10

Bit 11

Den 8

Den 5
200 bpi, 7 track
556 bpi, 7 channel
800 bpi, 7 channel'
800 bpi, 9 channel

1
1

*This mode is also referred to as Core Dump Mode. When this command is issued to a 9-tracl< transport, zeroes are
and 1 of the DECmagtape and the 9-tracl< transport operates as a 7-track transport.
written on tracks

9.9

INSTRUCTIONS AND STATUS BITS

The following

instructions are

used to program the

TM8-E. Refer to the appropriate table for the status bits

associated with each instruction.

Load Word Count Register (LWCR)
Octal Code:

6701

Operation:

Loads the WC Register with the contents of the AC (Figure 9-1 1) and clears the AC. The WC Register
should not be loaded when the control

busy.

the register

reliability and tape compatibility are not ensured. The WC Register

is
is

loaded during

CNTL BSY, data

loaded with the 2's complement

number of words to be transferred or number of blocks to be spaced. The WC Register is
incremented at TP1 of a Data Break cycle during data transfers, at LRCS during a Space Forward, or
at the first word of a record during a Space Reverse operation.
of the

9-24

RE-2 WCO H

RE-2 DATA

RE-1 BACO-

RE-1 BAC1

•

RE-1 BAC2

RE-2 DATA 1 L
RE-2 DATA 2 L

--!>-

RE-1 BAC3-

RE-1 BAC4

RE-1 BAC5

HOLDING

BAC

RE-1 BAC6

WORD
COUNT
REGISTER

—O--!>
—O-

RE-2 DATA 3 L
-RE-2 DATA 4 L

DATA
BUS
GATING

RE-2 DATA 5 L

-RE-2 DATA 6 L

RE-2 DATA 7 L

RE-1 BAC7

RE-1 BAC8

RE-2 DATA 8 L

h-t>-

-RE-2 DATA 9 L

RE-1 BAC9
RE-1 BAC10

RE-1 BAC11

{RE-2)

!>-

•RE-2 DATA 11 L
(RE-2)

OC-2

OC-2
RWCR L

LWCR L

Figure 9-1 1

-RE-2 DATA 10 L

CLK

{RE-2)

OC-2 BTP3 H

—IX
—

LWCR and RWCR Instruction Data Flow

Clear Word Count Register (CWCR)

Octal Code:

6702

Operation:

Clears the

WC Register. This instruction

used primarily in maintenance operations and should never

be used during CNTL BSY.

Load Current Address Register (LCAR)
Octal Code:

Operation:

6703
Loads the CA Register with the contents of the AC (Figure 9-12) and clears the AC. The CA Register
is

loaded to one less than the memory address of the first word to be transferred. If this instruction is

executed during CNTL BSY, one of the following occurs:
In the wrap-around modes (Function bit 6 = 0), the location of the data transfer cannot
1.
be ensured within the selected memory field.

In the

EMA INC ENABLE mode (Function bit 6 = 1), the location of the data transfer

cannot be ensured within memory.

The CA Register is incremented at each BRK RQST.
Clear Current Address Register (CCAR)

Octal Code:

6704

Operation:

Clears the CA Register. This instruction

used primarily for maintenance and should never be used

during CNTL BSY.

9-25

RE- 2 CAO H

-t>
RE-1 BACO-

-RE-2 DATA

RE-1 BAC1

-RE-2 DATA

•

L
1

RE-1 BAC2

•RE-2 DATA 2 L

RE-1 BAC3'

RE-2 DATA 3 L

RE-1 BAC4

-RE-2 DATA 4 L

RE-1 BAC5

CURR
ADDR

HOLDING
RE-1 BAC6-

BAC

DATA
BUS
GATING

RE-2 DATA 5 L

RE-2 DATA 6 L

RE-1 8AC7

RE-2 DATA 7 L

RE-1 BAC8

-RE-2 DATA 8 L

RE-1 BAC9

RE-2 DATA 9 L

RE-1 BAC10

-RE-2 DATA 10 L

RE-2 DATA 11 L

RE-1 BAC11

(RE-2)

CLK

(RE-2)

OC-2 B TP3 H-l

Figure 9-12

(RE-2)

OC-2

0C:-2

LCAR L

RCAR L

LCAR and RCAR Instruction Data Flow

Load Command Register (LCMR)
Octal Code:

Operation:

6705
Loads the Conrimand Register with the contents of the AC and clears the AC (Figure 9-13). This
must not be issued during CNTL BSY. The LCMR instruction selects tape transport.
Parity mode, memory field, recording densities, and enables or disables interrupts (Table 9-11 and
instruction

Figure 9-7).

Load Function Register (LFGR)
Octal Code:

Operation:

6706
Loads the Function Register with the contents of the AC and
Function Register

the

last

loaded

because

clears the

contains the

AC (Figure 9-14). The

GO bit. This instruction

determines the function the ti^ansport is to perform (Table 9-12 and Figure 9-8).

Load Data Buffer Register (LDBR)
Octal Code:

Operation:

6707
Loads the Data Buffer Register with the contents of the AC, clears the AC, and sets the MTTF flag
(Figure 9-15). This instruction is used, for maintenance purposes.

9-26

OC-2 LCMR
DATA

DATA

RE-1

ai>

^-:0-

SELO H

RE-1 BSELO H

BUF

RE-1 SEL1 H

COM

-RE-1 DATA
-RE-1

DATA

-RE-1

DATA 2 L

-RE-1

DATA 3 L

REG
RE-1 SEL2H
(RE-1)

BAC3
DATA 3 L

;=0-

COMMAND

RE-1 BSEL1 H

RE-1 BSEL2 H

RE-1 PEVN H

DATA 4 L

RE-1 lEEF H
-RE-1 DATA 4 L

DATA

5 L

DATA

6 L

(RE-1)

-RE-1 DATA 5 L

DATA
RE-1

CEMAO H

RE-1

CEMA1 H

RE-1

CEMA2 H

BUS
GATING

-RE-1 DATA 6 L

P/0

DATA 7 L
DATA

8 L

DATA 9

COMMAND

HBAC

;3I>

-RE-1 DATA 7 L

(RE-1)

'-33-

(RE-2)

-RE-1 DATA 8 L

RE-1 SEL16 H
-RE-1 DATA 9 L

P/0

COMMAND

DATA

RE-1 SEL 8 H

-RE-1 DATA 10 L

DATA 11 L

RE-1 DEN 5 H

(RE-1)

OC-2

AC ENABLE

LCMR

-RE-1 DATA 11 L

(RE-1)

EMA1 L

>P|^e'[d

CB-2 MAC1 H

Figure 9-13

LCMR and RCMR Instruction Data Flow

(6716)

OC-2 LFGR

OC-2 RFSR L

O
RE-1

BACO

RE-1 BAC1

RE-

BAC2

RE-1 FRO L

^ RE-1 DATA

RE-1 FR

, RE-1 DATA
3

RE-1 FR 2 L
3

RE-1 BAC3

FUNCTION

RE-1 FR 3 L

DATA

ENABLE CHECK CHAR

RE-1 BAC5

RE-1 GO L

BAC6

RE-1 EMA INC

(RE-1)

RE-1 DATA 2 L

^ RE-1 DATA 3 L

RE-1 BAC4

RE-1

L
1

BUS
GATING

3
^

RE-1 DATA 4 L

RE-1 DATA 5 L

SC-1 7 CHAN+DEN 5 L

RE-1 DATA 6 L

ENABLE L
NOT USED

RE-1 DATA 7 L

_(RE-2)
SC-1 EMA 7 INC

SC-2 DATA 8 L

SC-2 VP ERROR H

^ SC-2 DATA 9 L

DATA
BUS

SC-2 CRC ERROR H

SC-2 LRC ERROR H

GATING

^ SC-2 DATA 11 L

-0
(SC-2)

OC-2 RFSR L
(6716)

Figure 9-14

LFGR and RFSR Instruction Data Flow
9-27

^ SC-2 DATA 10 L

—

Table 9-12

Function Register Contents and Functions
Function

Bit No.

Function Selection: These bits determine the function

Bit 0, 1,and 2

the transport is to perform.

BitO

Bit 1

Bit 2

The selected transport is taken Offline and
rewound to BOT. The MTTF is set when the transport

Offline:

responds to this function and the controller can select

and use another transport. The transport must be
manually reset to the on-line state. The WC and CA
Registers need not be loaded.

Rewind: The transport rewinds at high speed (150 ips)
to BOT and stops. The MTTF is set when the transport

responds to the Rewind function. The controller can
select and use another transport. The

WC and CA

Registers need not be loaded.

Read: Data is transferred from the tape to memory in

the forward direction only. All registers must be loaded.

Read/Compare: Tape data is compared to data in core
memory. All registers must be loaded. If there is a
comparison error, CA incrementation ceases, the R/C

ERROR bit

set, and tape

motion continues to the

end of the record. The CA Register contains the
address of the word that produced the error.

Write:

Data is written on the tape in the forward dir-

ection only. All registers must be loaded. The Write

function is controlled by
disables the Write)

;

WC OVERFLOW (which

the transport writes the appro-

priate check characters to end the block.

Write End of File (File Mark)

The transport writes

the File Mark, which consists of a one word record.

The CA and WC Registers need not be loaded.
1

Space Forward: The tape moves forward at 45 ips
the number of records specified by the WC Register,
or until a File Mark is read. If EOT is read. Space

Forward stops at the first interrecord gap. The CA
Register need not be loaded for Space Forward to
occur.

9-28

Table 9-12 (Cont)

Function Register Contents and Functions

Function

Bit No.

Bit 0, 1, and 2 (Cont)

BitO

Bit 1

Bit 2

Space Reverse: The tape moves in the reverse direction
at 45 ips the number of blocks specified by the

The CA Register need not be read during a Space
Reverse.

Bits

Bit 4

Extended Gap: When bit 3 is a 1 the transport writes
with an additional 3-inch gap between records.
,

Enable Check Character:

When this bit is set (1) and a

9-track transport is selected, it allows the check characters to be read into the computer during a Read

function. When the Word Count overflows, this bit
allows two breaks during 9-track operation for the CRC

and LRC to be transferred to memory. If a Record
Length Incorrect error occurs, the check character is
considered bad and is not used. This bit is used
primarily for 9-track error correction.

Bit 5

Go: This bit causes the controller to issue a Set com-

mand to the transport when the transport is capable
of accepting it. The Set command is not issued if the
specified function is illegal.

Bite

EMA INC Enable: If this bit is not set (0), the TMS-E
(like all other PDP-8 data break options) treats the

extended memory the same way, i.e., each 4K block
is

used in a wrap-around mode. If this bit is set (1),

the extended memory is treated as a continuous

memory rather than 4K blocks. When the last location
in one field is reached, the

EMA bits are incremented

and the transfer continues in the next field; i.e., if a

word is placed in Field 2, location 7777, the following
word is placed in Field 3, location 0000 if the EMA
increment bit is set. If bit 6 is not set, the word is
placed in Field 2, location 0000.

9-29

Table 9-12 (Cont)

Function Register Contents and Functions
Bit No.

Function

Bit 6 (Cont)

in both modes of operation, the Current Address Is set

to one less than the first location to be accessed. In

EMA increment mode, the 12-bit CA Register and the
EMA bits are treated as one 15-bit register with
the EMA bits most significant. For example, to access
Field 2, location 20, load EMA = 2 and CA = 0017; to
access Field 2, location 0, load EMA =
and CA = 7777.
if Field 7
selected, the EMA cannot increment, but
wraps around in Field 7 and an EMA 7 INCREMENT
ERROR occurs.
three

RE-I

DBC2 L

RE-l BAG

RE-3 MPX OH

RE-1 BAG 1

RE-3 MPX

RE-1 BAG 2

RE-3 MPX 2H

RE-1 DB 2H

RE-1 BAG 3

RE-3 MPX 3H

RE-1 DB 3 H

RE-1 BAG 4

RE-3 MPX4H

RE-1 DB4 H

RE-1 BAGS

RE-3 MPX 5H

RE-1

DB5H

DATA
BUS

RE-1

DB6H

GATING

RE-1

DBO H

RE-1 DATA

RE-1 DB

RE-1 DATA

RE-1 DATA 2
o-

RE-1 DATA 3L
o-

RE-1 DATA4L
0-

MULTIPLEXER

DATA

BUFFER

RE-I BAC6 H

RE-3 MPX 6H

RE-1 BAG7 H

RE-3 MPX 7 H

RE-1

RE-1 BAGS H

RE-3 MPX 8H

RE-1 DBS H

RE-1 BAC9 H

RE-3 MPX 9H

RE-1 DB9 H

BACIO H

RE-3 MPX 10 H

RE-1 DBIOH

RE-1 DATA 5L
0-

RE-1 DATA 6L
i-

DB7H

R E -1 D ATA 7 L
0~

RE-1 DATA8L
p-

RE-1

RE-1 DATA9L
RE-1 DATA lOL
J-

RE-1 BACH H

RE-3 MPX IIH

RE-1 DBll H

RE-1 DATA 11 L
>-

(RE-3)

(RE-1)

CB -2 MPX
A

CB-2 MP X
B

Figure 9-15

(RE-1)

Y
CB-2 DBCl

OC-1

RDB

0,'0

LDBR and RDBR Instruction Data Flow

Read Word Count Register (RWCR)
Octal Code:

6711

Operation:

Clears the

AC and transfers the contents of the
Register into the AC (Figure 9-11). This
instruction is used primarily for maintenance, but it can also be used during error check
routines.

Clear Transport (CL T)
Octal Code:

6712

Operation:

Clears the transport master registers and all TM8-E registers and flags.

9-30

Read Current Address Register (RCAR)
Octal Code:

6713

Operation:

Clears the AC and transfers the contents of the CA Register to the AC (Figure 9-12). This instruction
is

used primarily for maintenance, but it can be used for error check routines.

Read Main Status Register (RI\/ISR)
Octal Code:

6714

Operation:

Clears the

AC and transfers the contents of the Main Status Register to the AC (Figure 9-16). The

12-bit Status Register contains the status of the transport and control logic (Table 9-13 and Figure
9-9).

SC-2 ERROR L

DATA
DATA

SC-2 REWINDING L

L
1

DATA 2 L

SC-2 BOT L

SELRH

DATA 3 L

SC-1 PARITY ERR L

DATA 4 L

SC-1

DATA

SC-2 FM L
SC-1

RECORD LENGTH
INCORRECT L

DATA 5 L

BUS
GATING

DATA 6 L

LATE L

DATA 7 L

SC-2 EOT L

DATA 8 L

SC-2 WRL L

DATA 9L

ERROR L

DATA 10

SC-2 ILLEGAL
FUNCTION L

DATAllL

SC-1 DATA

OC-1 RC

(SC-2)

7
0C-2RMSRL

Figure 9-16

RMSR Instruction Data Flow

Read Command Register (RCI\/IR)
Octal Code:

6715

Operation:

Clears the AC and transfers the contents of the Command Register to the AC. The contents of the

Command

instruction

are

instruction shown in Table 9-1 1 and Figure 9-7.

9-31

the same as that for the Load

Command Register

Table 9-13

Main Status Register Contents and Indications
Status Indication

Bit No.

Error:

The ERROR flag interrupts the processor if bit 4 in the Command Register is set (1).

An ILLEGAL FUNCTION or SELECT ERROR sets the MTTF flag immediately and stops
Data Break operations. The following errors,

they occur during any operation, set the

ERROR flag after the MTTF flag is set.

BOT
EOT
READ/COMPARE ERROR

Parity Error (VPE,CRCE, or LRCE)

RECORD LENGTH INCORRECT

File Mark (EOF)

DATA LATE
EMA 7 INCREMENT ERROR
A

Rewind Status (RWS):

Beginning of Tape (BOT):

indicates the selected transport is rewinding.

indicates the

BOT reflective strip is sensed by the selected

transport.

Select Remote:

Parity Error:

indicates a longitudinal parity error, vertical parity error, or CRC error

indicates the selected transport is not on-line.

has

been detected.

File

Mark (FMK):

indicates the selected transport has detected a File

Mark during a

Write FMK, Space, Read, or Read/Compare operation.

Record Length Incorrect: A 1 indicates that during a Read or Read/Compare operation, the
Register is read to
record length was different from the contents of the WC Register. The WC
determine whether the record was long or short.
Data Request Late:

indicates the computer failed to service the

BRK RQST before the

next data transfer to or from the transport.

End of Tape (EOT):

indicates the

EOT reflective strip has been sensed by the selected

transport.

File Protect:

indicates the selected transport has a write lockout ring removed, and no

write functions are accepted.

R/C ERROR: A 1 indicates a comparison failure occurred during the Read/Compare
error.
function. The CA Register contains the address of the word that produced the

9-32

Table 9-13 (Cont)

Main Status Register Contents and Indications
Bit No.

Status Indication

A 1 indicates one of the following Illegal Functions has been programmed.
1.

Execution of LCMR, LFGR, or LDBR while the control is busy.

Specifying any density but 800 bpi for a 9-track transport.

A Space Reverse function when the transport

Read, Read/Compare, or Space Forward after

at BOT.
a

Write or Write End of File

(WEOF) command on same transport.
5.

Changing to transports that are not ready (TUR is false).

Attempting to rewind when tape is at BOT.

Read Function Register and Second Status Register (RFSR)
Octal Code:

6716

Operation:

Clears the AC and transfers the contents of the Function Register and Second Status Register to the
AC (Figure 9-14). The contents of the Second Status Register and Function Register are shown in

Table 9-14.

Table 9-14

Second Status Register Contents and Functions
Function

Bit No.

Not used.

EMA 7 INC ERROR: EMA 7 INC ERROR occurs an attempt
EMA from Field 7 to Field 0. The data wraps around in Field 7.
if

Vertical Parity Error (VPE):

made to increment the

indicates that a VPE error has been detected. This bit is set

only on the character that is bad and cleared by the next good character.

CRC Error (CRCE): A 1 indicates a CRC error has been detected.

Longitudinal Parity Error (LPCE):

indicates an LPCE has been detected.

Read Data Buffer Register (RDBR)
Octal Code:

6717

Operation:

Clears the AC and transfers the contents of the Data Buffer Register to the AC (Figure 4-15). This
instruction can be used in an error check routine to read the contents of the LRC Register.

9-33

Skip If ERROR Flag Is Set (SKEF)
Octal Code:

6721

Operation:

Skip the next instruction if the ERROR flag is set.

Skip Control Not Busy (SKCB)
Octal Code:

6722

Operation:

Skip the next instruction if the control is not busy. Control

busy when the transport is in a GO

condition, control is not busy when MTTF is set at the End of Job (data transfer completed).

Skip Job Done (SKJD)
Octal Code:

6723

Operation:

Skip the next instruction under following conditions.

When JOB DONE (MTTF) is set at LRCS time of a Read, Read/Compare, Write, or

Write File Mark operation.

At the IRG following EOT, FMK, or WCOV during space operations.

MTTF is set by OFFLINE function, SELECT ERROR, or REWINDING status.

MTTF is set by an LDBR (Load Data Buffer Register) instruction.

Skip if Tape Unit Ready (SKTR)
Octal Code:

6724

Operation:

Skip the next instruction if TUR is true.

Clear All Registers and Flags (CLE)

Octal Code:

6725

Operation:

Clear all TM8-E registers and flags if TUR is true. If TUR is false clear MTTF, ERROR flag, and status
registers.

Check for Data Late Error (CKDL)
Octal Code:

6726

Operation:

Force

DATA LATE error condition during a data transfer. This instruction

maintenance (Paragraph 9.13.6).

Set Break Request (SBRM)
Octal Code:

6727

Operation:

Set BRK RQST for one Data Break. This instruction is used for maintenance only.

9-34

used only for

9.10

OPERATION AND PROGRAMMING

TM8-E operation and programming for each of the DECmagtape functions is described in the following paragraphs.
The timing necessary to perform each function and an example of the method used to program the TM8-E are
illustrated for each DECmagtape function. A flow diagram of TM8-E functions is illustrated in Figure 9-20. The logic
used to accomplish these operations is discussed in Chapter 4; the signals on the timing diagrams are defined in Table
9-15.

Table 9-15

TM8-E Signals and Signal Functions
Signal

BAC 0-B AC 1

OC-2 AC ENABLE

Origin

Function

Processor

A 12-bit data word transferred from the Processor AC to load

TM8-E registers.

M8321

AC ENABLE

asserted

any time

670X

instruction

executed to enable bits on the Data Bus to be applied to the

TM8-E registers.

CBOT

TU10

BOT indicates the reflective strip at the beginning of the tape
is

being

sensed

by the tape transport.

the transport

REWINDING or doing a SPACE REVERSE operation when C
BOT is asserted, the transport stops.

*BREAK CYCLE L

M8322

*BF^KIN PROG L

M8322

*BF^K RQST

M8322

The BRK RQST flip-flop is set by an SBRM instruction or
during the Write,

Read, and

Read/Compare operations to

initiate the Single Cycle Data Break and transfer data.

RE-1 BSELO

M8327

RE-1 BSEL 1

B SEL

through RE-1 B SEL 2 are outputs of the
Command Register applied to the TU10. They are
compared with RE-1 SEL
through RE-1 SEL 2 on the
M8323 module; if they are different, the CB-2 CHG TRANS L

RE-1

Buffered

RE-1 BSEL 2

signal is asserted.

*BUS STROBE

Processor

***

M8323
OC-2 CCA R

M8321

OC-2 CCAR is asserted when a 6702 instruction is executed to
clear the

*C0andC1

M8321

0C-2CLF

M8321

CA Register.

Clear all Flags (CLF)

asserted when the 6725 instruction

executed to clear the TM8-E and the Transport Master System
Register if tape unit is ready (TUR).
clear status register, MTTF, and

•OMNIBUS signals.
** Refer to Table 9-3, PDP-8/E & PDP-8/M Small Computer Handbook.

^**Refer to Table 9-2, PDP-8/E 8i PDP-8/M Small Computer Handbook.

9-35

tape unit is not ready,

ERROR flag.

Table 9-15 (Cont)

TM8-E Signals and Signal Functions
Signal

CB-3CLR ALLL

CB-3CLR STATUS

Function

Origin

NIT from processor, SC-1 TUR AND OC-2

Processor

Signal asserted by

M8322
M8321

CLF, OC-2 CLT, and the INITIALIZE instruction to clear all
TM8-E and TUlO Master System registers.

M8322

CB-3

CLR STATUS is asserted to clear the status registers,

ERROR flag, and MTTF a CLF instruction is executed and
C TUR not asserted by the transport.
if

SC-1 CONTROL BSY

M8323

The Control Busy flip-flop is set by an RE-1 GO command at

Command Register (bit 5 = 1) on the next TP4 time and

the

cleared by MTTF.

SC-1 COUNT CA L

M8323

SC-1

COUNT CA L

asserted at Break Request time.

the

Read/Compare (R/C) ERROR flag is set to stop incrementing
the

CA Register, the address of the data that produced a

Read/Compare error is left in the CA Register.

CREVH

M8321

C REV H is asserted by the Space Reverse function.

CB-2CHG DIR L

M8322

The Change Direction

flip-flop

set

any time a change

direction is sensed.

C SOWN L

TU10

Tape Settling Down (C SOWN L) is asserted 2.3 ms after the

MTTF flag sets for 10 ms.

CLRCS L

TUlO

LRC Strobe (C LRCS) is asserted by the TUlO when a LRC
character is read from the tape.

C CRCS L

TU10

CRC Strobe (C CRCS) is asserted when a CRC character is
read from tape.

CVPE L

TUlO

Vertical Parity Error (C

VPE L) is asserted when the TUlO

detects a vertical parity error to set the VPE flip-flop.

CCRCE L

TU10

Cyclic Redundancy Check Error (C CRCE L) is asserted when
the TUlO detects a CRC error.

C LRCE L

TUlO

Longitudinal Redundancy Check Error (C LRCE L) is asserted
when the TUlO detects an LRC error.

CSELR L

TUlO

Select

Remote (C SELR

asserted when the transport

selected and on-line. Other status signals are not valid until C

SELR L is asserted.

CSEL 16H

M8327

For future use.

CFWDH

M8321

C FWD H is asserted by Read, Read/Compare, Write, Write
File Mark, and Space Forward functions.

9-36

Table 9-15 (Cont)

TM8-E Signals and Signal Functions
Function

Signal

C RWS L

Rewind Status (C RWS

asserted any time the selected

transport is rewinding.

CCF^CE

The CRC Error (CRCE) is set when the TU10 detects a CRC
error.

CB-3T INITL

T INIT (tape initialize) is asserted by Space Reverse at BOT,
Select Error, and CLR ALL L.

C INIT L

transport)

(initialize

asserted

by INIT from

processor,

C SET H

SET (C SET H) is generated by the TM8-E to initiate transport
operation.

CREWH

C REW H is asserted when 1XXX is loaded into the Function
Register and initiates the Rewind operation. The three bits are
decoded by the Output Control Function Decoder and applied
to the tape transport. The transport rewinds to BOT and stops.

CWDR H

Write Data Ready (C

WDR H)

asserted by SC-1 SET during a

Write operation and is negated when Word Count goes to zero
by Word Count Overflow (CB-1 WCOV).

CWFMKH

Write File Mark (C WFMK)

asserted when 5XXX

loaded

(FR0-FR2) are
into the
decoded by the Output Function Decoder, and C WFMK is
Function

asserted to cause the

The 3

bits

TU10 to write the End of File Mark

(EOF).

CWREH

Write Enable (C WRE H)

asserted to inform the TU 10 that

the TM8-E is ready to Write, Write File Mark, or Rewind,

CWDOH
CWD1 H

CWD2H
C WD3 H

C WDO H through C WD7 H are data bits to be written on tape
during a Write operation, C WDO H and C WD1 H are not
written on 7-track transports, and they are zero values when
core dump mode is called for on a 9-track transport.

CWD4H
C WD5 H
C WD6 H
C WD7 H

C WXG H

Extended Gap (C WXG H) is asserted when bit 3 in the
Function Register is a 1 to cause the transport to leave a
3-inch gap between records.

9-37

Table 9-15 (Cont)

TM8-E Signals and Signal Functions
Signal

SC-1

DATA LATE L

Origin

M8323

Function

SC-1

DATA LATE L asserted when the computer fails to
BRK RQST before the next data transfer to or fronn
is

service a

tape.

CRDOL

TU10

CRD1 L

C RDO L through C RD7 L are data bits read from the tape
during a Read or Read/Compare operation. C RDO and C RD1

CRD2L

are not read from 7-track transports; they are zero values when

C RD3L

the core dump mode is called for on a 9-track transport.

CRD4L
CRD5L
CRD6L
CRD7 L
CPEVN L

M8321

C PEVN L is asserted when bit 3 in the Command Register is a
1

to select odd parity. The 7-track transports can use even or

odd

parity,

but bit 3 must always be

when writing on a

9-track tape. Even parity operation on 9-track tapes causes a 1

to be written on channel 3 (on the Parity track)

Data is all

Os.

CRDS L

TU10

Read Strobe (C RDS L) is a 100-ns pulse asserted by the TU10
each time a data character is read from DECmagtape.

CTUR L

TUlO

Tape Unit Ready (C TUR L) is asserted by the TU 10 when the
selected tape unit is ready.

C7CH L

TU10

Seven channel (C 7 CH L) is asserted by the selected transport
if

a 7-track transport.

When C 7 CH L is not asserted a

9-track transport has been selected and eight data bits are
transferred.

CB-3CHG TRANS L

M8322

The CB-3 CHG TRANS flip-flop sets and asserts CB-3 CHG
TRANS L when RE-1 BSEL through RE-1 BSEL 2 from the
Buffered Command Register and RE-1 SEL
through RE-1
SEL 2 are different. CB-3 CHG TRANS is cleared by the next
SC-1 SET Pulse.

CPMA DISABLE

M8322

•

OC-1 R/C ERROR L

M8321

The OC-1 R/C ERROR flag is set to assert OC-1 R/C ERROR
if an error occurs during a Read/Compare operation (data read
from DECmagtape is different from data in memory).

•Refer to Table 9-3, PDP-8/E & PDP-8/M Small Computer Handbook.

9-38

Table 9-15 (Cont)

TM8-E Signals and Signal Functions
Signal

RE-1 DBOO-RE-1 DB11

Function

Origin

M8327

RE-1

DB 00 through RE-1 DB 1 1 is a 12-bit word from the

Data Register which could be data read from tape, data from
the AC, or data from the Memory Data lines. The input to the

Data Register is controlled by a Data Multiplexer on the input
of

the

Data

These

bits

applied

are

the

Read/Compare Error detection logic to compare them with
memory data during a Read/Compare operation.
CB-2 DB MPX A L

M8322

Selects data for input to the Data Register (Table 9-17).

CB-2 DB MPX B L

M8322

Selects data for input to the Data Register (Table 9-17).

RE-1 DEN 5H (bit 10)

M8321

See Table 9-1 2 for these function bits.

RE-1 DEN8H
RE-1 lEEF

M8327

Enable Interrupt when ERROR flag (RE-1 lEEF) is asserted if
bit 4 in the

RE-1 lEJF

M8327

Enable Interrupt when JOB DONE (RE-1 lEJF)
bit 5 in the

RE-1 EMAO

M8327

Command Register is a 1.

EMA

RE-1

asserted

Command Register is a 1.
through

EMA 2 are

RE-2

used

address

RE-1 EMA 1

extended memory (Table 9-11). Bit 6 in the Function Register

RE-1 EMA 2

must be a 1 to use Extended Memory Addressing.

RE-2EMA7INCERR L

M8327

RE-2 EMA 7 INC ERR L is asserted when the program tries to
increment beyond

memory

fields

and

sets

bit

the

Second Status Register.
RE-1 EMA INC EN L

M8327

Extended Memory Address Increment (RE-1 EMA INC EN L)
asserted when bit 6 in the Function Register is a 1 to allow
memory to be treated as a continuous memory rather than 4K
is

blocks.

RE-1 ENABCHKCHAR L

M8327

Enable

ENAB CHK CHAR

Check Character (RE-1

asserted and sets bit 4 of the Second Status Register if bit 4 of

the

Function

character from 9-track transports.

9-39

read

the

CRC and LRC

Table 9-15 (Cont)

TM8-E Signals and Signal Functions
r

Signal

SC-2 EOT L

Function

Origin

TU10

End of Tape (SC-2 EOT) is asserted if the EOT reflective strip
is sensed by the selected transport. C
Main Status Register.

SC-2 ERROR L

M8323

ERROR flag

The SC-2

set

EOT sets bit 8 of the

by any one of the following

conditions:

EOT

R/C ERROR

PARITY ERROR
BOT

EMA7INCERR

REC LENGTH INCORRECT
DATA LATE

EOF
ILLEGAL FUNCTION
SELECT ERROR

h.
/.

The ERROR flag allows the SKIP line to be grounded if the

SKEF instruction is executed by the program.
RE-1 FR0-FR2

RE-1 GO

M8327

FRO through FR2 are decoded by Function
TM8-E output control module and TM8-E
control module to determine TU10 DECmagtape functions
and generate TM8-E control signals (Table 9-12).
Function

bits

decoders

RE-1

the

asserted when bit 5 in the Function Register is a 1.

RE-1 GO must be a 1 to allow tape operation to start.

SC-2 ILLEGAL FUNCTION

M8323

SC-2

ILLEGAL FUNCTION

asserted

conditions listed in Table 9-13 to set bit 11

by any
in the

the

Main Status

INT STROBE H

Processor

INT I/O L

M8321

INIT

Processor

*Clears

all

flags in the TM8-E

and TU10 Master System. It is

asserted by pressing the CLEAR key on the front panel or by a

6007 lOT instruction.

•Refer to Table 9-3, PDP-8/E & PDP-8/M Small Computer Handbook.

* Refer to Table Q-I.PDP-S/E & PDP-8/M Small Computer Handbook.

9-40

OMNIBUS SIGNALS

Table 9-15 (Cont)

TM8-E Signals and Signal Functions
Signal

'CB-3INT RQST L

Function

Origin

M8322

RQST

CB-3 INT

by one of the following

asserted

conditions:
Bit error in the Command Register

and the

SC-2 ERROR flag is set.
Bit 5 in the

Command Register is a 1 and the JOB

DONE (CB-3 MTTF) flag
I/O PAUSE L*

M8321

C LRCE L

TU10

set.

LRC ERROR (C LRCE L) is set by the TUlO when a LPE is
detected by the Master System.

OC-2 LWCR L

M8321

OC-2 LWCR is asserted to load the WC Register when a 6701
instruction is executed by the program.

OC-2 LDBR

M8321

Load Data Buffer Register (OC-2 LDBR) is asserted when a
6707 instruction is executed by the program to transfer the
contents

the

Data

the

Buffer

This

instruction also sets CB-3 MTTF (JOB DONE).

MAO-MA1

OMNIBUS

MAO

through

memory

MA1 1

locations.

controls the

are

During

used
a

address

data

break,

4096

possible

the

MA lines to select a memory location for a data

transfer between memory and the DECmagtape.

CB-2 MAC ACC L

M8322

CB-2 MAC ACC is asserted when a BRK RQST is granted to
enable the data transfer and clear BRK RQST.

SC-2 NOT LAST XFER L

M8322

MD0-MD11

Processor

MSIR DISABL

M8322

CB-1 OFFLINE L

M8322 and
M8321

OFFLINE is asserted when OXXX is loaded into the
Function Register by a LFGR instruction and the selected

CB-1

transport

rewinds

beginning

tape

and

stops.

The

transport must be manually reset to on-line condition.

SC-1

PARITY ERROR L

* Refer to Table 9-1 , PDP-8/E

M8323

The SC-1 PARITY ERROR flip-flop is set when an LRC, CRC,
or VPE error is detected by the selected TU 10 Tape Transport.

& PDP-8/M Small Computer Handbook.

** Refer to Table 9-2, PDP-8/E & PDP-8/M Small Computer Handbook.

•** Refer to Table 9-4, PDP-8/E & PDP-8/M Small Computer Handbook.
**** Refer to Table 9-3, PDP-8/E & PDP-8/M Small Computer Handbook.

9-41

Table 9-15 (Cont)

TM8-E Signals and Signal Functions
Signal

RE-1 PEVN H

Origin

M8327

Function

PEVN is high, the TU10 generates and checks for even
it is low, the TU10 generates and checks for odd
parity. The level of RE-1 PEVN is controlled by bit 3 of the
Command Register (when bit 3 is a 1, RE-1 PEVN is low).
RE-1

parity;

POWER OK H*

Processor

POWER OK goes high when a PDP-8/E power failure occurs
and generates a CB-3 CLR ALL to stop all transports and end
any operation occurring at the time of a power failure.

SC-1 PRESET H

M8323

SC-1

PRESET H is a 2.5-)US pulse that is triggered by setting

GO bit in the Function Register to a
the selected
ready (C TUR
true). RE-1 PRESET H triggers

the RE-1

transport

the RE-1 SET pulse.

RE-1

RCAR L

M8321

CA Register (RE-1 RCAR) is asserted when the 6713

Read

instruction is executed by the program to transfer the contents

of the CA Register to the AC.

OC-1

RDB L

M8321

Read

Data

Buffer

RDB) is asserted by an RDBR
1
H during a read data break to

(OC-1

instruction or by CB-2 IVIAC

transfer the contents of the Data Buffer Register to the Data
lines.

RE-1 RDBR L

M8321

Read Data Buffer Register (RE-1 RDBR) is asserted when a
6717 instruction is executed by the program to ground OC-1

RDB L and transfer the contents of the Data Buffer Register
to the AC.

SC-1

RECORD LENGTH

M8323

INCORRECT

SC-1

RECORD LENGTH INCORRECT is asserted and sets bit

6 in the Main Status Register if the record length differs from

WC Register. The WC Register must be read by the
program to determine if the record was too short or too long.

the

RE-1

REWIND

M8321

REWIND

RE-1

1XXX

by the Function Decoders

asserted

loaded into the three most significant bits of the

Function Register.
RE-1

RFSR L

M8321

RE-1

RFSR is asserted when a 6716 instruction is executed to

transfer

the

contents

the Second Status

and

Function Register to the AC.

OC-2 RMSR L

M8321

OC-2

RMSR is asserted when a 6714 instruction is executed

by the program to transfer the contents of the Main Status
Register to the AC.

^OMNIBUS signals.

9-42

Table 9-15 (Cont)

TM8-E Signals and Signal Functions
Signal

OC-2 RWCR L

Origin

M8321

Function

OC-2 RWCR

is asserted when a 6711 instruction is executed
by the program to transfer the contents of the WC Register to

the AC.

RE-1 SELOH

M8327

RE-1 SEL 1 H
RE-1 SEL2H

RE-1 SEL
through RE-1 SEL 2 are loaded into the three
most significant bit positions of the Command Register by an

LCMR instruction. These bits are used to select one of the
(maximum)

eight

transports

for

data

transfer

operation

(Table 9-11).

SC-1 SET H

M8323

SC-1 SET H is approximately a 5-//s pulse that is triggered by
setting the

applied

GO bit in the Function Register to 1. SC-1 SET H
to

the

selected

TU10 transports to start

tape

movement if TUR is true (Tape Unit Ready).
OC-2 SKIP L

I\/I8321

The OC-2 SKIP line is grounded when one of the following
conditions exist:

SKEF

instruction

ERROR flag
b.

executed

and

the

SC-2

set.

SKCB instruction is executed and SC-1 CONTROL
BSY is not set.

SKTR

instruction

executed

and

C TUR

asserted.

CB-1 SPACE H

M8322

SPACE H is asserted during Space Reverse or Space
Forward operation and continued until EOT, FMK, or WCOV,

CB-1

CB-1 SP FWD L

M8322

SKJD instruction is executed and the JOB DONE
(CB-3 MTTF) flag is set.

encountered. File Mark is read from the tape.

CB-1 SP FWD is asserted when 6XXX is loaded into the three

most significant bit positions of the Function Register. The
number of records specified by

transport spaces forward the
the

CB-1 SP REV L

M8322

WC Register.

CB-1 SP REV is asserted when 7XXX is loaded into the three

most significant bit positions of the Function

The

transport spaces in reverse the number of records specified by
the

WC Register.

9-43

Table 9-15 (Cont)

TM8-E Signals and Signal Functions
Signal

SC-1 SELR L

Function

Origin

M8323

Select Remote (SC-1 SELR L) indicates to the control that the
selected transport is on-line.

0C-2SBRM L

M8321

Set BRK RQST Maintenance {OC-2 SBRM) is asserted when a

6727 instruction is executed by the program to initiate one
Single Cycle Data Break.

SC-1 TUR L

RE-2WC0L

TUIOand
M8322

Tape Unit Ready (SC-1 TUR L) is asserted when the selected

M8327

Word Count

tape transport is ready.

all

(WCO)

used to generate CB-1

CB-1 WCOV L

M8322

asserted when the

WC Registers read

Os to indicate the data transfer is complete.

RE-2 WCO is

WCOV (Word Count Overflow).

Word Count Overflow (RE-2 WCOV) is asserted when the WC
Register contains all Os to negate C WDR and end a Data
Transfer operation.

CB-1 WR 9 L

M8322

Enables logic to apply 8

bits of data to the selected 9-track

transport during a Write operation.

CB-1 WR 1st 7 L

M8322

Enables the logic to apply the six most significant bits of a
12-bit data

word from memory to the selected 7- or 9-track

transport during a Write operation. Tracks

and 1 of a 9-track

transport are Os if it is used as a 7-track format.

CB-1 WR 2nd 7 L

M8322

Enables logic to apply the six least significant bits of a 12-bit
data word to the selected 7- or 9-track transport during a Write
operation. Tracks

and 1 of a 9-track transport are Os if it is

used to record a 7-track format.
SC-1 WRS L

TU10

Write Strobe (SC-1 WRS) is asserted by C WRS from the TU10

when the selected transport is ready to write new data: C

WRS

100-ns pulse that is asserted once for each character

written on tape.

9.10.1

Single Cycle Data Break

The Single Cycle Data Break is used for data transfers between PDP-8/E core memory and theTUlO DECmagtape
Transports (Figure 9-17). The concept of data transfers and the interrelationship of the Data Break Interface are
explained in Chapter 6 of the PDP-8/E & PDP-8/M Small Computer Handbook 1972. A detailed description of the
Data Break Interface is explained in Chapter 10, Volume 2. Figure 9-18 is a timing diagram of the Single Cycle Data
,

Break Interface; reference this diagram during the discussion of the TM8-E functions and programming that follows.
Data flow for the core dump mode of operation is shown in Figure 9-18.

9-44

NOTE
The programs and timing diagrams presented here are not
necessarily the best or only way to program the TM8-E. They
are shown to illustrate TM8-E functional operation and the
interaction of functional groups of logic. The timing diagram
referred to in the description of TM8-E functions is part of the
TM8-E Print Set (Drawing D-TD-TM8-E 1).
9.10.1.1

Signal Conventions - The following signal conventions are used in the TM8-E.

C, e.g.,
Interface signals. All signals that are used to interface the TMB-E with the TU10 are preceded by
the
from
signals
all
low
(O.OV);
C SET L. All signals applied to the TUlO are asserted when they are

TU10 are asserted when they are high (+3.0V),
All signals on the TM8-E

modules followed by L, e.g., SBRM L, are asserted (true) when they are O.OV.

All signals followed by H, e.g., SEL 1 H, are asserted (true) when they are 3.0V.

All signals

on the TMB-E preceded by B, e.g., BTP3 L, are inverted signals or the outputs of holding

registers, e.g., B

SEL

All signals on the TMB-E have a prefix to indicate their origin as shown in Paragraph 9.7.

Write Data - Data can be written on a

DECmagtape only in the forward direction (see
D-TD-TM8-E-1, sheets 7 and B for timing diagram). The CA Register must be loaded with the starting memory
address minus one; the WC Register must be loaded with the 2's complement of the number of words to be
9.10.1.2

or 9-track

The density and parity bits in the Command Register (Table 9-11) must be set to select tape density,
parity mode, and tape unit. The Write function is controlled by the WC Register such that when WCOV occurs the
data transfer stops. CB-3 MTTF is set when the LRC character passes under the read heads. Note that the WC, CA,
and Command Registers must be loaded prior to the Function Register because the Function Register contains the
GO bit, which initiates tape movement and sets SC-1 CNTL BSY (control busy). If any errors other than illegal

transferred.

functions or select errors occur during a write operation, the ERROR flag is set after MTTF is set. Operation may be
continued on the same transport in the same direction immediately if the registers are reloaded following MTTF. A

continuous operation may still be achieved when a change direction or change transport is encountered; however C

TUR from the selected transport must be asserted.
Read Data - Records are read from a 7- or 9-track DECmagtape transport and transferred to memory
only in the forward direction (D-TD-TMB-E-1, sheets 1 and 6 for timing diagrams). The WC, CA, and Command
Registers must be loaded because they are for a Write operation. Density tape unit, and parity must be selected;
density and parity must be the same as they were when the data was written on tape. During a Read operation, the
9.10.1.3

number of words loaded into the WC Register (in 2's complement) is transferred to memory. If the WC Register is
is
set to less than the actual record length, only the number of words in the WC are transferred. If the WC Register
Record
case,
a
either
In
memory.
to
transferred
is
greater than or equal to the actual record length, the entire record
Length Incorrect Error (SC-1 REC LNG INCORRECT) is generated for evaluation by the program. The WC and CA
Registers contain the number of words read from tape and the address where the last word was stored. The contents
of the

WC Register can be checked by the program to determine the cause of error (record too long or too short).

Parity checks are

made by the TU10 as data is read from tape. If any parity errors are detected, the SC-2 ERROR

program to
flag is set at the same time as CB-3 MTTF. The Second Status Register must be read and evaluated by the
is read from tape.
character
LRCS
the
when
flag)
is
set
DONE
MTTF
(JOB
error.
CB-3
the
what
caused
determine

Note that if a 9-track transport is used, a BRK RQST is made for each character read from tape; a 7-track transport
reads two characters before a BRK RQST is made. Core dump mode causes a 9-track transport to operate the same
as a 7-track transport.

Continuous operation may be obtained under the same conditions as a write operation. Read
Function flag. To read the CRC and LRC characters, bit 4 in the Function

after Write operations set the Illegal

9-45

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9-47

TP1

TP2

TP4

RQST

CB-2 MAC ACC L
CB-2 E26

^^«-^CB°2gS
^tl-'^^U
PRIORITY
* CPMA DISABLE L
* BRK

ji
Jl

_n_

*INT STROBE
* BRK

TP3

IN PROG L

CB-2 MAC1 (1)

CB-2 MAC2 (1)

* MS.IR DISABLE L

*MA,MS,LD CNTL
CB-1

SC-1

COUNT WC L
COUNT CA L

*BRK CYCLE L

^OMNIBUS SIGNALS AS CONTROLLED BY THE TM8-E

Figure 9-19

Single Cycle Data Break Timing Diagram

9.10.1.4 Read/Compare - The Read/Compare operation (see D-TD-TM8-E-1 sheet 2 for timing diagram) compares
data read from tape with data from memory that is addressed by the CA Register. The
and CA Registers must be

loaded and density and parity modes must be set.

an OC-1 R/C ERROR occurs, the incrementation of the CA

R/C ERROR

10 in the Main Status Register (Figure 9-9). Tape motion continues to the end of record and MTTF is

interrupt

enabled (Figure 9-7), the program is Interrupted by an OC-1 R/C ERROR and the Main Status
if the error was a OC-1 R/C ERROR. The CA Register must be read by the program
to

memory location where data was stored that caused the error. Note a Read/Compare operation
cannot follow a Write operation, the tape must be backspaced before starting a Read/Compare operation.

determine the

9.10.1.5 Extended Gap - Extended Gap is used with Write operation (bit 3 in the Command Register must be set)
to cause the transport to leave a 3-inch blank space (gap) at the beginning of a record (Drawing No. TD-TM8-E-1,
1 through 9). This feature is used to leave spaces to separate records or groups of records
and to space over
bad spots on tape. Note that the only difference between this operation and a normal Write operation is the time

sheets

required to obtain the first write strobe pulse from the TU10 (Table 9-15 for definition).

9.10.1.6 Write End of File - The Write End of File operation (D-TD-TM8-E-1, sheet 4) writes a single character on
tape to designate the end of a record or group of records. A ITg is written on 7-track transports and
238 is written
on 9-track transports. On 7- and 9-track transports, the EOF character is followed by an LRC character that is
identical to the EOF character. The
and CA Registers do not have to be loaded for this operation.

9-48

o
M—

(S3

o
CM

-<H3>

9-49

^
<ih

<Ih
GO

CONT

CHG DIR OR CHG TRANS

CONT

CHG DIR OR CHG TRANS

SELR

AND
SOWN

AND

AND
SDWN

AND

TUR

:
'

PRESET

<iy

SEND C SET
C RWD, AND

SEND C REW
TO TRANSPORT

CWRDTOTHE
TRANSPORT

-o
OFFLINE

ANDSEL ERROR

Figure 9-20

TM8-E Flow Diagram (Sheet 2 of 10)

9-50

^
LWCR

LCAR

GO =

LFGR

G0= 1
CHG DIR ORCHG TRANS

CONT

EXT GAP = 1
V.
•

SEND C SET, CWRT
C FWD AND C EXT
GAP TO TRANSPORT

SENDCSET, C WRT
AND C FWD TO
TRANSPORT

SET BRK RQST

INCREMENT CA

BREAK
INCREMENT WC
CLR BRK RQST
CUR DATA LATE
MD-»DB

^
Figure 9-20

TM8-E Flow Diagram (Sheet 3 of 10)

9-51

WRITE

1st 6 BITS

WD LINES

WAIT FOR C WRS

INCREMENT

DATA LATE

2nd 6 BITS

TO WD LINES

WAIT FOR

CWRS

INCREMENT

DATA LATE

6DISABLE

BRK RQST

SET ERROR IF ANY

CLR CNTL BSY
CLR GO
CLR BRK RQST

^
Figure 9-20

TM8-E Flow Diagram (Sheet 4 of TO)

9-52

WRITE FILE MARK

LFGR

G0=

CONT

CHGTR
I

SELR

AND

AND SOWN

TUR

PRESET

<iy

SENDCWRE
ANDC WFMK
TO TRANSPORT

i
WRITE A 17,

WRITE A

CHARACTER

23,

CHARACTER

WRITE LRC
A 23, CHARACTER

WRITE LRC

AHj CHARACTER

LRC S

CHECK FOR ERROR

WRITE
FILEMARK

SETS ERROR

FLAG

6
Figure 9-20

PROGRAM STOP

TM8-E Flow Diagram (Sheet 5 of 10)

9-53

READ OR READ/COMPARE

LFGR AND

<D-

SET GO

CHG DIR OR CHG TRANS

SELR

AND
SOWN

TUR

AND

^
SENDC FWD
AND C SET TO
TRANSPORT
READ/COMPARE

[^^

7 TRACK

TRANSPORT
READ/COMPARE

[>—<))

WAIT FOR RDS

INCREMENT DATA
LATE

DATA LATE

INCREMENT

Figure 9-20

TM8-E Flow Diagram (Sheet 6 of 10)

9-54

9 TRACK TRANSPORT

READ/COMPARE

READ 7 TRACK

SHORT
RECORD

LONG RECORD

SET

RECORD
LENGTH
INCORRECT

NOTE
IF

BIT 4

IN THE COMMAND

DO TWO MORE
BREAKS TO READ LRC AND CRC

Figure 9-20

TM8-E Flow Diagram (Sheet 7 of 10)

9-55

o
ftU/COIV

WAIT FOR RDS

INCREMENT

DATA LATE

LONG RECORD

SET RECORD

LENGTH INCORRECT

STROBE ist
6 BITS INTO

DB
SET ERROR IF ANY
CLR GO
CLR BRK RQST
CLR CNTL BSY

WAIT FOR RDS

INCREMENT
DATA LATE

STROBE 2nd 6
BITS INTO DB

SET BRK ROST

INCREMENT CA

BREAK INCREMENT WC
CLR DATA LATE
MD '" DB

STOP

INCREMENT

SHORT RECORD

DISABLE BRK ROST

Figure 9-20

TM8-E Flow Diagram (Sheet 8 of 10)

9-56

9 TRACK TRANSPORT

READ/COMPARE

WAIT FOR RDS

INCREMENT
DATA LATE

SET ERROR IF ANY

^N^ YES

DATA
LATE > 2

STROBE 8 BIT

WORD INTO DB

SET BRK RQST

AND INCREMENT CA

BREAK INCREMENT WC
CLR BRK RQST AND
DATA LATE

MD i'DB

DISABLE

SHORT
RECORD

BRK RQST

SET

RECORD
LENGTH

LONG
RECORD

INCOF RECT

Figure 9-20

TM8-E Flow Diagram (Sheet 9 of 10)

9-57

CLR GO
CLR BRK RQST
CLR CNTLBSY

^
LFGR AND

<D-

SET GO

CHG DIR OR CHG TRANSPORT

SELR

AND
SOWN

ANDTUR

^
SP FWD
1

SPREV

C FWD TO

C REV TO

TRANSPORT

Figure 9-20

TM8-E Flow Diagram (Sheet 10 of 10)

9-58

Space Forward —The Space Forward operation (see D-TD-TM8-E-1, sheet 5 for timing diagram) causes
the tape to space forward a number of records specified by the WC Register. The WC Register must be loaded with
9.10.1.7

WC Register incremented by the C LRCS
WC Register overflows and the last record has been passed
at EOT
an error that sets the SC-2 ERROR flip-flop
over. Note that an attempt to Space Forward when the tape

the 2's complement of the number of records to be spaced over. The

pulse at the end of each record. CB-3 MTTF sets when the

after CB-3

MTTF is set. Space Forward is terminated

a File

Mark is encountered. SC-2 ILLEGAL FUNCTION is

set if Space Forward is initiated after a Write or Write File Mark function.

Space Reverse - The Space Reverse operation (see D-TD-TM8-E-1, sheet 3 for timing diagram) causes the

9.10.1.8

tape to space reverse a number of records specified by the WC Register. The WC Register must be loaded with the 2's

complement of the number of records to be spaced over. CB-3 MTTF sets when the WC Register overflows and the
last record has been passed over. Note that an attempt to do a Space Reverse operation when tape is at BOT is an
function that sets the SC-2

illegal

ILLEGAL FUNCTION flip-flop and ends the operation. A Space Reverse

operation is terminated if a File Mark, BOT, or WCOV is encountered.

Rewind —The Rewind operation causes the tape to rewind at high speed (150 ips) to BOT. The WC and
CA Registers need not be loaded for this operation. CB-3 MTTF is set when the selected transport asserts Rewind

9.10.1.9

Status. After one transport is given the command to rewind another transport can be selected for other operations.
If

the selected unit is rewinding, C TUR

false (not ready)

and no operations can be performed on that transport.

Continuous Operation - As previously stated, an operation ends when the CB-3 MTTF (JOB DONE) flag
To
set.
continue an operation after CB-3 MTTF sets, the program must execute the LFGR instruction before
SDWiN (tape settling down time) to restart the transport and continue the operation. Note that the WC and CA
Registers may have to be loaded to select new Word Count and Memory Address parameters. The operation
9.10.1.10
is

continues until the WC Registers overflow and the operation is terminated.
9.10.2

Programming Notes and Examples

This section is not designed to teach programming but to give some programming notes and examples to be used in

programming the TM8-E. For programming information, refer to the following PDP-8/E handbooks:
a.

9.10.2.1

Introduction to Programming, 1 970
PDP-8/E & PDP-8/M Small Computer Handbook, 1 972

Programming Notes — The only programming restrictions to be considered are those that generate SC-2

ILLEGAL FUNCTIONS (Table 9-13), which includes attempting to perform Read operations after Write operations.
To rejad after writing a record, the program must do at least one tape move operation, i.e.. Space Reverse or Rewind.
9.10.2.2 Programming Examples — The following routine is an example of the method to be used to program the
TM8-E. Note that in this particular example program interrupts are not used.

The general method of calling this TM8-E routine is as follows:

Set locations "COMMAND" (Figure 9-8), "CUR ADR," "WRD CNT," and "FUNCTN" (Figure 9-9) as
indicated at the end of the TM8-E routine.

Execute "JMS TM8-E."

The routine returns to the next location if and only if the CB-3 ERROR flag is set with the final contents of the
Function/Status Register in the MO and the final contents of the Main Status Register in the AC. Refer to Table
9-13 for conditions to set the CB-3 ERROR flag. The routine returns to the second location following "JMS TM8" if
the ERROR flag is cleared (the AC is all Os and the

unchanged).

9-59

TM8E.

Enter here.

CLA

Ensure AC = 0000

CLF

Clear TM8-E flags.

TAD
LCMR

COMMAND

Load Command Register.

CLACMA
TAD

Get drive, parity, field, and density.
Get starting address minus one.

CURADR

LCAR

Load CA Register.

WRDCNT

TAD

Get 2's complement of the number of words to be transferred
or records to be spaced.

LWCR
TAD
LFGR

TM8EN0,

SKEF
SKP
JMP
SKTD
JMP
SKEF
JMP
RFSR

Load WC Register.

FUNCTION

Load Function Register and GO.
Wait for ERROR flag or MTTF flag.

TM8EN0

ERROR flag set.

.-4

MTTF set? ERROR flag set?

TM8E0K

No.

No errors reported for this operation.

ERROR flag set. Read Function/Status.

MQL

RMSR

Read Main Status Register and leave in AC.

SKP

TM8E0K,

Get Function, Gap, GO bit, and EMA Increment.

Bypass return address update if in error.

ISZ

CLF
JMP

TM8E

No error reported then update return address.
Clear TM8-E flags.

TM8E

Exit.

COMMAND,

This location must contain all information to be loaded into the TM8-E Command

FUNCTION,

This location must contain all information to be loaded into the TM8-E Function

CURADR,

This location must contain the first memory address minus one to be used in

Write, Read, or Read/Compare operations.

WRDCNT,

This location must contain the 2's complement of absolute value of the number
of words to be transferred in Write, Read or Read/Compare operations, or the

absolute number of records to be spaced in Space Forward or Space Reverse
operations.

The following is an example of a TM8-E routine using the Program Interrupt System.

TM8-E

Enter here.

CLA

Clear AC (AC = 0000).

CLF

TAD

Clear TM8-E flags.

COMMAND

lOF

LCMR

CLACMA
TAD

CURADR.
Load CA Register.

LCAR

TAD

Get drive, parity, field, and density (Table 9-12).
Turn PDP-8/E Interrupt System off.
Load Command Register (Table 9-11).
Get starting address minus one.

WRDCNT

Get 2's complement of number of words to be transferred or
records to be spaced.

LWCR

Load WC Register.

9-60

TM8-E (Cont)

FUNCTN

TAD
LFGR

Poll another

Get Function, Gap, GO bit, and EMA Increment (Table 9-13).
Load Function Register and GO (Table 9-13).

ION
INT SET,

Turn on program interrupt system.

TMB-EOK

Service another device if Interrupt Request is made.

ERROR flag set.

Device

TM8-E No,

RFSR

ERROR flag

set then

Read Function/Status Register and

load into MQ.

MQL
Read Main Status Register and leave in AC.

RMSR
TM8E0K,

ISZ

TM8-E

CLE
JMP1
INTSER

No error reported then update return address.
Clear TM8-E flags.
Continue servicing other devices.

SECTION 4 DETAILED LOGIC
The logic in the TM8-E is broken into functional groups for discussion purposes. Figure 9-21 should be used to
understand the interaction of the logic, signal flow between groups of logic, and the input or output signals. The
purpose of each group of logic is discussed in Paragraph 9.8.

NOTE
The signals on the TMB-E print set are preceded by two letters
and a number to indicate the origin of the signal, i.e., a signal
with SCI in front of it originates on sheet 1 of the status and
control module prints. Signals without prefixes are OMNIBUS
signals.

9.11

M8321 OUTPUT CONTROL MODULE

9.11.1

Input/Output Instruction Decoder

The I/O Instruction Decoders (Figure 9-21) decode instructions from the Memory Data Bus and generate signals to
control the operation of the TMB-E. Bits MD 3 through MD 11 are gated by I/O PAUSE when an I/O instruction is
executed by the processor. Bits MD 3 to MD 6 generate a signal, 67XX, which partially enables the gates to the I/O
Decoders. MD 7 and MD 8 generate a signal (670X, 671 X, or 672X) to apply bits MD 9, MD 10, and MD 1 1 to the
I/O Decoder. Each I/O Decoder is an 8251 IC; the 8251 IC is a Binary-to-Decimal Decoder (see Appendix A of

Volume 1 for a truth table, logic diagram, and pin locations), which decodes MD 9 through MD 1 1 and produces a
low on one output line. The low out of the 8251 IC indicates which instruction is to be executed. As an example, a
670X instruction with MD 9 low and MD 10 and 11 high (100) produces a low on pin 4 of the 670X Decoder to
indicate that a LFGR instruction (6706) was executed by the program. INT I/O L is grounded to prevent execution
of lOT instructions by the processor while TMB-E instructions are underway.
9.1 1 .2

C Line Select Logic

The C Line Select

logic (Figure

9-21)

controls the direction of data flow between the Data Bus and

AC and

determines if the AC is to be cleared or not. Table 9-16 shows the status of CO and CI to transfer data between the

AC and Data Bus using the TMB-E lOT instructions.
9.11.3

TP3 Logic

TP3 is used to enable the selection of the 670X I/O Decoder and is used throughout the TMB-E to enable the
execution of instructions (Figure 9-21) and to enable data transfers using the Single Cycle Data Break Interface.

9-61

T
LU

m -3 a:
h-

Q
2^

(f)

<\i
<\i

CO
to

M-

0,1

(?j

f^
C^
t^
(0

(/)

CJ
r^
(£

(0 (0 (0 U)
oAoftftftrtrt
<S>

5
< to
5 s o s o

[1!

a:
CVJ

U)
!

i^^

r;;

<c
^

<0
<^

o
u
0)

Q
H

O
CNJ

9-62

Table 9-16

C Line Select Levels for TM8-E Transfer Operations
Instruction

LWCR
LCAR
LCMR
LFGR
LDBR
RWCR
RCAR
RMSR
RCMR

Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low

RFSR

RDBR

9.111.4

Transfer of Operation

High

AC -» Data Bus ^ AC
AC^DataBusO-> AC
AC ^ Data BusO-> AC
AC -^ Data Bus 0^ AC
AC -» Data Bus -> AC
Data Bus ^ AC
Data Bus ^ AC
Data Bus -» AC
Data Bus -^ AC
Data Bus-* AC
Data Bus -^ AC

High
High

Low
Low
Low
Low
Low
Low

CLR ALL Logic

CLR ALL L (Figure 9-21) is asserted to clear TM8-E logic under the following conditions:
a.

At TF3 time, if a CLT (6712) instruction is executed by the program.

When a CLF (6725) instruction is executed by the program if C TUR is true.

When PWR OK H from the processor is lost due to a power failure.

When the processor asserts INIT H. This occurs during power up or when the CLEAR key is depressed
on the PDP-8/E console.

9.111.5

AC ENABLE Logic

OC-2 AC ENABLE (Figure 9-21) is asserted when a 670X instruction is executed by the program to enable gates to
apply the Data Bus information to the TM8-E registers that are loaded from the AC (Figure 9-27) and Control CO
and CI levels (Paragraph 9.11.1).
9.11.8

Skip Logic

The Skip logic (Figure 9-22) asserts OC-2 SKIP BUS L and causes the processor to skip an instruction when the
following conditions exist.

b.
c.

9.11.7

The 6721 (SKEF) instruction is executed and the SC-2 ERROR flag is set.
The 6722 (SKCB) instruction is executed and SC-1 CNTL BSY flag is set.
The 6723 (SKJD) instruction is executed and CB-3 MTTF flag is set.
The 6724 (SKTR) instruction is executed and C TUR L is true.
Output Control Function Decoder

The Output Control Function Decoder (Figure 9-23) is an 8251 IC, which decodes the three most significant bits of
the Function Register and determines what function the TU10 Transport performs (Table 9-12). The 8251 IC is a
BCD-to-Decimal Decoder (see Appendix A, Volume 1, for truth table, logic, and pin locations) which decodes FRO,
FR1, and FR2 and produces a low on one output line. The low out of the 8251 IC indicates the function to be
performed. As an example, if FRO is low, and FR1 and FR2 are high, pin 9 is low indicating a Write operation is to
be performed. The outputs of the Function Decoder, applied to the TU10, are defined in Table 9-15 and Figure 9-7.

9-63

P/0 M8321(0C-2)

SC-

SC-2 ERROR L

OC -2 6721 L

CON BUSY L

OC-2 6722 L

^E>°~1
OC-2

izJ^f5>Mz]2E)°

SKIP BUS L

CB-3 MTTF L

OC-2 6723 L
SC -

TUR

OC-2 6724

:=EH
Figure 9-22

Skip Logic

P/0 M8321(0C-1)

J2 -DD CREV H

Jl-X C FWD H

Jl-BB C WRE H

J2-RR C WFMK H

Jl-Z CR WD H

J2-V CWXG H

CB-2 MAC 2

~]^ E19 JP

TS2 L

—

^^1^7^ CB-2RDB

8E-0547

Figure 9-23

Output Control Function Decoder

9-64

Read/Compare Logic

9.11.8

The Read/Compare logic consists of 12 Exclusive-OR gates and the OC-1 R/C ERROR flag (flip-flop). The 12 bits of
data from the Memory Data Bus (data read from memory) are Exclusively-ORed with 12 bits of data from the Data
Register (data read from tape). During the data break, at TP3 time, if the data from memory is different from data

R/C ERROR flag is set and CA incrementation stops. Tape motion continues until
LRC strobe is obtained at End of Record. RE-1 DEN 5 H and RE-1 DEN 8 H are used to enable a gate on the

read from DECmagtape the SC-1

outputs of the Exclusive-OR gates for the four most significant bits to prevent them from causing a Read/Compare

when a 9-track transport is selected. RE-1 R/C ENABLE is always high when a Read/Compare function is

Error

selected by the program. Refer to D-TD-TM8-E-1, sheet 2, for the timing during a Read/Compare operation.
9. 11 .9

Write Data Select Logic

The Write Data Select logic selects 6 or 8 bits of data from memory to be written on DECmagtape (Figure 9-24). To
write on a 9-track transport, the gates labeled C on Figure 9-24 are enabled by CB-1
9 H to apply 8 bits of data

from the Data Buffer Register to the selected transport (see D-TDTM8-E-1, sheet 8, for timing).

When writing on a 7-track transport, CB-1 WR 1st 7 H enables the gates (labeled B in Figure 9-24) for the six most
significant bits

and then the gates (labeled A

Figure 9-24) are enabled by CB-1

WR 2nd 7 H for the six least

significant bits. The control signals for the gates originate in the control logic shown in Figure 9-46. The outputs to

the transport are limited to O.OV and +3V levels by the diode and resistor networks tied to the output lines.

9.12

TM8-E REGISTERS (M8327)

The TM8-E Registers are used to address memory, count the words in a data transfer, select DECmagtape operations,
and generate command signals for the TM8-E control logic and the TU10 Tape Transports. Each of the registers used
in

the TM8-E are discussed in the following paragraphs; the Status Register is discussed with the Transport Status

and Control logic in Paragraph 9.13.1.
9.12.1

Data Buffer Register and Multiplexer

The Data Buffer Register and Multiplexer (Figure 9-25) provides temporary storage for data manipulation (transfers
and Read/Compares). Inputs to the Data Multiplexer come from memory (MD

- DATA 11), or from the tape (CRD

(DATA

through MD 11), from the AC

through CRD 7). The Data Multiplexer is a 74153 IC (refer to

Section 7 for logic diagram, truth table and pin locations) which selects one of the four data inputs to be applied to
the Data Buffer Register. CB-2 DB MPX A and CB-2 DB MPX B controls the selection of data that is supplied to the

Data Buffer Register. Table 9-17 shows the levels required to load the Data Buffer Register for each operation. CB-1

DBC

and CB-1 DBC 2 are used to clock the output of the multiplexer into the Data Buffer Register. The Data
1
Buffer Register is two 74174 ICs (refer to Section 7 for truth table, logic diagram, and pin locations) each containing
six flip-flops that are set or cleared by the input from the Multiplexer. The contents of the Data Buffer Register are
applied to the Read/Compare logic, to output control logic, and to an 8235 IC (refer to Appendix A, Volume 1, for

truth table, logic diagram and pin locations) as shown
instruction

executed, the data

Figure 9-26. During a Read operation or when a

transferred to the Data Bus. During a

RDBR

Read operation, data is transferred to a

memiory location selected by the Current Address Register during Single Cycle Data Break. If the RDBR (6717)
is executed, the data is transferred to the AC via Data Bus. Refer to the flow diagram (Figure 9-20 and
Figure 9-15) for an illustration of this operation. The timing diagrams for these operations are shown in Drawing No.

instruction

D-TD-TM8-E-1, sheets 1 through 9.
9.12.2

ACInput Gating

The AC Input Gating (Figure 9-27) is used as a buffer between the Data Bus (inputs from the AC) and the TM8-E
Registers. OC-2 AC ENABLE L is asserted (low) any time a 670X instruction is executed by the program to transfer
data from the AC to the TM8-E Registers. The outputs of the NAND gates enabled by OC-2 AC ENABLE are
applied to the Command, Data, and Function Registers, and to two 74174 ICs, which provide a Holding Buffer for
inputs from the AC. The 74174 ICs (refer to Section 7 for truth table, logic diagram, and pin locations) are 6-bit
buffer registers for inputs to the WC and CA Registers and bits 6 through 8 of the Command Register. SC-1 B TP3 is
used to clock the outputs of the NAND gates into the AC Holding Buffer Register. The outputs of the AC Holding

Buffer Register are applied to the

WC and CA Registers (Figure 9-28).
9-65

«H4Hii

(

wv— in

(—

<>-WHii

(

WV— lO

>—

<»-wHii

-^\A/'v

«'-rtHii

'"-KHh

— lO I—WV— lO MW^— lO
(

(

Z-Aw Z_Ac Z_Aw ZAci Z_AS
#-Wv— in
+

••-f^i'

<'-MHii

h-V^/^

Z_Aui
+

— lO

(

h-^/VV

<^-+4Hii

— lO

Z_\.S

(

i-f/\^

— lO

Z_aS

(»--Wv— in ^A/v— in

+
i-c

C/)

Q
-o

o
cc

9-66

P/0 M8 32 7

MDO

CB-2 DB MPX

RE-1

li_i

SAC H'
SC-2

MPX

B H

P/0 M8322(CB-2)
CB-1 R

RD2 H'
RE-1

MD1L

SAC H'
SC-2
R03 H'
1

74153
E13

1st

7 L

N
—
—
—^E19*yV

CB- 2 MAC2 H
CB-22 B TP3 H
CB
WRITE H

CB-1 R 9 CH L

MPX

OC-2 LDBR L

RE-3 MPXO H

MD2

l2_i

RE-1

SAC 2 H'
SC-2
RD4 H'

RE-3 MPX

MPX

RE-3 MPX2 H

BAC 3 H'

E12

RE-3 MPX3 H

SC-2 RD5 H-

MPX

RE-3 MPX4 H

RDP H-

RE -3

BAC 4 H"
E20 )

74153

SC-2 RD7 HSC-2 RD1 H-

MPX

•*-H

MPX

SC-2 RD6 HSC-2 RDO H
N RE-1 BAC 5 H-

J E20)y

MPX5

RE-1

MD4L

74153

RE-1

MD3L

05 L

E26

5
14

P/0 M8322(CB-2)
RE-1

MD6L

MPX

BAC 6 H"

MD7L

SC-2 R D2 H-i— 74153
E25
N^RE-1 BAC 7 H

CB-1 R
n 2nd7
cna
i_
L

— N Lor ^
H^E19^^)>-^^

CB3-1 R 9 CH

—

CB-2

"ir-o LDBR
not?
OC-2

MPX
SC-2 RD3 H-i-

(

CB-2 MAC2
CB-2 B TP3
CB-1 WRITE

RE-3 MPX6 H

MD8 L

RE-1
BAC 8H'

MPX

RE-1

D B

\— DB6

RE-3 MPX7 H

RE-1

I— DB7

RE-3 MPX8 H

MD9 L

SC-2 RD4 H-iRE-1 BAC 9 H-

SC-2 RD5 H-i:

RE-3 MPX9 H

MPX

RE-3 MPX10 H

RE-1

RE-3 MPX11 H

RE-1
I— DB11

E44

DB10

12_A

RE-1

MPX

BAC 10 H'

(RE-1)

MD11 L

74174

9
14

MDIOL

— RE-1
DB8
RE-1
— DB9

74153
E43

SC-2 RD6 H-C
RE-1 BAC 11 H
SC-2 RD7 H-T

74153

E42

MPX

^Same AND gate

shown twice on ttils

CB-2 DB MPX A H(RE-3)

Figure 9-25

Input Data Multiplexer and Data Register

9-67

illustration.

Table 9-17

Data Multiplexer Selection Levels
Operation

CB-2 DB MPXA H

CB-2 DB MPXB H

(pin 14)

(pin 2)

low

Load Data Buffer

low

Write

high

low

Read 7 Channels
Read 9 Channels

low

high

P/0 M8327

RE -1 FRO L

—

RE -1 DBO
RE-t FR1 L
RE-1 FR2 L

DATA

—

RE-I DB1

—

8235
E4

RE-1 DB 2

DATA

DATA 2
DATA 3

RE-1 FR3 L

RE-1 DB 3

(RE-1)

RFSR L
1

RE-1 EN CHECK CHAR L

READL

^^
^ CB-2
MAC 2 H

+ 5V

P/0 M8321 ^7
°^'^
qN.

RE-1 DB 4

RE-I GO

C19

•

J TS2

C
E1

Ap
y OC-2
RDBR

8235

SC-I 7 CHAN + DEN5L
'

DATA 4

—

RE-I DB 5

^RDB l'

DATA 6

E23

,RE-1 DB 6

DATA 5

DATA 7

+ 3V

—

RE-1 DB 7

(RE-1)

+ 3V
1

RE-1

DBS

RE-1

DB9

RE-I

DB10

DATA 8
1

RE-I DB11

8235
E35

DATA 9
DATA 10

DATA

(RE-1)

T
+ 3V

8E-0569

Figure 9-26

Data Register and Function Register Output Multiplexer

9-68

P/0 M8327(RE-1)

BTP3

*RE-iB
DATA

"AGO H

*RE-1B
DATA

HBAC

<•

HBAC

»RE-1B
AC 2H

DATA 2 L

*RE-1B
"AC 3H

DATA 3 L

:=4ED
DATA

HBAC OH

HBAC 2H

74174
E9
DD

HBAC 3H

*RE-1B

AC 4H

4 L

DATA 5 L

l^yX-

HBAC 4H

*RE-1B
AC 5H

HBAC 5H

TO WORD COUNT AND
CURRENT ADDRESS REGISTERS

+ 3V

*RE-1B

AC 6H

DATA 6 L

E24
DATA

)

»
*RE-1 B
AC 7 H

7 L

E24

HBAC 6H

HBAC
DB

HBAC 7H

TO BITS 6-8 OF

COMMAND REGISTER

*RE-1 B
DATA

"
DATA

r^y r
E41

)

9 L
E41

HBAC 8H

74174

E39
DD

HBAC 9H

*RE-1 B
"AC )0H
'»

*RE-1B
AC 9H

DATA 10 L

DATA

AC 8H

E41

—

^
"'

HBAC 10H

.*RE-1B

N
d
E41
q
y

)

r^^c^^"
*

HBAC 11 H

AC ENABLE L
+ 3V

^OUTPUTS TO COMMAND REGISTER, DATA REGISTER AND FUNCTION REGISTER.

Figure 9-27

AC Input Gating and Holding Buffer Register

9-69

OC-2 LWCR L

P/0 M8327(RE-3)

RE-1
HBAC OH
RE-1
HBAC H

RE-2

OC-2 CWCR L
<!>

WCO

DATA OL

RE-1
HBAC 2H
RE-1
HBAC 3H

RE-2CA

74197

>
TA

RE-1

7^:^ RE-2 CA

8235
E2

DATA IL
DATA

DATA 3L

—rp

i-L

HBAC 4H
RE-1

E21

HBAC 5H

t>^

RE-2
CA 4'
RE-2
CA 5

RE-1

74197

HBAC 6H

E22

>
rj

RE-1

HBAC 7H

,;{^

DATA 4L

8235

DATA

E17

DATA 6L

RE-2.
CA 6

RE-27'

T"?

OC-2 RWCR L

RE-1
HBAC 8H
RE-1

HBAC

:>o-

WC
74197

E38

E-1

P/0 M8322(CB-1)

H BAC

RE-2
CA 8
RE-2
CA 9'
RE-2
CA 10
RE-2.
CA 11

^E37l

RE-1

HBAC

E37

CB-2
MAC

RE-2
CA 00
I

___
ra-i cparr u
BLRCS
L CB-1 SPACE H
_

p
I

DATA

8235
E33

YTJ

RE-2

CA 01

SC-1 FM L
[£J[)°~
^1

RE-2 CAO L

RE:-2 ma OL

[eJ~V" RE-2 ma 1L

'*~~Te"i~V- RE-2 MA 2L
RE-2 MA 3L

RE-2 CA 2L
RE-2 CA 3L
RE-2 CA 4L
•RE-2 CA 5L

RE-2 MA 4L
'

[eIs)^- RE-2 MA 5L

^^^l^tiieV- RE-2 MA 6L
[e16)o- RE-2 MA 7L
^^

RE-2 CA 6L

RE-2 CA 7L
RE-2 CA 8L

RE-2CA 9L
RE-2 MA 8L
RE-2 CA 10^1
''^

l^g)^

^^"2 ^'^ ^^

[e32)o- RE-2 MA 10L

RE-2 MA 11L

Figure 9-28

Current Address and Word Count Registers

9-70

DATA 9 L

9.12.3

Current Address (CA) Register

The Current Address Register (Figure 9-28) is a ripple counter that sequentially addresses locations in memory by
incrementing before each data transfer. The CA Register is loaded with a 12-bit address that is one less than the
desired starting address. The CA Register is incremented by the leading edge of SC-1 COUNT CA L (Figure 9-28)
each time a BRK RQST is made by the TM8-E. CB-2 MAC ACC is asserted after a BRK RQST is granted to the
TM8-E and removes the SC-1 COUNT CA L signal from the CA Register. The CA Register is not incremented when
SC-1 COUNT CA L goes high because the counter increments only a high-to-low transition of the signal. The CA
Register is loaded by the LCAR instruction before each DECmagtape operation and must not be loaded during
CNTL BSY.
The output of the CA Register is applied to the MA lines when CB-2 MAC 1 H enables the NAND gates (Figure
to select a location in memory which contains data to be read or a location to store data from the
DECmagtape. The contents of the CA Register are also applied to an 8235 IC (refer to Appendix A of Volume 1 for

9-28)

RCAR instruction is executed by the
CA Register is read by the program during error check routines and maintenance operations to
determine what address in memory generated an error. The CA Register is cleared by an CCAR instruction.

truth table, logic diagram, and pin locations) for transfer to the AC when an

program. The

9.12.4

Word Count (WC) Register

The Word Count Register is a ripple counter that (Figure 9-28) counts the data words transferred to or from the
DECmagtape during data transfers and counts the records during space operations. The WC Register is loaded from
the AC with the 2's complement of the number of words to be transferred or number of records to be spaced when a

LWCR instruction is executed by the program.
The output of the WC Register is applied to an 8235 IC (see Appendix A, Volume 1, for truth table, logic diagram,
and pin locations) and is transferred to the AC when an RWCR instruction is executed by the program. When bit
is applied to the CB-1 WCOV flip-flop (Figure 9-21).
makes the transition from the high to low state. RE-2 WC
CB-1 WCOV indicates to the control logic that the data transfer is complete (the specified number of words have
been transferred). Word Count is incremented during the Break cycle when SC-1 COUNT WC makes a high to low
transition by asserting one of the following:

9.12.5

CB-2 MAC ACC L during a Read or Write operation.
C LRCS L during a CB-1 SPACE operation if a File Mark is not detected.
Function Register

The Function Register (Figure 9-29) is loaded with 6 bits of data from the AC by an LFGR instruction. The 6 bits
determine the function (Table 9-12) the

TU10 Transport is to perform and provide control signals to initiate

DECmagtape operations. The Function Register consists of two 74175 ICs (refer to Section 7 for truth table, logic
diagram, and pin locations) which contain the flip-flops that are set or cleared by bits from the AC. The three most
significant bits of the Function Register (FRO through FR2) are applied to the output control Function Decoder
(Figure 9-23) and the control Function Decoder (Figure 9-39). FR3 through FR6 are applied to the control logic to

accomplish the functions shown

Table 9-12. The CB-3 MTTF input to the 74175 IC clears the three

significant bits FR4 through FR6 when the CB-3

least

MTTF (JOB DONE) flag is set at LRCS time (Figure 9-42).

The outputs of the Function Register are also applied to an output multiplexer (Figure 9-28) for transfer to the AC
when an RFSR instruction is executed by the program. The 8235 IC (refer to Appendix A, Volume 1, for truth
table, logic diagram,

and pin locations) transfers the Function and Status to the Data Bus for display in the AC or
RFSR L is asserted. RE-1 RFSR L is asserted when an RFSR instruction is

evaluation by the program when RE-1

executed by the program.

NOTE
The Function

must be the last register loaded
because it contains the GO bit, which initiates CNTL BSY,
Register

PRESET, and SET to start the tape transport.
9-71

P/0 M8327(RE-1)
E21

OC-2

LFGR L

H>
RE-1

RE-1

RE-1 BAG

RE-

BAG 2 H

RE-

BAG 3 H

FRO H
FRO L

RE-1 FR1 H

RE-1 FR1 L

E14
74175

RE-1 FR2 H
RE-1 FR2 L

(RE-1)

RE-1 FR3 H
RE-1 FR3 L

RE-1 ENABLE CHECK CHAR L
RE-1 GO H

RE-t GO L
RE-1 EMA INC ENABLE

CB-3 MTTF L

Figure 9-29

9.12.6

Function Register

Command Register

The Command Register (Figure 9-30) consists of nine flip-flops and a 3-bit ripple counter that are loaded from the
AC when an LCMR instruction is executed by the program (Table 9-11),
The four flip-flops that receive RE-1 BAC
Section

7, for truth table, logic

through RE-1 BAC 3 (Table 9-11) as inputs are on a 74175 IC (refer to

diagram, and pin locations). Three of the flip-flops on this IC generate SEL

through SEL 2 for indication of selection of one of the TU10 Transports and provide an input to the Buffered

Command Register for TU10 Transport selection (Paragraph 9.12.7). AC 03 is used to select odd or even parity
mode for the TU10 Transport. If this flip-flop is in a state, even parity is selected and C PEVN L to the TU10
Master System is asserted.

RE-1

BAC 4, RE-1 BAC 5, and RE-1 BAC 9 through RE-1 BAC 11 are applied to a 74174 IC (refer to Section 7 for

truth table, logic diagram, and pin locations), containing six flip-flops that are loaded by the inputs from the AC

(Table 9-11).

The remainder of the bits from the AC (AC 6 through AC 8) are applied to a 74197
1,

(refer to Appendix A, Volume

for truth table, logic diagram, and pin locations containing three flip-flops to select a

memory field during data

The 74197 IC is a 3-bit ripple counter that is incremented by SC-1 EMA INC L if bit 6 in the Function
Register is set (1). The output of the 74197 IC (RE-1 EMA 0- RE-1 EMA 2) is applied to the OMNIBUS when CB-2
MAC 1 H enables the three AND gates (Figure 9-0) during a Single Cycle Data Break. Refer to Paragraph 9.13.3 for a
discussion of the SC-1 EMA INC L signal generation.

transfer.

The contents

of the

Command Register are transferred to the Data Bus when the progam executes an RCMR

instruction to assert the control input of the 8235 ICs (Figure 9-30). The Command Register is cleared by CB-3 CLR

ALL L (Paragraph 9.1 1.4).
9-72

C
C3

E
E
o

o
o
CO

X
o
<
CD
—
ft:

X X
<M

<
—

o
< <
oo
CD
— —

LlI

ft:

X
in
o
<

UJ
q:

X
o

o
<

UJ
q:

lij

LU
q:

9-73

9-74

9.12.7

Buffered Command Register (BCM)

The Buffered Command

Register (Figure 9-30) receives RE-1 SEL
through RE-1 SEL 2 as inputs from the
command register. RE-1 B SEL 1 through RE-1 B SEL 2 out of the BCiVI are applied to the TU10 IVIaster System to
select a transport and provides an input to a comparison circuit to determine when a new transport has been selected

(Figure 9-43). CB-2 CHG TRANS L

is asserted if RE-1 SEL
through RE-1 SEL 2 from the command register and
through RE-1 B SEL 2 from the Buffered Command Register are different; thus CB-2 CHG TRANS L

RE-1 B SEL
is

asserted

new transport is selected by the program. The output of the BCM holds the select lines to the

previously selected transport in the same state until

the

CSDWN L (settled down)

obtained from the transport. Then

BCM is loaded by RE-2 LBCM L to select a new transport. Thus the BCM allows the program to load the

command and select a new transport without deselecting the previously selected transport before it stops.

M8323 TRANSPORT STATUS AND CONTROL MODULE

9.13

The Pt/18323 Transport Status and Control Module consists of the Main Status Register (Table 9-13), Second Status
Register (Table 9-14), logic for generation of timing and control signals, and a Data Multiplexer to transfer the

contents of the Status Registers to the Data Bus.

9.13.1

Main Status Register

The logic elements that make up the Main Status Register perform as follows.
9.13.1.1

SC-2

ERROR Flag Logic - The SC-2 ERROR flag (Figure 9-31)

attempts an illegal function or if SC-2 SEL ERROR
set after CB-3

b.
c.

d.
e.
f.

9.13.1.2

set

immediately

asserted by the selected transport. The SC-2

the program

ERROR flag is

MTTF is set if any of the following errors are detected.

EOT
BOT

DATA LATE
PARITY ERROR (LRCE, CRCE, or VPE in Second Status Register)
RECLNG INCORRECT

EMA 7 INC ERROR (Second Status Register)
R/C ERROR
File Mark (FM)
Illegal

Function Logic - The SC-2

ILLEGAL FUNCTION flip-flop (Figure 9-32) is set if the program

attemipts any of the following SC-2 ILLEGAL FUNCTIONS:

The program executes an LCMR, LFGR, or LDBR instruction when the SC-1 CNTL BSY flip-flop is set
(Paragraph 9.13.5).

Selection of any density other than 800 bpi if a 9-track transport is selected.

Selection of a Space Reverse operation when the selected TU10 Transport is at BOT.

Selection of Read, Read/Compare, or Space Forward after a Write or Write End of File operation if the

same transport is used.
e.

Changing to a transport that is not ready (C TUR is false) and SC-1 PRESET is issued.

Attempting a Rewind when tape is at BOT.

Any Write command issued to a transport with write lockout set.

9-75

P/0 M8323(SC-2)
CB-1 REWIND L

;=:EE>
SC-2
BOT L

SC~

CONTROL BUSY

E23

nr^

CB-1 SPREV L-d

SC-2
SP REVBOT H

CH L

SC-t C 7

E31

RE-1

DEN 8 H
SC-1

PRESET
E31

C
E28 V-

SC-1 TUR L
CB"3
CHG TRANS L-

P/O

SC-1
CONTROL
BSY L

M8321(0C-2)

E19

iOC-2 LCMR
|0C-2 LFGR

—d E24

\^y\

OC-2 LDBR

ILL.

FUN.
(MS)

C^^^O

SC-1
CLR STATUS L

+ 5V

E31
I

P/O

,^r.

M8322(CB-1)

CB-1 WRI

FM— y
CB-1 WFM
I

P/O

^E>
SC-1

PRESET H

CB-1 SP

FWD L

nE42>

QLL^

R/c L

WRLL-

M8322 (CB-2)

CB-1 REEAD L
CB-

,»

E32

^^O
y

P/0M8322(CB-1)
I

CB-1

WFM L

^
^—

j^'^'^y

CB-1 WRITE L

E30 JO-

E35

SC-1 SET H-

CB-3 CHG

CLEAR L
SC-1

PRESET H
I

Figure 9-32

Illegal

Function Flag and Control Logic

9-76

SC-2
ILLEGAL
FUN. L

Data Late Logic - The SC-1 Data Late (Figure 9-33) flip-flop is set if the computer fails to service a BRK
RQST before the next word is transferred to or from tape. A counter made up of flip-flops A, B, and C (Figure 9-33)
counts the Read Strobe or Write Strobe pulses generated by the TU10 each time a character is read from or written
on tape. SC-1 WRS L or SC-1 B RDS L clocks the three flip-flops (A, B, and C). CB-2 MAC ACC L (Figure 9-33) is
asserted after a BRK RQST is granted to the TM8-E by the processor to clear the counter and prevent the SC-1
DATA LATE flip-flop from setting when the next SC-1 WRS or SC-1 B RDS pulse occurs. If a 9-track transport is
selected and CB-2 MAC ACC is not asserted by the time the next SC-1 WRS or SC-1 B RDS pulse occurs, the set side
of the B flip-flop causes SC-1 DATA LATE to set. The set output of the B flip-flop is applied to the clock input of
SC-1 DATA LATE if the NAND gate tied to the set output is not disabled by C 7 CH L or RE-1 DEN 5 H. When a
7-track transport is selected, SC-1 DATA LATE sets after three SC-1 WRS L or SC-1 B RDS L pulses if the counter
has not been cleared by CB-2 MAC ACC L, Note that a 7-track transport requires only one Data Break cycle to
transfer two data characters to or from tape. The SC-1 DATA LATE flip-flop is always cleared during a Space
operation since no data is transferred. SC-1 DATA LATE is also cleared when a File Mark (C FMK) is detected
during a Read operation or by CB-3 CLR STATUS L.
9.13.1.3

P/0 M8323 (SC-1)

CB-1

WCOV
+5V

E12
A

+5V

E1
C

SC-1

WRS L

—
C

WRS L

——

—
C

"-M

E11

sc-t

DATA
LATE

TEST **

(MS)
C

—

SC-1

DATA
LATE L

CB-2

MAC ACC L
+ 3V

—Ol E10 )0—
C 7 CH L

RE-1 DEN 5 H

CB-3 CLR STAT

USL—P>SC-2 SPACE H

CB-2

~^ EiB>-^

B TP;

CB-1 BRK RQST H

J +3V —^ E20^O
1

RE-2 CAO H

E2
INC

CB-3 CLR STAT

EMA

"'"-[>
RE-1 GO H

SCto— EMA 7 INC ERR H
1

RE-1 EMA INC EN

RE-2 EMA

7hI;JB>^
D

EMA 7 INC ERR H

E13

EMA
INC

ERROR

«SAME INVERTER
**TEST POINT NOT ON THE TOP OF CONNECTOR

(SS)

Figure 9-33

Data Late and EMA Increment Error Flags

9-77

SC-1
EMA 7 INC ERR L

tt:_i-

*—
CO

ro
CO

S
o

T T
_i

v._i

Quj

< iu<r
UJ
cc

tEQ.

- -5
O
OQ (Do
O O
'

m
+-"

Q o

9-78

Record Length Incorrect Logic - The SC-1 RECORD LENGTH INCORRECT flip-flop (Figure 9-34) is set
when the number of data words read from the tape and the contents of the WC Register are different (record too
long or too short). As previously stated, the WC Register is loaded with the 2's complement of the number of words
to be transferred. Word Count is incremented during the data transfer. The WC Register should contain all Os and
generate CB-1 WCOV L before the LRC character is read from tape. If C LRCS H occurs before CB-1 WCOV, gate
E33 (Figure 9-34) is enabled, and the SC-1 RECORD LENGTH INCORRECT flip-flop sets. This condition occurs if
the WC Register has been loaded with a Word Count greater than the number of words in the record (record is
short). To detect a record that is too long, a counter made up of flip-flops A and B (Figure 9-34) counts the RDS
pulses that occur after CB-1 WCOV H. If two or more C RDS L pulses occur after CB-1 WCOV and there are no C
LRCS L or C CRCS L pulses, the SC-1 RECORD LENGTH INCORRECT flip-flop sets. This condition occurs if the
Word Count Register is loaded with a Word Count less than the number of words transferred (record is long). Note
that flip-flop A is cleared by C CRCS L or C LRCS L so that SC-1 RECORD LENGTH INCORRECT is not set
9.13.1.4

during the termination of a normal operation.

SPACE H and C FILE MARK L keep the SC-1 RECORD LENGTH INCORRECT flip-flop cleared during a
File Mark operation. CB-3 CLR STATUS L clears the SC-1 RECORD LENGTH INCORRECT
flip-flop when the Status Register is cleared by a CLF instruction.
CB-1

Space or Write

9.13.1.5

Tape Rewinding - Tape Rewinding (C

RWS L)

asserted (Figure 9-36)

the selected transport

rewinding.

End of Tape - End of Tape (C EOT) is asserted if the End of Tape reflective strip has been detected by
theTUlO (Figure 9-31). If C EOT is detected before CB-3 MTTF (JOB DONE) is set, the SC-2 ERROR flip-flop sets
9.13.1.6

and the Main Status Register must be read by the program to determine the cause of the error.
9.13.1.7

Beginning of Tape — Beginning of Tape (C BOT)

asserted when the

BOT reflective strip is detected by

ERROR flip-flop (Figure 9-31) sets.

If BOT is detected before CB-3 MTTF (JOB DONE)
The Main Status Register must be read by the program to determine the cause of the error.

the TU10.

set, the SC-2

9.13.1.8

Read/Compare Error —The Read/Compare operation is discussed in Paragraph 9.1.8.

9.13.1.9

Parity Error - The SC-1

PARITY ERROR flip-flop (Figure 9-35) is set if the TU10 detects any of the

following errors.

b.
c.

C LRCE (Longitudinal Parity Error)
C CRCE (Cyclic Redundancy Check Error)
C VPE (Vertical Parity Error)

If SC-1 PARITY ERROR is set, the SC-2 ERROR flip-flop (Figure 9-31) sets when MTTF (JOB DONE) sets. SC-1
PARITY ERROR is cleared any time a File Mark is read from tape. During space operations, CB-1 SPACE H keeps
SC-1 PARITY ERROR cleared (Figure 9-35) to prevent generation of erroneous parity errors. Note that the C VPE
is

cleared by the next good word read from tape and will not be seen unless it occurs as the last word read from tape.

9.13.1.10

File Mark

(EOF) -The FILE MARK flip-flop (Figure 9-35) is set any time the TU 10 detects a File Mark

during a Space, Read, or Read/Compare operation (Paragraph 9.1).

9.13.1.11

Select

Remote -SC-1 SELR L (Select Remote)

(Figure 9-37)

OFFLINE (not ready). SC-1 SEL ERROR is set if SC-1 SELR L
9.13.1.12

File Protect

- File Protect

true

when the selected transport is

lost during data transfer operation.

when Write Lockout (C WRL L) is asserted by the TU10, indicating that

the selected transport has the Write Lockout ring removed. Transports without a Write Lockout ring will set the
ILLEGAL FUNCTION flag during SC-1 PRESET time (Figure 9-32) if they are selected for a Write or Write File

Mark operation.

9-79

P/0M8323(SC-1)

O D

LRCE L

E34
LRC

ERROR
(SS)
B RDS H

SC-1

LRC ERROR H
E19

C VPE L

—C D

E26

E34
VPE

ERROR

PARITY
ERROR

(SS)

(MS)

E31

RDS L

—oP])>

SC-1

—

SC-1 VPE H

PARITY

ERROR L

+ 3V1

SC-1 FM L

CRCE

SC-1 CRC

ERROR L

E35
CRC

ERROR
C
C

RDS

(MS)
L

CRCS L

E33

SC-1 CRC

ERROR H

+ 3V1

Figure 9-35

9.13.2

Parity Error Flags

Second Status Register

The Second Status Register is read using tlie RFSR lOT (Figure 9-14). This lOT transfers the condition of the
Second Status Register to the AC for evaluation by the program. The logic elennents in the Second Status Register
perform as follows.
9.13.2.1 EMA 7 Increment Error- RE-2 EMA 7 flip-flop (Figure 9-33) is set if the program tries to increment
from Field 7 to Field
(RE-1 EMA INCREMENT bit must be set). If RE-2 EMA 7 H (Figure 9-30) is applied to the
data input and RE-1 EMA INC L is asserted, the RE-2 EMA 7 flip-flop sets, which in turn sets the SC-2 ERROR flag
when CB-3 MTTF is set (Figure 9-31). Refer to Paragraph 9.13.3 for a discussion of the EMA INC logic. The Second

Status Register must be read by the program after CB-3 MTTF is set to determine the cause of the error.

9-80

Vertical Parity Error (C VPE) - The SC-1 VPE flip-flop (Figure 9-35) is set during a Read or
Read/Compare operation if the TUlO Master Systenfi detects a Vertical Parity Error and asserts C VPE L. SC-1 VPE
is cleared when the next good word is read from tape. If SC-1 VPE is set at the end of an operation, the last word in

9.13.2.2

the record was the one that set SC-1

VPE.

LRC ERROR -The SC-1 LRC ERROR flip-flop (Figure 9-35) sets if the selected TU10 detects an LRC
LRC character is read. The TU10 asserts C LRCE L when an error is detected and sets SC-1 PARITY
ERROR and SC-1 LRC ERROR.

9.13.2.3

error when the

9.13.2.4
it

ORG ERROR - The SC-1 CRC ERROR flip-flop (Figure 9-35) sets if the TU10 detects a CRC error when

reads the CRC character from tape. The TU10 Master System asserts C CRCE L when a CRC error is detected to

set the SC-1

9.13.3

CRC ERROR flip-flop and the SC-1 PARITY ERROR flip-flop.

Main and Second Status Register Multiplexer

The contents of the Main Status Register and Second Status Register (Figure 9-36) are applied to three 8235 ICs
(refer to Appendix A, Volume 1, for truth table, logic diagram, and pin locations). The 12 bits (Figures 9-9 and
9-16)

from the Main Status Register are applied to the Data Bus if an RMSR instruction is executed by the program

and the 4 bits from the Second Status Register (Figures 9-10 and 9-14) are transferred to the Data Bus if an RFSR
instruction is executed by the program. Note that 8 bits of the Function Register (Figure 9-29) are also applied to
the Data Bus when the RFSR instruction is executed by the program.

P/0 M8323

SC-2 ERROR L
SC-2

RWS L -

DATA

REWINDING L

DATA

8235

.DATA 3

0-3

SC-2 BOT L80 -1

CSELRL

o[^>c4^L^-y(SC-2)

+ 3V

SC-1 PARITY ERR L-

^DATA 4

SC-1 FM L-

DATA 5

4-7
SC-1

REC LENGTH INCORRECT L-

E21

^DATA 6

8235

DATA 7

SC-1 DATA LATE
'

(SC-2)
1

+3V

SC-2 EOT L-

SC-1 EMA 7 INC ERROR H-

CWRL L

SC- VP ERR HOC-1 R/C ERR L
SC- CRC ERR H
SC-2 ILLEGAL FUN LSC-1 LRC ERR H-

AND
SS

—

DATA 8
DATA 9

8-11

DATA 1

E37
8235

DATA 1

(SC-2)
i

OC-2 RMSR L
OC-2 RFSR L

Figure 9-36

Main Status Register and Second Status Register Multiplexer

9-81

7m1

^X
ro

r~
liJ

-r-Ol

1—

—

VvAr

3
Q.

H
LU

CO
tu
a.

CO
CJ)

A
—

*—B

9-82

9.13.4

Extended Memory Address Increment Logic

The EMA bits (6, 7, and 8) in the Command Register (Figure 9-30) are used to select one of the memory fields
during a Data Break operation

bit 6 in the

Function Register is a 1. When bit 6 is set, the PDP-8/E memory is

memory instead of 4K blocks (Table 9-12). To accomplish this the EMA bits must be
incremented when the last memory location (7777) in each field is addressed and SC-1 COUNT CA L is asserted.
The RE-1 EMA INC flip-flop (Figure 9-33) is set when the Current Address Register goes to all Os and RE-1 EMA
INC EN L is asserted (bit 6 in the Function Register is 1). The EMA bits in the Command Register are incremented
transition until the EMA bits are all Is (RE-2 EMA 7). When RE-2
in the CA Register makes a 1 to
each time bit
EMA 7 H is asserted, the NAND gate on the output of RE-1 EMA INC is disabled. If an attempt is made to
increment beyond Field 7, the RE-1 EMA INC ERROR flip-flop is set by RE-2 EMA 7 H and the set side of RE-1
EMA INC. The RE-1 EMA INC flip-flop is cleared at TP3 time of BRK RQST and remains cleared until RE-2 CA L
makes a high-to-low transition at the end of a memory field.
treated as continuous

9.13.5

Control Busy (CNTL BSY)

The SC-1 CNTL BSY flip-flop (Figure 9-37) is set by RE-1 GO and OC-2 B TP4 when bit 5 in the Function Register
is loaded with a 1. SC-1 CNTL BSY is cleared when MTTF (JOB DONE) sets at the end of an operation or by CB-3

CLRALL.
9.13.6

PRESET and SET Pulse Generator

Figure

9-37 shows the SC-1

PRESET and SC-1 SET pulse generation

multivibrators that generate a pulse on the output

when

The 74123 ICs are monostable
makes a high-to-low transition. The

logic.

the input signal

duration of the output pulse is determined by an external resistor and capacitor, i.e., C39 and R36,

PRESET is a 2.5-jus pulse (approximate time) that is triggered when the RE-1 GO bit (bit 5) in the Function
Register is set Note that C SELR L and C TUR L must be asserted to enable the gate when starting from a standstill

SC-1

SDWN L allows the RE-1 GO signal to trigger the 74123 IC CB-2
(false). If CB-3 CHG DIR or CB-3 CHG TRANS are asserted the
high
TRANS
are
both
CHG DIR or CB-2 CHG
SC-1 PRESET returns to the clear state, E2 is clocked, and
When
SELR
C
TUR
L.
wait
for
L
and
TM8-E must
C
outputs
triggered,
triggered. When the second 74123 IC
74123
IC
is
second
not
the
ERROR
flag
is
set
the SC-2
condition. In a continuous mode of operation, C

a 1.0-jus pulse

(approximate time) that is applied to the selected TU10 to initiate tape motion. The E2 flip-flop is

cleared by CB-3 CLR STATUS L, the SC-1 SET pulse, or the SC-2

9.13.7

ERROR flag.

Data Late Error Check Logic

The logic shown in Figure 9-38 is used to check the Data Late Error logic (Figure 9-33). The processor timing is
stopped at TP3 time by the assertion of SC-1 NOT LAST XFER and restarted by asserting SC-1 BUS STROBE.

The 74123 ICs are monostable multivibrators that are triggered on a high-to-low transition of the input signal to
generate an output pulse. The duration of the output pulse is determined by an external capacitor and resistor, i.e.,
C40 and R37. When the CKDL instruction is executed by the program, OC-2 IBCM L is asserted to trigger the first

74123 IC and generate a long timing pulse, which is ANDed with El flip-flop and applied to the OMNIBUS as SC-1
NOT LAST XFER to stop processor timing. El is cleared atTP3 time and the trailing edge of the first 74123 causes
the second 74123 IC to output a pulse. This pulse asserts SC-1 BUS STROBE L and restarts processor timing. During
the time processor timing was stopped, an attempt was made by the TM8-E to transfer data. The SC-1 DATA LATE

ERROR flip-flop (Figure 9-33) should be set, because the TM8-E would normally transfer several words in a time
period this long. If the SC-1 DATA LATE ERROR flip-flop does not set, this group of logic is not working properly.

9-83

P/0 M8323(SC-2)
E3

SC -2
NOT LAST XFER L

+ 5V

C40 <R37

OC-2

IBCM L

RE-1 60 H-

R35

C38

74123

ONE
SHOT
E8

74123

ONE
SHOT

+ 3V1

SC-2

=E>

BUS STROBE L

E3
t-3V
+ 3V

+ 3V

^
E19

CB-2

BTP3 H

Figure 9-38

Data Late Error Check Logic

P/0 M8322 (CB-1)
RE-1

CB-1

FROH

OFFLINE L

CB-1 REWIND L

rp^—

— CB-1
REWIND H

*-C E18>

CB-1
READ L

CB-1

?®>

RE-1 FR1 H -

R-H-R/C H

jB>^"

CB-1
R/C L

+ R/C-I-WR L

FR
8251

E43
(CB-1)

CB-1
WRITE L
f-CE39:

RE-1 FR2 H

CB-1

WFM L

CB-1
WRITE H
CB-1

Z^^^y^

CB~ 1

WFM H

E36 )0

CB-1
SP FWD L

R-l-R/C-fWR+WFMK L

r3i3>" R-fR/C + SP FWD
CB-1
SP FWD L

CB-1

CB-1
SP REV L

SPACE H
SP REV L
— CB-1

Figure 9-39

Control Function Decoder

9-84

M8322 CONTROL MODULE

9.14

The logic elements of the M8322 Control Module are described in the following paragraphs.
Control Function Decoder

9.14.1

The Control Function Decoder (Figure 9-39) is an 8251 IC that decodes the three most significant bits (FRO— FR2)
of the Function Register (Table 9-12) to set up the control logic for a TU10 Transport operation.

NOTE
This decoder

identical to the

output Control Function

Decoder (Paragraph 9.11.7).

The 8251 IC is a BCD-to-Decimal Decoder (refer to Volume 1, Appendix A, for truth table, logic diagram, and pin
numbers) that decodes

bits

FRO through FR2 and produces a low on one output line of the IC for each 3-bit

combination, i.e., IOO2 causes pin 9 to be low and indicates a Write operation. The outputs of the IC are NORed to
generate one signal to represent a combination of operations, i.e., CB-1 SP REV L and CB-1 SP FWD L are NORed
to generate CB-1 SPACE H, to reduce the number of signals that are applied to elements of the control logic.

9.14.2

Data Break Request Logic

Figure 9-30 shows the logic used to
flip-flop

cleared and CB-1

make a BRK RQST during data transfer operations. The CB-1 BRK RQST
is asserted when the following conditions exist during Read, Write, and

BRK RQST H

Read/Compare operations.
a.

Write operation and SC-1

SET H are asserted for the first CB-1 BRK RQST at the beginning of a Write

operation.

CB-1 WRITE

1st 7 H

low and SC-1 WRS L (write strobe) is asserted during a Write operation. Refer

to Paragraph 9.14.10 for origin and discussion of these signals.

If CB-1

If an

READ 9 or SC-2 READ 2nd 7 is asserted (Figure 9-35) during a Read operation.

SBRM instruction (for maintenance only) is executed by the program.

Note that the CB-1

BRK RQST flip-flop

set for

only Write, Read, or Read/Compare operations, which are the

BRK RQST is set and CB-1 BRK RQST H is negated by CB-1 MAC
ACC L at TP1 time when the BRK RQST accepted by the processor. The BRK RQST flip-flop negated by SC-1
DATA LATE, CB-3 CLR ALL, RECORD LENGTH INCORRECT, or CB-1 WCOV RE-1 ENAB CHK CHAR not
cleared at the beginning of each data transfer operation by SC-1 PRESET H so that SC-1 RECORD
asserted. E24
LENGTH INCORRECT, CB-1 WCOV, or SC-2 ERROR can be reported during the operation and stop data transfers
only operations requiring data transfers. CB-1

these errors occur.

Word Count Overflow Logic -The CB-1 WCOV flip-flop (Figure 9-41) is set by RE-2 WCO L when bit
the WC Register makes a high-to-low transition (Figure 9-29). The set side of CB-1 WCOV is applied to NAND

9.14.2.1
in

ENAB CHK CHAR L. If bit 4 in the Function Register (Table 9-12) is 0,
ENAB CHK CHAR is high and CB-1 WCOV (Figure 9-40) sets E24 flip-flop which causes CB-1 BRK RQST to
negate and stop data transfers. If bit 4 in the Function Register is a 1, RE-1 ENAB CHK CHAR L is asserted and
CB-1 WCOV does not set E24. This allows two more data breaks to transfer the CRC and the LRC character on a
cleared by CB-3 CLR STATUS when a CLF instruction is
Read from a 9-track transport to memory. CB-1 WCOV

gate E32, which has as its other input RE-1

RE-1

executed by the program.

9-85

P/0 M8322(CB-1)
RE-1
GO H

CB-1
-WCOV H

E32 p
|__y +3V

RE-1
N CHECK

E40
RE-2
WCO H

CHAR L

q E28 \>

Of
I

SC-2 ERROR L

+ 3V-

CB-3 CLR
STATUS L

CB-1 OVER L

E24

CB-2
MACC ACC L

SC-1 REC

LENGTH INCORRECT H

CB-1 FINISHL^

E12

SC-1 PR ESET H

<«

g ^'3>

\
\_4_^^V°

+3V

E38^

r]>0

CB-3 CLR ALL L-

SCRE-

SET H

WRITE H

OC-2 SBRM L
CB-1 READ 9 CHL

CB-1 READ 2nd 7 L
CB-1 WRITE

SC-1 WRS L

\y^
Figure 9-40

9.14.3

Data Break Control Logic

Data Break Priority Logic

The priority of the TIVIS-E (Figure 9-41) is established by removing one of the A jumpers (A0-A5) and installing
one of the B jumpers (B0-B5); thus to establish a

priority (the highest priority) for the TM8-E, remove AO and
By this action all five NAND gates are disabled and the output of E9 is high, which enables E21. This
enables the set side of E26 to be applied to the CB-2 MAC 1 and CB-2 MAC 2 flip-flops and allows the TM8-E to
begin a Data Break operation at TP4, because the TM8-E has been assigned the highest priority. No other peripheral
using the Data Break Interface can have its AO jumper removed and its BO jumper installed. Note that when NAND
gate E34 is enabled at TS4 time, DATA
line is low (the TM8-E BO line is in place). Since all of the other
install

BO.

peripherals are monitoring the Data Bus, one of the

NAND gates in their priority logic

enabled and their BRK

RQST is not accepted.
As a further example, consider what happens if the TM8-E ranks third in the priority structure. This priority is
established by removing jumper A2 and installing jumper B2. Because jumpers AO and A1 are left in place, two other
peripherals can keep the TM8-E from making a
RQST. If the second highest priority peripheral has a BRK

BRK

RQST at the same time as the TM8-E, its interface brings the DATA 1 line low during TS4 and NAND gate E5B is
enabled. The output of E5B causes the output of E9 to go low and disable AND gate E21. This prevents the set side
of

E26 from setting CB-2 MAC 1 and CB-2 MAC 2 until the other peripheral completes its Data Break operation. As

implied, priority decreases from

through 1 1, and the TM8-E is assigned any priority between
the correct A jumper and installing the correct B jumper.

9-86

and 5 by removing

Wen

s
w
CD

Sh
0(/)
*

ro
OCT

* CO

?^«t

ODUJ

CD LJ

CJit
1

oa:

* QQ

OCT

« CD

c
o

-o

O
OJ
C>J

ro
00

9-87

^t-

m m
"u. mijj

;

o
o

S6
X

.^ a1

fr
iij

o
—
m
o

UJ
05

Q
00
O

m
o

Q(^(^

O
CVJ
CVJ

ro
CO

9-88

CM
cb

9.14.4

Processor Control Logic

The logic shown in Figure 9-41 is used to control the PDP-8/E processor during a Single Cycle Data Break operation.
If

E21

enabled by the priority logic and the set side of E26, CB-2 MAC

and CB-2 MAC 2 are set to assert the

OMNIBUS signals (the OMNIBUS signals are explained in Chapter 9 of the PDP-8/E & PDP-8/M Small Computer
Handbook) and take control of the processor for a Single Cycle Data Break operation. Note that MA, MS is not
asserted until TP1 time. CB-2 BREAK DATA CONT L, which controls direction of data flow on the Data Bus, is
controlled by READ L. During a Read operation, CB-1 READ L is asserted and data is transferred from tape to
memory. During Write and Read/Compare operations, CB-1 READ L is high to transfer data from memory to the
TM8-E. CB-2 MAC
and CB-2 MAC 2 are cleared by the output of AND gate E21 at TP4 time if BRK RQST is
removed. CB-1 BRK RQST (Figure 9-40) is cleared by CB-2 MAC ACC L at the same time CB-2 MAC and CB-2
1

MAC 2 are set to start a Single Cycle Data Break, The TM8-E continues to make break requests and to transfer data
to or from memory until the WC Register reads all Os (WCOV).
9.14.5

MTTF (JOB DONE) Logic

MTTF (JOB DONE flag shown in Figure 9-42) is set by one of the following conditions to indicate that a specified
function is complete or cannot be performed.

C LRCS (LRC character read from tape at the end of a record) during a Read, Read/Compare, Write, or

Write File Mark operation.

The C LRCS is read from tape during a Space operation.

The selected transport is given a command to rewind and C RWS is asserted by the selected transport to
indicate Rewind has started.

The selected transport is given the CB-1 OFFLINE command and C SEL ERR L is asserted by the

File Mark, EOT, or

WCOV are encountered during a Space operation.

selected TU 10.

9.14.6

lOT LDBR is executed by the program and CB-1 WCOV L is asserted.

Interrupt Logic

The Interrupt logic (Figure 9-42) asserts INT RQST L, which is serviced by the processor (i.e., perform a flag check
routine) when one of the following conditions exist.
Bit 6 in the Command Register (Interrupt Enable on SC-2

set (Figure 9-32).

ERROR flag) is a 1 and the SC-2 ERROR flag
Note that the SC-2 ERROR flag does not set until after CB-3 MTTF is set unless

CB-3SEL ERR or SC-2 ILLEGAL FUN is set at the beginning of an operation.
Bit 5 in the Command Register (Interrupt Enable on JOB

DONE flag) is a

and the CB-3 MTTF flag is

set.

9.14.7

Change Transport Control Logic

Figure 9-43 shows the logic used to generate the CB-3 CHG TRANS L signal when a new transport is selected by the
program. If an LCMR instruction is executed by the program, flip-flop E3 clears (Figure 9-43) and enables NAND
gate E7. At TP4 time, the output of E7 supplies a clock input to E8 and if any of the inputs (RE-1 SEL 0-RE-l
SEL 2 and RE-1 B SEL 0-RE-l B SEL 2) to the E4 Exclusive-OR gates are different, E8 zeroes and asserts CB-3

CHG TRANS L. The output of E7 also clocks the E3 flip-flop, causing to set and disable E7. If C TUR L and C
SOWN L are asserted or SEL REM L negated, NAND gate El
enabled at TP4 time. LBCM L
asserted to load
it

the Buffered

Command Register with bits RE-1 SEL

through RE-1 SEL 2 from the Command Register (Figure

9-30). If CB-3 CHG TRANS is set and C RWS L is asserted, RE-1 LBCM L is asserted to load the BCM (Figure 9-43).
CB-3 CLR STATUS resets the CB-3 CHG TRANS flip-flop. The Buffered Command Register is also loaded with

RE-1 SEL

through RE-1 SEL 2 when CB-3 CLR ALL is asserted (CLF instruction executed by the program).
9-89

P/0 M8322{CB-3)

+ 3V

+ 3V-

E3
C

+ 5V

T
OC -2

RE-1 SEL

-y

LCMR L

RE-1 BSEL

CB-3B
INITIALIZE L

RE-1 SEL

CB-2CHG

+ 3V1

RE-1 BSEL

DIR L

RE-1 SE

^-^^^!)°~ 11'^ ^^^

CHG TRANS L

RE-IB SEL

E8
CHG
TRANS

E12

TP4 L

,P/0 M8322
"(CB-1)
f—

—

!-i E27 \i
V

t>
riQ

CB -3 CLR

OC-2
d[

"\_LBCM L

STATUS L

SC-2 REWINDING LCB-3 B TP4 H

E11

jp-

CB-3

SC-2TUR L-

CLR
ALL

SC-2 SOWN L-

SC-1

SELR H

Figure 9-43

9.14.8

Change Transport and Buffered Command Register Control Logic

Change Direction Control Logic

Figure 9-44 shows the logic used to detect a change in direction of tape movement. E35 flip-flop is cleared by SC-1

SET H at the beginning of all operations except Space Reverse, Rewind, or Offline. This applies a high to the input
of E4, which is the same as the high out of El 9.

E4 has a high output if both inputs are equal and a low output if

REWIND L, or CB-1 OFFLINE L are asserted, the output of El
goes low and the output of E4 (CB-3 CHG DIR L) is asserted. CB-3 CHG DIR L forces the control to wait for C
TUR L and C SELR L before starting a new operation.
the inputs are unequal.

9.14.9

CB-1 SP REV L, CB-1

Write Data Ready Logic

Figure 9-45 shows the Write Data

Ready logic. C WDR H is applied to the selected transport when the Tl\/18-E is

ready to start a Write operation. SC-1 SET H and CB-1 WRITE H enable NAND gate E32 to set flip-flops E23A and
E23B. This enables E27A if a 7-track transport is selected and E27B if a 9-track transport is selected to assert CB-1

WDR H. If a 9-track transport selected, E23A cleared when CB-1 WCOV L asserted, which in turn disables
NAND gate E27B and CB-1 WDR H goes low. If a 7-track transport selected, E23A cleared by the first SC-1
WRS L pulse after CB-1 WCOV L asserted and E23B cleared by the second SC-1 WRS L pulse. This operation
disables NAND gate E27A and C WDR H goes low. SC-1 DATA LATE L and SC-2 ERROR L clear both E23
is

flip-flops

these errors occur during a Write operation. If a CLF instruction is executed by the program, CB-3 CLR

STATUS sets E23A and E23B to cause CB-1 WDR H to go low, which terminates a Write operation.

9-90

P/0 M8322(CB-2)
CB-1 SP REV L
CB- REWIND L
CB-1 OFFLINE L
I

+ 3V

El 9

CB-2

CHG DIR L

E4
E35

CB-3 CHG CLEAR L

Figure 9-44

Change Direction Detection Logic

p/0 M8322(CB-1)
CB-3 CLR STATUS L
SC-I DATA LATE L
SC-2 ERROR L

r"p/0 M8321(0C-2)

coxy

Ji-

CB-1 WRS L

CB-1 WCOV L

E23A

E23B

CB-1

E27a\>-

SC-

SET

CB-1 WRITE

WDR H

E33 )

H^iE>

—I

—f- D>
E32

CB-1 7 CHANNEL

+ DENS H

C WDR L

SC-1 7 CHANNEL L
+ DENS L

Figure 9-45

9.14.10

Write Data Ready Logic

Read and Write Control Logic

The logic shown in Figure 9-46 is used to generate control signals during Read and Write operations. Table 9-18
shows the levels of the control signals and the logic used to assert each signal for each Read and Write operation on
7- and 9-track transports. E40 is used only if a 7-track transport is selected. E40 is clocked on the rising edge of the
SC-1

RDS or SC-1 WRS pulses.

The Read and Write control signals are applied to the CB-1 BRK RQST control logic to determine when a BRK
RQST is to be made by the TM8-E (Figure 9-40). CB-1 BRK RQST is clocked on the falling edge of the SC-1 RDS or
SC-1 WRS pulses. Refer to Drawing D-TD-TM8-E-1, sheets 1 through 8, for the timing diagrams that illustrate these
operations.

9.14.11

Data Multiplexer Control Logic

Figure 9-47 shows the Data Multiplexer Control logic used to select data read from tape, from memory, or from the

AC as input to the Data Register (Figure 9-25). Table 9-17 shows the level of CB-2 DB MPXA H and CB-2 DB MPXB
H for all TM8-E operations.

9-91

c
.2
.t:

RDS

o
»*

rising

the

ILI

edge

RDS

edge

WRS

Reset
state

Set

edge

state

rising

CM
CO
LU

Set

state

edge

CWRS

Reset

rising

state

rising

CO
UJ

m
t -1
OC

E 3i

^ "^

^ >

"aJ

"5
5,
cn >

_a)

-J

OQ LU

\!Z

-£,

"a5

-J
-J

"c5

w
u

HI
OQ 1-

-1

O)
n>

cn
sz

^ "^

•^ "05

O
^

^ oc
h- O
«Q

Q
DC
.-

r"O

cn
x:

"^5

5, "05

^ >

-S,
cn

s, "o5

•S,

^ >
"05

"a5

-£,
.S'

-1
r-

9
<
o UJ
CO

"aJ

-£.

"53

"a5

"05

-J

T CO

>
«

.5?

"55

-S,

-5

a
u

V-

O Q

£ E ^

^ S £ c

U U- 1-

c
o

^1a

1 ^
o

§ 1 a

£, "o^

o 2 E ^
S5O U.2 h-E

9-92

+-•

|I5
§
5 U
<u

"o
c:
Qj

<rt

5 O o H

;;

" t:
™ o

Sh 1

5 O o 1-

P/0 M8322(CB-1)
CB-1
VVRITE H

CB-3 CLR STATUS
CB-1
it-r\

SCH WRS L

\^
;>o _^
-^

^^^

E37A

•

\qRD 1st 7 L
(p

E41B

E41C

CB-1

WR 1st 7 H

\q RD 2nd 7 L

<
'

•'lb

CB-1

+ 3V

\q RD 9 L

E32

+ 3V

CB-1 7

E39

SC-1 7 CH
+ DENS L

CB-1
E37B

E41A
;'.

E40

CH + DEN 5 H

CB-1 WR 9 H

-u^
8E-0555

Figure 9-46

Read and Write Control Logic

P/0 M8322(CB-2)

CB-

WRITE L

CB-2
CB-1 7 CHANNEL + DEN 5 L-

-MPXAH

E1B
C

\
E2 )0
q__^

CB-3 CLR ALL L

+ 3V
DC -2 LDBR L

d E2 \)0

i
i

|-q/

CB-1

CB-2

WRITE L

I
I

P/0 M8322(CB-1)
CB-1 R+ RC H

MPXB H

E38 V-p
1

Figure 9-47

9.14.12

E1B
1

+3V
SC-1 SET H

Data Multiplexer Control Logic

POWER OK Logic

The POWER OK logic shown in Figure 9-48 is used to assert CB-3 CLR ALL if PDP-8/E power falls below a certain
level. If PWR OK H goes low, NAND gate El 6 is enabled to assert CB-3 CLR ALL. This initializes all TM8-E logic
and the selected transport.

9-93

o
C

9-94

9.14.13

Initialize Logic

INIT H (Figure 9-48) is asserted when the PDP-8/E is powered up or by depressing the CLEAR key on the PDP-8/E

power control console. Note that INIT H is not the same signal as C INIT H; C INIT H is used to clear all logic on
the selected transport when the following conditions exist.

INIT H is asserted by the processor.

the tape unit is ready (C TUR L true) when a CLF instruction is executed by the program (CB-3 CLR

ALL is asserted).
c.

If a Space

If the

Reverse operation is attempted and transport is at BOT.

CLT instruction is executed to assert CB-3 CLR ALL.
SECTION 5 MAINTENANCE

Recommended preventive maintenance should be scheduled on a regular basis to maintain the performance and
reliability of the DECmagtape system. Preventive maintenance schedules are included in the TU10 DECmagtape
Maintenance Manual, Chapter 5, Paragraph 5.1.1. TiVlS-E DECmagtape diagnostics (Paragraph 9.3) are provided to
test and troubleshoot the TI\/18-E controller and the TU10 DECmagtape Transports. Preventive maintenance on the
Tl\/18-E

modules consists of running the TIV18-E diagnostics periodically to check system operation.

SECTION 6 SPARE PARTS
Table 9-19 lists the recommended spare parts for the TM8-E,

SECTION 7

IC DESCRIPTIONS

Only those ICs not included in Appendix A of Volume 1 are discussed in this section.

9-95

Table 9-19

TM8-E Spare Parts

DEC Part Number

Description

Quantity

10-00007

Capacitor, 15 pF, 100V

10-00042

Capacitor, 1000 pF, 100V

10-00067

Capacitor, 618 pF, 35V

10-01610

Capacitor, 0.01 juF, 100V

12-09941

Connector, 40 pins

13-00204

Resistor, 4712,

13-00229

Resistor, 10012, VaW

13-00275

Resistor, 22012,

13-00286

Resistor, 27012, %\N

13-00293

Resistor, 33012,

13-00317

Resistor, 47012, 'A\N

13-00443

Resistor, 41712,

13-00498

Resistor, 18 K12. %\N

1
1

13-00534

Resistor, 100 K12, y4W

13-01316

Resistor, 8.2 K12, 'A\N

13-01401

Resistor, 75012, 'A\N

13-01420

Resistor, 2712, 'A\N

15-10015

DEC 4008
IC, DEC 7474
IC, DEC 7400
IC, DEC 7410
IC, DEC 7430
IC, DEC 7401
IC, DEC 7402
IC, DEC 7495
IC, DEC 74H00
IC, DEC74H10
IC, DEC74H21
IC, DEC74H11
IC, DEC 380
IC, DEC 384
IC, DEC 8251
IC, DEC74H74
IC, DEC 7404
IC, DEC 314
IC, DEC 8881
IC, DEC 8242
IC, DEC 7416
IC, DEC 7414
IC, DEC 8235
IC, DEC 74153
IC, DEC 7412
IC, DEC 74197
IC, DEC 74123
IC, DEC 74175
IC, DEC 74174

19-05547

19-05575
19-05576
19-05578
19-05570
19-09004
19-09055
19-09056
19-09057

19-09058
19-09267

19-09485
19-09486
19-09584
19-09667

19-09686
19-09704
19-09705
19-09712
19-09928
19-09929

19-09935
19-09937

19-09955
19-10035
19-10435
19-10651

19-10652

IC,

9-96

2
2
2
2
1

2
2
1
1
1
1

3
2
1
1

2
1

3
1

2
2
1
1

1
1
1

DEC 74153

The DEC 74153 IC is a Dual 4-Line to 1-Line Data Selector/Multiplexer (see below for truth table, logic diagram,
and pin numbers). The IC can be used in one of two modes, a 4-line to 1-line multiplexer or a parallel-to-serial
converter, A strobe enable signal line is provided to select each of the input lines as an output. In the TM8-E, the

MD lines, Data Bus, or data read from the

strobe lines are tied together to allow the selection of signals from the

TU 10 Transport.

CONTROL INPUT

STROBE

OUTPUT

LOW

HIGH

LOW

HIGH

LOW

HIGH

H IGH

LOW

HIGH

LOW

DON'T CARE

TRUTH TABLE (EACH HALF)

LOCATOR

(TOP VIEW OF IC)

DEC 74153 IC (Sheet

9-97

STROBE
1A

DATA
INPUTS

CONTROL
INPUTS

=_}

^—
OUTPUTS

>n">
2A

DATA
INPUTS

STROBE

D>
LOGIC DIAGRAM

DEC 74153 IC (Sheet 2)

9-98

DEC 74174 IC
The 74174 IC contains six flip-flops with single rail output with a buffered clock and direct clear input. Each
flip-flop has an individual data input. The truth table and logic diagram are shown below.

Input

Outputs

*n+1

A o!13)

TRUTH TABLE

D
H

INPUT

OUTPUTS

tn + 1

(2).

-01 CLOCK

H
L

CLEAR

time before
clock pulse.

tp = Bit

(4)

B o-

(5)

time after
clock pulse.

tn + 1=Bit

-0|CLOCK

CLEAR

J
C tf

(7),

-QCLOCK
CLEAR

,.-J
(10)

(11)

D o-

-OJCLOCK

CLEAR

,.-T
(12).

(13)

-01 CLOCK

CLEAR

.^J
(15)

(14)

F o-

CLOCK

^Xy

CLEARS

Pin(16)»Vcc,Pin(8)=6ND

DEC 74174 IC

9-99

-CJCLOCK

CLEAR

DEC 74175 IC
The 74175 IC contains four flip-flops with double rail outputs with a buffered clock and direct clear input. Each
flip-flop has an individual input. The truth table and logic diagram are shown below.

TRUTH TABLE
INPUT

OUTPUTS
tn+1

H
L

L
H

time before
clock pulse.

tn = Bit

tn+1 = Blt time ofter
clock pulse.

(4)

(2)

-OjCLK

0/^

CLEAR

J
(5)

(7)

-OCLK Qb
CLEAR

J
02)

(10)

CLK Qc

CLEAR

J
(13)

(15).

CLOCK

(9),

^
-OCLK Qd
CLEAR

(1)

CLEAR o-

Pin{16)»Vcc.Pin (8)»GND

DEC 74175 IC

9-100

DEC 74197 IC
The DEC 74197 IC

pre-settable

binary counter that can also be used as a latch.

The IC consists of four

dc-coupled master-slave flip-flops connected to provide a divide-by-2 counter and a divide-by-8 counter. The logic
diagram, a truth table, and a pin locator are shown in the 74153 description.

The 74197 can be used in any one of three modes, viz; the divide-by-2/divide-by-8 mode, requiring no external
interconnection or IC pins, the latch mode, and the binary counter mode. If the first listed mode is used, an input at
divided by 2 by flip-flop A and the result is taken from pin 5; an input at pin 6 is divided by 8 by flip-flops

pin 8

B, C,

and D and the

result

taken from pin 12. Transfer of information to the outputs takes place on the

negative-going (trailing) edge of the clock pulse.

To use the latch mode, enter data at the four data inputs (pins 4, 10, 3, and 11) and enter a strobe pulse at pin 1.
The output pins, 5, 9, 2, and 12, respectively, will follow the inputs when pin 1 is low, but will remain unchanged
when pin 1 is high and the clock inputs are inactive.

Count
Clock 1 Input

Output

COUNT/LOAD

Vcc

CLEAR

DATA C

DATA A

DATA D

DATA B

CLOCK 2

GND

CLOCK

9
10

DEC 74197 IC (Sheet 1 of 2)

9-101

DATA A

COUNT/LOAD
CLEA R

3>.

—

CLOCK 1-

DATA B-

-t>-

:^>

nl>
CLOCK 2QB

DATA C-

DATA D-

:^>

^=o
QC

-QC

-QD

^o
^t>

DEC 74197 IC (Sheet 2 of 2)

9-102

-f

CHAPTER 10
TA8-E CASSETTE SYSTEM INTERFACE

SECTION 1

INTRODUCTION

The TA8-E interfaces the PDP-8/E, M, or F Computers and the TU60 Cassette Tape Transport System (2 drives)
(Figure 10-1). To perform this function, the TA8-E:
a.

Decodes lOT instructions to generate control signals and transfer data.

Transmits control signals to the TU60 and receives signals from the TU60 that indicate TU60 status.

Selects (in conjunction with the TU60)

one of the TU60 drives to perform an operation (i.e., read or

write).

Provides flags to indicate ERRORS and generates SKIP or INTERRUPT REQUEST.

Buffers the input/output data.

Provides TU60 and TA8-E status information to the computer.

z^
lOT INSTRUCTIONS

DATA(WRITE)

DATA (READ)
TA8-E
INTERFACE
{M8331)

DATA (AC4-ACH)

CONTROLS

TU60
CASSETTE
DRIVE

(DUAL DRIVE)
STATUS

\7
Figure 10-1

TA8-E Interface and TU60 Cassette Drive, Block Diagram

10-1

10.1

PHYSICAL DESCRIPTION

The TA8-E consists of the M8331 Interface Module that is inserted into the OMNIBUS to provide an interface for
the TU60. The TA8-E and TU60 can be ordered in two rack mounted configurations. These configurations are
outlined below:

•

TAB-AA - M8331 Module, TU60 AA, and 2 BC08R cables (rack mounted), 115 Vac

•

TA8-AB - M8331 Module, TU60 AB, and 2 BC08R cables (rack mounted), 230 Vac

The basic system consists of one TU60 Cassette Tape Transport System (2 drives) and one M8331 Interface Module
with interface cables. Jumpers on the M8331 module permit the selection of lOT device codes 70 through 77. These
device codes allow the user to install a maximum of eight TA8-E modules on one processor and to use eight dual
drive cassettes (16 drives),

10.2

POWER REQUIREMENTS

The M8331 module requires +5V at 2,4A. This logic power is supplied by the processor power when the M8331
module is inserted into the OMNIBUS. Power is not supplied to the TU60 by the TA8-E or vice versa,
10.3

TAPE FORMAT

The tape format (Figure 10-2) is 8-bit serial words with programmable block length (Figure 10-3). Block length is
limited only by the length of the tape, and

of data

up to 92K words can be recorded on one cassette cartridge. Each block

preceded by a PREGAP and PREAMBLE to identify the data block. A Cyclic Redundancy Check (CRC)

character is recorded at the end of the data block and is followed by a POST GAP, Gaps are erased areas on the tape
that are used to separate blocks of data and to provide a space to start and stop the tape drive.

The CRC character is computed by the TU60 hardware during a write operation and written at the end of a block of
data. The CRC character computed during a write operation is compared with the CRC character computed during
read operations to determine if data bits were picked up or lost. The CRC character is generated and checked by the
TU60 electronics, and if a CRC ERROR occurs, the CRC BLOCK ERROR flag is set by a signal from the TU60, The
TU60 Maintenance Manual contains a complete discussion of CRC character generation and error checking
operations.

The PREAMBLE is a word generated by the TU60 to identify a block of data and to provide sync pulses to read and
write data.

TAPE

DATA

"SPLICE

DATA

1
FILE
GAP

LOAD POINT GAP

M
BOT

DATA BLOCK

EOT

DATA FILE

Figure 10-2

Typical TU60 Format

10-2

PEAK CAPACITY
=1-90K

--75K

60K

AVERAGE
RATE

CAPACITY
(BYTES)

(BYTES/SEC)
--45K

--30K

--15K

256

128

92K

BLOCK LENGTH (BYTES/BLOCK)

Figure 10-3

10.4

TU60 Capacity and Data Rate vs Block Length

DOCUMENTATION

Reference documents are required to program and maintain the TA8-E as follows:

PDP-8/E, PDP-8/F, and PDP-8/M Small Computer Handbook - DEC, 1973

PDP-8/E, PDP-8/F, and PDP-8/M Maintenance Manual Volume 1, DEC-8E-HR1B-D

DEC Engineering Drawing, TA8-E Cassette System Interface, B-DD-TA8-E-0-0

TA8-E Diagnostic, MAINDEC-08-DHTAA-A

TA8-E Data Reliability Test, MAINDEC-08-DHTAB-A

TU60 Cassette Tape Transport Maintenance Manual, DEC-00-TU60-DA

TU60 Engineering Drawings, B-DD-TU60-0-0

10-3

SECTION 2 INSTALLATION AND ACCEPTANCE TEST
The TA8-E Cassette System Interface is installed on site by DEC Field Service personnel. The customer should not
attempt to unpack, inspect, checkout, or service the equipment.
10.5

INSTALLATION

Install the TA8-E as follows:

Ensure PDP-8/E power is off.

Ensure the correct device code select jumpers are installed (see Table 10-1 and refer to drawing

M8331-0-1).

Connect the BC08R cable to the M8331 module as shown in Figure 10-4.

Insert

the

M8331 module

into the

OMNIBUS.

Refer to Table 2-3

Volume

of the

PDP-8/E

Maintenance Manual for module installation priority and placement on the OMNIBUS.
5.

Unpack and install the TU60 Cassette Drives as specified in Chapter 2 of the TU60 Maintenance Manual.

Connect the other end of the cable to the TU60 Cassette Drive as shown in Figure 10-4.

Table 10-1
Device Code Selection Jumper Installation
Install Jumpers

Device Code

A
70
71

73
74
75
76
77

X
X

X
X
X
X

X
X
X

X
X

X
X
X
X

X
X
X

X
X

X designates jumper to be installed.

NUMBERS ON THE CONNECTOR
AND THE CONNECTOR NAME
ARE UPSIDE DOWN WHEN THE
CABLES ARE INSTALLED
CORRECTLY
PIN

RACK MOUNT CABLING

Figure 10-4

TA8-E and TU60 Cabling

10-4

10.6

ACCEPTANCE TEST

To test the TA8-E, run the following diagnostics in the order shown. The instructions for running the diagnostics are
on the document accompanying the binary tape.

TA8-E Diagnostic, IVlAINDEC-08-DHTAA-A

TA8-E Data Reliability Test, MAINDEC-08-DHTAB-A

Refer to the

Field

Installation

and Acceptance Test procedure

the

TA8-E

print set for acceptance test

requirements.

10.7

TA8-E INTERFACE

The rack-mounted system is provided with two BC08R cables to connect the TA8-E on the OMNIBUS to the TU60
Cassette Drives. The signals on these cables are shown in Table 10-2, and a complete description of each signal is
provided in Paragraph 10.10.

Table 10-2

TA8-E Input and Output Signals

M8331,J1
Number

M8331,J2
Number

TA8-E Input
or Output

Signal

R/W 05 L

Input

DRIVE EMPTY L

Output

BACK BLOCK GAP L

Output

WRITE MODE L

Input

REWIND L

Output

BACK FILE GAP L

Output

REWIND CMD L

Input

WRITE LOCKOUT L

R/W 01 L

R/W 02 L

R/W 03 L

'It-

Output

10-5

R/W 04 L

READ/WRITE CRC L

Table 10-2 (Cont)

TA8-E Input and Output Signals

M8331,J1

M8331, J2

TA8-E Input

Pin Number

or Output

Output

Signal

READ/WRITE FILE

GAPL
R

Output

START L

Output

INIT L

Output

TRANSFER L

Input

EOF L (End of FILE)

Input

EOT/BOT L (End of
Tape or Beginning of
Tape)

Input

TIIVIE

R/W 06 L

R/W 08 L

R/W 07 L

CRCBLKERR L

ERROR

*R/W 01 through R/W 08 are bidirectional lines used to transfer data in both directions.

NOTE
Pins not listed are tied to ground.

SECTION 3 FUNCTIONAL DESCRIPTION
This section provides a functional description of the major groups of

logic, a

list

TA8-E instructions, and a

description of each signal transmitted and received by the TA8-E.

10.8

FUNCTIONAL DESCRIPTION

The TA8-E logic is divided into functional areas for descriptive purposes. Figure 10-5 is useful in understanding
signal

10.8.1

flow and the interrelationship of groups of logic. Section 4 provides detailed discussion of each group of logic.

lOT Decoder

There are eight sets of I/O device codes that determine which of eight possible TA8-E modules is being addressed.

The decoding is done by jumpers connected to MD6, MD7, and MD8 (Table 10-1). When the correct code for the
TA8-E goes to the I/O decoder and I/O PAUSE is present, a SELECT H signal is generated to allow the decoding of

MD09-MD11 and to generate an INTERNAL I/O L. I/O PAUSE is present anytime an lOT instruction is executed
by the program. INTERNAL I/O L prevents the processor from executing other lOTs while this instruction is
executed. MD09-MD1 1 are decoded to control data transfers and to generate control signals that enable the TA8-E
to load the Status A Register. The Status A Register generates control signals that are transmitted to the TU60.

The lOT decoder also controls the CO and CI lines, which control the direction of data transfers between the AC
and the TA8-E registers.
10-6

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10-7

10.8.2

Status A Register

The Status A Register (Figure 10-6) is loaded from AC04-AC11 by the KLSA instruction and used to enable
interrupts, select one of two drives (drive A or B), enable the TU60 transnnitters and receivers, and provide signals

FR0-FR2 to the Function Register. Signals FR0-FR2 are decoded to select one of the TU60 functions. The KLSA
A Register to the AC during maintenance operations.

instruction also transfers the complement of the Status

ENABLE INTERRUPTS
NOT USED

NOT USED

FUNCTION REGISTER
(SEE TABLE 10-3)

DRIVE A/B

A 1=B

SELECT ENABLE
8E-0666

Figure 10-6

Contents of the Status A Register

READY FLAG
WRITE LOCK OUT

REWIND
DRIVE EMPTY

END OF FILE FLAG

EOT/ BOT
TIMING ERROR
CRC/ BLOCK ERROR
8E-0665

Figure 10-7

Contents of the Status B Register

10-8

Function Register

10.8.3

The Function

FR0-FR2 and provides control signals to the TU60. These control
TU60 will perform, i.e., read or write.

signals determine the operation the

Status B Register

10.8.4

The Status B Register contains the current status of TU60 (Figure 10-7), which can be transferred to the AC for
evaluation by the program. The KRSB instruction transfers the contents of this register to AC4-AC1 1.
10.8.5

Read/Write Buffer Register

The Read/Write Buffer Register provides temporary storage of data to be written on the tape or read from the tape.
Without this register the TA8-E would have to transfer data to the processor within 230 jus in order to prevent a

TIME ERROR. Using the Read/Write Buffer Register, 1.84 ms is allowed between transfers, or the time required by
the TU60 to read or write an 8-bit byte.

Data Flag

10.8.6

The Data flag is set for every byte read or written including the two CRC bytes. The Data flag is cleared by the
K(30A instruction. Data flags normally occur once every 1.84 ms (Paragraph 10.11.1.10).

INSTRUCTION AND STATUS BITS

10.9

The

instructions used to

program the TA8-E

are

shown

Table 10-3. The status

bits associated

with these

instructions are explained in Tables 10-4 and 10-5.

The KLSA

instruction (Table

10-3)

has two functions:

to transfer data

from AC4-AC11 to the Status A

to clear the AC and transfer the complement of the Status A Register to the AC. To accomplish

the C lines, CO and CI, must be switched during execution of the instruction. Processor timing must be stopped

during TS3 by

NOT LAST TRANSFER L to allow time to switch the C lines. After the C lines are switched,

processor timing is restarted by BUS STROBE and the complement of the Status A Register is read into the AC.

Programming Sequence

10.9.1

Figure 10-8 is a flow diagram of TA8-E operations showing the TA8-E programming and operation sequences.

INPUT AND OUTPUT INTERFACE SIGNALS

10.10

The input and output signals are O.OV (low) when true and +3V (high) when false. Note that the following signals
must be present at the TU60 during an entire operation.
a.

b.
c.

d.
e.

SELECT ENABLE L
DRIVE BL

BACK BLOCK GAP L
BACK FILE GAP L
READ/WRITE FILE GAP L

REWIND L, READ/WRITE CRC L, TRANSFER C, and WRITE MODEL signals are transmitted to the TU60 and
stored in the TU60 until an operation is completed.

10-9

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Table 10-3

TA8-E Instructions

Mnemonic

Operation

Octal

Code

A and Status B Registers (Tables 10-4 and 10-5).

KCLR

67X0

Clear All: Clear the Status

KSDR

67X1

Skip the next instruction if the Data flag is set during read or write operations.

IKS EN

67X2

Skip the next instruction if any of the following are true:

KSBF

67X3

IKLSA

67X4

Tape is at EOT/BOT (End of Tape or Beginning of Tape).

The TU60 is not ready or the selected drive is empty.

Skip the next instruction if the Ready flag is set.

Load Status A from AC4— AC11, clear the AC, and load the complement of
Status A back into the AC (Table 10-4).

IKSAF

67X5

Skip on any flag or error condition.

KGOA

67X6

Assert the contents of the Status A Register and transfer data into the AC during
a

read operation or out of the

AC to the Read/Write Buffer during a write

operation. This instruction has three functions.

Enables the command in the Status A Register to be executed by the

TU60.
b.

For read operations, the first KGOA instruction causes the tape to
start

moving, and when the Data flag sets, a second KGOA transfers

the first byte from the Read/Write Buffer to the AC. The Data flag
sets after each 8-bit byte is read from the TU60.

For write operations, the Status A Register is set up for a write, and
the

AC contains the first byte to be written on tape. When the

KGOA instruction

executed, the tape starts to move and the first

byte is transferred to the TU60.

KRSB

67X7

Transfer the contents of the Status B Register into AC4-AC1 1 (Table 10-5).

10-11

10.10.1

Output Interface Signals

The TA8-E provides the following output signals to control the TU60.
10.10.1.1

SELECT ENABLE L - This signal, at a logical

receivers if bit 04 in the Status

10.10.1.2
drives.

A Register

enables the TU60 input/output transmitters and

set (1).

DRIVE B L — This signal is asserted by bit 05 in the Status A Register to select one of the dual tape

A logical

(low) selects drive B or a logical

(high) selects drive A.

10.10.1.3 START L — This signal, at a logical 1, is used in conjunction with a specific command to initiate
command execution. If a command is to be performed, the drive must be in the READY state (READY L asserted)
and the command must be present and stable one microsecond prior to START L. If this is the case, when START L
is received, the TU60 removes the READY L signal and initiates execution of the tape command. When READY L is
removed, the TA8-E then removes START L. While the command is being executed, any additional START L signals
are ignored by the drive.

10.10.1.4

REWIND L - This signal, at a logical

(low), is clocked by the START L signal to cause the TU60 to

rewind to Beginning Of Tape (BOT).

Table 10-4
Contents of the Status A Register

AC
Function

Bit

When bit 11 is a 1, enable the interrupt logic.

Not Used.

08-06

AC08— AC06 are applied to the Function Register to select one of the TU60 operations as follows:
AC06

AC07

AC08

(FRO)

(FR1)

(FR2)

Operation

Read
Rewind
Write

Back Space to File Gap
Write Gap

1
1

Back Space to Block Gap

Space Forward to File Gap

Read/Write ORG Character

Select TU60 Drive A if bit 5 is a

Enable the TU60 input receivers and most of the output transmitters.

and Drive B if bit 5 is a 1 (high).

10-12

Table 10-5

Contents of the Status B Register

AC
Bit

Function

Ready flag: The Ready flag is set (1) when the selected drive is ready to accept commands from
the TA8-E. A cassette must be installed and the selected tape drive must be stopped, which would
indicate that previous tape operations have been completed.

WRITE LOCK: WRITE LOCK is set (1) if the selected drive is empty or if the cassette installed is
write protected.

09
08

REWIND: REWIND is set (1) if the selected drive is performing a rewind operation.

DRIVE EIVIPTY: DRIVE EIVIPTY is set (1) if the selected drive does not have a cassette installed
or the cassette installed is not a digital grade cassette.

End of File: The End of File (EOF) flag is set (1) if a file gap is detected or the TU60 reads a
blank space on the tape.

EOT/BOT: End of Tape or Beginning of Tape (EOT/BOT) is asserted if the photosensor on the

TU60 is uncovered when the tape is at the beginning or end of tape (Figure 10-2).
05

TIMING ERROR: TIIVIING ERROR is set (1) if the TA8-E does not respond to a TRANSFER
REQ from the TU60 within 230/15.

CRC/BLOCK ERROR: CRC/BLOCK ERROR is set (1) if a CRC ERROR is detected during a
read operation.

10.'i0.1.5

BACK BLOCK GAP L - This motion command signal, at a logical

(low), is clocked by the START L

signal to cause reverse tape motion at read/write speeds across a data block to the preceding PREGAP.

10.110.1.6 BACK FILE GAP L - This signal, at a logical 1 (low), is clocked by the START L signal to cause reverse
tape motion at search speed across a data file and the tape drive stops at two-thirds of the preceding file gap.
10.110.1.7
READ/WRITE FILE GAP L - This signal, at a logical 1 (low), is used in conjunction with the WRITE
MOiDE L signal to initiate either forward tape motion or a write file gap operation. If WRITE MODE L is a logical 1
when this signal is clocked by the START L signal, 535 ms of tape is erased. If the gap is a load point gap (at the

Beginning Of Tape), 1.4 seconds of tape is erased. If WRITE MODE L is a logical
on the selected drive moves forward, stopping at the beginning of the next file gap.

when this signal is clocked, tape

10.110.1.8 WRITE
L — This signal selects either the read or write logic. For a write or write
operation, this signal, at a logical 1, is clocked by the START L signal to set the TU60 Write flip-flop.

MODE

file

gap

For a read operation, this signal, at a logical 0, allows the START L signal to reset the Write flip-flop in the TU60.
Once the specific operation is initiated, the Write flip-flop remains either set or reset until the next operation is
started.

10-13

TRANSFER L - During a write operation, this signal, at a logical 1, is transmitted to the TU60 in
the case, TRANSFER L sets the TRANS REQ flip-flop and the
response to a TRANSFER REQ L signal. If this
10.10.1.9

8-bit byte is loaded into the TU60 Data Buffer.

During a read operation, this signal, at a logical
signal.

transmitted to the TU60 in response to a TRANSFER REQ L

TRANSFER L sets the TRANS REQ flip-flop to indicate that the 8-bit byte has been loaded into the

Read/Write Buffer.

READ/WRITE CRC L - During a write operation, this signal, at a logical 1, causes the accumulated
CRC character to be recorded on the tape. R/W CRC L is transmitted to the TU60 while the final data byte is being
recorded. When this occurs, the next TRANSFER REQ L signal is inhibited and the CRC character is recorded after
10.10.1.10

the final data bit is written (Paragraph 10.8.6).

During

1, tests

read operation, this signal, at a logical

the

CRC Register for an error. At the start of a read

operation, the CRC ERR flip-flop is set and remains set while the data block is being read. After the first eight CRC
L. READY L inhibits CRC ERROR (if one
REQ L signal is generated, the CRC Register
(data read incorrectly), the CRC ERR flip-flop remains set and when READY
not
checked for 0. If the register
L is generated, a CRC ERROR L signal is also generated. If the data has been read correctly, the CRC ERR flip-flop
not generated.
resets and a CRC ERROR L signal
bits

have been read, the TA8-E interface transmits READ/WRITE CRC

occurs) until the transfer is completed. When the final TRANSFER

10.10.1.11

INITIALIZE L- This signal, at a logical 1, removes all TU60 flags (except EOT/BOT or CRC ERROR),

generates READY L, and except for a rewind operation stops tape motion regardless of the tape position.

10.10.2

Input Interface Signals

The following input signals are received from the TU60 and applied to Status B, the interrupt logic, and the skip
logic.

10.10.2.1

OFF LINE L - This signal, at a logical 1, indicates that the appropriate tape cassette is not properly

loaded on the selected drive, or that the clear leader sensing lamp has failed.

10.10.2.2

READY L - This signal, at a logical

(low), indicates that the appropriate tape cassette has been

properly loaded and tape motion is not occurring on the selected drive. In general, READY L is generated when all
command functions have been completed and the drive is ready for the next operation, or when a clear leader on the
tape is encountered.

10.10.2.3

END FILE L - This signal, at a logical 1, indicates that a file gap has been detected or the tape is blank.

10.10.2.4

EOT/BOT L-This signal, at a logical

indicates that the drive has reached the

End-of-Tape or

Beginning-of-Tape (clear leader uncovers photosensor). When this occurs, tape motion stops and the READY Land

EOT/BOT L signals are generated.
10.10.2.5

REWIND L-This signal, at a logical 1, indicates that the selected drive is performing a rewind

operation.

10.10.2.6

WRITE PROTECT L -This signal, at a logical 1, indicates that a write-protected cassette is loaded on

the selected drive, or that the drive is empty.

the cassette is write protected, the selected drive will not perform

any write operations.
10.10.2.7

WRITE STATUS L — This signal, at a logical 1, indicates that a write or write file gap operation is being

performed on the selected drive.

10-14

TRANSFER REQUEST L - During a write operation, this signal, at a logical 1, indicates that the drive is

10.10.2.8

ready to receive an 8-bit byte from the Read/Write Buffer Register. The TRANSFER REQ L signal is generated one
bit time

before a byte is needed, and this signal is removed when the interface responds with a TRANSFER L signal.

During a read operation, TRANSFER REQ L, at a logical 1 (low), indicates that a byte from the drive is ready to be
transferred to the Read/Write Buffer Register. The TA8-E must then respond with a TRANSFER L signal within one
bit (230 lis) after the

TRANSFER REQ L signal is generated or a TIME ERROR occurs.

TIME ERROR L - This signal, at a logical

10.10.2.9

indicates that the

interface has not responded to a

TRANSFER REQ L signal within the allotted time (230 jUs).
CRC BLOCK ERROR L - This signal, at a logical 1, indicates that a CRC error has occurred during a
At the start of the read operation, the CRC ERR flip-flop is set. When the final CRC character
not 0, the CRC ERR flip-flop remains set, and when
read, the CRC Register is checked for 0. If the register
READY L is generated, a CRC ERROR L signal is also generated.
10.10.2.10

read operation.

SECTION 4 DETAILED LOGIC
10.111

DEVICE SELECT AND lOT DECODER

The lOT decoder (Figure 10-9) decodes TA8-E lOT instructions from the Memory Data Bus and generates signals to
control the TA8-E and TU60. Bits MD3-MD11 are gated by I/O PAUSE when an I/O instruction is generated.
MD3-MD8 generate signal SELECT H and enable bits MD9-MD11 to be applied to the lOT decoder. The device
code 67X, where X is equal to 0—7, is selected by the jumpers on the output of NAND gates E7 (Table 10-1). The
lOT decoder is a DEC 7442 IC (see Section 7 for truth table and logic diagram). The DEC 7442 IC is a
BCD-to-decimal decoder that decodes MD9— MD1 1 and produces a low or one on the output line to indicate which
instruction has been executed by the program. As an example,

MD9 low, MD10, and MD11 high (100) produce a

low on pin 4, which indicates a KLSA instruction was programmed.
10.12
10.12.1

CONTROL LOGIC
C Line Select Logic

The C line select logic (Figure 10-9) controls the direction of data flow between the AC and the Data Bus and
determines whether or not the AC is cleared. Table 10-6 gives the status of CO and CI (high or low) for transferring
data between the AC and Data Bus, using the TA8-E instructions. As previously stated, when the KLSA instruction
is

executed by the program, the C lines must be changed and this change must take place during the time that the

instruction is being executed. To accomplish this, flip-flop E14 (DIR) is cleared atTPStime of the instruction cycle

(Figure 10-10), causing CO L and CI L to go low and asserting NOT LAST TRANSFER L. NOT LAST TRANSFER

L stops processor timing to allow the Status A Register to settle and the C lines to switch before the complement of
the Status A Register is applied to the AC via the Data Bus. ENABLE H is negated (low) to prevent the contents of

the Status A Register from being applied to the Data Bus while the C lines are switching.

Table 10-6

C Line Select Levels for Transfers to the AC
Instruction

Transfer Operation

KLSA

low

high

AC->DATA BUS then O-^AC

low

high

low

DATA BUS->AC
WRITE: AC^DATABUS
READ: DATABUS-^AC
DATA BUS->AC

KGOB
KRSB

10-15

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10-16

+ 5V

CO L

Figure 10-10

Data Transfer Control Logic

At the same time E14 (DIR) is cleared, the 74123 IC (see Appendix A, Volume 1 for logic diagram) is triggered (the
74123 IC is a dual one-shot multivibrator). E19A outputs a 320 ns pulse when triggered by the high to low
transition on the output of E3 NAND gate at TP3 time. The trailing edge of the pulse out of E19A triggers E19B
and generates a 100 ns pulse. The 100 ns pulse out of E19B asserts BUS STROBE L to restart processor timing. E14
changes state at TP4 time, and the C lines are switched to transfer the information on the Data Bus to the AC.
10.12.2

Time Pulse Logic

Time pulses, TP2, TP3, and TP4, are used throughout the module to enable gates and enable the execution of
instructions.

10.12.3

Initialize and Clear All

Logic

INITIALIZE clears all TA8-E and TU60 logic when the power is first turned on, when the CLEAR key on the
is depressed, or when the CAF
instruction is executed. CLR ALL L is asserted when
INITIALIZE L is asserted, or when the KCLR instruction is executed to clear all logic on the TA8-E and TU60.

programmer's console

INIT L to the TU60 (Figure 10-9) is asserted longer than CLR ALL in the TA8-E to allow enough time for the signal
to be transferred to the TU60 and to clear the logic in the TU60. Flip-flop E20 is cleared by CLR ALL L to assert

INIT L at TP3 time and remains cleared until the next TP2 time. TP2 H sets flip-flop E20 and removes INIT L from
the TU60 during the next instruction cycle.

10-17

10.13

STATUS A REGISTER

The Status A Register (Figure 10-11) is loaded from the AC by a KLSA instruction, the AC is cleared, and the
complement of Status A is transferred back to the AC. Thus, one instruction is used to load and read the Status A
Register. The output of the Status A Register is used to enable interrupts, select a tape operation, select a tape drive,
and enable the TU60 transmitters and receivers.

DATA 11 L-

INTENAH rsjaO

E49\>— DATA

U"""^

NOT USED
E32
STATUS
REGISTER A
(8271)

DATA 09 L

NOT USED

FR2 H

DATA 08 L
CLR LD CLK DS

tS^ESO

E49\)— DATA 10 L

E49\>— DATA

l^y

9 L

DATA 08 L

DATA 07 L
1

E26\>— D/
)ATA 07 L

^o^^_^

,::3E)—
DATA 05 L

E26\>— DATA 06 L

E51

STATUS
REGISTER A
(8271)

DRIVE B H

SELECT ENABLE
SELECT

K>—\~_\/

ENABLE L
JVs^31

|__3/^ 04 L

ENABLE A H

Figure 10-1 1

10.14

Status A Register

FUNCTION REGISTER

The Function Register (Figure 10-12) decodes FRO— FR2 from the Status A Register to select one of the TU60
operations (Table 10-4). The Function Register is a DEC 7442 IC (see Section 7 for truth table and logic diagram)
that decodes FRO— FR2. The 7442 IC is a BCD-to-decimal decoder that produces a low on one output line for each
combination of bits that are supplied as inputs. As an example, if FRO is low and FR1 and FR2 are high (100), the
Back Space To File Gap line is asserted (low) and the TU60 is commanded to execute this operation. The output
signals applied to the

TU60 are explained in Paragraph 10.10.

10-18

10-19

10.15

START LOGIC

Before any operation can be started by the TA8-E and TU60, START L must be asserted (Figure 10-13). To set the
START flip-flop, the TU60 must be in the READY state and there must be a cassette installed on the selected drive.
When these conditions are met and the KGOA instruction is executed by the program, the START flip-flop will set
at TP3 time and assert START L (low). START L is applied to the TU60 and the operation selected by the program
when the Status A Register was loaded is started. The TU60 ignores any START L signals that are generated after an
operation is started.

START is cleared by CLR ALL when it is asserted by NIT L from the processor or when the KCLR instruction is
I

executed by the program.

END L is applied to Status B to indicate to the program that the selected drive is ready for an operation and the
previous operation is complete. Note that READY L is negated if the TU60 is performing an operation.

READY L

—q

lOT 6
(KGOA)

10— END L

REW L

E2 Jo

TP3 H
E16

E14

START

START L

'^EIS

CLEAR
ALL L

Figure 10-13

10.16

Start Logic

READ/WRITE BUFFER REGISTER

The Read/Write Buffer Register (Figure 10-14) is used during write operations to store an 8-bit byte until the drive is
ready to write it on the tape. During read operations, this register stores a word read from the tape until the
processor transfers the 8-bit byte to the AC. The Read/Write Buffer Register is an 8271 IC (see Appendix A, Volume
1 for truth table, logic diagram, and pin locations) which is parallel loaded when LOAD R/W BUFFER L is asserted
(Figure 10-13).

10-20

DATA 11 L

RW01 H

RW01 L

DATA 10 L

RW02 H

RW02 L
E47
8271

^zE^^

RW02 L

i^E)^

RW03 L

READ/WRITE

DATA 09 L

BUFFER
REGISTER

RW03 H
RW03 L

DATA 08 L

RW04 H
RW04.L

LOAD R/W BUFFER L

+5V

^A^

DATA 07 L

RW05 H

RW05

DATA 06 L

RW06 H
RW06 L

RW06 L
E39
8271

READ/WRITE
BUFFER
REGISTER

DATA 05 L

RW07 H

RW07 L

DATA 04 l.

RW08 H

RW08 L

RW08 L
CLK LD CLR DS

T~r

lOT 6 L (K60A)
READ L
WRITE DATA ENA H

Figure 10-14

Read/Write Buffer Register

10-21

LOAD R/W BUFFER L is asserted when one of the following conditions are met:
a.

XFER flag (Figure 10-15) must be set (1) and a read operation must be
XFER is set by TRANSFER RQST L each time a word is read from tape and

During read operations, the
selected by the program.

applied to the Read/Write lines (R/W 01— R/W 08). The selected drive must not be in a write status.

During write operations, if WRITE DATA ENA H (Figure 10-12)

asserted

by the Function Register

and the KGOA instruction is executed by the program. The selected drive must be in a write status.

E15

DATAd) H

E23

TRANSFER L

CLR ALL L
lOT 4 L.KGOAI—

0|>
TP3 H

JE>-I>-^
|77V--—
J
1

Figure 10-15

10.16.1

TA8-E Flags

Data Flag

The Data flag (Figure 10-15) is set each time a TRANSFER RQST is made by the TU60. When the Data flag sets,
the program is interrupted by an INT RQST if the interrupt system is turned on (bit 11 in Status A must be 1) or a
SKIP is generated if one of the SKIP lOTs are executed by the program. During read operations, the program must
execute the KGOA instruction and transfer data to the AC from the Read/Write Buffer Register. During write
operations, the
lines via the

KGOA instruction

executed and data is transferred from the AC and applied to the Read/Write

Read/Write Buffer Register. WRITE DATA ENA H enables data to be applied to the Read/Write lines

during write operations. During read operations,

READ DATA ENA L (Figure 10-16) is asserted to transfer data

from the Read/Write lines to the OMNIBUS.
10.17

INTERRUPT LOGIC

An INT RQST (Figure 10-16) is made by the TA8-E if bit 11 in the Status A Register is set (1), and the following
conditions exist:

One of the following Error flags is set.
1.

2.
3.
4.

TIME ERR
WRITE LOCK (If a write operation)

CRC/BLKERR
DRIVE EMPTY

The tape is REWINDING.
The tape is at EOT/BOT.
The Data flag is set.

END L is asserted (low).
10-22

SKIP L

E2 8

4!^

lOT 1 L(KSDR)

INT RQST L

DRIVE EMPTY L

WRITE LOCK H
WRITE DATA ENA H

Figure 10-16

Interrupt and Skip Logic

SKIP

10.18

SKIP L (Figure 10-16) is asserted and the program will skip the next instruction if one of the following conditions
exist:

The program executes a KSDR

instruction and the Data flag is set (1). The Data flag

set

when the

program must execute a data transfer during read and write operations.
b.

The program executes a KSEN instruction and the tape is at EOT/BOT or End of File (EOF).

The program executes a KSBF and the selected drive is not empty; tape drive is in the READY state and
not rewinding.

The program executes a KSAF instruction and any flag is set.

10.19

OUTPUT DATA MULTIPLEXER

The Output Data Multiplexer (Figure 10-17) is used to apply read data to the Data Bus during read operations or the
contents of Status B to the Data Bus when the KRSB instruction is executed by the program. The Output Data
Multiplexer consists of two 8235 ICs (see Appendix A, Volume 1 for truth table, logic diagram and pin locations)
that select one of two sets of inputs to be applied to the Data Bus. If the program executes a KRSB instruction, the
lOT 7 L signal is asserted and the contents of the Status B Register are applied to the Data Bus. During read
operations,

READ DATA ENA L is asserted (low) and the data on the Read/Write lines

Bus.

10-23

transferred to the Data

END L-

RW 01 H

J1-FF WRITE LOCK L

WRITE LOCK L

RW 02 H
REW L

J1-X REW

.zJfE)"
J1-J DRIVE EMPTY

J2-Z EOF L

.z^^

DATA 10 L

E42
(8235)

DATA 09 L

RW 03 HDRIVE EMPTY L

RW 04 H

DATA 11 L

P
SO

DATA 08 L

END FILE L

—q_^

E38 p-

J2-BB EOT/BOT L

RW 05 HEOT/BOT L

J2-DD TIM ERR L

TIM ERR L

J2-TT CRC BLK ERR L

RW 07 HCRC BLK ERR L

DATA 07 L

RW 06 H-

E37
(8235)

DATA 06 L
DATA 05 L

RW 08 H-

DATA 04 L

—^

SO
"V

lOT 7 L

READ DATA ENA L
'RW 01 -RW 08 FROM THE READ/WRITE BUFFER REGISTER

Figure 10-17

Output Data Multiplexer

SECTIONS MAINTENANCE
10.20

PREVENTIVE MAINTENANCE

Recommended

preventive

maintenance should

be scheduled at regular intervals to maintain

reliability

and

performance in the TU60 Cassette Tape Transport System. Preventive maintenance schedules are found in the TU60
Cassette Tape Transport Maintenance Manual {DEC-00-TU60-D A).

The TA8-E Diagnostic (MAINDEC-08-DHTAA-A) and the TA8-E Data Reliability Test (MAINDEC-08-DHTAB-A)
are supplied to checkout and test the TA8-E. The diagnostic programs and reliability tests check all logic and the
ability to read or write data. TA8-E signals can be monitored with an oscilloscope while the diagnostics are running
to aid in the location of malfunctioning components. When a malfunction is suspected, the TA8-E diagnostics should
be used to checkout and troubleshoot the TA8-E. Refer to the TU60 Cassette Tape Transport Maintenance Manua/
for test equipment, troubleshooting aids, and adjustments.

10.21

CORRECTIVE MAINTENANCE

The following programs are provided to aid in troubleshooting the TA8-E.

NOTE
A Tektronix 453A or equivalent oscilloscope with X10 scope
probe and an IC test clip are required for these tests.

10-24

10.21.1

lOT Decoder Check

To check the lOT decoder, perform the following steps:
1.

Deposit the following progrann into core memory, starting at location 0200.

Memory Location

Instruction

0200

7604
3202
0000
5200

0201

0202
0204

Operation

LAS

DCA switches in 202
Contents of switches

JMP-S to beginning

Set the Switch Register (SR) to 6700.

Load address 0200, then press CLEAR and CONT,

Set up the oscilloscope to monitor signals on channel A. Monitor SELECT H on pin 3 of El. SELECT H

should be present for 500 ns (Figure 10-18).

SYNC on channel A (SELECT H signal) and monitor pin 1 of E27 with channel B. Pin

the output

line of the lOT decoder for the 6700 (KCLR) instruction (Figure 10-9).

Change SR to 6701 and monitor logic for the 6701 instruction.

Set the Switch Register to octal values for each of the lOT instructions (Table 10-3) and monitor the
logic associated with each instruction. Refer to the M8331

module prints (D-CS-M8331-0-1).

-I-3V-

500ns-

V-

•APPROXIMATELY 6^s

Figure 10-18

10.21.2

lOT Decoder Output Signal

Status A Register Check

To check the Status A Register, perform the following steps:
1.

Deposit the following program into core memory, starting at location 0400.

Memory Location

Instruction

Operation

0400

7604
6704
5200

LAS
KLSA, Load Status A

0401

0402

10-25

JMP-2 to beginning

Set SR to 0377.

Monitor logic associated with E32 and E51 (Status A Register). Set SR4 through SR1 1 to both Os and Is
to

certain

both

can

transferred.

Monitor the gates associated

with

Status

(D-CS-M8331-0).
10.21.3

Status B Check

To check Status B signals, perform the following steps:
1,

Deposit the following program into core memory.

Memory Location

Instruction

0600

6707
5200

0601

Operation

KRSB, Read Status B
JMP-1 to beginning

With a jumper or clip lead, ground pin 4 of E38. AC bit 4 should read a 1.

With a jumper or clip lead, ground pin 7, AC bit 5 should read a 1.
4.

10.21.4

Check all of the status bits by grounding the pins of the E38 and E42 ICs (D-CS-M8331-0).
Read/Write Buffer Check

To check the Read/Write Buffer, perform the following steps:
1.

Deposit the following program into core memory.

Memory Location

Instruction

1000

CLA
TAD AC, WRITE

1002
1003
1004

7200
1300
6704
7604
6706

1005

7200

1006
1007
1010

1301

CLA
TAD AC, Read

6704
6706

Read Read/Write Buffer

1001

Operation

KLSA, Load Status A
LAS, Get Switches
KGOA, Load Read/Write
Buffer from AC

KLSA, Load Status A
Register

1011

1100
1101

5200
0020
0000

JMP-9, to beginning

Constant
Constant

Monitor pin 13 of E44 and toggle SR4. Pin 13 on E44 should follow SR4.

Repeat step 2 for R/W 07 through R/W 01 gates with SR5 through SR11 (D-CS-M8331) for pins for
R/W 07 through R/W 01.

10-26

10.21.5

Command Decoder Check

To check the command decoder, perform the following steps:
1.

Deposit the program used to check the Status A Register beginning at location 400.

Monitor FR0-FR2 and toggle SR6-SR8. The level of FR0-FR2 should change when the bit in the SR
associated with it changes.

SECTION 6 SPARE PARTS
The spare parts for the TA8-E are listed in Table 10-7.

Table 10-7

tA8-E Spare Parts

DEC Part No.

Description

19-10436

DEC IC 74123
DEC IC 7442
DEC IC 97401
DEC IC 6314
DEC IC 6380
DEC IC 8235

19-00046
19-09973
19-09972
19-09971

19-09935
19-09929

19-09705
19-09686
19-09615
19-05579
19-05577

19-05576
19-05575
19-05547

Quantity

DEC IC 7417
DEC IC 8881
DEC IC 7404
DEC IC 8271
DEC IC 7440
DEC IC 7420
DEC IC7410
DEC IC 7400
DEC IC 7474

SECTION 7

IC DESCRIPTIONS

This section contains a description of those ICs used on the TA8-E that are not used

the PDP-8/E. ICs not

included in this section are contained in Appendix A, Volume 1 of the PDP-8/E Maintenance Manual.

DEC 7442 IC
The DEC 7442 IC is a BCD-to-decimal decoder (Figure 10-19) that consists of eight inverters and ten 4-input NAND
gates. The inverters are connected in pairs to make BCD data available for decoding by the NAND gates. Full
decoding of valid input signals ensures that all outputs remain off for invalid input conditions.
In the TA8-E, the 7442 IC has a 3-bit input with the fourth bit (pin D)

used as an enabling signal that allows the IC

to have an output only when it is enabled. Thus, there will be no erroneous signals out of the decoder.

10-27

INPUT A

UTPUT

>
>
>

—r>c^.

INPUT BO-

-o OUTPUT

-OOUTPUT 2

-O OUTPUT 3

-OOUTPUT 4

>
>

INPUT C O-

-OOUTPUT

-OOUTPUT 7

INPUT D O-

OUTPUT 8

H>^
OUTPUT

OUTPUTS

INPUTS

1
1
1

23456789

01
—o—D—n—n—n—n—n—n—ar"

-Tj

1
1
1

GND

OUTPUTS
Truth Table

Figure 10-19

DEC 7442 IC

10-28

PART 8
DISKS

CHAPTER 11
RK8-E DISK DRIVE CONTROLLER

SECTION 1
11.11

INTRODUCTION

PURPOSE

The RK8-E (Figure

11-1) provides the interface between the PDP-8/E OIVINIBUS and the

RK05 Disl< Drive. As a

part of this function the RK8-E

/\
INSTRUCTIONS

STATUS
DATA

RK8-E CONTROLLER
M7104
M7105
M7106

DATA .CONTROLS, STATUS

CABLE 700-9026

RK05
N0.1

BC11

RK05
NO.

BC11A

RK05
NO. 3

BC11A

TERMINATOR
CARD

(M930)

Figure 11-1

RK8-E Controller and RK05 Disk Drive
System Block Diagram

Decodes programmed lOT instructions.

Accepts and stores current address, command, and extended memory address words.
Selects the designated RK05 and starts the designated operation.

Jointly (with the selected RK05) locates the disk address (track, sector, and surface).

Generates interrupts and skips for status checking operations.

11-1

RK05
N0.4

Generates break requests to initiate single cycle data breaks (data transfers to or from memory).

Buffers the input/output data and performs related conversions (serial to parallel and parallel to serial).

Performs housekeeping chores for single cycle data break data transfers (i.e., increments Current Address
Register and provides sequential memory addresses).

11.2

Counts bits and words in a transfer to determine when to end a data transfer.

Generates and checks CRC (parity) for each sector.

Provides flags to indicate current conditions and error status.

Provides logic to aid in the maintenance of the RK8-E and RK05.

PHYSICAL DESCRIPTION

The RK8-E consists of the following quad modules, which are inserted into the OMNIBUS and used to control up to
4 (maximum) RK05 Disk Drives.
•

M7104, RK8-E Data Buffer Register and Status Module

•

M7105, RK8-E Major Registers Module

•

M7106, RK8-E Control Module

The RK8-E modules are inserted into the OMNIBUS and connected together with H851 Top Connectors. The
RK8-E is connected to the RK05 Disk Drives by a 7009026 cable.
11.2.1

RK05 Disk Drive

The RK05 Disk Drive contains the drive electronics and mechanism for accepting and releasing the disk, positioning
the read/write heads, and reading and writing data from the RK8-E control. The drive contains a removable disk
cartridge, control logic, and a power supply. No power is supplied to the RK05 by the RK8-E, and the RK05
supplies no power to the RK8-E. Table 1 1-1

lists the

RK05 Disk Drive specifications.

NOTE
The specifications in Table 11-1 apply to the RK05 when it is
used with the RK8-E and a 16-sector cartridge. The RK05 may
be used

other systems with other controllers and sector

formats.

11.3

RECORDING METHODS AND FORMATS

This section describes the recording methods and the format used to write data on and read data from the RK05
Disk Drives.

11-2

Table 11-1

RK05 Disk Drive Specifications
Characteristic

Specification

Cylinder, Track, and Sector

Cylinder Density

200 CPI

Cylinders/Drive

203

Tracks/Cylinder

Sectors/Track

Sectors/Cylinder

Bit Density and Storage
Bit Density

2200 BPI

Bits/Cylinder

120,000

Bits/Sector

3750

Bits/Drive

24 million

Data Word Storage

Words/Sector

400g or 256

Words/Track

^Q
10,000g or 4096^Q

Words/Cylinder

20,000 or 81 92

Words/ Disk

1616K

Transfer Rate

Word Transfer

8.32 usee

Bit Transfer Rate

1440 kHz

Recording Method

11.3.1

Double Frequency

Double Frequency Recording Method

The RK8-E uses the double frequency recording method. During a write operation, the RK8-E
timing pulses called Write Data Clock pulses (Figure 11-2). The time between the

control generates

pulses is called a bit cell (space for

writing data). A pulse within the bit cell represents a data 1 and the absence of
pulse and data (0 or

a pulse represents a data 0. The clock
are sent to the drive as Write Data and Clock pulses. Each pulse is recorded on the
disk as a

flux transition. A pulse representing a data 1 and the clock pulses cause
a change in direction of current flow
through the write heads and thus a change in the magnetic flux on the surface of the disk.
Zero data bits do not

cause a change in current flow through the write head; thus, there is no change in the magnetic

flux on the surface of

the disk.

During a read operation, the drive electronics separates the bit cell flux transitions and the
bit cell flux transitions are sent to the

data flux transitions. The
RK8-E as Read Data Clock pulses and the data transitions are sent as Read

Data pulses (serial bits of data).

11-3

WRITE
WRITE DATA
690ns

WRITE DATA CLOCK

BIT

CELL

CLOCK DATA

L J

WRITE DATA CLOCK
AND DATA

DISK FLUX
TRANSITION

READ
READ DATA CLOCK

READ DATA

Figure 11-2

11.3.2

Double Frequency Recording Method

Disk Addressing

The surfaces of the RK05 Disk Cartridge are divided into 203 tracks and 16 sectors (Figure 11-3). Each surface has
one read/write head.

A drive can be commanded to seek one of 203 cylinder addresses. The drive generates a signal and supplies

to the

RK8-E when it is on the correct cylinder address. When the drive completes a seek, it is advisable to check the
cylinder address to ensure the heads are positioned correctly.

The RK8-E can be commanded to read the cylinder address (HEADER) from the first cylinder it finds and check
this against the cylinder address it previously sent to the disk drive. If the two addresses agree, the controller starts a
data transfer; if they do not agree, an ERROR flag is set. The program must determine what to do about the

ERROR flag.
A drive performing a seek can be deselected and another drive selected and commanded to seek; thus, overlapped
seeks are possible.

11.3.3

Sector Format

The sector format (Figure 11-3) consists of a 140 /xs PREAMBLE of zero data bits (time pulses only), a SYNC bit
(data bit = 1), a 16-bit HEADER word containing the cylinder address, 256 12-bit data words, a 16-bit Cyclic
Redundancy Check (CRC) character, and a 25 /xs POSTAMBLE (erase delay zone).
11.3.3.1

HEADER Word - The HEADER

a 16-bit

word containing 5 zero bits and a 8-bit cylinder address

followed by 3 zero bits.

11-4

SECTOR FORMAT
140ps

PREAMBLE
(ALL OS)

HEADER

SYNC
DATA =

(16
1

BIT

WORD)

CRC

256
DATA WORDS
WORDS)

(16

BIT

WORD)

(12 BIT

POSTAMBLE/ERASE
DELAY ZONE

(25;js)

V-

DISK SURFACE
*

SURFACE
SECTOR ADDRESS Os TO ITq ON UPPER OR
SECTOR ADDRESS ZOr TO STo ON LOWER OR 1 SURFACE TOTAL OF 32 SECTORS (16 ON TOP AND 16 ON BOTTOM)
8E-0528

Figure 11-3

11.3.3.2

Disk Format

CRC Character - Data is recorded on the RK05 in blocks of 256 12-bit words (serial data); thus, each

block contains 3072 bits of data recorded

a single string,

with no separations to indicate word boundaries or

record error checking bits.

A long string of data bits

susceptible to single bit errors caused by dropins, dropouts, or burst errors. Burst errors

Check
are caused by unwanted physical motion of the read/write heads. The RK8-E generates a Cyclic Redundancy
(CRC) character to check for these errors. The CRC is a block check character that is calculated by the RK8-E
during a read or write operation. The CRC character calculated during a write operation is written immediately
following the data (Figure 1 1-3) and becomes part of the data string. The process used to calculate the block check
word is such that if no errors occur, the CRC word calculated while reading data is identical to that calculated during
a write operation.

To calculate a CRC word, the data block is feated as a number 3072 bits long which is divided by a polynominal
(X**

-I-

X^^ + X^ + 1). The hardware required to do this is a shift register with Exclusive OR gating (division being

shift and subtract).

A maintenance instruction allows the program to read the CRC character written on the disk or the CRC character
read from the disk.

11-5

11.3.3.3

Formatting A Cartridge - A disk cartridge is "formatted" when the cylinder address of a sector is written

the HEADER

word of each sector. A special bit in the Command Register allows the program to write HEADER
words in each sector (format). The program need only set the bit and write something in each sector. The RK8-E
in

control writes the cylinder address automatically

program writes coded information

the HEADER area (Figure 11-3) of each sector. The formatting

the data region of each sector and reads

back to verify that the disk is

formatted correctly.

During a normal read or write operation, the disk seeks a cylinder specified by the RK8-E and reads the HEADER

word of the first sector it finds after the seek is complete. This HEADER word is compared with the cylinder
address specified by the RK8-E to ensure the correct cylinder has been found. The control then waits until the
sector containing the address specified by the program passes under the read/write heads before reading or writing
data.

11.3.3.4

Write Protect - WRITE

PROTECT is turned on at the RK05 Disk Drive or by a bit in the Command
loaded by the program. WRITE PROTECT must be turned off by pressing a manual control (WT

PROT) on each disk drive. If the program attempts to write on a disk that is write protected, the write operation is
inhibited and an error condition

pressing the

produced. WRITE

PROTECT may be turned on manually at the RK05 by

WT PROT switch.

MAJOR REGISTERS

11.4

The major registers of the RK8-E are in two broad categories: those that are loaded or read by user software and
those that are transparent to user software. The first category includes the Command Register, Current Address
Register, Disk Address Register and Status Register. The second category includes the 4-word Data Buffer Register,
the CRC Register, Major State Register, Modulo 12- and Modulo 16-bit counters, and the Modulo 128- or 256-Word
Count Register.
The major registers must be loaded from the AC by lOT instructions in the correct sequence before they perform
any control function. The individual flip-flops in the registers are set by a 1 (true) and cleared by a
the

(false) bit from
AC. Refer to Section 3 for a list of lOT instructions and a detailed discussion of the contents of each major

11.4.1

Command Register

The Command

loaded from the AC by lOT 6746. This lOT also clears the AC and the

Status Register.

1 1 .4.2

Current Address Register

The Current Address Register is a 12-bit register loaded from the AC with lOT 6744, which also clears the AC. This
register

and 3 bits of the Command Register (Figure 11-4) are combined to make up a 15-bit Memory Address
CA Register and the 3 bits in the Command Register are applied to the OMNIBUS to

select a memory location during a data transfer. The CA Register is incremented before each data transfer to select
the next sequential memory location. The EMA bits in the Command Register are not incremented, and these bits

must be changed by the program to select new memory fields. If the CA Register is incremented past the last
memory location in a field, it will wrap around in the same field. The data is stored in location 000 and starts
incrementing through the field again.
1 1 .4.3

Disk Address Register

The Disk Address Register is loaded from the AC by lOT 6743, which also clears the AC and enables the contents of
the Command Register to be applied to the control logic.

11-6

ENABLE

TRANSFER
128 WORD
BLOCK

INTERRUPT
ON DONE

BIT BIT BIT

CYLINDER
ADDRESS

BIT

MEMORY FIELD

DONE

READ DATA
READ ALL

SET WRITE PROTECT

SEEK ONLY

WRITE DATA
WRITE ALL

NOT USED
NOT USED

SIGNIFICANT

ENABLE
DONE

FUNCTION

MOST

•

FLAG
BIT BIT BIT

EMA2 EMA1 EMAO
EXTENNDED MEMORY
ADDRESS

6
7
'

BIT BIT
9 10

DRIVE

2
3

8E-0610

Figure 11-4

Contents of Connmand Register

The Disk Address Register selects a sector to be used in a data transfer. To select an individual sector, the following
must be selected (Figure 11-5).

Ip/n

ICOMMAND
1

—J

V.jURFACE \^^

SECTOR 8E-0609

Figure 11-5

of 203 cylinders

of 2 surfaces

of 1 6 sectors

Disk Address Register

The Disk Address Register and bit 11 in the Connmand Register (Figure 11-4) are combined to select a cylinder,
surface, and sector. The largest valid address is 145378 (cylinder address 202io).

11-7

11.4.4

Status Register

The Status Register (Figure 11-6) contains all the infornnation needed for the program to evaluate the operation of
the RK8-Eand RK05.

L,CYLINDER ADDRESS ERROR

CONTROL DONE-

RDYS/R/W-

DRIVE STATUS ERROR

— DATA REQUEST LATE

NOT USED-

1— CRC ERROR

SEEK FAIL—'
FILE NOT

WRITE LOCK OUT ERROR

READY—"
BUSY ERROR-

— TIME OUT ERROR

1=TRUE
0= FALSE

Figure 11-6

11.4.5

Contents of Status Register

Data Buffer Register

memory and a drive pass through the 4-word Data Buffer Register (DBI through DB4).

All data transfers between

This 4-word register increases the latency of the RK8-E control from 6.2 /lis with a single serial register and one data
buffer to 22.5 [is with 4 Data Buffer Registers. Latency is defined as the maximum time the RK8-E control waits for
access to the computer memory before data is lost. The numbers given above are for a memory cycle time of 1.2 jus.

During a read operation. Data Buffer 1 accepts the serial data from the drive and transfers a complete word to the
last

unused buffer, which

eventually removed from Data Buffer 4 and transferred to computer memory. On a

write, data from computer memory enters Data Buffer 1 in parallel mode, transfers to the last unused buffer, and is

shifted out to the drive as a 12-bit serial word from Data Buffer 4.

During maintenance operations, the contents of the CRC Register, Command Register, and the Surface/Sector
Register (disk address) are shifted into Data Buffer 4 by the maintenance lOT for transfer to the AC or memory.

11.4.6

CRC Register

The CRC Register is a 16-bit register used to calculate the CRC character that is written onto the disk after the last
data word. During a read,

calculates the CRC of the read data and does a bit-by-bit comparison with the CRC

word read from the disk. It also contains the cylinder address loaded from the AC by the Load Address and GO
instructions. The CRC Register does a bit-by-bit comparison of the HEADER word to confirm that the selected
drive has found the correct cylinder address.

NOTE
The CRC Register and the Disk Address Register are physically
the same logic with multipurposes.

1 1 .4.7

Major State Register

The Major State Register (Table 11-2 and Figure 11-7) is the control sequencer of the RK8-E; with its associated
gating, this register performs the major portion of the control functions of the RK8-E. The Major State Register is
incremented from one state to another, and its decoded outputs gate signals to or from the disk and perform
housekeeping tasks such as determining whether the control is in the HEADER region, data region or CRC region of
the disk format.

11-8

Table 11-2

Major States
Operation

Seek Seek

Major

Seek Check Check Seek Seek
Read Write Read Write

Function
State

IDLE

Control is not busy until the GO

Command (DLAG) is issued and the
contents of the AC are loaded into the

CRC. The CRC Register contains the
Cylinder/Surface Address (Disk Address)

STROBE

Strobe the Cylinder Address from the

CRC Register to the Disk Drive and
wait for the Disk Drive ADDRESS

ACKNOWLEDGE signal.
DRIVE
SEEKING

Wait for DISK READY to SEEK, READ,
or WRITE from the Disk Drive to
indicate the heads are positioned over

the Cylinder Address.

HEADER A

Wait for the first Sector Mark, then
start

HEADER B

READ DELAY.

At the end of READ DELAY turn the

READ flip-flop on. Zeros are read
until the SYNC bit is read at the beginning of a block of data.

HEADER C

Read the 16-bit HEADER word and

compare it with the cylinder address

SECTOR
SEEK

the CRC Register.

the HEADER word does not equal

the cylinder address set CYLINDER

ADDRESS ERROR and go to IDLE
state.

At each sector mark compare the

sector address with the Disk Sector

Address lines

the addresses are equal

go to the next state,

if this is

a write

operation transfer data from the processor to the Data Buffer Register.

11-9

Table 11-2 (Cont)

Major States
Operation
Seel<

Major
Function

State

HEADER D

At the beginning of the sector start

(Read)

READ DELAY (85 jus). At the end of
READ DELAY set the READ flip-flop.
Note zeros are read until the SYNC bit
is

Seek

Seek Check Check Seek Seek
Read Write Read Write

read.

HEADER D

At the beginning of the sector start

(Write)

SYNC DELAY. Zeros are written
during SYNC DELAY time and after
SYNC DELAY times OUT (140 /js) a
one SYNC bit is written.

HEADER E

Count and ignore the first 16 bits.

(Read)

HEADER E

Write the HEADER word contained

(Write)

the CRC Register.

DATA STATE

Read 256 12-bit data words and a 16-

(Read)

bit

X
X

CRC character from the Disk and

compute a CRC. The 12 bit data words
are transferred to the Data Buffer

the Data Buffer Register empty by transferring data to the processor via the single

cycle data break.

DATA STATE

Write 256 data words on the Disk Drive.

(Write)

The Data words are transferred.from the

processor via the Single Cycle Data Break.

CRC STATE

Read the CRC from the Disk Drive and

(Read)

compare it with the CRC computed by

the controller.

CRC STATE

Write the computed CRC on the disk

(Write)

after 256 data words have been written.

11-10

Table 11-2 (Cont)
Major States
Operation

Seek

Major"^
Function

State

END STATE

Seek

Seek Check Check Seek Seek
Read Write Read Write

the CRC character read from the Disk

Drive does not equal the computed CRC,

(Read)

CRC ERROR flag and clear Read.

set the

When the Data Buffer Registers are
transferred into processor memory, set

the DONE flag and go to the IDLE state

(Write)

to the

DELAY and Write zeros.
At the end of ERASE DELAY (25>is)
clear WRITE, set the DONE flag and go

Start ERASE

END STATE

IDLE state.

SECTOR MARK

SYNC BIT
•TP3

WAIT
FOR
READ
READ
SILO
CRC
256 WORDS
(12 BIT WORDS) WORD EMPTY

READ

STROBE

\ IDLE
1

DRIVE
SEEKING

HEADER

SECTOR
SEEK

HEADER

DATA

CRC

END

STATE

idle\
1

TO
SEEK ONLY GO
^"''
nt
IDLE A^(U St
DONE F LAG
IF

SE EK STATE

8 £-0529

Figure 11-7

11.4.8

SET THE
DONE FLAG

NOT A HEADER

Read and Write Flow Diagram

Bit Counters

The Modulo 12-bit counter determines PDP-8/E data word boundaries. The Modulo 16-bit counter determines where
the HEADER and CRC character are, so that the control knows when to check the HEADER and CRC characters.

11-11

1 28- or

1 1 .4.9

256-Word Counter

This register counts the output of the 12-bit counter to determine when the correct

number of data words (normally
256 words) have been transferred to or from the disk. When the half block bit is set in the Command Register, the
128th word stops the data transfer instead of the usual 256th word.

COMPANION DOCUMENTS

11.5

The following is a list of companion documents needed to operate and maintain the RK8-E.
a.

PDP-8/E, PDP-8/F, and PDP-8/M Small Computer Handbook - DEC1 973.

PDP-8/E Maintenance Manual, Volumes

Introduction to Programming - DEC 1973 Volumes

and II.

DEC Engineering Drawings, M7104-0-1, M7105-0-1, and M7106-0-1.

RK05 Disk Drive Maintenance Manual (DEC-00-RK05-DA).

11.5.1

Software

The following programs and associated documents are used in the maintenance

of the RK8-E.

RK8-E Diskless Control Diagnostic, MAINDEC-08-DHRKA-A-PB or D

R K8-E Drive Control Diagnostic, MAI NDEC-08-DHR KB-A-PB or D

RK8-E Disk Formatter, MAINDEC-08-DHRKD-A-PB or D

RK8-E Data Reliability Test, MAINDEC-08-DHRKC-A-PB or D

NOTE
The MAINDEC number is followed by PB for papertape and D
for Document, I.e., MAINDEC-08-DHRKA-A-PB for binary
tape and MAINDEC-08-DHRKA-A-D for the diagnostic
document. The latest revision of these documents and
programs should be used to run RK8-E diagnostics.

SECTION 2 SITE PREPARATION, INSTALLATION, AND ACCEPTANCE TEST
The RK8-E is installed on site by DEC Field Service personnel. The customer

should not attempt to unpack, inspect,

install, checkout, or service the equipment.

11.6

SITE PREPARATION

Adequate site planning and preparation simplifies the installation process
reliable

RKS-E

installation.

DEC Sales

and results in a more efficient and more

Engineers or Field Service Engineers are available for counseling
and

consultation with the user regarding the installation.
Site planning should include a list of the actual components
to be used in the installation. This list should include
such Items as storage cabinets. Teletype supplies, work tables, etc.

11-12

Primary requirements for installation of the RK8-E are:

A Teletype, Programmer's Console, and at least 4K of read/write memory must be available to run the

RK8-E diagnostics.
Adequate space and power must be supplied for the RK05 Disk Drives (refer to Chapter 10 of the RK05
Disk Drive l\/laintenance l\/lanual for power and space requirements).

NOTE
The RK8-E receives +5V, 3A of power from the OMNIBUS.

11.7

RK8-E diagnostics and documents must be available to checkout the RK8-E and RK05 (Paragraph 11.5).

Software to format RK05 disk cartridges must be available (Paragraph 11.5).

INSTALLATION

Perform the following steps to install the RK8-E:

Procedure

Step

Unpack and

inspect

RK05, using the RK05 Dis/< Drive l\/laintenance l\/fanual. Volume 2,

Paragraph 2.1, RK05 Field Installation and Acceptance Procedure.

Using the inventory list shipped with the equipment, verify all items have been received.

Ensure that PDP-8/E power is turned off.

Ensure correct jumpers are installed to select the device code assigned to this RK8-E. The

M7104 is normally shipped with the 674X device code selected, but 675X through 677X
device codes may be used (Table 11-3).
5

Install jumpers to select priority assigned to this RK8-E

Connect the 7009026 cable to the Berg connector on the M7106 module.

Insert the
I

11.8

(Table 11-4).

RK8-E modules into the OMNIBUS (Figure 11-8). Refer to Table 11-5 in Volume

of the PDP-8/E Maintenance i\^anua/ ior module installation priority.

Install

H851 Top Connectors between the modules (Figure 11-8).

ACCEPTANCE TEST

The following diagnostics must be run in the order shown and the specified number of passes to check the RK8-E.
(Refer to the diagnostic document for instructions to run the diagnostic).
a.

RK8-E Diskless Control Diagnostic, MAINDEC-08-DHRKA-A-PB (2 passes)

RK8-E Drive Control Diagnostic, MAINDEC-08-DHRKB-A-PB (1 pass)

RK8-E Formatter, MAINDEC-08-DHRKD-A-PB (1 pass)

RK8-E Data Reliability Test, MAINDEC-08-DHRKC-A-PB (1 pass)
11-13

Table 11-3
Device Select Jumper Installation
Octal

Code

Install

following Jumpers on M7104 Module

W2
W4
W6
W2
W4
W3
W2

674X

675X

676X

W6
W2

677X

W3
Table 11-4

RK8-E Priority Selection
Priority
Priority

W2
W3
W5

(highest)

Priority

Jumpers

Install

H851

EDGE
CONNECTORS

L^u:

=fta

-M7106

CABLE
D-AD-7009026-0-0
WITH M993

"
CABLE
D-AD-7009026-0-0
WITH M993

-M7105

-M7104

9=^

PDP8/E
OMNIBUS"
'

PDP8/E
OMNIBUS

Figure 1 1-8

RK8-E Module Installation

11-14

RK8-E INTERFACE

11.9

One 7009026 cable is used to connect the RK8-E controller to the first RK05 Disk Drive (four maximum). Note
RK8-E is connected to only one drive and the input to and output from the RK05 are daisy-chained to the

that the

other three disks (the connectors on all four disk drives are connected in parallel by BC1 1 A cables). The
7009026
cable is connected from two Berg connectors on the M7106 module to slot A07, A08, B07,
or B08 on RK05 Disk
Drive located closest to the RK8-E (Tables 11-5 and 11-6). The RK8-E modules on the OMNIBUS
are tied together
by H851 Top Connectors. The signals of the pins of the top connectors are shown in Tables 11-7 through 11-10.
These tables give the origin of signals on the top connectors for troubleshooting and signal monitoring.

An M930 Terminator Card must be installed in the unused interface slot of the last RK05 Disk D rive.

Table 11-5

RK8-E-RK05 Interface Cable (P2)
Connector J2

on RKB-E
Pin No.

Description

GND

DSK CAP EX L

The address sent to the selected disk drive was greater than
3128. (low=true)

DSK SEEK FAIL

GND

DSK ACKNOWLEDGE L

GND

DSK SEC 2 L

GND

DSK DRIVE 3 L

GND

DSK RESTORE L

GND

DSK DRIVE 2 L

GND

DSK CYL ADD 4 L

GND

Disk failed to seek the address specified

Disk has received and acknowledged the disk address

Disk sector address bit 1 (low=1)

Select disk drive 3 (low=true)

Recalibrate the selected disk drive (low=true)

Select disk drive 2 (low=true)

Disk cylinder address bit 2 (low=1)

11-15

Table 11-5 (Cont)

RK8E-RK05 Interface Cable (P2)
Connector J2

on RK8-E
Description

Pin No.

DSK DRIVE 1 L

GND

DSKCYLADD

GND

DSK DRIVE OL

GND

DSK CYL ADD 32 L

GND

DSK RDY S/R/W L

GND

DSKCYLADD 128 L

GND

DSKWRTCLK
DATAL

GND

DSKCYLADD 16 L

GND

DSK CYL ADD 64 L

GND

DSK CYL ADD 2 L

GND

DSK CYL ADD 8 L

GND

Select disk drive 1 (low=true)

Disk cylinder address bit

Select disk drive

(low=1)

(low=true)

Disk cylinder address bit 5 (low=1)

Selected disk drive ready to read, write, or seek

Disk cylinder address bit 7 (low=1)

Disk write clock data (low=true)

Disk cylinder address bit 4 (low=1

Disk cylinder address 6 (low=1)

Disk cylinder address bit 1 (low=1)

Disk cylinder address bit 3 (low=l)

11-16

Table 11-6

RK8-E-RK05 Interface Cable (PI)
Connector J1

on FtK8-E
Pin No.

Description

Signal

Not used

GND

DSK DATA IN L

GND

DSK RDCLKL

Serial Data from the disk drive

Clock pulses from the selected disk drive during

a read

operation

GND

DSK WRT PROTECT L

Disk write protect (low=true). The selected disk drive does

not write if this signal is true

GND

DSK READ L

GND

Not used

GND

DSK WRT STATUS L

GND

DSK SECTOR MK L

GND

DISK FILE RDY L

Disk read (low=true) causes the selected disk drive to read

Disk Write Status L (low=true. Disk OK)

Disk sector mark (low=true) from the selected disk drive

The

selected

disk

drive

ready to read or write data

(low=true)

GND

DSK HEAD SEL 1

Disk head select

bit;

when this bit is a 1, the lower or 1

surface of the disk cartridge is selected

11-17

Table 11-6 (Cont)

RK8-E-RK05 Interface Cable (PI)
Connector J1

on RK8-E
Pin No.

Signal

GND

DSK INDEX MKL

GND

DSK WRT ERASE
GATE L

GND

DSKSEC1 L

Description

Disk index mark (low=true) from the selected disk drive

Disk write erase gate (low=true)

Disk sector address bit

(low=1) from the selected disk

drive

GND

DSK SEC 4 L

GND

Not used

GND

DSK SEC 8 L

Disk address bit 2 {low--=1 ) from the selected disk drive

Disk sector address bit 3 (low=1) from the selected disk
drive

GND

Not used

GND

DSK STROBE L

GND

Not used

GND

Not used

Disk strobe enables the disk to receive disk address

11-18

Table 11-7

M7104 Top Connector Signal List
Signal

12TH BIT OK H

Pin No.

HM1

Origin

M7106

Description

Output of the divide by 12 counter each time 12 bits
are read or written

6RK3 0KH

HS1

6RK3 (DLAG) load disk address and go if RK8-E is

M7104

in the

IDLE state

6RK3 0KL

HS2

M7104

Same as 6RK3 H except low is true

6RK4L

JS2

M7104

6RK4 (DLCA) load Current Address Register

6RK6H

HR1

M7104

6RK6 (DLDC) load Command Register

6RK7H

JC1

M7104

6RK7 (DMAN) maintenance instruction

6RK7 OK H

HN2

M7104

6RK7 (DMAN) OK asserted only at TP3 time

WRTBRKL

HH1

M7105

Write break request (use DB1 for data transfer)

READBRK L

HL2

M7105

Read break request (use DB4 for data transfer)

B DATA 10

JA2

M7104

Buffered data bus bit 10 (high=true) (1)

B DATA 10

JP2

M7104

Buffered data bus bit 10 (low=true) (1)

B DATA 1 1 H

JR1

M7104

Buffered data bus bit 11 (low=true) (1)

B DATA 1 1 L

JH1

M7104

Buffered data bus bit 11 (low=true) (1)

BRKDIR (0) H

HP2

M7105

Controls state of MD DIR L on the OMNIBUS

BTP3 OK H

HKl

M7104

Asserted at

TP3 time if the RK8-E is in the IDLE

state for timing

CLR DRVCMDL

JC2

Clear commands to the selected disk drive (see DCLR

M7104

instruction and Table 11-11)

CLR ALL H

HD1

M7104

Clear

all

logic

(see

DCLR

instruction

and Table

11-11)

CLR ALL L

JU2

M7104

Same as CLR ALL H except low=true

DRV REVO H

JD2

RK05

Disk has read an index mark

DSK CAPACITY EX L

JK1

RK05

Disk capacity exceeded, a cylinder address greater

than 3128 was sent to the disk drive

DSKFILERDYL

HE1

RK05

Selected disk drive is ready

11-19

Table 11-7 (Cont)

M7104 Top Connector Signal List
Pin No.

Origin

DSK WRT STATUS

JD2

RK05

Selected disk drive is in a write status

SET IDLE PL L

JJ1

M7104

Set the IDLE state flip-flop

ENAB INTH

JB1

M7105

Enable the interrupt logic (see Table 3-2)

ENAB SEEK DONE H

JS1

M7105

Signal

Description

Enable seek done if bit 3 in the Command Register is
set

END STATE (0) H

JJ2

M7106

The RK8-E is in the END state

ERROR CLR L

JD1

M7104

Clear the ERROR flip-flop

RDCLKH

JM1

M7105

Maintenance clock or clock from the disk during a

read

HI DATA IN H

JR2

M7105

IDLE (0) H

JNl

M7106

Maintenance data or data from the disk during a read

RK8-E

not

IDLE

state

when this signal

(high)

IDLE (1) H

JL2

M7106

RK8-E is in IDLE state when this signal is 1 (high)

LAST WORD PL H

JN2

M7106

Output of the word counter each time 256 words are
read or written

LDCMD REG H

JP1

Load Command Register asserted by 6RK6 (DLDC at

M7105

TP3 time)

LO MAIN DATA H

HV2

M7105

Load main data

LOMAINSHFTL

HP1

M7105

Shift main data

MAIN (0) H

JE1

M7105

Clear side of MAIN enable flip-flop. This signal is true
when the MAIN flip-flop is cleared (normal

operations)

MAIN (1) H

HA2

M7105

Set side of
the

MAIN

MAIN flip-flop. This signal is true when
flip-flop

set

enable

maintenance

operations

B DATA 01 H

HT2

M7104

Buffered data bus bit 1

NOT EQUAL (0) H

JF2

M7105

The cylinder address sent to the disk and the cylinder
address read after seek is complete are not equal

11-20

Table 11-7 (Cont)

M7104 Top Connector Signal List
Description

Pin No.

Origin

RDYS/R/WL

HU1

RK05

Selected disk drive ready to seek, read, or write

B TP;2 H

HC2

M7104

Buffered time pulse 2

SECTOR SEEK (0) H

JF1

M7106

Signal

RK8-E is in sector seek state if sector seek (0) is true
high

SEEK FAILH

HU2

RK05

Selected disk drive failed to seek

MAIN PLH

HT1

M7105

See maintenance instruction and Table 11-14

DATA ENABLE (1) H

HN1

M7105

Enable

gate

apply

MA and EMA bits to the

OMNIBUS

DATA STATE (0) H

JM2

The RK8-E is not in data state when this signal is high

M7106

(0)

B DATA STATE (1) H

HL1

The RK8-E is in the data state when this signal is high

M7106

(1)

DB CONT 1 (0) H

HV1

M7106

Data buffer 1 control

DB CONT 4(1) H

HE2

M7104

Data buffer 4 control

DEVICE RKH

JA1

M7104

device

RK is high (true), the RK8-E is selected for

this operation

BTP3H

JT1

M7104

Buffered time pulse 3

DRIVE STATUS BAD H

JH2

RK05

Selected disk drive not operational (Table 11-12)

WRITE (1) H

HM2

M7106

WRITE function is (1) high when a write operation is
selected

WRTCMD L

JE2

M7106

WRT command to the disk during a write operation

WT BUFF TO DATA L

HD2

M7104

Transfer

DB4

the

data

lines

(used

during

maintenance operations to transfer contents of DB4
to the AC)

RK DATA 11 H

HF1

M7104

Disk data bit 1

LD DISK ADDRESS H

JB2

M7106

Load Disk Address Register when asserted by 6RK3

SHFTWRTBUFF L

HR2

M7106

Shift write buffer (DB4)

AC7 (0) H

HB1

M7104

Bit 7 from the

11-21

Table 11-7 (Cont)

M7104 Top Connector Signal List
Pin No.

Origin

RDYS/R/WSLOH

JL1

RK05

Selected disk drive ready to seek, read, or write

BRKRQH

HAl

M7105

Break request

BBRK RQH

HB2

M7104

Buffered break request

MAK (0) H

HJ1

M7105

Data BRK RQST accepted {RK8-E has priority)

DATA CLK OK H

HC1

M7106

Data clock OK

Signal

11-22

Description

Table 11-8

M7105 to M7104 Top Connector Signal List
Signal

12TH BIT OK H

Pin No.

HM1

Origin

Description

M7106

Output of divide by 12 counter each time 12 bits are
read or written

6RK3 0KH

HS1

M7104

6RK3 (DLAG) load disk address and go if RK8-E is
in the

IDLE state

6RK3 0KL

HS2

M7104

Same as 6RK3 H except low=true

6RK4 L

JS2

M7104

6RK4 (DLCA) Load Current Address Register

6RK6H

HR1

M7104

6RK6 (DLDC) load command address

6RK7H

JC1

M7104

6RK7 (OMAN) maintenance

6RK7 0KH

HN2

M7104

Same as 6RK7 except it is enabled at TP3 time

WRTBRK L

HH1

M7105

Write break request (use DB1 for data transfer)

READ BRK L

HL2

M7105

Read break request (use DB4 for data transfer)

B DATA 10

JA2

M7104

Buffered data bus bit 10 (high=trj3)

B DATA 10 L

JP2

M7104

Buffered data bus bit 10 (low=true)

B DATA 1 1 H

JR1

M7104

Buffered data bus bit 1 1 (high=true)

B DATA 1 1 L

JH1

M7104

Buffered data bus bit 1 1 (low=true)

BRKDIR (0) H

HP2

M7105

Controls MD DIR L on the OMNIBUS

B TP3 OK H

HK1

M7104

Buffered time pulse 3

CLR DRIVE CMD L

JC2

M7104

Clear selected disk drive (DCLD)

CLR ALLH

HD1

M7104

Clear

all

logic

(see

DCLR

instruction

and Table

11-11)

CLR ALL L

JU2

M7105

ENABLE DATA(I) H

HN1

M7105

Same as clear all H except low=true
Enable gates to apply

MA and EMA bits to the

OMNIBUS

DATA STATE (0) H

JM2

M7106

The RK8-E is in the DATA state (data transfers are
enabled)

B DATA STATE (1) H

HLl

Buffered DATA state

M7106

11-23

Table 11-8 (Cont)

M7105 to M7104 Top Connector Signal List
Signal

Pin No.

Description

Origin

DB CONT 1 (0) H

HV1

M7104

Data buffer 1 control

DBC0NT4 (1) H

HE2

M7104

Data buffer 4 control

DEVICE RKH

JA1

M7104

device

RK is high (true), the RK8-E is selected for

this operation

BTP3H

JT1

M7104

Buffered time pulse 3

DRIVE STATUS BAD H

JH2

M7105

The selected disk drive is not ready (Table 11-12 bit
10)

WRITE (1) H

HM2

M7106

The write function is selected

WRTCMD L

JE2

M7106

Write command to selected disk drive

WT BUFF TO DATA L

HD2

M7104

Transfer contents of write buffer (DB4) to the Data
lines

RK DATA 11 H

HF1

M7104

Disk data bit 1 1

LD DISK ADDRESS H

JB2

M7106

Load Disk Address Register when asserted by 6RK3

SHFTWRTBUFF L

HR2

M7106

Shift the Write Buffer out to the disk drive

AC7 (0) H

HB1

M7104

Bit 7 from the

RDY S/R/W H

JL1

M7105

Selected disk drive ready to seek, read, or write

BRK RQH

HA1

M7105

Break request

BBRK RQH

HB2

M7105

Buffered break request

MAK (0) H

HJ1

M7105

Data

(serial data to disk)

BRK RQST has been accepted

(RK8-E has

highest priority)

DATACLKOKH

HC1

M7106

DRV REVOH

JK2

M7106

DATA clock OK
Disk index mark

applied to

RK8-E during IDLE

state

DSK CAPACITY EX L

JK1

RK05

Disk capacity exceeded, address greater than 3128
sent to the disk drive

DSK FILE RDYL

HE1

RK05

Selected disk drive is ready (on-line)

DSK WRT STATUS L

JD2

RK05

Disk drive write status (low=true)

11-24

Table 11-8 (Cont)

M7105 to M7104 Top Connector Signal List
Signal

Pin No.

Description

Origin

SETIDLEPLL

JJ1

M7104

Set IDLE state flip-flop

ENAB INTH

JB1

M7105

Enable interrupt logic (Table 11-12)

ENAB SEEK DONE H

JS1

M7105

Enable seek done if bit 3 in Command Register is set

END STATE (0) H

JJ2

M7106

RK8-E in the END state when asserted

ERROR CLR L

JD1

M7104

Clear the ERROR flip-flop

RDCLKH

JMI

M7105

Main clock OR clock from the disk during a read

HI DATA IN H

JR2

M7105

Serial

IDLE (0) H

JN1

M7106

DATA from the disk drive during a read

RK8-E is not in the IDLE state when this signal is
high

IDLE (1) H

JL2

M7106

RK8-E

the

IDLE

state

when this signal

(high)

LAST WORD PL H

JN2

M7106

Output of word counter each time 256 words are
read or written

LDCMD REG H

JP1

M7106

Load Command Register (DLDC)

LO MAIN DATA H

HV2

M7105

Maintenance data (Table 11-14)

LOMAINSHFTL

HP1

M7105

Maintenance shift pulse (Table 11-14)

MAIN (0) H

JE1

M7105

Maintenance command (DMAN instruction)

MAIN (1) H

HA2

M7105

Maintenance command (DMAN instruction)

B DATA 01 H

HT2

M7104

Buffered data bit 2

NOT EQUAL (0) H

JF2

M7105

The cylinder address sent to the disk and the cylinder
address read after seek is complete are not equal

RDYS/R/WL

HU1

RK05

Selected disk drive ready to seek, read, or write

B TP2 H

HC2

M7104

Buffered time pulse 2

SECTOR SEEK (0) H

JF1

M7106

RK8-E is in sector seek state if sector seek (0) is true
high

SEEK FAIL H

HU2

RK05

Selected disk drive failed to seek

MAIN PL H

HT1

M7105

See maintenance instruction and Table 11-14

11-25

Table 11-9

M7105 to M7106 Top Connector Signal List
Signal

12TH BIT OK H

Pin No.

FA1

Origin

Description

M7106

Output of divide by 12 counter each time 12 bits are
read or written

6RK3 0KH

FA2

6RK3 (DLAG) load disk address and go if RK8-E is

M7104

IDLE state

B DATA 7 H

ER2

M7104

Buffered data bit 7 (high=true) (1)

B DATA 10

EKl

M7104

Buffered data bit 10 (high=true) (1)

B DATA 1 1 H

EJ1

M7104

Buffered data bit 11 (high=true) (1)

CLR DRIVE CMDL

FB2

M7104

Clear commands to the selected drive

CLR ALLL

EH1

M7104

Clear

all

logic (see the

DCLR instruction and Table

11-11)

DATA STATE (0) H

FP1

M7106

Data state (read or write data)

BTP3H

FJ1

M7104

Buffered time pulse 3

DRV REVOH

FC2

M7106

Disk index mark is applied to the RK8-E during IDLE
state

DSK FILE RDY L

FBI

RK05

Selected disk drive is operational

DSKWRT STATUS L

FD2

RK05

Selected disk drive is in a write status (low=true)

SET IDLE PL L

FK1

M7104

Set the IDLE state flip-flop

END STATE (0) H

FD1

M7106

END state (true=0)

ERROR CLR L

FE2

M7104

Clear the ERROR flip-flop

IDLE (0) H

FR2

M7106

The RK8-E is not in the IDLE state when this signal
is

IDLE (1) H

EC1

M7106

(0)

high

The RK8-E is in the IDLE state when this signal is (1)
high

LAST WORD PL H

FE1

LAST WORD is asserted when 256 words are read or

M7106

written

MAIN (0) H

FP2

M7105

Clear side of MAIN flip-flop. This signal is true when

the RK8-E is not in the maintenance mode

RDY S/R/W H

EDI

M7105

Selected disk drive is ready to seek, read, or write

11-26

Table 1 r 9 (Cont)
M7105toM7104Top Connector Signal List
Signal

DATA ENABLE (1) H

Pin No.

EU1

Origin

M7105

Description

Enable gates to apply

MA and EMA bits to the

OMNIBUS
SECTOR SEEK (0) H

FF2

M7106

The RK8-E

the sector seek state

SECTOR

SEEK is true (high)

LASTBRK(1)H

FN2

M7105

Last break (1=true) ends data transfer operations

WRITE (1) H

FF1

M7106

The write function is selected by the program

WRTCMD L

FV2

M7106

Write command to the RK05

BTP2H

FH2

M7104

Buffered time pulse 2

B DATA 8 H

EMI

M7104

Buffered data bus bit 8

B DATA 9 H

ELI

M7104

Buffered data bus bit 9

BRK ENABLE CLKH

FK2

M7106

Break enable clock pulse

BRK IN CLKH

FU2

M7106

Break in clock pulse

CLR CNTRS L

FS1

M7106

Clear counters asserted by CLR ALL, DATA CLR, or

HEADER E during STATE ENABLE
CLR SECTOR AD L

EF1

M7105

Clear Sector Address Register

CRC 16(1) H

EN2

M7105

CRC Register bit 16

CRC DATA H

EA1

M7106

Serial

DATAIN(0)H

FR1

M7106

Serial data from the disk during a read

RDCLK(I) H

EB1

M7105

Read clock from the disk during a read

RDSHFTDB L

FS2

M7106

Shift Data Buffer during read operations

SECTOR ADDR 01 H

EP2

M7105

Sector address bit

SHFT SURF SEC H

FU1

M7105

Shift Surface Sector Register

ENAB DATA L

EV1

M7105

Enable data to the buffers

SHFT CRC

FN1

M7106

Shift CRC out to the disk drive

FILE RDYH

EE1

RK05

Selected disk drive is READY

11-27

CRC data

high

Table 11-9 (Cont)

M7105 to M7104 Top Connector Signal List
Signal

Pin No.

Origin

Description

STROBE (DH

EF2

M7106

Asserted when file is ready and GO bit is set (1)

FUNCTION 00 H

EU2

M7106

Function bit 00

)

Select disk drive

)

operation, i.e., read

FUNCTION 01 H

EV2

M7106

Function bit 01

FUNCTION 02 H

ET2

M7106

Function bit 02

HALF BLOCK

ES2

M7105

Transfer 128 words instead of 256

DATA CLK OK H

FM1

M7106

Data clock OK

LOMAINSHFTL

FL1

M7106

Maintenance shift

DSKDRIVE2 L

EP1

M7105

Select disk drive 2 when low (true)

DSKDRIVE3 L

EN1

M7105

Select disk drive 3 (low=true)

DSKCYLAD128L

EE2

M7106

Disk cylinder address bit 7 (MSB)

DSK CYL AD 64 L

EB2

M7106

Disk cylinder address bit 6

DSKCYLAD32 L

EJ2

M7106

Disk cylinder address bit 5

DSK CYL AD 16 L

EC2

M7106

Disk cylinder address bit 4

DSK CYL ADSL

ET1

M7106

Disk cylinder address bit 3

DSK CYL AD 4 L

EH2

M7106

Disk cylinder address bit 2

DSK CYL AD 2 L

EK2

M7106

Disk cylinder address bit 1

DSK CYL AD 1 L

ESI

M7106

Disk cylinder address bit

DSK CAPACITY EX L

FC1

RK05

)

(LSB)

Disk capacity exceeded, address sent to the disk
greater than 3128

HI MAIN SHIFT L

FT2

M7106

Maintenance shift pulse

B LASTBRKH

FL2

M7106

Buffered last break

LDDSKADDRSH

EM2

M7106

Load Disk Address Register when asserted by 6RK3

RKDATA 11 H

FH1

M7105

Disk data bit 1

B TP3 OK H

FM2

M7104

Asserted during TP3 tinne of the IDLE state only for

timing and execution of instructions

11-28

Table 11-9 (Cont)

M7105 to M7104 Top Connector Signal List
Signal

Pin No.

Description

Origin

SHFTWRTBUFF L

FJ2

M7104

Shift write buffer (DB4)

STATE ENABLE B H

FV1

M7106

Buffered STATE ENABLE

DSK RDYS/R/WL

EL2

RK05

Selected disk drive ready to seek, read, or write

DSK SEEK FAIL L

EA2

RK05

The seek operation on the selected disk drive failed

DSK DRIVE OL

ED2

M7105

Select disk drive

DSK DRIVE 1 L

ER1

M7105

Select disk drive 1 when low (true)

11-29

when low (true)

Table 11-10

M7106 Top Connector Signal List
Signal

12TH BIT OK H

Pin No.

FA1

Origin

Description

M7106

Output of divide by 12 counter each time 12 bits are
read or written

6RK3 0KH

FA2

M7104

6RK3 (DLAG) load disk address and go

B DATA 7 H

ER2

M7104

Buffered data bus bit 7 {liigh=true)

B DATA 10

EK1

M7104

Buffered data bus bit 10 (high=true)

B DATA 1 1 H

EJ1

M7104

Buffered data bus bit 1 1 (higli=true)

CLR DRIVE CMDL

FB2

M7104

Clear

commands to the selected disk drive clear all

logic (see the

DCLR instruction and Table 11-11)

CLR ALLL

EH1

M7104

Clear all logic on the RK8-E

DATA STATE (0) H

FP1

M7106

Data state (read or write data)

BTP3H

FJ1

M7104

Buffered time pulse 3

DRV REVOH

FC2

M7106

Disk

INDEX MARK is applied to the RK8-E during

the IDLE state

DSKFILE RDYL

FBI

RK05

Selected disk drive is operational

DSK WRT STATUS L

FD2

RK05

Selected disk drive is in a write status (low=true)

SET IDLE PL L

FK1

M7104

Set the IDLE state flip-flop

END STATE (0) H

FD1

M7106

The RK8-E is in the END state

ERROR CLR L

FE2

M7104

Clear the ERROR flip-flops

IDLE (0) H

FR2

M7106

RK8-E is not in the IDLE state when this signal is
high

IDLE(1)H

EC1

M7106

RK8-E is in the IDLE state when this signal is high

LAST WORD PL H

FE1

M7106

Output of the word counter each time 256 words are
read and written

MAIN (0) H

FP2

M7105

Clear side of MAIN flip-flop. The RK8-E is not in the

maintenance mode when this signal is high

RDY S/R/W H

EDI

RK05

Selected disk drive ready to seek, read, or write

DATE ENABLE (1) H

EU1

M7105

Enables MA and EM A bits to be applied to the
OMNIBUS during a data break

11-30

Table 11-10 (Cont)

M7106 Top Connector Signal List
Pin No.

Origin

SECTOR SEEK (0) H

FF2

M7106

Sector seek state

LASTBRK(I)

FN2

M7105

Last break

WRITE (1) H

FF1

M7106

The Write function is selected

WRTCMDL

FV2

M7106

Write command

HI MAINSHFTL

FT2

M7105

Maintenance shift (DIVIAN pulse)

B LAST BRK H

FL2

M7106

Buffered last break

LDDISKADDRSH

EM2

M7106

Load disk address

RK DATA 11 H

FH1

M7104

Data bit 1 1 from the disk

BTP3 0K

FM2

M7104

Buffered time pulse 3 OK

SHIFT WRT BUFF L

FJ2

M7104

Shift Write Buffer (DB4)

STATE ENAB B H

FV1

M7106

State enable

DSKRDYS/R/WL

EL2

RK05

Selected disk drive ready to seek, read, or write

DISK SEEK FAIL L

EA2

RK05

The selected disk did not complete a seek operation

Signal

Description

(Table 11-12)

DSK DRIVE OL

ED2

M7105

Select disk drive

DSK DRIVE

ER1

M7105

Select disk drive 1 when low (true)

DSK DRIVE 2 L

EP1

M7105

Select disk drive 2 when low (true)

DSK DRIVE 3 L

EN1

M7105

Select disk drive 3 when low (true)

DSKCYLAD 128 L

EE2

M7106

Disk cylinder address bit 7

DSKCYLAD64 L

EB2

M7106

Disk cylinder address bit 6

DSK CYL AD 32 L

EJ2

M7106

Disk cylinder address bit 5

DSKCYLAD 16 L

EC2

M7106

Disk cylinder address bit 4

DSK CYL ADSL

ET1

M7106

Disk cylinder address bit 3

DSK CYL AD 4 L

EH2

M7106

Disk cylinder address bit 2

11-31

when low (true)

Table 11-10 (Cont)

M7106 Top Connector Signal List
Signal

Pin No.

Origin

DSKCYLAD2 L

EK2

M7106

Disk cylinder address bit 1

DSK CYL AD 1 L

ESI

M7106

Disk cylinder address bit

DSK CAPACITY EX L

FC1

RK05

Description

Disk capacity exceeded, cylinder address greater than

3128

DATACLKOKH

FM1

M7106

Data clock OK during DATA state only

LO MAIN SHIFT L

FL1

M7105

Main shift (DMAN pulse)

BTP2H

FH2

OMNIBUS

Buffered time pulse 2

B DATA 8 H

EMI

M7104

Buffered data bus bit 8

B DATA 9 H

ELI

M7104

Buffered data bus bit 9

BRK ENABLE CLKH

FK2

M7106

Break enable clock

BRKINCLKH

FU2

M7106

BREAK IN clock.

CLR CNTRS L

FS1

M7106

Clear counters asserted by CLR ALL, DATA CLR, or

HEADER E during STATE ENABLE
CLR SECTOR AD L

EF1

M7105

Clear Sector Address Register

CRC 16(1) H

EN2

M7105

CRC Register bit 16

CRC DATA H

EA1

M7106

Serial

DATA IN (0) H

FR1

M7106

DATA IN from the disk

RDCLK(I) H

EB1

M7105

Read clock from the disk

RDSHFTDB L

FS2

M7106

Shift Read Data Buffer (DL1)

SECTOR ADDR 01 H

EP2

M7105

Sector address bit

SHFT SURF SEC

FU1

M7105

Shift Surface Sector Register

ENAB DATA L

EV1

M7105

Enable data to the buffers

SHFT CRC

FN1

M7106

Shift CRC Register

FILE RDYH

EE1

RK05

Selected disk drive is READY

11-32

CRC DATA

Table 11-10 (Cont)

M7106 Top Connector Signal List
Signal

Pin No.

Origin

Description

STROBE (1) H

EF2

M7106

Asserted when file is ready and GO bit is set (1

FUNCTION 00 H

EU2

M7106

Function bit 00

FUNCTION 01 H

EV2

M7106

Function bit 01

)

Select disk drive

)

operation, i.e., read

V
1

FUNCTION 02 H

ET2

M7106

Function bit 02

HALF BLOCK H

FS2

M7106

Transfer 128 words instead of 256

11-33

)

SECTION 3 OPERATION AND PROGRAMMING
11.10

SINGLE CYCLE DATA BREAK DESCRIPTION

All data transfers between the

RK8-E and memory are via the single cycle data break interface. The concepts of data

transfers and interrelationships of the data break interface and peripherals are explained in Chapter 10 of the Sma/t

Computer Handbook 1973. A detailed description of the data break interface (KD8-E) is explained in Chapter 10,
Volume II of the PDP-8/E Maintenance Manual. The data break interface option operation is identical to the single
cycle data break control logic used in the RK8-E,

11.11

INSTRUCTIONS AND STATUS BITS

The following are used to program the RK8-E.
Skip on Disk DONE or ERROR flag (DSKP)
Octal Code:

6741

Operation:

Skip the next instruction if the TRANSFER DONE or ERROR flag is set.

Clear All (DCLR)

6742

Octal Code:

Transfer bits 10 and 11 from the AC to the clear logic in the

Operation:

RK8-E (see Table 11-11) and clear

the AC.

Table 11-11
Clear Operations Using the DCLR instruction

Bit 10

Bit 11

Operation

DCLS; clear tha AC and Status Register. This bit combination is normally used to clear
program interrupts.

DCLC; clears the AC and all RK8-E control logic but does not clear the selected RK05
control logic. This bit combination

used only to simulate a power clear or if the

controller does not respond to normal

control even

if it is

commands. Note this instruction stops the

rewriting a HEADER word; it should be used with care. The Status

all

zeroes after the

DCLR instruction is executed with this bit

combination in the AC.

DCLD; clears the AC and recalibrates the selected drive by forcing it to cylinder 000
(home position). This bit combination is used to recover from cylinder address errors
and select errors.

Accomplishes same operation as

11-34

CAUTION
The following programming sequence should be used to
recalibrate the selected disk drive with a

DCLR instruction.

DCLR with AC 0000

Clears Status Register and AC

STL

Set AC LINK bit to 1

RTL

Rotate AC and LINK left two. One in the LINK goes to AC bit 10 position

DCLR with AC 0010

The selected drive is recalibrated as explained in Table 11-11

DSKP

The program skips an instruction when the TRANSFER
when the read/write heads are at the cylinder 000

JMP-1

DCLR with AC 0000

Clears Status Register and the AC

DSKP

Skip on TRANSFER DONE

JMP-1

DONE flag is set

Recalibrate procedure is finished. Read/write heads are at cylinder 000 (home

position) and the AC is cleared

Load Address and GO (DLAG)
Octal Code:

6743

Operation:

Transfer the contents of the

AC to the Disk Address Register, clear the AC, and enable the

command in the Command Register to be executed. The Disk Address Register specifies one of 16
sectors, one of 2 surfaces, and one of 203 cylinders. The

AC must be loaded with the disk address

before this instruction is executed. In a normal read or write operation, the following occurs:

The selected drive seeks the track specified by AC bits

through 6 and bit 11 in the Command Register.

When the selected drive signals it has completed a SEEK, the HEADER word is checked on the first
sector to pass under the read/write heads.

the track specified checks with the HEADER word (read/write heads are on the right cylinder), the

control waits for the next sector pulse.

The control reads the sector address of each sector passing under the read/write heads and when the
correct sector is found a read or write operation is performed.

11-35

Load Current Address (DLCA)

6744

Octal Code:

Transfer the contents of the AC to the Current Address Register and clear the AC. The contents of

Operation:

the Current Address Register along with the EMA bits in the Command Register are applied to the

OMNIBUS MA and EMA lines to select a location in memory for a data transfer. Note that the AC
must be loaded with the address of the first memory location used in a data transfer.
Read Status Register (DRST)
Octal Code:

6745

Operation:

Clear the AC and transfer the contents of the Status Register to the AC (Table 11-12).

Table 11-12

Contents of Status Register
Bit

Indication

TRANSFER DONE is set (1).
a.

At the end of a data transfer

When an ERROR occurs while the controller is executing an operation

When the selected drive completes a seek only operation

When the selected drive completes a recalibrate operation if bit 4 in the Command Register is
set

NOTE
The TRANSFER DONE flag causes a program to interrupt if
bit 3 in the Command Register is set.

RDYS/R/W indicates the selected disk drive heads are in motion and the selected drive is RDY to SK,
RD, orWR.
Not used.

SEEK FAIL is set (1) to indicate the selected drive failed to seek a cylinder address specified by the
program. This bit
set by DSK SEEK FAIL L from the selected drive. The recalibrate operation
is

must be performed to clear bit 3. If the DLAG instruction is executed by the program and bit 3 is set
(1) the

ERROR flag sets.

FILE NOT READY indicates the selected drive is not ready or inoperative. This bit is set (1) if DSK
FILE DRY L from the selected drive is high. If the DLAG instruction is executed by the program, the

ERROR flag sets

bit 4

set (1). To clear bit 4, some action

power up the selected disk drive.

11-36

must be taken by the operator, i.e.,

Table 11-12 (Cont)

Contents of Status Register
Indication

Bit

CONTROL BUSY ERROR

instructions while the control

(1) if the program executes the DLAG, DLCA, or DLDC
BUSY (IDLE is cleared). If a CONTROL BUSY ERROR occurs, the
current operation is completed and the TRANSFER DONE flag sets at the end of the operation. This

error occurs

set

most often when programs

are debugged,

and requires rewriting of the program to

eliminate the error.

CAUTION
AC bit 11 should not be used to clear a
CONTROL BUSY ERROR. If the DCLR instruction is issued
IDT DCLR with

by the program, the operation is aborted even if the program is
writing a HEADER word.

TIME OUT ERROR is set (1) if the control has been busy for more than 280 ms. If TIME OUT
ERROR sets, the TRANSFER DONE flag sets. TIME OUT ERROR indicates a hardware problem
and can be cleared by the DCLR instruction.

WRITE LOCK ERROR indicates the program tried to write on a write-protected disk drive. To write
on a disk drive that has been write protected, the operator must manually clear the write lock protect

by pressing the WT PROT switch on the drive which produced the error.

CRC ERROR is set (1) if the CRC character read from the disk does not agree with the CRC
RK8-E as data is read from the disk. CRC ERROR sets the TRANSFER
DONE flag immediately and the operation is stopped. If a CRC ERROR occurs, a new read operation

character calculated by the

must be initiated to reread the data; if this is not successful, the data must be rewritten.

DATA REQUEST LATE
jUs.

set (1)

the processor does not respond to a break request within 22.5

The 4-word Data Buffer Register is filled within 22.5 jUs, and if one of the registers is not freed

within this time period, a DATA REQUEST LATE ERROR occurs. DATA REQUEST LATE sets the

TRANSFER DONE FLAG and stops the operation. A new operation must be initiated to transfer the
same data. Note that if the Data Buffer Register is full during a read operation, the processor must
grant a

BRK RQST within 6.5 jus after the register is filled; or if the Data Buffer Register is empty

during a write operation, the processor must grant a BRK

emptied. Either one of these conditions causes a
half-filled or half-empty, the latency would be

RQST within 6.5 /is after the register is

DATA REQUEST LATE error. If the register

13 jus.

DRIVE STATUS ERROR is set (1) when the DLAG instruction is executed by the program if:
a.

The DRIVE NOT READY for one of the following reasons:
1.

Power is not turned on

The drive does not exist (incorrect address)

The selected drive does not have a cartridge installed

The door on the selected drive is not closed (interlock open)

11-37

Table 11-12 (Cont)

Contents of Status Register
Bit

Indication

Disk is not up to speed (disk rotation less than 1500 rpm)

Load switch on the selected disk drive is in the RUN position. The TRANSFER DONE
flag is not set as a result of

The WRITE

DRIVE NOT READY

CHECK ERROR is set to indicate the drive has one of the following error

conditions.

Erase or write current without a WRITE GATE

The head position transducer lamp
inoperative. If WRITE CHECK ERROR
set, the
WT PROT switch on the selected drive must be depressed to remove the error. WRITE
CHECK ERROR does not set the TRANSFER DONE flag.

disk capacity

drive),

the

exceeded (cylinder address greater than 3128 was sent to the selected

program

must

TRANSFER DONE flag
4.

select

new

disk

address that

less

than 3128. The

set if the disk capacity is exceeded.

SEEK FAILURE occurs in the drive, this indicates a seek was not completed because
If the control is busy at the time a SEEK FAILURE

of some disk drive malfunction.
occurs, the

TRANSFER DONE flag

set and the disk drive

must be recalibrated using

the recalibrate lOT DCLR with AC = 10.

CYLINDER ADDRESS ERROR is set (1) if the HEADER word of a sector does not agree with the
cylinder address sent to the drive (either the HEADER word was read wrong or the read/write heads

were positioned to the wrong address).

The TRANSFER

DONE flag

HEADER word retained in the CRC Register. The
DCLR instruction (AC = 0010), and the disk drive
should be addressed again using the DLAG instruction. The cylinder address in the CRC Register
transferred to the AC by the maintenance instruction for the program to compare the disk address
is

set

and the

selected drive should be recalibrated using the

with the cylinder address requested by the program (refer to the 6747 maintenance lOT).

Load Command Register (DLDC)
Octal Code:

6746

Operation:

Transfer the contents of the AC to the Command Register and clear the AC and Status Register.

Note the AC must be loaded with information to be transferred to the Command Register (Table
11-13 and Figure 11-4) before this instruction is executed. Each of the functions selected by the

Command Register are discussed in detail in Paragraph 11.11.1.

11-38

Table 11-13

Command Functions
Function

Bit

0,1,2

Bits

and 2 of the Command Register are decoded and used to select disl< operations as

follows:

BitO

Bit 2

Biti

Read Data — Seek disk address, check the

HEADER, and

read one sector.

Read All —Seek disk address, do not check the HEADER,

and read one sector.
Write protect the selected drive.

4 is

Seek disk address, and

DONE flag when seek

completed.

bit

1, set

the

TRANSFER

Write Data — Seek disk address, check HEADER, and write

one sector.
Write

all,

seek disk address, do not check the

HEADER,

and write one sector.

Not used
Not used
3

If bit

3 is a 1, enable interrupt on ERROR flag or TRANSFER DONE.

If bit

4 is 1, set TRANSFER DONE flag when seek is complete.

bit

5 is a 1, the controller writes or reads 128 words in a sector instead of 256. The TRANSFER

DONE flag
6,7,8

set at the end of a sector and the last 128 words of the sector contains all zeroes.

Bits 6, 7, and 8 are used to address extended memory as follows:

Bite

Bit?

Bits

EMA2)

(EMA1)

(EMAO)
Field
1

Field 1

Field 3

Field 5

Field 7

Field 2

1
1

Field 4

1
1

Field 6

11-39

Table 11-13 (Cont)

Command Functions
Bit

Function

These

bits are

not incremented and the program must reload the Command Register to select a

new memory field when the Current Address Register overflows (reads all zeroes).
Bits 9 and 10 are used to select a disk drive as follows:

9,10

Bit 9

Bit 10

Drive
1

Drive 2

Drive 1

Bit 11

Drive 3

the extended cylinder address bit (Figure 11-15). It is added to the 7-bit Cylinder Address

causes an ADDRESS ERROR.

Maintenance lOT (DMAN)
Octal Code:

6747

Operation:

Transfers the contents of the

AC to the RK8-E maintenance control logic. The maintenance

operation performed is determined by contents of the AC (Table 11-14); therefore, the AC must

be loaded before this instruction is executed. Table 11-14 gives the purpose of each bit, and the
operations are discussed in detail in Paragraph 11.11.2.

11.11.1

Command Functions

When the Command Register is loaded by a DLDC instruction, the operation to be performed by the RK8-E is
determined by

bits 0, 1, and 2 from the AC. The following paragraphs explain each of these functions.
A flow
diagram illustrating all RK8-E operations is shown in Paragraph 11.15, Figure 11-15.

-A

11.11.1.1 Read Data
normal read operation (Table 11-13) is initiated when all zeroes (000) are transferred
from AC0-AC2 to the Command Register by a DLDC instruction. The RK8-E and RK05 must interact to SEEK
(find the correct cylinder), check the HEADER (find the correct surface), and read serial
data from the disk drive.
The serial data from the disk drive is read into Data Buffer 1 and transferred to the last empty buffer as a 12-bit
parallel

word. The parallel words are eventually moved into Data Buffer 4 and transferred to memory via the single

cycle data break.

The RK8-E tries to keep the Data Buffer Register empty, by initiating single cycle data breaks, so that a register will
be empty when each new word is received from the disk drive. If data is read from the disk drive
while the Data
Buffer Register is full, the DATA REQUEST LATE flag is set and the sector must be read again.

A read operation continues until 256 words have been read from the disk drive and the TRANSFER DONE flag sets.
If

the half block bit is set, 256 words are read, but only the first 128 words are data words. The second

are all zeroes and are not transferred to memory.

11-40

128 words

Table 11-14

Maintenance Functions
Function

Bit

Enables maintenance logic and disables lOT DLAG (GO).

Enable a shift to lower buffer (DB4) by setting the DB4 control flip-flop.

Check CRC Register

Check Command Register

Check Surface and Sector Register

Check Data Buffer

Check Data Break Request

Transfer contents of Data Buffer 4 to the AC

Not used

Maintenance data bit

Not used

Read All - Read All is initiated when 001 is transferred from AC0-AC2 to the Command Register by
DLDC instruction. Read All identical to a normal read operation except the HEADERS are not checked. This
allows a disk cartridge that has been formatted to be checked by the program to verify the HEADERs have been
11.11.1.2

the

written on the cartridge correctly.

11.11.1.3

Write Data - Write Data (Table 11-13)

initiated

when a 100 is transferred from AC0-AC2 to the

Command Register by a DLDC instruction. The RK8-E and RK05 must interact to SEEK (find the correct cylinder),
check the HEADER (find the correct sector), and write data transferred from memory to Data Buffer 1 as a 12-bit
parallel word via the single cycle data break. The 12-bit word is transferred from Data Buffer 1 to the last empty

The 12-bit word is eventually transferred into Data Buffer 4 where it is shifted out to the disk drive as a
12-bit serial word to be written on the disk cartridge.

buffer.

The RK8-E tries to keep the Data Buffer Register full during a write operation so that there will always be a word
available when the drive is ready to write. If the disk drive calls for data when the Data Buffer Register is empty, the
DATA REQUEST LATE flag is set and the sector must be rewritten.
The write operation continues until 256 words have been written on the cartridge and the TRANSFER DONE flag
sets. If the half block bit is set, 128 words of data from memory are written on the disk cartridge and 128 words of
all

zeroes are written on the remainder of the sector.

AC0-AC2 to the
Command Register by the DLDC instruction. This function is identical to the write function except the HEADERS

11.11.1.4

Write All -Write All (Table 11-13)

initiated

when

101

transferred

from

new disk cartridge. To format a disk cartridge, a
HEADER word must be written at the beginning of each sector. The word to be written is determined by the

are not

checked by the RK8-E. Write All

used to format a

program (Paragraph 11.12.1).
11-41

Write Protect - A 010 transferred from AC0-AC2 to the

11.11.1.5

Command Register by a DLDC instruction

turns on the WRITE PROTECT for the selected disk drive. If the program attempts to write on a disk drive that has

WRITE PROTECT set, a WRITE LOCK ERROR occurs and stops the write operation. The only way to enable
writing on a disk drive that has been write protected is to push OFF the WRT PROT OFF switch on the drive that
was write protected.
Seek Only - When

11.11.1.6

Oil

transferred

from

AC0-AC2 to the Command

DLDC

instruction, the selected disk drive seeks the cylinder contained in the Cylinder Address Register but does not check

the

HEADER or start a read or write operation. Cylinder (2 tracks) seek electronics are self-contained in each disk

drive so once the seek operation has been started a new disk drive can be selected. Thus, more than one disk drive

can be doing a seek operation and the control can select another disk drive for a read or write operation. If seek only
specified and the DLAG instruction
executed by the program (this instruction starts all disk operations), the
TRANSFER DONE flag is set after lOT DLAG
executed. TRANSFER DONE
set again when the seek is
is

complete if bit 4 in the Command Register is set (1 ).
Interrupt Enable - The program interrupt system

11.11.1.7

enabled

bit

3 in the Command Register is set.

When this bit is set (1), program interrupt is initiated if the TRANSFER DONE or ERROR flags are set.
11.11.1.8 TRANSFER DONE on SEEK COMPLETE - If bit 4 in the Command
TRANSFER DONE flags set when the selected drive has completed a seek operation.

set

(1),

the

NOTE
Programming precautions must be taken when using this bit
because

possible to select another drive just as the drive

that was previously selected completes a seek. If this happens,

the

program thinks there is a SEEK
on the newly selected drive (see Paragraph
11.12.5 for information on programming around this hazard),
unsophisticated

COMPLETE

11.11.1.9 Read or Write Half Block (128 Words) - If bit 5 in the Command Register is set, a half block (128
words) of data is specified for a data transfer instead of the usual 256 words contained in one sector. When writing,
the first 128 words of a sector come from memory and the second 128 words are all zeroes. The TRANSFER DONE
flag

set after a

complete sector (256 words)

written.

When reading, the first 128 words read from the disk

TRANSFER DONE flag set at the end of the sector when 256 words
have been read. The delay before setting the TRANSFER DONE flag during a read or write half block operation is
to allow the generation and checking of a CRC character at the end of the sector.
cartridge are transferred to memory. The

11.11.1.10

memory

Extended Memory Addressing - Bits 6, 7, and 8 of the Command Register are used to address extended

11-13). The extended memory address bits (EMA0-EMA2) are not incremented; thus, the
Command Register must be reloaded to select a new memory field. If the Current Address Register overflows, the

data

(Table

wrapped around

the same field. During a write operation,

data has already been written

those

locations it will be written over; also the data read from memory during a write operation is duplicated (reread).

Unit Select— Bits 9 and 10 of the Command Register are decoded to select one of four disk drives
(Table 11-13). Signals to and from a disk drive are inhibited except when the drive is selected.
11.11.1.11

11.11.1.12 Extended Cylinder Address - Bit 11 of the Command Register is an extension of the 7-bit
Cylinder/Surface/Sector Address Register (Figure 11-4). The maximum number of usable cylinders is decimal 203,
designated as OOio to 202io or OOs to 3128. When the program specifies a cylinder address greater than 3128, the

CYLINDER ADDRESS ERROR flip-flop is set.

11-42

11.11.2

Maintenance Functions

The maintenance lOT 6747 (OMAN) ANDed with the contents of the AC allows program access to the major
Register)
registers in the RK8-E. The maintenance instruction transfers data to the major registers (i.e., Data Buffer
using
memory
from
or
transferred
to
be
also
can
Data
memory.
AC
or
the
into
or reads the contents of the registers
write
write
or
to
from
read
changing
when
must
be
used
control)
(clear
instruction
A
DCLC
the maintenance lOT.
to read.

The major registers are described in Paragraph 11.4. Note that the CRC Register is a multipurpose register that
HEADER
contains the cylinder address loaded from the AC and the cylinder address that is written or read as a
read from
character
CRC
the
contains
also
Register
word. This register also calculates the CRC character. The CRC
the disk drive to be compared with the CRC that has been calculated. When the CRC Register is
Address Register, bits 1-3 and 12-16 are zeroes and bits 4-1 1 contains the cylinder address.

used as the Cylinder

The contents of the CRC, Command, and Surface/Sector Register must be shifted into Data Buffer 4 before they
can be transferred to the AC or memory. These operations are explained in the following paragraphs.

DMAN instruction is executed and ACOO is a 1, the controller is in the
are enabled, and the DLAG (GO) lOT is disabled. The maintenance
functions
maintenance
maintenance mode, the
(DCLC).
lOT
control
clear
the
control bit is cleared by
11.11.2.1

Maintenance Mode- If the

NOTE
Maintenance functions cannot be microprogrammed.

11.11.2.2

Shift Enable

- If AC bit 01

set when

lOT DMAN is executed by the program, the lower Data Buffer

(DB4) control flip-flop sets to enable a shift to the lower buffer.

Check ORG Register - When AC bit 02 is a 1 and the DMAN lOT is executed by the program, AC bit 10,
is shifted one position with
the CRC Register, and Data Buffer 4 are logically connected as a 29-bit shift register that
each DMAN lOT. AC bit 10 shifts into the CRC and the CRC shifts into Data Buffer 4.
11.11.2.3

The program must count the bits shifted to determine when to read Data Buffer 4. AC bit 02 does not set a

control

bit so a clear is not necessary.

Check Command Register - When AC bit 03 is set and the DMAN lOT is executed by the program, the
Command Register and Data Buffer 4 are logically connected as a 24-bit shift register that is shifted one position
Data Buffer 4. AC bit 03
with each DMAN lOT. The program must count the bits shifted to determine when to read
11.11.2.4

does not set a control bit so a clear is not necessary.

Check Surface/Sector Register - When AC bit 04 is 1 and the DMAN lOT is executed by the program,
shift register that is shifted
the surface bit, the Sector Register, and Data Buffer 4 are logically connected as a 17-bit
11.11.2.5

one position with each DMAN lOT. The surface bit shifts into the Sector Register and the Sector

Data Buffer 4.

The program must count the bits shifted to determine when to read the lower Data Buffer. AC bit 04

does not set a

control bit so a clear is not necessary.

Check Data Buffer - When AC bit 05 is a 1 and the DMAN 10T is executed by the program, AC bit 10
each DMAN lOT.
and Data Buffer 1 are connected logically as a 13-bit shift register that is shifted one position with
the overflow of
by
incremented
is
In addition, the bit counter and word counter are incremented. The word counter
11.,11. 2.6

the 1 2-bit counter.

11-43

After 12 shifts, the 12-bit counter overflows setting a control bit indicating that the upper Data Buffer 1 is full.
The
contents of Data Buffer 1 transfers to Data Buffer 4 which is read into memory. After 4 words if Data Buffer 4 is
1. the DATA REQUEST LATE ERROR flag
set. If Data
AC or memory, information transfers into the buffer filling Data Buffer 4 and
emptying Data Buffer 1. When the word counter overflows after 256 transfers, the TRANSFER DONE flag sets.

not read, and another bit
Buffer 4

shifted into Data Buffer

read either into the

AC bit 05 does not directly set a control bit but its results do. A DCLC lOT should be issued before and after a
sequence using AC bit 05.
11.11.2.7

Check Data Break Request - When AC bit 06 is a 1, and lOT DMAN is executed by the program, a single
is initiated. The direction of transfer is controlled by the function bits in
the Control
read is specified, the contents of Data Buffer 4 is transferred into the memory location specified by the

cycle data break request
Register.

If a

Current Address Register and the Extended Memory Address Register. A write transfers data into Data Buffer 1. The
data transfers into the buffer and the Data Buffer fills after four data break requests unless it is emptied by a read
into the AC.

cannot be emptied by a read into memory if the DCLC is executed before switching from read to

lOT DCLC clears the Data Buffer control bits so the buffer appears to be empty. AC bit 06
does set a control bit, but it is automatically cleared after the data break is completed.
write or write to read.

11.11.2.8 Check Lower Data Buffer - When AC bit 07 is a 1 and lOT
is executed by the program, the
contents of Data Buffer 4 are read into the AC. AC bit 07 does not set a control bit so a clear is not necessary.

DMAN

11.11.2.9

Maintenance Data - AC bit 10 is used in conjunction with other AC bits as data when the DMAN lOT is

executed by the program.
11.12

PROGRAMMING SEQUENCES

11.12.1

Format A New Disk Cartridge

The RK8-E control contains the logic required to format a disk cartridge. All the program must do is address every
sector on the disk and write on every sector using the Write All mode. The track address (cylinder and surface when

DLAG was issued)

automatically written on the particular sector HEADER word selected by the control. The data

not important except that the data should contain addressing information so a check can be made to
determine if the RK8-E and drive found the correct sector on the correct surface and cylinder.
written

To write a new disk, the Command Register function bits (bits 0, 1, 2) should contain octal 5 (Write All). To read a
newly formatted disk, the function bits should contain octal 1 (Read All). These function bits prevent the RK8-E
from reading HEADER words and reporting HEADER errors that exist on an unformatted disk.

Sequence of instructions to format a disk:
1.

Set up Current Address Register.

Set up Command Register 5000 for Write All, 1000 for Read All.

Set up first disk address and GO.

Wait for TRANSFER DONE flag, check for errors.

Set up current address again,

Set up second disk address and GO, etc.

11-44

11.12.2

Normal Read/Write

The programming sequence for a Write Data or Read Data mode is very similar to the sequence to format a disk. The
sequence is:

Set up current address.

Set up Command Register 0000 for Read Data, 4000 for Write Data.

Set up required disk address and GO.

Wait for TRANSFER DONE flag and check for errors.

1 1 .1 2.3

Bootstrap Loader

Many computers of the PDP-8 family include a clear with key start. On those machines, the clear of step 1 is not
required.

Clear Control.

Load the Command Register with AC = 0000. This also clears the Status Register.

Load disk address and GO.

JMP.

Most bootstrap loaders for the RK8-E are in sector 0, surface 0, and cylinder 0; thus, with the control cleared, a two
instruction bootstrap loader is all that is required.

11.12.4

Seek Only

The sequence for Seek Only (Command Register function bits equal 01 1) is different from Write All, Read All, Write
Data or Read Data. It is necessary to put two skip or interrupt sequences in the program.

The programming sequence is:
1

Set up Command Register, 3000 for Seek Only and desired unit number.

Load disk address and GO.

Wait for TRANSFER DONE flag. TRANSFER

ACKNOWLEDGE
4.

DONE

set during a Seek Only when DISK

ADDRESS

received from the drive.

Clear Status Register DONE flag.

Drive is not seeking but if the TRANSFER

DONE flag

to be set when the seek is complete, bit 4 of

the Command Register must be a 1, issue a load Command DLDC instruction with selected drive number
in

AC 0-1 1 and AC bit 4=1
1

Wait for TRANSFER DONE.

The alternative to steps 5 and 6 above is to check the condition of Status Register bit 1, which is
complete.

11-45

when the seek is

11.12.5

Overlapped Seeks

Overlapped seeks make use of the seek only feature. The program starts multiple drives seeking and then periodically
selects a different drive to determine

11.12.4 step 3, but

in general,

has completed seeking. A different drive may be selected after Paragraph

programs operating with other program interrupt devices could be confused as to

which drive actually completed a seek. For example, if bit 4 of the Command Register is a 1 (allowing seek complete
to set the TRANSFER DONE flag) and multiple drives are seeking, it is possible to select a different drive just as one

previously selected completes its seek. The TRANSFER DONE flag sets but the unsophisticated program incorrectly

thinks the newly selected drive has completed a seek.

A program has two methods of getting around this problem.
Before selecting a

new drive, the program changes the Command Register to make bit 4 a without
It then changes the drive number with bit 4 equal to 1. If the new drive has

changing the drive number.

completed a seek, there is no confusion as to which drive set the TRANSFER DONE flag.
Leave bit 4 of the Command Register set and check bit 1 of the Status Register to determine if the drive

selected or the drive previously selected set the TRANSFER
if the

1 1 .1 2.6

DONE flag. Bit

of the Status Register is

selected drive has completed the seek.

Recalibrate Selected Drive

The programming sequence for recalibrating a selected drive to cylinder 000 is similar to the sequence for Seek Only.
The sequence follows:

AC equal to 0002.

Issue lOT 6742 with the

Wait for TRANSFER DONE flag.

Clear status.

Drive is now seeking cylinder 000. If the TRANSFER DONE flag is to be set when the seek is complete,

bit

4 of the Command Register must be set,

i.e.,

issue

DLDC instruction with AC 10-11 set to the

selected drive and AC bit 4=1

Wait for TRANSFER DONE.

The alternative to steps 4 and 5 is to check bit 1

of the Status Register. Bit

when the recalibrate seek is

complete.

Data Transfers on Consecutive Sectors

1 1 .1 2.7

Octal

or octal 4 (Read All or Write All)

the function portion of the Command Register allows a program to

new disk cartridge by disabling the checking of headers. This feature is also used to transfer data on
consecutive sectors. Assume a program is required to transfer 512 words of data on two consecutive sectors. The

format

program should use Read Data and Write Data (octal
the transfer of the

first

and 4 in the function portion of the Command Register) for

256 words of data. When the first 256 words have been transferred and the TRANSFER

DONE flag is set, there is a minimum of 100 /is for the program to set up the control for transfer to the next
consecutive sector. The function portion of the Command Register should be changed to octal 1 or octal 5 (Read All
or Write All), the Status Register cleared, and the next sector specified along with surface and cylinder when issuing

DLAG. The control does check the header of the next sector but transfers 256 words of data. It is not necessary to
change the Current Address Register, if a 512-word buffer is available in memory.
11.13

PROGRAMMING EXAMPLES

The following paragraphs provide examples to be used in programming the RK8-E Controller and the RK05 Disk
Drive.

11-46

11.13.1

Write All

The programming sequence that follows could be used to write information on a disk sector

in the Write All

mode.

Example

BGN, CLACLLIAC

AC10=0 AC1 1=1

/ enable clear control

DCLR

/ lOT 6742 clear control

TADCURENT

/ desired current address

ACO-1

DLCA
TAD DRIVE
TAD WRTALL
TAD FIELD
TAD EXBIT
DLDC
TAD TRACK
DLAG

/ lOT 6743 load disk address and

DSKP

/ lOT 6741

/ lOT 6744 load current address

AC9— 1
AC

/ get drive number in

/ get Write All function in
/ get field in

AC6-8

/ get extended cylinder address bit in AC1

Command Register
ACO-1

/ lOT 6746 load

/ get desired track in

skip on DONE or

GO
ERROR flag

JMP.-1

/ wait for flag

DRST

/ lOT 6745 read Status Register

CIA

/ change

AC for testing

TAD K4000
SZA CLA
ERROR, HLT
JMP DONE

/ to other seek, read, or write routines.

FIELD, 0000

/ desired field in

TRACK, 0000

/ desired cylinder, surface, and sector

K4000, 4000

CURE NT, 0000
WRTALL, 5000
11.13.2

/ compare to expected value

/skip if status OK

/ERROR, disk status

AC6-8

/ expected status
/ any desired current address
/ write all function

ACO-2

Recalibrate

The programming sequence that follows could be used to "recalibrate" (return the read/write heads
disk drive.

Example

BGN, CLA CLL lAC

/ enable clear control

AC10=0 AC1 1 = 1

DCLR
TAD DRIVE
DLDC

/ lOT 6746 load

CLACLLCMLRTL

/ enable recalibrate AC10=1

DCLR

/ lOT 6742 recalibrate

DSKP
JMP.-H

/ wait for flag

TAD K0200
TAD DRIVE
DLDC

/ lOT 6742 clear control

ACQ— 10
Command Register

/ get drive number in

/ 6741

AC1 1=0

lOT skip on DONE or ERROR flag

/ get enable set

DONE bit in AC4
AC9— 10

/ get drive number in
/ lOT 6746 load

DSKP

/ lOT 6741

JMP.-1

/ wait for flag

DRST

CIA

/ change

Command Register

skip on

DONE or ERROR flag

lOT 6745 read Status Register

AC for testing

11-47

to cylinder 0) a

TAD K4000
SZA CLA
ERROR, HLT

JMPDONE
DRIVE, 0000
K0200, 0200
K4000. 4000
11.13.3

compare to expected value

/skip if status OK

ERROR, disk status

/ read

routines, to other seek, write

drive in AC9— 10

/ desired

/ enable set

DONE AC4
DONE flag.

/ expected status only

Seek Only

The programming sequence that follows could be used for a Seek Only operation.
Example

BGN,CLACLL lAC
DCLR
TAD DRIVE
TAD SEEK
TAD EXBIT
DLDC
TAD TRACK
DLAG
DSKP

/ enable

clear control AC10=0AC11 = 1

/ lOT 6742 clear control
/ get drive number in ACQ— 10

/ get seek function in
/ get extended

ACO—

cylinder address bit in AC1

lOT 6746 load Command Register

/ get desired track in

ACO— 1

lOT 6743 load disk address and GO.
/ lOT 6741 skip on DONE or ERROR flag
/

JMP.-1
TAD K0200

/ wait for flag

TAD DRIVE
DLDC

/ get drive

/ get enable

set

DONE on seek complete in AC4

DSKP

number in AC09 and AC10
/ lOT 6746 load Command Register
/ lOT 6741 skip on DONE or ERROR flag

JMP.-1

/ wait for flag

DRST

CIA

/ change

TAD K4000
SZA CLA

/ compare to expected

ERROR, HLT
JMP DONE

K0200, 0200
K4000, 4000

DRIVE, 0000
SEEK, 3000
EXBIT, 0000
TRACK, 0000

lOT 6745 read Status Register

AC for testing
value

/skip if OK
/

ERROR, disk status

/ seek complete,

now to read or write routine

/ or another seek

routine

/ enable

set

DONE bit (AC bit 4)

known good or expected status

/ desired drive in AC bits 9-10
/ seek only function in

/ extended

AC bits 0-2

cylinder bit in AC bit 1

/ any desired cylinder, surface, and sector.

11-48

11.13.4

Overlap Seek

The programming sequence that follows could be used

for an

Overlap Seek operation with multiple drives

(Note: four (4) drives are assumed).

Example

BGN,CLACLL lAC
DCLR
DCA DRIVE
TAD M4

DCACNTRL
OUT, TAD DRIVE

CLL RAL

AND K0006
DLDC
TAD DRIVE
CLL RAL
AND K0006
TAD SEEK
TAD EXBIT
DLDC
TAD TRACK
DLAG

/ enable

clear control AC10=0 AC1 1=1

lOT 6742 clear control

/ start with

/ 4 drive
/ set

drive

counter constant

up the counter
number pointer

/ get drive

/put ACl 0-11 in AC9-10
/ mask 9-10
/ lOT 6746 load Command Register
/ get

drive number pointer

/put ACl 0-11 in AC9-10

/mask 9-10
/ get seek function in
/ get extended
/

ACO—

cylinder address bit in ACl 1

lOT 6746 load Command Register
track in ACO— 1

/ get desired

DSKP

lOT 6743 load disk address and GO.
/ lOT 6741 skip on DONE or ERROR flag

JMP.-1

/ wait for flag

ISZ DRIVE

JMPCNTRL
JMPOUT
JMPWAIT

update drive number pointer

/ count drives
/ send

next drive out

/ to drive wait routine to wait for drives

number pointer

DRIVE, 0000
SEEK, 3000
EXEJIT, 0000
K0006, 0006
M4, 7774

/ drive

CNTRL,0

/ counter

/ seek only

function in ACO—

/ extended

cylinder bit in ACl 1

/mask 9-10
/

minus 4 constant

Routine to wait for drives doing an Overlap Seek.

WAIT, CLA CLL lAC

IN,

/ enable

clear control ACl 0=0 ACl 1=1

DCLR
DCA DRIVE
TAD M4

DCACNTRL

/ setup drive

TAD DRIVE
CLL RAL
AND K0006
DLDC

lOT 6742 clear control

/ start with

drive

/ 4 drive counter constant

counter

number pointer
/put ACl 0-11 in AC9-10
/mask 9-10
/ lOT 6746 load Command Register

/ get drive

11-49

RDSTA, DRST

lOT 6745 read Status Register

CLL RAL

/ transfer ACOl to ACOO

SZACLA

/ skip if drive

JMP RDSTA
ISZ DRIVE

/ drive still

not busy

busy AC bit 1

/ drive completed seek

ISZCNTRL

/ update drive counter

JMP IN
JMP DONE

/ wait for next drive
/ all

drives complete. To other read, write, or

/seek routines

DRIVE, 0000
K0006, 0006

/ drive number pointer

M4, 7774

/ drive counter constant

CNTRL,

/ counter

11.13.5

mask

Write Data

The programming sequence that follows could be used to write information on a disk sector in the Write Data mode.
Example

BGN,CLACLLIAC
DCLR

TADCURENT
DLCA
TAD DRIVE
TAD WRTDAT
TAD FIELD
TAD EXBIT
DLDC
TAD TRACK
DLAG

/ enable clear control

/ lOT 6742 clear control
/ desired

current address ACO— 1

lOT 6744 load Current Address
/ get drive number in AC9— 1
/

/ get Write

Data function in AC

/ get field in

AC6-8

/ get extended cylinder address bit in AC1
/ lOT 6746 load

Command Register
ACO— 1

/ get desired track in
/

lOT 6743 load Disk Address and GO.
lOT 6741 skip on DONE or ERROR flag

DSKP

JMP.-1

/ wait for flag

DRST

CIA

/ change

TAD K4000
SZA CLA
ERROR, HLT
JMP DONE

AC1 0=0 AC1 1 =1

lOT 6745 read Status Register

AC for testing

/ compare to expected value
/ skip if status
/

ERROR, disk status

/ to other seek, read, or write routines

FIELD, 0000

/ desired field in

TRACK, 0000

/ desired

K4000, 4000

/ expected status

CU RENT, 0000
WRTDAT, 4000

/write data function ACO—

AC6-8

cylinder, surface, and sector

/ any desired

current address

11-50

11.13.6

Read All

The programming sequence that follows could be used to read Information from a disk sector in the Read All mode.
Example

BGN,CLACLL. lAC

TADCURENT

/ desired

DLCA
TAD DRIVE
TAD REDALL
TAD FIELD
TAD EXBIT
DLDC
TAD TRACK
DLAG

lOT 6742 clear control
current address ACO— 1

lOT 6744 load current address
/ get drive number in AC9— 1
/

/ get

Read All function in AC

/ get field in

AC6-8

cylinder bit in AC1
lOT 6746 load Command Register

/ get extended
/

/ get desired track in

GO.
lOT 6741 skip on DONE or ERROR flag

JMP.-1

/ wait for flag

DRST

CIA

/ change

FIELD, 0000
TRACK, 0000
K4000, 4000
CU RENT, 0000
REDALL, 1000
11.13.7

ACO-1

/ lOT 6743 load disk address and

DSKP

TAD K4000
SZA CLA
ERROR, HLT
JMPDONE

AC10=0AC11=1

/ enable clear control

DCLR

lOT 6745 read Status Register

AC for testing

/ compare to expected value

/ skip if status
/

ERROR, disk status

/ to other seek,

read, or write routines.

/ desired field in

AC6-8

/ desired cylinder, surface, and sector
/ expected status
/ any desired

current address

/ Read All function ACO-2

Read Data

The following is an example of a programming sequence that could be used to read information from a disk sector in
the FJead Data mode.

Exannple

BGN,CLACLLIAC
DCLR

/ enable clear control

AC10=0 ACl 1=1

/ lOT 6742 clear control

TADCURENT

/ desired current address

DLCA
TAD DRIVE
TAD REDDAT
TAD FIELD
TAD EXBIT
DLDC
TAD TRACK
DLAG

/ lOT 6744 load current address
/ get drive number in
/ get

ACO—

AC9—

Read Data function in AC

/ get field in

AC6-8

/ get extended cylinder bit in

ACl 1

Command Register
in ACO— 1
desired
track
/ get
Register
Command
6743
load
/ lOT

/ lOT 6746 load

lOT 6741 skip on DONE or ERROR flag

DSKP

JMP.-1

/ wait for flag

DRST

CIA

/ change

lOT 6745 read Status Register

AC for testing

11-51

TAD K4000
SZACLA
ERROR. HLT
JMP DONE

/ compare to expected

value

/skip if status OK
/

ERROR, disk status

/ to other seek,

read, or write routines.

FIELD, 0000

/ desired field in

TRACK, 0000

/ desired

K4000, 4000

/ expected status

CURENT, 0000
REDDAT, 0000

/ any desired
/

AC6-8

cylinder, surface, and sector

current address

read data function ACO-2

SECTION 4 THEORY OF OPERATION
This chapter contains a block diagram description (functional level) and a detailed description of the RK8-E logic.
Figure 11-9 shows the signal flow between the functional groups of logic.

BLOCK DIAGRAM DESCRIPTION

11.14

The RK8-E consists of 8 major groups of logic:
I/O Bus Interface

Command Register
Status Register

Data Break Control
Data Buffer Registers

CRC Register
Control Sequencer (Major States Register and Counters)

Maintenance Logic
11.14.1

I/O Bus Interface

The I/O bus interface (Figure 11-9) provides the following:
a.

A buffer for MD00-MD1

from the OMNIBUS

OT decoder

Timing pulses for the execution of instructions and maintenance operations.

MDOO— MD11 are decoded by the lOT decoder when instructions are executed by the program and generate signals
RK8-E registers, execute skips and interrupts, and generate timing pulses for maintenance operations.
The outputs of the lOT decoder are used as control signals in other sections of the RK8-E. During the data break of

to load the

a write operation, the buffered memory data bits

(MD00-MD1 1) are applied to the Data Buffer Register for transfer

to the selected disk drive. This block of logic also contains bus drivers for signals to the OMNIBUS (i.e., BRK RQST,

INT RQST, SKIP, and INT I/O L) and provides a buffer for signals from the OMNIBUS (i.e., I/O PAUSE and the
time pulses).

11-52

Q
o
o
CO
LU

00
):^

11-53

Command Register

11.14.2

The Command Register (Table 11-13) enables all disk drive operations, i.e., read, write and seek, selects a disk
unit, selects a

drive

memory field for data transfers, enables interrupts, provides the most significant cylinder address bit,

and determines the number of words to be transferred (128 or 256). The Command Register (Figure 11-9)
is loaded
from the AC by a DLDC instruction with DATA 0-DATA 11. Note that the contents of the Command
Register are
decoded and used after the program executes the DLAG instruction (load disk address and GO).
During maintenance operations, the contents of the Command Register are transferred to the AC
using the DMAN
instruction (Table 11-14).

11.14.3

Status Register

The Status Register (Figure 11-9) contains the current status of the selected disk drive (Table 11-12). The program
determines the status of the RK8-E and disk drive by transferring the contents of the Status Register
to the AC using
DRST instruction. The Status Register receives its input from the RK05 Disk Drive and the data break control
logic. The DONE and ERROR flags are applied to the I/O bus interface to
generate skips and interrupts if the skip or
interrupt logic is enabled. Note that bit 3 in the Command Register must be set
(1) to enable an interrupt when the
DONE or ERROR flag sets.

11.14.4

Data Break Control Logic

The data break control logic (Figure 11-10) determines the break priority of the RK8-E, controls direction of
data
transfer (to or from memory), and selects a location in memory for the data transfer.

BRK RQST

DATA0-DATA1
^

PRIORITY
LOGIC

EMA0-EMA2

DSK HAS PRIORITY

^>f

r
CURRENT

COMMAND

ADDRESS
REGISTER

LAST BREAK

—
;k

\INC

LAST
BRK

COUNTER

(^128/256)

BRK RQST

NEW BRK RQST

BRK
ROST

0B4 FULL~1

—n

INT STROBE
(TP3)

TP1

ALLOW BRK
INHIBIT CLEAR

V
Figure 11-10

Data Break Control

11-54

The Current Address Register is loaded from the AC by a DLCA instruction with the initial address to be used in a
data transfer. The Current Address Register is incremented after each data break and applied to the MA lines

(MA00-MA1 1) to sequentially select memory locations for data transfers. Note that the memory field is selected by
bits in the Command Register (Table 11-13) and not incremented when the CA Register is incremented. The
direction of data transfer is determined by the decoded function bits in the Command Register, i.e., during a read
operation, data

transferred

from the Data Buffer Register to memory via the data bus. Time pulses from the

OMNIBUS and control signals from the Data Buffer Register determine the timing of the single cycle data break.
The data break control also generates signals to stall the processor and stop the execution of instructions during a
data transfer.

The data break priority is returned to the OMNIBUS as DATA (priority 0) or DATA 1 (priority 1) to indicate the
priority of the RK8-E. Data break control provides a DATA LATE signal to the Status Register if the processor does
not respond to a BRK RQST within 22.5/15. The last break counter counts the words in a data transfer and sets the

LAST BRK flip-flop when 128 (half block) or 256 words have been transferred.
11.14.5

Data Buffer Register

The Data Buffer Register (Figure 11-11) provides four Data Buffer Registers (DB1-DB4) for temporary storage of
data that is being transferred between memory and the disk drive. The four registers increase the data break latency
of the RK8-E control from 5.6 /is to 22.5 {is. Latency is defined as the maximum time the RK8-E can wait for a

BRK RQST to be accepted by the processor. During a write operation, parallel bits of data (MDOO-MDII) are
received from the OMNIBUS and applied to DB1. The parallel data is dropped into DB4 and shifted out of DB4 on
RK DATA 11 as serial data to the selected disk drive. During a read operation, serial data from the disk is shifted
DB1 and dropped into DB4. The parallel bits out of DB4 are transferred to the data bus for transfer to memory
during a single cycle data break. The control logic associated with the Data Buffer Register controls the registers and
into

generates signals that are applied to the data break control logic. During maintenance operations, the contents of the
CRC Register, Command Register, and Surface/Sector Register can be shifted into DB4 and transferred to the AC or

memory by the OMAN instruction. The shifting of data in these registers is accomplished by the MAIN pulse, which
is

generated by the DMAN instruction.

11.14.6

CRC Register

The CRC Register (Figure 11-12) is a 16-bit multipurpose register with the following functions:
a.

The CRC Register receives a cylinder address from the AC when the DLAG (GO) instruction is executed
by the program and transfers the cylinder address to the selected disk drive.

Makes a bit-by-bit comparison of the cylinder address specified by the program and the cylinder address
from the disk drive to determine if disk has found the correct cylinder.
During a write operation, a 16-bit CRC character is computed, transferred to the disk, and written at the

end of the record.
d.

During a read operation, a 16-bit CRC character is computed and compared with the CRC character
written at the end of the record. If the two characters are different, NOT EQUAL is asserted to set the
CRC ERROR flag. A CRC ERROR is produced if bits are lost or added during the read or write
operation.

The disk address is transferred from the AC as a 12-bit parallel word and bit 11 from the Command Register is added
to the
to the 7 most significant bits of the CRC Register to form the 8-bit cylinder address (Figure 11-5) transferred
the disk
selected disk drive. Bits 12 through 16 are not used for the disk address. The disk address is transferred to
drive on parallel lines during the STROBE major state.

11-55

DATA STATE

MAIN

(DB

FULL)

MD-^RD BUFF/
12th BIT

READ
LD RD BUFF

'C0NT1

DQI EMPTY

DB2 FULL

DB1 FULL

DB2 EMPTY

DB CONT 2

1—DB2

(DB2 FULL)

„

MAIN DATA
'^'^"^

C CONT 2

DB2 FULL

0-»DB2
1-*DB3

DB 2

EMPTY

DB3 EMPTY

DB CONT 3
7i(DB3 FULL)

-CONT 3

DB3 FULL

1-»DB4

0-»DB3

DB3 EMPTY

DB4 EMPTY
MAIN PL

AC1

—
DB CLOCK

DB CONT 4
(DB4 FULL

)

CMD REG BIT4(AC4)
CRC 16
SECTOR ADDR (AC3)

'CONT

CLR SYNC

TEST CLK

DB4

WRT CLK

DB4
K

DATA STATE

EMPTY

MAIN PULSE
{AC3 AND AC4)

12th BIT

TO MEMORY <7 DATA 00 - DATA 11

WRT
^l-^

SYNC

OATA BUFFER
1-—DB2
1—DBS

1— DB4

0—*DB4

WRT BUFF-* DATA

TO DISK
DB CLK
TEST
CLOCK

ONE
SHOT

SHOT

50ps

ISOfJS

B TP2

OMNIBUS SIGNALS

Figure 11-11

Data Buffer Register

11-56

DATA BUFFER CLOCK

ONE

n
o

u
en

<
H

fi
!5

<r
1-

H
o
o

O
CC
O

11-57

When the RK8-E moves into the DATA state, the CRC Register is cleared and the computation of a CRC character is
started.

During write operations, the CRC character is transferred to the disk drive during the CRC state as a 16-bit serial

word. The serial bits are shifted out of the CRC Register to the disk drive and written at the end of the data.
During read operations, the CRC character is computed from the data read from the disk and compared with the
CRC character that was written at the end of the data. The CRC Register makes a bit-by-bit comparison of the two
CRC characters, and if they are different, NOT EQUAL is asserted to set the CRC ERROR flag.

The contents of the CRC Register are checked using the maintenance instruction. The bits in the CRC Register are
shifted into Data Buffer 4 and transferred to the AC (Table 11-14).

1 1 .14.7

Control Sequencer

The control sequencer (Figures 11-13 and 11-14) comprises the Major States Register, word counter (128 or 256
words), and the bit counter. The word counter and bit counter keep track of the number of words transferred to or
from the disk drive. The bit counter counts 12 bits from the disk drive and increments the word counter each time a
word (12 bits) is read from the disk. After 256 words are read, the data transfer is stopped and the CRC character is
written on the disk during a write, or read from the disk during a read. If bit 5 in the Command Register is set (1),
the data transfer

stopped after 128 words are read or written, but the disk drive continues to write all zeroes

during a write operation or read all zeroes during a read operation until 256 words have been written or read. This
allows the RK8-E to process the CRC character, which is always written at the end of the data (Figure 11-7).

The Major States

i.e.,

PREAMBLE, HEADER, DATA, CRC, and

POSTAMBLE.
11.14.7.1

Major States - The Major States Register (Figures 11-13 and 11-14) controls each step the RK8-E

control progresses through to perform a seek, read, or write operation. Each major state causes specific operations to

be performed (Table 11-2 and Figure 11-7).

The Major States Register is a shift register that shifts a binary 1 starting at the IDLE state and ending with the END
states as shown in Figure 11-7 unless an error occurs

(i.e.,

an ADDRS ERROR) or the function does not require all

major states (i.e., sector, seek, and recalibrate).
11.14.7.2 IDLE State - The RK8-E must be in the IDLE state (Figure 11-13) to allow initiation of a disk function
and returns to the IDLE state after an operation is completed. The IDLE state indicates that the control is not busy

and that it is capable of accepting lOT instructions from the processor (Figure 11-14). The IDLE flip-flop is cleared
when the program executes a DLAG instruction (load disk address and GO) or the CLR drive (DCLD) instruction.
The DCLD instruction initiates a special state called RESTORE, which is discussed in Paragraph 11.15.3.

The IDLE state flip-flop is set by any of the following conditions to return the control to the IDLE state to wait for
RK8-E instructions.
a.

At the end of ERASE DELAY during a write function.

During last break of a read operation (after Data Buffer Register is empty).

When the selected disk drive asserts ACKNOWLEDGE during a seek only operation.

When the ERROR flag is set (Table 11-12).

11-58

FILE READY

RESTORE
D

RESTORE

ERROR

RD CMD

CLR DRIVE

ACKNOWLEDGE

FILE

READY

STROBE
D

STROBE
GO
C

ACKNOWLEDGE
CK HEADER AND RD
CK HEADER AND

RDY TO
SK/RD/WRT
ACKNOWLEDGE

WRT

DH=

DSKOK

HEADER

SECTOR MK

—
C

HEADER B

HEADER C

HEADER B

HEADER A

HEADER
C

RD SYNC BIT

—CJ—
C

D
HEADER C

SECTOR SEEK

WRT CMD

WRT GATE
1

WRITE
C

HEADER C

HEADER E

Figure 11-13

Major States Register

11-59

RD CMP

[

>,^^

HEADER D

y) HEADER B

SECTOR MK

ONE SHOT

READ DELAY

READ
DELAY

85^s

:ND STATE

SECTOR seek]

^/O

SECTOR MK

WRITE SYNC DELAY

HEADER D (1) H J

MAIN
PULSE(AC 2)
RD CLK

— LAST WORD
— 128th WORD

4-12

WRTCLK

t-;-128/
12th BIT

+3V-- D

COUNTER

-DATA CLOCK

WRITE CLOCK-DATA
2.88MHz

OSC

DATA STATE
C RC DATA

o
^

L__

]

N^_WRTCLK
y'~AND DAT/!
^

WRT
^b'^ij

CRC STATE

READ CLOCK-DATA

Figure 11-14

Read/Write Delays and Counters

11-60

RESTORE State - The RESTORE state is a special state (Figure 11-13) used to clear SELECT ERRORS
CYLINDER ADDRESS ERRORS. RESTORE is set by FILE READY and the CLR DRIVE command,
generated by the DCLD instruction. When the selected disk asserts ACKNOWLEDGE, the RESTORE flip-flop is
11.14.7.3

and

cleared and the Major States Register goes back to the IDLE state to wait for RK8-E instructions. Thus, the RK8-E
uses only one state for the clear operation and the control is released (made not busy) while the disk drive returns to

the home position.

11.14.7.4 STROBE State — The STROBE state (Figure 11-13) is used to transfer the cylinder address from the
CRC Register to the disk drive and wait for the selected drive to ACKNOWLEDGE the cylinder address. The
STROBE flip-flop is set by GO when the DLAG instruction is executed by the program if the selected disk drive is
ready (FILE READY asserted). STROBE is cleared when ACKNOWLEDGE is received from the selected drive and
the Major States Register moves to the HEADER A state or SECTOR SEEK state (Figure 11-7) when the selected
drive is ready to seek, read or write (Figure 11-14),

HEADER A State -The HEADER A state (Figure 11-13)

11„14.7.5

used to start a read delay (Figure 11-15)

and wait for a sector mark during read and write functions. When a sector mark is obtained from the disk drive, the

HEADER B state

entered and the HEADER A state is cleared by HEADER B.

HEADER B State - The HEADER B state (Figure 11-14) used to turn READ on at the end of READ
DELAY (Figure 1-12) and read zeroes until a SYNC pulse encountered. The SYNC pulse indicates the beginning
of the HEADER area of the disk format.
11 .14.7.6

when a sector mark is received from the disk (Figure
(SYNC pulse) is written on the disk to indicate where the
HEADER area starts. When the SYNC pulse \s read or written, the RK8-E advances to the HEADER C state and
During a write operation, the write sync delay

triggered

11-14). After a 140 /us (write sync delay), a one bit

HEADER Bis cleared.

HEADER C State - The HEADER C state (Figure 11-14) used to read the 16-bit HEADER word and
cleared when the divide-by-16
bit-by-bit with the disk address in the CRC Register. HEADER C
counter (Figure 11-15) asserts 16th bit to indicate the 16th bit of the HEADER word has been read from the disk
sets SECTOR SEEK (Figure 11-14) and starts the SECTOR SEEK major state.
drive. When HEADER C clears,
11.14.7.7

compare

11.14.7.8
set

SECTOR SEEK State - When the control enters the SECTOR SEEK state, cylinder address ERROR is

the cylinder address does not equal the HEADER word read from the disk during the HEADER C state (Figure

11-12).

During the

SECTOR SEEK state, the sector address

lines

from the

RK05 are compared with the

Surface/Sector Register.

HEADER D State - The HEADER D state used to wait for the completion of READ DLY (85 ms)
during a read function or the completion of SYNC DLY during a write operation. If this is a read function, the
read, the control advances to the HEADER
controller reads all zeroes until a SYNC bit is read. When the sync bit
E state. If this is a write function, the control writes zeroes and waits for SYNC DLY, then writes the SYNC bit (a
written, the RK8-E moves to the HEADER E state and clears the HEADER D
data 1). When the SYNC bit
11.14.7.9

flip-flop.

HEADER E State - The HEADER E state used to read, but ignores 16 bits of data during a read
HEADER word in the CRC Register is written. When the 16-bit
HEADER word has been read or written, the Major States Register advances to the DATA state.
11.14.7.10

operation. During a write operation, the 16-bit

11-61

<WA(T FOR A

RK8E
INSTRUCTION

^
^

]

Q
CONTROL IS NOT BUSY

^
GET THE SELECTED
DRIVE INTO A WRITE

PROTECT STATUS AT
TP3

IT ISA READ, WRITE,
GEEK, OR DRIVE

RECALIBRATE

AT TP3 ASSERT

ATTP3"LDDISK ADDRS"

"CLR DRIVE CMD"
SET RESTORE

EXTCYL ADDRS -CRCC,
AC0 6-CRC5n
AC7

-SECTOR SURFACE
INITIALIZE SELECTED
DRIVE AND SEEK
CYLINDER ADDRS ZERO

CLEAR STATUS REG
AND AC

"RDYS/R/W IS

NOT TRUE SET SELECT
ERROR AND STOP

CONTROL WAS

BUSY SET BUSY

ERROR

Figure 11-15

R K8-E Flow Diagram (sheet 1

11-62

-E>

AS THE CONTROL ENTERS
A MAJOR STATE (MSI
THE PREVIOUS MS IS

CLEARED

STROBE STATE
ENABLE CYLINDER
ADDRS(CRC4-11)
TO THE DISK ADDRESS
LINES, CLEAR IDLE
STATE

WAIT FOR "DISK ADDRESS

ACKNOWLEDGE"
CLR STROBE
(AND RESTOREI

SET DONE FLAG

H!>

DRIVE SEEKING

MONITOR DISK
"RDYS/R/W"
LINE,

DRIVE IS POSITIONING HEADS OVER

THE CYLINDER ADDRS

SK/RDOR
SK/WRT

SK/CHK/RDORSK/
CHK/WRT

(^MS

HEADER A STATE
WAIT FOR "SECTOR

MARK"
START READ DELAY

Tms

HEADER B STATE
AT THE END OF

READ DELAY SET
READ
READ ZEROS UNTIL
"SYNC BIT" IS READ
(FIRST ONE BIT OF
SECTOR)

Figure 11-15

R K8-E Flow Diagram (sheet 2)

11-63

HEADER C STATE
CLEAR THE COUNTERS

READ THE 16 BIT
HEADER WORD INTO
THE CRC REGISTER
AND COMPARE IT BIT
FOR BIT WITH THE
CYLINDER ADDRSIN
THE CRC REGISTER

IF WRITE TRANSFER
DATA FROM THE CP VIA
DATA BREAK REQUEST
TO THE DATA BUFFER
TRY TO KEEP THE
DATA BUFFER FULL

-6

[>
Q

SECTOR SEEK STATE

CLEAR READ

SET "CYL ADDRS
ERROR", DONE FLAG,

AND IDLE

-E>

WAIT FOR A SECTOR

MARK AND COMPARE
THE SECTOR ADDRS

READ COMMAND

START "READ DELAY"

IF WRITE COMMAND
START "SYNC DELAY"

Figure 11-15

RK8-E Flow Diagram (sheet 3)

11-64

HEADER D STATE
SET-UP FOR THE

HEADER WORD

READ

^X^

READ

\,^^

\„^^^ WRITE

WRITE

SET WRITE

AT THE END OF READ
DELAY SET READ

WRITE ZEROS FOR
THE LENGTH OF
"SYMC DELAY"

READ ZEROS UNTIL THE
SYNC BIT IS READ

THEM WRITE THE
"SYIMC BIT"

r MS

HEADER E STATE
CLEAR COUNTERS

WRITE

^>^

READ

^^v.

READ

^^^WRITE ^y"^
'

WRITE A 16 BIT

COUNT AND IGNORE

HEADER WORD

FIRST 16 BITS

SPECIFIED BY THE

CRC REGISTER

Figure 11-15

R K8-E Flow Diagram (sheet 4)

11-65

^
c

DATA STATE
CLEAR COUNTERS
AND THE CRC
REGISTER

-6SHIFT A 12 BIT WORD

SHIFT 12 BITS FROM

FROM DB4 TO THE DISK
AND CRC GENERATOR
INCREMENT WORD
CNTR ON 12TH BIT

THE DISK INTO DB1
AND INTO THE CRC
GENERATOR.
INCREMENT WORD

COUNTER ON 12TH BIT

DB1 IS EMPTY

ISSUE ABRKRGSTTO

WHEN A 12 BIT WORD IS

TRANSFER DATA TO
THE UPPER DATA
BUFFER FROM THE CP.
TRY TO KEEP ALL FOUR
DATA BUFFERS FULL

ASSEMBLED IN DB4,
ISSUE ABRK RQSTTO

TRANSFER THE WORD
TOTHECP. TRY TO
KEEP ALL 4 DATA
BUFFERS EMPTY FOR
INCOMING DATA FROM
THE DISK

INCREMENT LAST BR
COUNTER EACH TIME A
WORD IS TRANSFERRED
T0DB1

INCREMENT LAST BRK
COUNTER EACH TIME A
WORD IS TRANSFERRED
FROM DB4

WRITE ZEROS IN THE
REMAINING PORTION
OF THE SECTOR.
SHIFT ZEROS INTO THE
CRC GENERATOR.

EACH 12TH BIT OF
ZEROS INCREMENT
THE WORD COUNTER.
INHIBIT DATA REQUEST
LATE

READ THE REMAINING
PORTION OF THE SECTOR
("ZEROS") INTO THE CRC
GENERATOR. INHIBIT
DATA REQUEST LATE
12TH BIT INCREMENTS

WORD COUNTER

Figure 11-15

RK8-E Flow Diagram (sheet 5)
11-66

Cm
CLEAR COUNTERS

WRITE A 16BITCRC
CHECK WORD FROM
CRC REGISTER

READ A 16 BIT CRC
CHECK WORD FROM
DISK INTO CRC
REGISTER. COMPARE
EACH BIT WITH THE
GENERATED CRC WORD

IF CRC FROM DISK
DID NOT EQUAL THE

GENERATED CRC
SET CRC ERROR

AT END OF ERASE
DELAY CLEAR WRITE
WAIT UNTIL THE DATA
IN THE DATA BUFFER IS
EMPTIED INTO THE CP
ON LAST BREAK

SET DONE FLAG

Figure 11-15

RK8-E Flow Diagram (sheet 6)

11-67

INITIALIZE CONTROL
CLEAR MAJOR

LOAD (AC) INTO THE CA
REGISTER CLEAR AC

REGISTERS, SET

CONTROL TO IDLE,
AND CLEAR AC

-o

LOAD (AC) INTO THE

COMMAND REGISTER
AND CLEAR AC

DONE OR
ERROR FLAG IS SET

IF THE

ASSERT SKIP LINE

CLEAR THE AC AND
LOAD THE CONTENTS
OF THE STATUS
REGISTER INTO THE AC

Figure 11-15

RK8-E Flow Diagram (sheet 7)

11-68

MAINTENANCE
(OMAN
I

SET MAINTENANCE

MODE

CANNOT CLEAR
MAINTENANCE MODE
BY THIS INSTRUCTION

WHEN BRK RQSTIS
ACCEPTED, TRANSFER
DATA FROM THE
MEMORY LOCATION

WHEN THE BRK RQST
TRANSFER
DATA FR0MDB4 INTO
IS ACCEPTED,

THE MEMORY LOCATION
SPECIFIED BY THE

SPECIFIED BY THE

CURRENT ADDRESS

INTO DB1

DATA BUFFER CONTROL
DROPS DATA INTO
LOWER DATA BUFFER IF
DATA IS AVAILABLE IN
THE BUFFER ABOVE

DATA BUFFER CONTROL
DROPS DATA INTO THE
LOWEST EMPTY BUFFER

WAS EMPTY SET
DATA REQUEST LATE
IF DB4

IFDB1 WAS FULL SET
DATA REQUEST LATE

INCREMENT

CURRENT ADDRESS

Figure 11-15

R K8-E Flow Diagram (sheet 8)

11-69

CLEAR AC AND LOAD
DB4INT0 AC

DATA BUFFER CONTROL
DROPS DATA INTO
LOWER DATA BUFFER IF
DATA IS AVAILABLE
FROM THE BUFFER
ABOVE

SHIFT AC BIT10INTO

THE MSB OF OBI

INCREMENT
BIT COUNTERS

ON 12TH BIT DROP
THE UPPER BUFFER
INTO THE LOWEST
EMPTY BUFFER
SHIFT LSB OF THE

SECTOR-SURFACE REG
INTO THE MSB OF
THE LOWER DB
IF IT IS

EACH 12THBIT
INCREIV1ENTS

ENABLED

WORD COUNTER

SHIFT LSB OF THE

COMMAND REG INTO
THE MSB OF THE
LOWER DB
IF IT IS

ENABLED

SET DONE FLAG

SHIFT LSB OF THE CRC

REG INTO THE MSB OF
THE LOWER DB
IF IT IS ENABLED
IF DATA BUFFER IS
FULL SET DATA
REQUEST LATE

ENABLE LOWER DB
AS A SHI FT REG

HZ>

Figure 11-15

RK8-E Flow Diagram (sheet 9)

11-70

-E>

DATA

11.14.7.11
State - The
state is used to transfer 256 data words from PDP-8/E memory to the disk
drive during a write operation, or transfer 256 words of data from the disk drive to memory during a read operation.

DATA

The data break control logic tries to keep the Data Buffer full during a write operation and tries to keep the Data
Buffer empty during a read operation (the block diagram of the Data Buffer Register is discussed in Paragraph
11.14.5 and the block diagram of the Data Break control logic is discussed in Paragraph 11.14.4). The DATA state
ends when 256 words have been transferred and the word counter asserts LAST WORD. If the RK8-E has been
instructed to write 128 words, 128th word is asserted after 128 words (half block) have been transferred. The 128th
word ends data transfer operations and the disk reads or writes zeroes until the full block of data (256 words) has

been read or written. When

LAST WORD is asserted, the RK8-E advances to the CRC state and clears the DATA

state flip-flop.

CRC State - The CRC state (Figure 11-13) is used to write the CRC character, computed by the CRC
on the disk at the end of a sector during write operation. During read operations, the CRC
character computed by the CRC Register during the data transfer is compared with the CRC character read from the
disk. An Exclusive OR circuit on the CRC Register makes a bit-by-bit comparison of the CRC character
read from
the disk and the CRC character shifted out of the CRC Register. If the two characters are not equal, the CRC
ERROR flag is set to indicate a CRC ERROR occurred during the data transfer. The program must check the Status
Register to determine
the CRC ERROR set the ERROR flag. The Major States Register advances to the END state
and clears the CRC state flip-flop when 16th BIT L is asserted.
11.14.7.12

11.14.7.13 END State -The END state is used by the read operation to allow the Data Buffer Register to be
emptied by the single cycle data break, set the CRC ERROR flag if the CRC characters were not equal, clear READ,

DONE flag, and return the RK8-E to the IDLE state (not busy). During a write operation, the controller
WRITE
cleared, the DONE flag is set and the RK8-E is
returned to the IDLE state. Note that there
no CRC character comparison during a write operation and no CRC
ERROR should be detected.

set the
starts

ERASE DLY (Figure 11-13) and after 25

jjls,

11.14.8

Read/Write Delays, Clocks, and Counters

The read/write delays, clocks, and counters generate signals to assist the Major States Register in the control of disk
operations and help to develop the disk format.
11.14.8.1

Write Data Clock - The write data clock (Figure 11-14) is a 2.88 MHz oscillator that is used to generate

WRT CLK pulses (Figure 11-2) during a write operation. The time between WRT CLK pulses (690 ns) referred
to as a bit cell, which
used to write data. The WRT DATA CLK and a SYNC bit, CRC DATA bit, or a DATA bit
the

are written on the disk cartridge.

11.14.8.2

Write Sync Delay - Write sync delay (Figure 11-14)

MARK from the disk drive

140 jus delay that is started when a SECTOR

detected during write operations. After 140 /xs, WRT SYNC is asserted and the SYNC

bit is written on the disk drive.

11.14.8.3 Read Delay - The read delay (Figure 11-14) is an 85 jUS delay that is started when the SECTOR MK
from the disk drive is detected, if the RK8-E is in the HEADER D state of a read operation. The 85 jus delay allows
the control to wait for a SYNC bit before advancing to the HEADER E state. RD DLY asserts the RD gate to allow
the RK05to read.

11.14.8.4 Read Clock Data - The READ flip-flop (Figure 11-14) is set by RD DATA from the RK05 and cleared
by RD CLK to generate the READ signal. The READ signal is used to enable READ data pulses to be applied to the

Data Buffer Register. The READ data pulses are clocked into the Data Buffer Register by the RD CLK signal.

11-71

Counters -The RK8-E contains 4 counters (Figure 11-14) a divide-by-1 2-bit counter, a divide-by-1 6-bit
the bits of data
counter, a divide-by-1 28- or 256-word counter and a break counter. The divide-by-1 2 counter counts
by 1.
incremented
is
counter
word
as they are read from the disk drive. Each time 12 bits (one word) are read, the
the
in
bit
(bit
HALF
BLOCK
If
the
5)
After 256 words are read, LAST WORD L is asserted to end a data transfer.
the
causes
This
written.
or
read
are
Command Register is set, the 128th WORD signal is asserted after 128 words
11.14.8.5

RK8-E to stop data transfers between memory and the disk drive, but the disk drive continues to read or write all
zeroes until

LAST WORD L is asserted (256 words have been read or written). When LAST WORD is asserted, the

or written on the
data transfer is complete. The 16-bit counter asserts 16th bit when 16 bits are read from the disk
12.
instead
of
bits
count
16
written
to
or
read
disk. This is used when the PREAMBLE and CRC are

The break counter is incremented during TP2 time of a break cycle to count the single cycle data breaks. LAST BRK
H is asserted after 128 or 256 words have been transferred to or from memory. There are 128 break cycles when the

HALF BLOCK bit (bit 5) in the Command Register is a 1. Note that LAST BRK does not stop a read or write
last 128
operation because 256 words must be read or written to end an operation. If HALF BLOCK is set (1), the
words are all zeroes and not used.

11.14.9

Maintenance Logic

The maintenance logic (Figure 11-16) allows the program (software) to check the RK8-E operation. The program
can transfer the contents of the Data Buffer Register, CRC Register, Command Register, and Surface/Sector Register
to the AC or memory if the program executes the DMAN instruction. The operation performed when the DMAN
instruction is executed by the program is determined by the contents of the AC (Table 1 1-14 and Figure 11-15). The

maintenance

logic

allows

the

program to

shift

the contents of the

CRC

Command

DMAN instruction or to memory
generated each time a DMAN
accomplished by the MAIN pulse, which

Surface/Sector Register into the Data Buffer Register for transfer to the AC by a

is
by a data break. The shifting of registers is
when to transfer the
determine
and
of
shifts
of
the
number
track
must
keep
program
instruction is executed. The

data to the AC or memory.

The maintenance logic checks all counters in the RK8-E control and allows data to be transferred from the AC to
the Data Buffer Register.

The maintenance logic provides timing pulses to the major registers, data break control, and control sequencer to
check these groups of logic. Note that the DMAN instruction disables the DLAG (GO) lOT and a clear operation
must be performed to allow the program to continue after maintenance operations are executed by the program.
11.15

DETAILED LOGIC DESCRIPTION

The logic in the RK8-E is divided into functional groups for discussion purposes. The block diagram. Figure 11-9,
and the flow diagram. Figure 11-15, should be used to understand the interaction of the logic, the signal flow within
the RK8-E, and the input or output signals.
11.15.1

I/O Bus Interface

The I/O bus interface consists of the MD receivers, lOT decoder, interrupt and skip logic, and timing and control
logic.

MD Receivers - The MD receivers allow data on the MD lines to be applied to the device select logic and
executed by the program. The MD receivers also allow data on the
I/O decoder when an RK8-E I/O instruction
during a write operation (MD ^ RD BUFF L and MD -> RK L are
Register
Buffer
the
Data
applied
to
lines
to
be
MD
11.15.1.1

asserted).

11-72

MAINTENANCE ENABLE AND PULSE GENERATOR
MAIN (1)

ACO H

J
6RK7(DMAN)

AC10H

MAIN

AC7

~\ MAIN
^J MAIN
A M ENABLE
hit

L
1

y) 6RK7 (OMAN)H

\
/

DATA BUFFER AND MAINTENANCE CONTROL LOGIC
6KR7 (OMAN)
MAIN (1)

7(DMAN)
^

—^^

AC
DATA
|BITSy (DATAO -DATA11)
I

CONTROL DONE (MAINTENANCE)
LAST WORD
SHIFT DB H

-H2

12th BIT

-M28/256

MAIN(1)H

CONTROL DONE

NOTE- The function of each AC bit is shown in table 3-4,

CONTROL

*OMNIBUS SIGNALS

DONE

Figure 11-16

Maintenance Logic

lOT Decoder Logic - The lOT decoder (Figure 11-17) decodes IVID bits (instructions) from the Memory
Data Bus and generates signals to control the operation of the RK8-E. Bits MD3-1 1 are gated by MD ^ RK L when
11.15.1.2

is executed by the
I/O PAUSE L is asserted by the processor. I/O PAUSE L is asserted anytime an lOT instruction
lOT decoder (an
to
the
applied
to
be
program. MD3~8 generates a signal DEVICE RK H and enables bits MD9-11

8251

IC). The 8251

IC is a

BCD to decimal decoder (see Volume

Appendix A for truth table, logic diagram, and

executed by the
pin locations) that produces a low on one output line to indicate which instruction has been
a DLCA (6744)
indicates
which
pin
on
9,
a
low
produce
high
(100)
program. For example, MD9 low, MDIOandll
instruction was executed by the program. The jumpers on

MD6-8 are used to select the device code for the RK8-E

when multiple systems are installed (see Table 11-3 for jumpers to select the device codes). Internal I/O L is asserted
RK8-E is
by the DEVICE RK signal to prevent the processor from executing other lOT instructions while the
executing an lOT instruction.

11-73

11-74

11.15.2

Control Logic

11.15.2.1

C Line Select Logic - The C line select logic (Figure 11-17) controls the direction of data flow between

the Data Bus and the AC and determines whether the AC is cleared or not. Table 1 1-15 shows the status of CO and

CI to transfer data between the Data Bus and the AC using the RK8-E lOT instructions.

Table 11-15
C-Llne Select Levels and Transfer Operations
Instruction

Transfer Operation

DCLR
DLAG
DLCA
DRST
DLDC

Low
Low
Low
Low
Low
Low

High

AC->Data Bus, CKAC

High
High

AC^Data Bus, (KAC
AC^Data Bus, O^AC

Low

Data Bus^AC

High

AC->Data Bus (KAC

High

AC^Data Bus, 0->AC

DMAN
11.15.2.2

Time Pulse 3 (TP3) Logic - TP3 (Figure 11-18) is used throughout the RK8-E modules to enable

gates

ERROR (Paragraph 11.15.4).
for the execution of instructions. SHORT TP3 is used in the detection of a BUSY
IDLE - The IDLE state indicates that the control is not busy; the control must be in the IDLE state to
(Figure 11-18) instructions.
enable the execution of the 6RK2 (Figure 11-17), 6RK3, 6RK4, 6RK6, and 6RK7
11.15.2.3

Clear Logic - The logic of the RK8-E and/or the RK05 Disk Drives is cleared as

11.15.2.4

follows:

By INITIALIZE during power up or if the CLEAR key is depressed on the PDP-8/E console.

The RK8-E logic is cleared by CLR ALL L if the 6RK2 (DCLR) instruction is executed by the
and AC bits 1

By CLR ALL L and CLR DRV CMD L if the 6RK2 (DCLR) instruction is executed by the

AC bits 1
If a

program

and 1 1 equal 01 (Table 11-11).

and 1 1 equal

program and

(Table 11-11).

power failure is experienced and POWER OK H from the CPU goes low (Figure 11-18).
,

SHORT TP3 H

B DATA 10 H

FROM AC

B DATA 1 1 L

BTP3 OK H
TP3 H

E44^ CLR

DRV CMD L

6RK2 H

CLR ALL H

—A-»

E33^

CLR ALL L

E33
J^

INITIALIZE H

E>^

POWER OK H

Figure 11-18

INITIALIZE, CLEAR ALL and
Time Pulse 3 Logic
11-75

11.15.2.5

Interrupt Logic - INT

RQST L (Figure 11-19) is asserted to interrupt the program if ENABLE INT H is

asserted (bit 3 in the Command Register must be 1) and the

11.15.2.6

Skip Logic -The SKIP

line

grounded

ERROR or DONE flags are set.
ERROR flag or the DONE flag is set and the DSKP

the

instruction is executed by the program (Figure 11-19).

INT

RQST L

ERROR FLAG L

DONE FLAG (0) H
6RK1 H (DSKP)

Figure 1 1-19

11.15.3

Interrupt and Skip Logic

Command Register

The Command

address extended

loaded from the

AC by a 6RK6 (DLDC) instruction. The Command

used to select a disk functipn, enable interrupts, read or write 128 words instead of 256,

memory,

(EXT CYL ADDRS) for cylinder addressing. The
Appendix A for truth table, logic, and timing diagram)
that contain 12-f lip-flops, which are set or cleared by bits from the AC. The inputs to
the flip-flops are enabled by
DEVICE RK H, which asserts DATA ENAB L when the 6RK6 instruction is executed by the program to load the
Command Register. The outputs of the Command Register are applied to a function decoder, unit select decoder,
and the RK8-E control logic. Note that bit 1 1 is applied to the CRC Register to be used in cylinder addressing.
select a

unit,

and proyide a

Command Register consists of three 8271 ICs (see Volume

bit

The contents of the Command Register can be shifted into Data Buffer 4 if the 6RK7 (DMAN) instruction is
executed by the program and AC bit 3 is set. The MAIN PL H signal shifts the contents of the Command Register
one

bit

position each time the

becomes a

DMAN instruction

12-bit serial word that

executed by the program. The contents of the Command

applied to

DB4 in the Data Buffer Register as EXT CYL ADDRS H

(Figure 11-25).

The Command Register is cleared anytime CLR ALL L is asserted (Paragraph 11.15.1.2).
11.15.3.1 Function Decoder - The function decoder (Figure 11-20) is an 74155 IC that
decodes function bits
00-02 and determines what function is to be performed by the RK8-E and the selected RK05. The 74155 IC (see

Section 7 for the truth table, pin locator, and logic diagram) is a 3-line to 8-line decoder that generates
a low on one
output line to select one of the RK8-E functions (Table 11-13). As an example, if FOO is high and F01
and F02 are
low, the function is to seek a cylinder, check the HEADER, and write data on the specified
sector.

11.15.3.2 Unit Select Decoder - The unit select decoder (Figure 11-20) decodes the unit
select bits (UNIT SEL
and UNIT SEL 1) from the Command Register to select one of the RK05 Disk Drives.
The unit select decoder is a
74155 IC that decodes the two unit select bits and grounds one of the unit select lines. The 74155 IC (see Section
7
for truth table, pin locator, and logic) is used as 2-line to 4-line
decoder that grounds one of the unit select lines and
selects one of the RK05 Disk Drives. As an example, if both unit
select bits are high (1
pin 4 on
1),

grounded and drive 3 is selected for an operation.

11-76

the 74155 IC is

E
E
o

o
o
CM

X X

:*:

to
a.

aaaariiQarii

QQSS
-J
-I
0)

L.f

11-77

z ?
<
n
S CD

Status Register

11.15.4

The Status Register (Figure 11-21) provides current status of the RK8-E and the selected RK05 Disl< Drive to the
program. The contents of the Status Register are transferred to the AC for evaluation by the program if the 6RK5
(DRST) instruction is executed by the program (Figure 11-27). The flip-flops that make up the Status Register
supply inputs to the output data multiplexer (Figure 11-27) and are transferred to the AC via the Data Bus by the
6RK2 instruction. The flip-flops in the Status Register provide Is (set) or Os (cleared) to indicate error conditions.
11.15.4.1

TRANSFER DONE -The TRANSFER DONE flag (ACO) is set (Figure 11-21) during maintenance

operations as follows:

By the LAST WORD PL H signal at the end of a data transfer operation. LAST WORD PL H is asserted
after 256 words have been transferred. Note, if a half block or 128 words are transferred, the

TRANSFER DONE flag is not set until 256 words have been read or written.
By IDLE (1) H

the

IDLE flip-flop is set by the detection of an error during an operation or at the

completion of an operation.

By IDLE (1) H and RDY S/R/W if bit 4 (ENABLE SEEK DONE) is set.

11.15.4.2

HEADS IN MOTION -HEADS IN MOTION H (ACl) is asserted when the read/write heads on the

selected drive are in motion (Figure 11-21).

SEEK FAIL -SEEK FAIL (ACS) is set (1) when the DSK FAIL L signal from the RK05 is asserted
(Figure 11-21). DSK FAIL is asserted by the selected disk drive if it fails to seek the cylinder address specified by

11.15.4.3

program. A recalibrate operation must be executed by the program to clear this error condition.

DRIVE STATUS ERROR - The DRIVE STATUS ERR (AC6) is set when the selected disk drive is not
ready (i.e., not turned on) by FILE READY L from the RK05 (Figure 11-21). Some action must betaken by the
11.15.4.4

operator to clear this bit, i.e., power up the affected RK05.

CONTROL BUSY ERROR -CONTROL BUSY ERROR is set (1) if the program tries to do a DLAG,
DCLR with AC=10, DLDC, or DLCA instruction while the IDLE flip-flop is cleared (Figure 11-21). Note that the
11.15.4.5

control

busy unless the IDLE flip-flop in the Major States Register is set. This error occurs most often when new

programs are debugged, a rewrite of the program or routine that caused the error should eliminate the problem.

TIME OUT ERROR -TIME OUT ERROR is set (1) if the control has been busy for more than 280 ms
(Figure 11-21) or more than 7 revolutions of the disk cartridge. The DSK INDEX MK L signal is asserted once for
11.15.4.6

each revolution of the disk and applied as the clock input to the 74193 IC (see Section 7 for pin locations and logic
diagram). The 74193 IC is a 3-bit binary counter that sets the TIME OUT ERR bit in the Status Register if the Major
States Register remains in some state other than IDLE for 280 ms. The binary counter is cleared each time the Major
States Register goes to the IDLE state and starts a new countdown each time the IDLE flip-flop is cleared.

11.15.4.7

WRITE LOCK ERROR - WRITE LOCK ERROR (AC7) is set if the program tries to do a write

operation on a disk drive that has been write protected (Figure 11-21). If the selected disk drive has been write
STATUS L from the write protected disk drive is high and the WRT LOCK ERR flip-flop sets
protected, DSK

WRT

when the WRT CMD is issued by the program. The WRT LOCK ERR flip-flop in the RK8-E is cleared by LD DISK
ADDRS H if the affected disk drive is deselected. The WRT PROT switch of the affected disk drive must be
depressed to allow data to be written on any drive that has been write protected. Note that a disk drive is write
protected by programming the write protect function or by depressing WRT PROT switch on the RK05 (Table
11-13).

11-78

X
c;
<•>

< '^

li-

111

7
O <

UJ
lO

o
n

'HHi'

11-79

11.15.4.8

CRC ERROR - The CRC ERROR (ACS) bit is set

the CRC character read from the disl< drive does

not equal the CRC computed by the CRC Register during a read operation. The CRC character read from the disl<

during the CRC state is compared bit-by-bit with the CRC character computed by the RK8-E (Figure 11-12). If the

CRC characters are not equal, NOT EQUAL (0) H is asserted low and when the Major States Register enters the
END state the CRC ERROR bit is set.
11.15.4.9 DATA REQUEST LATE - DATA REQUEST LATE (AC9) is set
the processor does not respond to a
BRK RQST within 22.5 /us. If the processor does not respond in time, the Data Buffer Register is emptied during a
write operation or filled during a read operation. This causes one or more data words to be lost. The DATA RQST
if

LATE flip-flop (Figure 11-21) is set by one of the following:
HI

RD CLK and DB CONT

(H) during a read operation. This condition indicates the Data Buffer

DATA CLK OK H and DB CONT 4 (0) H during a write operation. This condition indicates the Data

Buffer Register is empty and there is no data to be written on the disk cartridge.

11.15.4.10

DRIVE STATUS ERROR - DRIVE STATUS ERROR (AGIO) is set if DRIVE STATUS BAD H is

asserted and the program initiates a load disk address (DLAG), attempts a clear drive command operation, or if the
disk capacity is exceeded (disk address greater than 3128). The conditions that cause DRIVE STATUS BAD H to be

asserted are given in Table 11-12, bit 10.

11.15.4.11 CYLINDER ADDRESS ERROR - CYLINDER ADDRESS ERROR (AC11) is set if the HEADER
word of a sector does not agree with the cylinder address sent to the disk drive. The HEADER word is read from a

HEADER C major state and compared with the cylinder address in the CRC Register. If the
HEADER word and the cylinder address in the CRC Register (Figure 11-12) are NOT EQUAL, CYLINDER ADDRS
ERR set and the TRANSFER DONE flag sets.

sector during the

ERROR Flag
The ERROR flag asserted by any of the following errors, which also set bits in the Status Register.
11.15.5

BUSY ERR
CRC ERR
TIME OUT ERR
DRIVE STATUS ERR
CYL ADDRS ERR

b.
c.

d.
e.

the

ERROR flag

set

and the DSKP instruction is executed by the program, the SKIP line is grounded. This

causes the program to skip an instruction (Figure 11-19). If the INTERRUPT ENABLE bit in the Command Register
(bits)

is a 1

11.1 5.6

and the ERROR flag is set, the program will be interrupted by an INT RQST (Figure 11-19).

Sector Address Comparator

The sector address comparator (Figure 11-22) compares the address in the Surface Sector Register with the sector
address read from the selected disk drive during the

HEADER C major state. The comparator is a 7485 IC (see

Section 7 for truth table, pin locator, and logic diagram) that asserts SECTOR EQ H when the two 4-bit inputs are
equal.

11-80

SECTOR SEEKd) H

DSK SEC 8 L

DSK SEC 4 L

RK05
SECTOR
ADDRESS

.z^iE}

QSK SEC 2 L
I

'Z^iEi}
[DSK SEC

E47
COMPARATOR

SECTOR EQ H
-|

HEADER D

z:&-

—

(7485)

SECTOR ADDRS 8 H
SURFACE -SECTOR ADDRS 4 H
SECTOR
SECTOR ADDRS 2 H
REGISTER
SECTOR ADDRS 1 H
I

8E-0589

Figure 11-22

11.15.7

Sector Address Comparator

Data Break Control Logic

The data break control logic (Figure 11-23 and 11-24) enables the RK8-E to assume control of the CPU Major
Register gating and directly address via the Current Address Register,

memory locations associated with a data

transfer. The priority network compares the priority of the RK8-E with other peripherals making BRK RQST at the

same time. If the RK8-E has the highest priority, the controller asserts signals indicating the RK8-E has accepted the
request at INT STROBE time. When the RK8-E asserts BREAK, the single cycle data break is started, a data word is
transferred to or from the address indicated by the Current Address Register. If the transfer is from the RK05 to
memory, the data is applied to the Data Bus (DATA0-DATA1 1) by the transfer control logic. Data transfers from

memory to the RK05 are taken from the MD lines (MD00-MD1 1) and transferred to the RK05 via the Data Buffer
Register.

Current

11.15.7.1

Address

Current

Address

(Figure

11-23)

and

the

EMA

bits

(EMA0-EMA2) are used to select a location in memory to be used in a data transfer. The Current Address Register
is loaded with the address of the first memory location to be used in a data transfer when the 6RK4 (DLCA)
IDLE state (control not busy) when the CA
Register is loaded. DATA ENABLE (1) H (Figure 11-24) is asserted at TP4 time to increment the CA Register and
sequentially select locations in memory for data transfers. The contents of the CA Register are applied to the
OMNIBUS when MAK (1) H is asserted during a data break.
instruction

The CA

executed by the program. The RK8-E must be

DEC 74161

the

ICs (see Section 7 for timing diagram, logic diagram, and pin

DEC 74161 IC is a presetable binary counter with clock input for incrementing. Note that the clock
input and the control input (load) must be asserted to load the CA Register.
locations). The

The EMA bits (EMA0-EMA2) from bits 6 through 8 of the Command Register are applied to the OMNIBUS when
DATA ENAB (1) H is asserted by the control logic (Figure 11-24) to select a memory field (0-7). The EMA bits are
not incremented and the Command Register must be changed by the program to change memory fields.

11-81

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11-83

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11.15.7.2 Data Transfer Control Logic -The data transfer control logic (Figure 11-24) determines the direction
and type of data transfer. The BRK ENAB flip-flop is set immediately if a write operation is initiated or when the

Major States Register enters the DATA state during read operations. BRK ENAB (1) H supplies an input to E37 and

E46 to allow a BRK RQST if other conditions are met. BRK IN is set during read operations and cleared during
write operation to enable either E37 during read breaks or E46 during write breaks. During read operations, E37 is

enabled by DB C0NT4 (1)

H and BRK IN (1) H to assert READ BRK Land initiate a BRK RQSTatTPI time. DB
C0NT4 (1) H is asserted (high) when DB4 in the Data Buffer Register is full. A new BRK RQST is made each time
DB4 is filled until the data transfer is complete. BRK RQST is cleared during a read break when MAK (0) H is low if
DBS in Data Buffer Register is empty. Note that DB C0NT3 (1) H is low when DBS is empty which enables E28 and
allows BRK RQST to clear at TP4 time if the MAK flip-flop is set. If DBS is full, BRK RQST is not cleared and a
new break cycle is started to transfer new data. The data in DBS is transferred to DB4 as soon as DB4 is empty; thus,
the data in DBS is in DB4 when the next break cycle starts.

During write operations, E46 is enabled to assert WRT BRKLifBRKINis cleared, BRK EN is set, LAST BRK (0)

H is asserted, and DB1 in the Data Buffer Register is empty. DB C0NT1 (0) H is true to enable E46 and make a
BRK RQST at TP1 time when DB1 is empty. BRK RQST is cleared at TP4 time if MAK is set to negate MAK (0) H
(low) and DB2 is full. If DB2 is empty, DB C0NT2 (0) H disables E28 and the BRK RQST flip-flop is not cleared. If
DB2 is empty, the data in DB1 is transferred immediately to DB2 and a new break cycle is started to fill DB1 if the
RK8-E has the highest priority.
The data transfer control logic tries to keep the Data Buffer Register full during a write operation and empty during
a read operation via the single cycle data break.

11.15.7.3

Priority Logic

— The RK8-E must have the highest priority to allow a break cycle when a BRK RQST is

made. DISK PRIORITY H (Figure 1 1-24) is asserted by a ground (W1 installed) on the input of E42 if the RK8-E is
assigned the highest priority (0).

DATA

L (highest priority) or DATA 1 L are asserted by the output of E38 when

NBR flip-flop is set to prevent other peripherals from doing a break cycle when the RK8-E has priority. If
priority
is selected for the RK8-E, jumper W3 is installed. When a peripheral with priority
makes a BRK RQST,
E32 is enabled to supply a high to the input of E42. A high on E42 negates PRIORITY H and the RK8-E must wait

the

until

DATA

L is negated by the peripheral with the highest priority.

is asserted and a BRK RQST is made (NBR is set), a break cycle is started. NBR is
INT STROBE time if BRK RQST is set. When NBR sets, CPMA DISABLE L and BRK IN PROG L are asserted
on the OMNIBUS to start a break cycle. The OMNIBUS signals are explained in Chapter 10 of \he Small Computer
Handbook - 1973.

Thus, when DISK PRIORITY H

set at

11.15.7.4 CPU Control Logic - The CPU control signals are asserted by the RK8-E at TP4 time if DISK
PRIORITY H is asserted. DATA ENABLE is set at TP4 time to assert BRK CYCLE L and MSIR DISABLE L (see

Chapter 10 of the Small Computer Handbook - 1973 for description of signals). BRK DIR is set during read breaks

by BRK IN (1) H to assert MD DIR

L. MD DIR L is asserted to allow data to be transferred from memory to the
RK8-E (write) and is negated to transfer data from the RK8-E to memory.

The next TP1 pulse after DATA ENABLE is set causes the MAK flip-flop to set and assert MA, MS LOAD CONT L.
This inhibits loading of the MA, MS Registers by the processor and allows the contents of the CA Register applied to
the

MA lines to select a location in memory for this data transfer.

MAK

is set at the same time as DATA ENABLE. The clear side of MAK is used to clear BRK RQST at the end of a
BRK cycle if DB2 is full during write operations or DBS is empty during read operations.

The LAST BRK flip-flop is set and B LAST BRK H from the break counter is asserted when the data transfer is
completed. The zero side of LAST BRK disables E46 and removes WRITE BRK L from the BRK RQST flip-flop to
stop write breaks. READ BRK L is negated when E37 is disabled by the loss of DB C0NT4 (1) H to stop read
breaks.

11-84

The data break control logic Is cleared when the load disk address (DLAG) instruction is executed by the program
by CLR ALL L which is asserted when the DCLR instruction is executed.
11.15.8

Data Buffer Register and Control Logic

The Data Buffer Register (Figure 11-25) and its associated control logic (Figure 11-26) has the following functions:
During read operations, serial data is shifted into DB1 by the RD CLK pulses and transferred to DB4
DB2 and DBS as 12-bit parallel words. The 12-bit words are then transferred to memory by the single
Register empty
cycle data break. The single cycle data break control logic tries to keep the Data Buffer
via

so that there is space for temporary storage of data transferred from the disk.

12-bit word is

During write operations, a 12-bit parallel word is transferred from memory to DBl. The
BUFF SHFT L
transferred to DB4 via DB2 and DBS. The 12-bit word is shifted out of DB4 by the WRT
to
be written on
data
serial
bits
of
as
12
logic
control
write
the
to
supplied
is
DB4
signal. The output of
the disk between clock pulses (Figure 11-2).

During maintenance operations, the contents of CRC Register, Command Register, or the Surface/Sector
Register are shifted into DB4 by the LO MAIN SHFT L pulse. The DMAN instruction is used to generate
Data
the LO MAIN SHFT L signal (Table 1 1-14). The contents of DB4 are transferred to the AC via the

Bus by the DMAN instruction. Thus, the program can read and evaluate the contents of the Command
check
Register, CRC Register, and Surface/Sector Register during maintenance operations or error
11-14
Table
and
operations,
maintenance
routines. The flow diagram in Figure 11-15 illustrates these
gives the AC bit requirements to accomplish the maintenance operations.

11.115.8.1

Data Buffer Register Control Logic - The Data Buffer Register control

logic (Figure 11-26) provides

Control Register and a
control signals to the Data Buffer Register (Figure 1 1-25). The DB control logic consists of a
four J-K master slave
of
consists
Register
Control
The
DB clock with gating logic to aid in the control operations.
flip-flops with

clock inputs.

The unique features of

transition in the flip-flop if neither the J or

these flip-flops are:

a clock

pulse will

inputs are enabled during the clock pulse and 2)

inputs are enabled during the clock pulse, the flip-flop will

not cause any

both the J and K

complement (change states). The J or K inputs are

i.e., if DBl is in a 1
enabled only when the input is of a state different from the present condition of the flip-flop,

state only a

state input will cause the flip-flop to change state. When the flip-flops are in a

the flip-flops are in the

in a

state, the Data Buffer

state, DBl

is full.

When

state, the registers are considered to be empty.

The DB clock is made up of one 741 2S IC (see Volume I, Appendix A for logic diagram and pin locations). This
duration each time the input is enabled. The
is a dual one-shot multivibrator that outputs a pulse of a specified
IC

duration of the output pulse is determined by an external capacitor and resistor, i.e., R7 and CSS.

DB CLK H out of the first 74123 IC is a 50 ns pulse that is asserted when one of the inputs to E6 are enabled to
the Data Buffer
cause the input to make a high-to-low transition. One of the inputs to E6 is enabled when one of
disables the
and
2S
IC
741
second
Control flip-flops is to be loaded. The pulse out of the first 741 2S triggers the
input to the first IC, also disabling the

DB4 signal for 150 ns. This allows the completion of a data transfer

before a new DB CLK pulse is generated. Without this delay, the Control Register would attempt
-> DBS) or to the Data Bus (i.e.,
before the output of a register has been transferred into another register (i.e., DB2
exist to load one of the
conditions
correct
the
when
only
Data Bus). Note that the clock pulse is initiated
DB4
for a data transfer
time
allow
IC
to
second
the
of
side
clear
Data Buffer Registers and is disabled by the
to load a register

(re(]ister-to-ret)ister or register-to-disk or processor).

11-85

n
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o t
n n

^ t
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z s

s.
^

L_X _
^ sA----A
3:

it
CO

10
CVJ

11-86

RD SHIFT DB L

P/0 M7105

6RK7 OK HMAIN ENAB H-

E37

B DATA 5 H-

'^HIGH MAIN SHIFT L

HIGH MAIN data L

—

MAIN DATA H-

i
di
E49 p
\^
/data in(o)h J ^'^y

DATA IN H

EXT CYL ADDRS H
^ ^

B DATA 3 H

CRC 16(1)H

[

JP
^

ADDRS

^mC

l——dT

—^*—£9^ MAIN(1)h|E30JN
^

B DATA 2 H
)R

LO MAIN DATA H

B DATA 4 H

B DATA 3 H
B DATA 4 Ji)E47)o

AC7(0)H
B DATA

MAIN(1)H

E39
MAIN

6RK7 0K L

B DATA 2 L

MAIN ENAB H

6RK7 OK H

J E31)

LO MAIN SHIFT L
^^
fTTTX
E31 V
MAIN PL H
^^^^
E25
J

MAIN(0)H

CLR ALL L
8E-0599B

Figure 1 1-25

11.15.8.2
1

Data Buffer Register (sheet 2)

Data Buffer Control 1 and Data Buffer 1 - Data Buffer control 1 is used to control Data Buffer Register
DB CONTl is set to a 1 state when DBl is loaded and rennains in a 1 state until the

(Figures 11-25 and 11-26).

data

transferred to

loaded (DB CONTl goes to a 1 state) during write breaks by data from memory
is asserted by BRK DIR (0) H and DATA ENABLE (1) H (Figure 11-25). During read

DB2. DBl

when LD RD BUFFER H
operations, DBl is loaded with serial data so the input to DB CONTl is not clocked in until 12 bits are read from
the disk cartridge. When 12 bits are read and shifted into DBl by the read clock, 12th BIT OK H is asserted and DB

CONTl goes to a 1 state (DBl is full).
Note that during maintenance operations MAIN DATA can be shifted into DBl by the 6RK7 (DMAN) instruction if
bit 5 in the AC is a 1. This allows the program to check the Data Buffer Register and control logic.
Data Buffer Register 1 consists of three 7495A ICs (see Volume I, Appendix A for logic diagrams, pin locations, and
truth table) connected in series to form a 12-bit register. During read operations, this register is loaded with 12 bits
is a 12-bit parallel word that is transferred to DB2. DBl is
word from memory (write operations) that is transferred to DB2 when DB2 is

of serial data from the disk cartridge. The output of DBl
also loaded with a 12-bit parallel

empty.
11.15.8.3 Data Buffer Control 2 and Data Buffer Register 2 - DB C0NT2 is set to a 1 state when DB CONTl (1)
H (DBl full) and DB C0NT2 (0) H (DB2 empty) are asserted. The output of NAND gate E13 (1 ^ DB2) triggers the
74123 IC and generates a 50 ns clock pulse, which clocks 1 ^ DB2 H into DB C0NT2. Note that DBl is not
transferred to DB2 unless 1 -^ DB2 is asserted to cause a clock pulse to be generated. This stops a transfer from DBl
to DB2 unless DB2 is empty.

Data Buffer Register 2 consists of two 74174 ICs (see Volume I, Appendix A for logic diagram, truth table, and pin
locations) that are connected in series to form a 12-bit register. This register is parallel loaded with 12 bits from DBl

when DB C0NT2 is set to a 1 state. The parallel output of DB2 is transferred to DB3 when DB3 is empty.
11-87

I
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to -1
1

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01 m
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<£ 3
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11-88

11.15.8.4

loadejd

Data Buffer Control 3 and Data Buffer Register 3 - Operation of Data Buffer Control 3 and Data Buffer

is identical to DB2 CONT and DB2, except that DB3 H is qualified by DBS (0) and DB2 (1). D63 is
from DB2 when DB2 is full and DB3 is empty. The output of DB3 is transferred to DB4 when DB4 is empty

RegiiJter

(DB C0NT4 in a
11.15.8.5

state) and

DB3 is full (DBS in a 1 state).

Data Buffer Control 4 and Data Buffer Register 4- Data Buffer Control 4 (Figure 11-26) is used to

control Data Buffer Register 4 (Figure 11-25). DB4 is loaded with the contents of DBS if DB CONTS (1) H (DBS

and DB C0NT4 (0) H (DB4 empty) are negated to assert 1 ^ DB4 H. This causes DB CLK H to be asserted and
DB4 goes to the 1 state (full).

full)

During write operations, the contents of Data Buffer Register 4 are shifted out to the disk via the write logic (Figure
line as serial data. WRT BUFF SHFT L is generated by the WRT CLK pulses (Figure
and shifts the data once for each clock pulse. When 12 bits of data have been shifted out to the disk, E26 is

on the RK DATA11

11-28)
1 1-28),

enabled and DB4 ENAB H is negated. This clears DB4 to the

state and DB4 can be loaded again from DBS.

During read operations, DB4 receives a 12-bit parallel word from DBS for transfer to memory via the Data Bus.
When WRT BUFF ^ DATA H is asserted to transfer the contents of DB4 to the Data Bus (DATA0-DATA1 ), CLR
SYN (0) H is asserted to enable NAND gate ES4. Signal -> DB4 H is asserted if the TEST CLK H pulse out of the
^ DB4 returns DB C0NT4 to the state when the next DB CLK H pulse occurs. When
74123 IC is negated and
DB C0NT4 goes back to the state, it is ready for new data to be transferred from DBS.
1

Data Buffer Register 4 consists of 3 7495A ICs (see Volume I, Appendix A for truth table, logic diagram, and pin
locations) that are connected in series to form a 12-bit register. The register is loaded with 12 parallel bits from DBS

when DB4 is empty and DBS is full. During write operations, the 12 bits are shifted out to the disk as serial data.
During read operations, a 12-bit parallel word is transferred to memory via the Data Bus.
During maintenance operations, the contents of the Command Register, the CRC Register, and the Surface/Sector

DB4 of the Data Buffer Register, for transfer to the AC. To accomplish this, the MAIN
must be set by transferring a 1 from the AC in bit position 1 using the DMAN instruction. This enables the
maintenance logic (Figure 11-25) and allows bits from the AC to shift data into DB4. Signals MAIN PL H and B
Register may be shifted into

flip-flop

DATA 01 H are used to set DB C0NT4 (Figure

1-26) and keep it in the 1 state, which disables transfers from DBS

while maintenance operations are underway. An input to DB4 is supplied by NOR gate E9 and NAND gate ESO as

LO MAIN DATA H. When a DMAN instruction is executed by the program, the following events can occur:
a.

bit 3 in the AC is a 1 when the DMAN instruction is executed, bit 1 1 from the Command Register
(EXT CYL ADDRS H) is applied to DB4. Each time the DMAN instruction is executed by the program,
if bit 3 in the AC is set, a bit is shifted out of the Command Register and into DB4. When the contents
If

of the Command Register are in

DB4 (12 shifts), if the DMAN instruction is executed and bit 7 in the

AC is a 1 LO DB -» AC L is asserted to transfer the contents of DB4 to the AC via the Data Bus.
,

bit

2 in the AC is a

and the DMAN instruction is executed, the contents of the CRC Register are

DB4. This operation is the same as that listed above for the Command Register. Note that
the program must keep track of the number of shifts required to shift all of the bits into DB4. The CRC
Register is transferred to the AC with the same instruction and AC bit used for the Command Register.
shifted into

bit

4 in the AC is a

and the DMAN instruction

executed, the contents of the Sector/Surface

DB4. This shift and transfer operation is the same as the other maintenance

operations.

The MAIN flip-flop must be cleared using the DCLR instruction after maintenance operations are completed.

11-89

Output Data Multiplexer

11.15.9

The output data multiplexer (Figure 1 1-27) selects either the contents of the Status Register or DB4 to be applied to
I, Appendix A for truth table,
logic diagram and pin locations) that are controlled by the 6RK5 (DRST) instruction and enable RK DATA L. If LO

the Data Bus. The output data multiplexer consists of three 8235 ICs (see Volume

DB -> AC is asserted during maintenance operations or WRT BUFF DATA L is asserted during read operations, RK
DATA L through RK DATA 11 L from DB4 are applied to the Data Bus. If the 6RK5 (DRST) instruction is
executed by the program, the contents of the Status Register are applied to the Data Bus for transfer to the AC.

RK DATA
L
L
RK DATA
RK DATA 2 L
RK DATA 3 L
DONE FLAG (1) H
1

RDYS/R/W H
GND
SEEK FAIL H

6RK5 (DRST)-

RK DATA 4 L
RK DATA 5 L
RK DATA 6 L
RK DATA 7 L
DISK FILE RDY L
BUSY ERROR H
TIME OUT ERROR H
WRT LOCK ERROR H

— AC

E31

P/0 M7105
[7/

LO DB

DATA ENAB (1)H

WRT BUFF — DATA L

—

53>

BRK DIR (1)H— E37
I

TS2 H

[>-"'

RK DATA 8 L
RK DATA 9 L
RK DATA 10 L
RK DATA 11 L
CRC ERROR H
DATA RQST LATE H
DRIVE STATUS ER H
CYL ADDR ER H

ENABLE RK DATA L

Figure 11-27

11.15.10

Output Data Multiplexer

Read/Write Logic

The read/write (Figure 1 1-28) logic provides a clock for generation of clock and data pulses to be written on the disk
cartridge, the

11.15,10.1

READ DLY logic, and logic to separate RD CLK pulses and READ DATA.

Write Clock - The write clock is a 2.88 MHz crystal-controlled oscillator that generates the WRT CLK

pulses. When the WRITE flip-flop
is

set during

SK/CHK/WRT or SK/WRT operations, the output of the write clock

enabled to clock E41. The set side of the E41 flip-flop is tied to the data input so that E41

set and cleared on

NAND gate for WRT CLK pulses when E41 set and a NAND gate for WRT
DATA pulses when E41 is cleared. Thus, WRT CLK pulses and WRT DATA pulses are applied as an output to the
RK05 from NOR gate E27. Note that the data pulses occur between clock pulses and a bit cell (Figure 11-2), and are

alternate clock pulses. This enables a

written on the disk cartridge
state)

in this

manner. The CRC bits (CRC 16 (1) H) from the CRC Register (during CRC

and the SYNC bit (at end of write delay) are applied to E27 as data pulses to be written on the RK05 between

WRT CLK pulses.
During the DATA state, the WRT CLK pulses are used to generate WRT SHFT CRC H, which is used to compute the

CRC character (Paragraph

1 1 .1 5.1 1 ).

11-90

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i^oSm^

hl^

III

to—ff

V 9

Hi'

11-91

11.15.10.2

Read Delay - The

read operation for

READ DLY is a 74123 IC that delays the setting of the READ flip-flop, and the
85 /xs. This allows the controller to wait for the SYNC bit before the Major States Register

advances to the HEADER E major state.

The 74123 is a one-shot multivibrator that is triggered when SECTOR MK H makes a low to high transition and

READ DLY pulse. After 85 /is, the READ flip-flop is set; after the SYNC bit is read, a read
operation is started. The set side of READ is applied to the RK05 as DSK READ L to cause the RK05 to read data.
outputs of 85 /us

The clear side of READ enables gates to allow RD CLK H and READ DATA IN L pulses to be applied to the RK8-E
Data Buffer Register and control logic.
11.15.11

ORG Register

The CRC Register (Figure 11-29) is used to store the disk address and compute a CRC character during read and
write operations. The CRC character is computed during write operations and written on the disk cartridge at the
end of the data. During read operations, a CRC character is computed and compared with the CRC character that
was written at the end of the data. If the two CRC characters are not equal, the CRC ERROR flag is set.
11.15.11.1

Disk Address -The CRC Register (Figure 11-29)

loaded with the 8-bit disk address when the DLDC

LD DISK ADDRS H. The two 7496 ICs receive 7 bits
(DATA0-DATA6) from the AC and one bit from Bit 11 (EXT CYL ADDRS H) of the Command Register. The disk
address bits are applied to the RK05 Disk Drive during the STROBE major state (Figure 11-31) to select a cylinder
instruction

executed by the program to assert

and surface on the selected disk drive.

The CRC Register stores the disk address until the Major States Register enters the DATA state. At this time, the
CRC Register is cleared by DATA STATE (0) H, which is negated (low). The CRC Register is also cleared by the
6RK3 (DCLR) instruction if it is executed by the program.
Note that the Load Disk Address instruction loads the Surface/Sector Register (Figure 11-29) at the same time the

CRC Register is loaded.
During the HEADER C major state, the HEADER word is read from the selected drive as DATA IN H and applied to
Exclusive-OR gate E24 (Figure 11-29). RD CLK 1 L asserts SHFT CRC H and shifts the contents of the CRC
Register out to E24. Thus, the contents of the CRC Register (specified disk address) and the
word read
from the disk are compared bit-by-bit. If any bits are different, NOT EQUAL is set by the output of the

HEADER

Exclusive-OR (E24) and the CYLINDER ADDRESS ERROR flag is set (Figure 11-21).

The CRC Register contains the disk address specified by the program until the Major States Register moves to the

DATA state. If CYLINDER ADDRESS ERROR

set, the

TRANSFER DONE flag sets and the drive that produced

the error must be recalibrated.

The disk address may be transferred to the AC for evaluation by the program using the DMAN instruction. When the
disk address is transferred, the contents of the CRC Register are shifted out on CRC 16 (1) H to DB4 of the Data
Buffer Register (Figure 11-25). Signal MAIN PL is asserted each time the
instruction is executed by the

DMAN

program to shift the CRC Register one position and transfer one bit of the CRC Register to DB4. Note that AC bit

02 must be a 1 to enable the MAIN PL and assert CRC MAIN SHFT L. The program must keep track of the number
of shifts and determine when to transfer DB4 to the AC.

Note that when the control is in any state except the DATA state, the Exclusive-OR gates for CRC 2 and CRC 15
have a ground on one input. The ground causes these gates to have an output that is the same as the input, which
allows the contents of the CRC Register to be shifted and compared with the CRC DATA H input.

11-92

005

III

Ml'

—^

<
<

X
*
<
<

3
CO

oc
CO

O
oc
o
Cf)

11-93

The Exclusive-OR gates for CRC 2 and CRC 15 are used in the computation of the CRC character (Paragraph
11.15.11.2).

11.15.11.2

CRC Character Computation - To generate a CRC word, the block of data

bits long which

(modulo 2)

divided (modulo 2) by a polynominal X^ ^ + X^ ^ + X^ + 1

accomplished by shifting the

treated as a number 3072

This division being shift and subtract

CRC Register and Exclusively ORing CRC 2, CRC 15, and CRC 16

(Figure 11-30) as follows:

The CRC Register is cleared at the beginning of the DATA state.

The CRC Register is shifted one bit position each time a bit is read or written by WRT CLK L or RD

DLK

The

bit,

which

read or written,

compared with CRC 16 (Exclusively ORed) and the result is

Exclusively ORed with CRC 2 and CRC 15.

Using this method, a CRC character is generated for each block of data (256 words) that is written on or read from
tape.

aJH

3CH3-t3D^
SERIAL DATA

8E-0585
Figure 11-30

CRC Computation Block Diagram

ORG 4 H

DRIVE OL

DSK CYL ADDR 128 L

DISK DRIVE

CRC 5 H

DRIVE 1 L-

DSK CYL ADDR 64 L

DISK DRIVE 1 L

CRC 6 H

DRIVE 2 L

DSK CYL ADDR 32 L

DISK DRIVE 2 L

CRC 7 H

DRIVE 3 L

DSK CYL ADDR 16 L

DISK DRIVE 3 L

CRC 8 H

DSK CYL ADDR 8 L

CRC 9 H
DSK CYL ADDR 4 L
CRC 10 H
DISK CYL ADDR 2 L

CRC 11 H
STROBE H

DISK CYL ADDR

P/0 M7105

Figure 1 1-31

Disk Address Output Buffers

11-94

CRC Character Check - The ORG character that is computed for each block of data during a write
operation is written on the disk cartridge after the data during the CRC state. This is accomplished by shifting the
contents of the CRC Register out to the disk drive via the read/write logic (Figure 11-28). During the CRC state, the
WRT CLK pulse is used to shift the contents of the CRC Register.
11.115.11.3

During read operations, a CRC is computed as explained above and when the control moves to the CRC major state,
the CRC character written on the disk is read. DATA IN H is enabled by CRC STATE H (Figure 11-29) and applied
to EE24 Exclusive-OR gate. As the CRC character is read from the disk the CRC Register is shifted by RD CLK 1

and a bit-by-bit comparison is made of the two CRC characters.

any of the

EQUAL

bits are different

set, the

the output of the Exclusive-OR (E24) sets the

NOT EQUAL flip-flop. If NOT

CRC ERROR flag sets during the END state (Figure 11-21).

The CRC character can be checked by the program using the OMAN instruction the same way the disk address was
checked (Paragraph 11.15.11.1).
Major States

11.15.12

The operation of the Major States Register (Figure 11-32) and the determination of the disk format is discussed in
Paragraph 1 1.14.7. The detailed logic is shown so that the reader can see all the signals required to enter each major
state.

RK8-E Counters

11.15.13

The RKB-E counters (Figure 11-33) are used to count the bits and words in a data transfer and keep track of the
number of data break cycles.
11.15.13.1

12-Bit Counter -The 12-bit counter (Figure 11-33) consists of 74161 IC (see Section 7 for truth table,

timing diagram, and pin locations) used as a binary counter. The 12-bit counter is incremented by

RD CLK 2 L

CARRY H is
12TH CARRY H increments the word counter
each time 12 bits are read or written until 256 or 128 words have been transferred. If HALF BLOCK H is asserted,
(read) or

WRT CLK L each time a bit

read or written. When 12 bits have been read or written, 12TH

asserted to indicate a 12-bit word has been read or written. Signal

12th BIT OK H is negated after 128 words are read or written.

During maintenance operations, HI MAIN SHFT L is asserted if the program executes the DM AN instruction and AC
This allows the program to check the counters and control logic.
1

bits 2, 3, or 4 are

The counters are cleared by CLR ALL L or CLR CNTRS L. Signal DATA CLR L is asserted each time the Major
States Register advances to the DATA state by a pulse out of the 74123 IC. The 74123 IC (see Volume I, Appendix

A for truth table, logic diagram, and pin locations) is a one-shot multivibrator that outputs a pulse each time the
DATA state flip-flop sets. The counters are also cleared each time the Major States Register enters the HEADER E
asserted when the Major States Register enters the CRC or HEADER C
major state or when STATE ENAB B H
is

major state.

Word Counter - The word counter (Figure 11-33) consists of two 74161 ICs (see Section 7 for truth
table, timing diagram, and pin locations) that are used as divide by 128 or 256 counters. The word counter is
incremented by 12TH CARRY L each time 12 bits of data are read or written. LAST WORD H is asserted after 256
11.15.13.2

words have been read or written. Signal 128TH WORD H is asserted after 128 words are read or written, and if
HALF BLOCK H is asserted (bit 5 in the Command Register must be a 1), the data transfer stops after 128 words.
Note that the disk drive continues to read or write zeroes until 256 words are read or written, but this data is not
memory. The TRANSFER DONE flag is not set until LAST WORD H is asserted after 256 words are

transferred to

read or written.

11-95

X
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< X^

5::

Q — C)
Z Q
^
-0

z
<
Q

<^ <a- o
ir)|_H^

Sg^?
Q
1..
-III

O
w
:>:

o
Q
tt

11-96

^^ ^-^
^^ —

LJ
h- rr
<t IT)
00 1fft

O
*s
d.

<o
(
,

11-97

55x
cam

ZLd

S to
S CI L_
O IE 03

IT)

OtiJ —

n~r

93-

TT~r
1

ill,

c
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00

<z
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CO

TT~r
CCLU _

zd *

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11-98

*5
mtj

11.15.13.3

16-Bit Counter -The

16-bit counter consists of a

74161

IC (see Section 7 for truth table, logic

diagram, and pin location) that is used as a binary counter. The 16-bit counter counts the bits in a HEADER word or

CRC character as they are read or written. The 16-bit counter is incremented by RD CLK 2 or the WRT CLK, which
asserts INC CNTRS H. After 16 bits are read or written, 16TH BIT H is asserted and applied to the control logic.

During maintenance operations, the

16-bit

counter

incremented by HI

MAIN SHFT L when the DM AN

instruction is executed by the program. This allows the program to check the 16-bit counter and associated logic.

11.15.13.4

Break Counter - The break counter (Figure 1 1-33) consists of two 74161 ICs (see Section 7 for truth

table, logic diagram,

and pin locations) that are used as a binary counter. The word counter is incremented at TP2

time of a break cycle (DATA ENABLE is set) to count the number of single cycle data breaks. B LAST BRK H is

256 words have been transferred to or from memory. If HALF BLOCK H is asserted (bit 5 in the
Command Register must be a 1), data transfers stop after 128 words have been transferred. Signal B LAST BRK H
sets the LAST BRK flip-flop (Figure 1 1-27) and stops data transfer operations.
asserted after

SECTION 5 MAINTENANCE

11.16

PREVENTIVE MAINTENANCE

The recommended preventive maintenance should be scheduled on a regular basis to maintain the performance and
reliability of the RK8-E and the RK05 Disk Drive system. Preventive maintenance schedules are found in the RK05
Disk Drive l\/laintenance l\/lanual (DEC-00-RK05-DA). RK8-E diagnostics (Paragraph 11.5.1) are provided to test and
troubleshoot the RK8-E controller. These diagnostics should be run at regular intervals to verify the operation of the
RK8-E.

11.17

CORRECTIVE MAINTENANCE

The following programs may be loaded into memory from the Switch Register and used to monitor RK8-E signals
during troubleshooting operations.

NOTE
The program to check the data buffers in Paragraph 11.17.1
should be run first.

11-99

11.17.1

Check Data Buffers

This program provides a scope loop to check the Data Buffers by shifting 12 bits of data (Is or Os) from AGIO into

DB1. When DB1 is full, a parallel transfer is made from DB1 to DB2, DB2 to DBS, DB3 to DB4. When DB4 is full, it
is read into the AC with the maintenance lOT and stored in memory.
1.

Clear disk control logic

Enable maintenance logic

Enable shift to data buffer 1

Set ACl

Issue maintenance lOT 12 times

Read data buffer 4

to equal data

Example:

Mnemonic

Operation

Location

Contents

7600

7301

CLACLLIAC

7601

6742
1230

DCLR
TAD -12
DCA COUNT

7602
7603
7604
7605
7606
7607
7610
7611

7612
7613
7614
7615
7616
7617
7620
7621

3231

7330
6747
7012
7012
7012
1232
6747
2231

5212
7200
1233
6747
3234
7402

CMLRAR
DMAN
RTR
RTR
RTR

ENABLE CLEAR CONTROL (AC10=0 ACl
/ lOT 6742 CLEAR CONTROL
/

DESIRED SHIFT COUNT
SET UP COUNTER

ENABLE MAINTENANCE MODE (AC00=1)
/ lOT 6747 MAINTENANCE lOT

/
/

DMAN
ISZ COUNT

ENABLE CHECK DATA BUFFER (AC05=1)
GET DATA TO BE SHIFTED INTO DB1
/ lOT 6747 MAINTENANCE lOT
/ SHIFTED ONE WORD YET?

JMP-2
CLA

TAD K20

TAD AC 10 DATA

DMAN
DCABUFREG
JMP START

/
/

NO, SHIFT ANOTHER BIT.
YES, CLEAR AC

ENABLE DB4 TO AC TRANSFER (AC07=1)
lOT 6747 MAINTENANCE lOT
/ STORE DATA WORD
/ (DEPOSIT A HLT TO MAKE ONE PASS)
/

-12

7630/ 7766

COUNT
ACl DATA

7631 /

K20

7632/ 0000 OR 0002
7633 / 0020

BUF REG

7634/

11-100

= 1)

11.117.2

Checking the Command Register

The following program is used to check the Command Register. The data is obtamed from the Switch Register and
loaded into the

Command Register. It is then shifted into the lower Data Buffer, and read into memory using'

maintenance lOT instructions.

Clear disk control logic

Load Command Register with data from the Switch Register

Enable maintenance logic

Enable shift to lower buffer

Set AC03 (check Command Register)

Issue maintenance lOT 12 times

Read DB4

Example:

Mnemonic

.ocation

Contents

7600

7301

CLACLLIAC

7601

6742
1230

DCLR
TAD-12
DCA COUNT
OSR
DLDC

7602
7603
7604
7606
7606
7607
7610
7611

7612
7613
7614
7615
7616
7617
7620
7621

7622

3231

7404
6746
7330
6747
7010
6747
7012
6747
2231

5213
7200
1232
6747
3233
5200

Operation

ENABLE CLEAR CONTROL (AC10=0 AC1 = 1)
lOT 6742 CLEAR CONTROL
1

DESIRED SHIFT COUNT
SET-UP COUNTER

OR THE SWITCH REGISTER
lOT 6746 LOAD COMMAND REGISTER
ENABLE MAINTENANCE MODE (AC00=1)
lOT 6747 MAINTENANCE lOT
ENABLE SHIFT TO LOWER BUFFER DB4 (AC01 = i;
lOT 6747 MAINTENANCE lOT
ENABLE CHECK COMMAND REGISTER
lOT 6747 MAINTENANCE lOT
SHIFTED ONE WORD YET?
NO, SHIFT ANOTHER BIT
YES, CLEAR AC
ENABLE DB4 TO AC TRANSFER AC07=1
lOT 6747 MAINTENANCE lOT
STORE WORD
LOOP OR HALT (HALT=1 PASS)

CLACLLCML RAR
OMAN
RAR

OMAN
RTR

OMAN
ISZ COUNT
JMP-2
CLA

TAD K20
DMAN

DCACMD REG
JMP START
-12

7630/ 7766

COUNT

7631 /

K20

7632/ 0020
7633/

CMD REG

11-101

11.17.3

Check Surface and Sector Register

This program is used to scope the Surface/Sector Register and Data Buffer 4. The data to be used is entered into the

Console Switch Register (switches 5-11) then loaded into the Surface/Sector Register. It is then shifted into the
lower Data Buffer (DB4 bits 5—11) where it is read into the AC and stored in memory.

Clear disk control logic

Enable maintenance logic

Load Surface/Sector Register with data from switches

Enable shift to lower Data Buffer

Enable shift Surface/Sector Register (AC04=1

Issue maintenance lOT 1 2 times

Read DB4

Example:
.ocation

Mnemonic

Contents

7000

7301

CLACLLIAC

7001

6742
1230

DCLR
TAD-12
DCA COUNT

7002
7003
7004
7005
7006
7007
7010
7011

7012
7013

7014
7015
7016
7017
7020
7021

7022
7023

3231

Operation

ENABLE CLEAR CONTROL (AC10=0 AC1 1=1)
lOT 6742 CLEAR CONTROL
/DESIRED SHIFT COUNT
/

CLA,CLL,CML,RAR

OMAN

6747

DMAN
ISZ COUNT

2231

5214
7200
1232
6747
3233
5200

LAS

DLAG
CLA,CLL,CML,RTR

OMAN
RTR

RAR

SET UP SHI FT COUNTER

ENABLE MAINTENANCE MODE (AC00=1)
lOT 6747 MAINTENANCE lOT
/ LOAD THE AC FROM THE SWITCH REGISTER
/ lOT 6743 LOAD DISK ADDRESS
/ENABLE SHIFT TO LOWER BUFFER (AC01=1)
/ lOT 6747 MAINTENANCE lOT
/ ROTATE AC AND LINK RIGHT TWO PLACES
/ ENABLE CHECK SURFACE AND SECTOR REGISTER

7330
6747
7604
6743
7332
6747
7012
7010

/{AC04=1)
/ lOT 6747 MAINTENANCE lOT

CLA
TAD K20

SHIFTED ONE WORD YET?
/NO, SHIFT ANOTHER BIT
/YES, CLEAR THE AC
/ ENABLE DB4 TO AC TRANSFER (AC07=1)

DMAN

JMP -2

DCA SS REG
JMP START

lOT 6747 MAINTENANCE lOT
/STORE WORD
/ LOOP OR HALT (HLT=1 PASS)

-12

7030 / 7766

COUNT

7031 /

K20

7032 / 0020

SS REG

7033/

11-102

.17.4

Check CRC Register
is used to scope the CRC Register logic. AC bit 10, CRC Register, and Data Buffer Register 4 are
connected in series. A data bit is shifted 28 times through this series register to allow the last 12 bits to be

This program
logically

read from DB4.

Clear disk control logic

Enable maintenance mode

Enable shift to lower buffer (DB4)

Load maintenance data into AGIO

Check CRC Register (AC02=1

Issue maintenance lOT 28 times

Read DB4

Shift 12 more data bits in

Read DB4

10.

Jump back to step 8

Example:

Mnemonic

Location

Contents

7000

7301

CLA,CLL,IAC

7001

6742
1230

DCLR

/ lOT 6742

7002
7003
7004

3231

TAD -28
DCA COUNT

7330

LOOP-CLA,CLL,

Operation

ENABLE CLEAR CONTROL (AC10=0 AC1 1-1
CLEAR CONTROL
/DESIRED SHIFT COUNT
/SET UP COUNT
/

ENABLE MAINTENANCE MODE (ACOO-1)

CML,RAR
7005
7006
7007
7010
7011

7012
7013
7014
7015
7016
7017
7020
7021

7022
7023

6747
7010
6747
7010
1232
6747
2231

5212
7200
1233
3231
1234

6747
3235
5204

OMAN
RAR

DMAN
RAR
TAD AC10 DATA
DMAN
ISZ COUNT
JMP-2
CLA

TAD -12
DCA COUNT
TADK20
DMAN
DCA CRC
JMP LOOP

MAINTENANCE lOT
/ENABLE SHIFT TO LOWER DATA BUFFER (AC01=1
/ lOT 6747 MAINTENANCE lOT
/ ENABLE CHECK CRC REGISTER
/ LOAD DATA BIT INTO AC10
/ lOT 6747 MAINTENANCE lOT
/SHIFTED ONE 12 BIT WORD YET?
/ lOT 6747

NO, SHIFT ANOTHER BIT
/YES, CLEAR THE AC
/DESIRED SHIFT COUNT
/SET UP COUNT
/

ENABLE DB4 TO AC TRANSFER (AC07=1
MAINTENANCE lOT
/STORE WORD
/ LOOP OR HALT (HALT=1 PASS)
/

/ lOT 6747

-28

7030 /7744

COUNT
AC10DATA

7031 /

-12

K20

CRC

7032 / 0000 OR 0002
7033 /7766
7034 /0020
7035 /

11-103

Single Cycle Data Break Transfers (Read Operation)

11.17,5

This program transfers data from the
logic,

RK05 to processor memory. It can be used to scope the data break control

Data Buffers, Current Address Register, Command Register, and the logic involved in read operation.

Clear control logic

Enable maintenance mode

Load AC from the Switch Register

Load Command Register

Enable shift to lower buffer

Set AC03 to 1 (check Command Register)

Issue maintenance lOT 12 times

Current address = 0000

Set AC06 to 1 (check data break request)

10.

Issue maintenance lOT

Example:

Mnemonic

Location

Contents

7600

7301

CLA,CLL,IAC

7601

6742
1230

DCLR
TAD -12
DCA COUNT

7602
7603
7604
7605
7606
7607
7610
7611

7612
7613
7614
7615
7616
7617
7620
7621

7622
7623
7624

3231

7604
6746
7330
6747
7010
6747
7012
6747
2000

LAS

DLDC

CLACLLCML RAR
OMAN
RAR

OMAN
RTR

OMAN
ISZ COUNT
JMP-2

7326
7006
7006
6747
7000
7000
7402

CLACLLCML RTL
RTL
RTL

OMAN
NOP
NOP
JMP START

Operation

ENABLE CLEAR CONTROL (AC10=0 AC1 = 1)
lOT 6742 CLEAR CONTROL
/ LOAD DESIRED SHIFT COUNT
/SET UP SHIFT COUNTER
/ TRANSFER SWITCH REGISTER CONTENTS TO THE AC
/STORE DATA IN LOCATION 0000
/ ENABLE MAINTENANCE MODE (AC0=1)
/ lOT 6747 MAINTENTANCE lOT
/ENABLE SHIFT TO LOWER DATA BUFFER (AC01 = 1)
/ lOT 6747 MAINTENANCE lOT
/ENABLE SHI FT TO COMMAND REGISTER (AC03=1)
/ lOT 6747 MAINTENANCE lOT
/SHIFT ONE WORD YET?
/NO, SHIFT ONE MORE BIT
/ ENABLE MAINTENANCE MODE
/ ENABLE DB4 TO AC TRANSFER
/

lOT 6747 MAINTENANCE lOT
/NO OPERATION
/NO OPERATION
/ (DEPOSIT A HALT TO MAKE ONE PASS)
/

11-104

11.17.6

Single Cycle Data Break Transfers (Write Operation)

This program transfers data from processor

memory to the Data Buffer. It Is used to scope the write operation

control logic. Current Address Register, Command Register, and the data break control logic.

Clear control logic

Enable maintenance logic

Set Command Register to write function

Load the AC from the Switch Register

Store data in location 0000 of memory

Enable break request bit

Issue maintenance lOT

Read DB4

Example:
Location

Mnemonic

Contents

7600

7301

CLA,CLL,IAC

7601

6742
7330
6746
7604
3000
7330
6747
7012
7012
7012
6747
7000
7000
7200
1225
6747
3226
7402

DCLR

7602
7603
7604
7605
7606
7607
7610
7611

7612
7613
7614
7615
7616
7617
7620
7621

7622

CLA,CLL,CML,RAR

DLDC
LAS

DCAO
CLA,CLL,CML,RAR

DMAN
RTR
RTR
RTR

DMAN
NOP
NOP
CLA

TAD K20
DMAN
DCA DATA
JUMP START

Operation

ENABLE CLEAR CONTROL (AC10=0 AC1 1=1)
lOT 6742 CLEAR CONTROL
/ ENABLE MAINTENANCE MODE (AC0=1)
/ lOT 6746 LOAD COMMAND REGISTER
/ LOAD AC FROM SWITCH REGISTER
/ LOAD AC INTO LOCATION 0000
/ ENABLE MAINTENANCE MODE (AC0=1)
/ lOT 6747 MAINTENANCE lOT
/ENABLE THE
/MAINTENANCE DATA
/ BREAK REQUEST (AC06=1)
/ lOT 6747 MAINTENANCE lOT
/NO OPERATION
/NO OPERATION
/CLEAR AC
/ ENABLE DB4 TO AC TRANSFER (AC07=1)
/ lOT 6747 MAINTENANCE lOT
/STORE DATA
/ (DEPOSIT A HALT TO MAKE ONE PASS)
/

11-105

11.17.7

Single Cycle Data Break Transfers (Write then Read)

This program transfers data in the Switch Register to DB1 of the RK8-E, then reads the data bacl< into memory after
it

has transferred into DB4. The transfers are effected by causing one break request while the Command Register has

a write command in

it,

then causing another break request with a read in the Command Register. Finally, check to

see if the word read equals the word written.

Clear control logic

Load Command Register with a write function

Load memory location 0000 with data from the Switch Register

Enable maintenance logic

Initiate one single cycle data break request

Load Command Register with a read function

Initiate one single cycle data break request

Check data read with data from Switch Register

Example:

Mnemonic

Operation

Location

Contents

7600

7301

CLACLLIAC

7601

DCLR

/ lOT 6742

7621

6742
7330
6747
6746
7604
3000
7326
7006
7006
6747
7000
7000
7200
6746
7326
7006
7006

7622
7623
7624
7625

6747
7000
7000
5200

7602
7603
7604
7605
7606
7607
7610
7611

7612
7613
7614
7615
7616
7617
7620

NOP
NOP
CLA
DLDC

ENABLE CLEAR DISK CONTROL LOGIC
CLEAR CONTROL
/ ENABLE MAINTENANCE MODE AC00=1
/ lOT 6747 MAINTENANCE lOT
/ lOT 6746 LOAD COMMAND REGISTER (WRITE)
/ LOAD AC FROM SWITCH REGISTER
/STORE WRITE DATA
/ENABLE THE
/MAINTENANCE DATA
/BREAK REQUEST AC06=1
/ lOT 6747 MAINTENANCE lOT
/NO OPERATION
/NO OPERATION
/CLEAR AC
/ lOT 6746 LOAD COMMAND (READ)

CLACLLCML RTL

CLACLLCMLRAR
DMAN
DLDC
LAS

DCAO
CLACLLCML RTL
RTL
RTL

DMAN

JMP START

ROTATE AC AND LINK LEFT TWO
ENABLE MAINTENANCE DATA BREAK
/ REQUEST (AC06=1)
/ lOT 6747 MAINTENANCE lOT
/NO OPERATION
/NO OPERATION
/ (HALT=1 TIME) (NOP=CHECK DATA)

CLACLL
TADO

/CLEAR AC AND LINK
/ LOAD AC WITH WRITE DATA

RTL
RTL

DMAN
NOP
NOP

/
/

CHECK DATA
7626
7627

7300
1000

11-106

.ocation

Contents

7630
7631

7040
3003

7632
7633
7634
7635
7636

0003
7440
7402
5200

1001

Mnemonic

CMA
DCA 0003
TAD 0001
AND 0003
SZA
HLT
JMP START

Operation

/COMPLEMENT WRITE DATA
/STORE DATA FROM AC IN MEMORY
/ LOAD AC WITH READ DATA
/ COMPARE READ AND WRITE DATA
/ SKIP ON ZERO AC (GOOD DATA)
/HALT
/JUMP TO START

11-107

SECTION 6 SPARE PARTS
Table 11-16 lists recommended spare parts for the RK8-E, These parts can be obtained from any local DEC office,
or from DEC, Maynard.

Table 11-16

RK8-E Spare Parts

DEC Part No.
11-00114
19-05542
19-05575
19-05576
19-05579
19-05585
19-05587
19-09004
19-09055
19-09056
19-09057
19-09061
19-09062
19-09267
19-09485
19-09486
19-09594
19-09615
19-09667
19-09686
19-09704
19-09705
19-09931
19-09935
19-10011
19-10018
19-10091
19-10155
19-10224
19-10363
19-10406
19-10436
19-10645
19-10650
19-10652
19-10656
18-10694

Description

Diode, D664

DEC IC, 7474
DEC IC ,7400
DEC IC ,7410
DEC IC ,7440
DEC IC ,7476
DEC IC ,7473
DEC IC ,7402
DEC IC ,7495
DEC IC 74H00
DECIC 74H10
DEC IC 74H52
DEC IC 74H53
DEC IC 74H11
DEC IC 380
DECIC 384
DEC IC 8251 B
DECIC 8271
DEC IC 74H74
DECIC 7404
DEC IC 314
DEC IC 8881
DEC IC 74H04
DEC IC 8235
DEC IC 7486
DEC IC 74193
DECIC 7437
DECIC 7408
DECIC 7485
DEC IC 7496
DEC IC 75451
DEC IC 74123
DECIC 75452
DEC IC, 74161
DEC IC 74174
DEC IC, 74155
DEC Crystal Oscillator

Quantity

2
2

11-108

SECTION?

IC DESCRIPTIONS

DEC 74155 IC

11.18

The 74155 IC (Figure 11-34) is TTL circuit used as a 2-line to 4-line decoder (unit select decoder) and as a S-line to
8-line decoder (function decoder) in the RK8-E. This IC may also be used as a Mine to 8- or 4-line multiplexer, but
it is not used this way in the RK8-E and will not be discussed here.

When the 74155 IC is used as a 2-line to 4-line decoder, as with the unit select decoder, the 1Y0 through 1Y3
outputs are selected by applying +3V to pin 1 and leaving pin 2 low. The inputs in this configuration are applied to
pins 3 and 13 and the outputs (low) are taken from pins 4, 5, 6, and 7.
In the 3-line to 8-line configuration, as in the function decoder, external

connections are installed to tie pin 1 to pin

15 and pin 2 to pin 14 (Figure 11-34). This allows both the 2Y and 1Y outputs to be used and provides for three
three
inputs instead of two. In this configuration, the 74155 IC becomes a BCD to decimal decoder, which decodes
binary bits (Paragraph 11.15.3.1).

DEC 74193 IC

11.19

The DEC 74193 (Figure 11-35) monolithic circuit is a synchronous, reversible (up/down), 4-bit binary counter
having a complexity of 55 equivalent gates. Synchronous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincidentally with each other when so instructed by the steering logic.
This

mode of operation eliminates the output counting spikes which are normally associated with asynchronous

(ripple-clock) counters. Figure 11 -35 contains the logic diagram and pin locations.

The outputs of the four master/slave flip-flops are triggered by a low-to-high level transition of either count (clock)
high.
input. The direction of counting is determined by which count input is pulsed while the other count input is

The counter is fully programmable, i.e., the outputs may be preset to any state by entering the desired data at the
data inputs while the load input is low. The output will change to agree with the data inputs, independently of the
count pulses. This feature allows the counters to be used as Modulo-N Dividers by simply modifying the count
length with the preset inputs.
applied. The
A CLEAR input has been provided which forces all outputs to the low level when a high level
on
the CLEAR,
placed
been
buffer
has
input
An
inputs.
and
load
the
count
of
independent
CLEAR function is
when the
important
This
load.
normalized
one
to
requirements
drive
lower
the
LOAD
inputs
to
COUNT, and
is

output of the driving circuitry is somewhat limited.

and CARRY
This counter was designed to be cascaded without the need for external circuitry. Both
output produces a pulse
outputs are available to cascade both the up- and down-counting functions. The

BORROW
BORROW
equal in width to the COUNT DOWN input when the counter underflows. Similarly, the CARRY output produces a
pulse equal in width to the COUNT UP input when an overflow condition exists. The counters can then be easily
cascaded by feeding the BORROW and CARRY outputs to the COUNT DOWN and COUNT UP inputs, respectively,
of the succeeding counter.

NOTE
Voltage values are with respect to network ground terminal.

11.20

DEC 7485

The DEC 7485 IC performs magnitude comparison of straight binary and straight BCD codes. Three fully decoded
for
decisions about two 4-bit words (A and B) are made and are externally available at three outputs. The delay time
a 4-bit comparison is 12 ns. Figure 11-36 shows the truth table, pin locator, and logic diagram.

11-109

OUTPUT

STROBE

1Y0

DATA

.OUTPUT

1Y1

SELECT

4>-H>

UTPUT
1Y3

.OUTPUT

SELECT

2Y0

<—|>J-^

OUTPUT

PUT PUT
2Y2

DATA
2C

SELECT
STROBE INPUT
2G
A
^Y3

OUTPUTS
.„

iW
^

2Y2

2Y1

-i

2Y3

2Y2

2Y1

2Y0

26 2C
B B A A

1Y3

1Y2

1Y1

1Y0

1Y1

1Y0.'

DATA STROBESELECT 1Y3
1C
1G
INPUT ^
•

B B A A

1G1C

1Y2
'-'

GND

OUTPUTS

Pin assignments for these circuits are ttiesame for all packages.

8E-0605

Figure 11-34

DEC 74155 IC Illustration (sheet 1)

11-110

^^^ ^^"^

—cX"^^

r
g-|0

?—

UJ
00

?—

8
CO
9
CD

-\
<

UJ
en

OQ
1

z
o
o
q:
u
o
o

iij

1
1

o
<

+->

CD
0)

r
—

^
"-^^

r/
>—
E — "0

i-f^

o
lU

—

f-\

'*
CO

z
o
UJ
1

u.
.

t
lij

—

Q
Q
<

z
z
8
UJ

Q
o
UJ
o
UJ
z
1

•<

j^
f

o <
'^£

rt-

o
UJ

in
in

) <«
(A)
UJ
rf

</>

§^

"
e
oq: 1

L
L._

^
en

1—

rl-

11-111

CM
_l

<
3
O

3
iZ

BORROW
OUTPUT

DATA
INPUT A

DATA
INPUT

CARRY
OUTPUT

OUTPUT Q,

OUTPUT Qb

-O

OUTPUT Qc

OUTPUT Qd

PRESET

DOWN
COUNT

UP
COUNT

_^
~^

CLEAR

_y o

1
PRESET

CLEAR

Trry

cy-

DATA
INPUT C

1
PRESET
Qc

OT
^C

u
CLEAR

cy--

DATA
INPUT D

CLEAR O-

PRESET
Qd

i>
LOAD O

O
Figure 11-35

74193 IC Illustration (sheet 1)

11-112

Qd
CLEAR

CLEAR

LOAD

DATA

_r
_r
COUNT
UP

COUNT

UrUTLrLTLJ

DOWN

OUTPUTS -<
°c

zzi

~3l

CARRY

BORROW

|0|

SEQUENCE
ILLUSTRATED

|.3|

CLEAR

— COUNT UP
PRESET

NOTE:
A. Clear overrides load data, and count Inputs.
B. Wtien counting up, count-down input must be high; when counting down, count-up input must be

Figure 11-35

74193 IC Illustration (sheet 2)

11-113

COUNT DOWN

higti.

o
LO

mi-

')< =

O
LU
Q
CD
CO

Q
Q

6
6

11-114

The 7485 IC is used to compare the desired 4-bit sector address with a 4-bit sector address read from the disl<
cartridge in the RK8-E. This application asserts the A-B output when the two 4-bit addresses are equal.
11.21

DEC 74161 IC

is a presetable high-speed binary counter. Synchronous operation is provided by
so that the outputs change coincident with each other when so
simultaneously
clocked
having
instructed by the count enable inputs and internal gating. This mode of operation eliminates output counting spikes

The DEC 74161
all

IC (Figure 11-37)

flip-flops

normally associated with ripple clock counters. A buffered clock input triggers the four master-slave flip-flops on the
edge of the clock input. To preset of load the counter register, the clock input and the enable

rising (positive-going)

must be asserted. The removal of enable allows the counter to be incremented by the clock input.
In the

RK8-E, these ICs are cascaded to provide a 12-bit Current Address Register that is preset to an address in

memory and incremented during the single cycle data break to select sequential memory locations.

11-115

n^i>

_^^r^C>-

^^^^>

O
INPUTS <

O
{>

Pin(16) = Vcc,Pin(8)-GND

(11)

—

F^O"

ENABLE
T

(TOP VIEW)^
CARRY r

Od enable

CLOCK

ABC

ENABLE
D

HiHiKiKiKiKiHiHiH
CLEAR CLOCK ^A

ENABLE 6ND

DATA INPUTS
positive logic: See discriptlon

Figure 11-37

DEC 74161 IC Illustration (sheet 1)

11-116

RIPPLE

CARRY

)>-OUTPUTS

CLEAR
LOAD

DATA INPUTS -<

CLOCK

CLOCK
enable: P

ENABLE T

OUTPUTS <
Qr

CARRY
12

-COUNT-

INHIBIT-

CLEAR PRESET
The following sequence is illustrated
1.

Cleor outputs to zero

2. Preset to binary 12
3.

Count to 13,14,15,0,1, and 2

4. Inhibit

8E-0603

Figure 11-37

DEC74161 IC Illustration (sheet 2)

11-117

CHAPTER 12
VT8-E HIGH SPEED VIDEO DISPLAY

TERMINAL AND CONTROL

SECTION 1

INTRODUCTION

The VT8-E, a video display option for the PDP-8/E, PDP-8/F, and PDP-8/M, consists of a video terminal and three
the
quad modules that plug into the OMNIBUS. The quad modules control the terminal operation and can interface
options
display
VT8-E
four
to
Printer.
Up
Line
Centronics
VT8-E to either an LA30A-P DECwriter or an LS01-E
can be used simultaneously with the same computer.
and a
The display terminal comprises a CRT with its associated power supply, deflection circuits, video circuits,
12-1).
(Figure
enclosure
desk-top
in
a
contained
is
monitor
The
logic.
keyboard with its control
Data

transferred

from the terminal keyboard to the computer AC Register by program interrupts. Data to be

VT8-E OMNIBUS control
displayed by the monitor is transferred from memory by single cycle data breaks to the
that
is displayed on the viewing
information
video
serial
to
data
parallel
the
convert
modules
control
The
modules.
alone or in combination.
screen. The monitor can display both alphanumeric characters and graphic symbols, either

>'scmiHuampmijmim^.
in,

vsSmi- i

::l,,-

-maeissmsi'iisrmmm'':

milium^: rn'mmmiiOMSr-smmmaM

i'mmaimw.MsmivmmM
'iymmmtimm-mimumM
'S'ttmmimamiPmmiimtM
-inmmfmmimpmnmti'f:^

••'maemmmmmmiPi'-

•>'t«K?SHrji:i«N»»srij««|t.

'****««'«»««*«»

Figure 12-1

VT8-E Display Monitor

12-1

Neither the LA30A-P nor the LS01-E Line Printers is discussed here. Details concerning these two printers
should be
obtained from the respective maintenance manuals. Publications and documents relevant to the VT8-E are:

12.1

PDP-8/E, PDP-8/F, and PDP-8/M Small Computer Handbook - DEC, 1973

PDP-8/E, PDP-8/F, and PDP-8/M Maintenance Manual, Volume 1

VT8-E Diagnostic; MAINDEC-08-DHVTB-A (Graphic), MAINDEC-08-DHVTA-A (Alphanumeric)

DEC Engineering Drawings, E-CS-M8335-0-1, E-CS-M8336-0-1, and E-CS-M8337-0-1 (interface modules)

DEC Engineering Drawing, D-CS-54099 17-0-1 (DEC keyboard #2)

DEC Engineering Drawings, D-CS-30 10326-1-0 (Motorola Raster Display)

SYSTEM OPERATING SPECIFICATIONS
Operating Temperature Range

5° to 43°C

Operating Humidity Range

10% to 90% (Relative)

(without condensation)

Power Requirements

100-130 Vac, 50 or 60 Hz

(display monitor)

±5% single phase at 2
200-260 Vac, 50 or 60 Hz
±5% single phase at 1A

Power Consumption
(display monitor)

12.1.1

55Wat115V
65W at 230V

CRT Operating Specifications (Motorola Raster Display)
Screen Size

10-1/8 in. X 7-5/8 in.

Phosphor

P4 (white)

Deflection Type

Magnetic

Deflection Method

Raster Scan

Input Impedance

75fi ± 5%

(at

VIDEO IN input)

Video Input Signal

0.9 to 2.2V with separate horizontal and vertical SYNC.

Video Pulse Rise and Fall Time

40 ns (10% to 90% point), measured at cathode with 1.0V
p-p input and 30V p-p output.

Video Output Amplitude

30V p-p (minimum), measured at cathode with 1.0V p-p input.

Resolution

Screen Center - 600 lines (minimum)

Screen Corners - 400 lines (minimum) (using shrinking raster

method)

12-2

Horizontal Sweep Frequency

15.6 kHz

Vertical Sweep Frequency

50 or 60 Hz (selectable)

Horizontal Retrace

11 ius (maximum)

Vertical Retrace

21 horizontal lines @ 15.6 kHz

High Voltage

kV (minimum) @ 50 /xA beam current @ 24 Vdc power

supply adjustment

12.1.2

High Voltage Regulation

12 ivrn (maximum), for a beam current change from 50 to
150 mA @ 24 Vdc power supply adjustment.

CRT Refresh Rate

50 or 60 Hz

Visible Display Specifications

12.1.2.1

Screen Refresh Rate

60 or 50 frames/sec (determined
by local line frequency)

Refresh Method

Raster Scan

Alphanumeric Mode
Viewing Area

8-1/4 in. (horiz) X 6-1/4 in. (vert)

(32 characters/line)
8-1/4 in. X 4-1/4 in. (64 characters/line)

Character Lines

Character Size

0.185 in. width

(32 characters/line)

0.220 in. height
0.090 in. width

(64 characters/line)

0.150 in. height
Character Spacing

Horizontal

0.0740 in. (32 characters/line)
0.0370 in. (64 characters/line)

Vertical

0.0946 in. (32 characters/line)
0.0645 in. (64 characters/line)

Character Set

64-character ASCII set

(upper case)

Character Generation Method

12.1.2.2

5X7 dot matrix

Graphic Mode

Viewing Area

7 in. X 6-1/4 in. (if wired for 32

alphanumeric characters per line)

12-3

Viewing Area (Cont)

7 in. X 4-1/2 in.

(if wired

for 64

alphanumeric characters per line)
Display Lines

200

Flicl<er-Free Points per Line

189

SECTION 2 INSTALLATION AND ACCEPTANCE TEST
The VT8-E Video Display and Control are installed on site by DEC
not attempt to unpack, inspect, install, checkout, or service

12.2

Field Service personnel.

The customer should

the equipment.

UNPACKING

The VT8-E Display Monitor is packed in a specially designed carton

to avoid damage during shipment.

NOTE
Carefully examine the

VT8-E for damage as It is unpacked.

Any damage should be reported immediately.
Unpack the VT8-E Display Monitor as follows:
Step

12.2.1

Procedure

Remove the Display Monitor from the shipping container.

Remove the polyethylene cover.

Remove any tape, etc., from the display monitor cabinet.

Remove the display monitor from the shipping skid.

Place the display monitor in the desired location.

Verify all items listed on the Inventory List shipped with
the VT8-E have been received.

Primary Power

The Display Monitor uses a single ac power cable (permanently
connected) to connect the site power source to the
display monitor. The monitor operates at 110-130
Vac, 50-60 Hz, single phase, or 200-260 Vac 50-60 Hz sinale
'
phase.
'

Each wire

the ac power cable is color-coded as shown

Table 12-1. The display monitor is normally supplied

15A connector. The selected ac service outlet must be capable of at least
2A, 110 Vac 50 or 60 Hz or 1A
200 Vac, 50 or 60 Hz.
with a

•

Table 12-1

AC Power Cable
Line

Terminal Strip

Nomenclature

Frame Ground

Neutral/Line 2

Neutral or Line 2

Line 1

12-4

•

12.2.2

VT8-E Installation

Install the VT8-E as follows:

Procedure

Step

Ensure PDP-8/E power is off.
Ensure the Display Monitor Power Select switch, located on the side of the Display
Monitor, is set correctly for the power source (115 Vac or 230 Vac).

Use

meter to measure the voltages on the wall receptacle and ensure that the hot,

neutral,

and ground connections are the same as those on the Display Monitor power

connector (Table 12-1).

On the M8336 and M8337, ensure the 5 jumpers are installed to select only 64 or 32
characters per line. All jumpers must be installed for the same mode.

On the M8335 module ensure the correct device code jumpers are installed. Table 12-2
contains a list of the split lugs which should be connected in each of the 6 groups (A— F)
to select one of the 64 possible device codes. Split lug locations (by groups) are shown on

D-CS-M8335-0-1- Engineering Drawing cover sheet.
6

On the M8337 and M8335 modules, ensure the jumpers are installed correctly to select
the priority assigned to this VT8-E (Table 12-3). Only priorities 9 (highest), 10, and 11
(lowest)

may be assigned to the VT8-E. Refer to M8337-0-1 and M8335-0-1 cover sheet

for jumper locations.

Connect J1 of the 7009042 Cable Assembly to Jl on the M8336 module.

Connect J2 of the 7009042 Cable Assembly to Jl on the M8335 module.

If a line

printer is used, connect the printer cable assembly to J2 on the M8335 module.

the VT8-E modules on the OMNIBUS as shown in Figure 12-2. Refer to Figure 2-3
Volume 1 for recommended module installation priorities. The VT8-E is not a memory
option. The VT8-E modules must be installed in this order;
Install

M8336
M8337
M8335
11

Install

Front
Middle
Rear

H851 Top Connectors as follows (Figure 12-2):

Between M8336H and M8337H

Between M8337E and M8335E

Between M8337F and M8335F

Route the 7009042 Cable Assembly to the Display Monitor and connect J3 Winchester
Connector to the mating corinector on the rear of the console.

12-5

If a

line printer is used, route the printer cable to the line printer and connect it.

NOTE
more than one VT8-E is installed in one system (up to four may
be installed in one system), the second control goes on the
If

OMNIBUS directly behind the first, and the third behind the second,
The two controls are interconnected by installing an H851 Top
Connector between M8335J of the first control and M8336J of the
etc.

second control. The controls must be assigned different device codes
(Tables 12-2 and 12-3).

Turn on PDP-8/E power and run the acceptance test in Paragraph 12.2.4.

Table 12-2
Device Code Select Jumper Installation

Group A

Group B

2-3

2-1

2-3

Device

Group C

Group D

Group E

2-3

2-1

2-3

2-1

Group F

Code

02
03
04
05
06
07

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

22
23
24
25
26
27
30

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

32
33
34
35
36

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

12-6

Table 12-2 (Cont)
Device Code Select Jumper Installation
Device

Group A

Group B

Group C

Group D

Group E

Group F

Code
37

2-1

2-3

2-1

2-3

42
43
44
45
46
47

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

53
54
55
56

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3
2-3

2-3

62
63
64
65
66

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

72
73
74
75
76
77

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

2-1

2-3

Table 12-3
Priority Jumper Installation

Priority

9 (highest)
10
11 (lowest)

M8337 Install

M8335 Install

Jumper

Jumpers

P9 and PIO

W2
W3

P9' and PIO'

12-7

P9'and PIO

M8336

M8337

M8336

OPERATORS
CONSOLE

VT8-E No. 2

VT-8E No,1

Figure 12-2

VT8-E Module Installation

Acceptance Test

12.2.3

The VT8-E is checked for proper operation by running the two diagnostic programs. Both MAINDECs referenced in
their
the introductory remarks and the A-SP-VT8-E engineering specification give detailed instructions for
performance

the

instructions

shipped with the paper tapes.

problems

arise,

refer to the

maintenance

instructions, both in this manual and in Volume 1.

SECTION 3 OPERATION AND PROGRAMMING
This section provides a functional description of the VTB-E logic, operation and programming information, a list of

lOT instructions, and some VTB-E programming examples.
12.3

FUNCTIONAL DESCRIPTION

The functional groups of logic in the VT8-E are described in the following paragraphs (Figure 12-3). Their purpose,
location (on what module), and function are provided to familiarize the reader with VT8-E operation. A detailed
description of VT8-E logic and timing is given in Chapter 4. Refer to Chapter 9 of the Small Computer

Handbook - DEC, 1973 for information about data transfers via lOT instructions and data breaks. A detailed block
diagram of the VT8-E showing data flow and the interrelationship of the functional groups is in the VT8-E Video
Display Control Engineering Drawings.

12.3.1

VTB-E Printer/Keyboard Control Module (M8335)

The functional groups of logic on the M8335 module are discussed in the following paragraphs.

MD Bus Gating -Data from the MD lines applied to the MB335 module by I/O PAUSE
instructions are executed by the program or by MD EN during single cycle data breaks. Single cycle data break

12.3.1.1

method used to transfer data between memory and the display control (Paragraph 12.3.4.1).

12-B

lOT

if
is

the

/^^

VT8-E PRINTER/KEYBOARD CONTROL (M8335)
(1) KEYBOARD AND PRINTER lOT DECODERS (2)
(2)MD BUS GATING
(3) DATA BUS GATING
(4) KEYBOARD BUFFER
(5) KEYBOARD FLAG
(6)1/0 TRANSFER CONTROL
(7)INTERRUPT AND SKIP LOGIC
(8) STARTING ADDRESS REGISTER AND COUNTER
(9) EXTENDED ADDRESS REGISTER AND COUNTER
(10) PRINTER BUFFER
(11) PRINTER FLAG
(12) HIGHER PRIORITY DETECTION

C0,C1
DATA 0- DATA 11

MD3-MD11

DATA (ASCI

KEYBOARD

CODE)

48 KEY
(ASCI CODE]

BUF MEM DATA

XADR CNTR
ADR CNTR
DATA

CODE)

PRINTER

LA30A-P
OR
LS01E

INT REQ

SKIP

.MAO- MA1

EMA0-EMA2
VT8-E LINE BUFFER (M8337)
(1) LINE BUFFER A AND B
(2) ASCII DECODING
(3) VIDEO

ROM

CONTROL

4) GRAPHIC
(5)

VIDEO BUFFER

CHARACTER BLANK DETECT

{6)E0S,BBF, AND EBF DETECT
(7) BLINK, CURSOR, BRIGHT, OR NORMAL DETECT
(8) DATA BREAK CONTROL
(9)

CONTROL
VIDEO

BREAK COUNTERS

(10)MA AND EMA BUS GATING
(ll)DATA BUS GATING
(12)

MAINTENANCE ENABLE

BRK RQST, MA, MS LOAD CONT MS.IR DISABLED, MP DIR.CPMA DIS.BRK IN PROG
(PROCESSOR CONTROL SIGNALS)

CONTROL

MD9-MD11

FREQUENCY DIVIDER BOARD (M8336)
(1) DISPLAY lOT DECODER
(2) CLOCK AND FREQUENCY DIVIDER
(3) 64 OR 32 CHARACTER SELECTION
(4) ALPHANUMERIC TIMING CONTROL
(5)GRAPHIC TIMING CONTROL
(6)CHARACTER COUNTER
7) LINE COUNTER
(8

ROW COUNTER

GRAPHIC

COMPOSITE VIDEO
(SYNC AND VIDEO)

OR
ALPHANUMERIC
DISPLAY

(9) VIDEO CONTROL
(lO)HORIZONTAL SYNC PULSE SHAPER
(11) VERTICAL SYNC PULSE SHAPER
(12)VIDE0 AND SYNC COMBINING CIRCUITS
(13 VIDEO ENABLE CONTROL
(14) REAL TIME CLOCK FLAG

Figure 12-3

12.3.1.2

VT8-E Block Diagram

lOT Decoders -The IVI8335 module contains two lOT decoders, one for the printer and one for the

keyboard. The decoders are assigned different device codes so that the printer lOT decoder is selected when printer

lOTs are programmed, and the keyboard lOT decoder

selected

when keyboard lOTs are programmed. The

keyboard and printer may be assigned any two of the device codes listed in Table 12-2. The device codes assigned to
the keyboard and printer must be different from each other and different from the display device code. The lOT
decoders decode

MD9— MD11 from the MD lines and generate control signals to control keyboard and printer

operations; i.e., data transfers. The keyboard and printer instructions are listed in Paragraph 12.3.4.

12.3.1.3

Data Bus Gating - The Data Bus gates are enabled and DATA0-DATA1 1 are applied to the M8335 logic

when the following occur:
a.

If the

program executes the PNPC or PNLP instructions to load the Printer Buffer.

the program executes a DPLA instruction to load the Starting Address Register or a DPGO instruction

to load the Extended Starting Address Register.

During a single cycle data break, DATA

- DATA 8, 9, or 10 monitored by the VT8-E during data

breaks to determine if the VT8-E has the highest priority for a data break.

12-9

Keyboard Buffer — The Keyboard Buffer receives a 7-bit ASCII code from the keyboard when one of the

12.3.1.4

is pressed. The keyboard also generates a KEYBOARD STROBE which enables the 7-bit
ASCII code to be transferred to the buffer and sets the KYBD flag. When the KYBD flag is set, an INT RQST is

keys on the keyboard

nnade if interrupts are enabled, or a SKIP if the DKSF instruction is executed by the program. An INT RQST or
SKIP notifies the program that data in the Keyboard Buffer is available to be read into the AC. The program must
transfer the data in the buffer to the AC and clear the KYBD flag so that a new 7-bit ASCII character can be
transferred from the keyboard to the buffer.

I/O Transfer Control - The I/O transfer control logic determines the direction of data flow on the Data
Bus and whether the AC is cleared or not. CO and CI (the C lines) are asserted by lOT instructions which transfer

12.3.1.5

data to or from the AC.
Interrupt and Skip Logic — The interrupt and skip logic allows the program to enable the interrupts and

12.3.1.6

generate an

INT RQST when the

KYBD and PRINT DONE flags are set or to check the flags using a SKIP

instruction, i.e., the DKSF instruction.

Interrupt Logic — The keyboard and printer interrupt logic is enabled

12.3.1.7

bit 11

the AC is set (1) when

DKIN instruction is executed by the program. If the interrupts are enabled, an INT RQST is made when the
KYBD flag is set or the PRINT DONE flag is set. The KYBD flag is set when a keyboard key is pressed, and the
PRINT DONE is set when the printer has finished printing a character.

the

Starting Address Register and Counter

12.3.1.8
that

(SAR) -The Starting Address Register (SAR) is a 12-bit register

loaded from the AC with the memory address of the first word to be transferred by the single cycle data

break facility. The contents of SAR are transferred to the address counter after the DPGO instruction is executed by
the program and the counter
address.

incremented at the end of each data break to select the next sequential memory

The contents of the counter are applied to the Memory Address lines (MAO-MA1 1) to address a location in

memory.
12.3.1.9
6, 7,

Extended Starting Address Register - The Extended Starting Address Register (XSAR) is loaded from bits

and 8 of the AC by the DPGO instruction. The contents of XSAR are transferred to the XADR COUNTER and

in memory for data transfers. The XADR COUNTER
incremented when the ADR
COUNTER overflows to select the next memory field. At this time the ADR COUNTER starts reading memory

used to select a field

locations in the newly selected memory field.

Buffer - The

Printer Buffer is a 7-bit register that
loaded from the AC by the PNLP
AC contains a 7-bit ASCII code for a character to be printed. The seven data bits are
transferred along with a PRINT STROBE pulse, and when the Print operation is completed, the PRINT DONE flag
set. If interrupts are enabled, an INT RQST is made at this time, or if the flag is checked by the PNSK instruction,

12.3.1.10

Printer

instruction. The data from the

the SKIP line is grounded. The program may perform a routine to transfer another character to the printer at this
time.

12.3.1.11 PRINT DONE Flag - The PRINT DONE flag is set each time the printer completes a print operation to
inform the program that the printer is ready to accept a new character.

12.3.1.12
the

Higher Priority Detection —The higher priority detection logic monitors the Data Bus to determine if

VT8-E has the highest priority for a data break. If there are any peripherals connected to the OMNIBUS that

have a higher priority that the VT8-E, one of the lines on the Data Bus will be low to prevent the VT8-E from doing
a data break.

asserted (low)

As an example, if the peripheral assigned the highest priority wants to do a data break, DATA
is
and the VT8-E cannot do a data break until DATA
goes high at the completion of the other

peripheral's data break. When the VT8-E is ready to do a data break, DATA 9 or DATA 10 will be asserted low to
prevent peripherals with a lower priority from doing a data break before the VT8-E. As previously discussed, the

VT8-E may be assigned one of the three lowest priorities.

12-10

VT8-E Line Buffer Module (M8337)

12.3.2

The functional groups of logic located on the VT8-E Line Buffer Module are discussed in the following paragraphs.

12.3.2.1

Line Buffers A and B — Line Buffers A and B provide temporary storage of 32 or 64 words from memory

in the Graphic mode. In the Alphanumeric mode the word
from memory (Figure 12-7) selects the visible field, display mode, and character to be displayed. In the Graphic
mode, the word from memory (16 words per line) consists of Is (display a dot) and Os (do not display a dot) to
produce a line on the face of the CRT. The display mode (Alphanumeric or Graphic) is selected by bit 10 (0 ->
ALPHA and 1 -^ GRAPHIC) from the AC when the DPGO instruction is executed by the program.

the Alphanumeric mode or 32 words from memory

Each alphanumeric character is displayed on the face of the CRT in a 5 (width) X 7 (height) dot matrix. To display

one row of characters (32 or 64 characters), the Display Monitor makes 10 horizontal sweeps across the face of the

CRT. The first two scans are used to load the Line Buffers from memory via the Single Cycle Data Break. The third
ROM location and the remaining seven scans display the alphanumeric data. The first of the
seven scans displays the first line of each character in the row of characters to be displayed, the second scan the

scan addresses a blank

second line, etc., until seven scans are completed to display a row of characters (32 or 64). When the tenth scan is
completed, the program must set up for a new break and initiate a new break cycle to reload the Line Buffers if
additional rows of characters (20 maximum) are to be displayed. During the display operation the 7-bit ASCII code

decoded by the ASCII decoding ROMS to generate the video signals to be displayed and the four
A display may be stopped after any number
of characters have been displayed, if the display is less than 20 rows, to save computer time. This is done by setting
(Figure 12-7)

control bits are decoded to determine the display mode and visible field.

CB1 and CB2 to Is when the last character is displayed.
In the

Graphic mode, data is displayed on the face of the CRT in a 189 (width) X 200 (height) dot matrix. Each line

(189 dots) requires 16 12-bit words. The last three bits of the sixteenth word are not used. Each bit of the data word
leaves a space. As an
represents a dot or space on the face of the CRT. A logical 1 causes a dot and a logical
Is displays a row of dots on the face of the CRT. In the Graphic mode,
3200 (200 X 16) words must be defined because there is no way to generate End-of-Screen (EOS). If the full screen

example, 16 words of data containing all

not used, the remainder of the memory locations used should contain all Os.

12.3.2.2

ASCII Decoding ROMs - The ASCII decoding ROMs decode the 7-bit ASCII code from the Line Buffers

and generate a video signal for each line of each character to be displayed. After the start of a horizontal scan, data is
shifted out of the Line Buffers to address (the buffer is in a recirculating mode, thus an end-around shift) a ROM
character generator location and generate video for one line of the character.

addressed seven times (once for each horizontal scan).

ROM character generator locations are

The video signals generated each time it is addressed are

changed by the assertion of signals inside the ROM to change the video pattern and produce the desired character
after seven scans. The video out of ROM (VIDE01-VIDE05) is applied to the Alphanumeric Video Buffer where it
Is

shifted out to the Video Control logic as five serial video pulses. These pulses will cause dots or spaces to appear

on the face of the CRT and after seven scans, an alphanumeric character is formed.
12.3.2.3

Graphic Video Buffer - In the Graphic mode, the contents of the Line Buffer are transferred one word at
Video Buffer. From the Graphic Video Buffer the 12-bit word is converted to serial video

a time to the Graphic

pulses and applied to the Video Control logic. Dots are displayed for data Is and spaces for data Os.

12.3.2.4

Character Display Mode Detection Logic — The Character Display mode is determined by CB3 and CB4
word from memory. As shown in Figure 12-7, the character may be displayed in the

(Figure 12-7) of the data

Normal, Blink, Bold, or Cursor modes. The Mode Detection logic decodes CB3 and CB4 to assert the control signals
necessary to select the four modes.

12.3.2.5

Visible Field Detection Logic

word. As shown

- The visible field is determined by CB1 and CB2 (Figure 12-7) of the data

Figure 12-7, the character may be displayed in the mode selected by CB1 and CB2 (NOP), a

12-11

blank field may be ended and the display enabled (EBL), a blank field may be started (BBF) or an End of Screen

(EOS) may be selected to end the display.

EOS is particularly helpful because it allows smaller displays to be

displayed without using the entire core buffer. This saves core buffer space and reduces processor loading.
Single Cycle Data Break Control Logic — The single cycle data break control logic is used to force the

12.3.2.6

processor into the Direct Memory Access (DMA) state and transfer data between core memory and the VT8-E Line
Buffers via the Memory Data lines.

Memory is addressed by the outputs of address and extended address counters,

which are applied to the Memory Address lines at the beginning of the break cycle.
Processor Control Signals — When the processor is forced into the

12.3.2.7

DMA state, the VT8-E must generate

control signals to control the processor. The control signals required to accomplish this are shown in Figure 12-3 and

explained in Chapter 9 of the Small Computer Handbook — DEC, 1973,

Break Counters — The break counters are used to count the words

12.3.2.8

overflow after 32 words are transferred

the 32 character

mode

or after

in a

data transfer.

The counters
in the 64

64 words are transferred

character mode to stop data transfers and release the processor.

MA and EMA Bus Gates — The MA and EMA bus gates apply the contents of the address counter and

12.3.2.9

extended address counter to the OMNIBUS MA lines during a data transfer. This allows the selection of a memory
field and memory location to be used in a data transfer.

12.3.2.10

Data Bus Gates — The Data Bus gates are enabled when the

DPMD instruction is executed by the

program to transfer data to the Data Bus. This allows VT8-E registers and buffers to be read into the AC for display
or evaluation by the program. To read the Display Buffers and Register with lOT instructions the Maintenance logic

must be enabled.

12.3.2.11

Maintenance Enable — The maintenance logic

enabled by the

DPSM

instruction. This allows the

program to read the VT8-E registers and buffers using the maintenance instructions. It also allows data breaks to be
taken by the VT8-E at a rate determined by the program.
12.3.2.12

Frequency Divider Board (M8336) — The functional groups of logic on the M8336 module are discussed

in the following paragraphs.

lOT Decoder — The display lOT decoder decodes the display instructions and generates the
to set up for data breaks, maintenance operations, and data transfers using lOT
instructions. The decoder is enabled when I/O PAUSE is asserted and the device code assigned to the display for this
VT8-E is decoded and decodes bits MD9— MD11 of the lOT instruction. At this time, the C lines are asserted to
12.3.2.13

Display

necessary

control

signals

control the direction of the data transfer,

INTERNAL I/O is asserted to prevent the processor from performing

other lOTs, and the instruction is executed by the VT8-E.
12.3.3

VT8-E Clock and Frequency Divider (M8336)

The VT8-E clock and frequency divider generates the necessary CRT sync pulses and control signals required to
display data on the CRT. The timing chain consists of a 21.84 MHz crystal controlled oscillator and a chain of
divide-by counters with selected outputs used to generate sync and control signals. Jumpers are provided to allow

the selection of 64- or 32-character display control signals. These jumpers allow control signals of different
frequencies to be selected for the display of 32 or 64 characters per row. The counters in the timing chain and their

function are discussed in detail in Paragraph 12.4.2.2.
12.3.3.1

Real

Time Clock

Flag — The Real

Time Clock flag

set (1) at the start of each vertical retrace.

interrupts are enabled, an interrupt request is made, or if a Skip instruction

SKIP bus is grounded and the program will skip an instruction.

12-12

being executed by the program, the

Video and Sync Combining Circuits - The Video and Sync Connbining circuits combine the horizontal
and vertical sync with the video pulses from the ROM Character Generator to produce a composite video signal.
12.3.3.2

12.3.4

lOT Instructions

The following instructions are used to program the VT8-E.
12.3.4.1

Display Instructions - The display instructions assume device code 05

used. There are

64 possible

printer
device codes which can be used (Table 12-2) for the display. The device code for the display, keyboard, and
must be different (e.g., device code 03 for the keyboard, 04 for the printer, and 05 for the display). If more than

one VT8-E

installed in the

same system, three new device codes must be selected for the second VT8-E. They

must also be different from each other and different from the device codes assigned to other PDP-8/E options
installed in the system.

Load Starting Address Register (DPLA)
Octal Code:

6050

Operation:

Transfer the contents of the AC to the Starting Address Register (SAR) and clear the AC. The AC
must contain the address of the first memory location to be used in a data transfer. The contents of

the SAR are transferred to the address counters and then incremented at the end of each single cycle
data break. This allows the sequential selection of locations in memory for data transfers.

Load Extended Starting Address (DPGO)
Octal Code:

Operation:

6051
Transfer the contents of AC10 and AC11 to the mode select logic, and AC6-AC8 to the Extended
Starting Address Register (XSAR). AC10 and AC11 are used to select alphanumeric or graphic mode

and enable or disable the interrupt system as follows:

ACID

AC11

Alphanumeric Mode, Interrupt Disabled
Alphanumeric Mode, Interrupt Enabled

Graphic Mode, Interrupt Disabled
Graphic Mode, Interrupt Enabled

1
1

AC6-AC8 must contain the memory field to be used in a data transfer. The XADR COUNTER is
incremented when the ADR COUNTER overflows at the end of each memory field to select the next
memory field. The ADR COUNTER selects the first location (0000) in the new memory field. Data
transfers may start immediately after this instruction is executed.

STOP the Display (DPSi\/l)
Octal Code:

6052

Operation:

Stop the display and inhibit video and VT8-E initiated data breaks. This instruction also transfers
AC1 1 and AC6-AC8 from the AC to the maintenance logic and the Extended Starting Address
AC6-AC8. If
Register. If AC11 is 1, the Extended Address Register is loaded with the contents of
counters and
address
to
the
transferred
are
AC11 is 0, the contents of the Starting Address Register

AC6-AC8

the VT8-E is set up for a maintenance break. The AC must contain the memory field in
to determine which operations are to be done before this instruction
and AC11 must be 1 or

executed.

12-13

Maintenance Instruction (DPI\/IB)
Octal Code:

Operation:

6053

memory location specified by the Address Counter to the Data Buffer.

Transfer the contents of the

The Address Counter is incremented by 1 to select the next location in memory.
l\/laintenance Instruction (DPMD)

Octal Code:

6054

Operation:

Jam-transfer the contents of the Data Buffer to the AC. Note that the DPMB and DPMS may be used
to transfer data from memory to the Data Buffer and then to the AC where it is displayed. This could
aid in troubleshooting the VT8-E.

Maintenance Instruction (DPMS)
Octal Code:

6055

Operation:

Transfer the contents of the Extended Address Counter to AC6-AC8 and the state of the SENSE
switch into ACO (Figure 12-4). This allows the program to determine what memory field is selected

and determine the condition of the SENSE switch. Bit
and

when

logical

is a logical 1 when the SENSE switch is on
SENSE switch is off. This switch is located on the keyboard and the

the

programmer determines its use and meaning.

MSB

LSB

MSB

SENSE
£ WITCH

LSB
C DNTENT S

NOT
USED

0=OFF

Figure 12-4

EXTEN DED ^—

NOT
USED

ADDRE SS REG ISTER
(MEM ORY Fl ELD)

Extended Address and Sense Switch Data

Skip On Real Time Clock Flag (DPCL)
Octal Code:

6056

Operation:

Skip the next instruction if the Real Time Clock flag is set (1
is

)

and clear the flag. Real Time Clock flag

set at the start of each vertical retrace.

Generate A Bell Tone (DPBL)
Octal Code:

6057

Operation:

Generate a half-second audible tone for use as a bell. This tone can be heard by the operator and can
be used to alert the operator that he must respond; i.e., supply data to the program via the keyboard.

12.3.4.2

Keyboard Instructions - The keyboard instructions assume a device code of 03 has been selected for the

keyboard.

12-14

Clear Keyboard Flag (DKCF)

Octal Code:

Operation:

6030
Clear the Keyboard flag. The Keyboard flag Is set when the Keyboard transmitter is ready to transfer
data, usually after one of the keyboard keys has been pressed.

Skip on Keyboard Flag (DKSF)
Octal Code:

6031

Operation:

Skip the next sequential instruction if Keyboard flag is set. Keyboard flag sets when one of the
keyboard keys has been pressed to supply data to the program.

Clear Keyboard Flag and

AC (DKCC)

Octal Code:

6032

Operation:

Clear the Keyboard flag and the AC.

Logically

OR Keyboard Buffer and the AC (DKOB)

Octal Code:

Operation:

6034
Logically

the

contents

the

Keyboard Buffer with AC5-AC11, deposit the

result

AC5-AC1 1, and transfer a 1 to AC4. AC0-AC03 remain unchanged. When DKOB is combined with
the CLA instruction, the contents of the Keyboard Buffer are transferred to AC5-AC1 1.
Enable Keyboard Printer Interrupt (DKIN)
Octal Code:

Operation:

6035
Enable Keyboard Printer interrupt if AC1 1 = 1 or disable if AC11 = 0. AC11 must be set to 1 or
before this instruction is executed by the program.

Read Keyboard Buffer (DKRB)
Octal Code:

6036

Operation:

Jam-transfer the contents of the Keyboard Buffer to AC5-AC11 (Figure 12-5), set AC4 to 1, clear
AC0-AC3, and clear the Keyboard flag. AC5-AC6 contains a 7-bit ASCII code which represents the

key pressed on the keyboard.

DATA BITS

7 BIT ASCII CODE

r
Figure 12-5

MOST SIGNIFICANT ASCII BIT

Keyboard Data Format

12-15

12.3.4.3

Printer Instructions - The following instructions assume a device code of 04 is used for the printer.

Set Printer Flag (PNSF)
Octal Code:

6040

Operation:

Set the Printer flag

Skip on Print Done Flag (PNSK)
Octal Code:

6041

Operation:

Skip the next sequential instruction if the Print DONE flag is set.

Clear Printer Flag (PNCF)

Octal Code:

6042

Operation:

Clear the Printer flag.

NOTE
Octal Code 6043 is not used.

Load Printer Buffer (PNLP)
Octal Code:

6044

Operation:

Load the Printer Buffer from AC5-AC11 (Figure 12-6) and Print. AC5-AC11 contains a 7-bit ASCII
code which determines the character to be printed.

DATA BITS

8
1

L MOST

;ant a 3CII

J>IGNIFIC

Bl T

IGNORE D BY F>RINTEF

Figure 12-6

Printer Data Format

Skip on Keyboard or Printer Interrupt (PNSI)
Octal Code:

6045

Operation:

Skip if the interrupt is enabled and either the Keyboard or Print DONE flag is set.

Load Printer Buffer (PNPC)
Octal Code:

6046

12-16

Load Printer Buffer from AC5-AC11 (Figure 12-6), Clear Print
ASCII code determines the character to be printed.

Operation:

12.3.5

DONE flag, and Print. The 7-bit

Display Data Format

The two types of data that can be displayed on the VT8-E CRT are alphanumeric and graphic data.
12.3.5.1

Alphanumeric Data Format — Alphanumeric data displayed on the CRT is determined by the 12-bit word

(Figure 12-7) transferred from

memory during a Single Cycle Data Break. This word determines the visible field,

character display mode, and the character to be displayed as shown in Figure 12-6. The VT8-E can display 20 lines
of alphanumeric information; 64 normal sized characters or 32 enlarged characters can be displayed on each line.

NOTE
EOS allows termination of the display and LF code 012 allows
termination of the current row. Both termination methods
save core

memory and computer time for display with less

than 20 lines.

MD BIT

NOT
USED

7 BIT ASCII

CB2

CBl

CB3

CHARACTER

CONTROL

MODE
CONTROL

BITS

(SEE TABLE 3-2)

CB4

VISIBLE
FIELD

CODE

MSB

LSB

DISPLAY

B ITS

CB)

CB2

VISIBLE FIELD CONTROL BITS

NOP

EBF

CB3

CB4

END BLANK

FIELD.

CHARACTER DISPLAY MODE CONTROL BITS

NORMAL

VISIBLE FIELD, DISPLAY
CHARACTER IN BITS 5-11
ACCORDING TO CBl, CB2.
IF

ENABLE

BLINK

VIDEO STARTING WITH THIS

BBF

RATE (1.6Hz FOR 50Hz
SYSTEMS) IF IN VISIBLE ZONE.

BEGIN BLANK FIELD, DISABLE
VIDEO FOR THIS CHARACTER
AND THOSE FOLLOWING.
BLANK FIELD CAN BE TER-

EOS

END OF SCREEN, THE PREVIOUS CHARACTER IS THE
LAST TO APPEAR ON THE
SCREEN. VIDEO AND DATA
BREAKS ARE INHIBITED UNTIL
THE NEXT VERTICAL RETRACE.
THIS ALLOWS ABREVIATED
DISPLAY BUFFERS WHEN IT IS
NOT DESIRED TO USE THE
ENTIRE SCREEN. THIS SAVES
CORE BUFFER SPACE AND REDUCES PROCESSOR LOADING,

Figure 12-7

BOLD

DISPLAY THIS CHARACTER AT INCREASED INTENSITY IF IN VISIBLE

CURSOR

DISPLAY THIS CHARACTER AS A
CURSOR IF IN A VISIBLE ZONE.

ZONE.

MINATED BY EBF CONTROL
CODE.
1

BLINK THIS CHARACTER AT A
1.9 Hz

CHARACTER.
1

DISPLAY THE CHARACTER IN BITS
AT NORMAL INTENSITY IF IN
VISIBLE ZONE.

5-1

THE CHARACTER AND ITS DOT
MATRIX COMPLEMENT ARE DISPLAYED ALTERNATLY AT A 3.7Hz
RATE {3.1Hz FOR 50Hz SYSTEMS).

Alphanumeric Display Data Format

12-17

12.3.5.2

Graphic Data Format — The VT8-E is capable of displaying graphic information on a 189 (width) X 200

dot matrix. Each dot position corresponds to a bit of a data word in the core buffer. The first word of the
is the first to be displayed and bit 1 1 the last. If a bit is set to
buffer defines the first 12 dots on the first row. Bit
(height)

a dot

displayed and if it is set to 0, no dot is displayed. Sixteen 12-bit words are required to display one line of

graphic data.

The last 3 bits of the sixteenth word are not used. As an example, 16 words of all Is (7777) from

memory would cause a line of 189 dots to be displayed on the face of the CRT. In the Graphic mode there is no way
to terminate the buffer short of

3200 words (200 lines), thus the entire buffer must be defined even if a major

portion is blank.

12.3.6

12.3.6.1

Display Monitor and Keyboard Switches and Controls
Display IVIonitor Switches and Controls — Table 12-4 lists the switches and controls found on the display

monitor enclosure.

Table 12-4
Switches and Controls
Control/Switch

Location

Function

CONTRAST Control

Right-hand side

Used to adjust the picture for contrast.

BRIGHTNESS Control

Right-hand side

Used

adjust

the

CRT brightness

(intensity).

VERTICAL Control

Used to synchronize the

Right-hand side

raster in the

vertical direction.

HORIZONTAL Control

Used to synchronize the

Right-hand side

raster in the

horizontal direction.
\

ON/OFF Switch

Keyboard upper-

1 1

5V/230V

AC Circuit Breaker

Applies

primary power when

the

115V

230V

primary

Right-hand side

Selects

of CRT frame

power for the display.

Rear panel

Resets circuit breaker after
momentary fault (do not hold in).

pushbutton

SENSE switch

\ ON position.

right corner

Keyboard lower-

Use determined by the programmer

right corner

ON = logical

OFF = logical

12.3.6.2

Keyboard Controls — The basic function of the keyboard is to provide a convenient, on-line method of

transmitting ASCII-coded characters to the CPU for processing and, perhaps, display on the VT8-E CRT screen. The

keyboard transmits an ASCII code directly to the computer each time a key is pressed, and the computer, in turn,

may transmit the character code to the VT8-E control logic. The control logic determines if the received data is to
be displayed or used to control the displayed text format.

12-18

The keyboard can transmit either full ASCII or a 97-character subset. The selected code is determined by an internal
selector switch. With the switch set to position 1, the keyboard transmits the full ASCII character set listed in Table
12-5. With the internal switch set to position 2, the keyboard transmits the 97-character ASCII subset listed in Table
12-6.

The VT8-E Display Monitor does not display lower case alphabetical characters. However, it can receive both upper
and lower case characters, which are interpreted and displayed as upper case characters (Table 12-7).

Table 12-5

VT8-E Transmit Codes - Full ASCII Operation
1

Bit No.

6
5

4 3 2

space

10
11

10
10

110

111
c^

10
10

w
C^

(BS)
1

10 10

10 11

ALT

HOME

110
110

1110
1111

ERASE

LINE

ERASE
SCREEN

CTRL
Shifted

12-19

DEL
(rub out)

Table 12-6

VT8-E Transmit Codes - Half ASCII Operation
(switch in position 2)

7
Bit No.

4 3 2

1
1

(0)

^:#

,./,$

•

^.'

••-:%

110

111

(

)

10
10

(BS)
1

10 10

10 11

:.-.:;* „ -.

1110
1111

HOME
ERASE
LINE

ERASE
SCREEN

[

]

ALT

Shifted

12-20

-,:.<^

110
110

(0)

space

A
-

DEL
(rub out)

Table 12-7

VT8-E Receiving Codes
7
Bit No.

6
5

4 3 2

1
1

D
1

Olio

111

(

)

10
10

space

10 10

CR/LF

10 11

[

110

]

110

1110
1111

[

]

12-21

>
/

space

^
-

>
/

12.3.7

Programming Examples

The following VT8-E programming examples are programs that may be used to display alphanumeric or graphic data
on the CRT.

12.3.7.1

Graphic Display Program Example — This program displays data from the Switch Register in a 189 X 200

dot matrix. A dot is displayed for those bits on the Switch Register that are set to Is and a space is displayed for
those bits in the Switch Register that are set to 0.

Memory
Location

Instruction

0200

6007
1216
6050

0201

0202
0203
0204
0205
0206
0207
0210

Mnemonic

VTGRPH

0212
0213
0214
0215

VT,

0221

0222

12.3.7.2

/THE DATA INTHESR.

/LENGTH OF DISPLAY BUFFER
/SET COUNTER FOR FILLING BUFFER.
/READ DATA PATTERN FROM THE SR.
/STORE IN BUFFER
/BUFFER FILLED.
/NO, CONTINUE FILLING IT.
/RELOAD BUFFER AGAIN.

COUNT

LAS

5205

0400
0377
0000
0002
1600

TAD
DPGO
TAD
DCA
TAD
DCA
DCA

5211

0216
0217
0220

M6200

BUF

DP LA

6051

0211

BUFMl

/CLEAR AND INITIALIZE.
/LOAD THE STARTING ADDRESS
/OF THE DISPLAY BUFFER INTO THE VT8-E.
/CODE FOR GRAPHIC
/DISPLAY IN GRAPHIC MODE.
/SET AUTO INDEX FOR STORING

CAP

TAD

1221

1217
3010
1222
3220
7604
3410
2220

Operation

ISZ

COUNT

JMP
JMP

-3

BUF,

400

BUFM1,
COUNT,

400-1

K2.

M6200,

-6200

/STARTING ADDRESS OF BUFFER.
/STARTING ADDRESS OF BUFFER -1.
/COUNTER FOR FILLING BUFFER.
/GRAPHIC ENABLE WORD.
/COUNT FOR FILLING BUFFER.

Alphanumeric Display Program Example — This program echos the character typed on the console

keyboard on the VT8-E display. The Switch Register is ORed with the character to display the character in the
Normal, Blink, Bright, or Cursor mode. The display mode is selected from the Switch Register (Figure 12-7) as
follows:

0000
0200
0400
0600

Normal
Blink
Bright

Cursor

12-22

Memory
Location

Instruction

0200

6007
1233
3010

0201

0202
0203
0204
0205
0206
0207
0210
0211

0212
0213
0214
0215
0216
0217
0220
0221

0222
0223

Mnemonic

VTALPH

1233
3011

1235
3410
1240

3234

CAF

TAD
DCA

BUFM1

TAD
DCA
TAD
DCA
TAD
DCA

BUFM1

EOS
1

M2400

COUNT

TAD

1232
6050

BUF

DPLA
DPGO

6051

6031

Operation

INPUT,

5214
6036
0236

KSF
JMP

/NO, WAIT.

.-1

/READ THE CHARACTER.

KRB

AND
MQL
TAD
DCA

7421

1235
3410
7604

/CLEAR AND INITIALIZE.
/ADDRESS OF BUFFER -1.
/SET AUTO INDEX FOR POSITIONING
/THE END OF SCREEN CHARACTER.
/ADDRESS OF BUFFER 1.
/SET AUTO INDEX FOR STORING CHARACTERS.
/GET THE END-OF-SCREEN CHARACTER (3000).
/PUT END OF SCREEN IN DISPLAY BUFFER AREA.
/SET COUNTER SO PROGRAM IS RESTARTED
/AFTER A FULL SCREEN IS DISPLAYED.
/(64 CHARACTER MODE)
/LOAD THE STARTING ADDRESS
/OF THE DISPLAY BUFFER INTO THE VT8-E.
/GO DISPLAY.
/CHARACTER YET

K177

/KEEP ONLY 7 BITS.
/SAVE IN THE MQ REGISTER.

EOS

/MOVE THE END-OF-SCREEN
/CHARACTER UP ONE IN THE BUFFER.
/READ DISPLAY MODE CONTROL BITS
/FROM THE SR.
/SAVE ONLY THE CONTROL BITS.
/"OR" THE CHARACTER WITH THEM.
/STORE CHARACTER WITH CONTROL BITS.
/FULL SCREEN (64 CHAR MODE)?
/NO, GET ANOTHER CHARACTER.
/YES, RESTART THE PROGRAM.

LAS

0237

AND

7501

MQA

3411

DCA
ISZ

COUNT

0231

2234
5214
5200

JMP
JMP

VTALPH

0232
0233
0234
0235

0400
0377
0000
3000

BUF,

400

BUFM1,
COUNT,

400-1

EOS,

3000

0236
0237
0240

0177
0600
5400

K177,

177

/7 BIT MASK.

K600,

600

M2400,

-2400

/CONTROL BIT MASK.
/LENGTH OF BUFFER.

0224
0225
0226
0227
0230

K600
1

INPUT

/STARTING ADDRESS OF BUFFER.
/STARTING ADDRESS OF BUFFER
/FULL SCREEN COUNTER.
/END-OF-SCREEN CHARACTER.

SECTION 4 DETAILED LOGIC DESCRIPTION
12.4

INTRODUCTION

A simple block diagram of the VT8-E Video Display and Control

shown in Figure 12-8. The interface supplies the

monitor with video and sync signals, and an audio tone. The video is either alphanumeric character information or
graphic information, or a combination of the two that is made possible by switching the display mode at the screen
refresh rate.

12-23

INTERFACE MODULES
DATA BREAK XFER,
DISPLAYABLE DATA

PDP8/E,
8/F,8/M
OMNIBUS

DISPAY MONITOR

M8337

VIDEO.AUDIO.SYNC

M8336
^PROGRAMMED INTERRUPT ^

^96-128-CHARACTER ASCT

DEC STANDARD

StI

KEYBOARD

M8335

XFERS

128-CHARACTER ASCII
SET

Figure 12-8

CRT DISPLAY CKTS

LA30(A)-P

OR
LS01-ED PRINTER

VT8-E Functional Block Diagram

The keyboard transfers data directly to the computer's AC Register by program interrupts or flags. Each character
code transmitted can either be displayed or used to control the displayed text format. Data transmitted to the
system printer

also transferred

by program interrupts or flags. When the Interrupt System is disabled, flags are

checked by the SKIP instructions.

The

logic

description

divided

into

two

parts:

one part concentrates on the interface

both the

logic for

keyboard/printer and the display, while the second part concentrates on the keyboard and CRT circuits.

12.4.1

Keyboard/Printer Logic

A block diagram of the VT8-E Keyboard/Printer logic is shown in Figure 12-9. Pin assignments for OMNIBUS signals
and connector signals can be found on Engineering Drawing E-CS-M8335-0-1.

OMNIBUS

KYBD(O) L

DATA 4-11 L
lOT

CONTROL
SIGNALS

KEYBOARD
TRANSMIT
LOGIC

KEYBOARD
STROBE L
BIT 1-7 L
SKIP L'^
INT RQST L-*lOT,

INTERNAL J/0 L-»-

CONTROL
SIGNALS

CO L.C1 L-*-

INT/SKIP
LOGIC

DATA
1/0

PAUSE L-

MD 3-11 L-

DEVICE

AND lOT
DECODER
LOGIC

lOT
"INSTRUCTIONS

INITIALIZE L
PRINT(O) L

BIT 1-7
.PRINTER
INITIALIZE L

INITIALIZE-

-^^^^

STROBE L
lOT,

CONTROL
SIGNALS

DATA

5-11 L-

Figure 12-9

PRINTER
RECEIVE
LOGIC

Printer/Keyboard Block Diagram

12-24

•DEMAND

The VT8-E Keyboard/Printer logic has two distinct functions:
Printer Buffer Register and transfer of data

transfer of data from the CPU AC Register to the
from the Keyboard Register to the AC Register. The transfer of data to

the Printer Buffer is carried out by the Printer Receive logic. When the printer is able to receive data, it asserts the

DEEMAND signal. This signal sets the PRNT FLG flip-flop in the Printer Receive logic. The resulting PRNT (0) L
causes the INT/SKIP logic to assert the OMNIBUS INT RQST L signal, if the VT8-E has been logically

signal

connected to the interrupt system. Alternatively, PRNT (0) L can be tested by a program skip instruction in the

INT/SKIP logic.
transfer.
lines

In either case,

the computer ultimately proceeds to a program subroutine that begins the data

When this subroutine is executed, the information is transferred from the AC Register to the DATA 5-1

and clocked into a 7-bit register in the Printer Receive logic. The register outputs are available at J1 as the BIT

1-7 signals. The logic then generates a PRINTER STROBE L signal that clocks the BIT 1-7 data into the Printer
Buffer Register, clears the PRNT FLG flip-flop, and causes the printer to negate the

DEMAND signal.

The transfer of data from the Keyboard Buffer Register to the AC Register is carried out by the Keyboard Transmit

When a keyboard key is pressed, information is applied, via the BIT 1-7 lines, to a 7-bit register in the
Keyboard Transmit logic. When the keyboard generates a KEYBOARD STROBE L signal, the information is clocked

logic.

into the 7-bit register and the KYBD FLG flip-flop is set. The KYBD (0) L signal can be tested in the INT/SKIP logic
with a SKIP instruction, or the interrupt system can be used to cause the program to enter an appropriate
subroutine. When the subroutine is executed, the information is gated from the register in the Keyboard Transmit
logic to lines DATA 5-1 1 (the logic asserts the DATA 4 L signal separately so that the input character is compatible
with the modified-ASCII Teletype code), then to the AC Register. The AC is loaded and, simultaneously, the KYBD

FLG flip-flop is cleared.
lOT Decoder Logic - The lOT Decoder logic is shown in Figure 12-10, which includes the Video Display
Decoding logic for reference. The VT8-E Keyboard/Printer uses 12 lOT instructions, 6 for the keyboard and 6 for
12.4.1.1

the printer. (One of the listed printer lOTs, Skip on Printer or Keyboard Interrupt, apply to both functions and one
of the keyboard lOTs, Interrupt Enable/Disable.) More than one keyboard/printer can be interfaced to the PDP-8/E

The VT8-E (or other control module) associated with each keyboard/printer must be assigned a
unique device selection code for both the keyboard and the printer. Therefore, the M8335 module is fabricated with

at the same time.

jumpers and solder terminals that allow the user to assign any one of 64 possible device selection codes to both the

keyboard and the printer (care should be taken when assigning device selection codes to preclude multiple
assignments of the same code). Figure 12-10 illustrates the octal codes and mnemonics that pertain when the VT8-E
is

manufactured. The octal codes and mnemonics for the instructions are listed in Paragraph 12.3.2. A complete list

of device codes and the jumpers required to select each device code is shown in Table 12-2.

12„4.1.2

Printer Receive Logic - The Printer Receive logic is shown in Figure 12-11. Significant signals are related

by the timing diagram in Figure 12-12. Refer to both figures when reading the logic description.

The printer routine is initiated by DEMAND changing to the true state, indicating that the printer is ready for
another character. This sets the PRNT flag flip-flop. This flip-flop can also be set by the PNSF instruction at TP3
time.

the VT8-E

signal causes the

logically

connected to the interrupt system, as this discussion assumes, the PRNT FLG (1) L

INT/SKIP logic to assert the OMNIBUS INT RQST L signal. The program proceeds to an interrupt

servicing routine to determine the identity of the requesting device.

The PNSI instruction in the routine causes the
program to jump to a VT8-E routine that determines whether the printer or keyboard requested the interrupt (other

options are open to the programmer, this is but one example). Ultimately, the VT8-E printer routine executes the

PNPC instruction.
During TS2 of the PNPC instruction, information is gated from the AC Register to the DATA lines and remains on

DATA lines through TS3. When PNPC L is decoded in the lOT Decoder logic, it enables NOR gates E25C and
E25D (Figure 12-11). NOR gate E25-D asserts the DATA EN signal; both DATA EN A L and DATA EN B L are
derived from this signal. The difference between the DATA EN A L and DATA EN B L signals is significant only
when considering the Display logic; for the present one must know only that one of these two signals gates lines
the

DATA 9 and DATA 10 to the 7-bit register. The remaining DATA lines are gated to the register flip-flops as shown.

12-25

P/0

M8336 MODULE
1

E46

BCD-TO- 3
DECIMAL ^
7442 ^

DPLA L
DP60 L
-DPSM L
- DPMB L
- DPMD L
-

iiO
LTT

SELECT DISPLAY L

O
::C^

MD11 L-

MD10 L-

603X605X-

-DPBL L

MSB

2r^:='

tl>'

DISP

KYBD

-C

MD3 L-

604X—

"=0

MD9 L-

DPCL L

::^:0
IKYBD

-DKCF L

-DKSKL

MD4 L-

DKCC L

EI8

::^3I>

BCD-TO
DECIMAL

:kybd

7442

MD5 L-

=33

::X>

-DKOB L
-DKIN L

{>^ MSB

-DKRB L

IKYBD

PRNT

MD6 L-

::^0

-PNSF L

-O

DISP

-&KYBD

-PNSK L

-PNCF L

BCD-TO- ,
DECIMAL ^
7442
4

-PNLP L

-PNSI L

-PNPC L

E26

MD7 L-

::^X>

Bzy

KYBD

-o

i>-

MSB

i»—

MD8 L-

::tO
+5V
CO L

I/O PAUSE

^3I>TO^tI>i

"ENABLE L

DKOB L

NOTE:
Logic

P/0

M8335 module, unless noted otherwise.

Figure 12-10

lOT Decoder Logic

12-26

-CI L

12-27

At TP3 time of the instruction, NAND gate E-17 is enabled and the information on the DATA lines is clocked into
the 7-bit register. Simultaneously, flip-flop STROBE 1 sets and the PRNT FLG flip-flop is cleared. The register data
is

applied, via the BIT 1-7 lines, to the Printer Buffer Register. At the beginning of TS2 of the instruction following

PNPC, flip-flop STROBE 2 sets and asserts PRINTER STROBE L. This signal loads the Printer Buffer Register and
negates the

DEMAND signal. Both STROBE

and STROBE 2 are cleared by the next TP3. When the print cycle

ends approximately 30 ms later, the DEMAND signal is again asserted and a new transfer can be started.

PRINT CYCLE

is30MS

PFMANP

PRNT FLG (1) L

INT RQST

PNSI

SKI P L

PNPC

TS2

TP3.

DATA 11-5

BIT 1-7.

INSTRUCTION

xxxx

RCVR STROBE

NOTE
T1,T2 and T3 are distinct lime periods.
The amount of time between periods
a function

program-routine execution time.

Figure 12-12

Printer Receive Logic Timing

12-28

12.4.1.3

Keyboard Transmit Logic - The Keyboard Transmit logic is shown in Figure 12-13. Significant signals are

related by the timing diagram in Figure 12-14. Refer to both figures when reading the logic description.

DKCC

DKRB
NITIALIZE

^ty°

—

KEYBOARD
STROBE H

— KYBD

FLG (1) L

DKOB L
E17D

DKRB L
BIT

DATA 11 L

-M-VVV-

E32
BIT 2 L

Db quad Qb

DATA 10 L

F/F

BIT 3 L

-W—

CLOCK

BIT 4 L

-M—

<»

BIT 5 L

-W—

DATA 9 L

E28 Jo

D ATA 8 L

E28

DATA 7 L

E31

<•

74175

QUAD
F/F

BIT 6 L

BIT 7 L

+—«•

NOTE

CLOCK

E27

M8335 module

Figure 12-13

Keyboard Transmit Logic

12-29

DA TA 6 L

]zi[^zy-^ ATA 5 L
+ 3V

;

Logic Is P/O

~n E27\>

DATA 4 L

ilT

1-7 Li

KEYBOARD STROBE

„J1

KYBD FLG (1) L

INT RQST

PNSI L

DKRB

DATA 11-4

CO L, CI

TP3.

Figure 12-14

Keyboard Transmit Logic Timing

The user initiates the keyboard sequence by pressing a key on the keyboard. The character information is placed on
BIT 1—7 lines. After a period of time that allows the BIT lines to settle, the keyboard generates the
KEYBOARD STROBE H signal. The trailing edge of this signal clocks the information into the 7-bit register and sets
the KYBD FLG flip-flop. If the VT8-E is logically connected to the interrupt system, as assumed, the KYBD FLG
(1) L signal causes the INT/SKIP logic to assert the OMNIBUS INT RQST L signal. The program proceeds to an
interrupt servicing routine to determine the identity of the requesting device. The PNSI instruction in the routine
causes the program to jump to a VT8-E routine that determines if the printer or keyboard requested the interrupt.
Ultimately, the VT8-E keyboard routine executes the DKRB instruction.

the

When the DKRB instruction is decoded, the lOT Decoder logic generates the DKRB L signal and activates the
OMNIBUS CO and CI lines. The DKRB L signal enables NOR gates E17C and El 7D; the output signal from E17D

DATA lines 5—1 1, and also causes NAND gate E27 to assert the
DATA 4 L signal. The DATA lines are gated to the AC Register and the information clocked into the register at
TP3 time. Also at TP3, the KYBD FLG flip-flop is cleared, readying the logic for a new data transfer.

gates the information from the register outputs to

INT/SKIP Logic -The INT/SKIP logic is shown in Figure 12-15. The PRNT FLG (1) L signal and the
KYBD FLG (1) L signal can cause program skips when tested by instructions PNSK and DKSK, respectively. The
signals can also be tested by the PNSI instruction, provided the EN A flip-flop, E37, has been set, logically
12.4.1.4

connecting the VT8-E to the interrupt system. When E37 is set, the PNSI L signal enables NAND gate E29, which, in
turn, enables

NAND gate E34,

either the

PRNT FLG (1) L signal or the KYBD FLG (1) L signal is asserted.

Simultaneously, NAND gate El 3 asserts the INT RQST L signal.

12-30

INITIALIZE L

B DATA

11 L-

-<:iD

E37
ENA

TP3

E33

F/F

PRI0T5L
(PNSI)L

E29

E34

j"b^

INITIALIZE

E34
E35 P— SKIP L

KYI0T5L(DKIN)

73>-

KY lOT 1 L
(DKSF)

KYBD

_«_

FLGCDL^^
PRI0T1 L
(PNSK)L

PRNT

FL6 (1)L

t^Ey

INT
RQST L

NOTE:
Logic

P/0

M8335 module.

Figure 12-15

Keyboard/Print Interrupt and Skip Logic

The ENA flip-flop is set by the OIVINIBUS NIT signal for the PDP-8 family computers. To clear the flip-flop,
remove the VT8-E from the interrupt system, load AC11 with logic and then program the DKIN instruction. The
logic
in AC1 1 keeps the DATA 1 1 L signal negated. Thus, the D input of E37 remains high. At TP3 time, NAND
gate E22B provides a clock pulse for E37, clearing the flip-flop. E37 can be set at any time with the same instruction
I

merely by loading AC11 with logic 1.
12.4.2

Display Logic

Information displayed by the VT8-E is transferred by data breaks from the PDP-8/E memory. As with all data break
devices, the start of the data transfer is under program control. However, the VT8-E is a 1 -cycle data break device;

consequently, it needs only a starting memory address to carry out the complete data transfer. The starting address,
the memory address of the first data word to be transferred to the VT8-E, is placed in the AC Register by a
program TAD instruction. Program lOT instructions gate this address onto the OMNIBUS DATA lines and cause it
i.e.,

to be loaded into a starting address register in the VT8-E (Figure 12-16). At the same time, the VT8-E Data Break
logic is readied for triggering.

When the CRT sweep is in a specified position, a synchronizing signal is generated by the VT8-E Timing logic. This
Data Break logic to request a data break and check priority. If no higher priority device has
requested a break at this time, the Data Break logic asserts a number of OMNIBUS control signals, enabling direct

signal enables the

communication between the interface and memory for one PDP-8/E timing cycle. At the same time, other Data
Break logic signals gate the starting address onto the OMNIBUS MA lines. During the data break timing cycle, the
in the addressed memory location is transferred on the MD lines and loaded into the interface Line Buffer
At TP4 time of the timing cycle, the Data Break logic increments the address in the Address Counter. The
data word in this new address is transferred during the next data break timing cycle, which might occur immediately

data word
Register.

after the first (priority

checked during TS4 of each data break cycle; a higher priority device can interrupt the

VT8-E data breaks).
After each transfer, the address

the Address Counter

incremented, and the data word in the new address is

loaded into the Line Buffer Register. This register holds 32 or 64 data words, depending on the mode (graphic or

alphanumeric) or the desired number of alphanumeric characters per line. The Data Break logic counts the number
of data breaks; when the specified number of data words has been loaded into the Line Buffer Register, the Data

Break logic ceases to request breaks.

12-31

O'
^,
a>"

>
>-

<
_i
00.0

>Oo

>5§
<flO-J

a
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m

Ijuj

r-.'-^

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— ore)

xujo

IliJO
CLtl. _|

Q-U. _l
-JLl.

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03

Qt-Z
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f^=>

<tiq:=)

OCD

„o
q: —
(TO

<5
53
2z

U.O
li.

_)
UJ

UJH

Z<rt

_|0

UJ
tK

Q
o
o
CD

12-32

If the VT8-E logic has been programmed to display 32 alphanumeric characters per line; for example, each data
word in the Line Buffer Register contains: the 7-bit ASCII code representation of an alphanumeric character (bits

5-11); data that controls how the character is displayed (bits 3 and 4); and data that controls the visible field (bits 1
and 2). Because the VT8-E displays only a 64-character set, bits 6—11 of the Line Buffer Register contain sufficient
data to display all alphanumeric characters. Characters are formed on the CRT screen when the CRT video circuits
selectively intensify points within a 5 X 7 dot matrix.

The letter F is illustrated in Figure 12-17, Each horizontal

scan line corresponds to one row of the letter. As the sweep scans along a line, video signals selectively intensify
points as illustrated (5 video signals in

displayed, for example, row

row

of the letter F).

32 alphanumeric characters per line are to be

of each character is swept out by the same scan line. The next scan line sweeps out

row 2 of all 32 characters, and so on until the 7th scan line sweeps out row 7 of the characters, completing the
character line.

•

8E-0626

Figure 12-17

Video Presentation for the Letter F

The video signals are generated, indirectly, by a ROM Character Generator. After the start of a horizontal scan line, a
6-bit ASCII character is shifted from the Line Buffer Register (at this time, the register is in the recirculating mode;
hence, an end-around shift is performed). The character addresses a ROM Character Generator location. This
location contains the video information for one row of the character. For example, assume that the letter F is the
first character to be displayed in a particular character line. The 6-bit ASCII representation of the letter F addresses
a particular ROM Character Generator location. The information in this location causes row 1 of the letter to be
painted during this scan line. The next character to be displayed is shifted from the Line Buffer Register and
addresses its unique ROM Character Generator location; the information in the location causes row 1 of this
character to be displayed just after character F. Row 1 of all 32 characters is displayed during this scan line.
Afl:er the start of the

next horizontal scan line, the 6-bit ASCII representation of the letter F is again shifted from

the Line Buffer Register. Meanwhile, certain

ROM control signals have been asserted so that the addressed location

Row 2 of the letter F to be
Row 2 of all other characters is displayed during this scan line in similar fashion.

differs from that of the first scan line. This location contains information that causes

painted during this scan

line.

Consequently, the Line Buffer Register is shifted 32 times during each scan line; after 7 end-around shifts of the
register, a character line has been displayed.

Each character line comprises ten scan lines, rather than the seven just described. The three additional lines occur at
the beginning of the character

line.

During the first two scan

lines,

the Line Buffer Register is loaded from the

OMNIBUS MD lines; during the third scan line, a blank ROM location addressed. Figure 12-18 represents two
character lines as they would appear on the CRT screen. Character line spacing (43% of character height) is provided
is

by the three blank scan lines.
If

the VT8-E has been programmed for a graphic display, one line of graphic data is displayed during each horizontal

scan

line.

A line of graphic data

represented by 16 12-bit data words; each bit of a data word represents a dot or a

12-33

space on the CRT screen. The Line Buffer Register is loaded with two lines of graphic data by 32 data breaks. As the
sweep scans along a line, video signals selectively intensify points to paint the graphic symbol. Although 16 12-bit
data words contain 192 bits, only 189 points can be painted by each scan.

10 SCAN
LINES PER

CHARACTER
LINE

LINE BUFFER

LOADED FOR
NEXT ROW OF

CHARACTERS

Figure 12-18

12.4.2.1

Two Alphanumeric Characters Displayed on the CRT

VT8-E Timing — The VT8-E Timing logic generates signals that sync the Display logic and the CRT sweep
12-19 illustrates the CRT vertical and horizontal sweep signals and the VT8-E sync signals.

circuits. Figure

For 60 Hz operation, the VT8-E timing generates a V SYNC L signal every 16.7 ms. This sync signal causes a vertical
retrace,

which

carried out in approximately

20 scan

lines.

A VZONE flip-flop in the timing controls the

displayable area in the vertical direction. When the flip-flop is set, the VZONE (1) signal enables a vertical display of

200 scan lines (the horizontal sweep rate is set at 15.6 kHz; a total of 60 scan lines is made non-displayable to
remove distortion-prone areas on the CRT screen).
The timing generates an HSYNC signal every 64.1 /is. A HZONE flip-flop in the timing controls the displayable area
in the horizontal direction.

When the flip-flop is set, the HZONE (1) signal enables graphic or alphanumeric video to

be painted in the distortion-free area of the screen (exceptions to this statement are pointed out in the detailed logic
discussion).

12-34

V SYNC L (f»60Hz)

VERT SWP

V ZONE (1)

U-40-U^

200 SCAN LINES

AT HORIZ. SWP

RATE

OF 15.6KHZ

NON- DISPLAYED
SCAN LINES

U—

NON -DISPLAYED
SCAN LINES

64.1/tS
H SYNC

HORIZ SWP (f»15.6KHz)

H ZONE (1)
I

90R18

34.61/iS (GRAPHIC)

OR 18

NON-DISPLAYED
CHARACTERS

NON-DISPLAYED
CHARACTERS
41.02/tS

"(ALPHANUMERIC)'

Figure 12-19

Sweep and Sync Signals

The VT8-E timing is such that either 50 or 100 alphanunneric characters could be displayed between HSYNC signals.
The HZONE (1) signal reduces the number of characters to either 32 or 64, respectively (an equal number of
removed on both sides of the screen). Note that the HZONE (1) signal is of shorter duration for the
is explained as follows.
Clock pulses of the same basic frequency are used to shift the
Alphanumeric Video Buffer Register and the Graphic Video Buffer Register. Seven shift signals are needed to display
the rows of the
alphanumeric character matrix (five signals intensify the scan, two signals provide spacing
between each character). Thus, 7 X 32, or 224 shift pulses are needed for an entire character line. An entire graphic
line needs only 192 shift pulses. Consequently, it seems that the HZONE (1) signal should be reduced by an amount
that allows 192 shift pulses to be generated (if the display area is not shortened, an improper display will result).
This would mean reducing the graphic displayable area by an amount equal to 32 shift pulses. However, this is not a
multiple of seven, which it must be to enable correct alphanumeric display. The closest number that is a multiple of
7 is 35. Thus, the horizontal zone for graphics allows only 189 shift pulses to be produced, cutting off the last 3 data
bits in each scan line (note that 28 could not be used because then too many graphic shift pulses would be
produced). The pulses are derived from a 5.46 MHz clock (t = 183.15 ns). Therefore, 189 shift pulses require an
characters

graphic display. This

5X7

HZONE (1) signal of only 34.61
12.4.2.2

jJis.

VT8-E Timing Logic — The VT8-E Timing logic generates the CRT sync pulses and the interface control

signals. All

timing and control signals are derived from'a crystal-controlled transistor oscillator that produces pulses

MHz. These pulses are applied to a Clock Pulse Generator, shown in Figure 12-20. The
generator divides the basic frequency by 2 and 4, producing well-shaped clock pulses of 10.92 MHz and 5.46 MHz.

at a frequency of 21.84

Two test points are available which allow the oscillator clock to be inhibited and external clocks injected to drive the
timing chain.

12-35

-O 32
I

+ 5V

r—

TP-

CRYSTAL

CNT
UP

CLOCK
F = 21. 84MHz

INIT +REMV SYNC
TRUTH TABLE
(Each Flip-Flop)
tn

n+1
K

NOTES:

1. Logic

P/0

M8336 Module

64 Alphanumeric Charocter/Line
Connect jumper "32" for 32 Alphanumeric Character/Line
3. DEC 74 73 J-K F/F Truth Table
2. Connect jumper"64"for

n =BIT TIME BEFORE CLOCK PULSE.
tn + 1

BIT TIME AFTER CLOCK PULSE.

Figure 12-20

Clock Pulse Generator

The clock pulses selected are applied to a chain of DEC 74161 4-Bit Counters that counts down the pulse frequency
to 3.75 Hz (for 60 Hz operation). Selected outputs of the timing chain are gated to produce sync pulses and control
signals.

A logic block representation of the DEC 74161 4-Bit Counter Integrated Circuit (IC) is shown in Figure 12-21. This
IC,

El 7, is the first one in the timing chain. Because it is a 4-bit counter, El 7 can produce one pulse at its CARRY

output for each 16 pulses

its

COUNT UP input. However, because the IC can be preset to any count, it can

produce a CARRY output for any number of input pulses less than 16. The preset inputs are labeled A through D in
Figure 12-21 (A is the LSB). They are wired so that El 7 is preset with a count of 1001 2 whenever a signal is applied

to the

and

LOAD input and a clock pulse occurs. The CARRY signal

generated when the count is in the 1 1 1 12 state

ENP and ENT are true. A Load signal is generated by the OR gate and El 7 is preset to 1001 2. Seven more

pulses at the clock input produce another

CARRY signal and, again, the counter

preset. Thus, the counter divides

by seven. The counter can also be preset by a REMOTE V SYNC IN L signal, enabling the timing to be controlled by

some external device. The output of each bit, designated QA through QD (QA is the LSB), is available for gating to
generate the sync and control signals,

+ 3V

REMOTE
VSYNC H

ri
©64
CARRY

CLOCK
(2

E17-i-7

ENABLE P

74193

LOAD D-

+ 3V—'— ENABLE T °A

Figure 12-21

4-Bit Counter

12-36

'=T>i

Figure 12-22 shows the entire chain of 74161 ICs. Each IC in the figure is represented in shorthand form:

i.e.,

the

PRESET inputs is not shown, the LOAD input circuits are not shown, and the destination of each

wiring of the

output is now shown (only those output bits that are used are indicated on the ICs). The binary designations above
each IC block represent the way the preset inputs are wired. For example. El 6 is wired thus:
tied to +3V; PRESET input C is grounded; PRESET inputs B and

PRESET input D is

A are tied to +3V. Therefore, E16 is preset with a

count of 1011 2 and divides by 5.

F«t0.92MHz *(1001)2

i64CH
CL.K

»(1011)2

E17+7
CARRY

a32CH

E16^5

32CH

CARRY

CLK
64H

»*(1110)2

F»5. 46MHz

E12-^2

CLK

CARRY

»(C100)2
E31- 12
^^^^^
CLK
LOAD

F = 5.46MHz-

»t(0110);

•(0110)2

E18*10
CARRY

CLK

CARRY

CLK

I—®6OHz0

•t(1110)2

£19-^10

CLK

50Hz

—t— +3V

E8-2
CARRY

CARRY
CLK

LOAD
A

^Sq^^
•COUNTER IS PRESET TO THIS BINARY VALUE

IC OUTPUT FREQUENCY
IC

NOTE;
Logic

P/0

REMOTE VERT SYNC IN
+ 50HZ RESET H
50Hz RESET

FREQ. OUTPUT

60Hz LINE

780KHz(32)
Et7
1560KHz(64)
El 6 i56KHz

M8336 Module

El 8

15.6KHZ

50Hz LINE

SAME
AS

60Hz

E19 1.56KHZ

E8 780Hz

Figure 12-22

E9 60Hz

50Hz

E42 3.75Hz

3.125Hz

VT8-E Timing Chain

Each IC has a NOR gate at its LOAD input, exactly as shown in Figure 12-21; this gate ORs the CARRY output
with REMOTE V SYNC and INIT (E17, E12, E16), or with REMOTE V SYNC and 50 Hz RESET (E18, E19, E8,
E9). The bit output destinations are shown, in part, only for ICs E19, E8, and E9.

The table in Figure 12-22 indicates the frequency of the CARRY output pulses of each IC. The output frequency
from El 7 differs for 32 character/line and 64 character/line operation. The bit output signals from El 7 determine
the alphanumeric character rate, the rate at which characters are painted on the CRT screen. Thus, the rate is twice
as

fast

for

64 character/line operation. El 2 divides by two; therefore, the input of El 6 is the same for both

character rates.

12-37

When a 50 Hz line is used, the tinning is modified in the last three ICs. For 60 Hz operation, E9 is preset with a count
of 001 12 and its

26, producing a

CARRY output provides the LOAD input for E9. E8 and E9, together, divide the output of E19 by
CARRY output pulse from E9 at a frequency of 60 Hz. This output gated elsewhere in the logic
is

V SYNC L signal that causes a CRT vertical retrace. For 50 Hz operation, the 50 Hz jumpers are
connected, and E9 is preset with a count of OOIO2. Furthermore, the LOAD input of E9 is controlled by REMOTE
V SYNC IN or 50 Hz RESET H. When E9 attains a count of 001 2 and both E19-D and E8-A are high, E9 is preset
and a V SYNC pulse is generated. E8 and E9, together, divide the output of El 9 by 31.2, producing pulses having a

to generate the

frequency of 50 Hz. The table shows the output of E9 as 50 Hz (the output is not actually from E9, as for 60 Hz
operation, but it is convenient to think of it as so). As for 60 Hz operation, the output is gated to generate the V

SYNC L signal.

Note that the REMOTE V SYNC IN or 50 Hz RESET line is activated when E9 is preset; thus, ICs E18, El 9, E8,
and E9 are preset at the moment of vertical retrace. This active step is not necessary during 60 Hz operation because
all

ICs automatically overflow to the preset state.

Figure 12-23 shows the logic that generates the horizontal and vertical sync signals, while Figure 12-24 shows the

HZONE and VZONE flip-flops and those signals that control the two flip-flops. The timing diagram in Figure 12-25
shows the line timing for both alphanumeric and graphic display. Two hundred of the HZONE (1) signals are
generated for each VZONE signal, as shown in Figure 12-19.

+ 5V

ri
+ 5V
E16 CARRY'CLK

x-IX

E18-A
E18-D

H SYNC

+ 3V
+ 5V

CLK

REMOTE VSYNC_
+50HZ RESET
E9 CARRY -

60Hz

SYNC

74123
>124m8

50Hz
CLE AR

P
+ 3V
NOTE'
Logic

P/O M8336 module.

Figure 12-23

Horizontal and Vertical Sync Circuits

12-38

E46A

+ 5V

V SYNC

D—^0>--M
EI6-B

EI6-A

EI8-BE16

ENABLE T

H ZONE (

)

D--0

CLK

EI8-A

EI8-B

EI8-C

EI8-B

E28
DEC
8266

EI8-C

E9-B —I

EI9-A

FOR GRAPHIC /SELECT A
LO FOR ALPHANUMERIC /
SELECT B

HI
I

E9-C

V ZONE(I)

E8-A
,^

|__^

EI9-B
EI9-C
EI9-D

E9-D

Figure 12-24

12.4.2.3

Horizontal and Vertical Zone Flip-Flops

Starting Address Register Logic - The Starting Address Register logic is shown in Figure 12-26. The logic

includes two Starting Address Registers:

one is a 12-bit register comprised of two DEC 74174 ICs (hex flip-flop);

the other uses three bits of a DEC 74175 IC (quad flip-flop). The Address Counter is comprised of four DEC 74193
ICs (4-bit up-counters) connected in series and is preset from the Buffer Registers.

The control signals that load and clock the Starting Address Registers and the Address Counter are generated by the
Starting Address Control logic, shown in Figure 12-27. When the program lOT instruction DPLA is issued, the 12-bit
starting address is placed on the DATA lines. The DPLA L signal causes both the DATA EN A L and DATA EN B L
signals to be asserted. The starting address is gated through the NAND gates to the DEC 74174 inputs and loaded
into the buffer at TP3 time by the LD ST

ADD signal.

The extended field must also be identified by the EMA bits. The extended field address bits are placed on lines
DATA 6, 7, and 8 by the DPGO lOT instruction. The DPGO L signal causes the DATA EN signals to be asserted,
gating the extended address to the DEC 74175 inputs. At TP3 time the XST ADD REG is loaded by the LD XST
ADD signal (DPGO).

12-39

E16 CLK UP

780KHZ

(32 CH/LINE)

Et6-A

E16-B

E16-C
E16 CARRY
156 KHz

—
E18-A

—

E18-B

—

—
E18-C

—

E18-D

—

E18-CARRY
(LINE COUNT)

—

HSYNC

—

15.6 KHz

H ZONE (1)

GRAPHIC —'

1
1

ALPHANUMERIC
8E-0634

Figure 12-25

Alphanumeric and Graphic Line Timing

The DPGO L signal also clears the MAINT/GO flip-flop (Figure 12-27) at TP3 time, negating the MAINT L signal.
This negated signal enables a vertical sweep synchronizing signal, E46(Q), to assert the LD ADD CNTR L signal. This
signal loads the starting address (including the extended address) into the 15-bit Address Counter.

At approximately the same time that the Address Counter is loaded, the Data Break Counting logic is readied for
When the sweep is in the specified position, the COUNTING signal is generated, enabling the Data Break

triggering.

Control logic to request a data break.

the VT8-E has highest priority, the MACO and MAC1 flip-flops in the Data

Break Control logic are set. The MAC0(1) and MAC1(1) signals gate the 15-bit starting address from the Starting

Address Register outputs onto the MAO-11 and EMAO-2 lines. At TP1 of the data break timing cycle, the MAC2
flip-flop in the

Data Break Control logic is set. The MAC1(1) signal then enables the Starting Address Control logic

to assert the CLK

ADD CNTR signal at TP4 time of the data break timing cycle. Thus, the address in the Starting

Address Register is counted up by one. The next data break timing cycle transfers the data word in the new address
to the VT8-E.

12.4.2.4

Data Break Counting Logic — The Data Break Counting

logic

shown

Figure

12-28. This logic

COUNTING signal that enables the Data Break Control logic to request data breaks. When the
PRESET BRK signal is generated, flip-flop E43A is set, asserting the COUNTING signal. The COUNTING signal
enables the NBR flip-flop in the Data Break Control logic to be set at INT STROBE time. If the VT8-E has highest
generates the

priority, data breaks begin.

assert the

Each TP1 signal of a data break timing cycle causes NAND gate E42 (Figure 12-28) to

COUNT BRK signal. This signal

counted by the 4-bit up-counter, E53. When the correct number of data

breaks has been performed, flip-flop E43A is cleared via NOR gate E33 and data breaks cease.

12-40

CLK ADD CNTR-

P/0 M8337

DATA11 L-

UP COUNT
Da
Qa

DATA 10 L-

MAR 11
MA11 L

MAR 10
Db

P10

E16

MA10 L

74193

DATA EN B LDATA 9 L1—O

O-y-c

4-BIT
UP CNTR
Dc
Qc

MAR 9

MACO (1)

E15

74174

DATA 8 L-

HEX
Do

F/F Qd

Dd
Qd
LOAD CARRY

DATA 7 LDa

UP COUNT
Qa

DATA 6 LQp

;Ey

MA8 L

;iH>

MA7 L

MAR 7

CLOCK

MA9 L

MAR 8

MAR 6
Dp

tE>-

— MA6

P— MA5 L

E12
74193

DATA

MAR 5

5 L

DATA 4 L
Dp
Qd
LOAD CARRY

MAR 4
E5 \>— MA4 L

E7
74174

UP COUNT

DATA 3 L
Da

DATA

MAR 3

Qb
E8
74 193

DATA

MAR

b— MA3 L

P— MA2 L

b— MAI L

P— MAO L

DATA

MAR 2

2 L

Dd
Qd
load carry

CLOCK

LD ST ADD

MAR
MAC1 (1)

UP COUNT
Da

E3
74175

Dq quad
F/F

E4
74193

Dd
LOAD

EMAR 2

:=Ey

EMAR

E2
1

EMA2 L

P— EMA1 L

EMAR
Qq

CLOCK

~"TT

LD X ST ADDLD ADD CNTR L-

NOTE:
Log.ic

P/O M8335 unless noted.

Figure 12-26

Starting Address Register Logic

12-41

Jf>—

EMAO L

+ 5V
DPLA L

+ 5V

DATA EN B L

DATA EN A L

E45>0-

LD ST ADD

TP3

tE>'

E44

LD XST ADD

DPGO L
INITIALIZE

7^>
+3V-

E56
MAI NT/

60
MAINT L

—
E54

DATA 10 L

GRAPH/ALPHAd)

E55
GRAPH/

ALPHA

GRAPH L

E46 (Q)
(V SYNC TIME)

E44

»— LD ADD CNTR L

P/0 M8337
TP4

^O
-#

MAC2(1)

ir>-H>-i
J
V^
1

NOTELogic

P/0

M8336 module unless noted.

Figure 12-27

Starting Address Register Control Logic

12-42

CLK ADD CNTR

;1(0)

—JE42\V- —
d(

E42 )0-»

COUNT BRK

L_f_ M8335

NOTES
1. Logic is

P/0 M8337 Module, unless noted,

W4 connected: 32 characters/line
W5 connected:64 characters/line

Figure 12-28

INITIALIZE

Data Break Control Logic

the logic has been programmed for an alphanumeric display (assume 32 characters/line), 32 data words must be

loaded into the Line Buffer Register during two scan lines of the character row. During each of the eight remaining
scan lines, the Line Buffer Register is recirculated. Thus, new information is loaded once every ten scan lines and the

PRESET BRK signal must be generated only once every ten scan lines.
Note that the logic within the dashed line in Figure 12-28 generates the PRESET BRK signal. The VSYNC L signal
prepares this logic for triggering by setting flip-flop E43B, thereby asserting the GO AFTER VSYNC signal (the
MAIINT L signal is negated by the Starting Address Control logic when a DPGO instruction is issued). VSYNC L also
clears the 4-bit up-counter and the two J-K flip-flops. When the

VZONE flip-flop

set,

NAND gate E7 is enabled.

Each E19 CARRY signal that occurs causes PRESET BRK to be generated. Because El 9 CARRY occurs once every
ten scan lines, the Line Buffer Register is loaded once every ten scan lines, as required.
Figure 12-29 illustrates the timing of the counting network for an alphanumeric display of 32 characters/line. This

timing applies to a graphic display, as well, although the GRAPH L signal would be asserted for such a display. If the
logic has been programmed for a graphic display, the PRESET BRK signal must be generated differently. Sixteen
data words are needed to display one line of graphic data. Thus, the Line Buffer Register can hold two lines of

graphic data. Since a line of graphic data is displayed by one scan line, a PRESET BRK signal is required once every

two scan lines. The logic in Figure 12-30 is used to genei-ate the Graphic mode PRESET BRK signal. It is similar to
the PRESET BRK logic in Figure 12-28, The VSYNC L signal is used in the same way and the data breaks are
counted by the counting logic in the same way. The LN CNT signal occurs at the end of each scan line, but the
E19-A signal is high for every other scan line. Consequently, the graphic PRESET BRK occurs once every two scan
lines.

12-43

SYNC L

PRESET BRK

COUNTING

E48B(0)

E48A(0)

TP1

(WHEN MAC (l)IS SET)

GRAPH L

E33A

Figure 12-29

Data Break Counting for 32 Characters/Line

E9-C

fn = An

Oo-^A

PRESET
BRK

°Bl E33

"^1

A2 8266

LINE CNT

0JB2

""3

"T
GRAPH/ALPHA (1)H
NOTE:
Logic

(HI
IS

P/0

FOR GRAPHIC SELECT A)

M8336 Module unless noted

Figure 12-30

PRESET BRK Generation Graphic IVIode

12.4.2.5 Data Break Controi Logic - The Data Break Control logic is shown in Figure 12-31. When the
COUNTING signal is asserted by the Data Break Counting logic, NAND gate E52 is enabled. (MAI NT L negated
by the DPGO instruction and HALT BRK L
asserted only for line-feed or end-of -screen.) The NBR flip-flop
set
at INT STROBE time, asserting the NBR (1) signal. This signal asserts OMNIBUS signals CPMA DISABLE L and
BRK IN PROG L and causes the VT8-E priority to be placed on the DATA lines during TS4. CPMA DISABLE L
causes the CPU CPMA Register to be disconnected from the OMNIBUS MA lines, while BRK IN PROG L ensures
that only data break devices place priority information on the DATA lines during TS4.
is

12-44

NBR(I)

I0T3MAINT L

CPMA DISABLE L

COUNTINGHALT BRK L
MAINT LINT

E52

STROBE

TS4 L -

'^D

MY PRIORITY L-

E46B

MACO

—

-^jr-n E28 j

—

BREAK CYCLE L

C
CT

MACO(O)

TP4

:E>

MACKD
E46A
MAC2(1)

MAC1

MA, MS

LOAD
CONT

MACKO)

E41B

MAC2
MAC2(0)

^
fp^D M8335

INITIALI2

'
I

NOTE:
Logic Is P/O

M8337 Module unless noted

Figure 12-31

Data Break Control Logic

the VT8- E has highest priority, IVIY PRIORITY L is asserted by the Priority logic (Figure 12-33). This signal is

NAMDed with the 0-output of the NBR flip-flop to produce a high logic level at the D-input of both the MACO and
MAC1 flip-flops; the flip-flops are set at TP4 time via NAND gate E28. The MAC0(1 signal asserts MS, R DISABLE
L, BREAK CYCLE L, and MD DIR L, and enables the MAC2 flip-flop to be set at TP1 time of the data break cycle,
thereby asserting MALC L. These OMNIBUS signals complete the CPU takeover process. MS, IR DISABLE L forces
the CPU to enter the Direct Memory Access (DMA) state and disables the CPU IR Register. The MALC L signal
prevents the CPMA Register from being clocked during the data break operation, while the BRK CYCLE L signal is
)

applied to the programmer's console and can be monitored on the display panel.

The MD DIR L signal is asserted so that the data word transferred during the data break timing cycle is rewritten in
the memory location during the write half of the memory timing cycle.

The MACI(O) signal is applied to NOR gate E42 to ensure that MACO and MAC1 can be cleared by TP4 whenever
NBR is cleared at INT STROBE time. The MAC1 and MAC2 outputs are used as gating signals elsewhere in the
Display logic.

12-45

Hi'

o
— o:
LUZ

O
LU

I
QQ

CM
CO
CN

+
c

1Sj

^ o - o -

^
->

12-46

o o- -

12.4.2.6

Data

Break

Halt,

Line

Feed,

and

End-of-Screen

Logic — The

Data

Break

Halt,

Line

Feed,

and

End-of-Screen logic is shown in Figure 12-32. This logic is used to clear the NBR flip-flop and stop Single Cycle Data
Breaks as follows:

the line feed ASCII code (012) is detected on the

MD lines, E47A sets. This clears NBR

the counter

has not overflowed and the Maintenance mode is not enabled.

If the Character Counter overflows

If the

when 64 or 32 characters are transferred, counting is negated.

EOS code is detected (Figure 12-7) and EOS CODE L is asserted.

V SYNC L is asserted at the end of the vertical scan.

If NBR is cleared by EOS CODE or LF CODE before the Character Counters have counted 64 or 32 characters, FIN
SHIFT (E51) sets. This allows the counters to continue counting until they overflow (read all Os) so that they will
contain a
count when the next data break is initiated. FIN SHIFT also allows BRK SHIFTS to be generated in
order to shift the line buffer data into the correct position. FIN SHIFT is clocked at each TP4 time and will clear at
the first TP4 time after COUNTING is negated.

I0T3

•

MAIN L is used to set NBR to cause one Single Cycle Data Break if the DPMB Maintenance instruction is

executed by the program.

12.4.2.7

Priority Logic

— The Priority logic

that connect to the OMNIBUS. Priority
sets the

shown in Figure 12-33. Similar logic is contained on all interfaces

checked during TS4 immediately following the INT STROBE signal that

NBR flip-flop.

The VT8-E can have priority 10, 11, or 12. The device having the lowest priority (12) asserts the DATA 11 L signal
is assigned. This priority causes the VT8-E to assert the DATA 10 L signal
during TS4 L (jumper W2 in the Data Break Control logic is connected). Jumpers PI and P9'must be connected in
the Priority logic. Because the DATA EN B L signal is asserted when NBR(1) is high, any data break device with a
higher priority can enable one of the NAND gates (the DATA EN A L signal is high throughout the priority check).
Thus, MY PRIORITY L is not asserted and VT8-E data breaks do not begin.
during TS4. Assume that priority 11

VT8-E is assigned priority 10, jumpers P10 and P9 are connected. Higher priority devices can assert any of
through 8, thereby preventing the VT8-E from beginning data breaks. However, any device with a
lower priority, 11 or 1 2, must wait until the VT8-E relinquishes control of the CPU.
If

the

DATA lines

12.4.2.8 Line Buffer Register and Control Signal Logic — The Line Buffer Register logic is shown in Figure 12-34.
The register comprises four DEC 2518 ICs (hex 32-bit Shift Registers) and is loaded from the MD lines during each

data break cycle

[MAC2 (0) is asserted low] by control signals generated in the Line Buffer Register Control logic

(Figures 12-35 and 12-36).

32 alphanumeric characters are to be displayed. Component Registers B1 and B2 are used as a 12 X 32-bit Shift
is loaded with the 32 ASCII-coded characters. If 64 characters must be displayed, the A1 and A2

Component Registers are also used as a 12 X 32-bit Shift Register. However, the two 12 X 32-bit registers are loaded
by word from the MD lines. Consequently, they function together as a 12 X 64-bit Shift Register.
If graphic data is displayed, the A and B Registers operate as two independent 12 X 32-bit Shift Registers. While one
is displaying two scan lines of data, the other is refreshing for the next two scan lines.

alternately, word

When the LD B L signal, for example, is asserted, the 12 X 32-bit B Register can be loaded from the MD lines. Data
gated to the LOAD inputs is shifted by the CLK B signal. When the LD B L signal is negated, the LOAD inputs are
disabled; the CLK B signal produces an end-around shift of the data that has been loaded.

12-47

DATA 11 L
DATA EN A L

DATA 10 L

DATA 9 L

DATA 8 L

DATA 7 L

DATA 6 L

DATA 5 L

DATA 4 L

DATA

bB>—[>-^^

3 L

MY PRIORITY L

DATA 2 L

DATA

NOTE:
Logic is P/0
unless noted.

M8335 module

TO OBTAIN

NRB

(

"|0-D>r[l>-LL'

DATA EN B L

Figure 12-33

CONNECT JUMPER

PRIORITY 12
PRIORITY 11

P9'.

PRIORITY 10

P9.

Pio'
P9; P10

P10

Priority Logic

Three DEC 74157 ICs (quad multiplexers) are included in the Line Buffer Register logic. The READ SELECT signal
controls the multiplexers, causing either the A^

inputs or the B ^

inputs to be gated to the f ^ outputs. The outputs

are transferred to the Video Buffer logic, alphanumeric or graphic, and converted to serial video information.

Figure 12-37 shows a timing diagram that illustrates how the Line Buffer Register and the multiplexer are controlled

when 32 alphanumeric characters are to be displayed. The timing shown is relative; pulse durations, gate widths, etc.,
may or may not be actual.

12-48

fp/o
'

MD11 L-

MD10 L-

M8335

=o
;zo

MD9 LMD8 L-

MD7 L-

:za3

LOAD

INPUTS
A1

HEX,32-BIT
SHIFT

;zO

E16

Ao
Fo

MD6 L-

A3 QUAD Fi
MULTIPLEXER
Bo 74157
F2

B2
F3
B3
SELECT

LOAD
INPUTS

2518

E15

Bo 74157
F2

MD5 L-

MD4 L-

.z3D
:^^D

SELECT

MD3
LOAD
INPUTS

MD2 L
MD1 L

MDO L

=o-

::=a3MD

2518

ENABLE L

A3 E14

74157

Bo
F2

MAC 2
(0)

B3
I

P/O

M8335

SELECT
I

82
2518

III

NOTE:

LD AL-

Logic is P/O M8337 Module unless Noted

LD B L-

CLK ACLK B-

READ
SELECT"

Figure 12-34

Line Buffer Register Logic

12-49

The period of time represented as ti is that period during which 32 data breaks are being performed (remember that
two scan lines are set aside for this purpose). During ti the Line Buffer Register must be loaded from the MD lines.
The Line Buffer Register Control logic (Figure 12-35) asserts the LD B L signal (the signal E19-D is low throughout
ti, keeping the VIS ZONE L signal high). Each data break cycle causes a data word to be gated to the B Register
LOAD inputs. The BRK SHIFT signal that occurs during TS3 L of the break cycle is gated through NAND gate
E37A, since the ALPHA CLK ALT is always cleared during a 32 character operation. This causes a CLK B signal to
be produced. When 32 data words have been loaded into the register, the COUNTING signal goes low and data
breaks cease (COUNTING goes low atTPI of the break cycle, while BRK SHIFT is asserted during TS3 L).

VIS

ZONE (DV ZONE (D-

ZONE L

E19-DMAINT/GO(UD

E26

^33 F,
A2 «266

E32

-0| B2

SHIFT LINE BUFFER

B3
D

SHIFT

JE30)

(1)H—°l

"^3

-tX

CLK AL

E38A

E37B»-*
AINT

-LD B L

BRK

E27

LD AL

OlB,

(2,3, OR 4 DECODED

INIT

BY E22
OCCUR BETWEEN EACH E17

L—a

—

CARRY IN VIS ZONE)
D

Bl E28 "^iP
.
8266
A2

]

NOTE:
1.

Is P/O M8336 Module
Connect jumper '32' for 32 Char/Line
Connect jumper '64' for 64 Char/Line

READ SELECT
SELECTS A)

Logic

"(LO

E38B

C
7

CLK B L

GRAPH/ALPHA (1)H_
(LO FOR ALPHANUMERIC)

^TL

Figure 12-35

Line Buffer Register Control Logic

Throughout each of the next eight scan lines, the Line Buffer Register must be shifted end-around. Period ta
represents the third scan line and the beginning of the fourth. The VIS ZONE L signal is asserted when HZONE(I)
goes high. The LD B L signal is negated, placing the register in the recirculating mode. During the time that VIS
ZONE L is low, the VT8-E timing generates 32 SHIFT LINE BUFFER signals. These signals enable NAND gate
E37A, thereby generating the CLK B signal. The register is shifted end-around by 32 CLK B signals. (Note that 31
CLK B signals are sufficient to shift all 32 characters through the multiplexer, but 32 are needed for the
recirculation.) Each time a character is placed on the register outputs, the multiplexer gates it to the ROM Character
logic (only the 6-bit ASCII code, bits 6-11, is gated to the ROM). There it is converted to serial video information
for display.

12-50

V SYNC L

PRESET BRK

E32

GRAPH
LOAD
ALTA/B

E33
^ 8266

LD A L

LD B L

^>^

\/.XLK A L

E18-CARRY

F»5.46MHz

TJH
B

3 7

-J.

CARRY

E31
COUNT 74161

LOAD
A

F=455KHz
H

E37

ZONE

V ZONE

;:;^i>
READ SELECT
(LO SELECTS A)

,CLK B L
FO >

BRK SHIFT-

-0 B 1

E36

A2 «266

B2
A3
B3 7

6RAPH/ALPHA(nH
(

FOR GRAPHIC)

(PIN 9 HI :Fn=An)
(PIN 9 LO! Fn=Bn)

NOTE;
Logic is P/0

M8336 Module

Figure 12-36

Line Buffer Register

The same operation is performed during each succeeding scan line. At the end of the tenth scan line, the character
line has been displayed. Another PRESET BRK signal is generated and 32 more characters are loaded into the Line'
Buffer Register. Note that as these next 32 characters are shifted into the register, the 32 displayed by the
just-completed character line are shifted out Because video is not enabled unless VIS ZONE L is low, there is no
danger of these earlier characters being displayed again.
Figure 12-38 shows a timing diagram that illustrates how the Line Buffer Register and the multiplexer are controlled

when 64 alphanumeric characters are loaded from the MD lines. Both the A and B Registers are used, providing 64
bits of storage space.

As the timing diagram illustrates, the A and B Registers are loaded alternately so that each

contains 32 characters when 64 data breaks have been completed. The registers are alternately recirculated during

each succeeding scan line (this timing is not shown, but is similar to that of Figure 12-37); when the characters have

been displayed, 64 new characters are shifted into the register.
Figure 12-36 shows the logic that controls the Line Buffer Register and the multiplexer during a graphic display.

Figure 12-39 shows a timing diagram that illustrates how the graphic data is transferred through the Line Buffer

Read Select changes every Graphic PRESET which corresponds to every other scan line within the
visible zone. When displaying Reg A, CLK A L is generated once for every 12 graphic dot positions that are
displayed. This shifts a new word to the output of the Shift Register. The word is then loaded into the Video Buffer
Register logic.

after the 12 bits of the previous word have been displayed.

Both the A and B Registers are used when graphic data is displayed. One register is loaded from the MD lines with 32
data words; simultaneously, the information in the other register is displayed.

12-51

PRESET BRK

-ff-

'\.

COUNTING

BRK SHIFT

-fj-

juuuuuuinnji

-ff-

SHIFT LINE

BUFFER

juuuinjuuuinjui

-ff-

juuinnnnnmi

ALPHA CLK ALT
A/B (1)

-ff-

-rff-

-if-

-J-f-

-fJ^

-rffi-

READ A/B (1)

READ SELECT

SELECT B

y>LD B L

RECIRCULATE 8

LOAD B
-ff-

CLK A
CLK B

ZONE (1)

VIS

ZONE L

juuumnnnnnM

juuuinnnnnn.
-/>

-y>-

-ff-ff-

Figure 12-37

Line Buffer Timing for 32 Character Line

-i}^

PRESET B

Ij"

-_Jl

-^fi-

-f^

COUNTI NO

BRK SHIFT

juuumnjuuuifui

—

JUU

.^'Sk'\^ J

LTLTLa

REAOA/e<„j

LTLrLn^/irLr

SELECT A
READ SELECT

l^^iJ^AfilJlJ^^nJL

LD A L.LD B L
-ff-

CLK A

CLK B

Figure 12-38

^f-

-rfJ-

V SYNC L

RECIRCULATE

JLJL_IUl_fLJL

JUUUiUUl
Line Buffer Timing for 64 Character Line

12-52

jummuuuuui

t1
t =

PRESET BRK

128.2/iS

2SCAN LINES

GRAPH LOAD ALT A/B (1)

LD A L

LOAD A

LD B L

RECIRCULATE B

BRK SHIFT

III

32 PULSES

RECIRCULATE A

T
32

„

aiL

455KHZ
PULSES

4V.

32 PULSES

READ SELECT
AL/B H
H ZONE (1 )

V ZONE (1)
16

455KHZ
32 PULSES

PULSES

CLK B

Figure 12-39

12,4.2.9

Line Buffer Timing

ROM Character Generator Logic - The ROIVI Character Generator logic

shown

Figure

12-40.

Included in the figure is a representation of the alphanumeric Video Buffer Register. The major components of the
character generator are three 23-XXA2 1024-bit read-only memories; each
locations.

A functional logic diagram of 23-XXA2

organized to provide 256 4-bit word

shown in Figure 12-41.

ASCII-coded characters are gated from the Line Buffer Register to each ROM on the six lines designated BIT 6-1 1.
The five most significant bits of the character, bits 6-10, are applied to a 1-of-32 decoder (Figure 12-41 ). The ROM
ROW CNT signals, generated in the VT8-E timing, are applied to 1-of-8 decoders. These three signals select one of
256 4-bit data words. The LSB of the ASCII character, bit 1 1, is used to gate the 4-bit word out of the ROM to the
Video Buffer Register, a DEC 7496 5-bit Shift Register. As Figure 12-40 shows, an odd ASCII character (bit 11 is
logic 1) causes the

ODD ROM outputs to be selected, while an even character causes the EVEN ROM to be selected.

The XTRA ROM provides the necessary fifth bit of the data word and is selected for both even and odd characters.

Remember that ten horizontal scan lines are required to display one character line. During the first two scans, the
characters are shifted into the Line Buffer Register. During each of the next eight scans, the Line Buffer Register is

ROM ROW CNT signals change during each
ROM LS ROW CNT the LSB. Consequently, eight

recirculated. Bits 6—1 1 of a character are the same during each scan. The

scan,

cycling through the counts OOO2

to III2, where

consecutive locations are selected for each ASCII character. The first location

video information that is ultimately displayed.

12-53

blank, the next seven contain the

ROM MS ROW CNT
ROM ROW CNT
ROM LS ROW CNT
BIT

NOTE:
Logic is P/0

Figure 12-40

M8337

Module

ROM Character Generation Logic

Consider the ASCII code for the character H: 001 000 (lOg). Bits 6-10 (001 00) are applied to the 1-of-32 decoder
during each scan. During Scan Line 3, the ROM ROW CNT signals are low (OOO2). The data in the addressed location

0000, and no video is displayed. During Scan Line 4, the ROM ROW CNT signals are 001 2. The data in this
location is 1000 and is displayed as video. Table 12-8 relates the eight scan lines, the ROM ROW CNT binary
is

representations, and the data in the addressed locations.

The fifth data bit for each scan is taken from the XTRA ROM. Note that only two outputs are available fronn this

ROM. If the character is even, the output at pin 1 1 is gated to the Video Buffer; if the character is odd, the output
12-9. The fifth data bit
is gated. This ROM is addressed exactly as is the EVEN ROM, as indicated in Table
for H is taken from pin 1 1 of the XTRA ROM. The result is shown below.

at pin 12

Scan Line

Data Bits Gated to

Video Buffer
3

00000

10001

11111

10001

NOTE: The pattern is generated for H.

12-54

BIT 6

BIT 7

BIT 8

BIT 9

BIT 10

ROM MS ROW CNT
ROM ROW CNT
ROM LS ROW CNT
BIT

1024- BIT MEMORY CELL

1-0F-32

32 X 32

DECODER

MEMORY MATRIX

1-0F-8
DECODER

1-0F-8

DECODER

11—f— 13

t;:^q
14

Figure 12-41

ROM Functional Logic Diagram

Table 12-8
Character H, EVEN ROM Data Bits

Scan Line

3
4
5
6
7

9
10

Bits 6-10

ROM ROW CNT Binary

Data Word in

Representation

Addressed Location

000

0000

001
Oil

1000
1000
1000

100

1111

101

1000
1000
1000

00100
00100
00100
00100
00100
00100
00100
00100

010

110
111

12-55

Table 12-9
Character H, XTRA ROM Data Bits
Bits 6-10

Scan Line

ROM ROW CNT Binary

Data Word in

Representation

Addressed Location

000

0000
0010
0010
0010
0010
0010
0010
0010

00100
00100
00100
00100
00100
00100
00100
00100

3
4
5

6
7

8
9
10

001

010
Oil

100
101

110
111

PIN 11

PIN 12

The pattern table for each ROM is included in Appendix A. To locate the pattern for an ASCII character, use the
following procedure:

Procedure

Step

the character is even, divide the 6-bit binary representation by 2. The result gives the 6

most significant bits of the location.
2

Find this location in the Octal Location column of the EVEN ROM pattern table (Table
A-1) for 4 of the data bits; find the same location in the Octal Location column of the

XTRA ROM pattern table (Table A-3) for the fifth data bit.
For example:

When the binary representation of character T, 010 100 (248), is divided

by 2, the result is 001 010 (128); octal locations 120-127 of the

EVEN and XTRA

ROMs contain the video information for the character.
3

the character

odd, take the even binary representation immediately preceding the

odd binary representation and divide by 2.
4

Find this location in the ODD and XTRA ROM pattern tables (Tables A-2 and A-3).

For example: To find the pattern for character G, 000 111 (078), divide 000 110 (OGs)

by 2; the result, 000 01 1 (038), identifies locations 030-037 as yielding G.

Alphanumeric Video Buffer Control Logic — Figure 12-42 shows the alphanumeric Video Buffer Control
logic. The logic generates the signals that allow the Video Buffer to convert the parallel ROM bits to serial
alphanumeric video bits. The logic is shown for 32 characters per line; if 64 characters per line are being displayed,
the input clock frequency is 10.92 MHz. Figure 12-43 shows a timing diagram for the 32 character per line
12.4.2.10

operation. Refer to both figures when reading the logic description.

The 5.46 MHz signal is gated by the logic to produce the LD ALPHA VIDEO BUFFER and CLK ALPHA VIDEO
BUFFER signals. The E17 up-counter provides the necessary gating signals. The A, B, and C outputs of E17 are
applied to the DEC 7442 BCD-to-Decimal Decoder, E22. When E22 decodes decimal 2, E26C is enabled and the
next clock produces a LD ALPHA VI DEO BUFFER signal. When E22 decodes decimal 3 through 7, E26B is enabled

12-56

and 5 clock pulses are gated through to produce CLK ALPHA VIDEO BUFFER. A VI D EN signal is also generated

when E22 decodes decimal 3 through 7. This signal is asserted through the E28 multiplexer when the VIS ZONE L
signal is low (note that the VIS ZONE L must be low for E22 to decode decimal 1 through 7).
Because E17 determines character rate, one LD ALPHA VIDEO BUFFER signal, one VID EN signal, and five CLK
ALPHA VID BUFFER signals are generated each time a character
shifted from the Line Buffer Register.
Remember that 32 SHIFT LINE BUFFER signals are used to recirculate the Line Buffer Register during each scan.
Each SHIFT LINE BUFFER signal generates a CLK B signal that shifts a different character to the ROM Character
Generator. The character generator produces five bits that represent the character. A LD ALPHA VIDEO BUFFER
is

signal then parallel loads these bits into the Video Buffer Register.

CLK ALPHA VIDEO BUFFER signals shift the data bits out of the buffer to the video logic. The VID EN
Note that the LD ALPHA VID BUFFER signal,
designated A in Figure 12-43, loads the character that is shifted from the Line Buffer Register by the CLK B signal
Five

signal enables the video logic to generate signals for the display.

designated A. While this character is being shifted from the Video Buffer, the new 5-bit character is being gated to
the buffer inputs. Note, also, that the character horizontal spacing is determined by the gating of the 5.46 MHz

The character width is represented by five clock pulses (0.185 inches for 32 characters/line); the horizontal
is
represented by the two clock pulses in each character period that are not gated (indicated by the
dotted-line CLK ALPHA VIDEO BUFFER pulses). Thus, the spacing is 40 percent of the character width, or 0.074
signal.

spacing

inches.

Figure 12-44 shows the timing of the alphanumeric Video Buffer Control logic for 64 characters per line. The logic is

the same as for 32 characters per line operation.

+ 3V

n.
CARRY
F=5.46 MHz
(32 CH/LINE)'

CLK

E17-7

74161

LD ALPHA VID BUFFER

E26B)

CLK ALPHA VID BUFFER

-VID EN

VIS ZONE L

note:
Logic Is P/0 M8336 Module

GRAPH/ALPHAd)
(LO FOR ALPHANUMERIC)

Figure 12-42

Alphanumeric Video Buffer

12-57

,45.8ns

—>\

5.46 MHz

—H

k- 183.15ns

E17 A

E17 B

E17C

CHARACTER RATE 780 KHz

kLPHA VID BUFFER 780 KHz

— —

— 549.45ns —

SHIFT LINE BUFFER

CLK B

(8-H)

D0T2 D0T3

|D(3T1

CLK ALPHA VID BUFF

1-1

i-i

D0T4

D0T5

CH SPACING

•"'•"'
II
II

11
II

ALPHA VID ENAB 780 KHz
1.28ps

Figure 12-43

12.4.2.11

8E-0652

Character Timing for a 32 Character Line

Graphic Video Buffer and Control Logic - The Graphic Video Buffer and Control logic

shown in

Figure 12-45. This logic converts the parallel data in the Line Buffer Register to the serial graphic video signals that
are applied to the Display Mode logic.

When a data word is shifted from the Line Buffer Register, it is applied to the Graphic Video Buffer on the lines
designated BIT

1—0. The Video Buffer Register comprises three DEC 7595 4-bit Shift Registers that can be parallel

loaded and serial shifted. The DEC 74161 counter, E31, counts down the 5.46 MHz clock pulses to produce an LD

GRAPH VID BUFFER signal at a frequency of 455 kHz. The derivation of this signal is shown in the timing diagram
in Figure 12-46. Graphic Video Buffer is loaded by CLK GRAPH VID BUFFER when LD GRAPH VID BUFFER is
true. This occurs every 12 clock pulses.

When the Video Buffer has been loaded, the LD GRAPH VID BUFFER signal goes low. The DEC 7495 Shift
Register cannot be shifted while this signal is high. The next eleven CLK GRAPH VID BUFFER signals shift data
(bit

pulses are available.

Twelve CLK GRAPH VID

dots. This occurs at

shifted out first).

Note that bit 11

out of the register

not shifted from the register since only 11 shift

BUFFER signals are also used to chop graphic video into distinct

AND gate E28.

12-58

11
I

12
I

'- - -« LRTLTLJiJiJiJTrTnjirLrirLru

L_r~Lj

E17 A

E17B

E17C

E17D
641ns
1.56 MHz

CHARACTER RATE

E12

E12-CARRY ,780 KHz|

LD ALPHA VID BUFF

SHIFT LINE BUFF

274ns-

CLK A
(780 KHz)
CLK B

READ SELECT (B-H,A-L)

rLTLTLrLTL

CLK ALPH VID BUFF

ALPHA VID EN

1
I

Figure 12-44

12.4.2.12

3
I

njuiTLn

5
I

Character Timing for a 64 Character Line

Visible Field Logic — When an alphanumeric character is to be displayed, the data word transferred to

the Line Buffer Register contains not only character information, but also information that controls the visible field

and the mode of display. The 12-bit data word is shown in Figure 12-47.

The ASCII-coded character is contained in bits 5—1 1. Because the VT8-E displays a 64 character set, only bits 6—1
are used to generate character video. Control bits 1 and 2 (referred to as CB1 and CB2) are used to determine the
visible field by selectively blanking the video display. Control bits 3 and 4 (referred to as CB3 and CB4) determine

how the video is displayed.
Figure 12-48 shows the visible field bits logic. These bits control the visible field as outlined in the table
accompanying the logic. When J-K flip-flop E44 is set, the BLANK L signal is asserted and the alphanumeric Video
Buffer output is inhibited (Figure 12-50 shows how the BLANK L signal inhibits video). Flip-flop E44 is controlled
in an intricate manner that can best be described by a timing diagram. This diagram is shown in Figure 12-49. The

timing begins with the start of a character line, represented by the PRESET BRK signal.

12-59

GRAPH VIS ZONE L
+ 3V

F = 5.46 MHz

E18-CARRY(LINE COUNT)

VID

Fn = An

NOTE:
Logic is P/0
unless noted

M8336 Module

NOTE:
Logic is P/0

M8336 Module unless noted.

Figure 12-45

Graphic Video Buffer Control Logic

Assume that a character in the previous character line had directed the beginning of a blank field; i.e., CB1 of this
character was high, while CB2 was low. When this character was shifted from the Line Buffer Register, the next LD

ALPHA VID BUFFER signal to occur sets the J-K flip-flop E50B (Figure 12-47). Each succeeding character either
a NOP direction or another BBF direction (both have the same result in the present situation). At the beginning of
the present character line, a PRESET BRK signal and a LINE CNT signal occur simultaneously. The leading edge of
the LINE CNT signal clears the E44 flip-flop, while the trailing edge of the PRESET BRK signal sets flip-flop E50A.
The next LINE CNT signal sets E44 again, because now E50A is set. All three flip-flops would remain in this state
is

throughout the entire character line and into and through each succeeding character line if no EBF direction were
received.

However, if an EBF direction is programmed into a data word, the blank field must be ended at the same point in
Scan Lines 3 through 10 (although nothing is displayed in Scan Line 3). Assume that character 16 of the present
character line directs an end to the blank field. The LD ALPHA VIDEO BUFFER signal corresponding to character

16 clears flip-flops E44 and E50B. For the rest of Scan Line 3, the BLANK L signal is negated. At the start of the
fourth scan

line, flip-flop

E44 has to be set again to blank the first 15 characters. The LINE CNT signal sets the

flip-flop,

thereby blanking the first 15 characters of Scan Line 4. Again, the sixteenth character says EBF and clears

flip-flop

E44 (flip-flop B stays clear throughout). This procedure continues until the character line is completed. The

second LINE CNT signal of the next character line clears flip-flop E44, which then remains clear until another BBF
or an EOS is directed.

12-60

GRAPH VIS ZONE H

5.46Mhz

CLK GRAPH VID BUFFER

njTTimnmnmriJTimnnr^
I"*'

^1^1 ^1^1® |'0MM121314

9|lo|ll|l2|l3|l4|l5

E31-A

iJijnjri_rirLririJxrLrLrLn

E31-B

L_r"L_i-L_r-L_r-L_r-L_r-L

E31-C

E31-D

LD GRAPH VID BUFFER

455Khz

SHIFT LINE BUFFER H

Graphic Word Timing

Figure 12-46

CB2

CB3

CB1

455Khz

LOAD

CB4

VISIBLE
FIELD

DISPLAY

BITS

T ASC11

MODE

Figure 12-47

12-Bit Data Word Format

When the 7-bit ASCII code for line feed (012) is detected, NAND gate El 1 is enabled, putting a high on the J input
LD ALPHA VID BUFFER signal corresponding to the character 012 sets E44, and the rest of
the character line is blanked. It would be contradictory to have the EBF control bits set for the line feed
character.
The K input of E44 should not be a 1 when the LF (012) character is detected.
of flip-flop E44. The

12.4.2.13

Display Mode Logic - The Display Mode logic is shown in Figure 12-50. These bits determine how the

alphanumeric video is displayed, as outlined in the table accompanying the logic.

When the character is to be displayed with normal intensity, the LD ALPHA VID BUFFER signal clears flip-flops
E27A and E27B. NAND gate E30B gates the serial output of the alphanumeric Video Buffer Register to NAND gate
E39. If the BLANK L signal is not asserted, the asserted ALPHA VID EN signal and the negated GRAPH L signal
gate the five data bits to the VIDEO line. If the character is to be displayed at increased intensity, E27A is set, while

NAND

E27B is cleared.
gate E34C is enabled, in addition to E30B. Inverters E29A and E29B have open-collector
outputs. For increased intensity, both gates are inactive. Consequently, the VIDEO output is approximately 5V. For
normal intensity E29B is active and there is a voltage drop in the neighborhood of 3.5V across the 1
Therefore the VIDEO output is approximately 3.5V.
12-61

k^ resistor.

LINE CNT

V SYNC L
LD ALPHA
VID BUFFER

BMD 5
BMD 6
BMD 7
BMD 9
BLANK L

BMD

TRUTH TABLE
J-K FLIP-FLOPS
Tn +

Tn
J

CB1

CB2

OPERATION

NOP

Q
On

EBF

CHARACTER AND THOSE FOLLOWING
BEGIN BLANK FIELD.FROM AND INCLUDING THIS CHARACTER. VISABLE FIELD CAN
BE STARTED LATER IN BUFFER BY EBF
END OF SCREEN. VISIBLE FIELD IS
ENDED BEFORE DISPLAYING THIS CHARACTER UNTIL NEXT VERTICAL RETRACE

1
1

BBF

Tn= bit time before clock
Tn + 1 'bit time after clock

DESCRIPTION
DISPLAY CHARACTER IN BIT 6-11 IF IN
VISIBLE ZONE
END BLANK FIELD.DISPLAY THIS

EOS

NOTE:
Logic is P/0

M8337 Module
Display Control Logic

Figure 12-48

E50A(1)

E50B(1)

PRESET BR

^JT

— _rL_rL_n
E44(1)

i_r'""L.j
CHARACTER
16

SAYS
EBF

Figure 12-49

BBF and EBF Timing

12-62

n_rL

CLK ALPHA VID BUFFERLOAD ALPHA
VID BUFFER

CLOCK

OUTPUT

E30cb

E39 )o

—*-

c|>
\y^

E34c)o

cr^>

ESOAJO-i

(•

E34bV>—

ALPHA
VID EN

E29B

CB3

NOP
1

NOTE:

Figure 12-50

BLINK

BRIGHT

Logic is P/O M8337 Module

DESCRIPTION

CB4 OPERATION

CURSR

DISPLAY CHARACTER AT NORMAL
INTENSITY

BLINK CHARACTER AT 1.875Hz RATE
DISPLAY CHARACTER AT INCREASED
INTENSITY
DISPLAY CHARACTER AS CURSOR

Display Mode Logic

A character is blinked at a 1.875 Hz rate when CBS is logic

and CB4 is logic 1. The 3.75 Hz signal clocks flip-flop

E32. The 0-output of the flip-flop alternately enables and disables NAND gate E30C, resulting in a VIDEO signal
that blinks at the desired rate. If CBS and CB4 are both logic 1, NAND gate ESOA is alternately enabled and disabled

by the S.75 Hz signal. NAND gate E30B is enabled by the character bit, while NAND gate ES4B is enabled by the
character's bit matrix complement. Thus, the character is displayed as a cursor.

12.4.2.14

Maintenance lOT Logic — The Maintenance lOT logic, shown in Figure 12-51, is enabled at TPS time if

the program executes the

DPSM instruction to set the MAINT/GO flip-flop {E56). Refer to Paragraph 12.S.4 for a

lOT instructions enabled when the VT8-E is in the Maintenance mode. These instructions allow
the registers and buffers in the VT8-E to be read into the AC. Data may also be transferred from memory using the
DPMB instruction. DPMB sets the BRK RQST flip-flop on the M83S7 module and the VT8-E executes one Single
Cycle Data Break to transfer data from the memory location determined by the Starting Address Register to the

description of the

Line Buffer.

12.4.2.15

Display Interrupt and Skip Logic — The Interrupt and Skip logic is shown in Figure 12-52. Interrupts are

in the AC is 1 when the DPGO instruction is executed by the program. This sets INT EN A and the
VT8-E makes an INT RQST when the Real Time Clock (RTC) flag sets at the start of a vertical retrace and signifies

enabled if bit 1 1

the end of the display frame.

The Skip Bus (SKIP L) is asserted at I/O PAUSE time of the DPCL instruction cycle to cause the program to skip
the next sequential instruction. The program may at this time switch modes (Alphanumeric/Graphic) without
disturbing the visible presentation.

12-63

INITIALIZE

^
MAINT/GOd)
E56
MAINT L

MAINT/

DPSM L

D >

TP3

E48C h-t

DPMB LD

-GRAPH/ALPHA (1

-I0T3- MAINT L

)

E55

GRAPH/
ALPHA

LD ADDR CNTR L

-GRAPH L

,^>I
LD XSTADD

DATA 11 L-

DATA EN A L

^D>-

-DATA EN B L

-CO L

DPMS

CI L

X BRK ADD RD EN

RD D BUFFER EN

NOTE:
Logic is P/0

M8336 Module

Figure 12-51

Maintenance lOT Logic

12.4.2.16 Bell Logic - The Bell logic is shown in Figure 12-53. BELL EN, a 74123 IC, outputs a 476 ms pulse
when the DPBL instruction is executed by the program to enable the 1.56 kHz signal from El 1—0 to be applied to
the bell. The volume of the tone is adjusted by potentiometer R25 on the M8336 module.

12.5

12.5.1

DISPLAY MONITOR CIRCUITS
Keyboard Logic

The keyboard (Drawing D-CS-301 01 66-0-0) provides the VT8-E output to the computer. There are 128 ASCII
characters or codes that can be generated by the keyboard. A 2-way slide switch is mounted on the Keyboard Logic
circuitry board to allow the

keyboard to be set for upper/lower case ASCII (128 codes) or lower case ASCII (96

codes) operation. Each key has a variable capacitance that is actuated when the key is pressed, causing an excitation
voltage to be applied to one side of the capacitor, generating base drive for the transistor amplifier. A sequential

scanning technique is used, employing a MOS integrated circuit that consists of an 8-bit and an 11-bit ring counter
(to compose an 8 X 11 matrix), and circuitry to sample the conductance of each transistor amplifier (one per key).
As the two (8-bit and 11 -bit) registers cycle, the 8-bit counter provides a collector voltage to as many as eleven of
the key output amplifiers. Up to eight of the transistor emitters are connected to each of the sensing circuits gated
by the 1 1-bit counter. The two sets of lines that form the 8 X 11 matrix are theoretically capable of sampling up to
88 keys.

12-64

+5V
DATA EN A

^:±r:iOfi

DATA 11 L

DPGO L

;t>-

INT
ENA

INT RQST L

^O'

TP3

TP4

SKIP L

RTC

—

^O—1>
JT D

DPCL L

E9-LD
(V

SYNC)

NOTE:
Logic

P/0 M8336 module.

Figure 12-52

Display Interrupt and Skip Logic

+ 5V
+ 5V

[^
TP3

7CM>

74123

BELL
EN

I>-H>-C>—^t-

DPBL
(1.56KHZ)

E11-D

NOTE:
Logic

P/0 M8336 module.

Figure 12-53

12-65

AUDIO

VOLUME A DJUST

Bell

Logic

The VT8-E uses the small 8-key keyboard as an extension of the main keyboard to generate cursor control codes to
position the cursor and to erase text. The keys used for cursor control or positioning are: cursor up (f ), cursor
down (I), cursor left K), cursor right (), and HOME. The erase-to-end-of-line (EOL) and erase-to-end-of-screen
(EOS) keys are used in conjunction with the LOCK key. The EOL and EOS codes will not be transmitted unless
they are used in conjunction with the LOCK key.

Motorola CRT Display

12.5.2

The following circuit descriptions refer to the detailed circuit schematic of the Motorola CRT Display Module shown
in

Drawing D-CS- 30 10326-0-3.

12.5.2.1

Video Amplifier - The Video Amplifier has four stages incorporating devices 01, 02, 03, and 04. The

01, functions as an emitter follower to provide a high impedance input with the 7512 terminating resistor
removed. The high impedance operation permits use of bridging connections to drive a number of monitors from the

first stage,

same signal source. The low output impedance of the first stage permits use of a low resistance contrast control
which furnishes flat video response over its entire range without the need for compensation. The collector output of
01 is used to drive the Sync Separator. C3 provides high frequency roll off to limit the collector output to the
band-width required to pass synchronization signals. 02 is a common emitter stage and is directly coupled to 04. 03

04 are connected in a cascade configuration. This common emitter/common base connection greatly reduces
the effect of Miller capacity compared with a conventional single transistor video output stage. C6 provides a ground

and

for video at the base of 03, the grounded base transistor of the video output cascade pair.

The video bias control (RIO) is used to set the quiescent collector voltage of 03, C5, C7, C8, and R15 for high
frequency compensation. Restoration of dc voltage is accomplished by setting the video bias control so that sync
tips,

which are negative-going at the collector of 03, just go into saturation. Variations

video drive result in

variations in the base current of 02 during sync time due to the low load reflected back when 03 is saturated. The

C4 will thus depend on the amplitude of output collector current during sync time. The result is a
clamping action which holds sync tips at the same level despite video signal variations. The Video Amplifier output is
charge on

direct coupled to the control grid of the CRT. R18 is used to isolate 03 from transients that may occur as a result of

CRT arcing.
Sync Separator - The Sync Separator uses a single stage, 05, to recover sync from the composite video
A single-stage Sync Separator adequate due to the high impedance of the following stages. The video input

12.5.2.2
signal,

to the Sync Separator is black positive. C1 1

is charged by the peak base current that flows when the positive peak of
the input takes 05 to saturation. This charge depends on the peak-to-peak input to 05 and thus makes the bias for

05 track the amplitude of the input signal. As a result, 05 amplifies only the positive peaks of the input signal. The
initial bias current through

R24 sets the clipping level.

12.5.2.3 Phase Detector — The Phase Detector uses two diodes in a key clamp circuit. Two inputs are required to
generate the required output, one from the Sync Separator and one from the horizontal deflection system. The
required output must be of the correct polarity and amplitude to correct phase differences between the input sync

and the horizontal time base. The horizontal collector pulse is integrated into a sawtooth by R45 and CI 5. During
sync time, both diodes in D7 conduct, shorting CI 5 to ground.

The sawtooth on CI 5 is thus clamped to ground at sync time. If the horizontal time base is in phase with the sync,
the sync pulse will occur when the sawtooth
(Figure 12-54).

is passing through its ac axis and the net charge on CI 5 will be
the horizontal time base is lagging the sync, the sawtooth on CI 5 will be clamped to ground at a

point negative from the ac axis. This will result in a positive dc charge on CI 6 (Figure 12-54). This is the correct
polarity to cause the Horizontal Oscillator to speed up to correct the phase lag.
Likewise, if the horizontal time base is leading the sync, the sawtooth on CI 5 will be clamped at a point positive
from its ac axis, resulting in a negative charge on CI 5. This is the required polarity to slow the horizontal oscillator
(Figure 12-54). R33, CI 7, CI 6, and R32 comprise the Phase Detector Filter. The bandpass of this filter is chosen to
correct the Horizontal Oscillator phase without ringing or hunting.

12-66

REFERENCE
•

inr
;^^^
:^^^

HORIZ.

SYNC
OSC ON FREQ
NO CORRECTION
VOLTAGE DEVELOPED

f__ OSC SLOW POS

CORRECTION VOLTAGE

FAST NEG
CORRECTION VOLTAGE
ry-s^- OSC

Figure 12-54

12.5.2.4

CRT Horizontal Oscillator Waveforms

Horizontal Oscillator - Q6 is employed in a modified type of Hartley oscillator. The operating frequency

of this oscillator is sensitive to its base input voltage. This permits control by the output of the Phase Detector and
also by the setting of the horizontal hold control. The horizontal hold range is set by adjusting the core of LI.

12.5.2.5

Pulse Shaper and Horizontal Drive - Q7

the Horizontal Driver.

Horizontal Driver.

used as a buffer stage between the Horizontal Oscillator and

provides isolation for the Horizontal Oscillator as well as a low impedance driver for the

R38 and C20 form a time constant which shapes the oscillator output to the required duty cycle

(approximately 50 percent), to drive the Horizontal Output circuitry. The Horizontal Driver stage, Q8, operates as a
switch to drive the Horizontal Output transistor through T1. Because of the low impedance drive and fast switching
times furnished by 07, very little power is dissipated in 08. C21 and R42 provide damping to suppress ringing of the

primary to T1 when 08 goes into cutoff.
12.5.2.6 Horizontal Output - The secondary of T1 provides the required low drive impedance for Q9. R44 and
C24 form a time constant for fast turn-off of the base of 09. 09 operates as a switch that, once each horizontal
period, connects the supply voltage across the parallel combination of the horizontal deflection

yoke and the

primary of T2. The required sawtooth of the deflection current through the horizontal yoke is formed by the L-R

time constant of the yoke and output transformer primary. The Horizontal Retrace pulse charges C27 through D2 to
provide operating voltage for G2 of the CRT. Momentary transients at the collector of 09, should they occur, are
limited to the voltage on C27, since D2 will conduct if the collector voltage exceeds this value.

The damper diode, D1, conducts during the period between retrace and turn-on of Q9. C28 is the retrace tuning
capacitor. C29 blocks dc from the deflection yoke. L3 is a magnetically-biased linearity coil that shapes deflection
current for optimum trace linearity. L4 is a series width control. C31 and R49, C42 and R68 are damping network
components for the linearity and width controls. C43D is charged through D5 developing the video supply voltage.

12.5.2.7

Vertical Oscillator Driver and Output - Sync from the collector of 05 is integrated by R26 and C35. 01

and Oil

are connected as a regenerative switch.

D3 until 01

The series combination of C37 and C38 charges through R58 and

turns on. This occurs when the emitter of 01

the base of Oil, turning that device on. When 01

exceeds its base voltage and causes current to flow into

and Oil conduct, C37 and C38 are discharged to nearly 0. O10

and Oil then shut off and the cycle repeats. The setting of the vertical hold control determines the repetition rate
of the charge and discharge of C37 and C38. The waveform generated is a positive-going ramp or sawtooth with a
fast retrace to 0. D3 provides a small incremental voltage above ground to overcome the forward base-emitter drop
of the two following stages.

012 is an emitter follower used to transform the high impedance drive sawtooth to a

low impedance drive for 013.

T3 matches the collector of 013 to the vertical yoke. When Q13 is cut off during Vertical Retrace, a high voltage
pulse is developed across the primary of T3. To limit this pulse to a safe value a varistor, R81, is connected across

12-67

the primary. R66 and C41 provide damping to shape the collector pulse so it may be used for retrace blanking. Since
the primary impedance of T3 decreases with current, the degree to which the primary shunts the reflected load

impedance varies with collector current. This would result in severe vertical non-linearity unless some compensation
is

employed.

Resistors
resistive,

R60 and R59 couple the emitter voltage of Q13 to the junction of C37 and C38. Since this path is
the waveform coupled back will be integrated into a parabola by C38. This results in a pre-distortion of the

drive sawtooth as shown in Figure 12-55. This is done to compensate for the non-linear charging of C37 and C38 and
the changing impedance of the primary of T3. An additional feedback path through R62 and C40 serves to optimize

the drive waveshape for best linearity.

PARABOLA
FROM EMITTER
OF Q24
EXISTING

VERTICAL SAWTOOTH
WITHOUT
VERT PARABOLA ADDED

PARABOLA PULSE AND
VERTICAL SAWTOOTH ADDED
TOGETHER, HENCE PRODUCING
THE REQUIRED VERT DRIVING SIGNAL

Figure 12-55

CRT Vertical Oscillator Waveforms

12.5.2.8 Retrace Blanking - Both Vertical and Horizontal Retrace blanking are provided by positive pulses applied
to the CRT cathode. The collector pulse from the Horizontal Output transistor is placed across R23 through R46.

The vertical

collector voltage

differentiated

by C30 to remove the sawtooth portion of the waveform. The

remaining pulse appears across R23. The mixed vertical and horizontal pulses on
cathode by CIO.
12.5.2.9

Power Supply — The regulated power supply

uses a series pass circuit.

R23 are coupled to the CRT

01 6 is the series pass transistor,

014 is the driver, and 015 is the reference amplifier. The output voltage of the regulator appears at the emitter of
016 and is fed into a voltage divider consisting of R71, R74, and R73. The voltage appearing on the arm of
potentiometer R74 is used as an error input to 015. R74 is thus used as the output voltage adjustment.
Zener diode D13 establishes a reference voltage at the emitter of 015. R72 establishes the minimum bias current for

D13 to ensure proper Zener operation.
The voltage at the arm of R74 is compared with the reference voltage at D13 by 015. If the voltage at the base of
015 increases due to an increase in input voltage to the power supply for example, 015 conducts more current. This
decreases the current available to the base of 014, so 014 and 01 6 conduct less current, resulting in less voltage at
the emitter of 016. In this manner, input voltage changes are reduced by the overall gain of the regulator, which is

R79 reduces the power dissipation in 016 by carrying some of the supply current. This does not impair
regulation over the operating range of the power supply due to the large amount of gain available.

quite high.

SECTIONS MAINTENANCE
12.6

INTRODUCTION

VT8-E maintenance theory is directed to the module replacement level. The maintenance effort is divided into two
basic categories:

preventive maintenance and corrective maintenance.

12-68

maintenance consists of routine periodic checl<s such

Preventive

as visual

inspections, standard maintenance

procedures that involve cleaning and lubricating, and diagnostic tests that expose possible weakening conditions to
allow corrective action to be taken, eliminating the causative factor(s) of possible failures.

maintenance consists of isolating the fault or problem and making necessary adjustments and/or

Corrective

replacements when a malfunction occurs. This involves the use of diagnostic routines prepared on paper tape and
designed to tcjst the functional units of the system. The procedures and techniques of periodic checking aid in fault
isolation.

Power requirements can be checked through the checkout procedures for power requirements contained in

Paragraph 12.2.2.

12.6.1

Equipment Required

Maintenance procedures for the VT8-E Video Display and Control require the standard equipment (or equivalent),
standard hand tools, and test probes listed in Table 12-10.

Table 12-10

Equipment Required
Equipment

Manufacturer

Designation

Multimeter

Triplett or Simpson

Oscilloscope

Tektronix

Probe

Tektronix

Model 630-NA or 620
Type 453
P6010

Recessed Tip

Tektronix

013-0090-00

Diagnostic Self-Test

Routines

12.6.2

Diagnostic Programming

The diagnostic

routines, supplied as paper tapes, are used to test the various

VT8-E functions and modules. A

complete description with instructions is provided with each tape.
12.6.3

Preventive Maintenance

Preventive maintenance consists of tasks performed periodically; its major purpose is to prevent failures caused by

minor damage or progressive deterioration due to aging. A preventive maintenance log book should be established
and necessary entries made according to a regular schedule. This data, compiled over an extended period of time, can
be very useful in anticipating possible component failures resulting in module replacement on a projected module or

component reliability basis.
Preventive maintenance tasks consist of mechanical and electrical checks. All maintenance schedules should be
established according to the environmental conditions at the particular installation site. Mechanical checks should be

performed

maintenance

often as required to allow the fan and
tasks

should

performed on

air

regular

filter

schedule

to function efficiently. All other preventive

determined

reliability

recommended schedule is every 600 operating hours or every four months, whichever occurs first.

12-69

requirements.

Mechanical Checks — Use the following procedure to perform a mechanical check on the equipment.

12.6.3.1

Procedure

Step

Unplug the VT8-E main power and remove the cover.

Clean the exterior with a clean cloth moistened in a mild detergent. Only a very soft cloth

should be used to avoid scratching the protective screen used on the face of the CRT.
Clean the interior using a vacuum cleaner and ensure that the cabinet air exhaust vents are
thoroughly clean and unobstructed to promote adequate cooling. Should the vents
become obstructed, premature component failure may occur due to an increase in the

VT8-E internal temperature.
4

Inspect

all

wiring and cables for cuts, breaks, fraying, deterioration, kinks, strain, and

mechanical security. Tape, solder, or replace any defective wiring or cable covering.
Inspect the following for mechancial security: jacks, connectors, keyboard, etc. Tighten

or replace as required.

Troubleshooting

12.6.4

12.6.4.1

System Troubleshooting - Begin troubleshooting by repeating the operation

which the malfunction

was initially observed, using the same program or function. Thoroughly check the program for proper settings and
determine if the fault is definitely located in the VT8-E.

the fault

isolated to the

VTB-E, but cannot be immediately

localized to a specific logic function, an effort

should be made to further isolate the fault to one of the VTB-E modules, e.g., keyboard,

M8335 module, CRT

module, etc. Some helpful aids during functional analysis are the VT8-E engineering drawings, circuit schematics,
timing diagrams, and the applicable VT8-E diagnostic programs.

Module Troubleshooting — Once the fault has been isolated to a specific module, carefully remove the
When the operability of the module is
verified, repair the faulty module or replace it with a module known to be operating properly and run the last
12.6.4.2

suspected module. Inspect the receptacle for wear or damaged contacts.

diagnostic program.

the system performs properly, return the system to an operating status and log an entry to

record all pertinent data concerning the fault or malfunction. When the individual defective part{s) within a module
is

located and repaired or replaced, the module should be verified by a validation test.

VTB-E Assembly/Disassembly — The following procedures are provided for removal, replacement, and
installation of the various VTB-E modular components. Special and cautionary notes contained within the
procedures afford special attention and should be adhered to. Only procedures for the removal of the VTB-E
12.6.4.3

modular components are provided; for installation, the procedures should be performed in their reverse order.
12.6.4.3.1

VTB-E Module Boards - The MB335, MB336, or M8337 module boards should be inserted straight into

the OMNIBUS, never at an angle. When inserting a module board be certain it is fully seated in the OMNIBUS.
12.6.4.3.2

Cover Removal — The VTB-E cover

secured with four Phillips-head screws. Screw locations are

midway on the two sides. The screws are inserted up through the lower casting and
into four cover-retaining brackets. To remove the cover, remove the four retaining screws and lift the cover off.

center-front, center-rear, and

NOTE
When the cover is removed, the 3-position interlock switch on
the left-hand side (viewing from the front) will go from the
fully depressed position (ON) to the middle position (OFF)
and must be pulled up to the third position (ON).

12-70

install

the cover, place the cover back on the lower casing, insert and tighten the four Phillips-head retaining

screws. The interlock switch should be in the fully depressed (ON) position.

12.6.4.3.3 VT8-E Keyboards Removal — The VT8-E contains two keyboards, a large teletypewriter-type keyboard,
and a small 8-key cursor control keyboard. The small keyboard is secured by four Phillips-head screws that are
inserted down through the four corners of the mounting board into the mounting bracket. The large keyboard is
secured by four Phillips-head screws that are inserted down through the keyboard mounting bracket. These four

screws should not be confused with the smaller and brighter Phillips-head screws that secure the keyboard to the

keyboard logic board. The smaller, brighter screws should not be removed.
Use the following procedure to remove the small keyboard:
Procedure

Step

Disconnect the ribbon cable from the small keyboard input connector.

Remove

the four

Phillips-head

retaining screws

from the four corners of the small

keyboard mounting board.
3

Slide the keyboard to the left and lift it out.

Use the following procedure to remove the large keyboard:
Procedure

Step

Disconnect the 44-pin Berg connector from the keyboard output connector.

Remove

the four, larger keyboard Phillips-head retaining screws from the keyboard

mounting bracket and remove the keyboard
12.6.4.3.4

CRT Removal - The CRT is secured to the VT8-E lower casting with four Phillips-head screws that are
and into the bottom four corners of the CRT chassis. Use the following

inserted through the bottom of the VT8-E

procedure to remove the CRT:

CAUTION
Protective goggles and

heavy gloves should be worn when

removing and/or carrying the CRT. Never grasp the CRT by
the neck, nor chip or scratch any part of the tube.

Procedure

Step

Press the interlock switch down to ensure main power is off.

Viewing the VT8-E from the front, locate (15-pin and 12-pin) Mate-N-Lok connectors PI
and P2 on the lower right-hand side of the CRT chassis and disconnect both connectors.
Locate and remove the four Phillips-head retaining screws on the bottom of the VT8-E,
used to secure the CRT chassis to the lower casting.

NOTE
Upon removal, the CRT should be placed face-down on a soft clean
cloth or pad.

Under no circumstances should the CRT be grasped by

the neck

Lift the

CRT out of the lower casing.
12-71

APPENDIX A

ROM PATTERN TABLES

Table A-1

ROM Pattern Table
(EVEN ROM)
Dieclmal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

000

0000

0111

031

1111

002
003

1000

24
25
26
27

030

001

032
033

1000
1000

1010

0111

034
035
036
037

1111

1000

28
29
30

004
005
006
007

010

0000

32
33
34
35

040

0000
1000
1000
1000

36
37
38
39

044
045
046
047

1111

3
4
5
6

1011

041

1000
1000
1000

Oil

1111

012
013

1000
1000
1111

014
015
016
017

020

050

0000

021

0000
1110

051

0011

022
023

1001

42
43

052
053

0001

024
025
026
027

1000
1000

44
45
46
47

054
055
056
057

0001

13
14

20
21

22
23

1000
1000
1111

1000

1001

1110

A-1

042
043

1000
1000
1000

0001

1001
1001

0110

Table A-1 (Cont)

ROM Pattern Table
(EVEN ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

48
49
50

060

0000
1000
1000
1000

84
85
86

124

126

127

0010
0010
0010
0010

1000
1000
1000

88
89
90

130

0000

131

1000

132

1111

133

1000
1000

0000
1000
1000
1100

134

93
94
95

135

136

061

125

062
063

52
53
54
55

064
065
066
067

56
57
58
59

070

074
075
076
077

1010

140

1001

141

1000
1000

98
99

142

0000
1000
1000

143

0101

100

0000

100

144

0010

101

1111

101

145

0101

102

1000
1000

102
103

146
147

1000
1000

104
105
106
107

150

0000

62
63

64
65
66
67

071

072
073

103

137

68
69
70

104

nil

105

107

1000
1000
1000

110

0000

73
74
75

111

1111

112

113

1000
1000

111

114

1111

115

1001

78
79

116

1000
1000

114

162

117

115

120

0000

121

1111

82
83

122

0010
0010

106

123

A-2

1000
1000
0101
0010

151

1111

152

0000

153

0001

108

154

109
110

155
156

0010
0100
1000

157

1111

112

160

113

161

163

0000
0000
1000
0100

116
117

164

0010

165

0001

118

166

119

167

0000
0000

Table A-1 (Cont)

ROM Pattern Table
(EVEN ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

120

170

0000

121

171

0111

172

123

173

1000
0000

234
235
236
237

0100
1010

122

156
157
158
159

124
125

174

160

240

0000

161

241

0001

126

176

162

242

127

177

0000
0000
0000
0000

163

243

0010
0100

164

166
167

244
245
246
247

0100
0100
0010

168

250

169

251

170

252
253

0000
0010
1010

175

128

200

129

201

130

202
203

0000
0000
0000
0000

133
134
135

204
205
206
207

0000
0000
0000
0000

131

132

165

171

1001

0110

0001

0111

136

210

0000

172

137

211

0101

138
139

212

0101

213

0101

173
174
175

140

214
215
216
217

0000
0000
0000
0000

176
177
178
179

260
262
263

0000
0000
0000
0000

144
145

220

0000
0010

180

146

222
223

0111

1000

182
183

264
265
266
267

0000
0010
0010
0100

141

142
143

147

148
149
150
151

152
153
154
155

221

224
225
226
227

230
231

232
233

181

254
255
256
257

261

1101

0111

1010
0010

0111

184

270

0000

185

271

1111

0010

186
187

272
273

0000
0000
0000
0000

0000
0100
1010

188
189
190

1010

191

274
275
276
277

0000
0000
0000
0010

A-3

Table A-1 (Cont)

ROM Pattern Table
(EVEN ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

192

300

0000

301

0111

341

0111

194

302
303

1001

224
225
226
227

340

193

342
343

1000
1000

1010
1100
1000
0111

228
229
230

344
345
346
347

0111

199

304
305
306
307

200

310

0000

311

0111

202
203

312
313

0000

232
233
234
235

350

201

352
353

0000
0000
0000
0010

204
205
206
207

314
315
316
317

0011

236
237
238
239

354
355
356
357

0000
0010
0000
0000

208
209
210

320

0000

240

360

0000

321

0001

241

361

0001

322
323

0011

211

242
243

362
363

0010
0100

212
213
214
215

324
325
326
327

1001

364
365
366
367

0100
0010

0001

244
245
246
247

216
217
218
219

330

0000
0011

332
333

0100
1000

248
249
250

370

331

220

334
335
336
337

1111

195
196
197
198

221

222
223

1000

231

1000

0100
1000
1111

0101

1111

0001

1000
1000
0111

A-4

351

371

251

372
373

252
253
254
255

374
375
376
377

1000
1000
0111

1000

0001

0000
0100
0010
0001

0000
0001

0010
0100

Table A-2

ROM Pattern Table
(ODD ROM)
Decimal
Loccition

Octal

Binary

Decimal

Octal

Binary

Data

Location

Data

Location

000

0000
0010

044
045
046
047

0010
0010
0010

0000
1000

002
003

0101

1000

36
37
38
39

1000

050

nil

051

1000

42
43

052
053

1001

004
005
006
007

010

0000

Oil

0111

012
013

1000
1000

054
055
056
057

1100
1010

44
45
46
47

1000
1000
1000
0111

48
49
50

060

0000

061

1000

062
063

1101

014
015
016
017

020

0000

021

1111

022
023

1000
1000

53
54
55

064
065
066
067

1010
1000
1000
1000

024
025
026
027

1111

070

0000

071

0111

1111

56
57
58
59

072
073

1000
1000

24
25
26
27

030

0000

031

0111

032
033

1000
1000

074
075
076
077

1000
1000
1000
0111

28
29
30

1000

0000

101

0111

1000
0111

64
65
66
67

100

102

034
035
036
037

1000
1000

040

0000

33
34
35

041

0111

042
043

0010
0010

3
4
5

13
14

20
21

22
23

001

1000

1000
1000

1011

68
69
70
71

A-5

103

0111

1010

1001

1000

1010

105

1000
1010

106
107

0110

104

1001

Table A-2 (Cont)

ROM Pattern Table
(ODD ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

110

0000

108

154

73
74

111

0111

155

112

156

1100
1100
1100

113

1000
1000

109
110
111

157

1111

0000

114

0111

112

160

115

1111

116

113
114

161

78
79

0000
1000

162

0001

117

0111

115

163

0001

0000
1000
1000
1000

116

164

0001

117

165

0001

118

166
167

0001

1000
1000
1000
0111

120

170

121

171

122

172

123

173

0000
0000
0000
0000

120

121

122

123

84
85
86
87

124
125

126
127

88
89
90

132

133

92
93
94
95

134

130

119

0000
1000
1000
1000

124

174

125

175

135

nil

126

176

0000
0000
0000

127

177

1111

1010
1010

128

200

129

201

136

1101

130

137

1000

131

202
203

0000
0010
0010
0010

96
97
98
99

140

132

142

0000
1000
1000

143

0101

135

204
205
206
207

0010
0010
0000
0010

100

144

101

145

102

146

103

147

0010
0010
0010
0010

136
137
138
139

131

141

133
134

104

150

0000

140

105

151

1111

141

106

152

142

107

153

1100
1100

143

A-6

210

0000

211

0101

212
213

0101

214
215
216
217

0101

1111

0101

Table A-2 (Cont)

ROM Pattern Table
(ODD ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

144

220

0000

180

0000
0000
0000

1111

145

221

1100

181

146
147

222

1100
0001

182

183

264
265
266
267

148
149
150

0010
0100

184

270

185

271

1001

186
187

272

0000
0000
0000

151

224
225
226
227

273

0001

152

230

188

191

274
275
276
277

0010
0100
1000
0000
0000
0010
Olio
0010

223

0001

153

231

154

232
233

0000
0010
0010
0010
0000
0000
0000
0000

192

300

193
194
195

301

159

234
235
236
237

160

240
241

162

242
243

0000
0100
0010

196

161

0010
0010
0010

0001

199

304
305
306
307

244
245
246
247

0001

200

310

0000

201

311

nil

0010
0100

202
203

312
313

0000

250

204
205
206
207

314
315
316
317

0011

252
253

0000
0000
0010
0010

254
255
256
257

1111

208
209
210

320

0000

0010
0010
0000

321

nil
1000

211

322
323

212
213
214
215

324
325
326
327

0000
0000

155
156
157

158

163
164
165

166
167

168
169
170
171

172

173
174
175

251

176
177

260

178
179

262
263

261

189

190

197

198

0001

0000
0000
0000
0000

A-7

302
303

0111

0001

0000
1000
0111

1111

1000
0111

Table A-2 (Cont)

ROM Pattern Table
(ODD ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

216
217
218

330

0000

236

331

1111

237

332
333

0000

238
239

354
355
356
357

0000
0010
0010
0100

334
335
336
337

0010
0100
0100
0100

0000
0000
0000

219

220
221

222
223
224
225
226
227

228
229
230
231

232
233
234
235

0001

240

360

241

361

242
243

362
363

244
245
246
247

364
365
366
367

0000
0000

370

0000

371

0111

0001

248
249
250

1110

251

372
373

0001

0000
0000
0000
0010

252
253
254
255

374
375
376
377

0010
0010
0000
0010

340

0000

341

0111

342
343

1000
1000

344
345
346
347

0111

350
351

352
353

0000

A-8

1111

0000
1111

1000

Table A-3

ROM Pattern Table
(XTRA ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

000

0000
0000
0010
0011

36
37
38
39

044
045
046
047

0010
0010
0010
0010

0011

050

0000

0011

051

0011

0001

004
005
006
007

42
43

052
053

0000
0000

010

Oil

0000
0000

012
013

0011

44
45
46
47

054
055
056
057

0000
0000
0000

0000
0010

060

0000

061

0001

0011

48
49
50

0000

062
063

0001

014
015
016
017

020

0000

021

022
023

0000
0010

53
54
55

064
065
066
067

0001

024
025
026
027

0010
0010
0000

070

071

0000
0010

58
59

072
073

0011
0011

24
25
26
27

030

0000
0010

032
033

0001

62
63

074
075
076
077

0011
0011
0011

28
29
30

034
035
036
037

0000

100

0001
0001

64
65
66

101

0000
0000

102

0011

0000

103

0011

040

0000
0010
0010
0010

68
69
70

104

0001

105
106
107

0001

2
3

4
5

13
14

18
19

20
21

22
23

32
33
34
35

001

002
003

031

041

042
043

0011

0010

0001

0000

A-9

0001

0001
0001
0011

0010

0000
0001

Table A-3 (Cont)

ROM Pattern Table
(XTRA ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

110
111

0000
0000

108

73
74

154
155

112

0011

110

156

0000
0000
0000

113

0010

111

157

0011

76
11
78
79

114

0000

112

160

0000

115

0001

113

161

0001

116
117

0011

114

0010

115

162
163

0001

120

0000

116

164

0001

121

0011

117

165

0001

82
83

122

0001

118

166

0011

123

0001

119

167

0001

124
125

0001

120

170

0001

121

171

126

0001

122

172

127

0000

123

173

0000
0000
0010
0000

130

0000

124

131

0011

125

174
175

132
133

0011

126

176

0000
0000
0000

0011

127

177

0001

84
85
86
87

88
89
90
91

109

0001

134

0011

128

200

93
94
95

135

0011

129

201

136
137

0001

130

0001

131

202
203

0000
0000
0000
0000

96
97
98
99

140

0000

132

141

0011

204
205
206
207

0000
0000
0000
0000

100

210

0000
0000
0000

142

0011

133
134

143

0000

135

144
145

136
137
138

102

146

103

147

0000
0000
0010
0010

104

150

0000

140

105

151

0011

141

106

152
153

0010
0000

142

101

107

139

143

A-10

211

212
213

214
215
216
217

0001

0000
0001

0000
0000

Table A-3 (Cont)

ROM Pattern Table
(XTRA ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Data

0000
0000

Lo(sation

Location

Data

Location

180

0001

144

220

0000
0000
0000

145

221

146

222
223

0011

183

264
265
266
267

184

270
271

0000
0000

148

185

0000
0010

186

272
273

0001

150

0000

151

224
225
226
227

0000
0000
0000
0000

152

230

153

231

154

191

274
275
276
277

232
233

0000
0000
0000
0000

192

300

193

301

194

302
303

0000
0000
0010
0010

158
159

234
235
236
237

0000
0010
0000
0010

199

304
305
306
307

0010
0010
0010
0000

200

310

201

202
203

181

182

187

188

189
190

195

147

149

155
156
157

0000

0001
0001

160

240

161

241

162
163

242
243

0000
0000
0000
0000

0000

164

311

0001

165

312
313

0011

166

0010

167

244
245
246
247

0000
0000
0000
0000

204
205
206
207

314
315
316
317

0000

0000
0000
0010
0000

208
209
210

196
197

198

168

250

0001

169

251

0001

170

0010

171

252
253

320

0000
0001

211

322
323

0000
0000

172
173
174
175

254
255
256
257

0011

321

212
213
214
215

324
325
326
327

0001
0011
0001
0000

176

260

177

261

178

262
263

0000
0000
0000
0000

179

A-11

0000
0010
0000

Table A-3 (Cont)

ROM Pattern Table
(XTRA ROM)
Decimal

Octal

Binary

Decimal

Octal

Binary

Location

Data

Location

Data

216
217
218
219

330

0000

331

0011

332
333

0001

236
237
238
239

354
355
356
357

0000
0000
0000
0000

334
335
336
337

0000
0010
0010
0000

240

360

241

361

242
243

362
363

0000
0000
0000

340

0000
0000

244
245
246
247

364
365
366
367

248
249
250

370

220
221

222
223
224
225
226
227
228
229
230
231

232
233
234
235

341

342
343
344
345
346
347

350
351

352
353

0000

0011
0011

0001

0011

371

0001

0000
0001

0000
0000
0000
0000

0010
0000

372
373

0001

251

0000
0000
0000
0000

252
253
254
255

374
375
376
377

0010
0000
0000
0000

A-12

0000

PDP-8/E MAINTENANCE MANUAL

VOLUME III
DEC-8E-HMM3A-C-D

HEADER'S COMMENTS

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^fame

Organization

Street

Department

City

State

Zip or Country

Fold Here

Do Not Tear Fold Here and Staple
-

FIRST CLASS
PERMIT NO. 33

MAYNARD,MASS.
BUSINESS REPLY MAIL

NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES
Postage will be paid by:

Digital Equipment Corporation

Technical Documentation Department

146 Main Street
Maynard, Massachusetts 01754

WORLD-WIDE SALES AND SERVICE

DIGITAL EQUIPMENT CORPORATION

MAIN OFFICE AND PLANT
Maynard Massachusetts

'J.S A. C'^SA '

Te-.ep!-'.

UNITED STATES
M1D-ATLA.«ITIC

NORTHEAST

(coitt)

6311 Kincston Pike, Suite 21E

TWX: y^O-SlA-Se-g

Telephone: (ei7)-89?-a320/0330

— SOUTHEAST

CENTRAL (cont)
WE&' ORLEANS

REGIONAL OFFICE
27t Wvman Street, Waitnam, Massacnusetts G2 54

WALTHAM

Ks^oxville.

Tennessee 37919

Telephone: (615)-688-6S71

T'.VX:

S10-583-C 123

3100 Hidgelake Dri ;, Suite
"0002
Metairie, Louisian
Telephone: S04-837-0257

Telephone: (61vS3M030

15 Liir.da Street, Walthatr, Massa^'nusetts 02154
P.YX; 710-324-6919

CENTRAL

CAMSR/DGE/BOSTON

REGIONAL OFFICE

REGIONAL OFFICE:

310 Soquel Way, Sunnyvale, California 94086

1850 Frontage Road, Northbrook, '.llinois 60062
TWX: 9'0-686-0655
Telephone: (312)-498-2500

Telephone: (40S)-735-9200

p;ttsburgh

801 E. Ball Road. Anaheim, California 92505
Telephone: (714)-776-6932/373a
TWX: 910-531-118

899 Main Street, CambritJge, Massachusetts 02139
TWX: 710-320-1167
Telephone: (617)-491-6I30

ROCHfSTER
IX Aliens Creek Road, Rochester, New York 1^618

400 Penn Center Boulevard
Pittsburgh, Pennsylvania 15235

TWX. 710-253-3078

Telephone: (716)-461-1700

CONNECTICUT
TWX:

71 0-461 -0C,=.4

— SOUTHEAST

MID-ATLANTIC

TWX: 510-685-2338

Telephone: (609)-452-2940

NEW rORK
95 Cedar Lane, Englewood.

New lersey 07631

TWX: 710-991-9721
NEW lERSEY

230 Huron View Boulevard, Ann Arbor, Michigan 481
TWX: 810-223-6053
Telephone: (313)-761-1150

1400 Terra Bella

PALO ALTO
TWX: 810-341-3436

LONG fSLAND
1
Huntington Quadrangle
Suite 1S07 Huntington Station, New York 11746
Telephone: (516)-694-4131, (212)-895-8095

Station Square Three, Paoli, Pennsylvania 19301
Telex: 510-668-8395

Telephone: (215)-647-4900/4410

WASHINGTON
Ex,'-utive Building
681, Kenilworth Ave,, Ri"erdale, Maryland 20840
TWX: 710-826-966:
Te'^phone: (30l)-779-1600/752-8797

DL'RHAM/CHAPEL HILL
2704 Chapel Hill Boulevard
Durhann, North Carolina 27707

TWX: 510-927-0912

Telephone: (919)-489-3347

ORLANDO
Suite 130, 7001 Lake Elle

!7^rlando, Florida 32809

TWX: 810-850-0180

(305)-851 -4450

;,_-

6303 Indian School Road. N.E.
Albuquerque, N.M. 87110
Telephone: (505)-29e-541 1 /5428

ST. LOUIS
Suite 110, 115 Prog
Pky., Maryland HeighlMissouri 63043
Telephone: (314)-878-4310
TWX: 910-764-OSJI

2305 South Colorado Blvd,, Suite #5
Denver, Colorado 80222
Telephone: (303)-757-3332/758-1656/758-1659

DAYTON

SEAULE

3101 Kettering Blvd., Dayton, Ohio 45439
Telephone: (513)-299-A377
TWX: 810-459..EiVi

Telephone: (2n 11-454-4058/455-5404

TWX: 810-757-4223

TWX: 910-989-0614

DENVER

TWX: 910-931-2650
1521 130th N.E.. Bellevue,

Washington 980O5

TWX: 910-443-2306

MILWAUKEE

SALT LAKE C.TY

8531 W. Capitol Dri^e, Milwaukse, WisconJn
Telephone: (414)-4e3 9110
TWX: 910-262-119

South 3rd East. Salt Lake City. ''ah 84111
Telephone: (801)-328-9838
TWX: 9;C-i<!!)-5834

DALLAS

4358 East Broadway Road

431

PHOENIX

^^^^ North Stemmons Freeway
Dallas, Texas 75247

Pho

TWX: 910-361-4000

TWX: 910-881-1651

Telephone: (713)-524-2961

Arij

TWX: 910-950^1691

Telephone: (602) 268-3488

3417 Milam Street, Suite A, Houston, Texas 77002

Telephone: (404H51 -3734/3735/3736

TWX: 910-366-7233

ALBUQUERQUE

Park Hill BIdg., 35104 Euclid Ave.
Willoughby, Ohio 44094
TWX: 810-427-2«08
Telephone: (216)-946-8484

HOUSTON

7350 Edgewater Drive
Oakland. California 94621
Telephone: (415)-635-5453/783a

CLEVELAND

Telephone: (214)-638^I880

ATLANTA
2815 Clearview Place, Suite 100,
Atlanta, Georgia 30340

"iWX: 910-576-2818

PHILADELPHIA

560 San Antonio Rd., Palo Alto, California 94306

OAKLAND

Suite 111, 8030 Cedar Avenue South,

Minneapolis, Minnesota 55420
Telephone: (ei2)-854-6562-3-4-5

U.S, Route 1
Princeton. New Jersey 08540
TWX: 5'C-685-2338
Telephone: C609) 452-2940

TWX: 910-335-123G

SAN FRANCISCO
Mountain View. California 94040
Telephone: (415)-964-e200
TWX: 910-373-1266

—

Beachway Drive
Suite
Indianapolis, Indiana 46224

MINNEAPOLIS

TWX: 710-987-8319

PRINCETON

SAN DIEGO
3444 Hgncnnk -Street
San Diego. California 92110
Telephone: (714)-298-0591. 0593

Telephone: (31 7)-243-8341

Telephone: (201)-335-3300

1510 Cotner Avenue, Los Angele
Telephone: (213)-479-3791/4318

ANN ARBOR

INDIANAPOLIS

Telephone: (201 )-871 -4984, (212)-594-6955. (212)-736-0447

Telephone:

CHICAGO
1850 Frontage Road, Northbrook, lliinois 60062
TvVX: 910-636-0655
Telephone: (3i2)-4S5-25G0

REGIONAL OFFICE:
U S. Route 1, Princeton, New lersey 08540

ANAHEIM

WEST LOS ANGELES

TWX: 710-797-3657

Telephone: (41 2)-243-9404

240 Pomeroy Ave., Merjden, Conn. 06450

Telephone: (203)-237-844i./7466

WEST

PORTLAND
Suite 168
5319 S.W. Canyon Court, Portland. Ore.- 97221
Telephone: (503) 297-3761/3765

INTERNATIONAL
EUROPEAN HEADQUARTERS

SWEDEN

Equipment Corporation International Europe
Route de 'Aire
1211 Geneva 26, Switzerland
Telephone: 42 79 50
Telex: 22 633

Digital

FRANCE

NORWAY
Digital

OSLO

fi)

•

Telex: 166 43

5 Koein,

Bismarckstrasse 7.
Telephone: 0221-522181
Telex: 888-2269
Telegram: Flip Chip KoeIn

140,

1620

230 Lakeshore Road East, Port Credit, Ontario
Telephone: (416)-274-1241
TWX: 610-492-4306

Copenhagen V

Lici";.!

Equipment Corporation S.A.

GENEVA

EDMONTON

Route de I'Aire

5531 - 103 Street
Edmonton, Alberta, Canada
Telephone: (403)-434-9333

Geneva 26, S.vitzerland
Teiep.ione: 42 79 50
Telex: 22 683
121'

FRANKFURT
6078 Neu-lsenburg 2
Am Forsthaus Gravenbruch 5-7
Telephone: 06102-5526
Telex: 41-76-82

ZURICH

TWX: 610-831-2248

VANCOUVER

Soheucrrerstrasse 21

Digital Equipn,ent of Canoda. Ltd.

HANNOVER

West 12th Avenue
Vancouver 9, British Columbia, Canada

2210

AUSTRIA
Digital

MONTREAL
9675 Cote de Llesse Road
Dorval,. Quebec, Canada 760
Telephone: 514-636-9393
TWX: 610-422-4124

SWITZERLAND
81

120 Holland Street, Ottawa 3, Ontario KlY 0X7
Telephone: (613)-725-2193
TWX; 610-562-8907

TORONTO

Equipment Corporation

Vesterbrogade

COLOGNE

Equipment Corporation

Ges.m.b.H

TWX: 6'0-929-2006

Telephone; (604)-736-5616

ITALY
Digital Equiprr

ARGENTINA

MILAN

BUENOS AIRES

VIENNA
Marlahilferstrasse 136. 1150 Vienna 15. Austria
Telephone: 85 51 86
.

UNITED KINGDOM
Digit-:l

U.K.

Jquipme.it

SPAIN

VENEZUELA

MADRID
Ltd.

12..Madrld 16

CARACAS

HEADQUARTERS

Arkv.r;:;ht Road, Reading, Berks.

Telephone: 0734-563555

Telex: 84327

Poi: 3L,iding, Tessa Road

BIRMINGHAM

Ingenieros S.A

Digital

Gandu.xer 76, Barcelo

Equipment Corporation Ttd.

CHILE
SANTIAGO

AUSTRALIA
Telex: j37 060

Digital

Equipment Australia Pty. Ltd,

Cable

'.Vilkcen,

)-B4l

Minchesler MIS Z'-.Z

EDINBURGH

JAPAN

P O, ;.;< ^V Crows Nest
N S v.'. Australia 3065
le.epnurie: 4ia-256d

LONDON

leiex;

TOKYO
AA2u/MJ

MELBOURNE
:;•.,,-.,•.,

P;,--.-

^"t,

-p>,.i.ps

It uo

Rkp
No

Lto

V r"

Telex: ,AA40Sll

NETHERLANDS

Tp »r-n

THE HAGUE

<»04.5«94B

PHILIPPINES
C

BRISBANE

BELGIUM
BRUSSELS

139 Meriv,3ie Street. South Brisbane
Q..,.iiri ::. Ijstralia 4'01
Telephone 444-047
Telex ,AA406ie

ADELAIDE
6 l,b-:trose

ohome

?4f

irent 1^0 DO a
* Hi^ fT "•o-i

3
If

070-E

(sales only)

h sh mbdsh

IB-

uk/o Jaoan
qn|,t^ Melbi^'imp

is:€-142

^ERTH

Telepho-^i

OGACHIL

'SYD.'.'E^

U.pet :--ec;',:t

Telephone

BARCELONA
At,:9io

READING
"fit: E.,::i:-i::c

Digital

8 Muenchen 13, Wallenstelnplatz 2
Telephone: 0B11-3S031
Telex: 524-226

Telephone: i0u44) 21 355 5501

OTTAWA

Telephone: 37 19 85, 37 02 30

COPENHAGEN

,».^ANCri£Sr£R

<
o
c
3

150 Rosamond Street. Carleton Place. Ontario
Telephone: (613)-257-2615
TWX: 610-561-1651

DENMARK
GmbH

Equipment of Canada. Ltd.

CANADIAN HEADQUARTERS

MUNICH

3 Hannover. Podbielskistrasse 102
Telephone: 0511-69-70-95
Tc's::; 922-952

3
Q>
3
C

Digital

Waldenmarthranesgate 84-6-86
Oslo
Norway

Equipment

Auckland, New Zealand
Telephone: 75-533

CANADA

Equipment

GRENOBLE

Digital

Ltd.

Hilton House. 430 ijueen Street. Box 2471 A,

PARJS

GERMANY

Equipment Corporatio

Vretenvagen 2, S-171 54 Solna, Sweden
Telephone: 98 13 90
Telex: 170 50
Cable: Digital Stockholm

Equipment Digital S.A.R.L

Auguste Ravler, F-38 Grenoble, France
Telephone: (76) 87 87 32
Telex: 32 882 F (Code 212)

Digital

AUCKLAND

327 Rue de Charenton, 75 Paris 12 ^K France
Telephone; 344-76-07
Telex: 21339
10 rue

3
O

NEW ZEALAND

Equipment Aktiebolag

STOCKHOLM

Avenue

-n

n
-f

Inte r
l»1l^h