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USER’S GUIDE.

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DEC—16-IMUGA-A-D

PDP16-M

USER’S GUIDE

digital equipment corporation maynard, massachusetts
-

lst Edition March 1973

The material in this manual is for informational

purposes and is

subject to change without notice.

The following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:

‘itsefiséil‘iiflifiilmmlmmlm.

‘

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

CONT ENTS

Page
CHAPTER 1

OVERVIEW

1.1

INTRODUCTION

................................

1.1.1

Functional Programming

1.1.2

Multiple Memory Features

1.2

1.2.1

1-1

..........................

1-1

MACHINE DESCRIPTION AND FEATURES

....................

1-2

..................

1-2

......................

1-3

1.2.3

Programmable Read-Only Memory (PROM)
Program Control Sequencer (PCS)
Register Transfer Module (RTM)

1.2.4

Modularity

1.2.2

1-1

..........................

.......................

1-3

................................

1-3

..................................

1-3

1.3

SOFTWARE

CHAPTER 2

A VIEW OF THE HARDWARE

2.1

FUNCTIONAL DESCRIPTION

2.2

PHYSICAL DESCRIPTION

2.3

SPECIFICATIONS

2.3.1

Processor

2.3.2

Mechanical

2.3.3

Electrical

2.3.4

Environmental

2.4

CONFIGURATION DATA

CHAPTER 3

INTERFACING

3.1

PARALLEL l/O DATA TRANSFERS

..........................

...........................

2-1
2-2

...............................

2-7

.................................

2-7

................................

..............................

...........................

2-9
210
2 10
2 10

.......................

3-1

..............................

3-2

3.1.1

GPI Interfacing

3.1.2

External Data Bus Interfacing

3.2

SERIAL l/O TRANSFERS

3.3

MUX AND FF l/C) INTERFACE

3.4

MUX AND FF I/O SLOT C19

3.5

GPII I/O SLOT 019

3.6

GP|2 I/O SLOT 020

3.7

GP|3 l/O SLOT D20

........................

............................

.........................

3-2
32
3-3

..........................

3-3

..............................

3-4

...............................

3—4

..............................

3-6

3.8

RTM DATA BUS SLOTS ABOI

3.9

PDP-11 PERIPHERAL INTERFACE CONNECTIONS

3.10

SI1 AND SI2 INTERFACE CONNECTIONS

3.11

INTERFACE CABLING

3.12

MANUAL/AUTO RUN OPTION

3.13

CONTINUE OPTION

CHAPTER 4

WRITING THE PROGRAM

4.1

—

A317

......................

................

3-6
3-7

...................

3—10

............................

3-12

........................

3-12

.............................

3‘12

......................

4-1

.............................

4-2

...............................

4-3

..............................

4-4

4.1.1

Arithmetic Group

4.1.2
4.1.3

Logical Group
Register Group

4.1.4

Constant Generator Group

4.1.5

I/O Group

4.1.6

Command Group

4.1.7

Test Group

.........................

................................

4-4
4-4

.............................

4-5

................................

4-6

CONTENTS (Cont)

Page
4.2

GOTO INSTRUCTION

4 3

IF INSTRUCTION

4.4

CALL AND EXIT INSTRUCTIONS

4.5

ASSEMBLER DIRECTIVES

.............................

...............

...............................

4-9

4.5.3
4.5.4

Assembler Initialization Code

.............................

................

Scratch Pad (SP) Option MS16-C
.

...................

4-12

4.6.5

Parallel l/O Option DB16-A

4-13

........................

......

4.6.6

PDP-11 Peripheral Interface Option DA16-F

4.6.7

Serial I/O Option DC16-A

4.6.8

Boolean Output Option KF L16

4.6.9

Boolean Input Option PCSIB-D

4.6.10

IF Instruction Option PCS16-D

.............

..........

4-16
4-16
4-17

.....................

........

4-18

............

4-19

................

4—19

......................

4-19

.............................

4.7.1

Read Paper Tape

4.7.2

Print Message on ASR 33

4.7.3

Multiply

.............

4-20

.............

.....................

4-14

...............

’

4-13

...................

Data Read/Write Memory Option M8160 and E

‘

4-10
.

4.6.4

4-9
4-10

Data PROM Option MR16-E

............

4.6.3

Constant Generator (K) Option MR16—D

SAMPLE PROGRAMS

....................

INSTRUCTION IMPLEMENTED THRU OPTIONS

4.6.1

4-7

4-8

Page Linkage Code
Source Program Segmentation

4.6

4-6

4-8

Comments

4.7

..............

...........................

4.5.2

4.6.2

........................

4.5.1

4-20

4-21

............................

CHAPTER 5

PROGRAM PREPARATION AND ASSEMBLY

5.1

BINARY LOADER

5.2

SYMBOLIC EDITOR

..............................

5.2.1

Writing a Program

5.2.2

Search Feature

5.2.3
5.2.4

Input/Output Control
Generating a Program Tape

5.2.5

Loading a Program Tape

................

.........

.........................

Restart Procedure

5.2.8

Summary of Special Keys and Commands
PAL16 ASSEMBLER

..........................

5.3.2

Pass 2

5.3.3

Assembling a Program
Error Messages

5-8
5-9
5-9

5-11

5-12

................

........................

5-3
5-7

5-11

............................

Pass 1

5-1

5-1 1

.............................

5.3.1

5-14

.......

5-14

..........................

5-17

..............................

UTILITY OPTION (TENTATIVE)

INSTALLATION

6.2

OPTION DESCRIPTION

6.3

OPERATIONAL DETAILS

..........................

6.3.1.1

Load

6.3.1.2

Modify

............................

Zero, Fetch, Load and Modify

................

5-14

................................

6.1

6.3.1

.................

Error Detection

CHAPTER 6

.......................

5.2.7

5.3.4

..............................

5.2.6

5.3

..............................

.......

6-1
6-2
6-3
6-5

................................

6-5

...............................

6-5

CONTENTS (Cont)

Page
Fetch

6.3.1.3
6.3.2

Simulate

6.3.3

Program

6.3.4

Check

6.3.5

Type

................................

6-6

...............

.........................

...........

APPENDIX A

PDP-1‘I PERIPHERAL SUMMARY

A.1

CONTROL AND STATUS REGISTERS

A.2

DATA REGISTERS

A.3

ASR 33 TELETYPE

A.4

PC11 HIGH SPEED READER PUNCH

LP11 LINE PRINTER

CR11 AND CM11 CARD READER

A.7

LA3O DECWRITER

A.8

AFC11 FLYING CAPACITOR

6-6

........................

6-7

A-1

..................

...................

A-1

...........................

A-I
A-3

............

A-4

...........................

A-4

...........

A-5

......................

.........................

A-6

.............................

A-7

A.9

UDC11 DIGITAL l/O

A.10

AA11-D D/A CONVERTER

A.11

ADOl-D A/D CONVERTER

APPENDIX B

ASCII AND EBCDIC Cll-IARACTER SET ENCODINGS

APPENDIX C

CONVERSION TABLES

APPENDIX D

INSTRUCTION SET

APPENDIX E

PDP16-M MACHINE CODES

APPENDIX F

DEFINITION TAPE LISTING

APPENDIX G

SIGNAL LISTINGS

APPENDIX H

USER OPTIONS

A-8

...................

A-9

.........................

ILLUSTRATIONS

Figure No.

Title

'Page

1-1

PDP16-M Simplified Block Diagram

2-1

PDP16—M Configuration

2-2

CPU Block Diagram

2-3

Logic Assembly Configuration Diagram
Logic Assembly l/O Slot Location
GPI Interfacing
External Data Bus Interfacing
PDP-‘Il Peripheral Interfacing
H803 Connector Block Pin Assignments
PDP-II Peripheral Interface Cabling Diagram

3-1
3-2
3-3
3-4
35

3-6

.....

1-2

.............................

2-3

...............................

2-4

....................

......................

........................

..............................

...........................

.............

...................

2-5
3-2
3-3
3-4
3-5

3-8

3-10

ILLUSTRATIONS (Cont)
'

Title

Figure No.

Page

SI Adapter Module M7333, TTY Connectors, and

3-7

Split Lug Identification

............................

3-8

Interface Cables

4-1

Address and Data Transfer Scheme

5-1

5-4

Loading the RIM Loader
Checking the RIM Loader
Loading the BIN Loader
Loading A Binary Tape Using BIN

5-5

Transition Between Editor Modes

5-6

Generating a Symbolic Tape Using Editor
Assembling with PAL16
Utility Computer Configuration
MR16-SL Utility Option

...............................

.......................

.............................

5-2
5-3

5-7

5-2

.............................

5-4

uuuuuuuuuuuuuuuuuuuuuuuuu

5-5
5-6

.....................

..........................

6-2

3-12
4-15

5-3

............................

6-1

3-11

.............................

5-10

5-18
6-2
6-4

TABLES
Title

Table No.
12-1

Module Slot Assignment and Description

2-2

Configuration Data

......................

..............................

3—1

MUX and FF I/O Slot C19

3-2

GPln" l/O Slot

23-3

RTM Data Bus Slots ABOI

3-4

H803 Connector Block Wirewrap Connections

Arithmetic Instruction Set

4-3

!5-1

RIM Loader Programs

5-1

95-2
‘5—4

Input/Output Control
Summary of Special Keys
Summary of Commands

‘5-5

PAL16 Assembler Switch Register Option

............................

.................................

—

AB17

........................

..............................

{5-3

...........................

............................

(3-1

PDP16-M I/O Slot Pin Assignments

G -2

PDP16-M RTM Data Bus Pin Assignments

PDP-11 UNIBUS Pin Assignments

.......................

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FOREWORD

All information necessary for interfacing,

programming, and debugging a PDP16-M is contained in this manual. The

manual contains six chapters and eight appendices.

Chapter 1 provides an overview of the PDP16-M. Applications, hardware features, and software are summarized.
Chapter 2 contains a brief description of the hardware. Functional and physical descriptions, specifications, and
configuration data are included.

Chapter 3 contains details for interfacing the PDP16-M with the outside world. All input and output signals, with
respective loading information, are identified. Specific details are included for interfacing with serial data
communication devices and low-speed POP-11 peripheral devices.
Chapter 4 covers the basic instruction set, assembler directives, and the instructions implemented through options.
The chapter details program formats and conventions, using many examples.

Chapter 5 describes how to prepare and assemble a PDP16-M control
Symbolic Editor, and the PAL16 Assembler are described in detail.
All features of the

program. The RIM and BIN

Loaders, the

utility option for the PDP16-M are discussed in Chapter 6. Detailed interface information is

included in this chapter to allow the user to interconnect his utility system.

Appendix A contains a summary of low speed PUP-11 peripheral devices. Their status control and data word formats
and addresses are specified. Option DA16-F permits the user to utilize low speed PDP-11 peripheral devices in a
PDP16—M system.

Appendix B lists the octal codes for the ASCII and EBCDIC character sets.
Appendix C contains various code conversion tables.

Appendix 0 lists the complete instruction set of the PDP16M. The list is ordered by classification.
Appendix E lists the complete instruction set of the PDP16-M. The list is ordered by octal machine code.
Appendix F is a listing of the definition tape used to initialize the PDP-16 Assembler.
Appendix G lists all PDP16-M and PDP-ll l/O signals. The lists are in alphabetic order.

Appendix H is a summary describing options available to the small and large users.

vii

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‘

CHAPTER 1

OVERVIEW

1.1

INTRODUCTION

The PDP16-M resembles both

a hard-wired controller and a general purpose minicomputer. It is similar to a
hard-wired controller because the program: is stored in a memory that is impervious to noise interference and process

sensors/controls can be easily interfaced. The PDP16-M also resembles a general purpose minicomputer because it
features arithmetic and data memory capability in addition to the logic and l/O

capability typical of a hard-wired
general, applications tend to be where a conventional minicomputer may be too costly and a
hard-wired design too time consuming. Some typical application areas for the PDP16-M are:
controller.

Machinery control, alarm scanning, data collection, monitoring, and remote telemetry in the industrial
field.

Fourier Analysis, auto and cross correlation, and waveform synthesis in the laboratory.

Input terminals for automated stock control, warehousing, and inventory control

in the commercial

market.
0

1.1.1

Data format conversion, code conversion,

complex arithmetic, and intelligent front-end processor to
larger computers in the data processing field.

Functional Programming

The PDPIG-M is

function-oriented minicomputer, with

simple design that novice computer users will quickly
It is termed a “function-oriented" computer because it

grasp and experienced computer users will

fully appreciate.
responds to a simple set of function reference instructions. The functions are specified by plain language statements
that are similar to those used in BASIC and FORTRAN programming languages. This makes the task of
programming the PDP16-M much easier than programming a conventional minicomputer. The functions
implemented in the PDP16—M include arithmetic, Boolean logic, data memory transfers, and l/O operations.
1.1.2

Multiple Memory Features

The PDP16-M features two segregated memories:

one

for control instruction storage and another for data storage.

This feature eliminates the need for direct memory reference instructions and the

programming complexities

associated with memory reference instructions that are inherent with conventional minicomputers.
The PDP16-M also uses an inexpensive,

state-of~the-art, programmable read-only memory (PROM) for program and

permanent data storage. PROMs are not susceptible to environmental noise, and their contents cannot be changed
inadvertently. Thus, they provide an ideal program and data storage medium for dedicated control applications in a
noisy environment. The use of PROMs in the PDP16-M also eliminates the need for expensive paper tape l/O

equipment or a computer console, required by computers that employ read/write program storage.

1-1

1.2

MACHINE DESCRIPTION AND FEATURES

Figure

1-1,

diagram of the PDP16-M, illustrates

block

simplified

some

the

main

features

the

PDP‘lG—M: segregated memory for instructions and data, arithmetic and logical capabilities offered by the ALU
(arithmetic and logic unit), and [/0 capabilities. The ALU, Data Memory, and HG channels are all interconnected via
a common

data highway called the Register Transfer Module (RTM) data bus. Notice that the instruction memory is

not connected to the bus. Function reference instructions are assigned 192 instruction codes for operating on data in

the ALU and for transferring data between the ALU, Data Memory, and WC channels. In addition, 64 instruction
codes

are

assigned

unconditional and conditional branch instructions and subroutine CALL and EXlT

instructions. These instructions operate only on the program control sequencer
program is stored in

application by

-—

not the RTM bus. The application

‘

PROM designated the instruction (control) memory. The program is written for a specific
using the simple PDPlG—M instruction set. All Boolean, arithmetic, and data transfer

the user,
in

functions found

other computers are available

in the PDP16-M. Functions like

AND, OR, exclusive-OR,

complement, shift, add, subtract, binary multiply, binary divide, move data, load data memory, read from data
memory, interrogate I/O devices, etc., can all be handled with ease in the PDP16—M. After the application program is
assembled and debugged, it is loaded into the PROM. The PROM can then be installed in its preassigned slot on the
PDPlB-M' logic assembly. After starting the program, the instructions are fetched and executed by the program
control sequencer one at a time without operator intervention. The instruction memory can be expanded from its
basic 256 words to 1024 words in 256-word increments, permitting the user to implement only the program

'4"

memory he needs.

”'3

ADDRESS

CENTRAL PROCESSING UNIT (CPU)

_?7::’:“°5“E§°%r
3

INSTRUCTION
MEMORY

(PROM)

£3?

>’“

INSTRUCTION

CONTROL

DATA

($23125

ROM'S FROM-é
ANc READ-WRlTE)

RTM

I/O
(BOOLEAN
PARALLEL
AND SERIAL)

Bus

____>

EXTERNAL
EQUiPMENT
.__.._.__

>
l6-OO7Z

Figure 14

1.2.1

PDPlSM Simplified Block Diagram

Programmable Read-Only Memory (PROM)

The PROM is an electrically programmable read-only memory. It contains 256 addressable 8-bit storage locations.

The PROM is housed in a 24-pin dual-in-line ceramic package with a quartz window that exposes the MOS chip. The
chip is a silocon gate matrix with switchable links. These links can be reset by exposing the chip to ultraviolet light.
After the links

are

reset, the PROM can be reprogrammed. The PROM may be reprogrammed a minimum of 100

times without affecting reliability.

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Program Control Sequencer (PCS)

1.2.2

The PCS fetches and executes the instructions

one at a time. It generates control signals in response to the
instruction code to Operate on data in the ALU and to transfer data between the ALU, Data Memory, and I/O
channels. The branch and subroutine instructions are executed by internal logic of the PCS.

1.2.3

The functional elements that are connected to the RTM bus are called

Register Transfer Modules because data can
by asserting the appropriate control inputs. Since a
functional element, when not accessing the bus, presents essentially no load to the RTM bus, the system can be
expanded to accommodate virtually an unlimited number of elements. The standard and optional functional
be transferred between the modules via the RTM bus simply

elements that are available for the PDP16-M include:

Arithmetic and Logic Unit

Data Memory

Scratchpad Registers
Constant ROMS
Data PROMs

Data Read-Write Memory
I/O Channels

Boolean l/O (TTL)

Serial l/O (TTY or TTL)
Parallel l/O (16-bit)
PDP-ll Peripheral l/O
1.2.4

Modularity

All components (modules and functional elements) of the PDP16—M are housed on a single prewired logic assembly.
The standard and optional components can be implemented simply by inserting the components in their preassigned
slot. Except for l/O interfacing, no other wiring is required.

1.3

SOFTWARE

An extensive software package is available for the PDP16-M. Software is available for:

Program development, including preparation and assembly.

Program debugging and loading.

Diagnostics for basic machine and all available options.

Program development, debugging, and loading must be done with the aid of a PDP-8/ E. For those customers who do
not have a PDP-8/E or do not wish to purchase one, Digital Equipment Corporation offers to load the Instruction
and Data Memory PROMs at a minimal cost. in this case, the user need only provide DEC with the source tape in
ASCII format. Refer to Appendix H.
The diagnostic programs are preloaded on PROMs. To run the diagnostics, the apprOpriate PROMs are inserted in the

instruction memory slots and the program is started by depressing the START switch on the console. If a failure
occurs, the diagnostic program will halt. Then, the diagnostic listing and optional maintenance modules may be used

quickly isolate the malfunction. The maintenance modules feature instruction and data readout displays, and
single step and breakpoint functions to aid in isolating the malfunction.

1-3

CHAPTER 2
A VIEW OF THE HARDWARE

The PDP16-M Maintenance Manual should be consulted by readers who are interested in specific hardware details.

2.1

FUNCTIONAL DESCRIPTION

The PDP16—M has an asychronous control (instruction) memory bus and an asychronous register transfer bus (Figure

2-1). Control PROMs connect to the control memory bus and all register transfer modules connect to the register
transfer bus. All data transfers on the control memory bus and register transfer bus are controlled by the CPU. The
CPU contains the instruction decoder, state generator, program counter, subroutine stack, arithmetic and logic unit,

LINK, A register, B register, and TR register (Figure 2-2).
The basic PDP16-M is equipped with one control PROM; three additional PROMs may be added to the memory bus.
The PROM has 256 8-bit storage locations.

When the PROM is addressed

by the program

counter

(PC) of the CPU, the word in that PROM location is

transferred to the CPU. Both the address and data are transferred via the memory bus. In the CPU, the control word
is decoded and executed. Only the LET instruction

(register transfer) operates on the register transfer bus. The bus

consists of 16 data lines and 5 control lines. All

transpire

over

arithmetic, logical, memory, and I/O register transfer operations
the bus. The GOTO and IF instructions simply cause the PC to be incremented to fetch the jump

address. The CALL/EXIT instructions operate on the hardware stack to store and retrieve the return address.

logical operations are implemented by instructions that operate on the ALU via the A, B, and
register serves as an argument register, and the
LlNK register facilitates carry manipulation. The TR register, which is byte and word addressable, can be used for
temporary storage or for data manipulation. The register transfer bus provides the data path for transferring the data
between these registers and any other register transfer modules that are connected to the bus. (Refer to Appendix D
for a list of all legal register transfer instructions.)

All arithmetic and

LINK registers. The A register can be used as an accumulator, the B

The basic PDP16-M is equipped With one Ill-word constant ROM and one parallel I/O, both of which are connected
to the bus. in

addition, the basic PDP16-lVl contains three flags/Boolean output channels and six Boolean input

channels. A wide variety of memory and l/O options can be added to the register transfer bus (Figure 2-1). These

options may be added to expand data/constant memory and l/O capabilities. ROMs are available for storing program
constants, data, or text information. Read/write MOS memories may be used for accumulating data for HO, and I/O
modules may be added to expand the interfacing capabilities. The standard data options that are available from DEC
are:

DATA MEMORY

Two 16 X 16 (16 words) Scratchpad Registers, MS16-C

Two Data R/W MOS Memories. Any of the following combinations can be implemented:

2-1

MS1'6-D

M31 6-E

Memory

(16 x 256)

(16 x 1024)

Size (words)

256

512

1024

1280

2048

One 16 X 24 Constant ROM, MR16-D

One 8 X 256 Data PROM (high or low order 8 bits), MR‘lS-E or 16 X 256 Data PROM, MR16-F

INPUT/OUTPUT
0

Two 16-bit Parallel l/O Channels, DBIG-A

Two Serial l/O Channels (TTY or TTL), DC16-A

One PDP-11

Boolean Input Channels I16), PCSIB—D

Flags/Boolean Output Channels (3). KFL16

Peripheral Interface, DAIG-F

The main frame of the PDP16—M is

prewired to accept any of the above options simply by inserting the Option

modules in the preassigned slot.
2.2

PHYSICAL DESCRIPTION

The PDPIG-M is packaged in a small table top or rack-mountable cabinet with a self-contained power supply, cooling

fans, an air filter, and a simple front panel.
Each slot of the logic assembly has been wired to accept only a specific module type.
CAUTION

Damage may result to the machine if an option is inserted into
the wrong slot.

Figure 2-3 and Table 2-1 illustrate the prewired configuration and describe each module of the PDPIG—M. The
corresponding model number for each module and Option is given in Table 2-1. Four additional optional modules are
available from DEC. These modules are designed to facilitate maintenance and program debugging. (Refer to Chapter
5 of the PDP16-M Maintenance Manual.)

2-2

"5}???

P0P“‘
l

.IIIII

PROM

CONTROL

MEMORY

CONTROL

8x256 CONTROL PROM PCSIG-B

OPTIONS
BUS
L

MEMORY OPTIONS

8X256 CONTROL PROM PCSIe-e

MEMORY

CONTROL

TRANSFER
REGISTER

DATA

CONTROL PCSIG—B

3x256 PROM

PERIPHERAL
AD R

DATA

DATA ”Rag‘E MR16-F

UMBUS “‘6":

CONS fi’EITQT ROM ”mew

BUS

Is-osa

MOS
DATA
R/w

stzse MSIG-D 16X1024 MSIG-E
OR

BO LGEAN PCSIG-D

MOS
DATA
R/w

stzs MSIG—D 16X1024 MSIS—E

SEIR/OAL ITY-TL) ADAPTER

OUT

FLAGS/ BO L KFL16

BUS

SCRATCHPAD
16x16 MSIe-C
SCRATCRPAD

16x16 MSIG-C

l/O

TRANSFER

OPTIONS REGISTER

SE35“ ITY-TL) INTERFACE

—_—_-—'_-_-"'-_-"'_"_‘-"\

0 ‘6-5

PARALEL DB‘s—A

DECODER

UNIT

FLAGS/ OUTBO L KFL16

PARALEL DB‘ST“

INSTRUCTION STATE PROGRAM STACK ARITH LINK REGISTER REGISTER REGISTER
A a

PARALEL DB‘G‘A

CONSTANT MR16_A

numbers
model

2-3

BASIC PDP16-M

2-1

Figure

16X4 ROM
(/1\I

L_____

CPU

CGENERATOR OUNTER LANDOGIC

BOLEAN ,NPUTS ”516-0

PDP16-M

8x256 CONTROL PROM PCSIG-B

Configuration
I

regIsIer

memoryond

I—

corespondmg

the
For

drawn g modules.
thIs
NOTE transfer
On

glvenIothe
are

BUS

CONTROL MEMORY

(DUHTIJUOD

umu’lbuN—O

STATE
GENERATOR

INSTRUCTION
DECODER

DEC EN

PROGRAM
COUNTER

CONTROL
REGISTER
TRANSFER
EN
REGISTER TRANSFER
TR

DECODER

RL'TRU

(EVOKE)

TEST
CONDITION

OPERATION

ARITHMETIC
AND
LOGIC UNIT

FLAGS

IF INSTRUCTION
TEST
MULTIPLEXER

<8lT>

B
REGISTER

(0.15)

OVF
OVF

BUS SENSE
AND

TERM

TRANSFER REGISTER
LOWER

UPPER

Figure 2-2

CPU Block Diagram

2—4

mummmmmmmm

HO -3

SLOT

1/0- 2

1/0 -1

SLOT

MUX

SLOT

PCS

M7336
‘

ADAPT

l/O SLOT

MUX.1 117.329

M7333’3‘AND M1307

CONT PROM3 M7327

MUXO

CONT PROMZ M7327

M7329

312 M7313

CONT PRDMi M7327 CONT PROMO M7327

3:1

DAT PROMi M7327

DAT PROM

M7313
'

DAT

PROM2 M7327

1N7 M7311

PDP-11 INT

M623:AND M1307

GP13

M7311

M1307

AND M1307

GP12

M7311

AND M1307

AND

M1307

GPll

M7311

M1307

AND

M1307

GPA

AND

com

12
11

M7300
H851

AND M1307

GPA REG M7301

AND M1103

L,PAGE,MUX M7306

(A818)

M7305
W

EVOKE

DEC 5

EVOKE

DEC 4 M73213

M7328

(51717-32)

EVOKE DEC) 3 M73213 (SP1-1st
EVOKE

DEC 2

M7328

EVOKE

01-:01

M7328

EVOKE

DEC 0

M7328

M7325

MEM2

M7319/M7324

Mew M7319/M7324 '_
V

'c M7307

5
'
"

SP1-131147313
31717-32

M72313.
1..

FFA-sM73‘Ds
SWCAB

M908

FF1-3

M7306

EVOKE

M7310

BUS SENSE AND TERM

M7332

16—0027

OPTIONS

Figure 22-3

Logic Assembly Configuration Diagram

Table 2-1
Module Slot Assignment and Description
Slot

Module No.

Model No.

Description

Configuration
How A
Test Slot

M7332

KBSiG-A

Basic

M7318

M3160

M7318

MS16-C

Option
Option

Timing Control, Data Testing, Bus Terminator
16-Bit Registers SP17 through SP32
16-Bit Registers SP1 through SP16

M7307

MR16-A

Basic

4-W0rd Constant Generator

M7319

M8160

MEM1

M7319

M8160

M7325

MR16-D

Option
Option
Option

M7305

MS16-A

Basic

16-Bit Register with Byte Control

M7301

KAR16

Basic

ALU and Registers A and B

M7300

KAC16

Basic

ALU Control Unit

M7311

DBilS—A

Basic

GP11

M7311

DB16-A

M7311

DB16-A

M7311

DB1l3-A

M7313

DC16—A

Option
Option
Option
Option

GP12

—

MEM2

—

256 X 16 R/W MOS Memory
256 X 16 R/W MOS Memory

24-Word Constant Generator

GP13

—

16-Bit 1/0 TTL Interface

16-Bit l/O TTL Interface
16-Bit 1/0 TTL Interface

lnterface for 8 or 16 X 246 Data PROM
S|1

Asynchronous Serial l/O interface

Table 21 (Cent)
Module Slot Assignment and Description

Description

Slot

Module No.

Model No.

Configuration

M7313

DC16—A

Option

Sl2

MUXO

M7329

PCSlG-D

Basic

M7329

PCS16—D

Option

Asynchronous Serial ”0 Interface
ln'put Multiplexer
MUX1
Input Multiplexer

M7336

PCS16-A

Basic

Processor Control

—

NOTE
The following variation is permitted for sockets A6 and A7.

M7324

MS16—E

M7324

MS16—E

Option
Option

MEM1
MEM2

—

1K X 16 R/W MOS Memory
1K X 16 R/W MOS Memory

Row B

Test Slot

Row C

M7310

KEV16

Basic

PAGEO and PAGEl Control

M7306

KFL16

Basic

FF1, FF2 and FF3

M7328

PCS16-C

Basic

Evoke Decoder 000—037
Evoke Decoder 040—077

M7328

PCS16-C

Basic

M7328

PCS16-C

Basic

Evoke Decoder 100—137

M7328

PCS16-C

M7328

PCSlG-C

Option
Option

SP1—SP16 Evoke Decoder 140—177

M7328

PCS16—C

Basic

Evoke Decoder 240—277

M7306

KFL16

Basic

Link, MUX Select, Page Select

M1307

KOR16—B

Basic

Control Logic

M1307

KOR16—B

Basic

Control Logic

M1307

KOR1SB

Basic

Control Logic

M1307

KOFl16-B

Basic

Control Logic

M1307

KOR16-B

Basic

Control Logic

M7327

MR16—FE

Option

8 X 246 Data PROM (lower 8 bits)

M7327

PCS16—B

Basic

Control PROM Loc 0000—0377

M7327

PCSlB-B

Option

Control PROM Loc 1000—1377

M1307

KOR16-A

Basic

Control Logic

VD Socket

Basic

Ale

SP17—SP32 Evoke Decoder 200—237

M
-

EXT1—EXT23, FF1—FF6, SI1, Sl2, MSYNC
and SSYNC

VD Socket

GPI2 HO and FF2

Basic

Row D

M908

Panel Socket

M706

KFL16

M1103

KOR16-A

Basic

Control Logic

1'0

M1307

KOR16—B

Basic

Control Logic

M1307

KORlG—B

Basic

Control Logic

Basic

Front Panel and Autostart (SWCAB)

Option

FF4, FF5 and FF6

2-6

49o

Table 2-1 (Cont)
Module Slot Assignment and Description
Module No.

Slot

Model No.

Description

Configuration
Row D

M1307

KOR16—B

Basic

Control Logic

M1307

KOR16-B

Basic

Control Logic

M623

DA16-F

M7327

MRlelE

M7327

PCSIB-B

M7327

PCSlG—B

M7333

Serial l/O interface Adapter

PDP-11 MSYNC and SSYNC interface

DC16—Ei

Option
Option
Option
Option
Option

VD Socket

Basic

GPll I/O and FF1

VD Socket

Basic

GPl3 l/O and FF3

2.3

2.3.1

8 X 256 Data PROM (upper 8 bits)

Control PROM Loc 0400—0777
Control PROM Loc 1400—1777

SPECIFICATIONS
Processor

Word Length

Control Program:

8 bits

Memory Address:

9 bits (10th bit is programmable)

Program Data:

16 bits

Memory

Programmed Instruction:

256-word

reprogrammable control

ROM

(PROM—expandable

1024 in 256-word increments

Program Data (Constants):

4-word diode ROM

expandable by 24 words and/or 256 8 or 16-bit

words

Auxiliary Data Storage:

256 to 2048 words of 16-bit read/write MOS memory

Control PROM

Type:

Electrically alterable quartz window ROM.

Organization:

256 8~bit words

Minimum Propagation Delay:

300 ns

Maximum Propagation Delay:

lus

Voltage Spec:

+5V i 5%

-9V :2 5%

2-7

Outputs:

1 TTL unit load drive: tri-state output or open collector drivers.

Address:

8-bit TTL address; internally decoded; 2 memory select inputs.

Programming:

The semiconductor PROM control memories are programmed by using
a

Scratchpad Register

special electrical interface. The quartz window PROM can be erased

with ultraviolet light and

reprogrammed at least 100 times.

expandable by 16-

(byte addressable)
registers.

Accumulators

1 (A)

Argument Register

—

32 word-addressable
‘

(B)

(/0 Channels

Flags (Boolean Outputs):

Boolean inputs:

Parallel:

——

—

expandable to 6
expandable to 22

(POP-11 Unibus compatible)

——

expandable by 2 TTL 16-bit data l/O

channels
NOTE
The

three

standard

flags

are

available

the channel

interface for 1/0 synchronization.

Serial:

2 (optional)

NOTE
The serial channels will accommodate baud rates of 110,

150, 300, 600, 1200, or 2400; one or two stop bits; and 5,
6, 7, or 8 data bits.

Instructions
Maximum Execution Time

Machine Code

LET:

2.4 us

0—2773

GOTO:

3.2 us

3008 and 3013

2 us if false

3023 ——3733

IF:

3.2 u 5 if true

CALL:

3.2 us

3743 and 3758

EXIT:

3.2 us

3763 or 3773

2-8

NOTE

The LET and EXIT instructions require one 8-bit memory
location each and the GOTO, IF, and CALL instructions
use

tWo 8-bit locations each,

one

for the

operation code

and the other for the jump address. The GOTO and IF
instructions are handled by the same logic with the

condition for the GOTO instruction always true.

Bus
Pin Assignments:

Bit

0
1

Bit

AA1 (L88)

AK1

A31

AL1

AC1

AMl

ADl

AN1

AE1

AP1

AF1

AR1

AH1

A81

AU1 (MSB)

(Slots A1 ——A1 7)

Control
Overflow

Voltage:

Current:

BA1

Power Clear

BB1

Data Accept

BC1

Done

801

Data Ready

BE1

Logic 1
Logic 0

0 to 0.4V

3.0 to 4.0V

Logic 1
Logic 0

24 to 31 mA with one terminator

1.5 to 4.0 mA

Mechanical

2.3.2

Chassis
Dimensions:

19X 13X 10.44 in.;48X 33X 26.5 cm

Fans:

Two fans exhaust from left side of cabinet. Filter is located on

right

side of cabinet.

Weight:

55 lb (approx); 25 kg

Mounting:

Chassis slides for rack

mounting in standard 19 in. cabinet. Without
slides, the cabinet may be used as a table top unit.

2-9

Front Panel
I

Run Light:

LED indicator is on when the program is running. It is turned off by
the HALT instruction.

Power Light:

LED indicator is on when +5V is available from internal power supply.

START Switch:

Initiates program execution

Panel Lock:

Disables the START switch.

2%
i

Electrical

2.3.3

PDP-16/MA: 115 Vac; 47—63 Hz; 2A maximum

Primary Power:

PDP-16/MB: 230 Vac; 47—63 Hz; 1A maximum
H740 Power Supply:

2.3.4

+5V @ 17A, -15 @ 2A

Environmental

Temperature:

0 to 60°C ambient

Relative Humidity:

95% maximum (without condensation)

Altitudes:

10K feet; 3000 meters

Vibration:

1 .896

R MS

overall

from

0—70

Hz.

Acceleration

density-0.029 Glez from 10-50 Hz with

spectral
approximate 8

dB/octave roll-off from 50 to 70 Hz.

2.4

CONFIGURATION DATA

The basic PDP16—M can be expanded simply by inserting the desired option into its preassigned slot. To

implement
options, some prerequisites to the basic machine are required. These prerequisites, the resident slot in the logic
assembly, the module number, the option number, and name and the purpose of each option are detailed in Table
some

2—2.

Table 2-2

Configuration Data

Purpose
increase storage for control
are

rarn to

512 words

Option

Module

Option Name

Model No.

No.

Slot

Control

PCS16—B

M7327

016

None

PCS16-B

M7327

CI 7

PCSl 6-B

in slot DIG

Prerequisite

PROM1

increase storage for control

Control

program to 768 words

FROM 2 or 3

D17

2-10

Table 2-2 (Cont)

Configuration Data

Purpose

Option Name

Option

Module

Model No.

No.

Slot

Prerequisite

NOTE
If only 768 words are implemented, it is desirable to insert the

third control PROM in slot D17

(thereby defining it as the

fourth PROM with the third PROM not implemented) to avoid

complicated page linking code (Paragraph 4.5.2).

Increase storage for control

Control

program to 1024 words

PROM 3

Increase storage for program

Constant

data (constants) from 4 to

Generator

28 words

(K)

Increase storage for program

Data PROM

data (constants) from 4 to

1 and Data

260 words

PROM 2

PCSl6-B

M7327

D17

PCS16B in slots
D16 and C17

MR16-D

M7325

A88

MR16—E

M7327

D15

None

DBlS-A in
slot AB15

MR16-E

M7327

C15

NOTE
Data PROM 1 and 2 must both be used (MR16—F) if 16-bit
data is required. If only 8-bit data is to be stored (such as
characters for

messages), then only one or the other need be
implemented. Both the constant generator (K) and the Data
PROMs can be implemented to extend data storage to 288

words.

Increase Scratchpad

Fast Registers

Registers from 1 to 17

(SP1 to 16)

M8160

M7318

AB4

PCSIG—C in
slot CDG

1 to 33

Fast Registers

MS16-C

M7318

AB3

(SP17 to 32)

PCSl6-C in
slot CD7

One scratchpad register, designated the transfer register (TR),
is implemented in the basic machine. If additional scratchpad

registers are required, either or both of the above options can
be implemented.

Add MOS Read/Write

MEM 1 and 2

Memory for Auxiliary
Data Storage
256 words

MEM 1

MS16-D

M7319

A86

None

Table 2-2 (Cont)

Configuration Data

Purpose

Option

Module

Option Name

Model No.

No.

MEM 2

MS16-D

Slot

Prerequisite

512 words

M7319

AB7

MS16-D in
slot ABS

1024 words

MEM 1

MS16-E

M7324

AB6

None

1280 words

MEM 2

MS16-D

M7319

A87

MS16—E in

slot A86
2048 words

MEM 2

MS16—E

M7324

AB7

MS16—E in
slot ABG

NOTE
MEM 2 can be implemented without MEM 1. The listing above
serves

only to illustrate what is required to expand the RM

memory from the minimum through all available sizes to the

maximum.

Expand Boolean inputs
(EXT) from 6 to 22;

MUX 1

PCS16-D

M7329

A319

None

test even bits of A

M
‘

using IF instruction

Expand flags from three

Flags FF4 to 6

KFL16

M7306

None

Add second Parallel l/O

GP|2

DB16-A

M7311

AB13

None

Add third Parallel l/O

GPIS

DB16—A

M7311

AB14

to six

DB16-A in
slot AB13

Add one serial l/O

Sl1

DC16-A

M7313

AB16

DC16-B

Add second serial l/O

S|2

DC16-A

M7313

AB16

DC16-B

Data PROM option interface

GPI

DB16-A

M7311

AB15

None

Decode EVOKES for SP1—16

EVOKE

PCSlB-C'

M7328

C06

None

Decoder

Decode EVOKES for SP17-—32

EVOKE

M
PCS16-C

Decoder

2-12

mmwmammmmmmm

‘

M7328

CD7

None

CHAPTER 3

INTERFACING

The PDP16-M

asynchronous 16-bit parallel transfer machine. Communication between the PDP16—M and

external equipment is accomplished via the following interface channels:

One Multiplexed (MUX) Input-Output Channel (TTL)
Two Serial Input-Output Channels (20-mA current loop or TTL)
Three Parallel 16—Bit input-Output Channels (TTL)

Interfacing the PDP16-M with the outside world is a user task; therefore, detailed planning is. required on the part of
user to ensure effective trouble-free interfacing. This chapter describes the PDP16-M input and output
characteristics. The user must be thoroughly familiar with these characteristics in planning his interface
requirements. Except for the optional serial l/O channel TTY current loops, all input and output signals are TTL
levels and are brought to pins of specific slots on the logic assembly (Figure 3-1). Cables are inserted in these slots to
bring the input and output signals to the outside world. All signals are high for assertion. Signals must be buffered

the

with

M-series modules if distances greater than 5 feet are to be driven or received by the interface slots.
are provided on the Si Adapter module to interface with serial l/O channel TTY current

Mate-N-Lok connectors

loops.
Because the PDP16~M has a limited number of l/O channels just like any other controller and computer, the user
must plan his interface carefully. if the interface is TTL compatible and the number of sensors, controls, and data

paths for a given application do not exceed the l/O capability of the PDP16-M, direct TTL compatible interface
connections may be made with only minimal planning for assigning the l/O signals to the l/O channels. However, if
the number of sensors, controls, and data paths exceed the l/O capability, additional interface components may have
to be designed or may have to be selected from the commercial market for concentrating (multiplexing) these
signals.
Digital Equipment Corporation has off-the-shelf PDP-11 peripheral devices for concentrating digital I/O, analog
inputs, and analog outputs. These devices may be interfaced directly with the PDP16-M if the DA16-F option is
implemented (Paragraph 3.9). For those applications that require other than TTL compatible signals, DEC offers A,
K, and M series modules that convert TTL. levels to accommodate most input or drive requirements.
After the interface configuration is firm, the user can start his programming effort.

3.1

PARALLEL l/O DATA TRANSFERS

Parallel

data transfers

configuration.

are

accomplished using the general

purpose interfaces

(GPls)

external data bus

PCS

M7336

‘

Mux1

M7329

st."

AND

M1307

Muxo

M7329

512

M7313

CONT PROM1M7327x CONT PROMO M7327*

311

M7313

«x-

DAT PROMl M7327

DAT pROMz M7327

DAT PROM INT M7311

pop-111m M623

AND M1307

131213

M7311

M1307

AND M1307

GPIZ

M7311

AND M1307

can

M7311

AND

M1307

AND

M1307

GPA

CONT

AND M1307

AND

M1307

GPA

REG M7301

CONTPROM3 M7327* CONT PROMZ M7327x

AND

M7300
H851

L,PAGE.MUX M7306

AND M1103

(Asia)

TR M7305

M7323

EVOKE

DEC 5

evoxe

DEC 4 M7326

MEM2

M7319/ M7324

MEMl

M7319/M7324

M7328

EVOKE

DEC 3 M7328

EVOKE

DEC 2

M7326

EVOKE

DEC1

M7328

SPl-16 M7318

EVOKE

DEC 0 M7323

5217-32

i=1=4 -6

M7306

M7318

a s M7332

evoxe M7310

CAB M908

* -OPTION

FFl-3

M7307

Isl/o SLOT
l6-OO49

Figure 34
3.1.1

Logic Assembly l/O Slot Location

GPl Interfacing

Sixteen bit data words may be transferred directly to or from the PDP16M via the three GPls by utilizing the l/O
commands GPl1=A, GPl2=A, A=GPI1, etc.

destination for l/O commands.

Register A in the arithmetic unit (GPA) is used as both a source and
Figure 3—2 shows a simple l/O interface where analog data is first addressed, then

strobed into the PDP16—M.

3.1.2

External Data Bus Interfacing

By implementing the external bus option (DAlG—F), an external asynchronous bus may be developed. In this
configuration the output half of SP” is normally used as an address register, the PDP16-M data bus is extended to
the external interface by cable, and the DA‘lG-F option is used to generate timing signals MSYN and SSYN. If both
input and output transfers are required, a program flag (FFl) can be used to denote input or output. Figure 3-3
shows the physical and electronic implementation of a gauging system where external counters are preloaded,
counted down by external pulse trains, and read back into the PDP16«M using the external bus configuration.
The external bus configuration can also be used to interface POP-11 peripherals which are not direct memory access
devices. Figure 3-4 shows an interface to the PC11 Paper-Tape Reader/Punch.
3.2

SERIAL l/O TRANSFERS

Two serial l/O interfaces may be implemented with the DC16-A options. The output of the DC16-A is 20 mil
current loop and TTL level compatible; 20' mil current loop outputs are available on
8-pin Mate-N-Lok connectors
on the 0016-8 Serial interface Adapter option. The TTL levels are available on the MUX and FF l/O
interface slot. These output: may be converted to ElA, current mode, or other required levels using M or K series

mounted

modules located on an external interface.

3-2

ADDRESS

A811
A/D

A162

MULTIPLEXER

CONVERTER

+ANALOGINPUT
CHANNELS

M38

START

16-0073

Figure 3-2
3.3

GPl Interfacing

MUX AND FF I/O INTERFACE

multiplexer and flip-flop l/O slot contains the output signals of the six programmable flags (FF1—FF6), the
I/O signals, MSYN, SSYN, and up to 22 Boolean input signals. The Boolean inputs are labelled
EXTl -EXT22. These signals normally represent the state of external flags or switches and must be TTL
compatible. These signals are referenced by the conditional branch instruction (IF statements) in the PDP16-M

The

four serial

software.

3.4

MUX AND FF ”0 SLOT C19

This slot provides the interface connections for the following signals:
a.

Boolean Inputs (EXT1—22)

Boolean Outputs (FF 1 —6)
Serial l/O Channel TTL Inputs

Serial l/O Channel TTL Outputs

UNIBUS signals
MSYN
SSYN
C1 (F F1)

Continue Signal

The pin assignments and TTL loading data is given in Table 3-1.

Any

one

of four standard cables can be used for

interfacing with the MUX and FF l/O slot. These cables are

described in Paragraph 3.11.

3-3

M105
ADDRESS
SELECTOR

M784 BUS RECEIVER

U /

COUNTER

COUNTER
PROBEI
COUNT

PROBEZ
COUNT

M7317
I

16-0074

Figure 3-3

3.5

External Data Bus Interfacing

GPI1 l/O SLOT D19

This slot provides the interface connections for the
a.

Input Data Line (IOU—~15)

Output Data Lines (DOD—15)

Boolean Output/ Flag (FF1)

following signals:

The pin assignments and TTL loading data are given in Table 3—2. Any one of four standard cables can be used for

Interfacing with the GPI1 I/O slot. These cables are described in Paragraph 3.11.
3.6

GPIZ l/O SLOT CZO

This slot provides the interface connections for the
a.

Input Data Lines (IOU—15)

Output Data Lines (DOD—15)

Boolean Output/ Flag (FF2l

following signals:

The pin assignments and TTL loading data are given in Table 3-2.
Any one of four standard cables can be used for

interfacing with the GPI2 slot. These cables are described in Paragraph 3.11.

3-4

FF1
7C1

EXTl

X33

8R4 (TAPE FLAG)

EXT2

8R5 (PUNCH FLAG)

I/O
SLOT

‘00

+3v

DO
7

A <oo>

A <01>

A <02>

DZ
.

POP16~M

$75

SLOT

ms
2

A (15>

PC11
PAPER
TAPE.
READER/PUNCH

A < 16>
A < 17>

RTM

03}: <

> D <oo:15>

DATA

SLOT

16-0075

Figure 3-4

PDP-11 Peripheral Interfacing
Table 3-1

MUX and FF ”0 Slot C19

Cable 1
Pin

Signal

TTL Loading

Ca_ble 2
TTL Loading
Signal

EXT 1

EXT 21

EXT 2

EXT 18

EXT 3

EXT 22

EXT 4

EXT 19

EXT 5

SI 1 SO (TTL)*

EXT 6

Sl 1Sl (TTL)*

EXT 7

31 2 SO (TTL)*

EXT 8

SI 2 SI (TTL)*

EXT 9

MSYN

EXT 1O

EXT 20

EXT 11

CONTlNUE

EXT 12

FF1

EXT 13

FF2

EXT 14

FF3

EXT 15

FF4

GROUND

FFS

EXT 16

FF6

EXT 17

SSYNC

'20 mil current loop (Tl'Y) interfacing connectors are on SI Adapter.

3-5

1
-

Table 3-2

GPln“ l/O Slot
Cable 1

Cable 2'!

Signal

TTL Loading

100

101

102

103

001

104

D02

Signal

TTL Loading

000

105

D03

106

004

107

005

l08

006

109

007

110

008

111

009

112

009

113

010

114

012

013

115

D14

FFn"

015

—-

-—

'n=1=slot 019

n=2=slot 020

n=3=slot 020

3.7

GP|3 l/O SLOT 020

This slot provides the interface connections for the following signals:
a.

Input Data Lines (IUD-15)

Output Data Lines (000-151

Boolean Output/Flag (FF3)

The pin assignments and TTL loading data are given in Table 3-2. Any one of four standard cables can be used for

interfacing with the GP13 l/O slot. These cables are described in Paragraph 3.11.
3.8

RTM DATA BUS SLOTS ABO‘I

—

AB17

These slots are interconnected to form the RTM data bus of the POP16—M.

Normally, these slots are occupied by the
register transfer modules (functional elements of the PDP16-Ml. However, when interfacing with devices that require

data bus extension, a vacant slot is used to establish that data path. The

pin assignments of the RTM data bus are

given in Table 3-3.
Any one of four standard cables can be used for interfacing with the HTM data bus. These cables are described in
Paragraph 3.11.

3-6

Table 3-3
RTM Data Bus Slots A301

Cable 1

AB17

Cable 2

Signal

Bit 00

Not Used

Bit 01

Not Used

Bit 02

Not Used

Bit 03

Not Used

Bit 04

Not Used

Bit 05

Not Used

Bit 06

Not Used

Bit 07

Not Used

Bit 08

Not Used

Bit 09

Not Used

Bit 10

Not Used

Bit 11

Not Used

Bit 12

Not Used

Bit 13

Not Used

Bit 14

Not Used

T1
U1

iBit 15

NOTE
BC02X or BCO3i-l cable must be inserted in row A, not row B,
of the specified slots. Row B carries the data bus interlocked

timing signals IDATA READY, DATA ACCEPT
OVERFI..OW, and POWER CLEAR.
3.9

DONE,

PDP-11 PERIPHERAL INTERFACE CONNECTIONS

The PDP16—M has been

prewired to interface with PDP-11 peripheral devices that do not need to become master

devices. Only accumulator type transfers can transpire between the PDP16—M and PDP-11 peripherals. One prewired

module slot, slot D14, is reserved on the logic assembly for installing the DA16-F option (module M623). This
module contains AND gate bus drivers for interfacing with the data transfer interlock signals of the PDP16-M and
the PUP-11 device. In addition to the M623 module, the following items are also required when connecting a PDP-11

device to a PDP16—M:

One H803 Connector Block

Three BC02X-05 or three BC03H-05 cables

One KTM16 Bus Terminator Option (M962)
NOTE
A BC11A Cable (preferably BC11A-02I is also required. This
cable is supplied with the PDP—11 peripheral device.

The control signals, the address, and the data required for operating a PDP-11 peripheral are distributed between
three slots on the PDP16-M logic assembly; three cables are, therefore, required. Since the pin assignments for the

various signals on the PDP16—M l/O slots do not match those of the PDP-11 device input slot, an H803 Connector

Block is employed to match the signals through wire wrapping. In addition, the H803 Connector Block is used to
provide ground and +3V to certain POP-11 device input lines. Figure 3—5 and Table 3-4 detail the pins on the
connector block to be wirewrapped.

3-7

‘OcomfltiiAOIC-monOra<0403020F090fl00m0~ —OCOmODOZOXOINOO><I—IOIOZOFit-O‘HCOWON aQCOMO'UOZOXOIOMCnch<oaomozfirocom00m'dm ‘ICOmO'DOZOXOIONOGOt'<.-<|.JU.Z.I_.C_.TI.O.W.N
”COUJC'OICXCICMOOP<.-4.JD.2.F.‘—.T|.U.W.N a0c0m0t0z0x010m00><Q—lO:n.z.r—.c.'n.o.m.m aOcOmOVOZOXOIOmOr-aop<o-romonr—ILO‘HOOUJON ‘0C.M.V.Z.x.l.m.fi.>(0-4QJDOZQFOLO‘nOImON
O

Figure 3—5

0 0 0‘ ID

H803 Connector Block Pin Assignments

After the H803 Connector Block is wirewrapped, the cables can be installed as shown in

Figure 3-6. The KTM16

bption must be installed in slot A03 of H803 to terminate the data bus.
M

NOTE
A

POP-11

peripheral interface option, the UNIBUS
converter [/0 interface module, will be available in the near
future. This option will simplify the interfacing procedure.
new

Table 3-4
H803 Connector Block Wirewrap Connections
PDP16-M

PDP-1 1

Signal

Name

From

Name

+5V

*AOJ A2

A04A2

BO4A2

+5V

GND

*AO‘I C2

A0402

A04C2

AO4T1

G ND

3-8

‘

Table 3-4 (Cont)
H803 Connector Block Wirewrap Connections
PUP-11

PDP16-M

Signal

Signal
Name

GND

From

*A01T1

From

A04T1

Name

GND

A04T1

BO4C2

BO4T1

GND

+5V

*BO1A2

BO4A2

+5V

GND

*80102
*BO1T1

80402

GND

GND
+5V

A01A2

AO3A2

A03A2

A0302

+5V

BO1A2

GND

A0102

GND

30102

GND

A01T1

GND

B01T1

DATA BIT 00

A01A1

A03A1

DATA BIT 01

A0181

DATA BIT 02

BO4T1

GND

BO3A2

+5V

BO3A2

+5V

80302

GND

80302

GND

BO3T1

GND

803T1

GND

A03A1

A0401

D00

A0381

A03B1

A04D2

D01

A0101

A03C1

A04D1

002

DATA BIT 03

A01 D1

A03D1

A04E2

D03

DATA BIT 04

A01 E1

A03E1

A04E1

D04

DATA BIT 05

A01I:1

A03F1

A04F1

A04F2

D05

DATA BIT 06

A01 H1

A03H1

A04H1

A04F1

D06

DATA BIT 07

A01.”

A03J1

A04H2

D07

DATA BIT 08

A01 K1

A03K1

A04H1

D08

DATA BIT 09

A01L1

A03L1

A04J2

DOQ

DATA BIT 10

A01M1

A03M1

A04J1

D10

DATA BIT 11

A01N1

A03N1

A04K2

D11

DATA BIT 12

A01P1

A03F1

A04K1

D12

DATA BIT 13

A01R1

A03H1

A04L2

D13

DATA BIT 14

A0131

A0331

A0381

A04L1

D14

DATA BIT 15

A01 U1

A03U1

A04M2

D15

A03T1

+3V

BOSA1

BO4F1

AC LO

+3V

BO3B1

BO4F2

DC LO

D00

301132

1304142

A00

001

B0102

BO4H1

A01

D02

801 E2

BO4J2

A02

003

B01152

1304.11

A03

D04

801 H2

BO4K2

A04

D05

BO1J2

BO4K1

A05

BO1 K2

BO4L2

A06

801 L2

BO4L1

A07

801 M2

BO4M2

A08

009

BO1N2

BO4M1

A09

D10

BO1P2

BO4N2

A10

D11

BO1R2

BO4N1

A11

D12

80182

BO4P2

A12

D13

BO1T2

BO4P1

A13

D14

BO1U2

BO4R2

A14

D15

BO1V2

BO4R1

A15

D06

D07

D08

3-9

Table 3-4 (Cont)
H803 Connector Block Wirewrap Connections

PDP-11

PDP16—M

Signal

Signal
To

From

Name

From

GND

BO4T1

B0482

GND

80482

B0481

A17

+3V

803C1

BO4U2

A16

MSYN

BOZKZ

80301

BO4V1

MSYN

SSYN

B02V2

BO3E1

303E1

BO4U1

SSYN

FF1

B02N2

B04T2

GND

B02T1

BO4T1

GND

“Use 933 Bus Strips for these connections (power and ground). For all other connections use 24 AWG Bus Wire.

KTMIG

THREE
30023

A303

30033
CABLES

"34

302

019

BCIIA
CABLE

A301
THRU
A317

A304

301

019

A301

A01

POP-11

H803

PDPIG-M

PERIPHERAL
16- 0067

Figure 3-6

3.10

PDP-l 1 Peripheral Interface Cabling Diagram

SI‘I AND 812 INTERFACE CONNECTIONS

I/O channel options are equipped to be interfaced with ‘ITL or TTY compatible signals. The TTL
compatible input and output connections are made available at the MUX and FF I/O slot (Paragraph 3.4). The TTY
20 mil current loop connections are made available through Mate-N—Lok connectors on the SI Adapter module. The
standard teletype cable that comes with the asynchronous device can be connected directly to the Mate-N-Lok
The serial

connectors.

3-10

Three prewired module slots are reserved on the PDP16-M

logic assembly for implementing the serial l/O channels.

They are:
Slot:

Module

A816

M7313

AB‘I7

M7313

Sl2

D18

M7333

Sl Adapter

Name

Sll

The M7333 SI

Adapter Module contains a set of split lugs and a Mate-N-Lok connector for each channel (Figure
3-7). The split lugs facilitate jumper installation for selecting the desired bit stream format. The number of DATA
bits, STOP bits and channel baud rate can be selected to complement the terminal device. Use the following chart

for installing the required jumpers.

Stop Bits

‘l

Yes

Data Bits

NB1

Yes

N32

Yes

Baud Rate

110

150

300

600

110

Yes

150

1200

2400

Yes

300

Yes

600

Yes

1200

Yes

2400

Yes

511
STOPAND

BAUD RATE
SPLW LUGS

cgfieTcTT‘oR

3:36:16 51333

SIZ
STOP AND
DATA BIT
SPLFTLUGS

SIlTTY
CONNECTOR

Figure 3-7

SI Adapter Module M7333, TTY Connectors, and

Split Lug Identification
3-11

The Mate-N-Lok connector is the TTY 20 mil current loop interface connector for interfacing with the terminal
device. TTL compatible serial I/O connections are made available on the MUX and FF l/O slot (C19).
3.11

INTERFACE CABLING

There are four different types of standard cables available for interfacing the outside world with the PDP16—M TTL

l/O signals of the MUX and FF I/O and GPI I/O slots (Figure 3-8); two are FIexprint®~type cables and two are
ribbon—type cables.
CABLE I (la WIRES)
M908

iii)
flfl
M908

CABLE 2 (18 WIRES)

M908

BCOEX

CABLE 1 (l8 WIRES)
CABLE 2 ()8 WIRES)
BCO4W

RIBBON

CABLES

CABLE I (I8 WIRES)

M901

CABLE 2 (18 WIRES)

M90,

BCOBH

CABLE 1 (18 WIRES)

M901

CABLE 2 (l8 WIRES)

BCO4T

FLEXPRINT CABLES
IS-OOBO

Figure 3-8

Interface Gables

The ribbon cables are easier to work with and have a low resistance which is suitable for long lines. The Flexprint
cables require

special tool for stripping the wires. There are two types of ribbon and Flexprint cables: One is

terminated with a single-height module at each end; the other is terminated with a single-height module at only one:
end. The type required by a given user depends entirely on the application.
3.12

MANUAL/AUTO RUN OPTION

Two methods for

starting the PDPIG-M program are available to the user: manual and automatic. in the manual

mode, the user must press the START switch on the console; in the auto mode, the program is automatically started
when the machine is turned on locally or remotely. The auto mode can be selected by the user simply by installing a
jumper wire between pins 31 and U1 on slot D01. If this jumper wire is not installed, the program must be started
manually.

3.1 3

CONTINUE OPTION

The HALT instruction can be used in the program to stop the program based on the outcome of a test or some other

signal, which is available at the MUX and FF l/O slot, provides the control for
continuing the program from where the program halted. A logic 0 (low) on the continue line will restart the
program. Depressing the START switch will always cause the program to start at location 000 of the page where the
condition. The CONTINUE

halt occurred.

Flexprint is a registered trademark of Sanders Associates, Inc.

3-12

CHAPTER 4
WRITING THE PROGRAM

The PDP16-M program is stored in a solid state,

reprogrammable, read-onIy-memory (PROM). The basic memory

module is 8 bits by 256 words. Up to four of these modules can be implemented in the PDP16-M. A special utility

option (MRIBSL) is required for loading the PROM with the object code (Chapter 6). The object code (punched on
a paper tape) is produced by assembling the source program on a PDP-8/E using the PALIG Assembler. A PDP-8/E
based Symbolic Editor provides the means for preparing the source program on-line and punching the ASCII source
paper tape. Besides loading the PROM, the utility Option permits the user to simulate and verify his program. The
simulate function allows the user to exercise his control program for debugging purposes before loading the PROM.
Once a PROM is loaded, the verify function can be used to check the contents of the PROM. The source program
must be written in PAL16 Assembly language. This chapter describes the language in detail.
Five classes of instructions have been implemented for the PDP16«M. They are:

4.1

Transfer (LET)

Unconditional Branch (GOTCI)

Conditional Branch (IF)

Jump to Subroutine (CALL)

Return from Subroutine (EXIT)

-—

The register transfer instruction is used to

specify arithmetic, logical, data transfer, HO, and control operations.
Seventy unique register transfer instructions have been implemented in the basic PDP16—M. The general format of
the instruction follows:

LET register get register-operation/comment
For example:

LET A

A+1/INCREMENT A

The word LET is optional. If used, a space must appear between LET and A=A+1.

4-1

4.1.1

Arithmetic Group
'

The following arithmetic operations can be performed on the contents of the A and B registers:

B/2

A+1
A—1

A+B
A-B

A/2
AX2
Two's complement arithmetic is used for the add and subtract operations. The symbols/ and X specify right and left

respectively. Shifting a register one bit to the right causes the contents of the register to be divided
by
Shifting the register one bit to the left multiplies the contents by two. Notice that the B register is equipped
with
the right shift (/I operation. The result from the specified arithmetic operation can be transferred to either
only
the A or the B register. For example:
shift operations,
two.

A=A+B
B=A+B
Carries (overflow) from arithmetic

operations can be saved. For any arithmetic instruction described above, the

overflow (‘l or 0) is saved simply by suffixing the instruction with (S). For example:

A=A+BISI /SAVE SIGN
A=A-B(SI /SAVE SIGN
A=AX2ISI / SAVE MSB
A=A/2(SI / SAVE LSB
The overflow is saved until another save instruction is executed. This feature is extremely useful in coding multiply,

Q...

divide, and other algorithms. The saved overflow can be tested for conditional branching or shifted into the LINK

IIF OVF IS ONE JUMP TO LABEL

L=OVF

[LINK GET OVF

The LINK register supplies the logic level for the LSB during left shift operations (A=AX2) and the M83 during right
shift Operations (A=A/ 2).

propagating the carry, the LINK register is useful in generating constants. Constants can be generated by
shifting the register. For example, the constant 00423 (000 000 100 010) is
the
instructions:
following
by
generated
Besides

setting and resetting the LINK and

>°>"°
¥T> >

FIST;

X2 / A contains octal 0001

X2 / A contains octal 0002

=AX2 / A contains octal 0004

AX2 / A contains octal 0010
1

AX2 / A contains octal 0021

>l’ )0
II

X2 / A contains octal 0042

4-2

If space is available in the control PROM and the constants required by the program never need to be changed, it is

desirable to generate the constants and store them in the TR or the optional scratch pad (SP) rather than using the
constant generator (C or K). Table 4-1 lists the complete arithmetic instruction set of PDPlG-M.

Table 4-1
Arithmetic Instruction Set
A Register

Overflow is not: Saved

Overflow is Saved

A=O
A=B
A=A+1

A=A+ 1 (S)

A=A— 1

A=A- 1 (S)

A=A+B

A=A+B(Sl

A=A- B

A=A- B(S)

A=A/ 2

A=A/ 2(8)

A=AX 2

A=AX 2(8)

A=B/2

A=B/2(S)
B Register

B=0

B=A
B=A+1

B=A+1(S)

B=A— 1

B=A— 1(8)

B=A+B

B=A+B(S)
B=A- 8(8)
B=A/2(8)
B=AX 2(8)
B=B/2(S)

B=A- B

B=A/2
B=AX 2

B=B/2
LINK Register

4.1.2

Logical Group

The following logical operations can be performed on the contents of the A and B registers:

ANOT
BNOT
AORB
AB

AXORB

4-3

The result from the specified logical operation can be transferred to either the A or the B register. For example:

A=AORB
B=AORB

4.1.3

registers, the transfer register (TR) is the only other register in the basic PDP16-M that can be
register is byte and word addressable to facilitate data manipulation. The
following instructions can be used to transfer data between the TR and A registers:
Besides the A and B

used for temporary data storage. The

TR=0
TR=A

A=TR

TRU=A

A=TRU

TRL=A

A=TRL

The instructions

specifying lower and upper byte transfers between the TR and the A register (TRL and TRU)

transfer only the specified 8-bit byte between the respective 8-bit locations of the registers. The remaining 8 bits of

be set to logic 0 during a byte transfer to the A register, and the remaining 8 bits of the TR will
unchanged during a byte transfer to the TR. However, the contents of the source register will remain
unchanged. Data cannot be transferred between the B and TR registers.

the A register will

remain

4.1.4

Constant Generator Group

required by the program can be generated by the program or wired in the constant generator (C). If
changed from time to time it is desirable to wire them in the constant generator. This avoids
to
change, reassemble, and reload the program. Up to four constants can be wired in the constant generator
having
that is part of the basic PDP16~M. The following instructions have been implemented to transfer the constants from
the constant generator to the B register:

Constants

constants need to be

The constants cannot be transferred directly to the A register.

4.1.5

l/O Group

The basic PDP16-M has one 16-bit parallel l/O channel (GPll), six Boolean input channels (EXTi—6), and three
Boolean output channels (FFl, FF2 and FF3). The Boolean output channels can also serve as program flags if not
used

output channels since they

can

be tested using the IF instruction. The following instructions control the

Boolean output channels/flags:
To Reset

To Set

FF1=0

FF1=1

FF2=0

FF2=1

FF3=0

FF3=1

The Boolean output channels can drive 8 TTL unit loads. A logic 1

flip—flop. For example:
FF1=1

4-4

(high) Boolean output is produced by setting the

The Boolean input channels can be tested for the presence of a 1

or 0 TTL

logic level using the IF instruction. For

example:
IF EXT1,LABEL
If a logic 1 is sensed, the program will jump to the instruction identified by the label. A 0 logic level at the EXT1

input channel causes the instruction following the IF instruction to be executed. The 16-bit parallel l/O channel can
be used in a variety of ways. The 16 bits can represent individual digital I/O points, a set point value, or a desired
combination of address and data for controlling l/O multiplexers. The A and B registers serve as the source and
destination registers for GPI1. The following instructions have been implemented to transfer output data to the
GPI1:

GPI1=A
GPII=B

Input data from the GPI1 can be transferred to the A or B registers using the following instructions:
A=GPl1

B=GP|1
The Boolean outputs

(FF1—FF3) and the Boolean inputs (EXT 1

—

EXT 6)

can

be used to synchronize and/or

interlock the data transfers between the PDP16-M and external devices.
4.1.6

Command Group

The five control commands in the PDP16-M instruction set are:

PAGEO
PAGE1
MUXO
MUX1

HALT
Two pages of control memory, each

containing 512 words (two control PROMs), can be implemented in the

PDP16-M. The PAGE commands are needed to switch from one page to the other because only 512 words can be

directly addressed. When the second multiplexer is implemented, the MUX commands are needed to switch from
one multiplexer to the other. Each multiplexer offers 30 conditions that can be tested using the IF instruction. The
HALT command causes the program to stop. The console START switch can be pressed to restart the program at
location 0 of the page where the machine stopped. Depressing the START switch does not produce a power clear.
(The power clear signal is generated during power up to reset all data and control registers.) Therefore, when the
machine is restarted, all data and control registers will be in the state they were in when the HALT command was
executed. That is, if the machine stopped in page 1 with multiplexer 1 selected and FF1 set, the program will
continue starting with the instruction in location 0 of page 1 with multiplexer 1 selected and FF1 set.
if the START switch is

depressed while the machine is running it may hang up unless the key switch is in the

PANEL LOCK position. With the key switch in this position, the START switch is disabled. The program can also be
restarted at the location following the HALT command by asserting the CONTINUE signal. The CONTINUE signal
is made available at the MUX and FF l/O slot.

When any of the above five instructions

are

executed, the bus is automatically zeroed and the IF DZ,LABEL

instruction will always be true.

4-5

Test Group

4.1.7

Every time a register transfer instruction is executed, an automatic test for positive, negative, or zero data (DP, DN,
DZ) is made. The result from this test is retained until the next register transfer instruction is executed. Sometimes it
is helpful to find out whether the previous data transfer was positive, negative, or zero. For this reason, two examine
instructions have been implemented:
EXA

EXB
These two instructions can be used to retest the contents of the A and B

registers prior to a conditional jump

instruction. For example:
A=A+B

MUXO
EXA
lF DP,SEND
SEND

GPI=A

GOTO INSTRUCTION

4.2

The GOTO instruction provides the user with a convenient way to transfer control from one part of his program to
another. Control can be transferred unconditionally using the following statement:

GOTO ADD

ADD

LET A=A+B

This statement, which references

a statement

label, can be used anywhere in the program to transfer control to

another part of the program within the same page. All labels must start with an alphabetic character (A—2) and end
with a delimiter. A space, rubout, tab, or a comma can be used as the delimiter. A label may contain from one to ten
characters. To transfer control to a label that appears on the other page,

linkage code must be written (Paragraph

4.5). Control can also be transferred unconditionally using the following statement.
GOTO ADD'—3
This statement, which references a label and a signed number preceded by an apostrophe, transfers control to the
third memory location prior to the ADD label. Control can be transferred to a statement before or after the label by

changing the sign of the number. This method of transferring control is useful when the coder runs out of symbol
table space for labels.

The following statement can also be used for transferring control unconditionally:

GOTO .'+5
This statement, which references

period instead of a label and a signed number preceded by an apostrophe,

transfers control to the fifth memory location after the GOTO instruction. Again the signed number can be positive
or

negative depending on which way the jump is to occur.

4—6

4.3

IF INSTRUCTION

The IF instruction is

conditional jump instruction. There are 21 hardwired conditions that can be tested in the

basic PDPl 6-M. These conditions are:

Condition

Remarks

DZ, DP, DN

Data Word Sign (zero, pos, neg) of Last Data Transfer

OVF

Overflow

A<1,3,5,...15>
FFl, 2, 3
EXT1,2’.3,...6

Odd A Register Bits

CLK

Clock

Boolean Outputs/Flags
Boolean Inputs

A conditional jump is specified by the following lF instruction:

A=TR
IF DP,ADD

ADD

A=A+B

After the A register gets the contents of TR, the IF instruction

causes

test of

DP. If the data transferred was

positive, the program will continue with the statement labeled ADD. This label cannot appear on the other page. If
the data was not positive, the instruction following the IF statement will be executed. Notice that there is a space
delimiter between IF and DP and a comma delimiter between DP and ADD. This format should always be followed
when writing IF statements.
Bit 03 of the A register is tested using the following statement:
I F A<3>,START

START

GPI1=B

If bit 03 of the A

following the IF instruction is executed. Notice that the bit to be tested is enclosed in left and right angle brackets.
This format should always be used in writing lF statements for testing the bits of the A register. The remaining
conditions declared above can also be tested by writing an lF statement as described. For example:
IF OVF,ONE

IF FFI,TWO

IF EXT1,THREE
IF CLK,FOUR

Remember that a space delimiter separates the word IF and the condition to be tested and the comma delimiter
separates the condition to be tested and the statement label.

4-7

To transfer control to a label that appears on the other page, linkage code must be writteanaragraph 4.5).

specifying a jump location relative to the label or the current location, described for the GOTO
instruction, also applies to the lF instruction. For example:

The feature for

A=TR
IF DP,.'+5

IF DN,ADD'—2

A=A+B

ADD

The first IF instruction will transfer control to the fifth memory location from its own location if the test is true.

The second lF instruction transfers control to the second memory location before the label ADD. Again this feature

permits the coder to minimize the number of labels in his program. When limited core storage (no more than 4K) is
available in the PDP-B/E used for assembly, it is desirable to minimize the number of labels because there is room for

only approximately 100 labels in the symbol table.
4.4

CALL AND EXIT INSTRUCTIONS

Repetitive functions can be coded as separate subroutines and called into Operation when needed by the main
program. The call statement brings the subroutine (on the current page) into operation and the EXIT statement
causes a return to the main program. For example:
CALL SUBl

A=GPI1

SUBl

B=CI

A=AXORB
IF DZ,STOP

EXIT
HALT

STOP
Notice that

space delimits the subroutine label and the word call. This format must be used in

writing CALL

statements. This subroutine transfers a data word from the GPl1 to the A register.

The data is then compared with the constant stored in C 1. If the data exhibits the same bit pattern as the constant,
the subroutine will initiate

halt, otherwise it will return control to the main program. Whenever a subroutine is
keep track of 16 return addresses; therefore,

called, the return address is stored in a hardware stack. The stack can
up to 16 subroutines can be called before

returning to the main program. To call a subroutine that appears on the

other page, page linkage code must be written (Paragraph 4.5.2).
4.5

ASSEMBLER DIRECTIVES

Besides the basic instruction set there are several assembler directives that have been implemented for the PDP16-M.
These directives
source

are

useful for commenting the source program, for placing the page linkage code, segmenting the

writing the assembler initialization code. Assembler directives do not cause object code to be
they only control the operation of the assembler.

tape, and

generated

—

4~8

Comments

4.5.1
It is

good practice to

comment the source

program.

Comprehensive comments make

it easier to read and

understand the program. Comments can appear anywhere in the source program. Typically, comments should be
placed at the beginning of a routine to relate its function and after the individual program statements of the routine.
The slash U) is used to denote a comment follows. For example:

/N BIT RIGHT SHIFT
/
/LOAD A WITH BIT COUNT 0 TO 5
/LOAD B WITH DATA TO BE SHIFTIED
/
SHIFTR

EXA

/TEST A (NOT NECESSARY IF JUST LOADED)

SHAGN

IF DZ,SHEND

/EXIT ROUTINE IF A=0

SHEND

B=B/2

SHIFT DATA RIGHT 1 BIT

A=A-1

/DECREMENT COUNT

GOTO SHAGN

/REPEAT

EXIT

/RETURN

$
Notice that a comment does not have to follow the slash. Placing a slash at the left margin without any comment is

simply a way to separate various program segments for readability.
4.5.2

Page Linkage Code

A jump (GOTO, IF, or CALL) into another page cannot be made directly because only 512 locations (the number of

locations in one page)

can

be addressed directly. This is because only a 9-bit jump address (8-bit jump address word

and the M-bit of the operation code) is stored in the control PROM. (Refer to Chapter 3 of PDP16-M Maintenance

Manual.) The jump into another page must be made via source page linkage code. The following instructions are used
to switch pages:

PAGEO
PAGE1
When either of these instructions are executed, the next sequential location in the specified page is executed. For

example:

PAGE 0
0000

PAGE 1

1000

0001
0002

0221

PAGE 1

1221

0667
0700
0777

1222

Instruction Executed

1667

PAGE 0

Instruction Executed
1777

4-9

Using the PAGE instruction in the manner illustrated above creates holes in the page from which the switch was
made. Holes such as these can be avoided by strategically placing the PAGE instructions or the source code. The
ORGn (where n is an octal number from 0 to 1777) allows the coder to place the source and linkage code wherever
he chooses. The ORGn statement causes the PC to be preset to the specified location (n) and causes all subsequent
instructions to be placed in sequential location after the preset locations. For example:

PAGE 0
0000

PAGE 1

1000

0001
0002

XYZ

1001

1002

GOTO P1

GOTO P0

ABC

HALT

ORG 775
0775

ORG 1775

PAGE 1

1775

PAGE 0
GOTO XYZ

GOTO ABC

0776

0777

Pages can be switched in the middle of a page. However, if this is done the coder must keep track of the number of
instructions (locations being utilized in a given page) and then use the ORGn statement to preset the PC to the first
location of each hole in order to utilize all the PROM storage space. Therefore, it is recommended that all page
linkages be placed at the end of the two pages. If a given page is not completely filled with program statements the

ORGn directive can be used to skip over the empty locations to maximize the storage space in the other page. The
PAGE instruction must be labeled so that. the GOTO or CALL instruction can reference the PAGE instructions.

Also, the next location on the other page must contain the GOTO or CALL instruction to the desired label as

applicable. To solve any instruction alignment problem, instructions EXA and EXB or the ORG directive can be
used as no—operation instructions.
Source Program Segmentation

4.5.3

The Symbolic Editor occupies approximately 1000 locations of core in a POP-8 and leaves all but the last page of

allowing, in a 4K core system, for approximately 60 lines of heavily commented text
approximately 340 lines of text without comments (approximately 420010 characters). The source program is
stored in the text buffer area of core. When the text buffer is full, the Symbolic Editor rings the teletype bell. At
this time the text buffer can be enlarged (Introduction to Programming, 1972) or the contents of the buffer can be
punched on paper tape (Chapter 5). However, to satisfy the PDPlG-M assembler a PAUSE or a $ sign directive must
terminate each source program segment that is to be punched. The PAUSE directive tells the assembler during
assembly that there is more to come and the $ sign directive notifies the assembler that the last tape has been read
in. After the Symbolic Editor rings the bell, up to 200 additional characters can be added to the text buffer (Chapter
5). The last statement of the program segment to be punched must be the PAUSE directive or the $ sign directive.

core

for the source program

-—

4.5.4

Assembler Initialization Code

The assembler occupies approximately 2000 locations of core in a PDP-B/ E. After the assembler is initialized with all
PDP16-M instructions there is room left in the symbol table for approximately 100 program labels. After loading,
the assembler is initialized by reading the definition tape. This tape is an ASCII tape prepared and punched using the

4-10

Symbolic Editor. The tape specifies all the PDPiG-M instruction and condition (MUXO and MUXi) mnemonics and
the corresponding octal machine codes. lRefer to Appendix F.) The following assembler directives are used to define
the mnemonics and the associated machine codes.

Directive

Remarks

lNlT

Delete All Symbols

Define instruction

Define Condition

FIX

Add instruction and Condition

PAUSE

Halt Reading Tape

Symbols Defined Above

A partial printout of the definition tape follows:

Mnemonic

Machine Code (octal)

Assembler Directive

lNlT
A=0

000

A=B

001

A=A+1

002

A=A— 1

003

A=A+B

004

DATO

275

T RU=A

276

TR L=A

277

EXT1

EXT2

EXT3

PWOK

GND

DC
FIX

PAUSE

4-11

34
'

If only a limited set of instructions or conditions are going to be used in coding the program a new definition tape
can

be created for initializing the assembler. For example:

IN IT
EEXA

036

B=B/ 2

032

A=A- 1

033

[)2

Fl X

PAUSE

/
/N BIT RIGHT SHIFT
/'

/'LOAD A WITH BIT COUNT 0 TO 15
I'LOAD 8 WITH DATA TO BE SHIFTED
[I
SHIFTR

EXA

/TEST A (NOT NECESSARY IF JUST

SHAGN

IF DZ,SHEND

/EX|T ROUTINE IF A=0

B=B/2

/SHIFT DATA RIGHT ONE BIT

A=A-1

/DECREMENT COUNT

LOADED)

SHEND

GOTO SHAGN

IREPEAT

EXIT

/RETURN

$
This will create

space for program labels, In

creating a new definition tape the user can define his own

instruction and condition mnemonics. For example, the A=A+1 mnemonic can be defined as INCA (increment A).

Or, the user can define the EXT1 Boolean input as CONTROLI. This feature allows the user to redefine all the
instruction and condition mnemonics to simplify his programming task.

4.6

INSTRUCTION IMPLEMENTED THRU OPTIONS

The following options will extend the power and the instruction set of the basic PDP16—M.

Option

Function

MSIGC

Scratch Pad (SP)

MRIB-D

Constant Generator (K)

MR16oE

Data PROM (RMAR—ROM)

MSIS—D or E

Data R/W Mem (MAR—MEM)

DBIB-A

Parallel l/O (GPI)

DA16-F

PUP-11 Peripheral Interface

DC16-A

Serial l/O (SI)

PCSIB—D

Boolean Input (EXT)

KFL16

Boolean Output (FF)

PCSIG—D

Multiplexer 1 (MUX1)

4-12

4.6.1

Scratch Pad (SP) Option MS16-C

Two MSlB-C options can be

registers
results,

be used

implemented in the PDP16—M. Each MSlS-C adds 16 16-bit high-speed registers. These

storage buffers for program generated constants, logical masks, intermediate arithmetic
l/O data. The following instructions have been implemented to transfer data between the scratch pad

can

registers and the A register:

Scratch Pad 1

Scratch Pad 2

SP1=A

A==SP1

SP17=A

A=SP17

SP2=A

A==SP2

SP18=A

A=SP18

SP3=A

A==SP3

SP19=A

A=SP19

SP4=A

A==SP4

SP20=A

A=SP20

SP5=A

A==SP5

SP21=A

A=SP21

SP6=A

A==SP6

SP22=A

A=SP22

SP7=A

A==SP7

SP23=A

A=SP23

SP8=A

A==SP8

SP24=A

A=SP24

SP9=A

A==SP9

SP25=A

A=SP25

SP10=A

A==SP10

SP26=A

A=SP26

SP11=A

A=SP11

SP27=A

A=SP27

SP12=A

A=SP12

SP28=A

A=SP28

SP13=A

A==SP13

SP29=A

A=SP29

SP14=A

A==SP14

SP30=A

A=SP30

SP15=A

A==SP15

SP31=A

A=SP31

SP16=A

A==SP16

SP32=A

A=SP32

Data cannot be transferred directly between the scratch pad registers and the B register.

4.6.2

Constant Generator (K) Option MR16-D

One MR16-D

option can be implemented in the PDP16—M. The option adds 24 16-bit read-only memory (ROM)

locations for program constants. Each constant is set by stringing a single wire through and around a set of 16 ferrite
cores.

The following instructions have been

implemented to transfer the constants from the constant generator to

the B register:

B=K1

B=K9

B=K17

B==K2

B=K10

B=K18

B=K3

B=K11

B=K19

B=K4

B=K12

B=K20

B=K5

B=K13

B=K21

B=K6

B=K14

B=K22

B=K7

B=K15

B=K23

B=K8

B=K16

B=K24

The constants cannot be transferred directly to the A register.
4.6.3

One

Data PROM Option MR16-E
or

two

MR16-E Data PROM options

programmable
characters

—

see

can

implemented in the PDP16-M. The options add 256 8-bit

for program constants, text information (ASCII
read-only memory (PROM)
conversion
or
code
matrix elements. The Data PROMs are identical to the
tables,
Appendix 8),
locations

4.13

control PROM. Preparation of the source code and the object code, as well as the loading procedure for the PROM,

required for the control PROMs. (See Data PROM option MR16-E/F description in the
following instructions have been implemented to address the PROM and
transfer the 8 or 16-bit data to the A or B register:

are

identical to that

PDP16-M Maintenance Manual.) The

Load Address

Transfer Data

RMAR=A

A=ROM

RMAR=B

B=ROM

If only one PROM is to be

implemented, it can be set up so that when the register transfer instruction (A=ROM or
B=ROM) is executed, the data is transferred to the eight high-order bits or the eight low-order bits of the specified
destination register. (See Data PROM option MR16-E/ F description in the PDP16-M Maintenance Manual.) If the
Data PROM is implemented to transfer its data into the eight low-order bits (0—7) of the destination register, the
eight high-order bits will always contain 15 and vice versa (Figure 4-1). When both Data PROM options are
implemented, a full 16—bit data word is transferred to the specified destination register in response to the register
transfer instruction. In any case, since only 256 PROM locations will be available, only an 8-bit address (0—377) is
required to address every location in the PROM(s). Arithmetic register transfer instructions can be used to generate a
specific address or the base address for the constants, messages, tables, or matrices stored in the PROM. (Refer to

example for generating constants in Paragraph 4.1.1.) The same procedure can be used for generating the desired
address for the Data PROM. These addresses can be stored in the SP registers for future reference. Addresses and/or
base addresses for these items can also be set into one of the constant generators (C or K). They
transferred from C or K to the RMAR register via the B register. For example:

e=c1

/GET ADDRESS

RMAR=B

/LOAD ADDRESS

can

then be

A=ROM

/GET DATA

A=ANOT

ICOMPLEMENT DATA

The data stored in the PROM is loaded in complement form by the MR16-SL Utility Interface Assembly. Therefore,
a

complement instruction must be used or the ASCII

source

tape must contain the data in complement form in

order to get the desired data.

Data Read/Write Memory Option MS16-D and E

4.6.4

One

two

M816

Data

Read/Write Memory options

can

implemented

the PDP16—M in any desired

combination. The MSiS-D option provides 256 16-bit words of storage and the MS16—E option provides 1024 16-bit

words of storage. Whatever the implemented combination, one option is designated MEM1 (slot A6) and the other is

designated MEM2 (slot A7). The address buffers for the two memories are MAR1 and MAR2, respectively. The
following is a listing of all normal combinations that can be implemented:

ME M1

MEM2

Total Memory

(slot A6)

(slot A7)

(words)

MS16-D

—

MS16—D

M31 6-D

256

littilnlflllfll‘tmmmm

51 2

MS16-E

M516-D

1280

MS16—E

M316-E

2048

1024

4-14

DATA
A=ROM

BIROM

A OR B REGISTER
l

ROM

4——

—-D

4
'

—.-1

‘_____.

3
"“““

3
A
R

256X8
DATA
ROM 1

256X8
DATA
ROM 2

(SLOT 015)

(SLOT as)

134

A
R

‘-+——

3
.

Cu—

........__..1

¢-————

__...1

0
M4

——_—.1

NOT USED
L

iiiili11116151131211
A OR B REGISTER

RMAR=A

RMAR=B

ADDRESS
16-0029

Figure 4-1

Address and Data Transfer Scheme

These memory Options are useful when a requirement exists for accumulating computed data for subsequent output

accumulating input data. Both parallel and serial data channels are available for transferring the data. The
following instructions have been implemented to address the memories and to transfer the data between the
memories and the A register:
or

for

Load Address

Transfer Data
IN

OUT

MAR1==

MEM1=A

A=MEM1

MARZaA

MEM2=A

A=MEM2

The B register cannot be used to address the memory to transfer the data.

4-15

register transfer instructions can be used to generate a specific address, the base address, and other
storing and/or retrieving data. Address and parameters describing the location and size of the data
block can be stored in the SP registers for future reference. The constant generator (C or K) can also be set up to
provide address and size constants for fixed input/output data buffers.

Arithmetic

parameters for

4.6.5

Parallel l/O Option DB16-A

The basic PDP16-M is equipped with one 16~bit parallel l/O channel
'

(Paragraph 4.1.5). Two additional parallel I/O
implementing the DBlG-A option. One DBlG-A option is required for each channel. Slots
C20 and 020 on the logic assembly are reserved for the parallel l/O channels. Slot C20 is assigned the mnemonic
GP|2 and slot 020 is assigned the mnemonic GPl3. The following instructions have been implemented to transfer
data to and from the channels via the A register:
channels can be added by

The B

Data Input

Data Output

A=GP|2

GPl 2=A

A=GPI3

GPI3=A

used for this purpose with OF”.
The Boolean outputs (FF1—-FF3) and the Boolean

inputs (EXT1—EXT6)

can

be used to

synchronize and/or

interlock the data transfers between the PDP16-M and external devices (Paragraph 4.1.5).
4.6.6

PDP-11 Peripheral Interface Option DA16-F

option must be implemented in order to interface the PDP16-M with low-speed PDP-11 peripheral
devices. The following instructions are needed to communicate with the PDP-11 peripheral devices:

The DA16-F

Instruction

Remarks

FF1=0

Prepares uutput Section of Device
Prepares Input Section of Device
Load Device Register Address
Load Device Register Address
Send Contents of A Register to Device Register
Send Contents of Device Register to A Register

FF1=1
GPl1=A
GPI1=B

DATO
DATl

@‘
'

thorough knowledge of the PDP-11 peripheral device is required before attempting to write routines for
controlling the device. Typically, POP-11 devices have status, control, and data registers. Each device register can be
individually addressed, read, and/or loaded. Appendix A summarizes the register formats and addresses for some of
the low-speed peripheral devices.

In generating addresses under program control or in

installing addresses in the constant generators, the complement

of the actual address must be created. This is because the GP” drives the address lines of the peripheral bus with

TTL levels, not open-collector drivers. The data does not have to be complemented because the data lines are driven
with open-collector drivers.

4-16

.sséeiiiiilmmfllfllwmflflm

‘
‘

Ilmlmmmmmmmnmmw

An example program for the UDC‘II follows:

CALL READST

READST

OUTPUT

(I
INPUT

SKIP

FF1=1

/SET CONTROL LINE C1

B=C1

i’GET STATUS REGISTER ADDRESS

GPI1=B

IADDRESS DEVICE STATUS REGISTER

DATI

l/READ STATUS INTO A REGISTER

IFA<14>,SKIP

i/SKIPIF POWER FAIL

FF1=0

/RESET CONTROL LINE C1

A=0

/CLEAR A REGISTER

B=C2

[GET OUTPUT MODULE ADDRESS

GPI1=B

{ADDRESS OUTPUT MODULE

A=A+1

ISET DATA BIT 00

DATO

/SEND A REGISTER CONTENTS TO OUTPUT MODULE

FF1=1

/SET CONTROL LINE C1

B=C3

/GET INPUT MODULE ADDRESS

GPI1=B

DATI

/ADDRESS INPUT MODULE
/READ DATA INTO A REGISTER

SP1=A

/STORE DATA

EXIT

/RETURN TO MAIN PROGRAM
NOTE
01 = 171776

c2,='1‘7‘i§'2'Z
c3

fifiz‘s‘

006001

006553

006551

This program reads the UDC status word and if no power fail exists, a data word is sent to an output module and the

input module is read. If a power fail is sensed, the program will return control to the main program.
example program is not intended to serve any specific function other than to illustrate how to use PDP16-M
instructions to program PDP-11 peripheral devices.

data from an

The

4.6.7

Serial l/O Option DC16-A

One or two serial interface channels can be added to a PDP16-M. They are added by implementing the DC16-A and

options. One DC16-A option is required for each channel. Slots A816 and A817 on the logic assembly are
l/O channels. Slot A816 is assigned the mnemonic SH and slot A817 is assigned the
mnemonic Sl2. Any TTY compatible devices such as teleprinter terminals, displays, or modems for communication
lines can be connected to the serial l/O channels. The following instructions have been implemented to transfer data

reserved for the serial

between the PDP16-M and the devices and the I/O channels:

Instruction

Remarks

TAPEI

Read one character from Channel 1

TAPE2

Read one character from Channel 2

IF KF1,LABEL

KF1 is set after character from Channel 1 is read and assembled

IF KF2,LABEL

KF2 is set after character from Channel 2 is read and assembled

A=Sl1

Transfer character from Channel 1 (SI 1) to A <0—7>

A=Sl2

Transfer character from Channel 2 (SI2) to A <0—7>

SI1=A

Transfer character from A <0—7> to Channel 1 device

Sl2=A

Transfer character from A <0—7> to Channel 2 device

IF PF,LABEL

PF1 is set after character is displayed, printed, or punched

IF PF,LABEL

PF2 is set after character is displayed, printed, or punched

4-17

The code required for transferring characters between the serial l/O device and the PDP16-M is illustrated below:

[TRANSMIT A CHARACTER
A=SP1

/GET CHARACTER

CALL OUTPUT

/CALL OUTPUT SUBROUTINE

OUTPUT

Sl1=A

/TRANSFER CHARACTER

IF PF1,L1

/TEST PUNCH FLAG AND JUMP IF SET

GOTO L2

/TEST FLAG AGAIN

EXlT

IRETURN

/READ A CHARACTER
CALL INPUT

/CALL INPUT SUBROUTINE

INPUT

TAPE1

/READ A CHARACTER

lF KF1,M1

/TEST KEYBOARD FLAG AND JUMP IF SET

GOTO M2

[TEST FLAG AGAIN

A=Sl1

/TRANSFER CHARACTER

EXIT

/RETURN

Notice that the code for

inputting and outputting characters is imbedded in subroutines so that the code can be
operation each time a character is to be transferred. A summary of ASCII character codes is given in

called into

Appendix B.
4.6.8

Boolean Output Option KFL16

Three additional Boolean output channels/program flags can be added to the PDP16-M (Paragraph 4.1.5). They are
added

by implementing the KFL16 option. The following instructions control the additional Boolean output

channels:

To' Reset

Each channel

can

To Set

FF4=O

FF4=1

F F5=0

FF5=1

FF6=0

FF6=1

drive up to 8 TTL unit loads. A logic 1

(high) Boolean output is produced by setting the flipflop.

For example:

FF4=1
The Boolean output channels

can

also

serve

program flags if not used as output channels because they can be

tested using the IF instruction. For example:

lF F F4,LABEL
IF FF5,LABEL

lF FF6,LABEL

v.3}!

4-18

V‘sninnwmluullmlllmm.

‘_

These instructions cause a test of the specified flip-flop. If the flip-flop is set, the instruction with the declared label
will be executed. If the flip-flop is not set, the next sequential instruction is executed. The flip-flops are set or reset

under program control to specify that a particular condition was satisfied (program flag).
Boolean Input Option PCS16-D

4.6.9

Sixteen additional Boolean input channels can be added to the PDP16-M (Paragraph 4.1.5) by implementing the
PC816«D option. The following instruction provides the means for testing the state (logic 1 or 0) of each input
channeh
lF EXTn,LABEL
where n=the numeral 7 through 22.

logic 1 is sensed, the program will jump to the instruction identified by the label. A 0 logic level at the EXTn
input channel causes the instruction following the lF instruction to be executed.

if a

IF Instruction Option PCS16-D

4.6.10

Besides adding the sixteen additional Boolean inputs (EXT1—22), the PCSlB-D option adds 12 additional hardwired
conditions that can be tested with the lF conditional jump instruction (Paragraph 4.3). These conditions are:

Conditions:

4.7

Remarks

One Bit LINK Register

A <0,2,4,...14>

Even Bits of the A Register

B<0>

LSB of B Register

B<15>

MSB of B Register

PWOK

AC Power OK

SAMPLE PROGRAMS

To further illustrate the

simplicity of coding algorithms using PAL16, the following additional general purpose

subroutines are presented:

Reading Paper Tape from ASiR 33

Print message on ASFl 33

Multiply two 16-bit numbers

4.19

4.7.1

Read Paper Tape

The following subroutine will read a paper tape from the Model ASR 33

Teletype®. The ASR 33 is connected to

...... e

serial I/O Channel 1 (SII).

READING PAPER TAPE FROM ASR 33

/
/

IGNORE BLANK TAPE LEADER. READ PAPER TAPE

AND LOAD IT INTO SEQUENTIAL LOCATIONS IN A

256X16 MEMORY. START IN LOC. 0 AND STOP

WHEN YOU REACH BLANK TAPE TRAILER.

/
B=0

READ

A=O

MAR1=A
READT

READN

CALL PTR

/READ CHARACTER

IF DZ,READT

/JUMP IF BLANK TAPE

M»

MEM1=A

A=B
A=A+1
B=A

MAR1=A

CALL PTR
IF DP,R EADN

EXIT

/
TAPEl

PTR

IF KF‘I,PTRR

F’TRW

GOTO PTRW
A=SI1

PTRR

EXIT

4.7.2

Print Message on ASR 33

The following subroutine will
Channel 1
I

print a message on the ASR 33 keyboard. The ASR 33 is connected to serial I/O

(SII).
PRINT MESSAGE ON ASR 33

I
I
l

ASCII CODES ARE STORED IN 256X8 PROM.

END OF MESSAGE IS CODE 377

B REGISTER HAS START ADDRESS OF TEXT

/
TEXT

TEXTW

RMAR=B

/|NIT|ALIZE PROM ADDRESS

A=ROM

/FETCH CODE

A=ANOT

/COMPLEMENT

IF PF1,TEXTP

/WAIT FOR TTY

GOTO TEXTW
TEXTP

SI I=A

/PFlINT CHARACTER

A=A+1

/INCREMENT

A=A/2

/SHIFT RIGHT

IF A<7>,TEXTC

/TEST FOR END OF MESSAGE CODE

A=B

B=A+l

/UPDATE TEXT POINTER

GOTO TEXTW
TEXTC
®

EXIT

Teletype is a registered trademark of the Teletype Corporation.

4-20

wwwwmflm

‘

AND

4.7.3

Multiply

The following subroutine will multiply ‘two 16-bit

signed numbers and yield a 32-bit result.

PDP16 MULTIPLY ROUTINE

\\\\\

TWO 16 BIT SIGNED NUMBERS YIELD A 32 BIT RESULT
SP2=NUMBER 1
B=NUMBER 2
THE B REGISTER WILL REMAIN UNCHANGED.

g C l—.4

A=0

/CLEAR A REG

SP1=A

/CLEAR SP1

L=1

/GENERATE SHIFT COUNT =15

A=AX2
A=AX2

SP3=A

/STORE SHIFT COUNT

START MULTIPLY
A=SP2

/LOAD NUMBER 1

A=A/2(S)

/FETCH LSB IN OVF

SP2=A
MPCON
MPSHF

A=SP1

/LOAD RESULT UPPER HALF

lF OVF,MPADD

/JUMP IF LSB WAS A 1

A=AX2ISI

/DOUBLE PRECISION ARITHMETIC SHIFT

L=OVF

/SET L

TO SIGN

A=A/2

A=A/2(S)

/SHIFT AND SAVE OVERFLOW

L=OVF
SP1=A

/STORE RESULT UPPER

A=SP2

/LOAD RESULT LOWER

A=A/2(S)

/SHIFT AND SAVE LSB

SP2=A

/STORE RESULT LOWER

A=SP3

/LOAD SHIFT COUNT

A=A-1

/DECREMENT COUNT

SP3=A

/SAVE NEW COUNT

IF DP,MPCON

/REPEAT15TIMES

IF DZ,MPSIGN

/JUMP IF SIGN BIT

EXIT
MPADD

A=A+B

/ADD TO RESULT UPPER

MPSIGN

IF OVF,MPSUB

/JUMP IF NEG SIGN

GOTO MPSHF
GOTO MPCON

MPSUB

A=SP1

/LOAD RESULT UPPER

A=A-B

/SUBTRACT FROM RESULT UPPER

GOTO MPSHF

/GO TO SHIFT

4-21

CHAPTER 5
PROGRAM PREPARATION AND ASSEMBLY

The PDP16-M control program (or data arrays for the data PROM) is prepared and assembled on a PDP-8/E. The
source

paper tape, which is required for assembly, is prepared under the control of the Symbolic Editor. The source

tape is read and translated by the PAL‘lGi Assembler. After successful assembly the object tape can be punched. The
object tape contains the machine code of the control program that is loaded into the PDP16—M control PROM.
The PDP-8/E to be used for program preparation and assembly need only be equipped with 4K of core and an ASR

33. The ASR 33 contains a low-speed reader and a low-speed punch.
Before either the Symbolic Editor or the PAL16 Assembler can be loaded, the Binary Loader must be in core.
5.1

BINARY LOADER

The Binary Loader (BIN) is a short utility program which, when in core, instructs the computer to read binary-coded
data punched on paper tape and store it in core memory. This loader is used to load the Symbolic Editor and PAL16
Assembler. It is also used to load the utility program (Chapter 6).

The Binary Loader is supplied to the user on punched paper tape in RIM-coded format. This tape is loaded into core

by the RIM Loader (Table 5-1).
There are two RIM Loaders:

one

for the low-speed reader (LSR) and another for the high-speed reader (HSFI). The

appropriate RIM Loader is toggleol in core with the computer switch register as detailed in Figure 5-1.

Table 5-1

RIM Loader Programs
Location

Instruction

Low-Speed Reader

High-Speed Reader

7756

6032

6014

7757

6031

6011

7760

5357

7761

6036

6016

7762

7106

7763

7006

7764

7510

7765

5357

5374

7766

7006

5-1

TabIe 5-1 (Cont)
RIM Loader Programs

Location

Instruction
Low-S 9eed Reader

Hi 9 h-S 9e ed Reader

46:6

’

7767

6031

6011

7770

5367

7771

6034

6016

7772

7420

7773

3776

7774

3376

7775

5356

5357

7776

0000

YES

’

655%

*SET
‘OF=DESIRED FIELD
IF=DESIRED FIELD

LOAD ADD

SET SR=FIRST
INSTRUCTION

LIFT

DEP

SET SR INEXT
INSTRUCTION

LIFT DEP

*DEC TAPE USERS SHOULD
LOAD RIM INTO FIELD 0

RIM IS LOADED

IS-DOQI

Figure 5-1

Loading the RIM Loader

5-2

WWWWWWIW

‘

After RIM is loaded, it is a good practice to verify that all instructions were stored preperly. This can be done by

performing the procedure illustrated in Figure 5-2. The flowchart also shows how to correct an incorrectly stored
instruction. With the correct RIM Loader in core, the Binary Loader paper tape can be read and stored in core by
following the procedure illustrated in Figure 5-3. After the Binary Loader paper tape is successfully read, the loader
resides in the last page of core, occupying absolute locations 7625 through 7752 and 7777.

The Binary Loader was purposely placed on the last page of core so that it would always be available for use

—

the

Symbolic Editor and the PAL16 Assembler do not use the last page of core. To load either the Symbolic Editor or
the PAL16 Assembler binary paper tapes perform the procedure illustrated in Figure 5-4. Since the Binary Loader
remains in the last page of core, unaffected by the loading procedure, it can be used again using the same procedure
to switch between the Symbolic Editor and the assembler, or vice versa.
5.2

SYMBOLIC EDITOR

The Symbolic Editor is a service program which allows the programmer to write and prepare symbolic programs and

generate a symbolic program tape of his programs. Editor is very flexible in that the programmer can type his
symbolic program on-Iine from the teletype keyboard, thus storinglit directly into core memory. Then, using certain
Editor commands, the programmer can have his program listed (printed) on the teleprinter for visual inspection.

USING

EXTENDED
MEMORY

SET
DF=CORRECT FIELD
IF= CORRECT FIELD

?
NO

SET SR I 7756

DEPRESS LOAD ADD

DEPRESS EXAM

MBINSTRUCTION

ET saw—E

I
LOAD—ADD

DEPRESS

I
ALL
INSTRUCTIONS

SET SR CORRECT
INSTRUCTION
=

CHECKED
?

5&3“

RIM IS LOADED

l6—0042

Figure 5-2

Checking the RIM Loader

5-3

YES

SET SR

l'SET
(JP-CORRECT FIELD
IF=CORRE€T FIELD

7756

DEPRESS
LOAD ADD

WHICH

REAgER
LOW- SPEED

HIGH-SPEED
READER

READER

TURN TTY
TO LINE

DEPRESS
CLEAR/CONT

PUT LSR
TO FREE

PUT BIN TAPE
IN LSR

PUT LSR
TO START

HSR STOPS AT
END OF TAPE
DEPRESS
CLEAR/CONT

r...—

TAPE
READS IN

?
YES
LSR STOPS AT
END OF TAPE

DEPRESS START

REMOVE TAPE
FROM READER

”SAME FIELD SETTINGS AS RIM

BIN

LOADED
3643093

Figure 5-3

Loading the BIN Loader

5~4

I Wmg"?
"WWWWVIWW.

LOAD

BIN

ex‘ise'ifi‘geo
MEMSRY

SET
DF=DES|RED FIELD
IF=FIELD OF BIN

SET SR I 7777

DEPRESS
LOAD ADD

LOW-SPEED
READER

TURN TTY
TO LINE

PUT BIN
TAPE IN LSR

SET LSR
TO START

TAPE
STOPS AT
BEGINNING OF
TRAILER TAPE
?

I DEPRESS CONT |
I

YES

END
OF TAPE

?
YES
OBJECT TAPE
IS LOADED
16-0044

Figure 54

Loading A Binary Tape Using BIN

5-5

Editor also allows the programmer to add, correct,

delete any

portion of his symbolic program. When the

programmer is satisfied that his program is correct and ready to be assembled, Editor can be commanded to generate
a

symbolic program tape of the stored program.

The Symbolic Editor program is issued on punched paper tape in binary-coded format. Therefore, it is loaded into

using the BIN Loader. When in core, Editor is activated by setting the switch register (SR) to 0200
(the starting address) and depressing the LOAD ADD (load address switch) and then the START switch, Editor

core

memory

responds with a carriage return/line feed sequence on the teletype.

lnitially, Editor is in command mode, (that is, it is ready to accept commands from the programmer); anything
typed by the programmer is interpreted as a command to Editor. Editor accepts only legal commands, and if the
programmer types something else, Editor ignores the command and types a question mark (.7).
When not in command mode, Editor is in text mode; that is, all characters typed from the keyboard or tapes read in
the tape reader are interpreted as text to be put into the text buffer in the manner specified by a preceding
Editor command. Figure 5-5 illustrates how the programmer can transfer Editor from one mode to another.

,,..4.

TYPE A COMMAND
THEN DEPRESS
RETURN KEY

COMMAND MODE

TEXT MODE

“m

TYPE DESIRED
INPUT. THEN
CTRL/FORM KEYS

16- 0045

Figure 5-5 Transition Between Editor Modes

Seven of Editor's basic commands are briefly described below:
COMMAND

MEANING

Append incoming text from the keyboard into the text buffer immediately following
the text currently stored in the buffer.

Read incoming text from the tape reader and append it to the text currently stored in
the buffer.

List entire text buffer; the programmer can specify one line or a group of lines.

Change a line; the programmer precedes the command with the decimal line number or
line numbers of the lines to be changed.

Insert into text buffer; the programmer

specifies the decimal line number in his

program where the inserted text is to begin.

specifies the line or group of lines to be

Delete from text buffer: the programmer
deleted.

Punch text buffer; the programmer can specify one line, a group of lines, or the entire
text buffer.

5-6

are executed, except the P command, when the RETURN key is depressed. To execute the P
command, press the RETURN key on the teletype, turn on the punch, and press the CONT (continue) switch on the

All commands

computer console.
The above commands are only the seven basic commands. A summary of all commands is provided in Table 5-4.
5.2.1

Writing a Program

Now that you have some idea of what you can do with the Symbolic Editor and what it can do for you, we will
write and edit a short program, explaining each step in the comments to the right of the printout.
The

example program is a print text routine for serial l/O channel Sll. The program is written in PAL16, to be

assembled using the PAL16 Assembler described later in this chapter.
The programmer loads Editor
address (0200

using the BIN Loader (Figure 5-4). Editor is then activated by loading the starting
octal) and depressing the LOAD ADD, CLEAR, and CONT switches. After Editor responds with a

—

carriage return/line feed, the programmer types A and RETURN key. Editor is now in text mode; that is, subsequent
characters typed are added in the text buffer. The programmer now types the symbolic program. (Block indenting is
facilitated using the CTR L/TAB key which Editor has programmed to indent in 8-character increments.)

TEXT PRINT ROUTINE

/
/

ASCII CODES ARE STORED IN 256X8 PROM

END OF MESSAGE IS CODE 377

B REGISTER HAS START ADDRESS OF TEXT

/
TEXT

RMAR=B

/|N|TIALIZE PROM ADDRESS

A=ROM

TEXTW

A=ROM

/FETCH CODE

A=ANOT

/COMPLEMENT

IF PF1,TEXTP

/WAIT FOR TTY

GOTO TEXTW
TEXTP

SI I=A

/PRINT CHARACTER

A=A+1

/|NCREMENT

A=A/2

/S|HIFT RIGHT

lF A<7>,TEXTC

/TEST FOR END OF MESSAGE CODE

A=B

B=A+2

/UPDATE TEXT POINTER

GOTO TEXTW
TEXTC

EXIT

Visual inspection reveals errors in lines 9, 19, and 20 (Editor maintains a line number count in decimal, with the first
line typed being 1 and the last line being 22). Line 9 can be removed using the D (delete) command, and lines 19 and

20 can be corrected using the C (change) command. However, Editor is presently in text mode, and in order to issue
another command, Editor must be transferred to command mode. This is done when the programmer types

CTRL/FORM (depress and hold down the CTRL key while typing the FORM key).

5-7

The programmer types CTR L/FORM; Editor responds with

CTR L/ FORM (nonprinting)

CR/LF and rings the teleprinter bell, indicating that it is in

command mode.
The programmer types 90 and the RETURN

key; Editor

responds with a CR/LF and the line is deleted.

types 18, IQC and the RETURN key,
informing Editor that lines 18 and 19 (formerly 19 and 20)
are to be changed.

The programmer

18, 19C

’

Editor responds with a CR/LF, transfers to text mode, and
waits for the programmer to change the lines.

/UP’DATE TEXT POINTER

B=A+1

"‘

The programmer types B=A+1 /UPDATE
TEXT POINTER and GOTO

GOTO TEXT

TEXT

The symbolic program should now be correct. However, it is good programming practice to check the program after

editing; this can be done using the L (list) command, but since only original lines 9, 19, and 20 were changed, it is
not necessary to have the whole program listed. The programmer can command Editor to list lines 9 through 20.

CTRL/FORM (nonprinting)

The programmer types CTRL/FORM to return Editor to
command mode; Editor responds with

CR/LF, rings the

bell, and waits for the next command.

9', 20L

The programmer types 9, 20L and
Editor types lines 9 through 20.

TEXTW

A=ROM

/FETCH CODE

A=ANOT

/COMPLEMENT

IF PF1,TEXTP

/WAIT FOR TTY

the RETURN key;

GOTO TEXTW
TEXTP

Sl1=A

/PRINT CHARACTER

A=A+1

/INCREMENT

A=A/2

/SHlFT RIGHT

IF A<7>,TEXTC

/TEST FOR END OF MESSAGE

3%“
,

A=B
B=A+1

/UPDATE TEXT POINTER

GOTO TEXT
TEXTC

EXIT

The changes were accepted properly. The symbolic program is correct and ready to be punched on paper tape.

5.2.2

Search Feature

A very convenient feature available with Editor is the search feature which allows the programmer to search a line of
text for a

specified character. When the programmer types a line number followed by 8, Editor waits for the user to

5-8

~=<mmi|llliilllllllilllillllllllllllllllllillillm

‘7

type in the character for which it is to search. The search character is not echoed (printed on the teleprinter). When
Editor locates and types the search character, typing stops and Editor waits for the programmer to either type new
text and terminate the line with a RETURN

key or to use one of the following special keys:

Special Key

Function

(—

to delete the entire line to the left,

RETURN

to delete the entire line to the right,

RUBOUT

delete from right to left one character for each RUBOUT typed (a / is echoed for each

RUBOUT typed),
LINE FEED

to insert a carriage return/line feed (CR/LF) thus dividing the line into two,

CTRL/FORM

to search for the next occurrence of the search character, and/or

CTR L/ BELL

to change the search character to the next character typed by the programmer.

Input/Output Control

5.2.3

register options are used with input and output commands to control the reading and punching of paper
tape. The options available to the programmer are shown in Table 5-2.

Switch

Table 5-2

Input/Output Control
SR Bit

Position

Input text as is

Convert all occurrences of 2 or more spaces to a tab

Output each tab as 8 spaces
Tab is punched as tab/rubout
Output as specified
Suppress output*
Low-speed punch and teleprinter
High-speed punch
Low-speed reader
High-speed reader

*Bit 2 allows the user to

Function

interrupt any output command and return immediately to command mode; when desired, merely set

bit2 to 1.

5.2.4

Generating a Program Tape

issuing the P (punch) command, Editor must be in command mode. Figure 5-6 illustrates the procedures
required to generate a symbolic program tape using the Editor.

Before

EDITOR iS IN
COMMAND MODE
AND COMPLETED
SYMBOLIC PROGRAM IS IN
TEXT BUFFER

HIGH-SPEED

LOW-SPEED
PUNCH

PUNCH

SELECTswnCH
REGISTER

SELECTSWWCH
REGISTER
OPTION

OPTION

‘

OEPRESS
HSP 0N

TYPE'rAND
RETURN KEYS

Agg gfiPRESS
{7

TYPETAND
RETURN KEYS

a”;
"w

AFTERLEADER
TAPEDEPRESS
LSP OFF

TYPECOMMAND
(P NP OR M NP)
ANDRETURNKEY

{i
TYPECOMMAND

WNPORMNM
OEPRESS

CONT

ANDRETURN KEY

TExTIs
PUNCHED

OEPRESS
LSP ON

DEPRESS
PUNCH

MORE;EXT

CONT

YES
—‘

TExTIS
PUNCHED
ANDTYPED

Aflflh
“

TYPEFAND
RETURN KEYS
OEPRESS
LSP OFF
TYPE'TAND
RETURN KEYS
TYPE FAND
RETURN KEYS
AND OEPRESS
LSP ON

REMOVE TA PE

PUNCH
MORETEXT
?

Aflhg
TYPE TAND
RETURN KEYS
AND OEPRESS
LSP OFF

AFTER TRAILER
OEPRESS LSP OFF

m
16-0046

Figure 5-6 Generating a Symbolic Tape Using Editor

540

CTR L/FORM (nonprinting)

The programmer types CTR L/FORM.

Editor

responds with

question mark, indicating that

Editor was already in command mode.
P

The programmer commands Editor to punch the entire text
buffer by typing P and the RETURN key.

When Editor recognizes a P command it: waits for the programmer to specify the low- or high-speed punch. If the
programmer wants the program punched and typed, he sets SR bit 10 to O and the program will be punched on the

low-speed punch and simultaneously typed on the teleprinter. If the programmer wants only a program tape and if
a high-speed punch available, he sets SR bit 10 to 1 and the program will be punched on the high-speed
punch. For the purposes of this discussion a printed program listing is desired, so the low-speed punch is specified.
The programmer turns on the low-speed punch and depresses the CONT switch on the computer console. Editor
begins punching and typing the contents of the entire text buffer.
he has

An image of the stored symbolic program has been punched and typed by Editor.

5.2.5

Loading a Program Tape

Set console switches

indicated in the section on input/output control options (Paragraph 5.2.3), depending on

options desired.
Place the symbolic tape of the program to be corrected in the appropriate paper-tape reader. At the keyboard, type
the READ command (R) followed by a carriage return. If using the teletype reader, turn it on now. The symbolic

tape will be read into the text buffer.
The Editor will continue reading the tape until a form feed code is encountered. if the tape contains no form feed

code, and the teletype reader is being used for input, type the CTR L/FORM key combination after the tape has
been read in. Upon recognizing the form feed character, Editor enters the command mode and rings a bell to
indicate that it is ready for the first command.
CAUTION
When

using the teletype reader, if the form feed code is
encountered before the symbolic tape has completely read in
(as indicated by the ringing of the bell), turn off the
paper-tape reader. Otherwise, characters on tape will be
interpreted as commands to Editor. The section of tape read in
up to the form feed code should then be edited first before

proceeding with the remainder of the tape.

5.2.6

Restart Procedure

If the programmer stops the computer, for example, purposely or accidentally turning the computer off, he may
restart Editor at location 0200 or 0177 without disturbing the text in the buffer. Editor can also be restarted at
location 0176; however, all text

currently in the buffer is wiped out. Therefore, the programmer can restart at

location 0176 to re-initialize for a new program.

5.2.7

Error Detection

Editor checks all commands for nonexistent information and incorrect formatting. When an error is detected, Editor
types a question mark (7) and ignores the command. However, if an argument is provided for a command that
doesn't require one, the argument is ignored and the command is executed properly.

5-11

Editor does not recognize extraneous and illegal control characters; therefore, a tape containing these characters can
be cleared up or corrected by merely reading the tape into Editor and punching out a new tape.

5.2.8

Summary of Special Keys and Command:

Using special keyboard keys and commands, the programmer controls Editor's operation. Certain keys have special
meaning to Editor, of which some can be used in either command or text mode. The mode of operation determines
the function of each key. The special keys and their functions are shown in Table 5-3.

Table 5-3

Summary of Special Keys
Command Mode

Key
RETURN

Text Mode

Execute preceding command

Enter line in text buffer

Cancel preceding command

Cancel line to the left margin

(Editor responds with a .7
followed by a carriage
return and line feed)

RU BOUT

same as *-

Delete to the left character for each depression;
a backslash

is echoed

[not used in Read (R)

command]
CTRL/FORM

Respond with question

Return to command mode and ring teleprinter

mark and remain in com-

bell

mand mode

.(period)

Value equal to decimal

M7:

Legal text character

value of current line

(may be used alone or with
and a number, for
example, .+8)
+ or

—

Value equal to number of

Legal text character

last line in buffer; used as
an

LINE FEED

argument

List next line

Used in Search (S) command to insert CR/LF

into line

ALTMODE

“AV

List next line
List next line
List previous line

Used with

or/to obtain

their value

Same as

(gives value of
legitimate argument)

CTR L/TAB

M
‘

Produces a tab, which on output is interpreted
as

10 spaces or a tab/rubout, depending on SR

option

Editor commands are given when in command mode. There are three basic types of commands: input, editing, and

output. Table 5-4 contains a summary of Editor commands and their function.

Table 5-4

Summary of Commands
Type
Input

Editing

Command

Function

Append incoming text from keyboard into text buffer

Append incoming text from tape reader into text buffer

List entire text buffer

List line n

m,nL.

List lines m through n inclusively

Change line n

m,nC

Change lines m through n inclusively

Insert before first line

Insert before line n

Delete entire text buffer

Delete line n

m,nD

Delete lines rn through n inclusively

m,n$jM

Move lines m through n to before line j

Print next tagged line (if none, Editor types .7)

Print next tagged line after line n (if none, .7)

Search buffer for character specified after RETURN

key and allow modification (search character is not
echoed on printer)

Output

Search line n, as above

m,nS

Search lines m through n inclusively, as above

Punch

Punch line n

m,nP

Punch lines m through n inclusively

entire

5—13

text buffer

Table 54 (Cont)

Summary of Commands
'

Type

Command

Output
(Cont)

Notes:

Function

Punch about 6 inches of leader/trailer tape

Punch 3 FORM FEED onto tape

Do P, F, K, and R commands

and n are decimal numbers, and m is smaller than n;j is a decimal number.

The P and N commands halt Editor to allow the programmer to select l/O control; press CONT to
execute these commands.

5.3

Commands are executed when the RETURN key is depressed, excluding the P and N commands.

PAL16 ASSEMBLER

The PAL16 Symbolic Assembler (PAL stands for Program Assembly Language) is a system program used to translate

symbolic programs written in the PAL16 language into binary-coded (machine code) programs. PAL16 is a two-pass
assembler that is run on the PDP-8 family of computers. In a two-pass assembler, the symbolic source program tape
must be processed by the assembler two times to produce the binary object tape. PAL16 accepts symbolic program
tapes from either the low-speed reader or the high-speed reader and produces the binary tapes on either the
low-speed or high-speed punch. A brief description of the two passes is given below:
5.3.1

Pass 1

The assembler reads the symbolic program tape; stores labels with an assigned program location; checks for defined

operation codes, valid label fields, duplicate labels, and valid labels; and generates the label table. No
error messages are typed during pass 1.

and proper

5.3.2

Pass 2

The assembler rereads the symbolic program tape, takes the indicated labels found in pass 1 and creates the object
machine code. The assembler also checks for undefined and

duplicate labels. During this pass the object code is

punched and/or a listing of the object and source program is produced.
During assembly, the programmer communicates with PAL16 via the switch register on the computer console.
Switches are set and reset to specify the high or low-speed reader for reading the source tapes, the high or low-speed

punch for punching the object tape, and the TTY or line printer for listing the program. A summary of available
switch register options is given in Table 5-5.

if the assembler finds errors in the source program, error messages are printed directly after the program listing and

before the symbol (label) table.

5.3.3

Assembling a Program

Paragraph 5.2 described how to prepare a PAL16 symbolic program and produce the paper tape using the Symbolic
Editor. After the paper tape is punched the program can be assembled using PAL16. A listing of a sample symbolic
program follows:

5-14

TEXT PRINT ROUTINE
ASCII CODES ARE STORED IN 256X8 PROM.

END OF MESSAGE IS CODE 377
B REGISTER HAS START ADDRESS OF TEXT

EXT

RMAR=B

I'lNlTlALIZE PROM ADDRESS

A=ROM

I'F ETCH CODE

A=ANOT

I'COMPLEMENT

TE XTW

IF PF1,TEXTP

TEXTP

S|1=A

I'PRINT CHARACTER

A=A+1

I'INCREMENT

A=A/2

I'SHIFT RIGHT

lF A<7>,TEXTC

I'TEST FOR END OF MESSAGE

GOTO TEXTW

A=B

/UPDATE TEXT POINTER

B=A+1

GOTO TEXT
TEXTC

EXIT

95
Table 5-5
PAL16 Assembler Switch Register Option
Function

Switch Register Setting
0

R P

Assemble and Punch

R P

Assemble Punch and

Load Definition or

Source Tape

Assemble and List
on

TTY

Assemble and List
on

Line Printer

List on TTY

Assemble Punch and
List on Line Printer

READERI T-LlNEPR|NT/TTY
PUNCH

Notes:

0 for HSR and 1 for LSR

0 for HSP and 1 for LSP

5-15

PUNCH J

L NOT LIST

First, PAL16 must be loaded into core memory, and since PAL16 is on punched paper tape in binary format, it is
loaded into core memory using the BIN Loader. Refer to Paragraph 5.1 for the loading procedure.
After PAL16 is loaded into

core memory, it must be initialized before it can be used to assemble a symbolic
Figure 5-7 illustrates the procedures required for initializing the assembler and for assembling a symbolic
program using the low-speed reader/punch, the high-speed reader/punch, and the TTY or line printer.

program.

An example of the assembly procedure using the low-speed reader/ punch (LSR and LSP) follows (Figure 5-7).

Initializing and Starting

Load PAL16 into core memory using BIN
Set SR=0200 and depress LOAD ADDR
Turn TTY to LINE and

place definition tape (assembler initialize code) in

LSR
Set SR=4000, set LSR to START and depress CLEAR/CONT

Entering Pass 1

Place symbolic source program tape in LSR
Set SR=0200 and depress LOAD ADDR

Set SR=4000 and depress CLEAR/CONT

Entering Pass 2

Place symbolic source program tape in LSR again
Set

SR=2002,

set

LSR

START, depress LSP

and

depress

CLEAR/CONT
The

octal/symbolic program and symbol table is listed (see below) and the

object code is punched on paper tape

TEXT PRINT ROUTINE

0000 246
0001 135
0002 011
0003 364

.4\\\\

ASCII CODES ARE STORED IN 256X8 PROM.
END OF MESSAGE IS CODE 377
B REGISTER HAS START ADDRESS OF TEXT

EXT

TEXTW

RMAR=B

/|NITIALIZE PROM ADDRESS

A=ROM

/FETCH CODE

A=ANOT

/COMPLEMENT

IF PF1,TEXTP

/WAIT FOR TTY

0004 007

GOTO TEXTW

0005 300

0006 003

TEXTP

S|1=A

/PR|NT CHARACTER

0010 002

A=A+1

/INCREMENT

0011 012

A=A/2

/SHIFT RIGHT

0012 334

IF A<7>,TEXTC

/TEST FOR END OF MESSAGE CODE

0007 050

5-16

0013020
0014 001

A==B

0015 257

B==A+1

0016 300

GOTO TEXT

/UPDATE TEXT POINTER

0017 000
0020 377

TEXTC

TEXT

0000

TEXTW

0003

TEXTP

0007

TEXTC

0020

EXIIT

The paper tape contains the binary object code (in ASCII

format) that is loaded into the control PROM using the
utility program. Refer to Chapter 6. The octal/symbolic program listing and symbol table
produced during pass 2 is used when debugging the program. If errors in the source program are encountered by the
assembler, appropriate error messages are printed just before the symbol table. Each error message is preceded by a
four digit line number (in octal) where the error was encountered.
load function of the

5.3.4

Error Messages

The error messages that are printed are mostly self-explanatory. A brief description of each error message follows:
XXXX UNDEFINED OP-CODE
This message is printed when an operation code is used that is not defined in the definition tape. For example:

A=ANOT

/where A=ANOT is not defined in definition tape.

XXXX INVALID LABEL

This message is

printed when a label greater than 10 characters in length or a label starting with a non-alphabetic

character is used. For example:
1 LOOP

XXXX UNDEFINED LABEL
This message is printed when a test condition for the IF statement is not defined in the definition tape or when the
destination label in a GOTO or an IF statement are not defined. For example:

IF DN,NEG
where DN or NEG is not defined. DN must be defined in the definition tape and NEG must be defined in the source
program and must appear on the left margin.

XXXX DUPLICATE LABEL
This message is printed when two labels with the same name are used.

517

LOAD

PAL16

SET SR = 0200

DEPRESS
ADDR

LOAD

PUT DEFINITION
TAPE IN

READER

HIGH SPEED
READER

WHICH
READER

LOW SPEED
READER

SET SR =0000

SET SR

4000

TURN TTY T0 LINE

TURN ON HSR

DEPRESS
CLEAR /CVONT

SET LSR
TO START

TAPE
READSIN

?
YES

SET SR=0200

DEPRESS LOAD
ADDR

PUT SOURCE
TAPE IN

READER

I
SET SRIOOOO
FOR HSR
SRIQOOO FOR LSR

DEPRESS
CLEAR/CONT

TAPE
READS IN
7
16-0047

Figure 5-7

Assembling with PAL16 (Sheet 1 of 2)

5-18

~%mwmmmmmmmnmww

‘

WWIWWHWMMMWWh

PUT SOURCE
TAPE IN
READER AGAIN

LINE

SET 55R

_P_RINTER

SW02=3

SET SR SW02= 0

SELECT LINE
PRINTER

SET SR SW11=1

LOW SPEED
PUNCH

HIGH SPEED

PUN

SET SR SW01 =1

SET SR SWO1= O
W10=1

[—URN ON Hspj
I

SWIO=1

FET SR sw10=o I

[ TURN ON LSP ]
I

DEPRESS
CLEAR /CONT

WAIT FOR TAPE
TO READ IN

ERROR

YES

MESS?AGE*

CORRECT ERROR
IAND

REASSEMBLE

NO
FINISHED

LIST OPTION CAN BE SELECTED JUST
BEFORE LAST PRINT 0F TAPE READS
IN TO PRINT ERROR MESSAGES. IF ANY.
16-0048

Figure 5-7

Assembling with PAL16 (Sheet 2 of 2)

5-19

XXXX MISSING OPERAND

This message is printed when no destination label is given to the GOTO or IF statements. For example:
IF DP, OR GOTO

XXXX INVALID STATEMENT FORMAT
This message is printed when the operation code starts on the left margin (first space) or if a label appears with no

operation code or operand.

xxxx INVALID CHARACTER

printed when other than characters represented by ASCll codes 212 through 337 are used in the
program. Therefore the ALT MODE key and all control command if used in the source program will cause
this error message to be printed.

This message is
source

XXXX NON-OCTAL DlGlT
This message is printed if a non-octal digit is used in preparing the definition table tape. For example:

A=AB

008

XXXX CONSTANT TOO LARGE
This message is printed when the evaluation number in the definition table exceeds the limit or if an ORG statement
is out if range. For example:

B=Sl1

300

ORG 3777

XXXX NO LABEL ON EQU STATEMENT
This message is printed when the evaluation number in the definition table is missing. For example:

B=Sl1

XXXX ADDRESSlNG ERROR

This message is printed if 3 CALL, GOTO, or lF instruction runs off the end of the page or references a label located
in the other page.

5-20

‘

"‘ '

“““W‘

Wmmmmmwmwwwmmmmmm

CHAPTER 6
_

UTILITY OPTION

(TENTATIVE)

After a program is written and assembled error-free, the program and the application interface must be exercised and

debugged. A new program will not always run the first time. Usually, inconspicuous bugs are characteristic of new
programs and newly interfaced equipment. Only after the program and the interfacing equipment are debugged
should the PROM be loaded. The utility option designated MR16-SL, offered by Digital Equipment Corporation in
conjunction with a PDP-8/E computer and supporting utility software, offers the means with which the user can
exercise, debug, and load his program (Appendix H). in addition to exercising and loading, this option offers useful
functions such as verifying that a PROM does contain accurate object code and listing the contents of a PROM. The

MR16-SL Utility Option comprises the following:
a.

M8307 Utility Option

Module (PROM simulator/loader control) that plugs directly into

vacant

OMNlBUS slot of the PDP-8/E.

6.1

MR16—SL Function Panel that mounts in a standard 19-inch rack.

Three BC08R-XX Cables for interconnecting the M8307 Utility Option module and the function panel.

Utility program tape (binary) containing the following:
a.

PROGRAM Subroutine

VERIFY Subroutine

SlMULATE Subroutine

Support Subroutines

INSTALLATION

Any standard PDP-8/E computer equipped with 4K of core memory and an ASR 33 (LT33DC) can serve as the
utility computer (Figure 6-1). Machines equipped with an ASR 35 and a high-speed reader/punch in place of the
ASR 33 can also be used. To install an MR16-SL Utility Option in a PDP-8/E computer, proceed as follows:
1.

Mount the MR16-SL Function Panel in close proximity to the PDP-B/E main frame.

install MR16~SL Utility Option Module (M8307) in a vacant OMNlBUS slot of the PDP-B/E.

Connect the three supplied cables.

Connect 62V (0.1A) power supply (user supplied) to + and

6-1

tabs located on the function panel.

POP-8E

< :: >

KKS-E
CPU

<:;>

MEMORY

(4K)

Kce—EA

KLB-

> “553%“ng

LT33—Dc
TELEPRINTER

O
M
N
I

a
u
s

p
R

BCOBR-Xx

PROM

R
A
M

-—-—T
MRls-SL
MODULE
M8307

——-----I

-——l
BCOBR‘XX

MRIe—SL
FUNCTION
PANEL

‘3

.—

PROM

F
Y

El
M

M
U
L
A

BCOBR-XX

BCOZX-lo

T
E

GND

52v

62V

‘

USER
INTERFACE

-x-

l
BUS
MONITOR

powea
SUPPLY

<\/
*

PDP‘G‘M

OPTIONS THAT ARE EXERCISED BY THE
APPLICATION PROGRAM TO BE SIMULATED
MUST BE INCLUDED.
16

Figure 6~1

JOY‘

fieE...

Utility Computer Configuration

Installing the utility option in a PDP-B/E does not dedicate the machine to just utility functions. The machine can
still be used for program development as described in Chapter 5.
6.2

OPTION DESCRIPTION

a programmable device interface (Figure 6-2) for debugging, verifying, and loading PDPlG-M
application programs. A special utility program controls the Operation of the device interface. The function panel
houses three connectors; one for each of the specified utility functions. The connectors are placarded: PROGRAM,
VERIFY, and SIMULATE. To program (load) or verify (check) a PROM, the PROM must be inserted in the

The MR16~SL is

corresponding

connector.

exercise

program

for

debugging

purposes, the PDPlB-M is connected to the

SIMULATE connector. After the utility program is loaded into PDP-8/E core memory and started, it will query the
operator as to which function is desired by typing an F on the teleprinter. The operator can then select the desired
function by typing the appropriate command.
Since the MR16-SL is fully supported by the utility program, the user need not concern himself with programming
the MR16—SL. Therefore, detailed description and programming information for the MR16-SL are not

provided in

this manual.

6.3
To

OPERATIONAL DETAILS
use

utility option, the user must first load the utility program into PDP-8/E core memory and start the

the

program at octal location 6000. The Binary Loader must be used to load the utility program tape (Paragraph 5.1).
After the program is loaded and started, the user can select any one of eight utility functions by typing the

appropriate command. The commands are:
Z

S
B

—

——

—-

—

——

—

Zero

Fetch
Load

Modify
Simulate

Program
Check

Type

The zero, fetch, load, and modify functions all deal with loading a PDP16-M application program into core memory.
The application program must be loaded into core memory of the PDP-8/E before a PROM can be loaded or checked
and before the program

application

can

be exercised

PDP16-M for debugging purposes. To debug

program and its

interface, the 8 command must be declared to select the simulate function. The B command stands for

PROGRAM and must be declared to load
program in PDP-8/E

core

PROM. To check the contents of

memory, the C command must be declared.

Finally,

PROM against the application

the T command, which stands for

TYPE, can be declared to list the content of the PROM on the teleprinter.

The 2 function is provided for zeroing the first 60003 locations of core memory. These locations are used as the

application program storage buffer. The application program is loaded into this buffer using the F, L, or M function.
The F function is used to read the program from a PROM; the L and M functions are used to read the program from
a

paper tape.

Loading a tape using the M function will cause the contents of the tape to be echoed on the TTY.

Therefore, unless a printout is desired, the L function should be used to load the tape. The buffer must be zeroed
before loading the application program so that any extraneous data that may be in these locations will not be loaded
into the PROM

checked. The 8 function is used to load a Control

Data PROM and the C function is used to

check the contents of the PROM against the contents of the application program buffer.
Either the

low-speed or high-speed paper-tape reader can be used for loading a paper tape.

6-3

PROGRAM

16-070

SIMULATE

VERIFY
1'

022—032(1)

SKIP
I/O

U<IIIJLLI

FUNCTION

)

AAA
vv

odew

AD R

UdMJlU

Option

vac/vac

AD ”
BYTE
HIGH

101'

LOAD

D
A

n——-—-

DATA

SKIP

‘EN

(09:1 )

(03:

’6

052-030)

BUS

o
c
E
0

08)

DEBUG

DEBUG VERIFY LOAD PWR

READ DATA

EN EN EN EN

T—NOT

—"

.5)
'

DEVICE

DONE

DEBUG

Figure

RDY

Low

MRIfi-SL
6-2

START

1.~_._.___. -——-——-—-> “a —-—-——-—~D ——-—-—~D -—-—-—-—~.
TEST

DATA

SEQ

BYTE

DATA HQ LB SEQ
READ LOAD LOAD START

DATA AD “

DATA

Utility

TIMING

‘1

‘3

”11%;.“me

RED
INT
I/O

(.0
w“

MRIG-SL

\
‘

+62V

PANEL

PAUSE

(0 :1 )

I/O

DATA

DRIVERS/ RECEIVERS

(08:1 )
DATA

FUNCTION DECODER

TEST
EN
E0
5

TART

MBY

Besides loading the application program, the M function can also be used for modifying the application program in
the buffer or inputting a program from the TTY keyboard. Only octal numbers, the % sign, and the 38 sign have any

meaning for the modify function. A % sign followed by an octal number, a RETURN and a LINE FEED sets the
(address) to the value of the octal number. Typing three octal digits, a RETURN, and a LINE
FEED, stores the binary value of the octal number in the memory location pointed to by the program counter. After
an object program resides in the buffer, it can be executed on the application PDP16-M
by selecting the S function,
it can be loaded into a PROM by selecting the B function, or a PROM loaded with the same program can be checked
by selecting the C function. Finally, the T function, which stands for TYPE, can be selected to list the contents of a
program counter

PROM.
6.3.1

Zero, Fetch, Load and Modify

These functions may be used to load the application program object code into PDP-8/ E core

memory

for subsequent
simulation, PROM loading, or PROM checking. After the utility program is loaded and started (SA=60008) by
depressing the PDP-8/ E START switch, the program types:
F
The user may then select the zero, fetch, load, or modify function by typing the corresponding command character.

When first starting, it is recommended to zero the buffer by typing 2 in response to the F query. For example:
FZ

6.3.1.1

Load

—

To load

object tape (punched by the PAL16 Assembler), simply place the tape in the reader

and type L for load. If the tape is in the high-speed reader it will read in. If the low-speed reader

(high or low speed)
is used, push LSR switch to START; after the tape is read, turn the LSR to OFF. Whether the LSR or the HSR is
used to load the tape, the CONT switch on the utility computer console must be depressed to reactivate the utility
program. The program will then type F, requesting another function. The user can now modify the program,
simulate the program, load a PROM, or check a PROM by selecting the appropriate function and performing the
necessary setup procedure. Refer to respective function descriptions.
Modify—The modify function allows the user to change the program stored in core memory or to
manually input a program via the teletype keyboard. To select this function, the user types M in response to F. The
utility computer is now ready to accept the input string. Only octal numbers, the % sign, and the $ sign have any
meaning for the modify function. A % sign followed by an octal number, a RETURN, and a LINE FEED sets the PC
(address) to the value of the octal number. Typing three octal digits, a RETURN, and a LINE FEED stores the
binary value of the octal number in the memory location pointed to by the PC.

6.3.1.2

NOTE
When starting, the PC is always set to 0000; therefore, the %

sign must be used to select memory locations at random.
A $ sign followed by a carriage RETURN and 3 LINE FEED must terminate each input string. After the $ sign and

keys are typed, the program responds by typing F to request the next function. An example of an input
string acceptable to the modify routine follows:

the control

Address (not typed)

Input String
FM

CR LF

300

CR LF

123

CR LF

%100

CR LF

100

CR LF

101

CR LF

102

332

CR LF

103

CR LF

6-5

The modify subroutine looks at only the last three data digits. Therefore, if a typing error is made, the correct three

digits can be typed on the same line without having to reset the PC.
6.3.1.3

Fetch —-The fetch function allows the

user

transcribe

program from

PROM

PDP-8/E

core

memory. To use this function, the user must first insert the PROM to be transcribed into the VERIFY connector of

panel (Figure 6-1). The user can then type F in response to the F query to select the fetch function.
modify the program, simulate the program, load a PROM, or check a PROM by selecting the
appropriate function and performing the necessary setup procedure. Refer to respective function description.

the function

The

user can now

6.3.2

Simulate

This function is used to exercise the program for

4%;

debugging purposes. To use this function, the user must first

connect the PDP16—M on which the program is to be run to the SlMULATE connector on the function panel (Figure

6-1). Optionally, Service Module M7335 and Bus Monitor Module M7322 can be installed in the PDPl6-M to
implement the data and address readout, single step, and break-point debugging features. (Refer to Chapter 5 of the
PDP76-M Maintenance Manual.) The PDP16—M must also be equipped with all the options that are exercised by the

’“

application program.
After the application program is loaded into core memory using the

F, L, or M function, it can be executed on the

application PDP16—M by typing the S command in response to the next F query. When the L function is used in
loading the application program, the PDP-B/E will halt after the $ sign, CR, and LF at the end of the paper tape are
read. The utility program will return by typing F on the teleprinter to request the next function only when CONT
on the PDP-8/E console is depressed. This feature gives the operator time to turn off the low-speed reader. After
turning off the reader and depressing CONT, the user simply types S in response to the F query and depresses the
START switch on the PDP16—M to start the program. The debugging features offered by the maintenance modules
are very useful in debugging the program and the application interface. Therefore, these modules should be used
when debugging a program.

6.3.3

Program

This function is used to load PROMs. To

use

this function the

user

must first install a

refreshed PROM in the

PlROG RAM connector on the function panel (Figure 6-1).
NOTE
A PROM is erased by exposir

it to ultraviolet light.

After the application program is loaded into core memory using the

F, L, or M function, the PROM can be loaded

by typing the 8 command in response to the next F query. The utility program then responds with ROM?. For

example:
i

FB
'

ROM?
The user they types 0, l, 2, or 3, depending on which PROM is to be loaded. Normally, the PROMs are loaded
sequentially from 0 to 3. After the PROM is loaded, the utility program will type F to request another function. For
example:

‘

FB
F

The above

listing indicates that the PROM was loaded successfully and the utility program is requesting another

function. The same procedure is repeated to load other PROMs.

6-6

(Minimum

WWWMWIWWWMWW

‘

6.3.4

Check

This function is used to verify that a PROM is programmed correctly. To use this function the user must first install
the PROM to be checked in the VERIFY connector

the function panel. The

user must

then load the master

application program into core. After the application program is loaded using the F or M function, the PROM can be
checked by typing the C command in response to the next F query. The utility program then responds with ROM?.
For example:
FC

ROM?
The user they types 0, ‘l, 2, or 3, depending on which PROM is to be checked. After the contents of the PROM are

checked against the contents of core memory, the utility program will type OK or X followed by F. For example:
FC

ROM? 0
OK
F

The above listing indicates that the PROM does contain an accurate application program. The same procedure is used
to

check other PROMs. If an X is typed instead of OK, the PROM does not contain a good application program and

must be reloaded.

6.3.5

Type

This function is used to list the contents of a PROM. The instruction codes and addresses stored in the PROM are

typed out as three octal digits. To use this function the user must first install the PROM whose contents are to be
listed in the VERIFY connector on the function panel. The user then simply types T in response to the F query.
After the contents of the PROM are listed, the utility program again types F to request the next function.

6-7

'aimiiaiimm‘fiu
mm it'Wmmm
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'

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‘

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‘

APPENDIX A
PDP-11 PERIPHERAL SUMMARY

A.1

CONTROL AND STATUS REGISTERS

Each

peripheral

has

one

and

control

registers that contain

status

all the information necessary to

communicate with that device. The general form, shown below, does not necessarily apply to every device, but is

presented as a guide.

ERRORS

————-+

BUSY

I
)

4% ,___J

K_.
|

UNlT SELECT
DONE OR READY
lNTERRUPT ENABLE

MEMORY EXTENSION
DEVICE FUNCTION
ENABLE
16-0090

A.2

DATA REGISTERS

registers may contain up to 16 bits of data depending on the type of device. TTY compatible devices
transfer only eight bits of data at a time.

The data

A.3

ASR 33 TE LETYPE

Address

Reader Status Register (TKS)

777560

Reader Buffer Register (TKB)

777562

Punch Status Register (TPS)

777564

Punch Buffer Register (TPB)

777566

A-l

Reader Status Register (TKS)

W1 WW

1111111

$222M

A-2

WWMWWMWIWIMWWWWWWWMWMHMWIWWWWWWWMW“WW%WWMMHWMWWW

A.4

P011 HIGH SPEED READER PUNCH

Address

Papertape Reader Status Register (PRS)
Papertape Reader Buffer (PRB)
Papertape Punch Status (PPS)
Papertape Punch Buffer (PPB)

777550

777552
777554
777556

Papertape Reader Status Register (PR3)

1514

%//////////////AL.%/////////%///

A34

j i

READER INTERRUPT ENABLE
READER ENABLE

0000000

Papertape Reader Buffer (PRB)

DATA

6666666

Papertape Punch Status (PPS)

1514

READY

4W1|1Wm

PUNCH INTERRUPT ENABLE

0000000

Papertape Punch Buffer Register (PPB)

/1/%//1/3///11/2/%//1///‘/////76|514L3l211‘0
J

DATA

A-3

A.5

LP11 LINE PRINTER
Address

777514

Line Printer Data Buffer (LPB)

777516

Line Printer Status Register (LPS)
15

DONE

INTERRUPT ENABLE

AJB

CR11 AND CM11 CARD READER
Address

777160

Card Reader Data Buffer (CRB1)

777162

Card Reader Data Buffer (CRBZ)

777164

Card Reader Status Register (CR5)

ERROR

‘GW

CARD DONE

CARD SUPPLY ERROR
CARD READER CHECK

TlMiNG ERROR
READER TO ON LINE-—-—---———-—-

BUSY

READER READY STATUS
COLUMN DONE

iNTERRUPT ENABLE
EJECT

READ
16-0101

A04

‘11M«fléimuwemmmmmmmmmr

‘
‘

“

”ml

‘mim

‘

“

I“ 11,5111!m»

WWWFWWWWWWWW Wmmfimmmmfimmmmgfimmmm

Card Reader Data Buffer Register (CRBL CRBZ)

ZONE
ZONE

_._.3N

ZONE

WT.T.IILI.,...

ZONE
ZONE
ZONE
ZONE
ZONE
ZONE
ZONE

ZONE
ZONE

@mflmbUN-’O

16-0102

No information can be |oaded into the Card Reader Data Buffer (CRB1) by any program; the content of this register
can

A.7

only be read.

LA30 DECWR ITE R

Address

Register
Keyboard Status Register (KBS)
Keybuffer Register (KBB)
Printer Status Register (PRS)
Printer Buffer Register (PRB)

777560

777562
777564
777566

Keyboard Status Register (KBS)

_A1

DONE
INTERRUPT ENABLE

16*0079

Keyboard Buffer Register (KBB)

16-0081

A-5

Printer Status Register (PR8)

//////////%/////////
lFNETEDR‘RUPT

7////////////////,
l

ENABLE

66666 0

Printer Buffer (PRB)

AFC11 FLYING CAPACITOR
Address

772570

Data Buffer Register (AFBR)

772572

Multiplexer Channel/Gain Register (AFCG)
Maintenance Register (AFMR)

772574

772576

Control and Status Register (AFCS)

DONE

JWHW

lNTERRUPT ENABLE

0000000

Multiplexer Channel/Gain Register 1AFCG1

\___V__.J
GAIN

———-——-———J

CHANNEL ADDRESS

6666666

A-6

‘

‘WWWWWMWWWWWW

Data Buffer Register IAFBR)

3qu

6
'

MAGNITUDE

M88

Maintenance Register (AFMRI

/
//A
7W
INHIBIT MX

KW...)

TIMING—J

I
J

x
v

FILE UNIT

CHANNEL
16-0087

A.9

UDC11 DIGITAL I/O
Address

771776

Scan Register (UJDSR)

771774

Data Registers

771XXX

Control and Status Register (UDCR)
14

llllilll
SCAN ERROR

POWER FAIL

L— __‘,____J

‘

IMMEDIATE INTERRUPT
DEFERRED INTERRUF’T
MAINTENANCE
IMMEDIATE SCAN DONE
RESERVED
DEFERRED SCAN DONE
IMMEDIATE SCAN ENABLE

DEFERRED SCAN ENABLE
IMMEDIATE INTERRUPT
DEFERRED INTERRUPT ENABLE
RESET

16-0083

Scan Register (UDSRI
15

1211

DEF E RRED VALID
P CL

I»

‘

P 0P

GENERIC CODE
SCAN VALUE
I6-0084

A-7

Data Registers

J
16-0076

AA11-D D/A CONVERTER

A.1O

Re ister

Add ess

Command and Status Register (CSR)

776756

Data Register DAC1

776760

Data Register DAC2

775762

Data Register DAC3

776704

Data Register DAC4

776766

Command and Status Register (CSRI

1514131211109876543210

Ll
We

LIGHT PEN FLAG
READY
DISPLAY INHIBIT ENABLE

LIGHT PEN INHIBIT ENABLE
MODE CONTROL

INTENSIFICATION CONTROL
ERASE

INTENSIFICATION
16-0085

Dam Registers (DACI

DAC1 and 2 may be used either in conjunction with the scope or for D/A channels. DAC3 and 4 may be used for
additional D/A channels.

MSB
I

LSB

DATA
I

\‘——-—v—-——“J
SIGN READ

ONLY“—'3

SIGN R/W

10-0103

A-8

Wmmmmmmm

H
I

WWWWWMWWWIE

A.1‘l

ADO‘l-D A/D CONVERTER

Address

Control and Status Register

776770

Data Register

776772

Control and Status Register
Transfer of a 16-bit control word from the PDP-ll to the control and status register (ADCS 776770) establishes the

operating conditions of the ADOl-D.
14

W/iL

5
’/

4L}

\vr'

“—j

ERROR

CHANNEL ADDRESS

DONE
INTERRUPT ENABLE
GAIN SELECT

PRIORITY REQUEST

EXTERNAL CLOCK ENABLE
A/D START
16

0008

Data Register
The A/D Converter Data Register (ADDB-776772) transfers data to the PDP-ll in the following format.

olooooomsel
I
I
1

L38
l

OUTPUT WORD FORMAT-UNIPOLAR OPERATION
15
S

S
_L

S
l

M88
l

O
I

OUTPUT WORD FORMAT- BIPOLAR OPERATION
16-0089

Bits 15 to 10 are tied together, and are 0 in the standard unipolar configuration. With the sign bit option, bits 15 to

10 indicate the sign of the input voltage.

Output Notation Table

Analog Input Voltage

Unipolar

Bipolar
176000

-10.0

177000

5.0

0.0

000000

5.0

001000

9.9902

001777

*For 10V full scale input range: divide by appropriate gain factor for other input ranges.

A-9

1..

WMWWWWEWWWWWWWWWMWWIWWWWWWWMWM

\\\\

APPENDIX B

ASCII AND EBCDIC CHARACTER SET ENCODINGS
USASClI Data Transmission Code
7
Bit Positions

0
0

0
1

0
0

1
1

NUL

DLE

SOH

«DCL

STX

DC1

”-

ETX

D03

EOT

DC4

ENC)

NAK

ACK

SYN

BEL.

ETB

CAN

(

)

SUB

ESC

;

[

{

]

’

p
a

USASCll Data Transmission Code

(Key)
All zeros

DC1

Device control 1

Start of heading

D02

Device control 2

Start of text

DC3

Device control 3

ETX

End of text

DC4

Device control 4

EOT

End of transmission

NAK

ENQ

SYN

Negative acknowledgement
Synchronous/idle

ACK

ETB

End of transmitted block

BEL

Enquiry
Acknowledgement
Bell or attention signal

CAN

Cancel (error in data)

Back space

End of medium

Horizontal tabulation

SUB

Start of special sequence

Line feed

ESC

Escape

Vertical tabulation

Form feed

Information group separator

Carriage return

Information record separator

Shift out

Shift in

DEL

DLE

NUL

SOH

STX

Data link escape
B-1

information file separator

information unit separator
Delete

}
~

DEL

EBCDIC Code

13111
Position:

0,1

NUL

DLE

SOH

505

STX

DC2

SYN

ETX

oc3

RES

BYP

1.1:

ETB

11.

Esc

EOT

g
h
1

DEL

11
o

«M
y

SMM

IFS

IGS

ENQ

IRS

ACK

1115

BEL

CAN
EM

DC4

NAK

;

sue

8
'

'
—

EBCDIC Code

(Key)
NUL

Null

STX

Start of Text

Punch Off

ETX

End of Text

ENO

Horizontal Tab

ACK

Enquire
Acknowledge

Lower Case

BEL

Bell

DEL

Delete
VT

Vertical Tabulation

RES

Restore

New Line

Backspace

Form Feed

Idle

Shift Out

Cursor Control

Shift In

SMM

Start of Manual Message

Digit Select
Start of Significance
Field Separator

BYP

Bypass

SOS

DLE

Data Link Escape

DCI

Device Control 1

DC2

Device Control 2

DC3

Device Control 3

004

Device Control 4

NAK

Line Feed

SYN

Negative Acknowledge
Synchronous Idle

EOB

End of Block (or ETB, End of

CAN

Cancel

Transmission Block)

End of Medium

SUB

Substitute
Information Group Separator

PRE

Prefix (or ESC, Escape)

IGS

Set Mode

IRS

Information Record Separator

IUS

Information Unit Separator

IFS

Information Field Separator

Punch On

Reader Step

Upper Case

1‘“

EOT

End of Transmission

Space

SOH

Start of Heading

A
"

semmwwmmmmwmimamm1

‘
1

mmummmmmmmmnmmmmmmwumwmwm-WWWWWWWWWWWWWW1111111111111111111111111

APPENDIX c
.3.

CONVERSION TABLES

Scales of Notation

2" IN DECIMAL
x

0.001
0002
0.003
c004
0005
0006
0007
0008
0009

1.00069 33874 62581
100138 72557 11335
100208 16050 79633
100277 64359 01078
100347 17485 09503
100416 754.12 38973
100486 38204 23785
1.00556 05803 98468
100625 78234 97782

001
002
003
004
005
006
0.07
0.08
0.09

10
10“

3
46
7

575
346

144
1 750
23 420

1000
0063
0005
0000
0000

000 000 000 000 000
146 314 631. 463 146
075 341 217 270 243
406 111 564 570 651
032 155 613 530 704

03 240
641 100
113 200
360 400
545 000

5
6
7
8
9

0000
0000
0000
0000
0000

002
000
000
000
000

niong

1
2
3

030102 99957
060205 99913
0.90308 99870
120411 99827
150514 99783

132
157
015 327
001 257
000 104
476
206

34625
83549
44133
79107
35623
65665
47927
11265
59830

36293
97035
44916
72894
73095
10398
12471
92248
73615

006
000
000
000
000

676
537
043
003
000

10
11
12
13
14

o 000
0000
0000
0000
0000

000
000
000
000
000

34 327 724 461 500 000
434 157 115 760 200 000
5 43
127 413 542 400 000
67 405 553 164 731 000 000

15
16
17
18

0000
0000
0000
0000

000
000
000
000

000 000 000 022 01
000 000 000 001 63
000 000 000 000 14
000 000 000 000 01

112
1 351
16 432
221 411
657 142

402
035
451
634
036

762
564
210
520
440

log 2 10 IN DECIMAL

nlogz 10
80949
61898
42847
23795
04744

nlog, 10

niong

6
7
8

1.80617 99740
210720 99696
2 40823 99653
2 70926 99610
301029 99566

Addition

85693
66642
47591

19 93156
23.25349
26 57542
29 89735
33.21928

28540
09489

044742

147707.

043127

233602.

Multiplication
Binary Scale

0
O ‘_‘.
O
own-440:1
1
1 - 10

0
0
1

O
O
011.0
1
1
‘

Octal Scale

01';

3.11037

552421.

255760

521305.

~.—

-.-I

—.

0.24276

301556.

0.27426

530661.

1n~,

vT—T

1.61337

611067.

v3:

1.51411

230704.

-—

—

1n.—.

1.11206

404435.

log-ac

033626

754251.

\I'z':

1.32404

746320.

logxr.‘

1.51544

163223.

losze

1.34252

166245.

|n2

0.54271

027760.

3.12305

407267.

163110

3.24464

741136.

2.23273

067355.

vTfi

337 66
657 77
136 32
411 35
264 11

000
000
000
000
000

610 706 64
364 055 37
745 152 75
143 561 06
560 276 4

3.32192
664385
9965713
13.28771
16.609641

1.07177
1 14869
123114
1.31950
1.41421
151571
162450
1.74110
1.86606

01
0.2
0.3
0.4
05
0.6
0.7
0.13
09

IN OCTAL

00
31
66
77
15

log.IO 2,

56719
90029
07193
56067
41377
41121
23067
61380
53360

10"

0
1
2
3
4

1
12

+
_n

2‘

55500
94797
21257
38266
49238
57608
66836
80405
01824

“

100695
101395
1.02101
1.02811
103526
104246
1.04971
1.05701
1.06437

C-1

log1

0.62573 030645.

Powers of Two

-—n
3

omwmaqu—O

O 25

0 125
0.062 U1

01031
0 007

812

O 003

906

0 001

953

0 000 976
O 000

192

0 015 625

244

0 000

122

O 000

061

0 000 030
O 000

015

O 000

007

O 000

003

() 000

001

0 000

000

O 000 000
0 000

000

0 000 000

625

0 000 000

390

O 000

000

695 312

O 000

000
923

828

O 000 000

290

461

914

0 000 000

645

230 957

O 000 000

...

0,000

(1 000

322
000

661

307

739

O 000 000

830

653

869

0 000

000

415

826 934

0 000

000

207

913

467

0 (100

456

733

’) f 100

000

551

438

0 000

000

275

614

183

877

O 000

000

637

807

091

755

O 000

000

818

511

O 000

000

909

701

772

039

023

0 000

000

454

350

886

519

046

O 000

000 000

227

675

443

759

093

0 000 000

837

721

379

418

860

689

422

562

137

1799

625
312
156
078

368

186

O 000

372

0 000

000

028

744

O 000

000

000 014

854

715

488

O "100

(.100

000 000 007

437

357

781

O 1'00

976

185

906

421

000

003

713

678

890

{100

000 000

001

356

839

945

n(X)O

000

1100

000 000

178 419

‘1")!

813

68")

089

209

50.3

622

3/1).

5‘,

O 000

000

044

604

111)]

254

74!)

D 000

000

022

302

'18

Lz14

481

O 000

000 (100 000 000

511

151

404

U88

018

961

U 000

000

I, h)

037

927

O 000

000

877

787

851

075

85‘)

”)1

000

236

618
042

809
702

000
000 013

O 000

000 (700 000 000

938 893

925

151

711

0 000

000 000 000

000 003 469 446

962

303

423

0 000

000

481

846

O 000

213

693

O 000

000 000

018 427

387

O 000

000 000
000 000

1 15

.788

.' 31)

5 76

460

752

152' 931

504

50‘;

843

009

611

686

000 000
000 000

734

723

000 867

361

000

680

433

‘7

223

172

036 854

775

O 000

.146

744

(173

709

551

O 000

000 000

000

I")

891

488

419

103

O 000

000

[86 976

838

206

0 000

000

000 000

312 5

120

560

000 000

625

108 420

280

578

125
5

054

210

640

289 062

027

105

320

644

531

000 000

000 000 013

552

160

822

265 625

000

147

573

952

676

412

O 000

000

000 006

776

580

41 1

132 812

."7‘:

147

905

352

825

O 000

000 000

000

000 003

388

789

290

205

566 406

102

‘91)

.‘95

810

705

651

0 000

000 000 000 000 000 001

694

894

645

180

591

620

411

303

O 000

000 000 000 000 000 000 847

947

322

161

183

241

822

606

O 000

000 000 000 000 000 000 423

473

161

7 3‘)

$66

482

645

213

236

080

‘

7;;

983

125

709 430

‘)

144

“62

000 056

434

0 000 000 000

000 000 000 000 211

820

2.5

783

203

1.35

391

601

562

C25

69’) 800

781

(‘5

512

847

900

390

Cu)“

‘

C-2

WMMWWWIWWW

___

w
H

‘

...H!lfl|fliflillfl!ikié=

Octal-Decimal Integer Conversion Table
2,

__i

0000

0777

0511

(Octal)

(Decimal)

Octal Dechnal
10000- 4096
200005 8192

30000512288
40000-16384
50000-20480
60000-24576
70000-28672

5iiv“

0000
0010
0020
0030
0040
0050
0060
0070

0000

0001
0008 0009
0016 0017
0024 0025
0032 0033
0040 0041
0048 0049
0056 0057

0002
0010

0003 0004 0005 0006 0007

0018
0026

0021
0029
0037

0100
0110

0064
0072

0065
0073

0086
0074

0120
0130

0080
0088

0081
0089
0097
0105
0113
0121

014010096
0150

0104

0160
0170

0112
0120

0200

0128

0210,0136
0220

0144

0230,0152
0240:0160

025010168
0260_0176

027010184

0011
0019

0012
0020
0028
0038

0013

0044

0045

0052
0060

0053
0061

0087

0068

0069

0076

0077

0082

0075
0083

0084

0085

0090

0091

0116

0117

0122

0099
0107
0115
0123

0092
0100
0108

0093

0098
0106

0124

0129
0137

0130

0131

0138

0145
0153
0181

0146

0189
0177
0185

0170
0178

0034

0042
0050
0058

0114

0154
0162

0186

0014
0022
0030
0038
0046
0054
0062

0031
0039
0047
0055
0063

0070
0078
0086

0071
0079
0087

0094
0102
0110

0095

0119

0125

0118
0126

0132

0133

0139

0140

0147
0155
0163

0148
0158
0164

0171
0179
0187

0172
0180
0188

0027
0035
0043
0051
0059

0015
0023

0256
0264
0272
0280
0440 0288
0450 0296

0262
0270
0278
0286

0291
0299
0307
0315

0260 0261
0268 0269
0276 0277
0284 0285
0292 0293
0300 0301
0308 0309
0316 0317

0263
0271
0279
0287
0295
0303
0311
0319

0322
0330
0338
0346
0354
0362
0370
0378

0323
0331
0339
0347

0324
0332
0340
0348

0355
0363
0371

0356
0364
0372
0380

0326
0334
0342
0350
0358
0366
0374

0387
0395

0257
0265
0273
0281
0289
0297
0305
0313

0258
0266
0274
0282

0259
0267
0275
0283

0290
0298
0306
0314

0304

0500
0510
0520
0530
0540
0550

0320

0127

0560
0570

0368
0376

0321
0329
0337
0345
0353
0381
0369
0377

0134

0135

0600

0384

0385

0386

0141

0142

0143

0610

0393

0394

0149

0151

0620

0401

0402

0159

0408
0416
0424

0410

0417

0418

0425

0426

0181
0189

0182
0190

0183
0191

0630
0640
0650
0660

0409

0185
0173

0150
0158
0166
0174

0392
0400

0432

0101
0109

0157

0103
0111

0187
0175

0312

0328
0336
0344
0352
0360

0379

0388
0396
0404
0412
0420
0428
0436

0325
0333
0341

0349
0357
0365
0373
0381

0294
0302
0310
0318

0382

0327
0335
0343
0351
0359
0367
0375
0383

0389
0397
0405

0390
0398
0406

0413

0414

0421

0422
0430

0391
0399
0407
0415
0423
0431

0438
0446

0439
0447
0455
0463

0433

0434

0403
0411
0419
0427
0435

0670.0440 0441

0442

0443

0444

0445

0700:0448

0449

0450

0451

0454

0458

0459
0467
0475

0452
0460

0453

0457
0465

0461

0462

0469
0477
0485
0493
0501

0470
0478
0486
0494

0509

0510

0471
0479
0487
0495
0503
0511

0774

0775

0429
0437

0192

0193

0194

031010200

0201
0209
0217

0249

0202
0210
0218
0226
0234
0242
0250

1032010208
l0330i0216 0225
1034010224

l035070232 0233
0241
[0360:0240
[037010248

0400
0410
0420
0430

0460
0470

I
0300

0195
0203
0211
0219

0196

0227
0235
0243
0251

0197
0205
0213
0221
0229
0237
0245
0253

0198

0204
0212
0220
0228
0236
0244
0252

0222
0230
0238
0246
0254

0223
0231

0515
0523
0531

0516

0517

0524

0525

0532

0539
0547

0540
0548
0556
0564
0572

0533
0541
0549

0206
0214

0199
0207
0215

0239

3071010456
072010464

0497
0505

0466
0474
0482
0490
0498
0506

0788

073010472

0740
0750

0480
0488

0247

076010496

0255

077010504

0518
0526
0534
0542
0550
0558
0566
0574

0519

1400

0527

1410j0775

0582
0590
0598

0583
0591
0599

0606

0473
0481
0489

0483

0468
0476
0484

0499
0507

0492
0500
0508

0770

0771

0491

0502

l
.

07‘

1000
to
1777

0512

1000

0512

0513

0514

1010

0520

0521

1020.0528

0529

0536

0537

0544

0545

0522
0530
0538
0546

1050;0552

0553

1 1023
(OctaD l(Decimal)

1030
1040

106010560 056!
0569
1070;0568

110010576

0577

0578

1110

0584

0535

1120

0592

0593
0601
0609
0617
0625
0633

0586
0594
0602
0610
0618
0626
0634

1130’0600
ll40!0608
115010616

1160;0624

1170;0632

1200’0640

iiivV

0554
0562
0570

0555
0563

0571
0579
0587
0695
0603
061!

0580

0557
0565

0573
0581

0619

0589
0596 0597
0604 0605
0612 0613
0620 0621

0627

0628

0629

0635

0636

0637

0588

0543

1430:0792

0769
0777
0785
0793

0551

1440

0535

1420'0784
0800

0801

0559

1450;0308

0309

0567

1460:0816

0817
0825

0575

1470;0824

0841

152010848

0849

1530;0356

0357

0614
0622
0630
0638

0607
0615
0623
0631
0639

1550'0872
1550 0880
1570 0888

0873
0661

0656
0866
0874
0882

0889

0890

0646
0654

0647
0655

1600
1610

0904

0663
0671
0679
0687

1620

0912

1630
1640

0897
0905
0913
0921
0929
0937
0945
0953

154010864 0865

0643
0651

0644
0652

0658

0659

0660

0645
0653
0661

123020664
1240:0672
125050680

0665

0666

0673

0674
0682

0667
0675

0668
0676

0669
0677

0662
0670
0678

0683

0684

0685

0686

0688

0689

0691

0692

0693

0895

1660

0699

0700

0701

0694
0702

0920
0928
0936
0944

0703

1670

0952

0707
0715
0723

0708

0709

0710

0711

1700

0960

0716

0717

0968

0961
0969

0724

0725

1720

0976

0977

0732
0740
0748

0733
0741

0719
0727
0735

1710

0731
0739
0747

0718
0726
0734

1730

0985

0756
0764

0743
0751
0759
0767

1740

0755
0763

0742
0750
0758
0766

1750
1760

0984
0992
1000
1008

1770

1016

1260

0681

127010696 0697

0690
0698

0842
0850

151010840

0642
0650

122050656

0310
0818
0826

0772 0773
0779 0780 0781
0787 0788 0789
0795 0796 0797
0803 0804 0805
0611 0812 0813
0819 0820 0821
0827 0828 0829

0782

0783

0790

0798
0808

0791
0799
0807

0814
0822
0830

0815
0823
0831

1500:0832 0833 0834 0835 0838 0837 0838 0839

0641
0649
0657

1210.0648

0773
0786
0794
0802

1650

0896

0843
0851
0859
0867
0875
0683
0891

0844 0845
0852 0853
0860 0861
0868 0869
0876 0877
0884 0885
0892 0893

0846

0847

0854
0862
0870
0878
0886
0894

0855

0900
0908
0916

0910

0903
0911

0918

0919

0863
0871
0879
0887
0895

0899
0907
0915
0923
0931
0939
0947
0955

0901
0909
0917
0924 0925
0932 0933
0940 0941
0948 0949
0956 0957

0902

0958

0959

0963
0971
0979
0986 0987
0994 0995
1002 1003
1010 1011
1018 1019

0964 0965
0972 0973
0980 0981
0988 0989
0996 0997
1004 1005
1012 1013
1020 1021

0966

0967
0975
0983
0991
0999
1007
1015
1023

0898
0906
0914
0922

0930
0938
0946
0954

0926 0927
0934 0935
0942 0943
0950 0951

130010704
131010712

0705

0706

0713
0721

0714

133010728 0729

0730

0737

132010720

1350'0744

0745

0738
0746

1360

0752

0753

0754

1370

0760

0761

0762

1390|0736
31

'41:

.5"

0722

0749
0757
0765

0993
1001
1009
1017

0962
0970
0978

0974
0982
0990
0998
1006
1014
1022

Octal-Decimal Integer Conversion Table (Cont)

,__._——_.—

1025
1033

1026

202071040

1041

1042

1027
1035
1043

1028

201011032

2000:1024

1029
1037
1045

1030
1038
1046

1031
1039
1047

2400
2410
2420

1280

1281

1282

1269
1297
1305
1313
1321
1329
1337

1290
1298
1306
1314
1322
1330
1336

1283
1291
1299
1307
1315
1323
1331
1339

1284
1292

1285
1293
1301
1309
1317
1325
1333
1341

1266
1294
1302
1310
1316

1287
1295
1303
1311
1319
1327
1335
1343

1345
1353
1361
1369
1377
1385
1393

1346
1354
1362
1370
1376
1386
1394

1350

1401

1409

1053

1054

1055

2430

1288
1296
1304

1061

1062
1070

1063

2440

1312

1069

1071

1077

1078

1079

1065

1086

1087

2450
2460
2470

1320
1328
1336

1092
1100

1093

1094

1101

1102

1095
1103

1108
1116

1109

1110

1111

1117

1119

1127

2500
2510
2520
2530
2540
2550
2560
2570

1344
1352
1360
1368
1376
1364
1392
1400
1406
1416
1424
1432

1215

2600
2610
2620
2630
2640
2650
2660
2670

l2300'1216 1217 1218 1219 1220 1221 1222 1223

2700

1034

1051
1059
1067

1036

1044
1052
1060
1068
1076
1084

203011048

1049

1050

2040

1056

1057

2050

1064
1072

1065
1073

1056
1066
1074

207011080

1081

1082

1075
1083

2100‘1086

1089

1090

1091

2110.1096
2120:1104

1097

1098

1099

1105

1106

1107

213011112

1113
1121
1129
1137

1114

1115

1122

1124

1125

1130

1:23
1131

2060

1120

2140

213011128
216011136

1217011144

1132

x133

1116
1126
1134

1138

1139

1140

1141

1142

1143

1145

1146

1147

1148

1149

1150

1151

1153
1161

1154
1162

1155

1156
1164

1157

1158

1165

1166
1174

1135

1300

1308
1316
1324
1332
1340

1326
1334

1342

1348

1402

1347
1355
1363
1371
1379
1367
1395
1403

1380
1388
1396
1404

1349
1357
1365
1373
1361
1389
1397
1405

1410
1418

1411
1419

1412
1420

1413
1421

1414

1429

1430

1437
1445
1453
1461
1469

1438

1356
1364
1372

1358
1366
1374
1362
1390
1398
1406

1351
1359
1367
1375
1383
1391
1399

1024

2000
to

2777

1535

(Octal)

(Decimal)

5"50
'

‘

Octal Decimal
10000- 4096
20000- 8192
30000-12288
40000516384
50000-20480
60000-24576
70000-28672

#95;

1407

1220011152

I2210‘ll60

1163

1173
1181
1189

1159
1167
1175

1168 1169 1170 1171 1172
12220
1182 1183
522321176 1177 1178 1179 1180
1190 1191
1184 1185 1186 1187 1188
12240
2250,1192 1193 1194 1195 1196 1197 1198 1199

226011200

1201

1202

!2270il208

1209

1210

1203
1211

1204
1212

1205

1213

1206
1214

1207

1440

1448

1417

1425

1426

1427

1428

1433

1434

1435

1436

1441

1442

1444

1449

1443
1451
1459
1467

1475
1483
1491

1476
1484
1492
1500
1508
1516
1524
1532

1456

1457

1450
1458

1464

1465

1466

1472
1480
1488
1496
1504

1474

1482
1490
1498
1506

1512

1473
1481
1489
1497
1505
1513

1520

1521

1522

1528

1529

1530

1507
1515
1523
1531

3400
3410
3420
3430
3440
3450
3460
3470

1792
1800
1808
1816
1824
1832
1640
1846

1793
1801

1794

1795
1803
1811
1819
1827
1835
1843
1851

3500
3510
3520
3530
3540
3550
3560
3570

1856
1664
1872
1680
1888
1896

1857
1865
1873
1881
1869
1897

1904

1905

1858
1866
1874
1882
1890
1898
1906

1912

1913

1914

1920

1921

1922

1928
1944
1952
1960
1968
1976

1929
1937
1945
1953
1961
1969
1977

1930
1938
1946
1954
1962
1970
1978

1923
1931
1939
1947
1955
1963
1971
1979

1964
1992
2000
2008
2016
2024
2032
2040

1965
1993
2001
2009
2017
2025
2033
2041

1986

1987

1994
2002
2010
2016
2026
2034
2042

1995
2003
2011
2019
2027
2035
2043

1452
1460
1468

1422

1446
1454
1462
1470

1415
1423
1431
1439
1447
1455
1463
1471

12310 1224

1225
1233

1226
1234

1227

12330
1234011248

1241

1242

1243

1249

1250

.235011256

1257

[236011264

1265

1258
1266
1274

1251
1259
1267

1232
1240

,2320

1237011272_}273

13000

13010

1235

1275

1228
1236
1244
1252
1260
1268
1276

1229
1237
1245
1253

1261
1269

1277

1230
1236
1246
1254
1262
1270
1276

1231
1239
1247
1255
1263
1271
1279

1536

1537
1545

1536

1539
1547
1555

1540
1546

1541

1542

1546

1549

1543
1551

1544

3030‘1560

1553
1561

304011568

1569

3050-1576

306011584

1577
1585

3070:1592

1593
1601

13020'1552

1554

1556
1564
1572
1580
1566
1596

1557

1550
1558

1565
1573

1566
1574

1567
1575

1581

1583

1597

1582
1590
1598

1605
1613

1606
1614

1607
1615

1622
1630
1638
1646
1654

1623
1631
1639
1647

1662

1655
1663

1670

1671

1562
1570
1578

1563

1586

1587

1594

1595

1602
1610
1618

1603 1604
1611 1612
1619 1620
1627 1626
1635 1636
1643 1644

1571
1579

1569

1559

1591
1599

2710
2720
2730
2740
2750
2760
2770

1809
1817
1825
1633
1841
1849

1514

1802
1610
1818
1826
1834
1842
1650

1499

1477
1485

1493
1501

1478
1466
1494

1479
1487
1495
1503
1511
1519

1509

1502
1510

1517
1525
1533

1534

1535

1796

1797
1805
1813
1821
1829
1837
1845
1853

1798

1799
1807
1815
1823
1831
1839
1847
1655

1804
1812

1620
1826
1836
1844
1852

1518
1526

1806
1814
1822
1830
1638
1846
1854

1527

I
3000

1536

3777

2047

(Octan

(Decnnan

1600
1606

3100
3110

3120'1616

313011624

314011632

315011640
316011648

3170‘1656
1664

3200

1609

1617
1625
1633
1641
1649
1657
1665

1626
1634
1642
1650
1658
1666

1659

1652
1660

1621
1629
1637
1645
1653
1661

1667

1668

1669

1651

321011672 1673 1674 1675 1676 1677 1678 1679
322011680

1661

1682

1663

1666

1690
1696

1684
1692
1700
1706
1716
1724

1685

1689

1693
1701
1709
1717

1694
1702

1733
1741
1749
1757

3260€|7l2

1713

1720

1721

1722

1691
1699
1707
1715
1723

1728

1729

1730

1731

1732

3310;1736

1737
1745
1753
1761
1769
1777
1785

1736
1746
1754
1762

1739

1770
1778
1786

1771
1779
1787

1740
1748
1756
1764
1772
1780
1788

323011638

324011696 1697

325011704
3270

1705

1706
1714

1725

1710
1716
1726

1667
1695
1703
1711
1719
1727

3600
3610
3620
3630
3640
3650
3660
3670

1936

1659
1667
1675
1663
1891
1699
1907
1915

1661

1876
1884

1869
1877
1865

1892
1900
1908
1916

1693
1901
1909
1917

1924

1925
1933
1941
1949
1957

1926
1934
1942

1927
1935
1943

1950
1958

1951
1959

1965
1973
1981

1966
1974

1967
1975

1982

1983

1989 1990
1997 1998
2005 2006
2012 2013 2014
2020 2021 2022
2028 2029 2030
2036 2037 2038
2044 2045 2046

1991
1999
2007
2015
2023
2031
2039
2047

1932
1940
1946
1956
1964
1972
1980

1662
1870
1878
1666
1894
1902
1910
1918

1663

1660
1866

1671

1879
1687
1895
1903
1911
1919

3300

332011744
3330 1752
13340

1760

13350

1768
1776
1784

13360

13370

1747
1755
1763

1765
1773
1781
1769

1734

1735

1742
1750
1758
1766
1774

1743
1751

1782
1790

1759
1767
1775
1763
1791

3700
3710
3720
3730
3740
3750
3760
3770

1986
1996
2004

AWE1

(244

.2521811mm111mmmmm11m 7

1:1

11773WEHMNMMMEWflWMHmemWWMflWWWHWMWMHM1M““WW”‘V“#“ww

‘

”““WWMflflWWMWflmwwflflflflmWfifiwmmmMWWW33

Octal-Decimal Integer Conversion Table (Cont)

2049

2050
2058
2066

2051

2054 2055
2059
2062 2063
2067 2068 2069 2070 2071
2075 2076 2077 2078 2079
2083 2084 2085 2086 2087
2091 2092 2093 2094 2095
2099 2100 2101 2102 2103
2107 2108 2109 2110 2111

4400

2115 2116
2123 2124
2131 2132
2139 2140
2147 2148
2155 2156
2163 2164
2171 2172

2117

450012368 2369 2370 2371

2177 2178 2179 2180
2185 2186 2187 2188
2192 2193 2194 2195 2196
2200 2201 2202 2203 2204
4240 2208 2209 2210 2211 2212
4250 2216 2217 2218 2219 2220
4260 2224 2225 2226 2227 2228
4270 2232 2233 2234 2235 2236

2181
2189

4000

2048

to
4777

2559

(Octal) (Decimal)
Octal Decimal
10000- 4096
20000~ 8192
30000~12288
40000~16384
50000~20480
60000-24576
70000~28672

4000

2048
4010 2056
4020 2064
4030 2072
4040 2080
4050 2088
4060 2996
4070 2104
4100
4110

2112

2113

2120

2121

2114
2122

4120

2128

2129
2136 2137
2144 2145
2152 2153
2160 2161
2168 2169

2130
2138
2146
2154
2162
2170

4130
4140

4150

4160
4170
4200
4210
4220
4230

2176
2184

4300
4310
4320
4330

2240

2241

2248

2249

2256

2257

2264
2272
2280
2288

4340

4350
4360

d31012296
,2

2560

5777

3071

(Octal)

(Decimal)

2242
2250
2258
2265 2266
2273 2274
2281 2282
2289 2290
2297 2298

2118
2126
2134

2119
2125
2127
2133
2135
2141 2142 2143
2149 2150 2151
2157 2158 2159
2165 2166 2167
2173 2174 2175

2197
2205
2213
2221
2229

2237

2243 2244 2245
2251 2252 2253
2259 2260 2261
2267 2268 2269
2275 2276 2277
2283 2284 2285
2291 2292 2293
2299 2300 2301

2560
501012568
5020 2576
5030 2584
5040 2592
5050 2600

2376

2377

2378

4520:2384
453012392
4540:2400
4550:2408

2385
2393

2386
2394

2416

2401
2409
2417

4570:2424

2425

2402
2410
2418
2426

4510

4560

2497 2498 2499 2500 2501
4700:2496
471012504 2505

2270
2278

2286
2294
2302

467052488

2513

2271

4730’2520

2279
2287

474012528

2521
2529
2537

2295

476022544 2545

2303;

477012552 2553 2554

475012536

[70

2607
2615
2623

5450'2856

2619

5100 2624
5110 2632
5120'2640
5130 2648
5140 2656

2625
2633
2641

2626

2627
2635
2643

515012664

2665

2658
2666

5160

2672

2673

2674

2667
2675

5170

2680

2681

2682

2683

2564
2572

2873

2874

2881

2882

2883

2686

2687

520012688 2689 2690 2691

2692

2693

2694

2695

2700
2708
2716

2701

2702
2710

2703
2711

2724

2709
2717
2725

2732
2740
2748

2733
2741
2749

2757

2758 2759
2766 2767
2774 2775
2782 2783
2790 2791
2798 2799
2806 2807
2814 2815

2697
2705
2713
2721

2698

2699

2706

2707

525012728 2729
5260?2736 2737

2730

2723
2731

2738
2748

2739
2747

523022712
524012720

5270:2744

530012752

2745
753

2714
2722

2754

2715

2755

2756

531032760 2761 2762 2763 2764 2765

5320‘2768
5330

2776

5340'2784
5350'2792
5360

2600

537012808

2769
2777
2785

2793
2801
2809

2770
2778
2786
2794
2802
2010

2771
2779
2787
2795
2803
2811

2773
2780 2781
2788 2789
2796 2797
2804 2805
2812 2813

2772

2837
2845

2853
2861
2869

2905

2906

2907

2908

2909

2910

2911

2913 2914 2915 2916 2917 2918 2919
5540:2912
5550 2920 2921 2922 2923 2924 2925 2926 2927
5560

2928

5570}2936

2929
2937

2930
2938

2931
2939

2932

2933

2934

2940

2941

2942

2935
2943

2951
560022944 2945 2946 2947 2948 2949 2950
2958 2959
5610

2952
5620‘2960

2719

563012968

2726

2727

5640!2976

2734

2735

2742
750

2743

5650
5660
5670

2884

2829

2502

2890 2891 2892 2893 2894 2895
551012888 2889
2897 2898 2899 2900 2901 2902 2903

2718

2751

2887

2872

2663
2671
2679

2696
2704

2886

2850
2858
2866

2662
2670
2678

5210
5220

2885

2864

2849
2857
2865

2654

2823
2831
2839
2847
2855
2863
2871
2878

544012848

5520|2896
553012904

2659

2877

2822
2830
2838
2846
2854
2862
2870
2878

2842

550012880

2651

2821

2517
2525

2641

2647
2655

2649
2657

2516

2840

2631
2639

2637

2509

2820
2827 2828
2835 2836
2843 2844
2851 2852
2859 2860
2867 2868
2875 2876

5460
5470

2471
2479
2407
2495

2508

2818
2826
2834

2646

2629

2836
2644

2819

2493

2486
2494

2463

2555

2817

2485

2462
2470
2478

2556

2532
2540
2543

2477

2533
2541
2549
2557

2524

2461
2469

2503
2511
2519
2527
2535
2543
2551
2559

2531
2539
2547

2438 2439
2446 2447
2453 2454 2455

2437
2445

2510
2518
2526
2534
2542
2550
2558

2507
2515
2523

2825
2833

2630
2638

2028

2522
2530
2538
2546

2435 2436
2443 2444
2451 2452
2459 2460
2467 2468
2475 2476
2483 2484
2491 2492

2824
2832

5410

2645
2652 2653
2660 2661
2668 2669
2676 2677
2684 2685

2634
2642
2650

2506
2514

472012512

5420
5430

2518

2421

2429

2255
2263

2482
2490

2583
2591
2599

2617

2399
2407
2415
2423
2431

2247

2481
2489

4660.2480

5400:2916

2616

2398
2406
2414
2422
2430

2262

4650§2472

2466
2474

2567
2575

5070

2397
2405
2413

2254

2465
2473

2565 2566
2573 2574
2580 2581 2582
2568 2589 2590
2596 2597 2598
834 2605 2606
2612 2613 2614
2620 2621 2622

2611

2391

2246

2458

2464

4640

2563
2571
2579
2587
2595
2603

2608

2383

2390

2449

2562
2570
2578

5060

2382

4620-2448

2434
2442
2450

463012456 2457

2561

2593
2601
2609

2374

2433
2441

2586
2594
2602
2610

2411
2419
2427

2396
2404
2412
2420
2428

2375

2373
2381
2389

2432

2577

2395
2403

2372
2380
2388

2440

2585

2379
2387

4610

2569

2315
2323
2331
2339
2347
2355
2363

2309 2310 2311
2317 2318 2319
2325 2326 2327
2333 2334 2335
2341 2342 2343
2349 2350 2351
2357 2358 2359
2365 2366 2367

4600

5000

2314
2322
2330
2338
2346
2354
2362

2308
2316
2324
2332
2340
2348
2356
2364

2183
2191
2199
2207
2214 2215
2222 2223
2230 2231
2238 2239

4470|2360

2306 2307

2190
2198
2206

2304 2305
4410 2312 2313
4420 2320 2321
4430.2328 2329
444012336 2337
4450 2344 2345
4460 2352 2353
2361

2182

l
1

5000

2057
2065
2073 2074
2081 2082
2089 2090
2097 2098
2105 2106

2052 2053
2060 2061

2984
2992
3000

2953

2954

2961
2969
2977
2985
2993

2962

3001

2970

2978
2986
2994
3002

3010
3018
3026
3024
3032 3033 3034
5740 3040 3041 3042
5750 3049 3049 3050
5760 3056 3057 3058
5770 3064 3065 3066

5700

5710
5720
5730

3008
3016

3009
3017
3025

2956
2964
2972
2980
2988
2996
3003 3004

2955
2963
2971
2979
2987
2995

2957
2965 2966
2973 2974
2981 2982
2989 2990
2997 2998
3005 3006

3012 3013
3020 3021
3028 3029
3036 3037
3043 3044 3045
3051 3052 3053
3059 3060 3061
3067 3068 3069

3011
3019
3027
3035

2967
2975
2963
2991
2999
3007

3015
3023
3031
3038 3039
3046 3047
3054 3055
3062 3063
3070 3071

3014

3022
3030

Octal-Decimal Integer Conversion Table (Cont)

600013072 3073 3074 3075 3076 3077 3078 3079

601013080

6020 3088
6030‘3096
6040 3104

605013112
606013120
607013128

3081

3089
3097
3105
3113
3121
3129

3082
3090
3098
3106
3114
3122
3130

3083
3091
3099
3107

3138

3139
3147

3115

3123
3131

3084
3092
3100
3108
3116
3124
3132

3085
3093
3101
3109
3117

3140
3148
3156
3164
3172
3180
3188
3196

3330
3338

3332
3340
3348
3356
3364
3372
3380
3388

3333
3341
3349
3357
3365
3373
3381
3389

3334
3342
3350
3358
3366
3374
3382
3390

3335
3343

6000

3346
3354
3362
3370
3378
3386

3331
3339
3347
3355
3363
3371
3379
3387

3351

6777

3359
3367
3375
3383
3391

(0cta1)

3394
3402
3410
3418
3426
3434
3442
3450

3395
3403
3411
3419
3427
3435
3443
3451

3396
3404
3412
3420
3428
3436

3397
3405
3413
3421
3429
3437
3445
3453

3398
3406
3414
3422
3430
3438
3446
3454

6600:3456 3457 3458 3459 3460 3461

3462
3470
3478
3486
3494

3087
3095

3125
3133

3086
3094
3102
3110
3118
3126
3134

3141
3149

3142
3150

3143

3157

3158

3159

3165
3173
3181
3189
3197

3166
3174

3167
3175
3183
3191
3199

3103
3111
3119
3127
3135

6400
6410

3328 3329
3336 3337
3344 3345
3352 3353
3360 3361

6420
6430
6440
6450
6460
6470

3368

3376
3384

3369
3377
3385

611013144

6120:3152
6130

3160

6140?3168
615073176
6160'3184
6170 3192

1%3

(Decimal)

Octal DecimaI
4096
10000
3192
20000
30000 12288
40000 16384
50000-20480
60000-24576
70000-28672
-

610013136

3072

3137
3145
3153
3161
3169
3177

3146
3154

3162
3170
3178

3185

3186

3193

3194

3155
3163
3171
3179
3187
3195

3182
3190

3198

3151

6500
6510
6520

3392
3400
3408

6530,3416
6540

3424

6550,3432
6560:3440
3448

6570

3393
3401
3409
3417
3425
3433
3441
3449

3444

3452

3399
3407
3415
3423
3431
3439
3447

—

3455

3200
3208

56200
'6210
6220

3216
3224

3201
3209
3217

3202
3210

3203
3211
3219

3242
3250
3258

3235
3243
3251
3259

3204
3212
3220
3228
3236
3244
3252
3260

3205
3213
3221
3229
3237
3245
3253
3261

3268

3269
3277

3218

3206

3214
3222
3230

3207
3215

3465

3466

3473
3481
3489
3497
3505
3513

3474

3506
3514

3467
3475
3483
3491
3499
3507
3515

f670013520 3521

3522
3530
3538
3546
3554
3562
3570
3578

{661033464

3472

26620

3262

3223
3231
3239
3247
3255
3263

1666013504
1667013512

3270

3271

3278

3326

3279
3287
3295
3303
3311
3319
3327

7000‘3584 3585 3586 3587 3588 3589

3590

3591

3597
3605
3613
3621
3629
3637
3645

3598
3606
3614
3622
3630
3638
3646

3599
3607

3652 3653
3660 3661
3668 3669
3676 3677
3684 3685
3692 3693
3700 3701
3708 3709

3654
3662
3670

3716 3717
3724 3725
3732 3733
3740 3741
3748 3749
3756 3757
3764 3765
3772 3773

3718
3726
3734
3742
3750
3758
3766
3774

3719
3727

3780
3733
3795
3394
3312
3820
3323

3781
3739

3938

3337

3732
3790
3798
3806
3814
3822
3830
3838

3733
3791
3799
3307
3815
3823
3831
3839

6230

3225

624013232

3233

625013240

3241

626013248

3249

627013256

3257

3226
3234

3227

3264

3265

.6310'3272

3273

16320

3280
3288

:6340

3296
3304
3312
3320

3281
3289
3297
3305
3313
3321

3266
3274
3282
3290
3298
3306
3314
3322

3267
3275
3283
3291
3299
3307
3315
3323

3276
3284
3292
3300
3308
3316
3324

3285
3293
3301
3309
3317
3325

26300
'6330

'6350

j6360

19370

1.7
7010 3592
702013600

3593
3601

3609
703013608
7040 3616 3617

705033624

3625

706013632 3633

7070g3640 3641

3596
3602 3603 3604
3610 3611 3612
3618 3619 3620
3626 3627 3628
3634 3635 3636
3642 3643 3644

3594

3595

711013656

3649
3657

3650
3658

3651
3659

712013664

3665

3673
3681

3666
3674
3682

3667

713013672

3648

7100

3680

7140

715013688 3689

3690

3697
3705

3698
3706

7160

3696

7170

3704

3675

3683
3691
3699
3707

3238

3246
3254

3286
3294
3302
3310
3318

3678
3686
3694

3702
3710

3615
3623
3631
3639
3647
3655
3663
3671
3679

3687
3695
3703
3711

663013480
.664013488

1665013496

671013528

3529

.672013536

3537
3545
3553
3561
3569

673013544
6740

3552

16750

3560
3568

j6760

1677013576 3577

3482
3490
3498

3468
3476

3516

3469
3477
3485
3493
3501
3509
3517

3523
3531
3539
3547
3555
3563
3571
3579

3524
3532
3540
3548
3556
3564
3572
3580

3525
3533
3541
3549
3557
3565
3573
3581

3484

3492
3500
3508

3502

3463
3471
3479
3487
3495
3503

3510
3513

3511

3526
3534
3542
3550
3558
3566
3574
3582

3527
3535
3543
3551
3559
3567
3575
3583

3519

3847
1740013840 3841 3842 3843 3844 3845 3846 3855

7000
to

3863
3871
3879
3887
3895
3903

7777

4095

(Octal)

(Decimal)

1741013848 3849

3850

3851

3852

1742013856

3858
3866
3874
3882
3890
3898

3859
3867
3875
3883
3891
3899

3860
3868
3876
3884
3892
3900
3908
3916
3924
3932

'743013864
744013872
745013880

3857
3865
3873
3881
3889
3897

3853
3861
3869
3877
3885
3893
3901

3854
3862
3870
3878
3886
3894
3902

3909
3917

3910
3918
3926
3934
3942
3950
3958

7460
7470

3888
3896

7500
7510

3904

3905

3906

3912

3913
3921

3914
3922

3928

3929

7540'3936

3937
3945
3953
3961

3930
3938
3946
3954
3962

3907
3915
3923
3931
3939
3947
3955
3963

3985
3993
4001
4009
4017
4025

3970
3978
3986
3994
4002
4010
4018
4026

3971 3972
3979 3980
3987 3988
3995 3996
4003 4004
4011 4012
4019 4020
4027 4028

3973 3974 3975
3981 3982 3983
3989 3990 3991
3997 3998 3999
4005 4006 4007
4013 4014 4015
4021 1022 4023
4029 4030 4031

4033

4034

4038

4042

4049

4050

4035
4043
4051

4037

4041

4045
4053
4061
4069
4077
4085
4093

4046
4054
4062
4070
4078
4086
4094

752013920
7530

7550

7560
7570

3944
3952

3960

3940
3948
3956
3964

3925

3933
3941
3949
3957
3965

3966

3911
3919
3927
3935
3943
3951
3959
3967

720013712 3713 3714 3715
721013720

3721

3728 3429
3736 3737
7240 3744 3745
7250 3752 3753
7260 3760 3761
7270,3768 3769

7220
7230

7300
7310
7320
7330
7340
7353
7360
7370

3775
3784
3792
3300
3808
3816
3824
3832

3777
3785
3793
3301
3809
3817
3825
3833

3722
3730

3738
3746
3754
3762
3770
77a
3786
3794
3902
3810
3818

3826
3834

3723
3731
3739
3747
3755
3763

3771
3779
3787
3795
3303
3811
3819
3827
3835

3797

3305
3313
3321
3329

3735
3743
3751
3759
3767
3775

7600 3968
7610 3976
7620 3984
7630 3992
7640 4000
7650 4008
7660 4016
7670 4024
7700
7710
7720
7730
7740
7750
7760
7770

4032
4040
4048
4058
4064
4072
4080
4088

3969
3977

4057
4065
4073
4081
4089

4058

4059

4066
4074

4067
4075

4082
4090

4036
4044
4052
4060

4068
4076
4083 4084
4091 4092

70WWW“mmmwmmflmHflflflflwmflmmflflflflmummnlflmmmHulumugmnmmummmummmmmmmmmwummwwwmmu,umw«w1ww‘nmwa

4039
4047
4055
4063
4071
4079

4087
4095

3584

M
,

Octal-Decimal Fraction Conversion Table

()ctal

Decimal

Octal

Decimal

Octal

Decimal

Octal

Decimal

.000

.000000

.100

.125000

.200

.250000

.300

.375000

.001

.001953

.101

.126053

.201

.251353

.301

.370953

.002

.003906

.102

.126006

.202

.253906

.302

.376306

.003

.005659

.103

.130859

.203

.255859

.303

.380859

.004

.0078l2

.104

.132512

.204

.257612

.304

.382812

.005

.009765

.105

.134765

.205

.259765

.305

.334765

.006

.011716

.106

.136716

.206

.261716

.306

.386718

.007

.013671

.107

.136671

.207

.263671

.307

.363671

.010

.015625

.110

.140625

.210

.265625

.310

.390625

.011

.017573

.111

.142576

.211

.267576

.311

.302575

.012

.019531

.112

.144531

.212

.269531

.312

.394531

.013

.021464

.113

.146464

.213

.271464

.313

.306464

.014

.023437

.114

.146437

.214

.273437

.314

.336437

.015

.025390

.115

.215

.275390

.315

.400300

.016

.027343

.116

.150390
.152343

.216

.277343

.316

.402343

.017

.029296

.117

.154296

.217

.279296

.317

.404296

.020

.031250

.120

.156250

.220

.281250

.320

.406250

.021

.033203

.121

.158203

.221

.263203

.321

.406203

.022

.035156

.122

.160156

.222

.285l56

.322

.410156

.023

.123

.162109

.223

.287109

.323

.412109

.124

.164062

.224

.289062

.324

.414062

.025

.037109
.039062
.041015

.125

.166015

.225

.291015

.325

.416015

.026

.042968

.126

.167968

.226

.292968

.326

.417066

.027

.044921

.127

.169921

.227

.294921

.327

.419921

.030

.046675

.130

.171675

.230

.296675

.330

.421875

.031

.046626

.131

.173828

.231

.298828

.331

.423828

.032

.050781

.132

.175761

.232

.300761

.332

.425761

.033

.052734

.133

.177734

.233

.302734

.333

.427734

.034

.054667

.134

.179687

.234

.304667

.334

.429667

.035

.056640

.135

.161640

.235

.306640

.335

.431640

.036

.056593

.136

.183593

.236

.308593

.336

.433593

.037

.060546

.137

.165546

.237

.310546

.337

.435546

.040

.062500

.140

.157500

.240

.312500

.340

.437500

.041

.064453

.141

.160453

.241

.314453

.341

.439453

.042

.066406

.142

.191406

.242

.316406

.342

.441406

.043

.063359

.143

.193359

.243

.316359

.343

.443359

.044

.070312

.144

.195312

.244

.320312

.344

.445312

.045

.072265

.145

.197265

.245

.322265

.345

.447265

.046

.074216

.146

.199215

.246

.324216

.346

.449216

.047

.076171

.147

.201171

.247

.326171

.347

.451171

.050

.075125

.150

.203125

.250

.328125

.350

.453125

.051

.060076

.151

.205076

.251

.330076

.351

.455078

.052

.052031

.152

.207031

.252

.332031

.352

.457031

.053

.063964

.153

.206964

.253

.333964

.353

.458964

.054

.065937

.154

.210937

.254

.335937

.354

,460937

.055

.087890

.155

.212890

.255

.337890

.355

.462590

.056

.089843

.156

.256

.339643

.356

.464643

.057

.091796

.157

.214643
.216796

.257

.341796

.357

.466796

.060

.093750

.160

.216750

.260

.343750

.360

.466750

.061

.095703

.161

.220703

.261

.345703

.361

.470703

.062

.097656

.162

.222656

.262

.347656

.362

.472656

.063

.099609

.163

.224609

.263

.349609

.363

.474609

.064

.101562

.164

.226562

.264

.351562

.364

.476562

.065

.103515

.165

.226515

.265

.353515

.365

.476515

.066

.105466

.166

.230466

.266

.355466

.366

.460466

.067

.107421

.167

.232421

.267

.357421

.367

.482421

.070

.109375

.170

.234375

.270

.370

.464375

.071

.111326

171

.236328

.271

.359375
.361326

.371

.486328

.072

.113261

.172

.238281

.272

.363261

.372

.488281

.073

.115234

.173

.240234

.273

.365234

.373

.490234

.074

.117167

174

.242167

.274

.367167

.374

.492167

.075

.119140

175

.244140

.275

.375

.494140

.076

.121093

.176

.246093

.276

.077

.123046

.177

.246046

.277

.369140
.371093
.373046

.376
.377

.496093
.496045

.024

C-7

Octal-Decimal Fraction Conversion Table (Cont)
Octal

Decnmal

Octal

Decimal

Octal

Decimal

Octal

Decimal

.oooooo

.000000

.000100

.000244

.000200

.000488

.oooaoo

.000732

.oooooz

.000003

.000101

.000247

.000201

.ooo492

.oooaox

.ooo7as

.oooooz

.000007

.000102

.000251

.000495

.000302

.ooo14o

.oooooa

.000011

.oooxoa

.ooozss

.000202
.ooozoa

.ooo499

.oooaoa

.ooo143

.000004

.000015

.000104

.000259

.000204

.000503

.000019

.000263

.000205

.000501

.ooooos

.000022

.000105
.000106

.000304
.000305

.ooo741

.ooooos

.oonze7

.ooozos

.000511

.ooosoe

.000155

.000001

.000026

.000107

.000210

.000207

.000514

.000307

.ooo759

.ooooxo

.000030

,000110

.000274

.000210

.000518

.000310

.000762

.oooo11

.000034

.oooszz

.000311

.ooo7es

.000033

.000278
.000282

.000211

.000012
.000013

.000111
.000112

.000212

.000526

.ooosxz

.ooo77o

.000041

.000113

.ooozee

.000213

.000530

.000313

.000774

.000014

.000045

.000114

.000239

.000214

.000534

.000314

.ooo17s

.000015

.000049

.000115

.000293

.000537

.000315

.ooo1sz

.000016

.000053

.000116

.000291

.000215
.000216
.000211

.000541

.000316

.ooo7ss

.ooo739

.ooo751

.000011

.000057

.000117

.000301

.000545

.000317

.000020

.000305
.000303
.000312

.000549

.oooazo

.ooo793

.000221

.000553

.000321

.ooo191

.000222

.000556

.oooszz

.oooeox

.oooozs

.oooo72

.000120
.000121
.000122
.000123

.ooozzo

.000022

.000061
.000064
.000063

.000223

.000560

.000323

.oooaos

.ooooz4

.000076

.000316
.oooazo

.000564

.000324

.ooosos

.oooozs

.000568

.000325

.000312

.000572

.000326

.oooaxs

.000320

.000021

gagga

.oooozs

.ooooso
.000083

.000124
.000125
.000126

.000324
.000328

.000224
.000225
.000226

.000021

.000087

.000121

.000331

.000221

.000576

.000321

.000030

.000091

.000335

.000230

.ooos79

.oooaao

.000823

.000031

.ooooss

.000130
.000131

.000339

.000231

.ooosas

.oooaax

.oooez7

.000032

.000099

.ooo132

.000343

.000232

.000587

.000332

.000831

.oooosa

.000102

.000133

.000341

.000233

.000591

.ooosas

.ooooa4

.oooxoe

.000134

.000350

.000234

.000595

.000333
.000334

.000035

.000110

.ooo135

.000354

.ooosss

.000114

.000136

.000358

.ooooa7

.000118

.000137

.000362

.000237

.000606

.000335
.000336
.000337

.000343

.ooooss

.000235
.000236

.oooo4o

.000122

.000140

.000356

.000240

.000610

.oooa4o

.oooes4

.000041

.000125

.000141

.000370

.oooz41

.000614

.000341

.ooossa

.oooo42

.000129

.000142

.000373

.000242

.000617

.000342

.000352

.000043

.000133

.000143

.oooa11

.000243

.000621

.000343

.ooosss

.000044

.000131

.000144

.000331

.000244

.000625

.oooae9

.oooo4s

.000141

.ooo14s

.000335

.000245

.000529

.000344
.oooa4s

.oooo4s

.000144

.000146

.000389

.000246

.ooosaa

.000345

.000877
.000881

.oooess

All”;
‘

.000602

”t

.000846
.oooeso

.ooos73

.oooo47

.000148

.000147

.000392

.000241

.oooea1

.000341

.ooooso

.000152

.000150

.000395

.000250

.ooos4o

.oooaso

.ooosss

.oooosx

.000156

.000151

.000400

.000251

.ooos44

.000351

.000388

.oooosz

.000160

.000152

.000404

.ooozsz

.000643

.000352

.oooesz

.oooosa

.000154

.000153

.000403

.000253

.000652

.000353

.oooase

.oooos4

.000157

.000154

.000411

.000254

.ooosss

.000354

.oooeoo

.ooooss

.000171

.000155

.000415

.ooozss

.oooes9

.oooass

.oooso4

.ooooss

.000175

.oooxss

.000419

.000256

.000663

.000356

.oooeo1

.oooos7

.000179

.000151

.000423

.000257

.oooes7

.ooossw

.000911

.ooooso

.000183

.oooxso

.ooozeo

,ooosvx

.oooaso

.000915

.000261

.ooos1s

.000361

.000919

.oooe19

.000362

.000923

.000682

.000363

.000926

.ooosas

.oooae4

.ooosao

.ooosso

.ooosss

.000934

”In.“

“

‘

.000061

.000186

.000161

.000427
.000431

.000062

.000190

.000162

.000434

.000063

.000194

.oooxaa

.ooooss

.000202

.000163
.000164
.000155

.000438

.oooos4

.000446

.000262
.000263
.000264
.ooozes

.000066

.000205

.000166

.ooo4so

.000265

.000594

.oooass

.oooaaa

.oooos1

.ooozos

.oooxs1

.000453

.ooozsv

.000698

.000357

.000942

.oooo7o

.000213

.ooo17o

.000701

.oooavo

.ooos4s

.000217

.000171

.000271

.ooo7os

.oooa11

.000949

.000172
.000113

.ooo457
.000461
.000465
.ooo4ss
.000473

.000270

.oooo11

.000272
.000273
.oooz74

.ooo7oa

.000372

.onoesa

.ooo713

.000373

.000957

.000111

.ooos74

.000961

.000475
.ooo4so

.oooz1s
.oooz7a

.ooo720

.oooa1s

.ooooss

.ooo124

.000376

.ooosea

.000434

.000211

.ooo1za

.oooa17

.ooos7z

.oooovz

.000221

.000073

.000225

.000074

.000223

.oooovs

.000232

.ooox14
.000115

.oooovs

.000236
.000240

.000115
.000117

.000071

.000442

’glua

“

Anna;
""'e

C-8

ltfi-rw‘flmmmmmmmmwmm~

‘

”:u;

‘

WWMMWWWWWWWWWWMWW

m2,

“SJ WWWWIWWWHWWM

Octal-Decimal Fraction Conversion Table (Cont)

Octal

Decimal

Octal

Decimal

.000400

.000976

.000500

.000401

.000980

.000501

.000402

.000984

.000403
.000404

Octal

Decimal

.001220

.000600

.001224

.000601

.000502

.001223

.000602

.000933

.000503

.001232

.000603

.000991

.000504

.001235

.000504

.000405

.000995

.000505

.001239

.000505

.000406

.000999

.000506

.001243

.000407

.001003

.000507

.001247

.000410

.001007

.000510

.001251

.000610

.001495

.000710

.001739

.000411

.00101c

.000511

.001255

.000611

.001499

.000711

.001743

.000412

.001014

.000512

.001258

.000612

.001502

.000712

.001747

.000413

.001013

.000513

.001262

.000618

.001506

.000713

.001750

.000414

.001022

.000514

.001266

.000614

.001510

.000714

.001754

.000415

.001026

.000515

.001270

.000615

.001514

.000715

.001755

.000416

.000516

.001274

.000616

.001513

.000716

.001762

.000417

.001029
.001033

.000517

.001277

.000617

.001522

.000717

.001766

.000420

.001037

.000520

.001281

.000620

.001525

.000720

.001770

.000421

.000521

.001285

.000621

.001529

.000721

.001773

.000422

.001041
.001045

.000522

.001289

.000622

.001533

.000722

.001777

.000423

.001049

.000523

.001293

.000623

.001537

.000723

.001791

.000424

.001052

.000524

.001296

.000624

.001541

.000724

.001735

.000425

.001056

.000525

.001300

.000625

.001544

.000725

.001759

.000426

.001060

.000526

.001304

.000626

.001548

.000726

.001792

.000427

.001064

.000527

.001308

.000627

.001552

.000727

.001796

.000430

.000530

.00L312

.000530

.001556

.000730

.001500

.000531

.001316

.000631

.001560

.000731

.001504

.000432

.001063
.001011
.001075

.000532

.001319

.000632

.001564

.000732

.001303

.000433

.001079

.000533

.001323

.000633

.001567

.000733

.0013x1

.000434

.001088

.000534

.001327

.000534

.001571

.000734

.001315

.000435

.001087

.000535

.001331

.000635

.00x575

.000735

.001519

.000436

.001091

.000536

.001335

.000636

.001579

.000736

.001523

.000437

.001094

.000537

.001338

.000637

.001588

.000737

.001527

.000440

.001098

.000540

.001342

.000640

.001586

.000740

.001331
.001834

.000431

Octal

Decimal

.001464

.000700

.001703

.001468

.000701

.001712

.001472

.000702

.001716

.001476

.000703

.001720

.001480

.000704

.001724

.001483

.000705

.001728

.000606

.001437

.000706

.001731

.000607

.001491

.000707

.001735

.000441

.001102

.000541

.001346

.000641

.001590

.000741

.000442

.001106

.000542

.001350

.000642

.001594

.000742

.001838

.000443

.001110

.000543

.001354

.000643

.001593

.000743

.001342

.000444

.001113

.000544

.001358

.000644

.001602

.000744

.001545

.000445

.001117

.000545

.001861

‘.000545

.001605

.000745

.001550

.000446

.001121

.000546

.001365

.000646

.001609

.000746

.001853

.000447

.001125

.000547

.001369

.000647

.001613

.000747

.001857

.000450

.001129

.000550

.001373

.000550

.001617

.000750

.001861

.000451

.001132

.000551

.001377

.000651

.001621

.000751

.001865

.000452

.001136

.000552

.001380

.000652

.001625

.000752

.001869

.000453

.001140

.000553

.001384

.000653

.001628

.000753

.001873

.000454

.001x44

.000554

.001388

.000654

.001632

.000754

.001876

.000455

.000555

.001392

.000655

.001636

.000755

.001880

.000456

.001148
.001152

.000556

.001396

.000656

.001640

.000756

,001884
.001888

.000457

.001155

.000557

.001399

.000657

.001644

.000757

.000460

.001159

.000560

.001403

.000660

.001647

.000760

.001392

.000461

.001163

.000561

.001407

.000661

.001651

,000761

.001395

.000462

.001161

.000562

.001411

.000662

.001655

.000762

.001599

.000463

.000563

.001415

.000663

.001659

.000763

.001903

.000464

.001171
.001174

.000564

.001419

000664

.001668

.000764

.001907

.000465

.001178

.000565

.001422

.000665

.001667

.000705

.001911

.000466

.001182

.000566

.001426

.000666

.001670

.000766

.001914

.000467

.001186

.000567

.001430

.000667

.001674

.000767

.001918

.000470

.001190

.000570

.001434

.000670

.001678

.000770

.001922

.000471

.001194
.001197

.000571

.001433

.000671

.001682

.000771

.001925

.000572

.001441

.000672

.001686

.000772

.001930

.000472

.000473

.001201

.000573

.001445

.000673

.001689

.000773

.001934

.000474

.000574

.001449

.000674

.001693

.000774

.001937

.000475

.001205
.001209

.000575

.001453

.000675

.001697

.000775

.001941

.000476

.001213

.000576

.001457

.000676

.001701

.000776

.001945

.000477

.001216

.000577

.001451

.000677

.001705

.000711

.001949

(3-9

mmmmmmmmmmammmmmmmWWW
'

mummnmmmnmmmmm

V
‘

‘

~ WIWWHWWIMWWE;

APPENDIX D

INSTRUCTION SET

appendix contains a complete list of the PDP‘lG-M instructions. The instruction mnemonics and the octal
are given. To facilitate quick reference, the instructions are ordered by class of instruction (basic
classes and optional instructions), rather than by machine code.

This

machine codes

ARITHMETIC GROUP

Octal Machine Code

Mnemonic
>A=O

000

_A=B

001

A=A+1

002

.A=A-1

003

A=A+B

004

A=A~B

005

WA=A/2

012

—~A=AX2

01 3

71-A=B/2

272

-—A

45.

‘

014

A+1lS)
A-1lS)
A+B(S)
A-B(Sl
A/2(S)
AX2I(S)
B/2(S)

015
016

017
020
021
273

,3 =0

022

r3 =A

023

"B=A+1

257

B =A-1

261

~B =A+B

024

A-B

025

43=Al2

265

—

"13 =AX2!

263

3/2

032

D-l

"’

Octal Machine Code

Mnemonic

A+1iS)

260

«B = A-1(S)

262

B = A+B(S)

033

B = A‘B(S)

034

r8 = A/2(S)

266

AX 2(3)

264

~-B

B/2(S)

035

-L

074

"i.

075

“L

LNOT

270

OVF

267

TEST GROUP

Octal Machine Code

Mnemonic
-EXA

036

_..EXB

037

LOGICAL GROUP

Octal Machine Code

Mnemonic

A = ANOT

011

AORB

007

010

AXORB

006

,B = BNOT

031

AORB

027

030

AXORB

026

—

Octal Machine Code

Mnemonic
"A

133

1A = TRU

131

TEL

132

"”TR = 0

250

130

-—TR

—TRU = A

276

«IRL

277

D-2

ummwmummmmsmmmm

CONSTANT GROUP

Mnemonic

Octal Machine Code

“B

C1]

046

047,

“'3

136

137

BOOLEAN OUTPUT GROUP

Mnemonic

Octal Machine Code

~FF1=0

056

¢F1=1

057

rFF2=0

060

rFF2=1

061

~FF3=0

062

»FF3=1

063

PARALLEL l/O GROUP

Mnlemonfic

Octal Machine Code

~A=GH1

041

_3=Gm1

256

~GH1=A

040

GPl1=B

255

COMMAND GROUP

Octal Machine Code

Mnemonlc

--PAGEO

072

JAGE1

073

-.~MUXO

076

‘MUX1

077

HlALT

271

D'3

CONDITIONAL JUMP GROUP (MUXOi

Mnemonic

Octal Machine Code
Into or Within

-GOTO
,

MEMO

MEM1

300

301

IF EXT1,

302

303

IF EXT2,

304

305

IF EXT3,

306

307

vlF EXT4,

310

311

—~-IF EXT5,

312

313

..IF EXT6,

314

315

.IF D2,

316

317

IF DP,

320

321
323

IF DN,

322

~IF OVF,

324

325

”IF A<1>,

326

327

“‘I F A<3>,

330

331

IF A<5>,

332

333

“IF A<7>,

334

335

~AIF A<9>,

336

337

“IF A<11>,

340

341

‘IF A<13>,

342

343

IF A<15>,

344

345

”IF FF1,

346

347

-IF FF2,

350

351

IF FF3,

352

353

~--lF FF4,

354

355

“1F FF5,

356

357

'1F FF6,

360

361

x-IF KF1,

362

363

~IF PF1,

364

365

JF KF2,

366

367

_JF PF2,

370

371

«IF CLK,

372

373

M
1

These instructions are implemented only if Boolean output flag option

KFL16 is installed.

These

instructions

serial

interface option

are

implemented only

are

implemented only if serial interface 2 option

DC16-A is installed.

These instructions

’

DC16-A is installed.

0-4

waiiii-iiiiimhllfllflllijflliflmmmmmii

‘1

1‘

“Wu

‘

“WWWmummmmmuneaiwmmmmmmmmfimmmmlitmmmmmmwmmmmmmmmmmmmmimmmmwwmmmsagmmmmwwr

SUBROUTINE GROUP

Octal Machine Code

Mnemonic

Into or Within

MEM1

MEMO
_CALL

374

(RETURN

376

375
_

376

SCRATCHPAD REGISTER OPTION M81643

Octal Machine Code

Mnemonic

A=SP1

140

-A=SP2

141

A=SP3

142

~A=SP4

143

~A=SP5

144

A=SP6

145

A=SP7

146

A=SP8

147

A=SP9

150

~A=SP10

151

--A=SP11

152

A==SP12

153

A==SP13

154

A==SP14

155

-A==SP15

156

A==SP16

157

‘

-SP1=A

160

161

SP3

162

“SP4

163

”5.5195

164

“SP6

165

.,.SP'7

166

.S%=A

167

170

ASP?
,

SP9

rSNO=A

171

.SP11=A

172

.SN2=A

173

174

_sm4=A

175

.5m5=A

176

JSP16=I\

177

A=SP1";

200

AA=SP18

201

A=SP19

202

_...SP13

D-5

Octal Machine Code

Mnemonic
—»A = SP20

203

SP21

204

SP22

205

A = SP23

206

A = SP24

207

SP25

210

SP26

211

SP27

212

SP28

213

SP29

214

SP30

215

SP31

216

SP32

217

~‘SP1 7

220

—SP18

221

~SP19

222

,.SP20

223

—SP21

224

"*SP22

225

«SP23

226

SP24

227

SP25

230

SP26

231

SP27

232

SP28

233

«VSP29

234

SP30

235

,.SP31

236

".SP32

237

CONSTANT GENERATOR OPTION MR16—D

Octal Machine Code

Mnemonic

-B=K1

100

,.B=K2

101

B=K3

102

B=K4

103

rB=K5

104

.B=K6

105

B=K7

106

B=K8

107

B=K9

110

-B=K10

111

—B=K11

112

-B=K12

113

B=K13

114

~~nmmmnwmmnmmmmmm1j

‘_

‘

w
1

wm WWW,mm,
mmmmw
7‘

‘

Octal Machine Code

Mnemonic

115

v8 = K14
”B

K15

116

«*3

K16

117

—‘B = K17

120

K18

121

’8

«B = K19

122

--»B = K20

123

K21

124

K22

125

B = K23

126

"B = K24

127

DATA PROM OPTION MR16—E/F

Mnemonic

Octal Machine Code

-RMAR

134

—-RMAR

246

A = ROM

135

«B = ROM

247

DATA READ/WRITE MEMORY OPTION MlS16-D/E

Octal Machine Code

Mnemonic
MAR1

240

‘MAR2

243

“MEMl

241

.MEMZ

244

“A

MEMlI

242

MEM2

245

PARALLEL l/O OPTION DB16-A

Octal Machine Code

Mnemonic

GPI2

043

GPl3

045

«GPIZ

042

—GPl3

044

0-7

PDP-11 PERIPHERAL INTERFACE OPTION DA16-F

Mnemonic
—FF1

Octal Machine Code

056

—GPl1

040

,GPll

255

ADATO

275

,DATl

274

SERIAL l/O OPTION DC16-A

Mnemonic

Octal Machine Code

——TAPE1

052

r-lF KF1,

See Conditional Jump Group

\Sl1

051

050

See Conditional Jump Group

r——lF PF1,
.CTAPEZ

055

lF KF2,
«A

~—Sl2

Sl2

am,

See Conditional Jump Group
054

053

~—-lF PF2,

See Conditional Jump Group

BOOLEAN OUTPUT OPTION KFL16

Mnemonic

‘

Octal Machine Code

F F4

FF4

065

FF5

066

064

FF5 = 1

067

FF6

070

FF6

071

D-8

r«mum.maumrmmmmmmwmammim

‘

BOOLEAN INPUT MULTIPLEXER (MUX1) OPTION PCS16-D

Mnemonic

Octal Machine Code
Into or Within
MEMO

MEM1

‘"GOTO

300

301

——IF A<0>,

302

303

4F A<2>~,

304

305

._JF A<4>,

306

307

«4F A<6>,

310

311

«IF A<8>,

312

313

~11: A<10>,

314

315

—«IF A<12>,

316

317

AF A<14:>,

320

321

"IF B<o>,

322

323

W11 B<15>,

324

325

”IF EXT7,

326

327

wIIF EXT8,

330

331

«~11: EXT9,

332

333

I-F EXT10,

334

335

IF EXT11,

336

337

.VHF EXT12,

340

341

.IF EXT13,

342

343

IF EXT14,

344

345

IF EXT'15,

346

347

I-F EXT'16,

350

351

IF EXT17,

352

353

IF EXT18,

354

355

“IF EXT19,

356

357

“1F EXT20,

360

361

IF EXT21,

362

363

«IF EXT22,

364

365

-1F L,

366

367

JFPWOK

370

371

—-

[)9

‘-1%:saii!Iiuuuslnhwiwmmiwzwwmmmmmw

3‘

“:1

gimmulfl“Wmmmmraumw
H

WWWMMMW‘WMWMWIWIW
‘

APPENDIX E

PDP16-M MACHINE CODES

This is

list, in octal machine code order, of all PDP16-M machine instructions. The basic PDP16-M hardware

consists of:

Quantity

Name

Model No.

Module No.

Slot

KBS16—A

Bus Control

M7332

A82

KAC16

GP’A Control Unit

M7300

AB11

KAR16

GP’A Register Unit

M7301

AB10

MR16-A

Four Word Constants Generator

M7307

A85

MS16-A

Transfer Register

M7305

AB9

DB16-A

General Purpose Interface 1

M7311

A812

PCSIG-A

PCS Control

M7336

AB20

PC816-B

P’CS Control PROM

M7327

C16

PCS16-C

Evoke Decoders (0, 1, 2, 5)

M7328

CD3, 4, 5, 8

PCSI6-D

MUXO

M7329

A818

KFL16

Flags (1, 2, 3)

M7306

Instruction

Machine Code

Time

(Octal)

(usec)

000

2.4

001

2.4

002

2.4

A = A+1

003

2.4

A--1

004

2.4

A-I-El

005

2.4

A = A--El

006

2.4

A = AXORB

007

2.4

AORB

010

2.4

A13

011

2.4

ANOT

012

2.4

A/ 2

013

2.4

AX2

014

2.4

A+1ISI
A--1(S)

015

Evoke

Decoder No.

Channel Decoder

E-1

Option

Slot

Time

Instruction

Evoke

Decoder No.

(Octal)

(usecI

016

2.4

017

2.4

020

2.4

021

2.4

022

2.4

023

2.4

024

2.4

025

2.4

026

2.4

027

2.4

030

Evoke

Option

Slot

Channel Decoder

A—B(S)

A/2(S)

AX 2(3)

B = 0

A+B

A—B

AXORB

AORB

2.4

BNOT

6/2

A+B(S)

A-B(S)

B/2(S)

A‘

GP|1

DBIB-A

A613

GP|2

DB16-A

A613

DB16-A

A614

0616A

A614

A+B(S)

fi
'

031

2.4

032

2.4

033

2.4

034

2.4

035

2.4

036

2.4

‘66

037

2.4

040

2.2

GP|1

041

2.0

042

2.2

GP|2

043

2.0

044

2.2

GPI3

045

2.0

GP|3

046

2.4

047

2.4

050

3.5

311

DC16-A

A616

051

2.1

A=SI1

DC16-A

A616

052

1.7

TAPEI

0016A

A616

053

3.5

512

DC16-A

A617

054

2.1

A=Sl2

DC16-A

A617

055

1.7

TAPE2

DC16—A

A617

056

1.8

FFI

057

1.8

FF1

060

1.8

FF2

061

1.8

FF2

062

1.8

FF3

063

1.8

FF3

064

1.8

FF4=0

KLF16

065

1.8

FF4=1

KLF16

066

1.8

FF5=0

KLF16

067

1.8

FF5=1

KLF16

070

1.8

FF6=0

KLF16

071

1.8

FF6=1

KLF16

E-2

ir-fizaéliflhfiiiifiififimwfii!fiiéifiifiiflifififififlwimfimgfifimfli;

1M...

Time

(Octal)

(usec)

072

1.8

073

Instruction

PAGEO

1.8

Evoke

Decoder No.

Channel Decoder

PAGE1

Option

Slot

More Than

CD16

2 PCS16-B's

CD17

More Than

CD16

2 PCS16-B's

CD17

074

1.8

075

1.8

076

1.8

MUXO

077

1.8

MUX1

PCS16-D

A819

100

2.4

B=K1

MR16-D

A88

101

2.4

B=K2

MR16-D

A88

102

2.4

B=K3

MR16-D

A88

103

2.4

B=K4

MR16-D

A88

104

2.4

B=K5

105

2.4

B=K6

106

2.4

B=K7

107

2.4

B=K8

110

2.4

B=K9

111

2.4

B=K1O

112

2.4

B=K1‘I

113

2.4

B=K12

114

2.4

115

2.4

B=K14

116

2.4

B=K15

117

2.4

8=K16

120

2.4

B=K1?

121

2.4

B=K18

122

2.4

B=K19

123

2.4

B=K20

124

2.4

E1=K21

125

2.4

B=K22

8=K13
'

126

2.4

B=K23

127

2.4

B=K24

130

2.3

TR=A

131

2.1

A=TRU

132

2.1

A=TRL

133

2.1

A=TR

134

2.2

RMAR

135

2.3

136

2.4

B=C3

137

2.4

8=C4

140

2.2

A=SP1

141

2.2

A=SPZ

142

2.2

A=SF’3

143

2.2

A=SP4

ROM

NMNMNNNMNNNMNMNMNNNMN-A4—0—3

MR16-D

A88

MR16-D

A88

MR16-D

A88

MR16-D

A88

MR16-D

A88

MR16-D

A88

MR16-D

A88

MR16-D

A88

MR16-D

A88

MR16-D

A88

MR16-D

A88

MR16-D

A88

MR16-D

A88

MR16-D

A88

MR16-D

A88

MR16~D

A88

MR16-D

A88

MR16-D

A88

MR16-D

A88

MR16-D

A88

PCS16-8 and
DB16-A

ABCD15

PCS16-B and

QWUM
E-3

DB16-A

ABCD15

MS16-C

A84

MS16-C

A84

MS16-C

A84

MS16-C

A84

Evoke.

Evoke

Decoder No.

Channel Decoder

@
Option

Slot

MS16-C

AB4

MS16-C

A34

M816-C

A34

M816-C

A34

MS16-C

A34

A=SP10

MS16—C

AB4

2.2

A =8P11

MS16-C

A34

153

2.2

SP12

M816-C

A34

154

2.2

SP13

MS16-C

A34

155

2.2

A = SP14

M816-C

AB4

156

2.2

SP15

MS16—C

AB4

157

2.2

A = SP16

MS16—C

AB4

160

2.6

SP1

M816-C

A34

161

2.6

SP2 = A

MS16—C

A34

162

2.6

SP3

M816-C

A34

163

2.6

SP4

M816—C

AB4

164

2.6

SP5

MS16-C

A34

165

2.6

SP6

MS16-C

A34

166

2.6

SP7

M816-C

A34

167

2.6

SP8

M816—C

A34

170

2.6

SP9

M816-C

AB4

171

2.6

SP10

M816-C

AB4

172

2.6

A34

173

2.6

174

Machine Code

Time

(Octal)

(psec)

144

2.2

SP5

145

2.2

SP6

146

2.2

A = SP7

147

2.2

SP8

150

2.2

SP9

151

2.2

152

SP12

MS16-C

SP13

M816-C

A34

2.6

SP13

MS16-C

A34

175

2.6

SP14

MS16-C

A34

176

2.6

SP15

MS16-C

A34

177

2.6

SP16

M816-C

A34

200

2.2

SP17

M816-C

A33

201

2.2

SP18

MS16-C

A33

202

2.2

A = SP19

M816—C

A33

203

2.2

SP20

M816-C

A33

204

2.2

SP21

MS16-C

A33

205

2.2

8P22

MS16-C

AB3

206

2.2

SP23

MS16-C

AB3

207

2.2

SP24

MS16-C

AB3

210

2.2

SP25

M816-C

A33

211

2.2

A = SP26

M816—C

A33

212

2.2

8P27

MS16-C

AB3

213

2.2

A = SP28

M816-C

A33

214

2.2

SP29

MS16-C

AB3

215

2.2

SP30

MS16-C

AB3

2.2

A = SP31

1'6

MS16—C

A83

217

2.2

A = SP32

M816-C

A33

220

2.6

SP17 = A

MS16-C

A33

221

2.6

SP18

MS16-C

A33

”W“?

m
”if
‘

216

E-4

? Evoke

Evoke

Decoder No.

Channel Decoder

Machine Code

Time

(Octal)

(usec)

222

2.6

SP19

MS16-C

A83

223

2.6

SP20

MS16-C

A83

224

2.6

SP21

MS16-C

A83

225

2.6

SP22

MS16-C

A83

226

2.6

SP23

MS16-C

A83

227

2.6

SP24

MS16-C

A83

230

2.6

SP25

MS16-C

A83

231

2.6

SP26

MS16-C

A83

232

2.6

SP27

MS16-C

A83

233

2.6

SP28

COOJ

MS16-C

A83

234

2.6

SP29

MS16-C

A83

235

2.6

SP30

MS16-C

A83

236

2.6

SP31

MS16-C

A83

237

2.6

SP32

MS16-C

A83

240

2.3

MAR1

241

3.6

MEM1

242

3.9

A = MEM1

243

2.3

MA82

244

3.6

MEM2

245

3.9

246

2.2

RMAFK

247

2.3

8=ROM

250

2.0

251

2.1

B = SH

252

3.5

253

2.1

254

MEM2

mmmmbhbbhhb-hcfib mawaoum-h
ww

(J1

Option

Slot

MS16-D or E

A86

MS16-D or E

A86

MS16-D or E

A86

MS16-D or E

A87

MS16-D or E

A87

MS16-D or E

A87

PCS16-B and
DB16-A

ABCD15

PCS16-B and
DB16-A

ABCD15

DC16-A

A816

DC16-A

A816

B = 812

DC16-A

A817

3.5

812

DC16-A

A817

255

2.2

GP|1

256

2.0

Gl’l1

257

2.4

A+1

260

2.4

A+1(S)

261

2.4

B = A--1

262

2.4

263

2.4

B = AX2

264

2.4

265

2.4

B =

AX2(S)
A/2

266

2.4

A/2(S)

267

1.8

OVIF

270

1.8

LNOT

B
=

A-1(S)

HALT

271
272

2.4

273

2.4

8/2

B/2(S)

274

DATI

275

DATO

276

2.3

TRU

277

2.3

TRL

mmmmmmmmmwmmm

15
16
17
2O
21

22
23

24
25
26
27

30
31
32

33
34
35

36
37

E-5

CONDITIONAL JUMP INSTRUCTIONS (INPUT MULTIPLEXERI
Machine Code

Time

(Octall*

(usecl

Instruction

Multiplexer

No.“

Channel

False

True

301

2.0

3.2

GOTO

302

303

2.0

3.2

IF EXT1,

304

305

2.0

3.2

IF EXT2,

306

307

2.0

3.2

lF EXT3,

310

311

2.0

3.2

lF EXT4,

31:2

313

2.0

3.2

IF EXT5,

314

315

2.0

3.2

lF EXTB,

316

317

2.0

3.2

IF DZ,

320

321

2.0

3.2

IF DP,

322

323

2.0

3.2

IF DN,

324

325

2.0

3.2

IF OVF,

326

327

2.0

3.2

IF A<1>,

330

331

2.0

3.2

IF A<3>,

332

333

2.0

3.2

IF A<5>,

334

335

2.0

3.2

IF A<7>,

336

337

2.0

3.2

IF A<9>,

340

341

2.0

3.2

IF A<11>,

342

343

2.0

3.2

IF A<13>,

344

345

2.0

3.2

IF A<15>,

346

347

2.0

3.2

IF FF1

350

351

2.0

3.2

IF FF2

MEMO

MEM1

300

352

353

2.0

3.2

IF FF3

354

355

2.0

3.2

IF FF4

356

357

2.0

3.2

IF FF5

360

361

2.0

3.2

IF FF6

362

363

2.0

3.2

IF KF1

364

365

2.0

3.2

IF PF1

366

367

2.0

3.2

IF KF2

370

371

2.0

3.2

IF PF2

372

373

2.0

3.2

IF CLK

300

301

2.0

3.2

GOTO

302

303

2.0

3.2

IF A<0>

304

305

2.0

3.2

IF A<2>

306

307

2.0

3.2

IF A<4>

310

311

2.0

3.2

IF A<6>

312

313

2.0

3.2

IF A<8>

314

315

2.0

3.2

IF A<10>

316

317

2.0

3.2

IF A<12>

320

321

2.0

3.2

IF A<14>

322

323

2.0

3.2

IF B<0>

324

325

2.0

3.2

IF B<15>

326

327

2.0

3.2

IF EXT7

330

331

2.0

3.2

IF EXT8

332

333

2.0

3.2

IF EXTQ

334

335

2.0

3.2

IF EXT10

:336

337

2.0

3.2

IF EXT11

AA]

m
'

E-6

~HW¥fiiflflllilllléilliWWflHliiiiiflm§mn 11‘:

,11‘111111‘11‘51114‘11‘»

‘uw‘XXlul“131131

CONDITIONAL JUMP INSTRUCTIONS (INPUT MULTIPLEXERI (Cont)
Time

Machine Code

(usec)

I()ctall*

Instruction

Multiplexer

No.H

Channel

False

True

2.0

IF EXT12

2.0

31.2

IF EXT13

2.0

31.2

IF EXT14

347

2.0

3.2

IF EXT15

350

351

2.0

3.2

IF EXT16

352

353

2.0

3.2

IF EXT17

354

355

2.0

3.2

IF EXT18

356

357

2.0

3.2

IF EXT19

360

361

2.0

3.2

IF EXT20

362

363

2.0

3.2

IF EXT21

364

365

2.0

3.2

IF EXT22

366

367

2.0

3.2

IF L

370

371

2.0

3.2

IF PWOK

372

373

2.0

3.2

Not used

MEMO

MEM1

340

341

342

343

344

345

346

‘.
I

d—J—l-fi—l-fid—I-fi—A—I—I

24
25
26
27
30
31
32
33
34

C odes are given for jumps into or within Memory 1 and into or within Memory 2. The least significant bit of the machine code is
the M (memory) bit.

“Multiplexer 1 (PCSi6-D) is optional and resides in slot A319 of the logic assembly. The MUXO and MUX1 commands are used to
select one or the other multiplexer.

SUBROUTINE INSTRUCTIONS
Machine Code

Time

(Octal)

(,usec)

374

3.2

CALL

375

3.2

CALL

376

3.2

EXIT

I nstruction

E~7

—

Jump to a Subroutine in Memory 0
Jump to a Subroutine in Memory 1
Return from a Subroutine

~
7

mammamsssaaummaa

APPENDIX F

DEFINITION TAPE LISTING

INIT
DI

000

001

002

003

004

005

006

007

010

01 1

012

013

A =

A+1ISI
A-1(S)
A+BISI
A-B(SI
A/2(S)
AX2(S)

021

022

023

A+B

024

A-B

025
026

014

015

016

017

020

AXORB

AORB

027

030

8 = NOTB

031

3/2

032

A+B(S)
A—B(S)
B/2(S)

033

B =

034

035

036

037

GP”

040

GPH

041

GPI2

042

A= GPI2

043

GPI3= A

044

A= GPI3

045

(:1

046

F-1

B=C2

047

SH==A

050

A=SH

051

TAPEI

EN2=A

053

IA=SQ

054

TAPE2

055

FF1=0

056

FF1=1

057

FF2=0

060

FF2=1

061

FF3=0

062

FF3=1

063

FF4=0

064

FF4=1

065

FF5=0

066

FF5=1

067

FF6=0

070

FF6=1

071

PAGEO

072

PAGE1

073

L=0

074

075

MUXO

076

MUX1

077

B=K1

100

B=K2

101

B=K3

102

B=K4

103

B=K5

104

B=K6

105

B=K7

106

B=K8

107

B=K9

110

B=K10

111

B=KII

112

B=K12

113

B=K13

114

B=K14

115

B=K15

116

B=K16

117

B=K17

120

B=K18

121

B=K19

122

B=K20

123

B=K21

124

B=K22

125

B=K23

126

B=K24

127

TR=A

130

A=TRU

131

A=TRL

132

A=TR

133

F-2

wwwwmmmmmmmmumu;

134

A=ROM

135

B=C3

136

B =C4

137

A=SP1

140

A=SP2

141

A=SP3

142

A=SP4

143

A=SP5

144

A=SP6

145

A=SP7

146

A=SP8

147

A=SP9

150

A=SP10

151

A =SP11

152

A=SP12

153

A =SP13

154

A=SP14

155

A =SP15

156

A=SP16

157

SP1 =A

160

SP2=A

161

SP3=A

162

SP4=A

163

SP5=A

164

SP6=A

165

SP7 =A

166

SP8=A

167

SP9=A

170

SP10= A

171

SP11=A

172

173

SP13=A

174

SP14=A

175

SP15=A

176

SP16=A

177

A=SP17

200

A =SP18

201

A=SP19

202

A=SP20

203

A=SP21

204

A=SP22

205

A=SP23

206

A=SP24

207

A=SP25

210

A =SP26

211

A=SP27

212

A =SP’28

213

A=SP29

214

A =sp3o

215

A=SP31

216

A=SF'32

217

5917 ==A

220

RMA

SP12

F-3

SP18 = A

221

SP19

222

SP20

223

$921

224

SP22 = A

225

sp23

226

SP24

227

31925

230

SP26 = A

231

232

SP28 = A

233

234

SP30 = A

sp27
3929

235

3931

236

SP32

237

24o

MEM1 = A

241

MEM1

242

243

MEM2 = A

244

MEM2

245

RMAR = B

246

ROM

247

250

MAR1
A

MAR2
A

511

251

252

512

253

254

255

GPH

256

B = A+1

257

312

GPI1
B

A+1(S)

260

A—1

261

A—1(S)

262

AX2

263

264

AX2(S)
A/2

265

B = A/2(S)

266

ov1=

267

LNOT

27o

271

3/2

272

B/2(S)

273

DATI

274

DATO

275

HALT
A

276

TRL = A

277

EXT1

EXT2

EXT3

EXT4

EXT5

EXT6

TRU

M5,,
‘

«Wmmifimfiuawwwmmumulwm

OVF

A<12>

A<3>

A<5>

A<7>

A<9>

A<1 1>

A<13>

A<15>

FF1

FF2

FF3

FF4

FF5

FF6

KF1

PF1

KF2

PF2

CLK

A<Ol>

A<2>

A<4>

A<6>

A<8>

A<10>

A<12>

A<1|4>

B<O>

B<15>

5x17

EXTB

EXTQ

EXT10

EXT1 1

EXT12

EXT13

EXT14

EXT15

EXT16

EXT17

EXT18

EXT19

EXT20

EX‘T21

EXT22

PWOK

EXT23

FIX

/
PAUSE

F-5

wamsmmmummmmmmmfl“

APPENDIX G
SIGNAL LISTINGS

Alphabetic signal listings with associated pin assignments of PDP16-M l/O and bus signals and PDP-11 l/O signals are
contained in this Appendix.

Table 6-1

P’DP16—M I/O Slot Pin Assignments

(By Signal Name)
Slot

AUTO RUN

D01

S1/U1

CONTINUE

C19

EXT1

C19

EXT2

C19

EXT3

C19

EXT4

C19

EXT5

C19

EXT6

C19

EXT7

C19

EXT8

C19

EXT9

C19

EXT10

C19

EXT11

C19

Signal

EXT12

C19

EXT13

C19

EX'T14

C19

EX‘T15

C19

EXT16

C19

EXT17

C19

EXT18

C19

EXT19

C19

EXT20

C19

EXT21

C19

EXT22

C19

FF1

C19

FF1

D19

FF2

C19

FF2

C20

FF3

C19

G-1

Table 6-1 (Cont)
PDP16~M I/O Slot Pin Assignments

(By Signal Name)
Slot

Signal

FF3

D20

FF4

C19

FF5

C19

FF6

C19

GPI1

D00

D19

GPI1

D01

D19

GPI1

D02

D19

GPI1

D03

D19

GPI1

D04

D19

GPI1

005

D19

J2
K2

GPI1

D06

D19

GPI1

D07

D19

GPI1

D08

D19

GPI1

D09

D19

GPI1

D10

D19

GPI1

D11

D19

GPI1

D12

D19

GPI1

D13

D19

GPI1

D14

D19

GPI1

D15

D19

GPI1

FF1

D19

GPI1

l00

D19

GPI1

I01

D19

GPI1

I02

D19

GPI1

|03

D19

GPI1

l04

D19

GPI1

I05

D19

GPI1

I06

D19

GPI1

I07

019

GPI1

|08

D19

GPI1

109

D19

GPI1

I10

D19

GPI1

I11

D19

GPI1

I12

D19

M
‘

GPI1

I13

D19

GPI1

I14

D19

GPI1

I15

D19

GPI2

D00

C20

GPI2

D01

C20

GP12

D02

C20

GPI2

D03

C20

GPI2

D04

C20

GPI2

D05

C20

GPI2

D06

C20

GPI2

D07

C20

GPI2

D08

020

6-2

I;éwmammwmmwiummmm”

3 III;

__,

‘

Table 6-1 (Cont)
PDP16—M 1/0 S1ot Pin Assignments

(By Signal Name)
Slot

Signal

GPI2

D09

C20

GPI2

D10

020

GP12

D11

C20

GP12

D12

C20

GPI2

D13

C20

GPI2

D14

C20

GPI2

D15

C20

GPI2

FF2

C20

GP12

100

C20

GPI2

101

C20

GP12

102

C20

GPI2

103

C20

GP12

104

C20

GP|2

105

C20

GPI2

106

C20

GP12

107

C20

GP12

108

C20

GPI2

109

020

C20

GP|2

I10

GP12

I11

GP12

C20

112

C20

GP12

113

C20

GPI2

114

C20

GPIIZ

115

C20

GP13

D00

D20

GP13

001

D20

GP13

D02

D20

GP13

D03

D20

GP13

D04

D20

GP13

D05

D20

GP13

D06

D20

GP13

D07

D20

GP13

D08

D20

GP13

D09

D20

GP13

D10

D20

GP13

D11

GP13

D20

D12

D20

GP13

D13

D20

GP13

D14

D20

GP13

D15

D20

GP13

FF3

D20

GP13

100

D20

GP13

101

D20

GP13

102

D20

GP13

103

D20

GP13

104

D20

G-3

Table 6-1 (Cont)

PDP16-M I/O Slot Pin Assignments

(By Signal Name)
Slot

Signal

GPI3

I05

020

GPI3

I06

D20

GP|3

I07

D20

GPI3

I08

D20

GPI3

I09

D20

GPI3

I10

020

GPI3

I11

D20

GPI3

I12

D20

GPI3

I13

D20

GPI3

I14

D20

GPI3

I15

D20

GROUND

C19

MSYN

C19

3”

C19

SI1

019

Sl2

C19

SI2

C19

SSYN

TabIeG-Z
PDP16-M RTM Data Bus Pin Assignments

(By Signal Name)
Signal

(Slots A801
DATA BIT 00

—

AB17I

AA1

DATA BIT 01

AB1

DATA BIT 02

AC1

DATA BIT O3

AD1

DATA BIT 04

AE1

DATA BIT 05

AF1

DATA BIT 06

AH1

DATA BIT 07

AJ1

DATA BIT 08

AK1

.........

DATA BIT 09

AL1

DATA BIT 10

AM1

DATA BIT 11

AN1

DATA BIT 12

AP1

DATA BIT 13

AFl1

DATA BIT 14

AS1

DATA BIT 15

AU1

DATA ACCEPT

BA1

DATA READY

BB1

DONE

BCi

OVERFLOW

BD1

POWER CLEAR

BE1

G-4

‘

FWWWWIWWWWW

Table 6-3
PDP-11 UNIBUS Pin Assignments

(By Signal Name)
Signal

A00 L

BH2

006 L

AF1

A01 L

BH1

D07 L

AH2

A02 L

BJ2

D08 L

AH1

A03 L

8.11

009 L

AJ2

A04 L

BK2

D10 L

AJ1

A05 L

BK1

D11 L

AK2

A06 L

BL2

D12 L

AK1

A07 L

BL1

D13 L

AL2

A08 L

BM2

D14 L

AL1

A09 L

BM1

D15 L

AM2

A10 L

BN2

GROUND

A32

A11 L

BN1

GROUND

AC2

A12 L

BP2

GROUND

AN1

A13 L

BP1

GROUND

AP1

A14 L

BR2

GROUND

AR1

A15 L

BR1

GROUND

A81

A16 L

BS2

GROUND

AT1

A17 L

BS1

GROUND

AV2

ACLO L

BF1

GROUND

BB2

BBSY L

AP2

GROUND

BC2

364 H

BE2

GROUND

BD1

865 H

BB1

GROUND

BE1

866 H

BA1

GROUND

BT1

867 H

AV1

GROUND

BV2

3R4 L

802

INIT L

AA1
AB1

Signa1

BR5 L

BC1

INTR L

8R6 L

AU2

MSYN L

BV1

BR7 L

AT2

NPG H

AU1

CO L

BU2

NPR L

A82

C1 L

BT2

PA L

AM1

DOO L

AC1

PB L

AN2

D01 L

AD2
AD1

+5V*
+5V*

AA2

002 L
003 L

AE2

SACK L

AR2

D04 L

AE1

DCLO L

BF2

D05 L

AF2

SSYN L

BU1

'+5V is wired to these pins to supply power to the bus terminator only.

+5V should never be connected via the UNIIBUS between system units.

G-5

BA2

«(-«fi

r‘maximummmmwnnmmWWFWWWWW

‘

APPENDIX H

USER OPTIONS

What can a potential user do and expect in terms of PDP16-M support? This depends largely on how many machines

implement. Since program assembly, program and hardware interface debugging, as well as PROM
a PDP-8/E, the additional cost for the utility PDP-8/E computer must be
loading,
considered. The small user would not: necessarily be able to justify this additional cost. Therefore, Digital Equipment
Corporation offers a service to load the PROMs for the small user at a nominal cost. However, the larger user,
whether an OEM or an end user, would benefit considerably by purchasing a PDP-8/E and the MR16—SL Utility
Interface Option. Although many PDP--8/ E configurations, ranging in price from $5,000 to $50,000 are available, the
PDP16—M program development and utility requirements are satisfied completely with the least expensive
configuration. Having a PDP-8/E with the MR16—SL option equips the user to do his own program development,
debugging, and loading, thereby saving the user time and money, and at the same time exposes the user to
state-of-the-art process control and computer techniques.
a user

wishes to
must

be done with the aid of

'5‘

;
.A

H~1

READER’S COMMENTS

PDP-16M USERS GUIDE

DEC-l 6-lMUGA-A-D

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